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swiftshader / SwiftShader / 1aca23075ab7e2ddfd03c57782afa7c48c2d0354 / . / src / IceInstX8632.def
blob: 3129dad30f527a07a7925f7984728f7292f9020e [file] [log] [blame]
Jim Stichnoth5bc2b1d2014-05-22 13:38:48 -0700[diff] [blame]1//===- subzero/src/IceInstX8632.def - X-macros for x86-32 insts -*- C++ -*-===//
2//
3// The Subzero Code Generator
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines properties of lowered x86-32 instructions in the
11// form of x-macros.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef SUBZERO_SRC_ICEINSTX8632_DEF
16#define SUBZERO_SRC_ICEINSTX8632_DEF
17
Jan Voung95598992014-07-09 09:54:25 -0700[diff] [blame]18// NOTE: esp is not considered isInt, to avoid register allocating it.
Jan Voungbd385e42014-09-18 18:18:10 -0700[diff] [blame]19#define REGX8632_GPR_TABLE \
20 /* val, encode, name, name16, name8, scratch, preserved, stackptr, \
Jim Stichnoth5bc2b1d2014-05-22 13:38:48 -0700[diff] [blame]21 frameptr, isI8, isInt, isFP */ \
Jim Stichnoth728c1d42015-07-15 09:00:07 -0700[diff] [blame]22 X(Reg_eax, 0, "eax", "ax", "al", 1, 0, 0, 0, 1, 1, 0) \
23 X(Reg_ecx, 1, "ecx", "cx", "cl", 1, 0, 0, 0, 1, 1, 0) \
24 X(Reg_edx, 2, "edx", "dx", "dl", 1, 0, 0, 0, 1, 1, 0) \
25 X(Reg_ebx, 3, "ebx", "bx", "bl", 0, 1, 0, 0, 1, 1, 0) \
26 X(Reg_esp, 4, "esp", "sp", "" , 0, 0, 1, 0, 0, 0, 0) \
27 X(Reg_ebp, 5, "ebp", "bp", "" , 0, 1, 0, 1, 0, 1, 0) \
28 X(Reg_esi, 6, "esi", "si", "" , 0, 1, 0, 0, 0, 1, 0) \
29 X(Reg_edi, 7, "edi", "di", "" , 0, 1, 0, 0, 0, 1, 0)
Jan Voungbd385e42014-09-18 18:18:10 -0700[diff] [blame]30
31#define REGX8632_XMM_TABLE \
Jim Stichnoth728c1d42015-07-15 09:00:07 -0700[diff] [blame]32 X(Reg_xmm0, 0, "xmm0", "" , "" , 1, 0, 0, 0, 0, 0, 1) \
33 X(Reg_xmm1, 1, "xmm1", "" , "" , 1, 0, 0, 0, 0, 0, 1) \
34 X(Reg_xmm2, 2, "xmm2", "" , "" , 1, 0, 0, 0, 0, 0, 1) \
35 X(Reg_xmm3, 3, "xmm3", "" , "" , 1, 0, 0, 0, 0, 0, 1) \
36 X(Reg_xmm4, 4, "xmm4", "" , "" , 1, 0, 0, 0, 0, 0, 1) \
37 X(Reg_xmm5, 5, "xmm5", "" , "" , 1, 0, 0, 0, 0, 0, 1) \
38 X(Reg_xmm6, 6, "xmm6", "" , "" , 1, 0, 0, 0, 0, 0, 1) \
39 X(Reg_xmm7, 7, "xmm7", "" , "" , 1, 0, 0, 0, 0, 0, 1) \
Jan Voungbd385e42014-09-18 18:18:10 -0700[diff] [blame]40//#define X(val, encode, name, name16, name8, scratch, preserved, stackptr,
Jim Stichnoth5bc2b1d2014-05-22 13:38:48 -0700[diff] [blame]41// frameptr, isI8, isInt, isFP)
42
Jan Voungbd385e42014-09-18 18:18:10 -0700[diff] [blame]43// We also provide a combined table, so that there is a namespace where
44// all of the registers are considered and have distinct numberings.
45// This is in contrast to the above, where the "encode" is based on how
46// the register numbers will be encoded in binaries and values can overlap.
47#define REGX8632_TABLE \
48 /* val, encode, name, name16, name8, scratch, preserved, stackptr, \
49 frameptr, isI8, isInt, isFP */ \
50 REGX8632_GPR_TABLE \
Jan Voungbd385e42014-09-18 18:18:10 -0700[diff] [blame]51 REGX8632_XMM_TABLE
52//#define X(val, encode, name, name16, name8, scratch, preserved, stackptr,
53// frameptr, isI8, isInt, isFP)
54
55#define REGX8632_TABLE_BOUNDS \
56 /* val, init */ \
57 X(Reg_GPR_First, = Reg_eax) \
58 X(Reg_GPR_Last, = Reg_edi) \
59 X(Reg_XMM_First, = Reg_xmm0) \
60 X(Reg_XMM_Last, = Reg_xmm7) \
61//define X(val, init)
62
63// We also need the encodings for the Byte registers (other info overlaps
64// what is in the REGX8632_GPR_TABLE).
65#define REGX8632_BYTEREG_TABLE \
66 /* val, encode */ \
67 X(Reg_al, = 0) \
68 X(Reg_cl, = 1) \
69 X(Reg_dl, = 2) \
John Porto448c16f2015-07-28 16:56:29 -0700[diff] [blame]70 X(Reg_bl, = 3)
Jan Voungbd385e42014-09-18 18:18:10 -0700[diff] [blame]71//#define X(val, encode)
72
Jan Voung3bd9f1a2014-06-18 10:50:57 -0700[diff] [blame]73// X86 segment registers.
Jan Voungfe14fb82014-10-13 15:56:32 -0700[diff] [blame]74#define SEG_REGX8632_TABLE \
75 /* enum value, name, prefix */ \
76 X(SegReg_CS, "cs", 0x2E) \
77 X(SegReg_DS, "ds", 0x3E) \
78 X(SegReg_ES, "es", 0x26) \
79 X(SegReg_SS, "ss", 0x36) \
80 X(SegReg_FS, "fs", 0x64) \
81 X(SegReg_GS, "gs", 0x65) \
82//#define X(val, name, prefix)
Jim Stichnoth5bc2b1d2014-05-22 13:38:48 -0700[diff] [blame]83
Jan Voung479e5632014-10-08 21:05:27 -0700[diff] [blame]84// X87 ST(n) registers.
85#define X87ST_REGX8632_TABLE \
86 /* enum value, encode, name */ \
87 X(X87ST_First, = 0, "st(0)") \
88 X(X87ST_0, = 0, "st(0)") \
89 X(X87ST_1, = 1, "st(1)") \
90 X(X87ST_2, = 2, "st(2)") \
91 X(X87ST_3, = 3, "st(3)") \
92 X(X87ST_4, = 4, "st(4)") \
93 X(X87ST_5, = 5, "st(5)") \
94 X(X87ST_6, = 6, "st(6)") \
95 X(X87ST_7, = 7, "st(7)") \
96 X(X87ST_Last, = 7, "st(7)") \
97//#define X(val, encode, name)
98
Jim Stichnoth5bc2b1d2014-05-22 13:38:48 -0700[diff] [blame]99#define ICEINSTX8632BR_TABLE \
Jan Voungbd385e42014-09-18 18:18:10 -0700[diff] [blame]100 /* enum value, encode, opposite, dump, emit */ \
101 X(Br_o, = 0, Br_no, "o", "jo") \
102 X(Br_no, = 1, Br_o, "no", "jno") \
103 X(Br_b, = 2, Br_ae, "b", "jb") \
104 X(Br_ae, = 3, Br_b, "ae", "jae") \
105 X(Br_e, = 4, Br_ne, "e", "je") \
106 X(Br_ne, = 5, Br_e, "ne", "jne") \
107 X(Br_be, = 6, Br_a, "be", "jbe") \
108 X(Br_a, = 7, Br_be, "a", "ja") \
109 X(Br_s, = 8, Br_ns, "s", "js") \
110 X(Br_ns, = 9, Br_s, "ns", "jns") \
111 X(Br_p, = 10, Br_np, "p", "jp") \
112 X(Br_np, = 11, Br_p, "np", "jnp") \
113 X(Br_l, = 12, Br_ge, "l", "jl") \
114 X(Br_ge, = 13, Br_l, "ge", "jge") \
115 X(Br_le, = 14, Br_g, "le", "jle") \
116 X(Br_g, = 15, Br_le, "g", "jg") \
117//#define X(tag, encode, opp, dump, emit)
Jim Stichnoth5bc2b1d2014-05-22 13:38:48 -0700[diff] [blame]118
Matt Walace0ca8f2014-07-24 12:34:20 -0700[diff] [blame]119#define ICEINSTX8632CMPPS_TABLE \
120 /* enum value, emit */ \
121 X(Cmpps_eq, "eq") \
122 X(Cmpps_lt, "lt") \
123 X(Cmpps_le, "le") \
124 X(Cmpps_unord, "unord") \
125 X(Cmpps_neq, "neq") \
126 X(Cmpps_nlt, "nlt") \
127 X(Cmpps_nle, "nle") \
128 X(Cmpps_ord, "ord") \
129//#define X(tag, emit)
130
Jim Stichnothbca2f652014-11-01 10:13:54 -0700[diff] [blame]131#define ICETYPEX8632_TABLE \
132 /* tag, element type, cvt, sdss, pack, width, fld */ \
133 X(IceType_void, IceType_void, "?" , "" , "" , "", "") \
134 X(IceType_i1, IceType_void, "si", "" , "" , "b", "") \
135 X(IceType_i8, IceType_void, "si", "" , "" , "b", "") \
136 X(IceType_i16, IceType_void, "si", "" , "" , "w", "") \
137 X(IceType_i32, IceType_void, "si", "" , "" , "l", "") \
138 X(IceType_i64, IceType_void, "si", "" , "" , "q", "") \
Jim Stichnoth8c980d02015-03-19 13:01:50 -0700[diff] [blame]139 X(IceType_f32, IceType_void, "ss", "ss", "d", "", "s") \
140 X(IceType_f64, IceType_void, "sd", "sd", "q", "", "l") \
Jim Stichnothbca2f652014-11-01 10:13:54 -0700[diff] [blame]141 X(IceType_v4i1, IceType_i32 , "?" , "" , "d", "", "") \
142 X(IceType_v8i1, IceType_i16 , "?" , "" , "w", "", "") \
143 X(IceType_v16i1, IceType_i8 , "?" , "" , "b", "", "") \
144 X(IceType_v16i8, IceType_i8 , "?" , "" , "b", "", "") \
145 X(IceType_v8i16, IceType_i16 , "?" , "" , "w", "", "") \
146 X(IceType_v4i32, IceType_i32 , "dq", "" , "d", "", "") \
Jim Stichnoth8c980d02015-03-19 13:01:50 -0700[diff] [blame]147 X(IceType_v4f32, IceType_f32 , "ps", "" , "d", "", "") \
Jim Stichnothbca2f652014-11-01 10:13:54 -0700[diff] [blame]148//#define X(tag, elementty, cvt, sdss, pack, width, fld)
Jim Stichnoth5bc2b1d2014-05-22 13:38:48 -0700[diff] [blame]149
150#endif // SUBZERO_SRC_ICEINSTX8632_DEF