Removes references to ah.
AH is a thorn in the flesh for our X86-64 backend. The assembler was
designed to always encode the low 8-bit registers, so %ah would become
%spl. While it is true we **could** force %spl to always be encoded as
%ah, that would not work if the instruction has a rex prefix.
This CL removes references to %ah from TargetX86Base. There used to be
2 uses of ah in the target lowering:
1) To zero-extend %al before an unsigned div:
mov <<src0>>, %al
mov 0, %ah
div <<src1>>
This pattern has been changed to
xor %eax, %eax
mov <<src0>>, %al
div <<src1>>
2) To access the 8-bit remainder for 8-bit division:
mov %ah, <<dest>>
This pattern has been changed to
shr $8, %eax
mov %al, <<Dest>>
BUG= https://code.google.com/p/nativeclient/issues/detail?id=4077
R=stichnot@chromium.org
Review URL: https://codereview.chromium.org/1260163003.
diff --git a/src/IceInstX8632.def b/src/IceInstX8632.def
index f9b1e88..3129dad 100644
--- a/src/IceInstX8632.def
+++ b/src/IceInstX8632.def
@@ -44,16 +44,10 @@
// all of the registers are considered and have distinct numberings.
// This is in contrast to the above, where the "encode" is based on how
// the register numbers will be encoded in binaries and values can overlap.
-// Note that the isI8 attributed of Reg_ah is not set. In general we
-// don't want the register allocator choosing Reg_ah, in particular
-// for lowering insertelement to pinsrb where internally we use an
-// 8-bit operand but externally pinsrb uses a 32-bit register, in
-// which Reg_ah doesn't map to eax.
#define REGX8632_TABLE \
/* val, encode, name, name16, name8, scratch, preserved, stackptr, \
frameptr, isI8, isInt, isFP */ \
REGX8632_GPR_TABLE \
- X(Reg_ah, 4, "???", "" , "ah", 0, 0, 0, 0, 0, 0, 0) \
REGX8632_XMM_TABLE
//#define X(val, encode, name, name16, name8, scratch, preserved, stackptr,
// frameptr, isI8, isInt, isFP)
@@ -73,8 +67,7 @@
X(Reg_al, = 0) \
X(Reg_cl, = 1) \
X(Reg_dl, = 2) \
- X(Reg_bl, = 3) \
- X(Reg_ah, = 4)
+ X(Reg_bl, = 3)
//#define X(val, encode)
// X86 segment registers.
