| Jim Stichnoth | 5bc2b1d | 2014-05-22 13:38:48 -0700 | [diff] [blame] | 1 | //===- subzero/src/IceInstX8632.def - X-macros for x86-32 insts -*- C++ -*-===// |
| 2 | // |
| 3 | // The Subzero Code Generator |
| 4 | // |
| 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
| 10 | // This file defines properties of lowered x86-32 instructions in the |
| 11 | // form of x-macros. |
| 12 | // |
| 13 | //===----------------------------------------------------------------------===// |
| 14 | |
| 15 | #ifndef SUBZERO_SRC_ICEINSTX8632_DEF |
| 16 | #define SUBZERO_SRC_ICEINSTX8632_DEF |
| 17 | |
| Jan Voung | 9559899 | 2014-07-09 09:54:25 -0700 | [diff] [blame] | 18 | // NOTE: esp is not considered isInt, to avoid register allocating it. |
| Jim Stichnoth | 5bc2b1d | 2014-05-22 13:38:48 -0700 | [diff] [blame] | 19 | #define REGX8632_TABLE \ |
| 20 | /* val, init, name, name16, name8, scratch, preserved, stackptr, \ |
| 21 | frameptr, isI8, isInt, isFP */ \ |
| 22 | X(Reg_eax, = 0, "eax", "ax", "al", 1, 0, 0, 0, 1, 1, 0) \ |
| 23 | X(Reg_ecx, = Reg_eax + 1, "ecx", "cx", "cl", 1, 0, 0, 0, 1, 1, 0) \ |
| 24 | X(Reg_edx, = Reg_eax + 2, "edx", "dx", "dl", 1, 0, 0, 0, 1, 1, 0) \ |
| 25 | X(Reg_ebx, = Reg_eax + 3, "ebx", "bx", "bl", 0, 1, 0, 0, 1, 1, 0) \ |
| Jan Voung | 9559899 | 2014-07-09 09:54:25 -0700 | [diff] [blame] | 26 | X(Reg_esp, = Reg_eax + 4, "esp", "sp", "" , 0, 0, 1, 0, 0, 0, 0) \ |
| Jim Stichnoth | 4376d29 | 2014-05-23 13:39:02 -0700 | [diff] [blame] | 27 | X(Reg_ebp, = Reg_eax + 5, "ebp", "bp", "" , 0, 1, 0, 1, 0, 1, 0) \ |
| 28 | X(Reg_esi, = Reg_eax + 6, "esi", "si", "" , 0, 1, 0, 0, 0, 1, 0) \ |
| 29 | X(Reg_edi, = Reg_eax + 7, "edi", "di", "" , 0, 1, 0, 0, 0, 1, 0) \ |
| 30 | X(Reg_ah, = Reg_edi + 1, "???", "" , "ah", 0, 0, 0, 0, 1, 0, 0) \ |
| 31 | X(Reg_xmm0, = Reg_ah + 1, "xmm0", "" , "" , 1, 0, 0, 0, 0, 0, 1) \ |
| 32 | X(Reg_xmm1, = Reg_xmm0 + 1, "xmm1", "" , "" , 1, 0, 0, 0, 0, 0, 1) \ |
| 33 | X(Reg_xmm2, = Reg_xmm0 + 2, "xmm2", "" , "" , 1, 0, 0, 0, 0, 0, 1) \ |
| 34 | X(Reg_xmm3, = Reg_xmm0 + 3, "xmm3", "" , "" , 1, 0, 0, 0, 0, 0, 1) \ |
| 35 | X(Reg_xmm4, = Reg_xmm0 + 4, "xmm4", "" , "" , 1, 0, 0, 0, 0, 0, 1) \ |
| 36 | X(Reg_xmm5, = Reg_xmm0 + 5, "xmm5", "" , "" , 1, 0, 0, 0, 0, 0, 1) \ |
| 37 | X(Reg_xmm6, = Reg_xmm0 + 6, "xmm6", "" , "" , 1, 0, 0, 0, 0, 0, 1) \ |
| 38 | X(Reg_xmm7, = Reg_xmm0 + 7, "xmm7", "" , "" , 1, 0, 0, 0, 0, 0, 1) \ |
| Jim Stichnoth | 5bc2b1d | 2014-05-22 13:38:48 -0700 | [diff] [blame] | 39 | //#define X(val, init, name, name16, name8, scratch, preserved, stackptr, |
| 40 | // frameptr, isI8, isInt, isFP) |
| 41 | |
| Jan Voung | 3bd9f1a | 2014-06-18 10:50:57 -0700 | [diff] [blame] | 42 | // X86 segment registers. |
| 43 | #define SEG_REGX8632_TABLE \ |
| 44 | /* enum value, name */ \ |
| 45 | X(SegReg_CS, "cs") \ |
| 46 | X(SegReg_DS, "ds") \ |
| 47 | X(SegReg_ES, "es") \ |
| 48 | X(SegReg_SS, "ss") \ |
| 49 | X(SegReg_FS, "fs") \ |
| 50 | X(SegReg_GS, "gs") \ |
| 51 | //#define X(val, name) |
| Jim Stichnoth | 5bc2b1d | 2014-05-22 13:38:48 -0700 | [diff] [blame] | 52 | |
| 53 | #define ICEINSTX8632BR_TABLE \ |
| 54 | /* enum value, dump, emit */ \ |
| 55 | X(Br_a, "a", "ja") \ |
| 56 | X(Br_ae, "ae", "jae") \ |
| 57 | X(Br_b, "b", "jb") \ |
| 58 | X(Br_be, "be", "jbe") \ |
| 59 | X(Br_e, "e", "je") \ |
| 60 | X(Br_g, "g", "jg") \ |
| 61 | X(Br_ge, "ge", "jge") \ |
| 62 | X(Br_l, "l", "jl") \ |
| 63 | X(Br_le, "le", "jle") \ |
| 64 | X(Br_ne, "ne", "jne") \ |
| 65 | X(Br_np, "np", "jnp") \ |
| 66 | X(Br_p, "p", "jp") \ |
| 67 | //#define X(tag, dump, emit) |
| 68 | |
| Matt Wala | ce0ca8f | 2014-07-24 12:34:20 -0700 | [diff] [blame] | 69 | #define ICEINSTX8632CMPPS_TABLE \ |
| 70 | /* enum value, emit */ \ |
| 71 | X(Cmpps_eq, "eq") \ |
| 72 | X(Cmpps_lt, "lt") \ |
| 73 | X(Cmpps_le, "le") \ |
| 74 | X(Cmpps_unord, "unord") \ |
| 75 | X(Cmpps_neq, "neq") \ |
| 76 | X(Cmpps_nlt, "nlt") \ |
| 77 | X(Cmpps_nle, "nle") \ |
| 78 | X(Cmpps_ord, "ord") \ |
| 79 | //#define X(tag, emit) |
| 80 | |
| Matt Wala | 4988923 | 2014-07-18 12:45:09 -0700 | [diff] [blame] | 81 | #define ICETYPEX8632_TABLE \ |
| 82 | /* tag, element type, cvt, sdss, pack, width */ \ |
| 83 | X(IceType_void, IceType_void, "?" , "" , "" , "???") \ |
| 84 | X(IceType_i1, IceType_void, "si", "" , "" , "byte ptr") \ |
| 85 | X(IceType_i8, IceType_void, "si", "" , "" , "byte ptr") \ |
| 86 | X(IceType_i16, IceType_void, "si", "" , "" , "word ptr") \ |
| 87 | X(IceType_i32, IceType_void, "si", "" , "" , "dword ptr") \ |
| 88 | X(IceType_i64, IceType_void, "si", "" , "" , "qword ptr") \ |
| 89 | X(IceType_f32, IceType_void, "ss", "ss", "" , "dword ptr") \ |
| 90 | X(IceType_f64, IceType_void, "sd", "sd", "" , "qword ptr") \ |
| Matt Wala | 0a45051 | 2014-07-30 12:44:39 -0700 | [diff] [blame] | 91 | X(IceType_v4i1, IceType_i32 , "?" , "" , "d", "xmmword ptr") \ |
| 92 | X(IceType_v8i1, IceType_i16 , "?" , "" , "w", "xmmword ptr") \ |
| 93 | X(IceType_v16i1, IceType_i8 , "?" , "" , "b", "xmmword ptr") \ |
| Matt Wala | 4988923 | 2014-07-18 12:45:09 -0700 | [diff] [blame] | 94 | X(IceType_v16i8, IceType_i8 , "?" , "" , "b", "xmmword ptr") \ |
| 95 | X(IceType_v8i16, IceType_i16 , "?" , "" , "w", "xmmword ptr") \ |
| 96 | X(IceType_v4i32, IceType_i32 , "dq", "" , "d", "xmmword ptr") \ |
| 97 | X(IceType_v4f32, IceType_f32 , "ps", "" , "" , "xmmword ptr") \ |
| 98 | //#define X(tag, elementty, cvt, sdss, width) |
| Jim Stichnoth | 5bc2b1d | 2014-05-22 13:38:48 -0700 | [diff] [blame] | 99 | |
| 100 | #endif // SUBZERO_SRC_ICEINSTX8632_DEF |
