Matt Wala | 9cb61e2 | 2014-07-24 09:44:42 -0700 | [diff] [blame] | 1 | target triple = "i686-pc-linux-gnu" |
| 2 | |
| 3 | define <4 x float> @_Z6selectDv4_iDv4_fS0_(<4 x i32> %cond.ext, <4 x float> %arg1, <4 x float> %arg2) { |
| 4 | entry: |
| 5 | %cond = trunc <4 x i32> %cond.ext to <4 x i1> |
| 6 | %res = select <4 x i1> %cond, <4 x float> %arg1, <4 x float> %arg2 |
| 7 | ret <4 x float> %res |
| 8 | } |
| 9 | |
| 10 | define <4 x i32> @_Z6selectDv4_iS_S_(<4 x i32> %cond.ext, <4 x i32> %arg1, <4 x i32> %arg2) { |
| 11 | entry: |
| 12 | %cond = trunc <4 x i32> %cond.ext to <4 x i1> |
| 13 | %res = select <4 x i1> %cond, <4 x i32> %arg1, <4 x i32> %arg2 |
| 14 | ret <4 x i32> %res |
| 15 | } |
| 16 | |
| 17 | define <4 x i32> @_Z6selectDv4_iDv4_jS0_(<4 x i32> %cond.ext, <4 x i32> %arg1, <4 x i32> %arg2) { |
| 18 | entry: |
| 19 | %cond = trunc <4 x i32> %cond.ext to <4 x i1> |
| 20 | %res = select <4 x i1> %cond, <4 x i32> %arg1, <4 x i32> %arg2 |
| 21 | ret <4 x i32> %res |
| 22 | } |
| 23 | |
| 24 | define <8 x i16> @_Z6selectDv8_sS_S_(<8 x i16> %cond.ext, <8 x i16> %arg1, <8 x i16> %arg2) { |
| 25 | entry: |
| 26 | %cond = trunc <8 x i16> %cond.ext to <8 x i1> |
| 27 | %res = select <8 x i1> %cond, <8 x i16> %arg1, <8 x i16> %arg2 |
| 28 | ret <8 x i16> %res |
| 29 | } |
| 30 | |
| 31 | define <8 x i16> @_Z6selectDv8_sDv8_tS0_(<8 x i16> %cond.ext, <8 x i16> %arg1, <8 x i16> %arg2) { |
| 32 | entry: |
| 33 | %cond = trunc <8 x i16> %cond.ext to <8 x i1> |
| 34 | %res = select <8 x i1> %cond, <8 x i16> %arg1, <8 x i16> %arg2 |
| 35 | ret <8 x i16> %res |
| 36 | } |
| 37 | |
| 38 | define <16 x i8> @_Z6selectDv16_aS_S_(<16 x i8> %cond.ext, <16 x i8> %arg1, <16 x i8> %arg2) { |
| 39 | entry: |
| 40 | %cond = trunc <16 x i8> %cond.ext to <16 x i1> |
| 41 | %res = select <16 x i1> %cond, <16 x i8> %arg1, <16 x i8> %arg2 |
| 42 | ret <16 x i8> %res |
| 43 | } |
| 44 | |
| 45 | define <16 x i8> @_Z6selectDv16_aDv16_hS0_(<16 x i8> %cond.ext, <16 x i8> %arg1, <16 x i8> %arg2) { |
| 46 | entry: |
| 47 | %cond = trunc <16 x i8> %cond.ext to <16 x i1> |
| 48 | %res = select <16 x i1> %cond, <16 x i8> %arg1, <16 x i8> %arg2 |
| 49 | ret <16 x i8> %res |
| 50 | } |
| 51 | |
| 52 | define <4 x i32> @_Z9select_i1Dv4_iS_S_(<4 x i32> %cond.ext, <4 x i32> %arg1.ext, <4 x i32> %arg2.ext) { |
| 53 | entry: |
| 54 | %cond = trunc <4 x i32> %cond.ext to <4 x i1> |
| 55 | %arg1 = trunc <4 x i32> %arg1.ext to <4 x i1> |
| 56 | %arg2 = trunc <4 x i32> %arg2.ext to <4 x i1> |
| 57 | %res.trunc = select <4 x i1> %cond, <4 x i1> %arg1, <4 x i1> %arg2 |
| 58 | %res = sext <4 x i1> %res.trunc to <4 x i32> |
| 59 | ret <4 x i32> %res |
| 60 | } |
| 61 | |
| 62 | define <8 x i16> @_Z9select_i1Dv8_sS_S_(<8 x i16> %cond.ext, <8 x i16> %arg1.ext, <8 x i16> %arg2.ext) { |
| 63 | entry: |
| 64 | %cond = trunc <8 x i16> %cond.ext to <8 x i1> |
| 65 | %arg1 = trunc <8 x i16> %arg1.ext to <8 x i1> |
| 66 | %arg2 = trunc <8 x i16> %arg2.ext to <8 x i1> |
| 67 | %res.trunc = select <8 x i1> %cond, <8 x i1> %arg1, <8 x i1> %arg2 |
| 68 | %res = sext <8 x i1> %res.trunc to <8 x i16> |
| 69 | ret <8 x i16> %res |
| 70 | } |
| 71 | |
| 72 | define <16 x i8> @_Z9select_i1Dv16_aS_S_(<16 x i8> %cond.ext, <16 x i8> %arg1.ext, <16 x i8> %arg2.ext) { |
| 73 | entry: |
| 74 | %cond = trunc <16 x i8> %cond.ext to <16 x i1> |
| 75 | %arg1 = trunc <16 x i8> %arg1.ext to <16 x i1> |
| 76 | %arg2 = trunc <16 x i8> %arg2.ext to <16 x i1> |
| 77 | %res.trunc = select <16 x i1> %cond, <16 x i1> %arg1, <16 x i1> %arg2 |
| 78 | %res = sext <16 x i1> %res.trunc to <16 x i8> |
| 79 | ret <16 x i8> %res |
| 80 | } |