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swiftshader / SwiftShader / 3e53dc99c9f61fc1f65e85735220f0b03d2487ca / . / src / DartARM32 / assembler_arm.cc
blob: 5c0a90ed3376e58cc44dc4b3b9f922bdb87974b6 [file] [log] [blame]
Karl Schimpf3e53dc92015-10-07 13:24:01 -0700[diff] [blame^]1// Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file
2// for details. All rights reserved. Use of this source code is governed by a
3// BSD-style license that can be found in the LICENSE file.
4//
5// This is forked from Dart revision df52deea9f25690eb8b66c5995da92b70f7ac1fe
6// Please update the (git) revision if we merge changes from Dart.
7// https://code.google.com/p/dart/wiki/GettingTheSource
8
9#include "vm/globals.h" // NOLINT
10#if defined(TARGET_ARCH_ARM)
11
12#include "vm/assembler.h"
13#include "vm/cpu.h"
14#include "vm/longjump.h"
15#include "vm/runtime_entry.h"
16#include "vm/simulator.h"
17#include "vm/stack_frame.h"
18#include "vm/stub_code.h"
19
20// An extra check since we are assuming the existence of /proc/cpuinfo below.
21#if !defined(USING_SIMULATOR) && !defined(__linux__) && !defined(ANDROID)
22#error ARM cross-compile only supported on Linux
23#endif
24
25namespace dart {
26
27DECLARE_FLAG(bool, allow_absolute_addresses);
28DEFINE_FLAG(bool, print_stop_message, true, "Print stop message.");
29DECLARE_FLAG(bool, inline_alloc);
30
31uint32_t Address::encoding3() const {
32 if (kind_ == Immediate) {
33 uint32_t offset = encoding_ & kOffset12Mask;
34 ASSERT(offset < 256);
35 return (encoding_ & ~kOffset12Mask) | B22 |
36 ((offset & 0xf0) << 4) | (offset & 0xf);
37 }
38 ASSERT(kind_ == IndexRegister);
39 return encoding_;
40}
41
42
43uint32_t Address::vencoding() const {
44 ASSERT(kind_ == Immediate);
45 uint32_t offset = encoding_ & kOffset12Mask;
46 ASSERT(offset < (1 << 10)); // In the range 0 to +1020.
47 ASSERT(Utils::IsAligned(offset, 4)); // Multiple of 4.
48 int mode = encoding_ & ((8|4|1) << 21);
49 ASSERT((mode == Offset) || (mode == NegOffset));
50 uint32_t vencoding = (encoding_ & (0xf << kRnShift)) | (offset >> 2);
51 if (mode == Offset) {
52 vencoding |= 1 << 23;
53 }
54 return vencoding;
55}
56
57
58void Assembler::InitializeMemoryWithBreakpoints(uword data, intptr_t length) {
59 ASSERT(Utils::IsAligned(data, 4));
60 ASSERT(Utils::IsAligned(length, 4));
61 const uword end = data + length;
62 while (data < end) {
63 *reinterpret_cast<int32_t*>(data) = Instr::kBreakPointInstruction;
64 data += 4;
65 }
66}
67
68
69void Assembler::Emit(int32_t value) {
70 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
71 buffer_.Emit<int32_t>(value);
72}
73
74
75void Assembler::EmitType01(Condition cond,
76 int type,
77 Opcode opcode,
78 int set_cc,
79 Register rn,
80 Register rd,
81 Operand o) {
82 ASSERT(rd != kNoRegister);
83 ASSERT(cond != kNoCondition);
84 int32_t encoding = static_cast<int32_t>(cond) << kConditionShift |
85 type << kTypeShift |
86 static_cast<int32_t>(opcode) << kOpcodeShift |
87 set_cc << kSShift |
88 static_cast<int32_t>(rn) << kRnShift |
89 static_cast<int32_t>(rd) << kRdShift |
90 o.encoding();
91 Emit(encoding);
92}
93
94
95void Assembler::EmitType5(Condition cond, int32_t offset, bool link) {
96 ASSERT(cond != kNoCondition);
97 int32_t encoding = static_cast<int32_t>(cond) << kConditionShift |
98 5 << kTypeShift |
99 (link ? 1 : 0) << kLinkShift;
100 Emit(Assembler::EncodeBranchOffset(offset, encoding));
101}
102
103
104void Assembler::EmitMemOp(Condition cond,
105 bool load,
106 bool byte,
107 Register rd,
108 Address ad) {
109 ASSERT(rd != kNoRegister);
110 ASSERT(cond != kNoCondition);
111 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
112 B26 | (ad.kind() == Address::Immediate ? 0 : B25) |
113 (load ? L : 0) |
114 (byte ? B : 0) |
115 (static_cast<int32_t>(rd) << kRdShift) |
116 ad.encoding();
117 Emit(encoding);
118}
119
120
121void Assembler::EmitMemOpAddressMode3(Condition cond,
122 int32_t mode,
123 Register rd,
124 Address ad) {
125 ASSERT(rd != kNoRegister);
126 ASSERT(cond != kNoCondition);
127 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
128 mode |
129 (static_cast<int32_t>(rd) << kRdShift) |
130 ad.encoding3();
131 Emit(encoding);
132}
133
134
135void Assembler::EmitMultiMemOp(Condition cond,
136 BlockAddressMode am,
137 bool load,
138 Register base,
139 RegList regs) {
140 ASSERT(base != kNoRegister);
141 ASSERT(cond != kNoCondition);
142 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
143 B27 |
144 am |
145 (load ? L : 0) |
146 (static_cast<int32_t>(base) << kRnShift) |
147 regs;
148 Emit(encoding);
149}
150
151
152void Assembler::EmitShiftImmediate(Condition cond,
153 Shift opcode,
154 Register rd,
155 Register rm,
156 Operand o) {
157 ASSERT(cond != kNoCondition);
158 ASSERT(o.type() == 1);
159 int32_t encoding = static_cast<int32_t>(cond) << kConditionShift |
160 static_cast<int32_t>(MOV) << kOpcodeShift |
161 static_cast<int32_t>(rd) << kRdShift |
162 o.encoding() << kShiftImmShift |
163 static_cast<int32_t>(opcode) << kShiftShift |
164 static_cast<int32_t>(rm);
165 Emit(encoding);
166}
167
168
169void Assembler::EmitShiftRegister(Condition cond,
170 Shift opcode,
171 Register rd,
172 Register rm,
173 Operand o) {
174 ASSERT(cond != kNoCondition);
175 ASSERT(o.type() == 0);
176 int32_t encoding = static_cast<int32_t>(cond) << kConditionShift |
177 static_cast<int32_t>(MOV) << kOpcodeShift |
178 static_cast<int32_t>(rd) << kRdShift |
179 o.encoding() << kShiftRegisterShift |
180 static_cast<int32_t>(opcode) << kShiftShift |
181 B4 |
182 static_cast<int32_t>(rm);
183 Emit(encoding);
184}
185
186
187void Assembler::and_(Register rd, Register rn, Operand o, Condition cond) {
188 EmitType01(cond, o.type(), AND, 0, rn, rd, o);
189}
190
191
192void Assembler::eor(Register rd, Register rn, Operand o, Condition cond) {
193 EmitType01(cond, o.type(), EOR, 0, rn, rd, o);
194}
195
196
197void Assembler::sub(Register rd, Register rn, Operand o, Condition cond) {
198 EmitType01(cond, o.type(), SUB, 0, rn, rd, o);
199}
200
201void Assembler::rsb(Register rd, Register rn, Operand o, Condition cond) {
202 EmitType01(cond, o.type(), RSB, 0, rn, rd, o);
203}
204
205void Assembler::rsbs(Register rd, Register rn, Operand o, Condition cond) {
206 EmitType01(cond, o.type(), RSB, 1, rn, rd, o);
207}
208
209
210void Assembler::add(Register rd, Register rn, Operand o, Condition cond) {
211 EmitType01(cond, o.type(), ADD, 0, rn, rd, o);
212}
213
214
215void Assembler::adds(Register rd, Register rn, Operand o, Condition cond) {
216 EmitType01(cond, o.type(), ADD, 1, rn, rd, o);
217}
218
219
220void Assembler::subs(Register rd, Register rn, Operand o, Condition cond) {
221 EmitType01(cond, o.type(), SUB, 1, rn, rd, o);
222}
223
224
225void Assembler::adc(Register rd, Register rn, Operand o, Condition cond) {
226 EmitType01(cond, o.type(), ADC, 0, rn, rd, o);
227}
228
229
230void Assembler::adcs(Register rd, Register rn, Operand o, Condition cond) {
231 EmitType01(cond, o.type(), ADC, 1, rn, rd, o);
232}
233
234
235void Assembler::sbc(Register rd, Register rn, Operand o, Condition cond) {
236 EmitType01(cond, o.type(), SBC, 0, rn, rd, o);
237}
238
239
240void Assembler::sbcs(Register rd, Register rn, Operand o, Condition cond) {
241 EmitType01(cond, o.type(), SBC, 1, rn, rd, o);
242}
243
244
245void Assembler::rsc(Register rd, Register rn, Operand o, Condition cond) {
246 EmitType01(cond, o.type(), RSC, 0, rn, rd, o);
247}
248
249
250void Assembler::tst(Register rn, Operand o, Condition cond) {
251 EmitType01(cond, o.type(), TST, 1, rn, R0, o);
252}
253
254
255void Assembler::teq(Register rn, Operand o, Condition cond) {
256 EmitType01(cond, o.type(), TEQ, 1, rn, R0, o);
257}
258
259
260void Assembler::cmp(Register rn, Operand o, Condition cond) {
261 EmitType01(cond, o.type(), CMP, 1, rn, R0, o);
262}
263
264
265void Assembler::cmn(Register rn, Operand o, Condition cond) {
266 EmitType01(cond, o.type(), CMN, 1, rn, R0, o);
267}
268
269
270void Assembler::orr(Register rd, Register rn, Operand o, Condition cond) {
271 EmitType01(cond, o.type(), ORR, 0, rn, rd, o);
272}
273
274
275void Assembler::orrs(Register rd, Register rn, Operand o, Condition cond) {
276 EmitType01(cond, o.type(), ORR, 1, rn, rd, o);
277}
278
279
280void Assembler::mov(Register rd, Operand o, Condition cond) {
281 EmitType01(cond, o.type(), MOV, 0, R0, rd, o);
282}
283
284
285void Assembler::movs(Register rd, Operand o, Condition cond) {
286 EmitType01(cond, o.type(), MOV, 1, R0, rd, o);
287}
288
289
290void Assembler::bic(Register rd, Register rn, Operand o, Condition cond) {
291 EmitType01(cond, o.type(), BIC, 0, rn, rd, o);
292}
293
294
295void Assembler::bics(Register rd, Register rn, Operand o, Condition cond) {
296 EmitType01(cond, o.type(), BIC, 1, rn, rd, o);
297}
298
299
300void Assembler::mvn(Register rd, Operand o, Condition cond) {
301 EmitType01(cond, o.type(), MVN, 0, R0, rd, o);
302}
303
304
305void Assembler::mvns(Register rd, Operand o, Condition cond) {
306 EmitType01(cond, o.type(), MVN, 1, R0, rd, o);
307}
308
309
310void Assembler::clz(Register rd, Register rm, Condition cond) {
311 ASSERT(rd != kNoRegister);
312 ASSERT(rm != kNoRegister);
313 ASSERT(cond != kNoCondition);
314 ASSERT(rd != PC);
315 ASSERT(rm != PC);
316 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
317 B24 | B22 | B21 | (0xf << 16) |
318 (static_cast<int32_t>(rd) << kRdShift) |
319 (0xf << 8) | B4 | static_cast<int32_t>(rm);
320 Emit(encoding);
321}
322
323
324void Assembler::movw(Register rd, uint16_t imm16, Condition cond) {
325 ASSERT(cond != kNoCondition);
326 int32_t encoding = static_cast<int32_t>(cond) << kConditionShift |
327 B25 | B24 | ((imm16 >> 12) << 16) |
328 static_cast<int32_t>(rd) << kRdShift | (imm16 & 0xfff);
329 Emit(encoding);
330}
331
332
333void Assembler::movt(Register rd, uint16_t imm16, Condition cond) {
334 ASSERT(cond != kNoCondition);
335 int32_t encoding = static_cast<int32_t>(cond) << kConditionShift |
336 B25 | B24 | B22 | ((imm16 >> 12) << 16) |
337 static_cast<int32_t>(rd) << kRdShift | (imm16 & 0xfff);
338 Emit(encoding);
339}
340
341
342void Assembler::EmitMulOp(Condition cond, int32_t opcode,
343 Register rd, Register rn,
344 Register rm, Register rs) {
345 ASSERT(rd != kNoRegister);
346 ASSERT(rn != kNoRegister);
347 ASSERT(rm != kNoRegister);
348 ASSERT(rs != kNoRegister);
349 ASSERT(cond != kNoCondition);
350 int32_t encoding = opcode |
351 (static_cast<int32_t>(cond) << kConditionShift) |
352 (static_cast<int32_t>(rn) << kRnShift) |
353 (static_cast<int32_t>(rd) << kRdShift) |
354 (static_cast<int32_t>(rs) << kRsShift) |
355 B7 | B4 |
356 (static_cast<int32_t>(rm) << kRmShift);
357 Emit(encoding);
358}
359
360
361void Assembler::mul(Register rd, Register rn, Register rm, Condition cond) {
362 // Assembler registers rd, rn, rm are encoded as rn, rm, rs.
363 EmitMulOp(cond, 0, R0, rd, rn, rm);
364}
365
366
367// Like mul, but sets condition flags.
368void Assembler::muls(Register rd, Register rn, Register rm, Condition cond) {
369 EmitMulOp(cond, B20, R0, rd, rn, rm);
370}
371
372
373void Assembler::mla(Register rd, Register rn,
374 Register rm, Register ra, Condition cond) {
375 // rd <- ra + rn * rm.
376 // Assembler registers rd, rn, rm, ra are encoded as rn, rm, rs, rd.
377 EmitMulOp(cond, B21, ra, rd, rn, rm);
378}
379
380
381void Assembler::mls(Register rd, Register rn,
382 Register rm, Register ra, Condition cond) {
383 // rd <- ra - rn * rm.
384 if (TargetCPUFeatures::arm_version() == ARMv7) {
385 // Assembler registers rd, rn, rm, ra are encoded as rn, rm, rs, rd.
386 EmitMulOp(cond, B22 | B21, ra, rd, rn, rm);
387 } else {
388 mul(IP, rn, rm, cond);
389 sub(rd, ra, Operand(IP), cond);
390 }
391}
392
393
394void Assembler::smull(Register rd_lo, Register rd_hi,
395 Register rn, Register rm, Condition cond) {
396 // Assembler registers rd_lo, rd_hi, rn, rm are encoded as rd, rn, rm, rs.
397 EmitMulOp(cond, B23 | B22, rd_lo, rd_hi, rn, rm);
398}
399
400
401void Assembler::umull(Register rd_lo, Register rd_hi,
402 Register rn, Register rm, Condition cond) {
403 // Assembler registers rd_lo, rd_hi, rn, rm are encoded as rd, rn, rm, rs.
404 EmitMulOp(cond, B23, rd_lo, rd_hi, rn, rm);
405}
406
407
408void Assembler::umlal(Register rd_lo, Register rd_hi,
409 Register rn, Register rm, Condition cond) {
410 // Assembler registers rd_lo, rd_hi, rn, rm are encoded as rd, rn, rm, rs.
411 EmitMulOp(cond, B23 | B21, rd_lo, rd_hi, rn, rm);
412}
413
414
415void Assembler::umaal(Register rd_lo, Register rd_hi,
416 Register rn, Register rm) {
417 ASSERT(rd_lo != IP);
418 ASSERT(rd_hi != IP);
419 ASSERT(rn != IP);
420 ASSERT(rm != IP);
421 if (TargetCPUFeatures::arm_version() != ARMv5TE) {
422 // Assembler registers rd_lo, rd_hi, rn, rm are encoded as rd, rn, rm, rs.
423 EmitMulOp(AL, B22, rd_lo, rd_hi, rn, rm);
424 } else {
425 mov(IP, Operand(0));
426 umlal(rd_lo, IP, rn, rm);
427 adds(rd_lo, rd_lo, Operand(rd_hi));
428 adc(rd_hi, IP, Operand(0));
429 }
430}
431
432
433void Assembler::EmitDivOp(Condition cond, int32_t opcode,
434 Register rd, Register rn, Register rm) {
435 ASSERT(TargetCPUFeatures::integer_division_supported());
436 ASSERT(rd != kNoRegister);
437 ASSERT(rn != kNoRegister);
438 ASSERT(rm != kNoRegister);
439 ASSERT(cond != kNoCondition);
440 int32_t encoding = opcode |
441 (static_cast<int32_t>(cond) << kConditionShift) |
442 (static_cast<int32_t>(rn) << kDivRnShift) |
443 (static_cast<int32_t>(rd) << kDivRdShift) |
444 B26 | B25 | B24 | B20 | B4 |
445 (static_cast<int32_t>(rm) << kDivRmShift);
446 Emit(encoding);
447}
448
449
450void Assembler::sdiv(Register rd, Register rn, Register rm, Condition cond) {
451 EmitDivOp(cond, 0, rd, rn, rm);
452}
453
454
455void Assembler::udiv(Register rd, Register rn, Register rm, Condition cond) {
456 EmitDivOp(cond, B21 , rd, rn, rm);
457}
458
459
460void Assembler::ldr(Register rd, Address ad, Condition cond) {
461 EmitMemOp(cond, true, false, rd, ad);
462}
463
464
465void Assembler::str(Register rd, Address ad, Condition cond) {
466 EmitMemOp(cond, false, false, rd, ad);
467}
468
469
470void Assembler::ldrb(Register rd, Address ad, Condition cond) {
471 EmitMemOp(cond, true, true, rd, ad);
472}
473
474
475void Assembler::strb(Register rd, Address ad, Condition cond) {
476 EmitMemOp(cond, false, true, rd, ad);
477}
478
479
480void Assembler::ldrh(Register rd, Address ad, Condition cond) {
481 EmitMemOpAddressMode3(cond, L | B7 | H | B4, rd, ad);
482}
483
484
485void Assembler::strh(Register rd, Address ad, Condition cond) {
486 EmitMemOpAddressMode3(cond, B7 | H | B4, rd, ad);
487}
488
489
490void Assembler::ldrsb(Register rd, Address ad, Condition cond) {
491 EmitMemOpAddressMode3(cond, L | B7 | B6 | B4, rd, ad);
492}
493
494
495void Assembler::ldrsh(Register rd, Address ad, Condition cond) {
496 EmitMemOpAddressMode3(cond, L | B7 | B6 | H | B4, rd, ad);
497}
498
499
500void Assembler::ldrd(Register rd, Register rn, int32_t offset, Condition cond) {
501 ASSERT((rd % 2) == 0);
502 if (TargetCPUFeatures::arm_version() == ARMv5TE) {
503 const Register rd2 = static_cast<Register>(static_cast<int32_t>(rd) + 1);
504 ldr(rd, Address(rn, offset), cond);
505 ldr(rd2, Address(rn, offset + kWordSize), cond);
506 } else {
507 EmitMemOpAddressMode3(cond, B7 | B6 | B4, rd, Address(rn, offset));
508 }
509}
510
511
512void Assembler::strd(Register rd, Register rn, int32_t offset, Condition cond) {
513 ASSERT((rd % 2) == 0);
514 if (TargetCPUFeatures::arm_version() == ARMv5TE) {
515 const Register rd2 = static_cast<Register>(static_cast<int32_t>(rd) + 1);
516 str(rd, Address(rn, offset), cond);
517 str(rd2, Address(rn, offset + kWordSize), cond);
518 } else {
519 EmitMemOpAddressMode3(cond, B7 | B6 | B5 | B4, rd, Address(rn, offset));
520 }
521}
522
523
524void Assembler::ldm(BlockAddressMode am, Register base, RegList regs,
525 Condition cond) {
526 ASSERT(regs != 0);
527 EmitMultiMemOp(cond, am, true, base, regs);
528}
529
530
531void Assembler::stm(BlockAddressMode am, Register base, RegList regs,
532 Condition cond) {
533 ASSERT(regs != 0);
534 EmitMultiMemOp(cond, am, false, base, regs);
535}
536
537
538void Assembler::ldrex(Register rt, Register rn, Condition cond) {
539 ASSERT(TargetCPUFeatures::arm_version() != ARMv5TE);
540 ASSERT(rn != kNoRegister);
541 ASSERT(rt != kNoRegister);
542 ASSERT(cond != kNoCondition);
543 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
544 B24 |
545 B23 |
546 L |
547 (static_cast<int32_t>(rn) << kLdExRnShift) |
548 (static_cast<int32_t>(rt) << kLdExRtShift) |
549 B11 | B10 | B9 | B8 | B7 | B4 | B3 | B2 | B1 | B0;
550 Emit(encoding);
551}
552
553
554void Assembler::strex(Register rd, Register rt, Register rn, Condition cond) {
555 ASSERT(TargetCPUFeatures::arm_version() != ARMv5TE);
556 ASSERT(rn != kNoRegister);
557 ASSERT(rd != kNoRegister);
558 ASSERT(rt != kNoRegister);
559 ASSERT(cond != kNoCondition);
560 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
561 B24 |
562 B23 |
563 (static_cast<int32_t>(rn) << kStrExRnShift) |
564 (static_cast<int32_t>(rd) << kStrExRdShift) |
565 B11 | B10 | B9 | B8 | B7 | B4 |
566 (static_cast<int32_t>(rt) << kStrExRtShift);
567 Emit(encoding);
568}
569
570
571void Assembler::clrex() {
572 ASSERT(TargetCPUFeatures::arm_version() != ARMv5TE);
573 int32_t encoding = (kSpecialCondition << kConditionShift) |
574 B26 | B24 | B22 | B21 | B20 | (0xff << 12) | B4 | 0xf;
575 Emit(encoding);
576}
577
578
579void Assembler::nop(Condition cond) {
580 ASSERT(cond != kNoCondition);
581 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
582 B25 | B24 | B21 | (0xf << 12);
583 Emit(encoding);
584}
585
586
587void Assembler::vmovsr(SRegister sn, Register rt, Condition cond) {
588 ASSERT(TargetCPUFeatures::vfp_supported());
589 ASSERT(sn != kNoSRegister);
590 ASSERT(rt != kNoRegister);
591 ASSERT(rt != SP);
592 ASSERT(rt != PC);
593 ASSERT(cond != kNoCondition);
594 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
595 B27 | B26 | B25 |
596 ((static_cast<int32_t>(sn) >> 1)*B16) |
597 (static_cast<int32_t>(rt)*B12) | B11 | B9 |
598 ((static_cast<int32_t>(sn) & 1)*B7) | B4;
599 Emit(encoding);
600}
601
602
603void Assembler::vmovrs(Register rt, SRegister sn, Condition cond) {
604 ASSERT(TargetCPUFeatures::vfp_supported());
605 ASSERT(sn != kNoSRegister);
606 ASSERT(rt != kNoRegister);
607 ASSERT(rt != SP);
608 ASSERT(rt != PC);
609 ASSERT(cond != kNoCondition);
610 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
611 B27 | B26 | B25 | B20 |
612 ((static_cast<int32_t>(sn) >> 1)*B16) |
613 (static_cast<int32_t>(rt)*B12) | B11 | B9 |
614 ((static_cast<int32_t>(sn) & 1)*B7) | B4;
615 Emit(encoding);
616}
617
618
619void Assembler::vmovsrr(SRegister sm, Register rt, Register rt2,
620 Condition cond) {
621 ASSERT(TargetCPUFeatures::vfp_supported());
622 ASSERT(sm != kNoSRegister);
623 ASSERT(sm != S31);
624 ASSERT(rt != kNoRegister);
625 ASSERT(rt != SP);
626 ASSERT(rt != PC);
627 ASSERT(rt2 != kNoRegister);
628 ASSERT(rt2 != SP);
629 ASSERT(rt2 != PC);
630 ASSERT(cond != kNoCondition);
631 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
632 B27 | B26 | B22 |
633 (static_cast<int32_t>(rt2)*B16) |
634 (static_cast<int32_t>(rt)*B12) | B11 | B9 |
635 ((static_cast<int32_t>(sm) & 1)*B5) | B4 |
636 (static_cast<int32_t>(sm) >> 1);
637 Emit(encoding);
638}
639
640
641void Assembler::vmovrrs(Register rt, Register rt2, SRegister sm,
642 Condition cond) {
643 ASSERT(TargetCPUFeatures::vfp_supported());
644 ASSERT(sm != kNoSRegister);
645 ASSERT(sm != S31);
646 ASSERT(rt != kNoRegister);
647 ASSERT(rt != SP);
648 ASSERT(rt != PC);
649 ASSERT(rt2 != kNoRegister);
650 ASSERT(rt2 != SP);
651 ASSERT(rt2 != PC);
652 ASSERT(rt != rt2);
653 ASSERT(cond != kNoCondition);
654 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
655 B27 | B26 | B22 | B20 |
656 (static_cast<int32_t>(rt2)*B16) |
657 (static_cast<int32_t>(rt)*B12) | B11 | B9 |
658 ((static_cast<int32_t>(sm) & 1)*B5) | B4 |
659 (static_cast<int32_t>(sm) >> 1);
660 Emit(encoding);
661}
662
663
664void Assembler::vmovdr(DRegister dn, int i, Register rt, Condition cond) {
665 ASSERT(TargetCPUFeatures::vfp_supported());
666 ASSERT((i == 0) || (i == 1));
667 ASSERT(rt != kNoRegister);
668 ASSERT(rt != SP);
669 ASSERT(rt != PC);
670 ASSERT(dn != kNoDRegister);
671 ASSERT(cond != kNoCondition);
672 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
673 B27 | B26 | B25 |
674 (i*B21) |
675 (static_cast<int32_t>(rt)*B12) | B11 | B9 | B8 |
676 ((static_cast<int32_t>(dn) >> 4)*B7) |
677 ((static_cast<int32_t>(dn) & 0xf)*B16) | B4;
678 Emit(encoding);
679}
680
681
682void Assembler::vmovdrr(DRegister dm, Register rt, Register rt2,
683 Condition cond) {
684 ASSERT(TargetCPUFeatures::vfp_supported());
685 ASSERT(dm != kNoDRegister);
686 ASSERT(rt != kNoRegister);
687 ASSERT(rt != SP);
688 ASSERT(rt != PC);
689 ASSERT(rt2 != kNoRegister);
690 ASSERT(rt2 != SP);
691 ASSERT(rt2 != PC);
692 ASSERT(cond != kNoCondition);
693 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
694 B27 | B26 | B22 |
695 (static_cast<int32_t>(rt2)*B16) |
696 (static_cast<int32_t>(rt)*B12) | B11 | B9 | B8 |
697 ((static_cast<int32_t>(dm) >> 4)*B5) | B4 |
698 (static_cast<int32_t>(dm) & 0xf);
699 Emit(encoding);
700}
701
702
703void Assembler::vmovrrd(Register rt, Register rt2, DRegister dm,
704 Condition cond) {
705 ASSERT(TargetCPUFeatures::vfp_supported());
706 ASSERT(dm != kNoDRegister);
707 ASSERT(rt != kNoRegister);
708 ASSERT(rt != SP);
709 ASSERT(rt != PC);
710 ASSERT(rt2 != kNoRegister);
711 ASSERT(rt2 != SP);
712 ASSERT(rt2 != PC);
713 ASSERT(rt != rt2);
714 ASSERT(cond != kNoCondition);
715 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
716 B27 | B26 | B22 | B20 |
717 (static_cast<int32_t>(rt2)*B16) |
718 (static_cast<int32_t>(rt)*B12) | B11 | B9 | B8 |
719 ((static_cast<int32_t>(dm) >> 4)*B5) | B4 |
720 (static_cast<int32_t>(dm) & 0xf);
721 Emit(encoding);
722}
723
724
725void Assembler::vldrs(SRegister sd, Address ad, Condition cond) {
726 ASSERT(TargetCPUFeatures::vfp_supported());
727 ASSERT(sd != kNoSRegister);
728 ASSERT(cond != kNoCondition);
729 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
730 B27 | B26 | B24 | B20 |
731 ((static_cast<int32_t>(sd) & 1)*B22) |
732 ((static_cast<int32_t>(sd) >> 1)*B12) |
733 B11 | B9 | ad.vencoding();
734 Emit(encoding);
735}
736
737
738void Assembler::vstrs(SRegister sd, Address ad, Condition cond) {
739 ASSERT(TargetCPUFeatures::vfp_supported());
740 ASSERT(static_cast<Register>(ad.encoding_ & (0xf << kRnShift)) != PC);
741 ASSERT(sd != kNoSRegister);
742 ASSERT(cond != kNoCondition);
743 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
744 B27 | B26 | B24 |
745 ((static_cast<int32_t>(sd) & 1)*B22) |
746 ((static_cast<int32_t>(sd) >> 1)*B12) |
747 B11 | B9 | ad.vencoding();
748 Emit(encoding);
749}
750
751
752void Assembler::vldrd(DRegister dd, Address ad, Condition cond) {
753 ASSERT(TargetCPUFeatures::vfp_supported());
754 ASSERT(dd != kNoDRegister);
755 ASSERT(cond != kNoCondition);
756 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
757 B27 | B26 | B24 | B20 |
758 ((static_cast<int32_t>(dd) >> 4)*B22) |
759 ((static_cast<int32_t>(dd) & 0xf)*B12) |
760 B11 | B9 | B8 | ad.vencoding();
761 Emit(encoding);
762}
763
764
765void Assembler::vstrd(DRegister dd, Address ad, Condition cond) {
766 ASSERT(TargetCPUFeatures::vfp_supported());
767 ASSERT(static_cast<Register>(ad.encoding_ & (0xf << kRnShift)) != PC);
768 ASSERT(dd != kNoDRegister);
769 ASSERT(cond != kNoCondition);
770 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
771 B27 | B26 | B24 |
772 ((static_cast<int32_t>(dd) >> 4)*B22) |
773 ((static_cast<int32_t>(dd) & 0xf)*B12) |
774 B11 | B9 | B8 | ad.vencoding();
775 Emit(encoding);
776}
777
778void Assembler::EmitMultiVSMemOp(Condition cond,
779 BlockAddressMode am,
780 bool load,
781 Register base,
782 SRegister start,
783 uint32_t count) {
784 ASSERT(TargetCPUFeatures::vfp_supported());
785 ASSERT(base != kNoRegister);
786 ASSERT(cond != kNoCondition);
787 ASSERT(start != kNoSRegister);
788 ASSERT(static_cast<int32_t>(start) + count <= kNumberOfSRegisters);
789
790 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
791 B27 | B26 | B11 | B9 |
792 am |
793 (load ? L : 0) |
794 (static_cast<int32_t>(base) << kRnShift) |
795 ((static_cast<int32_t>(start) & 0x1) ? D : 0) |
796 ((static_cast<int32_t>(start) >> 1) << 12) |
797 count;
798 Emit(encoding);
799}
800
801
802void Assembler::EmitMultiVDMemOp(Condition cond,
803 BlockAddressMode am,
804 bool load,
805 Register base,
806 DRegister start,
807 int32_t count) {
808 ASSERT(TargetCPUFeatures::vfp_supported());
809 ASSERT(base != kNoRegister);
810 ASSERT(cond != kNoCondition);
811 ASSERT(start != kNoDRegister);
812 ASSERT(static_cast<int32_t>(start) + count <= kNumberOfDRegisters);
813 const int armv5te = TargetCPUFeatures::arm_version() == ARMv5TE ? 1 : 0;
814
815 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
816 B27 | B26 | B11 | B9 | B8 |
817 am |
818 (load ? L : 0) |
819 (static_cast<int32_t>(base) << kRnShift) |
820 ((static_cast<int32_t>(start) & 0x10) ? D : 0) |
821 ((static_cast<int32_t>(start) & 0xf) << 12) |
822 (count << 1) | armv5te;
823 Emit(encoding);
824}
825
826
827void Assembler::vldms(BlockAddressMode am, Register base,
828 SRegister first, SRegister last, Condition cond) {
829 ASSERT((am == IA) || (am == IA_W) || (am == DB_W));
830 ASSERT(last > first);
831 EmitMultiVSMemOp(cond, am, true, base, first, last - first + 1);
832}
833
834
835void Assembler::vstms(BlockAddressMode am, Register base,
836 SRegister first, SRegister last, Condition cond) {
837 ASSERT((am == IA) || (am == IA_W) || (am == DB_W));
838 ASSERT(last > first);
839 EmitMultiVSMemOp(cond, am, false, base, first, last - first + 1);
840}
841
842
843void Assembler::vldmd(BlockAddressMode am, Register base,
844 DRegister first, intptr_t count, Condition cond) {
845 ASSERT((am == IA) || (am == IA_W) || (am == DB_W));
846 ASSERT(count <= 16);
847 ASSERT(first + count <= kNumberOfDRegisters);
848 EmitMultiVDMemOp(cond, am, true, base, first, count);
849}
850
851
852void Assembler::vstmd(BlockAddressMode am, Register base,
853 DRegister first, intptr_t count, Condition cond) {
854 ASSERT((am == IA) || (am == IA_W) || (am == DB_W));
855 ASSERT(count <= 16);
856 ASSERT(first + count <= kNumberOfDRegisters);
857 EmitMultiVDMemOp(cond, am, false, base, first, count);
858}
859
860
861void Assembler::EmitVFPsss(Condition cond, int32_t opcode,
862 SRegister sd, SRegister sn, SRegister sm) {
863 ASSERT(TargetCPUFeatures::vfp_supported());
864 ASSERT(sd != kNoSRegister);
865 ASSERT(sn != kNoSRegister);
866 ASSERT(sm != kNoSRegister);
867 ASSERT(cond != kNoCondition);
868 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
869 B27 | B26 | B25 | B11 | B9 | opcode |
870 ((static_cast<int32_t>(sd) & 1)*B22) |
871 ((static_cast<int32_t>(sn) >> 1)*B16) |
872 ((static_cast<int32_t>(sd) >> 1)*B12) |
873 ((static_cast<int32_t>(sn) & 1)*B7) |
874 ((static_cast<int32_t>(sm) & 1)*B5) |
875 (static_cast<int32_t>(sm) >> 1);
876 Emit(encoding);
877}
878
879
880void Assembler::EmitVFPddd(Condition cond, int32_t opcode,
881 DRegister dd, DRegister dn, DRegister dm) {
882 ASSERT(TargetCPUFeatures::vfp_supported());
883 ASSERT(dd != kNoDRegister);
884 ASSERT(dn != kNoDRegister);
885 ASSERT(dm != kNoDRegister);
886 ASSERT(cond != kNoCondition);
887 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
888 B27 | B26 | B25 | B11 | B9 | B8 | opcode |
889 ((static_cast<int32_t>(dd) >> 4)*B22) |
890 ((static_cast<int32_t>(dn) & 0xf)*B16) |
891 ((static_cast<int32_t>(dd) & 0xf)*B12) |
892 ((static_cast<int32_t>(dn) >> 4)*B7) |
893 ((static_cast<int32_t>(dm) >> 4)*B5) |
894 (static_cast<int32_t>(dm) & 0xf);
895 Emit(encoding);
896}
897
898
899void Assembler::vmovs(SRegister sd, SRegister sm, Condition cond) {
900 EmitVFPsss(cond, B23 | B21 | B20 | B6, sd, S0, sm);
901}
902
903
904void Assembler::vmovd(DRegister dd, DRegister dm, Condition cond) {
905 EmitVFPddd(cond, B23 | B21 | B20 | B6, dd, D0, dm);
906}
907
908
909bool Assembler::vmovs(SRegister sd, float s_imm, Condition cond) {
910 if (TargetCPUFeatures::arm_version() != ARMv7) {
911 return false;
912 }
913 uint32_t imm32 = bit_cast<uint32_t, float>(s_imm);
914 if (((imm32 & ((1 << 19) - 1)) == 0) &&
915 ((((imm32 >> 25) & ((1 << 6) - 1)) == (1 << 5)) ||
916 (((imm32 >> 25) & ((1 << 6) - 1)) == ((1 << 5) -1)))) {
917 uint8_t imm8 = ((imm32 >> 31) << 7) | (((imm32 >> 29) & 1) << 6) |
918 ((imm32 >> 19) & ((1 << 6) -1));
919 EmitVFPsss(cond, B23 | B21 | B20 | ((imm8 >> 4)*B16) | (imm8 & 0xf),
920 sd, S0, S0);
921 return true;
922 }
923 return false;
924}
925
926
927bool Assembler::vmovd(DRegister dd, double d_imm, Condition cond) {
928 if (TargetCPUFeatures::arm_version() != ARMv7) {
929 return false;
930 }
931 uint64_t imm64 = bit_cast<uint64_t, double>(d_imm);
932 if (((imm64 & ((1LL << 48) - 1)) == 0) &&
933 ((((imm64 >> 54) & ((1 << 9) - 1)) == (1 << 8)) ||
934 (((imm64 >> 54) & ((1 << 9) - 1)) == ((1 << 8) -1)))) {
935 uint8_t imm8 = ((imm64 >> 63) << 7) | (((imm64 >> 61) & 1) << 6) |
936 ((imm64 >> 48) & ((1 << 6) -1));
937 EmitVFPddd(cond, B23 | B21 | B20 | ((imm8 >> 4)*B16) | B8 | (imm8 & 0xf),
938 dd, D0, D0);
939 return true;
940 }
941 return false;
942}
943
944
945void Assembler::vadds(SRegister sd, SRegister sn, SRegister sm,
946 Condition cond) {
947 EmitVFPsss(cond, B21 | B20, sd, sn, sm);
948}
949
950
951void Assembler::vaddd(DRegister dd, DRegister dn, DRegister dm,
952 Condition cond) {
953 EmitVFPddd(cond, B21 | B20, dd, dn, dm);
954}
955
956
957void Assembler::vsubs(SRegister sd, SRegister sn, SRegister sm,
958 Condition cond) {
959 EmitVFPsss(cond, B21 | B20 | B6, sd, sn, sm);
960}
961
962
963void Assembler::vsubd(DRegister dd, DRegister dn, DRegister dm,
964 Condition cond) {
965 EmitVFPddd(cond, B21 | B20 | B6, dd, dn, dm);
966}
967
968
969void Assembler::vmuls(SRegister sd, SRegister sn, SRegister sm,
970 Condition cond) {
971 EmitVFPsss(cond, B21, sd, sn, sm);
972}
973
974
975void Assembler::vmuld(DRegister dd, DRegister dn, DRegister dm,
976 Condition cond) {
977 EmitVFPddd(cond, B21, dd, dn, dm);
978}
979
980
981void Assembler::vmlas(SRegister sd, SRegister sn, SRegister sm,
982 Condition cond) {
983 EmitVFPsss(cond, 0, sd, sn, sm);
984}
985
986
987void Assembler::vmlad(DRegister dd, DRegister dn, DRegister dm,
988 Condition cond) {
989 EmitVFPddd(cond, 0, dd, dn, dm);
990}
991
992
993void Assembler::vmlss(SRegister sd, SRegister sn, SRegister sm,
994 Condition cond) {
995 EmitVFPsss(cond, B6, sd, sn, sm);
996}
997
998
999void Assembler::vmlsd(DRegister dd, DRegister dn, DRegister dm,
1000 Condition cond) {
1001 EmitVFPddd(cond, B6, dd, dn, dm);
1002}
1003
1004
1005void Assembler::vdivs(SRegister sd, SRegister sn, SRegister sm,
1006 Condition cond) {
1007 EmitVFPsss(cond, B23, sd, sn, sm);
1008}
1009
1010
1011void Assembler::vdivd(DRegister dd, DRegister dn, DRegister dm,
1012 Condition cond) {
1013 EmitVFPddd(cond, B23, dd, dn, dm);
1014}
1015
1016
1017void Assembler::vabss(SRegister sd, SRegister sm, Condition cond) {
1018 EmitVFPsss(cond, B23 | B21 | B20 | B7 | B6, sd, S0, sm);
1019}
1020
1021
1022void Assembler::vabsd(DRegister dd, DRegister dm, Condition cond) {
1023 EmitVFPddd(cond, B23 | B21 | B20 | B7 | B6, dd, D0, dm);
1024}
1025
1026
1027void Assembler::vnegs(SRegister sd, SRegister sm, Condition cond) {
1028 EmitVFPsss(cond, B23 | B21 | B20 | B16 | B6, sd, S0, sm);
1029}
1030
1031
1032void Assembler::vnegd(DRegister dd, DRegister dm, Condition cond) {
1033 EmitVFPddd(cond, B23 | B21 | B20 | B16 | B6, dd, D0, dm);
1034}
1035
1036
1037void Assembler::vsqrts(SRegister sd, SRegister sm, Condition cond) {
1038 EmitVFPsss(cond, B23 | B21 | B20 | B16 | B7 | B6, sd, S0, sm);
1039}
1040
1041void Assembler::vsqrtd(DRegister dd, DRegister dm, Condition cond) {
1042 EmitVFPddd(cond, B23 | B21 | B20 | B16 | B7 | B6, dd, D0, dm);
1043}
1044
1045
1046void Assembler::EmitVFPsd(Condition cond, int32_t opcode,
1047 SRegister sd, DRegister dm) {
1048 ASSERT(TargetCPUFeatures::vfp_supported());
1049 ASSERT(sd != kNoSRegister);
1050 ASSERT(dm != kNoDRegister);
1051 ASSERT(cond != kNoCondition);
1052 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
1053 B27 | B26 | B25 | B11 | B9 | opcode |
1054 ((static_cast<int32_t>(sd) & 1)*B22) |
1055 ((static_cast<int32_t>(sd) >> 1)*B12) |
1056 ((static_cast<int32_t>(dm) >> 4)*B5) |
1057 (static_cast<int32_t>(dm) & 0xf);
1058 Emit(encoding);
1059}
1060
1061
1062void Assembler::EmitVFPds(Condition cond, int32_t opcode,
1063 DRegister dd, SRegister sm) {
1064 ASSERT(TargetCPUFeatures::vfp_supported());
1065 ASSERT(dd != kNoDRegister);
1066 ASSERT(sm != kNoSRegister);
1067 ASSERT(cond != kNoCondition);
1068 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
1069 B27 | B26 | B25 | B11 | B9 | opcode |
1070 ((static_cast<int32_t>(dd) >> 4)*B22) |
1071 ((static_cast<int32_t>(dd) & 0xf)*B12) |
1072 ((static_cast<int32_t>(sm) & 1)*B5) |
1073 (static_cast<int32_t>(sm) >> 1);
1074 Emit(encoding);
1075}
1076
1077
1078void Assembler::vcvtsd(SRegister sd, DRegister dm, Condition cond) {
1079 EmitVFPsd(cond, B23 | B21 | B20 | B18 | B17 | B16 | B8 | B7 | B6, sd, dm);
1080}
1081
1082
1083void Assembler::vcvtds(DRegister dd, SRegister sm, Condition cond) {
1084 EmitVFPds(cond, B23 | B21 | B20 | B18 | B17 | B16 | B7 | B6, dd, sm);
1085}
1086
1087
1088void Assembler::vcvtis(SRegister sd, SRegister sm, Condition cond) {
1089 EmitVFPsss(cond, B23 | B21 | B20 | B19 | B18 | B16 | B7 | B6, sd, S0, sm);
1090}
1091
1092
1093void Assembler::vcvtid(SRegister sd, DRegister dm, Condition cond) {
1094 EmitVFPsd(cond, B23 | B21 | B20 | B19 | B18 | B16 | B8 | B7 | B6, sd, dm);
1095}
1096
1097
1098void Assembler::vcvtsi(SRegister sd, SRegister sm, Condition cond) {
1099 EmitVFPsss(cond, B23 | B21 | B20 | B19 | B7 | B6, sd, S0, sm);
1100}
1101
1102
1103void Assembler::vcvtdi(DRegister dd, SRegister sm, Condition cond) {
1104 EmitVFPds(cond, B23 | B21 | B20 | B19 | B8 | B7 | B6, dd, sm);
1105}
1106
1107
1108void Assembler::vcvtus(SRegister sd, SRegister sm, Condition cond) {
1109 EmitVFPsss(cond, B23 | B21 | B20 | B19 | B18 | B7 | B6, sd, S0, sm);
1110}
1111
1112
1113void Assembler::vcvtud(SRegister sd, DRegister dm, Condition cond) {
1114 EmitVFPsd(cond, B23 | B21 | B20 | B19 | B18 | B8 | B7 | B6, sd, dm);
1115}
1116
1117
1118void Assembler::vcvtsu(SRegister sd, SRegister sm, Condition cond) {
1119 EmitVFPsss(cond, B23 | B21 | B20 | B19 | B6, sd, S0, sm);
1120}
1121
1122
1123void Assembler::vcvtdu(DRegister dd, SRegister sm, Condition cond) {
1124 EmitVFPds(cond, B23 | B21 | B20 | B19 | B8 | B6, dd, sm);
1125}
1126
1127
1128void Assembler::vcmps(SRegister sd, SRegister sm, Condition cond) {
1129 EmitVFPsss(cond, B23 | B21 | B20 | B18 | B6, sd, S0, sm);
1130}
1131
1132
1133void Assembler::vcmpd(DRegister dd, DRegister dm, Condition cond) {
1134 EmitVFPddd(cond, B23 | B21 | B20 | B18 | B6, dd, D0, dm);
1135}
1136
1137
1138void Assembler::vcmpsz(SRegister sd, Condition cond) {
1139 EmitVFPsss(cond, B23 | B21 | B20 | B18 | B16 | B6, sd, S0, S0);
1140}
1141
1142
1143void Assembler::vcmpdz(DRegister dd, Condition cond) {
1144 EmitVFPddd(cond, B23 | B21 | B20 | B18 | B16 | B6, dd, D0, D0);
1145}
1146
1147
1148void Assembler::vmrs(Register rd, Condition cond) {
1149 ASSERT(TargetCPUFeatures::vfp_supported());
1150 ASSERT(cond != kNoCondition);
1151 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
1152 B27 | B26 | B25 | B23 | B22 | B21 | B20 | B16 |
1153 (static_cast<int32_t>(rd)*B12) |
1154 B11 | B9 | B4;
1155 Emit(encoding);
1156}
1157
1158
1159void Assembler::vmstat(Condition cond) {
1160 vmrs(APSR, cond);
1161}
1162
1163
1164static inline int ShiftOfOperandSize(OperandSize size) {
1165 switch (size) {
1166 case kByte:
1167 case kUnsignedByte:
1168 return 0;
1169 case kHalfword:
1170 case kUnsignedHalfword:
1171 return 1;
1172 case kWord:
1173 case kUnsignedWord:
1174 return 2;
1175 case kWordPair:
1176 return 3;
1177 case kSWord:
1178 case kDWord:
1179 return 0;
1180 default:
1181 UNREACHABLE();
1182 break;
1183 }
1184
1185 UNREACHABLE();
1186 return -1;
1187}
1188
1189
1190void Assembler::EmitSIMDqqq(int32_t opcode, OperandSize size,
1191 QRegister qd, QRegister qn, QRegister qm) {
1192 ASSERT(TargetCPUFeatures::neon_supported());
1193 int sz = ShiftOfOperandSize(size);
1194 int32_t encoding =
1195 (static_cast<int32_t>(kSpecialCondition) << kConditionShift) |
1196 B25 | B6 |
1197 opcode | ((sz & 0x3) * B20) |
1198 ((static_cast<int32_t>(qd * 2) >> 4)*B22) |
1199 ((static_cast<int32_t>(qn * 2) & 0xf)*B16) |
1200 ((static_cast<int32_t>(qd * 2) & 0xf)*B12) |
1201 ((static_cast<int32_t>(qn * 2) >> 4)*B7) |
1202 ((static_cast<int32_t>(qm * 2) >> 4)*B5) |
1203 (static_cast<int32_t>(qm * 2) & 0xf);
1204 Emit(encoding);
1205}
1206
1207
1208void Assembler::EmitSIMDddd(int32_t opcode, OperandSize size,
1209 DRegister dd, DRegister dn, DRegister dm) {
1210 ASSERT(TargetCPUFeatures::neon_supported());
1211 int sz = ShiftOfOperandSize(size);
1212 int32_t encoding =
1213 (static_cast<int32_t>(kSpecialCondition) << kConditionShift) |
1214 B25 |
1215 opcode | ((sz & 0x3) * B20) |
1216 ((static_cast<int32_t>(dd) >> 4)*B22) |
1217 ((static_cast<int32_t>(dn) & 0xf)*B16) |
1218 ((static_cast<int32_t>(dd) & 0xf)*B12) |
1219 ((static_cast<int32_t>(dn) >> 4)*B7) |
1220 ((static_cast<int32_t>(dm) >> 4)*B5) |
1221 (static_cast<int32_t>(dm) & 0xf);
1222 Emit(encoding);
1223}
1224
1225
1226void Assembler::vmovq(QRegister qd, QRegister qm) {
1227 EmitSIMDqqq(B21 | B8 | B4, kByte, qd, qm, qm);
1228}
1229
1230
1231void Assembler::vaddqi(OperandSize sz,
1232 QRegister qd, QRegister qn, QRegister qm) {
1233 EmitSIMDqqq(B11, sz, qd, qn, qm);
1234}
1235
1236
1237void Assembler::vaddqs(QRegister qd, QRegister qn, QRegister qm) {
1238 EmitSIMDqqq(B11 | B10 | B8, kSWord, qd, qn, qm);
1239}
1240
1241
1242void Assembler::vsubqi(OperandSize sz,
1243 QRegister qd, QRegister qn, QRegister qm) {
1244 EmitSIMDqqq(B24 | B11, sz, qd, qn, qm);
1245}
1246
1247
1248void Assembler::vsubqs(QRegister qd, QRegister qn, QRegister qm) {
1249 EmitSIMDqqq(B21 | B11 | B10 | B8, kSWord, qd, qn, qm);
1250}
1251
1252
1253void Assembler::vmulqi(OperandSize sz,
1254 QRegister qd, QRegister qn, QRegister qm) {
1255 EmitSIMDqqq(B11 | B8 | B4, sz, qd, qn, qm);
1256}
1257
1258
1259void Assembler::vmulqs(QRegister qd, QRegister qn, QRegister qm) {
1260 EmitSIMDqqq(B24 | B11 | B10 | B8 | B4, kSWord, qd, qn, qm);
1261}
1262
1263
1264void Assembler::vshlqi(OperandSize sz,
1265 QRegister qd, QRegister qm, QRegister qn) {
1266 EmitSIMDqqq(B25 | B10, sz, qd, qn, qm);
1267}
1268
1269
1270void Assembler::vshlqu(OperandSize sz,
1271 QRegister qd, QRegister qm, QRegister qn) {
1272 EmitSIMDqqq(B25 | B24 | B10, sz, qd, qn, qm);
1273}
1274
1275
1276void Assembler::veorq(QRegister qd, QRegister qn, QRegister qm) {
1277 EmitSIMDqqq(B24 | B8 | B4, kByte, qd, qn, qm);
1278}
1279
1280
1281void Assembler::vorrq(QRegister qd, QRegister qn, QRegister qm) {
1282 EmitSIMDqqq(B21 | B8 | B4, kByte, qd, qn, qm);
1283}
1284
1285
1286void Assembler::vornq(QRegister qd, QRegister qn, QRegister qm) {
1287 EmitSIMDqqq(B21 | B20 | B8 | B4, kByte, qd, qn, qm);
1288}
1289
1290
1291void Assembler::vandq(QRegister qd, QRegister qn, QRegister qm) {
1292 EmitSIMDqqq(B8 | B4, kByte, qd, qn, qm);
1293}
1294
1295
1296void Assembler::vmvnq(QRegister qd, QRegister qm) {
1297 EmitSIMDqqq(B25 | B24 | B23 | B10 | B8 | B7, kWordPair, qd, Q0, qm);
1298}
1299
1300
1301void Assembler::vminqs(QRegister qd, QRegister qn, QRegister qm) {
1302 EmitSIMDqqq(B21 | B11 | B10 | B9 | B8, kSWord, qd, qn, qm);
1303}
1304
1305
1306void Assembler::vmaxqs(QRegister qd, QRegister qn, QRegister qm) {
1307 EmitSIMDqqq(B11 | B10 | B9 | B8, kSWord, qd, qn, qm);
1308}
1309
1310
1311void Assembler::vabsqs(QRegister qd, QRegister qm) {
1312 EmitSIMDqqq(B24 | B23 | B21 | B20 | B19 | B16 | B10 | B9 | B8, kSWord,
1313 qd, Q0, qm);
1314}
1315
1316
1317void Assembler::vnegqs(QRegister qd, QRegister qm) {
1318 EmitSIMDqqq(B24 | B23 | B21 | B20 | B19 | B16 | B10 | B9 | B8 | B7, kSWord,
1319 qd, Q0, qm);
1320}
1321
1322
1323void Assembler::vrecpeqs(QRegister qd, QRegister qm) {
1324 EmitSIMDqqq(B24 | B23 | B21 | B20 | B19 | B17 | B16 | B10 | B8, kSWord,
1325 qd, Q0, qm);
1326}
1327
1328
1329void Assembler::vrecpsqs(QRegister qd, QRegister qn, QRegister qm) {
1330 EmitSIMDqqq(B11 | B10 | B9 | B8 | B4, kSWord, qd, qn, qm);
1331}
1332
1333
1334void Assembler::vrsqrteqs(QRegister qd, QRegister qm) {
1335 EmitSIMDqqq(B24 | B23 | B21 | B20 | B19 | B17 | B16 | B10 | B8 | B7,
1336 kSWord, qd, Q0, qm);
1337}
1338
1339
1340void Assembler::vrsqrtsqs(QRegister qd, QRegister qn, QRegister qm) {
1341 EmitSIMDqqq(B21 | B11 | B10 | B9 | B8 | B4, kSWord, qd, qn, qm);
1342}
1343
1344
1345void Assembler::vdup(OperandSize sz, QRegister qd, DRegister dm, int idx) {
1346 ASSERT((sz != kDWord) && (sz != kSWord) && (sz != kWordPair));
1347 int code = 0;
1348
1349 switch (sz) {
1350 case kByte:
1351 case kUnsignedByte: {
1352 ASSERT((idx >= 0) && (idx < 8));
1353 code = 1 | (idx << 1);
1354 break;
1355 }
1356 case kHalfword:
1357 case kUnsignedHalfword: {
1358 ASSERT((idx >= 0) && (idx < 4));
1359 code = 2 | (idx << 2);
1360 break;
1361 }
1362 case kWord:
1363 case kUnsignedWord: {
1364 ASSERT((idx >= 0) && (idx < 2));
1365 code = 4 | (idx << 3);
1366 break;
1367 }
1368 default: {
1369 break;
1370 }
1371 }
1372
1373 EmitSIMDddd(B24 | B23 | B11 | B10 | B6, kWordPair,
1374 static_cast<DRegister>(qd * 2),
1375 static_cast<DRegister>(code & 0xf),
1376 dm);
1377}
1378
1379
1380void Assembler::vtbl(DRegister dd, DRegister dn, int len, DRegister dm) {
1381 ASSERT((len >= 1) && (len <= 4));
1382 EmitSIMDddd(B24 | B23 | B11 | ((len - 1) * B8), kWordPair, dd, dn, dm);
1383}
1384
1385
1386void Assembler::vzipqw(QRegister qd, QRegister qm) {
1387 EmitSIMDqqq(B24 | B23 | B21 | B20 | B19 | B17 | B8 | B7, kByte, qd, Q0, qm);
1388}
1389
1390
1391void Assembler::vceqqi(OperandSize sz,
1392 QRegister qd, QRegister qn, QRegister qm) {
1393 EmitSIMDqqq(B24 | B11 | B4, sz, qd, qn, qm);
1394}
1395
1396
1397void Assembler::vceqqs(QRegister qd, QRegister qn, QRegister qm) {
1398 EmitSIMDqqq(B11 | B10 | B9, kSWord, qd, qn, qm);
1399}
1400
1401
1402void Assembler::vcgeqi(OperandSize sz,
1403 QRegister qd, QRegister qn, QRegister qm) {
1404 EmitSIMDqqq(B9 | B8 | B4, sz, qd, qn, qm);
1405}
1406
1407
1408void Assembler::vcugeqi(OperandSize sz,
1409 QRegister qd, QRegister qn, QRegister qm) {
1410 EmitSIMDqqq(B24 | B9 | B8 | B4, sz, qd, qn, qm);
1411}
1412
1413
1414void Assembler::vcgeqs(QRegister qd, QRegister qn, QRegister qm) {
1415 EmitSIMDqqq(B24 | B11 | B10 | B9, kSWord, qd, qn, qm);
1416}
1417
1418
1419void Assembler::vcgtqi(OperandSize sz,
1420 QRegister qd, QRegister qn, QRegister qm) {
1421 EmitSIMDqqq(B9 | B8, sz, qd, qn, qm);
1422}
1423
1424
1425void Assembler::vcugtqi(OperandSize sz,
1426 QRegister qd, QRegister qn, QRegister qm) {
1427 EmitSIMDqqq(B24 | B9 | B8, sz, qd, qn, qm);
1428}
1429
1430
1431void Assembler::vcgtqs(QRegister qd, QRegister qn, QRegister qm) {
1432 EmitSIMDqqq(B24 | B21 | B11 | B10 | B9, kSWord, qd, qn, qm);
1433}
1434
1435
1436void Assembler::bkpt(uint16_t imm16) {
1437 Emit(BkptEncoding(imm16));
1438}
1439
1440
1441void Assembler::b(Label* label, Condition cond) {
1442 EmitBranch(cond, label, false);
1443}
1444
1445
1446void Assembler::bl(Label* label, Condition cond) {
1447 EmitBranch(cond, label, true);
1448}
1449
1450
1451void Assembler::bx(Register rm, Condition cond) {
1452 ASSERT(rm != kNoRegister);
1453 ASSERT(cond != kNoCondition);
1454 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
1455 B24 | B21 | (0xfff << 8) | B4 |
1456 (static_cast<int32_t>(rm) << kRmShift);
1457 Emit(encoding);
1458}
1459
1460
1461void Assembler::blx(Register rm, Condition cond) {
1462 ASSERT(rm != kNoRegister);
1463 ASSERT(cond != kNoCondition);
1464 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
1465 B24 | B21 | (0xfff << 8) | B5 | B4 |
1466 (static_cast<int32_t>(rm) << kRmShift);
1467 Emit(encoding);
1468}
1469
1470
1471void Assembler::MarkExceptionHandler(Label* label) {
1472 EmitType01(AL, 1, TST, 1, PC, R0, Operand(0));
1473 Label l;
1474 b(&l);
1475 EmitBranch(AL, label, false);
1476 Bind(&l);
1477}
1478
1479
1480void Assembler::Drop(intptr_t stack_elements) {
1481 ASSERT(stack_elements >= 0);
1482 if (stack_elements > 0) {
1483 AddImmediate(SP, SP, stack_elements * kWordSize);
1484 }
1485}
1486
1487
1488intptr_t Assembler::FindImmediate(int32_t imm) {
1489 return object_pool_wrapper_.FindImmediate(imm);
1490}
1491
1492
1493// Uses a code sequence that can easily be decoded.
1494void Assembler::LoadWordFromPoolOffset(Register rd,
1495 int32_t offset,
1496 Register pp,
1497 Condition cond) {
1498 ASSERT((pp != PP) || constant_pool_allowed());
1499 ASSERT(rd != pp);
1500 int32_t offset_mask = 0;
1501 if (Address::CanHoldLoadOffset(kWord, offset, &offset_mask)) {
1502 ldr(rd, Address(pp, offset), cond);
1503 } else {
1504 int32_t offset_hi = offset & ~offset_mask; // signed
1505 uint32_t offset_lo = offset & offset_mask; // unsigned
1506 // Inline a simplified version of AddImmediate(rd, pp, offset_hi).
1507 Operand o;
1508 if (Operand::CanHold(offset_hi, &o)) {
1509 add(rd, pp, o, cond);
1510 } else {
1511 LoadImmediate(rd, offset_hi, cond);
1512 add(rd, pp, Operand(rd), cond);
1513 }
1514 ldr(rd, Address(rd, offset_lo), cond);
1515 }
1516}
1517
1518void Assembler::CheckCodePointer() {
1519#ifdef DEBUG
1520 Label cid_ok, instructions_ok;
1521 Push(R0);
1522 Push(IP);
1523 CompareClassId(CODE_REG, kCodeCid, R0);
1524 b(&cid_ok, EQ);
1525 bkpt(0);
1526 Bind(&cid_ok);
1527
1528 const intptr_t offset = CodeSize() + Instr::kPCReadOffset +
1529 Instructions::HeaderSize() - kHeapObjectTag;
1530 mov(R0, Operand(PC));
1531 AddImmediate(R0, R0, -offset);
1532 ldr(IP, FieldAddress(CODE_REG, Code::saved_instructions_offset()));
1533 cmp(R0, Operand(IP));
1534 b(&instructions_ok, EQ);
1535 bkpt(1);
1536 Bind(&instructions_ok);
1537 Pop(IP);
1538 Pop(R0);
1539#endif
1540}
1541
1542
1543void Assembler::RestoreCodePointer() {
1544 ldr(CODE_REG, Address(FP, kPcMarkerSlotFromFp * kWordSize));
1545 CheckCodePointer();
1546}
1547
1548
1549void Assembler::LoadPoolPointer(Register reg) {
1550 // Load new pool pointer.
1551 CheckCodePointer();
1552 ldr(reg, FieldAddress(CODE_REG, Code::object_pool_offset()));
1553 set_constant_pool_allowed(reg == PP);
1554}
1555
1556
1557void Assembler::LoadIsolate(Register rd) {
1558 ldr(rd, Address(THR, Thread::isolate_offset()));
1559}
1560
1561
1562bool Assembler::CanLoadFromObjectPool(const Object& object) const {
1563 ASSERT(!Thread::CanLoadFromThread(object));
1564 if (!constant_pool_allowed()) {
1565 return false;
1566 }
1567
1568 ASSERT(object.IsNotTemporaryScopedHandle());
1569 ASSERT(object.IsOld());
1570 return true;
1571}
1572
1573
1574void Assembler::LoadObjectHelper(Register rd,
1575 const Object& object,
1576 Condition cond,
1577 bool is_unique,
1578 Register pp) {
1579 // Load common VM constants from the thread. This works also in places where
1580 // no constant pool is set up (e.g. intrinsic code).
1581 if (Thread::CanLoadFromThread(object)) {
1582 // Load common VM constants from the thread. This works also in places where
1583 // no constant pool is set up (e.g. intrinsic code).
1584 ldr(rd, Address(THR, Thread::OffsetFromThread(object)), cond);
1585 } else if (object.IsSmi()) {
1586 // Relocation doesn't apply to Smis.
1587 LoadImmediate(rd, reinterpret_cast<int32_t>(object.raw()), cond);
1588 } else if (CanLoadFromObjectPool(object)) {
1589 // Make sure that class CallPattern is able to decode this load from the
1590 // object pool.
1591 const int32_t offset = ObjectPool::element_offset(
1592 is_unique ? object_pool_wrapper_.AddObject(object)
1593 : object_pool_wrapper_.FindObject(object));
1594 LoadWordFromPoolOffset(rd, offset - kHeapObjectTag, pp, cond);
1595 } else {
1596 ASSERT(FLAG_allow_absolute_addresses);
1597 ASSERT(object.IsOld());
1598 // Make sure that class CallPattern is able to decode this load immediate.
1599 const int32_t object_raw = reinterpret_cast<int32_t>(object.raw());
1600 LoadImmediate(rd, object_raw, cond);
1601 }
1602}
1603
1604
1605void Assembler::LoadObject(Register rd, const Object& object, Condition cond) {
1606 LoadObjectHelper(rd, object, cond, /* is_unique = */ false, PP);
1607}
1608
1609
1610void Assembler::LoadUniqueObject(Register rd,
1611 const Object& object,
1612 Condition cond) {
1613 LoadObjectHelper(rd, object, cond, /* is_unique = */ true, PP);
1614}
1615
1616
1617void Assembler::LoadFunctionFromCalleePool(Register dst,
1618 const Function& function,
1619 Register new_pp) {
1620 const int32_t offset =
1621 ObjectPool::element_offset(object_pool_wrapper_.FindObject(function));
1622 LoadWordFromPoolOffset(dst, offset - kHeapObjectTag, new_pp, AL);
1623}
1624
1625
1626void Assembler::LoadNativeEntry(Register rd,
1627 const ExternalLabel* label,
1628 Patchability patchable,
1629 Condition cond) {
1630 const int32_t offset = ObjectPool::element_offset(
1631 object_pool_wrapper_.FindNativeEntry(label, patchable));
1632 LoadWordFromPoolOffset(rd, offset - kHeapObjectTag, PP, cond);
1633}
1634
1635
1636void Assembler::PushObject(const Object& object) {
1637 LoadObject(IP, object);
1638 Push(IP);
1639}
1640
1641
1642void Assembler::CompareObject(Register rn, const Object& object) {
1643 ASSERT(rn != IP);
1644 if (object.IsSmi()) {
1645 CompareImmediate(rn, reinterpret_cast<int32_t>(object.raw()));
1646 } else {
1647 LoadObject(IP, object);
1648 cmp(rn, Operand(IP));
1649 }
1650}
1651
1652
1653// Preserves object and value registers.
1654void Assembler::StoreIntoObjectFilterNoSmi(Register object,
1655 Register value,
1656 Label* no_update) {
1657 COMPILE_ASSERT((kNewObjectAlignmentOffset == kWordSize) &&
1658 (kOldObjectAlignmentOffset == 0));
1659
1660 // Write-barrier triggers if the value is in the new space (has bit set) and
1661 // the object is in the old space (has bit cleared).
1662 // To check that, we compute value & ~object and skip the write barrier
1663 // if the bit is not set. We can't destroy the object.
1664 bic(IP, value, Operand(object));
1665 tst(IP, Operand(kNewObjectAlignmentOffset));
1666 b(no_update, EQ);
1667}
1668
1669
1670// Preserves object and value registers.
1671void Assembler::StoreIntoObjectFilter(Register object,
1672 Register value,
1673 Label* no_update) {
1674 // For the value we are only interested in the new/old bit and the tag bit.
1675 // And the new bit with the tag bit. The resulting bit will be 0 for a Smi.
1676 and_(IP, value, Operand(value, LSL, kObjectAlignmentLog2 - 1));
1677 // And the result with the negated space bit of the object.
1678 bic(IP, IP, Operand(object));
1679 tst(IP, Operand(kNewObjectAlignmentOffset));
1680 b(no_update, EQ);
1681}
1682
1683
1684Operand Assembler::GetVerifiedMemoryShadow() {
1685 Operand offset;
1686 if (!Operand::CanHold(VerifiedMemory::offset(), &offset)) {
1687 FATAL1("Offset 0x%" Px " not representable", VerifiedMemory::offset());
1688 }
1689 return offset;
1690}
1691
1692
1693void Assembler::WriteShadowedField(Register base,
1694 intptr_t offset,
1695 Register value,
1696 Condition cond) {
1697 if (VerifiedMemory::enabled()) {
1698 ASSERT(base != value);
1699 Operand shadow(GetVerifiedMemoryShadow());
1700 add(base, base, shadow, cond);
1701 str(value, Address(base, offset), cond);
1702 sub(base, base, shadow, cond);
1703 }
1704 str(value, Address(base, offset), cond);
1705}
1706
1707
1708void Assembler::WriteShadowedFieldPair(Register base,
1709 intptr_t offset,
1710 Register value_even,
1711 Register value_odd,
1712 Condition cond) {
1713 ASSERT(value_odd == value_even + 1);
1714 if (VerifiedMemory::enabled()) {
1715 ASSERT(base != value_even);
1716 ASSERT(base != value_odd);
1717 Operand shadow(GetVerifiedMemoryShadow());
1718 add(base, base, shadow, cond);
1719 strd(value_even, base, offset, cond);
1720 sub(base, base, shadow, cond);
1721 }
1722 strd(value_even, base, offset, cond);
1723}
1724
1725
1726Register UseRegister(Register reg, RegList* used) {
1727 ASSERT(reg != SP);
1728 ASSERT(reg != PC);
1729 ASSERT((*used & (1 << reg)) == 0);
1730 *used |= (1 << reg);
1731 return reg;
1732}
1733
1734
1735Register AllocateRegister(RegList* used) {
1736 const RegList free = ~*used;
1737 return (free == 0) ?
1738 kNoRegister :
1739 UseRegister(static_cast<Register>(Utils::CountTrailingZeros(free)), used);
1740}
1741
1742
1743void Assembler::VerifiedWrite(const Address& address,
1744 Register new_value,
1745 FieldContent old_content) {
1746#if defined(DEBUG)
1747 ASSERT(address.mode() == Address::Offset ||
1748 address.mode() == Address::NegOffset);
1749 // Allocate temporary registers (and check for register collisions).
1750 RegList used = 0;
1751 UseRegister(new_value, &used);
1752 Register base = UseRegister(address.rn(), &used);
1753 if (address.rm() != kNoRegister) {
1754 UseRegister(address.rm(), &used);
1755 }
1756 Register old_value = AllocateRegister(&used);
1757 Register temp = AllocateRegister(&used);
1758 PushList(used);
1759 ldr(old_value, address);
1760 // First check that 'old_value' contains 'old_content'.
1761 // Smi test.
1762 tst(old_value, Operand(kHeapObjectTag));
1763 Label ok;
1764 switch (old_content) {
1765 case kOnlySmi:
1766 b(&ok, EQ); // Smi is OK.
1767 Stop("Expected smi.");
1768 break;
1769 case kHeapObjectOrSmi:
1770 b(&ok, EQ); // Smi is OK.
1771 // Non-smi case: Verify object pointer is word-aligned when untagged.
1772 COMPILE_ASSERT(kHeapObjectTag == 1);
1773 tst(old_value, Operand((kWordSize - 1) - kHeapObjectTag));
1774 b(&ok, EQ);
1775 Stop("Expected heap object or Smi");
1776 break;
1777 case kEmptyOrSmiOrNull:
1778 b(&ok, EQ); // Smi is OK.
1779 // Non-smi case: Check for the special zap word or null.
1780 // Note: Cannot use CompareImmediate, since IP may be in use.
1781 LoadImmediate(temp, Heap::kZap32Bits);
1782 cmp(old_value, Operand(temp));
1783 b(&ok, EQ);
1784 LoadObject(temp, Object::null_object());
1785 cmp(old_value, Operand(temp));
1786 b(&ok, EQ);
1787 Stop("Expected zapped, Smi or null");
1788 break;
1789 default:
1790 UNREACHABLE();
1791 }
1792 Bind(&ok);
1793 if (VerifiedMemory::enabled()) {
1794 Operand shadow_offset(GetVerifiedMemoryShadow());
1795 // Adjust the address to shadow.
1796 add(base, base, shadow_offset);
1797 ldr(temp, address);
1798 cmp(old_value, Operand(temp));
1799 Label match;
1800 b(&match, EQ);
1801 Stop("Write barrier verification failed");
1802 Bind(&match);
1803 // Write new value in shadow.
1804 str(new_value, address);
1805 // Restore original address.
1806 sub(base, base, shadow_offset);
1807 }
1808 str(new_value, address);
1809 PopList(used);
1810#else
1811 str(new_value, address);
1812#endif // DEBUG
1813}
1814
1815
1816void Assembler::StoreIntoObject(Register object,
1817 const Address& dest,
1818 Register value,
1819 bool can_value_be_smi) {
1820 ASSERT(object != value);
1821 VerifiedWrite(dest, value, kHeapObjectOrSmi);
1822 Label done;
1823 if (can_value_be_smi) {
1824 StoreIntoObjectFilter(object, value, &done);
1825 } else {
1826 StoreIntoObjectFilterNoSmi(object, value, &done);
1827 }
1828 // A store buffer update is required.
1829 RegList regs = (1 << CODE_REG) | (1 << LR);
1830 if (value != R0) {
1831 regs |= (1 << R0); // Preserve R0.
1832 }
1833 PushList(regs);
1834 if (object != R0) {
1835 mov(R0, Operand(object));
1836 }
1837 ldr(CODE_REG, Address(THR, Thread::update_store_buffer_code_offset()));
1838 ldr(LR, Address(THR, Thread::update_store_buffer_entry_point_offset()));
1839 blx(LR);
1840 PopList(regs);
1841 Bind(&done);
1842}
1843
1844
1845void Assembler::StoreIntoObjectOffset(Register object,
1846 int32_t offset,
1847 Register value,
1848 bool can_value_be_smi) {
1849 int32_t ignored = 0;
1850 if (Address::CanHoldStoreOffset(kWord, offset - kHeapObjectTag, &ignored)) {
1851 StoreIntoObject(
1852 object, FieldAddress(object, offset), value, can_value_be_smi);
1853 } else {
1854 AddImmediate(IP, object, offset - kHeapObjectTag);
1855 StoreIntoObject(object, Address(IP), value, can_value_be_smi);
1856 }
1857}
1858
1859
1860void Assembler::StoreIntoObjectNoBarrier(Register object,
1861 const Address& dest,
1862 Register value,
1863 FieldContent old_content) {
1864 VerifiedWrite(dest, value, old_content);
1865#if defined(DEBUG)
1866 Label done;
1867 StoreIntoObjectFilter(object, value, &done);
1868 Stop("Store buffer update is required");
1869 Bind(&done);
1870#endif // defined(DEBUG)
1871 // No store buffer update.
1872}
1873
1874
1875void Assembler::StoreIntoObjectNoBarrierOffset(Register object,
1876 int32_t offset,
1877 Register value,
1878 FieldContent old_content) {
1879 int32_t ignored = 0;
1880 if (Address::CanHoldStoreOffset(kWord, offset - kHeapObjectTag, &ignored)) {
1881 StoreIntoObjectNoBarrier(object, FieldAddress(object, offset), value,
1882 old_content);
1883 } else {
1884 AddImmediate(IP, object, offset - kHeapObjectTag);
1885 StoreIntoObjectNoBarrier(object, Address(IP), value, old_content);
1886 }
1887}
1888
1889
1890void Assembler::StoreIntoObjectNoBarrier(Register object,
1891 const Address& dest,
1892 const Object& value,
1893 FieldContent old_content) {
1894 ASSERT(value.IsSmi() || value.InVMHeap() ||
1895 (value.IsOld() && value.IsNotTemporaryScopedHandle()));
1896 // No store buffer update.
1897 LoadObject(IP, value);
1898 VerifiedWrite(dest, IP, old_content);
1899}
1900
1901
1902void Assembler::StoreIntoObjectNoBarrierOffset(Register object,
1903 int32_t offset,
1904 const Object& value,
1905 FieldContent old_content) {
1906 int32_t ignored = 0;
1907 if (Address::CanHoldStoreOffset(kWord, offset - kHeapObjectTag, &ignored)) {
1908 StoreIntoObjectNoBarrier(object, FieldAddress(object, offset), value,
1909 old_content);
1910 } else {
1911 AddImmediate(IP, object, offset - kHeapObjectTag);
1912 StoreIntoObjectNoBarrier(object, Address(IP), value, old_content);
1913 }
1914}
1915
1916
1917void Assembler::InitializeFieldsNoBarrier(Register object,
1918 Register begin,
1919 Register end,
1920 Register value_even,
1921 Register value_odd) {
1922 ASSERT(value_odd == value_even + 1);
1923 Label init_loop;
1924 Bind(&init_loop);
1925 AddImmediate(begin, 2 * kWordSize);
1926 cmp(begin, Operand(end));
1927 WriteShadowedFieldPair(begin, -2 * kWordSize, value_even, value_odd, LS);
1928 b(&init_loop, CC);
1929 WriteShadowedField(begin, -2 * kWordSize, value_even, HI);
1930#if defined(DEBUG)
1931 Label done;
1932 StoreIntoObjectFilter(object, value_even, &done);
1933 StoreIntoObjectFilter(object, value_odd, &done);
1934 Stop("Store buffer update is required");
1935 Bind(&done);
1936#endif // defined(DEBUG)
1937 // No store buffer update.
1938}
1939
1940
1941void Assembler::InitializeFieldsNoBarrierUnrolled(Register object,
1942 Register base,
1943 intptr_t begin_offset,
1944 intptr_t end_offset,
1945 Register value_even,
1946 Register value_odd) {
1947 ASSERT(value_odd == value_even + 1);
1948 intptr_t current_offset = begin_offset;
1949 while (current_offset + kWordSize < end_offset) {
1950 WriteShadowedFieldPair(base, current_offset, value_even, value_odd);
1951 current_offset += 2*kWordSize;
1952 }
1953 while (current_offset < end_offset) {
1954 WriteShadowedField(base, current_offset, value_even);
1955 current_offset += kWordSize;
1956 }
1957#if defined(DEBUG)
1958 Label done;
1959 StoreIntoObjectFilter(object, value_even, &done);
1960 StoreIntoObjectFilter(object, value_odd, &done);
1961 Stop("Store buffer update is required");
1962 Bind(&done);
1963#endif // defined(DEBUG)
1964 // No store buffer update.
1965}
1966
1967
1968void Assembler::StoreIntoSmiField(const Address& dest, Register value) {
1969#if defined(DEBUG)
1970 Label done;
1971 tst(value, Operand(kHeapObjectTag));
1972 b(&done, EQ);
1973 Stop("New value must be Smi.");
1974 Bind(&done);
1975#endif // defined(DEBUG)
1976 VerifiedWrite(dest, value, kOnlySmi);
1977}
1978
1979
1980void Assembler::LoadClassId(Register result, Register object, Condition cond) {
1981 ASSERT(RawObject::kClassIdTagPos == 16);
1982 ASSERT(RawObject::kClassIdTagSize == 16);
1983 const intptr_t class_id_offset = Object::tags_offset() +
1984 RawObject::kClassIdTagPos / kBitsPerByte;
1985 ldrh(result, FieldAddress(object, class_id_offset), cond);
1986}
1987
1988
1989void Assembler::LoadClassById(Register result, Register class_id) {
1990 ASSERT(result != class_id);
1991 LoadIsolate(result);
1992 const intptr_t offset =
1993 Isolate::class_table_offset() + ClassTable::table_offset();
1994 LoadFromOffset(kWord, result, result, offset);
1995 ldr(result, Address(result, class_id, LSL, 2));
1996}
1997
1998
1999void Assembler::LoadClass(Register result, Register object, Register scratch) {
2000 ASSERT(scratch != result);
2001 LoadClassId(scratch, object);
2002 LoadClassById(result, scratch);
2003}
2004
2005
2006void Assembler::CompareClassId(Register object,
2007 intptr_t class_id,
2008 Register scratch) {
2009 LoadClassId(scratch, object);
2010 CompareImmediate(scratch, class_id);
2011}
2012
2013
2014void Assembler::LoadClassIdMayBeSmi(Register result, Register object) {
2015 tst(object, Operand(kSmiTagMask));
2016 LoadClassId(result, object, NE);
2017 LoadImmediate(result, kSmiCid, EQ);
2018}
2019
2020
2021void Assembler::LoadTaggedClassIdMayBeSmi(Register result, Register object) {
2022 LoadClassIdMayBeSmi(result, object);
2023 SmiTag(result);
2024}
2025
2026
2027void Assembler::ComputeRange(Register result,
2028 Register value,
2029 Register scratch,
2030 Label* not_mint) {
2031 const Register hi = TMP;
2032 const Register lo = scratch;
2033
2034 Label done;
2035 mov(result, Operand(value, LSR, kBitsPerWord - 1));
2036 tst(value, Operand(kSmiTagMask));
2037 b(&done, EQ);
2038 CompareClassId(value, kMintCid, result);
2039 b(not_mint, NE);
2040 ldr(hi, FieldAddress(value, Mint::value_offset() + kWordSize));
2041 ldr(lo, FieldAddress(value, Mint::value_offset()));
2042 rsb(result, hi, Operand(ICData::kInt32RangeBit));
2043 cmp(hi, Operand(lo, ASR, kBitsPerWord - 1));
2044 b(&done, EQ);
2045 LoadImmediate(result, ICData::kUint32RangeBit); // Uint32
2046 tst(hi, Operand(hi));
2047 LoadImmediate(result, ICData::kInt64RangeBit, NE); // Int64
2048 Bind(&done);
2049}
2050
2051
2052void Assembler::UpdateRangeFeedback(Register value,
2053 intptr_t index,
2054 Register ic_data,
2055 Register scratch1,
2056 Register scratch2,
2057 Label* miss) {
2058 ASSERT(ICData::IsValidRangeFeedbackIndex(index));
2059 ComputeRange(scratch1, value, scratch2, miss);
2060 ldr(scratch2, FieldAddress(ic_data, ICData::state_bits_offset()));
2061 orr(scratch2,
2062 scratch2,
2063 Operand(scratch1, LSL, ICData::RangeFeedbackShift(index)));
2064 str(scratch2, FieldAddress(ic_data, ICData::state_bits_offset()));
2065}
2066
2067
2068static bool CanEncodeBranchOffset(int32_t offset) {
2069 ASSERT(Utils::IsAligned(offset, 4));
2070 return Utils::IsInt(Utils::CountOneBits(kBranchOffsetMask), offset);
2071}
2072
2073
2074int32_t Assembler::EncodeBranchOffset(int32_t offset, int32_t inst) {
2075 // The offset is off by 8 due to the way the ARM CPUs read PC.
2076 offset -= Instr::kPCReadOffset;
2077
2078 if (!CanEncodeBranchOffset(offset)) {
2079 ASSERT(!use_far_branches());
2080 Thread::Current()->long_jump_base()->Jump(
2081 1, Object::branch_offset_error());
2082 }
2083
2084 // Properly preserve only the bits supported in the instruction.
2085 offset >>= 2;
2086 offset &= kBranchOffsetMask;
2087 return (inst & ~kBranchOffsetMask) | offset;
2088}
2089
2090
2091int Assembler::DecodeBranchOffset(int32_t inst) {
2092 // Sign-extend, left-shift by 2, then add 8.
2093 return ((((inst & kBranchOffsetMask) << 8) >> 6) + Instr::kPCReadOffset);
2094}
2095
2096
2097static int32_t DecodeARMv7LoadImmediate(int32_t movt, int32_t movw) {
2098 int32_t offset = 0;
2099 offset |= (movt & 0xf0000) << 12;
2100 offset |= (movt & 0xfff) << 16;
2101 offset |= (movw & 0xf0000) >> 4;
2102 offset |= movw & 0xfff;
2103 return offset;
2104}
2105
2106
2107static int32_t DecodeARMv6LoadImmediate(int32_t mov, int32_t or1,
2108 int32_t or2, int32_t or3) {
2109 int32_t offset = 0;
2110 offset |= (mov & 0xff) << 24;
2111 offset |= (or1 & 0xff) << 16;
2112 offset |= (or2 & 0xff) << 8;
2113 offset |= (or3 & 0xff);
2114 return offset;
2115}
2116
2117
2118class PatchFarBranch : public AssemblerFixup {
2119 public:
2120 PatchFarBranch() {}
2121
2122 void Process(const MemoryRegion& region, intptr_t position) {
2123 const ARMVersion version = TargetCPUFeatures::arm_version();
2124 if ((version == ARMv5TE) || (version == ARMv6)) {
2125 ProcessARMv6(region, position);
2126 } else {
2127 ASSERT(version == ARMv7);
2128 ProcessARMv7(region, position);
2129 }
2130 }
2131
2132 private:
2133 void ProcessARMv6(const MemoryRegion& region, intptr_t position) {
2134 const int32_t mov = region.Load<int32_t>(position);
2135 const int32_t or1 = region.Load<int32_t>(position + 1*Instr::kInstrSize);
2136 const int32_t or2 = region.Load<int32_t>(position + 2*Instr::kInstrSize);
2137 const int32_t or3 = region.Load<int32_t>(position + 3*Instr::kInstrSize);
2138 const int32_t bx = region.Load<int32_t>(position + 4*Instr::kInstrSize);
2139
2140 if (((mov & 0xffffff00) == 0xe3a0c400) && // mov IP, (byte3 rot 4)
2141 ((or1 & 0xffffff00) == 0xe38cc800) && // orr IP, IP, (byte2 rot 8)
2142 ((or2 & 0xffffff00) == 0xe38ccc00) && // orr IP, IP, (byte1 rot 12)
2143 ((or3 & 0xffffff00) == 0xe38cc000)) { // orr IP, IP, byte0
2144 const int32_t offset = DecodeARMv6LoadImmediate(mov, or1, or2, or3);
2145 const int32_t dest = region.start() + offset;
2146 const int32_t dest0 = (dest & 0x000000ff);
2147 const int32_t dest1 = (dest & 0x0000ff00) >> 8;
2148 const int32_t dest2 = (dest & 0x00ff0000) >> 16;
2149 const int32_t dest3 = (dest & 0xff000000) >> 24;
2150 const int32_t patched_mov = 0xe3a0c400 | dest3;
2151 const int32_t patched_or1 = 0xe38cc800 | dest2;
2152 const int32_t patched_or2 = 0xe38ccc00 | dest1;
2153 const int32_t patched_or3 = 0xe38cc000 | dest0;
2154
2155 region.Store<int32_t>(position + 0 * Instr::kInstrSize, patched_mov);
2156 region.Store<int32_t>(position + 1 * Instr::kInstrSize, patched_or1);
2157 region.Store<int32_t>(position + 2 * Instr::kInstrSize, patched_or2);
2158 region.Store<int32_t>(position + 3 * Instr::kInstrSize, patched_or3);
2159 return;
2160 }
2161
2162 // If the offset loading instructions aren't there, we must have replaced
2163 // the far branch with a near one, and so these instructions
2164 // should be NOPs.
2165 ASSERT((or1 == Instr::kNopInstruction) &&
2166 (or2 == Instr::kNopInstruction) &&
2167 (or3 == Instr::kNopInstruction) &&
2168 (bx == Instr::kNopInstruction));
2169 }
2170
2171
2172 void ProcessARMv7(const MemoryRegion& region, intptr_t position) {
2173 const int32_t movw = region.Load<int32_t>(position);
2174 const int32_t movt = region.Load<int32_t>(position + Instr::kInstrSize);
2175 const int32_t bx = region.Load<int32_t>(position + 2 * Instr::kInstrSize);
2176
2177 if (((movt & 0xfff0f000) == 0xe340c000) && // movt IP, high
2178 ((movw & 0xfff0f000) == 0xe300c000)) { // movw IP, low
2179 const int32_t offset = DecodeARMv7LoadImmediate(movt, movw);
2180 const int32_t dest = region.start() + offset;
2181 const uint16_t dest_high = Utils::High16Bits(dest);
2182 const uint16_t dest_low = Utils::Low16Bits(dest);
2183 const int32_t patched_movt =
2184 0xe340c000 | ((dest_high >> 12) << 16) | (dest_high & 0xfff);
2185 const int32_t patched_movw =
2186 0xe300c000 | ((dest_low >> 12) << 16) | (dest_low & 0xfff);
2187
2188 region.Store<int32_t>(position, patched_movw);
2189 region.Store<int32_t>(position + Instr::kInstrSize, patched_movt);
2190 return;
2191 }
2192
2193 // If the offset loading instructions aren't there, we must have replaced
2194 // the far branch with a near one, and so these instructions
2195 // should be NOPs.
2196 ASSERT((movt == Instr::kNopInstruction) &&
2197 (bx == Instr::kNopInstruction));
2198 }
2199
2200 virtual bool IsPointerOffset() const { return false; }
2201};
2202
2203
2204void Assembler::EmitFarBranch(Condition cond, int32_t offset, bool link) {
2205 buffer_.EmitFixup(new PatchFarBranch());
2206 LoadPatchableImmediate(IP, offset);
2207 if (link) {
2208 blx(IP, cond);
2209 } else {
2210 bx(IP, cond);
2211 }
2212}
2213
2214
2215void Assembler::EmitBranch(Condition cond, Label* label, bool link) {
2216 if (label->IsBound()) {
2217 const int32_t dest = label->Position() - buffer_.Size();
2218 if (use_far_branches() && !CanEncodeBranchOffset(dest)) {
2219 EmitFarBranch(cond, label->Position(), link);
2220 } else {
2221 EmitType5(cond, dest, link);
2222 }
2223 } else {
2224 const intptr_t position = buffer_.Size();
2225 if (use_far_branches()) {
2226 const int32_t dest = label->position_;
2227 EmitFarBranch(cond, dest, link);
2228 } else {
2229 // Use the offset field of the branch instruction for linking the sites.
2230 EmitType5(cond, label->position_, link);
2231 }
2232 label->LinkTo(position);
2233 }
2234}
2235
2236
2237void Assembler::BindARMv6(Label* label) {
2238 ASSERT(!label->IsBound());
2239 intptr_t bound_pc = buffer_.Size();
2240 while (label->IsLinked()) {
2241 const int32_t position = label->Position();
2242 int32_t dest = bound_pc - position;
2243 if (use_far_branches() && !CanEncodeBranchOffset(dest)) {
2244 // Far branches are enabled and we can't encode the branch offset.
2245
2246 // Grab instructions that load the offset.
2247 const int32_t mov =
2248 buffer_.Load<int32_t>(position);
2249 const int32_t or1 =
2250 buffer_.Load<int32_t>(position + 1 * Instr::kInstrSize);
2251 const int32_t or2 =
2252 buffer_.Load<int32_t>(position + 2 * Instr::kInstrSize);
2253 const int32_t or3 =
2254 buffer_.Load<int32_t>(position + 3 * Instr::kInstrSize);
2255
2256 // Change from relative to the branch to relative to the assembler
2257 // buffer.
2258 dest = buffer_.Size();
2259 const int32_t dest0 = (dest & 0x000000ff);
2260 const int32_t dest1 = (dest & 0x0000ff00) >> 8;
2261 const int32_t dest2 = (dest & 0x00ff0000) >> 16;
2262 const int32_t dest3 = (dest & 0xff000000) >> 24;
2263 const int32_t patched_mov = 0xe3a0c400 | dest3;
2264 const int32_t patched_or1 = 0xe38cc800 | dest2;
2265 const int32_t patched_or2 = 0xe38ccc00 | dest1;
2266 const int32_t patched_or3 = 0xe38cc000 | dest0;
2267
2268 // Rewrite the instructions.
2269 buffer_.Store<int32_t>(position + 0 * Instr::kInstrSize, patched_mov);
2270 buffer_.Store<int32_t>(position + 1 * Instr::kInstrSize, patched_or1);
2271 buffer_.Store<int32_t>(position + 2 * Instr::kInstrSize, patched_or2);
2272 buffer_.Store<int32_t>(position + 3 * Instr::kInstrSize, patched_or3);
2273 label->position_ = DecodeARMv6LoadImmediate(mov, or1, or2, or3);
2274 } else if (use_far_branches() && CanEncodeBranchOffset(dest)) {
2275 // Grab instructions that load the offset, and the branch.
2276 const int32_t mov =
2277 buffer_.Load<int32_t>(position);
2278 const int32_t or1 =
2279 buffer_.Load<int32_t>(position + 1 * Instr::kInstrSize);
2280 const int32_t or2 =
2281 buffer_.Load<int32_t>(position + 2 * Instr::kInstrSize);
2282 const int32_t or3 =
2283 buffer_.Load<int32_t>(position + 3 * Instr::kInstrSize);
2284 const int32_t branch =
2285 buffer_.Load<int32_t>(position + 4 * Instr::kInstrSize);
2286
2287 // Grab the branch condition, and encode the link bit.
2288 const int32_t cond = branch & 0xf0000000;
2289 const int32_t link = (branch & 0x20) << 19;
2290
2291 // Encode the branch and the offset.
2292 const int32_t new_branch = cond | link | 0x0a000000;
2293 const int32_t encoded = EncodeBranchOffset(dest, new_branch);
2294
2295 // Write the encoded branch instruction followed by two nops.
2296 buffer_.Store<int32_t>(position, encoded);
2297 buffer_.Store<int32_t>(position + 1 * Instr::kInstrSize,
2298 Instr::kNopInstruction);
2299 buffer_.Store<int32_t>(position + 2 * Instr::kInstrSize,
2300 Instr::kNopInstruction);
2301 buffer_.Store<int32_t>(position + 3 * Instr::kInstrSize,
2302 Instr::kNopInstruction);
2303 buffer_.Store<int32_t>(position + 4 * Instr::kInstrSize,
2304 Instr::kNopInstruction);
2305
2306 label->position_ = DecodeARMv6LoadImmediate(mov, or1, or2, or3);
2307 } else {
2308 int32_t next = buffer_.Load<int32_t>(position);
2309 int32_t encoded = Assembler::EncodeBranchOffset(dest, next);
2310 buffer_.Store<int32_t>(position, encoded);
2311 label->position_ = Assembler::DecodeBranchOffset(next);
2312 }
2313 }
2314 label->BindTo(bound_pc);
2315}
2316
2317
2318void Assembler::BindARMv7(Label* label) {
2319 ASSERT(!label->IsBound());
2320 intptr_t bound_pc = buffer_.Size();
2321 while (label->IsLinked()) {
2322 const int32_t position = label->Position();
2323 int32_t dest = bound_pc - position;
2324 if (use_far_branches() && !CanEncodeBranchOffset(dest)) {
2325 // Far branches are enabled and we can't encode the branch offset.
2326
2327 // Grab instructions that load the offset.
2328 const int32_t movw =
2329 buffer_.Load<int32_t>(position + 0 * Instr::kInstrSize);
2330 const int32_t movt =
2331 buffer_.Load<int32_t>(position + 1 * Instr::kInstrSize);
2332
2333 // Change from relative to the branch to relative to the assembler
2334 // buffer.
2335 dest = buffer_.Size();
2336 const uint16_t dest_high = Utils::High16Bits(dest);
2337 const uint16_t dest_low = Utils::Low16Bits(dest);
2338 const int32_t patched_movt =
2339 0xe340c000 | ((dest_high >> 12) << 16) | (dest_high & 0xfff);
2340 const int32_t patched_movw =
2341 0xe300c000 | ((dest_low >> 12) << 16) | (dest_low & 0xfff);
2342
2343 // Rewrite the instructions.
2344 buffer_.Store<int32_t>(position + 0 * Instr::kInstrSize, patched_movw);
2345 buffer_.Store<int32_t>(position + 1 * Instr::kInstrSize, patched_movt);
2346 label->position_ = DecodeARMv7LoadImmediate(movt, movw);
2347 } else if (use_far_branches() && CanEncodeBranchOffset(dest)) {
2348 // Far branches are enabled, but we can encode the branch offset.
2349
2350 // Grab instructions that load the offset, and the branch.
2351 const int32_t movw =
2352 buffer_.Load<int32_t>(position + 0 * Instr::kInstrSize);
2353 const int32_t movt =
2354 buffer_.Load<int32_t>(position + 1 * Instr::kInstrSize);
2355 const int32_t branch =
2356 buffer_.Load<int32_t>(position + 2 * Instr::kInstrSize);
2357
2358 // Grab the branch condition, and encode the link bit.
2359 const int32_t cond = branch & 0xf0000000;
2360 const int32_t link = (branch & 0x20) << 19;
2361
2362 // Encode the branch and the offset.
2363 const int32_t new_branch = cond | link | 0x0a000000;
2364 const int32_t encoded = EncodeBranchOffset(dest, new_branch);
2365
2366 // Write the encoded branch instruction followed by two nops.
2367 buffer_.Store<int32_t>(position + 0 * Instr::kInstrSize,
2368 encoded);
2369 buffer_.Store<int32_t>(position + 1 * Instr::kInstrSize,
2370 Instr::kNopInstruction);
2371 buffer_.Store<int32_t>(position + 2 * Instr::kInstrSize,
2372 Instr::kNopInstruction);
2373
2374 label->position_ = DecodeARMv7LoadImmediate(movt, movw);
2375 } else {
2376 int32_t next = buffer_.Load<int32_t>(position);
2377 int32_t encoded = Assembler::EncodeBranchOffset(dest, next);
2378 buffer_.Store<int32_t>(position, encoded);
2379 label->position_ = Assembler::DecodeBranchOffset(next);
2380 }
2381 }
2382 label->BindTo(bound_pc);
2383}
2384
2385
2386void Assembler::Bind(Label* label) {
2387 const ARMVersion version = TargetCPUFeatures::arm_version();
2388 if ((version == ARMv5TE) || (version == ARMv6)) {
2389 BindARMv6(label);
2390 } else {
2391 ASSERT(version == ARMv7);
2392 BindARMv7(label);
2393 }
2394}
2395
2396
2397OperandSize Address::OperandSizeFor(intptr_t cid) {
2398 switch (cid) {
2399 case kArrayCid:
2400 case kImmutableArrayCid:
2401 return kWord;
2402 case kOneByteStringCid:
2403 case kExternalOneByteStringCid:
2404 return kByte;
2405 case kTwoByteStringCid:
2406 case kExternalTwoByteStringCid:
2407 return kHalfword;
2408 case kTypedDataInt8ArrayCid:
2409 return kByte;
2410 case kTypedDataUint8ArrayCid:
2411 case kTypedDataUint8ClampedArrayCid:
2412 case kExternalTypedDataUint8ArrayCid:
2413 case kExternalTypedDataUint8ClampedArrayCid:
2414 return kUnsignedByte;
2415 case kTypedDataInt16ArrayCid:
2416 return kHalfword;
2417 case kTypedDataUint16ArrayCid:
2418 return kUnsignedHalfword;
2419 case kTypedDataInt32ArrayCid:
2420 return kWord;
2421 case kTypedDataUint32ArrayCid:
2422 return kUnsignedWord;
2423 case kTypedDataInt64ArrayCid:
2424 case kTypedDataUint64ArrayCid:
2425 UNREACHABLE();
2426 return kByte;
2427 case kTypedDataFloat32ArrayCid:
2428 return kSWord;
2429 case kTypedDataFloat64ArrayCid:
2430 return kDWord;
2431 case kTypedDataFloat32x4ArrayCid:
2432 case kTypedDataInt32x4ArrayCid:
2433 case kTypedDataFloat64x2ArrayCid:
2434 return kRegList;
2435 case kTypedDataInt8ArrayViewCid:
2436 UNREACHABLE();
2437 return kByte;
2438 default:
2439 UNREACHABLE();
2440 return kByte;
2441 }
2442}
2443
2444
2445bool Address::CanHoldLoadOffset(OperandSize size,
2446 int32_t offset,
2447 int32_t* offset_mask) {
2448 switch (size) {
2449 case kByte:
2450 case kHalfword:
2451 case kUnsignedHalfword:
2452 case kWordPair: {
2453 *offset_mask = 0xff;
2454 return Utils::IsAbsoluteUint(8, offset); // Addressing mode 3.
2455 }
2456 case kUnsignedByte:
2457 case kWord:
2458 case kUnsignedWord: {
2459 *offset_mask = 0xfff;
2460 return Utils::IsAbsoluteUint(12, offset); // Addressing mode 2.
2461 }
2462 case kSWord:
2463 case kDWord: {
2464 *offset_mask = 0x3fc; // Multiple of 4.
2465 // VFP addressing mode.
2466 return (Utils::IsAbsoluteUint(10, offset) && Utils::IsAligned(offset, 4));
2467 }
2468 case kRegList: {
2469 *offset_mask = 0x0;
2470 return offset == 0;
2471 }
2472 default: {
2473 UNREACHABLE();
2474 return false;
2475 }
2476 }
2477}
2478
2479
2480bool Address::CanHoldStoreOffset(OperandSize size,
2481 int32_t offset,
2482 int32_t* offset_mask) {
2483 switch (size) {
2484 case kHalfword:
2485 case kUnsignedHalfword:
2486 case kWordPair: {
2487 *offset_mask = 0xff;
2488 return Utils::IsAbsoluteUint(8, offset); // Addressing mode 3.
2489 }
2490 case kByte:
2491 case kUnsignedByte:
2492 case kWord:
2493 case kUnsignedWord: {
2494 *offset_mask = 0xfff;
2495 return Utils::IsAbsoluteUint(12, offset); // Addressing mode 2.
2496 }
2497 case kSWord:
2498 case kDWord: {
2499 *offset_mask = 0x3fc; // Multiple of 4.
2500 // VFP addressing mode.
2501 return (Utils::IsAbsoluteUint(10, offset) && Utils::IsAligned(offset, 4));
2502 }
2503 case kRegList: {
2504 *offset_mask = 0x0;
2505 return offset == 0;
2506 }
2507 default: {
2508 UNREACHABLE();
2509 return false;
2510 }
2511 }
2512}
2513
2514
2515bool Address::CanHoldImmediateOffset(
2516 bool is_load, intptr_t cid, int64_t offset) {
2517 int32_t offset_mask = 0;
2518 if (is_load) {
2519 return CanHoldLoadOffset(OperandSizeFor(cid), offset, &offset_mask);
2520 } else {
2521 return CanHoldStoreOffset(OperandSizeFor(cid), offset, &offset_mask);
2522 }
2523}
2524
2525
2526void Assembler::Push(Register rd, Condition cond) {
2527 str(rd, Address(SP, -kWordSize, Address::PreIndex), cond);
2528}
2529
2530
2531void Assembler::Pop(Register rd, Condition cond) {
2532 ldr(rd, Address(SP, kWordSize, Address::PostIndex), cond);
2533}
2534
2535
2536void Assembler::PushList(RegList regs, Condition cond) {
2537 stm(DB_W, SP, regs, cond);
2538}
2539
2540
2541void Assembler::PopList(RegList regs, Condition cond) {
2542 ldm(IA_W, SP, regs, cond);
2543}
2544
2545
2546void Assembler::MoveRegister(Register rd, Register rm, Condition cond) {
2547 if (rd != rm) {
2548 mov(rd, Operand(rm), cond);
2549 }
2550}
2551
2552
2553void Assembler::Lsl(Register rd, Register rm, const Operand& shift_imm,
2554 Condition cond) {
2555 ASSERT(shift_imm.type() == 1);
2556 ASSERT(shift_imm.encoding() != 0); // Do not use Lsl if no shift is wanted.
2557 mov(rd, Operand(rm, LSL, shift_imm.encoding()), cond);
2558}
2559
2560
2561void Assembler::Lsl(Register rd, Register rm, Register rs, Condition cond) {
2562 mov(rd, Operand(rm, LSL, rs), cond);
2563}
2564
2565
2566void Assembler::Lsr(Register rd, Register rm, const Operand& shift_imm,
2567 Condition cond) {
2568 ASSERT(shift_imm.type() == 1);
2569 uint32_t shift = shift_imm.encoding();
2570 ASSERT(shift != 0); // Do not use Lsr if no shift is wanted.
2571 if (shift == 32) {
2572 shift = 0; // Comply to UAL syntax.
2573 }
2574 mov(rd, Operand(rm, LSR, shift), cond);
2575}
2576
2577
2578void Assembler::Lsr(Register rd, Register rm, Register rs, Condition cond) {
2579 mov(rd, Operand(rm, LSR, rs), cond);
2580}
2581
2582
2583void Assembler::Asr(Register rd, Register rm, const Operand& shift_imm,
2584 Condition cond) {
2585 ASSERT(shift_imm.type() == 1);
2586 uint32_t shift = shift_imm.encoding();
2587 ASSERT(shift != 0); // Do not use Asr if no shift is wanted.
2588 if (shift == 32) {
2589 shift = 0; // Comply to UAL syntax.
2590 }
2591 mov(rd, Operand(rm, ASR, shift), cond);
2592}
2593
2594
2595void Assembler::Asrs(Register rd, Register rm, const Operand& shift_imm,
2596 Condition cond) {
2597 ASSERT(shift_imm.type() == 1);
2598 uint32_t shift = shift_imm.encoding();
2599 ASSERT(shift != 0); // Do not use Asr if no shift is wanted.
2600 if (shift == 32) {
2601 shift = 0; // Comply to UAL syntax.
2602 }
2603 movs(rd, Operand(rm, ASR, shift), cond);
2604}
2605
2606
2607void Assembler::Asr(Register rd, Register rm, Register rs, Condition cond) {
2608 mov(rd, Operand(rm, ASR, rs), cond);
2609}
2610
2611
2612void Assembler::Ror(Register rd, Register rm, const Operand& shift_imm,
2613 Condition cond) {
2614 ASSERT(shift_imm.type() == 1);
2615 ASSERT(shift_imm.encoding() != 0); // Use Rrx instruction.
2616 mov(rd, Operand(rm, ROR, shift_imm.encoding()), cond);
2617}
2618
2619
2620void Assembler::Ror(Register rd, Register rm, Register rs, Condition cond) {
2621 mov(rd, Operand(rm, ROR, rs), cond);
2622}
2623
2624
2625void Assembler::Rrx(Register rd, Register rm, Condition cond) {
2626 mov(rd, Operand(rm, ROR, 0), cond);
2627}
2628
2629
2630void Assembler::SignFill(Register rd, Register rm, Condition cond) {
2631 Asr(rd, rm, Operand(31), cond);
2632}
2633
2634
2635void Assembler::Vreciprocalqs(QRegister qd, QRegister qm) {
2636 ASSERT(qm != QTMP);
2637 ASSERT(qd != QTMP);
2638
2639 // Reciprocal estimate.
2640 vrecpeqs(qd, qm);
2641 // 2 Newton-Raphson steps.
2642 vrecpsqs(QTMP, qm, qd);
2643 vmulqs(qd, qd, QTMP);
2644 vrecpsqs(QTMP, qm, qd);
2645 vmulqs(qd, qd, QTMP);
2646}
2647
2648
2649void Assembler::VreciprocalSqrtqs(QRegister qd, QRegister qm) {
2650 ASSERT(qm != QTMP);
2651 ASSERT(qd != QTMP);
2652
2653 // Reciprocal square root estimate.
2654 vrsqrteqs(qd, qm);
2655 // 2 Newton-Raphson steps. xn+1 = xn * (3 - Q1*xn^2) / 2.
2656 // First step.
2657 vmulqs(QTMP, qd, qd); // QTMP <- xn^2
2658 vrsqrtsqs(QTMP, qm, QTMP); // QTMP <- (3 - Q1*QTMP) / 2.
2659 vmulqs(qd, qd, QTMP); // xn+1 <- xn * QTMP
2660 // Second step.
2661 vmulqs(QTMP, qd, qd);
2662 vrsqrtsqs(QTMP, qm, QTMP);
2663 vmulqs(qd, qd, QTMP);
2664}
2665
2666
2667void Assembler::Vsqrtqs(QRegister qd, QRegister qm, QRegister temp) {
2668 ASSERT(temp != QTMP);
2669 ASSERT(qm != QTMP);
2670 ASSERT(qd != QTMP);
2671
2672 if (temp != kNoQRegister) {
2673 vmovq(temp, qm);
2674 qm = temp;
2675 }
2676
2677 VreciprocalSqrtqs(qd, qm);
2678 vmovq(qm, qd);
2679 Vreciprocalqs(qd, qm);
2680}
2681
2682
2683void Assembler::Vdivqs(QRegister qd, QRegister qn, QRegister qm) {
2684 ASSERT(qd != QTMP);
2685 ASSERT(qn != QTMP);
2686 ASSERT(qm != QTMP);
2687
2688 Vreciprocalqs(qd, qm);
2689 vmulqs(qd, qn, qd);
2690}
2691
2692
2693void Assembler::Branch(const StubEntry& stub_entry,
2694 Patchability patchable,
2695 Register pp,
2696 Condition cond) {
2697 const Code& target_code = Code::Handle(stub_entry.code());
2698 const int32_t offset = ObjectPool::element_offset(
2699 object_pool_wrapper_.FindObject(target_code, patchable));
2700 LoadWordFromPoolOffset(CODE_REG, offset - kHeapObjectTag, pp, cond);
2701 ldr(IP, FieldAddress(CODE_REG, Code::entry_point_offset()), cond);
2702 bx(IP, cond);
2703}
2704
2705
2706void Assembler::BranchLink(const Code& target, Patchability patchable) {
2707 // Make sure that class CallPattern is able to patch the label referred
2708 // to by this code sequence.
2709 // For added code robustness, use 'blx lr' in a patchable sequence and
2710 // use 'blx ip' in a non-patchable sequence (see other BranchLink flavors).
2711 const int32_t offset = ObjectPool::element_offset(
2712 object_pool_wrapper_.FindObject(target, patchable));
2713 LoadWordFromPoolOffset(CODE_REG, offset - kHeapObjectTag, PP, AL);
2714 ldr(LR, FieldAddress(CODE_REG, Code::entry_point_offset()));
2715 blx(LR); // Use blx instruction so that the return branch prediction works.
2716}
2717
2718
2719void Assembler::BranchLink(const StubEntry& stub_entry,
2720 Patchability patchable) {
2721 const Code& code = Code::Handle(stub_entry.code());
2722 BranchLink(code, patchable);
2723}
2724
2725
2726void Assembler::BranchLinkPatchable(const Code& target) {
2727 BranchLink(target, kPatchable);
2728}
2729
2730
2731void Assembler::BranchLink(const ExternalLabel* label) {
2732 LoadImmediate(LR, label->address()); // Target address is never patched.
2733 blx(LR); // Use blx instruction so that the return branch prediction works.
2734}
2735
2736
2737void Assembler::BranchLinkPatchable(const StubEntry& stub_entry) {
2738 BranchLinkPatchable(Code::Handle(stub_entry.code()));
2739}
2740
2741
2742void Assembler::BranchLinkOffset(Register base, int32_t offset) {
2743 ASSERT(base != PC);
2744 ASSERT(base != IP);
2745 LoadFromOffset(kWord, IP, base, offset);
2746 blx(IP); // Use blx instruction so that the return branch prediction works.
2747}
2748
2749
2750void Assembler::LoadPatchableImmediate(
2751 Register rd, int32_t value, Condition cond) {
2752 const ARMVersion version = TargetCPUFeatures::arm_version();
2753 if ((version == ARMv5TE) || (version == ARMv6)) {
2754 // This sequence is patched in a few places, and should remain fixed.
2755 const uint32_t byte0 = (value & 0x000000ff);
2756 const uint32_t byte1 = (value & 0x0000ff00) >> 8;
2757 const uint32_t byte2 = (value & 0x00ff0000) >> 16;
2758 const uint32_t byte3 = (value & 0xff000000) >> 24;
2759 mov(rd, Operand(4, byte3), cond);
2760 orr(rd, rd, Operand(8, byte2), cond);
2761 orr(rd, rd, Operand(12, byte1), cond);
2762 orr(rd, rd, Operand(byte0), cond);
2763 } else {
2764 ASSERT(version == ARMv7);
2765 const uint16_t value_low = Utils::Low16Bits(value);
2766 const uint16_t value_high = Utils::High16Bits(value);
2767 movw(rd, value_low, cond);
2768 movt(rd, value_high, cond);
2769 }
2770}
2771
2772
2773void Assembler::LoadDecodableImmediate(
2774 Register rd, int32_t value, Condition cond) {
2775 const ARMVersion version = TargetCPUFeatures::arm_version();
2776 if ((version == ARMv5TE) || (version == ARMv6)) {
2777 if (constant_pool_allowed()) {
2778 const int32_t offset = Array::element_offset(FindImmediate(value));
2779 LoadWordFromPoolOffset(rd, offset - kHeapObjectTag, PP, cond);
2780 } else {
2781 LoadPatchableImmediate(rd, value, cond);
2782 }
2783 } else {
2784 ASSERT(version == ARMv7);
2785 movw(rd, Utils::Low16Bits(value), cond);
2786 const uint16_t value_high = Utils::High16Bits(value);
2787 if (value_high != 0) {
2788 movt(rd, value_high, cond);
2789 }
2790 }
2791}
2792
2793
2794void Assembler::LoadImmediate(Register rd, int32_t value, Condition cond) {
2795 Operand o;
2796 if (Operand::CanHold(value, &o)) {
2797 mov(rd, o, cond);
2798 } else if (Operand::CanHold(~value, &o)) {
2799 mvn(rd, o, cond);
2800 } else {
2801 LoadDecodableImmediate(rd, value, cond);
2802 }
2803}
2804
2805
2806void Assembler::LoadSImmediate(SRegister sd, float value, Condition cond) {
2807 if (!vmovs(sd, value, cond)) {
2808 const DRegister dd = static_cast<DRegister>(sd >> 1);
2809 const int index = sd & 1;
2810 LoadImmediate(IP, bit_cast<int32_t, float>(value), cond);
2811 vmovdr(dd, index, IP, cond);
2812 }
2813}
2814
2815
2816void Assembler::LoadDImmediate(DRegister dd,
2817 double value,
2818 Register scratch,
2819 Condition cond) {
2820 ASSERT(scratch != PC);
2821 ASSERT(scratch != IP);
2822 if (!vmovd(dd, value, cond)) {
2823 // A scratch register and IP are needed to load an arbitrary double.
2824 ASSERT(scratch != kNoRegister);
2825 int64_t imm64 = bit_cast<int64_t, double>(value);
2826 LoadImmediate(IP, Utils::Low32Bits(imm64), cond);
2827 LoadImmediate(scratch, Utils::High32Bits(imm64), cond);
2828 vmovdrr(dd, IP, scratch, cond);
2829 }
2830}
2831
2832
2833void Assembler::LoadFromOffset(OperandSize size,
2834 Register reg,
2835 Register base,
2836 int32_t offset,
2837 Condition cond) {
2838 int32_t offset_mask = 0;
2839 if (!Address::CanHoldLoadOffset(size, offset, &offset_mask)) {
2840 ASSERT(base != IP);
2841 AddImmediate(IP, base, offset & ~offset_mask, cond);
2842 base = IP;
2843 offset = offset & offset_mask;
2844 }
2845 switch (size) {
2846 case kByte:
2847 ldrsb(reg, Address(base, offset), cond);
2848 break;
2849 case kUnsignedByte:
2850 ldrb(reg, Address(base, offset), cond);
2851 break;
2852 case kHalfword:
2853 ldrsh(reg, Address(base, offset), cond);
2854 break;
2855 case kUnsignedHalfword:
2856 ldrh(reg, Address(base, offset), cond);
2857 break;
2858 case kWord:
2859 ldr(reg, Address(base, offset), cond);
2860 break;
2861 case kWordPair:
2862 ldrd(reg, base, offset, cond);
2863 break;
2864 default:
2865 UNREACHABLE();
2866 }
2867}
2868
2869
2870void Assembler::StoreToOffset(OperandSize size,
2871 Register reg,
2872 Register base,
2873 int32_t offset,
2874 Condition cond) {
2875 int32_t offset_mask = 0;
2876 if (!Address::CanHoldStoreOffset(size, offset, &offset_mask)) {
2877 ASSERT(reg != IP);
2878 ASSERT(base != IP);
2879 AddImmediate(IP, base, offset & ~offset_mask, cond);
2880 base = IP;
2881 offset = offset & offset_mask;
2882 }
2883 switch (size) {
2884 case kByte:
2885 strb(reg, Address(base, offset), cond);
2886 break;
2887 case kHalfword:
2888 strh(reg, Address(base, offset), cond);
2889 break;
2890 case kWord:
2891 str(reg, Address(base, offset), cond);
2892 break;
2893 case kWordPair:
2894 strd(reg, base, offset, cond);
2895 break;
2896 default:
2897 UNREACHABLE();
2898 }
2899}
2900
2901
2902void Assembler::LoadSFromOffset(SRegister reg,
2903 Register base,
2904 int32_t offset,
2905 Condition cond) {
2906 int32_t offset_mask = 0;
2907 if (!Address::CanHoldLoadOffset(kSWord, offset, &offset_mask)) {
2908 ASSERT(base != IP);
2909 AddImmediate(IP, base, offset & ~offset_mask, cond);
2910 base = IP;
2911 offset = offset & offset_mask;
2912 }
2913 vldrs(reg, Address(base, offset), cond);
2914}
2915
2916
2917void Assembler::StoreSToOffset(SRegister reg,
2918 Register base,
2919 int32_t offset,
2920 Condition cond) {
2921 int32_t offset_mask = 0;
2922 if (!Address::CanHoldStoreOffset(kSWord, offset, &offset_mask)) {
2923 ASSERT(base != IP);
2924 AddImmediate(IP, base, offset & ~offset_mask, cond);
2925 base = IP;
2926 offset = offset & offset_mask;
2927 }
2928 vstrs(reg, Address(base, offset), cond);
2929}
2930
2931
2932void Assembler::LoadDFromOffset(DRegister reg,
2933 Register base,
2934 int32_t offset,
2935 Condition cond) {
2936 int32_t offset_mask = 0;
2937 if (!Address::CanHoldLoadOffset(kDWord, offset, &offset_mask)) {
2938 ASSERT(base != IP);
2939 AddImmediate(IP, base, offset & ~offset_mask, cond);
2940 base = IP;
2941 offset = offset & offset_mask;
2942 }
2943 vldrd(reg, Address(base, offset), cond);
2944}
2945
2946
2947void Assembler::StoreDToOffset(DRegister reg,
2948 Register base,
2949 int32_t offset,
2950 Condition cond) {
2951 int32_t offset_mask = 0;
2952 if (!Address::CanHoldStoreOffset(kDWord, offset, &offset_mask)) {
2953 ASSERT(base != IP);
2954 AddImmediate(IP, base, offset & ~offset_mask, cond);
2955 base = IP;
2956 offset = offset & offset_mask;
2957 }
2958 vstrd(reg, Address(base, offset), cond);
2959}
2960
2961
2962void Assembler::LoadMultipleDFromOffset(DRegister first,
2963 intptr_t count,
2964 Register base,
2965 int32_t offset) {
2966 ASSERT(base != IP);
2967 AddImmediate(IP, base, offset);
2968 vldmd(IA, IP, first, count);
2969}
2970
2971void Assembler::StoreMultipleDToOffset(DRegister first,
2972 intptr_t count,
2973 Register base,
2974 int32_t offset) {
2975 ASSERT(base != IP);
2976 AddImmediate(IP, base, offset);
2977 vstmd(IA, IP, first, count);
2978}
2979
2980
2981void Assembler::CopyDoubleField(
2982 Register dst, Register src, Register tmp1, Register tmp2, DRegister dtmp) {
2983 if (TargetCPUFeatures::vfp_supported()) {
2984 LoadDFromOffset(dtmp, src, Double::value_offset() - kHeapObjectTag);
2985 StoreDToOffset(dtmp, dst, Double::value_offset() - kHeapObjectTag);
2986 } else {
2987 LoadFromOffset(kWord, tmp1, src,
2988 Double::value_offset() - kHeapObjectTag);
2989 LoadFromOffset(kWord, tmp2, src,
2990 Double::value_offset() + kWordSize - kHeapObjectTag);
2991 StoreToOffset(kWord, tmp1, dst,
2992 Double::value_offset() - kHeapObjectTag);
2993 StoreToOffset(kWord, tmp2, dst,
2994 Double::value_offset() + kWordSize - kHeapObjectTag);
2995 }
2996}
2997
2998
2999void Assembler::CopyFloat32x4Field(
3000 Register dst, Register src, Register tmp1, Register tmp2, DRegister dtmp) {
3001 if (TargetCPUFeatures::neon_supported()) {
3002 LoadMultipleDFromOffset(dtmp, 2, src,
3003 Float32x4::value_offset() - kHeapObjectTag);
3004 StoreMultipleDToOffset(dtmp, 2, dst,
3005 Float32x4::value_offset() - kHeapObjectTag);
3006 } else {
3007 LoadFromOffset(kWord, tmp1, src,
3008 (Float32x4::value_offset() + 0 * kWordSize) - kHeapObjectTag);
3009 LoadFromOffset(kWord, tmp2, src,
3010 (Float32x4::value_offset() + 1 * kWordSize) - kHeapObjectTag);
3011 StoreToOffset(kWord, tmp1, dst,
3012 (Float32x4::value_offset() + 0 * kWordSize) - kHeapObjectTag);
3013 StoreToOffset(kWord, tmp2, dst,
3014 (Float32x4::value_offset() + 1 * kWordSize) - kHeapObjectTag);
3015
3016 LoadFromOffset(kWord, tmp1, src,
3017 (Float32x4::value_offset() + 2 * kWordSize) - kHeapObjectTag);
3018 LoadFromOffset(kWord, tmp2, src,
3019 (Float32x4::value_offset() + 3 * kWordSize) - kHeapObjectTag);
3020 StoreToOffset(kWord, tmp1, dst,
3021 (Float32x4::value_offset() + 2 * kWordSize) - kHeapObjectTag);
3022 StoreToOffset(kWord, tmp2, dst,
3023 (Float32x4::value_offset() + 3 * kWordSize) - kHeapObjectTag);
3024 }
3025}
3026
3027
3028void Assembler::CopyFloat64x2Field(
3029 Register dst, Register src, Register tmp1, Register tmp2, DRegister dtmp) {
3030 if (TargetCPUFeatures::neon_supported()) {
3031 LoadMultipleDFromOffset(dtmp, 2, src,
3032 Float64x2::value_offset() - kHeapObjectTag);
3033 StoreMultipleDToOffset(dtmp, 2, dst,
3034 Float64x2::value_offset() - kHeapObjectTag);
3035 } else {
3036 LoadFromOffset(kWord, tmp1, src,
3037 (Float64x2::value_offset() + 0 * kWordSize) - kHeapObjectTag);
3038 LoadFromOffset(kWord, tmp2, src,
3039 (Float64x2::value_offset() + 1 * kWordSize) - kHeapObjectTag);
3040 StoreToOffset(kWord, tmp1, dst,
3041 (Float64x2::value_offset() + 0 * kWordSize) - kHeapObjectTag);
3042 StoreToOffset(kWord, tmp2, dst,
3043 (Float64x2::value_offset() + 1 * kWordSize) - kHeapObjectTag);
3044
3045 LoadFromOffset(kWord, tmp1, src,
3046 (Float64x2::value_offset() + 2 * kWordSize) - kHeapObjectTag);
3047 LoadFromOffset(kWord, tmp2, src,
3048 (Float64x2::value_offset() + 3 * kWordSize) - kHeapObjectTag);
3049 StoreToOffset(kWord, tmp1, dst,
3050 (Float64x2::value_offset() + 2 * kWordSize) - kHeapObjectTag);
3051 StoreToOffset(kWord, tmp2, dst,
3052 (Float64x2::value_offset() + 3 * kWordSize) - kHeapObjectTag);
3053 }
3054}
3055
3056
3057void Assembler::AddImmediate(Register rd, int32_t value, Condition cond) {
3058 AddImmediate(rd, rd, value, cond);
3059}
3060
3061
3062void Assembler::AddImmediate(Register rd, Register rn, int32_t value,
3063 Condition cond) {
3064 if (value == 0) {
3065 if (rd != rn) {
3066 mov(rd, Operand(rn), cond);
3067 }
3068 return;
3069 }
3070 // We prefer to select the shorter code sequence rather than selecting add for
3071 // positive values and sub for negatives ones, which would slightly improve
3072 // the readability of generated code for some constants.
3073 Operand o;
3074 if (Operand::CanHold(value, &o)) {
3075 add(rd, rn, o, cond);
3076 } else if (Operand::CanHold(-value, &o)) {
3077 sub(rd, rn, o, cond);
3078 } else {
3079 ASSERT(rn != IP);
3080 if (Operand::CanHold(~value, &o)) {
3081 mvn(IP, o, cond);
3082 add(rd, rn, Operand(IP), cond);
3083 } else if (Operand::CanHold(~(-value), &o)) {
3084 mvn(IP, o, cond);
3085 sub(rd, rn, Operand(IP), cond);
3086 } else {
3087 LoadDecodableImmediate(IP, value, cond);
3088 add(rd, rn, Operand(IP), cond);
3089 }
3090 }
3091}
3092
3093
3094void Assembler::AddImmediateSetFlags(Register rd, Register rn, int32_t value,
3095 Condition cond) {
3096 Operand o;
3097 if (Operand::CanHold(value, &o)) {
3098 // Handles value == kMinInt32.
3099 adds(rd, rn, o, cond);
3100 } else if (Operand::CanHold(-value, &o)) {
3101 ASSERT(value != kMinInt32); // Would cause erroneous overflow detection.
3102 subs(rd, rn, o, cond);
3103 } else {
3104 ASSERT(rn != IP);
3105 if (Operand::CanHold(~value, &o)) {
3106 mvn(IP, o, cond);
3107 adds(rd, rn, Operand(IP), cond);
3108 } else if (Operand::CanHold(~(-value), &o)) {
3109 ASSERT(value != kMinInt32); // Would cause erroneous overflow detection.
3110 mvn(IP, o, cond);
3111 subs(rd, rn, Operand(IP), cond);
3112 } else {
3113 LoadDecodableImmediate(IP, value, cond);
3114 adds(rd, rn, Operand(IP), cond);
3115 }
3116 }
3117}
3118
3119
3120void Assembler::SubImmediateSetFlags(Register rd, Register rn, int32_t value,
3121 Condition cond) {
3122 Operand o;
3123 if (Operand::CanHold(value, &o)) {
3124 // Handles value == kMinInt32.
3125 subs(rd, rn, o, cond);
3126 } else if (Operand::CanHold(-value, &o)) {
3127 ASSERT(value != kMinInt32); // Would cause erroneous overflow detection.
3128 adds(rd, rn, o, cond);
3129 } else {
3130 ASSERT(rn != IP);
3131 if (Operand::CanHold(~value, &o)) {
3132 mvn(IP, o, cond);
3133 subs(rd, rn, Operand(IP), cond);
3134 } else if (Operand::CanHold(~(-value), &o)) {
3135 ASSERT(value != kMinInt32); // Would cause erroneous overflow detection.
3136 mvn(IP, o, cond);
3137 adds(rd, rn, Operand(IP), cond);
3138 } else {
3139 LoadDecodableImmediate(IP, value, cond);
3140 subs(rd, rn, Operand(IP), cond);
3141 }
3142 }
3143}
3144
3145
3146void Assembler::AndImmediate(Register rd, Register rs, int32_t imm,
3147 Condition cond) {
3148 Operand o;
3149 if (Operand::CanHold(imm, &o)) {
3150 and_(rd, rs, Operand(o), cond);
3151 } else {
3152 LoadImmediate(TMP, imm, cond);
3153 and_(rd, rs, Operand(TMP), cond);
3154 }
3155}
3156
3157
3158void Assembler::CompareImmediate(Register rn, int32_t value, Condition cond) {
3159 Operand o;
3160 if (Operand::CanHold(value, &o)) {
3161 cmp(rn, o, cond);
3162 } else {
3163 ASSERT(rn != IP);
3164 LoadImmediate(IP, value, cond);
3165 cmp(rn, Operand(IP), cond);
3166 }
3167}
3168
3169
3170void Assembler::TestImmediate(Register rn, int32_t imm, Condition cond) {
3171 Operand o;
3172 if (Operand::CanHold(imm, &o)) {
3173 tst(rn, o, cond);
3174 } else {
3175 LoadImmediate(IP, imm);
3176 tst(rn, Operand(IP), cond);
3177 }
3178}
3179
3180void Assembler::IntegerDivide(Register result, Register left, Register right,
3181 DRegister tmpl, DRegister tmpr) {
3182 ASSERT(tmpl != tmpr);
3183 if (TargetCPUFeatures::integer_division_supported()) {
3184 sdiv(result, left, right);
3185 } else {
3186 ASSERT(TargetCPUFeatures::vfp_supported());
3187 SRegister stmpl = static_cast<SRegister>(2 * tmpl);
3188 SRegister stmpr = static_cast<SRegister>(2 * tmpr);
3189 vmovsr(stmpl, left);
3190 vcvtdi(tmpl, stmpl); // left is in tmpl.
3191 vmovsr(stmpr, right);
3192 vcvtdi(tmpr, stmpr); // right is in tmpr.
3193 vdivd(tmpr, tmpl, tmpr);
3194 vcvtid(stmpr, tmpr);
3195 vmovrs(result, stmpr);
3196 }
3197}
3198
3199
3200static int NumRegsBelowFP(RegList regs) {
3201 int count = 0;
3202 for (int i = 0; i < FP; i++) {
3203 if ((regs & (1 << i)) != 0) {
3204 count++;
3205 }
3206 }
3207 return count;
3208}
3209
3210
3211void Assembler::EnterFrame(RegList regs, intptr_t frame_size) {
3212 if (prologue_offset_ == -1) {
3213 prologue_offset_ = CodeSize();
3214 }
3215 PushList(regs);
3216 if ((regs & (1 << FP)) != 0) {
3217 // Set FP to the saved previous FP.
3218 add(FP, SP, Operand(4 * NumRegsBelowFP(regs)));
3219 }
3220 AddImmediate(SP, -frame_size);
3221}
3222
3223
3224void Assembler::LeaveFrame(RegList regs) {
3225 ASSERT((regs & (1 << PC)) == 0); // Must not pop PC.
3226 if ((regs & (1 << FP)) != 0) {
3227 // Use FP to set SP.
3228 sub(SP, FP, Operand(4 * NumRegsBelowFP(regs)));
3229 }
3230 PopList(regs);
3231}
3232
3233
3234void Assembler::Ret() {
3235 bx(LR);
3236}
3237
3238
3239void Assembler::ReserveAlignedFrameSpace(intptr_t frame_space) {
3240 // Reserve space for arguments and align frame before entering
3241 // the C++ world.
3242 AddImmediate(SP, -frame_space);
3243 if (OS::ActivationFrameAlignment() > 1) {
3244 bic(SP, SP, Operand(OS::ActivationFrameAlignment() - 1));
3245 }
3246}
3247
3248
3249void Assembler::EnterCallRuntimeFrame(intptr_t frame_space) {
3250 // Preserve volatile CPU registers and PP.
3251 EnterFrame(kDartVolatileCpuRegs | (1 << PP) | (1 << FP), 0);
3252 COMPILE_ASSERT((kDartVolatileCpuRegs & (1 << PP)) == 0);
3253
3254 // Preserve all volatile FPU registers.
3255 if (TargetCPUFeatures::vfp_supported()) {
3256 DRegister firstv = EvenDRegisterOf(kDartFirstVolatileFpuReg);
3257 DRegister lastv = OddDRegisterOf(kDartLastVolatileFpuReg);
3258 if ((lastv - firstv + 1) >= 16) {
3259 DRegister mid = static_cast<DRegister>(firstv + 16);
3260 vstmd(DB_W, SP, mid, lastv - mid + 1);
3261 vstmd(DB_W, SP, firstv, 16);
3262 } else {
3263 vstmd(DB_W, SP, firstv, lastv - firstv + 1);
3264 }
3265 }
3266
3267 LoadPoolPointer();
3268
3269 ReserveAlignedFrameSpace(frame_space);
3270}
3271
3272
3273void Assembler::LeaveCallRuntimeFrame() {
3274 // SP might have been modified to reserve space for arguments
3275 // and ensure proper alignment of the stack frame.
3276 // We need to restore it before restoring registers.
3277 const intptr_t kPushedFpuRegisterSize =
3278 TargetCPUFeatures::vfp_supported() ?
3279 kDartVolatileFpuRegCount * kFpuRegisterSize : 0;
3280
3281 COMPILE_ASSERT(PP < FP);
3282 COMPILE_ASSERT((kDartVolatileCpuRegs & (1 << PP)) == 0);
3283 // kVolatileCpuRegCount +1 for PP, -1 because even though LR is volatile,
3284 // it is pushed ahead of FP.
3285 const intptr_t kPushedRegistersSize =
3286 kDartVolatileCpuRegCount * kWordSize + kPushedFpuRegisterSize;
3287 AddImmediate(SP, FP, -kPushedRegistersSize);
3288
3289 // Restore all volatile FPU registers.
3290 if (TargetCPUFeatures::vfp_supported()) {
3291 DRegister firstv = EvenDRegisterOf(kDartFirstVolatileFpuReg);
3292 DRegister lastv = OddDRegisterOf(kDartLastVolatileFpuReg);
3293 if ((lastv - firstv + 1) >= 16) {
3294 DRegister mid = static_cast<DRegister>(firstv + 16);
3295 vldmd(IA_W, SP, firstv, 16);
3296 vldmd(IA_W, SP, mid, lastv - mid + 1);
3297 } else {
3298 vldmd(IA_W, SP, firstv, lastv - firstv + 1);
3299 }
3300 }
3301
3302 // Restore volatile CPU registers.
3303 LeaveFrame(kDartVolatileCpuRegs | (1 << PP) | (1 << FP));
3304}
3305
3306
3307void Assembler::CallRuntime(const RuntimeEntry& entry,
3308 intptr_t argument_count) {
3309 entry.Call(this, argument_count);
3310}
3311
3312
3313void Assembler::EnterDartFrame(intptr_t frame_size) {
3314 ASSERT(!constant_pool_allowed());
3315
3316 // Registers are pushed in descending order: R9 | R10 | R11 | R14.
3317 EnterFrame((1 << PP) | (1 << CODE_REG) | (1 << FP) | (1 << LR), 0);
3318
3319 // Setup pool pointer for this dart function.
3320 LoadPoolPointer();
3321
3322 // Reserve space for locals.
3323 AddImmediate(SP, -frame_size);
3324}
3325
3326
3327// On entry to a function compiled for OSR, the caller's frame pointer, the
3328// stack locals, and any copied parameters are already in place. The frame
3329// pointer is already set up. The PC marker is not correct for the
3330// optimized function and there may be extra space for spill slots to
3331// allocate. We must also set up the pool pointer for the function.
3332void Assembler::EnterOsrFrame(intptr_t extra_size) {
3333 ASSERT(!constant_pool_allowed());
3334 Comment("EnterOsrFrame");
3335 RestoreCodePointer();
3336 LoadPoolPointer();
3337
3338 AddImmediate(SP, -extra_size);
3339}
3340
3341
3342void Assembler::LeaveDartFrame(RestorePP restore_pp) {
3343 if (restore_pp == kRestoreCallerPP) {
3344 ldr(PP, Address(FP, kSavedCallerPpSlotFromFp * kWordSize));
3345 set_constant_pool_allowed(false);
3346 }
3347 Drop(2); // Drop saved PP, PC marker.
3348 LeaveFrame((1 << FP) | (1 << LR));
3349}
3350
3351
3352void Assembler::EnterStubFrame() {
3353 EnterDartFrame(0);
3354}
3355
3356
3357void Assembler::LeaveStubFrame() {
3358 LeaveDartFrame();
3359}
3360
3361
3362void Assembler::LoadAllocationStatsAddress(Register dest,
3363 intptr_t cid,
3364 bool inline_isolate) {
3365 ASSERT(dest != kNoRegister);
3366 ASSERT(dest != TMP);
3367 ASSERT(cid > 0);
3368 const intptr_t class_offset = ClassTable::ClassOffsetFor(cid);
3369 if (inline_isolate) {
3370 ASSERT(FLAG_allow_absolute_addresses);
3371 ClassTable* class_table = Isolate::Current()->class_table();
3372 ClassHeapStats** table_ptr = class_table->TableAddressFor(cid);
3373 if (cid < kNumPredefinedCids) {
3374 LoadImmediate(dest, reinterpret_cast<uword>(*table_ptr) + class_offset);
3375 } else {
3376 LoadImmediate(dest, reinterpret_cast<uword>(table_ptr));
3377 ldr(dest, Address(dest, 0));
3378 AddImmediate(dest, class_offset);
3379 }
3380 } else {
3381 LoadIsolate(dest);
3382 intptr_t table_offset =
3383 Isolate::class_table_offset() + ClassTable::TableOffsetFor(cid);
3384 ldr(dest, Address(dest, table_offset));
3385 AddImmediate(dest, class_offset);
3386 }
3387}
3388
3389
3390void Assembler::MaybeTraceAllocation(intptr_t cid,
3391 Register temp_reg,
3392 Label* trace,
3393 bool inline_isolate) {
3394 LoadAllocationStatsAddress(temp_reg, cid, inline_isolate);
3395 const uword state_offset = ClassHeapStats::state_offset();
3396 ldr(temp_reg, Address(temp_reg, state_offset));
3397 tst(temp_reg, Operand(ClassHeapStats::TraceAllocationMask()));
3398 b(trace, NE);
3399}
3400
3401
3402void Assembler::IncrementAllocationStats(Register stats_addr_reg,
3403 intptr_t cid,
3404 Heap::Space space) {
3405 ASSERT(stats_addr_reg != kNoRegister);
3406 ASSERT(stats_addr_reg != TMP);
3407 ASSERT(cid > 0);
3408 const uword count_field_offset = (space == Heap::kNew) ?
3409 ClassHeapStats::allocated_since_gc_new_space_offset() :
3410 ClassHeapStats::allocated_since_gc_old_space_offset();
3411 const Address& count_address = Address(stats_addr_reg, count_field_offset);
3412 ldr(TMP, count_address);
3413 AddImmediate(TMP, 1);
3414 str(TMP, count_address);
3415}
3416
3417
3418void Assembler::IncrementAllocationStatsWithSize(Register stats_addr_reg,
3419 Register size_reg,
3420 Heap::Space space) {
3421 ASSERT(stats_addr_reg != kNoRegister);
3422 ASSERT(stats_addr_reg != TMP);
3423 const uword count_field_offset = (space == Heap::kNew) ?
3424 ClassHeapStats::allocated_since_gc_new_space_offset() :
3425 ClassHeapStats::allocated_since_gc_old_space_offset();
3426 const uword size_field_offset = (space == Heap::kNew) ?
3427 ClassHeapStats::allocated_size_since_gc_new_space_offset() :
3428 ClassHeapStats::allocated_size_since_gc_old_space_offset();
3429 const Address& count_address = Address(stats_addr_reg, count_field_offset);
3430 const Address& size_address = Address(stats_addr_reg, size_field_offset);
3431 ldr(TMP, count_address);
3432 AddImmediate(TMP, 1);
3433 str(TMP, count_address);
3434 ldr(TMP, size_address);
3435 add(TMP, TMP, Operand(size_reg));
3436 str(TMP, size_address);
3437}
3438
3439
3440void Assembler::TryAllocate(const Class& cls,
3441 Label* failure,
3442 Register instance_reg,
3443 Register temp_reg) {
3444 ASSERT(failure != NULL);
3445 if (FLAG_inline_alloc) {
3446 ASSERT(instance_reg != temp_reg);
3447 ASSERT(temp_reg != IP);
3448 const intptr_t instance_size = cls.instance_size();
3449 ASSERT(instance_size != 0);
3450 // If this allocation is traced, program will jump to failure path
3451 // (i.e. the allocation stub) which will allocate the object and trace the
3452 // allocation call site.
3453 MaybeTraceAllocation(cls.id(), temp_reg, failure,
3454 /* inline_isolate = */ false);
3455 Heap::Space space = Heap::SpaceForAllocation(cls.id());
3456 ldr(temp_reg, Address(THR, Thread::heap_offset()));
3457 ldr(instance_reg, Address(temp_reg, Heap::TopOffset(space)));
3458 // TODO(koda): Protect against unsigned overflow here.
3459 AddImmediateSetFlags(instance_reg, instance_reg, instance_size);
3460
3461 // instance_reg: potential next object start.
3462 ldr(IP, Address(temp_reg, Heap::EndOffset(space)));
3463 cmp(IP, Operand(instance_reg));
3464 // fail if heap end unsigned less than or equal to instance_reg.
3465 b(failure, LS);
3466
3467 // Successfully allocated the object, now update top to point to
3468 // next object start and store the class in the class field of object.
3469 str(instance_reg, Address(temp_reg, Heap::TopOffset(space)));
3470
3471 LoadAllocationStatsAddress(temp_reg, cls.id(),
3472 /* inline_isolate = */ false);
3473
3474 ASSERT(instance_size >= kHeapObjectTag);
3475 AddImmediate(instance_reg, -instance_size + kHeapObjectTag);
3476
3477 uword tags = 0;
3478 tags = RawObject::SizeTag::update(instance_size, tags);
3479 ASSERT(cls.id() != kIllegalCid);
3480 tags = RawObject::ClassIdTag::update(cls.id(), tags);
3481 LoadImmediate(IP, tags);
3482 str(IP, FieldAddress(instance_reg, Object::tags_offset()));
3483
3484 IncrementAllocationStats(temp_reg, cls.id(), space);
3485 } else {
3486 b(failure);
3487 }
3488}
3489
3490
3491void Assembler::TryAllocateArray(intptr_t cid,
3492 intptr_t instance_size,
3493 Label* failure,
3494 Register instance,
3495 Register end_address,
3496 Register temp1,
3497 Register temp2) {
3498 if (FLAG_inline_alloc) {
3499 // If this allocation is traced, program will jump to failure path
3500 // (i.e. the allocation stub) which will allocate the object and trace the
3501 // allocation call site.
3502 MaybeTraceAllocation(cid, temp1, failure, /* inline_isolate = */ false);
3503 Heap::Space space = Heap::SpaceForAllocation(cid);
3504 ldr(temp1, Address(THR, Thread::heap_offset()));
3505 // Potential new object start.
3506 ldr(instance, Address(temp1, Heap::TopOffset(space)));
3507 AddImmediateSetFlags(end_address, instance, instance_size);
3508 b(failure, CS); // Branch if unsigned overflow.
3509
3510 // Check if the allocation fits into the remaining space.
3511 // instance: potential new object start.
3512 // end_address: potential next object start.
3513 ldr(temp2, Address(temp1, Heap::EndOffset(space)));
3514 cmp(end_address, Operand(temp2));
3515 b(failure, CS);
3516
3517 LoadAllocationStatsAddress(temp2, cid, /* inline_isolate = */ false);
3518
3519 // Successfully allocated the object(s), now update top to point to
3520 // next object start and initialize the object.
3521 str(end_address, Address(temp1, Heap::TopOffset(space)));
3522 add(instance, instance, Operand(kHeapObjectTag));
3523
3524 // Initialize the tags.
3525 // instance: new object start as a tagged pointer.
3526 uword tags = 0;
3527 tags = RawObject::ClassIdTag::update(cid, tags);
3528 tags = RawObject::SizeTag::update(instance_size, tags);
3529 LoadImmediate(temp1, tags);
3530 str(temp1, FieldAddress(instance, Array::tags_offset())); // Store tags.
3531
3532 LoadImmediate(temp1, instance_size);
3533 IncrementAllocationStatsWithSize(temp2, temp1, space);
3534 } else {
3535 b(failure);
3536 }
3537}
3538
3539
3540void Assembler::Stop(const char* message) {
3541 if (FLAG_print_stop_message) {
3542 PushList((1 << R0) | (1 << IP) | (1 << LR)); // Preserve R0, IP, LR.
3543 LoadImmediate(R0, reinterpret_cast<int32_t>(message));
3544 // PrintStopMessage() preserves all registers.
3545 BranchLink(&StubCode::PrintStopMessage_entry()->label());
3546 PopList((1 << R0) | (1 << IP) | (1 << LR)); // Restore R0, IP, LR.
3547 }
3548 // Emit the message address before the svc instruction, so that we can
3549 // 'unstop' and continue execution in the simulator or jump to the next
3550 // instruction in gdb.
3551 Label stop;
3552 b(&stop);
3553 Emit(reinterpret_cast<int32_t>(message));
3554 Bind(&stop);
3555 bkpt(Instr::kStopMessageCode);
3556}
3557
3558
3559Address Assembler::ElementAddressForIntIndex(bool is_load,
3560 bool is_external,
3561 intptr_t cid,
3562 intptr_t index_scale,
3563 Register array,
3564 intptr_t index,
3565 Register temp) {
3566 const int64_t offset_base =
3567 (is_external ? 0 : (Instance::DataOffsetFor(cid) - kHeapObjectTag));
3568 const int64_t offset = offset_base +
3569 static_cast<int64_t>(index) * index_scale;
3570 ASSERT(Utils::IsInt(32, offset));
3571
3572 if (Address::CanHoldImmediateOffset(is_load, cid, offset)) {
3573 return Address(array, static_cast<int32_t>(offset));
3574 } else {
3575 ASSERT(Address::CanHoldImmediateOffset(is_load, cid, offset - offset_base));
3576 AddImmediate(temp, array, static_cast<int32_t>(offset_base));
3577 return Address(temp, static_cast<int32_t>(offset - offset_base));
3578 }
3579}
3580
3581
3582Address Assembler::ElementAddressForRegIndex(bool is_load,
3583 bool is_external,
3584 intptr_t cid,
3585 intptr_t index_scale,
3586 Register array,
3587 Register index) {
3588 // Note that index is expected smi-tagged, (i.e, LSL 1) for all arrays.
3589 const intptr_t shift = Utils::ShiftForPowerOfTwo(index_scale) - kSmiTagShift;
3590 int32_t offset =
3591 is_external ? 0 : (Instance::DataOffsetFor(cid) - kHeapObjectTag);
3592 const OperandSize size = Address::OperandSizeFor(cid);
3593 ASSERT(array != IP);
3594 ASSERT(index != IP);
3595 const Register base = is_load ? IP : index;
3596 if ((offset != 0) ||
3597 (size == kSWord) || (size == kDWord) || (size == kRegList)) {
3598 if (shift < 0) {
3599 ASSERT(shift == -1);
3600 add(base, array, Operand(index, ASR, 1));
3601 } else {
3602 add(base, array, Operand(index, LSL, shift));
3603 }
3604 } else {
3605 if (shift < 0) {
3606 ASSERT(shift == -1);
3607 return Address(array, index, ASR, 1);
3608 } else {
3609 return Address(array, index, LSL, shift);
3610 }
3611 }
3612 int32_t offset_mask = 0;
3613 if ((is_load && !Address::CanHoldLoadOffset(size,
3614 offset,
3615 &offset_mask)) ||
3616 (!is_load && !Address::CanHoldStoreOffset(size,
3617 offset,
3618 &offset_mask))) {
3619 AddImmediate(base, offset & ~offset_mask);
3620 offset = offset & offset_mask;
3621 }
3622 return Address(base, offset);
3623}
3624
3625
3626static const char* cpu_reg_names[kNumberOfCpuRegisters] = {
3627 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
3628 "r8", "ctx", "pp", "fp", "ip", "sp", "lr", "pc",
3629};
3630
3631
3632const char* Assembler::RegisterName(Register reg) {
3633 ASSERT((0 <= reg) && (reg < kNumberOfCpuRegisters));
3634 return cpu_reg_names[reg];
3635}
3636
3637
3638static const char* fpu_reg_names[kNumberOfFpuRegisters] = {
3639 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
3640#if defined(VFPv3_D32)
3641 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15",
3642#endif
3643};
3644
3645
3646const char* Assembler::FpuRegisterName(FpuRegister reg) {
3647 ASSERT((0 <= reg) && (reg < kNumberOfFpuRegisters));
3648 return fpu_reg_names[reg];
3649}
3650
3651} // namespace dart
3652
3653#endif // defined TARGET_ARCH_ARM