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swiftshader / SwiftShader / refs/heads/master / . / third_party / llvm-16.0 / configs / common / lib / Target / X86 / X86GenRegisterInfo.inc
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/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|* *|
|* Target Register Enum Values *|
|* *|
|* Automatically generated file, do not edit! *|
|* *|
\*===----------------------------------------------------------------------===*/
#ifdef GET_REGINFO_ENUM
#undef GET_REGINFO_ENUM
namespace llvm {
class MCRegisterClass;
extern const MCRegisterClass X86MCRegisterClasses[];
namespace X86 {
enum {
NoRegister,
AH = 1,
AL = 2,
AX = 3,
BH = 4,
BL = 5,
BP = 6,
BPH = 7,
BPL = 8,
BX = 9,
CH = 10,
CL = 11,
CS = 12,
CX = 13,
DF = 14,
DH = 15,
DI = 16,
DIH = 17,
DIL = 18,
DL = 19,
DS = 20,
DX = 21,
EAX = 22,
EBP = 23,
EBX = 24,
ECX = 25,
EDI = 26,
EDX = 27,
EFLAGS = 28,
EIP = 29,
EIZ = 30,
ES = 31,
ESI = 32,
ESP = 33,
FPCW = 34,
FPSW = 35,
FS = 36,
FS_BASE = 37,
GS = 38,
GS_BASE = 39,
HAX = 40,
HBP = 41,
HBX = 42,
HCX = 43,
HDI = 44,
HDX = 45,
HIP = 46,
HSI = 47,
HSP = 48,
IP = 49,
MXCSR = 50,
RAX = 51,
RBP = 52,
RBX = 53,
RCX = 54,
RDI = 55,
RDX = 56,
RFLAGS = 57,
RIP = 58,
RIZ = 59,
RSI = 60,
RSP = 61,
SI = 62,
SIH = 63,
SIL = 64,
SP = 65,
SPH = 66,
SPL = 67,
SS = 68,
SSP = 69,
TMMCFG = 70,
_EFLAGS = 71,
CR0 = 72,
CR1 = 73,
CR2 = 74,
CR3 = 75,
CR4 = 76,
CR5 = 77,
CR6 = 78,
CR7 = 79,
CR8 = 80,
CR9 = 81,
CR10 = 82,
CR11 = 83,
CR12 = 84,
CR13 = 85,
CR14 = 86,
CR15 = 87,
DR0 = 88,
DR1 = 89,
DR2 = 90,
DR3 = 91,
DR4 = 92,
DR5 = 93,
DR6 = 94,
DR7 = 95,
DR8 = 96,
DR9 = 97,
DR10 = 98,
DR11 = 99,
DR12 = 100,
DR13 = 101,
DR14 = 102,
DR15 = 103,
FP0 = 104,
FP1 = 105,
FP2 = 106,
FP3 = 107,
FP4 = 108,
FP5 = 109,
FP6 = 110,
FP7 = 111,
K0 = 112,
K1 = 113,
K2 = 114,
K3 = 115,
K4 = 116,
K5 = 117,
K6 = 118,
K7 = 119,
MM0 = 120,
MM1 = 121,
MM2 = 122,
MM3 = 123,
MM4 = 124,
MM5 = 125,
MM6 = 126,
MM7 = 127,
R8 = 128,
R9 = 129,
R10 = 130,
R11 = 131,
R12 = 132,
R13 = 133,
R14 = 134,
R15 = 135,
ST0 = 136,
ST1 = 137,
ST2 = 138,
ST3 = 139,
ST4 = 140,
ST5 = 141,
ST6 = 142,
ST7 = 143,
TMM0 = 144,
TMM1 = 145,
TMM2 = 146,
TMM3 = 147,
TMM4 = 148,
TMM5 = 149,
TMM6 = 150,
TMM7 = 151,
XMM0 = 152,
XMM1 = 153,
XMM2 = 154,
XMM3 = 155,
XMM4 = 156,
XMM5 = 157,
XMM6 = 158,
XMM7 = 159,
XMM8 = 160,
XMM9 = 161,
XMM10 = 162,
XMM11 = 163,
XMM12 = 164,
XMM13 = 165,
XMM14 = 166,
XMM15 = 167,
XMM16 = 168,
XMM17 = 169,
XMM18 = 170,
XMM19 = 171,
XMM20 = 172,
XMM21 = 173,
XMM22 = 174,
XMM23 = 175,
XMM24 = 176,
XMM25 = 177,
XMM26 = 178,
XMM27 = 179,
XMM28 = 180,
XMM29 = 181,
XMM30 = 182,
XMM31 = 183,
YMM0 = 184,
YMM1 = 185,
YMM2 = 186,
YMM3 = 187,
YMM4 = 188,
YMM5 = 189,
YMM6 = 190,
YMM7 = 191,
YMM8 = 192,
YMM9 = 193,
YMM10 = 194,
YMM11 = 195,
YMM12 = 196,
YMM13 = 197,
YMM14 = 198,
YMM15 = 199,
YMM16 = 200,
YMM17 = 201,
YMM18 = 202,
YMM19 = 203,
YMM20 = 204,
YMM21 = 205,
YMM22 = 206,
YMM23 = 207,
YMM24 = 208,
YMM25 = 209,
YMM26 = 210,
YMM27 = 211,
YMM28 = 212,
YMM29 = 213,
YMM30 = 214,
YMM31 = 215,
ZMM0 = 216,
ZMM1 = 217,
ZMM2 = 218,
ZMM3 = 219,
ZMM4 = 220,
ZMM5 = 221,
ZMM6 = 222,
ZMM7 = 223,
ZMM8 = 224,
ZMM9 = 225,
ZMM10 = 226,
ZMM11 = 227,
ZMM12 = 228,
ZMM13 = 229,
ZMM14 = 230,
ZMM15 = 231,
ZMM16 = 232,
ZMM17 = 233,
ZMM18 = 234,
ZMM19 = 235,
ZMM20 = 236,
ZMM21 = 237,
ZMM22 = 238,
ZMM23 = 239,
ZMM24 = 240,
ZMM25 = 241,
ZMM26 = 242,
ZMM27 = 243,
ZMM28 = 244,
ZMM29 = 245,
ZMM30 = 246,
ZMM31 = 247,
R8B = 248,
R9B = 249,
R10B = 250,
R11B = 251,
R12B = 252,
R13B = 253,
R14B = 254,
R15B = 255,
R8BH = 256,
R9BH = 257,
R10BH = 258,
R11BH = 259,
R12BH = 260,
R13BH = 261,
R14BH = 262,
R15BH = 263,
R8D = 264,
R9D = 265,
R10D = 266,
R11D = 267,
R12D = 268,
R13D = 269,
R14D = 270,
R15D = 271,
R8W = 272,
R9W = 273,
R10W = 274,
R11W = 275,
R12W = 276,
R13W = 277,
R14W = 278,
R15W = 279,
R8WH = 280,
R9WH = 281,
R10WH = 282,
R11WH = 283,
R12WH = 284,
R13WH = 285,
R14WH = 286,
R15WH = 287,
K0_K1 = 288,
K2_K3 = 289,
K4_K5 = 290,
K6_K7 = 291,
NUM_TARGET_REGS // 292
};
} // end namespace X86
// Register classes
namespace X86 {
enum {
GR8RegClassID = 0,
GRH8RegClassID = 1,
GR8_NOREXRegClassID = 2,
GR8_ABCD_HRegClassID = 3,
GR8_ABCD_LRegClassID = 4,
GRH16RegClassID = 5,
GR16RegClassID = 6,
GR16_NOREXRegClassID = 7,
VK1RegClassID = 8,
VK16RegClassID = 9,
VK2RegClassID = 10,
VK4RegClassID = 11,
VK8RegClassID = 12,
VK16WMRegClassID = 13,
VK1WMRegClassID = 14,
VK2WMRegClassID = 15,
VK4WMRegClassID = 16,
VK8WMRegClassID = 17,
SEGMENT_REGRegClassID = 18,
GR16_ABCDRegClassID = 19,
FPCCRRegClassID = 20,
FR16XRegClassID = 21,
FR16RegClassID = 22,
VK16PAIRRegClassID = 23,
VK1PAIRRegClassID = 24,
VK2PAIRRegClassID = 25,
VK4PAIRRegClassID = 26,
VK8PAIRRegClassID = 27,
VK16PAIR_with_sub_mask_0_in_VK16WMRegClassID = 28,
FR32XRegClassID = 29,
LOW32_ADDR_ACCESS_RBPRegClassID = 30,
LOW32_ADDR_ACCESSRegClassID = 31,
LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID = 32,
DEBUG_REGRegClassID = 33,
FR32RegClassID = 34,
GR32RegClassID = 35,
GR32_NOSPRegClassID = 36,
LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID = 37,
GR32_NOREXRegClassID = 38,
VK32RegClassID = 39,
GR32_NOREX_NOSPRegClassID = 40,
RFP32RegClassID = 41,
VK32WMRegClassID = 42,
GR32_ABCDRegClassID = 43,
GR32_TCRegClassID = 44,
GR32_ABCD_and_GR32_TCRegClassID = 45,
GR32_ADRegClassID = 46,
GR32_BPSPRegClassID = 47,
GR32_BSIRegClassID = 48,
GR32_CBRegClassID = 49,
GR32_DCRegClassID = 50,
GR32_DIBPRegClassID = 51,
GR32_SIDIRegClassID = 52,
LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClassID = 53,
CCRRegClassID = 54,
DFCCRRegClassID = 55,
GR32_ABCD_and_GR32_BSIRegClassID = 56,
GR32_AD_and_GR32_DCRegClassID = 57,
GR32_BPSP_and_GR32_DIBPRegClassID = 58,
GR32_BPSP_and_GR32_TCRegClassID = 59,
GR32_BSI_and_GR32_SIDIRegClassID = 60,
GR32_CB_and_GR32_DCRegClassID = 61,
GR32_DIBP_and_GR32_SIDIRegClassID = 62,
LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitRegClassID = 63,
LOW32_ADDR_ACCESS_with_sub_32bitRegClassID = 64,
RFP64RegClassID = 65,
FR64XRegClassID = 66,
GR64RegClassID = 67,
CONTROL_REGRegClassID = 68,
FR64RegClassID = 69,
GR64_with_sub_8bitRegClassID = 70,
GR64_NOSPRegClassID = 71,
GR64PLTSafeRegClassID = 72,
GR64_TCRegClassID = 73,
GR64_NOREXRegClassID = 74,
GR64_TCW64RegClassID = 75,
GR64_TC_with_sub_8bitRegClassID = 76,
GR64_NOSP_and_GR64_TCRegClassID = 77,
GR64_TCW64_with_sub_8bitRegClassID = 78,
GR64_TC_and_GR64_TCW64RegClassID = 79,
GR64_with_sub_16bit_in_GR16_NOREXRegClassID = 80,
VK64RegClassID = 81,
VR64RegClassID = 82,
GR64PLTSafe_and_GR64_TCRegClassID = 83,
GR64_NOREX_NOSPRegClassID = 84,
GR64_NOREX_and_GR64_TCRegClassID = 85,
GR64_NOSP_and_GR64_TCW64RegClassID = 86,
GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID = 87,
VK64WMRegClassID = 88,
GR64_TC_and_GR64_NOSP_and_GR64_TCW64RegClassID = 89,
GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID = 90,
GR64PLTSafe_and_GR64_TCW64RegClassID = 91,
GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClassID = 92,
GR64_NOREX_and_GR64_TCW64RegClassID = 93,
GR64_ABCDRegClassID = 94,
GR64_with_sub_32bit_in_GR32_TCRegClassID = 95,
GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClassID = 96,
GR64_ADRegClassID = 97,
GR64_and_LOW32_ADDR_ACCESS_RBPRegClassID = 98,
GR64_with_sub_32bit_in_GR32_BPSPRegClassID = 99,
GR64_with_sub_32bit_in_GR32_BSIRegClassID = 100,
GR64_with_sub_32bit_in_GR32_CBRegClassID = 101,
GR64_with_sub_32bit_in_GR32_DCRegClassID = 102,
GR64_with_sub_32bit_in_GR32_DIBPRegClassID = 103,
GR64_with_sub_32bit_in_GR32_SIDIRegClassID = 104,
GR64_and_LOW32_ADDR_ACCESSRegClassID = 105,
GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIRegClassID = 106,
GR64_with_sub_32bit_in_GR32_AD_and_GR32_DCRegClassID = 107,
GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPRegClassID = 108,
GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCRegClassID = 109,
GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIRegClassID = 110,
GR64_with_sub_32bit_in_GR32_CB_and_GR32_DCRegClassID = 111,
GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIRegClassID = 112,
RSTRegClassID = 113,
RFP80RegClassID = 114,
RFP80_7RegClassID = 115,
VR128XRegClassID = 116,
VR128RegClassID = 117,
VR256XRegClassID = 118,
VR256RegClassID = 119,
VR512RegClassID = 120,
VR512_0_15RegClassID = 121,
TILERegClassID = 122,
};
} // end namespace X86
// Subregister indices
namespace X86 {
enum : uint16_t {
NoSubRegister,
sub_8bit, // 1
sub_8bit_hi, // 2
sub_8bit_hi_phony, // 3
sub_16bit, // 4
sub_16bit_hi, // 5
sub_32bit, // 6
sub_mask_0, // 7
sub_mask_1, // 8
sub_xmm, // 9
sub_ymm, // 10
NUM_TARGET_SUBREGS
};
} // end namespace X86
// Register pressure sets enum.
namespace X86 {
enum RegisterPressureSets {
SEGMENT_REG = 0,
GR32_BPSP = 1,
LOW32_ADDR_ACCESS_with_sub_32bit = 2,
GR32_BSI = 3,
GR32_SIDI = 4,
GR32_DIBP_with_GR32_SIDI = 5,
GR32_DIBP_with_LOW32_ADDR_ACCESS_with_sub_32bit = 6,
RFP32 = 7,
GR8_ABCD_H_with_GR32_BSI = 8,
GR8_ABCD_L_with_GR32_BSI = 9,
VK1 = 10,
VR64 = 11,
TILE = 12,
GR8_NOREX = 13,
GR32_TC = 14,
GR32_BPSP_with_GR32_TC = 15,
FR16 = 16,
DEBUG_REG = 17,
CONTROL_REG = 18,
GR64_NOREX = 19,
GR64_TCW64 = 20,
GR32_BPSP_with_GR64_TCW64 = 21,
GR8 = 22,
GR8_with_GR32_DIBP = 23,
GR8_with_GR32_BSI = 24,
GR64_TC_with_GR64_TCW64 = 25,
GR8_with_LOW32_ADDR_ACCESS_with_sub_32bit = 26,
GR8_with_GR64_NOREX = 27,
GR64_TC = 28,
GR8_with_GR64_TCW64 = 29,
GR8_with_GR64_TC = 30,
GR8_with_GR64PLTSafe = 31,
FR16X = 32,
GR16 = 33,
};
} // end namespace X86
} // end namespace llvm
#endif // GET_REGINFO_ENUM
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|* *|
|* MC Register Information *|
|* *|
|* Automatically generated file, do not edit! *|
|* *|
\*===----------------------------------------------------------------------===*/
#ifdef GET_REGINFO_MC_DESC
#undef GET_REGINFO_MC_DESC
namespace llvm {
extern const MCPhysReg X86RegDiffLists[] = {
/* 0 */ 0, 1, 0,
/* 3 */ 64845, 1, 1, 0,
/* 7 */ 65253, 1, 1, 0,
/* 11 */ 65382, 1, 1, 0,
/* 15 */ 65466, 1, 1, 0,
/* 19 */ 2, 1, 0,
/* 22 */ 4, 1, 0,
/* 25 */ 6, 1, 0,
/* 28 */ 11, 1, 0,
/* 31 */ 22, 1, 0,
/* 34 */ 26, 1, 0,
/* 37 */ 29, 1, 0,
/* 40 */ 64821, 1, 0,
/* 43 */ 65045, 1, 0,
/* 46 */ 65360, 1, 0,
/* 49 */ 65361, 1, 0,
/* 52 */ 65362, 1, 0,
/* 55 */ 65363, 1, 0,
/* 58 */ 10, 3, 0,
/* 61 */ 4, 0,
/* 63 */ 5, 0,
/* 65 */ 65272, 1, 7, 0,
/* 69 */ 65417, 1, 7, 0,
/* 73 */ 10, 3, 7, 0,
/* 77 */ 65512, 8, 0,
/* 80 */ 65326, 1, 11, 0,
/* 84 */ 65332, 1, 11, 0,
/* 88 */ 65442, 1, 11, 0,
/* 92 */ 65448, 1, 11, 0,
/* 96 */ 12, 0,
/* 98 */ 65326, 1, 14, 0,
/* 102 */ 65332, 1, 14, 0,
/* 106 */ 65442, 1, 14, 0,
/* 110 */ 65448, 1, 14, 0,
/* 114 */ 21, 0,
/* 116 */ 22, 0,
/* 118 */ 136, 8, 65512, 8, 24, 0,
/* 124 */ 26, 0,
/* 126 */ 65507, 65526, 2, 65535, 27, 0,
/* 132 */ 65534, 65504, 28, 0,
/* 136 */ 65535, 65504, 28, 0,
/* 140 */ 65534, 65506, 28, 0,
/* 144 */ 65535, 65506, 28, 0,
/* 148 */ 65521, 28, 0,
/* 151 */ 2, 6, 29, 0,
/* 155 */ 6, 6, 29, 0,
/* 159 */ 65534, 10, 29, 0,
/* 163 */ 65535, 10, 29, 0,
/* 167 */ 2, 12, 29, 0,
/* 171 */ 3, 12, 29, 0,
/* 175 */ 4, 15, 29, 0,
/* 179 */ 5, 15, 29, 0,
/* 183 */ 65534, 17, 29, 0,
/* 187 */ 65535, 17, 29, 0,
/* 191 */ 1, 19, 29, 0,
/* 195 */ 2, 19, 29, 0,
/* 199 */ 65516, 29, 0,
/* 202 */ 65518, 29, 0,
/* 205 */ 65519, 29, 0,
/* 208 */ 65507, 65530, 65534, 65532, 30, 0,
/* 214 */ 32, 32, 0,
/* 217 */ 65507, 65524, 65534, 65535, 33, 0,
/* 223 */ 65507, 65519, 2, 65535, 34, 0,
/* 229 */ 65507, 65521, 65532, 65535, 38, 0,
/* 235 */ 65507, 65517, 65535, 65535, 39, 0,
/* 241 */ 40, 0,
/* 243 */ 172, 0,
/* 245 */ 173, 0,
/* 247 */ 174, 0,
/* 249 */ 175, 0,
/* 251 */ 176, 0,
/* 253 */ 64761, 0,
/* 255 */ 64799, 0,
/* 257 */ 64870, 0,
/* 259 */ 64893, 0,
/* 261 */ 65520, 65400, 0,
/* 264 */ 16, 65528, 65400, 0,
/* 268 */ 24, 65528, 65400, 0,
/* 272 */ 65421, 0,
/* 274 */ 65423, 0,
/* 276 */ 65461, 0,
/* 278 */ 65493, 0,
/* 280 */ 65504, 65504, 0,
/* 283 */ 65509, 0,
/* 285 */ 65511, 0,
/* 287 */ 65508, 32, 2, 65535, 65518, 0,
/* 293 */ 65508, 30, 2, 65535, 65520, 0,
/* 299 */ 65525, 0,
/* 301 */ 65530, 0,
/* 303 */ 65531, 0,
/* 305 */ 65534, 65532, 0,
/* 308 */ 65507, 20, 65533, 0,
/* 312 */ 65534, 0,
/* 314 */ 2, 65535, 0,
/* 317 */ 65532, 65535, 0,
/* 320 */ 65534, 65535, 0,
/* 323 */ 65535, 65535, 0,
};
extern const LaneBitmask X86LaneMaskLists[] = {
/* 0 */ LaneBitmask(0x0000000000000000), LaneBitmask::getAll(),
/* 2 */ LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000001), LaneBitmask::getAll(),
/* 5 */ LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000000004), LaneBitmask::getAll(),
/* 8 */ LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000000008), LaneBitmask::getAll(),
/* 12 */ LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask::getAll(),
/* 16 */ LaneBitmask(0x0000000000000007), LaneBitmask(0x0000000000000008), LaneBitmask::getAll(),
/* 19 */ LaneBitmask(0x0000000000000010), LaneBitmask(0x0000000000000020), LaneBitmask::getAll(),
/* 22 */ LaneBitmask(0x0000000000000040), LaneBitmask::getAll(),
};
extern const uint16_t X86SubRegIdxLists[] = {
/* 0 */ 1, 2, 0,
/* 3 */ 1, 3, 0,
/* 6 */ 6, 4, 1, 2, 5, 0,
/* 12 */ 6, 4, 1, 3, 5, 0,
/* 18 */ 6, 4, 5, 0,
/* 22 */ 7, 8, 0,
/* 25 */ 10, 9, 0,
};
extern const MCRegisterInfo::SubRegCoveredBits X86SubRegIdxRanges[] = {
{ 65535, 65535 },
{ 0, 8 }, // sub_8bit
{ 8, 8 }, // sub_8bit_hi
{ 8, 8 }, // sub_8bit_hi_phony
{ 0, 16 }, // sub_16bit
{ 16, 16 }, // sub_16bit_hi
{ 0, 32 }, // sub_32bit
{ 0, 65535 }, // sub_mask_0
{ 65535, 65535 }, // sub_mask_1
{ 0, 128 }, // sub_xmm
{ 0, 256 }, // sub_ymm
};
extern const char X86RegStrings[] = {
/* 0 */ 'X', 'M', 'M', '1', '0', 0,
/* 6 */ 'Y', 'M', 'M', '1', '0', 0,
/* 12 */ 'Z', 'M', 'M', '1', '0', 0,
/* 18 */ 'C', 'R', '1', '0', 0,
/* 23 */ 'D', 'R', '1', '0', 0,
/* 28 */ 'X', 'M', 'M', '2', '0', 0,
/* 34 */ 'Y', 'M', 'M', '2', '0', 0,
/* 40 */ 'Z', 'M', 'M', '2', '0', 0,
/* 46 */ 'X', 'M', 'M', '3', '0', 0,
/* 52 */ 'Y', 'M', 'M', '3', '0', 0,
/* 58 */ 'Z', 'M', 'M', '3', '0', 0,
/* 64 */ 'K', '0', 0,
/* 67 */ 'T', 'M', 'M', '0', 0,
/* 72 */ 'X', 'M', 'M', '0', 0,
/* 77 */ 'Y', 'M', 'M', '0', 0,
/* 82 */ 'Z', 'M', 'M', '0', 0,
/* 87 */ 'F', 'P', '0', 0,
/* 91 */ 'C', 'R', '0', 0,
/* 95 */ 'D', 'R', '0', 0,
/* 99 */ 'S', 'T', '0', 0,
/* 103 */ 'X', 'M', 'M', '1', '1', 0,
/* 109 */ 'Y', 'M', 'M', '1', '1', 0,
/* 115 */ 'Z', 'M', 'M', '1', '1', 0,
/* 121 */ 'C', 'R', '1', '1', 0,
/* 126 */ 'D', 'R', '1', '1', 0,
/* 131 */ 'X', 'M', 'M', '2', '1', 0,
/* 137 */ 'Y', 'M', 'M', '2', '1', 0,
/* 143 */ 'Z', 'M', 'M', '2', '1', 0,
/* 149 */ 'X', 'M', 'M', '3', '1', 0,
/* 155 */ 'Y', 'M', 'M', '3', '1', 0,
/* 161 */ 'Z', 'M', 'M', '3', '1', 0,
/* 167 */ 'K', '0', '_', 'K', '1', 0,
/* 173 */ 'T', 'M', 'M', '1', 0,
/* 178 */ 'X', 'M', 'M', '1', 0,
/* 183 */ 'Y', 'M', 'M', '1', 0,
/* 188 */ 'Z', 'M', 'M', '1', 0,
/* 193 */ 'F', 'P', '1', 0,
/* 197 */ 'C', 'R', '1', 0,
/* 201 */ 'D', 'R', '1', 0,
/* 205 */ 'S', 'T', '1', 0,
/* 209 */ 'X', 'M', 'M', '1', '2', 0,
/* 215 */ 'Y', 'M', 'M', '1', '2', 0,
/* 221 */ 'Z', 'M', 'M', '1', '2', 0,
/* 227 */ 'C', 'R', '1', '2', 0,
/* 232 */ 'D', 'R', '1', '2', 0,
/* 237 */ 'X', 'M', 'M', '2', '2', 0,
/* 243 */ 'Y', 'M', 'M', '2', '2', 0,
/* 249 */ 'Z', 'M', 'M', '2', '2', 0,
/* 255 */ 'K', '2', 0,
/* 258 */ 'T', 'M', 'M', '2', 0,
/* 263 */ 'X', 'M', 'M', '2', 0,
/* 268 */ 'Y', 'M', 'M', '2', 0,
/* 273 */ 'Z', 'M', 'M', '2', 0,
/* 278 */ 'F', 'P', '2', 0,
/* 282 */ 'C', 'R', '2', 0,
/* 286 */ 'D', 'R', '2', 0,
/* 290 */ 'S', 'T', '2', 0,
/* 294 */ 'X', 'M', 'M', '1', '3', 0,
/* 300 */ 'Y', 'M', 'M', '1', '3', 0,
/* 306 */ 'Z', 'M', 'M', '1', '3', 0,
/* 312 */ 'C', 'R', '1', '3', 0,
/* 317 */ 'D', 'R', '1', '3', 0,
/* 322 */ 'X', 'M', 'M', '2', '3', 0,
/* 328 */ 'Y', 'M', 'M', '2', '3', 0,
/* 334 */ 'Z', 'M', 'M', '2', '3', 0,
/* 340 */ 'K', '2', '_', 'K', '3', 0,
/* 346 */ 'T', 'M', 'M', '3', 0,
/* 351 */ 'X', 'M', 'M', '3', 0,
/* 356 */ 'Y', 'M', 'M', '3', 0,
/* 361 */ 'Z', 'M', 'M', '3', 0,
/* 366 */ 'F', 'P', '3', 0,
/* 370 */ 'C', 'R', '3', 0,
/* 374 */ 'D', 'R', '3', 0,
/* 378 */ 'S', 'T', '3', 0,
/* 382 */ 'X', 'M', 'M', '1', '4', 0,
/* 388 */ 'Y', 'M', 'M', '1', '4', 0,
/* 394 */ 'Z', 'M', 'M', '1', '4', 0,
/* 400 */ 'C', 'R', '1', '4', 0,
/* 405 */ 'D', 'R', '1', '4', 0,
/* 410 */ 'X', 'M', 'M', '2', '4', 0,
/* 416 */ 'Y', 'M', 'M', '2', '4', 0,
/* 422 */ 'Z', 'M', 'M', '2', '4', 0,
/* 428 */ 'K', '4', 0,
/* 431 */ 'T', 'M', 'M', '4', 0,
/* 436 */ 'X', 'M', 'M', '4', 0,
/* 441 */ 'Y', 'M', 'M', '4', 0,
/* 446 */ 'Z', 'M', 'M', '4', 0,
/* 451 */ 'F', 'P', '4', 0,
/* 455 */ 'C', 'R', '4', 0,
/* 459 */ 'D', 'R', '4', 0,
/* 463 */ 'S', 'T', '4', 0,
/* 467 */ 'X', 'M', 'M', '1', '5', 0,
/* 473 */ 'Y', 'M', 'M', '1', '5', 0,
/* 479 */ 'Z', 'M', 'M', '1', '5', 0,
/* 485 */ 'C', 'R', '1', '5', 0,
/* 490 */ 'D', 'R', '1', '5', 0,
/* 495 */ 'X', 'M', 'M', '2', '5', 0,
/* 501 */ 'Y', 'M', 'M', '2', '5', 0,
/* 507 */ 'Z', 'M', 'M', '2', '5', 0,
/* 513 */ 'K', '4', '_', 'K', '5', 0,
/* 519 */ 'T', 'M', 'M', '5', 0,
/* 524 */ 'X', 'M', 'M', '5', 0,
/* 529 */ 'Y', 'M', 'M', '5', 0,
/* 534 */ 'Z', 'M', 'M', '5', 0,
/* 539 */ 'F', 'P', '5', 0,
/* 543 */ 'C', 'R', '5', 0,
/* 547 */ 'D', 'R', '5', 0,
/* 551 */ 'S', 'T', '5', 0,
/* 555 */ 'X', 'M', 'M', '1', '6', 0,
/* 561 */ 'Y', 'M', 'M', '1', '6', 0,
/* 567 */ 'Z', 'M', 'M', '1', '6', 0,
/* 573 */ 'X', 'M', 'M', '2', '6', 0,
/* 579 */ 'Y', 'M', 'M', '2', '6', 0,
/* 585 */ 'Z', 'M', 'M', '2', '6', 0,
/* 591 */ 'K', '6', 0,
/* 594 */ 'T', 'M', 'M', '6', 0,
/* 599 */ 'X', 'M', 'M', '6', 0,
/* 604 */ 'Y', 'M', 'M', '6', 0,
/* 609 */ 'Z', 'M', 'M', '6', 0,
/* 614 */ 'F', 'P', '6', 0,
/* 618 */ 'C', 'R', '6', 0,
/* 622 */ 'D', 'R', '6', 0,
/* 626 */ 'S', 'T', '6', 0,
/* 630 */ 'X', 'M', 'M', '1', '7', 0,
/* 636 */ 'Y', 'M', 'M', '1', '7', 0,
/* 642 */ 'Z', 'M', 'M', '1', '7', 0,
/* 648 */ 'X', 'M', 'M', '2', '7', 0,
/* 654 */ 'Y', 'M', 'M', '2', '7', 0,
/* 660 */ 'Z', 'M', 'M', '2', '7', 0,
/* 666 */ 'K', '6', '_', 'K', '7', 0,
/* 672 */ 'T', 'M', 'M', '7', 0,
/* 677 */ 'X', 'M', 'M', '7', 0,
/* 682 */ 'Y', 'M', 'M', '7', 0,
/* 687 */ 'Z', 'M', 'M', '7', 0,
/* 692 */ 'F', 'P', '7', 0,
/* 696 */ 'C', 'R', '7', 0,
/* 700 */ 'D', 'R', '7', 0,
/* 704 */ 'S', 'T', '7', 0,
/* 708 */ 'X', 'M', 'M', '1', '8', 0,
/* 714 */ 'Y', 'M', 'M', '1', '8', 0,
/* 720 */ 'Z', 'M', 'M', '1', '8', 0,
/* 726 */ 'X', 'M', 'M', '2', '8', 0,
/* 732 */ 'Y', 'M', 'M', '2', '8', 0,
/* 738 */ 'Z', 'M', 'M', '2', '8', 0,
/* 744 */ 'X', 'M', 'M', '8', 0,
/* 749 */ 'Y', 'M', 'M', '8', 0,
/* 754 */ 'Z', 'M', 'M', '8', 0,
/* 759 */ 'C', 'R', '8', 0,
/* 763 */ 'D', 'R', '8', 0,
/* 767 */ 'X', 'M', 'M', '1', '9', 0,
/* 773 */ 'Y', 'M', 'M', '1', '9', 0,
/* 779 */ 'Z', 'M', 'M', '1', '9', 0,
/* 785 */ 'X', 'M', 'M', '2', '9', 0,
/* 791 */ 'Y', 'M', 'M', '2', '9', 0,
/* 797 */ 'Z', 'M', 'M', '2', '9', 0,
/* 803 */ 'X', 'M', 'M', '9', 0,
/* 808 */ 'Y', 'M', 'M', '9', 0,
/* 813 */ 'Z', 'M', 'M', '9', 0,
/* 818 */ 'C', 'R', '9', 0,
/* 822 */ 'D', 'R', '9', 0,
/* 826 */ 'R', '1', '0', 'B', 0,
/* 831 */ 'R', '1', '1', 'B', 0,
/* 836 */ 'R', '1', '2', 'B', 0,
/* 841 */ 'R', '1', '3', 'B', 0,
/* 846 */ 'R', '1', '4', 'B', 0,
/* 851 */ 'R', '1', '5', 'B', 0,
/* 856 */ 'R', '8', 'B', 0,
/* 860 */ 'R', '9', 'B', 0,
/* 864 */ 'R', '1', '0', 'D', 0,
/* 869 */ 'R', '1', '1', 'D', 0,
/* 874 */ 'R', '1', '2', 'D', 0,
/* 879 */ 'R', '1', '3', 'D', 0,
/* 884 */ 'R', '1', '4', 'D', 0,
/* 889 */ 'R', '1', '5', 'D', 0,
/* 894 */ 'R', '8', 'D', 0,
/* 898 */ 'R', '9', 'D', 0,
/* 902 */ 'F', 'S', '_', 'B', 'A', 'S', 'E', 0,
/* 910 */ 'G', 'S', '_', 'B', 'A', 'S', 'E', 0,
/* 918 */ 'D', 'F', 0,
/* 921 */ 'T', 'M', 'M', 'C', 'F', 'G', 0,
/* 928 */ 'A', 'H', 0,
/* 931 */ 'R', '1', '0', 'B', 'H', 0,
/* 937 */ 'R', '1', '1', 'B', 'H', 0,
/* 943 */ 'R', '1', '2', 'B', 'H', 0,
/* 949 */ 'R', '1', '3', 'B', 'H', 0,
/* 955 */ 'R', '1', '4', 'B', 'H', 0,
/* 961 */ 'R', '1', '5', 'B', 'H', 0,
/* 967 */ 'R', '8', 'B', 'H', 0,
/* 972 */ 'R', '9', 'B', 'H', 0,
/* 977 */ 'C', 'H', 0,
/* 980 */ 'D', 'H', 0,
/* 983 */ 'D', 'I', 'H', 0,
/* 987 */ 'S', 'I', 'H', 0,
/* 991 */ 'B', 'P', 'H', 0,
/* 995 */ 'S', 'P', 'H', 0,
/* 999 */ 'R', '1', '0', 'W', 'H', 0,
/* 1005 */ 'R', '1', '1', 'W', 'H', 0,
/* 1011 */ 'R', '1', '2', 'W', 'H', 0,
/* 1017 */ 'R', '1', '3', 'W', 'H', 0,
/* 1023 */ 'R', '1', '4', 'W', 'H', 0,
/* 1029 */ 'R', '1', '5', 'W', 'H', 0,
/* 1035 */ 'R', '8', 'W', 'H', 0,
/* 1040 */ 'R', '9', 'W', 'H', 0,
/* 1045 */ 'E', 'D', 'I', 0,
/* 1049 */ 'H', 'D', 'I', 0,
/* 1053 */ 'R', 'D', 'I', 0,
/* 1057 */ 'E', 'S', 'I', 0,
/* 1061 */ 'H', 'S', 'I', 0,
/* 1065 */ 'R', 'S', 'I', 0,
/* 1069 */ 'A', 'L', 0,
/* 1072 */ 'B', 'L', 0,
/* 1075 */ 'C', 'L', 0,
/* 1078 */ 'D', 'L', 0,
/* 1081 */ 'D', 'I', 'L', 0,
/* 1085 */ 'S', 'I', 'L', 0,
/* 1089 */ 'B', 'P', 'L', 0,
/* 1093 */ 'S', 'P', 'L', 0,
/* 1097 */ 'E', 'B', 'P', 0,
/* 1101 */ 'H', 'B', 'P', 0,
/* 1105 */ 'R', 'B', 'P', 0,
/* 1109 */ 'E', 'I', 'P', 0,
/* 1113 */ 'H', 'I', 'P', 0,
/* 1117 */ 'R', 'I', 'P', 0,
/* 1121 */ 'E', 'S', 'P', 0,
/* 1125 */ 'H', 'S', 'P', 0,
/* 1129 */ 'R', 'S', 'P', 0,
/* 1133 */ 'S', 'S', 'P', 0,
/* 1137 */ 'M', 'X', 'C', 'S', 'R', 0,
/* 1143 */ 'C', 'S', 0,
/* 1146 */ 'D', 'S', 0,
/* 1149 */ 'E', 'S', 0,
/* 1152 */ 'F', 'S', 0,
/* 1155 */ '_', 'E', 'F', 'L', 'A', 'G', 'S', 0,
/* 1163 */ 'R', 'F', 'L', 'A', 'G', 'S', 0,
/* 1170 */ 'S', 'S', 0,
/* 1173 */ 'R', '1', '0', 'W', 0,
/* 1178 */ 'R', '1', '1', 'W', 0,
/* 1183 */ 'R', '1', '2', 'W', 0,
/* 1188 */ 'R', '1', '3', 'W', 0,
/* 1193 */ 'R', '1', '4', 'W', 0,
/* 1198 */ 'R', '1', '5', 'W', 0,
/* 1203 */ 'R', '8', 'W', 0,
/* 1207 */ 'R', '9', 'W', 0,
/* 1211 */ 'F', 'P', 'C', 'W', 0,
/* 1216 */ 'F', 'P', 'S', 'W', 0,
/* 1221 */ 'E', 'A', 'X', 0,
/* 1225 */ 'H', 'A', 'X', 0,
/* 1229 */ 'R', 'A', 'X', 0,
/* 1233 */ 'E', 'B', 'X', 0,
/* 1237 */ 'H', 'B', 'X', 0,
/* 1241 */ 'R', 'B', 'X', 0,
/* 1245 */ 'E', 'C', 'X', 0,
/* 1249 */ 'H', 'C', 'X', 0,
/* 1253 */ 'R', 'C', 'X', 0,
/* 1257 */ 'E', 'D', 'X', 0,
/* 1261 */ 'H', 'D', 'X', 0,
/* 1265 */ 'R', 'D', 'X', 0,
/* 1269 */ 'E', 'I', 'Z', 0,
/* 1273 */ 'R', 'I', 'Z', 0,
0
};
extern const MCRegisterDesc X86RegDesc[] = { // Descriptors
{ 5, 0, 0, 0, 0, 0 },
{ 928, 2, 195, 2, 5041, 0 },
{ 1069, 2, 191, 2, 5041, 0 },
{ 1222, 323, 192, 0, 0, 2 },
{ 934, 2, 179, 2, 4993, 0 },
{ 1072, 2, 175, 2, 4993, 0 },
{ 1098, 314, 184, 3, 352, 5 },
{ 991, 2, 187, 2, 1008, 0 },
{ 1089, 2, 183, 2, 976, 0 },
{ 1234, 317, 176, 0, 304, 2 },
{ 977, 2, 171, 2, 4897, 0 },
{ 1075, 2, 167, 2, 4897, 0 },
{ 1143, 2, 2, 2, 4897, 0 },
{ 1246, 320, 168, 0, 400, 2 },
{ 918, 2, 2, 2, 4849, 0 },
{ 980, 2, 155, 2, 4849, 0 },
{ 1046, 314, 160, 3, 448, 5 },
{ 983, 2, 163, 2, 1536, 0 },
{ 1081, 2, 159, 2, 4562, 0 },
{ 1078, 2, 151, 2, 4817, 0 },
{ 1146, 2, 2, 2, 4817, 0 },
{ 1258, 305, 152, 0, 928, 2 },
{ 1221, 236, 153, 7, 1764, 8 },
{ 1097, 224, 153, 13, 1476, 12 },
{ 1233, 230, 153, 7, 1700, 8 },
{ 1245, 218, 153, 7, 1412, 8 },
{ 1045, 127, 153, 13, 1109, 12 },
{ 1257, 209, 153, 7, 1168, 8 },
{ 1156, 2, 2, 2, 1824, 0 },
{ 1109, 309, 153, 19, 496, 16 },
{ 1269, 2, 2, 2, 4817, 0 },
{ 1149, 2, 2, 2, 4817, 0 },
{ 1057, 294, 134, 13, 243, 12 },
{ 1121, 288, 134, 13, 243, 12 },
{ 1211, 2, 2, 2, 4993, 0 },
{ 1216, 2, 2, 2, 4993, 0 },
{ 1152, 2, 2, 2, 4993, 0 },
{ 902, 2, 2, 2, 4993, 0 },
{ 1160, 2, 2, 2, 4993, 0 },
{ 910, 2, 2, 2, 4993, 0 },
{ 1225, 2, 202, 2, 4561, 0 },
{ 1101, 2, 202, 2, 4561, 0 },
{ 1237, 2, 202, 2, 4561, 0 },
{ 1249, 2, 202, 2, 4561, 0 },
{ 1049, 2, 202, 2, 4561, 0 },
{ 1261, 2, 202, 2, 4561, 0 },
{ 1113, 2, 205, 2, 4355, 0 },
{ 1061, 2, 148, 2, 4387, 0 },
{ 1125, 2, 148, 2, 4387, 0 },
{ 1110, 2, 199, 2, 1856, 0 },
{ 1137, 2, 2, 2, 3728, 0 },
{ 1229, 235, 2, 6, 1636, 8 },
{ 1105, 223, 2, 12, 1348, 12 },
{ 1241, 229, 2, 6, 1572, 8 },
{ 1253, 217, 2, 6, 1284, 8 },
{ 1053, 126, 2, 12, 1045, 12 },
{ 1265, 208, 2, 6, 1168, 8 },
{ 1163, 2, 2, 2, 3824, 0 },
{ 1117, 308, 2, 18, 496, 16 },
{ 1273, 2, 2, 2, 3856, 0 },
{ 1065, 293, 2, 12, 179, 12 },
{ 1129, 287, 2, 12, 179, 12 },
{ 1058, 314, 141, 3, 544, 5 },
{ 987, 2, 144, 2, 2080, 0 },
{ 1085, 2, 140, 2, 1984, 0 },
{ 1122, 314, 133, 3, 592, 5 },
{ 995, 2, 136, 2, 3392, 0 },
{ 1093, 2, 132, 2, 4060, 0 },
{ 1170, 2, 2, 2, 4529, 0 },
{ 1133, 2, 2, 2, 4529, 0 },
{ 921, 2, 2, 2, 4529, 0 },
{ 1155, 2, 2, 2, 4529, 0 },
{ 91, 2, 2, 2, 4529, 0 },
{ 197, 2, 2, 2, 4529, 0 },
{ 282, 2, 2, 2, 4529, 0 },
{ 370, 2, 2, 2, 4529, 0 },
{ 455, 2, 2, 2, 4529, 0 },
{ 543, 2, 2, 2, 4529, 0 },
{ 618, 2, 2, 2, 4529, 0 },
{ 696, 2, 2, 2, 4529, 0 },
{ 759, 2, 2, 2, 4529, 0 },
{ 818, 2, 2, 2, 4529, 0 },
{ 18, 2, 2, 2, 4529, 0 },
{ 121, 2, 2, 2, 4529, 0 },
{ 227, 2, 2, 2, 4529, 0 },
{ 312, 2, 2, 2, 4529, 0 },
{ 400, 2, 2, 2, 4529, 0 },
{ 485, 2, 2, 2, 4529, 0 },
{ 95, 2, 2, 2, 4529, 0 },
{ 201, 2, 2, 2, 4529, 0 },
{ 286, 2, 2, 2, 4529, 0 },
{ 374, 2, 2, 2, 4529, 0 },
{ 459, 2, 2, 2, 4529, 0 },
{ 547, 2, 2, 2, 4529, 0 },
{ 622, 2, 2, 2, 4529, 0 },
{ 700, 2, 2, 2, 4529, 0 },
{ 763, 2, 2, 2, 4529, 0 },
{ 822, 2, 2, 2, 4529, 0 },
{ 23, 2, 2, 2, 4529, 0 },
{ 126, 2, 2, 2, 4529, 0 },
{ 232, 2, 2, 2, 4529, 0 },
{ 317, 2, 2, 2, 4529, 0 },
{ 405, 2, 2, 2, 4529, 0 },
{ 490, 2, 2, 2, 4529, 0 },
{ 87, 2, 2, 2, 4529, 0 },
{ 193, 2, 2, 2, 4529, 0 },
{ 278, 2, 2, 2, 4529, 0 },
{ 366, 2, 2, 2, 4529, 0 },
{ 451, 2, 2, 2, 4529, 0 },
{ 539, 2, 2, 2, 4529, 0 },
{ 614, 2, 2, 2, 4529, 0 },
{ 692, 2, 2, 2, 4529, 0 },
{ 64, 2, 251, 2, 4529, 0 },
{ 170, 2, 249, 2, 4529, 0 },
{ 255, 2, 249, 2, 4529, 0 },
{ 343, 2, 247, 2, 4529, 0 },
{ 428, 2, 247, 2, 4529, 0 },
{ 516, 2, 245, 2, 4529, 0 },
{ 591, 2, 245, 2, 4529, 0 },
{ 669, 2, 243, 2, 4529, 0 },
{ 68, 2, 2, 2, 4529, 0 },
{ 174, 2, 2, 2, 4529, 0 },
{ 259, 2, 2, 2, 4529, 0 },
{ 347, 2, 2, 2, 4529, 0 },
{ 432, 2, 2, 2, 4529, 0 },
{ 520, 2, 2, 2, 4529, 0 },
{ 595, 2, 2, 2, 4529, 0 },
{ 673, 2, 2, 2, 4529, 0 },
{ 760, 118, 2, 12, 115, 12 },
{ 819, 118, 2, 12, 115, 12 },
{ 19, 118, 2, 12, 115, 12 },
{ 122, 118, 2, 12, 115, 12 },
{ 228, 118, 2, 12, 115, 12 },
{ 313, 118, 2, 12, 115, 12 },
{ 401, 118, 2, 12, 115, 12 },
{ 486, 118, 2, 12, 115, 12 },
{ 99, 2, 2, 2, 4785, 0 },
{ 205, 2, 2, 2, 4785, 0 },
{ 290, 2, 2, 2, 4785, 0 },
{ 378, 2, 2, 2, 4785, 0 },
{ 463, 2, 2, 2, 4785, 0 },
{ 551, 2, 2, 2, 4785, 0 },
{ 626, 2, 2, 2, 4785, 0 },
{ 704, 2, 2, 2, 4785, 0 },
{ 67, 2, 2, 2, 4785, 0 },
{ 173, 2, 2, 2, 4785, 0 },
{ 258, 2, 2, 2, 4785, 0 },
{ 346, 2, 2, 2, 4785, 0 },
{ 431, 2, 2, 2, 4785, 0 },
{ 519, 2, 2, 2, 4785, 0 },
{ 594, 2, 2, 2, 4785, 0 },
{ 672, 2, 2, 2, 4785, 0 },
{ 72, 2, 214, 2, 4785, 0 },
{ 178, 2, 214, 2, 4785, 0 },
{ 263, 2, 214, 2, 4785, 0 },
{ 351, 2, 214, 2, 4785, 0 },
{ 436, 2, 214, 2, 4785, 0 },
{ 524, 2, 214, 2, 4785, 0 },
{ 599, 2, 214, 2, 4785, 0 },
{ 677, 2, 214, 2, 4785, 0 },
{ 744, 2, 214, 2, 4785, 0 },
{ 803, 2, 214, 2, 4785, 0 },
{ 0, 2, 214, 2, 4785, 0 },
{ 103, 2, 214, 2, 4785, 0 },
{ 209, 2, 214, 2, 4785, 0 },
{ 294, 2, 214, 2, 4785, 0 },
{ 382, 2, 214, 2, 4785, 0 },
{ 467, 2, 214, 2, 4785, 0 },
{ 555, 2, 214, 2, 4785, 0 },
{ 630, 2, 214, 2, 4785, 0 },
{ 708, 2, 214, 2, 4785, 0 },
{ 767, 2, 214, 2, 4785, 0 },
{ 28, 2, 214, 2, 4785, 0 },
{ 131, 2, 214, 2, 4785, 0 },
{ 237, 2, 214, 2, 4785, 0 },
{ 322, 2, 214, 2, 4785, 0 },
{ 410, 2, 214, 2, 4785, 0 },
{ 495, 2, 214, 2, 4785, 0 },
{ 573, 2, 214, 2, 4785, 0 },
{ 648, 2, 214, 2, 4785, 0 },
{ 726, 2, 214, 2, 4785, 0 },
{ 785, 2, 214, 2, 4785, 0 },
{ 46, 2, 214, 2, 4785, 0 },
{ 149, 2, 214, 2, 4785, 0 },
{ 77, 281, 215, 26, 4449, 22 },
{ 183, 281, 215, 26, 4449, 22 },
{ 268, 281, 215, 26, 4449, 22 },
{ 356, 281, 215, 26, 4449, 22 },
{ 441, 281, 215, 26, 4449, 22 },
{ 529, 281, 215, 26, 4449, 22 },
{ 604, 281, 215, 26, 4449, 22 },
{ 682, 281, 215, 26, 4449, 22 },
{ 749, 281, 215, 26, 4449, 22 },
{ 808, 281, 215, 26, 4449, 22 },
{ 6, 281, 215, 26, 4449, 22 },
{ 109, 281, 215, 26, 4449, 22 },
{ 215, 281, 215, 26, 4449, 22 },
{ 300, 281, 215, 26, 4449, 22 },
{ 388, 281, 215, 26, 4449, 22 },
{ 473, 281, 215, 26, 4449, 22 },
{ 561, 281, 215, 26, 4449, 22 },
{ 636, 281, 215, 26, 4449, 22 },
{ 714, 281, 215, 26, 4449, 22 },
{ 773, 281, 215, 26, 4449, 22 },
{ 34, 281, 215, 26, 4449, 22 },
{ 137, 281, 215, 26, 4449, 22 },
{ 243, 281, 215, 26, 4449, 22 },
{ 328, 281, 215, 26, 4449, 22 },
{ 416, 281, 215, 26, 4449, 22 },
{ 501, 281, 215, 26, 4449, 22 },
{ 579, 281, 215, 26, 4449, 22 },
{ 654, 281, 215, 26, 4449, 22 },
{ 732, 281, 215, 26, 4449, 22 },
{ 791, 281, 215, 26, 4449, 22 },
{ 52, 281, 215, 26, 4449, 22 },
{ 155, 281, 215, 26, 4449, 22 },
{ 82, 280, 2, 25, 4417, 22 },
{ 188, 280, 2, 25, 4417, 22 },
{ 273, 280, 2, 25, 4417, 22 },
{ 361, 280, 2, 25, 4417, 22 },
{ 446, 280, 2, 25, 4417, 22 },
{ 534, 280, 2, 25, 4417, 22 },
{ 609, 280, 2, 25, 4417, 22 },
{ 687, 280, 2, 25, 4417, 22 },
{ 754, 280, 2, 25, 4417, 22 },
{ 813, 280, 2, 25, 4417, 22 },
{ 12, 280, 2, 25, 4417, 22 },
{ 115, 280, 2, 25, 4417, 22 },
{ 221, 280, 2, 25, 4417, 22 },
{ 306, 280, 2, 25, 4417, 22 },
{ 394, 280, 2, 25, 4417, 22 },
{ 479, 280, 2, 25, 4417, 22 },
{ 567, 280, 2, 25, 4417, 22 },
{ 642, 280, 2, 25, 4417, 22 },
{ 720, 280, 2, 25, 4417, 22 },
{ 779, 280, 2, 25, 4417, 22 },
{ 40, 280, 2, 25, 4417, 22 },
{ 143, 280, 2, 25, 4417, 22 },
{ 249, 280, 2, 25, 4417, 22 },
{ 334, 280, 2, 25, 4417, 22 },
{ 422, 280, 2, 25, 4417, 22 },
{ 507, 280, 2, 25, 4417, 22 },
{ 585, 280, 2, 25, 4417, 22 },
{ 660, 280, 2, 25, 4417, 22 },
{ 738, 280, 2, 25, 4417, 22 },
{ 797, 280, 2, 25, 4417, 22 },
{ 58, 280, 2, 25, 4417, 22 },
{ 161, 280, 2, 25, 4417, 22 },
{ 856, 2, 268, 2, 4147, 0 },
{ 860, 2, 268, 2, 4147, 0 },
{ 826, 2, 268, 2, 4147, 0 },
{ 831, 2, 268, 2, 4147, 0 },
{ 836, 2, 268, 2, 4147, 0 },
{ 841, 2, 268, 2, 4147, 0 },
{ 846, 2, 268, 2, 4147, 0 },
{ 851, 2, 268, 2, 4147, 0 },
{ 967, 2, 264, 2, 4115, 0 },
{ 972, 2, 264, 2, 4115, 0 },
{ 931, 2, 264, 2, 4115, 0 },
{ 937, 2, 264, 2, 4115, 0 },
{ 943, 2, 264, 2, 4115, 0 },
{ 949, 2, 264, 2, 4115, 0 },
{ 955, 2, 264, 2, 4115, 0 },
{ 961, 2, 264, 2, 4115, 0 },
{ 894, 119, 262, 13, 51, 12 },
{ 898, 119, 262, 13, 51, 12 },
{ 864, 119, 262, 13, 51, 12 },
{ 869, 119, 262, 13, 51, 12 },
{ 874, 119, 262, 13, 51, 12 },
{ 879, 119, 262, 13, 51, 12 },
{ 884, 119, 262, 13, 51, 12 },
{ 889, 119, 262, 13, 51, 12 },
{ 1203, 77, 265, 3, 643, 5 },
{ 1207, 77, 265, 3, 643, 5 },
{ 1173, 77, 265, 3, 643, 5 },
{ 1178, 77, 265, 3, 643, 5 },
{ 1183, 77, 265, 3, 643, 5 },
{ 1188, 77, 265, 3, 643, 5 },
{ 1193, 77, 265, 3, 643, 5 },
{ 1198, 77, 265, 3, 643, 5 },
{ 1035, 2, 261, 2, 4083, 0 },
{ 1040, 2, 261, 2, 4083, 0 },
{ 999, 2, 261, 2, 4083, 0 },
{ 1005, 2, 261, 2, 4083, 0 },
{ 1011, 2, 261, 2, 4083, 0 },
{ 1017, 2, 261, 2, 4083, 0 },
{ 1023, 2, 261, 2, 4083, 0 },
{ 1029, 2, 261, 2, 4083, 0 },
{ 167, 46, 2, 22, 690, 19 },
{ 340, 49, 2, 22, 690, 19 },
{ 513, 52, 2, 22, 690, 19 },
{ 666, 55, 2, 22, 690, 19 },
};
extern const MCPhysReg X86RegUnitRoots[][2] = {
{ X86::AH },
{ X86::AL },
{ X86::BH },
{ X86::BL },
{ X86::BPL },
{ X86::BPH },
{ X86::CH },
{ X86::CL },
{ X86::CS },
{ X86::DF },
{ X86::DH },
{ X86::DIL },
{ X86::DIH },
{ X86::DL },
{ X86::DS },
{ X86::HAX },
{ X86::HBP },
{ X86::HBX },
{ X86::HCX },
{ X86::HDI },
{ X86::HDX },
{ X86::EFLAGS },
{ X86::IP },
{ X86::HIP },
{ X86::EIZ },
{ X86::ES },
{ X86::SIL },
{ X86::SIH },
{ X86::HSI },
{ X86::SPL },
{ X86::SPH },
{ X86::HSP },
{ X86::FPCW },
{ X86::FPSW },
{ X86::FS },
{ X86::FS_BASE },
{ X86::GS },
{ X86::GS_BASE },
{ X86::MXCSR },
{ X86::RFLAGS },
{ X86::RIZ },
{ X86::SS },
{ X86::SSP },
{ X86::TMMCFG },
{ X86::_EFLAGS },
{ X86::CR0 },
{ X86::CR1 },
{ X86::CR2 },
{ X86::CR3 },
{ X86::CR4 },
{ X86::CR5 },
{ X86::CR6 },
{ X86::CR7 },
{ X86::CR8 },
{ X86::CR9 },
{ X86::CR10 },
{ X86::CR11 },
{ X86::CR12 },
{ X86::CR13 },
{ X86::CR14 },
{ X86::CR15 },
{ X86::DR0 },
{ X86::DR1 },
{ X86::DR2 },
{ X86::DR3 },
{ X86::DR4 },
{ X86::DR5 },
{ X86::DR6 },
{ X86::DR7 },
{ X86::DR8 },
{ X86::DR9 },
{ X86::DR10 },
{ X86::DR11 },
{ X86::DR12 },
{ X86::DR13 },
{ X86::DR14 },
{ X86::DR15 },
{ X86::FP0 },
{ X86::FP1 },
{ X86::FP2 },
{ X86::FP3 },
{ X86::FP4 },
{ X86::FP5 },
{ X86::FP6 },
{ X86::FP7 },
{ X86::K0 },
{ X86::K1 },
{ X86::K2 },
{ X86::K3 },
{ X86::K4 },
{ X86::K5 },
{ X86::K6 },
{ X86::K7 },
{ X86::MM0 },
{ X86::MM1 },
{ X86::MM2 },
{ X86::MM3 },
{ X86::MM4 },
{ X86::MM5 },
{ X86::MM6 },
{ X86::MM7 },
{ X86::R8B },
{ X86::R8BH },
{ X86::R8WH },
{ X86::R9B },
{ X86::R9BH },
{ X86::R9WH },
{ X86::R10B },
{ X86::R10BH },
{ X86::R10WH },
{ X86::R11B },
{ X86::R11BH },
{ X86::R11WH },
{ X86::R12B },
{ X86::R12BH },
{ X86::R12WH },
{ X86::R13B },
{ X86::R13BH },
{ X86::R13WH },
{ X86::R14B },
{ X86::R14BH },
{ X86::R14WH },
{ X86::R15B },
{ X86::R15BH },
{ X86::R15WH },
{ X86::ST0 },
{ X86::ST1 },
{ X86::ST2 },
{ X86::ST3 },
{ X86::ST4 },
{ X86::ST5 },
{ X86::ST6 },
{ X86::ST7 },
{ X86::TMM0 },
{ X86::TMM1 },
{ X86::TMM2 },
{ X86::TMM3 },
{ X86::TMM4 },
{ X86::TMM5 },
{ X86::TMM6 },
{ X86::TMM7 },
{ X86::XMM0 },
{ X86::XMM1 },
{ X86::XMM2 },
{ X86::XMM3 },
{ X86::XMM4 },
{ X86::XMM5 },
{ X86::XMM6 },
{ X86::XMM7 },
{ X86::XMM8 },
{ X86::XMM9 },
{ X86::XMM10 },
{ X86::XMM11 },
{ X86::XMM12 },
{ X86::XMM13 },
{ X86::XMM14 },
{ X86::XMM15 },
{ X86::XMM16 },
{ X86::XMM17 },
{ X86::XMM18 },
{ X86::XMM19 },
{ X86::XMM20 },
{ X86::XMM21 },
{ X86::XMM22 },
{ X86::XMM23 },
{ X86::XMM24 },
{ X86::XMM25 },
{ X86::XMM26 },
{ X86::XMM27 },
{ X86::XMM28 },
{ X86::XMM29 },
{ X86::XMM30 },
{ X86::XMM31 },
};
namespace { // Register classes...
// GR8 Register Class...
const MCPhysReg GR8[] = {
X86::AL, X86::CL, X86::DL, X86::AH, X86::CH, X86::DH, X86::BL, X86::BH, X86::SIL, X86::DIL, X86::BPL, X86::SPL, X86::R8B, X86::R9B, X86::R10B, X86::R11B, X86::R14B, X86::R15B, X86::R12B, X86::R13B,
};
// GR8 Bit set.
const uint8_t GR8Bits[] = {
0x36, 0x8d, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff,
};
// GRH8 Register Class...
const MCPhysReg GRH8[] = {
X86::SIH, X86::DIH, X86::BPH, X86::SPH, X86::R8BH, X86::R9BH, X86::R10BH, X86::R11BH, X86::R12BH, X86::R13BH, X86::R14BH, X86::R15BH,
};
// GRH8 Bit set.
const uint8_t GRH8Bits[] = {
0x80, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x80, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff,
};
// GR8_NOREX Register Class...
const MCPhysReg GR8_NOREX[] = {
X86::AL, X86::CL, X86::DL, X86::AH, X86::CH, X86::DH, X86::BL, X86::BH,
};
// GR8_NOREX Bit set.
const uint8_t GR8_NOREXBits[] = {
0x36, 0x8c, 0x08,
};
// GR8_ABCD_H Register Class...
const MCPhysReg GR8_ABCD_H[] = {
X86::AH, X86::CH, X86::DH, X86::BH,
};
// GR8_ABCD_H Bit set.
const uint8_t GR8_ABCD_HBits[] = {
0x12, 0x84,
};
// GR8_ABCD_L Register Class...
const MCPhysReg GR8_ABCD_L[] = {
X86::AL, X86::CL, X86::DL, X86::BL,
};
// GR8_ABCD_L Bit set.
const uint8_t GR8_ABCD_LBits[] = {
0x24, 0x08, 0x08,
};
// GRH16 Register Class...
const MCPhysReg GRH16[] = {
X86::HAX, X86::HCX, X86::HDX, X86::HSI, X86::HDI, X86::HBX, X86::HBP, X86::HSP, X86::HIP, X86::R8WH, X86::R9WH, X86::R10WH, X86::R11WH, X86::R12WH, X86::R13WH, X86::R14WH, X86::R15WH,
};
// GRH16 Bit set.
const uint8_t GRH16Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff,
};
// GR16 Register Class...
const MCPhysReg GR16[] = {
X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, X86::BX, X86::BP, X86::SP, X86::R8W, X86::R9W, X86::R10W, X86::R11W, X86::R14W, X86::R15W, X86::R12W, X86::R13W,
};
// GR16 Bit set.
const uint8_t GR16Bits[] = {
0x48, 0x22, 0x21, 0x00, 0x00, 0x00, 0x00, 0x40, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff,
};
// GR16_NOREX Register Class...
const MCPhysReg GR16_NOREX[] = {
X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, X86::BX, X86::BP, X86::SP,
};
// GR16_NOREX Bit set.
const uint8_t GR16_NOREXBits[] = {
0x48, 0x22, 0x21, 0x00, 0x00, 0x00, 0x00, 0x40, 0x02,
};
// VK1 Register Class...
const MCPhysReg VK1[] = {
X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
};
// VK1 Bit set.
const uint8_t VK1Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff,
};
// VK16 Register Class...
const MCPhysReg VK16[] = {
X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
};
// VK16 Bit set.
const uint8_t VK16Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff,
};
// VK2 Register Class...
const MCPhysReg VK2[] = {
X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
};
// VK2 Bit set.
const uint8_t VK2Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff,
};
// VK4 Register Class...
const MCPhysReg VK4[] = {
X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
};
// VK4 Bit set.
const uint8_t VK4Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff,
};
// VK8 Register Class...
const MCPhysReg VK8[] = {
X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
};
// VK8 Bit set.
const uint8_t VK8Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff,
};
// VK16WM Register Class...
const MCPhysReg VK16WM[] = {
X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
};
// VK16WM Bit set.
const uint8_t VK16WMBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe,
};
// VK1WM Register Class...
const MCPhysReg VK1WM[] = {
X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
};
// VK1WM Bit set.
const uint8_t VK1WMBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe,
};
// VK2WM Register Class...
const MCPhysReg VK2WM[] = {
X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
};
// VK2WM Bit set.
const uint8_t VK2WMBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe,
};
// VK4WM Register Class...
const MCPhysReg VK4WM[] = {
X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
};
// VK4WM Bit set.
const uint8_t VK4WMBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe,
};
// VK8WM Register Class...
const MCPhysReg VK8WM[] = {
X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
};
// VK8WM Bit set.
const uint8_t VK8WMBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe,
};
// SEGMENT_REG Register Class...
const MCPhysReg SEGMENT_REG[] = {
X86::CS, X86::DS, X86::SS, X86::ES, X86::FS, X86::GS,
};
// SEGMENT_REG Bit set.
const uint8_t SEGMENT_REGBits[] = {
0x00, 0x10, 0x10, 0x80, 0x50, 0x00, 0x00, 0x00, 0x10,
};
// GR16_ABCD Register Class...
const MCPhysReg GR16_ABCD[] = {
X86::AX, X86::CX, X86::DX, X86::BX,
};
// GR16_ABCD Bit set.
const uint8_t GR16_ABCDBits[] = {
0x08, 0x22, 0x20,
};
// FPCCR Register Class...
const MCPhysReg FPCCR[] = {
X86::FPSW,
};
// FPCCR Bit set.
const uint8_t FPCCRBits[] = {
0x00, 0x00, 0x00, 0x00, 0x08,
};
// FR16X Register Class...
const MCPhysReg FR16X[] = {
X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::XMM16, X86::XMM17, X86::XMM18, X86::XMM19, X86::XMM20, X86::XMM21, X86::XMM22, X86::XMM23, X86::XMM24, X86::XMM25, X86::XMM26, X86::XMM27, X86::XMM28, X86::XMM29, X86::XMM30, X86::XMM31,
};
// FR16X Bit set.
const uint8_t FR16XBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
};
// FR16 Register Class...
const MCPhysReg FR16[] = {
X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15,
};
// FR16 Bit set.
const uint8_t FR16Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff,
};
// VK16PAIR Register Class...
const MCPhysReg VK16PAIR[] = {
X86::K0_K1, X86::K2_K3, X86::K4_K5, X86::K6_K7,
};
// VK16PAIR Bit set.
const uint8_t VK16PAIRBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f,
};
// VK1PAIR Register Class...
const MCPhysReg VK1PAIR[] = {
X86::K0_K1, X86::K2_K3, X86::K4_K5, X86::K6_K7,
};
// VK1PAIR Bit set.
const uint8_t VK1PAIRBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f,
};
// VK2PAIR Register Class...
const MCPhysReg VK2PAIR[] = {
X86::K0_K1, X86::K2_K3, X86::K4_K5, X86::K6_K7,
};
// VK2PAIR Bit set.
const uint8_t VK2PAIRBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f,
};
// VK4PAIR Register Class...
const MCPhysReg VK4PAIR[] = {
X86::K0_K1, X86::K2_K3, X86::K4_K5, X86::K6_K7,
};
// VK4PAIR Bit set.
const uint8_t VK4PAIRBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f,
};
// VK8PAIR Register Class...
const MCPhysReg VK8PAIR[] = {
X86::K0_K1, X86::K2_K3, X86::K4_K5, X86::K6_K7,
};
// VK8PAIR Bit set.
const uint8_t VK8PAIRBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f,
};
// VK16PAIR_with_sub_mask_0_in_VK16WM Register Class...
const MCPhysReg VK16PAIR_with_sub_mask_0_in_VK16WM[] = {
X86::K2_K3, X86::K4_K5, X86::K6_K7,
};
// VK16PAIR_with_sub_mask_0_in_VK16WM Bit set.
const uint8_t VK16PAIR_with_sub_mask_0_in_VK16WMBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0e,
};
// FR32X Register Class...
const MCPhysReg FR32X[] = {
X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::XMM16, X86::XMM17, X86::XMM18, X86::XMM19, X86::XMM20, X86::XMM21, X86::XMM22, X86::XMM23, X86::XMM24, X86::XMM25, X86::XMM26, X86::XMM27, X86::XMM28, X86::XMM29, X86::XMM30, X86::XMM31,
};
// FR32X Bit set.
const uint8_t FR32XBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
};
// LOW32_ADDR_ACCESS_RBP Register Class...
const MCPhysReg LOW32_ADDR_ACCESS_RBP[] = {
X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::RIP, X86::RBP,
};
// LOW32_ADDR_ACCESS_RBP Bit set.
const uint8_t LOW32_ADDR_ACCESS_RBPBits[] = {
0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x10, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff,
};
// LOW32_ADDR_ACCESS Register Class...
const MCPhysReg LOW32_ADDR_ACCESS[] = {
X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::RIP,
};
// LOW32_ADDR_ACCESS Bit set.
const uint8_t LOW32_ADDR_ACCESSBits[] = {
0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff,
};
// LOW32_ADDR_ACCESS_RBP_with_sub_8bit Register Class...
const MCPhysReg LOW32_ADDR_ACCESS_RBP_with_sub_8bit[] = {
X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::RBP,
};
// LOW32_ADDR_ACCESS_RBP_with_sub_8bit Bit set.
const uint8_t LOW32_ADDR_ACCESS_RBP_with_sub_8bitBits[] = {
0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff,
};
// DEBUG_REG Register Class...
const MCPhysReg DEBUG_REG[] = {
X86::DR0, X86::DR1, X86::DR2, X86::DR3, X86::DR4, X86::DR5, X86::DR6, X86::DR7, X86::DR8, X86::DR9, X86::DR10, X86::DR11, X86::DR12, X86::DR13, X86::DR14, X86::DR15,
};
// DEBUG_REG Bit set.
const uint8_t DEBUG_REGBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff,
};
// FR32 Register Class...
const MCPhysReg FR32[] = {
X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15,
};
// FR32 Bit set.
const uint8_t FR32Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff,
};
// GR32 Register Class...
const MCPhysReg GR32[] = {
X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R14D, X86::R15D, X86::R12D, X86::R13D,
};
// GR32 Bit set.
const uint8_t GR32Bits[] = {
0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff,
};
// GR32_NOSP Register Class...
const MCPhysReg GR32_NOSP[] = {
X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R14D, X86::R15D, X86::R12D, X86::R13D,
};
// GR32_NOSP Bit set.
const uint8_t GR32_NOSPBits[] = {
0x00, 0x00, 0xc0, 0x0f, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff,
};
// LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX Register Class...
const MCPhysReg LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX[] = {
X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::RBP,
};
// LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX Bit set.
const uint8_t LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXBits[] = {
0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x10,
};
// GR32_NOREX Register Class...
const MCPhysReg GR32_NOREX[] = {
X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP,
};
// GR32_NOREX Bit set.
const uint8_t GR32_NOREXBits[] = {
0x00, 0x00, 0xc0, 0x0f, 0x03,
};
// VK32 Register Class...
const MCPhysReg VK32[] = {
X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
};
// VK32 Bit set.
const uint8_t VK32Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff,
};
// GR32_NOREX_NOSP Register Class...
const MCPhysReg GR32_NOREX_NOSP[] = {
X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP,
};
// GR32_NOREX_NOSP Bit set.
const uint8_t GR32_NOREX_NOSPBits[] = {
0x00, 0x00, 0xc0, 0x0f, 0x01,
};
// RFP32 Register Class...
const MCPhysReg RFP32[] = {
X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6,
};
// RFP32 Bit set.
const uint8_t RFP32Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f,
};
// VK32WM Register Class...
const MCPhysReg VK32WM[] = {
X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
};
// VK32WM Bit set.
const uint8_t VK32WMBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe,
};
// GR32_ABCD Register Class...
const MCPhysReg GR32_ABCD[] = {
X86::EAX, X86::ECX, X86::EDX, X86::EBX,
};
// GR32_ABCD Bit set.
const uint8_t GR32_ABCDBits[] = {
0x00, 0x00, 0x40, 0x0b,
};
// GR32_TC Register Class...
const MCPhysReg GR32_TC[] = {
X86::EAX, X86::ECX, X86::EDX, X86::ESP,
};
// GR32_TC Bit set.
const uint8_t GR32_TCBits[] = {
0x00, 0x00, 0x40, 0x0a, 0x02,
};
// GR32_ABCD_and_GR32_TC Register Class...
const MCPhysReg GR32_ABCD_and_GR32_TC[] = {
X86::EAX, X86::ECX, X86::EDX,
};
// GR32_ABCD_and_GR32_TC Bit set.
const uint8_t GR32_ABCD_and_GR32_TCBits[] = {
0x00, 0x00, 0x40, 0x0a,
};
// GR32_AD Register Class...
const MCPhysReg GR32_AD[] = {
X86::EAX, X86::EDX,
};
// GR32_AD Bit set.
const uint8_t GR32_ADBits[] = {
0x00, 0x00, 0x40, 0x08,
};
// GR32_BPSP Register Class...
const MCPhysReg GR32_BPSP[] = {
X86::EBP, X86::ESP,
};
// GR32_BPSP Bit set.
const uint8_t GR32_BPSPBits[] = {
0x00, 0x00, 0x80, 0x00, 0x02,
};
// GR32_BSI Register Class...
const MCPhysReg GR32_BSI[] = {
X86::EBX, X86::ESI,
};
// GR32_BSI Bit set.
const uint8_t GR32_BSIBits[] = {
0x00, 0x00, 0x00, 0x01, 0x01,
};
// GR32_CB Register Class...
const MCPhysReg GR32_CB[] = {
X86::ECX, X86::EBX,
};
// GR32_CB Bit set.
const uint8_t GR32_CBBits[] = {
0x00, 0x00, 0x00, 0x03,
};
// GR32_DC Register Class...
const MCPhysReg GR32_DC[] = {
X86::EDX, X86::ECX,
};
// GR32_DC Bit set.
const uint8_t GR32_DCBits[] = {
0x00, 0x00, 0x00, 0x0a,
};
// GR32_DIBP Register Class...
const MCPhysReg GR32_DIBP[] = {
X86::EDI, X86::EBP,
};
// GR32_DIBP Bit set.
const uint8_t GR32_DIBPBits[] = {
0x00, 0x00, 0x80, 0x04,
};
// GR32_SIDI Register Class...
const MCPhysReg GR32_SIDI[] = {
X86::ESI, X86::EDI,
};
// GR32_SIDI Bit set.
const uint8_t GR32_SIDIBits[] = {
0x00, 0x00, 0x00, 0x04, 0x01,
};
// LOW32_ADDR_ACCESS_RBP_with_sub_32bit Register Class...
const MCPhysReg LOW32_ADDR_ACCESS_RBP_with_sub_32bit[] = {
X86::RIP, X86::RBP,
};
// LOW32_ADDR_ACCESS_RBP_with_sub_32bit Bit set.
const uint8_t LOW32_ADDR_ACCESS_RBP_with_sub_32bitBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x04,
};
// CCR Register Class...
const MCPhysReg CCR[] = {
X86::EFLAGS,
};
// CCR Bit set.
const uint8_t CCRBits[] = {
0x00, 0x00, 0x00, 0x10,
};
// DFCCR Register Class...
const MCPhysReg DFCCR[] = {
X86::DF,
};
// DFCCR Bit set.
const uint8_t DFCCRBits[] = {
0x00, 0x40,
};
// GR32_ABCD_and_GR32_BSI Register Class...
const MCPhysReg GR32_ABCD_and_GR32_BSI[] = {
X86::EBX,
};
// GR32_ABCD_and_GR32_BSI Bit set.
const uint8_t GR32_ABCD_and_GR32_BSIBits[] = {
0x00, 0x00, 0x00, 0x01,
};
// GR32_AD_and_GR32_DC Register Class...
const MCPhysReg GR32_AD_and_GR32_DC[] = {
X86::EDX,
};
// GR32_AD_and_GR32_DC Bit set.
const uint8_t GR32_AD_and_GR32_DCBits[] = {
0x00, 0x00, 0x00, 0x08,
};
// GR32_BPSP_and_GR32_DIBP Register Class...
const MCPhysReg GR32_BPSP_and_GR32_DIBP[] = {
X86::EBP,
};
// GR32_BPSP_and_GR32_DIBP Bit set.
const uint8_t GR32_BPSP_and_GR32_DIBPBits[] = {
0x00, 0x00, 0x80,
};
// GR32_BPSP_and_GR32_TC Register Class...
const MCPhysReg GR32_BPSP_and_GR32_TC[] = {
X86::ESP,
};
// GR32_BPSP_and_GR32_TC Bit set.
const uint8_t GR32_BPSP_and_GR32_TCBits[] = {
0x00, 0x00, 0x00, 0x00, 0x02,
};
// GR32_BSI_and_GR32_SIDI Register Class...
const MCPhysReg GR32_BSI_and_GR32_SIDI[] = {
X86::ESI,
};
// GR32_BSI_and_GR32_SIDI Bit set.
const uint8_t GR32_BSI_and_GR32_SIDIBits[] = {
0x00, 0x00, 0x00, 0x00, 0x01,
};
// GR32_CB_and_GR32_DC Register Class...
const MCPhysReg GR32_CB_and_GR32_DC[] = {
X86::ECX,
};
// GR32_CB_and_GR32_DC Bit set.
const uint8_t GR32_CB_and_GR32_DCBits[] = {
0x00, 0x00, 0x00, 0x02,
};
// GR32_DIBP_and_GR32_SIDI Register Class...
const MCPhysReg GR32_DIBP_and_GR32_SIDI[] = {
X86::EDI,
};
// GR32_DIBP_and_GR32_SIDI Bit set.
const uint8_t GR32_DIBP_and_GR32_SIDIBits[] = {
0x00, 0x00, 0x00, 0x04,
};
// LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit Register Class...
const MCPhysReg LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit[] = {
X86::RBP,
};
// LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit Bit set.
const uint8_t LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
};
// LOW32_ADDR_ACCESS_with_sub_32bit Register Class...
const MCPhysReg LOW32_ADDR_ACCESS_with_sub_32bit[] = {
X86::RIP,
};
// LOW32_ADDR_ACCESS_with_sub_32bit Bit set.
const uint8_t LOW32_ADDR_ACCESS_with_sub_32bitBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04,
};
// RFP64 Register Class...
const MCPhysReg RFP64[] = {
X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6,
};
// RFP64 Bit set.
const uint8_t RFP64Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f,
};
// FR64X Register Class...
const MCPhysReg FR64X[] = {
X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::XMM16, X86::XMM17, X86::XMM18, X86::XMM19, X86::XMM20, X86::XMM21, X86::XMM22, X86::XMM23, X86::XMM24, X86::XMM25, X86::XMM26, X86::XMM27, X86::XMM28, X86::XMM29, X86::XMM30, X86::XMM31,
};
// FR64X Bit set.
const uint8_t FR64XBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
};
// GR64 Register Class...
const MCPhysReg GR64[] = {
X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::RBX, X86::R14, X86::R15, X86::R12, X86::R13, X86::RBP, X86::RSP, X86::RIP,
};
// GR64 Bit set.
const uint8_t GR64Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x35, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff,
};
// CONTROL_REG Register Class...
const MCPhysReg CONTROL_REG[] = {
X86::CR0, X86::CR1, X86::CR2, X86::CR3, X86::CR4, X86::CR5, X86::CR6, X86::CR7, X86::CR8, X86::CR9, X86::CR10, X86::CR11, X86::CR12, X86::CR13, X86::CR14, X86::CR15,
};
// CONTROL_REG Bit set.
const uint8_t CONTROL_REGBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff,
};
// FR64 Register Class...
const MCPhysReg FR64[] = {
X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15,
};
// FR64 Bit set.
const uint8_t FR64Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff,
};
// GR64_with_sub_8bit Register Class...
const MCPhysReg GR64_with_sub_8bit[] = {
X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::RBX, X86::R14, X86::R15, X86::R12, X86::R13, X86::RBP, X86::RSP,
};
// GR64_with_sub_8bit Bit set.
const uint8_t GR64_with_sub_8bitBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x31, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff,
};
// GR64_NOSP Register Class...
const MCPhysReg GR64_NOSP[] = {
X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::RBX, X86::R14, X86::R15, X86::R12, X86::R13, X86::RBP,
};
// GR64_NOSP Bit set.
const uint8_t GR64_NOSPBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff,
};
// GR64PLTSafe Register Class...
const MCPhysReg GR64PLTSafe[] = {
X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::RBX, X86::R14, X86::R15, X86::R12, X86::R13, X86::RBP,
};
// GR64PLTSafe Bit set.
const uint8_t GR64PLTSafeBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf3,
};
// GR64_TC Register Class...
const MCPhysReg GR64_TC[] = {
X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R11, X86::RIP, X86::RSP,
};
// GR64_TC Bit set.
const uint8_t GR64_TCBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc8, 0x35, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0b,
};
// GR64_NOREX Register Class...
const MCPhysReg GR64_NOREX[] = {
X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RBX, X86::RBP, X86::RSP, X86::RIP,
};
// GR64_NOREX Bit set.
const uint8_t GR64_NOREXBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x35,
};
// GR64_TCW64 Register Class...
const MCPhysReg GR64_TCW64[] = {
X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R10, X86::R11, X86::RIP, X86::RSP,
};
// GR64_TCW64 Bit set.
const uint8_t GR64_TCW64Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x25, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f,
};
// GR64_TC_with_sub_8bit Register Class...
const MCPhysReg GR64_TC_with_sub_8bit[] = {
X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R11, X86::RSP,
};
// GR64_TC_with_sub_8bit Bit set.
const uint8_t GR64_TC_with_sub_8bitBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc8, 0x31, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0b,
};
// GR64_NOSP_and_GR64_TC Register Class...
const MCPhysReg GR64_NOSP_and_GR64_TC[] = {
X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R11,
};
// GR64_NOSP_and_GR64_TC Bit set.
const uint8_t GR64_NOSP_and_GR64_TCBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc8, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0b,
};
// GR64_TCW64_with_sub_8bit Register Class...
const MCPhysReg GR64_TCW64_with_sub_8bit[] = {
X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R10, X86::R11, X86::RSP,
};
// GR64_TCW64_with_sub_8bit Bit set.
const uint8_t GR64_TCW64_with_sub_8bitBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f,
};
// GR64_TC_and_GR64_TCW64 Register Class...
const MCPhysReg GR64_TC_and_GR64_TCW64[] = {
X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R11, X86::RIP, X86::RSP,
};
// GR64_TC_and_GR64_TCW64 Bit set.
const uint8_t GR64_TC_and_GR64_TCW64Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x25, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0b,
};
// GR64_with_sub_16bit_in_GR16_NOREX Register Class...
const MCPhysReg GR64_with_sub_16bit_in_GR16_NOREX[] = {
X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RBX, X86::RBP, X86::RSP,
};
// GR64_with_sub_16bit_in_GR16_NOREX Bit set.
const uint8_t GR64_with_sub_16bit_in_GR16_NOREXBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x31,
};
// VK64 Register Class...
const MCPhysReg VK64[] = {
X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
};
// VK64 Bit set.
const uint8_t VK64Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff,
};
// VR64 Register Class...
const MCPhysReg VR64[] = {
X86::MM0, X86::MM1, X86::MM2, X86::MM3, X86::MM4, X86::MM5, X86::MM6, X86::MM7,
};
// VR64 Bit set.
const uint8_t VR64Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff,
};
// GR64PLTSafe_and_GR64_TC Register Class...
const MCPhysReg GR64PLTSafe_and_GR64_TC[] = {
X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9,
};
// GR64PLTSafe_and_GR64_TC Bit set.
const uint8_t GR64PLTSafe_and_GR64_TCBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc8, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,
};
// GR64_NOREX_NOSP Register Class...
const MCPhysReg GR64_NOREX_NOSP[] = {
X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RBX, X86::RBP,
};
// GR64_NOREX_NOSP Bit set.
const uint8_t GR64_NOREX_NOSPBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x11,
};
// GR64_NOREX_and_GR64_TC Register Class...
const MCPhysReg GR64_NOREX_and_GR64_TC[] = {
X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RSP, X86::RIP,
};
// GR64_NOREX_and_GR64_TC Bit set.
const uint8_t GR64_NOREX_and_GR64_TCBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc8, 0x35,
};
// GR64_NOSP_and_GR64_TCW64 Register Class...
const MCPhysReg GR64_NOSP_and_GR64_TCW64[] = {
X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R10, X86::R11,
};
// GR64_NOSP_and_GR64_TCW64 Bit set.
const uint8_t GR64_NOSP_and_GR64_TCW64Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f,
};
// GR64_TCW64_and_GR64_TC_with_sub_8bit Register Class...
const MCPhysReg GR64_TCW64_and_GR64_TC_with_sub_8bit[] = {
X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R11, X86::RSP,
};
// GR64_TCW64_and_GR64_TC_with_sub_8bit Bit set.
const uint8_t GR64_TCW64_and_GR64_TC_with_sub_8bitBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0b,
};
// VK64WM Register Class...
const MCPhysReg VK64WM[] = {
X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
};
// VK64WM Bit set.
const uint8_t VK64WMBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe,
};
// GR64_TC_and_GR64_NOSP_and_GR64_TCW64 Register Class...
const MCPhysReg GR64_TC_and_GR64_NOSP_and_GR64_TCW64[] = {
X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9, X86::R11,
};
// GR64_TC_and_GR64_NOSP_and_GR64_TCW64 Bit set.
const uint8_t GR64_TC_and_GR64_NOSP_and_GR64_TCW64Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0b,
};
// GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX Register Class...
const MCPhysReg GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX[] = {
X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RSP,
};
// GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX Bit set.
const uint8_t GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc8, 0x31,
};
// GR64PLTSafe_and_GR64_TCW64 Register Class...
const MCPhysReg GR64PLTSafe_and_GR64_TCW64[] = {
X86::RAX, X86::RCX, X86::RDX, X86::R8, X86::R9,
};
// GR64PLTSafe_and_GR64_TCW64 Bit set.
const uint8_t GR64PLTSafe_and_GR64_TCW64Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,
};
// GR64_NOREX_and_GR64PLTSafe_and_GR64_TC Register Class...
const MCPhysReg GR64_NOREX_and_GR64PLTSafe_and_GR64_TC[] = {
X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI,
};
// GR64_NOREX_and_GR64PLTSafe_and_GR64_TC Bit set.
const uint8_t GR64_NOREX_and_GR64PLTSafe_and_GR64_TCBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc8, 0x11,
};
// GR64_NOREX_and_GR64_TCW64 Register Class...
const MCPhysReg GR64_NOREX_and_GR64_TCW64[] = {
X86::RAX, X86::RCX, X86::RDX, X86::RSP, X86::RIP,
};
// GR64_NOREX_and_GR64_TCW64 Bit set.
const uint8_t GR64_NOREX_and_GR64_TCW64Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x25,
};
// GR64_ABCD Register Class...
const MCPhysReg GR64_ABCD[] = {
X86::RAX, X86::RCX, X86::RDX, X86::RBX,
};
// GR64_ABCD Bit set.
const uint8_t GR64_ABCDBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x68, 0x01,
};
// GR64_with_sub_32bit_in_GR32_TC Register Class...
const MCPhysReg GR64_with_sub_32bit_in_GR32_TC[] = {
X86::RAX, X86::RCX, X86::RDX, X86::RSP,
};
// GR64_with_sub_32bit_in_GR32_TC Bit set.
const uint8_t GR64_with_sub_32bit_in_GR32_TCBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x21,
};
// GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC Register Class...
const MCPhysReg GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC[] = {
X86::RAX, X86::RCX, X86::RDX,
};
// GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC Bit set.
const uint8_t GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x01,
};
// GR64_AD Register Class...
const MCPhysReg GR64_AD[] = {
X86::RAX, X86::RDX,
};
// GR64_AD Bit set.
const uint8_t GR64_ADBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x01,
};
// GR64_and_LOW32_ADDR_ACCESS_RBP Register Class...
const MCPhysReg GR64_and_LOW32_ADDR_ACCESS_RBP[] = {
X86::RBP, X86::RIP,
};
// GR64_and_LOW32_ADDR_ACCESS_RBP Bit set.
const uint8_t GR64_and_LOW32_ADDR_ACCESS_RBPBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x04,
};
// GR64_with_sub_32bit_in_GR32_BPSP Register Class...
const MCPhysReg GR64_with_sub_32bit_in_GR32_BPSP[] = {
X86::RBP, X86::RSP,
};
// GR64_with_sub_32bit_in_GR32_BPSP Bit set.
const uint8_t GR64_with_sub_32bit_in_GR32_BPSPBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x20,
};
// GR64_with_sub_32bit_in_GR32_BSI Register Class...
const MCPhysReg GR64_with_sub_32bit_in_GR32_BSI[] = {
X86::RSI, X86::RBX,
};
// GR64_with_sub_32bit_in_GR32_BSI Bit set.
const uint8_t GR64_with_sub_32bit_in_GR32_BSIBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x10,
};
// GR64_with_sub_32bit_in_GR32_CB Register Class...
const MCPhysReg GR64_with_sub_32bit_in_GR32_CB[] = {
X86::RCX, X86::RBX,
};
// GR64_with_sub_32bit_in_GR32_CB Bit set.
const uint8_t GR64_with_sub_32bit_in_GR32_CBBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60,
};
// GR64_with_sub_32bit_in_GR32_DC Register Class...
const MCPhysReg GR64_with_sub_32bit_in_GR32_DC[] = {
X86::RCX, X86::RDX,
};
// GR64_with_sub_32bit_in_GR32_DC Bit set.
const uint8_t GR64_with_sub_32bit_in_GR32_DCBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x01,
};
// GR64_with_sub_32bit_in_GR32_DIBP Register Class...
const MCPhysReg GR64_with_sub_32bit_in_GR32_DIBP[] = {
X86::RDI, X86::RBP,
};
// GR64_with_sub_32bit_in_GR32_DIBP Bit set.
const uint8_t GR64_with_sub_32bit_in_GR32_DIBPBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x90,
};
// GR64_with_sub_32bit_in_GR32_SIDI Register Class...
const MCPhysReg GR64_with_sub_32bit_in_GR32_SIDI[] = {
X86::RSI, X86::RDI,
};
// GR64_with_sub_32bit_in_GR32_SIDI Bit set.
const uint8_t GR64_with_sub_32bit_in_GR32_SIDIBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x10,
};
// GR64_and_LOW32_ADDR_ACCESS Register Class...
const MCPhysReg GR64_and_LOW32_ADDR_ACCESS[] = {
X86::RIP,
};
// GR64_and_LOW32_ADDR_ACCESS Bit set.
const uint8_t GR64_and_LOW32_ADDR_ACCESSBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04,
};
// GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI Register Class...
const MCPhysReg GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI[] = {
X86::RBX,
};
// GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI Bit set.
const uint8_t GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,
};
// GR64_with_sub_32bit_in_GR32_AD_and_GR32_DC Register Class...
const MCPhysReg GR64_with_sub_32bit_in_GR32_AD_and_GR32_DC[] = {
X86::RDX,
};
// GR64_with_sub_32bit_in_GR32_AD_and_GR32_DC Bit set.
const uint8_t GR64_with_sub_32bit_in_GR32_AD_and_GR32_DCBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
};
// GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP Register Class...
const MCPhysReg GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP[] = {
X86::RBP,
};
// GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP Bit set.
const uint8_t GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
};
// GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC Register Class...
const MCPhysReg GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC[] = {
X86::RSP,
};
// GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC Bit set.
const uint8_t GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,
};
// GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI Register Class...
const MCPhysReg GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI[] = {
X86::RSI,
};
// GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI Bit set.
const uint8_t GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
};
// GR64_with_sub_32bit_in_GR32_CB_and_GR32_DC Register Class...
const MCPhysReg GR64_with_sub_32bit_in_GR32_CB_and_GR32_DC[] = {
X86::RCX,
};
// GR64_with_sub_32bit_in_GR32_CB_and_GR32_DC Bit set.
const uint8_t GR64_with_sub_32bit_in_GR32_CB_and_GR32_DCBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40,
};
// GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI Register Class...
const MCPhysReg GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI[] = {
X86::RDI,
};
// GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI Bit set.
const uint8_t GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
};
// RST Register Class...
const MCPhysReg RST[] = {
X86::ST0, X86::ST1, X86::ST2, X86::ST3, X86::ST4, X86::ST5, X86::ST6, X86::ST7,
};
// RST Bit set.
const uint8_t RSTBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff,
};
// RFP80 Register Class...
const MCPhysReg RFP80[] = {
X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6,
};
// RFP80 Bit set.
const uint8_t RFP80Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f,
};
// RFP80_7 Register Class...
const MCPhysReg RFP80_7[] = {
X86::FP7,
};
// RFP80_7 Bit set.
const uint8_t RFP80_7Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
};
// VR128X Register Class...
const MCPhysReg VR128X[] = {
X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::XMM16, X86::XMM17, X86::XMM18, X86::XMM19, X86::XMM20, X86::XMM21, X86::XMM22, X86::XMM23, X86::XMM24, X86::XMM25, X86::XMM26, X86::XMM27, X86::XMM28, X86::XMM29, X86::XMM30, X86::XMM31,
};
// VR128X Bit set.
const uint8_t VR128XBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
};
// VR128 Register Class...
const MCPhysReg VR128[] = {
X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15,
};
// VR128 Bit set.
const uint8_t VR128Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff,
};
// VR256X Register Class...
const MCPhysReg VR256X[] = {
X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, X86::YMM16, X86::YMM17, X86::YMM18, X86::YMM19, X86::YMM20, X86::YMM21, X86::YMM22, X86::YMM23, X86::YMM24, X86::YMM25, X86::YMM26, X86::YMM27, X86::YMM28, X86::YMM29, X86::YMM30, X86::YMM31,
};
// VR256X Bit set.
const uint8_t VR256XBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
};
// VR256 Register Class...
const MCPhysReg VR256[] = {
X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15,
};
// VR256 Bit set.
const uint8_t VR256Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff,
};
// VR512 Register Class...
const MCPhysReg VR512[] = {
X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15, X86::ZMM16, X86::ZMM17, X86::ZMM18, X86::ZMM19, X86::ZMM20, X86::ZMM21, X86::ZMM22, X86::ZMM23, X86::ZMM24, X86::ZMM25, X86::ZMM26, X86::ZMM27, X86::ZMM28, X86::ZMM29, X86::ZMM30, X86::ZMM31,
};
// VR512 Bit set.
const uint8_t VR512Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
};
// VR512_0_15 Register Class...
const MCPhysReg VR512_0_15[] = {
X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15,
};
// VR512_0_15 Bit set.
const uint8_t VR512_0_15Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff,
};
// TILE Register Class...
const MCPhysReg TILE[] = {
X86::TMM0, X86::TMM1, X86::TMM2, X86::TMM3, X86::TMM4, X86::TMM5, X86::TMM6, X86::TMM7,
};
// TILE Bit set.
const uint8_t TILEBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff,
};
} // end anonymous namespace
extern const char X86RegClassStrings[] = {
/* 0 */ 'R', 'F', 'P', '8', '0', 0,
/* 6 */ 'V', 'K', '1', 0,
/* 10 */ 'V', 'R', '5', '1', '2', 0,
/* 16 */ 'V', 'K', '3', '2', 0,
/* 21 */ 'R', 'F', 'P', '3', '2', 0,
/* 27 */ 'F', 'R', '3', '2', 0,
/* 32 */ 'G', 'R', '3', '2', 0,
/* 37 */ 'V', 'K', '2', 0,
/* 41 */ 'V', 'K', '6', '4', 0,
/* 46 */ 'R', 'F', 'P', '6', '4', 0,
/* 52 */ 'F', 'R', '6', '4', 0,
/* 57 */ 'G', 'R', '6', '4', 0,
/* 62 */ 'V', 'R', '6', '4', 0,
/* 67 */ 'G', 'R', '6', '4', '_', 'T', 'C', '_', 'a', 'n', 'd', '_', 'G', 'R', '6', '4', '_', 'T', 'C', 'W', '6', '4', 0,
/* 90 */ 'G', 'R', '6', '4', '_', 'T', 'C', '_', 'a', 'n', 'd', '_', 'G', 'R', '6', '4', '_', 'N', 'O', 'S', 'P', '_', 'a', 'n', 'd', '_', 'G', 'R', '6', '4', '_', 'T', 'C', 'W', '6', '4', 0,
/* 127 */ 'G', 'R', '6', '4', '_', 'N', 'O', 'R', 'E', 'X', '_', 'a', 'n', 'd', '_', 'G', 'R', '6', '4', '_', 'T', 'C', 'W', '6', '4', 0,
/* 153 */ 'G', 'R', '6', '4', 'P', 'L', 'T', 'S', 'a', 'f', 'e', '_', 'a', 'n', 'd', '_', 'G', 'R', '6', '4', '_', 'T', 'C', 'W', '6', '4', 0,
/* 180 */ 'V', 'K', '4', 0,
/* 184 */ 'V', 'R', '5', '1', '2', '_', '0', '_', '1', '5', 0,
/* 195 */ 'G', 'R', 'H', '1', '6', 0,
/* 201 */ 'V', 'K', '1', '6', 0,
/* 206 */ 'F', 'R', '1', '6', 0,
/* 211 */ 'G', 'R', '1', '6', 0,
/* 216 */ 'V', 'R', '2', '5', '6', 0,
/* 222 */ 'R', 'F', 'P', '8', '0', '_', '7', 0,
/* 230 */ 'V', 'R', '1', '2', '8', 0,
/* 236 */ 'G', 'R', 'H', '8', 0,
/* 241 */ 'V', 'K', '8', 0,
/* 245 */ 'G', 'R', '8', 0,
/* 249 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'C', 'B', 0,
/* 280 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'C', 'B', '_', 'a', 'n', 'd', '_', 'G', 'R', '3', '2', '_', 'D', 'C', 0,
/* 323 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'A', 'D', '_', 'a', 'n', 'd', '_', 'G', 'R', '3', '2', '_', 'D', 'C', 0,
/* 366 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'D', 'C', 0,
/* 397 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'A', 'B', 'C', 'D', '_', 'a', 'n', 'd', '_', 'G', 'R', '3', '2', '_', 'T', 'C', 0,
/* 442 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'B', 'P', 'S', 'P', '_', 'a', 'n', 'd', '_', 'G', 'R', '3', '2', '_', 'T', 'C', 0,
/* 487 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'T', 'C', 0,
/* 518 */ 'G', 'R', '6', '4', '_', 'N', 'O', 'S', 'P', '_', 'a', 'n', 'd', '_', 'G', 'R', '6', '4', '_', 'T', 'C', 0,
/* 540 */ 'G', 'R', '6', '4', '_', 'N', 'O', 'R', 'E', 'X', '_', 'a', 'n', 'd', '_', 'G', 'R', '6', '4', '_', 'T', 'C', 0,
/* 563 */ 'G', 'R', '6', '4', '_', 'N', 'O', 'R', 'E', 'X', '_', 'a', 'n', 'd', '_', 'G', 'R', '6', '4', 'P', 'L', 'T', 'S', 'a', 'f', 'e', '_', 'a', 'n', 'd', '_', 'G', 'R', '6', '4', '_', 'T', 'C', 0,
/* 602 */ 'G', 'R', '3', '2', '_', 'A', 'D', 0,
/* 610 */ 'G', 'R', '6', '4', '_', 'A', 'D', 0,
/* 618 */ 'G', 'R', '3', '2', '_', 'A', 'B', 'C', 'D', 0,
/* 628 */ 'G', 'R', '6', '4', '_', 'A', 'B', 'C', 'D', 0,
/* 638 */ 'G', 'R', '1', '6', '_', 'A', 'B', 'C', 'D', 0,
/* 648 */ 'T', 'I', 'L', 'E', 0,
/* 653 */ 'D', 'E', 'B', 'U', 'G', '_', 'R', 'E', 'G', 0,
/* 663 */ 'C', 'O', 'N', 'T', 'R', 'O', 'L', '_', 'R', 'E', 'G', 0,
/* 675 */ 'S', 'E', 'G', 'M', 'E', 'N', 'T', '_', 'R', 'E', 'G', 0,
/* 687 */ 'G', 'R', '8', '_', 'A', 'B', 'C', 'D', '_', 'H', 0,
/* 698 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'B', 'S', 'I', '_', 'a', 'n', 'd', '_', 'G', 'R', '3', '2', '_', 'S', 'I', 'D', 'I', 0,
/* 744 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'D', 'I', 'B', 'P', '_', 'a', 'n', 'd', '_', 'G', 'R', '3', '2', '_', 'S', 'I', 'D', 'I', 0,
/* 791 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'S', 'I', 'D', 'I', 0,
/* 824 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'A', 'B', 'C', 'D', '_', 'a', 'n', 'd', '_', 'G', 'R', '3', '2', '_', 'B', 'S', 'I', 0,
/* 870 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'B', 'S', 'I', 0,
/* 902 */ 'G', 'R', '8', '_', 'A', 'B', 'C', 'D', '_', 'L', 0,
/* 913 */ 'V', 'K', '1', 'W', 'M', 0,
/* 919 */ 'V', 'K', '3', '2', 'W', 'M', 0,
/* 926 */ 'V', 'K', '2', 'W', 'M', 0,
/* 932 */ 'V', 'K', '6', '4', 'W', 'M', 0,
/* 939 */ 'V', 'K', '4', 'W', 'M', 0,
/* 945 */ 'V', 'K', '1', '6', 'P', 'A', 'I', 'R', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', 'm', 'a', 's', 'k', '_', '0', '_', 'i', 'n', '_', 'V', 'K', '1', '6', 'W', 'M', 0,
/* 980 */ 'V', 'K', '8', 'W', 'M', 0,
/* 986 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'B', 'P', 'S', 'P', '_', 'a', 'n', 'd', '_', 'G', 'R', '3', '2', '_', 'D', 'I', 'B', 'P', 0,
/* 1033 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'D', 'I', 'B', 'P', 0,
/* 1066 */ 'G', 'R', '6', '4', '_', 'a', 'n', 'd', '_', 'L', 'O', 'W', '3', '2', '_', 'A', 'D', 'D', 'R', '_', 'A', 'C', 'C', 'E', 'S', 'S', '_', 'R', 'B', 'P', 0,
/* 1097 */ 'G', 'R', '3', '2', '_', 'N', 'O', 'S', 'P', 0,
/* 1107 */ 'G', 'R', '6', '4', '_', 'N', 'O', 'S', 'P', 0,
/* 1117 */ 'G', 'R', '3', '2', '_', 'N', 'O', 'R', 'E', 'X', '_', 'N', 'O', 'S', 'P', 0,
/* 1133 */ 'G', 'R', '6', '4', '_', 'N', 'O', 'R', 'E', 'X', '_', 'N', 'O', 'S', 'P', 0,
/* 1149 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '3', '2', '_', 'B', 'P', 'S', 'P', 0,
/* 1182 */ 'D', 'F', 'C', 'C', 'R', 0,
/* 1188 */ 'F', 'P', 'C', 'C', 'R', 0,
/* 1194 */ 'V', 'K', '1', 'P', 'A', 'I', 'R', 0,
/* 1202 */ 'V', 'K', '2', 'P', 'A', 'I', 'R', 0,
/* 1210 */ 'V', 'K', '4', 'P', 'A', 'I', 'R', 0,
/* 1218 */ 'V', 'K', '1', '6', 'P', 'A', 'I', 'R', 0,
/* 1227 */ 'V', 'K', '8', 'P', 'A', 'I', 'R', 0,
/* 1235 */ 'G', 'R', '6', '4', '_', 'a', 'n', 'd', '_', 'L', 'O', 'W', '3', '2', '_', 'A', 'D', 'D', 'R', '_', 'A', 'C', 'C', 'E', 'S', 'S', 0,
/* 1262 */ 'R', 'S', 'T', 0,
/* 1266 */ 'F', 'R', '3', '2', 'X', 0,
/* 1272 */ 'F', 'R', '6', '4', 'X', 0,
/* 1278 */ 'F', 'R', '1', '6', 'X', 0,
/* 1284 */ 'V', 'R', '2', '5', '6', 'X', 0,
/* 1291 */ 'V', 'R', '1', '2', '8', 'X', 0,
/* 1298 */ 'G', 'R', '3', '2', '_', 'N', 'O', 'R', 'E', 'X', 0,
/* 1309 */ 'G', 'R', '6', '4', '_', 'N', 'O', 'R', 'E', 'X', 0,
/* 1320 */ 'G', 'R', '6', '4', '_', 'T', 'C', '_', 'a', 'n', 'd', '_', 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '1', '6', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '1', '6', '_', 'N', 'O', 'R', 'E', 'X', 0,
/* 1366 */ 'L', 'O', 'W', '3', '2', '_', 'A', 'D', 'D', 'R', '_', 'A', 'C', 'C', 'E', 'S', 'S', '_', 'R', 'B', 'P', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '1', '6', 'b', 'i', 't', '_', 'i', 'n', '_', 'G', 'R', '1', '6', '_', 'N', 'O', 'R', 'E', 'X', 0,
/* 1417 */ 'G', 'R', '8', '_', 'N', 'O', 'R', 'E', 'X', 0,
/* 1427 */ 'G', 'R', '6', '4', 'P', 'L', 'T', 'S', 'a', 'f', 'e', 0,
/* 1439 */ 'L', 'O', 'W', '3', '2', '_', 'A', 'D', 'D', 'R', '_', 'A', 'C', 'C', 'E', 'S', 'S', '_', 'R', 'B', 'P', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', 0,
/* 1476 */ 'L', 'O', 'W', '3', '2', '_', 'A', 'D', 'D', 'R', '_', 'A', 'C', 'C', 'E', 'S', 'S', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', 0,
/* 1509 */ 'L', 'O', 'W', '3', '2', '_', 'A', 'D', 'D', 'R', '_', 'A', 'C', 'C', 'E', 'S', 'S', '_', 'R', 'B', 'P', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '8', 'b', 'i', 't', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', 'b', 'i', 't', 0,
/* 1560 */ 'G', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '8', 'b', 'i', 't', 0,
/* 1579 */ 'G', 'R', '6', '4', '_', 'T', 'C', 'W', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '8', 'b', 'i', 't', 0,
/* 1604 */ 'G', 'R', '6', '4', '_', 'T', 'C', 'W', '6', '4', '_', 'a', 'n', 'd', '_', 'G', 'R', '6', '4', '_', 'T', 'C', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '8', 'b', 'i', 't', 0,
/* 1641 */ 'L', 'O', 'W', '3', '2', '_', 'A', 'D', 'D', 'R', '_', 'A', 'C', 'C', 'E', 'S', 'S', '_', 'R', 'B', 'P', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '8', 'b', 'i', 't', 0,
0
};
extern const MCRegisterClass X86MCRegisterClasses[] = {
{ GR8, GR8Bits, 245, 20, sizeof(GR8Bits), X86::GR8RegClassID, 8, 1, true },
{ GRH8, GRH8Bits, 236, 12, sizeof(GRH8Bits), X86::GRH8RegClassID, 8, 1, false },
{ GR8_NOREX, GR8_NOREXBits, 1417, 8, sizeof(GR8_NOREXBits), X86::GR8_NOREXRegClassID, 8, 1, true },
{ GR8_ABCD_H, GR8_ABCD_HBits, 687, 4, sizeof(GR8_ABCD_HBits), X86::GR8_ABCD_HRegClassID, 8, 1, true },
{ GR8_ABCD_L, GR8_ABCD_LBits, 902, 4, sizeof(GR8_ABCD_LBits), X86::GR8_ABCD_LRegClassID, 8, 1, true },
{ GRH16, GRH16Bits, 195, 17, sizeof(GRH16Bits), X86::GRH16RegClassID, 16, 1, false },
{ GR16, GR16Bits, 211, 16, sizeof(GR16Bits), X86::GR16RegClassID, 16, 1, true },
{ GR16_NOREX, GR16_NOREXBits, 1355, 8, sizeof(GR16_NOREXBits), X86::GR16_NOREXRegClassID, 16, 1, true },
{ VK1, VK1Bits, 6, 8, sizeof(VK1Bits), X86::VK1RegClassID, 16, 1, true },
{ VK16, VK16Bits, 201, 8, sizeof(VK16Bits), X86::VK16RegClassID, 16, 1, true },
{ VK2, VK2Bits, 37, 8, sizeof(VK2Bits), X86::VK2RegClassID, 16, 1, true },
{ VK4, VK4Bits, 180, 8, sizeof(VK4Bits), X86::VK4RegClassID, 16, 1, true },
{ VK8, VK8Bits, 241, 8, sizeof(VK8Bits), X86::VK8RegClassID, 16, 1, true },
{ VK16WM, VK16WMBits, 973, 7, sizeof(VK16WMBits), X86::VK16WMRegClassID, 16, 1, true },
{ VK1WM, VK1WMBits, 913, 7, sizeof(VK1WMBits), X86::VK1WMRegClassID, 16, 1, true },
{ VK2WM, VK2WMBits, 926, 7, sizeof(VK2WMBits), X86::VK2WMRegClassID, 16, 1, true },
{ VK4WM, VK4WMBits, 939, 7, sizeof(VK4WMBits), X86::VK4WMRegClassID, 16, 1, true },
{ VK8WM, VK8WMBits, 980, 7, sizeof(VK8WMBits), X86::VK8WMRegClassID, 16, 1, true },
{ SEGMENT_REG, SEGMENT_REGBits, 675, 6, sizeof(SEGMENT_REGBits), X86::SEGMENT_REGRegClassID, 16, 1, true },
{ GR16_ABCD, GR16_ABCDBits, 638, 4, sizeof(GR16_ABCDBits), X86::GR16_ABCDRegClassID, 16, 1, true },
{ FPCCR, FPCCRBits, 1188, 1, sizeof(FPCCRBits), X86::FPCCRRegClassID, 16, -1, false },
{ FR16X, FR16XBits, 1278, 32, sizeof(FR16XBits), X86::FR16XRegClassID, 32, 1, true },
{ FR16, FR16Bits, 206, 16, sizeof(FR16Bits), X86::FR16RegClassID, 32, 1, true },
{ VK16PAIR, VK16PAIRBits, 1218, 4, sizeof(VK16PAIRBits), X86::VK16PAIRRegClassID, 32, 1, true },
{ VK1PAIR, VK1PAIRBits, 1194, 4, sizeof(VK1PAIRBits), X86::VK1PAIRRegClassID, 32, 1, true },
{ VK2PAIR, VK2PAIRBits, 1202, 4, sizeof(VK2PAIRBits), X86::VK2PAIRRegClassID, 32, 1, true },
{ VK4PAIR, VK4PAIRBits, 1210, 4, sizeof(VK4PAIRBits), X86::VK4PAIRRegClassID, 32, 1, true },
{ VK8PAIR, VK8PAIRBits, 1227, 4, sizeof(VK8PAIRBits), X86::VK8PAIRRegClassID, 32, 1, true },
{ VK16PAIR_with_sub_mask_0_in_VK16WM, VK16PAIR_with_sub_mask_0_in_VK16WMBits, 945, 3, sizeof(VK16PAIR_with_sub_mask_0_in_VK16WMBits), X86::VK16PAIR_with_sub_mask_0_in_VK16WMRegClassID, 32, 1, true },
{ FR32X, FR32XBits, 1266, 32, sizeof(FR32XBits), X86::FR32XRegClassID, 32, 1, true },
{ LOW32_ADDR_ACCESS_RBP, LOW32_ADDR_ACCESS_RBPBits, 1075, 18, sizeof(LOW32_ADDR_ACCESS_RBPBits), X86::LOW32_ADDR_ACCESS_RBPRegClassID, 32, 1, true },
{ LOW32_ADDR_ACCESS, LOW32_ADDR_ACCESSBits, 1244, 17, sizeof(LOW32_ADDR_ACCESSBits), X86::LOW32_ADDR_ACCESSRegClassID, 32, 1, true },
{ LOW32_ADDR_ACCESS_RBP_with_sub_8bit, LOW32_ADDR_ACCESS_RBP_with_sub_8bitBits, 1641, 17, sizeof(LOW32_ADDR_ACCESS_RBP_with_sub_8bitBits), X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID, 32, 1, true },
{ DEBUG_REG, DEBUG_REGBits, 653, 16, sizeof(DEBUG_REGBits), X86::DEBUG_REGRegClassID, 32, 1, true },
{ FR32, FR32Bits, 27, 16, sizeof(FR32Bits), X86::FR32RegClassID, 32, 1, true },
{ GR32, GR32Bits, 32, 16, sizeof(GR32Bits), X86::GR32RegClassID, 32, 1, true },
{ GR32_NOSP, GR32_NOSPBits, 1097, 15, sizeof(GR32_NOSPBits), X86::GR32_NOSPRegClassID, 32, 1, true },
{ LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX, LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXBits, 1366, 9, sizeof(LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXBits), X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID, 32, 1, true },
{ GR32_NOREX, GR32_NOREXBits, 1298, 8, sizeof(GR32_NOREXBits), X86::GR32_NOREXRegClassID, 32, 1, true },
{ VK32, VK32Bits, 16, 8, sizeof(VK32Bits), X86::VK32RegClassID, 32, 1, true },
{ GR32_NOREX_NOSP, GR32_NOREX_NOSPBits, 1117, 7, sizeof(GR32_NOREX_NOSPBits), X86::GR32_NOREX_NOSPRegClassID, 32, 1, true },
{ RFP32, RFP32Bits, 21, 7, sizeof(RFP32Bits), X86::RFP32RegClassID, 32, 1, true },
{ VK32WM, VK32WMBits, 919, 7, sizeof(VK32WMBits), X86::VK32WMRegClassID, 32, 1, true },
{ GR32_ABCD, GR32_ABCDBits, 618, 4, sizeof(GR32_ABCDBits), X86::GR32_ABCDRegClassID, 32, 1, true },
{ GR32_TC, GR32_TCBits, 434, 4, sizeof(GR32_TCBits), X86::GR32_TCRegClassID, 32, 1, true },
{ GR32_ABCD_and_GR32_TC, GR32_ABCD_and_GR32_TCBits, 420, 3, sizeof(GR32_ABCD_and_GR32_TCBits), X86::GR32_ABCD_and_GR32_TCRegClassID, 32, 1, true },
{ GR32_AD, GR32_ADBits, 602, 2, sizeof(GR32_ADBits), X86::GR32_ADRegClassID, 32, 1, true },
{ GR32_BPSP, GR32_BPSPBits, 1172, 2, sizeof(GR32_BPSPBits), X86::GR32_BPSPRegClassID, 32, 1, true },
{ GR32_BSI, GR32_BSIBits, 861, 2, sizeof(GR32_BSIBits), X86::GR32_BSIRegClassID, 32, 1, true },
{ GR32_CB, GR32_CBBits, 272, 2, sizeof(GR32_CBBits), X86::GR32_CBRegClassID, 32, 1, true },
{ GR32_DC, GR32_DCBits, 315, 2, sizeof(GR32_DCBits), X86::GR32_DCRegClassID, 32, 1, true },
{ GR32_DIBP, GR32_DIBPBits, 1023, 2, sizeof(GR32_DIBPBits), X86::GR32_DIBPRegClassID, 32, 1, true },
{ GR32_SIDI, GR32_SIDIBits, 734, 2, sizeof(GR32_SIDIBits), X86::GR32_SIDIRegClassID, 32, 1, true },
{ LOW32_ADDR_ACCESS_RBP_with_sub_32bit, LOW32_ADDR_ACCESS_RBP_with_sub_32bitBits, 1439, 2, sizeof(LOW32_ADDR_ACCESS_RBP_with_sub_32bitBits), X86::LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClassID, 32, 1, true },
{ CCR, CCRBits, 1184, 1, sizeof(CCRBits), X86::CCRRegClassID, 32, -1, false },
{ DFCCR, DFCCRBits, 1182, 1, sizeof(DFCCRBits), X86::DFCCRRegClassID, 32, -1, false },
{ GR32_ABCD_and_GR32_BSI, GR32_ABCD_and_GR32_BSIBits, 847, 1, sizeof(GR32_ABCD_and_GR32_BSIBits), X86::GR32_ABCD_and_GR32_BSIRegClassID, 32, 1, true },
{ GR32_AD_and_GR32_DC, GR32_AD_and_GR32_DCBits, 346, 1, sizeof(GR32_AD_and_GR32_DCBits), X86::GR32_AD_and_GR32_DCRegClassID, 32, 1, true },
{ GR32_BPSP_and_GR32_DIBP, GR32_BPSP_and_GR32_DIBPBits, 1009, 1, sizeof(GR32_BPSP_and_GR32_DIBPBits), X86::GR32_BPSP_and_GR32_DIBPRegClassID, 32, 1, true },
{ GR32_BPSP_and_GR32_TC, GR32_BPSP_and_GR32_TCBits, 465, 1, sizeof(GR32_BPSP_and_GR32_TCBits), X86::GR32_BPSP_and_GR32_TCRegClassID, 32, 1, true },
{ GR32_BSI_and_GR32_SIDI, GR32_BSI_and_GR32_SIDIBits, 721, 1, sizeof(GR32_BSI_and_GR32_SIDIBits), X86::GR32_BSI_and_GR32_SIDIRegClassID, 32, 1, true },
{ GR32_CB_and_GR32_DC, GR32_CB_and_GR32_DCBits, 303, 1, sizeof(GR32_CB_and_GR32_DCBits), X86::GR32_CB_and_GR32_DCRegClassID, 32, 1, true },
{ GR32_DIBP_and_GR32_SIDI, GR32_DIBP_and_GR32_SIDIBits, 767, 1, sizeof(GR32_DIBP_and_GR32_SIDIBits), X86::GR32_DIBP_and_GR32_SIDIRegClassID, 32, 1, true },
{ LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit, LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitBits, 1509, 1, sizeof(LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitBits), X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitRegClassID, 32, 1, true },
{ LOW32_ADDR_ACCESS_with_sub_32bit, LOW32_ADDR_ACCESS_with_sub_32bitBits, 1476, 1, sizeof(LOW32_ADDR_ACCESS_with_sub_32bitBits), X86::LOW32_ADDR_ACCESS_with_sub_32bitRegClassID, 32, 1, true },
{ RFP64, RFP64Bits, 46, 7, sizeof(RFP64Bits), X86::RFP64RegClassID, 64, 1, true },
{ FR64X, FR64XBits, 1272, 32, sizeof(FR64XBits), X86::FR64XRegClassID, 64, 1, true },
{ GR64, GR64Bits, 57, 17, sizeof(GR64Bits), X86::GR64RegClassID, 64, 1, true },
{ CONTROL_REG, CONTROL_REGBits, 663, 16, sizeof(CONTROL_REGBits), X86::CONTROL_REGRegClassID, 64, 1, true },
{ FR64, FR64Bits, 52, 16, sizeof(FR64Bits), X86::FR64RegClassID, 64, 1, true },
{ GR64_with_sub_8bit, GR64_with_sub_8bitBits, 1560, 16, sizeof(GR64_with_sub_8bitBits), X86::GR64_with_sub_8bitRegClassID, 64, 1, true },
{ GR64_NOSP, GR64_NOSPBits, 1107, 15, sizeof(GR64_NOSPBits), X86::GR64_NOSPRegClassID, 64, 1, true },
{ GR64PLTSafe, GR64PLTSafeBits, 1427, 13, sizeof(GR64PLTSafeBits), X86::GR64PLTSafeRegClassID, 64, 1, true },
{ GR64_TC, GR64_TCBits, 532, 10, sizeof(GR64_TCBits), X86::GR64_TCRegClassID, 64, 1, true },
{ GR64_NOREX, GR64_NOREXBits, 1309, 9, sizeof(GR64_NOREXBits), X86::GR64_NOREXRegClassID, 64, 1, true },
{ GR64_TCW64, GR64_TCW64Bits, 79, 9, sizeof(GR64_TCW64Bits), X86::GR64_TCW64RegClassID, 64, 1, true },
{ GR64_TC_with_sub_8bit, GR64_TC_with_sub_8bitBits, 1619, 9, sizeof(GR64_TC_with_sub_8bitBits), X86::GR64_TC_with_sub_8bitRegClassID, 64, 1, true },
{ GR64_NOSP_and_GR64_TC, GR64_NOSP_and_GR64_TCBits, 518, 8, sizeof(GR64_NOSP_and_GR64_TCBits), X86::GR64_NOSP_and_GR64_TCRegClassID, 64, 1, true },
{ GR64_TCW64_with_sub_8bit, GR64_TCW64_with_sub_8bitBits, 1579, 8, sizeof(GR64_TCW64_with_sub_8bitBits), X86::GR64_TCW64_with_sub_8bitRegClassID, 64, 1, true },
{ GR64_TC_and_GR64_TCW64, GR64_TC_and_GR64_TCW64Bits, 67, 8, sizeof(GR64_TC_and_GR64_TCW64Bits), X86::GR64_TC_and_GR64_TCW64RegClassID, 64, 1, true },
{ GR64_with_sub_16bit_in_GR16_NOREX, GR64_with_sub_16bit_in_GR16_NOREXBits, 1332, 8, sizeof(GR64_with_sub_16bit_in_GR16_NOREXBits), X86::GR64_with_sub_16bit_in_GR16_NOREXRegClassID, 64, 1, true },
{ VK64, VK64Bits, 41, 8, sizeof(VK64Bits), X86::VK64RegClassID, 64, 1, true },
{ VR64, VR64Bits, 62, 8, sizeof(VR64Bits), X86::VR64RegClassID, 64, 1, true },
{ GR64PLTSafe_and_GR64_TC, GR64PLTSafe_and_GR64_TCBits, 578, 7, sizeof(GR64PLTSafe_and_GR64_TCBits), X86::GR64PLTSafe_and_GR64_TCRegClassID, 64, 1, true },
{ GR64_NOREX_NOSP, GR64_NOREX_NOSPBits, 1133, 7, sizeof(GR64_NOREX_NOSPBits), X86::GR64_NOREX_NOSPRegClassID, 64, 1, true },
{ GR64_NOREX_and_GR64_TC, GR64_NOREX_and_GR64_TCBits, 540, 7, sizeof(GR64_NOREX_and_GR64_TCBits), X86::GR64_NOREX_and_GR64_TCRegClassID, 64, 1, true },
{ GR64_NOSP_and_GR64_TCW64, GR64_NOSP_and_GR64_TCW64Bits, 102, 7, sizeof(GR64_NOSP_and_GR64_TCW64Bits), X86::GR64_NOSP_and_GR64_TCW64RegClassID, 64, 1, true },
{ GR64_TCW64_and_GR64_TC_with_sub_8bit, GR64_TCW64_and_GR64_TC_with_sub_8bitBits, 1604, 7, sizeof(GR64_TCW64_and_GR64_TC_with_sub_8bitBits), X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID, 64, 1, true },
{ VK64WM, VK64WMBits, 932, 7, sizeof(VK64WMBits), X86::VK64WMRegClassID, 64, 1, true },
{ GR64_TC_and_GR64_NOSP_and_GR64_TCW64, GR64_TC_and_GR64_NOSP_and_GR64_TCW64Bits, 90, 6, sizeof(GR64_TC_and_GR64_NOSP_and_GR64_TCW64Bits), X86::GR64_TC_and_GR64_NOSP_and_GR64_TCW64RegClassID, 64, 1, true },
{ GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX, GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXBits, 1320, 6, sizeof(GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXBits), X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID, 64, 1, true },
{ GR64PLTSafe_and_GR64_TCW64, GR64PLTSafe_and_GR64_TCW64Bits, 153, 5, sizeof(GR64PLTSafe_and_GR64_TCW64Bits), X86::GR64PLTSafe_and_GR64_TCW64RegClassID, 64, 1, true },
{ GR64_NOREX_and_GR64PLTSafe_and_GR64_TC, GR64_NOREX_and_GR64PLTSafe_and_GR64_TCBits, 563, 5, sizeof(GR64_NOREX_and_GR64PLTSafe_and_GR64_TCBits), X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClassID, 64, 1, true },
{ GR64_NOREX_and_GR64_TCW64, GR64_NOREX_and_GR64_TCW64Bits, 127, 5, sizeof(GR64_NOREX_and_GR64_TCW64Bits), X86::GR64_NOREX_and_GR64_TCW64RegClassID, 64, 1, true },
{ GR64_ABCD, GR64_ABCDBits, 628, 4, sizeof(GR64_ABCDBits), X86::GR64_ABCDRegClassID, 64, 1, true },
{ GR64_with_sub_32bit_in_GR32_TC, GR64_with_sub_32bit_in_GR32_TCBits, 487, 4, sizeof(GR64_with_sub_32bit_in_GR32_TCBits), X86::GR64_with_sub_32bit_in_GR32_TCRegClassID, 64, 1, true },
{ GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC, GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCBits, 397, 3, sizeof(GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCBits), X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClassID, 64, 1, true },
{ GR64_AD, GR64_ADBits, 610, 2, sizeof(GR64_ADBits), X86::GR64_ADRegClassID, 64, 1, true },
{ GR64_and_LOW32_ADDR_ACCESS_RBP, GR64_and_LOW32_ADDR_ACCESS_RBPBits, 1066, 2, sizeof(GR64_and_LOW32_ADDR_ACCESS_RBPBits), X86::GR64_and_LOW32_ADDR_ACCESS_RBPRegClassID, 64, 1, true },
{ GR64_with_sub_32bit_in_GR32_BPSP, GR64_with_sub_32bit_in_GR32_BPSPBits, 1149, 2, sizeof(GR64_with_sub_32bit_in_GR32_BPSPBits), X86::GR64_with_sub_32bit_in_GR32_BPSPRegClassID, 64, 1, true },
{ GR64_with_sub_32bit_in_GR32_BSI, GR64_with_sub_32bit_in_GR32_BSIBits, 870, 2, sizeof(GR64_with_sub_32bit_in_GR32_BSIBits), X86::GR64_with_sub_32bit_in_GR32_BSIRegClassID, 64, 1, true },
{ GR64_with_sub_32bit_in_GR32_CB, GR64_with_sub_32bit_in_GR32_CBBits, 249, 2, sizeof(GR64_with_sub_32bit_in_GR32_CBBits), X86::GR64_with_sub_32bit_in_GR32_CBRegClassID, 64, 1, true },
{ GR64_with_sub_32bit_in_GR32_DC, GR64_with_sub_32bit_in_GR32_DCBits, 366, 2, sizeof(GR64_with_sub_32bit_in_GR32_DCBits), X86::GR64_with_sub_32bit_in_GR32_DCRegClassID, 64, 1, true },
{ GR64_with_sub_32bit_in_GR32_DIBP, GR64_with_sub_32bit_in_GR32_DIBPBits, 1033, 2, sizeof(GR64_with_sub_32bit_in_GR32_DIBPBits), X86::GR64_with_sub_32bit_in_GR32_DIBPRegClassID, 64, 1, true },
{ GR64_with_sub_32bit_in_GR32_SIDI, GR64_with_sub_32bit_in_GR32_SIDIBits, 791, 2, sizeof(GR64_with_sub_32bit_in_GR32_SIDIBits), X86::GR64_with_sub_32bit_in_GR32_SIDIRegClassID, 64, 1, true },
{ GR64_and_LOW32_ADDR_ACCESS, GR64_and_LOW32_ADDR_ACCESSBits, 1235, 1, sizeof(GR64_and_LOW32_ADDR_ACCESSBits), X86::GR64_and_LOW32_ADDR_ACCESSRegClassID, 64, 1, true },
{ GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI, GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIBits, 824, 1, sizeof(GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIBits), X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIRegClassID, 64, 1, true },
{ GR64_with_sub_32bit_in_GR32_AD_and_GR32_DC, GR64_with_sub_32bit_in_GR32_AD_and_GR32_DCBits, 323, 1, sizeof(GR64_with_sub_32bit_in_GR32_AD_and_GR32_DCBits), X86::GR64_with_sub_32bit_in_GR32_AD_and_GR32_DCRegClassID, 64, 1, true },
{ GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP, GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPBits, 986, 1, sizeof(GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPBits), X86::GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPRegClassID, 64, 1, true },
{ GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC, GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCBits, 442, 1, sizeof(GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCBits), X86::GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCRegClassID, 64, 1, true },
{ GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI, GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIBits, 698, 1, sizeof(GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIBits), X86::GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIRegClassID, 64, 1, true },
{ GR64_with_sub_32bit_in_GR32_CB_and_GR32_DC, GR64_with_sub_32bit_in_GR32_CB_and_GR32_DCBits, 280, 1, sizeof(GR64_with_sub_32bit_in_GR32_CB_and_GR32_DCBits), X86::GR64_with_sub_32bit_in_GR32_CB_and_GR32_DCRegClassID, 64, 1, true },
{ GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI, GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIBits, 744, 1, sizeof(GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIBits), X86::GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIRegClassID, 64, 1, true },
{ RST, RSTBits, 1262, 8, sizeof(RSTBits), X86::RSTRegClassID, 80, 1, false },
{ RFP80, RFP80Bits, 0, 7, sizeof(RFP80Bits), X86::RFP80RegClassID, 80, 1, true },
{ RFP80_7, RFP80_7Bits, 222, 1, sizeof(RFP80_7Bits), X86::RFP80_7RegClassID, 80, 1, false },
{ VR128X, VR128XBits, 1291, 32, sizeof(VR128XBits), X86::VR128XRegClassID, 128, 1, true },
{ VR128, VR128Bits, 230, 16, sizeof(VR128Bits), X86::VR128RegClassID, 128, 1, true },
{ VR256X, VR256XBits, 1284, 32, sizeof(VR256XBits), X86::VR256XRegClassID, 256, 1, true },
{ VR256, VR256Bits, 216, 16, sizeof(VR256Bits), X86::VR256RegClassID, 256, 1, true },
{ VR512, VR512Bits, 10, 32, sizeof(VR512Bits), X86::VR512RegClassID, 512, 1, true },
{ VR512_0_15, VR512_0_15Bits, 184, 16, sizeof(VR512_0_15Bits), X86::VR512_0_15RegClassID, 512, 1, true },
{ TILE, TILEBits, 648, 8, sizeof(TILEBits), X86::TILERegClassID, 8192, -1, true },
};
// X86 Dwarf<->LLVM register mappings.
extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour0Dwarf2L[] = {
{ 0U, X86::RAX },
{ 1U, X86::RDX },
{ 2U, X86::RCX },
{ 3U, X86::RBX },
{ 4U, X86::RSI },
{ 5U, X86::RDI },
{ 6U, X86::RBP },
{ 7U, X86::RSP },
{ 8U, X86::R8 },
{ 9U, X86::R9 },
{ 10U, X86::R10 },
{ 11U, X86::R11 },
{ 12U, X86::R12 },
{ 13U, X86::R13 },
{ 14U, X86::R14 },
{ 15U, X86::R15 },
{ 16U, X86::RIP },
{ 17U, X86::XMM0 },
{ 18U, X86::XMM1 },
{ 19U, X86::XMM2 },
{ 20U, X86::XMM3 },
{ 21U, X86::XMM4 },
{ 22U, X86::XMM5 },
{ 23U, X86::XMM6 },
{ 24U, X86::XMM7 },
{ 25U, X86::XMM8 },
{ 26U, X86::XMM9 },
{ 27U, X86::XMM10 },
{ 28U, X86::XMM11 },
{ 29U, X86::XMM12 },
{ 30U, X86::XMM13 },
{ 31U, X86::XMM14 },
{ 32U, X86::XMM15 },
{ 33U, X86::ST0 },
{ 34U, X86::ST1 },
{ 35U, X86::ST2 },
{ 36U, X86::ST3 },
{ 37U, X86::ST4 },
{ 38U, X86::ST5 },
{ 39U, X86::ST6 },
{ 40U, X86::ST7 },
{ 41U, X86::MM0 },
{ 42U, X86::MM1 },
{ 43U, X86::MM2 },
{ 44U, X86::MM3 },
{ 45U, X86::MM4 },
{ 46U, X86::MM5 },
{ 47U, X86::MM6 },
{ 48U, X86::MM7 },
{ 49U, X86::RFLAGS },
{ 58U, X86::FS_BASE },
{ 59U, X86::GS_BASE },
{ 67U, X86::XMM16 },
{ 68U, X86::XMM17 },
{ 69U, X86::XMM18 },
{ 70U, X86::XMM19 },
{ 71U, X86::XMM20 },
{ 72U, X86::XMM21 },
{ 73U, X86::XMM22 },
{ 74U, X86::XMM23 },
{ 75U, X86::XMM24 },
{ 76U, X86::XMM25 },
{ 77U, X86::XMM26 },
{ 78U, X86::XMM27 },
{ 79U, X86::XMM28 },
{ 80U, X86::XMM29 },
{ 81U, X86::XMM30 },
{ 82U, X86::XMM31 },
{ 118U, X86::K0 },
{ 119U, X86::K1 },
{ 120U, X86::K2 },
{ 121U, X86::K3 },
{ 122U, X86::K4 },
{ 123U, X86::K5 },
{ 124U, X86::K6 },
{ 125U, X86::K7 },
};
extern const unsigned X86DwarfFlavour0Dwarf2LSize = std::size(X86DwarfFlavour0Dwarf2L);
extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour1Dwarf2L[] = {
{ 0U, X86::EAX },
{ 1U, X86::ECX },
{ 2U, X86::EDX },
{ 3U, X86::EBX },
{ 4U, X86::EBP },
{ 5U, X86::ESP },
{ 6U, X86::ESI },
{ 7U, X86::EDI },
{ 8U, X86::EIP },
{ 9U, X86::EFLAGS },
{ 12U, X86::ST0 },
{ 13U, X86::ST1 },
{ 14U, X86::ST2 },
{ 15U, X86::ST3 },
{ 16U, X86::ST4 },
{ 17U, X86::ST5 },
{ 18U, X86::ST6 },
{ 19U, X86::ST7 },
{ 21U, X86::XMM0 },
{ 22U, X86::XMM1 },
{ 23U, X86::XMM2 },
{ 24U, X86::XMM3 },
{ 25U, X86::XMM4 },
{ 26U, X86::XMM5 },
{ 27U, X86::XMM6 },
{ 28U, X86::XMM7 },
{ 29U, X86::MM0 },
{ 30U, X86::MM1 },
{ 31U, X86::MM2 },
{ 32U, X86::MM3 },
{ 33U, X86::MM4 },
{ 34U, X86::MM5 },
{ 35U, X86::MM6 },
{ 36U, X86::MM7 },
{ 93U, X86::K0 },
{ 94U, X86::K1 },
{ 95U, X86::K2 },
{ 96U, X86::K3 },
{ 97U, X86::K4 },
{ 98U, X86::K5 },
{ 99U, X86::K6 },
{ 100U, X86::K7 },
};
extern const unsigned X86DwarfFlavour1Dwarf2LSize = std::size(X86DwarfFlavour1Dwarf2L);
extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour2Dwarf2L[] = {
{ 0U, X86::EAX },
{ 1U, X86::ECX },
{ 2U, X86::EDX },
{ 3U, X86::EBX },
{ 4U, X86::ESP },
{ 5U, X86::EBP },
{ 6U, X86::ESI },
{ 7U, X86::EDI },
{ 8U, X86::EIP },
{ 9U, X86::EFLAGS },
{ 11U, X86::ST0 },
{ 12U, X86::ST1 },
{ 13U, X86::ST2 },
{ 14U, X86::ST3 },
{ 15U, X86::ST4 },
{ 16U, X86::ST5 },
{ 17U, X86::ST6 },
{ 18U, X86::ST7 },
{ 21U, X86::XMM0 },
{ 22U, X86::XMM1 },
{ 23U, X86::XMM2 },
{ 24U, X86::XMM3 },
{ 25U, X86::XMM4 },
{ 26U, X86::XMM5 },
{ 27U, X86::XMM6 },
{ 28U, X86::XMM7 },
{ 29U, X86::MM0 },
{ 30U, X86::MM1 },
{ 31U, X86::MM2 },
{ 32U, X86::MM3 },
{ 33U, X86::MM4 },
{ 34U, X86::MM5 },
{ 35U, X86::MM6 },
{ 36U, X86::MM7 },
{ 93U, X86::K0 },
{ 94U, X86::K1 },
{ 95U, X86::K2 },
{ 96U, X86::K3 },
{ 97U, X86::K4 },
{ 98U, X86::K5 },
{ 99U, X86::K6 },
{ 100U, X86::K7 },
};
extern const unsigned X86DwarfFlavour2Dwarf2LSize = std::size(X86DwarfFlavour2Dwarf2L);
extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour0Dwarf2L[] = {
{ 0U, X86::RAX },
{ 1U, X86::RDX },
{ 2U, X86::RCX },
{ 3U, X86::RBX },
{ 4U, X86::RSI },
{ 5U, X86::RDI },
{ 6U, X86::RBP },
{ 7U, X86::RSP },
{ 8U, X86::R8 },
{ 9U, X86::R9 },
{ 10U, X86::R10 },
{ 11U, X86::R11 },
{ 12U, X86::R12 },
{ 13U, X86::R13 },
{ 14U, X86::R14 },
{ 15U, X86::R15 },
{ 16U, X86::RIP },
{ 17U, X86::XMM0 },
{ 18U, X86::XMM1 },
{ 19U, X86::XMM2 },
{ 20U, X86::XMM3 },
{ 21U, X86::XMM4 },
{ 22U, X86::XMM5 },
{ 23U, X86::XMM6 },
{ 24U, X86::XMM7 },
{ 25U, X86::XMM8 },
{ 26U, X86::XMM9 },
{ 27U, X86::XMM10 },
{ 28U, X86::XMM11 },
{ 29U, X86::XMM12 },
{ 30U, X86::XMM13 },
{ 31U, X86::XMM14 },
{ 32U, X86::XMM15 },
{ 33U, X86::ST0 },
{ 34U, X86::ST1 },
{ 35U, X86::ST2 },
{ 36U, X86::ST3 },
{ 37U, X86::ST4 },
{ 38U, X86::ST5 },
{ 39U, X86::ST6 },
{ 40U, X86::ST7 },
{ 41U, X86::MM0 },
{ 42U, X86::MM1 },
{ 43U, X86::MM2 },
{ 44U, X86::MM3 },
{ 45U, X86::MM4 },
{ 46U, X86::MM5 },
{ 47U, X86::MM6 },
{ 48U, X86::MM7 },
{ 49U, X86::RFLAGS },
{ 58U, X86::FS_BASE },
{ 59U, X86::GS_BASE },
{ 67U, X86::XMM16 },
{ 68U, X86::XMM17 },
{ 69U, X86::XMM18 },
{ 70U, X86::XMM19 },
{ 71U, X86::XMM20 },
{ 72U, X86::XMM21 },
{ 73U, X86::XMM22 },
{ 74U, X86::XMM23 },
{ 75U, X86::XMM24 },
{ 76U, X86::XMM25 },
{ 77U, X86::XMM26 },
{ 78U, X86::XMM27 },
{ 79U, X86::XMM28 },
{ 80U, X86::XMM29 },
{ 81U, X86::XMM30 },
{ 82U, X86::XMM31 },
{ 118U, X86::K0 },
{ 119U, X86::K1 },
{ 120U, X86::K2 },
{ 121U, X86::K3 },
{ 122U, X86::K4 },
{ 123U, X86::K5 },
{ 124U, X86::K6 },
{ 125U, X86::K7 },
};
extern const unsigned X86EHFlavour0Dwarf2LSize = std::size(X86EHFlavour0Dwarf2L);
extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour1Dwarf2L[] = {
{ 0U, X86::EAX },
{ 1U, X86::ECX },
{ 2U, X86::EDX },
{ 3U, X86::EBX },
{ 4U, X86::EBP },
{ 5U, X86::ESP },
{ 6U, X86::ESI },
{ 7U, X86::EDI },
{ 8U, X86::EIP },
{ 9U, X86::EFLAGS },
{ 12U, X86::ST0 },
{ 13U, X86::ST1 },
{ 14U, X86::ST2 },
{ 15U, X86::ST3 },
{ 16U, X86::ST4 },
{ 17U, X86::ST5 },
{ 18U, X86::ST6 },
{ 19U, X86::ST7 },
{ 21U, X86::XMM0 },
{ 22U, X86::XMM1 },
{ 23U, X86::XMM2 },
{ 24U, X86::XMM3 },
{ 25U, X86::XMM4 },
{ 26U, X86::XMM5 },
{ 27U, X86::XMM6 },
{ 28U, X86::XMM7 },
{ 29U, X86::MM0 },
{ 30U, X86::MM1 },
{ 31U, X86::MM2 },
{ 32U, X86::MM3 },
{ 33U, X86::MM4 },
{ 34U, X86::MM5 },
{ 35U, X86::MM6 },
{ 36U, X86::MM7 },
{ 93U, X86::K0 },
{ 94U, X86::K1 },
{ 95U, X86::K2 },
{ 96U, X86::K3 },
{ 97U, X86::K4 },
{ 98U, X86::K5 },
{ 99U, X86::K6 },
{ 100U, X86::K7 },
};
extern const unsigned X86EHFlavour1Dwarf2LSize = std::size(X86EHFlavour1Dwarf2L);
extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour2Dwarf2L[] = {
{ 0U, X86::EAX },
{ 1U, X86::ECX },
{ 2U, X86::EDX },
{ 3U, X86::EBX },
{ 4U, X86::ESP },
{ 5U, X86::EBP },
{ 6U, X86::ESI },
{ 7U, X86::EDI },
{ 8U, X86::EIP },
{ 9U, X86::EFLAGS },
{ 11U, X86::ST0 },
{ 12U, X86::ST1 },
{ 13U, X86::ST2 },
{ 14U, X86::ST3 },
{ 15U, X86::ST4 },
{ 16U, X86::ST5 },
{ 17U, X86::ST6 },
{ 18U, X86::ST7 },
{ 21U, X86::XMM0 },
{ 22U, X86::XMM1 },
{ 23U, X86::XMM2 },
{ 24U, X86::XMM3 },
{ 25U, X86::XMM4 },
{ 26U, X86::XMM5 },
{ 27U, X86::XMM6 },
{ 28U, X86::XMM7 },
{ 29U, X86::MM0 },
{ 30U, X86::MM1 },
{ 31U, X86::MM2 },
{ 32U, X86::MM3 },
{ 33U, X86::MM4 },
{ 34U, X86::MM5 },
{ 35U, X86::MM6 },
{ 36U, X86::MM7 },
{ 93U, X86::K0 },
{ 94U, X86::K1 },
{ 95U, X86::K2 },
{ 96U, X86::K3 },
{ 97U, X86::K4 },
{ 98U, X86::K5 },
{ 99U, X86::K6 },
{ 100U, X86::K7 },
};
extern const unsigned X86EHFlavour2Dwarf2LSize = std::size(X86EHFlavour2Dwarf2L);
extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour0L2Dwarf[] = {
{ X86::EAX, -2U },
{ X86::EBP, -2U },
{ X86::EBX, -2U },
{ X86::ECX, -2U },
{ X86::EDI, -2U },
{ X86::EDX, -2U },
{ X86::EFLAGS, 49U },
{ X86::EIP, -2U },
{ X86::ESI, -2U },
{ X86::ESP, -2U },
{ X86::FS_BASE, 58U },
{ X86::GS_BASE, 59U },
{ X86::RAX, 0U },
{ X86::RBP, 6U },
{ X86::RBX, 3U },
{ X86::RCX, 2U },
{ X86::RDI, 5U },
{ X86::RDX, 1U },
{ X86::RFLAGS, 49U },
{ X86::RIP, 16U },
{ X86::RSI, 4U },
{ X86::RSP, 7U },
{ X86::_EFLAGS, 49U },
{ X86::K0, 118U },
{ X86::K1, 119U },
{ X86::K2, 120U },
{ X86::K3, 121U },
{ X86::K4, 122U },
{ X86::K5, 123U },
{ X86::K6, 124U },
{ X86::K7, 125U },
{ X86::MM0, 41U },
{ X86::MM1, 42U },
{ X86::MM2, 43U },
{ X86::MM3, 44U },
{ X86::MM4, 45U },
{ X86::MM5, 46U },
{ X86::MM6, 47U },
{ X86::MM7, 48U },
{ X86::R8, 8U },
{ X86::R9, 9U },
{ X86::R10, 10U },
{ X86::R11, 11U },
{ X86::R12, 12U },
{ X86::R13, 13U },
{ X86::R14, 14U },
{ X86::R15, 15U },
{ X86::ST0, 33U },
{ X86::ST1, 34U },
{ X86::ST2, 35U },
{ X86::ST3, 36U },
{ X86::ST4, 37U },
{ X86::ST5, 38U },
{ X86::ST6, 39U },
{ X86::ST7, 40U },
{ X86::XMM0, 17U },
{ X86::XMM1, 18U },
{ X86::XMM2, 19U },
{ X86::XMM3, 20U },
{ X86::XMM4, 21U },
{ X86::XMM5, 22U },
{ X86::XMM6, 23U },
{ X86::XMM7, 24U },
{ X86::XMM8, 25U },
{ X86::XMM9, 26U },
{ X86::XMM10, 27U },
{ X86::XMM11, 28U },
{ X86::XMM12, 29U },
{ X86::XMM13, 30U },
{ X86::XMM14, 31U },
{ X86::XMM15, 32U },
{ X86::XMM16, 67U },
{ X86::XMM17, 68U },
{ X86::XMM18, 69U },
{ X86::XMM19, 70U },
{ X86::XMM20, 71U },
{ X86::XMM21, 72U },
{ X86::XMM22, 73U },
{ X86::XMM23, 74U },
{ X86::XMM24, 75U },
{ X86::XMM25, 76U },
{ X86::XMM26, 77U },
{ X86::XMM27, 78U },
{ X86::XMM28, 79U },
{ X86::XMM29, 80U },
{ X86::XMM30, 81U },
{ X86::XMM31, 82U },
{ X86::YMM0, 17U },
{ X86::YMM1, 18U },
{ X86::YMM2, 19U },
{ X86::YMM3, 20U },
{ X86::YMM4, 21U },
{ X86::YMM5, 22U },
{ X86::YMM6, 23U },
{ X86::YMM7, 24U },
{ X86::YMM8, 25U },
{ X86::YMM9, 26U },
{ X86::YMM10, 27U },
{ X86::YMM11, 28U },
{ X86::YMM12, 29U },
{ X86::YMM13, 30U },
{ X86::YMM14, 31U },
{ X86::YMM15, 32U },
{ X86::YMM16, 67U },
{ X86::YMM17, 68U },
{ X86::YMM18, 69U },
{ X86::YMM19, 70U },
{ X86::YMM20, 71U },
{ X86::YMM21, 72U },
{ X86::YMM22, 73U },
{ X86::YMM23, 74U },
{ X86::YMM24, 75U },
{ X86::YMM25, 76U },
{ X86::YMM26, 77U },
{ X86::YMM27, 78U },
{ X86::YMM28, 79U },
{ X86::YMM29, 80U },
{ X86::YMM30, 81U },
{ X86::YMM31, 82U },
{ X86::ZMM0, 17U },
{ X86::ZMM1, 18U },
{ X86::ZMM2, 19U },
{ X86::ZMM3, 20U },
{ X86::ZMM4, 21U },
{ X86::ZMM5, 22U },
{ X86::ZMM6, 23U },
{ X86::ZMM7, 24U },
{ X86::ZMM8, 25U },
{ X86::ZMM9, 26U },
{ X86::ZMM10, 27U },
{ X86::ZMM11, 28U },
{ X86::ZMM12, 29U },
{ X86::ZMM13, 30U },
{ X86::ZMM14, 31U },
{ X86::ZMM15, 32U },
{ X86::ZMM16, 67U },
{ X86::ZMM17, 68U },
{ X86::ZMM18, 69U },
{ X86::ZMM19, 70U },
{ X86::ZMM20, 71U },
{ X86::ZMM21, 72U },
{ X86::ZMM22, 73U },
{ X86::ZMM23, 74U },
{ X86::ZMM24, 75U },
{ X86::ZMM25, 76U },
{ X86::ZMM26, 77U },
{ X86::ZMM27, 78U },
{ X86::ZMM28, 79U },
{ X86::ZMM29, 80U },
{ X86::ZMM30, 81U },
{ X86::ZMM31, 82U },
};
extern const unsigned X86DwarfFlavour0L2DwarfSize = std::size(X86DwarfFlavour0L2Dwarf);
extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour1L2Dwarf[] = {
{ X86::EAX, 0U },
{ X86::EBP, 4U },
{ X86::EBX, 3U },
{ X86::ECX, 1U },
{ X86::EDI, 7U },
{ X86::EDX, 2U },
{ X86::EFLAGS, 9U },
{ X86::EIP, 8U },
{ X86::ESI, 6U },
{ X86::ESP, 5U },
{ X86::FS_BASE, -2U },
{ X86::GS_BASE, -2U },
{ X86::RAX, -2U },
{ X86::RBP, -2U },
{ X86::RBX, -2U },
{ X86::RCX, -2U },
{ X86::RDI, -2U },
{ X86::RDX, -2U },
{ X86::RFLAGS, -2U },
{ X86::RIP, -2U },
{ X86::RSI, -2U },
{ X86::RSP, -2U },
{ X86::_EFLAGS, 9U },
{ X86::K0, 93U },
{ X86::K1, 94U },
{ X86::K2, 95U },
{ X86::K3, 96U },
{ X86::K4, 97U },
{ X86::K5, 98U },
{ X86::K6, 99U },
{ X86::K7, 100U },
{ X86::MM0, 29U },
{ X86::MM1, 30U },
{ X86::MM2, 31U },
{ X86::MM3, 32U },
{ X86::MM4, 33U },
{ X86::MM5, 34U },
{ X86::MM6, 35U },
{ X86::MM7, 36U },
{ X86::R8, -2U },
{ X86::R9, -2U },
{ X86::R10, -2U },
{ X86::R11, -2U },
{ X86::R12, -2U },
{ X86::R13, -2U },
{ X86::R14, -2U },
{ X86::R15, -2U },
{ X86::ST0, 12U },
{ X86::ST1, 13U },
{ X86::ST2, 14U },
{ X86::ST3, 15U },
{ X86::ST4, 16U },
{ X86::ST5, 17U },
{ X86::ST6, 18U },
{ X86::ST7, 19U },
{ X86::XMM0, 21U },
{ X86::XMM1, 22U },
{ X86::XMM2, 23U },
{ X86::XMM3, 24U },
{ X86::XMM4, 25U },
{ X86::XMM5, 26U },
{ X86::XMM6, 27U },
{ X86::XMM7, 28U },
{ X86::XMM8, -2U },
{ X86::XMM9, -2U },
{ X86::XMM10, -2U },
{ X86::XMM11, -2U },
{ X86::XMM12, -2U },
{ X86::XMM13, -2U },
{ X86::XMM14, -2U },
{ X86::XMM15, -2U },
{ X86::XMM16, -2U },
{ X86::XMM17, -2U },
{ X86::XMM18, -2U },
{ X86::XMM19, -2U },
{ X86::XMM20, -2U },
{ X86::XMM21, -2U },
{ X86::XMM22, -2U },
{ X86::XMM23, -2U },
{ X86::XMM24, -2U },
{ X86::XMM25, -2U },
{ X86::XMM26, -2U },
{ X86::XMM27, -2U },
{ X86::XMM28, -2U },
{ X86::XMM29, -2U },
{ X86::XMM30, -2U },
{ X86::XMM31, -2U },
{ X86::YMM0, 21U },
{ X86::YMM1, 22U },
{ X86::YMM2, 23U },
{ X86::YMM3, 24U },
{ X86::YMM4, 25U },
{ X86::YMM5, 26U },
{ X86::YMM6, 27U },
{ X86::YMM7, 28U },
{ X86::YMM8, -2U },
{ X86::YMM9, -2U },
{ X86::YMM10, -2U },
{ X86::YMM11, -2U },
{ X86::YMM12, -2U },
{ X86::YMM13, -2U },
{ X86::YMM14, -2U },
{ X86::YMM15, -2U },
{ X86::YMM16, -2U },
{ X86::YMM17, -2U },
{ X86::YMM18, -2U },
{ X86::YMM19, -2U },
{ X86::YMM20, -2U },
{ X86::YMM21, -2U },
{ X86::YMM22, -2U },
{ X86::YMM23, -2U },
{ X86::YMM24, -2U },
{ X86::YMM25, -2U },
{ X86::YMM26, -2U },
{ X86::YMM27, -2U },
{ X86::YMM28, -2U },
{ X86::YMM29, -2U },
{ X86::YMM30, -2U },
{ X86::YMM31, -2U },
{ X86::ZMM0, 21U },
{ X86::ZMM1, 22U },
{ X86::ZMM2, 23U },
{ X86::ZMM3, 24U },
{ X86::ZMM4, 25U },
{ X86::ZMM5, 26U },
{ X86::ZMM6, 27U },
{ X86::ZMM7, 28U },
{ X86::ZMM8, -2U },
{ X86::ZMM9, -2U },
{ X86::ZMM10, -2U },
{ X86::ZMM11, -2U },
{ X86::ZMM12, -2U },
{ X86::ZMM13, -2U },
{ X86::ZMM14, -2U },
{ X86::ZMM15, -2U },
{ X86::ZMM16, -2U },
{ X86::ZMM17, -2U },
{ X86::ZMM18, -2U },
{ X86::ZMM19, -2U },
{ X86::ZMM20, -2U },
{ X86::ZMM21, -2U },
{ X86::ZMM22, -2U },
{ X86::ZMM23, -2U },
{ X86::ZMM24, -2U },
{ X86::ZMM25, -2U },
{ X86::ZMM26, -2U },
{ X86::ZMM27, -2U },
{ X86::ZMM28, -2U },
{ X86::ZMM29, -2U },
{ X86::ZMM30, -2U },
{ X86::ZMM31, -2U },
};
extern const unsigned X86DwarfFlavour1L2DwarfSize = std::size(X86DwarfFlavour1L2Dwarf);
extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour2L2Dwarf[] = {
{ X86::EAX, 0U },
{ X86::EBP, 5U },
{ X86::EBX, 3U },
{ X86::ECX, 1U },
{ X86::EDI, 7U },
{ X86::EDX, 2U },
{ X86::EFLAGS, 9U },
{ X86::EIP, 8U },
{ X86::ESI, 6U },
{ X86::ESP, 4U },
{ X86::FS_BASE, -2U },
{ X86::GS_BASE, -2U },
{ X86::RAX, -2U },
{ X86::RBP, -2U },
{ X86::RBX, -2U },
{ X86::RCX, -2U },
{ X86::RDI, -2U },
{ X86::RDX, -2U },
{ X86::RFLAGS, -2U },
{ X86::RIP, -2U },
{ X86::RSI, -2U },
{ X86::RSP, -2U },
{ X86::_EFLAGS, 9U },
{ X86::K0, 93U },
{ X86::K1, 94U },
{ X86::K2, 95U },
{ X86::K3, 96U },
{ X86::K4, 97U },
{ X86::K5, 98U },
{ X86::K6, 99U },
{ X86::K7, 100U },
{ X86::MM0, 29U },
{ X86::MM1, 30U },
{ X86::MM2, 31U },
{ X86::MM3, 32U },
{ X86::MM4, 33U },
{ X86::MM5, 34U },
{ X86::MM6, 35U },
{ X86::MM7, 36U },
{ X86::R8, -2U },
{ X86::R9, -2U },
{ X86::R10, -2U },
{ X86::R11, -2U },
{ X86::R12, -2U },
{ X86::R13, -2U },
{ X86::R14, -2U },
{ X86::R15, -2U },
{ X86::ST0, 11U },
{ X86::ST1, 12U },
{ X86::ST2, 13U },
{ X86::ST3, 14U },
{ X86::ST4, 15U },
{ X86::ST5, 16U },
{ X86::ST6, 17U },
{ X86::ST7, 18U },
{ X86::XMM0, 21U },
{ X86::XMM1, 22U },
{ X86::XMM2, 23U },
{ X86::XMM3, 24U },
{ X86::XMM4, 25U },
{ X86::XMM5, 26U },
{ X86::XMM6, 27U },
{ X86::XMM7, 28U },
{ X86::XMM8, -2U },
{ X86::XMM9, -2U },
{ X86::XMM10, -2U },
{ X86::XMM11, -2U },
{ X86::XMM12, -2U },
{ X86::XMM13, -2U },
{ X86::XMM14, -2U },
{ X86::XMM15, -2U },
{ X86::XMM16, -2U },
{ X86::XMM17, -2U },
{ X86::XMM18, -2U },
{ X86::XMM19, -2U },
{ X86::XMM20, -2U },
{ X86::XMM21, -2U },
{ X86::XMM22, -2U },
{ X86::XMM23, -2U },
{ X86::XMM24, -2U },
{ X86::XMM25, -2U },
{ X86::XMM26, -2U },
{ X86::XMM27, -2U },
{ X86::XMM28, -2U },
{ X86::XMM29, -2U },
{ X86::XMM30, -2U },
{ X86::XMM31, -2U },
{ X86::YMM0, 21U },
{ X86::YMM1, 22U },
{ X86::YMM2, 23U },
{ X86::YMM3, 24U },
{ X86::YMM4, 25U },
{ X86::YMM5, 26U },
{ X86::YMM6, 27U },
{ X86::YMM7, 28U },
{ X86::YMM8, -2U },
{ X86::YMM9, -2U },
{ X86::YMM10, -2U },
{ X86::YMM11, -2U },
{ X86::YMM12, -2U },
{ X86::YMM13, -2U },
{ X86::YMM14, -2U },
{ X86::YMM15, -2U },
{ X86::YMM16, -2U },
{ X86::YMM17, -2U },
{ X86::YMM18, -2U },
{ X86::YMM19, -2U },
{ X86::YMM20, -2U },
{ X86::YMM21, -2U },
{ X86::YMM22, -2U },
{ X86::YMM23, -2U },
{ X86::YMM24, -2U },
{ X86::YMM25, -2U },
{ X86::YMM26, -2U },
{ X86::YMM27, -2U },
{ X86::YMM28, -2U },
{ X86::YMM29, -2U },
{ X86::YMM30, -2U },
{ X86::YMM31, -2U },
{ X86::ZMM0, 21U },
{ X86::ZMM1, 22U },
{ X86::ZMM2, 23U },
{ X86::ZMM3, 24U },
{ X86::ZMM4, 25U },
{ X86::ZMM5, 26U },
{ X86::ZMM6, 27U },
{ X86::ZMM7, 28U },
{ X86::ZMM8, -2U },
{ X86::ZMM9, -2U },
{ X86::ZMM10, -2U },
{ X86::ZMM11, -2U },
{ X86::ZMM12, -2U },
{ X86::ZMM13, -2U },
{ X86::ZMM14, -2U },
{ X86::ZMM15, -2U },
{ X86::ZMM16, -2U },
{ X86::ZMM17, -2U },
{ X86::ZMM18, -2U },
{ X86::ZMM19, -2U },
{ X86::ZMM20, -2U },
{ X86::ZMM21, -2U },
{ X86::ZMM22, -2U },
{ X86::ZMM23, -2U },
{ X86::ZMM24, -2U },
{ X86::ZMM25, -2U },
{ X86::ZMM26, -2U },
{ X86::ZMM27, -2U },
{ X86::ZMM28, -2U },
{ X86::ZMM29, -2U },
{ X86::ZMM30, -2U },
{ X86::ZMM31, -2U },
};
extern const unsigned X86DwarfFlavour2L2DwarfSize = std::size(X86DwarfFlavour2L2Dwarf);
extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour0L2Dwarf[] = {
{ X86::EAX, -2U },
{ X86::EBP, -2U },
{ X86::EBX, -2U },
{ X86::ECX, -2U },
{ X86::EDI, -2U },
{ X86::EDX, -2U },
{ X86::EFLAGS, 49U },
{ X86::EIP, -2U },
{ X86::ESI, -2U },
{ X86::ESP, -2U },
{ X86::FS_BASE, 58U },
{ X86::GS_BASE, 59U },
{ X86::RAX, 0U },
{ X86::RBP, 6U },
{ X86::RBX, 3U },
{ X86::RCX, 2U },
{ X86::RDI, 5U },
{ X86::RDX, 1U },
{ X86::RFLAGS, 49U },
{ X86::RIP, 16U },
{ X86::RSI, 4U },
{ X86::RSP, 7U },
{ X86::_EFLAGS, 49U },
{ X86::K0, 118U },
{ X86::K1, 119U },
{ X86::K2, 120U },
{ X86::K3, 121U },
{ X86::K4, 122U },
{ X86::K5, 123U },
{ X86::K6, 124U },
{ X86::K7, 125U },
{ X86::MM0, 41U },
{ X86::MM1, 42U },
{ X86::MM2, 43U },
{ X86::MM3, 44U },
{ X86::MM4, 45U },
{ X86::MM5, 46U },
{ X86::MM6, 47U },
{ X86::MM7, 48U },
{ X86::R8, 8U },
{ X86::R9, 9U },
{ X86::R10, 10U },
{ X86::R11, 11U },
{ X86::R12, 12U },
{ X86::R13, 13U },
{ X86::R14, 14U },
{ X86::R15, 15U },
{ X86::ST0, 33U },
{ X86::ST1, 34U },
{ X86::ST2, 35U },
{ X86::ST3, 36U },
{ X86::ST4, 37U },
{ X86::ST5, 38U },
{ X86::ST6, 39U },
{ X86::ST7, 40U },
{ X86::XMM0, 17U },
{ X86::XMM1, 18U },
{ X86::XMM2, 19U },
{ X86::XMM3, 20U },
{ X86::XMM4, 21U },
{ X86::XMM5, 22U },
{ X86::XMM6, 23U },
{ X86::XMM7, 24U },
{ X86::XMM8, 25U },
{ X86::XMM9, 26U },
{ X86::XMM10, 27U },
{ X86::XMM11, 28U },
{ X86::XMM12, 29U },
{ X86::XMM13, 30U },
{ X86::XMM14, 31U },
{ X86::XMM15, 32U },
{ X86::XMM16, 67U },
{ X86::XMM17, 68U },
{ X86::XMM18, 69U },
{ X86::XMM19, 70U },
{ X86::XMM20, 71U },
{ X86::XMM21, 72U },
{ X86::XMM22, 73U },
{ X86::XMM23, 74U },
{ X86::XMM24, 75U },
{ X86::XMM25, 76U },
{ X86::XMM26, 77U },
{ X86::XMM27, 78U },
{ X86::XMM28, 79U },
{ X86::XMM29, 80U },
{ X86::XMM30, 81U },
{ X86::XMM31, 82U },
{ X86::YMM0, 17U },
{ X86::YMM1, 18U },
{ X86::YMM2, 19U },
{ X86::YMM3, 20U },
{ X86::YMM4, 21U },
{ X86::YMM5, 22U },
{ X86::YMM6, 23U },
{ X86::YMM7, 24U },
{ X86::YMM8, 25U },
{ X86::YMM9, 26U },
{ X86::YMM10, 27U },
{ X86::YMM11, 28U },
{ X86::YMM12, 29U },
{ X86::YMM13, 30U },
{ X86::YMM14, 31U },
{ X86::YMM15, 32U },
{ X86::YMM16, 67U },
{ X86::YMM17, 68U },
{ X86::YMM18, 69U },
{ X86::YMM19, 70U },
{ X86::YMM20, 71U },
{ X86::YMM21, 72U },
{ X86::YMM22, 73U },
{ X86::YMM23, 74U },
{ X86::YMM24, 75U },
{ X86::YMM25, 76U },
{ X86::YMM26, 77U },
{ X86::YMM27, 78U },
{ X86::YMM28, 79U },
{ X86::YMM29, 80U },
{ X86::YMM30, 81U },
{ X86::YMM31, 82U },
{ X86::ZMM0, 17U },
{ X86::ZMM1, 18U },
{ X86::ZMM2, 19U },
{ X86::ZMM3, 20U },
{ X86::ZMM4, 21U },
{ X86::ZMM5, 22U },
{ X86::ZMM6, 23U },
{ X86::ZMM7, 24U },
{ X86::ZMM8, 25U },
{ X86::ZMM9, 26U },
{ X86::ZMM10, 27U },
{ X86::ZMM11, 28U },
{ X86::ZMM12, 29U },
{ X86::ZMM13, 30U },
{ X86::ZMM14, 31U },
{ X86::ZMM15, 32U },
{ X86::ZMM16, 67U },
{ X86::ZMM17, 68U },
{ X86::ZMM18, 69U },
{ X86::ZMM19, 70U },
{ X86::ZMM20, 71U },
{ X86::ZMM21, 72U },
{ X86::ZMM22, 73U },
{ X86::ZMM23, 74U },
{ X86::ZMM24, 75U },
{ X86::ZMM25, 76U },
{ X86::ZMM26, 77U },
{ X86::ZMM27, 78U },
{ X86::ZMM28, 79U },
{ X86::ZMM29, 80U },
{ X86::ZMM30, 81U },
{ X86::ZMM31, 82U },
};
extern const unsigned X86EHFlavour0L2DwarfSize = std::size(X86EHFlavour0L2Dwarf);
extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour1L2Dwarf[] = {
{ X86::EAX, 0U },
{ X86::EBP, 4U },
{ X86::EBX, 3U },
{ X86::ECX, 1U },
{ X86::EDI, 7U },
{ X86::EDX, 2U },
{ X86::EFLAGS, 9U },
{ X86::EIP, 8U },
{ X86::ESI, 6U },
{ X86::ESP, 5U },
{ X86::FS_BASE, -2U },
{ X86::GS_BASE, -2U },
{ X86::RAX, -2U },
{ X86::RBP, -2U },
{ X86::RBX, -2U },
{ X86::RCX, -2U },
{ X86::RDI, -2U },
{ X86::RDX, -2U },
{ X86::RFLAGS, -2U },
{ X86::RIP, -2U },
{ X86::RSI, -2U },
{ X86::RSP, -2U },
{ X86::_EFLAGS, 9U },
{ X86::K0, 93U },
{ X86::K1, 94U },
{ X86::K2, 95U },
{ X86::K3, 96U },
{ X86::K4, 97U },
{ X86::K5, 98U },
{ X86::K6, 99U },
{ X86::K7, 100U },
{ X86::MM0, 29U },
{ X86::MM1, 30U },
{ X86::MM2, 31U },
{ X86::MM3, 32U },
{ X86::MM4, 33U },
{ X86::MM5, 34U },
{ X86::MM6, 35U },
{ X86::MM7, 36U },
{ X86::R8, -2U },
{ X86::R9, -2U },
{ X86::R10, -2U },
{ X86::R11, -2U },
{ X86::R12, -2U },
{ X86::R13, -2U },
{ X86::R14, -2U },
{ X86::R15, -2U },
{ X86::ST0, 12U },
{ X86::ST1, 13U },
{ X86::ST2, 14U },
{ X86::ST3, 15U },
{ X86::ST4, 16U },
{ X86::ST5, 17U },
{ X86::ST6, 18U },
{ X86::ST7, 19U },
{ X86::XMM0, 21U },
{ X86::XMM1, 22U },
{ X86::XMM2, 23U },
{ X86::XMM3, 24U },
{ X86::XMM4, 25U },
{ X86::XMM5, 26U },
{ X86::XMM6, 27U },
{ X86::XMM7, 28U },
{ X86::XMM8, -2U },
{ X86::XMM9, -2U },
{ X86::XMM10, -2U },
{ X86::XMM11, -2U },
{ X86::XMM12, -2U },
{ X86::XMM13, -2U },
{ X86::XMM14, -2U },
{ X86::XMM15, -2U },
{ X86::XMM16, -2U },
{ X86::XMM17, -2U },
{ X86::XMM18, -2U },
{ X86::XMM19, -2U },
{ X86::XMM20, -2U },
{ X86::XMM21, -2U },
{ X86::XMM22, -2U },
{ X86::XMM23, -2U },
{ X86::XMM24, -2U },
{ X86::XMM25, -2U },
{ X86::XMM26, -2U },
{ X86::XMM27, -2U },
{ X86::XMM28, -2U },
{ X86::XMM29, -2U },
{ X86::XMM30, -2U },
{ X86::XMM31, -2U },
{ X86::YMM0, 21U },
{ X86::YMM1, 22U },
{ X86::YMM2, 23U },
{ X86::YMM3, 24U },
{ X86::YMM4, 25U },
{ X86::YMM5, 26U },
{ X86::YMM6, 27U },
{ X86::YMM7, 28U },
{ X86::YMM8, -2U },
{ X86::YMM9, -2U },
{ X86::YMM10, -2U },
{ X86::YMM11, -2U },
{ X86::YMM12, -2U },
{ X86::YMM13, -2U },
{ X86::YMM14, -2U },
{ X86::YMM15, -2U },
{ X86::YMM16, -2U },
{ X86::YMM17, -2U },
{ X86::YMM18, -2U },
{ X86::YMM19, -2U },
{ X86::YMM20, -2U },
{ X86::YMM21, -2U },
{ X86::YMM22, -2U },
{ X86::YMM23, -2U },
{ X86::YMM24, -2U },
{ X86::YMM25, -2U },
{ X86::YMM26, -2U },
{ X86::YMM27, -2U },
{ X86::YMM28, -2U },
{ X86::YMM29, -2U },
{ X86::YMM30, -2U },
{ X86::YMM31, -2U },
{ X86::ZMM0, 21U },
{ X86::ZMM1, 22U },
{ X86::ZMM2, 23U },
{ X86::ZMM3, 24U },
{ X86::ZMM4, 25U },
{ X86::ZMM5, 26U },
{ X86::ZMM6, 27U },
{ X86::ZMM7, 28U },
{ X86::ZMM8, -2U },
{ X86::ZMM9, -2U },
{ X86::ZMM10, -2U },
{ X86::ZMM11, -2U },
{ X86::ZMM12, -2U },
{ X86::ZMM13, -2U },
{ X86::ZMM14, -2U },
{ X86::ZMM15, -2U },
{ X86::ZMM16, -2U },
{ X86::ZMM17, -2U },
{ X86::ZMM18, -2U },
{ X86::ZMM19, -2U },
{ X86::ZMM20, -2U },
{ X86::ZMM21, -2U },
{ X86::ZMM22, -2U },
{ X86::ZMM23, -2U },
{ X86::ZMM24, -2U },
{ X86::ZMM25, -2U },
{ X86::ZMM26, -2U },
{ X86::ZMM27, -2U },
{ X86::ZMM28, -2U },
{ X86::ZMM29, -2U },
{ X86::ZMM30, -2U },
{ X86::ZMM31, -2U },
};
extern const unsigned X86EHFlavour1L2DwarfSize = std::size(X86EHFlavour1L2Dwarf);
extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour2L2Dwarf[] = {
{ X86::EAX, 0U },
{ X86::EBP, 5U },
{ X86::EBX, 3U },
{ X86::ECX, 1U },
{ X86::EDI, 7U },
{ X86::EDX, 2U },
{ X86::EFLAGS, 9U },
{ X86::EIP, 8U },
{ X86::ESI, 6U },
{ X86::ESP, 4U },
{ X86::FS_BASE, -2U },
{ X86::GS_BASE, -2U },
{ X86::RAX, -2U },
{ X86::RBP, -2U },
{ X86::RBX, -2U },
{ X86::RCX, -2U },
{ X86::RDI, -2U },
{ X86::RDX, -2U },
{ X86::RFLAGS, -2U },
{ X86::RIP, -2U },
{ X86::RSI, -2U },
{ X86::RSP, -2U },
{ X86::_EFLAGS, 9U },
{ X86::K0, 93U },
{ X86::K1, 94U },
{ X86::K2, 95U },
{ X86::K3, 96U },
{ X86::K4, 97U },
{ X86::K5, 98U },
{ X86::K6, 99U },
{ X86::K7, 100U },
{ X86::MM0, 29U },
{ X86::MM1, 30U },
{ X86::MM2, 31U },
{ X86::MM3, 32U },
{ X86::MM4, 33U },
{ X86::MM5, 34U },
{ X86::MM6, 35U },
{ X86::MM7, 36U },
{ X86::R8, -2U },
{ X86::R9, -2U },
{ X86::R10, -2U },
{ X86::R11, -2U },
{ X86::R12, -2U },
{ X86::R13, -2U },
{ X86::R14, -2U },
{ X86::R15, -2U },
{ X86::ST0, 11U },
{ X86::ST1, 12U },
{ X86::ST2, 13U },
{ X86::ST3, 14U },
{ X86::ST4, 15U },
{ X86::ST5, 16U },
{ X86::ST6, 17U },
{ X86::ST7, 18U },
{ X86::XMM0, 21U },
{ X86::XMM1, 22U },
{ X86::XMM2, 23U },
{ X86::XMM3, 24U },
{ X86::XMM4, 25U },
{ X86::XMM5, 26U },
{ X86::XMM6, 27U },
{ X86::XMM7, 28U },
{ X86::XMM8, -2U },
{ X86::XMM9, -2U },
{ X86::XMM10, -2U },
{ X86::XMM11, -2U },
{ X86::XMM12, -2U },
{ X86::XMM13, -2U },
{ X86::XMM14, -2U },
{ X86::XMM15, -2U },
{ X86::XMM16, -2U },
{ X86::XMM17, -2U },
{ X86::XMM18, -2U },
{ X86::XMM19, -2U },
{ X86::XMM20, -2U },
{ X86::XMM21, -2U },
{ X86::XMM22, -2U },
{ X86::XMM23, -2U },
{ X86::XMM24, -2U },
{ X86::XMM25, -2U },
{ X86::XMM26, -2U },
{ X86::XMM27, -2U },
{ X86::XMM28, -2U },
{ X86::XMM29, -2U },
{ X86::XMM30, -2U },
{ X86::XMM31, -2U },
{ X86::YMM0, 21U },
{ X86::YMM1, 22U },
{ X86::YMM2, 23U },
{ X86::YMM3, 24U },
{ X86::YMM4, 25U },
{ X86::YMM5, 26U },
{ X86::YMM6, 27U },
{ X86::YMM7, 28U },
{ X86::YMM8, -2U },
{ X86::YMM9, -2U },
{ X86::YMM10, -2U },
{ X86::YMM11, -2U },
{ X86::YMM12, -2U },
{ X86::YMM13, -2U },
{ X86::YMM14, -2U },
{ X86::YMM15, -2U },
{ X86::YMM16, -2U },
{ X86::YMM17, -2U },
{ X86::YMM18, -2U },
{ X86::YMM19, -2U },
{ X86::YMM20, -2U },
{ X86::YMM21, -2U },
{ X86::YMM22, -2U },
{ X86::YMM23, -2U },
{ X86::YMM24, -2U },
{ X86::YMM25, -2U },
{ X86::YMM26, -2U },
{ X86::YMM27, -2U },
{ X86::YMM28, -2U },
{ X86::YMM29, -2U },
{ X86::YMM30, -2U },
{ X86::YMM31, -2U },
{ X86::ZMM0, 21U },
{ X86::ZMM1, 22U },
{ X86::ZMM2, 23U },
{ X86::ZMM3, 24U },
{ X86::ZMM4, 25U },
{ X86::ZMM5, 26U },
{ X86::ZMM6, 27U },
{ X86::ZMM7, 28U },
{ X86::ZMM8, -2U },
{ X86::ZMM9, -2U },
{ X86::ZMM10, -2U },
{ X86::ZMM11, -2U },
{ X86::ZMM12, -2U },
{ X86::ZMM13, -2U },
{ X86::ZMM14, -2U },
{ X86::ZMM15, -2U },
{ X86::ZMM16, -2U },
{ X86::ZMM17, -2U },
{ X86::ZMM18, -2U },
{ X86::ZMM19, -2U },
{ X86::ZMM20, -2U },
{ X86::ZMM21, -2U },
{ X86::ZMM22, -2U },
{ X86::ZMM23, -2U },
{ X86::ZMM24, -2U },
{ X86::ZMM25, -2U },
{ X86::ZMM26, -2U },
{ X86::ZMM27, -2U },
{ X86::ZMM28, -2U },
{ X86::ZMM29, -2U },
{ X86::ZMM30, -2U },
{ X86::ZMM31, -2U },
};
extern const unsigned X86EHFlavour2L2DwarfSize = std::size(X86EHFlavour2L2Dwarf);
extern const uint16_t X86RegEncodingTable[] = {
0,
4,
0,
0,
7,
3,
5,
65535,
5,
3,
5,
1,
1,
1,
0,
6,
7,
65535,
7,
2,
3,
2,
0,
5,
3,
1,
7,
2,
0,
0,
4,
0,
6,
4,
0,
0,
4,
0,
5,
0,
65535,
65535,
65535,
65535,
65535,
65535,
65535,
65535,
65535,
0,
0,
0,
5,
3,
1,
7,
2,
0,
0,
4,
6,
4,
6,
65535,
6,
4,
65535,
4,
2,
0,
0,
0,
0,
1,
2,
3,
4,
5,
6,
7,
8,
9,
10,
11,
12,
13,
14,
15,
0,
1,
2,
3,
4,
5,
6,
7,
8,
9,
10,
11,
12,
13,
14,
15,
0,
0,
0,
0,
0,
0,
0,
0,
0,
1,
2,
3,
4,
5,
6,
7,
0,
1,
2,
3,
4,
5,
6,
7,
8,
9,
10,
11,
12,
13,
14,
15,
0,
1,
2,
3,
4,
5,
6,
7,
0,
1,
2,
3,
4,
5,
6,
7,
0,
1,
2,
3,
4,
5,
6,
7,
8,
9,
10,
11,
12,
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29,
30,
31,
0,
1,
2,
3,
4,
5,
6,
7,
8,
9,
10,
11,
12,
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29,
30,
31,
0,
1,
2,
3,
4,
5,
6,
7,
8,
9,
10,
11,
12,
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29,
30,
31,
8,
9,
10,
11,
12,
13,
14,
15,
65535,
65535,
65535,
65535,
65535,
65535,
65535,
65535,
8,
9,
10,
11,
12,
13,
14,
15,
8,
9,
10,
11,
12,
13,
14,
15,
65535,
65535,
65535,
65535,
65535,
65535,
65535,
65535,
0,
2,
4,
6,
};
static inline void InitX86MCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
RI->InitMCRegisterInfo(X86RegDesc, 292, RA, PC, X86MCRegisterClasses, 123, X86RegUnitRoots, 173, X86RegDiffLists, X86LaneMaskLists, X86RegStrings, X86RegClassStrings, X86SubRegIdxLists, 11,
X86SubRegIdxRanges, X86RegEncodingTable);
switch (DwarfFlavour) {
default:
llvm_unreachable("Unknown DWARF flavour");
case 0:
RI->mapDwarfRegsToLLVMRegs(X86DwarfFlavour0Dwarf2L, X86DwarfFlavour0Dwarf2LSize, false);
break;
case 1:
RI->mapDwarfRegsToLLVMRegs(X86DwarfFlavour1Dwarf2L, X86DwarfFlavour1Dwarf2LSize, false);
break;
case 2:
RI->mapDwarfRegsToLLVMRegs(X86DwarfFlavour2Dwarf2L, X86DwarfFlavour2Dwarf2LSize, false);
break;
}
switch (EHFlavour) {
default:
llvm_unreachable("Unknown DWARF flavour");
case 0:
RI->mapDwarfRegsToLLVMRegs(X86EHFlavour0Dwarf2L, X86EHFlavour0Dwarf2LSize, true);
break;
case 1:
RI->mapDwarfRegsToLLVMRegs(X86EHFlavour1Dwarf2L, X86EHFlavour1Dwarf2LSize, true);
break;
case 2:
RI->mapDwarfRegsToLLVMRegs(X86EHFlavour2Dwarf2L, X86EHFlavour2Dwarf2LSize, true);
break;
}
switch (DwarfFlavour) {
default:
llvm_unreachable("Unknown DWARF flavour");
case 0:
RI->mapLLVMRegsToDwarfRegs(X86DwarfFlavour0L2Dwarf, X86DwarfFlavour0L2DwarfSize, false);
break;
case 1:
RI->mapLLVMRegsToDwarfRegs(X86DwarfFlavour1L2Dwarf, X86DwarfFlavour1L2DwarfSize, false);
break;
case 2:
RI->mapLLVMRegsToDwarfRegs(X86DwarfFlavour2L2Dwarf, X86DwarfFlavour2L2DwarfSize, false);
break;
}
switch (EHFlavour) {
default:
llvm_unreachable("Unknown DWARF flavour");
case 0:
RI->mapLLVMRegsToDwarfRegs(X86EHFlavour0L2Dwarf, X86EHFlavour0L2DwarfSize, true);
break;
case 1:
RI->mapLLVMRegsToDwarfRegs(X86EHFlavour1L2Dwarf, X86EHFlavour1L2DwarfSize, true);
break;
case 2:
RI->mapLLVMRegsToDwarfRegs(X86EHFlavour2L2Dwarf, X86EHFlavour2L2DwarfSize, true);
break;
}
}
} // end namespace llvm
#endif // GET_REGINFO_MC_DESC
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|* *|
|* Register Information Header Fragment *|
|* *|
|* Automatically generated file, do not edit! *|
|* *|
\*===----------------------------------------------------------------------===*/
#ifdef GET_REGINFO_HEADER
#undef GET_REGINFO_HEADER
#include "llvm/CodeGen/TargetRegisterInfo.h"
namespace llvm {
class X86FrameLowering;
struct X86GenRegisterInfo : public TargetRegisterInfo {
explicit X86GenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0,
unsigned PC = 0, unsigned HwMode = 0);
unsigned composeSubRegIndicesImpl(unsigned, unsigned) const override;
LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass *, unsigned) const override;
const TargetRegisterClass *getSubRegisterClass(const TargetRegisterClass *, unsigned) const override;
const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
unsigned getRegUnitWeight(unsigned RegUnit) const override;
unsigned getNumRegPressureSets() const override;
const char *getRegPressureSetName(unsigned Idx) const override;
unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override;
const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
const int *getRegUnitPressureSets(unsigned RegUnit) const override;
ArrayRef<const char *> getRegMaskNames() const override;
ArrayRef<const uint32_t *> getRegMasks() const override;
bool isGeneralPurposeRegister(const MachineFunction &, MCRegister) const override;
bool isFixedRegister(const MachineFunction &, MCRegister) const override;
bool isArgumentRegister(const MachineFunction &, MCRegister) const override;
bool isConstantPhysReg(MCRegister PhysReg) const override final;
/// Devirtualized TargetFrameLowering.
static const X86FrameLowering *getFrameLowering(
const MachineFunction &MF);
};
namespace X86 { // Register classes
extern const TargetRegisterClass GR8RegClass;
extern const TargetRegisterClass GRH8RegClass;
extern const TargetRegisterClass GR8_NOREXRegClass;
extern const TargetRegisterClass GR8_ABCD_HRegClass;
extern const TargetRegisterClass GR8_ABCD_LRegClass;
extern const TargetRegisterClass GRH16RegClass;
extern const TargetRegisterClass GR16RegClass;
extern const TargetRegisterClass GR16_NOREXRegClass;
extern const TargetRegisterClass VK1RegClass;
extern const TargetRegisterClass VK16RegClass;
extern const TargetRegisterClass VK2RegClass;
extern const TargetRegisterClass VK4RegClass;
extern const TargetRegisterClass VK8RegClass;
extern const TargetRegisterClass VK16WMRegClass;
extern const TargetRegisterClass VK1WMRegClass;
extern const TargetRegisterClass VK2WMRegClass;
extern const TargetRegisterClass VK4WMRegClass;
extern const TargetRegisterClass VK8WMRegClass;
extern const TargetRegisterClass SEGMENT_REGRegClass;
extern const TargetRegisterClass GR16_ABCDRegClass;
extern const TargetRegisterClass FPCCRRegClass;
extern const TargetRegisterClass FR16XRegClass;
extern const TargetRegisterClass FR16RegClass;
extern const TargetRegisterClass VK16PAIRRegClass;
extern const TargetRegisterClass VK1PAIRRegClass;
extern const TargetRegisterClass VK2PAIRRegClass;
extern const TargetRegisterClass VK4PAIRRegClass;
extern const TargetRegisterClass VK8PAIRRegClass;
extern const TargetRegisterClass VK16PAIR_with_sub_mask_0_in_VK16WMRegClass;
extern const TargetRegisterClass FR32XRegClass;
extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBPRegClass;
extern const TargetRegisterClass LOW32_ADDR_ACCESSRegClass;
extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass;
extern const TargetRegisterClass DEBUG_REGRegClass;
extern const TargetRegisterClass FR32RegClass;
extern const TargetRegisterClass GR32RegClass;
extern const TargetRegisterClass GR32_NOSPRegClass;
extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass;
extern const TargetRegisterClass GR32_NOREXRegClass;
extern const TargetRegisterClass VK32RegClass;
extern const TargetRegisterClass GR32_NOREX_NOSPRegClass;
extern const TargetRegisterClass RFP32RegClass;
extern const TargetRegisterClass VK32WMRegClass;
extern const TargetRegisterClass GR32_ABCDRegClass;
extern const TargetRegisterClass GR32_TCRegClass;
extern const TargetRegisterClass GR32_ABCD_and_GR32_TCRegClass;
extern const TargetRegisterClass GR32_ADRegClass;
extern const TargetRegisterClass GR32_BPSPRegClass;
extern const TargetRegisterClass GR32_BSIRegClass;
extern const TargetRegisterClass GR32_CBRegClass;
extern const TargetRegisterClass GR32_DCRegClass;
extern const TargetRegisterClass GR32_DIBPRegClass;
extern const TargetRegisterClass GR32_SIDIRegClass;
extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClass;
extern const TargetRegisterClass CCRRegClass;
extern const TargetRegisterClass DFCCRRegClass;
extern const TargetRegisterClass GR32_ABCD_and_GR32_BSIRegClass;
extern const TargetRegisterClass GR32_AD_and_GR32_DCRegClass;
extern const TargetRegisterClass GR32_BPSP_and_GR32_DIBPRegClass;
extern const TargetRegisterClass GR32_BPSP_and_GR32_TCRegClass;
extern const TargetRegisterClass GR32_BSI_and_GR32_SIDIRegClass;
extern const TargetRegisterClass GR32_CB_and_GR32_DCRegClass;
extern const TargetRegisterClass GR32_DIBP_and_GR32_SIDIRegClass;
extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitRegClass;
extern const TargetRegisterClass LOW32_ADDR_ACCESS_with_sub_32bitRegClass;
extern const TargetRegisterClass RFP64RegClass;
extern const TargetRegisterClass FR64XRegClass;
extern const TargetRegisterClass GR64RegClass;
extern const TargetRegisterClass CONTROL_REGRegClass;
extern const TargetRegisterClass FR64RegClass;
extern const TargetRegisterClass GR64_with_sub_8bitRegClass;
extern const TargetRegisterClass GR64_NOSPRegClass;
extern const TargetRegisterClass GR64PLTSafeRegClass;
extern const TargetRegisterClass GR64_TCRegClass;
extern const TargetRegisterClass GR64_NOREXRegClass;
extern const TargetRegisterClass GR64_TCW64RegClass;
extern const TargetRegisterClass GR64_TC_with_sub_8bitRegClass;
extern const TargetRegisterClass GR64_NOSP_and_GR64_TCRegClass;
extern const TargetRegisterClass GR64_TCW64_with_sub_8bitRegClass;
extern const TargetRegisterClass GR64_TC_and_GR64_TCW64RegClass;
extern const TargetRegisterClass GR64_with_sub_16bit_in_GR16_NOREXRegClass;
extern const TargetRegisterClass VK64RegClass;
extern const TargetRegisterClass VR64RegClass;
extern const TargetRegisterClass GR64PLTSafe_and_GR64_TCRegClass;
extern const TargetRegisterClass GR64_NOREX_NOSPRegClass;
extern const TargetRegisterClass GR64_NOREX_and_GR64_TCRegClass;
extern const TargetRegisterClass GR64_NOSP_and_GR64_TCW64RegClass;
extern const TargetRegisterClass GR64_TCW64_and_GR64_TC_with_sub_8bitRegClass;
extern const TargetRegisterClass VK64WMRegClass;
extern const TargetRegisterClass GR64_TC_and_GR64_NOSP_and_GR64_TCW64RegClass;
extern const TargetRegisterClass GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClass;
extern const TargetRegisterClass GR64PLTSafe_and_GR64_TCW64RegClass;
extern const TargetRegisterClass GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClass;
extern const TargetRegisterClass GR64_NOREX_and_GR64_TCW64RegClass;
extern const TargetRegisterClass GR64_ABCDRegClass;
extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_TCRegClass;
extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClass;
extern const TargetRegisterClass GR64_ADRegClass;
extern const TargetRegisterClass GR64_and_LOW32_ADDR_ACCESS_RBPRegClass;
extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BPSPRegClass;
extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BSIRegClass;
extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_CBRegClass;
extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_DCRegClass;
extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_DIBPRegClass;
extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_SIDIRegClass;
extern const TargetRegisterClass GR64_and_LOW32_ADDR_ACCESSRegClass;
extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIRegClass;
extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_AD_and_GR32_DCRegClass;
extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPRegClass;
extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCRegClass;
extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIRegClass;
extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_CB_and_GR32_DCRegClass;
extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIRegClass;
extern const TargetRegisterClass RSTRegClass;
extern const TargetRegisterClass RFP80RegClass;
extern const TargetRegisterClass RFP80_7RegClass;
extern const TargetRegisterClass VR128XRegClass;
extern const TargetRegisterClass VR128RegClass;
extern const TargetRegisterClass VR256XRegClass;
extern const TargetRegisterClass VR256RegClass;
extern const TargetRegisterClass VR512RegClass;
extern const TargetRegisterClass VR512_0_15RegClass;
extern const TargetRegisterClass TILERegClass;
} // end namespace X86
} // end namespace llvm
#endif // GET_REGINFO_HEADER
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|* *|
|* Target Register and Register Classes Information *|
|* *|
|* Automatically generated file, do not edit! *|
|* *|
\*===----------------------------------------------------------------------===*/
#ifdef GET_REGINFO_TARGET_DESC
#undef GET_REGINFO_TARGET_DESC
namespace llvm {
extern const MCRegisterClass X86MCRegisterClasses[];
static const MVT::SimpleValueType VTLists[] = {
/* 0 */ MVT::i8, MVT::Other,
/* 2 */ MVT::i16, MVT::Other,
/* 4 */ MVT::i32, MVT::Other,
/* 6 */ MVT::i64, MVT::Other,
/* 8 */ MVT::f16, MVT::Other,
/* 10 */ MVT::f80, MVT::f64, MVT::f32, MVT::Other,
/* 14 */ MVT::f64, MVT::Other,
/* 16 */ MVT::f80, MVT::Other,
/* 18 */ MVT::v4f32, MVT::v2f64, MVT::v8f16, MVT::v8bf16, MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64, MVT::f128, MVT::Other,
/* 28 */ MVT::v1i1, MVT::Other,
/* 30 */ MVT::v2i1, MVT::Other,
/* 32 */ MVT::v4i1, MVT::Other,
/* 34 */ MVT::v8i1, MVT::Other,
/* 36 */ MVT::v16i1, MVT::Other,
/* 38 */ MVT::v32i1, MVT::Other,
/* 40 */ MVT::v64i1, MVT::Other,
/* 42 */ MVT::v8f32, MVT::v4f64, MVT::v16f16, MVT::v16bf16, MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64, MVT::Other,
/* 51 */ MVT::v16f32, MVT::v8f64, MVT::v32f16, MVT::v32bf16, MVT::v64i8, MVT::v32i16, MVT::v16i32, MVT::v8i64, MVT::Other,
/* 60 */ MVT::v16f32, MVT::v8f64, MVT::v64i8, MVT::v32i16, MVT::v16i32, MVT::v8i64, MVT::Other,
/* 67 */ MVT::x86mmx, MVT::Other,
/* 69 */ MVT::Untyped, MVT::Other,
/* 71 */ MVT::x86amx, MVT::Other,
};
static const char *SubRegIndexNameTable[] = { "sub_8bit", "sub_8bit_hi", "sub_8bit_hi_phony", "sub_16bit", "sub_16bit_hi", "sub_32bit", "sub_mask_0", "sub_mask_1", "sub_xmm", "sub_ymm", "" };
static const LaneBitmask SubRegIndexLaneMaskTable[] = {
LaneBitmask::getAll(),
LaneBitmask(0x0000000000000001), // sub_8bit
LaneBitmask(0x0000000000000002), // sub_8bit_hi
LaneBitmask(0x0000000000000004), // sub_8bit_hi_phony
LaneBitmask(0x0000000000000007), // sub_16bit
LaneBitmask(0x0000000000000008), // sub_16bit_hi
LaneBitmask(0x000000000000000F), // sub_32bit
LaneBitmask(0x0000000000000010), // sub_mask_0
LaneBitmask(0x0000000000000020), // sub_mask_1
LaneBitmask(0x0000000000000040), // sub_xmm
LaneBitmask(0x0000000000000040), // sub_ymm
};
static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
// Mode = 0 (Default)
{ 8, 8, 8, VTLists+0 }, // GR8
{ 8, 8, 8, VTLists+0 }, // GRH8
{ 8, 8, 8, VTLists+0 }, // GR8_NOREX
{ 8, 8, 8, VTLists+0 }, // GR8_ABCD_H
{ 8, 8, 8, VTLists+0 }, // GR8_ABCD_L
{ 16, 16, 16, VTLists+2 }, // GRH16
{ 16, 16, 16, VTLists+2 }, // GR16
{ 16, 16, 16, VTLists+2 }, // GR16_NOREX
{ 16, 16, 16, VTLists+28 }, // VK1
{ 16, 16, 16, VTLists+36 }, // VK16
{ 16, 16, 16, VTLists+30 }, // VK2
{ 16, 16, 16, VTLists+32 }, // VK4
{ 16, 16, 16, VTLists+34 }, // VK8
{ 16, 16, 16, VTLists+36 }, // VK16WM
{ 16, 16, 16, VTLists+28 }, // VK1WM
{ 16, 16, 16, VTLists+30 }, // VK2WM
{ 16, 16, 16, VTLists+32 }, // VK4WM
{ 16, 16, 16, VTLists+34 }, // VK8WM
{ 16, 16, 16, VTLists+2 }, // SEGMENT_REG
{ 16, 16, 16, VTLists+2 }, // GR16_ABCD
{ 16, 16, 16, VTLists+2 }, // FPCCR
{ 32, 32, 16, VTLists+8 }, // FR16X
{ 32, 32, 16, VTLists+8 }, // FR16
{ 32, 32, 16, VTLists+69 }, // VK16PAIR
{ 32, 32, 16, VTLists+69 }, // VK1PAIR
{ 32, 32, 16, VTLists+69 }, // VK2PAIR
{ 32, 32, 16, VTLists+69 }, // VK4PAIR
{ 32, 32, 16, VTLists+69 }, // VK8PAIR
{ 32, 32, 16, VTLists+69 }, // VK16PAIR_with_sub_mask_0_in_VK16WM
{ 32, 32, 32, VTLists+12 }, // FR32X
{ 32, 32, 32, VTLists+4 }, // LOW32_ADDR_ACCESS_RBP
{ 32, 32, 32, VTLists+4 }, // LOW32_ADDR_ACCESS
{ 32, 32, 32, VTLists+4 }, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit
{ 32, 32, 32, VTLists+4 }, // DEBUG_REG
{ 32, 32, 32, VTLists+12 }, // FR32
{ 32, 32, 32, VTLists+4 }, // GR32
{ 32, 32, 32, VTLists+4 }, // GR32_NOSP
{ 32, 32, 32, VTLists+4 }, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX
{ 32, 32, 32, VTLists+4 }, // GR32_NOREX
{ 32, 32, 32, VTLists+38 }, // VK32
{ 32, 32, 32, VTLists+4 }, // GR32_NOREX_NOSP
{ 32, 32, 32, VTLists+12 }, // RFP32
{ 32, 32, 32, VTLists+38 }, // VK32WM
{ 32, 32, 32, VTLists+4 }, // GR32_ABCD
{ 32, 32, 32, VTLists+4 }, // GR32_TC
{ 32, 32, 32, VTLists+4 }, // GR32_ABCD_and_GR32_TC
{ 32, 32, 32, VTLists+4 }, // GR32_AD
{ 32, 32, 32, VTLists+4 }, // GR32_BPSP
{ 32, 32, 32, VTLists+4 }, // GR32_BSI
{ 32, 32, 32, VTLists+4 }, // GR32_CB
{ 32, 32, 32, VTLists+4 }, // GR32_DC
{ 32, 32, 32, VTLists+4 }, // GR32_DIBP
{ 32, 32, 32, VTLists+4 }, // GR32_SIDI
{ 32, 32, 32, VTLists+4 }, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit
{ 32, 32, 32, VTLists+4 }, // CCR
{ 32, 32, 32, VTLists+4 }, // DFCCR
{ 32, 32, 32, VTLists+4 }, // GR32_ABCD_and_GR32_BSI
{ 32, 32, 32, VTLists+4 }, // GR32_AD_and_GR32_DC
{ 32, 32, 32, VTLists+4 }, // GR32_BPSP_and_GR32_DIBP
{ 32, 32, 32, VTLists+4 }, // GR32_BPSP_and_GR32_TC
{ 32, 32, 32, VTLists+4 }, // GR32_BSI_and_GR32_SIDI
{ 32, 32, 32, VTLists+4 }, // GR32_CB_and_GR32_DC
{ 32, 32, 32, VTLists+4 }, // GR32_DIBP_and_GR32_SIDI
{ 32, 32, 32, VTLists+4 }, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
{ 32, 32, 32, VTLists+4 }, // LOW32_ADDR_ACCESS_with_sub_32bit
{ 64, 64, 32, VTLists+14 }, // RFP64
{ 64, 64, 64, VTLists+14 }, // FR64X
{ 64, 64, 64, VTLists+6 }, // GR64
{ 64, 64, 64, VTLists+6 }, // CONTROL_REG
{ 64, 64, 64, VTLists+14 }, // FR64
{ 64, 64, 64, VTLists+6 }, // GR64_with_sub_8bit
{ 64, 64, 64, VTLists+6 }, // GR64_NOSP
{ 64, 64, 64, VTLists+6 }, // GR64PLTSafe
{ 64, 64, 64, VTLists+6 }, // GR64_TC
{ 64, 64, 64, VTLists+6 }, // GR64_NOREX
{ 64, 64, 64, VTLists+6 }, // GR64_TCW64
{ 64, 64, 64, VTLists+6 }, // GR64_TC_with_sub_8bit
{ 64, 64, 64, VTLists+6 }, // GR64_NOSP_and_GR64_TC
{ 64, 64, 64, VTLists+6 }, // GR64_TCW64_with_sub_8bit
{ 64, 64, 64, VTLists+6 }, // GR64_TC_and_GR64_TCW64
{ 64, 64, 64, VTLists+6 }, // GR64_with_sub_16bit_in_GR16_NOREX
{ 64, 64, 64, VTLists+40 }, // VK64
{ 64, 64, 64, VTLists+67 }, // VR64
{ 64, 64, 64, VTLists+6 }, // GR64PLTSafe_and_GR64_TC
{ 64, 64, 64, VTLists+6 }, // GR64_NOREX_NOSP
{ 64, 64, 64, VTLists+6 }, // GR64_NOREX_and_GR64_TC
{ 64, 64, 64, VTLists+6 }, // GR64_NOSP_and_GR64_TCW64
{ 64, 64, 64, VTLists+6 }, // GR64_TCW64_and_GR64_TC_with_sub_8bit
{ 64, 64, 64, VTLists+40 }, // VK64WM
{ 64, 64, 64, VTLists+6 }, // GR64_TC_and_GR64_NOSP_and_GR64_TCW64
{ 64, 64, 64, VTLists+6 }, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX
{ 64, 64, 64, VTLists+6 }, // GR64PLTSafe_and_GR64_TCW64
{ 64, 64, 64, VTLists+6 }, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC
{ 64, 64, 64, VTLists+6 }, // GR64_NOREX_and_GR64_TCW64
{ 64, 64, 64, VTLists+6 }, // GR64_ABCD
{ 64, 64, 64, VTLists+6 }, // GR64_with_sub_32bit_in_GR32_TC
{ 64, 64, 64, VTLists+6 }, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
{ 64, 64, 64, VTLists+6 }, // GR64_AD
{ 64, 64, 64, VTLists+6 }, // GR64_and_LOW32_ADDR_ACCESS_RBP
{ 64, 64, 64, VTLists+6 }, // GR64_with_sub_32bit_in_GR32_BPSP
{ 64, 64, 64, VTLists+6 }, // GR64_with_sub_32bit_in_GR32_BSI
{ 64, 64, 64, VTLists+6 }, // GR64_with_sub_32bit_in_GR32_CB
{ 64, 64, 64, VTLists+6 }, // GR64_with_sub_32bit_in_GR32_DC
{ 64, 64, 64, VTLists+6 }, // GR64_with_sub_32bit_in_GR32_DIBP
{ 64, 64, 64, VTLists+6 }, // GR64_with_sub_32bit_in_GR32_SIDI
{ 64, 64, 64, VTLists+6 }, // GR64_and_LOW32_ADDR_ACCESS
{ 64, 64, 64, VTLists+6 }, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
{ 64, 64, 64, VTLists+6 }, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_DC
{ 64, 64, 64, VTLists+6 }, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
{ 64, 64, 64, VTLists+6 }, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC
{ 64, 64, 64, VTLists+6 }, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI
{ 64, 64, 64, VTLists+6 }, // GR64_with_sub_32bit_in_GR32_CB_and_GR32_DC
{ 64, 64, 64, VTLists+6 }, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI
{ 80, 80, 32, VTLists+10 }, // RST
{ 80, 80, 32, VTLists+16 }, // RFP80
{ 80, 80, 32, VTLists+16 }, // RFP80_7
{ 128, 128, 128, VTLists+18 }, // VR128X
{ 128, 128, 128, VTLists+18 }, // VR128
{ 256, 256, 256, VTLists+42 }, // VR256X
{ 256, 256, 256, VTLists+42 }, // VR256
{ 512, 512, 512, VTLists+51 }, // VR512
{ 512, 512, 512, VTLists+60 }, // VR512_0_15
{ 8192, 8192, 8192, VTLists+71 }, // TILE
};
static const TargetRegisterClass *const NullRegClasses[] = { nullptr };
static const uint32_t GR8SubClassMask[] = {
0x0000001d, 0x00000000, 0x00000000, 0x00000000,
0x000800c0, 0xff1ff979, 0xded971c0, 0x0001fdfb, // sub_8bit
0x00080000, 0x23066800, 0x40000000, 0x00008c63, // sub_8bit_hi
};
static const uint32_t GRH8SubClassMask[] = {
0x00000002, 0x00000000, 0x00000000, 0x00000000,
};
static const uint32_t GR8_NOREXSubClassMask[] = {
0x0000001c, 0x00000000, 0x00000000, 0x00000000,
0x00080000, 0x23066800, 0x40000000, 0x00008c63, // sub_8bit
0x00080000, 0x23066800, 0x40000000, 0x00008c63, // sub_8bit_hi
};
static const uint32_t GR8_ABCD_HSubClassMask[] = {
0x00000008, 0x00000000, 0x00000000, 0x00000000,
0x00080000, 0x23066800, 0x40000000, 0x00008c63, // sub_8bit_hi
};
static const uint32_t GR8_ABCD_LSubClassMask[] = {
0x00000010, 0x00000000, 0x00000000, 0x00000000,
0x00080000, 0x23066800, 0x40000000, 0x00008c63, // sub_8bit
};
static const uint32_t GRH16SubClassMask[] = {
0x00000020, 0x00000000, 0x00000000, 0x00000000,
};
static const uint32_t GR16SubClassMask[] = {
0x000800c0, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0xff1ff979, 0xded971c0, 0x0001fdfb, // sub_16bit
};
static const uint32_t GR16_NOREXSubClassMask[] = {
0x00080080, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0xff1ff960, 0xd4110000, 0x0001fdfb, // sub_16bit
};
static const uint32_t VK1SubClassMask[] = {
0x0003ff00, 0x00000480, 0x01020000, 0x00000000,
0x1f800000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
0x1f800000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
};
static const uint32_t VK16SubClassMask[] = {
0x0003ff00, 0x00000480, 0x01020000, 0x00000000,
0x1f800000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
0x1f800000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
};
static const uint32_t VK2SubClassMask[] = {
0x0003ff00, 0x00000480, 0x01020000, 0x00000000,
0x1f800000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
0x1f800000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
};
static const uint32_t VK4SubClassMask[] = {
0x0003ff00, 0x00000480, 0x01020000, 0x00000000,
0x1f800000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
0x1f800000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
};
static const uint32_t VK8SubClassMask[] = {
0x0003ff00, 0x00000480, 0x01020000, 0x00000000,
0x1f800000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
0x1f800000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
};
static const uint32_t VK16WMSubClassMask[] = {
0x0003e000, 0x00000400, 0x01000000, 0x00000000,
0x10000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
0x1f800000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
};
static const uint32_t VK1WMSubClassMask[] = {
0x0003e000, 0x00000400, 0x01000000, 0x00000000,
0x10000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
0x1f800000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
};
static const uint32_t VK2WMSubClassMask[] = {
0x0003e000, 0x00000400, 0x01000000, 0x00000000,
0x10000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
0x1f800000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
};
static const uint32_t VK4WMSubClassMask[] = {
0x0003e000, 0x00000400, 0x01000000, 0x00000000,
0x10000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
0x1f800000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
};
static const uint32_t VK8WMSubClassMask[] = {
0x0003e000, 0x00000400, 0x01000000, 0x00000000,
0x10000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
0x1f800000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
};
static const uint32_t SEGMENT_REGSubClassMask[] = {
0x00040000, 0x00000000, 0x00000000, 0x00000000,
};
static const uint32_t GR16_ABCDSubClassMask[] = {
0x00080000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x23066800, 0x40000000, 0x00008c63, // sub_16bit
};
static const uint32_t FPCCRSubClassMask[] = {
0x00100000, 0x00000000, 0x00000000, 0x00000000,
};
static const uint32_t FR16XSubClassMask[] = {
0x20600000, 0x00000004, 0x00000024, 0x00300000,
0x00000000, 0x00000000, 0x00000000, 0x03c00000, // sub_xmm
};
static const uint32_t FR16SubClassMask[] = {
0x00400000, 0x00000004, 0x00000020, 0x00200000,
0x00000000, 0x00000000, 0x00000000, 0x02800000, // sub_xmm
};
static const uint32_t VK16PAIRSubClassMask[] = {
0x1f800000, 0x00000000, 0x00000000, 0x00000000,
};
static const uint32_t VK1PAIRSubClassMask[] = {
0x1f800000, 0x00000000, 0x00000000, 0x00000000,
};
static const uint32_t VK2PAIRSubClassMask[] = {
0x1f800000, 0x00000000, 0x00000000, 0x00000000,
};
static const uint32_t VK4PAIRSubClassMask[] = {
0x1f800000, 0x00000000, 0x00000000, 0x00000000,
};
static const uint32_t VK8PAIRSubClassMask[] = {
0x1f800000, 0x00000000, 0x00000000, 0x00000000,
};
static const uint32_t VK16PAIR_with_sub_mask_0_in_VK16WMSubClassMask[] = {
0x10000000, 0x00000000, 0x00000000, 0x00000000,
};
static const uint32_t FR32XSubClassMask[] = {
0x20000000, 0x00000004, 0x00000024, 0x00300000,
0x00000000, 0x00000000, 0x00000000, 0x03c00000, // sub_xmm
};
static const uint32_t LOW32_ADDR_ACCESS_RBPSubClassMask[] = {
0xc0000000, 0xff3ff979, 0x00000001, 0x00001204,
0x00000000, 0x80000000, 0xded971c0, 0x0001fdfb, // sub_32bit
};
static const uint32_t LOW32_ADDR_ACCESSSubClassMask[] = {
0x80000000, 0x7f1ff958, 0x00000001, 0x00000200,
0x00000000, 0x80000000, 0xded971c0, 0x0001fdfb, // sub_32bit
};
static const uint32_t LOW32_ADDR_ACCESS_RBP_with_sub_8bitSubClassMask[] = {
0x00000000, 0xff1ff979, 0x00000000, 0x00001000,
0x00000000, 0x80000000, 0xded971c0, 0x0001fdfb, // sub_32bit
};
static const uint32_t DEBUG_REGSubClassMask[] = {
0x00000000, 0x00000002, 0x00000000, 0x00000000,
};
static const uint32_t FR32SubClassMask[] = {
0x00000000, 0x00000004, 0x00000020, 0x00200000,
0x00000000, 0x00000000, 0x00000000, 0x02800000, // sub_xmm
};
static const uint32_t GR32SubClassMask[] = {
0x00000000, 0x7f1ff958, 0x00000000, 0x00000000,
0x00000000, 0x80000000, 0xded971c0, 0x0001fdfb, // sub_32bit
};
static const uint32_t GR32_NOSPSubClassMask[] = {
0x00000000, 0x771f6910, 0x00000000, 0x00000000,
0x00000000, 0x80000000, 0x5a582180, 0x0001ddf3, // sub_32bit
};
static const uint32_t LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXSubClassMask[] = {
0x00000000, 0xff1ff960, 0x00000000, 0x00001000,
0x00000000, 0x80000000, 0xd4110000, 0x0001fdfb, // sub_32bit
};
static const uint32_t GR32_NOREXSubClassMask[] = {
0x00000000, 0x7f1ff940, 0x00000000, 0x00000000,
0x00000000, 0x80000000, 0xd4110000, 0x0001fdfb, // sub_32bit
};
static const uint32_t VK32SubClassMask[] = {
0x00000000, 0x00000480, 0x01020000, 0x00000000,
0x1f800000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
0x1f800000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
};
static const uint32_t GR32_NOREX_NOSPSubClassMask[] = {
0x00000000, 0x771f6900, 0x00000000, 0x00000000,
0x00000000, 0x80000000, 0x50100000, 0x0001ddf3, // sub_32bit
};
static const uint32_t RFP32SubClassMask[] = {
0x00000000, 0x00000200, 0x00000002, 0x00040000,
};
static const uint32_t VK32WMSubClassMask[] = {
0x00000000, 0x00000400, 0x01000000, 0x00000000,
0x10000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
0x1f800000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
};
static const uint32_t GR32_ABCDSubClassMask[] = {
0x00000000, 0x23066800, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x40000000, 0x00008c63, // sub_32bit
};
static const uint32_t GR32_TCSubClassMask[] = {
0x00000000, 0x2a047000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x80000000, 0x0000a843, // sub_32bit
};
static const uint32_t GR32_ABCD_and_GR32_TCSubClassMask[] = {
0x00000000, 0x22046000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00008843, // sub_32bit
};
static const uint32_t GR32_ADSubClassMask[] = {
0x00000000, 0x02004000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000802, // sub_32bit
};
static const uint32_t GR32_BPSPSubClassMask[] = {
0x00000000, 0x0c008000, 0x00000000, 0x00000000,
0x00000000, 0x80000000, 0x00000000, 0x00003008, // sub_32bit
};
static const uint32_t GR32_BSISubClassMask[] = {
0x00000000, 0x11010000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00004410, // sub_32bit
};
static const uint32_t GR32_CBSubClassMask[] = {
0x00000000, 0x21020000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00008420, // sub_32bit
};
static const uint32_t GR32_DCSubClassMask[] = {
0x00000000, 0x22040000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00008840, // sub_32bit
};
static const uint32_t GR32_DIBPSubClassMask[] = {
0x00000000, 0x44080000, 0x00000000, 0x00000000,
0x00000000, 0x80000000, 0x00000000, 0x00011080, // sub_32bit
};
static const uint32_t GR32_SIDISubClassMask[] = {
0x00000000, 0x50100000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00014100, // sub_32bit
};
static const uint32_t LOW32_ADDR_ACCESS_RBP_with_sub_32bitSubClassMask[] = {
0x00000000, 0x80200000, 0x00000001, 0x00001204,
};
static const uint32_t CCRSubClassMask[] = {
0x00000000, 0x00400000, 0x00000000, 0x00000000,
};
static const uint32_t DFCCRSubClassMask[] = {
0x00000000, 0x00800000, 0x00000000, 0x00000000,
};
static const uint32_t GR32_ABCD_and_GR32_BSISubClassMask[] = {
0x00000000, 0x01000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000400, // sub_32bit
};
static const uint32_t GR32_AD_and_GR32_DCSubClassMask[] = {
0x00000000, 0x02000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000800, // sub_32bit
};
static const uint32_t GR32_BPSP_and_GR32_DIBPSubClassMask[] = {
0x00000000, 0x04000000, 0x00000000, 0x00000000,
0x00000000, 0x80000000, 0x00000000, 0x00001000, // sub_32bit
};
static const uint32_t GR32_BPSP_and_GR32_TCSubClassMask[] = {
0x00000000, 0x08000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00002000, // sub_32bit
};
static const uint32_t GR32_BSI_and_GR32_SIDISubClassMask[] = {
0x00000000, 0x10000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00004000, // sub_32bit
};
static const uint32_t GR32_CB_and_GR32_DCSubClassMask[] = {
0x00000000, 0x20000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00008000, // sub_32bit
};
static const uint32_t GR32_DIBP_and_GR32_SIDISubClassMask[] = {
0x00000000, 0x40000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00010000, // sub_32bit
};
static const uint32_t LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitSubClassMask[] = {
0x00000000, 0x80000000, 0x00000000, 0x00001000,
};
static const uint32_t LOW32_ADDR_ACCESS_with_sub_32bitSubClassMask[] = {
0x00000000, 0x00000000, 0x00000001, 0x00000200,
};
static const uint32_t RFP64SubClassMask[] = {
0x00000000, 0x00000000, 0x00000002, 0x00040000,
};
static const uint32_t FR64XSubClassMask[] = {
0x00000000, 0x00000000, 0x00000024, 0x00300000,
0x00000000, 0x00000000, 0x00000000, 0x03c00000, // sub_xmm
};
static const uint32_t GR64SubClassMask[] = {
0x00000000, 0x00000000, 0xfef9ffc8, 0x0001ffff,
};
static const uint32_t CONTROL_REGSubClassMask[] = {
0x00000000, 0x00000000, 0x00000010, 0x00000000,
};
static const uint32_t FR64SubClassMask[] = {
0x00000000, 0x00000000, 0x00000020, 0x00200000,
0x00000000, 0x00000000, 0x00000000, 0x02800000, // sub_xmm
};
static const uint32_t GR64_with_sub_8bitSubClassMask[] = {
0x00000000, 0x00000000, 0xded971c0, 0x0001fdfb,
};
static const uint32_t GR64_NOSPSubClassMask[] = {
0x00000000, 0x00000000, 0x5a582180, 0x0001ddf3,
};
static const uint32_t GR64PLTSafeSubClassMask[] = {
0x00000000, 0x00000000, 0x58180100, 0x0001ddf3,
};
static const uint32_t GR64_TCSubClassMask[] = {
0x00000000, 0x00000000, 0xbea8b200, 0x0001eb43,
};
static const uint32_t GR64_NOREXSubClassMask[] = {
0x00000000, 0x00000000, 0xf4310400, 0x0001ffff,
};
static const uint32_t GR64_TCW64SubClassMask[] = {
0x00000000, 0x00000000, 0xaac0c800, 0x0000aa43,
};
static const uint32_t GR64_TC_with_sub_8bitSubClassMask[] = {
0x00000000, 0x00000000, 0x9e883000, 0x0001e943,
};
static const uint32_t GR64_NOSP_and_GR64_TCSubClassMask[] = {
0x00000000, 0x00000000, 0x1a082000, 0x0001c943,
};
static const uint32_t GR64_TCW64_with_sub_8bitSubClassMask[] = {
0x00000000, 0x00000000, 0x8ac04000, 0x0000a843,
};
static const uint32_t GR64_TC_and_GR64_TCW64SubClassMask[] = {
0x00000000, 0x00000000, 0xaa808000, 0x0000aa43,
};
static const uint32_t GR64_with_sub_16bit_in_GR16_NOREXSubClassMask[] = {
0x00000000, 0x00000000, 0xd4110000, 0x0001fdfb,
};
static const uint32_t VK64SubClassMask[] = {
0x00000000, 0x00000000, 0x01020000, 0x00000000,
0x1f800000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
0x1f800000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
};
static const uint32_t VR64SubClassMask[] = {
0x00000000, 0x00000000, 0x00040000, 0x00000000,
};
static const uint32_t GR64PLTSafe_and_GR64_TCSubClassMask[] = {
0x00000000, 0x00000000, 0x18080000, 0x0001c943,
};
static const uint32_t GR64_NOREX_NOSPSubClassMask[] = {
0x00000000, 0x00000000, 0x50100000, 0x0001ddf3,
};
static const uint32_t GR64_NOREX_and_GR64_TCSubClassMask[] = {
0x00000000, 0x00000000, 0xb4200000, 0x0001eb43,
};
static const uint32_t GR64_NOSP_and_GR64_TCW64SubClassMask[] = {
0x00000000, 0x00000000, 0x0a400000, 0x00008843,
};
static const uint32_t GR64_TCW64_and_GR64_TC_with_sub_8bitSubClassMask[] = {
0x00000000, 0x00000000, 0x8a800000, 0x0000a843,
};
static const uint32_t VK64WMSubClassMask[] = {
0x00000000, 0x00000000, 0x01000000, 0x00000000,
0x10000000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_0
0x1f800000, 0x00000000, 0x00000000, 0x00000000, // sub_mask_1
};
static const uint32_t GR64_TC_and_GR64_NOSP_and_GR64_TCW64SubClassMask[] = {
0x00000000, 0x00000000, 0x0a000000, 0x00008843,
};
static const uint32_t GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXSubClassMask[] = {
0x00000000, 0x00000000, 0x94000000, 0x0001e943,
};
static const uint32_t GR64PLTSafe_and_GR64_TCW64SubClassMask[] = {
0x00000000, 0x00000000, 0x08000000, 0x00008843,
};
static const uint32_t GR64_NOREX_and_GR64PLTSafe_and_GR64_TCSubClassMask[] = {
0x00000000, 0x00000000, 0x10000000, 0x0001c943,
};
static const uint32_t GR64_NOREX_and_GR64_TCW64SubClassMask[] = {
0x00000000, 0x00000000, 0xa0000000, 0x0000aa43,
};
static const uint32_t GR64_ABCDSubClassMask[] = {
0x00000000, 0x00000000, 0x40000000, 0x00008c63,
};
static const uint32_t GR64_with_sub_32bit_in_GR32_TCSubClassMask[] = {
0x00000000, 0x00000000, 0x80000000, 0x0000a843,
};
static const uint32_t GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCSubClassMask[] = {
0x00000000, 0x00000000, 0x00000000, 0x00008843,
};
static const uint32_t GR64_ADSubClassMask[] = {
0x00000000, 0x00000000, 0x00000000, 0x00000802,
};
static const uint32_t GR64_and_LOW32_ADDR_ACCESS_RBPSubClassMask[] = {
0x00000000, 0x00000000, 0x00000000, 0x00001204,
};
static const uint32_t GR64_with_sub_32bit_in_GR32_BPSPSubClassMask[] = {
0x00000000, 0x00000000, 0x00000000, 0x00003008,
};
static const uint32_t GR64_with_sub_32bit_in_GR32_BSISubClassMask[] = {
0x00000000, 0x00000000, 0x00000000, 0x00004410,
};
static const uint32_t GR64_with_sub_32bit_in_GR32_CBSubClassMask[] = {
0x00000000, 0x00000000, 0x00000000, 0x00008420,
};
static const uint32_t GR64_with_sub_32bit_in_GR32_DCSubClassMask[] = {
0x00000000, 0x00000000, 0x00000000, 0x00008840,
};
static const uint32_t GR64_with_sub_32bit_in_GR32_DIBPSubClassMask[] = {
0x00000000, 0x00000000, 0x00000000, 0x00011080,
};
static const uint32_t GR64_with_sub_32bit_in_GR32_SIDISubClassMask[] = {
0x00000000, 0x00000000, 0x00000000, 0x00014100,
};
static const uint32_t GR64_and_LOW32_ADDR_ACCESSSubClassMask[] = {
0x00000000, 0x00000000, 0x00000000, 0x00000200,
};
static const uint32_t GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSISubClassMask[] = {
0x00000000, 0x00000000, 0x00000000, 0x00000400,
};
static const uint32_t GR64_with_sub_32bit_in_GR32_AD_and_GR32_DCSubClassMask[] = {
0x00000000, 0x00000000, 0x00000000, 0x00000800,
};
static const uint32_t GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPSubClassMask[] = {
0x00000000, 0x00000000, 0x00000000, 0x00001000,
};
static const uint32_t GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCSubClassMask[] = {
0x00000000, 0x00000000, 0x00000000, 0x00002000,
};
static const uint32_t GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDISubClassMask[] = {
0x00000000, 0x00000000, 0x00000000, 0x00004000,
};
static const uint32_t GR64_with_sub_32bit_in_GR32_CB_and_GR32_DCSubClassMask[] = {
0x00000000, 0x00000000, 0x00000000, 0x00008000,
};
static const uint32_t GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDISubClassMask[] = {
0x00000000, 0x00000000, 0x00000000, 0x00010000,
};
static const uint32_t RSTSubClassMask[] = {
0x00000000, 0x00000000, 0x00000000, 0x00020000,
};
static const uint32_t RFP80SubClassMask[] = {
0x00000000, 0x00000000, 0x00000000, 0x00040000,
};
static const uint32_t RFP80_7SubClassMask[] = {
0x00000000, 0x00000000, 0x00000000, 0x00080000,
};
static const uint32_t VR128XSubClassMask[] = {
0x00000000, 0x00000000, 0x00000000, 0x00300000,
0x00000000, 0x00000000, 0x00000000, 0x03c00000, // sub_xmm
};
static const uint32_t VR128SubClassMask[] = {
0x00000000, 0x00000000, 0x00000000, 0x00200000,
0x00000000, 0x00000000, 0x00000000, 0x02800000, // sub_xmm
};
static const uint32_t VR256XSubClassMask[] = {
0x00000000, 0x00000000, 0x00000000, 0x00c00000,
0x00000000, 0x00000000, 0x00000000, 0x03000000, // sub_ymm
};
static const uint32_t VR256SubClassMask[] = {
0x00000000, 0x00000000, 0x00000000, 0x00800000,
0x00000000, 0x00000000, 0x00000000, 0x02000000, // sub_ymm
};
static const uint32_t VR512SubClassMask[] = {
0x00000000, 0x00000000, 0x00000000, 0x03000000,
};
static const uint32_t VR512_0_15SubClassMask[] = {
0x00000000, 0x00000000, 0x00000000, 0x02000000,
};
static const uint32_t TILESubClassMask[] = {
0x00000000, 0x00000000, 0x00000000, 0x04000000,
};
static const uint16_t SuperRegIdxSeqs[] = {
/* 0 */ 1, 0,
/* 2 */ 1, 2, 0,
/* 5 */ 4, 0,
/* 7 */ 6, 0,
/* 9 */ 7, 8, 0,
/* 12 */ 9, 0,
/* 14 */ 10, 0,
};
static const TargetRegisterClass *const GR8_NOREXSuperclasses[] = {
&X86::GR8RegClass,
nullptr
};
static const TargetRegisterClass *const GR8_ABCD_HSuperclasses[] = {
&X86::GR8RegClass,
&X86::GR8_NOREXRegClass,
nullptr
};
static const TargetRegisterClass *const GR8_ABCD_LSuperclasses[] = {
&X86::GR8RegClass,
&X86::GR8_NOREXRegClass,
nullptr
};
static const TargetRegisterClass *const GR16_NOREXSuperclasses[] = {
&X86::GR16RegClass,
nullptr
};
static const TargetRegisterClass *const VK1Superclasses[] = {
&X86::VK16RegClass,
&X86::VK2RegClass,
&X86::VK4RegClass,
&X86::VK8RegClass,
nullptr
};
static const TargetRegisterClass *const VK16Superclasses[] = {
&X86::VK1RegClass,
&X86::VK2RegClass,
&X86::VK4RegClass,
&X86::VK8RegClass,
nullptr
};
static const TargetRegisterClass *const VK2Superclasses[] = {
&X86::VK1RegClass,
&X86::VK16RegClass,
&X86::VK4RegClass,
&X86::VK8RegClass,
nullptr
};
static const TargetRegisterClass *const VK4Superclasses[] = {
&X86::VK1RegClass,
&X86::VK16RegClass,
&X86::VK2RegClass,
&X86::VK8RegClass,
nullptr
};
static const TargetRegisterClass *const VK8Superclasses[] = {
&X86::VK1RegClass,
&X86::VK16RegClass,
&X86::VK2RegClass,
&X86::VK4RegClass,
nullptr
};
static const TargetRegisterClass *const VK16WMSuperclasses[] = {
&X86::VK1RegClass,
&X86::VK16RegClass,
&X86::VK2RegClass,
&X86::VK4RegClass,
&X86::VK8RegClass,
&X86::VK1WMRegClass,
&X86::VK2WMRegClass,
&X86::VK4WMRegClass,
&X86::VK8WMRegClass,
nullptr
};
static const TargetRegisterClass *const VK1WMSuperclasses[] = {
&X86::VK1RegClass,
&X86::VK16RegClass,
&X86::VK2RegClass,
&X86::VK4RegClass,
&X86::VK8RegClass,
&X86::VK16WMRegClass,
&X86::VK2WMRegClass,
&X86::VK4WMRegClass,
&X86::VK8WMRegClass,
nullptr
};
static const TargetRegisterClass *const VK2WMSuperclasses[] = {
&X86::VK1RegClass,
&X86::VK16RegClass,
&X86::VK2RegClass,
&X86::VK4RegClass,
&X86::VK8RegClass,
&X86::VK16WMRegClass,
&X86::VK1WMRegClass,
&X86::VK4WMRegClass,
&X86::VK8WMRegClass,
nullptr
};
static const TargetRegisterClass *const VK4WMSuperclasses[] = {
&X86::VK1RegClass,
&X86::VK16RegClass,
&X86::VK2RegClass,
&X86::VK4RegClass,
&X86::VK8RegClass,
&X86::VK16WMRegClass,
&X86::VK1WMRegClass,
&X86::VK2WMRegClass,
&X86::VK8WMRegClass,
nullptr
};
static const TargetRegisterClass *const VK8WMSuperclasses[] = {
&X86::VK1RegClass,
&X86::VK16RegClass,
&X86::VK2RegClass,
&X86::VK4RegClass,
&X86::VK8RegClass,
&X86::VK16WMRegClass,
&X86::VK1WMRegClass,
&X86::VK2WMRegClass,
&X86::VK4WMRegClass,
nullptr
};
static const TargetRegisterClass *const GR16_ABCDSuperclasses[] = {
&X86::GR16RegClass,
&X86::GR16_NOREXRegClass,
nullptr
};
static const TargetRegisterClass *const FR16Superclasses[] = {
&X86::FR16XRegClass,
nullptr
};
static const TargetRegisterClass *const VK16PAIRSuperclasses[] = {
&X86::VK1PAIRRegClass,
&X86::VK2PAIRRegClass,
&X86::VK4PAIRRegClass,
&X86::VK8PAIRRegClass,
nullptr
};
static const TargetRegisterClass *const VK1PAIRSuperclasses[] = {
&X86::VK16PAIRRegClass,
&X86::VK2PAIRRegClass,
&X86::VK4PAIRRegClass,
&X86::VK8PAIRRegClass,
nullptr
};
static const TargetRegisterClass *const VK2PAIRSuperclasses[] = {
&X86::VK16PAIRRegClass,
&X86::VK1PAIRRegClass,
&X86::VK4PAIRRegClass,
&X86::VK8PAIRRegClass,
nullptr
};
static const TargetRegisterClass *const VK4PAIRSuperclasses[] = {
&X86::VK16PAIRRegClass,
&X86::VK1PAIRRegClass,
&X86::VK2PAIRRegClass,
&X86::VK8PAIRRegClass,
nullptr
};
static const TargetRegisterClass *const VK8PAIRSuperclasses[] = {
&X86::VK16PAIRRegClass,
&X86::VK1PAIRRegClass,
&X86::VK2PAIRRegClass,
&X86::VK4PAIRRegClass,
nullptr
};
static const TargetRegisterClass *const VK16PAIR_with_sub_mask_0_in_VK16WMSuperclasses[] = {
&X86::VK16PAIRRegClass,
&X86::VK1PAIRRegClass,
&X86::VK2PAIRRegClass,
&X86::VK4PAIRRegClass,
&X86::VK8PAIRRegClass,
nullptr
};
static const TargetRegisterClass *const FR32XSuperclasses[] = {
&X86::FR16XRegClass,
nullptr
};
static const TargetRegisterClass *const LOW32_ADDR_ACCESSSuperclasses[] = {
&X86::LOW32_ADDR_ACCESS_RBPRegClass,
nullptr
};
static const TargetRegisterClass *const LOW32_ADDR_ACCESS_RBP_with_sub_8bitSuperclasses[] = {
&X86::LOW32_ADDR_ACCESS_RBPRegClass,
nullptr
};
static const TargetRegisterClass *const FR32Superclasses[] = {
&X86::FR16XRegClass,
&X86::FR16RegClass,
&X86::FR32XRegClass,
nullptr
};
static const TargetRegisterClass *const GR32Superclasses[] = {
&X86::LOW32_ADDR_ACCESS_RBPRegClass,
&X86::LOW32_ADDR_ACCESSRegClass,
&X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
nullptr
};
static const TargetRegisterClass *const GR32_NOSPSuperclasses[] = {
&X86::LOW32_ADDR_ACCESS_RBPRegClass,
&X86::LOW32_ADDR_ACCESSRegClass,
&X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
&X86::GR32RegClass,
nullptr
};
static const TargetRegisterClass *const LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXSuperclasses[] = {
&X86::LOW32_ADDR_ACCESS_RBPRegClass,
&X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
nullptr
};
static const TargetRegisterClass *const GR32_NOREXSuperclasses[] = {
&X86::LOW32_ADDR_ACCESS_RBPRegClass,
&X86::LOW32_ADDR_ACCESSRegClass,
&X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
&X86::GR32RegClass,
&X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
nullptr
};
static const TargetRegisterClass *const VK32Superclasses[] = {
&X86::VK1RegClass,
&X86::VK16RegClass,
&X86::VK2RegClass,
&X86::VK4RegClass,
&X86::VK8RegClass,
nullptr
};
static const TargetRegisterClass *const GR32_NOREX_NOSPSuperclasses[] = {
&X86::LOW32_ADDR_ACCESS_RBPRegClass,
&X86::LOW32_ADDR_ACCESSRegClass,
&X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
&X86::GR32RegClass,
&X86::GR32_NOSPRegClass,
&X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
&X86::GR32_NOREXRegClass,
nullptr
};
static const TargetRegisterClass *const VK32WMSuperclasses[] = {
&X86::VK1RegClass,
&X86::VK16RegClass,
&X86::VK2RegClass,
&X86::VK4RegClass,
&X86::VK8RegClass,
&X86::VK16WMRegClass,
&X86::VK1WMRegClass,
&X86::VK2WMRegClass,
&X86::VK4WMRegClass,
&X86::VK8WMRegClass,
&X86::VK32RegClass,
nullptr
};
static const TargetRegisterClass *const GR32_ABCDSuperclasses[] = {
&X86::LOW32_ADDR_ACCESS_RBPRegClass,
&X86::LOW32_ADDR_ACCESSRegClass,
&X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
&X86::GR32RegClass,
&X86::GR32_NOSPRegClass,
&X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
&X86::GR32_NOREXRegClass,
&X86::GR32_NOREX_NOSPRegClass,
nullptr
};
static const TargetRegisterClass *const GR32_TCSuperclasses[] = {
&X86::LOW32_ADDR_ACCESS_RBPRegClass,
&X86::LOW32_ADDR_ACCESSRegClass,
&X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
&X86::GR32RegClass,
&X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
&X86::GR32_NOREXRegClass,
nullptr
};
static const TargetRegisterClass *const GR32_ABCD_and_GR32_TCSuperclasses[] = {
&X86::LOW32_ADDR_ACCESS_RBPRegClass,
&X86::LOW32_ADDR_ACCESSRegClass,
&X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
&X86::GR32RegClass,
&X86::GR32_NOSPRegClass,
&X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
&X86::GR32_NOREXRegClass,
&X86::GR32_NOREX_NOSPRegClass,
&X86::GR32_ABCDRegClass,
&X86::GR32_TCRegClass,
nullptr
};
static const TargetRegisterClass *const GR32_ADSuperclasses[] = {
&X86::LOW32_ADDR_ACCESS_RBPRegClass,
&X86::LOW32_ADDR_ACCESSRegClass,
&X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
&X86::GR32RegClass,
&X86::GR32_NOSPRegClass,
&X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
&X86::GR32_NOREXRegClass,
&X86::GR32_NOREX_NOSPRegClass,
&X86::GR32_ABCDRegClass,
&X86::GR32_TCRegClass,
&X86::GR32_ABCD_and_GR32_TCRegClass,
nullptr
};
static const TargetRegisterClass *const GR32_BPSPSuperclasses[] = {
&X86::LOW32_ADDR_ACCESS_RBPRegClass,
&X86::LOW32_ADDR_ACCESSRegClass,
&X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
&X86::GR32RegClass,
&X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
&X86::GR32_NOREXRegClass,
nullptr
};
static const TargetRegisterClass *const GR32_BSISuperclasses[] = {
&X86::LOW32_ADDR_ACCESS_RBPRegClass,
&X86::LOW32_ADDR_ACCESSRegClass,
&X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
&X86::GR32RegClass,
&X86::GR32_NOSPRegClass,
&X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
&X86::GR32_NOREXRegClass,
&X86::GR32_NOREX_NOSPRegClass,
nullptr
};
static const TargetRegisterClass *const GR32_CBSuperclasses[] = {
&X86::LOW32_ADDR_ACCESS_RBPRegClass,
&X86::LOW32_ADDR_ACCESSRegClass,
&X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
&X86::GR32RegClass,
&X86::GR32_NOSPRegClass,
&X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
&X86::GR32_NOREXRegClass,
&X86::GR32_NOREX_NOSPRegClass,
&X86::GR32_ABCDRegClass,
nullptr
};
static const TargetRegisterClass *const GR32_DCSuperclasses[] = {
&X86::LOW32_ADDR_ACCESS_RBPRegClass,
&X86::LOW32_ADDR_ACCESSRegClass,
&X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
&X86::GR32RegClass,
&X86::GR32_NOSPRegClass,
&X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
&X86::GR32_NOREXRegClass,
&X86::GR32_NOREX_NOSPRegClass,
&X86::GR32_ABCDRegClass,
&X86::GR32_TCRegClass,
&X86::GR32_ABCD_and_GR32_TCRegClass,
nullptr
};
static const TargetRegisterClass *const GR32_DIBPSuperclasses[] = {
&X86::LOW32_ADDR_ACCESS_RBPRegClass,
&X86::LOW32_ADDR_ACCESSRegClass,
&X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
&X86::GR32RegClass,
&X86::GR32_NOSPRegClass,
&X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
&X86::GR32_NOREXRegClass,
&X86::GR32_NOREX_NOSPRegClass,
nullptr
};
static const TargetRegisterClass *const GR32_SIDISuperclasses[] = {
&X86::LOW32_ADDR_ACCESS_RBPRegClass,
&X86::LOW32_ADDR_ACCESSRegClass,
&X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
&X86::GR32RegClass,
&X86::GR32_NOSPRegClass,
&X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
&X86::GR32_NOREXRegClass,
&X86::GR32_NOREX_NOSPRegClass,
nullptr
};
static const TargetRegisterClass *const LOW32_ADDR_ACCESS_RBP_with_sub_32bitSuperclasses[] = {
&X86::LOW32_ADDR_ACCESS_RBPRegClass,
nullptr
};
static const TargetRegisterClass *const GR32_ABCD_and_GR32_BSISuperclasses[] = {
&X86::LOW32_ADDR_ACCESS_RBPRegClass,
&X86::LOW32_ADDR_ACCESSRegClass,
&X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
&X86::GR32RegClass,
&X86::GR32_NOSPRegClass,
&X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
&X86::GR32_NOREXRegClass,
&X86::GR32_NOREX_NOSPRegClass,
&X86::GR32_ABCDRegClass,
&X86::GR32_BSIRegClass,
&X86::GR32_CBRegClass,
nullptr
};
static const TargetRegisterClass *const GR32_AD_and_GR32_DCSuperclasses[] = {
&X86::LOW32_ADDR_ACCESS_RBPRegClass,
&X86::LOW32_ADDR_ACCESSRegClass,
&X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
&X86::GR32RegClass,
&X86::GR32_NOSPRegClass,
&X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
&X86::GR32_NOREXRegClass,
&X86::GR32_NOREX_NOSPRegClass,
&X86::GR32_ABCDRegClass,
&X86::GR32_TCRegClass,
&X86::GR32_ABCD_and_GR32_TCRegClass,
&X86::GR32_ADRegClass,
&X86::GR32_DCRegClass,
nullptr
};
static const TargetRegisterClass *const GR32_BPSP_and_GR32_DIBPSuperclasses[] = {
&X86::LOW32_ADDR_ACCESS_RBPRegClass,
&X86::LOW32_ADDR_ACCESSRegClass,
&X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
&X86::GR32RegClass,
&X86::GR32_NOSPRegClass,
&X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
&X86::GR32_NOREXRegClass,
&X86::GR32_NOREX_NOSPRegClass,
&X86::GR32_BPSPRegClass,
&X86::GR32_DIBPRegClass,
nullptr
};
static const TargetRegisterClass *const GR32_BPSP_and_GR32_TCSuperclasses[] = {
&X86::LOW32_ADDR_ACCESS_RBPRegClass,
&X86::LOW32_ADDR_ACCESSRegClass,
&X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
&X86::GR32RegClass,
&X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
&X86::GR32_NOREXRegClass,
&X86::GR32_TCRegClass,
&X86::GR32_BPSPRegClass,
nullptr
};
static const TargetRegisterClass *const GR32_BSI_and_GR32_SIDISuperclasses[] = {
&X86::LOW32_ADDR_ACCESS_RBPRegClass,
&X86::LOW32_ADDR_ACCESSRegClass,
&X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
&X86::GR32RegClass,
&X86::GR32_NOSPRegClass,
&X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
&X86::GR32_NOREXRegClass,
&X86::GR32_NOREX_NOSPRegClass,
&X86::GR32_BSIRegClass,
&X86::GR32_SIDIRegClass,
nullptr
};
static const TargetRegisterClass *const GR32_CB_and_GR32_DCSuperclasses[] = {
&X86::LOW32_ADDR_ACCESS_RBPRegClass,
&X86::LOW32_ADDR_ACCESSRegClass,
&X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
&X86::GR32RegClass,
&X86::GR32_NOSPRegClass,
&X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
&X86::GR32_NOREXRegClass,
&X86::GR32_NOREX_NOSPRegClass,
&X86::GR32_ABCDRegClass,
&X86::GR32_TCRegClass,
&X86::GR32_ABCD_and_GR32_TCRegClass,
&X86::GR32_CBRegClass,
&X86::GR32_DCRegClass,
nullptr
};
static const TargetRegisterClass *const GR32_DIBP_and_GR32_SIDISuperclasses[] = {
&X86::LOW32_ADDR_ACCESS_RBPRegClass,
&X86::LOW32_ADDR_ACCESSRegClass,
&X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
&X86::GR32RegClass,
&X86::GR32_NOSPRegClass,
&X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
&X86::GR32_NOREXRegClass,
&X86::GR32_NOREX_NOSPRegClass,
&X86::GR32_DIBPRegClass,
&X86::GR32_SIDIRegClass,
nullptr
};
static const TargetRegisterClass *const LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitSuperclasses[] = {
&X86::LOW32_ADDR_ACCESS_RBPRegClass,
&X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
&X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
&X86::LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClass,
nullptr
};
static const TargetRegisterClass *const LOW32_ADDR_ACCESS_with_sub_32bitSuperclasses[] = {
&X86::LOW32_ADDR_ACCESS_RBPRegClass,
&X86::LOW32_ADDR_ACCESSRegClass,
&X86::LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClass,
nullptr
};
static const TargetRegisterClass *const RFP64Superclasses[] = {
&X86::RFP32RegClass,
nullptr
};
static const TargetRegisterClass *const FR64XSuperclasses[] = {
&X86::FR16XRegClass,
&X86::FR32XRegClass,
nullptr
};
static const TargetRegisterClass *const FR64Superclasses[] = {
&X86::FR16XRegClass,
&X86::FR16RegClass,
&X86::FR32XRegClass,
&X86::FR32RegClass,
&X86::FR64XRegClass,
nullptr
};
static const TargetRegisterClass *const GR64_with_sub_8bitSuperclasses[] = {
&X86::GR64RegClass,
nullptr
};
static const TargetRegisterClass *const GR64_NOSPSuperclasses[] = {
&X86::GR64RegClass,
&X86::GR64_with_sub_8bitRegClass,
nullptr
};
static const TargetRegisterClass *const GR64PLTSafeSuperclasses[] = {
&X86::GR64RegClass,
&X86::GR64_with_sub_8bitRegClass,
&X86::GR64_NOSPRegClass,
nullptr
};
static const TargetRegisterClass *const GR64_TCSuperclasses[] = {
&X86::GR64RegClass,
nullptr
};
static const TargetRegisterClass *const GR64_NOREXSuperclasses[] = {
&X86::GR64RegClass,
nullptr
};
static const TargetRegisterClass *const GR64_TCW64Superclasses[] = {
&X86::GR64RegClass,
nullptr
};
static const TargetRegisterClass *const GR64_TC_with_sub_8bitSuperclasses[] = {
&X86::GR64RegClass,
&X86::GR64_with_sub_8bitRegClass,
&X86::GR64_TCRegClass,
nullptr
};
static const TargetRegisterClass *const GR64_NOSP_and_GR64_TCSuperclasses[] = {
&X86::GR64RegClass,
&X86::GR64_with_sub_8bitRegClass,
&X86::GR64_NOSPRegClass,
&X86::GR64_TCRegClass,
&X86::GR64_TC_with_sub_8bitRegClass,
nullptr
};
static const TargetRegisterClass *const GR64_TCW64_with_sub_8bitSuperclasses[] = {
&X86::GR64RegClass,
&X86::GR64_with_sub_8bitRegClass,
&X86::GR64_TCW64RegClass,
nullptr
};
static const TargetRegisterClass *const GR64_TC_and_GR64_TCW64Superclasses[] = {
&X86::GR64RegClass,
&X86::GR64_TCRegClass,
&X86::GR64_TCW64RegClass,
nullptr
};
static const TargetRegisterClass *const GR64_with_sub_16bit_in_GR16_NOREXSuperclasses[] = {
&X86::GR64RegClass,
&X86::GR64_with_sub_8bitRegClass,
&X86::GR64_NOREXRegClass,
nullptr
};
static const TargetRegisterClass *const VK64Superclasses[] = {
&X86::VK1RegClass,
&X86::VK16RegClass,
&X86::VK2RegClass,
&X86::VK4RegClass,
&X86::VK8RegClass,
&X86::VK32RegClass,
nullptr
};
static const TargetRegisterClass *const GR64PLTSafe_and_GR64_TCSuperclasses[] = {
&X86::GR64RegClass,
&X86::GR64_with_sub_8bitRegClass,
&X86::GR64_NOSPRegClass,
&X86::GR64PLTSafeRegClass,
&X86::GR64_TCRegClass,
&X86::GR64_TC_with_sub_8bitRegClass,
&X86::GR64_NOSP_and_GR64_TCRegClass,
nullptr
};
static const TargetRegisterClass *const GR64_NOREX_NOSPSuperclasses[] = {
&X86::GR64RegClass,
&X86::GR64_with_sub_8bitRegClass,
&X86::GR64_NOSPRegClass,
&X86::GR64PLTSafeRegClass,
&X86::GR64_NOREXRegClass,
&X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
nullptr
};
static const TargetRegisterClass *const GR64_NOREX_and_GR64_TCSuperclasses[] = {
&X86::GR64RegClass,
&X86::GR64_TCRegClass,
&X86::GR64_NOREXRegClass,
nullptr
};
static const TargetRegisterClass *const GR64_NOSP_and_GR64_TCW64Superclasses[] = {
&X86::GR64RegClass,
&X86::GR64_with_sub_8bitRegClass,
&X86::GR64_NOSPRegClass,
&X86::GR64_TCW64RegClass,
&X86::GR64_TCW64_with_sub_8bitRegClass,
nullptr
};
static const TargetRegisterClass *const GR64_TCW64_and_GR64_TC_with_sub_8bitSuperclasses[] = {
&X86::GR64RegClass,
&X86::GR64_with_sub_8bitRegClass,
&X86::GR64_TCRegClass,
&X86::GR64_TCW64RegClass,
&X86::GR64_TC_with_sub_8bitRegClass,
&X86::GR64_TCW64_with_sub_8bitRegClass,
&X86::GR64_TC_and_GR64_TCW64RegClass,
nullptr
};
static const TargetRegisterClass *const VK64WMSuperclasses[] = {
&X86::VK1RegClass,
&X86::VK16RegClass,
&X86::VK2RegClass,
&X86::VK4RegClass,
&X86::VK8RegClass,
&X86::VK16WMRegClass,
&X86::VK1WMRegClass,
&X86::VK2WMRegClass,
&X86::VK4WMRegClass,
&X86::VK8WMRegClass,
&X86::VK32RegClass,
&X86::VK32WMRegClass,
&X86::VK64RegClass,
nullptr
};
static const TargetRegisterClass *const GR64_TC_and_GR64_NOSP_and_GR64_TCW64Superclasses[] = {
&X86::GR64RegClass,
&X86::GR64_with_sub_8bitRegClass,
&X86::GR64_NOSPRegClass,
&X86::GR64_TCRegClass,
&X86::GR64_TCW64RegClass,
&X86::GR64_TC_with_sub_8bitRegClass,
&X86::GR64_NOSP_and_GR64_TCRegClass,
&X86::GR64_TCW64_with_sub_8bitRegClass,
&X86::GR64_TC_and_GR64_TCW64RegClass,
&X86::GR64_NOSP_and_GR64_TCW64RegClass,
&X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClass,
nullptr
};
static const TargetRegisterClass *const GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXSuperclasses[] = {
&X86::GR64RegClass,
&X86::GR64_with_sub_8bitRegClass,
&X86::GR64_TCRegClass,
&X86::GR64_NOREXRegClass,
&X86::GR64_TC_with_sub_8bitRegClass,
&X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
&X86::GR64_NOREX_and_GR64_TCRegClass,
nullptr
};
static const TargetRegisterClass *const GR64PLTSafe_and_GR64_TCW64Superclasses[] = {
&X86::GR64RegClass,
&X86::GR64_with_sub_8bitRegClass,
&X86::GR64_NOSPRegClass,
&X86::GR64PLTSafeRegClass,
&X86::GR64_TCRegClass,
&X86::GR64_TCW64RegClass,
&X86::GR64_TC_with_sub_8bitRegClass,
&X86::GR64_NOSP_and_GR64_TCRegClass,
&X86::GR64_TCW64_with_sub_8bitRegClass,
&X86::GR64_TC_and_GR64_TCW64RegClass,
&X86::GR64PLTSafe_and_GR64_TCRegClass,
&X86::GR64_NOSP_and_GR64_TCW64RegClass,
&X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClass,
&X86::GR64_TC_and_GR64_NOSP_and_GR64_TCW64RegClass,
nullptr
};
static const TargetRegisterClass *const GR64_NOREX_and_GR64PLTSafe_and_GR64_TCSuperclasses[] = {
&X86::GR64RegClass,
&X86::GR64_with_sub_8bitRegClass,
&X86::GR64_NOSPRegClass,
&X86::GR64PLTSafeRegClass,
&X86::GR64_TCRegClass,
&X86::GR64_NOREXRegClass,
&X86::GR64_TC_with_sub_8bitRegClass,
&X86::GR64_NOSP_and_GR64_TCRegClass,
&X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
&X86::GR64PLTSafe_and_GR64_TCRegClass,
&X86::GR64_NOREX_NOSPRegClass,
&X86::GR64_NOREX_and_GR64_TCRegClass,
&X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClass,
nullptr
};
static const TargetRegisterClass *const GR64_NOREX_and_GR64_TCW64Superclasses[] = {
&X86::GR64RegClass,
&X86::GR64_TCRegClass,
&X86::GR64_NOREXRegClass,
&X86::GR64_TCW64RegClass,
&X86::GR64_TC_and_GR64_TCW64RegClass,
&X86::GR64_NOREX_and_GR64_TCRegClass,
nullptr
};
static const TargetRegisterClass *const GR64_ABCDSuperclasses[] = {
&X86::GR64RegClass,
&X86::GR64_with_sub_8bitRegClass,
&X86::GR64_NOSPRegClass,
&X86::GR64PLTSafeRegClass,
&X86::GR64_NOREXRegClass,
&X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
&X86::GR64_NOREX_NOSPRegClass,
nullptr
};
static const TargetRegisterClass *const GR64_with_sub_32bit_in_GR32_TCSuperclasses[] = {
&X86::GR64RegClass,
&X86::GR64_with_sub_8bitRegClass,
&X86::GR64_TCRegClass,
&X86::GR64_NOREXRegClass,
&X86::GR64_TCW64RegClass,
&X86::GR64_TC_with_sub_8bitRegClass,
&X86::GR64_TCW64_with_sub_8bitRegClass,
&X86::GR64_TC_and_GR64_TCW64RegClass,
&X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
&X86::GR64_NOREX_and_GR64_TCRegClass,
&X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClass,
&X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClass,
&X86::GR64_NOREX_and_GR64_TCW64RegClass,
nullptr
};
static const TargetRegisterClass *const GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCSuperclasses[] = {
&X86::GR64RegClass,
&X86::GR64_with_sub_8bitRegClass,
&X86::GR64_NOSPRegClass,
&X86::GR64PLTSafeRegClass,
&X86::GR64_TCRegClass,
&X86::GR64_NOREXRegClass,
&X86::GR64_TCW64RegClass,
&X86::GR64_TC_with_sub_8bitRegClass,
&X86::GR64_NOSP_and_GR64_TCRegClass,
&X86::GR64_TCW64_with_sub_8bitRegClass,
&X86::GR64_TC_and_GR64_TCW64RegClass,
&X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
&X86::GR64PLTSafe_and_GR64_TCRegClass,
&X86::GR64_NOREX_NOSPRegClass,
&X86::GR64_NOREX_and_GR64_TCRegClass,
&X86::GR64_NOSP_and_GR64_TCW64RegClass,
&X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClass,
&X86::GR64_TC_and_GR64_NOSP_and_GR64_TCW64RegClass,
&X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClass,
&X86::GR64PLTSafe_and_GR64_TCW64RegClass,
&X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClass,
&X86::GR64_NOREX_and_GR64_TCW64RegClass,
&X86::GR64_ABCDRegClass,
&X86::GR64_with_sub_32bit_in_GR32_TCRegClass,
nullptr
};
static const TargetRegisterClass *const GR64_ADSuperclasses[] = {
&X86::GR64RegClass,
&X86::GR64_with_sub_8bitRegClass,
&X86::GR64_NOSPRegClass,
&X86::GR64PLTSafeRegClass,
&X86::GR64_TCRegClass,
&X86::GR64_NOREXRegClass,
&X86::GR64_TCW64RegClass,
&X86::GR64_TC_with_sub_8bitRegClass,
&X86::GR64_NOSP_and_GR64_TCRegClass,
&X86::GR64_TCW64_with_sub_8bitRegClass,
&X86::GR64_TC_and_GR64_TCW64RegClass,
&X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
&X86::GR64PLTSafe_and_GR64_TCRegClass,
&X86::GR64_NOREX_NOSPRegClass,
&X86::GR64_NOREX_and_GR64_TCRegClass,
&X86::GR64_NOSP_and_GR64_TCW64RegClass,
&X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClass,
&X86::GR64_TC_and_GR64_NOSP_and_GR64_TCW64RegClass,
&X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClass,
&X86::GR64PLTSafe_and_GR64_TCW64RegClass,
&X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClass,
&X86::GR64_NOREX_and_GR64_TCW64RegClass,
&X86::GR64_ABCDRegClass,
&X86::GR64_with_sub_32bit_in_GR32_TCRegClass,
&X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClass,
nullptr
};
static const TargetRegisterClass *const GR64_and_LOW32_ADDR_ACCESS_RBPSuperclasses[] = {
&X86::LOW32_ADDR_ACCESS_RBPRegClass,
&X86::LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClass,
&X86::GR64RegClass,
&X86::GR64_NOREXRegClass,
nullptr
};
static const TargetRegisterClass *const GR64_with_sub_32bit_in_GR32_BPSPSuperclasses[] = {
&X86::GR64RegClass,
&X86::GR64_with_sub_8bitRegClass,
&X86::GR64_NOREXRegClass,
&X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
nullptr
};
static const TargetRegisterClass *const GR64_with_sub_32bit_in_GR32_BSISuperclasses[] = {
&X86::GR64RegClass,
&X86::GR64_with_sub_8bitRegClass,
&X86::GR64_NOSPRegClass,
&X86::GR64PLTSafeRegClass,
&X86::GR64_NOREXRegClass,
&X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
&X86::GR64_NOREX_NOSPRegClass,
nullptr
};
static const TargetRegisterClass *const GR64_with_sub_32bit_in_GR32_CBSuperclasses[] = {
&X86::GR64RegClass,
&X86::GR64_with_sub_8bitRegClass,
&X86::GR64_NOSPRegClass,
&X86::GR64PLTSafeRegClass,
&X86::GR64_NOREXRegClass,
&X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
&X86::GR64_NOREX_NOSPRegClass,
&X86::GR64_ABCDRegClass,
nullptr
};
static const TargetRegisterClass *const GR64_with_sub_32bit_in_GR32_DCSuperclasses[] = {
&X86::GR64RegClass,
&X86::GR64_with_sub_8bitRegClass,
&X86::GR64_NOSPRegClass,
&X86::GR64PLTSafeRegClass,
&X86::GR64_TCRegClass,
&X86::GR64_NOREXRegClass,
&X86::GR64_TCW64RegClass,
&X86::GR64_TC_with_sub_8bitRegClass,
&X86::GR64_NOSP_and_GR64_TCRegClass,
&X86::GR64_TCW64_with_sub_8bitRegClass,
&X86::GR64_TC_and_GR64_TCW64RegClass,
&X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
&X86::GR64PLTSafe_and_GR64_TCRegClass,
&X86::GR64_NOREX_NOSPRegClass,
&X86::GR64_NOREX_and_GR64_TCRegClass,
&X86::GR64_NOSP_and_GR64_TCW64RegClass,
&X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClass,
&X86::GR64_TC_and_GR64_NOSP_and_GR64_TCW64RegClass,
&X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClass,
&X86::GR64PLTSafe_and_GR64_TCW64RegClass,
&X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClass,
&X86::GR64_NOREX_and_GR64_TCW64RegClass,
&X86::GR64_ABCDRegClass,
&X86::GR64_with_sub_32bit_in_GR32_TCRegClass,
&X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClass,
nullptr
};
static const TargetRegisterClass *const GR64_with_sub_32bit_in_GR32_DIBPSuperclasses[] = {
&X86::GR64RegClass,
&X86::GR64_with_sub_8bitRegClass,
&X86::GR64_NOSPRegClass,
&X86::GR64PLTSafeRegClass,
&X86::GR64_NOREXRegClass,
&X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
&X86::GR64_NOREX_NOSPRegClass,
nullptr
};
static const TargetRegisterClass *const GR64_with_sub_32bit_in_GR32_SIDISuperclasses[] = {
&X86::GR64RegClass,
&X86::GR64_with_sub_8bitRegClass,
&X86::GR64_NOSPRegClass,
&X86::GR64PLTSafeRegClass,
&X86::GR64_TCRegClass,
&X86::GR64_NOREXRegClass,
&X86::GR64_TC_with_sub_8bitRegClass,
&X86::GR64_NOSP_and_GR64_TCRegClass,
&X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
&X86::GR64PLTSafe_and_GR64_TCRegClass,
&X86::GR64_NOREX_NOSPRegClass,
&X86::GR64_NOREX_and_GR64_TCRegClass,
&X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClass,
&X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClass,
nullptr
};
static const TargetRegisterClass *const GR64_and_LOW32_ADDR_ACCESSSuperclasses[] = {
&X86::LOW32_ADDR_ACCESS_RBPRegClass,
&X86::LOW32_ADDR_ACCESSRegClass,
&X86::LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClass,
&X86::LOW32_ADDR_ACCESS_with_sub_32bitRegClass,
&X86::GR64RegClass,
&X86::GR64_TCRegClass,
&X86::GR64_NOREXRegClass,
&X86::GR64_TCW64RegClass,
&X86::GR64_TC_and_GR64_TCW64RegClass,
&X86::GR64_NOREX_and_GR64_TCRegClass,
&X86::GR64_NOREX_and_GR64_TCW64RegClass,
&X86::GR64_and_LOW32_ADDR_ACCESS_RBPRegClass,
nullptr
};
static const TargetRegisterClass *const GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSISuperclasses[] = {
&X86::GR64RegClass,
&X86::GR64_with_sub_8bitRegClass,
&X86::GR64_NOSPRegClass,
&X86::GR64PLTSafeRegClass,
&X86::GR64_NOREXRegClass,
&X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
&X86::GR64_NOREX_NOSPRegClass,
&X86::GR64_ABCDRegClass,
&X86::GR64_with_sub_32bit_in_GR32_BSIRegClass,
&X86::GR64_with_sub_32bit_in_GR32_CBRegClass,
nullptr
};
static const TargetRegisterClass *const GR64_with_sub_32bit_in_GR32_AD_and_GR32_DCSuperclasses[] = {
&X86::GR64RegClass,
&X86::GR64_with_sub_8bitRegClass,
&X86::GR64_NOSPRegClass,
&X86::GR64PLTSafeRegClass,
&X86::GR64_TCRegClass,
&X86::GR64_NOREXRegClass,
&X86::GR64_TCW64RegClass,
&X86::GR64_TC_with_sub_8bitRegClass,
&X86::GR64_NOSP_and_GR64_TCRegClass,
&X86::GR64_TCW64_with_sub_8bitRegClass,
&X86::GR64_TC_and_GR64_TCW64RegClass,
&X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
&X86::GR64PLTSafe_and_GR64_TCRegClass,
&X86::GR64_NOREX_NOSPRegClass,
&X86::GR64_NOREX_and_GR64_TCRegClass,
&X86::GR64_NOSP_and_GR64_TCW64RegClass,
&X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClass,
&X86::GR64_TC_and_GR64_NOSP_and_GR64_TCW64RegClass,
&X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClass,
&X86::GR64PLTSafe_and_GR64_TCW64RegClass,
&X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClass,
&X86::GR64_NOREX_and_GR64_TCW64RegClass,
&X86::GR64_ABCDRegClass,
&X86::GR64_with_sub_32bit_in_GR32_TCRegClass,
&X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClass,
&X86::GR64_ADRegClass,
&X86::GR64_with_sub_32bit_in_GR32_DCRegClass,
nullptr
};
static const TargetRegisterClass *const GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPSuperclasses[] = {
&X86::LOW32_ADDR_ACCESS_RBPRegClass,
&X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
&X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
&X86::LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClass,
&X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitRegClass,
&X86::GR64RegClass,
&X86::GR64_with_sub_8bitRegClass,
&X86::GR64_NOSPRegClass,
&X86::GR64PLTSafeRegClass,
&X86::GR64_NOREXRegClass,
&X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
&X86::GR64_NOREX_NOSPRegClass,
&X86::GR64_and_LOW32_ADDR_ACCESS_RBPRegClass,
&X86::GR64_with_sub_32bit_in_GR32_BPSPRegClass,
&X86::GR64_with_sub_32bit_in_GR32_DIBPRegClass,
nullptr
};
static const TargetRegisterClass *const GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCSuperclasses[] = {
&X86::GR64RegClass,
&X86::GR64_with_sub_8bitRegClass,
&X86::GR64_TCRegClass,
&X86::GR64_NOREXRegClass,
&X86::GR64_TCW64RegClass,
&X86::GR64_TC_with_sub_8bitRegClass,
&X86::GR64_TCW64_with_sub_8bitRegClass,
&X86::GR64_TC_and_GR64_TCW64RegClass,
&X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
&X86::GR64_NOREX_and_GR64_TCRegClass,
&X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClass,
&X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClass,
&X86::GR64_NOREX_and_GR64_TCW64RegClass,
&X86::GR64_with_sub_32bit_in_GR32_TCRegClass,
&X86::GR64_with_sub_32bit_in_GR32_BPSPRegClass,
nullptr
};
static const TargetRegisterClass *const GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDISuperclasses[] = {
&X86::GR64RegClass,
&X86::GR64_with_sub_8bitRegClass,
&X86::GR64_NOSPRegClass,
&X86::GR64PLTSafeRegClass,
&X86::GR64_TCRegClass,
&X86::GR64_NOREXRegClass,
&X86::GR64_TC_with_sub_8bitRegClass,
&X86::GR64_NOSP_and_GR64_TCRegClass,
&X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
&X86::GR64PLTSafe_and_GR64_TCRegClass,
&X86::GR64_NOREX_NOSPRegClass,
&X86::GR64_NOREX_and_GR64_TCRegClass,
&X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClass,
&X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClass,
&X86::GR64_with_sub_32bit_in_GR32_BSIRegClass,
&X86::GR64_with_sub_32bit_in_GR32_SIDIRegClass,
nullptr
};
static const TargetRegisterClass *const GR64_with_sub_32bit_in_GR32_CB_and_GR32_DCSuperclasses[] = {
&X86::GR64RegClass,
&X86::GR64_with_sub_8bitRegClass,
&X86::GR64_NOSPRegClass,
&X86::GR64PLTSafeRegClass,
&X86::GR64_TCRegClass,
&X86::GR64_NOREXRegClass,
&X86::GR64_TCW64RegClass,
&X86::GR64_TC_with_sub_8bitRegClass,
&X86::GR64_NOSP_and_GR64_TCRegClass,
&X86::GR64_TCW64_with_sub_8bitRegClass,
&X86::GR64_TC_and_GR64_TCW64RegClass,
&X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
&X86::GR64PLTSafe_and_GR64_TCRegClass,
&X86::GR64_NOREX_NOSPRegClass,
&X86::GR64_NOREX_and_GR64_TCRegClass,
&X86::GR64_NOSP_and_GR64_TCW64RegClass,
&X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClass,
&X86::GR64_TC_and_GR64_NOSP_and_GR64_TCW64RegClass,
&X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClass,
&X86::GR64PLTSafe_and_GR64_TCW64RegClass,
&X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClass,
&X86::GR64_NOREX_and_GR64_TCW64RegClass,
&X86::GR64_ABCDRegClass,
&X86::GR64_with_sub_32bit_in_GR32_TCRegClass,
&X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClass,
&X86::GR64_with_sub_32bit_in_GR32_CBRegClass,
&X86::GR64_with_sub_32bit_in_GR32_DCRegClass,
nullptr
};
static const TargetRegisterClass *const GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDISuperclasses[] = {
&X86::GR64RegClass,
&X86::GR64_with_sub_8bitRegClass,
&X86::GR64_NOSPRegClass,
&X86::GR64PLTSafeRegClass,
&X86::GR64_TCRegClass,
&X86::GR64_NOREXRegClass,
&X86::GR64_TC_with_sub_8bitRegClass,
&X86::GR64_NOSP_and_GR64_TCRegClass,
&X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
&X86::GR64PLTSafe_and_GR64_TCRegClass,
&X86::GR64_NOREX_NOSPRegClass,
&X86::GR64_NOREX_and_GR64_TCRegClass,
&X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClass,
&X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClass,
&X86::GR64_with_sub_32bit_in_GR32_DIBPRegClass,
&X86::GR64_with_sub_32bit_in_GR32_SIDIRegClass,
nullptr
};
static const TargetRegisterClass *const RFP80Superclasses[] = {
&X86::RFP32RegClass,
&X86::RFP64RegClass,
nullptr
};
static const TargetRegisterClass *const VR128XSuperclasses[] = {
&X86::FR16XRegClass,
&X86::FR32XRegClass,
&X86::FR64XRegClass,
nullptr
};
static const TargetRegisterClass *const VR128Superclasses[] = {
&X86::FR16XRegClass,
&X86::FR16RegClass,
&X86::FR32XRegClass,
&X86::FR32RegClass,
&X86::FR64XRegClass,
&X86::FR64RegClass,
&X86::VR128XRegClass,
nullptr
};
static const TargetRegisterClass *const VR256Superclasses[] = {
&X86::VR256XRegClass,
nullptr
};
static const TargetRegisterClass *const VR512_0_15Superclasses[] = {
&X86::VR512RegClass,
nullptr
};
static inline unsigned GR8AltOrderSelect(const MachineFunction &MF) {
return MF.getSubtarget<X86Subtarget>().is64Bit();
}
static ArrayRef<MCPhysReg> GR8GetRawAllocationOrder(const MachineFunction &MF) {
static const MCPhysReg AltOrder1[] = { X86::AL, X86::CL, X86::DL, X86::BL, X86::SIL, X86::DIL, X86::BPL, X86::SPL, X86::R8B, X86::R9B, X86::R10B, X86::R11B, X86::R14B, X86::R15B, X86::R12B, X86::R13B };
const MCRegisterClass &MCR = X86MCRegisterClasses[X86::GR8RegClassID];
const ArrayRef<MCPhysReg> Order[] = {
ArrayRef(MCR.begin(), MCR.getNumRegs()),
ArrayRef(AltOrder1)
};
const unsigned Select = GR8AltOrderSelect(MF);
assert(Select < 2);
return Order[Select];
}
static inline unsigned GR8_NOREXAltOrderSelect(const MachineFunction &MF) {
return MF.getSubtarget<X86Subtarget>().is64Bit();
}
static ArrayRef<MCPhysReg> GR8_NOREXGetRawAllocationOrder(const MachineFunction &MF) {
static const MCPhysReg AltOrder1[] = { X86::AL, X86::CL, X86::DL, X86::BL };
const MCRegisterClass &MCR = X86MCRegisterClasses[X86::GR8_NOREXRegClassID];
const ArrayRef<MCPhysReg> Order[] = {
ArrayRef(MCR.begin(), MCR.getNumRegs()),
ArrayRef(AltOrder1)
};
const unsigned Select = GR8_NOREXAltOrderSelect(MF);
assert(Select < 2);
return Order[Select];
}
namespace X86 { // Register class instances
extern const TargetRegisterClass GR8RegClass = {
&X86MCRegisterClasses[GR8RegClassID],
GR8SubClassMask,
SuperRegIdxSeqs + 2,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
NullRegClasses,
GR8GetRawAllocationOrder
};
extern const TargetRegisterClass GRH8RegClass = {
&X86MCRegisterClasses[GRH8RegClassID],
GRH8SubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
NullRegClasses,
nullptr
};
extern const TargetRegisterClass GR8_NOREXRegClass = {
&X86MCRegisterClasses[GR8_NOREXRegClassID],
GR8_NOREXSubClassMask,
SuperRegIdxSeqs + 2,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
GR8_NOREXSuperclasses,
GR8_NOREXGetRawAllocationOrder
};
extern const TargetRegisterClass GR8_ABCD_HRegClass = {
&X86MCRegisterClasses[GR8_ABCD_HRegClassID],
GR8_ABCD_HSubClassMask,
SuperRegIdxSeqs + 3,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
GR8_ABCD_HSuperclasses,
nullptr
};
extern const TargetRegisterClass GR8_ABCD_LRegClass = {
&X86MCRegisterClasses[GR8_ABCD_LRegClassID],
GR8_ABCD_LSubClassMask,
SuperRegIdxSeqs + 0,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
GR8_ABCD_LSuperclasses,
nullptr
};
extern const TargetRegisterClass GRH16RegClass = {
&X86MCRegisterClasses[GRH16RegClassID],
GRH16SubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
NullRegClasses,
nullptr
};
extern const TargetRegisterClass GR16RegClass = {
&X86MCRegisterClasses[GR16RegClassID],
GR16SubClassMask,
SuperRegIdxSeqs + 5,
LaneBitmask(0x0000000000000003),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
true, /* CoveredBySubRegs */
NullRegClasses,
nullptr
};
extern const TargetRegisterClass GR16_NOREXRegClass = {
&X86MCRegisterClasses[GR16_NOREXRegClassID],
GR16_NOREXSubClassMask,
SuperRegIdxSeqs + 5,
LaneBitmask(0x0000000000000003),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
true, /* CoveredBySubRegs */
GR16_NOREXSuperclasses,
nullptr
};
extern const TargetRegisterClass VK1RegClass = {
&X86MCRegisterClasses[VK1RegClassID],
VK1SubClassMask,
SuperRegIdxSeqs + 9,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
VK1Superclasses,
nullptr
};
extern const TargetRegisterClass VK16RegClass = {
&X86MCRegisterClasses[VK16RegClassID],
VK16SubClassMask,
SuperRegIdxSeqs + 9,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
VK16Superclasses,
nullptr
};
extern const TargetRegisterClass VK2RegClass = {
&X86MCRegisterClasses[VK2RegClassID],
VK2SubClassMask,
SuperRegIdxSeqs + 9,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
VK2Superclasses,
nullptr
};
extern const TargetRegisterClass VK4RegClass = {
&X86MCRegisterClasses[VK4RegClassID],
VK4SubClassMask,
SuperRegIdxSeqs + 9,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
VK4Superclasses,
nullptr
};
extern const TargetRegisterClass VK8RegClass = {
&X86MCRegisterClasses[VK8RegClassID],
VK8SubClassMask,
SuperRegIdxSeqs + 9,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
VK8Superclasses,
nullptr
};
extern const TargetRegisterClass VK16WMRegClass = {
&X86MCRegisterClasses[VK16WMRegClassID],
VK16WMSubClassMask,
SuperRegIdxSeqs + 9,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
VK16WMSuperclasses,
nullptr
};
extern const TargetRegisterClass VK1WMRegClass = {
&X86MCRegisterClasses[VK1WMRegClassID],
VK1WMSubClassMask,
SuperRegIdxSeqs + 9,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
VK1WMSuperclasses,
nullptr
};
extern const TargetRegisterClass VK2WMRegClass = {
&X86MCRegisterClasses[VK2WMRegClassID],
VK2WMSubClassMask,
SuperRegIdxSeqs + 9,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
VK2WMSuperclasses,
nullptr
};
extern const TargetRegisterClass VK4WMRegClass = {
&X86MCRegisterClasses[VK4WMRegClassID],
VK4WMSubClassMask,
SuperRegIdxSeqs + 9,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
VK4WMSuperclasses,
nullptr
};
extern const TargetRegisterClass VK8WMRegClass = {
&X86MCRegisterClasses[VK8WMRegClassID],
VK8WMSubClassMask,
SuperRegIdxSeqs + 9,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
VK8WMSuperclasses,
nullptr
};
extern const TargetRegisterClass SEGMENT_REGRegClass = {
&X86MCRegisterClasses[SEGMENT_REGRegClassID],
SEGMENT_REGSubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
NullRegClasses,
nullptr
};
extern const TargetRegisterClass GR16_ABCDRegClass = {
&X86MCRegisterClasses[GR16_ABCDRegClassID],
GR16_ABCDSubClassMask,
SuperRegIdxSeqs + 5,
LaneBitmask(0x0000000000000003),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
true, /* CoveredBySubRegs */
GR16_ABCDSuperclasses,
nullptr
};
extern const TargetRegisterClass FPCCRRegClass = {
&X86MCRegisterClasses[FPCCRRegClassID],
FPCCRSubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
NullRegClasses,
nullptr
};
extern const TargetRegisterClass FR16XRegClass = {
&X86MCRegisterClasses[FR16XRegClassID],
FR16XSubClassMask,
SuperRegIdxSeqs + 12,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
NullRegClasses,
nullptr
};
extern const TargetRegisterClass FR16RegClass = {
&X86MCRegisterClasses[FR16RegClassID],
FR16SubClassMask,
SuperRegIdxSeqs + 12,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
FR16Superclasses,
nullptr
};
extern const TargetRegisterClass VK16PAIRRegClass = {
&X86MCRegisterClasses[VK16PAIRRegClassID],
VK16PAIRSubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x0000000000000030),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
true, /* CoveredBySubRegs */
VK16PAIRSuperclasses,
nullptr
};
extern const TargetRegisterClass VK1PAIRRegClass = {
&X86MCRegisterClasses[VK1PAIRRegClassID],
VK1PAIRSubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x0000000000000030),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
true, /* CoveredBySubRegs */
VK1PAIRSuperclasses,
nullptr
};
extern const TargetRegisterClass VK2PAIRRegClass = {
&X86MCRegisterClasses[VK2PAIRRegClassID],
VK2PAIRSubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x0000000000000030),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
true, /* CoveredBySubRegs */
VK2PAIRSuperclasses,
nullptr
};
extern const TargetRegisterClass VK4PAIRRegClass = {
&X86MCRegisterClasses[VK4PAIRRegClassID],
VK4PAIRSubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x0000000000000030),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
true, /* CoveredBySubRegs */
VK4PAIRSuperclasses,
nullptr
};
extern const TargetRegisterClass VK8PAIRRegClass = {
&X86MCRegisterClasses[VK8PAIRRegClassID],
VK8PAIRSubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x0000000000000030),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
true, /* CoveredBySubRegs */
VK8PAIRSuperclasses,
nullptr
};
extern const TargetRegisterClass VK16PAIR_with_sub_mask_0_in_VK16WMRegClass = {
&X86MCRegisterClasses[VK16PAIR_with_sub_mask_0_in_VK16WMRegClassID],
VK16PAIR_with_sub_mask_0_in_VK16WMSubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x0000000000000030),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
true, /* CoveredBySubRegs */
VK16PAIR_with_sub_mask_0_in_VK16WMSuperclasses,
nullptr
};
extern const TargetRegisterClass FR32XRegClass = {
&X86MCRegisterClasses[FR32XRegClassID],
FR32XSubClassMask,
SuperRegIdxSeqs + 12,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
FR32XSuperclasses,
nullptr
};
extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBPRegClass = {
&X86MCRegisterClasses[LOW32_ADDR_ACCESS_RBPRegClassID],
LOW32_ADDR_ACCESS_RBPSubClassMask,
SuperRegIdxSeqs + 7,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
NullRegClasses,
nullptr
};
extern const TargetRegisterClass LOW32_ADDR_ACCESSRegClass = {
&X86MCRegisterClasses[LOW32_ADDR_ACCESSRegClassID],
LOW32_ADDR_ACCESSSubClassMask,
SuperRegIdxSeqs + 7,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
LOW32_ADDR_ACCESSSuperclasses,
nullptr
};
extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass = {
&X86MCRegisterClasses[LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID],
LOW32_ADDR_ACCESS_RBP_with_sub_8bitSubClassMask,
SuperRegIdxSeqs + 7,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
LOW32_ADDR_ACCESS_RBP_with_sub_8bitSuperclasses,
nullptr
};
extern const TargetRegisterClass DEBUG_REGRegClass = {
&X86MCRegisterClasses[DEBUG_REGRegClassID],
DEBUG_REGSubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
NullRegClasses,
nullptr
};
extern const TargetRegisterClass FR32RegClass = {
&X86MCRegisterClasses[FR32RegClassID],
FR32SubClassMask,
SuperRegIdxSeqs + 12,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
FR32Superclasses,
nullptr
};
extern const TargetRegisterClass GR32RegClass = {
&X86MCRegisterClasses[GR32RegClassID],
GR32SubClassMask,
SuperRegIdxSeqs + 7,
LaneBitmask(0x0000000000000007),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
true, /* CoveredBySubRegs */
GR32Superclasses,
nullptr
};
extern const TargetRegisterClass GR32_NOSPRegClass = {
&X86MCRegisterClasses[GR32_NOSPRegClassID],
GR32_NOSPSubClassMask,
SuperRegIdxSeqs + 7,
LaneBitmask(0x0000000000000007),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
true, /* CoveredBySubRegs */
GR32_NOSPSuperclasses,
nullptr
};
extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass = {
&X86MCRegisterClasses[LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID],
LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXSubClassMask,
SuperRegIdxSeqs + 7,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXSuperclasses,
nullptr
};
extern const TargetRegisterClass GR32_NOREXRegClass = {
&X86MCRegisterClasses[GR32_NOREXRegClassID],
GR32_NOREXSubClassMask,
SuperRegIdxSeqs + 7,
LaneBitmask(0x0000000000000007),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
true, /* CoveredBySubRegs */
GR32_NOREXSuperclasses,
nullptr
};
extern const TargetRegisterClass VK32RegClass = {
&X86MCRegisterClasses[VK32RegClassID],
VK32SubClassMask,
SuperRegIdxSeqs + 9,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
VK32Superclasses,
nullptr
};
extern const TargetRegisterClass GR32_NOREX_NOSPRegClass = {
&X86MCRegisterClasses[GR32_NOREX_NOSPRegClassID],
GR32_NOREX_NOSPSubClassMask,
SuperRegIdxSeqs + 7,
LaneBitmask(0x0000000000000007),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
true, /* CoveredBySubRegs */
GR32_NOREX_NOSPSuperclasses,
nullptr
};
extern const TargetRegisterClass RFP32RegClass = {
&X86MCRegisterClasses[RFP32RegClassID],
RFP32SubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
NullRegClasses,
nullptr
};
extern const TargetRegisterClass VK32WMRegClass = {
&X86MCRegisterClasses[VK32WMRegClassID],
VK32WMSubClassMask,
SuperRegIdxSeqs + 9,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
VK32WMSuperclasses,
nullptr
};
extern const TargetRegisterClass GR32_ABCDRegClass = {
&X86MCRegisterClasses[GR32_ABCDRegClassID],
GR32_ABCDSubClassMask,
SuperRegIdxSeqs + 7,
LaneBitmask(0x0000000000000007),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
true, /* CoveredBySubRegs */
GR32_ABCDSuperclasses,
nullptr
};
extern const TargetRegisterClass GR32_TCRegClass = {
&X86MCRegisterClasses[GR32_TCRegClassID],
GR32_TCSubClassMask,
SuperRegIdxSeqs + 7,
LaneBitmask(0x0000000000000007),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
true, /* CoveredBySubRegs */
GR32_TCSuperclasses,
nullptr
};
extern const TargetRegisterClass GR32_ABCD_and_GR32_TCRegClass = {
&X86MCRegisterClasses[GR32_ABCD_and_GR32_TCRegClassID],
GR32_ABCD_and_GR32_TCSubClassMask,
SuperRegIdxSeqs + 7,
LaneBitmask(0x0000000000000007),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
true, /* CoveredBySubRegs */
GR32_ABCD_and_GR32_TCSuperclasses,
nullptr
};
extern const TargetRegisterClass GR32_ADRegClass = {
&X86MCRegisterClasses[GR32_ADRegClassID],
GR32_ADSubClassMask,
SuperRegIdxSeqs + 7,
LaneBitmask(0x0000000000000007),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
true, /* CoveredBySubRegs */
GR32_ADSuperclasses,
nullptr
};
extern const TargetRegisterClass GR32_BPSPRegClass = {
&X86MCRegisterClasses[GR32_BPSPRegClassID],
GR32_BPSPSubClassMask,
SuperRegIdxSeqs + 7,
LaneBitmask(0x0000000000000007),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
true, /* CoveredBySubRegs */
GR32_BPSPSuperclasses,
nullptr
};
extern const TargetRegisterClass GR32_BSIRegClass = {
&X86MCRegisterClasses[GR32_BSIRegClassID],
GR32_BSISubClassMask,
SuperRegIdxSeqs + 7,
LaneBitmask(0x0000000000000007),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
true, /* CoveredBySubRegs */
GR32_BSISuperclasses,
nullptr
};
extern const TargetRegisterClass GR32_CBRegClass = {
&X86MCRegisterClasses[GR32_CBRegClassID],
GR32_CBSubClassMask,
SuperRegIdxSeqs + 7,
LaneBitmask(0x0000000000000007),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
true, /* CoveredBySubRegs */
GR32_CBSuperclasses,
nullptr
};
extern const TargetRegisterClass GR32_DCRegClass = {
&X86MCRegisterClasses[GR32_DCRegClassID],
GR32_DCSubClassMask,
SuperRegIdxSeqs + 7,
LaneBitmask(0x0000000000000007),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
true, /* CoveredBySubRegs */
GR32_DCSuperclasses,
nullptr
};
extern const TargetRegisterClass GR32_DIBPRegClass = {
&X86MCRegisterClasses[GR32_DIBPRegClassID],
GR32_DIBPSubClassMask,
SuperRegIdxSeqs + 7,
LaneBitmask(0x0000000000000007),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
true, /* CoveredBySubRegs */
GR32_DIBPSuperclasses,
nullptr
};
extern const TargetRegisterClass GR32_SIDIRegClass = {
&X86MCRegisterClasses[GR32_SIDIRegClassID],
GR32_SIDISubClassMask,
SuperRegIdxSeqs + 7,
LaneBitmask(0x0000000000000007),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
true, /* CoveredBySubRegs */
GR32_SIDISuperclasses,
nullptr
};
extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClass = {
&X86MCRegisterClasses[LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClassID],
LOW32_ADDR_ACCESS_RBP_with_sub_32bitSubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
LOW32_ADDR_ACCESS_RBP_with_sub_32bitSuperclasses,
nullptr
};
extern const TargetRegisterClass CCRRegClass = {
&X86MCRegisterClasses[CCRRegClassID],
CCRSubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
NullRegClasses,
nullptr
};
extern const TargetRegisterClass DFCCRRegClass = {
&X86MCRegisterClasses[DFCCRRegClassID],
DFCCRSubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
NullRegClasses,
nullptr
};
extern const TargetRegisterClass GR32_ABCD_and_GR32_BSIRegClass = {
&X86MCRegisterClasses[GR32_ABCD_and_GR32_BSIRegClassID],
GR32_ABCD_and_GR32_BSISubClassMask,
SuperRegIdxSeqs + 7,
LaneBitmask(0x0000000000000007),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
true, /* CoveredBySubRegs */
GR32_ABCD_and_GR32_BSISuperclasses,
nullptr
};
extern const TargetRegisterClass GR32_AD_and_GR32_DCRegClass = {
&X86MCRegisterClasses[GR32_AD_and_GR32_DCRegClassID],
GR32_AD_and_GR32_DCSubClassMask,
SuperRegIdxSeqs + 7,
LaneBitmask(0x0000000000000007),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
true, /* CoveredBySubRegs */
GR32_AD_and_GR32_DCSuperclasses,
nullptr
};
extern const TargetRegisterClass GR32_BPSP_and_GR32_DIBPRegClass = {
&X86MCRegisterClasses[GR32_BPSP_and_GR32_DIBPRegClassID],
GR32_BPSP_and_GR32_DIBPSubClassMask,
SuperRegIdxSeqs + 7,
LaneBitmask(0x0000000000000007),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
true, /* CoveredBySubRegs */
GR32_BPSP_and_GR32_DIBPSuperclasses,
nullptr
};
extern const TargetRegisterClass GR32_BPSP_and_GR32_TCRegClass = {
&X86MCRegisterClasses[GR32_BPSP_and_GR32_TCRegClassID],
GR32_BPSP_and_GR32_TCSubClassMask,
SuperRegIdxSeqs + 7,
LaneBitmask(0x0000000000000007),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
true, /* CoveredBySubRegs */
GR32_BPSP_and_GR32_TCSuperclasses,
nullptr
};
extern const TargetRegisterClass GR32_BSI_and_GR32_SIDIRegClass = {
&X86MCRegisterClasses[GR32_BSI_and_GR32_SIDIRegClassID],
GR32_BSI_and_GR32_SIDISubClassMask,
SuperRegIdxSeqs + 7,
LaneBitmask(0x0000000000000007),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
true, /* CoveredBySubRegs */
GR32_BSI_and_GR32_SIDISuperclasses,
nullptr
};
extern const TargetRegisterClass GR32_CB_and_GR32_DCRegClass = {
&X86MCRegisterClasses[GR32_CB_and_GR32_DCRegClassID],
GR32_CB_and_GR32_DCSubClassMask,
SuperRegIdxSeqs + 7,
LaneBitmask(0x0000000000000007),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
true, /* CoveredBySubRegs */
GR32_CB_and_GR32_DCSuperclasses,
nullptr
};
extern const TargetRegisterClass GR32_DIBP_and_GR32_SIDIRegClass = {
&X86MCRegisterClasses[GR32_DIBP_and_GR32_SIDIRegClassID],
GR32_DIBP_and_GR32_SIDISubClassMask,
SuperRegIdxSeqs + 7,
LaneBitmask(0x0000000000000007),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
true, /* CoveredBySubRegs */
GR32_DIBP_and_GR32_SIDISuperclasses,
nullptr
};
extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitRegClass = {
&X86MCRegisterClasses[LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitRegClassID],
LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitSubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitSuperclasses,
nullptr
};
extern const TargetRegisterClass LOW32_ADDR_ACCESS_with_sub_32bitRegClass = {
&X86MCRegisterClasses[LOW32_ADDR_ACCESS_with_sub_32bitRegClassID],
LOW32_ADDR_ACCESS_with_sub_32bitSubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
LOW32_ADDR_ACCESS_with_sub_32bitSuperclasses,
nullptr
};
extern const TargetRegisterClass RFP64RegClass = {
&X86MCRegisterClasses[RFP64RegClassID],
RFP64SubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
RFP64Superclasses,
nullptr
};
extern const TargetRegisterClass FR64XRegClass = {
&X86MCRegisterClasses[FR64XRegClassID],
FR64XSubClassMask,
SuperRegIdxSeqs + 12,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
FR64XSuperclasses,
nullptr
};
extern const TargetRegisterClass GR64RegClass = {
&X86MCRegisterClasses[GR64RegClassID],
GR64SubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
NullRegClasses,
nullptr
};
extern const TargetRegisterClass CONTROL_REGRegClass = {
&X86MCRegisterClasses[CONTROL_REGRegClassID],
CONTROL_REGSubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
NullRegClasses,
nullptr
};
extern const TargetRegisterClass FR64RegClass = {
&X86MCRegisterClasses[FR64RegClassID],
FR64SubClassMask,
SuperRegIdxSeqs + 12,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
FR64Superclasses,
nullptr
};
extern const TargetRegisterClass GR64_with_sub_8bitRegClass = {
&X86MCRegisterClasses[GR64_with_sub_8bitRegClassID],
GR64_with_sub_8bitSubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
GR64_with_sub_8bitSuperclasses,
nullptr
};
extern const TargetRegisterClass GR64_NOSPRegClass = {
&X86MCRegisterClasses[GR64_NOSPRegClassID],
GR64_NOSPSubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
GR64_NOSPSuperclasses,
nullptr
};
extern const TargetRegisterClass GR64PLTSafeRegClass = {
&X86MCRegisterClasses[GR64PLTSafeRegClassID],
GR64PLTSafeSubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
GR64PLTSafeSuperclasses,
nullptr
};
extern const TargetRegisterClass GR64_TCRegClass = {
&X86MCRegisterClasses[GR64_TCRegClassID],
GR64_TCSubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
GR64_TCSuperclasses,
nullptr
};
extern const TargetRegisterClass GR64_NOREXRegClass = {
&X86MCRegisterClasses[GR64_NOREXRegClassID],
GR64_NOREXSubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
GR64_NOREXSuperclasses,
nullptr
};
extern const TargetRegisterClass GR64_TCW64RegClass = {
&X86MCRegisterClasses[GR64_TCW64RegClassID],
GR64_TCW64SubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
GR64_TCW64Superclasses,
nullptr
};
extern const TargetRegisterClass GR64_TC_with_sub_8bitRegClass = {
&X86MCRegisterClasses[GR64_TC_with_sub_8bitRegClassID],
GR64_TC_with_sub_8bitSubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
GR64_TC_with_sub_8bitSuperclasses,
nullptr
};
extern const TargetRegisterClass GR64_NOSP_and_GR64_TCRegClass = {
&X86MCRegisterClasses[GR64_NOSP_and_GR64_TCRegClassID],
GR64_NOSP_and_GR64_TCSubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
GR64_NOSP_and_GR64_TCSuperclasses,
nullptr
};
extern const TargetRegisterClass GR64_TCW64_with_sub_8bitRegClass = {
&X86MCRegisterClasses[GR64_TCW64_with_sub_8bitRegClassID],
GR64_TCW64_with_sub_8bitSubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
GR64_TCW64_with_sub_8bitSuperclasses,
nullptr
};
extern const TargetRegisterClass GR64_TC_and_GR64_TCW64RegClass = {
&X86MCRegisterClasses[GR64_TC_and_GR64_TCW64RegClassID],
GR64_TC_and_GR64_TCW64SubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
GR64_TC_and_GR64_TCW64Superclasses,
nullptr
};
extern const TargetRegisterClass GR64_with_sub_16bit_in_GR16_NOREXRegClass = {
&X86MCRegisterClasses[GR64_with_sub_16bit_in_GR16_NOREXRegClassID],
GR64_with_sub_16bit_in_GR16_NOREXSubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
GR64_with_sub_16bit_in_GR16_NOREXSuperclasses,
nullptr
};
extern const TargetRegisterClass VK64RegClass = {
&X86MCRegisterClasses[VK64RegClassID],
VK64SubClassMask,
SuperRegIdxSeqs + 9,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
VK64Superclasses,
nullptr
};
extern const TargetRegisterClass VR64RegClass = {
&X86MCRegisterClasses[VR64RegClassID],
VR64SubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
NullRegClasses,
nullptr
};
extern const TargetRegisterClass GR64PLTSafe_and_GR64_TCRegClass = {
&X86MCRegisterClasses[GR64PLTSafe_and_GR64_TCRegClassID],
GR64PLTSafe_and_GR64_TCSubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
GR64PLTSafe_and_GR64_TCSuperclasses,
nullptr
};
extern const TargetRegisterClass GR64_NOREX_NOSPRegClass = {
&X86MCRegisterClasses[GR64_NOREX_NOSPRegClassID],
GR64_NOREX_NOSPSubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
GR64_NOREX_NOSPSuperclasses,
nullptr
};
extern const TargetRegisterClass GR64_NOREX_and_GR64_TCRegClass = {
&X86MCRegisterClasses[GR64_NOREX_and_GR64_TCRegClassID],
GR64_NOREX_and_GR64_TCSubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
GR64_NOREX_and_GR64_TCSuperclasses,
nullptr
};
extern const TargetRegisterClass GR64_NOSP_and_GR64_TCW64RegClass = {
&X86MCRegisterClasses[GR64_NOSP_and_GR64_TCW64RegClassID],
GR64_NOSP_and_GR64_TCW64SubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
GR64_NOSP_and_GR64_TCW64Superclasses,
nullptr
};
extern const TargetRegisterClass GR64_TCW64_and_GR64_TC_with_sub_8bitRegClass = {
&X86MCRegisterClasses[GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID],
GR64_TCW64_and_GR64_TC_with_sub_8bitSubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
GR64_TCW64_and_GR64_TC_with_sub_8bitSuperclasses,
nullptr
};
extern const TargetRegisterClass VK64WMRegClass = {
&X86MCRegisterClasses[VK64WMRegClassID],
VK64WMSubClassMask,
SuperRegIdxSeqs + 9,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
VK64WMSuperclasses,
nullptr
};
extern const TargetRegisterClass GR64_TC_and_GR64_NOSP_and_GR64_TCW64RegClass = {
&X86MCRegisterClasses[GR64_TC_and_GR64_NOSP_and_GR64_TCW64RegClassID],
GR64_TC_and_GR64_NOSP_and_GR64_TCW64SubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
GR64_TC_and_GR64_NOSP_and_GR64_TCW64Superclasses,
nullptr
};
extern const TargetRegisterClass GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClass = {
&X86MCRegisterClasses[GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID],
GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXSubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXSuperclasses,
nullptr
};
extern const TargetRegisterClass GR64PLTSafe_and_GR64_TCW64RegClass = {
&X86MCRegisterClasses[GR64PLTSafe_and_GR64_TCW64RegClassID],
GR64PLTSafe_and_GR64_TCW64SubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
GR64PLTSafe_and_GR64_TCW64Superclasses,
nullptr
};
extern const TargetRegisterClass GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClass = {
&X86MCRegisterClasses[GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClassID],
GR64_NOREX_and_GR64PLTSafe_and_GR64_TCSubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
GR64_NOREX_and_GR64PLTSafe_and_GR64_TCSuperclasses,
nullptr
};
extern const TargetRegisterClass GR64_NOREX_and_GR64_TCW64RegClass = {
&X86MCRegisterClasses[GR64_NOREX_and_GR64_TCW64RegClassID],
GR64_NOREX_and_GR64_TCW64SubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
GR64_NOREX_and_GR64_TCW64Superclasses,
nullptr
};
extern const TargetRegisterClass GR64_ABCDRegClass = {
&X86MCRegisterClasses[GR64_ABCDRegClassID],
GR64_ABCDSubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
GR64_ABCDSuperclasses,
nullptr
};
extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_TCRegClass = {
&X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_TCRegClassID],
GR64_with_sub_32bit_in_GR32_TCSubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
GR64_with_sub_32bit_in_GR32_TCSuperclasses,
nullptr
};
extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClass = {
&X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClassID],
GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCSubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCSuperclasses,
nullptr
};
extern const TargetRegisterClass GR64_ADRegClass = {
&X86MCRegisterClasses[GR64_ADRegClassID],
GR64_ADSubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
GR64_ADSuperclasses,
nullptr
};
extern const TargetRegisterClass GR64_and_LOW32_ADDR_ACCESS_RBPRegClass = {
&X86MCRegisterClasses[GR64_and_LOW32_ADDR_ACCESS_RBPRegClassID],
GR64_and_LOW32_ADDR_ACCESS_RBPSubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
GR64_and_LOW32_ADDR_ACCESS_RBPSuperclasses,
nullptr
};
extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BPSPRegClass = {
&X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_BPSPRegClassID],
GR64_with_sub_32bit_in_GR32_BPSPSubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
GR64_with_sub_32bit_in_GR32_BPSPSuperclasses,
nullptr
};
extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BSIRegClass = {
&X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_BSIRegClassID],
GR64_with_sub_32bit_in_GR32_BSISubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
GR64_with_sub_32bit_in_GR32_BSISuperclasses,
nullptr
};
extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_CBRegClass = {
&X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_CBRegClassID],
GR64_with_sub_32bit_in_GR32_CBSubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
GR64_with_sub_32bit_in_GR32_CBSuperclasses,
nullptr
};
extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_DCRegClass = {
&X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_DCRegClassID],
GR64_with_sub_32bit_in_GR32_DCSubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
GR64_with_sub_32bit_in_GR32_DCSuperclasses,
nullptr
};
extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_DIBPRegClass = {
&X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_DIBPRegClassID],
GR64_with_sub_32bit_in_GR32_DIBPSubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
GR64_with_sub_32bit_in_GR32_DIBPSuperclasses,
nullptr
};
extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_SIDIRegClass = {
&X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_SIDIRegClassID],
GR64_with_sub_32bit_in_GR32_SIDISubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
GR64_with_sub_32bit_in_GR32_SIDISuperclasses,
nullptr
};
extern const TargetRegisterClass GR64_and_LOW32_ADDR_ACCESSRegClass = {
&X86MCRegisterClasses[GR64_and_LOW32_ADDR_ACCESSRegClassID],
GR64_and_LOW32_ADDR_ACCESSSubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
GR64_and_LOW32_ADDR_ACCESSSuperclasses,
nullptr
};
extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIRegClass = {
&X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIRegClassID],
GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSISubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSISuperclasses,
nullptr
};
extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_AD_and_GR32_DCRegClass = {
&X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_AD_and_GR32_DCRegClassID],
GR64_with_sub_32bit_in_GR32_AD_and_GR32_DCSubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
GR64_with_sub_32bit_in_GR32_AD_and_GR32_DCSuperclasses,
nullptr
};
extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPRegClass = {
&X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPRegClassID],
GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPSubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPSuperclasses,
nullptr
};
extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCRegClass = {
&X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCRegClassID],
GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCSubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCSuperclasses,
nullptr
};
extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIRegClass = {
&X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIRegClassID],
GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDISubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDISuperclasses,
nullptr
};
extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_CB_and_GR32_DCRegClass = {
&X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_CB_and_GR32_DCRegClassID],
GR64_with_sub_32bit_in_GR32_CB_and_GR32_DCSubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
GR64_with_sub_32bit_in_GR32_CB_and_GR32_DCSuperclasses,
nullptr
};
extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIRegClass = {
&X86MCRegisterClasses[GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIRegClassID],
GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDISubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x000000000000000F),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDISuperclasses,
nullptr
};
extern const TargetRegisterClass RSTRegClass = {
&X86MCRegisterClasses[RSTRegClassID],
RSTSubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
NullRegClasses,
nullptr
};
extern const TargetRegisterClass RFP80RegClass = {
&X86MCRegisterClasses[RFP80RegClassID],
RFP80SubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
RFP80Superclasses,
nullptr
};
extern const TargetRegisterClass RFP80_7RegClass = {
&X86MCRegisterClasses[RFP80_7RegClassID],
RFP80_7SubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
NullRegClasses,
nullptr
};
extern const TargetRegisterClass VR128XRegClass = {
&X86MCRegisterClasses[VR128XRegClassID],
VR128XSubClassMask,
SuperRegIdxSeqs + 12,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
VR128XSuperclasses,
nullptr
};
extern const TargetRegisterClass VR128RegClass = {
&X86MCRegisterClasses[VR128RegClassID],
VR128SubClassMask,
SuperRegIdxSeqs + 12,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
VR128Superclasses,
nullptr
};
extern const TargetRegisterClass VR256XRegClass = {
&X86MCRegisterClasses[VR256XRegClassID],
VR256XSubClassMask,
SuperRegIdxSeqs + 14,
LaneBitmask(0x0000000000000040),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
NullRegClasses,
nullptr
};
extern const TargetRegisterClass VR256RegClass = {
&X86MCRegisterClasses[VR256RegClassID],
VR256SubClassMask,
SuperRegIdxSeqs + 14,
LaneBitmask(0x0000000000000040),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
VR256Superclasses,
nullptr
};
extern const TargetRegisterClass VR512RegClass = {
&X86MCRegisterClasses[VR512RegClassID],
VR512SubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x0000000000000040),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
NullRegClasses,
nullptr
};
extern const TargetRegisterClass VR512_0_15RegClass = {
&X86MCRegisterClasses[VR512_0_15RegClassID],
VR512_0_15SubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x0000000000000040),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
VR512_0_15Superclasses,
nullptr
};
extern const TargetRegisterClass TILERegClass = {
&X86MCRegisterClasses[TILERegClassID],
TILESubClassMask,
SuperRegIdxSeqs + 1,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
NullRegClasses,
nullptr
};
} // end namespace X86
namespace {
const TargetRegisterClass *const RegisterClasses[] = {
&X86::GR8RegClass,
&X86::GRH8RegClass,
&X86::GR8_NOREXRegClass,
&X86::GR8_ABCD_HRegClass,
&X86::GR8_ABCD_LRegClass,
&X86::GRH16RegClass,
&X86::GR16RegClass,
&X86::GR16_NOREXRegClass,
&X86::VK1RegClass,
&X86::VK16RegClass,
&X86::VK2RegClass,
&X86::VK4RegClass,
&X86::VK8RegClass,
&X86::VK16WMRegClass,
&X86::VK1WMRegClass,
&X86::VK2WMRegClass,
&X86::VK4WMRegClass,
&X86::VK8WMRegClass,
&X86::SEGMENT_REGRegClass,
&X86::GR16_ABCDRegClass,
&X86::FPCCRRegClass,
&X86::FR16XRegClass,
&X86::FR16RegClass,
&X86::VK16PAIRRegClass,
&X86::VK1PAIRRegClass,
&X86::VK2PAIRRegClass,
&X86::VK4PAIRRegClass,
&X86::VK8PAIRRegClass,
&X86::VK16PAIR_with_sub_mask_0_in_VK16WMRegClass,
&X86::FR32XRegClass,
&X86::LOW32_ADDR_ACCESS_RBPRegClass,
&X86::LOW32_ADDR_ACCESSRegClass,
&X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass,
&X86::DEBUG_REGRegClass,
&X86::FR32RegClass,
&X86::GR32RegClass,
&X86::GR32_NOSPRegClass,
&X86::LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass,
&X86::GR32_NOREXRegClass,
&X86::VK32RegClass,
&X86::GR32_NOREX_NOSPRegClass,
&X86::RFP32RegClass,
&X86::VK32WMRegClass,
&X86::GR32_ABCDRegClass,
&X86::GR32_TCRegClass,
&X86::GR32_ABCD_and_GR32_TCRegClass,
&X86::GR32_ADRegClass,
&X86::GR32_BPSPRegClass,
&X86::GR32_BSIRegClass,
&X86::GR32_CBRegClass,
&X86::GR32_DCRegClass,
&X86::GR32_DIBPRegClass,
&X86::GR32_SIDIRegClass,
&X86::LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClass,
&X86::CCRRegClass,
&X86::DFCCRRegClass,
&X86::GR32_ABCD_and_GR32_BSIRegClass,
&X86::GR32_AD_and_GR32_DCRegClass,
&X86::GR32_BPSP_and_GR32_DIBPRegClass,
&X86::GR32_BPSP_and_GR32_TCRegClass,
&X86::GR32_BSI_and_GR32_SIDIRegClass,
&X86::GR32_CB_and_GR32_DCRegClass,
&X86::GR32_DIBP_and_GR32_SIDIRegClass,
&X86::LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitRegClass,
&X86::LOW32_ADDR_ACCESS_with_sub_32bitRegClass,
&X86::RFP64RegClass,
&X86::FR64XRegClass,
&X86::GR64RegClass,
&X86::CONTROL_REGRegClass,
&X86::FR64RegClass,
&X86::GR64_with_sub_8bitRegClass,
&X86::GR64_NOSPRegClass,
&X86::GR64PLTSafeRegClass,
&X86::GR64_TCRegClass,
&X86::GR64_NOREXRegClass,
&X86::GR64_TCW64RegClass,
&X86::GR64_TC_with_sub_8bitRegClass,
&X86::GR64_NOSP_and_GR64_TCRegClass,
&X86::GR64_TCW64_with_sub_8bitRegClass,
&X86::GR64_TC_and_GR64_TCW64RegClass,
&X86::GR64_with_sub_16bit_in_GR16_NOREXRegClass,
&X86::VK64RegClass,
&X86::VR64RegClass,
&X86::GR64PLTSafe_and_GR64_TCRegClass,
&X86::GR64_NOREX_NOSPRegClass,
&X86::GR64_NOREX_and_GR64_TCRegClass,
&X86::GR64_NOSP_and_GR64_TCW64RegClass,
&X86::GR64_TCW64_and_GR64_TC_with_sub_8bitRegClass,
&X86::VK64WMRegClass,
&X86::GR64_TC_and_GR64_NOSP_and_GR64_TCW64RegClass,
&X86::GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClass,
&X86::GR64PLTSafe_and_GR64_TCW64RegClass,
&X86::GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClass,
&X86::GR64_NOREX_and_GR64_TCW64RegClass,
&X86::GR64_ABCDRegClass,
&X86::GR64_with_sub_32bit_in_GR32_TCRegClass,
&X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClass,
&X86::GR64_ADRegClass,
&X86::GR64_and_LOW32_ADDR_ACCESS_RBPRegClass,
&X86::GR64_with_sub_32bit_in_GR32_BPSPRegClass,
&X86::GR64_with_sub_32bit_in_GR32_BSIRegClass,
&X86::GR64_with_sub_32bit_in_GR32_CBRegClass,
&X86::GR64_with_sub_32bit_in_GR32_DCRegClass,
&X86::GR64_with_sub_32bit_in_GR32_DIBPRegClass,
&X86::GR64_with_sub_32bit_in_GR32_SIDIRegClass,
&X86::GR64_and_LOW32_ADDR_ACCESSRegClass,
&X86::GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIRegClass,
&X86::GR64_with_sub_32bit_in_GR32_AD_and_GR32_DCRegClass,
&X86::GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPRegClass,
&X86::GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCRegClass,
&X86::GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIRegClass,
&X86::GR64_with_sub_32bit_in_GR32_CB_and_GR32_DCRegClass,
&X86::GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIRegClass,
&X86::RSTRegClass,
&X86::RFP80RegClass,
&X86::RFP80_7RegClass,
&X86::VR128XRegClass,
&X86::VR128RegClass,
&X86::VR256XRegClass,
&X86::VR256RegClass,
&X86::VR512RegClass,
&X86::VR512_0_15RegClass,
&X86::TILERegClass,
};
} // end anonymous namespace
static const uint8_t CostPerUseTable[] = {
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
static const bool InAllocatableClassTable[] = {
false, true, true, true, true, true, true, false, true, true, true, true, true, true, false, true, true, false, true, true, true, true, true, true, true, true, true, true, false, false, false, true, true, true, false, false, true, false, true, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, false, true, false, true, true, true, false, true, true, false, true, true, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, true, true, true, true, };
static const TargetRegisterInfoDesc X86RegInfoDesc = { // Extra Descriptors
CostPerUseTable, 1, InAllocatableClassTable};
unsigned X86GenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
static const uint8_t Rows[1][10] = {
{ X86::sub_8bit, X86::sub_8bit_hi, X86::sub_8bit_hi_phony, X86::sub_16bit, X86::sub_16bit_hi, 0, 0, 0, X86::sub_xmm, 0, },
};
--IdxA; assert(IdxA < 10); (void) IdxA;
--IdxB; assert(IdxB < 10);
return Rows[0][IdxB];
}
struct MaskRolOp {
LaneBitmask Mask;
uint8_t RotateLeft;
};
static const MaskRolOp LaneMaskComposeSequences[] = {
{ LaneBitmask(0xFFFFFFFFFFFFFFFF), 0 }, { LaneBitmask::getNone(), 0 }, // Sequence 0
{ LaneBitmask(0xFFFFFFFFFFFFFFFF), 1 }, { LaneBitmask::getNone(), 0 }, // Sequence 2
{ LaneBitmask(0xFFFFFFFFFFFFFFFF), 2 }, { LaneBitmask::getNone(), 0 }, // Sequence 4
{ LaneBitmask(0xFFFFFFFFFFFFFFFF), 3 }, { LaneBitmask::getNone(), 0 }, // Sequence 6
{ LaneBitmask(0xFFFFFFFFFFFFFFFF), 4 }, { LaneBitmask::getNone(), 0 }, // Sequence 8
{ LaneBitmask(0xFFFFFFFFFFFFFFFF), 5 }, { LaneBitmask::getNone(), 0 }, // Sequence 10
{ LaneBitmask(0xFFFFFFFFFFFFFFFF), 6 }, { LaneBitmask::getNone(), 0 } // Sequence 12
};
static const uint8_t CompositeSequences[] = {
0, // to sub_8bit
2, // to sub_8bit_hi
4, // to sub_8bit_hi_phony
0, // to sub_16bit
6, // to sub_16bit_hi
0, // to sub_32bit
8, // to sub_mask_0
10, // to sub_mask_1
12, // to sub_xmm
0 // to sub_ymm
};
LaneBitmask X86GenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
--IdxA; assert(IdxA < 10 && "Subregister index out of bounds");
LaneBitmask Result;
for (const MaskRolOp *Ops =
&LaneMaskComposeSequences[CompositeSequences[IdxA]];
Ops->Mask.any(); ++Ops) {
LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
if (unsigned S = Ops->RotateLeft)
Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
else
Result |= LaneBitmask(M);
}
return Result;
}
LaneBitmask X86GenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
LaneMask &= getSubRegIndexLaneMask(IdxA);
--IdxA; assert(IdxA < 10 && "Subregister index out of bounds");
LaneBitmask Result;
for (const MaskRolOp *Ops =
&LaneMaskComposeSequences[CompositeSequences[IdxA]];
Ops->Mask.any(); ++Ops) {
LaneBitmask::Type M = LaneMask.getAsInteger();
if (unsigned S = Ops->RotateLeft)
Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
else
Result |= LaneBitmask(M);
}
return Result;
}
const TargetRegisterClass *X86GenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
static const uint8_t Table[123][10] = {
{ // GR8
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // GRH8
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // GR8_NOREX
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // GR8_ABCD_H
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // GR8_ABCD_L
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // GRH16
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // GR16
7, // sub_8bit -> GR16
20, // sub_8bit_hi -> GR16_ABCD
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // GR16_NOREX
8, // sub_8bit -> GR16_NOREX
20, // sub_8bit_hi -> GR16_ABCD
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // VK1
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // VK16
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // VK2
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // VK4
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // VK8
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // VK16WM
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // VK1WM
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // VK2WM
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // VK4WM
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // VK8WM
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // SEGMENT_REG
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // GR16_ABCD
20, // sub_8bit -> GR16_ABCD
20, // sub_8bit_hi -> GR16_ABCD
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // FPCCR
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // FR16X
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // FR16
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // VK16PAIR
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
24, // sub_mask_0 -> VK16PAIR
24, // sub_mask_1 -> VK16PAIR
0, // sub_xmm
0, // sub_ymm
},
{ // VK1PAIR
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
25, // sub_mask_0 -> VK1PAIR
25, // sub_mask_1 -> VK1PAIR
0, // sub_xmm
0, // sub_ymm
},
{ // VK2PAIR
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
26, // sub_mask_0 -> VK2PAIR
26, // sub_mask_1 -> VK2PAIR
0, // sub_xmm
0, // sub_ymm
},
{ // VK4PAIR
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
27, // sub_mask_0 -> VK4PAIR
27, // sub_mask_1 -> VK4PAIR
0, // sub_xmm
0, // sub_ymm
},
{ // VK8PAIR
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
28, // sub_mask_0 -> VK8PAIR
28, // sub_mask_1 -> VK8PAIR
0, // sub_xmm
0, // sub_ymm
},
{ // VK16PAIR_with_sub_mask_0_in_VK16WM
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
29, // sub_mask_0 -> VK16PAIR_with_sub_mask_0_in_VK16WM
29, // sub_mask_1 -> VK16PAIR_with_sub_mask_0_in_VK16WM
0, // sub_xmm
0, // sub_ymm
},
{ // FR32X
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // LOW32_ADDR_ACCESS_RBP
33, // sub_8bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit
44, // sub_8bit_hi -> GR32_ABCD
0, // sub_8bit_hi_phony
31, // sub_16bit -> LOW32_ADDR_ACCESS_RBP
0, // sub_16bit_hi
54, // sub_32bit -> LOW32_ADDR_ACCESS_RBP_with_sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // LOW32_ADDR_ACCESS
36, // sub_8bit -> GR32
44, // sub_8bit_hi -> GR32_ABCD
0, // sub_8bit_hi_phony
32, // sub_16bit -> LOW32_ADDR_ACCESS
0, // sub_16bit_hi
65, // sub_32bit -> LOW32_ADDR_ACCESS_with_sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // LOW32_ADDR_ACCESS_RBP_with_sub_8bit
33, // sub_8bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit
44, // sub_8bit_hi -> GR32_ABCD
0, // sub_8bit_hi_phony
33, // sub_16bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit
0, // sub_16bit_hi
64, // sub_32bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // DEBUG_REG
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // FR32
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // GR32
36, // sub_8bit -> GR32
44, // sub_8bit_hi -> GR32_ABCD
0, // sub_8bit_hi_phony
36, // sub_16bit -> GR32
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // GR32_NOSP
37, // sub_8bit -> GR32_NOSP
44, // sub_8bit_hi -> GR32_ABCD
0, // sub_8bit_hi_phony
37, // sub_16bit -> GR32_NOSP
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX
38, // sub_8bit -> LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX
44, // sub_8bit_hi -> GR32_ABCD
0, // sub_8bit_hi_phony
38, // sub_16bit -> LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX
0, // sub_16bit_hi
64, // sub_32bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // GR32_NOREX
39, // sub_8bit -> GR32_NOREX
44, // sub_8bit_hi -> GR32_ABCD
0, // sub_8bit_hi_phony
39, // sub_16bit -> GR32_NOREX
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // VK32
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // GR32_NOREX_NOSP
41, // sub_8bit -> GR32_NOREX_NOSP
44, // sub_8bit_hi -> GR32_ABCD
0, // sub_8bit_hi_phony
41, // sub_16bit -> GR32_NOREX_NOSP
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // RFP32
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // VK32WM
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // GR32_ABCD
44, // sub_8bit -> GR32_ABCD
44, // sub_8bit_hi -> GR32_ABCD
0, // sub_8bit_hi_phony
44, // sub_16bit -> GR32_ABCD
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // GR32_TC
45, // sub_8bit -> GR32_TC
46, // sub_8bit_hi -> GR32_ABCD_and_GR32_TC
0, // sub_8bit_hi_phony
45, // sub_16bit -> GR32_TC
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // GR32_ABCD_and_GR32_TC
46, // sub_8bit -> GR32_ABCD_and_GR32_TC
46, // sub_8bit_hi -> GR32_ABCD_and_GR32_TC
0, // sub_8bit_hi_phony
46, // sub_16bit -> GR32_ABCD_and_GR32_TC
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // GR32_AD
47, // sub_8bit -> GR32_AD
47, // sub_8bit_hi -> GR32_AD
0, // sub_8bit_hi_phony
47, // sub_16bit -> GR32_AD
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // GR32_BPSP
48, // sub_8bit -> GR32_BPSP
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
48, // sub_16bit -> GR32_BPSP
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // GR32_BSI
49, // sub_8bit -> GR32_BSI
57, // sub_8bit_hi -> GR32_ABCD_and_GR32_BSI
0, // sub_8bit_hi_phony
49, // sub_16bit -> GR32_BSI
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // GR32_CB
50, // sub_8bit -> GR32_CB
50, // sub_8bit_hi -> GR32_CB
0, // sub_8bit_hi_phony
50, // sub_16bit -> GR32_CB
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // GR32_DC
51, // sub_8bit -> GR32_DC
51, // sub_8bit_hi -> GR32_DC
0, // sub_8bit_hi_phony
51, // sub_16bit -> GR32_DC
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // GR32_DIBP
52, // sub_8bit -> GR32_DIBP
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
52, // sub_16bit -> GR32_DIBP
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // GR32_SIDI
53, // sub_8bit -> GR32_SIDI
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
53, // sub_16bit -> GR32_SIDI
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // LOW32_ADDR_ACCESS_RBP_with_sub_32bit
64, // sub_8bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
54, // sub_16bit -> LOW32_ADDR_ACCESS_RBP_with_sub_32bit
0, // sub_16bit_hi
54, // sub_32bit -> LOW32_ADDR_ACCESS_RBP_with_sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // CCR
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // DFCCR
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // GR32_ABCD_and_GR32_BSI
57, // sub_8bit -> GR32_ABCD_and_GR32_BSI
57, // sub_8bit_hi -> GR32_ABCD_and_GR32_BSI
0, // sub_8bit_hi_phony
57, // sub_16bit -> GR32_ABCD_and_GR32_BSI
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // GR32_AD_and_GR32_DC
58, // sub_8bit -> GR32_AD_and_GR32_DC
58, // sub_8bit_hi -> GR32_AD_and_GR32_DC
0, // sub_8bit_hi_phony
58, // sub_16bit -> GR32_AD_and_GR32_DC
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // GR32_BPSP_and_GR32_DIBP
59, // sub_8bit -> GR32_BPSP_and_GR32_DIBP
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
59, // sub_16bit -> GR32_BPSP_and_GR32_DIBP
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // GR32_BPSP_and_GR32_TC
60, // sub_8bit -> GR32_BPSP_and_GR32_TC
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
60, // sub_16bit -> GR32_BPSP_and_GR32_TC
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // GR32_BSI_and_GR32_SIDI
61, // sub_8bit -> GR32_BSI_and_GR32_SIDI
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
61, // sub_16bit -> GR32_BSI_and_GR32_SIDI
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // GR32_CB_and_GR32_DC
62, // sub_8bit -> GR32_CB_and_GR32_DC
62, // sub_8bit_hi -> GR32_CB_and_GR32_DC
0, // sub_8bit_hi_phony
62, // sub_16bit -> GR32_CB_and_GR32_DC
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // GR32_DIBP_and_GR32_SIDI
63, // sub_8bit -> GR32_DIBP_and_GR32_SIDI
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
63, // sub_16bit -> GR32_DIBP_and_GR32_SIDI
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
64, // sub_8bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
64, // sub_16bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
0, // sub_16bit_hi
64, // sub_32bit -> LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // LOW32_ADDR_ACCESS_with_sub_32bit
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
65, // sub_16bit -> LOW32_ADDR_ACCESS_with_sub_32bit
0, // sub_16bit_hi
65, // sub_32bit -> LOW32_ADDR_ACCESS_with_sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // RFP64
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // FR64X
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // GR64
71, // sub_8bit -> GR64_with_sub_8bit
95, // sub_8bit_hi -> GR64_ABCD
0, // sub_8bit_hi_phony
68, // sub_16bit -> GR64
0, // sub_16bit_hi
68, // sub_32bit -> GR64
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // CONTROL_REG
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // FR64
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // GR64_with_sub_8bit
71, // sub_8bit -> GR64_with_sub_8bit
95, // sub_8bit_hi -> GR64_ABCD
0, // sub_8bit_hi_phony
71, // sub_16bit -> GR64_with_sub_8bit
0, // sub_16bit_hi
71, // sub_32bit -> GR64_with_sub_8bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // GR64_NOSP
72, // sub_8bit -> GR64_NOSP
95, // sub_8bit_hi -> GR64_ABCD
0, // sub_8bit_hi_phony
72, // sub_16bit -> GR64_NOSP
0, // sub_16bit_hi
72, // sub_32bit -> GR64_NOSP
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // GR64PLTSafe
73, // sub_8bit -> GR64PLTSafe
95, // sub_8bit_hi -> GR64_ABCD
0, // sub_8bit_hi_phony
73, // sub_16bit -> GR64PLTSafe
0, // sub_16bit_hi
73, // sub_32bit -> GR64PLTSafe
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // GR64_TC
77, // sub_8bit -> GR64_TC_with_sub_8bit
97, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
0, // sub_8bit_hi_phony
74, // sub_16bit -> GR64_TC
0, // sub_16bit_hi
74, // sub_32bit -> GR64_TC
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // GR64_NOREX
81, // sub_8bit -> GR64_with_sub_16bit_in_GR16_NOREX
95, // sub_8bit_hi -> GR64_ABCD
0, // sub_8bit_hi_phony
75, // sub_16bit -> GR64_NOREX
0, // sub_16bit_hi
75, // sub_32bit -> GR64_NOREX
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // GR64_TCW64
79, // sub_8bit -> GR64_TCW64_with_sub_8bit
97, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
0, // sub_8bit_hi_phony
76, // sub_16bit -> GR64_TCW64
0, // sub_16bit_hi
76, // sub_32bit -> GR64_TCW64
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // GR64_TC_with_sub_8bit
77, // sub_8bit -> GR64_TC_with_sub_8bit
97, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
0, // sub_8bit_hi_phony
77, // sub_16bit -> GR64_TC_with_sub_8bit
0, // sub_16bit_hi
77, // sub_32bit -> GR64_TC_with_sub_8bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // GR64_NOSP_and_GR64_TC
78, // sub_8bit -> GR64_NOSP_and_GR64_TC
97, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
0, // sub_8bit_hi_phony
78, // sub_16bit -> GR64_NOSP_and_GR64_TC
0, // sub_16bit_hi
78, // sub_32bit -> GR64_NOSP_and_GR64_TC
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // GR64_TCW64_with_sub_8bit
79, // sub_8bit -> GR64_TCW64_with_sub_8bit
97, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
0, // sub_8bit_hi_phony
79, // sub_16bit -> GR64_TCW64_with_sub_8bit
0, // sub_16bit_hi
79, // sub_32bit -> GR64_TCW64_with_sub_8bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // GR64_TC_and_GR64_TCW64
88, // sub_8bit -> GR64_TCW64_and_GR64_TC_with_sub_8bit
97, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
0, // sub_8bit_hi_phony
80, // sub_16bit -> GR64_TC_and_GR64_TCW64
0, // sub_16bit_hi
80, // sub_32bit -> GR64_TC_and_GR64_TCW64
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // GR64_with_sub_16bit_in_GR16_NOREX
81, // sub_8bit -> GR64_with_sub_16bit_in_GR16_NOREX
95, // sub_8bit_hi -> GR64_ABCD
0, // sub_8bit_hi_phony
81, // sub_16bit -> GR64_with_sub_16bit_in_GR16_NOREX
0, // sub_16bit_hi
81, // sub_32bit -> GR64_with_sub_16bit_in_GR16_NOREX
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // VK64
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // VR64
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // GR64PLTSafe_and_GR64_TC
84, // sub_8bit -> GR64PLTSafe_and_GR64_TC
97, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
0, // sub_8bit_hi_phony
84, // sub_16bit -> GR64PLTSafe_and_GR64_TC
0, // sub_16bit_hi
84, // sub_32bit -> GR64PLTSafe_and_GR64_TC
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // GR64_NOREX_NOSP
85, // sub_8bit -> GR64_NOREX_NOSP
95, // sub_8bit_hi -> GR64_ABCD
0, // sub_8bit_hi_phony
85, // sub_16bit -> GR64_NOREX_NOSP
0, // sub_16bit_hi
85, // sub_32bit -> GR64_NOREX_NOSP
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // GR64_NOREX_and_GR64_TC
91, // sub_8bit -> GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX
97, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
0, // sub_8bit_hi_phony
86, // sub_16bit -> GR64_NOREX_and_GR64_TC
0, // sub_16bit_hi
86, // sub_32bit -> GR64_NOREX_and_GR64_TC
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // GR64_NOSP_and_GR64_TCW64
87, // sub_8bit -> GR64_NOSP_and_GR64_TCW64
97, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
0, // sub_8bit_hi_phony
87, // sub_16bit -> GR64_NOSP_and_GR64_TCW64
0, // sub_16bit_hi
87, // sub_32bit -> GR64_NOSP_and_GR64_TCW64
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // GR64_TCW64_and_GR64_TC_with_sub_8bit
88, // sub_8bit -> GR64_TCW64_and_GR64_TC_with_sub_8bit
97, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
0, // sub_8bit_hi_phony
88, // sub_16bit -> GR64_TCW64_and_GR64_TC_with_sub_8bit
0, // sub_16bit_hi
88, // sub_32bit -> GR64_TCW64_and_GR64_TC_with_sub_8bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // VK64WM
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // GR64_TC_and_GR64_NOSP_and_GR64_TCW64
90, // sub_8bit -> GR64_TC_and_GR64_NOSP_and_GR64_TCW64
97, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
0, // sub_8bit_hi_phony
90, // sub_16bit -> GR64_TC_and_GR64_NOSP_and_GR64_TCW64
0, // sub_16bit_hi
90, // sub_32bit -> GR64_TC_and_GR64_NOSP_and_GR64_TCW64
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX
91, // sub_8bit -> GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX
97, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
0, // sub_8bit_hi_phony
91, // sub_16bit -> GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX
0, // sub_16bit_hi
91, // sub_32bit -> GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // GR64PLTSafe_and_GR64_TCW64
92, // sub_8bit -> GR64PLTSafe_and_GR64_TCW64
97, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
0, // sub_8bit_hi_phony
92, // sub_16bit -> GR64PLTSafe_and_GR64_TCW64
0, // sub_16bit_hi
92, // sub_32bit -> GR64PLTSafe_and_GR64_TCW64
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC
93, // sub_8bit -> GR64_NOREX_and_GR64PLTSafe_and_GR64_TC
97, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
0, // sub_8bit_hi_phony
93, // sub_16bit -> GR64_NOREX_and_GR64PLTSafe_and_GR64_TC
0, // sub_16bit_hi
93, // sub_32bit -> GR64_NOREX_and_GR64PLTSafe_and_GR64_TC
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // GR64_NOREX_and_GR64_TCW64
96, // sub_8bit -> GR64_with_sub_32bit_in_GR32_TC
97, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
0, // sub_8bit_hi_phony
94, // sub_16bit -> GR64_NOREX_and_GR64_TCW64
0, // sub_16bit_hi
94, // sub_32bit -> GR64_NOREX_and_GR64_TCW64
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // GR64_ABCD
95, // sub_8bit -> GR64_ABCD
95, // sub_8bit_hi -> GR64_ABCD
0, // sub_8bit_hi_phony
95, // sub_16bit -> GR64_ABCD
0, // sub_16bit_hi
95, // sub_32bit -> GR64_ABCD
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // GR64_with_sub_32bit_in_GR32_TC
96, // sub_8bit -> GR64_with_sub_32bit_in_GR32_TC
97, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
0, // sub_8bit_hi_phony
96, // sub_16bit -> GR64_with_sub_32bit_in_GR32_TC
0, // sub_16bit_hi
96, // sub_32bit -> GR64_with_sub_32bit_in_GR32_TC
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
97, // sub_8bit -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
97, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
0, // sub_8bit_hi_phony
97, // sub_16bit -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
0, // sub_16bit_hi
97, // sub_32bit -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // GR64_AD
98, // sub_8bit -> GR64_AD
98, // sub_8bit_hi -> GR64_AD
0, // sub_8bit_hi_phony
98, // sub_16bit -> GR64_AD
0, // sub_16bit_hi
98, // sub_32bit -> GR64_AD
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // GR64_and_LOW32_ADDR_ACCESS_RBP
109, // sub_8bit -> GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
99, // sub_16bit -> GR64_and_LOW32_ADDR_ACCESS_RBP
0, // sub_16bit_hi
99, // sub_32bit -> GR64_and_LOW32_ADDR_ACCESS_RBP
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // GR64_with_sub_32bit_in_GR32_BPSP
100, // sub_8bit -> GR64_with_sub_32bit_in_GR32_BPSP
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
100, // sub_16bit -> GR64_with_sub_32bit_in_GR32_BPSP
0, // sub_16bit_hi
100, // sub_32bit -> GR64_with_sub_32bit_in_GR32_BPSP
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // GR64_with_sub_32bit_in_GR32_BSI
101, // sub_8bit -> GR64_with_sub_32bit_in_GR32_BSI
107, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
0, // sub_8bit_hi_phony
101, // sub_16bit -> GR64_with_sub_32bit_in_GR32_BSI
0, // sub_16bit_hi
101, // sub_32bit -> GR64_with_sub_32bit_in_GR32_BSI
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // GR64_with_sub_32bit_in_GR32_CB
102, // sub_8bit -> GR64_with_sub_32bit_in_GR32_CB
102, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_CB
0, // sub_8bit_hi_phony
102, // sub_16bit -> GR64_with_sub_32bit_in_GR32_CB
0, // sub_16bit_hi
102, // sub_32bit -> GR64_with_sub_32bit_in_GR32_CB
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // GR64_with_sub_32bit_in_GR32_DC
103, // sub_8bit -> GR64_with_sub_32bit_in_GR32_DC
103, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_DC
0, // sub_8bit_hi_phony
103, // sub_16bit -> GR64_with_sub_32bit_in_GR32_DC
0, // sub_16bit_hi
103, // sub_32bit -> GR64_with_sub_32bit_in_GR32_DC
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // GR64_with_sub_32bit_in_GR32_DIBP
104, // sub_8bit -> GR64_with_sub_32bit_in_GR32_DIBP
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
104, // sub_16bit -> GR64_with_sub_32bit_in_GR32_DIBP
0, // sub_16bit_hi
104, // sub_32bit -> GR64_with_sub_32bit_in_GR32_DIBP
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // GR64_with_sub_32bit_in_GR32_SIDI
105, // sub_8bit -> GR64_with_sub_32bit_in_GR32_SIDI
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
105, // sub_16bit -> GR64_with_sub_32bit_in_GR32_SIDI
0, // sub_16bit_hi
105, // sub_32bit -> GR64_with_sub_32bit_in_GR32_SIDI
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // GR64_and_LOW32_ADDR_ACCESS
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
106, // sub_16bit -> GR64_and_LOW32_ADDR_ACCESS
0, // sub_16bit_hi
106, // sub_32bit -> GR64_and_LOW32_ADDR_ACCESS
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
107, // sub_8bit -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
107, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
0, // sub_8bit_hi_phony
107, // sub_16bit -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
0, // sub_16bit_hi
107, // sub_32bit -> GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // GR64_with_sub_32bit_in_GR32_AD_and_GR32_DC
108, // sub_8bit -> GR64_with_sub_32bit_in_GR32_AD_and_GR32_DC
108, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_AD_and_GR32_DC
0, // sub_8bit_hi_phony
108, // sub_16bit -> GR64_with_sub_32bit_in_GR32_AD_and_GR32_DC
0, // sub_16bit_hi
108, // sub_32bit -> GR64_with_sub_32bit_in_GR32_AD_and_GR32_DC
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
109, // sub_8bit -> GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
109, // sub_16bit -> GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
0, // sub_16bit_hi
109, // sub_32bit -> GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC
110, // sub_8bit -> GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
110, // sub_16bit -> GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC
0, // sub_16bit_hi
110, // sub_32bit -> GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI
111, // sub_8bit -> GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
111, // sub_16bit -> GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI
0, // sub_16bit_hi
111, // sub_32bit -> GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // GR64_with_sub_32bit_in_GR32_CB_and_GR32_DC
112, // sub_8bit -> GR64_with_sub_32bit_in_GR32_CB_and_GR32_DC
112, // sub_8bit_hi -> GR64_with_sub_32bit_in_GR32_CB_and_GR32_DC
0, // sub_8bit_hi_phony
112, // sub_16bit -> GR64_with_sub_32bit_in_GR32_CB_and_GR32_DC
0, // sub_16bit_hi
112, // sub_32bit -> GR64_with_sub_32bit_in_GR32_CB_and_GR32_DC
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI
113, // sub_8bit -> GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
113, // sub_16bit -> GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI
0, // sub_16bit_hi
113, // sub_32bit -> GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // RST
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // RFP80
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // RFP80_7
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // VR128X
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // VR128
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
{ // VR256X
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
119, // sub_xmm -> VR256X
0, // sub_ymm
},
{ // VR256
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
120, // sub_xmm -> VR256
0, // sub_ymm
},
{ // VR512
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
121, // sub_xmm -> VR512
121, // sub_ymm -> VR512
},
{ // VR512_0_15
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
122, // sub_xmm -> VR512_0_15
122, // sub_ymm -> VR512_0_15
},
{ // TILE
0, // sub_8bit
0, // sub_8bit_hi
0, // sub_8bit_hi_phony
0, // sub_16bit
0, // sub_16bit_hi
0, // sub_32bit
0, // sub_mask_0
0, // sub_mask_1
0, // sub_xmm
0, // sub_ymm
},
};
assert(RC && "Missing regclass");
if (!Idx) return RC;
--Idx;
assert(Idx < 10 && "Bad subreg");
unsigned TV = Table[RC->getID()][Idx];
return TV ? getRegClass(TV - 1) : nullptr;
}
const TargetRegisterClass *X86GenRegisterInfo::getSubRegisterClass(const TargetRegisterClass *RC, unsigned Idx) const {
static const uint8_t Table[123][10] = {
{ // GR8
0, // GR8:sub_8bit
0, // GR8:sub_8bit_hi
0, // GR8:sub_8bit_hi_phony
0, // GR8:sub_16bit
0, // GR8:sub_16bit_hi
0, // GR8:sub_32bit
0, // GR8:sub_mask_0
0, // GR8:sub_mask_1
0, // GR8:sub_xmm
0, // GR8:sub_ymm
},
{ // GRH8
0, // GRH8:sub_8bit
0, // GRH8:sub_8bit_hi
0, // GRH8:sub_8bit_hi_phony
0, // GRH8:sub_16bit
0, // GRH8:sub_16bit_hi
0, // GRH8:sub_32bit
0, // GRH8:sub_mask_0
0, // GRH8:sub_mask_1
0, // GRH8:sub_xmm
0, // GRH8:sub_ymm
},
{ // GR8_NOREX
0, // GR8_NOREX:sub_8bit
0, // GR8_NOREX:sub_8bit_hi
0, // GR8_NOREX:sub_8bit_hi_phony
0, // GR8_NOREX:sub_16bit
0, // GR8_NOREX:sub_16bit_hi
0, // GR8_NOREX:sub_32bit
0, // GR8_NOREX:sub_mask_0
0, // GR8_NOREX:sub_mask_1
0, // GR8_NOREX:sub_xmm
0, // GR8_NOREX:sub_ymm
},
{ // GR8_ABCD_H
0, // GR8_ABCD_H:sub_8bit
0, // GR8_ABCD_H:sub_8bit_hi
0, // GR8_ABCD_H:sub_8bit_hi_phony
0, // GR8_ABCD_H:sub_16bit
0, // GR8_ABCD_H:sub_16bit_hi
0, // GR8_ABCD_H:sub_32bit
0, // GR8_ABCD_H:sub_mask_0
0, // GR8_ABCD_H:sub_mask_1
0, // GR8_ABCD_H:sub_xmm
0, // GR8_ABCD_H:sub_ymm
},
{ // GR8_ABCD_L
0, // GR8_ABCD_L:sub_8bit
0, // GR8_ABCD_L:sub_8bit_hi
0, // GR8_ABCD_L:sub_8bit_hi_phony
0, // GR8_ABCD_L:sub_16bit
0, // GR8_ABCD_L:sub_16bit_hi
0, // GR8_ABCD_L:sub_32bit
0, // GR8_ABCD_L:sub_mask_0
0, // GR8_ABCD_L:sub_mask_1
0, // GR8_ABCD_L:sub_xmm
0, // GR8_ABCD_L:sub_ymm
},
{ // GRH16
0, // GRH16:sub_8bit
0, // GRH16:sub_8bit_hi
0, // GRH16:sub_8bit_hi_phony
0, // GRH16:sub_16bit
0, // GRH16:sub_16bit_hi
0, // GRH16:sub_32bit
0, // GRH16:sub_mask_0
0, // GRH16:sub_mask_1
0, // GRH16:sub_xmm
0, // GRH16:sub_ymm
},
{ // GR16
1, // GR16:sub_8bit -> GR8
4, // GR16:sub_8bit_hi -> GR8_ABCD_H
0, // GR16:sub_8bit_hi_phony
0, // GR16:sub_16bit
0, // GR16:sub_16bit_hi
0, // GR16:sub_32bit
0, // GR16:sub_mask_0
0, // GR16:sub_mask_1
0, // GR16:sub_xmm
0, // GR16:sub_ymm
},
{ // GR16_NOREX
1, // GR16_NOREX:sub_8bit -> GR8
4, // GR16_NOREX:sub_8bit_hi -> GR8_ABCD_H
0, // GR16_NOREX:sub_8bit_hi_phony
0, // GR16_NOREX:sub_16bit
0, // GR16_NOREX:sub_16bit_hi
0, // GR16_NOREX:sub_32bit
0, // GR16_NOREX:sub_mask_0
0, // GR16_NOREX:sub_mask_1
0, // GR16_NOREX:sub_xmm
0, // GR16_NOREX:sub_ymm
},
{ // VK1
0, // VK1:sub_8bit
0, // VK1:sub_8bit_hi
0, // VK1:sub_8bit_hi_phony
0, // VK1:sub_16bit
0, // VK1:sub_16bit_hi
0, // VK1:sub_32bit
0, // VK1:sub_mask_0
0, // VK1:sub_mask_1
0, // VK1:sub_xmm
0, // VK1:sub_ymm
},
{ // VK16
0, // VK16:sub_8bit
0, // VK16:sub_8bit_hi
0, // VK16:sub_8bit_hi_phony
0, // VK16:sub_16bit
0, // VK16:sub_16bit_hi
0, // VK16:sub_32bit
0, // VK16:sub_mask_0
0, // VK16:sub_mask_1
0, // VK16:sub_xmm
0, // VK16:sub_ymm
},
{ // VK2
0, // VK2:sub_8bit
0, // VK2:sub_8bit_hi
0, // VK2:sub_8bit_hi_phony
0, // VK2:sub_16bit
0, // VK2:sub_16bit_hi
0, // VK2:sub_32bit
0, // VK2:sub_mask_0
0, // VK2:sub_mask_1
0, // VK2:sub_xmm
0, // VK2:sub_ymm
},
{ // VK4
0, // VK4:sub_8bit
0, // VK4:sub_8bit_hi
0, // VK4:sub_8bit_hi_phony
0, // VK4:sub_16bit
0, // VK4:sub_16bit_hi
0, // VK4:sub_32bit
0, // VK4:sub_mask_0
0, // VK4:sub_mask_1
0, // VK4:sub_xmm
0, // VK4:sub_ymm
},
{ // VK8
0, // VK8:sub_8bit
0, // VK8:sub_8bit_hi
0, // VK8:sub_8bit_hi_phony
0, // VK8:sub_16bit
0, // VK8:sub_16bit_hi
0, // VK8:sub_32bit
0, // VK8:sub_mask_0
0, // VK8:sub_mask_1
0, // VK8:sub_xmm
0, // VK8:sub_ymm
},
{ // VK16WM
0, // VK16WM:sub_8bit
0, // VK16WM:sub_8bit_hi
0, // VK16WM:sub_8bit_hi_phony
0, // VK16WM:sub_16bit
0, // VK16WM:sub_16bit_hi
0, // VK16WM:sub_32bit
0, // VK16WM:sub_mask_0
0, // VK16WM:sub_mask_1
0, // VK16WM:sub_xmm
0, // VK16WM:sub_ymm
},
{ // VK1WM
0, // VK1WM:sub_8bit
0, // VK1WM:sub_8bit_hi
0, // VK1WM:sub_8bit_hi_phony
0, // VK1WM:sub_16bit
0, // VK1WM:sub_16bit_hi
0, // VK1WM:sub_32bit
0, // VK1WM:sub_mask_0
0, // VK1WM:sub_mask_1
0, // VK1WM:sub_xmm
0, // VK1WM:sub_ymm
},
{ // VK2WM
0, // VK2WM:sub_8bit
0, // VK2WM:sub_8bit_hi
0, // VK2WM:sub_8bit_hi_phony
0, // VK2WM:sub_16bit
0, // VK2WM:sub_16bit_hi
0, // VK2WM:sub_32bit
0, // VK2WM:sub_mask_0
0, // VK2WM:sub_mask_1
0, // VK2WM:sub_xmm
0, // VK2WM:sub_ymm
},
{ // VK4WM
0, // VK4WM:sub_8bit
0, // VK4WM:sub_8bit_hi
0, // VK4WM:sub_8bit_hi_phony
0, // VK4WM:sub_16bit
0, // VK4WM:sub_16bit_hi
0, // VK4WM:sub_32bit
0, // VK4WM:sub_mask_0
0, // VK4WM:sub_mask_1
0, // VK4WM:sub_xmm
0, // VK4WM:sub_ymm
},
{ // VK8WM
0, // VK8WM:sub_8bit
0, // VK8WM:sub_8bit_hi
0, // VK8WM:sub_8bit_hi_phony
0, // VK8WM:sub_16bit
0, // VK8WM:sub_16bit_hi
0, // VK8WM:sub_32bit
0, // VK8WM:sub_mask_0
0, // VK8WM:sub_mask_1
0, // VK8WM:sub_xmm
0, // VK8WM:sub_ymm
},
{ // SEGMENT_REG
0, // SEGMENT_REG:sub_8bit
0, // SEGMENT_REG:sub_8bit_hi
0, // SEGMENT_REG:sub_8bit_hi_phony
0, // SEGMENT_REG:sub_16bit
0, // SEGMENT_REG:sub_16bit_hi
0, // SEGMENT_REG:sub_32bit
0, // SEGMENT_REG:sub_mask_0
0, // SEGMENT_REG:sub_mask_1
0, // SEGMENT_REG:sub_xmm
0, // SEGMENT_REG:sub_ymm
},
{ // GR16_ABCD
5, // GR16_ABCD:sub_8bit -> GR8_ABCD_L
4, // GR16_ABCD:sub_8bit_hi -> GR8_ABCD_H
0, // GR16_ABCD:sub_8bit_hi_phony
0, // GR16_ABCD:sub_16bit
0, // GR16_ABCD:sub_16bit_hi
0, // GR16_ABCD:sub_32bit
0, // GR16_ABCD:sub_mask_0
0, // GR16_ABCD:sub_mask_1
0, // GR16_ABCD:sub_xmm
0, // GR16_ABCD:sub_ymm
},
{ // FPCCR
0, // FPCCR:sub_8bit
0, // FPCCR:sub_8bit_hi
0, // FPCCR:sub_8bit_hi_phony
0, // FPCCR:sub_16bit
0, // FPCCR:sub_16bit_hi
0, // FPCCR:sub_32bit
0, // FPCCR:sub_mask_0
0, // FPCCR:sub_mask_1
0, // FPCCR:sub_xmm
0, // FPCCR:sub_ymm
},
{ // FR16X
0, // FR16X:sub_8bit
0, // FR16X:sub_8bit_hi
0, // FR16X:sub_8bit_hi_phony
0, // FR16X:sub_16bit
0, // FR16X:sub_16bit_hi
0, // FR16X:sub_32bit
0, // FR16X:sub_mask_0
0, // FR16X:sub_mask_1
0, // FR16X:sub_xmm
0, // FR16X:sub_ymm
},
{ // FR16
0, // FR16:sub_8bit
0, // FR16:sub_8bit_hi
0, // FR16:sub_8bit_hi_phony
0, // FR16:sub_16bit
0, // FR16:sub_16bit_hi
0, // FR16:sub_32bit
0, // FR16:sub_mask_0
0, // FR16:sub_mask_1
0, // FR16:sub_xmm
0, // FR16:sub_ymm
},
{ // VK16PAIR
0, // VK16PAIR:sub_8bit
0, // VK16PAIR:sub_8bit_hi
0, // VK16PAIR:sub_8bit_hi_phony
0, // VK16PAIR:sub_16bit
0, // VK16PAIR:sub_16bit_hi
0, // VK16PAIR:sub_32bit
82, // VK16PAIR:sub_mask_0 -> VK64
89, // VK16PAIR:sub_mask_1 -> VK64WM
0, // VK16PAIR:sub_xmm
0, // VK16PAIR:sub_ymm
},
{ // VK1PAIR
0, // VK1PAIR:sub_8bit
0, // VK1PAIR:sub_8bit_hi
0, // VK1PAIR:sub_8bit_hi_phony
0, // VK1PAIR:sub_16bit
0, // VK1PAIR:sub_16bit_hi
0, // VK1PAIR:sub_32bit
82, // VK1PAIR:sub_mask_0 -> VK64
89, // VK1PAIR:sub_mask_1 -> VK64WM
0, // VK1PAIR:sub_xmm
0, // VK1PAIR:sub_ymm
},
{ // VK2PAIR
0, // VK2PAIR:sub_8bit
0, // VK2PAIR:sub_8bit_hi
0, // VK2PAIR:sub_8bit_hi_phony
0, // VK2PAIR:sub_16bit
0, // VK2PAIR:sub_16bit_hi
0, // VK2PAIR:sub_32bit
82, // VK2PAIR:sub_mask_0 -> VK64
89, // VK2PAIR:sub_mask_1 -> VK64WM
0, // VK2PAIR:sub_xmm
0, // VK2PAIR:sub_ymm
},
{ // VK4PAIR
0, // VK4PAIR:sub_8bit
0, // VK4PAIR:sub_8bit_hi
0, // VK4PAIR:sub_8bit_hi_phony
0, // VK4PAIR:sub_16bit
0, // VK4PAIR:sub_16bit_hi
0, // VK4PAIR:sub_32bit
82, // VK4PAIR:sub_mask_0 -> VK64
89, // VK4PAIR:sub_mask_1 -> VK64WM
0, // VK4PAIR:sub_xmm
0, // VK4PAIR:sub_ymm
},
{ // VK8PAIR
0, // VK8PAIR:sub_8bit
0, // VK8PAIR:sub_8bit_hi
0, // VK8PAIR:sub_8bit_hi_phony
0, // VK8PAIR:sub_16bit
0, // VK8PAIR:sub_16bit_hi
0, // VK8PAIR:sub_32bit
82, // VK8PAIR:sub_mask_0 -> VK64
89, // VK8PAIR:sub_mask_1 -> VK64WM
0, // VK8PAIR:sub_xmm
0, // VK8PAIR:sub_ymm
},
{ // VK16PAIR_with_sub_mask_0_in_VK16WM
0, // VK16PAIR_with_sub_mask_0_in_VK16WM:sub_8bit
0, // VK16PAIR_with_sub_mask_0_in_VK16WM:sub_8bit_hi
0, // VK16PAIR_with_sub_mask_0_in_VK16WM:sub_8bit_hi_phony
0, // VK16PAIR_with_sub_mask_0_in_VK16WM:sub_16bit
0, // VK16PAIR_with_sub_mask_0_in_VK16WM:sub_16bit_hi
0, // VK16PAIR_with_sub_mask_0_in_VK16WM:sub_32bit
89, // VK16PAIR_with_sub_mask_0_in_VK16WM:sub_mask_0 -> VK64WM
89, // VK16PAIR_with_sub_mask_0_in_VK16WM:sub_mask_1 -> VK64WM
0, // VK16PAIR_with_sub_mask_0_in_VK16WM:sub_xmm
0, // VK16PAIR_with_sub_mask_0_in_VK16WM:sub_ymm
},
{ // FR32X
0, // FR32X:sub_8bit
0, // FR32X:sub_8bit_hi
0, // FR32X:sub_8bit_hi_phony
0, // FR32X:sub_16bit
0, // FR32X:sub_16bit_hi
0, // FR32X:sub_32bit
0, // FR32X:sub_mask_0
0, // FR32X:sub_mask_1
0, // FR32X:sub_xmm
0, // FR32X:sub_ymm
},
{ // LOW32_ADDR_ACCESS_RBP
1, // LOW32_ADDR_ACCESS_RBP:sub_8bit -> GR8
4, // LOW32_ADDR_ACCESS_RBP:sub_8bit_hi -> GR8_ABCD_H
0, // LOW32_ADDR_ACCESS_RBP:sub_8bit_hi_phony
7, // LOW32_ADDR_ACCESS_RBP:sub_16bit -> GR16
0, // LOW32_ADDR_ACCESS_RBP:sub_16bit_hi
59, // LOW32_ADDR_ACCESS_RBP:sub_32bit -> GR32_BPSP_and_GR32_DIBP
0, // LOW32_ADDR_ACCESS_RBP:sub_mask_0
0, // LOW32_ADDR_ACCESS_RBP:sub_mask_1
0, // LOW32_ADDR_ACCESS_RBP:sub_xmm
0, // LOW32_ADDR_ACCESS_RBP:sub_ymm
},
{ // LOW32_ADDR_ACCESS
1, // LOW32_ADDR_ACCESS:sub_8bit -> GR8
4, // LOW32_ADDR_ACCESS:sub_8bit_hi -> GR8_ABCD_H
0, // LOW32_ADDR_ACCESS:sub_8bit_hi_phony
7, // LOW32_ADDR_ACCESS:sub_16bit -> GR16
0, // LOW32_ADDR_ACCESS:sub_16bit_hi
0, // LOW32_ADDR_ACCESS:sub_32bit
0, // LOW32_ADDR_ACCESS:sub_mask_0
0, // LOW32_ADDR_ACCESS:sub_mask_1
0, // LOW32_ADDR_ACCESS:sub_xmm
0, // LOW32_ADDR_ACCESS:sub_ymm
},
{ // LOW32_ADDR_ACCESS_RBP_with_sub_8bit
1, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit:sub_8bit -> GR8
4, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit:sub_8bit_hi -> GR8_ABCD_H
0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit:sub_8bit_hi_phony
7, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit:sub_16bit -> GR16
0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit:sub_16bit_hi
59, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit:sub_32bit -> GR32_BPSP_and_GR32_DIBP
0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit:sub_mask_0
0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit:sub_mask_1
0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit:sub_xmm
0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit:sub_ymm
},
{ // DEBUG_REG
0, // DEBUG_REG:sub_8bit
0, // DEBUG_REG:sub_8bit_hi
0, // DEBUG_REG:sub_8bit_hi_phony
0, // DEBUG_REG:sub_16bit
0, // DEBUG_REG:sub_16bit_hi
0, // DEBUG_REG:sub_32bit
0, // DEBUG_REG:sub_mask_0
0, // DEBUG_REG:sub_mask_1
0, // DEBUG_REG:sub_xmm
0, // DEBUG_REG:sub_ymm
},
{ // FR32
0, // FR32:sub_8bit
0, // FR32:sub_8bit_hi
0, // FR32:sub_8bit_hi_phony
0, // FR32:sub_16bit
0, // FR32:sub_16bit_hi
0, // FR32:sub_32bit
0, // FR32:sub_mask_0
0, // FR32:sub_mask_1
0, // FR32:sub_xmm
0, // FR32:sub_ymm
},
{ // GR32
1, // GR32:sub_8bit -> GR8
4, // GR32:sub_8bit_hi -> GR8_ABCD_H
0, // GR32:sub_8bit_hi_phony
7, // GR32:sub_16bit -> GR16
0, // GR32:sub_16bit_hi
0, // GR32:sub_32bit
0, // GR32:sub_mask_0
0, // GR32:sub_mask_1
0, // GR32:sub_xmm
0, // GR32:sub_ymm
},
{ // GR32_NOSP
1, // GR32_NOSP:sub_8bit -> GR8
4, // GR32_NOSP:sub_8bit_hi -> GR8_ABCD_H
0, // GR32_NOSP:sub_8bit_hi_phony
7, // GR32_NOSP:sub_16bit -> GR16
0, // GR32_NOSP:sub_16bit_hi
0, // GR32_NOSP:sub_32bit
0, // GR32_NOSP:sub_mask_0
0, // GR32_NOSP:sub_mask_1
0, // GR32_NOSP:sub_xmm
0, // GR32_NOSP:sub_ymm
},
{ // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX
1, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX:sub_8bit -> GR8
4, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX:sub_8bit_hi -> GR8_ABCD_H
0, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX:sub_8bit_hi_phony
8, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX:sub_16bit -> GR16_NOREX
0, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX:sub_16bit_hi
59, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX:sub_32bit -> GR32_BPSP_and_GR32_DIBP
0, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX:sub_mask_0
0, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX:sub_mask_1
0, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX:sub_xmm
0, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX:sub_ymm
},
{ // GR32_NOREX
1, // GR32_NOREX:sub_8bit -> GR8
4, // GR32_NOREX:sub_8bit_hi -> GR8_ABCD_H
0, // GR32_NOREX:sub_8bit_hi_phony
8, // GR32_NOREX:sub_16bit -> GR16_NOREX
0, // GR32_NOREX:sub_16bit_hi
0, // GR32_NOREX:sub_32bit
0, // GR32_NOREX:sub_mask_0
0, // GR32_NOREX:sub_mask_1
0, // GR32_NOREX:sub_xmm
0, // GR32_NOREX:sub_ymm
},
{ // VK32
0, // VK32:sub_8bit
0, // VK32:sub_8bit_hi
0, // VK32:sub_8bit_hi_phony
0, // VK32:sub_16bit
0, // VK32:sub_16bit_hi
0, // VK32:sub_32bit
0, // VK32:sub_mask_0
0, // VK32:sub_mask_1
0, // VK32:sub_xmm
0, // VK32:sub_ymm
},
{ // GR32_NOREX_NOSP
1, // GR32_NOREX_NOSP:sub_8bit -> GR8
4, // GR32_NOREX_NOSP:sub_8bit_hi -> GR8_ABCD_H
0, // GR32_NOREX_NOSP:sub_8bit_hi_phony
8, // GR32_NOREX_NOSP:sub_16bit -> GR16_NOREX
0, // GR32_NOREX_NOSP:sub_16bit_hi
0, // GR32_NOREX_NOSP:sub_32bit
0, // GR32_NOREX_NOSP:sub_mask_0
0, // GR32_NOREX_NOSP:sub_mask_1
0, // GR32_NOREX_NOSP:sub_xmm
0, // GR32_NOREX_NOSP:sub_ymm
},
{ // RFP32
0, // RFP32:sub_8bit
0, // RFP32:sub_8bit_hi
0, // RFP32:sub_8bit_hi_phony
0, // RFP32:sub_16bit
0, // RFP32:sub_16bit_hi
0, // RFP32:sub_32bit
0, // RFP32:sub_mask_0
0, // RFP32:sub_mask_1
0, // RFP32:sub_xmm
0, // RFP32:sub_ymm
},
{ // VK32WM
0, // VK32WM:sub_8bit
0, // VK32WM:sub_8bit_hi
0, // VK32WM:sub_8bit_hi_phony
0, // VK32WM:sub_16bit
0, // VK32WM:sub_16bit_hi
0, // VK32WM:sub_32bit
0, // VK32WM:sub_mask_0
0, // VK32WM:sub_mask_1
0, // VK32WM:sub_xmm
0, // VK32WM:sub_ymm
},
{ // GR32_ABCD
5, // GR32_ABCD:sub_8bit -> GR8_ABCD_L
4, // GR32_ABCD:sub_8bit_hi -> GR8_ABCD_H
0, // GR32_ABCD:sub_8bit_hi_phony
20, // GR32_ABCD:sub_16bit -> GR16_ABCD
0, // GR32_ABCD:sub_16bit_hi
0, // GR32_ABCD:sub_32bit
0, // GR32_ABCD:sub_mask_0
0, // GR32_ABCD:sub_mask_1
0, // GR32_ABCD:sub_xmm
0, // GR32_ABCD:sub_ymm
},
{ // GR32_TC
1, // GR32_TC:sub_8bit -> GR8
4, // GR32_TC:sub_8bit_hi -> GR8_ABCD_H
0, // GR32_TC:sub_8bit_hi_phony
8, // GR32_TC:sub_16bit -> GR16_NOREX
0, // GR32_TC:sub_16bit_hi
0, // GR32_TC:sub_32bit
0, // GR32_TC:sub_mask_0
0, // GR32_TC:sub_mask_1
0, // GR32_TC:sub_xmm
0, // GR32_TC:sub_ymm
},
{ // GR32_ABCD_and_GR32_TC
5, // GR32_ABCD_and_GR32_TC:sub_8bit -> GR8_ABCD_L
4, // GR32_ABCD_and_GR32_TC:sub_8bit_hi -> GR8_ABCD_H
0, // GR32_ABCD_and_GR32_TC:sub_8bit_hi_phony
20, // GR32_ABCD_and_GR32_TC:sub_16bit -> GR16_ABCD
0, // GR32_ABCD_and_GR32_TC:sub_16bit_hi
0, // GR32_ABCD_and_GR32_TC:sub_32bit
0, // GR32_ABCD_and_GR32_TC:sub_mask_0
0, // GR32_ABCD_and_GR32_TC:sub_mask_1
0, // GR32_ABCD_and_GR32_TC:sub_xmm
0, // GR32_ABCD_and_GR32_TC:sub_ymm
},
{ // GR32_AD
5, // GR32_AD:sub_8bit -> GR8_ABCD_L
4, // GR32_AD:sub_8bit_hi -> GR8_ABCD_H
0, // GR32_AD:sub_8bit_hi_phony
20, // GR32_AD:sub_16bit -> GR16_ABCD
0, // GR32_AD:sub_16bit_hi
0, // GR32_AD:sub_32bit
0, // GR32_AD:sub_mask_0
0, // GR32_AD:sub_mask_1
0, // GR32_AD:sub_xmm
0, // GR32_AD:sub_ymm
},
{ // GR32_BPSP
1, // GR32_BPSP:sub_8bit -> GR8
0, // GR32_BPSP:sub_8bit_hi
0, // GR32_BPSP:sub_8bit_hi_phony
8, // GR32_BPSP:sub_16bit -> GR16_NOREX
0, // GR32_BPSP:sub_16bit_hi
0, // GR32_BPSP:sub_32bit
0, // GR32_BPSP:sub_mask_0
0, // GR32_BPSP:sub_mask_1
0, // GR32_BPSP:sub_xmm
0, // GR32_BPSP:sub_ymm
},
{ // GR32_BSI
1, // GR32_BSI:sub_8bit -> GR8
4, // GR32_BSI:sub_8bit_hi -> GR8_ABCD_H
0, // GR32_BSI:sub_8bit_hi_phony
8, // GR32_BSI:sub_16bit -> GR16_NOREX
0, // GR32_BSI:sub_16bit_hi
0, // GR32_BSI:sub_32bit
0, // GR32_BSI:sub_mask_0
0, // GR32_BSI:sub_mask_1
0, // GR32_BSI:sub_xmm
0, // GR32_BSI:sub_ymm
},
{ // GR32_CB
5, // GR32_CB:sub_8bit -> GR8_ABCD_L
4, // GR32_CB:sub_8bit_hi -> GR8_ABCD_H
0, // GR32_CB:sub_8bit_hi_phony
20, // GR32_CB:sub_16bit -> GR16_ABCD
0, // GR32_CB:sub_16bit_hi
0, // GR32_CB:sub_32bit
0, // GR32_CB:sub_mask_0
0, // GR32_CB:sub_mask_1
0, // GR32_CB:sub_xmm
0, // GR32_CB:sub_ymm
},
{ // GR32_DC
5, // GR32_DC:sub_8bit -> GR8_ABCD_L
4, // GR32_DC:sub_8bit_hi -> GR8_ABCD_H
0, // GR32_DC:sub_8bit_hi_phony
20, // GR32_DC:sub_16bit -> GR16_ABCD
0, // GR32_DC:sub_16bit_hi
0, // GR32_DC:sub_32bit
0, // GR32_DC:sub_mask_0
0, // GR32_DC:sub_mask_1
0, // GR32_DC:sub_xmm
0, // GR32_DC:sub_ymm
},
{ // GR32_DIBP
1, // GR32_DIBP:sub_8bit -> GR8
0, // GR32_DIBP:sub_8bit_hi
0, // GR32_DIBP:sub_8bit_hi_phony
8, // GR32_DIBP:sub_16bit -> GR16_NOREX
0, // GR32_DIBP:sub_16bit_hi
0, // GR32_DIBP:sub_32bit
0, // GR32_DIBP:sub_mask_0
0, // GR32_DIBP:sub_mask_1
0, // GR32_DIBP:sub_xmm
0, // GR32_DIBP:sub_ymm
},
{ // GR32_SIDI
1, // GR32_SIDI:sub_8bit -> GR8
0, // GR32_SIDI:sub_8bit_hi
0, // GR32_SIDI:sub_8bit_hi_phony
8, // GR32_SIDI:sub_16bit -> GR16_NOREX
0, // GR32_SIDI:sub_16bit_hi
0, // GR32_SIDI:sub_32bit
0, // GR32_SIDI:sub_mask_0
0, // GR32_SIDI:sub_mask_1
0, // GR32_SIDI:sub_xmm
0, // GR32_SIDI:sub_ymm
},
{ // LOW32_ADDR_ACCESS_RBP_with_sub_32bit
1, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit:sub_8bit -> GR8
0, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit:sub_8bit_hi
0, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit:sub_8bit_hi_phony
8, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit:sub_16bit -> GR16_NOREX
0, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit:sub_16bit_hi
59, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit:sub_32bit -> GR32_BPSP_and_GR32_DIBP
0, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit:sub_mask_0
0, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit:sub_mask_1
0, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit:sub_xmm
0, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit:sub_ymm
},
{ // CCR
0, // CCR:sub_8bit
0, // CCR:sub_8bit_hi
0, // CCR:sub_8bit_hi_phony
0, // CCR:sub_16bit
0, // CCR:sub_16bit_hi
0, // CCR:sub_32bit
0, // CCR:sub_mask_0
0, // CCR:sub_mask_1
0, // CCR:sub_xmm
0, // CCR:sub_ymm
},
{ // DFCCR
0, // DFCCR:sub_8bit
0, // DFCCR:sub_8bit_hi
0, // DFCCR:sub_8bit_hi_phony
0, // DFCCR:sub_16bit
0, // DFCCR:sub_16bit_hi
0, // DFCCR:sub_32bit
0, // DFCCR:sub_mask_0
0, // DFCCR:sub_mask_1
0, // DFCCR:sub_xmm
0, // DFCCR:sub_ymm
},
{ // GR32_ABCD_and_GR32_BSI
5, // GR32_ABCD_and_GR32_BSI:sub_8bit -> GR8_ABCD_L
4, // GR32_ABCD_and_GR32_BSI:sub_8bit_hi -> GR8_ABCD_H
0, // GR32_ABCD_and_GR32_BSI:sub_8bit_hi_phony
20, // GR32_ABCD_and_GR32_BSI:sub_16bit -> GR16_ABCD
0, // GR32_ABCD_and_GR32_BSI:sub_16bit_hi
0, // GR32_ABCD_and_GR32_BSI:sub_32bit
0, // GR32_ABCD_and_GR32_BSI:sub_mask_0
0, // GR32_ABCD_and_GR32_BSI:sub_mask_1
0, // GR32_ABCD_and_GR32_BSI:sub_xmm
0, // GR32_ABCD_and_GR32_BSI:sub_ymm
},
{ // GR32_AD_and_GR32_DC
5, // GR32_AD_and_GR32_DC:sub_8bit -> GR8_ABCD_L
4, // GR32_AD_and_GR32_DC:sub_8bit_hi -> GR8_ABCD_H
0, // GR32_AD_and_GR32_DC:sub_8bit_hi_phony
20, // GR32_AD_and_GR32_DC:sub_16bit -> GR16_ABCD
0, // GR32_AD_and_GR32_DC:sub_16bit_hi
0, // GR32_AD_and_GR32_DC:sub_32bit
0, // GR32_AD_and_GR32_DC:sub_mask_0
0, // GR32_AD_and_GR32_DC:sub_mask_1
0, // GR32_AD_and_GR32_DC:sub_xmm
0, // GR32_AD_and_GR32_DC:sub_ymm
},
{ // GR32_BPSP_and_GR32_DIBP
1, // GR32_BPSP_and_GR32_DIBP:sub_8bit -> GR8
0, // GR32_BPSP_and_GR32_DIBP:sub_8bit_hi
0, // GR32_BPSP_and_GR32_DIBP:sub_8bit_hi_phony
8, // GR32_BPSP_and_GR32_DIBP:sub_16bit -> GR16_NOREX
0, // GR32_BPSP_and_GR32_DIBP:sub_16bit_hi
0, // GR32_BPSP_and_GR32_DIBP:sub_32bit
0, // GR32_BPSP_and_GR32_DIBP:sub_mask_0
0, // GR32_BPSP_and_GR32_DIBP:sub_mask_1
0, // GR32_BPSP_and_GR32_DIBP:sub_xmm
0, // GR32_BPSP_and_GR32_DIBP:sub_ymm
},
{ // GR32_BPSP_and_GR32_TC
1, // GR32_BPSP_and_GR32_TC:sub_8bit -> GR8
0, // GR32_BPSP_and_GR32_TC:sub_8bit_hi
0, // GR32_BPSP_and_GR32_TC:sub_8bit_hi_phony
8, // GR32_BPSP_and_GR32_TC:sub_16bit -> GR16_NOREX
0, // GR32_BPSP_and_GR32_TC:sub_16bit_hi
0, // GR32_BPSP_and_GR32_TC:sub_32bit
0, // GR32_BPSP_and_GR32_TC:sub_mask_0
0, // GR32_BPSP_and_GR32_TC:sub_mask_1
0, // GR32_BPSP_and_GR32_TC:sub_xmm
0, // GR32_BPSP_and_GR32_TC:sub_ymm
},
{ // GR32_BSI_and_GR32_SIDI
1, // GR32_BSI_and_GR32_SIDI:sub_8bit -> GR8
0, // GR32_BSI_and_GR32_SIDI:sub_8bit_hi
0, // GR32_BSI_and_GR32_SIDI:sub_8bit_hi_phony
8, // GR32_BSI_and_GR32_SIDI:sub_16bit -> GR16_NOREX
0, // GR32_BSI_and_GR32_SIDI:sub_16bit_hi
0, // GR32_BSI_and_GR32_SIDI:sub_32bit
0, // GR32_BSI_and_GR32_SIDI:sub_mask_0
0, // GR32_BSI_and_GR32_SIDI:sub_mask_1
0, // GR32_BSI_and_GR32_SIDI:sub_xmm
0, // GR32_BSI_and_GR32_SIDI:sub_ymm
},
{ // GR32_CB_and_GR32_DC
5, // GR32_CB_and_GR32_DC:sub_8bit -> GR8_ABCD_L
4, // GR32_CB_and_GR32_DC:sub_8bit_hi -> GR8_ABCD_H
0, // GR32_CB_and_GR32_DC:sub_8bit_hi_phony
20, // GR32_CB_and_GR32_DC:sub_16bit -> GR16_ABCD
0, // GR32_CB_and_GR32_DC:sub_16bit_hi
0, // GR32_CB_and_GR32_DC:sub_32bit
0, // GR32_CB_and_GR32_DC:sub_mask_0
0, // GR32_CB_and_GR32_DC:sub_mask_1
0, // GR32_CB_and_GR32_DC:sub_xmm
0, // GR32_CB_and_GR32_DC:sub_ymm
},
{ // GR32_DIBP_and_GR32_SIDI
1, // GR32_DIBP_and_GR32_SIDI:sub_8bit -> GR8
0, // GR32_DIBP_and_GR32_SIDI:sub_8bit_hi
0, // GR32_DIBP_and_GR32_SIDI:sub_8bit_hi_phony
8, // GR32_DIBP_and_GR32_SIDI:sub_16bit -> GR16_NOREX
0, // GR32_DIBP_and_GR32_SIDI:sub_16bit_hi
0, // GR32_DIBP_and_GR32_SIDI:sub_32bit
0, // GR32_DIBP_and_GR32_SIDI:sub_mask_0
0, // GR32_DIBP_and_GR32_SIDI:sub_mask_1
0, // GR32_DIBP_and_GR32_SIDI:sub_xmm
0, // GR32_DIBP_and_GR32_SIDI:sub_ymm
},
{ // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
1, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit:sub_8bit -> GR8
0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit:sub_8bit_hi
0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit:sub_8bit_hi_phony
8, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit:sub_16bit -> GR16_NOREX
0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit:sub_16bit_hi
59, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit:sub_32bit -> GR32_BPSP_and_GR32_DIBP
0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit:sub_mask_0
0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit:sub_mask_1
0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit:sub_xmm
0, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit:sub_ymm
},
{ // LOW32_ADDR_ACCESS_with_sub_32bit
0, // LOW32_ADDR_ACCESS_with_sub_32bit:sub_8bit
0, // LOW32_ADDR_ACCESS_with_sub_32bit:sub_8bit_hi
0, // LOW32_ADDR_ACCESS_with_sub_32bit:sub_8bit_hi_phony
0, // LOW32_ADDR_ACCESS_with_sub_32bit:sub_16bit
0, // LOW32_ADDR_ACCESS_with_sub_32bit:sub_16bit_hi
0, // LOW32_ADDR_ACCESS_with_sub_32bit:sub_32bit
0, // LOW32_ADDR_ACCESS_with_sub_32bit:sub_mask_0
0, // LOW32_ADDR_ACCESS_with_sub_32bit:sub_mask_1
0, // LOW32_ADDR_ACCESS_with_sub_32bit:sub_xmm
0, // LOW32_ADDR_ACCESS_with_sub_32bit:sub_ymm
},
{ // RFP64
0, // RFP64:sub_8bit
0, // RFP64:sub_8bit_hi
0, // RFP64:sub_8bit_hi_phony
0, // RFP64:sub_16bit
0, // RFP64:sub_16bit_hi
0, // RFP64:sub_32bit
0, // RFP64:sub_mask_0
0, // RFP64:sub_mask_1
0, // RFP64:sub_xmm
0, // RFP64:sub_ymm
},
{ // FR64X
0, // FR64X:sub_8bit
0, // FR64X:sub_8bit_hi
0, // FR64X:sub_8bit_hi_phony
0, // FR64X:sub_16bit
0, // FR64X:sub_16bit_hi
0, // FR64X:sub_32bit
0, // FR64X:sub_mask_0
0, // FR64X:sub_mask_1
0, // FR64X:sub_xmm
0, // FR64X:sub_ymm
},
{ // GR64
1, // GR64:sub_8bit -> GR8
4, // GR64:sub_8bit_hi -> GR8_ABCD_H
0, // GR64:sub_8bit_hi_phony
7, // GR64:sub_16bit -> GR16
0, // GR64:sub_16bit_hi
36, // GR64:sub_32bit -> GR32
0, // GR64:sub_mask_0
0, // GR64:sub_mask_1
0, // GR64:sub_xmm
0, // GR64:sub_ymm
},
{ // CONTROL_REG
0, // CONTROL_REG:sub_8bit
0, // CONTROL_REG:sub_8bit_hi
0, // CONTROL_REG:sub_8bit_hi_phony
0, // CONTROL_REG:sub_16bit
0, // CONTROL_REG:sub_16bit_hi
0, // CONTROL_REG:sub_32bit
0, // CONTROL_REG:sub_mask_0
0, // CONTROL_REG:sub_mask_1
0, // CONTROL_REG:sub_xmm
0, // CONTROL_REG:sub_ymm
},
{ // FR64
0, // FR64:sub_8bit
0, // FR64:sub_8bit_hi
0, // FR64:sub_8bit_hi_phony
0, // FR64:sub_16bit
0, // FR64:sub_16bit_hi
0, // FR64:sub_32bit
0, // FR64:sub_mask_0
0, // FR64:sub_mask_1
0, // FR64:sub_xmm
0, // FR64:sub_ymm
},
{ // GR64_with_sub_8bit
1, // GR64_with_sub_8bit:sub_8bit -> GR8
4, // GR64_with_sub_8bit:sub_8bit_hi -> GR8_ABCD_H
0, // GR64_with_sub_8bit:sub_8bit_hi_phony
7, // GR64_with_sub_8bit:sub_16bit -> GR16
0, // GR64_with_sub_8bit:sub_16bit_hi
36, // GR64_with_sub_8bit:sub_32bit -> GR32
0, // GR64_with_sub_8bit:sub_mask_0
0, // GR64_with_sub_8bit:sub_mask_1
0, // GR64_with_sub_8bit:sub_xmm
0, // GR64_with_sub_8bit:sub_ymm
},
{ // GR64_NOSP
1, // GR64_NOSP:sub_8bit -> GR8
4, // GR64_NOSP:sub_8bit_hi -> GR8_ABCD_H
0, // GR64_NOSP:sub_8bit_hi_phony
7, // GR64_NOSP:sub_16bit -> GR16
0, // GR64_NOSP:sub_16bit_hi
37, // GR64_NOSP:sub_32bit -> GR32_NOSP
0, // GR64_NOSP:sub_mask_0
0, // GR64_NOSP:sub_mask_1
0, // GR64_NOSP:sub_xmm
0, // GR64_NOSP:sub_ymm
},
{ // GR64PLTSafe
1, // GR64PLTSafe:sub_8bit -> GR8
4, // GR64PLTSafe:sub_8bit_hi -> GR8_ABCD_H
0, // GR64PLTSafe:sub_8bit_hi_phony
7, // GR64PLTSafe:sub_16bit -> GR16
0, // GR64PLTSafe:sub_16bit_hi
37, // GR64PLTSafe:sub_32bit -> GR32_NOSP
0, // GR64PLTSafe:sub_mask_0
0, // GR64PLTSafe:sub_mask_1
0, // GR64PLTSafe:sub_xmm
0, // GR64PLTSafe:sub_ymm
},
{ // GR64_TC
1, // GR64_TC:sub_8bit -> GR8
4, // GR64_TC:sub_8bit_hi -> GR8_ABCD_H
0, // GR64_TC:sub_8bit_hi_phony
7, // GR64_TC:sub_16bit -> GR16
0, // GR64_TC:sub_16bit_hi
36, // GR64_TC:sub_32bit -> GR32
0, // GR64_TC:sub_mask_0
0, // GR64_TC:sub_mask_1
0, // GR64_TC:sub_xmm
0, // GR64_TC:sub_ymm
},
{ // GR64_NOREX
1, // GR64_NOREX:sub_8bit -> GR8
4, // GR64_NOREX:sub_8bit_hi -> GR8_ABCD_H
0, // GR64_NOREX:sub_8bit_hi_phony
8, // GR64_NOREX:sub_16bit -> GR16_NOREX
0, // GR64_NOREX:sub_16bit_hi
39, // GR64_NOREX:sub_32bit -> GR32_NOREX
0, // GR64_NOREX:sub_mask_0
0, // GR64_NOREX:sub_mask_1
0, // GR64_NOREX:sub_xmm
0, // GR64_NOREX:sub_ymm
},
{ // GR64_TCW64
1, // GR64_TCW64:sub_8bit -> GR8
4, // GR64_TCW64:sub_8bit_hi -> GR8_ABCD_H
0, // GR64_TCW64:sub_8bit_hi_phony
7, // GR64_TCW64:sub_16bit -> GR16
0, // GR64_TCW64:sub_16bit_hi
36, // GR64_TCW64:sub_32bit -> GR32
0, // GR64_TCW64:sub_mask_0
0, // GR64_TCW64:sub_mask_1
0, // GR64_TCW64:sub_xmm
0, // GR64_TCW64:sub_ymm
},
{ // GR64_TC_with_sub_8bit
1, // GR64_TC_with_sub_8bit:sub_8bit -> GR8
4, // GR64_TC_with_sub_8bit:sub_8bit_hi -> GR8_ABCD_H
0, // GR64_TC_with_sub_8bit:sub_8bit_hi_phony
7, // GR64_TC_with_sub_8bit:sub_16bit -> GR16
0, // GR64_TC_with_sub_8bit:sub_16bit_hi
36, // GR64_TC_with_sub_8bit:sub_32bit -> GR32
0, // GR64_TC_with_sub_8bit:sub_mask_0
0, // GR64_TC_with_sub_8bit:sub_mask_1
0, // GR64_TC_with_sub_8bit:sub_xmm
0, // GR64_TC_with_sub_8bit:sub_ymm
},
{ // GR64_NOSP_and_GR64_TC
1, // GR64_NOSP_and_GR64_TC:sub_8bit -> GR8
4, // GR64_NOSP_and_GR64_TC:sub_8bit_hi -> GR8_ABCD_H
0, // GR64_NOSP_and_GR64_TC:sub_8bit_hi_phony
7, // GR64_NOSP_and_GR64_TC:sub_16bit -> GR16
0, // GR64_NOSP_and_GR64_TC:sub_16bit_hi
37, // GR64_NOSP_and_GR64_TC:sub_32bit -> GR32_NOSP
0, // GR64_NOSP_and_GR64_TC:sub_mask_0
0, // GR64_NOSP_and_GR64_TC:sub_mask_1
0, // GR64_NOSP_and_GR64_TC:sub_xmm
0, // GR64_NOSP_and_GR64_TC:sub_ymm
},
{ // GR64_TCW64_with_sub_8bit
1, // GR64_TCW64_with_sub_8bit:sub_8bit -> GR8
4, // GR64_TCW64_with_sub_8bit:sub_8bit_hi -> GR8_ABCD_H
0, // GR64_TCW64_with_sub_8bit:sub_8bit_hi_phony
7, // GR64_TCW64_with_sub_8bit:sub_16bit -> GR16
0, // GR64_TCW64_with_sub_8bit:sub_16bit_hi
36, // GR64_TCW64_with_sub_8bit:sub_32bit -> GR32
0, // GR64_TCW64_with_sub_8bit:sub_mask_0
0, // GR64_TCW64_with_sub_8bit:sub_mask_1
0, // GR64_TCW64_with_sub_8bit:sub_xmm
0, // GR64_TCW64_with_sub_8bit:sub_ymm
},
{ // GR64_TC_and_GR64_TCW64
1, // GR64_TC_and_GR64_TCW64:sub_8bit -> GR8
4, // GR64_TC_and_GR64_TCW64:sub_8bit_hi -> GR8_ABCD_H
0, // GR64_TC_and_GR64_TCW64:sub_8bit_hi_phony
7, // GR64_TC_and_GR64_TCW64:sub_16bit -> GR16
0, // GR64_TC_and_GR64_TCW64:sub_16bit_hi
36, // GR64_TC_and_GR64_TCW64:sub_32bit -> GR32
0, // GR64_TC_and_GR64_TCW64:sub_mask_0
0, // GR64_TC_and_GR64_TCW64:sub_mask_1
0, // GR64_TC_and_GR64_TCW64:sub_xmm
0, // GR64_TC_and_GR64_TCW64:sub_ymm
},
{ // GR64_with_sub_16bit_in_GR16_NOREX
1, // GR64_with_sub_16bit_in_GR16_NOREX:sub_8bit -> GR8
4, // GR64_with_sub_16bit_in_GR16_NOREX:sub_8bit_hi -> GR8_ABCD_H
0, // GR64_with_sub_16bit_in_GR16_NOREX:sub_8bit_hi_phony
8, // GR64_with_sub_16bit_in_GR16_NOREX:sub_16bit -> GR16_NOREX
0, // GR64_with_sub_16bit_in_GR16_NOREX:sub_16bit_hi
39, // GR64_with_sub_16bit_in_GR16_NOREX:sub_32bit -> GR32_NOREX
0, // GR64_with_sub_16bit_in_GR16_NOREX:sub_mask_0
0, // GR64_with_sub_16bit_in_GR16_NOREX:sub_mask_1
0, // GR64_with_sub_16bit_in_GR16_NOREX:sub_xmm
0, // GR64_with_sub_16bit_in_GR16_NOREX:sub_ymm
},
{ // VK64
0, // VK64:sub_8bit
0, // VK64:sub_8bit_hi
0, // VK64:sub_8bit_hi_phony
0, // VK64:sub_16bit
0, // VK64:sub_16bit_hi
0, // VK64:sub_32bit
0, // VK64:sub_mask_0
0, // VK64:sub_mask_1
0, // VK64:sub_xmm
0, // VK64:sub_ymm
},
{ // VR64
0, // VR64:sub_8bit
0, // VR64:sub_8bit_hi
0, // VR64:sub_8bit_hi_phony
0, // VR64:sub_16bit
0, // VR64:sub_16bit_hi
0, // VR64:sub_32bit
0, // VR64:sub_mask_0
0, // VR64:sub_mask_1
0, // VR64:sub_xmm
0, // VR64:sub_ymm
},
{ // GR64PLTSafe_and_GR64_TC
1, // GR64PLTSafe_and_GR64_TC:sub_8bit -> GR8
4, // GR64PLTSafe_and_GR64_TC:sub_8bit_hi -> GR8_ABCD_H
0, // GR64PLTSafe_and_GR64_TC:sub_8bit_hi_phony
7, // GR64PLTSafe_and_GR64_TC:sub_16bit -> GR16
0, // GR64PLTSafe_and_GR64_TC:sub_16bit_hi
37, // GR64PLTSafe_and_GR64_TC:sub_32bit -> GR32_NOSP
0, // GR64PLTSafe_and_GR64_TC:sub_mask_0
0, // GR64PLTSafe_and_GR64_TC:sub_mask_1
0, // GR64PLTSafe_and_GR64_TC:sub_xmm
0, // GR64PLTSafe_and_GR64_TC:sub_ymm
},
{ // GR64_NOREX_NOSP
1, // GR64_NOREX_NOSP:sub_8bit -> GR8
4, // GR64_NOREX_NOSP:sub_8bit_hi -> GR8_ABCD_H
0, // GR64_NOREX_NOSP:sub_8bit_hi_phony
8, // GR64_NOREX_NOSP:sub_16bit -> GR16_NOREX
0, // GR64_NOREX_NOSP:sub_16bit_hi
41, // GR64_NOREX_NOSP:sub_32bit -> GR32_NOREX_NOSP
0, // GR64_NOREX_NOSP:sub_mask_0
0, // GR64_NOREX_NOSP:sub_mask_1
0, // GR64_NOREX_NOSP:sub_xmm
0, // GR64_NOREX_NOSP:sub_ymm
},
{ // GR64_NOREX_and_GR64_TC
1, // GR64_NOREX_and_GR64_TC:sub_8bit -> GR8
4, // GR64_NOREX_and_GR64_TC:sub_8bit_hi -> GR8_ABCD_H
0, // GR64_NOREX_and_GR64_TC:sub_8bit_hi_phony
8, // GR64_NOREX_and_GR64_TC:sub_16bit -> GR16_NOREX
0, // GR64_NOREX_and_GR64_TC:sub_16bit_hi
39, // GR64_NOREX_and_GR64_TC:sub_32bit -> GR32_NOREX
0, // GR64_NOREX_and_GR64_TC:sub_mask_0
0, // GR64_NOREX_and_GR64_TC:sub_mask_1
0, // GR64_NOREX_and_GR64_TC:sub_xmm
0, // GR64_NOREX_and_GR64_TC:sub_ymm
},
{ // GR64_NOSP_and_GR64_TCW64
1, // GR64_NOSP_and_GR64_TCW64:sub_8bit -> GR8
4, // GR64_NOSP_and_GR64_TCW64:sub_8bit_hi -> GR8_ABCD_H
0, // GR64_NOSP_and_GR64_TCW64:sub_8bit_hi_phony
7, // GR64_NOSP_and_GR64_TCW64:sub_16bit -> GR16
0, // GR64_NOSP_and_GR64_TCW64:sub_16bit_hi
37, // GR64_NOSP_and_GR64_TCW64:sub_32bit -> GR32_NOSP
0, // GR64_NOSP_and_GR64_TCW64:sub_mask_0
0, // GR64_NOSP_and_GR64_TCW64:sub_mask_1
0, // GR64_NOSP_and_GR64_TCW64:sub_xmm
0, // GR64_NOSP_and_GR64_TCW64:sub_ymm
},
{ // GR64_TCW64_and_GR64_TC_with_sub_8bit
1, // GR64_TCW64_and_GR64_TC_with_sub_8bit:sub_8bit -> GR8
4, // GR64_TCW64_and_GR64_TC_with_sub_8bit:sub_8bit_hi -> GR8_ABCD_H
0, // GR64_TCW64_and_GR64_TC_with_sub_8bit:sub_8bit_hi_phony
7, // GR64_TCW64_and_GR64_TC_with_sub_8bit:sub_16bit -> GR16
0, // GR64_TCW64_and_GR64_TC_with_sub_8bit:sub_16bit_hi
36, // GR64_TCW64_and_GR64_TC_with_sub_8bit:sub_32bit -> GR32
0, // GR64_TCW64_and_GR64_TC_with_sub_8bit:sub_mask_0
0, // GR64_TCW64_and_GR64_TC_with_sub_8bit:sub_mask_1
0, // GR64_TCW64_and_GR64_TC_with_sub_8bit:sub_xmm
0, // GR64_TCW64_and_GR64_TC_with_sub_8bit:sub_ymm
},
{ // VK64WM
0, // VK64WM:sub_8bit
0, // VK64WM:sub_8bit_hi
0, // VK64WM:sub_8bit_hi_phony
0, // VK64WM:sub_16bit
0, // VK64WM:sub_16bit_hi
0, // VK64WM:sub_32bit
0, // VK64WM:sub_mask_0
0, // VK64WM:sub_mask_1
0, // VK64WM:sub_xmm
0, // VK64WM:sub_ymm
},
{ // GR64_TC_and_GR64_NOSP_and_GR64_TCW64
1, // GR64_TC_and_GR64_NOSP_and_GR64_TCW64:sub_8bit -> GR8
4, // GR64_TC_and_GR64_NOSP_and_GR64_TCW64:sub_8bit_hi -> GR8_ABCD_H
0, // GR64_TC_and_GR64_NOSP_and_GR64_TCW64:sub_8bit_hi_phony
7, // GR64_TC_and_GR64_NOSP_and_GR64_TCW64:sub_16bit -> GR16
0, // GR64_TC_and_GR64_NOSP_and_GR64_TCW64:sub_16bit_hi
37, // GR64_TC_and_GR64_NOSP_and_GR64_TCW64:sub_32bit -> GR32_NOSP
0, // GR64_TC_and_GR64_NOSP_and_GR64_TCW64:sub_mask_0
0, // GR64_TC_and_GR64_NOSP_and_GR64_TCW64:sub_mask_1
0, // GR64_TC_and_GR64_NOSP_and_GR64_TCW64:sub_xmm
0, // GR64_TC_and_GR64_NOSP_and_GR64_TCW64:sub_ymm
},
{ // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX
1, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX:sub_8bit -> GR8
4, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX:sub_8bit_hi -> GR8_ABCD_H
0, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX:sub_8bit_hi_phony
8, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX:sub_16bit -> GR16_NOREX
0, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX:sub_16bit_hi
39, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX:sub_32bit -> GR32_NOREX
0, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX:sub_mask_0
0, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX:sub_mask_1
0, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX:sub_xmm
0, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX:sub_ymm
},
{ // GR64PLTSafe_and_GR64_TCW64
1, // GR64PLTSafe_and_GR64_TCW64:sub_8bit -> GR8
4, // GR64PLTSafe_and_GR64_TCW64:sub_8bit_hi -> GR8_ABCD_H
0, // GR64PLTSafe_and_GR64_TCW64:sub_8bit_hi_phony
7, // GR64PLTSafe_and_GR64_TCW64:sub_16bit -> GR16
0, // GR64PLTSafe_and_GR64_TCW64:sub_16bit_hi
37, // GR64PLTSafe_and_GR64_TCW64:sub_32bit -> GR32_NOSP
0, // GR64PLTSafe_and_GR64_TCW64:sub_mask_0
0, // GR64PLTSafe_and_GR64_TCW64:sub_mask_1
0, // GR64PLTSafe_and_GR64_TCW64:sub_xmm
0, // GR64PLTSafe_and_GR64_TCW64:sub_ymm
},
{ // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC
1, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC:sub_8bit -> GR8
4, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC:sub_8bit_hi -> GR8_ABCD_H
0, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC:sub_8bit_hi_phony
8, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC:sub_16bit -> GR16_NOREX
0, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC:sub_16bit_hi
41, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC:sub_32bit -> GR32_NOREX_NOSP
0, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC:sub_mask_0
0, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC:sub_mask_1
0, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC:sub_xmm
0, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC:sub_ymm
},
{ // GR64_NOREX_and_GR64_TCW64
1, // GR64_NOREX_and_GR64_TCW64:sub_8bit -> GR8
4, // GR64_NOREX_and_GR64_TCW64:sub_8bit_hi -> GR8_ABCD_H
0, // GR64_NOREX_and_GR64_TCW64:sub_8bit_hi_phony
8, // GR64_NOREX_and_GR64_TCW64:sub_16bit -> GR16_NOREX
0, // GR64_NOREX_and_GR64_TCW64:sub_16bit_hi
45, // GR64_NOREX_and_GR64_TCW64:sub_32bit -> GR32_TC
0, // GR64_NOREX_and_GR64_TCW64:sub_mask_0
0, // GR64_NOREX_and_GR64_TCW64:sub_mask_1
0, // GR64_NOREX_and_GR64_TCW64:sub_xmm
0, // GR64_NOREX_and_GR64_TCW64:sub_ymm
},
{ // GR64_ABCD
5, // GR64_ABCD:sub_8bit -> GR8_ABCD_L
4, // GR64_ABCD:sub_8bit_hi -> GR8_ABCD_H
0, // GR64_ABCD:sub_8bit_hi_phony
20, // GR64_ABCD:sub_16bit -> GR16_ABCD
0, // GR64_ABCD:sub_16bit_hi
44, // GR64_ABCD:sub_32bit -> GR32_ABCD
0, // GR64_ABCD:sub_mask_0
0, // GR64_ABCD:sub_mask_1
0, // GR64_ABCD:sub_xmm
0, // GR64_ABCD:sub_ymm
},
{ // GR64_with_sub_32bit_in_GR32_TC
1, // GR64_with_sub_32bit_in_GR32_TC:sub_8bit -> GR8
4, // GR64_with_sub_32bit_in_GR32_TC:sub_8bit_hi -> GR8_ABCD_H
0, // GR64_with_sub_32bit_in_GR32_TC:sub_8bit_hi_phony
8, // GR64_with_sub_32bit_in_GR32_TC:sub_16bit -> GR16_NOREX
0, // GR64_with_sub_32bit_in_GR32_TC:sub_16bit_hi
45, // GR64_with_sub_32bit_in_GR32_TC:sub_32bit -> GR32_TC
0, // GR64_with_sub_32bit_in_GR32_TC:sub_mask_0
0, // GR64_with_sub_32bit_in_GR32_TC:sub_mask_1
0, // GR64_with_sub_32bit_in_GR32_TC:sub_xmm
0, // GR64_with_sub_32bit_in_GR32_TC:sub_ymm
},
{ // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
5, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC:sub_8bit -> GR8_ABCD_L
4, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC:sub_8bit_hi -> GR8_ABCD_H
0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC:sub_8bit_hi_phony
20, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC:sub_16bit -> GR16_ABCD
0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC:sub_16bit_hi
46, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC:sub_32bit -> GR32_ABCD_and_GR32_TC
0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC:sub_mask_0
0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC:sub_mask_1
0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC:sub_xmm
0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC:sub_ymm
},
{ // GR64_AD
5, // GR64_AD:sub_8bit -> GR8_ABCD_L
4, // GR64_AD:sub_8bit_hi -> GR8_ABCD_H
0, // GR64_AD:sub_8bit_hi_phony
20, // GR64_AD:sub_16bit -> GR16_ABCD
0, // GR64_AD:sub_16bit_hi
47, // GR64_AD:sub_32bit -> GR32_AD
0, // GR64_AD:sub_mask_0
0, // GR64_AD:sub_mask_1
0, // GR64_AD:sub_xmm
0, // GR64_AD:sub_ymm
},
{ // GR64_and_LOW32_ADDR_ACCESS_RBP
1, // GR64_and_LOW32_ADDR_ACCESS_RBP:sub_8bit -> GR8
0, // GR64_and_LOW32_ADDR_ACCESS_RBP:sub_8bit_hi
0, // GR64_and_LOW32_ADDR_ACCESS_RBP:sub_8bit_hi_phony
8, // GR64_and_LOW32_ADDR_ACCESS_RBP:sub_16bit -> GR16_NOREX
0, // GR64_and_LOW32_ADDR_ACCESS_RBP:sub_16bit_hi
59, // GR64_and_LOW32_ADDR_ACCESS_RBP:sub_32bit -> GR32_BPSP_and_GR32_DIBP
0, // GR64_and_LOW32_ADDR_ACCESS_RBP:sub_mask_0
0, // GR64_and_LOW32_ADDR_ACCESS_RBP:sub_mask_1
0, // GR64_and_LOW32_ADDR_ACCESS_RBP:sub_xmm
0, // GR64_and_LOW32_ADDR_ACCESS_RBP:sub_ymm
},
{ // GR64_with_sub_32bit_in_GR32_BPSP
1, // GR64_with_sub_32bit_in_GR32_BPSP:sub_8bit -> GR8
0, // GR64_with_sub_32bit_in_GR32_BPSP:sub_8bit_hi
0, // GR64_with_sub_32bit_in_GR32_BPSP:sub_8bit_hi_phony
8, // GR64_with_sub_32bit_in_GR32_BPSP:sub_16bit -> GR16_NOREX
0, // GR64_with_sub_32bit_in_GR32_BPSP:sub_16bit_hi
48, // GR64_with_sub_32bit_in_GR32_BPSP:sub_32bit -> GR32_BPSP
0, // GR64_with_sub_32bit_in_GR32_BPSP:sub_mask_0
0, // GR64_with_sub_32bit_in_GR32_BPSP:sub_mask_1
0, // GR64_with_sub_32bit_in_GR32_BPSP:sub_xmm
0, // GR64_with_sub_32bit_in_GR32_BPSP:sub_ymm
},
{ // GR64_with_sub_32bit_in_GR32_BSI
1, // GR64_with_sub_32bit_in_GR32_BSI:sub_8bit -> GR8
4, // GR64_with_sub_32bit_in_GR32_BSI:sub_8bit_hi -> GR8_ABCD_H
0, // GR64_with_sub_32bit_in_GR32_BSI:sub_8bit_hi_phony
8, // GR64_with_sub_32bit_in_GR32_BSI:sub_16bit -> GR16_NOREX
0, // GR64_with_sub_32bit_in_GR32_BSI:sub_16bit_hi
49, // GR64_with_sub_32bit_in_GR32_BSI:sub_32bit -> GR32_BSI
0, // GR64_with_sub_32bit_in_GR32_BSI:sub_mask_0
0, // GR64_with_sub_32bit_in_GR32_BSI:sub_mask_1
0, // GR64_with_sub_32bit_in_GR32_BSI:sub_xmm
0, // GR64_with_sub_32bit_in_GR32_BSI:sub_ymm
},
{ // GR64_with_sub_32bit_in_GR32_CB
5, // GR64_with_sub_32bit_in_GR32_CB:sub_8bit -> GR8_ABCD_L
4, // GR64_with_sub_32bit_in_GR32_CB:sub_8bit_hi -> GR8_ABCD_H
0, // GR64_with_sub_32bit_in_GR32_CB:sub_8bit_hi_phony
20, // GR64_with_sub_32bit_in_GR32_CB:sub_16bit -> GR16_ABCD
0, // GR64_with_sub_32bit_in_GR32_CB:sub_16bit_hi
50, // GR64_with_sub_32bit_in_GR32_CB:sub_32bit -> GR32_CB
0, // GR64_with_sub_32bit_in_GR32_CB:sub_mask_0
0, // GR64_with_sub_32bit_in_GR32_CB:sub_mask_1
0, // GR64_with_sub_32bit_in_GR32_CB:sub_xmm
0, // GR64_with_sub_32bit_in_GR32_CB:sub_ymm
},
{ // GR64_with_sub_32bit_in_GR32_DC
5, // GR64_with_sub_32bit_in_GR32_DC:sub_8bit -> GR8_ABCD_L
4, // GR64_with_sub_32bit_in_GR32_DC:sub_8bit_hi -> GR8_ABCD_H
0, // GR64_with_sub_32bit_in_GR32_DC:sub_8bit_hi_phony
20, // GR64_with_sub_32bit_in_GR32_DC:sub_16bit -> GR16_ABCD
0, // GR64_with_sub_32bit_in_GR32_DC:sub_16bit_hi
51, // GR64_with_sub_32bit_in_GR32_DC:sub_32bit -> GR32_DC
0, // GR64_with_sub_32bit_in_GR32_DC:sub_mask_0
0, // GR64_with_sub_32bit_in_GR32_DC:sub_mask_1
0, // GR64_with_sub_32bit_in_GR32_DC:sub_xmm
0, // GR64_with_sub_32bit_in_GR32_DC:sub_ymm
},
{ // GR64_with_sub_32bit_in_GR32_DIBP
1, // GR64_with_sub_32bit_in_GR32_DIBP:sub_8bit -> GR8
0, // GR64_with_sub_32bit_in_GR32_DIBP:sub_8bit_hi
0, // GR64_with_sub_32bit_in_GR32_DIBP:sub_8bit_hi_phony
8, // GR64_with_sub_32bit_in_GR32_DIBP:sub_16bit -> GR16_NOREX
0, // GR64_with_sub_32bit_in_GR32_DIBP:sub_16bit_hi
52, // GR64_with_sub_32bit_in_GR32_DIBP:sub_32bit -> GR32_DIBP
0, // GR64_with_sub_32bit_in_GR32_DIBP:sub_mask_0
0, // GR64_with_sub_32bit_in_GR32_DIBP:sub_mask_1
0, // GR64_with_sub_32bit_in_GR32_DIBP:sub_xmm
0, // GR64_with_sub_32bit_in_GR32_DIBP:sub_ymm
},
{ // GR64_with_sub_32bit_in_GR32_SIDI
1, // GR64_with_sub_32bit_in_GR32_SIDI:sub_8bit -> GR8
0, // GR64_with_sub_32bit_in_GR32_SIDI:sub_8bit_hi
0, // GR64_with_sub_32bit_in_GR32_SIDI:sub_8bit_hi_phony
8, // GR64_with_sub_32bit_in_GR32_SIDI:sub_16bit -> GR16_NOREX
0, // GR64_with_sub_32bit_in_GR32_SIDI:sub_16bit_hi
53, // GR64_with_sub_32bit_in_GR32_SIDI:sub_32bit -> GR32_SIDI
0, // GR64_with_sub_32bit_in_GR32_SIDI:sub_mask_0
0, // GR64_with_sub_32bit_in_GR32_SIDI:sub_mask_1
0, // GR64_with_sub_32bit_in_GR32_SIDI:sub_xmm
0, // GR64_with_sub_32bit_in_GR32_SIDI:sub_ymm
},
{ // GR64_and_LOW32_ADDR_ACCESS
0, // GR64_and_LOW32_ADDR_ACCESS:sub_8bit
0, // GR64_and_LOW32_ADDR_ACCESS:sub_8bit_hi
0, // GR64_and_LOW32_ADDR_ACCESS:sub_8bit_hi_phony
0, // GR64_and_LOW32_ADDR_ACCESS:sub_16bit
0, // GR64_and_LOW32_ADDR_ACCESS:sub_16bit_hi
0, // GR64_and_LOW32_ADDR_ACCESS:sub_32bit
0, // GR64_and_LOW32_ADDR_ACCESS:sub_mask_0
0, // GR64_and_LOW32_ADDR_ACCESS:sub_mask_1
0, // GR64_and_LOW32_ADDR_ACCESS:sub_xmm
0, // GR64_and_LOW32_ADDR_ACCESS:sub_ymm
},
{ // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
5, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI:sub_8bit -> GR8_ABCD_L
4, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI:sub_8bit_hi -> GR8_ABCD_H
0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI:sub_8bit_hi_phony
20, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI:sub_16bit -> GR16_ABCD
0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI:sub_16bit_hi
57, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI:sub_32bit -> GR32_ABCD_and_GR32_BSI
0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI:sub_mask_0
0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI:sub_mask_1
0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI:sub_xmm
0, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI:sub_ymm
},
{ // GR64_with_sub_32bit_in_GR32_AD_and_GR32_DC
5, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_DC:sub_8bit -> GR8_ABCD_L
4, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_DC:sub_8bit_hi -> GR8_ABCD_H
0, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_DC:sub_8bit_hi_phony
20, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_DC:sub_16bit -> GR16_ABCD
0, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_DC:sub_16bit_hi
58, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_DC:sub_32bit -> GR32_AD_and_GR32_DC
0, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_DC:sub_mask_0
0, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_DC:sub_mask_1
0, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_DC:sub_xmm
0, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_DC:sub_ymm
},
{ // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
1, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP:sub_8bit -> GR8
0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP:sub_8bit_hi
0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP:sub_8bit_hi_phony
8, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP:sub_16bit -> GR16_NOREX
0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP:sub_16bit_hi
59, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP:sub_32bit -> GR32_BPSP_and_GR32_DIBP
0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP:sub_mask_0
0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP:sub_mask_1
0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP:sub_xmm
0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP:sub_ymm
},
{ // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC
1, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC:sub_8bit -> GR8
0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC:sub_8bit_hi
0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC:sub_8bit_hi_phony
8, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC:sub_16bit -> GR16_NOREX
0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC:sub_16bit_hi
60, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC:sub_32bit -> GR32_BPSP_and_GR32_TC
0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC:sub_mask_0
0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC:sub_mask_1
0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC:sub_xmm
0, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC:sub_ymm
},
{ // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI
1, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI:sub_8bit -> GR8
0, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI:sub_8bit_hi
0, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI:sub_8bit_hi_phony
8, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI:sub_16bit -> GR16_NOREX
0, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI:sub_16bit_hi
61, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI:sub_32bit -> GR32_BSI_and_GR32_SIDI
0, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI:sub_mask_0
0, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI:sub_mask_1
0, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI:sub_xmm
0, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI:sub_ymm
},
{ // GR64_with_sub_32bit_in_GR32_CB_and_GR32_DC
5, // GR64_with_sub_32bit_in_GR32_CB_and_GR32_DC:sub_8bit -> GR8_ABCD_L
4, // GR64_with_sub_32bit_in_GR32_CB_and_GR32_DC:sub_8bit_hi -> GR8_ABCD_H
0, // GR64_with_sub_32bit_in_GR32_CB_and_GR32_DC:sub_8bit_hi_phony
20, // GR64_with_sub_32bit_in_GR32_CB_and_GR32_DC:sub_16bit -> GR16_ABCD
0, // GR64_with_sub_32bit_in_GR32_CB_and_GR32_DC:sub_16bit_hi
62, // GR64_with_sub_32bit_in_GR32_CB_and_GR32_DC:sub_32bit -> GR32_CB_and_GR32_DC
0, // GR64_with_sub_32bit_in_GR32_CB_and_GR32_DC:sub_mask_0
0, // GR64_with_sub_32bit_in_GR32_CB_and_GR32_DC:sub_mask_1
0, // GR64_with_sub_32bit_in_GR32_CB_and_GR32_DC:sub_xmm
0, // GR64_with_sub_32bit_in_GR32_CB_and_GR32_DC:sub_ymm
},
{ // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI
1, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI:sub_8bit -> GR8
0, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI:sub_8bit_hi
0, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI:sub_8bit_hi_phony
8, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI:sub_16bit -> GR16_NOREX
0, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI:sub_16bit_hi
63, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI:sub_32bit -> GR32_DIBP_and_GR32_SIDI
0, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI:sub_mask_0
0, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI:sub_mask_1
0, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI:sub_xmm
0, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI:sub_ymm
},
{ // RST
0, // RST:sub_8bit
0, // RST:sub_8bit_hi
0, // RST:sub_8bit_hi_phony
0, // RST:sub_16bit
0, // RST:sub_16bit_hi
0, // RST:sub_32bit
0, // RST:sub_mask_0
0, // RST:sub_mask_1
0, // RST:sub_xmm
0, // RST:sub_ymm
},
{ // RFP80
0, // RFP80:sub_8bit
0, // RFP80:sub_8bit_hi
0, // RFP80:sub_8bit_hi_phony
0, // RFP80:sub_16bit
0, // RFP80:sub_16bit_hi
0, // RFP80:sub_32bit
0, // RFP80:sub_mask_0
0, // RFP80:sub_mask_1
0, // RFP80:sub_xmm
0, // RFP80:sub_ymm
},
{ // RFP80_7
0, // RFP80_7:sub_8bit
0, // RFP80_7:sub_8bit_hi
0, // RFP80_7:sub_8bit_hi_phony
0, // RFP80_7:sub_16bit
0, // RFP80_7:sub_16bit_hi
0, // RFP80_7:sub_32bit
0, // RFP80_7:sub_mask_0
0, // RFP80_7:sub_mask_1
0, // RFP80_7:sub_xmm
0, // RFP80_7:sub_ymm
},
{ // VR128X
0, // VR128X:sub_8bit
0, // VR128X:sub_8bit_hi
0, // VR128X:sub_8bit_hi_phony
0, // VR128X:sub_16bit
0, // VR128X:sub_16bit_hi
0, // VR128X:sub_32bit
0, // VR128X:sub_mask_0
0, // VR128X:sub_mask_1
0, // VR128X:sub_xmm
0, // VR128X:sub_ymm
},
{ // VR128
0, // VR128:sub_8bit
0, // VR128:sub_8bit_hi
0, // VR128:sub_8bit_hi_phony
0, // VR128:sub_16bit
0, // VR128:sub_16bit_hi
0, // VR128:sub_32bit
0, // VR128:sub_mask_0
0, // VR128:sub_mask_1
0, // VR128:sub_xmm
0, // VR128:sub_ymm
},
{ // VR256X
0, // VR256X:sub_8bit
0, // VR256X:sub_8bit_hi
0, // VR256X:sub_8bit_hi_phony
0, // VR256X:sub_16bit
0, // VR256X:sub_16bit_hi
0, // VR256X:sub_32bit
0, // VR256X:sub_mask_0
0, // VR256X:sub_mask_1
22, // VR256X:sub_xmm -> FR16X
0, // VR256X:sub_ymm
},
{ // VR256
0, // VR256:sub_8bit
0, // VR256:sub_8bit_hi
0, // VR256:sub_8bit_hi_phony
0, // VR256:sub_16bit
0, // VR256:sub_16bit_hi
0, // VR256:sub_32bit
0, // VR256:sub_mask_0
0, // VR256:sub_mask_1
23, // VR256:sub_xmm -> FR16
0, // VR256:sub_ymm
},
{ // VR512
0, // VR512:sub_8bit
0, // VR512:sub_8bit_hi
0, // VR512:sub_8bit_hi_phony
0, // VR512:sub_16bit
0, // VR512:sub_16bit_hi
0, // VR512:sub_32bit
0, // VR512:sub_mask_0
0, // VR512:sub_mask_1
22, // VR512:sub_xmm -> FR16X
119, // VR512:sub_ymm -> VR256X
},
{ // VR512_0_15
0, // VR512_0_15:sub_8bit
0, // VR512_0_15:sub_8bit_hi
0, // VR512_0_15:sub_8bit_hi_phony
0, // VR512_0_15:sub_16bit
0, // VR512_0_15:sub_16bit_hi
0, // VR512_0_15:sub_32bit
0, // VR512_0_15:sub_mask_0
0, // VR512_0_15:sub_mask_1
23, // VR512_0_15:sub_xmm -> FR16
120, // VR512_0_15:sub_ymm -> VR256
},
{ // TILE
0, // TILE:sub_8bit
0, // TILE:sub_8bit_hi
0, // TILE:sub_8bit_hi_phony
0, // TILE:sub_16bit
0, // TILE:sub_16bit_hi
0, // TILE:sub_32bit
0, // TILE:sub_mask_0
0, // TILE:sub_mask_1
0, // TILE:sub_xmm
0, // TILE:sub_ymm
},
};
assert(RC && "Missing regclass");
if (!Idx) return RC;
--Idx;
assert(Idx < 10 && "Bad subreg");
unsigned TV = Table[RC->getID()][Idx];
return TV ? getRegClass(TV - 1) : nullptr;
}
/// Get the weight in units of pressure for this register class.
const RegClassWeight &X86GenRegisterInfo::
getRegClassWeight(const TargetRegisterClass *RC) const {
static const RegClassWeight RCWeightTable[] = {
{1, 20}, // GR8
{0, 0}, // GRH8
{1, 8}, // GR8_NOREX
{1, 4}, // GR8_ABCD_H
{1, 4}, // GR8_ABCD_L
{0, 0}, // GRH16
{2, 32}, // GR16
{2, 16}, // GR16_NOREX
{1, 8}, // VK1
{1, 8}, // VK16
{1, 8}, // VK2
{1, 8}, // VK4
{1, 8}, // VK8
{1, 7}, // VK16WM
{1, 7}, // VK1WM
{1, 7}, // VK2WM
{1, 7}, // VK4WM
{1, 7}, // VK8WM
{1, 6}, // SEGMENT_REG
{2, 8}, // GR16_ABCD
{0, 0}, // FPCCR
{1, 32}, // FR16X
{1, 16}, // FR16
{2, 8}, // VK16PAIR
{2, 8}, // VK1PAIR
{2, 8}, // VK2PAIR
{2, 8}, // VK4PAIR
{2, 8}, // VK8PAIR
{2, 6}, // VK16PAIR_with_sub_mask_0_in_VK16WM
{1, 32}, // FR32X
{2, 34}, // LOW32_ADDR_ACCESS_RBP
{2, 34}, // LOW32_ADDR_ACCESS
{2, 32}, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit
{1, 16}, // DEBUG_REG
{1, 16}, // FR32
{2, 32}, // GR32
{2, 30}, // GR32_NOSP
{2, 16}, // LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX
{2, 16}, // GR32_NOREX
{1, 8}, // VK32
{2, 14}, // GR32_NOREX_NOSP
{1, 7}, // RFP32
{1, 7}, // VK32WM
{2, 8}, // GR32_ABCD
{2, 8}, // GR32_TC
{2, 6}, // GR32_ABCD_and_GR32_TC
{2, 4}, // GR32_AD
{2, 4}, // GR32_BPSP
{2, 4}, // GR32_BSI
{2, 4}, // GR32_CB
{2, 4}, // GR32_DC
{2, 4}, // GR32_DIBP
{2, 4}, // GR32_SIDI
{2, 4}, // LOW32_ADDR_ACCESS_RBP_with_sub_32bit
{0, 0}, // CCR
{0, 0}, // DFCCR
{2, 2}, // GR32_ABCD_and_GR32_BSI
{2, 2}, // GR32_AD_and_GR32_DC
{2, 2}, // GR32_BPSP_and_GR32_DIBP
{2, 2}, // GR32_BPSP_and_GR32_TC
{2, 2}, // GR32_BSI_and_GR32_SIDI
{2, 2}, // GR32_CB_and_GR32_DC
{2, 2}, // GR32_DIBP_and_GR32_SIDI
{2, 2}, // LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit
{2, 2}, // LOW32_ADDR_ACCESS_with_sub_32bit
{1, 7}, // RFP64
{1, 32}, // FR64X
{2, 34}, // GR64
{1, 16}, // CONTROL_REG
{1, 16}, // FR64
{2, 32}, // GR64_with_sub_8bit
{2, 30}, // GR64_NOSP
{2, 26}, // GR64PLTSafe
{2, 20}, // GR64_TC
{2, 18}, // GR64_NOREX
{2, 18}, // GR64_TCW64
{2, 18}, // GR64_TC_with_sub_8bit
{2, 16}, // GR64_NOSP_and_GR64_TC
{2, 16}, // GR64_TCW64_with_sub_8bit
{2, 16}, // GR64_TC_and_GR64_TCW64
{2, 16}, // GR64_with_sub_16bit_in_GR16_NOREX
{1, 8}, // VK64
{1, 8}, // VR64
{2, 14}, // GR64PLTSafe_and_GR64_TC
{2, 14}, // GR64_NOREX_NOSP
{2, 14}, // GR64_NOREX_and_GR64_TC
{2, 14}, // GR64_NOSP_and_GR64_TCW64
{2, 14}, // GR64_TCW64_and_GR64_TC_with_sub_8bit
{1, 7}, // VK64WM
{2, 12}, // GR64_TC_and_GR64_NOSP_and_GR64_TCW64
{2, 12}, // GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX
{2, 10}, // GR64PLTSafe_and_GR64_TCW64
{2, 10}, // GR64_NOREX_and_GR64PLTSafe_and_GR64_TC
{2, 10}, // GR64_NOREX_and_GR64_TCW64
{2, 8}, // GR64_ABCD
{2, 8}, // GR64_with_sub_32bit_in_GR32_TC
{2, 6}, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC
{2, 4}, // GR64_AD
{2, 4}, // GR64_and_LOW32_ADDR_ACCESS_RBP
{2, 4}, // GR64_with_sub_32bit_in_GR32_BPSP
{2, 4}, // GR64_with_sub_32bit_in_GR32_BSI
{2, 4}, // GR64_with_sub_32bit_in_GR32_CB
{2, 4}, // GR64_with_sub_32bit_in_GR32_DC
{2, 4}, // GR64_with_sub_32bit_in_GR32_DIBP
{2, 4}, // GR64_with_sub_32bit_in_GR32_SIDI
{2, 2}, // GR64_and_LOW32_ADDR_ACCESS
{2, 2}, // GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI
{2, 2}, // GR64_with_sub_32bit_in_GR32_AD_and_GR32_DC
{2, 2}, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP
{2, 2}, // GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC
{2, 2}, // GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI
{2, 2}, // GR64_with_sub_32bit_in_GR32_CB_and_GR32_DC
{2, 2}, // GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI
{0, 0}, // RST
{1, 7}, // RFP80
{0, 0}, // RFP80_7
{1, 32}, // VR128X
{1, 16}, // VR128
{1, 32}, // VR256X
{1, 16}, // VR256
{1, 32}, // VR512
{1, 16}, // VR512_0_15
{1, 8}, // TILE
};
return RCWeightTable[RC->getID()];
}
/// Get the weight in units of pressure for this register unit.
unsigned X86GenRegisterInfo::
getRegUnitWeight(unsigned RegUnit) const {
assert(RegUnit < 173 && "invalid register unit");
// All register units have unit weight.
return 1;
}
// Get the number of dimensions of register pressure.
unsigned X86GenRegisterInfo::getNumRegPressureSets() const {
return 34;
}
// Get the name of this register unit pressure set.
const char *X86GenRegisterInfo::
getRegPressureSetName(unsigned Idx) const {
static const char *PressureNameTable[] = {
"SEGMENT_REG",
"GR32_BPSP",
"LOW32_ADDR_ACCESS_with_sub_32bit",
"GR32_BSI",
"GR32_SIDI",
"GR32_DIBP_with_GR32_SIDI",
"GR32_DIBP_with_LOW32_ADDR_ACCESS_with_sub_32bit",
"RFP32",
"GR8_ABCD_H_with_GR32_BSI",
"GR8_ABCD_L_with_GR32_BSI",
"VK1",
"VR64",
"TILE",
"GR8_NOREX",
"GR32_TC",
"GR32_BPSP_with_GR32_TC",
"FR16",
"DEBUG_REG",
"CONTROL_REG",
"GR64_NOREX",
"GR64_TCW64",
"GR32_BPSP_with_GR64_TCW64",
"GR8",
"GR8_with_GR32_DIBP",
"GR8_with_GR32_BSI",
"GR64_TC_with_GR64_TCW64",
"GR8_with_LOW32_ADDR_ACCESS_with_sub_32bit",
"GR8_with_GR64_NOREX",
"GR64_TC",
"GR8_with_GR64_TCW64",
"GR8_with_GR64_TC",
"GR8_with_GR64PLTSafe",
"FR16X",
"GR16",
};
return PressureNameTable[Idx];
}
// Get the register unit pressure limit for this dimension.
// This limit must be adjusted dynamically for reserved registers.
unsigned X86GenRegisterInfo::
getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
static const uint8_t PressureLimitTable[] = {
6, // 0: SEGMENT_REG
6, // 1: GR32_BPSP
6, // 2: LOW32_ADDR_ACCESS_with_sub_32bit
6, // 3: GR32_BSI
6, // 4: GR32_SIDI
6, // 5: GR32_DIBP_with_GR32_SIDI
6, // 6: GR32_DIBP_with_LOW32_ADDR_ACCESS_with_sub_32bit
7, // 7: RFP32
7, // 8: GR8_ABCD_H_with_GR32_BSI
7, // 9: GR8_ABCD_L_with_GR32_BSI
8, // 10: VK1
8, // 11: VR64
8, // 12: TILE
10, // 13: GR8_NOREX
12, // 14: GR32_TC
12, // 15: GR32_BPSP_with_GR32_TC
16, // 16: FR16
16, // 17: DEBUG_REG
16, // 18: CONTROL_REG
18, // 19: GR64_NOREX
20, // 20: GR64_TCW64
20, // 21: GR32_BPSP_with_GR64_TCW64
22, // 22: GR8
22, // 23: GR8_with_GR32_DIBP
22, // 24: GR8_with_GR32_BSI
22, // 25: GR64_TC_with_GR64_TCW64
23, // 26: GR8_with_LOW32_ADDR_ACCESS_with_sub_32bit
26, // 27: GR8_with_GR64_NOREX
26, // 28: GR64_TC
27, // 29: GR8_with_GR64_TCW64
28, // 30: GR8_with_GR64_TC
29, // 31: GR8_with_GR64PLTSafe
32, // 32: FR16X
34, // 33: GR16
};
return PressureLimitTable[Idx];
}
/// Table of pressure sets per register class or unit.
static const int RCSetsTable[] = {
/* 0 */ 0, -1,
/* 2 */ 7, -1,
/* 4 */ 10, -1,
/* 6 */ 11, -1,
/* 8 */ 12, -1,
/* 10 */ 17, -1,
/* 12 */ 18, -1,
/* 14 */ 16, 32, -1,
/* 17 */ 19, 27, 28, 33, -1,
/* 22 */ 1, 2, 15, 19, 21, 22, 27, 28, 33, -1,
/* 32 */ 2, 6, 15, 19, 21, 26, 27, 28, 33, -1,
/* 42 */ 20, 21, 25, 28, 29, 33, -1,
/* 49 */ 25, 28, 30, 33, -1,
/* 54 */ 19, 25, 27, 28, 30, 33, -1,
/* 61 */ 20, 21, 25, 28, 29, 30, 33, -1,
/* 69 */ 14, 15, 19, 20, 21, 25, 27, 28, 29, 30, 33, -1,
/* 81 */ 1, 2, 14, 15, 19, 20, 21, 22, 25, 27, 28, 29, 30, 33, -1,
/* 96 */ 2, 6, 14, 15, 19, 20, 21, 25, 26, 27, 28, 29, 30, 33, -1,
/* 111 */ 19, 27, 28, 31, 33, -1,
/* 117 */ 1, 5, 6, 19, 23, 27, 28, 31, 33, -1,
/* 127 */ 1, 2, 5, 6, 15, 19, 21, 22, 23, 26, 27, 28, 31, 33, -1,
/* 142 */ 25, 28, 30, 31, 33, -1,
/* 148 */ 3, 4, 8, 9, 13, 19, 24, 27, 28, 30, 31, 33, -1,
/* 161 */ 4, 5, 19, 24, 25, 27, 28, 30, 31, 33, -1,
/* 172 */ 3, 4, 5, 8, 9, 13, 19, 24, 25, 27, 28, 30, 31, 33, -1,
/* 187 */ 1, 4, 5, 6, 19, 23, 24, 25, 27, 28, 30, 31, 33, -1,
/* 201 */ 22, 23, 24, 26, 27, 29, 30, 31, 33, -1,
/* 211 */ 20, 21, 25, 28, 29, 30, 31, 33, -1,
/* 220 */ 3, 13, 14, 19, 20, 22, 23, 24, 26, 27, 28, 29, 30, 31, 33, -1,
/* 236 */ 8, 13, 14, 19, 20, 22, 23, 24, 26, 27, 28, 29, 30, 31, 33, -1,
/* 252 */ 3, 4, 8, 9, 13, 14, 19, 20, 22, 23, 24, 26, 27, 28, 29, 30, 31, 33, -1,
/* 271 */ 1, 2, 5, 6, 15, 19, 21, 22, 23, 24, 26, 27, 28, 29, 30, 31, 33, -1,
/* 289 */ 1, 4, 5, 6, 19, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 33, -1,
/* 306 */ 3, 4, 5, 8, 9, 13, 19, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 33, -1,
/* 325 */ 1, 2, 14, 15, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 33, -1,
/* 344 */ 3, 13, 14, 15, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 33, -1,
/* 363 */ 3, 8, 13, 14, 15, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 33, -1,
/* 383 */ 3, 9, 13, 14, 15, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 33, -1,
};
/// Get the dimensions of register pressure impacted by this register class.
/// Returns a -1 terminated array of pressure set IDs
const int *X86GenRegisterInfo::
getRegClassPressureSets(const TargetRegisterClass *RC) const {
static const uint16_t RCSetStartTable[] = {
201,1,221,236,255,1,20,17,4,4,4,4,4,4,4,4,4,4,0,221,1,15,14,4,4,4,4,4,4,15,20,20,20,10,14,20,20,17,17,4,111,2,4,221,83,345,345,22,148,220,345,117,161,32,1,1,252,345,127,81,172,344,187,127,96,2,15,20,12,14,20,20,114,49,17,42,49,49,42,61,17,4,6,142,111,54,42,61,4,61,54,211,163,69,221,83,345,345,32,22,148,220,345,117,161,96,252,345,127,81,172,344,187,1,2,1,15,14,15,14,15,14,8,};
return &RCSetsTable[RCSetStartTable[RC->getID()]];
}
/// Get the dimensions of register pressure impacted by this register unit.
/// Returns a -1 terminated array of pressure set IDs
const int *X86GenRegisterInfo::
getRegUnitPressureSets(unsigned RegUnit) const {
assert(RegUnit < 173 && "invalid register unit");
static const uint16_t RUSetStartTable[] = {
364,384,252,252,271,1,363,383,0,1,364,289,1,384,0,1,1,1,1,1,1,1,96,1,1,0,306,1,1,325,1,1,1,1,0,1,0,1,1,1,1,0,1,1,1,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,12,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,10,2,2,2,2,2,2,2,1,4,4,4,4,4,4,4,4,6,6,6,6,6,6,6,6,330,1,1,330,1,1,330,1,1,330,1,1,201,1,1,201,1,1,201,1,1,201,1,1,1,1,1,1,1,1,1,1,8,8,8,8,8,8,8,8,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,14,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,};
return &RCSetsTable[RUSetStartTable[RegUnit]];
}
extern const MCRegisterDesc X86RegDesc[];
extern const MCPhysReg X86RegDiffLists[];
extern const LaneBitmask X86LaneMaskLists[];
extern const char X86RegStrings[];
extern const char X86RegClassStrings[];
extern const MCPhysReg X86RegUnitRoots[][2];
extern const uint16_t X86SubRegIdxLists[];
extern const MCRegisterInfo::SubRegCoveredBits X86SubRegIdxRanges[];
extern const uint16_t X86RegEncodingTable[];
// X86 Dwarf<->LLVM register mappings.
extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour0Dwarf2L[];
extern const unsigned X86DwarfFlavour0Dwarf2LSize;
extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour1Dwarf2L[];
extern const unsigned X86DwarfFlavour1Dwarf2LSize;
extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour2Dwarf2L[];
extern const unsigned X86DwarfFlavour2Dwarf2LSize;
extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour0Dwarf2L[];
extern const unsigned X86EHFlavour0Dwarf2LSize;
extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour1Dwarf2L[];
extern const unsigned X86EHFlavour1Dwarf2LSize;
extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour2Dwarf2L[];
extern const unsigned X86EHFlavour2Dwarf2LSize;
extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour0L2Dwarf[];
extern const unsigned X86DwarfFlavour0L2DwarfSize;
extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour1L2Dwarf[];
extern const unsigned X86DwarfFlavour1L2DwarfSize;
extern const MCRegisterInfo::DwarfLLVMRegPair X86DwarfFlavour2L2Dwarf[];
extern const unsigned X86DwarfFlavour2L2DwarfSize;
extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour0L2Dwarf[];
extern const unsigned X86EHFlavour0L2DwarfSize;
extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour1L2Dwarf[];
extern const unsigned X86EHFlavour1L2DwarfSize;
extern const MCRegisterInfo::DwarfLLVMRegPair X86EHFlavour2L2Dwarf[];
extern const unsigned X86EHFlavour2L2DwarfSize;
X86GenRegisterInfo::
X86GenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
unsigned PC, unsigned HwMode)
: TargetRegisterInfo(&X86RegInfoDesc, RegisterClasses, RegisterClasses+123,
SubRegIndexNameTable, SubRegIndexLaneMaskTable,
LaneBitmask(0xFFFFFFFFFFFFFFB0), RegClassInfos, HwMode) {
InitMCRegisterInfo(X86RegDesc, 292, RA, PC,
X86MCRegisterClasses, 123,
X86RegUnitRoots,
173,
X86RegDiffLists,
X86LaneMaskLists,
X86RegStrings,
X86RegClassStrings,
X86SubRegIdxLists,
11,
X86SubRegIdxRanges,
X86RegEncodingTable);
switch (DwarfFlavour) {
default:
llvm_unreachable("Unknown DWARF flavour");
case 0:
mapDwarfRegsToLLVMRegs(X86DwarfFlavour0Dwarf2L, X86DwarfFlavour0Dwarf2LSize, false);
break;
case 1:
mapDwarfRegsToLLVMRegs(X86DwarfFlavour1Dwarf2L, X86DwarfFlavour1Dwarf2LSize, false);
break;
case 2:
mapDwarfRegsToLLVMRegs(X86DwarfFlavour2Dwarf2L, X86DwarfFlavour2Dwarf2LSize, false);
break;
}
switch (EHFlavour) {
default:
llvm_unreachable("Unknown DWARF flavour");
case 0:
mapDwarfRegsToLLVMRegs(X86EHFlavour0Dwarf2L, X86EHFlavour0Dwarf2LSize, true);
break;
case 1:
mapDwarfRegsToLLVMRegs(X86EHFlavour1Dwarf2L, X86EHFlavour1Dwarf2LSize, true);
break;
case 2:
mapDwarfRegsToLLVMRegs(X86EHFlavour2Dwarf2L, X86EHFlavour2Dwarf2LSize, true);
break;
}
switch (DwarfFlavour) {
default:
llvm_unreachable("Unknown DWARF flavour");
case 0:
mapLLVMRegsToDwarfRegs(X86DwarfFlavour0L2Dwarf, X86DwarfFlavour0L2DwarfSize, false);
break;
case 1:
mapLLVMRegsToDwarfRegs(X86DwarfFlavour1L2Dwarf, X86DwarfFlavour1L2DwarfSize, false);
break;
case 2:
mapLLVMRegsToDwarfRegs(X86DwarfFlavour2L2Dwarf, X86DwarfFlavour2L2DwarfSize, false);
break;
}
switch (EHFlavour) {
default:
llvm_unreachable("Unknown DWARF flavour");
case 0:
mapLLVMRegsToDwarfRegs(X86EHFlavour0L2Dwarf, X86EHFlavour0L2DwarfSize, true);
break;
case 1:
mapLLVMRegsToDwarfRegs(X86EHFlavour1L2Dwarf, X86EHFlavour1L2DwarfSize, true);
break;
case 2:
mapLLVMRegsToDwarfRegs(X86EHFlavour2L2Dwarf, X86EHFlavour2L2DwarfSize, true);
break;
}
}
static const MCPhysReg CSR_32_SaveList[] = { X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0 };
static const uint32_t CSR_32_RegMask[] = { 0x058703f0, 0xc0009601, 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
static const MCPhysReg CSR_32EHRet_SaveList[] = { X86::EAX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0 };
static const uint32_t CSR_32EHRet_RegMask[] = { 0x0def83fe, 0xc000b701, 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
static const MCPhysReg CSR_32_AllRegs_SaveList[] = { X86::EAX, X86::EBX, X86::ECX, X86::EDX, X86::EBP, X86::ESI, X86::EDI, 0 };
static const uint32_t CSR_32_AllRegs_RegMask[] = { 0x0fefaffe, 0xc000bf01, 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
static const MCPhysReg CSR_32_AllRegs_AVX_SaveList[] = { X86::EAX, X86::EBX, X86::ECX, X86::EDX, X86::EBP, X86::ESI, X86::EDI, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, 0 };
static const uint32_t CSR_32_AllRegs_AVX_RegMask[] = { 0x0fefaffe, 0xc000bf01, 0x00000001, 0x00000000, 0xff000000, 0xff000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
static const MCPhysReg CSR_32_AllRegs_AVX512_SaveList[] = { X86::EAX, X86::EBX, X86::ECX, X86::EDX, X86::EBP, X86::ESI, X86::EDI, X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 0 };
static const uint32_t CSR_32_AllRegs_AVX512_RegMask[] = { 0x0fefaffe, 0xc000bf01, 0x00000001, 0x00ff0000, 0xff000000, 0xff000000, 0xff000000, 0x00000000, 0x00000000, 0x0000000f, };
static const MCPhysReg CSR_32_AllRegs_SSE_SaveList[] = { X86::EAX, X86::EBX, X86::ECX, X86::EDX, X86::EBP, X86::ESI, X86::EDI, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, 0 };
static const uint32_t CSR_32_AllRegs_SSE_RegMask[] = { 0x0fefaffe, 0xc000bf01, 0x00000001, 0x00000000, 0xff000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
static const MCPhysReg CSR_32_RegCall_SaveList[] = { X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, 0 };
static const uint32_t CSR_32_RegCall_RegMask[] = { 0x058703f0, 0xc0009601, 0x00000001, 0x00000000, 0xf0000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
static const MCPhysReg CSR_32_RegCall_NoSSE_SaveList[] = { X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0 };
static const uint32_t CSR_32_RegCall_NoSSE_RegMask[] = { 0x058703f0, 0xc0009601, 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
static const MCPhysReg CSR_64_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0 };
static const uint32_t CSR_64_RegMask[] = { 0x018003f0, 0x00300600, 0x00000000, 0x00000000, 0x000000f0, 0x00000000, 0x00000000, 0xf0000000, 0xf0f0f0f0, 0x00000000, };
static const MCPhysReg CSR_64EHRet_SaveList[] = { X86::RAX, X86::RDX, X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0 };
static const uint32_t CSR_64EHRet_RegMask[] = { 0x09e883fe, 0x01382700, 0x00000000, 0x00000000, 0x000000f0, 0x00000000, 0x00000000, 0xf0000000, 0xf0f0f0f0, 0x00000000, };
static const MCPhysReg CSR_64_AllRegs_SaveList[] = { X86::RBX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::RAX, 0 };
static const uint32_t CSR_64_AllRegs_RegMask[] = { 0x0fefaffe, 0xd1f8bf01, 0x00000001, 0x00000000, 0xff0000ff, 0x000000ff, 0x00000000, 0xff000000, 0xffffffff, 0x00000000, };
static const MCPhysReg CSR_64_AllRegs_AVX_SaveList[] = { X86::RBX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::RAX, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, 0 };
static const uint32_t CSR_64_AllRegs_AVX_RegMask[] = { 0x0fefaffe, 0xd1f8bf01, 0x00000001, 0x00000000, 0xff0000ff, 0xff0000ff, 0x000000ff, 0xff000000, 0xffffffff, 0x00000000, };
static const MCPhysReg CSR_64_AllRegs_AVX512_SaveList[] = { X86::RBX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::RAX, X86::ZMM0, X86::ZMM1, X86::ZMM2, X86::ZMM3, X86::ZMM4, X86::ZMM5, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15, X86::ZMM16, X86::ZMM17, X86::ZMM18, X86::ZMM19, X86::ZMM20, X86::ZMM21, X86::ZMM22, X86::ZMM23, X86::ZMM24, X86::ZMM25, X86::ZMM26, X86::ZMM27, X86::ZMM28, X86::ZMM29, X86::ZMM30, X86::ZMM31, X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7, 0 };
static const uint32_t CSR_64_AllRegs_AVX512_RegMask[] = { 0x0fefaffe, 0xd1f8bf01, 0x00000001, 0x00ff0000, 0xff0000ff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x0000000f, };
static const MCPhysReg CSR_64_AllRegs_NoSSE_SaveList[] = { X86::RAX, X86::RBX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0 };
static const uint32_t CSR_64_AllRegs_NoSSE_RegMask[] = { 0x0fefaffe, 0xd1f8bf01, 0x00000001, 0x00000000, 0x000000ff, 0x00000000, 0x00000000, 0xff000000, 0xffffffff, 0x00000000, };
static const MCPhysReg CSR_64_CXX_TLS_Darwin_PE_SaveList[] = { X86::RBP, 0 };
static const uint32_t CSR_64_CXX_TLS_Darwin_PE_RegMask[] = { 0x008001c0, 0x00100200, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
static const MCPhysReg CSR_64_CXX_TLS_Darwin_ViaCopy_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RCX, X86::RDX, X86::RSI, X86::R8, X86::R9, X86::R10, X86::R11, 0 };
static const uint32_t CSR_64_CXX_TLS_Darwin_ViaCopy_RegMask[] = { 0x0b28ae30, 0xd160ac01, 0x00000001, 0x00000000, 0x000000ff, 0x00000000, 0x00000000, 0xff000000, 0xffffffff, 0x00000000, };
static const MCPhysReg CSR_64_HHVM_SaveList[] = { X86::R12, 0 };
static const uint32_t CSR_64_HHVM_RegMask[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000010, 0x00000000, 0x00000000, 0x10000000, 0x10101010, 0x00000000, };
static const MCPhysReg CSR_64_Intel_OCL_BI_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
static const uint32_t CSR_64_Intel_OCL_BI_RegMask[] = { 0x018003f0, 0x00300600, 0x00000000, 0x00000000, 0x000000f0, 0x000000ff, 0x00000000, 0xf0000000, 0xf0f0f0f0, 0x00000000, };
static const MCPhysReg CSR_64_Intel_OCL_BI_AVX_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, 0 };
static const uint32_t CSR_64_Intel_OCL_BI_AVX_RegMask[] = { 0x018003f0, 0x00300600, 0x00000000, 0x00000000, 0x000000f0, 0x000000ff, 0x000000ff, 0xf0000000, 0xf0f0f0f0, 0x00000000, };
static const MCPhysReg CSR_64_Intel_OCL_BI_AVX512_SaveList[] = { X86::RBX, X86::RSI, X86::R14, X86::R15, X86::ZMM16, X86::ZMM17, X86::ZMM18, X86::ZMM19, X86::ZMM20, X86::ZMM21, X86::ZMM22, X86::ZMM23, X86::ZMM24, X86::ZMM25, X86::ZMM26, X86::ZMM27, X86::ZMM28, X86::ZMM29, X86::ZMM30, X86::ZMM31, X86::K4, X86::K5, X86::K6, X86::K7, 0 };
static const uint32_t CSR_64_Intel_OCL_BI_AVX512_RegMask[] = { 0x01000230, 0xd0208401, 0x00000001, 0x00f00000, 0x000000c0, 0x00ffff00, 0x00ffff00, 0xc0ffff00, 0xc0c0c0c0, 0x0000000c, };
static const MCPhysReg CSR_64_MostRegs_SaveList[] = { X86::RBX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
static const uint32_t CSR_64_MostRegs_RegMask[] = { 0x0fafaff0, 0xd1f0be01, 0x00000001, 0x00000000, 0xff0000ff, 0x000000ff, 0x00000000, 0xff000000, 0xffffffff, 0x00000000, };
static const MCPhysReg CSR_64_RT_AllRegs_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
static const uint32_t CSR_64_RT_AllRegs_RegMask[] = { 0x0fefaffe, 0xd1f8bf01, 0x00000001, 0x00000000, 0xff0000f7, 0x000000ff, 0x00000000, 0xf7000000, 0xf7f7f7f7, 0x00000000, };
static const MCPhysReg CSR_64_RT_AllRegs_AVX_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::YMM0, X86::YMM1, X86::YMM2, X86::YMM3, X86::YMM4, X86::YMM5, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, 0 };
static const uint32_t CSR_64_RT_AllRegs_AVX_RegMask[] = { 0x0fefaffe, 0xd1f8bf01, 0x00000001, 0x00000000, 0xff0000f7, 0xff0000ff, 0x000000ff, 0xf7000000, 0xf7f7f7f7, 0x00000000, };
static const MCPhysReg CSR_64_RT_MostRegs_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, 0 };
static const uint32_t CSR_64_RT_MostRegs_RegMask[] = { 0x0fefaffe, 0xd1f8bf01, 0x00000001, 0x00000000, 0x000000f7, 0x00000000, 0x00000000, 0xf7000000, 0xf7f7f7f7, 0x00000000, };
static const MCPhysReg CSR_64_SwiftError_SaveList[] = { X86::RBX, X86::R13, X86::R14, X86::R15, X86::RBP, 0 };
static const uint32_t CSR_64_SwiftError_RegMask[] = { 0x018003f0, 0x00300600, 0x00000000, 0x00000000, 0x000000e0, 0x00000000, 0x00000000, 0xe0000000, 0xe0e0e0e0, 0x00000000, };
static const MCPhysReg CSR_64_SwiftTail_SaveList[] = { X86::RBX, X86::R12, X86::R15, X86::RBP, 0 };
static const uint32_t CSR_64_SwiftTail_RegMask[] = { 0x018003f0, 0x00300600, 0x00000000, 0x00000000, 0x00000090, 0x00000000, 0x00000000, 0x90000000, 0x90909090, 0x00000000, };
static const MCPhysReg CSR_64_TLS_Darwin_SaveList[] = { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, X86::RCX, X86::RDX, X86::RSI, X86::R8, X86::R9, X86::R10, X86::R11, 0 };
static const uint32_t CSR_64_TLS_Darwin_RegMask[] = { 0x0ba8aff0, 0xd170ae01, 0x00000001, 0x00000000, 0x000000ff, 0x00000000, 0x00000000, 0xff000000, 0xffffffff, 0x00000000, };
static const MCPhysReg CSR_NoRegs_SaveList[] = { 0 };
static const uint32_t CSR_NoRegs_RegMask[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
static const MCPhysReg CSR_SysV64_RegCall_SaveList[] = { X86::RBX, X86::RBP, X86::R12, X86::R13, X86::R14, X86::R15, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
static const uint32_t CSR_SysV64_RegCall_RegMask[] = { 0x018003f0, 0x00300600, 0x00000000, 0x00000000, 0x000000f0, 0x000000ff, 0x00000000, 0xf0000000, 0xf0f0f0f0, 0x00000000, };
static const MCPhysReg CSR_SysV64_RegCall_NoSSE_SaveList[] = { X86::RBX, X86::RBP, X86::R12, X86::R13, X86::R14, X86::R15, 0 };
static const uint32_t CSR_SysV64_RegCall_NoSSE_RegMask[] = { 0x018003f0, 0x00300600, 0x00000000, 0x00000000, 0x000000f0, 0x00000000, 0x00000000, 0xf0000000, 0xf0f0f0f0, 0x00000000, };
static const MCPhysReg CSR_Win32_CFGuard_Check_SaveList[] = { X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::ECX, 0 };
static const uint32_t CSR_Win32_CFGuard_Check_RegMask[] = { 0x07872ff0, 0xc0009e01, 0x00000001, 0x00000000, 0xf0000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
static const MCPhysReg CSR_Win32_CFGuard_Check_NoSSE_SaveList[] = { X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ECX, 0 };
static const uint32_t CSR_Win32_CFGuard_Check_NoSSE_RegMask[] = { 0x07872ff0, 0xc0009e01, 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
static const MCPhysReg CSR_Win64_SaveList[] = { X86::RBX, X86::RBP, X86::RDI, X86::RSI, X86::R12, X86::R13, X86::R14, X86::R15, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
static const uint32_t CSR_Win64_RegMask[] = { 0x058703f0, 0xd0b09601, 0x00000001, 0x00000000, 0xc00000f0, 0x000000ff, 0x00000000, 0xf0000000, 0xf0f0f0f0, 0x00000000, };
static const MCPhysReg CSR_Win64_Intel_OCL_BI_AVX_SaveList[] = { X86::RBX, X86::RBP, X86::RDI, X86::RSI, X86::R12, X86::R13, X86::R14, X86::R15, X86::YMM6, X86::YMM7, X86::YMM8, X86::YMM9, X86::YMM10, X86::YMM11, X86::YMM12, X86::YMM13, X86::YMM14, X86::YMM15, 0 };
static const uint32_t CSR_Win64_Intel_OCL_BI_AVX_RegMask[] = { 0x058703f0, 0xd0b09601, 0x00000001, 0x00000000, 0xc00000f0, 0xc00000ff, 0x000000ff, 0xf0000000, 0xf0f0f0f0, 0x00000000, };
static const MCPhysReg CSR_Win64_Intel_OCL_BI_AVX512_SaveList[] = { X86::RBX, X86::RBP, X86::RDI, X86::RSI, X86::R12, X86::R13, X86::R14, X86::R15, X86::ZMM6, X86::ZMM7, X86::ZMM8, X86::ZMM9, X86::ZMM10, X86::ZMM11, X86::ZMM12, X86::ZMM13, X86::ZMM14, X86::ZMM15, X86::ZMM16, X86::ZMM17, X86::ZMM18, X86::ZMM19, X86::ZMM20, X86::ZMM21, X86::K4, X86::K5, X86::K6, X86::K7, 0 };
static const uint32_t CSR_Win64_Intel_OCL_BI_AVX512_RegMask[] = { 0x058703f0, 0xd0b09601, 0x00000001, 0x00f00000, 0xc00000f0, 0xc0003fff, 0xc0003fff, 0xf0003fff, 0xf0f0f0f0, 0x0000000c, };
static const MCPhysReg CSR_Win64_NoSSE_SaveList[] = { X86::RBX, X86::RBP, X86::RDI, X86::RSI, X86::R12, X86::R13, X86::R14, X86::R15, 0 };
static const uint32_t CSR_Win64_NoSSE_RegMask[] = { 0x058703f0, 0xd0b09601, 0x00000001, 0x00000000, 0x000000f0, 0x00000000, 0x00000000, 0xf0000000, 0xf0f0f0f0, 0x00000000, };
static const MCPhysReg CSR_Win64_RegCall_SaveList[] = { X86::RBX, X86::RBP, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
static const uint32_t CSR_Win64_RegCall_RegMask[] = { 0x018003f0, 0x00300600, 0x00000000, 0x00000000, 0x000000fc, 0x000000ff, 0x00000000, 0xfc000000, 0xfcfcfcfc, 0x00000000, };
static const MCPhysReg CSR_Win64_RegCall_NoSSE_SaveList[] = { X86::RBX, X86::RBP, X86::R10, X86::R11, X86::R12, X86::R13, X86::R14, X86::R15, 0 };
static const uint32_t CSR_Win64_RegCall_NoSSE_RegMask[] = { 0x018003f0, 0x00300600, 0x00000000, 0x00000000, 0x000000fc, 0x00000000, 0x00000000, 0xfc000000, 0xfcfcfcfc, 0x00000000, };
static const MCPhysReg CSR_Win64_SwiftError_SaveList[] = { X86::RBX, X86::RBP, X86::RDI, X86::RSI, X86::R13, X86::R14, X86::R15, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
static const uint32_t CSR_Win64_SwiftError_RegMask[] = { 0x058703f0, 0xd0b09601, 0x00000001, 0x00000000, 0xc00000e0, 0x000000ff, 0x00000000, 0xe0000000, 0xe0e0e0e0, 0x00000000, };
static const MCPhysReg CSR_Win64_SwiftTail_SaveList[] = { X86::RBX, X86::RBP, X86::RDI, X86::RSI, X86::R12, X86::R15, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, 0 };
static const uint32_t CSR_Win64_SwiftTail_RegMask[] = { 0x058703f0, 0xd0b09601, 0x00000001, 0x00000000, 0xc0000090, 0x000000ff, 0x00000000, 0x90000000, 0x90909090, 0x00000000, };
ArrayRef<const uint32_t *> X86GenRegisterInfo::getRegMasks() const {
static const uint32_t *const Masks[] = {
CSR_32_RegMask,
CSR_32EHRet_RegMask,
CSR_32_AllRegs_RegMask,
CSR_32_AllRegs_AVX_RegMask,
CSR_32_AllRegs_AVX512_RegMask,
CSR_32_AllRegs_SSE_RegMask,
CSR_32_RegCall_RegMask,
CSR_32_RegCall_NoSSE_RegMask,
CSR_64_RegMask,
CSR_64EHRet_RegMask,
CSR_64_AllRegs_RegMask,
CSR_64_AllRegs_AVX_RegMask,
CSR_64_AllRegs_AVX512_RegMask,
CSR_64_AllRegs_NoSSE_RegMask,
CSR_64_CXX_TLS_Darwin_PE_RegMask,
CSR_64_CXX_TLS_Darwin_ViaCopy_RegMask,
CSR_64_HHVM_RegMask,
CSR_64_Intel_OCL_BI_RegMask,
CSR_64_Intel_OCL_BI_AVX_RegMask,
CSR_64_Intel_OCL_BI_AVX512_RegMask,
CSR_64_MostRegs_RegMask,
CSR_64_RT_AllRegs_RegMask,
CSR_64_RT_AllRegs_AVX_RegMask,
CSR_64_RT_MostRegs_RegMask,
CSR_64_SwiftError_RegMask,
CSR_64_SwiftTail_RegMask,
CSR_64_TLS_Darwin_RegMask,
CSR_NoRegs_RegMask,
CSR_SysV64_RegCall_RegMask,
CSR_SysV64_RegCall_NoSSE_RegMask,
CSR_Win32_CFGuard_Check_RegMask,
CSR_Win32_CFGuard_Check_NoSSE_RegMask,
CSR_Win64_RegMask,
CSR_Win64_Intel_OCL_BI_AVX_RegMask,
CSR_Win64_Intel_OCL_BI_AVX512_RegMask,
CSR_Win64_NoSSE_RegMask,
CSR_Win64_RegCall_RegMask,
CSR_Win64_RegCall_NoSSE_RegMask,
CSR_Win64_SwiftError_RegMask,
CSR_Win64_SwiftTail_RegMask,
};
return ArrayRef(Masks);
}
bool X86GenRegisterInfo::
isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
return
X86::GR64RegClass.contains(PhysReg) ||
X86::GR32RegClass.contains(PhysReg) ||
X86::GR16RegClass.contains(PhysReg) ||
X86::GR8RegClass.contains(PhysReg) ||
false;
}
bool X86GenRegisterInfo::
isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
return
X86::DEBUG_REGRegClass.contains(PhysReg) ||
X86::CONTROL_REGRegClass.contains(PhysReg) ||
X86::CCRRegClass.contains(PhysReg) ||
X86::FPCCRRegClass.contains(PhysReg) ||
X86::DFCCRRegClass.contains(PhysReg) ||
X86::TILERegClass.contains(PhysReg) ||
X86::VK1PAIRRegClass.contains(PhysReg) ||
X86::VK2PAIRRegClass.contains(PhysReg) ||
X86::VK4PAIRRegClass.contains(PhysReg) ||
X86::VK8PAIRRegClass.contains(PhysReg) ||
X86::VK16PAIRRegClass.contains(PhysReg) ||
false;
}
bool X86GenRegisterInfo::
isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
return
false;
}
bool X86GenRegisterInfo::
isConstantPhysReg(MCRegister PhysReg) const {
return
false;
}
ArrayRef<const char *> X86GenRegisterInfo::getRegMaskNames() const {
static const char *Names[] = {
"CSR_32",
"CSR_32EHRet",
"CSR_32_AllRegs",
"CSR_32_AllRegs_AVX",
"CSR_32_AllRegs_AVX512",
"CSR_32_AllRegs_SSE",
"CSR_32_RegCall",
"CSR_32_RegCall_NoSSE",
"CSR_64",
"CSR_64EHRet",
"CSR_64_AllRegs",
"CSR_64_AllRegs_AVX",
"CSR_64_AllRegs_AVX512",
"CSR_64_AllRegs_NoSSE",
"CSR_64_CXX_TLS_Darwin_PE",
"CSR_64_CXX_TLS_Darwin_ViaCopy",
"CSR_64_HHVM",
"CSR_64_Intel_OCL_BI",
"CSR_64_Intel_OCL_BI_AVX",
"CSR_64_Intel_OCL_BI_AVX512",
"CSR_64_MostRegs",
"CSR_64_RT_AllRegs",
"CSR_64_RT_AllRegs_AVX",
"CSR_64_RT_MostRegs",
"CSR_64_SwiftError",
"CSR_64_SwiftTail",
"CSR_64_TLS_Darwin",
"CSR_NoRegs",
"CSR_SysV64_RegCall",
"CSR_SysV64_RegCall_NoSSE",
"CSR_Win32_CFGuard_Check",
"CSR_Win32_CFGuard_Check_NoSSE",
"CSR_Win64",
"CSR_Win64_Intel_OCL_BI_AVX",
"CSR_Win64_Intel_OCL_BI_AVX512",
"CSR_Win64_NoSSE",
"CSR_Win64_RegCall",
"CSR_Win64_RegCall_NoSSE",
"CSR_Win64_SwiftError",
"CSR_Win64_SwiftTail",
};
return ArrayRef(Names);
}
const X86FrameLowering *
X86GenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
return static_cast<const X86FrameLowering *>(
MF.getSubtarget().getFrameLowering());
}
} // end namespace llvm
#endif // GET_REGINFO_TARGET_DESC