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swiftshader / SwiftShader / refs/heads/master / . / third_party / llvm-16.0 / configs / common / lib / Target / X86 / X86GenRegisterInfo.inc
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/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|* *|
|* Target Register Enum Values *|
|* *|
|* Automatically generated file, do not edit! *|
|* *|
\*===----------------------------------------------------------------------===*/
#ifdef GET_REGINFO_ENUM
#undef GET_REGINFO_ENUM
namespace llvm {
class MCRegisterClass;
extern const MCRegisterClass X86MCRegisterClasses[];
namespace X86 {
enum {
NoRegister,
AH = 1,
AL = 2,
AX = 3,
BH = 4,
BL = 5,
BP = 6,
BPH = 7,
BPL = 8,
BX = 9,
CH = 10,
CL = 11,
CS = 12,
CX = 13,
DF = 14,
DH = 15,
DI = 16,
DIH = 17,
DIL = 18,
DL = 19,
DS = 20,
DX = 21,
EAX = 22,
EBP = 23,
EBX = 24,
ECX = 25,
EDI = 26,
EDX = 27,
EFLAGS = 28,
EIP = 29,
EIZ = 30,
ES = 31,
ESI = 32,
ESP = 33,
FPCW = 34,
FPSW = 35,
FS = 36,
FS_BASE = 37,
GS = 38,
GS_BASE = 39,
HAX = 40,
HBP = 41,
HBX = 42,
HCX = 43,
HDI = 44,
HDX = 45,
HIP = 46,
HSI = 47,
HSP = 48,
IP = 49,
MXCSR = 50,
RAX = 51,
RBP = 52,
RBX = 53,
RCX = 54,
RDI = 55,
RDX = 56,
RFLAGS = 57,
RIP = 58,
RIZ = 59,
RSI = 60,
RSP = 61,
SI = 62,
SIH = 63,
SIL = 64,
SP = 65,
SPH = 66,
SPL = 67,
SS = 68,
SSP = 69,
TMMCFG = 70,
_EFLAGS = 71,
CR0 = 72,
CR1 = 73,
CR2 = 74,
CR3 = 75,
CR4 = 76,
CR5 = 77,
CR6 = 78,
CR7 = 79,
CR8 = 80,
CR9 = 81,
CR10 = 82,
CR11 = 83,
CR12 = 84,
CR13 = 85,
CR14 = 86,
CR15 = 87,
DR0 = 88,
DR1 = 89,
DR2 = 90,
DR3 = 91,
DR4 = 92,
DR5 = 93,
DR6 = 94,
DR7 = 95,
DR8 = 96,
DR9 = 97,
DR10 = 98,
DR11 = 99,
DR12 = 100,
DR13 = 101,
DR14 = 102,
DR15 = 103,
FP0 = 104,
FP1 = 105,
FP2 = 106,
FP3 = 107,
FP4 = 108,
FP5 = 109,
FP6 = 110,
FP7 = 111,
K0 = 112,
K1 = 113,
K2 = 114,
K3 = 115,
K4 = 116,
K5 = 117,
K6 = 118,
K7 = 119,
MM0 = 120,
MM1 = 121,
MM2 = 122,
MM3 = 123,
MM4 = 124,
MM5 = 125,
MM6 = 126,
MM7 = 127,
R8 = 128,
R9 = 129,
R10 = 130,
R11 = 131,
R12 = 132,
R13 = 133,
R14 = 134,
R15 = 135,
ST0 = 136,
ST1 = 137,
ST2 = 138,
ST3 = 139,
ST4 = 140,
ST5 = 141,
ST6 = 142,
ST7 = 143,
TMM0 = 144,
TMM1 = 145,
TMM2 = 146,
TMM3 = 147,
TMM4 = 148,
TMM5 = 149,
TMM6 = 150,
TMM7 = 151,
XMM0 = 152,
XMM1 = 153,
XMM2 = 154,
XMM3 = 155,
XMM4 = 156,
XMM5 = 157,
XMM6 = 158,
XMM7 = 159,
XMM8 = 160,
XMM9 = 161,
XMM10 = 162,
XMM11 = 163,
XMM12 = 164,
XMM13 = 165,
XMM14 = 166,
XMM15 = 167,
XMM16 = 168,
XMM17 = 169,
XMM18 = 170,
XMM19 = 171,
XMM20 = 172,
XMM21 = 173,
XMM22 = 174,
XMM23 = 175,
XMM24 = 176,
XMM25 = 177,
XMM26 = 178,
XMM27 = 179,
XMM28 = 180,
XMM29 = 181,
XMM30 = 182,
XMM31 = 183,
YMM0 = 184,
YMM1 = 185,
YMM2 = 186,
YMM3 = 187,
YMM4 = 188,
YMM5 = 189,
YMM6 = 190,
YMM7 = 191,
YMM8 = 192,
YMM9 = 193,
YMM10 = 194,
YMM11 = 195,
YMM12 = 196,
YMM13 = 197,
YMM14 = 198,
YMM15 = 199,
YMM16 = 200,
YMM17 = 201,
YMM18 = 202,
YMM19 = 203,
YMM20 = 204,
YMM21 = 205,
YMM22 = 206,
YMM23 = 207,
YMM24 = 208,
YMM25 = 209,
YMM26 = 210,
YMM27 = 211,
YMM28 = 212,
YMM29 = 213,
YMM30 = 214,
YMM31 = 215,
ZMM0 = 216,
ZMM1 = 217,
ZMM2 = 218,
ZMM3 = 219,
ZMM4 = 220,
ZMM5 = 221,
ZMM6 = 222,
ZMM7 = 223,
ZMM8 = 224,
ZMM9 = 225,
ZMM10 = 226,
ZMM11 = 227,
ZMM12 = 228,
ZMM13 = 229,
ZMM14 = 230,
ZMM15 = 231,
ZMM16 = 232,
ZMM17 = 233,
ZMM18 = 234,
ZMM19 = 235,
ZMM20 = 236,
ZMM21 = 237,
ZMM22 = 238,
ZMM23 = 239,
ZMM24 = 240,
ZMM25 = 241,
ZMM26 = 242,
ZMM27 = 243,
ZMM28 = 244,
ZMM29 = 245,
ZMM30 = 246,
ZMM31 = 247,
R8B = 248,
R9B = 249,
R10B = 250,
R11B = 251,
R12B = 252,
R13B = 253,
R14B = 254,
R15B = 255,
R8BH = 256,
R9BH = 257,
R10BH = 258,
R11BH = 259,
R12BH = 260,
R13BH = 261,
R14BH = 262,
R15BH = 263,
R8D = 264,
R9D = 265,
R10D = 266,
R11D = 267,
R12D = 268,
R13D = 269,
R14D = 270,
R15D = 271,
R8W = 272,
R9W = 273,
R10W = 274,
R11W = 275,
R12W = 276,
R13W = 277,
R14W = 278,
R15W = 279,
R8WH = 280,
R9WH = 281,
R10WH = 282,
R11WH = 283,
R12WH = 284,
R13WH = 285,
R14WH = 286,
R15WH = 287,
K0_K1 = 288,
K2_K3 = 289,
K4_K5 = 290,
K6_K7 = 291,
NUM_TARGET_REGS // 292
};
} // end namespace X86
// Register classes
namespace X86 {
enum {
GR8RegClassID = 0,
GRH8RegClassID = 1,
GR8_NOREXRegClassID = 2,
GR8_ABCD_HRegClassID = 3,
GR8_ABCD_LRegClassID = 4,
GRH16RegClassID = 5,
GR16RegClassID = 6,
GR16_NOREXRegClassID = 7,
VK1RegClassID = 8,
VK16RegClassID = 9,
VK2RegClassID = 10,
VK4RegClassID = 11,
VK8RegClassID = 12,
VK16WMRegClassID = 13,
VK1WMRegClassID = 14,
VK2WMRegClassID = 15,
VK4WMRegClassID = 16,
VK8WMRegClassID = 17,
SEGMENT_REGRegClassID = 18,
GR16_ABCDRegClassID = 19,
FPCCRRegClassID = 20,
FR16XRegClassID = 21,
FR16RegClassID = 22,
VK16PAIRRegClassID = 23,
VK1PAIRRegClassID = 24,
VK2PAIRRegClassID = 25,
VK4PAIRRegClassID = 26,
VK8PAIRRegClassID = 27,
VK16PAIR_with_sub_mask_0_in_VK16WMRegClassID = 28,
FR32XRegClassID = 29,
LOW32_ADDR_ACCESS_RBPRegClassID = 30,
LOW32_ADDR_ACCESSRegClassID = 31,
LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClassID = 32,
DEBUG_REGRegClassID = 33,
FR32RegClassID = 34,
GR32RegClassID = 35,
GR32_NOSPRegClassID = 36,
LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClassID = 37,
GR32_NOREXRegClassID = 38,
VK32RegClassID = 39,
GR32_NOREX_NOSPRegClassID = 40,
RFP32RegClassID = 41,
VK32WMRegClassID = 42,
GR32_ABCDRegClassID = 43,
GR32_TCRegClassID = 44,
GR32_ABCD_and_GR32_TCRegClassID = 45,
GR32_ADRegClassID = 46,
GR32_BPSPRegClassID = 47,
GR32_BSIRegClassID = 48,
GR32_CBRegClassID = 49,
GR32_DCRegClassID = 50,
GR32_DIBPRegClassID = 51,
GR32_SIDIRegClassID = 52,
LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClassID = 53,
CCRRegClassID = 54,
DFCCRRegClassID = 55,
GR32_ABCD_and_GR32_BSIRegClassID = 56,
GR32_AD_and_GR32_DCRegClassID = 57,
GR32_BPSP_and_GR32_DIBPRegClassID = 58,
GR32_BPSP_and_GR32_TCRegClassID = 59,
GR32_BSI_and_GR32_SIDIRegClassID = 60,
GR32_CB_and_GR32_DCRegClassID = 61,
GR32_DIBP_and_GR32_SIDIRegClassID = 62,
LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitRegClassID = 63,
LOW32_ADDR_ACCESS_with_sub_32bitRegClassID = 64,
RFP64RegClassID = 65,
FR64XRegClassID = 66,
GR64RegClassID = 67,
CONTROL_REGRegClassID = 68,
FR64RegClassID = 69,
GR64_with_sub_8bitRegClassID = 70,
GR64_NOSPRegClassID = 71,
GR64PLTSafeRegClassID = 72,
GR64_TCRegClassID = 73,
GR64_NOREXRegClassID = 74,
GR64_TCW64RegClassID = 75,
GR64_TC_with_sub_8bitRegClassID = 76,
GR64_NOSP_and_GR64_TCRegClassID = 77,
GR64_TCW64_with_sub_8bitRegClassID = 78,
GR64_TC_and_GR64_TCW64RegClassID = 79,
GR64_with_sub_16bit_in_GR16_NOREXRegClassID = 80,
VK64RegClassID = 81,
VR64RegClassID = 82,
GR64PLTSafe_and_GR64_TCRegClassID = 83,
GR64_NOREX_NOSPRegClassID = 84,
GR64_NOREX_and_GR64_TCRegClassID = 85,
GR64_NOSP_and_GR64_TCW64RegClassID = 86,
GR64_TCW64_and_GR64_TC_with_sub_8bitRegClassID = 87,
VK64WMRegClassID = 88,
GR64_TC_and_GR64_NOSP_and_GR64_TCW64RegClassID = 89,
GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClassID = 90,
GR64PLTSafe_and_GR64_TCW64RegClassID = 91,
GR64_NOREX_and_GR64PLTSafe_and_GR64_TCRegClassID = 92,
GR64_NOREX_and_GR64_TCW64RegClassID = 93,
GR64_ABCDRegClassID = 94,
GR64_with_sub_32bit_in_GR32_TCRegClassID = 95,
GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClassID = 96,
GR64_ADRegClassID = 97,
GR64_and_LOW32_ADDR_ACCESS_RBPRegClassID = 98,
GR64_with_sub_32bit_in_GR32_BPSPRegClassID = 99,
GR64_with_sub_32bit_in_GR32_BSIRegClassID = 100,
GR64_with_sub_32bit_in_GR32_CBRegClassID = 101,
GR64_with_sub_32bit_in_GR32_DCRegClassID = 102,
GR64_with_sub_32bit_in_GR32_DIBPRegClassID = 103,
GR64_with_sub_32bit_in_GR32_SIDIRegClassID = 104,
GR64_and_LOW32_ADDR_ACCESSRegClassID = 105,
GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIRegClassID = 106,
GR64_with_sub_32bit_in_GR32_AD_and_GR32_DCRegClassID = 107,
GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPRegClassID = 108,
GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCRegClassID = 109,
GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIRegClassID = 110,
GR64_with_sub_32bit_in_GR32_CB_and_GR32_DCRegClassID = 111,
GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIRegClassID = 112,
RSTRegClassID = 113,
RFP80RegClassID = 114,
RFP80_7RegClassID = 115,
VR128XRegClassID = 116,
VR128RegClassID = 117,
VR256XRegClassID = 118,
VR256RegClassID = 119,
VR512RegClassID = 120,
VR512_0_15RegClassID = 121,
TILERegClassID = 122,
};
} // end namespace X86
// Subregister indices
namespace X86 {
enum : uint16_t {
NoSubRegister,
sub_8bit, // 1
sub_8bit_hi, // 2
sub_8bit_hi_phony, // 3
sub_16bit, // 4
sub_16bit_hi, // 5
sub_32bit, // 6
sub_mask_0, // 7
sub_mask_1, // 8
sub_xmm, // 9
sub_ymm, // 10
NUM_TARGET_SUBREGS
};
} // end namespace X86
// Register pressure sets enum.
namespace X86 {
enum RegisterPressureSets {
SEGMENT_REG = 0,
GR32_BPSP = 1,
LOW32_ADDR_ACCESS_with_sub_32bit = 2,
GR32_BSI = 3,
GR32_SIDI = 4,
GR32_DIBP_with_GR32_SIDI = 5,
GR32_DIBP_with_LOW32_ADDR_ACCESS_with_sub_32bit = 6,
RFP32 = 7,
GR8_ABCD_H_with_GR32_BSI = 8,
GR8_ABCD_L_with_GR32_BSI = 9,
VK1 = 10,
VR64 = 11,
TILE = 12,
GR8_NOREX = 13,
GR32_TC = 14,
GR32_BPSP_with_GR32_TC = 15,
FR16 = 16,
DEBUG_REG = 17,
CONTROL_REG = 18,
GR64_NOREX = 19,
GR64_TCW64 = 20,
GR32_BPSP_with_GR64_TCW64 = 21,
GR8 = 22,
GR8_with_GR32_DIBP = 23,
GR8_with_GR32_BSI = 24,
GR64_TC_with_GR64_TCW64 = 25,
GR8_with_LOW32_ADDR_ACCESS_with_sub_32bit = 26,
GR8_with_GR64_NOREX = 27,
GR64_TC = 28,
GR8_with_GR64_TCW64 = 29,
GR8_with_GR64_TC = 30,
GR8_with_GR64PLTSafe = 31,
FR16X = 32,
GR16 = 33,
};
} // end namespace X86
} // end namespace llvm
#endif // GET_REGINFO_ENUM
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|* *|
|* MC Register Information *|
|* *|
|* Automatically generated file, do not edit! *|
|* *|
\*===----------------------------------------------------------------------===*/
#ifdef GET_REGINFO_MC_DESC
#undef GET_REGINFO_MC_DESC
namespace llvm {
extern const MCPhysReg X86RegDiffLists[] = {
/* 0 */ 0, 1, 0,
/* 3 */ 64845, 1, 1, 0,
/* 7 */ 65253, 1, 1, 0,
/* 11 */ 65382, 1, 1, 0,
/* 15 */ 65466, 1, 1, 0,
/* 19 */ 2, 1, 0,
/* 22 */ 4, 1, 0,
/* 25 */ 6, 1, 0,
/* 28 */ 11, 1, 0,
/* 31 */ 22, 1, 0,
/* 34 */ 26, 1, 0,
/* 37 */ 29, 1, 0,
/* 40 */ 64821, 1, 0,
/* 43 */ 65045, 1, 0,
/* 46 */ 65360, 1, 0,
/* 49 */ 65361, 1, 0,
/* 52 */ 65362, 1, 0,
/* 55 */ 65363, 1, 0,
/* 58 */ 10, 3, 0,
/* 61 */ 4, 0,
/* 63 */ 5, 0,
/* 65 */ 65272, 1, 7, 0,
/* 69 */ 65417, 1, 7, 0,
/* 73 */ 10, 3, 7, 0,
/* 77 */ 65512, 8, 0,
/* 80 */ 65326, 1, 11, 0,
/* 84 */ 65332, 1, 11, 0,
/* 88 */ 65442, 1, 11, 0,
/* 92 */ 65448, 1, 11, 0,
/* 96 */ 12, 0,
/* 98 */ 65326, 1, 14, 0,
/* 102 */ 65332, 1, 14, 0,
/* 106 */ 65442, 1, 14, 0,
/* 110 */ 65448, 1, 14, 0,
/* 114 */ 21, 0,
/* 116 */ 22, 0,
/* 118 */ 136, 8, 65512, 8, 24, 0,
/* 124 */ 26, 0,
/* 126 */ 65507, 65526, 2, 65535, 27, 0,
/* 132 */ 65534, 65504, 28, 0,
/* 136 */ 65535, 65504, 28, 0,
/* 140 */ 65534, 65506, 28, 0,
/* 144 */ 65535, 65506, 28, 0,
/* 148 */ 65521, 28, 0,
/* 151 */ 2, 6, 29, 0,
/* 155 */ 6, 6, 29, 0,
/* 159 */ 65534, 10, 29, 0,
/* 163 */ 65535, 10, 29, 0,
/* 167 */ 2, 12, 29, 0,
/* 171 */ 3, 12, 29, 0,
/* 175 */ 4, 15, 29, 0,
/* 179 */ 5, 15, 29, 0,
/* 183 */ 65534, 17, 29, 0,
/* 187 */ 65535, 17, 29, 0,
/* 191 */ 1, 19, 29, 0,
/* 195 */ 2, 19, 29, 0,
/* 199 */ 65516, 29, 0,
/* 202 */ 65518, 29, 0,
/* 205 */ 65519, 29, 0,
/* 208 */ 65507, 65530, 65534, 65532, 30, 0,
/* 214 */ 32, 32, 0,
/* 217 */ 65507, 65524, 65534, 65535, 33, 0,
/* 223 */ 65507, 65519, 2, 65535, 34, 0,
/* 229 */ 65507, 65521, 65532, 65535, 38, 0,
/* 235 */ 65507, 65517, 65535, 65535, 39, 0,
/* 241 */ 40, 0,
/* 243 */ 172, 0,
/* 245 */ 173, 0,
/* 247 */ 174, 0,
/* 249 */ 175, 0,
/* 251 */ 176, 0,
/* 253 */ 64761, 0,
/* 255 */ 64799, 0,
/* 257 */ 64870, 0,
/* 259 */ 64893, 0,
/* 261 */ 65520, 65400, 0,
/* 264 */ 16, 65528, 65400, 0,
/* 268 */ 24, 65528, 65400, 0,
/* 272 */ 65421, 0,
/* 274 */ 65423, 0,
/* 276 */ 65461, 0,
/* 278 */ 65493, 0,
/* 280 */ 65504, 65504, 0,
/* 283 */ 65509, 0,
/* 285 */ 65511, 0,
/* 287 */ 65508, 32, 2, 65535, 65518, 0,
/* 293 */ 65508, 30, 2, 65535, 65520, 0,
/* 299 */ 65525, 0,
/* 301 */ 65530, 0,
/* 303 */ 65531, 0,
/* 305 */ 65534, 65532, 0,
/* 308 */ 65507, 20, 65533, 0,
/* 312 */ 65534, 0,
/* 314 */ 2, 65535, 0,
/* 317 */ 65532, 65535, 0,
/* 320 */ 65534, 65535, 0,
/* 323 */ 65535, 65535, 0,
};
extern const LaneBitmask X86LaneMaskLists[] = {
/* 0 */ LaneBitmask(0x0000000000000000), LaneBitmask::getAll(),
/* 2 */ LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000001), LaneBitmask::getAll(),
/* 5 */ LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000000004), LaneBitmask::getAll(),
/* 8 */ LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000000008), LaneBitmask::getAll(),
/* 12 */ LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask::getAll(),
/* 16 */ LaneBitmask(0x0000000000000007), LaneBitmask(0x0000000000000008), LaneBitmask::getAll(),
/* 19 */ LaneBitmask(0x0000000000000010), LaneBitmask(0x0000000000000020), LaneBitmask::getAll(),
/* 22 */ LaneBitmask(0x0000000000000040), LaneBitmask::getAll(),
};
extern const uint16_t X86SubRegIdxLists[] = {
/* 0 */ 1, 2, 0,
/* 3 */ 1, 3, 0,
/* 6 */ 6, 4, 1, 2, 5, 0,
/* 12 */ 6, 4, 1, 3, 5, 0,
/* 18 */ 6, 4, 5, 0,
/* 22 */ 7, 8, 0,
/* 25 */ 10, 9, 0,
};
extern const MCRegisterInfo::SubRegCoveredBits X86SubRegIdxRanges[] = {
{ 65535, 65535 },
{ 0, 8 }, // sub_8bit
{ 8, 8 }, // sub_8bit_hi
{ 8, 8 }, // sub_8bit_hi_phony
{ 0, 16 }, // sub_16bit
{ 16, 16 }, // sub_16bit_hi
{ 0, 32 }, // sub_32bit
{ 0, 65535 }, // sub_mask_0
{ 65535, 65535 }, // sub_mask_1
{ 0, 128 }, // sub_xmm
{ 0, 256 }, // sub_ymm
};
extern const char X86RegStrings[] = {
/* 0 */ 'X', 'M', 'M', '1', '0', 0,
/* 6 */ 'Y', 'M', 'M', '1', '0', 0,
/* 12 */ 'Z', 'M', 'M', '1', '0', 0,
/* 18 */ 'C', 'R', '1', '0', 0,
/* 23 */ 'D', 'R', '1', '0', 0,
/* 28 */ 'X', 'M', 'M', '2', '0', 0,
/* 34 */ 'Y', 'M', 'M', '2', '0', 0,
/* 40 */ 'Z', 'M', 'M', '2', '0', 0,
/* 46 */ 'X', 'M', 'M', '3', '0', 0,
/* 52 */ 'Y', 'M', 'M', '3', '0', 0,
/* 58 */ 'Z', 'M', 'M', '3', '0', 0,
/* 64 */ 'K', '0', 0,
/* 67 */ 'T', 'M', 'M', '0', 0,
/* 72 */ 'X', 'M', 'M', '0', 0,
/* 77 */ 'Y', 'M', 'M', '0', 0,
/* 82 */ 'Z', 'M', 'M', '0', 0,
/* 87 */ 'F', 'P', '0', 0,
/* 91 */ 'C', 'R', '0', 0,
/* 95 */ 'D', 'R', '0', 0,
/* 99 */ 'S', 'T', '0', 0,
/* 103 */ 'X', 'M', 'M', '1', '1', 0,
/* 109 */ 'Y', 'M', 'M', '1', '1', 0,
/* 115 */ 'Z', 'M', 'M', '1', '1', 0,
/* 121 */ 'C', 'R', '1', '1', 0,
/* 126 */ 'D', 'R', '1', '1', 0,
/* 131 */ 'X', 'M', 'M', '2', '1', 0,
/* 137 */ 'Y', 'M', 'M', '2', '1', 0,
/* 143 */ 'Z', 'M', 'M', '2', '1', 0,
/* 149 */ 'X', 'M', 'M', '3', '1', 0,
/* 155 */ 'Y', 'M', 'M', '3', '1', 0,
/* 161 */ 'Z', 'M', 'M', '3', '1', 0,
/* 167 */ 'K', '0', '_', 'K', '1', 0,
/* 173 */ 'T', 'M', 'M', '1', 0,
/* 178 */ 'X', 'M', 'M', '1', 0,
/* 183 */ 'Y', 'M', 'M', '1', 0,
/* 188 */ 'Z', 'M', 'M', '1', 0,
/* 193 */ 'F', 'P', '1', 0,
/* 197 */ 'C', 'R', '1', 0,
/* 201 */ 'D', 'R', '1', 0,
/* 205 */ 'S', 'T', '1', 0,
/* 209 */ 'X', 'M', 'M', '1', '2', 0,
/* 215 */ 'Y', 'M', 'M', '1', '2', 0,
/* 221 */ 'Z', 'M', 'M', '1', '2', 0,
/* 227 */ 'C', 'R', '1', '2', 0,
/* 232 */ 'D', 'R', '1', '2', 0,
/* 237 */ 'X', 'M', 'M', '2', '2', 0,
/* 243 */ 'Y', 'M', 'M', '2', '2', 0,
/* 249 */ 'Z', 'M', 'M', '2', '2', 0,
/* 255 */ 'K', '2', 0,
/* 258 */ 'T', 'M', 'M', '2', 0,
/* 263 */ 'X', 'M', 'M', '2', 0,
/* 268 */ 'Y', 'M', 'M', '2', 0,
/* 273 */ 'Z', 'M', 'M', '2', 0,
/* 278 */ 'F', 'P', '2', 0,
/* 282 */ 'C', 'R', '2', 0,
/* 286 */ 'D', 'R', '2', 0,
/* 290 */ 'S', 'T', '2', 0,
/* 294 */ 'X', 'M', 'M', '1', '3', 0,
/* 300 */ 'Y', 'M', 'M', '1', '3', 0,
/* 306 */ 'Z', 'M', 'M', '1', '3', 0,
/* 312 */ 'C', 'R', '1', '3', 0,
/* 317 */ 'D', 'R', '1', '3', 0,
/* 322 */ 'X', 'M', 'M', '2', '3', 0,
/* 328 */ 'Y', 'M', 'M', '2', '3', 0,
/* 334 */ 'Z', 'M', 'M', '2', '3', 0,
/* 340 */ 'K', '2', '_', 'K', '3', 0,
/* 346 */ 'T', 'M', 'M', '3', 0,
/* 351 */ 'X', 'M', 'M', '3', 0,
/* 356 */ 'Y', 'M', 'M', '3', 0,
/* 361 */ 'Z', 'M', 'M', '3', 0,
/* 366 */ 'F', 'P', '3', 0,
/* 370 */ 'C', 'R', '3', 0,
/* 374 */ 'D', 'R', '3', 0,
/* 378 */ 'S', 'T', '3', 0,
/* 382 */ 'X', 'M', 'M', '1', '4', 0,
/* 388 */ 'Y', 'M', 'M', '1', '4', 0,
/* 394 */ 'Z', 'M', 'M', '1', '4', 0,
/* 400 */ 'C', 'R', '1', '4', 0,
/* 405 */ 'D', 'R', '1', '4', 0,
/* 410 */ 'X', 'M', 'M', '2', '4', 0,
/* 416 */ 'Y', 'M', 'M', '2', '4', 0,
/* 422 */ 'Z', 'M', 'M', '2', '4', 0,
/* 428 */ 'K', '4', 0,
/* 431 */ 'T', 'M', 'M', '4', 0,
/* 436 */ 'X', 'M', 'M', '4', 0,
/* 441 */ 'Y', 'M', 'M', '4', 0,
/* 446 */ 'Z', 'M', 'M', '4', 0,
/* 451 */ 'F', 'P', '4', 0,
/* 455 */ 'C', 'R', '4', 0,
/* 459 */ 'D', 'R', '4', 0,
/* 463 */ 'S', 'T', '4', 0,
/* 467 */ 'X', 'M', 'M', '1', '5', 0,
/* 473 */ 'Y', 'M', 'M', '1', '5', 0,
/* 479 */ 'Z', 'M', 'M', '1', '5', 0,
/* 485 */ 'C', 'R', '1', '5', 0,
/* 490 */ 'D', 'R', '1', '5', 0,
/* 495 */ 'X', 'M', 'M', '2', '5', 0,
/* 501 */ 'Y', 'M', 'M', '2', '5', 0,
/* 507 */ 'Z', 'M', 'M', '2', '5', 0,
/* 513 */ 'K', '4', '_', 'K', '5', 0,
/* 519 */ 'T', 'M', 'M', '5', 0,
/* 524 */ 'X', 'M', 'M', '5', 0,
/* 529 */ 'Y', 'M', 'M', '5', 0,
/* 534 */ 'Z', 'M', 'M', '5', 0,
/* 539 */ 'F', 'P', '5', 0,
/* 543 */ 'C', 'R', '5', 0,
/* 547 */ 'D', 'R', '5', 0,
/* 551 */ 'S', 'T', '5', 0,
/* 555 */ 'X', 'M', 'M', '1', '6', 0,
/* 561 */ 'Y', 'M', 'M', '1', '6', 0,
/* 567 */ 'Z', 'M', 'M', '1', '6', 0,
/* 573 */ 'X', 'M', 'M', '2', '6', 0,
/* 579 */ 'Y', 'M', 'M', '2', '6', 0,
/* 585 */ 'Z', 'M', 'M', '2', '6', 0,
/* 591 */ 'K', '6', 0,
/* 594 */ 'T', 'M', 'M', '6', 0,
/* 599 */ 'X', 'M', 'M', '6', 0,
/* 604 */ 'Y', 'M', 'M', '6', 0,
/* 609 */ 'Z', 'M', 'M', '6', 0,
/* 614 */ 'F', 'P', '6', 0,
/* 618 */ 'C', 'R', '6', 0,
/* 622 */ 'D', 'R', '6', 0,
/* 626 */ 'S', 'T', '6', 0,
/* 630 */ 'X', 'M', 'M', '1', '7', 0,
/* 636 */ 'Y', 'M', 'M', '1', '7', 0,
/* 642 */ 'Z', 'M', 'M', '1', '7', 0,
/* 648 */ 'X', 'M', 'M', '2', '7', 0,
/* 654 */ 'Y', 'M', 'M', '2', '7', 0,
/* 660 */ 'Z', 'M', 'M', '2', '7', 0,
/* 666 */ 'K', '6', '_', 'K', '7', 0,
/* 672 */ 'T', 'M', 'M', '7', 0,
/* 677 */ 'X', 'M', 'M', '7', 0,
/* 682 */ 'Y', 'M', 'M', '7', 0,
/* 687 */ 'Z', 'M', 'M', '7', 0,
/* 692 */ 'F', 'P', '7', 0,
/* 696 */ 'C', 'R', '7', 0,
/* 700 */ 'D', 'R', '7', 0,
/* 704 */ 'S', 'T', '7', 0,
/* 708 */ 'X', 'M', 'M', '1', '8', 0,
/* 714 */ 'Y', 'M', 'M', '1', '8', 0,
/* 720 */ 'Z', 'M', 'M', '1', '8', 0,
/* 726 */ 'X', 'M', 'M', '2', '8', 0,
/* 732 */ 'Y', 'M', 'M', '2', '8', 0,
/* 738 */ 'Z', 'M', 'M', '2', '8', 0,
/* 744 */ 'X', 'M', 'M', '8', 0,
/* 749 */ 'Y', 'M', 'M', '8', 0,
/* 754 */ 'Z', 'M', 'M', '8', 0,
/* 759 */ 'C', 'R', '8', 0,
/* 763 */ 'D', 'R', '8', 0,
/* 767 */ 'X', 'M', 'M', '1', '9', 0,
/* 773 */ 'Y', 'M', 'M', '1', '9', 0,
/* 779 */ 'Z', 'M', 'M', '1', '9', 0,
/* 785 */ 'X', 'M', 'M', '2', '9', 0,
/* 791 */ 'Y', 'M', 'M', '2', '9', 0,
/* 797 */ 'Z', 'M', 'M', '2', '9', 0,
/* 803 */ 'X', 'M', 'M', '9', 0,
/* 808 */ 'Y', 'M', 'M', '9', 0,
/* 813 */ 'Z', 'M', 'M', '9', 0,
/* 818 */ 'C', 'R', '9', 0,
/* 822 */ 'D', 'R', '9', 0,
/* 826 */ 'R', '1', '0', 'B', 0,
/* 831 */ 'R', '1', '1', 'B', 0,
/* 836 */ 'R', '1', '2', 'B', 0,
/* 841 */ 'R', '1', '3', 'B', 0,
/* 846 */ 'R', '1', '4', 'B', 0,
/* 851 */ 'R', '1', '5', 'B', 0,
/* 856 */ 'R', '8', 'B', 0,
/* 860 */ 'R', '9', 'B', 0,
/* 864 */ 'R', '1', '0', 'D', 0,
/* 869 */ 'R', '1', '1', 'D', 0,
/* 874 */ 'R', '1', '2', 'D', 0,
/* 879 */ 'R', '1', '3', 'D', 0,
/* 884 */ 'R', '1', '4', 'D', 0,
/* 889 */ 'R', '1', '5', 'D', 0,
/* 894 */ 'R', '8', 'D', 0,
/* 898 */ 'R', '9', 'D', 0,
/* 902 */ 'F', 'S', '_', 'B', 'A', 'S', 'E', 0,
/* 910 */ 'G', 'S', '_', 'B', 'A', 'S', 'E', 0,
/* 918 */ 'D', 'F', 0,
/* 921 */ 'T', 'M', 'M', 'C', 'F', 'G', 0,
/* 928 */ 'A', 'H', 0,
/* 931 */ 'R', '1', '0', 'B', 'H', 0,
/* 937 */ 'R', '1', '1', 'B', 'H', 0,
/* 943 */ 'R', '1', '2', 'B', 'H', 0,
/* 949 */ 'R', '1', '3', 'B', 'H', 0,
/* 955 */ 'R', '1', '4', 'B', 'H', 0,
/* 961 */ 'R', '1', '5', 'B', 'H', 0,
/* 967 */ 'R', '8', 'B', 'H', 0,
/* 972 */ 'R', '9', 'B', 'H', 0,
/* 977 */ 'C', 'H', 0,
/* 980 */ 'D', 'H', 0,
/* 983 */ 'D', 'I', 'H', 0,
/* 987 */ 'S', 'I', 'H', 0,
/* 991 */ 'B', 'P', 'H', 0,
/* 995 */ 'S', 'P', 'H', 0,
/* 999 */ 'R', '1', '0', 'W', 'H', 0,
/* 1005 */ 'R', '1', '1', 'W', 'H', 0,
/* 1011 */ 'R', '1', '2', 'W', 'H', 0,
/* 1017 */ 'R', '1', '3', 'W', 'H', 0,
/* 1023 */ 'R', '1', '4', 'W', 'H', 0,
/* 1029 */ 'R', '1', '5', 'W', 'H', 0,
/* 1035 */ 'R', '8', 'W', 'H', 0,
/* 1040 */ 'R', '9', 'W', 'H', 0,
/* 1045 */ 'E', 'D', 'I', 0,
/* 1049 */ 'H', 'D', 'I', 0,
/* 1053 */ 'R', 'D', 'I', 0,
/* 1057 */ 'E', 'S', 'I', 0,
/* 1061 */ 'H', 'S', 'I', 0,
/* 1065 */ 'R', 'S', 'I', 0,
/* 1069 */ 'A', 'L', 0,
/* 1072 */ 'B', 'L', 0,
/* 1075 */ 'C', 'L', 0,
/* 1078 */ 'D', 'L', 0,
/* 1081 */ 'D', 'I', 'L', 0,
/* 1085 */ 'S', 'I', 'L', 0,
/* 1089 */ 'B', 'P', 'L', 0,
/* 1093 */ 'S', 'P', 'L', 0,
/* 1097 */ 'E', 'B', 'P', 0,
/* 1101 */ 'H', 'B', 'P', 0,
/* 1105 */ 'R', 'B', 'P', 0,
/* 1109 */ 'E', 'I', 'P', 0,
/* 1113 */ 'H', 'I', 'P', 0,
/* 1117 */ 'R', 'I', 'P', 0,
/* 1121 */ 'E', 'S', 'P', 0,
/* 1125 */ 'H', 'S', 'P', 0,
/* 1129 */ 'R', 'S', 'P', 0,
/* 1133 */ 'S', 'S', 'P', 0,
/* 1137 */ 'M', 'X', 'C', 'S', 'R', 0,
/* 1143 */ 'C', 'S', 0,
/* 1146 */ 'D', 'S', 0,
/* 1149 */ 'E', 'S', 0,
/* 1152 */ 'F', 'S', 0,
/* 1155 */ '_', 'E', 'F', 'L', 'A', 'G', 'S', 0,
/* 1163 */ 'R', 'F', 'L', 'A', 'G', 'S', 0,
/* 1170 */ 'S', 'S', 0,
/* 1173 */ 'R', '1', '0', 'W', 0,
/* 1178 */ 'R', '1', '1', 'W', 0,
/* 1183 */ 'R', '1', '2', 'W', 0,
/* 1188 */ 'R', '1', '3', 'W', 0,
/* 1193 */ 'R', '1', '4', 'W', 0,
/* 1198 */ 'R', '1', '5', 'W', 0,
/* 1203 */ 'R', '8', 'W', 0,
/* 1207 */ 'R', '9', 'W', 0,
/* 1211 */ 'F', 'P', 'C', 'W', 0,
/* 1216 */ 'F', 'P', 'S', 'W', 0,
/* 1221 */ 'E', 'A', 'X', 0,
/* 1225 */ 'H', 'A', 'X', 0,
/* 1229 */ 'R', 'A', 'X', 0,
/* 1233 */ 'E', 'B', 'X', 0,
/* 1237 */ 'H', 'B', 'X', 0,
/* 1241 */ 'R', 'B', 'X', 0,
/* 1245 */ 'E', 'C', 'X', 0,
/* 1249 */ 'H', 'C', 'X', 0,
/* 1253 */ 'R', 'C', 'X', 0,
/* 1257 */ 'E', 'D', 'X', 0,
/* 1261 */ 'H', 'D', 'X', 0,
/* 1265 */ 'R', 'D', 'X', 0,
/* 1269 */ 'E', 'I', 'Z', 0,
/* 1273 */ 'R', 'I', 'Z', 0,
0
};
extern const MCRegisterDesc X86RegDesc[] = { // Descriptors
{ 5, 0, 0, 0, 0, 0 },
{ 928, 2, 195, 2, 5041, 0 },
{ 1069, 2, 191, 2, 5041, 0 },
{ 1222, 323, 192, 0, 0, 2 },
{ 934, 2, 179, 2, 4993, 0 },
{ 1072, 2, 175, 2, 4993, 0 },
{ 1098, 314, 184, 3, 352, 5 },
{ 991, 2, 187, 2, 1008, 0 },
{ 1089, 2, 183, 2, 976, 0 },
{ 1234, 317, 176, 0, 304, 2 },
{ 977, 2, 171, 2, 4897, 0 },
{ 1075, 2, 167, 2, 4897, 0 },
{ 1143, 2, 2, 2, 4897, 0 },
{ 1246, 320, 168, 0, 400, 2 },
{ 918, 2, 2, 2, 4849, 0 },
{ 980, 2, 155, 2, 4849, 0 },
{ 1046, 314, 160, 3, 448, 5 },
{ 983, 2, 163, 2, 1536, 0 },
{ 1081, 2, 159, 2, 4562, 0 },
{ 1078, 2, 151, 2, 4817, 0 },
{ 1146, 2, 2, 2, 4817, 0 },
{ 1258, 305, 152, 0, 928, 2 },
{ 1221, 236, 153, 7, 1764, 8 },
{ 1097, 224, 153, 13, 1476, 12 },
{ 1233, 230, 153, 7, 1700, 8 },
{ 1245, 218, 153, 7, 1412, 8 },
{ 1045, 127, 153, 13, 1109, 12 },
{ 1257, 209, 153, 7, 1168, 8 },
{ 1156, 2, 2, 2, 1824, 0 },
{ 1109, 309, 153, 19, 496, 16 },
{ 1269, 2, 2, 2, 4817, 0 },
{ 1149, 2, 2, 2, 4817, 0 },
{ 1057, 294, 134, 13, 243, 12 },
{ 1121, 288, 134, 13, 243, 12 },
{ 1211, 2, 2, 2, 4993, 0 },
{ 1216, 2, 2, 2, 4993, 0 },
{ 1152, 2, 2, 2, 4993, 0 },
{ 902, 2, 2, 2, 4993, 0 },
{ 1160, 2, 2, 2, 4993, 0 },
{ 910, 2, 2, 2, 4993, 0 },
{ 1225, 2, 202, 2, 4561, 0 },
{ 1101, 2, 202, 2, 4561, 0 },
{ 1237, 2, 202, 2, 4561, 0 },
{ 1249, 2, 202, 2, 4561, 0 },
{ 1049, 2, 202, 2, 4561, 0 },
{ 1261, 2, 202, 2, 4561, 0 },
{ 1113, 2, 205, 2, 4355, 0 },
{ 1061, 2, 148, 2, 4387, 0 },
{ 1125, 2, 148, 2, 4387, 0 },
{ 1110, 2, 199, 2, 1856, 0 },
{ 1137, 2, 2, 2, 3728, 0 },
{ 1229, 235, 2, 6, 1636, 8 },
{ 1105, 223, 2, 12, 1348, 12 },
{ 1241, 229, 2, 6, 1572, 8 },
{ 1253, 217, 2, 6, 1284, 8 },
{ 1053, 126, 2, 12, 1045, 12 },
{ 1265, 208, 2, 6, 1168, 8 },
{ 1163, 2, 2, 2, 3824, 0 },
{ 1117, 308, 2, 18, 496, 16 },
{ 1273, 2, 2, 2, 3856, 0 },
{ 1065, 293, 2, 12, 179, 12 },
{ 1129, 287, 2, 12, 179, 12 },
{ 1058, 314, 141, 3, 544, 5 },
{ 987, 2, 144, 2, 2080, 0 },
{ 1085, 2, 140, 2, 1984, 0 },
{ 1122, 314, 133, 3, 592, 5 },
{ 995, 2, 136, 2, 3392, 0 },
{ 1093, 2, 132, 2, 4060, 0 },
{ 1170, 2, 2, 2, 4529, 0 },
{ 1133, 2, 2, 2, 4529, 0 },
{ 921, 2, 2, 2, 4529, 0 },
{ 1155, 2, 2, 2, 4529, 0 },
{ 91, 2, 2, 2, 4529, 0 },
{ 197, 2, 2, 2, 4529, 0 },
{ 282, 2, 2, 2, 4529, 0 },
{ 370, 2, 2, 2, 4529, 0 },
{ 455, 2, 2, 2, 4529, 0 },
{ 543, 2, 2, 2, 4529, 0 },
{ 618, 2, 2, 2, 4529, 0 },
{ 696, 2, 2, 2, 4529, 0 },
{ 759, 2, 2, 2, 4529, 0 },
{ 818, 2, 2, 2, 4529, 0 },
{ 18, 2, 2, 2, 4529, 0 },
{ 121, 2, 2, 2, 4529, 0 },
{ 227, 2, 2, 2, 4529, 0 },
{ 312, 2, 2, 2, 4529, 0 },
{ 400, 2, 2, 2, 4529, 0 },
{ 485, 2, 2, 2, 4529, 0 },
{ 95, 2, 2, 2, 4529, 0 },
{ 201, 2, 2, 2, 4529, 0 },
{ 286, 2, 2, 2, 4529, 0 },
{ 374, 2, 2, 2, 4529, 0 },
{ 459, 2, 2, 2, 4529, 0 },
{ 547, 2, 2, 2, 4529, 0 },
{ 622, 2, 2, 2, 4529, 0 },
{ 700, 2, 2, 2, 4529, 0 },
{ 763, 2, 2, 2, 4529, 0 },
{ 822, 2, 2, 2, 4529, 0 },
{ 23, 2, 2, 2, 4529, 0 },
{ 126, 2, 2, 2, 4529, 0 },
{ 232, 2, 2, 2, 4529, 0 },
{ 317, 2, 2, 2, 4529, 0 },
{ 405, 2, 2, 2, 4529, 0 },
{ 490, 2, 2, 2, 4529, 0 },
{ 87, 2, 2, 2, 4529, 0 },
{ 193, 2, 2, 2, 4529, 0 },
{ 278, 2, 2, 2, 4529, 0 },
{ 366, 2, 2, 2, 4529, 0 },
{ 451, 2, 2, 2, 4529, 0 },
{ 539, 2, 2, 2, 4529, 0 },
{ 614, 2, 2, 2, 4529, 0 },
{ 692, 2, 2, 2, 4529, 0 },
{ 64, 2, 251, 2, 4529, 0 },
{ 170, 2, 249, 2, 4529, 0 },
{ 255, 2, 249, 2, 4529, 0 },
{ 343, 2, 247, 2, 4529, 0 },
{ 428, 2, 247, 2, 4529, 0 },
{ 516, 2, 245, 2, 4529, 0 },
{ 591, 2, 245, 2, 4529, 0 },
{ 669, 2, 243, 2, 4529, 0 },
{ 68, 2, 2, 2, 4529, 0 },
{ 174, 2, 2, 2, 4529, 0 },
{ 259, 2, 2, 2, 4529, 0 },
{ 347, 2, 2, 2, 4529, 0 },
{ 432, 2, 2, 2, 4529, 0 },
{ 520, 2, 2, 2, 4529, 0 },
{ 595, 2, 2, 2, 4529, 0 },
{ 673, 2, 2, 2, 4529, 0 },
{ 760, 118, 2, 12, 115, 12 },
{ 819, 118, 2, 12, 115, 12 },
{ 19, 118, 2, 12, 115, 12 },
{ 122, 118, 2, 12, 115, 12 },
{ 228, 118, 2, 12, 115, 12 },
{ 313, 118, 2, 12, 115, 12 },
{ 401, 118, 2, 12, 115, 12 },
{ 486, 118, 2, 12, 115, 12 },
{ 99, 2, 2, 2, 4785, 0 },
{ 205, 2, 2, 2, 4785, 0 },
{ 290, 2, 2, 2, 4785, 0 },
{ 378, 2, 2, 2, 4785, 0 },
{ 463, 2, 2, 2, 4785, 0 },
{ 551, 2, 2, 2, 4785, 0 },
{ 626, 2, 2, 2, 4785, 0 },
{ 704, 2, 2, 2, 4785, 0 },
{ 67, 2, 2, 2, 4785, 0 },
{ 173, 2, 2, 2, 4785, 0 },
{ 258, 2, 2, 2, 4785, 0 },
{ 346, 2, 2, 2, 4785, 0 },
{ 431, 2, 2, 2, 4785, 0 },
{ 519, 2, 2, 2, 4785, 0 },
{ 594, 2, 2, 2, 4785, 0 },
{ 672, 2, 2, 2, 4785, 0 },
{ 72, 2, 214, 2, 4785, 0 },
{ 178, 2, 214, 2, 4785, 0 },
{ 263, 2, 214, 2, 4785, 0 },
{ 351, 2, 214, 2, 4785, 0 },
{ 436, 2, 214, 2, 4785, 0 },
{ 524, 2, 214, 2, 4785, 0 },
{ 599, 2, 214, 2, 4785, 0 },
{ 677, 2, 214, 2, 4785, 0 },
{ 744, 2, 214, 2, 4785, 0 },
{ 803, 2, 214, 2, 4785, 0 },
{ 0, 2, 214, 2, 4785, 0 },
{ 103, 2, 214, 2, 4785, 0 },
{ 209, 2, 214, 2, 4785, 0 },
{ 294, 2, 214, 2, 4785, 0 },
{ 382, 2, 214, 2, 4785, 0 },
{ 467, 2, 214, 2, 4785, 0 },
{ 555, 2, 214, 2, 4785, 0 },
{ 630, 2, 214, 2, 4785, 0 },
{ 708, 2, 214, 2, 4785, 0 },
{ 767, 2, 214, 2, 4785, 0 },
{ 28, 2, 214, 2, 4785, 0 },
{ 131, 2, 214, 2, 4785, 0 },
{ 237, 2, 214, 2, 4785, 0 },
{ 322, 2, 214, 2, 4785, 0 },
{ 410, 2, 214, 2, 4785, 0 },
{ 495, 2, 214, 2, 4785, 0 },
{ 573, 2, 214, 2, 4785, 0 },
{ 648, 2, 214, 2, 4785, 0 },
{ 726, 2, 214, 2, 4785, 0 },
{ 785, 2, 214, 2, 4785, 0 },
{ 46, 2, 214, 2, 4785, 0 },
{ 149, 2, 214, 2, 4785, 0 },
{ 77, 281, 215, 26, 4449, 22 },
{ 183, 281, 215, 26, 4449, 22 },
{ 268, 281, 215, 26, 4449, 22 },
{ 356, 281, 215, 26, 4449, 22 },
{ 441, 281, 215, 26, 4449, 22 },
{ 529, 281, 215, 26, 4449, 22 },
{ 604, 281, 215, 26, 4449, 22 },
{ 682, 281, 215, 26, 4449, 22 },
{ 749, 281, 215, 26, 4449, 22 },
{ 808, 281, 215, 26, 4449, 22 },
{ 6, 281, 215, 26, 4449, 22 },
{ 109, 281, 215, 26, 4449, 22 },
{ 215, 281, 215, 26, 4449, 22 },
{ 300, 281, 215, 26, 4449, 22 },
{ 388, 281, 215, 26, 4449, 22 },
{ 473, 281, 215, 26, 4449, 22 },
{ 561, 281, 215, 26, 4449, 22 },
{ 636, 281, 215, 26, 4449, 22 },
{ 714, 281, 215, 26, 4449, 22 },
{ 773, 281, 215, 26, 4449, 22 },
{ 34, 281, 215, 26, 4449, 22 },
{ 137, 281, 215, 26, 4449, 22 },
{ 243, 281, 215, 26, 4449, 22 },
{ 328, 281, 215, 26, 4449, 22 },
{ 416, 281, 215, 26, 4449, 22 },
{ 501, 281, 215, 26, 4449, 22 },
{ 579, 281, 215, 26, 4449, 22 },
{ 654, 281, 215, 26, 4449, 22 },
{ 732, 281, 215, 26, 4449, 22 },
{ 791, 281, 215, 26, 4449, 22 },
{ 52, 281, 215, 26, 4449, 22 },
{ 155, 281, 215, 26, 4449, 22 },
{ 82, 280, 2, 25, 4417, 22 },
{ 188, 280, 2, 25, 4417, 22 },
{ 273, 280, 2, 25, 4417, 22 },
{ 361, 280, 2, 25, 4417, 22 },
{ 446, 280, 2, 25, 4417, 22 },
{ 534, 280, 2, 25, 4417, 22 },
{ 609, 280, 2, 25, 4417, 22 },
{ 687, 280, 2, 25, 4417, 22 },
{ 754, 280, 2, 25, 4417, 22 },
{ 813, 280, 2, 25, 4417, 22 },
{ 12, 280, 2, 25, 4417, 22 },
{ 115, 280, 2, 25, 4417, 22 },
{ 221, 280, 2, 25, 4417, 22 },
{ 306, 280, 2, 25, 4417, 22 },
{ 394, 280, 2, 25, 4417, 22 },
{ 479, 280, 2, 25, 4417, 22 },
{ 567, 280, 2, 25, 4417, 22 },
{ 642, 280, 2, 25, 4417, 22 },
{ 720, 280, 2, 25, 4417, 22 },
{ 779, 280, 2, 25, 4417, 22 },
{ 40, 280, 2, 25, 4417, 22 },
{ 143, 280, 2, 25, 4417, 22 },
{ 249, 280, 2, 25, 4417, 22 },
{ 334, 280, 2, 25, 4417, 22 },
{ 422, 280, 2, 25, 4417, 22 },
{ 507, 280, 2, 25, 4417, 22 },
{ 585, 280, 2, 25, 4417, 22 },
{ 660, 280, 2, 25, 4417, 22 },
{ 738, 280, 2, 25, 4417, 22 },
{ 797, 280, 2, 25, 4417, 22 },
{ 58, 280, 2, 25, 4417, 22 },
{ 161, 280, 2, 25, 4417, 22 },
{ 856, 2, 268, 2, 4147, 0 },
{ 860, 2, 268, 2, 4147, 0 },
{ 826, 2, 268, 2, 4147, 0 },
{ 831, 2, 268, 2, 4147, 0 },
{ 836, 2, 268, 2, 4147, 0 },
{ 841, 2, 268, 2, 4147, 0 },
{ 846, 2, 268, 2, 4147, 0 },
{ 851, 2, 268, 2, 4147, 0 },
{ 967, 2, 264, 2, 4115, 0 },
{ 972, 2, 264, 2, 4115, 0 },
{ 931, 2, 264, 2, 4115, 0 },
{ 937, 2, 264, 2, 4115, 0 },
{ 943, 2, 264, 2, 4115, 0 },
{ 949, 2, 264, 2, 4115, 0 },
{ 955, 2, 264, 2, 4115, 0 },
{ 961, 2, 264, 2, 4115, 0 },
{ 894, 119, 262, 13, 51, 12 },
{ 898, 119, 262, 13, 51, 12 },
{ 864, 119, 262, 13, 51, 12 },
{ 869, 119, 262, 13, 51, 12 },
{ 874, 119, 262, 13, 51, 12 },
{ 879, 119, 262, 13, 51, 12 },
{ 884, 119, 262, 13, 51, 12 },
{ 889, 119, 262, 13, 51, 12 },
{ 1203, 77, 265, 3, 643, 5 },
{ 1207, 77, 265, 3, 643, 5 },
{ 1173, 77, 265, 3, 643, 5 },
{ 1178, 77, 265, 3, 643, 5 },
{ 1183, 77, 265, 3, 643, 5 },
{ 1188, 77, 265, 3, 643, 5 },
{ 1193, 77, 265, 3, 643, 5 },
{ 1198, 77, 265, 3, 643, 5 },
{ 1035, 2, 261, 2, 4083, 0 },
{ 1040, 2, 261, 2, 4083, 0 },
{ 999, 2, 261, 2, 4083, 0 },
{ 1005, 2, 261, 2, 4083, 0 },
{ 1011, 2, 261, 2, 4083, 0 },
{ 1017, 2, 261, 2, 4083, 0 },
{ 1023, 2, 261, 2, 4083, 0 },
{ 1029, 2, 261, 2, 4083, 0 },
{ 167, 46, 2, 22, 690, 19 },
{ 340, 49, 2, 22, 690, 19 },
{ 513, 52, 2, 22, 690, 19 },
{ 666, 55, 2, 22, 690, 19 },
};
extern const MCPhysReg X86RegUnitRoots[][2] = {
{ X86::AH },
{ X86::AL },
{ X86::BH },
{ X86::BL },
{ X86::BPL },
{ X86::BPH },
{ X86::CH },
{ X86::CL },
{ X86::CS },
{ X86::DF },
{ X86::DH },
{ X86::DIL },
{ X86::DIH },
{ X86::DL },
{ X86::DS },
{ X86::HAX },
{ X86::HBP },
{ X86::HBX },
{ X86::HCX },
{ X86::HDI },
{ X86::HDX },
{ X86::EFLAGS },
{ X86::IP },
{ X86::HIP },
{ X86::EIZ },
{ X86::ES },
{ X86::SIL },
{ X86::SIH },
{ X86::HSI },
{ X86::SPL },
{ X86::SPH },
{ X86::HSP },
{ X86::FPCW },
{ X86::FPSW },
{ X86::FS },
{ X86::FS_BASE },
{ X86::GS },
{ X86::GS_BASE },
{ X86::MXCSR },
{ X86::RFLAGS },
{ X86::RIZ },
{ X86::SS },
{ X86::SSP },
{ X86::TMMCFG },
{ X86::_EFLAGS },
{ X86::CR0 },
{ X86::CR1 },
{ X86::CR2 },
{ X86::CR3 },
{ X86::CR4 },
{ X86::CR5 },
{ X86::CR6 },
{ X86::CR7 },
{ X86::CR8 },
{ X86::CR9 },
{ X86::CR10 },
{ X86::CR11 },
{ X86::CR12 },
{ X86::CR13 },
{ X86::CR14 },
{ X86::CR15 },
{ X86::DR0 },
{ X86::DR1 },
{ X86::DR2 },
{ X86::DR3 },
{ X86::DR4 },
{ X86::DR5 },
{ X86::DR6 },
{ X86::DR7 },
{ X86::DR8 },
{ X86::DR9 },
{ X86::DR10 },
{ X86::DR11 },
{ X86::DR12 },
{ X86::DR13 },
{ X86::DR14 },
{ X86::DR15 },
{ X86::FP0 },
{ X86::FP1 },
{ X86::FP2 },
{ X86::FP3 },
{ X86::FP4 },
{ X86::FP5 },
{ X86::FP6 },
{ X86::FP7 },
{ X86::K0 },
{ X86::K1 },
{ X86::K2 },
{ X86::K3 },
{ X86::K4 },
{ X86::K5 },
{ X86::K6 },
{ X86::K7 },
{ X86::MM0 },
{ X86::MM1 },
{ X86::MM2 },
{ X86::MM3 },
{ X86::MM4 },
{ X86::MM5 },
{ X86::MM6 },
{ X86::MM7 },
{ X86::R8B },
{ X86::R8BH },
{ X86::R8WH },
{ X86::R9B },
{ X86::R9BH },
{ X86::R9WH },
{ X86::R10B },
{ X86::R10BH },
{ X86::R10WH },
{ X86::R11B },
{ X86::R11BH },
{ X86::R11WH },
{ X86::R12B },
{ X86::R12BH },
{ X86::R12WH },
{ X86::R13B },
{ X86::R13BH },
{ X86::R13WH },
{ X86::R14B },
{ X86::R14BH },
{ X86::R14WH },
{ X86::R15B },
{ X86::R15BH },
{ X86::R15WH },
{ X86::ST0 },
{ X86::ST1 },
{ X86::ST2 },
{ X86::ST3 },
{ X86::ST4 },
{ X86::ST5 },
{ X86::ST6 },
{ X86::ST7 },
{ X86::TMM0 },
{ X86::TMM1 },
{ X86::TMM2 },
{ X86::TMM3 },
{ X86::TMM4 },
{ X86::TMM5 },
{ X86::TMM6 },
{ X86::TMM7 },
{ X86::XMM0 },
{ X86::XMM1 },
{ X86::XMM2 },
{ X86::XMM3 },
{ X86::XMM4 },
{ X86::XMM5 },
{ X86::XMM6 },
{ X86::XMM7 },
{ X86::XMM8 },
{ X86::XMM9 },
{ X86::XMM10 },
{ X86::XMM11 },
{ X86::XMM12 },
{ X86::XMM13 },
{ X86::XMM14 },
{ X86::XMM15 },
{ X86::XMM16 },
{ X86::XMM17 },
{ X86::XMM18 },
{ X86::XMM19 },
{ X86::XMM20 },
{ X86::XMM21 },
{ X86::XMM22 },
{ X86::XMM23 },
{ X86::XMM24 },
{ X86::XMM25 },
{ X86::XMM26 },
{ X86::XMM27 },
{ X86::XMM28 },
{ X86::XMM29 },
{ X86::XMM30 },
{ X86::XMM31 },
};
namespace { // Register classes...
// GR8 Register Class...
const MCPhysReg GR8[] = {
X86::AL, X86::CL, X86::DL, X86::AH, X86::CH, X86::DH, X86::BL, X86::BH, X86::SIL, X86::DIL, X86::BPL, X86::SPL, X86::R8B, X86::R9B, X86::R10B, X86::R11B, X86::R14B, X86::R15B, X86::R12B, X86::R13B,
};
// GR8 Bit set.
const uint8_t GR8Bits[] = {
0x36, 0x8d, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff,
};
// GRH8 Register Class...
const MCPhysReg GRH8[] = {
X86::SIH, X86::DIH, X86::BPH, X86::SPH, X86::R8BH, X86::R9BH, X86::R10BH, X86::R11BH, X86::R12BH, X86::R13BH, X86::R14BH, X86::R15BH,
};
// GRH8 Bit set.
const uint8_t GRH8Bits[] = {
0x80, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x80, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff,
};
// GR8_NOREX Register Class...
const MCPhysReg GR8_NOREX[] = {
X86::AL, X86::CL, X86::DL, X86::AH, X86::CH, X86::DH, X86::BL, X86::BH,
};
// GR8_NOREX Bit set.
const uint8_t GR8_NOREXBits[] = {
0x36, 0x8c, 0x08,
};
// GR8_ABCD_H Register Class...
const MCPhysReg GR8_ABCD_H[] = {
X86::AH, X86::CH, X86::DH, X86::BH,
};
// GR8_ABCD_H Bit set.
const uint8_t GR8_ABCD_HBits[] = {
0x12, 0x84,
};
// GR8_ABCD_L Register Class...
const MCPhysReg GR8_ABCD_L[] = {
X86::AL, X86::CL, X86::DL, X86::BL,
};
// GR8_ABCD_L Bit set.
const uint8_t GR8_ABCD_LBits[] = {
0x24, 0x08, 0x08,
};
// GRH16 Register Class...
const MCPhysReg GRH16[] = {
X86::HAX, X86::HCX, X86::HDX, X86::HSI, X86::HDI, X86::HBX, X86::HBP, X86::HSP, X86::HIP, X86::R8WH, X86::R9WH, X86::R10WH, X86::R11WH, X86::R12WH, X86::R13WH, X86::R14WH, X86::R15WH,
};
// GRH16 Bit set.
const uint8_t GRH16Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff,
};
// GR16 Register Class...
const MCPhysReg GR16[] = {
X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, X86::BX, X86::BP, X86::SP, X86::R8W, X86::R9W, X86::R10W, X86::R11W, X86::R14W, X86::R15W, X86::R12W, X86::R13W,
};
// GR16 Bit set.
const uint8_t GR16Bits[] = {
0x48, 0x22, 0x21, 0x00, 0x00, 0x00, 0x00, 0x40, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff,
};
// GR16_NOREX Register Class...
const MCPhysReg GR16_NOREX[] = {
X86::AX, X86::CX, X86::DX, X86::SI, X86::DI, X86::BX, X86::BP, X86::SP,
};
// GR16_NOREX Bit set.
const uint8_t GR16_NOREXBits[] = {
0x48, 0x22, 0x21, 0x00, 0x00, 0x00, 0x00, 0x40, 0x02,
};
// VK1 Register Class...
const MCPhysReg VK1[] = {
X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
};
// VK1 Bit set.
const uint8_t VK1Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff,
};
// VK16 Register Class...
const MCPhysReg VK16[] = {
X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
};
// VK16 Bit set.
const uint8_t VK16Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff,
};
// VK2 Register Class...
const MCPhysReg VK2[] = {
X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
};
// VK2 Bit set.
const uint8_t VK2Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff,
};
// VK4 Register Class...
const MCPhysReg VK4[] = {
X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
};
// VK4 Bit set.
const uint8_t VK4Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff,
};
// VK8 Register Class...
const MCPhysReg VK8[] = {
X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
};
// VK8 Bit set.
const uint8_t VK8Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff,
};
// VK16WM Register Class...
const MCPhysReg VK16WM[] = {
X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
};
// VK16WM Bit set.
const uint8_t VK16WMBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe,
};
// VK1WM Register Class...
const MCPhysReg VK1WM[] = {
X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
};
// VK1WM Bit set.
const uint8_t VK1WMBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe,
};
// VK2WM Register Class...
const MCPhysReg VK2WM[] = {
X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
};
// VK2WM Bit set.
const uint8_t VK2WMBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe,
};
// VK4WM Register Class...
const MCPhysReg VK4WM[] = {
X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
};
// VK4WM Bit set.
const uint8_t VK4WMBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe,
};
// VK8WM Register Class...
const MCPhysReg VK8WM[] = {
X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
};
// VK8WM Bit set.
const uint8_t VK8WMBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe,
};
// SEGMENT_REG Register Class...
const MCPhysReg SEGMENT_REG[] = {
X86::CS, X86::DS, X86::SS, X86::ES, X86::FS, X86::GS,
};
// SEGMENT_REG Bit set.
const uint8_t SEGMENT_REGBits[] = {
0x00, 0x10, 0x10, 0x80, 0x50, 0x00, 0x00, 0x00, 0x10,
};
// GR16_ABCD Register Class...
const MCPhysReg GR16_ABCD[] = {
X86::AX, X86::CX, X86::DX, X86::BX,
};
// GR16_ABCD Bit set.
const uint8_t GR16_ABCDBits[] = {
0x08, 0x22, 0x20,
};
// FPCCR Register Class...
const MCPhysReg FPCCR[] = {
X86::FPSW,
};
// FPCCR Bit set.
const uint8_t FPCCRBits[] = {
0x00, 0x00, 0x00, 0x00, 0x08,
};
// FR16X Register Class...
const MCPhysReg FR16X[] = {
X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::XMM16, X86::XMM17, X86::XMM18, X86::XMM19, X86::XMM20, X86::XMM21, X86::XMM22, X86::XMM23, X86::XMM24, X86::XMM25, X86::XMM26, X86::XMM27, X86::XMM28, X86::XMM29, X86::XMM30, X86::XMM31,
};
// FR16X Bit set.
const uint8_t FR16XBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
};
// FR16 Register Class...
const MCPhysReg FR16[] = {
X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15,
};
// FR16 Bit set.
const uint8_t FR16Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff,
};
// VK16PAIR Register Class...
const MCPhysReg VK16PAIR[] = {
X86::K0_K1, X86::K2_K3, X86::K4_K5, X86::K6_K7,
};
// VK16PAIR Bit set.
const uint8_t VK16PAIRBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f,
};
// VK1PAIR Register Class...
const MCPhysReg VK1PAIR[] = {
X86::K0_K1, X86::K2_K3, X86::K4_K5, X86::K6_K7,
};
// VK1PAIR Bit set.
const uint8_t VK1PAIRBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f,
};
// VK2PAIR Register Class...
const MCPhysReg VK2PAIR[] = {
X86::K0_K1, X86::K2_K3, X86::K4_K5, X86::K6_K7,
};
// VK2PAIR Bit set.
const uint8_t VK2PAIRBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f,
};
// VK4PAIR Register Class...
const MCPhysReg VK4PAIR[] = {
X86::K0_K1, X86::K2_K3, X86::K4_K5, X86::K6_K7,
};
// VK4PAIR Bit set.
const uint8_t VK4PAIRBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f,
};
// VK8PAIR Register Class...
const MCPhysReg VK8PAIR[] = {
X86::K0_K1, X86::K2_K3, X86::K4_K5, X86::K6_K7,
};
// VK8PAIR Bit set.
const uint8_t VK8PAIRBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f,
};
// VK16PAIR_with_sub_mask_0_in_VK16WM Register Class...
const MCPhysReg VK16PAIR_with_sub_mask_0_in_VK16WM[] = {
X86::K2_K3, X86::K4_K5, X86::K6_K7,
};
// VK16PAIR_with_sub_mask_0_in_VK16WM Bit set.
const uint8_t VK16PAIR_with_sub_mask_0_in_VK16WMBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0e,
};
// FR32X Register Class...
const MCPhysReg FR32X[] = {
X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::XMM16, X86::XMM17, X86::XMM18, X86::XMM19, X86::XMM20, X86::XMM21, X86::XMM22, X86::XMM23, X86::XMM24, X86::XMM25, X86::XMM26, X86::XMM27, X86::XMM28, X86::XMM29, X86::XMM30, X86::XMM31,
};
// FR32X Bit set.
const uint8_t FR32XBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
};
// LOW32_ADDR_ACCESS_RBP Register Class...
const MCPhysReg LOW32_ADDR_ACCESS_RBP[] = {
X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::RIP, X86::RBP,
};
// LOW32_ADDR_ACCESS_RBP Bit set.
const uint8_t LOW32_ADDR_ACCESS_RBPBits[] = {
0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x10, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff,
};
// LOW32_ADDR_ACCESS Register Class...
const MCPhysReg LOW32_ADDR_ACCESS[] = {
X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::RIP,
};
// LOW32_ADDR_ACCESS Bit set.
const uint8_t LOW32_ADDR_ACCESSBits[] = {
0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff,
};
// LOW32_ADDR_ACCESS_RBP_with_sub_8bit Register Class...
const MCPhysReg LOW32_ADDR_ACCESS_RBP_with_sub_8bit[] = {
X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R14D, X86::R15D, X86::R12D, X86::R13D, X86::RBP,
};
// LOW32_ADDR_ACCESS_RBP_with_sub_8bit Bit set.
const uint8_t LOW32_ADDR_ACCESS_RBP_with_sub_8bitBits[] = {
0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff,
};
// DEBUG_REG Register Class...
const MCPhysReg DEBUG_REG[] = {
X86::DR0, X86::DR1, X86::DR2, X86::DR3, X86::DR4, X86::DR5, X86::DR6, X86::DR7, X86::DR8, X86::DR9, X86::DR10, X86::DR11, X86::DR12, X86::DR13, X86::DR14, X86::DR15,
};
// DEBUG_REG Bit set.
const uint8_t DEBUG_REGBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff,
};
// FR32 Register Class...
const MCPhysReg FR32[] = {
X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15,
};
// FR32 Bit set.
const uint8_t FR32Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff,
};
// GR32 Register Class...
const MCPhysReg GR32[] = {
X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R14D, X86::R15D, X86::R12D, X86::R13D,
};
// GR32 Bit set.
const uint8_t GR32Bits[] = {
0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff,
};
// GR32_NOSP Register Class...
const MCPhysReg GR32_NOSP[] = {
X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::R8D, X86::R9D, X86::R10D, X86::R11D, X86::R14D, X86::R15D, X86::R12D, X86::R13D,
};
// GR32_NOSP Bit set.
const uint8_t GR32_NOSPBits[] = {
0x00, 0x00, 0xc0, 0x0f, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff,
};
// LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX Register Class...
const MCPhysReg LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX[] = {
X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP, X86::RBP,
};
// LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX Bit set.
const uint8_t LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXBits[] = {
0x00, 0x00, 0xc0, 0x0f, 0x03, 0x00, 0x10,
};
// GR32_NOREX Register Class...
const MCPhysReg GR32_NOREX[] = {
X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, X86::ESP,
};
// GR32_NOREX Bit set.
const uint8_t GR32_NOREXBits[] = {
0x00, 0x00, 0xc0, 0x0f, 0x03,
};
// VK32 Register Class...
const MCPhysReg VK32[] = {
X86::K0, X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
};
// VK32 Bit set.
const uint8_t VK32Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff,
};
// GR32_NOREX_NOSP Register Class...
const MCPhysReg GR32_NOREX_NOSP[] = {
X86::EAX, X86::ECX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP,
};
// GR32_NOREX_NOSP Bit set.
const uint8_t GR32_NOREX_NOSPBits[] = {
0x00, 0x00, 0xc0, 0x0f, 0x01,
};
// RFP32 Register Class...
const MCPhysReg RFP32[] = {
X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6,
};
// RFP32 Bit set.
const uint8_t RFP32Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f,
};
// VK32WM Register Class...
const MCPhysReg VK32WM[] = {
X86::K1, X86::K2, X86::K3, X86::K4, X86::K5, X86::K6, X86::K7,
};
// VK32WM Bit set.
const uint8_t VK32WMBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe,
};
// GR32_ABCD Register Class...
const MCPhysReg GR32_ABCD[] = {
X86::EAX, X86::ECX, X86::EDX, X86::EBX,
};
// GR32_ABCD Bit set.
const uint8_t GR32_ABCDBits[] = {
0x00, 0x00, 0x40, 0x0b,
};
// GR32_TC Register Class...
const MCPhysReg GR32_TC[] = {
X86::EAX, X86::ECX, X86::EDX, X86::ESP,
};
// GR32_TC Bit set.
const uint8_t GR32_TCBits[] = {
0x00, 0x00, 0x40, 0x0a, 0x02,
};
// GR32_ABCD_and_GR32_TC Register Class...
const MCPhysReg GR32_ABCD_and_GR32_TC[] = {
X86::EAX, X86::ECX, X86::EDX,
};
// GR32_ABCD_and_GR32_TC Bit set.
const uint8_t GR32_ABCD_and_GR32_TCBits[] = {
0x00, 0x00, 0x40, 0x0a,
};
// GR32_AD Register Class...
const MCPhysReg GR32_AD[] = {
X86::EAX, X86::EDX,
};
// GR32_AD Bit set.
const uint8_t GR32_ADBits[] = {
0x00, 0x00, 0x40, 0x08,
};
// GR32_BPSP Register Class...
const MCPhysReg GR32_BPSP[] = {
X86::EBP, X86::ESP,
};
// GR32_BPSP Bit set.
const uint8_t GR32_BPSPBits[] = {
0x00, 0x00, 0x80, 0x00, 0x02,
};
// GR32_BSI Register Class...
const MCPhysReg GR32_BSI[] = {
X86::EBX, X86::ESI,
};
// GR32_BSI Bit set.
const uint8_t GR32_BSIBits[] = {
0x00, 0x00, 0x00, 0x01, 0x01,
};
// GR32_CB Register Class...
const MCPhysReg GR32_CB[] = {
X86::ECX, X86::EBX,
};
// GR32_CB Bit set.
const uint8_t GR32_CBBits[] = {
0x00, 0x00, 0x00, 0x03,
};
// GR32_DC Register Class...
const MCPhysReg GR32_DC[] = {
X86::EDX, X86::ECX,
};
// GR32_DC Bit set.
const uint8_t GR32_DCBits[] = {
0x00, 0x00, 0x00, 0x0a,
};
// GR32_DIBP Register Class...
const MCPhysReg GR32_DIBP[] = {
X86::EDI, X86::EBP,
};
// GR32_DIBP Bit set.
const uint8_t GR32_DIBPBits[] = {
0x00, 0x00, 0x80, 0x04,
};
// GR32_SIDI Register Class...
const MCPhysReg GR32_SIDI[] = {
X86::ESI, X86::EDI,
};
// GR32_SIDI Bit set.
const uint8_t GR32_SIDIBits[] = {
0x00, 0x00, 0x00, 0x04, 0x01,
};
// LOW32_ADDR_ACCESS_RBP_with_sub_32bit Register Class...
const MCPhysReg LOW32_ADDR_ACCESS_RBP_with_sub_32bit[] = {
X86::RIP, X86::RBP,
};
// LOW32_ADDR_ACCESS_RBP_with_sub_32bit Bit set.
const uint8_t LOW32_ADDR_ACCESS_RBP_with_sub_32bitBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x04,
};
// CCR Register Class...
const MCPhysReg CCR[] = {
X86::EFLAGS,
};
// CCR Bit set.
const uint8_t CCRBits[] = {
0x00, 0x00, 0x00, 0x10,
};
// DFCCR Register Class...
const MCPhysReg DFCCR[] = {
X86::DF,
};
// DFCCR Bit set.
const uint8_t DFCCRBits[] = {
0x00, 0x40,
};
// GR32_ABCD_and_GR32_BSI Register Class...
const MCPhysReg GR32_ABCD_and_GR32_BSI[] = {
X86::EBX,
};
// GR32_ABCD_and_GR32_BSI Bit set.
const uint8_t GR32_ABCD_and_GR32_BSIBits[] = {
0x00, 0x00, 0x00, 0x01,
};
// GR32_AD_and_GR32_DC Register Class...
const MCPhysReg GR32_AD_and_GR32_DC[] = {
X86::EDX,
};
// GR32_AD_and_GR32_DC Bit set.
const uint8_t GR32_AD_and_GR32_DCBits[] = {
0x00, 0x00, 0x00, 0x08,
};
// GR32_BPSP_and_GR32_DIBP Register Class...
const MCPhysReg GR32_BPSP_and_GR32_DIBP[] = {
X86::EBP,
};
// GR32_BPSP_and_GR32_DIBP Bit set.
const uint8_t GR32_BPSP_and_GR32_DIBPBits[] = {
0x00, 0x00, 0x80,
};
// GR32_BPSP_and_GR32_TC Register Class...
const MCPhysReg GR32_BPSP_and_GR32_TC[] = {
X86::ESP,
};
// GR32_BPSP_and_GR32_TC Bit set.
const uint8_t GR32_BPSP_and_GR32_TCBits[] = {
0x00, 0x00, 0x00, 0x00, 0x02,
};
// GR32_BSI_and_GR32_SIDI Register Class...
const MCPhysReg GR32_BSI_and_GR32_SIDI[] = {
X86::ESI,
};
// GR32_BSI_and_GR32_SIDI Bit set.
const uint8_t GR32_BSI_and_GR32_SIDIBits[] = {
0x00, 0x00, 0x00, 0x00, 0x01,
};
// GR32_CB_and_GR32_DC Register Class...
const MCPhysReg GR32_CB_and_GR32_DC[] = {
X86::ECX,
};
// GR32_CB_and_GR32_DC Bit set.
const uint8_t GR32_CB_and_GR32_DCBits[] = {
0x00, 0x00, 0x00, 0x02,
};
// GR32_DIBP_and_GR32_SIDI Register Class...
const MCPhysReg GR32_DIBP_and_GR32_SIDI[] = {
X86::EDI,
};
// GR32_DIBP_and_GR32_SIDI Bit set.
const uint8_t GR32_DIBP_and_GR32_SIDIBits[] = {
0x00, 0x00, 0x00, 0x04,
};
// LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit Register Class...
const MCPhysReg LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit[] = {
X86::RBP,
};
// LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit Bit set.
const uint8_t LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
};
// LOW32_ADDR_ACCESS_with_sub_32bit Register Class...
const MCPhysReg LOW32_ADDR_ACCESS_with_sub_32bit[] = {
X86::RIP,
};
// LOW32_ADDR_ACCESS_with_sub_32bit Bit set.
const uint8_t LOW32_ADDR_ACCESS_with_sub_32bitBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04,
};
// RFP64 Register Class...
const MCPhysReg RFP64[] = {
X86::FP0, X86::FP1, X86::FP2, X86::FP3, X86::FP4, X86::FP5, X86::FP6,
};
// RFP64 Bit set.
const uint8_t RFP64Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f,
};
// FR64X Register Class...
const MCPhysReg FR64X[] = {
X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15, X86::XMM16, X86::XMM17, X86::XMM18, X86::XMM19, X86::XMM20, X86::XMM21, X86::XMM22, X86::XMM23, X86::XMM24, X86::XMM25, X86::XMM26, X86::XMM27, X86::XMM28, X86::XMM29, X86::XMM30, X86::XMM31,
};
// FR64X Bit set.
const uint8_t FR64XBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
};
// GR64 Register Class...
const MCPhysReg GR64[] = {
X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::RBX, X86::R14, X86::R15, X86::R12, X86::R13, X86::RBP, X86::RSP, X86::RIP,
};
// GR64 Bit set.
const uint8_t GR64Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x35, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff,
};
// CONTROL_REG Register Class...
const MCPhysReg CONTROL_REG[] = {
X86::CR0, X86::CR1, X86::CR2, X86::CR3, X86::CR4, X86::CR5, X86::CR6, X86::CR7, X86::CR8, X86::CR9, X86::CR10, X86::CR11, X86::CR12, X86::CR13, X86::CR14, X86::CR15,
};
// CONTROL_REG Bit set.
const uint8_t CONTROL_REGBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff,
};
// FR64 Register Class...
const MCPhysReg FR64[] = {
X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, X86::XMM14, X86::XMM15,
};
// FR64 Bit set.
const uint8_t FR64Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff,
};
// GR64_with_sub_8bit Register Class...
const MCPhysReg GR64_with_sub_8bit[] = {
X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::RBX, X86::R14, X86::R15, X86::R12, X86::R13, X86::RBP, X86::RSP,
};
// GR64_with_sub_8bit Bit set.
const uint8_t GR64_with_sub_8bitBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x31, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff,
};
// GR64_NOSP Register Class...
const MCPhysReg GR64_NOSP[] = {
X86::RAX, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::RBX, X86::R14, X86::R15, X86::R12, X86::R13, X86::RBP,
};
// GR64_NOSP Bit set