blob: 737b8418cfc375ed5496b2a7eb3721b56fa5707a [file] [log] [blame]
#ifdef GET_RISCVMaskedPseudosTable_DECL
const RISCVMaskedPseudoInfo *getMaskedPseudoInfo(unsigned MaskedPseudo);
const RISCVMaskedPseudoInfo *lookupMaskedIntrinsicByUnmaskedTA(unsigned UnmaskedPseudo);
#endif
#ifdef GET_RISCVMaskedPseudosTable_IMPL
constexpr RISCVMaskedPseudoInfo RISCVMaskedPseudosTable[] = {
{ PseudoVAADDU_VV_M1_MASK, PseudoVAADDU_VV_M1, PseudoVAADDU_VV_M1_TU, 0x3 }, // 0
{ PseudoVAADDU_VV_M2_MASK, PseudoVAADDU_VV_M2, PseudoVAADDU_VV_M2_TU, 0x3 }, // 1
{ PseudoVAADDU_VV_M4_MASK, PseudoVAADDU_VV_M4, PseudoVAADDU_VV_M4_TU, 0x3 }, // 2
{ PseudoVAADDU_VV_M8_MASK, PseudoVAADDU_VV_M8, PseudoVAADDU_VV_M8_TU, 0x3 }, // 3
{ PseudoVAADDU_VV_MF2_MASK, PseudoVAADDU_VV_MF2, PseudoVAADDU_VV_MF2_TU, 0x3 }, // 4
{ PseudoVAADDU_VV_MF4_MASK, PseudoVAADDU_VV_MF4, PseudoVAADDU_VV_MF4_TU, 0x3 }, // 5
{ PseudoVAADDU_VV_MF8_MASK, PseudoVAADDU_VV_MF8, PseudoVAADDU_VV_MF8_TU, 0x3 }, // 6
{ PseudoVAADDU_VX_M1_MASK, PseudoVAADDU_VX_M1, PseudoVAADDU_VX_M1_TU, 0x3 }, // 7
{ PseudoVAADDU_VX_M2_MASK, PseudoVAADDU_VX_M2, PseudoVAADDU_VX_M2_TU, 0x3 }, // 8
{ PseudoVAADDU_VX_M4_MASK, PseudoVAADDU_VX_M4, PseudoVAADDU_VX_M4_TU, 0x3 }, // 9
{ PseudoVAADDU_VX_M8_MASK, PseudoVAADDU_VX_M8, PseudoVAADDU_VX_M8_TU, 0x3 }, // 10
{ PseudoVAADDU_VX_MF2_MASK, PseudoVAADDU_VX_MF2, PseudoVAADDU_VX_MF2_TU, 0x3 }, // 11
{ PseudoVAADDU_VX_MF4_MASK, PseudoVAADDU_VX_MF4, PseudoVAADDU_VX_MF4_TU, 0x3 }, // 12
{ PseudoVAADDU_VX_MF8_MASK, PseudoVAADDU_VX_MF8, PseudoVAADDU_VX_MF8_TU, 0x3 }, // 13
{ PseudoVAADD_VV_M1_MASK, PseudoVAADD_VV_M1, PseudoVAADD_VV_M1_TU, 0x3 }, // 14
{ PseudoVAADD_VV_M2_MASK, PseudoVAADD_VV_M2, PseudoVAADD_VV_M2_TU, 0x3 }, // 15
{ PseudoVAADD_VV_M4_MASK, PseudoVAADD_VV_M4, PseudoVAADD_VV_M4_TU, 0x3 }, // 16
{ PseudoVAADD_VV_M8_MASK, PseudoVAADD_VV_M8, PseudoVAADD_VV_M8_TU, 0x3 }, // 17
{ PseudoVAADD_VV_MF2_MASK, PseudoVAADD_VV_MF2, PseudoVAADD_VV_MF2_TU, 0x3 }, // 18
{ PseudoVAADD_VV_MF4_MASK, PseudoVAADD_VV_MF4, PseudoVAADD_VV_MF4_TU, 0x3 }, // 19
{ PseudoVAADD_VV_MF8_MASK, PseudoVAADD_VV_MF8, PseudoVAADD_VV_MF8_TU, 0x3 }, // 20
{ PseudoVAADD_VX_M1_MASK, PseudoVAADD_VX_M1, PseudoVAADD_VX_M1_TU, 0x3 }, // 21
{ PseudoVAADD_VX_M2_MASK, PseudoVAADD_VX_M2, PseudoVAADD_VX_M2_TU, 0x3 }, // 22
{ PseudoVAADD_VX_M4_MASK, PseudoVAADD_VX_M4, PseudoVAADD_VX_M4_TU, 0x3 }, // 23
{ PseudoVAADD_VX_M8_MASK, PseudoVAADD_VX_M8, PseudoVAADD_VX_M8_TU, 0x3 }, // 24
{ PseudoVAADD_VX_MF2_MASK, PseudoVAADD_VX_MF2, PseudoVAADD_VX_MF2_TU, 0x3 }, // 25
{ PseudoVAADD_VX_MF4_MASK, PseudoVAADD_VX_MF4, PseudoVAADD_VX_MF4_TU, 0x3 }, // 26
{ PseudoVAADD_VX_MF8_MASK, PseudoVAADD_VX_MF8, PseudoVAADD_VX_MF8_TU, 0x3 }, // 27
{ PseudoVADD_VI_M1_MASK, PseudoVADD_VI_M1, PseudoVADD_VI_M1_TU, 0x3 }, // 28
{ PseudoVADD_VI_M2_MASK, PseudoVADD_VI_M2, PseudoVADD_VI_M2_TU, 0x3 }, // 29
{ PseudoVADD_VI_M4_MASK, PseudoVADD_VI_M4, PseudoVADD_VI_M4_TU, 0x3 }, // 30
{ PseudoVADD_VI_M8_MASK, PseudoVADD_VI_M8, PseudoVADD_VI_M8_TU, 0x3 }, // 31
{ PseudoVADD_VI_MF2_MASK, PseudoVADD_VI_MF2, PseudoVADD_VI_MF2_TU, 0x3 }, // 32
{ PseudoVADD_VI_MF4_MASK, PseudoVADD_VI_MF4, PseudoVADD_VI_MF4_TU, 0x3 }, // 33
{ PseudoVADD_VI_MF8_MASK, PseudoVADD_VI_MF8, PseudoVADD_VI_MF8_TU, 0x3 }, // 34
{ PseudoVADD_VV_M1_MASK, PseudoVADD_VV_M1, PseudoVADD_VV_M1_TU, 0x3 }, // 35
{ PseudoVADD_VV_M2_MASK, PseudoVADD_VV_M2, PseudoVADD_VV_M2_TU, 0x3 }, // 36
{ PseudoVADD_VV_M4_MASK, PseudoVADD_VV_M4, PseudoVADD_VV_M4_TU, 0x3 }, // 37
{ PseudoVADD_VV_M8_MASK, PseudoVADD_VV_M8, PseudoVADD_VV_M8_TU, 0x3 }, // 38
{ PseudoVADD_VV_MF2_MASK, PseudoVADD_VV_MF2, PseudoVADD_VV_MF2_TU, 0x3 }, // 39
{ PseudoVADD_VV_MF4_MASK, PseudoVADD_VV_MF4, PseudoVADD_VV_MF4_TU, 0x3 }, // 40
{ PseudoVADD_VV_MF8_MASK, PseudoVADD_VV_MF8, PseudoVADD_VV_MF8_TU, 0x3 }, // 41
{ PseudoVADD_VX_M1_MASK, PseudoVADD_VX_M1, PseudoVADD_VX_M1_TU, 0x3 }, // 42
{ PseudoVADD_VX_M2_MASK, PseudoVADD_VX_M2, PseudoVADD_VX_M2_TU, 0x3 }, // 43
{ PseudoVADD_VX_M4_MASK, PseudoVADD_VX_M4, PseudoVADD_VX_M4_TU, 0x3 }, // 44
{ PseudoVADD_VX_M8_MASK, PseudoVADD_VX_M8, PseudoVADD_VX_M8_TU, 0x3 }, // 45
{ PseudoVADD_VX_MF2_MASK, PseudoVADD_VX_MF2, PseudoVADD_VX_MF2_TU, 0x3 }, // 46
{ PseudoVADD_VX_MF4_MASK, PseudoVADD_VX_MF4, PseudoVADD_VX_MF4_TU, 0x3 }, // 47
{ PseudoVADD_VX_MF8_MASK, PseudoVADD_VX_MF8, PseudoVADD_VX_MF8_TU, 0x3 }, // 48
{ PseudoVAND_VI_M1_MASK, PseudoVAND_VI_M1, PseudoVAND_VI_M1_TU, 0x3 }, // 49
{ PseudoVAND_VI_M2_MASK, PseudoVAND_VI_M2, PseudoVAND_VI_M2_TU, 0x3 }, // 50
{ PseudoVAND_VI_M4_MASK, PseudoVAND_VI_M4, PseudoVAND_VI_M4_TU, 0x3 }, // 51
{ PseudoVAND_VI_M8_MASK, PseudoVAND_VI_M8, PseudoVAND_VI_M8_TU, 0x3 }, // 52
{ PseudoVAND_VI_MF2_MASK, PseudoVAND_VI_MF2, PseudoVAND_VI_MF2_TU, 0x3 }, // 53
{ PseudoVAND_VI_MF4_MASK, PseudoVAND_VI_MF4, PseudoVAND_VI_MF4_TU, 0x3 }, // 54
{ PseudoVAND_VI_MF8_MASK, PseudoVAND_VI_MF8, PseudoVAND_VI_MF8_TU, 0x3 }, // 55
{ PseudoVAND_VV_M1_MASK, PseudoVAND_VV_M1, PseudoVAND_VV_M1_TU, 0x3 }, // 56
{ PseudoVAND_VV_M2_MASK, PseudoVAND_VV_M2, PseudoVAND_VV_M2_TU, 0x3 }, // 57
{ PseudoVAND_VV_M4_MASK, PseudoVAND_VV_M4, PseudoVAND_VV_M4_TU, 0x3 }, // 58
{ PseudoVAND_VV_M8_MASK, PseudoVAND_VV_M8, PseudoVAND_VV_M8_TU, 0x3 }, // 59
{ PseudoVAND_VV_MF2_MASK, PseudoVAND_VV_MF2, PseudoVAND_VV_MF2_TU, 0x3 }, // 60
{ PseudoVAND_VV_MF4_MASK, PseudoVAND_VV_MF4, PseudoVAND_VV_MF4_TU, 0x3 }, // 61
{ PseudoVAND_VV_MF8_MASK, PseudoVAND_VV_MF8, PseudoVAND_VV_MF8_TU, 0x3 }, // 62
{ PseudoVAND_VX_M1_MASK, PseudoVAND_VX_M1, PseudoVAND_VX_M1_TU, 0x3 }, // 63
{ PseudoVAND_VX_M2_MASK, PseudoVAND_VX_M2, PseudoVAND_VX_M2_TU, 0x3 }, // 64
{ PseudoVAND_VX_M4_MASK, PseudoVAND_VX_M4, PseudoVAND_VX_M4_TU, 0x3 }, // 65
{ PseudoVAND_VX_M8_MASK, PseudoVAND_VX_M8, PseudoVAND_VX_M8_TU, 0x3 }, // 66
{ PseudoVAND_VX_MF2_MASK, PseudoVAND_VX_MF2, PseudoVAND_VX_MF2_TU, 0x3 }, // 67
{ PseudoVAND_VX_MF4_MASK, PseudoVAND_VX_MF4, PseudoVAND_VX_MF4_TU, 0x3 }, // 68
{ PseudoVAND_VX_MF8_MASK, PseudoVAND_VX_MF8, PseudoVAND_VX_MF8_TU, 0x3 }, // 69
{ PseudoVASUBU_VV_M1_MASK, PseudoVASUBU_VV_M1, PseudoVASUBU_VV_M1_TU, 0x3 }, // 70
{ PseudoVASUBU_VV_M2_MASK, PseudoVASUBU_VV_M2, PseudoVASUBU_VV_M2_TU, 0x3 }, // 71
{ PseudoVASUBU_VV_M4_MASK, PseudoVASUBU_VV_M4, PseudoVASUBU_VV_M4_TU, 0x3 }, // 72
{ PseudoVASUBU_VV_M8_MASK, PseudoVASUBU_VV_M8, PseudoVASUBU_VV_M8_TU, 0x3 }, // 73
{ PseudoVASUBU_VV_MF2_MASK, PseudoVASUBU_VV_MF2, PseudoVASUBU_VV_MF2_TU, 0x3 }, // 74
{ PseudoVASUBU_VV_MF4_MASK, PseudoVASUBU_VV_MF4, PseudoVASUBU_VV_MF4_TU, 0x3 }, // 75
{ PseudoVASUBU_VV_MF8_MASK, PseudoVASUBU_VV_MF8, PseudoVASUBU_VV_MF8_TU, 0x3 }, // 76
{ PseudoVASUBU_VX_M1_MASK, PseudoVASUBU_VX_M1, PseudoVASUBU_VX_M1_TU, 0x3 }, // 77
{ PseudoVASUBU_VX_M2_MASK, PseudoVASUBU_VX_M2, PseudoVASUBU_VX_M2_TU, 0x3 }, // 78
{ PseudoVASUBU_VX_M4_MASK, PseudoVASUBU_VX_M4, PseudoVASUBU_VX_M4_TU, 0x3 }, // 79
{ PseudoVASUBU_VX_M8_MASK, PseudoVASUBU_VX_M8, PseudoVASUBU_VX_M8_TU, 0x3 }, // 80
{ PseudoVASUBU_VX_MF2_MASK, PseudoVASUBU_VX_MF2, PseudoVASUBU_VX_MF2_TU, 0x3 }, // 81
{ PseudoVASUBU_VX_MF4_MASK, PseudoVASUBU_VX_MF4, PseudoVASUBU_VX_MF4_TU, 0x3 }, // 82
{ PseudoVASUBU_VX_MF8_MASK, PseudoVASUBU_VX_MF8, PseudoVASUBU_VX_MF8_TU, 0x3 }, // 83
{ PseudoVASUB_VV_M1_MASK, PseudoVASUB_VV_M1, PseudoVASUB_VV_M1_TU, 0x3 }, // 84
{ PseudoVASUB_VV_M2_MASK, PseudoVASUB_VV_M2, PseudoVASUB_VV_M2_TU, 0x3 }, // 85
{ PseudoVASUB_VV_M4_MASK, PseudoVASUB_VV_M4, PseudoVASUB_VV_M4_TU, 0x3 }, // 86
{ PseudoVASUB_VV_M8_MASK, PseudoVASUB_VV_M8, PseudoVASUB_VV_M8_TU, 0x3 }, // 87
{ PseudoVASUB_VV_MF2_MASK, PseudoVASUB_VV_MF2, PseudoVASUB_VV_MF2_TU, 0x3 }, // 88
{ PseudoVASUB_VV_MF4_MASK, PseudoVASUB_VV_MF4, PseudoVASUB_VV_MF4_TU, 0x3 }, // 89
{ PseudoVASUB_VV_MF8_MASK, PseudoVASUB_VV_MF8, PseudoVASUB_VV_MF8_TU, 0x3 }, // 90
{ PseudoVASUB_VX_M1_MASK, PseudoVASUB_VX_M1, PseudoVASUB_VX_M1_TU, 0x3 }, // 91
{ PseudoVASUB_VX_M2_MASK, PseudoVASUB_VX_M2, PseudoVASUB_VX_M2_TU, 0x3 }, // 92
{ PseudoVASUB_VX_M4_MASK, PseudoVASUB_VX_M4, PseudoVASUB_VX_M4_TU, 0x3 }, // 93
{ PseudoVASUB_VX_M8_MASK, PseudoVASUB_VX_M8, PseudoVASUB_VX_M8_TU, 0x3 }, // 94
{ PseudoVASUB_VX_MF2_MASK, PseudoVASUB_VX_MF2, PseudoVASUB_VX_MF2_TU, 0x3 }, // 95
{ PseudoVASUB_VX_MF4_MASK, PseudoVASUB_VX_MF4, PseudoVASUB_VX_MF4_TU, 0x3 }, // 96
{ PseudoVASUB_VX_MF8_MASK, PseudoVASUB_VX_MF8, PseudoVASUB_VX_MF8_TU, 0x3 }, // 97
{ PseudoVDIVU_VV_M1_MASK, PseudoVDIVU_VV_M1, PseudoVDIVU_VV_M1_TU, 0x3 }, // 98
{ PseudoVDIVU_VV_M2_MASK, PseudoVDIVU_VV_M2, PseudoVDIVU_VV_M2_TU, 0x3 }, // 99
{ PseudoVDIVU_VV_M4_MASK, PseudoVDIVU_VV_M4, PseudoVDIVU_VV_M4_TU, 0x3 }, // 100
{ PseudoVDIVU_VV_M8_MASK, PseudoVDIVU_VV_M8, PseudoVDIVU_VV_M8_TU, 0x3 }, // 101
{ PseudoVDIVU_VV_MF2_MASK, PseudoVDIVU_VV_MF2, PseudoVDIVU_VV_MF2_TU, 0x3 }, // 102
{ PseudoVDIVU_VV_MF4_MASK, PseudoVDIVU_VV_MF4, PseudoVDIVU_VV_MF4_TU, 0x3 }, // 103
{ PseudoVDIVU_VV_MF8_MASK, PseudoVDIVU_VV_MF8, PseudoVDIVU_VV_MF8_TU, 0x3 }, // 104
{ PseudoVDIVU_VX_M1_MASK, PseudoVDIVU_VX_M1, PseudoVDIVU_VX_M1_TU, 0x3 }, // 105
{ PseudoVDIVU_VX_M2_MASK, PseudoVDIVU_VX_M2, PseudoVDIVU_VX_M2_TU, 0x3 }, // 106
{ PseudoVDIVU_VX_M4_MASK, PseudoVDIVU_VX_M4, PseudoVDIVU_VX_M4_TU, 0x3 }, // 107
{ PseudoVDIVU_VX_M8_MASK, PseudoVDIVU_VX_M8, PseudoVDIVU_VX_M8_TU, 0x3 }, // 108
{ PseudoVDIVU_VX_MF2_MASK, PseudoVDIVU_VX_MF2, PseudoVDIVU_VX_MF2_TU, 0x3 }, // 109
{ PseudoVDIVU_VX_MF4_MASK, PseudoVDIVU_VX_MF4, PseudoVDIVU_VX_MF4_TU, 0x3 }, // 110
{ PseudoVDIVU_VX_MF8_MASK, PseudoVDIVU_VX_MF8, PseudoVDIVU_VX_MF8_TU, 0x3 }, // 111
{ PseudoVDIV_VV_M1_MASK, PseudoVDIV_VV_M1, PseudoVDIV_VV_M1_TU, 0x3 }, // 112
{ PseudoVDIV_VV_M2_MASK, PseudoVDIV_VV_M2, PseudoVDIV_VV_M2_TU, 0x3 }, // 113
{ PseudoVDIV_VV_M4_MASK, PseudoVDIV_VV_M4, PseudoVDIV_VV_M4_TU, 0x3 }, // 114
{ PseudoVDIV_VV_M8_MASK, PseudoVDIV_VV_M8, PseudoVDIV_VV_M8_TU, 0x3 }, // 115
{ PseudoVDIV_VV_MF2_MASK, PseudoVDIV_VV_MF2, PseudoVDIV_VV_MF2_TU, 0x3 }, // 116
{ PseudoVDIV_VV_MF4_MASK, PseudoVDIV_VV_MF4, PseudoVDIV_VV_MF4_TU, 0x3 }, // 117
{ PseudoVDIV_VV_MF8_MASK, PseudoVDIV_VV_MF8, PseudoVDIV_VV_MF8_TU, 0x3 }, // 118
{ PseudoVDIV_VX_M1_MASK, PseudoVDIV_VX_M1, PseudoVDIV_VX_M1_TU, 0x3 }, // 119
{ PseudoVDIV_VX_M2_MASK, PseudoVDIV_VX_M2, PseudoVDIV_VX_M2_TU, 0x3 }, // 120
{ PseudoVDIV_VX_M4_MASK, PseudoVDIV_VX_M4, PseudoVDIV_VX_M4_TU, 0x3 }, // 121
{ PseudoVDIV_VX_M8_MASK, PseudoVDIV_VX_M8, PseudoVDIV_VX_M8_TU, 0x3 }, // 122
{ PseudoVDIV_VX_MF2_MASK, PseudoVDIV_VX_MF2, PseudoVDIV_VX_MF2_TU, 0x3 }, // 123
{ PseudoVDIV_VX_MF4_MASK, PseudoVDIV_VX_MF4, PseudoVDIV_VX_MF4_TU, 0x3 }, // 124
{ PseudoVDIV_VX_MF8_MASK, PseudoVDIV_VX_MF8, PseudoVDIV_VX_MF8_TU, 0x3 }, // 125
{ PseudoVFADD_VF16_M1_MASK, PseudoVFADD_VF16_M1, PseudoVFADD_VF16_M1_TU, 0x3 }, // 126
{ PseudoVFADD_VF16_M2_MASK, PseudoVFADD_VF16_M2, PseudoVFADD_VF16_M2_TU, 0x3 }, // 127
{ PseudoVFADD_VF16_M4_MASK, PseudoVFADD_VF16_M4, PseudoVFADD_VF16_M4_TU, 0x3 }, // 128
{ PseudoVFADD_VF16_M8_MASK, PseudoVFADD_VF16_M8, PseudoVFADD_VF16_M8_TU, 0x3 }, // 129
{ PseudoVFADD_VF16_MF2_MASK, PseudoVFADD_VF16_MF2, PseudoVFADD_VF16_MF2_TU, 0x3 }, // 130
{ PseudoVFADD_VF16_MF4_MASK, PseudoVFADD_VF16_MF4, PseudoVFADD_VF16_MF4_TU, 0x3 }, // 131
{ PseudoVFADD_VF32_M1_MASK, PseudoVFADD_VF32_M1, PseudoVFADD_VF32_M1_TU, 0x3 }, // 132
{ PseudoVFADD_VF32_M2_MASK, PseudoVFADD_VF32_M2, PseudoVFADD_VF32_M2_TU, 0x3 }, // 133
{ PseudoVFADD_VF32_M4_MASK, PseudoVFADD_VF32_M4, PseudoVFADD_VF32_M4_TU, 0x3 }, // 134
{ PseudoVFADD_VF32_M8_MASK, PseudoVFADD_VF32_M8, PseudoVFADD_VF32_M8_TU, 0x3 }, // 135
{ PseudoVFADD_VF32_MF2_MASK, PseudoVFADD_VF32_MF2, PseudoVFADD_VF32_MF2_TU, 0x3 }, // 136
{ PseudoVFADD_VF64_M1_MASK, PseudoVFADD_VF64_M1, PseudoVFADD_VF64_M1_TU, 0x3 }, // 137
{ PseudoVFADD_VF64_M2_MASK, PseudoVFADD_VF64_M2, PseudoVFADD_VF64_M2_TU, 0x3 }, // 138
{ PseudoVFADD_VF64_M4_MASK, PseudoVFADD_VF64_M4, PseudoVFADD_VF64_M4_TU, 0x3 }, // 139
{ PseudoVFADD_VF64_M8_MASK, PseudoVFADD_VF64_M8, PseudoVFADD_VF64_M8_TU, 0x3 }, // 140
{ PseudoVFADD_VV_M1_MASK, PseudoVFADD_VV_M1, PseudoVFADD_VV_M1_TU, 0x3 }, // 141
{ PseudoVFADD_VV_M2_MASK, PseudoVFADD_VV_M2, PseudoVFADD_VV_M2_TU, 0x3 }, // 142
{ PseudoVFADD_VV_M4_MASK, PseudoVFADD_VV_M4, PseudoVFADD_VV_M4_TU, 0x3 }, // 143
{ PseudoVFADD_VV_M8_MASK, PseudoVFADD_VV_M8, PseudoVFADD_VV_M8_TU, 0x3 }, // 144
{ PseudoVFADD_VV_MF2_MASK, PseudoVFADD_VV_MF2, PseudoVFADD_VV_MF2_TU, 0x3 }, // 145
{ PseudoVFADD_VV_MF4_MASK, PseudoVFADD_VV_MF4, PseudoVFADD_VV_MF4_TU, 0x3 }, // 146
{ PseudoVFCLASS_V_M1_MASK, PseudoVFCLASS_V_M1, PseudoVFCLASS_V_M1_TU, 0x2 }, // 147
{ PseudoVFCLASS_V_M2_MASK, PseudoVFCLASS_V_M2, PseudoVFCLASS_V_M2_TU, 0x2 }, // 148
{ PseudoVFCLASS_V_M4_MASK, PseudoVFCLASS_V_M4, PseudoVFCLASS_V_M4_TU, 0x2 }, // 149
{ PseudoVFCLASS_V_M8_MASK, PseudoVFCLASS_V_M8, PseudoVFCLASS_V_M8_TU, 0x2 }, // 150
{ PseudoVFCLASS_V_MF2_MASK, PseudoVFCLASS_V_MF2, PseudoVFCLASS_V_MF2_TU, 0x2 }, // 151
{ PseudoVFCLASS_V_MF4_MASK, PseudoVFCLASS_V_MF4, PseudoVFCLASS_V_MF4_TU, 0x2 }, // 152
{ PseudoVFCVT_F_XU_V_M1_MASK, PseudoVFCVT_F_XU_V_M1, PseudoVFCVT_F_XU_V_M1_TU, 0x2 }, // 153
{ PseudoVFCVT_F_XU_V_M2_MASK, PseudoVFCVT_F_XU_V_M2, PseudoVFCVT_F_XU_V_M2_TU, 0x2 }, // 154
{ PseudoVFCVT_F_XU_V_M4_MASK, PseudoVFCVT_F_XU_V_M4, PseudoVFCVT_F_XU_V_M4_TU, 0x2 }, // 155
{ PseudoVFCVT_F_XU_V_M8_MASK, PseudoVFCVT_F_XU_V_M8, PseudoVFCVT_F_XU_V_M8_TU, 0x2 }, // 156
{ PseudoVFCVT_F_XU_V_MF2_MASK, PseudoVFCVT_F_XU_V_MF2, PseudoVFCVT_F_XU_V_MF2_TU, 0x2 }, // 157
{ PseudoVFCVT_F_XU_V_MF4_MASK, PseudoVFCVT_F_XU_V_MF4, PseudoVFCVT_F_XU_V_MF4_TU, 0x2 }, // 158
{ PseudoVFCVT_F_X_V_M1_MASK, PseudoVFCVT_F_X_V_M1, PseudoVFCVT_F_X_V_M1_TU, 0x2 }, // 159
{ PseudoVFCVT_F_X_V_M2_MASK, PseudoVFCVT_F_X_V_M2, PseudoVFCVT_F_X_V_M2_TU, 0x2 }, // 160
{ PseudoVFCVT_F_X_V_M4_MASK, PseudoVFCVT_F_X_V_M4, PseudoVFCVT_F_X_V_M4_TU, 0x2 }, // 161
{ PseudoVFCVT_F_X_V_M8_MASK, PseudoVFCVT_F_X_V_M8, PseudoVFCVT_F_X_V_M8_TU, 0x2 }, // 162
{ PseudoVFCVT_F_X_V_MF2_MASK, PseudoVFCVT_F_X_V_MF2, PseudoVFCVT_F_X_V_MF2_TU, 0x2 }, // 163
{ PseudoVFCVT_F_X_V_MF4_MASK, PseudoVFCVT_F_X_V_MF4, PseudoVFCVT_F_X_V_MF4_TU, 0x2 }, // 164
{ PseudoVFCVT_RTZ_XU_F_V_M1_MASK, PseudoVFCVT_RTZ_XU_F_V_M1, PseudoVFCVT_RTZ_XU_F_V_M1_TU, 0x2 }, // 165
{ PseudoVFCVT_RTZ_XU_F_V_M2_MASK, PseudoVFCVT_RTZ_XU_F_V_M2, PseudoVFCVT_RTZ_XU_F_V_M2_TU, 0x2 }, // 166
{ PseudoVFCVT_RTZ_XU_F_V_M4_MASK, PseudoVFCVT_RTZ_XU_F_V_M4, PseudoVFCVT_RTZ_XU_F_V_M4_TU, 0x2 }, // 167
{ PseudoVFCVT_RTZ_XU_F_V_M8_MASK, PseudoVFCVT_RTZ_XU_F_V_M8, PseudoVFCVT_RTZ_XU_F_V_M8_TU, 0x2 }, // 168
{ PseudoVFCVT_RTZ_XU_F_V_MF2_MASK, PseudoVFCVT_RTZ_XU_F_V_MF2, PseudoVFCVT_RTZ_XU_F_V_MF2_TU, 0x2 }, // 169
{ PseudoVFCVT_RTZ_XU_F_V_MF4_MASK, PseudoVFCVT_RTZ_XU_F_V_MF4, PseudoVFCVT_RTZ_XU_F_V_MF4_TU, 0x2 }, // 170
{ PseudoVFCVT_RTZ_X_F_V_M1_MASK, PseudoVFCVT_RTZ_X_F_V_M1, PseudoVFCVT_RTZ_X_F_V_M1_TU, 0x2 }, // 171
{ PseudoVFCVT_RTZ_X_F_V_M2_MASK, PseudoVFCVT_RTZ_X_F_V_M2, PseudoVFCVT_RTZ_X_F_V_M2_TU, 0x2 }, // 172
{ PseudoVFCVT_RTZ_X_F_V_M4_MASK, PseudoVFCVT_RTZ_X_F_V_M4, PseudoVFCVT_RTZ_X_F_V_M4_TU, 0x2 }, // 173
{ PseudoVFCVT_RTZ_X_F_V_M8_MASK, PseudoVFCVT_RTZ_X_F_V_M8, PseudoVFCVT_RTZ_X_F_V_M8_TU, 0x2 }, // 174
{ PseudoVFCVT_RTZ_X_F_V_MF2_MASK, PseudoVFCVT_RTZ_X_F_V_MF2, PseudoVFCVT_RTZ_X_F_V_MF2_TU, 0x2 }, // 175
{ PseudoVFCVT_RTZ_X_F_V_MF4_MASK, PseudoVFCVT_RTZ_X_F_V_MF4, PseudoVFCVT_RTZ_X_F_V_MF4_TU, 0x2 }, // 176
{ PseudoVFCVT_XU_F_V_M1_MASK, PseudoVFCVT_XU_F_V_M1, PseudoVFCVT_XU_F_V_M1_TU, 0x2 }, // 177
{ PseudoVFCVT_XU_F_V_M2_MASK, PseudoVFCVT_XU_F_V_M2, PseudoVFCVT_XU_F_V_M2_TU, 0x2 }, // 178
{ PseudoVFCVT_XU_F_V_M4_MASK, PseudoVFCVT_XU_F_V_M4, PseudoVFCVT_XU_F_V_M4_TU, 0x2 }, // 179
{ PseudoVFCVT_XU_F_V_M8_MASK, PseudoVFCVT_XU_F_V_M8, PseudoVFCVT_XU_F_V_M8_TU, 0x2 }, // 180
{ PseudoVFCVT_XU_F_V_MF2_MASK, PseudoVFCVT_XU_F_V_MF2, PseudoVFCVT_XU_F_V_MF2_TU, 0x2 }, // 181
{ PseudoVFCVT_XU_F_V_MF4_MASK, PseudoVFCVT_XU_F_V_MF4, PseudoVFCVT_XU_F_V_MF4_TU, 0x2 }, // 182
{ PseudoVFCVT_X_F_V_M1_MASK, PseudoVFCVT_X_F_V_M1, PseudoVFCVT_X_F_V_M1_TU, 0x2 }, // 183
{ PseudoVFCVT_X_F_V_M2_MASK, PseudoVFCVT_X_F_V_M2, PseudoVFCVT_X_F_V_M2_TU, 0x2 }, // 184
{ PseudoVFCVT_X_F_V_M4_MASK, PseudoVFCVT_X_F_V_M4, PseudoVFCVT_X_F_V_M4_TU, 0x2 }, // 185
{ PseudoVFCVT_X_F_V_M8_MASK, PseudoVFCVT_X_F_V_M8, PseudoVFCVT_X_F_V_M8_TU, 0x2 }, // 186
{ PseudoVFCVT_X_F_V_MF2_MASK, PseudoVFCVT_X_F_V_MF2, PseudoVFCVT_X_F_V_MF2_TU, 0x2 }, // 187
{ PseudoVFCVT_X_F_V_MF4_MASK, PseudoVFCVT_X_F_V_MF4, PseudoVFCVT_X_F_V_MF4_TU, 0x2 }, // 188
{ PseudoVFDIV_VF16_M1_MASK, PseudoVFDIV_VF16_M1, PseudoVFDIV_VF16_M1_TU, 0x3 }, // 189
{ PseudoVFDIV_VF16_M2_MASK, PseudoVFDIV_VF16_M2, PseudoVFDIV_VF16_M2_TU, 0x3 }, // 190
{ PseudoVFDIV_VF16_M4_MASK, PseudoVFDIV_VF16_M4, PseudoVFDIV_VF16_M4_TU, 0x3 }, // 191
{ PseudoVFDIV_VF16_M8_MASK, PseudoVFDIV_VF16_M8, PseudoVFDIV_VF16_M8_TU, 0x3 }, // 192
{ PseudoVFDIV_VF16_MF2_MASK, PseudoVFDIV_VF16_MF2, PseudoVFDIV_VF16_MF2_TU, 0x3 }, // 193
{ PseudoVFDIV_VF16_MF4_MASK, PseudoVFDIV_VF16_MF4, PseudoVFDIV_VF16_MF4_TU, 0x3 }, // 194
{ PseudoVFDIV_VF32_M1_MASK, PseudoVFDIV_VF32_M1, PseudoVFDIV_VF32_M1_TU, 0x3 }, // 195
{ PseudoVFDIV_VF32_M2_MASK, PseudoVFDIV_VF32_M2, PseudoVFDIV_VF32_M2_TU, 0x3 }, // 196
{ PseudoVFDIV_VF32_M4_MASK, PseudoVFDIV_VF32_M4, PseudoVFDIV_VF32_M4_TU, 0x3 }, // 197
{ PseudoVFDIV_VF32_M8_MASK, PseudoVFDIV_VF32_M8, PseudoVFDIV_VF32_M8_TU, 0x3 }, // 198
{ PseudoVFDIV_VF32_MF2_MASK, PseudoVFDIV_VF32_MF2, PseudoVFDIV_VF32_MF2_TU, 0x3 }, // 199
{ PseudoVFDIV_VF64_M1_MASK, PseudoVFDIV_VF64_M1, PseudoVFDIV_VF64_M1_TU, 0x3 }, // 200
{ PseudoVFDIV_VF64_M2_MASK, PseudoVFDIV_VF64_M2, PseudoVFDIV_VF64_M2_TU, 0x3 }, // 201
{ PseudoVFDIV_VF64_M4_MASK, PseudoVFDIV_VF64_M4, PseudoVFDIV_VF64_M4_TU, 0x3 }, // 202
{ PseudoVFDIV_VF64_M8_MASK, PseudoVFDIV_VF64_M8, PseudoVFDIV_VF64_M8_TU, 0x3 }, // 203
{ PseudoVFDIV_VV_M1_MASK, PseudoVFDIV_VV_M1, PseudoVFDIV_VV_M1_TU, 0x3 }, // 204
{ PseudoVFDIV_VV_M2_MASK, PseudoVFDIV_VV_M2, PseudoVFDIV_VV_M2_TU, 0x3 }, // 205
{ PseudoVFDIV_VV_M4_MASK, PseudoVFDIV_VV_M4, PseudoVFDIV_VV_M4_TU, 0x3 }, // 206
{ PseudoVFDIV_VV_M8_MASK, PseudoVFDIV_VV_M8, PseudoVFDIV_VV_M8_TU, 0x3 }, // 207
{ PseudoVFDIV_VV_MF2_MASK, PseudoVFDIV_VV_MF2, PseudoVFDIV_VV_MF2_TU, 0x3 }, // 208
{ PseudoVFDIV_VV_MF4_MASK, PseudoVFDIV_VV_MF4, PseudoVFDIV_VV_MF4_TU, 0x3 }, // 209
{ PseudoVFMAX_VF16_M1_MASK, PseudoVFMAX_VF16_M1, PseudoVFMAX_VF16_M1_TU, 0x3 }, // 210
{ PseudoVFMAX_VF16_M2_MASK, PseudoVFMAX_VF16_M2, PseudoVFMAX_VF16_M2_TU, 0x3 }, // 211
{ PseudoVFMAX_VF16_M4_MASK, PseudoVFMAX_VF16_M4, PseudoVFMAX_VF16_M4_TU, 0x3 }, // 212
{ PseudoVFMAX_VF16_M8_MASK, PseudoVFMAX_VF16_M8, PseudoVFMAX_VF16_M8_TU, 0x3 }, // 213
{ PseudoVFMAX_VF16_MF2_MASK, PseudoVFMAX_VF16_MF2, PseudoVFMAX_VF16_MF2_TU, 0x3 }, // 214
{ PseudoVFMAX_VF16_MF4_MASK, PseudoVFMAX_VF16_MF4, PseudoVFMAX_VF16_MF4_TU, 0x3 }, // 215
{ PseudoVFMAX_VF32_M1_MASK, PseudoVFMAX_VF32_M1, PseudoVFMAX_VF32_M1_TU, 0x3 }, // 216
{ PseudoVFMAX_VF32_M2_MASK, PseudoVFMAX_VF32_M2, PseudoVFMAX_VF32_M2_TU, 0x3 }, // 217
{ PseudoVFMAX_VF32_M4_MASK, PseudoVFMAX_VF32_M4, PseudoVFMAX_VF32_M4_TU, 0x3 }, // 218
{ PseudoVFMAX_VF32_M8_MASK, PseudoVFMAX_VF32_M8, PseudoVFMAX_VF32_M8_TU, 0x3 }, // 219
{ PseudoVFMAX_VF32_MF2_MASK, PseudoVFMAX_VF32_MF2, PseudoVFMAX_VF32_MF2_TU, 0x3 }, // 220
{ PseudoVFMAX_VF64_M1_MASK, PseudoVFMAX_VF64_M1, PseudoVFMAX_VF64_M1_TU, 0x3 }, // 221
{ PseudoVFMAX_VF64_M2_MASK, PseudoVFMAX_VF64_M2, PseudoVFMAX_VF64_M2_TU, 0x3 }, // 222
{ PseudoVFMAX_VF64_M4_MASK, PseudoVFMAX_VF64_M4, PseudoVFMAX_VF64_M4_TU, 0x3 }, // 223
{ PseudoVFMAX_VF64_M8_MASK, PseudoVFMAX_VF64_M8, PseudoVFMAX_VF64_M8_TU, 0x3 }, // 224
{ PseudoVFMAX_VV_M1_MASK, PseudoVFMAX_VV_M1, PseudoVFMAX_VV_M1_TU, 0x3 }, // 225
{ PseudoVFMAX_VV_M2_MASK, PseudoVFMAX_VV_M2, PseudoVFMAX_VV_M2_TU, 0x3 }, // 226
{ PseudoVFMAX_VV_M4_MASK, PseudoVFMAX_VV_M4, PseudoVFMAX_VV_M4_TU, 0x3 }, // 227
{ PseudoVFMAX_VV_M8_MASK, PseudoVFMAX_VV_M8, PseudoVFMAX_VV_M8_TU, 0x3 }, // 228
{ PseudoVFMAX_VV_MF2_MASK, PseudoVFMAX_VV_MF2, PseudoVFMAX_VV_MF2_TU, 0x3 }, // 229
{ PseudoVFMAX_VV_MF4_MASK, PseudoVFMAX_VV_MF4, PseudoVFMAX_VV_MF4_TU, 0x3 }, // 230
{ PseudoVFMIN_VF16_M1_MASK, PseudoVFMIN_VF16_M1, PseudoVFMIN_VF16_M1_TU, 0x3 }, // 231
{ PseudoVFMIN_VF16_M2_MASK, PseudoVFMIN_VF16_M2, PseudoVFMIN_VF16_M2_TU, 0x3 }, // 232
{ PseudoVFMIN_VF16_M4_MASK, PseudoVFMIN_VF16_M4, PseudoVFMIN_VF16_M4_TU, 0x3 }, // 233
{ PseudoVFMIN_VF16_M8_MASK, PseudoVFMIN_VF16_M8, PseudoVFMIN_VF16_M8_TU, 0x3 }, // 234
{ PseudoVFMIN_VF16_MF2_MASK, PseudoVFMIN_VF16_MF2, PseudoVFMIN_VF16_MF2_TU, 0x3 }, // 235
{ PseudoVFMIN_VF16_MF4_MASK, PseudoVFMIN_VF16_MF4, PseudoVFMIN_VF16_MF4_TU, 0x3 }, // 236
{ PseudoVFMIN_VF32_M1_MASK, PseudoVFMIN_VF32_M1, PseudoVFMIN_VF32_M1_TU, 0x3 }, // 237
{ PseudoVFMIN_VF32_M2_MASK, PseudoVFMIN_VF32_M2, PseudoVFMIN_VF32_M2_TU, 0x3 }, // 238
{ PseudoVFMIN_VF32_M4_MASK, PseudoVFMIN_VF32_M4, PseudoVFMIN_VF32_M4_TU, 0x3 }, // 239
{ PseudoVFMIN_VF32_M8_MASK, PseudoVFMIN_VF32_M8, PseudoVFMIN_VF32_M8_TU, 0x3 }, // 240
{ PseudoVFMIN_VF32_MF2_MASK, PseudoVFMIN_VF32_MF2, PseudoVFMIN_VF32_MF2_TU, 0x3 }, // 241
{ PseudoVFMIN_VF64_M1_MASK, PseudoVFMIN_VF64_M1, PseudoVFMIN_VF64_M1_TU, 0x3 }, // 242
{ PseudoVFMIN_VF64_M2_MASK, PseudoVFMIN_VF64_M2, PseudoVFMIN_VF64_M2_TU, 0x3 }, // 243
{ PseudoVFMIN_VF64_M4_MASK, PseudoVFMIN_VF64_M4, PseudoVFMIN_VF64_M4_TU, 0x3 }, // 244
{ PseudoVFMIN_VF64_M8_MASK, PseudoVFMIN_VF64_M8, PseudoVFMIN_VF64_M8_TU, 0x3 }, // 245
{ PseudoVFMIN_VV_M1_MASK, PseudoVFMIN_VV_M1, PseudoVFMIN_VV_M1_TU, 0x3 }, // 246
{ PseudoVFMIN_VV_M2_MASK, PseudoVFMIN_VV_M2, PseudoVFMIN_VV_M2_TU, 0x3 }, // 247
{ PseudoVFMIN_VV_M4_MASK, PseudoVFMIN_VV_M4, PseudoVFMIN_VV_M4_TU, 0x3 }, // 248
{ PseudoVFMIN_VV_M8_MASK, PseudoVFMIN_VV_M8, PseudoVFMIN_VV_M8_TU, 0x3 }, // 249
{ PseudoVFMIN_VV_MF2_MASK, PseudoVFMIN_VV_MF2, PseudoVFMIN_VV_MF2_TU, 0x3 }, // 250
{ PseudoVFMIN_VV_MF4_MASK, PseudoVFMIN_VV_MF4, PseudoVFMIN_VV_MF4_TU, 0x3 }, // 251
{ PseudoVFMUL_VF16_M1_MASK, PseudoVFMUL_VF16_M1, PseudoVFMUL_VF16_M1_TU, 0x3 }, // 252
{ PseudoVFMUL_VF16_M2_MASK, PseudoVFMUL_VF16_M2, PseudoVFMUL_VF16_M2_TU, 0x3 }, // 253
{ PseudoVFMUL_VF16_M4_MASK, PseudoVFMUL_VF16_M4, PseudoVFMUL_VF16_M4_TU, 0x3 }, // 254
{ PseudoVFMUL_VF16_M8_MASK, PseudoVFMUL_VF16_M8, PseudoVFMUL_VF16_M8_TU, 0x3 }, // 255
{ PseudoVFMUL_VF16_MF2_MASK, PseudoVFMUL_VF16_MF2, PseudoVFMUL_VF16_MF2_TU, 0x3 }, // 256
{ PseudoVFMUL_VF16_MF4_MASK, PseudoVFMUL_VF16_MF4, PseudoVFMUL_VF16_MF4_TU, 0x3 }, // 257
{ PseudoVFMUL_VF32_M1_MASK, PseudoVFMUL_VF32_M1, PseudoVFMUL_VF32_M1_TU, 0x3 }, // 258
{ PseudoVFMUL_VF32_M2_MASK, PseudoVFMUL_VF32_M2, PseudoVFMUL_VF32_M2_TU, 0x3 }, // 259
{ PseudoVFMUL_VF32_M4_MASK, PseudoVFMUL_VF32_M4, PseudoVFMUL_VF32_M4_TU, 0x3 }, // 260
{ PseudoVFMUL_VF32_M8_MASK, PseudoVFMUL_VF32_M8, PseudoVFMUL_VF32_M8_TU, 0x3 }, // 261
{ PseudoVFMUL_VF32_MF2_MASK, PseudoVFMUL_VF32_MF2, PseudoVFMUL_VF32_MF2_TU, 0x3 }, // 262
{ PseudoVFMUL_VF64_M1_MASK, PseudoVFMUL_VF64_M1, PseudoVFMUL_VF64_M1_TU, 0x3 }, // 263
{ PseudoVFMUL_VF64_M2_MASK, PseudoVFMUL_VF64_M2, PseudoVFMUL_VF64_M2_TU, 0x3 }, // 264
{ PseudoVFMUL_VF64_M4_MASK, PseudoVFMUL_VF64_M4, PseudoVFMUL_VF64_M4_TU, 0x3 }, // 265
{ PseudoVFMUL_VF64_M8_MASK, PseudoVFMUL_VF64_M8, PseudoVFMUL_VF64_M8_TU, 0x3 }, // 266
{ PseudoVFMUL_VV_M1_MASK, PseudoVFMUL_VV_M1, PseudoVFMUL_VV_M1_TU, 0x3 }, // 267
{ PseudoVFMUL_VV_M2_MASK, PseudoVFMUL_VV_M2, PseudoVFMUL_VV_M2_TU, 0x3 }, // 268
{ PseudoVFMUL_VV_M4_MASK, PseudoVFMUL_VV_M4, PseudoVFMUL_VV_M4_TU, 0x3 }, // 269
{ PseudoVFMUL_VV_M8_MASK, PseudoVFMUL_VV_M8, PseudoVFMUL_VV_M8_TU, 0x3 }, // 270
{ PseudoVFMUL_VV_MF2_MASK, PseudoVFMUL_VV_MF2, PseudoVFMUL_VV_MF2_TU, 0x3 }, // 271
{ PseudoVFMUL_VV_MF4_MASK, PseudoVFMUL_VV_MF4, PseudoVFMUL_VV_MF4_TU, 0x3 }, // 272
{ PseudoVFNCVT_F_F_W_M1_MASK, PseudoVFNCVT_F_F_W_M1, PseudoVFNCVT_F_F_W_M1_TU, 0x2 }, // 273
{ PseudoVFNCVT_F_F_W_M2_MASK, PseudoVFNCVT_F_F_W_M2, PseudoVFNCVT_F_F_W_M2_TU, 0x2 }, // 274
{ PseudoVFNCVT_F_F_W_M4_MASK, PseudoVFNCVT_F_F_W_M4, PseudoVFNCVT_F_F_W_M4_TU, 0x2 }, // 275
{ PseudoVFNCVT_F_F_W_MF2_MASK, PseudoVFNCVT_F_F_W_MF2, PseudoVFNCVT_F_F_W_MF2_TU, 0x2 }, // 276
{ PseudoVFNCVT_F_F_W_MF4_MASK, PseudoVFNCVT_F_F_W_MF4, PseudoVFNCVT_F_F_W_MF4_TU, 0x2 }, // 277
{ PseudoVFNCVT_F_XU_W_M1_MASK, PseudoVFNCVT_F_XU_W_M1, PseudoVFNCVT_F_XU_W_M1_TU, 0x2 }, // 278
{ PseudoVFNCVT_F_XU_W_M2_MASK, PseudoVFNCVT_F_XU_W_M2, PseudoVFNCVT_F_XU_W_M2_TU, 0x2 }, // 279
{ PseudoVFNCVT_F_XU_W_M4_MASK, PseudoVFNCVT_F_XU_W_M4, PseudoVFNCVT_F_XU_W_M4_TU, 0x2 }, // 280
{ PseudoVFNCVT_F_XU_W_MF2_MASK, PseudoVFNCVT_F_XU_W_MF2, PseudoVFNCVT_F_XU_W_MF2_TU, 0x2 }, // 281
{ PseudoVFNCVT_F_XU_W_MF4_MASK, PseudoVFNCVT_F_XU_W_MF4, PseudoVFNCVT_F_XU_W_MF4_TU, 0x2 }, // 282
{ PseudoVFNCVT_F_X_W_M1_MASK, PseudoVFNCVT_F_X_W_M1, PseudoVFNCVT_F_X_W_M1_TU, 0x2 }, // 283
{ PseudoVFNCVT_F_X_W_M2_MASK, PseudoVFNCVT_F_X_W_M2, PseudoVFNCVT_F_X_W_M2_TU, 0x2 }, // 284
{ PseudoVFNCVT_F_X_W_M4_MASK, PseudoVFNCVT_F_X_W_M4, PseudoVFNCVT_F_X_W_M4_TU, 0x2 }, // 285
{ PseudoVFNCVT_F_X_W_MF2_MASK, PseudoVFNCVT_F_X_W_MF2, PseudoVFNCVT_F_X_W_MF2_TU, 0x2 }, // 286
{ PseudoVFNCVT_F_X_W_MF4_MASK, PseudoVFNCVT_F_X_W_MF4, PseudoVFNCVT_F_X_W_MF4_TU, 0x2 }, // 287
{ PseudoVFNCVT_ROD_F_F_W_M1_MASK, PseudoVFNCVT_ROD_F_F_W_M1, PseudoVFNCVT_ROD_F_F_W_M1_TU, 0x2 }, // 288
{ PseudoVFNCVT_ROD_F_F_W_M2_MASK, PseudoVFNCVT_ROD_F_F_W_M2, PseudoVFNCVT_ROD_F_F_W_M2_TU, 0x2 }, // 289
{ PseudoVFNCVT_ROD_F_F_W_M4_MASK, PseudoVFNCVT_ROD_F_F_W_M4, PseudoVFNCVT_ROD_F_F_W_M4_TU, 0x2 }, // 290
{ PseudoVFNCVT_ROD_F_F_W_MF2_MASK, PseudoVFNCVT_ROD_F_F_W_MF2, PseudoVFNCVT_ROD_F_F_W_MF2_TU, 0x2 }, // 291
{ PseudoVFNCVT_ROD_F_F_W_MF4_MASK, PseudoVFNCVT_ROD_F_F_W_MF4, PseudoVFNCVT_ROD_F_F_W_MF4_TU, 0x2 }, // 292
{ PseudoVFNCVT_RTZ_XU_F_W_M1_MASK, PseudoVFNCVT_RTZ_XU_F_W_M1, PseudoVFNCVT_RTZ_XU_F_W_M1_TU, 0x2 }, // 293
{ PseudoVFNCVT_RTZ_XU_F_W_M2_MASK, PseudoVFNCVT_RTZ_XU_F_W_M2, PseudoVFNCVT_RTZ_XU_F_W_M2_TU, 0x2 }, // 294
{ PseudoVFNCVT_RTZ_XU_F_W_M4_MASK, PseudoVFNCVT_RTZ_XU_F_W_M4, PseudoVFNCVT_RTZ_XU_F_W_M4_TU, 0x2 }, // 295
{ PseudoVFNCVT_RTZ_XU_F_W_MF2_MASK, PseudoVFNCVT_RTZ_XU_F_W_MF2, PseudoVFNCVT_RTZ_XU_F_W_MF2_TU, 0x2 }, // 296
{ PseudoVFNCVT_RTZ_XU_F_W_MF4_MASK, PseudoVFNCVT_RTZ_XU_F_W_MF4, PseudoVFNCVT_RTZ_XU_F_W_MF4_TU, 0x2 }, // 297
{ PseudoVFNCVT_RTZ_XU_F_W_MF8_MASK, PseudoVFNCVT_RTZ_XU_F_W_MF8, PseudoVFNCVT_RTZ_XU_F_W_MF8_TU, 0x2 }, // 298
{ PseudoVFNCVT_RTZ_X_F_W_M1_MASK, PseudoVFNCVT_RTZ_X_F_W_M1, PseudoVFNCVT_RTZ_X_F_W_M1_TU, 0x2 }, // 299
{ PseudoVFNCVT_RTZ_X_F_W_M2_MASK, PseudoVFNCVT_RTZ_X_F_W_M2, PseudoVFNCVT_RTZ_X_F_W_M2_TU, 0x2 }, // 300
{ PseudoVFNCVT_RTZ_X_F_W_M4_MASK, PseudoVFNCVT_RTZ_X_F_W_M4, PseudoVFNCVT_RTZ_X_F_W_M4_TU, 0x2 }, // 301
{ PseudoVFNCVT_RTZ_X_F_W_MF2_MASK, PseudoVFNCVT_RTZ_X_F_W_MF2, PseudoVFNCVT_RTZ_X_F_W_MF2_TU, 0x2 }, // 302
{ PseudoVFNCVT_RTZ_X_F_W_MF4_MASK, PseudoVFNCVT_RTZ_X_F_W_MF4, PseudoVFNCVT_RTZ_X_F_W_MF4_TU, 0x2 }, // 303
{ PseudoVFNCVT_RTZ_X_F_W_MF8_MASK, PseudoVFNCVT_RTZ_X_F_W_MF8, PseudoVFNCVT_RTZ_X_F_W_MF8_TU, 0x2 }, // 304
{ PseudoVFNCVT_XU_F_W_M1_MASK, PseudoVFNCVT_XU_F_W_M1, PseudoVFNCVT_XU_F_W_M1_TU, 0x2 }, // 305
{ PseudoVFNCVT_XU_F_W_M2_MASK, PseudoVFNCVT_XU_F_W_M2, PseudoVFNCVT_XU_F_W_M2_TU, 0x2 }, // 306
{ PseudoVFNCVT_XU_F_W_M4_MASK, PseudoVFNCVT_XU_F_W_M4, PseudoVFNCVT_XU_F_W_M4_TU, 0x2 }, // 307
{ PseudoVFNCVT_XU_F_W_MF2_MASK, PseudoVFNCVT_XU_F_W_MF2, PseudoVFNCVT_XU_F_W_MF2_TU, 0x2 }, // 308
{ PseudoVFNCVT_XU_F_W_MF4_MASK, PseudoVFNCVT_XU_F_W_MF4, PseudoVFNCVT_XU_F_W_MF4_TU, 0x2 }, // 309
{ PseudoVFNCVT_XU_F_W_MF8_MASK, PseudoVFNCVT_XU_F_W_MF8, PseudoVFNCVT_XU_F_W_MF8_TU, 0x2 }, // 310
{ PseudoVFNCVT_X_F_W_M1_MASK, PseudoVFNCVT_X_F_W_M1, PseudoVFNCVT_X_F_W_M1_TU, 0x2 }, // 311
{ PseudoVFNCVT_X_F_W_M2_MASK, PseudoVFNCVT_X_F_W_M2, PseudoVFNCVT_X_F_W_M2_TU, 0x2 }, // 312
{ PseudoVFNCVT_X_F_W_M4_MASK, PseudoVFNCVT_X_F_W_M4, PseudoVFNCVT_X_F_W_M4_TU, 0x2 }, // 313
{ PseudoVFNCVT_X_F_W_MF2_MASK, PseudoVFNCVT_X_F_W_MF2, PseudoVFNCVT_X_F_W_MF2_TU, 0x2 }, // 314
{ PseudoVFNCVT_X_F_W_MF4_MASK, PseudoVFNCVT_X_F_W_MF4, PseudoVFNCVT_X_F_W_MF4_TU, 0x2 }, // 315
{ PseudoVFNCVT_X_F_W_MF8_MASK, PseudoVFNCVT_X_F_W_MF8, PseudoVFNCVT_X_F_W_MF8_TU, 0x2 }, // 316
{ PseudoVFRDIV_VF16_M1_MASK, PseudoVFRDIV_VF16_M1, PseudoVFRDIV_VF16_M1_TU, 0x3 }, // 317
{ PseudoVFRDIV_VF16_M2_MASK, PseudoVFRDIV_VF16_M2, PseudoVFRDIV_VF16_M2_TU, 0x3 }, // 318
{ PseudoVFRDIV_VF16_M4_MASK, PseudoVFRDIV_VF16_M4, PseudoVFRDIV_VF16_M4_TU, 0x3 }, // 319
{ PseudoVFRDIV_VF16_M8_MASK, PseudoVFRDIV_VF16_M8, PseudoVFRDIV_VF16_M8_TU, 0x3 }, // 320
{ PseudoVFRDIV_VF16_MF2_MASK, PseudoVFRDIV_VF16_MF2, PseudoVFRDIV_VF16_MF2_TU, 0x3 }, // 321
{ PseudoVFRDIV_VF16_MF4_MASK, PseudoVFRDIV_VF16_MF4, PseudoVFRDIV_VF16_MF4_TU, 0x3 }, // 322
{ PseudoVFRDIV_VF32_M1_MASK, PseudoVFRDIV_VF32_M1, PseudoVFRDIV_VF32_M1_TU, 0x3 }, // 323
{ PseudoVFRDIV_VF32_M2_MASK, PseudoVFRDIV_VF32_M2, PseudoVFRDIV_VF32_M2_TU, 0x3 }, // 324
{ PseudoVFRDIV_VF32_M4_MASK, PseudoVFRDIV_VF32_M4, PseudoVFRDIV_VF32_M4_TU, 0x3 }, // 325
{ PseudoVFRDIV_VF32_M8_MASK, PseudoVFRDIV_VF32_M8, PseudoVFRDIV_VF32_M8_TU, 0x3 }, // 326
{ PseudoVFRDIV_VF32_MF2_MASK, PseudoVFRDIV_VF32_MF2, PseudoVFRDIV_VF32_MF2_TU, 0x3 }, // 327
{ PseudoVFRDIV_VF64_M1_MASK, PseudoVFRDIV_VF64_M1, PseudoVFRDIV_VF64_M1_TU, 0x3 }, // 328
{ PseudoVFRDIV_VF64_M2_MASK, PseudoVFRDIV_VF64_M2, PseudoVFRDIV_VF64_M2_TU, 0x3 }, // 329
{ PseudoVFRDIV_VF64_M4_MASK, PseudoVFRDIV_VF64_M4, PseudoVFRDIV_VF64_M4_TU, 0x3 }, // 330
{ PseudoVFRDIV_VF64_M8_MASK, PseudoVFRDIV_VF64_M8, PseudoVFRDIV_VF64_M8_TU, 0x3 }, // 331
{ PseudoVFREC7_V_M1_MASK, PseudoVFREC7_V_M1, PseudoVFREC7_V_M1_TU, 0x2 }, // 332
{ PseudoVFREC7_V_M2_MASK, PseudoVFREC7_V_M2, PseudoVFREC7_V_M2_TU, 0x2 }, // 333
{ PseudoVFREC7_V_M4_MASK, PseudoVFREC7_V_M4, PseudoVFREC7_V_M4_TU, 0x2 }, // 334
{ PseudoVFREC7_V_M8_MASK, PseudoVFREC7_V_M8, PseudoVFREC7_V_M8_TU, 0x2 }, // 335
{ PseudoVFREC7_V_MF2_MASK, PseudoVFREC7_V_MF2, PseudoVFREC7_V_MF2_TU, 0x2 }, // 336
{ PseudoVFREC7_V_MF4_MASK, PseudoVFREC7_V_MF4, PseudoVFREC7_V_MF4_TU, 0x2 }, // 337
{ PseudoVFRSQRT7_V_M1_MASK, PseudoVFRSQRT7_V_M1, PseudoVFRSQRT7_V_M1_TU, 0x2 }, // 338
{ PseudoVFRSQRT7_V_M2_MASK, PseudoVFRSQRT7_V_M2, PseudoVFRSQRT7_V_M2_TU, 0x2 }, // 339
{ PseudoVFRSQRT7_V_M4_MASK, PseudoVFRSQRT7_V_M4, PseudoVFRSQRT7_V_M4_TU, 0x2 }, // 340
{ PseudoVFRSQRT7_V_M8_MASK, PseudoVFRSQRT7_V_M8, PseudoVFRSQRT7_V_M8_TU, 0x2 }, // 341
{ PseudoVFRSQRT7_V_MF2_MASK, PseudoVFRSQRT7_V_MF2, PseudoVFRSQRT7_V_MF2_TU, 0x2 }, // 342
{ PseudoVFRSQRT7_V_MF4_MASK, PseudoVFRSQRT7_V_MF4, PseudoVFRSQRT7_V_MF4_TU, 0x2 }, // 343
{ PseudoVFRSUB_VF16_M1_MASK, PseudoVFRSUB_VF16_M1, PseudoVFRSUB_VF16_M1_TU, 0x3 }, // 344
{ PseudoVFRSUB_VF16_M2_MASK, PseudoVFRSUB_VF16_M2, PseudoVFRSUB_VF16_M2_TU, 0x3 }, // 345
{ PseudoVFRSUB_VF16_M4_MASK, PseudoVFRSUB_VF16_M4, PseudoVFRSUB_VF16_M4_TU, 0x3 }, // 346
{ PseudoVFRSUB_VF16_M8_MASK, PseudoVFRSUB_VF16_M8, PseudoVFRSUB_VF16_M8_TU, 0x3 }, // 347
{ PseudoVFRSUB_VF16_MF2_MASK, PseudoVFRSUB_VF16_MF2, PseudoVFRSUB_VF16_MF2_TU, 0x3 }, // 348
{ PseudoVFRSUB_VF16_MF4_MASK, PseudoVFRSUB_VF16_MF4, PseudoVFRSUB_VF16_MF4_TU, 0x3 }, // 349
{ PseudoVFRSUB_VF32_M1_MASK, PseudoVFRSUB_VF32_M1, PseudoVFRSUB_VF32_M1_TU, 0x3 }, // 350
{ PseudoVFRSUB_VF32_M2_MASK, PseudoVFRSUB_VF32_M2, PseudoVFRSUB_VF32_M2_TU, 0x3 }, // 351
{ PseudoVFRSUB_VF32_M4_MASK, PseudoVFRSUB_VF32_M4, PseudoVFRSUB_VF32_M4_TU, 0x3 }, // 352
{ PseudoVFRSUB_VF32_M8_MASK, PseudoVFRSUB_VF32_M8, PseudoVFRSUB_VF32_M8_TU, 0x3 }, // 353
{ PseudoVFRSUB_VF32_MF2_MASK, PseudoVFRSUB_VF32_MF2, PseudoVFRSUB_VF32_MF2_TU, 0x3 }, // 354
{ PseudoVFRSUB_VF64_M1_MASK, PseudoVFRSUB_VF64_M1, PseudoVFRSUB_VF64_M1_TU, 0x3 }, // 355
{ PseudoVFRSUB_VF64_M2_MASK, PseudoVFRSUB_VF64_M2, PseudoVFRSUB_VF64_M2_TU, 0x3 }, // 356
{ PseudoVFRSUB_VF64_M4_MASK, PseudoVFRSUB_VF64_M4, PseudoVFRSUB_VF64_M4_TU, 0x3 }, // 357
{ PseudoVFRSUB_VF64_M8_MASK, PseudoVFRSUB_VF64_M8, PseudoVFRSUB_VF64_M8_TU, 0x3 }, // 358
{ PseudoVFSGNJN_VF16_M1_MASK, PseudoVFSGNJN_VF16_M1, PseudoVFSGNJN_VF16_M1_TU, 0x3 }, // 359
{ PseudoVFSGNJN_VF16_M2_MASK, PseudoVFSGNJN_VF16_M2, PseudoVFSGNJN_VF16_M2_TU, 0x3 }, // 360
{ PseudoVFSGNJN_VF16_M4_MASK, PseudoVFSGNJN_VF16_M4, PseudoVFSGNJN_VF16_M4_TU, 0x3 }, // 361
{ PseudoVFSGNJN_VF16_M8_MASK, PseudoVFSGNJN_VF16_M8, PseudoVFSGNJN_VF16_M8_TU, 0x3 }, // 362
{ PseudoVFSGNJN_VF16_MF2_MASK, PseudoVFSGNJN_VF16_MF2, PseudoVFSGNJN_VF16_MF2_TU, 0x3 }, // 363
{ PseudoVFSGNJN_VF16_MF4_MASK, PseudoVFSGNJN_VF16_MF4, PseudoVFSGNJN_VF16_MF4_TU, 0x3 }, // 364
{ PseudoVFSGNJN_VF32_M1_MASK, PseudoVFSGNJN_VF32_M1, PseudoVFSGNJN_VF32_M1_TU, 0x3 }, // 365
{ PseudoVFSGNJN_VF32_M2_MASK, PseudoVFSGNJN_VF32_M2, PseudoVFSGNJN_VF32_M2_TU, 0x3 }, // 366
{ PseudoVFSGNJN_VF32_M4_MASK, PseudoVFSGNJN_VF32_M4, PseudoVFSGNJN_VF32_M4_TU, 0x3 }, // 367
{ PseudoVFSGNJN_VF32_M8_MASK, PseudoVFSGNJN_VF32_M8, PseudoVFSGNJN_VF32_M8_TU, 0x3 }, // 368
{ PseudoVFSGNJN_VF32_MF2_MASK, PseudoVFSGNJN_VF32_MF2, PseudoVFSGNJN_VF32_MF2_TU, 0x3 }, // 369
{ PseudoVFSGNJN_VF64_M1_MASK, PseudoVFSGNJN_VF64_M1, PseudoVFSGNJN_VF64_M1_TU, 0x3 }, // 370
{ PseudoVFSGNJN_VF64_M2_MASK, PseudoVFSGNJN_VF64_M2, PseudoVFSGNJN_VF64_M2_TU, 0x3 }, // 371
{ PseudoVFSGNJN_VF64_M4_MASK, PseudoVFSGNJN_VF64_M4, PseudoVFSGNJN_VF64_M4_TU, 0x3 }, // 372
{ PseudoVFSGNJN_VF64_M8_MASK, PseudoVFSGNJN_VF64_M8, PseudoVFSGNJN_VF64_M8_TU, 0x3 }, // 373
{ PseudoVFSGNJN_VV_M1_MASK, PseudoVFSGNJN_VV_M1, PseudoVFSGNJN_VV_M1_TU, 0x3 }, // 374
{ PseudoVFSGNJN_VV_M2_MASK, PseudoVFSGNJN_VV_M2, PseudoVFSGNJN_VV_M2_TU, 0x3 }, // 375
{ PseudoVFSGNJN_VV_M4_MASK, PseudoVFSGNJN_VV_M4, PseudoVFSGNJN_VV_M4_TU, 0x3 }, // 376
{ PseudoVFSGNJN_VV_M8_MASK, PseudoVFSGNJN_VV_M8, PseudoVFSGNJN_VV_M8_TU, 0x3 }, // 377
{ PseudoVFSGNJN_VV_MF2_MASK, PseudoVFSGNJN_VV_MF2, PseudoVFSGNJN_VV_MF2_TU, 0x3 }, // 378
{ PseudoVFSGNJN_VV_MF4_MASK, PseudoVFSGNJN_VV_MF4, PseudoVFSGNJN_VV_MF4_TU, 0x3 }, // 379
{ PseudoVFSGNJX_VF16_M1_MASK, PseudoVFSGNJX_VF16_M1, PseudoVFSGNJX_VF16_M1_TU, 0x3 }, // 380
{ PseudoVFSGNJX_VF16_M2_MASK, PseudoVFSGNJX_VF16_M2, PseudoVFSGNJX_VF16_M2_TU, 0x3 }, // 381
{ PseudoVFSGNJX_VF16_M4_MASK, PseudoVFSGNJX_VF16_M4, PseudoVFSGNJX_VF16_M4_TU, 0x3 }, // 382
{ PseudoVFSGNJX_VF16_M8_MASK, PseudoVFSGNJX_VF16_M8, PseudoVFSGNJX_VF16_M8_TU, 0x3 }, // 383
{ PseudoVFSGNJX_VF16_MF2_MASK, PseudoVFSGNJX_VF16_MF2, PseudoVFSGNJX_VF16_MF2_TU, 0x3 }, // 384
{ PseudoVFSGNJX_VF16_MF4_MASK, PseudoVFSGNJX_VF16_MF4, PseudoVFSGNJX_VF16_MF4_TU, 0x3 }, // 385
{ PseudoVFSGNJX_VF32_M1_MASK, PseudoVFSGNJX_VF32_M1, PseudoVFSGNJX_VF32_M1_TU, 0x3 }, // 386
{ PseudoVFSGNJX_VF32_M2_MASK, PseudoVFSGNJX_VF32_M2, PseudoVFSGNJX_VF32_M2_TU, 0x3 }, // 387
{ PseudoVFSGNJX_VF32_M4_MASK, PseudoVFSGNJX_VF32_M4, PseudoVFSGNJX_VF32_M4_TU, 0x3 }, // 388
{ PseudoVFSGNJX_VF32_M8_MASK, PseudoVFSGNJX_VF32_M8, PseudoVFSGNJX_VF32_M8_TU, 0x3 }, // 389
{ PseudoVFSGNJX_VF32_MF2_MASK, PseudoVFSGNJX_VF32_MF2, PseudoVFSGNJX_VF32_MF2_TU, 0x3 }, // 390
{ PseudoVFSGNJX_VF64_M1_MASK, PseudoVFSGNJX_VF64_M1, PseudoVFSGNJX_VF64_M1_TU, 0x3 }, // 391
{ PseudoVFSGNJX_VF64_M2_MASK, PseudoVFSGNJX_VF64_M2, PseudoVFSGNJX_VF64_M2_TU, 0x3 }, // 392
{ PseudoVFSGNJX_VF64_M4_MASK, PseudoVFSGNJX_VF64_M4, PseudoVFSGNJX_VF64_M4_TU, 0x3 }, // 393
{ PseudoVFSGNJX_VF64_M8_MASK, PseudoVFSGNJX_VF64_M8, PseudoVFSGNJX_VF64_M8_TU, 0x3 }, // 394
{ PseudoVFSGNJX_VV_M1_MASK, PseudoVFSGNJX_VV_M1, PseudoVFSGNJX_VV_M1_TU, 0x3 }, // 395
{ PseudoVFSGNJX_VV_M2_MASK, PseudoVFSGNJX_VV_M2, PseudoVFSGNJX_VV_M2_TU, 0x3 }, // 396
{ PseudoVFSGNJX_VV_M4_MASK, PseudoVFSGNJX_VV_M4, PseudoVFSGNJX_VV_M4_TU, 0x3 }, // 397
{ PseudoVFSGNJX_VV_M8_MASK, PseudoVFSGNJX_VV_M8, PseudoVFSGNJX_VV_M8_TU, 0x3 }, // 398
{ PseudoVFSGNJX_VV_MF2_MASK, PseudoVFSGNJX_VV_MF2, PseudoVFSGNJX_VV_MF2_TU, 0x3 }, // 399
{ PseudoVFSGNJX_VV_MF4_MASK, PseudoVFSGNJX_VV_MF4, PseudoVFSGNJX_VV_MF4_TU, 0x3 }, // 400
{ PseudoVFSGNJ_VF16_M1_MASK, PseudoVFSGNJ_VF16_M1, PseudoVFSGNJ_VF16_M1_TU, 0x3 }, // 401
{ PseudoVFSGNJ_VF16_M2_MASK, PseudoVFSGNJ_VF16_M2, PseudoVFSGNJ_VF16_M2_TU, 0x3 }, // 402
{ PseudoVFSGNJ_VF16_M4_MASK, PseudoVFSGNJ_VF16_M4, PseudoVFSGNJ_VF16_M4_TU, 0x3 }, // 403
{ PseudoVFSGNJ_VF16_M8_MASK, PseudoVFSGNJ_VF16_M8, PseudoVFSGNJ_VF16_M8_TU, 0x3 }, // 404
{ PseudoVFSGNJ_VF16_MF2_MASK, PseudoVFSGNJ_VF16_MF2, PseudoVFSGNJ_VF16_MF2_TU, 0x3 }, // 405
{ PseudoVFSGNJ_VF16_MF4_MASK, PseudoVFSGNJ_VF16_MF4, PseudoVFSGNJ_VF16_MF4_TU, 0x3 }, // 406
{ PseudoVFSGNJ_VF32_M1_MASK, PseudoVFSGNJ_VF32_M1, PseudoVFSGNJ_VF32_M1_TU, 0x3 }, // 407
{ PseudoVFSGNJ_VF32_M2_MASK, PseudoVFSGNJ_VF32_M2, PseudoVFSGNJ_VF32_M2_TU, 0x3 }, // 408
{ PseudoVFSGNJ_VF32_M4_MASK, PseudoVFSGNJ_VF32_M4, PseudoVFSGNJ_VF32_M4_TU, 0x3 }, // 409
{ PseudoVFSGNJ_VF32_M8_MASK, PseudoVFSGNJ_VF32_M8, PseudoVFSGNJ_VF32_M8_TU, 0x3 }, // 410
{ PseudoVFSGNJ_VF32_MF2_MASK, PseudoVFSGNJ_VF32_MF2, PseudoVFSGNJ_VF32_MF2_TU, 0x3 }, // 411
{ PseudoVFSGNJ_VF64_M1_MASK, PseudoVFSGNJ_VF64_M1, PseudoVFSGNJ_VF64_M1_TU, 0x3 }, // 412
{ PseudoVFSGNJ_VF64_M2_MASK, PseudoVFSGNJ_VF64_M2, PseudoVFSGNJ_VF64_M2_TU, 0x3 }, // 413
{ PseudoVFSGNJ_VF64_M4_MASK, PseudoVFSGNJ_VF64_M4, PseudoVFSGNJ_VF64_M4_TU, 0x3 }, // 414
{ PseudoVFSGNJ_VF64_M8_MASK, PseudoVFSGNJ_VF64_M8, PseudoVFSGNJ_VF64_M8_TU, 0x3 }, // 415
{ PseudoVFSGNJ_VV_M1_MASK, PseudoVFSGNJ_VV_M1, PseudoVFSGNJ_VV_M1_TU, 0x3 }, // 416
{ PseudoVFSGNJ_VV_M2_MASK, PseudoVFSGNJ_VV_M2, PseudoVFSGNJ_VV_M2_TU, 0x3 }, // 417
{ PseudoVFSGNJ_VV_M4_MASK, PseudoVFSGNJ_VV_M4, PseudoVFSGNJ_VV_M4_TU, 0x3 }, // 418
{ PseudoVFSGNJ_VV_M8_MASK, PseudoVFSGNJ_VV_M8, PseudoVFSGNJ_VV_M8_TU, 0x3 }, // 419
{ PseudoVFSGNJ_VV_MF2_MASK, PseudoVFSGNJ_VV_MF2, PseudoVFSGNJ_VV_MF2_TU, 0x3 }, // 420
{ PseudoVFSGNJ_VV_MF4_MASK, PseudoVFSGNJ_VV_MF4, PseudoVFSGNJ_VV_MF4_TU, 0x3 }, // 421
{ PseudoVFSLIDE1DOWN_VF16_M1_MASK, PseudoVFSLIDE1DOWN_VF16_M1, PseudoVFSLIDE1DOWN_VF16_M1_TU, 0x3 }, // 422
{ PseudoVFSLIDE1DOWN_VF16_M2_MASK, PseudoVFSLIDE1DOWN_VF16_M2, PseudoVFSLIDE1DOWN_VF16_M2_TU, 0x3 }, // 423
{ PseudoVFSLIDE1DOWN_VF16_M4_MASK, PseudoVFSLIDE1DOWN_VF16_M4, PseudoVFSLIDE1DOWN_VF16_M4_TU, 0x3 }, // 424
{ PseudoVFSLIDE1DOWN_VF16_M8_MASK, PseudoVFSLIDE1DOWN_VF16_M8, PseudoVFSLIDE1DOWN_VF16_M8_TU, 0x3 }, // 425
{ PseudoVFSLIDE1DOWN_VF16_MF2_MASK, PseudoVFSLIDE1DOWN_VF16_MF2, PseudoVFSLIDE1DOWN_VF16_MF2_TU, 0x3 }, // 426
{ PseudoVFSLIDE1DOWN_VF16_MF4_MASK, PseudoVFSLIDE1DOWN_VF16_MF4, PseudoVFSLIDE1DOWN_VF16_MF4_TU, 0x3 }, // 427
{ PseudoVFSLIDE1DOWN_VF32_M1_MASK, PseudoVFSLIDE1DOWN_VF32_M1, PseudoVFSLIDE1DOWN_VF32_M1_TU, 0x3 }, // 428
{ PseudoVFSLIDE1DOWN_VF32_M2_MASK, PseudoVFSLIDE1DOWN_VF32_M2, PseudoVFSLIDE1DOWN_VF32_M2_TU, 0x3 }, // 429
{ PseudoVFSLIDE1DOWN_VF32_M4_MASK, PseudoVFSLIDE1DOWN_VF32_M4, PseudoVFSLIDE1DOWN_VF32_M4_TU, 0x3 }, // 430
{ PseudoVFSLIDE1DOWN_VF32_M8_MASK, PseudoVFSLIDE1DOWN_VF32_M8, PseudoVFSLIDE1DOWN_VF32_M8_TU, 0x3 }, // 431
{ PseudoVFSLIDE1DOWN_VF32_MF2_MASK, PseudoVFSLIDE1DOWN_VF32_MF2, PseudoVFSLIDE1DOWN_VF32_MF2_TU, 0x3 }, // 432
{ PseudoVFSLIDE1DOWN_VF64_M1_MASK, PseudoVFSLIDE1DOWN_VF64_M1, PseudoVFSLIDE1DOWN_VF64_M1_TU, 0x3 }, // 433
{ PseudoVFSLIDE1DOWN_VF64_M2_MASK, PseudoVFSLIDE1DOWN_VF64_M2, PseudoVFSLIDE1DOWN_VF64_M2_TU, 0x3 }, // 434
{ PseudoVFSLIDE1DOWN_VF64_M4_MASK, PseudoVFSLIDE1DOWN_VF64_M4, PseudoVFSLIDE1DOWN_VF64_M4_TU, 0x3 }, // 435
{ PseudoVFSLIDE1DOWN_VF64_M8_MASK, PseudoVFSLIDE1DOWN_VF64_M8, PseudoVFSLIDE1DOWN_VF64_M8_TU, 0x3 }, // 436
{ PseudoVFSLIDE1UP_VF16_M1_MASK, PseudoVFSLIDE1UP_VF16_M1, PseudoVFSLIDE1UP_VF16_M1_TU, 0x3 }, // 437
{ PseudoVFSLIDE1UP_VF16_M2_MASK, PseudoVFSLIDE1UP_VF16_M2, PseudoVFSLIDE1UP_VF16_M2_TU, 0x3 }, // 438
{ PseudoVFSLIDE1UP_VF16_M4_MASK, PseudoVFSLIDE1UP_VF16_M4, PseudoVFSLIDE1UP_VF16_M4_TU, 0x3 }, // 439
{ PseudoVFSLIDE1UP_VF16_M8_MASK, PseudoVFSLIDE1UP_VF16_M8, PseudoVFSLIDE1UP_VF16_M8_TU, 0x3 }, // 440
{ PseudoVFSLIDE1UP_VF16_MF2_MASK, PseudoVFSLIDE1UP_VF16_MF2, PseudoVFSLIDE1UP_VF16_MF2_TU, 0x3 }, // 441
{ PseudoVFSLIDE1UP_VF16_MF4_MASK, PseudoVFSLIDE1UP_VF16_MF4, PseudoVFSLIDE1UP_VF16_MF4_TU, 0x3 }, // 442
{ PseudoVFSLIDE1UP_VF32_M1_MASK, PseudoVFSLIDE1UP_VF32_M1, PseudoVFSLIDE1UP_VF32_M1_TU, 0x3 }, // 443
{ PseudoVFSLIDE1UP_VF32_M2_MASK, PseudoVFSLIDE1UP_VF32_M2, PseudoVFSLIDE1UP_VF32_M2_TU, 0x3 }, // 444
{ PseudoVFSLIDE1UP_VF32_M4_MASK, PseudoVFSLIDE1UP_VF32_M4, PseudoVFSLIDE1UP_VF32_M4_TU, 0x3 }, // 445
{ PseudoVFSLIDE1UP_VF32_M8_MASK, PseudoVFSLIDE1UP_VF32_M8, PseudoVFSLIDE1UP_VF32_M8_TU, 0x3 }, // 446
{ PseudoVFSLIDE1UP_VF32_MF2_MASK, PseudoVFSLIDE1UP_VF32_MF2, PseudoVFSLIDE1UP_VF32_MF2_TU, 0x3 }, // 447
{ PseudoVFSLIDE1UP_VF64_M1_MASK, PseudoVFSLIDE1UP_VF64_M1, PseudoVFSLIDE1UP_VF64_M1_TU, 0x3 }, // 448
{ PseudoVFSLIDE1UP_VF64_M2_MASK, PseudoVFSLIDE1UP_VF64_M2, PseudoVFSLIDE1UP_VF64_M2_TU, 0x3 }, // 449
{ PseudoVFSLIDE1UP_VF64_M4_MASK, PseudoVFSLIDE1UP_VF64_M4, PseudoVFSLIDE1UP_VF64_M4_TU, 0x3 }, // 450
{ PseudoVFSLIDE1UP_VF64_M8_MASK, PseudoVFSLIDE1UP_VF64_M8, PseudoVFSLIDE1UP_VF64_M8_TU, 0x3 }, // 451
{ PseudoVFSQRT_V_M1_MASK, PseudoVFSQRT_V_M1, PseudoVFSQRT_V_M1_TU, 0x2 }, // 452
{ PseudoVFSQRT_V_M2_MASK, PseudoVFSQRT_V_M2, PseudoVFSQRT_V_M2_TU, 0x2 }, // 453
{ PseudoVFSQRT_V_M4_MASK, PseudoVFSQRT_V_M4, PseudoVFSQRT_V_M4_TU, 0x2 }, // 454
{ PseudoVFSQRT_V_M8_MASK, PseudoVFSQRT_V_M8, PseudoVFSQRT_V_M8_TU, 0x2 }, // 455
{ PseudoVFSQRT_V_MF2_MASK, PseudoVFSQRT_V_MF2, PseudoVFSQRT_V_MF2_TU, 0x2 }, // 456
{ PseudoVFSQRT_V_MF4_MASK, PseudoVFSQRT_V_MF4, PseudoVFSQRT_V_MF4_TU, 0x2 }, // 457
{ PseudoVFSUB_VF16_M1_MASK, PseudoVFSUB_VF16_M1, PseudoVFSUB_VF16_M1_TU, 0x3 }, // 458
{ PseudoVFSUB_VF16_M2_MASK, PseudoVFSUB_VF16_M2, PseudoVFSUB_VF16_M2_TU, 0x3 }, // 459
{ PseudoVFSUB_VF16_M4_MASK, PseudoVFSUB_VF16_M4, PseudoVFSUB_VF16_M4_TU, 0x3 }, // 460
{ PseudoVFSUB_VF16_M8_MASK, PseudoVFSUB_VF16_M8, PseudoVFSUB_VF16_M8_TU, 0x3 }, // 461
{ PseudoVFSUB_VF16_MF2_MASK, PseudoVFSUB_VF16_MF2, PseudoVFSUB_VF16_MF2_TU, 0x3 }, // 462
{ PseudoVFSUB_VF16_MF4_MASK, PseudoVFSUB_VF16_MF4, PseudoVFSUB_VF16_MF4_TU, 0x3 }, // 463
{ PseudoVFSUB_VF32_M1_MASK, PseudoVFSUB_VF32_M1, PseudoVFSUB_VF32_M1_TU, 0x3 }, // 464
{ PseudoVFSUB_VF32_M2_MASK, PseudoVFSUB_VF32_M2, PseudoVFSUB_VF32_M2_TU, 0x3 }, // 465
{ PseudoVFSUB_VF32_M4_MASK, PseudoVFSUB_VF32_M4, PseudoVFSUB_VF32_M4_TU, 0x3 }, // 466
{ PseudoVFSUB_VF32_M8_MASK, PseudoVFSUB_VF32_M8, PseudoVFSUB_VF32_M8_TU, 0x3 }, // 467
{ PseudoVFSUB_VF32_MF2_MASK, PseudoVFSUB_VF32_MF2, PseudoVFSUB_VF32_MF2_TU, 0x3 }, // 468
{ PseudoVFSUB_VF64_M1_MASK, PseudoVFSUB_VF64_M1, PseudoVFSUB_VF64_M1_TU, 0x3 }, // 469
{ PseudoVFSUB_VF64_M2_MASK, PseudoVFSUB_VF64_M2, PseudoVFSUB_VF64_M2_TU, 0x3 }, // 470
{ PseudoVFSUB_VF64_M4_MASK, PseudoVFSUB_VF64_M4, PseudoVFSUB_VF64_M4_TU, 0x3 }, // 471
{ PseudoVFSUB_VF64_M8_MASK, PseudoVFSUB_VF64_M8, PseudoVFSUB_VF64_M8_TU, 0x3 }, // 472
{ PseudoVFSUB_VV_M1_MASK, PseudoVFSUB_VV_M1, PseudoVFSUB_VV_M1_TU, 0x3 }, // 473
{ PseudoVFSUB_VV_M2_MASK, PseudoVFSUB_VV_M2, PseudoVFSUB_VV_M2_TU, 0x3 }, // 474
{ PseudoVFSUB_VV_M4_MASK, PseudoVFSUB_VV_M4, PseudoVFSUB_VV_M4_TU, 0x3 }, // 475
{ PseudoVFSUB_VV_M8_MASK, PseudoVFSUB_VV_M8, PseudoVFSUB_VV_M8_TU, 0x3 }, // 476
{ PseudoVFSUB_VV_MF2_MASK, PseudoVFSUB_VV_MF2, PseudoVFSUB_VV_MF2_TU, 0x3 }, // 477
{ PseudoVFSUB_VV_MF4_MASK, PseudoVFSUB_VV_MF4, PseudoVFSUB_VV_MF4_TU, 0x3 }, // 478
{ PseudoVFWADD_VF16_M1_MASK, PseudoVFWADD_VF16_M1, PseudoVFWADD_VF16_M1_TU, 0x3 }, // 479
{ PseudoVFWADD_VF16_M2_MASK, PseudoVFWADD_VF16_M2, PseudoVFWADD_VF16_M2_TU, 0x3 }, // 480
{ PseudoVFWADD_VF16_M4_MASK, PseudoVFWADD_VF16_M4, PseudoVFWADD_VF16_M4_TU, 0x3 }, // 481
{ PseudoVFWADD_VF16_MF2_MASK, PseudoVFWADD_VF16_MF2, PseudoVFWADD_VF16_MF2_TU, 0x3 }, // 482
{ PseudoVFWADD_VF16_MF4_MASK, PseudoVFWADD_VF16_MF4, PseudoVFWADD_VF16_MF4_TU, 0x3 }, // 483
{ PseudoVFWADD_VF32_M1_MASK, PseudoVFWADD_VF32_M1, PseudoVFWADD_VF32_M1_TU, 0x3 }, // 484
{ PseudoVFWADD_VF32_M2_MASK, PseudoVFWADD_VF32_M2, PseudoVFWADD_VF32_M2_TU, 0x3 }, // 485
{ PseudoVFWADD_VF32_M4_MASK, PseudoVFWADD_VF32_M4, PseudoVFWADD_VF32_M4_TU, 0x3 }, // 486
{ PseudoVFWADD_VF32_MF2_MASK, PseudoVFWADD_VF32_MF2, PseudoVFWADD_VF32_MF2_TU, 0x3 }, // 487
{ PseudoVFWADD_VV_M1_MASK, PseudoVFWADD_VV_M1, PseudoVFWADD_VV_M1_TU, 0x3 }, // 488
{ PseudoVFWADD_VV_M2_MASK, PseudoVFWADD_VV_M2, PseudoVFWADD_VV_M2_TU, 0x3 }, // 489
{ PseudoVFWADD_VV_M4_MASK, PseudoVFWADD_VV_M4, PseudoVFWADD_VV_M4_TU, 0x3 }, // 490
{ PseudoVFWADD_VV_MF2_MASK, PseudoVFWADD_VV_MF2, PseudoVFWADD_VV_MF2_TU, 0x3 }, // 491
{ PseudoVFWADD_VV_MF4_MASK, PseudoVFWADD_VV_MF4, PseudoVFWADD_VV_MF4_TU, 0x3 }, // 492
{ PseudoVFWADD_WF16_M1_MASK, PseudoVFWADD_WF16_M1, PseudoVFWADD_WF16_M1_TU, 0x3 }, // 493
{ PseudoVFWADD_WF16_M2_MASK, PseudoVFWADD_WF16_M2, PseudoVFWADD_WF16_M2_TU, 0x3 }, // 494
{ PseudoVFWADD_WF16_M4_MASK, PseudoVFWADD_WF16_M4, PseudoVFWADD_WF16_M4_TU, 0x3 }, // 495
{ PseudoVFWADD_WF16_MF2_MASK, PseudoVFWADD_WF16_MF2, PseudoVFWADD_WF16_MF2_TU, 0x3 }, // 496
{ PseudoVFWADD_WF16_MF4_MASK, PseudoVFWADD_WF16_MF4, PseudoVFWADD_WF16_MF4_TU, 0x3 }, // 497
{ PseudoVFWADD_WF32_M1_MASK, PseudoVFWADD_WF32_M1, PseudoVFWADD_WF32_M1_TU, 0x3 }, // 498
{ PseudoVFWADD_WF32_M2_MASK, PseudoVFWADD_WF32_M2, PseudoVFWADD_WF32_M2_TU, 0x3 }, // 499
{ PseudoVFWADD_WF32_M4_MASK, PseudoVFWADD_WF32_M4, PseudoVFWADD_WF32_M4_TU, 0x3 }, // 500
{ PseudoVFWADD_WF32_MF2_MASK, PseudoVFWADD_WF32_MF2, PseudoVFWADD_WF32_MF2_TU, 0x3 }, // 501
{ PseudoVFWADD_WV_M1_MASK, PseudoVFWADD_WV_M1, PseudoVFWADD_WV_M1_TU, 0x3 }, // 502
{ PseudoVFWADD_WV_M2_MASK, PseudoVFWADD_WV_M2, PseudoVFWADD_WV_M2_TU, 0x3 }, // 503
{ PseudoVFWADD_WV_M4_MASK, PseudoVFWADD_WV_M4, PseudoVFWADD_WV_M4_TU, 0x3 }, // 504
{ PseudoVFWADD_WV_MF2_MASK, PseudoVFWADD_WV_MF2, PseudoVFWADD_WV_MF2_TU, 0x3 }, // 505
{ PseudoVFWADD_WV_MF4_MASK, PseudoVFWADD_WV_MF4, PseudoVFWADD_WV_MF4_TU, 0x3 }, // 506
{ PseudoVFWCVT_F_F_V_M1_MASK, PseudoVFWCVT_F_F_V_M1, PseudoVFWCVT_F_F_V_M1_TU, 0x2 }, // 507
{ PseudoVFWCVT_F_F_V_M2_MASK, PseudoVFWCVT_F_F_V_M2, PseudoVFWCVT_F_F_V_M2_TU, 0x2 }, // 508
{ PseudoVFWCVT_F_F_V_M4_MASK, PseudoVFWCVT_F_F_V_M4, PseudoVFWCVT_F_F_V_M4_TU, 0x2 }, // 509
{ PseudoVFWCVT_F_F_V_MF2_MASK, PseudoVFWCVT_F_F_V_MF2, PseudoVFWCVT_F_F_V_MF2_TU, 0x2 }, // 510
{ PseudoVFWCVT_F_F_V_MF4_MASK, PseudoVFWCVT_F_F_V_MF4, PseudoVFWCVT_F_F_V_MF4_TU, 0x2 }, // 511
{ PseudoVFWCVT_F_XU_V_M1_MASK, PseudoVFWCVT_F_XU_V_M1, PseudoVFWCVT_F_XU_V_M1_TU, 0x2 }, // 512
{ PseudoVFWCVT_F_XU_V_M2_MASK, PseudoVFWCVT_F_XU_V_M2, PseudoVFWCVT_F_XU_V_M2_TU, 0x2 }, // 513
{ PseudoVFWCVT_F_XU_V_M4_MASK, PseudoVFWCVT_F_XU_V_M4, PseudoVFWCVT_F_XU_V_M4_TU, 0x2 }, // 514
{ PseudoVFWCVT_F_XU_V_MF2_MASK, PseudoVFWCVT_F_XU_V_MF2, PseudoVFWCVT_F_XU_V_MF2_TU, 0x2 }, // 515
{ PseudoVFWCVT_F_XU_V_MF4_MASK, PseudoVFWCVT_F_XU_V_MF4, PseudoVFWCVT_F_XU_V_MF4_TU, 0x2 }, // 516
{ PseudoVFWCVT_F_XU_V_MF8_MASK, PseudoVFWCVT_F_XU_V_MF8, PseudoVFWCVT_F_XU_V_MF8_TU, 0x2 }, // 517
{ PseudoVFWCVT_F_X_V_M1_MASK, PseudoVFWCVT_F_X_V_M1, PseudoVFWCVT_F_X_V_M1_TU, 0x2 }, // 518
{ PseudoVFWCVT_F_X_V_M2_MASK, PseudoVFWCVT_F_X_V_M2, PseudoVFWCVT_F_X_V_M2_TU, 0x2 }, // 519
{ PseudoVFWCVT_F_X_V_M4_MASK, PseudoVFWCVT_F_X_V_M4, PseudoVFWCVT_F_X_V_M4_TU, 0x2 }, // 520
{ PseudoVFWCVT_F_X_V_MF2_MASK, PseudoVFWCVT_F_X_V_MF2, PseudoVFWCVT_F_X_V_MF2_TU, 0x2 }, // 521
{ PseudoVFWCVT_F_X_V_MF4_MASK, PseudoVFWCVT_F_X_V_MF4, PseudoVFWCVT_F_X_V_MF4_TU, 0x2 }, // 522
{ PseudoVFWCVT_F_X_V_MF8_MASK, PseudoVFWCVT_F_X_V_MF8, PseudoVFWCVT_F_X_V_MF8_TU, 0x2 }, // 523
{ PseudoVFWCVT_RTZ_XU_F_V_M1_MASK, PseudoVFWCVT_RTZ_XU_F_V_M1, PseudoVFWCVT_RTZ_XU_F_V_M1_TU, 0x2 }, // 524
{ PseudoVFWCVT_RTZ_XU_F_V_M2_MASK, PseudoVFWCVT_RTZ_XU_F_V_M2, PseudoVFWCVT_RTZ_XU_F_V_M2_TU, 0x2 }, // 525
{ PseudoVFWCVT_RTZ_XU_F_V_M4_MASK, PseudoVFWCVT_RTZ_XU_F_V_M4, PseudoVFWCVT_RTZ_XU_F_V_M4_TU, 0x2 }, // 526
{ PseudoVFWCVT_RTZ_XU_F_V_MF2_MASK, PseudoVFWCVT_RTZ_XU_F_V_MF2, PseudoVFWCVT_RTZ_XU_F_V_MF2_TU, 0x2 }, // 527
{ PseudoVFWCVT_RTZ_XU_F_V_MF4_MASK, PseudoVFWCVT_RTZ_XU_F_V_MF4, PseudoVFWCVT_RTZ_XU_F_V_MF4_TU, 0x2 }, // 528
{ PseudoVFWCVT_RTZ_X_F_V_M1_MASK, PseudoVFWCVT_RTZ_X_F_V_M1, PseudoVFWCVT_RTZ_X_F_V_M1_TU, 0x2 }, // 529
{ PseudoVFWCVT_RTZ_X_F_V_M2_MASK, PseudoVFWCVT_RTZ_X_F_V_M2, PseudoVFWCVT_RTZ_X_F_V_M2_TU, 0x2 }, // 530
{ PseudoVFWCVT_RTZ_X_F_V_M4_MASK, PseudoVFWCVT_RTZ_X_F_V_M4, PseudoVFWCVT_RTZ_X_F_V_M4_TU, 0x2 }, // 531
{ PseudoVFWCVT_RTZ_X_F_V_MF2_MASK, PseudoVFWCVT_RTZ_X_F_V_MF2, PseudoVFWCVT_RTZ_X_F_V_MF2_TU, 0x2 }, // 532
{ PseudoVFWCVT_RTZ_X_F_V_MF4_MASK, PseudoVFWCVT_RTZ_X_F_V_MF4, PseudoVFWCVT_RTZ_X_F_V_MF4_TU, 0x2 }, // 533
{ PseudoVFWCVT_XU_F_V_M1_MASK, PseudoVFWCVT_XU_F_V_M1, PseudoVFWCVT_XU_F_V_M1_TU, 0x2 }, // 534
{ PseudoVFWCVT_XU_F_V_M2_MASK, PseudoVFWCVT_XU_F_V_M2, PseudoVFWCVT_XU_F_V_M2_TU, 0x2 }, // 535
{ PseudoVFWCVT_XU_F_V_M4_MASK, PseudoVFWCVT_XU_F_V_M4, PseudoVFWCVT_XU_F_V_M4_TU, 0x2 }, // 536
{ PseudoVFWCVT_XU_F_V_MF2_MASK, PseudoVFWCVT_XU_F_V_MF2, PseudoVFWCVT_XU_F_V_MF2_TU, 0x2 }, // 537
{ PseudoVFWCVT_XU_F_V_MF4_MASK, PseudoVFWCVT_XU_F_V_MF4, PseudoVFWCVT_XU_F_V_MF4_TU, 0x2 }, // 538
{ PseudoVFWCVT_X_F_V_M1_MASK, PseudoVFWCVT_X_F_V_M1, PseudoVFWCVT_X_F_V_M1_TU, 0x2 }, // 539
{ PseudoVFWCVT_X_F_V_M2_MASK, PseudoVFWCVT_X_F_V_M2, PseudoVFWCVT_X_F_V_M2_TU, 0x2 }, // 540
{ PseudoVFWCVT_X_F_V_M4_MASK, PseudoVFWCVT_X_F_V_M4, PseudoVFWCVT_X_F_V_M4_TU, 0x2 }, // 541
{ PseudoVFWCVT_X_F_V_MF2_MASK, PseudoVFWCVT_X_F_V_MF2, PseudoVFWCVT_X_F_V_MF2_TU, 0x2 }, // 542
{ PseudoVFWCVT_X_F_V_MF4_MASK, PseudoVFWCVT_X_F_V_MF4, PseudoVFWCVT_X_F_V_MF4_TU, 0x2 }, // 543
{ PseudoVFWMUL_VF16_M1_MASK, PseudoVFWMUL_VF16_M1, PseudoVFWMUL_VF16_M1_TU, 0x3 }, // 544
{ PseudoVFWMUL_VF16_M2_MASK, PseudoVFWMUL_VF16_M2, PseudoVFWMUL_VF16_M2_TU, 0x3 }, // 545
{ PseudoVFWMUL_VF16_M4_MASK, PseudoVFWMUL_VF16_M4, PseudoVFWMUL_VF16_M4_TU, 0x3 }, // 546
{ PseudoVFWMUL_VF16_MF2_MASK, PseudoVFWMUL_VF16_MF2, PseudoVFWMUL_VF16_MF2_TU, 0x3 }, // 547
{ PseudoVFWMUL_VF16_MF4_MASK, PseudoVFWMUL_VF16_MF4, PseudoVFWMUL_VF16_MF4_TU, 0x3 }, // 548
{ PseudoVFWMUL_VF32_M1_MASK, PseudoVFWMUL_VF32_M1, PseudoVFWMUL_VF32_M1_TU, 0x3 }, // 549
{ PseudoVFWMUL_VF32_M2_MASK, PseudoVFWMUL_VF32_M2, PseudoVFWMUL_VF32_M2_TU, 0x3 }, // 550
{ PseudoVFWMUL_VF32_M4_MASK, PseudoVFWMUL_VF32_M4, PseudoVFWMUL_VF32_M4_TU, 0x3 }, // 551
{ PseudoVFWMUL_VF32_MF2_MASK, PseudoVFWMUL_VF32_MF2, PseudoVFWMUL_VF32_MF2_TU, 0x3 }, // 552
{ PseudoVFWMUL_VV_M1_MASK, PseudoVFWMUL_VV_M1, PseudoVFWMUL_VV_M1_TU, 0x3 }, // 553
{ PseudoVFWMUL_VV_M2_MASK, PseudoVFWMUL_VV_M2, PseudoVFWMUL_VV_M2_TU, 0x3 }, // 554
{ PseudoVFWMUL_VV_M4_MASK, PseudoVFWMUL_VV_M4, PseudoVFWMUL_VV_M4_TU, 0x3 }, // 555
{ PseudoVFWMUL_VV_MF2_MASK, PseudoVFWMUL_VV_MF2, PseudoVFWMUL_VV_MF2_TU, 0x3 }, // 556
{ PseudoVFWMUL_VV_MF4_MASK, PseudoVFWMUL_VV_MF4, PseudoVFWMUL_VV_MF4_TU, 0x3 }, // 557
{ PseudoVFWSUB_VF16_M1_MASK, PseudoVFWSUB_VF16_M1, PseudoVFWSUB_VF16_M1_TU, 0x3 }, // 558
{ PseudoVFWSUB_VF16_M2_MASK, PseudoVFWSUB_VF16_M2, PseudoVFWSUB_VF16_M2_TU, 0x3 }, // 559
{ PseudoVFWSUB_VF16_M4_MASK, PseudoVFWSUB_VF16_M4, PseudoVFWSUB_VF16_M4_TU, 0x3 }, // 560
{ PseudoVFWSUB_VF16_MF2_MASK, PseudoVFWSUB_VF16_MF2, PseudoVFWSUB_VF16_MF2_TU, 0x3 }, // 561
{ PseudoVFWSUB_VF16_MF4_MASK, PseudoVFWSUB_VF16_MF4, PseudoVFWSUB_VF16_MF4_TU, 0x3 }, // 562
{ PseudoVFWSUB_VF32_M1_MASK, PseudoVFWSUB_VF32_M1, PseudoVFWSUB_VF32_M1_TU, 0x3 }, // 563
{ PseudoVFWSUB_VF32_M2_MASK, PseudoVFWSUB_VF32_M2, PseudoVFWSUB_VF32_M2_TU, 0x3 }, // 564
{ PseudoVFWSUB_VF32_M4_MASK, PseudoVFWSUB_VF32_M4, PseudoVFWSUB_VF32_M4_TU, 0x3 }, // 565
{ PseudoVFWSUB_VF32_MF2_MASK, PseudoVFWSUB_VF32_MF2, PseudoVFWSUB_VF32_MF2_TU, 0x3 }, // 566
{ PseudoVFWSUB_VV_M1_MASK, PseudoVFWSUB_VV_M1, PseudoVFWSUB_VV_M1_TU, 0x3 }, // 567
{ PseudoVFWSUB_VV_M2_MASK, PseudoVFWSUB_VV_M2, PseudoVFWSUB_VV_M2_TU, 0x3 }, // 568
{ PseudoVFWSUB_VV_M4_MASK, PseudoVFWSUB_VV_M4, PseudoVFWSUB_VV_M4_TU, 0x3 }, // 569
{ PseudoVFWSUB_VV_MF2_MASK, PseudoVFWSUB_VV_MF2, PseudoVFWSUB_VV_MF2_TU, 0x3 }, // 570
{ PseudoVFWSUB_VV_MF4_MASK, PseudoVFWSUB_VV_MF4, PseudoVFWSUB_VV_MF4_TU, 0x3 }, // 571
{ PseudoVFWSUB_WF16_M1_MASK, PseudoVFWSUB_WF16_M1, PseudoVFWSUB_WF16_M1_TU, 0x3 }, // 572
{ PseudoVFWSUB_WF16_M2_MASK, PseudoVFWSUB_WF16_M2, PseudoVFWSUB_WF16_M2_TU, 0x3 }, // 573
{ PseudoVFWSUB_WF16_M4_MASK, PseudoVFWSUB_WF16_M4, PseudoVFWSUB_WF16_M4_TU, 0x3 }, // 574
{ PseudoVFWSUB_WF16_MF2_MASK, PseudoVFWSUB_WF16_MF2, PseudoVFWSUB_WF16_MF2_TU, 0x3 }, // 575
{ PseudoVFWSUB_WF16_MF4_MASK, PseudoVFWSUB_WF16_MF4, PseudoVFWSUB_WF16_MF4_TU, 0x3 }, // 576
{ PseudoVFWSUB_WF32_M1_MASK, PseudoVFWSUB_WF32_M1, PseudoVFWSUB_WF32_M1_TU, 0x3 }, // 577
{ PseudoVFWSUB_WF32_M2_MASK, PseudoVFWSUB_WF32_M2, PseudoVFWSUB_WF32_M2_TU, 0x3 }, // 578
{ PseudoVFWSUB_WF32_M4_MASK, PseudoVFWSUB_WF32_M4, PseudoVFWSUB_WF32_M4_TU, 0x3 }, // 579
{ PseudoVFWSUB_WF32_MF2_MASK, PseudoVFWSUB_WF32_MF2, PseudoVFWSUB_WF32_MF2_TU, 0x3 }, // 580
{ PseudoVFWSUB_WV_M1_MASK, PseudoVFWSUB_WV_M1, PseudoVFWSUB_WV_M1_TU, 0x3 }, // 581
{ PseudoVFWSUB_WV_M2_MASK, PseudoVFWSUB_WV_M2, PseudoVFWSUB_WV_M2_TU, 0x3 }, // 582
{ PseudoVFWSUB_WV_M4_MASK, PseudoVFWSUB_WV_M4, PseudoVFWSUB_WV_M4_TU, 0x3 }, // 583
{ PseudoVFWSUB_WV_MF2_MASK, PseudoVFWSUB_WV_MF2, PseudoVFWSUB_WV_MF2_TU, 0x3 }, // 584
{ PseudoVFWSUB_WV_MF4_MASK, PseudoVFWSUB_WV_MF4, PseudoVFWSUB_WV_MF4_TU, 0x3 }, // 585
{ PseudoVID_V_M1_MASK, PseudoVID_V_M1, PseudoVID_V_M1_TU, 0x1 }, // 586
{ PseudoVID_V_M2_MASK, PseudoVID_V_M2, PseudoVID_V_M2_TU, 0x1 }, // 587
{ PseudoVID_V_M4_MASK, PseudoVID_V_M4, PseudoVID_V_M4_TU, 0x1 }, // 588
{ PseudoVID_V_M8_MASK, PseudoVID_V_M8, PseudoVID_V_M8_TU, 0x1 }, // 589
{ PseudoVID_V_MF2_MASK, PseudoVID_V_MF2, PseudoVID_V_MF2_TU, 0x1 }, // 590
{ PseudoVID_V_MF4_MASK, PseudoVID_V_MF4, PseudoVID_V_MF4_TU, 0x1 }, // 591
{ PseudoVID_V_MF8_MASK, PseudoVID_V_MF8, PseudoVID_V_MF8_TU, 0x1 }, // 592
{ PseudoVIOTA_M_M1_MASK, PseudoVIOTA_M_M1, PseudoVIOTA_M_M1_TU, 0x2 }, // 593
{ PseudoVIOTA_M_M2_MASK, PseudoVIOTA_M_M2, PseudoVIOTA_M_M2_TU, 0x2 }, // 594
{ PseudoVIOTA_M_M4_MASK, PseudoVIOTA_M_M4, PseudoVIOTA_M_M4_TU, 0x2 }, // 595
{ PseudoVIOTA_M_M8_MASK, PseudoVIOTA_M_M8, PseudoVIOTA_M_M8_TU, 0x2 }, // 596
{ PseudoVIOTA_M_MF2_MASK, PseudoVIOTA_M_MF2, PseudoVIOTA_M_MF2_TU, 0x2 }, // 597
{ PseudoVIOTA_M_MF4_MASK, PseudoVIOTA_M_MF4, PseudoVIOTA_M_MF4_TU, 0x2 }, // 598
{ PseudoVIOTA_M_MF8_MASK, PseudoVIOTA_M_MF8, PseudoVIOTA_M_MF8_TU, 0x2 }, // 599
{ PseudoVLE16FF_V_M1_MASK, PseudoVLE16FF_V_M1, PseudoVLE16FF_V_M1_TU, 0x2 }, // 600
{ PseudoVLE16FF_V_M2_MASK, PseudoVLE16FF_V_M2, PseudoVLE16FF_V_M2_TU, 0x2 }, // 601
{ PseudoVLE16FF_V_M4_MASK, PseudoVLE16FF_V_M4, PseudoVLE16FF_V_M4_TU, 0x2 }, // 602
{ PseudoVLE16FF_V_M8_MASK, PseudoVLE16FF_V_M8, PseudoVLE16FF_V_M8_TU, 0x2 }, // 603
{ PseudoVLE16FF_V_MF2_MASK, PseudoVLE16FF_V_MF2, PseudoVLE16FF_V_MF2_TU, 0x2 }, // 604
{ PseudoVLE16FF_V_MF4_MASK, PseudoVLE16FF_V_MF4, PseudoVLE16FF_V_MF4_TU, 0x2 }, // 605
{ PseudoVLE16_V_M1_MASK, PseudoVLE16_V_M1, PseudoVLE16_V_M1_TU, 0x2 }, // 606
{ PseudoVLE16_V_M2_MASK, PseudoVLE16_V_M2, PseudoVLE16_V_M2_TU, 0x2 }, // 607
{ PseudoVLE16_V_M4_MASK, PseudoVLE16_V_M4, PseudoVLE16_V_M4_TU, 0x2 }, // 608
{ PseudoVLE16_V_M8_MASK, PseudoVLE16_V_M8, PseudoVLE16_V_M8_TU, 0x2 }, // 609
{ PseudoVLE16_V_MF2_MASK, PseudoVLE16_V_MF2, PseudoVLE16_V_MF2_TU, 0x2 }, // 610
{ PseudoVLE16_V_MF4_MASK, PseudoVLE16_V_MF4, PseudoVLE16_V_MF4_TU, 0x2 }, // 611
{ PseudoVLE32FF_V_M1_MASK, PseudoVLE32FF_V_M1, PseudoVLE32FF_V_M1_TU, 0x2 }, // 612
{ PseudoVLE32FF_V_M2_MASK, PseudoVLE32FF_V_M2, PseudoVLE32FF_V_M2_TU, 0x2 }, // 613
{ PseudoVLE32FF_V_M4_MASK, PseudoVLE32FF_V_M4, PseudoVLE32FF_V_M4_TU, 0x2 }, // 614
{ PseudoVLE32FF_V_M8_MASK, PseudoVLE32FF_V_M8, PseudoVLE32FF_V_M8_TU, 0x2 }, // 615
{ PseudoVLE32FF_V_MF2_MASK, PseudoVLE32FF_V_MF2, PseudoVLE32FF_V_MF2_TU, 0x2 }, // 616
{ PseudoVLE32_V_M1_MASK, PseudoVLE32_V_M1, PseudoVLE32_V_M1_TU, 0x2 }, // 617
{ PseudoVLE32_V_M2_MASK, PseudoVLE32_V_M2, PseudoVLE32_V_M2_TU, 0x2 }, // 618
{ PseudoVLE32_V_M4_MASK, PseudoVLE32_V_M4, PseudoVLE32_V_M4_TU, 0x2 }, // 619
{ PseudoVLE32_V_M8_MASK, PseudoVLE32_V_M8, PseudoVLE32_V_M8_TU, 0x2 }, // 620
{ PseudoVLE32_V_MF2_MASK, PseudoVLE32_V_MF2, PseudoVLE32_V_MF2_TU, 0x2 }, // 621
{ PseudoVLE64FF_V_M1_MASK, PseudoVLE64FF_V_M1, PseudoVLE64FF_V_M1_TU, 0x2 }, // 622
{ PseudoVLE64FF_V_M2_MASK, PseudoVLE64FF_V_M2, PseudoVLE64FF_V_M2_TU, 0x2 }, // 623
{ PseudoVLE64FF_V_M4_MASK, PseudoVLE64FF_V_M4, PseudoVLE64FF_V_M4_TU, 0x2 }, // 624
{ PseudoVLE64FF_V_M8_MASK, PseudoVLE64FF_V_M8, PseudoVLE64FF_V_M8_TU, 0x2 }, // 625
{ PseudoVLE64_V_M1_MASK, PseudoVLE64_V_M1, PseudoVLE64_V_M1_TU, 0x2 }, // 626
{ PseudoVLE64_V_M2_MASK, PseudoVLE64_V_M2, PseudoVLE64_V_M2_TU, 0x2 }, // 627
{ PseudoVLE64_V_M4_MASK, PseudoVLE64_V_M4, PseudoVLE64_V_M4_TU, 0x2 }, // 628
{ PseudoVLE64_V_M8_MASK, PseudoVLE64_V_M8, PseudoVLE64_V_M8_TU, 0x2 }, // 629
{ PseudoVLE8FF_V_M1_MASK, PseudoVLE8FF_V_M1, PseudoVLE8FF_V_M1_TU, 0x2 }, // 630
{ PseudoVLE8FF_V_M2_MASK, PseudoVLE8FF_V_M2, PseudoVLE8FF_V_M2_TU, 0x2 }, // 631
{ PseudoVLE8FF_V_M4_MASK, PseudoVLE8FF_V_M4, PseudoVLE8FF_V_M4_TU, 0x2 }, // 632
{ PseudoVLE8FF_V_M8_MASK, PseudoVLE8FF_V_M8, PseudoVLE8FF_V_M8_TU, 0x2 }, // 633
{ PseudoVLE8FF_V_MF2_MASK, PseudoVLE8FF_V_MF2, PseudoVLE8FF_V_MF2_TU, 0x2 }, // 634
{ PseudoVLE8FF_V_MF4_MASK, PseudoVLE8FF_V_MF4, PseudoVLE8FF_V_MF4_TU, 0x2 }, // 635
{ PseudoVLE8FF_V_MF8_MASK, PseudoVLE8FF_V_MF8, PseudoVLE8FF_V_MF8_TU, 0x2 }, // 636
{ PseudoVLE8_V_M1_MASK, PseudoVLE8_V_M1, PseudoVLE8_V_M1_TU, 0x2 }, // 637
{ PseudoVLE8_V_M2_MASK, PseudoVLE8_V_M2, PseudoVLE8_V_M2_TU, 0x2 }, // 638
{ PseudoVLE8_V_M4_MASK, PseudoVLE8_V_M4, PseudoVLE8_V_M4_TU, 0x2 }, // 639
{ PseudoVLE8_V_M8_MASK, PseudoVLE8_V_M8, PseudoVLE8_V_M8_TU, 0x2 }, // 640
{ PseudoVLE8_V_MF2_MASK, PseudoVLE8_V_MF2, PseudoVLE8_V_MF2_TU, 0x2 }, // 641
{ PseudoVLE8_V_MF4_MASK, PseudoVLE8_V_MF4, PseudoVLE8_V_MF4_TU, 0x2 }, // 642
{ PseudoVLE8_V_MF8_MASK, PseudoVLE8_V_MF8, PseudoVLE8_V_MF8_TU, 0x2 }, // 643
{ PseudoVLOXEI16_V_M1_M1_MASK, PseudoVLOXEI16_V_M1_M1, PseudoVLOXEI16_V_M1_M1_TU, 0x3 }, // 644
{ PseudoVLOXEI16_V_M1_M2_MASK, PseudoVLOXEI16_V_M1_M2, PseudoVLOXEI16_V_M1_M2_TU, 0x3 }, // 645
{ PseudoVLOXEI16_V_M1_M4_MASK, PseudoVLOXEI16_V_M1_M4, PseudoVLOXEI16_V_M1_M4_TU, 0x3 }, // 646
{ PseudoVLOXEI16_V_M1_MF2_MASK, PseudoVLOXEI16_V_M1_MF2, PseudoVLOXEI16_V_M1_MF2_TU, 0x3 }, // 647
{ PseudoVLOXEI16_V_M2_M1_MASK, PseudoVLOXEI16_V_M2_M1, PseudoVLOXEI16_V_M2_M1_TU, 0x3 }, // 648
{ PseudoVLOXEI16_V_M2_M2_MASK, PseudoVLOXEI16_V_M2_M2, PseudoVLOXEI16_V_M2_M2_TU, 0x3 }, // 649
{ PseudoVLOXEI16_V_M2_M4_MASK, PseudoVLOXEI16_V_M2_M4, PseudoVLOXEI16_V_M2_M4_TU, 0x3 }, // 650
{ PseudoVLOXEI16_V_M2_M8_MASK, PseudoVLOXEI16_V_M2_M8, PseudoVLOXEI16_V_M2_M8_TU, 0x3 }, // 651
{ PseudoVLOXEI16_V_M4_M2_MASK, PseudoVLOXEI16_V_M4_M2, PseudoVLOXEI16_V_M4_M2_TU, 0x3 }, // 652
{ PseudoVLOXEI16_V_M4_M4_MASK, PseudoVLOXEI16_V_M4_M4, PseudoVLOXEI16_V_M4_M4_TU, 0x3 }, // 653
{ PseudoVLOXEI16_V_M4_M8_MASK, PseudoVLOXEI16_V_M4_M8, PseudoVLOXEI16_V_M4_M8_TU, 0x3 }, // 654
{ PseudoVLOXEI16_V_M8_M4_MASK, PseudoVLOXEI16_V_M8_M4, PseudoVLOXEI16_V_M8_M4_TU, 0x3 }, // 655
{ PseudoVLOXEI16_V_M8_M8_MASK, PseudoVLOXEI16_V_M8_M8, PseudoVLOXEI16_V_M8_M8_TU, 0x3 }, // 656
{ PseudoVLOXEI16_V_MF2_M1_MASK, PseudoVLOXEI16_V_MF2_M1, PseudoVLOXEI16_V_MF2_M1_TU, 0x3 }, // 657
{ PseudoVLOXEI16_V_MF2_M2_MASK, PseudoVLOXEI16_V_MF2_M2, PseudoVLOXEI16_V_MF2_M2_TU, 0x3 }, // 658
{ PseudoVLOXEI16_V_MF2_MF2_MASK, PseudoVLOXEI16_V_MF2_MF2, PseudoVLOXEI16_V_MF2_MF2_TU, 0x3 }, // 659
{ PseudoVLOXEI16_V_MF2_MF4_MASK, PseudoVLOXEI16_V_MF2_MF4, PseudoVLOXEI16_V_MF2_MF4_TU, 0x3 }, // 660
{ PseudoVLOXEI16_V_MF4_M1_MASK, PseudoVLOXEI16_V_MF4_M1, PseudoVLOXEI16_V_MF4_M1_TU, 0x3 }, // 661
{ PseudoVLOXEI16_V_MF4_MF2_MASK, PseudoVLOXEI16_V_MF4_MF2, PseudoVLOXEI16_V_MF4_MF2_TU, 0x3 }, // 662
{ PseudoVLOXEI16_V_MF4_MF4_MASK, PseudoVLOXEI16_V_MF4_MF4, PseudoVLOXEI16_V_MF4_MF4_TU, 0x3 }, // 663
{ PseudoVLOXEI16_V_MF4_MF8_MASK, PseudoVLOXEI16_V_MF4_MF8, PseudoVLOXEI16_V_MF4_MF8_TU, 0x3 }, // 664
{ PseudoVLOXEI32_V_M1_M1_MASK, PseudoVLOXEI32_V_M1_M1, PseudoVLOXEI32_V_M1_M1_TU, 0x3 }, // 665
{ PseudoVLOXEI32_V_M1_M2_MASK, PseudoVLOXEI32_V_M1_M2, PseudoVLOXEI32_V_M1_M2_TU, 0x3 }, // 666
{ PseudoVLOXEI32_V_M1_MF2_MASK, PseudoVLOXEI32_V_M1_MF2, PseudoVLOXEI32_V_M1_MF2_TU, 0x3 }, // 667
{ PseudoVLOXEI32_V_M1_MF4_MASK, PseudoVLOXEI32_V_M1_MF4, PseudoVLOXEI32_V_M1_MF4_TU, 0x3 }, // 668
{ PseudoVLOXEI32_V_M2_M1_MASK, PseudoVLOXEI32_V_M2_M1, PseudoVLOXEI32_V_M2_M1_TU, 0x3 }, // 669
{ PseudoVLOXEI32_V_M2_M2_MASK, PseudoVLOXEI32_V_M2_M2, PseudoVLOXEI32_V_M2_M2_TU, 0x3 }, // 670
{ PseudoVLOXEI32_V_M2_M4_MASK, PseudoVLOXEI32_V_M2_M4, PseudoVLOXEI32_V_M2_M4_TU, 0x3 }, // 671
{ PseudoVLOXEI32_V_M2_MF2_MASK, PseudoVLOXEI32_V_M2_MF2, PseudoVLOXEI32_V_M2_MF2_TU, 0x3 }, // 672
{ PseudoVLOXEI32_V_M4_M1_MASK, PseudoVLOXEI32_V_M4_M1, PseudoVLOXEI32_V_M4_M1_TU, 0x3 }, // 673
{ PseudoVLOXEI32_V_M4_M2_MASK, PseudoVLOXEI32_V_M4_M2, PseudoVLOXEI32_V_M4_M2_TU, 0x3 }, // 674
{ PseudoVLOXEI32_V_M4_M4_MASK, PseudoVLOXEI32_V_M4_M4, PseudoVLOXEI32_V_M4_M4_TU, 0x3 }, // 675
{ PseudoVLOXEI32_V_M4_M8_MASK, PseudoVLOXEI32_V_M4_M8, PseudoVLOXEI32_V_M4_M8_TU, 0x3 }, // 676
{ PseudoVLOXEI32_V_M8_M2_MASK, PseudoVLOXEI32_V_M8_M2, PseudoVLOXEI32_V_M8_M2_TU, 0x3 }, // 677
{ PseudoVLOXEI32_V_M8_M4_MASK, PseudoVLOXEI32_V_M8_M4, PseudoVLOXEI32_V_M8_M4_TU, 0x3 }, // 678
{ PseudoVLOXEI32_V_M8_M8_MASK, PseudoVLOXEI32_V_M8_M8, PseudoVLOXEI32_V_M8_M8_TU, 0x3 }, // 679
{ PseudoVLOXEI32_V_MF2_M1_MASK, PseudoVLOXEI32_V_MF2_M1, PseudoVLOXEI32_V_MF2_M1_TU, 0x3 }, // 680
{ PseudoVLOXEI32_V_MF2_MF2_MASK, PseudoVLOXEI32_V_MF2_MF2, PseudoVLOXEI32_V_MF2_MF2_TU, 0x3 }, // 681
{ PseudoVLOXEI32_V_MF2_MF4_MASK, PseudoVLOXEI32_V_MF2_MF4, PseudoVLOXEI32_V_MF2_MF4_TU, 0x3 }, // 682
{ PseudoVLOXEI32_V_MF2_MF8_MASK, PseudoVLOXEI32_V_MF2_MF8, PseudoVLOXEI32_V_MF2_MF8_TU, 0x3 }, // 683
{ PseudoVLOXEI64_V_M1_M1_MASK, PseudoVLOXEI64_V_M1_M1, PseudoVLOXEI64_V_M1_M1_TU, 0x3 }, // 684
{ PseudoVLOXEI64_V_M1_MF2_MASK, PseudoVLOXEI64_V_M1_MF2, PseudoVLOXEI64_V_M1_MF2_TU, 0x3 }, // 685
{ PseudoVLOXEI64_V_M1_MF4_MASK, PseudoVLOXEI64_V_M1_MF4, PseudoVLOXEI64_V_M1_MF4_TU, 0x3 }, // 686
{ PseudoVLOXEI64_V_M1_MF8_MASK, PseudoVLOXEI64_V_M1_MF8, PseudoVLOXEI64_V_M1_MF8_TU, 0x3 }, // 687
{ PseudoVLOXEI64_V_M2_M1_MASK, PseudoVLOXEI64_V_M2_M1, PseudoVLOXEI64_V_M2_M1_TU, 0x3 }, // 688
{ PseudoVLOXEI64_V_M2_M2_MASK, PseudoVLOXEI64_V_M2_M2, PseudoVLOXEI64_V_M2_M2_TU, 0x3 }, // 689
{ PseudoVLOXEI64_V_M2_MF2_MASK, PseudoVLOXEI64_V_M2_MF2, PseudoVLOXEI64_V_M2_MF2_TU, 0x3 }, // 690
{ PseudoVLOXEI64_V_M2_MF4_MASK, PseudoVLOXEI64_V_M2_MF4, PseudoVLOXEI64_V_M2_MF4_TU, 0x3 }, // 691
{ PseudoVLOXEI64_V_M4_M1_MASK, PseudoVLOXEI64_V_M4_M1, PseudoVLOXEI64_V_M4_M1_TU, 0x3 }, // 692
{ PseudoVLOXEI64_V_M4_M2_MASK, PseudoVLOXEI64_V_M4_M2, PseudoVLOXEI64_V_M4_M2_TU, 0x3 }, // 693
{ PseudoVLOXEI64_V_M4_M4_MASK, PseudoVLOXEI64_V_M4_M4, PseudoVLOXEI64_V_M4_M4_TU, 0x3 }, // 694
{ PseudoVLOXEI64_V_M4_MF2_MASK, PseudoVLOXEI64_V_M4_MF2, PseudoVLOXEI64_V_M4_MF2_TU, 0x3 }, // 695
{ PseudoVLOXEI64_V_M8_M1_MASK, PseudoVLOXEI64_V_M8_M1, PseudoVLOXEI64_V_M8_M1_TU, 0x3 }, // 696
{ PseudoVLOXEI64_V_M8_M2_MASK, PseudoVLOXEI64_V_M8_M2, PseudoVLOXEI64_V_M8_M2_TU, 0x3 }, // 697
{ PseudoVLOXEI64_V_M8_M4_MASK, PseudoVLOXEI64_V_M8_M4, PseudoVLOXEI64_V_M8_M4_TU, 0x3 }, // 698
{ PseudoVLOXEI64_V_M8_M8_MASK, PseudoVLOXEI64_V_M8_M8, PseudoVLOXEI64_V_M8_M8_TU, 0x3 }, // 699
{ PseudoVLOXEI8_V_M1_M1_MASK, PseudoVLOXEI8_V_M1_M1, PseudoVLOXEI8_V_M1_M1_TU, 0x3 }, // 700
{ PseudoVLOXEI8_V_M1_M2_MASK, PseudoVLOXEI8_V_M1_M2, PseudoVLOXEI8_V_M1_M2_TU, 0x3 }, // 701
{ PseudoVLOXEI8_V_M1_M4_MASK, PseudoVLOXEI8_V_M1_M4, PseudoVLOXEI8_V_M1_M4_TU, 0x3 }, // 702
{ PseudoVLOXEI8_V_M1_M8_MASK, PseudoVLOXEI8_V_M1_M8, PseudoVLOXEI8_V_M1_M8_TU, 0x3 }, // 703
{ PseudoVLOXEI8_V_M2_M2_MASK, PseudoVLOXEI8_V_M2_M2, PseudoVLOXEI8_V_M2_M2_TU, 0x3 }, // 704
{ PseudoVLOXEI8_V_M2_M4_MASK, PseudoVLOXEI8_V_M2_M4, PseudoVLOXEI8_V_M2_M4_TU, 0x3 }, // 705
{ PseudoVLOXEI8_V_M2_M8_MASK, PseudoVLOXEI8_V_M2_M8, PseudoVLOXEI8_V_M2_M8_TU, 0x3 }, // 706
{ PseudoVLOXEI8_V_M4_M4_MASK, PseudoVLOXEI8_V_M4_M4, PseudoVLOXEI8_V_M4_M4_TU, 0x3 }, // 707
{ PseudoVLOXEI8_V_M4_M8_MASK, PseudoVLOXEI8_V_M4_M8, PseudoVLOXEI8_V_M4_M8_TU, 0x3 }, // 708
{ PseudoVLOXEI8_V_M8_M8_MASK, PseudoVLOXEI8_V_M8_M8, PseudoVLOXEI8_V_M8_M8_TU, 0x3 }, // 709
{ PseudoVLOXEI8_V_MF2_M1_MASK, PseudoVLOXEI8_V_MF2_M1, PseudoVLOXEI8_V_MF2_M1_TU, 0x3 }, // 710
{ PseudoVLOXEI8_V_MF2_M2_MASK, PseudoVLOXEI8_V_MF2_M2, PseudoVLOXEI8_V_MF2_M2_TU, 0x3 }, // 711
{ PseudoVLOXEI8_V_MF2_M4_MASK, PseudoVLOXEI8_V_MF2_M4, PseudoVLOXEI8_V_MF2_M4_TU, 0x3 }, // 712
{ PseudoVLOXEI8_V_MF2_MF2_MASK, PseudoVLOXEI8_V_MF2_MF2, PseudoVLOXEI8_V_MF2_MF2_TU, 0x3 }, // 713
{ PseudoVLOXEI8_V_MF4_M1_MASK, PseudoVLOXEI8_V_MF4_M1, PseudoVLOXEI8_V_MF4_M1_TU, 0x3 }, // 714
{ PseudoVLOXEI8_V_MF4_M2_MASK, PseudoVLOXEI8_V_MF4_M2, PseudoVLOXEI8_V_MF4_M2_TU, 0x3 }, // 715
{ PseudoVLOXEI8_V_MF4_MF2_MASK, PseudoVLOXEI8_V_MF4_MF2, PseudoVLOXEI8_V_MF4_MF2_TU, 0x3 }, // 716
{ PseudoVLOXEI8_V_MF4_MF4_MASK, PseudoVLOXEI8_V_MF4_MF4, PseudoVLOXEI8_V_MF4_MF4_TU, 0x3 }, // 717
{ PseudoVLOXEI8_V_MF8_M1_MASK, PseudoVLOXEI8_V_MF8_M1, PseudoVLOXEI8_V_MF8_M1_TU, 0x3 }, // 718
{ PseudoVLOXEI8_V_MF8_MF2_MASK, PseudoVLOXEI8_V_MF8_MF2, PseudoVLOXEI8_V_MF8_MF2_TU, 0x3 }, // 719
{ PseudoVLOXEI8_V_MF8_MF4_MASK, PseudoVLOXEI8_V_MF8_MF4, PseudoVLOXEI8_V_MF8_MF4_TU, 0x3 }, // 720
{ PseudoVLOXEI8_V_MF8_MF8_MASK, PseudoVLOXEI8_V_MF8_MF8, PseudoVLOXEI8_V_MF8_MF8_TU, 0x3 }, // 721
{ PseudoVLSE16_V_M1_MASK, PseudoVLSE16_V_M1, PseudoVLSE16_V_M1_TU, 0x3 }, // 722
{ PseudoVLSE16_V_M2_MASK, PseudoVLSE16_V_M2, PseudoVLSE16_V_M2_TU, 0x3 }, // 723
{ PseudoVLSE16_V_M4_MASK, PseudoVLSE16_V_M4, PseudoVLSE16_V_M4_TU, 0x3 }, // 724
{ PseudoVLSE16_V_M8_MASK, PseudoVLSE16_V_M8, PseudoVLSE16_V_M8_TU, 0x3 }, // 725
{ PseudoVLSE16_V_MF2_MASK, PseudoVLSE16_V_MF2, PseudoVLSE16_V_MF2_TU, 0x3 }, // 726
{ PseudoVLSE16_V_MF4_MASK, PseudoVLSE16_V_MF4, PseudoVLSE16_V_MF4_TU, 0x3 }, // 727
{ PseudoVLSE32_V_M1_MASK, PseudoVLSE32_V_M1, PseudoVLSE32_V_M1_TU, 0x3 }, // 728
{ PseudoVLSE32_V_M2_MASK, PseudoVLSE32_V_M2, PseudoVLSE32_V_M2_TU, 0x3 }, // 729
{ PseudoVLSE32_V_M4_MASK, PseudoVLSE32_V_M4, PseudoVLSE32_V_M4_TU, 0x3 }, // 730
{ PseudoVLSE32_V_M8_MASK, PseudoVLSE32_V_M8, PseudoVLSE32_V_M8_TU, 0x3 }, // 731
{ PseudoVLSE32_V_MF2_MASK, PseudoVLSE32_V_MF2, PseudoVLSE32_V_MF2_TU, 0x3 }, // 732
{ PseudoVLSE64_V_M1_MASK, PseudoVLSE64_V_M1, PseudoVLSE64_V_M1_TU, 0x3 }, // 733
{ PseudoVLSE64_V_M2_MASK, PseudoVLSE64_V_M2, PseudoVLSE64_V_M2_TU, 0x3 }, // 734
{ PseudoVLSE64_V_M4_MASK, PseudoVLSE64_V_M4, PseudoVLSE64_V_M4_TU, 0x3 }, // 735
{ PseudoVLSE64_V_M8_MASK, PseudoVLSE64_V_M8, PseudoVLSE64_V_M8_TU, 0x3 }, // 736
{ PseudoVLSE8_V_M1_MASK, PseudoVLSE8_V_M1, PseudoVLSE8_V_M1_TU, 0x3 }, // 737
{ PseudoVLSE8_V_M2_MASK, PseudoVLSE8_V_M2, PseudoVLSE8_V_M2_TU, 0x3 }, // 738
{ PseudoVLSE8_V_M4_MASK, PseudoVLSE8_V_M4, PseudoVLSE8_V_M4_TU, 0x3 }, // 739
{ PseudoVLSE8_V_M8_MASK, PseudoVLSE8_V_M8, PseudoVLSE8_V_M8_TU, 0x3 }, // 740
{ PseudoVLSE8_V_MF2_MASK, PseudoVLSE8_V_MF2, PseudoVLSE8_V_MF2_TU, 0x3 }, // 741
{ PseudoVLSE8_V_MF4_MASK, PseudoVLSE8_V_MF4, PseudoVLSE8_V_MF4_TU, 0x3 }, // 742
{ PseudoVLSE8_V_MF8_MASK, PseudoVLSE8_V_MF8, PseudoVLSE8_V_MF8_TU, 0x3 }, // 743
{ PseudoVLUXEI16_V_M1_M1_MASK, PseudoVLUXEI16_V_M1_M1, PseudoVLUXEI16_V_M1_M1_TU, 0x3 }, // 744
{ PseudoVLUXEI16_V_M1_M2_MASK, PseudoVLUXEI16_V_M1_M2, PseudoVLUXEI16_V_M1_M2_TU, 0x3 }, // 745
{ PseudoVLUXEI16_V_M1_M4_MASK, PseudoVLUXEI16_V_M1_M4, PseudoVLUXEI16_V_M1_M4_TU, 0x3 }, // 746
{ PseudoVLUXEI16_V_M1_MF2_MASK, PseudoVLUXEI16_V_M1_MF2, PseudoVLUXEI16_V_M1_MF2_TU, 0x3 }, // 747
{ PseudoVLUXEI16_V_M2_M1_MASK, PseudoVLUXEI16_V_M2_M1, PseudoVLUXEI16_V_M2_M1_TU, 0x3 }, // 748
{ PseudoVLUXEI16_V_M2_M2_MASK, PseudoVLUXEI16_V_M2_M2, PseudoVLUXEI16_V_M2_M2_TU, 0x3 }, // 749
{ PseudoVLUXEI16_V_M2_M4_MASK, PseudoVLUXEI16_V_M2_M4, PseudoVLUXEI16_V_M2_M4_TU, 0x3 }, // 750
{ PseudoVLUXEI16_V_M2_M8_MASK, PseudoVLUXEI16_V_M2_M8, PseudoVLUXEI16_V_M2_M8_TU, 0x3 }, // 751
{ PseudoVLUXEI16_V_M4_M2_MASK, PseudoVLUXEI16_V_M4_M2, PseudoVLUXEI16_V_M4_M2_TU, 0x3 }, // 752
{ PseudoVLUXEI16_V_M4_M4_MASK, PseudoVLUXEI16_V_M4_M4, PseudoVLUXEI16_V_M4_M4_TU, 0x3 }, // 753
{ PseudoVLUXEI16_V_M4_M8_MASK, PseudoVLUXEI16_V_M4_M8, PseudoVLUXEI16_V_M4_M8_TU, 0x3 }, // 754
{ PseudoVLUXEI16_V_M8_M4_MASK, PseudoVLUXEI16_V_M8_M4, PseudoVLUXEI16_V_M8_M4_TU, 0x3 }, // 755
{ PseudoVLUXEI16_V_M8_M8_MASK, PseudoVLUXEI16_V_M8_M8, PseudoVLUXEI16_V_M8_M8_TU, 0x3 }, // 756
{ PseudoVLUXEI16_V_MF2_M1_MASK, PseudoVLUXEI16_V_MF2_M1, PseudoVLUXEI16_V_MF2_M1_TU, 0x3 }, // 757
{ PseudoVLUXEI16_V_MF2_M2_MASK, PseudoVLUXEI16_V_MF2_M2, PseudoVLUXEI16_V_MF2_M2_TU, 0x3 }, // 758
{ PseudoVLUXEI16_V_MF2_MF2_MASK, PseudoVLUXEI16_V_MF2_MF2, PseudoVLUXEI16_V_MF2_MF2_TU, 0x3 }, // 759
{ PseudoVLUXEI16_V_MF2_MF4_MASK, PseudoVLUXEI16_V_MF2_MF4, PseudoVLUXEI16_V_MF2_MF4_TU, 0x3 }, // 760
{ PseudoVLUXEI16_V_MF4_M1_MASK, PseudoVLUXEI16_V_MF4_M1, PseudoVLUXEI16_V_MF4_M1_TU, 0x3 }, // 761
{ PseudoVLUXEI16_V_MF4_MF2_MASK, PseudoVLUXEI16_V_MF4_MF2, PseudoVLUXEI16_V_MF4_MF2_TU, 0x3 }, // 762
{ PseudoVLUXEI16_V_MF4_MF4_MASK, PseudoVLUXEI16_V_MF4_MF4, PseudoVLUXEI16_V_MF4_MF4_TU, 0x3 }, // 763
{ PseudoVLUXEI16_V_MF4_MF8_MASK, PseudoVLUXEI16_V_MF4_MF8, PseudoVLUXEI16_V_MF4_MF8_TU, 0x3 }, // 764
{ PseudoVLUXEI32_V_M1_M1_MASK, PseudoVLUXEI32_V_M1_M1, PseudoVLUXEI32_V_M1_M1_TU, 0x3 }, // 765
{ PseudoVLUXEI32_V_M1_M2_MASK, PseudoVLUXEI32_V_M1_M2, PseudoVLUXEI32_V_M1_M2_TU, 0x3 }, // 766
{ PseudoVLUXEI32_V_M1_MF2_MASK, PseudoVLUXEI32_V_M1_MF2, PseudoVLUXEI32_V_M1_MF2_TU, 0x3 }, // 767
{ PseudoVLUXEI32_V_M1_MF4_MASK, PseudoVLUXEI32_V_M1_MF4, PseudoVLUXEI32_V_M1_MF4_TU, 0x3 }, // 768
{ PseudoVLUXEI32_V_M2_M1_MASK, PseudoVLUXEI32_V_M2_M1, PseudoVLUXEI32_V_M2_M1_TU, 0x3 }, // 769
{ PseudoVLUXEI32_V_M2_M2_MASK, PseudoVLUXEI32_V_M2_M2, PseudoVLUXEI32_V_M2_M2_TU, 0x3 }, // 770
{ PseudoVLUXEI32_V_M2_M4_MASK, PseudoVLUXEI32_V_M2_M4, PseudoVLUXEI32_V_M2_M4_TU, 0x3 }, // 771
{ PseudoVLUXEI32_V_M2_MF2_MASK, PseudoVLUXEI32_V_M2_MF2, PseudoVLUXEI32_V_M2_MF2_TU, 0x3 }, // 772
{ PseudoVLUXEI32_V_M4_M1_MASK, PseudoVLUXEI32_V_M4_M1, PseudoVLUXEI32_V_M4_M1_TU, 0x3 }, // 773
{ PseudoVLUXEI32_V_M4_M2_MASK, PseudoVLUXEI32_V_M4_M2, PseudoVLUXEI32_V_M4_M2_TU, 0x3 }, // 774
{ PseudoVLUXEI32_V_M4_M4_MASK, PseudoVLUXEI32_V_M4_M4, PseudoVLUXEI32_V_M4_M4_TU, 0x3 }, // 775
{ PseudoVLUXEI32_V_M4_M8_MASK, PseudoVLUXEI32_V_M4_M8, PseudoVLUXEI32_V_M4_M8_TU, 0x3 }, // 776
{ PseudoVLUXEI32_V_M8_M2_MASK, PseudoVLUXEI32_V_M8_M2, PseudoVLUXEI32_V_M8_M2_TU, 0x3 }, // 777
{ PseudoVLUXEI32_V_M8_M4_MASK, PseudoVLUXEI32_V_M8_M4, PseudoVLUXEI32_V_M8_M4_TU, 0x3 }, // 778
{ PseudoVLUXEI32_V_M8_M8_MASK, PseudoVLUXEI32_V_M8_M8, PseudoVLUXEI32_V_M8_M8_TU, 0x3 }, // 779
{ PseudoVLUXEI32_V_MF2_M1_MASK, PseudoVLUXEI32_V_MF2_M1, PseudoVLUXEI32_V_MF2_M1_TU, 0x3 }, // 780
{ PseudoVLUXEI32_V_MF2_MF2_MASK, PseudoVLUXEI32_V_MF2_MF2, PseudoVLUXEI32_V_MF2_MF2_TU, 0x3 }, // 781
{ PseudoVLUXEI32_V_MF2_MF4_MASK, PseudoVLUXEI32_V_MF2_MF4, PseudoVLUXEI32_V_MF2_MF4_TU, 0x3 }, // 782
{ PseudoVLUXEI32_V_MF2_MF8_MASK, PseudoVLUXEI32_V_MF2_MF8, PseudoVLUXEI32_V_MF2_MF8_TU, 0x3 }, // 783
{ PseudoVLUXEI64_V_M1_M1_MASK, PseudoVLUXEI64_V_M1_M1, PseudoVLUXEI64_V_M1_M1_TU, 0x3 }, // 784
{ PseudoVLUXEI64_V_M1_MF2_MASK, PseudoVLUXEI64_V_M1_MF2, PseudoVLUXEI64_V_M1_MF2_TU, 0x3 }, // 785
{ PseudoVLUXEI64_V_M1_MF4_MASK, PseudoVLUXEI64_V_M1_MF4, PseudoVLUXEI64_V_M1_MF4_TU, 0x3 }, // 786
{ PseudoVLUXEI64_V_M1_MF8_MASK, PseudoVLUXEI64_V_M1_MF8, PseudoVLUXEI64_V_M1_MF8_TU, 0x3 }, // 787
{ PseudoVLUXEI64_V_M2_M1_MASK, PseudoVLUXEI64_V_M2_M1, PseudoVLUXEI64_V_M2_M1_TU, 0x3 }, // 788
{ PseudoVLUXEI64_V_M2_M2_MASK, PseudoVLUXEI64_V_M2_M2, PseudoVLUXEI64_V_M2_M2_TU, 0x3 }, // 789
{ PseudoVLUXEI64_V_M2_MF2_MASK, PseudoVLUXEI64_V_M2_MF2, PseudoVLUXEI64_V_M2_MF2_TU, 0x3 }, // 790
{ PseudoVLUXEI64_V_M2_MF4_MASK, PseudoVLUXEI64_V_M2_MF4, PseudoVLUXEI64_V_M2_MF4_TU, 0x3 }, // 791
{ PseudoVLUXEI64_V_M4_M1_MASK, PseudoVLUXEI64_V_M4_M1, PseudoVLUXEI64_V_M4_M1_TU, 0x3 }, // 792
{ PseudoVLUXEI64_V_M4_M2_MASK, PseudoVLUXEI64_V_M4_M2, PseudoVLUXEI64_V_M4_M2_TU, 0x3 }, // 793
{ PseudoVLUXEI64_V_M4_M4_MASK, PseudoVLUXEI64_V_M4_M4, PseudoVLUXEI64_V_M4_M4_TU, 0x3 }, // 794
{ PseudoVLUXEI64_V_M4_MF2_MASK, PseudoVLUXEI64_V_M4_MF2, PseudoVLUXEI64_V_M4_MF2_TU, 0x3 }, // 795
{ PseudoVLUXEI64_V_M8_M1_MASK, PseudoVLUXEI64_V_M8_M1, PseudoVLUXEI64_V_M8_M1_TU, 0x3 }, // 796
{ PseudoVLUXEI64_V_M8_M2_MASK, PseudoVLUXEI64_V_M8_M2, PseudoVLUXEI64_V_M8_M2_TU, 0x3 }, // 797
{ PseudoVLUXEI64_V_M8_M4_MASK, PseudoVLUXEI64_V_M8_M4, PseudoVLUXEI64_V_M8_M4_TU, 0x3 }, // 798
{ PseudoVLUXEI64_V_M8_M8_MASK, PseudoVLUXEI64_V_M8_M8, PseudoVLUXEI64_V_M8_M8_TU, 0x3 }, // 799
{ PseudoVLUXEI8_V_M1_M1_MASK, PseudoVLUXEI8_V_M1_M1, PseudoVLUXEI8_V_M1_M1_TU, 0x3 }, // 800
{ PseudoVLUXEI8_V_M1_M2_MASK, PseudoVLUXEI8_V_M1_M2, PseudoVLUXEI8_V_M1_M2_TU, 0x3 }, // 801
{ PseudoVLUXEI8_V_M1_M4_MASK, PseudoVLUXEI8_V_M1_M4, PseudoVLUXEI8_V_M1_M4_TU, 0x3 }, // 802
{ PseudoVLUXEI8_V_M1_M8_MASK, PseudoVLUXEI8_V_M1_M8, PseudoVLUXEI8_V_M1_M8_TU, 0x3 }, // 803
{ PseudoVLUXEI8_V_M2_M2_MASK, PseudoVLUXEI8_V_M2_M2, PseudoVLUXEI8_V_M2_M2_TU, 0x3 }, // 804
{ PseudoVLUXEI8_V_M2_M4_MASK, PseudoVLUXEI8_V_M2_M4, PseudoVLUXEI8_V_M2_M4_TU, 0x3 }, // 805
{ PseudoVLUXEI8_V_M2_M8_MASK, PseudoVLUXEI8_V_M2_M8, PseudoVLUXEI8_V_M2_M8_TU, 0x3 }, // 806
{ PseudoVLUXEI8_V_M4_M4_MASK, PseudoVLUXEI8_V_M4_M4, PseudoVLUXEI8_V_M4_M4_TU, 0x3 }, // 807
{ PseudoVLUXEI8_V_M4_M8_MASK, PseudoVLUXEI8_V_M4_M8, PseudoVLUXEI8_V_M4_M8_TU, 0x3 }, // 808
{ PseudoVLUXEI8_V_M8_M8_MASK, PseudoVLUXEI8_V_M8_M8, PseudoVLUXEI8_V_M8_M8_TU, 0x3 }, // 809
{ PseudoVLUXEI8_V_MF2_M1_MASK, PseudoVLUXEI8_V_MF2_M1, PseudoVLUXEI8_V_MF2_M1_TU, 0x3 }, // 810
{ PseudoVLUXEI8_V_MF2_M2_MASK, PseudoVLUXEI8_V_MF2_M2, PseudoVLUXEI8_V_MF2_M2_TU, 0x3 }, // 811
{ PseudoVLUXEI8_V_MF2_M4_MASK, PseudoVLUXEI8_V_MF2_M4, PseudoVLUXEI8_V_MF2_M4_TU, 0x3 }, // 812
{ PseudoVLUXEI8_V_MF2_MF2_MASK, PseudoVLUXEI8_V_MF2_MF2, PseudoVLUXEI8_V_MF2_MF2_TU, 0x3 }, // 813
{ PseudoVLUXEI8_V_MF4_M1_MASK, PseudoVLUXEI8_V_MF4_M1, PseudoVLUXEI8_V_MF4_M1_TU, 0x3 }, // 814
{ PseudoVLUXEI8_V_MF4_M2_MASK, PseudoVLUXEI8_V_MF4_M2, PseudoVLUXEI8_V_MF4_M2_TU, 0x3 }, // 815
{ PseudoVLUXEI8_V_MF4_MF2_MASK, PseudoVLUXEI8_V_MF4_MF2, PseudoVLUXEI8_V_MF4_MF2_TU, 0x3 }, // 816
{ PseudoVLUXEI8_V_MF4_MF4_MASK, PseudoVLUXEI8_V_MF4_MF4, PseudoVLUXEI8_V_MF4_MF4_TU, 0x3 }, // 817
{ PseudoVLUXEI8_V_MF8_M1_MASK, PseudoVLUXEI8_V_MF8_M1, PseudoVLUXEI8_V_MF8_M1_TU, 0x3 }, // 818
{ PseudoVLUXEI8_V_MF8_MF2_MASK, PseudoVLUXEI8_V_MF8_MF2, PseudoVLUXEI8_V_MF8_MF2_TU, 0x3 }, // 819
{ PseudoVLUXEI8_V_MF8_MF4_MASK, PseudoVLUXEI8_V_MF8_MF4, PseudoVLUXEI8_V_MF8_MF4_TU, 0x3 }, // 820
{ PseudoVLUXEI8_V_MF8_MF8_MASK, PseudoVLUXEI8_V_MF8_MF8, PseudoVLUXEI8_V_MF8_MF8_TU, 0x3 }, // 821
{ PseudoVMAXU_VV_M1_MASK, PseudoVMAXU_VV_M1, PseudoVMAXU_VV_M1_TU, 0x3 }, // 822
{ PseudoVMAXU_VV_M2_MASK, PseudoVMAXU_VV_M2, PseudoVMAXU_VV_M2_TU, 0x3 }, // 823
{ PseudoVMAXU_VV_M4_MASK, PseudoVMAXU_VV_M4, PseudoVMAXU_VV_M4_TU, 0x3 }, // 824
{ PseudoVMAXU_VV_M8_MASK, PseudoVMAXU_VV_M8, PseudoVMAXU_VV_M8_TU, 0x3 }, // 825
{ PseudoVMAXU_VV_MF2_MASK, PseudoVMAXU_VV_MF2, PseudoVMAXU_VV_MF2_TU, 0x3 }, // 826
{ PseudoVMAXU_VV_MF4_MASK, PseudoVMAXU_VV_MF4, PseudoVMAXU_VV_MF4_TU, 0x3 }, // 827
{ PseudoVMAXU_VV_MF8_MASK, PseudoVMAXU_VV_MF8, PseudoVMAXU_VV_MF8_TU, 0x3 }, // 828
{ PseudoVMAXU_VX_M1_MASK, PseudoVMAXU_VX_M1, PseudoVMAXU_VX_M1_TU, 0x3 }, // 829
{ PseudoVMAXU_VX_M2_MASK, PseudoVMAXU_VX_M2, PseudoVMAXU_VX_M2_TU, 0x3 }, // 830
{ PseudoVMAXU_VX_M4_MASK, PseudoVMAXU_VX_M4, PseudoVMAXU_VX_M4_TU, 0x3 }, // 831
{ PseudoVMAXU_VX_M8_MASK, PseudoVMAXU_VX_M8, PseudoVMAXU_VX_M8_TU, 0x3 }, // 832
{ PseudoVMAXU_VX_MF2_MASK, PseudoVMAXU_VX_MF2, PseudoVMAXU_VX_MF2_TU, 0x3 }, // 833
{ PseudoVMAXU_VX_MF4_MASK, PseudoVMAXU_VX_MF4, PseudoVMAXU_VX_MF4_TU, 0x3 }, // 834
{ PseudoVMAXU_VX_MF8_MASK, PseudoVMAXU_VX_MF8, PseudoVMAXU_VX_MF8_TU, 0x3 }, // 835
{ PseudoVMAX_VV_M1_MASK, PseudoVMAX_VV_M1, PseudoVMAX_VV_M1_TU, 0x3 }, // 836
{ PseudoVMAX_VV_M2_MASK, PseudoVMAX_VV_M2, PseudoVMAX_VV_M2_TU, 0x3 }, // 837
{ PseudoVMAX_VV_M4_MASK, PseudoVMAX_VV_M4, PseudoVMAX_VV_M4_TU, 0x3 }, // 838
{ PseudoVMAX_VV_M8_MASK, PseudoVMAX_VV_M8, PseudoVMAX_VV_M8_TU, 0x3 }, // 839
{ PseudoVMAX_VV_MF2_MASK, PseudoVMAX_VV_MF2, PseudoVMAX_VV_MF2_TU, 0x3 }, // 840
{ PseudoVMAX_VV_MF4_MASK, PseudoVMAX_VV_MF4, PseudoVMAX_VV_MF4_TU, 0x3 }, // 841
{ PseudoVMAX_VV_MF8_MASK, PseudoVMAX_VV_MF8, PseudoVMAX_VV_MF8_TU, 0x3 }, // 842
{ PseudoVMAX_VX_M1_MASK, PseudoVMAX_VX_M1, PseudoVMAX_VX_M1_TU, 0x3 }, // 843
{ PseudoVMAX_VX_M2_MASK, PseudoVMAX_VX_M2, PseudoVMAX_VX_M2_TU, 0x3 }, // 844
{ PseudoVMAX_VX_M4_MASK, PseudoVMAX_VX_M4, PseudoVMAX_VX_M4_TU, 0x3 }, // 845
{ PseudoVMAX_VX_M8_MASK, PseudoVMAX_VX_M8, PseudoVMAX_VX_M8_TU, 0x3 }, // 846
{ PseudoVMAX_VX_MF2_MASK, PseudoVMAX_VX_MF2, PseudoVMAX_VX_MF2_TU, 0x3 }, // 847
{ PseudoVMAX_VX_MF4_MASK, PseudoVMAX_VX_MF4, PseudoVMAX_VX_MF4_TU, 0x3 }, // 848
{ PseudoVMAX_VX_MF8_MASK, PseudoVMAX_VX_MF8, PseudoVMAX_VX_MF8_TU, 0x3 }, // 849
{ PseudoVMFEQ_VF16_M1_MASK, PseudoVMFEQ_VF16_M1, PseudoVMFEQ_VF16_M1_MASK, 0x3 }, // 850
{ PseudoVMFEQ_VF16_M2_MASK, PseudoVMFEQ_VF16_M2, PseudoVMFEQ_VF16_M2_MASK, 0x3 }, // 851
{ PseudoVMFEQ_VF16_M4_MASK, PseudoVMFEQ_VF16_M4, PseudoVMFEQ_VF16_M4_MASK, 0x3 }, // 852
{ PseudoVMFEQ_VF16_M8_MASK, PseudoVMFEQ_VF16_M8, PseudoVMFEQ_VF16_M8_MASK, 0x3 }, // 853
{ PseudoVMFEQ_VF16_MF2_MASK, PseudoVMFEQ_VF16_MF2, PseudoVMFEQ_VF16_MF2_MASK, 0x3 }, // 854
{ PseudoVMFEQ_VF16_MF4_MASK, PseudoVMFEQ_VF16_MF4, PseudoVMFEQ_VF16_MF4_MASK, 0x3 }, // 855
{ PseudoVMFEQ_VF32_M1_MASK, PseudoVMFEQ_VF32_M1, PseudoVMFEQ_VF32_M1_MASK, 0x3 }, // 856
{ PseudoVMFEQ_VF32_M2_MASK, PseudoVMFEQ_VF32_M2, PseudoVMFEQ_VF32_M2_MASK, 0x3 }, // 857
{ PseudoVMFEQ_VF32_M4_MASK, PseudoVMFEQ_VF32_M4, PseudoVMFEQ_VF32_M4_MASK, 0x3 }, // 858
{ PseudoVMFEQ_VF32_M8_MASK, PseudoVMFEQ_VF32_M8, PseudoVMFEQ_VF32_M8_MASK, 0x3 }, // 859
{ PseudoVMFEQ_VF32_MF2_MASK, PseudoVMFEQ_VF32_MF2, PseudoVMFEQ_VF32_MF2_MASK, 0x3 }, // 860
{ PseudoVMFEQ_VF64_M1_MASK, PseudoVMFEQ_VF64_M1, PseudoVMFEQ_VF64_M1_MASK, 0x3 }, // 861
{ PseudoVMFEQ_VF64_M2_MASK, PseudoVMFEQ_VF64_M2, PseudoVMFEQ_VF64_M2_MASK, 0x3 }, // 862
{ PseudoVMFEQ_VF64_M4_MASK, PseudoVMFEQ_VF64_M4, PseudoVMFEQ_VF64_M4_MASK, 0x3 }, // 863
{ PseudoVMFEQ_VF64_M8_MASK, PseudoVMFEQ_VF64_M8, PseudoVMFEQ_VF64_M8_MASK, 0x3 }, // 864
{ PseudoVMFEQ_VV_M1_MASK, PseudoVMFEQ_VV_M1, PseudoVMFEQ_VV_M1_MASK, 0x3 }, // 865
{ PseudoVMFEQ_VV_M2_MASK, PseudoVMFEQ_VV_M2, PseudoVMFEQ_VV_M2_MASK, 0x3 }, // 866
{ PseudoVMFEQ_VV_M4_MASK, PseudoVMFEQ_VV_M4, PseudoVMFEQ_VV_M4_MASK, 0x3 }, // 867
{ PseudoVMFEQ_VV_M8_MASK, PseudoVMFEQ_VV_M8, PseudoVMFEQ_VV_M8_MASK, 0x3 }, // 868
{ PseudoVMFEQ_VV_MF2_MASK, PseudoVMFEQ_VV_MF2, PseudoVMFEQ_VV_MF2_MASK, 0x3 }, // 869
{ PseudoVMFEQ_VV_MF4_MASK, PseudoVMFEQ_VV_MF4, PseudoVMFEQ_VV_MF4_MASK, 0x3 }, // 870
{ PseudoVMFGE_VF16_M1_MASK, PseudoVMFGE_VF16_M1, PseudoVMFGE_VF16_M1_MASK, 0x3 }, // 871
{ PseudoVMFGE_VF16_M2_MASK, PseudoVMFGE_VF16_M2, PseudoVMFGE_VF16_M2_MASK, 0x3 }, // 872
{ PseudoVMFGE_VF16_M4_MASK, PseudoVMFGE_VF16_M4, PseudoVMFGE_VF16_M4_MASK, 0x3 }, // 873
{ PseudoVMFGE_VF16_M8_MASK, PseudoVMFGE_VF16_M8, PseudoVMFGE_VF16_M8_MASK, 0x3 }, // 874
{ PseudoVMFGE_VF16_MF2_MASK, PseudoVMFGE_VF16_MF2, PseudoVMFGE_VF16_MF2_MASK, 0x3 }, // 875
{ PseudoVMFGE_VF16_MF4_MASK, PseudoVMFGE_VF16_MF4, PseudoVMFGE_VF16_MF4_MASK, 0x3 }, // 876
{ PseudoVMFGE_VF32_M1_MASK, PseudoVMFGE_VF32_M1, PseudoVMFGE_VF32_M1_MASK, 0x3 }, // 877
{ PseudoVMFGE_VF32_M2_MASK, PseudoVMFGE_VF32_M2, PseudoVMFGE_VF32_M2_MASK, 0x3 }, // 878
{ PseudoVMFGE_VF32_M4_MASK, PseudoVMFGE_VF32_M4, PseudoVMFGE_VF32_M4_MASK, 0x3 }, // 879
{ PseudoVMFGE_VF32_M8_MASK, PseudoVMFGE_VF32_M8, PseudoVMFGE_VF32_M8_MASK, 0x3 }, // 880
{ PseudoVMFGE_VF32_MF2_MASK, PseudoVMFGE_VF32_MF2, PseudoVMFGE_VF32_MF2_MASK, 0x3 }, // 881
{ PseudoVMFGE_VF64_M1_MASK, PseudoVMFGE_VF64_M1, PseudoVMFGE_VF64_M1_MASK, 0x3 }, // 882
{ PseudoVMFGE_VF64_M2_MASK, PseudoVMFGE_VF64_M2, PseudoVMFGE_VF64_M2_MASK, 0x3 }, // 883
{ PseudoVMFGE_VF64_M4_MASK, PseudoVMFGE_VF64_M4, PseudoVMFGE_VF64_M4_MASK, 0x3 }, // 884
{ PseudoVMFGE_VF64_M8_MASK, PseudoVMFGE_VF64_M8, PseudoVMFGE_VF64_M8_MASK, 0x3 }, // 885
{ PseudoVMFGT_VF16_M1_MASK, PseudoVMFGT_VF16_M1, PseudoVMFGT_VF16_M1_MASK, 0x3 }, // 886
{ PseudoVMFGT_VF16_M2_MASK, PseudoVMFGT_VF16_M2, PseudoVMFGT_VF16_M2_MASK, 0x3 }, // 887
{ PseudoVMFGT_VF16_M4_MASK, PseudoVMFGT_VF16_M4, PseudoVMFGT_VF16_M4_MASK, 0x3 }, // 888
{ PseudoVMFGT_VF16_M8_MASK, PseudoVMFGT_VF16_M8, PseudoVMFGT_VF16_M8_MASK, 0x3 }, // 889
{ PseudoVMFGT_VF16_MF2_MASK, PseudoVMFGT_VF16_MF2, PseudoVMFGT_VF16_MF2_MASK, 0x3 }, // 890
{ PseudoVMFGT_VF16_MF4_MASK, PseudoVMFGT_VF16_MF4, PseudoVMFGT_VF16_MF4_MASK, 0x3 }, // 891
{ PseudoVMFGT_VF32_M1_MASK, PseudoVMFGT_VF32_M1, PseudoVMFGT_VF32_M1_MASK, 0x3 }, // 892
{ PseudoVMFGT_VF32_M2_MASK, PseudoVMFGT_VF32_M2, PseudoVMFGT_VF32_M2_MASK, 0x3 }, // 893
{ PseudoVMFGT_VF32_M4_MASK, PseudoVMFGT_VF32_M4, PseudoVMFGT_VF32_M4_MASK, 0x3 }, // 894
{ PseudoVMFGT_VF32_M8_MASK, PseudoVMFGT_VF32_M8, PseudoVMFGT_VF32_M8_MASK, 0x3 }, // 895
{ PseudoVMFGT_VF32_MF2_MASK, PseudoVMFGT_VF32_MF2, PseudoVMFGT_VF32_MF2_MASK, 0x3 }, // 896
{ PseudoVMFGT_VF64_M1_MASK, PseudoVMFGT_VF64_M1, PseudoVMFGT_VF64_M1_MASK, 0x3 }, // 897
{ PseudoVMFGT_VF64_M2_MASK, PseudoVMFGT_VF64_M2, PseudoVMFGT_VF64_M2_MASK, 0x3 }, // 898
{ PseudoVMFGT_VF64_M4_MASK, PseudoVMFGT_VF64_M4, PseudoVMFGT_VF64_M4_MASK, 0x3 }, // 899
{ PseudoVMFGT_VF64_M8_MASK, PseudoVMFGT_VF64_M8, PseudoVMFGT_VF64_M8_MASK, 0x3 }, // 900
{ PseudoVMFLE_VF16_M1_MASK, PseudoVMFLE_VF16_M1, PseudoVMFLE_VF16_M1_MASK, 0x3 }, // 901
{ PseudoVMFLE_VF16_M2_MASK, PseudoVMFLE_VF16_M2, PseudoVMFLE_VF16_M2_MASK, 0x3 }, // 902
{ PseudoVMFLE_VF16_M4_MASK, PseudoVMFLE_VF16_M4, PseudoVMFLE_VF16_M4_MASK, 0x3 }, // 903
{ PseudoVMFLE_VF16_M8_MASK, PseudoVMFLE_VF16_M8, PseudoVMFLE_VF16_M8_MASK, 0x3 }, // 904
{ PseudoVMFLE_VF16_MF2_MASK, PseudoVMFLE_VF16_MF2, PseudoVMFLE_VF16_MF2_MASK, 0x3 }, // 905
{ PseudoVMFLE_VF16_MF4_MASK, PseudoVMFLE_VF16_MF4, PseudoVMFLE_VF16_MF4_MASK, 0x3 }, // 906
{ PseudoVMFLE_VF32_M1_MASK, PseudoVMFLE_VF32_M1, PseudoVMFLE_VF32_M1_MASK, 0x3 }, // 907
{ PseudoVMFLE_VF32_M2_MASK, PseudoVMFLE_VF32_M2, PseudoVMFLE_VF32_M2_MASK, 0x3 }, // 908
{ PseudoVMFLE_VF32_M4_MASK, PseudoVMFLE_VF32_M4, PseudoVMFLE_VF32_M4_MASK, 0x3 }, // 909
{ PseudoVMFLE_VF32_M8_MASK, PseudoVMFLE_VF32_M8, PseudoVMFLE_VF32_M8_MASK, 0x3 }, // 910
{ PseudoVMFLE_VF32_MF2_MASK, PseudoVMFLE_VF32_MF2, PseudoVMFLE_VF32_MF2_MASK, 0x3 }, // 911
{ PseudoVMFLE_VF64_M1_MASK, PseudoVMFLE_VF64_M1, PseudoVMFLE_VF64_M1_MASK, 0x3 }, // 912
{ PseudoVMFLE_VF64_M2_MASK, PseudoVMFLE_VF64_M2, PseudoVMFLE_VF64_M2_MASK, 0x3 }, // 913
{ PseudoVMFLE_VF64_M4_MASK, PseudoVMFLE_VF64_M4, PseudoVMFLE_VF64_M4_MASK, 0x3 }, // 914
{ PseudoVMFLE_VF64_M8_MASK, PseudoVMFLE_VF64_M8, PseudoVMFLE_VF64_M8_MASK, 0x3 }, // 915
{ PseudoVMFLE_VV_M1_MASK, PseudoVMFLE_VV_M1, PseudoVMFLE_VV_M1_MASK, 0x3 }, // 916
{ PseudoVMFLE_VV_M2_MASK, PseudoVMFLE_VV_M2, PseudoVMFLE_VV_M2_MASK, 0x3 }, // 917
{ PseudoVMFLE_VV_M4_MASK, PseudoVMFLE_VV_M4, PseudoVMFLE_VV_M4_MASK, 0x3 }, // 918
{ PseudoVMFLE_VV_M8_MASK, PseudoVMFLE_VV_M8, PseudoVMFLE_VV_M8_MASK, 0x3 }, // 919
{ PseudoVMFLE_VV_MF2_MASK, PseudoVMFLE_VV_MF2, PseudoVMFLE_VV_MF2_MASK, 0x3 }, // 920
{ PseudoVMFLE_VV_MF4_MASK, PseudoVMFLE_VV_MF4, PseudoVMFLE_VV_MF4_MASK, 0x3 }, // 921
{ PseudoVMFLT_VF16_M1_MASK, PseudoVMFLT_VF16_M1, PseudoVMFLT_VF16_M1_MASK, 0x3 }, // 922
{ PseudoVMFLT_VF16_M2_MASK, PseudoVMFLT_VF16_M2, PseudoVMFLT_VF16_M2_MASK, 0x3 }, // 923
{ PseudoVMFLT_VF16_M4_MASK, PseudoVMFLT_VF16_M4, PseudoVMFLT_VF16_M4_MASK, 0x3 }, // 924
{ PseudoVMFLT_VF16_M8_MASK, PseudoVMFLT_VF16_M8, PseudoVMFLT_VF16_M8_MASK, 0x3 }, // 925
{ PseudoVMFLT_VF16_MF2_MASK, PseudoVMFLT_VF16_MF2, PseudoVMFLT_VF16_MF2_MASK, 0x3 }, // 926
{ PseudoVMFLT_VF16_MF4_MASK, PseudoVMFLT_VF16_MF4, PseudoVMFLT_VF16_MF4_MASK, 0x3 }, // 927
{ PseudoVMFLT_VF32_M1_MASK, PseudoVMFLT_VF32_M1, PseudoVMFLT_VF32_M1_MASK, 0x3 }, // 928
{ PseudoVMFLT_VF32_M2_MASK, PseudoVMFLT_VF32_M2, PseudoVMFLT_VF32_M2_MASK, 0x3 }, // 929
{ PseudoVMFLT_VF32_M4_MASK, PseudoVMFLT_VF32_M4, PseudoVMFLT_VF32_M4_MASK, 0x3 }, // 930
{ PseudoVMFLT_VF32_M8_MASK, PseudoVMFLT_VF32_M8, PseudoVMFLT_VF32_M8_MASK, 0x3 }, // 931
{ PseudoVMFLT_VF32_MF2_MASK, PseudoVMFLT_VF32_MF2, PseudoVMFLT_VF32_MF2_MASK, 0x3 }, // 932
{ PseudoVMFLT_VF64_M1_MASK, PseudoVMFLT_VF64_M1, PseudoVMFLT_VF64_M1_MASK, 0x3 }, // 933
{ PseudoVMFLT_VF64_M2_MASK, PseudoVMFLT_VF64_M2, PseudoVMFLT_VF64_M2_MASK, 0x3 }, // 934
{ PseudoVMFLT_VF64_M4_MASK, PseudoVMFLT_VF64_M4, PseudoVMFLT_VF64_M4_MASK, 0x3 }, // 935
{ PseudoVMFLT_VF64_M8_MASK, PseudoVMFLT_VF64_M8, PseudoVMFLT_VF64_M8_MASK, 0x3 }, // 936
{ PseudoVMFLT_VV_M1_MASK, PseudoVMFLT_VV_M1, PseudoVMFLT_VV_M1_MASK, 0x3 }, // 937
{ PseudoVMFLT_VV_M2_MASK, PseudoVMFLT_VV_M2, PseudoVMFLT_VV_M2_MASK, 0x3 }, // 938
{ PseudoVMFLT_VV_M4_MASK, PseudoVMFLT_VV_M4, PseudoVMFLT_VV_M4_MASK, 0x3 }, // 939
{ PseudoVMFLT_VV_M8_MASK, PseudoVMFLT_VV_M8, PseudoVMFLT_VV_M8_MASK, 0x3 }, // 940
{ PseudoVMFLT_VV_MF2_MASK, PseudoVMFLT_VV_MF2, PseudoVMFLT_VV_MF2_MASK, 0x3 }, // 941
{ PseudoVMFLT_VV_MF4_MASK, PseudoVMFLT_VV_MF4, PseudoVMFLT_VV_MF4_MASK, 0x3 }, // 942
{ PseudoVMFNE_VF16_M1_MASK, PseudoVMFNE_VF16_M1, PseudoVMFNE_VF16_M1_MASK, 0x3 }, // 943
{ PseudoVMFNE_VF16_M2_MASK, PseudoVMFNE_VF16_M2, PseudoVMFNE_VF16_M2_MASK, 0x3 }, // 944
{ PseudoVMFNE_VF16_M4_MASK, PseudoVMFNE_VF16_M4, PseudoVMFNE_VF16_M4_MASK, 0x3 }, // 945
{ PseudoVMFNE_VF16_M8_MASK, PseudoVMFNE_VF16_M8, PseudoVMFNE_VF16_M8_MASK, 0x3 }, // 946
{ PseudoVMFNE_VF16_MF2_MASK, PseudoVMFNE_VF16_MF2, PseudoVMFNE_VF16_MF2_MASK, 0x3 }, // 947
{ PseudoVMFNE_VF16_MF4_MASK, PseudoVMFNE_VF16_MF4, PseudoVMFNE_VF16_MF4_MASK, 0x3 }, // 948
{ PseudoVMFNE_VF32_M1_MASK, PseudoVMFNE_VF32_M1, PseudoVMFNE_VF32_M1_MASK, 0x3 }, // 949
{ PseudoVMFNE_VF32_M2_MASK, PseudoVMFNE_VF32_M2, PseudoVMFNE_VF32_M2_MASK, 0x3 }, // 950
{ PseudoVMFNE_VF32_M4_MASK, PseudoVMFNE_VF32_M4, PseudoVMFNE_VF32_M4_MASK, 0x3 }, // 951
{ PseudoVMFNE_VF32_M8_MASK, PseudoVMFNE_VF32_M8, PseudoVMFNE_VF32_M8_MASK, 0x3 }, // 952
{ PseudoVMFNE_VF32_MF2_MASK, PseudoVMFNE_VF32_MF2, PseudoVMFNE_VF32_MF2_MASK, 0x3 }, // 953
{ PseudoVMFNE_VF64_M1_MASK, PseudoVMFNE_VF64_M1, PseudoVMFNE_VF64_M1_MASK, 0x3 }, // 954
{ PseudoVMFNE_VF64_M2_MASK, PseudoVMFNE_VF64_M2, PseudoVMFNE_VF64_M2_MASK, 0x3 }, // 955
{ PseudoVMFNE_VF64_M4_MASK, PseudoVMFNE_VF64_M4, PseudoVMFNE_VF64_M4_MASK, 0x3 }, // 956
{ PseudoVMFNE_VF64_M8_MASK, PseudoVMFNE_VF64_M8, PseudoVMFNE_VF64_M8_MASK, 0x3 }, // 957
{ PseudoVMFNE_VV_M1_MASK, PseudoVMFNE_VV_M1, PseudoVMFNE_VV_M1_MASK, 0x3 }, // 958
{ PseudoVMFNE_VV_M2_MASK, PseudoVMFNE_VV_M2, PseudoVMFNE_VV_M2_MASK, 0x3 }, // 959
{ PseudoVMFNE_VV_M4_MASK, PseudoVMFNE_VV_M4, PseudoVMFNE_VV_M4_MASK, 0x3 }, // 960
{ PseudoVMFNE_VV_M8_MASK, PseudoVMFNE_VV_M8, PseudoVMFNE_VV_M8_MASK, 0x3 }, // 961
{ PseudoVMFNE_VV_MF2_MASK, PseudoVMFNE_VV_MF2, PseudoVMFNE_VV_MF2_MASK, 0x3 }, // 962
{ PseudoVMFNE_VV_MF4_MASK, PseudoVMFNE_VV_MF4, PseudoVMFNE_VV_MF4_MASK, 0x3 }, // 963
{ PseudoVMINU_VV_M1_MASK, PseudoVMINU_VV_M1, PseudoVMINU_VV_M1_TU, 0x3 }, // 964
{ PseudoVMINU_VV_M2_MASK, PseudoVMINU_VV_M2, PseudoVMINU_VV_M2_TU, 0x3 }, // 965
{ PseudoVMINU_VV_M4_MASK, PseudoVMINU_VV_M4, PseudoVMINU_VV_M4_TU, 0x3 }, // 966
{ PseudoVMINU_VV_M8_MASK, PseudoVMINU_VV_M8, PseudoVMINU_VV_M8_TU, 0x3 }, // 967
{ PseudoVMINU_VV_MF2_MASK, PseudoVMINU_VV_MF2, PseudoVMINU_VV_MF2_TU, 0x3 }, // 968
{ PseudoVMINU_VV_MF4_MASK, PseudoVMINU_VV_MF4, PseudoVMINU_VV_MF4_TU, 0x3 }, // 969
{ PseudoVMINU_VV_MF8_MASK, PseudoVMINU_VV_MF8, PseudoVMINU_VV_MF8_TU, 0x3 }, // 970
{ PseudoVMINU_VX_M1_MASK, PseudoVMINU_VX_M1, PseudoVMINU_VX_M1_TU, 0x3 }, // 971
{ PseudoVMINU_VX_M2_MASK, PseudoVMINU_VX_M2, PseudoVMINU_VX_M2_TU, 0x3 }, // 972
{ PseudoVMINU_VX_M4_MASK, PseudoVMINU_VX_M4, PseudoVMINU_VX_M4_TU, 0x3 }, // 973
{ PseudoVMINU_VX_M8_MASK, PseudoVMINU_VX_M8, PseudoVMINU_VX_M8_TU, 0x3 }, // 974
{ PseudoVMINU_VX_MF2_MASK, PseudoVMINU_VX_MF2, PseudoVMINU_VX_MF2_TU, 0x3 }, // 975
{ PseudoVMINU_VX_MF4_MASK, PseudoVMINU_VX_MF4, PseudoVMINU_VX_MF4_TU, 0x3 }, // 976
{ PseudoVMINU_VX_MF8_MASK, PseudoVMINU_VX_MF8, PseudoVMINU_VX_MF8_TU, 0x3 }, // 977
{ PseudoVMIN_VV_M1_MASK, PseudoVMIN_VV_M1, PseudoVMIN_VV_M1_TU, 0x3 }, // 978
{ PseudoVMIN_VV_M2_MASK, PseudoVMIN_VV_M2, PseudoVMIN_VV_M2_TU, 0x3 }, // 979
{ PseudoVMIN_VV_M4_MASK, PseudoVMIN_VV_M4, PseudoVMIN_VV_M4_TU, 0x3 }, // 980
{ PseudoVMIN_VV_M8_MASK, PseudoVMIN_VV_M8, PseudoVMIN_VV_M8_TU, 0x3 }, // 981
{ PseudoVMIN_VV_MF2_MASK, PseudoVMIN_VV_MF2, PseudoVMIN_VV_MF2_TU, 0x3 }, // 982
{ PseudoVMIN_VV_MF4_MASK, PseudoVMIN_VV_MF4, PseudoVMIN_VV_MF4_TU, 0x3 }, // 983
{ PseudoVMIN_VV_MF8_MASK, PseudoVMIN_VV_MF8, PseudoVMIN_VV_MF8_TU, 0x3 }, // 984
{ PseudoVMIN_VX_M1_MASK, PseudoVMIN_VX_M1, PseudoVMIN_VX_M1_TU, 0x3 }, // 985
{ PseudoVMIN_VX_M2_MASK, PseudoVMIN_VX_M2, PseudoVMIN_VX_M2_TU, 0x3 }, // 986
{ PseudoVMIN_VX_M4_MASK, PseudoVMIN_VX_M4, PseudoVMIN_VX_M4_TU, 0x3 }, // 987
{ PseudoVMIN_VX_M8_MASK, PseudoVMIN_VX_M8, PseudoVMIN_VX_M8_TU, 0x3 }, // 988
{ PseudoVMIN_VX_MF2_MASK, PseudoVMIN_VX_MF2, PseudoVMIN_VX_MF2_TU, 0x3 }, // 989
{ PseudoVMIN_VX_MF4_MASK, PseudoVMIN_VX_MF4, PseudoVMIN_VX_MF4_TU, 0x3 }, // 990
{ PseudoVMIN_VX_MF8_MASK, PseudoVMIN_VX_MF8, PseudoVMIN_VX_MF8_TU, 0x3 }, // 991
{ PseudoVMSEQ_VI_M1_MASK, PseudoVMSEQ_VI_M1, PseudoVMSEQ_VI_M1_MASK, 0x3 }, // 992
{ PseudoVMSEQ_VI_M2_MASK, PseudoVMSEQ_VI_M2, PseudoVMSEQ_VI_M2_MASK, 0x3 }, // 993
{ PseudoVMSEQ_VI_M4_MASK, PseudoVMSEQ_VI_M4, PseudoVMSEQ_VI_M4_MASK, 0x3 }, // 994
{ PseudoVMSEQ_VI_M8_MASK, PseudoVMSEQ_VI_M8, PseudoVMSEQ_VI_M8_MASK, 0x3 }, // 995
{ PseudoVMSEQ_VI_MF2_MASK, PseudoVMSEQ_VI_MF2, PseudoVMSEQ_VI_MF2_MASK, 0x3 }, // 996
{ PseudoVMSEQ_VI_MF4_MASK, PseudoVMSEQ_VI_MF4, PseudoVMSEQ_VI_MF4_MASK, 0x3 }, // 997
{ PseudoVMSEQ_VI_MF8_MASK, PseudoVMSEQ_VI_MF8, PseudoVMSEQ_VI_MF8_MASK, 0x3 }, // 998
{ PseudoVMSEQ_VV_M1_MASK, PseudoVMSEQ_VV_M1, PseudoVMSEQ_VV_M1_MASK, 0x3 }, // 999
{ PseudoVMSEQ_VV_M2_MASK, PseudoVMSEQ_VV_M2, PseudoVMSEQ_VV_M2_MASK, 0x3 }, // 1000
{ PseudoVMSEQ_VV_M4_MASK, PseudoVMSEQ_VV_M4, PseudoVMSEQ_VV_M4_MASK, 0x3 }, // 1001
{ PseudoVMSEQ_VV_M8_MASK, PseudoVMSEQ_VV_M8, PseudoVMSEQ_VV_M8_MASK, 0x3 }, // 1002
{ PseudoVMSEQ_VV_MF2_MASK, PseudoVMSEQ_VV_MF2, PseudoVMSEQ_VV_MF2_MASK, 0x3 }, // 1003
{ PseudoVMSEQ_VV_MF4_MASK, PseudoVMSEQ_VV_MF4, PseudoVMSEQ_VV_MF4_MASK, 0x3 }, // 1004
{ PseudoVMSEQ_VV_MF8_MASK, PseudoVMSEQ_VV_MF8, PseudoVMSEQ_VV_MF8_MASK, 0x3 }, // 1005
{ PseudoVMSEQ_VX_M1_MASK, PseudoVMSEQ_VX_M1, PseudoVMSEQ_VX_M1_MASK, 0x3 }, // 1006
{ PseudoVMSEQ_VX_M2_MASK, PseudoVMSEQ_VX_M2, PseudoVMSEQ_VX_M2_MASK, 0x3 }, // 1007
{ PseudoVMSEQ_VX_M4_MASK, PseudoVMSEQ_VX_M4, PseudoVMSEQ_VX_M4_MASK, 0x3 }, // 1008
{ PseudoVMSEQ_VX_M8_MASK, PseudoVMSEQ_VX_M8, PseudoVMSEQ_VX_M8_MASK, 0x3 }, // 1009
{ PseudoVMSEQ_VX_MF2_MASK, PseudoVMSEQ_VX_MF2, PseudoVMSEQ_VX_MF2_MASK, 0x3 }, // 1010
{ PseudoVMSEQ_VX_MF4_MASK, PseudoVMSEQ_VX_MF4, PseudoVMSEQ_VX_MF4_MASK, 0x3 }, // 1011
{ PseudoVMSEQ_VX_MF8_MASK, PseudoVMSEQ_VX_MF8, PseudoVMSEQ_VX_MF8_MASK, 0x3 }, // 1012
{ PseudoVMSGTU_VI_M1_MASK, PseudoVMSGTU_VI_M1, PseudoVMSGTU_VI_M1_MASK, 0x3 }, // 1013
{ PseudoVMSGTU_VI_M2_MASK, PseudoVMSGTU_VI_M2, PseudoVMSGTU_VI_M2_MASK, 0x3 }, // 1014
{ PseudoVMSGTU_VI_M4_MASK, PseudoVMSGTU_VI_M4, PseudoVMSGTU_VI_M4_MASK, 0x3 }, // 1015
{ PseudoVMSGTU_VI_M8_MASK, PseudoVMSGTU_VI_M8, PseudoVMSGTU_VI_M8_MASK, 0x3 }, // 1016
{ PseudoVMSGTU_VI_MF2_MASK, PseudoVMSGTU_VI_MF2, PseudoVMSGTU_VI_MF2_MASK, 0x3 }, // 1017
{ PseudoVMSGTU_VI_MF4_MASK, PseudoVMSGTU_VI_MF4, PseudoVMSGTU_VI_MF4_MASK, 0x3 }, // 1018
{ PseudoVMSGTU_VI_MF8_MASK, PseudoVMSGTU_VI_MF8, PseudoVMSGTU_VI_MF8_MASK, 0x3 }, // 1019
{ PseudoVMSGTU_VX_M1_MASK, PseudoVMSGTU_VX_M1, PseudoVMSGTU_VX_M1_MASK, 0x3 }, // 1020
{ PseudoVMSGTU_VX_M2_MASK, PseudoVMSGTU_VX_M2, PseudoVMSGTU_VX_M2_MASK, 0x3 }, // 1021
{ PseudoVMSGTU_VX_M4_MASK, PseudoVMSGTU_VX_M4, PseudoVMSGTU_VX_M4_MASK, 0x3 }, // 1022
{ PseudoVMSGTU_VX_M8_MASK, PseudoVMSGTU_VX_M8, PseudoVMSGTU_VX_M8_MASK, 0x3 }, // 1023
{ PseudoVMSGTU_VX_MF2_MASK, PseudoVMSGTU_VX_MF2, PseudoVMSGTU_VX_MF2_MASK, 0x3 }, // 1024
{ PseudoVMSGTU_VX_MF4_MASK, PseudoVMSGTU_VX_MF4, PseudoVMSGTU_VX_MF4_MASK, 0x3 }, // 1025
{ PseudoVMSGTU_VX_MF8_MASK, PseudoVMSGTU_VX_MF8, PseudoVMSGTU_VX_MF8_MASK, 0x3 }, // 1026
{ PseudoVMSGT_VI_M1_MASK, PseudoVMSGT_VI_M1, PseudoVMSGT_VI_M1_MASK, 0x3 }, // 1027
{ PseudoVMSGT_VI_M2_MASK, PseudoVMSGT_VI_M2, PseudoVMSGT_VI_M2_MASK, 0x3 }, // 1028
{ PseudoVMSGT_VI_M4_MASK, PseudoVMSGT_VI_M4, PseudoVMSGT_VI_M4_MASK, 0x3 }, // 1029
{ PseudoVMSGT_VI_M8_MASK, PseudoVMSGT_VI_M8, PseudoVMSGT_VI_M8_MASK, 0x3 }, // 1030
{ PseudoVMSGT_VI_MF2_MASK, PseudoVMSGT_VI_MF2, PseudoVMSGT_VI_MF2_MASK, 0x3 }, // 1031
{ PseudoVMSGT_VI_MF4_MASK, PseudoVMSGT_VI_MF4, PseudoVMSGT_VI_MF4_MASK, 0x3 }, // 1032
{ PseudoVMSGT_VI_MF8_MASK, PseudoVMSGT_VI_MF8, PseudoVMSGT_VI_MF8_MASK, 0x3 }, // 1033
{ PseudoVMSGT_VX_M1_MASK, PseudoVMSGT_VX_M1, PseudoVMSGT_VX_M1_MASK, 0x3 }, // 1034
{ PseudoVMSGT_VX_M2_MASK, PseudoVMSGT_VX_M2, PseudoVMSGT_VX_M2_MASK, 0x3 }, // 1035
{ PseudoVMSGT_VX_M4_MASK, PseudoVMSGT_VX_M4, PseudoVMSGT_VX_M4_MASK, 0x3 }, // 1036
{ PseudoVMSGT_VX_M8_MASK, PseudoVMSGT_VX_M8, PseudoVMSGT_VX_M8_MASK, 0x3 }, // 1037
{ PseudoVMSGT_VX_MF2_MASK, PseudoVMSGT_VX_MF2, PseudoVMSGT_VX_MF2_MASK, 0x3 }, // 1038
{ PseudoVMSGT_VX_MF4_MASK, PseudoVMSGT_VX_MF4, PseudoVMSGT_VX_MF4_MASK, 0x3 }, // 1039
{ PseudoVMSGT_VX_MF8_MASK, PseudoVMSGT_VX_MF8, PseudoVMSGT_VX_MF8_MASK, 0x3 }, // 1040
{ PseudoVMSLEU_VI_M1_MASK, PseudoVMSLEU_VI_M1, PseudoVMSLEU_VI_M1_MASK, 0x3 }, // 1041
{ PseudoVMSLEU_VI_M2_MASK, PseudoVMSLEU_VI_M2, PseudoVMSLEU_VI_M2_MASK, 0x3 }, // 1042
{ PseudoVMSLEU_VI_M4_MASK, PseudoVMSLEU_VI_M4, PseudoVMSLEU_VI_M4_MASK, 0x3 }, // 1043
{ PseudoVMSLEU_VI_M8_MASK, PseudoVMSLEU_VI_M8, PseudoVMSLEU_VI_M8_MASK, 0x3 }, // 1044
{ PseudoVMSLEU_VI_MF2_MASK, PseudoVMSLEU_VI_MF2, PseudoVMSLEU_VI_MF2_MASK, 0x3 }, // 1045
{ PseudoVMSLEU_VI_MF4_MASK, PseudoVMSLEU_VI_MF4, PseudoVMSLEU_VI_MF4_MASK, 0x3 }, // 1046
{ PseudoVMSLEU_VI_MF8_MASK, PseudoVMSLEU_VI_MF8, PseudoVMSLEU_VI_MF8_MASK, 0x3 }, // 1047
{ PseudoVMSLEU_VV_M1_MASK, PseudoVMSLEU_VV_M1, PseudoVMSLEU_VV_M1_MASK, 0x3 }, // 1048
{ PseudoVMSLEU_VV_M2_MASK, PseudoVMSLEU_VV_M2, PseudoVMSLEU_VV_M2_MASK, 0x3 }, // 1049
{ PseudoVMSLEU_VV_M4_MASK, PseudoVMSLEU_VV_M4, PseudoVMSLEU_VV_M4_MASK, 0x3 }, // 1050
{ PseudoVMSLEU_VV_M8_MASK, PseudoVMSLEU_VV_M8, PseudoVMSLEU_VV_M8_MASK, 0x3 }, // 1051
{ PseudoVMSLEU_VV_MF2_MASK, PseudoVMSLEU_VV_MF2, PseudoVMSLEU_VV_MF2_MASK, 0x3 }, // 1052
{ PseudoVMSLEU_VV_MF4_MASK, PseudoVMSLEU_VV_MF4, PseudoVMSLEU_VV_MF4_MASK, 0x3 }, // 1053
{ PseudoVMSLEU_VV_MF8_MASK, PseudoVMSLEU_VV_MF8, PseudoVMSLEU_VV_MF8_MASK, 0x3 }, // 1054
{ PseudoVMSLEU_VX_M1_MASK, PseudoVMSLEU_VX_M1, PseudoVMSLEU_VX_M1_MASK, 0x3 }, // 1055
{ PseudoVMSLEU_VX_M2_MASK, PseudoVMSLEU_VX_M2, PseudoVMSLEU_VX_M2_MASK, 0x3 }, // 1056
{ PseudoVMSLEU_VX_M4_MASK, PseudoVMSLEU_VX_M4, PseudoVMSLEU_VX_M4_MASK, 0x3 }, // 1057
{ PseudoVMSLEU_VX_M8_MASK, PseudoVMSLEU_VX_M8, PseudoVMSLEU_VX_M8_MASK, 0x3 }, // 1058
{ PseudoVMSLEU_VX_MF2_MASK, PseudoVMSLEU_VX_MF2, PseudoVMSLEU_VX_MF2_MASK, 0x3 }, // 1059
{ PseudoVMSLEU_VX_MF4_MASK, PseudoVMSLEU_VX_MF4, PseudoVMSLEU_VX_MF4_MASK, 0x3 }, // 1060
{ PseudoVMSLEU_VX_MF8_MASK, PseudoVMSLEU_VX_MF8, PseudoVMSLEU_VX_MF8_MASK, 0x3 }, // 1061
{ PseudoVMSLE_VI_M1_MASK, PseudoVMSLE_VI_M1, PseudoVMSLE_VI_M1_MASK, 0x3 }, // 1062
{ PseudoVMSLE_VI_M2_MASK, PseudoVMSLE_VI_M2, PseudoVMSLE_VI_M2_MASK, 0x3 }, // 1063
{ PseudoVMSLE_VI_M4_MASK, PseudoVMSLE_VI_M4, PseudoVMSLE_VI_M4_MASK, 0x3 }, // 1064
{ PseudoVMSLE_VI_M8_MASK, PseudoVMSLE_VI_M8, PseudoVMSLE_VI_M8_MASK, 0x3 }, // 1065
{ PseudoVMSLE_VI_MF2_MASK, PseudoVMSLE_VI_MF2, PseudoVMSLE_VI_MF2_MASK, 0x3 }, // 1066
{ PseudoVMSLE_VI_MF4_MASK, PseudoVMSLE_VI_MF4, PseudoVMSLE_VI_MF4_MASK, 0x3 }, // 1067
{ PseudoVMSLE_VI_MF8_MASK, PseudoVMSLE_VI_MF8, PseudoVMSLE_VI_MF8_MASK, 0x3 }, // 1068
{ PseudoVMSLE_VV_M1_MASK, PseudoVMSLE_VV_M1, PseudoVMSLE_VV_M1_MASK, 0x3 }, // 1069
{ PseudoVMSLE_VV_M2_MASK, PseudoVMSLE_VV_M2, PseudoVMSLE_VV_M2_MASK, 0x3 }, // 1070
{ PseudoVMSLE_VV_M4_MASK, PseudoVMSLE_VV_M4, PseudoVMSLE_VV_M4_MASK, 0x3 }, // 1071
{ PseudoVMSLE_VV_M8_MASK, PseudoVMSLE_VV_M8, PseudoVMSLE_VV_M8_MASK, 0x3 }, // 1072
{ PseudoVMSLE_VV_MF2_MASK, PseudoVMSLE_VV_MF2, PseudoVMSLE_VV_MF2_MASK, 0x3 }, // 1073
{ PseudoVMSLE_VV_MF4_MASK, PseudoVMSLE_VV_MF4, PseudoVMSLE_VV_MF4_MASK, 0x3 }, // 1074
{ PseudoVMSLE_VV_MF8_MASK, PseudoVMSLE_VV_MF8, PseudoVMSLE_VV_MF8_MASK, 0x3 }, // 1075
{ PseudoVMSLE_VX_M1_MASK, PseudoVMSLE_VX_M1, PseudoVMSLE_VX_M1_MASK, 0x3 }, // 1076
{ PseudoVMSLE_VX_M2_MASK, PseudoVMSLE_VX_M2, PseudoVMSLE_VX_M2_MASK, 0x3 }, // 1077
{ PseudoVMSLE_VX_M4_MASK, PseudoVMSLE_VX_M4, PseudoVMSLE_VX_M4_MASK, 0x3 }, // 1078
{ PseudoVMSLE_VX_M8_MASK, PseudoVMSLE_VX_M8, PseudoVMSLE_VX_M8_MASK, 0x3 }, // 1079
{ PseudoVMSLE_VX_MF2_MASK, PseudoVMSLE_VX_MF2, PseudoVMSLE_VX_MF2_MASK, 0x3 }, // 1080
{ PseudoVMSLE_VX_MF4_MASK, PseudoVMSLE_VX_MF4, PseudoVMSLE_VX_MF4_MASK, 0x3 }, // 1081
{ PseudoVMSLE_VX_MF8_MASK, PseudoVMSLE_VX_MF8, PseudoVMSLE_VX_MF8_MASK, 0x3 }, // 1082
{ PseudoVMSLTU_VV_M1_MASK, PseudoVMSLTU_VV_M1, PseudoVMSLTU_VV_M1_MASK, 0x3 }, // 1083
{ PseudoVMSLTU_VV_M2_MASK, PseudoVMSLTU_VV_M2, PseudoVMSLTU_VV_M2_MASK, 0x3 }, // 1084
{ PseudoVMSLTU_VV_M4_MASK, PseudoVMSLTU_VV_M4, PseudoVMSLTU_VV_M4_MASK, 0x3 }, // 1085
{ PseudoVMSLTU_VV_M8_MASK, PseudoVMSLTU_VV_M8, PseudoVMSLTU_VV_M8_MASK, 0x3 }, // 1086
{ PseudoVMSLTU_VV_MF2_MASK, PseudoVMSLTU_VV_MF2, PseudoVMSLTU_VV_MF2_MASK, 0x3 }, // 1087
{ PseudoVMSLTU_VV_MF4_MASK, PseudoVMSLTU_VV_MF4, PseudoVMSLTU_VV_MF4_MASK, 0x3 }, // 1088
{ PseudoVMSLTU_VV_MF8_MASK, PseudoVMSLTU_VV_MF8, PseudoVMSLTU_VV_MF8_MASK, 0x3 }, // 1089
{ PseudoVMSLTU_VX_M1_MASK, PseudoVMSLTU_VX_M1, PseudoVMSLTU_VX_M1_MASK, 0x3 }, // 1090
{ PseudoVMSLTU_VX_M2_MASK, PseudoVMSLTU_VX_M2, PseudoVMSLTU_VX_M2_MASK, 0x3 }, // 1091
{ PseudoVMSLTU_VX_M4_MASK, PseudoVMSLTU_VX_M4, PseudoVMSLTU_VX_M4_MASK, 0x3 }, // 1092
{ PseudoVMSLTU_VX_M8_MASK, PseudoVMSLTU_VX_M8, PseudoVMSLTU_VX_M8_MASK, 0x3 }, // 1093
{ PseudoVMSLTU_VX_MF2_MASK, PseudoVMSLTU_VX_MF2, PseudoVMSLTU_VX_MF2_MASK, 0x3 }, // 1094
{ PseudoVMSLTU_VX_MF4_MASK, PseudoVMSLTU_VX_MF4, PseudoVMSLTU_VX_MF4_MASK, 0x3 }, // 1095
{ PseudoVMSLTU_VX_MF8_MASK, PseudoVMSLTU_VX_MF8, PseudoVMSLTU_VX_MF8_MASK, 0x3 }, // 1096
{ PseudoVMSLT_VV_M1_MASK, PseudoVMSLT_VV_M1, PseudoVMSLT_VV_M1_MASK, 0x3 }, // 1097
{ PseudoVMSLT_VV_M2_MASK, PseudoVMSLT_VV_M2, PseudoVMSLT_VV_M2_MASK, 0x3 }, // 1098
{ PseudoVMSLT_VV_M4_MASK, PseudoVMSLT_VV_M4, PseudoVMSLT_VV_M4_MASK, 0x3 }, // 1099
{ PseudoVMSLT_VV_M8_MASK, PseudoVMSLT_VV_M8, PseudoVMSLT_VV_M8_MASK, 0x3 }, // 1100
{ PseudoVMSLT_VV_MF2_MASK, PseudoVMSLT_VV_MF2, PseudoVMSLT_VV_MF2_MASK, 0x3 }, // 1101
{ PseudoVMSLT_VV_MF4_MASK, PseudoVMSLT_VV_MF4, PseudoVMSLT_VV_MF4_MASK, 0x3 }, // 1102
{ PseudoVMSLT_VV_MF8_MASK, PseudoVMSLT_VV_MF8, PseudoVMSLT_VV_MF8_MASK, 0x3 }, // 1103
{ PseudoVMSLT_VX_M1_MASK, PseudoVMSLT_VX_M1, PseudoVMSLT_VX_M1_MASK, 0x3 }, // 1104
{ PseudoVMSLT_VX_M2_MASK, PseudoVMSLT_VX_M2, PseudoVMSLT_VX_M2_MASK, 0x3 }, // 1105
{ PseudoVMSLT_VX_M4_MASK, PseudoVMSLT_VX_M4, PseudoVMSLT_VX_M4_MASK, 0x3 }, // 1106
{ PseudoVMSLT_VX_M8_MASK, PseudoVMSLT_VX_M8, PseudoVMSLT_VX_M8_MASK, 0x3 }, // 1107
{ PseudoVMSLT_VX_MF2_MASK, PseudoVMSLT_VX_MF2, PseudoVMSLT_VX_MF2_MASK, 0x3 }, // 1108
{ PseudoVMSLT_VX_MF4_MASK, PseudoVMSLT_VX_MF4, PseudoVMSLT_VX_MF4_MASK, 0x3 }, // 1109
{ PseudoVMSLT_VX_MF8_MASK, PseudoVMSLT_VX_MF8, PseudoVMSLT_VX_MF8_MASK, 0x3 }, // 1110
{ PseudoVMSNE_VI_M1_MASK, PseudoVMSNE_VI_M1, PseudoVMSNE_VI_M1_MASK, 0x3 }, // 1111
{ PseudoVMSNE_VI_M2_MASK, PseudoVMSNE_VI_M2, PseudoVMSNE_VI_M2_MASK, 0x3 }, // 1112
{ PseudoVMSNE_VI_M4_MASK, PseudoVMSNE_VI_M4, PseudoVMSNE_VI_M4_MASK, 0x3 }, // 1113
{ PseudoVMSNE_VI_M8_MASK, PseudoVMSNE_VI_M8, PseudoVMSNE_VI_M8_MASK, 0x3 }, // 1114
{ PseudoVMSNE_VI_MF2_MASK, PseudoVMSNE_VI_MF2, PseudoVMSNE_VI_MF2_MASK, 0x3 }, // 1115
{ PseudoVMSNE_VI_MF4_MASK, PseudoVMSNE_VI_MF4, PseudoVMSNE_VI_MF4_MASK, 0x3 }, // 1116
{ PseudoVMSNE_VI_MF8_MASK, PseudoVMSNE_VI_MF8, PseudoVMSNE_VI_MF8_MASK, 0x3 }, // 1117
{ PseudoVMSNE_VV_M1_MASK, PseudoVMSNE_VV_M1, PseudoVMSNE_VV_M1_MASK, 0x3 }, // 1118
{ PseudoVMSNE_VV_M2_MASK, PseudoVMSNE_VV_M2, PseudoVMSNE_VV_M2_MASK, 0x3 }, // 1119
{ PseudoVMSNE_VV_M4_MASK, PseudoVMSNE_VV_M4, PseudoVMSNE_VV_M4_MASK, 0x3 }, // 1120
{ PseudoVMSNE_VV_M8_MASK, PseudoVMSNE_VV_M8, PseudoVMSNE_VV_M8_MASK, 0x3 }, // 1121
{ PseudoVMSNE_VV_MF2_MASK, PseudoVMSNE_VV_MF2, PseudoVMSNE_VV_MF2_MASK, 0x3 }, // 1122
{ PseudoVMSNE_VV_MF4_MASK, PseudoVMSNE_VV_MF4, PseudoVMSNE_VV_MF4_MASK, 0x3 }, // 1123
{ PseudoVMSNE_VV_MF8_MASK, PseudoVMSNE_VV_MF8, PseudoVMSNE_VV_MF8_MASK, 0x3 }, // 1124
{ PseudoVMSNE_VX_M1_MASK, PseudoVMSNE_VX_M1, PseudoVMSNE_VX_M1_MASK, 0x3 }, // 1125
{ PseudoVMSNE_VX_M2_MASK, PseudoVMSNE_VX_M2, PseudoVMSNE_VX_M2_MASK, 0x3 }, // 1126
{ PseudoVMSNE_VX_M4_MASK, PseudoVMSNE_VX_M4, PseudoVMSNE_VX_M4_MASK, 0x3 }, // 1127
{ PseudoVMSNE_VX_M8_MASK, PseudoVMSNE_VX_M8, PseudoVMSNE_VX_M8_MASK, 0x3 }, // 1128
{ PseudoVMSNE_VX_MF2_MASK, PseudoVMSNE_VX_MF2, PseudoVMSNE_VX_MF2_MASK, 0x3 }, // 1129
{ PseudoVMSNE_VX_MF4_MASK, PseudoVMSNE_VX_MF4, PseudoVMSNE_VX_MF4_MASK, 0x3 }, // 1130
{ PseudoVMSNE_VX_MF8_MASK, PseudoVMSNE_VX_MF8, PseudoVMSNE_VX_MF8_MASK, 0x3 }, // 1131
{ PseudoVMULHSU_VV_M1_MASK, PseudoVMULHSU_VV_M1, PseudoVMULHSU_VV_M1_TU, 0x3 }, // 1132
{ PseudoVMULHSU_VV_M2_MASK, PseudoVMULHSU_VV_M2, PseudoVMULHSU_VV_M2_TU, 0x3 }, // 1133
{ PseudoVMULHSU_VV_M4_MASK, PseudoVMULHSU_VV_M4, PseudoVMULHSU_VV_M4_TU, 0x3 }, // 1134
{ PseudoVMULHSU_VV_M8_MASK, PseudoVMULHSU_VV_M8, PseudoVMULHSU_VV_M8_TU, 0x3 }, // 1135
{ PseudoVMULHSU_VV_MF2_MASK, PseudoVMULHSU_VV_MF2, PseudoVMULHSU_VV_MF2_TU, 0x3 }, // 1136
{ PseudoVMULHSU_VV_MF4_MASK, PseudoVMULHSU_VV_MF4, PseudoVMULHSU_VV_MF4_TU, 0x3 }, // 1137
{ PseudoVMULHSU_VV_MF8_MASK, PseudoVMULHSU_VV_MF8, PseudoVMULHSU_VV_MF8_TU, 0x3 }, // 1138
{ PseudoVMULHSU_VX_M1_MASK, PseudoVMULHSU_VX_M1, PseudoVMULHSU_VX_M1_TU, 0x3 }, // 1139
{ PseudoVMULHSU_VX_M2_MASK, PseudoVMULHSU_VX_M2, PseudoVMULHSU_VX_M2_TU, 0x3 }, // 1140
{ PseudoVMULHSU_VX_M4_MASK, PseudoVMULHSU_VX_M4, PseudoVMULHSU_VX_M4_TU, 0x3 }, // 1141
{ PseudoVMULHSU_VX_M8_MASK, PseudoVMULHSU_VX_M8, PseudoVMULHSU_VX_M8_TU, 0x3 }, // 1142
{ PseudoVMULHSU_VX_MF2_MASK, PseudoVMULHSU_VX_MF2, PseudoVMULHSU_VX_MF2_TU, 0x3 }, // 1143
{ PseudoVMULHSU_VX_MF4_MASK, PseudoVMULHSU_VX_MF4, PseudoVMULHSU_VX_MF4_TU, 0x3 }, // 1144
{ PseudoVMULHSU_VX_MF8_MASK, PseudoVMULHSU_VX_MF8, PseudoVMULHSU_VX_MF8_TU, 0x3 }, // 1145
{ PseudoVMULHU_VV_M1_MASK, PseudoVMULHU_VV_M1, PseudoVMULHU_VV_M1_TU, 0x3 }, // 1146
{ PseudoVMULHU_VV_M2_MASK, PseudoVMULHU_VV_M2, PseudoVMULHU_VV_M2_TU, 0x3 }, // 1147
{ PseudoVMULHU_VV_M4_MASK, PseudoVMULHU_VV_M4, PseudoVMULHU_VV_M4_TU, 0x3 }, // 1148
{ PseudoVMULHU_VV_M8_MASK, PseudoVMULHU_VV_M8, PseudoVMULHU_VV_M8_TU, 0x3 }, // 1149
{ PseudoVMULHU_VV_MF2_MASK, PseudoVMULHU_VV_MF2, PseudoVMULHU_VV_MF2_TU, 0x3 }, // 1150
{ PseudoVMULHU_VV_MF4_MASK, PseudoVMULHU_VV_MF4, PseudoVMULHU_VV_MF4_TU, 0x3 }, // 1151
{ PseudoVMULHU_VV_MF8_MASK, PseudoVMULHU_VV_MF8, PseudoVMULHU_VV_MF8_TU, 0x3 }, // 1152
{ PseudoVMULHU_VX_M1_MASK, PseudoVMULHU_VX_M1, PseudoVMULHU_VX_M1_TU, 0x3 }, // 1153
{ PseudoVMULHU_VX_M2_MASK, PseudoVMULHU_VX_M2, PseudoVMULHU_VX_M2_TU, 0x3 }, // 1154
{ PseudoVMULHU_VX_M4_MASK, PseudoVMULHU_VX_M4, PseudoVMULHU_VX_M4_TU, 0x3 }, // 1155
{ PseudoVMULHU_VX_M8_MASK, PseudoVMULHU_VX_M8, PseudoVMULHU_VX_M8_TU, 0x3 }, // 1156
{ PseudoVMULHU_VX_MF2_MASK, PseudoVMULHU_VX_MF2, PseudoVMULHU_VX_MF2_TU, 0x3 }, // 1157
{ PseudoVMULHU_VX_MF4_MASK, PseudoVMULHU_VX_MF4, PseudoVMULHU_VX_MF4_TU, 0x3 }, // 1158
{ PseudoVMULHU_VX_MF8_MASK, PseudoVMULHU_VX_MF8, PseudoVMULHU_VX_MF8_TU, 0x3 }, // 1159
{ PseudoVMULH_VV_M1_MASK, PseudoVMULH_VV_M1, PseudoVMULH_VV_M1_TU, 0x3 }, // 1160
{ PseudoVMULH_VV_M2_MASK, PseudoVMULH_VV_M2, PseudoVMULH_VV_M2_TU, 0x3 }, // 1161
{ PseudoVMULH_VV_M4_MASK, PseudoVMULH_VV_M4, PseudoVMULH_VV_M4_TU, 0x3 }, // 1162
{ PseudoVMULH_VV_M8_MASK, PseudoVMULH_VV_M8, PseudoVMULH_VV_M8_TU, 0x3 }, // 1163
{ PseudoVMULH_VV_MF2_MASK, PseudoVMULH_VV_MF2, PseudoVMULH_VV_MF2_TU, 0x3 }, // 1164
{ PseudoVMULH_VV_MF4_MASK, PseudoVMULH_VV_MF4, PseudoVMULH_VV_MF4_TU, 0x3 }, // 1165
{ PseudoVMULH_VV_MF8_MASK, PseudoVMULH_VV_MF8, PseudoVMULH_VV_MF8_TU, 0x3 }, // 1166
{ PseudoVMULH_VX_M1_MASK, PseudoVMULH_VX_M1, PseudoVMULH_VX_M1_TU, 0x3 }, // 1167
{ PseudoVMULH_VX_M2_MASK, PseudoVMULH_VX_M2, PseudoVMULH_VX_M2_TU, 0x3 }, // 1168
{ PseudoVMULH_VX_M4_MASK, PseudoVMULH_VX_M4, PseudoVMULH_VX_M4_TU, 0x3 }, // 1169
{ PseudoVMULH_VX_M8_MASK, PseudoVMULH_VX_M8, PseudoVMULH_VX_M8_TU, 0x3 }, // 1170
{ PseudoVMULH_VX_MF2_MASK, PseudoVMULH_VX_MF2, PseudoVMULH_VX_MF2_TU, 0x3 }, // 1171
{ PseudoVMULH_VX_MF4_MASK, PseudoVMULH_VX_MF4, PseudoVMULH_VX_MF4_TU, 0x3 }, // 1172
{ PseudoVMULH_VX_MF8_MASK, PseudoVMULH_VX_MF8, PseudoVMULH_VX_MF8_TU, 0x3 }, // 1173
{ PseudoVMUL_VV_M1_MASK, PseudoVMUL_VV_M1, PseudoVMUL_VV_M1_TU, 0x3 }, // 1174
{ PseudoVMUL_VV_M2_MASK, PseudoVMUL_VV_M2, PseudoVMUL_VV_M2_TU, 0x3 }, // 1175
{ PseudoVMUL_VV_M4_MASK, PseudoVMUL_VV_M4, PseudoVMUL_VV_M4_TU, 0x3 }, // 1176
{ PseudoVMUL_VV_M8_MASK, PseudoVMUL_VV_M8, PseudoVMUL_VV_M8_TU, 0x3 }, // 1177
{ PseudoVMUL_VV_MF2_MASK, PseudoVMUL_VV_MF2, PseudoVMUL_VV_MF2_TU, 0x3 }, // 1178
{ PseudoVMUL_VV_MF4_MASK, PseudoVMUL_VV_MF4, PseudoVMUL_VV_MF4_TU, 0x3 }, // 1179
{ PseudoVMUL_VV_MF8_MASK, PseudoVMUL_VV_MF8, PseudoVMUL_VV_MF8_TU, 0x3 }, // 1180
{ PseudoVMUL_VX_M1_MASK, PseudoVMUL_VX_M1, PseudoVMUL_VX_M1_TU, 0x3 }, // 1181
{ PseudoVMUL_VX_M2_MASK, PseudoVMUL_VX_M2, PseudoVMUL_VX_M2_TU, 0x3 }, // 1182
{ PseudoVMUL_VX_M4_MASK, PseudoVMUL_VX_M4, PseudoVMUL_VX_M4_TU, 0x3 }, // 1183
{ PseudoVMUL_VX_M8_MASK, PseudoVMUL_VX_M8, PseudoVMUL_VX_M8_TU, 0x3 }, // 1184
{ PseudoVMUL_VX_MF2_MASK, PseudoVMUL_VX_MF2, PseudoVMUL_VX_MF2_TU, 0x3 }, // 1185
{ PseudoVMUL_VX_MF4_MASK, PseudoVMUL_VX_MF4, PseudoVMUL_VX_MF4_TU, 0x3 }, // 1186
{ PseudoVMUL_VX_MF8_MASK, PseudoVMUL_VX_MF8, PseudoVMUL_VX_MF8_TU, 0x3 }, // 1187
{ PseudoVNCLIPU_WI_M1_MASK, PseudoVNCLIPU_WI_M1, PseudoVNCLIPU_WI_M1_TU, 0x3 }, // 1188
{ PseudoVNCLIPU_WI_M2_MASK, PseudoVNCLIPU_WI_M2, PseudoVNCLIPU_WI_M2_TU, 0x3 }, // 1189
{ PseudoVNCLIPU_WI_M4_MASK, PseudoVNCLIPU_WI_M4, PseudoVNCLIPU_WI_M4_TU, 0x3 }, // 1190
{ PseudoVNCLIPU_WI_MF2_MASK, PseudoVNCLIPU_WI_MF2, PseudoVNCLIPU_WI_MF2_TU, 0x3 }, // 1191
{ PseudoVNCLIPU_WI_MF4_MASK, PseudoVNCLIPU_WI_MF4, PseudoVNCLIPU_WI_MF4_TU, 0x3 }, // 1192
{ PseudoVNCLIPU_WI_MF8_MASK, PseudoVNCLIPU_WI_MF8, PseudoVNCLIPU_WI_MF8_TU, 0x3 }, // 1193
{ PseudoVNCLIPU_WV_M1_MASK, PseudoVNCLIPU_WV_M1, PseudoVNCLIPU_WV_M1_TU, 0x3 }, // 1194
{ PseudoVNCLIPU_WV_M2_MASK, PseudoVNCLIPU_WV_M2, PseudoVNCLIPU_WV_M2_TU, 0x3 }, // 1195
{ PseudoVNCLIPU_WV_M4_MASK, PseudoVNCLIPU_WV_M4, PseudoVNCLIPU_WV_M4_TU, 0x3 }, // 1196
{ PseudoVNCLIPU_WV_MF2_MASK, PseudoVNCLIPU_WV_MF2, PseudoVNCLIPU_WV_MF2_TU, 0x3 }, // 1197
{ PseudoVNCLIPU_WV_MF4_MASK, PseudoVNCLIPU_WV_MF4, PseudoVNCLIPU_WV_MF4_TU, 0x3 }, // 1198
{ PseudoVNCLIPU_WV_MF8_MASK, PseudoVNCLIPU_WV_MF8, PseudoVNCLIPU_WV_MF8_TU, 0x3 }, // 1199
{ PseudoVNCLIPU_WX_M1_MASK, PseudoVNCLIPU_WX_M1, PseudoVNCLIPU_WX_M1_TU, 0x3 }, // 1200
{ PseudoVNCLIPU_WX_M2_MASK, PseudoVNCLIPU_WX_M2, PseudoVNCLIPU_WX_M2_TU, 0x3 }, // 1201
{ PseudoVNCLIPU_WX_M4_MASK, PseudoVNCLIPU_WX_M4, PseudoVNCLIPU_WX_M4_TU, 0x3 }, // 1202
{ PseudoVNCLIPU_WX_MF2_MASK, PseudoVNCLIPU_WX_MF2, PseudoVNCLIPU_WX_MF2_TU, 0x3 }, // 1203
{ PseudoVNCLIPU_WX_MF4_MASK, PseudoVNCLIPU_WX_MF4, PseudoVNCLIPU_WX_MF4_TU, 0x3 }, // 1204
{ PseudoVNCLIPU_WX_MF8_MASK, PseudoVNCLIPU_WX_MF8, PseudoVNCLIPU_WX_MF8_TU, 0x3 }, // 1205
{ PseudoVNCLIP_WI_M1_MASK, PseudoVNCLIP_WI_M1, PseudoVNCLIP_WI_M1_TU, 0x3 }, // 1206
{ PseudoVNCLIP_WI_M2_MASK, PseudoVNCLIP_WI_M2, PseudoVNCLIP_WI_M2_TU, 0x3 }, // 1207
{ PseudoVNCLIP_WI_M4_MASK, PseudoVNCLIP_WI_M4, PseudoVNCLIP_WI_M4_TU, 0x3 }, // 1208
{ PseudoVNCLIP_WI_MF2_MASK, PseudoVNCLIP_WI_MF2, PseudoVNCLIP_WI_MF2_TU, 0x3 }, // 1209
{ PseudoVNCLIP_WI_MF4_MASK, PseudoVNCLIP_WI_MF4, PseudoVNCLIP_WI_MF4_TU, 0x3 }, // 1210
{ PseudoVNCLIP_WI_MF8_MASK, PseudoVNCLIP_WI_MF8, PseudoVNCLIP_WI_MF8_TU, 0x3 }, // 1211
{ PseudoVNCLIP_WV_M1_MASK, PseudoVNCLIP_WV_M1, PseudoVNCLIP_WV_M1_TU, 0x3 }, // 1212
{ PseudoVNCLIP_WV_M2_MASK, PseudoVNCLIP_WV_M2, PseudoVNCLIP_WV_M2_TU, 0x3 }, // 1213
{ PseudoVNCLIP_WV_M4_MASK, PseudoVNCLIP_WV_M4, PseudoVNCLIP_WV_M4_TU, 0x3 }, // 1214
{ PseudoVNCLIP_WV_MF2_MASK, PseudoVNCLIP_WV_MF2, PseudoVNCLIP_WV_MF2_TU, 0x3 }, // 1215
{ PseudoVNCLIP_WV_MF4_MASK, PseudoVNCLIP_WV_MF4, PseudoVNCLIP_WV_MF4_TU, 0x3 }, // 1216
{ PseudoVNCLIP_WV_MF8_MASK, PseudoVNCLIP_WV_MF8, PseudoVNCLIP_WV_MF8_TU, 0x3 }, // 1217
{ PseudoVNCLIP_WX_M1_MASK, PseudoVNCLIP_WX_M1, PseudoVNCLIP_WX_M1_TU, 0x3 }, // 1218
{ PseudoVNCLIP_WX_M2_MASK, PseudoVNCLIP_WX_M2, PseudoVNCLIP_WX_M2_TU, 0x3 }, // 1219
{ PseudoVNCLIP_WX_M4_MASK, PseudoVNCLIP_WX_M4, PseudoVNCLIP_WX_M4_TU, 0x3 }, // 1220
{ PseudoVNCLIP_WX_MF2_MASK, PseudoVNCLIP_WX_MF2, PseudoVNCLIP_WX_MF2_TU, 0x3 }, // 1221
{ PseudoVNCLIP_WX_MF4_MASK, PseudoVNCLIP_WX_MF4, PseudoVNCLIP_WX_MF4_TU, 0x3 }, // 1222
{ PseudoVNCLIP_WX_MF8_MASK, PseudoVNCLIP_WX_MF8, PseudoVNCLIP_WX_MF8_TU, 0x3 }, // 1223
{ PseudoVNSRA_WI_M1_MASK, PseudoVNSRA_WI_M1, PseudoVNSRA_WI_M1_TU, 0x3 }, // 1224
{ PseudoVNSRA_WI_M2_MASK, PseudoVNSRA_WI_M2, PseudoVNSRA_WI_M2_TU, 0x3 }, // 1225
{ PseudoVNSRA_WI_M4_MASK, PseudoVNSRA_WI_M4, PseudoVNSRA_WI_M4_TU, 0x3 }, // 1226
{ PseudoVNSRA_WI_MF2_MASK, PseudoVNSRA_WI_MF2, PseudoVNSRA_WI_MF2_TU, 0x3 }, // 1227
{ PseudoVNSRA_WI_MF4_MASK, PseudoVNSRA_WI_MF4, PseudoVNSRA_WI_MF4_TU, 0x3 }, // 1228
{ PseudoVNSRA_WI_MF8_MASK, PseudoVNSRA_WI_MF8, PseudoVNSRA_WI_MF8_TU, 0x3 }, // 1229
{ PseudoVNSRA_WV_M1_MASK, PseudoVNSRA_WV_M1, PseudoVNSRA_WV_M1_TU, 0x3 }, // 1230
{ PseudoVNSRA_WV_M2_MASK, PseudoVNSRA_WV_M2, PseudoVNSRA_WV_M2_TU, 0x3 }, // 1231
{ PseudoVNSRA_WV_M4_MASK, PseudoVNSRA_WV_M4, PseudoVNSRA_WV_M4_TU, 0x3 }, // 1232
{ PseudoVNSRA_WV_MF2_MASK, PseudoVNSRA_WV_MF2, PseudoVNSRA_WV_MF2_TU, 0x3 }, // 1233
{ PseudoVNSRA_WV_MF4_MASK, PseudoVNSRA_WV_MF4, PseudoVNSRA_WV_MF4_TU, 0x3 }, // 1234
{ PseudoVNSRA_WV_MF8_MASK, PseudoVNSRA_WV_MF8, PseudoVNSRA_WV_MF8_TU, 0x3 }, // 1235
{ PseudoVNSRA_WX_M1_MASK, PseudoVNSRA_WX_M1, PseudoVNSRA_WX_M1_TU, 0x3 }, // 1236
{ PseudoVNSRA_WX_M2_MASK, PseudoVNSRA_WX_M2, PseudoVNSRA_WX_M2_TU, 0x3 }, // 1237
{ PseudoVNSRA_WX_M4_MASK, PseudoVNSRA_WX_M4, PseudoVNSRA_WX_M4_TU, 0x3 }, // 1238
{ PseudoVNSRA_WX_MF2_MASK, PseudoVNSRA_WX_MF2, PseudoVNSRA_WX_MF2_TU, 0x3 }, // 1239
{ PseudoVNSRA_WX_MF4_MASK, PseudoVNSRA_WX_MF4, PseudoVNSRA_WX_MF4_TU, 0x3 }, // 1240
{ PseudoVNSRA_WX_MF8_MASK, PseudoVNSRA_WX_MF8, PseudoVNSRA_WX_MF8_TU, 0x3 }, // 1241
{ PseudoVNSRL_WI_M1_MASK, PseudoVNSRL_WI_M1, PseudoVNSRL_WI_M1_TU, 0x3 }, // 1242
{ PseudoVNSRL_WI_M2_MASK, PseudoVNSRL_WI_M2, PseudoVNSRL_WI_M2_TU, 0x3 }, // 1243
{ PseudoVNSRL_WI_M4_MASK, PseudoVNSRL_WI_M4, PseudoVNSRL_WI_M4_TU, 0x3 }, // 1244
{ PseudoVNSRL_WI_MF2_MASK, PseudoVNSRL_WI_MF2, PseudoVNSRL_WI_MF2_TU, 0x3 }, // 1245
{ PseudoVNSRL_WI_MF4_MASK, PseudoVNSRL_WI_MF4, PseudoVNSRL_WI_MF4_TU, 0x3 }, // 1246
{ PseudoVNSRL_WI_MF8_MASK, PseudoVNSRL_WI_MF8, PseudoVNSRL_WI_MF8_TU, 0x3 }, // 1247
{ PseudoVNSRL_WV_M1_MASK, PseudoVNSRL_WV_M1, PseudoVNSRL_WV_M1_TU, 0x3 }, // 1248
{ PseudoVNSRL_WV_M2_MASK, PseudoVNSRL_WV_M2, PseudoVNSRL_WV_M2_TU, 0x3 }, // 1249
{ PseudoVNSRL_WV_M4_MASK, PseudoVNSRL_WV_M4, PseudoVNSRL_WV_M4_TU, 0x3 }, // 1250
{ PseudoVNSRL_WV_MF2_MASK, PseudoVNSRL_WV_MF2, PseudoVNSRL_WV_MF2_TU, 0x3 }, // 1251
{ PseudoVNSRL_WV_MF4_MASK, PseudoVNSRL_WV_MF4, PseudoVNSRL_WV_MF4_TU, 0x3 }, // 1252
{ PseudoVNSRL_WV_MF8_MASK, PseudoVNSRL_WV_MF8, PseudoVNSRL_WV_MF8_TU, 0x3 }, // 1253
{ PseudoVNSRL_WX_M1_MASK, PseudoVNSRL_WX_M1, PseudoVNSRL_WX_M1_TU, 0x3 }, // 1254
{ PseudoVNSRL_WX_M2_MASK, PseudoVNSRL_WX_M2, PseudoVNSRL_WX_M2_TU, 0x3 }, // 1255
{ PseudoVNSRL_WX_M4_MASK, PseudoVNSRL_WX_M4, PseudoVNSRL_WX_M4_TU, 0x3 }, // 1256
{ PseudoVNSRL_WX_MF2_MASK, PseudoVNSRL_WX_MF2, PseudoVNSRL_WX_MF2_TU, 0x3 }, // 1257
{ PseudoVNSRL_WX_MF4_MASK, PseudoVNSRL_WX_MF4, PseudoVNSRL_WX_MF4_TU, 0x3 }, // 1258
{ PseudoVNSRL_WX_MF8_MASK, PseudoVNSRL_WX_MF8, PseudoVNSRL_WX_MF8_TU, 0x3 }, // 1259
{ PseudoVOR_VI_M1_MASK, PseudoVOR_VI_M1, PseudoVOR_VI_M1_TU, 0x3 }, // 1260
{ PseudoVOR_VI_M2_MASK, PseudoVOR_VI_M2, PseudoVOR_VI_M2_TU, 0x3 }, // 1261
{ PseudoVOR_VI_M4_MASK, PseudoVOR_VI_M4, PseudoVOR_VI_M4_TU, 0x3 }, // 1262
{ PseudoVOR_VI_M8_MASK, PseudoVOR_VI_M8, PseudoVOR_VI_M8_TU, 0x3 }, // 1263
{ PseudoVOR_VI_MF2_MASK, PseudoVOR_VI_MF2, PseudoVOR_VI_MF2_TU, 0x3 }, // 1264
{ PseudoVOR_VI_MF4_MASK, PseudoVOR_VI_MF4, PseudoVOR_VI_MF4_TU, 0x3 }, // 1265
{ PseudoVOR_VI_MF8_MASK, PseudoVOR_VI_MF8, PseudoVOR_VI_MF8_TU, 0x3 }, // 1266
{ PseudoVOR_VV_M1_MASK, PseudoVOR_VV_M1, PseudoVOR_VV_M1_TU, 0x3 }, // 1267
{ PseudoVOR_VV_M2_MASK, PseudoVOR_VV_M2, PseudoVOR_VV_M2_TU, 0x3 }, // 1268
{ PseudoVOR_VV_M4_MASK, PseudoVOR_VV_M4, PseudoVOR_VV_M4_TU, 0x3 }, // 1269
{ PseudoVOR_VV_M8_MASK, PseudoVOR_VV_M8, PseudoVOR_VV_M8_TU, 0x3 }, // 1270
{ PseudoVOR_VV_MF2_MASK, PseudoVOR_VV_MF2, PseudoVOR_VV_MF2_TU, 0x3 }, // 1271
{ PseudoVOR_VV_MF4_MASK, PseudoVOR_VV_MF4, PseudoVOR_VV_MF4_TU, 0x3 }, // 1272
{ PseudoVOR_VV_MF8_MASK, PseudoVOR_VV_MF8, PseudoVOR_VV_MF8_TU, 0x3 }, // 1273
{ PseudoVOR_VX_M1_MASK, PseudoVOR_VX_M1, PseudoVOR_VX_M1_TU, 0x3 }, // 1274
{ PseudoVOR_VX_M2_MASK, PseudoVOR_VX_M2, PseudoVOR_VX_M2_TU, 0x3 }, // 1275
{ PseudoVOR_VX_M4_MASK, PseudoVOR_VX_M4, PseudoVOR_VX_M4_TU, 0x3 }, // 1276
{ PseudoVOR_VX_M8_MASK, PseudoVOR_VX_M8, PseudoVOR_VX_M8_TU, 0x3 }, // 1277
{ PseudoVOR_VX_MF2_MASK, PseudoVOR_VX_MF2, PseudoVOR_VX_MF2_TU, 0x3 }, // 1278
{ PseudoVOR_VX_MF4_MASK, PseudoVOR_VX_MF4, PseudoVOR_VX_MF4_TU, 0x3 }, // 1279
{ PseudoVOR_VX_MF8_MASK, PseudoVOR_VX_MF8, PseudoVOR_VX_MF8_TU, 0x3 }, // 1280
{ PseudoVREMU_VV_M1_MASK, PseudoVREMU_VV_M1, PseudoVREMU_VV_M1_TU, 0x3 }, // 1281
{ PseudoVREMU_VV_M2_MASK, PseudoVREMU_VV_M2, PseudoVREMU_VV_M2_TU, 0x3 }, // 1282
{ PseudoVREMU_VV_M4_MASK, PseudoVREMU_VV_M4, PseudoVREMU_VV_M4_TU, 0x3 }, // 1283
{ PseudoVREMU_VV_M8_MASK, PseudoVREMU_VV_M8, PseudoVREMU_VV_M8_TU, 0x3 }, // 1284
{ PseudoVREMU_VV_MF2_MASK, PseudoVREMU_VV_MF2, PseudoVREMU_VV_MF2_TU, 0x3 }, // 1285
{ PseudoVREMU_VV_MF4_MASK, PseudoVREMU_VV_MF4, PseudoVREMU_VV_MF4_TU, 0x3 }, // 1286
{ PseudoVREMU_VV_MF8_MASK, PseudoVREMU_VV_MF8, PseudoVREMU_VV_MF8_TU, 0x3 }, // 1287
{ PseudoVREMU_VX_M1_MASK, PseudoVREMU_VX_M1, PseudoVREMU_VX_M1_TU, 0x3 }, // 1288
{ PseudoVREMU_VX_M2_MASK, PseudoVREMU_VX_M2, PseudoVREMU_VX_M2_TU, 0x3 }, // 1289
{ PseudoVREMU_VX_M4_MASK, PseudoVREMU_VX_M4, PseudoVREMU_VX_M4_TU, 0x3 }, // 1290
{ PseudoVREMU_VX_M8_MASK, PseudoVREMU_VX_M8, PseudoVREMU_VX_M8_TU, 0x3 }, // 1291
{ PseudoVREMU_VX_MF2_MASK, PseudoVREMU_VX_MF2, PseudoVREMU_VX_MF2_TU, 0x3 }, // 1292
{ PseudoVREMU_VX_MF4_MASK, PseudoVREMU_VX_MF4, PseudoVREMU_VX_MF4_TU, 0x3 }, // 1293
{ PseudoVREMU_VX_MF8_MASK, PseudoVREMU_VX_MF8, PseudoVREMU_VX_MF8_TU, 0x3 }, // 1294
{ PseudoVREM_VV_M1_MASK, PseudoVREM_VV_M1, PseudoVREM_VV_M1_TU, 0x3 }, // 1295
{ PseudoVREM_VV_M2_MASK, PseudoVREM_VV_M2, PseudoVREM_VV_M2_TU, 0x3 }, // 1296
{ PseudoVREM_VV_M4_MASK, PseudoVREM_VV_M4, PseudoVREM_VV_M4_TU, 0x3 }, // 1297
{ PseudoVREM_VV_M8_MASK, PseudoVREM_VV_M8, PseudoVREM_VV_M8_TU, 0x3 }, // 1298
{ PseudoVREM_VV_MF2_MASK, PseudoVREM_VV_MF2, PseudoVREM_VV_MF2_TU, 0x3 }, // 1299
{ PseudoVREM_VV_MF4_MASK, PseudoVREM_VV_MF4, PseudoVREM_VV_MF4_TU, 0x3 }, // 1300
{ PseudoVREM_VV_MF8_MASK, PseudoVREM_VV_MF8, PseudoVREM_VV_MF8_TU, 0x3 }, // 1301
{ PseudoVREM_VX_M1_MASK, PseudoVREM_VX_M1, PseudoVREM_VX_M1_TU, 0x3 }, // 1302
{ PseudoVREM_VX_M2_MASK, PseudoVREM_VX_M2, PseudoVREM_VX_M2_TU, 0x3 }, // 1303
{ PseudoVREM_VX_M4_MASK, PseudoVREM_VX_M4, PseudoVREM_VX_M4_TU, 0x3 }, // 1304
{ PseudoVREM_VX_M8_MASK, PseudoVREM_VX_M8, PseudoVREM_VX_M8_TU, 0x3 }, // 1305
{ PseudoVREM_VX_MF2_MASK, PseudoVREM_VX_MF2, PseudoVREM_VX_MF2_TU, 0x3 }, // 1306
{ PseudoVREM_VX_MF4_MASK, PseudoVREM_VX_MF4, PseudoVREM_VX_MF4_TU, 0x3 }, // 1307
{ PseudoVREM_VX_MF8_MASK, PseudoVREM_VX_MF8, PseudoVREM_VX_MF8_TU, 0x3 }, // 1308
{ PseudoVRGATHEREI16_VV_M1_M1_MASK, PseudoVRGATHEREI16_VV_M1_M1, PseudoVRGATHEREI16_VV_M1_M1_TU, 0x3 }, // 1309
{ PseudoVRGATHEREI16_VV_M1_M2_MASK, PseudoVRGATHEREI16_VV_M1_M2, PseudoVRGATHEREI16_VV_M1_M2_TU, 0x3 }, // 1310
{ PseudoVRGATHEREI16_VV_M1_MF2_MASK, PseudoVRGATHEREI16_VV_M1_MF2, PseudoVRGATHEREI16_VV_M1_MF2_TU, 0x3 }, // 1311
{ PseudoVRGATHEREI16_VV_M1_MF4_MASK, PseudoVRGATHEREI16_VV_M1_MF4, PseudoVRGATHEREI16_VV_M1_MF4_TU, 0x3 }, // 1312
{ PseudoVRGATHEREI16_VV_M2_M1_MASK, PseudoVRGATHEREI16_VV_M2_M1, PseudoVRGATHEREI16_VV_M2_M1_TU, 0x3 }, // 1313
{ PseudoVRGATHEREI16_VV_M2_M2_MASK, PseudoVRGATHEREI16_VV_M2_M2, PseudoVRGATHEREI16_VV_M2_M2_TU, 0x3 }, // 1314
{ PseudoVRGATHEREI16_VV_M2_M4_MASK, PseudoVRGATHEREI16_VV_M2_M4, PseudoVRGATHEREI16_VV_M2_M4_TU, 0x3 }, // 1315
{ PseudoVRGATHEREI16_VV_M2_MF2_MASK, PseudoVRGATHEREI16_VV_M2_MF2, PseudoVRGATHEREI16_VV_M2_MF2_TU, 0x3 }, // 1316
{ PseudoVRGATHEREI16_VV_M4_M1_MASK, PseudoVRGATHEREI16_VV_M4_M1, PseudoVRGATHEREI16_VV_M4_M1_TU, 0x3 }, // 1317
{ PseudoVRGATHEREI16_VV_M4_M2_MASK, PseudoVRGATHEREI16_VV_M4_M2, PseudoVRGATHEREI16_VV_M4_M2_TU, 0x3 }, // 1318
{ PseudoVRGATHEREI16_VV_M4_M4_MASK, PseudoVRGATHEREI16_VV_M4_M4, PseudoVRGATHEREI16_VV_M4_M4_TU, 0x3 }, // 1319
{ PseudoVRGATHEREI16_VV_M4_M8_MASK, PseudoVRGATHEREI16_VV_M4_M8, PseudoVRGATHEREI16_VV_M4_M8_TU, 0x3 }, // 1320
{ PseudoVRGATHEREI16_VV_M8_M2_MASK, PseudoVRGATHEREI16_VV_M8_M2, PseudoVRGATHEREI16_VV_M8_M2_TU, 0x3 }, // 1321
{ PseudoVRGATHEREI16_VV_M8_M4_MASK, PseudoVRGATHEREI16_VV_M8_M4, PseudoVRGATHEREI16_VV_M8_M4_TU, 0x3 }, // 1322
{ PseudoVRGATHEREI16_VV_M8_M8_MASK, PseudoVRGATHEREI16_VV_M8_M8, PseudoVRGATHEREI16_VV_M8_M8_TU, 0x3 }, // 1323
{ PseudoVRGATHEREI16_VV_MF2_M1_MASK, PseudoVRGATHEREI16_VV_MF2_M1, PseudoVRGATHEREI16_VV_MF2_M1_TU, 0x3 }, // 1324
{ PseudoVRGATHEREI16_VV_MF2_MF2_MASK, PseudoVRGATHEREI16_VV_MF2_MF2, PseudoVRGATHEREI16_VV_MF2_MF2_TU, 0x3 }, // 1325
{ PseudoVRGATHEREI16_VV_MF2_MF4_MASK, PseudoVRGATHEREI16_VV_MF2_MF4, PseudoVRGATHEREI16_VV_MF2_MF4_TU, 0x3 }, // 1326
{ PseudoVRGATHEREI16_VV_MF2_MF8_MASK, PseudoVRGATHEREI16_VV_MF2_MF8, PseudoVRGATHEREI16_VV_MF2_MF8_TU, 0x3 }, // 1327
{ PseudoVRGATHEREI16_VV_MF4_MF2_MASK, PseudoVRGATHEREI16_VV_MF4_MF2, PseudoVRGATHEREI16_VV_MF4_MF2_TU, 0x3 }, // 1328
{ PseudoVRGATHEREI16_VV_MF4_MF4_MASK, PseudoVRGATHEREI16_VV_MF4_MF4, PseudoVRGATHEREI16_VV_MF4_MF4_TU, 0x3 }, // 1329
{ PseudoVRGATHEREI16_VV_MF4_MF8_MASK, PseudoVRGATHEREI16_VV_MF4_MF8, PseudoVRGATHEREI16_VV_MF4_MF8_TU, 0x3 }, // 1330
{ PseudoVRGATHEREI16_VV_MF8_MF4_MASK, PseudoVRGATHEREI16_VV_MF8_MF4, PseudoVRGATHEREI16_VV_MF8_MF4_TU, 0x3 }, // 1331
{ PseudoVRGATHEREI16_VV_MF8_MF8_MASK, PseudoVRGATHEREI16_VV_MF8_MF8, PseudoVRGATHEREI16_VV_MF8_MF8_TU, 0x3 }, // 1332
{ PseudoVRGATHER_VI_M1_MASK, PseudoVRGATHER_VI_M1, PseudoVRGATHER_VI_M1_TU, 0x3 }, // 1333
{ PseudoVRGATHER_VI_M2_MASK, PseudoVRGATHER_VI_M2, PseudoVRGATHER_VI_M2_TU, 0x3 }, // 1334
{ PseudoVRGATHER_VI_M4_MASK, PseudoVRGATHER_VI_M4, PseudoVRGATHER_VI_M4_TU, 0x3 }, // 1335
{ PseudoVRGATHER_VI_M8_MASK, PseudoVRGATHER_VI_M8, PseudoVRGATHER_VI_M8_TU, 0x3 }, // 1336
{ PseudoVRGATHER_VI_MF2_MASK, PseudoVRGATHER_VI_MF2, PseudoVRGATHER_VI_MF2_TU, 0x3 }, // 1337
{ PseudoVRGATHER_VI_MF4_MASK, PseudoVRGATHER_VI_MF4, PseudoVRGATHER_VI_MF4_TU, 0x3 }, // 1338
{ PseudoVRGATHER_VI_MF8_MASK, PseudoVRGATHER_VI_MF8, PseudoVRGATHER_VI_MF8_TU, 0x3 }, // 1339
{ PseudoVRGATHER_VV_M1_MASK, PseudoVRGATHER_VV_M1, PseudoVRGATHER_VV_M1_TU, 0x3 }, // 1340
{ PseudoVRGATHER_VV_M2_MASK, PseudoVRGATHER_VV_M2, PseudoVRGATHER_VV_M2_TU, 0x3 }, // 1341
{ PseudoVRGATHER_VV_M4_MASK, PseudoVRGATHER_VV_M4, PseudoVRGATHER_VV_M4_TU, 0x3 }, // 1342
{ PseudoVRGATHER_VV_M8_MASK, PseudoVRGATHER_VV_M8, PseudoVRGATHER_VV_M8_TU, 0x3 }, // 1343
{ PseudoVRGATHER_VV_MF2_MASK, PseudoVRGATHER_VV_MF2, PseudoVRGATHER_VV_MF2_TU, 0x3 }, // 1344
{ PseudoVRGATHER_VV_MF4_MASK, PseudoVRGATHER_VV_MF4, PseudoVRGATHER_VV_MF4_TU, 0x3 }, // 1345
{ PseudoVRGATHER_VV_MF8_MASK, PseudoVRGATHER_VV_MF8, PseudoVRGATHER_VV_MF8_TU, 0x3 }, // 1346
{ PseudoVRGATHER_VX_M1_MASK, PseudoVRGATHER_VX_M1, PseudoVRGATHER_VX_M1_TU, 0x3 }, // 1347
{ PseudoVRGATHER_VX_M2_MASK, PseudoVRGATHER_VX_M2, PseudoVRGATHER_VX_M2_TU, 0x3 }, // 1348
{ PseudoVRGATHER_VX_M4_MASK, PseudoVRGATHER_VX_M4, PseudoVRGATHER_VX_M4_TU, 0x3 }, // 1349
{ PseudoVRGATHER_VX_M8_MASK, PseudoVRGATHER_VX_M8, PseudoVRGATHER_VX_M8_TU, 0x3 }, // 1350
{ PseudoVRGATHER_VX_MF2_MASK, PseudoVRGATHER_VX_MF2, PseudoVRGATHER_VX_MF2_TU, 0x3 }, // 1351
{ PseudoVRGATHER_VX_MF4_MASK, PseudoVRGATHER_VX_MF4, PseudoVRGATHER_VX_MF4_TU, 0x3 }, // 1352
{ PseudoVRGATHER_VX_MF8_MASK, PseudoVRGATHER_VX_MF8, PseudoVRGATHER_VX_MF8_TU, 0x3 }, // 1353
{ PseudoVRSUB_VI_M1_MASK, PseudoVRSUB_VI_M1, PseudoVRSUB_VI_M1_TU, 0x3 }, // 1354
{ PseudoVRSUB_VI_M2_MASK, PseudoVRSUB_VI_M2, PseudoVRSUB_VI_M2_TU, 0x3 }, // 1355
{ PseudoVRSUB_VI_M4_MASK, PseudoVRSUB_VI_M4, PseudoVRSUB_VI_M4_TU, 0x3 }, // 1356
{ PseudoVRSUB_VI_M8_MASK, PseudoVRSUB_VI_M8, PseudoVRSUB_VI_M8_TU, 0x3 }, // 1357
{ PseudoVRSUB_VI_MF2_MASK, PseudoVRSUB_VI_MF2, PseudoVRSUB_VI_MF2_TU, 0x3 }, // 1358
{ PseudoVRSUB_VI_MF4_MASK, PseudoVRSUB_VI_MF4, PseudoVRSUB_VI_MF4_TU, 0x3 }, // 1359
{ PseudoVRSUB_VI_MF8_MASK, PseudoVRSUB_VI_MF8, PseudoVRSUB_VI_MF8_TU, 0x3 }, // 1360
{ PseudoVRSUB_VX_M1_MASK, PseudoVRSUB_VX_M1, PseudoVRSUB_VX_M1_TU, 0x3 }, // 1361
{ PseudoVRSUB_VX_M2_MASK, PseudoVRSUB_VX_M2, PseudoVRSUB_VX_M2_TU, 0x3 }, // 1362
{ PseudoVRSUB_VX_M4_MASK, PseudoVRSUB_VX_M4, PseudoVRSUB_VX_M4_TU, 0x3 }, // 1363
{ PseudoVRSUB_VX_M8_MASK, PseudoVRSUB_VX_M8, PseudoVRSUB_VX_M8_TU, 0x3 }, // 1364
{ PseudoVRSUB_VX_MF2_MASK, PseudoVRSUB_VX_MF2, PseudoVRSUB_VX_MF2_TU, 0x3 }, // 1365
{ PseudoVRSUB_VX_MF4_MASK, PseudoVRSUB_VX_MF4, PseudoVRSUB_VX_MF4_TU, 0x3 }, // 1366
{ PseudoVRSUB_VX_MF8_MASK, PseudoVRSUB_VX_MF8, PseudoVRSUB_VX_MF8_TU, 0x3 }, // 1367
{ PseudoVSADDU_VI_M1_MASK, PseudoVSADDU_VI_M1, PseudoVSADDU_VI_M1_TU, 0x3 }, // 1368
{ PseudoVSADDU_VI_M2_MASK, PseudoVSADDU_VI_M2, PseudoVSADDU_VI_M2_TU, 0x3 }, // 1369
{ PseudoVSADDU_VI_M4_MASK, PseudoVSADDU_VI_M4, PseudoVSADDU_VI_M4_TU, 0x3 }, // 1370
{ PseudoVSADDU_VI_M8_MASK, PseudoVSADDU_VI_M8, PseudoVSADDU_VI_M8_TU, 0x3 }, // 1371
{ PseudoVSADDU_VI_MF2_MASK, PseudoVSADDU_VI_MF2, PseudoVSADDU_VI_MF2_TU, 0x3 }, // 1372
{ PseudoVSADDU_VI_MF4_MASK, PseudoVSADDU_VI_MF4, PseudoVSADDU_VI_MF4_TU, 0x3 }, // 1373
{ PseudoVSADDU_VI_MF8_MASK, PseudoVSADDU_VI_MF8, PseudoVSADDU_VI_MF8_TU, 0x3 }, // 1374
{ PseudoVSADDU_VV_M1_MASK, PseudoVSADDU_VV_M1, PseudoVSADDU_VV_M1_TU, 0x3 }, // 1375
{ PseudoVSADDU_VV_M2_MASK, PseudoVSADDU_VV_M2, PseudoVSADDU_VV_M2_TU, 0x3 }, // 1376
{ PseudoVSADDU_VV_M4_MASK, PseudoVSADDU_VV_M4, PseudoVSADDU_VV_M4_TU, 0x3 }, // 1377
{ PseudoVSADDU_VV_M8_MASK, PseudoVSADDU_VV_M8, PseudoVSADDU_VV_M8_TU, 0x3 }, // 1378
{ PseudoVSADDU_VV_MF2_MASK, PseudoVSADDU_VV_MF2, PseudoVSADDU_VV_MF2_TU, 0x3 }, // 1379
{ PseudoVSADDU_VV_MF4_MASK, PseudoVSADDU_VV_MF4, PseudoVSADDU_VV_MF4_TU, 0x3 }, // 1380
{ PseudoVSADDU_VV_MF8_MASK, PseudoVSADDU_VV_MF8, PseudoVSADDU_VV_MF8_TU, 0x3 }, // 1381
{ PseudoVSADDU_VX_M1_MASK, PseudoVSADDU_VX_M1, PseudoVSADDU_VX_M1_TU, 0x3 }, // 1382
{ PseudoVSADDU_VX_M2_MASK, PseudoVSADDU_VX_M2, PseudoVSADDU_VX_M2_TU, 0x3 }, // 1383
{ PseudoVSADDU_VX_M4_MASK, PseudoVSADDU_VX_M4, PseudoVSADDU_VX_M4_TU, 0x3 }, // 1384
{ PseudoVSADDU_VX_M8_MASK, PseudoVSADDU_VX_M8, PseudoVSADDU_VX_M8_TU, 0x3 }, // 1385
{ PseudoVSADDU_VX_MF2_MASK, PseudoVSADDU_VX_MF2, PseudoVSADDU_VX_MF2_TU, 0x3 }, // 1386
{ PseudoVSADDU_VX_MF4_MASK, PseudoVSADDU_VX_MF4, PseudoVSADDU_VX_MF4_TU, 0x3 }, // 1387
{ PseudoVSADDU_VX_MF8_MASK, PseudoVSADDU_VX_MF8, PseudoVSADDU_VX_MF8_TU, 0x3 }, // 1388
{ PseudoVSADD_VI_M1_MASK, PseudoVSADD_VI_M1, PseudoVSADD_VI_M1_TU, 0x3 }, // 1389
{ PseudoVSADD_VI_M2_MASK, PseudoVSADD_VI_M2, PseudoVSADD_VI_M2_TU, 0x3 }, // 1390
{ PseudoVSADD_VI_M4_MASK, PseudoVSADD_VI_M4, PseudoVSADD_VI_M4_TU, 0x3 }, // 1391
{ PseudoVSADD_VI_M8_MASK, PseudoVSADD_VI_M8, PseudoVSADD_VI_M8_TU, 0x3 }, // 1392
{ PseudoVSADD_VI_MF2_MASK, PseudoVSADD_VI_MF2, PseudoVSADD_VI_MF2_TU, 0x3 }, // 1393
{ PseudoVSADD_VI_MF4_MASK, PseudoVSADD_VI_MF4, PseudoVSADD_VI_MF4_TU, 0x3 }, // 1394
{ PseudoVSADD_VI_MF8_MASK, PseudoVSADD_VI_MF8, PseudoVSADD_VI_MF8_TU, 0x3 }, // 1395
{ PseudoVSADD_VV_M1_MASK, PseudoVSADD_VV_M1, PseudoVSADD_VV_M1_TU, 0x3 }, // 1396
{ PseudoVSADD_VV_M2_MASK, PseudoVSADD_VV_M2, PseudoVSADD_VV_M2_TU, 0x3 }, // 1397
{ PseudoVSADD_VV_M4_MASK, PseudoVSADD_VV_M4, PseudoVSADD_VV_M4_TU, 0x3 }, // 1398
{ PseudoVSADD_VV_M8_MASK, PseudoVSADD_VV_M8, PseudoVSADD_VV_M8_TU, 0x3 }, // 1399
{ PseudoVSADD_VV_MF2_MASK, PseudoVSADD_VV_MF2, PseudoVSADD_VV_MF2_TU, 0x3 }, // 1400
{ PseudoVSADD_VV_MF4_MASK, PseudoVSADD_VV_MF4, PseudoVSADD_VV_MF4_TU, 0x3 }, // 1401
{ PseudoVSADD_VV_MF8_MASK, PseudoVSADD_VV_MF8, PseudoVSADD_VV_MF8_TU, 0x3 }, // 1402
{ PseudoVSADD_VX_M1_MASK, PseudoVSADD_VX_M1, PseudoVSADD_VX_M1_TU, 0x3 }, // 1403
{ PseudoVSADD_VX_M2_MASK, PseudoVSADD_VX_M2, PseudoVSADD_VX_M2_TU, 0x3 }, // 1404
{ PseudoVSADD_VX_M4_MASK, PseudoVSADD_VX_M4, PseudoVSADD_VX_M4_TU, 0x3 }, // 1405
{ PseudoVSADD_VX_M8_MASK, PseudoVSADD_VX_M8, PseudoVSADD_VX_M8_TU, 0x3 }, // 1406
{ PseudoVSADD_VX_MF2_MASK, PseudoVSADD_VX_MF2, PseudoVSADD_VX_MF2_TU, 0x3 }, // 1407
{ PseudoVSADD_VX_MF4_MASK, PseudoVSADD_VX_MF4, PseudoVSADD_VX_MF4_TU, 0x3 }, // 1408
{ PseudoVSADD_VX_MF8_MASK, PseudoVSADD_VX_MF8, PseudoVSADD_VX_MF8_TU, 0x3 }, // 1409
{ PseudoVSEXT_VF2_M1_MASK, PseudoVSEXT_VF2_M1, PseudoVSEXT_VF2_M1_TU, 0x2 }, // 1410
{ PseudoVSEXT_VF2_M2_MASK, PseudoVSEXT_VF2_M2, PseudoVSEXT_VF2_M2_TU, 0x2 }, // 1411
{ PseudoVSEXT_VF2_M4_MASK, PseudoVSEXT_VF2_M4, PseudoVSEXT_VF2_M4_TU, 0x2 }, // 1412
{ PseudoVSEXT_VF2_M8_MASK, PseudoVSEXT_VF2_M8, PseudoVSEXT_VF2_M8_TU, 0x2 }, // 1413
{ PseudoVSEXT_VF2_MF2_MASK, PseudoVSEXT_VF2_MF2, PseudoVSEXT_VF2_MF2_TU, 0x2 }, // 1414
{ PseudoVSEXT_VF2_MF4_MASK, PseudoVSEXT_VF2_MF4, PseudoVSEXT_VF2_MF4_TU, 0x2 }, // 1415
{ PseudoVSEXT_VF4_M1_MASK, PseudoVSEXT_VF4_M1, PseudoVSEXT_VF4_M1_TU, 0x2 }, // 1416
{ PseudoVSEXT_VF4_M2_MASK, PseudoVSEXT_VF4_M2, PseudoVSEXT_VF4_M2_TU, 0x2 }, // 1417
{ PseudoVSEXT_VF4_M4_MASK, PseudoVSEXT_VF4_M4, PseudoVSEXT_VF4_M4_TU, 0x2 }, // 1418
{ PseudoVSEXT_VF4_M8_MASK, PseudoVSEXT_VF4_M8, PseudoVSEXT_VF4_M8_TU, 0x2 }, // 1419
{ PseudoVSEXT_VF4_MF2_MASK, PseudoVSEXT_VF4_MF2, PseudoVSEXT_VF4_MF2_TU, 0x2 }, // 1420
{ PseudoVSEXT_VF8_M1_MASK, PseudoVSEXT_VF8_M1, PseudoVSEXT_VF8_M1_TU, 0x2 }, // 1421
{ PseudoVSEXT_VF8_M2_MASK, PseudoVSEXT_VF8_M2, PseudoVSEXT_VF8_M2_TU, 0x2 }, // 1422
{ PseudoVSEXT_VF8_M4_MASK, PseudoVSEXT_VF8_M4, PseudoVSEXT_VF8_M4_TU, 0x2 }, // 1423
{ PseudoVSEXT_VF8_M8_MASK, PseudoVSEXT_VF8_M8, PseudoVSEXT_VF8_M8_TU, 0x2 }, // 1424
{ PseudoVSLIDE1DOWN_VX_M1_MASK, PseudoVSLIDE1DOWN_VX_M1, PseudoVSLIDE1DOWN_VX_M1_TU, 0x3 }, // 1425
{ PseudoVSLIDE1DOWN_VX_M2_MASK, PseudoVSLIDE1DOWN_VX_M2, PseudoVSLIDE1DOWN_VX_M2_TU, 0x3 }, // 1426
{ PseudoVSLIDE1DOWN_VX_M4_MASK, PseudoVSLIDE1DOWN_VX_M4, PseudoVSLIDE1DOWN_VX_M4_TU, 0x3 }, // 1427
{ PseudoVSLIDE1DOWN_VX_M8_MASK, PseudoVSLIDE1DOWN_VX_M8, PseudoVSLIDE1DOWN_VX_M8_TU, 0x3 }, // 1428
{ PseudoVSLIDE1DOWN_VX_MF2_MASK, PseudoVSLIDE1DOWN_VX_MF2, PseudoVSLIDE1DOWN_VX_MF2_TU, 0x3 }, // 1429
{ PseudoVSLIDE1DOWN_VX_MF4_MASK, PseudoVSLIDE1DOWN_VX_MF4, PseudoVSLIDE1DOWN_VX_MF4_TU, 0x3 }, // 1430
{ PseudoVSLIDE1DOWN_VX_MF8_MASK, PseudoVSLIDE1DOWN_VX_MF8, PseudoVSLIDE1DOWN_VX_MF8_TU, 0x3 }, // 1431
{ PseudoVSLIDE1UP_VX_M1_MASK, PseudoVSLIDE1UP_VX_M1, PseudoVSLIDE1UP_VX_M1_TU, 0x3 }, // 1432
{ PseudoVSLIDE1UP_VX_M2_MASK, PseudoVSLIDE1UP_VX_M2, PseudoVSLIDE1UP_VX_M2_TU, 0x3 }, // 1433
{ PseudoVSLIDE1UP_VX_M4_MASK, PseudoVSLIDE1UP_VX_M4, PseudoVSLIDE1UP_VX_M4_TU, 0x3 }, // 1434
{ PseudoVSLIDE1UP_VX_M8_MASK, PseudoVSLIDE1UP_VX_M8, PseudoVSLIDE1UP_VX_M8_TU, 0x3 }, // 1435
{ PseudoVSLIDE1UP_VX_MF2_MASK, PseudoVSLIDE1UP_VX_MF2, PseudoVSLIDE1UP_VX_MF2_TU, 0x3 }, // 1436
{ PseudoVSLIDE1UP_VX_MF4_MASK, PseudoVSLIDE1UP_VX_MF4, PseudoVSLIDE1UP_VX_MF4_TU, 0x3 }, // 1437
{ PseudoVSLIDE1UP_VX_MF8_MASK, PseudoVSLIDE1UP_VX_MF8, PseudoVSLIDE1UP_VX_MF8_TU, 0x3 }, // 1438
{ PseudoVSLL_VI_M1_MASK, PseudoVSLL_VI_M1, PseudoVSLL_VI_M1_TU, 0x3 }, // 1439
{ PseudoVSLL_VI_M2_MASK, PseudoVSLL_VI_M2, PseudoVSLL_VI_M2_TU, 0x3 }, // 1440
{ PseudoVSLL_VI_M4_MASK, PseudoVSLL_VI_M4, PseudoVSLL_VI_M4_TU, 0x3 }, // 1441
{ PseudoVSLL_VI_M8_MASK, PseudoVSLL_VI_M8, PseudoVSLL_VI_M8_TU, 0x3 }, // 1442
{ PseudoVSLL_VI_MF2_MASK, PseudoVSLL_VI_MF2, PseudoVSLL_VI_MF2_TU, 0x3 }, // 1443
{ PseudoVSLL_VI_MF4_MASK, PseudoVSLL_VI_MF4, PseudoVSLL_VI_MF4_TU, 0x3 }, // 1444
{ PseudoVSLL_VI_MF8_MASK, PseudoVSLL_VI_MF8, PseudoVSLL_VI_MF8_TU, 0x3 }, // 1445
{ PseudoVSLL_VV_M1_MASK, PseudoVSLL_VV_M1, PseudoVSLL_VV_M1_TU, 0x3 }, // 1446
{ PseudoVSLL_VV_M2_MASK, PseudoVSLL_VV_M2, PseudoVSLL_VV_M2_TU, 0x3 }, // 1447
{ PseudoVSLL_VV_M4_MASK, PseudoVSLL_VV_M4, PseudoVSLL_VV_M4_TU, 0x3 }, // 1448
{ PseudoVSLL_VV_M8_MASK, PseudoVSLL_VV_M8, PseudoVSLL_VV_M8_TU, 0x3 }, // 1449
{ PseudoVSLL_VV_MF2_MASK, PseudoVSLL_VV_MF2, PseudoVSLL_VV_MF2_TU, 0x3 }, // 1450
{ PseudoVSLL_VV_MF4_MASK, PseudoVSLL_VV_MF4, PseudoVSLL_VV_MF4_TU, 0x3 }, // 1451
{ PseudoVSLL_VV_MF8_MASK, PseudoVSLL_VV_MF8, PseudoVSLL_VV_MF8_TU, 0x3 }, // 1452
{ PseudoVSLL_VX_M1_MASK, PseudoVSLL_VX_M1, PseudoVSLL_VX_M1_TU, 0x3 }, // 1453
{ PseudoVSLL_VX_M2_MASK, PseudoVSLL_VX_M2, PseudoVSLL_VX_M2_TU, 0x3 }, // 1454
{ PseudoVSLL_VX_M4_MASK, PseudoVSLL_VX_M4, PseudoVSLL_VX_M4_TU, 0x3 }, // 1455
{ PseudoVSLL_VX_M8_MASK, PseudoVSLL_VX_M8, PseudoVSLL_VX_M8_TU, 0x3 }, // 1456
{ PseudoVSLL_VX_MF2_MASK, PseudoVSLL_VX_MF2, PseudoVSLL_VX_MF2_TU, 0x3 }, // 1457
{ PseudoVSLL_VX_MF4_MASK, PseudoVSLL_VX_MF4, PseudoVSLL_VX_MF4_TU, 0x3 }, // 1458
{ PseudoVSLL_VX_MF8_MASK, PseudoVSLL_VX_MF8, PseudoVSLL_VX_MF8_TU, 0x3 }, // 1459
{ PseudoVSMUL_VV_M1_MASK, PseudoVSMUL_VV_M1, PseudoVSMUL_VV_M1_TU, 0x3 }, // 1460
{ PseudoVSMUL_VV_M2_MASK, PseudoVSMUL_VV_M2, PseudoVSMUL_VV_M2_TU, 0x3 }, // 1461
{ PseudoVSMUL_VV_M4_MASK, PseudoVSMUL_VV_M4, PseudoVSMUL_VV_M4_TU, 0x3 }, // 1462
{ PseudoVSMUL_VV_M8_MASK, PseudoVSMUL_VV_M8, PseudoVSMUL_VV_M8_TU, 0x3 }, // 1463
{ PseudoVSMUL_VV_MF2_MASK, PseudoVSMUL_VV_MF2, PseudoVSMUL_VV_MF2_TU, 0x3 }, // 1464
{ PseudoVSMUL_VV_MF4_MASK, PseudoVSMUL_VV_MF4, PseudoVSMUL_VV_MF4_TU, 0x3 }, // 1465
{ PseudoVSMUL_VV_MF8_MASK, PseudoVSMUL_VV_MF8, PseudoVSMUL_VV_MF8_TU, 0x3 }, // 1466
{ PseudoVSMUL_VX_M1_MASK, PseudoVSMUL_VX_M1, PseudoVSMUL_VX_M1_TU, 0x3 }, // 1467
{ PseudoVSMUL_VX_M2_MASK, PseudoVSMUL_VX_M2, PseudoVSMUL_VX_M2_TU, 0x3 }, // 1468
{ PseudoVSMUL_VX_M4_MASK, PseudoVSMUL_VX_M4, PseudoVSMUL_VX_M4_TU, 0x3 }, // 1469
{ PseudoVSMUL_VX_M8_MASK, PseudoVSMUL_VX_M8, PseudoVSMUL_VX_M8_TU, 0x3 }, // 1470
{ PseudoVSMUL_VX_MF2_MASK, PseudoVSMUL_VX_MF2, PseudoVSMUL_VX_MF2_TU, 0x3 }, // 1471
{ PseudoVSMUL_VX_MF4_MASK, PseudoVSMUL_VX_MF4, PseudoVSMUL_VX_MF4_TU, 0x3 }, // 1472
{ PseudoVSMUL_VX_MF8_MASK, PseudoVSMUL_VX_MF8, PseudoVSMUL_VX_MF8_TU, 0x3 }, // 1473
{ PseudoVSRA_VI_M1_MASK, PseudoVSRA_VI_M1, PseudoVSRA_VI_M1_TU, 0x3 }, // 1474
{ PseudoVSRA_VI_M2_MASK, PseudoVSRA_VI_M2, PseudoVSRA_VI_M2_TU, 0x3 }, // 1475
{ PseudoVSRA_VI_M4_MASK, PseudoVSRA_VI_M4, PseudoVSRA_VI_M4_TU, 0x3 }, // 1476
{ PseudoVSRA_VI_M8_MASK, PseudoVSRA_VI_M8, PseudoVSRA_VI_M8_TU, 0x3 }, // 1477
{ PseudoVSRA_VI_MF2_MASK, PseudoVSRA_VI_MF2, PseudoVSRA_VI_MF2_TU, 0x3 }, // 1478
{ PseudoVSRA_VI_MF4_MASK, PseudoVSRA_VI_MF4, PseudoVSRA_VI_MF4_TU, 0x3 }, // 1479
{ PseudoVSRA_VI_MF8_MASK, PseudoVSRA_VI_MF8, PseudoVSRA_VI_MF8_TU, 0x3 }, // 1480
{ PseudoVSRA_VV_M1_MASK, PseudoVSRA_VV_M1, PseudoVSRA_VV_M1_TU, 0x3 }, // 1481
{ PseudoVSRA_VV_M2_MASK, PseudoVSRA_VV_M2, PseudoVSRA_VV_M2_TU, 0x3 }, // 1482
{ PseudoVSRA_VV_M4_MASK, PseudoVSRA_VV_M4, PseudoVSRA_VV_M4_TU, 0x3 }, // 1483
{ PseudoVSRA_VV_M8_MASK, PseudoVSRA_VV_M8, PseudoVSRA_VV_M8_TU, 0x3 }, // 1484
{ PseudoVSRA_VV_MF2_MASK, PseudoVSRA_VV_MF2, PseudoVSRA_VV_MF2_TU, 0x3 }, // 1485