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swiftshader / SwiftShader / refs/heads/master / . / third_party / llvm-16.0 / configs / common / lib / Target / RISCV / RISCVGenAsmMatcher.inc
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/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|* *|
|* Assembly Matcher Source Fragment *|
|* *|
|* Automatically generated file, do not edit! *|
|* *|
\*===----------------------------------------------------------------------===*/
#ifdef GET_ASSEMBLER_HEADER
#undef GET_ASSEMBLER_HEADER
// This should be included into the middle of the declaration of
// your subclasses implementation of MCTargetAsmParser.
FeatureBitset ComputeAvailableFeatures(const FeatureBitset &FB) const;
void convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
const OperandVector &Operands,
const SmallBitVector &OptionalOperandsMask);
void convertToMapAndConstraints(unsigned Kind,
const OperandVector &Operands) override;
unsigned MatchInstructionImpl(const OperandVector &Operands,
MCInst &Inst,
uint64_t &ErrorInfo,
FeatureBitset &MissingFeatures,
bool matchingInlineAsm,
unsigned VariantID = 0);
unsigned MatchInstructionImpl(const OperandVector &Operands,
MCInst &Inst,
uint64_t &ErrorInfo,
bool matchingInlineAsm,
unsigned VariantID = 0) {
FeatureBitset MissingFeatures;
return MatchInstructionImpl(Operands, Inst, ErrorInfo, MissingFeatures,
matchingInlineAsm, VariantID);
}
OperandMatchResultTy MatchOperandParserImpl(
OperandVector &Operands,
StringRef Mnemonic,
bool ParseForAllFeatures = false);
OperandMatchResultTy tryCustomParseOperand(
OperandVector &Operands,
unsigned MCK);
#endif // GET_ASSEMBLER_HEADER_INFO
#ifdef GET_OPERAND_DIAGNOSTIC_TYPES
#undef GET_OPERAND_DIAGNOSTIC_TYPES
Match_InvalidBareSymbol,
Match_InvalidCLUIImm,
Match_InvalidCSRSystemRegister,
Match_InvalidCallSymbol,
Match_InvalidFRMArg,
Match_InvalidFenceArg,
Match_InvalidImmXLenLI,
Match_InvalidImmZero,
Match_InvalidPseudoJumpSymbol,
Match_InvalidRnumArg,
Match_InvalidSImm10Lsb0000NonZero,
Match_InvalidSImm12,
Match_InvalidSImm12Lsb0,
Match_InvalidSImm12Lsb00000,
Match_InvalidSImm13Lsb0,
Match_InvalidSImm21Lsb0JAL,
Match_InvalidSImm5,
Match_InvalidSImm5Plus1,
Match_InvalidSImm6,
Match_InvalidSImm6NonZero,
Match_InvalidSImm9Lsb0,
Match_InvalidTPRelAddSymbol,
Match_InvalidUImm10Lsb00NonZero,
Match_InvalidUImm2,
Match_InvalidUImm20AUIPC,
Match_InvalidUImm20LUI,
Match_InvalidUImm3,
Match_InvalidUImm5,
Match_InvalidUImm7,
Match_InvalidUImm7Lsb00,
Match_InvalidUImm8Lsb00,
Match_InvalidUImm8Lsb000,
Match_InvalidUImm9Lsb000,
Match_InvalidUImmLog2XLen,
Match_InvalidUImmLog2XLenHalf,
Match_InvalidUImmLog2XLenNonZero,
Match_InvalidVMaskRegister,
Match_InvalidVTypeI,
END_OPERAND_DIAGNOSTIC_TYPES
#endif // GET_OPERAND_DIAGNOSTIC_TYPES
#ifdef GET_REGISTER_MATCHER
#undef GET_REGISTER_MATCHER
// Bits for subtarget features that participate in instruction matching.
enum SubtargetFeatureBits : uint8_t {
Feature_HasStdExtMBit = 9,
Feature_HasStdExtMOrZmmulBit = 10,
Feature_HasStdExtABit = 1,
Feature_HasStdExtFBit = 7,
Feature_HasStdExtDBit = 6,
Feature_HasStdExtHBit = 8,
Feature_HasStdExtZihintpauseBit = 34,
Feature_HasStdExtZihintntlBit = 33,
Feature_HasStdExtZfhminBit = 25,
Feature_HasStdExtZfhBit = 23,
Feature_HasStdExtZfhOrZfhminBit = 24,
Feature_HasStdExtZfinxBit = 26,
Feature_HasStdExtZdinxBit = 22,
Feature_HasStdExtZhinxminBit = 29,
Feature_HasStdExtZhinxBit = 27,
Feature_HasStdExtZhinxOrZhinxminBit = 28,
Feature_HasStdExtCBit = 2,
Feature_HasStdExtZbaBit = 13,
Feature_HasStdExtZbbBit = 14,
Feature_HasStdExtZbcBit = 16,
Feature_HasStdExtZbsBit = 21,
Feature_HasStdExtZbkbBit = 18,
Feature_HasStdExtZbkxBit = 20,
Feature_HasStdExtZbbOrZbkbBit = 15,
Feature_HasStdExtZbkcBit = 19,
Feature_HasStdExtZbcOrZbkcBit = 17,
Feature_HasStdExtZkndBit = 35,
Feature_HasStdExtZkneBit = 37,
Feature_HasStdExtZkndOrZkneBit = 36,
Feature_HasStdExtZknhBit = 38,
Feature_HasStdExtZksedBit = 40,
Feature_HasStdExtZkshBit = 41,
Feature_HasStdExtZkrBit = 39,
Feature_HasStdExtCOrZcaBit = 3,
Feature_HasStdExtCOrZcdBit = 4,
Feature_HasStdExtCOrZcfBit = 5,
Feature_HasRVCHintsBit = 0,
Feature_HasVInstructionsBit = 43,
Feature_HasVInstructionsI64Bit = 45,
Feature_HasVInstructionsAnyFBit = 44,
Feature_HasStdExtZicbomBit = 30,
Feature_HasStdExtZicbozBit = 32,
Feature_HasStdExtZicbopBit = 31,
Feature_HasStdExtSvinvalBit = 11,
Feature_HasStdExtZtsoBit = 42,
Feature_HasStdExtZawrsBit = 12,
Feature_HasVendorXVentanaCondOpsBit = 47,
Feature_HasVendorXTHeadVdotBit = 46,
Feature_IsRV64Bit = 50,
Feature_IsRV32Bit = 48,
Feature_IsRV32EBit = 49,
};
static unsigned MatchRegisterName(StringRef Name) {
switch (Name.size()) {
default: break;
case 2: // 66 strings to match.
switch (Name[0]) {
default: break;
case 'f': // 30 strings to match.
switch (Name[1]) {
default: break;
case '0': // 3 strings to match.
return 72; // "f0"
case '1': // 3 strings to match.
return 73; // "f1"
case '2': // 3 strings to match.
return 74; // "f2"
case '3': // 3 strings to match.
return 75; // "f3"
case '4': // 3 strings to match.
return 76; // "f4"
case '5': // 3 strings to match.
return 77; // "f5"
case '6': // 3 strings to match.
return 78; // "f6"
case '7': // 3 strings to match.
return 79; // "f7"
case '8': // 3 strings to match.
return 80; // "f8"
case '9': // 3 strings to match.
return 81; // "f9"
}
break;
case 'v': // 21 strings to match.
switch (Name[1]) {
default: break;
case '0': // 4 strings to match.
return 8; // "v0"
case '1': // 1 string to match.
return 9; // "v1"
case '2': // 2 strings to match.
return 10; // "v2"
case '3': // 1 string to match.
return 11; // "v3"
case '4': // 3 strings to match.
return 12; // "v4"
case '5': // 1 string to match.
return 13; // "v5"
case '6': // 2 strings to match.
return 14; // "v6"
case '7': // 1 string to match.
return 15; // "v7"
case '8': // 4 strings to match.
return 16; // "v8"
case '9': // 1 string to match.
return 17; // "v9"
case 'l': // 1 string to match.
return 3; // "vl"
}
break;
case 'x': // 15 strings to match.
switch (Name[1]) {
default: break;
case '0': // 2 strings to match.
return 40; // "x0"
case '1': // 1 string to match.
return 41; // "x1"
case '2': // 2 strings to match.
return 42; // "x2"
case '3': // 1 string to match.
return 43; // "x3"
case '4': // 2 strings to match.
return 44; // "x4"
case '5': // 1 string to match.
return 45; // "x5"
case '6': // 2 strings to match.
return 46; // "x6"
case '7': // 1 string to match.
return 47; // "x7"
case '8': // 2 strings to match.
return 48; // "x8"
case '9': // 1 string to match.
return 49; // "x9"
}
break;
}
break;
case 3: // 140 strings to match.
switch (Name[0]) {
default: break;
case 'f': // 67 strings to match.
switch (Name[1]) {
default: break;
case '1': // 30 strings to match.
switch (Name[2]) {
default: break;
case '0': // 3 strings to match.
return 82; // "f10"
case '1': // 3 strings to match.
return 83; // "f11"
case '2': // 3 strings to match.
return 84; // "f12"
case '3': // 3 strings to match.
return 85; // "f13"
case '4': // 3 strings to match.
return 86; // "f14"
case '5': // 3 strings to match.
return 87; // "f15"
case '6': // 3 strings to match.
return 88; // "f16"
case '7': // 3 strings to match.
return 89; // "f17"
case '8': // 3 strings to match.
return 90; // "f18"
case '9': // 3 strings to match.
return 91; // "f19"
}
break;
case '2': // 30 strings to match.
switch (Name[2]) {
default: break;
case '0': // 3 strings to match.
return 92; // "f20"
case '1': // 3 strings to match.
return 93; // "f21"
case '2': // 3 strings to match.
return 94; // "f22"
case '3': // 3 strings to match.
return 95; // "f23"
case '4': // 3 strings to match.
return 96; // "f24"
case '5': // 3 strings to match.
return 97; // "f25"
case '6': // 3 strings to match.
return 98; // "f26"
case '7': // 3 strings to match.
return 99; // "f27"
case '8': // 3 strings to match.
return 100; // "f28"
case '9': // 3 strings to match.
return 101; // "f29"
}
break;
case '3': // 6 strings to match.
switch (Name[2]) {
default: break;
case '0': // 3 strings to match.
return 102; // "f30"
case '1': // 3 strings to match.
return 103; // "f31"
}
break;
case 'r': // 1 string to match.
if (Name[2] != 'm')
break;
return 2; // "frm"
}
break;
case 'v': // 40 strings to match.
switch (Name[1]) {
default: break;
case '1': // 18 strings to match.
switch (Name[2]) {
default: break;
case '0': // 2 strings to match.
return 18; // "v10"
case '1': // 1 string to match.
return 19; // "v11"
case '2': // 3 strings to match.
return 20; // "v12"
case '3': // 1 string to match.
return 21; // "v13"
case '4': // 2 strings to match.
return 22; // "v14"
case '5': // 1 string to match.
return 23; // "v15"
case '6': // 4 strings to match.
return 24; // "v16"
case '7': // 1 string to match.
return 25; // "v17"
case '8': // 2 strings to match.
return 26; // "v18"
case '9': // 1 string to match.
return 27; // "v19"
}
break;
case '2': // 19 strings to match.
switch (Name[2]) {
default: break;
case '0': // 3 strings to match.
return 28; // "v20"
case '1': // 1 string to match.
return 29; // "v21"
case '2': // 2 strings to match.
return 30; // "v22"
case '3': // 1 string to match.
return 31; // "v23"
case '4': // 4 strings to match.
return 32; // "v24"
case '5': // 1 string to match.
return 33; // "v25"
case '6': // 2 strings to match.
return 34; // "v26"
case '7': // 1 string to match.
return 35; // "v27"
case '8': // 3 strings to match.
return 36; // "v28"
case '9': // 1 string to match.
return 37; // "v29"
}
break;
case '3': // 3 strings to match.
switch (Name[2]) {
default: break;
case '0': // 2 strings to match.
return 38; // "v30"
case '1': // 1 string to match.
return 39; // "v31"
}
break;
}
break;
case 'x': // 33 strings to match.
switch (Name[1]) {
default: break;
case '1': // 15 strings to match.
switch (Name[2]) {
default: break;
case '0': // 2 strings to match.
return 50; // "x10"
case '1': // 1 string to match.
return 51; // "x11"
case '2': // 2 strings to match.
return 52; // "x12"
case '3': // 1 string to match.
return 53; // "x13"
case '4': // 2 strings to match.
return 54; // "x14"
case '5': // 1 string to match.
return 55; // "x15"
case '6': // 2 strings to match.
return 56; // "x16"
case '7': // 1 string to match.
return 57; // "x17"
case '8': // 2 strings to match.
return 58; // "x18"
case '9': // 1 string to match.
return 59; // "x19"
}
break;
case '2': // 15 strings to match.
switch (Name[2]) {
default: break;
case '0': // 2 strings to match.
return 60; // "x20"
case '1': // 1 string to match.
return 61; // "x21"
case '2': // 2 strings to match.
return 62; // "x22"
case '3': // 1 string to match.
return 63; // "x23"
case '4': // 2 strings to match.
return 64; // "x24"
case '5': // 1 string to match.
return 65; // "x25"
case '6': // 2 strings to match.
return 66; // "x26"
case '7': // 1 string to match.
return 67; // "x27"
case '8': // 2 strings to match.
return 68; // "x28"
case '9': // 1 string to match.
return 69; // "x29"
}
break;
case '3': // 3 strings to match.
switch (Name[2]) {
default: break;
case '0': // 2 strings to match.
return 70; // "x30"
case '1': // 1 string to match.
return 71; // "x31"
}
break;
}
break;
}
break;
case 4: // 1 string to match.
if (memcmp(Name.data()+0, "vxrm", 4) != 0)
break;
return 6; // "vxrm"
case 5: // 3 strings to match.
if (Name[0] != 'v')
break;
switch (Name[1]) {
default: break;
case 'l': // 1 string to match.
if (memcmp(Name.data()+2, "enb", 3) != 0)
break;
return 4; // "vlenb"
case 't': // 1 string to match.
if (memcmp(Name.data()+2, "ype", 3) != 0)
break;
return 5; // "vtype"
case 'x': // 1 string to match.
if (memcmp(Name.data()+2, "sat", 3) != 0)
break;
return 7; // "vxsat"
}
break;
case 6: // 1 string to match.
if (memcmp(Name.data()+0, "fflags", 6) != 0)
break;
return 1; // "fflags"
}
return 0;
}
static unsigned MatchRegisterAltName(StringRef Name) {
switch (Name.size()) {
default: break;
case 2: // 154 strings to match.
switch (Name[0]) {
default: break;
case 'a': // 12 strings to match.
switch (Name[1]) {
default: break;
case '0': // 2 strings to match.
return 50; // "a0"
case '1': // 1 string to match.
return 51; // "a1"
case '2': // 2 strings to match.
return 52; // "a2"
case '3': // 1 string to match.
return 53; // "a3"
case '4': // 2 strings to match.
return 54; // "a4"
case '5': // 1 string to match.
return 55; // "a5"
case '6': // 2 strings to match.
return 56; // "a6"
case '7': // 1 string to match.
return 57; // "a7"
}
break;
case 'f': // 2 strings to match.
if (Name[1] != 'p')
break;
return 48; // "fp"
case 'g': // 1 string to match.
if (Name[1] != 'p')
break;
return 43; // "gp"
case 'r': // 1 string to match.
if (Name[1] != 'a')
break;
return 41; // "ra"
case 's': // 17 strings to match.
switch (Name[1]) {
default: break;
case '0': // 2 strings to match.
return 48; // "s0"
case '1': // 1 string to match.
return 49; // "s1"
case '2': // 2 strings to match.
return 58; // "s2"
case '3': // 1 string to match.
return 59; // "s3"
case '4': // 2 strings to match.
return 60; // "s4"
case '5': // 1 string to match.
return 61; // "s5"
case '6': // 2 strings to match.
return 62; // "s6"
case '7': // 1 string to match.
return 63; // "s7"
case '8': // 2 strings to match.
return 64; // "s8"
case '9': // 1 string to match.
return 65; // "s9"
case 'p': // 2 strings to match.
return 42; // "sp"
}
break;
case 't': // 12 strings to match.
switch (Name[1]) {
default: break;
case '0': // 1 string to match.
return 45; // "t0"
case '1': // 2 strings to match.
return 46; // "t1"
case '2': // 1 string to match.
return 47; // "t2"
case '3': // 2 strings to match.
return 68; // "t3"
case '4': // 1 string to match.
return 69; // "t4"
case '5': // 2 strings to match.
return 70; // "t5"
case '6': // 1 string to match.
return 71; // "t6"
case 'p': // 2 strings to match.
return 44; // "tp"
}
break;
case 'v': // 109 strings to match.
switch (Name[1]) {
default: break;
case '0': // 15 strings to match.
return 8; // "v0"
case '1': // 8 strings to match.
return 9; // "v1"
case '2': // 12 strings to match.
return 10; // "v2"
case '3': // 8 strings to match.
return 11; // "v3"
case '4': // 14 strings to match.
return 12; // "v4"
case '5': // 8 strings to match.
return 13; // "v5"
case '6': // 12 strings to match.
return 14; // "v6"
case '7': // 8 strings to match.
return 15; // "v7"
case '8': // 15 strings to match.
return 16; // "v8"
case '9': // 8 strings to match.
return 17; // "v9"
case 'l': // 1 string to match.
return 3; // "vl"
}
break;
}
break;
case 3: // 284 strings to match.
switch (Name[0]) {
default: break;
case 'f': // 84 strings to match.
switch (Name[1]) {
default: break;
case 'a': // 24 strings to match.
switch (Name[2]) {
default: break;
case '0': // 3 strings to match.
return 82; // "fa0"
case '1': // 3 strings to match.
return 83; // "fa1"
case '2': // 3 strings to match.
return 84; // "fa2"
case '3': // 3 strings to match.
return 85; // "fa3"
case '4': // 3 strings to match.
return 86; // "fa4"
case '5': // 3 strings to match.
return 87; // "fa5"
case '6': // 3 strings to match.
return 88; // "fa6"
case '7': // 3 strings to match.
return 89; // "fa7"
}
break;
case 's': // 30 strings to match.
switch (Name[2]) {
default: break;
case '0': // 3 strings to match.
return 80; // "fs0"
case '1': // 3 strings to match.
return 81; // "fs1"
case '2': // 3 strings to match.
return 90; // "fs2"
case '3': // 3 strings to match.
return 91; // "fs3"
case '4': // 3 strings to match.
return 92; // "fs4"
case '5': // 3 strings to match.
return 93; // "fs5"
case '6': // 3 strings to match.
return 94; // "fs6"
case '7': // 3 strings to match.
return 95; // "fs7"
case '8': // 3 strings to match.
return 96; // "fs8"
case '9': // 3 strings to match.
return 97; // "fs9"
}
break;
case 't': // 30 strings to match.
switch (Name[2]) {
default: break;
case '0': // 3 strings to match.
return 72; // "ft0"
case '1': // 3 strings to match.
return 73; // "ft1"
case '2': // 3 strings to match.
return 74; // "ft2"
case '3': // 3 strings to match.
return 75; // "ft3"
case '4': // 3 strings to match.
return 76; // "ft4"
case '5': // 3 strings to match.
return 77; // "ft5"
case '6': // 3 strings to match.
return 78; // "ft6"
case '7': // 3 strings to match.
return 79; // "ft7"
case '8': // 3 strings to match.
return 100; // "ft8"
case '9': // 3 strings to match.
return 101; // "ft9"
}
break;
}
break;
case 's': // 3 strings to match.
if (Name[1] != '1')
break;
switch (Name[2]) {
default: break;
case '0': // 2 strings to match.
return 66; // "s10"
case '1': // 1 string to match.
return 67; // "s11"
}
break;
case 'v': // 197 strings to match.
switch (Name[1]) {
default: break;
case '1': // 105 strings to match.
switch (Name[2]) {
default: break;
case '0': // 12 strings to match.
return 18; // "v10"
case '1': // 8 strings to match.
return 19; // "v11"
case '2': // 14 strings to match.
return 20; // "v12"
case '3': // 8 strings to match.
return 21; // "v13"
case '4': // 12 strings to match.
return 22; // "v14"
case '5': // 8 strings to match.
return 23; // "v15"
case '6': // 15 strings to match.
return 24; // "v16"
case '7': // 8 strings to match.
return 25; // "v17"
case '8': // 12 strings to match.
return 26; // "v18"
case '9': // 8 strings to match.
return 27; // "v19"
}
break;
case '2': // 88 strings to match.
switch (Name[2]) {
default: break;
case '0': // 14 strings to match.
return 28; // "v20"
case '1': // 8 strings to match.
return 29; // "v21"
case '2': // 12 strings to match.
return 30; // "v22"
case '3': // 8 strings to match.
return 31; // "v23"
case '4': // 15 strings to match.
return 32; // "v24"
case '5': // 7 strings to match.
return 33; // "v25"
case '6': // 9 strings to match.
return 34; // "v26"
case '7': // 5 strings to match.
return 35; // "v27"
case '8': // 7 strings to match.
return 36; // "v28"
case '9': // 3 strings to match.
return 37; // "v29"
}
break;
case '3': // 4 strings to match.
switch (Name[2]) {
default: break;
case '0': // 3 strings to match.
return 38; // "v30"
case '1': // 1 string to match.
return 39; // "v31"
}
break;
}
break;
}
break;
case 4: // 15 strings to match.
switch (Name[0]) {
default: break;
case 'f': // 12 strings to match.
switch (Name[1]) {
default: break;
case 's': // 6 strings to match.
if (Name[2] != '1')
break;
switch (Name[3]) {
default: break;
case '0': // 3 strings to match.
return 98; // "fs10"
case '1': // 3 strings to match.
return 99; // "fs11"
}
break;
case 't': // 6 strings to match.
if (Name[2] != '1')
break;
switch (Name[3]) {
default: break;
case '0': // 3 strings to match.
return 102; // "ft10"
case '1': // 3 strings to match.
return 103; // "ft11"
}
break;
}
break;
case 'v': // 1 string to match.
if (memcmp(Name.data()+1, "xrm", 3) != 0)
break;
return 6; // "vxrm"
case 'z': // 2 strings to match.
if (memcmp(Name.data()+1, "ero", 3) != 0)
break;
return 40; // "zero"
}
break;
case 5: // 3 strings to match.
if (Name[0] != 'v')
break;
switch (Name[1]) {
default: break;
case 'l': // 1 string to match.
if (memcmp(Name.data()+2, "enb", 3) != 0)
break;
return 4; // "vlenb"
case 't': // 1 string to match.
if (memcmp(Name.data()+2, "ype", 3) != 0)
break;
return 5; // "vtype"
case 'x': // 1 string to match.
if (memcmp(Name.data()+2, "sat", 3) != 0)
break;
return 7; // "vxsat"
}
break;
}
return 0;
}
#endif // GET_REGISTER_MATCHER
#ifdef GET_SUBTARGET_FEATURE_NAME
#undef GET_SUBTARGET_FEATURE_NAME
// User-level names for subtarget features that participate in
// instruction matching.
static const char *getSubtargetFeatureName(uint64_t Val) {
switch(Val) {
case Feature_HasStdExtMBit: return "'M' (Integer Multiplication and Division)";
case Feature_HasStdExtMOrZmmulBit: return "'M' (Integer Multiplication and Division) or 'Zmmul' (Integer Multiplication)";
case Feature_HasStdExtABit: return "'A' (Atomic Instructions)";
case Feature_HasStdExtFBit: return "'F' (Single-Precision Floating-Point)";
case Feature_HasStdExtDBit: return "'D' (Double-Precision Floating-Point)";
case Feature_HasStdExtHBit: return "'H' (Hypervisor)";
case Feature_HasStdExtZihintpauseBit: return "'Zihintpause' (Pause Hint)";
case Feature_HasStdExtZihintntlBit: return "'Zihintntl' (Non-Temporal Locality Hints)";
case Feature_HasStdExtZfhminBit: return "'Zfhmin' (Half-Precision Floating-Point Minimal)";
case Feature_HasStdExtZfhBit: return "'Zfh' (Half-Precision Floating-Point)";
case Feature_HasStdExtZfhOrZfhminBit: return "'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal)";
case Feature_HasStdExtZfinxBit: return "'Zfinx' (Float in Integer)";
case Feature_HasStdExtZdinxBit: return "'Zdinx' (Double in Integer)";
case Feature_HasStdExtZhinxminBit: return "'Zhinxmin' (Half Float in Integer Minimal)";
case Feature_HasStdExtZhinxBit: return "'Zhinx' (Half Float in Integer)";
case Feature_HasStdExtZhinxOrZhinxminBit: return "'Zhinx' (Half Float in Integer) or 'Zhinxmin' (Half Float in Integer Minimal)";
case Feature_HasStdExtCBit: return "'C' (Compressed Instructions)";
case Feature_HasStdExtZbaBit: return "'Zba' (Address Generation Instructions)";
case Feature_HasStdExtZbbBit: return "'Zbb' (Basic Bit-Manipulation)";
case Feature_HasStdExtZbcBit: return "'Zbc' (Carry-Less Multiplication)";
case Feature_HasStdExtZbsBit: return "'Zbs' (Single-Bit Instructions)";
case Feature_HasStdExtZbkbBit: return "'Zbkb' (Bitmanip instructions for Cryptography)";
case Feature_HasStdExtZbkxBit: return "'Zbkx' (Crossbar permutation instructions)";
case Feature_HasStdExtZbbOrZbkbBit: return "'Zbb' (Basic Bit-Manipulation) or 'Zbkb' (Bitmanip instructions for Cryptography)";
case Feature_HasStdExtZbkcBit: return "'Zbkc' (Carry-less multiply instructions for Cryptography)";
case Feature_HasStdExtZbcOrZbkcBit: return "'Zbc' (Carry-Less Multiplication) or 'Zbkc' (Carry-less multiply instructions for Cryptography)";
case Feature_HasStdExtZkndBit: return "'Zknd' (NIST Suite: AES Decryption)";
case Feature_HasStdExtZkneBit: return "'Zkne' (NIST Suite: AES Encryption)";
case Feature_HasStdExtZkndOrZkneBit: return "'Zknd' (NIST Suite: AES Decryption) or 'Zkne' (NIST Suite: AES Encryption)";
case Feature_HasStdExtZknhBit: return "'Zknh' (NIST Suite: Hash Function Instructions)";
case Feature_HasStdExtZksedBit: return "'Zksed' (ShangMi Suite: SM4 Block Cipher Instructions)";
case Feature_HasStdExtZkshBit: return "'Zksh' (ShangMi Suite: SM3 Hash Function Instructions)";
case Feature_HasStdExtZkrBit: return "'Zkr' (Entropy Source Extension)";
case Feature_HasStdExtCOrZcaBit: return "'C' (Compressed Instructions) or 'Zca' (part of the C extension, excluding compressed floating point loads/stores)";
case Feature_HasStdExtCOrZcdBit: return "'C' (Compressed Instructions) or 'Zcd' (Compressed Double-Precision Floating-Point Instructions)";
case Feature_HasStdExtCOrZcfBit: return "'C' (Compressed Instructions) or 'Zcf' (Compressed Single-Precision Floating-Point Instructions)";
case Feature_HasRVCHintsBit: return "RVC Hint Instructions";
case Feature_HasVInstructionsBit: return "'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors)";
case Feature_HasVInstructionsI64Bit: return "'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors)";
case Feature_HasVInstructionsAnyFBit: return "'V' (Vector Extension for Application Processors), 'Zve32f', 'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors)";
case Feature_HasStdExtZicbomBit: return "'Zicbom' (Cache-Block Management Instructions)";
case Feature_HasStdExtZicbozBit: return "'Zicboz' (Cache-Block Zero Instructions)";
case Feature_HasStdExtZicbopBit: return "'Zicbop' (Cache-Block Prefetch Instructions)";
case Feature_HasStdExtSvinvalBit: return "'Svinval' (Fine-Grained Address-Translation Cache Invalidation)";
case Feature_HasStdExtZtsoBit: return "'Ztso' (Memory Model - Total Store Order)";
case Feature_HasStdExtZawrsBit: return "'Zawrs' (Wait on Reservation Set)";
case Feature_HasVendorXVentanaCondOpsBit: return "'XVentanaCondOps' (Ventana Conditional Ops)";
case Feature_HasVendorXTHeadVdotBit: return "'xtheadvdot' (T-Head Vector Extensions for Dot)";
case Feature_IsRV64Bit: return "RV64I Base Instruction Set";
case Feature_IsRV32Bit: return "RV32I Base Instruction Set";
case Feature_IsRV32EBit: return "";
default: return "(unknown)";
}
}
#endif // GET_SUBTARGET_FEATURE_NAME
#ifdef GET_MATCHER_IMPLEMENTATION
#undef GET_MATCHER_IMPLEMENTATION
static void applyMnemonicAliases(StringRef &Mnemonic, const FeatureBitset &Features, unsigned VariantID) {
switch (VariantID) {
case 0:
switch (Mnemonic.size()) {
default: break;
case 4: // 1 string to match.
if (memcmp(Mnemonic.data()+0, "move", 4) != 0)
break;
Mnemonic = "mv"; // "move"
return;
case 5: // 1 string to match.
if (memcmp(Mnemonic.data()+0, "scall", 5) != 0)
break;
Mnemonic = "ecall"; // "scall"
return;
case 6: // 1 string to match.
if (memcmp(Mnemonic.data()+0, "sbreak", 6) != 0)
break;
Mnemonic = "ebreak"; // "sbreak"
return;
case 7: // 2 strings to match.
if (memcmp(Mnemonic.data()+0, "fmv.", 4) != 0)
break;
switch (Mnemonic[4]) {
default: break;
case 's': // 1 string to match.
if (memcmp(Mnemonic.data()+5, ".x", 2) != 0)
break;
if (Features.test(Feature_HasStdExtFBit)) // "fmv.s.x"
Mnemonic = "fmv.w.x";
return;
case 'x': // 1 string to match.
if (memcmp(Mnemonic.data()+5, ".s", 2) != 0)
break;
if (Features.test(Feature_HasStdExtFBit)) // "fmv.x.s"
Mnemonic = "fmv.x.w";
return;
}
break;
}
break;
}
switch (Mnemonic.size()) {
default: break;
case 4: // 1 string to match.
if (memcmp(Mnemonic.data()+0, "move", 4) != 0)
break;
Mnemonic = "mv"; // "move"
return;
case 5: // 1 string to match.
if (memcmp(Mnemonic.data()+0, "scall", 5) != 0)
break;
Mnemonic = "ecall"; // "scall"
return;
case 6: // 1 string to match.
if (memcmp(Mnemonic.data()+0, "sbreak", 6) != 0)
break;
Mnemonic = "ebreak"; // "sbreak"
return;
case 7: // 2 strings to match.
if (memcmp(Mnemonic.data()+0, "fmv.", 4) != 0)
break;
switch (Mnemonic[4]) {
default: break;
case 's': // 1 string to match.
if (memcmp(Mnemonic.data()+5, ".x", 2) != 0)
break;
if (Features.test(Feature_HasStdExtFBit)) // "fmv.s.x"
Mnemonic = "fmv.w.x";
return;
case 'x': // 1 string to match.
if (memcmp(Mnemonic.data()+5, ".s", 2) != 0)
break;
if (Features.test(Feature_HasStdExtFBit)) // "fmv.x.s"
Mnemonic = "fmv.x.w";
return;
}
break;
}
}
enum {
Tie0_1_1,
};
static const uint8_t TiedAsmOperandTable[][3] = {
/* Tie0_1_1 */ { 0, 1, 1 },
};
namespace {
enum OperatorConversionKind {
CVT_Done,
CVT_Reg,
CVT_Tied,
CVT_95_addImmOperands,
CVT_95_Reg,
CVT_95_addRegOperands,
CVT_regX0,
CVT_imm_95_0,
CVT_regX5,
CVT_regX2,
CVT_regX3,
CVT_regX4,
CVT_95_addCSRSystemRegisterOperands,
CVT_imm_95_7,
CVT_95_addFRMArgOperands,
CVT_imm_95_15,
CVT_95_addFenceArgOperands,
CVT_imm_95_3,
CVT_imm_95_1,
CVT_imm_95_2,
CVT_regX1,
CVT_imm_95__MINUS_1,
CVT_imm_95_3072,
CVT_imm_95_3200,
CVT_imm_95_3074,
CVT_imm_95_3202,
CVT_imm_95_3073,
CVT_imm_95_3201,
CVT_95_addRegOperands_95_defaultMaskRegOp,
CVT_reg0,
CVT_95_addVTypeIOperands,
CVT_imm_95_255,
CVT_NUM_CONVERTERS
};
enum InstructionConversionKind {
Convert__InsnDirectiveOpcode1_0__UImm31_1__Reg1_2__Reg1_3__SImm13Lsb01_4,
Convert__Reg1_2__InsnDirectiveOpcode1_0__UImm31_1__Reg1_3__SImm121_4,
Convert__Reg1_2__InsnDirectiveOpcode1_0__UImm31_1__Reg1_5__SImm121_3,
Convert__Reg1_1__InsnDirectiveOpcode1_0__SImm21Lsb0JAL1_2,
Convert__Reg1_3__InsnDirectiveOpcode1_0__UImm31_1__UImm71_2__Reg1_4__Reg1_5,
Convert__Reg1_3__InsnDirectiveOpcode1_0__UImm31_1__UImm21_2__Reg1_4__Reg1_5__Reg1_6,
Convert__InsnDirectiveOpcode1_0__UImm31_1__Reg1_2__Reg1_5__SImm121_3,
Convert__Reg1_1__InsnDirectiveOpcode1_0__UImm20LUI1_2,
Convert__Reg1_0__Reg1_1__Reg1_2,
Convert__Reg1_0__Reg1_1__SImm121_2,
Convert__Reg1_0__Reg1_1__Reg1_2__TPRelAddSymbol1_3,
Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3,
Convert__Reg1_0__Reg1_1,
Convert__Reg1_0__Reg1_1__RnumArg1_2,
Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1,
Convert__Reg1_0__UImm20AUIPC1_1,
Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2,
Convert__Reg1_0__Reg1_1__SImm13Lsb01_2,
Convert__Reg1_0__regX0__SImm13Lsb01_1,
Convert__Reg1_1__Reg1_0__SImm13Lsb01_2,
Convert__regX0__Reg1_0__SImm13Lsb01_1,
Convert__Reg1_0__Tie0_1_1__Reg1_1,
Convert__Reg1_0__Tie0_1_1__ImmZero1_1,
Convert__Reg1_0__Tie0_1_1__SImm6NonZero1_1,
Convert__Reg1_0__Tie0_1_1__SImm10Lsb0000NonZero1_1,
Convert__Reg1_0__Reg1_1__UImm10Lsb00NonZero1_2,
Convert__Reg1_0__Tie0_1_1__SImm61_1,
Convert__Reg1_0__SImm9Lsb01_1,
Convert_NoOperands,
Convert__Reg1_0__Reg1_2__imm_95_0,
Convert__Reg1_0__Reg1_3__UImm8Lsb0001_1,
Convert__Reg1_0__Reg1_3__UImm9Lsb0001_1,
Convert__Reg1_0__Reg1_3__UImm7Lsb001_1,
Convert__Reg1_0__Reg1_3__UImm8Lsb001_1,
Convert__SImm12Lsb01_0,
Convert__Reg1_0,
Convert__Reg1_0__SImm61_1,
Convert__Reg1_0__CLUIImm1_1,
Convert__SImm6NonZero1_0,
Convert__regX0__Tie0_1_1__regX5,
Convert__regX0__Tie0_1_1__regX2,
Convert__regX0__Tie0_1_1__regX3,
Convert__regX0__Tie0_1_1__regX4,
Convert__Reg1_0__Tie0_1_1__UImmLog2XLenNonZero1_1,
Convert__Reg1_0__Tie0_1_1,
Convert__CallSymbol1_0,
Convert__Reg1_0__CallSymbol1_1,
Convert__ZeroOffsetMemOpOperand1_0,
Convert__regX0__CSRSystemRegister1_0__Reg1_1,
Convert__regX0__CSRSystemRegister1_0__UImm51_1,
Convert__Reg1_0__CSRSystemRegister1_1__regX0,
Convert__Reg1_0__CSRSystemRegister1_1__Reg1_2,
Convert__Reg1_0__CSRSystemRegister1_1__UImm51_2,
Convert__imm_95_0__imm_95_0,
Convert__Reg1_0__Reg1_1__Reg1_1,
Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_1,
Convert__GPRPF64AsFPR1_0__GPRPF64AsFPR1_1__GPRPF64AsFPR1_1,
Convert__GPRAsFPR1_0__GPRAsFPR1_1__GPRAsFPR1_1,
Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_7,
Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2__imm_95_7,
Convert__GPRPF64AsFPR1_0__GPRPF64AsFPR1_1__GPRPF64AsFPR1_2__imm_95_7,
Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3,
Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2__FRMArg1_3,
Convert__GPRPF64AsFPR1_0__GPRPF64AsFPR1_1__GPRPF64AsFPR1_2__FRMArg1_3,
Convert__GPRAsFPR1_0__GPRAsFPR1_1__GPRAsFPR1_2__imm_95_7,
Convert__GPRAsFPR1_0__GPRAsFPR1_1__GPRAsFPR1_2__FRMArg1_3,
Convert__Reg1_0__GPRF64AsFPR1_1,
Convert__Reg1_0__GPRPF64AsFPR1_1,
Convert__Reg1_0__GPRAsFPR1_1,
Convert__GPRF64AsFPR1_0__GPRAsFPR1_1,
Convert__Reg1_0__Reg1_1__imm_95_7,
Convert__GPRF64AsFPR1_0__Reg1_1__imm_95_7,
Convert__Reg1_0__Reg1_1__FRMArg1_2,
Convert__GPRF64AsFPR1_0__Reg1_1__FRMArg1_2,
Convert__GPRPF64AsFPR1_0__GPRAsFPR1_1,
Convert__GPRF64AsFPR1_0__Reg1_1,
Convert__GPRPF64AsFPR1_0__Reg1_1,
Convert__GPRAsFPR1_0__GPRF64AsFPR1_1__imm_95_7,
Convert__GPRAsFPR1_0__GPRF64AsFPR1_1__FRMArg1_2,
Convert__GPRAsFPR1_0__Reg1_1__imm_95_7,
Convert__GPRAsFPR1_0__Reg1_1__FRMArg1_2,
Convert__GPRAsFPR1_0__GPRAsFPR1_1__imm_95_7,
Convert__GPRAsFPR1_0__GPRAsFPR1_1__FRMArg1_2,
Convert__Reg1_0__GPRF64AsFPR1_1__imm_95_7,
Convert__Reg1_0__GPRF64AsFPR1_1__FRMArg1_2,
Convert__Reg1_0__GPRAsFPR1_1__imm_95_7,
Convert__Reg1_0__GPRAsFPR1_1__FRMArg1_2,
Convert__GPRAsFPR1_0__GPRPF64AsFPR1_1__imm_95_7,
Convert__GPRAsFPR1_0__GPRPF64AsFPR1_1__FRMArg1_2,
Convert__GPRAsFPR1_0__GPRAsFPR1_1,
Convert__Reg1_0__GPRPF64AsFPR1_1__imm_95_7,
Convert__Reg1_0__GPRPF64AsFPR1_1__FRMArg1_2,
Convert__imm_95_15__imm_95_15,
Convert__FenceArg1_0__FenceArg1_1,
Convert__Reg1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2,
Convert__Reg1_0__GPRPF64AsFPR1_1__GPRPF64AsFPR1_2,
Convert__Reg1_0__GPRAsFPR1_1__GPRAsFPR1_2,
Convert__Reg1_0__Reg1_2__Reg1_1,
Convert__Reg1_0__GPRF64AsFPR1_2__GPRF64AsFPR1_1,
Convert__Reg1_0__GPRPF64AsFPR1_2__GPRPF64AsFPR1_1,
Convert__Reg1_0__GPRAsFPR1_2__GPRAsFPR1_1,
Convert__Reg1_2__Reg1_0__BareSymbol1_1,
Convert__Reg1_0__Reg1_3__SImm121_1,
Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__imm_95_7,
Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2__GPRF64AsFPR1_3__imm_95_7,
Convert__GPRPF64AsFPR1_0__GPRPF64AsFPR1_1__GPRPF64AsFPR1_2__GPRPF64AsFPR1_3__imm_95_7,
Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4,
Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2__GPRF64AsFPR1_3__FRMArg1_4,
Convert__GPRPF64AsFPR1_0__GPRPF64AsFPR1_1__GPRPF64AsFPR1_2__GPRPF64AsFPR1_3__FRMArg1_4,
Convert__GPRAsFPR1_0__GPRAsFPR1_1__GPRAsFPR1_2__GPRAsFPR1_3__imm_95_7,
Convert__GPRAsFPR1_0__GPRAsFPR1_1__GPRAsFPR1_2__GPRAsFPR1_3__FRMArg1_4,
Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2,
Convert__GPRPF64AsFPR1_0__GPRPF64AsFPR1_1__GPRPF64AsFPR1_2,
Convert__GPRAsFPR1_0__GPRAsFPR1_1__GPRAsFPR1_2,
Convert__Reg1_0__imm_95_3__regX0,
Convert__Reg1_0__imm_95_1__regX0,
Convert__Reg1_0__imm_95_2__regX0,
Convert__regX0__imm_95_3__Reg1_0,
Convert__Reg1_0__imm_95_3__Reg1_1,
Convert__regX0__imm_95_1__Reg1_0,
Convert__Reg1_0__imm_95_1__Reg1_1,
Convert__regX0__imm_95_1__UImm51_0,
Convert__Reg1_0__imm_95_1__UImm51_1,
Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__imm_95_7,
Convert__GPRPF64AsFPR1_0__GPRPF64AsFPR1_1__imm_95_7,
Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__FRMArg1_2,
Convert__GPRPF64AsFPR1_0__GPRPF64AsFPR1_1__FRMArg1_2,
Convert__regX0__imm_95_2__Reg1_0,
Convert__Reg1_0__imm_95_2__Reg1_1,
Convert__regX0__imm_95_2__UImm51_0,
Convert__Reg1_0__imm_95_2__UImm51_1,
Convert__regX0__regX0,
Convert__Reg1_0__regX0,
Convert__Reg1_0__ZeroOffsetMemOpOperand1_1,
Convert__regX0__SImm21Lsb0JAL1_0,
Convert__regX1__SImm21Lsb0JAL1_0,
Convert__Reg1_0__SImm21Lsb0JAL1_1,
Convert__regX1__Reg1_0__imm_95_0,
Convert__Reg1_0__Reg1_1__imm_95_0,
Convert__regX1__Reg1_0__SImm121_1,
Convert__regX1__Reg1_2__SImm121_0,
Convert__regX0__Reg1_0__imm_95_0,
Convert__regX0__Reg1_0__SImm121_1,
Convert__regX0__Reg1_2__SImm121_0,
Convert__Reg1_1__PseudoJumpSymbol1_0,
Convert__Reg1_0__BareSymbol1_1,
Convert__Reg1_0__regX0__SImm121_1,
Convert__Reg1_0__ImmXLenLI1_1,
Convert__Reg1_0__UImm20LUI1_1,
Convert__Reg1_0__regX0__Reg1_1,
Convert__regX0__regX0__imm_95_0,
Convert__Reg1_0__Reg1_1__imm_95__MINUS_1,
Convert__regX0__regX0__regX5,
Convert__regX0__regX0__regX2,
Convert__regX0__regX0__regX3,
Convert__regX0__regX0__regX4,
Convert__imm_95_1__imm_95_0,
Convert__Reg1_2__SImm12Lsb000001_0,
Convert__Reg1_0__imm_95_3072__regX0,
Convert__Reg1_0__imm_95_3200__regX0,
Convert__Reg1_0__imm_95_3074__regX0,
Convert__Reg1_0__imm_95_3202__regX0,
Convert__Reg1_0__imm_95_3073__regX0,
Convert__Reg1_0__imm_95_3201__regX0,
Convert__regX0__regX1__imm_95_0,
Convert__Reg1_0__Reg1_1__UImm51_2,
Convert__Reg1_0__Reg1_1__imm_95_1,
Convert__Reg1_0__Reg1_1__regX0,
Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3,
Convert__Reg1_0__Reg1_1__SImm51_2__imm_95_0,
Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0,
Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskRegOpOperand1_3,
Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2,
Convert__Reg1_0__Reg1_1__Reg1_1__reg0,
Convert__Reg1_0__Reg1_1__Reg1_1__RVVMaskRegOpOperand1_2,
Convert__Reg1_0__RVVMaskRegOpOperand1_1,
Convert__Reg1_0__Reg1_2,
Convert__Reg1_0__Reg1_2__RVVMaskRegOpOperand1_4,
Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5,
Convert__Reg1_0__Reg1_1__SImm51_2,
Convert__Reg1_0__Reg1_0__Reg1_0,
Convert__Reg1_0__Reg1_2__Reg1_1__RVVMaskRegOpOperand1_3,
Convert__Reg1_0__Reg1_1__SImm5Plus11_2__RVVMaskRegOpOperand1_3,
Convert__Reg1_0__Reg1_4__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3,
Convert__Reg1_0__SImm51_1,
Convert__Reg1_0__Reg1_1__UImm51_2__RVVMaskRegOpOperand1_3,
Convert__Reg1_0__Reg1_1__regX0__reg0,
Convert__Reg1_0__Reg1_1__regX0__RVVMaskRegOpOperand1_2,
Convert__Reg1_0__Reg1_1__imm_95__MINUS_1__reg0,
Convert__Reg1_0__Reg1_1__imm_95__MINUS_1__RVVMaskRegOpOperand1_2,
Convert__Reg1_0__UImm51_1__VTypeI101_2,
Convert__Reg1_0__Reg1_1__VTypeI111_2,
Convert__Reg1_0__Reg1_1__imm_95_255,
CVT_NUM_SIGNATURES
};
} // end anonymous namespace
static const uint8_t ConversionTable[CVT_NUM_SIGNATURES][15] = {
// Convert__InsnDirectiveOpcode1_0__UImm31_1__Reg1_2__Reg1_3__SImm13Lsb01_4
{ CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_Done },
// Convert__Reg1_2__InsnDirectiveOpcode1_0__UImm31_1__Reg1_3__SImm121_4
{ CVT_95_Reg, 3, CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_Done },
// Convert__Reg1_2__InsnDirectiveOpcode1_0__UImm31_1__Reg1_5__SImm121_3
{ CVT_95_Reg, 3, CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_Reg, 6, CVT_95_addImmOperands, 4, CVT_Done },
// Convert__Reg1_1__InsnDirectiveOpcode1_0__SImm21Lsb0JAL1_2
{ CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 3, CVT_Done },
// Convert__Reg1_3__InsnDirectiveOpcode1_0__UImm31_1__UImm71_2__Reg1_4__Reg1_5
{ CVT_95_Reg, 4, CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_Done },
// Convert__Reg1_3__InsnDirectiveOpcode1_0__UImm31_1__UImm21_2__Reg1_4__Reg1_5__Reg1_6
{ CVT_95_Reg, 4, CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_95_Reg, 5, CVT_95_Reg, 6, CVT_95_Reg, 7, CVT_Done },
// Convert__InsnDirectiveOpcode1_0__UImm31_1__Reg1_2__Reg1_5__SImm121_3
{ CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 2, CVT_95_Reg, 3, CVT_95_Reg, 6, CVT_95_addImmOperands, 4, CVT_Done },
// Convert__Reg1_1__InsnDirectiveOpcode1_0__UImm20LUI1_2
{ CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_95_addImmOperands, 3, CVT_Done },
// Convert__Reg1_0__Reg1_1__Reg1_2
{ CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
// Convert__Reg1_0__Reg1_1__SImm121_2
{ CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
// Convert__Reg1_0__Reg1_1__Reg1_2__TPRelAddSymbol1_3
{ CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
// Convert__Reg1_0__Reg1_1__Reg1_2__UImm21_3
{ CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
// Convert__Reg1_0__Reg1_1
{ CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Done },
// Convert__Reg1_0__Reg1_1__RnumArg1_2
{ CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
// Convert__Reg1_0__ZeroOffsetMemOpOperand1_2__Reg1_1
{ CVT_95_Reg, 1, CVT_95_addRegOperands, 3, CVT_95_Reg, 2, CVT_Done },
// Convert__Reg1_0__UImm20AUIPC1_1
{ CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
// Convert__Reg1_0__Reg1_1__UImmLog2XLen1_2
{ CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
// Convert__Reg1_0__Reg1_1__SImm13Lsb01_2
{ CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
// Convert__Reg1_0__regX0__SImm13Lsb01_1
{ CVT_95_Reg, 1, CVT_regX0, 0, CVT_95_addImmOperands, 2, CVT_Done },
// Convert__Reg1_1__Reg1_0__SImm13Lsb01_2
{ CVT_95_Reg, 2, CVT_95_Reg, 1, CVT_95_addImmOperands, 3, CVT_Done },
// Convert__regX0__Reg1_0__SImm13Lsb01_1
{ CVT_regX0, 0, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
// Convert__Reg1_0__Tie0_1_1__Reg1_1
{ CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_Done },
// Convert__Reg1_0__Tie0_1_1__ImmZero1_1
{ CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_Done },
// Convert__Reg1_0__Tie0_1_1__SImm6NonZero1_1
{ CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_Done },
// Convert__Reg1_0__Tie0_1_1__SImm10Lsb0000NonZero1_1
{ CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_Done },
// Convert__Reg1_0__Reg1_1__UImm10Lsb00NonZero1_2
{ CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
// Convert__Reg1_0__Tie0_1_1__SImm61_1
{ CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_Done },
// Convert__Reg1_0__SImm9Lsb01_1
{ CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
// Convert_NoOperands
{ CVT_Done },
// Convert__Reg1_0__Reg1_2__imm_95_0
{ CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_Done },
// Convert__Reg1_0__Reg1_3__UImm8Lsb0001_1
{ CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_Done },
// Convert__Reg1_0__Reg1_3__UImm9Lsb0001_1
{ CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_Done },
// Convert__Reg1_0__Reg1_3__UImm7Lsb001_1
{ CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_Done },
// Convert__Reg1_0__Reg1_3__UImm8Lsb001_1
{ CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_Done },
// Convert__SImm12Lsb01_0
{ CVT_95_addImmOperands, 1, CVT_Done },
// Convert__Reg1_0
{ CVT_95_Reg, 1, CVT_Done },
// Convert__Reg1_0__SImm61_1
{ CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
// Convert__Reg1_0__CLUIImm1_1
{ CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
// Convert__SImm6NonZero1_0
{ CVT_95_addImmOperands, 1, CVT_Done },
// Convert__regX0__Tie0_1_1__regX5
{ CVT_regX0, 0, CVT_Tied, Tie0_1_1, CVT_regX5, 0, CVT_Done },
// Convert__regX0__Tie0_1_1__regX2
{ CVT_regX0, 0, CVT_Tied, Tie0_1_1, CVT_regX2, 0, CVT_Done },
// Convert__regX0__Tie0_1_1__regX3
{ CVT_regX0, 0, CVT_Tied, Tie0_1_1, CVT_regX3, 0, CVT_Done },
// Convert__regX0__Tie0_1_1__regX4
{ CVT_regX0, 0, CVT_Tied, Tie0_1_1, CVT_regX4, 0, CVT_Done },
// Convert__Reg1_0__Tie0_1_1__UImmLog2XLenNonZero1_1
{ CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 2, CVT_Done },
// Convert__Reg1_0__Tie0_1_1
{ CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_Done },
// Convert__CallSymbol1_0
{ CVT_95_addImmOperands, 1, CVT_Done },
// Convert__Reg1_0__CallSymbol1_1
{ CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
// Convert__ZeroOffsetMemOpOperand1_0
{ CVT_95_addRegOperands, 1, CVT_Done },
// Convert__regX0__CSRSystemRegister1_0__Reg1_1
{ CVT_regX0, 0, CVT_95_addCSRSystemRegisterOperands, 1, CVT_95_Reg, 2, CVT_Done },
// Convert__regX0__CSRSystemRegister1_0__UImm51_1
{ CVT_regX0, 0, CVT_95_addCSRSystemRegisterOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
// Convert__Reg1_0__CSRSystemRegister1_1__regX0
{ CVT_95_Reg, 1, CVT_95_addCSRSystemRegisterOperands, 2, CVT_regX0, 0, CVT_Done },
// Convert__Reg1_0__CSRSystemRegister1_1__Reg1_2
{ CVT_95_Reg, 1, CVT_95_addCSRSystemRegisterOperands, 2, CVT_95_Reg, 3, CVT_Done },
// Convert__Reg1_0__CSRSystemRegister1_1__UImm51_2
{ CVT_95_Reg, 1, CVT_95_addCSRSystemRegisterOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
// Convert__imm_95_0__imm_95_0
{ CVT_imm_95_0, 0, CVT_imm_95_0, 0, CVT_Done },
// Convert__Reg1_0__Reg1_1__Reg1_1
{ CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 2, CVT_Done },
// Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_1
{ CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 2, CVT_Done },
// Convert__GPRPF64AsFPR1_0__GPRPF64AsFPR1_1__GPRPF64AsFPR1_1
{ CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 2, CVT_Done },
// Convert__GPRAsFPR1_0__GPRAsFPR1_1__GPRAsFPR1_1
{ CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 2, CVT_Done },
// Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_7
{ CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_imm_95_7, 0, CVT_Done },
// Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2__imm_95_7
{ CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_imm_95_7, 0, CVT_Done },
// Convert__GPRPF64AsFPR1_0__GPRPF64AsFPR1_1__GPRPF64AsFPR1_2__imm_95_7
{ CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_imm_95_7, 0, CVT_Done },
// Convert__Reg1_0__Reg1_1__Reg1_2__FRMArg1_3
{ CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addFRMArgOperands, 4, CVT_Done },
// Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2__FRMArg1_3
{ CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addFRMArgOperands, 4, CVT_Done },
// Convert__GPRPF64AsFPR1_0__GPRPF64AsFPR1_1__GPRPF64AsFPR1_2__FRMArg1_3
{ CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addFRMArgOperands, 4, CVT_Done },
// Convert__GPRAsFPR1_0__GPRAsFPR1_1__GPRAsFPR1_2__imm_95_7
{ CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_imm_95_7, 0, CVT_Done },
// Convert__GPRAsFPR1_0__GPRAsFPR1_1__GPRAsFPR1_2__FRMArg1_3
{ CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addFRMArgOperands, 4, CVT_Done },
// Convert__Reg1_0__GPRF64AsFPR1_1
{ CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_Done },
// Convert__Reg1_0__GPRPF64AsFPR1_1
{ CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_Done },
// Convert__Reg1_0__GPRAsFPR1_1
{ CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_Done },
// Convert__GPRF64AsFPR1_0__GPRAsFPR1_1
{ CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_Done },
// Convert__Reg1_0__Reg1_1__imm_95_7
{ CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_imm_95_7, 0, CVT_Done },
// Convert__GPRF64AsFPR1_0__Reg1_1__imm_95_7
{ CVT_95_addRegOperands, 1, CVT_95_Reg, 2, CVT_imm_95_7, 0, CVT_Done },
// Convert__Reg1_0__Reg1_1__FRMArg1_2
{ CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addFRMArgOperands, 3, CVT_Done },
// Convert__GPRF64AsFPR1_0__Reg1_1__FRMArg1_2
{ CVT_95_addRegOperands, 1, CVT_95_Reg, 2, CVT_95_addFRMArgOperands, 3, CVT_Done },
// Convert__GPRPF64AsFPR1_0__GPRAsFPR1_1
{ CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_Done },
// Convert__GPRF64AsFPR1_0__Reg1_1
{ CVT_95_addRegOperands, 1, CVT_95_Reg, 2, CVT_Done },
// Convert__GPRPF64AsFPR1_0__Reg1_1
{ CVT_95_addRegOperands, 1, CVT_95_Reg, 2, CVT_Done },
// Convert__GPRAsFPR1_0__GPRF64AsFPR1_1__imm_95_7
{ CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_imm_95_7, 0, CVT_Done },
// Convert__GPRAsFPR1_0__GPRF64AsFPR1_1__FRMArg1_2
{ CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands, 3, CVT_Done },
// Convert__GPRAsFPR1_0__Reg1_1__imm_95_7
{ CVT_95_addRegOperands, 1, CVT_95_Reg, 2, CVT_imm_95_7, 0, CVT_Done },
// Convert__GPRAsFPR1_0__Reg1_1__FRMArg1_2
{ CVT_95_addRegOperands, 1, CVT_95_Reg, 2, CVT_95_addFRMArgOperands, 3, CVT_Done },
// Convert__GPRAsFPR1_0__GPRAsFPR1_1__imm_95_7
{ CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_imm_95_7, 0, CVT_Done },
// Convert__GPRAsFPR1_0__GPRAsFPR1_1__FRMArg1_2
{ CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands, 3, CVT_Done },
// Convert__Reg1_0__GPRF64AsFPR1_1__imm_95_7
{ CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_imm_95_7, 0, CVT_Done },
// Convert__Reg1_0__GPRF64AsFPR1_1__FRMArg1_2
{ CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands, 3, CVT_Done },
// Convert__Reg1_0__GPRAsFPR1_1__imm_95_7
{ CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_imm_95_7, 0, CVT_Done },
// Convert__Reg1_0__GPRAsFPR1_1__FRMArg1_2
{ CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands, 3, CVT_Done },
// Convert__GPRAsFPR1_0__GPRPF64AsFPR1_1__imm_95_7
{ CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_imm_95_7, 0, CVT_Done },
// Convert__GPRAsFPR1_0__GPRPF64AsFPR1_1__FRMArg1_2
{ CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands, 3, CVT_Done },
// Convert__GPRAsFPR1_0__GPRAsFPR1_1
{ CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_Done },
// Convert__Reg1_0__GPRPF64AsFPR1_1__imm_95_7
{ CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_imm_95_7, 0, CVT_Done },
// Convert__Reg1_0__GPRPF64AsFPR1_1__FRMArg1_2
{ CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands, 3, CVT_Done },
// Convert__imm_95_15__imm_95_15
{ CVT_imm_95_15, 0, CVT_imm_95_15, 0, CVT_Done },
// Convert__FenceArg1_0__FenceArg1_1
{ CVT_95_addFenceArgOperands, 1, CVT_95_addFenceArgOperands, 2, CVT_Done },
// Convert__Reg1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2
{ CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done },
// Convert__Reg1_0__GPRPF64AsFPR1_1__GPRPF64AsFPR1_2
{ CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done },
// Convert__Reg1_0__GPRAsFPR1_1__GPRAsFPR1_2
{ CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done },
// Convert__Reg1_0__Reg1_2__Reg1_1
{ CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_Done },
// Convert__Reg1_0__GPRF64AsFPR1_2__GPRF64AsFPR1_1
{ CVT_95_Reg, 1, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 2, CVT_Done },
// Convert__Reg1_0__GPRPF64AsFPR1_2__GPRPF64AsFPR1_1
{ CVT_95_Reg, 1, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 2, CVT_Done },
// Convert__Reg1_0__GPRAsFPR1_2__GPRAsFPR1_1
{ CVT_95_Reg, 1, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 2, CVT_Done },
// Convert__Reg1_2__Reg1_0__BareSymbol1_1
{ CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
// Convert__Reg1_0__Reg1_3__SImm121_1
{ CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_Done },
// Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__imm_95_7
{ CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_imm_95_7, 0, CVT_Done },
// Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2__GPRF64AsFPR1_3__imm_95_7
{ CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 4, CVT_imm_95_7, 0, CVT_Done },
// Convert__GPRPF64AsFPR1_0__GPRPF64AsFPR1_1__GPRPF64AsFPR1_2__GPRPF64AsFPR1_3__imm_95_7
{ CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 4, CVT_imm_95_7, 0, CVT_Done },
// Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__FRMArg1_4
{ CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addFRMArgOperands, 5, CVT_Done },
// Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2__GPRF64AsFPR1_3__FRMArg1_4
{ CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 4, CVT_95_addFRMArgOperands, 5, CVT_Done },
// Convert__GPRPF64AsFPR1_0__GPRPF64AsFPR1_1__GPRPF64AsFPR1_2__GPRPF64AsFPR1_3__FRMArg1_4
{ CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 4, CVT_95_addFRMArgOperands, 5, CVT_Done },
// Convert__GPRAsFPR1_0__GPRAsFPR1_1__GPRAsFPR1_2__GPRAsFPR1_3__imm_95_7
{ CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 4, CVT_imm_95_7, 0, CVT_Done },
// Convert__GPRAsFPR1_0__GPRAsFPR1_1__GPRAsFPR1_2__GPRAsFPR1_3__FRMArg1_4
{ CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_95_addRegOperands, 4, CVT_95_addFRMArgOperands, 5, CVT_Done },
// Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__GPRF64AsFPR1_2
{ CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done },
// Convert__GPRPF64AsFPR1_0__GPRPF64AsFPR1_1__GPRPF64AsFPR1_2
{ CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done },
// Convert__GPRAsFPR1_0__GPRAsFPR1_1__GPRAsFPR1_2
{ CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addRegOperands, 3, CVT_Done },
// Convert__Reg1_0__imm_95_3__regX0
{ CVT_95_Reg, 1, CVT_imm_95_3, 0, CVT_regX0, 0, CVT_Done },
// Convert__Reg1_0__imm_95_1__regX0
{ CVT_95_Reg, 1, CVT_imm_95_1, 0, CVT_regX0, 0, CVT_Done },
// Convert__Reg1_0__imm_95_2__regX0
{ CVT_95_Reg, 1, CVT_imm_95_2, 0, CVT_regX0, 0, CVT_Done },
// Convert__regX0__imm_95_3__Reg1_0
{ CVT_regX0, 0, CVT_imm_95_3, 0, CVT_95_Reg, 1, CVT_Done },
// Convert__Reg1_0__imm_95_3__Reg1_1
{ CVT_95_Reg, 1, CVT_imm_95_3, 0, CVT_95_Reg, 2, CVT_Done },
// Convert__regX0__imm_95_1__Reg1_0
{ CVT_regX0, 0, CVT_imm_95_1, 0, CVT_95_Reg, 1, CVT_Done },
// Convert__Reg1_0__imm_95_1__Reg1_1
{ CVT_95_Reg, 1, CVT_imm_95_1, 0, CVT_95_Reg, 2, CVT_Done },
// Convert__regX0__imm_95_1__UImm51_0
{ CVT_regX0, 0, CVT_imm_95_1, 0, CVT_95_addImmOperands, 1, CVT_Done },
// Convert__Reg1_0__imm_95_1__UImm51_1
{ CVT_95_Reg, 1, CVT_imm_95_1, 0, CVT_95_addImmOperands, 2, CVT_Done },
// Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__imm_95_7
{ CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_imm_95_7, 0, CVT_Done },
// Convert__GPRPF64AsFPR1_0__GPRPF64AsFPR1_1__imm_95_7
{ CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_imm_95_7, 0, CVT_Done },
// Convert__GPRF64AsFPR1_0__GPRF64AsFPR1_1__FRMArg1_2
{ CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands, 3, CVT_Done },
// Convert__GPRPF64AsFPR1_0__GPRPF64AsFPR1_1__FRMArg1_2
{ CVT_95_addRegOperands, 1, CVT_95_addRegOperands, 2, CVT_95_addFRMArgOperands, 3, CVT_Done },
// Convert__regX0__imm_95_2__Reg1_0
{ CVT_regX0, 0, CVT_imm_95_2, 0, CVT_95_Reg, 1, CVT_Done },
// Convert__Reg1_0__imm_95_2__Reg1_1
{ CVT_95_Reg, 1, CVT_imm_95_2, 0, CVT_95_Reg, 2, CVT_Done },
// Convert__regX0__imm_95_2__UImm51_0
{ CVT_regX0, 0, CVT_imm_95_2, 0, CVT_95_addImmOperands, 1, CVT_Done },
// Convert__Reg1_0__imm_95_2__UImm51_1
{ CVT_95_Reg, 1, CVT_imm_95_2, 0, CVT_95_addImmOperands, 2, CVT_Done },
// Convert__regX0__regX0
{ CVT_regX0, 0, CVT_regX0, 0, CVT_Done },
// Convert__Reg1_0__regX0
{ CVT_95_Reg, 1, CVT_regX0, 0, CVT_Done },
// Convert__Reg1_0__ZeroOffsetMemOpOperand1_1
{ CVT_95_Reg, 1, CVT_95_addRegOperands, 2, CVT_Done },
// Convert__regX0__SImm21Lsb0JAL1_0
{ CVT_regX0, 0, CVT_95_addImmOperands, 1, CVT_Done },
// Convert__regX1__SImm21Lsb0JAL1_0
{ CVT_regX1, 0, CVT_95_addImmOperands, 1, CVT_Done },
// Convert__Reg1_0__SImm21Lsb0JAL1_1
{ CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
// Convert__regX1__Reg1_0__imm_95_0
{ CVT_regX1, 0, CVT_95_Reg, 1, CVT_imm_95_0, 0, CVT_Done },
// Convert__Reg1_0__Reg1_1__imm_95_0
{ CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_imm_95_0, 0, CVT_Done },
// Convert__regX1__Reg1_0__SImm121_1
{ CVT_regX1, 0, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
// Convert__regX1__Reg1_2__SImm121_0
{ CVT_regX1, 0, CVT_95_Reg, 3, CVT_95_addImmOperands, 1, CVT_Done },
// Convert__regX0__Reg1_0__imm_95_0
{ CVT_regX0, 0, CVT_95_Reg, 1, CVT_imm_95_0, 0, CVT_Done },
// Convert__regX0__Reg1_0__SImm121_1
{ CVT_regX0, 0, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
// Convert__regX0__Reg1_2__SImm121_0
{ CVT_regX0, 0, CVT_95_Reg, 3, CVT_95_addImmOperands, 1, CVT_Done },
// Convert__Reg1_1__PseudoJumpSymbol1_0
{ CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
// Convert__Reg1_0__BareSymbol1_1
{ CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
// Convert__Reg1_0__regX0__SImm121_1
{ CVT_95_Reg, 1, CVT_regX0, 0, CVT_95_addImmOperands, 2, CVT_Done },
// Convert__Reg1_0__ImmXLenLI1_1
{ CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
// Convert__Reg1_0__UImm20LUI1_1
{ CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
// Convert__Reg1_0__regX0__Reg1_1
{ CVT_95_Reg, 1, CVT_regX0, 0, CVT_95_Reg, 2, CVT_Done },
// Convert__regX0__regX0__imm_95_0
{ CVT_regX0, 0, CVT_regX0, 0, CVT_imm_95_0, 0, CVT_Done },
// Convert__Reg1_0__Reg1_1__imm_95__MINUS_1
{ CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_imm_95__MINUS_1, 0, CVT_Done },
// Convert__regX0__regX0__regX5
{ CVT_regX0, 0, CVT_regX0, 0, CVT_regX5, 0, CVT_Done },
// Convert__regX0__regX0__regX2
{ CVT_regX0, 0, CVT_regX0, 0, CVT_regX2, 0, CVT_Done },
// Convert__regX0__regX0__regX3
{ CVT_regX0, 0, CVT_regX0, 0, CVT_regX3, 0, CVT_Done },
// Convert__regX0__regX0__regX4
{ CVT_regX0, 0, CVT_regX0, 0, CVT_regX4, 0, CVT_Done },
// Convert__imm_95_1__imm_95_0
{ CVT_imm_95_1, 0, CVT_imm_95_0, 0, CVT_Done },
// Convert__Reg1_2__SImm12Lsb000001_0
{ CVT_95_Reg, 3, CVT_95_addImmOperands, 1, CVT_Done },
// Convert__Reg1_0__imm_95_3072__regX0
{ CVT_95_Reg, 1, CVT_imm_95_3072, 0, CVT_regX0, 0, CVT_Done },
// Convert__Reg1_0__imm_95_3200__regX0
{ CVT_95_Reg, 1, CVT_imm_95_3200, 0, CVT_regX0, 0, CVT_Done },
// Convert__Reg1_0__imm_95_3074__regX0
{ CVT_95_Reg, 1, CVT_imm_95_3074, 0, CVT_regX0, 0, CVT_Done },
// Convert__Reg1_0__imm_95_3202__regX0
{ CVT_95_Reg, 1, CVT_imm_95_3202, 0, CVT_regX0, 0, CVT_Done },
// Convert__Reg1_0__imm_95_3073__regX0
{ CVT_95_Reg, 1, CVT_imm_95_3073, 0, CVT_regX0, 0, CVT_Done },
// Convert__Reg1_0__imm_95_3201__regX0
{ CVT_95_Reg, 1, CVT_imm_95_3201, 0, CVT_regX0, 0, CVT_Done },
// Convert__regX0__regX1__imm_95_0
{ CVT_regX0, 0, CVT_regX1, 0, CVT_imm_95_0, 0, CVT_Done },
// Convert__Reg1_0__Reg1_1__UImm51_2
{ CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
// Convert__Reg1_0__Reg1_1__imm_95_1
{ CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_imm_95_1, 0, CVT_Done },
// Convert__Reg1_0__Reg1_1__regX0
{ CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_regX0, 0, CVT_Done },
// Convert__Reg1_0__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3
{ CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addRegOperands_95_defaultMaskRegOp, 4, CVT_Done },
// Convert__Reg1_0__Reg1_1__SImm51_2__imm_95_0
{ CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_imm_95_0, 0, CVT_Done },
// Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0
{ CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_Done },
// Convert__Reg1_0__Reg1_1__SImm51_2__RVVMaskRegOpOperand1_3
{ CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addRegOperands_95_defaultMaskRegOp, 4, CVT_Done },
// Convert__Reg1_0__Reg1_1__RVVMaskRegOpOperand1_2
{ CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addRegOperands_95_defaultMaskRegOp, 3, CVT_Done },
// Convert__Reg1_0__Reg1_1__Reg1_1__reg0
{ CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 2, CVT_reg0, 0, CVT_Done },
// Convert__Reg1_0__Reg1_1__Reg1_1__RVVMaskRegOpOperand1_2
{ CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 2, CVT_95_addRegOperands_95_defaultMaskRegOp, 3, CVT_Done },
// Convert__Reg1_0__RVVMaskRegOpOperand1_1
{ CVT_95_Reg, 1, CVT_95_addRegOperands_95_defaultMaskRegOp, 2, CVT_Done },
// Convert__Reg1_0__Reg1_2
{ CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_Done },
// Convert__Reg1_0__Reg1_2__RVVMaskRegOpOperand1_4
{ CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_addRegOperands_95_defaultMaskRegOp, 5, CVT_Done },
// Convert__Reg1_0__Reg1_2__Reg1_4__RVVMaskRegOpOperand1_5
{ CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addRegOperands_95_defaultMaskRegOp, 6, CVT_Done },
// Convert__Reg1_0__Reg1_1__SImm51_2
{ CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
// Convert__Reg1_0__Reg1_0__Reg1_0
{ CVT_95_Reg, 1, CVT_95_Reg, 1, CVT_95_Reg, 1, CVT_Done },
// Convert__Reg1_0__Reg1_2__Reg1_1__RVVMaskRegOpOperand1_3
{ CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_95_addRegOperands_95_defaultMaskRegOp, 4, CVT_Done },
// Convert__Reg1_0__Reg1_1__SImm5Plus11_2__RVVMaskRegOpOperand1_3
{ CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addRegOperands_95_defaultMaskRegOp, 4, CVT_Done },
// Convert__Reg1_0__Reg1_4__Reg1_1__Reg1_2__RVVMaskRegOpOperand1_3
{ CVT_95_Reg, 1, CVT_95_Reg, 5, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addRegOperands_95_defaultMaskRegOp, 4, CVT_Done },
// Convert__Reg1_0__SImm51_1
{ CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
// Convert__Reg1_0__Reg1_1__UImm51_2__RVVMaskRegOpOperand1_3
{ CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_addRegOperands_95_defaultMaskRegOp, 4, CVT_Done },
// Convert__Reg1_0__Reg1_1__regX0__reg0
{ CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_regX0, 0, CVT_reg0, 0, CVT_Done },
// Convert__Reg1_0__Reg1_1__regX0__RVVMaskRegOpOperand1_2
{ CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_regX0, 0, CVT_95_addRegOperands_95_defaultMaskRegOp, 3, CVT_Done },
// Convert__Reg1_0__Reg1_1__imm_95__MINUS_1__reg0
{ CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_imm_95__MINUS_1, 0, CVT_reg0, 0, CVT_Done },
// Convert__Reg1_0__Reg1_1__imm_95__MINUS_1__RVVMaskRegOpOperand1_2
{ CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_imm_95__MINUS_1, 0, CVT_95_addRegOperands_95_defaultMaskRegOp, 3, CVT_Done },
// Convert__Reg1_0__UImm51_1__VTypeI101_2
{ CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_95_addVTypeIOperands, 3, CVT_Done },
// Convert__Reg1_0__Reg1_1__VTypeI111_2
{ CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addVTypeIOperands, 3, CVT_Done },
// Convert__Reg1_0__Reg1_1__imm_95_255
{ CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_imm_95_255, 0, CVT_Done },
};
void RISCVAsmParser::
convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
const OperandVector &Operands,
const SmallBitVector &OptionalOperandsMask) {
assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
const uint8_t *Converter = ConversionTable[Kind];
unsigned DefaultsOffset[8] = { 0 };
assert(OptionalOperandsMask.size() == 7);
for (unsigned i = 0, NumDefaults = 0; i < 7; ++i) {
DefaultsOffset[i + 1] = NumDefaults;
NumDefaults += (OptionalOperandsMask[i] ? 1 : 0);
}
unsigned OpIdx;
Inst.setOpcode(Opcode);
for (const uint8_t *p = Converter; *p; p += 2) {
OpIdx = *(p + 1) - DefaultsOffset[*(p + 1)];
switch (*p) {
default: llvm_unreachable("invalid conversion entry!");
case CVT_Reg:
static_cast<RISCVOperand &>(*Operands[OpIdx]).addRegOperands(Inst, 1);
break;
case CVT_Tied: {
assert(OpIdx < (size_t)(std::end(TiedAsmOperandTable) -
std::begin(TiedAsmOperandTable)) &&
"Tied operand not found");
unsigned TiedResOpnd = TiedAsmOperandTable[OpIdx][0];
if (TiedResOpnd != (uint8_t)-1)
Inst.addOperand(Inst.getOperand(TiedResOpnd));
break;
}
case CVT_95_addImmOperands:
static_cast<RISCVOperand &>(*Operands[OpIdx]).addImmOperands(Inst, 1);
break;
case CVT_95_Reg:
static_cast<RISCVOperand &>(*Operands[OpIdx]).addRegOperands(Inst, 1);
break;
case CVT_95_addRegOperands:
static_cast<RISCVOperand &>(*Operands[OpIdx]).addRegOperands(Inst, 1);
break;
case CVT_regX0:
Inst.addOperand(MCOperand::createReg(RISCV::X0));
break;
case CVT_imm_95_0:
Inst.addOperand(MCOperand::createImm(0));
break;
case CVT_regX5:
Inst.addOperand(MCOperand::createReg(RISCV::X5));
break;
case CVT_regX2:
Inst.addOperand(MCOperand::createReg(RISCV::X2));
break;
case CVT_regX3:
Inst.addOperand(MCOperand::createReg(RISCV::X3));
break;
case CVT_regX4:
Inst.addOperand(MCOperand::createReg(RISCV::X4));
break;
case CVT_95_addCSRSystemRegisterOperands:
static_cast<RISCVOperand &>(*Operands[OpIdx]).addCSRSystemRegisterOperands(Inst, 1);
break;
case CVT_imm_95_7:
Inst.addOperand(MCOperand::createImm(7));
break;
case CVT_95_addFRMArgOperands:
static_cast<RISCVOperand &>(*Operands[OpIdx]).addFRMArgOperands(Inst, 1);
break;
case CVT_imm_95_15:
Inst.addOperand(MCOperand::createImm(15));
break;
case CVT_95_addFenceArgOperands:
static_cast<RISCVOperand &>(*Operands[OpIdx]).addFenceArgOperands(Inst, 1);
break;
case CVT_imm_95_3:
Inst.addOperand(MCOperand::createImm(3));
break;
case CVT_imm_95_1:
Inst.addOperand(MCOperand::createImm(1));
break;
case CVT_imm_95_2:
Inst.addOperand(MCOperand::createImm(2));
break;
case CVT_regX1:
Inst.addOperand(MCOperand::createReg(RISCV::X1));
break;
case CVT_imm_95__MINUS_1:
Inst.addOperand(MCOperand::createImm(-1));
break;
case CVT_imm_95_3072:
Inst.addOperand(MCOperand::createImm(3072));
break;
case CVT_imm_95_3200:
Inst.addOperand(MCOperand::createImm(3200));
break;
case CVT_imm_95_3074:
Inst.addOperand(MCOperand::createImm(3074));
break;
case CVT_imm_95_3202:
Inst.addOperand(MCOperand::createImm(3202));
break;
case CVT_imm_95_3073:
Inst.addOperand(MCOperand::createImm(3073));
break;
case CVT_imm_95_3201:
Inst.addOperand(MCOperand::createImm(3201));
break;
case CVT_95_addRegOperands_95_defaultMaskRegOp:
if (OptionalOperandsMask[*(p + 1) - 1]) {
defaultMaskRegOp()->addRegOperands(Inst, 1);
} else {
static_cast<RISCVOperand &>(*Operands[OpIdx]).addRegOperands(Inst, 1);
}
break;
case CVT_reg0:
Inst.addOperand(MCOperand::createReg(0));
break;
case CVT_95_addVTypeIOperands:
static_cast<RISCVOperand &>(*Operands[OpIdx]).addVTypeIOperands(Inst, 1);
break;
case CVT_imm_95_255:
Inst.addOperand(MCOperand::createImm(255));
break;
}
}
}
void RISCVAsmParser::
convertToMapAndConstraints(unsigned Kind,
const OperandVector &Operands) {
assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
unsigned NumMCOperands = 0;
const uint8_t *Converter = ConversionTable[Kind];
for (const uint8_t *p = Converter; *p; p += 2) {
switch (*p) {
default: llvm_unreachable("invalid conversion entry!");
case CVT_Reg:
Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
Operands[*(p + 1)]->setConstraint("r");
++NumMCOperands;
break;
case CVT_Tied:
++NumMCOperands;
break;
case CVT_95_addImmOperands:
Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
Operands[*(p + 1)]->setConstraint("m");
NumMCOperands += 1;
break;
case CVT_95_Reg:
Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
Operands[*(p + 1)]->setConstraint("r");
NumMCOperands += 1;
break;
case CVT_95_addRegOperands:
Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
Operands[*(p + 1)]->setConstraint("m");
NumMCOperands += 1;
break;
case CVT_regX0:
Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
Operands[*(p + 1)]->setConstraint("m");
++NumMCOperands;
break;
case CVT_imm_95_0:
Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
Operands[*(p + 1)]->setConstraint("");
++NumMCOperands;
break;
case CVT_regX5:
Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
Operands[*(p + 1)]->setConstraint("m");
++NumMCOperands;
break;
case CVT_regX2:
Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
Operands[*(p + 1)]->setConstraint("m");
++NumMCOperands;
break;
case CVT_regX3:
Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
Operands[*(p + 1)]->setConstraint("m");
++NumMCOperands;
break;
case CVT_regX4:
Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
Operands[*(p + 1)]->setConstraint("m");
++NumMCOperands;
break;
case CVT_95_addCSRSystemRegisterOperands:
Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
Operands[*(p + 1)]->setConstraint("m");
NumMCOperands += 1;
break;
case CVT_imm_95_7:
Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
Operands[*(p + 1)]->setConstraint("");
++NumMCOperands;
break;
case CVT_95_addFRMArgOperands:
Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
Operands[*(p + 1)]->setConstraint("m");
NumMCOperands += 1;
break;
case CVT_imm_95_15:
Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
Operands[*(p + 1)]->setConstraint("");
++NumMCOperands;
break;
case CVT_95_addFenceArgOperands:
Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
Operands[*(p + 1)]->setConstraint("m");
NumMCOperands += 1;
break;
case CVT_imm_95_3:
Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
Operands[*(p + 1)]->setConstraint("");
++NumMCOperands;
break;
case CVT_imm_95_1:
Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
Operands[*(p + 1)]->setConstraint("");
++NumMCOperands;
break;
case CVT_imm_95_2:
Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
Operands[*(p + 1)]->setConstraint("");
++NumMCOperands;
break;
case CVT_regX1:
Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
Operands[*(p + 1)]->setConstraint("m");
++NumMCOperands;
break;
case CVT_imm_95__MINUS_1:
Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
Operands[*(p + 1)]->setConstraint("");
++NumMCOperands;
break;
case CVT_imm_95_3072:
Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
Operands[*(p + 1)]->setConstraint("");
++NumMCOperands;
break;
case CVT_imm_95_3200:
Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
Operands[*(p + 1)]->setConstraint("");
++NumMCOperands;
break;
case CVT_imm_95_3074:
Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
Operands[*(p + 1)]->setConstraint("");
++NumMCOperands;
break;
case CVT_imm_95_3202:
Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
Operands[*(p + 1)]->setConstraint("");
++NumMCOperands;
break;
case CVT_imm_95_3073:
Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
Operands[*(p + 1)]->setConstraint("");
++NumMCOperands;
break;
case CVT_imm_95_3201:
Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
Operands[*(p + 1)]->setConstraint("");
++NumMCOperands;
break;
case CVT_95_addRegOperands_95_defaultMaskRegOp:
Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
Operands[*(p + 1)]->setConstraint("m");
NumMCOperands += 1;
break;
case CVT_reg0:
Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
Operands[*(p + 1)]->setConstraint("m");
++NumMCOperands;
break;
case CVT_95_addVTypeIOperands:
Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
Operands[*(p + 1)]->setConstraint("m");
NumMCOperands += 1;
break;
case CVT_imm_95_255:
Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
Operands[*(p + 1)]->setConstraint("");
++NumMCOperands;
break;
}
}
}
namespace {
/// MatchClassKind - The kinds of classes which participate in
/// instruction matching.
enum MatchClassKind {
InvalidMatchClass = 0,
OptionalMatchClass = 1,
MCK__40_, // '('
MCK__41_, // ')'
MCK_LAST_TOKEN = MCK__41_,
MCK_Reg69, // derived register class
MCK_Reg66, // derived register class
MCK_Reg63, // derived register class
MCK_Reg60, // derived register class
MCK_Reg57, // derived register class
MCK_Reg54, // derived register class
MCK_Reg51, // derived register class
MCK_Reg48, // derived register class
MCK_Reg45, // derived register class
MCK_Reg42, // derived register class
MCK_Reg39, // derived register class
MCK_Reg30, // derived register class
MCK_Reg28, // derived register class
MCK_Reg24, // derived register class
MCK_Reg21, // derived register class
MCK_Reg18, // derived register class
MCK_GPRX0, // register class 'GPRX0'
MCK_SP, // register class 'SP'
MCK_VMV0, // register class 'VMV0,V0'
MCK_Reg36, // derived register class
MCK_VCSR, // register class 'VCSR'
MCK_VRM8NoV0, // register class 'VRM8NoV0'
MCK_Reg35, // derived register class
MCK_VRM8, // register class 'VRM8'
MCK_Reg9, // derived register class
MCK_VRN2M4NoV0, // register class 'VRN2M4NoV0'
MCK_Reg34, // derived register class
MCK_VRM4NoV0, // register class 'VRM4NoV0'
MCK_VRN2M4, // register class 'VRN2M4'
MCK_FPR32C, // register class 'FPR32C'
MCK_FPR64C, // register class 'FPR64C'
MCK_GPRC, // register class 'GPRC'
MCK_VRM4, // register class 'VRM4'
MCK_VRN4M2NoV0, // register class 'VRN4M2NoV0'
MCK_Reg33, // derived register class
MCK_VRN3M2NoV0, // register class 'VRN3M2NoV0'
MCK_VRN4M2, // register class 'VRN4M2'
MCK_Reg32, // derived register class
MCK_GPRTC, // register class 'GPRTC'
MCK_VRN2M2NoV0, // register class 'VRN2M2NoV0'
MCK_VRN3M2, // register class 'VRN3M2'
MCK_Reg31, // derived register class
MCK_VRM2NoV0, // register class 'VRM2NoV0'
MCK_VRN2M2, // register class 'VRN2M2'
MCK_GPRPF64, // register class 'GPRPF64'
MCK_VRM2, // register class 'VRM2'
MCK_VRN8M1NoV0, // register class 'VRN8M1NoV0'
MCK_VRN7M1NoV0, // register class 'VRN7M1NoV0'
MCK_VRN8M1, // register class 'VRN8M1'
MCK_GPRJALR, // register class 'GPRJALR'
MCK_VRN6M1NoV0, // register class 'VRN6M1NoV0'
MCK_VRN7M1, // register class 'VRN7M1'
MCK_VRN5M1NoV0, // register class 'VRN5M1NoV0'
MCK_VRN6M1, // register class 'VRN6M1'
MCK_VRN4M1NoV0, // register class 'VRN4M1NoV0'
MCK_VRN5M1, // register class 'VRN5M1'
MCK_VRN3M1NoV0, // register class 'VRN3M1NoV0'
MCK_VRN4M1, // register class 'VRN4M1'
MCK_GPRNoX0X2, // register class 'GPRNoX0X2'
MCK_VRN2M1NoV0, // register class 'VRN2M1NoV0'
MCK_VRN3M1, // register class 'VRN3M1'
MCK_GPRNoX0, // register class 'GPRNoX0'
MCK_VRN2M1, // register class 'VRN2M1'
MCK_VRNoV0, // register class 'VRNoV0'
MCK_FPR16, // register class 'FPR16'
MCK_FPR32, // register class 'FPR32'
MCK_FPR64, // register class 'FPR64'
MCK_GPR, // register class 'GPR,GPRF16,GPRF32,GPRF64'
MCK_VM, // register class 'VM,VR'
MCK_AnyReg, // register class 'AnyReg'
MCK_LAST_REGISTER = MCK_AnyReg,
MCK_BareSymbol, // user defined class 'BareSymbol'
MCK_CLUIImm, // user defined class 'CLUIImmAsmOperand'
MCK_CSRSystemRegister, // user defined class 'CSRSystemRegister'
MCK_CallSymbol, // user defined class 'CallSymbol'
MCK_FRMArg, // user defined class 'FRMArg'
MCK_FenceArg, // user defined class 'FenceArg'
MCK_GPRAsFPR, // user defined class 'GPRAsFPR'
MCK_GPRF64AsFPR, // user defined class 'GPRF64AsFPR'
MCK_GPRPF64AsFPR, // user defined class 'GPRPF64AsFPR'
MCK_Imm, // user defined class 'ImmAsmOperand'
MCK_ImmZero, // user defined class 'ImmZeroAsmOperand'
MCK_InsnDirectiveOpcode, // user defined class 'InsnDirectiveOpcode'
MCK_PseudoJumpSymbol, // user defined class 'PseudoJumpSymbol'
MCK_RnumArg, // user defined class 'RnumArg'
MCK_SImm5Plus1, // user defined class 'SImm5Plus1AsmOperand'
MCK_SImm21Lsb0JAL, // user defined class 'Simm21Lsb0JALAsmOperand'
MCK_TPRelAddSymbol, // user defined class 'TPRelAddSymbol'
MCK_UImmLog2XLen, // user defined class 'UImmLog2XLenAsmOperand'
MCK_UImmLog2XLenHalf, // user defined class 'UImmLog2XLenHalfAsmOperand'
MCK_UImmLog2XLenNonZero, // user defined class 'UImmLog2XLenNonZeroAsmOperand'
MCK_RVVMaskRegOpOperand, // user defined class 'VMaskAsmOperand'
MCK_ZeroOffsetMemOpOperand, // user defined class 'ZeroOffsetMemOpOperand'
MCK_UImm2, // user defined class 'anonymous_4648'
MCK_UImm3, // user defined class 'anonymous_4649'
MCK_UImm5, // user defined class 'anonymous_4650'
MCK_UImm7, // user defined class 'anonymous_4651'
MCK_SImm12, // user defined class 'anonymous_4652'
MCK_SImm13Lsb0, // user defined class 'anonymous_4653'
MCK_UImm20LUI, // user defined class 'anonymous_4654'
MCK_UImm20AUIPC, // user defined class 'anonymous_4655'
MCK_ImmXLenLI, // user defined class 'anonymous_4656'
MCK_SImm12Lsb00000, // user defined class 'anonymous_49973'
MCK_SImm6, // user defined class 'anonymous_5403'
MCK_SImm6NonZero, // user defined class 'anonymous_5404'
MCK_UImm7Lsb00, // user defined class 'anonymous_5405'
MCK_UImm8Lsb00, // user defined class 'anonymous_5406'
MCK_UImm8Lsb000, // user defined class 'anonymous_5407'
MCK_SImm9Lsb0, // user defined class 'anonymous_5408'
MCK_UImm9Lsb000, // user defined class 'anonymous_5409'
MCK_UImm10Lsb00NonZero, // user defined class 'anonymous_5410'
MCK_SImm10Lsb0000NonZero, // user defined class 'anonymous_5411'
MCK_SImm12Lsb0, // user defined class 'anonymous_5412'
MCK_VTypeI10, // user defined class 'anonymous_5639'
MCK_VTypeI11, // user defined class 'anonymous_5640'
MCK_SImm5, // user defined class 'anonymous_5641'
NumMatchClassKinds
};
} // end anonymous namespace
static unsigned getDiagKindFromRegisterClass(MatchClassKind RegisterClass) {
return MCTargetAsmParser::Match_InvalidOperand;
}
static MatchClassKind matchTokenString(StringRef Name) {
switch (Name.size()) {
default: break;
case 1: // 2 strings to match.
switch (Name[0]) {
default: break;
case '(': // 1 string to match.
return MCK__40_; // "("
case ')': // 1 string to match.
return MCK__41_; // ")"
}
break;
}
return InvalidMatchClass;
}
/// isSubclass - Compute whether \p A is a subclass of \p B.
static bool isSubclass(MatchClassKind A, MatchClassKind B) {
if (A == B)
return true;
switch (A) {
default:
return false;
case MCK_Reg69:
return B == MCK_VRN8M1;
case MCK_Reg66:
return B == MCK_VRN7M1;
case MCK_Reg63:
return B == MCK_VRN6M1;
case MCK_Reg60:
return B == MCK_VRN5M1;
case MCK_Reg57:
return B == MCK_VRN4M2;
case MCK_Reg54:
return B == MCK_VRN4M1;
case MCK_Reg51:
return B == MCK_VRN3M2;
case MCK_Reg48:
return B == MCK_VRN3M1;
case MCK_Reg45:
return B == MCK_VRN2M4;
case MCK_Reg42:
return B == MCK_VRN2M2;
case MCK_Reg39:
return B == MCK_VRN2M1;
case MCK_Reg30:
switch (B) {
default: return false;
case MCK_Reg31: return true;
case MCK_GPRPF64: return true;
}
case MCK_Reg28:
return B == MCK_GPRPF64;
case MCK_Reg24:
return B == MCK_VRM8;
case MCK_Reg21:
return B == MCK_VRM4;
case MCK_Reg18:
return B == MCK_VRM2;
case MCK_GPRX0:
switch (B) {
default: return false;
case MCK_GPR: return true;
case MCK_AnyReg: return true;
}
case MCK_SP:
switch (B) {
default: return false;
case MCK_GPRNoX0: return true;
case MCK_GPR: return true;
case MCK_AnyReg: return true;
}
case MCK_VMV0:
switch (B) {
default: return false;
case MCK_VM: return true;
case MCK_AnyReg: return true;
}
case MCK_Reg36:
switch (B) {
default: return false;
case MCK_Reg35: return true;
case MCK_Reg34: return true;
case MCK_Reg33: return true;
case MCK_Reg32: return true;
case MCK_Reg31: return true;
case MCK_GPRPF64: return true;
}
case MCK_VRM8NoV0:
return B == MCK_VRM8;
case MCK_Reg35:
switch (B) {
default: return false;
case MCK_Reg33: return true;
case MCK_Reg32: return true;
case MCK_Reg31: return true;
case MCK_GPRPF64: return true;
}
case MCK_Reg9:
switch (B) {
default: return false;
case MCK_GPRC: return true;
case MCK_GPRTC: return true;
case MCK_GPRJALR: return true;
case MCK_GPRNoX0X2: return true;
case MCK_GPRNoX0: return true;
case MCK_GPR: return true;
case MCK_AnyReg: return true;
}
case MCK_VRN2M4NoV0:
return B == MCK_VRN2M4;
case MCK_Reg34:
switch (B) {
default: return false;
case MCK_Reg33: return true;
case MCK_Reg32: return true;
case MCK_Reg31: return true;
case MCK_GPRPF64: return true;
}
case MCK_VRM4NoV0:
return B == MCK_VRM4;
case MCK_FPR32C:
return B == MCK_FPR32;
case MCK_FPR64C:
switch (B) {
default: return false;
case MCK_FPR64: return true;
case MCK_AnyReg: return true;
}
case MCK_GPRC:
switch (B) {
default: return false;
case MCK_GPRJALR: return true;
case MCK_GPRNoX0X2: return true;
case MCK_GPRNoX0: return true;
case MCK_GPR: return true;
case MCK_AnyReg: return true;
}
case MCK_VRN4M2NoV0:
return B == MCK_VRN4M2;
case MCK_Reg33:
switch (B) {
default: return false;
case MCK_Reg32: return true;
case MCK_Reg31: return true;
case MCK_GPRPF64: return true;
}
case MCK_VRN3M2NoV0:
return B == MCK_VRN3M2;
case MCK_Reg32:
switch (B) {
default: return false;
case MCK_Reg31: return true;
case MCK_GPRPF64: return true;
}
case MCK_GPRTC:
switch (B) {
default: return false;
case MCK_GPRJALR: return true;
case MCK_GPRNoX0X2: return true;
case MCK_GPRNoX0: return true;
case MCK_GPR: return true;
case MCK_AnyReg: return true;
}
case MCK_VRN2M2NoV0:
return B == MCK_VRN2M2;
case MCK_Reg31:
return B == MCK_GPRPF64;
case MCK_VRM2NoV0:
return B == MCK_VRM2;
case MCK_VRN8M1NoV0:
return B == MCK_VRN8M1;
case MCK_VRN7M1NoV0:
return B == MCK_VRN7M1;
case MCK_GPRJALR:
switch (B) {
default: return false;
case MCK_GPRNoX0X2: return true;
case MCK_GPRNoX0: return true;
case MCK_GPR: return true;
case MCK_AnyReg: return true;
}
case MCK_VRN6M1NoV0:
return B == MCK_VRN6M1;
case MCK_VRN5M1NoV0:
return B == MCK_VRN5M1;
case MCK_VRN4M1NoV0:
return B == MCK_VRN4M1;
case MCK_VRN3M1NoV0:
return B == MCK_VRN3M1;
case MCK_GPRNoX0X2:
switch (B) {
default: return false;
case MCK_GPRNoX0: return true;
case MCK_GPR: return true;
case MCK_AnyReg: return true;
}
case MCK_VRN2M1NoV0:
return B == MCK_VRN2M1;
case MCK_GPRNoX0:
switch (B) {
default: return false;
case MCK_GPR: return true;
case MCK_AnyReg: return true;
}
case MCK_VRNoV0:
switch (B) {
default: return false;
case MCK_VM: return true;
case MCK_AnyReg: return true;
}
case MCK_FPR64:
return B == MCK_AnyReg;
case MCK_GPR:
return B == MCK_AnyReg;
case MCK_VM:
return B == MCK_AnyReg;
case MCK_RVVMaskRegOpOperand:
return B == OptionalMatchClass;
}
}
static unsigned validateOperandClass(MCParsedAsmOperand &GOp, MatchClassKind Kind) {
RISCVOperand &Operand = (RISCVOperand &)GOp;
if (Kind == InvalidMatchClass)
return MCTargetAsmParser::Match_InvalidOperand;
if (Operand.isToken() && Kind <= MCK_LAST_TOKEN)
return isSubclass(matchTokenString(Operand.getToken()), Kind) ?
MCTargetAsmParser::Match_Success :
MCTargetAsmParser::Match_InvalidOperand;
switch (Kind) {
default: break;
// 'BareSymbol' class
case MCK_BareSymbol: {
DiagnosticPredicate DP(Operand.isBareSymbol());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
if (DP.isNearMatch())
return RISCVAsmParser::Match_InvalidBareSymbol;
break;
}
// 'CLUIImm' class
case MCK_CLUIImm: {
DiagnosticPredicate DP(Operand.isCLUIImm());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
if (DP.isNearMatch())
return RISCVAsmParser::Match_InvalidCLUIImm;
break;
}
// 'CSRSystemRegister' class
case MCK_CSRSystemRegister: {
DiagnosticPredicate DP(Operand.isCSRSystemRegister());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
if (DP.isNearMatch())
return RISCVAsmParser::Match_InvalidCSRSystemRegister;
break;
}
// 'CallSymbol' class
case MCK_CallSymbol: {
DiagnosticPredicate DP(Operand.isCallSymbol());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
if (DP.isNearMatch())
return RISCVAsmParser::Match_InvalidCallSymbol;
break;
}
// 'FRMArg' class
case MCK_FRMArg: {
DiagnosticPredicate DP(Operand.isFRMArg());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
if (DP.isNearMatch())
return RISCVAsmParser::Match_InvalidFRMArg;
break;
}
// 'FenceArg' class
case MCK_FenceArg: {
DiagnosticPredicate DP(Operand.isFenceArg());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
if (DP.isNearMatch())
return RISCVAsmParser::Match_InvalidFenceArg;
break;
}
// 'GPRAsFPR' class
case MCK_GPRAsFPR: {
DiagnosticPredicate DP(Operand.isGPRAsFPR());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
break;
}
// 'GPRF64AsFPR' class
case MCK_GPRF64AsFPR: {
DiagnosticPredicate DP(Operand.isGPRF64AsFPR());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
break;
}
// 'GPRPF64AsFPR' class
case MCK_GPRPF64AsFPR: {
DiagnosticPredicate DP(Operand.isGPRPF64AsFPR());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
break;
}
// 'Imm' class
case MCK_Imm: {
DiagnosticPredicate DP(Operand.isImm());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
break;
}
// 'ImmZero' class
case MCK_ImmZero: {
DiagnosticPredicate DP(Operand.isImmZero());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
if (DP.isNearMatch())
return RISCVAsmParser::Match_InvalidImmZero;
break;
}
// 'InsnDirectiveOpcode' class
case MCK_InsnDirectiveOpcode: {
DiagnosticPredicate DP(Operand.isImm());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
break;
}
// 'PseudoJumpSymbol' class
case MCK_PseudoJumpSymbol: {
DiagnosticPredicate DP(Operand.isPseudoJumpSymbol());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
if (DP.isNearMatch())
return RISCVAsmParser::Match_InvalidPseudoJumpSymbol;
break;
}
// 'RnumArg' class
case MCK_RnumArg: {
DiagnosticPredicate DP(Operand.isRnumArg());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
if (DP.isNearMatch())
return RISCVAsmParser::Match_InvalidRnumArg;
break;
}
// 'SImm5Plus1' class
case MCK_SImm5Plus1: {
DiagnosticPredicate DP(Operand.isSImm5Plus1());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
if (DP.isNearMatch())
return RISCVAsmParser::Match_InvalidSImm5Plus1;
break;
}
// 'SImm21Lsb0JAL' class
case MCK_SImm21Lsb0JAL: {
DiagnosticPredicate DP(Operand.isSImm21Lsb0JAL());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
if (DP.isNearMatch())
return RISCVAsmParser::Match_InvalidSImm21Lsb0JAL;
break;
}
// 'TPRelAddSymbol' class
case MCK_TPRelAddSymbol: {
DiagnosticPredicate DP(Operand.isTPRelAddSymbol());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
if (DP.isNearMatch())
return RISCVAsmParser::Match_InvalidTPRelAddSymbol;
break;
}
// 'UImmLog2XLen' class
case MCK_UImmLog2XLen: {
DiagnosticPredicate DP(Operand.isUImmLog2XLen());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
if (DP.isNearMatch())
return RISCVAsmParser::Match_InvalidUImmLog2XLen;
break;
}
// 'UImmLog2XLenHalf' class
case MCK_UImmLog2XLenHalf: {
DiagnosticPredicate DP(Operand.isUImmLog2XLenHalf());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
if (DP.isNearMatch())
return RISCVAsmParser::Match_InvalidUImmLog2XLenHalf;
break;
}
// 'UImmLog2XLenNonZero' class
case MCK_UImmLog2XLenNonZero: {
DiagnosticPredicate DP(Operand.isUImmLog2XLenNonZero());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
if (DP.isNearMatch())
return RISCVAsmParser::Match_InvalidUImmLog2XLenNonZero;
break;
}
// 'RVVMaskRegOpOperand' class
case MCK_RVVMaskRegOpOperand: {
DiagnosticPredicate DP(Operand.isV0Reg());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
if (DP.isNearMatch())
return RISCVAsmParser::Match_InvalidVMaskRegister;
break;
}
// 'ZeroOffsetMemOpOperand' class
case MCK_ZeroOffsetMemOpOperand: {
DiagnosticPredicate DP(Operand.isGPR());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
break;
}
// 'UImm2' class
case MCK_UImm2: {
DiagnosticPredicate DP(Operand.isUImm2());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
if (DP.isNearMatch())
return RISCVAsmParser::Match_InvalidUImm2;
break;
}
// 'UImm3' class
case MCK_UImm3: {
DiagnosticPredicate DP(Operand.isUImm3());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
if (DP.isNearMatch())
return RISCVAsmParser::Match_InvalidUImm3;
break;
}
// 'UImm5' class
case MCK_UImm5: {
DiagnosticPredicate DP(Operand.isUImm5());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
if (DP.isNearMatch())
return RISCVAsmParser::Match_InvalidUImm5;
break;
}
// 'UImm7' class
case MCK_UImm7: {
DiagnosticPredicate DP(Operand.isUImm7());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
if (DP.isNearMatch())
return RISCVAsmParser::Match_InvalidUImm7;
break;
}
// 'SImm12' class
case MCK_SImm12: {
DiagnosticPredicate DP(Operand.isSImm12());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
if (DP.isNearMatch())
return RISCVAsmParser::Match_InvalidSImm12;
break;
}
// 'SImm13Lsb0' class
case MCK_SImm13Lsb0: {
DiagnosticPredicate DP(Operand.isSImm13Lsb0());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
if (DP.isNearMatch())
return RISCVAsmParser::Match_InvalidSImm13Lsb0;
break;
}
// 'UImm20LUI' class
case MCK_UImm20LUI: {
DiagnosticPredicate DP(Operand.isUImm20LUI());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
if (DP.isNearMatch())
return RISCVAsmParser::Match_InvalidUImm20LUI;
break;
}
// 'UImm20AUIPC' class
case MCK_UImm20AUIPC: {
DiagnosticPredicate DP(Operand.isUImm20AUIPC());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
if (DP.isNearMatch())
return RISCVAsmParser::Match_InvalidUImm20AUIPC;
break;
}
// 'ImmXLenLI' class
case MCK_ImmXLenLI: {
DiagnosticPredicate DP(Operand.isImmXLenLI());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
if (DP.isNearMatch())
return RISCVAsmParser::Match_InvalidImmXLenLI;
break;
}
// 'SImm12Lsb00000' class
case MCK_SImm12Lsb00000: {
DiagnosticPredicate DP(Operand.isSImm12Lsb00000());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
if (DP.isNearMatch())
return RISCVAsmParser::Match_InvalidSImm12Lsb00000;
break;
}
// 'SImm6' class
case MCK_SImm6: {
DiagnosticPredicate DP(Operand.isSImm6());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
if (DP.isNearMatch())
return RISCVAsmParser::Match_InvalidSImm6;
break;
}
// 'SImm6NonZero' class
case MCK_SImm6NonZero: {
DiagnosticPredicate DP(Operand.isSImm6NonZero());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
if (DP.isNearMatch())
return RISCVAsmParser::Match_InvalidSImm6NonZero;
break;
}
// 'UImm7Lsb00' class
case MCK_UImm7Lsb00: {
DiagnosticPredicate DP(Operand.isUImm7Lsb00());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
if (DP.isNearMatch())
return RISCVAsmParser::Match_InvalidUImm7Lsb00;
break;
}
// 'UImm8Lsb00' class
case MCK_UImm8Lsb00: {
DiagnosticPredicate DP(Operand.isUImm8Lsb00());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
if (DP.isNearMatch())
return RISCVAsmParser::Match_InvalidUImm8Lsb00;
break;
}
// 'UImm8Lsb000' class
case MCK_UImm8Lsb000: {
DiagnosticPredicate DP(Operand.isUImm8Lsb000());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
if (DP.isNearMatch())
return RISCVAsmParser::Match_InvalidUImm8Lsb000;
break;
}
// 'SImm9Lsb0' class
case MCK_SImm9Lsb0: {
DiagnosticPredicate DP(Operand.isSImm9Lsb0());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
if (DP.isNearMatch())
return RISCVAsmParser::Match_InvalidSImm9Lsb0;
break;
}
// 'UImm9Lsb000' class
case MCK_UImm9Lsb000: {
DiagnosticPredicate DP(Operand.isUImm9Lsb000());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
if (DP.isNearMatch())
return RISCVAsmParser::Match_InvalidUImm9Lsb000;
break;
}
// 'UImm10Lsb00NonZero' class
case MCK_UImm10Lsb00NonZero: {
DiagnosticPredicate DP(Operand.isUImm10Lsb00NonZero());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
if (DP.isNearMatch())
return RISCVAsmParser::Match_InvalidUImm10Lsb00NonZero;
break;
}
// 'SImm10Lsb0000NonZero' class
case MCK_SImm10Lsb0000NonZero: {
DiagnosticPredicate DP(Operand.isSImm10Lsb0000NonZero());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
if (DP.isNearMatch())
return RISCVAsmParser::Match_InvalidSImm10Lsb0000NonZero;
break;
}
// 'SImm12Lsb0' class
case MCK_SImm12Lsb0: {
DiagnosticPredicate DP(Operand.isSImm12Lsb0());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
if (DP.isNearMatch())
return RISCVAsmParser::Match_InvalidSImm12Lsb0;
break;
}
// 'VTypeI10' class
case MCK_VTypeI10: {
DiagnosticPredicate DP(Operand.isVTypeI10());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
if (DP.isNearMatch())
return RISCVAsmParser::Match_InvalidVTypeI;
break;
}
// 'VTypeI11' class
case MCK_VTypeI11: {
DiagnosticPredicate DP(Operand.isVTypeI11());
if (DP.isMatch())
return MCTargetAsmParser::Match_Success;
if (DP.isNearMatch())