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swiftshader / SwiftShader / refs/heads/master / . / third_party / llvm-16.0 / configs / common / lib / Target / PowerPC / PPCGenRegisterInfo.inc
blob: 9c674f04ff9b73d71fe0d19919d1e28c4fd729dc [file] [log] [blame]
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|* *|
|* Target Register Enum Values *|
|* *|
|* Automatically generated file, do not edit! *|
|* *|
\*===----------------------------------------------------------------------===*/
#ifdef GET_REGINFO_ENUM
#undef GET_REGINFO_ENUM
namespace llvm {
class MCRegisterClass;
extern const MCRegisterClass PPCMCRegisterClasses[];
namespace PPC {
enum {
NoRegister,
BP = 1,
CARRY = 2,
CTR = 3,
FP = 4,
LR = 5,
RM = 6,
SPEFSCR = 7,
VRSAVE = 8,
XER = 9,
ZERO = 10,
ACC0 = 11,
ACC1 = 12,
ACC2 = 13,
ACC3 = 14,
ACC4 = 15,
ACC5 = 16,
ACC6 = 17,
ACC7 = 18,
BP8 = 19,
CR0 = 20,
CR1 = 21,
CR2 = 22,
CR3 = 23,
CR4 = 24,
CR5 = 25,
CR6 = 26,
CR7 = 27,
CTR8 = 28,
DMR0 = 29,
DMR1 = 30,
DMR2 = 31,
DMR3 = 32,
DMR4 = 33,
DMR5 = 34,
DMR6 = 35,
DMR7 = 36,
DMRROW0 = 37,
DMRROW1 = 38,
DMRROW2 = 39,
DMRROW3 = 40,
DMRROW4 = 41,
DMRROW5 = 42,
DMRROW6 = 43,
DMRROW7 = 44,
DMRROW8 = 45,
DMRROW9 = 46,
DMRROW10 = 47,
DMRROW11 = 48,
DMRROW12 = 49,
DMRROW13 = 50,
DMRROW14 = 51,
DMRROW15 = 52,
DMRROW16 = 53,
DMRROW17 = 54,
DMRROW18 = 55,
DMRROW19 = 56,
DMRROW20 = 57,
DMRROW21 = 58,
DMRROW22 = 59,
DMRROW23 = 60,
DMRROW24 = 61,
DMRROW25 = 62,
DMRROW26 = 63,
DMRROW27 = 64,
DMRROW28 = 65,
DMRROW29 = 66,
DMRROW30 = 67,
DMRROW31 = 68,
DMRROW32 = 69,
DMRROW33 = 70,
DMRROW34 = 71,
DMRROW35 = 72,
DMRROW36 = 73,
DMRROW37 = 74,
DMRROW38 = 75,
DMRROW39 = 76,
DMRROW40 = 77,
DMRROW41 = 78,
DMRROW42 = 79,
DMRROW43 = 80,
DMRROW44 = 81,
DMRROW45 = 82,
DMRROW46 = 83,
DMRROW47 = 84,
DMRROW48 = 85,
DMRROW49 = 86,
DMRROW50 = 87,
DMRROW51 = 88,
DMRROW52 = 89,
DMRROW53 = 90,
DMRROW54 = 91,
DMRROW55 = 92,
DMRROW56 = 93,
DMRROW57 = 94,
DMRROW58 = 95,
DMRROW59 = 96,
DMRROW60 = 97,
DMRROW61 = 98,
DMRROW62 = 99,
DMRROW63 = 100,
DMRROWp0 = 101,
DMRROWp1 = 102,
DMRROWp2 = 103,
DMRROWp3 = 104,
DMRROWp4 = 105,
DMRROWp5 = 106,
DMRROWp6 = 107,
DMRROWp7 = 108,
DMRROWp8 = 109,
DMRROWp9 = 110,
DMRROWp10 = 111,
DMRROWp11 = 112,
DMRROWp12 = 113,
DMRROWp13 = 114,
DMRROWp14 = 115,
DMRROWp15 = 116,
DMRROWp16 = 117,
DMRROWp17 = 118,
DMRROWp18 = 119,
DMRROWp19 = 120,
DMRROWp20 = 121,
DMRROWp21 = 122,
DMRROWp22 = 123,
DMRROWp23 = 124,
DMRROWp24 = 125,
DMRROWp25 = 126,
DMRROWp26 = 127,
DMRROWp27 = 128,
DMRROWp28 = 129,
DMRROWp29 = 130,
DMRROWp30 = 131,
DMRROWp31 = 132,
DMRp0 = 133,
DMRp1 = 134,
DMRp2 = 135,
DMRp3 = 136,
F0 = 137,
F1 = 138,
F2 = 139,
F3 = 140,
F4 = 141,
F5 = 142,
F6 = 143,
F7 = 144,
F8 = 145,
F9 = 146,
F10 = 147,
F11 = 148,
F12 = 149,
F13 = 150,
F14 = 151,
F15 = 152,
F16 = 153,
F17 = 154,
F18 = 155,
F19 = 156,
F20 = 157,
F21 = 158,
F22 = 159,
F23 = 160,
F24 = 161,
F25 = 162,
F26 = 163,
F27 = 164,
F28 = 165,
F29 = 166,
F30 = 167,
F31 = 168,
FP8 = 169,
LR8 = 170,
R0 = 171,
R1 = 172,
R2 = 173,
R3 = 174,
R4 = 175,
R5 = 176,
R6 = 177,
R7 = 178,
R8 = 179,
R9 = 180,
R10 = 181,
R11 = 182,
R12 = 183,
R13 = 184,
R14 = 185,
R15 = 186,
R16 = 187,
R17 = 188,
R18 = 189,
R19 = 190,
R20 = 191,
R21 = 192,
R22 = 193,
R23 = 194,
R24 = 195,
R25 = 196,
R26 = 197,
R27 = 198,
R28 = 199,
R29 = 200,
R30 = 201,
R31 = 202,
S0 = 203,
S1 = 204,
S2 = 205,
S3 = 206,
S4 = 207,
S5 = 208,
S6 = 209,
S7 = 210,
S8 = 211,
S9 = 212,
S10 = 213,
S11 = 214,
S12 = 215,
S13 = 216,
S14 = 217,
S15 = 218,
S16 = 219,
S17 = 220,
S18 = 221,
S19 = 222,
S20 = 223,
S21 = 224,
S22 = 225,
S23 = 226,
S24 = 227,
S25 = 228,
S26 = 229,
S27 = 230,
S28 = 231,
S29 = 232,
S30 = 233,
S31 = 234,
UACC0 = 235,
UACC1 = 236,
UACC2 = 237,
UACC3 = 238,
UACC4 = 239,
UACC5 = 240,
UACC6 = 241,
UACC7 = 242,
V0 = 243,
V1 = 244,
V2 = 245,
V3 = 246,
V4 = 247,
V5 = 248,
V6 = 249,
V7 = 250,
V8 = 251,
V9 = 252,
V10 = 253,
V11 = 254,
V12 = 255,
V13 = 256,
V14 = 257,
V15 = 258,
V16 = 259,
V17 = 260,
V18 = 261,
V19 = 262,
V20 = 263,
V21 = 264,
V22 = 265,
V23 = 266,
V24 = 267,
V25 = 268,
V26 = 269,
V27 = 270,
V28 = 271,
V29 = 272,
V30 = 273,
V31 = 274,
VF0 = 275,
VF1 = 276,
VF2 = 277,
VF3 = 278,
VF4 = 279,
VF5 = 280,
VF6 = 281,
VF7 = 282,
VF8 = 283,
VF9 = 284,
VF10 = 285,
VF11 = 286,
VF12 = 287,
VF13 = 288,
VF14 = 289,
VF15 = 290,
VF16 = 291,
VF17 = 292,
VF18 = 293,
VF19 = 294,
VF20 = 295,
VF21 = 296,
VF22 = 297,
VF23 = 298,
VF24 = 299,
VF25 = 300,
VF26 = 301,
VF27 = 302,
VF28 = 303,
VF29 = 304,
VF30 = 305,
VF31 = 306,
VSL0 = 307,
VSL1 = 308,
VSL2 = 309,
VSL3 = 310,
VSL4 = 311,
VSL5 = 312,
VSL6 = 313,
VSL7 = 314,
VSL8 = 315,
VSL9 = 316,
VSL10 = 317,
VSL11 = 318,
VSL12 = 319,
VSL13 = 320,
VSL14 = 321,
VSL15 = 322,
VSL16 = 323,
VSL17 = 324,
VSL18 = 325,
VSL19 = 326,
VSL20 = 327,
VSL21 = 328,
VSL22 = 329,
VSL23 = 330,
VSL24 = 331,
VSL25 = 332,
VSL26 = 333,
VSL27 = 334,
VSL28 = 335,
VSL29 = 336,
VSL30 = 337,
VSL31 = 338,
VSRp0 = 339,
VSRp1 = 340,
VSRp2 = 341,
VSRp3 = 342,
VSRp4 = 343,
VSRp5 = 344,
VSRp6 = 345,
VSRp7 = 346,
VSRp8 = 347,
VSRp9 = 348,
VSRp10 = 349,
VSRp11 = 350,
VSRp12 = 351,
VSRp13 = 352,
VSRp14 = 353,
VSRp15 = 354,
VSRp16 = 355,
VSRp17 = 356,
VSRp18 = 357,
VSRp19 = 358,
VSRp20 = 359,
VSRp21 = 360,
VSRp22 = 361,
VSRp23 = 362,
VSRp24 = 363,
VSRp25 = 364,
VSRp26 = 365,
VSRp27 = 366,
VSRp28 = 367,
VSRp29 = 368,
VSRp30 = 369,
VSRp31 = 370,
VSX32 = 371,
VSX33 = 372,
VSX34 = 373,
VSX35 = 374,
VSX36 = 375,
VSX37 = 376,
VSX38 = 377,
VSX39 = 378,
VSX40 = 379,
VSX41 = 380,
VSX42 = 381,
VSX43 = 382,
VSX44 = 383,
VSX45 = 384,
VSX46 = 385,
VSX47 = 386,
VSX48 = 387,
VSX49 = 388,
VSX50 = 389,
VSX51 = 390,
VSX52 = 391,
VSX53 = 392,
VSX54 = 393,
VSX55 = 394,
VSX56 = 395,
VSX57 = 396,
VSX58 = 397,
VSX59 = 398,
VSX60 = 399,
VSX61 = 400,
VSX62 = 401,
VSX63 = 402,
WACC0 = 403,
WACC1 = 404,
WACC2 = 405,
WACC3 = 406,
WACC4 = 407,
WACC5 = 408,
WACC6 = 409,
WACC7 = 410,
WACC_HI0 = 411,
WACC_HI1 = 412,
WACC_HI2 = 413,
WACC_HI3 = 414,
WACC_HI4 = 415,
WACC_HI5 = 416,
WACC_HI6 = 417,
WACC_HI7 = 418,
X0 = 419,
X1 = 420,
X2 = 421,
X3 = 422,
X4 = 423,
X5 = 424,
X6 = 425,
X7 = 426,
X8 = 427,
X9 = 428,
X10 = 429,
X11 = 430,
X12 = 431,
X13 = 432,
X14 = 433,
X15 = 434,
X16 = 435,
X17 = 436,
X18 = 437,
X19 = 438,
X20 = 439,
X21 = 440,
X22 = 441,
X23 = 442,
X24 = 443,
X25 = 444,
X26 = 445,
X27 = 446,
X28 = 447,
X29 = 448,
X30 = 449,
X31 = 450,
ZERO8 = 451,
CR0EQ = 452,
CR1EQ = 453,
CR2EQ = 454,
CR3EQ = 455,
CR4EQ = 456,
CR5EQ = 457,
CR6EQ = 458,
CR7EQ = 459,
CR0GT = 460,
CR1GT = 461,
CR2GT = 462,
CR3GT = 463,
CR4GT = 464,
CR5GT = 465,
CR6GT = 466,
CR7GT = 467,
CR0LT = 468,
CR1LT = 469,
CR2LT = 470,
CR3LT = 471,
CR4LT = 472,
CR5LT = 473,
CR6LT = 474,
CR7LT = 475,
CR0UN = 476,
CR1UN = 477,
CR2UN = 478,
CR3UN = 479,
CR4UN = 480,
CR5UN = 481,
CR6UN = 482,
CR7UN = 483,
G8p0 = 484,
G8p1 = 485,
G8p2 = 486,
G8p3 = 487,
G8p4 = 488,
G8p5 = 489,
G8p6 = 490,
G8p7 = 491,
G8p8 = 492,
G8p9 = 493,
G8p10 = 494,
G8p11 = 495,
G8p12 = 496,
G8p13 = 497,
G8p14 = 498,
G8p15 = 499,
NUM_TARGET_REGS // 500
};
} // end namespace PPC
// Register classes
namespace PPC {
enum {
VSSRCRegClassID = 0,
GPRCRegClassID = 1,
GPRC_NOR0RegClassID = 2,
GPRC_and_GPRC_NOR0RegClassID = 3,
CRBITRCRegClassID = 4,
F4RCRegClassID = 5,
CRRCRegClassID = 6,
CARRYRCRegClassID = 7,
CTRRCRegClassID = 8,
LRRCRegClassID = 9,
VRSAVERCRegClassID = 10,
SPILLTOVSRRCRegClassID = 11,
VSFRCRegClassID = 12,
G8RCRegClassID = 13,
G8RC_NOX0RegClassID = 14,
SPILLTOVSRRC_and_VSFRCRegClassID = 15,
G8RC_and_G8RC_NOX0RegClassID = 16,
F8RCRegClassID = 17,
SPERCRegClassID = 18,
VFRCRegClassID = 19,
SPERC_with_sub_32_in_GPRC_NOR0RegClassID = 20,
SPILLTOVSRRC_and_VFRCRegClassID = 21,
SPILLTOVSRRC_and_F4RCRegClassID = 22,
CTRRC8RegClassID = 23,
LR8RCRegClassID = 24,
DMRROWRCRegClassID = 25,
VSRCRegClassID = 26,
VSRC_with_sub_64_in_SPILLTOVSRRCRegClassID = 27,
VRRCRegClassID = 28,
VSLRCRegClassID = 29,
VRRC_with_sub_64_in_SPILLTOVSRRCRegClassID = 30,
G8pRCRegClassID = 31,
G8pRC_with_sub_32_in_GPRC_NOR0RegClassID = 32,
VSLRC_with_sub_64_in_SPILLTOVSRRCRegClassID = 33,
DMRROWpRCRegClassID = 34,
VSRpRCRegClassID = 35,
VSRpRC_with_sub_64_in_SPILLTOVSRRCRegClassID = 36,
VSRpRC_with_sub_64_in_F4RCRegClassID = 37,
VSRpRC_with_sub_64_in_VFRCRegClassID = 38,
VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRCRegClassID = 39,
VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RCRegClassID = 40,
ACCRCRegClassID = 41,
UACCRCRegClassID = 42,
WACCRCRegClassID = 43,
WACC_HIRCRegClassID = 44,
ACCRC_with_sub_64_in_SPILLTOVSRRCRegClassID = 45,
UACCRC_with_sub_64_in_SPILLTOVSRRCRegClassID = 46,
ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCRegClassID = 47,
UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCRegClassID = 48,
DMRRCRegClassID = 49,
DMRpRCRegClassID = 50,
};
} // end namespace PPC
// Subregister indices
namespace PPC {
enum : uint16_t {
NoSubRegister,
sub_32, // 1
sub_64, // 2
sub_dmr0, // 3
sub_dmr1, // 4
sub_dmrrow0, // 5
sub_dmrrow1, // 6
sub_dmrrowp0, // 7
sub_dmrrowp1, // 8
sub_eq, // 9
sub_gp8_x0, // 10
sub_gp8_x1, // 11
sub_gt, // 12
sub_lt, // 13
sub_pair0, // 14
sub_pair1, // 15
sub_un, // 16
sub_vsx0, // 17
sub_vsx1, // 18
sub_wacc_hi, // 19
sub_wacc_lo, // 20
sub_vsx1_then_sub_64, // 21
sub_pair1_then_sub_64, // 22
sub_pair1_then_sub_vsx0, // 23
sub_pair1_then_sub_vsx1, // 24
sub_pair1_then_sub_vsx1_then_sub_64, // 25
sub_dmrrowp1_then_sub_dmrrow0, // 26
sub_dmrrowp1_then_sub_dmrrow1, // 27
sub_wacc_hi_then_sub_dmrrow0, // 28
sub_wacc_hi_then_sub_dmrrow1, // 29
sub_wacc_hi_then_sub_dmrrowp0, // 30
sub_wacc_hi_then_sub_dmrrowp1, // 31
sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0, // 32
sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1, // 33
sub_dmr1_then_sub_dmrrow0, // 34
sub_dmr1_then_sub_dmrrow1, // 35
sub_dmr1_then_sub_dmrrowp0, // 36
sub_dmr1_then_sub_dmrrowp1, // 37
sub_dmr1_then_sub_wacc_hi, // 38
sub_dmr1_then_sub_wacc_lo, // 39
sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0, // 40
sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1, // 41
sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0, // 42
sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1, // 43
sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0, // 44
sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1, // 45
sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0, // 46
sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1, // 47
sub_gp8_x1_then_sub_32, // 48
NUM_TARGET_SUBREGS
};
} // end namespace PPC
// Register pressure sets enum.
namespace PPC {
enum RegisterPressureSets {
CARRYRC = 0,
VRSAVERC = 1,
SPILLTOVSRRC_and_F4RC = 2,
SPILLTOVSRRC_and_VFRC = 3,
CRBITRC = 4,
F4RC = 5,
VFRC = 6,
WACCRC = 7,
WACC_HIRC = 8,
GPRC = 9,
SPILLTOVSRRC_and_VSFRC = 10,
SPILLTOVSRRC_and_VSFRC_with_VFRC = 11,
F4RC_with_SPILLTOVSRRC_and_VSFRC = 12,
VSSRC = 13,
DMRROWRC = 14,
SPILLTOVSRRC = 15,
SPILLTOVSRRC_with_SPILLTOVSRRC_and_F4RC = 16,
SPILLTOVSRRC_with_VFRC = 17,
F4RC_with_SPILLTOVSRRC = 18,
VSSRC_with_SPILLTOVSRRC = 19,
};
} // end namespace PPC
} // end namespace llvm
#endif // GET_REGINFO_ENUM
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|* *|
|* MC Register Information *|
|* *|
|* Automatically generated file, do not edit! *|
|* *|
\*===----------------------------------------------------------------------===*/
#ifdef GET_REGINFO_MC_DESC
#undef GET_REGINFO_MC_DESC
namespace llvm {
extern const MCPhysReg PPCRegDiffLists[] = {
/* 0 */ 0, 0,
/* 2 */ 74, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0,
/* 19 */ 90, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0,
/* 36 */ 106, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0,
/* 53 */ 122, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0,
/* 70 */ 65378, 1, 1, 1, 1, 1, 1, 1, 0,
/* 79 */ 62326, 1, 1, 1, 0,
/* 84 */ 62386, 1, 1, 1, 0,
/* 89 */ 64605, 1, 1, 1, 0,
/* 94 */ 65497, 1, 1, 1, 0,
/* 99 */ 65501, 1, 1, 1, 0,
/* 104 */ 64707, 1, 0,
/* 107 */ 64867, 1, 0,
/* 110 */ 64997, 1, 0,
/* 113 */ 65408, 1, 0,
/* 116 */ 65472, 1, 0,
/* 119 */ 65234, 65472, 1, 64, 65473, 1, 0,
/* 126 */ 65474, 1, 0,
/* 129 */ 374, 65234, 65472, 1, 64, 65473, 1, 371, 65228, 65474, 1, 62, 65475, 1, 0,
/* 144 */ 65476, 1, 0,
/* 147 */ 65237, 65476, 1, 60, 65477, 1, 0,
/* 154 */ 65478, 1, 0,
/* 157 */ 65432, 374, 65234, 65472, 1, 64, 65473, 1, 371, 65228, 65474, 1, 62, 65475, 1, 65522, 374, 65237, 65476, 1, 60, 65477, 1, 364, 65231, 65478, 1, 58, 65479, 1, 0,
/* 188 */ 65480, 1, 0,
/* 191 */ 65240, 65480, 1, 56, 65481, 1, 0,
/* 198 */ 65482, 1, 0,
/* 201 */ 374, 65240, 65480, 1, 56, 65481, 1, 357, 65234, 65482, 1, 54, 65483, 1, 0,
/* 216 */ 65484, 1, 0,
/* 219 */ 65243, 65484, 1, 52, 65485, 1, 0,
/* 226 */ 65486, 1, 0,
/* 229 */ 65433, 374, 65240, 65480, 1, 56, 65481, 1, 357, 65234, 65482, 1, 54, 65483, 1, 65508, 374, 65243, 65484, 1, 52, 65485, 1, 350, 65237, 65486, 1, 50, 65487, 1, 0,
/* 260 */ 65488, 1, 0,
/* 263 */ 65246, 65488, 1, 48, 65489, 1, 0,
/* 270 */ 65490, 1, 0,
/* 273 */ 374, 65246, 65488, 1, 48, 65489, 1, 343, 65240, 65490, 1, 46, 65491, 1, 0,
/* 288 */ 65492, 1, 0,
/* 291 */ 65249, 65492, 1, 44, 65493, 1, 0,
/* 298 */ 65494, 1, 0,
/* 301 */ 65434, 374, 65246, 65488, 1, 48, 65489, 1, 343, 65240, 65490, 1, 46, 65491, 1, 65494, 374, 65249, 65492, 1, 44, 65493, 1, 336, 65243, 65494, 1, 42, 65495, 1, 0,
/* 332 */ 65496, 1, 0,
/* 335 */ 65252, 65496, 1, 40, 65497, 1, 0,
/* 342 */ 65498, 1, 0,
/* 345 */ 374, 65252, 65496, 1, 40, 65497, 1, 329, 65246, 65498, 1, 38, 65499, 1, 0,
/* 360 */ 65500, 1, 0,
/* 363 */ 65255, 65500, 1, 36, 65501, 1, 0,
/* 370 */ 65502, 1, 0,
/* 373 */ 65435, 374, 65252, 65496, 1, 40, 65497, 1, 329, 65246, 65498, 1, 38, 65499, 1, 65480, 374, 65255, 65500, 1, 36, 65501, 1, 322, 65249, 65502, 1, 34, 65503, 1, 0,
/* 404 */ 3, 0,
/* 406 */ 8, 0,
/* 408 */ 18, 0,
/* 410 */ 448, 65528, 65528, 24, 0,
/* 415 */ 65424, 32, 65505, 32, 0,
/* 420 */ 65425, 32, 65505, 32, 0,
/* 425 */ 65426, 32, 65505, 32, 0,
/* 430 */ 65427, 32, 65505, 32, 0,
/* 435 */ 65428, 32, 65505, 32, 0,
/* 440 */ 65429, 32, 65505, 32, 0,
/* 445 */ 65430, 32, 65505, 32, 0,
/* 450 */ 65431, 32, 65505, 32, 0,
/* 455 */ 65432, 32, 65505, 32, 0,
/* 460 */ 65433, 32, 65505, 32, 0,
/* 465 */ 65434, 32, 65505, 32, 0,
/* 470 */ 65435, 32, 65505, 32, 0,
/* 475 */ 65436, 32, 65505, 32, 0,
/* 480 */ 65437, 32, 65505, 32, 0,
/* 485 */ 65438, 32, 65505, 32, 0,
/* 490 */ 65439, 32, 65505, 32, 0,
/* 495 */ 37, 0,
/* 497 */ 32, 216, 49, 0,
/* 501 */ 32, 216, 50, 0,
/* 505 */ 32, 216, 51, 0,
/* 509 */ 32, 216, 52, 0,
/* 513 */ 32, 216, 53, 0,
/* 517 */ 32, 216, 54, 0,
/* 521 */ 32, 216, 55, 0,
/* 525 */ 32, 216, 56, 0,
/* 529 */ 32, 216, 57, 0,
/* 533 */ 32, 216, 58, 0,
/* 537 */ 32, 216, 59, 0,
/* 541 */ 32, 216, 60, 0,
/* 545 */ 32, 216, 61, 0,
/* 549 */ 32, 216, 62, 0,
/* 553 */ 32, 216, 63, 0,
/* 557 */ 32, 216, 64, 0,
/* 561 */ 32, 216, 65, 0,
/* 565 */ 73, 0,
/* 567 */ 65504, 96, 0,
/* 570 */ 65504, 97, 0,
/* 573 */ 65504, 98, 0,
/* 576 */ 65504, 99, 0,
/* 579 */ 32, 286, 65154, 100, 0,
/* 584 */ 33, 286, 65154, 100, 0,
/* 589 */ 33, 287, 65154, 100, 0,
/* 594 */ 34, 287, 65154, 100, 0,
/* 599 */ 34, 280, 65162, 100, 0,
/* 604 */ 35, 280, 65162, 100, 0,
/* 609 */ 35, 281, 65162, 100, 0,
/* 614 */ 36, 281, 65162, 100, 0,
/* 619 */ 65504, 100, 0,
/* 622 */ 36, 289, 65154, 101, 0,
/* 627 */ 37, 289, 65154, 101, 0,
/* 632 */ 37, 290, 65154, 101, 0,
/* 637 */ 38, 290, 65154, 101, 0,
/* 642 */ 40, 292, 65154, 101, 0,
/* 647 */ 41, 292, 65154, 101, 0,
/* 652 */ 41, 293, 65154, 101, 0,
/* 657 */ 42, 293, 65154, 101, 0,
/* 662 */ 38, 283, 65162, 101, 0,
/* 667 */ 39, 283, 65162, 101, 0,
/* 672 */ 39, 284, 65162, 101, 0,
/* 677 */ 40, 284, 65162, 101, 0,
/* 682 */ 42, 286, 65162, 101, 0,
/* 687 */ 43, 286, 65162, 101, 0,
/* 692 */ 43, 287, 65162, 101, 0,
/* 697 */ 44, 287, 65162, 101, 0,
/* 702 */ 65504, 101, 0,
/* 705 */ 44, 295, 65154, 102, 0,
/* 710 */ 45, 295, 65154, 102, 0,
/* 715 */ 45, 296, 65154, 102, 0,
/* 720 */ 46, 296, 65154, 102, 0,
/* 725 */ 48, 298, 65154, 102, 0,
/* 730 */ 49, 298, 65154, 102, 0,
/* 735 */ 49, 299, 65154, 102, 0,
/* 740 */ 50, 299, 65154, 102, 0,
/* 745 */ 46, 289, 65162, 102, 0,
/* 750 */ 47, 289, 65162, 102, 0,
/* 755 */ 47, 290, 65162, 102, 0,
/* 760 */ 48, 290, 65162, 102, 0,
/* 765 */ 50, 292, 65162, 102, 0,
/* 770 */ 51, 292, 65162, 102, 0,
/* 775 */ 51, 293, 65162, 102, 0,
/* 780 */ 52, 293, 65162, 102, 0,
/* 785 */ 65504, 102, 0,
/* 788 */ 52, 301, 65154, 103, 0,
/* 793 */ 53, 301, 65154, 103, 0,
/* 798 */ 53, 302, 65154, 103, 0,
/* 803 */ 54, 302, 65154, 103, 0,
/* 808 */ 56, 304, 65154, 103, 0,
/* 813 */ 57, 304, 65154, 103, 0,
/* 818 */ 57, 305, 65154, 103, 0,
/* 823 */ 58, 305, 65154, 103, 0,
/* 828 */ 54, 295, 65162, 103, 0,
/* 833 */ 55, 295, 65162, 103, 0,
/* 838 */ 55, 296, 65162, 103, 0,
/* 843 */ 56, 296, 65162, 103, 0,
/* 848 */ 58, 298, 65162, 103, 0,
/* 853 */ 59, 298, 65162, 103, 0,
/* 858 */ 59, 299, 65162, 103, 0,
/* 863 */ 60, 299, 65162, 103, 0,
/* 868 */ 65504, 103, 0,
/* 871 */ 60, 307, 65154, 104, 0,
/* 876 */ 61, 307, 65154, 104, 0,
/* 881 */ 61, 308, 65154, 104, 0,
/* 886 */ 62, 308, 65154, 104, 0,
/* 891 */ 62, 301, 65162, 104, 0,
/* 896 */ 63, 301, 65162, 104, 0,
/* 901 */ 63, 302, 65162, 104, 0,
/* 906 */ 64, 302, 65162, 104, 0,
/* 911 */ 65504, 104, 0,
/* 914 */ 65504, 105, 0,
/* 917 */ 65504, 106, 0,
/* 920 */ 65504, 107, 0,
/* 923 */ 65504, 108, 0,
/* 926 */ 65504, 109, 0,
/* 929 */ 65504, 110, 0,
/* 932 */ 65504, 111, 0,
/* 935 */ 65504, 112, 0,
/* 938 */ 165, 0,
/* 940 */ 170, 16, 65200, 224, 0,
/* 945 */ 170, 17, 65200, 224, 0,
/* 950 */ 170, 17, 65201, 224, 0,
/* 955 */ 170, 18, 65201, 224, 0,
/* 960 */ 170, 19, 65201, 224, 0,
/* 965 */ 170, 19, 65202, 224, 0,
/* 970 */ 170, 20, 65202, 224, 0,
/* 975 */ 170, 21, 65202, 224, 0,
/* 980 */ 170, 21, 65203, 224, 0,
/* 985 */ 170, 22, 65203, 224, 0,
/* 990 */ 170, 23, 65203, 224, 0,
/* 995 */ 170, 23, 65204, 224, 0,
/* 1000 */ 170, 24, 65204, 224, 0,
/* 1005 */ 170, 25, 65204, 224, 0,
/* 1010 */ 170, 25, 65205, 224, 0,
/* 1015 */ 170, 26, 65205, 224, 0,
/* 1020 */ 170, 27, 65205, 224, 0,
/* 1025 */ 170, 27, 65206, 224, 0,
/* 1030 */ 170, 28, 65206, 224, 0,
/* 1035 */ 170, 29, 65206, 224, 0,
/* 1040 */ 170, 29, 65207, 224, 0,
/* 1045 */ 170, 30, 65207, 224, 0,
/* 1050 */ 170, 31, 65207, 224, 0,
/* 1055 */ 170, 31, 65208, 224, 0,
/* 1060 */ 170, 32, 65208, 224, 0,
/* 1065 */ 441, 0,
/* 1067 */ 63676, 0,
/* 1069 */ 63705, 0,
/* 1071 */ 63738, 0,
/* 1073 */ 63771, 0,
/* 1075 */ 65080, 0,
/* 1077 */ 65088, 0,
/* 1079 */ 65095, 0,
/* 1081 */ 65096, 0,
/* 1083 */ 65104, 0,
/* 1085 */ 65238, 0,
/* 1087 */ 65256, 0,
/* 1089 */ 65471, 65288, 249, 65288, 0,
/* 1094 */ 65472, 65288, 249, 65288, 0,
/* 1099 */ 65473, 65288, 249, 65288, 0,
/* 1104 */ 65474, 65288, 249, 65288, 0,
/* 1109 */ 65475, 65288, 249, 65288, 0,
/* 1114 */ 65476, 65288, 249, 65288, 0,
/* 1119 */ 65477, 65288, 249, 65288, 0,
/* 1124 */ 65478, 65288, 249, 65288, 0,
/* 1129 */ 65479, 65288, 249, 65288, 0,
/* 1134 */ 65480, 65288, 249, 65288, 0,
/* 1139 */ 65481, 65288, 249, 65288, 0,
/* 1144 */ 65482, 65288, 249, 65288, 0,
/* 1149 */ 65483, 65288, 249, 65288, 0,
/* 1154 */ 65484, 65288, 249, 65288, 0,
/* 1159 */ 65485, 65288, 249, 65288, 0,
/* 1164 */ 65486, 65288, 249, 65288, 0,
/* 1169 */ 65504, 65366, 171, 65366, 0,
/* 1174 */ 104, 65504, 65366, 171, 65366, 202, 65505, 65366, 171, 65366, 0,
/* 1185 */ 328, 65504, 65366, 171, 65366, 202, 65505, 65366, 171, 65366, 0,
/* 1196 */ 65506, 65366, 171, 65366, 0,
/* 1201 */ 105, 65506, 65366, 171, 65366, 200, 65507, 65366, 171, 65366, 0,
/* 1212 */ 329, 65506, 65366, 171, 65366, 200, 65507, 65366, 171, 65366, 0,
/* 1223 */ 65508, 65366, 171, 65366, 0,
/* 1228 */ 106, 65508, 65366, 171, 65366, 198, 65509, 65366, 171, 65366, 0,
/* 1239 */ 330, 65508, 65366, 171, 65366, 198, 65509, 65366, 171, 65366, 0,
/* 1250 */ 65510, 65366, 171, 65366, 0,
/* 1255 */ 107, 65510, 65366, 171, 65366, 196, 65511, 65366, 171, 65366, 0,
/* 1266 */ 331, 65510, 65366, 171, 65366, 196, 65511, 65366, 171, 65366, 0,
/* 1277 */ 65512, 65366, 171, 65366, 0,
/* 1282 */ 108, 65512, 65366, 171, 65366, 194, 65513, 65366, 171, 65366, 0,
/* 1293 */ 332, 65512, 65366, 171, 65366, 194, 65513, 65366, 171, 65366, 0,
/* 1304 */ 65514, 65366, 171, 65366, 0,
/* 1309 */ 109, 65514, 65366, 171, 65366, 192, 65515, 65366, 171, 65366, 0,
/* 1320 */ 333, 65514, 65366, 171, 65366, 192, 65515, 65366, 171, 65366, 0,
/* 1331 */ 65516, 65366, 171, 65366, 0,
/* 1336 */ 110, 65516, 65366, 171, 65366, 190, 65517, 65366, 171, 65366, 0,
/* 1347 */ 334, 65516, 65366, 171, 65366, 190, 65517, 65366, 171, 65366, 0,
/* 1358 */ 65518, 65366, 171, 65366, 0,
/* 1363 */ 111, 65518, 65366, 171, 65366, 188, 65519, 65366, 171, 65366, 0,
/* 1374 */ 335, 65518, 65366, 171, 65366, 188, 65519, 65366, 171, 65366, 0,
/* 1385 */ 65368, 0,
/* 1387 */ 65371, 0,
/* 1389 */ 65408, 0,
/* 1391 */ 65432, 0,
/* 1393 */ 65464, 0,
/* 1395 */ 65472, 0,
/* 1397 */ 65474, 0,
/* 1399 */ 65504, 0,
/* 1401 */ 65518, 0,
/* 1403 */ 65535, 0,
};
extern const LaneBitmask PPCLaneMaskLists[] = {
/* 0 */ LaneBitmask(0x0000000000000000), LaneBitmask::getAll(),
/* 2 */ LaneBitmask(0x0000000000000001), LaneBitmask::getAll(),
/* 4 */ LaneBitmask(0x0000000000000002), LaneBitmask::getAll(),
/* 6 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask::getAll(),
/* 9 */ LaneBitmask(0x0000000000000040), LaneBitmask(0x0000000000000020), LaneBitmask(0x0000000000000010), LaneBitmask(0x0000000000000080), LaneBitmask::getAll(),
/* 14 */ LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000100), LaneBitmask::getAll(),
/* 17 */ LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000100), LaneBitmask(0x0000000000000200), LaneBitmask(0x0000000000000400), LaneBitmask::getAll(),
/* 22 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000800), LaneBitmask(0x0000000000001000), LaneBitmask::getAll(),
/* 27 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000800), LaneBitmask(0x0000000000001000), LaneBitmask(0x0000000000002000), LaneBitmask(0x0000000000004000), LaneBitmask(0x0000000000008000), LaneBitmask(0x0000000000010000), LaneBitmask::getAll(),
/* 36 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000800), LaneBitmask(0x0000000000001000), LaneBitmask(0x0000000000002000), LaneBitmask(0x0000000000004000), LaneBitmask(0x0000000000008000), LaneBitmask(0x0000000000010000), LaneBitmask(0x0000000000020000), LaneBitmask(0x0000000000040000), LaneBitmask(0x0000000000080000), LaneBitmask(0x0000000000100000), LaneBitmask(0x0000000000200000), LaneBitmask(0x0000000000400000), LaneBitmask(0x0000000000800000), LaneBitmask(0x0000000001000000), LaneBitmask::getAll(),
/* 53 */ LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000002000000), LaneBitmask::getAll(),
};
extern const uint16_t PPCSubRegIdxLists[] = {
/* 0 */ 1, 0,
/* 2 */ 2, 0,
/* 4 */ 5, 6, 0,
/* 7 */ 13, 12, 9, 16, 0,
/* 12 */ 17, 2, 18, 21, 0,
/* 17 */ 14, 17, 2, 18, 21, 15, 23, 22, 24, 25, 0,
/* 28 */ 7, 5, 6, 8, 26, 27, 0,
/* 35 */ 20, 7, 5, 6, 8, 26, 27, 19, 30, 28, 29, 31, 32, 33, 0,
/* 50 */ 3, 20, 7, 5, 6, 8, 26, 27, 19, 30, 28, 29, 31, 32, 33, 4, 39, 36, 34, 35, 37, 40, 41, 38, 44, 42, 43, 45, 46, 47, 0,
/* 81 */ 10, 1, 11, 48, 0,
};
extern const MCRegisterInfo::SubRegCoveredBits PPCSubRegIdxRanges[] = {
{ 65535, 65535 },
{ 0, 32 }, // sub_32
{ 0, 64 }, // sub_64
{ 0, 1024 }, // sub_dmr0
{ 1024, 1024 }, // sub_dmr1
{ 0, 128 }, // sub_dmrrow0
{ 128, 128 }, // sub_dmrrow1
{ 0, 256 }, // sub_dmrrowp0
{ 256, 256 }, // sub_dmrrowp1
{ 2, 1 }, // sub_eq
{ 0, 64 }, // sub_gp8_x0
{ 64, 64 }, // sub_gp8_x1
{ 1, 1 }, // sub_gt
{ 0, 1 }, // sub_lt
{ 0, 256 }, // sub_pair0
{ 256, 256 }, // sub_pair1
{ 3, 1 }, // sub_un
{ 0, 128 }, // sub_vsx0
{ 128, 128 }, // sub_vsx1
{ 512, 512 }, // sub_wacc_hi
{ 0, 512 }, // sub_wacc_lo
{ 128, 64 }, // sub_vsx1_then_sub_64
{ 256, 64 }, // sub_pair1_then_sub_64
{ 256, 128 }, // sub_pair1_then_sub_vsx0
{ 384, 128 }, // sub_pair1_then_sub_vsx1
{ 384, 64 }, // sub_pair1_then_sub_vsx1_then_sub_64
{ 256, 128 }, // sub_dmrrowp1_then_sub_dmrrow0
{ 384, 128 }, // sub_dmrrowp1_then_sub_dmrrow1
{ 512, 128 }, // sub_wacc_hi_then_sub_dmrrow0
{ 640, 128 }, // sub_wacc_hi_then_sub_dmrrow1
{ 512, 256 }, // sub_wacc_hi_then_sub_dmrrowp0
{ 768, 256 }, // sub_wacc_hi_then_sub_dmrrowp1
{ 768, 128 }, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
{ 896, 128 }, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
{ 1024, 128 }, // sub_dmr1_then_sub_dmrrow0
{ 1152, 128 }, // sub_dmr1_then_sub_dmrrow1
{ 1024, 256 }, // sub_dmr1_then_sub_dmrrowp0
{ 1280, 256 }, // sub_dmr1_then_sub_dmrrowp1
{ 1536, 512 }, // sub_dmr1_then_sub_wacc_hi
{ 1024, 512 }, // sub_dmr1_then_sub_wacc_lo
{ 1280, 128 }, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
{ 1408, 128 }, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
{ 1536, 128 }, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
{ 1664, 128 }, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
{ 1536, 256 }, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
{ 1792, 256 }, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
{ 1792, 128 }, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
{ 1920, 128 }, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
{ 64, 32 }, // sub_gp8_x1_then_sub_32
};
#ifdef __GNUC__
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Woverlength-strings"
#endif
extern const char PPCRegStrings[] = {
/* 0 */ "VF10\0"
/* 5 */ "VSL10\0"
/* 11 */ "R10\0"
/* 15 */ "S10\0"
/* 19 */ "V10\0"
/* 23 */ "DMRROW10\0"
/* 32 */ "X10\0"
/* 36 */ "G8p10\0"
/* 42 */ "VSRp10\0"
/* 49 */ "DMRROWp10\0"
/* 59 */ "VF20\0"
/* 64 */ "VSL20\0"
/* 70 */ "R20\0"
/* 74 */ "S20\0"
/* 78 */ "V20\0"
/* 82 */ "DMRROW20\0"
/* 91 */ "X20\0"
/* 95 */ "VSRp20\0"
/* 102 */ "DMRROWp20\0"
/* 112 */ "VF30\0"
/* 117 */ "VSL30\0"
/* 123 */ "R30\0"
/* 127 */ "S30\0"
/* 131 */ "V30\0"
/* 135 */ "DMRROW30\0"
/* 144 */ "X30\0"
/* 148 */ "VSRp30\0"
/* 155 */ "DMRROWp30\0"
/* 165 */ "DMRROW40\0"
/* 174 */ "VSX40\0"
/* 180 */ "DMRROW50\0"
/* 189 */ "VSX50\0"
/* 195 */ "DMRROW60\0"
/* 204 */ "VSX60\0"
/* 210 */ "UACC0\0"
/* 216 */ "WACC0\0"
/* 222 */ "VF0\0"
/* 226 */ "WACC_HI0\0"
/* 235 */ "VSL0\0"
/* 240 */ "CR0\0"
/* 244 */ "DMR0\0"
/* 249 */ "S0\0"
/* 252 */ "V0\0"
/* 255 */ "DMRROW0\0"
/* 263 */ "X0\0"
/* 266 */ "G8p0\0"
/* 271 */ "DMRp0\0"
/* 277 */ "VSRp0\0"
/* 283 */ "DMRROWp0\0"
/* 292 */ "VF11\0"
/* 297 */ "VSL11\0"
/* 303 */ "R11\0"
/* 307 */ "S11\0"
/* 311 */ "V11\0"
/* 315 */ "DMRROW11\0"
/* 324 */ "X11\0"
/* 328 */ "G8p11\0"
/* 334 */ "VSRp11\0"
/* 341 */ "DMRROWp11\0"
/* 351 */ "VF21\0"
/* 356 */ "VSL21\0"
/* 362 */ "R21\0"
/* 366 */ "S21\0"
/* 370 */ "V21\0"
/* 374 */ "DMRROW21\0"
/* 383 */ "X21\0"
/* 387 */ "VSRp21\0"
/* 394 */ "DMRROWp21\0"
/* 404 */ "VF31\0"
/* 409 */ "VSL31\0"
/* 415 */ "R31\0"
/* 419 */ "S31\0"
/* 423 */ "V31\0"
/* 427 */ "DMRROW31\0"
/* 436 */ "X31\0"
/* 440 */ "VSRp31\0"
/* 447 */ "DMRROWp31\0"
/* 457 */ "DMRROW41\0"
/* 466 */ "VSX41\0"
/* 472 */ "DMRROW51\0"
/* 481 */ "VSX51\0"
/* 487 */ "DMRROW61\0"
/* 496 */ "VSX61\0"
/* 502 */ "UACC1\0"
/* 508 */ "WACC1\0"
/* 514 */ "VF1\0"
/* 518 */ "WACC_HI1\0"
/* 527 */ "VSL1\0"
/* 532 */ "CR1\0"
/* 536 */ "DMR1\0"
/* 541 */ "S1\0"
/* 544 */ "V1\0"
/* 547 */ "DMRROW1\0"
/* 555 */ "X1\0"
/* 558 */ "G8p1\0"
/* 563 */ "DMRp1\0"
/* 569 */ "VSRp1\0"
/* 575 */ "DMRROWp1\0"
/* 584 */ "VF12\0"
/* 589 */ "VSL12\0"
/* 595 */ "R12\0"
/* 599 */ "S12\0"
/* 603 */ "V12\0"
/* 607 */ "DMRROW12\0"
/* 616 */ "X12\0"
/* 620 */ "G8p12\0"
/* 626 */ "VSRp12\0"
/* 633 */ "DMRROWp12\0"
/* 643 */ "VF22\0"
/* 648 */ "VSL22\0"
/* 654 */ "R22\0"
/* 658 */ "S22\0"
/* 662 */ "V22\0"
/* 666 */ "DMRROW22\0"
/* 675 */ "X22\0"
/* 679 */ "VSRp22\0"
/* 686 */ "DMRROWp22\0"
/* 696 */ "DMRROW32\0"
/* 705 */ "VSX32\0"
/* 711 */ "DMRROW42\0"
/* 720 */ "VSX42\0"
/* 726 */ "DMRROW52\0"
/* 735 */ "VSX52\0"
/* 741 */ "DMRROW62\0"
/* 750 */ "VSX62\0"
/* 756 */ "UACC2\0"
/* 762 */ "WACC2\0"
/* 768 */ "VF2\0"
/* 772 */ "WACC_HI2\0"
/* 781 */ "VSL2\0"
/* 786 */ "CR2\0"
/* 790 */ "DMR2\0"
/* 795 */ "S2\0"
/* 798 */ "V2\0"
/* 801 */ "DMRROW2\0"
/* 809 */ "X2\0"
/* 812 */ "G8p2\0"
/* 817 */ "DMRp2\0"
/* 823 */ "VSRp2\0"
/* 829 */ "DMRROWp2\0"
/* 838 */ "VF13\0"
/* 843 */ "VSL13\0"
/* 849 */ "R13\0"
/* 853 */ "S13\0"
/* 857 */ "V13\0"
/* 861 */ "DMRROW13\0"
/* 870 */ "X13\0"
/* 874 */ "G8p13\0"
/* 880 */ "VSRp13\0"
/* 887 */ "DMRROWp13\0"
/* 897 */ "VF23\0"
/* 902 */ "VSL23\0"
/* 908 */ "R23\0"
/* 912 */ "S23\0"
/* 916 */ "V23\0"
/* 920 */ "DMRROW23\0"
/* 929 */ "X23\0"
/* 933 */ "VSRp23\0"
/* 940 */ "DMRROWp23\0"
/* 950 */ "DMRROW33\0"
/* 959 */ "VSX33\0"
/* 965 */ "DMRROW43\0"
/* 974 */ "VSX43\0"
/* 980 */ "DMRROW53\0"
/* 989 */ "VSX53\0"
/* 995 */ "DMRROW63\0"
/* 1004 */ "VSX63\0"
/* 1010 */ "UACC3\0"
/* 1016 */ "WACC3\0"
/* 1022 */ "VF3\0"
/* 1026 */ "WACC_HI3\0"
/* 1035 */ "VSL3\0"
/* 1040 */ "CR3\0"
/* 1044 */ "DMR3\0"
/* 1049 */ "S3\0"
/* 1052 */ "V3\0"
/* 1055 */ "DMRROW3\0"
/* 1063 */ "X3\0"
/* 1066 */ "G8p3\0"
/* 1071 */ "DMRp3\0"
/* 1077 */ "VSRp3\0"
/* 1083 */ "DMRROWp3\0"
/* 1092 */ "VF14\0"
/* 1097 */ "VSL14\0"
/* 1103 */ "R14\0"
/* 1107 */ "S14\0"
/* 1111 */ "V14\0"
/* 1115 */ "DMRROW14\0"
/* 1124 */ "X14\0"
/* 1128 */ "G8p14\0"
/* 1134 */ "VSRp14\0"
/* 1141 */ "DMRROWp14\0"
/* 1151 */ "VF24\0"
/* 1156 */ "VSL24\0"
/* 1162 */ "R24\0"
/* 1166 */ "S24\0"
/* 1170 */ "V24\0"
/* 1174 */ "DMRROW24\0"
/* 1183 */ "X24\0"
/* 1187 */ "VSRp24\0"
/* 1194 */ "DMRROWp24\0"
/* 1204 */ "DMRROW34\0"
/* 1213 */ "VSX34\0"
/* 1219 */ "DMRROW44\0"
/* 1228 */ "VSX44\0"
/* 1234 */ "DMRROW54\0"
/* 1243 */ "VSX54\0"
/* 1249 */ "UACC4\0"
/* 1255 */ "WACC4\0"
/* 1261 */ "VF4\0"
/* 1265 */ "WACC_HI4\0"
/* 1274 */ "VSL4\0"
/* 1279 */ "CR4\0"
/* 1283 */ "DMR4\0"
/* 1288 */ "S4\0"
/* 1291 */ "V4\0"
/* 1294 */ "DMRROW4\0"
/* 1302 */ "X4\0"
/* 1305 */ "G8p4\0"
/* 1310 */ "VSRp4\0"
/* 1316 */ "DMRROWp4\0"
/* 1325 */ "VF15\0"
/* 1330 */ "VSL15\0"
/* 1336 */ "R15\0"
/* 1340 */ "S15\0"
/* 1344 */ "V15\0"
/* 1348 */ "DMRROW15\0"
/* 1357 */ "X15\0"
/* 1361 */ "G8p15\0"
/* 1367 */ "VSRp15\0"
/* 1374 */ "DMRROWp15\0"
/* 1384 */ "VF25\0"
/* 1389 */ "VSL25\0"
/* 1395 */ "R25\0"
/* 1399 */ "S25\0"
/* 1403 */ "V25\0"
/* 1407 */ "DMRROW25\0"
/* 1416 */ "X25\0"
/* 1420 */ "VSRp25\0"
/* 1427 */ "DMRROWp25\0"
/* 1437 */ "DMRROW35\0"
/* 1446 */ "VSX35\0"
/* 1452 */ "DMRROW45\0"
/* 1461 */ "VSX45\0"
/* 1467 */ "DMRROW55\0"
/* 1476 */ "VSX55\0"
/* 1482 */ "UACC5\0"
/* 1488 */ "WACC5\0"
/* 1494 */ "VF5\0"
/* 1498 */ "WACC_HI5\0"
/* 1507 */ "VSL5\0"
/* 1512 */ "CR5\0"
/* 1516 */ "DMR5\0"
/* 1521 */ "S5\0"
/* 1524 */ "V5\0"
/* 1527 */ "DMRROW5\0"
/* 1535 */ "X5\0"
/* 1538 */ "G8p5\0"
/* 1543 */ "VSRp5\0"
/* 1549 */ "DMRROWp5\0"
/* 1558 */ "VF16\0"
/* 1563 */ "VSL16\0"
/* 1569 */ "R16\0"
/* 1573 */ "S16\0"
/* 1577 */ "V16\0"
/* 1581 */ "DMRROW16\0"
/* 1590 */ "X16\0"
/* 1594 */ "VSRp16\0"
/* 1601 */ "DMRROWp16\0"
/* 1611 */ "VF26\0"
/* 1616 */ "VSL26\0"
/* 1622 */ "R26\0"
/* 1626 */ "S26\0"
/* 1630 */ "V26\0"
/* 1634 */ "DMRROW26\0"
/* 1643 */ "X26\0"
/* 1647 */ "VSRp26\0"
/* 1654 */ "DMRROWp26\0"
/* 1664 */ "DMRROW36\0"
/* 1673 */ "VSX36\0"
/* 1679 */ "DMRROW46\0"
/* 1688 */ "VSX46\0"
/* 1694 */ "DMRROW56\0"
/* 1703 */ "VSX56\0"
/* 1709 */ "UACC6\0"
/* 1715 */ "WACC6\0"
/* 1721 */ "VF6\0"
/* 1725 */ "WACC_HI6\0"
/* 1734 */ "VSL6\0"
/* 1739 */ "CR6\0"
/* 1743 */ "DMR6\0"
/* 1748 */ "S6\0"
/* 1751 */ "V6\0"
/* 1754 */ "DMRROW6\0"
/* 1762 */ "X6\0"
/* 1765 */ "G8p6\0"
/* 1770 */ "VSRp6\0"
/* 1776 */ "DMRROWp6\0"
/* 1785 */ "VF17\0"
/* 1790 */ "VSL17\0"
/* 1796 */ "R17\0"
/* 1800 */ "S17\0"
/* 1804 */ "V17\0"
/* 1808 */ "DMRROW17\0"
/* 1817 */ "X17\0"
/* 1821 */ "VSRp17\0"
/* 1828 */ "DMRROWp17\0"
/* 1838 */ "VF27\0"
/* 1843 */ "VSL27\0"
/* 1849 */ "R27\0"
/* 1853 */ "S27\0"
/* 1857 */ "V27\0"
/* 1861 */ "DMRROW27\0"
/* 1870 */ "X27\0"
/* 1874 */ "VSRp27\0"
/* 1881 */ "DMRROWp27\0"
/* 1891 */ "DMRROW37\0"
/* 1900 */ "VSX37\0"
/* 1906 */ "DMRROW47\0"
/* 1915 */ "VSX47\0"
/* 1921 */ "DMRROW57\0"
/* 1930 */ "VSX57\0"
/* 1936 */ "UACC7\0"
/* 1942 */ "WACC7\0"
/* 1948 */ "VF7\0"
/* 1952 */ "WACC_HI7\0"
/* 1961 */ "VSL7\0"
/* 1966 */ "CR7\0"
/* 1970 */ "DMR7\0"
/* 1975 */ "S7\0"
/* 1978 */ "V7\0"
/* 1981 */ "DMRROW7\0"
/* 1989 */ "X7\0"
/* 1992 */ "G8p7\0"
/* 1997 */ "VSRp7\0"
/* 2003 */ "DMRROWp7\0"
/* 2012 */ "VF18\0"
/* 2017 */ "VSL18\0"
/* 2023 */ "R18\0"
/* 2027 */ "S18\0"
/* 2031 */ "V18\0"
/* 2035 */ "DMRROW18\0"
/* 2044 */ "X18\0"
/* 2048 */ "VSRp18\0"
/* 2055 */ "DMRROWp18\0"
/* 2065 */ "VF28\0"
/* 2070 */ "VSL28\0"
/* 2076 */ "R28\0"
/* 2080 */ "S28\0"
/* 2084 */ "V28\0"
/* 2088 */ "DMRROW28\0"
/* 2097 */ "X28\0"
/* 2101 */ "VSRp28\0"
/* 2108 */ "DMRROWp28\0"
/* 2118 */ "DMRROW38\0"
/* 2127 */ "VSX38\0"
/* 2133 */ "DMRROW48\0"
/* 2142 */ "VSX48\0"
/* 2148 */ "DMRROW58\0"
/* 2157 */ "VSX58\0"
/* 2163 */ "VF8\0"
/* 2167 */ "VSL8\0"
/* 2172 */ "ZERO8\0"
/* 2178 */ "BP8\0"
/* 2182 */ "FP8\0"
/* 2186 */ "LR8\0"
/* 2190 */ "CTR8\0"
/* 2195 */ "S8\0"
/* 2198 */ "V8\0"
/* 2201 */ "DMRROW8\0"
/* 2209 */ "X8\0"
/* 2212 */ "G8p8\0"
/* 2217 */ "VSRp8\0"
/* 2223 */ "DMRROWp8\0"
/* 2232 */ "VF19\0"
/* 2237 */ "VSL19\0"
/* 2243 */ "R19\0"
/* 2247 */ "S19\0"
/* 2251 */ "V19\0"
/* 2255 */ "DMRROW19\0"
/* 2264 */ "X19\0"
/* 2268 */ "VSRp19\0"
/* 2275 */ "DMRROWp19\0"
/* 2285 */ "VF29\0"
/* 2290 */ "VSL29\0"
/* 2296 */ "R29\0"
/* 2300 */ "S29\0"
/* 2304 */ "V29\0"
/* 2308 */ "DMRROW29\0"
/* 2317 */ "X29\0"
/* 2321 */ "VSRp29\0"
/* 2328 */ "DMRROWp29\0"
/* 2338 */ "DMRROW39\0"
/* 2347 */ "VSX39\0"
/* 2353 */ "DMRROW49\0"
/* 2362 */ "VSX49\0"
/* 2368 */ "DMRROW59\0"
/* 2377 */ "VSX59\0"
/* 2383 */ "VF9\0"
/* 2387 */ "VSL9\0"
/* 2392 */ "R9\0"
/* 2395 */ "S9\0"
/* 2398 */ "V9\0"
/* 2401 */ "DMRROW9\0"
/* 2409 */ "X9\0"
/* 2412 */ "G8p9\0"
/* 2417 */ "VSRp9\0"
/* 2423 */ "DMRROWp9\0"
/* 2432 */ "VRSAVE\0"
/* 2439 */ "RM\0"
/* 2442 */ "CR0UN\0"
/* 2448 */ "CR1UN\0"
/* 2454 */ "CR2UN\0"
/* 2460 */ "CR3UN\0"
/* 2466 */ "CR4UN\0"
/* 2472 */ "CR5UN\0"
/* 2478 */ "CR6UN\0"
/* 2484 */ "CR7UN\0"
/* 2490 */ "ZERO\0"
/* 2495 */ "BP\0"
/* 2498 */ "FP\0"
/* 2501 */ "CR0EQ\0"
/* 2507 */ "CR1EQ\0"
/* 2513 */ "CR2EQ\0"
/* 2519 */ "CR3EQ\0"
/* 2525 */ "CR4EQ\0"
/* 2531 */ "CR5EQ\0"
/* 2537 */ "CR6EQ\0"
/* 2543 */ "CR7EQ\0"
/* 2549 */ "SPEFSCR\0"
/* 2557 */ "XER\0"
/* 2561 */ "LR\0"
/* 2564 */ "CTR\0"
/* 2568 */ "CR0GT\0"
/* 2574 */ "CR1GT\0"
/* 2580 */ "CR2GT\0"
/* 2586 */ "CR3GT\0"
/* 2592 */ "CR4GT\0"
/* 2598 */ "CR5GT\0"
/* 2604 */ "CR6GT\0"
/* 2610 */ "CR7GT\0"
/* 2616 */ "CR0LT\0"
/* 2622 */ "CR1LT\0"
/* 2628 */ "CR2LT\0"
/* 2634 */ "CR3LT\0"
/* 2640 */ "CR4LT\0"
/* 2646 */ "CR5LT\0"
/* 2652 */ "CR6LT\0"
/* 2658 */ "CR7LT\0"
/* 2664 */ "CARRY\0"
};
#ifdef __GNUC__
#pragma GCC diagnostic pop
#endif
extern const MCRegisterDesc PPCRegDesc[] = { // Descriptors
{ 4, 0, 0, 0, 0, 0 },
{ 2495, 1, 408, 1, 22449, 0 },
{ 2664, 1, 1, 1, 22449, 0 },
{ 2564, 1, 1, 1, 22449, 0 },
{ 2498, 1, 938, 1, 22449, 0 },
{ 2561, 1, 1, 1, 22449, 0 },
{ 2439, 1, 1, 1, 22449, 0 },
{ 2549, 1, 1, 1, 22449, 0 },
{ 2432, 1, 1, 1, 22449, 0 },
{ 2557, 1, 1, 1, 22359, 0 },
{ 2490, 1, 1065, 1, 22359, 0 },
{ 211, 1185, 1, 17, 1588, 17 },
{ 503, 1212, 1, 17, 1588, 17 },
{ 757, 1239, 1, 17, 1588, 17 },
{ 1011, 1266, 1, 17, 1588, 17 },
{ 1250, 1293, 1, 17, 1588, 17 },
{ 1483, 1320, 1, 17, 1588, 17 },
{ 1710, 1347, 1, 17, 1588, 17 },
{ 1937, 1374, 1, 17, 1588, 17 },
{ 2178, 1401, 1, 0, 0, 2 },
{ 240, 410, 1, 7, 1508, 9 },
{ 532, 410, 1, 7, 1508, 9 },
{ 786, 410, 1, 7, 1508, 9 },
{ 1040, 410, 1, 7, 1508, 9 },
{ 1279, 410, 1, 7, 1508, 9 },
{ 1512, 410, 1, 7, 1508, 9 },
{ 1739, 410, 1, 7, 1508, 9 },
{ 1966, 410, 1, 7, 1508, 9 },
{ 2190, 1, 1, 1, 9040, 0 },
{ 244, 129, 874, 35, 1128, 27 },
{ 536, 173, 791, 35, 1128, 27 },
{ 790, 201, 791, 35, 1128, 27 },
{ 1044, 245, 708, 35, 1128, 27 },
{ 1283, 273, 708, 35, 1128, 27 },
{ 1516, 317, 625, 35, 1128, 27 },
{ 1743, 345, 625, 35, 1128, 27 },
{ 1970, 389, 582, 35, 1128, 27 },
{ 255, 1, 906, 1, 7921, 0 },
{ 547, 1, 901, 1, 7921, 0 },
{ 801, 1, 896, 1, 7921, 0 },
{ 1055, 1, 891, 1, 7921, 0 },
{ 1294, 1, 886, 1, 7921, 0 },
{ 1527, 1, 881, 1, 7921, 0 },
{ 1754, 1, 876, 1, 7921, 0 },
{ 1981, 1, 871, 1, 7921, 0 },
{ 2201, 1, 863, 1, 7921, 0 },
{ 2401, 1, 858, 1, 7921, 0 },
{ 23, 1, 853, 1, 7921, 0 },
{ 315, 1, 848, 1, 7921, 0 },
{ 607, 1, 823, 1, 7921, 0 },
{ 861, 1, 818, 1, 7921, 0 },
{ 1115, 1, 813, 1, 7921, 0 },
{ 1348, 1, 808, 1, 7921, 0 },
{ 1581, 1, 843, 1, 7921, 0 },
{ 1808, 1, 838, 1, 7921, 0 },
{ 2035, 1, 833, 1, 7921, 0 },
{ 2255, 1, 828, 1, 7921, 0 },
{ 82, 1, 803, 1, 7921, 0 },
{ 374, 1, 798, 1, 7921, 0 },
{ 666, 1, 793, 1, 7921, 0 },
{ 920, 1, 788, 1, 7921, 0 },
{ 1174, 1, 780, 1, 7921, 0 },
{ 1407, 1, 775, 1, 7921, 0 },
{ 1634, 1, 770, 1, 7921, 0 },
{ 1861, 1, 765, 1, 7921, 0 },
{ 2088, 1, 740, 1, 7921, 0 },
{ 2308, 1, 735, 1, 7921, 0 },
{ 135, 1, 730, 1, 7921, 0 },
{ 427, 1, 725, 1, 7921, 0 },
{ 696, 1, 760, 1, 7921, 0 },
{ 950, 1, 755, 1, 7921, 0 },
{ 1204, 1, 750, 1, 7921, 0 },
{ 1437, 1, 745, 1, 7921, 0 },
{ 1664, 1, 720, 1, 7921, 0 },
{ 1891, 1, 715, 1, 7921, 0 },
{ 2118, 1, 710, 1, 7921, 0 },
{ 2338, 1, 705, 1, 7921, 0 },
{ 165, 1, 697, 1, 7921, 0 },
{ 457, 1, 692, 1, 7921, 0 },
{ 711, 1, 687, 1, 7921, 0 },
{ 965, 1, 682, 1, 7921, 0 },
{ 1219, 1, 657, 1, 7921, 0 },
{ 1452, 1, 652, 1, 7921, 0 },
{ 1679, 1, 647, 1, 7921, 0 },
{ 1906, 1, 642, 1, 7921, 0 },
{ 2133, 1, 677, 1, 7921, 0 },
{ 2353, 1, 672, 1, 7921, 0 },
{ 180, 1, 667, 1, 7921, 0 },
{ 472, 1, 662, 1, 7921, 0 },
{ 726, 1, 637, 1, 7921, 0 },
{ 980, 1, 632, 1, 7921, 0 },
{ 1234, 1, 627, 1, 7921, 0 },
{ 1467, 1, 622, 1, 7921, 0 },
{ 1694, 1, 614, 1, 7921, 0 },
{ 1921, 1, 609, 1, 7921, 0 },
{ 2148, 1, 604, 1, 7921, 0 },
{ 2368, 1, 599, 1, 7921, 0 },
{ 195, 1, 594, 1, 7921, 0 },
{ 487, 1, 589, 1, 7921, 0 },
{ 741, 1, 584, 1, 7921, 0 },
{ 995, 1, 579, 1, 7921, 0 },
{ 283, 116, 902, 4, 1810, 6 },
{ 575, 123, 892, 4, 1810, 6 },
{ 829, 126, 882, 4, 1810, 6 },
{ 1083, 141, 872, 4, 1810, 6 },
{ 1316, 144, 859, 4, 1810, 6 },
{ 1549, 151, 849, 4, 1810, 6 },
{ 1776, 154, 819, 4, 1810, 6 },
{ 2003, 185, 809, 4, 1810, 6 },
{ 2223, 188, 839, 4, 1810, 6 },
{ 2423, 195, 829, 4, 1810, 6 },
{ 49, 198, 799, 4, 1810, 6 },
{ 341, 213, 789, 4, 1810, 6 },
{ 633, 216, 776, 4, 1810, 6 },
{ 887, 223, 766, 4, 1810, 6 },
{ 1141, 226, 736, 4, 1810, 6 },
{ 1374, 257, 726, 4, 1810, 6 },
{ 1601, 260, 756, 4, 1810, 6 },
{ 1828, 267, 746, 4, 1810, 6 },
{ 2055, 270, 716, 4, 1810, 6 },
{ 2275, 285, 706, 4, 1810, 6 },
{ 102, 288, 693, 4, 1810, 6 },
{ 394, 295, 683, 4, 1810, 6 },
{ 686, 298, 653, 4, 1810, 6 },
{ 940, 329, 643, 4, 1810, 6 },
{ 1194, 332, 673, 4, 1810, 6 },
{ 1427, 339, 663, 4, 1810, 6 },
{ 1654, 342, 633, 4, 1810, 6 },
{ 1881, 357, 623, 4, 1810, 6 },
{ 2108, 360, 610, 4, 1810, 6 },
{ 2328, 367, 600, 4, 1810, 6 },
{ 155, 370, 590, 4, 1810, 6 },
{ 447, 401, 580, 4, 1810, 6 },
{ 271, 157, 1, 50, 32, 36 },
{ 563, 229, 1, 50, 304, 36 },
{ 817, 301, 1, 50, 576, 36 },
{ 1071, 373, 1, 50, 848, 36 },
{ 223, 1, 1060, 1, 22225, 0 },
{ 515, 1, 1055, 1, 22225, 0 },
{ 769, 1, 1050, 1, 22225, 0 },
{ 1023, 1, 1045, 1, 22225, 0 },
{ 1262, 1, 1045, 1, 22225, 0 },
{ 1495, 1, 1040, 1, 22225, 0 },
{ 1722, 1, 1035, 1, 22225, 0 },
{ 1949, 1, 1030, 1, 22225, 0 },
{ 2164, 1, 1030, 1, 22225, 0 },
{ 2384, 1, 1025, 1, 22225, 0 },
{ 1, 1, 1020, 1, 22225, 0 },
{ 293, 1, 1015, 1, 22225, 0 },
{ 585, 1, 1015, 1, 22225, 0 },
{ 839, 1, 1010, 1, 22225, 0 },
{ 1093, 1, 1005, 1, 22225, 0 },
{ 1326, 1, 1000, 1, 22225, 0 },
{ 1559, 1, 1000, 1, 22225, 0 },
{ 1786, 1, 995, 1, 22225, 0 },
{ 2013, 1, 990, 1, 22225, 0 },
{ 2233, 1, 985, 1, 22225, 0 },
{ 60, 1, 985, 1, 22225, 0 },
{ 352, 1, 980, 1, 22225, 0 },
{ 644, 1, 975, 1, 22225, 0 },
{ 898, 1, 970, 1, 22225, 0 },
{ 1152, 1, 970, 1, 22225, 0 },
{ 1385, 1, 965, 1, 22225, 0 },
{ 1612, 1, 960, 1, 22225, 0 },
{ 1839, 1, 955, 1, 22225, 0 },
{ 2066, 1, 955, 1, 22225, 0 },
{ 2286, 1, 950, 1, 22225, 0 },
{ 113, 1, 945, 1, 22225, 0 },
{ 405, 1, 940, 1, 22225, 0 },
{ 2182, 1387, 1, 0, 6464, 2 },
{ 2186, 1, 1, 1, 22385, 0 },
{ 241, 1, 561, 1, 22385, 0 },
{ 533, 1, 557, 1, 22385, 0 },
{ 787, 1, 557, 1, 22385, 0 },
{ 1041, 1, 553, 1, 22385, 0 },
{ 1280, 1, 553, 1, 22385, 0 },
{ 1513, 1, 549, 1, 22385, 0 },
{ 1740, 1, 549, 1, 22385, 0 },
{ 1967, 1, 545, 1, 22385, 0 },
{ 2187, 1, 545, 1, 22385, 0 },
{ 2392, 1, 541, 1, 22385, 0 },
{ 11, 1, 541, 1, 22385, 0 },
{ 303, 1, 537, 1, 22385, 0 },
{ 595, 1, 537, 1, 22385, 0 },
{ 849, 1, 533, 1, 22385, 0 },
{ 1103, 1, 533, 1, 22385, 0 },
{ 1336, 1, 529, 1, 22385, 0 },
{ 1569, 1, 529, 1, 22385, 0 },
{ 1796, 1, 525, 1, 22385, 0 },
{ 2023, 1, 525, 1, 22385, 0 },
{ 2243, 1, 521, 1, 22385, 0 },
{ 70, 1, 521, 1, 22385, 0 },
{ 362, 1, 517, 1, 22385, 0 },
{ 654, 1, 517, 1, 22385, 0 },
{ 908, 1, 513, 1, 22385, 0 },
{ 1162, 1, 513, 1, 22385, 0 },
{ 1395, 1, 509, 1, 22385, 0 },
{ 1622, 1, 509, 1, 22385, 0 },
{ 1849, 1, 505, 1, 22385, 0 },
{ 2076, 1, 505, 1, 22385, 0 },
{ 2296, 1, 501, 1, 22385, 0 },
{ 123, 1, 501, 1, 22385, 0 },
{ 415, 1, 497, 1, 22385, 0 },
{ 249, 1399, 1, 0, 22321, 2 },
{ 541, 1399, 1, 0, 22321, 2 },
{ 795, 1399, 1, 0, 22321, 2 },
{ 1049, 1399, 1, 0, 22321, 2 },
{ 1288, 1399, 1, 0, 22321, 2 },
{ 1521, 1399, 1, 0, 22321, 2 },
{ 1748, 1399, 1, 0, 22321, 2 },
{ 1975, 1399, 1, 0, 22321, 2 },
{ 2195, 1399, 1, 0, 22321, 2 },
{ 2395, 1399, 1, 0, 22321, 2 },
{ 15, 1399, 1, 0, 22321, 2 },
{ 307, 1399, 1, 0, 22321, 2 },
{ 599, 1399, 1, 0, 22321, 2 },
{ 853, 1399, 1, 0, 22321, 2 },
{ 1107, 1399, 1, 0, 22321, 2 },
{ 1340, 1399, 1, 0, 22321, 2 },
{ 1573, 1399, 1, 0, 22321, 2 },
{ 1800, 1399, 1, 0, 22321, 2 },
{ 2027, 1399, 1, 0, 22321, 2 },
{ 2247, 1399, 1, 0, 22321, 2 },
{ 74, 1399, 1, 0, 22321, 2 },
{ 366, 1399, 1, 0, 22321, 2 },
{ 658, 1399, 1, 0, 22321, 2 },
{ 912, 1399, 1, 0, 22321, 2 },
{ 1166, 1399, 1, 0, 22321, 2 },
{ 1399, 1399, 1, 0, 22321, 2 },
{ 1626, 1399, 1, 0, 22321, 2 },
{ 1853, 1399, 1, 0, 22321, 2 },
{ 2080, 1399, 1, 0, 22321, 2 },
{ 2300, 1399, 1, 0, 22321, 2 },
{ 127, 1399, 1, 0, 22321, 2 },
{ 419, 1399, 1, 0, 22321, 2 },
{ 210, 1174, 1, 17, 1428, 17 },
{ 502, 1201, 1, 17, 1428, 17 },
{ 756, 1228, 1, 17, 1428, 17 },
{ 1010, 1255, 1, 17, 1428, 17 },
{ 1249, 1282, 1, 17, 1428, 17 },
{ 1482, 1309, 1, 17, 1428, 17 },
{ 1709, 1336, 1, 17, 1428, 17 },
{ 1936, 1363, 1, 17, 1428, 17 },
{ 252, 418, 936, 2, 22289, 4 },
{ 544, 418, 933, 2, 22289, 4 },
{ 798, 418, 933, 2, 22289, 4 },
{ 1052, 418, 930, 2, 22289, 4 },
{ 1291, 418, 930, 2, 22289, 4 },
{ 1524, 418, 927, 2, 22289, 4 },
{ 1751, 418, 927, 2, 22289, 4 },
{ 1978, 418, 924, 2, 22289, 4 },
{ 2198, 418, 924, 2, 22289, 4 },
{ 2398, 418, 921, 2, 22289, 4 },
{ 19, 418, 921, 2, 22289, 4 },
{ 311, 418, 918, 2, 22289, 4 },
{ 603, 418, 918, 2, 22289, 4 },
{ 857, 418, 915, 2, 22289, 4 },
{ 1111, 418, 915, 2, 22289, 4 },
{ 1344, 418, 874, 2, 22289, 4 },
{ 1577, 418, 874, 2, 22289, 4 },
{ 1804, 418, 791, 2, 22289, 4 },
{ 2031, 418, 791, 2, 22289, 4 },
{ 2251, 418, 708, 2, 22289, 4 },
{ 78, 418, 708, 2, 22289, 4 },
{ 370, 418, 625, 2, 22289, 4 },
{ 662, 418, 625, 2, 22289, 4 },
{ 916, 418, 582, 2, 22289, 4 },
{ 1170, 418, 582, 2, 22289, 4 },
{ 1403, 418, 577, 2, 22289, 4 },
{ 1630, 418, 577, 2, 22289, 4 },
{ 1857, 418, 574, 2, 22289, 4 },
{ 2084, 418, 574, 2, 22289, 4 },
{ 2304, 418, 571, 2, 22289, 4 },
{ 131, 418, 571, 2, 22289, 4 },
{ 423, 418, 568, 2, 22289, 4 },
{ 222, 1, 935, 1, 22257, 0 },
{ 514, 1, 932, 1, 22257, 0 },
{ 768, 1, 932, 1, 22257, 0 },
{ 1022, 1, 929, 1, 22257, 0 },
{ 1261, 1, 929, 1, 22257, 0 },
{ 1494, 1, 926, 1, 22257, 0 },
{ 1721, 1, 926, 1, 22257, 0 },
{ 1948, 1, 923, 1, 22257, 0 },
{ 2163, 1, 923, 1, 22257, 0 },
{ 2383, 1, 920, 1, 22257, 0 },
{ 0, 1, 920, 1, 22257, 0 },
{ 292, 1, 917, 1, 22257, 0 },
{ 584, 1, 917, 1, 22257, 0 },
{ 838, 1, 914, 1, 22257, 0 },
{ 1092, 1, 914, 1, 22257, 0 },
{ 1325, 1, 911, 1, 22257, 0 },
{ 1558, 1, 911, 1, 22257, 0 },
{ 1785, 1, 868, 1, 22257, 0 },
{ 2012, 1, 868, 1, 22257, 0 },
{ 2232, 1, 785, 1, 22257, 0 },
{ 59, 1, 785, 1, 22257, 0 },
{ 351, 1, 702, 1, 22257, 0 },
{ 643, 1, 702, 1, 22257, 0 },
{ 897, 1, 619, 1, 22257, 0 },
{ 1151, 1, 619, 1, 22257, 0 },
{ 1384, 1, 576, 1, 22257, 0 },
{ 1611, 1, 576, 1, 22257, 0 },
{ 1838, 1, 573, 1, 22257, 0 },
{ 2065, 1, 573, 1, 22257, 0 },
{ 2285, 1, 570, 1, 22257, 0 },
{ 112, 1, 570, 1, 22257, 0 },
{ 404, 1, 567, 1, 22257, 0 },
{ 235, 1172, 1061, 2, 17361, 4 },
{ 527, 1172, 1056, 2, 17361, 4 },
{ 781, 1172, 1051, 2, 17361, 4 },
{ 1035, 1172, 1046, 2, 17361, 4 },
{ 1274, 1172, 1046, 2, 17361, 4 },
{ 1507, 1172, 1041, 2, 17361, 4 },
{ 1734, 1172, 1036, 2, 17361, 4 },
{ 1961, 1172, 1031, 2, 17361, 4 },
{ 2167, 1172, 1031, 2, 17361, 4 },
{ 2387, 1172, 1026, 2, 17361, 4 },
{ 5, 1172, 1021, 2, 17361, 4 },
{ 297, 1172, 1016, 2, 17361, 4 },
{ 589, 1172, 1016, 2, 17361, 4 },
{ 843, 1172, 1011, 2, 17361, 4 },
{ 1097, 1172, 1006, 2, 17361, 4 },
{ 1330, 1172, 1001, 2, 17361, 4 },
{ 1563, 1172, 1001, 2, 17361, 4 },
{ 1790, 1172, 996, 2, 17361, 4 },
{ 2017, 1172, 991, 2, 17361, 4 },
{ 2237, 1172, 986, 2, 17361, 4 },
{ 64, 1172, 986, 2, 17361, 4 },
{ 356, 1172, 981, 2, 17361, 4 },
{ 648, 1172, 976, 2, 17361, 4 },
{ 902, 1172, 971, 2, 17361, 4 },
{ 1156, 1172, 971, 2, 17361, 4 },
{ 1389, 1172, 966, 2, 17361, 4 },
{ 1616, 1172, 961, 2, 17361, 4 },
{ 1843, 1172, 956, 2, 17361, 4 },
{ 2070, 1172, 956, 2, 17361, 4 },
{ 2290, 1172, 951, 2, 17361, 4 },
{ 117, 1172, 946, 2, 17361, 4 },
{ 409, 1172, 941, 2, 17361, 4 },
{ 277, 1169, 1057, 12, 1714, 14 },
{ 569, 1180, 1042, 12, 1714, 14 },
{ 823, 1196, 1042, 12, 1714, 14 },
{ 1077, 1207, 1027, 12, 1714, 14 },
{ 1310, 1223, 1027, 12, 1714, 14 },
{ 1543, 1234, 1012, 12, 1714, 14 },
{ 1770, 1250, 1012, 12, 1714, 14 },
{ 1997, 1261, 997, 12, 1714, 14 },
{ 2217, 1277, 997, 12, 1714, 14 },
{ 2417, 1288, 982, 12, 1714, 14 },
{ 42, 1304, 982, 12, 1714, 14 },
{ 334, 1315, 967, 12, 1714, 14 },
{ 626, 1331, 967, 12, 1714, 14 },
{ 880, 1342, 952, 12, 1714, 14 },
{ 1134, 1358, 952, 12, 1714, 14 },
{ 1367, 1369, 942, 12, 1714, 14 },
{ 1594, 415, 1, 12, 1762, 14 },
{ 1821, 420, 1, 12, 1762, 14 },
{ 2048, 425, 1, 12, 1762, 14 },
{ 2268, 430, 1, 12, 1762, 14 },
{ 95, 435, 1, 12, 1762, 14 },
{ 387, 440, 1, 12, 1762, 14 },
{ 679, 445, 1, 12, 1762, 14 },
{ 933, 450, 1, 12, 1762, 14 },
{ 1187, 455, 1, 12, 1762, 14 },
{ 1420, 460, 1, 12, 1762, 14 },
{ 1647, 465, 1, 12, 1762, 14 },
{ 1874, 470, 1, 12, 1762, 14 },
{ 2101, 475, 1, 12, 1762, 14 },
{ 2321, 480, 1, 12, 1762, 14 },
{ 148, 485, 1, 12, 1762, 14 },
{ 440, 490, 1, 12, 1762, 14 },
{ 705, 1, 1, 1, 22161, 0 },
{ 959, 1, 1, 1, 22161, 0 },
{ 1213, 1, 1, 1, 22161, 0 },
{ 1446, 1, 1, 1, 22161, 0 },
{ 1673, 1, 1, 1, 22161, 0 },
{ 1900, 1, 1, 1, 22161, 0 },
{ 2127, 1, 1, 1, 22161, 0 },
{ 2347, 1, 1, 1, 22161, 0 },
{ 174, 1, 1, 1, 22161, 0 },
{ 466, 1, 1, 1, 22161, 0 },
{ 720, 1, 1, 1, 22161, 0 },
{ 974, 1, 1, 1, 22161, 0 },
{ 1228, 1, 1, 1, 22161, 0 },
{ 1461, 1, 1, 1, 22161, 0 },
{ 1688, 1, 1, 1, 22161, 0 },
{ 1915, 1, 1, 1, 22161, 0 },
{ 2142, 1, 1, 1, 22161, 0 },
{ 2362, 1, 1, 1, 22161, 0 },
{ 189, 1, 1, 1, 22161, 0 },
{ 481, 1, 1, 1, 22161, 0 },
{ 735, 1, 1, 1, 22161, 0 },
{ 989, 1, 1, 1, 22161, 0 },
{ 1243, 1, 1, 1, 22161, 0 },
{ 1476, 1, 1, 1, 22161, 0 },
{ 1703, 1, 1, 1, 22161, 0 },
{ 1930, 1, 1, 1, 22161, 0 },
{ 2157, 1, 1, 1, 22161, 0 },
{ 2377, 1, 1, 1, 22161, 0 },
{ 204, 1, 1, 1, 22161, 0 },
{ 496, 1, 1, 1, 22161, 0 },
{ 750, 1, 1, 1, 22161, 0 },
{ 1004, 1, 1, 1, 22161, 0 },
{ 216, 119, 893, 28, 1352, 22 },
{ 508, 147, 830, 28, 1352, 22 },
{ 762, 191, 830, 28, 1352, 22 },
{ 1016, 219, 747, 28, 1352, 22 },
{ 1255, 263, 747, 28, 1352, 22 },
{ 1488, 291, 664, 28, 1352, 22 },
{ 1715, 335, 664, 28, 1352, 22 },
{ 1942, 363, 601, 28, 1352, 22 },
{ 226, 137, 873, 28, 1272, 22 },
{ 518, 181, 790, 28, 1272, 22 },
{ 772, 209, 790, 28, 1272, 22 },
{ 1026, 253, 707, 28, 1272, 22 },
{ 1265, 281, 707, 28, 1272, 22 },
{ 1498, 325, 624, 28, 1272, 22 },
{ 1725, 353, 624, 28, 1272, 22 },
{ 1952, 397, 581, 28, 1272, 22 },
{ 263, 1092, 563, 0, 17393, 2 },
{ 555, 1092, 559, 0, 17393, 2 },
{ 809, 1092, 559, 0, 17393, 2 },
{ 1063, 1092, 555, 0, 17393, 2 },
{ 1302, 1092, 555, 0, 17393, 2 },
{ 1535, 1092, 551, 0, 17393, 2 },
{ 1762, 1092, 551, 0, 17393, 2 },
{ 1989, 1092, 547, 0, 17393, 2 },
{ 2209, 1092, 547, 0, 17393, 2 },
{ 2409, 1092, 543, 0, 17393, 2 },
{ 32, 1092, 543, 0, 17393, 2 },
{ 324, 1092, 539, 0, 17393, 2 },
{ 616, 1092, 539, 0, 17393, 2 },
{ 870, 1092, 535, 0, 17393, 2 },
{ 1124, 1092, 535, 0, 17393, 2 },
{ 1357, 1092, 531, 0, 17393, 2 },
{ 1590, 1092, 531, 0, 17393, 2 },
{ 1817, 1092, 527, 0, 17393, 2 },
{ 2044, 1092, 527, 0, 17393, 2 },
{ 2264, 1092, 523, 0, 17393, 2 },
{ 91, 1092, 523, 0, 17393, 2 },
{ 383, 1092, 519, 0, 17393, 2 },
{ 675, 1092, 519, 0, 17393, 2 },
{ 929, 1092, 515, 0, 17393, 2 },
{ 1183, 1092, 515, 0, 17393, 2 },
{ 1416, 1092, 511, 0, 17393, 2 },
{ 1643, 1092, 511, 0, 17393, 2 },
{ 1870, 1092, 507, 0, 17393, 2 },
{ 2097, 1092, 507, 0, 17393, 2 },
{ 2317, 1092, 503, 0, 17393, 2 },
{ 144, 1092, 503, 0, 17393, 2 },
{ 436, 1092, 499, 0, 17393, 2 },
{ 2172, 1079, 1, 0, 6496, 2 },
{ 2501, 1, 1083, 1, 17172, 0 },
{ 2507, 1, 1083, 1, 17172, 0 },
{ 2513, 1, 1083, 1, 17172, 0 },
{ 2519, 1, 1083, 1, 17172, 0 },
{ 2525, 1, 1083, 1, 17172, 0 },
{ 2531, 1, 1083, 1, 17172, 0 },
{ 2537, 1, 1083, 1, 17172, 0 },
{ 2543, 1, 1083, 1, 17172, 0 },
{ 2568, 1, 1081, 1, 17140, 0 },
{ 2574, 1, 1081, 1, 17140, 0 },
{ 2580, 1, 1081, 1, 17140, 0 },
{ 2586, 1, 1081, 1, 17140, 0 },
{ 2592, 1, 1081, 1, 17140, 0 },
{ 2598, 1, 1081, 1, 17140, 0 },
{ 2604, 1, 1081, 1, 17140, 0 },
{ 2610, 1, 1081, 1, 17140, 0 },
{ 2616, 1, 1077, 1, 17108, 0 },
{ 2622, 1, 1077, 1, 17108, 0 },
{ 2628, 1, 1077, 1, 17108, 0 },
{ 2634, 1, 1077, 1, 17108, 0 },
{ 2640, 1, 1077, 1, 17108, 0 },
{ 2646, 1, 1077, 1, 17108, 0 },
{ 2652, 1, 1077, 1, 17108, 0 },
{ 2658, 1, 1077, 1, 17108, 0 },
{ 2442, 1, 1075, 1, 17076, 0 },
{ 2448, 1, 1075, 1, 17076, 0 },
{ 2454, 1, 1075, 1, 17076, 0 },
{ 2460, 1, 1075, 1, 17076, 0 },
{ 2466, 1, 1075, 1, 17076, 0 },
{ 2472, 1, 1075, 1, 17076, 0 },
{ 2478, 1, 1075, 1, 17076, 0 },
{ 2484, 1, 1075, 1, 17076, 0 },
{ 266, 1089, 1, 81, 1666, 53 },
{ 558, 1094, 1, 81, 1666, 53 },
{ 812, 1099, 1, 81, 1666, 53 },
{ 1066, 1104, 1, 81, 1666, 53 },
{ 1305, 1109, 1, 81, 1666, 53 },
{ 1538, 1114, 1, 81, 1666, 53 },
{ 1765, 1119, 1, 81, 1666, 53 },
{ 1992, 1124, 1, 81, 1666, 53 },
{ 2212, 1129, 1, 81, 1666, 53 },
{ 2412, 1134, 1, 81, 1666, 53 },
{ 36, 1139, 1, 81, 1666, 53 },
{ 328, 1144, 1, 81, 1666, 53 },
{ 620, 1149, 1, 81, 1666, 53 },
{ 874, 1154, 1, 81, 1666, 53 },
{ 1128, 1159, 1, 81, 1666, 53 },
{ 1361, 1164, 1, 81, 1666, 53 },
};
extern const MCPhysReg PPCRegUnitRoots[][2] = {
{ PPC::BP },
{ PPC::CARRY, PPC::XER },
{ PPC::CTR },
{ PPC::FP },
{ PPC::LR },
{ PPC::RM },
{ PPC::SPEFSCR },
{ PPC::VRSAVE },
{ PPC::ZERO },
{ PPC::F0 },
{ PPC::F1 },
{ PPC::F2 },
{ PPC::F3 },
{ PPC::F4 },
{ PPC::F5 },
{ PPC::F6 },
{ PPC::F7 },
{ PPC::F8 },
{ PPC::F9 },
{ PPC::F10 },
{ PPC::F11 },
{ PPC::F12 },
{ PPC::F13 },
{ PPC::F14 },
{ PPC::F15 },
{ PPC::F16 },
{ PPC::F17 },
{ PPC::F18 },
{ PPC::F19 },
{ PPC::F20 },
{ PPC::F21 },
{ PPC::F22 },
{ PPC::F23 },
{ PPC::F24 },
{ PPC::F25 },
{ PPC::F26 },
{ PPC::F27 },
{ PPC::F28 },
{ PPC::F29 },
{ PPC::F30 },
{ PPC::F31 },
{ PPC::CR0LT },
{ PPC::CR0GT },
{ PPC::CR0EQ },
{ PPC::CR0UN },
{ PPC::CR1LT },
{ PPC::CR1GT },
{ PPC::CR1EQ },
{ PPC::CR1UN },
{ PPC::CR2LT },
{ PPC::CR2GT },
{ PPC::CR2EQ },
{ PPC::CR2UN },
{ PPC::CR3LT },
{ PPC::CR3GT },
{ PPC::CR3EQ },
{ PPC::CR3UN },
{ PPC::CR4LT },
{ PPC::CR4GT },
{ PPC::CR4EQ },
{ PPC::CR4UN },
{ PPC::CR5LT },
{ PPC::CR5GT },
{ PPC::CR5EQ },
{ PPC::CR5UN },
{ PPC::CR6LT },
{ PPC::CR6GT },
{ PPC::CR6EQ },
{ PPC::CR6UN },
{ PPC::CR7LT },
{ PPC::CR7GT },
{ PPC::CR7EQ },
{ PPC::CR7UN },
{ PPC::CTR8 },
{ PPC::DMRROW0 },
{ PPC::DMRROW1 },
{ PPC::DMRROW2 },
{ PPC::DMRROW3 },
{ PPC::DMRROW4 },
{ PPC::DMRROW5 },
{ PPC::DMRROW6 },
{ PPC::DMRROW7 },
{ PPC::DMRROW8 },
{ PPC::DMRROW9 },
{ PPC::DMRROW10 },
{ PPC::DMRROW11 },
{ PPC::DMRROW12 },
{ PPC::DMRROW13 },
{ PPC::DMRROW14 },
{ PPC::DMRROW15 },
{ PPC::DMRROW16 },
{ PPC::DMRROW17 },
{ PPC::DMRROW18 },
{ PPC::DMRROW19 },
{ PPC::DMRROW20 },
{ PPC::DMRROW21 },
{ PPC::DMRROW22 },
{ PPC::DMRROW23 },
{ PPC::DMRROW24 },
{ PPC::DMRROW25 },
{ PPC::DMRROW26 },
{ PPC::DMRROW27 },
{ PPC::DMRROW28 },
{ PPC::DMRROW29 },
{ PPC::DMRROW30 },
{ PPC::DMRROW31 },
{ PPC::DMRROW32 },
{ PPC::DMRROW33 },
{ PPC::DMRROW34 },
{ PPC::DMRROW35 },
{ PPC::DMRROW36 },
{ PPC::DMRROW37 },
{ PPC::DMRROW38 },
{ PPC::DMRROW39 },
{ PPC::DMRROW40 },
{ PPC::DMRROW41 },
{ PPC::DMRROW42 },
{ PPC::DMRROW43 },
{ PPC::DMRROW44 },
{ PPC::DMRROW45 },
{ PPC::DMRROW46 },
{ PPC::DMRROW47 },
{ PPC::DMRROW48 },
{ PPC::DMRROW49 },
{ PPC::DMRROW50 },
{ PPC::DMRROW51 },
{ PPC::DMRROW52 },
{ PPC::DMRROW53 },
{ PPC::DMRROW54 },
{ PPC::DMRROW55 },
{ PPC::DMRROW56 },
{ PPC::DMRROW57 },
{ PPC::DMRROW58 },
{ PPC::DMRROW59 },
{ PPC::DMRROW60 },
{ PPC::DMRROW61 },
{ PPC::DMRROW62 },
{ PPC::DMRROW63 },
{ PPC::LR8 },
{ PPC::R0 },
{ PPC::R1 },
{ PPC::R2 },
{ PPC::R3 },
{ PPC::R4 },
{ PPC::R5 },
{ PPC::R6 },
{ PPC::R7 },
{ PPC::R8 },
{ PPC::R9 },
{ PPC::R10 },
{ PPC::R11 },
{ PPC::R12 },
{ PPC::R13 },
{ PPC::R14 },
{ PPC::R15 },
{ PPC::R16 },
{ PPC::R17 },
{ PPC::R18 },
{ PPC::R19 },
{ PPC::R20 },
{ PPC::R21 },
{ PPC::R22 },
{ PPC::R23 },
{ PPC::R24 },
{ PPC::R25 },
{ PPC::R26 },
{ PPC::R27 },
{ PPC::R28 },
{ PPC::R29 },
{ PPC::R30 },
{ PPC::R31 },
{ PPC::VF0 },
{ PPC::VF1 },
{ PPC::VF2 },
{ PPC::VF3 },
{ PPC::VF4 },
{ PPC::VF5 },
{ PPC::VF6 },
{ PPC::VF7 },
{ PPC::VF8 },
{ PPC::VF9 },
{ PPC::VF10 },
{ PPC::VF11 },
{ PPC::VF12 },
{ PPC::VF13 },
{ PPC::VF14 },
{ PPC::VF15 },
{ PPC::VF16 },
{ PPC::VF17 },
{ PPC::VF18 },
{ PPC::VF19 },
{ PPC::VF20 },
{ PPC::VF21 },
{ PPC::VF22 },
{ PPC::VF23 },
{ PPC::VF24 },
{ PPC::VF25 },
{ PPC::VF26 },
{ PPC::VF27 },
{ PPC::VF28 },
{ PPC::VF29 },
{ PPC::VF30 },
{ PPC::VF31 },
{ PPC::VSX32 },
{ PPC::VSX33 },
{ PPC::VSX34 },
{ PPC::VSX35 },
{ PPC::VSX36 },
{ PPC::VSX37 },
{ PPC::VSX38 },
{ PPC::VSX39 },
{ PPC::VSX40 },
{ PPC::VSX41 },
{ PPC::VSX42 },
{ PPC::VSX43 },
{ PPC::VSX44 },
{ PPC::VSX45 },
{ PPC::VSX46 },
{ PPC::VSX47 },
{ PPC::VSX48 },
{ PPC::VSX49 },
{ PPC::VSX50 },
{ PPC::VSX51 },
{ PPC::VSX52 },
{ PPC::VSX53 },
{ PPC::VSX54 },
{ PPC::VSX55 },
{ PPC::VSX56 },
{ PPC::VSX57 },
{ PPC::VSX58 },
{ PPC::VSX59 },
{ PPC::VSX60 },
{ PPC::VSX61 },
{ PPC::VSX62 },
{ PPC::VSX63 },
};
namespace { // Register classes...
// VSSRC Register Class...
const MCPhysReg VSSRC[] = {
PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F31, PPC::F30, PPC::F29, PPC::F28, PPC::F27, PPC::F26, PPC::F25, PPC::F24, PPC::F23, PPC::F22, PPC::F21, PPC::F20, PPC::F19, PPC::F18, PPC::F17, PPC::F16, PPC::F15, PPC::F14, PPC::VF2, PPC::VF3, PPC::VF4, PPC::VF5, PPC::VF0, PPC::VF1, PPC::VF6, PPC::VF7, PPC::VF8, PPC::VF9, PPC::VF10, PPC::VF11, PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15, PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19, PPC::VF31, PPC::VF30, PPC::VF29, PPC::VF28, PPC::VF27, PPC::VF26, PPC::VF25, PPC::VF24, PPC::VF23, PPC::VF22, PPC::VF21, PPC::VF20,
};
// VSSRC Bit set.
const uint8_t VSSRCBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
};
// GPRC Register Class...
const MCPhysReg GPRC[] = {
PPC::R2, PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R11, PPC::R12, PPC::R30, PPC::R29, PPC::R28, PPC::R27, PPC::R26, PPC::R25, PPC::R24, PPC::R23, PPC::R22, PPC::R21, PPC::R20, PPC::R19, PPC::R18, PPC::R17, PPC::R16, PPC::R15, PPC::R14, PPC::R13, PPC::R31, PPC::R0, PPC::R1, PPC::FP, PPC::BP,
};
// GPRC Bit set.
const uint8_t GPRCBits[] = {
0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
};
// GPRC_NOR0 Register Class...
const MCPhysReg GPRC_NOR0[] = {
PPC::R2, PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R11, PPC::R12, PPC::R30, PPC::R29, PPC::R28, PPC::R27, PPC::R26, PPC::R25, PPC::R24, PPC::R23, PPC::R22, PPC::R21, PPC::R20, PPC::R19, PPC::R18, PPC::R17, PPC::R16, PPC::R15, PPC::R14, PPC::R13, PPC::R31, PPC::R1, PPC::FP, PPC::BP, PPC::ZERO,
};
// GPRC_NOR0 Bit set.
const uint8_t GPRC_NOR0Bits[] = {
0x12, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x07,
};
// GPRC_and_GPRC_NOR0 Register Class...
const MCPhysReg GPRC_and_GPRC_NOR0[] = {
PPC::R2, PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R11, PPC::R12, PPC::R30, PPC::R29, PPC::R28, PPC::R27, PPC::R26, PPC::R25, PPC::R24, PPC::R23, PPC::R22, PPC::R21, PPC::R20, PPC::R19, PPC::R18, PPC::R17, PPC::R16, PPC::R15, PPC::R14, PPC::R13, PPC::R31, PPC::R1, PPC::FP, PPC::BP,
};
// GPRC_and_GPRC_NOR0 Bit set.
const uint8_t GPRC_and_GPRC_NOR0Bits[] = {
0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x07,
};
// CRBITRC Register Class...
const MCPhysReg CRBITRC[] = {
PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN, PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN, PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN, PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN, PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN, PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN, PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN, PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN,
};
// CRBITRC Bit set.
const uint8_t CRBITRCBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f,
};
// F4RC Register Class...
const MCPhysReg F4RC[] = {
PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F31, PPC::F30, PPC::F29, PPC::F28, PPC::F27, PPC::F26, PPC::F25, PPC::F24, PPC::F23, PPC::F22, PPC::F21, PPC::F20, PPC::F19, PPC::F18, PPC::F17, PPC::F16, PPC::F15, PPC::F14,
};
// F4RC Bit set.
const uint8_t F4RCBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01,
};
// CRRC Register Class...
const MCPhysReg CRRC[] = {
PPC::CR0, PPC::CR1, PPC::CR5, PPC::CR6, PPC::CR7, PPC::CR2, PPC::CR3, PPC::CR4,
};
// CRRC Bit set.
const uint8_t CRRCBits[] = {
0x00, 0x00, 0xf0, 0x0f,
};
// CARRYRC Register Class...
const MCPhysReg CARRYRC[] = {
PPC::CARRY, PPC::XER,
};
// CARRYRC Bit set.
const uint8_t CARRYRCBits[] = {
0x04, 0x02,
};
// CTRRC Register Class...
const MCPhysReg CTRRC[] = {
PPC::CTR,
};
// CTRRC Bit set.
const uint8_t CTRRCBits[] = {
0x08,
};
// LRRC Register Class...
const MCPhysReg LRRC[] = {
PPC::LR,
};
// LRRC Bit set.
const uint8_t LRRCBits[] = {
0x20,
};
// VRSAVERC Register Class...
const MCPhysReg VRSAVERC[] = {
PPC::VRSAVE,
};
// VRSAVERC Bit set.
const uint8_t VRSAVERCBits[] = {
0x00, 0x01,
};
// SPILLTOVSRRC Register Class...
const MCPhysReg SPILLTOVSRRC[] = {
PPC::X2, PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X11, PPC::X12, PPC::X30, PPC::X29, PPC::X28, PPC::X27, PPC::X26, PPC::X25, PPC::X24, PPC::X23, PPC::X22, PPC::X21, PPC::X20, PPC::X19, PPC::X18, PPC::X17, PPC::X16, PPC::X15, PPC::X14, PPC::X31, PPC::X13, PPC::X0, PPC::X1, PPC::FP8, PPC::BP8, PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::VF2, PPC::VF3, PPC::VF4, PPC::VF5, PPC::VF0, PPC::VF1, PPC::VF6, PPC::VF7, PPC::VF8, PPC::VF9, PPC::VF10, PPC::VF11, PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15, PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19,
};
// SPILLTOVSRRC Bit set.
const uint8_t SPILLTOVSRRCBits[] = {
0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x7f, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
};
// VSFRC Register Class...
const MCPhysReg VSFRC[] = {
PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F31, PPC::F30, PPC::F29, PPC::F28, PPC::F27, PPC::F26, PPC::F25, PPC::F24, PPC::F23, PPC::F22, PPC::F21, PPC::F20, PPC::F19, PPC::F18, PPC::F17, PPC::F16, PPC::F15, PPC::F14, PPC::VF2, PPC::VF3, PPC::VF4, PPC::VF5, PPC::VF0, PPC::VF1, PPC::VF6, PPC::VF7, PPC::VF8, PPC::VF9, PPC::VF10, PPC::VF11, PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15, PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19, PPC::VF31, PPC::VF30, PPC::VF29, PPC::VF28, PPC::VF27, PPC::VF26, PPC::VF25, PPC::VF24, PPC::VF23, PPC::VF22, PPC::VF21, PPC::VF20,
};
// VSFRC Bit set.
const uint8_t VSFRCBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
};
// G8RC Register Class...
const MCPhysReg G8RC[] = {
PPC::X2, PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X11, PPC::X12, PPC::X30, PPC::X29, PPC::X28, PPC::X27, PPC::X26, PPC::X25, PPC::X24, PPC::X23, PPC::X22, PPC::X21, PPC::X20, PPC::X19, PPC::X18, PPC::X17, PPC::X16, PPC::X15, PPC::X14, PPC::X31, PPC::X13, PPC::X0, PPC::X1, PPC::FP8, PPC::BP8,
};
// G8RC Bit set.
const uint8_t G8RCBits[] = {
0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
};
// G8RC_NOX0 Register Class...
const MCPhysReg G8RC_NOX0[] = {
PPC::X2, PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X11, PPC::X12, PPC::X30, PPC::X29, PPC::X28, PPC::X27, PPC::X26, PPC::X25, PPC::X24, PPC::X23, PPC::X22, PPC::X21, PPC::X20, PPC::X19, PPC::X18, PPC::X17, PPC::X16, PPC::X15, PPC::X14, PPC::X31, PPC::X13, PPC::X1, PPC::FP8, PPC::BP8, PPC::ZERO8,
};
// G8RC_NOX0 Bit set.
const uint8_t G8RC_NOX0Bits[] = {
0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f,
};
// SPILLTOVSRRC_and_VSFRC Register Class...
const MCPhysReg SPILLTOVSRRC_and_VSFRC[] = {
PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::VF2, PPC::VF3, PPC::VF4, PPC::VF5, PPC::VF0, PPC::VF1, PPC::VF6, PPC::VF7, PPC::VF8, PPC::VF9, PPC::VF10, PPC::VF11, PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15, PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19,
};
// SPILLTOVSRRC_and_VSFRC Bit set.
const uint8_t SPILLTOVSRRC_and_VSFRCBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x7f,
};
// G8RC_and_G8RC_NOX0 Register Class...
const MCPhysReg G8RC_and_G8RC_NOX0[] = {
PPC::X2, PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X11, PPC::X12, PPC::X30, PPC::X29, PPC::X28, PPC::X27, PPC::X26, PPC::X25, PPC::X24, PPC::X23, PPC::X22, PPC::X21, PPC::X20, PPC::X19, PPC::X18, PPC::X17, PPC::X16, PPC::X15, PPC::X14, PPC::X31, PPC::X13, PPC::X1, PPC::FP8, PPC::BP8,
};
// G8RC_and_G8RC_NOX0 Bit set.
const uint8_t G8RC_and_G8RC_NOX0Bits[] = {
0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x07,
};
// F8RC Register Class...
const MCPhysReg F8RC[] = {
PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F31, PPC::F30, PPC::F29, PPC::F28, PPC::F27, PPC::F26, PPC::F25, PPC::F24, PPC::F23, PPC::F22, PPC::F21, PPC::F20, PPC::F19, PPC::F18, PPC::F17, PPC::F16, PPC::F15, PPC::F14,
};
// F8RC Bit set.
const uint8_t F8RCBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01,
};
// SPERC Register Class...
const MCPhysReg SPERC[] = {
PPC::S2, PPC::S3, PPC::S4, PPC::S5, PPC::S6, PPC::S7, PPC::S8, PPC::S9, PPC::S10, PPC::S11, PPC::S12, PPC::S30, PPC::S29, PPC::S28, PPC::S27, PPC::S26, PPC::S25, PPC::S24, PPC::S23, PPC::S22, PPC::S21, PPC::S20, PPC::S19, PPC::S18, PPC::S17, PPC::S16, PPC::S15, PPC::S14, PPC::S13, PPC::S31, PPC::S0, PPC::S1,
};
// SPERC Bit set.
const uint8_t SPERCBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
};
// VFRC Register Class...
const MCPhysReg VFRC[] = {
PPC::VF2, PPC::VF3, PPC::VF4, PPC::VF5, PPC::VF0, PPC::VF1, PPC::VF6, PPC::VF7, PPC::VF8, PPC::VF9, PPC::VF10, PPC::VF11, PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15, PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19, PPC::VF31, PPC::VF30, PPC::VF29, PPC::VF28, PPC::VF27, PPC::VF26, PPC::VF25, PPC::VF24, PPC::VF23, PPC::VF22, PPC::VF21, PPC::VF20,
};
// VFRC Bit set.
const uint8_t VFRCBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
};
// SPERC_with_sub_32_in_GPRC_NOR0 Register Class...
const MCPhysReg SPERC_with_sub_32_in_GPRC_NOR0[] = {
PPC::S2, PPC::S3, PPC::S4, PPC::S5, PPC::S6, PPC::S7, PPC::S8, PPC::S9, PPC::S10, PPC::S11, PPC::S12, PPC::S30, PPC::S29, PPC::S28, PPC::S27, PPC::S26, PPC::S25, PPC::S24, PPC::S23, PPC::S22, PPC::S21, PPC::S20, PPC::S19, PPC::S18, PPC::S17, PPC::S16, PPC::S15, PPC::S14, PPC::S13, PPC::S31, PPC::S1,
};
// SPERC_with_sub_32_in_GPRC_NOR0 Bit set.
const uint8_t SPERC_with_sub_32_in_GPRC_NOR0Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x07,
};
// SPILLTOVSRRC_and_VFRC Register Class...
const MCPhysReg SPILLTOVSRRC_and_VFRC[] = {
PPC::VF2, PPC::VF3, PPC::VF4, PPC::VF5, PPC::VF0, PPC::VF1, PPC::VF6, PPC::VF7, PPC::VF8, PPC::VF9, PPC::VF10, PPC::VF11, PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15, PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19,
};
// SPILLTOVSRRC_and_VFRC Bit set.
const uint8_t SPILLTOVSRRC_and_VFRCBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x7f,
};
// SPILLTOVSRRC_and_F4RC Register Class...
const MCPhysReg SPILLTOVSRRC_and_F4RC[] = {
PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13,
};
// SPILLTOVSRRC_and_F4RC Bit set.
const uint8_t SPILLTOVSRRC_and_F4RCBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x7f,
};
// CTRRC8 Register Class...
const MCPhysReg CTRRC8[] = {
PPC::CTR8,
};
// CTRRC8 Bit set.
const uint8_t CTRRC8Bits[] = {
0x00, 0x00, 0x00, 0x10,
};
// LR8RC Register Class...
const MCPhysReg LR8RC[] = {
PPC::LR8,
};
// LR8RC Bit set.
const uint8_t LR8RCBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04,
};
// DMRROWRC Register Class...
const MCPhysReg DMRROWRC[] = {
PPC::DMRROW0, PPC::DMRROW1, PPC::DMRROW2, PPC::DMRROW3, PPC::DMRROW4, PPC::DMRROW5, PPC::DMRROW6, PPC::DMRROW7, PPC::DMRROW8, PPC::DMRROW9, PPC::DMRROW10, PPC::DMRROW11, PPC::DMRROW12, PPC::DMRROW13, PPC::DMRROW14, PPC::DMRROW15, PPC::DMRROW16, PPC::DMRROW17, PPC::DMRROW18, PPC::DMRROW19, PPC::DMRROW20, PPC::DMRROW21, PPC::DMRROW22, PPC::DMRROW23, PPC::DMRROW24, PPC::DMRROW25, PPC::DMRROW26, PPC::DMRROW27, PPC::DMRROW28, PPC::DMRROW29, PPC::DMRROW30, PPC::DMRROW31, PPC::DMRROW32, PPC::DMRROW33, PPC::DMRROW34, PPC::DMRROW35, PPC::DMRROW36, PPC::DMRROW37, PPC::DMRROW38, PPC::DMRROW39, PPC::DMRROW40, PPC::DMRROW41, PPC::DMRROW42, PPC::DMRROW43, PPC::DMRROW44, PPC::DMRROW45, PPC::DMRROW46, PPC::DMRROW47, PPC::DMRROW48, PPC::DMRROW49, PPC::DMRROW50, PPC::DMRROW51, PPC::DMRROW52, PPC::DMRROW53, PPC::DMRROW54, PPC::DMRROW55, PPC::DMRROW56, PPC::DMRROW57, PPC::DMRROW58, PPC::DMRROW59, PPC::DMRROW60, PPC::DMRROW61, PPC::DMRROW62, PPC::DMRROW63,
};
// DMRROWRC Bit set.
const uint8_t DMRROWRCBits[] = {
0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x1f,
};
// VSRC Register Class...
const MCPhysReg VSRC[] = {
PPC::VSL0, PPC::VSL1, PPC::VSL2, PPC::VSL3, PPC::VSL4, PPC::VSL5, PPC::VSL6, PPC::VSL7, PPC::VSL8, PPC::VSL9, PPC::VSL10, PPC::VSL11, PPC::VSL12, PPC::VSL13, PPC::VSL31, PPC::VSL30, PPC::VSL29, PPC::VSL28, PPC::VSL27, PPC::VSL26, PPC::VSL25, PPC::VSL24, PPC::VSL23, PPC::VSL22, PPC::VSL21, PPC::VSL20, PPC::VSL19, PPC::VSL18, PPC::VSL17, PPC::VSL16, PPC::VSL15, PPC::VSL14, PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V0, PPC::V1, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V31, PPC::V30, PPC::V29, PPC::V28, PPC::V27, PPC::V26, PPC::V25, PPC::V24, PPC::V23, PPC::V22, PPC::V21, PPC::V20,
};
// VSRC Bit set.
const uint8_t VSRCBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
};
// VSRC_with_sub_64_in_SPILLTOVSRRC Register Class...
const MCPhysReg VSRC_with_sub_64_in_SPILLTOVSRRC[] = {
PPC::VSL0, PPC::VSL1, PPC::VSL2, PPC::VSL3, PPC::VSL4, PPC::VSL5, PPC::VSL6, PPC::VSL7, PPC::VSL8, PPC::VSL9, PPC::VSL10, PPC::VSL11, PPC::VSL12, PPC::VSL13, PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V0, PPC::V1, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19,
};
// VSRC_with_sub_64_in_SPILLTOVSRRC Bit set.
const uint8_t VSRC_with_sub_64_in_SPILLTOVSRRCBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x01,
};
// VRRC Register Class...
const MCPhysReg VRRC[] = {
PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V0, PPC::V1, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V31, PPC::V30, PPC::V29, PPC::V28, PPC::V27, PPC::V26, PPC::V25, PPC::V24, PPC::V23, PPC::V22, PPC::V21, PPC::V20,
};
// VRRC Bit set.
const uint8_t VRRCBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
};
// VSLRC Register Class...
const MCPhysReg VSLRC[] = {
PPC::VSL0, PPC::VSL1, PPC::VSL2, PPC::VSL3, PPC::VSL4, PPC::VSL5, PPC::VSL6, PPC::VSL7, PPC::VSL8, PPC::VSL9, PPC::VSL10, PPC::VSL11, PPC::VSL12, PPC::VSL13, PPC::VSL31, PPC::VSL30, PPC::VSL29, PPC::VSL28, PPC::VSL27, PPC::VSL26, PPC::VSL25, PPC::VSL24, PPC::VSL23, PPC::VSL22, PPC::VSL21, PPC::VSL20, PPC::VSL19, PPC::VSL18, PPC::VSL17, PPC::VSL16, PPC::VSL15, PPC::VSL14,
};
// VSLRC Bit set.
const uint8_t VSLRCBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
};
// VRRC_with_sub_64_in_SPILLTOVSRRC Register Class...
const MCPhysReg VRRC_with_sub_64_in_SPILLTOVSRRC[] = {
PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V0, PPC::V1, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19,
};
// VRRC_with_sub_64_in_SPILLTOVSRRC Bit set.
const uint8_t VRRC_with_sub_64_in_SPILLTOVSRRCBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x7f,
};
// G8pRC Register Class...
const MCPhysReg G8pRC[] = {
PPC::G8p1, PPC::G8p2, PPC::G8p3, PPC::G8p4, PPC::G8p5, PPC::G8p14, PPC::G8p13, PPC::G8p12, PPC::G8p11, PPC::G8p10, PPC::G8p9, PPC::G8p8, PPC::G8p7, PPC::G8p15, PPC::G8p6, PPC::G8p0,
};
// G8pRC Bit set.
const uint8_t G8pRCBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f,
};
// G8pRC_with_sub_32_in_GPRC_NOR0 Register Class...
const MCPhysReg G8pRC_with_sub_32_in_GPRC_NOR0[] = {
PPC::G8p1, PPC::G8p2, PPC::G8p3, PPC::G8p4, PPC::G8p5, PPC::G8p14, PPC::G8p13, PPC::G8p12, PPC::G8p11, PPC::G8p10, PPC::G8p9, PPC::G8p8, PPC::G8p7, PPC::G8p15, PPC::G8p6,
};
// G8pRC_with_sub_32_in_GPRC_NOR0 Bit set.
const uint8_t G8pRC_with_sub_32_in_GPRC_NOR0Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f,
};
// VSLRC_with_sub_64_in_SPILLTOVSRRC Register Class...
const MCPhysReg VSLRC_with_sub_64_in_SPILLTOVSRRC[] = {
PPC::VSL0, PPC::VSL1, PPC::VSL2, PPC::VSL3, PPC::VSL4, PPC::VSL5, PPC::VSL6, PPC::VSL7, PPC::VSL8, PPC::VSL9, PPC::VSL10, PPC::VSL11, PPC::VSL12, PPC::VSL13,
};
// VSLRC_with_sub_64_in_SPILLTOVSRRC Bit set.
const uint8_t VSLRC_with_sub_64_in_SPILLTOVSRRCBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x01,
};
// DMRROWpRC Register Class...
const MCPhysReg DMRROWpRC[] = {
PPC::DMRROWp0, PPC::DMRROWp1, PPC::DMRROWp2, PPC::DMRROWp3, PPC::DMRROWp4, PPC::DMRROWp5, PPC::DMRROWp6, PPC::DMRROWp7, PPC::DMRROWp8, PPC::DMRROWp9, PPC::DMRROWp10, PPC::DMRROWp11, PPC::DMRROWp12, PPC::DMRROWp13, PPC::DMRROWp14, PPC::DMRROWp15, PPC::DMRROWp16, PPC::DMRROWp17, PPC::DMRROWp18, PPC::DMRROWp19, PPC::DMRROWp20, PPC::DMRROWp21, PPC::DMRROWp22, PPC::DMRROWp23, PPC::DMRROWp24, PPC::DMRROWp25, PPC::DMRROWp26, PPC::DMRROWp27, PPC::DMRROWp28, PPC::DMRROWp29, PPC::DMRROWp30, PPC::DMRROWp31,
};
// DMRROWpRC Bit set.
const uint8_t DMRROWpRCBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f,
};
// VSRpRC Register Class...
const MCPhysReg VSRpRC[] = {
PPC::VSRp17, PPC::VSRp18, PPC::VSRp16, PPC::VSRp19, PPC::VSRp20, PPC::VSRp21, PPC::VSRp22, PPC::VSRp23, PPC::VSRp24, PPC::VSRp25, PPC::VSRp31, PPC::VSRp30, PPC::VSRp29, PPC::VSRp28, PPC::VSRp27, PPC::VSRp26, PPC::VSRp0, PPC::VSRp1, PPC::VSRp2, PPC::VSRp3, PPC::VSRp4, PPC::VSRp5, PPC::VSRp6, PPC::VSRp15, PPC::VSRp14, PPC::VSRp13, PPC::VSRp12, PPC::VSRp11, PPC::VSRp10, PPC::VSRp9, PPC::VSRp8, PPC::VSRp7,
};
// VSRpRC Bit set.
const uint8_t VSRpRCBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
};
// VSRpRC_with_sub_64_in_SPILLTOVSRRC Register Class...
const MCPhysReg VSRpRC_with_sub_64_in_SPILLTOVSRRC[] = {
PPC::VSRp17, PPC::VSRp18, PPC::VSRp16, PPC::VSRp19, PPC::VSRp20, PPC::VSRp21, PPC::VSRp22, PPC::VSRp23, PPC::VSRp24, PPC::VSRp25, PPC::VSRp0, PPC::VSRp1, PPC::VSRp2, PPC::VSRp3, PPC::VSRp4, PPC::VSRp5, PPC::VSRp6,
};
// VSRpRC_with_sub_64_in_SPILLTOVSRRC Bit set.
const uint8_t VSRpRC_with_sub_64_in_SPILLTOVSRRCBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03, 0xf8, 0x1f,
};
// VSRpRC_with_sub_64_in_F4RC Register Class...
const MCPhysReg VSRpRC_with_sub_64_in_F4RC[] = {
PPC::VSRp0, PPC::VSRp1, PPC::VSRp2, PPC::VSRp3, PPC::VSRp4, PPC::VSRp5, PPC::VSRp6, PPC::VSRp15, PPC::VSRp14, PPC::VSRp13, PPC::VSRp12, PPC::VSRp11, PPC::VSRp10, PPC::VSRp9, PPC::VSRp8, PPC::VSRp7,
};
// VSRpRC_with_sub_64_in_F4RC Bit set.
const uint8_t VSRpRC_with_sub_64_in_F4RCBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x07,
};
// VSRpRC_with_sub_64_in_VFRC Register Class...
const MCPhysReg VSRpRC_with_sub_64_in_VFRC[] = {
PPC::VSRp17, PPC::VSRp18, PPC::VSRp16, PPC::VSRp19, PPC::VSRp20, PPC::VSRp21, PPC::VSRp22, PPC::VSRp23, PPC::VSRp24, PPC::VSRp25, PPC::VSRp31, PPC::VSRp30, PPC::VSRp29, PPC::VSRp28, PPC::VSRp27, PPC::VSRp26,
};
// VSRpRC_with_sub_64_in_VFRC Bit set.
const uint8_t VSRpRC_with_sub_64_in_VFRCBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x07,
};
// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC Register Class...
const MCPhysReg VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC[] = {
PPC::VSRp17, PPC::VSRp18, PPC::VSRp16, PPC::VSRp19, PPC::VSRp20, PPC::VSRp21, PPC::VSRp22, PPC::VSRp23, PPC::VSRp24, PPC::VSRp25,
};
// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC Bit set.
const uint8_t VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRCBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x1f,
};
// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC Register Class...
const MCPhysReg VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC[] = {
PPC::VSRp0, PPC::VSRp1, PPC::VSRp2, PPC::VSRp3, PPC::VSRp4, PPC::VSRp5, PPC::VSRp6,
};
// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC Bit set.
const uint8_t VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RCBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03,
};
// ACCRC Register Class...
const MCPhysReg ACCRC[] = {
PPC::ACC0, PPC::ACC1, PPC::ACC2, PPC::ACC3, PPC::ACC4, PPC::ACC5, PPC::ACC6, PPC::ACC7,
};
// ACCRC Bit set.
const uint8_t ACCRCBits[] = {
0x00, 0xf8, 0x07,
};
// UACCRC Register Class...
const MCPhysReg UACCRC[] = {
PPC::UACC0, PPC::UACC1, PPC::UACC2, PPC::UACC3, PPC::UACC4, PPC::UACC5, PPC::UACC6, PPC::UACC7,
};
// UACCRC Bit set.
const uint8_t UACCRCBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07,
};
// WACCRC Register Class...
const MCPhysReg WACCRC[] = {
PPC::WACC0, PPC::WACC1, PPC::WACC2, PPC::WACC3, PPC::WACC4, PPC::WACC5, PPC::WACC6, PPC::WACC7,
};
// WACCRC Bit set.
const uint8_t WACCRCBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07,
};
// WACC_HIRC Register Class...
const MCPhysReg WACC_HIRC[] = {
PPC::WACC_HI0, PPC::WACC_HI1, PPC::WACC_HI2, PPC::WACC_HI3, PPC::WACC_HI4, PPC::WACC_HI5, PPC::WACC_HI6, PPC::WACC_HI7,
};
// WACC_HIRC Bit set.
const uint8_t WACC_HIRCBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07,
};
// ACCRC_with_sub_64_in_SPILLTOVSRRC Register Class...
const MCPhysReg ACCRC_with_sub_64_in_SPILLTOVSRRC[] = {
PPC::ACC0, PPC::ACC1, PPC::ACC2, PPC::ACC3,
};
// ACCRC_with_sub_64_in_SPILLTOVSRRC Bit set.
const uint8_t ACCRC_with_sub_64_in_SPILLTOVSRRCBits[] = {
0x00, 0x78,
};
// UACCRC_with_sub_64_in_SPILLTOVSRRC Register Class...
const MCPhysReg UACCRC_with_sub_64_in_SPILLTOVSRRC[] = {
PPC::UACC0, PPC::UACC1, PPC::UACC2, PPC::UACC3,
};
// UACCRC_with_sub_64_in_SPILLTOVSRRC Bit set.
const uint8_t UACCRC_with_sub_64_in_SPILLTOVSRRCBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78,
};
// ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC Register Class...
const MCPhysReg ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC[] = {
PPC::ACC0, PPC::ACC1, PPC::ACC2,
};
// ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC Bit set.
const uint8_t ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCBits[] = {
0x00, 0x38,
};
// UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC Register Class...
const MCPhysReg UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC[] = {
PPC::UACC0, PPC::UACC1, PPC::UACC2,
};
// UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC Bit set.
const uint8_t UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38,
};
// DMRRC Register Class...
const MCPhysReg DMRRC[] = {
PPC::DMR0, PPC::DMR1, PPC::DMR2, PPC::DMR3, PPC::DMR4, PPC::DMR5, PPC::DMR6, PPC::DMR7,
};
// DMRRC Bit set.
const uint8_t DMRRCBits[] = {
0x00, 0x00, 0x00, 0xe0, 0x1f,
};
// DMRpRC Register Class...
const MCPhysReg DMRpRC[] = {
PPC::DMRp0, PPC::DMRp1, PPC::DMRp2, PPC::DMRp3,
};
// DMRpRC Bit set.
const uint8_t DMRpRCBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01,
};
} // end anonymous namespace
#ifdef __GNUC__
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Woverlength-strings"
#endif
extern const char PPCRegClassStrings[] = {
/* 0 */ "GPRC_and_GPRC_NOR0\0"
/* 19 */ "SPERC_with_sub_32_in_GPRC_NOR0\0"
/* 50 */ "G8pRC_with_sub_32_in_GPRC_NOR0\0"
/* 81 */ "G8RC_and_G8RC_NOX0\0"
/* 100 */ "CTRRC8\0"
/* 107 */ "VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC\0"
/* 151 */ "VSRpRC_with_sub_64_in_F4RC\0"
/* 178 */ "F8RC\0"
/* 183 */ "G8RC\0"
/* 188 */ "LR8RC\0"
/* 194 */ "UACCRC\0"
/* 201 */ "WACCRC\0"
/* 208 */ "SPERC\0"
/* 214 */ "VRSAVERC\0"
/* 223 */ "SPILLTOVSRRC_and_VSFRC\0"
/* 246 */ "VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC\0"
/* 290 */ "VSRpRC_with_sub_64_in_VFRC\0"
/* 317 */ "WACC_HIRC\0"
/* 327 */ "VSLRC\0"
/* 333 */ "GPRC\0"
/* 338 */ "CRRC\0"
/* 343 */ "LRRC\0"
/* 348 */ "DMRRC\0"
/* 354 */ "UACCRC_with_sub_64_in_SPILLTOVSRRC\0"
/* 389 */ "VSLRC_with_sub_64_in_SPILLTOVSRRC\0"
/* 423 */ "VRRC_with_sub_64_in_SPILLTOVSRRC\0"
/* 456 */ "VSRC_with_sub_64_in_SPILLTOVSRRC\0"
/* 489 */ "VSRpRC_with_sub_64_in_SPILLTOVSRRC\0"
/* 524 */ "UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC\0"
/* 574 */ "CTRRC\0"
/* 580 */ "VRRC\0"
/* 585 */ "VSSRC\0"
/* 591 */ "VSRC\0"
/* 596 */ "CRBITRC\0"
/* 604 */ "DMRROWRC\0"
/* 613 */ "CARRYRC\0"
/* 621 */ "G8pRC\0"
/* 627 */ "DMRpRC\0"
/* 634 */ "VSRpRC\0"
/* 641 */ "DMRROWpRC\0"
};
#ifdef __GNUC__
#pragma GCC diagnostic pop
#endif
extern const MCRegisterClass PPCMCRegisterClasses[] = {
{ VSSRC, VSSRCBits, 585, 64, sizeof(VSSRCBits), PPC::VSSRCRegClassID, 32, 1, true },
{ GPRC, GPRCBits, 333, 34, sizeof(GPRCBits), PPC::GPRCRegClassID, 32, 1, true },
{ GPRC_NOR0, GPRC_NOR0Bits, 9, 34, sizeof(GPRC_NOR0Bits), PPC::GPRC_NOR0RegClassID, 32, 1, true },
{ GPRC_and_GPRC_NOR0, GPRC_and_GPRC_NOR0Bits, 0, 33, sizeof(GPRC_and_GPRC_NOR0Bits), PPC::GPRC_and_GPRC_NOR0RegClassID, 32, 1, true },
{ CRBITRC, CRBITRCBits, 596, 32, sizeof(CRBITRCBits), PPC::CRBITRCRegClassID, 32, 1, true },
{ F4RC, F4RCBits, 146, 32, sizeof(F4RCBits), PPC::F4RCRegClassID, 32, 1, true },
{ CRRC, CRRCBits, 338, 8, sizeof(CRRCBits), PPC::CRRCRegClassID, 32, 1, true },
{ CARRYRC, CARRYRCBits, 613, 2, sizeof(CARRYRCBits), PPC::CARRYRCRegClassID, 32, -1, true },
{ CTRRC, CTRRCBits, 574, 1, sizeof(CTRRCBits), PPC::CTRRCRegClassID, 32, 1, false },
{ LRRC, LRRCBits, 343, 1, sizeof(LRRCBits), PPC::LRRCRegClassID, 32, 1, false },
{ VRSAVERC, VRSAVERCBits, 214, 1, sizeof(VRSAVERCBits), PPC::VRSAVERCRegClassID, 32, 1, true },
{ SPILLTOVSRRC, SPILLTOVSRRCBits, 376, 68, sizeof(SPILLTOVSRRCBits), PPC::SPILLTOVSRRCRegClassID, 64, 1, true },
{ VSFRC, VSFRCBits, 240, 64, sizeof(VSFRCBits), PPC::VSFRCRegClassID, 64, 1, true },
{ G8RC, G8RCBits, 183, 34, sizeof(G8RCBits), PPC::G8RCRegClassID, 64, 1, true },
{ G8RC_NOX0, G8RC_NOX0Bits, 90, 34, sizeof(G8RC_NOX0Bits), PPC::G8RC_NOX0RegClassID, 64, 1, true },
{ SPILLTOVSRRC_and_VSFRC, SPILLTOVSRRC_and_VSFRCBits, 223, 34, sizeof(SPILLTOVSRRC_and_VSFRCBits), PPC::SPILLTOVSRRC_and_VSFRCRegClassID, 64, 1, true },
{ G8RC_and_G8RC_NOX0, G8RC_and_G8RC_NOX0Bits, 81, 33, sizeof(G8RC_and_G8RC_NOX0Bits), PPC::G8RC_and_G8RC_NOX0RegClassID, 64, 1, true },
{ F8RC, F8RCBits, 178, 32, sizeof(F8RCBits), PPC::F8RCRegClassID, 64, 1, true },
{ SPERC, SPERCBits, 208, 32, sizeof(SPERCBits), PPC::SPERCRegClassID, 64, 1, true },
{ VFRC, VFRCBits, 285, 32, sizeof(VFRCBits), PPC::VFRCRegClassID, 64, 1, true },
{ SPERC_with_sub_32_in_GPRC_NOR0, SPERC_with_sub_32_in_GPRC_NOR0Bits, 19, 31, sizeof(SPERC_with_sub_32_in_GPRC_NOR0Bits), PPC::SPERC_with_sub_32_in_GPRC_NOR0RegClassID, 64, 1, true },
{ SPILLTOVSRRC_and_VFRC, SPILLTOVSRRC_and_VFRCBits, 268, 20, sizeof(SPILLTOVSRRC_and_VFRCBits), PPC::SPILLTOVSRRC_and_VFRCRegClassID, 64, 1, true },
{ SPILLTOVSRRC_and_F4RC, SPILLTOVSRRC_and_F4RCBits, 129, 14, sizeof(SPILLTOVSRRC_and_F4RCBits), PPC::SPILLTOVSRRC_and_F4RCRegClassID, 64, 1, true },
{ CTRRC8, CTRRC8Bits, 100, 1, sizeof(CTRRC8Bits), PPC::CTRRC8RegClassID, 64, 1, false },
{ LR8RC, LR8RCBits, 188, 1, sizeof(LR8RCBits), PPC::LR8RCRegClassID, 64, 1, false },
{ DMRROWRC, DMRROWRCBits, 604, 64, sizeof(DMRROWRCBits), PPC::DMRROWRCRegClassID, 128, 1, true },
{ VSRC, VSRCBits, 591, 64, sizeof(VSRCBits), PPC::VSRCRegClassID, 128, 1, true },
{ VSRC_with_sub_64_in_SPILLTOVSRRC, VSRC_with_sub_64_in_SPILLTOVSRRCBits, 456, 34, sizeof(VSRC_with_sub_64_in_SPILLTOVSRRCBits), PPC::VSRC_with_sub_64_in_SPILLTOVSRRCRegClassID, 128, 1, true },
{ VRRC, VRRCBits, 580, 32, sizeof(VRRCBits), PPC::VRRCRegClassID, 128, 1, true },
{ VSLRC, VSLRCBits, 327, 32, sizeof(VSLRCBits), PPC::VSLRCRegClassID, 128, 1, true },
{ VRRC_with_sub_64_in_SPILLTOVSRRC, VRRC_with_sub_64_in_SPILLTOVSRRCBits, 423, 20, sizeof(VRRC_with_sub_64_in_SPILLTOVSRRCBits), PPC::VRRC_with_sub_64_in_SPILLTOVSRRCRegClassID, 128, 1, true },
{ G8pRC, G8pRCBits, 621, 16, sizeof(G8pRCBits), PPC::G8pRCRegClassID, 128, 1, true },
{ G8pRC_with_sub_32_in_GPRC_NOR0, G8pRC_with_sub_32_in_GPRC_NOR0Bits, 50, 15, sizeof(G8pRC_with_sub_32_in_GPRC_NOR0Bits), PPC::G8pRC_with_sub_32_in_GPRC_NOR0RegClassID, 128, 1, true },
{ VSLRC_with_sub_64_in_SPILLTOVSRRC, VSLRC_with_sub_64_in_SPILLTOVSRRCBits, 389, 14, sizeof(VSLRC_with_sub_64_in_SPILLTOVSRRCBits), PPC::VSLRC_with_sub_64_in_SPILLTOVSRRCRegClassID, 128, 1, true },
{ DMRROWpRC, DMRROWpRCBits, 641, 32, sizeof(DMRROWpRCBits), PPC::DMRROWpRCRegClassID, 256, 1, true },
{ VSRpRC, VSRpRCBits, 634, 32, sizeof(VSRpRCBits), PPC::VSRpRCRegClassID, 256, 1, true },
{ VSRpRC_with_sub_64_in_SPILLTOVSRRC, VSRpRC_with_sub_64_in_SPILLTOVSRRCBits, 489, 17, sizeof(VSRpRC_with_sub_64_in_SPILLTOVSRRCBits), PPC::VSRpRC_with_sub_64_in_SPILLTOVSRRCRegClassID, 256, 1, true },
{ VSRpRC_with_sub_64_in_F4RC, VSRpRC_with_sub_64_in_F4RCBits, 151, 16, sizeof(VSRpRC_with_sub_64_in_F4RCBits), PPC::VSRpRC_with_sub_64_in_F4RCRegClassID, 256, 1, true },
{ VSRpRC_with_sub_64_in_VFRC, VSRpRC_with_sub_64_in_VFRCBits, 290, 16, sizeof(VSRpRC_with_sub_64_in_VFRCBits), PPC::VSRpRC_with_sub_64_in_VFRCRegClassID, 256, 1, true },
{ VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC, VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRCBits, 246, 10, sizeof(VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRCBits), PPC::VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRCRegClassID, 256, 1, true },
{ VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC, VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RCBits, 107, 7, sizeof(VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RCBits), PPC::VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RCRegClassID, 256, 1, true },
{ ACCRC, ACCRCBits, 195, 8, sizeof(ACCRCBits), PPC::ACCRCRegClassID, 512, 1, true },
{ UACCRC, UACCRCBits, 194, 8, sizeof(UACCRCBits), PPC::UACCRCRegClassID, 512, 1, true },
{ WACCRC, WACCRCBits, 201, 8, sizeof(WACCRCBits), PPC::WACCRCRegClassID, 512, 1, true },
{ WACC_HIRC, WACC_HIRCBits, 317, 8, sizeof(WACC_HIRCBits), PPC::WACC_HIRCRegClassID, 512, 1, true },
{ ACCRC_with_sub_64_in_SPILLTOVSRRC, ACCRC_with_sub_64_in_SPILLTOVSRRCBits, 355, 4, sizeof(ACCRC_with_sub_64_in_SPILLTOVSRRCBits), PPC::ACCRC_with_sub_64_in_SPILLTOVSRRCRegClassID, 512, 1, true },
{ UACCRC_with_sub_64_in_SPILLTOVSRRC, UACCRC_with_sub_64_in_SPILLTOVSRRCBits, 354, 4, sizeof(UACCRC_with_sub_64_in_SPILLTOVSRRCBits), PPC::UACCRC_with_sub_64_in_SPILLTOVSRRCRegClassID, 512, 1, true },
{ ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC, ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCBits, 525, 3, sizeof(ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCBits), PPC::ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCRegClassID, 512, 1, true },
{ UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC, UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCBits, 524, 3, sizeof(UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCBits), PPC::UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCRegClassID, 512, 1, true },
{ DMRRC, DMRRCBits, 348, 8, sizeof(DMRRCBits), PPC::DMRRCRegClassID, 1024, 1, true },
{ DMRpRC, DMRpRCBits, 627, 4, sizeof(DMRpRCBits), PPC::DMRpRCRegClassID, 2048, 1, true },
};
// PPC Dwarf<->LLVM register mappings.
extern const MCRegisterInfo::DwarfLLVMRegPair PPCDwarfFlavour0Dwarf2L[] = {
{ 0U, PPC::X0 },
{ 1U, PPC::X1 },
{ 2U, PPC::X2 },
{ 3U, PPC::X3 },
{ 4U, PPC::X4 },
{ 5U, PPC::X5 },
{ 6U, PPC::X6 },
{ 7U, PPC::X7 },
{ 8U, PPC::X8 },
{ 9U, PPC::X9 },
{ 10U, PPC::X10 },
{ 11U, PPC::X11 },
{ 12U, PPC::X12 },
{ 13U, PPC::X13 },
{ 14U, PPC::X14 },
{ 15U, PPC::X15 },
{ 16U, PPC::X16 },
{ 17U, PPC::X17 },
{ 18U, PPC::X18 },
{ 19U, PPC::X19 },
{ 20U, PPC::X20 },
{ 21U, PPC::X21 },
{ 22U, PPC::X22 },
{ 23U, PPC::X23 },
{ 24U, PPC::X24 },
{ 25U, PPC::X25 },
{ 26U, PPC::X26 },
{ 27U, PPC::X27 },
{ 28U, PPC::X28 },
{ 29U, PPC::X29 },
{ 30U, PPC::X30 },
{ 31U, PPC::X31 },
{ 32U, PPC::F0 },
{ 33U, PPC::F1 },
{ 34U, PPC::F2 },
{ 35U, PPC::F3 },
{ 36U, PPC::F4 },
{ 37U, PPC::F5 },
{ 38U, PPC::F6 },
{ 39U, PPC::F7 },
{ 40U, PPC::F8 },
{ 41U, PPC::F9 },
{ 42U, PPC::F10 },
{ 43U, PPC::F11 },
{ 44U, PPC::F12 },
{ 45U, PPC::F13 },
{ 46U, PPC::F14 },
{ 47U, PPC::F15 },
{ 48U, PPC::F16 },
{ 49U, PPC::F17 },
{ 50U, PPC::F18 },
{ 51U, PPC::F19 },
{ 52U, PPC::F20 },
{ 53U, PPC::F21 },
{ 54U, PPC::F22 },
{ 55U, PPC::F23 },
{ 56U, PPC::F24 },
{ 57U, PPC::F25 },
{ 58U, PPC::F26 },
{ 59U, PPC::F27 },
{ 60U, PPC::F28 },
{ 61U, PPC::F29 },
{ 62U, PPC::F30 },
{ 63U, PPC::F31 },
{ 65U, PPC::LR8 },
{ 66U, PPC::CTR8 },
{ 68U, PPC::CR0 },
{ 69U, PPC::CR1 },
{ 70U, PPC::CR2 },
{ 71U, PPC::CR3 },
{ 72U, PPC::CR4 },
{ 73U, PPC::CR5 },
{ 74U, PPC::CR6 },
{ 75U, PPC::CR7 },
{ 76U, PPC::XER },
{ 77U, PPC::VF0 },
{ 78U, PPC::VF1 },
{ 79U, PPC::VF2 },
{ 80U, PPC::VF3 },
{ 81U, PPC::VF4 },
{ 82U, PPC::VF5 },
{ 83U, PPC::VF6 },
{ 84U, PPC::VF7 },
{ 85U, PPC::VF8 },
{ 86U, PPC::VF9 },
{ 87U, PPC::VF10 },
{ 88U, PPC::VF11 },
{ 89U, PPC::VF12 },
{ 90U, PPC::VF13 },
{ 91U, PPC::VF14 },
{ 92U, PPC::VF15 },
{ 93U, PPC::VF16 },
{ 94U, PPC::VF17 },
{ 95U, PPC::VF18 },
{ 96U, PPC::VF19 },
{ 97U, PPC::VF20 },
{ 98U, PPC::VF21 },
{ 99U, PPC::VF22 },
{ 100U, PPC::VF23 },
{ 101U, PPC::VF24 },
{ 102U, PPC::VF25 },
{ 103U, PPC::VF26 },
{ 104U, PPC::VF27 },
{ 105U, PPC::VF28 },
{ 106U, PPC::VF29 },
{ 107U, PPC::VF30 },
{ 108U, PPC::VF31 },
{ 109U, PPC::VRSAVE },
{ 612U, PPC::SPEFSCR },
{ 1200U, PPC::S0 },
{ 1201U, PPC::S1 },
{ 1202U, PPC::S2 },
{ 1203U, PPC::S3 },
{ 1204U, PPC::S4 },
{ 1205U, PPC::S5 },
{ 1206U, PPC::S6 },
{ 1207U, PPC::S7 },
{ 1208U, PPC::S8 },
{ 1209U, PPC::S9 },
{ 1210U, PPC::S10 },
{ 1211U, PPC::S11 },
{ 1212U, PPC::S12 },
{ 1213U, PPC::S13 },
{ 1214U, PPC::S14 },
{ 1215U, PPC::S15 },
{ 1216U, PPC::S16 },
{ 1217U, PPC::S17 },
{ 1218U, PPC::S18 },
{ 1219U, PPC::S19 },
{ 1220U, PPC::S20 },
{ 1221U, PPC::S21 },
{ 1222U, PPC::S22 },
{ 1223U, PPC::S23 },
{ 1224U, PPC::S24 },
{ 1225U, PPC::S25 },
{ 1226U, PPC::S26 },
{ 1227U, PPC::S27 },
{ 1228U, PPC::S28 },
{ 1229U, PPC::S29 },
{ 1230U, PPC::S30 },
{ 1231U, PPC::S31 },
};
extern const unsigned PPCDwarfFlavour0Dwarf2LSize = std::size(PPCDwarfFlavour0Dwarf2L);
extern const MCRegisterInfo::DwarfLLVMRegPair PPCDwarfFlavour1Dwarf2L[] = {
{ 0U, PPC::R0 },
{ 1U, PPC::R1 },
{ 2U, PPC::R2 },
{ 3U, PPC::R3 },
{ 4U, PPC::R4 },
{ 5U, PPC::R5 },
{ 6U, PPC::R6 },
{ 7U, PPC::R7 },
{ 8U, PPC::R8 },
{ 9U, PPC::R9 },
{ 10U, PPC::R10 },
{ 11U, PPC::R11 },
{ 12U, PPC::R12 },
{ 13U, PPC::R13 },
{ 14U, PPC::R14 },
{ 15U, PPC::R15 },
{ 16U, PPC::R16 },
{ 17U, PPC::R17 },
{ 18U, PPC::R18 },
{ 19U, PPC::R19 },
{ 20U, PPC::R20 },
{ 21U, PPC::R21 },
{ 22U, PPC::R22 },
{ 23U, PPC::R23 },
{ 24U, PPC::R24 },
{ 25U, PPC::R25 },
{ 26U, PPC::R26 },
{ 27U, PPC::R27 },
{ 28U, PPC::R28 },
{ 29U, PPC::R29 },
{ 30U, PPC::R30 },
{ 31U, PPC::R31 },
{ 32U, PPC::F0 },
{ 33U, PPC::F1 },
{ 34U, PPC::F2 },
{ 35U, PPC::F3 },
{ 36U, PPC::F4 },
{ 37U, PPC::F5 },
{ 38U, PPC::F6 },
{ 39U, PPC::F7 },
{ 40U, PPC::F8 },
{ 41U, PPC::F9 },
{ 42U, PPC::F10 },
{ 43U, PPC::F11 },
{ 44U, PPC::F12 },
{ 45U, PPC::F13 },
{ 46U, PPC::F14 },
{ 47U, PPC::F15 },
{ 48U, PPC::F16 },
{ 49U, PPC::F17 },
{ 50U, PPC::F18 },
{ 51U, PPC::F19 },
{ 52U, PPC::F20 },
{ 53U, PPC::F21 },
{ 54U, PPC::F22 },
{ 55U, PPC::F23 },
{ 56U, PPC::F24 },
{ 57U, PPC::F25 },
{ 58U, PPC::F26 },
{ 59U, PPC::F27 },
{ 60U, PPC::F28 },
{ 61U, PPC::F29 },
{ 62U, PPC::F30 },
{ 63U, PPC::F31 },
{ 65U, PPC::LR },
{ 66U, PPC::CTR },
{ 68U, PPC::CR0 },
{ 69U, PPC::CR1 },
{ 70U, PPC::CR2 },
{ 71U, PPC::CR3 },
{ 72U, PPC::CR4 },
{ 73U, PPC::CR5 },
{ 74U, PPC::CR6 },
{ 75U, PPC::CR7 },
{ 77U, PPC::VF0 },
{ 78U, PPC::VF1 },
{ 79U, PPC::VF2 },
{ 80U, PPC::VF3 },
{ 81U, PPC::VF4 },
{ 82U, PPC::VF5 },
{ 83U, PPC::VF6 },
{ 84U, PPC::VF7 },
{ 85U, PPC::VF8 },
{ 86U, PPC::VF9 },
{ 87U, PPC::VF10 },
{ 88U, PPC::VF11 },
{ 89U, PPC::VF12 },
{ 90U, PPC::VF13 },
{ 91U, PPC::VF14 },
{ 92U, PPC::VF15 },
{ 93U, PPC::VF16 },
{ 94U, PPC::VF17 },
{ 95U, PPC::VF18 },
{ 96U, PPC::VF19 },
{ 97U, PPC::VF20 },
{ 98U, PPC::VF21 },
{ 99U, PPC::VF22 },
{ 100U, PPC::VF23 },
{ 101U, PPC::VF24 },
{ 102U, PPC::VF25 },
{ 103U, PPC::VF26 },
{ 104U, PPC::VF27 },
{ 105U, PPC::VF28 },
{ 106U, PPC::VF29 },
{ 107U, PPC::VF30 },
{ 108U, PPC::VF31 },
{ 112U, PPC::SPEFSCR },
{ 1200U, PPC::S0 },
{ 1201U, PPC::S1 },
{ 1202U, PPC::S2 },
{ 1203U, PPC::S3 },
{ 1204U, PPC::S4 },
{ 1205U, PPC::S5 },
{ 1206U, PPC::S6 },
{ 1207U, PPC::S7 },
{ 1208U, PPC::S8 },
{ 1209U, PPC::S9 },
{ 1210U, PPC::S10 },
{ 1211U, PPC::S11 },
{ 1212U, PPC::S12 },
{ 1213U, PPC::S13 },
{ 1214U, PPC::S14 },
{ 1215U, PPC::S15 },
{ 1216U, PPC::S16 },
{ 1217U, PPC::S17 },
{ 1218U, PPC::S18 },
{ 1219U, PPC::S19 },
{ 1220U, PPC::S20 },
{ 1221U, PPC::S21 },
{ 1222U, PPC::S22 },
{ 1223U, PPC::S23 },
{ 1224U, PPC::S24 },
{ 1225U, PPC::S25 },
{ 1226U, PPC::S26 },
{ 1227U, PPC::S27 },
{ 1228U, PPC::S28 },
{ 1229U, PPC::S29 },
{ 1230U, PPC::S30 },
{ 1231U, PPC::S31 },
};
extern const unsigned PPCDwarfFlavour1Dwarf2LSize = std::size(PPCDwarfFlavour1Dwarf2L);
extern const MCRegisterInfo::DwarfLLVMRegPair PPCEHFlavour0Dwarf2L[] = {
{ 0U, PPC::X0 },
{ 1U, PPC::X1 },
{ 2U, PPC::X2 },
{ 3U, PPC::X3 },
{ 4U, PPC::X4 },
{ 5U, PPC::X5 },
{ 6U, PPC::X6 },
{ 7U, PPC::X7 },
{ 8U, PPC::X8 },
{ 9U, PPC::X9 },
{ 10U, PPC::X10 },
{ 11U, PPC::X11 },
{ 12U, PPC::X12 },
{ 13U, PPC::X13 },
{ 14U, PPC::X14 },
{ 15U, PPC::X15 },
{ 16U, PPC::X16 },
{ 17U, PPC::X17 },
{ 18U, PPC::X18 },
{ 19U, PPC::X19 },
{ 20U, PPC::X20 },
{ 21U, PPC::X21 },
{ 22U, PPC::X22 },
{ 23U, PPC::X23 },
{ 24U, PPC::X24 },
{ 25U, PPC::X25 },
{ 26U, PPC::X26 },
{ 27U, PPC::X27 },
{ 28U, PPC::X28 },
{ 29U, PPC::X29 },
{ 30U, PPC::X30 },
{ 31U, PPC::X31 },
{ 32U, PPC::F0 },
{ 33U, PPC::F1 },
{ 34U, PPC::F2 },
{ 35U, PPC::F3 },
{ 36U, PPC::F4 },
{ 37U, PPC::F5 },
{ 38U, PPC::F6 },
{ 39U, PPC::F7 },
{ 40U, PPC::F8 },
{ 41U, PPC::F9 },
{ 42U, PPC::F10 },
{ 43U, PPC::F11 },
{ 44U, PPC::F12 },
{ 45U, PPC::F13 },
{ 46U, PPC::F14 },
{ 47U, PPC::F15 },
{ 48U, PPC::F16 },
{ 49U, PPC::F17 },
{ 50U, PPC::F18 },
{ 51U, PPC::F19 },
{ 52U, PPC::F20 },
{ 53U, PPC::F21 },
{ 54U, PPC::F22 },
{ 55U, PPC::F23 },
{ 56U, PPC::F24 },
{ 57U, PPC::F25 },
{ 58U, PPC::F26 },
{ 59U, PPC::F27 },
{ 60U, PPC::F28 },
{ 61U, PPC::F29 },
{ 62U, PPC::F30 },
{ 63U, PPC::F31 },
{ 65U, PPC::LR8 },
{ 66U, PPC::CTR8 },
{ 68U, PPC::CR0 },
{ 69U, PPC::CR1 },
{ 70U, PPC::CR2 },
{ 71U, PPC::CR3 },
{ 72U, PPC::CR4 },
{ 73U, PPC::CR5 },
{ 74U, PPC::CR6 },
{ 75U, PPC::CR7 },
{ 76U, PPC::XER },
{ 77U, PPC::VF0 },
{ 78U, PPC::VF1 },
{ 79U, PPC::VF2 },
{ 80U, PPC::VF3 },
{ 81U, PPC::VF4 },
{ 82U, PPC::VF5 },
{ 83U, PPC::VF6 },
{ 84U, PPC::VF7 },
{ 85U, PPC::VF8 },
{ 86U, PPC::VF9 },
{ 87U, PPC::VF10 },
{ 88U, PPC::VF11 },
{ 89U, PPC::VF12 },
{ 90U, PPC::VF13 },
{ 91U, PPC::VF14 },
{ 92U, PPC::VF15 },
{ 93U, PPC::VF16 },
{ 94U, PPC::VF17 },
{ 95U, PPC::VF18 },
{ 96U, PPC::VF19 },
{ 97U, PPC::VF20 },
{ 98U, PPC::VF21 },
{ 99U, PPC::VF22 },
{ 100U, PPC::VF23 },
{ 101U, PPC::VF24 },
{ 102U, PPC::VF25 },
{ 103U, PPC::VF26 },
{ 104U, PPC::VF27 },
{ 105U, PPC::VF28 },
{ 106U, PPC::VF29 },
{ 107U, PPC::VF30 },
{ 108U, PPC::VF31 },
{ 109U, PPC::VRSAVE },
{ 612U, PPC::SPEFSCR },
{ 1200U, PPC::S0 },
{ 1201U, PPC::S1 },
{ 1202U, PPC::S2 },
{ 1203U, PPC::S3 },
{ 1204U, PPC::S4 },
{ 1205U, PPC::S5 },
{ 1206U, PPC::S6 },
{ 1207U, PPC::S7 },
{ 1208U, PPC::S8 },
{ 1209U, PPC::S9 },
{ 1210U, PPC::S10 },
{ 1211U, PPC::S11 },
{ 1212U, PPC::S12 },
{ 1213U, PPC::S13 },
{ 1214U, PPC::S14 },
{ 1215U, PPC::S15 },
{ 1216U, PPC::S16 },
{ 1217U, PPC::S17 },
{ 1218U, PPC::S18 },
{ 1219U, PPC::S19 },
{ 1220U, PPC::S20 },
{ 1221U, PPC::S21 },
{ 1222U, PPC::S22 },
{ 1223U, PPC::S23 },
{ 1224U, PPC::S24 },
{ 1225U, PPC::S25 },
{ 1226U, PPC::S26 },
{ 1227U, PPC::S27 },
{ 1228U, PPC::S28 },
{ 1229U, PPC::S29 },
{ 1230U, PPC::S30 },
{ 1231U, PPC::S31 },
};
extern const unsigned PPCEHFlavour0Dwarf2LSize = std::size(PPCEHFlavour0Dwarf2L);
extern const MCRegisterInfo::DwarfLLVMRegPair PPCEHFlavour1Dwarf2L[] = {
{ 0U, PPC::R0 },
{ 1U, PPC::R1 },
{ 2U, PPC::R2 },
{ 3U, PPC::R3 },
{ 4U, PPC::R4 },
{ 5U, PPC::R5 },
{ 6U, PPC::R6 },
{ 7U, PPC::R7 },
{ 8U, PPC::R8 },
{ 9U, PPC::R9 },
{ 10U, PPC::R10 },
{ 11U, PPC::R11 },
{ 12U, PPC::R12 },
{ 13U, PPC::R13 },
{ 14U, PPC::R14 },
{ 15U, PPC::R15 },
{ 16U, PPC::R16 },
{ 17U, PPC::R17 },
{ 18U, PPC::R18 },
{ 19U, PPC::R19 },
{ 20U, PPC::R20 },
{ 21U, PPC::R21 },
{ 22U, PPC::R22 },
{ 23U, PPC::R23 },
{ 24U, PPC::R24 },
{ 25U, PPC::R25 },
{ 26U, PPC::R26 },
{ 27U, PPC::R27 },
{ 28U, PPC::R28 },
{ 29U, PPC::R29 },
{ 30U, PPC::R30 },
{ 31U, PPC::R31 },
{ 32U, PPC::F0 },
{ 33U, PPC::F1 },
{ 34U, PPC::F2 },
{ 35U, PPC::F3 },
{ 36U, PPC::F4 },
{ 37U, PPC::F5 },
{ 38U, PPC::F6 },
{ 39U, PPC::F7 },
{ 40U, PPC::F8 },
{ 41U, PPC::F9 },
{ 42U, PPC::F10 },
{ 43U, PPC::F11 },
{ 44U, PPC::F12 },
{ 45U, PPC::F13 },
{ 46U, PPC::F14 },
{ 47U, PPC::F15 },
{ 48U, PPC::F16 },
{ 49U, PPC::F17 },
{ 50U, PPC::F18 },
{ 51U, PPC::F19 },
{ 52U, PPC::F20 },
{ 53U, PPC::F21 },
{ 54U, PPC::F22 },
{ 55U, PPC::F23 },
{ 56U, PPC::F24 },
{ 57U, PPC::F25 },
{ 58U, PPC::F26 },
{ 59U, PPC::F27 },
{ 60U, PPC::F28 },
{ 61U, PPC::F29 },
{ 62U, PPC::F30 },
{ 63U, PPC::F31 },
{ 65U, PPC::LR },
{ 66U, PPC::CTR },
{ 68U, PPC::CR0 },
{ 69U, PPC::CR1 },
{ 70U, PPC::CR2 },
{ 71U, PPC::CR3 },
{ 72U, PPC::CR4 },
{ 73U, PPC::CR5 },
{ 74U, PPC::CR6 },
{ 75U, PPC::CR7 },
{ 77U, PPC::VF0 },
{ 78U, PPC::VF1 },
{ 79U, PPC::VF2 },
{ 80U, PPC::VF3 },
{ 81U, PPC::VF4 },
{ 82U, PPC::VF5 },
{ 83U, PPC::VF6 },
{ 84U, PPC::VF7 },
{ 85U, PPC::VF8 },
{ 86U, PPC::VF9 },
{ 87U, PPC::VF10 },
{ 88U, PPC::VF11 },
{ 89U, PPC::VF12 },
{ 90U, PPC::VF13 },
{ 91U, PPC::VF14 },
{ 92U, PPC::VF15 },
{ 93U, PPC::VF16 },
{ 94U, PPC::VF17 },
{ 95U, PPC::VF18 },
{ 96U, PPC::VF19 },
{ 97U, PPC::VF20 },
{ 98U, PPC::VF21 },
{ 99U, PPC::VF22 },
{ 100U, PPC::VF23 },
{ 101U, PPC::VF24 },
{ 102U, PPC::VF25 },
{ 103U, PPC::VF26 },
{ 104U, PPC::VF27 },
{ 105U, PPC::VF28 },
{ 106U, PPC::VF29 },
{ 107U, PPC::VF30 },
{ 108U, PPC::VF31 },
{ 112U, PPC::SPEFSCR },
{ 1200U, PPC::S0 },
{ 1201U, PPC::S1 },
{ 1202U, PPC::S2 },
{ 1203U, PPC::S3 },
{ 1204U, PPC::S4 },
{ 1205U, PPC::S5 },
{ 1206U, PPC::S6 },
{ 1207U, PPC::S7 },
{ 1208U, PPC::S8 },
{ 1209U, PPC::S9 },
{ 1210U, PPC::S10 },
{ 1211U, PPC::S11 },
{ 1212U, PPC::S12 },
{ 1213U, PPC::S13 },
{ 1214U, PPC::S14 },
{ 1215U, PPC::S15 },
{ 1216U, PPC::S16 },
{ 1217U, PPC::S17 },
{ 1218U, PPC::S18 },
{ 1219U, PPC::S19 },
{ 1220U, PPC::S20 },
{ 1221U, PPC::S21 },
{ 1222U, PPC::S22 },
{ 1223U, PPC::S23 },
{ 1224U, PPC::S24 },
{ 1225U, PPC::S25 },
{ 1226U, PPC::S26 },
{ 1227U, PPC::S27 },
{ 1228U, PPC::S28 },
{ 1229U, PPC::S29 },
{ 1230U, PPC::S30 },
{ 1231U, PPC::S31 },
};
extern const unsigned PPCEHFlavour1Dwarf2LSize = std::size(PPCEHFlavour1Dwarf2L);
extern const MCRegisterInfo::DwarfLLVMRegPair PPCDwarfFlavour0L2Dwarf[] = {
{ PPC::CARRY, 76U },
{ PPC::CTR, -2U },
{ PPC::LR, -2U },
{ PPC::SPEFSCR, 612U },
{ PPC::VRSAVE, 109U },
{ PPC::XER, 76U },
{ PPC::ZERO, -2U },
{ PPC::CR0, 68U },
{ PPC::CR1, 69U },
{ PPC::CR2, 70U },
{ PPC::CR3, 71U },
{ PPC::CR4, 72U },
{ PPC::CR5, 73U },
{ PPC::CR6, 74U },
{ PPC::CR7, 75U },
{ PPC::CTR8, 66U },
{ PPC::F0, 32U },
{ PPC::F1, 33U },
{ PPC::F2, 34U },
{ PPC::F3, 35U },
{ PPC::F4, 36U },
{ PPC::F5, 37U },
{ PPC::F6, 38U },
{ PPC::F7, 39U },
{ PPC::F8, 40U },
{ PPC::F9, 41U },
{ PPC::F10, 42U },
{ PPC::F11, 43U },
{ PPC::F12, 44U },
{ PPC::F13, 45U },
{ PPC::F14, 46U },
{ PPC::F15, 47U },
{ PPC::F16, 48U },
{ PPC::F17, 49U },
{ PPC::F18, 50U },
{ PPC::F19, 51U },
{ PPC::F20, 52U },
{ PPC::F21, 53U },
{ PPC::F22, 54U },
{ PPC::F23, 55U },
{ PPC::F24, 56U },
{ PPC::F25, 57U },
{ PPC::F26, 58U },
{ PPC::F27, 59U },
{ PPC::F28, 60U },
{ PPC::F29, 61U },
{ PPC::F30, 62U },
{ PPC::F31, 63U },
{ PPC::LR8, 65U },
{ PPC::R0, -2U },
{ PPC::R1, -2U },
{ PPC::R2, -2U },
{ PPC::R3, -2U },
{ PPC::R4, -2U },
{ PPC::R5, -2U },
{ PPC::R6, -2U },
{ PPC::R7, -2U },
{ PPC::R8, -2U },
{ PPC::R9, -2U },
{ PPC::R10, -2U },
{ PPC::R11, -2U },
{ PPC::R12, -2U },
{ PPC::R13, -2U },
{ PPC::R14, -2U },
{ PPC::R15, -2U },
{ PPC::R16, -2U },
{ PPC::R17, -2U },
{ PPC::R18, -2U },
{ PPC::R19, -2U },
{ PPC::R20, -2U },
{ PPC::R21, -2U },
{ PPC::R22, -2U },
{ PPC::R23, -2U },
{ PPC::R24, -2U },
{ PPC::R25, -2U },
{ PPC::R26, -2U },
{ PPC::R27, -2U },
{ PPC::R28, -2U },
{ PPC::R29, -2U },
{ PPC::R30, -2U },
{ PPC::R31, -2U },
{ PPC::S0, 1200U },
{ PPC::S1, 1201U },
{ PPC::S2, 1202U },
{ PPC::S3, 1203U },
{ PPC::S4, 1204U },
{ PPC::S5, 1205U },
{ PPC::S6, 1206U },
{ PPC::S7, 1207U },
{ PPC::S8, 1208U },
{ PPC::S9, 1209U },
{ PPC::S10, 1210U },
{ PPC::S11, 1211U },
{ PPC::S12, 1212U },
{ PPC::S13, 1213U },
{ PPC::S14, 1214U },
{ PPC::S15, 1215U },
{ PPC::S16, 1216U },
{ PPC::S17, 1217U },
{ PPC::S18, 1218U },
{ PPC::S19, 1219U },
{ PPC::S20, 1220U },
{ PPC::S21, 1221U },
{ PPC::S22, 1222U },
{ PPC::S23, 1223U },
{ PPC::S24, 1224U },
{ PPC::S25, 1225U },
{ PPC::S26, 1226U },
{ PPC::S27, 1227U },
{ PPC::S28, 1228U },
{ PPC::S29, 1229U },
{ PPC::S30, 1230U },
{ PPC::S31, 1231U },
{ PPC::V0, 77U },
{ PPC::V1, 78U },
{ PPC::V2, 79U },
{ PPC::V3, 80U },
{ PPC::V4, 81U },
{ PPC::V5, 82U },
{ PPC::V6, 83U },
{ PPC::V7, 84U },
{ PPC::V8, 85U },
{ PPC::V9, 86U },
{ PPC::V10, 87U },
{ PPC::V11, 88U },
{ PPC::V12, 89U },
{ PPC::V13, 90U },
{ PPC::V14, 91U },
{ PPC::V15, 92U },
{ PPC::V16, 93U },
{ PPC::V17, 94U },
{ PPC::V18, 95U },
{ PPC::V19, 96U },
{ PPC::V20, 97U },
{ PPC::V21, 98U },
{ PPC::V22, 99U },
{ PPC::V23, 100U },
{ PPC::V24, 101U },
{ PPC::V25, 102U },
{ PPC::V26, 103U },
{ PPC::V27, 104U },
{ PPC::V28, 105U },
{ PPC::V29, 106U },
{ PPC::V30, 107U },
{ PPC::V31, 108U },
{ PPC::VF0, 77U },
{ PPC::VF1, 78U },
{ PPC::VF2, 79U },
{ PPC::VF3, 80U },
{ PPC::VF4, 81U },
{ PPC::VF5, 82U },
{ PPC::VF6, 83U },
{ PPC::VF7, 84U },
{ PPC::VF8, 85U },
{ PPC::VF9, 86U },
{ PPC::VF10, 87U },
{ PPC::VF11, 88U },
{ PPC::VF12, 89U },
{ PPC::VF13, 90U },
{ PPC::VF14, 91U },
{ PPC::VF15, 92U },
{ PPC::VF16, 93U },
{ PPC::VF17, 94U },
{ PPC::VF18, 95U },
{ PPC::VF19, 96U },
{ PPC::VF20, 97U },
{ PPC::VF21, 98U },
{ PPC::VF22, 99U },
{ PPC::VF23, 100U },
{ PPC::VF24, 101U },
{ PPC::VF25, 102U },
{ PPC::VF26, 103U },
{ PPC::VF27, 104U },
{ PPC::VF28, 105U },
{ PPC::VF29, 106U },
{ PPC::VF30, 107U },
{ PPC::VF31, 108U },
{ PPC::VSL0, 32U },
{ PPC::VSL1, 33U },
{ PPC::VSL2, 34U },
{ PPC::VSL3, 35U },
{ PPC::VSL4, 36U },
{ PPC::VSL5, 37U },
{ PPC::VSL6, 38U },
{ PPC::VSL7, 39U },
{ PPC::VSL8, 40U },
{ PPC::VSL9, 41U },
{ PPC::VSL10, 42U },
{ PPC::VSL11, 43U },
{ PPC::VSL12, 44U },
{ PPC::VSL13, 45U },
{ PPC::VSL14, 46U },
{ PPC::VSL15, 47U },
{ PPC::VSL16, 48U },
{ PPC::VSL17, 49U },
{ PPC::VSL18, 50U },
{ PPC::VSL19, 51U },
{ PPC::VSL20, 52U },
{ PPC::VSL21, 53U },
{ PPC::VSL22, 54U },
{ PPC::VSL23, 55U },
{ PPC::VSL24, 56U },
{ PPC::VSL25, 57U },
{ PPC::VSL26, 58U },
{ PPC::VSL27, 59U },
{ PPC::VSL28, 60U },
{ PPC::VSL29, 61U },
{ PPC::VSL30, 62U },
{ PPC::VSL31, 63U },
{ PPC::X0, 0U },
{ PPC::X1, 1U },
{ PPC::X2, 2U },
{ PPC::X3, 3U },
{ PPC::X4, 4U },
{ PPC::X5, 5U },
{ PPC::X6, 6U },
{ PPC::X7, 7U },
{ PPC::X8, 8U },
{ PPC::X9, 9U },
{ PPC::X10, 10U },
{ PPC::X11, 11U },
{ PPC::X12, 12U },
{ PPC::X13, 13U },
{ PPC::X14, 14U },
{ PPC::X15, 15U },
{ PPC::X16, 16U },
{ PPC::X17, 17U },
{ PPC::X18, 18U },
{ PPC::X19, 19U },
{ PPC::X20, 20U },
{ PPC::X21, 21U },
{ PPC::X22, 22U },
{ PPC::X23, 23U },
{ PPC::X24, 24U },
{ PPC::X25, 25U },
{ PPC::X26, 26U },
{ PPC::X27, 27U },
{ PPC::X28, 28U },
{ PPC::X29, 29U },
{ PPC::X30, 30U },
{ PPC::X31, 31U },
{ PPC::ZERO8, 0U },
};
extern const unsigned PPCDwarfFlavour0L2DwarfSize = std::size(PPCDwarfFlavour0L2Dwarf);
extern const MCRegisterInfo::DwarfLLVMRegPair PPCDwarfFlavour1L2Dwarf[] = {
{ PPC::CTR, 66U },
{ PPC::LR, 65U },
{ PPC::SPEFSCR, 112U },
{ PPC::ZERO, 0U },
{ PPC::CR0, 68U },
{ PPC::CR1, 69U },
{ PPC::CR2, 70U },
{ PPC::CR3, 71U },
{ PPC::CR4, 72U },
{ PPC::CR5, 73U },
{ PPC::CR6, 74U },
{ PPC::CR7, 75U },
{ PPC::CTR8, -2U },
{ PPC::F0, 32U },
{ PPC::F1, 33U },
{ PPC::F2, 34U },
{ PPC::F3, 35U },
{ PPC::F4, 36U },
{ PPC::F5, 37U },
{ PPC::F6, 38U },
{ PPC::F7, 39U },
{ PPC::F8, 40U },
{ PPC::F9, 41U },
{ PPC::F10, 42U },
{ PPC::F11, 43U },
{ PPC::F12, 44U },
{ PPC::F13, 45U },
{ PPC::F14, 46U },
{ PPC::F15, 47U },
{ PPC::F16, 48U },
{ PPC::F17, 49U },
{ PPC::F18, 50U },
{ PPC::F19, 51U },
{ PPC::F20, 52U },
{ PPC::F21, 53U },
{ PPC::F22, 54U },
{ PPC::F23, 55U },
{ PPC::F24, 56U },
{ PPC::F25, 57U },
{ PPC::F26, 58U },
{ PPC::F27, 59U },
{ PPC::F28, 60U },
{ PPC::F29, 61U },
{ PPC::F30, 62U },
{ PPC::F31, 63U },
{ PPC::LR8, -2U },
{ PPC::R0, 0U },
{ PPC::R1, 1U },
{ PPC::R2, 2U },
{ PPC::R3, 3U },
{ PPC::R4, 4U },
{ PPC::R5, 5U },
{ PPC::R6, 6U },
{ PPC::R7, 7U },
{ PPC::R8, 8U },
{ PPC::R9, 9U },
{ PPC::R10, 10U },
{ PPC::R11, 11U },
{ PPC::R12, 12U },
{ PPC::R13, 13U },
{ PPC::R14, 14U },
{ PPC::R15, 15U },
{ PPC::R16, 16U },
{ PPC::R17, 17U },
{ PPC::R18, 18U },
{ PPC::R19, 19U },
{ PPC::R20, 20U },
{ PPC::R21, 21U },
{ PPC::R22, 22U },
{ PPC::R23, 23U },
{ PPC::R24, 24U },
{ PPC::R25, 25U },
{ PPC::R26, 26U },
{ PPC::R27, 27U },
{ PPC::R28, 28U },
{ PPC::R29, 29U },
{ PPC::R30, 30U },
{ PPC::R31, 31U },
{ PPC::S0, 1200U },
{ PPC::S1, 1201U },
{ PPC::S2, 1202U },
{ PPC::S3, 1203U },
{ PPC::S4, 1204U },
{ PPC::S5, 1205U },
{ PPC::S6, 1206U },
{ PPC::S7, 1207U },
{ PPC::S8, 1208U },
{ PPC::S9, 1209U },
{ PPC::S10, 1210U },
{ PPC::S11, 1211U },
{ PPC::S12, 1212U },
{ PPC::S13, 1213U },
{ PPC::S14, 1214U },
{ PPC::S15, 1215U },
{ PPC::S16, 1216U },
{ PPC::S17, 1217U },
{ PPC::S18, 1218U },
{ PPC::S19, 1219U },
{ PPC::S20, 1220U },
{ PPC::S21, 1221U },
{ PPC::S22, 1222U },
{ PPC::S23, 1223U },
{ PPC::S24, 1224U },
{ PPC::S25, 1225U },
{ PPC::S26, 1226U },
{ PPC::S27, 1227U },
{ PPC::S28, 1228U },
{ PPC::S29, 1229U },
{ PPC::S30, 1230U },
{ PPC::S31, 1231U },
{ PPC::V0, 77U },
{ PPC::V1, 78U },
{ PPC::V2, 79U },
{ PPC::V3, 80U },
{ PPC::V4, 81U },
{ PPC::V5, 82U },
{ PPC::V6, 83U },
{ PPC::V7, 84U },
{ PPC::V8, 85U },
{ PPC::V9, 86U },
{ PPC::V10, 87U },
{ PPC::V11, 88U },
{ PPC::V12, 89U },
{ PPC::V13, 90U },
{ PPC::V14, 91U },
{ PPC::V15, 92U },
{ PPC::V16, 93U },
{ PPC::V17, 94U },
{ PPC::V18, 95U },
{ PPC::V19, 96U },
{ PPC::V20, 97U },
{ PPC::V21, 98U },
{ PPC::V22, 99U },
{ PPC::V23, 100U },
{ PPC::V24, 101U },
{ PPC::V25, 102U },
{ PPC::V26, 103U },
{ PPC::V27, 104U },
{ PPC::V28, 105U },
{ PPC::V29, 106U },
{ PPC::V30, 107U },
{ PPC::V31, 108U },
{ PPC::VF0, 77U },
{ PPC::VF1, 78U },
{ PPC::VF2, 79U },
{ PPC::VF3, 80U },
{ PPC::VF4, 81U },
{ PPC::VF5, 82U },
{ PPC::VF6, 83U },
{ PPC::VF7, 84U },
{ PPC::VF8, 85U },
{ PPC::VF9, 86U },
{ PPC::VF10, 87U },
{ PPC::VF11, 88U },
{ PPC::VF12, 89U },
{ PPC::VF13, 90U },
{ PPC::VF14, 91U },
{ PPC::VF15, 92U },
{ PPC::VF16, 93U },
{ PPC::VF17, 94U },
{ PPC::VF18, 95U },
{ PPC::VF19, 96U },
{ PPC::VF20, 97U },
{ PPC::VF21, 98U },
{ PPC::VF22, 99U },
{ PPC::VF23, 100U },
{ PPC::VF24, 101U },
{ PPC::VF25, 102U },
{ PPC::VF26, 103U },
{ PPC::VF27, 104U },
{ PPC::VF28, 105U },
{ PPC::VF29, 106U },
{ PPC::VF30, 107U },
{ PPC::VF31, 108U },
{ PPC::VSL0, 32U },
{ PPC::VSL1, 33U },
{ PPC::VSL2, 34U },
{ PPC::VSL3, 35U },
{ PPC::VSL4, 36U },
{ PPC::VSL5, 37U },
{ PPC::VSL6, 38U },
{ PPC::VSL7, 39U },
{ PPC::VSL8, 40U },
{ PPC::VSL9, 41U },
{ PPC::VSL10, 42U },
{ PPC::VSL11, 43U },
{ PPC::VSL12, 44U },
{ PPC::VSL13, 45U },
{ PPC::VSL14, 46U },
{ PPC::VSL15, 47U },
{ PPC::VSL16, 48U },
{ PPC::VSL17, 49U },
{ PPC::VSL18, 50U },
{ PPC::VSL19, 51U },
{ PPC::VSL20, 52U },
{ PPC::VSL21, 53U },
{ PPC::VSL22, 54U },
{ PPC::VSL23, 55U },
{ PPC::VSL24, 56U },
{ PPC::VSL25, 57U },
{ PPC::VSL26, 58U },
{ PPC::VSL27, 59U },
{ PPC::VSL28, 60U },
{ PPC::VSL29, 61U },
{ PPC::VSL30, 62U },
{ PPC::VSL31, 63U },
{ PPC::X0, -2U },
{ PPC::X1, -2U },
{ PPC::X2, -2U },
{ PPC::X3, -2U },
{ PPC::X4, -2U },
{ PPC::X5, -2U },
{ PPC::X6, -2U },
{ PPC::X7, -2U },
{ PPC::X8, -2U },
{ PPC::X9, -2U },
{ PPC::X10, -2U },
{ PPC::X11, -2U },
{ PPC::X12, -2U },
{ PPC::X13, -2U },
{ PPC::X14, -2U },
{ PPC::X15, -2U },
{ PPC::X16, -2U },
{ PPC::X17, -2U },
{ PPC::X18, -2U },
{ PPC::X19, -2U },
{ PPC::X20, -2U },
{ PPC::X21, -2U },
{ PPC::X22, -2U },
{ PPC::X23, -2U },
{ PPC::X24, -2U },
{ PPC::X25, -2U },
{ PPC::X26, -2U },
{ PPC::X27, -2U },
{ PPC::X28, -2U },
{ PPC::X29, -2U },
{ PPC::X30, -2U },
{ PPC::X31, -2U },
{ PPC::ZERO8, -2U },
};
extern const unsigned PPCDwarfFlavour1L2DwarfSize = std::size(PPCDwarfFlavour1L2Dwarf);
extern const MCRegisterInfo::DwarfLLVMRegPair PPCEHFlavour0L2Dwarf[] = {
{ PPC::CARRY, 76U },
{ PPC::CTR, -2U },
{ PPC::LR, -2U },
{ PPC::SPEFSCR, 612U },
{ PPC::VRSAVE, 109U },
{ PPC::XER, 76U },
{ PPC::ZERO, -2U },
{ PPC::CR0, 68U },
{ PPC::CR1, 69U },
{ PPC::CR2, 70U },
{ PPC::CR3, 71U },
{ PPC::CR4, 72U },
{ PPC::CR5, 73U },
{ PPC::CR6, 74U },
{ PPC::CR7, 75U },
{ PPC::CTR8, 66U },
{ PPC::F0, 32U },
{ PPC::F1, 33U },
{ PPC::F2, 34U },
{ PPC::F3, 35U },
{ PPC::F4, 36U },
{ PPC::F5, 37U },
{ PPC::F6, 38U },
{ PPC::F7, 39U },
{ PPC::F8, 40U },
{ PPC::F9, 41U },
{ PPC::F10, 42U },
{ PPC::F11, 43U },
{ PPC::F12, 44U },
{ PPC::F13, 45U },
{ PPC::F14, 46U },
{ PPC::F15, 47U },
{ PPC::F16, 48U },
{ PPC::F17, 49U },
{ PPC::F18, 50U },
{ PPC::F19, 51U },
{ PPC::F20, 52U },
{ PPC::F21, 53U },
{ PPC::F22, 54U },
{ PPC::F23, 55U },
{ PPC::F24, 56U },
{ PPC::F25, 57U },
{ PPC::F26, 58U },
{ PPC::F27, 59U },
{ PPC::F28, 60U },
{ PPC::F29, 61U },
{ PPC::F30, 62U },
{ PPC::F31, 63U },
{ PPC::LR8, 65U },
{ PPC::R0, -2U },
{ PPC::R1, -2U },
{ PPC::R2, -2U },
{ PPC::R3, -2U },
{ PPC::R4, -2U },
{ PPC::R5, -2U },
{ PPC::R6, -2U },
{ PPC::R7, -2U },
{ PPC::R8, -2U },
{ PPC::R9, -2U },
{ PPC::R10, -2U },
{ PPC::R11, -2U },
{ PPC::R12, -2U },
{ PPC::R13, -2U },
{ PPC::R14, -2U },
{ PPC::R15, -2U },
{ PPC::R16, -2U },
{ PPC::R17, -2U },
{ PPC::R18, -2U },
{ PPC::R19, -2U },
{ PPC::R20, -2U },
{ PPC::R21, -2U },
{ PPC::R22, -2U },
{ PPC::R23, -2U },
{ PPC::R24, -2U },
{ PPC::R25, -2U },
{ PPC::R26, -2U },
{ PPC::R27, -2U },
{ PPC::R28, -2U },
{ PPC::R29, -2U },
{ PPC::R30, -2U },
{ PPC::R31, -2U },
{ PPC::S0, 1200U },
{ PPC::S1, 1201U },
{ PPC::S2, 1202U },
{ PPC::S3, 1203U },
{ PPC::S4, 1204U },
{ PPC::S5, 1205U },
{ PPC::S6, 1206U },
{ PPC::S7, 1207U },
{ PPC::S8, 1208U },
{ PPC::S9, 1209U },
{ PPC::S10, 1210U },
{ PPC::S11, 1211U },
{ PPC::S12, 1212U },
{ PPC::S13, 1213U },
{ PPC::S14, 1214U },
{ PPC::S15, 1215U },
{ PPC::S16, 1216U },
{ PPC::S17, 1217U },
{ PPC::S18, 1218U },
{ PPC::S19, 1219U },
{ PPC::S20, 1220U },
{ PPC::S21, 1221U },
{ PPC::S22, 1222U },
{ PPC::S23, 1223U },
{ PPC::S24, 1224U },
{ PPC::S25, 1225U },
{ PPC::S26, 1226U },
{ PPC::S27, 1227U },
{ PPC::S28, 1228U },
{ PPC::S29, 1229U },
{ PPC::S30, 1230U },
{ PPC::S31, 1231U },
{ PPC::V0, 77U },
{ PPC::V1, 78U },
{ PPC::V2, 79U },
{ PPC::V3, 80U },
{ PPC::V4, 81U },
{ PPC::V5, 82U },
{ PPC::V6, 83U },
{ PPC::V7, 84U },
{ PPC::V8, 85U },
{ PPC::V9, 86U },
{ PPC::V10, 87U },
{ PPC::V11, 88U },
{ PPC::V12, 89U },
{ PPC::V13, 90U },
{ PPC::V14, 91U },
{ PPC::V15, 92U },
{ PPC::V16, 93U },
{ PPC::V17, 94U },
{ PPC::V18, 95U },
{ PPC::V19, 96U },
{ PPC::V20, 97U },
{ PPC::V21, 98U },
{ PPC::V22, 99U },
{ PPC::V23, 100U },
{ PPC::V24, 101U },
{ PPC::V25, 102U },
{ PPC::V26, 103U },
{ PPC::V27, 104U },
{ PPC::V28, 105U },
{ PPC::V29, 106U },
{ PPC::V30, 107U },
{ PPC::V31, 108U },
{ PPC::VF0, 77U },
{ PPC::VF1, 78U },
{ PPC::VF2, 79U },
{ PPC::VF3, 80U },
{ PPC::VF4, 81U },
{ PPC::VF5, 82U },
{ PPC::VF6, 83U },
{ PPC::VF7, 84U },
{ PPC::VF8, 85U },
{ PPC::VF9, 86U },
{ PPC::VF10, 87U },
{ PPC::VF11, 88U },
{ PPC::VF12, 89U },
{ PPC::VF13, 90U },
{ PPC::VF14, 91U },
{ PPC::VF15, 92U },
{ PPC::VF16, 93U },
{ PPC::VF17, 94U },
{ PPC::VF18, 95U },
{ PPC::VF19, 96U },
{ PPC::VF20, 97U },
{ PPC::VF21, 98U },
{ PPC::VF22, 99U },
{ PPC::VF23, 100U },
{ PPC::VF24, 101U },
{ PPC::VF25, 102U },
{ PPC::VF26, 103U },
{ PPC::VF27, 104U },
{ PPC::VF28, 105U },
{ PPC::VF29, 106U },
{ PPC::VF30, 107U },
{ PPC::VF31, 108U },
{ PPC::VSL0, 32U },
{ PPC::VSL1, 33U },
{ PPC::VSL2, 34U },
{ PPC::VSL3, 35U },
{ PPC::VSL4, 36U },
{ PPC::VSL5, 37U },
{ PPC::VSL6, 38U },
{ PPC::VSL7, 39U },
{ PPC::VSL8, 40U },
{ PPC::VSL9, 41U },
{ PPC::VSL10, 42U },
{ PPC::VSL11, 43U },
{ PPC::VSL12, 44U },
{ PPC::VSL13, 45U },
{ PPC::VSL14, 46U },
{ PPC::VSL15, 47U },
{ PPC::VSL16, 48U },
{ PPC::VSL17, 49U },
{ PPC::VSL18, 50U },
{ PPC::VSL19, 51U },
{ PPC::VSL20, 52U },
{ PPC::VSL21, 53U },
{ PPC::VSL22, 54U },
{ PPC::VSL23, 55U },
{ PPC::VSL24, 56U },
{ PPC::VSL25, 57U },
{ PPC::VSL26, 58U },
{ PPC::VSL27, 59U },
{ PPC::VSL28, 60U },
{ PPC::VSL29, 61U },
{ PPC::VSL30, 62U },
{ PPC::VSL31, 63U },
{ PPC::X0, 0U },
{ PPC::X1, 1U },
{ PPC::X2, 2U },
{ PPC::X3, 3U },
{ PPC::X4, 4U },
{ PPC::X5, 5U },
{ PPC::X6, 6U },
{ PPC::X7, 7U },
{ PPC::X8, 8U },
{ PPC::X9, 9U },
{ PPC::X10, 10U },
{ PPC::X11, 11U },
{ PPC::X12, 12U },
{ PPC::X13, 13U },
{ PPC::X14, 14U },
{ PPC::X15, 15U },
{ PPC::X16, 16U },
{ PPC::X17, 17U },
{ PPC::X18, 18U },
{ PPC::X19, 19U },
{ PPC::X20, 20U },
{ PPC::X21, 21U },
{ PPC::X22, 22U },
{ PPC::X23, 23U },
{ PPC::X24, 24U },
{ PPC::X25, 25U },
{ PPC::X26, 26U },
{ PPC::X27, 27U },
{ PPC::X28, 28U },
{ PPC::X29, 29U },
{ PPC::X30, 30U },
{ PPC::X31, 31U },
{ PPC::ZERO8, 0U },
};
extern const unsigned PPCEHFlavour0L2DwarfSize = std::size(PPCEHFlavour0L2Dwarf);
extern const MCRegisterInfo::DwarfLLVMRegPair PPCEHFlavour1L2Dwarf[] = {
{ PPC::CTR, 66U },
{ PPC::LR, 65U },
{ PPC::SPEFSCR, 112U },
{ PPC::ZERO, 0U },
{ PPC::CR0, 68U },
{ PPC::CR1, 69U },
{ PPC::CR2, 70U },
{ PPC::CR3, 71U },
{ PPC::CR4, 72U },
{ PPC::CR5, 73U },
{ PPC::CR6, 74U },
{ PPC::CR7, 75U },
{ PPC::CTR8, -2U },
{ PPC::F0, 32U },
{ PPC::F1, 33U },
{ PPC::F2, 34U },
{ PPC::F3, 35U },
{ PPC::F4, 36U },
{ PPC::F5, 37U },
{ PPC::F6, 38U },
{ PPC::F7, 39U },
{ PPC::F8, 40U },
{ PPC::F9, 41U },
{ PPC::F10, 42U },
{ PPC::F11, 43U },
{ PPC::F12, 44U },
{ PPC::F13, 45U },
{ PPC::F14, 46U },
{ PPC::F15, 47U },
{ PPC::F16, 48U },
{ PPC::F17, 49U },
{ PPC::F18, 50U },
{ PPC::F19, 51U },
{ PPC::F20, 52U },
{ PPC::F21, 53U },
{ PPC::F22, 54U },
{ PPC::F23, 55U },
{ PPC::F24, 56U },
{ PPC::F25, 57U },
{ PPC::F26, 58U },
{ PPC::F27, 59U },
{ PPC::F28, 60U },
{ PPC::F29, 61U },
{ PPC::F30, 62U },
{ PPC::F31, 63U },
{ PPC::LR8, -2U },
{ PPC::R0, 0U },
{ PPC::R1, 1U },
{ PPC::R2, 2U },
{ PPC::R3, 3U },
{ PPC::R4, 4U },
{ PPC::R5, 5U },
{ PPC::R6, 6U },
{ PPC::R7, 7U },
{ PPC::R8, 8U },
{ PPC::R9, 9U },
{ PPC::R10, 10U },
{ PPC::R11, 11U },
{ PPC::R12, 12U },
{ PPC::R13, 13U },
{ PPC::R14, 14U },
{ PPC::R15, 15U },
{ PPC::R16, 16U },
{ PPC::R17, 17U },
{ PPC::R18, 18U },
{ PPC::R19, 19U },
{ PPC::R20, 20U },
{ PPC::R21, 21U },
{ PPC::R22, 22U },
{ PPC::R23, 23U },
{ PPC::R24, 24U },
{ PPC::R25, 25U },
{ PPC::R26, 26U },
{ PPC::R27, 27U },
{ PPC::R28, 28U },
{ PPC::R29, 29U },
{ PPC::R30, 30U },
{ PPC::R31, 31U },
{ PPC::S0, 1200U },
{ PPC::S1, 1201U },
{ PPC::S2, 1202U },
{ PPC::S3, 1203U },
{ PPC::S4, 1204U },
{ PPC::S5, 1205U },
{ PPC::S6, 1206U },
{ PPC::S7, 1207U },
{ PPC::S8, 1208U },
{ PPC::S9, 1209U },
{ PPC::S10, 1210U },
{ PPC::S11, 1211U },
{ PPC::S12, 1212U },
{ PPC::S13, 1213U },
{ PPC::S14, 1214U },
{ PPC::S15, 1215U },
{ PPC::S16, 1216U },
{ PPC::S17, 1217U },
{ PPC::S18, 1218U },
{ PPC::S19, 1219U },
{ PPC::S20, 1220U },
{ PPC::S21, 1221U },
{ PPC::S22, 1222U },
{ PPC::S23, 1223U },
{ PPC::S24, 1224U },
{ PPC::S25, 1225U },
{ PPC::S26, 1226U },
{ PPC::S27, 1227U },
{ PPC::S28, 1228U },
{ PPC::S29, 1229U },
{ PPC::S30, 1230U },
{ PPC::S31, 1231U },
{ PPC::V0, 77U },
{ PPC::V1, 78U },
{ PPC::V2, 79U },
{ PPC::V3, 80U },
{ PPC::V4, 81U },
{ PPC::V5, 82U },
{ PPC::V6, 83U },
{ PPC::V7, 84U },
{ PPC::V8, 85U },
{ PPC::V9, 86U },
{ PPC::V10, 87U },
{ PPC::V11, 88U },
{ PPC::V12, 89U },
{ PPC::V13, 90U },
{ PPC::V14, 91U },
{ PPC::V15, 92U },
{ PPC::V16, 93U },
{ PPC::V17, 94U },
{ PPC::V18, 95U },
{ PPC::V19, 96U },
{ PPC::V20, 97U },
{ PPC::V21, 98U },
{ PPC::V22, 99U },
{ PPC::V23, 100U },
{ PPC::V24, 101U },
{ PPC::V25, 102U },
{ PPC::V26, 103U },
{ PPC::V27, 104U },
{ PPC::V28, 105U },
{ PPC::V29, 106U },
{ PPC::V30, 107U },
{ PPC::V31, 108U },
{ PPC::VF0, 77U },
{ PPC::VF1, 78U },
{ PPC::VF2, 79U },
{ PPC::VF3, 80U },
{ PPC::VF4, 81U },
{ PPC::VF5, 82U },
{ PPC::VF6, 83U },
{ PPC::VF7, 84U },
{ PPC::VF8, 85U },
{ PPC::VF9, 86U },
{ PPC::VF10, 87U },
{ PPC::VF11, 88U },
{ PPC::VF12, 89U },
{ PPC::VF13, 90U },
{ PPC::VF14, 91U },
{ PPC::VF15, 92U },
{ PPC::VF16, 93U },
{ PPC::VF17, 94U },
{ PPC::VF18, 95U },
{ PPC::VF19, 96U },
{ PPC::VF20, 97U },
{ PPC::VF21, 98U },
{ PPC::VF22, 99U },
{ PPC::VF23, 100U },
{ PPC::VF24, 101U },
{ PPC::VF25, 102U },
{ PPC::VF26, 103U },
{ PPC::VF27, 104U },
{ PPC::VF28, 105U },
{ PPC::VF29, 106U },
{ PPC::VF30, 107U },
{ PPC::VF31, 108U },
{ PPC::VSL0, 32U },
{ PPC::VSL1, 33U },
{ PPC::VSL2, 34U },
{ PPC::VSL3, 35U },
{ PPC::VSL4, 36U },
{ PPC::VSL5, 37U },
{ PPC::VSL6, 38U },
{ PPC::VSL7, 39U },
{ PPC::VSL8, 40U },
{ PPC::VSL9, 41U },
{ PPC::VSL10, 42U },
{ PPC::VSL11, 43U },
{ PPC::VSL12, 44U },
{ PPC::VSL13, 45U },
{ PPC::VSL14, 46U },
{ PPC::VSL15, 47U },
{ PPC::VSL16, 48U },
{ PPC::VSL17, 49U },
{ PPC::VSL18, 50U },
{ PPC::VSL19, 51U },
{ PPC::VSL20, 52U },
{ PPC::VSL21, 53U },
{ PPC::VSL22, 54U },
{ PPC::VSL23, 55U },
{ PPC::VSL24, 56U },
{ PPC::VSL25, 57U },
{ PPC::VSL26, 58U },
{ PPC::VSL27, 59U },
{ PPC::VSL28, 60U },
{ PPC::VSL29, 61U },
{ PPC::VSL30, 62U },
{ PPC::VSL31, 63U },
{ PPC::X0, -2U },
{ PPC::X1, -2U },
{ PPC::X2, -2U },
{ PPC::X3, -2U },
{ PPC::X4, -2U },
{ PPC::X5, -2U },
{ PPC::X6, -2U },
{ PPC::X7, -2U },
{ PPC::X8, -2U },
{ PPC::X9, -2U },
{ PPC::X10, -2U },
{ PPC::X11, -2U },
{ PPC::X12, -2U },
{ PPC::X13, -2U },
{ PPC::X14, -2U },
{ PPC::X15, -2U },
{ PPC::X16, -2U },
{ PPC::X17, -2U },
{ PPC::X18, -2U },
{ PPC::X19, -2U },
{ PPC::X20, -2U },
{ PPC::X21, -2U },
{ PPC::X22, -2U },
{ PPC::X23, -2U },
{ PPC::X24, -2U },
{ PPC::X25, -2U },
{ PPC::X26, -2U },
{ PPC::X27, -2U },
{ PPC::X28, -2U },
{ PPC::X29, -2U },
{ PPC::X30, -2U },
{ PPC::X31, -2U },
{ PPC::ZERO8, -2U },
};
extern const unsigned PPCEHFlavour1L2DwarfSize = std::size(PPCEHFlavour1L2Dwarf);
extern const uint16_t PPCRegEncodingTable[] = {
0,
0,
1,
9,
0,
8,
0,
512,
256,
1,
0,
0,
1,
2,
3,
4,
5,
6,
7,
0,
0,
1,
2,
3,
4,
5,
6,
7,
9,
0,
1,
2,
3,
4,
5,
6,
7,
0,
1,
2,
3,
4,
5,
6,
7,
8,
9,
10,
11,
12,
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29,
30,
31,
32,
33,
34,
35,
36,
37,
38,
39,
40,
41,
42,
43,
44,
45,
46,
47,
48,
49,
50,
51,
52,
53,
54,
55,
56,
57,
58,
59,
60,
61,
62,
63,
0,
1,
2,
3,
4,
5,
6,
7,
8,
9,
10,
11,
12,
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29,
30,
31,
0,
1,
2,
3,
0,
1,
2,
3,
4,
5,
6,
7,
8,
9,
10,
11,
12,
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29,
30,
31,
0,
8,
0,
1,
2,
3,
4,
5,
6,
7,
8,
9,
10,
11,
12,
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29,
30,
31,
0,
1,
2,
3,
4,
5,
6,
7,
8,
9,
10,
11,
12,
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29,
30,
31,
0,
1,
2,
3,
4,
5,
6,
7,
0,
1,
2,
3,
4,
5,
6,
7,
8,
9,
10,
11,
12,
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29,
30,
31,
32,
33,
34,
35,
36,
37,
38,
39,
40,
41,
42,
43,
44,
45,
46,
47,
48,
49,
50,
51,
52,
53,
54,
55,
56,
57,
58,
59,
60,
61,
62,
63,
0,
1,
2,
3,
4,
5,
6,
7,
8,
9,
10,
11,
12,
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29,
30,
31,
0,
1,
2,
3,
4,
5,
6,
7,
8,
9,
10,
11,
12,
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29,
30,
31,
32,
33,
34,
35,
36,
37,
38,
39,
40,
41,
42,
43,
44,
45,
46,
47,
48,
49,
50,
51,
52,
53,
54,
55,
56,
57,
58,
59,
60,
61,
62,
63,
0,
1,
2,
3,
4,
5,
6,
7,
0,
1,
2,
3,
4,
5,
6,
7,
0,
1,
2,
3,
4,
5,
6,
7,
8,
9,
10,
11,
12,
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29,
30,
31,
0,
2,
6,
10,
14,
18,
22,
26,
30,
1,
5,
9,
13,
17,
21,
25,
29,
0,
4,
8,
12,
16,
20,
24,
28,
3,
7,
11,
15,
19,
23,
27,
31,
0,
2,
4,
6,
8,
10,
12,
14,
16,
18,
20,
22,
24,
26,
28,
30,
};
static inline void InitPPCMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
RI->InitMCRegisterInfo(PPCRegDesc, 500, RA, PC, PPCMCRegisterClasses, 51, PPCRegUnitRoots, 235, PPCRegDiffLists, PPCLaneMaskLists, PPCRegStrings, PPCRegClassStrings, PPCSubRegIdxLists, 49,
PPCSubRegIdxRanges, PPCRegEncodingTable);
switch (DwarfFlavour) {
default:
llvm_unreachable("Unknown DWARF flavour");
case 0:
RI->mapDwarfRegsToLLVMRegs(PPCDwarfFlavour0Dwarf2L, PPCDwarfFlavour0Dwarf2LSize, false);
break;
case 1:
RI->mapDwarfRegsToLLVMRegs(PPCDwarfFlavour1Dwarf2L, PPCDwarfFlavour1Dwarf2LSize, false);
break;
}
switch (EHFlavour) {
default:
llvm_unreachable("Unknown DWARF flavour");
case 0:
RI->mapDwarfRegsToLLVMRegs(PPCEHFlavour0Dwarf2L, PPCEHFlavour0Dwarf2LSize, true);
break;
case 1:
RI->mapDwarfRegsToLLVMRegs(PPCEHFlavour1Dwarf2L, PPCEHFlavour1Dwarf2LSize, true);
break;
}
switch (DwarfFlavour) {
default:
llvm_unreachable("Unknown DWARF flavour");
case 0:
RI->mapLLVMRegsToDwarfRegs(PPCDwarfFlavour0L2Dwarf, PPCDwarfFlavour0L2DwarfSize, false);
break;
case 1:
RI->mapLLVMRegsToDwarfRegs(PPCDwarfFlavour1L2Dwarf, PPCDwarfFlavour1L2DwarfSize, false);
break;
}
switch (EHFlavour) {
default:
llvm_unreachable("Unknown DWARF flavour");
case 0:
RI->mapLLVMRegsToDwarfRegs(PPCEHFlavour0L2Dwarf, PPCEHFlavour0L2DwarfSize, true);
break;
case 1:
RI->mapLLVMRegsToDwarfRegs(PPCEHFlavour1L2Dwarf, PPCEHFlavour1L2DwarfSize, true);
break;
}
}
} // end namespace llvm
#endif // GET_REGINFO_MC_DESC
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|* *|
|* Register Information Header Fragment *|
|* *|
|* Automatically generated file, do not edit! *|
|* *|
\*===----------------------------------------------------------------------===*/
#ifdef GET_REGINFO_HEADER
#undef GET_REGINFO_HEADER
#include "llvm/CodeGen/TargetRegisterInfo.h"
namespace llvm {
class PPCFrameLowering;
struct PPCGenRegisterInfo : public TargetRegisterInfo {
explicit PPCGenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0,
unsigned PC = 0, unsigned HwMode = 0);
unsigned composeSubRegIndicesImpl(unsigned, unsigned) const override;
LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass *, unsigned) const override;
const TargetRegisterClass *getSubRegisterClass(const TargetRegisterClass *, unsigned) const override;
const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
unsigned getRegUnitWeight(unsigned RegUnit) const override;
unsigned getNumRegPressureSets() const override;
const char *getRegPressureSetName(unsigned Idx) const override;
unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override;
const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
const int *getRegUnitPressureSets(unsigned RegUnit) const override;
ArrayRef<const char *> getRegMaskNames() const override;
ArrayRef<const uint32_t *> getRegMasks() const override;
bool isGeneralPurposeRegister(const MachineFunction &, MCRegister) const override;
bool isFixedRegister(const MachineFunction &, MCRegister) const override;
bool isArgumentRegister(const MachineFunction &, MCRegister) const override;
bool isConstantPhysReg(MCRegister PhysReg) const override final;
/// Devirtualized TargetFrameLowering.
static const PPCFrameLowering *getFrameLowering(
const MachineFunction &MF);
};
namespace PPC { // Register classes
extern const TargetRegisterClass VSSRCRegClass;
extern const TargetRegisterClass GPRCRegClass;
extern const TargetRegisterClass GPRC_NOR0RegClass;
extern const TargetRegisterClass GPRC_and_GPRC_NOR0RegClass;
extern const TargetRegisterClass CRBITRCRegClass;
extern const TargetRegisterClass F4RCRegClass;
extern const TargetRegisterClass CRRCRegClass;
extern const TargetRegisterClass CARRYRCRegClass;
extern const TargetRegisterClass CTRRCRegClass;
extern const TargetRegisterClass LRRCRegClass;
extern const TargetRegisterClass VRSAVERCRegClass;
extern const TargetRegisterClass SPILLTOVSRRCRegClass;
extern const TargetRegisterClass VSFRCRegClass;
extern const TargetRegisterClass G8RCRegClass;
extern const TargetRegisterClass G8RC_NOX0RegClass;
extern const TargetRegisterClass SPILLTOVSRRC_and_VSFRCRegClass;
extern const TargetRegisterClass G8RC_and_G8RC_NOX0RegClass;
extern const TargetRegisterClass F8RCRegClass;
extern const TargetRegisterClass SPERCRegClass;
extern const TargetRegisterClass VFRCRegClass;
extern const TargetRegisterClass SPERC_with_sub_32_in_GPRC_NOR0RegClass;
extern const TargetRegisterClass SPILLTOVSRRC_and_VFRCRegClass;
extern const TargetRegisterClass SPILLTOVSRRC_and_F4RCRegClass;
extern const TargetRegisterClass CTRRC8RegClass;
extern const TargetRegisterClass LR8RCRegClass;
extern const TargetRegisterClass DMRROWRCRegClass;
extern const TargetRegisterClass VSRCRegClass;
extern const TargetRegisterClass VSRC_with_sub_64_in_SPILLTOVSRRCRegClass;
extern const TargetRegisterClass VRRCRegClass;
extern const TargetRegisterClass VSLRCRegClass;
extern const TargetRegisterClass VRRC_with_sub_64_in_SPILLTOVSRRCRegClass;
extern const TargetRegisterClass G8pRCRegClass;
extern const TargetRegisterClass G8pRC_with_sub_32_in_GPRC_NOR0RegClass;
extern const TargetRegisterClass VSLRC_with_sub_64_in_SPILLTOVSRRCRegClass;
extern const TargetRegisterClass DMRROWpRCRegClass;
extern const TargetRegisterClass VSRpRCRegClass;
extern const TargetRegisterClass VSRpRC_with_sub_64_in_SPILLTOVSRRCRegClass;
extern const TargetRegisterClass VSRpRC_with_sub_64_in_F4RCRegClass;
extern const TargetRegisterClass VSRpRC_with_sub_64_in_VFRCRegClass;
extern const TargetRegisterClass VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRCRegClass;
extern const TargetRegisterClass VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RCRegClass;
extern const TargetRegisterClass ACCRCRegClass;
extern const TargetRegisterClass UACCRCRegClass;
extern const TargetRegisterClass WACCRCRegClass;
extern const TargetRegisterClass WACC_HIRCRegClass;
extern const TargetRegisterClass ACCRC_with_sub_64_in_SPILLTOVSRRCRegClass;
extern const TargetRegisterClass UACCRC_with_sub_64_in_SPILLTOVSRRCRegClass;
extern const TargetRegisterClass ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCRegClass;
extern const TargetRegisterClass UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCRegClass;
extern const TargetRegisterClass DMRRCRegClass;
extern const TargetRegisterClass DMRpRCRegClass;
} // end namespace PPC
} // end namespace llvm
#endif // GET_REGINFO_HEADER
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|* *|
|* Target Register and Register Classes Information *|
|* *|
|* Automatically generated file, do not edit! *|
|* *|
\*===----------------------------------------------------------------------===*/
#ifdef GET_REGINFO_TARGET_DESC
#undef GET_REGINFO_TARGET_DESC
namespace llvm {
extern const MCRegisterClass PPCMCRegisterClasses[];
static const MVT::SimpleValueType VTLists[] = {
/* 0 */ MVT::i1, MVT::Other,
/* 2 */ MVT::i32, MVT::Other,
/* 4 */ MVT::i64, MVT::Other,
/* 6 */ MVT::i128, MVT::Other,
/* 8 */ MVT::i32, MVT::f32, MVT::Other,
/* 11 */ MVT::i64, MVT::f64, MVT::Other,
/* 14 */ MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64, MVT::v1i128, MVT::v4f32, MVT::v2f64, MVT::f128, MVT::Other,
/* 23 */ MVT::v128i1, MVT::Other,
/* 25 */ MVT::v256i1, MVT::Other,
/* 27 */ MVT::v512i1, MVT::Other,
/* 29 */ MVT::v1024i1, MVT::Other,
/* 31 */ MVT::v2048i1, MVT::Other,
/* 33 */ MVT::v4i32, MVT::v4f32, MVT::v2f64, MVT::v2i64, MVT::Other,
};
static const char *SubRegIndexNameTable[] = { "sub_32", "sub_64", "sub_dmr0", "sub_dmr1", "sub_dmrrow0", "sub_dmrrow1", "sub_dmrrowp0", "sub_dmrrowp1", "sub_eq", "sub_gp8_x0", "sub_gp8_x1", "sub_gt", "sub_lt", "sub_pair0", "sub_pair1", "sub_un", "sub_vsx0", "sub_vsx1", "sub_wacc_hi", "sub_wacc_lo", "sub_vsx1_then_sub_64", "sub_pair1_then_sub_64", "sub_pair1_then_sub_vsx0", "sub_pair1_then_sub_vsx1", "sub_pair1_then_sub_vsx1_then_sub_64", "sub_dmrrowp1_then_sub_dmrrow0", "sub_dmrrowp1_then_sub_dmrrow1", "sub_wacc_hi_then_sub_dmrrow0", "sub_wacc_hi_then_sub_dmrrow1", "sub_wacc_hi_then_sub_dmrrowp0", "sub_wacc_hi_then_sub_dmrrowp1", "sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0", "sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1", "sub_dmr1_then_sub_dmrrow0", "sub_dmr1_then_sub_dmrrow1", "sub_dmr1_then_sub_dmrrowp0", "sub_dmr1_then_sub_dmrrowp1", "sub_dmr1_then_sub_wacc_hi", "sub_dmr1_then_sub_wacc_lo", "sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0", "sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1", "sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0", "sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1", "sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0", "sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1", "sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0", "sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1", "sub_gp8_x1_then_sub_32", "" };
static const LaneBitmask SubRegIndexLaneMaskTable[] = {
LaneBitmask::getAll(),
LaneBitmask(0x0000000000000001), // sub_32
LaneBitmask(0x0000000000000002), // sub_64
LaneBitmask(0x000000000001F80C), // sub_dmr0
LaneBitmask(0x0000000001FE0000), // sub_dmr1
LaneBitmask(0x0000000000000004), // sub_dmrrow0
LaneBitmask(0x0000000000000008), // sub_dmrrow1
LaneBitmask(0x000000000000000C), // sub_dmrrowp0
LaneBitmask(0x0000000000001800), // sub_dmrrowp1
LaneBitmask(0x0000000000000010), // sub_eq
LaneBitmask(0x0000000000000001), // sub_gp8_x0
LaneBitmask(0x0000000002000000), // sub_gp8_x1
LaneBitmask(0x0000000000000020), // sub_gt
LaneBitmask(0x0000000000000040), // sub_lt
LaneBitmask(0x0000000000000102), // sub_pair0
LaneBitmask(0x0000000000000600), // sub_pair1
LaneBitmask(0x0000000000000080), // sub_un
LaneBitmask(0x0000000000000002), // sub_vsx0
LaneBitmask(0x0000000000000100), // sub_vsx1
LaneBitmask(0x000000000001E000), // sub_wacc_hi
LaneBitmask(0x000000000000180C), // sub_wacc_lo
LaneBitmask(0x0000000000000100), // sub_vsx1_then_sub_64
LaneBitmask(0x0000000000000200), // sub_pair1_then_sub_64
LaneBitmask(0x0000000000000200), // sub_pair1_then_sub_vsx0
LaneBitmask(0x0000000000000400), // sub_pair1_then_sub_vsx1
LaneBitmask(0x0000000000000400), // sub_pair1_then_sub_vsx1_then_sub_64
LaneBitmask(0x0000000000000800), // sub_dmrrowp1_then_sub_dmrrow0
LaneBitmask(0x0000000000001000), // sub_dmrrowp1_then_sub_dmrrow1
LaneBitmask(0x0000000000002000), // sub_wacc_hi_then_sub_dmrrow0
LaneBitmask(0x0000000000004000), // sub_wacc_hi_then_sub_dmrrow1
LaneBitmask(0x0000000000006000), // sub_wacc_hi_then_sub_dmrrowp0
LaneBitmask(0x0000000000018000), // sub_wacc_hi_then_sub_dmrrowp1
LaneBitmask(0x0000000000008000), // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
LaneBitmask(0x0000000000010000), // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
LaneBitmask(0x0000000000020000), // sub_dmr1_then_sub_dmrrow0
LaneBitmask(0x0000000000040000), // sub_dmr1_then_sub_dmrrow1
LaneBitmask(0x0000000000060000), // sub_dmr1_then_sub_dmrrowp0
LaneBitmask(0x0000000000180000), // sub_dmr1_then_sub_dmrrowp1
LaneBitmask(0x0000000001E00000), // sub_dmr1_then_sub_wacc_hi
LaneBitmask(0x00000000001E0000), // sub_dmr1_then_sub_wacc_lo
LaneBitmask(0x0000000000080000), // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
LaneBitmask(0x0000000000100000), // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
LaneBitmask(0x0000000000200000), // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
LaneBitmask(0x0000000000400000), // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
LaneBitmask(0x0000000000600000), // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
LaneBitmask(0x0000000001800000), // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
LaneBitmask(0x0000000000800000), // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
LaneBitmask(0x0000000001000000), // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
LaneBitmask(0x0000000002000000), // sub_gp8_x1_then_sub_32
};
static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
// Mode = 0 (Default)
{ 32, 32, 32, VTLists+9 }, // VSSRC
{ 32, 32, 32, VTLists+8 }, // GPRC
{ 32, 32, 32, VTLists+8 }, // GPRC_NOR0
{ 32, 32, 32, VTLists+8 }, // GPRC_and_GPRC_NOR0
{ 32, 32, 32, VTLists+0 }, // CRBITRC
{ 32, 32, 32, VTLists+9 }, // F4RC
{ 32, 32, 32, VTLists+2 }, // CRRC
{ 32, 32, 32, VTLists+2 }, // CARRYRC
{ 32, 32, 32, VTLists+2 }, // CTRRC
{ 32, 32, 32, VTLists+2 }, // LRRC
{ 32, 32, 32, VTLists+2 }, // VRSAVERC
{ 64, 64, 64, VTLists+11 }, // SPILLTOVSRRC
{ 64, 64, 64, VTLists+12 }, // VSFRC
{ 64, 64, 64, VTLists+4 }, // G8RC
{ 64, 64, 64, VTLists+4 }, // G8RC_NOX0
{ 64, 64, 64, VTLists+12 }, // SPILLTOVSRRC_and_VSFRC
{ 64, 64, 64, VTLists+4 }, // G8RC_and_G8RC_NOX0
{ 64, 64, 64, VTLists+12 }, // F8RC
{ 64, 64, 64, VTLists+12 }, // SPERC
{ 64, 64, 64, VTLists+12 }, // VFRC
{ 64, 64, 64, VTLists+12 }, // SPERC_with_sub_32_in_GPRC_NOR0
{ 64, 64, 64, VTLists+12 }, // SPILLTOVSRRC_and_VFRC
{ 64, 64, 64, VTLists+12 }, // SPILLTOVSRRC_and_F4RC
{ 64, 64, 64, VTLists+4 }, // CTRRC8
{ 64, 64, 64, VTLists+4 }, // LR8RC
{ 128, 128, 128, VTLists+23 }, // DMRROWRC
{ 128, 128, 128, VTLists+33 }, // VSRC
{ 128, 128, 128, VTLists+33 }, // VSRC_with_sub_64_in_SPILLTOVSRRC
{ 128, 128, 128, VTLists+14 }, // VRRC
{ 128, 128, 128, VTLists+33 }, // VSLRC
{ 128, 128, 128, VTLists+14 }, // VRRC_with_sub_64_in_SPILLTOVSRRC
{ 128, 128, 128, VTLists+6 }, // G8pRC
{ 128, 128, 128, VTLists+6 }, // G8pRC_with_sub_32_in_GPRC_NOR0
{ 128, 128, 128, VTLists+33 }, // VSLRC_with_sub_64_in_SPILLTOVSRRC
{ 256, 256, 128, VTLists+25 }, // DMRROWpRC
{ 256, 256, 128, VTLists+25 }, // VSRpRC
{ 256, 256, 128, VTLists+25 }, // VSRpRC_with_sub_64_in_SPILLTOVSRRC
{ 256, 256, 128, VTLists+25 }, // VSRpRC_with_sub_64_in_F4RC
{ 256, 256, 128, VTLists+25 }, // VSRpRC_with_sub_64_in_VFRC
{ 256, 256, 128, VTLists+25 }, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC
{ 256, 256, 128, VTLists+25 }, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC
{ 512, 512, 128, VTLists+27 }, // ACCRC
{ 512, 512, 128, VTLists+27 }, // UACCRC
{ 512, 512, 128, VTLists+27 }, // WACCRC
{ 512, 512, 128, VTLists+27 }, // WACC_HIRC
{ 512, 512, 128, VTLists+27 }, // ACCRC_with_sub_64_in_SPILLTOVSRRC
{ 512, 512, 128, VTLists+27 }, // UACCRC_with_sub_64_in_SPILLTOVSRRC
{ 512, 512, 128, VTLists+27 }, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
{ 512, 512, 128, VTLists+27 }, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
{ 1024, 1024, 128, VTLists+29 }, // DMRRC
{ 2048, 2048, 128, VTLists+31 }, // DMRpRC
};
static const TargetRegisterClass *const NullRegClasses[] = { nullptr };
static const uint32_t VSSRCSubClassMask[] = {
0x006a9021, 0x00000000,
0x7c000000, 0x0001e7fa, // sub_64
0x00000000, 0x0001e7f8, // sub_vsx1_then_sub_64
0x00000000, 0x0001e600, // sub_pair1_then_sub_64
0x00000000, 0x0001e600, // sub_pair1_then_sub_vsx1_then_sub_64
};
static const uint32_t GPRCSubClassMask[] = {
0x0000000a, 0x00000000,
0x80152000, 0x00000001, // sub_32
0x80000000, 0x00000001, // sub_gp8_x1_then_sub_32
};
static const uint32_t GPRC_NOR0SubClassMask[] = {
0x0000000c, 0x00000000,
0x00114000, 0x00000001, // sub_32
0x80000000, 0x00000001, // sub_gp8_x1_then_sub_32
};
static const uint32_t GPRC_and_GPRC_NOR0SubClassMask[] = {
0x00000008, 0x00000000,
0x00110000, 0x00000001, // sub_32
0x80000000, 0x00000001, // sub_gp8_x1_then_sub_32
};
static const uint32_t CRBITRCSubClassMask[] = {
0x00000010, 0x00000000,
0x00000040, 0x00000000, // sub_eq
0x00000040, 0x00000000, // sub_gt
0x00000040, 0x00000000, // sub_lt
0x00000040, 0x00000000, // sub_un
};
static const uint32_t F4RCSubClassMask[] = {
0x00420020, 0x00000000,
0x20000000, 0x0001e722, // sub_64
0x00000000, 0x0001e720, // sub_vsx1_then_sub_64
0x00000000, 0x0001e600, // sub_pair1_then_sub_64
0x00000000, 0x0001e600, // sub_pair1_then_sub_vsx1_then_sub_64
};
static const uint32_t CRRCSubClassMask[] = {
0x00000040, 0x00000000,
};
static const uint32_t CARRYRCSubClassMask[] = {
0x00000080, 0x00000000,
};
static const uint32_t CTRRCSubClassMask[] = {
0x00000100, 0x00000000,
};
static const uint32_t LRRCSubClassMask[] = {
0x00000200, 0x00000000,
};
static const uint32_t VRSAVERCSubClassMask[] = {
0x00000400, 0x00000000,
};
static const uint32_t SPILLTOVSRRCSubClassMask[] = {
0x0061a800, 0x00000000,
0x48000000, 0x0001e192, // sub_64
0x80000000, 0x00000001, // sub_gp8_x0
0x80000000, 0x00000001, // sub_gp8_x1
0x00000000, 0x0001e190, // sub_vsx1_then_sub_64
0x00000000, 0x00018000, // sub_pair1_then_sub_64
0x00000000, 0x00018000, // sub_pair1_then_sub_vsx1_then_sub_64
};
static const uint32_t VSFRCSubClassMask[] = {
0x006a9000, 0x00000000,
0x7c000000, 0x0001e7fa, // sub_64
0x00000000, 0x0001e7f8, // sub_vsx1_then_sub_64
0x00000000, 0x0001e600, // sub_pair1_then_sub_64
0x00000000, 0x0001e600, // sub_pair1_then_sub_vsx1_then_sub_64
};
static const uint32_t G8RCSubClassMask[] = {
0x00012000, 0x00000000,
0x80000000, 0x00000001, // sub_gp8_x0
0x80000000, 0x00000001, // sub_gp8_x1
};
static const uint32_t G8RC_NOX0SubClassMask[] = {
0x00014000, 0x00000000,
0x00000000, 0x00000001, // sub_gp8_x0
0x80000000, 0x00000001, // sub_gp8_x1
};
static const uint32_t SPILLTOVSRRC_and_VSFRCSubClassMask[] = {
0x00608000, 0x00000000,
0x48000000, 0x0001e192, // sub_64
0x00000000, 0x0001e190, // sub_vsx1_then_sub_64
0x00000000, 0x00018000, // sub_pair1_then_sub_64
0x00000000, 0x00018000, // sub_pair1_then_sub_vsx1_then_sub_64
};
static const uint32_t G8RC_and_G8RC_NOX0SubClassMask[] = {
0x00010000, 0x00000000,
0x00000000, 0x00000001, // sub_gp8_x0
0x80000000, 0x00000001, // sub_gp8_x1
};
static const uint32_t F8RCSubClassMask[] = {
0x00420000, 0x00000000,
0x20000000, 0x0001e722, // sub_64
0x00000000, 0x0001e720, // sub_vsx1_then_sub_64
0x00000000, 0x0001e600, // sub_pair1_then_sub_64
0x00000000, 0x0001e600, // sub_pair1_then_sub_vsx1_then_sub_64
};
static const uint32_t SPERCSubClassMask[] = {
0x00140000, 0x00000000,
};
static const uint32_t VFRCSubClassMask[] = {
0x00280000, 0x00000000,
0x50000000, 0x000000c0, // sub_64
0x00000000, 0x000000c0, // sub_vsx1_then_sub_64
};
static const uint32_t SPERC_with_sub_32_in_GPRC_NOR0SubClassMask[] = {
0x00100000, 0x00000000,
};
static const uint32_t SPILLTOVSRRC_and_VFRCSubClassMask[] = {
0x00200000, 0x00000000,
0x40000000, 0x00000080, // sub_64
0x00000000, 0x00000080, // sub_vsx1_then_sub_64
};
static const uint32_t SPILLTOVSRRC_and_F4RCSubClassMask[] = {
0x00400000, 0x00000000,
0x00000000, 0x0001e102, // sub_64
0x00000000, 0x0001e100, // sub_vsx1_then_sub_64
0x00000000, 0x00018000, // sub_pair1_then_sub_64
0x00000000, 0x00018000, // sub_pair1_then_sub_vsx1_then_sub_64
};
static const uint32_t CTRRC8SubClassMask[] = {
0x00800000, 0x00000000,
};
static const uint32_t LR8RCSubClassMask[] = {
0x01000000, 0x00000000,
};
static const uint32_t DMRROWRCSubClassMask[] = {
0x02000000, 0x00000000,
0x00000000, 0x00061804, // sub_dmrrow0
0x00000000, 0x00061804, // sub_dmrrow1
0x00000000, 0x00061800, // sub_dmrrowp1_then_sub_dmrrow0
0x00000000, 0x00061800, // sub_dmrrowp1_then_sub_dmrrow1
0x00000000, 0x00060000, // sub_wacc_hi_then_sub_dmrrow0
0x00000000, 0x00060000, // sub_wacc_hi_then_sub_dmrrow1
0x00000000, 0x00060000, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0x00000000, 0x00060000, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0x00000000, 0x00040000, // sub_dmr1_then_sub_dmrrow0
0x00000000, 0x00040000, // sub_dmr1_then_sub_dmrrow1
0x00000000, 0x00040000, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
0x00000000, 0x00040000, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
0x00000000, 0x00040000, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
0x00000000, 0x00040000, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
0x00000000, 0x00040000, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0x00000000, 0x00040000, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
};
static const uint32_t VSRCSubClassMask[] = {
0x7c000000, 0x00000002,
0x00000000, 0x0001e7f8, // sub_vsx0
0x00000000, 0x0001e7f8, // sub_vsx1
0x00000000, 0x0001e600, // sub_pair1_then_sub_vsx0
0x00000000, 0x0001e600, // sub_pair1_then_sub_vsx1
};
static const uint32_t VSRC_with_sub_64_in_SPILLTOVSRRCSubClassMask[] = {
0x48000000, 0x00000002,
0x00000000, 0x0001e190, // sub_vsx0
0x00000000, 0x0001e190, // sub_vsx1
0x00000000, 0x00018000, // sub_pair1_then_sub_vsx0
0x00000000, 0x00018000, // sub_pair1_then_sub_vsx1
};
static const uint32_t VRRCSubClassMask[] = {
0x50000000, 0x00000000,
0x00000000, 0x000000c0, // sub_vsx0
0x00000000, 0x000000c0, // sub_vsx1
};
static const uint32_t VSLRCSubClassMask[] = {
0x20000000, 0x00000002,
0x00000000, 0x0001e720, // sub_vsx0
0x00000000, 0x0001e720, // sub_vsx1
0x00000000, 0x0001e600, // sub_pair1_then_sub_vsx0
0x00000000, 0x0001e600, // sub_pair1_then_sub_vsx1
};
static const uint32_t VRRC_with_sub_64_in_SPILLTOVSRRCSubClassMask[] = {
0x40000000, 0x00000000,
0x00000000, 0x00000080, // sub_vsx0
0x00000000, 0x00000080, // sub_vsx1
};
static const uint32_t G8pRCSubClassMask[] = {
0x80000000, 0x00000001,
};
static const uint32_t G8pRC_with_sub_32_in_GPRC_NOR0SubClassMask[] = {
0x00000000, 0x00000001,
};
static const uint32_t VSLRC_with_sub_64_in_SPILLTOVSRRCSubClassMask[] = {
0x00000000, 0x00000002,
0x00000000, 0x0001e100, // sub_vsx0
0x00000000, 0x0001e100, // sub_vsx1
0x00000000, 0x00018000, // sub_pair1_then_sub_vsx0
0x00000000, 0x00018000, // sub_pair1_then_sub_vsx1
};
static const uint32_t DMRROWpRCSubClassMask[] = {
0x00000000, 0x00000004,
0x00000000, 0x00061800, // sub_dmrrowp0
0x00000000, 0x00061800, // sub_dmrrowp1
0x00000000, 0x00060000, // sub_wacc_hi_then_sub_dmrrowp0
0x00000000, 0x00060000, // sub_wacc_hi_then_sub_dmrrowp1
0x00000000, 0x00040000, // sub_dmr1_then_sub_dmrrowp0
0x00000000, 0x00040000, // sub_dmr1_then_sub_dmrrowp1
0x00000000, 0x00040000, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
0x00000000, 0x00040000, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
};
static const uint32_t VSRpRCSubClassMask[] = {
0x00000000, 0x000001f8,
0x00000000, 0x0001e600, // sub_pair0
0x00000000, 0x0001e600, // sub_pair1
};
static const uint32_t VSRpRC_with_sub_64_in_SPILLTOVSRRCSubClassMask[] = {
0x00000000, 0x00000190,
0x00000000, 0x0001e000, // sub_pair0
0x00000000, 0x00018000, // sub_pair1
};
static const uint32_t VSRpRC_with_sub_64_in_F4RCSubClassMask[] = {
0x00000000, 0x00000120,
0x00000000, 0x0001e600, // sub_pair0
0x00000000, 0x0001e600, // sub_pair1
};
static const uint32_t VSRpRC_with_sub_64_in_VFRCSubClassMask[] = {
0x00000000, 0x000000c0,
};
static const uint32_t VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRCSubClassMask[] = {
0x00000000, 0x00000080,
};
static const uint32_t VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RCSubClassMask[] = {
0x00000000, 0x00000100,
0x00000000, 0x0001e000, // sub_pair0
0x00000000, 0x00018000, // sub_pair1
};
static const uint32_t ACCRCSubClassMask[] = {
0x00000000, 0x0000a200,
};
static const uint32_t UACCRCSubClassMask[] = {
0x00000000, 0x00014400,
};
static const uint32_t WACCRCSubClassMask[] = {
0x00000000, 0x00000800,
0x00000000, 0x00060000, // sub_wacc_lo
0x00000000, 0x00040000, // sub_dmr1_then_sub_wacc_lo
};
static const uint32_t WACC_HIRCSubClassMask[] = {
0x00000000, 0x00001000,
0x00000000, 0x00060000, // sub_wacc_hi
0x00000000, 0x00040000, // sub_dmr1_then_sub_wacc_hi
};
static const uint32_t ACCRC_with_sub_64_in_SPILLTOVSRRCSubClassMask[] = {
0x00000000, 0x0000a000,
};
static const uint32_t UACCRC_with_sub_64_in_SPILLTOVSRRCSubClassMask[] = {
0x00000000, 0x00014000,
};
static const uint32_t ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCSubClassMask[] = {
0x00000000, 0x00008000,
};
static const uint32_t UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCSubClassMask[] = {
0x00000000, 0x00010000,
};
static const uint32_t DMRRCSubClassMask[] = {
0x00000000, 0x00020000,
0x00000000, 0x00040000, // sub_dmr0
0x00000000, 0x00040000, // sub_dmr1
};
static const uint32_t DMRpRCSubClassMask[] = {
0x00000000, 0x00040000,
};
static const uint16_t SuperRegIdxSeqs[] = {
/* 0 */ 3, 4, 0,
/* 3 */ 10, 11, 0,
/* 6 */ 14, 15, 0,
/* 9 */ 9, 12, 13, 16, 0,
/* 14 */ 17, 18, 0,
/* 17 */ 2, 21, 0,
/* 20 */ 17, 18, 23, 24, 0,
/* 25 */ 2, 21, 22, 25, 0,
/* 30 */ 2, 10, 11, 21, 22, 25, 0,
/* 37 */ 19, 38, 0,
/* 40 */ 20, 39, 0,
/* 43 */ 7, 8, 30, 31, 36, 37, 44, 45, 0,
/* 52 */ 5, 6, 26, 27, 28, 29, 32, 33, 34, 35, 40, 41, 42, 43, 46, 47, 0,
/* 69 */ 1, 48, 0,
};
static const TargetRegisterClass *const GPRC_and_GPRC_NOR0Superclasses[] = {
&PPC::GPRCRegClass,
&PPC::GPRC_NOR0RegClass,
nullptr
};
static const TargetRegisterClass *const F4RCSuperclasses[] = {
&PPC::VSSRCRegClass,
nullptr
};
static const TargetRegisterClass *const VSFRCSuperclasses[] = {
&PPC::VSSRCRegClass,
nullptr
};
static const TargetRegisterClass *const G8RCSuperclasses[] = {
&PPC::SPILLTOVSRRCRegClass,
nullptr
};
static const TargetRegisterClass *const SPILLTOVSRRC_and_VSFRCSuperclasses[] = {
&PPC::VSSRCRegClass,
&PPC::SPILLTOVSRRCRegClass,
&PPC::VSFRCRegClass,
nullptr
};
static const TargetRegisterClass *const G8RC_and_G8RC_NOX0Superclasses[] = {
&PPC::SPILLTOVSRRCRegClass,
&PPC::G8RCRegClass,
&PPC::G8RC_NOX0RegClass,
nullptr
};
static const TargetRegisterClass *const F8RCSuperclasses[] = {
&PPC::VSSRCRegClass,
&PPC::F4RCRegClass,
&PPC::VSFRCRegClass,
nullptr
};
static const TargetRegisterClass *const VFRCSuperclasses[] = {
&PPC::VSSRCRegClass,
&PPC::VSFRCRegClass,
nullptr
};
static const TargetRegisterClass *const SPERC_with_sub_32_in_GPRC_NOR0Superclasses[] = {
&PPC::SPERCRegClass,
nullptr
};
static const TargetRegisterClass *const SPILLTOVSRRC_and_VFRCSuperclasses[] = {
&PPC::VSSRCRegClass,
&PPC::SPILLTOVSRRCRegClass,
&PPC::VSFRCRegClass,
&PPC::SPILLTOVSRRC_and_VSFRCRegClass,
&PPC::VFRCRegClass,
nullptr
};
static const TargetRegisterClass *const SPILLTOVSRRC_and_F4RCSuperclasses[] = {
&PPC::VSSRCRegClass,
&PPC::F4RCRegClass,
&PPC::SPILLTOVSRRCRegClass,
&PPC::VSFRCRegClass,
&PPC::SPILLTOVSRRC_and_VSFRCRegClass,
&PPC::F8RCRegClass,
nullptr
};
static const TargetRegisterClass *const VSRC_with_sub_64_in_SPILLTOVSRRCSuperclasses[] = {
&PPC::VSRCRegClass,
nullptr
};
static const TargetRegisterClass *const VRRCSuperclasses[] = {
&PPC::VSRCRegClass,
nullptr
};
static const TargetRegisterClass *const VSLRCSuperclasses[] = {
&PPC::VSRCRegClass,
nullptr
};
static const TargetRegisterClass *const VRRC_with_sub_64_in_SPILLTOVSRRCSuperclasses[] = {
&PPC::VSRCRegClass,
&PPC::VSRC_with_sub_64_in_SPILLTOVSRRCRegClass,
&PPC::VRRCRegClass,
nullptr
};
static const TargetRegisterClass *const G8pRC_with_sub_32_in_GPRC_NOR0Superclasses[] = {
&PPC::G8pRCRegClass,
nullptr
};
static const TargetRegisterClass *const VSLRC_with_sub_64_in_SPILLTOVSRRCSuperclasses[] = {
&PPC::VSRCRegClass,
&PPC::VSRC_with_sub_64_in_SPILLTOVSRRCRegClass,
&PPC::VSLRCRegClass,
nullptr
};
static const TargetRegisterClass *const VSRpRC_with_sub_64_in_SPILLTOVSRRCSuperclasses[] = {
&PPC::VSRpRCRegClass,
nullptr
};
static const TargetRegisterClass *const VSRpRC_with_sub_64_in_F4RCSuperclasses[] = {
&PPC::VSRpRCRegClass,
nullptr
};
static const TargetRegisterClass *const VSRpRC_with_sub_64_in_VFRCSuperclasses[] = {
&PPC::VSRpRCRegClass,
nullptr
};
static const TargetRegisterClass *const VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRCSuperclasses[] = {
&PPC::VSRpRCRegClass,
&PPC::VSRpRC_with_sub_64_in_SPILLTOVSRRCRegClass,
&PPC::VSRpRC_with_sub_64_in_VFRCRegClass,
nullptr
};
static const TargetRegisterClass *const VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RCSuperclasses[] = {
&PPC::VSRpRCRegClass,
&PPC::VSRpRC_with_sub_64_in_SPILLTOVSRRCRegClass,
&PPC::VSRpRC_with_sub_64_in_F4RCRegClass,
nullptr
};
static const TargetRegisterClass *const ACCRC_with_sub_64_in_SPILLTOVSRRCSuperclasses[] = {
&PPC::ACCRCRegClass,
nullptr
};
static const TargetRegisterClass *const UACCRC_with_sub_64_in_SPILLTOVSRRCSuperclasses[] = {
&PPC::UACCRCRegClass,
nullptr
};
static const TargetRegisterClass *const ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCSuperclasses[] = {
&PPC::ACCRCRegClass,
&PPC::ACCRC_with_sub_64_in_SPILLTOVSRRCRegClass,
nullptr
};
static const TargetRegisterClass *const UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCSuperclasses[] = {
&PPC::UACCRCRegClass,
&PPC::UACCRC_with_sub_64_in_SPILLTOVSRRCRegClass,
nullptr
};
static inline unsigned GPRCAltOrderSelect(const MachineFunction &MF) {
return MF.getSubtarget<PPCSubtarget>().getGPRAllocationOrderIdx();
}
static ArrayRef<MCPhysReg> GPRCGetRawAllocationOrder(const MachineFunction &MF) {
static const MCPhysReg AltOrder1[] = { PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R11, PPC::R12, PPC::R30, PPC::R29, PPC::R28, PPC::R27, PPC::R26, PPC::R25, PPC::R24, PPC::R23, PPC::R22, PPC::R21, PPC::R20, PPC::R19, PPC::R18, PPC::R17, PPC::R16, PPC::R15, PPC::R14, PPC::R13, PPC::R31, PPC::R0, PPC::R1, PPC::FP, PPC::BP, PPC::R2 };
static const MCPhysReg AltOrder2[] = { PPC::R2, PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R11, PPC::R12, PPC::R31, PPC::R30, PPC::R29, PPC::R28, PPC::R27, PPC::R26, PPC::R25, PPC::R24, PPC::R23, PPC::R22, PPC::R21, PPC::R20, PPC::R19, PPC::R18, PPC::R17, PPC::R16, PPC::R15, PPC::R14, PPC::R13, PPC::R0, PPC::R1, PPC::FP, PPC::BP };
const MCRegisterClass &MCR = PPCMCRegisterClasses[PPC::GPRCRegClassID];
const ArrayRef<MCPhysReg> Order[] = {
ArrayRef(MCR.begin(), MCR.getNumRegs()),
ArrayRef(AltOrder1),
ArrayRef(AltOrder2)
};
const unsigned Select = GPRCAltOrderSelect(MF);
assert(Select < 3);
return Order[Select];
}
static inline unsigned GPRC_NOR0AltOrderSelect(const MachineFunction &MF) {
return MF.getSubtarget<PPCSubtarget>().getGPRAllocationOrderIdx();
}
static ArrayRef<MCPhysReg> GPRC_NOR0GetRawAllocationOrder(const MachineFunction &MF) {
static const MCPhysReg AltOrder1[] = { PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R11, PPC::R12, PPC::R30, PPC::R29, PPC::R28, PPC::R27, PPC::R26, PPC::R25, PPC::R24, PPC::R23, PPC::R22, PPC::R21, PPC::R20, PPC::R19, PPC::R18, PPC::R17, PPC::R16, PPC::R15, PPC::R14, PPC::R13, PPC::R31, PPC::R1, PPC::FP, PPC::BP, PPC::ZERO, PPC::R2 };
static const MCPhysReg AltOrder2[] = { PPC::R2, PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R11, PPC::R12, PPC::R31, PPC::R30, PPC::R29, PPC::R28, PPC::R27, PPC::R26, PPC::R25, PPC::R24, PPC::R23, PPC::R22, PPC::R21, PPC::R20, PPC::R19, PPC::R18, PPC::R17, PPC::R16, PPC::R15, PPC::R14, PPC::R13, PPC::R1, PPC::FP, PPC::BP, PPC::ZERO };
const MCRegisterClass &MCR = PPCMCRegisterClasses[PPC::GPRC_NOR0RegClassID];
const ArrayRef<MCPhysReg> Order[] = {
ArrayRef(MCR.begin(), MCR.getNumRegs()),
ArrayRef(AltOrder1),
ArrayRef(AltOrder2)
};
const unsigned Select = GPRC_NOR0AltOrderSelect(MF);
assert(Select < 3);
return Order[Select];
}
static inline unsigned GPRC_and_GPRC_NOR0AltOrderSelect(const MachineFunction &MF) {
return MF.getSubtarget<PPCSubtarget>().getGPRAllocationOrderIdx();
}
static ArrayRef<MCPhysReg> GPRC_and_GPRC_NOR0GetRawAllocationOrder(const MachineFunction &MF) {
static const MCPhysReg AltOrder1[] = { PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R11, PPC::R12, PPC::R30, PPC::R29, PPC::R28, PPC::R27, PPC::R26, PPC::R25, PPC::R24, PPC::R23, PPC::R22, PPC::R21, PPC::R20, PPC::R19, PPC::R18, PPC::R17, PPC::R16, PPC::R15, PPC::R14, PPC::R13, PPC::R31, PPC::R1, PPC::FP, PPC::BP, PPC::R2 };
static const MCPhysReg AltOrder2[] = { PPC::R2, PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R11, PPC::R12, PPC::R31, PPC::R30, PPC::R29, PPC::R28, PPC::R27, PPC::R26, PPC::R25, PPC::R24, PPC::R23, PPC::R22, PPC::R21, PPC::R20, PPC::R19, PPC::R18, PPC::R17, PPC::R16, PPC::R15, PPC::R14, PPC::R13, PPC::R1, PPC::FP, PPC::BP };
const MCRegisterClass &MCR = PPCMCRegisterClasses[PPC::GPRC_and_GPRC_NOR0RegClassID];
const ArrayRef<MCPhysReg> Order[] = {
ArrayRef(MCR.begin(), MCR.getNumRegs()),
ArrayRef(AltOrder1),
ArrayRef(AltOrder2)
};
const unsigned Select = GPRC_and_GPRC_NOR0AltOrderSelect(MF);
assert(Select < 3);
return Order[Select];
}
static inline unsigned CRBITRCAltOrderSelect(const MachineFunction &MF) {
return MF.getSubtarget<PPCSubtarget>().isELFv2ABI() &&
MF.getInfo<PPCFunctionInfo>()->isNonVolatileCRDisabled();
}
static ArrayRef<MCPhysReg> CRBITRCGetRawAllocationOrder(const MachineFunction &MF) {
static const MCPhysReg AltOrder1[] = { PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN, PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN, PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN, PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN, PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN };
const MCRegisterClass &MCR = PPCMCRegisterClasses[PPC::CRBITRCRegClassID];
const ArrayRef<MCPhysReg> Order[] = {
ArrayRef(MCR.begin(), MCR.getNumRegs()),
ArrayRef(AltOrder1)
};
const unsigned Select = CRBITRCAltOrderSelect(MF);
assert(Select < 2);
return Order[Select];
}
static inline unsigned CRRCAltOrderSelect(const MachineFunction &MF) {
return MF.getSubtarget<PPCSubtarget>().isELFv2ABI() &&
MF.getInfo<PPCFunctionInfo>()->isNonVolatileCRDisabled();
}
static ArrayRef<MCPhysReg> CRRCGetRawAllocationOrder(const MachineFunction &MF) {
static const MCPhysReg AltOrder1[] = { PPC::CR0, PPC::CR1, PPC::CR5, PPC::CR6, PPC::CR7 };
const MCRegisterClass &MCR = PPCMCRegisterClasses[PPC::CRRCRegClassID];
const ArrayRef<MCPhysReg> Order[] = {
ArrayRef(MCR.begin(), MCR.getNumRegs()),
ArrayRef(AltOrder1)
};
const unsigned Select = CRRCAltOrderSelect(MF);
assert(Select < 2);
return Order[Select];
}
static inline unsigned G8RCAltOrderSelect(const MachineFunction &MF) {
return MF.getSubtarget<PPCSubtarget>().getGPRAllocationOrderIdx();
}
static ArrayRef<MCPhysReg> G8RCGetRawAllocationOrder(const MachineFunction &MF) {
static const MCPhysReg AltOrder1[] = { PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X11, PPC::X12, PPC::X30, PPC::X29, PPC::X28, PPC::X27, PPC::X26, PPC::X25, PPC::X24, PPC::X23, PPC::X22, PPC::X21, PPC::X20, PPC::X19, PPC::X18, PPC::X17, PPC::X16, PPC::X15, PPC::X14, PPC::X31, PPC::X13, PPC::X0, PPC::X1, PPC::FP8, PPC::BP8, PPC::X2 };
static const MCPhysReg AltOrder2[] = { PPC::X2, PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X11, PPC::X12, PPC::X31, PPC::X30, PPC::X29, PPC::X28, PPC::X27, PPC::X26, PPC::X25, PPC::X24, PPC::X23, PPC::X22, PPC::X21, PPC::X20, PPC::X19, PPC::X18, PPC::X17, PPC::X16, PPC::X15, PPC::X14, PPC::X13, PPC::X0, PPC::X1, PPC::FP8, PPC::BP8 };
const MCRegisterClass &MCR = PPCMCRegisterClasses[PPC::G8RCRegClassID];
const ArrayRef<MCPhysReg> Order[] = {
ArrayRef(MCR.begin(), MCR.getNumRegs()),
ArrayRef(AltOrder1),
ArrayRef(AltOrder2)
};
const unsigned Select = G8RCAltOrderSelect(MF);
assert(Select < 3);
return Order[Select];
}
static inline unsigned G8RC_NOX0AltOrderSelect(const MachineFunction &MF) {
return MF.getSubtarget<PPCSubtarget>().getGPRAllocationOrderIdx();
}
static ArrayRef<MCPhysReg> G8RC_NOX0GetRawAllocationOrder(const MachineFunction &MF) {
static const MCPhysReg AltOrder1[] = { PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X11, PPC::X12, PPC::X30, PPC::X29, PPC::X28, PPC::X27, PPC::X26, PPC::X25, PPC::X24, PPC::X23, PPC::X22, PPC::X21, PPC::X20, PPC::X19, PPC::X18, PPC::X17, PPC::X16, PPC::X15, PPC::X14, PPC::X31, PPC::X13, PPC::X1, PPC::FP8, PPC::BP8, PPC::ZERO8, PPC::X2 };
static const MCPhysReg AltOrder2[] = { PPC::X2, PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X11, PPC::X12, PPC::X31, PPC::X30, PPC::X29, PPC::X28, PPC::X27, PPC::X26, PPC::X25, PPC::X24, PPC::X23, PPC::X22, PPC::X21, PPC::X20, PPC::X19, PPC::X18, PPC::X17, PPC::X16, PPC::X15, PPC::X14, PPC::X13, PPC::X1, PPC::FP8, PPC::BP8, PPC::ZERO8 };
const MCRegisterClass &MCR = PPCMCRegisterClasses[PPC::G8RC_NOX0RegClassID];
const ArrayRef<MCPhysReg> Order[] = {
ArrayRef(MCR.begin(), MCR.getNumRegs()),
ArrayRef(AltOrder1),
ArrayRef(AltOrder2)
};
const unsigned Select = G8RC_NOX0AltOrderSelect(MF);
assert(Select < 3);
return Order[Select];
}
static inline unsigned G8RC_and_G8RC_NOX0AltOrderSelect(const MachineFunction &MF) {
return MF.getSubtarget<PPCSubtarget>().getGPRAllocationOrderIdx();
}
static ArrayRef<MCPhysReg> G8RC_and_G8RC_NOX0GetRawAllocationOrder(const MachineFunction &MF) {
static const MCPhysReg AltOrder1[] = { PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X11, PPC::X12, PPC::X30, PPC::X29, PPC::X28, PPC::X27, PPC::X26, PPC::X25, PPC::X24, PPC::X23, PPC::X22, PPC::X21, PPC::X20, PPC::X19, PPC::X18, PPC::X17, PPC::X16, PPC::X15, PPC::X14, PPC::X31, PPC::X13, PPC::X1, PPC::FP8, PPC::BP8, PPC::X2 };
static const MCPhysReg AltOrder2[] = { PPC::X2, PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X11, PPC::X12, PPC::X31, PPC::X30, PPC::X29, PPC::X28, PPC::X27, PPC::X26, PPC::X25, PPC::X24, PPC::X23, PPC::X22, PPC::X21, PPC::X20, PPC::X19, PPC::X18, PPC::X17, PPC::X16, PPC::X15, PPC::X14, PPC::X13, PPC::X1, PPC::FP8, PPC::BP8 };
const MCRegisterClass &MCR = PPCMCRegisterClasses[PPC::G8RC_and_G8RC_NOX0RegClassID];
const ArrayRef<MCPhysReg> Order[] = {
ArrayRef(MCR.begin(), MCR.getNumRegs()),
ArrayRef(AltOrder1),
ArrayRef(AltOrder2)
};
const unsigned Select = G8RC_and_G8RC_NOX0AltOrderSelect(MF);
assert(Select < 3);
return Order[Select];
}
static inline unsigned G8pRCAltOrderSelect(const MachineFunction &MF) {
return MF.getSubtarget<PPCSubtarget>().is64BitELFABI();
}
static ArrayRef<MCPhysReg> G8pRCGetRawAllocationOrder(const MachineFunction &MF) {
static const MCPhysReg AltOrder1[] = { PPC::G8p2, PPC::G8p3, PPC::G8p4, PPC::G8p5, PPC::G8p14, PPC::G8p13, PPC::G8p12, PPC::G8p11, PPC::G8p10, PPC::G8p9, PPC::G8p8, PPC::G8p7, PPC::G8p15, PPC::G8p6, PPC::G8p0, PPC::G8p1 };
const MCRegisterClass &MCR = PPCMCRegisterClasses[PPC::G8pRCRegClassID];
const ArrayRef<MCPhysReg> Order[] = {
ArrayRef(MCR.begin(), MCR.getNumRegs()),
ArrayRef(AltOrder1)
};
const unsigned Select = G8pRCAltOrderSelect(MF);
assert(Select < 2);
return Order[Select];
}
static inline unsigned G8pRC_with_sub_32_in_GPRC_NOR0AltOrderSelect(const MachineFunction &MF) {
return MF.getSubtarget<PPCSubtarget>().is64BitELFABI();
}
static ArrayRef<MCPhysReg> G8pRC_with_sub_32_in_GPRC_NOR0GetRawAllocationOrder(const MachineFunction &MF) {
static const MCPhysReg AltOrder1[] = { PPC::G8p2, PPC::G8p3, PPC::G8p4, PPC::G8p5, PPC::G8p14, PPC::G8p13, PPC::G8p12, PPC::G8p11, PPC::G8p10, PPC::G8p9, PPC::G8p8, PPC::G8p7, PPC::G8p15, PPC::G8p6, PPC::G8p1 };
const MCRegisterClass &MCR = PPCMCRegisterClasses[PPC::G8pRC_with_sub_32_in_GPRC_NOR0RegClassID];
const ArrayRef<MCPhysReg> Order[] = {
ArrayRef(MCR.begin(), MCR.getNumRegs()),
ArrayRef(AltOrder1)
};
const unsigned Select = G8pRC_with_sub_32_in_GPRC_NOR0AltOrderSelect(MF);
assert(Select < 2);
return Order[Select];
}
namespace PPC { // Register class instances
extern const TargetRegisterClass VSSRCRegClass = {
&PPCMCRegisterClasses[VSSRCRegClassID],
VSSRCSubClassMask,
SuperRegIdxSeqs + 25,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
NullRegClasses,
nullptr
};
extern const TargetRegisterClass GPRCRegClass = {
&PPCMCRegisterClasses[GPRCRegClassID],
GPRCSubClassMask,
SuperRegIdxSeqs + 69,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
NullRegClasses,
GPRCGetRawAllocationOrder
};
extern const TargetRegisterClass GPRC_NOR0RegClass = {
&PPCMCRegisterClasses[GPRC_NOR0RegClassID],
GPRC_NOR0SubClassMask,
SuperRegIdxSeqs + 69,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
NullRegClasses,
GPRC_NOR0GetRawAllocationOrder
};
extern const TargetRegisterClass GPRC_and_GPRC_NOR0RegClass = {
&PPCMCRegisterClasses[GPRC_and_GPRC_NOR0RegClassID],
GPRC_and_GPRC_NOR0SubClassMask,
SuperRegIdxSeqs + 69,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
GPRC_and_GPRC_NOR0Superclasses,
GPRC_and_GPRC_NOR0GetRawAllocationOrder
};
extern const TargetRegisterClass CRBITRCRegClass = {
&PPCMCRegisterClasses[CRBITRCRegClassID],
CRBITRCSubClassMask,
SuperRegIdxSeqs + 9,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
NullRegClasses,
CRBITRCGetRawAllocationOrder
};
extern const TargetRegisterClass F4RCRegClass = {
&PPCMCRegisterClasses[F4RCRegClassID],
F4RCSubClassMask,
SuperRegIdxSeqs + 25,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
F4RCSuperclasses,
nullptr
};
extern const TargetRegisterClass CRRCRegClass = {
&PPCMCRegisterClasses[CRRCRegClassID],
CRRCSubClassMask,
SuperRegIdxSeqs + 2,
LaneBitmask(0x00000000000000F0),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
NullRegClasses,
CRRCGetRawAllocationOrder
};
extern const TargetRegisterClass CARRYRCRegClass = {
&PPCMCRegisterClasses[CARRYRCRegClassID],
CARRYRCSubClassMask,
SuperRegIdxSeqs + 2,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
NullRegClasses,
nullptr
};
extern const TargetRegisterClass CTRRCRegClass = {
&PPCMCRegisterClasses[CTRRCRegClassID],
CTRRCSubClassMask,
SuperRegIdxSeqs + 2,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
NullRegClasses,
nullptr
};
extern const TargetRegisterClass LRRCRegClass = {
&PPCMCRegisterClasses[LRRCRegClassID],
LRRCSubClassMask,
SuperRegIdxSeqs + 2,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
NullRegClasses,
nullptr
};
extern const TargetRegisterClass VRSAVERCRegClass = {
&PPCMCRegisterClasses[VRSAVERCRegClassID],
VRSAVERCSubClassMask,
SuperRegIdxSeqs + 2,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
NullRegClasses,
nullptr
};
extern const TargetRegisterClass SPILLTOVSRRCRegClass = {
&PPCMCRegisterClasses[SPILLTOVSRRCRegClassID],
SPILLTOVSRRCSubClassMask,
SuperRegIdxSeqs + 30,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
NullRegClasses,
nullptr
};
extern const TargetRegisterClass VSFRCRegClass = {
&PPCMCRegisterClasses[VSFRCRegClassID],
VSFRCSubClassMask,
SuperRegIdxSeqs + 25,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
VSFRCSuperclasses,
nullptr
};
extern const TargetRegisterClass G8RCRegClass = {
&PPCMCRegisterClasses[G8RCRegClassID],
G8RCSubClassMask,
SuperRegIdxSeqs + 3,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
G8RCSuperclasses,
G8RCGetRawAllocationOrder
};
extern const TargetRegisterClass G8RC_NOX0RegClass = {
&PPCMCRegisterClasses[G8RC_NOX0RegClassID],
G8RC_NOX0SubClassMask,
SuperRegIdxSeqs + 3,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
NullRegClasses,
G8RC_NOX0GetRawAllocationOrder
};
extern const TargetRegisterClass SPILLTOVSRRC_and_VSFRCRegClass = {
&PPCMCRegisterClasses[SPILLTOVSRRC_and_VSFRCRegClassID],
SPILLTOVSRRC_and_VSFRCSubClassMask,
SuperRegIdxSeqs + 25,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
SPILLTOVSRRC_and_VSFRCSuperclasses,
nullptr
};
extern const TargetRegisterClass G8RC_and_G8RC_NOX0RegClass = {
&PPCMCRegisterClasses[G8RC_and_G8RC_NOX0RegClassID],
G8RC_and_G8RC_NOX0SubClassMask,
SuperRegIdxSeqs + 3,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
G8RC_and_G8RC_NOX0Superclasses,
G8RC_and_G8RC_NOX0GetRawAllocationOrder
};
extern const TargetRegisterClass F8RCRegClass = {
&PPCMCRegisterClasses[F8RCRegClassID],
F8RCSubClassMask,
SuperRegIdxSeqs + 25,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
F8RCSuperclasses,
nullptr
};
extern const TargetRegisterClass SPERCRegClass = {
&PPCMCRegisterClasses[SPERCRegClassID],
SPERCSubClassMask,
SuperRegIdxSeqs + 2,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
NullRegClasses,
nullptr
};
extern const TargetRegisterClass VFRCRegClass = {
&PPCMCRegisterClasses[VFRCRegClassID],
VFRCSubClassMask,
SuperRegIdxSeqs + 17,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
VFRCSuperclasses,
nullptr
};
extern const TargetRegisterClass SPERC_with_sub_32_in_GPRC_NOR0RegClass = {
&PPCMCRegisterClasses[SPERC_with_sub_32_in_GPRC_NOR0RegClassID],
SPERC_with_sub_32_in_GPRC_NOR0SubClassMask,
SuperRegIdxSeqs + 2,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
SPERC_with_sub_32_in_GPRC_NOR0Superclasses,
nullptr
};
extern const TargetRegisterClass SPILLTOVSRRC_and_VFRCRegClass = {
&PPCMCRegisterClasses[SPILLTOVSRRC_and_VFRCRegClassID],
SPILLTOVSRRC_and_VFRCSubClassMask,
SuperRegIdxSeqs + 17,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
SPILLTOVSRRC_and_VFRCSuperclasses,
nullptr
};
extern const TargetRegisterClass SPILLTOVSRRC_and_F4RCRegClass = {
&PPCMCRegisterClasses[SPILLTOVSRRC_and_F4RCRegClassID],
SPILLTOVSRRC_and_F4RCSubClassMask,
SuperRegIdxSeqs + 25,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
SPILLTOVSRRC_and_F4RCSuperclasses,
nullptr
};
extern const TargetRegisterClass CTRRC8RegClass = {
&PPCMCRegisterClasses[CTRRC8RegClassID],
CTRRC8SubClassMask,
SuperRegIdxSeqs + 2,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
NullRegClasses,
nullptr
};
extern const TargetRegisterClass LR8RCRegClass = {
&PPCMCRegisterClasses[LR8RCRegClassID],
LR8RCSubClassMask,
SuperRegIdxSeqs + 2,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
NullRegClasses,
nullptr
};
extern const TargetRegisterClass DMRROWRCRegClass = {
&PPCMCRegisterClasses[DMRROWRCRegClassID],
DMRROWRCSubClassMask,
SuperRegIdxSeqs + 52,
LaneBitmask(0x0000000000000001),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
NullRegClasses,
nullptr
};
extern const TargetRegisterClass VSRCRegClass = {
&PPCMCRegisterClasses[VSRCRegClassID],
VSRCSubClassMask,
SuperRegIdxSeqs + 20,
LaneBitmask(0x0000000000000002),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
NullRegClasses,
nullptr
};
extern const TargetRegisterClass VSRC_with_sub_64_in_SPILLTOVSRRCRegClass = {
&PPCMCRegisterClasses[VSRC_with_sub_64_in_SPILLTOVSRRCRegClassID],
VSRC_with_sub_64_in_SPILLTOVSRRCSubClassMask,
SuperRegIdxSeqs + 20,
LaneBitmask(0x0000000000000002),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
VSRC_with_sub_64_in_SPILLTOVSRRCSuperclasses,
nullptr
};
extern const TargetRegisterClass VRRCRegClass = {
&PPCMCRegisterClasses[VRRCRegClassID],
VRRCSubClassMask,
SuperRegIdxSeqs + 14,
LaneBitmask(0x0000000000000002),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
VRRCSuperclasses,
nullptr
};
extern const TargetRegisterClass VSLRCRegClass = {
&PPCMCRegisterClasses[VSLRCRegClassID],
VSLRCSubClassMask,
SuperRegIdxSeqs + 20,
LaneBitmask(0x0000000000000002),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
VSLRCSuperclasses,
nullptr
};
extern const TargetRegisterClass VRRC_with_sub_64_in_SPILLTOVSRRCRegClass = {
&PPCMCRegisterClasses[VRRC_with_sub_64_in_SPILLTOVSRRCRegClassID],
VRRC_with_sub_64_in_SPILLTOVSRRCSubClassMask,
SuperRegIdxSeqs + 14,
LaneBitmask(0x0000000000000002),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
VRRC_with_sub_64_in_SPILLTOVSRRCSuperclasses,
nullptr
};
extern const TargetRegisterClass G8pRCRegClass = {
&PPCMCRegisterClasses[G8pRCRegClassID],
G8pRCSubClassMask,
SuperRegIdxSeqs + 2,
LaneBitmask(0x0000000002000001),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
NullRegClasses,
G8pRCGetRawAllocationOrder
};
extern const TargetRegisterClass G8pRC_with_sub_32_in_GPRC_NOR0RegClass = {
&PPCMCRegisterClasses[G8pRC_with_sub_32_in_GPRC_NOR0RegClassID],
G8pRC_with_sub_32_in_GPRC_NOR0SubClassMask,
SuperRegIdxSeqs + 2,
LaneBitmask(0x0000000002000001),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
G8pRC_with_sub_32_in_GPRC_NOR0Superclasses,
G8pRC_with_sub_32_in_GPRC_NOR0GetRawAllocationOrder
};
extern const TargetRegisterClass VSLRC_with_sub_64_in_SPILLTOVSRRCRegClass = {
&PPCMCRegisterClasses[VSLRC_with_sub_64_in_SPILLTOVSRRCRegClassID],
VSLRC_with_sub_64_in_SPILLTOVSRRCSubClassMask,
SuperRegIdxSeqs + 20,
LaneBitmask(0x0000000000000002),
0,
false,
0x00, /* TSFlags */
false, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
VSLRC_with_sub_64_in_SPILLTOVSRRCSuperclasses,
nullptr
};
extern const TargetRegisterClass DMRROWpRCRegClass = {
&PPCMCRegisterClasses[DMRROWpRCRegClassID],
DMRROWpRCSubClassMask,
SuperRegIdxSeqs + 43,
LaneBitmask(0x000000000000000C),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
NullRegClasses,
nullptr
};
extern const TargetRegisterClass VSRpRCRegClass = {
&PPCMCRegisterClasses[VSRpRCRegClassID],
VSRpRCSubClassMask,
SuperRegIdxSeqs + 6,
LaneBitmask(0x0000000000000102),
2,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
NullRegClasses,
nullptr
};
extern const TargetRegisterClass VSRpRC_with_sub_64_in_SPILLTOVSRRCRegClass = {
&PPCMCRegisterClasses[VSRpRC_with_sub_64_in_SPILLTOVSRRCRegClassID],
VSRpRC_with_sub_64_in_SPILLTOVSRRCSubClassMask,
SuperRegIdxSeqs + 6,
LaneBitmask(0x0000000000000102),
2,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
VSRpRC_with_sub_64_in_SPILLTOVSRRCSuperclasses,
nullptr
};
extern const TargetRegisterClass VSRpRC_with_sub_64_in_F4RCRegClass = {
&PPCMCRegisterClasses[VSRpRC_with_sub_64_in_F4RCRegClassID],
VSRpRC_with_sub_64_in_F4RCSubClassMask,
SuperRegIdxSeqs + 6,
LaneBitmask(0x0000000000000102),
2,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
VSRpRC_with_sub_64_in_F4RCSuperclasses,
nullptr
};
extern const TargetRegisterClass VSRpRC_with_sub_64_in_VFRCRegClass = {
&PPCMCRegisterClasses[VSRpRC_with_sub_64_in_VFRCRegClassID],
VSRpRC_with_sub_64_in_VFRCSubClassMask,
SuperRegIdxSeqs + 2,
LaneBitmask(0x0000000000000102),
2,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
VSRpRC_with_sub_64_in_VFRCSuperclasses,
nullptr
};
extern const TargetRegisterClass VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRCRegClass = {
&PPCMCRegisterClasses[VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRCRegClassID],
VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRCSubClassMask,
SuperRegIdxSeqs + 2,
LaneBitmask(0x0000000000000102),
2,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRCSuperclasses,
nullptr
};
extern const TargetRegisterClass VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RCRegClass = {
&PPCMCRegisterClasses[VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RCRegClassID],
VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RCSubClassMask,
SuperRegIdxSeqs + 6,
LaneBitmask(0x0000000000000102),
2,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RCSuperclasses,
nullptr
};
extern const TargetRegisterClass ACCRCRegClass = {
&PPCMCRegisterClasses[ACCRCRegClassID],
ACCRCSubClassMask,
SuperRegIdxSeqs + 2,
LaneBitmask(0x0000000000000702),
31,
true,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
NullRegClasses,
nullptr
};
extern const TargetRegisterClass UACCRCRegClass = {
&PPCMCRegisterClasses[UACCRCRegClassID],
UACCRCSubClassMask,
SuperRegIdxSeqs + 2,
LaneBitmask(0x0000000000000702),
4,
true,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
NullRegClasses,
nullptr
};
extern const TargetRegisterClass WACCRCRegClass = {
&PPCMCRegisterClasses[WACCRCRegClassID],
WACCRCSubClassMask,
SuperRegIdxSeqs + 40,
LaneBitmask(0x000000000000180C),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
NullRegClasses,
nullptr
};
extern const TargetRegisterClass WACC_HIRCRegClass = {
&PPCMCRegisterClasses[WACC_HIRCRegClassID],
WACC_HIRCSubClassMask,
SuperRegIdxSeqs + 37,
LaneBitmask(0x000000000000180C),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
NullRegClasses,
nullptr
};
extern const TargetRegisterClass ACCRC_with_sub_64_in_SPILLTOVSRRCRegClass = {
&PPCMCRegisterClasses[ACCRC_with_sub_64_in_SPILLTOVSRRCRegClassID],
ACCRC_with_sub_64_in_SPILLTOVSRRCSubClassMask,
SuperRegIdxSeqs + 2,
LaneBitmask(0x0000000000000702),
31,
true,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
ACCRC_with_sub_64_in_SPILLTOVSRRCSuperclasses,
nullptr
};
extern const TargetRegisterClass UACCRC_with_sub_64_in_SPILLTOVSRRCRegClass = {
&PPCMCRegisterClasses[UACCRC_with_sub_64_in_SPILLTOVSRRCRegClassID],
UACCRC_with_sub_64_in_SPILLTOVSRRCSubClassMask,
SuperRegIdxSeqs + 2,
LaneBitmask(0x0000000000000702),
4,
true,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
UACCRC_with_sub_64_in_SPILLTOVSRRCSuperclasses,
nullptr
};
extern const TargetRegisterClass ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCRegClass = {
&PPCMCRegisterClasses[ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCRegClassID],
ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCSubClassMask,
SuperRegIdxSeqs + 2,
LaneBitmask(0x0000000000000702),
31,
true,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCSuperclasses,
nullptr
};
extern const TargetRegisterClass UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCRegClass = {
&PPCMCRegisterClasses[UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCRegClassID],
UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCSubClassMask,
SuperRegIdxSeqs + 2,
LaneBitmask(0x0000000000000702),
4,
true,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCSuperclasses,
nullptr
};
extern const TargetRegisterClass DMRRCRegClass = {
&PPCMCRegisterClasses[DMRRCRegClassID],
DMRRCSubClassMask,
SuperRegIdxSeqs + 0,
LaneBitmask(0x000000000001F80C),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
NullRegClasses,
nullptr
};
extern const TargetRegisterClass DMRpRCRegClass = {
&PPCMCRegisterClasses[DMRpRCRegClassID],
DMRpRCSubClassMask,
SuperRegIdxSeqs + 2,
LaneBitmask(0x0000000001FFF80C),
0,
false,
0x00, /* TSFlags */
true, /* HasDisjunctSubRegs */
false, /* CoveredBySubRegs */
NullRegClasses,
nullptr
};
} // end namespace PPC
namespace {
const TargetRegisterClass *const RegisterClasses[] = {
&PPC::VSSRCRegClass,
&PPC::GPRCRegClass,
&PPC::GPRC_NOR0RegClass,
&PPC::GPRC_and_GPRC_NOR0RegClass,
&PPC::CRBITRCRegClass,
&PPC::F4RCRegClass,
&PPC::CRRCRegClass,
&PPC::CARRYRCRegClass,
&PPC::CTRRCRegClass,
&PPC::LRRCRegClass,
&PPC::VRSAVERCRegClass,
&PPC::SPILLTOVSRRCRegClass,
&PPC::VSFRCRegClass,
&PPC::G8RCRegClass,
&PPC::G8RC_NOX0RegClass,
&PPC::SPILLTOVSRRC_and_VSFRCRegClass,
&PPC::G8RC_and_G8RC_NOX0RegClass,
&PPC::F8RCRegClass,
&PPC::SPERCRegClass,
&PPC::VFRCRegClass,
&PPC::SPERC_with_sub_32_in_GPRC_NOR0RegClass,
&PPC::SPILLTOVSRRC_and_VFRCRegClass,
&PPC::SPILLTOVSRRC_and_F4RCRegClass,
&PPC::CTRRC8RegClass,
&PPC::LR8RCRegClass,
&PPC::DMRROWRCRegClass,
&PPC::VSRCRegClass,
&PPC::VSRC_with_sub_64_in_SPILLTOVSRRCRegClass,
&PPC::VRRCRegClass,
&PPC::VSLRCRegClass,
&PPC::VRRC_with_sub_64_in_SPILLTOVSRRCRegClass,
&PPC::G8pRCRegClass,
&PPC::G8pRC_with_sub_32_in_GPRC_NOR0RegClass,
&PPC::VSLRC_with_sub_64_in_SPILLTOVSRRCRegClass,
&PPC::DMRROWpRCRegClass,
&PPC::VSRpRCRegClass,
&PPC::VSRpRC_with_sub_64_in_SPILLTOVSRRCRegClass,
&PPC::VSRpRC_with_sub_64_in_F4RCRegClass,
&PPC::VSRpRC_with_sub_64_in_VFRCRegClass,
&PPC::VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRCRegClass,
&PPC::VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RCRegClass,
&PPC::ACCRCRegClass,
&PPC::UACCRCRegClass,
&PPC::WACCRCRegClass,
&PPC::WACC_HIRCRegClass,
&PPC::ACCRC_with_sub_64_in_SPILLTOVSRRCRegClass,
&PPC::UACCRC_with_sub_64_in_SPILLTOVSRRCRegClass,
&PPC::ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCRegClass,
&PPC::UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCRegClass,
&PPC::DMRRCRegClass,
&PPC::DMRpRCRegClass,
};
} // end anonymous namespace
static const uint8_t CostPerUseTable[] = {
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
static const bool InAllocatableClassTable[] = {
false, true, true, false, true, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, };
static const TargetRegisterInfoDesc PPCRegInfoDesc = { // Extra Descriptors
CostPerUseTable, 1, InAllocatableClassTable};
unsigned PPCGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
static const uint8_t RowMap[48] = {
0, 0, 0, 1, 0, 0, 0, 2, 0, 0, 1, 0, 0, 0, 1, 0, 0, 2, 3, 0, 0, 0, 1, 3, 0, 0, 0, 0, 0, 3, 4, 0, 0, 0, 0, 1, 5, 6, 1, 0, 0, 0, 0, 6, 7, 0, 0, 0,
};
static const uint8_t Rows[8][48] = {
{ PPC::sub_32, PPC::sub_64, 0, 0, PPC::sub_dmrrow0, PPC::sub_dmrrow1, PPC::sub_dmrrowp0, PPC::sub_dmrrowp1, 0, 0, 0, 0, 0, 0, 0, 0, PPC::sub_vsx0, PPC::sub_vsx1, PPC::sub_wacc_hi, PPC::sub_wacc_lo, PPC::sub_vsx1_then_sub_64, 0, 0, 0, 0, PPC::sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_dmrrowp1_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrowp0, PPC::sub_wacc_hi_then_sub_dmrrowp1, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
{ PPC::sub_gp8_x1_then_sub_32, PPC::sub_pair1_then_sub_64, 0, 0, PPC::sub_dmr1_then_sub_dmrrow0, PPC::sub_dmr1_then_sub_dmrrow1, PPC::sub_dmr1_then_sub_dmrrowp0, PPC::sub_dmr1_then_sub_dmrrowp1, 0, 0, 0, 0, 0, 0, 0, 0, PPC::sub_pair1_then_sub_vsx0, PPC::sub_pair1_then_sub_vsx1, PPC::sub_dmr1_then_sub_wacc_hi, PPC::sub_dmr1_then_sub_wacc_lo, PPC::sub_pair1_then_sub_vsx1_then_sub_64, 0, 0, 0, 0, PPC::sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1, PPC::sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0, PPC::sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1, PPC::sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0, PPC::sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1, PPC::sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
{ 0, PPC::sub_vsx1_then_sub_64, 0, 0, PPC::sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_dmrrowp1_then_sub_dmrrow1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
{ 0, PPC::sub_pair1_then_sub_vsx1_then_sub_64, 0, 0, PPC::sub_wacc_hi_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrowp0, PPC::sub_wacc_hi_then_sub_dmrrowp1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
{ 0, 0, 0, 0, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
{ 0, 0, 0, 0, PPC::sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
{ 0, 0, 0, 0, PPC::sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0, PPC::sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1, PPC::sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0, PPC::sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, PPC::sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
{ 0, 0, 0, 0, PPC::sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
};
--IdxA; assert(IdxA < 48); (void) IdxA;
--IdxB; assert(IdxB < 48);
return Rows[RowMap[IdxA]][IdxB];
}
struct MaskRolOp {
LaneBitmask Mask;
uint8_t RotateLeft;
};
static const MaskRolOp LaneMaskComposeSequences[] = {
{ LaneBitmask(0xFFFFFFFFFFFFFFFF), 0 }, { LaneBitmask::getNone(), 0 }, // Sequence 0
{ LaneBitmask(0xFFFFFFFFFFFFFFFF), 1 }, { LaneBitmask::getNone(), 0 }, // Sequence 2
{ LaneBitmask(0x000000000000000C), 15 }, { LaneBitmask(0x000000000001F800), 8 }, { LaneBitmask::getNone(), 0 }, // Sequence 4
{ LaneBitmask(0xFFFFFFFFFFFFFFFF), 2 }, { LaneBitmask::getNone(), 0 }, // Sequence 7
{ LaneBitmask(0xFFFFFFFFFFFFFFFF), 3 }, { LaneBitmask::getNone(), 0 }, // Sequence 9
{ LaneBitmask(0xFFFFFFFFFFFFFFFF), 9 }, { LaneBitmask::getNone(), 0 }, // Sequence 11
{ LaneBitmask(0xFFFFFFFFFFFFFFFF), 4 }, { LaneBitmask::getNone(), 0 }, // Sequence 13
{ LaneBitmask(0xFFFFFFFFFFFFFFFF), 25 }, { LaneBitmask::getNone(), 0 }, // Sequence 15
{ LaneBitmask(0xFFFFFFFFFFFFFFFF), 5 }, { LaneBitmask::getNone(), 0 }, // Sequence 17
{ LaneBitmask(0xFFFFFFFFFFFFFFFF), 6 }, { LaneBitmask::getNone(), 0 }, // Sequence 19
{ LaneBitmask(0x0000000000000002), 8 }, { LaneBitmask(0x0000000000000100), 2 }, { LaneBitmask::getNone(), 0 }, // Sequence 21
{ LaneBitmask(0xFFFFFFFFFFFFFFFF), 7 }, { LaneBitmask::getNone(), 0 }, // Sequence 24
{ LaneBitmask(0x000000000000000C), 11 }, { LaneBitmask(0x0000000000001800), 4 }, { LaneBitmask::getNone(), 0 }, // Sequence 26
{ LaneBitmask(0xFFFFFFFFFFFFFFFF), 8 }, { LaneBitmask::getNone(), 0 }, // Sequence 29
{ LaneBitmask(0xFFFFFFFFFFFFFFFF), 10 }, { LaneBitmask::getNone(), 0 }, // Sequence 31
{ LaneBitmask(0xFFFFFFFFFFFFFFFF), 11 }, { LaneBitmask::getNone(), 0 }, // Sequence 33
{ LaneBitmask(0xFFFFFFFFFFFFFFFF), 12 }, { LaneBitmask::getNone(), 0 }, // Sequence 35
{ LaneBitmask(0xFFFFFFFFFFFFFFFF), 13 }, { LaneBitmask::getNone(), 0 }, // Sequence 37
{ LaneBitmask(0xFFFFFFFFFFFFFFFF), 14 }, { LaneBitmask::getNone(), 0 }, // Sequence 39
{ LaneBitmask(0xFFFFFFFFFFFFFFFF), 15 }, { LaneBitmask::getNone(), 0 }, // Sequence 41
{ LaneBitmask(0xFFFFFFFFFFFFFFFF), 16 }, { LaneBitmask::getNone(), 0 }, // Sequence 43
{ LaneBitmask(0xFFFFFFFFFFFFFFFF), 17 }, { LaneBitmask::getNone(), 0 }, // Sequence 45
{ LaneBitmask(0xFFFFFFFFFFFFFFFF), 18 }, { LaneBitmask::getNone(), 0 }, // Sequence 47
{ LaneBitmask(0x000000000000000C), 19 }, { LaneBitmask(0x0000000000001800), 12 }, { LaneBitmask::getNone(), 0 }, // Sequence 49
{ LaneBitmask(0x000000000000000C), 15 }, { LaneBitmask(0x0000000000001800), 8 }, { LaneBitmask::getNone(), 0 }, // Sequence 52
{ LaneBitmask(0xFFFFFFFFFFFFFFFF), 19 }, { LaneBitmask::getNone(), 0 }, // Sequence 55
{ LaneBitmask(0xFFFFFFFFFFFFFFFF), 20 }, { LaneBitmask::getNone(), 0 }, // Sequence 57
{ LaneBitmask(0xFFFFFFFFFFFFFFFF), 21 }, { LaneBitmask::getNone(), 0 }, // Sequence 59
{ LaneBitmask(0xFFFFFFFFFFFFFFFF), 22 }, { LaneBitmask::getNone(), 0 }, // Sequence 61
{ LaneBitmask(0xFFFFFFFFFFFFFFFF), 23 }, { LaneBitmask::getNone(), 0 }, // Sequence 63
{ LaneBitmask(0xFFFFFFFFFFFFFFFF), 24 }, { LaneBitmask::getNone(), 0 } // Sequence 65
};
static const uint8_t CompositeSequences[] = {
0, // to sub_32
2, // to sub_64
0, // to sub_dmr0
4, // to sub_dmr1
7, // to sub_dmrrow0
9, // to sub_dmrrow1
0, // to sub_dmrrowp0
11, // to sub_dmrrowp1
13, // to sub_eq
0, // to sub_gp8_x0
15, // to sub_gp8_x1
17, // to sub_gt
19, // to sub_lt
0, // to sub_pair0
21, // to sub_pair1
24, // to sub_un
0, // to sub_vsx0
24, // to sub_vsx1
26, // to sub_wacc_hi
0, // to sub_wacc_lo
29, // to sub_vsx1_then_sub_64
11, // to sub_pair1_then_sub_64
29, // to sub_pair1_then_sub_vsx0
11, // to sub_pair1_then_sub_vsx1
31, // to sub_pair1_then_sub_vsx1_then_sub_64
33, // to sub_dmrrowp1_then_sub_dmrrow0
35, // to sub_dmrrowp1_then_sub_dmrrow1
37, // to sub_wacc_hi_then_sub_dmrrow0
39, // to sub_wacc_hi_then_sub_dmrrow1
33, // to sub_wacc_hi_then_sub_dmrrowp0
37, // to sub_wacc_hi_then_sub_dmrrowp1
41, // to sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
43, // to sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
45, // to sub_dmr1_then_sub_dmrrow0
47, // to sub_dmr1_then_sub_dmrrow1
41, // to sub_dmr1_then_sub_dmrrowp0
45, // to sub_dmr1_then_sub_dmrrowp1
49, // to sub_dmr1_then_sub_wacc_hi
52, // to sub_dmr1_then_sub_wacc_lo
55, // to sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
57, // to sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
59, // to sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
61, // to sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
55, // to sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
59, // to sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
63, // to sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
65, // to sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
15 // to sub_gp8_x1_then_sub_32
};
LaneBitmask PPCGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
--IdxA; assert(IdxA < 48 && "Subregister index out of bounds");
LaneBitmask Result;
for (const MaskRolOp *Ops =
&LaneMaskComposeSequences[CompositeSequences[IdxA]];
Ops->Mask.any(); ++Ops) {
LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
if (unsigned S = Ops->RotateLeft)
Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
else
Result |= LaneBitmask(M);
}
return Result;
}
LaneBitmask PPCGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
LaneMask &= getSubRegIndexLaneMask(IdxA);
--IdxA; assert(IdxA < 48 && "Subregister index out of bounds");
LaneBitmask Result;
for (const MaskRolOp *Ops =
&LaneMaskComposeSequences[CompositeSequences[IdxA]];
Ops->Mask.any(); ++Ops) {
LaneBitmask::Type M = LaneMask.getAsInteger();
if (unsigned S = Ops->RotateLeft)
Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
else
Result |= LaneBitmask(M);
}
return Result;
}
const TargetRegisterClass *PPCGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
static const uint8_t Table[51][48] = {
{ // VSSRC
0, // sub_32
0, // sub_64
0, // sub_dmr0
0, // sub_dmr1
0, // sub_dmrrow0
0, // sub_dmrrow1
0, // sub_dmrrowp0
0, // sub_dmrrowp1
0, // sub_eq
0, // sub_gp8_x0
0, // sub_gp8_x1
0, // sub_gt
0, // sub_lt
0, // sub_pair0
0, // sub_pair1
0, // sub_un
0, // sub_vsx0
0, // sub_vsx1
0, // sub_wacc_hi
0, // sub_wacc_lo
0, // sub_vsx1_then_sub_64
0, // sub_pair1_then_sub_64
0, // sub_pair1_then_sub_vsx0
0, // sub_pair1_then_sub_vsx1
0, // sub_pair1_then_sub_vsx1_then_sub_64
0, // sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmrrowp1_then_sub_dmrrow1
0, // sub_wacc_hi_then_sub_dmrrow0
0, // sub_wacc_hi_then_sub_dmrrow1
0, // sub_wacc_hi_then_sub_dmrrowp0
0, // sub_wacc_hi_then_sub_dmrrowp1
0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_dmrrowp0
0, // sub_dmr1_then_sub_dmrrowp1
0, // sub_dmr1_then_sub_wacc_hi
0, // sub_dmr1_then_sub_wacc_lo
0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_gp8_x1_then_sub_32
},
{ // GPRC
0, // sub_32
0, // sub_64
0, // sub_dmr0
0, // sub_dmr1
0, // sub_dmrrow0
0, // sub_dmrrow1
0, // sub_dmrrowp0
0, // sub_dmrrowp1
0, // sub_eq
0, // sub_gp8_x0
0, // sub_gp8_x1
0, // sub_gt
0, // sub_lt
0, // sub_pair0
0, // sub_pair1
0, // sub_un
0, // sub_vsx0
0, // sub_vsx1
0, // sub_wacc_hi
0, // sub_wacc_lo
0, // sub_vsx1_then_sub_64
0, // sub_pair1_then_sub_64
0, // sub_pair1_then_sub_vsx0
0, // sub_pair1_then_sub_vsx1
0, // sub_pair1_then_sub_vsx1_then_sub_64
0, // sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmrrowp1_then_sub_dmrrow1
0, // sub_wacc_hi_then_sub_dmrrow0
0, // sub_wacc_hi_then_sub_dmrrow1
0, // sub_wacc_hi_then_sub_dmrrowp0
0, // sub_wacc_hi_then_sub_dmrrowp1
0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_dmrrowp0
0, // sub_dmr1_then_sub_dmrrowp1
0, // sub_dmr1_then_sub_wacc_hi
0, // sub_dmr1_then_sub_wacc_lo
0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_gp8_x1_then_sub_32
},
{ // GPRC_NOR0
0, // sub_32
0, // sub_64
0, // sub_dmr0
0, // sub_dmr1
0, // sub_dmrrow0
0, // sub_dmrrow1
0, // sub_dmrrowp0
0, // sub_dmrrowp1
0, // sub_eq
0, // sub_gp8_x0
0, // sub_gp8_x1
0, // sub_gt
0, // sub_lt
0, // sub_pair0
0, // sub_pair1
0, // sub_un
0, // sub_vsx0
0, // sub_vsx1
0, // sub_wacc_hi
0, // sub_wacc_lo
0, // sub_vsx1_then_sub_64
0, // sub_pair1_then_sub_64
0, // sub_pair1_then_sub_vsx0
0, // sub_pair1_then_sub_vsx1
0, // sub_pair1_then_sub_vsx1_then_sub_64
0, // sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmrrowp1_then_sub_dmrrow1
0, // sub_wacc_hi_then_sub_dmrrow0
0, // sub_wacc_hi_then_sub_dmrrow1
0, // sub_wacc_hi_then_sub_dmrrowp0
0, // sub_wacc_hi_then_sub_dmrrowp1
0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_dmrrowp0
0, // sub_dmr1_then_sub_dmrrowp1
0, // sub_dmr1_then_sub_wacc_hi
0, // sub_dmr1_then_sub_wacc_lo
0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_gp8_x1_then_sub_32
},
{ // GPRC_and_GPRC_NOR0
0, // sub_32
0, // sub_64
0, // sub_dmr0
0, // sub_dmr1
0, // sub_dmrrow0
0, // sub_dmrrow1
0, // sub_dmrrowp0
0, // sub_dmrrowp1
0, // sub_eq
0, // sub_gp8_x0
0, // sub_gp8_x1
0, // sub_gt
0, // sub_lt
0, // sub_pair0
0, // sub_pair1
0, // sub_un
0, // sub_vsx0
0, // sub_vsx1
0, // sub_wacc_hi
0, // sub_wacc_lo
0, // sub_vsx1_then_sub_64
0, // sub_pair1_then_sub_64
0, // sub_pair1_then_sub_vsx0
0, // sub_pair1_then_sub_vsx1
0, // sub_pair1_then_sub_vsx1_then_sub_64
0, // sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmrrowp1_then_sub_dmrrow1
0, // sub_wacc_hi_then_sub_dmrrow0
0, // sub_wacc_hi_then_sub_dmrrow1
0, // sub_wacc_hi_then_sub_dmrrowp0
0, // sub_wacc_hi_then_sub_dmrrowp1
0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_dmrrowp0
0, // sub_dmr1_then_sub_dmrrowp1
0, // sub_dmr1_then_sub_wacc_hi
0, // sub_dmr1_then_sub_wacc_lo
0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_gp8_x1_then_sub_32
},
{ // CRBITRC
0, // sub_32
0, // sub_64
0, // sub_dmr0
0, // sub_dmr1
0, // sub_dmrrow0
0, // sub_dmrrow1
0, // sub_dmrrowp0
0, // sub_dmrrowp1
0, // sub_eq
0, // sub_gp8_x0
0, // sub_gp8_x1
0, // sub_gt
0, // sub_lt
0, // sub_pair0
0, // sub_pair1
0, // sub_un
0, // sub_vsx0
0, // sub_vsx1
0, // sub_wacc_hi
0, // sub_wacc_lo
0, // sub_vsx1_then_sub_64
0, // sub_pair1_then_sub_64
0, // sub_pair1_then_sub_vsx0
0, // sub_pair1_then_sub_vsx1
0, // sub_pair1_then_sub_vsx1_then_sub_64
0, // sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmrrowp1_then_sub_dmrrow1
0, // sub_wacc_hi_then_sub_dmrrow0
0, // sub_wacc_hi_then_sub_dmrrow1
0, // sub_wacc_hi_then_sub_dmrrowp0
0, // sub_wacc_hi_then_sub_dmrrowp1
0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_dmrrowp0
0, // sub_dmr1_then_sub_dmrrowp1
0, // sub_dmr1_then_sub_wacc_hi
0, // sub_dmr1_then_sub_wacc_lo
0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_gp8_x1_then_sub_32
},
{ // F4RC
0, // sub_32
0, // sub_64
0, // sub_dmr0
0, // sub_dmr1
0, // sub_dmrrow0
0, // sub_dmrrow1
0, // sub_dmrrowp0
0, // sub_dmrrowp1
0, // sub_eq
0, // sub_gp8_x0
0, // sub_gp8_x1
0, // sub_gt
0, // sub_lt
0, // sub_pair0
0, // sub_pair1
0, // sub_un
0, // sub_vsx0
0, // sub_vsx1
0, // sub_wacc_hi
0, // sub_wacc_lo
0, // sub_vsx1_then_sub_64
0, // sub_pair1_then_sub_64
0, // sub_pair1_then_sub_vsx0
0, // sub_pair1_then_sub_vsx1
0, // sub_pair1_then_sub_vsx1_then_sub_64
0, // sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmrrowp1_then_sub_dmrrow1
0, // sub_wacc_hi_then_sub_dmrrow0
0, // sub_wacc_hi_then_sub_dmrrow1
0, // sub_wacc_hi_then_sub_dmrrowp0
0, // sub_wacc_hi_then_sub_dmrrowp1
0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_dmrrowp0
0, // sub_dmr1_then_sub_dmrrowp1
0, // sub_dmr1_then_sub_wacc_hi
0, // sub_dmr1_then_sub_wacc_lo
0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_gp8_x1_then_sub_32
},
{ // CRRC
0, // sub_32
0, // sub_64
0, // sub_dmr0
0, // sub_dmr1
0, // sub_dmrrow0
0, // sub_dmrrow1
0, // sub_dmrrowp0
0, // sub_dmrrowp1
7, // sub_eq -> CRRC
0, // sub_gp8_x0
0, // sub_gp8_x1
7, // sub_gt -> CRRC
7, // sub_lt -> CRRC
0, // sub_pair0
0, // sub_pair1
7, // sub_un -> CRRC
0, // sub_vsx0
0, // sub_vsx1
0, // sub_wacc_hi
0, // sub_wacc_lo
0, // sub_vsx1_then_sub_64
0, // sub_pair1_then_sub_64
0, // sub_pair1_then_sub_vsx0
0, // sub_pair1_then_sub_vsx1
0, // sub_pair1_then_sub_vsx1_then_sub_64
0, // sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmrrowp1_then_sub_dmrrow1
0, // sub_wacc_hi_then_sub_dmrrow0
0, // sub_wacc_hi_then_sub_dmrrow1
0, // sub_wacc_hi_then_sub_dmrrowp0
0, // sub_wacc_hi_then_sub_dmrrowp1
0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_dmrrowp0
0, // sub_dmr1_then_sub_dmrrowp1
0, // sub_dmr1_then_sub_wacc_hi
0, // sub_dmr1_then_sub_wacc_lo
0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_gp8_x1_then_sub_32
},
{ // CARRYRC
0, // sub_32
0, // sub_64
0, // sub_dmr0
0, // sub_dmr1
0, // sub_dmrrow0
0, // sub_dmrrow1
0, // sub_dmrrowp0
0, // sub_dmrrowp1
0, // sub_eq
0, // sub_gp8_x0
0, // sub_gp8_x1
0, // sub_gt
0, // sub_lt
0, // sub_pair0
0, // sub_pair1
0, // sub_un
0, // sub_vsx0
0, // sub_vsx1
0, // sub_wacc_hi
0, // sub_wacc_lo
0, // sub_vsx1_then_sub_64
0, // sub_pair1_then_sub_64
0, // sub_pair1_then_sub_vsx0
0, // sub_pair1_then_sub_vsx1
0, // sub_pair1_then_sub_vsx1_then_sub_64
0, // sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmrrowp1_then_sub_dmrrow1
0, // sub_wacc_hi_then_sub_dmrrow0
0, // sub_wacc_hi_then_sub_dmrrow1
0, // sub_wacc_hi_then_sub_dmrrowp0
0, // sub_wacc_hi_then_sub_dmrrowp1
0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_dmrrowp0
0, // sub_dmr1_then_sub_dmrrowp1
0, // sub_dmr1_then_sub_wacc_hi
0, // sub_dmr1_then_sub_wacc_lo
0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_gp8_x1_then_sub_32
},
{ // CTRRC
0, // sub_32
0, // sub_64
0, // sub_dmr0
0, // sub_dmr1
0, // sub_dmrrow0
0, // sub_dmrrow1
0, // sub_dmrrowp0
0, // sub_dmrrowp1
0, // sub_eq
0, // sub_gp8_x0
0, // sub_gp8_x1
0, // sub_gt
0, // sub_lt
0, // sub_pair0
0, // sub_pair1
0, // sub_un
0, // sub_vsx0
0, // sub_vsx1
0, // sub_wacc_hi
0, // sub_wacc_lo
0, // sub_vsx1_then_sub_64
0, // sub_pair1_then_sub_64
0, // sub_pair1_then_sub_vsx0
0, // sub_pair1_then_sub_vsx1
0, // sub_pair1_then_sub_vsx1_then_sub_64
0, // sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmrrowp1_then_sub_dmrrow1
0, // sub_wacc_hi_then_sub_dmrrow0
0, // sub_wacc_hi_then_sub_dmrrow1
0, // sub_wacc_hi_then_sub_dmrrowp0
0, // sub_wacc_hi_then_sub_dmrrowp1
0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_dmrrowp0
0, // sub_dmr1_then_sub_dmrrowp1
0, // sub_dmr1_then_sub_wacc_hi
0, // sub_dmr1_then_sub_wacc_lo
0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_gp8_x1_then_sub_32
},
{ // LRRC
0, // sub_32
0, // sub_64
0, // sub_dmr0
0, // sub_dmr1
0, // sub_dmrrow0
0, // sub_dmrrow1
0, // sub_dmrrowp0
0, // sub_dmrrowp1
0, // sub_eq
0, // sub_gp8_x0
0, // sub_gp8_x1
0, // sub_gt
0, // sub_lt
0, // sub_pair0
0, // sub_pair1
0, // sub_un
0, // sub_vsx0
0, // sub_vsx1
0, // sub_wacc_hi
0, // sub_wacc_lo
0, // sub_vsx1_then_sub_64
0, // sub_pair1_then_sub_64
0, // sub_pair1_then_sub_vsx0
0, // sub_pair1_then_sub_vsx1
0, // sub_pair1_then_sub_vsx1_then_sub_64
0, // sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmrrowp1_then_sub_dmrrow1
0, // sub_wacc_hi_then_sub_dmrrow0
0, // sub_wacc_hi_then_sub_dmrrow1
0, // sub_wacc_hi_then_sub_dmrrowp0
0, // sub_wacc_hi_then_sub_dmrrowp1
0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_dmrrowp0
0, // sub_dmr1_then_sub_dmrrowp1
0, // sub_dmr1_then_sub_wacc_hi
0, // sub_dmr1_then_sub_wacc_lo
0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_gp8_x1_then_sub_32
},
{ // VRSAVERC
0, // sub_32
0, // sub_64
0, // sub_dmr0
0, // sub_dmr1
0, // sub_dmrrow0
0, // sub_dmrrow1
0, // sub_dmrrowp0
0, // sub_dmrrowp1
0, // sub_eq
0, // sub_gp8_x0
0, // sub_gp8_x1
0, // sub_gt
0, // sub_lt
0, // sub_pair0
0, // sub_pair1
0, // sub_un
0, // sub_vsx0
0, // sub_vsx1
0, // sub_wacc_hi
0, // sub_wacc_lo
0, // sub_vsx1_then_sub_64
0, // sub_pair1_then_sub_64
0, // sub_pair1_then_sub_vsx0
0, // sub_pair1_then_sub_vsx1
0, // sub_pair1_then_sub_vsx1_then_sub_64
0, // sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmrrowp1_then_sub_dmrrow1
0, // sub_wacc_hi_then_sub_dmrrow0
0, // sub_wacc_hi_then_sub_dmrrow1
0, // sub_wacc_hi_then_sub_dmrrowp0
0, // sub_wacc_hi_then_sub_dmrrowp1
0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_dmrrowp0
0, // sub_dmr1_then_sub_dmrrowp1
0, // sub_dmr1_then_sub_wacc_hi
0, // sub_dmr1_then_sub_wacc_lo
0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_gp8_x1_then_sub_32
},
{ // SPILLTOVSRRC
14, // sub_32 -> G8RC
0, // sub_64
0, // sub_dmr0
0, // sub_dmr1
0, // sub_dmrrow0
0, // sub_dmrrow1
0, // sub_dmrrowp0
0, // sub_dmrrowp1
0, // sub_eq
0, // sub_gp8_x0
0, // sub_gp8_x1
0, // sub_gt
0, // sub_lt
0, // sub_pair0
0, // sub_pair1
0, // sub_un
0, // sub_vsx0
0, // sub_vsx1
0, // sub_wacc_hi
0, // sub_wacc_lo
0, // sub_vsx1_then_sub_64
0, // sub_pair1_then_sub_64
0, // sub_pair1_then_sub_vsx0
0, // sub_pair1_then_sub_vsx1
0, // sub_pair1_then_sub_vsx1_then_sub_64
0, // sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmrrowp1_then_sub_dmrrow1
0, // sub_wacc_hi_then_sub_dmrrow0
0, // sub_wacc_hi_then_sub_dmrrow1
0, // sub_wacc_hi_then_sub_dmrrowp0
0, // sub_wacc_hi_then_sub_dmrrowp1
0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_dmrrowp0
0, // sub_dmr1_then_sub_dmrrowp1
0, // sub_dmr1_then_sub_wacc_hi
0, // sub_dmr1_then_sub_wacc_lo
0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_gp8_x1_then_sub_32
},
{ // VSFRC
0, // sub_32
0, // sub_64
0, // sub_dmr0
0, // sub_dmr1
0, // sub_dmrrow0
0, // sub_dmrrow1
0, // sub_dmrrowp0
0, // sub_dmrrowp1
0, // sub_eq
0, // sub_gp8_x0
0, // sub_gp8_x1
0, // sub_gt
0, // sub_lt
0, // sub_pair0
0, // sub_pair1
0, // sub_un
0, // sub_vsx0
0, // sub_vsx1
0, // sub_wacc_hi
0, // sub_wacc_lo
0, // sub_vsx1_then_sub_64
0, // sub_pair1_then_sub_64
0, // sub_pair1_then_sub_vsx0
0, // sub_pair1_then_sub_vsx1
0, // sub_pair1_then_sub_vsx1_then_sub_64
0, // sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmrrowp1_then_sub_dmrrow1
0, // sub_wacc_hi_then_sub_dmrrow0
0, // sub_wacc_hi_then_sub_dmrrow1
0, // sub_wacc_hi_then_sub_dmrrowp0
0, // sub_wacc_hi_then_sub_dmrrowp1
0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_dmrrowp0
0, // sub_dmr1_then_sub_dmrrowp1
0, // sub_dmr1_then_sub_wacc_hi
0, // sub_dmr1_then_sub_wacc_lo
0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_gp8_x1_then_sub_32
},
{ // G8RC
14, // sub_32 -> G8RC
0, // sub_64
0, // sub_dmr0
0, // sub_dmr1
0, // sub_dmrrow0
0, // sub_dmrrow1
0, // sub_dmrrowp0
0, // sub_dmrrowp1
0, // sub_eq
0, // sub_gp8_x0
0, // sub_gp8_x1
0, // sub_gt
0, // sub_lt
0, // sub_pair0
0, // sub_pair1
0, // sub_un
0, // sub_vsx0
0, // sub_vsx1
0, // sub_wacc_hi
0, // sub_wacc_lo
0, // sub_vsx1_then_sub_64
0, // sub_pair1_then_sub_64
0, // sub_pair1_then_sub_vsx0
0, // sub_pair1_then_sub_vsx1
0, // sub_pair1_then_sub_vsx1_then_sub_64
0, // sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmrrowp1_then_sub_dmrrow1
0, // sub_wacc_hi_then_sub_dmrrow0
0, // sub_wacc_hi_then_sub_dmrrow1
0, // sub_wacc_hi_then_sub_dmrrowp0
0, // sub_wacc_hi_then_sub_dmrrowp1
0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_dmrrowp0
0, // sub_dmr1_then_sub_dmrrowp1
0, // sub_dmr1_then_sub_wacc_hi
0, // sub_dmr1_then_sub_wacc_lo
0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_gp8_x1_then_sub_32
},
{ // G8RC_NOX0
15, // sub_32 -> G8RC_NOX0
0, // sub_64
0, // sub_dmr0
0, // sub_dmr1
0, // sub_dmrrow0
0, // sub_dmrrow1
0, // sub_dmrrowp0
0, // sub_dmrrowp1
0, // sub_eq
0, // sub_gp8_x0
0, // sub_gp8_x1
0, // sub_gt
0, // sub_lt
0, // sub_pair0
0, // sub_pair1
0, // sub_un
0, // sub_vsx0
0, // sub_vsx1
0, // sub_wacc_hi
0, // sub_wacc_lo
0, // sub_vsx1_then_sub_64
0, // sub_pair1_then_sub_64
0, // sub_pair1_then_sub_vsx0
0, // sub_pair1_then_sub_vsx1
0, // sub_pair1_then_sub_vsx1_then_sub_64
0, // sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmrrowp1_then_sub_dmrrow1
0, // sub_wacc_hi_then_sub_dmrrow0
0, // sub_wacc_hi_then_sub_dmrrow1
0, // sub_wacc_hi_then_sub_dmrrowp0
0, // sub_wacc_hi_then_sub_dmrrowp1
0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_dmrrowp0
0, // sub_dmr1_then_sub_dmrrowp1
0, // sub_dmr1_then_sub_wacc_hi
0, // sub_dmr1_then_sub_wacc_lo
0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_gp8_x1_then_sub_32
},
{ // SPILLTOVSRRC_and_VSFRC
0, // sub_32
0, // sub_64
0, // sub_dmr0
0, // sub_dmr1
0, // sub_dmrrow0
0, // sub_dmrrow1
0, // sub_dmrrowp0
0, // sub_dmrrowp1
0, // sub_eq
0, // sub_gp8_x0
0, // sub_gp8_x1
0, // sub_gt
0, // sub_lt
0, // sub_pair0
0, // sub_pair1
0, // sub_un
0, // sub_vsx0
0, // sub_vsx1
0, // sub_wacc_hi
0, // sub_wacc_lo
0, // sub_vsx1_then_sub_64
0, // sub_pair1_then_sub_64
0, // sub_pair1_then_sub_vsx0
0, // sub_pair1_then_sub_vsx1
0, // sub_pair1_then_sub_vsx1_then_sub_64
0, // sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmrrowp1_then_sub_dmrrow1
0, // sub_wacc_hi_then_sub_dmrrow0
0, // sub_wacc_hi_then_sub_dmrrow1
0, // sub_wacc_hi_then_sub_dmrrowp0
0, // sub_wacc_hi_then_sub_dmrrowp1
0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_dmrrowp0
0, // sub_dmr1_then_sub_dmrrowp1
0, // sub_dmr1_then_sub_wacc_hi
0, // sub_dmr1_then_sub_wacc_lo
0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_gp8_x1_then_sub_32
},
{ // G8RC_and_G8RC_NOX0
17, // sub_32 -> G8RC_and_G8RC_NOX0
0, // sub_64
0, // sub_dmr0
0, // sub_dmr1
0, // sub_dmrrow0
0, // sub_dmrrow1
0, // sub_dmrrowp0
0, // sub_dmrrowp1
0, // sub_eq
0, // sub_gp8_x0
0, // sub_gp8_x1
0, // sub_gt
0, // sub_lt
0, // sub_pair0
0, // sub_pair1
0, // sub_un
0, // sub_vsx0
0, // sub_vsx1
0, // sub_wacc_hi
0, // sub_wacc_lo
0, // sub_vsx1_then_sub_64
0, // sub_pair1_then_sub_64
0, // sub_pair1_then_sub_vsx0
0, // sub_pair1_then_sub_vsx1
0, // sub_pair1_then_sub_vsx1_then_sub_64
0, // sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmrrowp1_then_sub_dmrrow1
0, // sub_wacc_hi_then_sub_dmrrow0
0, // sub_wacc_hi_then_sub_dmrrow1
0, // sub_wacc_hi_then_sub_dmrrowp0
0, // sub_wacc_hi_then_sub_dmrrowp1
0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_dmrrowp0
0, // sub_dmr1_then_sub_dmrrowp1
0, // sub_dmr1_then_sub_wacc_hi
0, // sub_dmr1_then_sub_wacc_lo
0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_gp8_x1_then_sub_32
},
{ // F8RC
0, // sub_32
0, // sub_64
0, // sub_dmr0
0, // sub_dmr1
0, // sub_dmrrow0
0, // sub_dmrrow1
0, // sub_dmrrowp0
0, // sub_dmrrowp1
0, // sub_eq
0, // sub_gp8_x0
0, // sub_gp8_x1
0, // sub_gt
0, // sub_lt
0, // sub_pair0
0, // sub_pair1
0, // sub_un
0, // sub_vsx0
0, // sub_vsx1
0, // sub_wacc_hi
0, // sub_wacc_lo
0, // sub_vsx1_then_sub_64
0, // sub_pair1_then_sub_64
0, // sub_pair1_then_sub_vsx0
0, // sub_pair1_then_sub_vsx1
0, // sub_pair1_then_sub_vsx1_then_sub_64
0, // sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmrrowp1_then_sub_dmrrow1
0, // sub_wacc_hi_then_sub_dmrrow0
0, // sub_wacc_hi_then_sub_dmrrow1
0, // sub_wacc_hi_then_sub_dmrrowp0
0, // sub_wacc_hi_then_sub_dmrrowp1
0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_dmrrowp0
0, // sub_dmr1_then_sub_dmrrowp1
0, // sub_dmr1_then_sub_wacc_hi
0, // sub_dmr1_then_sub_wacc_lo
0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_gp8_x1_then_sub_32
},
{ // SPERC
19, // sub_32 -> SPERC
0, // sub_64
0, // sub_dmr0
0, // sub_dmr1
0, // sub_dmrrow0
0, // sub_dmrrow1
0, // sub_dmrrowp0
0, // sub_dmrrowp1
0, // sub_eq
0, // sub_gp8_x0
0, // sub_gp8_x1
0, // sub_gt
0, // sub_lt
0, // sub_pair0
0, // sub_pair1
0, // sub_un
0, // sub_vsx0
0, // sub_vsx1
0, // sub_wacc_hi
0, // sub_wacc_lo
0, // sub_vsx1_then_sub_64
0, // sub_pair1_then_sub_64
0, // sub_pair1_then_sub_vsx0
0, // sub_pair1_then_sub_vsx1
0, // sub_pair1_then_sub_vsx1_then_sub_64
0, // sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmrrowp1_then_sub_dmrrow1
0, // sub_wacc_hi_then_sub_dmrrow0
0, // sub_wacc_hi_then_sub_dmrrow1
0, // sub_wacc_hi_then_sub_dmrrowp0
0, // sub_wacc_hi_then_sub_dmrrowp1
0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_dmrrowp0
0, // sub_dmr1_then_sub_dmrrowp1
0, // sub_dmr1_then_sub_wacc_hi
0, // sub_dmr1_then_sub_wacc_lo
0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_gp8_x1_then_sub_32
},
{ // VFRC
0, // sub_32
0, // sub_64
0, // sub_dmr0
0, // sub_dmr1
0, // sub_dmrrow0
0, // sub_dmrrow1
0, // sub_dmrrowp0
0, // sub_dmrrowp1
0, // sub_eq
0, // sub_gp8_x0
0, // sub_gp8_x1
0, // sub_gt
0, // sub_lt
0, // sub_pair0
0, // sub_pair1
0, // sub_un
0, // sub_vsx0
0, // sub_vsx1
0, // sub_wacc_hi
0, // sub_wacc_lo
0, // sub_vsx1_then_sub_64
0, // sub_pair1_then_sub_64
0, // sub_pair1_then_sub_vsx0
0, // sub_pair1_then_sub_vsx1
0, // sub_pair1_then_sub_vsx1_then_sub_64
0, // sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmrrowp1_then_sub_dmrrow1
0, // sub_wacc_hi_then_sub_dmrrow0
0, // sub_wacc_hi_then_sub_dmrrow1
0, // sub_wacc_hi_then_sub_dmrrowp0
0, // sub_wacc_hi_then_sub_dmrrowp1
0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_dmrrowp0
0, // sub_dmr1_then_sub_dmrrowp1
0, // sub_dmr1_then_sub_wacc_hi
0, // sub_dmr1_then_sub_wacc_lo
0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_gp8_x1_then_sub_32
},
{ // SPERC_with_sub_32_in_GPRC_NOR0
21, // sub_32 -> SPERC_with_sub_32_in_GPRC_NOR0
0, // sub_64
0, // sub_dmr0
0, // sub_dmr1
0, // sub_dmrrow0
0, // sub_dmrrow1
0, // sub_dmrrowp0
0, // sub_dmrrowp1
0, // sub_eq
0, // sub_gp8_x0
0, // sub_gp8_x1
0, // sub_gt
0, // sub_lt
0, // sub_pair0
0, // sub_pair1
0, // sub_un
0, // sub_vsx0
0, // sub_vsx1
0, // sub_wacc_hi
0, // sub_wacc_lo
0, // sub_vsx1_then_sub_64
0, // sub_pair1_then_sub_64
0, // sub_pair1_then_sub_vsx0
0, // sub_pair1_then_sub_vsx1
0, // sub_pair1_then_sub_vsx1_then_sub_64
0, // sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmrrowp1_then_sub_dmrrow1
0, // sub_wacc_hi_then_sub_dmrrow0
0, // sub_wacc_hi_then_sub_dmrrow1
0, // sub_wacc_hi_then_sub_dmrrowp0
0, // sub_wacc_hi_then_sub_dmrrowp1
0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_dmrrowp0
0, // sub_dmr1_then_sub_dmrrowp1
0, // sub_dmr1_then_sub_wacc_hi
0, // sub_dmr1_then_sub_wacc_lo
0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_gp8_x1_then_sub_32
},
{ // SPILLTOVSRRC_and_VFRC
0, // sub_32
0, // sub_64
0, // sub_dmr0
0, // sub_dmr1
0, // sub_dmrrow0
0, // sub_dmrrow1
0, // sub_dmrrowp0
0, // sub_dmrrowp1
0, // sub_eq
0, // sub_gp8_x0
0, // sub_gp8_x1
0, // sub_gt
0, // sub_lt
0, // sub_pair0
0, // sub_pair1
0, // sub_un
0, // sub_vsx0
0, // sub_vsx1
0, // sub_wacc_hi
0, // sub_wacc_lo
0, // sub_vsx1_then_sub_64
0, // sub_pair1_then_sub_64
0, // sub_pair1_then_sub_vsx0
0, // sub_pair1_then_sub_vsx1
0, // sub_pair1_then_sub_vsx1_then_sub_64
0, // sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmrrowp1_then_sub_dmrrow1
0, // sub_wacc_hi_then_sub_dmrrow0
0, // sub_wacc_hi_then_sub_dmrrow1
0, // sub_wacc_hi_then_sub_dmrrowp0
0, // sub_wacc_hi_then_sub_dmrrowp1
0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_dmrrowp0
0, // sub_dmr1_then_sub_dmrrowp1
0, // sub_dmr1_then_sub_wacc_hi
0, // sub_dmr1_then_sub_wacc_lo
0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_gp8_x1_then_sub_32
},
{ // SPILLTOVSRRC_and_F4RC
0, // sub_32
0, // sub_64
0, // sub_dmr0
0, // sub_dmr1
0, // sub_dmrrow0
0, // sub_dmrrow1
0, // sub_dmrrowp0
0, // sub_dmrrowp1
0, // sub_eq
0, // sub_gp8_x0
0, // sub_gp8_x1
0, // sub_gt
0, // sub_lt
0, // sub_pair0
0, // sub_pair1
0, // sub_un
0, // sub_vsx0
0, // sub_vsx1
0, // sub_wacc_hi
0, // sub_wacc_lo
0, // sub_vsx1_then_sub_64
0, // sub_pair1_then_sub_64
0, // sub_pair1_then_sub_vsx0
0, // sub_pair1_then_sub_vsx1
0, // sub_pair1_then_sub_vsx1_then_sub_64
0, // sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmrrowp1_then_sub_dmrrow1
0, // sub_wacc_hi_then_sub_dmrrow0
0, // sub_wacc_hi_then_sub_dmrrow1
0, // sub_wacc_hi_then_sub_dmrrowp0
0, // sub_wacc_hi_then_sub_dmrrowp1
0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_dmrrowp0
0, // sub_dmr1_then_sub_dmrrowp1
0, // sub_dmr1_then_sub_wacc_hi
0, // sub_dmr1_then_sub_wacc_lo
0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_gp8_x1_then_sub_32
},
{ // CTRRC8
0, // sub_32
0, // sub_64
0, // sub_dmr0
0, // sub_dmr1
0, // sub_dmrrow0
0, // sub_dmrrow1
0, // sub_dmrrowp0
0, // sub_dmrrowp1
0, // sub_eq
0, // sub_gp8_x0
0, // sub_gp8_x1
0, // sub_gt
0, // sub_lt
0, // sub_pair0
0, // sub_pair1
0, // sub_un
0, // sub_vsx0
0, // sub_vsx1
0, // sub_wacc_hi
0, // sub_wacc_lo
0, // sub_vsx1_then_sub_64
0, // sub_pair1_then_sub_64
0, // sub_pair1_then_sub_vsx0
0, // sub_pair1_then_sub_vsx1
0, // sub_pair1_then_sub_vsx1_then_sub_64
0, // sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmrrowp1_then_sub_dmrrow1
0, // sub_wacc_hi_then_sub_dmrrow0
0, // sub_wacc_hi_then_sub_dmrrow1
0, // sub_wacc_hi_then_sub_dmrrowp0
0, // sub_wacc_hi_then_sub_dmrrowp1
0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_dmrrowp0
0, // sub_dmr1_then_sub_dmrrowp1
0, // sub_dmr1_then_sub_wacc_hi
0, // sub_dmr1_then_sub_wacc_lo
0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_gp8_x1_then_sub_32
},
{ // LR8RC
0, // sub_32
0, // sub_64
0, // sub_dmr0
0, // sub_dmr1
0, // sub_dmrrow0
0, // sub_dmrrow1
0, // sub_dmrrowp0
0, // sub_dmrrowp1
0, // sub_eq
0, // sub_gp8_x0
0, // sub_gp8_x1
0, // sub_gt
0, // sub_lt
0, // sub_pair0
0, // sub_pair1
0, // sub_un
0, // sub_vsx0
0, // sub_vsx1
0, // sub_wacc_hi
0, // sub_wacc_lo
0, // sub_vsx1_then_sub_64
0, // sub_pair1_then_sub_64
0, // sub_pair1_then_sub_vsx0
0, // sub_pair1_then_sub_vsx1
0, // sub_pair1_then_sub_vsx1_then_sub_64
0, // sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmrrowp1_then_sub_dmrrow1
0, // sub_wacc_hi_then_sub_dmrrow0
0, // sub_wacc_hi_then_sub_dmrrow1
0, // sub_wacc_hi_then_sub_dmrrowp0
0, // sub_wacc_hi_then_sub_dmrrowp1
0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_dmrrowp0
0, // sub_dmr1_then_sub_dmrrowp1
0, // sub_dmr1_then_sub_wacc_hi
0, // sub_dmr1_then_sub_wacc_lo
0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_gp8_x1_then_sub_32
},
{ // DMRROWRC
0, // sub_32
0, // sub_64
0, // sub_dmr0
0, // sub_dmr1
0, // sub_dmrrow0
0, // sub_dmrrow1
0, // sub_dmrrowp0
0, // sub_dmrrowp1
0, // sub_eq
0, // sub_gp8_x0
0, // sub_gp8_x1
0, // sub_gt
0, // sub_lt
0, // sub_pair0
0, // sub_pair1
0, // sub_un
0, // sub_vsx0
0, // sub_vsx1
0, // sub_wacc_hi
0, // sub_wacc_lo
0, // sub_vsx1_then_sub_64
0, // sub_pair1_then_sub_64
0, // sub_pair1_then_sub_vsx0
0, // sub_pair1_then_sub_vsx1
0, // sub_pair1_then_sub_vsx1_then_sub_64
0, // sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmrrowp1_then_sub_dmrrow1
0, // sub_wacc_hi_then_sub_dmrrow0
0, // sub_wacc_hi_then_sub_dmrrow1
0, // sub_wacc_hi_then_sub_dmrrowp0
0, // sub_wacc_hi_then_sub_dmrrowp1
0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_dmrrowp0
0, // sub_dmr1_then_sub_dmrrowp1
0, // sub_dmr1_then_sub_wacc_hi
0, // sub_dmr1_then_sub_wacc_lo
0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_gp8_x1_then_sub_32
},
{ // VSRC
0, // sub_32
27, // sub_64 -> VSRC
0, // sub_dmr0
0, // sub_dmr1
0, // sub_dmrrow0
0, // sub_dmrrow1
0, // sub_dmrrowp0
0, // sub_dmrrowp1
0, // sub_eq
0, // sub_gp8_x0
0, // sub_gp8_x1
0, // sub_gt
0, // sub_lt
0, // sub_pair0
0, // sub_pair1
0, // sub_un
0, // sub_vsx0
0, // sub_vsx1
0, // sub_wacc_hi
0, // sub_wacc_lo
0, // sub_vsx1_then_sub_64
0, // sub_pair1_then_sub_64
0, // sub_pair1_then_sub_vsx0
0, // sub_pair1_then_sub_vsx1
0, // sub_pair1_then_sub_vsx1_then_sub_64
0, // sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmrrowp1_then_sub_dmrrow1
0, // sub_wacc_hi_then_sub_dmrrow0
0, // sub_wacc_hi_then_sub_dmrrow1
0, // sub_wacc_hi_then_sub_dmrrowp0
0, // sub_wacc_hi_then_sub_dmrrowp1
0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_dmrrowp0
0, // sub_dmr1_then_sub_dmrrowp1
0, // sub_dmr1_then_sub_wacc_hi
0, // sub_dmr1_then_sub_wacc_lo
0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_gp8_x1_then_sub_32
},
{ // VSRC_with_sub_64_in_SPILLTOVSRRC
0, // sub_32
28, // sub_64 -> VSRC_with_sub_64_in_SPILLTOVSRRC
0, // sub_dmr0
0, // sub_dmr1
0, // sub_dmrrow0
0, // sub_dmrrow1
0, // sub_dmrrowp0
0, // sub_dmrrowp1
0, // sub_eq
0, // sub_gp8_x0
0, // sub_gp8_x1
0, // sub_gt
0, // sub_lt
0, // sub_pair0
0, // sub_pair1
0, // sub_un
0, // sub_vsx0
0, // sub_vsx1
0, // sub_wacc_hi
0, // sub_wacc_lo
0, // sub_vsx1_then_sub_64
0, // sub_pair1_then_sub_64
0, // sub_pair1_then_sub_vsx0
0, // sub_pair1_then_sub_vsx1
0, // sub_pair1_then_sub_vsx1_then_sub_64
0, // sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmrrowp1_then_sub_dmrrow1
0, // sub_wacc_hi_then_sub_dmrrow0
0, // sub_wacc_hi_then_sub_dmrrow1
0, // sub_wacc_hi_then_sub_dmrrowp0
0, // sub_wacc_hi_then_sub_dmrrowp1
0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_dmrrowp0
0, // sub_dmr1_then_sub_dmrrowp1
0, // sub_dmr1_then_sub_wacc_hi
0, // sub_dmr1_then_sub_wacc_lo
0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_gp8_x1_then_sub_32
},
{ // VRRC
0, // sub_32
29, // sub_64 -> VRRC
0, // sub_dmr0
0, // sub_dmr1
0, // sub_dmrrow0
0, // sub_dmrrow1
0, // sub_dmrrowp0
0, // sub_dmrrowp1
0, // sub_eq
0, // sub_gp8_x0
0, // sub_gp8_x1
0, // sub_gt
0, // sub_lt
0, // sub_pair0
0, // sub_pair1
0, // sub_un
0, // sub_vsx0
0, // sub_vsx1
0, // sub_wacc_hi
0, // sub_wacc_lo
0, // sub_vsx1_then_sub_64
0, // sub_pair1_then_sub_64
0, // sub_pair1_then_sub_vsx0
0, // sub_pair1_then_sub_vsx1
0, // sub_pair1_then_sub_vsx1_then_sub_64
0, // sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmrrowp1_then_sub_dmrrow1
0, // sub_wacc_hi_then_sub_dmrrow0
0, // sub_wacc_hi_then_sub_dmrrow1
0, // sub_wacc_hi_then_sub_dmrrowp0
0, // sub_wacc_hi_then_sub_dmrrowp1
0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_dmrrowp0
0, // sub_dmr1_then_sub_dmrrowp1
0, // sub_dmr1_then_sub_wacc_hi
0, // sub_dmr1_then_sub_wacc_lo
0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_gp8_x1_then_sub_32
},
{ // VSLRC
0, // sub_32
30, // sub_64 -> VSLRC
0, // sub_dmr0
0, // sub_dmr1
0, // sub_dmrrow0
0, // sub_dmrrow1
0, // sub_dmrrowp0
0, // sub_dmrrowp1
0, // sub_eq
0, // sub_gp8_x0
0, // sub_gp8_x1
0, // sub_gt
0, // sub_lt
0, // sub_pair0
0, // sub_pair1
0, // sub_un
0, // sub_vsx0
0, // sub_vsx1
0, // sub_wacc_hi
0, // sub_wacc_lo
0, // sub_vsx1_then_sub_64
0, // sub_pair1_then_sub_64
0, // sub_pair1_then_sub_vsx0
0, // sub_pair1_then_sub_vsx1
0, // sub_pair1_then_sub_vsx1_then_sub_64
0, // sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmrrowp1_then_sub_dmrrow1
0, // sub_wacc_hi_then_sub_dmrrow0
0, // sub_wacc_hi_then_sub_dmrrow1
0, // sub_wacc_hi_then_sub_dmrrowp0
0, // sub_wacc_hi_then_sub_dmrrowp1
0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_dmrrowp0
0, // sub_dmr1_then_sub_dmrrowp1
0, // sub_dmr1_then_sub_wacc_hi
0, // sub_dmr1_then_sub_wacc_lo
0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_gp8_x1_then_sub_32
},
{ // VRRC_with_sub_64_in_SPILLTOVSRRC
0, // sub_32
31, // sub_64 -> VRRC_with_sub_64_in_SPILLTOVSRRC
0, // sub_dmr0
0, // sub_dmr1
0, // sub_dmrrow0
0, // sub_dmrrow1
0, // sub_dmrrowp0
0, // sub_dmrrowp1
0, // sub_eq
0, // sub_gp8_x0
0, // sub_gp8_x1
0, // sub_gt
0, // sub_lt
0, // sub_pair0
0, // sub_pair1
0, // sub_un
0, // sub_vsx0
0, // sub_vsx1
0, // sub_wacc_hi
0, // sub_wacc_lo
0, // sub_vsx1_then_sub_64
0, // sub_pair1_then_sub_64
0, // sub_pair1_then_sub_vsx0
0, // sub_pair1_then_sub_vsx1
0, // sub_pair1_then_sub_vsx1_then_sub_64
0, // sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmrrowp1_then_sub_dmrrow1
0, // sub_wacc_hi_then_sub_dmrrow0
0, // sub_wacc_hi_then_sub_dmrrow1
0, // sub_wacc_hi_then_sub_dmrrowp0
0, // sub_wacc_hi_then_sub_dmrrowp1
0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_dmrrowp0
0, // sub_dmr1_then_sub_dmrrowp1
0, // sub_dmr1_then_sub_wacc_hi
0, // sub_dmr1_then_sub_wacc_lo
0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_gp8_x1_then_sub_32
},
{ // G8pRC
32, // sub_32 -> G8pRC
0, // sub_64
0, // sub_dmr0
0, // sub_dmr1
0, // sub_dmrrow0
0, // sub_dmrrow1
0, // sub_dmrrowp0
0, // sub_dmrrowp1
0, // sub_eq
32, // sub_gp8_x0 -> G8pRC
32, // sub_gp8_x1 -> G8pRC
0, // sub_gt
0, // sub_lt
0, // sub_pair0
0, // sub_pair1
0, // sub_un
0, // sub_vsx0
0, // sub_vsx1
0, // sub_wacc_hi
0, // sub_wacc_lo
0, // sub_vsx1_then_sub_64
0, // sub_pair1_then_sub_64
0, // sub_pair1_then_sub_vsx0
0, // sub_pair1_then_sub_vsx1
0, // sub_pair1_then_sub_vsx1_then_sub_64
0, // sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmrrowp1_then_sub_dmrrow1
0, // sub_wacc_hi_then_sub_dmrrow0
0, // sub_wacc_hi_then_sub_dmrrow1
0, // sub_wacc_hi_then_sub_dmrrowp0
0, // sub_wacc_hi_then_sub_dmrrowp1
0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_dmrrowp0
0, // sub_dmr1_then_sub_dmrrowp1
0, // sub_dmr1_then_sub_wacc_hi
0, // sub_dmr1_then_sub_wacc_lo
0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
32, // sub_gp8_x1_then_sub_32 -> G8pRC
},
{ // G8pRC_with_sub_32_in_GPRC_NOR0
33, // sub_32 -> G8pRC_with_sub_32_in_GPRC_NOR0
0, // sub_64
0, // sub_dmr0
0, // sub_dmr1
0, // sub_dmrrow0
0, // sub_dmrrow1
0, // sub_dmrrowp0
0, // sub_dmrrowp1
0, // sub_eq
33, // sub_gp8_x0 -> G8pRC_with_sub_32_in_GPRC_NOR0
33, // sub_gp8_x1 -> G8pRC_with_sub_32_in_GPRC_NOR0
0, // sub_gt
0, // sub_lt
0, // sub_pair0
0, // sub_pair1
0, // sub_un
0, // sub_vsx0
0, // sub_vsx1
0, // sub_wacc_hi
0, // sub_wacc_lo
0, // sub_vsx1_then_sub_64
0, // sub_pair1_then_sub_64
0, // sub_pair1_then_sub_vsx0
0, // sub_pair1_then_sub_vsx1
0, // sub_pair1_then_sub_vsx1_then_sub_64
0, // sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmrrowp1_then_sub_dmrrow1
0, // sub_wacc_hi_then_sub_dmrrow0
0, // sub_wacc_hi_then_sub_dmrrow1
0, // sub_wacc_hi_then_sub_dmrrowp0
0, // sub_wacc_hi_then_sub_dmrrowp1
0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_dmrrowp0
0, // sub_dmr1_then_sub_dmrrowp1
0, // sub_dmr1_then_sub_wacc_hi
0, // sub_dmr1_then_sub_wacc_lo
0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
33, // sub_gp8_x1_then_sub_32 -> G8pRC_with_sub_32_in_GPRC_NOR0
},
{ // VSLRC_with_sub_64_in_SPILLTOVSRRC
0, // sub_32
34, // sub_64 -> VSLRC_with_sub_64_in_SPILLTOVSRRC
0, // sub_dmr0
0, // sub_dmr1
0, // sub_dmrrow0
0, // sub_dmrrow1
0, // sub_dmrrowp0
0, // sub_dmrrowp1
0, // sub_eq
0, // sub_gp8_x0
0, // sub_gp8_x1
0, // sub_gt
0, // sub_lt
0, // sub_pair0
0, // sub_pair1
0, // sub_un
0, // sub_vsx0
0, // sub_vsx1
0, // sub_wacc_hi
0, // sub_wacc_lo
0, // sub_vsx1_then_sub_64
0, // sub_pair1_then_sub_64
0, // sub_pair1_then_sub_vsx0
0, // sub_pair1_then_sub_vsx1
0, // sub_pair1_then_sub_vsx1_then_sub_64
0, // sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmrrowp1_then_sub_dmrrow1
0, // sub_wacc_hi_then_sub_dmrrow0
0, // sub_wacc_hi_then_sub_dmrrow1
0, // sub_wacc_hi_then_sub_dmrrowp0
0, // sub_wacc_hi_then_sub_dmrrowp1
0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_dmrrowp0
0, // sub_dmr1_then_sub_dmrrowp1
0, // sub_dmr1_then_sub_wacc_hi
0, // sub_dmr1_then_sub_wacc_lo
0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_gp8_x1_then_sub_32
},
{ // DMRROWpRC
0, // sub_32
0, // sub_64
0, // sub_dmr0
0, // sub_dmr1
35, // sub_dmrrow0 -> DMRROWpRC
35, // sub_dmrrow1 -> DMRROWpRC
0, // sub_dmrrowp0
0, // sub_dmrrowp1
0, // sub_eq
0, // sub_gp8_x0
0, // sub_gp8_x1
0, // sub_gt
0, // sub_lt
0, // sub_pair0
0, // sub_pair1
0, // sub_un
0, // sub_vsx0
0, // sub_vsx1
0, // sub_wacc_hi
0, // sub_wacc_lo
0, // sub_vsx1_then_sub_64
0, // sub_pair1_then_sub_64
0, // sub_pair1_then_sub_vsx0
0, // sub_pair1_then_sub_vsx1
0, // sub_pair1_then_sub_vsx1_then_sub_64
0, // sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmrrowp1_then_sub_dmrrow1
0, // sub_wacc_hi_then_sub_dmrrow0
0, // sub_wacc_hi_then_sub_dmrrow1
0, // sub_wacc_hi_then_sub_dmrrowp0
0, // sub_wacc_hi_then_sub_dmrrowp1
0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_dmrrowp0
0, // sub_dmr1_then_sub_dmrrowp1
0, // sub_dmr1_then_sub_wacc_hi
0, // sub_dmr1_then_sub_wacc_lo
0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_gp8_x1_then_sub_32
},
{ // VSRpRC
0, // sub_32
36, // sub_64 -> VSRpRC
0, // sub_dmr0
0, // sub_dmr1
0, // sub_dmrrow0
0, // sub_dmrrow1
0, // sub_dmrrowp0
0, // sub_dmrrowp1
0, // sub_eq
0, // sub_gp8_x0
0, // sub_gp8_x1
0, // sub_gt
0, // sub_lt
0, // sub_pair0
0, // sub_pair1
0, // sub_un
36, // sub_vsx0 -> VSRpRC
36, // sub_vsx1 -> VSRpRC
0, // sub_wacc_hi
0, // sub_wacc_lo
36, // sub_vsx1_then_sub_64 -> VSRpRC
0, // sub_pair1_then_sub_64
0, // sub_pair1_then_sub_vsx0
0, // sub_pair1_then_sub_vsx1
0, // sub_pair1_then_sub_vsx1_then_sub_64
0, // sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmrrowp1_then_sub_dmrrow1
0, // sub_wacc_hi_then_sub_dmrrow0
0, // sub_wacc_hi_then_sub_dmrrow1
0, // sub_wacc_hi_then_sub_dmrrowp0
0, // sub_wacc_hi_then_sub_dmrrowp1
0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_dmrrowp0
0, // sub_dmr1_then_sub_dmrrowp1
0, // sub_dmr1_then_sub_wacc_hi
0, // sub_dmr1_then_sub_wacc_lo
0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_gp8_x1_then_sub_32
},
{ // VSRpRC_with_sub_64_in_SPILLTOVSRRC
0, // sub_32
37, // sub_64 -> VSRpRC_with_sub_64_in_SPILLTOVSRRC
0, // sub_dmr0
0, // sub_dmr1
0, // sub_dmrrow0
0, // sub_dmrrow1
0, // sub_dmrrowp0
0, // sub_dmrrowp1
0, // sub_eq
0, // sub_gp8_x0
0, // sub_gp8_x1
0, // sub_gt
0, // sub_lt
0, // sub_pair0
0, // sub_pair1
0, // sub_un
37, // sub_vsx0 -> VSRpRC_with_sub_64_in_SPILLTOVSRRC
37, // sub_vsx1 -> VSRpRC_with_sub_64_in_SPILLTOVSRRC
0, // sub_wacc_hi
0, // sub_wacc_lo
37, // sub_vsx1_then_sub_64 -> VSRpRC_with_sub_64_in_SPILLTOVSRRC
0, // sub_pair1_then_sub_64
0, // sub_pair1_then_sub_vsx0
0, // sub_pair1_then_sub_vsx1
0, // sub_pair1_then_sub_vsx1_then_sub_64
0, // sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmrrowp1_then_sub_dmrrow1
0, // sub_wacc_hi_then_sub_dmrrow0
0, // sub_wacc_hi_then_sub_dmrrow1
0, // sub_wacc_hi_then_sub_dmrrowp0
0, // sub_wacc_hi_then_sub_dmrrowp1
0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_dmrrowp0
0, // sub_dmr1_then_sub_dmrrowp1
0, // sub_dmr1_then_sub_wacc_hi
0, // sub_dmr1_then_sub_wacc_lo
0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_gp8_x1_then_sub_32
},
{ // VSRpRC_with_sub_64_in_F4RC
0, // sub_32
38, // sub_64 -> VSRpRC_with_sub_64_in_F4RC
0, // sub_dmr0
0, // sub_dmr1
0, // sub_dmrrow0
0, // sub_dmrrow1
0, // sub_dmrrowp0
0, // sub_dmrrowp1
0, // sub_eq
0, // sub_gp8_x0
0, // sub_gp8_x1
0, // sub_gt
0, // sub_lt
0, // sub_pair0
0, // sub_pair1
0, // sub_un
38, // sub_vsx0 -> VSRpRC_with_sub_64_in_F4RC
38, // sub_vsx1 -> VSRpRC_with_sub_64_in_F4RC
0, // sub_wacc_hi
0, // sub_wacc_lo
38, // sub_vsx1_then_sub_64 -> VSRpRC_with_sub_64_in_F4RC
0, // sub_pair1_then_sub_64
0, // sub_pair1_then_sub_vsx0
0, // sub_pair1_then_sub_vsx1
0, // sub_pair1_then_sub_vsx1_then_sub_64
0, // sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmrrowp1_then_sub_dmrrow1
0, // sub_wacc_hi_then_sub_dmrrow0
0, // sub_wacc_hi_then_sub_dmrrow1
0, // sub_wacc_hi_then_sub_dmrrowp0
0, // sub_wacc_hi_then_sub_dmrrowp1
0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_dmrrowp0
0, // sub_dmr1_then_sub_dmrrowp1
0, // sub_dmr1_then_sub_wacc_hi
0, // sub_dmr1_then_sub_wacc_lo
0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_gp8_x1_then_sub_32
},
{ // VSRpRC_with_sub_64_in_VFRC
0, // sub_32
39, // sub_64 -> VSRpRC_with_sub_64_in_VFRC
0, // sub_dmr0
0, // sub_dmr1
0, // sub_dmrrow0
0, // sub_dmrrow1
0, // sub_dmrrowp0
0, // sub_dmrrowp1
0, // sub_eq
0, // sub_gp8_x0
0, // sub_gp8_x1
0, // sub_gt
0, // sub_lt
0, // sub_pair0
0, // sub_pair1
0, // sub_un
39, // sub_vsx0 -> VSRpRC_with_sub_64_in_VFRC
39, // sub_vsx1 -> VSRpRC_with_sub_64_in_VFRC
0, // sub_wacc_hi
0, // sub_wacc_lo
39, // sub_vsx1_then_sub_64 -> VSRpRC_with_sub_64_in_VFRC
0, // sub_pair1_then_sub_64
0, // sub_pair1_then_sub_vsx0
0, // sub_pair1_then_sub_vsx1
0, // sub_pair1_then_sub_vsx1_then_sub_64
0, // sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmrrowp1_then_sub_dmrrow1
0, // sub_wacc_hi_then_sub_dmrrow0
0, // sub_wacc_hi_then_sub_dmrrow1
0, // sub_wacc_hi_then_sub_dmrrowp0
0, // sub_wacc_hi_then_sub_dmrrowp1
0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_dmrrowp0
0, // sub_dmr1_then_sub_dmrrowp1
0, // sub_dmr1_then_sub_wacc_hi
0, // sub_dmr1_then_sub_wacc_lo
0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_gp8_x1_then_sub_32
},
{ // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC
0, // sub_32
40, // sub_64 -> VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC
0, // sub_dmr0
0, // sub_dmr1
0, // sub_dmrrow0
0, // sub_dmrrow1
0, // sub_dmrrowp0
0, // sub_dmrrowp1
0, // sub_eq
0, // sub_gp8_x0
0, // sub_gp8_x1
0, // sub_gt
0, // sub_lt
0, // sub_pair0
0, // sub_pair1
0, // sub_un
40, // sub_vsx0 -> VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC
40, // sub_vsx1 -> VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC
0, // sub_wacc_hi
0, // sub_wacc_lo
40, // sub_vsx1_then_sub_64 -> VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC
0, // sub_pair1_then_sub_64
0, // sub_pair1_then_sub_vsx0
0, // sub_pair1_then_sub_vsx1
0, // sub_pair1_then_sub_vsx1_then_sub_64
0, // sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmrrowp1_then_sub_dmrrow1
0, // sub_wacc_hi_then_sub_dmrrow0
0, // sub_wacc_hi_then_sub_dmrrow1
0, // sub_wacc_hi_then_sub_dmrrowp0
0, // sub_wacc_hi_then_sub_dmrrowp1
0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_dmrrowp0
0, // sub_dmr1_then_sub_dmrrowp1
0, // sub_dmr1_then_sub_wacc_hi
0, // sub_dmr1_then_sub_wacc_lo
0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_gp8_x1_then_sub_32
},
{ // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC
0, // sub_32
41, // sub_64 -> VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC
0, // sub_dmr0
0, // sub_dmr1
0, // sub_dmrrow0
0, // sub_dmrrow1
0, // sub_dmrrowp0
0, // sub_dmrrowp1
0, // sub_eq
0, // sub_gp8_x0
0, // sub_gp8_x1
0, // sub_gt
0, // sub_lt
0, // sub_pair0
0, // sub_pair1
0, // sub_un
41, // sub_vsx0 -> VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC
41, // sub_vsx1 -> VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC
0, // sub_wacc_hi
0, // sub_wacc_lo
41, // sub_vsx1_then_sub_64 -> VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC
0, // sub_pair1_then_sub_64
0, // sub_pair1_then_sub_vsx0
0, // sub_pair1_then_sub_vsx1
0, // sub_pair1_then_sub_vsx1_then_sub_64
0, // sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmrrowp1_then_sub_dmrrow1
0, // sub_wacc_hi_then_sub_dmrrow0
0, // sub_wacc_hi_then_sub_dmrrow1
0, // sub_wacc_hi_then_sub_dmrrowp0
0, // sub_wacc_hi_then_sub_dmrrowp1
0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_dmrrowp0
0, // sub_dmr1_then_sub_dmrrowp1
0, // sub_dmr1_then_sub_wacc_hi
0, // sub_dmr1_then_sub_wacc_lo
0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_gp8_x1_then_sub_32
},
{ // ACCRC
0, // sub_32
42, // sub_64 -> ACCRC
0, // sub_dmr0
0, // sub_dmr1
0, // sub_dmrrow0
0, // sub_dmrrow1
0, // sub_dmrrowp0
0, // sub_dmrrowp1
0, // sub_eq
0, // sub_gp8_x0
0, // sub_gp8_x1
0, // sub_gt
0, // sub_lt
42, // sub_pair0 -> ACCRC
42, // sub_pair1 -> ACCRC
0, // sub_un
42, // sub_vsx0 -> ACCRC
42, // sub_vsx1 -> ACCRC
0, // sub_wacc_hi
0, // sub_wacc_lo
42, // sub_vsx1_then_sub_64 -> ACCRC
42, // sub_pair1_then_sub_64 -> ACCRC
42, // sub_pair1_then_sub_vsx0 -> ACCRC
42, // sub_pair1_then_sub_vsx1 -> ACCRC
42, // sub_pair1_then_sub_vsx1_then_sub_64 -> ACCRC
0, // sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmrrowp1_then_sub_dmrrow1
0, // sub_wacc_hi_then_sub_dmrrow0
0, // sub_wacc_hi_then_sub_dmrrow1
0, // sub_wacc_hi_then_sub_dmrrowp0
0, // sub_wacc_hi_then_sub_dmrrowp1
0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_dmrrowp0
0, // sub_dmr1_then_sub_dmrrowp1
0, // sub_dmr1_then_sub_wacc_hi
0, // sub_dmr1_then_sub_wacc_lo
0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_gp8_x1_then_sub_32
},
{ // UACCRC
0, // sub_32
43, // sub_64 -> UACCRC
0, // sub_dmr0
0, // sub_dmr1
0, // sub_dmrrow0
0, // sub_dmrrow1
0, // sub_dmrrowp0
0, // sub_dmrrowp1
0, // sub_eq
0, // sub_gp8_x0
0, // sub_gp8_x1
0, // sub_gt
0, // sub_lt
43, // sub_pair0 -> UACCRC
43, // sub_pair1 -> UACCRC
0, // sub_un
43, // sub_vsx0 -> UACCRC
43, // sub_vsx1 -> UACCRC
0, // sub_wacc_hi
0, // sub_wacc_lo
43, // sub_vsx1_then_sub_64 -> UACCRC
43, // sub_pair1_then_sub_64 -> UACCRC
43, // sub_pair1_then_sub_vsx0 -> UACCRC
43, // sub_pair1_then_sub_vsx1 -> UACCRC
43, // sub_pair1_then_sub_vsx1_then_sub_64 -> UACCRC
0, // sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmrrowp1_then_sub_dmrrow1
0, // sub_wacc_hi_then_sub_dmrrow0
0, // sub_wacc_hi_then_sub_dmrrow1
0, // sub_wacc_hi_then_sub_dmrrowp0
0, // sub_wacc_hi_then_sub_dmrrowp1
0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_dmrrowp0
0, // sub_dmr1_then_sub_dmrrowp1
0, // sub_dmr1_then_sub_wacc_hi
0, // sub_dmr1_then_sub_wacc_lo
0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_gp8_x1_then_sub_32
},
{ // WACCRC
0, // sub_32
0, // sub_64
0, // sub_dmr0
0, // sub_dmr1
44, // sub_dmrrow0 -> WACCRC
44, // sub_dmrrow1 -> WACCRC
44, // sub_dmrrowp0 -> WACCRC
44, // sub_dmrrowp1 -> WACCRC
0, // sub_eq
0, // sub_gp8_x0
0, // sub_gp8_x1
0, // sub_gt
0, // sub_lt
0, // sub_pair0
0, // sub_pair1
0, // sub_un
0, // sub_vsx0
0, // sub_vsx1
0, // sub_wacc_hi
0, // sub_wacc_lo
0, // sub_vsx1_then_sub_64
0, // sub_pair1_then_sub_64
0, // sub_pair1_then_sub_vsx0
0, // sub_pair1_then_sub_vsx1
0, // sub_pair1_then_sub_vsx1_then_sub_64
44, // sub_dmrrowp1_then_sub_dmrrow0 -> WACCRC
44, // sub_dmrrowp1_then_sub_dmrrow1 -> WACCRC
0, // sub_wacc_hi_then_sub_dmrrow0
0, // sub_wacc_hi_then_sub_dmrrow1
0, // sub_wacc_hi_then_sub_dmrrowp0
0, // sub_wacc_hi_then_sub_dmrrowp1
0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_dmrrowp0
0, // sub_dmr1_then_sub_dmrrowp1
0, // sub_dmr1_then_sub_wacc_hi
0, // sub_dmr1_then_sub_wacc_lo
0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_gp8_x1_then_sub_32
},
{ // WACC_HIRC
0, // sub_32
0, // sub_64
0, // sub_dmr0
0, // sub_dmr1
45, // sub_dmrrow0 -> WACC_HIRC
45, // sub_dmrrow1 -> WACC_HIRC
45, // sub_dmrrowp0 -> WACC_HIRC
45, // sub_dmrrowp1 -> WACC_HIRC
0, // sub_eq
0, // sub_gp8_x0
0, // sub_gp8_x1
0, // sub_gt
0, // sub_lt
0, // sub_pair0
0, // sub_pair1
0, // sub_un
0, // sub_vsx0
0, // sub_vsx1
0, // sub_wacc_hi
0, // sub_wacc_lo
0, // sub_vsx1_then_sub_64
0, // sub_pair1_then_sub_64
0, // sub_pair1_then_sub_vsx0
0, // sub_pair1_then_sub_vsx1
0, // sub_pair1_then_sub_vsx1_then_sub_64
45, // sub_dmrrowp1_then_sub_dmrrow0 -> WACC_HIRC
45, // sub_dmrrowp1_then_sub_dmrrow1 -> WACC_HIRC
0, // sub_wacc_hi_then_sub_dmrrow0
0, // sub_wacc_hi_then_sub_dmrrow1
0, // sub_wacc_hi_then_sub_dmrrowp0
0, // sub_wacc_hi_then_sub_dmrrowp1
0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_dmrrowp0
0, // sub_dmr1_then_sub_dmrrowp1
0, // sub_dmr1_then_sub_wacc_hi
0, // sub_dmr1_then_sub_wacc_lo
0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_gp8_x1_then_sub_32
},
{ // ACCRC_with_sub_64_in_SPILLTOVSRRC
0, // sub_32
46, // sub_64 -> ACCRC_with_sub_64_in_SPILLTOVSRRC
0, // sub_dmr0
0, // sub_dmr1
0, // sub_dmrrow0
0, // sub_dmrrow1
0, // sub_dmrrowp0
0, // sub_dmrrowp1
0, // sub_eq
0, // sub_gp8_x0
0, // sub_gp8_x1
0, // sub_gt
0, // sub_lt
46, // sub_pair0 -> ACCRC_with_sub_64_in_SPILLTOVSRRC
46, // sub_pair1 -> ACCRC_with_sub_64_in_SPILLTOVSRRC
0, // sub_un
46, // sub_vsx0 -> ACCRC_with_sub_64_in_SPILLTOVSRRC
46, // sub_vsx1 -> ACCRC_with_sub_64_in_SPILLTOVSRRC
0, // sub_wacc_hi
0, // sub_wacc_lo
46, // sub_vsx1_then_sub_64 -> ACCRC_with_sub_64_in_SPILLTOVSRRC
46, // sub_pair1_then_sub_64 -> ACCRC_with_sub_64_in_SPILLTOVSRRC
46, // sub_pair1_then_sub_vsx0 -> ACCRC_with_sub_64_in_SPILLTOVSRRC
46, // sub_pair1_then_sub_vsx1 -> ACCRC_with_sub_64_in_SPILLTOVSRRC
46, // sub_pair1_then_sub_vsx1_then_sub_64 -> ACCRC_with_sub_64_in_SPILLTOVSRRC
0, // sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmrrowp1_then_sub_dmrrow1
0, // sub_wacc_hi_then_sub_dmrrow0
0, // sub_wacc_hi_then_sub_dmrrow1
0, // sub_wacc_hi_then_sub_dmrrowp0
0, // sub_wacc_hi_then_sub_dmrrowp1
0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_dmrrowp0
0, // sub_dmr1_then_sub_dmrrowp1
0, // sub_dmr1_then_sub_wacc_hi
0, // sub_dmr1_then_sub_wacc_lo
0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_gp8_x1_then_sub_32
},
{ // UACCRC_with_sub_64_in_SPILLTOVSRRC
0, // sub_32
47, // sub_64 -> UACCRC_with_sub_64_in_SPILLTOVSRRC
0, // sub_dmr0
0, // sub_dmr1
0, // sub_dmrrow0
0, // sub_dmrrow1
0, // sub_dmrrowp0
0, // sub_dmrrowp1
0, // sub_eq
0, // sub_gp8_x0
0, // sub_gp8_x1
0, // sub_gt
0, // sub_lt
47, // sub_pair0 -> UACCRC_with_sub_64_in_SPILLTOVSRRC
47, // sub_pair1 -> UACCRC_with_sub_64_in_SPILLTOVSRRC
0, // sub_un
47, // sub_vsx0 -> UACCRC_with_sub_64_in_SPILLTOVSRRC
47, // sub_vsx1 -> UACCRC_with_sub_64_in_SPILLTOVSRRC
0, // sub_wacc_hi
0, // sub_wacc_lo
47, // sub_vsx1_then_sub_64 -> UACCRC_with_sub_64_in_SPILLTOVSRRC
47, // sub_pair1_then_sub_64 -> UACCRC_with_sub_64_in_SPILLTOVSRRC
47, // sub_pair1_then_sub_vsx0 -> UACCRC_with_sub_64_in_SPILLTOVSRRC
47, // sub_pair1_then_sub_vsx1 -> UACCRC_with_sub_64_in_SPILLTOVSRRC
47, // sub_pair1_then_sub_vsx1_then_sub_64 -> UACCRC_with_sub_64_in_SPILLTOVSRRC
0, // sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmrrowp1_then_sub_dmrrow1
0, // sub_wacc_hi_then_sub_dmrrow0
0, // sub_wacc_hi_then_sub_dmrrow1
0, // sub_wacc_hi_then_sub_dmrrowp0
0, // sub_wacc_hi_then_sub_dmrrowp1
0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_dmrrowp0
0, // sub_dmr1_then_sub_dmrrowp1
0, // sub_dmr1_then_sub_wacc_hi
0, // sub_dmr1_then_sub_wacc_lo
0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_gp8_x1_then_sub_32
},
{ // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
0, // sub_32
48, // sub_64 -> ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
0, // sub_dmr0
0, // sub_dmr1
0, // sub_dmrrow0
0, // sub_dmrrow1
0, // sub_dmrrowp0
0, // sub_dmrrowp1
0, // sub_eq
0, // sub_gp8_x0
0, // sub_gp8_x1
0, // sub_gt
0, // sub_lt
48, // sub_pair0 -> ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
48, // sub_pair1 -> ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
0, // sub_un
48, // sub_vsx0 -> ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
48, // sub_vsx1 -> ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
0, // sub_wacc_hi
0, // sub_wacc_lo
48, // sub_vsx1_then_sub_64 -> ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
48, // sub_pair1_then_sub_64 -> ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
48, // sub_pair1_then_sub_vsx0 -> ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
48, // sub_pair1_then_sub_vsx1 -> ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
48, // sub_pair1_then_sub_vsx1_then_sub_64 -> ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
0, // sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmrrowp1_then_sub_dmrrow1
0, // sub_wacc_hi_then_sub_dmrrow0
0, // sub_wacc_hi_then_sub_dmrrow1
0, // sub_wacc_hi_then_sub_dmrrowp0
0, // sub_wacc_hi_then_sub_dmrrowp1
0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_dmrrowp0
0, // sub_dmr1_then_sub_dmrrowp1
0, // sub_dmr1_then_sub_wacc_hi
0, // sub_dmr1_then_sub_wacc_lo
0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_gp8_x1_then_sub_32
},
{ // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
0, // sub_32
49, // sub_64 -> UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
0, // sub_dmr0
0, // sub_dmr1
0, // sub_dmrrow0
0, // sub_dmrrow1
0, // sub_dmrrowp0
0, // sub_dmrrowp1
0, // sub_eq
0, // sub_gp8_x0
0, // sub_gp8_x1
0, // sub_gt
0, // sub_lt
49, // sub_pair0 -> UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
49, // sub_pair1 -> UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
0, // sub_un
49, // sub_vsx0 -> UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
49, // sub_vsx1 -> UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
0, // sub_wacc_hi
0, // sub_wacc_lo
49, // sub_vsx1_then_sub_64 -> UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
49, // sub_pair1_then_sub_64 -> UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
49, // sub_pair1_then_sub_vsx0 -> UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
49, // sub_pair1_then_sub_vsx1 -> UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
49, // sub_pair1_then_sub_vsx1_then_sub_64 -> UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
0, // sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmrrowp1_then_sub_dmrrow1
0, // sub_wacc_hi_then_sub_dmrrow0
0, // sub_wacc_hi_then_sub_dmrrow1
0, // sub_wacc_hi_then_sub_dmrrowp0
0, // sub_wacc_hi_then_sub_dmrrowp1
0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_dmrrowp0
0, // sub_dmr1_then_sub_dmrrowp1
0, // sub_dmr1_then_sub_wacc_hi
0, // sub_dmr1_then_sub_wacc_lo
0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_gp8_x1_then_sub_32
},
{ // DMRRC
0, // sub_32
0, // sub_64
0, // sub_dmr0
0, // sub_dmr1
50, // sub_dmrrow0 -> DMRRC
50, // sub_dmrrow1 -> DMRRC
50, // sub_dmrrowp0 -> DMRRC
50, // sub_dmrrowp1 -> DMRRC
0, // sub_eq
0, // sub_gp8_x0
0, // sub_gp8_x1
0, // sub_gt
0, // sub_lt
0, // sub_pair0
0, // sub_pair1
0, // sub_un
0, // sub_vsx0
0, // sub_vsx1
50, // sub_wacc_hi -> DMRRC
50, // sub_wacc_lo -> DMRRC
0, // sub_vsx1_then_sub_64
0, // sub_pair1_then_sub_64
0, // sub_pair1_then_sub_vsx0
0, // sub_pair1_then_sub_vsx1
0, // sub_pair1_then_sub_vsx1_then_sub_64
50, // sub_dmrrowp1_then_sub_dmrrow0 -> DMRRC
50, // sub_dmrrowp1_then_sub_dmrrow1 -> DMRRC
50, // sub_wacc_hi_then_sub_dmrrow0 -> DMRRC
50, // sub_wacc_hi_then_sub_dmrrow1 -> DMRRC
50, // sub_wacc_hi_then_sub_dmrrowp0 -> DMRRC
50, // sub_wacc_hi_then_sub_dmrrowp1 -> DMRRC
50, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0 -> DMRRC
50, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1 -> DMRRC
0, // sub_dmr1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_dmrrowp0
0, // sub_dmr1_then_sub_dmrrowp1
0, // sub_dmr1_then_sub_wacc_hi
0, // sub_dmr1_then_sub_wacc_lo
0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // sub_gp8_x1_then_sub_32
},
{ // DMRpRC
0, // sub_32
0, // sub_64
51, // sub_dmr0 -> DMRpRC
51, // sub_dmr1 -> DMRpRC
51, // sub_dmrrow0 -> DMRpRC
51, // sub_dmrrow1 -> DMRpRC
51, // sub_dmrrowp0 -> DMRpRC
51, // sub_dmrrowp1 -> DMRpRC
0, // sub_eq
0, // sub_gp8_x0
0, // sub_gp8_x1
0, // sub_gt
0, // sub_lt
0, // sub_pair0
0, // sub_pair1
0, // sub_un
0, // sub_vsx0
0, // sub_vsx1
51, // sub_wacc_hi -> DMRpRC
51, // sub_wacc_lo -> DMRpRC
0, // sub_vsx1_then_sub_64
0, // sub_pair1_then_sub_64
0, // sub_pair1_then_sub_vsx0
0, // sub_pair1_then_sub_vsx1
0, // sub_pair1_then_sub_vsx1_then_sub_64
51, // sub_dmrrowp1_then_sub_dmrrow0 -> DMRpRC
51, // sub_dmrrowp1_then_sub_dmrrow1 -> DMRpRC
51, // sub_wacc_hi_then_sub_dmrrow0 -> DMRpRC
51, // sub_wacc_hi_then_sub_dmrrow1 -> DMRpRC
51, // sub_wacc_hi_then_sub_dmrrowp0 -> DMRpRC
51, // sub_wacc_hi_then_sub_dmrrowp1 -> DMRpRC
51, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0 -> DMRpRC
51, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1 -> DMRpRC
51, // sub_dmr1_then_sub_dmrrow0 -> DMRpRC
51, // sub_dmr1_then_sub_dmrrow1 -> DMRpRC
51, // sub_dmr1_then_sub_dmrrowp0 -> DMRpRC
51, // sub_dmr1_then_sub_dmrrowp1 -> DMRpRC
51, // sub_dmr1_then_sub_wacc_hi -> DMRpRC
51, // sub_dmr1_then_sub_wacc_lo -> DMRpRC
51, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0 -> DMRpRC
51, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1 -> DMRpRC
51, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0 -> DMRpRC
51, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1 -> DMRpRC
51, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0 -> DMRpRC
51, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1 -> DMRpRC
51, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0 -> DMRpRC
51, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1 -> DMRpRC
0, // sub_gp8_x1_then_sub_32
},
};
assert(RC && "Missing regclass");
if (!Idx) return RC;
--Idx;
assert(Idx < 48 && "Bad subreg");
unsigned TV = Table[RC->getID()][Idx];
return TV ? getRegClass(TV - 1) : nullptr;
}
const TargetRegisterClass *PPCGenRegisterInfo::getSubRegisterClass(const TargetRegisterClass *RC, unsigned Idx) const {
static const uint8_t Table[51][48] = {
{ // VSSRC
0, // VSSRC:sub_32
0, // VSSRC:sub_64
0, // VSSRC:sub_dmr0
0, // VSSRC:sub_dmr1
0, // VSSRC:sub_dmrrow0
0, // VSSRC:sub_dmrrow1
0, // VSSRC:sub_dmrrowp0
0, // VSSRC:sub_dmrrowp1
0, // VSSRC:sub_eq
0, // VSSRC:sub_gp8_x0
0, // VSSRC:sub_gp8_x1
0, // VSSRC:sub_gt
0, // VSSRC:sub_lt
0, // VSSRC:sub_pair0
0, // VSSRC:sub_pair1
0, // VSSRC:sub_un
0, // VSSRC:sub_vsx0
0, // VSSRC:sub_vsx1
0, // VSSRC:sub_wacc_hi
0, // VSSRC:sub_wacc_lo
0, // VSSRC:sub_vsx1_then_sub_64
0, // VSSRC:sub_pair1_then_sub_64
0, // VSSRC:sub_pair1_then_sub_vsx0
0, // VSSRC:sub_pair1_then_sub_vsx1
0, // VSSRC:sub_pair1_then_sub_vsx1_then_sub_64
0, // VSSRC:sub_dmrrowp1_then_sub_dmrrow0
0, // VSSRC:sub_dmrrowp1_then_sub_dmrrow1
0, // VSSRC:sub_wacc_hi_then_sub_dmrrow0
0, // VSSRC:sub_wacc_hi_then_sub_dmrrow1
0, // VSSRC:sub_wacc_hi_then_sub_dmrrowp0
0, // VSSRC:sub_wacc_hi_then_sub_dmrrowp1
0, // VSSRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // VSSRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // VSSRC:sub_dmr1_then_sub_dmrrow0
0, // VSSRC:sub_dmr1_then_sub_dmrrow1
0, // VSSRC:sub_dmr1_then_sub_dmrrowp0
0, // VSSRC:sub_dmr1_then_sub_dmrrowp1
0, // VSSRC:sub_dmr1_then_sub_wacc_hi
0, // VSSRC:sub_dmr1_then_sub_wacc_lo
0, // VSSRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
0, // VSSRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
0, // VSSRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
0, // VSSRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
0, // VSSRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
0, // VSSRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
0, // VSSRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // VSSRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // VSSRC:sub_gp8_x1_then_sub_32
},
{ // GPRC
0, // GPRC:sub_32
0, // GPRC:sub_64
0, // GPRC:sub_dmr0
0, // GPRC:sub_dmr1
0, // GPRC:sub_dmrrow0
0, // GPRC:sub_dmrrow1
0, // GPRC:sub_dmrrowp0
0, // GPRC:sub_dmrrowp1
0, // GPRC:sub_eq
0, // GPRC:sub_gp8_x0
0, // GPRC:sub_gp8_x1
0, // GPRC:sub_gt
0, // GPRC:sub_lt
0, // GPRC:sub_pair0
0, // GPRC:sub_pair1
0, // GPRC:sub_un
0, // GPRC:sub_vsx0
0, // GPRC:sub_vsx1
0, // GPRC:sub_wacc_hi
0, // GPRC:sub_wacc_lo
0, // GPRC:sub_vsx1_then_sub_64
0, // GPRC:sub_pair1_then_sub_64
0, // GPRC:sub_pair1_then_sub_vsx0
0, // GPRC:sub_pair1_then_sub_vsx1
0, // GPRC:sub_pair1_then_sub_vsx1_then_sub_64
0, // GPRC:sub_dmrrowp1_then_sub_dmrrow0
0, // GPRC:sub_dmrrowp1_then_sub_dmrrow1
0, // GPRC:sub_wacc_hi_then_sub_dmrrow0
0, // GPRC:sub_wacc_hi_then_sub_dmrrow1
0, // GPRC:sub_wacc_hi_then_sub_dmrrowp0
0, // GPRC:sub_wacc_hi_then_sub_dmrrowp1
0, // GPRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // GPRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // GPRC:sub_dmr1_then_sub_dmrrow0
0, // GPRC:sub_dmr1_then_sub_dmrrow1
0, // GPRC:sub_dmr1_then_sub_dmrrowp0
0, // GPRC:sub_dmr1_then_sub_dmrrowp1
0, // GPRC:sub_dmr1_then_sub_wacc_hi
0, // GPRC:sub_dmr1_then_sub_wacc_lo
0, // GPRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
0, // GPRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
0, // GPRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
0, // GPRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
0, // GPRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
0, // GPRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
0, // GPRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // GPRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // GPRC:sub_gp8_x1_then_sub_32
},
{ // GPRC_NOR0
0, // GPRC_NOR0:sub_32
0, // GPRC_NOR0:sub_64
0, // GPRC_NOR0:sub_dmr0
0, // GPRC_NOR0:sub_dmr1
0, // GPRC_NOR0:sub_dmrrow0
0, // GPRC_NOR0:sub_dmrrow1
0, // GPRC_NOR0:sub_dmrrowp0
0, // GPRC_NOR0:sub_dmrrowp1
0, // GPRC_NOR0:sub_eq
0, // GPRC_NOR0:sub_gp8_x0
0, // GPRC_NOR0:sub_gp8_x1
0, // GPRC_NOR0:sub_gt
0, // GPRC_NOR0:sub_lt
0, // GPRC_NOR0:sub_pair0
0, // GPRC_NOR0:sub_pair1
0, // GPRC_NOR0:sub_un
0, // GPRC_NOR0:sub_vsx0
0, // GPRC_NOR0:sub_vsx1
0, // GPRC_NOR0:sub_wacc_hi
0, // GPRC_NOR0:sub_wacc_lo
0, // GPRC_NOR0:sub_vsx1_then_sub_64
0, // GPRC_NOR0:sub_pair1_then_sub_64
0, // GPRC_NOR0:sub_pair1_then_sub_vsx0
0, // GPRC_NOR0:sub_pair1_then_sub_vsx1
0, // GPRC_NOR0:sub_pair1_then_sub_vsx1_then_sub_64
0, // GPRC_NOR0:sub_dmrrowp1_then_sub_dmrrow0
0, // GPRC_NOR0:sub_dmrrowp1_then_sub_dmrrow1
0, // GPRC_NOR0:sub_wacc_hi_then_sub_dmrrow0
0, // GPRC_NOR0:sub_wacc_hi_then_sub_dmrrow1
0, // GPRC_NOR0:sub_wacc_hi_then_sub_dmrrowp0
0, // GPRC_NOR0:sub_wacc_hi_then_sub_dmrrowp1
0, // GPRC_NOR0:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // GPRC_NOR0:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // GPRC_NOR0:sub_dmr1_then_sub_dmrrow0
0, // GPRC_NOR0:sub_dmr1_then_sub_dmrrow1
0, // GPRC_NOR0:sub_dmr1_then_sub_dmrrowp0
0, // GPRC_NOR0:sub_dmr1_then_sub_dmrrowp1
0, // GPRC_NOR0:sub_dmr1_then_sub_wacc_hi
0, // GPRC_NOR0:sub_dmr1_then_sub_wacc_lo
0, // GPRC_NOR0:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
0, // GPRC_NOR0:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
0, // GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
0, // GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
0, // GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
0, // GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
0, // GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // GPRC_NOR0:sub_gp8_x1_then_sub_32
},
{ // GPRC_and_GPRC_NOR0
0, // GPRC_and_GPRC_NOR0:sub_32
0, // GPRC_and_GPRC_NOR0:sub_64
0, // GPRC_and_GPRC_NOR0:sub_dmr0
0, // GPRC_and_GPRC_NOR0:sub_dmr1
0, // GPRC_and_GPRC_NOR0:sub_dmrrow0
0, // GPRC_and_GPRC_NOR0:sub_dmrrow1
0, // GPRC_and_GPRC_NOR0:sub_dmrrowp0
0, // GPRC_and_GPRC_NOR0:sub_dmrrowp1
0, // GPRC_and_GPRC_NOR0:sub_eq
0, // GPRC_and_GPRC_NOR0:sub_gp8_x0
0, // GPRC_and_GPRC_NOR0:sub_gp8_x1
0, // GPRC_and_GPRC_NOR0:sub_gt
0, // GPRC_and_GPRC_NOR0:sub_lt
0, // GPRC_and_GPRC_NOR0:sub_pair0
0, // GPRC_and_GPRC_NOR0:sub_pair1
0, // GPRC_and_GPRC_NOR0:sub_un
0, // GPRC_and_GPRC_NOR0:sub_vsx0
0, // GPRC_and_GPRC_NOR0:sub_vsx1
0, // GPRC_and_GPRC_NOR0:sub_wacc_hi
0, // GPRC_and_GPRC_NOR0:sub_wacc_lo
0, // GPRC_and_GPRC_NOR0:sub_vsx1_then_sub_64
0, // GPRC_and_GPRC_NOR0:sub_pair1_then_sub_64
0, // GPRC_and_GPRC_NOR0:sub_pair1_then_sub_vsx0
0, // GPRC_and_GPRC_NOR0:sub_pair1_then_sub_vsx1
0, // GPRC_and_GPRC_NOR0:sub_pair1_then_sub_vsx1_then_sub_64
0, // GPRC_and_GPRC_NOR0:sub_dmrrowp1_then_sub_dmrrow0
0, // GPRC_and_GPRC_NOR0:sub_dmrrowp1_then_sub_dmrrow1
0, // GPRC_and_GPRC_NOR0:sub_wacc_hi_then_sub_dmrrow0
0, // GPRC_and_GPRC_NOR0:sub_wacc_hi_then_sub_dmrrow1
0, // GPRC_and_GPRC_NOR0:sub_wacc_hi_then_sub_dmrrowp0
0, // GPRC_and_GPRC_NOR0:sub_wacc_hi_then_sub_dmrrowp1
0, // GPRC_and_GPRC_NOR0:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // GPRC_and_GPRC_NOR0:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // GPRC_and_GPRC_NOR0:sub_dmr1_then_sub_dmrrow0
0, // GPRC_and_GPRC_NOR0:sub_dmr1_then_sub_dmrrow1
0, // GPRC_and_GPRC_NOR0:sub_dmr1_then_sub_dmrrowp0
0, // GPRC_and_GPRC_NOR0:sub_dmr1_then_sub_dmrrowp1
0, // GPRC_and_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi
0, // GPRC_and_GPRC_NOR0:sub_dmr1_then_sub_wacc_lo
0, // GPRC_and_GPRC_NOR0:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
0, // GPRC_and_GPRC_NOR0:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
0, // GPRC_and_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
0, // GPRC_and_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
0, // GPRC_and_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
0, // GPRC_and_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
0, // GPRC_and_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // GPRC_and_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // GPRC_and_GPRC_NOR0:sub_gp8_x1_then_sub_32
},
{ // CRBITRC
0, // CRBITRC:sub_32
0, // CRBITRC:sub_64
0, // CRBITRC:sub_dmr0
0, // CRBITRC:sub_dmr1
0, // CRBITRC:sub_dmrrow0
0, // CRBITRC:sub_dmrrow1
0, // CRBITRC:sub_dmrrowp0
0, // CRBITRC:sub_dmrrowp1
0, // CRBITRC:sub_eq
0, // CRBITRC:sub_gp8_x0
0, // CRBITRC:sub_gp8_x1
0, // CRBITRC:sub_gt
0, // CRBITRC:sub_lt
0, // CRBITRC:sub_pair0
0, // CRBITRC:sub_pair1
0, // CRBITRC:sub_un
0, // CRBITRC:sub_vsx0
0, // CRBITRC:sub_vsx1
0, // CRBITRC:sub_wacc_hi
0, // CRBITRC:sub_wacc_lo
0, // CRBITRC:sub_vsx1_then_sub_64
0, // CRBITRC:sub_pair1_then_sub_64
0, // CRBITRC:sub_pair1_then_sub_vsx0
0, // CRBITRC:sub_pair1_then_sub_vsx1
0, // CRBITRC:sub_pair1_then_sub_vsx1_then_sub_64
0, // CRBITRC:sub_dmrrowp1_then_sub_dmrrow0
0, // CRBITRC:sub_dmrrowp1_then_sub_dmrrow1
0, // CRBITRC:sub_wacc_hi_then_sub_dmrrow0
0, // CRBITRC:sub_wacc_hi_then_sub_dmrrow1
0, // CRBITRC:sub_wacc_hi_then_sub_dmrrowp0
0, // CRBITRC:sub_wacc_hi_then_sub_dmrrowp1
0, // CRBITRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // CRBITRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // CRBITRC:sub_dmr1_then_sub_dmrrow0
0, // CRBITRC:sub_dmr1_then_sub_dmrrow1
0, // CRBITRC:sub_dmr1_then_sub_dmrrowp0
0, // CRBITRC:sub_dmr1_then_sub_dmrrowp1
0, // CRBITRC:sub_dmr1_then_sub_wacc_hi
0, // CRBITRC:sub_dmr1_then_sub_wacc_lo
0, // CRBITRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
0, // CRBITRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
0, // CRBITRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
0, // CRBITRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
0, // CRBITRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
0, // CRBITRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
0, // CRBITRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // CRBITRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // CRBITRC:sub_gp8_x1_then_sub_32
},
{ // F4RC
0, // F4RC:sub_32
0, // F4RC:sub_64
0, // F4RC:sub_dmr0
0, // F4RC:sub_dmr1
0, // F4RC:sub_dmrrow0
0, // F4RC:sub_dmrrow1
0, // F4RC:sub_dmrrowp0
0, // F4RC:sub_dmrrowp1
0, // F4RC:sub_eq
0, // F4RC:sub_gp8_x0
0, // F4RC:sub_gp8_x1
0, // F4RC:sub_gt
0, // F4RC:sub_lt
0, // F4RC:sub_pair0
0, // F4RC:sub_pair1
0, // F4RC:sub_un
0, // F4RC:sub_vsx0
0, // F4RC:sub_vsx1
0, // F4RC:sub_wacc_hi
0, // F4RC:sub_wacc_lo
0, // F4RC:sub_vsx1_then_sub_64
0, // F4RC:sub_pair1_then_sub_64
0, // F4RC:sub_pair1_then_sub_vsx0
0, // F4RC:sub_pair1_then_sub_vsx1
0, // F4RC:sub_pair1_then_sub_vsx1_then_sub_64
0, // F4RC:sub_dmrrowp1_then_sub_dmrrow0
0, // F4RC:sub_dmrrowp1_then_sub_dmrrow1
0, // F4RC:sub_wacc_hi_then_sub_dmrrow0
0, // F4RC:sub_wacc_hi_then_sub_dmrrow1
0, // F4RC:sub_wacc_hi_then_sub_dmrrowp0
0, // F4RC:sub_wacc_hi_then_sub_dmrrowp1
0, // F4RC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // F4RC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // F4RC:sub_dmr1_then_sub_dmrrow0
0, // F4RC:sub_dmr1_then_sub_dmrrow1
0, // F4RC:sub_dmr1_then_sub_dmrrowp0
0, // F4RC:sub_dmr1_then_sub_dmrrowp1
0, // F4RC:sub_dmr1_then_sub_wacc_hi
0, // F4RC:sub_dmr1_then_sub_wacc_lo
0, // F4RC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
0, // F4RC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
0, // F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
0, // F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
0, // F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
0, // F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
0, // F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // F4RC:sub_gp8_x1_then_sub_32
},
{ // CRRC
0, // CRRC:sub_32
0, // CRRC:sub_64
0, // CRRC:sub_dmr0
0, // CRRC:sub_dmr1
0, // CRRC:sub_dmrrow0
0, // CRRC:sub_dmrrow1
0, // CRRC:sub_dmrrowp0
0, // CRRC:sub_dmrrowp1
5, // CRRC:sub_eq -> CRBITRC
0, // CRRC:sub_gp8_x0
0, // CRRC:sub_gp8_x1
5, // CRRC:sub_gt -> CRBITRC
5, // CRRC:sub_lt -> CRBITRC
0, // CRRC:sub_pair0
0, // CRRC:sub_pair1
5, // CRRC:sub_un -> CRBITRC
0, // CRRC:sub_vsx0
0, // CRRC:sub_vsx1
0, // CRRC:sub_wacc_hi
0, // CRRC:sub_wacc_lo
0, // CRRC:sub_vsx1_then_sub_64
0, // CRRC:sub_pair1_then_sub_64
0, // CRRC:sub_pair1_then_sub_vsx0
0, // CRRC:sub_pair1_then_sub_vsx1
0, // CRRC:sub_pair1_then_sub_vsx1_then_sub_64
0, // CRRC:sub_dmrrowp1_then_sub_dmrrow0
0, // CRRC:sub_dmrrowp1_then_sub_dmrrow1
0, // CRRC:sub_wacc_hi_then_sub_dmrrow0
0, // CRRC:sub_wacc_hi_then_sub_dmrrow1
0, // CRRC:sub_wacc_hi_then_sub_dmrrowp0
0, // CRRC:sub_wacc_hi_then_sub_dmrrowp1
0, // CRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // CRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // CRRC:sub_dmr1_then_sub_dmrrow0
0, // CRRC:sub_dmr1_then_sub_dmrrow1
0, // CRRC:sub_dmr1_then_sub_dmrrowp0
0, // CRRC:sub_dmr1_then_sub_dmrrowp1
0, // CRRC:sub_dmr1_then_sub_wacc_hi
0, // CRRC:sub_dmr1_then_sub_wacc_lo
0, // CRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
0, // CRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
0, // CRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
0, // CRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
0, // CRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
0, // CRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
0, // CRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // CRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // CRRC:sub_gp8_x1_then_sub_32
},
{ // CARRYRC
0, // CARRYRC:sub_32
0, // CARRYRC:sub_64
0, // CARRYRC:sub_dmr0
0, // CARRYRC:sub_dmr1
0, // CARRYRC:sub_dmrrow0
0, // CARRYRC:sub_dmrrow1
0, // CARRYRC:sub_dmrrowp0
0, // CARRYRC:sub_dmrrowp1
0, // CARRYRC:sub_eq
0, // CARRYRC:sub_gp8_x0
0, // CARRYRC:sub_gp8_x1
0, // CARRYRC:sub_gt
0, // CARRYRC:sub_lt
0, // CARRYRC:sub_pair0
0, // CARRYRC:sub_pair1
0, // CARRYRC:sub_un
0, // CARRYRC:sub_vsx0
0, // CARRYRC:sub_vsx1
0, // CARRYRC:sub_wacc_hi
0, // CARRYRC:sub_wacc_lo
0, // CARRYRC:sub_vsx1_then_sub_64
0, // CARRYRC:sub_pair1_then_sub_64
0, // CARRYRC:sub_pair1_then_sub_vsx0
0, // CARRYRC:sub_pair1_then_sub_vsx1
0, // CARRYRC:sub_pair1_then_sub_vsx1_then_sub_64
0, // CARRYRC:sub_dmrrowp1_then_sub_dmrrow0
0, // CARRYRC:sub_dmrrowp1_then_sub_dmrrow1
0, // CARRYRC:sub_wacc_hi_then_sub_dmrrow0
0, // CARRYRC:sub_wacc_hi_then_sub_dmrrow1
0, // CARRYRC:sub_wacc_hi_then_sub_dmrrowp0
0, // CARRYRC:sub_wacc_hi_then_sub_dmrrowp1
0, // CARRYRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // CARRYRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // CARRYRC:sub_dmr1_then_sub_dmrrow0
0, // CARRYRC:sub_dmr1_then_sub_dmrrow1
0, // CARRYRC:sub_dmr1_then_sub_dmrrowp0
0, // CARRYRC:sub_dmr1_then_sub_dmrrowp1
0, // CARRYRC:sub_dmr1_then_sub_wacc_hi
0, // CARRYRC:sub_dmr1_then_sub_wacc_lo
0, // CARRYRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
0, // CARRYRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
0, // CARRYRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
0, // CARRYRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
0, // CARRYRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
0, // CARRYRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
0, // CARRYRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // CARRYRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // CARRYRC:sub_gp8_x1_then_sub_32
},
{ // CTRRC
0, // CTRRC:sub_32
0, // CTRRC:sub_64
0, // CTRRC:sub_dmr0
0, // CTRRC:sub_dmr1
0, // CTRRC:sub_dmrrow0
0, // CTRRC:sub_dmrrow1
0, // CTRRC:sub_dmrrowp0
0, // CTRRC:sub_dmrrowp1
0, // CTRRC:sub_eq
0, // CTRRC:sub_gp8_x0
0, // CTRRC:sub_gp8_x1
0, // CTRRC:sub_gt
0, // CTRRC:sub_lt
0, // CTRRC:sub_pair0
0, // CTRRC:sub_pair1
0, // CTRRC:sub_un
0, // CTRRC:sub_vsx0
0, // CTRRC:sub_vsx1
0, // CTRRC:sub_wacc_hi
0, // CTRRC:sub_wacc_lo
0, // CTRRC:sub_vsx1_then_sub_64
0, // CTRRC:sub_pair1_then_sub_64
0, // CTRRC:sub_pair1_then_sub_vsx0
0, // CTRRC:sub_pair1_then_sub_vsx1
0, // CTRRC:sub_pair1_then_sub_vsx1_then_sub_64
0, // CTRRC:sub_dmrrowp1_then_sub_dmrrow0
0, // CTRRC:sub_dmrrowp1_then_sub_dmrrow1
0, // CTRRC:sub_wacc_hi_then_sub_dmrrow0
0, // CTRRC:sub_wacc_hi_then_sub_dmrrow1
0, // CTRRC:sub_wacc_hi_then_sub_dmrrowp0
0, // CTRRC:sub_wacc_hi_then_sub_dmrrowp1
0, // CTRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // CTRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // CTRRC:sub_dmr1_then_sub_dmrrow0
0, // CTRRC:sub_dmr1_then_sub_dmrrow1
0, // CTRRC:sub_dmr1_then_sub_dmrrowp0
0, // CTRRC:sub_dmr1_then_sub_dmrrowp1
0, // CTRRC:sub_dmr1_then_sub_wacc_hi
0, // CTRRC:sub_dmr1_then_sub_wacc_lo
0, // CTRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
0, // CTRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
0, // CTRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
0, // CTRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
0, // CTRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
0, // CTRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
0, // CTRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // CTRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // CTRRC:sub_gp8_x1_then_sub_32
},
{ // LRRC
0, // LRRC:sub_32
0, // LRRC:sub_64
0, // LRRC:sub_dmr0
0, // LRRC:sub_dmr1
0, // LRRC:sub_dmrrow0
0, // LRRC:sub_dmrrow1
0, // LRRC:sub_dmrrowp0
0, // LRRC:sub_dmrrowp1
0, // LRRC:sub_eq
0, // LRRC:sub_gp8_x0
0, // LRRC:sub_gp8_x1
0, // LRRC:sub_gt
0, // LRRC:sub_lt
0, // LRRC:sub_pair0
0, // LRRC:sub_pair1
0, // LRRC:sub_un
0, // LRRC:sub_vsx0
0, // LRRC:sub_vsx1
0, // LRRC:sub_wacc_hi
0, // LRRC:sub_wacc_lo
0, // LRRC:sub_vsx1_then_sub_64
0, // LRRC:sub_pair1_then_sub_64
0, // LRRC:sub_pair1_then_sub_vsx0
0, // LRRC:sub_pair1_then_sub_vsx1
0, // LRRC:sub_pair1_then_sub_vsx1_then_sub_64
0, // LRRC:sub_dmrrowp1_then_sub_dmrrow0
0, // LRRC:sub_dmrrowp1_then_sub_dmrrow1
0, // LRRC:sub_wacc_hi_then_sub_dmrrow0
0, // LRRC:sub_wacc_hi_then_sub_dmrrow1
0, // LRRC:sub_wacc_hi_then_sub_dmrrowp0
0, // LRRC:sub_wacc_hi_then_sub_dmrrowp1
0, // LRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // LRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // LRRC:sub_dmr1_then_sub_dmrrow0
0, // LRRC:sub_dmr1_then_sub_dmrrow1
0, // LRRC:sub_dmr1_then_sub_dmrrowp0
0, // LRRC:sub_dmr1_then_sub_dmrrowp1
0, // LRRC:sub_dmr1_then_sub_wacc_hi
0, // LRRC:sub_dmr1_then_sub_wacc_lo
0, // LRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
0, // LRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
0, // LRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
0, // LRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
0, // LRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
0, // LRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
0, // LRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // LRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // LRRC:sub_gp8_x1_then_sub_32
},
{ // VRSAVERC
0, // VRSAVERC:sub_32
0, // VRSAVERC:sub_64
0, // VRSAVERC:sub_dmr0
0, // VRSAVERC:sub_dmr1
0, // VRSAVERC:sub_dmrrow0
0, // VRSAVERC:sub_dmrrow1
0, // VRSAVERC:sub_dmrrowp0
0, // VRSAVERC:sub_dmrrowp1
0, // VRSAVERC:sub_eq
0, // VRSAVERC:sub_gp8_x0
0, // VRSAVERC:sub_gp8_x1
0, // VRSAVERC:sub_gt
0, // VRSAVERC:sub_lt
0, // VRSAVERC:sub_pair0
0, // VRSAVERC:sub_pair1
0, // VRSAVERC:sub_un
0, // VRSAVERC:sub_vsx0
0, // VRSAVERC:sub_vsx1
0, // VRSAVERC:sub_wacc_hi
0, // VRSAVERC:sub_wacc_lo
0, // VRSAVERC:sub_vsx1_then_sub_64
0, // VRSAVERC:sub_pair1_then_sub_64
0, // VRSAVERC:sub_pair1_then_sub_vsx0
0, // VRSAVERC:sub_pair1_then_sub_vsx1
0, // VRSAVERC:sub_pair1_then_sub_vsx1_then_sub_64
0, // VRSAVERC:sub_dmrrowp1_then_sub_dmrrow0
0, // VRSAVERC:sub_dmrrowp1_then_sub_dmrrow1
0, // VRSAVERC:sub_wacc_hi_then_sub_dmrrow0
0, // VRSAVERC:sub_wacc_hi_then_sub_dmrrow1
0, // VRSAVERC:sub_wacc_hi_then_sub_dmrrowp0
0, // VRSAVERC:sub_wacc_hi_then_sub_dmrrowp1
0, // VRSAVERC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // VRSAVERC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // VRSAVERC:sub_dmr1_then_sub_dmrrow0
0, // VRSAVERC:sub_dmr1_then_sub_dmrrow1
0, // VRSAVERC:sub_dmr1_then_sub_dmrrowp0
0, // VRSAVERC:sub_dmr1_then_sub_dmrrowp1
0, // VRSAVERC:sub_dmr1_then_sub_wacc_hi
0, // VRSAVERC:sub_dmr1_then_sub_wacc_lo
0, // VRSAVERC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
0, // VRSAVERC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
0, // VRSAVERC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
0, // VRSAVERC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
0, // VRSAVERC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
0, // VRSAVERC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
0, // VRSAVERC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // VRSAVERC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // VRSAVERC:sub_gp8_x1_then_sub_32
},
{ // SPILLTOVSRRC
2, // SPILLTOVSRRC:sub_32 -> GPRC
0, // SPILLTOVSRRC:sub_64
0, // SPILLTOVSRRC:sub_dmr0
0, // SPILLTOVSRRC:sub_dmr1
0, // SPILLTOVSRRC:sub_dmrrow0
0, // SPILLTOVSRRC:sub_dmrrow1
0, // SPILLTOVSRRC:sub_dmrrowp0
0, // SPILLTOVSRRC:sub_dmrrowp1
0, // SPILLTOVSRRC:sub_eq
0, // SPILLTOVSRRC:sub_gp8_x0
0, // SPILLTOVSRRC:sub_gp8_x1
0, // SPILLTOVSRRC:sub_gt
0, // SPILLTOVSRRC:sub_lt
0, // SPILLTOVSRRC:sub_pair0
0, // SPILLTOVSRRC:sub_pair1
0, // SPILLTOVSRRC:sub_un
0, // SPILLTOVSRRC:sub_vsx0
0, // SPILLTOVSRRC:sub_vsx1
0, // SPILLTOVSRRC:sub_wacc_hi
0, // SPILLTOVSRRC:sub_wacc_lo
0, // SPILLTOVSRRC:sub_vsx1_then_sub_64
0, // SPILLTOVSRRC:sub_pair1_then_sub_64
0, // SPILLTOVSRRC:sub_pair1_then_sub_vsx0
0, // SPILLTOVSRRC:sub_pair1_then_sub_vsx1
0, // SPILLTOVSRRC:sub_pair1_then_sub_vsx1_then_sub_64
0, // SPILLTOVSRRC:sub_dmrrowp1_then_sub_dmrrow0
0, // SPILLTOVSRRC:sub_dmrrowp1_then_sub_dmrrow1
0, // SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrow0
0, // SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrow1
0, // SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp0
0, // SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1
0, // SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // SPILLTOVSRRC:sub_dmr1_then_sub_dmrrow0
0, // SPILLTOVSRRC:sub_dmr1_then_sub_dmrrow1
0, // SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp0
0, // SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1
0, // SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi
0, // SPILLTOVSRRC:sub_dmr1_then_sub_wacc_lo
0, // SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
0, // SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
0, // SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
0, // SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
0, // SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
0, // SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
0, // SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // SPILLTOVSRRC:sub_gp8_x1_then_sub_32
},
{ // VSFRC
0, // VSFRC:sub_32
0, // VSFRC:sub_64
0, // VSFRC:sub_dmr0
0, // VSFRC:sub_dmr1
0, // VSFRC:sub_dmrrow0
0, // VSFRC:sub_dmrrow1
0, // VSFRC:sub_dmrrowp0
0, // VSFRC:sub_dmrrowp1
0, // VSFRC:sub_eq
0, // VSFRC:sub_gp8_x0
0, // VSFRC:sub_gp8_x1
0, // VSFRC:sub_gt
0, // VSFRC:sub_lt
0, // VSFRC:sub_pair0
0, // VSFRC:sub_pair1
0, // VSFRC:sub_un
0, // VSFRC:sub_vsx0
0, // VSFRC:sub_vsx1
0, // VSFRC:sub_wacc_hi
0, // VSFRC:sub_wacc_lo
0, // VSFRC:sub_vsx1_then_sub_64
0, // VSFRC:sub_pair1_then_sub_64
0, // VSFRC:sub_pair1_then_sub_vsx0
0, // VSFRC:sub_pair1_then_sub_vsx1
0, // VSFRC:sub_pair1_then_sub_vsx1_then_sub_64
0, // VSFRC:sub_dmrrowp1_then_sub_dmrrow0
0, // VSFRC:sub_dmrrowp1_then_sub_dmrrow1
0, // VSFRC:sub_wacc_hi_then_sub_dmrrow0
0, // VSFRC:sub_wacc_hi_then_sub_dmrrow1
0, // VSFRC:sub_wacc_hi_then_sub_dmrrowp0
0, // VSFRC:sub_wacc_hi_then_sub_dmrrowp1
0, // VSFRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // VSFRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // VSFRC:sub_dmr1_then_sub_dmrrow0
0, // VSFRC:sub_dmr1_then_sub_dmrrow1
0, // VSFRC:sub_dmr1_then_sub_dmrrowp0
0, // VSFRC:sub_dmr1_then_sub_dmrrowp1
0, // VSFRC:sub_dmr1_then_sub_wacc_hi
0, // VSFRC:sub_dmr1_then_sub_wacc_lo
0, // VSFRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
0, // VSFRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
0, // VSFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
0, // VSFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
0, // VSFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
0, // VSFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
0, // VSFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // VSFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // VSFRC:sub_gp8_x1_then_sub_32
},
{ // G8RC
2, // G8RC:sub_32 -> GPRC
0, // G8RC:sub_64
0, // G8RC:sub_dmr0
0, // G8RC:sub_dmr1
0, // G8RC:sub_dmrrow0
0, // G8RC:sub_dmrrow1
0, // G8RC:sub_dmrrowp0
0, // G8RC:sub_dmrrowp1
0, // G8RC:sub_eq
0, // G8RC:sub_gp8_x0
0, // G8RC:sub_gp8_x1
0, // G8RC:sub_gt
0, // G8RC:sub_lt
0, // G8RC:sub_pair0
0, // G8RC:sub_pair1
0, // G8RC:sub_un
0, // G8RC:sub_vsx0
0, // G8RC:sub_vsx1
0, // G8RC:sub_wacc_hi
0, // G8RC:sub_wacc_lo
0, // G8RC:sub_vsx1_then_sub_64
0, // G8RC:sub_pair1_then_sub_64
0, // G8RC:sub_pair1_then_sub_vsx0
0, // G8RC:sub_pair1_then_sub_vsx1
0, // G8RC:sub_pair1_then_sub_vsx1_then_sub_64
0, // G8RC:sub_dmrrowp1_then_sub_dmrrow0
0, // G8RC:sub_dmrrowp1_then_sub_dmrrow1
0, // G8RC:sub_wacc_hi_then_sub_dmrrow0
0, // G8RC:sub_wacc_hi_then_sub_dmrrow1
0, // G8RC:sub_wacc_hi_then_sub_dmrrowp0
0, // G8RC:sub_wacc_hi_then_sub_dmrrowp1
0, // G8RC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // G8RC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // G8RC:sub_dmr1_then_sub_dmrrow0
0, // G8RC:sub_dmr1_then_sub_dmrrow1
0, // G8RC:sub_dmr1_then_sub_dmrrowp0
0, // G8RC:sub_dmr1_then_sub_dmrrowp1
0, // G8RC:sub_dmr1_then_sub_wacc_hi
0, // G8RC:sub_dmr1_then_sub_wacc_lo
0, // G8RC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
0, // G8RC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
0, // G8RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
0, // G8RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
0, // G8RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
0, // G8RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
0, // G8RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // G8RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // G8RC:sub_gp8_x1_then_sub_32
},
{ // G8RC_NOX0
3, // G8RC_NOX0:sub_32 -> GPRC_NOR0
0, // G8RC_NOX0:sub_64
0, // G8RC_NOX0:sub_dmr0
0, // G8RC_NOX0:sub_dmr1
0, // G8RC_NOX0:sub_dmrrow0
0, // G8RC_NOX0:sub_dmrrow1
0, // G8RC_NOX0:sub_dmrrowp0
0, // G8RC_NOX0:sub_dmrrowp1
0, // G8RC_NOX0:sub_eq
0, // G8RC_NOX0:sub_gp8_x0
0, // G8RC_NOX0:sub_gp8_x1
0, // G8RC_NOX0:sub_gt
0, // G8RC_NOX0:sub_lt
0, // G8RC_NOX0:sub_pair0
0, // G8RC_NOX0:sub_pair1
0, // G8RC_NOX0:sub_un
0, // G8RC_NOX0:sub_vsx0
0, // G8RC_NOX0:sub_vsx1
0, // G8RC_NOX0:sub_wacc_hi
0, // G8RC_NOX0:sub_wacc_lo
0, // G8RC_NOX0:sub_vsx1_then_sub_64
0, // G8RC_NOX0:sub_pair1_then_sub_64
0, // G8RC_NOX0:sub_pair1_then_sub_vsx0
0, // G8RC_NOX0:sub_pair1_then_sub_vsx1
0, // G8RC_NOX0:sub_pair1_then_sub_vsx1_then_sub_64
0, // G8RC_NOX0:sub_dmrrowp1_then_sub_dmrrow0
0, // G8RC_NOX0:sub_dmrrowp1_then_sub_dmrrow1
0, // G8RC_NOX0:sub_wacc_hi_then_sub_dmrrow0
0, // G8RC_NOX0:sub_wacc_hi_then_sub_dmrrow1
0, // G8RC_NOX0:sub_wacc_hi_then_sub_dmrrowp0
0, // G8RC_NOX0:sub_wacc_hi_then_sub_dmrrowp1
0, // G8RC_NOX0:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // G8RC_NOX0:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // G8RC_NOX0:sub_dmr1_then_sub_dmrrow0
0, // G8RC_NOX0:sub_dmr1_then_sub_dmrrow1
0, // G8RC_NOX0:sub_dmr1_then_sub_dmrrowp0
0, // G8RC_NOX0:sub_dmr1_then_sub_dmrrowp1
0, // G8RC_NOX0:sub_dmr1_then_sub_wacc_hi
0, // G8RC_NOX0:sub_dmr1_then_sub_wacc_lo
0, // G8RC_NOX0:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
0, // G8RC_NOX0:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
0, // G8RC_NOX0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
0, // G8RC_NOX0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
0, // G8RC_NOX0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
0, // G8RC_NOX0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
0, // G8RC_NOX0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // G8RC_NOX0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // G8RC_NOX0:sub_gp8_x1_then_sub_32
},
{ // SPILLTOVSRRC_and_VSFRC
0, // SPILLTOVSRRC_and_VSFRC:sub_32
0, // SPILLTOVSRRC_and_VSFRC:sub_64
0, // SPILLTOVSRRC_and_VSFRC:sub_dmr0
0, // SPILLTOVSRRC_and_VSFRC:sub_dmr1
0, // SPILLTOVSRRC_and_VSFRC:sub_dmrrow0
0, // SPILLTOVSRRC_and_VSFRC:sub_dmrrow1
0, // SPILLTOVSRRC_and_VSFRC:sub_dmrrowp0
0, // SPILLTOVSRRC_and_VSFRC:sub_dmrrowp1
0, // SPILLTOVSRRC_and_VSFRC:sub_eq
0, // SPILLTOVSRRC_and_VSFRC:sub_gp8_x0
0, // SPILLTOVSRRC_and_VSFRC:sub_gp8_x1
0, // SPILLTOVSRRC_and_VSFRC:sub_gt
0, // SPILLTOVSRRC_and_VSFRC:sub_lt
0, // SPILLTOVSRRC_and_VSFRC:sub_pair0
0, // SPILLTOVSRRC_and_VSFRC:sub_pair1
0, // SPILLTOVSRRC_and_VSFRC:sub_un
0, // SPILLTOVSRRC_and_VSFRC:sub_vsx0
0, // SPILLTOVSRRC_and_VSFRC:sub_vsx1
0, // SPILLTOVSRRC_and_VSFRC:sub_wacc_hi
0, // SPILLTOVSRRC_and_VSFRC:sub_wacc_lo
0, // SPILLTOVSRRC_and_VSFRC:sub_vsx1_then_sub_64
0, // SPILLTOVSRRC_and_VSFRC:sub_pair1_then_sub_64
0, // SPILLTOVSRRC_and_VSFRC:sub_pair1_then_sub_vsx0
0, // SPILLTOVSRRC_and_VSFRC:sub_pair1_then_sub_vsx1
0, // SPILLTOVSRRC_and_VSFRC:sub_pair1_then_sub_vsx1_then_sub_64
0, // SPILLTOVSRRC_and_VSFRC:sub_dmrrowp1_then_sub_dmrrow0
0, // SPILLTOVSRRC_and_VSFRC:sub_dmrrowp1_then_sub_dmrrow1
0, // SPILLTOVSRRC_and_VSFRC:sub_wacc_hi_then_sub_dmrrow0
0, // SPILLTOVSRRC_and_VSFRC:sub_wacc_hi_then_sub_dmrrow1
0, // SPILLTOVSRRC_and_VSFRC:sub_wacc_hi_then_sub_dmrrowp0
0, // SPILLTOVSRRC_and_VSFRC:sub_wacc_hi_then_sub_dmrrowp1
0, // SPILLTOVSRRC_and_VSFRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // SPILLTOVSRRC_and_VSFRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // SPILLTOVSRRC_and_VSFRC:sub_dmr1_then_sub_dmrrow0
0, // SPILLTOVSRRC_and_VSFRC:sub_dmr1_then_sub_dmrrow1
0, // SPILLTOVSRRC_and_VSFRC:sub_dmr1_then_sub_dmrrowp0
0, // SPILLTOVSRRC_and_VSFRC:sub_dmr1_then_sub_dmrrowp1
0, // SPILLTOVSRRC_and_VSFRC:sub_dmr1_then_sub_wacc_hi
0, // SPILLTOVSRRC_and_VSFRC:sub_dmr1_then_sub_wacc_lo
0, // SPILLTOVSRRC_and_VSFRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
0, // SPILLTOVSRRC_and_VSFRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
0, // SPILLTOVSRRC_and_VSFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
0, // SPILLTOVSRRC_and_VSFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
0, // SPILLTOVSRRC_and_VSFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
0, // SPILLTOVSRRC_and_VSFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
0, // SPILLTOVSRRC_and_VSFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // SPILLTOVSRRC_and_VSFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // SPILLTOVSRRC_and_VSFRC:sub_gp8_x1_then_sub_32
},
{ // G8RC_and_G8RC_NOX0
4, // G8RC_and_G8RC_NOX0:sub_32 -> GPRC_and_GPRC_NOR0
0, // G8RC_and_G8RC_NOX0:sub_64
0, // G8RC_and_G8RC_NOX0:sub_dmr0
0, // G8RC_and_G8RC_NOX0:sub_dmr1
0, // G8RC_and_G8RC_NOX0:sub_dmrrow0
0, // G8RC_and_G8RC_NOX0:sub_dmrrow1
0, // G8RC_and_G8RC_NOX0:sub_dmrrowp0
0, // G8RC_and_G8RC_NOX0:sub_dmrrowp1
0, // G8RC_and_G8RC_NOX0:sub_eq
0, // G8RC_and_G8RC_NOX0:sub_gp8_x0
0, // G8RC_and_G8RC_NOX0:sub_gp8_x1
0, // G8RC_and_G8RC_NOX0:sub_gt
0, // G8RC_and_G8RC_NOX0:sub_lt
0, // G8RC_and_G8RC_NOX0:sub_pair0
0, // G8RC_and_G8RC_NOX0:sub_pair1
0, // G8RC_and_G8RC_NOX0:sub_un
0, // G8RC_and_G8RC_NOX0:sub_vsx0
0, // G8RC_and_G8RC_NOX0:sub_vsx1
0, // G8RC_and_G8RC_NOX0:sub_wacc_hi
0, // G8RC_and_G8RC_NOX0:sub_wacc_lo
0, // G8RC_and_G8RC_NOX0:sub_vsx1_then_sub_64
0, // G8RC_and_G8RC_NOX0:sub_pair1_then_sub_64
0, // G8RC_and_G8RC_NOX0:sub_pair1_then_sub_vsx0
0, // G8RC_and_G8RC_NOX0:sub_pair1_then_sub_vsx1
0, // G8RC_and_G8RC_NOX0:sub_pair1_then_sub_vsx1_then_sub_64
0, // G8RC_and_G8RC_NOX0:sub_dmrrowp1_then_sub_dmrrow0
0, // G8RC_and_G8RC_NOX0:sub_dmrrowp1_then_sub_dmrrow1
0, // G8RC_and_G8RC_NOX0:sub_wacc_hi_then_sub_dmrrow0
0, // G8RC_and_G8RC_NOX0:sub_wacc_hi_then_sub_dmrrow1
0, // G8RC_and_G8RC_NOX0:sub_wacc_hi_then_sub_dmrrowp0
0, // G8RC_and_G8RC_NOX0:sub_wacc_hi_then_sub_dmrrowp1
0, // G8RC_and_G8RC_NOX0:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // G8RC_and_G8RC_NOX0:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // G8RC_and_G8RC_NOX0:sub_dmr1_then_sub_dmrrow0
0, // G8RC_and_G8RC_NOX0:sub_dmr1_then_sub_dmrrow1
0, // G8RC_and_G8RC_NOX0:sub_dmr1_then_sub_dmrrowp0
0, // G8RC_and_G8RC_NOX0:sub_dmr1_then_sub_dmrrowp1
0, // G8RC_and_G8RC_NOX0:sub_dmr1_then_sub_wacc_hi
0, // G8RC_and_G8RC_NOX0:sub_dmr1_then_sub_wacc_lo
0, // G8RC_and_G8RC_NOX0:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
0, // G8RC_and_G8RC_NOX0:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
0, // G8RC_and_G8RC_NOX0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
0, // G8RC_and_G8RC_NOX0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
0, // G8RC_and_G8RC_NOX0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
0, // G8RC_and_G8RC_NOX0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
0, // G8RC_and_G8RC_NOX0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // G8RC_and_G8RC_NOX0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // G8RC_and_G8RC_NOX0:sub_gp8_x1_then_sub_32
},
{ // F8RC
0, // F8RC:sub_32
0, // F8RC:sub_64
0, // F8RC:sub_dmr0
0, // F8RC:sub_dmr1
0, // F8RC:sub_dmrrow0
0, // F8RC:sub_dmrrow1
0, // F8RC:sub_dmrrowp0
0, // F8RC:sub_dmrrowp1
0, // F8RC:sub_eq
0, // F8RC:sub_gp8_x0
0, // F8RC:sub_gp8_x1
0, // F8RC:sub_gt
0, // F8RC:sub_lt
0, // F8RC:sub_pair0
0, // F8RC:sub_pair1
0, // F8RC:sub_un
0, // F8RC:sub_vsx0
0, // F8RC:sub_vsx1
0, // F8RC:sub_wacc_hi
0, // F8RC:sub_wacc_lo
0, // F8RC:sub_vsx1_then_sub_64
0, // F8RC:sub_pair1_then_sub_64
0, // F8RC:sub_pair1_then_sub_vsx0
0, // F8RC:sub_pair1_then_sub_vsx1
0, // F8RC:sub_pair1_then_sub_vsx1_then_sub_64
0, // F8RC:sub_dmrrowp1_then_sub_dmrrow0
0, // F8RC:sub_dmrrowp1_then_sub_dmrrow1
0, // F8RC:sub_wacc_hi_then_sub_dmrrow0
0, // F8RC:sub_wacc_hi_then_sub_dmrrow1
0, // F8RC:sub_wacc_hi_then_sub_dmrrowp0
0, // F8RC:sub_wacc_hi_then_sub_dmrrowp1
0, // F8RC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // F8RC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // F8RC:sub_dmr1_then_sub_dmrrow0
0, // F8RC:sub_dmr1_then_sub_dmrrow1
0, // F8RC:sub_dmr1_then_sub_dmrrowp0
0, // F8RC:sub_dmr1_then_sub_dmrrowp1
0, // F8RC:sub_dmr1_then_sub_wacc_hi
0, // F8RC:sub_dmr1_then_sub_wacc_lo
0, // F8RC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
0, // F8RC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
0, // F8RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
0, // F8RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
0, // F8RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
0, // F8RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
0, // F8RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // F8RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // F8RC:sub_gp8_x1_then_sub_32
},
{ // SPERC
2, // SPERC:sub_32 -> GPRC
0, // SPERC:sub_64
0, // SPERC:sub_dmr0
0, // SPERC:sub_dmr1
0, // SPERC:sub_dmrrow0
0, // SPERC:sub_dmrrow1
0, // SPERC:sub_dmrrowp0
0, // SPERC:sub_dmrrowp1
0, // SPERC:sub_eq
0, // SPERC:sub_gp8_x0
0, // SPERC:sub_gp8_x1
0, // SPERC:sub_gt
0, // SPERC:sub_lt
0, // SPERC:sub_pair0
0, // SPERC:sub_pair1
0, // SPERC:sub_un
0, // SPERC:sub_vsx0
0, // SPERC:sub_vsx1
0, // SPERC:sub_wacc_hi
0, // SPERC:sub_wacc_lo
0, // SPERC:sub_vsx1_then_sub_64
0, // SPERC:sub_pair1_then_sub_64
0, // SPERC:sub_pair1_then_sub_vsx0
0, // SPERC:sub_pair1_then_sub_vsx1
0, // SPERC:sub_pair1_then_sub_vsx1_then_sub_64
0, // SPERC:sub_dmrrowp1_then_sub_dmrrow0
0, // SPERC:sub_dmrrowp1_then_sub_dmrrow1
0, // SPERC:sub_wacc_hi_then_sub_dmrrow0
0, // SPERC:sub_wacc_hi_then_sub_dmrrow1
0, // SPERC:sub_wacc_hi_then_sub_dmrrowp0
0, // SPERC:sub_wacc_hi_then_sub_dmrrowp1
0, // SPERC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // SPERC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // SPERC:sub_dmr1_then_sub_dmrrow0
0, // SPERC:sub_dmr1_then_sub_dmrrow1
0, // SPERC:sub_dmr1_then_sub_dmrrowp0
0, // SPERC:sub_dmr1_then_sub_dmrrowp1
0, // SPERC:sub_dmr1_then_sub_wacc_hi
0, // SPERC:sub_dmr1_then_sub_wacc_lo
0, // SPERC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
0, // SPERC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
0, // SPERC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
0, // SPERC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
0, // SPERC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
0, // SPERC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
0, // SPERC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // SPERC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // SPERC:sub_gp8_x1_then_sub_32
},
{ // VFRC
0, // VFRC:sub_32
0, // VFRC:sub_64
0, // VFRC:sub_dmr0
0, // VFRC:sub_dmr1
0, // VFRC:sub_dmrrow0
0, // VFRC:sub_dmrrow1
0, // VFRC:sub_dmrrowp0
0, // VFRC:sub_dmrrowp1
0, // VFRC:sub_eq
0, // VFRC:sub_gp8_x0
0, // VFRC:sub_gp8_x1
0, // VFRC:sub_gt
0, // VFRC:sub_lt
0, // VFRC:sub_pair0
0, // VFRC:sub_pair1
0, // VFRC:sub_un
0, // VFRC:sub_vsx0
0, // VFRC:sub_vsx1
0, // VFRC:sub_wacc_hi
0, // VFRC:sub_wacc_lo
0, // VFRC:sub_vsx1_then_sub_64
0, // VFRC:sub_pair1_then_sub_64
0, // VFRC:sub_pair1_then_sub_vsx0
0, // VFRC:sub_pair1_then_sub_vsx1
0, // VFRC:sub_pair1_then_sub_vsx1_then_sub_64
0, // VFRC:sub_dmrrowp1_then_sub_dmrrow0
0, // VFRC:sub_dmrrowp1_then_sub_dmrrow1
0, // VFRC:sub_wacc_hi_then_sub_dmrrow0
0, // VFRC:sub_wacc_hi_then_sub_dmrrow1
0, // VFRC:sub_wacc_hi_then_sub_dmrrowp0
0, // VFRC:sub_wacc_hi_then_sub_dmrrowp1
0, // VFRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // VFRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // VFRC:sub_dmr1_then_sub_dmrrow0
0, // VFRC:sub_dmr1_then_sub_dmrrow1
0, // VFRC:sub_dmr1_then_sub_dmrrowp0
0, // VFRC:sub_dmr1_then_sub_dmrrowp1
0, // VFRC:sub_dmr1_then_sub_wacc_hi
0, // VFRC:sub_dmr1_then_sub_wacc_lo
0, // VFRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
0, // VFRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
0, // VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
0, // VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
0, // VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
0, // VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
0, // VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // VFRC:sub_gp8_x1_then_sub_32
},
{ // SPERC_with_sub_32_in_GPRC_NOR0
4, // SPERC_with_sub_32_in_GPRC_NOR0:sub_32 -> GPRC_and_GPRC_NOR0
0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_64
0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_dmr0
0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_dmr1
0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_dmrrow0
0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_dmrrow1
0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_dmrrowp0
0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_dmrrowp1
0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_eq
0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_gp8_x0
0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_gp8_x1
0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_gt
0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_lt
0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_pair0
0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_pair1
0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_un
0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_vsx0
0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_vsx1
0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_wacc_hi
0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_wacc_lo
0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_vsx1_then_sub_64
0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_pair1_then_sub_64
0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_pair1_then_sub_vsx0
0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_pair1_then_sub_vsx1
0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_pair1_then_sub_vsx1_then_sub_64
0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_dmrrowp1_then_sub_dmrrow0
0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_dmrrowp1_then_sub_dmrrow1
0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_wacc_hi_then_sub_dmrrow0
0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_wacc_hi_then_sub_dmrrow1
0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_wacc_hi_then_sub_dmrrowp0
0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_wacc_hi_then_sub_dmrrowp1
0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_dmrrow0
0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_dmrrow1
0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_dmrrowp0
0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_dmrrowp1
0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi
0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_wacc_lo
0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // SPERC_with_sub_32_in_GPRC_NOR0:sub_gp8_x1_then_sub_32
},
{ // SPILLTOVSRRC_and_VFRC
0, // SPILLTOVSRRC_and_VFRC:sub_32
0, // SPILLTOVSRRC_and_VFRC:sub_64
0, // SPILLTOVSRRC_and_VFRC:sub_dmr0
0, // SPILLTOVSRRC_and_VFRC:sub_dmr1
0, // SPILLTOVSRRC_and_VFRC:sub_dmrrow0
0, // SPILLTOVSRRC_and_VFRC:sub_dmrrow1
0, // SPILLTOVSRRC_and_VFRC:sub_dmrrowp0
0, // SPILLTOVSRRC_and_VFRC:sub_dmrrowp1
0, // SPILLTOVSRRC_and_VFRC:sub_eq
0, // SPILLTOVSRRC_and_VFRC:sub_gp8_x0
0, // SPILLTOVSRRC_and_VFRC:sub_gp8_x1
0, // SPILLTOVSRRC_and_VFRC:sub_gt
0, // SPILLTOVSRRC_and_VFRC:sub_lt
0, // SPILLTOVSRRC_and_VFRC:sub_pair0
0, // SPILLTOVSRRC_and_VFRC:sub_pair1
0, // SPILLTOVSRRC_and_VFRC:sub_un
0, // SPILLTOVSRRC_and_VFRC:sub_vsx0
0, // SPILLTOVSRRC_and_VFRC:sub_vsx1
0, // SPILLTOVSRRC_and_VFRC:sub_wacc_hi
0, // SPILLTOVSRRC_and_VFRC:sub_wacc_lo
0, // SPILLTOVSRRC_and_VFRC:sub_vsx1_then_sub_64
0, // SPILLTOVSRRC_and_VFRC:sub_pair1_then_sub_64
0, // SPILLTOVSRRC_and_VFRC:sub_pair1_then_sub_vsx0
0, // SPILLTOVSRRC_and_VFRC:sub_pair1_then_sub_vsx1
0, // SPILLTOVSRRC_and_VFRC:sub_pair1_then_sub_vsx1_then_sub_64
0, // SPILLTOVSRRC_and_VFRC:sub_dmrrowp1_then_sub_dmrrow0
0, // SPILLTOVSRRC_and_VFRC:sub_dmrrowp1_then_sub_dmrrow1
0, // SPILLTOVSRRC_and_VFRC:sub_wacc_hi_then_sub_dmrrow0
0, // SPILLTOVSRRC_and_VFRC:sub_wacc_hi_then_sub_dmrrow1
0, // SPILLTOVSRRC_and_VFRC:sub_wacc_hi_then_sub_dmrrowp0
0, // SPILLTOVSRRC_and_VFRC:sub_wacc_hi_then_sub_dmrrowp1
0, // SPILLTOVSRRC_and_VFRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // SPILLTOVSRRC_and_VFRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_dmrrow0
0, // SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_dmrrow1
0, // SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_dmrrowp0
0, // SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_dmrrowp1
0, // SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_wacc_hi
0, // SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_wacc_lo
0, // SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
0, // SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
0, // SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
0, // SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
0, // SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
0, // SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
0, // SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // SPILLTOVSRRC_and_VFRC:sub_gp8_x1_then_sub_32
},
{ // SPILLTOVSRRC_and_F4RC
0, // SPILLTOVSRRC_and_F4RC:sub_32
0, // SPILLTOVSRRC_and_F4RC:sub_64
0, // SPILLTOVSRRC_and_F4RC:sub_dmr0
0, // SPILLTOVSRRC_and_F4RC:sub_dmr1
0, // SPILLTOVSRRC_and_F4RC:sub_dmrrow0
0, // SPILLTOVSRRC_and_F4RC:sub_dmrrow1
0, // SPILLTOVSRRC_and_F4RC:sub_dmrrowp0
0, // SPILLTOVSRRC_and_F4RC:sub_dmrrowp1
0, // SPILLTOVSRRC_and_F4RC:sub_eq
0, // SPILLTOVSRRC_and_F4RC:sub_gp8_x0
0, // SPILLTOVSRRC_and_F4RC:sub_gp8_x1
0, // SPILLTOVSRRC_and_F4RC:sub_gt
0, // SPILLTOVSRRC_and_F4RC:sub_lt
0, // SPILLTOVSRRC_and_F4RC:sub_pair0
0, // SPILLTOVSRRC_and_F4RC:sub_pair1
0, // SPILLTOVSRRC_and_F4RC:sub_un
0, // SPILLTOVSRRC_and_F4RC:sub_vsx0
0, // SPILLTOVSRRC_and_F4RC:sub_vsx1
0, // SPILLTOVSRRC_and_F4RC:sub_wacc_hi
0, // SPILLTOVSRRC_and_F4RC:sub_wacc_lo
0, // SPILLTOVSRRC_and_F4RC:sub_vsx1_then_sub_64
0, // SPILLTOVSRRC_and_F4RC:sub_pair1_then_sub_64
0, // SPILLTOVSRRC_and_F4RC:sub_pair1_then_sub_vsx0
0, // SPILLTOVSRRC_and_F4RC:sub_pair1_then_sub_vsx1
0, // SPILLTOVSRRC_and_F4RC:sub_pair1_then_sub_vsx1_then_sub_64
0, // SPILLTOVSRRC_and_F4RC:sub_dmrrowp1_then_sub_dmrrow0
0, // SPILLTOVSRRC_and_F4RC:sub_dmrrowp1_then_sub_dmrrow1
0, // SPILLTOVSRRC_and_F4RC:sub_wacc_hi_then_sub_dmrrow0
0, // SPILLTOVSRRC_and_F4RC:sub_wacc_hi_then_sub_dmrrow1
0, // SPILLTOVSRRC_and_F4RC:sub_wacc_hi_then_sub_dmrrowp0
0, // SPILLTOVSRRC_and_F4RC:sub_wacc_hi_then_sub_dmrrowp1
0, // SPILLTOVSRRC_and_F4RC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // SPILLTOVSRRC_and_F4RC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_dmrrow0
0, // SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_dmrrow1
0, // SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_dmrrowp0
0, // SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_dmrrowp1
0, // SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_wacc_hi
0, // SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_wacc_lo
0, // SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
0, // SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
0, // SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
0, // SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
0, // SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
0, // SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
0, // SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // SPILLTOVSRRC_and_F4RC:sub_gp8_x1_then_sub_32
},
{ // CTRRC8
0, // CTRRC8:sub_32
0, // CTRRC8:sub_64
0, // CTRRC8:sub_dmr0
0, // CTRRC8:sub_dmr1
0, // CTRRC8:sub_dmrrow0
0, // CTRRC8:sub_dmrrow1
0, // CTRRC8:sub_dmrrowp0
0, // CTRRC8:sub_dmrrowp1
0, // CTRRC8:sub_eq
0, // CTRRC8:sub_gp8_x0
0, // CTRRC8:sub_gp8_x1
0, // CTRRC8:sub_gt
0, // CTRRC8:sub_lt
0, // CTRRC8:sub_pair0
0, // CTRRC8:sub_pair1
0, // CTRRC8:sub_un
0, // CTRRC8:sub_vsx0
0, // CTRRC8:sub_vsx1
0, // CTRRC8:sub_wacc_hi
0, // CTRRC8:sub_wacc_lo
0, // CTRRC8:sub_vsx1_then_sub_64
0, // CTRRC8:sub_pair1_then_sub_64
0, // CTRRC8:sub_pair1_then_sub_vsx0
0, // CTRRC8:sub_pair1_then_sub_vsx1
0, // CTRRC8:sub_pair1_then_sub_vsx1_then_sub_64
0, // CTRRC8:sub_dmrrowp1_then_sub_dmrrow0
0, // CTRRC8:sub_dmrrowp1_then_sub_dmrrow1
0, // CTRRC8:sub_wacc_hi_then_sub_dmrrow0
0, // CTRRC8:sub_wacc_hi_then_sub_dmrrow1
0, // CTRRC8:sub_wacc_hi_then_sub_dmrrowp0
0, // CTRRC8:sub_wacc_hi_then_sub_dmrrowp1
0, // CTRRC8:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // CTRRC8:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // CTRRC8:sub_dmr1_then_sub_dmrrow0
0, // CTRRC8:sub_dmr1_then_sub_dmrrow1
0, // CTRRC8:sub_dmr1_then_sub_dmrrowp0
0, // CTRRC8:sub_dmr1_then_sub_dmrrowp1
0, // CTRRC8:sub_dmr1_then_sub_wacc_hi
0, // CTRRC8:sub_dmr1_then_sub_wacc_lo
0, // CTRRC8:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
0, // CTRRC8:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
0, // CTRRC8:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
0, // CTRRC8:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
0, // CTRRC8:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
0, // CTRRC8:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
0, // CTRRC8:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // CTRRC8:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // CTRRC8:sub_gp8_x1_then_sub_32
},
{ // LR8RC
0, // LR8RC:sub_32
0, // LR8RC:sub_64
0, // LR8RC:sub_dmr0
0, // LR8RC:sub_dmr1
0, // LR8RC:sub_dmrrow0
0, // LR8RC:sub_dmrrow1
0, // LR8RC:sub_dmrrowp0
0, // LR8RC:sub_dmrrowp1
0, // LR8RC:sub_eq
0, // LR8RC:sub_gp8_x0
0, // LR8RC:sub_gp8_x1
0, // LR8RC:sub_gt
0, // LR8RC:sub_lt
0, // LR8RC:sub_pair0
0, // LR8RC:sub_pair1
0, // LR8RC:sub_un
0, // LR8RC:sub_vsx0
0, // LR8RC:sub_vsx1
0, // LR8RC:sub_wacc_hi
0, // LR8RC:sub_wacc_lo
0, // LR8RC:sub_vsx1_then_sub_64
0, // LR8RC:sub_pair1_then_sub_64
0, // LR8RC:sub_pair1_then_sub_vsx0
0, // LR8RC:sub_pair1_then_sub_vsx1
0, // LR8RC:sub_pair1_then_sub_vsx1_then_sub_64
0, // LR8RC:sub_dmrrowp1_then_sub_dmrrow0
0, // LR8RC:sub_dmrrowp1_then_sub_dmrrow1
0, // LR8RC:sub_wacc_hi_then_sub_dmrrow0
0, // LR8RC:sub_wacc_hi_then_sub_dmrrow1
0, // LR8RC:sub_wacc_hi_then_sub_dmrrowp0
0, // LR8RC:sub_wacc_hi_then_sub_dmrrowp1
0, // LR8RC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // LR8RC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // LR8RC:sub_dmr1_then_sub_dmrrow0
0, // LR8RC:sub_dmr1_then_sub_dmrrow1
0, // LR8RC:sub_dmr1_then_sub_dmrrowp0
0, // LR8RC:sub_dmr1_then_sub_dmrrowp1
0, // LR8RC:sub_dmr1_then_sub_wacc_hi
0, // LR8RC:sub_dmr1_then_sub_wacc_lo
0, // LR8RC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
0, // LR8RC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
0, // LR8RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
0, // LR8RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
0, // LR8RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
0, // LR8RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
0, // LR8RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // LR8RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // LR8RC:sub_gp8_x1_then_sub_32
},
{ // DMRROWRC
0, // DMRROWRC:sub_32
0, // DMRROWRC:sub_64
0, // DMRROWRC:sub_dmr0
0, // DMRROWRC:sub_dmr1
0, // DMRROWRC:sub_dmrrow0
0, // DMRROWRC:sub_dmrrow1
0, // DMRROWRC:sub_dmrrowp0
0, // DMRROWRC:sub_dmrrowp1
0, // DMRROWRC:sub_eq
0, // DMRROWRC:sub_gp8_x0
0, // DMRROWRC:sub_gp8_x1
0, // DMRROWRC:sub_gt
0, // DMRROWRC:sub_lt
0, // DMRROWRC:sub_pair0
0, // DMRROWRC:sub_pair1
0, // DMRROWRC:sub_un
0, // DMRROWRC:sub_vsx0
0, // DMRROWRC:sub_vsx1
0, // DMRROWRC:sub_wacc_hi
0, // DMRROWRC:sub_wacc_lo
0, // DMRROWRC:sub_vsx1_then_sub_64
0, // DMRROWRC:sub_pair1_then_sub_64
0, // DMRROWRC:sub_pair1_then_sub_vsx0
0, // DMRROWRC:sub_pair1_then_sub_vsx1
0, // DMRROWRC:sub_pair1_then_sub_vsx1_then_sub_64
0, // DMRROWRC:sub_dmrrowp1_then_sub_dmrrow0
0, // DMRROWRC:sub_dmrrowp1_then_sub_dmrrow1
0, // DMRROWRC:sub_wacc_hi_then_sub_dmrrow0
0, // DMRROWRC:sub_wacc_hi_then_sub_dmrrow1
0, // DMRROWRC:sub_wacc_hi_then_sub_dmrrowp0
0, // DMRROWRC:sub_wacc_hi_then_sub_dmrrowp1
0, // DMRROWRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // DMRROWRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // DMRROWRC:sub_dmr1_then_sub_dmrrow0
0, // DMRROWRC:sub_dmr1_then_sub_dmrrow1
0, // DMRROWRC:sub_dmr1_then_sub_dmrrowp0
0, // DMRROWRC:sub_dmr1_then_sub_dmrrowp1
0, // DMRROWRC:sub_dmr1_then_sub_wacc_hi
0, // DMRROWRC:sub_dmr1_then_sub_wacc_lo
0, // DMRROWRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
0, // DMRROWRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
0, // DMRROWRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
0, // DMRROWRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
0, // DMRROWRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
0, // DMRROWRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
0, // DMRROWRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // DMRROWRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // DMRROWRC:sub_gp8_x1_then_sub_32
},
{ // VSRC
0, // VSRC:sub_32
1, // VSRC:sub_64 -> VSSRC
0, // VSRC:sub_dmr0
0, // VSRC:sub_dmr1
0, // VSRC:sub_dmrrow0
0, // VSRC:sub_dmrrow1
0, // VSRC:sub_dmrrowp0
0, // VSRC:sub_dmrrowp1
0, // VSRC:sub_eq
0, // VSRC:sub_gp8_x0
0, // VSRC:sub_gp8_x1
0, // VSRC:sub_gt
0, // VSRC:sub_lt
0, // VSRC:sub_pair0
0, // VSRC:sub_pair1
0, // VSRC:sub_un
0, // VSRC:sub_vsx0
0, // VSRC:sub_vsx1
0, // VSRC:sub_wacc_hi
0, // VSRC:sub_wacc_lo
0, // VSRC:sub_vsx1_then_sub_64
0, // VSRC:sub_pair1_then_sub_64
0, // VSRC:sub_pair1_then_sub_vsx0
0, // VSRC:sub_pair1_then_sub_vsx1
0, // VSRC:sub_pair1_then_sub_vsx1_then_sub_64
0, // VSRC:sub_dmrrowp1_then_sub_dmrrow0
0, // VSRC:sub_dmrrowp1_then_sub_dmrrow1
0, // VSRC:sub_wacc_hi_then_sub_dmrrow0
0, // VSRC:sub_wacc_hi_then_sub_dmrrow1
0, // VSRC:sub_wacc_hi_then_sub_dmrrowp0
0, // VSRC:sub_wacc_hi_then_sub_dmrrowp1
0, // VSRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // VSRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // VSRC:sub_dmr1_then_sub_dmrrow0
0, // VSRC:sub_dmr1_then_sub_dmrrow1
0, // VSRC:sub_dmr1_then_sub_dmrrowp0
0, // VSRC:sub_dmr1_then_sub_dmrrowp1
0, // VSRC:sub_dmr1_then_sub_wacc_hi
0, // VSRC:sub_dmr1_then_sub_wacc_lo
0, // VSRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
0, // VSRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
0, // VSRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
0, // VSRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
0, // VSRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
0, // VSRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
0, // VSRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // VSRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // VSRC:sub_gp8_x1_then_sub_32
},
{ // VSRC_with_sub_64_in_SPILLTOVSRRC
0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_32
16, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_64 -> SPILLTOVSRRC_and_VSFRC
0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr0
0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1
0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrow0
0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrow1
0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp0
0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1
0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_eq
0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_gp8_x0
0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_gp8_x1
0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_gt
0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_lt
0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_pair0
0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1
0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_un
0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx0
0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx1
0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi
0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_lo
0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx1_then_sub_64
0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_64
0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx0
0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1
0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1_then_sub_64
0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1_then_sub_dmrrow0
0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1_then_sub_dmrrow1
0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrow0
0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrow1
0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp0
0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1
0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrow0
0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrow1
0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp0
0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1
0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi
0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_lo
0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_gp8_x1_then_sub_32
},
{ // VRRC
0, // VRRC:sub_32
20, // VRRC:sub_64 -> VFRC
0, // VRRC:sub_dmr0
0, // VRRC:sub_dmr1
0, // VRRC:sub_dmrrow0
0, // VRRC:sub_dmrrow1
0, // VRRC:sub_dmrrowp0
0, // VRRC:sub_dmrrowp1
0, // VRRC:sub_eq
0, // VRRC:sub_gp8_x0
0, // VRRC:sub_gp8_x1
0, // VRRC:sub_gt
0, // VRRC:sub_lt
0, // VRRC:sub_pair0
0, // VRRC:sub_pair1
0, // VRRC:sub_un
0, // VRRC:sub_vsx0
0, // VRRC:sub_vsx1
0, // VRRC:sub_wacc_hi
0, // VRRC:sub_wacc_lo
0, // VRRC:sub_vsx1_then_sub_64
0, // VRRC:sub_pair1_then_sub_64
0, // VRRC:sub_pair1_then_sub_vsx0
0, // VRRC:sub_pair1_then_sub_vsx1
0, // VRRC:sub_pair1_then_sub_vsx1_then_sub_64
0, // VRRC:sub_dmrrowp1_then_sub_dmrrow0
0, // VRRC:sub_dmrrowp1_then_sub_dmrrow1
0, // VRRC:sub_wacc_hi_then_sub_dmrrow0
0, // VRRC:sub_wacc_hi_then_sub_dmrrow1
0, // VRRC:sub_wacc_hi_then_sub_dmrrowp0
0, // VRRC:sub_wacc_hi_then_sub_dmrrowp1
0, // VRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // VRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // VRRC:sub_dmr1_then_sub_dmrrow0
0, // VRRC:sub_dmr1_then_sub_dmrrow1
0, // VRRC:sub_dmr1_then_sub_dmrrowp0
0, // VRRC:sub_dmr1_then_sub_dmrrowp1
0, // VRRC:sub_dmr1_then_sub_wacc_hi
0, // VRRC:sub_dmr1_then_sub_wacc_lo
0, // VRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
0, // VRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
0, // VRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
0, // VRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
0, // VRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
0, // VRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
0, // VRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // VRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // VRRC:sub_gp8_x1_then_sub_32
},
{ // VSLRC
0, // VSLRC:sub_32
6, // VSLRC:sub_64 -> F4RC
0, // VSLRC:sub_dmr0
0, // VSLRC:sub_dmr1
0, // VSLRC:sub_dmrrow0
0, // VSLRC:sub_dmrrow1
0, // VSLRC:sub_dmrrowp0
0, // VSLRC:sub_dmrrowp1
0, // VSLRC:sub_eq
0, // VSLRC:sub_gp8_x0
0, // VSLRC:sub_gp8_x1
0, // VSLRC:sub_gt
0, // VSLRC:sub_lt
0, // VSLRC:sub_pair0
0, // VSLRC:sub_pair1
0, // VSLRC:sub_un
0, // VSLRC:sub_vsx0
0, // VSLRC:sub_vsx1
0, // VSLRC:sub_wacc_hi
0, // VSLRC:sub_wacc_lo
0, // VSLRC:sub_vsx1_then_sub_64
0, // VSLRC:sub_pair1_then_sub_64
0, // VSLRC:sub_pair1_then_sub_vsx0
0, // VSLRC:sub_pair1_then_sub_vsx1
0, // VSLRC:sub_pair1_then_sub_vsx1_then_sub_64
0, // VSLRC:sub_dmrrowp1_then_sub_dmrrow0
0, // VSLRC:sub_dmrrowp1_then_sub_dmrrow1
0, // VSLRC:sub_wacc_hi_then_sub_dmrrow0
0, // VSLRC:sub_wacc_hi_then_sub_dmrrow1
0, // VSLRC:sub_wacc_hi_then_sub_dmrrowp0
0, // VSLRC:sub_wacc_hi_then_sub_dmrrowp1
0, // VSLRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // VSLRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // VSLRC:sub_dmr1_then_sub_dmrrow0
0, // VSLRC:sub_dmr1_then_sub_dmrrow1
0, // VSLRC:sub_dmr1_then_sub_dmrrowp0
0, // VSLRC:sub_dmr1_then_sub_dmrrowp1
0, // VSLRC:sub_dmr1_then_sub_wacc_hi
0, // VSLRC:sub_dmr1_then_sub_wacc_lo
0, // VSLRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
0, // VSLRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
0, // VSLRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
0, // VSLRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
0, // VSLRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
0, // VSLRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
0, // VSLRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // VSLRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // VSLRC:sub_gp8_x1_then_sub_32
},
{ // VRRC_with_sub_64_in_SPILLTOVSRRC
0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_32
22, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_64 -> SPILLTOVSRRC_and_VFRC
0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr0
0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1
0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrow0
0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrow1
0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp0
0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1
0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_eq
0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_gp8_x0
0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_gp8_x1
0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_gt
0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_lt
0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_pair0
0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1
0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_un
0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx0
0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx1
0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi
0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_lo
0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx1_then_sub_64
0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_64
0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx0
0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1
0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1_then_sub_64
0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1_then_sub_dmrrow0
0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1_then_sub_dmrrow1
0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrow0
0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrow1
0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp0
0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1
0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrow0
0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrow1
0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp0
0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1
0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi
0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_lo
0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_gp8_x1_then_sub_32
},
{ // G8pRC
2, // G8pRC:sub_32 -> GPRC
0, // G8pRC:sub_64
0, // G8pRC:sub_dmr0
0, // G8pRC:sub_dmr1
0, // G8pRC:sub_dmrrow0
0, // G8pRC:sub_dmrrow1
0, // G8pRC:sub_dmrrowp0
0, // G8pRC:sub_dmrrowp1
0, // G8pRC:sub_eq
14, // G8pRC:sub_gp8_x0 -> G8RC
17, // G8pRC:sub_gp8_x1 -> G8RC_and_G8RC_NOX0
0, // G8pRC:sub_gt
0, // G8pRC:sub_lt
0, // G8pRC:sub_pair0
0, // G8pRC:sub_pair1
0, // G8pRC:sub_un
0, // G8pRC:sub_vsx0
0, // G8pRC:sub_vsx1
0, // G8pRC:sub_wacc_hi
0, // G8pRC:sub_wacc_lo
0, // G8pRC:sub_vsx1_then_sub_64
0, // G8pRC:sub_pair1_then_sub_64
0, // G8pRC:sub_pair1_then_sub_vsx0
0, // G8pRC:sub_pair1_then_sub_vsx1
0, // G8pRC:sub_pair1_then_sub_vsx1_then_sub_64
0, // G8pRC:sub_dmrrowp1_then_sub_dmrrow0
0, // G8pRC:sub_dmrrowp1_then_sub_dmrrow1
0, // G8pRC:sub_wacc_hi_then_sub_dmrrow0
0, // G8pRC:sub_wacc_hi_then_sub_dmrrow1
0, // G8pRC:sub_wacc_hi_then_sub_dmrrowp0
0, // G8pRC:sub_wacc_hi_then_sub_dmrrowp1
0, // G8pRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // G8pRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // G8pRC:sub_dmr1_then_sub_dmrrow0
0, // G8pRC:sub_dmr1_then_sub_dmrrow1
0, // G8pRC:sub_dmr1_then_sub_dmrrowp0
0, // G8pRC:sub_dmr1_then_sub_dmrrowp1
0, // G8pRC:sub_dmr1_then_sub_wacc_hi
0, // G8pRC:sub_dmr1_then_sub_wacc_lo
0, // G8pRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
0, // G8pRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
0, // G8pRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
0, // G8pRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
0, // G8pRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
0, // G8pRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
0, // G8pRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // G8pRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
4, // G8pRC:sub_gp8_x1_then_sub_32 -> GPRC_and_GPRC_NOR0
},
{ // G8pRC_with_sub_32_in_GPRC_NOR0
4, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_32 -> GPRC_and_GPRC_NOR0
0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_64
0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmr0
0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmr1
0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmrrow0
0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmrrow1
0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmrrowp0
0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmrrowp1
0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_eq
17, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_gp8_x0 -> G8RC_and_G8RC_NOX0
17, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_gp8_x1 -> G8RC_and_G8RC_NOX0
0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_gt
0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_lt
0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_pair0
0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_pair1
0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_un
0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_vsx0
0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_vsx1
0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_wacc_hi
0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_wacc_lo
0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_vsx1_then_sub_64
0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_pair1_then_sub_64
0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_pair1_then_sub_vsx0
0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_pair1_then_sub_vsx1
0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_pair1_then_sub_vsx1_then_sub_64
0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmrrowp1_then_sub_dmrrow0
0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmrrowp1_then_sub_dmrrow1
0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_wacc_hi_then_sub_dmrrow0
0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_wacc_hi_then_sub_dmrrow1
0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_wacc_hi_then_sub_dmrrowp0
0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_wacc_hi_then_sub_dmrrowp1
0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_dmrrow0
0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_dmrrow1
0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_dmrrowp0
0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_dmrrowp1
0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi
0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_wacc_lo
0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
4, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_gp8_x1_then_sub_32 -> GPRC_and_GPRC_NOR0
},
{ // VSLRC_with_sub_64_in_SPILLTOVSRRC
0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_32
23, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_64 -> SPILLTOVSRRC_and_F4RC
0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr0
0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1
0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrow0
0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrow1
0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp0
0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1
0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_eq
0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_gp8_x0
0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_gp8_x1
0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_gt
0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_lt
0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_pair0
0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1
0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_un
0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx0
0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx1
0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi
0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_lo
0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx1_then_sub_64
0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_64
0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx0
0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1
0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1_then_sub_64
0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1_then_sub_dmrrow0
0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1_then_sub_dmrrow1
0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrow0
0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrow1
0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp0
0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1
0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrow0
0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrow1
0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp0
0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1
0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi
0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_lo
0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_gp8_x1_then_sub_32
},
{ // DMRROWpRC
0, // DMRROWpRC:sub_32
0, // DMRROWpRC:sub_64
0, // DMRROWpRC:sub_dmr0
0, // DMRROWpRC:sub_dmr1
26, // DMRROWpRC:sub_dmrrow0 -> DMRROWRC
26, // DMRROWpRC:sub_dmrrow1 -> DMRROWRC
0, // DMRROWpRC:sub_dmrrowp0
0, // DMRROWpRC:sub_dmrrowp1
0, // DMRROWpRC:sub_eq
0, // DMRROWpRC:sub_gp8_x0
0, // DMRROWpRC:sub_gp8_x1
0, // DMRROWpRC:sub_gt
0, // DMRROWpRC:sub_lt
0, // DMRROWpRC:sub_pair0
0, // DMRROWpRC:sub_pair1
0, // DMRROWpRC:sub_un
0, // DMRROWpRC:sub_vsx0
0, // DMRROWpRC:sub_vsx1
0, // DMRROWpRC:sub_wacc_hi
0, // DMRROWpRC:sub_wacc_lo
0, // DMRROWpRC:sub_vsx1_then_sub_64
0, // DMRROWpRC:sub_pair1_then_sub_64
0, // DMRROWpRC:sub_pair1_then_sub_vsx0
0, // DMRROWpRC:sub_pair1_then_sub_vsx1
0, // DMRROWpRC:sub_pair1_then_sub_vsx1_then_sub_64
0, // DMRROWpRC:sub_dmrrowp1_then_sub_dmrrow0
0, // DMRROWpRC:sub_dmrrowp1_then_sub_dmrrow1
0, // DMRROWpRC:sub_wacc_hi_then_sub_dmrrow0
0, // DMRROWpRC:sub_wacc_hi_then_sub_dmrrow1
0, // DMRROWpRC:sub_wacc_hi_then_sub_dmrrowp0
0, // DMRROWpRC:sub_wacc_hi_then_sub_dmrrowp1
0, // DMRROWpRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // DMRROWpRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // DMRROWpRC:sub_dmr1_then_sub_dmrrow0
0, // DMRROWpRC:sub_dmr1_then_sub_dmrrow1
0, // DMRROWpRC:sub_dmr1_then_sub_dmrrowp0
0, // DMRROWpRC:sub_dmr1_then_sub_dmrrowp1
0, // DMRROWpRC:sub_dmr1_then_sub_wacc_hi
0, // DMRROWpRC:sub_dmr1_then_sub_wacc_lo
0, // DMRROWpRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
0, // DMRROWpRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
0, // DMRROWpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
0, // DMRROWpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
0, // DMRROWpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
0, // DMRROWpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
0, // DMRROWpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // DMRROWpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // DMRROWpRC:sub_gp8_x1_then_sub_32
},
{ // VSRpRC
0, // VSRpRC:sub_32
13, // VSRpRC:sub_64 -> VSFRC
0, // VSRpRC:sub_dmr0
0, // VSRpRC:sub_dmr1
0, // VSRpRC:sub_dmrrow0
0, // VSRpRC:sub_dmrrow1
0, // VSRpRC:sub_dmrrowp0
0, // VSRpRC:sub_dmrrowp1
0, // VSRpRC:sub_eq
0, // VSRpRC:sub_gp8_x0
0, // VSRpRC:sub_gp8_x1
0, // VSRpRC:sub_gt
0, // VSRpRC:sub_lt
0, // VSRpRC:sub_pair0
0, // VSRpRC:sub_pair1
0, // VSRpRC:sub_un
27, // VSRpRC:sub_vsx0 -> VSRC
27, // VSRpRC:sub_vsx1 -> VSRC
0, // VSRpRC:sub_wacc_hi
0, // VSRpRC:sub_wacc_lo
13, // VSRpRC:sub_vsx1_then_sub_64 -> VSFRC
0, // VSRpRC:sub_pair1_then_sub_64
0, // VSRpRC:sub_pair1_then_sub_vsx0
0, // VSRpRC:sub_pair1_then_sub_vsx1
0, // VSRpRC:sub_pair1_then_sub_vsx1_then_sub_64
0, // VSRpRC:sub_dmrrowp1_then_sub_dmrrow0
0, // VSRpRC:sub_dmrrowp1_then_sub_dmrrow1
0, // VSRpRC:sub_wacc_hi_then_sub_dmrrow0
0, // VSRpRC:sub_wacc_hi_then_sub_dmrrow1
0, // VSRpRC:sub_wacc_hi_then_sub_dmrrowp0
0, // VSRpRC:sub_wacc_hi_then_sub_dmrrowp1
0, // VSRpRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // VSRpRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // VSRpRC:sub_dmr1_then_sub_dmrrow0
0, // VSRpRC:sub_dmr1_then_sub_dmrrow1
0, // VSRpRC:sub_dmr1_then_sub_dmrrowp0
0, // VSRpRC:sub_dmr1_then_sub_dmrrowp1
0, // VSRpRC:sub_dmr1_then_sub_wacc_hi
0, // VSRpRC:sub_dmr1_then_sub_wacc_lo
0, // VSRpRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
0, // VSRpRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
0, // VSRpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
0, // VSRpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
0, // VSRpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
0, // VSRpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
0, // VSRpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // VSRpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // VSRpRC:sub_gp8_x1_then_sub_32
},
{ // VSRpRC_with_sub_64_in_SPILLTOVSRRC
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_32
16, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_64 -> SPILLTOVSRRC_and_VSFRC
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr0
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrow0
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrow1
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp0
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_eq
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_gp8_x0
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_gp8_x1
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_gt
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_lt
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_pair0
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_un
28, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx0 -> VSRC_with_sub_64_in_SPILLTOVSRRC
28, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx1 -> VSRC_with_sub_64_in_SPILLTOVSRRC
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_lo
16, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx1_then_sub_64 -> SPILLTOVSRRC_and_VSFRC
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_64
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx0
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1_then_sub_64
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1_then_sub_dmrrow0
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1_then_sub_dmrrow1
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrow0
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrow1
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp0
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrow0
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrow1
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp0
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_lo
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_gp8_x1_then_sub_32
},
{ // VSRpRC_with_sub_64_in_F4RC
0, // VSRpRC_with_sub_64_in_F4RC:sub_32
18, // VSRpRC_with_sub_64_in_F4RC:sub_64 -> F8RC
0, // VSRpRC_with_sub_64_in_F4RC:sub_dmr0
0, // VSRpRC_with_sub_64_in_F4RC:sub_dmr1
0, // VSRpRC_with_sub_64_in_F4RC:sub_dmrrow0
0, // VSRpRC_with_sub_64_in_F4RC:sub_dmrrow1
0, // VSRpRC_with_sub_64_in_F4RC:sub_dmrrowp0
0, // VSRpRC_with_sub_64_in_F4RC:sub_dmrrowp1
0, // VSRpRC_with_sub_64_in_F4RC:sub_eq
0, // VSRpRC_with_sub_64_in_F4RC:sub_gp8_x0
0, // VSRpRC_with_sub_64_in_F4RC:sub_gp8_x1
0, // VSRpRC_with_sub_64_in_F4RC:sub_gt
0, // VSRpRC_with_sub_64_in_F4RC:sub_lt
0, // VSRpRC_with_sub_64_in_F4RC:sub_pair0
0, // VSRpRC_with_sub_64_in_F4RC:sub_pair1
0, // VSRpRC_with_sub_64_in_F4RC:sub_un
30, // VSRpRC_with_sub_64_in_F4RC:sub_vsx0 -> VSLRC
30, // VSRpRC_with_sub_64_in_F4RC:sub_vsx1 -> VSLRC
0, // VSRpRC_with_sub_64_in_F4RC:sub_wacc_hi
0, // VSRpRC_with_sub_64_in_F4RC:sub_wacc_lo
18, // VSRpRC_with_sub_64_in_F4RC:sub_vsx1_then_sub_64 -> F8RC
0, // VSRpRC_with_sub_64_in_F4RC:sub_pair1_then_sub_64
0, // VSRpRC_with_sub_64_in_F4RC:sub_pair1_then_sub_vsx0
0, // VSRpRC_with_sub_64_in_F4RC:sub_pair1_then_sub_vsx1
0, // VSRpRC_with_sub_64_in_F4RC:sub_pair1_then_sub_vsx1_then_sub_64
0, // VSRpRC_with_sub_64_in_F4RC:sub_dmrrowp1_then_sub_dmrrow0
0, // VSRpRC_with_sub_64_in_F4RC:sub_dmrrowp1_then_sub_dmrrow1
0, // VSRpRC_with_sub_64_in_F4RC:sub_wacc_hi_then_sub_dmrrow0
0, // VSRpRC_with_sub_64_in_F4RC:sub_wacc_hi_then_sub_dmrrow1
0, // VSRpRC_with_sub_64_in_F4RC:sub_wacc_hi_then_sub_dmrrowp0
0, // VSRpRC_with_sub_64_in_F4RC:sub_wacc_hi_then_sub_dmrrowp1
0, // VSRpRC_with_sub_64_in_F4RC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // VSRpRC_with_sub_64_in_F4RC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // VSRpRC_with_sub_64_in_F4RC:sub_dmr1_then_sub_dmrrow0
0, // VSRpRC_with_sub_64_in_F4RC:sub_dmr1_then_sub_dmrrow1
0, // VSRpRC_with_sub_64_in_F4RC:sub_dmr1_then_sub_dmrrowp0
0, // VSRpRC_with_sub_64_in_F4RC:sub_dmr1_then_sub_dmrrowp1
0, // VSRpRC_with_sub_64_in_F4RC:sub_dmr1_then_sub_wacc_hi
0, // VSRpRC_with_sub_64_in_F4RC:sub_dmr1_then_sub_wacc_lo
0, // VSRpRC_with_sub_64_in_F4RC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
0, // VSRpRC_with_sub_64_in_F4RC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
0, // VSRpRC_with_sub_64_in_F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
0, // VSRpRC_with_sub_64_in_F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
0, // VSRpRC_with_sub_64_in_F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
0, // VSRpRC_with_sub_64_in_F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
0, // VSRpRC_with_sub_64_in_F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // VSRpRC_with_sub_64_in_F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // VSRpRC_with_sub_64_in_F4RC:sub_gp8_x1_then_sub_32
},
{ // VSRpRC_with_sub_64_in_VFRC
0, // VSRpRC_with_sub_64_in_VFRC:sub_32
20, // VSRpRC_with_sub_64_in_VFRC:sub_64 -> VFRC
0, // VSRpRC_with_sub_64_in_VFRC:sub_dmr0
0, // VSRpRC_with_sub_64_in_VFRC:sub_dmr1
0, // VSRpRC_with_sub_64_in_VFRC:sub_dmrrow0
0, // VSRpRC_with_sub_64_in_VFRC:sub_dmrrow1
0, // VSRpRC_with_sub_64_in_VFRC:sub_dmrrowp0
0, // VSRpRC_with_sub_64_in_VFRC:sub_dmrrowp1
0, // VSRpRC_with_sub_64_in_VFRC:sub_eq
0, // VSRpRC_with_sub_64_in_VFRC:sub_gp8_x0
0, // VSRpRC_with_sub_64_in_VFRC:sub_gp8_x1
0, // VSRpRC_with_sub_64_in_VFRC:sub_gt
0, // VSRpRC_with_sub_64_in_VFRC:sub_lt
0, // VSRpRC_with_sub_64_in_VFRC:sub_pair0
0, // VSRpRC_with_sub_64_in_VFRC:sub_pair1
0, // VSRpRC_with_sub_64_in_VFRC:sub_un
29, // VSRpRC_with_sub_64_in_VFRC:sub_vsx0 -> VRRC
29, // VSRpRC_with_sub_64_in_VFRC:sub_vsx1 -> VRRC
0, // VSRpRC_with_sub_64_in_VFRC:sub_wacc_hi
0, // VSRpRC_with_sub_64_in_VFRC:sub_wacc_lo
20, // VSRpRC_with_sub_64_in_VFRC:sub_vsx1_then_sub_64 -> VFRC
0, // VSRpRC_with_sub_64_in_VFRC:sub_pair1_then_sub_64
0, // VSRpRC_with_sub_64_in_VFRC:sub_pair1_then_sub_vsx0
0, // VSRpRC_with_sub_64_in_VFRC:sub_pair1_then_sub_vsx1
0, // VSRpRC_with_sub_64_in_VFRC:sub_pair1_then_sub_vsx1_then_sub_64
0, // VSRpRC_with_sub_64_in_VFRC:sub_dmrrowp1_then_sub_dmrrow0
0, // VSRpRC_with_sub_64_in_VFRC:sub_dmrrowp1_then_sub_dmrrow1
0, // VSRpRC_with_sub_64_in_VFRC:sub_wacc_hi_then_sub_dmrrow0
0, // VSRpRC_with_sub_64_in_VFRC:sub_wacc_hi_then_sub_dmrrow1
0, // VSRpRC_with_sub_64_in_VFRC:sub_wacc_hi_then_sub_dmrrowp0
0, // VSRpRC_with_sub_64_in_VFRC:sub_wacc_hi_then_sub_dmrrowp1
0, // VSRpRC_with_sub_64_in_VFRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // VSRpRC_with_sub_64_in_VFRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // VSRpRC_with_sub_64_in_VFRC:sub_dmr1_then_sub_dmrrow0
0, // VSRpRC_with_sub_64_in_VFRC:sub_dmr1_then_sub_dmrrow1
0, // VSRpRC_with_sub_64_in_VFRC:sub_dmr1_then_sub_dmrrowp0
0, // VSRpRC_with_sub_64_in_VFRC:sub_dmr1_then_sub_dmrrowp1
0, // VSRpRC_with_sub_64_in_VFRC:sub_dmr1_then_sub_wacc_hi
0, // VSRpRC_with_sub_64_in_VFRC:sub_dmr1_then_sub_wacc_lo
0, // VSRpRC_with_sub_64_in_VFRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
0, // VSRpRC_with_sub_64_in_VFRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
0, // VSRpRC_with_sub_64_in_VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
0, // VSRpRC_with_sub_64_in_VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
0, // VSRpRC_with_sub_64_in_VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
0, // VSRpRC_with_sub_64_in_VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
0, // VSRpRC_with_sub_64_in_VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // VSRpRC_with_sub_64_in_VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // VSRpRC_with_sub_64_in_VFRC:sub_gp8_x1_then_sub_32
},
{ // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_32
22, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_64 -> SPILLTOVSRRC_and_VFRC
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmr0
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmr1
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmrrow0
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmrrow1
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmrrowp0
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmrrowp1
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_eq
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_gp8_x0
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_gp8_x1
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_gt
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_lt
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_pair0
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_pair1
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_un
31, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_vsx0 -> VRRC_with_sub_64_in_SPILLTOVSRRC
31, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_vsx1 -> VRRC_with_sub_64_in_SPILLTOVSRRC
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_wacc_hi
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_wacc_lo
22, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_vsx1_then_sub_64 -> SPILLTOVSRRC_and_VFRC
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_pair1_then_sub_64
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_pair1_then_sub_vsx0
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_pair1_then_sub_vsx1
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_pair1_then_sub_vsx1_then_sub_64
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmrrowp1_then_sub_dmrrow0
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmrrowp1_then_sub_dmrrow1
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_wacc_hi_then_sub_dmrrow0
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_wacc_hi_then_sub_dmrrow1
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_wacc_hi_then_sub_dmrrowp0
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_wacc_hi_then_sub_dmrrowp1
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_dmrrow0
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_dmrrow1
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_dmrrowp0
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_dmrrowp1
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_wacc_hi
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_wacc_lo
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_gp8_x1_then_sub_32
},
{ // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_32
23, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_64 -> SPILLTOVSRRC_and_F4RC
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmr0
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmr1
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmrrow0
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmrrow1
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmrrowp0
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmrrowp1
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_eq
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_gp8_x0
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_gp8_x1
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_gt
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_lt
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_pair0
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_pair1
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_un
34, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_vsx0 -> VSLRC_with_sub_64_in_SPILLTOVSRRC
34, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_vsx1 -> VSLRC_with_sub_64_in_SPILLTOVSRRC
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_wacc_hi
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_wacc_lo
23, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_vsx1_then_sub_64 -> SPILLTOVSRRC_and_F4RC
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_pair1_then_sub_64
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_pair1_then_sub_vsx0
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_pair1_then_sub_vsx1
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_pair1_then_sub_vsx1_then_sub_64
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmrrowp1_then_sub_dmrrow0
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmrrowp1_then_sub_dmrrow1
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_wacc_hi_then_sub_dmrrow0
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_wacc_hi_then_sub_dmrrow1
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_wacc_hi_then_sub_dmrrowp0
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_wacc_hi_then_sub_dmrrowp1
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_dmrrow0
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_dmrrow1
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_dmrrowp0
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_dmrrowp1
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_wacc_hi
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_wacc_lo
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_gp8_x1_then_sub_32
},
{ // ACCRC
0, // ACCRC:sub_32
18, // ACCRC:sub_64 -> F8RC
0, // ACCRC:sub_dmr0
0, // ACCRC:sub_dmr1
0, // ACCRC:sub_dmrrow0
0, // ACCRC:sub_dmrrow1
0, // ACCRC:sub_dmrrowp0
0, // ACCRC:sub_dmrrowp1
0, // ACCRC:sub_eq
0, // ACCRC:sub_gp8_x0
0, // ACCRC:sub_gp8_x1
0, // ACCRC:sub_gt
0, // ACCRC:sub_lt
38, // ACCRC:sub_pair0 -> VSRpRC_with_sub_64_in_F4RC
38, // ACCRC:sub_pair1 -> VSRpRC_with_sub_64_in_F4RC
0, // ACCRC:sub_un
30, // ACCRC:sub_vsx0 -> VSLRC
30, // ACCRC:sub_vsx1 -> VSLRC
0, // ACCRC:sub_wacc_hi
0, // ACCRC:sub_wacc_lo
18, // ACCRC:sub_vsx1_then_sub_64 -> F8RC
18, // ACCRC:sub_pair1_then_sub_64 -> F8RC
30, // ACCRC:sub_pair1_then_sub_vsx0 -> VSLRC
30, // ACCRC:sub_pair1_then_sub_vsx1 -> VSLRC
18, // ACCRC:sub_pair1_then_sub_vsx1_then_sub_64 -> F8RC
0, // ACCRC:sub_dmrrowp1_then_sub_dmrrow0
0, // ACCRC:sub_dmrrowp1_then_sub_dmrrow1
0, // ACCRC:sub_wacc_hi_then_sub_dmrrow0
0, // ACCRC:sub_wacc_hi_then_sub_dmrrow1
0, // ACCRC:sub_wacc_hi_then_sub_dmrrowp0
0, // ACCRC:sub_wacc_hi_then_sub_dmrrowp1
0, // ACCRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // ACCRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // ACCRC:sub_dmr1_then_sub_dmrrow0
0, // ACCRC:sub_dmr1_then_sub_dmrrow1
0, // ACCRC:sub_dmr1_then_sub_dmrrowp0
0, // ACCRC:sub_dmr1_then_sub_dmrrowp1
0, // ACCRC:sub_dmr1_then_sub_wacc_hi
0, // ACCRC:sub_dmr1_then_sub_wacc_lo
0, // ACCRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
0, // ACCRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
0, // ACCRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
0, // ACCRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
0, // ACCRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
0, // ACCRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
0, // ACCRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // ACCRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // ACCRC:sub_gp8_x1_then_sub_32
},
{ // UACCRC
0, // UACCRC:sub_32
18, // UACCRC:sub_64 -> F8RC
0, // UACCRC:sub_dmr0
0, // UACCRC:sub_dmr1
0, // UACCRC:sub_dmrrow0
0, // UACCRC:sub_dmrrow1
0, // UACCRC:sub_dmrrowp0
0, // UACCRC:sub_dmrrowp1
0, // UACCRC:sub_eq
0, // UACCRC:sub_gp8_x0
0, // UACCRC:sub_gp8_x1
0, // UACCRC:sub_gt
0, // UACCRC:sub_lt
38, // UACCRC:sub_pair0 -> VSRpRC_with_sub_64_in_F4RC
38, // UACCRC:sub_pair1 -> VSRpRC_with_sub_64_in_F4RC
0, // UACCRC:sub_un
30, // UACCRC:sub_vsx0 -> VSLRC
30, // UACCRC:sub_vsx1 -> VSLRC
0, // UACCRC:sub_wacc_hi
0, // UACCRC:sub_wacc_lo
18, // UACCRC:sub_vsx1_then_sub_64 -> F8RC
18, // UACCRC:sub_pair1_then_sub_64 -> F8RC
30, // UACCRC:sub_pair1_then_sub_vsx0 -> VSLRC
30, // UACCRC:sub_pair1_then_sub_vsx1 -> VSLRC
18, // UACCRC:sub_pair1_then_sub_vsx1_then_sub_64 -> F8RC
0, // UACCRC:sub_dmrrowp1_then_sub_dmrrow0
0, // UACCRC:sub_dmrrowp1_then_sub_dmrrow1
0, // UACCRC:sub_wacc_hi_then_sub_dmrrow0
0, // UACCRC:sub_wacc_hi_then_sub_dmrrow1
0, // UACCRC:sub_wacc_hi_then_sub_dmrrowp0
0, // UACCRC:sub_wacc_hi_then_sub_dmrrowp1
0, // UACCRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // UACCRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // UACCRC:sub_dmr1_then_sub_dmrrow0
0, // UACCRC:sub_dmr1_then_sub_dmrrow1
0, // UACCRC:sub_dmr1_then_sub_dmrrowp0
0, // UACCRC:sub_dmr1_then_sub_dmrrowp1
0, // UACCRC:sub_dmr1_then_sub_wacc_hi
0, // UACCRC:sub_dmr1_then_sub_wacc_lo
0, // UACCRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
0, // UACCRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
0, // UACCRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
0, // UACCRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
0, // UACCRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
0, // UACCRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
0, // UACCRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // UACCRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // UACCRC:sub_gp8_x1_then_sub_32
},
{ // WACCRC
0, // WACCRC:sub_32
0, // WACCRC:sub_64
0, // WACCRC:sub_dmr0
0, // WACCRC:sub_dmr1
26, // WACCRC:sub_dmrrow0 -> DMRROWRC
26, // WACCRC:sub_dmrrow1 -> DMRROWRC
35, // WACCRC:sub_dmrrowp0 -> DMRROWpRC
35, // WACCRC:sub_dmrrowp1 -> DMRROWpRC
0, // WACCRC:sub_eq
0, // WACCRC:sub_gp8_x0
0, // WACCRC:sub_gp8_x1
0, // WACCRC:sub_gt
0, // WACCRC:sub_lt
0, // WACCRC:sub_pair0
0, // WACCRC:sub_pair1
0, // WACCRC:sub_un
0, // WACCRC:sub_vsx0
0, // WACCRC:sub_vsx1
0, // WACCRC:sub_wacc_hi
0, // WACCRC:sub_wacc_lo
0, // WACCRC:sub_vsx1_then_sub_64
0, // WACCRC:sub_pair1_then_sub_64
0, // WACCRC:sub_pair1_then_sub_vsx0
0, // WACCRC:sub_pair1_then_sub_vsx1
0, // WACCRC:sub_pair1_then_sub_vsx1_then_sub_64
26, // WACCRC:sub_dmrrowp1_then_sub_dmrrow0 -> DMRROWRC
26, // WACCRC:sub_dmrrowp1_then_sub_dmrrow1 -> DMRROWRC
0, // WACCRC:sub_wacc_hi_then_sub_dmrrow0
0, // WACCRC:sub_wacc_hi_then_sub_dmrrow1
0, // WACCRC:sub_wacc_hi_then_sub_dmrrowp0
0, // WACCRC:sub_wacc_hi_then_sub_dmrrowp1
0, // WACCRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // WACCRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // WACCRC:sub_dmr1_then_sub_dmrrow0
0, // WACCRC:sub_dmr1_then_sub_dmrrow1
0, // WACCRC:sub_dmr1_then_sub_dmrrowp0
0, // WACCRC:sub_dmr1_then_sub_dmrrowp1
0, // WACCRC:sub_dmr1_then_sub_wacc_hi
0, // WACCRC:sub_dmr1_then_sub_wacc_lo
0, // WACCRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
0, // WACCRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
0, // WACCRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
0, // WACCRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
0, // WACCRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
0, // WACCRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
0, // WACCRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // WACCRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // WACCRC:sub_gp8_x1_then_sub_32
},
{ // WACC_HIRC
0, // WACC_HIRC:sub_32
0, // WACC_HIRC:sub_64
0, // WACC_HIRC:sub_dmr0
0, // WACC_HIRC:sub_dmr1
26, // WACC_HIRC:sub_dmrrow0 -> DMRROWRC
26, // WACC_HIRC:sub_dmrrow1 -> DMRROWRC
35, // WACC_HIRC:sub_dmrrowp0 -> DMRROWpRC
35, // WACC_HIRC:sub_dmrrowp1 -> DMRROWpRC
0, // WACC_HIRC:sub_eq
0, // WACC_HIRC:sub_gp8_x0
0, // WACC_HIRC:sub_gp8_x1
0, // WACC_HIRC:sub_gt
0, // WACC_HIRC:sub_lt
0, // WACC_HIRC:sub_pair0
0, // WACC_HIRC:sub_pair1
0, // WACC_HIRC:sub_un
0, // WACC_HIRC:sub_vsx0
0, // WACC_HIRC:sub_vsx1
0, // WACC_HIRC:sub_wacc_hi
0, // WACC_HIRC:sub_wacc_lo
0, // WACC_HIRC:sub_vsx1_then_sub_64
0, // WACC_HIRC:sub_pair1_then_sub_64
0, // WACC_HIRC:sub_pair1_then_sub_vsx0
0, // WACC_HIRC:sub_pair1_then_sub_vsx1
0, // WACC_HIRC:sub_pair1_then_sub_vsx1_then_sub_64
26, // WACC_HIRC:sub_dmrrowp1_then_sub_dmrrow0 -> DMRROWRC
26, // WACC_HIRC:sub_dmrrowp1_then_sub_dmrrow1 -> DMRROWRC
0, // WACC_HIRC:sub_wacc_hi_then_sub_dmrrow0
0, // WACC_HIRC:sub_wacc_hi_then_sub_dmrrow1
0, // WACC_HIRC:sub_wacc_hi_then_sub_dmrrowp0
0, // WACC_HIRC:sub_wacc_hi_then_sub_dmrrowp1
0, // WACC_HIRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // WACC_HIRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // WACC_HIRC:sub_dmr1_then_sub_dmrrow0
0, // WACC_HIRC:sub_dmr1_then_sub_dmrrow1
0, // WACC_HIRC:sub_dmr1_then_sub_dmrrowp0
0, // WACC_HIRC:sub_dmr1_then_sub_dmrrowp1
0, // WACC_HIRC:sub_dmr1_then_sub_wacc_hi
0, // WACC_HIRC:sub_dmr1_then_sub_wacc_lo
0, // WACC_HIRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
0, // WACC_HIRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
0, // WACC_HIRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
0, // WACC_HIRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
0, // WACC_HIRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
0, // WACC_HIRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
0, // WACC_HIRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // WACC_HIRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // WACC_HIRC:sub_gp8_x1_then_sub_32
},
{ // ACCRC_with_sub_64_in_SPILLTOVSRRC
0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_32
23, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_64 -> SPILLTOVSRRC_and_F4RC
0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr0
0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1
0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrow0
0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrow1
0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp0
0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1
0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_eq
0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_gp8_x0
0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_gp8_x1
0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_gt
0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_lt
41, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_pair0 -> VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC
38, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1 -> VSRpRC_with_sub_64_in_F4RC
0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_un
34, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx0 -> VSLRC_with_sub_64_in_SPILLTOVSRRC
34, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx1 -> VSLRC_with_sub_64_in_SPILLTOVSRRC
0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi
0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_lo
23, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx1_then_sub_64 -> SPILLTOVSRRC_and_F4RC
18, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_64 -> F8RC
30, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx0 -> VSLRC
30, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1 -> VSLRC
18, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1_then_sub_64 -> F8RC
0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1_then_sub_dmrrow0
0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1_then_sub_dmrrow1
0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrow0
0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrow1
0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp0
0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1
0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrow0
0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrow1
0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp0
0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1
0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi
0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_lo
0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_gp8_x1_then_sub_32
},
{ // UACCRC_with_sub_64_in_SPILLTOVSRRC
0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_32
23, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_64 -> SPILLTOVSRRC_and_F4RC
0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr0
0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1
0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrow0
0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrow1
0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp0
0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1
0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_eq
0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_gp8_x0
0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_gp8_x1
0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_gt
0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_lt
41, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_pair0 -> VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC
38, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1 -> VSRpRC_with_sub_64_in_F4RC
0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_un
34, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx0 -> VSLRC_with_sub_64_in_SPILLTOVSRRC
34, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx1 -> VSLRC_with_sub_64_in_SPILLTOVSRRC
0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi
0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_lo
23, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx1_then_sub_64 -> SPILLTOVSRRC_and_F4RC
18, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_64 -> F8RC
30, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx0 -> VSLRC
30, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1 -> VSLRC
18, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1_then_sub_64 -> F8RC
0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1_then_sub_dmrrow0
0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1_then_sub_dmrrow1
0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrow0
0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrow1
0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp0
0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1
0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrow0
0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrow1
0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp0
0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1
0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi
0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_lo
0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_gp8_x1_then_sub_32
},
{ // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_32
23, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_64 -> SPILLTOVSRRC_and_F4RC
0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr0
0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1
0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmrrow0
0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmrrow1
0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmrrowp0
0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1
0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_eq
0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_gp8_x0
0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_gp8_x1
0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_gt
0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_lt
41, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_pair0 -> VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC
41, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_pair1 -> VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC
0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_un
34, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_vsx0 -> VSLRC_with_sub_64_in_SPILLTOVSRRC
34, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_vsx1 -> VSLRC_with_sub_64_in_SPILLTOVSRRC
0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_wacc_hi
0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_wacc_lo
23, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_vsx1_then_sub_64 -> SPILLTOVSRRC_and_F4RC
23, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_64 -> SPILLTOVSRRC_and_F4RC
34, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx0 -> VSLRC_with_sub_64_in_SPILLTOVSRRC
34, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1 -> VSLRC_with_sub_64_in_SPILLTOVSRRC
23, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1_then_sub_64 -> SPILLTOVSRRC_and_F4RC
0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1_then_sub_dmrrow0
0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1_then_sub_dmrrow1
0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrow0
0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrow1
0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp0
0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1
0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrow0
0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrow1
0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp0
0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1
0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi
0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_lo
0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_gp8_x1_then_sub_32
},
{ // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_32
23, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_64 -> SPILLTOVSRRC_and_F4RC
0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr0
0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1
0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmrrow0
0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmrrow1
0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmrrowp0
0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1
0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_eq
0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_gp8_x0
0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_gp8_x1
0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_gt
0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_lt
41, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_pair0 -> VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC
41, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_pair1 -> VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC
0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_un
34, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_vsx0 -> VSLRC_with_sub_64_in_SPILLTOVSRRC
34, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_vsx1 -> VSLRC_with_sub_64_in_SPILLTOVSRRC
0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_wacc_hi
0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_wacc_lo
23, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_vsx1_then_sub_64 -> SPILLTOVSRRC_and_F4RC
23, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_64 -> SPILLTOVSRRC_and_F4RC
34, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx0 -> VSLRC_with_sub_64_in_SPILLTOVSRRC
34, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1 -> VSLRC_with_sub_64_in_SPILLTOVSRRC
23, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1_then_sub_64 -> SPILLTOVSRRC_and_F4RC
0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1_then_sub_dmrrow0
0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1_then_sub_dmrrow1
0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrow0
0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrow1
0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp0
0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1
0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrow0
0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrow1
0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp0
0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1
0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi
0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_lo
0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_gp8_x1_then_sub_32
},
{ // DMRRC
0, // DMRRC:sub_32
0, // DMRRC:sub_64
0, // DMRRC:sub_dmr0
0, // DMRRC:sub_dmr1
26, // DMRRC:sub_dmrrow0 -> DMRROWRC
26, // DMRRC:sub_dmrrow1 -> DMRROWRC
35, // DMRRC:sub_dmrrowp0 -> DMRROWpRC
35, // DMRRC:sub_dmrrowp1 -> DMRROWpRC
0, // DMRRC:sub_eq
0, // DMRRC:sub_gp8_x0
0, // DMRRC:sub_gp8_x1
0, // DMRRC:sub_gt
0, // DMRRC:sub_lt
0, // DMRRC:sub_pair0
0, // DMRRC:sub_pair1
0, // DMRRC:sub_un
0, // DMRRC:sub_vsx0
0, // DMRRC:sub_vsx1
45, // DMRRC:sub_wacc_hi -> WACC_HIRC
44, // DMRRC:sub_wacc_lo -> WACCRC
0, // DMRRC:sub_vsx1_then_sub_64
0, // DMRRC:sub_pair1_then_sub_64
0, // DMRRC:sub_pair1_then_sub_vsx0
0, // DMRRC:sub_pair1_then_sub_vsx1
0, // DMRRC:sub_pair1_then_sub_vsx1_then_sub_64
26, // DMRRC:sub_dmrrowp1_then_sub_dmrrow0 -> DMRROWRC
26, // DMRRC:sub_dmrrowp1_then_sub_dmrrow1 -> DMRROWRC
26, // DMRRC:sub_wacc_hi_then_sub_dmrrow0 -> DMRROWRC
26, // DMRRC:sub_wacc_hi_then_sub_dmrrow1 -> DMRROWRC
35, // DMRRC:sub_wacc_hi_then_sub_dmrrowp0 -> DMRROWpRC
35, // DMRRC:sub_wacc_hi_then_sub_dmrrowp1 -> DMRROWpRC
26, // DMRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0 -> DMRROWRC
26, // DMRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1 -> DMRROWRC
0, // DMRRC:sub_dmr1_then_sub_dmrrow0
0, // DMRRC:sub_dmr1_then_sub_dmrrow1
0, // DMRRC:sub_dmr1_then_sub_dmrrowp0
0, // DMRRC:sub_dmr1_then_sub_dmrrowp1
0, // DMRRC:sub_dmr1_then_sub_wacc_hi
0, // DMRRC:sub_dmr1_then_sub_wacc_lo
0, // DMRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
0, // DMRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
0, // DMRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
0, // DMRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
0, // DMRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
0, // DMRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
0, // DMRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
0, // DMRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
0, // DMRRC:sub_gp8_x1_then_sub_32
},
{ // DMRpRC
0, // DMRpRC:sub_32
0, // DMRpRC:sub_64
50, // DMRpRC:sub_dmr0 -> DMRRC
50, // DMRpRC:sub_dmr1 -> DMRRC
26, // DMRpRC:sub_dmrrow0 -> DMRROWRC
26, // DMRpRC:sub_dmrrow1 -> DMRROWRC
35, // DMRpRC:sub_dmrrowp0 -> DMRROWpRC
35, // DMRpRC:sub_dmrrowp1 -> DMRROWpRC
0, // DMRpRC:sub_eq
0, // DMRpRC:sub_gp8_x0
0, // DMRpRC:sub_gp8_x1
0, // DMRpRC:sub_gt
0, // DMRpRC:sub_lt
0, // DMRpRC:sub_pair0
0, // DMRpRC:sub_pair1
0, // DMRpRC:sub_un
0, // DMRpRC:sub_vsx0
0, // DMRpRC:sub_vsx1
45, // DMRpRC:sub_wacc_hi -> WACC_HIRC
44, // DMRpRC:sub_wacc_lo -> WACCRC
0, // DMRpRC:sub_vsx1_then_sub_64
0, // DMRpRC:sub_pair1_then_sub_64
0, // DMRpRC:sub_pair1_then_sub_vsx0
0, // DMRpRC:sub_pair1_then_sub_vsx1
0, // DMRpRC:sub_pair1_then_sub_vsx1_then_sub_64
26, // DMRpRC:sub_dmrrowp1_then_sub_dmrrow0 -> DMRROWRC
26, // DMRpRC:sub_dmrrowp1_then_sub_dmrrow1 -> DMRROWRC
26, // DMRpRC:sub_wacc_hi_then_sub_dmrrow0 -> DMRROWRC
26, // DMRpRC:sub_wacc_hi_then_sub_dmrrow1 -> DMRROWRC
35, // DMRpRC:sub_wacc_hi_then_sub_dmrrowp0 -> DMRROWpRC
35, // DMRpRC:sub_wacc_hi_then_sub_dmrrowp1 -> DMRROWpRC
26, // DMRpRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0 -> DMRROWRC
26, // DMRpRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1 -> DMRROWRC
26, // DMRpRC:sub_dmr1_then_sub_dmrrow0 -> DMRROWRC
26, // DMRpRC:sub_dmr1_then_sub_dmrrow1 -> DMRROWRC
35, // DMRpRC:sub_dmr1_then_sub_dmrrowp0 -> DMRROWpRC
35, // DMRpRC:sub_dmr1_then_sub_dmrrowp1 -> DMRROWpRC
45, // DMRpRC:sub_dmr1_then_sub_wacc_hi -> WACC_HIRC
44, // DMRpRC:sub_dmr1_then_sub_wacc_lo -> WACCRC
26, // DMRpRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0 -> DMRROWRC
26, // DMRpRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1 -> DMRROWRC
26, // DMRpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0 -> DMRROWRC
26, // DMRpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1 -> DMRROWRC
35, // DMRpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0 -> DMRROWpRC
35, // DMRpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1 -> DMRROWpRC
26, // DMRpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0 -> DMRROWRC
26, // DMRpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1 -> DMRROWRC
0, // DMRpRC:sub_gp8_x1_then_sub_32
},
};
assert(RC && "Missing regclass");
if (!Idx) return RC;
--Idx;
assert(Idx < 48 && "Bad subreg");
unsigned TV = Table[RC->getID()][Idx];
return TV ? getRegClass(TV - 1) : nullptr;
}
/// Get the weight in units of pressure for this register class.
const RegClassWeight &PPCGenRegisterInfo::
getRegClassWeight(const TargetRegisterClass *RC) const {
static const RegClassWeight RCWeightTable[] = {
{1, 64}, // VSSRC
{1, 34}, // GPRC
{1, 34}, // GPRC_NOR0
{1, 33}, // GPRC_and_GPRC_NOR0
{1, 32}, // CRBITRC
{1, 32}, // F4RC
{4, 32}, // CRRC
{1, 1}, // CARRYRC
{0, 0}, // CTRRC
{0, 0}, // LRRC
{1, 1}, // VRSAVERC
{1, 68}, // SPILLTOVSRRC
{1, 64}, // VSFRC
{1, 34}, // G8RC
{1, 34}, // G8RC_NOX0
{1, 34}, // SPILLTOVSRRC_and_VSFRC
{1, 33}, // G8RC_and_G8RC_NOX0
{1, 32}, // F8RC
{1, 32}, // SPERC
{1, 32}, // VFRC
{1, 31}, // SPERC_with_sub_32_in_GPRC_NOR0
{1, 20}, // SPILLTOVSRRC_and_VFRC
{1, 14}, // SPILLTOVSRRC_and_F4RC
{0, 0}, // CTRRC8
{0, 0}, // LR8RC
{1, 64}, // DMRROWRC
{1, 64}, // VSRC
{1, 34}, // VSRC_with_sub_64_in_SPILLTOVSRRC
{1, 32}, // VRRC
{1, 32}, // VSLRC
{1, 20}, // VRRC_with_sub_64_in_SPILLTOVSRRC
{2, 32}, // G8pRC
{2, 30}, // G8pRC_with_sub_32_in_GPRC_NOR0
{1, 14}, // VSLRC_with_sub_64_in_SPILLTOVSRRC
{2, 64}, // DMRROWpRC
{2, 64}, // VSRpRC
{2, 34}, // VSRpRC_with_sub_64_in_SPILLTOVSRRC
{2, 32}, // VSRpRC_with_sub_64_in_F4RC
{2, 32}, // VSRpRC_with_sub_64_in_VFRC
{2, 20}, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC
{2, 14}, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC
{4, 32}, // ACCRC
{4, 32}, // UACCRC
{4, 32}, // WACCRC
{4, 32}, // WACC_HIRC
{4, 16}, // ACCRC_with_sub_64_in_SPILLTOVSRRC
{4, 16}, // UACCRC_with_sub_64_in_SPILLTOVSRRC
{4, 12}, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
{4, 12}, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
{8, 64}, // DMRRC
{16, 64}, // DMRpRC
};
return RCWeightTable[RC->getID()];
}
/// Get the weight in units of pressure for this register unit.
unsigned PPCGenRegisterInfo::
getRegUnitWeight(unsigned RegUnit) const {
assert(RegUnit < 235 && "invalid register unit");
// All register units have unit weight.
return 1;
}
// Get the number of dimensions of register pressure.
unsigned PPCGenRegisterInfo::getNumRegPressureSets() const {
return 20;
}
// Get the name of this register unit pressure set.
const char *PPCGenRegisterInfo::
getRegPressureSetName(unsigned Idx) const {
static const char *PressureNameTable[] = {
"CARRYRC",
"VRSAVERC",
"SPILLTOVSRRC_and_F4RC",
"SPILLTOVSRRC_and_VFRC",
"CRBITRC",
"F4RC",
"VFRC",
"WACCRC",
"WACC_HIRC",
"GPRC",
"SPILLTOVSRRC_and_VSFRC",
"SPILLTOVSRRC_and_VSFRC_with_VFRC",
"F4RC_with_SPILLTOVSRRC_and_VSFRC",
"VSSRC",
"DMRROWRC",
"SPILLTOVSRRC",
"SPILLTOVSRRC_with_SPILLTOVSRRC_and_F4RC",
"SPILLTOVSRRC_with_VFRC",
"F4RC_with_SPILLTOVSRRC",
"VSSRC_with_SPILLTOVSRRC",
};
return PressureNameTable[Idx];
}
// Get the register unit pressure limit for this dimension.
// This limit must be adjusted dynamically for reserved registers.
unsigned PPCGenRegisterInfo::
getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
static const uint8_t PressureLimitTable[] = {
1, // 0: CARRYRC
1, // 1: VRSAVERC
16, // 2: SPILLTOVSRRC_and_F4RC
20, // 3: SPILLTOVSRRC_and_VFRC
32, // 4: CRBITRC
32, // 5: F4RC
32, // 6: VFRC
32, // 7: WACCRC
32, // 8: WACC_HIRC
35, // 9: GPRC
36, // 10: SPILLTOVSRRC_and_VSFRC
46, // 11: SPILLTOVSRRC_and_VSFRC_with_VFRC
52, // 12: F4RC_with_SPILLTOVSRRC_and_VSFRC
64, // 13: VSSRC
64, // 14: DMRROWRC
69, // 15: SPILLTOVSRRC
70, // 16: SPILLTOVSRRC_with_SPILLTOVSRRC_and_F4RC
80, // 17: SPILLTOVSRRC_with_VFRC
86, // 18: F4RC_with_SPILLTOVSRRC
98, // 19: VSSRC_with_SPILLTOVSRRC
};
return PressureLimitTable[Idx];
}
/// Table of pressure sets per register class or unit.
static const int RCSetsTable[] = {
/* 0 */ 0, -1,
/* 2 */ 1, -1,
/* 4 */ 4, -1,
/* 6 */ 7, 14, -1,
/* 9 */ 8, 14, -1,
/* 12 */ 9, 15, -1,
/* 15 */ 13, 19, -1,
/* 18 */ 6, 11, 13, 17, 19, -1,
/* 24 */ 5, 12, 13, 18, 19, -1,
/* 30 */ 2, 5, 10, 12, 13, 16, 18, 19, -1,
/* 39 */ 9, 15, 16, 17, 18, 19, -1,
/* 46 */ 2, 5, 10, 11, 12, 13, 15, 16, 17, 18, 19, -1,
/* 58 */ 3, 6, 10, 11, 12, 13, 15, 16, 17, 18, 19, -1,
};
/// Get the dimensions of register pressure impacted by this register class.
/// Returns a -1 terminated array of pressure set IDs
const int *PPCGenRegisterInfo::
getRegClassPressureSets(const TargetRegisterClass *RC) const {
static const uint8_t RCSetStartTable[] = {
15,39,12,39,4,24,4,0,1,1,2,40,15,39,12,48,39,24,39,18,39,58,46,1,1,7,15,48,18,24,58,39,39,46,7,15,48,24,18,58,46,24,24,6,9,30,30,46,46,7,7,};
return &RCSetsTable[RCSetStartTable[RC->getID()]];
}
/// Get the dimensions of register pressure impacted by this register unit.
/// Returns a -1 terminated array of pressure set IDs
const int *PPCGenRegisterInfo::
getRegUnitPressureSets(unsigned RegUnit) const {
assert(RegUnit < 235 && "invalid register unit");
static const uint8_t RUSetStartTable[] = {
39,0,1,39,1,1,1,2,12,46,46,46,46,46,46,46,46,46,46,46,46,46,46,30,30,24,24,24,24,24,24,24,24,24,24,24,24,24,24,24,24,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,1,6,6,6,6,9,9,9,9,6,6,6,6,9,9,9,9,6,6,6,6,9,9,9,9,6,6,6,6,9,9,9,9,6,6,6,6,9,9,9,9,6,6,6,6,9,9,9,9,6,6,6,6,9,9,9,9,6,6,6,6,9,9,9,9,1,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,58,58,58,58,58,58,58,58,58,58,58,58,58,58,58,58,58,58,58,58,18,18,18,18,18,18,18,18,18,18,18,18,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,};
return &RCSetsTable[RUSetStartTable[RegUnit]];
}
extern const MCRegisterDesc PPCRegDesc[];
extern const MCPhysReg PPCRegDiffLists[];
extern const LaneBitmask PPCLaneMaskLists[];
extern const char PPCRegStrings[];
extern const char PPCRegClassStrings[];
extern const MCPhysReg PPCRegUnitRoots[][2];
extern const uint16_t PPCSubRegIdxLists[];
extern const MCRegisterInfo::SubRegCoveredBits PPCSubRegIdxRanges[];
extern const uint16_t PPCRegEncodingTable[];
// PPC Dwarf<->LLVM register mappings.
extern const MCRegisterInfo::DwarfLLVMRegPair PPCDwarfFlavour0Dwarf2L[];
extern const unsigned PPCDwarfFlavour0Dwarf2LSize;
extern const MCRegisterInfo::DwarfLLVMRegPair PPCDwarfFlavour1Dwarf2L[];
extern const unsigned PPCDwarfFlavour1Dwarf2LSize;
extern const MCRegisterInfo::DwarfLLVMRegPair PPCEHFlavour0Dwarf2L[];
extern const unsigned PPCEHFlavour0Dwarf2LSize;
extern const MCRegisterInfo::DwarfLLVMRegPair PPCEHFlavour1Dwarf2L[];
extern const unsigned PPCEHFlavour1Dwarf2LSize;
extern const MCRegisterInfo::DwarfLLVMRegPair PPCDwarfFlavour0L2Dwarf[];
extern const unsigned PPCDwarfFlavour0L2DwarfSize;
extern const MCRegisterInfo::DwarfLLVMRegPair PPCDwarfFlavour1L2Dwarf[];
extern const unsigned PPCDwarfFlavour1L2DwarfSize;
extern const MCRegisterInfo::DwarfLLVMRegPair PPCEHFlavour0L2Dwarf[];
extern const unsigned PPCEHFlavour0L2DwarfSize;
extern const MCRegisterInfo::DwarfLLVMRegPair PPCEHFlavour1L2Dwarf[];
extern const unsigned PPCEHFlavour1L2DwarfSize;
PPCGenRegisterInfo::
PPCGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
unsigned PC, unsigned HwMode)
: TargetRegisterInfo(&PPCRegInfoDesc, RegisterClasses, RegisterClasses+51,
SubRegIndexNameTable, SubRegIndexLaneMaskTable,
LaneBitmask(0xFFFFFFFFFC000000), RegClassInfos, HwMode) {
InitMCRegisterInfo(PPCRegDesc, 500, RA, PC,
PPCMCRegisterClasses, 51,
PPCRegUnitRoots,
235,
PPCRegDiffLists,
PPCLaneMaskLists,
PPCRegStrings,
PPCRegClassStrings,
PPCSubRegIdxLists,
49,
PPCSubRegIdxRanges,
PPCRegEncodingTable);
switch (DwarfFlavour) {
default:
llvm_unreachable("Unknown DWARF flavour");
case 0:
mapDwarfRegsToLLVMRegs(PPCDwarfFlavour0Dwarf2L, PPCDwarfFlavour0Dwarf2LSize, false);
break;
case 1:
mapDwarfRegsToLLVMRegs(PPCDwarfFlavour1Dwarf2L, PPCDwarfFlavour1Dwarf2LSize, false);
break;
}
switch (EHFlavour) {
default:
llvm_unreachable("Unknown DWARF flavour");
case 0:
mapDwarfRegsToLLVMRegs(PPCEHFlavour0Dwarf2L, PPCEHFlavour0Dwarf2LSize, true);
break;
case 1:
mapDwarfRegsToLLVMRegs(PPCEHFlavour1Dwarf2L, PPCEHFlavour1Dwarf2LSize, true);
break;
}
switch (DwarfFlavour) {
default:
llvm_unreachable("Unknown DWARF flavour");
case 0:
mapLLVMRegsToDwarfRegs(PPCDwarfFlavour0L2Dwarf, PPCDwarfFlavour0L2DwarfSize, false);
break;
case 1:
mapLLVMRegsToDwarfRegs(PPCDwarfFlavour1L2Dwarf, PPCDwarfFlavour1L2DwarfSize, false);
break;
}
switch (EHFlavour) {
default:
llvm_unreachable("Unknown DWARF flavour");
case 0:
mapLLVMRegsToDwarfRegs(PPCEHFlavour0L2Dwarf, PPCEHFlavour0L2DwarfSize, true);
break;
case 1:
mapLLVMRegsToDwarfRegs(PPCEHFlavour1L2Dwarf, PPCEHFlavour1L2DwarfSize, true);
break;
}
}
static const MCPhysReg CSR_64_AllRegs_SaveList[] = { PPC::X0, PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, 0 };
static const uint32_t CSR_64_AllRegs_RegMask[] = { 0x0ff00400, 0x00000000, 0x00000000, 0x00000000, 0xfffffe00, 0xfe3fc9ff, 0x000007ff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xfffe3fc8, 0xffffffff, 0x0000000f, };
static const MCPhysReg CSR_64_AllRegs_AIX_Dflt_Altivec_SaveList[] = { PPC::X0, PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, PPC::V0, PPC::V1, PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19, 0 };
static const uint32_t CSR_64_AllRegs_AIX_Dflt_Altivec_RegMask[] = { 0x0ff00400, 0x00000000, 0x00000000, 0x00000000, 0xfffffe00, 0xfe3fc9ff, 0x000007ff, 0xfff80000, 0xfff8007f, 0x0000007f, 0x00000000, 0x00000000, 0x00000000, 0xfffe3fc8, 0xffffffff, 0x0000000f, };
static const MCPhysReg CSR_64_AllRegs_AIX_Dflt_VSX_SaveList[] = { PPC::X0, PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, PPC::V0, PPC::V1, PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, PPC::VSL0, PPC::VSL1, PPC::VSL2, PPC::VSL3, PPC::VSL4, PPC::VSL5, PPC::VSL6, PPC::VSL7, PPC::VSL8, PPC::VSL9, PPC::VSL10, PPC::VSL11, PPC::VSL12, PPC::VSL13, PPC::VSL14, PPC::VSL15, PPC::VSL16, PPC::VSL17, PPC::VSL18, PPC::VSL19, 0 };
static const uint32_t CSR_64_AllRegs_AIX_Dflt_VSX_RegMask[] = { 0x0ff00400, 0x00000000, 0x00000000, 0x00000000, 0xfffffe00, 0xfe3fc9ff, 0x000007ff, 0xfff80000, 0xffffffff, 0xffffffff, 0x0000007f, 0x00000000, 0x00000000, 0xfffe3fc8, 0xffffffff, 0x0000000f, };
static const MCPhysReg CSR_64_AllRegs_Altivec_SaveList[] = { PPC::X0, PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, PPC::V0, PPC::V1, PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, 0 };
static const uint32_t CSR_64_AllRegs_Altivec_RegMask[] = { 0x0ff00400, 0x00000000, 0x00000000, 0x00000000, 0xfffffe00, 0xfe3fc9ff, 0x000007ff, 0xfff80000, 0xffffffff, 0x0007ffff, 0x00000000, 0x00000000, 0x00000000, 0xfffe3fc8, 0xffffffff, 0x0000000f, };
static const MCPhysReg CSR_64_AllRegs_VSRP_SaveList[] = { PPC::X0, PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, PPC::V0, PPC::V1, PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, PPC::VSL0, PPC::VSL1, PPC::VSL2, PPC::VSL3, PPC::VSL4, PPC::VSL5, PPC::VSL6, PPC::VSL7, PPC::VSL8, PPC::VSL9, PPC::VSL10, PPC::VSL11, PPC::VSL12, PPC::VSL13, PPC::VSL14, PPC::VSL15, PPC::VSL16, PPC::VSL17, PPC::VSL18, PPC::VSL19, PPC::VSL20, PPC::VSL21, PPC::VSL22, PPC::VSL23, PPC::VSL24, PPC::VSL25, PPC::VSL26, PPC::VSL27, PPC::VSL28, PPC::VSL29, PPC::VSL30, PPC::VSL31, PPC::VSRp0, PPC::VSRp1, PPC::VSRp2, PPC::VSRp3, PPC::VSRp4, PPC::VSRp5, PPC::VSRp6, PPC::VSRp7, PPC::VSRp8, PPC::VSRp9, PPC::VSRp10, PPC::VSRp11, PPC::VSRp12, PPC::VSRp13, PPC::VSRp14, PPC::VSRp15, PPC::VSRp16, PPC::VSRp17, PPC::VSRp18, PPC::VSRp19, PPC::VSRp20, PPC::VSRp21, PPC::VSRp22, PPC::VSRp23, PPC::VSRp24, PPC::VSRp25, PPC::VSRp26, PPC::VSRp27, PPC::VSRp28, PPC::VSRp29, PPC::VSRp30, PPC::VSRp31, 0 };
static const uint32_t CSR_64_AllRegs_VSRP_RegMask[] = { 0x0ff00400, 0x00000000, 0x00000000, 0x00000000, 0xfffffe00, 0xfe3fc9ff, 0x000007ff, 0xfff80000, 0xffffffff, 0xffffffff, 0xffffffff, 0x0007ffff, 0x00000000, 0xfffe3fc8, 0xffffffff, 0x0000000f, };
static const MCPhysReg CSR_64_AllRegs_VSX_SaveList[] = { PPC::X0, PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, PPC::V0, PPC::V1, PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, PPC::VSL0, PPC::VSL1, PPC::VSL2, PPC::VSL3, PPC::VSL4, PPC::VSL5, PPC::VSL6, PPC::VSL7, PPC::VSL8, PPC::VSL9, PPC::VSL10, PPC::VSL11, PPC::VSL12, PPC::VSL13, PPC::VSL14, PPC::VSL15, PPC::VSL16, PPC::VSL17, PPC::VSL18, PPC::VSL19, PPC::VSL20, PPC::VSL21, PPC::VSL22, PPC::VSL23, PPC::VSL24, PPC::VSL25, PPC::VSL26, PPC::VSL27, PPC::VSL28, PPC::VSL29, PPC::VSL30, PPC::VSL31, 0 };
static const uint32_t CSR_64_AllRegs_VSX_RegMask[] = { 0x0ff00400, 0x00000000, 0x00000000, 0x00000000, 0xfffffe00, 0xfe3fc9ff, 0x000007ff, 0xfff80000, 0xffffffff, 0xffffffff, 0x0007ffff, 0x00000000, 0x00000000, 0xfffe3fc8, 0xffffffff, 0x0000000f, };
static const MCPhysReg CSR_AIX32_SaveList[] = { PPC::R13, PPC::R14, PPC::R15, PPC::R16, PPC::R17, PPC::R18, PPC::R19, PPC::R20, PPC::R21, PPC::R22, PPC::R23, PPC::R24, PPC::R25, PPC::R26, PPC::R27, PPC::R28, PPC::R29, PPC::R30, PPC::R31, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR2, PPC::CR3, PPC::CR4, 0 };
static const uint32_t CSR_AIX32_RegMask[] = { 0x01c00400, 0x00000000, 0x00000000, 0x00000000, 0xff800000, 0xff0001ff, 0x000007ff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xc1c1c1c8, 0x00000001, };
static const MCPhysReg CSR_AIX32_Altivec_SaveList[] = { PPC::R13, PPC::R14, PPC::R15, PPC::R16, PPC::R17, PPC::R18, PPC::R19, PPC::R20, PPC::R21, PPC::R22, PPC::R23, PPC::R24, PPC::R25, PPC::R26, PPC::R27, PPC::R28, PPC::R29, PPC::R30, PPC::R31, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR2, PPC::CR3, PPC::CR4, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, 0 };
static const uint32_t CSR_AIX32_Altivec_RegMask[] = { 0x01c00400, 0x00000000, 0x00000000, 0x00000000, 0xff800000, 0xff0001ff, 0x000007ff, 0x00000000, 0x0007ff80, 0x0007ff80, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xc1c1c1c8, 0x00000001, };
static const MCPhysReg CSR_AIX32_VSRP_SaveList[] = { PPC::R13, PPC::R14, PPC::R15, PPC::R16, PPC::R17, PPC::R18, PPC::R19, PPC::R20, PPC::R21, PPC::R22, PPC::R23, PPC::R24, PPC::R25, PPC::R26, PPC::R27, PPC::R28, PPC::R29, PPC::R30, PPC::R31, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR2, PPC::CR3, PPC::CR4, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, PPC::VSRp26, PPC::VSRp27, PPC::VSRp28, PPC::VSRp29, PPC::VSRp30, PPC::VSRp31, 0 };
static const uint32_t CSR_AIX32_VSRP_RegMask[] = { 0x01c00400, 0x00000000, 0x00000000, 0x00000000, 0xff800000, 0xff0001ff, 0x000007ff, 0x00000000, 0x0007ff80, 0x0007ff80, 0x00000000, 0x0007e000, 0x00000000, 0x00000000, 0xc1c1c1c8, 0x00000001, };
static const MCPhysReg CSR_AIX64_R2_VSRP_SaveList[] = { PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR2, PPC::CR3, PPC::CR4, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, PPC::VSRp26, PPC::VSRp27, PPC::VSRp28, PPC::VSRp29, PPC::VSRp30, PPC::VSRp31, PPC::X2, 0 };
static const uint32_t CSR_AIX64_R2_VSRP_RegMask[] = { 0x01c00400, 0x00000000, 0x00000000, 0x00000000, 0xff800000, 0xfe0021ff, 0x000007ff, 0x00000000, 0x0007ff80, 0x0007ff80, 0x00000000, 0x0007e000, 0x00000000, 0xfffe0020, 0xc1c1c1cf, 0x00000001, };
static const MCPhysReg CSR_AIX64_VSRP_SaveList[] = { PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR2, PPC::CR3, PPC::CR4, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, PPC::VSRp26, PPC::VSRp27, PPC::VSRp28, PPC::VSRp29, PPC::VSRp30, PPC::VSRp31, 0 };
static const uint32_t CSR_AIX64_VSRP_RegMask[] = { 0x01c00400, 0x00000000, 0x00000000, 0x00000000, 0xff800000, 0xfe0001ff, 0x000007ff, 0x00000000, 0x0007ff80, 0x0007ff80, 0x00000000, 0x0007e000, 0x00000000, 0xfffe0000, 0xc1c1c1cf, 0x00000001, };
static const MCPhysReg CSR_ALL_VSRP_SaveList[] = { PPC::VSRp0, PPC::VSRp1, PPC::VSRp2, PPC::VSRp3, PPC::VSRp4, PPC::VSRp5, PPC::VSRp6, PPC::VSRp7, PPC::VSRp8, PPC::VSRp9, PPC::VSRp10, PPC::VSRp11, PPC::VSRp12, PPC::VSRp13, PPC::VSRp14, PPC::VSRp15, PPC::VSRp16, PPC::VSRp17, PPC::VSRp18, PPC::VSRp19, PPC::VSRp20, PPC::VSRp21, PPC::VSRp22, PPC::VSRp23, PPC::VSRp24, PPC::VSRp25, PPC::VSRp26, PPC::VSRp27, PPC::VSRp28, PPC::VSRp29, PPC::VSRp30, PPC::VSRp31, 0 };
static const uint32_t CSR_ALL_VSRP_RegMask[] = { 0x00000400, 0x00000000, 0x00000000, 0x00000000, 0xfffffe00, 0x000001ff, 0x00000000, 0xfff80000, 0xffffffff, 0xffffffff, 0xffffffff, 0x0007ffff, 0x00000000, 0x00000000, 0x00000008, 0x00000000, };
static const MCPhysReg CSR_Altivec_SaveList[] = { PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, 0 };
static const uint32_t CSR_Altivec_RegMask[] = { 0x00000400, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0007ff80, 0x0007ff80, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000008, 0x00000000, };
static const MCPhysReg CSR_NoRegs_SaveList[] = { 0 };
static const uint32_t CSR_NoRegs_RegMask[] = { 0x00000400, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000008, 0x00000000, };
static const MCPhysReg CSR_PPC64_SaveList[] = { PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR2, PPC::CR3, PPC::CR4, 0 };
static const uint32_t CSR_PPC64_RegMask[] = { 0x01c00400, 0x00000000, 0x00000000, 0x00000000, 0xff800000, 0xfe0001ff, 0x000007ff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xfffe0000, 0xc1c1c1cf, 0x00000001, };
static const MCPhysReg CSR_PPC64_Altivec_SaveList[] = { PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR2, PPC::CR3, PPC::CR4, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, 0 };
static const uint32_t CSR_PPC64_Altivec_RegMask[] = { 0x01c00400, 0x00000000, 0x00000000, 0x00000000, 0xff800000, 0xfe0001ff, 0x000007ff, 0x00000000, 0x0007ff80, 0x0007ff80, 0x00000000, 0x00000000, 0x00000000, 0xfffe0000, 0xc1c1c1cf, 0x00000001, };
static const MCPhysReg CSR_PPC64_R2_SaveList[] = { PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR2, PPC::CR3, PPC::CR4, PPC::X2, 0 };
static const uint32_t CSR_PPC64_R2_RegMask[] = { 0x01c00400, 0x00000000, 0x00000000, 0x00000000, 0xff800000, 0xfe0021ff, 0x000007ff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xfffe0020, 0xc1c1c1cf, 0x00000001, };
static const MCPhysReg CSR_PPC64_R2_Altivec_SaveList[] = { PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR2, PPC::CR3, PPC::CR4, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, PPC::X2, 0 };
static const uint32_t CSR_PPC64_R2_Altivec_RegMask[] = { 0x01c00400, 0x00000000, 0x00000000, 0x00000000, 0xff800000, 0xfe0021ff, 0x000007ff, 0x00000000, 0x0007ff80, 0x0007ff80, 0x00000000, 0x00000000, 0x00000000, 0xfffe0020, 0xc1c1c1cf, 0x00000001, };
static const MCPhysReg CSR_SPE_SaveList[] = { PPC::S14, PPC::S15, PPC::S16, PPC::S17, PPC::S18, PPC::S19, PPC::S20, PPC::S21, PPC::S22, PPC::S23, PPC::S24, PPC::S25, PPC::S26, PPC::S27, PPC::S28, PPC::S29, PPC::S30, 0 };
static const uint32_t CSR_SPE_RegMask[] = { 0x00000400, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xfe000000, 0xfe0003ff, 0x000003ff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000008, 0x00000000, };
static const MCPhysReg CSR_SPE_NO_S30_31_SaveList[] = { PPC::S14, PPC::S15, PPC::S16, PPC::S17, PPC::S18, PPC::S19, PPC::S20, PPC::S21, PPC::S22, PPC::S23, PPC::S24, PPC::S25, PPC::S26, PPC::S27, PPC::S28, PPC::S29, 0 };
static const uint32_t CSR_SPE_NO_S30_31_RegMask[] = { 0x00000400, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xfe000000, 0xfe0001ff, 0x000001ff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000008, 0x00000000, };
static const MCPhysReg CSR_SVR32_ColdCC_SaveList[] = { PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R14, PPC::R15, PPC::R16, PPC::R17, PPC::R18, PPC::R19, PPC::R20, PPC::R21, PPC::R22, PPC::R23, PPC::R24, PPC::R25, PPC::R26, PPC::R27, PPC::R28, PPC::R29, PPC::R30, PPC::R31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, PPC::F0, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, 0 };
static const uint32_t CSR_SVR32_ColdCC_RegMask[] = { 0x0ff00400, 0x00000000, 0x00000000, 0x00000000, 0xfffffa00, 0xfe3f81ff, 0x000007ff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xfffffff8, 0x0000000f, };
static const MCPhysReg CSR_SVR32_ColdCC_Altivec_SaveList[] = { PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R14, PPC::R15, PPC::R16, PPC::R17, PPC::R18, PPC::R19, PPC::R20, PPC::R21, PPC::R22, PPC::R23, PPC::R24, PPC::R25, PPC::R26, PPC::R27, PPC::R28, PPC::R29, PPC::R30, PPC::R31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, PPC::F0, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::V0, PPC::V1, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, 0 };
static const uint32_t CSR_SVR32_ColdCC_Altivec_RegMask[] = { 0x0ff00400, 0x00000000, 0x00000000, 0x00000000, 0xfffffa00, 0xfe3f81ff, 0x000007ff, 0xffd80000, 0xffdfffff, 0x0007ffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xfffffff8, 0x0000000f, };
static const MCPhysReg CSR_SVR32_ColdCC_Common_SaveList[] = { PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R14, PPC::R15, PPC::R16, PPC::R17, PPC::R18, PPC::R19, PPC::R20, PPC::R21, PPC::R22, PPC::R23, PPC::R24, PPC::R25, PPC::R26, PPC::R27, PPC::R28, PPC::R29, PPC::R30, PPC::R31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, 0 };
static const uint32_t CSR_SVR32_ColdCC_Common_RegMask[] = { 0x0ff00400, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xfe3f8000, 0x000007ff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xfffffff8, 0x0000000f, };
static const MCPhysReg CSR_SVR32_ColdCC_SPE_SaveList[] = { PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R14, PPC::R15, PPC::R16, PPC::R17, PPC::R18, PPC::R19, PPC::R20, PPC::R21, PPC::R22, PPC::R23, PPC::R24, PPC::R25, PPC::R26, PPC::R27, PPC::R28, PPC::R29, PPC::R30, PPC::R31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, PPC::S4, PPC::S5, PPC::S6, PPC::S7, PPC::S8, PPC::S9, PPC::S10, PPC::S14, PPC::S15, PPC::S16, PPC::S17, PPC::S18, PPC::S19, PPC::S20, PPC::S21, PPC::S22, PPC::S23, PPC::S24, PPC::S25, PPC::S26, PPC::S27, PPC::S28, PPC::S29, PPC::S30, PPC::S31, 0 };
static const uint32_t CSR_SVR32_ColdCC_SPE_RegMask[] = { 0x0ff00400, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xfe3f8000, 0xfe3f87ff, 0x000007ff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xfffffff8, 0x0000000f, };
static const MCPhysReg CSR_SVR32_ColdCC_VSRP_SaveList[] = { PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R14, PPC::R15, PPC::R16, PPC::R17, PPC::R18, PPC::R19, PPC::R20, PPC::R21, PPC::R22, PPC::R23, PPC::R24, PPC::R25, PPC::R26, PPC::R27, PPC::R28, PPC::R29, PPC::R30, PPC::R31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, PPC::F0, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::V0, PPC::V1, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, PPC::VSRp0, PPC::VSRp1, PPC::VSRp2, PPC::VSRp3, PPC::VSRp4, PPC::VSRp5, PPC::VSRp6, PPC::VSRp7, PPC::VSRp8, PPC::VSRp9, PPC::VSRp10, PPC::VSRp11, PPC::VSRp12, PPC::VSRp13, PPC::VSRp14, PPC::VSRp15, PPC::VSRp16, PPC::VSRp18, PPC::VSRp19, PPC::VSRp20, PPC::VSRp21, PPC::VSRp22, PPC::VSRp23, PPC::VSRp24, PPC::VSRp25, PPC::VSRp26, PPC::VSRp27, PPC::VSRp28, PPC::VSRp29, PPC::VSRp30, PPC::VSRp31, 0 };
static const uint32_t CSR_SVR32_ColdCC_VSRP_RegMask[] = { 0x0ff00400, 0x00000000, 0x00000000, 0x00000000, 0xfffffe00, 0xfe3f81ff, 0x000007ff, 0xffd80000, 0xffdfffff, 0xffffffff, 0xffffffff, 0x0007ffef, 0x00000000, 0x00000000, 0xfffffff8, 0x0000000f, };
static const MCPhysReg CSR_SVR432_SaveList[] = { PPC::R14, PPC::R15, PPC::R16, PPC::R17, PPC::R18, PPC::R19, PPC::R20, PPC::R21, PPC::R22, PPC::R23, PPC::R24, PPC::R25, PPC::R26, PPC::R27, PPC::R28, PPC::R29, PPC::R30, PPC::R31, PPC::CR2, PPC::CR3, PPC::CR4, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, 0 };
static const uint32_t CSR_SVR432_RegMask[] = { 0x01c00400, 0x00000000, 0x00000000, 0x00000000, 0xff800000, 0xfe0001ff, 0x000007ff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xc1c1c1c8, 0x00000001, };
static const MCPhysReg CSR_SVR432_Altivec_SaveList[] = { PPC::R14, PPC::R15, PPC::R16, PPC::R17, PPC::R18, PPC::R19, PPC::R20, PPC::R21, PPC::R22, PPC::R23, PPC::R24, PPC::R25, PPC::R26, PPC::R27, PPC::R28, PPC::R29, PPC::R30, PPC::R31, PPC::CR2, PPC::CR3, PPC::CR4, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, 0 };
static const uint32_t CSR_SVR432_Altivec_RegMask[] = { 0x01c00400, 0x00000000, 0x00000000, 0x00000000, 0xff800000, 0xfe0001ff, 0x000007ff, 0x00000000, 0x0007ff80, 0x0007ff80, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xc1c1c1c8, 0x00000001, };
static const MCPhysReg CSR_SVR432_COMM_SaveList[] = { PPC::R14, PPC::R15, PPC::R16, PPC::R17, PPC::R18, PPC::R19, PPC::R20, PPC::R21, PPC::R22, PPC::R23, PPC::R24, PPC::R25, PPC::R26, PPC::R27, PPC::R28, PPC::R29, PPC::R30, PPC::R31, PPC::CR2, PPC::CR3, PPC::CR4, 0 };
static const uint32_t CSR_SVR432_COMM_RegMask[] = { 0x01c00400, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xfe000000, 0x000007ff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xc1c1c1c8, 0x00000001, };
static const MCPhysReg CSR_SVR432_SPE_SaveList[] = { PPC::R14, PPC::R15, PPC::R16, PPC::R17, PPC::R18, PPC::R19, PPC::R20, PPC::R21, PPC::R22, PPC::R23, PPC::R24, PPC::R25, PPC::R26, PPC::R27, PPC::R28, PPC::R29, PPC::R30, PPC::R31, PPC::CR2, PPC::CR3, PPC::CR4, PPC::S14, PPC::S15, PPC::S16, PPC::S17, PPC::S18, PPC::S19, PPC::S20, PPC::S21, PPC::S22, PPC::S23, PPC::S24, PPC::S25, PPC::S26, PPC::S27, PPC::S28, PPC::S29, PPC::S30, 0 };
static const uint32_t CSR_SVR432_SPE_RegMask[] = { 0x01c00400, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xfe000000, 0xfe0007ff, 0x000003ff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xc1c1c1c8, 0x00000001, };
static const MCPhysReg CSR_SVR432_SPE_NO_S30_31_SaveList[] = { PPC::R14, PPC::R15, PPC::R16, PPC::R17, PPC::R18, PPC::R19, PPC::R20, PPC::R21, PPC::R22, PPC::R23, PPC::R24, PPC::R25, PPC::R26, PPC::R27, PPC::R28, PPC::R29, PPC::R30, PPC::R31, PPC::CR2, PPC::CR3, PPC::CR4, PPC::S14, PPC::S15, PPC::S16, PPC::S17, PPC::S18, PPC::S19, PPC::S20, PPC::S21, PPC::S22, PPC::S23, PPC::S24, PPC::S25, PPC::S26, PPC::S27, PPC::S28, PPC::S29, 0 };
static const uint32_t CSR_SVR432_SPE_NO_S30_31_RegMask[] = { 0x01c00400, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xfe000000, 0xfe0007ff, 0x000001ff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xc1c1c1c8, 0x00000001, };
static const MCPhysReg CSR_SVR432_VSRP_SaveList[] = { PPC::R14, PPC::R15, PPC::R16, PPC::R17, PPC::R18, PPC::R19, PPC::R20, PPC::R21, PPC::R22, PPC::R23, PPC::R24, PPC::R25, PPC::R26, PPC::R27, PPC::R28, PPC::R29, PPC::R30, PPC::R31, PPC::CR2, PPC::CR3, PPC::CR4, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, PPC::VSRp26, PPC::VSRp27, PPC::VSRp28, PPC::VSRp29, PPC::VSRp30, PPC::VSRp31, 0 };
static const uint32_t CSR_SVR432_VSRP_RegMask[] = { 0x01c00400, 0x00000000, 0x00000000, 0x00000000, 0xff800000, 0xfe0001ff, 0x000007ff, 0x00000000, 0x0007ff80, 0x0007ff80, 0x00000000, 0x0007e000, 0x00000000, 0x00000000, 0xc1c1c1c8, 0x00000001, };
static const MCPhysReg CSR_SVR464_R2_VSRP_SaveList[] = { PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR2, PPC::CR3, PPC::CR4, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, PPC::VSRp26, PPC::VSRp27, PPC::VSRp28, PPC::VSRp29, PPC::VSRp30, PPC::VSRp31, PPC::X2, 0 };
static const uint32_t CSR_SVR464_R2_VSRP_RegMask[] = { 0x01c00400, 0x00000000, 0x00000000, 0x00000000, 0xff800000, 0xfe0021ff, 0x000007ff, 0x00000000, 0x0007ff80, 0x0007ff80, 0x00000000, 0x0007e000, 0x00000000, 0xfffe0020, 0xc1c1c1cf, 0x00000001, };
static const MCPhysReg CSR_SVR464_VSRP_SaveList[] = { PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR2, PPC::CR3, PPC::CR4, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, PPC::VSRp26, PPC::VSRp27, PPC::VSRp28, PPC::VSRp29, PPC::VSRp30, PPC::VSRp31, 0 };
static const uint32_t CSR_SVR464_VSRP_RegMask[] = { 0x01c00400, 0x00000000, 0x00000000, 0x00000000, 0xff800000, 0xfe0001ff, 0x000007ff, 0x00000000, 0x0007ff80, 0x0007ff80, 0x00000000, 0x0007e000, 0x00000000, 0xfffe0000, 0xc1c1c1cf, 0x00000001, };
static const MCPhysReg CSR_SVR64_ColdCC_SaveList[] = { PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F0, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, 0 };
static const uint32_t CSR_SVR64_ColdCC_RegMask[] = { 0x0ff00400, 0x00000000, 0x00000000, 0x00000000, 0xfffffa00, 0xfe3f81ff, 0x000007ff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xfffe3f80, 0xffffffff, 0x0000000f, };
static const MCPhysReg CSR_SVR64_ColdCC_Altivec_SaveList[] = { PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F0, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, PPC::V0, PPC::V1, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, 0 };
static const uint32_t CSR_SVR64_ColdCC_Altivec_RegMask[] = { 0x0ff00400, 0x00000000, 0x00000000, 0x00000000, 0xfffffa00, 0xfe3f81ff, 0x000007ff, 0xffd80000, 0xffdfffff, 0x0007ffff, 0x00000000, 0x00000000, 0x00000000, 0xfffe3f80, 0xffffffff, 0x0000000f, };
static const MCPhysReg CSR_SVR64_ColdCC_R2_SaveList[] = { PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F0, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, PPC::X2, 0 };
static const uint32_t CSR_SVR64_ColdCC_R2_RegMask[] = { 0x0ff00400, 0x00000000, 0x00000000, 0x00000000, 0xfffffa00, 0xfe3fa1ff, 0x000007ff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xfffe3fa0, 0xffffffff, 0x0000000f, };
static const MCPhysReg CSR_SVR64_ColdCC_R2_Altivec_SaveList[] = { PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F0, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, PPC::V0, PPC::V1, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, PPC::X2, 0 };
static const uint32_t CSR_SVR64_ColdCC_R2_Altivec_RegMask[] = { 0x0ff00400, 0x00000000, 0x00000000, 0x00000000, 0xfffffa00, 0xfe3fa1ff, 0x000007ff, 0xffd80000, 0xffdfffff, 0x0007ffff, 0x00000000, 0x00000000, 0x00000000, 0xfffe3fa0, 0xffffffff, 0x0000000f, };
static const MCPhysReg CSR_SVR64_ColdCC_R2_VSRP_SaveList[] = { PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F0, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, PPC::VSRp0, PPC::VSRp1, PPC::VSRp2, PPC::VSRp3, PPC::VSRp4, PPC::VSRp5, PPC::VSRp6, PPC::VSRp7, PPC::VSRp8, PPC::VSRp9, PPC::VSRp10, PPC::VSRp11, PPC::VSRp12, PPC::VSRp13, PPC::VSRp14, PPC::VSRp15, PPC::VSRp16, PPC::VSRp18, PPC::VSRp19, PPC::VSRp20, PPC::VSRp21, PPC::VSRp22, PPC::VSRp23, PPC::VSRp24, PPC::VSRp25, PPC::VSRp26, PPC::VSRp27, PPC::VSRp28, PPC::VSRp29, PPC::VSRp30, PPC::VSRp31, PPC::X2, 0 };
static const uint32_t CSR_SVR64_ColdCC_R2_VSRP_RegMask[] = { 0x0ff00400, 0x00000000, 0x00000000, 0x00000000, 0xfffffe00, 0xfe3fa1ff, 0x000007ff, 0xff980000, 0xff9fffff, 0xffffffff, 0xffffffff, 0x0007ffef, 0x00000000, 0xfffe3fa0, 0xffffffff, 0x0000000f, };
static const MCPhysReg CSR_SVR64_ColdCC_VSRP_SaveList[] = { PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F0, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, PPC::VSRp0, PPC::VSRp1, PPC::VSRp2, PPC::VSRp3, PPC::VSRp4, PPC::VSRp5, PPC::VSRp6, PPC::VSRp7, PPC::VSRp8, PPC::VSRp9, PPC::VSRp10, PPC::VSRp11, PPC::VSRp12, PPC::VSRp13, PPC::VSRp14, PPC::VSRp15, PPC::VSRp16, PPC::VSRp18, PPC::VSRp19, PPC::VSRp20, PPC::VSRp21, PPC::VSRp22, PPC::VSRp23, PPC::VSRp24, PPC::VSRp25, PPC::VSRp26, PPC::VSRp27, PPC::VSRp28, PPC::VSRp29, PPC::VSRp30, PPC::VSRp31, 0 };
static const uint32_t CSR_SVR64_ColdCC_VSRP_RegMask[] = { 0x0ff00400, 0x00000000, 0x00000000, 0x00000000, 0xfffffe00, 0xfe3f81ff, 0x000007ff, 0xff980000, 0xff9fffff, 0xffffffff, 0xffffffff, 0x0007ffef, 0x00000000, 0xfffe3f80, 0xffffffff, 0x0000000f, };
static const MCPhysReg CSR_VSRP_SaveList[] = { PPC::VSRp26, PPC::VSRp27, PPC::VSRp28, PPC::VSRp29, PPC::VSRp30, PPC::VSRp31, 0 };
static const uint32_t CSR_VSRP_RegMask[] = { 0x00000400, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0007ff80, 0x0007ff80, 0x00000000, 0x0007e000, 0x00000000, 0x00000000, 0x00000008, 0x00000000, };
ArrayRef<const uint32_t *> PPCGenRegisterInfo::getRegMasks() const {
static const uint32_t *const Masks[] = {
CSR_64_AllRegs_RegMask,
CSR_64_AllRegs_AIX_Dflt_Altivec_RegMask,
CSR_64_AllRegs_AIX_Dflt_VSX_RegMask,
CSR_64_AllRegs_Altivec_RegMask,
CSR_64_AllRegs_VSRP_RegMask,
CSR_64_AllRegs_VSX_RegMask,
CSR_AIX32_RegMask,
CSR_AIX32_Altivec_RegMask,
CSR_AIX32_VSRP_RegMask,
CSR_AIX64_R2_VSRP_RegMask,
CSR_AIX64_VSRP_RegMask,
CSR_ALL_VSRP_RegMask,
CSR_Altivec_RegMask,
CSR_NoRegs_RegMask,
CSR_PPC64_RegMask,
CSR_PPC64_Altivec_RegMask,
CSR_PPC64_R2_RegMask,
CSR_PPC64_R2_Altivec_RegMask,
CSR_SPE_RegMask,
CSR_SPE_NO_S30_31_RegMask,
CSR_SVR32_ColdCC_RegMask,
CSR_SVR32_ColdCC_Altivec_RegMask,
CSR_SVR32_ColdCC_Common_RegMask,
CSR_SVR32_ColdCC_SPE_RegMask,
CSR_SVR32_ColdCC_VSRP_RegMask,
CSR_SVR432_RegMask,
CSR_SVR432_Altivec_RegMask,
CSR_SVR432_COMM_RegMask,
CSR_SVR432_SPE_RegMask,
CSR_SVR432_SPE_NO_S30_31_RegMask,
CSR_SVR432_VSRP_RegMask,
CSR_SVR464_R2_VSRP_RegMask,
CSR_SVR464_VSRP_RegMask,
CSR_SVR64_ColdCC_RegMask,
CSR_SVR64_ColdCC_Altivec_RegMask,
CSR_SVR64_ColdCC_R2_RegMask,
CSR_SVR64_ColdCC_R2_Altivec_RegMask,
CSR_SVR64_ColdCC_R2_VSRP_RegMask,
CSR_SVR64_ColdCC_VSRP_RegMask,
CSR_VSRP_RegMask,
};
return ArrayRef(Masks);
}
bool PPCGenRegisterInfo::
isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
return
false;
}
bool PPCGenRegisterInfo::
isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
return
false;
}
bool PPCGenRegisterInfo::
isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
return
false;
}
bool PPCGenRegisterInfo::
isConstantPhysReg(MCRegister PhysReg) const {
return
PhysReg == PPC::ZERO ||
PhysReg == PPC::ZERO8 ||
false;
}
ArrayRef<const char *> PPCGenRegisterInfo::getRegMaskNames() const {
static const char *Names[] = {
"CSR_64_AllRegs",
"CSR_64_AllRegs_AIX_Dflt_Altivec",
"CSR_64_AllRegs_AIX_Dflt_VSX",
"CSR_64_AllRegs_Altivec",
"CSR_64_AllRegs_VSRP",
"CSR_64_AllRegs_VSX",
"CSR_AIX32",
"CSR_AIX32_Altivec",
"CSR_AIX32_VSRP",
"CSR_AIX64_R2_VSRP",
"CSR_AIX64_VSRP",
"CSR_ALL_VSRP",
"CSR_Altivec",
"CSR_NoRegs",
"CSR_PPC64",
"CSR_PPC64_Altivec",
"CSR_PPC64_R2",
"CSR_PPC64_R2_Altivec",
"CSR_SPE",
"CSR_SPE_NO_S30_31",
"CSR_SVR32_ColdCC",
"CSR_SVR32_ColdCC_Altivec",
"CSR_SVR32_ColdCC_Common",
"CSR_SVR32_ColdCC_SPE",
"CSR_SVR32_ColdCC_VSRP",
"CSR_SVR432",
"CSR_SVR432_Altivec",
"CSR_SVR432_COMM",
"CSR_SVR432_SPE",
"CSR_SVR432_SPE_NO_S30_31",
"CSR_SVR432_VSRP",
"CSR_SVR464_R2_VSRP",
"CSR_SVR464_VSRP",
"CSR_SVR64_ColdCC",
"CSR_SVR64_ColdCC_Altivec",
"CSR_SVR64_ColdCC_R2",
"CSR_SVR64_ColdCC_R2_Altivec",
"CSR_SVR64_ColdCC_R2_VSRP",
"CSR_SVR64_ColdCC_VSRP",
"CSR_VSRP",
};
return ArrayRef(Names);
}
const PPCFrameLowering *
PPCGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
return static_cast<const PPCFrameLowering *>(
MF.getSubtarget().getFrameLowering());
}
} // end namespace llvm
#endif // GET_REGINFO_TARGET_DESC