| /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
| |* *| |
| |* "Fast" Instruction Selector for the PPC target *| |
| |* *| |
| |* Automatically generated file, do not edit! *| |
| |* *| |
| \*===----------------------------------------------------------------------===*/ |
| |
| |
| // FastEmit Immediate Predicate functions. |
| static bool Predicate_imm32SExt16(int64_t Imm) { |
| |
| // imm32SExt16 predicate - True if the i32 immediate fits in a 16-bit |
| // sign extended field. Used by instructions like 'addi'. |
| return (int32_t)Imm == (short)Imm; |
| |
| } |
| static bool Predicate_imm64SExt16(int64_t Imm) { |
| |
| // imm64SExt16 predicate - True if the i64 immediate fits in a 16-bit |
| // sign extended field. Used by instructions like 'addi'. |
| return (int64_t)Imm == (short)Imm; |
| |
| } |
| static bool Predicate_immSExt5NonZero(int64_t Imm) { |
| return Imm && isInt<5>(Imm); |
| } |
| static bool Predicate_i32immNonAllOneNonZero(int64_t Imm) { |
| return Imm && (Imm != -1); |
| } |
| |
| |
| // FastEmit functions for ISD::READCYCLECOUNTER. |
| |
| unsigned fastEmit_ISD_READCYCLECOUNTER_MVT_i64_(MVT RetVT) { |
| if (RetVT.SimpleTy != MVT::i64) |
| return 0; |
| return fastEmitInst_(PPC::MFTB8, &PPC::G8RCRegClass); |
| } |
| |
| unsigned fastEmit_ISD_READCYCLECOUNTER_(MVT VT, MVT RetVT) { |
| switch (VT.SimpleTy) { |
| case MVT::i64: return fastEmit_ISD_READCYCLECOUNTER_MVT_i64_(RetVT); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for PPCISD::MFFS. |
| |
| unsigned fastEmit_PPCISD_MFFS_MVT_f64_(MVT RetVT) { |
| if (RetVT.SimpleTy != MVT::f64) |
| return 0; |
| if ((Subtarget->hasFPU())) { |
| return fastEmitInst_(PPC::MFFS, &PPC::F8RCRegClass); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_PPCISD_MFFS_(MVT VT, MVT RetVT) { |
| switch (VT.SimpleTy) { |
| case MVT::f64: return fastEmit_PPCISD_MFFS_MVT_f64_(RetVT); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for PPCISD::PPC32_GOT. |
| |
| unsigned fastEmit_PPCISD_PPC32_GOT_MVT_i32_(MVT RetVT) { |
| if (RetVT.SimpleTy != MVT::i32) |
| return 0; |
| return fastEmitInst_(PPC::PPC32GOT, &PPC::GPRCRegClass); |
| } |
| |
| unsigned fastEmit_PPCISD_PPC32_GOT_(MVT VT, MVT RetVT) { |
| switch (VT.SimpleTy) { |
| case MVT::i32: return fastEmit_PPCISD_PPC32_GOT_MVT_i32_(RetVT); |
| default: return 0; |
| } |
| } |
| |
| // Top-level FastEmit function. |
| |
| unsigned fastEmit_(MVT VT, MVT RetVT, unsigned Opcode) override { |
| switch (Opcode) { |
| case ISD::READCYCLECOUNTER: return fastEmit_ISD_READCYCLECOUNTER_(VT, RetVT); |
| case PPCISD::MFFS: return fastEmit_PPCISD_MFFS_(VT, RetVT); |
| case PPCISD::PPC32_GOT: return fastEmit_PPCISD_PPC32_GOT_(VT, RetVT); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for ISD::ANY_EXTEND. |
| |
| unsigned fastEmit_ISD_ANY_EXTEND_MVT_i1_MVT_i32_r(unsigned Op0) { |
| if ((Subtarget->isISA3_1())) { |
| return fastEmitInst_r(PPC::SETBC, &PPC::GPRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_ANY_EXTEND_MVT_i1_MVT_i64_r(unsigned Op0) { |
| if ((Subtarget->isISA3_1())) { |
| return fastEmitInst_r(PPC::SETBC8, &PPC::G8RCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_ANY_EXTEND_MVT_i1_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::i32: return fastEmit_ISD_ANY_EXTEND_MVT_i1_MVT_i32_r(Op0); |
| case MVT::i64: return fastEmit_ISD_ANY_EXTEND_MVT_i1_MVT_i64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_ISD_ANY_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::i1: return fastEmit_ISD_ANY_EXTEND_MVT_i1_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for ISD::BITCAST. |
| |
| unsigned fastEmit_ISD_BITCAST_MVT_i64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::f64) |
| return 0; |
| if ((Subtarget->hasDirectMove()) && (Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::MTVSRD, &PPC::VSFRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_BITCAST_MVT_f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::i64) |
| return 0; |
| if ((Subtarget->hasDirectMove()) && (Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::MFVSRD, &PPC::G8RCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_BITCAST_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::i64: return fastEmit_ISD_BITCAST_MVT_i64_r(RetVT, Op0); |
| case MVT::f64: return fastEmit_ISD_BITCAST_MVT_f64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for ISD::BSWAP. |
| |
| unsigned fastEmit_ISD_BSWAP_MVT_i32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::i32) |
| return 0; |
| if ((Subtarget->isISA3_1())) { |
| return fastEmitInst_r(PPC::BRW, &PPC::GPRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_BSWAP_MVT_i64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::i64) |
| return 0; |
| if ((Subtarget->isISA3_1())) { |
| return fastEmitInst_r(PPC::BRD, &PPC::G8RCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_BSWAP_MVT_v4i32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v4i32) |
| return 0; |
| if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XXBRW, &PPC::VSRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_BSWAP_MVT_v2i64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v2i64) |
| return 0; |
| if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XXBRD, &PPC::VSRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_BSWAP_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::i32: return fastEmit_ISD_BSWAP_MVT_i32_r(RetVT, Op0); |
| case MVT::i64: return fastEmit_ISD_BSWAP_MVT_i64_r(RetVT, Op0); |
| case MVT::v4i32: return fastEmit_ISD_BSWAP_MVT_v4i32_r(RetVT, Op0); |
| case MVT::v2i64: return fastEmit_ISD_BSWAP_MVT_v2i64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for ISD::CTLZ. |
| |
| unsigned fastEmit_ISD_CTLZ_MVT_i32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::i32) |
| return 0; |
| return fastEmitInst_r(PPC::CNTLZW, &PPC::GPRCRegClass, Op0); |
| } |
| |
| unsigned fastEmit_ISD_CTLZ_MVT_i64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::i64) |
| return 0; |
| return fastEmitInst_r(PPC::CNTLZD, &PPC::G8RCRegClass, Op0); |
| } |
| |
| unsigned fastEmit_ISD_CTLZ_MVT_v16i8_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v16i8) |
| return 0; |
| if ((Subtarget->hasP8Altivec())) { |
| return fastEmitInst_r(PPC::VCLZB, &PPC::VRRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_CTLZ_MVT_v8i16_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v8i16) |
| return 0; |
| if ((Subtarget->hasP8Altivec())) { |
| return fastEmitInst_r(PPC::VCLZH, &PPC::VRRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_CTLZ_MVT_v4i32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v4i32) |
| return 0; |
| if ((Subtarget->hasP8Altivec())) { |
| return fastEmitInst_r(PPC::VCLZW, &PPC::VRRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_CTLZ_MVT_v2i64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v2i64) |
| return 0; |
| if ((Subtarget->hasP8Altivec())) { |
| return fastEmitInst_r(PPC::VCLZD, &PPC::VRRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_CTLZ_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::i32: return fastEmit_ISD_CTLZ_MVT_i32_r(RetVT, Op0); |
| case MVT::i64: return fastEmit_ISD_CTLZ_MVT_i64_r(RetVT, Op0); |
| case MVT::v16i8: return fastEmit_ISD_CTLZ_MVT_v16i8_r(RetVT, Op0); |
| case MVT::v8i16: return fastEmit_ISD_CTLZ_MVT_v8i16_r(RetVT, Op0); |
| case MVT::v4i32: return fastEmit_ISD_CTLZ_MVT_v4i32_r(RetVT, Op0); |
| case MVT::v2i64: return fastEmit_ISD_CTLZ_MVT_v2i64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for ISD::CTPOP. |
| |
| unsigned fastEmit_ISD_CTPOP_MVT_i32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::i32) |
| return 0; |
| return fastEmitInst_r(PPC::POPCNTW, &PPC::GPRCRegClass, Op0); |
| } |
| |
| unsigned fastEmit_ISD_CTPOP_MVT_i64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::i64) |
| return 0; |
| return fastEmitInst_r(PPC::POPCNTD, &PPC::G8RCRegClass, Op0); |
| } |
| |
| unsigned fastEmit_ISD_CTPOP_MVT_v16i8_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v16i8) |
| return 0; |
| if ((Subtarget->hasP8Altivec())) { |
| return fastEmitInst_r(PPC::VPOPCNTB, &PPC::VRRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_CTPOP_MVT_v8i16_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v8i16) |
| return 0; |
| if ((Subtarget->hasP8Altivec())) { |
| return fastEmitInst_r(PPC::VPOPCNTH, &PPC::VRRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_CTPOP_MVT_v4i32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v4i32) |
| return 0; |
| if ((Subtarget->hasP8Altivec())) { |
| return fastEmitInst_r(PPC::VPOPCNTW, &PPC::VRRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_CTPOP_MVT_v2i64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v2i64) |
| return 0; |
| if ((Subtarget->hasP8Altivec())) { |
| return fastEmitInst_r(PPC::VPOPCNTD, &PPC::VRRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_CTPOP_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::i32: return fastEmit_ISD_CTPOP_MVT_i32_r(RetVT, Op0); |
| case MVT::i64: return fastEmit_ISD_CTPOP_MVT_i64_r(RetVT, Op0); |
| case MVT::v16i8: return fastEmit_ISD_CTPOP_MVT_v16i8_r(RetVT, Op0); |
| case MVT::v8i16: return fastEmit_ISD_CTPOP_MVT_v8i16_r(RetVT, Op0); |
| case MVT::v4i32: return fastEmit_ISD_CTPOP_MVT_v4i32_r(RetVT, Op0); |
| case MVT::v2i64: return fastEmit_ISD_CTPOP_MVT_v2i64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for ISD::CTTZ. |
| |
| unsigned fastEmit_ISD_CTTZ_MVT_i32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::i32) |
| return 0; |
| if ((Subtarget->isISA3_0())) { |
| return fastEmitInst_r(PPC::CNTTZW, &PPC::GPRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_CTTZ_MVT_i64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::i64) |
| return 0; |
| if ((Subtarget->isISA3_0())) { |
| return fastEmitInst_r(PPC::CNTTZD, &PPC::G8RCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_CTTZ_MVT_v16i8_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v16i8) |
| return 0; |
| if ((Subtarget->hasP9Altivec())) { |
| return fastEmitInst_r(PPC::VCTZB, &PPC::VRRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_CTTZ_MVT_v8i16_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v8i16) |
| return 0; |
| if ((Subtarget->hasP9Altivec())) { |
| return fastEmitInst_r(PPC::VCTZH, &PPC::VRRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_CTTZ_MVT_v4i32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v4i32) |
| return 0; |
| if ((Subtarget->hasP9Altivec())) { |
| return fastEmitInst_r(PPC::VCTZW, &PPC::VRRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_CTTZ_MVT_v2i64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v2i64) |
| return 0; |
| if ((Subtarget->hasP9Altivec())) { |
| return fastEmitInst_r(PPC::VCTZD, &PPC::VRRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_CTTZ_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::i32: return fastEmit_ISD_CTTZ_MVT_i32_r(RetVT, Op0); |
| case MVT::i64: return fastEmit_ISD_CTTZ_MVT_i64_r(RetVT, Op0); |
| case MVT::v16i8: return fastEmit_ISD_CTTZ_MVT_v16i8_r(RetVT, Op0); |
| case MVT::v8i16: return fastEmit_ISD_CTTZ_MVT_v8i16_r(RetVT, Op0); |
| case MVT::v4i32: return fastEmit_ISD_CTTZ_MVT_v4i32_r(RetVT, Op0); |
| case MVT::v2i64: return fastEmit_ISD_CTTZ_MVT_v2i64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for ISD::FABS. |
| |
| unsigned fastEmit_ISD_FABS_MVT_f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::f32) |
| return 0; |
| if ((Subtarget->hasSPE())) { |
| return fastEmitInst_r(PPC::EFSABS, &PPC::GPRCRegClass, Op0); |
| } |
| if ((Subtarget->hasFPU())) { |
| return fastEmitInst_r(PPC::FABSS, &PPC::F4RCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FABS_MVT_f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::f64) |
| return 0; |
| if ((Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XSABSDP, &PPC::VSFRCRegClass, Op0); |
| } |
| if ((Subtarget->hasSPE())) { |
| return fastEmitInst_r(PPC::EFDABS, &PPC::SPERCRegClass, Op0); |
| } |
| if ((Subtarget->hasFPU())) { |
| return fastEmitInst_r(PPC::FABSD, &PPC::F8RCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FABS_MVT_f128_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::f128) |
| return 0; |
| if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XSABSQP, &PPC::VRRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FABS_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v4f32) |
| return 0; |
| if ((Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XVABSSP, &PPC::VSRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FABS_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v2f64) |
| return 0; |
| if ((Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XVABSDP, &PPC::VSRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FABS_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::f32: return fastEmit_ISD_FABS_MVT_f32_r(RetVT, Op0); |
| case MVT::f64: return fastEmit_ISD_FABS_MVT_f64_r(RetVT, Op0); |
| case MVT::f128: return fastEmit_ISD_FABS_MVT_f128_r(RetVT, Op0); |
| case MVT::v4f32: return fastEmit_ISD_FABS_MVT_v4f32_r(RetVT, Op0); |
| case MVT::v2f64: return fastEmit_ISD_FABS_MVT_v2f64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for ISD::FCEIL. |
| |
| unsigned fastEmit_ISD_FCEIL_MVT_f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::f32) |
| return 0; |
| if ((Subtarget->hasFPU())) { |
| return fastEmitInst_r(PPC::FRIPS, &PPC::F4RCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FCEIL_MVT_f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::f64) |
| return 0; |
| if ((Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XSRDPIP, &PPC::VSFRCRegClass, Op0); |
| } |
| if ((Subtarget->hasFPU())) { |
| return fastEmitInst_r(PPC::FRIPD, &PPC::F8RCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FCEIL_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v4f32) |
| return 0; |
| if ((Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XVRSPIP, &PPC::VSRCRegClass, Op0); |
| } |
| if ((Subtarget->hasAltivec())) { |
| return fastEmitInst_r(PPC::VRFIP, &PPC::VRRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FCEIL_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v2f64) |
| return 0; |
| if ((Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XVRDPIP, &PPC::VSRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FCEIL_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::f32: return fastEmit_ISD_FCEIL_MVT_f32_r(RetVT, Op0); |
| case MVT::f64: return fastEmit_ISD_FCEIL_MVT_f64_r(RetVT, Op0); |
| case MVT::v4f32: return fastEmit_ISD_FCEIL_MVT_v4f32_r(RetVT, Op0); |
| case MVT::v2f64: return fastEmit_ISD_FCEIL_MVT_v2f64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for ISD::FFLOOR. |
| |
| unsigned fastEmit_ISD_FFLOOR_MVT_f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::f32) |
| return 0; |
| if ((Subtarget->hasFPU())) { |
| return fastEmitInst_r(PPC::FRIMS, &PPC::F4RCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FFLOOR_MVT_f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::f64) |
| return 0; |
| if ((Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XSRDPIM, &PPC::VSFRCRegClass, Op0); |
| } |
| if ((Subtarget->hasFPU())) { |
| return fastEmitInst_r(PPC::FRIMD, &PPC::F8RCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FFLOOR_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v4f32) |
| return 0; |
| if ((Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XVRSPIM, &PPC::VSRCRegClass, Op0); |
| } |
| if ((Subtarget->hasAltivec())) { |
| return fastEmitInst_r(PPC::VRFIM, &PPC::VRRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FFLOOR_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v2f64) |
| return 0; |
| if ((Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XVRDPIM, &PPC::VSRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FFLOOR_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::f32: return fastEmit_ISD_FFLOOR_MVT_f32_r(RetVT, Op0); |
| case MVT::f64: return fastEmit_ISD_FFLOOR_MVT_f64_r(RetVT, Op0); |
| case MVT::v4f32: return fastEmit_ISD_FFLOOR_MVT_v4f32_r(RetVT, Op0); |
| case MVT::v2f64: return fastEmit_ISD_FFLOOR_MVT_v2f64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for ISD::FNEARBYINT. |
| |
| unsigned fastEmit_ISD_FNEARBYINT_MVT_f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::f64) |
| return 0; |
| if ((Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XSRDPIC, &PPC::VSFRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FNEARBYINT_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v4f32) |
| return 0; |
| if ((Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XVRSPIC, &PPC::VSRCRegClass, Op0); |
| } |
| if ((Subtarget->hasAltivec())) { |
| return fastEmitInst_r(PPC::VRFIN, &PPC::VRRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FNEARBYINT_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v2f64) |
| return 0; |
| if ((Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XVRDPIC, &PPC::VSRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FNEARBYINT_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::f64: return fastEmit_ISD_FNEARBYINT_MVT_f64_r(RetVT, Op0); |
| case MVT::v4f32: return fastEmit_ISD_FNEARBYINT_MVT_v4f32_r(RetVT, Op0); |
| case MVT::v2f64: return fastEmit_ISD_FNEARBYINT_MVT_v2f64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for ISD::FNEG. |
| |
| unsigned fastEmit_ISD_FNEG_MVT_f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::f32) |
| return 0; |
| if ((Subtarget->hasSPE())) { |
| return fastEmitInst_r(PPC::EFSNEG, &PPC::GPRCRegClass, Op0); |
| } |
| if ((Subtarget->hasFPU())) { |
| return fastEmitInst_r(PPC::FNEGS, &PPC::F4RCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FNEG_MVT_f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::f64) |
| return 0; |
| if ((Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XSNEGDP, &PPC::VSFRCRegClass, Op0); |
| } |
| if ((Subtarget->hasSPE())) { |
| return fastEmitInst_r(PPC::EFDNEG, &PPC::SPERCRegClass, Op0); |
| } |
| if ((Subtarget->hasFPU())) { |
| return fastEmitInst_r(PPC::FNEGD, &PPC::F8RCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FNEG_MVT_f128_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::f128) |
| return 0; |
| if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XSNEGQP, &PPC::VRRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FNEG_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v4f32) |
| return 0; |
| if ((Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XVNEGSP, &PPC::VSRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FNEG_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v2f64) |
| return 0; |
| if ((Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XVNEGDP, &PPC::VSRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FNEG_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::f32: return fastEmit_ISD_FNEG_MVT_f32_r(RetVT, Op0); |
| case MVT::f64: return fastEmit_ISD_FNEG_MVT_f64_r(RetVT, Op0); |
| case MVT::f128: return fastEmit_ISD_FNEG_MVT_f128_r(RetVT, Op0); |
| case MVT::v4f32: return fastEmit_ISD_FNEG_MVT_v4f32_r(RetVT, Op0); |
| case MVT::v2f64: return fastEmit_ISD_FNEG_MVT_v2f64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for ISD::FP_EXTEND. |
| |
| unsigned fastEmit_ISD_FP_EXTEND_MVT_f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::f64) |
| return 0; |
| if ((Subtarget->hasSPE())) { |
| return fastEmitInst_r(PPC::EFDCFS, &PPC::SPERCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FP_EXTEND_MVT_f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::f128) |
| return 0; |
| if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XSCVDPQP, &PPC::VRRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FP_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::f32: return fastEmit_ISD_FP_EXTEND_MVT_f32_r(RetVT, Op0); |
| case MVT::f64: return fastEmit_ISD_FP_EXTEND_MVT_f64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for ISD::FP_ROUND. |
| |
| unsigned fastEmit_ISD_FP_ROUND_MVT_f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::f32) |
| return 0; |
| if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XSRSP, &PPC::VSSRCRegClass, Op0); |
| } |
| if ((Subtarget->hasSPE())) { |
| return fastEmitInst_r(PPC::EFSCFD, &PPC::GPRCRegClass, Op0); |
| } |
| if ((Subtarget->hasFPU())) { |
| return fastEmitInst_r(PPC::FRSP, &PPC::F4RCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FP_ROUND_MVT_f128_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::f64) |
| return 0; |
| if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XSCVQPDP, &PPC::VFRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FP_ROUND_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::f64: return fastEmit_ISD_FP_ROUND_MVT_f64_r(RetVT, Op0); |
| case MVT::f128: return fastEmit_ISD_FP_ROUND_MVT_f128_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for ISD::FP_TO_SINT. |
| |
| unsigned fastEmit_ISD_FP_TO_SINT_MVT_f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::i32) |
| return 0; |
| if ((Subtarget->hasSPE())) { |
| return fastEmitInst_r(PPC::EFSCTSIZ, &PPC::GPRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FP_TO_SINT_MVT_f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::i32) |
| return 0; |
| if ((Subtarget->hasSPE())) { |
| return fastEmitInst_r(PPC::EFDCTSIZ, &PPC::GPRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FP_TO_SINT_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v4i32) |
| return 0; |
| if ((Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XVCVSPSXWS, &PPC::VSRCRegClass, Op0); |
| } |
| if ((Subtarget->hasAltivec())) { |
| return fastEmitInst_r(PPC::VCTSXS_0, &PPC::VRRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FP_TO_SINT_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v2i64) |
| return 0; |
| if ((Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XVCVDPSXDS, &PPC::VSRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FP_TO_SINT_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::f32: return fastEmit_ISD_FP_TO_SINT_MVT_f32_r(RetVT, Op0); |
| case MVT::f64: return fastEmit_ISD_FP_TO_SINT_MVT_f64_r(RetVT, Op0); |
| case MVT::v4f32: return fastEmit_ISD_FP_TO_SINT_MVT_v4f32_r(RetVT, Op0); |
| case MVT::v2f64: return fastEmit_ISD_FP_TO_SINT_MVT_v2f64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for ISD::FP_TO_UINT. |
| |
| unsigned fastEmit_ISD_FP_TO_UINT_MVT_f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::i32) |
| return 0; |
| if ((Subtarget->hasSPE())) { |
| return fastEmitInst_r(PPC::EFSCTUIZ, &PPC::GPRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FP_TO_UINT_MVT_f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::i32) |
| return 0; |
| if ((Subtarget->hasSPE())) { |
| return fastEmitInst_r(PPC::EFDCTUIZ, &PPC::GPRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FP_TO_UINT_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v4i32) |
| return 0; |
| if ((Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XVCVSPUXWS, &PPC::VSRCRegClass, Op0); |
| } |
| if ((Subtarget->hasAltivec())) { |
| return fastEmitInst_r(PPC::VCTUXS_0, &PPC::VRRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FP_TO_UINT_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v2i64) |
| return 0; |
| if ((Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XVCVDPUXDS, &PPC::VSRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FP_TO_UINT_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::f32: return fastEmit_ISD_FP_TO_UINT_MVT_f32_r(RetVT, Op0); |
| case MVT::f64: return fastEmit_ISD_FP_TO_UINT_MVT_f64_r(RetVT, Op0); |
| case MVT::v4f32: return fastEmit_ISD_FP_TO_UINT_MVT_v4f32_r(RetVT, Op0); |
| case MVT::v2f64: return fastEmit_ISD_FP_TO_UINT_MVT_v2f64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for ISD::FRINT. |
| |
| unsigned fastEmit_ISD_FRINT_MVT_f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::f64) |
| return 0; |
| if ((Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XSRDPIC, &PPC::VSFRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FRINT_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v4f32) |
| return 0; |
| if ((Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XVRSPIC, &PPC::VSRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FRINT_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v2f64) |
| return 0; |
| if ((Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XVRDPIC, &PPC::VSRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FRINT_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::f64: return fastEmit_ISD_FRINT_MVT_f64_r(RetVT, Op0); |
| case MVT::v4f32: return fastEmit_ISD_FRINT_MVT_v4f32_r(RetVT, Op0); |
| case MVT::v2f64: return fastEmit_ISD_FRINT_MVT_v2f64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for ISD::FROUND. |
| |
| unsigned fastEmit_ISD_FROUND_MVT_f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::f32) |
| return 0; |
| if ((Subtarget->hasFPU())) { |
| return fastEmitInst_r(PPC::FRINS, &PPC::F4RCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FROUND_MVT_f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::f64) |
| return 0; |
| if ((Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XSRDPI, &PPC::VSFRCRegClass, Op0); |
| } |
| if ((Subtarget->hasFPU())) { |
| return fastEmitInst_r(PPC::FRIND, &PPC::F8RCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FROUND_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v4f32) |
| return 0; |
| if ((Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XVRSPI, &PPC::VSRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FROUND_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v2f64) |
| return 0; |
| if ((Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XVRDPI, &PPC::VSRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FROUND_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::f32: return fastEmit_ISD_FROUND_MVT_f32_r(RetVT, Op0); |
| case MVT::f64: return fastEmit_ISD_FROUND_MVT_f64_r(RetVT, Op0); |
| case MVT::v4f32: return fastEmit_ISD_FROUND_MVT_v4f32_r(RetVT, Op0); |
| case MVT::v2f64: return fastEmit_ISD_FROUND_MVT_v2f64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for ISD::FSQRT. |
| |
| unsigned fastEmit_ISD_FSQRT_MVT_f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::f32) |
| return 0; |
| if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XSSQRTSP, &PPC::VSSRCRegClass, Op0); |
| } |
| if ((Subtarget->hasFPU())) { |
| return fastEmitInst_r(PPC::FSQRTS, &PPC::F4RCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FSQRT_MVT_f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::f64) |
| return 0; |
| if ((Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XSSQRTDP, &PPC::VSFRCRegClass, Op0); |
| } |
| if ((Subtarget->hasFPU())) { |
| return fastEmitInst_r(PPC::FSQRT, &PPC::F8RCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FSQRT_MVT_f128_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::f128) |
| return 0; |
| if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XSSQRTQP, &PPC::VRRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FSQRT_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v4f32) |
| return 0; |
| if ((Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XVSQRTSP, &PPC::VSRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FSQRT_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v2f64) |
| return 0; |
| if ((Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XVSQRTDP, &PPC::VSRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FSQRT_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::f32: return fastEmit_ISD_FSQRT_MVT_f32_r(RetVT, Op0); |
| case MVT::f64: return fastEmit_ISD_FSQRT_MVT_f64_r(RetVT, Op0); |
| case MVT::f128: return fastEmit_ISD_FSQRT_MVT_f128_r(RetVT, Op0); |
| case MVT::v4f32: return fastEmit_ISD_FSQRT_MVT_v4f32_r(RetVT, Op0); |
| case MVT::v2f64: return fastEmit_ISD_FSQRT_MVT_v2f64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for ISD::FTRUNC. |
| |
| unsigned fastEmit_ISD_FTRUNC_MVT_f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::f32) |
| return 0; |
| if ((Subtarget->hasFPU())) { |
| return fastEmitInst_r(PPC::FRIZS, &PPC::F4RCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FTRUNC_MVT_f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::f64) |
| return 0; |
| if ((Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XSRDPIZ, &PPC::VSFRCRegClass, Op0); |
| } |
| if ((Subtarget->hasFPU())) { |
| return fastEmitInst_r(PPC::FRIZD, &PPC::F8RCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FTRUNC_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v4f32) |
| return 0; |
| if ((Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XVRSPIZ, &PPC::VSRCRegClass, Op0); |
| } |
| if ((Subtarget->hasAltivec())) { |
| return fastEmitInst_r(PPC::VRFIZ, &PPC::VRRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FTRUNC_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v2f64) |
| return 0; |
| if ((Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XVRDPIZ, &PPC::VSRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_FTRUNC_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::f32: return fastEmit_ISD_FTRUNC_MVT_f32_r(RetVT, Op0); |
| case MVT::f64: return fastEmit_ISD_FTRUNC_MVT_f64_r(RetVT, Op0); |
| case MVT::v4f32: return fastEmit_ISD_FTRUNC_MVT_v4f32_r(RetVT, Op0); |
| case MVT::v2f64: return fastEmit_ISD_FTRUNC_MVT_v2f64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for ISD::SCALAR_TO_VECTOR. |
| |
| unsigned fastEmit_ISD_SCALAR_TO_VECTOR_MVT_i32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v4i32) |
| return 0; |
| if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::MTVSRWS, &PPC::VSRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SCALAR_TO_VECTOR_MVT_f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v4f32) |
| return 0; |
| if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX()) && (!Subtarget->isLittleEndian())) { |
| return fastEmitInst_r(PPC::XSCVDPSPN, &PPC::VSRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SCALAR_TO_VECTOR_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::i32: return fastEmit_ISD_SCALAR_TO_VECTOR_MVT_i32_r(RetVT, Op0); |
| case MVT::f32: return fastEmit_ISD_SCALAR_TO_VECTOR_MVT_f32_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for ISD::SIGN_EXTEND. |
| |
| unsigned fastEmit_ISD_SIGN_EXTEND_MVT_i1_MVT_i32_r(unsigned Op0) { |
| if ((Subtarget->isISA3_1())) { |
| return fastEmitInst_r(PPC::SETNBC, &PPC::GPRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SIGN_EXTEND_MVT_i1_MVT_i64_r(unsigned Op0) { |
| if ((Subtarget->isISA3_1())) { |
| return fastEmitInst_r(PPC::SETNBC8, &PPC::G8RCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SIGN_EXTEND_MVT_i1_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::i32: return fastEmit_ISD_SIGN_EXTEND_MVT_i1_MVT_i32_r(Op0); |
| case MVT::i64: return fastEmit_ISD_SIGN_EXTEND_MVT_i1_MVT_i64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_ISD_SIGN_EXTEND_MVT_i32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::i64) |
| return 0; |
| return fastEmitInst_r(PPC::EXTSW_32_64, &PPC::G8RCRegClass, Op0); |
| } |
| |
| unsigned fastEmit_ISD_SIGN_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::i1: return fastEmit_ISD_SIGN_EXTEND_MVT_i1_r(RetVT, Op0); |
| case MVT::i32: return fastEmit_ISD_SIGN_EXTEND_MVT_i32_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for ISD::SINT_TO_FP. |
| |
| unsigned fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f32_r(unsigned Op0) { |
| if ((Subtarget->hasSPE())) { |
| return fastEmitInst_r(PPC::EFSCFSI, &PPC::GPRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f64_r(unsigned Op0) { |
| if ((Subtarget->hasSPE())) { |
| return fastEmitInst_r(PPC::EFDCFSI, &PPC::SPERCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SINT_TO_FP_MVT_i32_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::f32: return fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f32_r(Op0); |
| case MVT::f64: return fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v4f32) |
| return 0; |
| if ((Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XVCVSXWSP, &PPC::VSRCRegClass, Op0); |
| } |
| if ((Subtarget->hasAltivec())) { |
| return fastEmitInst_r(PPC::VCFSX_0, &PPC::VRRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SINT_TO_FP_MVT_v2i64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v2f64) |
| return 0; |
| if ((Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XVCVSXDDP, &PPC::VSRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_SINT_TO_FP_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::i32: return fastEmit_ISD_SINT_TO_FP_MVT_i32_r(RetVT, Op0); |
| case MVT::v4i32: return fastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(RetVT, Op0); |
| case MVT::v2i64: return fastEmit_ISD_SINT_TO_FP_MVT_v2i64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for ISD::STRICT_FCEIL. |
| |
| unsigned fastEmit_ISD_STRICT_FCEIL_MVT_f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::f32) |
| return 0; |
| if ((Subtarget->hasFPU())) { |
| return fastEmitInst_r(PPC::FRIPS, &PPC::F4RCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FCEIL_MVT_f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::f64) |
| return 0; |
| if ((Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XSRDPIP, &PPC::VSFRCRegClass, Op0); |
| } |
| if ((Subtarget->hasFPU())) { |
| return fastEmitInst_r(PPC::FRIPD, &PPC::F8RCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FCEIL_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v4f32) |
| return 0; |
| if ((Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XVRSPIP, &PPC::VSRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FCEIL_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v2f64) |
| return 0; |
| if ((Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XVRDPIP, &PPC::VSRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FCEIL_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::f32: return fastEmit_ISD_STRICT_FCEIL_MVT_f32_r(RetVT, Op0); |
| case MVT::f64: return fastEmit_ISD_STRICT_FCEIL_MVT_f64_r(RetVT, Op0); |
| case MVT::v4f32: return fastEmit_ISD_STRICT_FCEIL_MVT_v4f32_r(RetVT, Op0); |
| case MVT::v2f64: return fastEmit_ISD_STRICT_FCEIL_MVT_v2f64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for ISD::STRICT_FFLOOR. |
| |
| unsigned fastEmit_ISD_STRICT_FFLOOR_MVT_f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::f32) |
| return 0; |
| if ((Subtarget->hasFPU())) { |
| return fastEmitInst_r(PPC::FRIMS, &PPC::F4RCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FFLOOR_MVT_f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::f64) |
| return 0; |
| if ((Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XSRDPIM, &PPC::VSFRCRegClass, Op0); |
| } |
| if ((Subtarget->hasFPU())) { |
| return fastEmitInst_r(PPC::FRIMD, &PPC::F8RCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FFLOOR_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v4f32) |
| return 0; |
| if ((Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XVRSPIM, &PPC::VSRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FFLOOR_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v2f64) |
| return 0; |
| if ((Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XVRDPIM, &PPC::VSRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FFLOOR_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::f32: return fastEmit_ISD_STRICT_FFLOOR_MVT_f32_r(RetVT, Op0); |
| case MVT::f64: return fastEmit_ISD_STRICT_FFLOOR_MVT_f64_r(RetVT, Op0); |
| case MVT::v4f32: return fastEmit_ISD_STRICT_FFLOOR_MVT_v4f32_r(RetVT, Op0); |
| case MVT::v2f64: return fastEmit_ISD_STRICT_FFLOOR_MVT_v2f64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for ISD::STRICT_FP_EXTEND. |
| |
| unsigned fastEmit_ISD_STRICT_FP_EXTEND_MVT_f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::f64) |
| return 0; |
| if ((Subtarget->hasSPE())) { |
| return fastEmitInst_r(PPC::EFDCFS, &PPC::SPERCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FP_EXTEND_MVT_f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::f128) |
| return 0; |
| if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XSCVDPQP, &PPC::VRRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FP_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::f32: return fastEmit_ISD_STRICT_FP_EXTEND_MVT_f32_r(RetVT, Op0); |
| case MVT::f64: return fastEmit_ISD_STRICT_FP_EXTEND_MVT_f64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for ISD::STRICT_FP_ROUND. |
| |
| unsigned fastEmit_ISD_STRICT_FP_ROUND_MVT_f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::f32) |
| return 0; |
| if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XSRSP, &PPC::VSSRCRegClass, Op0); |
| } |
| if ((Subtarget->hasSPE())) { |
| return fastEmitInst_r(PPC::EFSCFD, &PPC::GPRCRegClass, Op0); |
| } |
| if ((Subtarget->hasFPU())) { |
| return fastEmitInst_r(PPC::FRSP, &PPC::F4RCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FP_ROUND_MVT_f128_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::f64) |
| return 0; |
| if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XSCVQPDP, &PPC::VFRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FP_ROUND_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::f64: return fastEmit_ISD_STRICT_FP_ROUND_MVT_f64_r(RetVT, Op0); |
| case MVT::f128: return fastEmit_ISD_STRICT_FP_ROUND_MVT_f128_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for ISD::STRICT_FP_TO_SINT. |
| |
| unsigned fastEmit_ISD_STRICT_FP_TO_SINT_MVT_f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::i32) |
| return 0; |
| if ((Subtarget->hasSPE())) { |
| return fastEmitInst_r(PPC::EFSCTSIZ, &PPC::GPRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FP_TO_SINT_MVT_f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::i32) |
| return 0; |
| if ((Subtarget->hasSPE())) { |
| return fastEmitInst_r(PPC::EFDCTSIZ, &PPC::GPRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FP_TO_SINT_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v4i32) |
| return 0; |
| if ((Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XVCVSPSXWS, &PPC::VSRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FP_TO_SINT_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v2i64) |
| return 0; |
| if ((Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XVCVDPSXDS, &PPC::VSRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FP_TO_SINT_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::f32: return fastEmit_ISD_STRICT_FP_TO_SINT_MVT_f32_r(RetVT, Op0); |
| case MVT::f64: return fastEmit_ISD_STRICT_FP_TO_SINT_MVT_f64_r(RetVT, Op0); |
| case MVT::v4f32: return fastEmit_ISD_STRICT_FP_TO_SINT_MVT_v4f32_r(RetVT, Op0); |
| case MVT::v2f64: return fastEmit_ISD_STRICT_FP_TO_SINT_MVT_v2f64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for ISD::STRICT_FP_TO_UINT. |
| |
| unsigned fastEmit_ISD_STRICT_FP_TO_UINT_MVT_f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::i32) |
| return 0; |
| if ((Subtarget->hasSPE())) { |
| return fastEmitInst_r(PPC::EFSCTUIZ, &PPC::GPRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FP_TO_UINT_MVT_f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::i32) |
| return 0; |
| if ((Subtarget->hasSPE())) { |
| return fastEmitInst_r(PPC::EFDCTUIZ, &PPC::GPRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FP_TO_UINT_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v4i32) |
| return 0; |
| if ((Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XVCVSPUXWS, &PPC::VSRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FP_TO_UINT_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v2i64) |
| return 0; |
| if ((Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XVCVDPUXDS, &PPC::VSRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FP_TO_UINT_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::f32: return fastEmit_ISD_STRICT_FP_TO_UINT_MVT_f32_r(RetVT, Op0); |
| case MVT::f64: return fastEmit_ISD_STRICT_FP_TO_UINT_MVT_f64_r(RetVT, Op0); |
| case MVT::v4f32: return fastEmit_ISD_STRICT_FP_TO_UINT_MVT_v4f32_r(RetVT, Op0); |
| case MVT::v2f64: return fastEmit_ISD_STRICT_FP_TO_UINT_MVT_v2f64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for ISD::STRICT_FRINT. |
| |
| unsigned fastEmit_ISD_STRICT_FRINT_MVT_f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::f64) |
| return 0; |
| if ((Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XSRDPIC, &PPC::VSFRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FRINT_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v4f32) |
| return 0; |
| if ((Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XVRSPIC, &PPC::VSRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FRINT_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v2f64) |
| return 0; |
| if ((Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XVRDPIC, &PPC::VSRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FRINT_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::f64: return fastEmit_ISD_STRICT_FRINT_MVT_f64_r(RetVT, Op0); |
| case MVT::v4f32: return fastEmit_ISD_STRICT_FRINT_MVT_v4f32_r(RetVT, Op0); |
| case MVT::v2f64: return fastEmit_ISD_STRICT_FRINT_MVT_v2f64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for ISD::STRICT_FROUND. |
| |
| unsigned fastEmit_ISD_STRICT_FROUND_MVT_f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::f32) |
| return 0; |
| if ((Subtarget->hasFPU())) { |
| return fastEmitInst_r(PPC::FRINS, &PPC::F4RCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FROUND_MVT_f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::f64) |
| return 0; |
| if ((Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XSRDPI, &PPC::VSFRCRegClass, Op0); |
| } |
| if ((Subtarget->hasFPU())) { |
| return fastEmitInst_r(PPC::FRIND, &PPC::F8RCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FROUND_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v4f32) |
| return 0; |
| if ((Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XVRSPI, &PPC::VSRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FROUND_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v2f64) |
| return 0; |
| if ((Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XVRDPI, &PPC::VSRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FROUND_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::f32: return fastEmit_ISD_STRICT_FROUND_MVT_f32_r(RetVT, Op0); |
| case MVT::f64: return fastEmit_ISD_STRICT_FROUND_MVT_f64_r(RetVT, Op0); |
| case MVT::v4f32: return fastEmit_ISD_STRICT_FROUND_MVT_v4f32_r(RetVT, Op0); |
| case MVT::v2f64: return fastEmit_ISD_STRICT_FROUND_MVT_v2f64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for ISD::STRICT_FSQRT. |
| |
| unsigned fastEmit_ISD_STRICT_FSQRT_MVT_f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::f32) |
| return 0; |
| if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XSSQRTSP, &PPC::VSSRCRegClass, Op0); |
| } |
| if ((Subtarget->hasFPU())) { |
| return fastEmitInst_r(PPC::FSQRTS, &PPC::F4RCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FSQRT_MVT_f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::f64) |
| return 0; |
| if ((Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XSSQRTDP, &PPC::VSFRCRegClass, Op0); |
| } |
| if ((Subtarget->hasFPU())) { |
| return fastEmitInst_r(PPC::FSQRT, &PPC::F8RCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FSQRT_MVT_f128_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::f128) |
| return 0; |
| if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XSSQRTQP, &PPC::VRRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FSQRT_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v4f32) |
| return 0; |
| if ((Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XVSQRTSP, &PPC::VSRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FSQRT_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v2f64) |
| return 0; |
| if ((Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XVSQRTDP, &PPC::VSRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FSQRT_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::f32: return fastEmit_ISD_STRICT_FSQRT_MVT_f32_r(RetVT, Op0); |
| case MVT::f64: return fastEmit_ISD_STRICT_FSQRT_MVT_f64_r(RetVT, Op0); |
| case MVT::f128: return fastEmit_ISD_STRICT_FSQRT_MVT_f128_r(RetVT, Op0); |
| case MVT::v4f32: return fastEmit_ISD_STRICT_FSQRT_MVT_v4f32_r(RetVT, Op0); |
| case MVT::v2f64: return fastEmit_ISD_STRICT_FSQRT_MVT_v2f64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for ISD::STRICT_FTRUNC. |
| |
| unsigned fastEmit_ISD_STRICT_FTRUNC_MVT_f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::f32) |
| return 0; |
| if ((Subtarget->hasFPU())) { |
| return fastEmitInst_r(PPC::FRIZS, &PPC::F4RCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FTRUNC_MVT_f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::f64) |
| return 0; |
| if ((Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XSRDPIZ, &PPC::VSFRCRegClass, Op0); |
| } |
| if ((Subtarget->hasFPU())) { |
| return fastEmitInst_r(PPC::FRIZD, &PPC::F8RCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FTRUNC_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v4f32) |
| return 0; |
| if ((Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XVRSPIZ, &PPC::VSRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FTRUNC_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v2f64) |
| return 0; |
| if ((Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XVRDPIZ, &PPC::VSRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_FTRUNC_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::f32: return fastEmit_ISD_STRICT_FTRUNC_MVT_f32_r(RetVT, Op0); |
| case MVT::f64: return fastEmit_ISD_STRICT_FTRUNC_MVT_f64_r(RetVT, Op0); |
| case MVT::v4f32: return fastEmit_ISD_STRICT_FTRUNC_MVT_v4f32_r(RetVT, Op0); |
| case MVT::v2f64: return fastEmit_ISD_STRICT_FTRUNC_MVT_v2f64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for ISD::STRICT_SINT_TO_FP. |
| |
| unsigned fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i32_MVT_f32_r(unsigned Op0) { |
| if ((Subtarget->hasSPE())) { |
| return fastEmitInst_r(PPC::EFSCFSI, &PPC::GPRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i32_MVT_f64_r(unsigned Op0) { |
| if ((Subtarget->hasSPE())) { |
| return fastEmitInst_r(PPC::EFDCFSI, &PPC::SPERCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i32_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::f32: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i32_MVT_f32_r(Op0); |
| case MVT::f64: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i32_MVT_f64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_ISD_STRICT_SINT_TO_FP_MVT_v4i32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v4f32) |
| return 0; |
| if ((Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XVCVSXWSP, &PPC::VSRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_SINT_TO_FP_MVT_v2i64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v2f64) |
| return 0; |
| if ((Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XVCVSXDDP, &PPC::VSRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_SINT_TO_FP_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::i32: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i32_r(RetVT, Op0); |
| case MVT::v4i32: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_v4i32_r(RetVT, Op0); |
| case MVT::v2i64: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_v2i64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for ISD::STRICT_UINT_TO_FP. |
| |
| unsigned fastEmit_ISD_STRICT_UINT_TO_FP_MVT_i32_MVT_f32_r(unsigned Op0) { |
| if ((Subtarget->hasSPE())) { |
| return fastEmitInst_r(PPC::EFSCFUI, &PPC::GPRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_UINT_TO_FP_MVT_i32_MVT_f64_r(unsigned Op0) { |
| if ((Subtarget->hasSPE())) { |
| return fastEmitInst_r(PPC::EFDCFUI, &PPC::SPERCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_UINT_TO_FP_MVT_i32_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::f32: return fastEmit_ISD_STRICT_UINT_TO_FP_MVT_i32_MVT_f32_r(Op0); |
| case MVT::f64: return fastEmit_ISD_STRICT_UINT_TO_FP_MVT_i32_MVT_f64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_ISD_STRICT_UINT_TO_FP_MVT_v4i32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v4f32) |
| return 0; |
| if ((Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XVCVUXWSP, &PPC::VSRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_UINT_TO_FP_MVT_v2i64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v2f64) |
| return 0; |
| if ((Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XVCVUXDDP, &PPC::VSRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_STRICT_UINT_TO_FP_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::i32: return fastEmit_ISD_STRICT_UINT_TO_FP_MVT_i32_r(RetVT, Op0); |
| case MVT::v4i32: return fastEmit_ISD_STRICT_UINT_TO_FP_MVT_v4i32_r(RetVT, Op0); |
| case MVT::v2i64: return fastEmit_ISD_STRICT_UINT_TO_FP_MVT_v2i64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for ISD::TRUNCATE. |
| |
| unsigned fastEmit_ISD_TRUNCATE_MVT_i32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::i1) |
| return 0; |
| return fastEmitInst_r(PPC::ANDI_rec_1_GT_BIT, &PPC::CRBITRCRegClass, Op0); |
| } |
| |
| unsigned fastEmit_ISD_TRUNCATE_MVT_i64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::i1) |
| return 0; |
| return fastEmitInst_r(PPC::ANDI_rec_1_GT_BIT8, &PPC::CRBITRCRegClass, Op0); |
| } |
| |
| unsigned fastEmit_ISD_TRUNCATE_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::i32: return fastEmit_ISD_TRUNCATE_MVT_i32_r(RetVT, Op0); |
| case MVT::i64: return fastEmit_ISD_TRUNCATE_MVT_i64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for ISD::UINT_TO_FP. |
| |
| unsigned fastEmit_ISD_UINT_TO_FP_MVT_i32_MVT_f32_r(unsigned Op0) { |
| if ((Subtarget->hasSPE())) { |
| return fastEmitInst_r(PPC::EFSCFUI, &PPC::GPRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_UINT_TO_FP_MVT_i32_MVT_f64_r(unsigned Op0) { |
| if ((Subtarget->hasSPE())) { |
| return fastEmitInst_r(PPC::EFDCFUI, &PPC::SPERCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_UINT_TO_FP_MVT_i32_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::f32: return fastEmit_ISD_UINT_TO_FP_MVT_i32_MVT_f32_r(Op0); |
| case MVT::f64: return fastEmit_ISD_UINT_TO_FP_MVT_i32_MVT_f64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_ISD_UINT_TO_FP_MVT_v4i32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v4f32) |
| return 0; |
| if ((Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XVCVUXWSP, &PPC::VSRCRegClass, Op0); |
| } |
| if ((Subtarget->hasAltivec())) { |
| return fastEmitInst_r(PPC::VCFUX_0, &PPC::VRRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_UINT_TO_FP_MVT_v2i64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v2f64) |
| return 0; |
| if ((Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XVCVUXDDP, &PPC::VSRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_UINT_TO_FP_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::i32: return fastEmit_ISD_UINT_TO_FP_MVT_i32_r(RetVT, Op0); |
| case MVT::v4i32: return fastEmit_ISD_UINT_TO_FP_MVT_v4i32_r(RetVT, Op0); |
| case MVT::v2i64: return fastEmit_ISD_UINT_TO_FP_MVT_v2i64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for ISD::ZERO_EXTEND. |
| |
| unsigned fastEmit_ISD_ZERO_EXTEND_MVT_i1_MVT_i32_r(unsigned Op0) { |
| if ((Subtarget->isISA3_1())) { |
| return fastEmitInst_r(PPC::SETBC, &PPC::GPRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_ZERO_EXTEND_MVT_i1_MVT_i64_r(unsigned Op0) { |
| if ((Subtarget->isISA3_1())) { |
| return fastEmitInst_r(PPC::SETBC8, &PPC::G8RCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_ISD_ZERO_EXTEND_MVT_i1_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::i32: return fastEmit_ISD_ZERO_EXTEND_MVT_i1_MVT_i32_r(Op0); |
| case MVT::i64: return fastEmit_ISD_ZERO_EXTEND_MVT_i1_MVT_i64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_ISD_ZERO_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::i1: return fastEmit_ISD_ZERO_EXTEND_MVT_i1_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for PPCISD::FCFID. |
| |
| unsigned fastEmit_PPCISD_FCFID_MVT_f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::f64) |
| return 0; |
| if ((Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XSCVSXDDP, &PPC::VSFRCRegClass, Op0); |
| } |
| return fastEmitInst_r(PPC::FCFID, &PPC::F8RCRegClass, Op0); |
| } |
| |
| unsigned fastEmit_PPCISD_FCFID_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::f64: return fastEmit_PPCISD_FCFID_MVT_f64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for PPCISD::FCFIDS. |
| |
| unsigned fastEmit_PPCISD_FCFIDS_MVT_f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::f32) |
| return 0; |
| if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XSCVSXDSP, &PPC::VSSRCRegClass, Op0); |
| } |
| return fastEmitInst_r(PPC::FCFIDS, &PPC::F4RCRegClass, Op0); |
| } |
| |
| unsigned fastEmit_PPCISD_FCFIDS_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::f64: return fastEmit_PPCISD_FCFIDS_MVT_f64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for PPCISD::FCFIDU. |
| |
| unsigned fastEmit_PPCISD_FCFIDU_MVT_f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::f64) |
| return 0; |
| if ((Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XSCVUXDDP, &PPC::VSFRCRegClass, Op0); |
| } |
| return fastEmitInst_r(PPC::FCFIDU, &PPC::F8RCRegClass, Op0); |
| } |
| |
| unsigned fastEmit_PPCISD_FCFIDU_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::f64: return fastEmit_PPCISD_FCFIDU_MVT_f64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for PPCISD::FCFIDUS. |
| |
| unsigned fastEmit_PPCISD_FCFIDUS_MVT_f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::f32) |
| return 0; |
| if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XSCVUXDSP, &PPC::VSSRCRegClass, Op0); |
| } |
| return fastEmitInst_r(PPC::FCFIDUS, &PPC::F4RCRegClass, Op0); |
| } |
| |
| unsigned fastEmit_PPCISD_FCFIDUS_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::f64: return fastEmit_PPCISD_FCFIDUS_MVT_f64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for PPCISD::FCTIDUZ. |
| |
| unsigned fastEmit_PPCISD_FCTIDUZ_MVT_f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::f32) |
| return 0; |
| if ((Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XSCVDPUXDSs, &PPC::VSSRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_PPCISD_FCTIDUZ_MVT_f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::f64) |
| return 0; |
| if ((Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XSCVDPUXDS, &PPC::VSFRCRegClass, Op0); |
| } |
| return fastEmitInst_r(PPC::FCTIDUZ, &PPC::F8RCRegClass, Op0); |
| } |
| |
| unsigned fastEmit_PPCISD_FCTIDUZ_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::f32: return fastEmit_PPCISD_FCTIDUZ_MVT_f32_r(RetVT, Op0); |
| case MVT::f64: return fastEmit_PPCISD_FCTIDUZ_MVT_f64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for PPCISD::FCTIDZ. |
| |
| unsigned fastEmit_PPCISD_FCTIDZ_MVT_f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::f32) |
| return 0; |
| if ((Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XSCVDPSXDSs, &PPC::VSSRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_PPCISD_FCTIDZ_MVT_f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::f64) |
| return 0; |
| if ((Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XSCVDPSXDS, &PPC::VSFRCRegClass, Op0); |
| } |
| return fastEmitInst_r(PPC::FCTIDZ, &PPC::F8RCRegClass, Op0); |
| } |
| |
| unsigned fastEmit_PPCISD_FCTIDZ_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::f32: return fastEmit_PPCISD_FCTIDZ_MVT_f32_r(RetVT, Op0); |
| case MVT::f64: return fastEmit_PPCISD_FCTIDZ_MVT_f64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for PPCISD::FCTIWUZ. |
| |
| unsigned fastEmit_PPCISD_FCTIWUZ_MVT_f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::f32) |
| return 0; |
| if ((Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XSCVDPUXWSs, &PPC::VSSRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_PPCISD_FCTIWUZ_MVT_f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::f64) |
| return 0; |
| if ((Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XSCVDPUXWS, &PPC::VSFRCRegClass, Op0); |
| } |
| return fastEmitInst_r(PPC::FCTIWUZ, &PPC::F8RCRegClass, Op0); |
| } |
| |
| unsigned fastEmit_PPCISD_FCTIWUZ_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::f32: return fastEmit_PPCISD_FCTIWUZ_MVT_f32_r(RetVT, Op0); |
| case MVT::f64: return fastEmit_PPCISD_FCTIWUZ_MVT_f64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for PPCISD::FCTIWZ. |
| |
| unsigned fastEmit_PPCISD_FCTIWZ_MVT_f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::f32) |
| return 0; |
| if ((Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XSCVDPSXWSs, &PPC::VSSRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_PPCISD_FCTIWZ_MVT_f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::f64) |
| return 0; |
| if ((Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XSCVDPSXWS, &PPC::VSFRCRegClass, Op0); |
| } |
| if ((Subtarget->hasFPU())) { |
| return fastEmitInst_r(PPC::FCTIWZ, &PPC::F8RCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_PPCISD_FCTIWZ_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::f32: return fastEmit_PPCISD_FCTIWZ_MVT_f32_r(RetVT, Op0); |
| case MVT::f64: return fastEmit_PPCISD_FCTIWZ_MVT_f64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for PPCISD::FRE. |
| |
| unsigned fastEmit_PPCISD_FRE_MVT_f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::f32) |
| return 0; |
| if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XSRESP, &PPC::VSSRCRegClass, Op0); |
| } |
| if ((Subtarget->hasFPU())) { |
| return fastEmitInst_r(PPC::FRES, &PPC::F4RCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_PPCISD_FRE_MVT_f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::f64) |
| return 0; |
| if ((Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XSREDP, &PPC::VSFRCRegClass, Op0); |
| } |
| if ((Subtarget->hasFPU())) { |
| return fastEmitInst_r(PPC::FRE, &PPC::F8RCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_PPCISD_FRE_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v4f32) |
| return 0; |
| if ((Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XVRESP, &PPC::VSRCRegClass, Op0); |
| } |
| if ((Subtarget->hasAltivec())) { |
| return fastEmitInst_r(PPC::VREFP, &PPC::VRRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_PPCISD_FRE_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v2f64) |
| return 0; |
| if ((Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XVREDP, &PPC::VSRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_PPCISD_FRE_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::f32: return fastEmit_PPCISD_FRE_MVT_f32_r(RetVT, Op0); |
| case MVT::f64: return fastEmit_PPCISD_FRE_MVT_f64_r(RetVT, Op0); |
| case MVT::v4f32: return fastEmit_PPCISD_FRE_MVT_v4f32_r(RetVT, Op0); |
| case MVT::v2f64: return fastEmit_PPCISD_FRE_MVT_v2f64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for PPCISD::FRSQRTE. |
| |
| unsigned fastEmit_PPCISD_FRSQRTE_MVT_f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::f32) |
| return 0; |
| if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XSRSQRTESP, &PPC::VSSRCRegClass, Op0); |
| } |
| if ((Subtarget->hasFPU())) { |
| return fastEmitInst_r(PPC::FRSQRTES, &PPC::F4RCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_PPCISD_FRSQRTE_MVT_f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::f64) |
| return 0; |
| if ((Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XSRSQRTEDP, &PPC::VSFRCRegClass, Op0); |
| } |
| if ((Subtarget->hasFPU())) { |
| return fastEmitInst_r(PPC::FRSQRTE, &PPC::F8RCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_PPCISD_FRSQRTE_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v4f32) |
| return 0; |
| if ((Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XVRSQRTESP, &PPC::VSRCRegClass, Op0); |
| } |
| if ((Subtarget->hasAltivec())) { |
| return fastEmitInst_r(PPC::VRSQRTEFP, &PPC::VRRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_PPCISD_FRSQRTE_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v2f64) |
| return 0; |
| if ((Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XVRSQRTEDP, &PPC::VSRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_PPCISD_FRSQRTE_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::f32: return fastEmit_PPCISD_FRSQRTE_MVT_f32_r(RetVT, Op0); |
| case MVT::f64: return fastEmit_PPCISD_FRSQRTE_MVT_f64_r(RetVT, Op0); |
| case MVT::v4f32: return fastEmit_PPCISD_FRSQRTE_MVT_v4f32_r(RetVT, Op0); |
| case MVT::v2f64: return fastEmit_PPCISD_FRSQRTE_MVT_v2f64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for PPCISD::FSQRT. |
| |
| unsigned fastEmit_PPCISD_FSQRT_MVT_f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::f64) |
| return 0; |
| if ((Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XSSQRTDP, &PPC::VSFRCRegClass, Op0); |
| } |
| return fastEmitInst_r(PPC::FSQRT, &PPC::F8RCRegClass, Op0); |
| } |
| |
| unsigned fastEmit_PPCISD_FSQRT_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v4f32) |
| return 0; |
| if ((Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XVSQRTSP, &PPC::VSRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_PPCISD_FSQRT_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v2f64) |
| return 0; |
| if ((Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XVSQRTDP, &PPC::VSRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_PPCISD_FSQRT_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::f64: return fastEmit_PPCISD_FSQRT_MVT_f64_r(RetVT, Op0); |
| case MVT::v4f32: return fastEmit_PPCISD_FSQRT_MVT_v4f32_r(RetVT, Op0); |
| case MVT::v2f64: return fastEmit_PPCISD_FSQRT_MVT_v2f64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for PPCISD::FTSQRT. |
| |
| unsigned fastEmit_PPCISD_FTSQRT_MVT_f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::i32) |
| return 0; |
| if ((Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XSTSQRTDP, &PPC::CRRCRegClass, Op0); |
| } |
| if ((Subtarget->hasFPU())) { |
| return fastEmitInst_r(PPC::FTSQRT, &PPC::CRRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_PPCISD_FTSQRT_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::i32) |
| return 0; |
| if ((Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XVTSQRTSP, &PPC::CRRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_PPCISD_FTSQRT_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::i32) |
| return 0; |
| if ((Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XVTSQRTDP, &PPC::CRRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_PPCISD_FTSQRT_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::f64: return fastEmit_PPCISD_FTSQRT_MVT_f64_r(RetVT, Op0); |
| case MVT::v4f32: return fastEmit_PPCISD_FTSQRT_MVT_v4f32_r(RetVT, Op0); |
| case MVT::v2f64: return fastEmit_PPCISD_FTSQRT_MVT_v2f64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for PPCISD::MFVSR. |
| |
| unsigned fastEmit_PPCISD_MFVSR_MVT_f64_MVT_i32_r(unsigned Op0) { |
| if ((Subtarget->hasDirectMove()) && (Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::MFVSRWZ, &PPC::GPRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_PPCISD_MFVSR_MVT_f64_MVT_i64_r(unsigned Op0) { |
| if ((Subtarget->hasDirectMove()) && (Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::MFVSRD, &PPC::G8RCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_PPCISD_MFVSR_MVT_f64_r(MVT RetVT, unsigned Op0) { |
| switch (RetVT.SimpleTy) { |
| case MVT::i32: return fastEmit_PPCISD_MFVSR_MVT_f64_MVT_i32_r(Op0); |
| case MVT::i64: return fastEmit_PPCISD_MFVSR_MVT_f64_MVT_i64_r(Op0); |
| default: return 0; |
| } |
| } |
| |
| unsigned fastEmit_PPCISD_MFVSR_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::f64: return fastEmit_PPCISD_MFVSR_MVT_f64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for PPCISD::MTCTR. |
| |
| unsigned fastEmit_PPCISD_MTCTR_MVT_i32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::isVoid) |
| return 0; |
| return fastEmitInst_r(PPC::MTCTR, &PPC::GPRCRegClass, Op0); |
| } |
| |
| unsigned fastEmit_PPCISD_MTCTR_MVT_i64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::isVoid) |
| return 0; |
| return fastEmitInst_r(PPC::MTCTR8, &PPC::G8RCRegClass, Op0); |
| } |
| |
| unsigned fastEmit_PPCISD_MTCTR_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::i32: return fastEmit_PPCISD_MTCTR_MVT_i32_r(RetVT, Op0); |
| case MVT::i64: return fastEmit_PPCISD_MTCTR_MVT_i64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for PPCISD::MTVSRA. |
| |
| unsigned fastEmit_PPCISD_MTVSRA_MVT_i32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::f64) |
| return 0; |
| if ((Subtarget->hasDirectMove()) && (Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::MTVSRWA, &PPC::VSFRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_PPCISD_MTVSRA_MVT_i64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::f64) |
| return 0; |
| if ((Subtarget->hasDirectMove()) && (Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::MTVSRD, &PPC::VSFRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_PPCISD_MTVSRA_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::i32: return fastEmit_PPCISD_MTVSRA_MVT_i32_r(RetVT, Op0); |
| case MVT::i64: return fastEmit_PPCISD_MTVSRA_MVT_i64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for PPCISD::MTVSRZ. |
| |
| unsigned fastEmit_PPCISD_MTVSRZ_MVT_i32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::f64) |
| return 0; |
| if ((Subtarget->hasDirectMove()) && (Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::MTVSRWZ, &PPC::VSFRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_PPCISD_MTVSRZ_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::i32: return fastEmit_PPCISD_MTVSRZ_MVT_i32_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for PPCISD::SCALAR_TO_VECTOR_PERMUTED. |
| |
| unsigned fastEmit_PPCISD_SCALAR_TO_VECTOR_PERMUTED_MVT_f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v4f32) |
| return 0; |
| if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX()) && (Subtarget->isLittleEndian())) { |
| return fastEmitInst_r(PPC::XSCVDPSPN, &PPC::VSRCRegClass, Op0); |
| } |
| if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX()) && (!Subtarget->isLittleEndian())) { |
| return fastEmitInst_r(PPC::XSCVDPSPN, &PPC::VSRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_PPCISD_SCALAR_TO_VECTOR_PERMUTED_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::f32: return fastEmit_PPCISD_SCALAR_TO_VECTOR_PERMUTED_MVT_f32_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for PPCISD::STRICT_FCFID. |
| |
| unsigned fastEmit_PPCISD_STRICT_FCFID_MVT_f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::f64) |
| return 0; |
| if ((Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XSCVSXDDP, &PPC::VSFRCRegClass, Op0); |
| } |
| return fastEmitInst_r(PPC::FCFID, &PPC::F8RCRegClass, Op0); |
| } |
| |
| unsigned fastEmit_PPCISD_STRICT_FCFID_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::f64: return fastEmit_PPCISD_STRICT_FCFID_MVT_f64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for PPCISD::STRICT_FCFIDS. |
| |
| unsigned fastEmit_PPCISD_STRICT_FCFIDS_MVT_f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::f32) |
| return 0; |
| if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XSCVSXDSP, &PPC::VSSRCRegClass, Op0); |
| } |
| return fastEmitInst_r(PPC::FCFIDS, &PPC::F4RCRegClass, Op0); |
| } |
| |
| unsigned fastEmit_PPCISD_STRICT_FCFIDS_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::f64: return fastEmit_PPCISD_STRICT_FCFIDS_MVT_f64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for PPCISD::STRICT_FCFIDU. |
| |
| unsigned fastEmit_PPCISD_STRICT_FCFIDU_MVT_f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::f64) |
| return 0; |
| if ((Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XSCVUXDDP, &PPC::VSFRCRegClass, Op0); |
| } |
| return fastEmitInst_r(PPC::FCFIDU, &PPC::F8RCRegClass, Op0); |
| } |
| |
| unsigned fastEmit_PPCISD_STRICT_FCFIDU_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::f64: return fastEmit_PPCISD_STRICT_FCFIDU_MVT_f64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for PPCISD::STRICT_FCFIDUS. |
| |
| unsigned fastEmit_PPCISD_STRICT_FCFIDUS_MVT_f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::f32) |
| return 0; |
| if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XSCVUXDSP, &PPC::VSSRCRegClass, Op0); |
| } |
| return fastEmitInst_r(PPC::FCFIDUS, &PPC::F4RCRegClass, Op0); |
| } |
| |
| unsigned fastEmit_PPCISD_STRICT_FCFIDUS_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::f64: return fastEmit_PPCISD_STRICT_FCFIDUS_MVT_f64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for PPCISD::STRICT_FCTIDUZ. |
| |
| unsigned fastEmit_PPCISD_STRICT_FCTIDUZ_MVT_f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::f32) |
| return 0; |
| if ((Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XSCVDPUXDSs, &PPC::VSSRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_PPCISD_STRICT_FCTIDUZ_MVT_f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::f64) |
| return 0; |
| if ((Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XSCVDPUXDS, &PPC::VSFRCRegClass, Op0); |
| } |
| return fastEmitInst_r(PPC::FCTIDUZ, &PPC::F8RCRegClass, Op0); |
| } |
| |
| unsigned fastEmit_PPCISD_STRICT_FCTIDUZ_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::f32: return fastEmit_PPCISD_STRICT_FCTIDUZ_MVT_f32_r(RetVT, Op0); |
| case MVT::f64: return fastEmit_PPCISD_STRICT_FCTIDUZ_MVT_f64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for PPCISD::STRICT_FCTIDZ. |
| |
| unsigned fastEmit_PPCISD_STRICT_FCTIDZ_MVT_f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::f32) |
| return 0; |
| if ((Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XSCVDPSXDSs, &PPC::VSSRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_PPCISD_STRICT_FCTIDZ_MVT_f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::f64) |
| return 0; |
| if ((Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XSCVDPSXDS, &PPC::VSFRCRegClass, Op0); |
| } |
| return fastEmitInst_r(PPC::FCTIDZ, &PPC::F8RCRegClass, Op0); |
| } |
| |
| unsigned fastEmit_PPCISD_STRICT_FCTIDZ_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::f32: return fastEmit_PPCISD_STRICT_FCTIDZ_MVT_f32_r(RetVT, Op0); |
| case MVT::f64: return fastEmit_PPCISD_STRICT_FCTIDZ_MVT_f64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for PPCISD::STRICT_FCTIWUZ. |
| |
| unsigned fastEmit_PPCISD_STRICT_FCTIWUZ_MVT_f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::f32) |
| return 0; |
| if ((Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XSCVDPUXWSs, &PPC::VSSRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_PPCISD_STRICT_FCTIWUZ_MVT_f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::f64) |
| return 0; |
| if ((Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XSCVDPUXWS, &PPC::VSFRCRegClass, Op0); |
| } |
| return fastEmitInst_r(PPC::FCTIWUZ, &PPC::F8RCRegClass, Op0); |
| } |
| |
| unsigned fastEmit_PPCISD_STRICT_FCTIWUZ_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::f32: return fastEmit_PPCISD_STRICT_FCTIWUZ_MVT_f32_r(RetVT, Op0); |
| case MVT::f64: return fastEmit_PPCISD_STRICT_FCTIWUZ_MVT_f64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for PPCISD::STRICT_FCTIWZ. |
| |
| unsigned fastEmit_PPCISD_STRICT_FCTIWZ_MVT_f32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::f32) |
| return 0; |
| if ((Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XSCVDPSXWSs, &PPC::VSSRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_PPCISD_STRICT_FCTIWZ_MVT_f64_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::f64) |
| return 0; |
| if ((Subtarget->hasVSX())) { |
| return fastEmitInst_r(PPC::XSCVDPSXWS, &PPC::VSFRCRegClass, Op0); |
| } |
| if ((Subtarget->hasFPU())) { |
| return fastEmitInst_r(PPC::FCTIWZ, &PPC::F8RCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_PPCISD_STRICT_FCTIWZ_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::f32: return fastEmit_PPCISD_STRICT_FCTIWZ_MVT_f32_r(RetVT, Op0); |
| case MVT::f64: return fastEmit_PPCISD_STRICT_FCTIWZ_MVT_f64_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for PPCISD::XXMFACC. |
| |
| unsigned fastEmit_PPCISD_XXMFACC_MVT_v512i1_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v512i1) |
| return 0; |
| if ((!Subtarget->isISAFuture()) && (Subtarget->hasMMA())) { |
| return fastEmitInst_r(PPC::XXMFACC, &PPC::ACCRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_PPCISD_XXMFACC_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::v512i1: return fastEmit_PPCISD_XXMFACC_MVT_v512i1_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // FastEmit functions for PPCISD::XXSPLTI_SP_TO_DP. |
| |
| unsigned fastEmit_PPCISD_XXSPLTI_SP_TO_DP_MVT_i32_r(MVT RetVT, unsigned Op0) { |
| if (RetVT.SimpleTy != MVT::v2f64) |
| return 0; |
| if ((Subtarget->hasPrefixInstrs())) { |
| return fastEmitInst_r(PPC::XXSPLTIDP, &PPC::VSRCRegClass, Op0); |
| } |
| return 0; |
| } |
| |
| unsigned fastEmit_PPCISD_XXSPLTI_SP_TO_DP_r(MVT VT, MVT RetVT, unsigned Op0) { |
| switch (VT.SimpleTy) { |
| case MVT::i32: return fastEmit_PPCISD_XXSPLTI_SP_TO_DP_MVT_i32_r(RetVT, Op0); |
| default: return 0; |
| } |
| } |
| |
| // Top-level FastEmit function. |
| |
| unsigned fastEmit_r(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0) override { |
| switch (Opcode) { |
| case ISD::ANY_EXTEND: return fastEmit_ISD_ANY_EXTEND_r(VT, RetVT, Op0); |
| case ISD::BITCAST: return fastEmit_ISD_BITCAST_r(VT, RetVT, Op0); |
| case ISD::BSWAP: return fastEmit_ISD_BSWAP_r(VT, RetVT, Op0); |
| case ISD::CTLZ: return fastEmit_ISD_CTLZ_r(VT, RetVT, Op0); |
| case ISD::CTPOP: return fastEmit_ISD_CTPOP_r(VT, RetVT, Op0); |
| case ISD::CTTZ: return fastEmit_ISD_CTTZ_r(VT, RetVT, Op0); |
| case ISD::FABS: return fastEmit_ISD_FABS_r(VT, RetVT, Op0); |
| case ISD::FCEIL: return fastEmit_ISD_FCEIL_r(VT, RetVT, Op0); |
| case ISD::FFLOOR: return fastEmit_ISD_FFLOOR_r(VT, RetVT, Op0); |
|