| /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
| |* *| |
| |* Assembly Writer Source Fragment *| |
| |* *| |
| |* Automatically generated file, do not edit! *| |
| |* *| |
| \*===----------------------------------------------------------------------===*/ |
| |
| /// getMnemonic - This method is automatically generated by tablegen |
| /// from the instruction set description. |
| std::pair<const char *, uint64_t> PPCInstPrinter::getMnemonic(const MCInst *MI) { |
| |
| #ifdef __GNUC__ |
| #pragma GCC diagnostic push |
| #pragma GCC diagnostic ignored "-Woverlength-strings" |
| #endif |
| static const char AsmStrs[] = { |
| /* 0 */ "#EH_SjLj_Setup\t\0" |
| /* 16 */ "bdzla+ \0" |
| /* 24 */ "bdnzla+ \0" |
| /* 33 */ "bdza+ \0" |
| /* 40 */ "bdnza+ \0" |
| /* 48 */ "bdzl+ \0" |
| /* 55 */ "bdnzl+ \0" |
| /* 63 */ "bdz+ \0" |
| /* 69 */ "bdnz+ \0" |
| /* 76 */ "bcl 20, 31, \0" |
| /* 89 */ "bctrl\n\tld 2, \0" |
| /* 103 */ "bctrl\n\tlwz 2, \0" |
| /* 118 */ "bc 12, \0" |
| /* 126 */ "bcl 12, \0" |
| /* 135 */ "bclrl 12, \0" |
| /* 146 */ "bcctrl 12, \0" |
| /* 158 */ "bclr 12, \0" |
| /* 168 */ "bcctr 12, \0" |
| /* 179 */ "mtspr 3, \0" |
| /* 189 */ "bc 4, \0" |
| /* 196 */ "bcl 4, \0" |
| /* 204 */ "bclrl 4, \0" |
| /* 214 */ "bcctrl 4, \0" |
| /* 225 */ "bclr 4, \0" |
| /* 234 */ "bcctr 4, \0" |
| /* 244 */ "mtspr 256, \0" |
| /* 256 */ "bdzla- \0" |
| /* 264 */ "bdnzla- \0" |
| /* 273 */ "bdza- \0" |
| /* 280 */ "bdnza- \0" |
| /* 288 */ "bdzl- \0" |
| /* 295 */ "bdnzl- \0" |
| /* 303 */ "bdz- \0" |
| /* 309 */ "bdnz- \0" |
| /* 316 */ "vcmpneb. \0" |
| /* 326 */ "vcmpgtsb. \0" |
| /* 337 */ "extsb. \0" |
| /* 345 */ "vcmpequb. \0" |
| /* 356 */ "bcdsub. \0" |
| /* 365 */ "fsub. \0" |
| /* 372 */ "fmsub. \0" |
| /* 380 */ "fnmsub. \0" |
| /* 389 */ "vcmpgtub. \0" |
| /* 400 */ "vcmpnezb. \0" |
| /* 411 */ "addc. \0" |
| /* 418 */ "andc. \0" |
| /* 425 */ "tabortdc. \0" |
| /* 436 */ "subfc. \0" |
| /* 444 */ "subic. \0" |
| /* 452 */ "addic. \0" |
| /* 460 */ "rldic. \0" |
| /* 468 */ "bcdtrunc. \0" |
| /* 479 */ "bcdutrunc. \0" |
| /* 491 */ "orc. \0" |
| /* 497 */ "tabortwc. \0" |
| /* 508 */ "srad. \0" |
| /* 515 */ "bcdadd. \0" |
| /* 524 */ "fadd. \0" |
| /* 531 */ "fmadd. \0" |
| /* 539 */ "fnmadd. \0" |
| /* 548 */ "mulhd. \0" |
| /* 556 */ "fcfid. \0" |
| /* 564 */ "fctid. \0" |
| /* 572 */ "mulld. \0" |
| /* 580 */ "sld. \0" |
| /* 586 */ "nand. \0" |
| /* 593 */ "tend. \0" |
| /* 600 */ "srd. \0" |
| /* 606 */ "vcmpgtsd. \0" |
| /* 617 */ "vcmpequd. \0" |
| /* 628 */ "vcmpgtud. \0" |
| /* 639 */ "divd. \0" |
| /* 646 */ "cntlzd. \0" |
| /* 655 */ "cnttzd. \0" |
| /* 664 */ "adde. \0" |
| /* 671 */ "divde. \0" |
| /* 679 */ "slbfee. \0" |
| /* 688 */ "subfe. \0" |
| /* 696 */ "addme. \0" |
| /* 704 */ "subfme. \0" |
| /* 713 */ "fre. \0" |
| /* 719 */ "frsqrte. \0" |
| /* 729 */ "paste. \0" |
| /* 737 */ "divwe. \0" |
| /* 745 */ "addze. \0" |
| /* 753 */ "subfze. \0" |
| /* 762 */ "subf. \0" |
| /* 769 */ "mtfsf. \0" |
| /* 777 */ "fneg. \0" |
| /* 784 */ "vcmpneh. \0" |
| /* 794 */ "vcmpgtsh. \0" |
| /* 805 */ "extsh. \0" |
| /* 813 */ "vcmpequh. \0" |
| /* 824 */ "vcmpgtuh. \0" |
| /* 835 */ "vcmpnezh. \0" |
| /* 846 */ "tabortdci. \0" |
| /* 858 */ "tabortwci. \0" |
| /* 870 */ "sradi. \0" |
| /* 878 */ "clrlsldi. \0" |
| /* 889 */ "extldi. \0" |
| /* 898 */ "andi. \0" |
| /* 905 */ "clrrdi. \0" |
| /* 914 */ "insrdi. \0" |
| /* 923 */ "rotrdi. \0" |
| /* 932 */ "extrdi. \0" |
| /* 941 */ "mtfsfi. \0" |
| /* 950 */ "extswsli. \0" |
| /* 961 */ "rldimi. \0" |
| /* 970 */ "rlwimi. \0" |
| /* 979 */ "srawi. \0" |
| /* 987 */ "clrlslwi. \0" |
| /* 998 */ "inslwi. \0" |
| /* 1007 */ "extlwi. \0" |
| /* 1016 */ "clrrwi. \0" |
| /* 1025 */ "insrwi. \0" |
| /* 1034 */ "rotrwi. \0" |
| /* 1043 */ "extrwi. \0" |
| /* 1052 */ "vstribl. \0" |
| /* 1062 */ "rldcl. \0" |
| /* 1070 */ "rldicl. \0" |
| /* 1079 */ "fsel. \0" |
| /* 1086 */ "vstrihl. \0" |
| /* 1096 */ "fmul. \0" |
| /* 1103 */ "treclaim. \0" |
| /* 1114 */ "frim. \0" |
| /* 1121 */ "rlwinm. \0" |
| /* 1130 */ "rlwnm. \0" |
| /* 1138 */ "bcdcfn. \0" |
| /* 1147 */ "bcdcpsgn. \0" |
| /* 1158 */ "fcpsgn. \0" |
| /* 1167 */ "bcdsetsgn. \0" |
| /* 1179 */ "tbegin. \0" |
| /* 1188 */ "frin. \0" |
| /* 1195 */ "bcdctn. \0" |
| /* 1204 */ "addco. \0" |
| /* 1212 */ "subfco. \0" |
| /* 1221 */ "addo. \0" |
| /* 1228 */ "mulldo. \0" |
| /* 1237 */ "divdo. \0" |
| /* 1245 */ "addeo. \0" |
| /* 1253 */ "divdeo. \0" |
| /* 1262 */ "subfeo. \0" |
| /* 1271 */ "addmeo. \0" |
| /* 1280 */ "subfmeo. \0" |
| /* 1290 */ "divweo. \0" |
| /* 1299 */ "addzeo. \0" |
| /* 1308 */ "subfzeo. \0" |
| /* 1318 */ "subfo. \0" |
| /* 1326 */ "nego. \0" |
| /* 1333 */ "divduo. \0" |
| /* 1342 */ "divdeuo. \0" |
| /* 1352 */ "divweuo. \0" |
| /* 1362 */ "divwuo. \0" |
| /* 1371 */ "mullwo. \0" |
| /* 1380 */ "divwo. \0" |
| /* 1388 */ "xvcmpgedp. \0" |
| /* 1400 */ "xvcmpeqdp. \0" |
| /* 1412 */ "xvcmpgtdp. \0" |
| /* 1424 */ "vcmpbfp. \0" |
| /* 1434 */ "vcmpgefp. \0" |
| /* 1445 */ "vcmpeqfp. \0" |
| /* 1456 */ "vcmpgtfp. \0" |
| /* 1467 */ "frip. \0" |
| /* 1474 */ "xvcmpgesp. \0" |
| /* 1486 */ "xvcmpeqsp. \0" |
| /* 1498 */ "frsp. \0" |
| /* 1505 */ "xvcmpgtsp. \0" |
| /* 1517 */ "icblq. \0" |
| /* 1525 */ "bcdcfsq. \0" |
| /* 1535 */ "bcdctsq. \0" |
| /* 1545 */ "vcmpgtsq. \0" |
| /* 1556 */ "vcmpequq. \0" |
| /* 1567 */ "vcmpgtuq. \0" |
| /* 1578 */ "vstribr. \0" |
| /* 1588 */ "rldcr. \0" |
| /* 1596 */ "rldicr. \0" |
| /* 1605 */ "vstrihr. \0" |
| /* 1615 */ "fmr. \0" |
| /* 1621 */ "nor. \0" |
| /* 1627 */ "xor. \0" |
| /* 1633 */ "bcdsr. \0" |
| /* 1641 */ "tsr. \0" |
| /* 1647 */ "fabs. \0" |
| /* 1654 */ "fnabs. \0" |
| /* 1662 */ "fsubs. \0" |
| /* 1670 */ "fmsubs. \0" |
| /* 1679 */ "fnmsubs. \0" |
| /* 1689 */ "bcds. \0" |
| /* 1696 */ "fadds. \0" |
| /* 1704 */ "fmadds. \0" |
| /* 1713 */ "fnmadds. \0" |
| /* 1723 */ "fcfids. \0" |
| /* 1732 */ "fres. \0" |
| /* 1739 */ "frsqrtes. \0" |
| /* 1750 */ "mffs. \0" |
| /* 1757 */ "andis. \0" |
| /* 1765 */ "fmuls. \0" |
| /* 1773 */ "fsqrts. \0" |
| /* 1782 */ "bcdus. \0" |
| /* 1790 */ "fcfidus. \0" |
| /* 1800 */ "subfus. \0" |
| /* 1809 */ "fdivs. \0" |
| /* 1817 */ "tabort. \0" |
| /* 1826 */ "fsqrt. \0" |
| /* 1834 */ "mulhdu. \0" |
| /* 1843 */ "fcfidu. \0" |
| /* 1852 */ "fctidu. \0" |
| /* 1861 */ "divdu. \0" |
| /* 1869 */ "divdeu. \0" |
| /* 1878 */ "divweu. \0" |
| /* 1887 */ "mulhwu. \0" |
| /* 1896 */ "fctiwu. \0" |
| /* 1905 */ "divwu. \0" |
| /* 1913 */ "fdiv. \0" |
| /* 1920 */ "eqv. \0" |
| /* 1926 */ "sraw. \0" |
| /* 1933 */ "vcmpnew. \0" |
| /* 1943 */ "mulhw. \0" |
| /* 1951 */ "fctiw. \0" |
| /* 1959 */ "mullw. \0" |
| /* 1967 */ "slw. \0" |
| /* 1973 */ "srw. \0" |
| /* 1979 */ "vcmpgtsw. \0" |
| /* 1990 */ "extsw. \0" |
| /* 1998 */ "vcmpequw. \0" |
| /* 2009 */ "vcmpgtuw. \0" |
| /* 2020 */ "divw. \0" |
| /* 2027 */ "vcmpnezw. \0" |
| /* 2038 */ "cntlzw. \0" |
| /* 2047 */ "cnttzw. \0" |
| /* 2056 */ "stbcx. \0" |
| /* 2064 */ "stdcx. \0" |
| /* 2072 */ "sthcx. \0" |
| /* 2080 */ "stqcx. \0" |
| /* 2088 */ "stwcx. \0" |
| /* 2096 */ "tlbsx. \0" |
| /* 2104 */ "fctidz. \0" |
| /* 2113 */ "bcdcfz. \0" |
| /* 2122 */ "friz. \0" |
| /* 2129 */ "bcdctz. \0" |
| /* 2138 */ "fctiduz. \0" |
| /* 2148 */ "fctiwuz. \0" |
| /* 2158 */ "fctiwz. \0" |
| /* 2167 */ "mtfsb0 \0" |
| /* 2175 */ "mtfsb1 \0" |
| /* 2183 */ "dmxxinstfdmr512 \0" |
| /* 2200 */ "dmxxextfdmr512 \0" |
| /* 2216 */ "#ATOMIC_CMP_SWAP_I32 \0" |
| /* 2238 */ "pmxvbf16ger2 \0" |
| /* 2252 */ "pmxvf16ger2 \0" |
| /* 2265 */ "pmxvi16ger2 \0" |
| /* 2278 */ "pmxvi8ger4 \0" |
| /* 2290 */ "#ATOMIC_CMP_SWAP_I16 \0" |
| /* 2312 */ "xvcvspbf16 \0" |
| /* 2324 */ "dmxxinstfdmr256 \0" |
| /* 2341 */ "dmxxextfdmr256 \0" |
| /* 2357 */ "#TC_RETURNa8 \0" |
| /* 2371 */ "#TC_RETURNd8 \0" |
| /* 2385 */ "#TC_RETURNr8 \0" |
| /* 2399 */ "pmxvi4ger8 \0" |
| /* 2411 */ "#BUILD_UACC \0" |
| /* 2424 */ "#ADJCALLSTACKDOWN \0" |
| /* 2443 */ "#ADJCALLSTACKUP \0" |
| /* 2460 */ "#TC_RETURNa \0" |
| /* 2473 */ "evmhegsmfaa \0" |
| /* 2486 */ "evmhogsmfaa \0" |
| /* 2499 */ "evmwsmfaa \0" |
| /* 2510 */ "evmwssfaa \0" |
| /* 2521 */ "evmhegsmiaa \0" |
| /* 2534 */ "evmhogsmiaa \0" |
| /* 2547 */ "evmwsmiaa \0" |
| /* 2558 */ "evmhegumiaa \0" |
| /* 2571 */ "evmhogumiaa \0" |
| /* 2584 */ "evmwumiaa \0" |
| /* 2595 */ "dcba \0" |
| /* 2601 */ "bca \0" |
| /* 2606 */ "evmhesmfa \0" |
| /* 2617 */ "evmwhsmfa \0" |
| /* 2628 */ "evmhosmfa \0" |
| /* 2639 */ "evmwsmfa \0" |
| /* 2649 */ "evmhessfa \0" |
| /* 2660 */ "evmwhssfa \0" |
| /* 2671 */ "evmhossfa \0" |
| /* 2682 */ "evmwssfa \0" |
| /* 2692 */ "plha \0" |
| /* 2698 */ "evmhesmia \0" |
| /* 2709 */ "evmwhsmia \0" |
| /* 2720 */ "evmhosmia \0" |
| /* 2731 */ "evmwsmia \0" |
| /* 2741 */ "evmheumia \0" |
| /* 2752 */ "evmwhumia \0" |
| /* 2763 */ "evmwlumia \0" |
| /* 2774 */ "evmhoumia \0" |
| /* 2785 */ "evmwumia \0" |
| /* 2795 */ "bla \0" |
| /* 2800 */ "bcla \0" |
| /* 2806 */ "bdzla \0" |
| /* 2813 */ "bdnzla \0" |
| /* 2821 */ "evmra \0" |
| /* 2828 */ "plwa \0" |
| /* 2834 */ "mtvsrwa \0" |
| /* 2843 */ "bdza \0" |
| /* 2849 */ "bdnza \0" |
| /* 2856 */ "vsrab \0" |
| /* 2863 */ "rfebb \0" |
| /* 2870 */ "vcntmbb \0" |
| /* 2879 */ "xvtlsbb \0" |
| /* 2888 */ "vclzlsbb \0" |
| /* 2898 */ "vctzlsbb \0" |
| /* 2908 */ "vcmpneb \0" |
| /* 2917 */ "vmrghb \0" |
| /* 2925 */ "xxspltib \0" |
| /* 2935 */ "vmrglb \0" |
| /* 2943 */ "vclrlb \0" |
| /* 2951 */ "vrlb \0" |
| /* 2957 */ "vslb \0" |
| /* 2963 */ "vpmsumb \0" |
| /* 2972 */ "vgnb \0" |
| /* 2978 */ "cmpb \0" |
| /* 2984 */ "cmpeqb \0" |
| /* 2992 */ "cmprb \0" |
| /* 2999 */ "vclrrb \0" |
| /* 3007 */ "vsrb \0" |
| /* 3013 */ "vmulesb \0" |
| /* 3022 */ "vavgsb \0" |
| /* 3030 */ "vupkhsb \0" |
| /* 3039 */ "vspltisb \0" |
| /* 3049 */ "vupklsb \0" |
| /* 3058 */ "vminsb \0" |
| /* 3066 */ "vmulosb \0" |
| /* 3075 */ "vcmpgtsb \0" |
| /* 3085 */ "evextsb \0" |
| /* 3094 */ "vmaxsb \0" |
| /* 3102 */ "setb \0" |
| /* 3108 */ "mftb \0" |
| /* 3114 */ "vspltb \0" |
| /* 3122 */ "vpopcntb \0" |
| /* 3132 */ "vinsertb \0" |
| /* 3142 */ "pstb \0" |
| /* 3148 */ "vabsdub \0" |
| /* 3157 */ "vmuleub \0" |
| /* 3166 */ "vavgub \0" |
| /* 3174 */ "vminub \0" |
| /* 3182 */ "vmuloub \0" |
| /* 3191 */ "vcmpequb \0" |
| /* 3201 */ "efdsub \0" |
| /* 3209 */ "fsub \0" |
| /* 3215 */ "fmsub \0" |
| /* 3222 */ "fnmsub \0" |
| /* 3230 */ "efssub \0" |
| /* 3238 */ "evfssub \0" |
| /* 3247 */ "vextractub \0" |
| /* 3259 */ "vcmpgtub \0" |
| /* 3269 */ "vmaxub \0" |
| /* 3277 */ "xxblendvb \0" |
| /* 3288 */ "vcmpnezb \0" |
| /* 3298 */ "vclzb \0" |
| /* 3305 */ "vctzb \0" |
| /* 3312 */ "setnbc \0" |
| /* 3320 */ "setbc \0" |
| /* 3327 */ "xxmfacc \0" |
| /* 3336 */ "xxmtacc \0" |
| /* 3345 */ "addc \0" |
| /* 3351 */ "xxlandc \0" |
| /* 3360 */ "crandc \0" |
| /* 3368 */ "evandc \0" |
| /* 3376 */ "subfc \0" |
| /* 3383 */ "subic \0" |
| /* 3390 */ "addic \0" |
| /* 3397 */ "rldic \0" |
| /* 3404 */ "subfic \0" |
| /* 3412 */ "xsrdpic \0" |
| /* 3421 */ "xvrdpic \0" |
| /* 3430 */ "xvrspic \0" |
| /* 3439 */ "icblc \0" |
| /* 3446 */ "brinc \0" |
| /* 3453 */ "sync \0" |
| /* 3459 */ "xxlorc \0" |
| /* 3467 */ "crorc \0" |
| /* 3474 */ "evorc \0" |
| /* 3481 */ "sc \0" |
| /* 3485 */ "vextsb2d \0" |
| /* 3495 */ "vextsh2d \0" |
| /* 3505 */ "vextsw2d \0" |
| /* 3515 */ "#TC_RETURNd \0" |
| /* 3528 */ "vshasigmad \0" |
| /* 3540 */ "vsrad \0" |
| /* 3547 */ "vgbbd \0" |
| /* 3554 */ "vcntmbd \0" |
| /* 3563 */ "vprtybd \0" |
| /* 3572 */ "efdadd \0" |
| /* 3580 */ "fadd \0" |
| /* 3586 */ "fmadd \0" |
| /* 3593 */ "fnmadd \0" |
| /* 3601 */ "efsadd \0" |
| /* 3609 */ "evfsadd \0" |
| /* 3618 */ "evldd \0" |
| /* 3625 */ "mtvsrdd \0" |
| /* 3634 */ "evstdd \0" |
| /* 3642 */ "vcfuged \0" |
| /* 3651 */ "efscfd \0" |
| /* 3659 */ "plfd \0" |
| /* 3665 */ "pstfd \0" |
| /* 3672 */ "vnegd \0" |
| /* 3679 */ "maddhd \0" |
| /* 3687 */ "mulhd \0" |
| /* 3694 */ "fcfid \0" |
| /* 3701 */ "efdcfsid \0" |
| /* 3711 */ "fctid \0" |
| /* 3718 */ "efdcfuid \0" |
| /* 3728 */ "tlbld \0" |
| /* 3735 */ "maddld \0" |
| /* 3743 */ "vmulld \0" |
| /* 3751 */ "cmpld \0" |
| /* 3758 */ "mfvsrld \0" |
| /* 3767 */ "vrld \0" |
| /* 3773 */ "vsld \0" |
| /* 3779 */ "vbpermd \0" |
| /* 3788 */ "vpmsumd \0" |
| /* 3797 */ "xxland \0" |
| /* 3805 */ "xxlnand \0" |
| /* 3814 */ "crnand \0" |
| /* 3822 */ "evnand \0" |
| /* 3830 */ "crand \0" |
| /* 3837 */ "evand \0" |
| /* 3844 */ "vpdepd \0" |
| /* 3852 */ "cmpd \0" |
| /* 3858 */ "xxbrd \0" |
| /* 3865 */ "mtmsrd \0" |
| /* 3873 */ "mfvsrd \0" |
| /* 3881 */ "mtvsrd \0" |
| /* 3889 */ "vmodsd \0" |
| /* 3897 */ "vmulesd \0" |
| /* 3906 */ "vdivesd \0" |
| /* 3915 */ "vmulhsd \0" |
| /* 3924 */ "vminsd \0" |
| /* 3932 */ "vinsd \0" |
| /* 3939 */ "vmulosd \0" |
| /* 3948 */ "vcmpgtsd \0" |
| /* 3958 */ "vdivsd \0" |
| /* 3966 */ "vmaxsd \0" |
| /* 3974 */ "plxsd \0" |
| /* 3981 */ "pstxsd \0" |
| /* 3989 */ "vextractd \0" |
| /* 4000 */ "vpopcntd \0" |
| /* 4010 */ "vinsertd \0" |
| /* 4020 */ "pstd \0" |
| /* 4026 */ "vpextd \0" |
| /* 4034 */ "vmsumcud \0" |
| /* 4044 */ "vmodud \0" |
| /* 4052 */ "vmuleud \0" |
| /* 4061 */ "vdiveud \0" |
| /* 4070 */ "vmulhud \0" |
| /* 4079 */ "vminud \0" |
| /* 4087 */ "vmuloud \0" |
| /* 4096 */ "vcmpequd \0" |
| /* 4106 */ "vcmpgtud \0" |
| /* 4116 */ "vdivud \0" |
| /* 4124 */ "vmaxud \0" |
| /* 4132 */ "xxblendvd \0" |
| /* 4143 */ "divd \0" |
| /* 4149 */ "vclzd \0" |
| /* 4156 */ "cntlzd \0" |
| /* 4164 */ "vctzd \0" |
| /* 4171 */ "cnttzd \0" |
| /* 4179 */ "mfbhrbe \0" |
| /* 4188 */ "mffsce \0" |
| /* 4196 */ "adde \0" |
| /* 4202 */ "divde \0" |
| /* 4209 */ "slbmfee \0" |
| /* 4218 */ "wrtee \0" |
| /* 4225 */ "subfe \0" |
| /* 4232 */ "evlwhe \0" |
| /* 4240 */ "evstwhe \0" |
| /* 4249 */ "slbie \0" |
| /* 4256 */ "tlbie \0" |
| /* 4263 */ "addme \0" |
| /* 4270 */ "subfme \0" |
| /* 4278 */ "tlbre \0" |
| /* 4285 */ "fre \0" |
| /* 4290 */ "slbmte \0" |
| /* 4298 */ "frsqrte \0" |
| /* 4307 */ "tlbwe \0" |
| /* 4314 */ "divwe \0" |
| /* 4321 */ "evstwwe \0" |
| /* 4330 */ "addze \0" |
| /* 4337 */ "subfze \0" |
| /* 4345 */ "dcbf \0" |
| /* 4351 */ "subf \0" |
| /* 4357 */ "evmhesmf \0" |
| /* 4367 */ "evmwhsmf \0" |
| /* 4377 */ "evmhosmf \0" |
| /* 4387 */ "evmwsmf \0" |
| /* 4396 */ "mcrf \0" |
| /* 4402 */ "mfocrf \0" |
| /* 4410 */ "mtocrf \0" |
| /* 4418 */ "mtcrf \0" |
| /* 4425 */ "efdcfsf \0" |
| /* 4434 */ "efscfsf \0" |
| /* 4443 */ "evfscfsf \0" |
| /* 4453 */ "mtfsf \0" |
| /* 4460 */ "evmhessf \0" |
| /* 4470 */ "evmwhssf \0" |
| /* 4480 */ "evmhossf \0" |
| /* 4490 */ "evmwssf \0" |
| /* 4499 */ "efdctsf \0" |
| /* 4508 */ "efsctsf \0" |
| /* 4517 */ "evfsctsf \0" |
| /* 4527 */ "efdcfuf \0" |
| /* 4536 */ "efscfuf \0" |
| /* 4545 */ "evfscfuf \0" |
| /* 4555 */ "efdctuf \0" |
| /* 4564 */ "efsctuf \0" |
| /* 4573 */ "slbieg \0" |
| /* 4581 */ "efdneg \0" |
| /* 4589 */ "fneg \0" |
| /* 4595 */ "efsneg \0" |
| /* 4603 */ "evfsneg \0" |
| /* 4612 */ "evneg \0" |
| /* 4619 */ "vsrah \0" |
| /* 4626 */ "vcntmbh \0" |
| /* 4635 */ "evldh \0" |
| /* 4642 */ "evstdh \0" |
| /* 4650 */ "vcmpneh \0" |
| /* 4659 */ "vmrghh \0" |
| /* 4667 */ "vmrglh \0" |
| /* 4675 */ "vrlh \0" |
| /* 4681 */ "vslh \0" |
| /* 4687 */ "vpmsumh \0" |
| /* 4696 */ "xxbrh \0" |
| /* 4703 */ "vsrh \0" |
| /* 4709 */ "vmulesh \0" |
| /* 4718 */ "vavgsh \0" |
| /* 4726 */ "vupkhsh \0" |
| /* 4735 */ "vspltish \0" |
| /* 4745 */ "vupklsh \0" |
| /* 4754 */ "vminsh \0" |
| /* 4762 */ "vmulosh \0" |
| /* 4771 */ "vcmpgtsh \0" |
| /* 4781 */ "evextsh \0" |
| /* 4790 */ "vmaxsh \0" |
| /* 4798 */ "vsplth \0" |
| /* 4806 */ "vpopcnth \0" |
| /* 4816 */ "vinserth \0" |
| /* 4826 */ "psth \0" |
| /* 4832 */ "vabsduh \0" |
| /* 4841 */ "vmuleuh \0" |
| /* 4850 */ "vavguh \0" |
| /* 4858 */ "vminuh \0" |
| /* 4866 */ "vmulouh \0" |
| /* 4875 */ "vcmpequh \0" |
| /* 4885 */ "vextractuh \0" |
| /* 4897 */ "vcmpgtuh \0" |
| /* 4907 */ "vmaxuh \0" |
| /* 4915 */ "xxblendvh \0" |
| /* 4926 */ "vcmpnezh \0" |
| /* 4936 */ "vclzh \0" |
| /* 4943 */ "vctzh \0" |
| /* 4950 */ "dcbi \0" |
| /* 4956 */ "icbi \0" |
| /* 4962 */ "vsldbi \0" |
| /* 4970 */ "vsrdbi \0" |
| /* 4978 */ "subi \0" |
| /* 4984 */ "dccci \0" |
| /* 4991 */ "iccci \0" |
| /* 4998 */ "sradi \0" |
| /* 5005 */ "paddi \0" |
| /* 5012 */ "cmpldi \0" |
| /* 5020 */ "clrlsldi \0" |
| /* 5030 */ "extldi \0" |
| /* 5038 */ "xxpermdi \0" |
| /* 5048 */ "cmpdi \0" |
| /* 5055 */ "clrrdi \0" |
| /* 5063 */ "insrdi \0" |
| /* 5071 */ "rotrdi \0" |
| /* 5079 */ "extrdi \0" |
| /* 5087 */ "tdi \0" |
| /* 5092 */ "wrteei \0" |
| /* 5100 */ "mtfsfi \0" |
| /* 5108 */ "evsplatfi \0" |
| /* 5119 */ "evmergehi \0" |
| /* 5130 */ "evmergelohi \0" |
| /* 5143 */ "tlbli \0" |
| /* 5150 */ "mulli \0" |
| /* 5157 */ "pli \0" |
| /* 5162 */ "extswsli \0" |
| /* 5172 */ "mtvsrbmi \0" |
| /* 5182 */ "vrldmi \0" |
| /* 5190 */ "rldimi \0" |
| /* 5198 */ "rlwimi \0" |
| /* 5206 */ "vrlqmi \0" |
| /* 5214 */ "evmhesmi \0" |
| /* 5224 */ "evmwhsmi \0" |
| /* 5234 */ "evmhosmi \0" |
| /* 5244 */ "evmwsmi \0" |
| /* 5253 */ "evmheumi \0" |
| /* 5263 */ "evmwhumi \0" |
| /* 5273 */ "evmwlumi \0" |
| /* 5283 */ "evmhoumi \0" |
| /* 5293 */ "evmwumi \0" |
| /* 5302 */ "vrlwmi \0" |
| /* 5310 */ "mffscrni \0" |
| /* 5320 */ "mffscdrni \0" |
| /* 5331 */ "vsldoi \0" |
| /* 5339 */ "xsrdpi \0" |
| /* 5347 */ "xvrdpi \0" |
| /* 5355 */ "xsrqpi \0" |
| /* 5363 */ "xvrspi \0" |
| /* 5371 */ "xori \0" |
| /* 5377 */ "efdcfsi \0" |
| /* 5386 */ "efscfsi \0" |
| /* 5395 */ "evfscfsi \0" |
| /* 5405 */ "efdctsi \0" |
| /* 5414 */ "efsctsi \0" |
| /* 5423 */ "evfsctsi \0" |
| /* 5433 */ "evsplati \0" |
| /* 5443 */ "efdcfui \0" |
| /* 5452 */ "efscfui \0" |
| /* 5461 */ "evfscfui \0" |
| /* 5471 */ "efdctui \0" |
| /* 5480 */ "efsctui \0" |
| /* 5489 */ "evfsctui \0" |
| /* 5499 */ "srawi \0" |
| /* 5506 */ "xxsldwi \0" |
| /* 5515 */ "cmplwi \0" |
| /* 5523 */ "evrlwi \0" |
| /* 5531 */ "clrlslwi \0" |
| /* 5541 */ "inslwi \0" |
| /* 5549 */ "evslwi \0" |
| /* 5557 */ "extlwi \0" |
| /* 5565 */ "cmpwi \0" |
| /* 5572 */ "clrrwi \0" |
| /* 5580 */ "insrwi \0" |
| /* 5588 */ "rotrwi \0" |
| /* 5596 */ "extrwi \0" |
| /* 5604 */ "lswi \0" |
| /* 5610 */ "stswi \0" |
| /* 5617 */ "twi \0" |
| /* 5622 */ "tcheck \0" |
| /* 5630 */ "hashchk \0" |
| /* 5639 */ "xxeval \0" |
| /* 5647 */ "vstribl \0" |
| /* 5656 */ "bcl \0" |
| /* 5661 */ "rldcl \0" |
| /* 5668 */ "rldicl \0" |
| /* 5676 */ "tlbiel \0" |
| /* 5684 */ "fsel \0" |
| /* 5690 */ "isel \0" |
| /* 5696 */ "vsel \0" |
| /* 5702 */ "xxsel \0" |
| /* 5709 */ "dcbfl \0" |
| /* 5716 */ "vstrihl \0" |
| /* 5725 */ "lxvprll \0" |
| /* 5734 */ "stxvprll \0" |
| /* 5744 */ "lxvrll \0" |
| /* 5752 */ "stxvrll \0" |
| /* 5761 */ "lxvll \0" |
| /* 5768 */ "stxvll \0" |
| /* 5776 */ "bclrl \0" |
| /* 5783 */ "lxvprl \0" |
| /* 5791 */ "stxvprl \0" |
| /* 5800 */ "bcctrl \0" |
| /* 5808 */ "lxvrl \0" |
| /* 5815 */ "stxvrl \0" |
| /* 5823 */ "mffsl \0" |
| /* 5830 */ "lvsl \0" |
| /* 5836 */ "efdmul \0" |
| /* 5844 */ "fmul \0" |
| /* 5850 */ "efsmul \0" |
| /* 5858 */ "evfsmul \0" |
| /* 5867 */ "lxvl \0" |
| /* 5873 */ "stxvl \0" |
| /* 5880 */ "lvxl \0" |
| /* 5886 */ "stvxl \0" |
| /* 5893 */ "dcbzl \0" |
| /* 5900 */ "bdzl \0" |
| /* 5906 */ "bdnzl \0" |
| /* 5913 */ "vexpandbm \0" |
| /* 5924 */ "vmsummbm \0" |
| /* 5934 */ "mtvsrbm \0" |
| /* 5943 */ "vextractbm \0" |
| /* 5955 */ "vsububm \0" |
| /* 5964 */ "vaddubm \0" |
| /* 5973 */ "vmsumubm \0" |
| /* 5983 */ "xxgenpcvbm \0" |
| /* 5995 */ "vexpanddm \0" |
| /* 6006 */ "mtvsrdm \0" |
| /* 6015 */ "vextractdm \0" |
| /* 6027 */ "vsubudm \0" |
| /* 6036 */ "vaddudm \0" |
| /* 6045 */ "vmsumudm \0" |
| /* 6055 */ "xxgenpcvdm \0" |
| /* 6067 */ "vclzdm \0" |
| /* 6075 */ "cntlzdm \0" |
| /* 6084 */ "vctzdm \0" |
| /* 6092 */ "cnttzdm \0" |
| /* 6101 */ "vexpandhm \0" |
| /* 6112 */ "mtvsrhm \0" |
| /* 6121 */ "vmsumshm \0" |
| /* 6131 */ "vextracthm \0" |
| /* 6143 */ "vsubuhm \0" |
| /* 6152 */ "vmladduhm \0" |
| /* 6163 */ "vadduhm \0" |
| /* 6172 */ "vmsumuhm \0" |
| /* 6182 */ "xxgenpcvhm \0" |
| /* 6194 */ "vrfim \0" |
| /* 6201 */ "xsrdpim \0" |
| /* 6210 */ "xvrdpim \0" |
| /* 6219 */ "xvrspim \0" |
| /* 6228 */ "frim \0" |
| /* 6234 */ "vrldnm \0" |
| /* 6242 */ "rlwinm \0" |
| /* 6250 */ "vrlqnm \0" |
| /* 6258 */ "vrlwnm \0" |
| /* 6266 */ "vexpandqm \0" |
| /* 6277 */ "mtvsrqm \0" |
| /* 6286 */ "vextractqm \0" |
| /* 6298 */ "vsubuqm \0" |
| /* 6307 */ "vadduqm \0" |
| /* 6316 */ "vsubeuqm \0" |
| /* 6326 */ "vaddeuqm \0" |
| /* 6336 */ "vperm \0" |
| /* 6343 */ "xxperm \0" |
| /* 6351 */ "vpkudum \0" |
| /* 6360 */ "vpkuhum \0" |
| /* 6369 */ "vpkuwum \0" |
| /* 6378 */ "vexpandwm \0" |
| /* 6389 */ "mtvsrwm \0" |
| /* 6398 */ "vextractwm \0" |
| /* 6410 */ "vsubuwm \0" |
| /* 6419 */ "vadduwm \0" |
| /* 6428 */ "vmuluwm \0" |
| /* 6437 */ "xxgenpcvwm \0" |
| /* 6449 */ "evmhegsmfan \0" |
| /* 6462 */ "evmhogsmfan \0" |
| /* 6475 */ "evmwsmfan \0" |
| /* 6486 */ "evmwssfan \0" |
| /* 6497 */ "evmhegsmian \0" |
| /* 6510 */ "evmhogsmian \0" |
| /* 6523 */ "evmwsmian \0" |
| /* 6534 */ "evmhegumian \0" |
| /* 6547 */ "evmhogumian \0" |
| /* 6560 */ "evmwumian \0" |
| /* 6571 */ "fcpsgn \0" |
| /* 6579 */ "vrfin \0" |
| /* 6586 */ "frin \0" |
| /* 6592 */ "mfsrin \0" |
| /* 6600 */ "mtsrin \0" |
| /* 6608 */ "pmxvbf16ger2nn \0" |
| /* 6624 */ "pmxvf16ger2nn \0" |
| /* 6639 */ "pmxvf32gernn \0" |
| /* 6653 */ "pmxvf64gernn \0" |
| /* 6667 */ "pmxvbf16ger2pn \0" |
| /* 6683 */ "pmxvf16ger2pn \0" |
| /* 6698 */ "xscvspdpn \0" |
| /* 6709 */ "pmxvf32gerpn \0" |
| /* 6723 */ "pmxvf64gerpn \0" |
| /* 6737 */ "xvcvbf16spn \0" |
| /* 6750 */ "xscvdpspn \0" |
| /* 6761 */ "darn \0" |
| /* 6767 */ "mffscrn \0" |
| /* 6776 */ "mffscdrn \0" |
| /* 6786 */ "addco \0" |
| /* 6793 */ "subfco \0" |
| /* 6801 */ "addo \0" |
| /* 6807 */ "mulldo \0" |
| /* 6815 */ "divdo \0" |
| /* 6822 */ "addeo \0" |
| /* 6829 */ "divdeo \0" |
| /* 6837 */ "subfeo \0" |
| /* 6845 */ "addmeo \0" |
| /* 6853 */ "subfmeo \0" |
| /* 6862 */ "divweo \0" |
| /* 6870 */ "addzeo \0" |
| /* 6878 */ "subfzeo \0" |
| /* 6887 */ "subfo \0" |
| /* 6894 */ "nego \0" |
| /* 6900 */ "evstwho \0" |
| /* 6909 */ "evmergelo \0" |
| /* 6920 */ "evmergehilo \0" |
| /* 6933 */ "vslo \0" |
| /* 6939 */ "xscvqpdpo \0" |
| /* 6950 */ "fcmpo \0" |
| /* 6957 */ "xsnmsubqpo \0" |
| /* 6969 */ "xsmsubqpo \0" |
| /* 6980 */ "xssubqpo \0" |
| /* 6990 */ "xsnmaddqpo \0" |
| /* 7002 */ "xsmaddqpo \0" |
| /* 7013 */ "xsaddqpo \0" |
| /* 7023 */ "xsmulqpo \0" |
| /* 7033 */ "xssqrtqpo \0" |
| /* 7044 */ "xsdivqpo \0" |
| /* 7054 */ "vsro \0" |
| /* 7060 */ "divduo \0" |
| /* 7068 */ "divdeuo \0" |
| /* 7077 */ "divweuo \0" |
| /* 7086 */ "divwuo \0" |
| /* 7094 */ "mullwo \0" |
| /* 7102 */ "divwo \0" |
| /* 7109 */ "evstwwo \0" |
| /* 7118 */ "xsnmsubadp \0" |
| /* 7130 */ "xvnmsubadp \0" |
| /* 7142 */ "xsmsubadp \0" |
| /* 7153 */ "xvmsubadp \0" |
| /* 7164 */ "xsnmaddadp \0" |
| /* 7176 */ "xvnmaddadp \0" |
| /* 7188 */ "xsmaddadp \0" |
| /* 7199 */ "xvmaddadp \0" |
| /* 7210 */ "xssubdp \0" |
| /* 7219 */ "xvsubdp \0" |
| /* 7228 */ "xststdcdp \0" |
| /* 7239 */ "xvtstdcdp \0" |
| /* 7250 */ "xsmincdp \0" |
| /* 7260 */ "xsmaxcdp \0" |
| /* 7270 */ "xsadddp \0" |
| /* 7279 */ "xvadddp \0" |
| /* 7288 */ "xscvsxddp \0" |
| /* 7299 */ "xvcvsxddp \0" |
| /* 7310 */ "xscvuxddp \0" |
| /* 7321 */ "xvcvuxddp \0" |
| /* 7332 */ "xscmpgedp \0" |
| /* 7343 */ "xvcmpgedp \0" |
| /* 7354 */ "xsredp \0" |
| /* 7362 */ "xvredp \0" |
| /* 7370 */ "xsrsqrtedp \0" |
| /* 7382 */ "xvrsqrtedp \0" |
| /* 7394 */ "xsnegdp \0" |
| /* 7403 */ "xvnegdp \0" |
| /* 7412 */ "xsxsigdp \0" |
| /* 7422 */ "xvxsigdp \0" |
| /* 7432 */ "xxspltidp \0" |
| /* 7443 */ "xsminjdp \0" |
| /* 7453 */ "xsmaxjdp \0" |
| /* 7463 */ "xsmuldp \0" |
| /* 7472 */ "xvmuldp \0" |
| /* 7481 */ "xsnmsubmdp \0" |
| /* 7493 */ "xvnmsubmdp \0" |
| /* 7505 */ "xsmsubmdp \0" |
| /* 7516 */ "xvmsubmdp \0" |
| /* 7527 */ "xsnmaddmdp \0" |
| /* 7539 */ "xvnmaddmdp \0" |
| /* 7551 */ "xsmaddmdp \0" |
| /* 7562 */ "xvmaddmdp \0" |
| /* 7573 */ "xscpsgndp \0" |
| /* 7584 */ "xvcpsgndp \0" |
| /* 7595 */ "xsmindp \0" |
| /* 7604 */ "xvmindp \0" |
| /* 7613 */ "xscmpodp \0" |
| /* 7623 */ "xscvhpdp \0" |
| /* 7633 */ "xscvqpdp \0" |
| /* 7643 */ "xscvspdp \0" |
| /* 7653 */ "xvcvspdp \0" |
| /* 7663 */ "xsiexpdp \0" |
| /* 7673 */ "xviexpdp \0" |
| /* 7683 */ "xscmpexpdp \0" |
| /* 7695 */ "xsxexpdp \0" |
| /* 7705 */ "xvxexpdp \0" |
| /* 7715 */ "xscmpeqdp \0" |
| /* 7726 */ "xvcmpeqdp \0" |
| /* 7737 */ "xsnabsdp \0" |
| /* 7747 */ "xvnabsdp \0" |
| /* 7757 */ "xsabsdp \0" |
| /* 7766 */ "xvabsdp \0" |
| /* 7775 */ "xscmpgtdp \0" |
| /* 7786 */ "xvcmpgtdp \0" |
| /* 7797 */ "xssqrtdp \0" |
| /* 7807 */ "xstsqrtdp \0" |
| /* 7818 */ "xvtsqrtdp \0" |
| /* 7829 */ "xvsqrtdp \0" |
| /* 7839 */ "xscmpudp \0" |
| /* 7849 */ "xsdivdp \0" |
| /* 7858 */ "xstdivdp \0" |
| /* 7868 */ "xvtdivdp \0" |
| /* 7878 */ "xvdivdp \0" |
| /* 7887 */ "xvcvsxwdp \0" |
| /* 7898 */ "xvcvuxwdp \0" |
| /* 7909 */ "xsmaxdp \0" |
| /* 7918 */ "xvmaxdp \0" |
| /* 7927 */ "dcbfep \0" |
| /* 7935 */ "icbiep \0" |
| /* 7943 */ "dcbzlep \0" |
| /* 7952 */ "dcbtep \0" |
| /* 7960 */ "dcbstep \0" |
| /* 7969 */ "dcbtstep \0" |
| /* 7979 */ "dcbzep \0" |
| /* 7987 */ "vcmpbfp \0" |
| /* 7996 */ "vnmsubfp \0" |
| /* 8006 */ "vsubfp \0" |
| /* 8014 */ "vmaddfp \0" |
| /* 8023 */ "vaddfp \0" |
| /* 8031 */ "vlogefp \0" |
| /* 8040 */ "vcmpgefp \0" |
| /* 8050 */ "vrefp \0" |
| /* 8057 */ "vexptefp \0" |
| /* 8067 */ "vrsqrtefp \0" |
| /* 8078 */ "vminfp \0" |
| /* 8086 */ "vcmpeqfp \0" |
| /* 8096 */ "vcmpgtfp \0" |
| /* 8106 */ "vmaxfp \0" |
| /* 8114 */ "xscvdphp \0" |
| /* 8124 */ "xvcvsphp \0" |
| /* 8134 */ "vrfip \0" |
| /* 8141 */ "xsrdpip \0" |
| /* 8150 */ "xvrdpip \0" |
| /* 8159 */ "xvrspip \0" |
| /* 8168 */ "frip \0" |
| /* 8174 */ "hashchkp \0" |
| /* 8184 */ "dcbflp \0" |
| /* 8192 */ "pmxvbf16ger2np \0" |
| /* 8208 */ "pmxvf16ger2np \0" |
| /* 8223 */ "pmxvf32gernp \0" |
| /* 8237 */ "pmxvf64gernp \0" |
| /* 8251 */ "pmxvbf16ger2pp \0" |
| /* 8267 */ "pmxvf16ger2pp \0" |
| /* 8282 */ "pmxvi16ger2pp \0" |
| /* 8297 */ "pmxvi8ger4pp \0" |
| /* 8311 */ "pmxvi4ger8pp \0" |
| /* 8325 */ "pmxvf32gerpp \0" |
| /* 8339 */ "pmxvf64gerpp \0" |
| /* 8353 */ "pmxvi16ger2spp \0" |
| /* 8369 */ "pmxvi8ger4spp \0" |
| /* 8384 */ "xsnmsubqp \0" |
| /* 8395 */ "xsmsubqp \0" |
| /* 8405 */ "xssubqp \0" |
| /* 8414 */ "xststdcqp \0" |
| /* 8425 */ "xsmincqp \0" |
| /* 8435 */ "xsmaxcqp \0" |
| /* 8445 */ "xsnmaddqp \0" |
| /* 8456 */ "xsmaddqp \0" |
| /* 8466 */ "xsaddqp \0" |
| /* 8475 */ "xscvsdqp \0" |
| /* 8485 */ "xscvudqp \0" |
| /* 8495 */ "xscmpgeqp \0" |
| /* 8506 */ "xsnegqp \0" |
| /* 8515 */ "xsxsigqp \0" |
| /* 8525 */ "xsmulqp \0" |
| /* 8534 */ "xscpsgnqp \0" |
| /* 8545 */ "xscmpoqp \0" |
| /* 8555 */ "xscvdpqp \0" |
| /* 8565 */ "xsiexpqp \0" |
| /* 8575 */ "xscmpexpqp \0" |
| /* 8587 */ "xsxexpqp \0" |
| /* 8597 */ "xscmpeqqp \0" |
| /* 8608 */ "xscvsqqp \0" |
| /* 8618 */ "xscvuqqp \0" |
| /* 8628 */ "xsnabsqp \0" |
| /* 8638 */ "xsabsqp \0" |
| /* 8647 */ "xscmpgtqp \0" |
| /* 8658 */ "xssqrtqp \0" |
| /* 8668 */ "xscmpuqp \0" |
| /* 8678 */ "xsdivqp \0" |
| /* 8687 */ "xsnmsubasp \0" |
| /* 8699 */ "xvnmsubasp \0" |
| /* 8711 */ "xsmsubasp \0" |
| /* 8722 */ "xvmsubasp \0" |
| /* 8733 */ "xsnmaddasp \0" |
| /* 8745 */ "xvnmaddasp \0" |
| /* 8757 */ "xsmaddasp \0" |
| /* 8768 */ "xvmaddasp \0" |
| /* 8779 */ "xssubsp \0" |
| /* 8788 */ "xvsubsp \0" |
| /* 8797 */ "xststdcsp \0" |
| /* 8808 */ "xvtstdcsp \0" |
| /* 8819 */ "xsaddsp \0" |
| /* 8828 */ "xvaddsp \0" |
| /* 8837 */ "xscvsxdsp \0" |
| /* 8848 */ "xvcvsxdsp \0" |
| /* 8859 */ "xscvuxdsp \0" |
| /* 8870 */ "xvcvuxdsp \0" |
| /* 8881 */ "xvcmpgesp \0" |
| /* 8892 */ "xsresp \0" |
| /* 8900 */ "xvresp \0" |
| /* 8908 */ "xsrsqrtesp \0" |
| /* 8920 */ "xvrsqrtesp \0" |
| /* 8932 */ "xvnegsp \0" |
| /* 8941 */ "xvxsigsp \0" |
| /* 8951 */ "xsmulsp \0" |
| /* 8960 */ "xvmulsp \0" |
| /* 8969 */ "xsnmsubmsp \0" |
| /* 8981 */ "xvnmsubmsp \0" |
| /* 8993 */ "xsmsubmsp \0" |
| /* 9004 */ "xvmsubmsp \0" |
| /* 9015 */ "xsnmaddmsp \0" |
| /* 9027 */ "xvnmaddmsp \0" |
| /* 9039 */ "xsmaddmsp \0" |
| /* 9050 */ "xvmaddmsp \0" |
| /* 9061 */ "xvcpsgnsp \0" |
| /* 9072 */ "xvminsp \0" |
| /* 9081 */ "xscvdpsp \0" |
| /* 9091 */ "xvcvdpsp \0" |
| /* 9101 */ "xvcvhpsp \0" |
| /* 9111 */ "xviexpsp \0" |
| /* 9121 */ "xvxexpsp \0" |
| /* 9131 */ "xvcmpeqsp \0" |
| /* 9142 */ "frsp \0" |
| /* 9148 */ "xsrsp \0" |
| /* 9155 */ "xvnabssp \0" |
| /* 9165 */ "xvabssp \0" |
| /* 9174 */ "plxssp \0" |
| /* 9182 */ "pstxssp \0" |
| /* 9191 */ "xvcmpgtsp \0" |
| /* 9202 */ "xssqrtsp \0" |
| /* 9212 */ "xvtsqrtsp \0" |
| /* 9223 */ "xvsqrtsp \0" |
| /* 9233 */ "xsdivsp \0" |
| /* 9242 */ "xvtdivsp \0" |
| /* 9252 */ "xvdivsp \0" |
| /* 9261 */ "xvcvsxwsp \0" |
| /* 9272 */ "xvcvuxwsp \0" |
| /* 9283 */ "xvmaxsp \0" |
| /* 9292 */ "hashstp \0" |
| /* 9301 */ "plxvp \0" |
| /* 9308 */ "pstxvp \0" |
| /* 9316 */ "xsrqpxp \0" |
| /* 9325 */ "vextsd2q \0" |
| /* 9335 */ "vsraq \0" |
| /* 9342 */ "vprtybq \0" |
| /* 9351 */ "efdcmpeq \0" |
| /* 9361 */ "efscmpeq \0" |
| /* 9371 */ "evfscmpeq \0" |
| /* 9382 */ "evcmpeq \0" |
| /* 9391 */ "efdtsteq \0" |
| /* 9401 */ "efststeq \0" |
| /* 9411 */ "evfststeq \0" |
| /* 9422 */ "lxvkq \0" |
| /* 9429 */ "vrlq \0" |
| /* 9435 */ "vslq \0" |
| /* 9441 */ "vbpermq \0" |
| /* 9450 */ "xxbrq \0" |
| /* 9457 */ "vsrq \0" |
| /* 9463 */ "vmodsq \0" |
| /* 9471 */ "vdivesq \0" |
| /* 9480 */ "vcmpsq \0" |
| /* 9488 */ "vcmpgtsq \0" |
| /* 9498 */ "vdivsq \0" |
| /* 9506 */ "stq \0" |
| /* 9511 */ "vmul10uq \0" |
| /* 9521 */ "vmul10cuq \0" |
| /* 9532 */ "vsubcuq \0" |
| /* 9541 */ "vaddcuq \0" |
| /* 9550 */ "vmul10ecuq \0" |
| /* 9562 */ "vsubecuq \0" |
| /* 9572 */ "vaddecuq \0" |
| /* 9582 */ "vmoduq \0" |
| /* 9590 */ "vmul10euq \0" |
| /* 9601 */ "vdiveuq \0" |
| /* 9610 */ "vcmpuq \0" |
| /* 9618 */ "vcmpequq \0" |
| /* 9628 */ "vcmpgtuq \0" |
| /* 9638 */ "vdivuq \0" |
| /* 9646 */ "#TC_RETURNr \0" |
| /* 9659 */ "mbar \0" |
| /* 9665 */ "vstribr \0" |
| /* 9674 */ "setnbcr \0" |
| /* 9683 */ "setbcr \0" |
| /* 9691 */ "mfdcr \0" |
| /* 9698 */ "rldcr \0" |
| /* 9705 */ "mtdcr \0" |
| /* 9712 */ "mfcr \0" |
| /* 9718 */ "rldicr \0" |
| /* 9726 */ "mfvscr \0" |
| /* 9734 */ "mtvscr \0" |
| /* 9742 */ "pmxvf32ger \0" |
| /* 9754 */ "pmxvf64ger \0" |
| /* 9766 */ "vncipher \0" |
| /* 9776 */ "vcipher \0" |
| /* 9785 */ "vstrihr \0" |
| /* 9794 */ "bclr \0" |
| /* 9800 */ "mflr \0" |
| /* 9806 */ "mtlr \0" |
| /* 9812 */ "fmr \0" |
| /* 9817 */ "dmmr \0" |
| /* 9823 */ "mfpmr \0" |
| /* 9830 */ "mtpmr \0" |
| /* 9837 */ "vpermr \0" |
| /* 9845 */ "xxpermr \0" |
| /* 9854 */ "xxlor \0" |
| /* 9861 */ "xxlnor \0" |
| /* 9869 */ "crnor \0" |
| /* 9876 */ "evnor \0" |
| /* 9883 */ "cror \0" |
| /* 9889 */ "evor \0" |
| /* 9895 */ "xxlxor \0" |
| /* 9903 */ "dmxor \0" |
| /* 9910 */ "vpermxor \0" |
| /* 9920 */ "crxor \0" |
| /* 9927 */ "evxor \0" |
| /* 9934 */ "mfspr \0" |
| /* 9941 */ "mtspr \0" |
| /* 9948 */ "mfsr \0" |
| /* 9954 */ "mfmsr \0" |
| /* 9961 */ "mtmsr \0" |
| /* 9968 */ "mtsr \0" |
| /* 9974 */ "lvsr \0" |
| /* 9980 */ "bcctr \0" |
| /* 9987 */ "mfctr \0" |
| /* 9994 */ "mtctr \0" |
| /* 10001 */ "pmxvi16ger2s \0" |
| /* 10015 */ "efdabs \0" |
| /* 10023 */ "fabs \0" |
| /* 10029 */ "efdnabs \0" |
| /* 10038 */ "fnabs \0" |
| /* 10045 */ "efsnabs \0" |
| /* 10054 */ "evfsnabs \0" |
| /* 10064 */ "efsabs \0" |
| /* 10072 */ "evfsabs \0" |
| /* 10081 */ "evabs \0" |
| /* 10088 */ "vsum4sbs \0" |
| /* 10098 */ "vsubsbs \0" |
| /* 10107 */ "vaddsbs \0" |
| /* 10116 */ "vsum4ubs \0" |
| /* 10126 */ "vsububs \0" |
| /* 10135 */ "vaddubs \0" |
| /* 10144 */ "fsubs \0" |
| /* 10151 */ "fmsubs \0" |
| /* 10159 */ "fnmsubs \0" |
| /* 10168 */ "fadds \0" |
| /* 10175 */ "fmadds \0" |
| /* 10183 */ "fnmadds \0" |
| /* 10192 */ "fcfids \0" |
| /* 10200 */ "dcbtds \0" |
| /* 10208 */ "dcbtstds \0" |
| /* 10218 */ "xscvdpsxds \0" |
| /* 10230 */ "xvcvdpsxds \0" |
| /* 10242 */ "xvcvspsxds \0" |
| /* 10254 */ "xscvdpuxds \0" |
| /* 10266 */ "xvcvdpuxds \0" |
| /* 10278 */ "xvcvspuxds \0" |
| /* 10290 */ "fres \0" |
| /* 10296 */ "frsqrtes \0" |
| /* 10306 */ "efdcfs \0" |
| /* 10314 */ "mffs \0" |
| /* 10320 */ "plfs \0" |
| /* 10326 */ "mcrfs \0" |
| /* 10333 */ "pstfs \0" |
| /* 10340 */ "vsum4shs \0" |
| /* 10350 */ "vsubshs \0" |
| /* 10359 */ "vmhaddshs \0" |
| /* 10370 */ "vmhraddshs \0" |
| /* 10382 */ "vaddshs \0" |
| /* 10391 */ "vmsumshs \0" |
| /* 10401 */ "vsubuhs \0" |
| /* 10410 */ "vadduhs \0" |
| /* 10419 */ "vmsumuhs \0" |
| /* 10429 */ "subis \0" |
| /* 10436 */ "subpcis \0" |
| /* 10445 */ "addpcis \0" |
| /* 10454 */ "addis \0" |
| /* 10461 */ "lis \0" |
| /* 10466 */ "xoris \0" |
| /* 10473 */ "evsrwis \0" |
| /* 10482 */ "icbtls \0" |
| /* 10490 */ "fmuls \0" |
| /* 10497 */ "evlwhos \0" |
| /* 10506 */ "dcbfps \0" |
| /* 10514 */ "dcbstps \0" |
| /* 10523 */ "vpksdss \0" |
| /* 10532 */ "vpkshss \0" |
| /* 10541 */ "vpkswss \0" |
| /* 10550 */ "evcmpgts \0" |
| /* 10560 */ "evcmplts \0" |
| /* 10570 */ "fsqrts \0" |
| /* 10578 */ "fcfidus \0" |
| /* 10587 */ "vpksdus \0" |
| /* 10596 */ "vpkudus \0" |
| /* 10605 */ "subfus \0" |
| /* 10613 */ "vpkshus \0" |
| /* 10622 */ "vpkuhus \0" |
| /* 10631 */ "vpkswus \0" |
| /* 10640 */ "vpkuwus \0" |
| /* 10649 */ "fdivs \0" |
| /* 10656 */ "evsrws \0" |
| /* 10664 */ "mtvsrws \0" |
| /* 10673 */ "vsum2sws \0" |
| /* 10683 */ "vsubsws \0" |
| /* 10692 */ "vaddsws \0" |
| /* 10701 */ "vsumsws \0" |
| /* 10710 */ "vsubuws \0" |
| /* 10719 */ "vadduws \0" |
| /* 10728 */ "evdivws \0" |
| /* 10737 */ "xscvdpsxws \0" |
| /* 10749 */ "xvcvdpsxws \0" |
| /* 10761 */ "xvcvspsxws \0" |
| /* 10773 */ "xscvdpuxws \0" |
| /* 10785 */ "xvcvdpuxws \0" |
| /* 10797 */ "xvcvspuxws \0" |
| /* 10809 */ "vctsxs \0" |
| /* 10817 */ "vctuxs \0" |
| /* 10825 */ "ldat \0" |
| /* 10831 */ "stdat \0" |
| /* 10838 */ "evlhhesplat \0" |
| /* 10851 */ "evlwhsplat \0" |
| /* 10863 */ "evlhhossplat \0" |
| /* 10877 */ "evlhhousplat \0" |
| /* 10891 */ "evlwwsplat \0" |
| /* 10903 */ "lwat \0" |
| /* 10909 */ "stwat \0" |
| /* 10916 */ "dcbt \0" |
| /* 10922 */ "icbt \0" |
| /* 10928 */ "dcbtct \0" |
| /* 10936 */ "dcbtstct \0" |
| /* 10946 */ "efdcmpgt \0" |
| /* 10956 */ "efscmpgt \0" |
| /* 10966 */ "evfscmpgt \0" |
| /* 10977 */ "efdtstgt \0" |
| /* 10987 */ "efststgt \0" |
| /* 10997 */ "evfststgt \0" |
| /* 11008 */ "wait \0" |
| /* 11014 */ "efdcmplt \0" |
| /* 11024 */ "efscmplt \0" |
| /* 11034 */ "evfscmplt \0" |
| /* 11045 */ "efdtstlt \0" |
| /* 11055 */ "efststlt \0" |
| /* 11065 */ "evfststlt \0" |
| /* 11076 */ "crnot \0" |
| /* 11083 */ "fsqrt \0" |
| /* 11090 */ "ftsqrt \0" |
| /* 11098 */ "vncipherlast \0" |
| /* 11112 */ "vcipherlast \0" |
| /* 11125 */ "dcbst \0" |
| /* 11132 */ "dst \0" |
| /* 11137 */ "hashst \0" |
| /* 11145 */ "dcbtst \0" |
| /* 11153 */ "dstst \0" |
| /* 11160 */ "dcbtt \0" |
| /* 11167 */ "dstt \0" |
| /* 11173 */ "dcbtstt \0" |
| /* 11182 */ "dststt \0" |
| /* 11190 */ "lhau \0" |
| /* 11196 */ "stbu \0" |
| /* 11202 */ "lfdu \0" |
| /* 11208 */ "stfdu \0" |
| /* 11215 */ "maddhdu \0" |
| /* 11224 */ "mulhdu \0" |
| /* 11232 */ "fcfidu \0" |
| /* 11240 */ "fctidu \0" |
| /* 11248 */ "ldu \0" |
| /* 11253 */ "stdu \0" |
| /* 11259 */ "divdu \0" |
| /* 11266 */ "divdeu \0" |
| /* 11274 */ "divweu \0" |
| /* 11282 */ "sthu \0" |
| /* 11288 */ "evsrwiu \0" |
| /* 11297 */ "evlwhou \0" |
| /* 11306 */ "fcmpu \0" |
| /* 11313 */ "lfsu \0" |
| /* 11319 */ "stfsu \0" |
| /* 11326 */ "evcmpgtu \0" |
| /* 11336 */ "evcmpltu \0" |
| /* 11346 */ "mulhwu \0" |
| /* 11354 */ "fctiwu \0" |
| /* 11362 */ "evsrwu \0" |
| /* 11370 */ "stwu \0" |
| /* 11376 */ "evdivwu \0" |
| /* 11385 */ "lbzu \0" |
| /* 11391 */ "lhzu \0" |
| /* 11397 */ "lwzu \0" |
| /* 11403 */ "slbmfev \0" |
| /* 11412 */ "efddiv \0" |
| /* 11420 */ "fdiv \0" |
| /* 11426 */ "efsdiv \0" |
| /* 11434 */ "evfsdiv \0" |
| /* 11443 */ "ftdiv \0" |
| /* 11450 */ "vslv \0" |
| /* 11456 */ "xxleqv \0" |
| /* 11464 */ "creqv \0" |
| /* 11471 */ "eveqv \0" |
| /* 11478 */ "vsrv \0" |
| /* 11484 */ "plxv \0" |
| /* 11490 */ "pstxv \0" |
| /* 11497 */ "vextsb2w \0" |
| /* 11507 */ "vextsh2w \0" |
| /* 11517 */ "evmhesmfaaw \0" |
| /* 11530 */ "evmhosmfaaw \0" |
| /* 11543 */ "evmhessfaaw \0" |
| /* 11556 */ "evmhossfaaw \0" |
| /* 11569 */ "evaddsmiaaw \0" |
| /* 11582 */ "evmhesmiaaw \0" |
| /* 11595 */ "evsubfsmiaaw \0" |
| /* 11609 */ "evmwlsmiaaw \0" |
| /* 11622 */ "evmhosmiaaw \0" |
| /* 11635 */ "evaddumiaaw \0" |
| /* 11648 */ "evmheumiaaw \0" |
| /* 11661 */ "evsubfumiaaw \0" |
| /* 11675 */ "evmwlumiaaw \0" |
| /* 11688 */ "evmhoumiaaw \0" |
| /* 11701 */ "evaddssiaaw \0" |
| /* 11714 */ "evmhessiaaw \0" |
| /* 11727 */ "evsubfssiaaw \0" |
| /* 11741 */ "evmwlssiaaw \0" |
| /* 11754 */ "evmhossiaaw \0" |
| /* 11767 */ "evaddusiaaw \0" |
| /* 11780 */ "evmheusiaaw \0" |
| /* 11793 */ "evsubfusiaaw \0" |
| /* 11807 */ "evmwlusiaaw \0" |
| /* 11820 */ "evmhousiaaw \0" |
| /* 11833 */ "vshasigmaw \0" |
| /* 11845 */ "vsraw \0" |
| /* 11852 */ "vcntmbw \0" |
| /* 11861 */ "vprtybw \0" |
| /* 11870 */ "evaddw \0" |
| /* 11878 */ "evldw \0" |
| /* 11885 */ "evrndw \0" |
| /* 11893 */ "evstdw \0" |
| /* 11901 */ "vmrgew \0" |
| /* 11909 */ "vcmpnew \0" |
| /* 11918 */ "evsubfw \0" |
| /* 11927 */ "evsubifw \0" |
| /* 11937 */ "vnegw \0" |
| /* 11944 */ "vmrghw \0" |
| /* 11952 */ "xxmrghw \0" |
| /* 11961 */ "mulhw \0" |
| /* 11968 */ "evaddiw \0" |
| /* 11977 */ "fctiw \0" |
| /* 11984 */ "xxspltiw \0" |
| /* 11994 */ "vmrglw \0" |
| /* 12002 */ "xxmrglw \0" |
| /* 12011 */ "mullw \0" |
| /* 12018 */ "cmplw \0" |
| /* 12025 */ "evrlw \0" |
| /* 12032 */ "evslw \0" |
| /* 12039 */ "lmw \0" |
| /* 12044 */ "stmw \0" |
| /* 12050 */ "vpmsumw \0" |
| /* 12059 */ "evmhesmfanw \0" |
| /* 12072 */ "evmhosmfanw \0" |
| /* 12085 */ "evmhessfanw \0" |
| /* 12098 */ "evmhossfanw \0" |
| /* 12111 */ "evmhesmianw \0" |
| /* 12124 */ "evmwlsmianw \0" |
| /* 12137 */ "evmhosmianw \0" |
| /* 12150 */ "evmheumianw \0" |
| /* 12163 */ "evmwlumianw \0" |
| /* 12176 */ "evmhoumianw \0" |
| /* 12189 */ "evmhessianw \0" |
| /* 12202 */ "evmwlssianw \0" |
| /* 12215 */ "evmhossianw \0" |
| /* 12228 */ "evmheusianw \0" |
| /* 12241 */ "evmwlusianw \0" |
| /* 12254 */ "evmhousianw \0" |
| /* 12267 */ "vmrgow \0" |
| /* 12275 */ "cmpw \0" |
| /* 12281 */ "xxbrw \0" |
| /* 12288 */ "vsrw \0" |
| /* 12294 */ "vmodsw \0" |
| /* 12302 */ "vmulesw \0" |
| /* 12311 */ "vdivesw \0" |
| /* 12320 */ "vavgsw \0" |
| /* 12328 */ "vupkhsw \0" |
| /* 12337 */ "vmulhsw \0" |
| /* 12346 */ "vspltisw \0" |
| /* 12356 */ "vupklsw \0" |
| /* 12365 */ "evcntlsw \0" |
| /* 12375 */ "vminsw \0" |
| /* 12383 */ "vinsw \0" |
| /* 12390 */ "vmulosw \0" |
| /* 12399 */ "vcmpgtsw \0" |
| /* 12409 */ "extsw \0" |
| /* 12416 */ "vdivsw \0" |
| /* 12424 */ "vmaxsw \0" |
| /* 12432 */ "vspltw \0" |
| /* 12440 */ "xxspltw \0" |
| /* 12449 */ "vpopcntw \0" |
| /* 12459 */ "vinsertw \0" |
| /* 12469 */ "xxinsertw \0" |
| /* 12480 */ "pstw \0" |
| /* 12486 */ "vsubcuw \0" |
| /* 12495 */ "vaddcuw \0" |
| /* 12504 */ "vmoduw \0" |
| /* 12512 */ "vabsduw \0" |
| /* 12521 */ "vmuleuw \0" |
| /* 12530 */ "vdiveuw \0" |
| /* 12539 */ "vavguw \0" |
| /* 12547 */ "vmulhuw \0" |
| /* 12556 */ "vminuw \0" |
| /* 12564 */ "vmulouw \0" |
| /* 12573 */ "vcmpequw \0" |
| /* 12583 */ "vextractuw \0" |
| /* 12595 */ "xxextractuw \0" |
| /* 12608 */ "vcmpgtuw \0" |
| /* 12618 */ "vdivuw \0" |
| /* 12626 */ "vmaxuw \0" |
| /* 12634 */ "xxblendvw \0" |
| /* 12645 */ "divw \0" |
| /* 12651 */ "vcmpnezw \0" |
| /* 12661 */ "vclzw \0" |
| /* 12668 */ "evcntlzw \0" |
| /* 12678 */ "vctzw \0" |
| /* 12685 */ "cnttzw \0" |
| /* 12693 */ "lxvd2x \0" |
| /* 12701 */ "stxvd2x \0" |
| /* 12710 */ "lxvw4x \0" |
| /* 12718 */ "stxvw4x \0" |
| /* 12727 */ "lxvb16x \0" |
| /* 12736 */ "stxvb16x \0" |
| /* 12746 */ "lxvh8x \0" |
| /* 12754 */ "stxvh8x \0" |
| /* 12763 */ "lhax \0" |
| /* 12769 */ "tlbivax \0" |
| /* 12778 */ "lfiwax \0" |
| /* 12786 */ "lxsiwax \0" |
| /* 12795 */ "lwax \0" |
| /* 12801 */ "lvebx \0" |
| /* 12808 */ "stvebx \0" |
| /* 12816 */ "stxsibx \0" |
| /* 12825 */ "lxvrbx \0" |
| /* 12833 */ "stxvrbx \0" |
| /* 12842 */ "stbx \0" |
| /* 12848 */ "xxsplti32dx \0" |
| /* 12861 */ "evlddx \0" |
| /* 12869 */ "evstddx \0" |
| /* 12878 */ "lfdx \0" |
| /* 12884 */ "stfdx \0" |
| /* 12891 */ "ldx \0" |
| /* 12896 */ "lxvrdx \0" |
| /* 12904 */ "stxvrdx \0" |
| /* 12913 */ "lxsdx \0" |
| /* 12920 */ "stxsdx \0" |
| /* 12928 */ "stdx \0" |
| /* 12934 */ "addex \0" |
| /* 12941 */ "evlwhex \0" |
| /* 12950 */ "evstwhex \0" |
| /* 12960 */ "evstwwex \0" |
| /* 12970 */ "evldhx \0" |
| /* 12978 */ "evstdhx \0" |
| /* 12987 */ "lvehx \0" |
| /* 12994 */ "stvehx \0" |
| /* 13002 */ "stxsihx \0" |
| /* 13011 */ "lxvrhx \0" |
| /* 13019 */ "stxvrhx \0" |
| /* 13028 */ "sthx \0" |
| /* 13034 */ "stbcix \0" |
| /* 13042 */ "ldcix \0" |
| /* 13049 */ "stdcix \0" |
| /* 13057 */ "sthcix \0" |
| /* 13065 */ "stwcix \0" |
| /* 13073 */ "lbzcix \0" |
| /* 13081 */ "lhzcix \0" |
| /* 13089 */ "lwzcix \0" |
| /* 13097 */ "xsrqpix \0" |
| /* 13106 */ "vinsblx \0" |
| /* 13115 */ "vextublx \0" |
| /* 13125 */ "vinsdlx \0" |
| /* 13134 */ "vinshlx \0" |
| /* 13143 */ "vextuhlx \0" |
| /* 13153 */ "vinsbvlx \0" |
| /* 13163 */ "vextdubvlx \0" |
| /* 13175 */ "vextddvlx \0" |
| /* 13186 */ "vinshvlx \0" |
| /* 13196 */ "vextduhvlx \0" |
| /* 13208 */ "vinswvlx \0" |
| /* 13218 */ "vextduwvlx \0" |
| /* 13230 */ "vinswlx \0" |
| /* 13239 */ "vextuwlx \0" |
| /* 13249 */ "xxpermx \0" |
| /* 13258 */ "vsbox \0" |
| /* 13265 */ "evstwhox \0" |
| /* 13275 */ "evstwwox \0" |
| /* 13285 */ "lbepx \0" |
| /* 13292 */ "stbepx \0" |
| /* 13300 */ "lfdepx \0" |
| /* 13308 */ "stfdepx \0" |
| /* 13317 */ "lhepx \0" |
| /* 13324 */ "sthepx \0" |
| /* 13332 */ "lwepx \0" |
| /* 13339 */ "stwepx \0" |
| /* 13347 */ "vupkhpx \0" |
| /* 13356 */ "vpkpx \0" |
| /* 13363 */ "vupklpx \0" |
| /* 13372 */ "lxsspx \0" |
| /* 13380 */ "stxsspx \0" |
| /* 13389 */ "lxvpx \0" |
| /* 13396 */ "stxvpx \0" |
| /* 13404 */ "lbarx \0" |
| /* 13411 */ "ldarx \0" |
| /* 13418 */ "lharx \0" |
| /* 13425 */ "lqarx \0" |
| /* 13432 */ "lwarx \0" |
| /* 13439 */ "ldbrx \0" |
| /* 13446 */ "stdbrx \0" |
| /* 13454 */ "lhbrx \0" |
| /* 13461 */ "sthbrx \0" |
| /* 13469 */ "vinsbrx \0" |
| /* 13478 */ "vextubrx \0" |
| /* 13488 */ "lwbrx \0" |
| /* 13495 */ "stwbrx \0" |
| /* 13503 */ "vinsdrx \0" |
| /* 13512 */ "vinshrx \0" |
| /* 13521 */ "vextuhrx \0" |
| /* 13531 */ "vinsbvrx \0" |
| /* 13541 */ "vextdubvrx \0" |
| /* 13553 */ "vextddvrx \0" |
| /* 13564 */ "vinshvrx \0" |
| /* 13574 */ "vextduhvrx \0" |
| /* 13586 */ "vinswvrx \0" |
| /* 13596 */ "vextduwvrx \0" |
| /* 13608 */ "vinswrx \0" |
| /* 13617 */ "vextuwrx \0" |
| /* 13627 */ "mcrxrx \0" |
| /* 13635 */ "tlbsx \0" |
| /* 13642 */ "lxvdsx \0" |
| /* 13650 */ "vcfsx \0" |
| /* 13657 */ "lfsx \0" |
| /* 13663 */ "stfsx \0" |
| /* 13670 */ "evlwhosx \0" |
| /* 13680 */ "lxvwsx \0" |
| /* 13688 */ "evlhhesplatx \0" |
| /* 13702 */ "evlwhsplatx \0" |
| /* 13715 */ "evlhhossplatx \0" |
| /* 13730 */ "evlhhousplatx \0" |
| /* 13745 */ "evlwwsplatx \0" |
| /* 13758 */ "lhaux \0" |
| /* 13765 */ "lwaux \0" |
| /* 13772 */ "stbux \0" |
| /* 13779 */ "lfdux \0" |
| /* 13786 */ "stfdux \0" |
| /* 13794 */ "ldux \0" |
| /* 13800 */ "stdux \0" |
| /* 13807 */ "vcfux \0" |
| /* 13814 */ "sthux \0" |
| /* 13821 */ "evlwhoux \0" |
| /* 13831 */ "lfsux \0" |
| /* 13838 */ "stfsux \0" |
| /* 13846 */ "stwux \0" |
| /* 13853 */ "lbzux \0" |
| /* 13860 */ "lhzux \0" |
| /* 13867 */ "lwzux \0" |
| /* 13874 */ "lvx \0" |
| /* 13879 */ "stvx \0" |
| /* 13885 */ "lxvx \0" |
| /* 13891 */ "stxvx \0" |
| /* 13898 */ "evldwx \0" |
| /* 13906 */ "evstdwx \0" |
| /* 13915 */ "lvewx \0" |
| /* 13922 */ "stvewx \0" |
| /* 13930 */ "stfiwx \0" |
| /* 13938 */ "stxsiwx \0" |
| /* 13947 */ "lxvrwx \0" |
| /* 13955 */ "stxvrwx \0" |
| /* 13964 */ "stwx \0" |
| /* 13970 */ "lxsibzx \0" |
| /* 13979 */ "lbzx \0" |
| /* 13985 */ "lxsihzx \0" |
| /* 13994 */ "lhzx \0" |
| /* 14000 */ "lfiwzx \0" |
| /* 14008 */ "lxsiwzx \0" |
| /* 14017 */ "lwzx \0" |
| /* 14023 */ "copy \0" |
| /* 14029 */ "dcbz \0" |
| /* 14035 */ "plbz \0" |
| /* 14041 */ "xxsetaccz \0" |
| /* 14052 */ "bdz \0" |
| /* 14057 */ "efdctsidz \0" |
| /* 14068 */ "fctidz \0" |
| /* 14076 */ "efdctuidz \0" |
| /* 14087 */ "xscvqpsdz \0" |
| /* 14098 */ "xscvqpudz \0" |
| /* 14109 */ "plhz \0" |
| /* 14115 */ "vrfiz \0" |
| /* 14122 */ "xsrdpiz \0" |
| /* 14131 */ "xvrdpiz \0" |
| /* 14140 */ "xvrspiz \0" |
| /* 14149 */ "friz \0" |
| /* 14155 */ "efdctsiz \0" |
| /* 14165 */ "efsctsiz \0" |
| /* 14175 */ "evfsctsiz \0" |
| /* 14186 */ "efdctuiz \0" |
| /* 14196 */ "efsctuiz \0" |
| /* 14206 */ "bdnz \0" |
| /* 14212 */ "xscvqpsqz \0" |
| /* 14223 */ "xscvqpuqz \0" |
| /* 14234 */ "dmsetdmrz \0" |
| /* 14245 */ "fctiduz \0" |
| /* 14254 */ "fctiwuz \0" |
| /* 14263 */ "fctiwz \0" |
| /* 14271 */ "plwz \0" |
| /* 14277 */ "mfvsrwz \0" |
| /* 14286 */ "mtvsrwz \0" |
| /* 14295 */ "xscvqpswz \0" |
| /* 14306 */ "xscvqpuwz \0" |
| /* 14317 */ "bdzlrl+\0" |
| /* 14325 */ "bdnzlrl+\0" |
| /* 14334 */ "bdzlr+\0" |
| /* 14341 */ "bdnzlr+\0" |
| /* 14349 */ "evsel crD,\0" |
| /* 14360 */ "bdzlrl-\0" |
| /* 14368 */ "bdnzlrl-\0" |
| /* 14377 */ "bdzlr-\0" |
| /* 14384 */ "bdnzlr-\0" |
| /* 14392 */ "# XRay Function Patchable RET.\0" |
| /* 14423 */ "# XRay Typed Event Log.\0" |
| /* 14447 */ "# XRay Custom Event Log.\0" |
| /* 14472 */ "# XRay Function Enter.\0" |
| /* 14495 */ "# XRay Tail Call Exit.\0" |
| /* 14518 */ "# XRay Function Exit.\0" |
| /* 14540 */ "trechkpt.\0" |
| /* 14550 */ "ori 1, 1, 0\0" |
| /* 14562 */ "ori 2, 2, 0\0" |
| /* 14574 */ "#ADDISdtprelHA32\0" |
| /* 14591 */ "#ATOMIC_LOAD_SUB_I32\0" |
| /* 14612 */ "#ATOMIC_LOAD_ADD_I32\0" |
| /* 14633 */ "#ATOMIC_LOAD_NAND_I32\0" |
| /* 14655 */ "#ATOMIC_LOAD_AND_I32\0" |
| /* 14676 */ "#ATOMIC_LOAD_UMIN_I32\0" |
| /* 14698 */ "#ATOMIC_LOAD_MIN_I32\0" |
| /* 14719 */ "#ATOMIC_SWAP_I32\0" |
| /* 14736 */ "#ATOMIC_LOAD_XOR_I32\0" |
| /* 14757 */ "#ATOMIC_LOAD_OR_I32\0" |
| /* 14777 */ "#ATOMIC_LOAD_UMAX_I32\0" |
| /* 14799 */ "#ATOMIC_LOAD_MAX_I32\0" |
| /* 14820 */ "#ADDItlsgdL32\0" |
| /* 14834 */ "#ADDItlsldL32\0" |
| /* 14848 */ "#LDgotTprelL32\0" |
| /* 14863 */ "#ADDIdtprelL32\0" |
| /* 14878 */ "#EH_SJLJ_LONGJMP32\0" |
| /* 14897 */ "#EH_SJLJ_SETJMP32\0" |
| /* 14915 */ "#ADDItlsgdLADDR32\0" |
| /* 14933 */ "#ADDItlsldLADDR32\0" |
| /* 14951 */ "GETtlsldADDR32\0" |
| /* 14966 */ "GETtlsADDR32\0" |
| /* 14979 */ "#PROBED_ALLOCA_32\0" |
| /* 14997 */ "#PREPARE_PROBED_ALLOCA_32\0" |
| /* 15023 */ "#PROBED_STACKALLOC_32\0" |
| /* 15045 */ "#PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_32\0" |
| /* 15088 */ "#DFLOADf32\0" |
| /* 15099 */ "#XFLOADf32\0" |
| /* 15110 */ "#DFSTOREf32\0" |
| /* 15122 */ "#XFSTOREf32\0" |
| /* 15134 */ "#ATOMIC_LOAD_SUB_I64\0" |
| /* 15155 */ "#ATOMIC_LOAD_ADD_I64\0" |
| /* 15176 */ "#ATOMIC_LOAD_NAND_I64\0" |
| /* 15198 */ "#ATOMIC_LOAD_UMIN_I64\0" |
| /* 15220 */ "#ATOMIC_LOAD_MIN_I64\0" |
| /* 15241 */ "#ATOMIC_SWAP_I64\0" |
| /* 15258 */ "#ATOMIC_CMP_SWAP_I64\0" |
| /* 15279 */ "#ATOMIC_LOAD_XOR_I64\0" |
| /* 15300 */ "#ATOMIC_LOAD_OR_I64\0" |
| /* 15320 */ "#ATOMIC_LOAD_UMAX_I64\0" |
| /* 15342 */ "#ATOMIC_LOAD_MAX_I64\0" |
| /* 15363 */ "#EH_SJLJ_LONGJMP64\0" |
| /* 15382 */ "#EH_SJLJ_SETJMP64\0" |
| /* 15400 */ "#PROBED_ALLOCA_64\0" |
| /* 15418 */ "#PREPARE_PROBED_ALLOCA_64\0" |
| /* 15444 */ "#PROBED_STACKALLOC_64\0" |
| /* 15466 */ "#PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_64\0" |
| /* 15509 */ "#DFLOADf64\0" |
| /* 15520 */ "#XFLOADf64\0" |
| /* 15531 */ "#DFSTOREf64\0" |
| /* 15543 */ "#XFSTOREf64\0" |
| /* 15555 */ "#ATOMIC_LOAD_AND_i64\0" |
| /* 15576 */ "#SELECT_CC_SPE4\0" |
| /* 15592 */ "#SELECT_SPE4\0" |
| /* 15605 */ "#SELECT_CC_F4\0" |
| /* 15619 */ "#SELECT_F4\0" |
| /* 15630 */ "#SELECT_CC_I4\0" |
| /* 15644 */ "#SELECT_I4\0" |
| /* 15655 */ "crxor 6, 6, 6\0" |
| /* 15669 */ "creqv 6, 6, 6\0" |
| /* 15683 */ "#SELECT_CC_F16\0" |
| /* 15698 */ "#SELECT_F16\0" |
| /* 15710 */ "#ATOMIC_LOAD_SUB_I16\0" |
| /* 15731 */ "#ATOMIC_LOAD_ADD_I16\0" |
| /* 15752 */ "#ATOMIC_LOAD_NAND_I16\0" |
| /* 15774 */ "#ATOMIC_LOAD_AND_I16\0" |
| /* 15795 */ "#ATOMIC_LOAD_UMIN_I16\0" |
| /* 15817 */ "#ATOMIC_LOAD_MIN_I16\0" |
| /* 15838 */ "#ATOMIC_SWAP_I16\0" |
| /* 15855 */ "#ATOMIC_LOAD_XOR_I16\0" |
| /* 15876 */ "#ATOMIC_LOAD_OR_I16\0" |
| /* 15896 */ "#ATOMIC_LOAD_UMAX_I16\0" |
| /* 15918 */ "#ATOMIC_LOAD_MAX_I16\0" |
| /* 15939 */ "#ATOMIC_LOAD_SUB_I128\0" |
| /* 15961 */ "#ATOMIC_LOAD_ADD_I128\0" |
| /* 15983 */ "#ATOMIC_LOAD_NAND_I128\0" |
| /* 16006 */ "#ATOMIC_LOAD_AND_I128\0" |
| /* 16028 */ "#ATOMIC_SWAP_I128\0" |
| /* 16046 */ "#ATOMIC_CMP_SWAP_I128\0" |
| /* 16068 */ "#ATOMIC_LOAD_XOR_I128\0" |
| /* 16090 */ "#ATOMIC_LOAD_OR_I128\0" |
| /* 16111 */ "#ADDIStocHA8\0" |
| /* 16124 */ "#DYNALLOC8\0" |
| /* 16135 */ "#CFENCE8\0" |
| /* 16144 */ "#SELECT_CC_F8\0" |
| /* 16158 */ "#SELECT_F8\0" |
| /* 16169 */ "#ATOMIC_LOAD_SUB_I8\0" |
| /* 16189 */ "#SELECT_CC_I8\0" |
| /* 16203 */ "#ATOMIC_LOAD_ADD_I8\0" |
| /* 16223 */ "#ATOMIC_LOAD_NAND_I8\0" |
| /* 16244 */ "#ATOMIC_LOAD_AND_I8\0" |
| /* 16264 */ "#ATOMIC_LOAD_UMIN_I8\0" |
| /* 16285 */ "#ATOMIC_LOAD_MIN_I8\0" |
| /* 16305 */ "#ATOMIC_CMP_SWAP_I8\0" |
| /* 16325 */ "ATOMIC_LOAD_XOR_I8\0" |
| /* 16344 */ "#ATOMIC_LOAD_OR_I8\0" |
| /* 16363 */ "#SELECT_I8\0" |
| /* 16374 */ "#ATOMIC_LOAD_UMAX_I8\0" |
| /* 16395 */ "#ATOMIC_LOAD_MAX_I8\0" |
| /* 16415 */ "#MovePCtoLR8\0" |
| /* 16428 */ "#DYNAREAOFFSET8\0" |
| /* 16444 */ "#ANDI_rec_1_EQ_BIT8\0" |
| /* 16464 */ "#ANDI_rec_1_GT_BIT8\0" |
| /* 16484 */ "#TLSGDAIX8\0" |
| /* 16495 */ "#ADDItoc8\0" |
| /* 16505 */ "#ATOMIC_SWAP_i8\0" |
| /* 16521 */ "#ADDIStocHA\0" |
| /* 16533 */ "#ADDIStlsgdHA\0" |
| /* 16547 */ "#ADDIStlsldHA\0" |
| /* 16561 */ "#ADDISgotTprelHA\0" |
| /* 16578 */ "#ADDISdtprelHA\0" |
| /* 16593 */ "#ReadTB\0" |
| /* 16601 */ "#RESTORE_UACC\0" |
| /* 16615 */ "#SPILL_UACC\0" |
| /* 16627 */ "#RESTORE_WACC\0" |
| /* 16641 */ "#SPILL_WACC\0" |
| /* 16653 */ "#RESTORE_ACC\0" |
| /* 16666 */ "#SPILL_ACC\0" |
| /* 16677 */ "#DYNALLOC\0" |
| /* 16687 */ "#SELECT_CC_VSFRC\0" |
| /* 16704 */ "#SELECT_VSFRC\0" |
| /* 16718 */ "#SELECT_CC_VRRC\0" |
| /* 16734 */ "#SELECT_VRRC\0" |
| /* 16747 */ "#SELECT_CC_VSSRC\0" |
| /* 16764 */ "#SELECT_VSSRC\0" |
| /* 16778 */ "#SELECT_CC_VSRC\0" |
| /* 16794 */ "#SELECT_VSRC\0" |
| /* 16807 */ "#SPILLTOVSR_LD\0" |
| /* 16822 */ "LIFETIME_END\0" |
| /* 16835 */ "#SETRND\0" |
| /* 16843 */ "#BUILD_QUADWORD\0" |
| /* 16859 */ "#RESTORE_QUADWORD\0" |
| /* 16877 */ "#SPILL_QUADWORD\0" |
| /* 16893 */ "#SPLIT_QUADWORD\0" |
| /* 16909 */ "PSEUDO_PROBE\0" |
| /* 16922 */ "BUNDLE\0" |
| /* 16929 */ "#SELECT_CC_SPE\0" |
| /* 16944 */ "#SELECT_SPE\0" |
| /* 16956 */ "DBG_VALUE\0" |
| /* 16966 */ "DBG_INSTR_REF\0" |
| /* 16980 */ "DBG_PHI\0" |
| /* 16988 */ "#LDtocJTI\0" |
| /* 16998 */ "DBG_LABEL\0" |
| /* 17008 */ "#GETtlsldADDRPCREL\0" |
| /* 17027 */ "#GETtlsADDRPCREL\0" |
| /* 17044 */ "#LDtocL\0" |
| /* 17052 */ "#ADDItocL\0" |
| /* 17062 */ "#LWZtocL\0" |
| /* 17071 */ "#ADDItlsgdL\0" |
| /* 17083 */ "#ADDItlsldL\0" |
| /* 17095 */ "#LDgotTprelL\0" |
| /* 17108 */ "#ADDIdtprelL\0" |
| /* 17121 */ "#SETFLM\0" |
| /* 17129 */ "#LQX_PSEUDO\0" |
| /* 17141 */ "#STQX_PSEUDO\0" |
| /* 17154 */ "#PPCEIEIO\0" |
| /* 17164 */ "#UNENCODED_NOP\0" |
| /* 17179 */ "#UpdateGBR\0" |
| /* 17190 */ "#RESTORE_CR\0" |
| /* 17202 */ "#SPILL_CR\0" |
| /* 17212 */ "#ADDItlsgdLADDR\0" |
| /* 17228 */ "#ADDItlsldLADDR\0" |
| /* 17244 */ "#GETtlsldADDR\0" |
| /* 17258 */ "#GETtlsADDR\0" |
| /* 17270 */ "#KILL_PAIR\0" |
| /* 17281 */ "#MovePCtoLR\0" |
| /* 17293 */ "#MoveGOTtoLR\0" |
| /* 17306 */ "#TCHECK_RET\0" |
| /* 17318 */ "#TBEGIN_RET\0" |
| /* 17330 */ "#DYNAREAOFFSET\0" |
| /* 17345 */ "#RESTORE_CRBIT\0" |
| /* 17360 */ "#SPILL_CRBIT\0" |
| /* 17373 */ "#ANDI_rec_1_EQ_BIT\0" |
| /* 17392 */ "#ANDI_rec_1_GT_BIT\0" |
| /* 17411 */ "#PPC32GOT\0" |
| /* 17421 */ "#PPC32PICGOT\0" |
| /* 17434 */ "#LDtocCPT\0" |
| /* 17444 */ "LIFETIME_START\0" |
| /* 17459 */ "DBG_VALUE_LIST\0" |
| /* 17474 */ "#SPILLTOVSR_ST\0" |
| /* 17489 */ "#LIWAX\0" |
| /* 17496 */ "#SPILLTOVSR_LDX\0" |
| /* 17512 */ "GETtlsADDR32AIX\0" |
| /* 17528 */ "GETtlsADDR64AIX\0" |
| /* 17544 */ "#TLSGDAIX\0" |
| /* 17554 */ "#SPILLTOVSR_STX\0" |
| /* 17570 */ "#STIWX\0" |
| /* 17577 */ "#LIWZX\0" |
| /* 17584 */ "bca\0" |
| /* 17588 */ "slbia\0" |
| /* 17594 */ "tlbia\0" |
| /* 17600 */ "bcla\0" |
| /* 17605 */ "clrbhrb\0" |
| /* 17613 */ "bc\0" |
| /* 17616 */ "slbsync\0" |
| /* 17624 */ "tlbsync\0" |
| /* 17632 */ "msgsync\0" |
| /* 17640 */ "isync\0" |
| /* 17646 */ "msync\0" |
| /* 17652 */ "#LDtoc\0" |
| /* 17659 */ "#ADDItoc\0" |
| /* 17668 */ "#LWZtoc\0" |
| /* 17676 */ "hrfid\0" |
| /* 17682 */ "tlbre\0" |
| /* 17688 */ "tlbwe\0" |
| /* 17694 */ "#SETRNDi\0" |
| /* 17703 */ "rfci\0" |
| /* 17708 */ "rfmci\0" |
| /* 17714 */ "rfdi\0" |
| /* 17719 */ "rfi\0" |
| /* 17723 */ "bcl\0" |
| /* 17727 */ "#PADDIdtprel\0" |
| /* 17740 */ "# FEntry call\0" |
| /* 17754 */ "dssall\0" |
| /* 17761 */ "blrl\0" |
| /* 17766 */ "bdzlrl\0" |
| /* 17773 */ "bdnzlrl\0" |
| /* 17781 */ "bctrl\0" |
| /* 17787 */ "attn\0" |
| /* 17792 */ "eieio\0" |
| /* 17798 */ "nap\0" |
| /* 17802 */ "trap\0" |
| /* 17807 */ "nop\0" |
| /* 17811 */ "#DecreaseCTR8loop\0" |
| /* 17829 */ "#DecreaseCTRloop\0" |
| /* 17846 */ "stop\0" |
| /* 17851 */ "blr\0" |
| /* 17855 */ "bdzlr\0" |
| /* 17861 */ "bdnzlr\0" |
| /* 17868 */ "bctr\0" |
| /* 17873 */ "cpabort\0" |
| }; |
| #ifdef __GNUC__ |
| #pragma GCC diagnostic pop |
| #endif |
| |
| static const uint32_t OpInfo0[] = { |
| 0U, // PHI |
| 0U, // INLINEASM |
| 0U, // INLINEASM_BR |
| 0U, // CFI_INSTRUCTION |
| 0U, // EH_LABEL |
| 0U, // GC_LABEL |
| 0U, // ANNOTATION_LABEL |
| 0U, // KILL |
| 0U, // EXTRACT_SUBREG |
| 0U, // INSERT_SUBREG |
| 0U, // IMPLICIT_DEF |
| 0U, // SUBREG_TO_REG |
| 0U, // COPY_TO_REGCLASS |
| 16957U, // DBG_VALUE |
| 17460U, // DBG_VALUE_LIST |
| 16967U, // DBG_INSTR_REF |
| 16981U, // DBG_PHI |
| 16999U, // DBG_LABEL |
| 0U, // REG_SEQUENCE |
| 0U, // COPY |
| 16923U, // BUNDLE |
| 17445U, // LIFETIME_START |
| 16823U, // LIFETIME_END |
| 16910U, // PSEUDO_PROBE |
| 0U, // ARITH_FENCE |
| 0U, // STACKMAP |
| 17741U, // FENTRY_CALL |
| 0U, // PATCHPOINT |
| 0U, // LOAD_STACK_GUARD |
| 0U, // PREALLOCATED_SETUP |
| 0U, // PREALLOCATED_ARG |
| 0U, // STATEPOINT |
| 0U, // LOCAL_ESCAPE |
| 0U, // FAULTING_OP |
| 0U, // PATCHABLE_OP |
| 14473U, // PATCHABLE_FUNCTION_ENTER |
| 14393U, // PATCHABLE_RET |
| 14519U, // PATCHABLE_FUNCTION_EXIT |
| 14496U, // PATCHABLE_TAIL_CALL |
| 14448U, // PATCHABLE_EVENT_CALL |
| 14424U, // PATCHABLE_TYPED_EVENT_CALL |
| 0U, // ICALL_BRANCH_FUNNEL |
| 0U, // MEMBARRIER |
| 0U, // G_ASSERT_SEXT |
| 0U, // G_ASSERT_ZEXT |
| 0U, // G_ASSERT_ALIGN |
| 0U, // G_ADD |
| 0U, // G_SUB |
| 0U, // G_MUL |
| 0U, // G_SDIV |
| 0U, // G_UDIV |
| 0U, // G_SREM |
| 0U, // G_UREM |
| 0U, // G_SDIVREM |
| 0U, // G_UDIVREM |
| 0U, // G_AND |
| 0U, // G_OR |
| 0U, // G_XOR |
| 0U, // G_IMPLICIT_DEF |
| 0U, // G_PHI |
| 0U, // G_FRAME_INDEX |
| 0U, // G_GLOBAL_VALUE |
| 0U, // G_EXTRACT |
| 0U, // G_UNMERGE_VALUES |
| 0U, // G_INSERT |
| 0U, // G_MERGE_VALUES |
| 0U, // G_BUILD_VECTOR |
| 0U, // G_BUILD_VECTOR_TRUNC |
| 0U, // G_CONCAT_VECTORS |
| 0U, // G_PTRTOINT |
| 0U, // G_INTTOPTR |
| 0U, // G_BITCAST |
| 0U, // G_FREEZE |
| 0U, // G_INTRINSIC_FPTRUNC_ROUND |
| 0U, // G_INTRINSIC_TRUNC |
| 0U, // G_INTRINSIC_ROUND |
| 0U, // G_INTRINSIC_LRINT |
| 0U, // G_INTRINSIC_ROUNDEVEN |
| 0U, // G_READCYCLECOUNTER |
| 0U, // G_LOAD |
| 0U, // G_SEXTLOAD |
| 0U, // G_ZEXTLOAD |
| 0U, // G_INDEXED_LOAD |
| 0U, // G_INDEXED_SEXTLOAD |
| 0U, // G_INDEXED_ZEXTLOAD |
| 0U, // G_STORE |
| 0U, // G_INDEXED_STORE |
| 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS |
| 0U, // G_ATOMIC_CMPXCHG |
| 0U, // G_ATOMICRMW_XCHG |
| 0U, // G_ATOMICRMW_ADD |
| 0U, // G_ATOMICRMW_SUB |
| 0U, // G_ATOMICRMW_AND |
| 0U, // G_ATOMICRMW_NAND |
| 0U, // G_ATOMICRMW_OR |
| 0U, // G_ATOMICRMW_XOR |
| 0U, // G_ATOMICRMW_MAX |
| 0U, // G_ATOMICRMW_MIN |
| 0U, // G_ATOMICRMW_UMAX |
| 0U, // G_ATOMICRMW_UMIN |
| 0U, // G_ATOMICRMW_FADD |
| 0U, // G_ATOMICRMW_FSUB |
| 0U, // G_ATOMICRMW_FMAX |
| 0U, // G_ATOMICRMW_FMIN |
| 0U, // G_ATOMICRMW_UINC_WRAP |
| 0U, // G_ATOMICRMW_UDEC_WRAP |
| 0U, // G_FENCE |
| 0U, // G_BRCOND |
| 0U, // G_BRINDIRECT |
| 0U, // G_INVOKE_REGION_START |
| 0U, // G_INTRINSIC |
| 0U, // G_INTRINSIC_W_SIDE_EFFECTS |
| 0U, // G_ANYEXT |
| 0U, // G_TRUNC |
| 0U, // G_CONSTANT |
| 0U, // G_FCONSTANT |
| 0U, // G_VASTART |
| 0U, // G_VAARG |
| 0U, // G_SEXT |
| 0U, // G_SEXT_INREG |
| 0U, // G_ZEXT |
| 0U, // G_SHL |
| 0U, // G_LSHR |
| 0U, // G_ASHR |
| 0U, // G_FSHL |
| 0U, // G_FSHR |
| 0U, // G_ROTR |
| 0U, // G_ROTL |
| 0U, // G_ICMP |
| 0U, // G_FCMP |
| 0U, // G_SELECT |
| 0U, // G_UADDO |
| 0U, // G_UADDE |
| 0U, // G_USUBO |
| 0U, // G_USUBE |
| 0U, // G_SADDO |
| 0U, // G_SADDE |
| 0U, // G_SSUBO |
| 0U, // G_SSUBE |
| 0U, // G_UMULO |
| 0U, // G_SMULO |
| 0U, // G_UMULH |
| 0U, // G_SMULH |
| 0U, // G_UADDSAT |
| 0U, // G_SADDSAT |
| 0U, // G_USUBSAT |
| 0U, // G_SSUBSAT |
| 0U, // G_USHLSAT |
| 0U, // G_SSHLSAT |
| 0U, // G_SMULFIX |
| 0U, // G_UMULFIX |
| 0U, // G_SMULFIXSAT |
| 0U, // G_UMULFIXSAT |
| 0U, // G_SDIVFIX |
| 0U, // G_UDIVFIX |
| 0U, // G_SDIVFIXSAT |
| 0U, // G_UDIVFIXSAT |
| 0U, // G_FADD |
| 0U, // G_FSUB |
| 0U, // G_FMUL |
| 0U, // G_FMA |
| 0U, // G_FMAD |
| 0U, // G_FDIV |
| 0U, // G_FREM |
| 0U, // G_FPOW |
| 0U, // G_FPOWI |
| 0U, // G_FEXP |
| 0U, // G_FEXP2 |
| 0U, // G_FLOG |
| 0U, // G_FLOG2 |
| 0U, // G_FLOG10 |
| 0U, // G_FNEG |
| 0U, // G_FPEXT |
| 0U, // G_FPTRUNC |
| 0U, // G_FPTOSI |
| 0U, // G_FPTOUI |
| 0U, // G_SITOFP |
| 0U, // G_UITOFP |
| 0U, // G_FABS |
| 0U, // G_FCOPYSIGN |
| 0U, // G_IS_FPCLASS |
| 0U, // G_FCANONICALIZE |
| 0U, // G_FMINNUM |
| 0U, // G_FMAXNUM |
| 0U, // G_FMINNUM_IEEE |
| 0U, // G_FMAXNUM_IEEE |
| 0U, // G_FMINIMUM |
| 0U, // G_FMAXIMUM |
| 0U, // G_PTR_ADD |
| 0U, // G_PTRMASK |
| 0U, // G_SMIN |
| 0U, // G_SMAX |
| 0U, // G_UMIN |
| 0U, // G_UMAX |
| 0U, // G_ABS |
| 0U, // G_LROUND |
| 0U, // G_LLROUND |
| 0U, // G_BR |
| 0U, // G_BRJT |
| 0U, // G_INSERT_VECTOR_ELT |
| 0U, // G_EXTRACT_VECTOR_ELT |
| 0U, // G_SHUFFLE_VECTOR |
| 0U, // G_CTTZ |
| 0U, // G_CTTZ_ZERO_UNDEF |
| 0U, // G_CTLZ |
| 0U, // G_CTLZ_ZERO_UNDEF |
| 0U, // G_CTPOP |
| 0U, // G_BSWAP |
| 0U, // G_BITREVERSE |
| 0U, // G_FCEIL |
| 0U, // G_FCOS |
| 0U, // G_FSIN |
| 0U, // G_FSQRT |
| 0U, // G_FFLOOR |
| 0U, // G_FRINT |
| 0U, // G_FNEARBYINT |
| 0U, // G_ADDRSPACE_CAST |
| 0U, // G_BLOCK_ADDR |
| 0U, // G_JUMP_TABLE |
| 0U, // G_DYN_STACKALLOC |
| 0U, // G_STRICT_FADD |
| 0U, // G_STRICT_FSUB |
| 0U, // G_STRICT_FMUL |
| 0U, // G_STRICT_FDIV |
| 0U, // G_STRICT_FREM |
| 0U, // G_STRICT_FMA |
| 0U, // G_STRICT_FSQRT |
| 0U, // G_READ_REGISTER |
| 0U, // G_WRITE_REGISTER |
| 0U, // G_MEMCPY |
| 0U, // G_MEMCPY_INLINE |
| 0U, // G_MEMMOVE |
| 0U, // G_MEMSET |
| 0U, // G_BZERO |
| 0U, // G_VECREDUCE_SEQ_FADD |
| 0U, // G_VECREDUCE_SEQ_FMUL |
| 0U, // G_VECREDUCE_FADD |
| 0U, // G_VECREDUCE_FMUL |
| 0U, // G_VECREDUCE_FMAX |
| 0U, // G_VECREDUCE_FMIN |
| 0U, // G_VECREDUCE_ADD |
| 0U, // G_VECREDUCE_MUL |
| 0U, // G_VECREDUCE_AND |
| 0U, // G_VECREDUCE_OR |
| 0U, // G_VECREDUCE_XOR |
| 0U, // G_VECREDUCE_SMAX |
| 0U, // G_VECREDUCE_SMIN |
| 0U, // G_VECREDUCE_UMAX |
| 0U, // G_VECREDUCE_UMIN |
| 0U, // G_SBFX |
| 0U, // G_UBFX |
| 16047U, // ATOMIC_CMP_SWAP_I128 |
| 15962U, // ATOMIC_LOAD_ADD_I128 |
| 16007U, // ATOMIC_LOAD_AND_I128 |
| 15984U, // ATOMIC_LOAD_NAND_I128 |
| 16091U, // ATOMIC_LOAD_OR_I128 |
| 15940U, // ATOMIC_LOAD_SUB_I128 |
| 16069U, // ATOMIC_LOAD_XOR_I128 |
| 16029U, // ATOMIC_SWAP_I128 |
| 16844U, // BUILD_QUADWORD |
| 35180U, // BUILD_UACC |
| 16136U, // CFENCE8 |
| 1073779613U, // CLRLSLDI |
| 1073775471U, // CLRLSLDI_rec |
| 1073780124U, // CLRLSLWI |
| 1073775580U, // CLRLSLWI_rec |
| 1073779648U, // CLRRDI |
| 1073775498U, // CLRRDI_rec |
| 1073780165U, // CLRRWI |
| 1073775609U, // CLRRWI_rec |
| 1119822U, // DCBFL |
| 1122297U, // DCBFLP |
| 1124619U, // DCBFPS |
| 1118458U, // DCBFx |
| 1124627U, // DCBSTPS |
| 33630897U, // DCBTCT |
| 33630169U, // DCBTDS |
| 33630905U, // DCBTSTCT |
| 33630177U, // DCBTSTDS |
| 1125286U, // DCBTSTT |
| 1125258U, // DCBTSTx |
| 1125273U, // DCBTT |
| 1125029U, // DCBTx |
| 15089U, // DFLOADf32 |
| 15510U, // DFLOADf64 |
| 15111U, // DFSTOREf32 |
| 15532U, // DFSTOREf64 |
| 1073779623U, // EXTLDI |
| 1073775482U, // EXTLDI_rec |
| 1073780150U, // EXTLWI |
| 1073775600U, // EXTLWI_rec |
| 1073779672U, // EXTRDI |
| 1073775525U, // EXTRDI_rec |
| 1073780189U, // EXTRWI |
| 1073775636U, // EXTRWI_rec |
| 1073780134U, // INSLWI |
| 1073775591U, // INSLWI_rec |
| 1073779656U, // INSRDI |
| 1073775507U, // INSRDI_rec |
| 1073780173U, // INSRWI |
| 1073775618U, // INSRWI_rec |
| 17271U, // KILL_PAIR |
| 67144429U, // LAx |
| 17490U, // LIWAX |
| 17578U, // LIWZX |
| 1073779791U, // RLWIMIbm |
| 1073775563U, // RLWIMIbm_rec |
| 1073780835U, // RLWINMbm |
| 1073775714U, // RLWINMbm_rec |
| 1073780852U, // RLWNMbm |
| 1073775723U, // RLWNMbm_rec |
| 1073779664U, // ROTRDI |
| 1073775516U, // ROTRDI_rec |
| 1073780181U, // ROTRWI |
| 1073775627U, // ROTRWI_rec |
| 1073779617U, // SLDI |
| 1073775475U, // SLDI_rec |
| 1073780128U, // SLWI |
| 1073775584U, // SLWI_rec |
| 16808U, // SPILLTOVSR_LD |
| 17497U, // SPILLTOVSR_LDX |
| 17475U, // SPILLTOVSR_ST |
| 17555U, // SPILLTOVSR_STX |
| 1073779658U, // SRDI |
| 1073775509U, // SRDI_rec |
| 1073780175U, // SRWI |
| 1073775620U, // SRWI_rec |
| 17571U, // STIWX |
| 1073779571U, // SUBI |
| 1073777976U, // SUBIC |
| 1073775037U, // SUBIC_rec |
| 1073785022U, // SUBIS |
| 100706501U, // SUBPCIS |
| 15100U, // XFLOADf32 |
| 15521U, // XFLOADf64 |
| 15123U, // XFSTOREf32 |
| 15544U, // XFSTOREf64 |
| 1073778168U, // ADD4 |
| 1073781394U, // ADD4O |
| 1073775814U, // ADD4O_rec |
| 1073778168U, // ADD4TLS |
| 1073775111U, // ADD4_rec |
| 1073778168U, // ADD8 |
| 1073781394U, // ADD8O |
| 1073775814U, // ADD8O_rec |
| 1073778168U, // ADD8TLS |
| 1073778168U, // ADD8TLS_ |
| 1073775111U, // ADD8_rec |
| 1073777938U, // ADDC |
| 1073777938U, // ADDC8 |
| 1073781379U, // ADDC8O |
| 1073775797U, // ADDC8O_rec |
| 1073775004U, // ADDC8_rec |
| 1073781379U, // ADDCO |
| 1073775797U, // ADDCO_rec |
| 1073775004U, // ADDC_rec |
| 1073778789U, // ADDE |
| 1073778789U, // ADDE8 |
| 1073781415U, // ADDE8O |
| 1073775838U, // ADDE8O_rec |
| 1073775257U, // ADDE8_rec |
| 1073781415U, // ADDEO |
| 1073775838U, // ADDEO_rec |
| 1073787527U, // ADDEX |
| 1073787527U, // ADDEX8 |
| 1073775257U, // ADDE_rec |
| 1073779599U, // ADDI |
| 1073779599U, // ADDI8 |
| 1073777983U, // ADDIC |
| 1073777983U, // ADDIC8 |
| 1073775045U, // ADDIC_rec |
| 1073785047U, // ADDIS |
| 1073785047U, // ADDIS8 |
| 16579U, // ADDISdtprelHA |
| 14575U, // ADDISdtprelHA32 |
| 16562U, // ADDISgotTprelHA |
| 16534U, // ADDIStlsgdHA |
| 16548U, // ADDIStlsldHA |
| 16522U, // ADDIStocHA |
| 16112U, // ADDIStocHA8 |
| 17109U, // ADDIdtprelL |
| 14864U, // ADDIdtprelL32 |
| 17072U, // ADDItlsgdL |
| 14821U, // ADDItlsgdL32 |
| 17213U, // ADDItlsgdLADDR |
| 14916U, // ADDItlsgdLADDR32 |
| 17084U, // ADDItlsldL |
| 14835U, // ADDItlsldL32 |
| 17229U, // ADDItlsldLADDR |
| 14934U, // ADDItlsldLADDR32 |
| 17660U, // ADDItoc |
| 16496U, // ADDItoc8 |
| 17053U, // ADDItocL |
| 37032U, // ADDME |
| 37032U, // ADDME8 |
| 39614U, // ADDME8O |
| 34040U, // ADDME8O_rec |
| 33465U, // ADDME8_rec |
| 39614U, // ADDMEO |
| 34040U, // ADDMEO_rec |
| 33465U, // ADDME_rec |
| 43214U, // ADDPCIS |
| 37099U, // ADDZE |
| 37099U, // ADDZE8 |
| 39639U, // ADDZE8O |
| 34068U, // ADDZE8O_rec |
| 33514U, // ADDZE8_rec |
| 39639U, // ADDZEO |
| 34068U, // ADDZEO_rec |
| 33514U, // ADDZE_rec |
| 100729U, // ADJCALLSTACKDOWN |
| 100748U, // ADJCALLSTACKUP |
| 1073778393U, // AND |
| 1073778393U, // AND8 |
| 1073775180U, // AND8_rec |
| 1073777947U, // ANDC |
| 1073777947U, // ANDC8 |
| 1073775011U, // ANDC8_rec |
| 1073775011U, // ANDC_rec |
| 1073775491U, // ANDI8_rec |
| 1073776350U, // ANDIS8_rec |
| 1073776350U, // ANDIS_rec |
| 1073775491U, // ANDI_rec |
| 17374U, // ANDI_rec_1_EQ_BIT |
| 16445U, // ANDI_rec_1_EQ_BIT8 |
| 17393U, // ANDI_rec_1_GT_BIT |
| 16465U, // ANDI_rec_1_GT_BIT8 |
| 1073775180U, // AND_rec |
| 2283833587U, // ATOMIC_CMP_SWAP_I16 |
| 2283833513U, // ATOMIC_CMP_SWAP_I32 |
| 15259U, // ATOMIC_CMP_SWAP_I64 |
| 16306U, // ATOMIC_CMP_SWAP_I8 |
| 15732U, // ATOMIC_LOAD_ADD_I16 |
| 14613U, // ATOMIC_LOAD_ADD_I32 |
| 15156U, // ATOMIC_LOAD_ADD_I64 |
| 16204U, // ATOMIC_LOAD_ADD_I8 |
| 15775U, // ATOMIC_LOAD_AND_I16 |
| 14656U, // ATOMIC_LOAD_AND_I32 |
| 15556U, // ATOMIC_LOAD_AND_I64 |
| 16245U, // ATOMIC_LOAD_AND_I8 |
| 15919U, // ATOMIC_LOAD_MAX_I16 |
| 14800U, // ATOMIC_LOAD_MAX_I32 |
| 15343U, // ATOMIC_LOAD_MAX_I64 |
| 16396U, // ATOMIC_LOAD_MAX_I8 |
| 15818U, // ATOMIC_LOAD_MIN_I16 |
| 14699U, // ATOMIC_LOAD_MIN_I32 |
| 15221U, // ATOMIC_LOAD_MIN_I64 |
| 16286U, // ATOMIC_LOAD_MIN_I8 |
| 15753U, // ATOMIC_LOAD_NAND_I16 |
| 14634U, // ATOMIC_LOAD_NAND_I32 |
| 15177U, // ATOMIC_LOAD_NAND_I64 |
| 16224U, // ATOMIC_LOAD_NAND_I8 |
| 15877U, // ATOMIC_LOAD_OR_I16 |
| 14758U, // ATOMIC_LOAD_OR_I32 |
| 15301U, // ATOMIC_LOAD_OR_I64 |
| 16345U, // ATOMIC_LOAD_OR_I8 |
| 15711U, // ATOMIC_LOAD_SUB_I16 |
| 14592U, // ATOMIC_LOAD_SUB_I32 |
| 15135U, // ATOMIC_LOAD_SUB_I64 |
| 16170U, // ATOMIC_LOAD_SUB_I8 |
| 15897U, // ATOMIC_LOAD_UMAX_I16 |
| 14778U, // ATOMIC_LOAD_UMAX_I32 |
| 15321U, // ATOMIC_LOAD_UMAX_I64 |
| 16375U, // ATOMIC_LOAD_UMAX_I8 |
| 15796U, // ATOMIC_LOAD_UMIN_I16 |
| 14677U, // ATOMIC_LOAD_UMIN_I32 |
| 15199U, // ATOMIC_LOAD_UMIN_I64 |
| 16265U, // ATOMIC_LOAD_UMIN_I8 |
| 15856U, // ATOMIC_LOAD_XOR_I16 |
| 14737U, // ATOMIC_LOAD_XOR_I32 |
| 15280U, // ATOMIC_LOAD_XOR_I64 |
| 16326U, // ATOMIC_LOAD_XOR_I8 |
| 15839U, // ATOMIC_SWAP_I16 |
| 14720U, // ATOMIC_SWAP_I32 |
| 15242U, // ATOMIC_SWAP_I64 |
| 16506U, // ATOMIC_SWAP_I8 |
| 17788U, // ATTN |
| 1182509U, // B |
| 1215014U, // BA |
| 167805047U, // BC |
| 3359948U, // BCC |
| 4408524U, // BCCA |
| 5457100U, // BCCCTR |
| 5457100U, // BCCCTR8 |
| 6505676U, // BCCCTRL |
| 6505676U, // BCCCTRL8 |
| 7554252U, // BCCL |
| 8602828U, // BCCLA |
| 9651404U, // BCCLR |
| 10699980U, // BCCLRL |
| 11567273U, // BCCTR |
| 11567273U, // BCCTR8 |
| 11567339U, // BCCTR8n |
| 11567251U, // BCCTRL |
| 11567251U, // BCCTRL8 |
| 11567319U, // BCCTRL8n |
| 11567319U, // BCCTRLn |
| 11567339U, // BCCTRn |
| 1073775108U, // BCDADD_rec |
| 1073775731U, // BCDCFN_rec |
| 1073776118U, // BCDCFSQ_rec |
| 1073776706U, // BCDCFZ_rec |
| 1073775740U, // BCDCPSGN_rec |
| 33964U, // BCDCTN_rec |
| 34304U, // BCDCTSQ_rec |
| 1073776722U, // BCDCTZ_rec |
| 1073775760U, // BCDSETSGN_rec |
| 1073776226U, // BCDSR_rec |
| 1073774949U, // BCDSUB_rec |
| 1073776282U, // BCDS_rec |
| 1073775061U, // BCDTRUNC_rec |
| 1073776375U, // BCDUS_rec |
| 1073775072U, // BCDUTRUNC_rec |
| 167805055U, // BCL |
| 11567263U, // BCLR |
| 11567240U, // BCLRL |
| 11567309U, // BCLRLn |
| 11567330U, // BCLRn |
| 1179725U, // BCLalways |
| 167805125U, // BCLn |
| 17869U, // BCTR |
| 17869U, // BCTR8 |
| 17782U, // BCTRL |
| 17782U, // BCTRL8 |
| 229466U, // BCTRL8_LDinto_toc |
| 229466U, // BCTRL8_LDinto_toc_RM |
| 17782U, // BCTRL8_RM |
| 229480U, // BCTRL_LWZinto_toc |
| 229480U, // BCTRL_LWZinto_toc_RM |
| 17782U, // BCTRL_RM |
| 167805118U, // BCn |
| 1193855U, // BDNZ |
| 1193855U, // BDNZ8 |
| 1215266U, // BDNZA |
| 1212697U, // BDNZAm |
| 1212457U, // BDNZAp |
| 1185555U, // BDNZL |
| 1215230U, // BDNZLA |
| 1212681U, // BDNZLAm |
| 1212441U, // BDNZLAp |
| 17862U, // BDNZLR |
| 17862U, // BDNZLR8 |
| 17774U, // BDNZLRL |
| 14369U, // BDNZLRLm |
| 14326U, // BDNZLRLp |
| 14385U, // BDNZLRm |
| 14342U, // BDNZLRp |
| 1179944U, // BDNZLm |
| 1179704U, // BDNZLp |
| 1179958U, // BDNZm |
| 1179718U, // BDNZp |
| 1193701U, // BDZ |
| 1193701U, // BDZ8 |
| 1215260U, // BDZA |
| 1212690U, // BDZAm |
| 1212450U, // BDZAp |
| 1185549U, // BDZL |
| 1215223U, // BDZLA |
| 1212673U, // BDZLAm |
| 1212433U, // BDZLAp |
| 17856U, // BDZLR |
| 17856U, // BDZLR8 |
| 17767U, // BDZLRL |
| 14361U, // BDZLRLm |
| 14318U, // BDZLRLp |
| 14378U, // BDZLRm |
| 14335U, // BDZLRp |
| 1179937U, // BDZLm |
| 1179697U, // BDZLp |
| 1179952U, // BDZm |
| 1179712U, // BDZp |
| 1185301U, // BL |
| 1185301U, // BL8 |
| 12719637U, // BL8_NOP |
| 12719637U, // BL8_NOP_RM |
| 12850709U, // BL8_NOP_TLS |
| 1185301U, // BL8_NOTOC |
| 1185301U, // BL8_NOTOC_RM |
| 1316373U, // BL8_NOTOC_TLS |
| 1185301U, // BL8_RM |
| 1316373U, // BL8_TLS |
| 1316373U, // BL8_TLS_ |
| 1215212U, // BLA |
| 1215212U, // BLA8 |
| 12749548U, // BLA8_NOP |
| 12749548U, // BLA8_NOP_RM |
| 1215212U, // BLA8_RM |
| 1215212U, // BLA_RM |
| 17852U, // BLR |
| 17852U, // BLR8 |
| 17762U, // BLRL |
| 12719637U, // BL_NOP |
| 12719637U, // BL_NOP_RM |
| 1185301U, // BL_RM |
| 1316373U, // BL_TLS |
| 1073778373U, // BPERMD |
| 36629U, // BRD |
| 37467U, // BRH |
| 37467U, // BRH8 |
| 1073778039U, // BRINC |
| 45052U, // BRW |
| 45052U, // BRW8 |
| 1073778236U, // CFUGED |
| 17606U, // CLRBHRB |
| 1073777571U, // CMPB |
| 1073777571U, // CMPB8 |
| 1073778445U, // CMPD |
| 1073779641U, // CMPDI |
| 1073777577U, // CMPEQB |
| 1073778344U, // CMPLD |
| 1073779605U, // CMPLDI |
| 1073786611U, // CMPLW |
| 1073780108U, // CMPLWI |
| 1275104177U, // CMPRB |
| 1275104177U, // CMPRB8 |
| 1073786868U, // CMPW |
| 1073780158U, // CMPWI |
| 36925U, // CNTLZD |
| 1073780668U, // CNTLZDM |
| 33415U, // CNTLZD_rec |
| 45439U, // CNTLZW |
| 45439U, // CNTLZW8 |
| 34807U, // CNTLZW8_rec |
| 34807U, // CNTLZW_rec |
| 36940U, // CNTTZD |
| 1073780685U, // CNTTZDM |
| 33424U, // CNTTZD_rec |
| 45454U, // CNTTZW |
| 45454U, // CNTTZW8 |
| 34816U, // CNTTZW8_rec |
| 34816U, // CNTTZW_rec |
| 17874U, // CP_ABORT |
| 46792U, // CP_COPY |
| 46792U, // CP_COPY8 |
| 1073775322U, // CP_PASTE8_rec |
| 1073775322U, // CP_PASTE_rec |
| 15670U, // CR6SET |
| 15656U, // CR6UNSET |
| 1073778423U, // CRAND |
| 1073777953U, // CRANDC |
| 1073786057U, // CREQV |
| 1073778407U, // CRNAND |
| 1073784462U, // CRNOR |
| 43845U, // CRNOT |
| 1073784476U, // CROR |
| 1073778060U, // CRORC |
| 1308667081U, // CRSET |
| 1308665537U, // CRUNSET |
| 1073784513U, // CRXOR |
| 3359948U, // CTRL_DEP |
| 268474986U, // DARN |
| 1116708U, // DCBA |
| 13930746U, // DCBF |
| 1122040U, // DCBFEP |
| 1119063U, // DCBI |
| 1125238U, // DCBST |
| 1122073U, // DCBSTEP |
| 14985893U, // DCBT |
| 335633U, // DCBTEP |
| 14986122U, // DCBTST |
| 335650U, // DCBTSTEP |
| 1128142U, // DCBZ |
| 1122092U, // DCBZEP |
| 1120006U, // DCBZL |
| 1122056U, // DCBZLEP |
| 37753U, // DCCCI |
| 1073778736U, // DIVD |
| 1073778795U, // DIVDE |
| 1073781422U, // DIVDEO |
| 1073775846U, // DIVDEO_rec |
| 1073785859U, // DIVDEU |
| 1073781661U, // DIVDEUO |
| 1073775935U, // DIVDEUO_rec |
| 1073776462U, // DIVDEU_rec |
| 1073775264U, // DIVDE_rec |
| 1073781408U, // DIVDO |
| 1073775830U, // DIVDO_rec |
| 1073785852U, // DIVDU |
| 1073781653U, // DIVDUO |
| 1073775926U, // DIVDUO_rec |
| 1073776454U, // DIVDU_rec |
| 1073775232U, // DIVD_rec |
| 1073787238U, // DIVW |
| 1073778907U, // DIVWE |
| 1073781455U, // DIVWEO |
| 1073775883U, // DIVWEO_rec |
| 1073785867U, // DIVWEU |
| 1073781670U, // DIVWEUO |
| 1073775945U, // DIVWEUO_rec |
| 1073776471U, // DIVWEU_rec |
| 1073775330U, // DIVWE_rec |
| 1073781695U, // DIVWO |
| 1073775973U, // DIVWO_rec |
| 1073785971U, // DIVWU |
| 1073781679U, // DIVWUO |
| 1073775955U, // DIVWUO_rec |
| 1073776498U, // DIVWU_rec |
| 1073776613U, // DIVW_rec |
| 42586U, // DMMR |
| 1095579U, // DMSETDMRZ |
| 302032560U, // DMXOR |
| 1308985638U, // DMXXEXTFDMR256 |
| 11929753U, // DMXXEXTFDMR512 |
| 16124057U, // DMXXEXTFDMR512_HI |
| 1073776917U, // DMXXINSTFDMR256 |
| 1073776776U, // DMXXINSTFDMR512 |
| 1073776776U, // DMXXINSTFDMR512_HI |
| 1485088U, // DSS |
| 17755U, // DSSALL |
| 1376103293U, // DST |
| 1376103293U, // DST64 |
| 1376103314U, // DSTST |
| 1376103314U, // DSTST64 |
| 1376103343U, // DSTSTT |
| 1376103343U, // DSTSTT64 |
| 1376103328U, // DSTT |
| 1376103328U, // DSTT64 |
| 16678U, // DYNALLOC |
| 16125U, // DYNALLOC8 |
| 17331U, // DYNAREAOFFSET |
| 16429U, // DYNAREAOFFSET8 |
| 17812U, // DecreaseCTR8loop |
| 17830U, // DecreaseCTRloop |
| 42784U, // EFDABS |
| 1073778165U, // EFDADD |
| 43075U, // EFDCFS |
| 37194U, // EFDCFSF |
| 38146U, // EFDCFSI |
| 36470U, // EFDCFSID |
| 37296U, // EFDCFUF |
| 38212U, // EFDCFUI |
| 36487U, // EFDCFUID |
| 1073783944U, // EFDCMPEQ |
| 1073785539U, // EFDCMPGT |
| 1073785607U, // EFDCMPLT |
| 37268U, // EFDCTSF |
| 38174U, // EFDCTSI |
| 46826U, // EFDCTSIDZ |
| 46924U, // EFDCTSIZ |
| 37324U, // EFDCTUF |
| 38240U, // EFDCTUI |
| 46845U, // EFDCTUIDZ |
| 46955U, // EFDCTUIZ |
| 1073786005U, // EFDDIV |
| 1073780429U, // EFDMUL |
| 42798U, // EFDNABS |
| 37350U, // EFDNEG |
| 1073777794U, // EFDSUB |
| 1073783984U, // EFDTSTEQ |
| 1073785570U, // EFDTSTGT |
| 1073785638U, // EFDTSTLT |
| 42833U, // EFSABS |
| 1073778194U, // EFSADD |
| 36420U, // EFSCFD |
| 37203U, // EFSCFSF |
| 38155U, // EFSCFSI |
| 37305U, // EFSCFUF |
| 38221U, // EFSCFUI |
| 1073783954U, // EFSCMPEQ |
| 1073785549U, // EFSCMPGT |
| 1073785617U, // EFSCMPLT |
| 37277U, // EFSCTSF |
| 38183U, // EFSCTSI |
| 46934U, // EFSCTSIZ |
| 37333U, // EFSCTUF |
| 38249U, // EFSCTUI |
| 46965U, // EFSCTUIZ |
| 1073786019U, // EFSDIV |
| 1073780443U, // EFSMUL |
| 42814U, // EFSNABS |
| 37364U, // EFSNEG |
| 1073777823U, // EFSSUB |
| 1073783994U, // EFSTSTEQ |
| 1073785580U, // EFSTSTGT |
| 1073785648U, // EFSTSTLT |
| 14879U, // EH_SjLj_LongJmp32 |
| 15364U, // EH_SjLj_LongJmp64 |
| 14898U, // EH_SjLj_SetJmp32 |
| 15383U, // EH_SjLj_SetJmp64 |
| 1179649U, // EH_SjLj_Setup |
| 1073786052U, // EQV |
| 1073786052U, // EQV8 |
| 1073776513U, // EQV8_rec |
| 1073776513U, // EQV_rec |
| 42850U, // EVABS |
| 1107340993U, // EVADDIW |
| 44338U, // EVADDSMIAAW |
| 44470U, // EVADDSSIAAW |
| 44404U, // EVADDUMIAAW |
| 44536U, // EVADDUSIAAW |
| 1073786463U, // EVADDW |
| 1073778430U, // EVAND |
| 1073777961U, // EVANDC |
| 1073783975U, // EVCMPEQ |
| 1073785143U, // EVCMPGTS |
| 1073785919U, // EVCMPGTU |
| 1073785153U, // EVCMPLTS |
| 1073785929U, // EVCMPLTU |
| 45134U, // EVCNTLSW |
| 45437U, // EVCNTLZW |
| 1073785321U, // EVDIVWS |
| 1073785969U, // EVDIVWU |
| 1073786064U, // EVEQV |
| 35854U, // EVEXTSB |
| 37550U, // EVEXTSH |
| 42841U, // EVFSABS |
| 1073778202U, // EVFSADD |
| 37212U, // EVFSCFSF |
| 38164U, // EVFSCFSI |
| 37314U, // EVFSCFUF |
| 38230U, // EVFSCFUI |
| 1073783964U, // EVFSCMPEQ |
| 1073785559U, // EVFSCMPGT |
| 1073785627U, // EVFSCMPLT |
| 37286U, // EVFSCTSF |
| 38192U, // EVFSCTSI |
| 46944U, // EVFSCTSIZ |
| 37286U, // EVFSCTUF |
| 38258U, // EVFSCTUI |
| 46944U, // EVFSCTUIZ |
| 1073786027U, // EVFSDIV |
| 1073780451U, // EVFSMUL |
| 42823U, // EVFSNABS |
| 37372U, // EVFSNEG |
| 1073777831U, // EVFSSUB |
| 1073784004U, // EVFSTSTEQ |
| 1073785590U, // EVFSTSTGT |
| 1073785658U, // EVFSTSTLT |
| 67145251U, // EVLDD |
| 134263358U, // EVLDDX |
| 67146268U, // EVLDH |
| 134263467U, // EVLDHX |
| 67153511U, // EVLDW |
| 134264395U, // EVLDWX |
| 67152471U, // EVLHHESPLAT |
| 134264185U, // EVLHHESPLATX |
| 67152496U, // EVLHHOSSPLAT |
| 134264212U, // EVLHHOSSPLATX |
| 67152510U, // EVLHHOUSPLAT |
| 134264227U, // EVLHHOUSPLATX |
| 67145865U, // EVLWHE |
| 134263438U, // EVLWHEX |
| 67152130U, // EVLWHOS |
| 134264167U, // EVLWHOSX |
| 67152930U, // EVLWHOU |
| 134264318U, // EVLWHOUX |
| 67152484U, // EVLWHSPLAT |
| 134264199U, // EVLWHSPLATX |
| 67152524U, // EVLWWSPLAT |
| 134264242U, // EVLWWSPLATX |
| 1073779712U, // EVMERGEHI |
| 1073781513U, // EVMERGEHILO |
| 1073781502U, // EVMERGELO |
| 1073779723U, // EVMERGELOHI |
| 1073777066U, // EVMHEGSMFAA |
| 1073781042U, // EVMHEGSMFAN |
| 1073777114U, // EVMHEGSMIAA |
| 1073781090U, // EVMHEGSMIAN |
| 1073777151U, // EVMHEGUMIAA |
| 1073781127U, // EVMHEGUMIAN |
| 1073778950U, // EVMHESMF |
| 1073777199U, // EVMHESMFA |
| 1073786110U, // EVMHESMFAAW |
| 1073786652U, // EVMHESMFANW |
| 1073779807U, // EVMHESMI |
| 1073777291U, // EVMHESMIA |
| 1073786175U, // EVMHESMIAAW |
| 1073786704U, // EVMHESMIANW |
| 1073779053U, // EVMHESSF |
| 1073777242U, // EVMHESSFA |
| 1073786136U, // EVMHESSFAAW |
| 1073786678U, // EVMHESSFANW |
| 1073786307U, // EVMHESSIAAW |
| 1073786782U, // EVMHESSIANW |
| 1073779846U, // EVMHEUMI |
| 1073777334U, // EVMHEUMIA |
| 1073786241U, // EVMHEUMIAAW |
| 1073786743U, // EVMHEUMIANW |
| 1073786373U, // EVMHEUSIAAW |
| 1073786821U, // EVMHEUSIANW |
| 1073777079U, // EVMHOGSMFAA |
| 1073781055U, // EVMHOGSMFAN |
| 1073777127U, // EVMHOGSMIAA |
| 1073781103U, // EVMHOGSMIAN |
| 1073777164U, // EVMHOGUMIAA |
| 1073781140U, // EVMHOGUMIAN |
| 1073778970U, // EVMHOSMF |
| 1073777221U, // EVMHOSMFA |
| 1073786123U, // EVMHOSMFAAW |
| 1073786665U, // EVMHOSMFANW |
| 1073779827U, // EVMHOSMI |
| 1073777313U, // EVMHOSMIA |
| 1073786215U, // EVMHOSMIAAW |
| 1073786730U, // EVMHOSMIANW |
| 1073779073U, // EVMHOSSF |
| 1073777264U, // EVMHOSSFA |
| 1073786149U, // EVMHOSSFAAW |
| 1073786691U, // EVMHOSSFANW |
| 1073786347U, // EVMHOSSIAAW |
| 1073786808U, // EVMHOSSIANW |
| 1073779876U, // EVMHOUMI |
| 1073777367U, // EVMHOUMIA |
| 1073786281U, // EVMHOUMIAAW |
| 1073786769U, // EVMHOUMIANW |
| 1073786413U, // EVMHOUSIAAW |
| 1073786847U, // EVMHOUSIANW |
| 35590U, // EVMRA |
| 1073778960U, // EVMWHSMF |
| 1073777210U, // EVMWHSMFA |
| 1073779817U, // EVMWHSMI |
| 1073777302U, // EVMWHSMIA |
| 1073779063U, // EVMWHSSF |
| 1073777253U, // EVMWHSSFA |
| 1073779856U, // EVMWHUMI |
| 1073777345U, // EVMWHUMIA |
| 1073786202U, // EVMWLSMIAAW |
| 1073786717U, // EVMWLSMIANW |
| 1073786334U, // EVMWLSSIAAW |
| 1073786795U, // EVMWLSSIANW |
| 1073779866U, // EVMWLUMI |
| 1073777356U, // EVMWLUMIA |
| 1073786268U, // EVMWLUMIAAW |
| 1073786756U, // EVMWLUMIANW |
| 1073786400U, // EVMWLUSIAAW |
| 1073786834U, // EVMWLUSIANW |
| 1073778980U, // EVMWSMF |
| 1073777232U, // EVMWSMFA |
| 1073777092U, // EVMWSMFAA |
| 1073781068U, // EVMWSMFAN |
| 1073779837U, // EVMWSMI |
| 1073777324U, // EVMWSMIA |
| 1073777140U, // EVMWSMIAA |
| 1073781116U, // EVMWSMIAN |
| 1073779083U, // EVMWSSF |
| 1073777275U, // EVMWSSFA |
| 1073777103U, // EVMWSSFAA |
| 1073781079U, // EVMWSSFAN |
| 1073779886U, // EVMWUMI |
| 1073777378U, // EVMWUMIA |
| 1073777177U, // EVMWUMIAA |
| 1073781153U, // EVMWUMIAN |
| 1073778415U, // EVNAND |
| 37381U, // EVNEG |
| 1073784469U, // EVNOR |
| 1073784482U, // EVOR |
| 1073778067U, // EVORC |
| 1073786618U, // EVRLW |
| 1073780116U, // EVRLWI |
| 44654U, // EVRNDW |
| 3238049806U, // EVSEL |
| 1073786625U, // EVSLW |
| 1073780142U, // EVSLWI |
| 335582197U, // EVSPLATFI |
| 335582522U, // EVSPLATI |
| 1073785066U, // EVSRWIS |
| 1073785881U, // EVSRWIU |
| 1073785249U, // EVSRWS |
| 1073785955U, // EVSRWU |
| 67145267U, // EVSTDD |
| 134263366U, // EVSTDDX |
| 67146275U, // EVSTDH |
| 134263475U, // EVSTDHX |
| 67153526U, // EVSTDW |
| 134264403U, // EVSTDWX |
| 67145873U, // EVSTWHE |
| 134263447U, // EVSTWHEX |
| 67148533U, // EVSTWHO |
| 134263762U, // EVSTWHOX |
| 67145954U, // EVSTWWE |
| 134263457U, // EVSTWWEX |
| 67148742U, // EVSTWWO |
| 134263772U, // EVSTWWOX |
| 44364U, // EVSUBFSMIAAW |
| 44496U, // EVSUBFSSIAAW |
| 44430U, // EVSUBFUMIAAW |
| 44562U, // EVSUBFUSIAAW |
| 1073786511U, // EVSUBFW |
| 1442885272U, // EVSUBIFW |
| 1073784520U, // EVXOR |
| 35856U, // EXTSB |
| 35856U, // EXTSB8 |
| 35856U, // EXTSB8_32_64 |
| 33106U, // EXTSB8_rec |
| 33106U, // EXTSB_rec |
| 37552U, // EXTSH |
| 37552U, // EXTSH8 |
| 37552U, // EXTSH8_32_64 |
| 33574U, // EXTSH8_rec |
| 33574U, // EXTSH_rec |
| 45178U, // EXTSW |
| 1073779755U, // EXTSWSLI |
| 1073779755U, // EXTSWSLI_32_64 |
| 1073775543U, // EXTSWSLI_32_64_rec |
| 1073775543U, // EXTSWSLI_rec |
| 45178U, // EXTSW_32 |
| 45178U, // EXTSW_32_64 |
| 34759U, // EXTSW_32_64_rec |
| 34759U, // EXTSW_rec |
| 17793U, // EnforceIEIO |
| 42792U, // FABSD |
| 34416U, // FABSD_rec |
| 42792U, // FABSS |
| 34416U, // FABSS_rec |
| 1073778173U, // FADD |
| 1073784761U, // FADDS |
| 1073776289U, // FADDS_rec |
| 1073775117U, // FADD_rec |
| 0U, // FADDrtz |
| 36463U, // FCFID |
| 42961U, // FCFIDS |
| 34492U, // FCFIDS_rec |
| 44001U, // FCFIDU |
| 43347U, // FCFIDUS |
| 34559U, // FCFIDUS_rec |
| 34612U, // FCFIDU_rec |
| 33325U, // FCFID_rec |
| 1073781543U, // FCMPOD |
| 1073781543U, // FCMPOS |
| 1073785899U, // FCMPUD |
| 1073785899U, // FCMPUS |
| 1073781164U, // FCPSGND |
| 1073775751U, // FCPSGND_rec |
| 1073781164U, // FCPSGNS |
| 1073775751U, // FCPSGNS_rec |
| 36480U, // FCTID |
| 44009U, // FCTIDU |
| 47014U, // FCTIDUZ |
| 34907U, // FCTIDUZ_rec |
| 34621U, // FCTIDU_rec |
| 46837U, // FCTIDZ |
| 34873U, // FCTIDZ_rec |
| 33333U, // FCTID_rec |
| 44746U, // FCTIW |
| 44123U, // FCTIWU |
| 47023U, // FCTIWUZ |
| 34917U, // FCTIWUZ_rec |
| 34665U, // FCTIWU_rec |
| 47032U, // FCTIWZ |
| 34927U, // FCTIWZ_rec |
| 34720U, // FCTIW_rec |
| 1073786013U, // FDIV |
| 1073785242U, // FDIVS |
| 1073776402U, // FDIVS_rec |
| 1073776506U, // FDIV_rec |
| 1073778179U, // FMADD |
| 1073784768U, // FMADDS |
| 1073776297U, // FMADDS_rec |
| 1073775124U, // FMADD_rec |
| 42581U, // FMR |
| 34384U, // FMR_rec |
| 1073777808U, // FMSUB |
| 1073784744U, // FMSUBS |
| 1073776263U, // FMSUBS_rec |
| 1073774965U, // FMSUB_rec |
| 1073780437U, // FMUL |
| 1073785083U, // FMULS |
| 1073776358U, // FMULS_rec |
| 1073775689U, // FMUL_rec |
| 42807U, // FNABSD |
| 34423U, // FNABSD_rec |
| 42807U, // FNABSS |
| 34423U, // FNABSS_rec |
| 37358U, // FNEGD |
| 33546U, // FNEGD_rec |
| 37358U, // FNEGS |
| 33546U, // FNEGS_rec |
| 1073778186U, // FNMADD |
| 1073784776U, // FNMADDS |
| 1073776306U, // FNMADDS_rec |
| 1073775132U, // FNMADD_rec |
| 1073777815U, // FNMSUB |
| 1073784752U, // FNMSUBS |
| 1073776272U, // FNMSUBS_rec |
| 1073774973U, // FNMSUB_rec |
| 37054U, // FRE |
| 43059U, // FRES |
| 34501U, // FRES_rec |
| 33482U, // FRE_rec |
| 38997U, // FRIMD |
| 33883U, // FRIMD_rec |
| 38997U, // FRIMS |
| 33883U, // FRIMS_rec |
| 39355U, // FRIND |
| 33957U, // FRIND_rec |
| 39355U, // FRINS |
| 33957U, // FRINS_rec |
| 40937U, // FRIPD |
| 34236U, // FRIPD_rec |
| 40937U, // FRIPS |
| 34236U, // FRIPS_rec |
| 46918U, // FRIZD |
| 34891U, // FRIZD_rec |
| 46918U, // FRIZS |
| 34891U, // FRIZS_rec |
| 41911U, // FRSP |
| 34267U, // FRSP_rec |
| 37067U, // FRSQRTE |
| 43065U, // FRSQRTES |
| 34508U, // FRSQRTES_rec |
| 33488U, // FRSQRTE_rec |
| 1073780277U, // FSELD |
| 1073775672U, // FSELD_rec |
| 1073780277U, // FSELS |
| 1073775672U, // FSELS_rec |
| 43852U, // FSQRT |
| 43339U, // FSQRTS |
| 34542U, // FSQRTS_rec |
| 34595U, // FSQRT_rec |
| 1073777802U, // FSUB |
| 1073784737U, // FSUBS |
| 1073776255U, // FSUBS_rec |
| 1073774958U, // FSUB_rec |
| 1073786036U, // FTDIV |
| 43859U, // FTSQRT |
| 17259U, // GETtlsADDR |
| 14967U, // GETtlsADDR32 |
| 17513U, // GETtlsADDR32AIX |
| 17529U, // GETtlsADDR64AIX |
| 17028U, // GETtlsADDRPCREL |
| 17245U, // GETtlsldADDR |
| 14952U, // GETtlsldADDR32 |
| 17009U, // GETtlsldADDRPCREL |
| 402691583U, // HASHCHK |
| 402691583U, // HASHCHK8 |
| 402694127U, // HASHCHKP |
| 402694127U, // HASHCHKP8 |
| 402697090U, // HASHST |
| 402697090U, // HASHST8 |
| 402695245U, // HASHSTP |
| 402695245U, // HASHSTP8 |
| 17677U, // HRFID |
| 1119069U, // ICBI |
| 1122048U, // ICBIEP |
| 462192U, // ICBLC |
| 460270U, // ICBLQ |
| 469675U, // ICBT |
| 469235U, // ICBTLS |
| 37760U, // ICCCI |
| 1073780283U, // ISEL |
| 1073780283U, // ISEL8 |
| 17641U, // ISYNC |
| 436243181U, // LA |
| 436243181U, // LA8 |
| 134263901U, // LBARX |
| 134263901U, // LBARXL |
| 134263782U, // LBEPX |
| 67155669U, // LBZ |
| 67155669U, // LBZ8 |
| 1073787666U, // LBZCIX |
| 469806202U, // LBZU |
| 469806202U, // LBZU8 |
| 503363102U, // LBZUX |
| 503363102U, // LBZUX8 |
| 134264476U, // LBZX |
| 134264476U, // LBZX8 |
| 1073788572U, // LBZXTLS |
| 1073788572U, // LBZXTLS_ |
| 1073788572U, // LBZXTLS_32 |
| 67145364U, // LD |
| 134263908U, // LDARX |
| 134263908U, // LDARXL |
| 1073785418U, // LDAT |
| 134263936U, // LDBRX |
| 1073787635U, // LDCIX |
| 469806065U, // LDU |
| 503363043U, // LDUX |
| 134263388U, // LDX |
| 1073787484U, // LDXTLS |
| 1073787484U, // LDXTLS_ |
| 17096U, // LDgotTprelL |
| 14849U, // LDgotTprelL32 |
| 17653U, // LDtoc |
| 17435U, // LDtocBA |
| 17435U, // LDtocCPT |
| 16989U, // LDtocJTI |
| 17045U, // LDtocL |
| 67145293U, // LFD |
| 134263797U, // LFDEPX |
| 469806019U, // LFDU |
| 503363028U, // LFDUX |
| 134263375U, // LFDX |
| 134263275U, // LFIWAX |
| 134264497U, // LFIWZX |
| 67151954U, // LFS |
| 469806130U, // LFSU |
| 503363080U, // LFSUX |
| 134264154U, // LFSX |
| 67144326U, // LHA |
| 67144326U, // LHA8 |
| 134263915U, // LHARX |
| 134263915U, // LHARXL |
| 469806007U, // LHAU |
| 469806007U, // LHAU8 |
| 503363007U, // LHAUX |
| 503363007U, // LHAUX8 |
| 134263260U, // LHAX |
| 134263260U, // LHAX8 |
| 134263951U, // LHBRX |
| 134263951U, // LHBRX8 |
| 134263814U, // LHEPX |
| 67155743U, // LHZ |
| 67155743U, // LHZ8 |
| 1073787674U, // LHZCIX |
| 469806208U, // LHZU |
| 469806208U, // LHZU8 |
| 503363109U, // LHZUX |
| 503363109U, // LHZUX8 |
| 134264491U, // LHZX |
| 134264491U, // LHZX8 |
| 1073788587U, // LHZXTLS |
| 1073788587U, // LHZXTLS_ |
| 1073788587U, // LHZXTLS_32 |
| 100701211U, // LI |
| 100701211U, // LI8 |
| 100706526U, // LIS |
| 100706526U, // LIS8 |
| 67153672U, // LMW |
| 67151064U, // LQ |
| 134263922U, // LQARX |
| 134263922U, // LQARXL |
| 17130U, // LQX_PSEUDO |
| 1073780197U, // LSWI |
| 134263298U, // LVEBX |
| 134263484U, // LVEHX |
| 134264412U, // LVEWX |
| 134256327U, // LVSL |
| 134260471U, // LVSR |
| 134264371U, // LVX |
| 134256377U, // LVXL |
| 67144462U, // LWA |
| 134263929U, // LWARX |
| 134263929U, // LWARXL |
| 1073785496U, // LWAT |
| 503363014U, // LWAUX |
| 134263292U, // LWAX |
| 134263292U, // LWAX_32 |
| 67144462U, // LWA_32 |
| 134263985U, // LWBRX |
| 134263985U, // LWBRX8 |
| 134263829U, // LWEPX |
| 67155905U, // LWZ |
| 67155905U, // LWZ8 |
| 1073787682U, // LWZCIX |
| 469806214U, // LWZU |
| 469806214U, // LWZU8 |
| 503363116U, // LWZUX |
| 503363116U, // LWZUX8 |
| 134264514U, // LWZX |
| 134264514U, // LWZX8 |
| 1073788610U, // LWZXTLS |
| 1073788610U, // LWZXTLS_ |
| 1073788610U, // LWZXTLS_32 |
| 17669U, // LWZtoc |
| 17063U, // LWZtocL |
| 67145608U, // LXSD |
| 134263410U, // LXSDX |
| 134264467U, // LXSIBZX |
| 134264482U, // LXSIHZX |
| 134263283U, // LXSIWAX |
| 134264505U, // LXSIWZX |
| 67150808U, // LXSSP |
| 134263869U, // LXSSPX |
| 67153118U, // LXV |
| 134263224U, // LXVB16X |
| 134263190U, // LXVD2X |
| 134264139U, // LXVDSX |
| 134263243U, // LXVH8X |
| 369140943U, // LXVKQ |
| 1073780460U, // LXVL |
| 1073780354U, // LXVLL |
| 67150935U, // LXVP |
| 1073780376U, // LXVPRL |
| 1073780318U, // LXVPRLL |
| 134263886U, // LXVPX |
| 134263322U, // LXVRBX |
| 134263393U, // LXVRDX |
| 134263508U, // LXVRHX |
| 1073780401U, // LXVRL |
| 1073780337U, // LXVRLL |
| 134264444U, // LXVRWX |
| 134263207U, // LXVW4X |
| 134264177U, // LXVWSX |
| 134264382U, // LXVX |
| 1073778272U, // MADDHD |
| 1073785808U, // MADDHDU |
| 1073778328U, // MADDLD |
| 1073778328U, // MADDLD8 |
| 1484220U, // MBAR |
| 37165U, // MCRF |
| 43095U, // MCRFS |
| 1094972U, // MCRXRX |
| 536907860U, // MFBHRBE |
| 1091057U, // MFCR |
| 1091057U, // MFCR8 |
| 1091332U, // MFCTR |
| 1091332U, // MFCTR8 |
| 42460U, // MFDCR |
| 1091659U, // MFFS |
| 39545U, // MFFSCDRN |
| 570463433U, // MFFSCDRNI |
| 1085533U, // MFFSCE |
| 39536U, // MFFSCRN |
| 268473535U, // MFFSCRNI |
| 1087168U, // MFFSL |
| 1083095U, // MFFS_rec |
| 1091145U, // MFLR |
| 1091145U, // MFLR8 |
| 1091299U, // MFMSR |
| 604016947U, // MFOCRF |
| 604016947U, // MFOCRF8 |
| 42592U, // MFPMR |
| 42703U, // MFSPR |
| 42703U, // MFSPR8 |
| 637576925U, // MFSR |
| 39361U, // MFSRIN |
| 35877U, // MFTB |
| 17868495U, // MFTB8 |
| 18917071U, // MFUDSCR |
| 36642U, // MFVRD |
| 19965647U, // MFVRSAVE |
| 19965647U, // MFVRSAVEv |
| 47046U, // MFVRWZ |
| 1091071U, // MFVSCR |
| 36642U, // MFVSRD |
| 36527U, // MFVSRLD |
| 47046U, // MFVSRWZ |
| 1073778483U, // MODSD |
| 1073786888U, // MODSW |
| 1073778638U, // MODUD |
| 1073787098U, // MODUW |
| 17633U, // MSGSYNC |
| 17647U, // MSYNC |
| 37187U, // MTCRF |
| 37187U, // MTCRF8 |
| 1091339U, // MTCTR |
| 1091339U, // MTCTR8 |
| 1091339U, // MTCTR8loop |
| 1091339U, // MTCTRloop |
| 235251178U, // MTDCR |
| 1476728U, // MTFSB0 |
| 1476736U, // MTFSB1 |
| 1073779046U, // MTFSF |
| 302486509U, // MTFSFI |
| 671581102U, // MTFSFI_rec |
| 1545197U, // MTFSFIb |
| 1073775362U, // MTFSF_rec |
| 37222U, // MTFSFb |
| 1091151U, // MTLR |
| 1091151U, // MTLR8 |
| 201369322U, // MTMSR |
| 201363226U, // MTMSRD |
| 528699U, // MTOCRF |
| 528699U, // MTOCRF8 |
| 42599U, // MTPMR |
| 42710U, // MTSPR |
| 42710U, // MTSPR8 |
| 567025U, // MTSR |
| 39369U, // MTSRIN |
| 1081524U, // MTUDSCR |
| 36650U, // MTVRD |
| 1081589U, // MTVRSAVE |
| 1409269U, // MTVRSAVEv |
| 35603U, // MTVRWA |
| 47055U, // MTVRWZ |
| 1091079U, // MTVSCR |
| 38703U, // MTVSRBM |
| 704681013U, // MTVSRBMI |
| 36650U, // MTVSRD |
| 1073778218U, // MTVSRDD |
| 38775U, // MTVSRDM |
| 38881U, // MTVSRHM |
| 39046U, // MTVSRQM |
| 35603U, // MTVSRWA |
| 39158U, // MTVSRWM |
| 43433U, // MTVSRWS |
| 47055U, // MTVSRWZ |
| 1073778280U, // MULHD |
| 1073785817U, // MULHDU |
| 1073776427U, // MULHDU_rec |
| 1073775141U, // MULHD_rec |
| 1073786554U, // MULHW |
| 1073785939U, // MULHWU |
| 1073776480U, // MULHWU_rec |
| 1073776536U, // MULHW_rec |
| 1073778337U, // MULLD |
| 1073781400U, // MULLDO |
| 1073775821U, // MULLDO_rec |
| 1073775165U, // MULLD_rec |
| 1073779743U, // MULLI |
| 1073779743U, // MULLI8 |
| 1073786604U, // MULLW |
| 1073781687U, // MULLWO |
| 1073775964U, // MULLWO_rec |
| 1073776552U, // MULLW_rec |
| 17294U, // MoveGOTtoLR |
| 17282U, // MovePCtoLR |
| 16416U, // MovePCtoLR8 |
| 1073778401U, // NAND |
| 1073778401U, // NAND8 |
| 1073775179U, // NAND8_rec |
| 1073775179U, // NAND_rec |
| 17799U, // NAP |
| 37353U, // NEG |
| 37353U, // NEG8 |
| 39663U, // NEG8O |
| 34095U, // NEG8O_rec |
| 33547U, // NEG8_rec |
| 39663U, // NEGO |
| 34095U, // NEGO_rec |
| 33547U, // NEG_rec |
| 17808U, // NOP |
| 14551U, // NOP_GT_PWR6 |
| 14563U, // NOP_GT_PWR7 |
| 1073784457U, // NOR |
| 1073784457U, // NOR8 |
| 1073776214U, // NOR8_rec |
| 1073776214U, // NOR_rec |
| 1073784450U, // OR |
| 1073784450U, // OR8 |
| 1073776215U, // OR8_rec |
| 1073778055U, // ORC |
| 1073778055U, // ORC8 |
| 1073775084U, // ORC8_rec |
| 1073775084U, // ORC_rec |
| 1073779965U, // ORI |
| 1073779965U, // ORI8 |
| 1073785060U, // ORIS |
| 1073785060U, // ORIS8 |
| 1073776215U, // OR_rec |
| 1073779598U, // PADDI |
| 1073779598U, // PADDI8 |
| 738235278U, // PADDI8pc |
| 17728U, // PADDIdtprel |
| 738235278U, // PADDIpc |
| 1073778438U, // PDEPD |
| 1073778620U, // PEXTD |
| 771798740U, // PLBZ |
| 771798740U, // PLBZ8 |
| 805353172U, // PLBZ8pc |
| 805353172U, // PLBZpc |
| 771788458U, // PLD |
| 805342890U, // PLDpc |
| 771788364U, // PLFD |
| 805342796U, // PLFDpc |
| 771795025U, // PLFS |
| 805349457U, // PLFSpc |
| 771787397U, // PLHA |
| 771787397U, // PLHA8 |
| 805341829U, // PLHA8pc |
| 805341829U, // PLHApc |
| 771798814U, // PLHZ |
| 771798814U, // PLHZ8 |
| 805353246U, // PLHZ8pc |
| 805353246U, // PLHZpc |
| 838898726U, // PLI |
| 838898726U, // PLI8 |
| 771787533U, // PLWA |
| 771787533U, // PLWA8 |
| 805341965U, // PLWA8pc |
| 805341965U, // PLWApc |
| 771798976U, // PLWZ |
| 771798976U, // PLWZ8 |
| 805353408U, // PLWZ8pc |
| 805353408U, // PLWZpc |
| 771788679U, // PLXSD |
| 805343111U, // PLXSDpc |
| 771793879U, // PLXSSP |
| 805348311U, // PLXSSPpc |
| 771796189U, // PLXV |
| 771794006U, // PLXVP |
| 805348438U, // PLXVPpc |
| 805350621U, // PLXVpc |
| 1073776831U, // PMXVBF16GER2 |
| 1375771089U, // PMXVBF16GER2NN |
| 1375772673U, // PMXVBF16GER2NP |
| 1375771148U, // PMXVBF16GER2PN |
| 1375772732U, // PMXVBF16GER2PP |
| 1073776831U, // PMXVBF16GER2W |
| 1375771089U, // PMXVBF16GER2WNN |
| 1375772673U, // PMXVBF16GER2WNP |
| 1375771148U, // PMXVBF16GER2WPN |
| 1375772732U, // PMXVBF16GER2WPP |
| 1073776845U, // PMXVF16GER2 |
| 1375771105U, // PMXVF16GER2NN |
| 1375772689U, // PMXVF16GER2NP |
| 1375771164U, // PMXVF16GER2PN |
| 1375772748U, // PMXVF16GER2PP |
| 1073776845U, // PMXVF16GER2W |
| 1375771105U, // PMXVF16GER2WNN |
| 1375772689U, // PMXVF16GER2WNP |
| 1375771164U, // PMXVF16GER2WPN |
| 1375772748U, // PMXVF16GER2WPP |
| 1073784335U, // PMXVF32GER |
| 1375771120U, // PMXVF32GERNN |
| 1375772704U, // PMXVF32GERNP |
| 1375771190U, // PMXVF32GERPN |
| 1375772806U, // PMXVF32GERPP |
| 1073784335U, // PMXVF32GERW |
| 1375771120U, // PMXVF32GERWNN |
| 1375772704U, // PMXVF32GERWNP |
| 1375771190U, // PMXVF32GERWPN |
| 1375772806U, // PMXVF32GERWPP |
| 1073784347U, // PMXVF64GER |
| 1375771134U, // PMXVF64GERNN |
| 1375772718U, // PMXVF64GERNP |
| 1375771204U, // PMXVF64GERPN |
| 1375772820U, // PMXVF64GERPP |
| 1073784347U, // PMXVF64GERW |
| 1375771134U, // PMXVF64GERWNN |
| 1375772718U, // PMXVF64GERWNP |
| 1375771204U, // PMXVF64GERWPN |
| 1375772820U, // PMXVF64GERWPP |
| 1073776858U, // PMXVI16GER2 |
| 1375772763U, // PMXVI16GER2PP |
| 1073784594U, // PMXVI16GER2S |
| 1375772834U, // PMXVI16GER2SPP |
| 1073784594U, // PMXVI16GER2SW |
| 1375772834U, // PMXVI16GER2SWPP |
| 1073776858U, // PMXVI16GER2W |
| 1375772763U, // PMXVI16GER2WPP |
| 1073776992U, // PMXVI4GER8 |
| 1375772792U, // PMXVI4GER8PP |
| 1073776992U, // PMXVI4GER8W |
| 1375772792U, // PMXVI4GER8WPP |
| 1073776871U, // PMXVI8GER4 |
| 1375772778U, // PMXVI8GER4PP |
| 1375772850U, // PMXVI8GER4SPP |
| 1073776871U, // PMXVI8GER4W |
| 1375772778U, // PMXVI8GER4WPP |
| 1375772850U, // PMXVI8GER4WSPP |
| 35892U, // POPCNTB |
| 35892U, // POPCNTB8 |
| 36770U, // POPCNTD |
| 45219U, // POPCNTW |
| 17412U, // PPC32GOT |
| 17422U, // PPC32PICGOT |
| 14998U, // PREPARE_PROBED_ALLOCA_32 |
| 15419U, // PREPARE_PROBED_ALLOCA_64 |
| 15046U, // PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_32 |
| 15467U, // PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_64 |
| 14980U, // PROBED_ALLOCA_32 |
| 15401U, // PROBED_ALLOCA_64 |
| 15024U, // PROBED_STACKALLOC_32 |
| 15445U, // PROBED_STACKALLOC_64 |
| 771787847U, // PSTB |
| 771787847U, // PSTB8 |
| 805342279U, // PSTB8pc |
| 805342279U, // PSTBpc |
| 771788725U, // PSTD |
| 805343157U, // PSTDpc |
| 771788370U, // PSTFD |
| 805342802U, // PSTFDpc |
| 771795038U, // PSTFS |
| 805349470U, // PSTFSpc |
| 771789531U, // PSTH |
| 771789531U, // PSTH8 |
| 805343963U, // PSTH8pc |
| 805343963U, // PSTHpc |
| 771797185U, // PSTW |
| 771797185U, // PSTW8 |
| 805351617U, // PSTW8pc |
| 805351617U, // PSTWpc |
| 771788686U, // PSTXSD |
| 805343118U, // PSTXSDpc |
| 771793887U, // PSTXSSP |
| 805348319U, // PSTXSSPpc |
| 771796195U, // PSTXV |
| 771794013U, // PSTXVP |
| 805348445U, // PSTXVPpc |
| 805350627U, // PSTXVpc |
| 17155U, // PseudoEIEIO |
| 16654U, // RESTORE_ACC |
| 17191U, // RESTORE_CR |
| 17346U, // RESTORE_CRBIT |
| 16860U, // RESTORE_QUADWORD |
| 16602U, // RESTORE_UACC |
| 16628U, // RESTORE_WACC |
| 17704U, // RFCI |
| 17715U, // RFDI |
| 592688U, // RFEBB |
| 17720U, // RFI |
| 17678U, // RFID |
| 17709U, // RFMCI |
| 1073780254U, // RLDCL |
| 1073775655U, // RLDCL_rec |
| 1073784291U, // RLDCR |
| 1073776181U, // RLDCR_rec |
| 1073777990U, // RLDIC |
| 1073780261U, // RLDICL |
| 1073780261U, // RLDICL_32 |
| 1073780261U, // RLDICL_32_64 |
| 1073775663U, // RLDICL_32_rec |
| 1073775663U, // RLDICL_rec |
| 1073784311U, // RLDICR |
| 1073784311U, // RLDICR_32 |
| 1073776189U, // RLDICR_rec |
| 1073775053U, // RLDIC_rec |
| 1375769671U, // RLDIMI |
| 1375765442U, // RLDIMI_rec |
| 1375769679U, // RLWIMI |
| 1375769679U, // RLWIMI8 |
| 1375765451U, // RLWIMI8_rec |
| 1375765451U, // RLWIMI_rec |
| 1073780835U, // RLWINM |
| 1073780835U, // RLWINM8 |
| 1073775714U, // RLWINM8_rec |
| 1073775714U, // RLWINM_rec |
| 1073780852U, // RLWNM |
| 1073780852U, // RLWNM8 |
| 1073775723U, // RLWNM8_rec |
| 1073775723U, // RLWNM_rec |
| 16594U, // ReadTB |
| 1084826U, // SC |
| 15684U, // SELECT_CC_F16 |
| 15606U, // SELECT_CC_F4 |
| 16145U, // SELECT_CC_F8 |
| 15631U, // SELECT_CC_I4 |
| 16190U, // SELECT_CC_I8 |
| 16930U, // SELECT_CC_SPE |
| 15577U, // SELECT_CC_SPE4 |
| 16719U, // SELECT_CC_VRRC |
| 16688U, // SELECT_CC_VSFRC |
| 16779U, // SELECT_CC_VSRC |
| 16748U, // SELECT_CC_VSSRC |
| 15699U, // SELECT_F16 |
| 15620U, // SELECT_F4 |
| 16159U, // SELECT_F8 |
| 15645U, // SELECT_I4 |
| 16364U, // SELECT_I8 |
| 16945U, // SELECT_SPE |
| 15593U, // SELECT_SPE4 |
| 16735U, // SELECT_VRRC |
| 16705U, // SELECT_VSFRC |
| 16795U, // SELECT_VSRC |
| 16765U, // SELECT_VSSRC |
| 35871U, // SETB |
| 35871U, // SETB8 |
| 36089U, // SETBC |
| 36089U, // SETBC8 |
| 42452U, // SETBCR |
| 42452U, // SETBCR8 |
| 17122U, // SETFLM |
| 36081U, // SETNBC |
| 36081U, // SETNBC8 |
| 42443U, // SETNBCR |
| 42443U, // SETNBCR8 |
| 16836U, // SETRND |
| 17695U, // SETRNDi |
| 33448U, // SLBFEE_rec |
| 17589U, // SLBIA |
| 1085594U, // SLBIE |
| 37342U, // SLBIEG |
| 36978U, // SLBMFEE |
| 44172U, // SLBMFEV |
| 37059U, // SLBMTE |
| 17617U, // SLBSYNC |
| 1073778367U, // SLD |
| 1073775173U, // SLD_rec |
| 1073786627U, // SLW |
| 1073786627U, // SLW8 |
| 1073776560U, // SLW8_rec |
| 1073776560U, // SLW_rec |
| 67155905U, // SPELWZ |
| 134264514U, // SPELWZX |
| 67154114U, // SPESTW |
| 134264461U, // SPESTWX |
| 16667U, // SPILL_ACC |
| 17203U, // SPILL_CR |
| 17361U, // SPILL_CRBIT |
| 16878U, // SPILL_QUADWORD |
| 16616U, // SPILL_UACC |
| 16642U, // SPILL_WACC |
| 16894U, // SPLIT_QUADWORD |
| 1073778134U, // SRAD |
| 1073779591U, // SRADI |
| 1073779591U, // SRADI_32 |
| 1073775463U, // SRADI_rec |
| 1073775101U, // SRAD_rec |
| 1073786439U, // SRAW |
| 1073780092U, // SRAWI |
| 1073775572U, // SRAWI_rec |
| 1073776519U, // SRAW_rec |
| 1073778461U, // SRD |
| 1073775193U, // SRD_rec |
| 1073786882U, // SRW |
| 1073786882U, // SRW8 |
| 1073776566U, // SRW8_rec |
| 1073776566U, // SRW_rec |
| 67144776U, // STB |
| 67144776U, // STB8 |
| 1073787627U, // STBCIX |
| 134252553U, // STBCX |
| 134263789U, // STBEPX |
| 470133693U, // STBU |
| 470133693U, // STBU8 |
| 503690701U, // STBUX |
| 503690701U, // STBUX8 |
| 134263339U, // STBX |
| 134263339U, // STBX8 |
| 1073787435U, // STBXTLS |
| 1073787435U, // STBXTLS_ |
| 1073787435U, // STBXTLS_32 |
| 67145654U, // STD |
| 1073785424U, // STDAT |
| 134263943U, // STDBRX |
| 1073787642U, // STDCIX |
| 134252561U, // STDCX |
| 470133750U, // STDU |
| 503690729U, // STDUX |
| 134263425U, // STDX |
| 1073787521U, // STDXTLS |
| 1073787521U, // STDXTLS_ |
| 67145299U, // STFD |
| 134263805U, // STFDEPX |
| 470133705U, // STFDU |
| 503690715U, // STFDUX |
| 134263381U, // STFDX |
| 134264427U, // STFIWX |
| 67151967U, // STFS |
| 470133816U, // STFSU |
| 503690767U, // STFSUX |
| 134264160U, // STFSX |
| 67146460U, // STH |
| 67146460U, // STH8 |
| 134263958U, // STHBRX |
| 1073787650U, // STHCIX |
| 134252569U, // STHCX |
| 134263821U, // STHEPX |
| 470133779U, // STHU |
| 470133779U, // STHU8 |
| 503690743U, // STHUX |
| 503690743U, // STHUX8 |
| 134263525U, // STHX |
| 134263525U, // STHX8 |
| 1073787621U, // STHXTLS |
| 1073787621U, // STHXTLS_ |
| 1073787621U, // STHXTLS_32 |
| 67153677U, // STMW |
| 17847U, // STOP |
| 67151139U, // STQ |
| 134252577U, // STQCX |
| 17142U, // STQX_PSEUDO |
| 1073780203U, // STSWI |
| 134263305U, // STVEBX |
| 134263491U, // STVEHX |
| 134264419U, // STVEWX |
| 134264376U, // STVX |
| 134256383U, // STVXL |
| 67154114U, // STW |
| 67154114U, // STW8 |
| 1073785502U, // STWAT |
| 134263992U, // STWBRX |
| 1073787658U, // STWCIX |
| 134252585U, // STWCX |
| 134263836U, // STWEPX |
| 470133867U, // STWU |
| 470133867U, // STWU8 |
| 503690775U, // STWUX |
| 503690775U, // STWUX8 |
| 134264461U, // STWX |
| 134264461U, // STWX8 |
| 1073788557U, // STWXTLS |
| 1073788557U, // STWXTLS_ |
| 1073788557U, // STWXTLS_32 |
| 67145615U, // STXSD |
| 134263417U, // STXSDX |
| 134263313U, // STXSIBX |
| 134263313U, // STXSIBXv |
| 134263499U, // STXSIHX |
| 134263499U, // STXSIHXv |
| 134264435U, // STXSIWX |
| 67150816U, // STXSSP |
| 134263877U, // STXSSPX |
| 67153124U, // STXV |
| 134263233U, // STXVB16X |
| 134263198U, // STXVD2X |
| 134263251U, // STXVH8X |
| 1073780466U, // STXVL |
| 1073780361U, // STXVLL |
| 67150942U, // STXVP |
| 1073780384U, // STXVPRL |
| 1073780327U, // STXVPRLL |
| 134263893U, // STXVPX |
| 134263330U, // STXVRBX |
| 134263401U, // STXVRDX |
| 134263516U, // STXVRHX |
| 1073780408U, // STXVRL |
| 1073780345U, // STXVRLL |
| 134264452U, // STXVRWX |
| 134263215U, // STXVW4X |
| 134264388U, // STXVX |
| 1073778944U, // SUBF |
| 1073778944U, // SUBF8 |
| 1073781480U, // SUBF8O |
| 1073775911U, // SUBF8O_rec |
| 1073775355U, // SUBF8_rec |
| 1073777969U, // SUBFC |
| 1073777969U, // SUBFC8 |
| 1073781386U, // SUBFC8O |
| 1073775805U, // SUBFC8O_rec |
| 1073775029U, // SUBFC8_rec |
| 1073781386U, // SUBFCO |
| 1073775805U, // SUBFCO_rec |
| 1073775029U, // SUBFC_rec |
| 1073778818U, // SUBFE |
| 1073778818U, // SUBFE8 |
| 1073781430U, // SUBFE8O |
| 1073775855U, // SUBFE8O_rec |
| 1073775281U, // SUBFE8_rec |
| 1073781430U, // SUBFEO |
| 1073775855U, // SUBFEO_rec |
| 1073775281U, // SUBFE_rec |
| 1073777997U, // SUBFIC |
| 1073777997U, // SUBFIC8 |
| 37039U, // SUBFME |
| 37039U, // SUBFME8 |
| 39622U, // SUBFME8O |
| 34049U, // SUBFME8O_rec |
| 33473U, // SUBFME8_rec |
| 39622U, // SUBFMEO |
| 34049U, // SUBFMEO_rec |
| 33473U, // SUBFME_rec |
| 1073781480U, // SUBFO |
| 1073775911U, // SUBFO_rec |
| 872458606U, // SUBFUS |
| 872449801U, // SUBFUS_rec |
| 37106U, // SUBFZE |
| 37106U, // SUBFZE8 |
| 39647U, // SUBFZE8O |
| 34077U, // SUBFZE8O_rec |
| 33522U, // SUBFZE8_rec |
| 39647U, // SUBFZEO |
| 34077U, // SUBFZEO_rec |
| 33522U, // SUBFZE_rec |
| 1073775355U, // SUBF_rec |
| 626046U, // SYNC |
| 1083162U, // TABORT |
| 1074168234U, // TABORTDC |
| 1074168655U, // TABORTDCI |
| 1074168306U, // TABORTWC |
| 1074168667U, // TABORTWCI |
| 1182509U, // TAILB |
| 1182509U, // TAILB8 |
| 1215014U, // TAILBA |
| 1215014U, // TAILBA8 |
| 17869U, // TAILBCTR |
| 17869U, // TAILBCTR8 |
| 591004U, // TBEGIN |
| 17319U, // TBEGIN_RET |
| 1086967U, // TCHECK |
| 17307U, // TCHECK_RET |
| 2263453U, // TCRETURNai |
| 2263350U, // TCRETURNai8 |
| 2231740U, // TCRETURNdi |
| 2230596U, // TCRETURNdi8 |
| 2139567U, // TCRETURNri |
| 2132306U, // TCRETURNri8 |
| 1074171805U, // TD |
| 1074172896U, // TDI |
| 590418U, // TEND |
| 17595U, // TLBIA |
| 252022945U, // TLBIE |
| 1087021U, // TLBIEL |
| 45538U, // TLBIVAX |
| 1085073U, // TLBLD |
| 1086488U, // TLBLI |
| 17683U, // TLBRE |
| 1073778871U, // TLBRE2 |
| 46404U, // TLBSX |
| 1073788228U, // TLBSX2 |
| 1073776689U, // TLBSX2D |
| 17625U, // TLBSYNC |
| 17689U, // TLBWE |
| 1073778900U, // TLBWE2 |
| 17545U, // TLSGDAIX |
| 16485U, // TLSGDAIX8 |
| 17803U, // TRAP |
| 14541U, // TRECHKPT |
| 1082448U, // TRECLAIM |
| 591466U, // TSR |
| 1074180245U, // TW |
| 1074173426U, // TWI |
| 17165U, // UNENCODED_NOP |
| 17180U, // UpdateGBR |
| 1073777741U, // VABSDUB |
| 1073779425U, // VABSDUH |
| 1073787105U, // VABSDUW |
| 1073784134U, // VADDCUQ |
| 1073787088U, // VADDCUW |
| 1073784165U, // VADDECUQ |
| 1073780919U, // VADDEUQM |
| 1073782616U, // VADDFP |
| 1073784700U, // VADDSBS |
| 1073784975U, // VADDSHS |
| 1073785285U, // VADDSWS |
| 1073780557U, // VADDUBM |
| 1073784728U, // VADDUBS |
| 1073780629U, // VADDUDM |
| 1073780756U, // VADDUHM |
| 1073785003U, // VADDUHS |
| 1073780900U, // VADDUQM |
| 1073781012U, // VADDUWM |
| 1073785312U, // VADDUWS |
| 1073778431U, // VAND |
| 1073777962U, // VANDC |
| 1073777615U, // VAVGSB |
| 1073779311U, // VAVGSH |
| 1073786913U, // VAVGSW |
| 1073777759U, // VAVGUB |
| 1073779443U, // VAVGUH |
| 1073787132U, // VAVGUW |
| 1073778372U, // VBPERMD |
| 1073784034U, // VBPERMQ |
| 1375778131U, // VCFSX |
| 1073788243U, // VCFSX_0 |
| 1073778235U, // VCFUGED |
| 1375778288U, // VCFUX |
| 1073788400U, // VCFUX_0 |
| 1073784369U, // VCIPHER |
| 1073785705U, // VCIPHERLAST |
| 1073777536U, // VCLRLB |
| 1073777592U, // VCLRRB |
| 36067U, // VCLZB |
| 36918U, // VCLZD |
| 1073780660U, // VCLZDM |
| 37705U, // VCLZH |
| 35657U, // VCLZLSBB |
| 45430U, // VCLZW |
| 1073782580U, // VCMPBFP |
| 1073776017U, // VCMPBFP_rec |
| 1073782679U, // VCMPEQFP |
| 1073776038U, // VCMPEQFP_rec |
| 1073777784U, // VCMPEQUB |
| 1073774938U, // VCMPEQUB_rec |
| 1073778689U, // VCMPEQUD |
| 1073775210U, // VCMPEQUD_rec |
| 1073779468U, // VCMPEQUH |
| 1073775406U, // VCMPEQUH_rec |
| 1073784211U, // VCMPEQUQ |
| 1073776149U, // VCMPEQUQ_rec |
| 1073787166U, // VCMPEQUW |
| 1073776591U, // VCMPEQUW_rec |
| 1073782633U, // VCMPGEFP |
| 1073776027U, // VCMPGEFP_rec |
| 1073782689U, // VCMPGTFP |
| 1073776049U, // VCMPGTFP_rec |
| 1073777668U, // VCMPGTSB |
| 1073774919U, // VCMPGTSB_rec |
| 1073778541U, // VCMPGTSD |
| 1073775199U, // VCMPGTSD_rec |
| 1073779364U, // VCMPGTSH |
| 1073775387U, // VCMPGTSH_rec |
| 1073784081U, // VCMPGTSQ |
| 1073776138U, // VCMPGTSQ_rec |
| 1073786992U, // VCMPGTSW |
| 1073776572U, // VCMPGTSW_rec |
| 1073777852U, // VCMPGTUB |
| 1073774982U, // VCMPGTUB_rec |
| 1073778699U, // VCMPGTUD |
| 1073775221U, // VCMPGTUD_rec |
| 1073779490U, // VCMPGTUH |
| 1073775417U, // VCMPGTUH_rec |
| 1073784221U, // VCMPGTUQ |
| 1073776160U, // VCMPGTUQ_rec |
| 1073787201U, // VCMPGTUW |
| 1073776602U, // VCMPGTUW_rec |
| 1073777501U, // VCMPNEB |
| 1073774909U, // VCMPNEB_rec |
| 1073779243U, // VCMPNEH |
| 1073775377U, // VCMPNEH_rec |
| 1073786502U, // VCMPNEW |
| 1073776526U, // VCMPNEW_rec |
| 1073777881U, // VCMPNEZB |
| 1073774993U, // VCMPNEZB_rec |
| 1073779519U, // VCMPNEZH |
| 1073775428U, // VCMPNEZH_rec |
| 1073787244U, // VCMPNEZW |
| 1073776620U, // VCMPNEZW_rec |
| 1073784073U, // VCMPSQ |
| 1073784203U, // VCMPUQ |
| 1073777463U, // VCNTMBB |
| 1073778147U, // VCNTMBD |
| 1073779219U, // VCNTMBH |
| 1073786445U, // VCNTMBW |
| 1375775290U, // VCTSXS |
| 1073785402U, // VCTSXS_0 |
| 1375775298U, // VCTUXS |
| 1073785410U, // VCTUXS_0 |
| 36074U, // VCTZB |
| 36933U, // VCTZD |
| 1073780677U, // VCTZDM |
| 37712U, // VCTZH |
| 35667U, // VCTZLSBB |
| 45447U, // VCTZW |
| 1073778499U, // VDIVESD |
| 1073784064U, // VDIVESQ |
| 1073786904U, // VDIVESW |
| 1073778654U, // VDIVEUD |
| 1073784194U, // VDIVEUQ |
| 1073787123U, // VDIVEUW |
| 1073778551U, // VDIVSD |
| 1073784091U, // VDIVSQ |
| 1073787009U, // VDIVSW |
| 1073778709U, // VDIVUD |
| 1073784231U, // VDIVUQ |
| 1073787211U, // VDIVUW |
| 1073786065U, // VEQV |
| 38682U, // VEXPANDBM |
| 38764U, // VEXPANDDM |
| 38870U, // VEXPANDHM |
| 39035U, // VEXPANDQM |
| 39147U, // VEXPANDWM |
| 40826U, // VEXPTEFP |
| 1073787768U, // VEXTDDVLX |
| 1073788146U, // VEXTDDVRX |
| 1073787756U, // VEXTDUBVLX |
| 1073788134U, // VEXTDUBVRX |
| 1073787789U, // VEXTDUHVLX |
| 1073788167U, // VEXTDUHVRX |
| 1073787811U, // VEXTDUWVLX |
| 1073788189U, // VEXTDUWVRX |
| 38712U, // VEXTRACTBM |
| 1375768470U, // VEXTRACTD |
| 38784U, // VEXTRACTDM |
| 38900U, // VEXTRACTHM |
| 39055U, // VEXTRACTQM |
| 1375767728U, // VEXTRACTUB |
| 1375769366U, // VEXTRACTUH |
| 1375777064U, // VEXTRACTUW |
| 39167U, // VEXTRACTWM |
| 36254U, // VEXTSB2D |
| 36254U, // VEXTSB2Ds |
| 44266U, // VEXTSB2W |
| 44266U, // VEXTSB2Ws |
| 42094U, // VEXTSD2Q |
| 36264U, // VEXTSH2D |
| 36264U, // VEXTSH2Ds |
| 44276U, // VEXTSH2W |
| 44276U, // VEXTSH2Ws |
| 36274U, // VEXTSW2D |
| 36274U, // VEXTSW2Ds |
| 1073787708U, // VEXTUBLX |
| 1073788071U, // VEXTUBRX |
| 1073787736U, // VEXTUHLX |
| 1073788114U, // VEXTUHRX |
| 1073787832U, // VEXTUWLX |
| 1073788210U, // VEXTUWRX |
| 36316U, // VGBBD |
| 1073777565U, // VGNB |
| 1375777587U, // VINSBLX |
| 1375777950U, // VINSBRX |
| 1375777634U, // VINSBVLX |
| 1375778012U, // VINSBVRX |
| 906006365U, // VINSD |
| 1375777606U, // VINSDLX |
| 1375777984U, // VINSDRX |
| 906005565U, // VINSERTB |
| 1375768491U, // VINSERTD |
| 906007249U, // VINSERTH |
| 1375776940U, // VINSERTW |
| 1375777615U, // VINSHLX |
| 1375777993U, // VINSHRX |
| 1375777667U, // VINSHVLX |
| 1375778045U, // VINSHVRX |
| 906014816U, // VINSW |
| 1375777711U, // VINSWLX |
| 1375778089U, // VINSWRX |
| 1375777689U, // VINSWVLX |
| 1375778067U, // VINSWVRX |
| 40800U, // VLOGEFP |
| 1073782607U, // VMADDFP |
| 1073782699U, // VMAXFP |
| 1073777687U, // VMAXSB |
| 1073778559U, // VMAXSD |
| 1073779383U, // VMAXSH |
| 1073787017U, // VMAXSW |
| 1073777862U, // VMAXUB |
| 1073778717U, // VMAXUD |
| 1073779500U, // VMAXUH |
| 1073787219U, // VMAXUW |
| 1073784952U, // VMHADDSHS |
| 1073784963U, // VMHRADDSHS |
| 1073782671U, // VMINFP |
| 1073777651U, // VMINSB |
| 1073778517U, // VMINSD |
| 1073779347U, // VMINSH |
| 1073786968U, // VMINSW |
| 1073777767U, // VMINUB |
| 1073778672U, // VMINUD |
| 1073779451U, // VMINUH |
| 1073787149U, // VMINUW |
| 1073780745U, // VMLADDUHM |
| 1073778482U, // VMODSD |
| 1073784056U, // VMODSQ |
| 1073786887U, // VMODSW |
| 1073778637U, // VMODUD |
| 1073784175U, // VMODUQ |
| 1073787097U, // VMODUW |
| 1073786494U, // VMRGEW |
| 1073777510U, // VMRGHB |
| 1073779252U, // VMRGHH |
| 1073786537U, // VMRGHW |
| 1073777528U, // VMRGLB |
| 1073779260U, // VMRGLH |
| 1073786587U, // VMRGLW |
| 1073786860U, // VMRGOW |
| 1073778627U, // VMSUMCUD |
| 1073780517U, // VMSUMMBM |
| 1073780714U, // VMSUMSHM |
| 1073784984U, // VMSUMSHS |
| 1073780566U, // VMSUMUBM |
| 1073780638U, // VMSUMUDM |
| 1073780765U, // VMSUMUHM |
| 1073785012U, // VMSUMUHS |
| 42290U, // VMUL10CUQ |
| 1073784143U, // VMUL10ECUQ |
| 1073784183U, // VMUL10EUQ |
| 42280U, // VMUL10UQ |
| 1073777606U, // VMULESB |
| 1073778490U, // VMULESD |
| 1073779302U, // VMULESH |
| 1073786895U, // VMULESW |
| 1073777750U, // VMULEUB |
| 1073778645U, // VMULEUD |
| 1073779434U, // VMULEUH |
| 1073787114U, // VMULEUW |
| 1073778508U, // VMULHSD |
| 1073786930U, // VMULHSW |
| 1073778663U, // VMULHUD |
| 1073787140U, // VMULHUW |
| 1073778336U, // VMULLD |
| 1073777659U, // VMULOSB |
| 1073778532U, // VMULOSD |
| 1073779355U, // VMULOSH |
| 1073786983U, // VMULOSW |
| 1073777775U, // VMULOUB |
| 1073778680U, // VMULOUD |
| 1073779459U, // VMULOUH |
| 1073787157U, // VMULOUW |
| 1073781021U, // VMULUWM |
| 1073778416U, // VNAND |
| 1073784359U, // VNCIPHER |
| 1073785691U, // VNCIPHERLAST |
| 36441U, // VNEGD |
| 44706U, // VNEGW |
| 1073782589U, // VNMSUBFP |
| 1073784470U, // VNOR |
| 1073784483U, // VOR |
| 1073778068U, // VORC |
| 1073778437U, // VPDEPD |
| 1073780929U, // VPERM |
| 1073784430U, // VPERMR |
| 1073784503U, // VPERMXOR |
| 1073778619U, // VPEXTD |
| 1073787949U, // VPKPX |
| 1073785116U, // VPKSDSS |
| 1073785180U, // VPKSDUS |
| 1073785125U, // VPKSHSS |
| 1073785206U, // VPKSHUS |
| 1073785134U, // VPKSWSS |
| 1073785224U, // VPKSWUS |
| 1073780944U, // VPKUDUM |
| 1073785189U, // VPKUDUS |
| 1073780953U, // VPKUHUM |
| 1073785215U, // VPKUHUS |
| 1073780962U, // VPKUWUM |
| 1073785233U, // VPKUWUS |
| 1073777556U, // VPMSUMB |
| 1073778381U, // VPMSUMD |
| 1073779280U, // VPMSUMH |
| 1073786643U, // VPMSUMW |
| 35891U, // VPOPCNTB |
| 36769U, // VPOPCNTD |
| 37575U, // VPOPCNTH |
| 45218U, // VPOPCNTW |
| 36332U, // VPRTYBD |
| 42111U, // VPRTYBQ |
| 44630U, // VPRTYBW |
| 40819U, // VREFP |
| 38963U, // VRFIM |
| 39348U, // VRFIN |
| 40903U, // VRFIP |
| 46884U, // VRFIZ |
| 1073777544U, // VRLB |
| 1073778360U, // VRLD |
| 1073779775U, // VRLDMI |
| 1073780827U, // VRLDNM |
| 1073779268U, // VRLH |
| 1073784022U, // VRLQ |
| 1073779799U, // VRLQMI |
| 1073780843U, // VRLQNM |
| 1073786619U, // VRLW |
| 1073779895U, // VRLWMI |
| 1073780851U, // VRLWNM |
| 40836U, // VRSQRTEFP |
| 46027U, // VSBOX |
| 1073780289U, // VSEL |
| 1073778121U, // VSHASIGMAD |
| 1073786426U, // VSHASIGMAW |
| 1073780424U, // VSL |
| 1073777550U, // VSLB |
| 1073778366U, // VSLD |
| 1073779555U, // VSLDBI |
| 1073779924U, // VSLDOI |
| 1073779274U, // VSLH |
| 1073781526U, // VSLO |
| 1073784028U, // VSLQ |
| 1073786043U, // VSLV |
| 1073786626U, // VSLW |
| 1375767595U, // VSPLTB |
| 1375767595U, // VSPLTBs |
| 1375769279U, // VSPLTH |
| 1375769279U, // VSPLTHs |
| 335580128U, // VSPLTISB |
| 335581824U, // VSPLTISH |
| 335589435U, // VSPLTISW |
| 1375776913U, // VSPLTW |
| 1073784568U, // VSR |
| 1073777449U, // VSRAB |
| 1073778133U, // VSRAD |
| 1073779212U, // VSRAH |
| 1073783928U, // VSRAQ |
| 1073786438U, // VSRAW |
| 1073777600U, // VSRB |
| 1073778468U, // VSRD |
| 1073779563U, // VSRDBI |
| 1073779296U, // VSRH |
| 1073781647U, // VSRO |
| 1073784050U, // VSRQ |
| 1073786071U, // VSRV |
| 1073786881U, // VSRW |
| 38416U, // VSTRIBL |
| 33821U, // VSTRIBL_rec |
| 42434U, // VSTRIBR |
| 34347U, // VSTRIBR_rec |
| 38485U, // VSTRIHL |
| 33855U, // VSTRIHL_rec |
| 42554U, // VSTRIHR |
| 34374U, // VSTRIHR_rec |
| 1073784125U, // VSUBCUQ |
| 1073787079U, // VSUBCUW |
| 1073784155U, // VSUBECUQ |
| 1073780909U, // VSUBEUQM |
| 1073782599U, // VSUBFP |
| 1073784691U, // VSUBSBS |
| 1073784943U, // VSUBSHS |
| 1073785276U, // VSUBSWS |
| 1073780548U, // VSUBUBM |
| 1073784719U, // VSUBUBS |
| 1073780620U, // VSUBUDM |
| 1073780736U, // VSUBUHM |
| 1073784994U, // VSUBUHS |
| 1073780891U, // VSUBUQM |
| 1073781003U, // VSUBUWM |
| 1073785303U, // VSUBUWS |
| 1073785266U, // VSUM2SWS |
| 1073784681U, // VSUM4SBS |
| 1073784933U, // VSUM4SHS |
| 1073784709U, // VSUM4UBS |
| 1073785294U, // VSUMSWS |
| 46116U, // VUPKHPX |
| 35799U, // VUPKHSB |
| 37495U, // VUPKHSH |
| 45097U, // VUPKHSW |
| 46132U, // VUPKLPX |
| 35818U, // VUPKLSB |
| 37514U, // VUPKLSH |
| 45125U, // VUPKLSW |
| 1073784521U, // VXOR |
| 1308665545U, // V_SET0 |
| 1308665545U, // V_SET0B |
| 1308665545U, // V_SET0H |
| 21016635U, // V_SETALLONES |
| 21016635U, // V_SETALLONESB |
| 21016635U, // V_SETALLONESH |
| 633601U, // WAIT |
| 1085563U, // WRTEE |
| 1086437U, // WRTEEI |
| 1073784491U, // XOR |
| 1073784491U, // XOR8 |
| 1073776220U, // XOR8_rec |
| 1073779964U, // XORI |
| 1073779964U, // XORI8 |
| 1073785059U, // XORIS |
| 1073785059U, // XORIS8 |
| 1073776220U, // XOR_rec |
| 40526U, // XSABSDP |
| 41407U, // XSABSQP |
| 1073781863U, // XSADDDP |
| 1073783059U, // XSADDQP |
| 1073781606U, // XSADDQPO |
| 1073783412U, // XSADDSP |
| 1073782308U, // XSCMPEQDP |
| 1073783190U, // XSCMPEQQP |
| 1073782276U, // XSCMPEXPDP |
| 1073783168U, // XSCMPEXPQP |
| 1073781925U, // XSCMPGEDP |
| 1073783088U, // XSCMPGEQP |
| 1073782368U, // XSCMPGTDP |
| 1073783240U, // XSCMPGTQP |
| 1073782206U, // XSCMPODP |
| 1073783138U, // XSCMPOQP |
| 1073782432U, // XSCMPUDP |
| 1073783261U, // XSCMPUQP |
| 1073782166U, // XSCPSGNDP |
| 1073783127U, // XSCPSGNQP |
| 40883U, // XSCVDPHP |
| 41324U, // XSCVDPQP |
| 41850U, // XSCVDPSP |
| 39519U, // XSCVDPSPN |
| 42987U, // XSCVDPSXDS |
| 42987U, // XSCVDPSXDSs |
| 43506U, // XSCVDPSXWS |
| 43506U, // XSCVDPSXWSs |
| 43023U, // XSCVDPUXDS |
| 43023U, // XSCVDPUXDSs |
| 43542U, // XSCVDPUXWS |
| 43542U, // XSCVDPUXWSs |
| 40392U, // XSCVHPDP |
| 40402U, // XSCVQPDP |
| 39708U, // XSCVQPDPO |
| 46856U, // XSCVQPSDZ |
| 46981U, // XSCVQPSQZ |
| 47064U, // XSCVQPSWZ |
| 46867U, // XSCVQPUDZ |
| 46992U, // XSCVQPUQZ |
| 47075U, // XSCVQPUWZ |
| 41244U, // XSCVSDQP |
| 40412U, // XSCVSPDP |
| 39467U, // XSCVSPDPN |
| 41377U, // XSCVSQQP |
| 40057U, // XSCVSXDDP |
| 41606U, // XSCVSXDSP |
| 41254U, // XSCVUDQP |
| 41387U, // XSCVUQQP |
| 40079U, // XSCVUXDDP |
| 41628U, // XSCVUXDSP |
| 1073782442U, // XSDIVDP |
| 1073783271U, // XSDIVQP |
| 1073781637U, // XSDIVQPO |
| 1073783826U, // XSDIVSP |
| 1073782256U, // XSIEXPDP |
| 1073783158U, // XSIEXPQP |
| 1375771669U, // XSMADDADP |
| 1375773238U, // XSMADDASP |
| 1375772032U, // XSMADDMDP |
| 1375773520U, // XSMADDMSP |
| 1375772937U, // XSMADDQP |
| 1375771483U, // XSMADDQPO |
| 1073781853U, // XSMAXCDP |
| 1073783028U, // XSMAXCQP |
| 1073782502U, // XSMAXDP |
| 1073782046U, // XSMAXJDP |
| 1073781843U, // XSMINCDP |
| 1073783018U, // XSMINCQP |
| 1073782188U, // XSMINDP |
| 1073782036U, // XSMINJDP |
| 1375771623U, // XSMSUBADP |
| 1375773192U, // XSMSUBASP |
| 1375771986U, // XSMSUBMDP |
| 1375773474U, // XSMSUBMSP |
| 1375772876U, // XSMSUBQP |
| 1375771450U, // XSMSUBQPO |
| 1073782056U, // XSMULDP |
| 1073783118U, // XSMULQP |
| 1073781616U, // XSMULQPO |
| 1073783544U, // XSMULSP |
| 40506U, // XSNABSDP |
| 40506U, // XSNABSDPs |
| 41397U, // XSNABSQP |
| 40163U, // XSNEGDP |
| 41275U, // XSNEGQP |
| 1375771645U, // XSNMADDADP |
| 1375773214U, // XSNMADDASP |
| 1375772008U, // XSNMADDMDP |
| 1375773496U, // XSNMADDMSP |
| 1375772926U, // XSNMADDQP |
| 1375771471U, // XSNMADDQPO |
| 1375771599U, // XSNMSUBADP |
| 1375773168U, // XSNMSUBASP |
| 1375771962U, // XSNMSUBMDP |
| 1375773450U, // XSNMSUBMSP |
| 1375772865U, // XSNMSUBQP |
| 1375771438U, // XSNMSUBQPO |
| 38108U, // XSRDPI |
| 36181U, // XSRDPIC |
| 38970U, // XSRDPIM |
| 40910U, // XSRDPIP |
| 46891U, // XSRDPIZ |
| 40123U, // XSREDP |
| 41661U, // XSRESP |
| 660716U, // XSRQPI |
| 668458U, // XSRQPIX |
| 664677U, // XSRQPXP |
| 41917U, // XSRSP |
| 40139U, // XSRSQRTEDP |
| 41677U, // XSRSQRTESP |
| 40566U, // XSSQRTDP |
| 41427U, // XSSQRTQP |
| 39802U, // XSSQRTQPO |
| 41971U, // XSSQRTSP |
| 1073781803U, // XSSUBDP |
| 1073782998U, // XSSUBQP |
| 1073781573U, // XSSUBQPO |
| 1073783372U, // XSSUBSP |
| 1073782451U, // XSTDIVDP |
| 40576U, // XSTSQRTDP |
| 1375771709U, // XSTSTDCDP |
| 1375772895U, // XSTSTDCQP |
| 1375773278U, // XSTSTDCSP |
| 40464U, // XSXEXPDP |
| 41356U, // XSXEXPQP |
| 40181U, // XSXSIGDP |
| 41284U, // XSXSIGQP |
| 40535U, // XVABSDP |
| 41934U, // XVABSSP |
| 1073781872U, // XVADDDP |
| 1073783421U, // XVADDSP |
| 1073776833U, // XVBF16GER2 |
| 1375771091U, // XVBF16GER2NN |
| 1375772675U, // XVBF16GER2NP |
| 1375771150U, // XVBF16GER2PN |
| 1375772734U, // XVBF16GER2PP |
| 1073776833U, // XVBF16GER2W |
| 1375771091U, // XVBF16GER2WNN |
| 1375772675U, // XVBF16GER2WNP |
| 1375771150U, // XVBF16GER2WPN |
| 1375772734U, // XVBF16GER2WPP |
| 1073782319U, // XVCMPEQDP |
| 1073775993U, // XVCMPEQDP_rec |
| 1073783724U, // XVCMPEQSP |
| 1073776079U, // XVCMPEQSP_rec |
| 1073781936U, // XVCMPGEDP |
| 1073775981U, // XVCMPGEDP_rec |
| 1073783474U, // XVCMPGESP |
| 1073776067U, // XVCMPGESP_rec |
| 1073782379U, // XVCMPGTDP |
| 1073776005U, // XVCMPGTDP_rec |
| 1073783784U, // XVCMPGTSP |
| 1073776098U, // XVCMPGTSP_rec |
| 1073782177U, // XVCPSGNDP |
| 1073783654U, // XVCPSGNSP |
| 39506U, // XVCVBF16SPN |
| 41860U, // XVCVDPSP |
| 42999U, // XVCVDPSXDS |
| 43518U, // XVCVDPSXWS |
| 43035U, // XVCVDPUXDS |
| 43554U, // XVCVDPUXWS |
| 41870U, // XVCVHPSP |
| 35081U, // XVCVSPBF16 |
| 40422U, // XVCVSPDP |
| 40893U, // XVCVSPHP |
| 43011U, // XVCVSPSXDS |
| 43530U, // XVCVSPSXWS |
| 43047U, // XVCVSPUXDS |
| 43566U, // XVCVSPUXWS |
| 40068U, // XVCVSXDDP |
| 41617U, // XVCVSXDSP |
| 40656U, // XVCVSXWDP |
| 42030U, // XVCVSXWSP |
| 40090U, // XVCVUXDDP |
| 41639U, // XVCVUXDSP |
| 40667U, // XVCVUXWDP |
| 42041U, // XVCVUXWSP |
| 1073782471U, // XVDIVDP |
| 1073783845U, // XVDIVSP |
| 1073776847U, // XVF16GER2 |
| 1375771107U, // XVF16GER2NN |
| 1375772691U, // XVF16GER2NP |
| 1375771166U, // XVF16GER2PN |
| 1375772750U, // XVF16GER2PP |
| 1073776847U, // XVF16GER2W |
| 1375771107U, // XVF16GER2WNN |
| 1375772691U, // XVF16GER2WNP |
| 1375771166U, // XVF16GER2WPN |
| 1375772750U, // XVF16GER2WPP |
| 1073784337U, // XVF32GER |
| 1375771122U, // XVF32GERNN |
| 1375772706U, // XVF32GERNP |
| 1375771192U, // XVF32GERPN |
| 1375772808U, // XVF32GERPP |
| 1073784337U, // XVF32GERW |
| 1375771122U, // XVF32GERWNN |
| 1375772706U, // XVF32GERWNP |
| 1375771192U, // XVF32GERWPN |
| 1375772808U, // XVF32GERWPP |
| 1073784349U, // XVF64GER |
| 1375771136U, // XVF64GERNN |
| 1375772720U, // XVF64GERNP |
| 1375771206U, // XVF64GERPN |
| 1375772822U, // XVF64GERPP |
| 1073784349U, // XVF64GERW |
| 1375771136U, // XVF64GERWNN |
| 1375772720U, // XVF64GERWNP |
| 1375771206U, // XVF64GERWPN |
| 1375772822U, // XVF64GERWPP |
| 1073776860U, // XVI16GER2 |
| 1375772765U, // XVI16GER2PP |
| 1073784596U, // XVI16GER2S |
| 1375772836U, // XVI16GER2SPP |
| 1073784596U, // XVI16GER2SW |
| 1375772836U, // XVI16GER2SWPP |
| 1073776860U, // XVI16GER2W |
| 1375772765U, // XVI16GER2WPP |
| 1073776994U, // XVI4GER8 |
| 1375772794U, // XVI4GER8PP |
| 1073776994U, // XVI4GER8W |
| 1375772794U, // XVI4GER8WPP |
| 1073776873U, // XVI8GER4 |
| 1375772780U, // XVI8GER4PP |
| 1375772852U, // XVI8GER4SPP |
| 1073776873U, // XVI8GER4W |
| 1375772780U, // XVI8GER4WPP |
| 1375772852U, // XVI8GER4WSPP |
| 1073782266U, // XVIEXPDP |
| 1073783704U, // XVIEXPSP |
| 1375771680U, // XVMADDADP |
| 1375773249U, // XVMADDASP |
| 1375772043U, // XVMADDMDP |
| 1375773531U, // XVMADDMSP |
| 1073782511U, // XVMAXDP |
| 1073783876U, // XVMAXSP |
| 1073782197U, // XVMINDP |
| 1073783665U, // XVMINSP |
| 1375771634U, // XVMSUBADP |
| 1375773203U, // XVMSUBASP |
| 1375771997U, // XVMSUBMDP |
| 1375773485U, // XVMSUBMSP |
| 1073782065U, // XVMULDP |
| 1073783553U, // XVMULSP |
| 40516U, // XVNABSDP |
| 41924U, // XVNABSSP |
| 40172U, // XVNEGDP |
| 41701U, // XVNEGSP |
| 1375771657U, // XVNMADDADP |
| 1375773226U, // XVNMADDASP |
| 1375772020U, // XVNMADDMDP |
| 1375773508U, // XVNMADDMSP |
| 1375771611U, // XVNMSUBADP |
| 1375773180U, // XVNMSUBASP |
| 1375771974U, // XVNMSUBMDP |
| 1375773462U, // XVNMSUBMSP |
| 38116U, // XVRDPI |
| 36190U, // XVRDPIC |
| 38979U, // XVRDPIM |
| 40919U, // XVRDPIP |
| 46900U, // XVRDPIZ |
| 40131U, // XVREDP |
| 41669U, // XVRESP |
| 38132U, // XVRSPI |
| 36199U, // XVRSPIC |
| 38988U, // XVRSPIM |
| 40928U, // XVRSPIP |
| 46909U, // XVRSPIZ |
| 40151U, // XVRSQRTEDP |
| 41689U, // XVRSQRTESP |
| 40598U, // XVSQRTDP |
| 41992U, // XVSQRTSP |
| 1073781812U, // XVSUBDP |
| 1073783381U, // XVSUBSP |
| 1073782461U, // XVTDIVDP |
| 1073783835U, // XVTDIVSP |
| 35648U, // XVTLSBB |
| 40587U, // XVTSQRTDP |
| 41981U, // XVTSQRTSP |
| 1375771720U, // XVTSTDCDP |
| 1375773289U, // XVTSTDCSP |
| 40474U, // XVXEXPDP |
| 41890U, // XVXEXPSP |
| 40191U, // XVXSIGDP |
| 41710U, // XVXSIGSP |
| 1073777870U, // XXBLENDVB |
| 1073778725U, // XXBLENDVD |
| 1073779508U, // XXBLENDVH |
| 1073787227U, // XXBLENDVW |
| 36627U, // XXBRD |
| 37465U, // XXBRH |
| 42219U, // XXBRQ |
| 45050U, // XXBRW |
| 1073780232U, // XXEVAL |
| 1073787188U, // XXEXTRACTUW |
| 1073780576U, // XXGENPCVBM |
| 1073780648U, // XXGENPCVDM |
| 1073780775U, // XXGENPCVHM |
| 1073781030U, // XXGENPCVWM |
| 1375776950U, // XXINSERTW |
| 1073778390U, // XXLAND |
| 1073777944U, // XXLANDC |
| 1073786049U, // XXLEQV |
| 1308667073U, // XXLEQVOnes |
| 1073778398U, // XXLNAND |
| 1073784454U, // XXLNOR |
| 1073784447U, // XXLOR |
| 1073778052U, // XXLORC |
| 1073784447U, // XXLORf |
| 1073784488U, // XXLXOR |
| 1308665512U, // XXLXORdpz |
| 1308665512U, // XXLXORspz |
| 1308665512U, // XXLXORz |
| 1412352U, // XXMFACC |
| 1412352U, // XXMFACCW |
| 1073786545U, // XXMRGHW |
| 1073786595U, // XXMRGLW |
| 1084681U, // XXMTACC |
| 1084681U, // XXMTACCW |
| 1073780936U, // XXPERM |
| 1073779631U, // XXPERMDI |
| 1073779631U, // XXPERMDIs |
| 1073784438U, // XXPERMR |
| 1073787842U, // XXPERMX |
| 1073780295U, // XXSEL |
| 1095386U, // XXSETACCZ |
| 1095386U, // XXSETACCZW |
| 1073780099U, // XXSLDWI |
| 1073780099U, // XXSLDWIs |
| 1744876081U, // XXSPLTI32DX |
| 939559790U, // XXSPLTIB |
| 40201U, // XXSPLTIDP |
| 44753U, // XXSPLTIW |
| 1073787033U, // XXSPLTW |
| 1073787033U, // XXSPLTWs |
| 1074171125U, // gBC |
| 1074170410U, // gBCA |
| 22725809U, // gBCAat |
| 1074177789U, // gBCCTR |
| 1074173609U, // gBCCTRL |
| 1074173465U, // gBCL |
| 1074170609U, // gBCLA |
| 22725825U, // gBCLAat |
| 1074177603U, // gBCLR |
| 1074173585U, // gBCLRL |
| 23774524U, // gBCLat |
| 23774414U, // gBCat |
| }; |
| |
| static const uint16_t OpInfo1[] = { |
| 0U, // PHI |
| 0U, // INLINEASM |
| 0U, // INLINEASM_BR |
| 0U, // CFI_INSTRUCTION |
| 0U, // EH_LABEL |
| 0U, // GC_LABEL |
| 0U, // ANNOTATION_LABEL |
| 0U, // KILL |
| 0U, // EXTRACT_SUBREG |
| 0U, // INSERT_SUBREG |
| 0U, // IMPLICIT_DEF |
| 0U, // SUBREG_TO_REG |
| 0U, // COPY_TO_REGCLASS |
| 0U, // DBG_VALUE |
| 0U, // DBG_VALUE_LIST |
| 0U, // DBG_INSTR_REF |
| 0U, // DBG_PHI |
| 0U, // DBG_LABEL |
| 0U, // REG_SEQUENCE |
| 0U, // COPY |
| 0U, // BUNDLE |
| 0U, // LIFETIME_START |
| 0U, // LIFETIME_END |
| 0U, // PSEUDO_PROBE |
| 0U, // ARITH_FENCE |
| 0U, // STACKMAP |
| 0U, // FENTRY_CALL |
| 0U, // PATCHPOINT |
| 0U, // LOAD_STACK_GUARD |
| 0U, // PREALLOCATED_SETUP |
| 0U, // PREALLOCATED_ARG |
| 0U, // STATEPOINT |
| 0U, // LOCAL_ESCAPE |
| 0U, // FAULTING_OP |
| 0U, // PATCHABLE_OP |
| 0U, // PATCHABLE_FUNCTION_ENTER |
| 0U, // PATCHABLE_RET |
| 0U, // PATCHABLE_FUNCTION_EXIT |
| 0U, // PATCHABLE_TAIL_CALL |
| 0U, // PATCHABLE_EVENT_CALL |
| 0U, // PATCHABLE_TYPED_EVENT_CALL |
| 0U, // ICALL_BRANCH_FUNNEL |
| 0U, // MEMBARRIER |
| 0U, // G_ASSERT_SEXT |
| 0U, // G_ASSERT_ZEXT |
| 0U, // G_ASSERT_ALIGN |
| 0U, // G_ADD |
| 0U, // G_SUB |
| 0U, // G_MUL |
| 0U, // G_SDIV |
| 0U, // G_UDIV |
| 0U, // G_SREM |
| 0U, // G_UREM |
| 0U, // G_SDIVREM |
| 0U, // G_UDIVREM |
| 0U, // G_AND |
| 0U, // G_OR |
| 0U, // G_XOR |
| 0U, // G_IMPLICIT_DEF |
| 0U, // G_PHI |
| 0U, // G_FRAME_INDEX |
| 0U, // G_GLOBAL_VALUE |
| 0U, // G_EXTRACT |
| 0U, // G_UNMERGE_VALUES |
| 0U, // G_INSERT |
| 0U, // G_MERGE_VALUES |
| 0U, // G_BUILD_VECTOR |
| 0U, // G_BUILD_VECTOR_TRUNC |
| 0U, // G_CONCAT_VECTORS |
| 0U, // G_PTRTOINT |
| 0U, // G_INTTOPTR |
| 0U, // G_BITCAST |
| 0U, // G_FREEZE |
| 0U, // G_INTRINSIC_FPTRUNC_ROUND |
| 0U, // G_INTRINSIC_TRUNC |
| 0U, // G_INTRINSIC_ROUND |
| 0U, // G_INTRINSIC_LRINT |
| 0U, // G_INTRINSIC_ROUNDEVEN |
| 0U, // G_READCYCLECOUNTER |
| 0U, // G_LOAD |
| 0U, // G_SEXTLOAD |
| 0U, // G_ZEXTLOAD |
| 0U, // G_INDEXED_LOAD |
| 0U, // G_INDEXED_SEXTLOAD |
| 0U, // G_INDEXED_ZEXTLOAD |
| 0U, // G_STORE |
| 0U, // G_INDEXED_STORE |
| 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS |
| 0U, // G_ATOMIC_CMPXCHG |
| 0U, // G_ATOMICRMW_XCHG |
| 0U, // G_ATOMICRMW_ADD |
| 0U, // G_ATOMICRMW_SUB |
| 0U, // G_ATOMICRMW_AND |
| 0U, // G_ATOMICRMW_NAND |
| 0U, // G_ATOMICRMW_OR |
| 0U, // G_ATOMICRMW_XOR |
| 0U, // G_ATOMICRMW_MAX |
| 0U, // G_ATOMICRMW_MIN |
| 0U, // G_ATOMICRMW_UMAX |
| 0U, // G_ATOMICRMW_UMIN |
| 0U, // G_ATOMICRMW_FADD |
| 0U, // G_ATOMICRMW_FSUB |
| 0U, // G_ATOMICRMW_FMAX |
| 0U, // G_ATOMICRMW_FMIN |
| 0U, // G_ATOMICRMW_UINC_WRAP |
| 0U, // G_ATOMICRMW_UDEC_WRAP |
| 0U, // G_FENCE |
| 0U, // G_BRCOND |
| 0U, // G_BRINDIRECT |
| 0U, // G_INVOKE_REGION_START |
| 0U, // G_INTRINSIC |
| 0U, // G_INTRINSIC_W_SIDE_EFFECTS |
| 0U, // G_ANYEXT |
| 0U, // G_TRUNC |
| 0U, // G_CONSTANT |
| 0U, // G_FCONSTANT |
| 0U, // G_VASTART |
| 0U, // G_VAARG |
| 0U, // G_SEXT |
| 0U, // G_SEXT_INREG |
| 0U, // G_ZEXT |
| 0U, // G_SHL |
| 0U, // G_LSHR |
| 0U, // G_ASHR |
| 0U, // G_FSHL |
| 0U, // G_FSHR |
| 0U, // G_ROTR |
| 0U, // G_ROTL |
| 0U, // G_ICMP |
| 0U, // G_FCMP |
| 0U, // G_SELECT |
| 0U, // G_UADDO |
| 0U, // G_UADDE |
| 0U, // G_USUBO |
| 0U, // G_USUBE |
| 0U, // G_SADDO |
| 0U, // G_SADDE |
| 0U, // G_SSUBO |
| 0U, // G_SSUBE |
| 0U, // G_UMULO |
| 0U, // G_SMULO |
| 0U, // G_UMULH |
| 0U, // G_SMULH |
| 0U, // G_UADDSAT |
| 0U, // G_SADDSAT |
| 0U, // G_USUBSAT |
| 0U, // G_SSUBSAT |
| 0U, // G_USHLSAT |
| 0U, // G_SSHLSAT |
| 0U, // G_SMULFIX |
| 0U, // G_UMULFIX |
| 0U, // G_SMULFIXSAT |
| 0U, // G_UMULFIXSAT |
| 0U, // G_SDIVFIX |
| 0U, // G_UDIVFIX |
| 0U, // G_SDIVFIXSAT |
| 0U, // G_UDIVFIXSAT |
| 0U, // G_FADD |
| 0U, // G_FSUB |
| 0U, // G_FMUL |
| 0U, // G_FMA |
| 0U, // G_FMAD |
| 0U, // G_FDIV |
| 0U, // G_FREM |
| 0U, // G_FPOW |
| 0U, // G_FPOWI |
| 0U, // G_FEXP |
| 0U, // G_FEXP2 |
| 0U, // G_FLOG |
| 0U, // G_FLOG2 |
| 0U, // G_FLOG10 |
| 0U, // G_FNEG |
| 0U, // G_FPEXT |
| 0U, // G_FPTRUNC |
| 0U, // G_FPTOSI |
| 0U, // G_FPTOUI |
| 0U, // G_SITOFP |
| 0U, // G_UITOFP |
| 0U, // G_FABS |
| 0U, // G_FCOPYSIGN |
| 0U, // G_IS_FPCLASS |
| 0U, // G_FCANONICALIZE |
| 0U, // G_FMINNUM |
| 0U, // G_FMAXNUM |
| 0U, // G_FMINNUM_IEEE |
| 0U, // G_FMAXNUM_IEEE |
| 0U, // G_FMINIMUM |
| 0U, // G_FMAXIMUM |
| 0U, // G_PTR_ADD |
| 0U, // G_PTRMASK |
| 0U, // G_SMIN |
| 0U, // G_SMAX |
| 0U, // G_UMIN |
| 0U, // G_UMAX |
| 0U, // G_ABS |
| 0U, // G_LROUND |
| 0U, // G_LLROUND |
| 0U, // G_BR |
| 0U, // G_BRJT |
| 0U, // G_INSERT_VECTOR_ELT |
| 0U, // G_EXTRACT_VECTOR_ELT |
| 0U, // G_SHUFFLE_VECTOR |
| 0U, // G_CTTZ |
| 0U, // G_CTTZ_ZERO_UNDEF |
| 0U, // G_CTLZ |
| 0U, // G_CTLZ_ZERO_UNDEF |
| 0U, // G_CTPOP |
| 0U, // G_BSWAP |
| 0U, // G_BITREVERSE |
| 0U, // G_FCEIL |
| 0U, // G_FCOS |
| 0U, // G_FSIN |
| 0U, // G_FSQRT |
| 0U, // G_FFLOOR |
| 0U, // G_FRINT |
| 0U, // G_FNEARBYINT |
| 0U, // G_ADDRSPACE_CAST |
| 0U, // G_BLOCK_ADDR |
| 0U, // G_JUMP_TABLE |
| 0U, // G_DYN_STACKALLOC |
| 0U, // G_STRICT_FADD |
| 0U, // G_STRICT_FSUB |
| 0U, // G_STRICT_FMUL |
| 0U, // G_STRICT_FDIV |
| 0U, // G_STRICT_FREM |
| 0U, // G_STRICT_FMA |
| 0U, // G_STRICT_FSQRT |
| 0U, // G_READ_REGISTER |
| 0U, // G_WRITE_REGISTER |
| 0U, // G_MEMCPY |
| 0U, // G_MEMCPY_INLINE |
| 0U, // G_MEMMOVE |
| 0U, // G_MEMSET |
| 0U, // G_BZERO |
| 0U, // G_VECREDUCE_SEQ_FADD |
| 0U, // G_VECREDUCE_SEQ_FMUL |
| 0U, // G_VECREDUCE_FADD |
| 0U, // G_VECREDUCE_FMUL |
| 0U, // G_VECREDUCE_FMAX |
| 0U, // G_VECREDUCE_FMIN |
| 0U, // G_VECREDUCE_ADD |
| 0U, // G_VECREDUCE_MUL |
| 0U, // G_VECREDUCE_AND |
| 0U, // G_VECREDUCE_OR |
| 0U, // G_VECREDUCE_XOR |
| 0U, // G_VECREDUCE_SMAX |
| 0U, // G_VECREDUCE_SMIN |
| 0U, // G_VECREDUCE_UMAX |
| 0U, // G_VECREDUCE_UMIN |
| 0U, // G_SBFX |
| 0U, // G_UBFX |
| 0U, // ATOMIC_CMP_SWAP_I128 |
| 0U, // ATOMIC_LOAD_ADD_I128 |
| 0U, // ATOMIC_LOAD_AND_I128 |
| 0U, // ATOMIC_LOAD_NAND_I128 |
| 0U, // ATOMIC_LOAD_OR_I128 |
| 0U, // ATOMIC_LOAD_SUB_I128 |
| 0U, // ATOMIC_LOAD_XOR_I128 |
| 0U, // ATOMIC_SWAP_I128 |
| 0U, // BUILD_QUADWORD |
| 0U, // BUILD_UACC |
| 0U, // CFENCE8 |
| 0U, // CLRLSLDI |
| 0U, // CLRLSLDI_rec |
| 258U, // CLRLSLWI |
| 258U, // CLRLSLWI_rec |
| 64U, // CLRRDI |
| 64U, // CLRRDI_rec |
| 66U, // CLRRWI |
| 66U, // CLRRWI_rec |
| 0U, // DCBFL |
| 0U, // DCBFLP |
| 0U, // DCBFPS |
| 0U, // DCBFx |
| 0U, // DCBSTPS |
| 0U, // DCBTCT |
| 0U, // DCBTDS |
| 0U, // DCBTSTCT |
| 0U, // DCBTSTDS |
| 0U, // DCBTSTT |
| 0U, // DCBTSTx |
| 0U, // DCBTT |
| 0U, // DCBTx |
| 0U, // DFLOADf32 |
| 0U, // DFLOADf64 |
| 0U, // DFSTOREf32 |
| 0U, // DFSTOREf64 |
| 0U, // EXTLDI |
| 0U, // EXTLDI_rec |
| 258U, // EXTLWI |
| 258U, // EXTLWI_rec |
| 0U, // EXTRDI |
| 0U, // EXTRDI_rec |
| 258U, // EXTRWI |
| 258U, // EXTRWI_rec |
| 258U, // INSLWI |
| 258U, // INSLWI_rec |
| 0U, // INSRDI |
| 0U, // INSRDI_rec |
| 258U, // INSRWI |
| 258U, // INSRWI_rec |
| 0U, // KILL_PAIR |
| 0U, // LAx |
| 0U, // LIWAX |
| 0U, // LIWZX |
| 514U, // RLWIMIbm |
| 514U, // RLWIMIbm_rec |
| 514U, // RLWINMbm |
| 514U, // RLWINMbm_rec |
| 514U, // RLWNMbm |
| 514U, // RLWNMbm_rec |
| 64U, // ROTRDI |
| 64U, // ROTRDI_rec |
| 66U, // ROTRWI |
| 66U, // ROTRWI_rec |
| 64U, // SLDI |
| 64U, // SLDI_rec |
| 66U, // SLWI |
| 66U, // SLWI_rec |
| 0U, // SPILLTOVSR_LD |
| 0U, // SPILLTOVSR_LDX |
| 0U, // SPILLTOVSR_ST |
| 0U, // SPILLTOVSR_STX |
| 64U, // SRDI |
| 64U, // SRDI_rec |
| 66U, // SRWI |
| 66U, // SRWI_rec |
| 0U, // STIWX |
| 4U, // SUBI |
| 4U, // SUBIC |
| 4U, // SUBIC_rec |
| 4U, // SUBIS |
| 0U, // SUBPCIS |
| 0U, // XFLOADf32 |
| 0U, // XFLOADf64 |
| 0U, // XFSTOREf32 |
| 0U, // XFSTOREf64 |
| 70U, // ADD4 |
| 70U, // ADD4O |
| 70U, // ADD4O_rec |
| 70U, // ADD4TLS |
| 70U, // ADD4_rec |
| 70U, // ADD8 |
| 70U, // ADD8O |
| 70U, // ADD8O_rec |
| 70U, // ADD8TLS |
| 70U, // ADD8TLS_ |
| 70U, // ADD8_rec |
| 70U, // ADDC |
| 70U, // ADDC8 |
| 70U, // ADDC8O |
| 70U, // ADDC8O_rec |
| 70U, // ADDC8_rec |
| 70U, // ADDCO |
| 70U, // ADDCO_rec |
| 70U, // ADDC_rec |
| 70U, // ADDE |
| 70U, // ADDE8 |
| 70U, // ADDE8O |
| 70U, // ADDE8O_rec |
| 70U, // ADDE8_rec |
| 70U, // ADDEO |
| 70U, // ADDEO_rec |
| 774U, // ADDEX |
| 774U, // ADDEX8 |
| 70U, // ADDE_rec |
| 4U, // ADDI |
| 4U, // ADDI8 |
| 4U, // ADDIC |
| 4U, // ADDIC8 |
| 4U, // ADDIC_rec |
| 4U, // ADDIS |
| 4U, // ADDIS8 |
| 0U, // ADDISdtprelHA |
| 0U, // ADDISdtprelHA32 |
| 0U, // ADDISgotTprelHA |
| 0U, // ADDIStlsgdHA |
| 0U, // ADDIStlsldHA |
| 0U, // ADDIStocHA |
| 0U, // ADDIStocHA8 |
| 0U, // ADDIdtprelL |
| 0U, // ADDIdtprelL32 |
| 0U, // ADDItlsgdL |
| 0U, // ADDItlsgdL32 |
| 0U, // ADDItlsgdLADDR |
| 0U, // ADDItlsgdLADDR32 |
| 0U, // ADDItlsldL |
| 0U, // ADDItlsldL32 |
| 0U, // ADDItlsldLADDR |
| 0U, // ADDItlsldLADDR32 |
| 0U, // ADDItoc |
| 0U, // ADDItoc8 |
| 0U, // ADDItocL |
| 0U, // ADDME |
| 0U, // ADDME8 |
| 0U, // ADDME8O |
| 0U, // ADDME8O_rec |
| 0U, // ADDME8_rec |
| 0U, // ADDMEO |
| 0U, // ADDMEO_rec |
| 0U, // ADDME_rec |
| 0U, // ADDPCIS |
| 0U, // ADDZE |
| 0U, // ADDZE8 |
| 0U, // ADDZE8O |
| 0U, // ADDZE8O_rec |
| 0U, // ADDZE8_rec |
| 0U, // ADDZEO |
| 0U, // ADDZEO_rec |
| 0U, // ADDZE_rec |
| 0U, // ADJCALLSTACKDOWN |
| 0U, // ADJCALLSTACKUP |
| 70U, // AND |
| 70U, // AND8 |
| 70U, // AND8_rec |
| 70U, // ANDC |
| 70U, // ANDC8 |
| 70U, // ANDC8_rec |
| 70U, // ANDC_rec |
| 8U, // ANDI8_rec |
| 8U, // ANDIS8_rec |
| 8U, // ANDIS_rec |
| 8U, // ANDI_rec |
| 0U, // ANDI_rec_1_EQ_BIT |
| 0U, // ANDI_rec_1_EQ_BIT8 |
| 0U, // ANDI_rec_1_GT_BIT |
| 0U, // ANDI_rec_1_GT_BIT8 |
| 70U, // AND_rec |
| 0U, // ATOMIC_CMP_SWAP_I16 |
| 0U, // ATOMIC_CMP_SWAP_I32 |
| 0U, // ATOMIC_CMP_SWAP_I64 |
| 0U, // ATOMIC_CMP_SWAP_I8 |
| 0U, // ATOMIC_LOAD_ADD_I16 |
| 0U, // ATOMIC_LOAD_ADD_I32 |
| 0U, // ATOMIC_LOAD_ADD_I64 |
| 0U, // ATOMIC_LOAD_ADD_I8 |
| 0U, // ATOMIC_LOAD_AND_I16 |
| 0U, // ATOMIC_LOAD_AND_I32 |
| 0U, // ATOMIC_LOAD_AND_I64 |
| 0U, // ATOMIC_LOAD_AND_I8 |
| 0U, // ATOMIC_LOAD_MAX_I16 |
| 0U, // ATOMIC_LOAD_MAX_I32 |
| 0U, // ATOMIC_LOAD_MAX_I64 |
| 0U, // ATOMIC_LOAD_MAX_I8 |
| 0U, // ATOMIC_LOAD_MIN_I16 |
| 0U, // ATOMIC_LOAD_MIN_I32 |
| 0U, // ATOMIC_LOAD_MIN_I64 |
| 0U, // ATOMIC_LOAD_MIN_I8 |
| 0U, // ATOMIC_LOAD_NAND_I16 |
| 0U, // ATOMIC_LOAD_NAND_I32 |
| 0U, // ATOMIC_LOAD_NAND_I64 |
| 0U, // ATOMIC_LOAD_NAND_I8 |
| 0U, // ATOMIC_LOAD_OR_I16 |
| 0U, // ATOMIC_LOAD_OR_I32 |
| 0U, // ATOMIC_LOAD_OR_I64 |
| 0U, // ATOMIC_LOAD_OR_I8 |
| 0U, // ATOMIC_LOAD_SUB_I16 |
| 0U, // ATOMIC_LOAD_SUB_I32 |
| 0U, // ATOMIC_LOAD_SUB_I64 |
| 0U, // ATOMIC_LOAD_SUB_I8 |
| 0U, // ATOMIC_LOAD_UMAX_I16 |
| 0U, // ATOMIC_LOAD_UMAX_I32 |
| 0U, // ATOMIC_LOAD_UMAX_I64 |
| 0U, // ATOMIC_LOAD_UMAX_I8 |
| 0U, // ATOMIC_LOAD_UMIN_I16 |
| 0U, // ATOMIC_LOAD_UMIN_I32 |
| 0U, // ATOMIC_LOAD_UMIN_I64 |
| 0U, // ATOMIC_LOAD_UMIN_I8 |
| 0U, // ATOMIC_LOAD_XOR_I16 |
| 0U, // ATOMIC_LOAD_XOR_I32 |
| 0U, // ATOMIC_LOAD_XOR_I64 |
| 0U, // ATOMIC_LOAD_XOR_I8 |
| 0U, // ATOMIC_SWAP_I16 |
| 0U, // ATOMIC_SWAP_I32 |
| 0U, // ATOMIC_SWAP_I64 |
| 0U, // ATOMIC_SWAP_I8 |
| 0U, // ATTN |
| 0U, // B |
| 0U, // BA |
| 0U, // BC |
| 0U, // BCC |
| 0U, // BCCA |
| 0U, // BCCCTR |
| 0U, // BCCCTR8 |
| 0U, // BCCCTRL |
| 0U, // BCCCTRL8 |
| 0U, // BCCL |
| 0U, // BCCLA |
| 0U, // BCCLR |
| 0U, // BCCLRL |
| 0U, // BCCTR |
| 0U, // BCCTR8 |
| 0U, // BCCTR8n |
| 0U, // BCCTRL |
| 0U, // BCCTRL8 |
| 0U, // BCCTRL8n |
| 0U, // BCCTRLn |
| 0U, // BCCTRn |
| 1030U, // BCDADD_rec |
| 74U, // BCDCFN_rec |
| 74U, // BCDCFSQ_rec |
| 74U, // BCDCFZ_rec |
| 70U, // BCDCPSGN_rec |
| 0U, // BCDCTN_rec |
| 0U, // BCDCTSQ_rec |
| 74U, // BCDCTZ_rec |
| 74U, // BCDSETSGN_rec |
| 1030U, // BCDSR_rec |
| 1030U, // BCDSUB_rec |
| 1030U, // BCDS_rec |
| 1030U, // BCDTRUNC_rec |
| 70U, // BCDUS_rec |
| 70U, // BCDUTRUNC_rec |
| 0U, // BCL |
| 0U, // BCLR |
| 0U, // BCLRL |
| 0U, // BCLRLn |
| 0U, // BCLRn |
| 0U, // BCLalways |
| 0U, // BCLn |
| 0U, // BCTR |
| 0U, // BCTR8 |
| 0U, // BCTRL |
| 0U, // BCTRL8 |
| 0U, // BCTRL8_LDinto_toc |
| 0U, // BCTRL8_LDinto_toc_RM |
| 0U, // BCTRL8_RM |
| 0U, // BCTRL_LWZinto_toc |
| 0U, // BCTRL_LWZinto_toc_RM |
| 0U, // BCTRL_RM |
| 0U, // BCn |
| 0U, // BDNZ |
| 0U, // BDNZ8 |
| 0U, // BDNZA |
| 0U, // BDNZAm |
| 0U, // BDNZAp |
| 0U, // BDNZL |
| 0U, // BDNZLA |
| 0U, // BDNZLAm |
| 0U, // BDNZLAp |
| 0U, // BDNZLR |
| 0U, // BDNZLR8 |
| 0U, // BDNZLRL |
| 0U, // BDNZLRLm |
| 0U, // BDNZLRLp |
| 0U, // BDNZLRm |
| 0U, // BDNZLRp |
| 0U, // BDNZLm |
| 0U, // BDNZLp |
| 0U, // BDNZm |
| 0U, // BDNZp |
| 0U, // BDZ |
| 0U, // BDZ8 |
| 0U, // BDZA |
| 0U, // BDZAm |
| 0U, // BDZAp |
| 0U, // BDZL |
| 0U, // BDZLA |
| 0U, // BDZLAm |
| 0U, // BDZLAp |
| 0U, // BDZLR |
| 0U, // BDZLR8 |
| 0U, // BDZLRL |
| 0U, // BDZLRLm |
| 0U, // BDZLRLp |
| 0U, // BDZLRm |
| 0U, // BDZLRp |
| 0U, // BDZLm |
| 0U, // BDZLp |
| 0U, // BDZm |
| 0U, // BDZp |
| 0U, // BL |
| 0U, // BL8 |
| 0U, // BL8_NOP |
| 0U, // BL8_NOP_RM |
| 0U, // BL8_NOP_TLS |
| 0U, // BL8_NOTOC |
| 0U, // BL8_NOTOC_RM |
| 0U, // BL8_NOTOC_TLS |
| 0U, // BL8_RM |
| 0U, // BL8_TLS |
| 0U, // BL8_TLS_ |
| 0U, // BLA |
| 0U, // BLA8 |
| 0U, // BLA8_NOP |
| 0U, // BLA8_NOP_RM |
| 0U, // BLA8_RM |
| 0U, // BLA_RM |
| 0U, // BLR |
| 0U, // BLR8 |
| 0U, // BLRL |
| 0U, // BL_NOP |
| 0U, // BL_NOP_RM |
| 0U, // BL_RM |
| 0U, // BL_TLS |
| 70U, // BPERMD |
| 0U, // BRD |
| 0U, // BRH |
| 0U, // BRH8 |
| 70U, // BRINC |
| 0U, // BRW |
| 0U, // BRW8 |
| 70U, // CFUGED |
| 0U, // CLRBHRB |
| 70U, // CMPB |
| 70U, // CMPB8 |
| 70U, // CMPD |
| 4U, // CMPDI |
| 70U, // CMPEQB |
| 70U, // CMPLD |
| 8U, // CMPLDI |
| 70U, // CMPLW |
| 8U, // CMPLWI |
| 518U, // CMPRB |
| 518U, // CMPRB8 |
| 70U, // CMPW |
| 4U, // CMPWI |
| 0U, // CNTLZD |
| 70U, // CNTLZDM |
| 0U, // CNTLZD_rec |
| 0U, // CNTLZW |
| 0U, // CNTLZW8 |
| 0U, // CNTLZW8_rec |
| 0U, // CNTLZW_rec |
| 0U, // CNTTZD |
| 70U, // CNTTZDM |
| 0U, // CNTTZD_rec |
| 0U, // CNTTZW |
| 0U, // CNTTZW8 |
| 0U, // CNTTZW8_rec |
| 0U, // CNTTZW_rec |
| 0U, // CP_ABORT |
| 0U, // CP_COPY |
| 0U, // CP_COPY8 |
| 74U, // CP_PASTE8_rec |
| 74U, // CP_PASTE_rec |
| 0U, // CR6SET |
| 0U, // CR6UNSET |
| 70U, // CRAND |
| 70U, // CRANDC |
| 70U, // CREQV |
| 70U, // CRNAND |
| 70U, // CRNOR |
| 0U, // CRNOT |
| 70U, // CROR |
| 70U, // CRORC |
| 12U, // CRSET |
| 12U, // CRUNSET |
| 70U, // CRXOR |
| 0U, // CTRL_DEP |
| 0U, // DARN |
| 0U, // DCBA |
| 0U, // DCBF |
| 0U, // DCBFEP |
| 0U, // DCBI |
| 0U, // DCBST |
| 0U, // DCBSTEP |
| 0U, // DCBT |
| 0U, // DCBTEP |
| 0U, // DCBTST |
| 0U, // DCBTSTEP |
| 0U, // DCBZ |
| 0U, // DCBZEP |
| 0U, // DCBZL |
| 0U, // DCBZLEP |
| 0U, // DCCCI |
| 70U, // DIVD |
| 70U, // DIVDE |
| 70U, // DIVDEO |
| 70U, // DIVDEO_rec |
| 70U, // DIVDEU |
| 70U, // DIVDEUO |
| 70U, // DIVDEUO_rec |
| 70U, // DIVDEU_rec |
| 70U, // DIVDE_rec |
| 70U, // DIVDO |
| 70U, // DIVDO_rec |
| 70U, // DIVDU |
| 70U, // DIVDUO |
| 70U, // DIVDUO_rec |
| 70U, // DIVDU_rec |
| 70U, // DIVD_rec |
| 70U, // DIVW |
| 70U, // DIVWE |
| 70U, // DIVWEO |
| 70U, // DIVWEO_rec |
| 70U, // DIVWEU |
| 70U, // DIVWEUO |
| 70U, // DIVWEUO_rec |
| 70U, // DIVWEU_rec |
| 70U, // DIVWE_rec |
| 70U, // DIVWO |
| 70U, // DIVWO_rec |
| 70U, // DIVWU |
| 70U, // DIVWUO |
| 70U, // DIVWUO_rec |
| 70U, // DIVWU_rec |
| 70U, // DIVW_rec |
| 0U, // DMMR |
| 0U, // DMSETDMRZ |
| 0U, // DMXOR |
| 14U, // DMXXEXTFDMR256 |
| 0U, // DMXXEXTFDMR512 |
| 0U, // DMXXEXTFDMR512_HI |
| 14U, // DMXXINSTFDMR256 |
| 134U, // DMXXINSTFDMR512 |
| 198U, // DMXXINSTFDMR512_HI |
| 0U, // DSS |
| 0U, // DSSALL |
| 16U, // DST |
| 16U, // DST64 |
| 16U, // DSTST |
| 16U, // DSTST64 |
| 16U, // DSTSTT |
| 16U, // DSTSTT64 |
| 16U, // DSTT |
| 16U, // DSTT64 |
| 0U, // DYNALLOC |
| 0U, // DYNALLOC8 |
| 0U, // DYNAREAOFFSET |
| 0U, // DYNAREAOFFSET8 |
| 0U, // DecreaseCTR8loop |
| 0U, // DecreaseCTRloop |
| 0U, // EFDABS |
| 70U, // EFDADD |
| 0U, // EFDCFS |
| 0U, // EFDCFSF |
| 0U, // EFDCFSI |
| 0U, // EFDCFSID |
| 0U, // EFDCFUF |
| 0U, // EFDCFUI |
| 0U, // EFDCFUID |
| 70U, // EFDCMPEQ |
| 70U, // EFDCMPGT |
| 70U, // EFDCMPLT |
| 0U, // EFDCTSF |
| 0U, // EFDCTSI |
| 0U, // EFDCTSIDZ |
| 0U, // EFDCTSIZ |
| 0U, // EFDCTUF |
| 0U, // EFDCTUI |
| 0U, // EFDCTUIDZ |
| 0U, // EFDCTUIZ |
| 70U, // EFDDIV |
| 70U, // EFDMUL |
| 0U, // EFDNABS |
| 0U, // EFDNEG |
| 70U, // EFDSUB |
| 70U, // EFDTSTEQ |
| 70U, // EFDTSTGT |
| 70U, // EFDTSTLT |
| 0U, // EFSABS |
| 70U, // EFSADD |
| 0U, // EFSCFD |
| 0U, // EFSCFSF |
| 0U, // EFSCFSI |
| 0U, // EFSCFUF |
| 0U, // EFSCFUI |
| 70U, // EFSCMPEQ |
| 70U, // EFSCMPGT |
| 70U, // EFSCMPLT |
| 0U, // EFSCTSF |
| 0U, // EFSCTSI |
| 0U, // EFSCTSIZ |
| 0U, // EFSCTUF |
| 0U, // EFSCTUI |
| 0U, // EFSCTUIZ |
| 70U, // EFSDIV |
| 70U, // EFSMUL |
| 0U, // EFSNABS |
| 0U, // EFSNEG |
| 70U, // EFSSUB |
| 70U, // EFSTSTEQ |
| 70U, // EFSTSTGT |
| 70U, // EFSTSTLT |
| 0U, // EH_SjLj_LongJmp32 |
| 0U, // EH_SjLj_LongJmp64 |
| 0U, // EH_SjLj_SetJmp32 |
| 0U, // EH_SjLj_SetJmp64 |
| 0U, // EH_SjLj_Setup |
| 70U, // EQV |
| 70U, // EQV8 |
| 70U, // EQV8_rec |
| 70U, // EQV_rec |
| 0U, // EVABS |
| 82U, // EVADDIW |
| 0U, // EVADDSMIAAW |
| 0U, // EVADDSSIAAW |
| 0U, // EVADDUMIAAW |
| 0U, // EVADDUSIAAW |
| 70U, // EVADDW |
| 70U, // EVAND |
| 70U, // EVANDC |
| 70U, // EVCMPEQ |
| 70U, // EVCMPGTS |
| 70U, // EVCMPGTU |
| 70U, // EVCMPLTS |
| 70U, // EVCMPLTU |
| 0U, // EVCNTLSW |
| 0U, // EVCNTLZW |
| 70U, // EVDIVWS |
| 70U, // EVDIVWU |
| 70U, // EVEQV |
| 0U, // EVEXTSB |
| 0U, // EVEXTSH |
| 0U, // EVFSABS |
| 70U, // EVFSADD |
| 0U, // EVFSCFSF |
| 0U, // EVFSCFSI |
| 0U, // EVFSCFUF |
| 0U, // EVFSCFUI |
| 70U, // EVFSCMPEQ |
| 70U, // EVFSCMPGT |
| 70U, // EVFSCMPLT |
| 0U, // EVFSCTSF |
| 0U, // EVFSCTSI |
| 0U, // EVFSCTSIZ |
| 0U, // EVFSCTUF |
| 0U, // EVFSCTUI |
| 0U, // EVFSCTUIZ |
| 70U, // EVFSDIV |
| 70U, // EVFSMUL |
| 0U, // EVFSNABS |
| 0U, // EVFSNEG |
| 70U, // EVFSSUB |
| 70U, // EVFSTSTEQ |
| 70U, // EVFSTSTGT |
| 70U, // EVFSTSTLT |
| 0U, // EVLDD |
| 0U, // EVLDDX |
| 0U, // EVLDH |
| 0U, // EVLDHX |
| 0U, // EVLDW |
| 0U, // EVLDWX |
| 0U, // EVLHHESPLAT |
| 0U, // EVLHHESPLATX |
| 0U, // EVLHHOSSPLAT |
| 0U, // EVLHHOSSPLATX |
| 0U, // EVLHHOUSPLAT |
| 0U, // EVLHHOUSPLATX |
| 0U, // EVLWHE |
| 0U, // EVLWHEX |
| 0U, // EVLWHOS |
| 0U, // EVLWHOSX |
| 0U, // EVLWHOU |
| 0U, // EVLWHOUX |
| 0U, // EVLWHSPLAT |
| 0U, // EVLWHSPLATX |
| 0U, // EVLWWSPLAT |
| 0U, // EVLWWSPLATX |
| 70U, // EVMERGEHI |
| 70U, // EVMERGEHILO |
| 70U, // EVMERGELO |
| 70U, // EVMERGELOHI |
| 70U, // EVMHEGSMFAA |
| 70U, // EVMHEGSMFAN |
| 70U, // EVMHEGSMIAA |
| 70U, // EVMHEGSMIAN |
| 70U, // EVMHEGUMIAA |
| 70U, // EVMHEGUMIAN |
| 70U, // EVMHESMF |
| 70U, // EVMHESMFA |
| 70U, // EVMHESMFAAW |
| 70U, // EVMHESMFANW |
| 70U, // EVMHESMI |
| 70U, // EVMHESMIA |
| 70U, // EVMHESMIAAW |
| 70U, // EVMHESMIANW |
| 70U, // EVMHESSF |
| 70U, // EVMHESSFA |
| 70U, // EVMHESSFAAW |
| 70U, // EVMHESSFANW |
| 70U, // EVMHESSIAAW |
| 70U, // EVMHESSIANW |
| 70U, // EVMHEUMI |
| 70U, // EVMHEUMIA |
| 70U, // EVMHEUMIAAW |
| 70U, // EVMHEUMIANW |
| 70U, // EVMHEUSIAAW |
| 70U, // EVMHEUSIANW |
| 70U, // EVMHOGSMFAA |
| 70U, // EVMHOGSMFAN |
| 70U, // EVMHOGSMIAA |
| 70U, // EVMHOGSMIAN |
| 70U, // EVMHOGUMIAA |
| 70U, // EVMHOGUMIAN |
| 70U, // EVMHOSMF |
| 70U, // EVMHOSMFA |
| 70U, // EVMHOSMFAAW |
| 70U, // EVMHOSMFANW |
| 70U, // EVMHOSMI |
| 70U, // EVMHOSMIA |
| 70U, // EVMHOSMIAAW |
| 70U, // EVMHOSMIANW |
| 70U, // EVMHOSSF |
| 70U, // EVMHOSSFA |
| 70U, // EVMHOSSFAAW |
| 70U, // EVMHOSSFANW |
| 70U, // EVMHOSSIAAW |
| 70U, // EVMHOSSIANW |
| 70U, // EVMHOUMI |
| 70U, // EVMHOUMIA |
| 70U, // EVMHOUMIAAW |
| 70U, // EVMHOUMIANW |
| 70U, // EVMHOUSIAAW |
| 70U, // EVMHOUSIANW |
| 0U, // EVMRA |
| 70U, // EVMWHSMF |
| 70U, // EVMWHSMFA |
| 70U, // EVMWHSMI |
| 70U, // EVMWHSMIA |
| 70U, // EVMWHSSF |
| 70U, // EVMWHSSFA |
| 70U, // EVMWHUMI |
| 70U, // EVMWHUMIA |
| 70U, // EVMWLSMIAAW |
| 70U, // EVMWLSMIANW |
| 70U, // EVMWLSSIAAW |
| 70U, // EVMWLSSIANW |
| 70U, // EVMWLUMI |
| 70U, // EVMWLUMIA |
| 70U, // EVMWLUMIAAW |
| 70U, // EVMWLUMIANW |
| 70U, // EVMWLUSIAAW |
| 70U, // EVMWLUSIANW |
| 70U, // EVMWSMF |
| 70U, // EVMWSMFA |
| 70U, // EVMWSMFAA |
| 70U, // EVMWSMFAN |
| 70U, // EVMWSMI |
| 70U, // EVMWSMIA |
| 70U, // EVMWSMIAA |
| 70U, // EVMWSMIAN |
| 70U, // EVMWSSF |
| 70U, // EVMWSSFA |
| 70U, // EVMWSSFAA |
| 70U, // EVMWSSFAN |
| 70U, // EVMWUMI |
| 70U, // EVMWUMIA |
| 70U, // EVMWUMIAA |
| 70U, // EVMWUMIAN |
| 70U, // EVNAND |
| 0U, // EVNEG |
| 70U, // EVNOR |
| 70U, // EVOR |
| 70U, // EVORC |
| 70U, // EVRLW |
| 66U, // EVRLWI |
| 0U, // EVRNDW |
| 0U, // EVSEL |
| 70U, // EVSLW |
| 66U, // EVSLWI |
| 0U, // EVSPLATFI |
| 0U, // EVSPLATI |
| 66U, // EVSRWIS |
| 66U, // EVSRWIU |
| 70U, // EVSRWS |
| 70U, // EVSRWU |
| 0U, // EVSTDD |
| 0U, // EVSTDDX |
| 0U, // EVSTDH |
| 0U, // EVSTDHX |
| 0U, // EVSTDW |
| 0U, // EVSTDWX |
| 0U, // EVSTWHE |
| 0U, // EVSTWHEX |
| 0U, // EVSTWHO |
| 0U, // EVSTWHOX |
| 0U, // EVSTWWE |
| 0U, // EVSTWWEX |
| 0U, // EVSTWWO |
| 0U, // EVSTWWOX |
| 0U, // EVSUBFSMIAAW |
| 0U, // EVSUBFSSIAAW |
| 0U, // EVSUBFUMIAAW |
| 0U, // EVSUBFUSIAAW |
| 70U, // EVSUBFW |
| 70U, // EVSUBIFW |
| 70U, // EVXOR |
| 0U, // EXTSB |
| 0U, // EXTSB8 |
| 0U, // EXTSB8_32_64 |
| 0U, // EXTSB8_rec |
| 0U, // EXTSB_rec |
| 0U, // EXTSH |
| 0U, // EXTSH8 |
| 0U, // EXTSH8_32_64 |
| 0U, // EXTSH8_rec |
| 0U, // EXTSH_rec |
| 0U, // EXTSW |
| 64U, // EXTSWSLI |
| 64U, // EXTSWSLI_32_64 |
| 64U, // EXTSWSLI_32_64_rec |
| 64U, // EXTSWSLI_rec |
| 0U, // EXTSW_32 |
| 0U, // EXTSW_32_64 |
| 0U, // EXTSW_32_64_rec |
| 0U, // EXTSW_rec |
| 0U, // EnforceIEIO |
| 0U, // FABSD |
| 0U, // FABSD_rec |
| 0U, // FABSS |
| 0U, // FABSS_rec |
| 70U, // FADD |
| 70U, // FADDS |
| 70U, // FADDS_rec |
| 70U, // FADD_rec |
| 0U, // FADDrtz |
| 0U, // FCFID |
| 0U, // FCFIDS |
| 0U, // FCFIDS_rec |
| 0U, // FCFIDU |
| 0U, // FCFIDUS |
| 0U, // FCFIDUS_rec |
| 0U, // FCFIDU_rec |
| 0U, // FCFID_rec |
| 70U, // FCMPOD |
| 70U, // FCMPOS |
| 70U, // FCMPUD |
| 70U, // FCMPUS |
| 70U, // FCPSGND |
| 70U, // FCPSGND_rec |
| 70U, // FCPSGNS |
| 70U, // FCPSGNS_rec |
| 0U, // FCTID |
| 0U, // FCTIDU |
| 0U, // FCTIDUZ |
| 0U, // FCTIDUZ_rec |
| 0U, // FCTIDU_rec |
| 0U, // FCTIDZ |
| 0U, // FCTIDZ_rec |
| 0U, // FCTID_rec |
| 0U, // FCTIW |
| 0U, // FCTIWU |
| 0U, // FCTIWUZ |
| 0U, // FCTIWUZ_rec |
| 0U, // FCTIWU_rec |
| 0U, // FCTIWZ |
| 0U, // FCTIWZ_rec |
| 0U, // FCTIW_rec |
| 70U, // FDIV |
| 70U, // FDIVS |
| 70U, // FDIVS_rec |
| 70U, // FDIV_rec |
| 518U, // FMADD |
| 518U, // FMADDS |
| 518U, // FMADDS_rec |
| 518U, // FMADD_rec |
| 0U, // FMR |
| 0U, // FMR_rec |
| 518U, // FMSUB |
| 518U, // FMSUBS |
| 518U, // FMSUBS_rec |
| 518U, // FMSUB_rec |
| 70U, // FMUL |
| 70U, // FMULS |
| 70U, // FMULS_rec |
| 70U, // FMUL_rec |
| 0U, // FNABSD |
| 0U, // FNABSD_rec |
| 0U, // FNABSS |
| 0U, // FNABSS_rec |
| 0U, // FNEGD |
| 0U, // FNEGD_rec |
| 0U, // FNEGS |
| 0U, // FNEGS_rec |
| 518U, // FNMADD |
| 518U, // FNMADDS |
| 518U, // FNMADDS_rec |
| 518U, // FNMADD_rec |
| 518U, // FNMSUB |
| 518U, // FNMSUBS |
| 518U, // FNMSUBS_rec |
| 518U, // FNMSUB_rec |
| 0U, // FRE |
| 0U, // FRES |
| 0U, // FRES_rec |
| 0U, // FRE_rec |
| 0U, // FRIMD |
| 0U, // FRIMD_rec |
| 0U, // FRIMS |
| 0U, // FRIMS_rec |
| 0U, // FRIND |
| 0U, // FRIND_rec |
| 0U, // FRINS |
| 0U, // FRINS_rec |
| 0U, // FRIPD |
| 0U, // FRIPD_rec |
| 0U, // FRIPS |
| 0U, // FRIPS_rec |
| 0U, // FRIZD |
| 0U, // FRIZD_rec |
| 0U, // FRIZS |
| 0U, // FRIZS_rec |
| 0U, // FRSP |
| 0U, // FRSP_rec |
| 0U, // FRSQRTE |
| 0U, // FRSQRTES |
| 0U, // FRSQRTES_rec |
| 0U, // FRSQRTE_rec |
| 518U, // FSELD |
| 518U, // FSELD_rec |
| 518U, // FSELS |
| 518U, // FSELS_rec |
| 0U, // FSQRT |
| 0U, // FSQRTS |
| 0U, // FSQRTS_rec |
| 0U, // FSQRT_rec |
| 70U, // FSUB |
| 70U, // FSUBS |
| 70U, // FSUBS_rec |
| 70U, // FSUB_rec |
| 70U, // FTDIV |
| 0U, // FTSQRT |
| 0U, // GETtlsADDR |
| 0U, // GETtlsADDR32 |
| 0U, // GETtlsADDR32AIX |
| 0U, // GETtlsADDR64AIX |
| 0U, // GETtlsADDRPCREL |
| 0U, // GETtlsldADDR |
| 0U, // GETtlsldADDR32 |
| 0U, // GETtlsldADDRPCREL |
| 0U, // HASHCHK |
| 0U, // HASHCHK8 |
| 0U, // HASHCHKP |
| 0U, // HASHCHKP8 |
| 0U, // HASHST |
| 0U, // HASHST8 |
| 0U, // HASHSTP |
| 0U, // HASHSTP8 |
| 0U, // HRFID |
| 0U, // ICBI |
| 0U, // ICBIEP |
| 0U, // ICBLC |
| 0U, // ICBLQ |
| 0U, // ICBT |
| 0U, // ICBTLS |
| 0U, // ICCCI |
| 518U, // ISEL |
| 518U, // ISEL8 |
| 0U, // ISYNC |
| 0U, // LA |
| 0U, // LA8 |
| 0U, // LBARX |
| 1U, // LBARXL |
| 0U, // LBEPX |
| 0U, // LBZ |
| 0U, // LBZ8 |
| 70U, // LBZCIX |
| 0U, // LBZU |
| 0U, // LBZU8 |
| 0U, // LBZUX |
| 0U, // LBZUX8 |
| 0U, // LBZX |
| 0U, // LBZX8 |
| 70U, // LBZXTLS |
| 70U, // LBZXTLS_ |
| 70U, // LBZXTLS_32 |
| 0U, // LD |
| 0U, // LDARX |
| 1U, // LDARXL |
| 66U, // LDAT |
| 0U, // LDBRX |
| 70U, // LDCIX |
| 0U, // LDU |
| 0U, // LDUX |
| 0U, // LDX |
| 70U, // LDXTLS |
| 70U, // LDXTLS_ |
| 0U, // LDgotTprelL |
| 0U, // LDgotTprelL32 |
| 0U, // LDtoc |
| 0U, // LDtocBA |
| 0U, // LDtocCPT |
| 0U, // LDtocJTI |
| 0U, // LDtocL |
| 0U, // LFD |
| 0U, // LFDEPX |
| 0U, // LFDU |
| 0U, // LFDUX |
| 0U, // LFDX |
| 0U, // LFIWAX |
| 0U, // LFIWZX |
| 0U, // LFS |
| 0U, // LFSU |
| 0U, // LFSUX |
| 0U, // LFSX |
| 0U, // LHA |
| 0U, // LHA8 |
| 0U, // LHARX |
| 1U, // LHARXL |
| 0U, // LHAU |
| 0U, // LHAU8 |
| 0U, // LHAUX |
| 0U, // LHAUX8 |
| 0U, // LHAX |
| 0U, // LHAX8 |
| 0U, // LHBRX |
| 0U, // LHBRX8 |
| 0U, // LHEPX |
| 0U, // LHZ |
| 0U, // LHZ8 |
| 70U, // LHZCIX |
| 0U, // LHZU |
| 0U, // LHZU8 |
| 0U, // LHZUX |
| 0U, // LHZUX8 |
| 0U, // LHZX |
| 0U, // LHZX8 |
| 70U, // LHZXTLS |
| 70U, // LHZXTLS_ |
| 70U, // LHZXTLS_32 |
| 0U, // LI |
| 0U, // LI8 |
| 0U, // LIS |
| 0U, // LIS8 |
| 0U, // LMW |
| 0U, // LQ |
| 0U, // LQARX |
| 1U, // LQARXL |
| 0U, // LQX_PSEUDO |
| 66U, // LSWI |
| 0U, // LVEBX |
| 0U, // LVEHX |
| 0U, // LVEWX |
| 0U, // LVSL |
| 0U, // LVSR |
| 0U, // LVX |
| 0U, // LVXL |
| 0U, // LWA |
| 0U, // LWARX |
| 1U, // LWARXL |
| 66U, // LWAT |
| 0U, // LWAUX |
| 0U, // LWAX |
| 0U, // LWAX_32 |
| 0U, // LWA_32 |
| 0U, // LWBRX |
| 0U, // LWBRX8 |
| 0U, // LWEPX |
| 0U, // LWZ |
| 0U, // LWZ8 |
| 70U, // LWZCIX |
| 0U, // LWZU |
| 0U, // LWZU8 |
| 0U, // LWZUX |
| 0U, // LWZUX8 |
| 0U, // LWZX |
| 0U, // LWZX8 |
| 70U, // LWZXTLS |
| 70U, // LWZXTLS_ |
| 70U, // LWZXTLS_32 |
| 0U, // LWZtoc |
| 0U, // LWZtocL |
| 0U, // LXSD |
| 0U, // LXSDX |
| 0U, // LXSIBZX |
| 0U, // LXSIHZX |
| 0U, // LXSIWAX |
| 0U, // LXSIWZX |
| 0U, // LXSSP |
| 0U, // LXSSPX |
| 0U, // LXV |
| 0U, // LXVB16X |
| 0U, // LXVD2X |
| 0U, // LXVDSX |
| 0U, // LXVH8X |
| 0U, // LXVKQ |
| 70U, // LXVL |
| 70U, // LXVLL |
| 0U, // LXVP |
| 70U, // LXVPRL |
| 70U, // LXVPRLL |
| 0U, // LXVPX |
| 0U, // LXVRBX |
| 0U, // LXVRDX |
| 0U, // LXVRHX |
| 70U, // LXVRL |
| 70U, // LXVRLL |
| 0U, // LXVRWX |
| 0U, // LXVW4X |
| 0U, // LXVWSX |
| 0U, // LXVX |
| 518U, // MADDHD |
| 518U, // MADDHDU |
| 518U, // MADDLD |
| 518U, // MADDLD8 |
| 0U, // MBAR |
| 0U, // MCRF |
| 0U, // MCRFS |
| 0U, // MCRXRX |
| 0U, // MFBHRBE |
| 0U, // MFCR |
| 0U, // MFCR8 |
| 0U, // MFCTR |
| 0U, // MFCTR8 |
| 0U, // MFDCR |
| 0U, // MFFS |
| 0U, // MFFSCDRN |
| 0U, // MFFSCDRNI |
| 0U, // MFFSCE |
| 0U, // MFFSCRN |
| 0U, // MFFSCRNI |
| 0U, // MFFSL |
| 0U, // MFFS_rec |
| 0U, // MFLR |
| 0U, // MFLR8 |
| 0U, // MFMSR |
| 0U, // MFOCRF |
| 0U, // MFOCRF8 |
| 0U, // MFPMR |
| 0U, // MFSPR |
| 0U, // MFSPR8 |
| 0U, // MFSR |
| 0U, // MFSRIN |
| 0U, // MFTB |
| 0U, // MFTB8 |
| 0U, // MFUDSCR |
| 0U, // MFVRD |
| 0U, // MFVRSAVE |
| 0U, // MFVRSAVEv |
| 0U, // MFVRWZ |
| 0U, // MFVSCR |
| 0U, // MFVSRD |
| 0U, // MFVSRLD |
| 0U, // MFVSRWZ |
| 70U, // MODSD |
| 70U, // MODSW |
| 70U, // MODUD |
| 70U, // MODUW |
| 0U, // MSGSYNC |
| 0U, // MSYNC |
| 0U, // MTCRF |
| 0U, // MTCRF8 |
| 0U, // MTCTR |
| 0U, // MTCTR8 |
| 0U, // MTCTR8loop |
| 0U, // MTCTRloop |
| 0U, // MTDCR |
| 0U, // MTFSB0 |
| 0U, // MTFSB1 |
| 522U, // MTFSF |
| 0U, // MTFSFI |
| 0U, // MTFSFI_rec |
| 0U, // MTFSFIb |
| 522U, // MTFSF_rec |
| 0U, // MTFSFb |
| 0U, // MTLR |
| 0U, // MTLR8 |
| 0U, // MTMSR |
| 0U, // MTMSRD |
| 0U, // MTOCRF |
| 0U, // MTOCRF8 |
| 0U, // MTPMR |
| 0U, // MTSPR |
| 0U, // MTSPR8 |
| 0U, // MTSR |
| 0U, // MTSRIN |
| 0U, // MTUDSCR |
| 0U, // MTVRD |
| 0U, // MTVRSAVE |
| 0U, // MTVRSAVEv |
| 0U, // MTVRWA |
| 0U, // MTVRWZ |
| 0U, // MTVSCR |
| 0U, // MTVSRBM |
| 0U, // MTVSRBMI |
| 0U, // MTVSRD |
| 70U, // MTVSRDD |
| 0U, // MTVSRDM |
| 0U, // MTVSRHM |
| 0U, // MTVSRQM |
| 0U, // MTVSRWA |
| 0U, // MTVSRWM |
| 0U, // MTVSRWS |
| 0U, // MTVSRWZ |
| 70U, // MULHD |
| 70U, // MULHDU |
| 70U, // MULHDU_rec |
| 70U, // MULHD_rec |
| 70U, // MULHW |
| 70U, // MULHWU |
| 70U, // MULHWU_rec |
| 70U, // MULHW_rec |
| 70U, // MULLD |
| 70U, // MULLDO |
| 70U, // MULLDO_rec |
| 70U, // MULLD_rec |
| 4U, // MULLI |
| 4U, // MULLI8 |
| 70U, // MULLW |
| 70U, // MULLWO |
| 70U, // MULLWO_rec |
| 70U, // MULLW_rec |
| 0U, // MoveGOTtoLR |
| 0U, // MovePCtoLR |
| 0U, // MovePCtoLR8 |
| 70U, // NAND |
| 70U, // NAND8 |
| 70U, // NAND8_rec |
| 70U, // NAND_rec |
| 0U, // NAP |
| 0U, // NEG |
| 0U, // NEG8 |
| 0U, // NEG8O |
| 0U, // NEG8O_rec |
| 0U, // NEG8_rec |
| 0U, // NEGO |
| 0U, // NEGO_rec |
| 0U, // NEG_rec |
| 0U, // NOP |
| 0U, // NOP_GT_PWR6 |
| 0U, // NOP_GT_PWR7 |
| 70U, // NOR |
| 70U, // NOR8 |
| 70U, // NOR8_rec |
| 70U, // NOR_rec |
| 70U, // OR |
| 70U, // OR8 |
| 70U, // OR8_rec |
| 70U, // ORC |
| 70U, // ORC8 |
| 70U, // ORC8_rec |
| 70U, // ORC_rec |
| 8U, // ORI |
| 8U, // ORI8 |
| 8U, // ORIS |
| 8U, // ORIS8 |
| 70U, // OR_rec |
| 20U, // PADDI |
| 20U, // PADDI8 |
| 0U, // PADDI8pc |
| 0U, // PADDIdtprel |
| 0U, // PADDIpc |
| 70U, // PDEPD |
| 70U, // PEXTD |
| 0U, // PLBZ |
| 0U, // PLBZ8 |
| 0U, // PLBZ8pc |
| 0U, // PLBZpc |
| 0U, // PLD |
| 0U, // PLDpc |
| 0U, // PLFD |
| 0U, // PLFDpc |
| 0U, // PLFS |
| 0U, // PLFSpc |
| 0U, // PLHA |
| 0U, // PLHA8 |
| 0U, // PLHA8pc |
| 0U, // PLHApc |
| 0U, // PLHZ |
| 0U, // PLHZ8 |
| 0U, // PLHZ8pc |
| 0U, // PLHZpc |
| 0U, // PLI |
| 0U, // PLI8 |
| 0U, // PLWA |
| 0U, // PLWA8 |
| 0U, // PLWA8pc |
| 0U, // PLWApc |
| 0U, // PLWZ |
| 0U, // PLWZ8 |
| 0U, // PLWZ8pc |
| 0U, // PLWZpc |
| 0U, // PLXSD |
| 0U, // PLXSDpc |
| 0U, // PLXSSP |
| 0U, // PLXSSPpc |
| 0U, // PLXV |
| 0U, // PLXVP |
| 0U, // PLXVPpc |
| 0U, // PLXVpc |
| 5382U, // PMXVBF16GER2 |
| 26134U, // PMXVBF16GER2NN |
| 26134U, // PMXVBF16GER2NP |
| 26134U, // PMXVBF16GER2PN |
| 26134U, // PMXVBF16GER2PP |
| 5382U, // PMXVBF16GER2W |
| 26134U, // PMXVBF16GER2WNN |
| 26134U, // PMXVBF16GER2WNP |
| 26134U, // PMXVBF16GER2WPN |
| 26134U, // PMXVBF16GER2WPP |
| 5382U, // PMXVF16GER2 |
| 26134U, // PMXVF16GER2NN |
| 26134U, // PMXVF16GER2NP |
| 26134U, // PMXVF16GER2PN |
| 26134U, // PMXVF16GER2PP |
| 5382U, // PMXVF16GER2W |
| 26134U, // PMXVF16GER2WNN |
| 26134U, // PMXVF16GER2WNP |
| 26134U, // PMXVF16GER2WPN |
| 26134U, // PMXVF16GER2WPP |
| 5382U, // PMXVF32GER |
| 42518U, // PMXVF32GERNN |
| 42518U, // PMXVF32GERNP |
| 42518U, // PMXVF32GERPN |
| 42518U, // PMXVF32GERPP |
| 5382U, // PMXVF32GERW |
| 42518U, // PMXVF32GERWNN |
| 42518U, // PMXVF32GERWNP |
| 42518U, // PMXVF32GERWPN |
| 42518U, // PMXVF32GERWPP |
| 54534U, // PMXVF64GER |
| 13846U, // PMXVF64GERNN |
| 13846U, // PMXVF64GERNP |
| 13846U, // PMXVF64GERPN |
| 13846U, // PMXVF64GERPP |
| 54534U, // PMXVF64GERW |
| 13846U, // PMXVF64GERWNN |
| 13846U, // PMXVF64GERWNP |
| 13846U, // PMXVF64GERWPN |
| 13846U, // PMXVF64GERWPP |
| 5382U, // PMXVI16GER2 |
| 26134U, // PMXVI16GER2PP |
| 5382U, // PMXVI16GER2S |
| 26134U, // PMXVI16GER2SPP |
| 5382U, // PMXVI16GER2SW |
| 26134U, // PMXVI16GER2SWPP |
| 5382U, // PMXVI16GER2W |
| 26134U, // PMXVI16GER2WPP |
| 5382U, // PMXVI4GER8 |
| 26134U, // PMXVI4GER8PP |
| 5382U, // PMXVI4GER8W |
| 26134U, // PMXVI4GER8WPP |
| 5382U, // PMXVI8GER4 |
| 26134U, // PMXVI8GER4PP |
| 26134U, // PMXVI8GER4SPP |
| 5382U, // PMXVI8GER4W |
| 26134U, // PMXVI8GER4WPP |
| 26134U, // PMXVI8GER4WSPP |
| 0U, // POPCNTB |
| 0U, // POPCNTB8 |
| 0U, // POPCNTD |
| 0U, // POPCNTW |
| 0U, // PPC32GOT |
| 0U, // PPC32PICGOT |
| 0U, // PREPARE_PROBED_ALLOCA_32 |
| 0U, // PREPARE_PROBED_ALLOCA_64 |
| 0U, // PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_32 |
| 0U, // PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_64 |
| 0U, // PROBED_ALLOCA_32 |
| 0U, // PROBED_ALLOCA_64 |
| 0U, // PROBED_STACKALLOC_32 |
| 0U, // PROBED_STACKALLOC_64 |
| 0U, // PSTB |
| 0U, // PSTB8 |
| 0U, // PSTB8pc |
| 0U, // PSTBpc |
| 0U, // PSTD |
| 0U, // PSTDpc |
| 0U, // PSTFD |
| 0U, // PSTFDpc |
| 0U, // PSTFS |
| 0U, // PSTFSpc |
| 0U, // PSTH |
| 0U, // PSTH8 |
| 0U, // PSTH8pc |
| 0U, // PSTHpc |
| 0U, // PSTW |
| 0U, // PSTW8 |
| 0U, // PSTW8pc |
| 0U, // PSTWpc |
| 0U, // PSTXSD |
| 0U, // PSTXSDpc |
| 0U, // PSTXSSP |
| 0U, // PSTXSSPpc |
| 0U, // PSTXV |
| 0U, // PSTXVP |
| 0U, // PSTXVPpc |
| 0U, // PSTXVpc |
| 0U, // PseudoEIEIO |
| 0U, // RESTORE_ACC |
| 0U, // RESTORE_CR |
| 0U, // RESTORE_CRBIT |
| 0U, // RESTORE_QUADWORD |
| 0U, // RESTORE_UACC |
| 0U, // RESTORE_WACC |
| 0U, // RFCI |
| 0U, // RFDI |
| 0U, // RFEBB |
| 0U, // RFI |
| 0U, // RFID |
| 0U, // RFMCI |
| 6U, // RLDCL |
| 6U, // RLDCL_rec |
| 6U, // RLDCR |
| 6U, // RLDCR_rec |
| 0U, // RLDIC |
| 0U, // RLDICL |
| 0U, // RLDICL_32 |
| 0U, // RLDICL_32_64 |
| 0U, // RLDICL_32_rec |
| 0U, // RLDICL_rec |
| 0U, // RLDICR |
| 0U, // RLDICR_32 |
| 0U, // RLDICR_rec |
| 0U, // RLDIC_rec |
| 24U, // RLDIMI |
| 24U, // RLDIMI_rec |
| 26U, // RLWIMI |
| 26U, // RLWIMI8 |
| 26U, // RLWIMI8_rec |
| 26U, // RLWIMI_rec |
| 4354U, // RLWINM |
| 4354U, // RLWINM8 |
| 4354U, // RLWINM8_rec |
| 4354U, // RLWINM_rec |
| 4358U, // RLWNM |
| 4358U, // RLWNM8 |
| 4358U, // RLWNM8_rec |
| 4358U, // RLWNM_rec |
| 0U, // ReadTB |
| 0U, // SC |
| 0U, // SELECT_CC_F16 |
| 0U, // SELECT_CC_F4 |
| 0U, // SELECT_CC_F8 |
| 0U, // SELECT_CC_I4 |
| 0U, // SELECT_CC_I8 |
| 0U, // SELECT_CC_SPE |
| 0U, // SELECT_CC_SPE4 |
| 0U, // SELECT_CC_VRRC |
| 0U, // SELECT_CC_VSFRC |
| 0U, // SELECT_CC_VSRC |
| 0U, // SELECT_CC_VSSRC |
| 0U, // SELECT_F16 |
| 0U, // SELECT_F4 |
| 0U, // SELECT_F8 |
| 0U, // SELECT_I4 |
| 0U, // SELECT_I8 |
| 0U, // SELECT_SPE |
| 0U, // SELECT_SPE4 |
| 0U, // SELECT_VRRC |
| 0U, // SELECT_VSFRC |
| 0U, // SELECT_VSRC |
| 0U, // SELECT_VSSRC |
| 0U, // SETB |
| 0U, // SETB8 |
| 0U, // SETBC |
| 0U, // SETBC8 |
| 0U, // SETBCR |
| 0U, // SETBCR8 |
| 0U, // SETFLM |
| 0U, // SETNBC |
| 0U, // SETNBC8 |
| 0U, // SETNBCR |
| 0U, // SETNBCR8 |
| 0U, // SETRND |
| 0U, // SETRNDi |
| 0U, // SLBFEE_rec |
| 0U, // SLBIA |
| 0U, // SLBIE |
| 0U, // SLBIEG |
| 0U, // SLBMFEE |
| 0U, // SLBMFEV |
| 0U, // SLBMTE |
| 0U, // SLBSYNC |
| 70U, // SLD |
| 70U, // SLD_rec |
| 70U, // SLW |
| 70U, // SLW8 |
| 70U, // SLW8_rec |
| 70U, // SLW_rec |
| 0U, // SPELWZ |
| 0U, // SPELWZX |
| 0U, // SPESTW |
| 0U, // SPESTWX |
| 0U, // SPILL_ACC |
| 0U, // SPILL_CR |
| 0U, // SPILL_CRBIT |
| 0U, // SPILL_QUADWORD |
| 0U, // SPILL_UACC |
| 0U, // SPILL_WACC |
| 0U, // SPLIT_QUADWORD |
| 70U, // SRAD |
| 64U, // SRADI |
| 64U, // SRADI_32 |
| 64U, // SRADI_rec |
| 70U, // SRAD_rec |
| 70U, // SRAW |
| 66U, // SRAWI |
| 66U, // SRAWI_rec |
| 70U, // SRAW_rec |
| 70U, // SRD |
| 70U, // SRD_rec |
| 70U, // SRW |
| 70U, // SRW8 |
| 70U, // SRW8_rec |
| 70U, // SRW_rec |
| 0U, // STB |
| 0U, // STB8 |
| 70U, // STBCIX |
| 0U, // STBCX |
| 0U, // STBEPX |
| 0U, // STBU |
| 0U, // STBU8 |
| 0U, // STBUX |
| 0U, // STBUX8 |
| 0U, // STBX |
| 0U, // STBX8 |
| 70U, // STBXTLS |
| 70U, // STBXTLS_ |
| 70U, // STBXTLS_32 |
| 0U, // STD |
| 66U, // STDAT |
| 0U, // STDBRX |
| 70U, // STDCIX |
| 0U, // STDCX |
| 0U, // STDU |
| 0U, // STDUX |
| 0U, // STDX |
| 70U, // STDXTLS |
| 70U, // STDXTLS_ |
| 0U, // STFD |
| 0U, // STFDEPX |
| 0U, // STFDU |
| 0U, // STFDUX |
| 0U, // STFDX |
| 0U, // STFIWX |
| 0U, // STFS |
| 0U, // STFSU |
| 0U, // STFSUX |
| 0U, // STFSX |
| 0U, // STH |
| 0U, // STH8 |
| 0U, // STHBRX |
| 70U, // STHCIX |
| 0U, // STHCX |
| 0U, // STHEPX |
| 0U, // STHU |
| 0U, // STHU8 |
| 0U, // STHUX |
| 0U, // STHUX8 |
| 0U, // STHX |
| 0U, // STHX8 |
| 70U, // STHXTLS |
| 70U, // STHXTLS_ |
| 70U, // STHXTLS_32 |
| 0U, // STMW |
| 0U, // STOP |
| 0U, // STQ |
| 0U, // STQCX |
| 0U, // STQX_PSEUDO |
| 66U, // STSWI |
| 0U, // STVEBX |
| 0U, // STVEHX |
| 0U, // STVEWX |
| 0U, // STVX |
| 0U, // STVXL |
| 0U, // STW |
| 0U, // STW8 |
| 66U, // STWAT |
| 0U, // STWBRX |
| 70U, // STWCIX |
| 0U, // STWCX |
| 0U, // STWEPX |
| 0U, // STWU |
| 0U, // STWU8 |
| 0U, // STWUX |
| 0U, // STWUX8 |
| 0U, // STWX |
| 0U, // STWX8 |
| 70U, // STWXTLS |
| 70U, // STWXTLS_ |
| 70U, // STWXTLS_32 |
| 0U, // STXSD |
| 0U, // STXSDX |
| 0U, // STXSIBX |
| 0U, // STXSIBXv |
| 0U, // STXSIHX |
| 0U, // STXSIHXv |
| 0U, // STXSIWX |
| 0U, // STXSSP |
| 0U, // STXSSPX |
| 0U, // STXV |
| 0U, // STXVB16X |
| 0U, // STXVD2X |
| 0U, // STXVH8X |
| 70U, // STXVL |
| 70U, // STXVLL |
| 0U, // STXVP |
| 70U, // STXVPRL |
| 70U, // STXVPRLL |
| 0U, // STXVPX |
| 0U, // STXVRBX |
| 0U, // STXVRDX |
| 0U, // STXVRHX |
| 70U, // STXVRL |
| 70U, // STXVRLL |
| 0U, // STXVRWX |
| 0U, // STXVW4X |
| 0U, // STXVX |
| 70U, // SUBF |
| 70U, // SUBF8 |
| 70U, // SUBF8O |
| 70U, // SUBF8O_rec |
| 70U, // SUBF8_rec |
| 70U, // SUBFC |
| 70U, // SUBFC8 |
| 70U, // SUBFC8O |
| 70U, // SUBFC8O_rec |
| 70U, // SUBFC8_rec |
| 70U, // SUBFCO |
| 70U, // SUBFCO_rec |
| 70U, // SUBFC_rec |
| 70U, // SUBFE |
| 70U, // SUBFE8 |
| 70U, // SUBFE8O |
| 70U, // SUBFE8O_rec |
| 70U, // SUBFE8_rec |
| 70U, // SUBFEO |
| 70U, // SUBFEO_rec |
| 70U, // SUBFE_rec |
| 4U, // SUBFIC |
| 4U, // SUBFIC8 |
| 0U, // SUBFME |
| 0U, // SUBFME8 |
| 0U, // SUBFME8O |
| 0U, // SUBFME8O_rec |
| 0U, // SUBFME8_rec |
| 0U, // SUBFMEO |
| 0U, // SUBFMEO_rec |
| 0U, // SUBFME_rec |
| 70U, // SUBFO |
| 70U, // SUBFO_rec |
| 0U, // SUBFUS |
| 0U, // SUBFUS_rec |
| 0U, // SUBFZE |
| 0U, // SUBFZE8 |
| 0U, // SUBFZE8O |
| 0U, // SUBFZE8O_rec |
| 0U, // SUBFZE8_rec |
| 0U, // SUBFZEO |
| 0U, // SUBFZEO_rec |
| 0U, // SUBFZE_rec |
| 70U, // SUBF_rec |
| 0U, // SYNC |
| 0U, // TABORT |
| 70U, // TABORTDC |
| 66U, // TABORTDCI |
| 70U, // TABORTWC |
| 66U, // TABORTWCI |
| 0U, // TAILB |
| 0U, // TAILB8 |
| 0U, // TAILBA |
| 0U, // TAILBA8 |
| 0U, // TAILBCTR |
| 0U, // TAILBCTR8 |
| 0U, // TBEGIN |
| 0U, // TBEGIN_RET |
| 0U, // TCHECK |
| 0U, // TCHECK_RET |
| 0U, // TCRETURNai |
| 0U, // TCRETURNai8 |
| 0U, // TCRETURNdi |
| 0U, // TCRETURNdi8 |
| 0U, // TCRETURNri |
| 0U, // TCRETURNri8 |
| 70U, // TD |
| 4U, // TDI |
| 0U, // TEND |
| 0U, // TLBIA |
| 0U, // TLBIE |
| 0U, // TLBIEL |
| 0U, // TLBIVAX |
| 0U, // TLBLD |
| 0U, // TLBLI |
| 0U, // TLBRE |
| 70U, // TLBRE2 |
| 0U, // TLBSX |
| 70U, // TLBSX2 |
| 70U, // TLBSX2D |
| 0U, // TLBSYNC |
| 0U, // TLBWE |
| 70U, // TLBWE2 |
| 0U, // TLSGDAIX |
| 0U, // TLSGDAIX8 |
| 0U, // TRAP |
| 0U, // TRECHKPT |
| 0U, // TRECLAIM |
| 0U, // TSR |
| 70U, // TW |
| 4U, // TWI |
| 0U, // UNENCODED_NOP |
| 0U, // UpdateGBR |
| 70U, // VABSDUB |
| 70U, // VABSDUH |
| 70U, // VABSDUW |
| 70U, // VADDCUQ |
| 70U, // VADDCUW |
| 518U, // VADDECUQ |
| 518U, // VADDEUQM |
| 70U, // VADDFP |
| 70U, // VADDSBS |
| 70U, // VADDSHS |
| 70U, // VADDSWS |
| 70U, // VADDUBM |
| 70U, // VADDUBS |
| 70U, // VADDUDM |
| 70U, // VADDUHM |
| 70U, // VADDUHS |
| 70U, // VADDUQM |
| 70U, // VADDUWM |
| 70U, // VADDUWS |
| 70U, // VAND |
| 70U, // VANDC |
| 70U, // VAVGSB |
| 70U, // VAVGSH |
| 70U, // VAVGSW |
| 70U, // VAVGUB |
| 70U, // VAVGUH |
| 70U, // VAVGUW |
| 70U, // VBPERMD |
| 70U, // VBPERMQ |
| 28U, // VCFSX |
| 1U, // VCFSX_0 |
| 70U, // VCFUGED |
| 28U, // VCFUX |
| 1U, // VCFUX_0 |
| 70U, // VCIPHER |
| 70U, // VCIPHERLAST |
| 70U, // VCLRLB |
| 70U, // VCLRRB |
| 0U, // VCLZB |
| 0U, // VCLZD |
| 70U, // VCLZDM |
| 0U, // VCLZH |
| 0U, // VCLZLSBB |
| 0U, // VCLZW |
| 70U, // VCMPBFP |
| 70U, // VCMPBFP_rec |
| 70U, // VCMPEQFP |
| 70U, // VCMPEQFP_rec |
| 70U, // VCMPEQUB |
| 70U, // VCMPEQUB_rec |
| 70U, // VCMPEQUD |
| 70U, // VCMPEQUD_rec |
| 70U, // VCMPEQUH |
| 70U, // VCMPEQUH_rec |
| 70U, // VCMPEQUQ |
| 70U, // VCMPEQUQ_rec |
| 70U, // VCMPEQUW |
| 70U, // VCMPEQUW_rec |
| 70U, // VCMPGEFP |
| 70U, // VCMPGEFP_rec |
| 70U, // VCMPGTFP |
| 70U, // VCMPGTFP_rec |
| 70U, // VCMPGTSB |
| 70U, // VCMPGTSB_rec |
| 70U, // VCMPGTSD |
| 70U, // VCMPGTSD_rec |
| 70U, // VCMPGTSH |
| 70U, // VCMPGTSH_rec |
| 70U, // VCMPGTSQ |
| 70U, // VCMPGTSQ_rec |
| 70U, // VCMPGTSW |
| 70U, // VCMPGTSW_rec |
| 70U, // VCMPGTUB |
| 70U, // VCMPGTUB_rec |
| 70U, // VCMPGTUD |
| 70U, // VCMPGTUD_rec |
| 70U, // VCMPGTUH |
| 70U, // VCMPGTUH_rec |
| 70U, // VCMPGTUQ |
| 70U, // VCMPGTUQ_rec |
| 70U, // VCMPGTUW |
| 70U, // VCMPGTUW_rec |
| 70U, // VCMPNEB |
| 70U, // VCMPNEB_rec |
| 70U, // VCMPNEH |
| 70U, // VCMPNEH_rec |
| 70U, // VCMPNEW |
| 70U, // VCMPNEW_rec |
| 70U, // VCMPNEZB |
| 70U, // VCMPNEZB_rec |
| 70U, // VCMPNEZH |
| 70U, // VCMPNEZH_rec |
| 70U, // VCMPNEZW |
| 70U, // VCMPNEZW_rec |
| 70U, // VCMPSQ |
| 70U, // VCMPUQ |
| 74U, // VCNTMBB |
| 74U, // VCNTMBD |
| 74U, // VCNTMBH |
| 74U, // VCNTMBW |
| 28U, // VCTSXS |
| 1U, // VCTSXS_0 |
| 28U, // VCTUXS |
| 1U, // VCTUXS_0 |
| 0U, // VCTZB |
| 0U, // VCTZD |
| 70U, // VCTZDM |
| 0U, // VCTZH |
| 0U, // VCTZLSBB |
| 0U, // VCTZW |
| 70U, // VDIVESD |
| 70U, // VDIVESQ |
| 70U, // VDIVESW |
| 70U, // VDIVEUD |
| 70U, // VDIVEUQ |
| 70U, // VDIVEUW |
| 70U, // VDIVSD |
| 70U, // VDIVSQ |
| 70U, // VDIVSW |
| 70U, // VDIVUD |
| 70U, // VDIVUQ |
| 70U, // VDIVUW |
| 70U, // VEQV |
| 0U, // VEXPANDBM |
| 0U, // VEXPANDDM |
| 0U, // VEXPANDHM |
| 0U, // VEXPANDQM |
| 0U, // VEXPANDWM |
| 0U, // VEXPTEFP |
| 518U, // VEXTDDVLX |
| 518U, // VEXTDDVRX |
| 518U, // VEXTDUBVLX |
| 518U, // VEXTDUBVRX |
| 518U, // VEXTDUHVLX |
| 518U, // VEXTDUHVRX |
| 518U, // VEXTDUWVLX |
| 518U, // VEXTDUWVRX |
| 0U, // VEXTRACTBM |
| 30U, // VEXTRACTD |
| 0U, // VEXTRACTDM |
| 0U, // VEXTRACTHM |
| 0U, // VEXTRACTQM |
| 30U, // VEXTRACTUB |
| 30U, // VEXTRACTUH |
| 30U, // VEXTRACTUW |
| 0U, // VEXTRACTWM |
| 0U, // VEXTSB2D |
| 0U, // VEXTSB2Ds |
| 0U, // VEXTSB2W |
| 0U, // VEXTSB2Ws |
| 0U, // VEXTSD2Q |
| 0U, // VEXTSH2D |
| 0U, // VEXTSH2Ds |
| 0U, // VEXTSH2W |
| 0U, // VEXTSH2Ws |
| 0U, // VEXTSW2D |
| 0U, // VEXTSW2Ds |
| 70U, // VEXTUBLX |
| 70U, // VEXTUBRX |
| 70U, // VEXTUHLX |
| 70U, // VEXTUHRX |
| 70U, // VEXTUWLX |
| 70U, // VEXTUWRX |
| 0U, // VGBBD |
| 32U, // VGNB |
| 86U, // VINSBLX |
| 86U, // VINSBRX |
| 86U, // VINSBVLX |
| 86U, // VINSBVRX |
| 0U, // VINSD |
| 86U, // VINSDLX |
| 86U, // VINSDRX |
| 0U, // VINSERTB |
| 30U, // VINSERTD |
| 0U, // VINSERTH |
| 30U, // VINSERTW |
| 86U, // VINSHLX |
| 86U, // VINSHRX |
| 86U, // VINSHVLX |
| 86U, // VINSHVRX |
| 0U, // VINSW |
| 86U, // VINSWLX |
| 86U, // VINSWRX |
| 86U, // VINSWVLX |
| 86U, // VINSWVRX |
| 0U, // VLOGEFP |
| 518U, // VMADDFP |
| 70U, // VMAXFP |
| 70U, // VMAXSB |
| 70U, // VMAXSD |
| 70U, // VMAXSH |
| 70U, // VMAXSW |
| 70U, // VMAXUB |
| 70U, // VMAXUD |
| 70U, // VMAXUH |
| 70U, // VMAXUW |
| 518U, // VMHADDSHS |
| 518U, // VMHRADDSHS |
| 70U, // VMINFP |
| 70U, // VMINSB |
| 70U, // VMINSD |
| 70U, // VMINSH |
| 70U, // VMINSW |
| 70U, // VMINUB |
| 70U, // VMINUD |
| 70U, // VMINUH |
| 70U, // VMINUW |
| 518U, // VMLADDUHM |
| 70U, // VMODSD |
| 70U, // VMODSQ |
| 70U, // VMODSW |
| 70U, // VMODUD |
| 70U, // VMODUQ |
| 70U, // VMODUW |
| 70U, // VMRGEW |
| 70U, // VMRGHB |
| 70U, // VMRGHH |
| 70U, // VMRGHW |
| 70U, // VMRGLB |
| 70U, // VMRGLH |
| 70U, // VMRGLW |
| 70U, // VMRGOW |
| 518U, // VMSUMCUD |
| 518U, // VMSUMMBM |
| 518U, // VMSUMSHM |
| 518U, // VMSUMSHS |
| 518U, // VMSUMUBM |
| 518U, // VMSUMUDM |
| 518U, // VMSUMUHM |
| 518U, // VMSUMUHS |
| 0U, // VMUL10CUQ |
| 70U, // VMUL10ECUQ |
| 70U, // VMUL10EUQ |
| 0U, // VMUL10UQ |
| 70U, // VMULESB |
| 70U, // VMULESD |
| 70U, // VMULESH |
| 70U, // VMULESW |
| 70U, // VMULEUB |
| 70U, // VMULEUD |
| 70U, // VMULEUH |
| 70U, // VMULEUW |
| 70U, // VMULHSD |
| 70U, // VMULHSW |
| 70U, // VMULHUD |
| 70U, // VMULHUW |
| 70U, // VMULLD |
| 70U, // VMULOSB |
| 70U, // VMULOSD |
| 70U, // VMULOSH |
| 70U, // VMULOSW |
| 70U, // VMULOUB |
| 70U, // VMULOUD |
| 70U, // VMULOUH |
| 70U, // VMULOUW |
| 70U, // VMULUWM |
| 70U, // VNAND |
| 70U, // VNCIPHER |
| 70U, // VNCIPHERLAST |
| 0U, // VNEGD |
| 0U, // VNEGW |
| 518U, // VNMSUBFP |
| 70U, // VNOR |
| 70U, // VOR |
| 70U, // VORC |
| 70U, // VPDEPD |
| 518U, // VPERM |
| 518U, // VPERMR |
| 518U, // VPERMXOR |
| 70U, // VPEXTD |
| 70U, // VPKPX |
| 70U, // VPKSDSS |
| 70U, // VPKSDUS |
| 70U, // VPKSHSS |
| 70U, // VPKSHUS |
| 70U, // VPKSWSS |
| 70U, // VPKSWUS |
| 70U, // VPKUDUM |
| 70U, // VPKUDUS |
| 70U, // VPKUHUM |
| 70U, // VPKUHUS |
| 70U, // VPKUWUM |
| 70U, // VPKUWUS |
| 70U, // VPMSUMB |
| 70U, // VPMSUMD |
| 70U, // VPMSUMH |
| 70U, // VPMSUMW |
| 0U, // VPOPCNTB |
| 0U, // VPOPCNTD |
| 0U, // VPOPCNTH |
| 0U, // VPOPCNTW |
| 0U, // VPRTYBD |
| 0U, // VPRTYBQ |
| 0U, // VPRTYBW |
| 0U, // VREFP |
| 0U, // VRFIM |
| 0U, // VRFIN |
| 0U, // VRFIP |
| 0U, // VRFIZ |
| 70U, // VRLB |
| 70U, // VRLD |
| 70U, // VRLDMI |
| 70U, // VRLDNM |
| 70U, // VRLH |
| 70U, // VRLQ |
| 70U, // VRLQMI |
| 70U, // VRLQNM |
| 70U, // VRLW |
| 70U, // VRLWMI |
| 70U, // VRLWNM |
| 0U, // VRSQRTEFP |
| 0U, // VSBOX |
| 518U, // VSEL |
| 1290U, // VSHASIGMAD |
| 1290U, // VSHASIGMAW |
| 70U, // VSL |
| 70U, // VSLB |
| 70U, // VSLD |
| 1798U, // VSLDBI |
| 1286U, // VSLDOI |
| 70U, // VSLH |
| 70U, // VSLO |
| 70U, // VSLQ |
| 70U, // VSLV |
| 70U, // VSLW |
| 28U, // VSPLTB |
| 28U, // VSPLTBs |
| 28U, // VSPLTH |
| 28U, // VSPLTHs |
| 0U, // VSPLTISB |
| 0U, // VSPLTISH |
| 0U, // VSPLTISW |
| 28U, // VSPLTW |
| 70U, // VSR |
| 70U, // VSRAB |
| 70U, // VSRAD |
| 70U, // VSRAH |
| 70U, // VSRAQ |
| 70U, // VSRAW |
| 70U, // VSRB |
| 70U, // VSRD |
| 1798U, // VSRDBI |
| 70U, // VSRH |
| 70U, // VSRO |
| 70U, // VSRQ |
| 70U, // VSRV |
| 70U, // VSRW |
| 0U, // VSTRIBL |
| 0U, // VSTRIBL_rec |
| 0U, // VSTRIBR |
| 0U, // VSTRIBR_rec |
| 0U, // VSTRIHL |
| 0U, // VSTRIHL_rec |
| 0U, // VSTRIHR |
| 0U, // VSTRIHR_rec |
| 70U, // VSUBCUQ |
| 70U, // VSUBCUW |
| 518U, // VSUBECUQ |
| 518U, // VSUBEUQM |
| 70U, // VSUBFP |
| 70U, // VSUBSBS |
| 70U, // VSUBSHS |
| 70U, // VSUBSWS |
| 70U, // VSUBUBM |
| 70U, // VSUBUBS |
| 70U, // VSUBUDM |
| 70U, // VSUBUHM |
| 70U, // VSUBUHS |
| 70U, // VSUBUQM |
| 70U, // VSUBUWM |
| 70U, // VSUBUWS |
| 70U, // VSUM2SWS |
| 70U, // VSUM4SBS |
| 70U, // VSUM4SHS |
| 70U, // VSUM4UBS |
| 70U, // VSUMSWS |
| 0U, // VUPKHPX |
| 0U, // VUPKHSB |
| 0U, // VUPKHSH |
| 0U, // VUPKHSW |
| 0U, // VUPKLPX |
| 0U, // VUPKLSB |
| 0U, // VUPKLSH |
| 0U, // VUPKLSW |
| 70U, // VXOR |
| 12U, // V_SET0 |
| 12U, // V_SET0B |
| 12U, // V_SET0H |
| 0U, // V_SETALLONES |
| 0U, // V_SETALLONESB |
| 0U, // V_SETALLONESH |
| 0U, // WAIT |
| 0U, // WRTEE |
| 0U, // WRTEEI |
| 70U, // XOR |
| 70U, // XOR8 |
| 70U, // XOR8_rec |
| 8U, // XORI |
| 8U, // XORI8 |
| 8U, // XORIS |
| 8U, // XORIS8 |
| 70U, // XOR_rec |
| 0U, // XSABSDP |
| 0U, // XSABSQP |
| 70U, // XSADDDP |
| 70U, // XSADDQP |
| 70U, // XSADDQPO |
| 70U, // XSADDSP |
| 70U, // XSCMPEQDP |
| 70U, // XSCMPEQQP |
| 70U, // XSCMPEXPDP |
| 70U, // XSCMPEXPQP |
| 70U, // XSCMPGEDP |
| 70U, // XSCMPGEQP |
| 70U, // XSCMPGTDP |
| 70U, // XSCMPGTQP |
| 70U, // XSCMPODP |
| 70U, // XSCMPOQP |
| 70U, // XSCMPUDP |
| 70U, // XSCMPUQP |
| 70U, // XSCPSGNDP |
| 70U, // XSCPSGNQP |
| 0U, // XSCVDPHP |
| 0U, // XSCVDPQP |
| 0U, // XSCVDPSP |
| 0U, // XSCVDPSPN |
| 0U, // XSCVDPSXDS |
| 0U, // XSCVDPSXDSs |
| 0U, // XSCVDPSXWS |
| 0U, // XSCVDPSXWSs |
| 0U, // XSCVDPUXDS |
| 0U, // XSCVDPUXDSs |
| 0U, // XSCVDPUXWS |
| 0U, // XSCVDPUXWSs |
| 0U, // XSCVHPDP |
| 0U, // XSCVQPDP |
| 0U, // XSCVQPDPO |
| 0U, // XSCVQPSDZ |
| 0U, // XSCVQPSQZ |
| 0U, // XSCVQPSWZ |
| 0U, // XSCVQPUDZ |
| 0U, // XSCVQPUQZ |
| 0U, // XSCVQPUWZ |
| 0U, // XSCVSDQP |
| 0U, // XSCVSPDP |
| 0U, // XSCVSPDPN |
| 0U, // XSCVSQQP |
| 0U, // XSCVSXDDP |
| 0U, // XSCVSXDSP |
| 0U, // XSCVUDQP |
| 0U, // XSCVUQQP |
| 0U, // XSCVUXDDP |
| 0U, // XSCVUXDSP |
| 70U, // XSDIVDP |
| 70U, // XSDIVQP |
| 70U, // XSDIVQPO |
| 70U, // XSDIVSP |
| 70U, // XSIEXPDP |
| 70U, // XSIEXPQP |
| 86U, // XSMADDADP |
| 86U, // XSMADDASP |
| 86U, // XSMADDMDP |
| 86U, // XSMADDMSP |
| 86U, // XSMADDQP |
| 86U, // XSMADDQPO |
| 70U, // XSMAXCDP |
| 70U, // XSMAXCQP |
| 70U, // XSMAXDP |
| 70U, // XSMAXJDP |
| 70U, // XSMINCDP |
| 70U, // XSMINCQP |
| 70U, // XSMINDP |
| 70U, // XSMINJDP |
| 86U, // XSMSUBADP |
| 86U, // XSMSUBASP |
| 86U, // XSMSUBMDP |
| 86U, // XSMSUBMSP |
| 86U, // XSMSUBQP |
| 86U, // XSMSUBQPO |
| 70U, // XSMULDP |
| 70U, // XSMULQP |
| 70U, // XSMULQPO |
| 70U, // XSMULSP |
| 0U, // XSNABSDP |
| 0U, // XSNABSDPs |
| 0U, // XSNABSQP |
| 0U, // XSNEGDP |
| 0U, // XSNEGQP |
| 86U, // XSNMADDADP |
| 86U, // XSNMADDASP |
| 86U, // XSNMADDMDP |
| 86U, // XSNMADDMSP |
| 86U, // XSNMADDQP |
| 86U, // XSNMADDQPO |
| 86U, // XSNMSUBADP |
| 86U, // XSNMSUBASP |
| 86U, // XSNMSUBMDP |
| 86U, // XSNMSUBMSP |
| 86U, // XSNMSUBQP |
| 86U, // XSNMSUBQPO |
| 0U, // XSRDPI |
| 0U, // XSRDPIC |
| 0U, // XSRDPIM |
| 0U, // XSRDPIP |
| 0U, // XSRDPIZ |
| 0U, // XSREDP |
| 0U, // XSRESP |
| 0U, // XSRQPI |
| 0U, // XSRQPIX |
| 0U, // XSRQPXP |
| 0U, // XSRSP |
| 0U, // XSRSQRTEDP |
| 0U, // XSRSQRTESP |
| 0U, // XSSQRTDP |
| 0U, // XSSQRTQP |
| 0U, // XSSQRTQPO |
| 0U, // XSSQRTSP |
| 70U, // XSSUBDP |
| 70U, // XSSUBQP |
| 70U, // XSSUBQPO |
| 70U, // XSSUBSP |
| 70U, // XSTDIVDP |
| 0U, // XSTSQRTDP |
| 34U, // XSTSTDCDP |
| 34U, // XSTSTDCQP |
| 34U, // XSTSTDCSP |
| 0U, // XSXEXPDP |
| 0U, // XSXEXPQP |
| 0U, // XSXSIGDP |
| 0U, // XSXSIGQP |
| 0U, // XVABSDP |
| 0U, // XVABSSP |
| 70U, // XVADDDP |
| 70U, // XVADDSP |
| 70U, // XVBF16GER2 |
| 86U, // XVBF16GER2NN |
| 86U, // XVBF16GER2NP |
| 86U, // XVBF16GER2PN |
| 86U, // XVBF16GER2PP |
| 70U, // XVBF16GER2W |
| 86U, // XVBF16GER2WNN |
| 86U, // XVBF16GER2WNP |
| 86U, // XVBF16GER2WPN |
| 86U, // XVBF16GER2WPP |
| 70U, // XVCMPEQDP |
| 70U, // XVCMPEQDP_rec |
| 70U, // XVCMPEQSP |
| 70U, // XVCMPEQSP_rec |
| 70U, // XVCMPGEDP |
| 70U, // XVCMPGEDP_rec |
| 70U, // XVCMPGESP |
| 70U, // XVCMPGESP_rec |
| 70U, // XVCMPGTDP |
| 70U, // XVCMPGTDP_rec |
| 70U, // XVCMPGTSP |
| 70U, // XVCMPGTSP_rec |
| 70U, // XVCPSGNDP |
| 70U, // XVCPSGNSP |
| 0U, // XVCVBF16SPN |
| 0U, // XVCVDPSP |
| 0U, // XVCVDPSXDS |
| 0U, // XVCVDPSXWS |
| 0U, // XVCVDPUXDS |
| 0U, // XVCVDPUXWS |
| 0U, // XVCVHPSP |
| 0U, // XVCVSPBF16 |
| 0U, // XVCVSPDP |
| 0U, // XVCVSPHP |
| 0U, // XVCVSPSXDS |
| 0U, // XVCVSPSXWS |
| 0U, // XVCVSPUXDS |
| 0U, // XVCVSPUXWS |
| 0U, // XVCVSXDDP |
| 0U, // XVCVSXDSP |
| 0U, // XVCVSXWDP |
| 0U, // XVCVSXWSP |
| 0U, // XVCVUXDDP |
| 0U, // XVCVUXDSP |
| 0U, // XVCVUXWDP |
| 0U, // XVCVUXWSP |
| 70U, // XVDIVDP |
| 70U, // XVDIVSP |
| 70U, // XVF16GER2 |
| 86U, // XVF16GER2NN |
| 86U, // XVF16GER2NP |
| 86U, // XVF16GER2PN |
| 86U, // XVF16GER2PP |
| 70U, // XVF16GER2W |
| 86U, // XVF16GER2WNN |
| 86U, // XVF16GER2WNP |
| 86U, // XVF16GER2WPN |
| 86U, // XVF16GER2WPP |
| 70U, // XVF32GER |
| 86U, // XVF32GERNN |
| 86U, // XVF32GERNP |
| 86U, // XVF32GERPN |
| 86U, // XVF32GERPP |
| 70U, // XVF32GERW |
| 86U, // XVF32GERWNN |
| 86U, // XVF32GERWNP |
| 86U, // XVF32GERWPN |
| 86U, // XVF32GERWPP |
| 70U, // XVF64GER |
| 86U, // XVF64GERNN |
| 86U, // XVF64GERNP |
| 86U, // XVF64GERPN |
| 86U, // XVF64GERPP |
| 70U, // XVF64GERW |
| 86U, // XVF64GERWNN |
| 86U, // XVF64GERWNP |
| 86U, // XVF64GERWPN |
| 86U, // XVF64GERWPP |
| 70U, // XVI16GER2 |
| 86U, // XVI16GER2PP |
| 70U, // XVI16GER2S |
| 86U, // XVI16GER2SPP |
| 70U, // XVI16GER2SW |
| 86U, // XVI16GER2SWPP |
| 70U, // XVI16GER2W |
| 86U, // XVI16GER2WPP |
| 70U, // XVI4GER8 |
| 86U, // XVI4GER8PP |
| 70U, // XVI4GER8W |
| 86U, // XVI4GER8WPP |
| 70U, // XVI8GER4 |
| 86U, // XVI8GER4PP |
| 86U, // XVI8GER4SPP |
| 70U, // XVI8GER4W |
| 86U, // XVI8GER4WPP |
| 86U, // XVI8GER4WSPP |
| 70U, // XVIEXPDP |
| 70U, // XVIEXPSP |
| 86U, // XVMADDADP |
| 86U, // XVMADDASP |
| 86U, // XVMADDMDP |
| 86U, // XVMADDMSP |
| 70U, // XVMAXDP |
| 70U, // XVMAXSP |
| 70U, // XVMINDP |
| 70U, // XVMINSP |
| 86U, // XVMSUBADP |
| 86U, // XVMSUBASP |
| 86U, // XVMSUBMDP |
| 86U, // XVMSUBMSP |
| 70U, // XVMULDP |
| 70U, // XVMULSP |
| 0U, // XVNABSDP |
| 0U, // XVNABSSP |
| 0U, // XVNEGDP |
| 0U, // XVNEGSP |
| 86U, // XVNMADDADP |
| 86U, // XVNMADDASP |
| 86U, // XVNMADDMDP |
| 86U, // XVNMADDMSP |
| 86U, // XVNMSUBADP |
| 86U, // XVNMSUBASP |
| 86U, // XVNMSUBMDP |
| 86U, // XVNMSUBMSP |
| 0U, // XVRDPI |
| 0U, // XVRDPIC |
| 0U, // XVRDPIM |
| 0U, // XVRDPIP |
| 0U, // XVRDPIZ |
| 0U, // XVREDP |
| 0U, // XVRESP |
| 0U, // XVRSPI |
| 0U, // XVRSPIC |
| 0U, // XVRSPIM |
| 0U, // XVRSPIP |
| 0U, // XVRSPIZ |
| 0U, // XVRSQRTEDP |
| 0U, // XVRSQRTESP |
| 0U, // XVSQRTDP |
| 0U, // XVSQRTSP |
| 70U, // XVSUBDP |
| 70U, // XVSUBSP |
| 70U, // XVTDIVDP |
| 70U, // XVTDIVSP |
| 0U, // XVTLSBB |
| 0U, // XVTSQRTDP |
| 0U, // XVTSQRTSP |
| 34U, // XVTSTDCDP |
| 34U, // XVTSTDCSP |
| 0U, // XVXEXPDP |
| 0U, // XVXEXPSP |
| 0U, // XVXSIGDP |
| 0U, // XVXSIGSP |
| 518U, // XXBLENDVB |
| 518U, // XXBLENDVD |
| 518U, // XXBLENDVH |
| 518U, // XXBLENDVW |
| 0U, // XXBRD |
| 0U, // XXBRH |
| 0U, // XXBRQ |
| 0U, // XXBRW |
| 20998U, // XXEVAL |
| 36U, // XXEXTRACTUW |
| 38U, // XXGENPCVBM |
| 38U, // XXGENPCVDM |
| 38U, // XXGENPCVHM |
| 38U, // XXGENPCVWM |
| 40U, // XXINSERTW |
| 70U, // XXLAND |
| 70U, // XXLANDC |
| 70U, // XXLEQV |
| 12U, // XXLEQVOnes |
| 70U, // XXLNAND |
| 70U, // XXLNOR |
| 70U, // XXLOR |
| 70U, // XXLORC |
| 70U, // XXLORf |
| 70U, // XXLXOR |
| 12U, // XXLXORdpz |
| 12U, // XXLXORspz |
| 12U, // XXLXORz |
| 0U, // XXMFACC |
| 0U, // XXMFACCW |
| 70U, // XXMRGHW |
| 70U, // XXMRGLW |
| 0U, // XXMTACC |
| 0U, // XXMTACCW |
| 86U, // XXPERM |
| 774U, // XXPERMDI |
| 2066U, // XXPERMDIs |
| 86U, // XXPERMR |
| 37382U, // XXPERMX |
| 518U, // XXSEL |
| 0U, // XXSETACCZ |
| 0U, // XXSETACCZW |
| 774U, // XXSLDWI |
| 2066U, // XXSLDWIs |
| 86U, // XXSPLTI32DX |
| 0U, // XXSPLTIB |
| 0U, // XXSPLTIDP |
| 0U, // XXSPLTIW |
| 14U, // XXSPLTW |
| 14U, // XXSPLTWs |
| 42U, // gBC |
| 44U, // gBCA |
| 0U, // gBCAat |
| 70U, // gBCCTR |
| 70U, // gBCCTRL |
| 42U, // gBCL |
| 44U, // gBCLA |
| 0U, // gBCLAat |
| 70U, // gBCLR |
| 70U, // gBCLRL |
| 0U, // gBCLat |
| 0U, // gBCat |
| }; |
| |
| static const uint8_t OpInfo2[] = { |
| 0U, // PHI |
| 0U, // INLINEASM |
| 0U, // INLINEASM_BR |
| 0U, // CFI_INSTRUCTION |
| 0U, // EH_LABEL |
| 0U, // GC_LABEL |
| 0U, // ANNOTATION_LABEL |
| 0U, // KILL |
| 0U, // EXTRACT_SUBREG |
| 0U, // INSERT_SUBREG |
| 0U, // IMPLICIT_DEF |
| 0U, // SUBREG_TO_REG |
| 0U, // COPY_TO_REGCLASS |
| 0U, // DBG_VALUE |
| 0U, // DBG_VALUE_LIST |
| 0U, // DBG_INSTR_REF |
| 0U, // DBG_PHI |
| 0U, // DBG_LABEL |
| 0U, // REG_SEQUENCE |
| 0U, // COPY |
| 0U, // BUNDLE |
| 0U, // LIFETIME_START |
| 0U, // LIFETIME_END |
| 0U, // PSEUDO_PROBE |
| 0U, // ARITH_FENCE |
| 0U, // STACKMAP |
| 0U, // FENTRY_CALL |
| 0U, // PATCHPOINT |
| 0U, // LOAD_STACK_GUARD |
| 0U, // PREALLOCATED_SETUP |
| 0U, // PREALLOCATED_ARG |
| 0U, // STATEPOINT |
| 0U, // LOCAL_ESCAPE |
| 0U, // FAULTING_OP |
| 0U, // PATCHABLE_OP |
| 0U, // PATCHABLE_FUNCTION_ENTER |
| 0U, // PATCHABLE_RET |
| 0U, // PATCHABLE_FUNCTION_EXIT |
| 0U, // PATCHABLE_TAIL_CALL |
| 0U, // PATCHABLE_EVENT_CALL |
| 0U, // PATCHABLE_TYPED_EVENT_CALL |
| 0U, // ICALL_BRANCH_FUNNEL |
| 0U, // MEMBARRIER |
| 0U, // G_ASSERT_SEXT |
| 0U, // G_ASSERT_ZEXT |
| 0U, // G_ASSERT_ALIGN |
| 0U, // G_ADD |
| 0U, // G_SUB |
| 0U, // G_MUL |
| 0U, // G_SDIV |
| 0U, // G_UDIV |
| 0U, // G_SREM |
| 0U, // G_UREM |
| 0U, // G_SDIVREM |
| 0U, // G_UDIVREM |
| 0U, // G_AND |
| 0U, // G_OR |
| 0U, // G_XOR |
| 0U, // G_IMPLICIT_DEF |
| 0U, // G_PHI |
| 0U, // G_FRAME_INDEX |
| 0U, // G_GLOBAL_VALUE |
| 0U, // G_EXTRACT |
| 0U, // G_UNMERGE_VALUES |
| 0U, // G_INSERT |
| 0U, // G_MERGE_VALUES |
| 0U, // G_BUILD_VECTOR |
| 0U, // G_BUILD_VECTOR_TRUNC |
| 0U, // G_CONCAT_VECTORS |
| 0U, // G_PTRTOINT |
| 0U, // G_INTTOPTR |
| 0U, // G_BITCAST |
| 0U, // G_FREEZE |
| 0U, // G_INTRINSIC_FPTRUNC_ROUND |
| 0U, // G_INTRINSIC_TRUNC |
| 0U, // G_INTRINSIC_ROUND |
| 0U, // G_INTRINSIC_LRINT |
| 0U, // G_INTRINSIC_ROUNDEVEN |
| 0U, // G_READCYCLECOUNTER |
| 0U, // G_LOAD |
| 0U, // G_SEXTLOAD |
| 0U, // G_ZEXTLOAD |
| 0U, // G_INDEXED_LOAD |
| 0U, // G_INDEXED_SEXTLOAD |
| 0U, // G_INDEXED_ZEXTLOAD |
| 0U, // G_STORE |
| 0U, // G_INDEXED_STORE |
| 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS |
| 0U, // G_ATOMIC_CMPXCHG |
| 0U, // G_ATOMICRMW_XCHG |
| 0U, // G_ATOMICRMW_ADD |
| 0U, // G_ATOMICRMW_SUB |
| 0U, // G_ATOMICRMW_AND |
| 0U, // G_ATOMICRMW_NAND |
| 0U, // G_ATOMICRMW_OR |
| 0U, // G_ATOMICRMW_XOR |
| 0U, // G_ATOMICRMW_MAX |
| 0U, // G_ATOMICRMW_MIN |
| 0U, // G_ATOMICRMW_UMAX |
| 0U, // G_ATOMICRMW_UMIN |
| 0U, // G_ATOMICRMW_FADD |
| 0U, // G_ATOMICRMW_FSUB |
| 0U, // G_ATOMICRMW_FMAX |
| 0U, // G_ATOMICRMW_FMIN |
| 0U, // G_ATOMICRMW_UINC_WRAP |
| 0U, // G_ATOMICRMW_UDEC_WRAP |
| 0U, // G_FENCE |
| 0U, // G_BRCOND |
| 0U, // G_BRINDIRECT |
| 0U, // G_INVOKE_REGION_START |
| 0U, // G_INTRINSIC |
| 0U, // G_INTRINSIC_W_SIDE_EFFECTS |
| 0U, // G_ANYEXT |
| 0U, // G_TRUNC |
| 0U, // G_CONSTANT |
| 0U, // G_FCONSTANT |
| 0U, // G_VASTART |
| 0U, // G_VAARG |
| 0U, // G_SEXT |
| 0U, // G_SEXT_INREG |
| 0U, // G_ZEXT |
| 0U, // G_SHL |
| 0U, // G_LSHR |
| 0U, // G_ASHR |
| 0U, // G_FSHL |
| 0U, // G_FSHR |
| 0U, // G_ROTR |
| 0U, // G_ROTL |
| 0U, // G_ICMP |
| 0U, // G_FCMP |
| 0U, // G_SELECT |
| 0U, // G_UADDO |
| 0U, // G_UADDE |
| 0U, // G_USUBO |
| 0U, // G_USUBE |
| 0U, // G_SADDO |
| 0U, // G_SADDE |
| 0U, // G_SSUBO |
| 0U, // G_SSUBE |
| 0U, // G_UMULO |
| 0U, // G_SMULO |
| 0U, // G_UMULH |
| 0U, // G_SMULH |
| 0U, // G_UADDSAT |
| 0U, // G_SADDSAT |
| 0U, // G_USUBSAT |
| 0U, // G_SSUBSAT |
| 0U, // G_USHLSAT |
| 0U, // G_SSHLSAT |
| 0U, // G_SMULFIX |
| 0U, // G_UMULFIX |
| 0U, // G_SMULFIXSAT |
| 0U, // G_UMULFIXSAT |
| 0U, // G_SDIVFIX |
| 0U, // G_UDIVFIX |
| 0U, // G_SDIVFIXSAT |
| 0U, // G_UDIVFIXSAT |
| 0U, // G_FADD |
| 0U, // G_FSUB |
| 0U, // G_FMUL |
| 0U, // G_FMA |
| 0U, // G_FMAD |
| 0U, // G_FDIV |
| 0U, // G_FREM |
| 0U, // G_FPOW |
| 0U, // G_FPOWI |
| 0U, // G_FEXP |
| 0U, // G_FEXP2 |
| 0U, // G_FLOG |
| 0U, // G_FLOG2 |
| 0U, // G_FLOG10 |
| 0U, // G_FNEG |
| 0U, // G_FPEXT |
| 0U, // G_FPTRUNC |
| 0U, // G_FPTOSI |
| 0U, // G_FPTOUI |
| 0U, // G_SITOFP |
| 0U, // G_UITOFP |
| 0U, // G_FABS |
| 0U, // G_FCOPYSIGN |
| 0U, // G_IS_FPCLASS |
| 0U, // G_FCANONICALIZE |
| 0U, // G_FMINNUM |
| 0U, // G_FMAXNUM |
| 0U, // G_FMINNUM_IEEE |
| 0U, // G_FMAXNUM_IEEE |
| 0U, // G_FMINIMUM |
| 0U, // G_FMAXIMUM |
| 0U, // G_PTR_ADD |
| 0U, // G_PTRMASK |
| 0U, // G_SMIN |
| 0U, // G_SMAX |
| 0U, // G_UMIN |
| 0U, // G_UMAX |
| 0U, // G_ABS |
| 0U, // G_LROUND |
| 0U, // G_LLROUND |
| 0U, // G_BR |
| 0U, // G_BRJT |
| 0U, // G_INSERT_VECTOR_ELT |
| 0U, // G_EXTRACT_VECTOR_ELT |
| 0U, // G_SHUFFLE_VECTOR |
| 0U, // G_CTTZ |
| 0U, // G_CTTZ_ZERO_UNDEF |
| 0U, // G_CTLZ |
| 0U, // G_CTLZ_ZERO_UNDEF |
| 0U, // G_CTPOP |
| 0U, // G_BSWAP |
| 0U, // G_BITREVERSE |
| 0U, // G_FCEIL |
| 0U, // G_FCOS |
| 0U, // G_FSIN |
| 0U, // G_FSQRT |
| 0U, // G_FFLOOR |
| 0U, // G_FRINT |
| 0U, // G_FNEARBYINT |
| 0U, // G_ADDRSPACE_CAST |
| 0U, // G_BLOCK_ADDR |
| 0U, // G_JUMP_TABLE |
| 0U, // G_DYN_STACKALLOC |
| 0U, // G_STRICT_FADD |
| 0U, // G_STRICT_FSUB |
| 0U, // G_STRICT_FMUL |
| 0U, // G_STRICT_FDIV |
| 0U, // G_STRICT_FREM |
| 0U, // G_STRICT_FMA |
| 0U, // G_STRICT_FSQRT |
| 0U, // G_READ_REGISTER |
| 0U, // G_WRITE_REGISTER |
| 0U, // G_MEMCPY |
| 0U, // G_MEMCPY_INLINE |
| 0U, // G_MEMMOVE |
| 0U, // G_MEMSET |
| 0U, // G_BZERO |
| 0U, // G_VECREDUCE_SEQ_FADD |
| 0U, // G_VECREDUCE_SEQ_FMUL |
| 0U, // G_VECREDUCE_FADD |
| 0U, // G_VECREDUCE_FMUL |
| 0U, // G_VECREDUCE_FMAX |
| 0U, // G_VECREDUCE_FMIN |
| 0U, // G_VECREDUCE_ADD |
| 0U, // G_VECREDUCE_MUL |
| 0U, // G_VECREDUCE_AND |
| 0U, // G_VECREDUCE_OR |
| 0U, // G_VECREDUCE_XOR |
| 0U, // G_VECREDUCE_SMAX |
| 0U, // G_VECREDUCE_SMIN |
| 0U, // G_VECREDUCE_UMAX |
| 0U, // G_VECREDUCE_UMIN |
| 0U, // G_SBFX |
| 0U, // G_UBFX |
| 0U, // ATOMIC_CMP_SWAP_I128 |
| 0U, // ATOMIC_LOAD_ADD_I128 |
| 0U, // ATOMIC_LOAD_AND_I128 |
| 0U, // ATOMIC_LOAD_NAND_I128 |
| 0U, // ATOMIC_LOAD_OR_I128 |
| 0U, // ATOMIC_LOAD_SUB_I128 |
| 0U, // ATOMIC_LOAD_XOR_I128 |
| 0U, // ATOMIC_SWAP_I128 |
| 0U, // BUILD_QUADWORD |
| 0U, // BUILD_UACC |
| 0U, // CFENCE8 |
| 0U, // CLRLSLDI |
| 0U, // CLRLSLDI_rec |
| 0U, // CLRLSLWI |
| 0U, // CLRLSLWI_rec |
| 0U, // CLRRDI |
| 0U, // CLRRDI_rec |
| 0U, // CLRRWI |
| 0U, // CLRRWI_rec |
| 0U, // DCBFL |
| 0U, // DCBFLP |
| 0U, // DCBFPS |
| 0U, // DCBFx |
| 0U, // DCBSTPS |
| 0U, // DCBTCT |
| 0U, // DCBTDS |
| 0U, // DCBTSTCT |
| 0U, // DCBTSTDS |
| 0U, // DCBTSTT |
| 0U, // DCBTSTx |
| 0U, // DCBTT |
| 0U, // DCBTx |
| 0U, // DFLOADf32 |
| 0U, // DFLOADf64 |
| 0U, // DFSTOREf32 |
| 0U, // DFSTOREf64 |
| 0U, // EXTLDI |
| 0U, // EXTLDI_rec |
| 0U, // EXTLWI |
| 0U, // EXTLWI_rec |
| 0U, // EXTRDI |
| 0U, // EXTRDI_rec |
| 0U, // EXTRWI |
| 0U, // EXTRWI_rec |
| 0U, // INSLWI |
| 0U, // INSLWI_rec |
| 0U, // INSRDI |
| 0U, // INSRDI_rec |
| 0U, // INSRWI |
| 0U, // INSRWI_rec |
| 0U, // KILL_PAIR |
| 0U, // LAx |
| 0U, // LIWAX |
| 0U, // LIWZX |
| 0U, // RLWIMIbm |
| 0U, // RLWIMIbm_rec |
| 0U, // RLWINMbm |
| 0U, // RLWINMbm_rec |
| 0U, // RLWNMbm |
| 0U, // RLWNMbm_rec |
| 0U, // ROTRDI |
| 0U, // ROTRDI_rec |
| 0U, // ROTRWI |
| 0U, // ROTRWI_rec |
| 0U, // SLDI |
| 0U, // SLDI_rec |
| 0U, // SLWI |
| 0U, // SLWI_rec |
| 0U, // SPILLTOVSR_LD |
| 0U, // SPILLTOVSR_LDX |
| 0U, // SPILLTOVSR_ST |
| 0U, // SPILLTOVSR_STX |
| 0U, // SRDI |
| 0U, // SRDI_rec |
| 0U, // SRWI |
| 0U, // SRWI_rec |
| 0U, // STIWX |
| 0U, // SUBI |
| 0U, // SUBIC |
| 0U, // SUBIC_rec |
| 0U, // SUBIS |
| 0U, // SUBPCIS |
| 0U, // XFLOADf32 |
| 0U, // XFLOADf64 |
| 0U, // XFSTOREf32 |
| 0U, // XFSTOREf64 |
| 0U, // ADD4 |
| 0U, // ADD4O |
| 0U, // ADD4O_rec |
| 0U, // ADD4TLS |
| 0U, // ADD4_rec |
| 0U, // ADD8 |
| 0U, // ADD8O |
| 0U, // ADD8O_rec |
| 0U, // ADD8TLS |
| 0U, // ADD8TLS_ |
| 0U, // ADD8_rec |
| 0U, // ADDC |
| 0U, // ADDC8 |
| 0U, // ADDC8O |
| 0U, // ADDC8O_rec |
| 0U, // ADDC8_rec |
| 0U, // ADDCO |
| 0U, // ADDCO_rec |
| 0U, // ADDC_rec |
| 0U, // ADDE |
| 0U, // ADDE8 |
| 0U, // ADDE8O |
| 0U, // ADDE8O_rec |
| 0U, // ADDE8_rec |
| 0U, // ADDEO |
| 0U, // ADDEO_rec |
| 0U, // ADDEX |
| 0U, // ADDEX8 |
| 0U, // ADDE_rec |
| 0U, // ADDI |
| 0U, // ADDI8 |
| 0U, // ADDIC |
| 0U, // ADDIC8 |
| 0U, // ADDIC_rec |
| 0U, // ADDIS |
| 0U, // ADDIS8 |
| 0U, // ADDISdtprelHA |
| 0U, // ADDISdtprelHA32 |
| 0U, // ADDISgotTprelHA |
| 0U, // ADDIStlsgdHA |
| 0U, // ADDIStlsldHA |
| 0U, // ADDIStocHA |
| 0U, // ADDIStocHA8 |
| 0U, // ADDIdtprelL |
| 0U, // ADDIdtprelL32 |
| 0U, // ADDItlsgdL |
| 0U, // ADDItlsgdL32 |
| 0U, // ADDItlsgdLADDR |
| 0U, // ADDItlsgdLADDR32 |
| 0U, // ADDItlsldL |
| 0U, // ADDItlsldL32 |
| 0U, // ADDItlsldLADDR |
| 0U, // ADDItlsldLADDR32 |
| 0U, // ADDItoc |
| 0U, // ADDItoc8 |
| 0U, // ADDItocL |
| 0U, // ADDME |
| 0U, // ADDME8 |
| 0U, // ADDME8O |
| 0U, // ADDME8O_rec |
| 0U, // ADDME8_rec |
| 0U, // ADDMEO |
| 0U, // ADDMEO_rec |
| 0U, // ADDME_rec |
| 0U, // ADDPCIS |
| 0U, // ADDZE |
| 0U, // ADDZE8 |
| 0U, // ADDZE8O |
| 0U, // ADDZE8O_rec |
| 0U, // ADDZE8_rec |
| 0U, // ADDZEO |
| 0U, // ADDZEO_rec |
| 0U, // ADDZE_rec |
| 0U, // ADJCALLSTACKDOWN |
| 0U, // ADJCALLSTACKUP |
| 0U, // AND |
| 0U, // AND8 |
| 0U, // AND8_rec |
| 0U, // ANDC |
| 0U, // ANDC8 |
| 0U, // ANDC8_rec |
| 0U, // ANDC_rec |
| 0U, // ANDI8_rec |
| 0U, // ANDIS8_rec |
| 0U, // ANDIS_rec |
| 0U, // ANDI_rec |
| 0U, // ANDI_rec_1_EQ_BIT |
| 0U, // ANDI_rec_1_EQ_BIT8 |
| 0U, // ANDI_rec_1_GT_BIT |
| 0U, // ANDI_rec_1_GT_BIT8 |
| 0U, // AND_rec |
| 0U, // ATOMIC_CMP_SWAP_I16 |
| 0U, // ATOMIC_CMP_SWAP_I32 |
| 0U, // ATOMIC_CMP_SWAP_I64 |
| 0U, // ATOMIC_CMP_SWAP_I8 |
| 0U, // ATOMIC_LOAD_ADD_I16 |
| 0U, // ATOMIC_LOAD_ADD_I32 |
| 0U, // ATOMIC_LOAD_ADD_I64 |
| 0U, // ATOMIC_LOAD_ADD_I8 |
| 0U, // ATOMIC_LOAD_AND_I16 |
| 0U, // ATOMIC_LOAD_AND_I32 |
| 0U, // ATOMIC_LOAD_AND_I64 |
| 0U, // ATOMIC_LOAD_AND_I8 |
| 0U, // ATOMIC_LOAD_MAX_I16 |
| 0U, // ATOMIC_LOAD_MAX_I32 |
| 0U, // ATOMIC_LOAD_MAX_I64 |
| 0U, // ATOMIC_LOAD_MAX_I8 |
| 0U, // ATOMIC_LOAD_MIN_I16 |
| 0U, // ATOMIC_LOAD_MIN_I32 |
| 0U, // ATOMIC_LOAD_MIN_I64 |
| 0U, // ATOMIC_LOAD_MIN_I8 |
| 0U, // ATOMIC_LOAD_NAND_I16 |
| 0U, // ATOMIC_LOAD_NAND_I32 |
| 0U, // ATOMIC_LOAD_NAND_I64 |
| 0U, // ATOMIC_LOAD_NAND_I8 |
| 0U, // ATOMIC_LOAD_OR_I16 |
| 0U, // ATOMIC_LOAD_OR_I32 |
| 0U, // ATOMIC_LOAD_OR_I64 |
| 0U, // ATOMIC_LOAD_OR_I8 |
| 0U, // ATOMIC_LOAD_SUB_I16 |
| 0U, // ATOMIC_LOAD_SUB_I32 |
| 0U, // ATOMIC_LOAD_SUB_I64 |
| 0U, // ATOMIC_LOAD_SUB_I8 |
| 0U, // ATOMIC_LOAD_UMAX_I16 |
| 0U, // ATOMIC_LOAD_UMAX_I32 |
| 0U, // ATOMIC_LOAD_UMAX_I64 |
| 0U, // ATOMIC_LOAD_UMAX_I8 |
| 0U, // ATOMIC_LOAD_UMIN_I16 |
| 0U, // ATOMIC_LOAD_UMIN_I32 |
| 0U, // ATOMIC_LOAD_UMIN_I64 |
| 0U, // ATOMIC_LOAD_UMIN_I8 |
| 0U, // ATOMIC_LOAD_XOR_I16 |
| 0U, // ATOMIC_LOAD_XOR_I32 |
| 0U, // ATOMIC_LOAD_XOR_I64 |
| 0U, // ATOMIC_LOAD_XOR_I8 |
| 0U, // ATOMIC_SWAP_I16 |
| 0U, // ATOMIC_SWAP_I32 |
| 0U, // ATOMIC_SWAP_I64 |
| 0U, // ATOMIC_SWAP_I8 |
| 0U, // ATTN |
| 0U, // B |
| 0U, // BA |
| 0U, // BC |
| 0U, // BCC |
| 0U, // BCCA |
| 0U, // BCCCTR |
| 0U, // BCCCTR8 |
| 0U, // BCCCTRL |
| 0U, // BCCCTRL8 |
| 0U, // BCCL |
| 0U, // BCCLA |
| 0U, // BCCLR |
| 0U, // BCCLRL |
| 0U, // BCCTR |
| 0U, // BCCTR8 |
| 0U, // BCCTR8n |
| 0U, // BCCTRL |
| 0U, // BCCTRL8 |
| 0U, // BCCTRL8n |
| 0U, // BCCTRLn |
| 0U, // BCCTRn |
| 0U, // BCDADD_rec |
| 0U, // BCDCFN_rec |
| 0U, // BCDCFSQ_rec |
| 0U, // BCDCFZ_rec |
| 0U, // BCDCPSGN_rec |
| 0U, // BCDCTN_rec |
| 0U, // BCDCTSQ_rec |
| 0U, // BCDCTZ_rec |
| 0U, // BCDSETSGN_rec |
| 0U, // BCDSR_rec |
| 0U, // BCDSUB_rec |
| 0U, // BCDS_rec |
| 0U, // BCDTRUNC_rec |
| 0U, // BCDUS_rec |
| 0U, // BCDUTRUNC_rec |
| 0U, // BCL |
| 0U, // BCLR |
| 0U, // BCLRL |
| 0U, // BCLRLn |
| 0U, // BCLRn |
| 0U, // BCLalways |
| 0U, // BCLn |
| 0U, // BCTR |
| 0U, // BCTR8 |
| 0U, // BCTRL |
| 0U, // BCTRL8 |
| 0U, // BCTRL8_LDinto_toc |
| 0U, // BCTRL8_LDinto_toc_RM |
| 0U, // BCTRL8_RM |
| 0U, // BCTRL_LWZinto_toc |
| 0U, // BCTRL_LWZinto_toc_RM |
| 0U, // BCTRL_RM |
| 0U, // BCn |
| 0U, // BDNZ |
| 0U, // BDNZ8 |
| 0U, // BDNZA |
| 0U, // BDNZAm |
| 0U, // BDNZAp |
| 0U, // BDNZL |
| 0U, // BDNZLA |
| 0U, // BDNZLAm |
| 0U, // BDNZLAp |
| 0U, // BDNZLR |
| 0U, // BDNZLR8 |
| 0U, // BDNZLRL |
| 0U, // BDNZLRLm |
| 0U, // BDNZLRLp |
| 0U, // BDNZLRm |
| 0U, // BDNZLRp |
| 0U, // BDNZLm |
| 0U, // BDNZLp |
| 0U, // BDNZm |
| 0U, // BDNZp |
| 0U, // BDZ |
| 0U, // BDZ8 |
| 0U, // BDZA |
| 0U, // BDZAm |
| 0U, // BDZAp |
| 0U, // BDZL |
| 0U, // BDZLA |
| 0U, // BDZLAm |
| 0U, // BDZLAp |
| 0U, // BDZLR |
| 0U, // BDZLR8 |
| 0U, // BDZLRL |
| 0U, // BDZLRLm |
| 0U, // BDZLRLp |
| 0U, // BDZLRm |
| 0U, // BDZLRp |
| 0U, // BDZLm |
| 0U, // BDZLp |
| 0U, // BDZm |
| 0U, // BDZp |
| 0U, // BL |
| 0U, // BL8 |
| 0U, // BL8_NOP |
| 0U, // BL8_NOP_RM |
| 0U, // BL8_NOP_TLS |
| 0U, // BL8_NOTOC |
| 0U, // BL8_NOTOC_RM |
| 0U, // BL8_NOTOC_TLS |
| 0U, // BL8_RM |
| 0U, // BL8_TLS |
| 0U, // BL8_TLS_ |
| 0U, // BLA |
| 0U, // BLA8 |
| 0U, // BLA8_NOP |
| 0U, // BLA8_NOP_RM |
| 0U, // BLA8_RM |
| 0U, // BLA_RM |
| 0U, // BLR |
| 0U, // BLR8 |
| 0U, // BLRL |
| 0U, // BL_NOP |
| 0U, // BL_NOP_RM |
| 0U, // BL_RM |
| 0U, // BL_TLS |
| 0U, // BPERMD |
| 0U, // BRD |
| 0U, // BRH |
| 0U, // BRH8 |
| 0U, // BRINC |
| 0U, // BRW |
| 0U, // BRW8 |
| 0U, // CFUGED |
| 0U, // CLRBHRB |
| 0U, // CMPB |
| 0U, // CMPB8 |
| 0U, // CMPD |
| 0U, // CMPDI |
| 0U, // CMPEQB |
| 0U, // CMPLD |
| 0U, // CMPLDI |
| 0U, // CMPLW |
| 0U, // CMPLWI |
| 0U, // CMPRB |
| 0U, // CMPRB8 |
| 0U, // CMPW |
| 0U, // CMPWI |
| 0U, // CNTLZD |
| 0U, // CNTLZDM |
| 0U, // CNTLZD_rec |
| 0U, // CNTLZW |
| 0U, // CNTLZW8 |
| 0U, // CNTLZW8_rec |
| 0U, // CNTLZW_rec |
| 0U, // CNTTZD |
| 0U, // CNTTZDM |
| 0U, // CNTTZD_rec |
| 0U, // CNTTZW |
| 0U, // CNTTZW8 |
| 0U, // CNTTZW8_rec |
| 0U, // CNTTZW_rec |
| 0U, // CP_ABORT |
| 0U, // CP_COPY |
| 0U, // CP_COPY8 |
| 0U, // CP_PASTE8_rec |
| 0U, // CP_PASTE_rec |
| 0U, // CR6SET |
| 0U, // CR6UNSET |
| 0U, // CRAND |
| 0U, // CRANDC |
| 0U, // CREQV |
| 0U, // CRNAND |
| 0U, // CRNOR |
| 0U, // CRNOT |
| 0U, // CROR |
| 0U, // CRORC |
| 0U, // CRSET |
| 0U, // CRUNSET |
| 0U, // CRXOR |
| 0U, // CTRL_DEP |
| 0U, // DARN |
| 0U, // DCBA |
| 0U, // DCBF |
| 0U, // DCBFEP |
| 0U, // DCBI |
| 0U, // DCBST |
| 0U, // DCBSTEP |
| 0U, // DCBT |
| 0U, // DCBTEP |
| 0U, // DCBTST |
| 0U, // DCBTSTEP |
| 0U, // DCBZ |
| 0U, // DCBZEP |
| 0U, // DCBZL |
| 0U, // DCBZLEP |
| 0U, // DCCCI |
| 0U, // DIVD |
| 0U, // DIVDE |
| 0U, // DIVDEO |
| 0U, // DIVDEO_rec |
| 0U, // DIVDEU |
| 0U, // DIVDEUO |
| 0U, // DIVDEUO_rec |
| 0U, // DIVDEU_rec |
| 0U, // DIVDE_rec |
| 0U, // DIVDO |
| 0U, // DIVDO_rec |
| 0U, // DIVDU |
| 0U, // DIVDUO |
| 0U, // DIVDUO_rec |
| 0U, // DIVDU_rec |
| 0U, // DIVD_rec |
| 0U, // DIVW |
| 0U, // DIVWE |
| 0U, // DIVWEO |
| 0U, // DIVWEO_rec |
| 0U, // DIVWEU |
| 0U, // DIVWEUO |
| 0U, // DIVWEUO_rec |
| 0U, // DIVWEU_rec |
| 0U, // DIVWE_rec |
| 0U, // DIVWO |
| 0U, // DIVWO_rec |
| 0U, // DIVWU |
| 0U, // DIVWUO |
| 0U, // DIVWUO_rec |
| 0U, // DIVWU_rec |
| 0U, // DIVW_rec |
| 0U, // DMMR |
| 0U, // DMSETDMRZ |
| 0U, // DMXOR |
| 0U, // DMXXEXTFDMR256 |
| 0U, // DMXXEXTFDMR512 |
| 0U, // DMXXEXTFDMR512_HI |
| 0U, // DMXXINSTFDMR256 |
| 0U, // DMXXINSTFDMR512 |
| 0U, // DMXXINSTFDMR512_HI |
| 0U, // DSS |
| 0U, // DSSALL |
| 0U, // DST |
| 0U, // DST64 |
| 0U, // DSTST |
| 0U, // DSTST64 |
| 0U, // DSTSTT |
| 0U, // DSTSTT64 |
| 0U, // DSTT |
| 0U, // DSTT64 |
| 0U, // DYNALLOC |
| 0U, // DYNALLOC8 |
| 0U, // DYNAREAOFFSET |
| 0U, // DYNAREAOFFSET8 |
| 0U, // DecreaseCTR8loop |
| 0U, // DecreaseCTRloop |
| 0U, // EFDABS |
| 0U, // EFDADD |
| 0U, // EFDCFS |
| 0U, // EFDCFSF |
| 0U, // EFDCFSI |
| 0U, // EFDCFSID |
| 0U, // EFDCFUF |
| 0U, // EFDCFUI |
| 0U, // EFDCFUID |
| 0U, // EFDCMPEQ |
| 0U, // EFDCMPGT |
| 0U, // EFDCMPLT |
| 0U, // EFDCTSF |
| 0U, // EFDCTSI |
| 0U, // EFDCTSIDZ |
| 0U, // EFDCTSIZ |
| 0U, // EFDCTUF |
| 0U, // EFDCTUI |
| 0U, // EFDCTUIDZ |
| 0U, // EFDCTUIZ |
| 0U, // EFDDIV |
| 0U, // EFDMUL |
| 0U, // EFDNABS |
| 0U, // EFDNEG |
| 0U, // EFDSUB |
| 0U, // EFDTSTEQ |
| 0U, // EFDTSTGT |
| 0U, // EFDTSTLT |
| 0U, // EFSABS |
| 0U, // EFSADD |
| 0U, // EFSCFD |
| 0U, // EFSCFSF |
| 0U, // EFSCFSI |
| 0U, // EFSCFUF |
| 0U, // EFSCFUI |
| 0U, // EFSCMPEQ |
| 0U, // EFSCMPGT |
| 0U, // EFSCMPLT |
| 0U, // EFSCTSF |
| 0U, // EFSCTSI |
| 0U, // EFSCTSIZ |
| 0U, // EFSCTUF |
| 0U, // EFSCTUI |
| 0U, // EFSCTUIZ |
| 0U, // EFSDIV |
| 0U, // EFSMUL |
| 0U, // EFSNABS |
| 0U, // EFSNEG |
| 0U, // EFSSUB |
| 0U, // EFSTSTEQ |
| 0U, // EFSTSTGT |
| 0U, // EFSTSTLT |
| 0U, // EH_SjLj_LongJmp32 |
| 0U, // EH_SjLj_LongJmp64 |
| 0U, // EH_SjLj_SetJmp32 |
| 0U, // EH_SjLj_SetJmp64 |
| 0U, // EH_SjLj_Setup |
| 0U, // EQV |
| 0U, // EQV8 |
| 0U, // EQV8_rec |
| 0U, // EQV_rec |
| 0U, // EVABS |
| 0U, // EVADDIW |
| 0U, // EVADDSMIAAW |
| 0U, // EVADDSSIAAW |
| 0U, // EVADDUMIAAW |
| 0U, // EVADDUSIAAW |
| 0U, // EVADDW |
| 0U, // EVAND |
| 0U, // EVANDC |
| 0U, // EVCMPEQ |
| 0U, // EVCMPGTS |
| 0U, // EVCMPGTU |
| 0U, // EVCMPLTS |
| 0U, // EVCMPLTU |
| 0U, // EVCNTLSW |
| 0U, // EVCNTLZW |
| 0U, // EVDIVWS |
| 0U, // EVDIVWU |
| 0U, // EVEQV |
| 0U, // EVEXTSB |
| 0U, // EVEXTSH |
| 0U, // EVFSABS |
| 0U, // EVFSADD |
| 0U, // EVFSCFSF |
| 0U, // EVFSCFSI |
| 0U, // EVFSCFUF |
| 0U, // EVFSCFUI |
| 0U, // EVFSCMPEQ |
| 0U, // EVFSCMPGT |
| 0U, // EVFSCMPLT |
| 0U, // EVFSCTSF |
| 0U, // EVFSCTSI |
| 0U, // EVFSCTSIZ |
| 0U, // EVFSCTUF |
| 0U, // EVFSCTUI |
| 0U, // EVFSCTUIZ |
| 0U, // EVFSDIV |
| 0U, // EVFSMUL |
| 0U, // EVFSNABS |
| 0U, // EVFSNEG |
| 0U, // EVFSSUB |
| 0U, // EVFSTSTEQ |
| 0U, // EVFSTSTGT |
| 0U, // EVFSTSTLT |
| 0U, // EVLDD |
| 0U, // EVLDDX |
| 0U, // EVLDH |
| 0U, // EVLDHX |
| 0U, // EVLDW |
| 0U, // EVLDWX |
| 0U, // EVLHHESPLAT |
| 0U, // EVLHHESPLATX |
| 0U, // EVLHHOSSPLAT |
| 0U, // EVLHHOSSPLATX |
| 0U, // EVLHHOUSPLAT |
| 0U, // EVLHHOUSPLATX |
| 0U, // EVLWHE |
| 0U, // EVLWHEX |
| 0U, // EVLWHOS |
| 0U, // EVLWHOSX |
| 0U, // EVLWHOU |
| 0U, // EVLWHOUX |
| 0U, // EVLWHSPLAT |
| 0U, // EVLWHSPLATX |
| 0U, // EVLWWSPLAT |
| 0U, // EVLWWSPLATX |
| 0U, // EVMERGEHI |
| 0U, // EVMERGEHILO |
| 0U, // EVMERGELO |
| 0U, // EVMERGELOHI |
| 0U, // EVMHEGSMFAA |
| 0U, // EVMHEGSMFAN |
| 0U, // EVMHEGSMIAA |
| 0U, // EVMHEGSMIAN |
| 0U, // EVMHEGUMIAA |
| 0U, // EVMHEGUMIAN |
| 0U, // EVMHESMF |
| 0U, // EVMHESMFA |
| 0U, // EVMHESMFAAW |
| 0U, // EVMHESMFANW |
| 0U, // EVMHESMI |
| 0U, // EVMHESMIA |
| 0U, // EVMHESMIAAW |
| 0U, // EVMHESMIANW |
| 0U, // EVMHESSF |
| 0U, // EVMHESSFA |
| 0U, // EVMHESSFAAW |
| 0U, // EVMHESSFANW |
| 0U, // EVMHESSIAAW |
| 0U, // EVMHESSIANW |
| 0U, // EVMHEUMI |
| 0U, // EVMHEUMIA |
| 0U, // EVMHEUMIAAW |
| 0U, // EVMHEUMIANW |
| 0U, // EVMHEUSIAAW |
| 0U, // EVMHEUSIANW |
| 0U, // EVMHOGSMFAA |
| 0U, // EVMHOGSMFAN |
| 0U, // EVMHOGSMIAA |
| 0U, // EVMHOGSMIAN |
| 0U, // EVMHOGUMIAA |
| 0U, // EVMHOGUMIAN |
| 0U, // EVMHOSMF |
| 0U, // EVMHOSMFA |
| 0U, // EVMHOSMFAAW |
| 0U, // EVMHOSMFANW |
| 0U, // EVMHOSMI |
| 0U, // EVMHOSMIA |
| 0U, // EVMHOSMIAAW |
| 0U, // EVMHOSMIANW |
| 0U, // EVMHOSSF |
| 0U, // EVMHOSSFA |
| 0U, // EVMHOSSFAAW |
| 0U, // EVMHOSSFANW |
| 0U, // EVMHOSSIAAW |
| 0U, // EVMHOSSIANW |
| 0U, // EVMHOUMI |
| 0U, // EVMHOUMIA |
| 0U, // EVMHOUMIAAW |
| 0U, // EVMHOUMIANW |
| 0U, // EVMHOUSIAAW |
| 0U, // EVMHOUSIANW |
| 0U, // EVMRA |
| 0U, // EVMWHSMF |
| 0U, // EVMWHSMFA |
| 0U, // EVMWHSMI |
| 0U, // EVMWHSMIA |
| 0U, // EVMWHSSF |
| 0U, // EVMWHSSFA |
| 0U, // EVMWHUMI |
| 0U, // EVMWHUMIA |
| 0U, // EVMWLSMIAAW |
| 0U, // EVMWLSMIANW |
| 0U, // EVMWLSSIAAW |
| 0U, // EVMWLSSIANW |
| 0U, // EVMWLUMI |
| 0U, // EVMWLUMIA |
| 0U, // EVMWLUMIAAW |
| 0U, // EVMWLUMIANW |
| 0U, // EVMWLUSIAAW |
| 0U, // EVMWLUSIANW |
| 0U, // EVMWSMF |
| 0U, // EVMWSMFA |
| 0U, // EVMWSMFAA |
| 0U, // EVMWSMFAN |
| 0U, // EVMWSMI |
| 0U, // EVMWSMIA |
| 0U, // EVMWSMIAA |
| 0U, // EVMWSMIAN |
| 0U, // EVMWSSF |
| 0U, // EVMWSSFA |
| 0U, // EVMWSSFAA |
| 0U, // EVMWSSFAN |
| 0U, // EVMWUMI |
| 0U, // EVMWUMIA |
| 0U, // EVMWUMIAA |
| 0U, // EVMWUMIAN |
| 0U, // EVNAND |
| 0U, // EVNEG |
| 0U, // EVNOR |
| 0U, // EVOR |
| 0U, // EVORC |
| 0U, // EVRLW |
| 0U, // EVRLWI |
| 0U, // EVRNDW |
| 0U, // EVSEL |
| 0U, // EVSLW |
| 0U, // EVSLWI |
| 0U, // EVSPLATFI |
| 0U, // EVSPLATI |
| 0U, // EVSRWIS |
| 0U, // EVSRWIU |
| 0U, // EVSRWS |
| 0U, // EVSRWU |
| 0U, // EVSTDD |
| 0U, // EVSTDDX |
| 0U, // EVSTDH |
| 0U, // EVSTDHX |
| 0U, // EVSTDW |
| 0U, // EVSTDWX |
| 0U, // EVSTWHE |
| 0U, // EVSTWHEX |
| 0U, // EVSTWHO |
| 0U, // EVSTWHOX |
| 0U, // EVSTWWE |
| 0U, // EVSTWWEX |
| 0U, // EVSTWWO |
| 0U, // EVSTWWOX |
| 0U, // EVSUBFSMIAAW |
| 0U, // EVSUBFSSIAAW |
| 0U, // EVSUBFUMIAAW |
| 0U, // EVSUBFUSIAAW |
| 0U, // EVSUBFW |
| 0U, // EVSUBIFW |
| 0U, // EVXOR |
| 0U, // EXTSB |
| 0U, // EXTSB8 |
| 0U, // EXTSB8_32_64 |
| 0U, // EXTSB8_rec |
| 0U, // EXTSB_rec |
| 0U, // EXTSH |
| 0U, // EXTSH8 |
| 0U, // EXTSH8_32_64 |
| 0U, // EXTSH8_rec |
| 0U, // EXTSH_rec |
| 0U, // EXTSW |
| 0U, // EXTSWSLI |
| 0U, // EXTSWSLI_32_64 |
| 0U, // EXTSWSLI_32_64_rec |
| 0U, // EXTSWSLI_rec |
| 0U, // EXTSW_32 |
| 0U, // EXTSW_32_64 |
| 0U, // EXTSW_32_64_rec |
| 0U, // EXTSW_rec |
| 0U, // EnforceIEIO |
| 0U, // FABSD |
| 0U, // FABSD_rec |
| 0U, // FABSS |
| 0U, // FABSS_rec |
| 0U, // FADD |
| 0U, // FADDS |
| 0U, // FADDS_rec |
| 0U, // FADD_rec |
| 0U, // FADDrtz |
| 0U, // FCFID |
| 0U, // FCFIDS |
| 0U, // FCFIDS_rec |
| 0U, // FCFIDU |
| 0U, // FCFIDUS |
| 0U, // FCFIDUS_rec |
| 0U, // FCFIDU_rec |
| 0U, // FCFID_rec |
| 0U, // FCMPOD |
| 0U, // FCMPOS |
| 0U, // FCMPUD |
| 0U, // FCMPUS |
| 0U, // FCPSGND |
| 0U, // FCPSGND_rec |
| 0U, // FCPSGNS |
| 0U, // FCPSGNS_rec |
| 0U, // FCTID |
| 0U, // FCTIDU |
| 0U, // FCTIDUZ |
| 0U, // FCTIDUZ_rec |
| 0U, // FCTIDU_rec |
| 0U, // FCTIDZ |
| 0U, // FCTIDZ_rec |
| 0U, // FCTID_rec |
| 0U, // FCTIW |
| 0U, // FCTIWU |
| 0U, // FCTIWUZ |
| 0U, // FCTIWUZ_rec |
| 0U, // FCTIWU_rec |
| 0U, // FCTIWZ |
| 0U, // FCTIWZ_rec |
| 0U, // FCTIW_rec |
| 0U, // FDIV |
| 0U, // FDIVS |
| 0U, // FDIVS_rec |
| 0U, // FDIV_rec |
| 0U, // FMADD |
| 0U, // FMADDS |
| 0U, // FMADDS_rec |
| 0U, // FMADD_rec |
| 0U, // FMR |
| 0U, // FMR_rec |
| 0U, // FMSUB |
| 0U, // FMSUBS |
| 0U, // FMSUBS_rec |
| 0U, // FMSUB_rec |
| 0U, // FMUL |
| 0U, // FMULS |
| 0U, // FMULS_rec |
| 0U, // FMUL_rec |
| 0U, // FNABSD |
| 0U, // FNABSD_rec |
| 0U, // FNABSS |
| 0U, // FNABSS_rec |
| 0U, // FNEGD |
| 0U, // FNEGD_rec |
| 0U, // FNEGS |
| 0U, // FNEGS_rec |
| 0U, // FNMADD |
| 0U, // FNMADDS |
| 0U, // FNMADDS_rec |
| 0U, // FNMADD_rec |
| 0U, // FNMSUB |
| 0U, // FNMSUBS |
| 0U, // FNMSUBS_rec |
| 0U, // FNMSUB_rec |
| 0U, // FRE |
| 0U, // FRES |
| 0U, // FRES_rec |
| 0U, // FRE_rec |
| 0U, // FRIMD |
| 0U, // FRIMD_rec |
| 0U, // FRIMS |
| 0U, // FRIMS_rec |
| 0U, // FRIND |
| 0U, // FRIND_rec |
| 0U, // FRINS |
| 0U, // FRINS_rec |
| 0U, // FRIPD |
| 0U, // FRIPD_rec |
| 0U, // FRIPS |
| 0U, // FRIPS_rec |
| 0U, // FRIZD |
| 0U, // FRIZD_rec |
| 0U, // FRIZS |
| 0U, // FRIZS_rec |
| 0U, // FRSP |
| 0U, // FRSP_rec |
| 0U, // FRSQRTE |
| 0U, // FRSQRTES |
| 0U, // FRSQRTES_rec |
| 0U, // FRSQRTE_rec |
| 0U, // FSELD |
| 0U, // FSELD_rec |
| 0U, // FSELS |
| 0U, // FSELS_rec |
| 0U, // FSQRT |
| 0U, // FSQRTS |
| 0U, // FSQRTS_rec |
| 0U, // FSQRT_rec |
| 0U, // FSUB |
| 0U, // FSUBS |
| 0U, // FSUBS_rec |
| 0U, // FSUB_rec |
| 0U, // FTDIV |
| 0U, // FTSQRT |
| 0U, // GETtlsADDR |
| 0U, // GETtlsADDR32 |
| 0U, // GETtlsADDR32AIX |
| 0U, // GETtlsADDR64AIX |
| 0U, // GETtlsADDRPCREL |
| 0U, // GETtlsldADDR |
| 0U, // GETtlsldADDR32 |
| 0U, // GETtlsldADDRPCREL |
| 0U, // HASHCHK |
| 0U, // HASHCHK8 |
| 0U, // HASHCHKP |
| 0U, // HASHCHKP8 |
| 0U, // HASHST |
| 0U, // HASHST8 |
| 0U, // HASHSTP |
| 0U, // HASHSTP8 |
| 0U, // HRFID |
| 0U, // ICBI |
| 0U, // ICBIEP |
| 0U, // ICBLC |
| 0U, // ICBLQ |
| 0U, // ICBT |
| 0U, // ICBTLS |
| 0U, // ICCCI |
| 0U, // ISEL |
| 0U, // ISEL8 |
| 0U, // ISYNC |
| 0U, // LA |
| 0U, // LA8 |
| 0U, // LBARX |
| 0U, // LBARXL |
| 0U, // LBEPX |
| 0U, // LBZ |
| 0U, // LBZ8 |
| 0U, // LBZCIX |
| 0U, // LBZU |
| 0U, // LBZU8 |
| 0U, // LBZUX |
| 0U, // LBZUX8 |
| 0U, // LBZX |
| 0U, // LBZX8 |
| 0U, // LBZXTLS |
| 0U, // LBZXTLS_ |
| 0U, // LBZXTLS_32 |
| 0U, // LD |
| 0U, // LDARX |
| 0U, // LDARXL |
| 0U, // LDAT |
| 0U, // LDBRX |
| 0U, // LDCIX |
| 0U, // LDU |
| 0U, // LDUX |
| 0U, // LDX |
| 0U, // LDXTLS |
| 0U, // LDXTLS_ |
| 0U, // LDgotTprelL |
| 0U, // LDgotTprelL32 |
| 0U, // LDtoc |
| 0U, // LDtocBA |
| 0U, // LDtocCPT |
| 0U, // LDtocJTI |
| 0U, // LDtocL |
| 0U, // LFD |
| 0U, // LFDEPX |
| 0U, // LFDU |
| 0U, // LFDUX |
| 0U, // LFDX |
| 0U, // LFIWAX |
| 0U, // LFIWZX |
| 0U, // LFS |
| 0U, // LFSU |
| 0U, // LFSUX |
| 0U, // LFSX |
| 0U, // LHA |
| 0U, // LHA8 |
| 0U, // LHARX |
| 0U, // LHARXL |
| 0U, // LHAU |
| 0U, // LHAU8 |
| 0U, // LHAUX |
| 0U, // LHAUX8 |
| 0U, // LHAX |
| 0U, // LHAX8 |
| 0U, // LHBRX |
| 0U, // LHBRX8 |
| 0U, // LHEPX |
| 0U, // LHZ |
| 0U, // LHZ8 |
| 0U, // LHZCIX |
| 0U, // LHZU |
| 0U, // LHZU8 |
| 0U, // LHZUX |
| 0U, // LHZUX8 |
| 0U, // LHZX |
| 0U, // LHZX8 |
| 0U, // LHZXTLS |
| 0U, // LHZXTLS_ |
| 0U, // LHZXTLS_32 |
| 0U, // LI |
| 0U, // LI8 |
| 0U, // LIS |
| 0U, // LIS8 |
| 0U, // LMW |
| 0U, // LQ |
| 0U, // LQARX |
| 0U, // LQARXL |
| 0U, // LQX_PSEUDO |
| 0U, // LSWI |
| 0U, // LVEBX |
| 0U, // LVEHX |
| 0U, // LVEWX |
| 0U, // LVSL |
| 0U, // LVSR |
| 0U, // LVX |
| 0U, // LVXL |
| 0U, // LWA |
| 0U, // LWARX |
| 0U, // LWARXL |
| 0U, // LWAT |
| 0U, // LWAUX |
| 0U, // LWAX |
| 0U, // LWAX_32 |
| 0U, // LWA_32 |
| 0U, // LWBRX |
| 0U, // LWBRX8 |
| 0U, // LWEPX |
| 0U, // LWZ |
| 0U, // LWZ8 |
| 0U, // LWZCIX |
| 0U, // LWZU |
| 0U, // LWZU8 |
| 0U, // LWZUX |
| 0U, // LWZUX8 |
| 0U, // LWZX |
| 0U, // LWZX8 |
| 0U, // LWZXTLS |
| 0U, // LWZXTLS_ |
| 0U, // LWZXTLS_32 |
| 0U, // LWZtoc |
| 0U, // LWZtocL |
| 0U, // LXSD |
| 0U, // LXSDX |
| 0U, // LXSIBZX |
| 0U, // LXSIHZX |
| 0U, // LXSIWAX |
| 0U, // LXSIWZX |
| 0U, // LXSSP |
| 0U, // LXSSPX |
| 0U, // LXV |
| 0U, // LXVB16X |
| 0U, // LXVD2X |
| 0U, // LXVDSX |
| 0U, // LXVH8X |
| 0U, // LXVKQ |
| 0U, // LXVL |
| 0U, // LXVLL |
| 0U, // LXVP |
| 0U, // LXVPRL |
| 0U, // LXVPRLL |
| 0U, // LXVPX |
| 0U, // LXVRBX |
| 0U, // LXVRDX |
| 0U, // LXVRHX |
| 0U, // LXVRL |
| 0U, // LXVRLL |
| 0U, // LXVRWX |
| 0U, // LXVW4X |
| 0U, // LXVWSX |
| 0U, // LXVX |
| 0U, // MADDHD |
| 0U, // MADDHDU |
| 0U, // MADDLD |
| 0U, // MADDLD8 |
| 0U, // MBAR |
| 0U, // MCRF |
| 0U, // MCRFS |
| 0U, // MCRXRX |
| 0U, // MFBHRBE |
| 0U, // MFCR |
| 0U, // MFCR8 |
| 0U, // MFCTR |
| 0U, // MFCTR8 |
| 0U, // MFDCR |
| 0U, // MFFS |
| 0U, // MFFSCDRN |
| 0U, // MFFSCDRNI |
| 0U, // MFFSCE |
| 0U, // MFFSCRN |
| 0U, // MFFSCRNI |
| 0U, // MFFSL |
| 0U, // MFFS_rec |
| 0U, // MFLR |
| 0U, // MFLR8 |
| 0U, // MFMSR |
| 0U, // MFOCRF |
| 0U, // MFOCRF8 |
| 0U, // MFPMR |
| 0U, // MFSPR |
| 0U, // MFSPR8 |
| 0U, // MFSR |
| 0U, // MFSRIN |
| 0U, // MFTB |
| 0U, // MFTB8 |
| 0U, // MFUDSCR |
| 0U, // MFVRD |
| 0U, // MFVRSAVE |
| 0U, // MFVRSAVEv |
| 0U, // MFVRWZ |
| 0U, // MFVSCR |
| 0U, // MFVSRD |
| 0U, // MFVSRLD |
| 0U, // MFVSRWZ |
| 0U, // MODSD |
| 0U, // MODSW |
| 0U, // MODUD |
| 0U, // MODUW |
| 0U, // MSGSYNC |
| 0U, // MSYNC |
| 0U, // MTCRF |
| 0U, // MTCRF8 |
| 0U, // MTCTR |
| 0U, // MTCTR8 |
| 0U, // MTCTR8loop |
| 0U, // MTCTRloop |
| 0U, // MTDCR |
| 0U, // MTFSB0 |
| 0U, // MTFSB1 |
| 0U, // MTFSF |
| 0U, // MTFSFI |
| 0U, // MTFSFI_rec |
| 0U, // MTFSFIb |
| 0U, // MTFSF_rec |
| 0U, // MTFSFb |
| 0U, // MTLR |
| 0U, // MTLR8 |
| 0U, // MTMSR |
| 0U, // MTMSRD |
| 0U, // MTOCRF |
| 0U, // MTOCRF8 |
| 0U, // MTPMR |
| 0U, // MTSPR |
| 0U, // MTSPR8 |
| 0U, // MTSR |
| 0U, // MTSRIN |
| 0U, // MTUDSCR |
| 0U, // MTVRD |
| 0U, // MTVRSAVE |
| 0U, // MTVRSAVEv |
| 0U, // MTVRWA |
| 0U, // MTVRWZ |
| 0U, // MTVSCR |
| 0U, // MTVSRBM |
| 0U, // MTVSRBMI |
| 0U, // MTVSRD |
| 0U, // MTVSRDD |
| 0U, // MTVSRDM |
| 0U, // MTVSRHM |
| 0U, // MTVSRQM |
| 0U, // MTVSRWA |
| 0U, // MTVSRWM |
| 0U, // MTVSRWS |
| 0U, // MTVSRWZ |
| 0U, // MULHD |
| 0U, // MULHDU |
| 0U, // MULHDU_rec |
| 0U, // MULHD_rec |
| 0U, // MULHW |
| 0U, // MULHWU |
| 0U, // MULHWU_rec |
| 0U, // MULHW_rec |
| 0U, // MULLD |
| 0U, // MULLDO |
| 0U, // MULLDO_rec |
| 0U, // MULLD_rec |
| 0U, // MULLI |
| 0U, // MULLI8 |
| 0U, // MULLW |
| 0U, // MULLWO |
| 0U, // MULLWO_rec |
| 0U, // MULLW_rec |
| 0U, // MoveGOTtoLR |
| 0U, // MovePCtoLR |
| 0U, // MovePCtoLR8 |
| 0U, // NAND |
| 0U, // NAND8 |
| 0U, // NAND8_rec |
| 0U, // NAND_rec |
| 0U, // NAP |
| 0U, // NEG |
| 0U, // NEG8 |
| 0U, // NEG8O |
| 0U, // NEG8O_rec |
| 0U, // NEG8_rec |
| 0U, // NEGO |
| 0U, // NEGO_rec |
| 0U, // NEG_rec |
| 0U, // NOP |
| 0U, // NOP_GT_PWR6 |
| 0U, // NOP_GT_PWR7 |
| 0U, // NOR |
| 0U, // NOR8 |
| 0U, // NOR8_rec |
| 0U, // NOR_rec |
| 0U, // OR |
| 0U, // OR8 |
| 0U, // OR8_rec |
| 0U, // ORC |
| 0U, // ORC8 |
| 0U, // ORC8_rec |
| 0U, // ORC_rec |
| 0U, // ORI |
| 0U, // ORI8 |
| 0U, // ORIS |
| 0U, // ORIS8 |
| 0U, // OR_rec |
| 0U, // PADDI |
| 0U, // PADDI8 |
| 0U, // PADDI8pc |
| 0U, // PADDIdtprel |
| 0U, // PADDIpc |
| 0U, // PDEPD |
| 0U, // PEXTD |
| 0U, // PLBZ |
| 0U, // PLBZ8 |
| 0U, // PLBZ8pc |
| 0U, // PLBZpc |
| 0U, // PLD |
| 0U, // PLDpc |
| 0U, // PLFD |
| 0U, // PLFDpc |
| 0U, // PLFS |
| 0U, // PLFSpc |
| 0U, // PLHA |
| 0U, // PLHA8 |
| 0U, // PLHA8pc |
| 0U, // PLHApc |
| 0U, // PLHZ |
| 0U, // PLHZ8 |
| 0U, // PLHZ8pc |
| 0U, // PLHZpc |
| 0U, // PLI |
| 0U, // PLI8 |
| 0U, // PLWA |
| 0U, // PLWA8 |
| 0U, // PLWA8pc |
| 0U, // PLWApc |
| 0U, // PLWZ |
| 0U, // PLWZ8 |
| 0U, // PLWZ8pc |
| 0U, // PLWZpc |
| 0U, // PLXSD |
| 0U, // PLXSDpc |
| 0U, // PLXSSP |
| 0U, // PLXSSPpc |
| 0U, // PLXV |
| 0U, // PLXVP |
| 0U, // PLXVPpc |
| 0U, // PLXVpc |
| 0U, // PMXVBF16GER2 |
| 2U, // PMXVBF16GER2NN |
| 2U, // PMXVBF16GER2NP |
| 2U, // PMXVBF16GER2PN |
| 2U, // PMXVBF16GER2PP |
| 0U, // PMXVBF16GER2W |
| 2U, // PMXVBF16GER2WNN |
| 2U, // PMXVBF16GER2WNP |
| 2U, // PMXVBF16GER2WPN |
| 2U, // PMXVBF16GER2WPP |
| 0U, // PMXVF16GER2 |
| 2U, // PMXVF16GER2NN |
| 2U, // PMXVF16GER2NP |
| 2U, // PMXVF16GER2PN |
| 2U, // PMXVF16GER2PP |
| 0U, // PMXVF16GER2W |
| 2U, // PMXVF16GER2WNN |
| 2U, // PMXVF16GER2WNP |
| 2U, // PMXVF16GER2WPN |
| 2U, // PMXVF16GER2WPP |
| 4U, // PMXVF32GER |
| 0U, // PMXVF32GERNN |
| 0U, // PMXVF32GERNP |
| 0U, // PMXVF32GERPN |
| 0U, // PMXVF32GERPP |
| 4U, // PMXVF32GERW |
| 0U, // PMXVF32GERWNN |
| 0U, // PMXVF32GERWNP |
| 0U, // PMXVF32GERWPN |
| 0U, // PMXVF32GERWPP |
| 0U, // PMXVF64GER |
| 0U, // PMXVF64GERNN |
| 0U, // PMXVF64GERNP |
| 0U, // PMXVF64GERPN |
| 0U, // PMXVF64GERPP |
| 0U, // PMXVF64GERW |
| 0U, // PMXVF64GERWNN |
| 0U, // PMXVF64GERWNP |
| 0U, // PMXVF64GERWPN |
| 0U, // PMXVF64GERWPP |
| 0U, // PMXVI16GER2 |
| 2U, // PMXVI16GER2PP |
| 0U, // PMXVI16GER2S |
| 2U, // PMXVI16GER2SPP |
| 0U, // PMXVI16GER2SW |
| 2U, // PMXVI16GER2SWPP |
| 0U, // PMXVI16GER2W |
| 2U, // PMXVI16GER2WPP |
| 16U, // PMXVI4GER8 |
| 6U, // PMXVI4GER8PP |
| 16U, // PMXVI4GER8W |
| 6U, // PMXVI4GER8WPP |
| 32U, // PMXVI8GER4 |
| 8U, // PMXVI8GER4PP |
| 8U, // PMXVI8GER4SPP |
| 32U, // PMXVI8GER4W |
| 8U, // PMXVI8GER4WPP |
| 8U, // PMXVI8GER4WSPP |
| 0U, // POPCNTB |
| 0U, // POPCNTB8 |
| 0U, // POPCNTD |
| 0U, // POPCNTW |
| 0U, // PPC32GOT |
| 0U, // PPC32PICGOT |
| 0U, // PREPARE_PROBED_ALLOCA_32 |
| 0U, // PREPARE_PROBED_ALLOCA_64 |
| 0U, // PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_32 |
| 0U, // PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_64 |
| 0U, // PROBED_ALLOCA_32 |
| 0U, // PROBED_ALLOCA_64 |
| 0U, // PROBED_STACKALLOC_32 |
| 0U, // PROBED_STACKALLOC_64 |
| 0U, // PSTB |
| 0U, // PSTB8 |
| 0U, // PSTB8pc |
| 0U, // PSTBpc |
| 0U, // PSTD |
| 0U, // PSTDpc |
| 0U, // PSTFD |
| 0U, // PSTFDpc |
| 0U, // PSTFS |
| 0U, // PSTFSpc |
| 0U, // PSTH |
| 0U, // PSTH8 |
| 0U, // PSTH8pc |
| 0U, // PSTHpc |
| 0U, // PSTW |
| 0U, // PSTW8 |
| 0U, // PSTW8pc |
| 0U, // PSTWpc |
| 0U, // PSTXSD |
| 0U, // PSTXSDpc |
| 0U, // PSTXSSP |
| 0U, // PSTXSSPpc |
| 0U, // PSTXV |
| 0U, // PSTXVP |
| 0U, // PSTXVPpc |
| 0U, // PSTXVpc |
| 0U, // PseudoEIEIO |
| 0U, // RESTORE_ACC |
| 0U, // RESTORE_CR |
| 0U, // RESTORE_CRBIT |
| 0U, // RESTORE_QUADWORD |
| 0U, // RESTORE_UACC |
| 0U, // RESTORE_WACC |
| 0U, // RFCI |
| 0U, // RFDI |
| 0U, // RFEBB |
| 0U, // RFI |
| 0U, // RFID |
| 0U, // RFMCI |
| 0U, // RLDCL |
| 0U, // RLDCL_rec |
| 0U, // RLDCR |
| 0U, // RLDCR_rec |
| 0U, // RLDIC |
| 0U, // RLDICL |
| 0U, // RLDICL_32 |
| 0U, // RLDICL_32_64 |
| 0U, // RLDICL_32_rec |
| 0U, // RLDICL_rec |
| 0U, // RLDICR |
| 0U, // RLDICR_32 |
| 0U, // RLDICR_rec |
| 0U, // RLDIC_rec |
| 0U, // RLDIMI |
| 0U, // RLDIMI_rec |
| 0U, // RLWIMI |
| 0U, // RLWIMI8 |
| 0U, // RLWIMI8_rec |
| 0U, // RLWIMI_rec |
| 1U, // RLWINM |
| 1U, // RLWINM8 |
| 1U, // RLWINM8_rec |
| 1U, // RLWINM_rec |
| 1U, // RLWNM |
| 1U, // RLWNM8 |
| 1U, // RLWNM8_rec |
| 1U, // RLWNM_rec |
| 0U, // ReadTB |
| 0U, // SC |
| 0U, // SELECT_CC_F16 |
| 0U, // SELECT_CC_F4 |
| 0U, // SELECT_CC_F8 |
| 0U, // SELECT_CC_I4 |
| 0U, // SELECT_CC_I8 |
| 0U, // SELECT_CC_SPE |
| 0U, // SELECT_CC_SPE4 |
| 0U, // SELECT_CC_VRRC |
| 0U, // SELECT_CC_VSFRC |
| 0U, // SELECT_CC_VSRC |
| 0U, // SELECT_CC_VSSRC |
| 0U, // SELECT_F16 |
| 0U, // SELECT_F4 |
| 0U, // SELECT_F8 |
| 0U, // SELECT_I4 |
| 0U, // SELECT_I8 |
| 0U, // SELECT_SPE |
| 0U, // SELECT_SPE4 |
| 0U, // SELECT_VRRC |
| 0U, // SELECT_VSFRC |
| 0U, // SELECT_VSRC |
| 0U, // SELECT_VSSRC |
| 0U, // SETB |
| 0U, // SETB8 |
| 0U, // SETBC |
| 0U, // SETBC8 |
| 0U, // SETBCR |
| 0U, // SETBCR8 |
| 0U, // SETFLM |
| 0U, // SETNBC |
| 0U, // SETNBC8 |
| 0U, // SETNBCR |
| 0U, // SETNBCR8 |
| 0U, // SETRND |
| 0U, // SETRNDi |
| 0U, // SLBFEE_rec |
| 0U, // SLBIA |
| 0U, // SLBIE |
| 0U, // SLBIEG |
| 0U, // SLBMFEE |
| 0U, // SLBMFEV |
| 0U, // SLBMTE |
| 0U, // SLBSYNC |
| 0U, // SLD |
| 0U, // SLD_rec |
| 0U, // SLW |
| 0U, // SLW8 |
| 0U, // SLW8_rec |
| 0U, // SLW_rec |
| 0U, // SPELWZ |
| 0U, // SPELWZX |
| 0U, // SPESTW |
| 0U, // SPESTWX |
| 0U, // SPILL_ACC |
| 0U, // SPILL_CR |
| 0U, // SPILL_CRBIT |
| 0U, // SPILL_QUADWORD |
| 0U, // SPILL_UACC |
| 0U, // SPILL_WACC |
| 0U, // SPLIT_QUADWORD |
| 0U, // SRAD |
| 0U, // SRADI |
| 0U, // SRADI_32 |
| 0U, // SRADI_rec |
| 0U, // SRAD_rec |
| 0U, // SRAW |
| 0U, // SRAWI |
| 0U, // SRAWI_rec |
| 0U, // SRAW_rec |
| 0U, // SRD |
| 0U, // SRD_rec |
| 0U, // SRW |
| 0U, // SRW8 |
| 0U, // SRW8_rec |
| 0U, // SRW_rec |
| 0U, // STB |
| 0U, // STB8 |
| 0U, // STBCIX |
| 0U, // STBCX |
| 0U, // STBEPX |
| 0U, // STBU |
| 0U, // STBU8 |
| 0U, // STBUX |
| 0U, // STBUX8 |
| 0U, // STBX |
| 0U, // STBX8 |
| 0U, // STBXTLS |
| 0U, // STBXTLS_ |
| 0U, // STBXTLS_32 |
| 0U, // STD |
| 0U, // STDAT |
| 0U, // STDBRX |
| 0U, // STDCIX |
| 0U, // STDCX |
| 0U, // STDU |
| 0U, // STDUX |
| 0U, // STDX |
| 0U, // STDXTLS |
| 0U, // STDXTLS_ |
| 0U, // STFD |
| 0U, // STFDEPX |
| 0U, // STFDU |
| 0U, // STFDUX |
| 0U, // STFDX |
| 0U, // STFIWX |
| 0U, // STFS |
| 0U, // STFSU |
| 0U, // STFSUX |
| 0U, // STFSX |
| 0U, // STH |
| 0U, // STH8 |
| 0U, // STHBRX |
| 0U, // STHCIX |
| 0U, // STHCX |
| 0U, // STHEPX |
| 0U, // STHU |
| 0U, // STHU8 |
| 0U, // STHUX |
| 0U, // STHUX8 |
| 0U, // STHX |
| 0U, // STHX8 |
| 0U, // STHXTLS |
| 0U, // STHXTLS_ |
| 0U, // STHXTLS_32 |
| 0U, // STMW |
| 0U, // STOP |
| 0U, // STQ |
| 0U, // STQCX |
| 0U, // STQX_PSEUDO |
| 0U, // STSWI |
| 0U, // STVEBX |
| 0U, // STVEHX |
| 0U, // STVEWX |
| 0U, // STVX |
| 0U, // STVXL |
| 0U, // STW |
| 0U, // STW8 |
| 0U, // STWAT |
| 0U, // STWBRX |
| 0U, // STWCIX |
| 0U, // STWCX |
| 0U, // STWEPX |
| 0U, // STWU |
| 0U, // STWU8 |
| 0U, // STWUX |
| 0U, // STWUX8 |
| 0U, // STWX |
| 0U, // STWX8 |
| 0U, // STWXTLS |
| 0U, // STWXTLS_ |
| 0U, // STWXTLS_32 |
| 0U, // STXSD |
| 0U, // STXSDX |
| 0U, // STXSIBX |
| 0U, // STXSIBXv |
| 0U, // STXSIHX |
| 0U, // STXSIHXv |
| 0U, // STXSIWX |
| 0U, // STXSSP |
| 0U, // STXSSPX |
| 0U, // STXV |
| 0U, // STXVB16X |
| 0U, // STXVD2X |
| 0U, // STXVH8X |
| 0U, // STXVL |
| 0U, // STXVLL |
| 0U, // STXVP |
| 0U, // STXVPRL |
| 0U, // STXVPRLL |
| 0U, // STXVPX |
| 0U, // STXVRBX |
| 0U, // STXVRDX |
| 0U, // STXVRHX |
| 0U, // STXVRL |
| 0U, // STXVRLL |
| 0U, // STXVRWX |
| 0U, // STXVW4X |
| 0U, // STXVX |
| 0U, // SUBF |
| 0U, // SUBF8 |
| 0U, // SUBF8O |
| 0U, // SUBF8O_rec |
| 0U, // SUBF8_rec |
| 0U, // SUBFC |
| 0U, // SUBFC8 |
| 0U, // SUBFC8O |
| 0U, // SUBFC8O_rec |
| 0U, // SUBFC8_rec |
| 0U, // SUBFCO |
| 0U, // SUBFCO_rec |
| 0U, // SUBFC_rec |
| 0U, // SUBFE |
| 0U, // SUBFE8 |
| 0U, // SUBFE8O |
| 0U, // SUBFE8O_rec |
| 0U, // SUBFE8_rec |
| 0U, // SUBFEO |
| 0U, // SUBFEO_rec |
| 0U, // SUBFE_rec |
| 0U, // SUBFIC |
| 0U, // SUBFIC8 |
| 0U, // SUBFME |
| 0U, // SUBFME8 |
| 0U, // SUBFME8O |
| 0U, // SUBFME8O_rec |
| 0U, // SUBFME8_rec |
| 0U, // SUBFMEO |
| 0U, // SUBFMEO_rec |
| 0U, // SUBFME_rec |
| 0U, // SUBFO |
| 0U, // SUBFO_rec |
| 0U, // SUBFUS |
| 0U, // SUBFUS_rec |
| 0U, // SUBFZE |
| 0U, // SUBFZE8 |
| 0U, // SUBFZE8O |
| 0U, // SUBFZE8O_rec |
| 0U, // SUBFZE8_rec |
| 0U, // SUBFZEO |
| 0U, // SUBFZEO_rec |
| 0U, // SUBFZE_rec |
| 0U, // SUBF_rec |
| 0U, // SYNC |
| 0U, // TABORT |
| 0U, // TABORTDC |
| 0U, // TABORTDCI |
| 0U, // TABORTWC |
| 0U, // TABORTWCI |
| 0U, // TAILB |
| 0U, // TAILB8 |
| 0U, // TAILBA |
| 0U, // TAILBA8 |
| 0U, // TAILBCTR |
| 0U, // TAILBCTR8 |
| 0U, // TBEGIN |
| 0U, // TBEGIN_RET |
| 0U, // TCHECK |
| 0U, // TCHECK_RET |
| 0U, // TCRETURNai |
| 0U, // TCRETURNai8 |
| 0U, // TCRETURNdi |
| 0U, // TCRETURNdi8 |
| 0U, // TCRETURNri |
| 0U, // TCRETURNri8 |
| 0U, // TD |
| 0U, // TDI |
| 0U, // TEND |
| 0U, // TLBIA |
| 0U, // TLBIE |
| 0U, // TLBIEL |
| 0U, // TLBIVAX |
| 0U, // TLBLD |
| 0U, // TLBLI |
| 0U, // TLBRE |
| 0U, // TLBRE2 |
| 0U, // TLBSX |
| 0U, // TLBSX2 |
| 0U, // TLBSX2D |
| 0U, // TLBSYNC |
| 0U, // TLBWE |
| 0U, // TLBWE2 |
| 0U, // TLSGDAIX |
| 0U, // TLSGDAIX8 |
| 0U, // TRAP |
| 0U, // TRECHKPT |
| 0U, // TRECLAIM |
| 0U, // TSR |
| 0U, // TW |
| 0U, // TWI |
| 0U, // UNENCODED_NOP |
| 0U, // UpdateGBR |
| 0U, // VABSDUB |
| 0U, // VABSDUH |
| 0U, // VABSDUW |
| 0U, // VADDCUQ |
| 0U, // VADDCUW |
| 0U, // VADDECUQ |
| 0U, // VADDEUQM |
| 0U, // VADDFP |
| 0U, // VADDSBS |
| 0U, // VADDSHS |
| 0U, // VADDSWS |
| 0U, // VADDUBM |
| 0U, // VADDUBS |
| 0U, // VADDUDM |
| 0U, // VADDUHM |
| 0U, // VADDUHS |
| 0U, // VADDUQM |
| 0U, // VADDUWM |
| 0U, // VADDUWS |
| 0U, // VAND |
| 0U, // VANDC |
| 0U, // VAVGSB |
| 0U, // VAVGSH |
| 0U, // VAVGSW |
| 0U, // VAVGUB |
| 0U, // VAVGUH |
| 0U, // VAVGUW |
| 0U, // VBPERMD |
| 0U, // VBPERMQ |
| 0U, // VCFSX |
| 0U, // VCFSX_0 |
| 0U, // VCFUGED |
| 0U, // VCFUX |
| 0U, // VCFUX_0 |
| 0U, // VCIPHER |
| 0U, // VCIPHERLAST |
| 0U, // VCLRLB |
| 0U, // VCLRRB |
| 0U, // VCLZB |
| 0U, // VCLZD |
| 0U, // VCLZDM |
| 0U, // VCLZH |
| 0U, // VCLZLSBB |
| 0U, // VCLZW |
| 0U, // VCMPBFP |
| 0U, // VCMPBFP_rec |
| 0U, // VCMPEQFP |
| 0U, // VCMPEQFP_rec |
| 0U, // VCMPEQUB |
| 0U, // VCMPEQUB_rec |
| 0U, // VCMPEQUD |
| 0U, // VCMPEQUD_rec |
| 0U, // VCMPEQUH |
| 0U, // VCMPEQUH_rec |
| 0U, // VCMPEQUQ |
| 0U, // VCMPEQUQ_rec |
| 0U, // VCMPEQUW |
| 0U, // VCMPEQUW_rec |
| 0U, // VCMPGEFP |
| 0U, // VCMPGEFP_rec |
| 0U, // VCMPGTFP |
| 0U, // VCMPGTFP_rec |
| 0U, // VCMPGTSB |
| 0U, // VCMPGTSB_rec |
| 0U, // VCMPGTSD |
| 0U, // VCMPGTSD_rec |
| 0U, // VCMPGTSH |
| 0U, // VCMPGTSH_rec |
| 0U, // VCMPGTSQ |
| 0U, // VCMPGTSQ_rec |
| 0U, // VCMPGTSW |
| 0U, // VCMPGTSW_rec |
| 0U, // VCMPGTUB |
| 0U, // VCMPGTUB_rec |
| 0U, // VCMPGTUD |
| 0U, // VCMPGTUD_rec |
| 0U, // VCMPGTUH |
| 0U, // VCMPGTUH_rec |
| 0U, // VCMPGTUQ |
| 0U, // VCMPGTUQ_rec |
| 0U, // VCMPGTUW |
| 0U, // VCMPGTUW_rec |
| 0U, // VCMPNEB |
| 0U, // VCMPNEB_rec |
| 0U, // VCMPNEH |
| 0U, // VCMPNEH_rec |
| 0U, // VCMPNEW |
| 0U, // VCMPNEW_rec |
| 0U, // VCMPNEZB |
| 0U, // VCMPNEZB_rec |
| 0U, // VCMPNEZH |
| 0U, // VCMPNEZH_rec |
| 0U, // VCMPNEZW |
| 0U, // VCMPNEZW_rec |
| 0U, // VCMPSQ |
| 0U, // VCMPUQ |
| 0U, // VCNTMBB |
| 0U, // VCNTMBD |
| 0U, // VCNTMBH |
| 0U, // VCNTMBW |
| 0U, // VCTSXS |
| 0U, // VCTSXS_0 |
| 0U, // VCTUXS |
| 0U, // VCTUXS_0 |
| 0U, // VCTZB |
| 0U, // VCTZD |
| 0U, // VCTZDM |
| 0U, // VCTZH |
| 0U, // VCTZLSBB |
| 0U, // VCTZW |
| 0U, // VDIVESD |
| 0U, // VDIVESQ |
| 0U, // VDIVESW |
| 0U, // VDIVEUD |
| 0U, // VDIVEUQ |
| 0U, // VDIVEUW |
| 0U, // VDIVSD |
| 0U, // VDIVSQ |
| 0U, // VDIVSW |
| 0U, // VDIVUD |
| 0U, // VDIVUQ |
| 0U, // VDIVUW |
| 0U, // VEQV |
| 0U, // VEXPANDBM |
| 0U, // VEXPANDDM |
| 0U, // VEXPANDHM |
| 0U, // VEXPANDQM |
| 0U, // VEXPANDWM |
| 0U, // VEXPTEFP |
| 0U, // VEXTDDVLX |
| 0U, // VEXTDDVRX |
| 0U, // VEXTDUBVLX |
| 0U, // VEXTDUBVRX |
| 0U, // VEXTDUHVLX |
| 0U, // VEXTDUHVRX |
| 0U, // VEXTDUWVLX |
| 0U, // VEXTDUWVRX |
| 0U, // VEXTRACTBM |
| 0U, // VEXTRACTD |
| 0U, // VEXTRACTDM |
| 0U, // VEXTRACTHM |
| 0U, // VEXTRACTQM |
| 0U, // VEXTRACTUB |
| 0U, // VEXTRACTUH |
| 0U, // VEXTRACTUW |
| 0U, // VEXTRACTWM |
| 0U, // VEXTSB2D |
| 0U, // VEXTSB2Ds |
| 0U, // VEXTSB2W |
| 0U, // VEXTSB2Ws |
| 0U, // VEXTSD2Q |
| 0U, // VEXTSH2D |
| 0U, // VEXTSH2Ds |
| 0U, // VEXTSH2W |
| 0U, // VEXTSH2Ws |
| 0U, // VEXTSW2D |
| 0U, // VEXTSW2Ds |
| 0U, // VEXTUBLX |
| 0U, // VEXTUBRX |
| 0U, // VEXTUHLX |
| 0U, // VEXTUHRX |
| 0U, // VEXTUWLX |
| 0U, // VEXTUWRX |
| 0U, // VGBBD |
| 0U, // VGNB |
| 0U, // VINSBLX |
| 0U, // VINSBRX |
| 0U, // VINSBVLX |
| 0U, // VINSBVRX |
| 0U, // VINSD |
| 0U, // VINSDLX |
| 0U, // VINSDRX |
| 0U, // VINSERTB |
| 0U, // VINSERTD |
| 0U, // VINSERTH |
| 0U, // VINSERTW |
| 0U, // VINSHLX |
| 0U, // VINSHRX |
| 0U, // VINSHVLX |
| 0U, // VINSHVRX |
| 0U, // VINSW |
| 0U, // VINSWLX |
| 0U, // VINSWRX |
| 0U, // VINSWVLX |
| 0U, // VINSWVRX |
| 0U, // VLOGEFP |
| 0U, // VMADDFP |
| 0U, // VMAXFP |
| 0U, // VMAXSB |
| 0U, // VMAXSD |
| 0U, // VMAXSH |
| 0U, // VMAXSW |
| 0U, // VMAXUB |
| 0U, // VMAXUD |
| 0U, // VMAXUH |
| 0U, // VMAXUW |
| 0U, // VMHADDSHS |
| 0U, // VMHRADDSHS |
| 0U, // VMINFP |
| 0U, // VMINSB |
| 0U, // VMINSD |
| 0U, // VMINSH |
| 0U, // VMINSW |
| 0U, // VMINUB |
| 0U, // VMINUD |
| 0U, // VMINUH |
| 0U, // VMINUW |
| 0U, // VMLADDUHM |
| 0U, // VMODSD |
| 0U, // VMODSQ |
| 0U, // VMODSW |
| 0U, // VMODUD |
| 0U, // VMODUQ |
| 0U, // VMODUW |
| 0U, // VMRGEW |
| 0U, // VMRGHB |
| 0U, // VMRGHH |
| 0U, // VMRGHW |
| 0U, // VMRGLB |
| 0U, // VMRGLH |
| 0U, // VMRGLW |
| 0U, // VMRGOW |
| 0U, // VMSUMCUD |
| 0U, // VMSUMMBM |
| 0U, // VMSUMSHM |
| 0U, // VMSUMSHS |
| 0U, // VMSUMUBM |
| 0U, // VMSUMUDM |
| 0U, // VMSUMUHM |
| 0U, // VMSUMUHS |
| 0U, // VMUL10CUQ |
| 0U, // VMUL10ECUQ |
| 0U, // VMUL10EUQ |
| 0U, // VMUL10UQ |
| 0U, // VMULESB |
| 0U, // VMULESD |
| 0U, // VMULESH |
| 0U, // VMULESW |
| 0U, // VMULEUB |
| 0U, // VMULEUD |
| 0U, // VMULEUH |
| 0U, // VMULEUW |
| 0U, // VMULHSD |
| 0U, // VMULHSW |
| 0U, // VMULHUD |
| 0U, // VMULHUW |
| 0U, // VMULLD |
| 0U, // VMULOSB |
| 0U, // VMULOSD |
| 0U, // VMULOSH |
| 0U, // VMULOSW |
| 0U, // VMULOUB |
| 0U, // VMULOUD |
| 0U, // VMULOUH |
| 0U, // VMULOUW |
| 0U, // VMULUWM |
| 0U, // VNAND |
| 0U, // VNCIPHER |
| 0U, // VNCIPHERLAST |
| 0U, // VNEGD |
| 0U, // VNEGW |
| 0U, // VNMSUBFP |
| 0U, // VNOR |
| 0U, // VOR |
| 0U, // VORC |
| 0U, // VPDEPD |
| 0U, // VPERM |
| 0U, // VPERMR |
| 0U, // VPERMXOR |
| 0U, // VPEXTD |
| 0U, // VPKPX |
| 0U, // VPKSDSS |
| 0U, // VPKSDUS |
| 0U, // VPKSHSS |
| 0U, // VPKSHUS |
| 0U, // VPKSWSS |
| 0U, // VPKSWUS |
| 0U, // VPKUDUM |
| 0U, // VPKUDUS |
| 0U, // VPKUHUM |
| 0U, // VPKUHUS |
| 0U, // VPKUWUM |
| 0U, // VPKUWUS |
| 0U, // VPMSUMB |
| 0U, // VPMSUMD |
| 0U, // VPMSUMH |
| 0U, // VPMSUMW |
| 0U, // VPOPCNTB |
| 0U, // VPOPCNTD |
| 0U, // VPOPCNTH |
| 0U, // VPOPCNTW |
| 0U, // VPRTYBD |
| 0U, // VPRTYBQ |
| 0U, // VPRTYBW |
| 0U, // VREFP |
| 0U, // VRFIM |
| 0U, // VRFIN |
| 0U, // VRFIP |
| 0U, // VRFIZ |
| 0U, // VRLB |
| 0U, // VRLD |
| 0U, // VRLDMI |
| 0U, // VRLDNM |
| 0U, // VRLH |
| 0U, // VRLQ |
| 0U, // VRLQMI |
| 0U, // VRLQNM |
| 0U, // VRLW |
| 0U, // VRLWMI |
| 0U, // VRLWNM |
| 0U, // VRSQRTEFP |
| 0U, // VSBOX |
| 0U, // VSEL |
| 0U, // VSHASIGMAD |
| 0U, // VSHASIGMAW |
| 0U, // VSL |
| 0U, // VSLB |
| 0U, // VSLD |
| 0U, // VSLDBI |
| 0U, // VSLDOI |
| 0U, // VSLH |
| 0U, // VSLO |
| 0U, // VSLQ |
| 0U, // VSLV |
| 0U, // VSLW |
| 0U, // VSPLTB |
| 0U, // VSPLTBs |
| 0U, // VSPLTH |
| 0U, // VSPLTHs |
| 0U, // VSPLTISB |
| 0U, // VSPLTISH |
| 0U, // VSPLTISW |
| 0U, // VSPLTW |
| 0U, // VSR |
| 0U, // VSRAB |
| 0U, // VSRAD |
| 0U, // VSRAH |
| 0U, // VSRAQ |
| 0U, // VSRAW |
| 0U, // VSRB |
| 0U, // VSRD |
| 0U, // VSRDBI |
| 0U, // VSRH |
| 0U, // VSRO |
| 0U, // VSRQ |
| 0U, // VSRV |
| 0U, // VSRW |
| 0U, // VSTRIBL |
| 0U, // VSTRIBL_rec |
| 0U, // VSTRIBR |
| 0U, // VSTRIBR_rec |
| 0U, // VSTRIHL |
| 0U, // VSTRIHL_rec |
| 0U, // VSTRIHR |
| 0U, // VSTRIHR_rec |
| 0U, // VSUBCUQ |
| 0U, // VSUBCUW |
| 0U, // VSUBECUQ |
| 0U, // VSUBEUQM |
| 0U, // VSUBFP |
| 0U, // VSUBSBS |
| 0U, // VSUBSHS |
| 0U, // VSUBSWS |
| 0U, // VSUBUBM |
| 0U, // VSUBUBS |
| 0U, // VSUBUDM |
| 0U, // VSUBUHM |
| 0U, // VSUBUHS |
| 0U, // VSUBUQM |
| 0U, // VSUBUWM |
| 0U, // VSUBUWS |
| 0U, // VSUM2SWS |
| 0U, // VSUM4SBS |
| 0U, // VSUM4SHS |
| 0U, // VSUM4UBS |
| 0U, // VSUMSWS |
| 0U, // VUPKHPX |
| 0U, // VUPKHSB |
| 0U, // VUPKHSH |
| 0U, // VUPKHSW |
| 0U, // VUPKLPX |
| 0U, // VUPKLSB |
| 0U, // VUPKLSH |
| 0U, // VUPKLSW |
| 0U, // VXOR |
| 0U, // V_SET0 |
| 0U, // V_SET0B |
| 0U, // V_SET0H |
| 0U, // V_SETALLONES |
| 0U, // V_SETALLONESB |
| 0U, // V_SETALLONESH |
| 0U, // WAIT |
| 0U, // WRTEE |
| 0U, // WRTEEI |
| 0U, // XOR |
| 0U, // XOR8 |
| 0U, // XOR8_rec |
| 0U, // XORI |
| 0U, // XORI8 |
| 0U, // XORIS |
| 0U, // XORIS8 |
| 0U, // XOR_rec |
| 0U, // XSABSDP |
| 0U, // XSABSQP |
| 0U, // XSADDDP |
| 0U, // XSADDQP |
| 0U, // XSADDQPO |
| 0U, // XSADDSP |
| 0U, // XSCMPEQDP |
| 0U, // XSCMPEQQP |
| 0U, // XSCMPEXPDP |
| 0U, // XSCMPEXPQP |
| 0U, // XSCMPGEDP |
| 0U, // XSCMPGEQP |
| 0U, // XSCMPGTDP |
| 0U, // XSCMPGTQP |
| 0U, // XSCMPODP |
| 0U, // XSCMPOQP |
| 0U, // XSCMPUDP |
| 0U, // XSCMPUQP |
| 0U, // XSCPSGNDP |
| 0U, // XSCPSGNQP |
| 0U, // XSCVDPHP |
| 0U, // XSCVDPQP |
| 0U, // XSCVDPSP |
| 0U, // XSCVDPSPN |
| 0U, // XSCVDPSXDS |
| 0U, // XSCVDPSXDSs |
| 0U, // XSCVDPSXWS |
| 0U, // XSCVDPSXWSs |
| 0U, // XSCVDPUXDS |
| 0U, // XSCVDPUXDSs |
| 0U, // XSCVDPUXWS |
| 0U, // XSCVDPUXWSs |
| 0U, // XSCVHPDP |
| 0U, // XSCVQPDP |
| 0U, // XSCVQPDPO |
| 0U, // XSCVQPSDZ |
| 0U, // XSCVQPSQZ |
| 0U, // XSCVQPSWZ |
| 0U, // XSCVQPUDZ |
| 0U, // XSCVQPUQZ |
| 0U, // XSCVQPUWZ |
| 0U, // XSCVSDQP |
| 0U, // XSCVSPDP |
| 0U, // XSCVSPDPN |
| 0U, // XSCVSQQP |
| 0U, // XSCVSXDDP |
| 0U, // XSCVSXDSP |
| 0U, // XSCVUDQP |
| 0U, // XSCVUQQP |
| 0U, // XSCVUXDDP |
| 0U, // XSCVUXDSP |
| 0U, // XSDIVDP |
| 0U, // XSDIVQP |
| 0U, // XSDIVQPO |
| 0U, // XSDIVSP |
| 0U, // XSIEXPDP |
| 0U, // XSIEXPQP |
| 0U, // XSMADDADP |
| 0U, // XSMADDASP |
| 0U, // XSMADDMDP |
| 0U, // XSMADDMSP |
| 0U, // XSMADDQP |
| 0U, // XSMADDQPO |
| 0U, // XSMAXCDP |
| 0U, // XSMAXCQP |
| 0U, // XSMAXDP |
| 0U, // XSMAXJDP |
| 0U, // XSMINCDP |
| 0U, // XSMINCQP |
| 0U, // XSMINDP |
| 0U, // XSMINJDP |
| 0U, // XSMSUBADP |
| 0U, // XSMSUBASP |
| 0U, // XSMSUBMDP |
| 0U, // XSMSUBMSP |
| 0U, // XSMSUBQP |
| 0U, // XSMSUBQPO |
| 0U, // XSMULDP |
| 0U, // XSMULQP |
| 0U, // XSMULQPO |
| 0U, // XSMULSP |
| 0U, // XSNABSDP |
| 0U, // XSNABSDPs |
| 0U, // XSNABSQP |
| 0U, // XSNEGDP |
| 0U, // XSNEGQP |
| 0U, // XSNMADDADP |
| 0U, // XSNMADDASP |
| 0U, // XSNMADDMDP |
| 0U, // XSNMADDMSP |
| 0U, // XSNMADDQP |
| 0U, // XSNMADDQPO |
| 0U, // XSNMSUBADP |
| 0U, // XSNMSUBASP |
| 0U, // XSNMSUBMDP |
| 0U, // XSNMSUBMSP |
| 0U, // XSNMSUBQP |
| 0U, // XSNMSUBQPO |
| 0U, // XSRDPI |
| 0U, // XSRDPIC |
| 0U, // XSRDPIM |
| 0U, // XSRDPIP |
| 0U, // XSRDPIZ |
| 0U, // XSREDP |
| 0U, // XSRESP |
| 0U, // XSRQPI |
| 0U, // XSRQPIX |
| 0U, // XSRQPXP |
| 0U, // XSRSP |
| 0U, // XSRSQRTEDP |
| 0U, // XSRSQRTESP |
| 0U, // XSSQRTDP |
| 0U, // XSSQRTQP |
| 0U, // XSSQRTQPO |
| 0U, // XSSQRTSP |
| 0U, // XSSUBDP |
| 0U, // XSSUBQP |
| 0U, // XSSUBQPO |
| 0U, // XSSUBSP |
| 0U, // XSTDIVDP |
| 0U, // XSTSQRTDP |
| 0U, // XSTSTDCDP |
| 0U, // XSTSTDCQP |
| 0U, // XSTSTDCSP |
| 0U, // XSXEXPDP |
| 0U, // XSXEXPQP |
| 0U, // XSXSIGDP |
| 0U, // XSXSIGQP |
| 0U, // XVABSDP |
| 0U, // XVABSSP |
| 0U, // XVADDDP |
| 0U, // XVADDSP |
| 0U, // XVBF16GER2 |
| 0U, // XVBF16GER2NN |
| 0U, // XVBF16GER2NP |
| 0U, // XVBF16GER2PN |
| 0U, // XVBF16GER2PP |
| 0U, // XVBF16GER2W |
| 0U, // XVBF16GER2WNN |
| 0U, // XVBF16GER2WNP |
| 0U, // XVBF16GER2WPN |
| 0U, // XVBF16GER2WPP |
| 0U, // XVCMPEQDP |
| 0U, // XVCMPEQDP_rec |
| 0U, // XVCMPEQSP |
| 0U, // XVCMPEQSP_rec |
| 0U, // XVCMPGEDP |
| 0U, // XVCMPGEDP_rec |
| 0U, // XVCMPGESP |
| 0U, // XVCMPGESP_rec |
| 0U, // XVCMPGTDP |
| 0U, // XVCMPGTDP_rec |
| 0U, // XVCMPGTSP |
| 0U, // XVCMPGTSP_rec |
| 0U, // XVCPSGNDP |
| 0U, // XVCPSGNSP |
| 0U, // XVCVBF16SPN |
| 0U, // XVCVDPSP |
| 0U, // XVCVDPSXDS |
| 0U, // XVCVDPSXWS |
| 0U, // XVCVDPUXDS |
| 0U, // XVCVDPUXWS |
| 0U, // XVCVHPSP |
| 0U, // XVCVSPBF16 |
| 0U, // XVCVSPDP |
| 0U, // XVCVSPHP |
| 0U, // XVCVSPSXDS |
| 0U, // XVCVSPSXWS |
| 0U, // XVCVSPUXDS |
| 0U, // XVCVSPUXWS |
| 0U, // XVCVSXDDP |
| 0U, // XVCVSXDSP |
| 0U, // XVCVSXWDP |
| 0U, // XVCVSXWSP |
| 0U, // XVCVUXDDP |
| 0U, // XVCVUXDSP |
| 0U, // XVCVUXWDP |
| 0U, // XVCVUXWSP |
| 0U, // XVDIVDP |
| 0U, // XVDIVSP |
| 0U, // XVF16GER2 |
| 0U, // XVF16GER2NN |
| 0U, // XVF16GER2NP |
| 0U, // XVF16GER2PN |
| 0U, // XVF16GER2PP |
| 0U, // XVF16GER2W |
| 0U, // XVF16GER2WNN |
| 0U, // XVF16GER2WNP |
| 0U, // XVF16GER2WPN |
| 0U, // XVF16GER2WPP |
| 0U, // XVF32GER |
| 0U, // XVF32GERNN |
| 0U, // XVF32GERNP |
| 0U, // XVF32GERPN |
| 0U, // XVF32GERPP |
| 0U, // XVF32GERW |
| 0U, // XVF32GERWNN |
| 0U, // XVF32GERWNP |
| 0U, // XVF32GERWPN |
| 0U, // XVF32GERWPP |
| 0U, // XVF64GER |
| 0U, // XVF64GERNN |
| 0U, // XVF64GERNP |
| 0U, // XVF64GERPN |
| 0U, // XVF64GERPP |
| 0U, // XVF64GERW |
| 0U, // XVF64GERWNN |
| 0U, // XVF64GERWNP |
| 0U, // XVF64GERWPN |
| 0U, // XVF64GERWPP |
| 0U, // XVI16GER2 |
| 0U, // XVI16GER2PP |
| 0U, // XVI16GER2S |
| 0U, // XVI16GER2SPP |
| 0U, // XVI16GER2SW |
| 0U, // XVI16GER2SWPP |
| 0U, // XVI16GER2W |
| 0U, // XVI16GER2WPP |
| 0U, // XVI4GER8 |
| 0U, // XVI4GER8PP |
| 0U, // XVI4GER8W |
| 0U, // XVI4GER8WPP |
| 0U, // XVI8GER4 |
| 0U, // XVI8GER4PP |
| 0U, // XVI8GER4SPP |
| 0U, // XVI8GER4W |
| 0U, // XVI8GER4WPP |
| 0U, // XVI8GER4WSPP |
| 0U, // XVIEXPDP |
| 0U, // XVIEXPSP |
| 0U, // XVMADDADP |
| 0U, // XVMADDASP |
| 0U, // XVMADDMDP |
| 0U, // XVMADDMSP |
| 0U, // XVMAXDP |
| 0U, // XVMAXSP |
| 0U, // XVMINDP |
| 0U, // XVMINSP |
| 0U, // XVMSUBADP |
| 0U, // XVMSUBASP |
| 0U, // XVMSUBMDP |
| 0U, // XVMSUBMSP |
| 0U, // XVMULDP |
| 0U, // XVMULSP |
| 0U, // XVNABSDP |
| 0U, // XVNABSSP |
| 0U, // XVNEGDP |
| 0U, // XVNEGSP |
| 0U, // XVNMADDADP |
| 0U, // XVNMADDASP |
| 0U, // XVNMADDMDP |
| 0U, // XVNMADDMSP |
| 0U, // XVNMSUBADP |
| 0U, // XVNMSUBASP |
| 0U, // XVNMSUBMDP |
| 0U, // XVNMSUBMSP |
| 0U, // XVRDPI |
| 0U, // XVRDPIC |
| 0U, // XVRDPIM |
| 0U, // XVRDPIP |
| 0U, // XVRDPIZ |
| 0U, // XVREDP |
| 0U, // XVRESP |
| 0U, // XVRSPI |
| 0U, // XVRSPIC |
| 0U, // XVRSPIM |
| 0U, // XVRSPIP |
| 0U, // XVRSPIZ |
| 0U, // XVRSQRTEDP |
| 0U, // XVRSQRTESP |
| 0U, // XVSQRTDP |
| 0U, // XVSQRTSP |
| 0U, // XVSUBDP |
| 0U, // XVSUBSP |
| 0U, // XVTDIVDP |
| 0U, // XVTDIVSP |
| 0U, // XVTLSBB |
| 0U, // XVTSQRTDP |
| 0U, // XVTSQRTSP |
| 0U, // XVTSTDCDP |
| 0U, // XVTSTDCSP |
| 0U, // XVXEXPDP |
| 0U, // XVXEXPSP |
| 0U, // XVXSIGDP |
| 0U, // XVXSIGSP |
| 0U, // XXBLENDVB |
| 0U, // XXBLENDVD |
| 0U, // XXBLENDVH |
| 0U, // XXBLENDVW |
| 0U, // XXBRD |
| 0U, // XXBRH |
| 0U, // XXBRQ |
| 0U, // XXBRW |
| 1U, // XXEVAL |
| 0U, // XXEXTRACTUW |
| 0U, // XXGENPCVBM |
| 0U, // XXGENPCVDM |
| 0U, // XXGENPCVHM |
| 0U, // XXGENPCVWM |
| 0U, // XXINSERTW |
| 0U, // XXLAND |
| 0U, // XXLANDC |
| 0U, // XXLEQV |
| 0U, // XXLEQVOnes |
| 0U, // XXLNAND |
| 0U, // XXLNOR |
| 0U, // XXLOR |
| 0U, // XXLORC |
| 0U, // XXLORf |
| 0U, // XXLXOR |
| 0U, // XXLXORdpz |
| 0U, // XXLXORspz |
| 0U, // XXLXORz |
| 0U, // XXMFACC |
| 0U, // XXMFACCW |
| 0U, // XXMRGHW |
| 0U, // XXMRGLW |
| 0U, // XXMTACC |
| 0U, // XXMTACCW |
| 0U, // XXPERM |
| 0U, // XXPERMDI |
| 0U, // XXPERMDIs |
| 0U, // XXPERMR |
| 1U, // XXPERMX |
| 0U, // XXSEL |
| 0U, // XXSETACCZ |
| 0U, // XXSETACCZW |
| 0U, // XXSLDWI |
| 0U, // XXSLDWIs |
| 0U, // XXSPLTI32DX |
| 0U, // XXSPLTIB |
| 0U, // XXSPLTIDP |
| 0U, // XXSPLTIW |
| 0U, // XXSPLTW |
| 0U, // XXSPLTWs |
| 0U, // gBC |
| 0U, // gBCA |
| 0U, // gBCAat |
| 0U, // gBCCTR |
| 0U, // gBCCTRL |
| 0U, // gBCL |
| 0U, // gBCLA |
| 0U, // gBCLAat |
| 0U, // gBCLR |
| 0U, // gBCLRL |
| 0U, // gBCLat |
| 0U, // gBCat |
| }; |
| |
| // Emit the opcode for the instruction. |
| uint64_t Bits = 0; |
| Bits |= (uint64_t)OpInfo0[MI->getOpcode()] << 0; |
| Bits |= (uint64_t)OpInfo1[MI->getOpcode()] << 32; |
| Bits |= (uint64_t)OpInfo2[MI->getOpcode()] << 48; |
| return {AsmStrs+(Bits & 32767)-1, Bits}; |
| |
| } |
| /// printInstruction - This method is automatically generated by tablegen |
| /// from the instruction set description. |
| LLVM_NO_PROFILE_INSTRUMENT_FUNCTION |
| void PPCInstPrinter::printInstruction(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &O) { |
| O << "\t"; |
| |
| auto MnemonicInfo = getMnemonic(MI); |
| |
| O << MnemonicInfo.first; |
| |
| uint64_t Bits = MnemonicInfo.second; |
| assert(Bits != 0 && "Cannot print this instruction."); |
| |
| // Fragment 0 encoded into 5 bits for 22 unique commands. |
| switch ((Bits >> 15) & 31) { |
| default: llvm_unreachable("Invalid command number."); |
| case 0: |
| // DBG_VALUE, DBG_VALUE_LIST, DBG_INSTR_REF, DBG_PHI, DBG_LABEL, BUNDLE, ... |
| return; |
| break; |
| case 1: |
| // BUILD_UACC, CLRLSLDI, CLRLSLDI_rec, CLRLSLWI, CLRLSLWI_rec, CLRRDI, CL... |
| printOperand(MI, 0, STI, O); |
| break; |
| case 2: |
| // DCBFL, DCBFLP, DCBFPS, DCBFx, DCBSTPS, DCBTCT, DCBTDS, DCBTSTCT, DCBTS... |
| printMemRegReg(MI, 0, STI, O); |
| break; |
| case 3: |
| // ADJCALLSTACKDOWN, ADJCALLSTACKUP |
| printU16ImmOperand(MI, 0, STI, O); |
| O << ' '; |
| printU16ImmOperand(MI, 1, STI, O); |
| return; |
| break; |
| case 4: |
| // B, BCLalways, BDNZ, BDNZ8, BDNZL, BDNZLm, BDNZLp, BDNZm, BDNZp, BDZ, B... |
| printBranchOperand(MI, Address, 0, STI, O); |
| break; |
| case 5: |
| // BA, BDNZA, BDNZAm, BDNZAp, BDNZLA, BDNZLAm, BDNZLAp, BDZA, BDZAm, BDZA... |
| printAbsBranchOperand(MI, 0, STI, O); |
| break; |
| case 6: |
| // BCC, BCCA, BCCCTR, BCCCTR8, BCCCTRL, BCCCTRL8, BCCL, BCCLA, BCCLR, BCC... |
| printPredicateOperand(MI, 0, STI, O, "cc"); |
| break; |
| case 7: |
| // BCTRL8_LDinto_toc, BCTRL8_LDinto_toc_RM, BCTRL_LWZinto_toc, BCTRL_LWZi... |
| printMemRegImm(MI, 0, STI, O); |
| return; |
| break; |
| case 8: |
| // BL8_NOP_TLS, BL8_NOTOC_TLS, BL8_TLS, BL8_TLS_, BL_TLS |
| printTLSCall(MI, 0, STI, O); |
| break; |
| case 9: |
| // DCBF, DCBT, DCBTST |
| printMemRegReg(MI, 1, STI, O); |
| O << ", "; |
| break; |
| case 10: |
| // DCBTEP, DCBTSTEP |
| printU5ImmOperand(MI, 2, STI, O); |
| O << ", "; |
| printMemRegReg(MI, 0, STI, O); |
| return; |
| break; |
| case 11: |
| // DMXXEXTFDMR256, DST, DST64, DSTST, DSTST64, DSTSTT, DSTSTT64, DSTT, DS... |
| printOperand(MI, 1, STI, O); |
| break; |
| case 12: |
| // DMXXEXTFDMR512, DMXXEXTFDMR512_HI |
| printOperand(MI, 2, STI, O); |
| O << ", "; |
| printOperand(MI, 0, STI, O); |
| O << ", "; |
| printOperand(MI, 1, STI, O); |
| break; |
| case 13: |
| // DSS, MBAR, MTFSB0, MTFSB1, TABORTDC, TABORTDCI, TABORTWC, TABORTWCI, T... |
| printU5ImmOperand(MI, 0, STI, O); |
| break; |
| case 14: |
| // ICBLC, ICBLQ, ICBT, ICBTLS |
| printU4ImmOperand(MI, 0, STI, O); |
| O << ", "; |
| printMemRegReg(MI, 1, STI, O); |
| return; |
| break; |
| case 15: |
| // MTFSFI, MTFSFI_rec, MTFSFIb |
| printU3ImmOperand(MI, 0, STI, O); |
| O << ", "; |
| printU4ImmOperand(MI, 1, STI, O); |
| break; |
| case 16: |
| // MTOCRF, MTOCRF8 |
| printcrbitm(MI, 0, STI, O); |
| O << ", "; |
| printOperand(MI, 1, STI, O); |
| return; |
| break; |
| case 17: |
| // MTSR |
| printU4ImmOperand(MI, 1, STI, O); |
| O << ", "; |
| printOperand(MI, 0, STI, O); |
| return; |
| break; |
| case 18: |
| // RFEBB, TBEGIN, TEND, TSR |
| printU1ImmOperand(MI, 0, STI, O); |
| return; |
| break; |
| case 19: |
| // SYNC, WAIT |
| printU2ImmOperand(MI, 0, STI, O); |
| return; |
| break; |
| case 20: |
| // XSRQPI, XSRQPIX, XSRQPXP |
| printU1ImmOperand(MI, 1, STI, O); |
| O << ", "; |
| printOperand(MI, 0, STI, O); |
| O << ", "; |
| printOperand(MI, 2, STI, O); |
| O << ", "; |
| printU2ImmOperand(MI, 3, STI, O); |
| return; |
| break; |
| case 21: |
| // gBCAat, gBCLAat, gBCLat, gBCat |
| printATBitsAsHint(MI, 1, STI, O); |
| O << ' '; |
| printU5ImmOperand(MI, 0, STI, O); |
| O << ", "; |
| printOperand(MI, 2, STI, O); |
| O << ", "; |
| break; |
| } |
| |
| |
| // Fragment 1 encoded into 5 bits for 23 unique commands. |
| switch ((Bits >> 20) & 31) { |
| default: llvm_unreachable("Invalid command number."); |
| case 0: |
| // BUILD_UACC, CLRLSLDI, CLRLSLDI_rec, CLRLSLWI, CLRLSLWI_rec, CLRRDI, CL... |
| O << ", "; |
| break; |
| case 1: |
| // DCBFL, DCBFLP, DCBFPS, DCBFx, DCBSTPS, DCBTSTT, DCBTSTx, DCBTT, DCBTx,... |
| return; |
| break; |
| case 2: |
| // ATOMIC_CMP_SWAP_I16, ATOMIC_CMP_SWAP_I32, TCRETURNai, TCRETURNai8, TCR... |
| O << ' '; |
| break; |
| case 3: |
| // BCC, CTRL_DEP |
| printPredicateOperand(MI, 0, STI, O, "pm"); |
| O << ' '; |
| printPredicateOperand(MI, 0, STI, O, "reg"); |
| O << ", "; |
| printBranchOperand(MI, Address, 2, STI, O); |
| return; |
| break; |
| case 4: |
| // BCCA |
| O << 'a'; |
| printPredicateOperand(MI, 0, STI, O, "pm"); |
| O << ' '; |
| printPredicateOperand(MI, 0, STI, O, "reg"); |
| O << ", "; |
| printAbsBranchOperand(MI, 2, STI, O); |
| return; |
| break; |
| case 5: |
| // BCCCTR, BCCCTR8 |
| O << "ctr"; |
| printPredicateOperand(MI, 0, STI, O, "pm"); |
| O << ' '; |
| printPredicateOperand(MI, 0, STI, O, "reg"); |
| return; |
| break; |
| case 6: |
| // BCCCTRL, BCCCTRL8 |
| O << "ctrl"; |
| printPredicateOperand(MI, 0, STI, O, "pm"); |
| O << ' '; |
| printPredicateOperand(MI, 0, STI, O, "reg"); |
| return; |
| break; |
| case 7: |
| // BCCL |
| O << 'l'; |
| printPredicateOperand(MI, 0, STI, O, "pm"); |
| O << ' '; |
| printPredicateOperand(MI, 0, STI, O, "reg"); |
| O << ", "; |
| printBranchOperand(MI, Address, 2, STI, O); |
| return; |
| break; |
| case 8: |
| // BCCLA |
| O << "la"; |
| printPredicateOperand(MI, 0, STI, O, "pm"); |
| O << ' '; |
| printPredicateOperand(MI, 0, STI, O, "reg"); |
| O << ", "; |
| printAbsBranchOperand(MI, 2, STI, O); |
| return; |
| break; |
| case 9: |
| // BCCLR |
| O << "lr"; |
| printPredicateOperand(MI, 0, STI, O, "pm"); |
| O << ' '; |
| printPredicateOperand(MI, 0, STI, O, "reg"); |
| return; |
| break; |
| case 10: |
| // BCCLRL |
| O << "lrl"; |
| printPredicateOperand(MI, 0, STI, O, "pm"); |
| O << ' '; |
| printPredicateOperand(MI, 0, STI, O, "reg"); |
| return; |
| break; |
| case 11: |
| // BCCTR, BCCTR8, BCCTR8n, BCCTRL, BCCTRL8, BCCTRL8n, BCCTRLn, BCCTRn, BC... |
| O << ", 0"; |
| return; |
| break; |
| case 12: |
| // BL8_NOP, BL8_NOP_RM, BL8_NOP_TLS, BLA8_NOP, BLA8_NOP_RM, BL_NOP, BL_NO... |
| O << "\n\tnop"; |
| return; |
| break; |
| case 13: |
| // DCBF |
| printU3ImmOperand(MI, 0, STI, O); |
| return; |
| break; |
| case 14: |
| // DCBT, DCBTST |
| printU5ImmOperand(MI, 0, STI, O); |
| return; |
| break; |
| case 15: |
| // DMXXEXTFDMR512_HI |
| O << ", 1"; |
| return; |
| break; |
| case 16: |
| // EVSEL, TLBIE |
| O << ','; |
| break; |
| case 17: |
| // MFTB8 |
| O << ", 268"; |
| return; |
| break; |
| case 18: |
| // MFUDSCR |
| O << ", 3"; |
| return; |
| break; |
| case 19: |
| // MFVRSAVE, MFVRSAVEv |
| O << ", 256"; |
| return; |
| break; |
| case 20: |
| // V_SETALLONES, V_SETALLONESB, V_SETALLONESH |
| O << ", -1"; |
| return; |
| break; |
| case 21: |
| // gBCAat, gBCLAat |
| printAbsBranchOperand(MI, 3, STI, O); |
| return; |
| break; |
| case 22: |
| // gBCLat, gBCat |
| printBranchOperand(MI, Address, 3, STI, O); |
| return; |
| break; |
| } |
| |
| |
| // Fragment 2 encoded into 5 bits for 29 unique commands. |
| switch ((Bits >> 25) & 31) { |
| default: llvm_unreachable("Invalid command number."); |
| case 0: |
| // BUILD_UACC, CLRLSLDI, CLRLSLDI_rec, CLRLSLWI, CLRLSLWI_rec, CLRRDI, CL... |
| printOperand(MI, 1, STI, O); |
| break; |
| case 1: |
| // DCBTCT, DCBTDS, DCBTSTCT, DCBTSTDS, EVADDIW |
| printU5ImmOperand(MI, 2, STI, O); |
| break; |
| case 2: |
| // LAx, EVLDD, EVLDH, EVLDW, EVLHHESPLAT, EVLHHOSSPLAT, EVLHHOUSPLAT, EVL... |
| printMemRegImm(MI, 1, STI, O); |
| return; |
| break; |
| case 3: |
| // SUBPCIS, LI, LI8, LIS, LIS8 |
| printS16ImmOperand(MI, 1, STI, O); |
| return; |
| break; |
| case 4: |
| // ATOMIC_CMP_SWAP_I16, ATOMIC_CMP_SWAP_I32, EVLDDX, EVLDHX, EVLDWX, EVLH... |
| printMemRegReg(MI, 1, STI, O); |
| break; |
| case 5: |
| // BC, BCL, BCLn, BCn |
| printBranchOperand(MI, Address, 1, STI, O); |
| return; |
| break; |
| case 6: |
| // CMPRB, CMPRB8, MTMSR, MTMSRD |
| printU1ImmOperand(MI, 1, STI, O); |
| break; |
| case 7: |
| // CRSET, CRUNSET, DMXXEXTFDMR256, MTDCR, TLBIE, V_SET0, V_SET0B, V_SET0H... |
| printOperand(MI, 0, STI, O); |
| break; |
| case 8: |
| // DARN, MFFSCRNI |
| printU2ImmOperand(MI, 1, STI, O); |
| return; |
| break; |
| case 9: |
| // DMXOR, DST, DST64, DSTST, DSTST64, DSTSTT, DSTSTT64, DSTT, DSTT64, MTF... |
| printOperand(MI, 2, STI, O); |
| break; |
| case 10: |
| // EVSPLATFI, EVSPLATI, VSPLTISB, VSPLTISH, VSPLTISW |
| printS5ImmOperand(MI, 1, STI, O); |
| return; |
| break; |
| case 11: |
| // EVSUBIFW, LXVKQ |
| printU5ImmOperand(MI, 1, STI, O); |
| break; |
| case 12: |
| // HASHCHK, HASHCHK8, HASHCHKP, HASHCHKP8, HASHST, HASHST8, HASHSTP, HASH... |
| printMemRegImmHash(MI, 1, STI, O); |
| return; |
| break; |
| case 13: |
| // LA, LA8 |
| printS16ImmOperand(MI, 2, STI, O); |
| O << '('; |
| printOperand(MI, 1, STI, O); |
| O << ')'; |
| return; |
| break; |
| case 14: |
| // LBZU, LBZU8, LDU, LFDU, LFSU, LHAU, LHAU8, LHZU, LHZU8, LWZU, LWZU8, S... |
| printMemRegImm(MI, 2, STI, O); |
| return; |
| break; |
| case 15: |
| // LBZUX, LBZUX8, LDUX, LFDUX, LFSUX, LHAUX, LHAUX8, LHZUX, LHZUX8, LWAUX... |
| printMemRegReg(MI, 2, STI, O); |
| return; |
| break; |
| case 16: |
| // MFBHRBE |
| printU10ImmOperand(MI, 1, STI, O); |
| return; |
| break; |
| case 17: |
| // MFFSCDRNI |
| printU3ImmOperand(MI, 1, STI, O); |
| return; |
| break; |
| case 18: |
| // MFOCRF, MFOCRF8 |
| printcrbitm(MI, 1, STI, O); |
| return; |
| break; |
| case 19: |
| // MFSR |
| printU4ImmOperand(MI, 1, STI, O); |
| return; |
| break; |
| case 20: |
| // MTFSFI_rec, XXSPLTI32DX |
| printU1ImmOperand(MI, 2, STI, O); |
| break; |
| case 21: |
| // MTVSRBMI |
| printU16ImmOperand(MI, 1, STI, O); |
| return; |
| break; |
| case 22: |
| // PADDI8pc, PADDIpc |
| printImmZeroOperand(MI, 1, STI, O); |
| O << ", "; |
| printS34ImmOperand(MI, 2, STI, O); |
| O << ", 1"; |
| return; |
| break; |
| case 23: |
| // PLBZ, PLBZ8, PLD, PLFD, PLFS, PLHA, PLHA8, PLHZ, PLHZ8, PLWA, PLWA8, P... |
| printMemRegImm34(MI, 1, STI, O); |
| O << ", 0"; |
| return; |
| break; |
| case 24: |
| // PLBZ8pc, PLBZpc, PLDpc, PLFDpc, PLFSpc, PLHA8pc, PLHApc, PLHZ8pc, PLHZ... |
| printMemRegImm34PCRel(MI, 1, STI, O); |
| O << ", 1"; |
| return; |
| break; |
| case 25: |
| // PLI, PLI8 |
| printS34ImmOperand(MI, 1, STI, O); |
| return; |
| break; |
| case 26: |
| // SUBFUS, SUBFUS_rec |
| printU1ImmOperand(MI, 3, STI, O); |
| O << ", "; |
| printOperand(MI, 1, STI, O); |
| O << ", "; |
| printOperand(MI, 2, STI, O); |
| return; |
| break; |
| case 27: |
| // VINSD, VINSERTB, VINSERTH, VINSW |
| printOperand(MI, 3, STI, O); |
| O << ", "; |
| printU4ImmOperand(MI, 2, STI, O); |
| return; |
| break; |
| case 28: |
| // XXSPLTIB |
| printU8ImmOperand(MI, 1, STI, O); |
| return; |
| break; |
| } |
| |
| |
| // Fragment 3 encoded into 3 bits for 6 unique commands. |
| switch ((Bits >> 30) & 7) { |
| default: llvm_unreachable("Invalid command number."); |
| case 0: |
| // BUILD_UACC, DCBTCT, DCBTDS, DCBTSTCT, DCBTSTDS, ADDME, ADDME8, ADDME8O... |
| return; |
| break; |
| case 1: |
| // CLRLSLDI, CLRLSLDI_rec, CLRLSLWI, CLRLSLWI_rec, CLRRDI, CLRRDI_rec, CL... |
| O << ", "; |
| break; |
| case 2: |
| // ATOMIC_CMP_SWAP_I16, ATOMIC_CMP_SWAP_I32 |
| O << ' '; |
| printOperand(MI, 3, STI, O); |
| O << ' '; |
| printOperand(MI, 4, STI, O); |
| return; |
| break; |
| case 3: |
| // EVSEL |
| O << ','; |
| printOperand(MI, 2, STI, O); |
| return; |
| break; |
| case 4: |
| // LBARXL, LDARXL, LHARXL, LQARXL, LWARXL |
| O << ", 1"; |
| return; |
| break; |
| case 5: |
| // VCFSX_0, VCFUX_0, VCTSXS_0, VCTUXS_0 |
| O << ", 0"; |
| return; |
| break; |
| } |
| |
| |
| // Fragment 4 encoded into 5 bits for 23 unique commands. |
| switch ((Bits >> 33) & 31) { |
| default: llvm_unreachable("Invalid command number."); |
| case 0: |
| // CLRLSLDI, CLRLSLDI_rec, CLRRDI, CLRRDI_rec, EXTLDI, EXTLDI_rec, EXTRDI... |
| printU6ImmOperand(MI, 2, STI, O); |
| break; |
| case 1: |
| // CLRLSLWI, CLRLSLWI_rec, CLRRWI, CLRRWI_rec, EXTLWI, EXTLWI_rec, EXTRWI... |
| printU5ImmOperand(MI, 2, STI, O); |
| break; |
| case 2: |
| // SUBI, SUBIC, SUBIC_rec, SUBIS, ADDI, ADDI8, ADDIC, ADDIC8, ADDIC_rec, ... |
| printS16ImmOperand(MI, 2, STI, O); |
| return; |
| break; |
| case 3: |
| // ADD4, ADD4O, ADD4O_rec, ADD4TLS, ADD4_rec, ADD8, ADD8O, ADD8O_rec, ADD... |
| printOperand(MI, 2, STI, O); |
| break; |
| case 4: |
| // ANDI8_rec, ANDIS8_rec, ANDIS_rec, ANDI_rec, CMPLDI, CMPLWI, ORI, ORI8,... |
| printU16ImmOperand(MI, 2, STI, O); |
| return; |
| break; |
| case 5: |
| // BCDCFN_rec, BCDCFSQ_rec, BCDCFZ_rec, BCDCTZ_rec, BCDSETSGN_rec, CP_PAS... |
| printU1ImmOperand(MI, 2, STI, O); |
| break; |
| case 6: |
| // CRSET, CRUNSET, V_SET0, V_SET0B, V_SET0H, XXLEQVOnes, XXLXORdpz, XXLXO... |
| printOperand(MI, 0, STI, O); |
| return; |
| break; |
| case 7: |
| // DMXXEXTFDMR256, DMXXINSTFDMR256, XXSPLTW, XXSPLTWs |
| printU2ImmOperand(MI, 2, STI, O); |
| return; |
| break; |
| case 8: |
| // DST, DST64, DSTST, DSTST64, DSTSTT, DSTSTT64, DSTT, DSTT64 |
| printU5ImmOperand(MI, 0, STI, O); |
| return; |
| break; |
| case 9: |
| // EVADDIW, XXPERMDIs, XXSLDWIs |
| printOperand(MI, 1, STI, O); |
| break; |
| case 10: |
| // PADDI, PADDI8 |
| printS34ImmOperand(MI, 2, STI, O); |
| O << ", 0"; |
| return; |
| break; |
| case 11: |
| // PMXVBF16GER2NN, PMXVBF16GER2NP, PMXVBF16GER2PN, PMXVBF16GER2PP, PMXVBF... |
| printOperand(MI, 3, STI, O); |
| break; |
| case 12: |
| // RLDIMI, RLDIMI_rec |
| printU6ImmOperand(MI, 3, STI, O); |
| O << ", "; |
| printU6ImmOperand(MI, 4, STI, O); |
| return; |
| break; |
| case 13: |
| // RLWIMI, RLWIMI8, RLWIMI8_rec, RLWIMI_rec |
| printU5ImmOperand(MI, 3, STI, O); |
| O << ", "; |
| printU5ImmOperand(MI, 4, STI, O); |
| O << ", "; |
| printU5ImmOperand(MI, 5, STI, O); |
| return; |
| break; |
| case 14: |
| // VCFSX, VCFUX, VCTSXS, VCTUXS, VSPLTB, VSPLTBs, VSPLTH, VSPLTHs, VSPLTW |
| printU5ImmOperand(MI, 1, STI, O); |
| return; |
| break; |
| case 15: |
| // VEXTRACTD, VEXTRACTUB, VEXTRACTUH, VEXTRACTUW, VINSERTD, VINSERTW |
| printU4ImmOperand(MI, 1, STI, O); |
| return; |
| break; |
| case 16: |
| // VGNB |
| printU3ImmOperand(MI, 2, STI, O); |
| return; |
| break; |
| case 17: |
| // XSTSTDCDP, XSTSTDCQP, XSTSTDCSP, XVTSTDCDP, XVTSTDCSP |
| printU7ImmOperand(MI, 1, STI, O); |
| return; |
| break; |
| case 18: |
| // XXEXTRACTUW |
| printU4ImmOperand(MI, 2, STI, O); |
| return; |
| break; |
| case 19: |
| // XXGENPCVBM, XXGENPCVDM, XXGENPCVHM, XXGENPCVWM |
| printS5ImmOperand(MI, 2, STI, O); |
| return; |
| break; |
| case 20: |
| // XXINSERTW |
| printU4ImmOperand(MI, 3, STI, O); |
| return; |
| break; |
| case 21: |
| // gBC, gBCL |
| printBranchOperand(MI, Address, 2, STI, O); |
| return; |
| break; |
| case 22: |
| // gBCA, gBCLA |
| printAbsBranchOperand(MI, 2, STI, O); |
| return; |
| break; |
| } |
| |
| |
| // Fragment 5 encoded into 2 bits for 4 unique commands. |
| switch ((Bits >> 38) & 3) { |
| default: llvm_unreachable("Invalid command number."); |
| case 0: |
| // CLRLSLDI, CLRLSLDI_rec, CLRLSLWI, CLRLSLWI_rec, EXTLDI, EXTLDI_rec, EX... |
| O << ", "; |
| break; |
| case 1: |
| // CLRRDI, CLRRDI_rec, CLRRWI, CLRRWI_rec, ROTRDI, ROTRDI_rec, ROTRWI, RO... |
| return; |
| break; |
| case 2: |
| // DMXXINSTFDMR512 |
| O << ", 0"; |
| return; |
| break; |
| case 3: |
| // DMXXINSTFDMR512_HI |
| O << ", 1"; |
| return; |
| break; |
| } |
| |
| |
| // Fragment 6 encoded into 4 bits for 9 unique commands. |
| switch ((Bits >> 40) & 15) { |
| default: llvm_unreachable("Invalid command number."); |
| case 0: |
| // CLRLSLDI, CLRLSLDI_rec, EXTLDI, EXTLDI_rec, EXTRDI, EXTRDI_rec, INSRDI... |
| printU6ImmOperand(MI, 3, STI, O); |
| return; |
| break; |
| case 1: |
| // CLRLSLWI, CLRLSLWI_rec, EXTLWI, EXTLWI_rec, EXTRWI, EXTRWI_rec, INSLWI... |
| printU5ImmOperand(MI, 3, STI, O); |
| break; |
| case 2: |
| // RLWIMIbm, RLWIMIbm_rec, RLWINMbm, RLWINMbm_rec, RLWNMbm, RLWNMbm_rec, ... |
| printOperand(MI, 3, STI, O); |
| break; |
| case 3: |
| // ADDEX, ADDEX8, XXPERMDI, XXSLDWI |
| printU2ImmOperand(MI, 3, STI, O); |
| return; |
| break; |
| case 4: |
| // BCDADD_rec, BCDSR_rec, BCDSUB_rec, BCDS_rec, BCDTRUNC_rec |
| printU1ImmOperand(MI, 3, STI, O); |
| return; |
| break; |
| case 5: |
| // PMXVBF16GER2, PMXVBF16GER2W, PMXVF16GER2, PMXVF16GER2W, PMXVF32GER, PM... |
| printU4ImmOperand(MI, 3, STI, O); |
| break; |
| case 6: |
| // PMXVBF16GER2NN, PMXVBF16GER2NP, PMXVBF16GER2PN, PMXVBF16GER2PP, PMXVBF... |
| printU4ImmOperand(MI, 4, STI, O); |
| O << ", "; |
| break; |
| case 7: |
| // VSLDBI, VSRDBI |
| printU3ImmOperand(MI, 3, STI, O); |
| return; |
| break; |
| case 8: |
| // XXPERMDIs, XXSLDWIs |
| printU2ImmOperand(MI, 2, STI, O); |
| return; |
| break; |
| } |
| |
| |
| // Fragment 7 encoded into 2 bits for 4 unique commands. |
| switch ((Bits >> 44) & 3) { |
| default: llvm_unreachable("Invalid command number."); |
| case 0: |
| // CLRLSLWI, CLRLSLWI_rec, EXTLWI, EXTLWI_rec, EXTRWI, EXTRWI_rec, INSLWI... |
| return; |
| break; |
| case 1: |
| // PMXVBF16GER2, PMXVBF16GER2W, PMXVF16GER2, PMXVF16GER2W, PMXVF32GER, PM... |
| O << ", "; |
| break; |
| case 2: |
| // PMXVBF16GER2NN, PMXVBF16GER2NP, PMXVBF16GER2PN, PMXVBF16GER2PP, PMXVBF... |
| printU4ImmOperand(MI, 5, STI, O); |
| break; |
| case 3: |
| // PMXVF64GERNN, PMXVF64GERNP, PMXVF64GERPN, PMXVF64GERPP, PMXVF64GERWNN,... |
| printU2ImmOperand(MI, 5, STI, O); |
| return; |
| break; |
| } |
| |
| |
| // Fragment 8 encoded into 3 bits for 7 unique commands. |
| switch ((Bits >> 46) & 7) { |
| default: llvm_unreachable("Invalid command number."); |
| case 0: |
| // PMXVBF16GER2, PMXVBF16GER2W, PMXVF16GER2, PMXVF16GER2W, PMXVF32GER, PM... |
| printU4ImmOperand(MI, 4, STI, O); |
| break; |
| case 1: |
| // PMXVBF16GER2NN, PMXVBF16GER2NP, PMXVBF16GER2PN, PMXVBF16GER2PP, PMXVBF... |
| O << ", "; |
| break; |
| case 2: |
| // PMXVF32GERNN, PMXVF32GERNP, PMXVF32GERPN, PMXVF32GERPP, PMXVF32GERWNN,... |
| return; |
| break; |
| case 3: |
| // PMXVF64GER, PMXVF64GERW |
| printU2ImmOperand(MI, 4, STI, O); |
| return; |
| break; |
| case 4: |
| // RLWINM, RLWINM8, RLWINM8_rec, RLWINM_rec, RLWNM, RLWNM8, RLWNM8_rec, R... |
| printU5ImmOperand(MI, 4, STI, O); |
| return; |
| break; |
| case 5: |
| // XXEVAL |
| printU8ImmOperand(MI, 4, STI, O); |
| return; |
| break; |
| case 6: |
| // XXPERMX |
| printU3ImmOperand(MI, 4, STI, O); |
| return; |
| break; |
| } |
| |
| |
| // Fragment 9 encoded into 3 bits for 5 unique commands. |
| switch ((Bits >> 49) & 7) { |
| default: llvm_unreachable("Invalid command number."); |
| case 0: |
| // PMXVBF16GER2, PMXVBF16GER2W, PMXVF16GER2, PMXVF16GER2W, PMXVI16GER2, P... |
| O << ", "; |
| break; |
| case 1: |
| // PMXVBF16GER2NN, PMXVBF16GER2NP, PMXVBF16GER2PN, PMXVBF16GER2PP, PMXVBF... |
| printU2ImmOperand(MI, 6, STI, O); |
| return; |
| break; |
| case 2: |
| // PMXVF32GER, PMXVF32GERW |
| return; |
| break; |
| case 3: |
| // PMXVI4GER8PP, PMXVI4GER8WPP |
| printU8ImmOperand(MI, 6, STI, O); |
| return; |
| break; |
| case 4: |
| // PMXVI8GER4PP, PMXVI8GER4SPP, PMXVI8GER4WPP, PMXVI8GER4WSPP |
| printU4ImmOperand(MI, 6, STI, O); |
| return; |
| break; |
| } |
| |
| |
| // Fragment 10 encoded into 2 bits for 3 unique commands. |
| switch ((Bits >> 52) & 3) { |
| default: llvm_unreachable("Invalid command number."); |
| case 0: |
| // PMXVBF16GER2, PMXVBF16GER2W, PMXVF16GER2, PMXVF16GER2W, PMXVI16GER2, P... |
| printU2ImmOperand(MI, 5, STI, O); |
| return; |
| break; |
| case 1: |
| // PMXVI4GER8, PMXVI4GER8W |
| printU8ImmOperand(MI, 5, STI, O); |
| return; |
| break; |
| case 2: |
| // PMXVI8GER4, PMXVI8GER4W |
| printU4ImmOperand(MI, 5, STI, O); |
| return; |
| break; |
| } |
| |
| } |
| |
| |
| /// getRegisterName - This method is automatically generated by tblgen |
| /// from the register set description. This returns the assembler name |
| /// for the specified register. |
| const char *PPCInstPrinter::getRegisterName(MCRegister Reg) { |
| unsigned RegNo = Reg.id(); |
| assert(RegNo && RegNo < 500 && "Invalid register number!"); |
| |
| |
| #ifdef __GNUC__ |
| #pragma GCC diagnostic push |
| #pragma GCC diagnostic ignored "-Woverlength-strings" |
| #endif |
| static const char AsmStrs[] = { |
| /* 0 */ "**ROUNDING MODE**\0" |
| /* 18 */ "**FRAME POINTER**\0" |
| /* 36 */ "**BASE POINTER**\0" |
| /* 53 */ "f10\0" |
| /* 57 */ "vsp10\0" |
| /* 63 */ "dmrrowp10\0" |
| /* 73 */ "r10\0" |
| /* 77 */ "vs10\0" |
| /* 82 */ "v10\0" |
| /* 86 */ "dmrrow10\0" |
| /* 95 */ "f20\0" |
| /* 99 */ "vsp20\0" |
| /* 105 */ "dmrrowp20\0" |
| /* 115 */ "r20\0" |
| /* 119 */ "vs20\0" |
| /* 124 */ "v20\0" |
| /* 128 */ "dmrrow20\0" |
| /* 137 */ "f30\0" |
| /* 141 */ "vsp30\0" |
| /* 147 */ "dmrrowp30\0" |
| /* 157 */ "r30\0" |
| /* 161 */ "vs30\0" |
| /* 166 */ "v30\0" |
| /* 170 */ "dmrrow30\0" |
| /* 179 */ "vsp40\0" |
| /* 185 */ "vs40\0" |
| /* 190 */ "dmrrow40\0" |
| /* 199 */ "vsp50\0" |
| /* 205 */ "vs50\0" |
| /* 210 */ "dmrrow50\0" |
| /* 219 */ "vsp60\0" |
| /* 225 */ "vs60\0" |
| /* 230 */ "dmrrow60\0" |
| /* 239 */ "wacc0\0" |
| /* 245 */ "f0\0" |
| /* 248 */ "wacc_hi0\0" |
| /* 257 */ "dmrp0\0" |
| /* 263 */ "vsp0\0" |
| /* 268 */ "dmrrowp0\0" |
| /* 277 */ "cr0\0" |
| /* 281 */ "dmr0\0" |
| /* 286 */ "vs0\0" |
| /* 290 */ "v0\0" |
| /* 293 */ "dmrrow0\0" |
| /* 301 */ "f11\0" |
| /* 305 */ "dmrrowp11\0" |
| /* 315 */ "r11\0" |
| /* 319 */ "vs11\0" |
| /* 324 */ "v11\0" |
| /* 328 */ "dmrrow11\0" |
| /* 337 */ "f21\0" |
| /* 341 */ "dmrrowp21\0" |
| /* 351 */ "r21\0" |
| /* 355 */ "vs21\0" |
| /* 360 */ "v21\0" |
| /* 364 */ "dmrrow21\0" |
| /* 373 */ "f31\0" |
| /* 377 */ "dmrrowp31\0" |
| /* 387 */ "r31\0" |
| /* 391 */ "vs31\0" |
| /* 396 */ "v31\0" |
| /* 400 */ "dmrrow31\0" |
| /* 409 */ "vs41\0" |
| /* 414 */ "dmrrow41\0" |
| /* 423 */ "vs51\0" |
| /* 428 */ "dmrrow51\0" |
| /* 437 */ "vs61\0" |
| /* 442 */ "dmrrow61\0" |
| /* 451 */ "wacc1\0" |
| /* 457 */ "f1\0" |
| /* 460 */ "wacc_hi1\0" |
| /* 469 */ "dmrp1\0" |
| /* 475 */ "dmrrowp1\0" |
| /* 484 */ "cr1\0" |
| /* 488 */ "dmr1\0" |
| /* 493 */ "vs1\0" |
| /* 497 */ "v1\0" |
| /* 500 */ "dmrrow1\0" |
| /* 508 */ "f12\0" |
| /* 512 */ "vsp12\0" |
| /* 518 */ "dmrrowp12\0" |
| /* 528 */ "r12\0" |
| /* 532 */ "vs12\0" |
| /* 537 */ "v12\0" |
| /* 541 */ "dmrrow12\0" |
| /* 550 */ "f22\0" |
| /* 554 */ "vsp22\0" |
| /* 560 */ "dmrrowp22\0" |
| /* 570 */ "r22\0" |
| /* 574 */ "vs22\0" |
| /* 579 */ "v22\0" |
| /* 583 */ "dmrrow22\0" |
| /* 592 */ "vsp32\0" |
| /* 598 */ "vs32\0" |
| /* 603 */ "dmrrow32\0" |
| /* 612 */ "vsp42\0" |
| /* 618 */ "vs42\0" |
| /* 623 */ "dmrrow42\0" |
| /* 632 */ "vsp52\0" |
| /* 638 */ "vs52\0" |
| /* 643 */ "dmrrow52\0" |
| /* 652 */ "vsp62\0" |
| /* 658 */ "vs62\0" |
| /* 663 */ "dmrrow62\0" |
| /* 672 */ "wacc2\0" |
| /* 678 */ "f2\0" |
| /* 681 */ "wacc_hi2\0" |
| /* 690 */ "dmrp2\0" |
| /* 696 */ "vsp2\0" |
| /* 701 */ "dmrrowp2\0" |
| /* 710 */ "cr2\0" |
| /* 714 */ "dmr2\0" |
| /* 719 */ "vs2\0" |
| /* 723 */ "v2\0" |
| /* 726 */ "dmrrow2\0" |
| /* 734 */ "f13\0" |
| /* 738 */ "dmrrowp13\0" |
| /* 748 */ "r13\0" |
| /* 752 */ "vs13\0" |
| /* 757 */ "v13\0" |
| /* 761 */ "dmrrow13\0" |
| /* 770 */ "f23\0" |
| /* 774 */ "dmrrowp23\0" |
| /* 784 */ "r23\0" |
| /* 788 */ "vs23\0" |
| /* 793 */ "v23\0" |
| /* 797 */ "dmrrow23\0" |
| /* 806 */ "vs33\0" |
| /* 811 */ "dmrrow33\0" |
| /* 820 */ "vs43\0" |
| /* 825 */ "dmrrow43\0" |
| /* 834 */ "vs53\0" |
| /* 839 */ "dmrrow53\0" |
| /* 848 */ "vs63\0" |
| /* 853 */ "dmrrow63\0" |
| /* 862 */ "wacc3\0" |
| /* 868 */ "f3\0" |
| /* 871 */ "wacc_hi3\0" |
| /* 880 */ "dmrp3\0" |
| /* 886 */ "dmrrowp3\0" |
| /* 895 */ "cr3\0" |
| /* 899 */ "dmr3\0" |
| /* 904 */ "vs3\0" |
| /* 908 */ "v3\0" |
| /* 911 */ "dmrrow3\0" |
| /* 919 */ "f14\0" |
| /* 923 */ "vsp14\0" |
| /* 929 */ "dmrrowp14\0" |
| /* 939 */ "r14\0" |
| /* 943 */ "vs14\0" |
| /* 948 */ "v14\0" |
| /* 952 */ "dmrrow14\0" |
| /* 961 */ "f24\0" |
| /* 965 */ "vsp24\0" |
| /* 971 */ "dmrrowp24\0" |
| /* 981 */ "r24\0" |
| /* 985 */ "vs24\0" |
| /* 990 */ "v24\0" |
| /* 994 */ "dmrrow24\0" |
| /* 1003 */ "vsp34\0" |
| /* 1009 */ "vs34\0" |
| /* 1014 */ "dmrrow34\0" |
| /* 1023 */ "vsp44\0" |
| /* 1029 */ "vs44\0" |
| /* 1034 */ "dmrrow44\0" |
| /* 1043 */ "vsp54\0" |
| /* 1049 */ "vs54\0" |
| /* 1054 */ "dmrrow54\0" |
| /* 1063 */ "wacc4\0" |
| /* 1069 */ "f4\0" |
| /* 1072 */ "wacc_hi4\0" |
| /* 1081 */ "vsp4\0" |
| /* 1086 */ "dmrrowp4\0" |
| /* 1095 */ "cr4\0" |
| /* 1099 */ "dmr4\0" |
| /* 1104 */ "vs4\0" |
| /* 1108 */ "v4\0" |
| /* 1111 */ "dmrrow4\0" |
| /* 1119 */ "f15\0" |
| /* 1123 */ "dmrrowp15\0" |
| /* 1133 */ "r15\0" |
| /* 1137 */ "vs15\0" |
| /* 1142 */ "v15\0" |
| /* 1146 */ "dmrrow15\0" |
| /* 1155 */ "f25\0" |
| /* 1159 */ "dmrrowp25\0" |
| /* 1169 */ "r25\0" |
| /* 1173 */ "vs25\0" |
| /* 1178 */ "v25\0" |
| /* 1182 */ "dmrrow25\0" |
| /* 1191 */ "vs35\0" |
| /* 1196 */ "dmrrow35\0" |
| /* 1205 */ "vs45\0" |
| /* 1210 */ "dmrrow45\0" |
| /* 1219 */ "vs55\0" |
| /* 1224 */ "dmrrow55\0" |
| /* 1233 */ "wacc5\0" |
| /* 1239 */ "f5\0" |
| /* 1242 */ "wacc_hi5\0" |
| /* 1251 */ "dmrrowp5\0" |
| /* 1260 */ "cr5\0" |
| /* 1264 */ "dmr5\0" |
| /* 1269 */ "vs5\0" |
| /* 1273 */ "v5\0" |
| /* 1276 */ "dmrrow5\0" |
| /* 1284 */ "f16\0" |
| /* 1288 */ "vsp16\0" |
| /* 1294 */ "dmrrowp16\0" |
| /* 1304 */ "r16\0" |
| /* 1308 */ "vs16\0" |
| /* 1313 */ "v16\0" |
| /* 1317 */ "dmrrow16\0" |
| /* 1326 */ "f26\0" |
| /* 1330 */ "vsp26\0" |
| /* 1336 */ "dmrrowp26\0" |
| /* 1346 */ "r26\0" |
| /* 1350 */ "vs26\0" |
| /* 1355 */ "v26\0" |
| /* 1359 */ "dmrrow26\0" |
| /* 1368 */ "vsp36\0" |
| /* 1374 */ "vs36\0" |
| /* 1379 */ "dmrrow36\0" |
| /* 1388 */ "vsp46\0" |
| /* 1394 */ "vs46\0" |
| /* 1399 */ "dmrrow46\0" |
| /* 1408 */ "vsp56\0" |
| /* 1414 */ "vs56\0" |
| /* 1419 */ "dmrrow56\0" |
| /* 1428 */ "wacc6\0" |
| /* 1434 */ "f6\0" |
| /* 1437 */ "wacc_hi6\0" |
| /* 1446 */ "vsp6\0" |
| /* 1451 */ "dmrrowp6\0" |
| /* 1460 */ "cr6\0" |
| /* 1464 */ "dmr6\0" |
| /* 1469 */ "vs6\0" |
| /* 1473 */ "v6\0" |
| /* 1476 */ "dmrrow6\0" |
| /* 1484 */ "f17\0" |
| /* 1488 */ "dmrrowp17\0" |
| /* 1498 */ "r17\0" |
| /* 1502 */ "vs17\0" |
| /* 1507 */ "v17\0" |
| /* 1511 */ "dmrrow17\0" |
| /* 1520 */ "f27\0" |
| /* 1524 */ "dmrrowp27\0" |
| /* 1534 */ "r27\0" |
| /* 1538 */ "vs27\0" |
| /* 1543 */ "v27\0" |
| /* 1547 */ "dmrrow27\0" |
| /* 1556 */ "vs37\0" |
| /* 1561 */ "dmrrow37\0" |
| /* 1570 */ "vs47\0" |
| /* 1575 */ "dmrrow47\0" |
| /* 1584 */ "vs57\0" |
| /* 1589 */ "dmrrow57\0" |
| /* 1598 */ "wacc7\0" |
| /* 1604 */ "f7\0" |
| /* 1607 */ "wacc_hi7\0" |
| /* 1616 */ "dmrrowp7\0" |
| /* 1625 */ "cr7\0" |
| /* 1629 */ "dmr7\0" |
| /* 1634 */ "vs7\0" |
| /* 1638 */ "v7\0" |
| /* 1641 */ "dmrrow7\0" |
| /* 1649 */ "f18\0" |
| /* 1653 */ "vsp18\0" |
| /* 1659 */ "dmrrowp18\0" |
| /* 1669 */ "r18\0" |
| /* 1673 */ "vs18\0" |
| /* 1678 */ "v18\0" |
| /* 1682 */ "dmrrow18\0" |
| /* 1691 */ "f28\0" |
| /* 1695 */ "vsp28\0" |
| /* 1701 */ "dmrrowp28\0" |
| /* 1711 */ "r28\0" |
| /* 1715 */ "vs28\0" |
| /* 1720 */ "v28\0" |
| /* 1724 */ "dmrrow28\0" |
| /* 1733 */ "vsp38\0" |
| /* 1739 */ "vs38\0" |
| /* 1744 */ "dmrrow38\0" |
| /* 1753 */ "vsp48\0" |
| /* 1759 */ "vs48\0" |
| /* 1764 */ "dmrrow48\0" |
| /* 1773 */ "vsp58\0" |
| /* 1779 */ "vs58\0" |
| /* 1784 */ "dmrrow58\0" |
| /* 1793 */ "f8\0" |
| /* 1796 */ "vsp8\0" |
| /* 1801 */ "dmrrowp8\0" |
| /* 1810 */ "r8\0" |
| /* 1813 */ "vs8\0" |
| /* 1817 */ "v8\0" |
| /* 1820 */ "dmrrow8\0" |
| /* 1828 */ "f19\0" |
| /* 1832 */ "dmrrowp19\0" |
| /* 1842 */ "r19\0" |
| /* 1846 */ "vs19\0" |
| /* 1851 */ "v19\0" |
| /* 1855 */ "dmrrow19\0" |
| /* 1864 */ "f29\0" |
| /* 1868 */ "dmrrowp29\0" |
| /* 1878 */ "r29\0" |
| /* 1882 */ "vs29\0" |
| /* 1887 */ "v29\0" |
| /* 1891 */ "dmrrow29\0" |
| /* 1900 */ "vs39\0" |
| /* 1905 */ "dmrrow39\0" |
| /* 1914 */ "vs49\0" |
| /* 1919 */ "dmrrow49\0" |
| /* 1928 */ "vs59\0" |
| /* 1933 */ "dmrrow59\0" |
| /* 1942 */ "f9\0" |
| /* 1945 */ "dmrrowp9\0" |
| /* 1954 */ "r9\0" |
| /* 1957 */ "vs9\0" |
| /* 1961 */ "v9\0" |
| /* 1964 */ "dmrrow9\0" |
| /* 1972 */ "vrsave\0" |
| /* 1979 */ "spefscr\0" |
| /* 1987 */ "xer\0" |
| /* 1991 */ "lr\0" |
| /* 1994 */ "ctr\0" |
| }; |
| #ifdef __GNUC__ |
| #pragma GCC diagnostic pop |
| #endif |
| |
| static const uint16_t RegAsmOffset[] = { |
| 36, 1987, 1994, 18, 1991, 0, 1979, 1972, 1987, 55, 240, 452, 673, 863, |
| 1064, 1234, 1429, 1599, 36, 277, 484, 710, 895, 1095, 1260, 1460, 1625, 1994, |
| 281, 488, 714, 899, 1099, 1264, 1464, 1629, 293, 500, 726, 911, 1111, 1276, |
| 1476, 1641, 1820, 1964, 86, 328, 541, 761, 952, 1146, 1317, 1511, 1682, 1855, |
| 128, 364, 583, 797, 994, 1182, 1359, 1547, 1724, 1891, 170, 400, 603, 811, |
| 1014, 1196, 1379, 1561, 1744, 1905, 190, 414, 623, 825, 1034, 1210, 1399, 1575, |
| 1764, 1919, 210, 428, 643, 839, 1054, 1224, 1419, 1589, 1784, 1933, 230, 442, |
| 663, 853, 268, 475, 701, 886, 1086, 1251, 1451, 1616, 1801, 1945, 63, 305, |
| 518, 738, 929, 1123, 1294, 1488, 1659, 1832, 105, 341, 560, 774, 971, 1159, |
| 1336, 1524, 1701, 1868, 147, 377, 257, 469, 690, 880, 245, 457, 678, 868, |
| 1069, 1239, 1434, 1604, 1793, 1942, 53, 301, 508, 734, 919, 1119, 1284, 1484, |
| 1649, 1828, 95, 337, 550, 770, 961, 1155, 1326, 1520, 1691, 1864, 137, 373, |
| 18, 1991, 278, 485, 711, 896, 1096, 1261, 1461, 1626, 1810, 1954, 73, 315, |
| 528, 748, 939, 1133, 1304, 1498, 1669, 1842, 115, 351, 570, 784, 981, 1169, |
| 1346, 1534, 1711, 1878, 157, 387, 278, 485, 711, 896, 1096, 1261, 1461, 1626, |
| 1810, 1954, 73, 315, 528, 748, 939, 1133, 1304, 1498, 1669, 1842, 115, 351, |
| 570, 784, 981, 1169, 1346, 1534, 1711, 1878, 157, 387, 240, 452, 673, 863, |
| 1064, 1234, 1429, 1599, 290, 497, 723, 908, 1108, 1273, 1473, 1638, 1817, 1961, |
| 82, 324, 537, 757, 948, 1142, 1313, 1507, 1678, 1851, 124, 360, 579, 793, |
| 990, 1178, 1355, 1543, 1720, 1887, 166, 396, 290, 497, 723, 908, 1108, 1273, |
| 1473, 1638, 1817, 1961, 82, 324, 537, 757, 948, 1142, 1313, 1507, 1678, 1851, |
| 124, 360, 579, 793, 990, 1178, 1355, 1543, 1720, 1887, 166, 396, 286, 493, |
| 719, 904, 1104, 1269, 1469, 1634, 1813, 1957, 77, 319, 532, 752, 943, 1137, |
| 1308, 1502, 1673, 1846, 119, 355, 574, 788, 985, 1173, 1350, 1538, 1715, 1882, |
| 161, 391, 263, 696, 1081, 1446, 1796, 57, 512, 923, 1288, 1653, 99, 554, |
| 965, 1330, 1695, 141, 592, 1003, 1368, 1733, 179, 612, 1023, 1388, 1753, 199, |
| 632, 1043, 1408, 1773, 219, 652, 598, 806, 1009, 1191, 1374, 1556, 1739, 1900, |
| 185, 409, 618, 820, 1029, 1205, 1394, 1570, 1759, 1914, 205, 423, 638, 834, |
| 1049, 1219, 1414, 1584, 1779, 1928, 225, 437, 658, 848, 239, 451, 672, 862, |
| 1063, 1233, 1428, 1598, 248, 460, 681, 871, 1072, 1242, 1437, 1607, 278, 485, |
| 711, 896, 1096, 1261, 1461, 1626, 1810, 1954, 73, 315, 528, 748, 939, 1133, |
| 1304, 1498, 1669, 1842, 115, 351, 570, 784, 981, 1169, 1346, 1534, 1711, 1878, |
| 157, 387, 55, 510, 1286, 54, 920, 1650, 551, 1327, 138, 303, 1121, 1830, |
| 735, 1485, 338, 1156, 1865, 55, 921, 1651, 509, 1285, 96, 962, 1692, 736, |
| 1486, 302, 1120, 1829, 771, 1521, 374, 278, 711, 1096, 1461, 1810, 73, 528, |
| 939, 1304, 1669, 115, 570, 981, 1346, 1711, 157, |
| }; |
| |
| assert (*(AsmStrs+RegAsmOffset[RegNo-1]) && |
| "Invalid alt name index for register!"); |
| return AsmStrs+RegAsmOffset[RegNo-1]; |
| } |
| |
| #ifdef PRINT_ALIAS_INSTR |
| #undef PRINT_ALIAS_INSTR |
| |
| bool PPCInstPrinter::printAliasInstr(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &OS) { |
| static const PatternsForOpcode OpToPatterns[] = { |
| {PPC::ADDI, 0, 1 }, |
| {PPC::ADDI8, 1, 1 }, |
| {PPC::ADDIS, 2, 1 }, |
| {PPC::ADDIS8, 3, 1 }, |
| {PPC::ADDPCIS, 4, 1 }, |
| {PPC::BCC, 5, 24 }, |
| {PPC::BCCA, 29, 24 }, |
| {PPC::BCCCTR, 53, 24 }, |
| {PPC::BCCCTRL, 77, 24 }, |
| {PPC::BCCL, 101, 24 }, |
| {PPC::BCCLA, 125, 24 }, |
| {PPC::BCCLR, 149, 24 }, |
| {PPC::BCCLRL, 173, 24 }, |
| {PPC::CMPD, 197, 1 }, |
| {PPC::CMPDI, 198, 1 }, |
| {PPC::CMPLD, 199, 1 }, |
| {PPC::CMPLDI, 200, 1 }, |
| {PPC::CMPLW, 201, 1 }, |
| {PPC::CMPLWI, 202, 1 }, |
| {PPC::CMPW, 203, 1 }, |
| {PPC::CMPWI, 204, 1 }, |
| {PPC::CNTLZW, 205, 1 }, |
| {PPC::CNTLZW8, 206, 1 }, |
| {PPC::CNTLZW8_rec, 207, 1 }, |
| {PPC::CNTLZW_rec, 208, 1 }, |
| {PPC::CP_PASTE_rec, 209, 1 }, |
| {PPC::CREQV, 210, 1 }, |
| {PPC::CRNOR, 211, 1 }, |
| {PPC::CROR, 212, 1 }, |
| {PPC::CRXOR, 213, 1 }, |
| {PPC::ISEL, 214, 3 }, |
| {PPC::ISEL8, 217, 3 }, |
| {PPC::MBAR, 220, 1 }, |
| {PPC::MFDCR, 221, 8 }, |
| {PPC::MFSPR, 229, 46 }, |
| {PPC::MFSPR8, 275, 19 }, |
| {PPC::MFTB, 294, 1 }, |
| {PPC::MFUDSCR, 295, 1 }, |
| {PPC::MFVRSAVE, 296, 1 }, |
| {PPC::MFVSRD, 297, 1 }, |
| {PPC::MFVSRWZ, 298, 1 }, |
| {PPC::MTCRF, 299, 1 }, |
| {PPC::MTCRF8, 300, 1 }, |
| {PPC::MTDCR, 301, 8 }, |
| {PPC::MTFSF, 309, 1 }, |
| {PPC::MTFSFI, 310, 1 }, |
| {PPC::MTFSFI_rec, 311, 1 }, |
| {PPC::MTFSF_rec, 312, 1 }, |
| {PPC::MTMSR, 313, 1 }, |
| {PPC::MTMSRD, 314, 1 }, |
| {PPC::MTSPR, 315, 45 }, |
| {PPC::MTSPR8, 360, 18 }, |
| {PPC::MTUDSCR, 378, 1 }, |
| {PPC::MTVRSAVE, 379, 1 }, |
| {PPC::MTVSRD, 380, 1 }, |
| {PPC::MTVSRWA, 381, 1 }, |
| {PPC::MTVSRWZ, 382, 1 }, |
| {PPC::NOR, 383, 1 }, |
| {PPC::NOR8, 384, 1 }, |
| {PPC::NOR8_rec, 385, 1 }, |
| {PPC::NOR_rec, 386, 1 }, |
| {PPC::OR, 387, 1 }, |
| {PPC::OR8, 388, 1 }, |
| {PPC::OR8_rec, 389, 1 }, |
| {PPC::ORI, 390, 1 }, |
| {PPC::ORI8, 391, 1 }, |
| {PPC::OR_rec, 392, 1 }, |
| {PPC::RFEBB, 393, 1 }, |
| {PPC::RLDCL, 394, 1 }, |
| {PPC::RLDCL_rec, 395, 1 }, |
| {PPC::RLDICL, 396, 2 }, |
| {PPC::RLDICL_32_64, 398, 2 }, |
| {PPC::RLDICL_rec, 400, 2 }, |
| {PPC::RLWINM, 402, 2 }, |
| {PPC::RLWINM8, 404, 2 }, |
| {PPC::RLWINM8_rec, 406, 2 }, |
| {PPC::RLWINM_rec, 408, 2 }, |
| {PPC::RLWNM, 410, 1 }, |
| {PPC::RLWNM8, 411, 1 }, |
| {PPC::RLWNM8_rec, 412, 1 }, |
| {PPC::RLWNM_rec, 413, 1 }, |
| {PPC::SC, 414, 1 }, |
| {PPC::SUBF, 415, 1 }, |
| {PPC::SUBF8, 416, 1 }, |
| {PPC::SUBF8_rec, 417, 1 }, |
| {PPC::SUBFC, 418, 1 }, |
| {PPC::SUBFC8, 419, 1 }, |
| {PPC::SUBFC8_rec, 420, 1 }, |
| {PPC::SUBFC_rec, 421, 1 }, |
| {PPC::SUBF_rec, 422, 1 }, |
| {PPC::SYNC, 423, 3 }, |
| {PPC::TD, 426, 7 }, |
| {PPC::TDI, 433, 7 }, |
| {PPC::TEND, 440, 2 }, |
| {PPC::TLBIE, 442, 1 }, |
| {PPC::TLBRE2, 443, 2 }, |
| {PPC::TLBWE2, 445, 2 }, |
| {PPC::TSR, 447, 2 }, |
| {PPC::TW, 449, 8 }, |
| {PPC::TWI, 457, 7 }, |
| {PPC::VNOR, 464, 1 }, |
| {PPC::VOR, 465, 1 }, |
| {PPC::WAIT, 466, 3 }, |
| {PPC::XORI, 469, 1 }, |
| {PPC::XORI8, 470, 1 }, |
| {PPC::XVCPSGNDP, 471, 1 }, |
| {PPC::XVCPSGNSP, 472, 1 }, |
| {PPC::XXPERMDI, 473, 5 }, |
| {PPC::XXPERMDIs, 478, 3 }, |
| {PPC::gBC, 481, 10 }, |
| {PPC::gBCA, 491, 10 }, |
| {PPC::gBCAat, 501, 2 }, |
| {PPC::gBCCTR, 503, 7 }, |
| {PPC::gBCCTRL, 510, 7 }, |
| {PPC::gBCL, 517, 10 }, |
| {PPC::gBCLA, 527, 10 }, |
| {PPC::gBCLAat, 537, 2 }, |
| {PPC::gBCLR, 539, 11 }, |
| {PPC::gBCLRL, 550, 11 }, |
| {PPC::gBCLat, 561, 2 }, |
| {PPC::gBCat, 563, 2 }, |
| }; |
| |
| static const AliasPattern Patterns[] = { |
| // PPC::ADDI - 0 |
| {0, 0, 3, 2 }, |
| // PPC::ADDI8 - 1 |
| {0, 2, 3, 2 }, |
| // PPC::ADDIS - 2 |
| {12, 4, 3, 2 }, |
| // PPC::ADDIS8 - 3 |
| {12, 6, 3, 2 }, |
| // PPC::ADDPCIS - 4 |
| {25, 8, 2, 2 }, |
| // PPC::BCC - 5 |
| {33, 10, 3, 2 }, |
| {46, 12, 3, 2 }, |
| {55, 14, 3, 2 }, |
| {69, 16, 3, 2 }, |
| {79, 18, 3, 2 }, |
| {93, 20, 3, 2 }, |
| {103, 22, 3, 2 }, |
| {116, 24, 3, 2 }, |
| {125, 26, 3, 2 }, |
| {139, 28, 3, 2 }, |
| {149, 30, 3, 2 }, |
| {163, 32, 3, 2 }, |
| {173, 34, 3, 2 }, |
| {186, 36, 3, 2 }, |
| {195, 38, 3, 2 }, |
| {209, 40, 3, 2 }, |
| {219, 42, 3, 2 }, |
| {233, 44, 3, 2 }, |
| {243, 46, 3, 2 }, |
| {256, 48, 3, 2 }, |
| {265, 50, 3, 2 }, |
| {279, 52, 3, 2 }, |
| {289, 54, 3, 2 }, |
| {303, 56, 3, 2 }, |
| // PPC::BCCA - 29 |
| {313, 58, 3, 2 }, |
| {327, 60, 3, 2 }, |
| {337, 62, 3, 2 }, |
| {352, 64, 3, 2 }, |
| {363, 66, 3, 2 }, |
| {378, 68, 3, 2 }, |
| {389, 70, 3, 2 }, |
| {403, 72, 3, 2 }, |
| {413, 74, 3, 2 }, |
| {428, 76, 3, 2 }, |
| {439, 78, 3, 2 }, |
| {454, 80, 3, 2 }, |
| {465, 82, 3, 2 }, |
| {479, 84, 3, 2 }, |
| {489, 86, 3, 2 }, |
| {504, 88, 3, 2 }, |
| {515, 90, 3, 2 }, |
| {530, 92, 3, 2 }, |
| {541, 94, 3, 2 }, |
| {555, 96, 3, 2 }, |
| {565, 98, 3, 2 }, |
| {580, 100, 3, 2 }, |
| {591, 102, 3, 2 }, |
| {606, 104, 3, 2 }, |
| // PPC::BCCCTR - 53 |
| {617, 106, 2, 2 }, |
| {627, 108, 2, 2 }, |
| {634, 110, 2, 2 }, |
| {645, 112, 2, 2 }, |
| {653, 114, 2, 2 }, |
| {664, 116, 2, 2 }, |
| {672, 118, 2, 2 }, |
| {682, 120, 2, 2 }, |
| {689, 122, 2, 2 }, |
| {700, 124, 2, 2 }, |
| {708, 126, 2, 2 }, |
| {719, 128, 2, 2 }, |
| {727, 130, 2, 2 }, |
| {737, 132, 2, 2 }, |
| {744, 134, 2, 2 }, |
| {755, 136, 2, 2 }, |
| {763, 138, 2, 2 }, |
| {774, 140, 2, 2 }, |
| {782, 142, 2, 2 }, |
| {792, 144, 2, 2 }, |
| {799, 146, 2, 2 }, |
| {810, 148, 2, 2 }, |
| {818, 150, 2, 2 }, |
| {829, 152, 2, 2 }, |
| // PPC::BCCCTRL - 77 |
| {837, 154, 2, 2 }, |
| {848, 156, 2, 2 }, |
| {856, 158, 2, 2 }, |
| {868, 160, 2, 2 }, |
| {877, 162, 2, 2 }, |
| {889, 164, 2, 2 }, |
| {898, 166, 2, 2 }, |
| {909, 168, 2, 2 }, |
| {917, 170, 2, 2 }, |
| {929, 172, 2, 2 }, |
| {938, 174, 2, 2 }, |
| {950, 176, 2, 2 }, |
| {959, 178, 2, 2 }, |
| {970, 180, 2, 2 }, |
| {978, 182, 2, 2 }, |
| {990, 184, 2, 2 }, |
| {999, 186, 2, 2 }, |
| {1011, 188, 2, 2 }, |
| {1020, 190, 2, 2 }, |
| {1031, 192, 2, 2 }, |
| {1039, 194, 2, 2 }, |
| {1051, 196, 2, 2 }, |
| {1060, 198, 2, 2 }, |
| {1072, 200, 2, 2 }, |
| // PPC::BCCL - 101 |
| {1081, 202, 3, 2 }, |
| {1095, 204, 3, 2 }, |
| {1105, 206, 3, 2 }, |
| {1120, 208, 3, 2 }, |
| {1131, 210, 3, 2 }, |
| {1146, 212, 3, 2 }, |
| {1157, 214, 3, 2 }, |
| {1171, 216, 3, 2 }, |
| {1181, 218, 3, 2 }, |
| {1196, 220, 3, 2 }, |
| {1207, 222, 3, 2 }, |
| {1222, 224, 3, 2 }, |
| {1233, 226, 3, 2 }, |
| {1247, 228, 3, 2 }, |
| {1257, 230, 3, 2 }, |
| {1272, 232, 3, 2 }, |
| {1283, 234, 3, 2 }, |
| {1298, 236, 3, 2 }, |
| {1309, 238, 3, 2 }, |
| {1323, 240, 3, 2 }, |
| {1333, 242, 3, 2 }, |
| {1348, 244, 3, 2 }, |
| {1359, 246, 3, 2 }, |
| {1374, 248, 3, 2 }, |
| // PPC::BCCLA - 125 |
| {1385, 250, 3, 2 }, |
| {1400, 252, 3, 2 }, |
| {1411, 254, 3, 2 }, |
| {1427, 256, 3, 2 }, |
| {1439, 258, 3, 2 }, |
| {1455, 260, 3, 2 }, |
| {1467, 262, 3, 2 }, |
| {1482, 264, 3, 2 }, |
| {1493, 266, 3, 2 }, |
| {1509, 268, 3, 2 }, |
| {1521, 270, 3, 2 }, |
| {1537, 272, 3, 2 }, |
| {1549, 274, 3, 2 }, |
| {1564, 276, 3, 2 }, |
| {1575, 278, 3, 2 }, |
| {1591, 280, 3, 2 }, |
| {1603, 282, 3, 2 }, |
| {1619, 284, 3, 2 }, |
| {1631, 286, 3, 2 }, |
| {1646, 288, 3, 2 }, |
| {1657, 290, 3, 2 }, |
| {1673, 292, 3, 2 }, |
| {1685, 294, 3, 2 }, |
| {1701, 296, 3, 2 }, |
| // PPC::BCCLR - 149 |
| {1713, 298, 2, 2 }, |
| {1722, 300, 2, 2 }, |
| {1728, 302, 2, 2 }, |
| {1738, 304, 2, 2 }, |
| {1745, 306, 2, 2 }, |
| {1755, 308, 2, 2 }, |
| {1762, 310, 2, 2 }, |
| {1771, 312, 2, 2 }, |
| {1777, 314, 2, 2 }, |
| {1787, 316, 2, 2 }, |
| {1794, 318, 2, 2 }, |
| {1804, 320, 2, 2 }, |
| {1811, 322, 2, 2 }, |
| {1820, 324, 2, 2 }, |
| {1826, 326, 2, 2 }, |
| {1836, 328, 2, 2 }, |
| {1843, 330, 2, 2 }, |
| {1853, 332, 2, 2 }, |
| {1860, 334, 2, 2 }, |
| {1869, 336, 2, 2 }, |
| {1875, 338, 2, 2 }, |
| {1885, 340, 2, 2 }, |
| {1892, 342, 2, 2 }, |
| {1902, 344, 2, 2 }, |
| // PPC::BCCLRL - 173 |
| {1909, 346, 2, 2 }, |
| {1919, 348, 2, 2 }, |
| {1926, 350, 2, 2 }, |
| {1937, 352, 2, 2 }, |
| {1945, 354, 2, 2 }, |
| {1956, 356, 2, 2 }, |
| {1964, 358, 2, 2 }, |
| {1974, 360, 2, 2 }, |
| {1981, 362, 2, 2 }, |
| {1992, 364, 2, 2 }, |
| {2000, 366, 2, 2 }, |
| {2011, 368, 2, 2 }, |
| {2019, 370, 2, 2 }, |
| {2029, 372, 2, 2 }, |
| {2036, 374, 2, 2 }, |
| {2047, 376, 2, 2 }, |
| {2055, 378, 2, 2 }, |
| {2066, 380, 2, 2 }, |
| {2074, 382, 2, 2 }, |
| {2084, 384, 2, 2 }, |
| {2091, 386, 2, 2 }, |
| {2102, 388, 2, 2 }, |
| {2110, 390, 2, 2 }, |
| {2121, 392, 2, 2 }, |
| // PPC::CMPD - 197 |
| {2129, 394, 3, 3 }, |
| // PPC::CMPDI - 198 |
| {2141, 397, 3, 2 }, |
| // PPC::CMPLD - 199 |
| {2156, 399, 3, 3 }, |
| // PPC::CMPLDI - 200 |
| {2169, 402, 3, 2 }, |
| // PPC::CMPLW - 201 |
| {2185, 404, 3, 3 }, |
| // PPC::CMPLWI - 202 |
| {2198, 407, 3, 2 }, |
| // PPC::CMPW - 203 |
| {2214, 409, 3, 3 }, |
| // PPC::CMPWI - 204 |
| {2226, 412, 3, 2 }, |
| // PPC::CNTLZW - 205 |
| {2241, 414, 2, 2 }, |
| // PPC::CNTLZW8 - 206 |
| {2241, 416, 2, 2 }, |
| // PPC::CNTLZW8_rec - 207 |
| {2255, 418, 2, 2 }, |
| // PPC::CNTLZW_rec - 208 |
| {2255, 420, 2, 2 }, |
| // PPC::CP_PASTE_rec - 209 |
| {2270, 422, 3, 3 }, |
| // PPC::CREQV - 210 |
| {2284, 425, 3, 3 }, |
| // PPC::CRNOR - 211 |
| {2293, 428, 3, 3 }, |
| // PPC::CROR - 212 |
| {2306, 431, 3, 3 }, |
| // PPC::CRXOR - 213 |
| {2320, 434, 3, 3 }, |
| // PPC::ISEL - 214 |
| {2329, 437, 4, 4 }, |
| {2347, 441, 4, 4 }, |
| {2365, 445, 4, 4 }, |
| // PPC::ISEL8 - 217 |
| {2329, 449, 4, 4 }, |
| {2347, 453, 4, 4 }, |
| {2365, 457, 4, 4 }, |
| // PPC::MBAR - 220 |
| {2383, 461, 1, 1 }, |
| // PPC::MFDCR - 221 |
| {2388, 462, 2, 5 }, |
| {2397, 467, 2, 5 }, |
| {2406, 472, 2, 5 }, |
| {2415, 477, 2, 5 }, |
| {2424, 482, 2, 5 }, |
| {2433, 487, 2, 5 }, |
| {2442, 492, 2, 5 }, |
| {2451, 497, 2, 5 }, |
| // PPC::MFSPR - 229 |
| {2460, 502, 2, 2 }, |
| {2469, 504, 2, 5 }, |
| {2480, 509, 2, 5 }, |
| {2490, 514, 2, 5 }, |
| {2500, 519, 2, 5 }, |
| {2508, 524, 2, 5 }, |
| {2517, 529, 2, 5 }, |
| {2527, 534, 2, 5 }, |
| {2537, 539, 2, 5 }, |
| {2548, 544, 2, 5 }, |
| {2557, 549, 2, 5 }, |
| {2566, 554, 2, 5 }, |
| {2576, 559, 2, 5 }, |
| {2586, 564, 2, 5 }, |
| {2596, 569, 2, 5 }, |
| {2606, 574, 2, 5 }, |
| {2615, 579, 2, 5 }, |
| {2624, 584, 2, 5 }, |
| {2633, 589, 2, 5 }, |
| {2642, 594, 2, 5 }, |
| {2655, 599, 2, 5 }, |
| {2669, 604, 2, 5 }, |
| {2683, 609, 2, 5 }, |
| {2697, 614, 2, 5 }, |
| {2711, 619, 2, 5 }, |
| {2725, 624, 2, 5 }, |
| {2739, 629, 2, 5 }, |
| {2753, 634, 2, 5 }, |
| {2767, 639, 2, 5 }, |
| {2781, 644, 2, 5 }, |
| {2795, 649, 2, 5 }, |
| {2809, 654, 2, 5 }, |
| {2823, 659, 2, 5 }, |
| {2837, 664, 2, 5 }, |
| {2851, 669, 2, 5 }, |
| {2865, 674, 2, 5 }, |
| {2879, 679, 2, 5 }, |
| {2888, 684, 2, 5 }, |
| {2897, 689, 2, 5 }, |
| {2907, 694, 2, 5 }, |
| {2916, 699, 2, 5 }, |
| {2926, 704, 2, 5 }, |
| {2936, 709, 2, 5 }, |
| {2946, 714, 2, 5 }, |
| {2956, 719, 2, 5 }, |
| {2966, 724, 2, 5 }, |
| // PPC::MFSPR8 - 275 |
| {2460, 729, 2, 2 }, |
| {2469, 731, 2, 5 }, |
| {2480, 736, 2, 5 }, |
| {2490, 741, 2, 5 }, |
| {2500, 746, 2, 5 }, |
| {2508, 751, 2, 5 }, |
| {2517, 756, 2, 5 }, |
| {2527, 761, 2, 5 }, |
| {2537, 766, 2, 5 }, |
| {2548, 771, 2, 5 }, |
| {2557, 776, 2, 5 }, |
| {2566, 781, 2, 5 }, |
| {2576, 786, 2, 5 }, |
| {2586, 791, 2, 5 }, |
| {2596, 796, 2, 5 }, |
| {2606, 801, 2, 5 }, |
| {2624, 806, 2, 5 }, |
| {2633, 811, 2, 5 }, |
| {2642, 816, 2, 5 }, |
| // PPC::MFTB - 294 |
| {2976, 821, 2, 2 }, |
| // PPC::MFUDSCR - 295 |
| {2469, 823, 1, 4 }, |
| // PPC::MFVRSAVE - 296 |
| {2985, 827, 1, 1 }, |
| // PPC::MFVSRD - 297 |
| {2997, 828, 2, 2 }, |
| // PPC::MFVSRWZ - 298 |
| {3011, 830, 2, 2 }, |
| // PPC::MTCRF - 299 |
| {3026, 832, 2, 2 }, |
| // PPC::MTCRF8 - 300 |
| {3026, 834, 2, 2 }, |
| // PPC::MTDCR - 301 |
| {3034, 836, 2, 5 }, |
| {3043, 841, 2, 5 }, |
| {3052, 846, 2, 5 }, |
| {3061, 851, 2, 5 }, |
| {3070, 856, 2, 5 }, |
| {3079, 861, 2, 5 }, |
| {3088, 866, 2, 5 }, |
| {3097, 871, 2, 5 }, |
| // PPC::MTFSF - 309 |
| {3106, 876, 4, 4 }, |
| // PPC::MTFSFI - 310 |
| {3119, 880, 3, 3 }, |
| // PPC::MTFSFI_rec - 311 |
| {3137, 883, 3, 3 }, |
| // PPC::MTFSF_rec - 312 |
| {3156, 886, 4, 4 }, |
| // PPC::MTMSR - 313 |
| {3170, 890, 2, 5 }, |
| // PPC::MTMSRD - 314 |
| {3179, 895, 2, 5 }, |
| // PPC::MTSPR - 315 |
| {3189, 900, 2, 2 }, |
| {3198, 902, 2, 5 }, |
| {3209, 907, 2, 5 }, |
| {3217, 912, 2, 5 }, |
| {3226, 917, 2, 5 }, |
| {3236, 922, 2, 5 }, |
| {3246, 927, 2, 5 }, |
| {3257, 932, 2, 5 }, |
| {3266, 937, 2, 5 }, |
| {3275, 942, 2, 5 }, |
| {3285, 947, 2, 5 }, |
| {3295, 952, 2, 5 }, |
| {3305, 957, 2, 5 }, |
| {3315, 962, 2, 5 }, |
| {3324, 967, 2, 5 }, |
| {3333, 972, 2, 5 }, |
| {3342, 977, 2, 5 }, |
| {3351, 982, 2, 5 }, |
| {3360, 987, 2, 5 }, |
| {3373, 992, 2, 5 }, |
| {3387, 997, 2, 5 }, |
| {3401, 1002, 2, 5 }, |
| {3415, 1007, 2, 5 }, |
| {3429, 1012, 2, 5 }, |
| {3443, 1017, 2, 5 }, |
| {3457, 1022, 2, 5 }, |
| {3471, 1027, 2, 5 }, |
| {3485, 1032, 2, 5 }, |
| {3499, 1037, 2, 5 }, |
| {3513, 1042, 2, 5 }, |
| {3527, 1047, 2, 5 }, |
| {3541, 1052, 2, 5 }, |
| {3555, 1057, 2, 5 }, |
| {3569, 1062, 2, 5 }, |
| {3583, 1067, 2, 5 }, |
| {3597, 1072, 2, 5 }, |
| {3606, 1077, 2, 5 }, |
| {3615, 1082, 2, 5 }, |
| {3625, 1087, 2, 5 }, |
| {3634, 1092, 2, 5 }, |
| {3644, 1097, 2, 5 }, |
| {3654, 1102, 2, 5 }, |
| {3664, 1107, 2, 5 }, |
| {3674, 1112, 2, 5 }, |
| {3684, 1117, 2, 5 }, |
| // PPC::MTSPR8 - 360 |
| {3189, 1122, 2, 2 }, |
| {3198, 1124, 2, 5 }, |
| {3209, 1129, 2, 5 }, |
| {3217, 1134, 2, 5 }, |
| {3226, 1139, 2, 5 }, |
| {3236, 1144, 2, 5 }, |
| {3246, 1149, 2, 5 }, |
| {3257, 1154, 2, 5 }, |
| {3266, 1159, 2, 5 }, |
| {3275, 1164, 2, 5 }, |
| {3285, 1169, 2, 5 }, |
| {3295, 1174, 2, 5 }, |
| {3305, 1179, 2, 5 }, |
| {3315, 1184, 2, 5 }, |
| {3333, 1189, 2, 5 }, |
| {3342, 1194, 2, 5 }, |
| {3351, 1199, 2, 5 }, |
| {3360, 1204, 2, 5 }, |
| // PPC::MTUDSCR - 378 |
| {3694, 1209, 1, 4 }, |
| // PPC::MTVRSAVE - 379 |
| {3705, 1213, 1, 1 }, |
| // PPC::MTVSRD - 380 |
| {3717, 1214, 2, 2 }, |
| // PPC::MTVSRWA - 381 |
| {3731, 1216, 2, 2 }, |
| // PPC::MTVSRWZ - 382 |
| {3746, 1218, 2, 2 }, |
| // PPC::NOR - 383 |
| {3761, 1220, 3, 3 }, |
| // PPC::NOR8 - 384 |
| {3761, 1223, 3, 3 }, |
| // PPC::NOR8_rec - 385 |
| {3772, 1226, 3, 3 }, |
| // PPC::NOR_rec - 386 |
| {3772, 1229, 3, 3 }, |
| // PPC::OR - 387 |
| {3784, 1232, 3, 3 }, |
| // PPC::OR8 - 388 |
| {3784, 1235, 3, 3 }, |
| // PPC::OR8_rec - 389 |
| {3794, 1238, 3, 3 }, |
| // PPC::ORI - 390 |
| {3805, 1241, 3, 3 }, |
| // PPC::ORI8 - 391 |
| {3805, 1244, 3, 3 }, |
| // PPC::OR_rec - 392 |
| {3794, 1247, 3, 3 }, |
| // PPC::RFEBB - 393 |
| {3809, 1250, 1, 1 }, |
| // PPC::RLDCL - 394 |
| {3815, 1251, 4, 4 }, |
| // PPC::RLDCL_rec - 395 |
| {3832, 1255, 4, 4 }, |
| // PPC::RLDICL - 396 |
| {3850, 1259, 4, 4 }, |
| {3870, 1263, 4, 3 }, |
| // PPC::RLDICL_32_64 - 398 |
| {3850, 1266, 4, 4 }, |
| {3870, 1270, 4, 3 }, |
| // PPC::RLDICL_rec - 400 |
| {3890, 1273, 4, 4 }, |
| {3911, 1277, 4, 3 }, |
| // PPC::RLWINM - 402 |
| {3932, 1280, 5, 5 }, |
| {3952, 1285, 5, 5 }, |
| // PPC::RLWINM8 - 404 |
| {3932, 1290, 5, 5 }, |
| {3952, 1295, 5, 5 }, |
| // PPC::RLWINM8_rec - 406 |
| {3972, 1300, 5, 5 }, |
| {3993, 1305, 5, 5 }, |
| // PPC::RLWINM_rec - 408 |
| {3972, 1310, 5, 5 }, |
| {3993, 1315, 5, 5 }, |
| // PPC::RLWNM - 410 |
| {4014, 1320, 5, 5 }, |
| // PPC::RLWNM8 - 411 |
| {4014, 1325, 5, 5 }, |
| // PPC::RLWNM8_rec - 412 |
| {4031, 1330, 5, 5 }, |
| // PPC::RLWNM_rec - 413 |
| {4031, 1335, 5, 5 }, |
| // PPC::SC - 414 |
| {4049, 1340, 1, 1 }, |
| // PPC::SUBF - 415 |
| {4052, 1341, 3, 3 }, |
| // PPC::SUBF8 - 416 |
| {4052, 1344, 3, 3 }, |
| // PPC::SUBF8_rec - 417 |
| {4067, 1347, 3, 3 }, |
| // PPC::SUBFC - 418 |
| {4083, 1350, 3, 3 }, |
| // PPC::SUBFC8 - 419 |
| {4083, 1353, 3, 3 }, |
| // PPC::SUBFC8_rec - 420 |
| {4099, 1356, 3, 3 }, |
| // PPC::SUBFC_rec - 421 |
| {4099, 1359, 3, 3 }, |
| // PPC::SUBF_rec - 422 |
| {4067, 1362, 3, 3 }, |
| // PPC::SYNC - 423 |
| {4116, 1365, 1, 1 }, |
| {4121, 1366, 1, 1 }, |
| {4128, 1367, 1, 1 }, |
| // PPC::TD - 426 |
| {4136, 1368, 3, 3 }, |
| {4148, 1371, 3, 3 }, |
| {4160, 1374, 3, 3 }, |
| {4172, 1377, 3, 3 }, |
| {4184, 1380, 3, 3 }, |
| {4197, 1383, 3, 3 }, |
| {4210, 1386, 3, 3 }, |
| // PPC::TDI - 433 |
| {4221, 1389, 3, 2 }, |
| {4236, 1391, 3, 2 }, |
| {4251, 1393, 3, 2 }, |
| {4266, 1395, 3, 2 }, |
| {4281, 1397, 3, 2 }, |
| {4297, 1399, 3, 2 }, |
| {4313, 1401, 3, 2 }, |
| // PPC::TEND - 440 |
| {4327, 1403, 1, 1 }, |
| {4333, 1404, 1, 1 }, |
| // PPC::TLBIE - 442 |
| {4342, 1405, 2, 2 }, |
| // PPC::TLBRE2 - 443 |
| {4351, 1407, 3, 3 }, |
| {4366, 1410, 3, 3 }, |
| // PPC::TLBWE2 - 445 |
| {4381, 1413, 3, 3 }, |
| {4396, 1416, 3, 3 }, |
| // PPC::TSR - 447 |
| {4411, 1419, 1, 1 }, |
| {4421, 1420, 1, 1 }, |
| // PPC::TW - 449 |
| {4430, 1421, 3, 3 }, |
| {4435, 1424, 3, 3 }, |
| {4447, 1427, 3, 3 }, |
| {4459, 1430, 3, 3 }, |
| {4471, 1433, 3, 3 }, |
| {4483, 1436, 3, 3 }, |
| {4496, 1439, 3, 3 }, |
| {4509, 1442, 3, 3 }, |
| // PPC::TWI - 457 |
| {4520, 1445, 3, 2 }, |
| {4535, 1447, 3, 2 }, |
| {4550, 1449, 3, 2 }, |
| {4565, 1451, 3, 2 }, |
| {4580, 1453, 3, 2 }, |
| {4596, 1455, 3, 2 }, |
| {4612, 1457, 3, 2 }, |
| // PPC::VNOR - 464 |
| {4626, 1459, 3, 3 }, |
| // PPC::VOR - 465 |
| {4638, 1462, 3, 3 }, |
| // PPC::WAIT - 466 |
| {4649, 1465, 1, 1 }, |
| {4654, 1466, 1, 1 }, |
| {4662, 1467, 1, 1 }, |
| // PPC::XORI - 469 |
| {4671, 1468, 3, 3 }, |
| // PPC::XORI8 - 470 |
| {4671, 1471, 3, 3 }, |
| // PPC::XVCPSGNDP - 471 |
| {4676, 1474, 3, 3 }, |
| // PPC::XVCPSGNSP - 472 |
| {4691, 1477, 3, 3 }, |
| // PPC::XXPERMDI - 473 |
| {4706, 1480, 4, 7 }, |
| {4724, 1487, 4, 7 }, |
| {4742, 1494, 4, 4 }, |
| {4761, 1498, 4, 4 }, |
| {4780, 1502, 4, 4 }, |
| // PPC::XXPERMDIs - 478 |
| {4706, 1506, 3, 6 }, |
| {4724, 1512, 3, 6 }, |
| {4780, 1518, 3, 3 }, |
| // PPC::gBC - 481 |
| {4795, 1521, 3, 2 }, |
| {4807, 1523, 3, 2 }, |
| {4819, 1525, 3, 2 }, |
| {4832, 1527, 3, 2 }, |
| {4845, 1529, 3, 2 }, |
| {4858, 1531, 3, 2 }, |
| {4871, 1533, 3, 2 }, |
| {4886, 1535, 3, 2 }, |
| {4901, 1537, 3, 2 }, |
| {4915, 1539, 3, 2 }, |
| // PPC::gBCA - 491 |
| {4929, 1541, 3, 2 }, |
| {4942, 1543, 3, 2 }, |
| {4955, 1545, 3, 2 }, |
| {4969, 1547, 3, 2 }, |
| {4983, 1549, 3, 2 }, |
| {4997, 1551, 3, 2 }, |
| {5011, 1553, 3, 2 }, |
| {5027, 1555, 3, 2 }, |
| {5043, 1557, 3, 2 }, |
| {5058, 1559, 3, 2 }, |
| // PPC::gBCAat - 501 |
| {5073, 1561, 4, 3 }, |
| {5093, 1564, 4, 3 }, |
| // PPC::gBCCTR - 503 |
| {5113, 1567, 3, 3 }, |
| {5128, 1570, 3, 3 }, |
| {5137, 1573, 3, 3 }, |
| {5146, 1576, 3, 3 }, |
| {5156, 1579, 3, 3 }, |
| {5166, 1582, 3, 3 }, |
| {5176, 1585, 3, 3 }, |
| // PPC::gBCCTRL - 510 |
| {5186, 1588, 3, 3 }, |
| {5202, 1591, 3, 3 }, |
| {5212, 1594, 3, 3 }, |
| {5222, 1597, 3, 3 }, |
| {5233, 1600, 3, 3 }, |
| {5244, 1603, 3, 3 }, |
| {5255, 1606, 3, 3 }, |
| // PPC::gBCL - 517 |
| {5266, 1609, 3, 2 }, |
| {5279, 1611, 3, 2 }, |
| {5292, 1613, 3, 2 }, |
| {5306, 1615, 3, 2 }, |
| {5320, 1617, 3, 2 }, |
| {5334, 1619, 3, 2 }, |
| {5348, 1621, 3, 2 }, |
| {5364, 1623, 3, 2 }, |
| {5380, 1625, 3, 2 }, |
| {5395, 1627, 3, 2 }, |
| // PPC::gBCLA - 527 |
| {5410, 1629, 3, 2 }, |
| {5424, 1631, 3, 2 }, |
| {5438, 1633, 3, 2 }, |
| {5453, 1635, 3, 2 }, |
| {5468, 1637, 3, 2 }, |
| {5483, 1639, 3, 2 }, |
| {5498, 1641, 3, 2 }, |
| {5515, 1643, 3, 2 }, |
| {5532, 1645, 3, 2 }, |
| {5548, 1647, 3, 2 }, |
| // PPC::gBCLAat - 537 |
| {5564, 1649, 4, 3 }, |
| {5585, 1652, 4, 3 }, |
| // PPC::gBCLR - 539 |
| {5606, 1655, 3, 3 }, |
| {5620, 1658, 3, 3 }, |
| {5628, 1661, 3, 3 }, |
| {5636, 1664, 3, 3 }, |
| {5645, 1667, 3, 3 }, |
| {5654, 1670, 3, 3 }, |
| {5663, 1673, 3, 3 }, |
| {5672, 1676, 3, 3 }, |
| {5683, 1679, 3, 3 }, |
| {5694, 1682, 3, 3 }, |
| {5704, 1685, 3, 3 }, |
| // PPC::gBCLRL - 550 |
| {5714, 1688, 3, 3 }, |
| {5729, 1691, 3, 3 }, |
| {5738, 1694, 3, 3 }, |
| {5747, 1697, 3, 3 }, |
| {5757, 1700, 3, 3 }, |
| {5767, 1703, 3, 3 }, |
| {5777, 1706, 3, 3 }, |
| {5787, 1709, 3, 3 }, |
| {5799, 1712, 3, 3 }, |
| {5811, 1715, 3, 3 }, |
| {5822, 1718, 3, 3 }, |
| // PPC::gBCLat - 561 |
| {5833, 1721, 4, 3 }, |
| {5853, 1724, 4, 3 }, |
| // PPC::gBCat - 563 |
| {5873, 1727, 4, 3 }, |
| {5892, 1730, 4, 3 }, |
| }; |
| |
| static const AliasPatternCond Conds[] = { |
| // (ADDI gprc:$rD, ZERO, s16imm:$imm) - 0 |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_Reg, PPC::ZERO}, |
| // (ADDI8 g8rc:$rD, ZERO8, s16imm64:$imm) - 2 |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| {AliasPatternCond::K_Reg, PPC::ZERO8}, |
| // (ADDIS gprc:$rD, ZERO, s17imm:$imm) - 4 |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_Reg, PPC::ZERO}, |
| // (ADDIS8 g8rc:$rD, ZERO8, s17imm64:$imm) - 6 |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| {AliasPatternCond::K_Reg, PPC::ZERO8}, |
| // (ADDPCIS g8rc:$RT, 0) - 8 |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (BCC 12, crrc:$cc, condbrtarget:$dst) - 10 |
| {AliasPatternCond::K_Imm, uint32_t(12)}, |
| {AliasPatternCond::K_RegClass, PPC::CRRCRegClassID}, |
| // (BCC 12, CR0, condbrtarget:$dst) - 12 |
| {AliasPatternCond::K_Imm, uint32_t(12)}, |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| // (BCC 14, crrc:$cc, condbrtarget:$dst) - 14 |
| {AliasPatternCond::K_Imm, uint32_t(14)}, |
| {AliasPatternCond::K_RegClass, PPC::CRRCRegClassID}, |
| // (BCC 14, CR0, condbrtarget:$dst) - 16 |
| {AliasPatternCond::K_Imm, uint32_t(14)}, |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| // (BCC 15, crrc:$cc, condbrtarget:$dst) - 18 |
| {AliasPatternCond::K_Imm, uint32_t(15)}, |
| {AliasPatternCond::K_RegClass, PPC::CRRCRegClassID}, |
| // (BCC 15, CR0, condbrtarget:$dst) - 20 |
| {AliasPatternCond::K_Imm, uint32_t(15)}, |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| // (BCC 44, crrc:$cc, condbrtarget:$dst) - 22 |
| {AliasPatternCond::K_Imm, uint32_t(44)}, |
| {AliasPatternCond::K_RegClass, PPC::CRRCRegClassID}, |
| // (BCC 44, CR0, condbrtarget:$dst) - 24 |
| {AliasPatternCond::K_Imm, uint32_t(44)}, |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| // (BCC 46, crrc:$cc, condbrtarget:$dst) - 26 |
| {AliasPatternCond::K_Imm, uint32_t(46)}, |
| {AliasPatternCond::K_RegClass, PPC::CRRCRegClassID}, |
| // (BCC 46, CR0, condbrtarget:$dst) - 28 |
| {AliasPatternCond::K_Imm, uint32_t(46)}, |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| // (BCC 47, crrc:$cc, condbrtarget:$dst) - 30 |
| {AliasPatternCond::K_Imm, uint32_t(47)}, |
| {AliasPatternCond::K_RegClass, PPC::CRRCRegClassID}, |
| // (BCC 47, CR0, condbrtarget:$dst) - 32 |
| {AliasPatternCond::K_Imm, uint32_t(47)}, |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| // (BCC 76, crrc:$cc, condbrtarget:$dst) - 34 |
| {AliasPatternCond::K_Imm, uint32_t(76)}, |
| {AliasPatternCond::K_RegClass, PPC::CRRCRegClassID}, |
| // (BCC 76, CR0, condbrtarget:$dst) - 36 |
| {AliasPatternCond::K_Imm, uint32_t(76)}, |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| // (BCC 78, crrc:$cc, condbrtarget:$dst) - 38 |
| {AliasPatternCond::K_Imm, uint32_t(78)}, |
| {AliasPatternCond::K_RegClass, PPC::CRRCRegClassID}, |
| // (BCC 78, CR0, condbrtarget:$dst) - 40 |
| {AliasPatternCond::K_Imm, uint32_t(78)}, |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| // (BCC 79, crrc:$cc, condbrtarget:$dst) - 42 |
| {AliasPatternCond::K_Imm, uint32_t(79)}, |
| {AliasPatternCond::K_RegClass, PPC::CRRCRegClassID}, |
| // (BCC 79, CR0, condbrtarget:$dst) - 44 |
| {AliasPatternCond::K_Imm, uint32_t(79)}, |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| // (BCC 68, crrc:$cc, condbrtarget:$dst) - 46 |
| {AliasPatternCond::K_Imm, uint32_t(68)}, |
| {AliasPatternCond::K_RegClass, PPC::CRRCRegClassID}, |
| // (BCC 68, CR0, condbrtarget:$dst) - 48 |
| {AliasPatternCond::K_Imm, uint32_t(68)}, |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| // (BCC 70, crrc:$cc, condbrtarget:$dst) - 50 |
| {AliasPatternCond::K_Imm, uint32_t(70)}, |
| {AliasPatternCond::K_RegClass, PPC::CRRCRegClassID}, |
| // (BCC 70, CR0, condbrtarget:$dst) - 52 |
| {AliasPatternCond::K_Imm, uint32_t(70)}, |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| // (BCC 71, crrc:$cc, condbrtarget:$dst) - 54 |
| {AliasPatternCond::K_Imm, uint32_t(71)}, |
| {AliasPatternCond::K_RegClass, PPC::CRRCRegClassID}, |
| // (BCC 71, CR0, condbrtarget:$dst) - 56 |
| {AliasPatternCond::K_Imm, uint32_t(71)}, |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| // (BCCA 12, crrc:$cc, abscondbrtarget:$dst) - 58 |
| {AliasPatternCond::K_Imm, uint32_t(12)}, |
| {AliasPatternCond::K_RegClass, PPC::CRRCRegClassID}, |
| // (BCCA 12, CR0, abscondbrtarget:$dst) - 60 |
| {AliasPatternCond::K_Imm, uint32_t(12)}, |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| // (BCCA 14, crrc:$cc, abscondbrtarget:$dst) - 62 |
| {AliasPatternCond::K_Imm, uint32_t(14)}, |
| {AliasPatternCond::K_RegClass, PPC::CRRCRegClassID}, |
| // (BCCA 14, CR0, abscondbrtarget:$dst) - 64 |
| {AliasPatternCond::K_Imm, uint32_t(14)}, |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| // (BCCA 15, crrc:$cc, abscondbrtarget:$dst) - 66 |
| {AliasPatternCond::K_Imm, uint32_t(15)}, |
| {AliasPatternCond::K_RegClass, PPC::CRRCRegClassID}, |
| // (BCCA 15, CR0, abscondbrtarget:$dst) - 68 |
| {AliasPatternCond::K_Imm, uint32_t(15)}, |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| // (BCCA 44, crrc:$cc, abscondbrtarget:$dst) - 70 |
| {AliasPatternCond::K_Imm, uint32_t(44)}, |
| {AliasPatternCond::K_RegClass, PPC::CRRCRegClassID}, |
| // (BCCA 44, CR0, abscondbrtarget:$dst) - 72 |
| {AliasPatternCond::K_Imm, uint32_t(44)}, |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| // (BCCA 46, crrc:$cc, abscondbrtarget:$dst) - 74 |
| {AliasPatternCond::K_Imm, uint32_t(46)}, |
| {AliasPatternCond::K_RegClass, PPC::CRRCRegClassID}, |
| // (BCCA 46, CR0, abscondbrtarget:$dst) - 76 |
| {AliasPatternCond::K_Imm, uint32_t(46)}, |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| // (BCCA 47, crrc:$cc, abscondbrtarget:$dst) - 78 |
| {AliasPatternCond::K_Imm, uint32_t(47)}, |
| {AliasPatternCond::K_RegClass, PPC::CRRCRegClassID}, |
| // (BCCA 47, CR0, abscondbrtarget:$dst) - 80 |
| {AliasPatternCond::K_Imm, uint32_t(47)}, |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| // (BCCA 76, crrc:$cc, abscondbrtarget:$dst) - 82 |
| {AliasPatternCond::K_Imm, uint32_t(76)}, |
| {AliasPatternCond::K_RegClass, PPC::CRRCRegClassID}, |
| // (BCCA 76, CR0, abscondbrtarget:$dst) - 84 |
| {AliasPatternCond::K_Imm, uint32_t(76)}, |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| // (BCCA 78, crrc:$cc, abscondbrtarget:$dst) - 86 |
| {AliasPatternCond::K_Imm, uint32_t(78)}, |
| {AliasPatternCond::K_RegClass, PPC::CRRCRegClassID}, |
| // (BCCA 78, CR0, abscondbrtarget:$dst) - 88 |
| {AliasPatternCond::K_Imm, uint32_t(78)}, |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| // (BCCA 79, crrc:$cc, abscondbrtarget:$dst) - 90 |
| {AliasPatternCond::K_Imm, uint32_t(79)}, |
| {AliasPatternCond::K_RegClass, PPC::CRRCRegClassID}, |
| // (BCCA 79, CR0, abscondbrtarget:$dst) - 92 |
| {AliasPatternCond::K_Imm, uint32_t(79)}, |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| // (BCCA 68, crrc:$cc, abscondbrtarget:$dst) - 94 |
| {AliasPatternCond::K_Imm, uint32_t(68)}, |
| {AliasPatternCond::K_RegClass, PPC::CRRCRegClassID}, |
| // (BCCA 68, CR0, abscondbrtarget:$dst) - 96 |
| {AliasPatternCond::K_Imm, uint32_t(68)}, |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| // (BCCA 70, crrc:$cc, abscondbrtarget:$dst) - 98 |
| {AliasPatternCond::K_Imm, uint32_t(70)}, |
| {AliasPatternCond::K_RegClass, PPC::CRRCRegClassID}, |
| // (BCCA 70, CR0, abscondbrtarget:$dst) - 100 |
| {AliasPatternCond::K_Imm, uint32_t(70)}, |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| // (BCCA 71, crrc:$cc, abscondbrtarget:$dst) - 102 |
| {AliasPatternCond::K_Imm, uint32_t(71)}, |
| {AliasPatternCond::K_RegClass, PPC::CRRCRegClassID}, |
| // (BCCA 71, CR0, abscondbrtarget:$dst) - 104 |
| {AliasPatternCond::K_Imm, uint32_t(71)}, |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| // (BCCCTR 12, crrc:$cc) - 106 |
| {AliasPatternCond::K_Imm, uint32_t(12)}, |
| {AliasPatternCond::K_RegClass, PPC::CRRCRegClassID}, |
| // (BCCCTR 12, CR0) - 108 |
| {AliasPatternCond::K_Imm, uint32_t(12)}, |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| // (BCCCTR 14, crrc:$cc) - 110 |
| {AliasPatternCond::K_Imm, uint32_t(14)}, |
| {AliasPatternCond::K_RegClass, PPC::CRRCRegClassID}, |
| // (BCCCTR 14, CR0) - 112 |
| {AliasPatternCond::K_Imm, uint32_t(14)}, |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| // (BCCCTR 15, crrc:$cc) - 114 |
| {AliasPatternCond::K_Imm, uint32_t(15)}, |
| {AliasPatternCond::K_RegClass, PPC::CRRCRegClassID}, |
| // (BCCCTR 15, CR0) - 116 |
| {AliasPatternCond::K_Imm, uint32_t(15)}, |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| // (BCCCTR 44, crrc:$cc) - 118 |
| {AliasPatternCond::K_Imm, uint32_t(44)}, |
| {AliasPatternCond::K_RegClass, PPC::CRRCRegClassID}, |
| // (BCCCTR 44, CR0) - 120 |
| {AliasPatternCond::K_Imm, uint32_t(44)}, |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| // (BCCCTR 46, crrc:$cc) - 122 |
| {AliasPatternCond::K_Imm, uint32_t(46)}, |
| {AliasPatternCond::K_RegClass, PPC::CRRCRegClassID}, |
| // (BCCCTR 46, CR0) - 124 |
| {AliasPatternCond::K_Imm, uint32_t(46)}, |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| // (BCCCTR 47, crrc:$cc) - 126 |
| {AliasPatternCond::K_Imm, uint32_t(47)}, |
| {AliasPatternCond::K_RegClass, PPC::CRRCRegClassID}, |
| // (BCCCTR 47, CR0) - 128 |
| {AliasPatternCond::K_Imm, uint32_t(47)}, |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| // (BCCCTR 76, crrc:$cc) - 130 |
| {AliasPatternCond::K_Imm, uint32_t(76)}, |
| {AliasPatternCond::K_RegClass, PPC::CRRCRegClassID}, |
| // (BCCCTR 76, CR0) - 132 |
| {AliasPatternCond::K_Imm, uint32_t(76)}, |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| // (BCCCTR 78, crrc:$cc) - 134 |
| {AliasPatternCond::K_Imm, uint32_t(78)}, |
| {AliasPatternCond::K_RegClass, PPC::CRRCRegClassID}, |
| // (BCCCTR 78, CR0) - 136 |
| {AliasPatternCond::K_Imm, uint32_t(78)}, |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| // (BCCCTR 79, crrc:$cc) - 138 |
| {AliasPatternCond::K_Imm, uint32_t(79)}, |
| {AliasPatternCond::K_RegClass, PPC::CRRCRegClassID}, |
| // (BCCCTR 79, CR0) - 140 |
| {AliasPatternCond::K_Imm, uint32_t(79)}, |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| // (BCCCTR 68, crrc:$cc) - 142 |
| {AliasPatternCond::K_Imm, uint32_t(68)}, |
| {AliasPatternCond::K_RegClass, PPC::CRRCRegClassID}, |
| // (BCCCTR 68, CR0) - 144 |
| {AliasPatternCond::K_Imm, uint32_t(68)}, |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| // (BCCCTR 70, crrc:$cc) - 146 |
| {AliasPatternCond::K_Imm, uint32_t(70)}, |
| {AliasPatternCond::K_RegClass, PPC::CRRCRegClassID}, |
| // (BCCCTR 70, CR0) - 148 |
| {AliasPatternCond::K_Imm, uint32_t(70)}, |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| // (BCCCTR 71, crrc:$cc) - 150 |
| {AliasPatternCond::K_Imm, uint32_t(71)}, |
| {AliasPatternCond::K_RegClass, PPC::CRRCRegClassID}, |
| // (BCCCTR 71, CR0) - 152 |
| {AliasPatternCond::K_Imm, uint32_t(71)}, |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| // (BCCCTRL 12, crrc:$cc) - 154 |
| {AliasPatternCond::K_Imm, uint32_t(12)}, |
| {AliasPatternCond::K_RegClass, PPC::CRRCRegClassID}, |
| // (BCCCTRL 12, CR0) - 156 |
| {AliasPatternCond::K_Imm, uint32_t(12)}, |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| // (BCCCTRL 14, crrc:$cc) - 158 |
| {AliasPatternCond::K_Imm, uint32_t(14)}, |
| {AliasPatternCond::K_RegClass, PPC::CRRCRegClassID}, |
| // (BCCCTRL 14, CR0) - 160 |
| {AliasPatternCond::K_Imm, uint32_t(14)}, |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| // (BCCCTRL 15, crrc:$cc) - 162 |
| {AliasPatternCond::K_Imm, uint32_t(15)}, |
| {AliasPatternCond::K_RegClass, PPC::CRRCRegClassID}, |
| // (BCCCTRL 15, CR0) - 164 |
| {AliasPatternCond::K_Imm, uint32_t(15)}, |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| // (BCCCTRL 44, crrc:$cc) - 166 |
| {AliasPatternCond::K_Imm, uint32_t(44)}, |
| {AliasPatternCond::K_RegClass, PPC::CRRCRegClassID}, |
| // (BCCCTRL 44, CR0) - 168 |
| {AliasPatternCond::K_Imm, uint32_t(44)}, |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| // (BCCCTRL 46, crrc:$cc) - 170 |
| {AliasPatternCond::K_Imm, uint32_t(46)}, |
| {AliasPatternCond::K_RegClass, PPC::CRRCRegClassID}, |
| // (BCCCTRL 46, CR0) - 172 |
| {AliasPatternCond::K_Imm, uint32_t(46)}, |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| // (BCCCTRL 47, crrc:$cc) - 174 |
| {AliasPatternCond::K_Imm, uint32_t(47)}, |
| {AliasPatternCond::K_RegClass, PPC::CRRCRegClassID}, |
| // (BCCCTRL 47, CR0) - 176 |
| {AliasPatternCond::K_Imm, uint32_t(47)}, |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| // (BCCCTRL 76, crrc:$cc) - 178 |
| {AliasPatternCond::K_Imm, uint32_t(76)}, |
| {AliasPatternCond::K_RegClass, PPC::CRRCRegClassID}, |
| // (BCCCTRL 76, CR0) - 180 |
| {AliasPatternCond::K_Imm, uint32_t(76)}, |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| // (BCCCTRL 78, crrc:$cc) - 182 |
| {AliasPatternCond::K_Imm, uint32_t(78)}, |
| {AliasPatternCond::K_RegClass, PPC::CRRCRegClassID}, |
| // (BCCCTRL 78, CR0) - 184 |
| {AliasPatternCond::K_Imm, uint32_t(78)}, |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| // (BCCCTRL 79, crrc:$cc) - 186 |
| {AliasPatternCond::K_Imm, uint32_t(79)}, |
| {AliasPatternCond::K_RegClass, PPC::CRRCRegClassID}, |
| // (BCCCTRL 79, CR0) - 188 |
| {AliasPatternCond::K_Imm, uint32_t(79)}, |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| // (BCCCTRL 68, crrc:$cc) - 190 |
| {AliasPatternCond::K_Imm, uint32_t(68)}, |
| {AliasPatternCond::K_RegClass, PPC::CRRCRegClassID}, |
| // (BCCCTRL 68, CR0) - 192 |
| {AliasPatternCond::K_Imm, uint32_t(68)}, |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| // (BCCCTRL 70, crrc:$cc) - 194 |
| {AliasPatternCond::K_Imm, uint32_t(70)}, |
| {AliasPatternCond::K_RegClass, PPC::CRRCRegClassID}, |
| // (BCCCTRL 70, CR0) - 196 |
| {AliasPatternCond::K_Imm, uint32_t(70)}, |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| // (BCCCTRL 71, crrc:$cc) - 198 |
| {AliasPatternCond::K_Imm, uint32_t(71)}, |
| {AliasPatternCond::K_RegClass, PPC::CRRCRegClassID}, |
| // (BCCCTRL 71, CR0) - 200 |
| {AliasPatternCond::K_Imm, uint32_t(71)}, |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| // (BCCL 12, crrc:$cc, condbrtarget:$dst) - 202 |
| {AliasPatternCond::K_Imm, uint32_t(12)}, |
| {AliasPatternCond::K_RegClass, PPC::CRRCRegClassID}, |
| // (BCCL 12, CR0, condbrtarget:$dst) - 204 |
| {AliasPatternCond::K_Imm, uint32_t(12)}, |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| // (BCCL 14, crrc:$cc, condbrtarget:$dst) - 206 |
| {AliasPatternCond::K_Imm, uint32_t(14)}, |
| {AliasPatternCond::K_RegClass, PPC::CRRCRegClassID}, |
| // (BCCL 14, CR0, condbrtarget:$dst) - 208 |
| {AliasPatternCond::K_Imm, uint32_t(14)}, |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| // (BCCL 15, crrc:$cc, condbrtarget:$dst) - 210 |
| {AliasPatternCond::K_Imm, uint32_t(15)}, |
| {AliasPatternCond::K_RegClass, PPC::CRRCRegClassID}, |
| // (BCCL 15, CR0, condbrtarget:$dst) - 212 |
| {AliasPatternCond::K_Imm, uint32_t(15)}, |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| // (BCCL 44, crrc:$cc, condbrtarget:$dst) - 214 |
| {AliasPatternCond::K_Imm, uint32_t(44)}, |
| {AliasPatternCond::K_RegClass, PPC::CRRCRegClassID}, |
| // (BCCL 44, CR0, condbrtarget:$dst) - 216 |
| {AliasPatternCond::K_Imm, uint32_t(44)}, |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| // (BCCL 46, crrc:$cc, condbrtarget:$dst) - 218 |
| {AliasPatternCond::K_Imm, uint32_t(46)}, |
| {AliasPatternCond::K_RegClass, PPC::CRRCRegClassID}, |
| // (BCCL 46, CR0, condbrtarget:$dst) - 220 |
| {AliasPatternCond::K_Imm, uint32_t(46)}, |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| // (BCCL 47, crrc:$cc, condbrtarget:$dst) - 222 |
| {AliasPatternCond::K_Imm, uint32_t(47)}, |
| {AliasPatternCond::K_RegClass, PPC::CRRCRegClassID}, |
| // (BCCL 47, CR0, condbrtarget:$dst) - 224 |
| {AliasPatternCond::K_Imm, uint32_t(47)}, |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| // (BCCL 76, crrc:$cc, condbrtarget:$dst) - 226 |
| {AliasPatternCond::K_Imm, uint32_t(76)}, |
| {AliasPatternCond::K_RegClass, PPC::CRRCRegClassID}, |
| // (BCCL 76, CR0, condbrtarget:$dst) - 228 |
| {AliasPatternCond::K_Imm, uint32_t(76)}, |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| // (BCCL 78, crrc:$cc, condbrtarget:$dst) - 230 |
| {AliasPatternCond::K_Imm, uint32_t(78)}, |
| {AliasPatternCond::K_RegClass, PPC::CRRCRegClassID}, |
| // (BCCL 78, CR0, condbrtarget:$dst) - 232 |
| {AliasPatternCond::K_Imm, uint32_t(78)}, |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| // (BCCL 79, crrc:$cc, condbrtarget:$dst) - 234 |
| {AliasPatternCond::K_Imm, uint32_t(79)}, |
| {AliasPatternCond::K_RegClass, PPC::CRRCRegClassID}, |
| // (BCCL 79, CR0, condbrtarget:$dst) - 236 |
| {AliasPatternCond::K_Imm, uint32_t(79)}, |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| // (BCCL 68, crrc:$cc, condbrtarget:$dst) - 238 |
| {AliasPatternCond::K_Imm, uint32_t(68)}, |
| {AliasPatternCond::K_RegClass, PPC::CRRCRegClassID}, |
| // (BCCL 68, CR0, condbrtarget:$dst) - 240 |
| {AliasPatternCond::K_Imm, uint32_t(68)}, |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| // (BCCL 70, crrc:$cc, condbrtarget:$dst) - 242 |
| {AliasPatternCond::K_Imm, uint32_t(70)}, |
| {AliasPatternCond::K_RegClass, PPC::CRRCRegClassID}, |
| // (BCCL 70, CR0, condbrtarget:$dst) - 244 |
| {AliasPatternCond::K_Imm, uint32_t(70)}, |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| // (BCCL 71, crrc:$cc, condbrtarget:$dst) - 246 |
| {AliasPatternCond::K_Imm, uint32_t(71)}, |
| {AliasPatternCond::K_RegClass, PPC::CRRCRegClassID}, |
| // (BCCL 71, CR0, condbrtarget:$dst) - 248 |
| {AliasPatternCond::K_Imm, uint32_t(71)}, |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| // (BCCLA 12, crrc:$cc, abscondbrtarget:$dst) - 250 |
| {AliasPatternCond::K_Imm, uint32_t(12)}, |
| {AliasPatternCond::K_RegClass, PPC::CRRCRegClassID}, |
| // (BCCLA 12, CR0, abscondbrtarget:$dst) - 252 |
| {AliasPatternCond::K_Imm, uint32_t(12)}, |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| // (BCCLA 14, crrc:$cc, abscondbrtarget:$dst) - 254 |
| {AliasPatternCond::K_Imm, uint32_t(14)}, |
| {AliasPatternCond::K_RegClass, PPC::CRRCRegClassID}, |
| // (BCCLA 14, CR0, abscondbrtarget:$dst) - 256 |
| {AliasPatternCond::K_Imm, uint32_t(14)}, |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| // (BCCLA 15, crrc:$cc, abscondbrtarget:$dst) - 258 |
| {AliasPatternCond::K_Imm, uint32_t(15)}, |
| {AliasPatternCond::K_RegClass, PPC::CRRCRegClassID}, |
| // (BCCLA 15, CR0, abscondbrtarget:$dst) - 260 |
| {AliasPatternCond::K_Imm, uint32_t(15)}, |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| // (BCCLA 44, crrc:$cc, abscondbrtarget:$dst) - 262 |
| {AliasPatternCond::K_Imm, uint32_t(44)}, |
| {AliasPatternCond::K_RegClass, PPC::CRRCRegClassID}, |
| // (BCCLA 44, CR0, abscondbrtarget:$dst) - 264 |
| {AliasPatternCond::K_Imm, uint32_t(44)}, |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| // (BCCLA 46, crrc:$cc, abscondbrtarget:$dst) - 266 |
| {AliasPatternCond::K_Imm, uint32_t(46)}, |
| {AliasPatternCond::K_RegClass, PPC::CRRCRegClassID}, |
| // (BCCLA 46, CR0, abscondbrtarget:$dst) - 268 |
| {AliasPatternCond::K_Imm, uint32_t(46)}, |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| // (BCCLA 47, crrc:$cc, abscondbrtarget:$dst) - 270 |
| {AliasPatternCond::K_Imm, uint32_t(47)}, |
| {AliasPatternCond::K_RegClass, PPC::CRRCRegClassID}, |
| // (BCCLA 47, CR0, abscondbrtarget:$dst) - 272 |
| {AliasPatternCond::K_Imm, uint32_t(47)}, |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| // (BCCLA 76, crrc:$cc, abscondbrtarget:$dst) - 274 |
| {AliasPatternCond::K_Imm, uint32_t(76)}, |
| {AliasPatternCond::K_RegClass, PPC::CRRCRegClassID}, |
| // (BCCLA 76, CR0, abscondbrtarget:$dst) - 276 |
| {AliasPatternCond::K_Imm, uint32_t(76)}, |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| // (BCCLA 78, crrc:$cc, abscondbrtarget:$dst) - 278 |
| {AliasPatternCond::K_Imm, uint32_t(78)}, |
| {AliasPatternCond::K_RegClass, PPC::CRRCRegClassID}, |
| // (BCCLA 78, CR0, abscondbrtarget:$dst) - 280 |
| {AliasPatternCond::K_Imm, uint32_t(78)}, |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| // (BCCLA 79, crrc:$cc, abscondbrtarget:$dst) - 282 |
| {AliasPatternCond::K_Imm, uint32_t(79)}, |
| {AliasPatternCond::K_RegClass, PPC::CRRCRegClassID}, |
| // (BCCLA 79, CR0, abscondbrtarget:$dst) - 284 |
| {AliasPatternCond::K_Imm, uint32_t(79)}, |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| // (BCCLA 68, crrc:$cc, abscondbrtarget:$dst) - 286 |
| {AliasPatternCond::K_Imm, uint32_t(68)}, |
| {AliasPatternCond::K_RegClass, PPC::CRRCRegClassID}, |
| // (BCCLA 68, CR0, abscondbrtarget:$dst) - 288 |
| {AliasPatternCond::K_Imm, uint32_t(68)}, |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| // (BCCLA 70, crrc:$cc, abscondbrtarget:$dst) - 290 |
| {AliasPatternCond::K_Imm, uint32_t(70)}, |
| {AliasPatternCond::K_RegClass, PPC::CRRCRegClassID}, |
| // (BCCLA 70, CR0, abscondbrtarget:$dst) - 292 |
| {AliasPatternCond::K_Imm, uint32_t(70)}, |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| // (BCCLA 71, crrc:$cc, abscondbrtarget:$dst) - 294 |
| {AliasPatternCond::K_Imm, uint32_t(71)}, |
| {AliasPatternCond::K_RegClass, PPC::CRRCRegClassID}, |
| // (BCCLA 71, CR0, abscondbrtarget:$dst) - 296 |
| {AliasPatternCond::K_Imm, uint32_t(71)}, |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| // (BCCLR 12, crrc:$cc) - 298 |
| {AliasPatternCond::K_Imm, uint32_t(12)}, |
| {AliasPatternCond::K_RegClass, PPC::CRRCRegClassID}, |
| // (BCCLR 12, CR0) - 300 |
| {AliasPatternCond::K_Imm, uint32_t(12)}, |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| // (BCCLR 14, crrc:$cc) - 302 |
| {AliasPatternCond::K_Imm, uint32_t(14)}, |
| {AliasPatternCond::K_RegClass, PPC::CRRCRegClassID}, |
| // (BCCLR 14, CR0) - 304 |
| {AliasPatternCond::K_Imm, uint32_t(14)}, |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| // (BCCLR 15, crrc:$cc) - 306 |
| {AliasPatternCond::K_Imm, uint32_t(15)}, |
| {AliasPatternCond::K_RegClass, PPC::CRRCRegClassID}, |
| // (BCCLR 15, CR0) - 308 |
| {AliasPatternCond::K_Imm, uint32_t(15)}, |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| // (BCCLR 44, crrc:$cc) - 310 |
| {AliasPatternCond::K_Imm, uint32_t(44)}, |
| {AliasPatternCond::K_RegClass, PPC::CRRCRegClassID}, |
| // (BCCLR 44, CR0) - 312 |
| {AliasPatternCond::K_Imm, uint32_t(44)}, |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| // (BCCLR 46, crrc:$cc) - 314 |
| {AliasPatternCond::K_Imm, uint32_t(46)}, |
| {AliasPatternCond::K_RegClass, PPC::CRRCRegClassID}, |
| // (BCCLR 46, CR0) - 316 |
| {AliasPatternCond::K_Imm, uint32_t(46)}, |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| // (BCCLR 47, crrc:$cc) - 318 |
| {AliasPatternCond::K_Imm, uint32_t(47)}, |
| {AliasPatternCond::K_RegClass, PPC::CRRCRegClassID}, |
| // (BCCLR 47, CR0) - 320 |
| {AliasPatternCond::K_Imm, uint32_t(47)}, |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| // (BCCLR 76, crrc:$cc) - 322 |
| {AliasPatternCond::K_Imm, uint32_t(76)}, |
| {AliasPatternCond::K_RegClass, PPC::CRRCRegClassID}, |
| // (BCCLR 76, CR0) - 324 |
| {AliasPatternCond::K_Imm, uint32_t(76)}, |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| // (BCCLR 78, crrc:$cc) - 326 |
| {AliasPatternCond::K_Imm, uint32_t(78)}, |
| {AliasPatternCond::K_RegClass, PPC::CRRCRegClassID}, |
| // (BCCLR 78, CR0) - 328 |
| {AliasPatternCond::K_Imm, uint32_t(78)}, |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| // (BCCLR 79, crrc:$cc) - 330 |
| {AliasPatternCond::K_Imm, uint32_t(79)}, |
| {AliasPatternCond::K_RegClass, PPC::CRRCRegClassID}, |
| // (BCCLR 79, CR0) - 332 |
| {AliasPatternCond::K_Imm, uint32_t(79)}, |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| // (BCCLR 68, crrc:$cc) - 334 |
| {AliasPatternCond::K_Imm, uint32_t(68)}, |
| {AliasPatternCond::K_RegClass, PPC::CRRCRegClassID}, |
| // (BCCLR 68, CR0) - 336 |
| {AliasPatternCond::K_Imm, uint32_t(68)}, |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| // (BCCLR 70, crrc:$cc) - 338 |
| {AliasPatternCond::K_Imm, uint32_t(70)}, |
| {AliasPatternCond::K_RegClass, PPC::CRRCRegClassID}, |
| // (BCCLR 70, CR0) - 340 |
| {AliasPatternCond::K_Imm, uint32_t(70)}, |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| // (BCCLR 71, crrc:$cc) - 342 |
| {AliasPatternCond::K_Imm, uint32_t(71)}, |
| {AliasPatternCond::K_RegClass, PPC::CRRCRegClassID}, |
| // (BCCLR 71, CR0) - 344 |
| {AliasPatternCond::K_Imm, uint32_t(71)}, |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| // (BCCLRL 12, crrc:$cc) - 346 |
| {AliasPatternCond::K_Imm, uint32_t(12)}, |
| {AliasPatternCond::K_RegClass, PPC::CRRCRegClassID}, |
| // (BCCLRL 12, CR0) - 348 |
| {AliasPatternCond::K_Imm, uint32_t(12)}, |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| // (BCCLRL 14, crrc:$cc) - 350 |
| {AliasPatternCond::K_Imm, uint32_t(14)}, |
| {AliasPatternCond::K_RegClass, PPC::CRRCRegClassID}, |
| // (BCCLRL 14, CR0) - 352 |
| {AliasPatternCond::K_Imm, uint32_t(14)}, |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| // (BCCLRL 15, crrc:$cc) - 354 |
| {AliasPatternCond::K_Imm, uint32_t(15)}, |
| {AliasPatternCond::K_RegClass, PPC::CRRCRegClassID}, |
| // (BCCLRL 15, CR0) - 356 |
| {AliasPatternCond::K_Imm, uint32_t(15)}, |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| // (BCCLRL 44, crrc:$cc) - 358 |
| {AliasPatternCond::K_Imm, uint32_t(44)}, |
| {AliasPatternCond::K_RegClass, PPC::CRRCRegClassID}, |
| // (BCCLRL 44, CR0) - 360 |
| {AliasPatternCond::K_Imm, uint32_t(44)}, |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| // (BCCLRL 46, crrc:$cc) - 362 |
| {AliasPatternCond::K_Imm, uint32_t(46)}, |
| {AliasPatternCond::K_RegClass, PPC::CRRCRegClassID}, |
| // (BCCLRL 46, CR0) - 364 |
| {AliasPatternCond::K_Imm, uint32_t(46)}, |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| // (BCCLRL 47, crrc:$cc) - 366 |
| {AliasPatternCond::K_Imm, uint32_t(47)}, |
| {AliasPatternCond::K_RegClass, PPC::CRRCRegClassID}, |
| // (BCCLRL 47, CR0) - 368 |
| {AliasPatternCond::K_Imm, uint32_t(47)}, |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| // (BCCLRL 76, crrc:$cc) - 370 |
| {AliasPatternCond::K_Imm, uint32_t(76)}, |
| {AliasPatternCond::K_RegClass, PPC::CRRCRegClassID}, |
| // (BCCLRL 76, CR0) - 372 |
| {AliasPatternCond::K_Imm, uint32_t(76)}, |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| // (BCCLRL 78, crrc:$cc) - 374 |
| {AliasPatternCond::K_Imm, uint32_t(78)}, |
| {AliasPatternCond::K_RegClass, PPC::CRRCRegClassID}, |
| // (BCCLRL 78, CR0) - 376 |
| {AliasPatternCond::K_Imm, uint32_t(78)}, |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| // (BCCLRL 79, crrc:$cc) - 378 |
| {AliasPatternCond::K_Imm, uint32_t(79)}, |
| {AliasPatternCond::K_RegClass, PPC::CRRCRegClassID}, |
| // (BCCLRL 79, CR0) - 380 |
| {AliasPatternCond::K_Imm, uint32_t(79)}, |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| // (BCCLRL 68, crrc:$cc) - 382 |
| {AliasPatternCond::K_Imm, uint32_t(68)}, |
| {AliasPatternCond::K_RegClass, PPC::CRRCRegClassID}, |
| // (BCCLRL 68, CR0) - 384 |
| {AliasPatternCond::K_Imm, uint32_t(68)}, |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| // (BCCLRL 70, crrc:$cc) - 386 |
| {AliasPatternCond::K_Imm, uint32_t(70)}, |
| {AliasPatternCond::K_RegClass, PPC::CRRCRegClassID}, |
| // (BCCLRL 70, CR0) - 388 |
| {AliasPatternCond::K_Imm, uint32_t(70)}, |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| // (BCCLRL 71, crrc:$cc) - 390 |
| {AliasPatternCond::K_Imm, uint32_t(71)}, |
| {AliasPatternCond::K_RegClass, PPC::CRRCRegClassID}, |
| // (BCCLRL 71, CR0) - 392 |
| {AliasPatternCond::K_Imm, uint32_t(71)}, |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| // (CMPD CR0, g8rc:$rA, g8rc:$rB) - 394 |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| // (CMPDI CR0, g8rc:$rA, s16imm64:$imm) - 397 |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| // (CMPLD CR0, g8rc:$rA, g8rc:$rB) - 399 |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| // (CMPLDI CR0, g8rc:$rA, u16imm64:$imm) - 402 |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| // (CMPLW CR0, gprc:$rA, gprc:$rB) - 404 |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| // (CMPLWI CR0, gprc:$rA, u16imm:$imm) - 407 |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| // (CMPW CR0, gprc:$rA, gprc:$rB) - 409 |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| // (CMPWI CR0, gprc:$rA, s16imm:$imm) - 412 |
| {AliasPatternCond::K_Reg, PPC::CR0}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| // (CNTLZW gprc:$rA, gprc:$rS) - 414 |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| // (CNTLZW8 g8rc:$rA, g8rc:$rS) - 416 |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| // (CNTLZW8_rec g8rc:$rA, g8rc:$rS) - 418 |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| // (CNTLZW_rec gprc:$rA, gprc:$rS) - 420 |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| // (CP_PASTE_rec gprc:$RA, gprc:$RB, 1) - 422 |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| // (CREQV crbitrc:$bx, crbitrc:$bx, crbitrc:$bx) - 425 |
| {AliasPatternCond::K_RegClass, PPC::CRBITRCRegClassID}, |
| {AliasPatternCond::K_TiedReg, 0}, |
| {AliasPatternCond::K_TiedReg, 0}, |
| // (CRNOR crbitrc:$bx, crbitrc:$by, crbitrc:$by) - 428 |
| {AliasPatternCond::K_RegClass, PPC::CRBITRCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::CRBITRCRegClassID}, |
| {AliasPatternCond::K_TiedReg, 1}, |
| // (CROR crbitrc:$bx, crbitrc:$by, crbitrc:$by) - 431 |
| {AliasPatternCond::K_RegClass, PPC::CRBITRCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::CRBITRCRegClassID}, |
| {AliasPatternCond::K_TiedReg, 1}, |
| // (CRXOR crbitrc:$bx, crbitrc:$bx, crbitrc:$bx) - 434 |
| {AliasPatternCond::K_RegClass, PPC::CRBITRCRegClassID}, |
| {AliasPatternCond::K_TiedReg, 0}, |
| {AliasPatternCond::K_TiedReg, 0}, |
| // (ISEL gprc:$rT, gprc_nor0:$rA, gprc:$rB, CR0LT) - 437 |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::GPRC_NOR0RegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_Reg, PPC::CR0LT}, |
| // (ISEL gprc:$rT, gprc_nor0:$rA, gprc:$rB, CR0GT) - 441 |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::GPRC_NOR0RegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_Reg, PPC::CR0GT}, |
| // (ISEL gprc:$rT, gprc_nor0:$rA, gprc:$rB, CR0EQ) - 445 |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::GPRC_NOR0RegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_Reg, PPC::CR0EQ}, |
| // (ISEL8 g8rc:$rT, g8rc_nox0:$rA, g8rc:$rB, CR0LT) - 449 |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::G8RC_NOX0RegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| {AliasPatternCond::K_Reg, PPC::CR0LT}, |
| // (ISEL8 g8rc:$rT, g8rc_nox0:$rA, g8rc:$rB, CR0GT) - 453 |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::G8RC_NOX0RegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| {AliasPatternCond::K_Reg, PPC::CR0GT}, |
| // (ISEL8 g8rc:$rT, g8rc_nox0:$rA, g8rc:$rB, CR0EQ) - 457 |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::G8RC_NOX0RegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| {AliasPatternCond::K_Reg, PPC::CR0EQ}, |
| // (MBAR 0) - 461 |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (MFDCR gprc:$Rx, 128) - 462 |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(128)}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MFDCR gprc:$Rx, 129) - 467 |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(129)}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MFDCR gprc:$Rx, 130) - 472 |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(130)}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MFDCR gprc:$Rx, 131) - 477 |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(131)}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MFDCR gprc:$Rx, 132) - 482 |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(132)}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MFDCR gprc:$Rx, 133) - 487 |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(133)}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MFDCR gprc:$Rx, 134) - 492 |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(134)}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MFDCR gprc:$Rx, 135) - 497 |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(135)}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MFSPR gprc:$Rx, 1) - 502 |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| // (MFSPR gprc:$Rx, 3) - 504 |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(3)}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MFSPR gprc:$Rx, 4) - 509 |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(4)}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MFSPR gprc:$Rx, 5) - 514 |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(5)}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MFSPR gprc:$Rx, 8) - 519 |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(8)}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MFSPR gprc:$Rx, 9) - 524 |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(9)}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MFSPR gprc:$Rx, 13) - 529 |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(13)}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MFSPR gprc:$Rx, 17) - 534 |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(17)}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MFSPR gprc:$Rx, 18) - 539 |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(18)}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MFSPR gprc:$Rx, 19) - 544 |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(19)}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MFSPR gprc:$Rx, 22) - 549 |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(22)}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MFSPR gprc:$Rx, 25) - 554 |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(25)}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MFSPR gprc:$Rx, 26) - 559 |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(26)}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MFSPR gprc:$Rx, 27) - 564 |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(27)}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MFSPR gprc:$Rx, 28) - 569 |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(28)}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MFSPR gprc:$Rx, 29) - 574 |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(29)}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MFSPR gprc:$Rx, 48) - 579 |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(48)}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MFSPR gprc:$RT, 280) - 584 |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(280)}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MFSPR gprc:$RT, 287) - 589 |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(287)}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MFSPR gprc:$Rx, 512) - 594 |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(512)}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MFSPR gprc:$Rx, 536) - 599 |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(536)}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MFSPR gprc:$Rx, 537) - 604 |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(537)}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MFSPR gprc:$Rx, 528) - 609 |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(528)}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MFSPR gprc:$Rx, 529) - 614 |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(529)}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MFSPR gprc:$Rx, 538) - 619 |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(538)}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MFSPR gprc:$Rx, 539) - 624 |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(539)}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MFSPR gprc:$Rx, 530) - 629 |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(530)}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MFSPR gprc:$Rx, 531) - 634 |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(531)}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MFSPR gprc:$Rx, 540) - 639 |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(540)}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MFSPR gprc:$Rx, 541) - 644 |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(541)}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MFSPR gprc:$Rx, 532) - 649 |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(532)}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MFSPR gprc:$Rx, 533) - 654 |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(533)}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MFSPR gprc:$Rx, 542) - 659 |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(542)}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MFSPR gprc:$Rx, 543) - 664 |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(543)}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MFSPR gprc:$Rx, 534) - 669 |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(534)}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MFSPR gprc:$Rx, 535) - 674 |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(535)}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MFSPR gprc:$RT, 896) - 679 |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(896)}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MFSPR gprc:$Rx, 980) - 684 |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(980)}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MFSPR gprc:$Rx, 981) - 689 |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(981)}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MFSPR gprc:$Rx, 986) - 694 |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(986)}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MFSPR gprc:$Rx, 988) - 699 |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(988)}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MFSPR gprc:$Rx, 989) - 704 |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(989)}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MFSPR gprc:$Rx, 990) - 709 |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(990)}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MFSPR gprc:$Rx, 991) - 714 |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(991)}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MFSPR gprc:$Rx, 1018) - 719 |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(1018)}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MFSPR gprc:$Rx, 1019) - 724 |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(1019)}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MFSPR8 g8rc:$Rx, 1) - 729 |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| // (MFSPR8 g8rc:$Rx, 3) - 731 |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(3)}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MFSPR8 g8rc:$Rx, 4) - 736 |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(4)}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MFSPR8 g8rc:$Rx, 5) - 741 |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(5)}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MFSPR8 g8rc:$Rx, 8) - 746 |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(8)}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MFSPR8 g8rc:$Rx, 9) - 751 |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(9)}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MFSPR8 g8rc:$Rx, 13) - 756 |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(13)}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MFSPR8 g8rc:$Rx, 17) - 761 |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(17)}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MFSPR8 g8rc:$Rx, 18) - 766 |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(18)}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MFSPR8 g8rc:$Rx, 19) - 771 |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(19)}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MFSPR8 g8rc:$Rx, 22) - 776 |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(22)}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MFSPR8 g8rc:$Rx, 25) - 781 |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(25)}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MFSPR8 g8rc:$Rx, 26) - 786 |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(26)}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MFSPR8 g8rc:$Rx, 27) - 791 |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(27)}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MFSPR8 g8rc:$Rx, 28) - 796 |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(28)}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MFSPR8 g8rc:$Rx, 29) - 801 |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(29)}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MFSPR8 g8rc:$RT, 280) - 806 |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(280)}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MFSPR8 g8rc:$RT, 287) - 811 |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(287)}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MFSPR8 g8rc:$Rx, 512) - 816 |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(512)}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MFTB gprc:$Rx, 269) - 821 |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(269)}, |
| // (MFUDSCR gprc:$Rx) - 823 |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MFVRSAVE gprc:$rS) - 827 |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| // (MFVSRD g8rc:$rA, f8rc:$src) - 828 |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::F8RCRegClassID}, |
| // (MFVSRWZ gprc:$rA, f8rc:$src) - 830 |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::F8RCRegClassID}, |
| // (MTCRF 255, gprc:$rA) - 832 |
| {AliasPatternCond::K_Imm, uint32_t(255)}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| // (MTCRF8 255, g8rc:$rA) - 834 |
| {AliasPatternCond::K_Imm, uint32_t(255)}, |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| // (MTDCR gprc:$Rx, 128) - 836 |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(128)}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MTDCR gprc:$Rx, 129) - 841 |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(129)}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MTDCR gprc:$Rx, 130) - 846 |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(130)}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MTDCR gprc:$Rx, 131) - 851 |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(131)}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MTDCR gprc:$Rx, 132) - 856 |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(132)}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MTDCR gprc:$Rx, 133) - 861 |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(133)}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MTDCR gprc:$Rx, 134) - 866 |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(134)}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MTDCR gprc:$Rx, 135) - 871 |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(135)}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MTFSF i32imm:$FLM, f8rc:$FRB, 0, 0) - 876 |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, PPC::F8RCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (MTFSFI u3imm:$BF, u4imm:$U, 0) - 880 |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (MTFSFI_rec u3imm:$BF, u4imm:$U, 0) - 883 |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (MTFSF_rec i32imm:$FLM, f8rc:$FRB, 0, 0) - 886 |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, PPC::F8RCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (MTMSR gprc:$RS, 0) - 890 |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MTMSRD gprc:$RS, 0) - 895 |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MTSPR 1, gprc:$Rx) - 900 |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| // (MTSPR 3, gprc:$Rx) - 902 |
| {AliasPatternCond::K_Imm, uint32_t(3)}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MTSPR 8, gprc:$Rx) - 907 |
| {AliasPatternCond::K_Imm, uint32_t(8)}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MTSPR 9, gprc:$Rx) - 912 |
| {AliasPatternCond::K_Imm, uint32_t(9)}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MTSPR 13, gprc:$Rx) - 917 |
| {AliasPatternCond::K_Imm, uint32_t(13)}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MTSPR 17, gprc:$Rx) - 922 |
| {AliasPatternCond::K_Imm, uint32_t(17)}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MTSPR 18, gprc:$Rx) - 927 |
| {AliasPatternCond::K_Imm, uint32_t(18)}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MTSPR 19, gprc:$Rx) - 932 |
| {AliasPatternCond::K_Imm, uint32_t(19)}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MTSPR 22, gprc:$Rx) - 937 |
| {AliasPatternCond::K_Imm, uint32_t(22)}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MTSPR 25, gprc:$Rx) - 942 |
| {AliasPatternCond::K_Imm, uint32_t(25)}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MTSPR 26, gprc:$Rx) - 947 |
| {AliasPatternCond::K_Imm, uint32_t(26)}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MTSPR 27, gprc:$Rx) - 952 |
| {AliasPatternCond::K_Imm, uint32_t(27)}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MTSPR 28, gprc:$Rx) - 957 |
| {AliasPatternCond::K_Imm, uint32_t(28)}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MTSPR 29, gprc:$Rx) - 962 |
| {AliasPatternCond::K_Imm, uint32_t(29)}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MTSPR 48, gprc:$Rx) - 967 |
| {AliasPatternCond::K_Imm, uint32_t(48)}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MTSPR 280, gprc:$RT) - 972 |
| {AliasPatternCond::K_Imm, uint32_t(280)}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MTSPR 284, gprc:$Rx) - 977 |
| {AliasPatternCond::K_Imm, uint32_t(284)}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MTSPR 285, gprc:$Rx) - 982 |
| {AliasPatternCond::K_Imm, uint32_t(285)}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MTSPR 512, gprc:$Rx) - 987 |
| {AliasPatternCond::K_Imm, uint32_t(512)}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MTSPR 536, gprc:$Rx) - 992 |
| {AliasPatternCond::K_Imm, uint32_t(536)}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MTSPR 537, gprc:$Rx) - 997 |
| {AliasPatternCond::K_Imm, uint32_t(537)}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MTSPR 528, gprc:$Rx) - 1002 |
| {AliasPatternCond::K_Imm, uint32_t(528)}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MTSPR 529, gprc:$Rx) - 1007 |
| {AliasPatternCond::K_Imm, uint32_t(529)}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MTSPR 538, gprc:$Rx) - 1012 |
| {AliasPatternCond::K_Imm, uint32_t(538)}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MTSPR 539, gprc:$Rx) - 1017 |
| {AliasPatternCond::K_Imm, uint32_t(539)}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MTSPR 530, gprc:$Rx) - 1022 |
| {AliasPatternCond::K_Imm, uint32_t(530)}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MTSPR 531, gprc:$Rx) - 1027 |
| {AliasPatternCond::K_Imm, uint32_t(531)}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MTSPR 540, gprc:$Rx) - 1032 |
| {AliasPatternCond::K_Imm, uint32_t(540)}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MTSPR 541, gprc:$Rx) - 1037 |
| {AliasPatternCond::K_Imm, uint32_t(541)}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MTSPR 532, gprc:$Rx) - 1042 |
| {AliasPatternCond::K_Imm, uint32_t(532)}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MTSPR 533, gprc:$Rx) - 1047 |
| {AliasPatternCond::K_Imm, uint32_t(533)}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MTSPR 542, gprc:$Rx) - 1052 |
| {AliasPatternCond::K_Imm, uint32_t(542)}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MTSPR 543, gprc:$Rx) - 1057 |
| {AliasPatternCond::K_Imm, uint32_t(543)}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MTSPR 534, gprc:$Rx) - 1062 |
| {AliasPatternCond::K_Imm, uint32_t(534)}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MTSPR 535, gprc:$Rx) - 1067 |
| {AliasPatternCond::K_Imm, uint32_t(535)}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MTSPR 896, gprc:$RT) - 1072 |
| {AliasPatternCond::K_Imm, uint32_t(896)}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MTSPR 980, gprc:$Rx) - 1077 |
| {AliasPatternCond::K_Imm, uint32_t(980)}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MTSPR 981, gprc:$Rx) - 1082 |
| {AliasPatternCond::K_Imm, uint32_t(981)}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MTSPR 986, gprc:$Rx) - 1087 |
| {AliasPatternCond::K_Imm, uint32_t(986)}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MTSPR 988, gprc:$Rx) - 1092 |
| {AliasPatternCond::K_Imm, uint32_t(988)}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MTSPR 989, gprc:$Rx) - 1097 |
| {AliasPatternCond::K_Imm, uint32_t(989)}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MTSPR 990, gprc:$Rx) - 1102 |
| {AliasPatternCond::K_Imm, uint32_t(990)}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MTSPR 991, gprc:$Rx) - 1107 |
| {AliasPatternCond::K_Imm, uint32_t(991)}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MTSPR 1018, gprc:$Rx) - 1112 |
| {AliasPatternCond::K_Imm, uint32_t(1018)}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MTSPR 1019, gprc:$Rx) - 1117 |
| {AliasPatternCond::K_Imm, uint32_t(1019)}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MTSPR8 1, g8rc:$Rx) - 1122 |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| // (MTSPR8 3, g8rc:$Rx) - 1124 |
| {AliasPatternCond::K_Imm, uint32_t(3)}, |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MTSPR8 8, g8rc:$Rx) - 1129 |
| {AliasPatternCond::K_Imm, uint32_t(8)}, |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MTSPR8 9, g8rc:$Rx) - 1134 |
| {AliasPatternCond::K_Imm, uint32_t(9)}, |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MTSPR8 13, g8rc:$Rx) - 1139 |
| {AliasPatternCond::K_Imm, uint32_t(13)}, |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MTSPR8 17, g8rc:$Rx) - 1144 |
| {AliasPatternCond::K_Imm, uint32_t(17)}, |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MTSPR8 18, g8rc:$Rx) - 1149 |
| {AliasPatternCond::K_Imm, uint32_t(18)}, |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MTSPR8 19, g8rc:$Rx) - 1154 |
| {AliasPatternCond::K_Imm, uint32_t(19)}, |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MTSPR8 22, g8rc:$Rx) - 1159 |
| {AliasPatternCond::K_Imm, uint32_t(22)}, |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MTSPR8 25, g8rc:$Rx) - 1164 |
| {AliasPatternCond::K_Imm, uint32_t(25)}, |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MTSPR8 26, g8rc:$Rx) - 1169 |
| {AliasPatternCond::K_Imm, uint32_t(26)}, |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MTSPR8 27, g8rc:$Rx) - 1174 |
| {AliasPatternCond::K_Imm, uint32_t(27)}, |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MTSPR8 28, g8rc:$Rx) - 1179 |
| {AliasPatternCond::K_Imm, uint32_t(28)}, |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MTSPR8 29, g8rc:$Rx) - 1184 |
| {AliasPatternCond::K_Imm, uint32_t(29)}, |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MTSPR8 280, g8rc:$RT) - 1189 |
| {AliasPatternCond::K_Imm, uint32_t(280)}, |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MTSPR8 284, g8rc:$Rx) - 1194 |
| {AliasPatternCond::K_Imm, uint32_t(284)}, |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MTSPR8 285, g8rc:$Rx) - 1199 |
| {AliasPatternCond::K_Imm, uint32_t(285)}, |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MTSPR8 512, g8rc:$Rx) - 1204 |
| {AliasPatternCond::K_Imm, uint32_t(512)}, |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MTUDSCR gprc:$Rx) - 1209 |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (MTVRSAVE gprc:$rS) - 1213 |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| // (MTVSRD f8rc:$dst, g8rc:$rA) - 1214 |
| {AliasPatternCond::K_RegClass, PPC::F8RCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| // (MTVSRWA f8rc:$dst, gprc:$rA) - 1216 |
| {AliasPatternCond::K_RegClass, PPC::F8RCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| // (MTVSRWZ f8rc:$dst, gprc:$rA) - 1218 |
| {AliasPatternCond::K_RegClass, PPC::F8RCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| // (NOR gprc:$rA, gprc:$rS, gprc:$rS) - 1220 |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_TiedReg, 1}, |
| // (NOR8 g8rc:$rA, g8rc:$rB, g8rc:$rB) - 1223 |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| {AliasPatternCond::K_TiedReg, 1}, |
| // (NOR8_rec g8rc:$rA, g8rc:$rB, g8rc:$rB) - 1226 |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| {AliasPatternCond::K_TiedReg, 1}, |
| // (NOR_rec gprc:$rA, gprc:$rS, gprc:$rS) - 1229 |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_TiedReg, 1}, |
| // (OR gprc:$rA, gprc:$rB, gprc:$rB) - 1232 |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_TiedReg, 1}, |
| // (OR8 g8rc:$rA, g8rc:$rB, g8rc:$rB) - 1235 |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| {AliasPatternCond::K_TiedReg, 1}, |
| // (OR8_rec g8rc:$rA, g8rc:$rB, g8rc:$rB) - 1238 |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| {AliasPatternCond::K_TiedReg, 1}, |
| // (ORI R0, R0, 0) - 1241 |
| {AliasPatternCond::K_Reg, PPC::R0}, |
| {AliasPatternCond::K_Reg, PPC::R0}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (ORI8 X0, X0, 0) - 1244 |
| {AliasPatternCond::K_Reg, PPC::X0}, |
| {AliasPatternCond::K_Reg, PPC::X0}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (OR_rec gprc:$rA, gprc:$rB, gprc:$rB) - 1247 |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_TiedReg, 1}, |
| // (RFEBB 1) - 1250 |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| // (RLDCL g8rc:$rA, g8rc:$rS, gprc:$rB, 0) - 1251 |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (RLDCL_rec g8rc:$rA, g8rc:$rS, gprc:$rB, 0) - 1255 |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (RLDICL g8rc:$rA, g8rc:$rS, u6imm:$n, 0) - 1259 |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (RLDICL g8rc:$rA, g8rc:$rS, 0, u6imm:$n) - 1263 |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (RLDICL_32_64 g8rc:$rA, gprc:$rS, u6imm:$n, 0) - 1266 |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (RLDICL_32_64 g8rc:$rA, gprc:$rS, 0, u6imm:$n) - 1270 |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (RLDICL_rec g8rc:$rA, g8rc:$rS, u6imm:$n, 0) - 1273 |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (RLDICL_rec g8rc:$rA, g8rc:$rS, 0, u6imm:$n) - 1277 |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (RLWINM gprc:$rA, gprc:$rS, u5imm:$n, 0, 31) - 1280 |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| // (RLWINM gprc:$rA, gprc:$rS, 0, u5imm:$n, 31) - 1285 |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| // (RLWINM8 g8rc:$rA, g8rc:$rS, u5imm:$n, 0, 31) - 1290 |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| // (RLWINM8 g8rc:$rA, g8rc:$rS, 0, u5imm:$n, 31) - 1295 |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| // (RLWINM8_rec g8rc:$rA, g8rc:$rS, u5imm:$n, 0, 31) - 1300 |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| // (RLWINM8_rec g8rc:$rA, g8rc:$rS, 0, u5imm:$n, 31) - 1305 |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| // (RLWINM_rec gprc:$rA, gprc:$rS, u5imm:$n, 0, 31) - 1310 |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| // (RLWINM_rec gprc:$rA, gprc:$rS, 0, u5imm:$n, 31) - 1315 |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| // (RLWNM gprc:$rA, gprc:$rS, gprc:$rB, 0, 31) - 1320 |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| // (RLWNM8 g8rc:$rA, g8rc:$rS, g8rc:$rB, 0, 31) - 1325 |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| // (RLWNM8_rec g8rc:$rA, g8rc:$rS, g8rc:$rB, 0, 31) - 1330 |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| // (RLWNM_rec gprc:$rA, gprc:$rS, gprc:$rB, 0, 31) - 1335 |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| // (SC 0) - 1340 |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (SUBF gprc:$rA, gprc:$rC, gprc:$rB) - 1341 |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| // (SUBF8 g8rc:$rA, g8rc:$rC, g8rc:$rB) - 1344 |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| // (SUBF8_rec g8rc:$rA, g8rc:$rC, g8rc:$rB) - 1347 |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| // (SUBFC gprc:$rA, gprc:$rC, gprc:$rB) - 1350 |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| // (SUBFC8 g8rc:$rA, g8rc:$rC, g8rc:$rB) - 1353 |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| // (SUBFC8_rec g8rc:$rA, g8rc:$rC, g8rc:$rB) - 1356 |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| // (SUBFC_rec gprc:$rA, gprc:$rC, gprc:$rB) - 1359 |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| // (SUBF_rec gprc:$rA, gprc:$rC, gprc:$rB) - 1362 |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| // (SYNC 0) - 1365 |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (SYNC 1) - 1366 |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| // (SYNC 2) - 1367 |
| {AliasPatternCond::K_Imm, uint32_t(2)}, |
| // (TD 16, g8rc:$rA, g8rc:$rB) - 1368 |
| {AliasPatternCond::K_Imm, uint32_t(16)}, |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| // (TD 4, g8rc:$rA, g8rc:$rB) - 1371 |
| {AliasPatternCond::K_Imm, uint32_t(4)}, |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| // (TD 8, g8rc:$rA, g8rc:$rB) - 1374 |
| {AliasPatternCond::K_Imm, uint32_t(8)}, |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| // (TD 24, g8rc:$rA, g8rc:$rB) - 1377 |
| {AliasPatternCond::K_Imm, uint32_t(24)}, |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| // (TD 2, g8rc:$rA, g8rc:$rB) - 1380 |
| {AliasPatternCond::K_Imm, uint32_t(2)}, |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| // (TD 1, g8rc:$rA, g8rc:$rB) - 1383 |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| // (TD 31, g8rc:$rA, g8rc:$rB) - 1386 |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| // (TDI 16, g8rc:$rA, s16imm:$imm) - 1389 |
| {AliasPatternCond::K_Imm, uint32_t(16)}, |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| // (TDI 4, g8rc:$rA, s16imm:$imm) - 1391 |
| {AliasPatternCond::K_Imm, uint32_t(4)}, |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| // (TDI 8, g8rc:$rA, s16imm:$imm) - 1393 |
| {AliasPatternCond::K_Imm, uint32_t(8)}, |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| // (TDI 24, g8rc:$rA, s16imm:$imm) - 1395 |
| {AliasPatternCond::K_Imm, uint32_t(24)}, |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| // (TDI 2, g8rc:$rA, s16imm:$imm) - 1397 |
| {AliasPatternCond::K_Imm, uint32_t(2)}, |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| // (TDI 1, g8rc:$rA, s16imm:$imm) - 1399 |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| // (TDI 31, g8rc:$rA, s16imm:$imm) - 1401 |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_RegClass, PPC::G8RCRegClassID}, |
| // (TEND 0) - 1403 |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (TEND 1) - 1404 |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| // (TLBIE R0, gprc:$RB) - 1405 |
| {AliasPatternCond::K_Reg, PPC::R0}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| // (TLBRE2 gprc:$RS, gprc:$A, 0) - 1407 |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (TLBRE2 gprc:$RS, gprc:$A, 1) - 1410 |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| // (TLBWE2 gprc:$RS, gprc:$A, 0) - 1413 |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (TLBWE2 gprc:$RS, gprc:$A, 1) - 1416 |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| // (TSR 0) - 1419 |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (TSR 1) - 1420 |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| // (TW 31, R0, R0) - 1421 |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_Reg, PPC::R0}, |
| {AliasPatternCond::K_Reg, PPC::R0}, |
| // (TW 16, gprc:$rA, gprc:$rB) - 1424 |
| {AliasPatternCond::K_Imm, uint32_t(16)}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| // (TW 4, gprc:$rA, gprc:$rB) - 1427 |
| {AliasPatternCond::K_Imm, uint32_t(4)}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| // (TW 8, gprc:$rA, gprc:$rB) - 1430 |
| {AliasPatternCond::K_Imm, uint32_t(8)}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| // (TW 24, gprc:$rA, gprc:$rB) - 1433 |
| {AliasPatternCond::K_Imm, uint32_t(24)}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| // (TW 2, gprc:$rA, gprc:$rB) - 1436 |
| {AliasPatternCond::K_Imm, uint32_t(2)}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| // (TW 1, gprc:$rA, gprc:$rB) - 1439 |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| // (TW 31, gprc:$rA, gprc:$rB) - 1442 |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| // (TWI 16, gprc:$rA, s16imm:$imm) - 1445 |
| {AliasPatternCond::K_Imm, uint32_t(16)}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| // (TWI 4, gprc:$rA, s16imm:$imm) - 1447 |
| {AliasPatternCond::K_Imm, uint32_t(4)}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| // (TWI 8, gprc:$rA, s16imm:$imm) - 1449 |
| {AliasPatternCond::K_Imm, uint32_t(8)}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| // (TWI 24, gprc:$rA, s16imm:$imm) - 1451 |
| {AliasPatternCond::K_Imm, uint32_t(24)}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| // (TWI 2, gprc:$rA, s16imm:$imm) - 1453 |
| {AliasPatternCond::K_Imm, uint32_t(2)}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| // (TWI 1, gprc:$rA, s16imm:$imm) - 1455 |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| // (TWI 31, gprc:$rA, s16imm:$imm) - 1457 |
| {AliasPatternCond::K_Imm, uint32_t(31)}, |
| {AliasPatternCond::K_RegClass, PPC::GPRCRegClassID}, |
| // (VNOR vrrc:$vD, vrrc:$vA, vrrc:$vA) - 1459 |
| {AliasPatternCond::K_RegClass, PPC::VRRCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::VRRCRegClassID}, |
| {AliasPatternCond::K_TiedReg, 1}, |
| // (VOR vrrc:$vD, vrrc:$vA, vrrc:$vA) - 1462 |
| {AliasPatternCond::K_RegClass, PPC::VRRCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::VRRCRegClassID}, |
| {AliasPatternCond::K_TiedReg, 1}, |
| // (WAIT 0) - 1465 |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (WAIT 1) - 1466 |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| // (WAIT 2) - 1467 |
| {AliasPatternCond::K_Imm, uint32_t(2)}, |
| // (XORI R0, R0, 0) - 1468 |
| {AliasPatternCond::K_Reg, PPC::R0}, |
| {AliasPatternCond::K_Reg, PPC::R0}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (XORI8 X0, X0, 0) - 1471 |
| {AliasPatternCond::K_Reg, PPC::X0}, |
| {AliasPatternCond::K_Reg, PPC::X0}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (XVCPSGNDP vsrc:$XT, vsrc:$XB, vsrc:$XB) - 1474 |
| {AliasPatternCond::K_RegClass, PPC::VSRCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::VSRCRegClassID}, |
| {AliasPatternCond::K_TiedReg, 1}, |
| // (XVCPSGNSP vsrc:$XT, vsrc:$XB, vsrc:$XB) - 1477 |
| {AliasPatternCond::K_RegClass, PPC::VSRCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::VSRCRegClassID}, |
| {AliasPatternCond::K_TiedReg, 1}, |
| // (XXPERMDI vsrc:$XT, vsrc:$XB, vsrc:$XB, 0) - 1480 |
| {AliasPatternCond::K_RegClass, PPC::VSRCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::VSRCRegClassID}, |
| {AliasPatternCond::K_TiedReg, 1}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (XXPERMDI vsrc:$XT, vsrc:$XB, vsrc:$XB, 3) - 1487 |
| {AliasPatternCond::K_RegClass, PPC::VSRCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::VSRCRegClassID}, |
| {AliasPatternCond::K_TiedReg, 1}, |
| {AliasPatternCond::K_Imm, uint32_t(3)}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (XXPERMDI vsrc:$XT, vsrc:$XA, vsrc:$XB, 0) - 1494 |
| {AliasPatternCond::K_RegClass, PPC::VSRCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::VSRCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::VSRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (XXPERMDI vsrc:$XT, vsrc:$XA, vsrc:$XB, 3) - 1498 |
| {AliasPatternCond::K_RegClass, PPC::VSRCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::VSRCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::VSRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(3)}, |
| // (XXPERMDI vsrc:$XT, vsrc:$XB, vsrc:$XB, 2) - 1502 |
| {AliasPatternCond::K_RegClass, PPC::VSRCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::VSRCRegClassID}, |
| {AliasPatternCond::K_TiedReg, 1}, |
| {AliasPatternCond::K_Imm, uint32_t(2)}, |
| // (XXPERMDIs vsrc:$XT, vsfrc:$XB, 0) - 1506 |
| {AliasPatternCond::K_RegClass, PPC::VSRCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::VSFRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (XXPERMDIs vsrc:$XT, vsfrc:$XB, 3) - 1512 |
| {AliasPatternCond::K_RegClass, PPC::VSRCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::VSFRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(3)}, |
| {AliasPatternCond::K_OrNegFeature, PPC::AIXOS}, |
| {AliasPatternCond::K_OrFeature, PPC::FeatureModernAIXAs}, |
| {AliasPatternCond::K_EndOrFeatures, 0}, |
| // (XXPERMDIs vsrc:$XT, vsfrc:$XB, 2) - 1518 |
| {AliasPatternCond::K_RegClass, PPC::VSRCRegClassID}, |
| {AliasPatternCond::K_RegClass, PPC::VSFRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(2)}, |
| // (gBC 12, crbitrc:$bi, condbrtarget:$dst) - 1521 |
| {AliasPatternCond::K_Imm, uint32_t(12)}, |
| {AliasPatternCond::K_RegClass, PPC::CRBITRCRegClassID}, |
| // (gBC 4, crbitrc:$bi, condbrtarget:$dst) - 1523 |
| {AliasPatternCond::K_Imm, uint32_t(4)}, |
| {AliasPatternCond::K_RegClass, PPC::CRBITRCRegClassID}, |
| // (gBC 14, crbitrc:$bi, condbrtarget:$dst) - 1525 |
| {AliasPatternCond::K_Imm, uint32_t(14)}, |
| {AliasPatternCond::K_RegClass, PPC::CRBITRCRegClassID}, |
| // (gBC 6, crbitrc:$bi, condbrtarget:$dst) - 1527 |
| {AliasPatternCond::K_Imm, uint32_t(6)}, |
| {AliasPatternCond::K_RegClass, PPC::CRBITRCRegClassID}, |
| // (gBC 15, crbitrc:$bi, condbrtarget:$dst) - 1529 |
| {AliasPatternCond::K_Imm, uint32_t(15)}, |
| {AliasPatternCond::K_RegClass, PPC::CRBITRCRegClassID}, |
| // (gBC 7, crbitrc:$bi, condbrtarget:$dst) - 1531 |
| {AliasPatternCond::K_Imm, uint32_t(7)}, |
| {AliasPatternCond::K_RegClass, PPC::CRBITRCRegClassID}, |
| // (gBC 8, crbitrc:$bi, condbrtarget:$dst) - 1533 |
| {AliasPatternCond::K_Imm, uint32_t(8)}, |
| {AliasPatternCond::K_RegClass, PPC::CRBITRCRegClassID}, |
| // (gBC 0, crbitrc:$bi, condbrtarget:$dst) - 1535 |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_RegClass, PPC::CRBITRCRegClassID}, |
| // (gBC 10, crbitrc:$bi, condbrtarget:$dst) - 1537 |
| {AliasPatternCond::K_Imm, uint32_t(10)}, |
| {AliasPatternCond::K_RegClass, PPC::CRBITRCRegClassID}, |
| // (gBC 2, crbitrc:$bi, condbrtarget:$dst) - 1539 |
| {AliasPatternCond::K_Imm, uint32_t(2)}, |
| {AliasPatternCond::K_RegClass, PPC::CRBITRCRegClassID}, |
| // (gBCA 12, crbitrc:$bi, abscondbrtarget:$dst) - 1541 |
| {AliasPatternCond::K_Imm, uint32_t(12)}, |
| {AliasPatternCond::K_RegClass, PPC::CRBITRCRegClassID}, |
| // (gBCA 4, crbitrc:$bi, abscondbrtarget:$dst) - 1543 |
| {AliasPatternCond::K_Imm, uint32_t(4)}, |
| {AliasPatternCond::K_RegClass, PPC::CRBITRCRegClassID}, |
| // (gBCA 14, crbitrc:$bi, abscondbrtarget:$dst) - 1545 |
| {AliasPatternCond::K_Imm, uint32_t(14)}, |
| {AliasPatternCond::K_RegClass, PPC::CRBITRCRegClassID}, |
| // (gBCA 6, crbitrc:$bi, abscondbrtarget:$dst) - 1547 |
| {AliasPatternCond::K_Imm, uint32_t(6)}, |
| {AliasPatternCond::K_RegClass, PPC::CRBITRCRegClassID}, |
| // (gBCA 15, crbitrc:$bi, abscondbrtarget:$dst) - 1549 |
| {AliasPatternCond::K_Imm, uint32_t(15)}, |
| {AliasPatternCond::K_RegClass, PPC::CRBITRCRegClassID}, |
| // (gBCA 7, crbitrc:$bi, abscondbrtarget:$dst) - 1551 |
| {AliasPatternCond::K_Imm, uint32_t(7)}, |
| {AliasPatternCond::K_RegClass, PPC::CRBITRCRegClassID}, |
| // (gBCA 8, crbitrc:$bi, abscondbrtarget:$dst) - 1553 |
| {AliasPatternCond::K_Imm, uint32_t(8)}, |
| {AliasPatternCond::K_RegClass, PPC::CRBITRCRegClassID}, |
| // (gBCA 0, crbitrc:$bi, abscondbrtarget:$dst) - 1555 |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_RegClass, PPC::CRBITRCRegClassID}, |
| // (gBCA 10, crbitrc:$bi, abscondbrtarget:$dst) - 1557 |
| {AliasPatternCond::K_Imm, uint32_t(10)}, |
| {AliasPatternCond::K_RegClass, PPC::CRBITRCRegClassID}, |
| // (gBCA 2, crbitrc:$bi, abscondbrtarget:$dst) - 1559 |
| {AliasPatternCond::K_Imm, uint32_t(2)}, |
| {AliasPatternCond::K_RegClass, PPC::CRBITRCRegClassID}, |
| // (gBCAat u5imm:$bo, 3, crbitrc:$bi, condbrtarget:$dst) - 1561 |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(3)}, |
| {AliasPatternCond::K_RegClass, PPC::CRBITRCRegClassID}, |
| // (gBCAat u5imm:$bo, 2, crbitrc:$bi, condbrtarget:$dst) - 1564 |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(2)}, |
| {AliasPatternCond::K_RegClass, PPC::CRBITRCRegClassID}, |
| // (gBCCTR u5imm:$bo, crbitrc:$bi, 0) - 1567 |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, PPC::CRBITRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (gBCCTR 12, crbitrc:$bi, 0) - 1570 |
| {AliasPatternCond::K_Imm, uint32_t(12)}, |
| {AliasPatternCond::K_RegClass, PPC::CRBITRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (gBCCTR 4, crbitrc:$bi, 0) - 1573 |
| {AliasPatternCond::K_Imm, uint32_t(4)}, |
| {AliasPatternCond::K_RegClass, PPC::CRBITRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (gBCCTR 14, crbitrc:$bi, 0) - 1576 |
| {AliasPatternCond::K_Imm, uint32_t(14)}, |
| {AliasPatternCond::K_RegClass, PPC::CRBITRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (gBCCTR 6, crbitrc:$bi, 0) - 1579 |
| {AliasPatternCond::K_Imm, uint32_t(6)}, |
| {AliasPatternCond::K_RegClass, PPC::CRBITRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (gBCCTR 15, crbitrc:$bi, 0) - 1582 |
| {AliasPatternCond::K_Imm, uint32_t(15)}, |
| {AliasPatternCond::K_RegClass, PPC::CRBITRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (gBCCTR 7, crbitrc:$bi, 0) - 1585 |
| {AliasPatternCond::K_Imm, uint32_t(7)}, |
| {AliasPatternCond::K_RegClass, PPC::CRBITRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (gBCCTRL u5imm:$bo, crbitrc:$bi, 0) - 1588 |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, PPC::CRBITRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (gBCCTRL 12, crbitrc:$bi, 0) - 1591 |
| {AliasPatternCond::K_Imm, uint32_t(12)}, |
| {AliasPatternCond::K_RegClass, PPC::CRBITRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (gBCCTRL 4, crbitrc:$bi, 0) - 1594 |
| {AliasPatternCond::K_Imm, uint32_t(4)}, |
| {AliasPatternCond::K_RegClass, PPC::CRBITRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (gBCCTRL 14, crbitrc:$bi, 0) - 1597 |
| {AliasPatternCond::K_Imm, uint32_t(14)}, |
| {AliasPatternCond::K_RegClass, PPC::CRBITRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (gBCCTRL 6, crbitrc:$bi, 0) - 1600 |
| {AliasPatternCond::K_Imm, uint32_t(6)}, |
| {AliasPatternCond::K_RegClass, PPC::CRBITRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (gBCCTRL 15, crbitrc:$bi, 0) - 1603 |
| {AliasPatternCond::K_Imm, uint32_t(15)}, |
| {AliasPatternCond::K_RegClass, PPC::CRBITRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (gBCCTRL 7, crbitrc:$bi, 0) - 1606 |
| {AliasPatternCond::K_Imm, uint32_t(7)}, |
| {AliasPatternCond::K_RegClass, PPC::CRBITRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (gBCL 12, crbitrc:$bi, condbrtarget:$dst) - 1609 |
| {AliasPatternCond::K_Imm, uint32_t(12)}, |
| {AliasPatternCond::K_RegClass, PPC::CRBITRCRegClassID}, |
| // (gBCL 4, crbitrc:$bi, condbrtarget:$dst) - 1611 |
| {AliasPatternCond::K_Imm, uint32_t(4)}, |
| {AliasPatternCond::K_RegClass, PPC::CRBITRCRegClassID}, |
| // (gBCL 14, crbitrc:$bi, condbrtarget:$dst) - 1613 |
| {AliasPatternCond::K_Imm, uint32_t(14)}, |
| {AliasPatternCond::K_RegClass, PPC::CRBITRCRegClassID}, |
| // (gBCL 6, crbitrc:$bi, condbrtarget:$dst) - 1615 |
| {AliasPatternCond::K_Imm, uint32_t(6)}, |
| {AliasPatternCond::K_RegClass, PPC::CRBITRCRegClassID}, |
| // (gBCL 15, crbitrc:$bi, condbrtarget:$dst) - 1617 |
| {AliasPatternCond::K_Imm, uint32_t(15)}, |
| {AliasPatternCond::K_RegClass, PPC::CRBITRCRegClassID}, |
| // (gBCL 7, crbitrc:$bi, condbrtarget:$dst) - 1619 |
| {AliasPatternCond::K_Imm, uint32_t(7)}, |
| {AliasPatternCond::K_RegClass, PPC::CRBITRCRegClassID}, |
| // (gBCL 8, crbitrc:$bi, condbrtarget:$dst) - 1621 |
| {AliasPatternCond::K_Imm, uint32_t(8)}, |
| {AliasPatternCond::K_RegClass, PPC::CRBITRCRegClassID}, |
| // (gBCL 0, crbitrc:$bi, condbrtarget:$dst) - 1623 |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_RegClass, PPC::CRBITRCRegClassID}, |
| // (gBCL 10, crbitrc:$bi, condbrtarget:$dst) - 1625 |
| {AliasPatternCond::K_Imm, uint32_t(10)}, |
| {AliasPatternCond::K_RegClass, PPC::CRBITRCRegClassID}, |
| // (gBCL 2, crbitrc:$bi, condbrtarget:$dst) - 1627 |
| {AliasPatternCond::K_Imm, uint32_t(2)}, |
| {AliasPatternCond::K_RegClass, PPC::CRBITRCRegClassID}, |
| // (gBCLA 12, crbitrc:$bi, abscondbrtarget:$dst) - 1629 |
| {AliasPatternCond::K_Imm, uint32_t(12)}, |
| {AliasPatternCond::K_RegClass, PPC::CRBITRCRegClassID}, |
| // (gBCLA 4, crbitrc:$bi, abscondbrtarget:$dst) - 1631 |
| {AliasPatternCond::K_Imm, uint32_t(4)}, |
| {AliasPatternCond::K_RegClass, PPC::CRBITRCRegClassID}, |
| // (gBCLA 14, crbitrc:$bi, abscondbrtarget:$dst) - 1633 |
| {AliasPatternCond::K_Imm, uint32_t(14)}, |
| {AliasPatternCond::K_RegClass, PPC::CRBITRCRegClassID}, |
| // (gBCLA 6, crbitrc:$bi, abscondbrtarget:$dst) - 1635 |
| {AliasPatternCond::K_Imm, uint32_t(6)}, |
| {AliasPatternCond::K_RegClass, PPC::CRBITRCRegClassID}, |
| // (gBCLA 15, crbitrc:$bi, abscondbrtarget:$dst) - 1637 |
| {AliasPatternCond::K_Imm, uint32_t(15)}, |
| {AliasPatternCond::K_RegClass, PPC::CRBITRCRegClassID}, |
| // (gBCLA 7, crbitrc:$bi, abscondbrtarget:$dst) - 1639 |
| {AliasPatternCond::K_Imm, uint32_t(7)}, |
| {AliasPatternCond::K_RegClass, PPC::CRBITRCRegClassID}, |
| // (gBCLA 8, crbitrc:$bi, abscondbrtarget:$dst) - 1641 |
| {AliasPatternCond::K_Imm, uint32_t(8)}, |
| {AliasPatternCond::K_RegClass, PPC::CRBITRCRegClassID}, |
| // (gBCLA 0, crbitrc:$bi, abscondbrtarget:$dst) - 1643 |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_RegClass, PPC::CRBITRCRegClassID}, |
| // (gBCLA 10, crbitrc:$bi, abscondbrtarget:$dst) - 1645 |
| {AliasPatternCond::K_Imm, uint32_t(10)}, |
| {AliasPatternCond::K_RegClass, PPC::CRBITRCRegClassID}, |
| // (gBCLA 2, crbitrc:$bi, abscondbrtarget:$dst) - 1647 |
| {AliasPatternCond::K_Imm, uint32_t(2)}, |
| {AliasPatternCond::K_RegClass, PPC::CRBITRCRegClassID}, |
| // (gBCLAat u5imm:$bo, 3, crbitrc:$bi, condbrtarget:$dst) - 1649 |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(3)}, |
| {AliasPatternCond::K_RegClass, PPC::CRBITRCRegClassID}, |
| // (gBCLAat u5imm:$bo, 2, crbitrc:$bi, condbrtarget:$dst) - 1652 |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(2)}, |
| {AliasPatternCond::K_RegClass, PPC::CRBITRCRegClassID}, |
| // (gBCLR u5imm:$bo, crbitrc:$bi, 0) - 1655 |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, PPC::CRBITRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (gBCLR 12, crbitrc:$bi, 0) - 1658 |
| {AliasPatternCond::K_Imm, uint32_t(12)}, |
| {AliasPatternCond::K_RegClass, PPC::CRBITRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (gBCLR 4, crbitrc:$bi, 0) - 1661 |
| {AliasPatternCond::K_Imm, uint32_t(4)}, |
| {AliasPatternCond::K_RegClass, PPC::CRBITRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (gBCLR 14, crbitrc:$bi, 0) - 1664 |
| {AliasPatternCond::K_Imm, uint32_t(14)}, |
| {AliasPatternCond::K_RegClass, PPC::CRBITRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (gBCLR 6, crbitrc:$bi, 0) - 1667 |
| {AliasPatternCond::K_Imm, uint32_t(6)}, |
| {AliasPatternCond::K_RegClass, PPC::CRBITRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (gBCLR 15, crbitrc:$bi, 0) - 1670 |
| {AliasPatternCond::K_Imm, uint32_t(15)}, |
| {AliasPatternCond::K_RegClass, PPC::CRBITRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (gBCLR 7, crbitrc:$bi, 0) - 1673 |
| {AliasPatternCond::K_Imm, uint32_t(7)}, |
| {AliasPatternCond::K_RegClass, PPC::CRBITRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (gBCLR 8, crbitrc:$bi, 0) - 1676 |
| {AliasPatternCond::K_Imm, uint32_t(8)}, |
| {AliasPatternCond::K_RegClass, PPC::CRBITRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (gBCLR 0, crbitrc:$bi, 0) - 1679 |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_RegClass, PPC::CRBITRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (gBCLR 10, crbitrc:$bi, 0) - 1682 |
| {AliasPatternCond::K_Imm, uint32_t(10)}, |
| {AliasPatternCond::K_RegClass, PPC::CRBITRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (gBCLR 2, crbitrc:$bi, 0) - 1685 |
| {AliasPatternCond::K_Imm, uint32_t(2)}, |
| {AliasPatternCond::K_RegClass, PPC::CRBITRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (gBCLRL u5imm:$bo, crbitrc:$bi, 0) - 1688 |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, PPC::CRBITRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (gBCLRL 12, crbitrc:$bi, 0) - 1691 |
| {AliasPatternCond::K_Imm, uint32_t(12)}, |
| {AliasPatternCond::K_RegClass, PPC::CRBITRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (gBCLRL 4, crbitrc:$bi, 0) - 1694 |
| {AliasPatternCond::K_Imm, uint32_t(4)}, |
| {AliasPatternCond::K_RegClass, PPC::CRBITRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (gBCLRL 14, crbitrc:$bi, 0) - 1697 |
| {AliasPatternCond::K_Imm, uint32_t(14)}, |
| {AliasPatternCond::K_RegClass, PPC::CRBITRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (gBCLRL 6, crbitrc:$bi, 0) - 1700 |
| {AliasPatternCond::K_Imm, uint32_t(6)}, |
| {AliasPatternCond::K_RegClass, PPC::CRBITRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (gBCLRL 15, crbitrc:$bi, 0) - 1703 |
| {AliasPatternCond::K_Imm, uint32_t(15)}, |
| {AliasPatternCond::K_RegClass, PPC::CRBITRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (gBCLRL 7, crbitrc:$bi, 0) - 1706 |
| {AliasPatternCond::K_Imm, uint32_t(7)}, |
| {AliasPatternCond::K_RegClass, PPC::CRBITRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (gBCLRL 8, crbitrc:$bi, 0) - 1709 |
| {AliasPatternCond::K_Imm, uint32_t(8)}, |
| {AliasPatternCond::K_RegClass, PPC::CRBITRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (gBCLRL 0, crbitrc:$bi, 0) - 1712 |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_RegClass, PPC::CRBITRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (gBCLRL 10, crbitrc:$bi, 0) - 1715 |
| {AliasPatternCond::K_Imm, uint32_t(10)}, |
| {AliasPatternCond::K_RegClass, PPC::CRBITRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (gBCLRL 2, crbitrc:$bi, 0) - 1718 |
| {AliasPatternCond::K_Imm, uint32_t(2)}, |
| {AliasPatternCond::K_RegClass, PPC::CRBITRCRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (gBCLat u5imm:$bo, 3, crbitrc:$bi, condbrtarget:$dst) - 1721 |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(3)}, |
| {AliasPatternCond::K_RegClass, PPC::CRBITRCRegClassID}, |
| // (gBCLat u5imm:$bo, 2, crbitrc:$bi, condbrtarget:$dst) - 1724 |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(2)}, |
| {AliasPatternCond::K_RegClass, PPC::CRBITRCRegClassID}, |
| // (gBCat u5imm:$bo, 3, crbitrc:$bi, condbrtarget:$dst) - 1727 |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(3)}, |
| {AliasPatternCond::K_RegClass, PPC::CRBITRCRegClassID}, |
| // (gBCat u5imm:$bo, 2, crbitrc:$bi, condbrtarget:$dst) - 1730 |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Imm, uint32_t(2)}, |
| {AliasPatternCond::K_RegClass, PPC::CRBITRCRegClassID}, |
| }; |
| |
| static const char AsmStrings[] = |
| /* 0 */ "li $\x01, $\xFF\x03\x01\0" |
| /* 12 */ "lis $\x01, $\xFF\x03\x01\0" |
| /* 25 */ "lnia $\x01\0" |
| /* 33 */ "blt $\x02, $\xFF\x03\x02\0" |
| /* 46 */ "blt $\xFF\x03\x02\0" |
| /* 55 */ "blt- $\x02, $\xFF\x03\x02\0" |
| /* 69 */ "blt- $\xFF\x03\x02\0" |
| /* 79 */ "blt+ $\x02, $\xFF\x03\x02\0" |
| /* 93 */ "blt+ $\xFF\x03\x02\0" |
| /* 103 */ "bgt $\x02, $\xFF\x03\x02\0" |
| /* 116 */ "bgt $\xFF\x03\x02\0" |
| /* 125 */ "bgt- $\x02, $\xFF\x03\x02\0" |
| /* 139 */ "bgt- $\xFF\x03\x02\0" |
| /* 149 */ "bgt+ $\x02, $\xFF\x03\x02\0" |
| /* 163 */ "bgt+ $\xFF\x03\x02\0" |
| /* 173 */ "beq $\x02, $\xFF\x03\x02\0" |
| /* 186 */ "beq $\xFF\x03\x02\0" |
| /* 195 */ "beq- $\x02, $\xFF\x03\x02\0" |
| /* 209 */ "beq- $\xFF\x03\x02\0" |
| /* 219 */ "beq+ $\x02, $\xFF\x03\x02\0" |
| /* 233 */ "beq+ $\xFF\x03\x02\0" |
| /* 243 */ "bne $\x02, $\xFF\x03\x02\0" |
| /* 256 */ "bne $\xFF\x03\x02\0" |
| /* 265 */ "bne- $\x02, $\xFF\x03\x02\0" |
| /* 279 */ "bne- $\xFF\x03\x02\0" |
| /* 289 */ "bne+ $\x02, $\xFF\x03\x02\0" |
| /* 303 */ "bne+ $\xFF\x03\x02\0" |
| /* 313 */ "blta $\x02, $\xFF\x03\x03\0" |
| /* 327 */ "blta $\xFF\x03\x03\0" |
| /* 337 */ "blta- $\x02, $\xFF\x03\x03\0" |
| /* 352 */ "blta- $\xFF\x03\x03\0" |
| /* 363 */ "blta+ $\x02, $\xFF\x03\x03\0" |
| /* 378 */ "blta+ $\xFF\x03\x03\0" |
| /* 389 */ "bgta $\x02, $\xFF\x03\x03\0" |
| /* 403 */ "bgta $\xFF\x03\x03\0" |
| /* 413 */ "bgta- $\x02, $\xFF\x03\x03\0" |
| /* 428 */ "bgta- $\xFF\x03\x03\0" |
| /* 439 */ "bgta+ $\x02, $\xFF\x03\x03\0" |
| /* 454 */ "bgta+ $\xFF\x03\x03\0" |
| /* 465 */ "beqa $\x02, $\xFF\x03\x03\0" |
| /* 479 */ "beqa $\xFF\x03\x03\0" |
| /* 489 */ "beqa- $\x02, $\xFF\x03\x03\0" |
| /* 504 */ "beqa- $\xFF\x03\x03\0" |
| /* 515 */ "beqa+ $\x02, $\xFF\x03\x03\0" |
| /* 530 */ "beqa+ $\xFF\x03\x03\0" |
| /* 541 */ "bnea $\x02, $\xFF\x03\x03\0" |
| /* 555 */ "bnea $\xFF\x03\x03\0" |
| /* 565 */ "bnea- $\x02, $\xFF\x03\x03\0" |
| /* 580 */ "bnea- $\xFF\x03\x03\0" |
| /* 591 */ "bnea+ $\x02, $\xFF\x03\x03\0" |
| /* 606 */ "bnea+ $\xFF\x03\x03\0" |
| /* 617 */ "bltctr $\x02\0" |
| /* 627 */ "bltctr\0" |
| /* 634 */ "bltctr- $\x02\0" |
| /* 645 */ "bltctr-\0" |
| /* 653 */ "bltctr+ $\x02\0" |
| /* 664 */ "bltctr+\0" |
| /* 672 */ "bgtctr $\x02\0" |
| /* 682 */ "bgtctr\0" |
| /* 689 */ "bgtctr- $\x02\0" |
| /* 700 */ "bgtctr-\0" |
| /* 708 */ "bgtctr+ $\x02\0" |
| /* 719 */ "bgtctr+\0" |
| /* 727 */ "beqctr $\x02\0" |
| /* 737 */ "beqctr\0" |
| /* 744 */ "beqctr- $\x02\0" |
| /* 755 */ "beqctr-\0" |
| /* 763 */ "beqctr+ $\x02\0" |
| /* 774 */ "beqctr+\0" |
| /* 782 */ "bnectr $\x02\0" |
| /* 792 */ "bnectr\0" |
| /* 799 */ "bnectr- $\x02\0" |
| /* 810 */ "bnectr-\0" |
| /* 818 */ "bnectr+ $\x02\0" |
| /* 829 */ "bnectr+\0" |
| /* 837 */ "bltctrl $\x02\0" |
| /* 848 */ "bltctrl\0" |
| /* 856 */ "bltctrl- $\x02\0" |
| /* 868 */ "bltctrl-\0" |
| /* 877 */ "bltctrl+ $\x02\0" |
| /* 889 */ "bltctrl+\0" |
| /* 898 */ "bgtctrl $\x02\0" |
| /* 909 */ "bgtctrl\0" |
| /* 917 */ "bgtctrl- $\x02\0" |
| /* 929 */ "bgtctrl-\0" |
| /* 938 */ "bgtctrl+ $\x02\0" |
| /* 950 */ "bgtctrl+\0" |
| /* 959 */ "beqctrl $\x02\0" |
| /* 970 */ "beqctrl\0" |
| /* 978 */ "beqctrl- $\x02\0" |
| /* 990 */ "beqctrl-\0" |
| /* 999 */ "beqctrl+ $\x02\0" |
| /* 1011 */ "beqctrl+\0" |
| /* 1020 */ "bnectrl $\x02\0" |
| /* 1031 */ "bnectrl\0" |
| /* 1039 */ "bnectrl- $\x02\0" |
| /* 1051 */ "bnectrl-\0" |
| /* 1060 */ "bnectrl+ $\x02\0" |
| /* 1072 */ "bnectrl+\0" |
| /* 1081 */ "bltl $\x02, $\xFF\x03\x02\0" |
| /* 1095 */ "bltl $\xFF\x03\x02\0" |
| /* 1105 */ "bltl- $\x02, $\xFF\x03\x02\0" |
| /* 1120 */ "bltl- $\xFF\x03\x02\0" |
| /* 1131 */ "bltl+ $\x02, $\xFF\x03\x02\0" |
| /* 1146 */ "bltl+ $\xFF\x03\x02\0" |
| /* 1157 */ "bgtl $\x02, $\xFF\x03\x02\0" |
| /* 1171 */ "bgtl $\xFF\x03\x02\0" |
| /* 1181 */ "bgtl- $\x02, $\xFF\x03\x02\0" |
| /* 1196 */ "bgtl- $\xFF\x03\x02\0" |
| /* 1207 */ "bgtl+ $\x02, $\xFF\x03\x02\0" |
| /* 1222 */ "bgtl+ $\xFF\x03\x02\0" |
| /* 1233 */ "beql $\x02, $\xFF\x03\x02\0" |
| /* 1247 */ "beql $\xFF\x03\x02\0" |
| /* 1257 */ "beql- $\x02, $\xFF\x03\x02\0" |
| /* 1272 */ "beql- $\xFF\x03\x02\0" |
| /* 1283 */ "beql+ $\x02, $\xFF\x03\x02\0" |
| /* 1298 */ "beql+ $\xFF\x03\x02\0" |
| /* 1309 */ "bnel $\x02, $\xFF\x03\x02\0" |
| /* 1323 */ "bnel $\xFF\x03\x02\0" |
| /* 1333 */ "bnel- $\x02, $\xFF\x03\x02\0" |
| /* 1348 */ "bnel- $\xFF\x03\x02\0" |
| /* 1359 */ "bnel+ $\x02, $\xFF\x03\x02\0" |
| /* 1374 */ "bnel+ $\xFF\x03\x02\0" |
| /* 1385 */ "bltla $\x02, $\xFF\x03\x03\0" |
| /* 1400 */ "bltla $\xFF\x03\x03\0" |
| /* 1411 */ "bltla- $\x02, $\xFF\x03\x03\0" |
| /* 1427 */ "bltla- $\xFF\x03\x03\0" |
| /* 1439 */ "bltla+ $\x02, $\xFF\x03\x03\0" |
| /* 1455 */ "bltla+ $\xFF\x03\x03\0" |
| /* 1467 */ "bgtla $\x02, $\xFF\x03\x03\0" |
| /* 1482 */ "bgtla $\xFF\x03\x03\0" |
| /* 1493 */ "bgtla- $\x02, $\xFF\x03\x03\0" |
| /* 1509 */ "bgtla- $\xFF\x03\x03\0" |
| /* 1521 */ "bgtla+ $\x02, $\xFF\x03\x03\0" |
| /* 1537 */ "bgtla+ $\xFF\x03\x03\0" |
| /* 1549 */ "beqla $\x02, $\xFF\x03\x03\0" |
| /* 1564 */ "beqla $\xFF\x03\x03\0" |
| /* 1575 */ "beqla- $\x02, $\xFF\x03\x03\0" |
| /* 1591 */ "beqla- $\xFF\x03\x03\0" |
| /* 1603 */ "beqla+ $\x02, $\xFF\x03\x03\0" |
| /* 1619 */ "beqla+ $\xFF\x03\x03\0" |
| /* 1631 */ "bnela $\x02, $\xFF\x03\x03\0" |
| /* 1646 */ "bnela $\xFF\x03\x03\0" |
| /* 1657 */ "bnela- $\x02, $\xFF\x03\x03\0" |
| /* 1673 */ "bnela- $\xFF\x03\x03\0" |
| /* 1685 */ "bnela+ $\x02, $\xFF\x03\x03\0" |
| /* 1701 */ "bnela+ $\xFF\x03\x03\0" |
| /* 1713 */ "bltlr $\x02\0" |
| /* 1722 */ "bltlr\0" |
| /* 1728 */ "bltlr- $\x02\0" |
| /* 1738 */ "bltlr-\0" |
| /* 1745 */ "bltlr+ $\x02\0" |
| /* 1755 */ "bltlr+\0" |
| /* 1762 */ "bgtlr $\x02\0" |
| /* 1771 */ "bgtlr\0" |
| /* 1777 */ "bgtlr- $\x02\0" |
| /* 1787 */ "bgtlr-\0" |
| /* 1794 */ "bgtlr+ $\x02\0" |
| /* 1804 */ "bgtlr+\0" |
| /* 1811 */ "beqlr $\x02\0" |
| /* 1820 */ "beqlr\0" |
| /* 1826 */ "beqlr- $\x02\0" |
| /* 1836 */ "beqlr-\0" |
| /* 1843 */ "beqlr+ $\x02\0" |
| /* 1853 */ "beqlr+\0" |
| /* 1860 */ "bnelr $\x02\0" |
| /* 1869 */ "bnelr\0" |
| /* 1875 */ "bnelr- $\x02\0" |
| /* 1885 */ "bnelr-\0" |
| /* 1892 */ "bnelr+ $\x02\0" |
| /* 1902 */ "bnelr+\0" |
| /* 1909 */ "bltlrl $\x02\0" |
| /* 1919 */ "bltlrl\0" |
| /* 1926 */ "bltlrl- $\x02\0" |
| /* 1937 */ "bltlrl-\0" |
| /* 1945 */ "bltlrl+ $\x02\0" |
| /* 1956 */ "bltlrl+\0" |
| /* 1964 */ "bgtlrl $\x02\0" |
| /* 1974 */ "bgtlrl\0" |
| /* 1981 */ "bgtlrl- $\x02\0" |
| /* 1992 */ "bgtlrl-\0" |
| /* 2000 */ "bgtlrl+ $\x02\0" |
| /* 2011 */ "bgtlrl+\0" |
| /* 2019 */ "beqlrl $\x02\0" |
| /* 2029 */ "beqlrl\0" |
| /* 2036 */ "beqlrl- $\x02\0" |
| /* 2047 */ "beqlrl-\0" |
| /* 2055 */ "beqlrl+ $\x02\0" |
| /* 2066 */ "beqlrl+\0" |
| /* 2074 */ "bnelrl $\x02\0" |
| /* 2084 */ "bnelrl\0" |
| /* 2091 */ "bnelrl- $\x02\0" |
| /* 2102 */ "bnelrl-\0" |
| /* 2110 */ "bnelrl+ $\x02\0" |
| /* 2121 */ "bnelrl+\0" |
| /* 2129 */ "cmpd $\x02, $\x03\0" |
| /* 2141 */ "cmpdi $\x02, $\xFF\x03\x01\0" |
| /* 2156 */ "cmpld $\x02, $\x03\0" |
| /* 2169 */ "cmpldi $\x02, $\xFF\x03\x04\0" |
| /* 2185 */ "cmplw $\x02, $\x03\0" |
| /* 2198 */ "cmplwi $\x02, $\xFF\x03\x04\0" |
| /* 2214 */ "cmpw $\x02, $\x03\0" |
| /* 2226 */ "cmpwi $\x02, $\xFF\x03\x01\0" |
| /* 2241 */ "cntlzw $\x01, $\x02\0" |
| /* 2255 */ "cntlzw. $\x01, $\x02\0" |
| /* 2270 */ "paste. $\x01, $\x02\0" |
| /* 2284 */ "crset $\x01\0" |
| /* 2293 */ "crnot $\x01, $\x02\0" |
| /* 2306 */ "crmove $\x01, $\x02\0" |
| /* 2320 */ "crclr $\x01\0" |
| /* 2329 */ "isellt $\x01, $\x02, $\x03\0" |
| /* 2347 */ "iselgt $\x01, $\x02, $\x03\0" |
| /* 2365 */ "iseleq $\x01, $\x02, $\x03\0" |
| /* 2383 */ "mbar\0" |
| /* 2388 */ "mfbr0 $\x01\0" |
| /* 2397 */ "mfbr1 $\x01\0" |
| /* 2406 */ "mfbr2 $\x01\0" |
| /* 2415 */ "mfbr3 $\x01\0" |
| /* 2424 */ "mfbr4 $\x01\0" |
| /* 2433 */ "mfbr5 $\x01\0" |
| /* 2442 */ "mfbr6 $\x01\0" |
| /* 2451 */ "mfbr7 $\x01\0" |
| /* 2460 */ "mfxer $\x01\0" |
| /* 2469 */ "mfudscr $\x01\0" |
| /* 2480 */ "mfrtcu $\x01\0" |
| /* 2490 */ "mfrtcl $\x01\0" |
| /* 2500 */ "mflr $\x01\0" |
| /* 2508 */ "mfctr $\x01\0" |
| /* 2517 */ "mfuamr $\x01\0" |
| /* 2527 */ "mfdscr $\x01\0" |
| /* 2537 */ "mfdsisr $\x01\0" |
| /* 2548 */ "mfdar $\x01\0" |
| /* 2557 */ "mfdec $\x01\0" |
| /* 2566 */ "mfsdr1 $\x01\0" |
| /* 2576 */ "mfsrr0 $\x01\0" |
| /* 2586 */ "mfsrr1 $\x01\0" |
| /* 2596 */ "mfcfar $\x01\0" |
| /* 2606 */ "mfamr $\x01\0" |
| /* 2615 */ "mfpid $\x01\0" |
| /* 2624 */ "mfasr $\x01\0" |
| /* 2633 */ "mfpvr $\x01\0" |
| /* 2642 */ "mfspefscr $\x01\0" |
| /* 2655 */ "mfdbatu $\x01, 0\0" |
| /* 2669 */ "mfdbatl $\x01, 0\0" |
| /* 2683 */ "mfibatu $\x01, 0\0" |
| /* 2697 */ "mfibatl $\x01, 0\0" |
| /* 2711 */ "mfdbatu $\x01, 1\0" |
| /* 2725 */ "mfdbatl $\x01, 1\0" |
| /* 2739 */ "mfibatu $\x01, 1\0" |
| /* 2753 */ "mfibatl $\x01, 1\0" |
| /* 2767 */ "mfdbatu $\x01, 2\0" |
| /* 2781 */ "mfdbatl $\x01, 2\0" |
| /* 2795 */ "mfibatu $\x01, 2\0" |
| /* 2809 */ "mfibatl $\x01, 2\0" |
| /* 2823 */ "mfdbatu $\x01, 3\0" |
| /* 2837 */ "mfdbatl $\x01, 3\0" |
| /* 2851 */ "mfibatu $\x01, 3\0" |
| /* 2865 */ "mfibatl $\x01, 3\0" |
| /* 2879 */ "mfppr $\x01\0" |
| /* 2888 */ "mfesr $\x01\0" |
| /* 2897 */ "mfdear $\x01\0" |
| /* 2907 */ "mftcr $\x01\0" |
| /* 2916 */ "mftbhi $\x01\0" |
| /* 2926 */ "mftblo $\x01\0" |
| /* 2936 */ "mfsrr2 $\x01\0" |
| /* 2946 */ "mfsrr3 $\x01\0" |
| /* 2956 */ "mfdccr $\x01\0" |
| /* 2966 */ "mficcr $\x01\0" |
| /* 2976 */ "mftbu $\x01\0" |
| /* 2985 */ "mfvrsave $\x01\0" |
| /* 2997 */ "mffprd $\x01, $\x02\0" |
| /* 3011 */ "mffprwz $\x01, $\x02\0" |
| /* 3026 */ "mtcr $\x02\0" |
| /* 3034 */ "mtbr0 $\x01\0" |
| /* 3043 */ "mtbr1 $\x01\0" |
| /* 3052 */ "mtbr2 $\x01\0" |
| /* 3061 */ "mtbr3 $\x01\0" |
| /* 3070 */ "mtbr4 $\x01\0" |
| /* 3079 */ "mtbr5 $\x01\0" |
| /* 3088 */ "mtbr6 $\x01\0" |
| /* 3097 */ "mtbr7 $\x01\0" |
| /* 3106 */ "mtfsf $\x01, $\x02\0" |
| /* 3119 */ "mtfsfi $\xFF\x01\x05, $\xFF\x02\x06\0" |
| /* 3137 */ "mtfsfi. $\xFF\x01\x05, $\xFF\x02\x06\0" |
| /* 3156 */ "mtfsf. $\x01, $\x02\0" |
| /* 3170 */ "mtmsr $\x01\0" |
| /* 3179 */ "mtmsrd $\x01\0" |
| /* 3189 */ "mtxer $\x02\0" |
| /* 3198 */ "mtudscr $\x02\0" |
| /* 3209 */ "mtlr $\x02\0" |
| /* 3217 */ "mtctr $\x02\0" |
| /* 3226 */ "mtuamr $\x02\0" |
| /* 3236 */ "mtdscr $\x02\0" |
| /* 3246 */ "mtdsisr $\x02\0" |
| /* 3257 */ "mtdar $\x02\0" |
| /* 3266 */ "mtdec $\x02\0" |
| /* 3275 */ "mtsdr1 $\x02\0" |
| /* 3285 */ "mtsrr0 $\x02\0" |
| /* 3295 */ "mtsrr1 $\x02\0" |
| /* 3305 */ "mtcfar $\x02\0" |
| /* 3315 */ "mtamr $\x02\0" |
| /* 3324 */ "mtpid $\x02\0" |
| /* 3333 */ "mtasr $\x02\0" |
| /* 3342 */ "mttbl $\x02\0" |
| /* 3351 */ "mttbu $\x02\0" |
| /* 3360 */ "mtspefscr $\x02\0" |
| /* 3373 */ "mtdbatu 0, $\x02\0" |
| /* 3387 */ "mtdbatl 0, $\x02\0" |
| /* 3401 */ "mtibatu 0, $\x02\0" |
| /* 3415 */ "mtibatl 0, $\x02\0" |
| /* 3429 */ "mtdbatu 1, $\x02\0" |
| /* 3443 */ "mtdbatl 1, $\x02\0" |
| /* 3457 */ "mtibatu 1, $\x02\0" |
| /* 3471 */ "mtibatl 1, $\x02\0" |
| /* 3485 */ "mtdbatu 2, $\x02\0" |
| /* 3499 */ "mtdbatl 2, $\x02\0" |
| /* 3513 */ "mtibatu 2, $\x02\0" |
| /* 3527 */ "mtibatl 2, $\x02\0" |
| /* 3541 */ "mtdbatu 3, $\x02\0" |
| /* 3555 */ "mtdbatl 3, $\x02\0" |
| /* 3569 */ "mtibatu 3, $\x02\0" |
| /* 3583 */ "mtibatl 3, $\x02\0" |
| /* 3597 */ "mtppr $\x02\0" |
| /* 3606 */ "mtesr $\x02\0" |
| /* 3615 */ "mtdear $\x02\0" |
| /* 3625 */ "mttcr $\x02\0" |
| /* 3634 */ "mttbhi $\x02\0" |
| /* 3644 */ "mttblo $\x02\0" |
| /* 3654 */ "mtsrr2 $\x02\0" |
| /* 3664 */ "mtsrr3 $\x02\0" |
| /* 3674 */ "mtdccr $\x02\0" |
| /* 3684 */ "mticcr $\x02\0" |
| /* 3694 */ "mtudscr $\x01\0" |
| /* 3705 */ "mtvrsave $\x01\0" |
| /* 3717 */ "mtfprd $\x01, $\x02\0" |
| /* 3731 */ "mtfprwa $\x01, $\x02\0" |
| /* 3746 */ "mtfprwz $\x01, $\x02\0" |
| /* 3761 */ "not $\x01, $\x02\0" |
| /* 3772 */ "not. $\x01, $\x02\0" |
| /* 3784 */ "mr $\x01, $\x02\0" |
| /* 3794 */ "mr. $\x01, $\x02\0" |
| /* 3805 */ "nop\0" |
| /* 3809 */ "rfebb\0" |
| /* 3815 */ "rotld $\x01, $\x02, $\x03\0" |
| /* 3832 */ "rotld. $\x01, $\x02, $\x03\0" |
| /* 3850 */ "rotldi $\x01, $\x02, $\xFF\x03\x07\0" |
| /* 3870 */ "clrldi $\x01, $\x02, $\xFF\x04\x07\0" |
| /* 3890 */ "rotldi. $\x01, $\x02, $\xFF\x03\x07\0" |
| /* 3911 */ "clrldi. $\x01, $\x02, $\xFF\x04\x07\0" |
| /* 3932 */ "rotlwi $\x01, $\x02, $\xFF\x03\x08\0" |
| /* 3952 */ "clrlwi $\x01, $\x02, $\xFF\x04\x08\0" |
| /* 3972 */ "rotlwi. $\x01, $\x02, $\xFF\x03\x08\0" |
| /* 3993 */ "clrlwi. $\x01, $\x02, $\xFF\x04\x08\0" |
| /* 4014 */ "rotlw $\x01, $\x02, $\x03\0" |
| /* 4031 */ "rotlw. $\x01, $\x02, $\x03\0" |
| /* 4049 */ "sc\0" |
| /* 4052 */ "sub $\x01, $\x03, $\x02\0" |
| /* 4067 */ "sub. $\x01, $\x03, $\x02\0" |
| /* 4083 */ "subc $\x01, $\x03, $\x02\0" |
| /* 4099 */ "subc. $\x01, $\x03, $\x02\0" |
| /* 4116 */ "sync\0" |
| /* 4121 */ "lwsync\0" |
| /* 4128 */ "ptesync\0" |
| /* 4136 */ "tdlt $\x02, $\x03\0" |
| /* 4148 */ "tdeq $\x02, $\x03\0" |
| /* 4160 */ "tdgt $\x02, $\x03\0" |
| /* 4172 */ "tdne $\x02, $\x03\0" |
| /* 4184 */ "tdllt $\x02, $\x03\0" |
| /* 4197 */ "tdlgt $\x02, $\x03\0" |
| /* 4210 */ "tdu $\x02, $\x03\0" |
| /* 4221 */ "tdlti $\x02, $\xFF\x03\x01\0" |
| /* 4236 */ "tdeqi $\x02, $\xFF\x03\x01\0" |
| /* 4251 */ "tdgti $\x02, $\xFF\x03\x01\0" |
| /* 4266 */ "tdnei $\x02, $\xFF\x03\x01\0" |
| /* 4281 */ "tdllti $\x02, $\xFF\x03\x01\0" |
| /* 4297 */ "tdlgti $\x02, $\xFF\x03\x01\0" |
| /* 4313 */ "tdui $\x02, $\xFF\x03\x01\0" |
| /* 4327 */ "tend.\0" |
| /* 4333 */ "tendall.\0" |
| /* 4342 */ "tlbie $\x02\0" |
| /* 4351 */ "tlbrehi $\x01, $\x02\0" |
| /* 4366 */ "tlbrelo $\x01, $\x02\0" |
| /* 4381 */ "tlbwehi $\x01, $\x02\0" |
| /* 4396 */ "tlbwelo $\x01, $\x02\0" |
| /* 4411 */ "tsuspend.\0" |
| /* 4421 */ "tresume.\0" |
| /* 4430 */ "trap\0" |
| /* 4435 */ "twlt $\x02, $\x03\0" |
| /* 4447 */ "tweq $\x02, $\x03\0" |
| /* 4459 */ "twgt $\x02, $\x03\0" |
| /* 4471 */ "twne $\x02, $\x03\0" |
| /* 4483 */ "twllt $\x02, $\x03\0" |
| /* 4496 */ "twlgt $\x02, $\x03\0" |
| /* 4509 */ "twu $\x02, $\x03\0" |
| /* 4520 */ "twlti $\x02, $\xFF\x03\x01\0" |
| /* 4535 */ "tweqi $\x02, $\xFF\x03\x01\0" |
| /* 4550 */ "twgti $\x02, $\xFF\x03\x01\0" |
| /* 4565 */ "twnei $\x02, $\xFF\x03\x01\0" |
| /* 4580 */ "twllti $\x02, $\xFF\x03\x01\0" |
| /* 4596 */ "twlgti $\x02, $\xFF\x03\x01\0" |
| /* 4612 */ "twui $\x02, $\xFF\x03\x01\0" |
| /* 4626 */ "vnot $\x01, $\x02\0" |
| /* 4638 */ "vmr $\x01, $\x02\0" |
| /* 4649 */ "wait\0" |
| /* 4654 */ "waitrsv\0" |
| /* 4662 */ "waitimpl\0" |
| /* 4671 */ "xnop\0" |
| /* 4676 */ "xvmovdp $\x01, $\x02\0" |
| /* 4691 */ "xvmovsp $\x01, $\x02\0" |
| /* 4706 */ "xxspltd $\x01, $\x02, 0\0" |
| /* 4724 */ "xxspltd $\x01, $\x02, 1\0" |
| /* 4742 */ "xxmrghd $\x01, $\x02, $\x03\0" |
| /* 4761 */ "xxmrgld $\x01, $\x02, $\x03\0" |
| /* 4780 */ "xxswapd $\x01, $\x02\0" |
| /* 4795 */ "bt $\x02, $\xFF\x03\x02\0" |
| /* 4807 */ "bf $\x02, $\xFF\x03\x02\0" |
| /* 4819 */ "bt- $\x02, $\xFF\x03\x02\0" |
| /* 4832 */ "bf- $\x02, $\xFF\x03\x02\0" |
| /* 4845 */ "bt+ $\x02, $\xFF\x03\x02\0" |
| /* 4858 */ "bf+ $\x02, $\xFF\x03\x02\0" |
| /* 4871 */ "bdnzt $\x02, $\xFF\x03\x02\0" |
| /* 4886 */ "bdnzf $\x02, $\xFF\x03\x02\0" |
| /* 4901 */ "bdzt $\x02, $\xFF\x03\x02\0" |
| /* 4915 */ "bdzf $\x02, $\xFF\x03\x02\0" |
| /* 4929 */ "bta $\x02, $\xFF\x03\x03\0" |
| /* 4942 */ "bfa $\x02, $\xFF\x03\x03\0" |
| /* 4955 */ "bta- $\x02, $\xFF\x03\x03\0" |
| /* 4969 */ "bfa- $\x02, $\xFF\x03\x03\0" |
| /* 4983 */ "bta+ $\x02, $\xFF\x03\x03\0" |
| /* 4997 */ "bfa+ $\x02, $\xFF\x03\x03\0" |
| /* 5011 */ "bdnzta $\x02, $\xFF\x03\x03\0" |
| /* 5027 */ "bdnzfa $\x02, $\xFF\x03\x03\0" |
| /* 5043 */ "bdzta $\x02, $\xFF\x03\x03\0" |
| /* 5058 */ "bdzfa $\x02, $\xFF\x03\x03\0" |
| /* 5073 */ "bca+ $\xFF\x01\x08, $\x03, $\xFF\x04\x02\0" |
| /* 5093 */ "bca- $\xFF\x01\x08, $\x03, $\xFF\x04\x02\0" |
| /* 5113 */ "bcctr $\xFF\x01\x08, $\x02\0" |
| /* 5128 */ "btctr $\x02\0" |
| /* 5137 */ "bfctr $\x02\0" |
| /* 5146 */ "btctr- $\x02\0" |
| /* 5156 */ "bfctr- $\x02\0" |
| /* 5166 */ "btctr+ $\x02\0" |
| /* 5176 */ "bfctr+ $\x02\0" |
| /* 5186 */ "bcctrl $\xFF\x01\x08, $\x02\0" |
| /* 5202 */ "btctrl $\x02\0" |
| /* 5212 */ "bfctrl $\x02\0" |
| /* 5222 */ "btctrl- $\x02\0" |
| /* 5233 */ "bfctrl- $\x02\0" |
| /* 5244 */ "btctrl+ $\x02\0" |
| /* 5255 */ "bfctrl+ $\x02\0" |
| /* 5266 */ "btl $\x02, $\xFF\x03\x02\0" |
| /* 5279 */ "bfl $\x02, $\xFF\x03\x02\0" |
| /* 5292 */ "btl- $\x02, $\xFF\x03\x02\0" |
| /* 5306 */ "bfl- $\x02, $\xFF\x03\x02\0" |
| /* 5320 */ "btl+ $\x02, $\xFF\x03\x02\0" |
| /* 5334 */ "bfl+ $\x02, $\xFF\x03\x02\0" |
| /* 5348 */ "bdnztl $\x02, $\xFF\x03\x02\0" |
| /* 5364 */ "bdnzfl $\x02, $\xFF\x03\x02\0" |
| /* 5380 */ "bdztl $\x02, $\xFF\x03\x02\0" |
| /* 5395 */ "bdzfl $\x02, $\xFF\x03\x02\0" |
| /* 5410 */ "btla $\x02, $\xFF\x03\x03\0" |
| /* 5424 */ "bfla $\x02, $\xFF\x03\x03\0" |
| /* 5438 */ "btla- $\x02, $\xFF\x03\x03\0" |
| /* 5453 */ "bfla- $\x02, $\xFF\x03\x03\0" |
| /* 5468 */ "btla+ $\x02, $\xFF\x03\x03\0" |
| /* 5483 */ "bfla+ $\x02, $\xFF\x03\x03\0" |
| /* 5498 */ "bdnztla $\x02, $\xFF\x03\x03\0" |
| /* 5515 */ "bdnzfla $\x02, $\xFF\x03\x03\0" |
| /* 5532 */ "bdztla $\x02, $\xFF\x03\x03\0" |
| /* 5548 */ "bdzfla $\x02, $\xFF\x03\x03\0" |
| /* 5564 */ "bcla+ $\xFF\x01\x08, $\x03, $\xFF\x04\x02\0" |
| /* 5585 */ "bcla- $\xFF\x01\x08, $\x03, $\xFF\x04\x02\0" |
| /* 5606 */ "bclr $\xFF\x01\x08, $\x02\0" |
| /* 5620 */ "btlr $\x02\0" |
| /* 5628 */ "bflr $\x02\0" |
| /* 5636 */ "btlr- $\x02\0" |
| /* 5645 */ "bflr- $\x02\0" |
| /* 5654 */ "btlr+ $\x02\0" |
| /* 5663 */ "bflr+ $\x02\0" |
| /* 5672 */ "bdnztlr $\x02\0" |
| /* 5683 */ "bdnzflr $\x02\0" |
| /* 5694 */ "bdztlr $\x02\0" |
| /* 5704 */ "bdzflr $\x02\0" |
| /* 5714 */ "bclrl $\xFF\x01\x08, $\x02\0" |
| /* 5729 */ "btlrl $\x02\0" |
| /* 5738 */ "bflrl $\x02\0" |
| /* 5747 */ "btlrl- $\x02\0" |
| /* 5757 */ "bflrl- $\x02\0" |
| /* 5767 */ "btlrl+ $\x02\0" |
| /* 5777 */ "bflrl+ $\x02\0" |
| /* 5787 */ "bdnztlrl $\x02\0" |
| /* 5799 */ "bdnzflrl $\x02\0" |
| /* 5811 */ "bdztlrl $\x02\0" |
| /* 5822 */ "bdzflrl $\x02\0" |
| /* 5833 */ "bcl+ $\xFF\x01\x08, $\x03, $\xFF\x04\x02\0" |
| /* 5853 */ "bcl- $\xFF\x01\x08, $\x03, $\xFF\x04\x02\0" |
| /* 5873 */ "bc+ $\xFF\x01\x08, $\x03, $\xFF\x04\x02\0" |
| /* 5892 */ "bc- $\xFF\x01\x08, $\x03, $\xFF\x04\x02\0" |
| ; |
| |
| #ifndef NDEBUG |
| static struct SortCheck { |
| SortCheck(ArrayRef<PatternsForOpcode> OpToPatterns) { |
| assert(std::is_sorted( |
| OpToPatterns.begin(), OpToPatterns.end(), |
| [](const PatternsForOpcode &L, const PatternsForOpcode &R) { |
| return L.Opcode < R.Opcode; |
| }) && |
| "tablegen failed to sort opcode patterns"); |
| } |
| } sortCheckVar(OpToPatterns); |
| #endif |
| |
| AliasMatchingData M { |
| ArrayRef(OpToPatterns), |
| ArrayRef(Patterns), |
| ArrayRef(Conds), |
| StringRef(AsmStrings, std::size(AsmStrings)), |
| nullptr, |
| }; |
| const char *AsmString = matchAliasPatterns(MI, &STI, M); |
| if (!AsmString) return false; |
| |
| unsigned I = 0; |
| while (AsmString[I] != ' ' && AsmString[I] != '\t' && |
| AsmString[I] != '$' && AsmString[I] != '\0') |
| ++I; |
| OS << '\t' << StringRef(AsmString, I); |
| if (AsmString[I] != '\0') { |
| if (AsmString[I] == ' ' || AsmString[I] == '\t') { |
| OS << '\t'; |
| ++I; |
| } |
| do { |
| if (AsmString[I] == '$') { |
| ++I; |
| if (AsmString[I] == (char)0xff) { |
| ++I; |
| int OpIdx = AsmString[I++] - 1; |
| int PrintMethodIdx = AsmString[I++] - 1; |
| printCustomAliasOperand(MI, Address, OpIdx, PrintMethodIdx, STI, OS); |
| } else |
| printOperand(MI, unsigned(AsmString[I++]) - 1, STI, OS); |
| } else { |
| OS << AsmString[I++]; |
| } |
| } while (AsmString[I] != '\0'); |
| } |
| |
| return true; |
| } |
| |
| void PPCInstPrinter::printCustomAliasOperand( |
| const MCInst *MI, uint64_t Address, unsigned OpIdx, |
| unsigned PrintMethodIdx, |
| const MCSubtargetInfo &STI, |
| raw_ostream &OS) { |
| switch (PrintMethodIdx) { |
| default: |
| llvm_unreachable("Unknown PrintMethod kind"); |
| break; |
| case 0: |
| printS16ImmOperand(MI, OpIdx, STI, OS); |
| break; |
| case 1: |
| printBranchOperand(MI, Address, OpIdx, STI, OS); |
| break; |
| case 2: |
| printAbsBranchOperand(MI, OpIdx, STI, OS); |
| break; |
| case 3: |
| printU16ImmOperand(MI, OpIdx, STI, OS); |
| break; |
| case 4: |
| printU3ImmOperand(MI, OpIdx, STI, OS); |
| break; |
| case 5: |
| printU4ImmOperand(MI, OpIdx, STI, OS); |
| break; |
| case 6: |
| printU6ImmOperand(MI, OpIdx, STI, OS); |
| break; |
| case 7: |
| printU5ImmOperand(MI, OpIdx, STI, OS); |
| break; |
| } |
| } |
| |
| #endif // PRINT_ALIAS_INSTR |
