| /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
| |* *| |
| |* Target Register Enum Values *| |
| |* *| |
| |* Automatically generated file, do not edit! *| |
| |* *| |
| \*===----------------------------------------------------------------------===*/ |
| |
| |
| #ifdef GET_REGINFO_ENUM |
| #undef GET_REGINFO_ENUM |
| |
| namespace llvm { |
| |
| class MCRegisterClass; |
| extern const MCRegisterClass MipsMCRegisterClasses[]; |
| |
| namespace Mips { |
| enum { |
| NoRegister, |
| AT = 1, |
| DSPCCond = 2, |
| DSPCarry = 3, |
| DSPEFI = 4, |
| DSPOutFlag = 5, |
| DSPPos = 6, |
| DSPSCount = 7, |
| FP = 8, |
| GP = 9, |
| MSAAccess = 10, |
| MSACSR = 11, |
| MSAIR = 12, |
| MSAMap = 13, |
| MSAModify = 14, |
| MSARequest = 15, |
| MSASave = 16, |
| MSAUnmap = 17, |
| PC = 18, |
| RA = 19, |
| SP = 20, |
| ZERO = 21, |
| A0 = 22, |
| A1 = 23, |
| A2 = 24, |
| A3 = 25, |
| AC0 = 26, |
| AC1 = 27, |
| AC2 = 28, |
| AC3 = 29, |
| AT_64 = 30, |
| COP00 = 31, |
| COP01 = 32, |
| COP02 = 33, |
| COP03 = 34, |
| COP04 = 35, |
| COP05 = 36, |
| COP06 = 37, |
| COP07 = 38, |
| COP08 = 39, |
| COP09 = 40, |
| COP20 = 41, |
| COP21 = 42, |
| COP22 = 43, |
| COP23 = 44, |
| COP24 = 45, |
| COP25 = 46, |
| COP26 = 47, |
| COP27 = 48, |
| COP28 = 49, |
| COP29 = 50, |
| COP30 = 51, |
| COP31 = 52, |
| COP32 = 53, |
| COP33 = 54, |
| COP34 = 55, |
| COP35 = 56, |
| COP36 = 57, |
| COP37 = 58, |
| COP38 = 59, |
| COP39 = 60, |
| COP010 = 61, |
| COP011 = 62, |
| COP012 = 63, |
| COP013 = 64, |
| COP014 = 65, |
| COP015 = 66, |
| COP016 = 67, |
| COP017 = 68, |
| COP018 = 69, |
| COP019 = 70, |
| COP020 = 71, |
| COP021 = 72, |
| COP022 = 73, |
| COP023 = 74, |
| COP024 = 75, |
| COP025 = 76, |
| COP026 = 77, |
| COP027 = 78, |
| COP028 = 79, |
| COP029 = 80, |
| COP030 = 81, |
| COP031 = 82, |
| COP210 = 83, |
| COP211 = 84, |
| COP212 = 85, |
| COP213 = 86, |
| COP214 = 87, |
| COP215 = 88, |
| COP216 = 89, |
| COP217 = 90, |
| COP218 = 91, |
| COP219 = 92, |
| COP220 = 93, |
| COP221 = 94, |
| COP222 = 95, |
| COP223 = 96, |
| COP224 = 97, |
| COP225 = 98, |
| COP226 = 99, |
| COP227 = 100, |
| COP228 = 101, |
| COP229 = 102, |
| COP230 = 103, |
| COP231 = 104, |
| COP310 = 105, |
| COP311 = 106, |
| COP312 = 107, |
| COP313 = 108, |
| COP314 = 109, |
| COP315 = 110, |
| COP316 = 111, |
| COP317 = 112, |
| COP318 = 113, |
| COP319 = 114, |
| COP320 = 115, |
| COP321 = 116, |
| COP322 = 117, |
| COP323 = 118, |
| COP324 = 119, |
| COP325 = 120, |
| COP326 = 121, |
| COP327 = 122, |
| COP328 = 123, |
| COP329 = 124, |
| COP330 = 125, |
| COP331 = 126, |
| D0 = 127, |
| D1 = 128, |
| D2 = 129, |
| D3 = 130, |
| D4 = 131, |
| D5 = 132, |
| D6 = 133, |
| D7 = 134, |
| D8 = 135, |
| D9 = 136, |
| D10 = 137, |
| D11 = 138, |
| D12 = 139, |
| D13 = 140, |
| D14 = 141, |
| D15 = 142, |
| DSPOutFlag20 = 143, |
| DSPOutFlag21 = 144, |
| DSPOutFlag22 = 145, |
| DSPOutFlag23 = 146, |
| F0 = 147, |
| F1 = 148, |
| F2 = 149, |
| F3 = 150, |
| F4 = 151, |
| F5 = 152, |
| F6 = 153, |
| F7 = 154, |
| F8 = 155, |
| F9 = 156, |
| F10 = 157, |
| F11 = 158, |
| F12 = 159, |
| F13 = 160, |
| F14 = 161, |
| F15 = 162, |
| F16 = 163, |
| F17 = 164, |
| F18 = 165, |
| F19 = 166, |
| F20 = 167, |
| F21 = 168, |
| F22 = 169, |
| F23 = 170, |
| F24 = 171, |
| F25 = 172, |
| F26 = 173, |
| F27 = 174, |
| F28 = 175, |
| F29 = 176, |
| F30 = 177, |
| F31 = 178, |
| FCC0 = 179, |
| FCC1 = 180, |
| FCC2 = 181, |
| FCC3 = 182, |
| FCC4 = 183, |
| FCC5 = 184, |
| FCC6 = 185, |
| FCC7 = 186, |
| FCR0 = 187, |
| FCR1 = 188, |
| FCR2 = 189, |
| FCR3 = 190, |
| FCR4 = 191, |
| FCR5 = 192, |
| FCR6 = 193, |
| FCR7 = 194, |
| FCR8 = 195, |
| FCR9 = 196, |
| FCR10 = 197, |
| FCR11 = 198, |
| FCR12 = 199, |
| FCR13 = 200, |
| FCR14 = 201, |
| FCR15 = 202, |
| FCR16 = 203, |
| FCR17 = 204, |
| FCR18 = 205, |
| FCR19 = 206, |
| FCR20 = 207, |
| FCR21 = 208, |
| FCR22 = 209, |
| FCR23 = 210, |
| FCR24 = 211, |
| FCR25 = 212, |
| FCR26 = 213, |
| FCR27 = 214, |
| FCR28 = 215, |
| FCR29 = 216, |
| FCR30 = 217, |
| FCR31 = 218, |
| FP_64 = 219, |
| F_HI0 = 220, |
| F_HI1 = 221, |
| F_HI2 = 222, |
| F_HI3 = 223, |
| F_HI4 = 224, |
| F_HI5 = 225, |
| F_HI6 = 226, |
| F_HI7 = 227, |
| F_HI8 = 228, |
| F_HI9 = 229, |
| F_HI10 = 230, |
| F_HI11 = 231, |
| F_HI12 = 232, |
| F_HI13 = 233, |
| F_HI14 = 234, |
| F_HI15 = 235, |
| F_HI16 = 236, |
| F_HI17 = 237, |
| F_HI18 = 238, |
| F_HI19 = 239, |
| F_HI20 = 240, |
| F_HI21 = 241, |
| F_HI22 = 242, |
| F_HI23 = 243, |
| F_HI24 = 244, |
| F_HI25 = 245, |
| F_HI26 = 246, |
| F_HI27 = 247, |
| F_HI28 = 248, |
| F_HI29 = 249, |
| F_HI30 = 250, |
| F_HI31 = 251, |
| GP_64 = 252, |
| HI0 = 253, |
| HI1 = 254, |
| HI2 = 255, |
| HI3 = 256, |
| HWR0 = 257, |
| HWR1 = 258, |
| HWR2 = 259, |
| HWR3 = 260, |
| HWR4 = 261, |
| HWR5 = 262, |
| HWR6 = 263, |
| HWR7 = 264, |
| HWR8 = 265, |
| HWR9 = 266, |
| HWR10 = 267, |
| HWR11 = 268, |
| HWR12 = 269, |
| HWR13 = 270, |
| HWR14 = 271, |
| HWR15 = 272, |
| HWR16 = 273, |
| HWR17 = 274, |
| HWR18 = 275, |
| HWR19 = 276, |
| HWR20 = 277, |
| HWR21 = 278, |
| HWR22 = 279, |
| HWR23 = 280, |
| HWR24 = 281, |
| HWR25 = 282, |
| HWR26 = 283, |
| HWR27 = 284, |
| HWR28 = 285, |
| HWR29 = 286, |
| HWR30 = 287, |
| HWR31 = 288, |
| K0 = 289, |
| K1 = 290, |
| LO0 = 291, |
| LO1 = 292, |
| LO2 = 293, |
| LO3 = 294, |
| MPL0 = 295, |
| MPL1 = 296, |
| MPL2 = 297, |
| MSA8 = 298, |
| MSA9 = 299, |
| MSA10 = 300, |
| MSA11 = 301, |
| MSA12 = 302, |
| MSA13 = 303, |
| MSA14 = 304, |
| MSA15 = 305, |
| MSA16 = 306, |
| MSA17 = 307, |
| MSA18 = 308, |
| MSA19 = 309, |
| MSA20 = 310, |
| MSA21 = 311, |
| MSA22 = 312, |
| MSA23 = 313, |
| MSA24 = 314, |
| MSA25 = 315, |
| MSA26 = 316, |
| MSA27 = 317, |
| MSA28 = 318, |
| MSA29 = 319, |
| MSA30 = 320, |
| MSA31 = 321, |
| P0 = 322, |
| P1 = 323, |
| P2 = 324, |
| RA_64 = 325, |
| S0 = 326, |
| S1 = 327, |
| S2 = 328, |
| S3 = 329, |
| S4 = 330, |
| S5 = 331, |
| S6 = 332, |
| S7 = 333, |
| SP_64 = 334, |
| T0 = 335, |
| T1 = 336, |
| T2 = 337, |
| T3 = 338, |
| T4 = 339, |
| T5 = 340, |
| T6 = 341, |
| T7 = 342, |
| T8 = 343, |
| T9 = 344, |
| V0 = 345, |
| V1 = 346, |
| W0 = 347, |
| W1 = 348, |
| W2 = 349, |
| W3 = 350, |
| W4 = 351, |
| W5 = 352, |
| W6 = 353, |
| W7 = 354, |
| W8 = 355, |
| W9 = 356, |
| W10 = 357, |
| W11 = 358, |
| W12 = 359, |
| W13 = 360, |
| W14 = 361, |
| W15 = 362, |
| W16 = 363, |
| W17 = 364, |
| W18 = 365, |
| W19 = 366, |
| W20 = 367, |
| W21 = 368, |
| W22 = 369, |
| W23 = 370, |
| W24 = 371, |
| W25 = 372, |
| W26 = 373, |
| W27 = 374, |
| W28 = 375, |
| W29 = 376, |
| W30 = 377, |
| W31 = 378, |
| ZERO_64 = 379, |
| A0_64 = 380, |
| A1_64 = 381, |
| A2_64 = 382, |
| A3_64 = 383, |
| AC0_64 = 384, |
| D0_64 = 385, |
| D1_64 = 386, |
| D2_64 = 387, |
| D3_64 = 388, |
| D4_64 = 389, |
| D5_64 = 390, |
| D6_64 = 391, |
| D7_64 = 392, |
| D8_64 = 393, |
| D9_64 = 394, |
| D10_64 = 395, |
| D11_64 = 396, |
| D12_64 = 397, |
| D13_64 = 398, |
| D14_64 = 399, |
| D15_64 = 400, |
| D16_64 = 401, |
| D17_64 = 402, |
| D18_64 = 403, |
| D19_64 = 404, |
| D20_64 = 405, |
| D21_64 = 406, |
| D22_64 = 407, |
| D23_64 = 408, |
| D24_64 = 409, |
| D25_64 = 410, |
| D26_64 = 411, |
| D27_64 = 412, |
| D28_64 = 413, |
| D29_64 = 414, |
| D30_64 = 415, |
| D31_64 = 416, |
| DSPOutFlag16_19 = 417, |
| HI0_64 = 418, |
| K0_64 = 419, |
| K1_64 = 420, |
| LO0_64 = 421, |
| S0_64 = 422, |
| S1_64 = 423, |
| S2_64 = 424, |
| S3_64 = 425, |
| S4_64 = 426, |
| S5_64 = 427, |
| S6_64 = 428, |
| S7_64 = 429, |
| T0_64 = 430, |
| T1_64 = 431, |
| T2_64 = 432, |
| T3_64 = 433, |
| T4_64 = 434, |
| T5_64 = 435, |
| T6_64 = 436, |
| T7_64 = 437, |
| T8_64 = 438, |
| T9_64 = 439, |
| V0_64 = 440, |
| V1_64 = 441, |
| NUM_TARGET_REGS // 442 |
| }; |
| } // end namespace Mips |
| |
| // Register classes |
| |
| namespace Mips { |
| enum { |
| MSA128F16RegClassID = 0, |
| CCRRegClassID = 1, |
| COP0RegClassID = 2, |
| COP2RegClassID = 3, |
| COP3RegClassID = 4, |
| DSPRRegClassID = 5, |
| FGR32RegClassID = 6, |
| FGRCCRegClassID = 7, |
| GPR32RegClassID = 8, |
| HWRegsRegClassID = 9, |
| MSACtrlRegClassID = 10, |
| GPR32NONZERORegClassID = 11, |
| CPU16RegsPlusSPRegClassID = 12, |
| CPU16RegsRegClassID = 13, |
| FCCRegClassID = 14, |
| GPRMM16RegClassID = 15, |
| GPRMM16MovePRegClassID = 16, |
| GPRMM16ZeroRegClassID = 17, |
| CPU16Regs_and_GPRMM16ZeroRegClassID = 18, |
| GPR32NONZERO_and_GPRMM16MovePRegClassID = 19, |
| GPRMM16MovePPairSecondRegClassID = 20, |
| CPU16Regs_and_GPRMM16MovePRegClassID = 21, |
| GPRMM16MoveP_and_GPRMM16ZeroRegClassID = 22, |
| HI32DSPRegClassID = 23, |
| LO32DSPRegClassID = 24, |
| CPU16Regs_and_GPRMM16MovePPairSecondRegClassID = 25, |
| GPRMM16MovePPairFirstRegClassID = 26, |
| GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID = 27, |
| GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID = 28, |
| CPURARegRegClassID = 29, |
| CPUSPRegRegClassID = 30, |
| DSPCCRegClassID = 31, |
| GP32RegClassID = 32, |
| GPR32ZERORegClassID = 33, |
| HI32RegClassID = 34, |
| LO32RegClassID = 35, |
| SP32RegClassID = 36, |
| FGR64RegClassID = 37, |
| GPR64RegClassID = 38, |
| GPR64_with_sub_32_in_GPR32NONZERORegClassID = 39, |
| AFGR64RegClassID = 40, |
| GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID = 41, |
| GPR64_with_sub_32_in_CPU16RegsRegClassID = 42, |
| GPR64_with_sub_32_in_GPRMM16MovePRegClassID = 43, |
| GPR64_with_sub_32_in_GPRMM16ZeroRegClassID = 44, |
| GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClassID = 45, |
| GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClassID = 46, |
| GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClassID = 47, |
| ACC64DSPRegClassID = 48, |
| GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClassID = 49, |
| GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClassID = 50, |
| GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClassID = 51, |
| GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClassID = 52, |
| GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID = 53, |
| OCTEON_MPLRegClassID = 54, |
| OCTEON_PRegClassID = 55, |
| GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID = 56, |
| ACC64RegClassID = 57, |
| GP64RegClassID = 58, |
| GPR64_with_sub_32_in_CPURARegRegClassID = 59, |
| GPR64_with_sub_32_in_GPR32ZERORegClassID = 60, |
| HI64RegClassID = 61, |
| LO64RegClassID = 62, |
| SP64RegClassID = 63, |
| MSA128BRegClassID = 64, |
| MSA128DRegClassID = 65, |
| MSA128HRegClassID = 66, |
| MSA128WRegClassID = 67, |
| MSA128WEvensRegClassID = 68, |
| ACC128RegClassID = 69, |
| |
| }; |
| } // end namespace Mips |
| |
| |
| // Subregister indices |
| |
| namespace Mips { |
| enum : uint16_t { |
| NoSubRegister, |
| sub_32, // 1 |
| sub_64, // 2 |
| sub_dsp16_19, // 3 |
| sub_dsp20, // 4 |
| sub_dsp21, // 5 |
| sub_dsp22, // 6 |
| sub_dsp23, // 7 |
| sub_hi, // 8 |
| sub_lo, // 9 |
| sub_hi_then_sub_32, // 10 |
| sub_32_sub_hi_then_sub_32, // 11 |
| NUM_TARGET_SUBREGS |
| }; |
| } // end namespace Mips |
| |
| // Register pressure sets enum. |
| namespace Mips { |
| enum RegisterPressureSets { |
| DSPCC = 0, |
| GPR32ZERO = 1, |
| GPR64_with_sub_32_in_CPURAReg = 2, |
| HI32 = 3, |
| GPRMM16MovePPairFirst = 4, |
| CPU16Regs_and_GPRMM16MoveP = 5, |
| HI32DSP = 6, |
| LO32DSP = 7, |
| GPRMM16MovePPairSecond = 8, |
| GPRMM16MoveP = 9, |
| ACC64DSP = 10, |
| CPU16Regs = 11, |
| GPRMM16Zero_with_GPRMM16MovePPairSecond = 12, |
| CPU16Regs_with_GPRMM16MovePPairSecond = 13, |
| CPU16Regs_with_GPRMM16MoveP = 14, |
| DSPR = 15, |
| FGR32 = 16, |
| MSA128WEvens = 17, |
| FGR32_with_MSA128WEvens = 18, |
| MSA128F16 = 19, |
| }; |
| } // end namespace Mips |
| |
| } // end namespace llvm |
| |
| #endif // GET_REGINFO_ENUM |
| |
| /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
| |* *| |
| |* MC Register Information *| |
| |* *| |
| |* Automatically generated file, do not edit! *| |
| |* *| |
| \*===----------------------------------------------------------------------===*/ |
| |
| |
| #ifdef GET_REGINFO_MC_DESC |
| #undef GET_REGINFO_MC_DESC |
| |
| namespace llvm { |
| |
| extern const MCPhysReg MipsRegDiffLists[] = { |
| /* 0 */ 0, 0, |
| /* 2 */ 4, 1, 1, 1, 1, 0, |
| /* 8 */ 412, 65262, 1, 1, 1, 0, |
| /* 14 */ 20, 1, 0, |
| /* 17 */ 21, 1, 0, |
| /* 20 */ 22, 1, 0, |
| /* 23 */ 23, 1, 0, |
| /* 26 */ 24, 1, 0, |
| /* 29 */ 25, 1, 0, |
| /* 32 */ 26, 1, 0, |
| /* 35 */ 27, 1, 0, |
| /* 38 */ 28, 1, 0, |
| /* 41 */ 29, 1, 0, |
| /* 44 */ 30, 1, 0, |
| /* 47 */ 31, 1, 0, |
| /* 50 */ 32, 1, 0, |
| /* 53 */ 33, 1, 0, |
| /* 56 */ 34, 1, 0, |
| /* 59 */ 35, 1, 0, |
| /* 62 */ 65415, 1, 0, |
| /* 65 */ 65513, 1, 0, |
| /* 68 */ 3, 0, |
| /* 70 */ 4, 0, |
| /* 72 */ 6, 0, |
| /* 74 */ 11, 0, |
| /* 76 */ 12, 0, |
| /* 78 */ 22, 0, |
| /* 80 */ 23, 0, |
| /* 82 */ 29, 0, |
| /* 84 */ 30, 0, |
| /* 86 */ 65284, 72, 0, |
| /* 89 */ 65322, 72, 0, |
| /* 92 */ 38, 65298, 73, 0, |
| /* 96 */ 95, 0, |
| /* 98 */ 96, 0, |
| /* 100 */ 130, 0, |
| /* 102 */ 211, 0, |
| /* 104 */ 243, 0, |
| /* 106 */ 306, 0, |
| /* 108 */ 314, 0, |
| /* 110 */ 358, 0, |
| /* 112 */ 64983, 0, |
| /* 114 */ 65060, 0, |
| /* 116 */ 65124, 0, |
| /* 118 */ 65178, 0, |
| /* 120 */ 65181, 0, |
| /* 122 */ 65222, 0, |
| /* 124 */ 65230, 0, |
| /* 126 */ 65271, 0, |
| /* 128 */ 65293, 0, |
| /* 130 */ 37, 65406, 127, 65371, 65309, 0, |
| /* 136 */ 65325, 0, |
| /* 138 */ 65371, 0, |
| /* 140 */ 65386, 0, |
| /* 142 */ 65395, 0, |
| /* 144 */ 65396, 0, |
| /* 146 */ 65397, 0, |
| /* 148 */ 65398, 0, |
| /* 150 */ 65406, 0, |
| /* 152 */ 65415, 0, |
| /* 154 */ 65440, 0, |
| /* 156 */ 65441, 0, |
| /* 158 */ 165, 65498, 0, |
| /* 161 */ 65516, 258, 65498, 0, |
| /* 165 */ 65515, 259, 65498, 0, |
| /* 169 */ 65514, 260, 65498, 0, |
| /* 173 */ 65513, 261, 65498, 0, |
| /* 177 */ 65512, 262, 65498, 0, |
| /* 181 */ 65511, 263, 65498, 0, |
| /* 185 */ 65510, 264, 65498, 0, |
| /* 189 */ 65509, 265, 65498, 0, |
| /* 193 */ 65508, 266, 65498, 0, |
| /* 197 */ 65507, 267, 65498, 0, |
| /* 201 */ 65506, 268, 65498, 0, |
| /* 205 */ 65505, 269, 65498, 0, |
| /* 209 */ 65504, 270, 65498, 0, |
| /* 213 */ 65503, 271, 65498, 0, |
| /* 217 */ 65502, 272, 65498, 0, |
| /* 221 */ 65501, 273, 65498, 0, |
| /* 225 */ 65500, 274, 65498, 0, |
| /* 229 */ 65271, 395, 65499, 0, |
| /* 233 */ 65309, 392, 65502, 0, |
| /* 237 */ 65507, 0, |
| /* 239 */ 65510, 0, |
| /* 241 */ 65511, 0, |
| /* 243 */ 65512, 0, |
| /* 245 */ 65516, 0, |
| /* 247 */ 65521, 0, |
| /* 249 */ 65522, 0, |
| /* 251 */ 65535, 0, |
| }; |
| |
| extern const LaneBitmask MipsLaneMaskLists[] = { |
| /* 0 */ LaneBitmask(0x0000000000000000), LaneBitmask::getAll(), |
| /* 2 */ LaneBitmask(0x0000000000000001), LaneBitmask::getAll(), |
| /* 4 */ LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000010), LaneBitmask(0x0000000000000020), LaneBitmask::getAll(), |
| /* 10 */ LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000000040), LaneBitmask::getAll(), |
| }; |
| |
| extern const uint16_t MipsSubRegIdxLists[] = { |
| /* 0 */ 1, 0, |
| /* 2 */ 3, 4, 5, 6, 7, 0, |
| /* 8 */ 2, 9, 8, 0, |
| /* 12 */ 9, 1, 8, 10, 11, 0, |
| }; |
| |
| extern const MCRegisterInfo::SubRegCoveredBits MipsSubRegIdxRanges[] = { |
| { 65535, 65535 }, |
| { 0, 32 }, // sub_32 |
| { 0, 64 }, // sub_64 |
| { 16, 4 }, // sub_dsp16_19 |
| { 20, 1 }, // sub_dsp20 |
| { 21, 1 }, // sub_dsp21 |
| { 22, 1 }, // sub_dsp22 |
| { 23, 1 }, // sub_dsp23 |
| { 32, 32 }, // sub_hi |
| { 0, 32 }, // sub_lo |
| { 32, 32 }, // sub_hi_then_sub_32 |
| { 0, 64 }, // sub_32_sub_hi_then_sub_32 |
| }; |
| |
| |
| #ifdef __GNUC__ |
| #pragma GCC diagnostic push |
| #pragma GCC diagnostic ignored "-Woverlength-strings" |
| #endif |
| extern const char MipsRegStrings[] = { |
| /* 0 */ "COP00\0" |
| /* 6 */ "COP010\0" |
| /* 13 */ "COP210\0" |
| /* 20 */ "COP310\0" |
| /* 27 */ "MSA10\0" |
| /* 33 */ "D10\0" |
| /* 37 */ "F10\0" |
| /* 41 */ "F_HI10\0" |
| /* 48 */ "FCR10\0" |
| /* 54 */ "HWR10\0" |
| /* 60 */ "W10\0" |
| /* 64 */ "COP020\0" |
| /* 71 */ "COP220\0" |
| /* 78 */ "COP320\0" |
| /* 85 */ "MSA20\0" |
| /* 91 */ "F20\0" |
| /* 95 */ "F_HI20\0" |
| /* 102 */ "COP20\0" |
| /* 108 */ "FCR20\0" |
| /* 114 */ "HWR20\0" |
| /* 120 */ "W20\0" |
| /* 124 */ "DSPOutFlag20\0" |
| /* 137 */ "COP030\0" |
| /* 144 */ "COP230\0" |
| /* 151 */ "COP330\0" |
| /* 158 */ "MSA30\0" |
| /* 164 */ "F30\0" |
| /* 168 */ "F_HI30\0" |
| /* 175 */ "COP30\0" |
| /* 181 */ "FCR30\0" |
| /* 187 */ "HWR30\0" |
| /* 193 */ "W30\0" |
| /* 197 */ "A0\0" |
| /* 200 */ "AC0\0" |
| /* 204 */ "FCC0\0" |
| /* 209 */ "D0\0" |
| /* 212 */ "F0\0" |
| /* 215 */ "F_HI0\0" |
| /* 221 */ "K0\0" |
| /* 224 */ "MPL0\0" |
| /* 229 */ "LO0\0" |
| /* 233 */ "P0\0" |
| /* 236 */ "FCR0\0" |
| /* 241 */ "HWR0\0" |
| /* 246 */ "S0\0" |
| /* 249 */ "T0\0" |
| /* 252 */ "V0\0" |
| /* 255 */ "W0\0" |
| /* 258 */ "COP01\0" |
| /* 264 */ "COP011\0" |
| /* 271 */ "COP211\0" |
| /* 278 */ "COP311\0" |
| /* 285 */ "MSA11\0" |
| /* 291 */ "D11\0" |
| /* 295 */ "F11\0" |
| /* 299 */ "F_HI11\0" |
| /* 306 */ "FCR11\0" |
| /* 312 */ "HWR11\0" |
| /* 318 */ "W11\0" |
| /* 322 */ "COP021\0" |
| /* 329 */ "COP221\0" |
| /* 336 */ "COP321\0" |
| /* 343 */ "MSA21\0" |
| /* 349 */ "F21\0" |
| /* 353 */ "F_HI21\0" |
| /* 360 */ "COP21\0" |
| /* 366 */ "FCR21\0" |
| /* 372 */ "HWR21\0" |
| /* 378 */ "W21\0" |
| /* 382 */ "DSPOutFlag21\0" |
| /* 395 */ "COP031\0" |
| /* 402 */ "COP231\0" |
| /* 409 */ "COP331\0" |
| /* 416 */ "MSA31\0" |
| /* 422 */ "F31\0" |
| /* 426 */ "F_HI31\0" |
| /* 433 */ "COP31\0" |
| /* 439 */ "FCR31\0" |
| /* 445 */ "HWR31\0" |
| /* 451 */ "W31\0" |
| /* 455 */ "A1\0" |
| /* 458 */ "AC1\0" |
| /* 462 */ "FCC1\0" |
| /* 467 */ "D1\0" |
| /* 470 */ "F1\0" |
| /* 473 */ "F_HI1\0" |
| /* 479 */ "K1\0" |
| /* 482 */ "MPL1\0" |
| /* 487 */ "LO1\0" |
| /* 491 */ "P1\0" |
| /* 494 */ "FCR1\0" |
| /* 499 */ "HWR1\0" |
| /* 504 */ "S1\0" |
| /* 507 */ "T1\0" |
| /* 510 */ "V1\0" |
| /* 513 */ "W1\0" |
| /* 516 */ "COP02\0" |
| /* 522 */ "COP012\0" |
| /* 529 */ "COP212\0" |
| /* 536 */ "COP312\0" |
| /* 543 */ "MSA12\0" |
| /* 549 */ "D12\0" |
| /* 553 */ "F12\0" |
| /* 557 */ "F_HI12\0" |
| /* 564 */ "FCR12\0" |
| /* 570 */ "HWR12\0" |
| /* 576 */ "W12\0" |
| /* 580 */ "COP022\0" |
| /* 587 */ "COP222\0" |
| /* 594 */ "COP322\0" |
| /* 601 */ "MSA22\0" |
| /* 607 */ "F22\0" |
| /* 611 */ "F_HI22\0" |
| /* 618 */ "COP22\0" |
| /* 624 */ "FCR22\0" |
| /* 630 */ "HWR22\0" |
| /* 636 */ "W22\0" |
| /* 640 */ "DSPOutFlag22\0" |
| /* 653 */ "COP32\0" |
| /* 659 */ "A2\0" |
| /* 662 */ "AC2\0" |
| /* 666 */ "FCC2\0" |
| /* 671 */ "D2\0" |
| /* 674 */ "F2\0" |
| /* 677 */ "F_HI2\0" |
| /* 683 */ "MPL2\0" |
| /* 688 */ "LO2\0" |
| /* 692 */ "P2\0" |
| /* 695 */ "FCR2\0" |
| /* 700 */ "HWR2\0" |
| /* 705 */ "S2\0" |
| /* 708 */ "T2\0" |
| /* 711 */ "W2\0" |
| /* 714 */ "COP03\0" |
| /* 720 */ "COP013\0" |
| /* 727 */ "COP213\0" |
| /* 734 */ "COP313\0" |
| /* 741 */ "MSA13\0" |
| /* 747 */ "D13\0" |
| /* 751 */ "F13\0" |
| /* 755 */ "F_HI13\0" |
| /* 762 */ "FCR13\0" |
| /* 768 */ "HWR13\0" |
| /* 774 */ "W13\0" |
| /* 778 */ "COP023\0" |
| /* 785 */ "COP223\0" |
| /* 792 */ "COP323\0" |
| /* 799 */ "MSA23\0" |
| /* 805 */ "F23\0" |
| /* 809 */ "F_HI23\0" |
| /* 816 */ "COP23\0" |
| /* 822 */ "FCR23\0" |
| /* 828 */ "HWR23\0" |
| /* 834 */ "W23\0" |
| /* 838 */ "DSPOutFlag23\0" |
| /* 851 */ "COP33\0" |
| /* 857 */ "A3\0" |
| /* 860 */ "AC3\0" |
| /* 864 */ "FCC3\0" |
| /* 869 */ "D3\0" |
| /* 872 */ "F3\0" |
| /* 875 */ "F_HI3\0" |
| /* 881 */ "LO3\0" |
| /* 885 */ "FCR3\0" |
| /* 890 */ "HWR3\0" |
| /* 895 */ "S3\0" |
| /* 898 */ "T3\0" |
| /* 901 */ "W3\0" |
| /* 904 */ "COP04\0" |
| /* 910 */ "COP014\0" |
| /* 917 */ "COP214\0" |
| /* 924 */ "COP314\0" |
| /* 931 */ "MSA14\0" |
| /* 937 */ "D14\0" |
| /* 941 */ "F14\0" |
| /* 945 */ "F_HI14\0" |
| /* 952 */ "FCR14\0" |
| /* 958 */ "HWR14\0" |
| /* 964 */ "W14\0" |
| /* 968 */ "COP024\0" |
| /* 975 */ "COP224\0" |
| /* 982 */ "COP324\0" |
| /* 989 */ "MSA24\0" |
| /* 995 */ "F24\0" |
| /* 999 */ "F_HI24\0" |
| /* 1006 */ "COP24\0" |
| /* 1012 */ "FCR24\0" |
| /* 1018 */ "HWR24\0" |
| /* 1024 */ "W24\0" |
| /* 1028 */ "COP34\0" |
| /* 1034 */ "D10_64\0" |
| /* 1041 */ "D20_64\0" |
| /* 1048 */ "D30_64\0" |
| /* 1055 */ "A0_64\0" |
| /* 1061 */ "AC0_64\0" |
| /* 1068 */ "D0_64\0" |
| /* 1074 */ "HI0_64\0" |
| /* 1081 */ "K0_64\0" |
| /* 1087 */ "LO0_64\0" |
| /* 1094 */ "S0_64\0" |
| /* 1100 */ "T0_64\0" |
| /* 1106 */ "V0_64\0" |
| /* 1112 */ "D11_64\0" |
| /* 1119 */ "D21_64\0" |
| /* 1126 */ "D31_64\0" |
| /* 1133 */ "A1_64\0" |
| /* 1139 */ "D1_64\0" |
| /* 1145 */ "K1_64\0" |
| /* 1151 */ "S1_64\0" |
| /* 1157 */ "T1_64\0" |
| /* 1163 */ "V1_64\0" |
| /* 1169 */ "D12_64\0" |
| /* 1176 */ "D22_64\0" |
| /* 1183 */ "A2_64\0" |
| /* 1189 */ "D2_64\0" |
| /* 1195 */ "S2_64\0" |
| /* 1201 */ "T2_64\0" |
| /* 1207 */ "D13_64\0" |
| /* 1214 */ "D23_64\0" |
| /* 1221 */ "A3_64\0" |
| /* 1227 */ "D3_64\0" |
| /* 1233 */ "S3_64\0" |
| /* 1239 */ "T3_64\0" |
| /* 1245 */ "D14_64\0" |
| /* 1252 */ "D24_64\0" |
| /* 1259 */ "D4_64\0" |
| /* 1265 */ "S4_64\0" |
| /* 1271 */ "T4_64\0" |
| /* 1277 */ "D15_64\0" |
| /* 1284 */ "D25_64\0" |
| /* 1291 */ "D5_64\0" |
| /* 1297 */ "S5_64\0" |
| /* 1303 */ "T5_64\0" |
| /* 1309 */ "D16_64\0" |
| /* 1316 */ "D26_64\0" |
| /* 1323 */ "D6_64\0" |
| /* 1329 */ "S6_64\0" |
| /* 1335 */ "T6_64\0" |
| /* 1341 */ "D17_64\0" |
| /* 1348 */ "D27_64\0" |
| /* 1355 */ "D7_64\0" |
| /* 1361 */ "S7_64\0" |
| /* 1367 */ "T7_64\0" |
| /* 1373 */ "D18_64\0" |
| /* 1380 */ "D28_64\0" |
| /* 1387 */ "D8_64\0" |
| /* 1393 */ "T8_64\0" |
| /* 1399 */ "D19_64\0" |
| /* 1406 */ "D29_64\0" |
| /* 1413 */ "D9_64\0" |
| /* 1419 */ "T9_64\0" |
| /* 1425 */ "RA_64\0" |
| /* 1431 */ "ZERO_64\0" |
| /* 1439 */ "FP_64\0" |
| /* 1445 */ "GP_64\0" |
| /* 1451 */ "SP_64\0" |
| /* 1457 */ "AT_64\0" |
| /* 1463 */ "FCC4\0" |
| /* 1468 */ "D4\0" |
| /* 1471 */ "F4\0" |
| /* 1474 */ "F_HI4\0" |
| /* 1480 */ "FCR4\0" |
| /* 1485 */ "HWR4\0" |
| /* 1490 */ "S4\0" |
| /* 1493 */ "T4\0" |
| /* 1496 */ "W4\0" |
| /* 1499 */ "COP05\0" |
| /* 1505 */ "COP015\0" |
| /* 1512 */ "COP215\0" |
| /* 1519 */ "COP315\0" |
| /* 1526 */ "MSA15\0" |
| /* 1532 */ "D15\0" |
| /* 1536 */ "F15\0" |
| /* 1540 */ "F_HI15\0" |
| /* 1547 */ "FCR15\0" |
| /* 1553 */ "HWR15\0" |
| /* 1559 */ "W15\0" |
| /* 1563 */ "COP025\0" |
| /* 1570 */ "COP225\0" |
| /* 1577 */ "COP325\0" |
| /* 1584 */ "MSA25\0" |
| /* 1590 */ "F25\0" |
| /* 1594 */ "F_HI25\0" |
| /* 1601 */ "COP25\0" |
| /* 1607 */ "FCR25\0" |
| /* 1613 */ "HWR25\0" |
| /* 1619 */ "W25\0" |
| /* 1623 */ "COP35\0" |
| /* 1629 */ "FCC5\0" |
| /* 1634 */ "D5\0" |
| /* 1637 */ "F5\0" |
| /* 1640 */ "F_HI5\0" |
| /* 1646 */ "FCR5\0" |
| /* 1651 */ "HWR5\0" |
| /* 1656 */ "S5\0" |
| /* 1659 */ "T5\0" |
| /* 1662 */ "W5\0" |
| /* 1665 */ "COP06\0" |
| /* 1671 */ "COP016\0" |
| /* 1678 */ "COP216\0" |
| /* 1685 */ "COP316\0" |
| /* 1692 */ "MSA16\0" |
| /* 1698 */ "F16\0" |
| /* 1702 */ "F_HI16\0" |
| /* 1709 */ "FCR16\0" |
| /* 1715 */ "HWR16\0" |
| /* 1721 */ "W16\0" |
| /* 1725 */ "COP026\0" |
| /* 1732 */ "COP226\0" |
| /* 1739 */ "COP326\0" |
| /* 1746 */ "MSA26\0" |
| /* 1752 */ "F26\0" |
| /* 1756 */ "F_HI26\0" |
| /* 1763 */ "COP26\0" |
| /* 1769 */ "FCR26\0" |
| /* 1775 */ "HWR26\0" |
| /* 1781 */ "W26\0" |
| /* 1785 */ "COP36\0" |
| /* 1791 */ "FCC6\0" |
| /* 1796 */ "D6\0" |
| /* 1799 */ "F6\0" |
| /* 1802 */ "F_HI6\0" |
| /* 1808 */ "FCR6\0" |
| /* 1813 */ "HWR6\0" |
| /* 1818 */ "S6\0" |
| /* 1821 */ "T6\0" |
| /* 1824 */ "W6\0" |
| /* 1827 */ "COP07\0" |
| /* 1833 */ "COP017\0" |
| /* 1840 */ "COP217\0" |
| /* 1847 */ "COP317\0" |
| /* 1854 */ "MSA17\0" |
| /* 1860 */ "F17\0" |
| /* 1864 */ "F_HI17\0" |
| /* 1871 */ "FCR17\0" |
| /* 1877 */ "HWR17\0" |
| /* 1883 */ "W17\0" |
| /* 1887 */ "COP027\0" |
| /* 1894 */ "COP227\0" |
| /* 1901 */ "COP327\0" |
| /* 1908 */ "MSA27\0" |
| /* 1914 */ "F27\0" |
| /* 1918 */ "F_HI27\0" |
| /* 1925 */ "COP27\0" |
| /* 1931 */ "FCR27\0" |
| /* 1937 */ "HWR27\0" |
| /* 1943 */ "W27\0" |
| /* 1947 */ "COP37\0" |
| /* 1953 */ "FCC7\0" |
| /* 1958 */ "D7\0" |
| /* 1961 */ "F7\0" |
| /* 1964 */ "F_HI7\0" |
| /* 1970 */ "FCR7\0" |
| /* 1975 */ "HWR7\0" |
| /* 1980 */ "S7\0" |
| /* 1983 */ "T7\0" |
| /* 1986 */ "W7\0" |
| /* 1989 */ "COP08\0" |
| /* 1995 */ "COP018\0" |
| /* 2002 */ "COP218\0" |
| /* 2009 */ "COP318\0" |
| /* 2016 */ "MSA18\0" |
| /* 2022 */ "F18\0" |
| /* 2026 */ "F_HI18\0" |
| /* 2033 */ "FCR18\0" |
| /* 2039 */ "HWR18\0" |
| /* 2045 */ "W18\0" |
| /* 2049 */ "COP028\0" |
| /* 2056 */ "COP228\0" |
| /* 2063 */ "COP328\0" |
| /* 2070 */ "MSA28\0" |
| /* 2076 */ "F28\0" |
| /* 2080 */ "F_HI28\0" |
| /* 2087 */ "COP28\0" |
| /* 2093 */ "FCR28\0" |
| /* 2099 */ "HWR28\0" |
| /* 2105 */ "W28\0" |
| /* 2109 */ "COP38\0" |
| /* 2115 */ "MSA8\0" |
| /* 2120 */ "D8\0" |
| /* 2123 */ "F8\0" |
| /* 2126 */ "F_HI8\0" |
| /* 2132 */ "FCR8\0" |
| /* 2137 */ "HWR8\0" |
| /* 2142 */ "T8\0" |
| /* 2145 */ "W8\0" |
| /* 2148 */ "COP09\0" |
| /* 2154 */ "COP019\0" |
| /* 2161 */ "COP219\0" |
| /* 2168 */ "COP319\0" |
| /* 2175 */ "MSA19\0" |
| /* 2181 */ "F19\0" |
| /* 2185 */ "F_HI19\0" |
| /* 2192 */ "FCR19\0" |
| /* 2198 */ "HWR19\0" |
| /* 2204 */ "W19\0" |
| /* 2208 */ "DSPOutFlag16_19\0" |
| /* 2224 */ "COP029\0" |
| /* 2231 */ "COP229\0" |
| /* 2238 */ "COP329\0" |
| /* 2245 */ "MSA29\0" |
| /* 2251 */ "F29\0" |
| /* 2255 */ "F_HI29\0" |
| /* 2262 */ "COP29\0" |
| /* 2268 */ "FCR29\0" |
| /* 2274 */ "HWR29\0" |
| /* 2280 */ "W29\0" |
| /* 2284 */ "COP39\0" |
| /* 2290 */ "MSA9\0" |
| /* 2295 */ "D9\0" |
| /* 2298 */ "F9\0" |
| /* 2301 */ "F_HI9\0" |
| /* 2307 */ "FCR9\0" |
| /* 2312 */ "HWR9\0" |
| /* 2317 */ "T9\0" |
| /* 2320 */ "W9\0" |
| /* 2323 */ "RA\0" |
| /* 2326 */ "PC\0" |
| /* 2329 */ "DSPEFI\0" |
| /* 2336 */ "ZERO\0" |
| /* 2341 */ "FP\0" |
| /* 2344 */ "GP\0" |
| /* 2347 */ "SP\0" |
| /* 2350 */ "MSAIR\0" |
| /* 2356 */ "MSACSR\0" |
| /* 2363 */ "AT\0" |
| /* 2366 */ "DSPCCond\0" |
| /* 2375 */ "MSASave\0" |
| /* 2383 */ "DSPOutFlag\0" |
| /* 2394 */ "MSAMap\0" |
| /* 2401 */ "MSAUnmap\0" |
| /* 2410 */ "DSPPos\0" |
| /* 2417 */ "MSAAccess\0" |
| /* 2427 */ "DSPSCount\0" |
| /* 2437 */ "MSARequest\0" |
| /* 2448 */ "MSAModify\0" |
| /* 2458 */ "DSPCarry\0" |
| }; |
| #ifdef __GNUC__ |
| #pragma GCC diagnostic pop |
| #endif |
| |
| extern const MCRegisterDesc MipsRegDesc[] = { // Descriptors |
| { 5, 0, 0, 0, 0, 0 }, |
| { 2363, 1, 82, 1, 4017, 0 }, |
| { 2366, 1, 1, 1, 4017, 0 }, |
| { 2458, 1, 1, 1, 4017, 0 }, |
| { 2329, 1, 1, 1, 4017, 0 }, |
| { 2383, 8, 1, 2, 32, 4 }, |
| { 2410, 1, 1, 1, 1089, 0 }, |
| { 2427, 1, 1, 1, 1089, 0 }, |
| { 2341, 1, 102, 1, 1089, 0 }, |
| { 2344, 1, 104, 1, 1089, 0 }, |
| { 2417, 1, 1, 1, 1089, 0 }, |
| { 2356, 1, 1, 1, 1089, 0 }, |
| { 2350, 1, 1, 1, 1089, 0 }, |
| { 2394, 1, 1, 1, 1089, 0 }, |
| { 2448, 1, 1, 1, 1089, 0 }, |
| { 2437, 1, 1, 1, 1089, 0 }, |
| { 2375, 1, 1, 1, 1089, 0 }, |
| { 2401, 1, 1, 1, 1089, 0 }, |
| { 2326, 1, 1, 1, 1089, 0 }, |
| { 2323, 1, 106, 1, 1089, 0 }, |
| { 2347, 1, 108, 1, 1089, 0 }, |
| { 2336, 1, 110, 1, 1089, 0 }, |
| { 197, 1, 110, 1, 1089, 0 }, |
| { 455, 1, 110, 1, 1089, 0 }, |
| { 659, 1, 110, 1, 1089, 0 }, |
| { 857, 1, 110, 1, 1089, 0 }, |
| { 200, 190, 110, 9, 1042, 10 }, |
| { 458, 190, 1, 9, 1042, 10 }, |
| { 662, 190, 1, 9, 1042, 10 }, |
| { 860, 190, 1, 9, 1042, 10 }, |
| { 1457, 237, 1, 0, 0, 2 }, |
| { 0, 1, 1, 1, 1153, 0 }, |
| { 258, 1, 1, 1, 1153, 0 }, |
| { 516, 1, 1, 1, 1153, 0 }, |
| { 714, 1, 1, 1, 1153, 0 }, |
| { 904, 1, 1, 1, 1153, 0 }, |
| { 1499, 1, 1, 1, 1153, 0 }, |
| { 1665, 1, 1, 1, 1153, 0 }, |
| { 1827, 1, 1, 1, 1153, 0 }, |
| { 1989, 1, 1, 1, 1153, 0 }, |
| { 2148, 1, 1, 1, 1153, 0 }, |
| { 102, 1, 1, 1, 1153, 0 }, |
| { 360, 1, 1, 1, 1153, 0 }, |
| { 618, 1, 1, 1, 1153, 0 }, |
| { 816, 1, 1, 1, 1153, 0 }, |
| { 1006, 1, 1, 1, 1153, 0 }, |
| { 1601, 1, 1, 1, 1153, 0 }, |
| { 1763, 1, 1, 1, 1153, 0 }, |
| { 1925, 1, 1, 1, 1153, 0 }, |
| { 2087, 1, 1, 1, 1153, 0 }, |
| { 2262, 1, 1, 1, 1153, 0 }, |
| { 175, 1, 1, 1, 1153, 0 }, |
| { 433, 1, 1, 1, 1153, 0 }, |
| { 653, 1, 1, 1, 1153, 0 }, |
| { 851, 1, 1, 1, 1153, 0 }, |
| { 1028, 1, 1, 1, 1153, 0 }, |
| { 1623, 1, 1, 1, 1153, 0 }, |
| { 1785, 1, 1, 1, 1153, 0 }, |
| { 1947, 1, 1, 1, 1153, 0 }, |
| { 2109, 1, 1, 1, 1153, 0 }, |
| { 2284, 1, 1, 1, 1153, 0 }, |
| { 6, 1, 1, 1, 1153, 0 }, |
| { 264, 1, 1, 1, 1153, 0 }, |
| { 522, 1, 1, 1, 1153, 0 }, |
| { 720, 1, 1, 1, 1153, 0 }, |
| { 910, 1, 1, 1, 1153, 0 }, |
| { 1505, 1, 1, 1, 1153, 0 }, |
| { 1671, 1, 1, 1, 1153, 0 }, |
| { 1833, 1, 1, 1, 1153, 0 }, |
| { 1995, 1, 1, 1, 1153, 0 }, |
| { 2154, 1, 1, 1, 1153, 0 }, |
| { 64, 1, 1, 1, 1153, 0 }, |
| { 322, 1, 1, 1, 1153, 0 }, |
| { 580, 1, 1, 1, 1153, 0 }, |
| { 778, 1, 1, 1, 1153, 0 }, |
| { 968, 1, 1, 1, 1153, 0 }, |
| { 1563, 1, 1, 1, 1153, 0 }, |
| { 1725, 1, 1, 1, 1153, 0 }, |
| { 1887, 1, 1, 1, 1153, 0 }, |
| { 2049, 1, 1, 1, 1153, 0 }, |
| { 2224, 1, 1, 1, 1153, 0 }, |
| { 137, 1, 1, 1, 1153, 0 }, |
| { 395, 1, 1, 1, 1153, 0 }, |
| { 13, 1, 1, 1, 1153, 0 }, |
| { 271, 1, 1, 1, 1153, 0 }, |
| { 529, 1, 1, 1, 1153, 0 }, |
| { 727, 1, 1, 1, 1153, 0 }, |
| { 917, 1, 1, 1, 1153, 0 }, |
| { 1512, 1, 1, 1, 1153, 0 }, |
| { 1678, 1, 1, 1, 1153, 0 }, |
| { 1840, 1, 1, 1, 1153, 0 }, |
| { 2002, 1, 1, 1, 1153, 0 }, |
| { 2161, 1, 1, 1, 1153, 0 }, |
| { 71, 1, 1, 1, 1153, 0 }, |
| { 329, 1, 1, 1, 1153, 0 }, |
| { 587, 1, 1, 1, 1153, 0 }, |
| { 785, 1, 1, 1, 1153, 0 }, |
| { 975, 1, 1, 1, 1153, 0 }, |
| { 1570, 1, 1, 1, 1153, 0 }, |
| { 1732, 1, 1, 1, 1153, 0 }, |
| { 1894, 1, 1, 1, 1153, 0 }, |
| { 2056, 1, 1, 1, 1153, 0 }, |
| { 2231, 1, 1, 1, 1153, 0 }, |
| { 144, 1, 1, 1, 1153, 0 }, |
| { 402, 1, 1, 1, 1153, 0 }, |
| { 20, 1, 1, 1, 1153, 0 }, |
| { 278, 1, 1, 1, 1153, 0 }, |
| { 536, 1, 1, 1, 1153, 0 }, |
| { 734, 1, 1, 1, 1153, 0 }, |
| { 924, 1, 1, 1, 1153, 0 }, |
| { 1519, 1, 1, 1, 1153, 0 }, |
| { 1685, 1, 1, 1, 1153, 0 }, |
| { 1847, 1, 1, 1, 1153, 0 }, |
| { 2009, 1, 1, 1, 1153, 0 }, |
| { 2168, 1, 1, 1, 1153, 0 }, |
| { 78, 1, 1, 1, 1153, 0 }, |
| { 336, 1, 1, 1, 1153, 0 }, |
| { 594, 1, 1, 1, 1153, 0 }, |
| { 792, 1, 1, 1, 1153, 0 }, |
| { 982, 1, 1, 1, 1153, 0 }, |
| { 1577, 1, 1, 1, 1153, 0 }, |
| { 1739, 1, 1, 1, 1153, 0 }, |
| { 1901, 1, 1, 1, 1153, 0 }, |
| { 2063, 1, 1, 1, 1153, 0 }, |
| { 2238, 1, 1, 1, 1153, 0 }, |
| { 151, 1, 1, 1, 1153, 0 }, |
| { 409, 1, 1, 1, 1153, 0 }, |
| { 209, 14, 1, 9, 994, 10 }, |
| { 467, 17, 1, 9, 994, 10 }, |
| { 671, 20, 1, 9, 994, 10 }, |
| { 869, 23, 1, 9, 994, 10 }, |
| { 1468, 26, 1, 9, 994, 10 }, |
| { 1634, 29, 1, 9, 994, 10 }, |
| { 1796, 32, 1, 9, 994, 10 }, |
| { 1958, 35, 1, 9, 994, 10 }, |
| { 2120, 38, 1, 9, 994, 10 }, |
| { 2295, 41, 1, 9, 994, 10 }, |
| { 33, 44, 1, 9, 994, 10 }, |
| { 291, 47, 1, 9, 994, 10 }, |
| { 549, 50, 1, 9, 994, 10 }, |
| { 747, 53, 1, 9, 994, 10 }, |
| { 937, 56, 1, 9, 994, 10 }, |
| { 1532, 59, 1, 9, 994, 10 }, |
| { 124, 1, 148, 1, 2369, 0 }, |
| { 382, 1, 146, 1, 2369, 0 }, |
| { 640, 1, 144, 1, 2369, 0 }, |
| { 838, 1, 142, 1, 2369, 0 }, |
| { 212, 1, 161, 1, 3985, 0 }, |
| { 470, 1, 165, 1, 3985, 0 }, |
| { 674, 1, 165, 1, 3985, 0 }, |
| { 872, 1, 169, 1, 3985, 0 }, |
| { 1471, 1, 169, 1, 3985, 0 }, |
| { 1637, 1, 173, 1, 3985, 0 }, |
| { 1799, 1, 173, 1, 3985, 0 }, |
| { 1961, 1, 177, 1, 3985, 0 }, |
| { 2123, 1, 177, 1, 3985, 0 }, |
| { 2298, 1, 181, 1, 3985, 0 }, |
| { 37, 1, 181, 1, 3985, 0 }, |
| { 295, 1, 185, 1, 3985, 0 }, |
| { 553, 1, 185, 1, 3985, 0 }, |
| { 751, 1, 189, 1, 3985, 0 }, |
| { 941, 1, 189, 1, 3985, 0 }, |
| { 1536, 1, 193, 1, 3985, 0 }, |
| { 1698, 1, 193, 1, 3985, 0 }, |
| { 1860, 1, 197, 1, 3985, 0 }, |
| { 2022, 1, 197, 1, 3985, 0 }, |
| { 2181, 1, 201, 1, 3985, 0 }, |
| { 91, 1, 201, 1, 3985, 0 }, |
| { 349, 1, 205, 1, 3985, 0 }, |
| { 607, 1, 205, 1, 3985, 0 }, |
| { 805, 1, 209, 1, 3985, 0 }, |
| { 995, 1, 209, 1, 3985, 0 }, |
| { 1590, 1, 213, 1, 3985, 0 }, |
| { 1752, 1, 213, 1, 3985, 0 }, |
| { 1914, 1, 217, 1, 3985, 0 }, |
| { 2076, 1, 217, 1, 3985, 0 }, |
| { 2251, 1, 221, 1, 3985, 0 }, |
| { 164, 1, 221, 1, 3985, 0 }, |
| { 422, 1, 225, 1, 3985, 0 }, |
| { 204, 1, 1, 1, 3985, 0 }, |
| { 462, 1, 1, 1, 3985, 0 }, |
| { 666, 1, 1, 1, 3985, 0 }, |
| { 864, 1, 1, 1, 3985, 0 }, |
| { 1463, 1, 1, 1, 3985, 0 }, |
| { 1629, 1, 1, 1, 3985, 0 }, |
| { 1791, 1, 1, 1, 3985, 0 }, |
| { 1953, 1, 1, 1, 3985, 0 }, |
| { 236, 1, 1, 1, 3985, 0 }, |
| { 494, 1, 1, 1, 3985, 0 }, |
| { 695, 1, 1, 1, 3985, 0 }, |
| { 885, 1, 1, 1, 3985, 0 }, |
| { 1480, 1, 1, 1, 3985, 0 }, |
| { 1646, 1, 1, 1, 3985, 0 }, |
| { 1808, 1, 1, 1, 3985, 0 }, |
| { 1970, 1, 1, 1, 3985, 0 }, |
| { 2132, 1, 1, 1, 3985, 0 }, |
| { 2307, 1, 1, 1, 3985, 0 }, |
| { 48, 1, 1, 1, 3985, 0 }, |
| { 306, 1, 1, 1, 3985, 0 }, |
| { 564, 1, 1, 1, 3985, 0 }, |
| { 762, 1, 1, 1, 3985, 0 }, |
| { 952, 1, 1, 1, 3985, 0 }, |
| { 1547, 1, 1, 1, 3985, 0 }, |
| { 1709, 1, 1, 1, 3985, 0 }, |
| { 1871, 1, 1, 1, 3985, 0 }, |
| { 2033, 1, 1, 1, 3985, 0 }, |
| { 2192, 1, 1, 1, 3985, 0 }, |
| { 108, 1, 1, 1, 3985, 0 }, |
| { 366, 1, 1, 1, 3985, 0 }, |
| { 624, 1, 1, 1, 3985, 0 }, |
| { 822, 1, 1, 1, 3985, 0 }, |
| { 1012, 1, 1, 1, 3985, 0 }, |
| { 1607, 1, 1, 1, 3985, 0 }, |
| { 1769, 1, 1, 1, 3985, 0 }, |
| { 1931, 1, 1, 1, 3985, 0 }, |
| { 2093, 1, 1, 1, 3985, 0 }, |
| { 2268, 1, 1, 1, 3985, 0 }, |
| { 181, 1, 1, 1, 3985, 0 }, |
| { 439, 1, 1, 1, 3985, 0 }, |
| { 1439, 136, 1, 0, 1184, 2 }, |
| { 215, 1, 158, 1, 3953, 0 }, |
| { 473, 1, 158, 1, 3953, 0 }, |
| { 677, 1, 158, 1, 3953, 0 }, |
| { 875, 1, 158, 1, 3953, 0 }, |
| { 1474, 1, 158, 1, 3953, 0 }, |
| { 1640, 1, 158, 1, 3953, 0 }, |
| { 1802, 1, 158, 1, 3953, 0 }, |
| { 1964, 1, 158, 1, 3953, 0 }, |
| { 2126, 1, 158, 1, 3953, 0 }, |
| { 2301, 1, 158, 1, 3953, 0 }, |
| { 41, 1, 158, 1, 3953, 0 }, |
| { 299, 1, 158, 1, 3953, 0 }, |
| { 557, 1, 158, 1, 3953, 0 }, |
| { 755, 1, 158, 1, 3953, 0 }, |
| { 945, 1, 158, 1, 3953, 0 }, |
| { 1540, 1, 158, 1, 3953, 0 }, |
| { 1702, 1, 158, 1, 3953, 0 }, |
| { 1864, 1, 158, 1, 3953, 0 }, |
| { 2026, 1, 158, 1, 3953, 0 }, |
| { 2185, 1, 158, 1, 3953, 0 }, |
| { 95, 1, 158, 1, 3953, 0 }, |
| { 353, 1, 158, 1, 3953, 0 }, |
| { 611, 1, 158, 1, 3953, 0 }, |
| { 809, 1, 158, 1, 3953, 0 }, |
| { 999, 1, 158, 1, 3953, 0 }, |
| { 1594, 1, 158, 1, 3953, 0 }, |
| { 1756, 1, 158, 1, 3953, 0 }, |
| { 1918, 1, 158, 1, 3953, 0 }, |
| { 2080, 1, 158, 1, 3953, 0 }, |
| { 2255, 1, 158, 1, 3953, 0 }, |
| { 168, 1, 158, 1, 3953, 0 }, |
| { 426, 1, 158, 1, 3953, 0 }, |
| { 1445, 128, 1, 0, 1216, 2 }, |
| { 217, 1, 233, 1, 1826, 0 }, |
| { 475, 1, 134, 1, 1826, 0 }, |
| { 679, 1, 134, 1, 1826, 0 }, |
| { 877, 1, 134, 1, 1826, 0 }, |
| { 241, 1, 1, 1, 3921, 0 }, |
| { 499, 1, 1, 1, 3921, 0 }, |
| { 700, 1, 1, 1, 3921, 0 }, |
| { 890, 1, 1, 1, 3921, 0 }, |
| { 1485, 1, 1, 1, 3921, 0 }, |
| { 1651, 1, 1, 1, 3921, 0 }, |
| { 1813, 1, 1, 1, 3921, 0 }, |
| { 1975, 1, 1, 1, 3921, 0 }, |
| { 2137, 1, 1, 1, 3921, 0 }, |
| { 2312, 1, 1, 1, 3921, 0 }, |
| { 54, 1, 1, 1, 3921, 0 }, |
| { 312, 1, 1, 1, 3921, 0 }, |
| { 570, 1, 1, 1, 3921, 0 }, |
| { 768, 1, 1, 1, 3921, 0 }, |
| { 958, 1, 1, 1, 3921, 0 }, |
| { 1553, 1, 1, 1, 3921, 0 }, |
| { 1715, 1, 1, 1, 3921, 0 }, |
| { 1877, 1, 1, 1, 3921, 0 }, |
| { 2039, 1, 1, 1, 3921, 0 }, |
| { 2198, 1, 1, 1, 3921, 0 }, |
| { 114, 1, 1, 1, 3921, 0 }, |
| { 372, 1, 1, 1, 3921, 0 }, |
| { 630, 1, 1, 1, 3921, 0 }, |
| { 828, 1, 1, 1, 3921, 0 }, |
| { 1018, 1, 1, 1, 3921, 0 }, |
| { 1613, 1, 1, 1, 3921, 0 }, |
| { 1775, 1, 1, 1, 3921, 0 }, |
| { 1937, 1, 1, 1, 3921, 0 }, |
| { 2099, 1, 1, 1, 3921, 0 }, |
| { 2274, 1, 1, 1, 3921, 0 }, |
| { 187, 1, 1, 1, 3921, 0 }, |
| { 445, 1, 1, 1, 3921, 0 }, |
| { 221, 1, 100, 1, 3921, 0 }, |
| { 479, 1, 100, 1, 3921, 0 }, |
| { 229, 1, 229, 1, 1794, 0 }, |
| { 487, 1, 126, 1, 1794, 0 }, |
| { 688, 1, 126, 1, 1794, 0 }, |
| { 881, 1, 126, 1, 1794, 0 }, |
| { 224, 1, 1, 1, 3889, 0 }, |
| { 482, 1, 1, 1, 3889, 0 }, |
| { 683, 1, 1, 1, 3889, 0 }, |
| { 2115, 1, 1, 1, 3889, 0 }, |
| { 2290, 1, 1, 1, 3889, 0 }, |
| { 27, 1, 1, 1, 3889, 0 }, |
| { 285, 1, 1, 1, 3889, 0 }, |
| { 543, 1, 1, 1, 3889, 0 }, |
| { 741, 1, 1, 1, 3889, 0 }, |
| { 931, 1, 1, 1, 3889, 0 }, |
| { 1526, 1, 1, 1, 3889, 0 }, |
| { 1692, 1, 1, 1, 3889, 0 }, |
| { 1854, 1, 1, 1, 3889, 0 }, |
| { 2016, 1, 1, 1, 3889, 0 }, |
| { 2175, 1, 1, 1, 3889, 0 }, |
| { 85, 1, 1, 1, 3889, 0 }, |
| { 343, 1, 1, 1, 3889, 0 }, |
| { 601, 1, 1, 1, 3889, 0 }, |
| { 799, 1, 1, 1, 3889, 0 }, |
| { 989, 1, 1, 1, 3889, 0 }, |
| { 1584, 1, 1, 1, 3889, 0 }, |
| { 1746, 1, 1, 1, 3889, 0 }, |
| { 1908, 1, 1, 1, 3889, 0 }, |
| { 2070, 1, 1, 1, 3889, 0 }, |
| { 2245, 1, 1, 1, 3889, 0 }, |
| { 158, 1, 1, 1, 3889, 0 }, |
| { 416, 1, 1, 1, 3889, 0 }, |
| { 233, 1, 1, 1, 3889, 0 }, |
| { 491, 1, 1, 1, 3889, 0 }, |
| { 692, 1, 1, 1, 3889, 0 }, |
| { 1425, 124, 1, 0, 1248, 2 }, |
| { 246, 1, 98, 1, 3857, 0 }, |
| { 504, 1, 98, 1, 3857, 0 }, |
| { 705, 1, 98, 1, 3857, 0 }, |
| { 895, 1, 98, 1, 3857, 0 }, |
| { 1490, 1, 98, 1, 3857, 0 }, |
| { 1656, 1, 98, 1, 3857, 0 }, |
| { 1818, 1, 98, 1, 3857, 0 }, |
| { 1980, 1, 98, 1, 3857, 0 }, |
| { 1451, 122, 1, 0, 1280, 2 }, |
| { 249, 1, 96, 1, 3825, 0 }, |
| { 507, 1, 96, 1, 3825, 0 }, |
| { 708, 1, 96, 1, 3825, 0 }, |
| { 898, 1, 96, 1, 3825, 0 }, |
| { 1493, 1, 96, 1, 3825, 0 }, |
| { 1659, 1, 96, 1, 3825, 0 }, |
| { 1821, 1, 96, 1, 3825, 0 }, |
| { 1983, 1, 96, 1, 3825, 0 }, |
| { 2142, 1, 96, 1, 3825, 0 }, |
| { 2317, 1, 96, 1, 3825, 0 }, |
| { 252, 1, 96, 1, 3825, 0 }, |
| { 510, 1, 96, 1, 3825, 0 }, |
| { 255, 92, 1, 8, 1425, 10 }, |
| { 513, 92, 1, 8, 1425, 10 }, |
| { 711, 92, 1, 8, 1425, 10 }, |
| { 901, 92, 1, 8, 1425, 10 }, |
| { 1496, 92, 1, 8, 1425, 10 }, |
| { 1662, 92, 1, 8, 1425, 10 }, |
| { 1824, 92, 1, 8, 1425, 10 }, |
| { 1986, 92, 1, 8, 1425, 10 }, |
| { 2145, 92, 1, 8, 1425, 10 }, |
| { 2320, 92, 1, 8, 1425, 10 }, |
| { 60, 92, 1, 8, 1425, 10 }, |
| { 318, 92, 1, 8, 1425, 10 }, |
| { 576, 92, 1, 8, 1425, 10 }, |
| { 774, 92, 1, 8, 1425, 10 }, |
| { 964, 92, 1, 8, 1425, 10 }, |
| { 1559, 92, 1, 8, 1425, 10 }, |
| { 1721, 92, 1, 8, 1425, 10 }, |
| { 1883, 92, 1, 8, 1425, 10 }, |
| { 2045, 92, 1, 8, 1425, 10 }, |
| { 2204, 92, 1, 8, 1425, 10 }, |
| { 120, 92, 1, 8, 1425, 10 }, |
| { 378, 92, 1, 8, 1425, 10 }, |
| { 636, 92, 1, 8, 1425, 10 }, |
| { 834, 92, 1, 8, 1425, 10 }, |
| { 1024, 92, 1, 8, 1425, 10 }, |
| { 1619, 92, 1, 8, 1425, 10 }, |
| { 1781, 92, 1, 8, 1425, 10 }, |
| { 1943, 92, 1, 8, 1425, 10 }, |
| { 2105, 92, 1, 8, 1425, 10 }, |
| { 2280, 92, 1, 8, 1425, 10 }, |
| { 193, 92, 1, 8, 1425, 10 }, |
| { 451, 92, 1, 8, 1425, 10 }, |
| { 1431, 118, 1, 0, 1921, 2 }, |
| { 1055, 118, 1, 0, 1921, 2 }, |
| { 1133, 118, 1, 0, 1921, 2 }, |
| { 1183, 118, 1, 0, 1921, 2 }, |
| { 1221, 118, 1, 0, 1921, 2 }, |
| { 1061, 130, 1, 12, 656, 10 }, |
| { 1068, 93, 159, 9, 1377, 10 }, |
| { 1139, 93, 159, 9, 1377, 10 }, |
| { 1189, 93, 159, 9, 1377, 10 }, |
| { 1227, 93, 159, 9, 1377, 10 }, |
| { 1259, 93, 159, 9, 1377, 10 }, |
| { 1291, 93, 159, 9, 1377, 10 }, |
| { 1323, 93, 159, 9, 1377, 10 }, |
| { 1355, 93, 159, 9, 1377, 10 }, |
| { 1387, 93, 159, 9, 1377, 10 }, |
| { 1413, 93, 159, 9, 1377, 10 }, |
| { 1034, 93, 159, 9, 1377, 10 }, |
| { 1112, 93, 159, 9, 1377, 10 }, |
| { 1169, 93, 159, 9, 1377, 10 }, |
| { 1207, 93, 159, 9, 1377, 10 }, |
| { 1245, 93, 159, 9, 1377, 10 }, |
| { 1277, 93, 159, 9, 1377, 10 }, |
| { 1309, 93, 159, 9, 1377, 10 }, |
| { 1341, 93, 159, 9, 1377, 10 }, |
| { 1373, 93, 159, 9, 1377, 10 }, |
| { 1399, 93, 159, 9, 1377, 10 }, |
| { 1041, 93, 159, 9, 1377, 10 }, |
| { 1119, 93, 159, 9, 1377, 10 }, |
| { 1176, 93, 159, 9, 1377, 10 }, |
| { 1214, 93, 159, 9, 1377, 10 }, |
| { 1252, 93, 159, 9, 1377, 10 }, |
| { 1284, 93, 159, 9, 1377, 10 }, |
| { 1316, 93, 159, 9, 1377, 10 }, |
| { 1348, 93, 159, 9, 1377, 10 }, |
| { 1380, 93, 159, 9, 1377, 10 }, |
| { 1406, 93, 159, 9, 1377, 10 }, |
| { 1048, 93, 159, 9, 1377, 10 }, |
| { 1126, 93, 159, 9, 1377, 10 }, |
| { 2208, 1, 116, 1, 1120, 0 }, |
| { 1074, 138, 235, 0, 1344, 2 }, |
| { 1081, 150, 1, 0, 2241, 2 }, |
| { 1145, 150, 1, 0, 2241, 2 }, |
| { 1087, 150, 231, 0, 1312, 2 }, |
| { 1094, 154, 1, 0, 2433, 2 }, |
| { 1151, 154, 1, 0, 2433, 2 }, |
| { 1195, 154, 1, 0, 2433, 2 }, |
| { 1233, 154, 1, 0, 2433, 2 }, |
| { 1265, 154, 1, 0, 2433, 2 }, |
| { 1297, 154, 1, 0, 2433, 2 }, |
| { 1329, 154, 1, 0, 2433, 2 }, |
| { 1361, 154, 1, 0, 2433, 2 }, |
| { 1100, 156, 1, 0, 2433, 2 }, |
| { 1157, 156, 1, 0, 2433, 2 }, |
| { 1201, 156, 1, 0, 2433, 2 }, |
| { 1239, 156, 1, 0, 2433, 2 }, |
| { 1271, 156, 1, 0, 2433, 2 }, |
| { 1303, 156, 1, 0, 2433, 2 }, |
| { 1335, 156, 1, 0, 2433, 2 }, |
| { 1367, 156, 1, 0, 2433, 2 }, |
| { 1393, 156, 1, 0, 2433, 2 }, |
| { 1419, 156, 1, 0, 2433, 2 }, |
| { 1106, 156, 1, 0, 2433, 2 }, |
| { 1163, 156, 1, 0, 2433, 2 }, |
| }; |
| |
| extern const MCPhysReg MipsRegUnitRoots[][2] = { |
| { Mips::AT }, |
| { Mips::DSPCCond }, |
| { Mips::DSPCarry }, |
| { Mips::DSPEFI }, |
| { Mips::DSPOutFlag16_19 }, |
| { Mips::DSPOutFlag20 }, |
| { Mips::DSPOutFlag21 }, |
| { Mips::DSPOutFlag22 }, |
| { Mips::DSPOutFlag23 }, |
| { Mips::DSPPos }, |
| { Mips::DSPSCount }, |
| { Mips::FP }, |
| { Mips::GP }, |
| { Mips::MSAAccess }, |
| { Mips::MSACSR }, |
| { Mips::MSAIR }, |
| { Mips::MSAMap }, |
| { Mips::MSAModify }, |
| { Mips::MSARequest }, |
| { Mips::MSASave }, |
| { Mips::MSAUnmap }, |
| { Mips::PC }, |
| { Mips::RA }, |
| { Mips::SP }, |
| { Mips::ZERO }, |
| { Mips::A0 }, |
| { Mips::A1 }, |
| { Mips::A2 }, |
| { Mips::A3 }, |
| { Mips::LO0 }, |
| { Mips::HI0 }, |
| { Mips::LO1 }, |
| { Mips::HI1 }, |
| { Mips::LO2 }, |
| { Mips::HI2 }, |
| { Mips::LO3 }, |
| { Mips::HI3 }, |
| { Mips::COP00 }, |
| { Mips::COP01 }, |
| { Mips::COP02 }, |
| { Mips::COP03 }, |
| { Mips::COP04 }, |
| { Mips::COP05 }, |
| { Mips::COP06 }, |
| { Mips::COP07 }, |
| { Mips::COP08 }, |
| { Mips::COP09 }, |
| { Mips::COP20 }, |
| { Mips::COP21 }, |
| { Mips::COP22 }, |
| { Mips::COP23 }, |
| { Mips::COP24 }, |
| { Mips::COP25 }, |
| { Mips::COP26 }, |
| { Mips::COP27 }, |
| { Mips::COP28 }, |
| { Mips::COP29 }, |
| { Mips::COP30 }, |
| { Mips::COP31 }, |
| { Mips::COP32 }, |
| { Mips::COP33 }, |
| { Mips::COP34 }, |
| { Mips::COP35 }, |
| { Mips::COP36 }, |
| { Mips::COP37 }, |
| { Mips::COP38 }, |
| { Mips::COP39 }, |
| { Mips::COP010 }, |
| { Mips::COP011 }, |
| { Mips::COP012 }, |
| { Mips::COP013 }, |
| { Mips::COP014 }, |
| { Mips::COP015 }, |
| { Mips::COP016 }, |
| { Mips::COP017 }, |
| { Mips::COP018 }, |
| { Mips::COP019 }, |
| { Mips::COP020 }, |
| { Mips::COP021 }, |
| { Mips::COP022 }, |
| { Mips::COP023 }, |
| { Mips::COP024 }, |
| { Mips::COP025 }, |
| { Mips::COP026 }, |
| { Mips::COP027 }, |
| { Mips::COP028 }, |
| { Mips::COP029 }, |
| { Mips::COP030 }, |
| { Mips::COP031 }, |
| { Mips::COP210 }, |
| { Mips::COP211 }, |
| { Mips::COP212 }, |
| { Mips::COP213 }, |
| { Mips::COP214 }, |
| { Mips::COP215 }, |
| { Mips::COP216 }, |
| { Mips::COP217 }, |
| { Mips::COP218 }, |
| { Mips::COP219 }, |
| { Mips::COP220 }, |
| { Mips::COP221 }, |
| { Mips::COP222 }, |
| { Mips::COP223 }, |
| { Mips::COP224 }, |
| { Mips::COP225 }, |
| { Mips::COP226 }, |
| { Mips::COP227 }, |
| { Mips::COP228 }, |
| { Mips::COP229 }, |
| { Mips::COP230 }, |
| { Mips::COP231 }, |
| { Mips::COP310 }, |
| { Mips::COP311 }, |
| { Mips::COP312 }, |
| { Mips::COP313 }, |
| { Mips::COP314 }, |
| { Mips::COP315 }, |
| { Mips::COP316 }, |
| { Mips::COP317 }, |
| { Mips::COP318 }, |
| { Mips::COP319 }, |
| { Mips::COP320 }, |
| { Mips::COP321 }, |
| { Mips::COP322 }, |
| { Mips::COP323 }, |
| { Mips::COP324 }, |
| { Mips::COP325 }, |
| { Mips::COP326 }, |
| { Mips::COP327 }, |
| { Mips::COP328 }, |
| { Mips::COP329 }, |
| { Mips::COP330 }, |
| { Mips::COP331 }, |
| { Mips::F0 }, |
| { Mips::F1 }, |
| { Mips::F2 }, |
| { Mips::F3 }, |
| { Mips::F4 }, |
| { Mips::F5 }, |
| { Mips::F6 }, |
| { Mips::F7 }, |
| { Mips::F8 }, |
| { Mips::F9 }, |
| { Mips::F10 }, |
| { Mips::F11 }, |
| { Mips::F12 }, |
| { Mips::F13 }, |
| { Mips::F14 }, |
| { Mips::F15 }, |
| { Mips::F16 }, |
| { Mips::F17 }, |
| { Mips::F18 }, |
| { Mips::F19 }, |
| { Mips::F20 }, |
| { Mips::F21 }, |
| { Mips::F22 }, |
| { Mips::F23 }, |
| { Mips::F24 }, |
| { Mips::F25 }, |
| { Mips::F26 }, |
| { Mips::F27 }, |
| { Mips::F28 }, |
| { Mips::F29 }, |
| { Mips::F30 }, |
| { Mips::F31 }, |
| { Mips::FCC0 }, |
| { Mips::FCC1 }, |
| { Mips::FCC2 }, |
| { Mips::FCC3 }, |
| { Mips::FCC4 }, |
| { Mips::FCC5 }, |
| { Mips::FCC6 }, |
| { Mips::FCC7 }, |
| { Mips::FCR0 }, |
| { Mips::FCR1 }, |
| { Mips::FCR2 }, |
| { Mips::FCR3 }, |
| { Mips::FCR4 }, |
| { Mips::FCR5 }, |
| { Mips::FCR6 }, |
| { Mips::FCR7 }, |
| { Mips::FCR8 }, |
| { Mips::FCR9 }, |
| { Mips::FCR10 }, |
| { Mips::FCR11 }, |
| { Mips::FCR12 }, |
| { Mips::FCR13 }, |
| { Mips::FCR14 }, |
| { Mips::FCR15 }, |
| { Mips::FCR16 }, |
| { Mips::FCR17 }, |
| { Mips::FCR18 }, |
| { Mips::FCR19 }, |
| { Mips::FCR20 }, |
| { Mips::FCR21 }, |
| { Mips::FCR22 }, |
| { Mips::FCR23 }, |
| { Mips::FCR24 }, |
| { Mips::FCR25 }, |
| { Mips::FCR26 }, |
| { Mips::FCR27 }, |
| { Mips::FCR28 }, |
| { Mips::FCR29 }, |
| { Mips::FCR30 }, |
| { Mips::FCR31 }, |
| { Mips::F_HI0 }, |
| { Mips::F_HI1 }, |
| { Mips::F_HI2 }, |
| { Mips::F_HI3 }, |
| { Mips::F_HI4 }, |
| { Mips::F_HI5 }, |
| { Mips::F_HI6 }, |
| { Mips::F_HI7 }, |
| { Mips::F_HI8 }, |
| { Mips::F_HI9 }, |
| { Mips::F_HI10 }, |
| { Mips::F_HI11 }, |
| { Mips::F_HI12 }, |
| { Mips::F_HI13 }, |
| { Mips::F_HI14 }, |
| { Mips::F_HI15 }, |
| { Mips::F_HI16 }, |
| { Mips::F_HI17 }, |
| { Mips::F_HI18 }, |
| { Mips::F_HI19 }, |
| { Mips::F_HI20 }, |
| { Mips::F_HI21 }, |
| { Mips::F_HI22 }, |
| { Mips::F_HI23 }, |
| { Mips::F_HI24 }, |
| { Mips::F_HI25 }, |
| { Mips::F_HI26 }, |
| { Mips::F_HI27 }, |
| { Mips::F_HI28 }, |
| { Mips::F_HI29 }, |
| { Mips::F_HI30 }, |
| { Mips::F_HI31 }, |
| { Mips::HWR0 }, |
| { Mips::HWR1 }, |
| { Mips::HWR2 }, |
| { Mips::HWR3 }, |
| { Mips::HWR4 }, |
| { Mips::HWR5 }, |
| { Mips::HWR6 }, |
| { Mips::HWR7 }, |
| { Mips::HWR8 }, |
| { Mips::HWR9 }, |
| { Mips::HWR10 }, |
| { Mips::HWR11 }, |
| { Mips::HWR12 }, |
| { Mips::HWR13 }, |
| { Mips::HWR14 }, |
| { Mips::HWR15 }, |
| { Mips::HWR16 }, |
| { Mips::HWR17 }, |
| { Mips::HWR18 }, |
| { Mips::HWR19 }, |
| { Mips::HWR20 }, |
| { Mips::HWR21 }, |
| { Mips::HWR22 }, |
| { Mips::HWR23 }, |
| { Mips::HWR24 }, |
| { Mips::HWR25 }, |
| { Mips::HWR26 }, |
| { Mips::HWR27 }, |
| { Mips::HWR28 }, |
| { Mips::HWR29 }, |
| { Mips::HWR30 }, |
| { Mips::HWR31 }, |
| { Mips::K0 }, |
| { Mips::K1 }, |
| { Mips::MPL0 }, |
| { Mips::MPL1 }, |
| { Mips::MPL2 }, |
| { Mips::MSA8 }, |
| { Mips::MSA9 }, |
| { Mips::MSA10 }, |
| { Mips::MSA11 }, |
| { Mips::MSA12 }, |
| { Mips::MSA13 }, |
| { Mips::MSA14 }, |
| { Mips::MSA15 }, |
| { Mips::MSA16 }, |
| { Mips::MSA17 }, |
| { Mips::MSA18 }, |
| { Mips::MSA19 }, |
| { Mips::MSA20 }, |
| { Mips::MSA21 }, |
| { Mips::MSA22 }, |
| { Mips::MSA23 }, |
| { Mips::MSA24 }, |
| { Mips::MSA25 }, |
| { Mips::MSA26 }, |
| { Mips::MSA27 }, |
| { Mips::MSA28 }, |
| { Mips::MSA29 }, |
| { Mips::MSA30 }, |
| { Mips::MSA31 }, |
| { Mips::P0 }, |
| { Mips::P1 }, |
| { Mips::P2 }, |
| { Mips::S0 }, |
| { Mips::S1 }, |
| { Mips::S2 }, |
| { Mips::S3 }, |
| { Mips::S4 }, |
| { Mips::S5 }, |
| { Mips::S6 }, |
| { Mips::S7 }, |
| { Mips::T0 }, |
| { Mips::T1 }, |
| { Mips::T2 }, |
| { Mips::T3 }, |
| { Mips::T4 }, |
| { Mips::T5 }, |
| { Mips::T6 }, |
| { Mips::T7 }, |
| { Mips::T8 }, |
| { Mips::T9 }, |
| { Mips::V0 }, |
| { Mips::V1 }, |
| }; |
| |
| namespace { // Register classes... |
| // MSA128F16 Register Class... |
| const MCPhysReg MSA128F16[] = { |
| Mips::W0, Mips::W1, Mips::W2, Mips::W3, Mips::W4, Mips::W5, Mips::W6, Mips::W7, Mips::W8, Mips::W9, Mips::W10, Mips::W11, Mips::W12, Mips::W13, Mips::W14, Mips::W15, Mips::W16, Mips::W17, Mips::W18, Mips::W19, Mips::W20, Mips::W21, Mips::W22, Mips::W23, Mips::W24, Mips::W25, Mips::W26, Mips::W27, Mips::W28, Mips::W29, Mips::W30, Mips::W31, |
| }; |
| |
| // MSA128F16 Bit set. |
| const uint8_t MSA128F16Bits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, |
| }; |
| |
| // CCR Register Class... |
| const MCPhysReg CCR[] = { |
| Mips::FCR0, Mips::FCR1, Mips::FCR2, Mips::FCR3, Mips::FCR4, Mips::FCR5, Mips::FCR6, Mips::FCR7, Mips::FCR8, Mips::FCR9, Mips::FCR10, Mips::FCR11, Mips::FCR12, Mips::FCR13, Mips::FCR14, Mips::FCR15, Mips::FCR16, Mips::FCR17, Mips::FCR18, Mips::FCR19, Mips::FCR20, Mips::FCR21, Mips::FCR22, Mips::FCR23, Mips::FCR24, Mips::FCR25, Mips::FCR26, Mips::FCR27, Mips::FCR28, Mips::FCR29, Mips::FCR30, Mips::FCR31, |
| }; |
| |
| // CCR Bit set. |
| const uint8_t CCRBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, |
| }; |
| |
| // COP0 Register Class... |
| const MCPhysReg COP0[] = { |
| Mips::COP00, Mips::COP01, Mips::COP02, Mips::COP03, Mips::COP04, Mips::COP05, Mips::COP06, Mips::COP07, Mips::COP08, Mips::COP09, Mips::COP010, Mips::COP011, Mips::COP012, Mips::COP013, Mips::COP014, Mips::COP015, Mips::COP016, Mips::COP017, Mips::COP018, Mips::COP019, Mips::COP020, Mips::COP021, Mips::COP022, Mips::COP023, Mips::COP024, Mips::COP025, Mips::COP026, Mips::COP027, Mips::COP028, Mips::COP029, Mips::COP030, Mips::COP031, |
| }; |
| |
| // COP0 Bit set. |
| const uint8_t COP0Bits[] = { |
| 0x00, 0x00, 0x00, 0x80, 0xff, 0x01, 0x00, 0xe0, 0xff, 0xff, 0x07, |
| }; |
| |
| // COP2 Register Class... |
| const MCPhysReg COP2[] = { |
| Mips::COP20, Mips::COP21, Mips::COP22, Mips::COP23, Mips::COP24, Mips::COP25, Mips::COP26, Mips::COP27, Mips::COP28, Mips::COP29, Mips::COP210, Mips::COP211, Mips::COP212, Mips::COP213, Mips::COP214, Mips::COP215, Mips::COP216, Mips::COP217, Mips::COP218, Mips::COP219, Mips::COP220, Mips::COP221, Mips::COP222, Mips::COP223, Mips::COP224, Mips::COP225, Mips::COP226, Mips::COP227, Mips::COP228, Mips::COP229, Mips::COP230, Mips::COP231, |
| }; |
| |
| // COP2 Bit set. |
| const uint8_t COP2Bits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x07, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0x01, |
| }; |
| |
| // COP3 Register Class... |
| const MCPhysReg COP3[] = { |
| Mips::COP30, Mips::COP31, Mips::COP32, Mips::COP33, Mips::COP34, Mips::COP35, Mips::COP36, Mips::COP37, Mips::COP38, Mips::COP39, Mips::COP310, Mips::COP311, Mips::COP312, Mips::COP313, Mips::COP314, Mips::COP315, Mips::COP316, Mips::COP317, Mips::COP318, Mips::COP319, Mips::COP320, Mips::COP321, Mips::COP322, Mips::COP323, Mips::COP324, Mips::COP325, Mips::COP326, Mips::COP327, Mips::COP328, Mips::COP329, Mips::COP330, Mips::COP331, |
| }; |
| |
| // COP3 Bit set. |
| const uint8_t COP3Bits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0x7f, |
| }; |
| |
| // DSPR Register Class... |
| const MCPhysReg DSPR[] = { |
| Mips::ZERO, Mips::AT, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::T0, Mips::T1, Mips::T2, Mips::T3, Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7, Mips::T8, Mips::T9, Mips::K0, Mips::K1, Mips::GP, Mips::SP, Mips::FP, Mips::RA, |
| }; |
| |
| // DSPR Bit set. |
| const uint8_t DSPRBits[] = { |
| 0x02, 0x03, 0xf8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0xc0, 0xbf, 0xff, 0x07, |
| }; |
| |
| // FGR32 Register Class... |
| const MCPhysReg FGR32[] = { |
| Mips::F0, Mips::F1, Mips::F2, Mips::F3, Mips::F4, Mips::F5, Mips::F6, Mips::F7, Mips::F8, Mips::F9, Mips::F10, Mips::F11, Mips::F12, Mips::F13, Mips::F14, Mips::F15, Mips::F16, Mips::F17, Mips::F18, Mips::F19, Mips::F20, Mips::F21, Mips::F22, Mips::F23, Mips::F24, Mips::F25, Mips::F26, Mips::F27, Mips::F28, Mips::F29, Mips::F30, Mips::F31, |
| }; |
| |
| // FGR32 Bit set. |
| const uint8_t FGR32Bits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, |
| }; |
| |
| // FGRCC Register Class... |
| const MCPhysReg FGRCC[] = { |
| Mips::F0, Mips::F1, Mips::F2, Mips::F3, Mips::F4, Mips::F5, Mips::F6, Mips::F7, Mips::F8, Mips::F9, Mips::F10, Mips::F11, Mips::F12, Mips::F13, Mips::F14, Mips::F15, Mips::F16, Mips::F17, Mips::F18, Mips::F19, Mips::F20, Mips::F21, Mips::F22, Mips::F23, Mips::F24, Mips::F25, Mips::F26, Mips::F27, Mips::F28, Mips::F29, Mips::F30, Mips::F31, |
| }; |
| |
| // FGRCC Bit set. |
| const uint8_t FGRCCBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, |
| }; |
| |
| // GPR32 Register Class... |
| const MCPhysReg GPR32[] = { |
| Mips::ZERO, Mips::AT, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::T0, Mips::T1, Mips::T2, Mips::T3, Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7, Mips::T8, Mips::T9, Mips::K0, Mips::K1, Mips::GP, Mips::SP, Mips::FP, Mips::RA, |
| }; |
| |
| // GPR32 Bit set. |
| const uint8_t GPR32Bits[] = { |
| 0x02, 0x03, 0xf8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0xc0, 0xbf, 0xff, 0x07, |
| }; |
| |
| // HWRegs Register Class... |
| const MCPhysReg HWRegs[] = { |
| Mips::HWR0, Mips::HWR1, Mips::HWR2, Mips::HWR3, Mips::HWR4, Mips::HWR5, Mips::HWR6, Mips::HWR7, Mips::HWR8, Mips::HWR9, Mips::HWR10, Mips::HWR11, Mips::HWR12, Mips::HWR13, Mips::HWR14, Mips::HWR15, Mips::HWR16, Mips::HWR17, Mips::HWR18, Mips::HWR19, Mips::HWR20, Mips::HWR21, Mips::HWR22, Mips::HWR23, Mips::HWR24, Mips::HWR25, Mips::HWR26, Mips::HWR27, Mips::HWR28, Mips::HWR29, Mips::HWR30, Mips::HWR31, |
| }; |
| |
| // HWRegs Bit set. |
| const uint8_t HWRegsBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, |
| }; |
| |
| // MSACtrl Register Class... |
| const MCPhysReg MSACtrl[] = { |
| Mips::MSAIR, Mips::MSACSR, Mips::MSAAccess, Mips::MSASave, Mips::MSAModify, Mips::MSARequest, Mips::MSAMap, Mips::MSAUnmap, Mips::MSA8, Mips::MSA9, Mips::MSA10, Mips::MSA11, Mips::MSA12, Mips::MSA13, Mips::MSA14, Mips::MSA15, Mips::MSA16, Mips::MSA17, Mips::MSA18, Mips::MSA19, Mips::MSA20, Mips::MSA21, Mips::MSA22, Mips::MSA23, Mips::MSA24, Mips::MSA25, Mips::MSA26, Mips::MSA27, Mips::MSA28, Mips::MSA29, Mips::MSA30, Mips::MSA31, |
| }; |
| |
| // MSACtrl Bit set. |
| const uint8_t MSACtrlBits[] = { |
| 0x00, 0xfc, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0x03, |
| }; |
| |
| // GPR32NONZERO Register Class... |
| const MCPhysReg GPR32NONZERO[] = { |
| Mips::AT, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::T0, Mips::T1, Mips::T2, Mips::T3, Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7, Mips::T8, Mips::T9, Mips::K0, Mips::K1, Mips::GP, Mips::SP, Mips::FP, Mips::RA, |
| }; |
| |
| // GPR32NONZERO Bit set. |
| const uint8_t GPR32NONZEROBits[] = { |
| 0x02, 0x03, 0xd8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0xc0, 0xbf, 0xff, 0x07, |
| }; |
| |
| // CPU16RegsPlusSP Register Class... |
| const MCPhysReg CPU16RegsPlusSP[] = { |
| Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::S0, Mips::S1, Mips::SP, |
| }; |
| |
| // CPU16RegsPlusSP Bit set. |
| const uint8_t CPU16RegsPlusSPBits[] = { |
| 0x00, 0x00, 0xd0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06, |
| }; |
| |
| // CPU16Regs Register Class... |
| const MCPhysReg CPU16Regs[] = { |
| Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::S0, Mips::S1, |
| }; |
| |
| // CPU16Regs Bit set. |
| const uint8_t CPU16RegsBits[] = { |
| 0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06, |
| }; |
| |
| // FCC Register Class... |
| const MCPhysReg FCC[] = { |
| Mips::FCC0, Mips::FCC1, Mips::FCC2, Mips::FCC3, Mips::FCC4, Mips::FCC5, Mips::FCC6, Mips::FCC7, |
| }; |
| |
| // FCC Bit set. |
| const uint8_t FCCBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07, |
| }; |
| |
| // GPRMM16 Register Class... |
| const MCPhysReg GPRMM16[] = { |
| Mips::S0, Mips::S1, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, |
| }; |
| |
| // GPRMM16 Bit set. |
| const uint8_t GPRMM16Bits[] = { |
| 0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06, |
| }; |
| |
| // GPRMM16MoveP Register Class... |
| const MCPhysReg GPRMM16MoveP[] = { |
| Mips::ZERO, Mips::S1, Mips::V0, Mips::V1, Mips::S0, Mips::S2, Mips::S3, Mips::S4, |
| }; |
| |
| // GPRMM16MoveP Bit set. |
| const uint8_t GPRMM16MovePBits[] = { |
| 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x06, |
| }; |
| |
| // GPRMM16Zero Register Class... |
| const MCPhysReg GPRMM16Zero[] = { |
| Mips::ZERO, Mips::S1, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, |
| }; |
| |
| // GPRMM16Zero Bit set. |
| const uint8_t GPRMM16ZeroBits[] = { |
| 0x00, 0x00, 0xe0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06, |
| }; |
| |
| // CPU16Regs_and_GPRMM16Zero Register Class... |
| const MCPhysReg CPU16Regs_and_GPRMM16Zero[] = { |
| Mips::S1, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, |
| }; |
| |
| // CPU16Regs_and_GPRMM16Zero Bit set. |
| const uint8_t CPU16Regs_and_GPRMM16ZeroBits[] = { |
| 0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06, |
| }; |
| |
| // GPR32NONZERO_and_GPRMM16MoveP Register Class... |
| const MCPhysReg GPR32NONZERO_and_GPRMM16MoveP[] = { |
| Mips::S1, Mips::V0, Mips::V1, Mips::S0, Mips::S2, Mips::S3, Mips::S4, |
| }; |
| |
| // GPR32NONZERO_and_GPRMM16MoveP Bit set. |
| const uint8_t GPR32NONZERO_and_GPRMM16MovePBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x06, |
| }; |
| |
| // GPRMM16MovePPairSecond Register Class... |
| const MCPhysReg GPRMM16MovePPairSecond[] = { |
| Mips::A1, Mips::A2, Mips::A3, Mips::S5, Mips::S6, |
| }; |
| |
| // GPRMM16MovePPairSecond Bit set. |
| const uint8_t GPRMM16MovePPairSecondBits[] = { |
| 0x00, 0x00, 0x80, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, |
| }; |
| |
| // CPU16Regs_and_GPRMM16MoveP Register Class... |
| const MCPhysReg CPU16Regs_and_GPRMM16MoveP[] = { |
| Mips::S1, Mips::V0, Mips::V1, Mips::S0, |
| }; |
| |
| // CPU16Regs_and_GPRMM16MoveP Bit set. |
| const uint8_t CPU16Regs_and_GPRMM16MovePBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06, |
| }; |
| |
| // GPRMM16MoveP_and_GPRMM16Zero Register Class... |
| const MCPhysReg GPRMM16MoveP_and_GPRMM16Zero[] = { |
| Mips::ZERO, Mips::S1, Mips::V0, Mips::V1, |
| }; |
| |
| // GPRMM16MoveP_and_GPRMM16Zero Bit set. |
| const uint8_t GPRMM16MoveP_and_GPRMM16ZeroBits[] = { |
| 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06, |
| }; |
| |
| // HI32DSP Register Class... |
| const MCPhysReg HI32DSP[] = { |
| Mips::HI0, Mips::HI1, Mips::HI2, Mips::HI3, |
|
