| /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
| |* *| |
| |* Target Instruction Enum Values and Descriptors *| |
| |* *| |
| |* Automatically generated file, do not edit! *| |
| |* *| |
| \*===----------------------------------------------------------------------===*/ |
| |
| #ifdef GET_INSTRINFO_ENUM |
| #undef GET_INSTRINFO_ENUM |
| namespace llvm { |
| |
| namespace Mips { |
| enum { |
| PHI = 0, |
| INLINEASM = 1, |
| INLINEASM_BR = 2, |
| CFI_INSTRUCTION = 3, |
| EH_LABEL = 4, |
| GC_LABEL = 5, |
| ANNOTATION_LABEL = 6, |
| KILL = 7, |
| EXTRACT_SUBREG = 8, |
| INSERT_SUBREG = 9, |
| IMPLICIT_DEF = 10, |
| SUBREG_TO_REG = 11, |
| COPY_TO_REGCLASS = 12, |
| DBG_VALUE = 13, |
| DBG_VALUE_LIST = 14, |
| DBG_INSTR_REF = 15, |
| DBG_PHI = 16, |
| DBG_LABEL = 17, |
| REG_SEQUENCE = 18, |
| COPY = 19, |
| BUNDLE = 20, |
| LIFETIME_START = 21, |
| LIFETIME_END = 22, |
| PSEUDO_PROBE = 23, |
| ARITH_FENCE = 24, |
| STACKMAP = 25, |
| FENTRY_CALL = 26, |
| PATCHPOINT = 27, |
| LOAD_STACK_GUARD = 28, |
| PREALLOCATED_SETUP = 29, |
| PREALLOCATED_ARG = 30, |
| STATEPOINT = 31, |
| LOCAL_ESCAPE = 32, |
| FAULTING_OP = 33, |
| PATCHABLE_OP = 34, |
| PATCHABLE_FUNCTION_ENTER = 35, |
| PATCHABLE_RET = 36, |
| PATCHABLE_FUNCTION_EXIT = 37, |
| PATCHABLE_TAIL_CALL = 38, |
| PATCHABLE_EVENT_CALL = 39, |
| PATCHABLE_TYPED_EVENT_CALL = 40, |
| ICALL_BRANCH_FUNNEL = 41, |
| MEMBARRIER = 42, |
| G_ASSERT_SEXT = 43, |
| G_ASSERT_ZEXT = 44, |
| G_ASSERT_ALIGN = 45, |
| G_ADD = 46, |
| G_SUB = 47, |
| G_MUL = 48, |
| G_SDIV = 49, |
| G_UDIV = 50, |
| G_SREM = 51, |
| G_UREM = 52, |
| G_SDIVREM = 53, |
| G_UDIVREM = 54, |
| G_AND = 55, |
| G_OR = 56, |
| G_XOR = 57, |
| G_IMPLICIT_DEF = 58, |
| G_PHI = 59, |
| G_FRAME_INDEX = 60, |
| G_GLOBAL_VALUE = 61, |
| G_EXTRACT = 62, |
| G_UNMERGE_VALUES = 63, |
| G_INSERT = 64, |
| G_MERGE_VALUES = 65, |
| G_BUILD_VECTOR = 66, |
| G_BUILD_VECTOR_TRUNC = 67, |
| G_CONCAT_VECTORS = 68, |
| G_PTRTOINT = 69, |
| G_INTTOPTR = 70, |
| G_BITCAST = 71, |
| G_FREEZE = 72, |
| G_INTRINSIC_FPTRUNC_ROUND = 73, |
| G_INTRINSIC_TRUNC = 74, |
| G_INTRINSIC_ROUND = 75, |
| G_INTRINSIC_LRINT = 76, |
| G_INTRINSIC_ROUNDEVEN = 77, |
| G_READCYCLECOUNTER = 78, |
| G_LOAD = 79, |
| G_SEXTLOAD = 80, |
| G_ZEXTLOAD = 81, |
| G_INDEXED_LOAD = 82, |
| G_INDEXED_SEXTLOAD = 83, |
| G_INDEXED_ZEXTLOAD = 84, |
| G_STORE = 85, |
| G_INDEXED_STORE = 86, |
| G_ATOMIC_CMPXCHG_WITH_SUCCESS = 87, |
| G_ATOMIC_CMPXCHG = 88, |
| G_ATOMICRMW_XCHG = 89, |
| G_ATOMICRMW_ADD = 90, |
| G_ATOMICRMW_SUB = 91, |
| G_ATOMICRMW_AND = 92, |
| G_ATOMICRMW_NAND = 93, |
| G_ATOMICRMW_OR = 94, |
| G_ATOMICRMW_XOR = 95, |
| G_ATOMICRMW_MAX = 96, |
| G_ATOMICRMW_MIN = 97, |
| G_ATOMICRMW_UMAX = 98, |
| G_ATOMICRMW_UMIN = 99, |
| G_ATOMICRMW_FADD = 100, |
| G_ATOMICRMW_FSUB = 101, |
| G_ATOMICRMW_FMAX = 102, |
| G_ATOMICRMW_FMIN = 103, |
| G_ATOMICRMW_UINC_WRAP = 104, |
| G_ATOMICRMW_UDEC_WRAP = 105, |
| G_FENCE = 106, |
| G_BRCOND = 107, |
| G_BRINDIRECT = 108, |
| G_INVOKE_REGION_START = 109, |
| G_INTRINSIC = 110, |
| G_INTRINSIC_W_SIDE_EFFECTS = 111, |
| G_ANYEXT = 112, |
| G_TRUNC = 113, |
| G_CONSTANT = 114, |
| G_FCONSTANT = 115, |
| G_VASTART = 116, |
| G_VAARG = 117, |
| G_SEXT = 118, |
| G_SEXT_INREG = 119, |
| G_ZEXT = 120, |
| G_SHL = 121, |
| G_LSHR = 122, |
| G_ASHR = 123, |
| G_FSHL = 124, |
| G_FSHR = 125, |
| G_ROTR = 126, |
| G_ROTL = 127, |
| G_ICMP = 128, |
| G_FCMP = 129, |
| G_SELECT = 130, |
| G_UADDO = 131, |
| G_UADDE = 132, |
| G_USUBO = 133, |
| G_USUBE = 134, |
| G_SADDO = 135, |
| G_SADDE = 136, |
| G_SSUBO = 137, |
| G_SSUBE = 138, |
| G_UMULO = 139, |
| G_SMULO = 140, |
| G_UMULH = 141, |
| G_SMULH = 142, |
| G_UADDSAT = 143, |
| G_SADDSAT = 144, |
| G_USUBSAT = 145, |
| G_SSUBSAT = 146, |
| G_USHLSAT = 147, |
| G_SSHLSAT = 148, |
| G_SMULFIX = 149, |
| G_UMULFIX = 150, |
| G_SMULFIXSAT = 151, |
| G_UMULFIXSAT = 152, |
| G_SDIVFIX = 153, |
| G_UDIVFIX = 154, |
| G_SDIVFIXSAT = 155, |
| G_UDIVFIXSAT = 156, |
| G_FADD = 157, |
| G_FSUB = 158, |
| G_FMUL = 159, |
| G_FMA = 160, |
| G_FMAD = 161, |
| G_FDIV = 162, |
| G_FREM = 163, |
| G_FPOW = 164, |
| G_FPOWI = 165, |
| G_FEXP = 166, |
| G_FEXP2 = 167, |
| G_FLOG = 168, |
| G_FLOG2 = 169, |
| G_FLOG10 = 170, |
| G_FNEG = 171, |
| G_FPEXT = 172, |
| G_FPTRUNC = 173, |
| G_FPTOSI = 174, |
| G_FPTOUI = 175, |
| G_SITOFP = 176, |
| G_UITOFP = 177, |
| G_FABS = 178, |
| G_FCOPYSIGN = 179, |
| G_IS_FPCLASS = 180, |
| G_FCANONICALIZE = 181, |
| G_FMINNUM = 182, |
| G_FMAXNUM = 183, |
| G_FMINNUM_IEEE = 184, |
| G_FMAXNUM_IEEE = 185, |
| G_FMINIMUM = 186, |
| G_FMAXIMUM = 187, |
| G_PTR_ADD = 188, |
| G_PTRMASK = 189, |
| G_SMIN = 190, |
| G_SMAX = 191, |
| G_UMIN = 192, |
| G_UMAX = 193, |
| G_ABS = 194, |
| G_LROUND = 195, |
| G_LLROUND = 196, |
| G_BR = 197, |
| G_BRJT = 198, |
| G_INSERT_VECTOR_ELT = 199, |
| G_EXTRACT_VECTOR_ELT = 200, |
| G_SHUFFLE_VECTOR = 201, |
| G_CTTZ = 202, |
| G_CTTZ_ZERO_UNDEF = 203, |
| G_CTLZ = 204, |
| G_CTLZ_ZERO_UNDEF = 205, |
| G_CTPOP = 206, |
| G_BSWAP = 207, |
| G_BITREVERSE = 208, |
| G_FCEIL = 209, |
| G_FCOS = 210, |
| G_FSIN = 211, |
| G_FSQRT = 212, |
| G_FFLOOR = 213, |
| G_FRINT = 214, |
| G_FNEARBYINT = 215, |
| G_ADDRSPACE_CAST = 216, |
| G_BLOCK_ADDR = 217, |
| G_JUMP_TABLE = 218, |
| G_DYN_STACKALLOC = 219, |
| G_STRICT_FADD = 220, |
| G_STRICT_FSUB = 221, |
| G_STRICT_FMUL = 222, |
| G_STRICT_FDIV = 223, |
| G_STRICT_FREM = 224, |
| G_STRICT_FMA = 225, |
| G_STRICT_FSQRT = 226, |
| G_READ_REGISTER = 227, |
| G_WRITE_REGISTER = 228, |
| G_MEMCPY = 229, |
| G_MEMCPY_INLINE = 230, |
| G_MEMMOVE = 231, |
| G_MEMSET = 232, |
| G_BZERO = 233, |
| G_VECREDUCE_SEQ_FADD = 234, |
| G_VECREDUCE_SEQ_FMUL = 235, |
| G_VECREDUCE_FADD = 236, |
| G_VECREDUCE_FMUL = 237, |
| G_VECREDUCE_FMAX = 238, |
| G_VECREDUCE_FMIN = 239, |
| G_VECREDUCE_ADD = 240, |
| G_VECREDUCE_MUL = 241, |
| G_VECREDUCE_AND = 242, |
| G_VECREDUCE_OR = 243, |
| G_VECREDUCE_XOR = 244, |
| G_VECREDUCE_SMAX = 245, |
| G_VECREDUCE_SMIN = 246, |
| G_VECREDUCE_UMAX = 247, |
| G_VECREDUCE_UMIN = 248, |
| G_SBFX = 249, |
| G_UBFX = 250, |
| ABSMacro = 251, |
| ADJCALLSTACKDOWN = 252, |
| ADJCALLSTACKUP = 253, |
| AND_V_D_PSEUDO = 254, |
| AND_V_H_PSEUDO = 255, |
| AND_V_W_PSEUDO = 256, |
| ATOMIC_CMP_SWAP_I16 = 257, |
| ATOMIC_CMP_SWAP_I16_POSTRA = 258, |
| ATOMIC_CMP_SWAP_I32 = 259, |
| ATOMIC_CMP_SWAP_I32_POSTRA = 260, |
| ATOMIC_CMP_SWAP_I64 = 261, |
| ATOMIC_CMP_SWAP_I64_POSTRA = 262, |
| ATOMIC_CMP_SWAP_I8 = 263, |
| ATOMIC_CMP_SWAP_I8_POSTRA = 264, |
| ATOMIC_LOAD_ADD_I16 = 265, |
| ATOMIC_LOAD_ADD_I16_POSTRA = 266, |
| ATOMIC_LOAD_ADD_I32 = 267, |
| ATOMIC_LOAD_ADD_I32_POSTRA = 268, |
| ATOMIC_LOAD_ADD_I64 = 269, |
| ATOMIC_LOAD_ADD_I64_POSTRA = 270, |
| ATOMIC_LOAD_ADD_I8 = 271, |
| ATOMIC_LOAD_ADD_I8_POSTRA = 272, |
| ATOMIC_LOAD_AND_I16 = 273, |
| ATOMIC_LOAD_AND_I16_POSTRA = 274, |
| ATOMIC_LOAD_AND_I32 = 275, |
| ATOMIC_LOAD_AND_I32_POSTRA = 276, |
| ATOMIC_LOAD_AND_I64 = 277, |
| ATOMIC_LOAD_AND_I64_POSTRA = 278, |
| ATOMIC_LOAD_AND_I8 = 279, |
| ATOMIC_LOAD_AND_I8_POSTRA = 280, |
| ATOMIC_LOAD_MAX_I16 = 281, |
| ATOMIC_LOAD_MAX_I16_POSTRA = 282, |
| ATOMIC_LOAD_MAX_I32 = 283, |
| ATOMIC_LOAD_MAX_I32_POSTRA = 284, |
| ATOMIC_LOAD_MAX_I64 = 285, |
| ATOMIC_LOAD_MAX_I64_POSTRA = 286, |
| ATOMIC_LOAD_MAX_I8 = 287, |
| ATOMIC_LOAD_MAX_I8_POSTRA = 288, |
| ATOMIC_LOAD_MIN_I16 = 289, |
| ATOMIC_LOAD_MIN_I16_POSTRA = 290, |
| ATOMIC_LOAD_MIN_I32 = 291, |
| ATOMIC_LOAD_MIN_I32_POSTRA = 292, |
| ATOMIC_LOAD_MIN_I64 = 293, |
| ATOMIC_LOAD_MIN_I64_POSTRA = 294, |
| ATOMIC_LOAD_MIN_I8 = 295, |
| ATOMIC_LOAD_MIN_I8_POSTRA = 296, |
| ATOMIC_LOAD_NAND_I16 = 297, |
| ATOMIC_LOAD_NAND_I16_POSTRA = 298, |
| ATOMIC_LOAD_NAND_I32 = 299, |
| ATOMIC_LOAD_NAND_I32_POSTRA = 300, |
| ATOMIC_LOAD_NAND_I64 = 301, |
| ATOMIC_LOAD_NAND_I64_POSTRA = 302, |
| ATOMIC_LOAD_NAND_I8 = 303, |
| ATOMIC_LOAD_NAND_I8_POSTRA = 304, |
| ATOMIC_LOAD_OR_I16 = 305, |
| ATOMIC_LOAD_OR_I16_POSTRA = 306, |
| ATOMIC_LOAD_OR_I32 = 307, |
| ATOMIC_LOAD_OR_I32_POSTRA = 308, |
| ATOMIC_LOAD_OR_I64 = 309, |
| ATOMIC_LOAD_OR_I64_POSTRA = 310, |
| ATOMIC_LOAD_OR_I8 = 311, |
| ATOMIC_LOAD_OR_I8_POSTRA = 312, |
| ATOMIC_LOAD_SUB_I16 = 313, |
| ATOMIC_LOAD_SUB_I16_POSTRA = 314, |
| ATOMIC_LOAD_SUB_I32 = 315, |
| ATOMIC_LOAD_SUB_I32_POSTRA = 316, |
| ATOMIC_LOAD_SUB_I64 = 317, |
| ATOMIC_LOAD_SUB_I64_POSTRA = 318, |
| ATOMIC_LOAD_SUB_I8 = 319, |
| ATOMIC_LOAD_SUB_I8_POSTRA = 320, |
| ATOMIC_LOAD_UMAX_I16 = 321, |
| ATOMIC_LOAD_UMAX_I16_POSTRA = 322, |
| ATOMIC_LOAD_UMAX_I32 = 323, |
| ATOMIC_LOAD_UMAX_I32_POSTRA = 324, |
| ATOMIC_LOAD_UMAX_I64 = 325, |
| ATOMIC_LOAD_UMAX_I64_POSTRA = 326, |
| ATOMIC_LOAD_UMAX_I8 = 327, |
| ATOMIC_LOAD_UMAX_I8_POSTRA = 328, |
| ATOMIC_LOAD_UMIN_I16 = 329, |
| ATOMIC_LOAD_UMIN_I16_POSTRA = 330, |
| ATOMIC_LOAD_UMIN_I32 = 331, |
| ATOMIC_LOAD_UMIN_I32_POSTRA = 332, |
| ATOMIC_LOAD_UMIN_I64 = 333, |
| ATOMIC_LOAD_UMIN_I64_POSTRA = 334, |
| ATOMIC_LOAD_UMIN_I8 = 335, |
| ATOMIC_LOAD_UMIN_I8_POSTRA = 336, |
| ATOMIC_LOAD_XOR_I16 = 337, |
| ATOMIC_LOAD_XOR_I16_POSTRA = 338, |
| ATOMIC_LOAD_XOR_I32 = 339, |
| ATOMIC_LOAD_XOR_I32_POSTRA = 340, |
| ATOMIC_LOAD_XOR_I64 = 341, |
| ATOMIC_LOAD_XOR_I64_POSTRA = 342, |
| ATOMIC_LOAD_XOR_I8 = 343, |
| ATOMIC_LOAD_XOR_I8_POSTRA = 344, |
| ATOMIC_SWAP_I16 = 345, |
| ATOMIC_SWAP_I16_POSTRA = 346, |
| ATOMIC_SWAP_I32 = 347, |
| ATOMIC_SWAP_I32_POSTRA = 348, |
| ATOMIC_SWAP_I64 = 349, |
| ATOMIC_SWAP_I64_POSTRA = 350, |
| ATOMIC_SWAP_I8 = 351, |
| ATOMIC_SWAP_I8_POSTRA = 352, |
| B = 353, |
| BAL_BR = 354, |
| BAL_BR_MM = 355, |
| BEQLImmMacro = 356, |
| BGE = 357, |
| BGEImmMacro = 358, |
| BGEL = 359, |
| BGELImmMacro = 360, |
| BGEU = 361, |
| BGEUImmMacro = 362, |
| BGEUL = 363, |
| BGEULImmMacro = 364, |
| BGT = 365, |
| BGTImmMacro = 366, |
| BGTL = 367, |
| BGTLImmMacro = 368, |
| BGTU = 369, |
| BGTUImmMacro = 370, |
| BGTUL = 371, |
| BGTULImmMacro = 372, |
| BLE = 373, |
| BLEImmMacro = 374, |
| BLEL = 375, |
| BLELImmMacro = 376, |
| BLEU = 377, |
| BLEUImmMacro = 378, |
| BLEUL = 379, |
| BLEULImmMacro = 380, |
| BLT = 381, |
| BLTImmMacro = 382, |
| BLTL = 383, |
| BLTLImmMacro = 384, |
| BLTU = 385, |
| BLTUImmMacro = 386, |
| BLTUL = 387, |
| BLTULImmMacro = 388, |
| BNELImmMacro = 389, |
| BPOSGE32_PSEUDO = 390, |
| BSEL_D_PSEUDO = 391, |
| BSEL_FD_PSEUDO = 392, |
| BSEL_FW_PSEUDO = 393, |
| BSEL_H_PSEUDO = 394, |
| BSEL_W_PSEUDO = 395, |
| B_MM = 396, |
| B_MMR6_Pseudo = 397, |
| B_MM_Pseudo = 398, |
| BeqImm = 399, |
| BneImm = 400, |
| BteqzT8CmpX16 = 401, |
| BteqzT8CmpiX16 = 402, |
| BteqzT8SltX16 = 403, |
| BteqzT8SltiX16 = 404, |
| BteqzT8SltiuX16 = 405, |
| BteqzT8SltuX16 = 406, |
| BtnezT8CmpX16 = 407, |
| BtnezT8CmpiX16 = 408, |
| BtnezT8SltX16 = 409, |
| BtnezT8SltiX16 = 410, |
| BtnezT8SltiuX16 = 411, |
| BtnezT8SltuX16 = 412, |
| BuildPairF64 = 413, |
| BuildPairF64_64 = 414, |
| CFTC1 = 415, |
| CONSTPOOL_ENTRY = 416, |
| COPY_FD_PSEUDO = 417, |
| COPY_FW_PSEUDO = 418, |
| CTTC1 = 419, |
| Constant32 = 420, |
| DMULImmMacro = 421, |
| DMULMacro = 422, |
| DMULOMacro = 423, |
| DMULOUMacro = 424, |
| DROL = 425, |
| DROLImm = 426, |
| DROR = 427, |
| DRORImm = 428, |
| DSDivIMacro = 429, |
| DSDivMacro = 430, |
| DSRemIMacro = 431, |
| DSRemMacro = 432, |
| DUDivIMacro = 433, |
| DUDivMacro = 434, |
| DURemIMacro = 435, |
| DURemMacro = 436, |
| ERet = 437, |
| ExtractElementF64 = 438, |
| ExtractElementF64_64 = 439, |
| FABS_D = 440, |
| FABS_W = 441, |
| FEXP2_D_1_PSEUDO = 442, |
| FEXP2_W_1_PSEUDO = 443, |
| FILL_FD_PSEUDO = 444, |
| FILL_FW_PSEUDO = 445, |
| GotPrologue16 = 446, |
| INSERT_B_VIDX64_PSEUDO = 447, |
| INSERT_B_VIDX_PSEUDO = 448, |
| INSERT_D_VIDX64_PSEUDO = 449, |
| INSERT_D_VIDX_PSEUDO = 450, |
| INSERT_FD_PSEUDO = 451, |
| INSERT_FD_VIDX64_PSEUDO = 452, |
| INSERT_FD_VIDX_PSEUDO = 453, |
| INSERT_FW_PSEUDO = 454, |
| INSERT_FW_VIDX64_PSEUDO = 455, |
| INSERT_FW_VIDX_PSEUDO = 456, |
| INSERT_H_VIDX64_PSEUDO = 457, |
| INSERT_H_VIDX_PSEUDO = 458, |
| INSERT_W_VIDX64_PSEUDO = 459, |
| INSERT_W_VIDX_PSEUDO = 460, |
| JALR64Pseudo = 461, |
| JALRHB64Pseudo = 462, |
| JALRHBPseudo = 463, |
| JALRPseudo = 464, |
| JAL_MMR6 = 465, |
| JalOneReg = 466, |
| JalTwoReg = 467, |
| LDMacro = 468, |
| LDR_D = 469, |
| LDR_W = 470, |
| LD_F16 = 471, |
| LOAD_ACC128 = 472, |
| LOAD_ACC64 = 473, |
| LOAD_ACC64DSP = 474, |
| LOAD_CCOND_DSP = 475, |
| LONG_BRANCH_ADDiu = 476, |
| LONG_BRANCH_ADDiu2Op = 477, |
| LONG_BRANCH_DADDiu = 478, |
| LONG_BRANCH_DADDiu2Op = 479, |
| LONG_BRANCH_LUi = 480, |
| LONG_BRANCH_LUi2Op = 481, |
| LONG_BRANCH_LUi2Op_64 = 482, |
| LWM_MM = 483, |
| LoadAddrImm32 = 484, |
| LoadAddrImm64 = 485, |
| LoadAddrReg32 = 486, |
| LoadAddrReg64 = 487, |
| LoadImm32 = 488, |
| LoadImm64 = 489, |
| LoadImmDoubleFGR = 490, |
| LoadImmDoubleFGR_32 = 491, |
| LoadImmDoubleGPR = 492, |
| LoadImmSingleFGR = 493, |
| LoadImmSingleGPR = 494, |
| LwConstant32 = 495, |
| MFTACX = 496, |
| MFTC0 = 497, |
| MFTC1 = 498, |
| MFTDSP = 499, |
| MFTGPR = 500, |
| MFTHC1 = 501, |
| MFTHI = 502, |
| MFTLO = 503, |
| MIPSeh_return32 = 504, |
| MIPSeh_return64 = 505, |
| MSA_FP_EXTEND_D_PSEUDO = 506, |
| MSA_FP_EXTEND_W_PSEUDO = 507, |
| MSA_FP_ROUND_D_PSEUDO = 508, |
| MSA_FP_ROUND_W_PSEUDO = 509, |
| MTTACX = 510, |
| MTTC0 = 511, |
| MTTC1 = 512, |
| MTTDSP = 513, |
| MTTGPR = 514, |
| MTTHC1 = 515, |
| MTTHI = 516, |
| MTTLO = 517, |
| MULImmMacro = 518, |
| MULOMacro = 519, |
| MULOUMacro = 520, |
| MultRxRy16 = 521, |
| MultRxRyRz16 = 522, |
| MultuRxRy16 = 523, |
| MultuRxRyRz16 = 524, |
| NOP = 525, |
| NORImm = 526, |
| NORImm64 = 527, |
| NOR_V_D_PSEUDO = 528, |
| NOR_V_H_PSEUDO = 529, |
| NOR_V_W_PSEUDO = 530, |
| OR_V_D_PSEUDO = 531, |
| OR_V_H_PSEUDO = 532, |
| OR_V_W_PSEUDO = 533, |
| PseudoCMPU_EQ_QB = 534, |
| PseudoCMPU_LE_QB = 535, |
| PseudoCMPU_LT_QB = 536, |
| PseudoCMP_EQ_PH = 537, |
| PseudoCMP_LE_PH = 538, |
| PseudoCMP_LT_PH = 539, |
| PseudoCVT_D32_W = 540, |
| PseudoCVT_D64_L = 541, |
| PseudoCVT_D64_W = 542, |
| PseudoCVT_S_L = 543, |
| PseudoCVT_S_W = 544, |
| PseudoDMULT = 545, |
| PseudoDMULTu = 546, |
| PseudoDSDIV = 547, |
| PseudoDUDIV = 548, |
| PseudoD_SELECT_I = 549, |
| PseudoD_SELECT_I64 = 550, |
| PseudoIndirectBranch = 551, |
| PseudoIndirectBranch64 = 552, |
| PseudoIndirectBranch64R6 = 553, |
| PseudoIndirectBranchR6 = 554, |
| PseudoIndirectBranch_MM = 555, |
| PseudoIndirectBranch_MMR6 = 556, |
| PseudoIndirectHazardBranch = 557, |
| PseudoIndirectHazardBranch64 = 558, |
| PseudoIndrectHazardBranch64R6 = 559, |
| PseudoIndrectHazardBranchR6 = 560, |
| PseudoMADD = 561, |
| PseudoMADDU = 562, |
| PseudoMADDU_MM = 563, |
| PseudoMADD_MM = 564, |
| PseudoMFHI = 565, |
| PseudoMFHI64 = 566, |
| PseudoMFHI_MM = 567, |
| PseudoMFLO = 568, |
| PseudoMFLO64 = 569, |
| PseudoMFLO_MM = 570, |
| PseudoMSUB = 571, |
| PseudoMSUBU = 572, |
| PseudoMSUBU_MM = 573, |
| PseudoMSUB_MM = 574, |
| PseudoMTLOHI = 575, |
| PseudoMTLOHI64 = 576, |
| PseudoMTLOHI_DSP = 577, |
| PseudoMTLOHI_MM = 578, |
| PseudoMULT = 579, |
| PseudoMULT_MM = 580, |
| PseudoMULTu = 581, |
| PseudoMULTu_MM = 582, |
| PseudoPICK_PH = 583, |
| PseudoPICK_QB = 584, |
| PseudoReturn = 585, |
| PseudoReturn64 = 586, |
| PseudoSDIV = 587, |
| PseudoSELECTFP_F_D32 = 588, |
| PseudoSELECTFP_F_D64 = 589, |
| PseudoSELECTFP_F_I = 590, |
| PseudoSELECTFP_F_I64 = 591, |
| PseudoSELECTFP_F_S = 592, |
| PseudoSELECTFP_T_D32 = 593, |
| PseudoSELECTFP_T_D64 = 594, |
| PseudoSELECTFP_T_I = 595, |
| PseudoSELECTFP_T_I64 = 596, |
| PseudoSELECTFP_T_S = 597, |
| PseudoSELECT_D32 = 598, |
| PseudoSELECT_D64 = 599, |
| PseudoSELECT_I = 600, |
| PseudoSELECT_I64 = 601, |
| PseudoSELECT_S = 602, |
| PseudoTRUNC_W_D = 603, |
| PseudoTRUNC_W_D32 = 604, |
| PseudoTRUNC_W_S = 605, |
| PseudoUDIV = 606, |
| ROL = 607, |
| ROLImm = 608, |
| ROR = 609, |
| RORImm = 610, |
| RetRA = 611, |
| RetRA16 = 612, |
| SDC1_M1 = 613, |
| SDIV_MM_Pseudo = 614, |
| SDMacro = 615, |
| SDivIMacro = 616, |
| SDivMacro = 617, |
| SEQIMacro = 618, |
| SEQMacro = 619, |
| SGE = 620, |
| SGEImm = 621, |
| SGEImm64 = 622, |
| SGEU = 623, |
| SGEUImm = 624, |
| SGEUImm64 = 625, |
| SGTImm = 626, |
| SGTImm64 = 627, |
| SGTUImm = 628, |
| SGTUImm64 = 629, |
| SLE = 630, |
| SLEImm = 631, |
| SLEImm64 = 632, |
| SLEU = 633, |
| SLEUImm = 634, |
| SLEUImm64 = 635, |
| SLTImm64 = 636, |
| SLTUImm64 = 637, |
| SNEIMacro = 638, |
| SNEMacro = 639, |
| SNZ_B_PSEUDO = 640, |
| SNZ_D_PSEUDO = 641, |
| SNZ_H_PSEUDO = 642, |
| SNZ_V_PSEUDO = 643, |
| SNZ_W_PSEUDO = 644, |
| SRemIMacro = 645, |
| SRemMacro = 646, |
| STORE_ACC128 = 647, |
| STORE_ACC64 = 648, |
| STORE_ACC64DSP = 649, |
| STORE_CCOND_DSP = 650, |
| STR_D = 651, |
| STR_W = 652, |
| ST_F16 = 653, |
| SWM_MM = 654, |
| SZ_B_PSEUDO = 655, |
| SZ_D_PSEUDO = 656, |
| SZ_H_PSEUDO = 657, |
| SZ_V_PSEUDO = 658, |
| SZ_W_PSEUDO = 659, |
| SaaAddr = 660, |
| SaadAddr = 661, |
| SelBeqZ = 662, |
| SelBneZ = 663, |
| SelTBteqZCmp = 664, |
| SelTBteqZCmpi = 665, |
| SelTBteqZSlt = 666, |
| SelTBteqZSlti = 667, |
| SelTBteqZSltiu = 668, |
| SelTBteqZSltu = 669, |
| SelTBtneZCmp = 670, |
| SelTBtneZCmpi = 671, |
| SelTBtneZSlt = 672, |
| SelTBtneZSlti = 673, |
| SelTBtneZSltiu = 674, |
| SelTBtneZSltu = 675, |
| SltCCRxRy16 = 676, |
| SltiCCRxImmX16 = 677, |
| SltiuCCRxImmX16 = 678, |
| SltuCCRxRy16 = 679, |
| SltuRxRyRz16 = 680, |
| TAILCALL = 681, |
| TAILCALL64R6REG = 682, |
| TAILCALLHB64R6REG = 683, |
| TAILCALLHBR6REG = 684, |
| TAILCALLR6REG = 685, |
| TAILCALLREG = 686, |
| TAILCALLREG64 = 687, |
| TAILCALLREGHB = 688, |
| TAILCALLREGHB64 = 689, |
| TAILCALLREG_MM = 690, |
| TAILCALLREG_MMR6 = 691, |
| TAILCALL_MM = 692, |
| TAILCALL_MMR6 = 693, |
| TRAP = 694, |
| TRAP_MM = 695, |
| UDIV_MM_Pseudo = 696, |
| UDivIMacro = 697, |
| UDivMacro = 698, |
| URemIMacro = 699, |
| URemMacro = 700, |
| Ulh = 701, |
| Ulhu = 702, |
| Ulw = 703, |
| Ush = 704, |
| Usw = 705, |
| XOR_V_D_PSEUDO = 706, |
| XOR_V_H_PSEUDO = 707, |
| XOR_V_W_PSEUDO = 708, |
| ABSQ_S_PH = 709, |
| ABSQ_S_PH_MM = 710, |
| ABSQ_S_QB = 711, |
| ABSQ_S_QB_MMR2 = 712, |
| ABSQ_S_W = 713, |
| ABSQ_S_W_MM = 714, |
| ADD = 715, |
| ADDIUPC = 716, |
| ADDIUPC_MM = 717, |
| ADDIUPC_MMR6 = 718, |
| ADDIUR1SP_MM = 719, |
| ADDIUR2_MM = 720, |
| ADDIUS5_MM = 721, |
| ADDIUSP_MM = 722, |
| ADDIU_MMR6 = 723, |
| ADDQH_PH = 724, |
| ADDQH_PH_MMR2 = 725, |
| ADDQH_R_PH = 726, |
| ADDQH_R_PH_MMR2 = 727, |
| ADDQH_R_W = 728, |
| ADDQH_R_W_MMR2 = 729, |
| ADDQH_W = 730, |
| ADDQH_W_MMR2 = 731, |
| ADDQ_PH = 732, |
| ADDQ_PH_MM = 733, |
| ADDQ_S_PH = 734, |
| ADDQ_S_PH_MM = 735, |
| ADDQ_S_W = 736, |
| ADDQ_S_W_MM = 737, |
| ADDR_PS64 = 738, |
| ADDSC = 739, |
| ADDSC_MM = 740, |
| ADDS_A_B = 741, |
| ADDS_A_D = 742, |
| ADDS_A_H = 743, |
| ADDS_A_W = 744, |
| ADDS_S_B = 745, |
| ADDS_S_D = 746, |
| ADDS_S_H = 747, |
| ADDS_S_W = 748, |
| ADDS_U_B = 749, |
| ADDS_U_D = 750, |
| ADDS_U_H = 751, |
| ADDS_U_W = 752, |
| ADDU16_MM = 753, |
| ADDU16_MMR6 = 754, |
| ADDUH_QB = 755, |
| ADDUH_QB_MMR2 = 756, |
| ADDUH_R_QB = 757, |
| ADDUH_R_QB_MMR2 = 758, |
| ADDU_MMR6 = 759, |
| ADDU_PH = 760, |
| ADDU_PH_MMR2 = 761, |
| ADDU_QB = 762, |
| ADDU_QB_MM = 763, |
| ADDU_S_PH = 764, |
| ADDU_S_PH_MMR2 = 765, |
| ADDU_S_QB = 766, |
| ADDU_S_QB_MM = 767, |
| ADDVI_B = 768, |
| ADDVI_D = 769, |
| ADDVI_H = 770, |
| ADDVI_W = 771, |
| ADDV_B = 772, |
| ADDV_D = 773, |
| ADDV_H = 774, |
| ADDV_W = 775, |
| ADDWC = 776, |
| ADDWC_MM = 777, |
| ADD_A_B = 778, |
| ADD_A_D = 779, |
| ADD_A_H = 780, |
| ADD_A_W = 781, |
| ADD_MM = 782, |
| ADD_MMR6 = 783, |
| ADDi = 784, |
| ADDi_MM = 785, |
| ADDiu = 786, |
| ADDiu_MM = 787, |
| ADDu = 788, |
| ADDu_MM = 789, |
| ALIGN = 790, |
| ALIGN_MMR6 = 791, |
| ALUIPC = 792, |
| ALUIPC_MMR6 = 793, |
| AND = 794, |
| AND16_MM = 795, |
| AND16_MMR6 = 796, |
| AND64 = 797, |
| ANDI16_MM = 798, |
| ANDI16_MMR6 = 799, |
| ANDI_B = 800, |
| ANDI_MMR6 = 801, |
| AND_MM = 802, |
| AND_MMR6 = 803, |
| AND_V = 804, |
| ANDi = 805, |
| ANDi64 = 806, |
| ANDi_MM = 807, |
| APPEND = 808, |
| APPEND_MMR2 = 809, |
| ASUB_S_B = 810, |
| ASUB_S_D = 811, |
| ASUB_S_H = 812, |
| ASUB_S_W = 813, |
| ASUB_U_B = 814, |
| ASUB_U_D = 815, |
| ASUB_U_H = 816, |
| ASUB_U_W = 817, |
| AUI = 818, |
| AUIPC = 819, |
| AUIPC_MMR6 = 820, |
| AUI_MMR6 = 821, |
| AVER_S_B = 822, |
| AVER_S_D = 823, |
| AVER_S_H = 824, |
| AVER_S_W = 825, |
| AVER_U_B = 826, |
| AVER_U_D = 827, |
| AVER_U_H = 828, |
| AVER_U_W = 829, |
| AVE_S_B = 830, |
| AVE_S_D = 831, |
| AVE_S_H = 832, |
| AVE_S_W = 833, |
| AVE_U_B = 834, |
| AVE_U_D = 835, |
| AVE_U_H = 836, |
| AVE_U_W = 837, |
| AddiuRxImmX16 = 838, |
| AddiuRxPcImmX16 = 839, |
| AddiuRxRxImm16 = 840, |
| AddiuRxRxImmX16 = 841, |
| AddiuRxRyOffMemX16 = 842, |
| AddiuSpImm16 = 843, |
| AddiuSpImmX16 = 844, |
| AdduRxRyRz16 = 845, |
| AndRxRxRy16 = 846, |
| B16_MM = 847, |
| BADDu = 848, |
| BAL = 849, |
| BALC = 850, |
| BALC_MMR6 = 851, |
| BALIGN = 852, |
| BALIGN_MMR2 = 853, |
| BBIT0 = 854, |
| BBIT032 = 855, |
| BBIT1 = 856, |
| BBIT132 = 857, |
| BC = 858, |
| BC16_MMR6 = 859, |
| BC1EQZ = 860, |
| BC1EQZC_MMR6 = 861, |
| BC1F = 862, |
| BC1FL = 863, |
| BC1F_MM = 864, |
| BC1NEZ = 865, |
| BC1NEZC_MMR6 = 866, |
| BC1T = 867, |
| BC1TL = 868, |
| BC1T_MM = 869, |
| BC2EQZ = 870, |
| BC2EQZC_MMR6 = 871, |
| BC2NEZ = 872, |
| BC2NEZC_MMR6 = 873, |
| BCLRI_B = 874, |
| BCLRI_D = 875, |
| BCLRI_H = 876, |
| BCLRI_W = 877, |
| BCLR_B = 878, |
| BCLR_D = 879, |
| BCLR_H = 880, |
| BCLR_W = 881, |
| BC_MMR6 = 882, |
| BEQ = 883, |
| BEQ64 = 884, |
| BEQC = 885, |
| BEQC64 = 886, |
| BEQC_MMR6 = 887, |
| BEQL = 888, |
| BEQZ16_MM = 889, |
| BEQZALC = 890, |
| BEQZALC_MMR6 = 891, |
| BEQZC = 892, |
| BEQZC16_MMR6 = 893, |
| BEQZC64 = 894, |
| BEQZC_MM = 895, |
| BEQZC_MMR6 = 896, |
| BEQ_MM = 897, |
| BGEC = 898, |
| BGEC64 = 899, |
| BGEC_MMR6 = 900, |
| BGEUC = 901, |
| BGEUC64 = 902, |
| BGEUC_MMR6 = 903, |
| BGEZ = 904, |
| BGEZ64 = 905, |
| BGEZAL = 906, |
| BGEZALC = 907, |
| BGEZALC_MMR6 = 908, |
| BGEZALL = 909, |
| BGEZALS_MM = 910, |
| BGEZAL_MM = 911, |
| BGEZC = 912, |
| BGEZC64 = 913, |
| BGEZC_MMR6 = 914, |
| BGEZL = 915, |
| BGEZ_MM = 916, |
| BGTZ = 917, |
| BGTZ64 = 918, |
| BGTZALC = 919, |
| BGTZALC_MMR6 = 920, |
| BGTZC = 921, |
| BGTZC64 = 922, |
| BGTZC_MMR6 = 923, |
| BGTZL = 924, |
| BGTZ_MM = 925, |
| BINSLI_B = 926, |
| BINSLI_D = 927, |
| BINSLI_H = 928, |
| BINSLI_W = 929, |
| BINSL_B = 930, |
| BINSL_D = 931, |
| BINSL_H = 932, |
| BINSL_W = 933, |
| BINSRI_B = 934, |
| BINSRI_D = 935, |
| BINSRI_H = 936, |
| BINSRI_W = 937, |
| BINSR_B = 938, |
| BINSR_D = 939, |
| BINSR_H = 940, |
| BINSR_W = 941, |
| BITREV = 942, |
| BITREV_MM = 943, |
| BITSWAP = 944, |
| BITSWAP_MMR6 = 945, |
| BLEZ = 946, |
| BLEZ64 = 947, |
| BLEZALC = 948, |
| BLEZALC_MMR6 = 949, |
| BLEZC = 950, |
| BLEZC64 = 951, |
| BLEZC_MMR6 = 952, |
| BLEZL = 953, |
| BLEZ_MM = 954, |
| BLTC = 955, |
| BLTC64 = 956, |
| BLTC_MMR6 = 957, |
| BLTUC = 958, |
| BLTUC64 = 959, |
| BLTUC_MMR6 = 960, |
| BLTZ = 961, |
| BLTZ64 = 962, |
| BLTZAL = 963, |
| BLTZALC = 964, |
| BLTZALC_MMR6 = 965, |
| BLTZALL = 966, |
| BLTZALS_MM = 967, |
| BLTZAL_MM = 968, |
| BLTZC = 969, |
| BLTZC64 = 970, |
| BLTZC_MMR6 = 971, |
| BLTZL = 972, |
| BLTZ_MM = 973, |
| BMNZI_B = 974, |
| BMNZ_V = 975, |
| BMZI_B = 976, |
| BMZ_V = 977, |
| BNE = 978, |
| BNE64 = 979, |
| BNEC = 980, |
| BNEC64 = 981, |
| BNEC_MMR6 = 982, |
| BNEGI_B = 983, |
| BNEGI_D = 984, |
| BNEGI_H = 985, |
| BNEGI_W = 986, |
| BNEG_B = 987, |
| BNEG_D = 988, |
| BNEG_H = 989, |
| BNEG_W = 990, |
| BNEL = 991, |
| BNEZ16_MM = 992, |
| BNEZALC = 993, |
| BNEZALC_MMR6 = 994, |
| BNEZC = 995, |
| BNEZC16_MMR6 = 996, |
| BNEZC64 = 997, |
| BNEZC_MM = 998, |
| BNEZC_MMR6 = 999, |
| BNE_MM = 1000, |
| BNVC = 1001, |
| BNVC_MMR6 = 1002, |
| BNZ_B = 1003, |
| BNZ_D = 1004, |
| BNZ_H = 1005, |
| BNZ_V = 1006, |
| BNZ_W = 1007, |
| BOVC = 1008, |
| BOVC_MMR6 = 1009, |
| BPOSGE32 = 1010, |
| BPOSGE32C_MMR3 = 1011, |
| BPOSGE32_MM = 1012, |
| BREAK = 1013, |
| BREAK16_MM = 1014, |
| BREAK16_MMR6 = 1015, |
| BREAK_MM = 1016, |
| BREAK_MMR6 = 1017, |
| BSELI_B = 1018, |
| BSEL_V = 1019, |
| BSETI_B = 1020, |
| BSETI_D = 1021, |
| BSETI_H = 1022, |
| BSETI_W = 1023, |
| BSET_B = 1024, |
| BSET_D = 1025, |
| BSET_H = 1026, |
| BSET_W = 1027, |
| BZ_B = 1028, |
| BZ_D = 1029, |
| BZ_H = 1030, |
| BZ_V = 1031, |
| BZ_W = 1032, |
| BeqzRxImm16 = 1033, |
| BeqzRxImmX16 = 1034, |
| Bimm16 = 1035, |
| BimmX16 = 1036, |
| BnezRxImm16 = 1037, |
| BnezRxImmX16 = 1038, |
| Break16 = 1039, |
| Bteqz16 = 1040, |
| BteqzX16 = 1041, |
| Btnez16 = 1042, |
| BtnezX16 = 1043, |
| CACHE = 1044, |
| CACHEE = 1045, |
| CACHEE_MM = 1046, |
| CACHE_MM = 1047, |
| CACHE_MMR6 = 1048, |
| CACHE_R6 = 1049, |
| CEIL_L_D64 = 1050, |
| CEIL_L_D_MMR6 = 1051, |
| CEIL_L_S = 1052, |
| CEIL_L_S_MMR6 = 1053, |
| CEIL_W_D32 = 1054, |
| CEIL_W_D64 = 1055, |
| CEIL_W_D_MMR6 = 1056, |
| CEIL_W_MM = 1057, |
| CEIL_W_S = 1058, |
| CEIL_W_S_MM = 1059, |
| CEIL_W_S_MMR6 = 1060, |
| CEQI_B = 1061, |
| CEQI_D = 1062, |
| CEQI_H = 1063, |
| CEQI_W = 1064, |
| CEQ_B = 1065, |
| CEQ_D = 1066, |
| CEQ_H = 1067, |
| CEQ_W = 1068, |
| CFC1 = 1069, |
| CFC1_MM = 1070, |
| CFC2_MM = 1071, |
| CFCMSA = 1072, |
| CINS = 1073, |
| CINS32 = 1074, |
| CINS64_32 = 1075, |
| CINS_i32 = 1076, |
| CLASS_D = 1077, |
| CLASS_D_MMR6 = 1078, |
| CLASS_S = 1079, |
| CLASS_S_MMR6 = 1080, |
| CLEI_S_B = 1081, |
| CLEI_S_D = 1082, |
| CLEI_S_H = 1083, |
| CLEI_S_W = 1084, |
| CLEI_U_B = 1085, |
| CLEI_U_D = 1086, |
| CLEI_U_H = 1087, |
| CLEI_U_W = 1088, |
| CLE_S_B = 1089, |
| CLE_S_D = 1090, |
| CLE_S_H = 1091, |
| CLE_S_W = 1092, |
| CLE_U_B = 1093, |
| CLE_U_D = 1094, |
| CLE_U_H = 1095, |
| CLE_U_W = 1096, |
| CLO = 1097, |
| CLO_MM = 1098, |
| CLO_MMR6 = 1099, |
| CLO_R6 = 1100, |
| CLTI_S_B = 1101, |
| CLTI_S_D = 1102, |
| CLTI_S_H = 1103, |
| CLTI_S_W = 1104, |
| CLTI_U_B = 1105, |
| CLTI_U_D = 1106, |
| CLTI_U_H = 1107, |
| CLTI_U_W = 1108, |
| CLT_S_B = 1109, |
| CLT_S_D = 1110, |
| CLT_S_H = 1111, |
| CLT_S_W = 1112, |
| CLT_U_B = 1113, |
| CLT_U_D = 1114, |
| CLT_U_H = 1115, |
| CLT_U_W = 1116, |
| CLZ = 1117, |
| CLZ_MM = 1118, |
| CLZ_MMR6 = 1119, |
| CLZ_R6 = 1120, |
| CMPGDU_EQ_QB = 1121, |
| CMPGDU_EQ_QB_MMR2 = 1122, |
| CMPGDU_LE_QB = 1123, |
| CMPGDU_LE_QB_MMR2 = 1124, |
| CMPGDU_LT_QB = 1125, |
| CMPGDU_LT_QB_MMR2 = 1126, |
| CMPGU_EQ_QB = 1127, |
| CMPGU_EQ_QB_MM = 1128, |
| CMPGU_LE_QB = 1129, |
| CMPGU_LE_QB_MM = 1130, |
| CMPGU_LT_QB = 1131, |
| CMPGU_LT_QB_MM = 1132, |
| CMPU_EQ_QB = 1133, |
| CMPU_EQ_QB_MM = 1134, |
| CMPU_LE_QB = 1135, |
| CMPU_LE_QB_MM = 1136, |
| CMPU_LT_QB = 1137, |
| CMPU_LT_QB_MM = 1138, |
| CMP_AF_D_MMR6 = 1139, |
| CMP_AF_S_MMR6 = 1140, |
| CMP_EQ_D = 1141, |
| CMP_EQ_D_MMR6 = 1142, |
| CMP_EQ_PH = 1143, |
| CMP_EQ_PH_MM = 1144, |
| CMP_EQ_S = 1145, |
| CMP_EQ_S_MMR6 = 1146, |
| CMP_F_D = 1147, |
| CMP_F_S = 1148, |
| CMP_LE_D = 1149, |
| CMP_LE_D_MMR6 = 1150, |
| CMP_LE_PH = 1151, |
| CMP_LE_PH_MM = 1152, |
| CMP_LE_S = 1153, |
| CMP_LE_S_MMR6 = 1154, |
| CMP_LT_D = 1155, |
| CMP_LT_D_MMR6 = 1156, |
| CMP_LT_PH = 1157, |
| CMP_LT_PH_MM = 1158, |
| CMP_LT_S = 1159, |
| CMP_LT_S_MMR6 = 1160, |
| CMP_SAF_D = 1161, |
| CMP_SAF_D_MMR6 = 1162, |
| CMP_SAF_S = 1163, |
| CMP_SAF_S_MMR6 = 1164, |
| CMP_SEQ_D = 1165, |
| CMP_SEQ_D_MMR6 = 1166, |
| CMP_SEQ_S = 1167, |
| CMP_SEQ_S_MMR6 = 1168, |
| CMP_SLE_D = 1169, |
| CMP_SLE_D_MMR6 = 1170, |
| CMP_SLE_S = 1171, |
| CMP_SLE_S_MMR6 = 1172, |
| CMP_SLT_D = 1173, |
| CMP_SLT_D_MMR6 = 1174, |
| CMP_SLT_S = 1175, |
| CMP_SLT_S_MMR6 = 1176, |
| CMP_SUEQ_D = 1177, |
| CMP_SUEQ_D_MMR6 = 1178, |
| CMP_SUEQ_S = 1179, |
| CMP_SUEQ_S_MMR6 = 1180, |
| CMP_SULE_D = 1181, |
| CMP_SULE_D_MMR6 = 1182, |
| CMP_SULE_S = 1183, |
| CMP_SULE_S_MMR6 = 1184, |
| CMP_SULT_D = 1185, |
| CMP_SULT_D_MMR6 = 1186, |
| CMP_SULT_S = 1187, |
| CMP_SULT_S_MMR6 = 1188, |
| CMP_SUN_D = 1189, |
| CMP_SUN_D_MMR6 = 1190, |
| CMP_SUN_S = 1191, |
| CMP_SUN_S_MMR6 = 1192, |
| CMP_UEQ_D = 1193, |
| CMP_UEQ_D_MMR6 = 1194, |
| CMP_UEQ_S = 1195, |
| CMP_UEQ_S_MMR6 = 1196, |
| CMP_ULE_D = 1197, |
| CMP_ULE_D_MMR6 = 1198, |
| CMP_ULE_S = 1199, |
| CMP_ULE_S_MMR6 = 1200, |
| CMP_ULT_D = 1201, |
| CMP_ULT_D_MMR6 = 1202, |
| CMP_ULT_S = 1203, |
| CMP_ULT_S_MMR6 = 1204, |
| CMP_UN_D = 1205, |
| CMP_UN_D_MMR6 = 1206, |
| CMP_UN_S = 1207, |
| CMP_UN_S_MMR6 = 1208, |
| COPY_S_B = 1209, |
| COPY_S_D = 1210, |
| COPY_S_H = 1211, |
| COPY_S_W = 1212, |
| COPY_U_B = 1213, |
| COPY_U_H = 1214, |
| COPY_U_W = 1215, |
| CRC32B = 1216, |
| CRC32CB = 1217, |
| CRC32CD = 1218, |
| CRC32CH = 1219, |
| CRC32CW = 1220, |
| CRC32D = 1221, |
| CRC32H = 1222, |
| CRC32W = 1223, |
| CTC1 = 1224, |
| CTC1_MM = 1225, |
| CTC2_MM = 1226, |
| CTCMSA = 1227, |
| CVT_D32_S = 1228, |
| CVT_D32_S_MM = 1229, |
| CVT_D32_W = 1230, |
| CVT_D32_W_MM = 1231, |
| CVT_D64_L = 1232, |
| CVT_D64_S = 1233, |
| CVT_D64_S_MM = 1234, |
| CVT_D64_W = 1235, |
| CVT_D64_W_MM = 1236, |
| CVT_D_L_MMR6 = 1237, |
| CVT_L_D64 = 1238, |
| CVT_L_D64_MM = 1239, |
| CVT_L_D_MMR6 = 1240, |
| CVT_L_S = 1241, |
| CVT_L_S_MM = 1242, |
| CVT_L_S_MMR6 = 1243, |
| CVT_PS_PW64 = 1244, |
| CVT_PS_S64 = 1245, |
| CVT_PW_PS64 = 1246, |
| CVT_S_D32 = 1247, |
| CVT_S_D32_MM = 1248, |
| CVT_S_D64 = 1249, |
| CVT_S_D64_MM = 1250, |
| CVT_S_L = 1251, |
| CVT_S_L_MMR6 = 1252, |
| CVT_S_PL64 = 1253, |
| CVT_S_PU64 = 1254, |
| CVT_S_W = 1255, |
| CVT_S_W_MM = 1256, |
| CVT_S_W_MMR6 = 1257, |
| CVT_W_D32 = 1258, |
| CVT_W_D32_MM = 1259, |
| CVT_W_D64 = 1260, |
| CVT_W_D64_MM = 1261, |
| CVT_W_S = 1262, |
| CVT_W_S_MM = 1263, |
| CVT_W_S_MMR6 = 1264, |
| C_EQ_D32 = 1265, |
| C_EQ_D32_MM = 1266, |
| C_EQ_D64 = 1267, |
| C_EQ_D64_MM = 1268, |
| C_EQ_S = 1269, |
| C_EQ_S_MM = 1270, |
| C_F_D32 = 1271, |
| C_F_D32_MM = 1272, |
| C_F_D64 = 1273, |
| C_F_D64_MM = 1274, |
| C_F_S = 1275, |
| C_F_S_MM = 1276, |
| C_LE_D32 = 1277, |
| C_LE_D32_MM = 1278, |
| C_LE_D64 = 1279, |
| C_LE_D64_MM = 1280, |
| C_LE_S = 1281, |
| C_LE_S_MM = 1282, |
| C_LT_D32 = 1283, |
| C_LT_D32_MM = 1284, |
| C_LT_D64 = 1285, |
| C_LT_D64_MM = 1286, |
| C_LT_S = 1287, |
| C_LT_S_MM = 1288, |
| C_NGE_D32 = 1289, |
| C_NGE_D32_MM = 1290, |
| C_NGE_D64 = 1291, |
| C_NGE_D64_MM = 1292, |
| C_NGE_S = 1293, |
| C_NGE_S_MM = 1294, |
| C_NGLE_D32 = 1295, |
| C_NGLE_D32_MM = 1296, |
| C_NGLE_D64 = 1297, |
| C_NGLE_D64_MM = 1298, |
| C_NGLE_S = 1299, |
| C_NGLE_S_MM = 1300, |
| C_NGL_D32 = 1301, |
| C_NGL_D32_MM = 1302, |
| C_NGL_D64 = 1303, |
| C_NGL_D64_MM = 1304, |
| C_NGL_S = 1305, |
| C_NGL_S_MM = 1306, |
| C_NGT_D32 = 1307, |
| C_NGT_D32_MM = 1308, |
| C_NGT_D64 = 1309, |
| C_NGT_D64_MM = 1310, |
| C_NGT_S = 1311, |
| C_NGT_S_MM = 1312, |
| C_OLE_D32 = 1313, |
| C_OLE_D32_MM = 1314, |
| C_OLE_D64 = 1315, |
| C_OLE_D64_MM = 1316, |
| C_OLE_S = 1317, |
| C_OLE_S_MM = 1318, |
| C_OLT_D32 = 1319, |
| C_OLT_D32_MM = 1320, |
| C_OLT_D64 = 1321, |
| C_OLT_D64_MM = 1322, |
| C_OLT_S = 1323, |
| C_OLT_S_MM = 1324, |
| C_SEQ_D32 = 1325, |
| C_SEQ_D32_MM = 1326, |
| C_SEQ_D64 = 1327, |
| C_SEQ_D64_MM = 1328, |
| C_SEQ_S = 1329, |
| C_SEQ_S_MM = 1330, |
| C_SF_D32 = 1331, |
| C_SF_D32_MM = 1332, |
| C_SF_D64 = 1333, |
| C_SF_D64_MM = 1334, |
| C_SF_S = 1335, |
| C_SF_S_MM = 1336, |
| C_UEQ_D32 = 1337, |
| C_UEQ_D32_MM = 1338, |
| C_UEQ_D64 = 1339, |
| C_UEQ_D64_MM = 1340, |
| C_UEQ_S = 1341, |
| C_UEQ_S_MM = 1342, |
| C_ULE_D32 = 1343, |
| C_ULE_D32_MM = 1344, |
| C_ULE_D64 = 1345, |
| C_ULE_D64_MM = 1346, |
| C_ULE_S = 1347, |
| C_ULE_S_MM = 1348, |
| C_ULT_D32 = 1349, |
| C_ULT_D32_MM = 1350, |
| C_ULT_D64 = 1351, |
| C_ULT_D64_MM = 1352, |
| C_ULT_S = 1353, |
| C_ULT_S_MM = 1354, |
| C_UN_D32 = 1355, |
| C_UN_D32_MM = 1356, |
| C_UN_D64 = 1357, |
| C_UN_D64_MM = 1358, |
| C_UN_S = 1359, |
| C_UN_S_MM = 1360, |
| CmpRxRy16 = 1361, |
| CmpiRxImm16 = 1362, |
| CmpiRxImmX16 = 1363, |
| DADD = 1364, |
| DADDi = 1365, |
| DADDiu = 1366, |
| DADDu = 1367, |
| DAHI = 1368, |
| DALIGN = 1369, |
| DATI = 1370, |
| DAUI = 1371, |
| DBITSWAP = 1372, |
| DCLO = 1373, |
| DCLO_R6 = 1374, |
| DCLZ = 1375, |
| DCLZ_R6 = 1376, |
| DDIV = 1377, |
| DDIVU = 1378, |
| DERET = 1379, |
| DERET_MM = 1380, |
| DERET_MMR6 = 1381, |
| DEXT = 1382, |
| DEXT64_32 = 1383, |
| DEXTM = 1384, |
| DEXTU = 1385, |
| DI = 1386, |
| DINS = 1387, |
| DINSM = 1388, |
| DINSU = 1389, |
| DIV = 1390, |
| DIVU = 1391, |
| DIVU_MMR6 = 1392, |
| DIV_MMR6 = 1393, |
| DIV_S_B = 1394, |
| DIV_S_D = 1395, |
| DIV_S_H = 1396, |
| DIV_S_W = 1397, |
| DIV_U_B = 1398, |
| DIV_U_D = 1399, |
| DIV_U_H = 1400, |
| DIV_U_W = 1401, |
| DI_MM = 1402, |
| DI_MMR6 = 1403, |
| DLSA = 1404, |
| DLSA_R6 = 1405, |
| DMFC0 = 1406, |
| DMFC1 = 1407, |
| DMFC2 = 1408, |
| DMFC2_OCTEON = 1409, |
| DMFGC0 = 1410, |
| DMOD = 1411, |
| DMODU = 1412, |
| DMT = 1413, |
| DMTC0 = 1414, |
| DMTC1 = 1415, |
| DMTC2 = 1416, |
| DMTC2_OCTEON = 1417, |
| DMTGC0 = 1418, |
| DMUH = 1419, |
| DMUHU = 1420, |
| DMUL = 1421, |
| DMULT = 1422, |
| DMULTu = 1423, |
| DMULU = 1424, |
| DMUL_R6 = 1425, |
| DOTP_S_D = 1426, |
| DOTP_S_H = 1427, |
| DOTP_S_W = 1428, |
| DOTP_U_D = 1429, |
| DOTP_U_H = 1430, |
| DOTP_U_W = 1431, |
| DPADD_S_D = 1432, |
| DPADD_S_H = 1433, |
| DPADD_S_W = 1434, |
| DPADD_U_D = 1435, |
| DPADD_U_H = 1436, |
| DPADD_U_W = 1437, |
| DPAQX_SA_W_PH = 1438, |
| DPAQX_SA_W_PH_MMR2 = 1439, |
| DPAQX_S_W_PH = 1440, |
| DPAQX_S_W_PH_MMR2 = 1441, |
| DPAQ_SA_L_W = 1442, |
| DPAQ_SA_L_W_MM = 1443, |
| DPAQ_S_W_PH = 1444, |
| DPAQ_S_W_PH_MM = 1445, |
| DPAU_H_QBL = 1446, |
| DPAU_H_QBL_MM = 1447, |
| DPAU_H_QBR = 1448, |
| DPAU_H_QBR_MM = 1449, |
| DPAX_W_PH = 1450, |
| DPAX_W_PH_MMR2 = 1451, |
| DPA_W_PH = 1452, |
| DPA_W_PH_MMR2 = 1453, |
| DPOP = 1454, |
| DPSQX_SA_W_PH = 1455, |
| DPSQX_SA_W_PH_MMR2 = 1456, |
| DPSQX_S_W_PH = 1457, |
| DPSQX_S_W_PH_MMR2 = 1458, |
| DPSQ_SA_L_W = 1459, |
| DPSQ_SA_L_W_MM = 1460, |
| DPSQ_S_W_PH = 1461, |
| DPSQ_S_W_PH_MM = 1462, |
| DPSUB_S_D = 1463, |
| DPSUB_S_H = 1464, |
| DPSUB_S_W = 1465, |
| DPSUB_U_D = 1466, |
| DPSUB_U_H = 1467, |
| DPSUB_U_W = 1468, |
| DPSU_H_QBL = 1469, |
| DPSU_H_QBL_MM = 1470, |
| DPSU_H_QBR = 1471, |
| DPSU_H_QBR_MM = 1472, |
| DPSX_W_PH = 1473, |
| DPSX_W_PH_MMR2 = 1474, |
| DPS_W_PH = 1475, |
| DPS_W_PH_MMR2 = 1476, |
| DROTR = 1477, |
| DROTR32 = 1478, |
| DROTRV = 1479, |
| DSBH = 1480, |
| DSDIV = 1481, |
| DSHD = 1482, |
| DSLL = 1483, |
| DSLL32 = 1484, |
| DSLL64_32 = 1485, |
| DSLLV = 1486, |
| DSRA = 1487, |
| DSRA32 = 1488, |
| DSRAV = 1489, |
| DSRL = 1490, |
| DSRL32 = 1491, |
| DSRLV = 1492, |
| DSUB = 1493, |
| DSUBu = 1494, |
| DUDIV = 1495, |
| DVP = 1496, |
| DVPE = 1497, |
| DVP_MMR6 = 1498, |
| DivRxRy16 = 1499, |
| DivuRxRy16 = 1500, |
| EHB = 1501, |
| EHB_MM = 1502, |
| EHB_MMR6 = 1503, |
| EI = 1504, |
| EI_MM = 1505, |
| EI_MMR6 = 1506, |
| EMT = 1507, |
| ERET = 1508, |
| ERETNC = 1509, |
| ERETNC_MMR6 = 1510, |
| ERET_MM = 1511, |
| ERET_MMR6 = 1512, |
| EVP = 1513, |
| EVPE = 1514, |
| EVP_MMR6 = 1515, |
| EXT = 1516, |
| EXTP = 1517, |
| EXTPDP = 1518, |
| EXTPDPV = 1519, |
| EXTPDPV_MM = 1520, |
| EXTPDP_MM = 1521, |
| EXTPV = 1522, |
| EXTPV_MM = 1523, |
| EXTP_MM = 1524, |
| EXTRV_RS_W = 1525, |
| EXTRV_RS_W_MM = 1526, |
| EXTRV_R_W = 1527, |
| EXTRV_R_W_MM = 1528, |
| EXTRV_S_H = 1529, |
| EXTRV_S_H_MM = 1530, |
| EXTRV_W = 1531, |
| EXTRV_W_MM = 1532, |
| EXTR_RS_W = 1533, |
| EXTR_RS_W_MM = 1534, |
| EXTR_R_W = 1535, |
| EXTR_R_W_MM = 1536, |
| EXTR_S_H = 1537, |
| EXTR_S_H_MM = 1538, |
| EXTR_W = 1539, |
| EXTR_W_MM = 1540, |
| EXTS = 1541, |
| EXTS32 = 1542, |
| EXT_MM = 1543, |
| EXT_MMR6 = 1544, |
| FABS_D32 = 1545, |
| FABS_D32_MM = 1546, |
| FABS_D64 = 1547, |
| FABS_D64_MM = 1548, |
| FABS_S = 1549, |
| FABS_S_MM = 1550, |
| FADD_D = 1551, |
| FADD_D32 = 1552, |
| FADD_D32_MM = 1553, |
| FADD_D64 = 1554, |
| FADD_D64_MM = 1555, |
| FADD_PS64 = 1556, |
| FADD_S = 1557, |
| FADD_S_MM = 1558, |
| FADD_S_MMR6 = 1559, |
| FADD_W = 1560, |
| FCAF_D = 1561, |
| FCAF_W = 1562, |
| FCEQ_D = 1563, |
| FCEQ_W = 1564, |
| FCLASS_D = 1565, |
| FCLASS_W = 1566, |
| FCLE_D = 1567, |
| FCLE_W = 1568, |
| FCLT_D = 1569, |
| FCLT_W = 1570, |
| FCMP_D32 = 1571, |
| FCMP_D32_MM = 1572, |
| FCMP_D64 = 1573, |
| FCMP_S32 = 1574, |
| FCMP_S32_MM = 1575, |
| FCNE_D = 1576, |
| FCNE_W = 1577, |
| FCOR_D = 1578, |
| FCOR_W = 1579, |
| FCUEQ_D = 1580, |
| FCUEQ_W = 1581, |
| FCULE_D = 1582, |
| FCULE_W = 1583, |
| FCULT_D = 1584, |
| FCULT_W = 1585, |
| FCUNE_D = 1586, |
| FCUNE_W = 1587, |
| FCUN_D = 1588, |
| FCUN_W = 1589, |
| FDIV_D = 1590, |
| FDIV_D32 = 1591, |
| FDIV_D32_MM = 1592, |
| FDIV_D64 = 1593, |
| FDIV_D64_MM = 1594, |
| FDIV_S = 1595, |
| FDIV_S_MM = 1596, |
| FDIV_S_MMR6 = 1597, |
| FDIV_W = 1598, |
| FEXDO_H = 1599, |
| FEXDO_W = 1600, |
| FEXP2_D = 1601, |
| FEXP2_W = 1602, |
| FEXUPL_D = 1603, |
| FEXUPL_W = 1604, |
| FEXUPR_D = 1605, |
| FEXUPR_W = 1606, |
| FFINT_S_D = 1607, |
| FFINT_S_W = 1608, |
| FFINT_U_D = 1609, |
| FFINT_U_W = 1610, |
| FFQL_D = 1611, |
| FFQL_W = 1612, |
| FFQR_D = 1613, |
| FFQR_W = 1614, |
| FILL_B = 1615, |
| FILL_D = 1616, |
| FILL_H = 1617, |
| FILL_W = 1618, |
| FLOG2_D = 1619, |
| FLOG2_W = 1620, |
| FLOOR_L_D64 = 1621, |
| FLOOR_L_D_MMR6 = 1622, |
| FLOOR_L_S = 1623, |
| FLOOR_L_S_MMR6 = 1624, |
| FLOOR_W_D32 = 1625, |
| FLOOR_W_D64 = 1626, |
| FLOOR_W_D_MMR6 = 1627, |
| FLOOR_W_MM = 1628, |
| FLOOR_W_S = 1629, |
| FLOOR_W_S_MM = 1630, |
| FLOOR_W_S_MMR6 = 1631, |
| FMADD_D = 1632, |
| FMADD_W = 1633, |
| FMAX_A_D = 1634, |
| FMAX_A_W = 1635, |
| FMAX_D = 1636, |
| FMAX_W = 1637, |
| FMIN_A_D = 1638, |
| FMIN_A_W = 1639, |
| FMIN_D = 1640, |
| FMIN_W = 1641, |
| FMOV_D32 = 1642, |
| FMOV_D32_MM = 1643, |
| FMOV_D64 = 1644, |
| FMOV_D64_MM = 1645, |
| FMOV_D_MMR6 = 1646, |
| FMOV_S = 1647, |
| FMOV_S_MM = 1648, |
| FMOV_S_MMR6 = 1649, |
| FMSUB_D = 1650, |
| FMSUB_W = 1651, |
| FMUL_D = 1652, |
| FMUL_D32 = 1653, |
| FMUL_D32_MM = 1654, |
| FMUL_D64 = 1655, |
| FMUL_D64_MM = 1656, |
| FMUL_PS64 = 1657, |
| FMUL_S = 1658, |
| FMUL_S_MM = 1659, |
| FMUL_S_MMR6 = 1660, |
| FMUL_W = 1661, |
| FNEG_D32 = 1662, |
| FNEG_D32_MM = 1663, |
| FNEG_D64 = 1664, |
| FNEG_D64_MM = 1665, |
| FNEG_S = 1666, |
| FNEG_S_MM = 1667, |
| FNEG_S_MMR6 = 1668, |
| FORK = 1669, |
| FRCP_D = 1670, |
| FRCP_W = 1671, |
| FRINT_D = 1672, |
| FRINT_W = 1673, |
| FRSQRT_D = 1674, |
| FRSQRT_W = 1675, |
| FSAF_D = 1676, |
| FSAF_W = 1677, |
| FSEQ_D = 1678, |
| FSEQ_W = 1679, |
| FSLE_D = 1680, |
| FSLE_W = 1681, |
| FSLT_D = 1682, |
| FSLT_W = 1683, |
| FSNE_D = 1684, |
| FSNE_W = 1685, |
| FSOR_D = 1686, |
| FSOR_W = 1687, |
| FSQRT_D = 1688, |
| FSQRT_D32 = 1689, |
| FSQRT_D32_MM = 1690, |
| FSQRT_D64 = 1691, |
| FSQRT_D64_MM = 1692, |
| FSQRT_S = 1693, |
| FSQRT_S_MM = 1694, |
| FSQRT_W = 1695, |
| FSUB_D = 1696, |
| FSUB_D32 = 1697, |
| FSUB_D32_MM = 1698, |
| FSUB_D64 = 1699, |
| FSUB_D64_MM = 1700, |
| FSUB_PS64 = 1701, |
| FSUB_S = 1702, |
| FSUB_S_MM = 1703, |
| FSUB_S_MMR6 = 1704, |
| FSUB_W = 1705, |
| FSUEQ_D = 1706, |
| FSUEQ_W = 1707, |
| FSULE_D = 1708, |
| FSULE_W = 1709, |
| FSULT_D = 1710, |
| FSULT_W = 1711, |
| FSUNE_D = 1712, |
| FSUNE_W = 1713, |
| FSUN_D = 1714, |
| FSUN_W = 1715, |
| FTINT_S_D = 1716, |
| FTINT_S_W = 1717, |
| FTINT_U_D = 1718, |
| FTINT_U_W = 1719, |
| FTQ_H = 1720, |
| FTQ_W = 1721, |
| FTRUNC_S_D = 1722, |
| FTRUNC_S_W = 1723, |
| FTRUNC_U_D = 1724, |
| FTRUNC_U_W = 1725, |
| GINVI = 1726, |
| GINVI_MMR6 = 1727, |
| GINVT = 1728, |
| GINVT_MMR6 = 1729, |
| HADD_S_D = 1730, |
| HADD_S_H = 1731, |
| HADD_S_W = 1732, |
| HADD_U_D = 1733, |
| HADD_U_H = 1734, |
| HADD_U_W = 1735, |
| HSUB_S_D = 1736, |
| HSUB_S_H = 1737, |
| HSUB_S_W = 1738, |
| HSUB_U_D = 1739, |
| HSUB_U_H = 1740, |
| HSUB_U_W = 1741, |
| HYPCALL = 1742, |
| HYPCALL_MM = 1743, |
| ILVEV_B = 1744, |
| ILVEV_D = 1745, |
| ILVEV_H = 1746, |
| ILVEV_W = 1747, |
| ILVL_B = 1748, |
| ILVL_D = 1749, |
| ILVL_H = 1750, |
| ILVL_W = 1751, |
| ILVOD_B = 1752, |
| ILVOD_D = 1753, |
| ILVOD_H = 1754, |
| ILVOD_W = 1755, |
| ILVR_B = 1756, |
| ILVR_D = 1757, |
| ILVR_H = 1758, |
| ILVR_W = 1759, |
| INS = 1760, |
| INSERT_B = 1761, |
| INSERT_D = 1762, |
| INSERT_H = 1763, |
| INSERT_W = 1764, |
| INSV = 1765, |
| INSVE_B = 1766, |
| INSVE_D = 1767, |
| INSVE_H = 1768, |
| INSVE_W = 1769, |
| INSV_MM = 1770, |
| INS_MM = 1771, |
| INS_MMR6 = 1772, |
| J = 1773, |
| JAL = 1774, |
| JALR = 1775, |
| JALR16_MM = 1776, |
| JALR64 = 1777, |
| JALRC16_MMR6 = 1778, |
| JALRC_HB_MMR6 = 1779, |
| JALRC_MMR6 = 1780, |
| JALRS16_MM = 1781, |
| JALRS_MM = 1782, |
| JALR_HB = 1783, |
| JALR_HB64 = 1784, |
| JALR_MM = 1785, |
| JALS_MM = 1786, |
| JALX = 1787, |
| JALX_MM = 1788, |
| JAL_MM = 1789, |
| JIALC = 1790, |
| JIALC64 = 1791, |
| JIALC_MMR6 = 1792, |
| JIC = 1793, |
| JIC64 = 1794, |
| JIC_MMR6 = 1795, |
| JR = 1796, |
| JR16_MM = 1797, |
| JR64 = 1798, |
| JRADDIUSP = 1799, |
| JRC16_MM = 1800, |
| JRC16_MMR6 = 1801, |
| JRCADDIUSP_MMR6 = 1802, |
| JR_HB = 1803, |
| JR_HB64 = 1804, |
| JR_HB64_R6 = 1805, |
| JR_HB_R6 = 1806, |
| JR_MM = 1807, |
| J_MM = 1808, |
| Jal16 = 1809, |
| JalB16 = 1810, |
| JrRa16 = 1811, |
| JrcRa16 = 1812, |
| JrcRx16 = 1813, |
| JumpLinkReg16 = 1814, |
| LB = 1815, |
| LB64 = 1816, |
| LBE = 1817, |
| LBE_MM = 1818, |
| LBU16_MM = 1819, |
| LBUX = 1820, |
| LBUX_MM = 1821, |
| LBU_MMR6 = 1822, |
| LB_MM = 1823, |
| LB_MMR6 = 1824, |
| LBu = 1825, |
| LBu64 = 1826, |
| LBuE = 1827, |
| LBuE_MM = 1828, |
| LBu_MM = 1829, |
| LD = 1830, |
| LDC1 = 1831, |
| LDC164 = 1832, |
| LDC1_D64_MMR6 = 1833, |
| LDC1_MM_D32 = 1834, |
| LDC1_MM_D64 = 1835, |
| LDC2 = 1836, |
| LDC2_MMR6 = 1837, |
| LDC2_R6 = 1838, |
| LDC3 = 1839, |
| LDI_B = 1840, |
| LDI_D = 1841, |
| LDI_H = 1842, |
| LDI_W = 1843, |
| LDL = 1844, |
| LDPC = 1845, |
| LDR = 1846, |
| LDXC1 = 1847, |
| LDXC164 = 1848, |
| LD_B = 1849, |
| LD_D = 1850, |
| LD_H = 1851, |
| LD_W = 1852, |
| LEA_ADDiu = 1853, |
| LEA_ADDiu64 = 1854, |
| LEA_ADDiu_MM = 1855, |
| LH = 1856, |
| LH64 = 1857, |
| LHE = 1858, |
| LHE_MM = 1859, |
| LHU16_MM = 1860, |
| LHX = 1861, |
| LHX_MM = 1862, |
| LH_MM = 1863, |
| LHu = 1864, |
| LHu64 = 1865, |
| LHuE = 1866, |
| LHuE_MM = 1867, |
| LHu_MM = 1868, |
| LI16_MM = 1869, |
| LI16_MMR6 = 1870, |
| LL = 1871, |
| LL64 = 1872, |
| LL64_R6 = 1873, |
| LLD = 1874, |
| LLD_R6 = 1875, |
| LLE = 1876, |
| LLE_MM = 1877, |
| LL_MM = 1878, |
| LL_MMR6 = 1879, |
| LL_R6 = 1880, |
| LSA = 1881, |
| LSA_MMR6 = 1882, |
| LSA_R6 = 1883, |
| LUI_MMR6 = 1884, |
| LUXC1 = 1885, |
| LUXC164 = 1886, |
| LUXC1_MM = 1887, |
| LUi = 1888, |
| LUi64 = 1889, |
| LUi_MM = 1890, |
| LW = 1891, |
| LW16_MM = 1892, |
| LW64 = 1893, |
| LWC1 = 1894, |
| LWC1_MM = 1895, |
| LWC2 = 1896, |
| LWC2_MMR6 = 1897, |
| LWC2_R6 = 1898, |
| LWC3 = 1899, |
| LWDSP = 1900, |
| LWDSP_MM = 1901, |
| LWE = 1902, |
| LWE_MM = 1903, |
| LWGP_MM = 1904, |
| LWL = 1905, |
| LWL64 = 1906, |
| LWLE = 1907, |
| LWLE_MM = 1908, |
| LWL_MM = 1909, |
| LWM16_MM = 1910, |
| LWM16_MMR6 = 1911, |
| LWM32_MM = 1912, |
| LWPC = 1913, |
| LWPC_MMR6 = 1914, |
| LWP_MM = 1915, |
| LWR = 1916, |
| LWR64 = 1917, |
| LWRE = 1918, |
| LWRE_MM = 1919, |
| LWR_MM = 1920, |
| LWSP_MM = 1921, |
| LWUPC = 1922, |
| LWU_MM = 1923, |
| LWX = 1924, |
| LWXC1 = 1925, |
| LWXC1_MM = 1926, |
| LWXS_MM = 1927, |
| LWX_MM = 1928, |
| LW_MM = 1929, |
| LW_MMR6 = 1930, |
| LWu = 1931, |
| LbRxRyOffMemX16 = 1932, |
| LbuRxRyOffMemX16 = 1933, |
| LhRxRyOffMemX16 = 1934, |
| LhuRxRyOffMemX16 = 1935, |
| LiRxImm16 = 1936, |
| LiRxImmAlignX16 = 1937, |
| LiRxImmX16 = 1938, |
| LwRxPcTcp16 = 1939, |
| LwRxPcTcpX16 = 1940, |
| LwRxRyOffMemX16 = 1941, |
| LwRxSpImmX16 = 1942, |
| MADD = 1943, |
| MADDF_D = 1944, |
| MADDF_D_MMR6 = 1945, |
| MADDF_S = 1946, |
| MADDF_S_MMR6 = 1947, |
| MADDR_Q_H = 1948, |
| MADDR_Q_W = 1949, |
| MADDU = 1950, |
| MADDU_DSP = 1951, |
| MADDU_DSP_MM = 1952, |
| MADDU_MM = 1953, |
| MADDV_B = 1954, |
| MADDV_D = 1955, |
| MADDV_H = 1956, |
| MADDV_W = 1957, |
| MADD_D32 = 1958, |
| MADD_D32_MM = 1959, |
| MADD_D64 = 1960, |
| MADD_DSP = 1961, |
| MADD_DSP_MM = 1962, |
| MADD_MM = 1963, |
| MADD_Q_H = 1964, |
| MADD_Q_W = 1965, |
| MADD_S = 1966, |
| MADD_S_MM = 1967, |
| MAQ_SA_W_PHL = 1968, |
| MAQ_SA_W_PHL_MM = 1969, |
| MAQ_SA_W_PHR = 1970, |
| MAQ_SA_W_PHR_MM = 1971, |
| MAQ_S_W_PHL = 1972, |
| MAQ_S_W_PHL_MM = 1973, |
| MAQ_S_W_PHR = 1974, |
| MAQ_S_W_PHR_MM = 1975, |
| MAXA_D = 1976, |
| MAXA_D_MMR6 = 1977, |
| MAXA_S = 1978, |
| MAXA_S_MMR6 = 1979, |
| MAXI_S_B = 1980, |
| MAXI_S_D = 1981, |
| MAXI_S_H = 1982, |
| MAXI_S_W = 1983, |
| MAXI_U_B = 1984, |
| MAXI_U_D = 1985, |
| MAXI_U_H = 1986, |
| MAXI_U_W = 1987, |
| MAX_A_B = 1988, |
| MAX_A_D = 1989, |
| MAX_A_H = 1990, |
| MAX_A_W = 1991, |
| MAX_D = 1992, |
| MAX_D_MMR6 = 1993, |
| MAX_S = 1994, |
| MAX_S_B = 1995, |
| MAX_S_D = 1996, |
| MAX_S_H = 1997, |
| MAX_S_MMR6 = 1998, |
| MAX_S_W = 1999, |
| MAX_U_B = 2000, |
| MAX_U_D = 2001, |
| MAX_U_H = 2002, |
| MAX_U_W = 2003, |
| MFC0 = 2004, |
| MFC0_MMR6 = 2005, |
| MFC1 = 2006, |
| MFC1_D64 = 2007, |
| MFC1_MM = 2008, |
| MFC1_MMR6 = 2009, |
| MFC2 = 2010, |
| MFC2_MMR6 = 2011, |
| MFGC0 = 2012, |
| MFGC0_MM = 2013, |
| MFHC0_MMR6 = 2014, |
| MFHC1_D32 = 2015, |
| MFHC1_D32_MM = 2016, |
| MFHC1_D64 = 2017, |
| MFHC1_D64_MM = 2018, |
| MFHC2_MMR6 = 2019, |
| MFHGC0 = 2020, |
| MFHGC0_MM = 2021, |
| MFHI = 2022, |
| MFHI16_MM = 2023, |
| MFHI64 = 2024, |
| MFHI_DSP = 2025, |
| MFHI_DSP_MM = 2026, |
| MFHI_MM = 2027, |
| MFLO = 2028, |
| MFLO16_MM = 2029, |
| MFLO64 = 2030, |
| MFLO_DSP = 2031, |
| MFLO_DSP_MM = 2032, |
| MFLO_MM = 2033, |
| MFTR = 2034, |
| MINA_D = 2035, |
| MINA_D_MMR6 = 2036, |
| MINA_S = 2037, |
| MINA_S_MMR6 = 2038, |
| MINI_S_B = 2039, |
| MINI_S_D = 2040, |
| MINI_S_H = 2041, |
| MINI_S_W = 2042, |
| MINI_U_B = 2043, |
| MINI_U_D = 2044, |
| MINI_U_H = 2045, |
| MINI_U_W = 2046, |
| MIN_A_B = 2047, |
| MIN_A_D = 2048, |
| MIN_A_H = 2049, |
| MIN_A_W = 2050, |
| MIN_D = 2051, |
| MIN_D_MMR6 = 2052, |
| MIN_S = 2053, |
| MIN_S_B = 2054, |
| MIN_S_D = 2055, |
| MIN_S_H = 2056, |
| MIN_S_MMR6 = 2057, |
| MIN_S_W = 2058, |
| MIN_U_B = 2059, |
| MIN_U_D = 2060, |
| MIN_U_H = 2061, |
| MIN_U_W = 2062, |
| MOD = 2063, |
| MODSUB = 2064, |
| MODSUB_MM = 2065, |
| MODU = 2066, |
| MODU_MMR6 = 2067, |
| MOD_MMR6 = 2068, |
| MOD_S_B = 2069, |
| MOD_S_D = 2070, |
| MOD_S_H = 2071, |
| MOD_S_W = 2072, |
| MOD_U_B = 2073, |
| MOD_U_D = 2074, |
| MOD_U_H = 2075, |
| MOD_U_W = 2076, |
| MOVE16_MM = 2077, |
| MOVE16_MMR6 = 2078, |
| MOVEP_MM = 2079, |
| MOVEP_MMR6 = 2080, |
| MOVE_V = 2081, |
| MOVF_D32 = 2082, |
| MOVF_D32_MM = 2083, |
| MOVF_D64 = 2084, |
| MOVF_I = 2085, |
| MOVF_I64 = 2086, |
| MOVF_I_MM = 2087, |
| MOVF_S = 2088, |
| MOVF_S_MM = 2089, |
| MOVN_I64_D64 = 2090, |
| MOVN_I64_I = 2091, |
| MOVN_I64_I64 = 2092, |
| MOVN_I64_S = 2093, |
| MOVN_I_D32 = 2094, |
| MOVN_I_D32_MM = 2095, |
| MOVN_I_D64 = 2096, |
| MOVN_I_I = 2097, |
| MOVN_I_I64 = 2098, |
| MOVN_I_MM = 2099, |
| MOVN_I_S = 2100, |
| MOVN_I_S_MM = 2101, |
| MOVT_D32 = 2102, |
| MOVT_D32_MM = 2103, |
| MOVT_D64 = 2104, |
| MOVT_I = 2105, |
| MOVT_I64 = 2106, |
| MOVT_I_MM = 2107, |
| MOVT_S = 2108, |
| MOVT_S_MM = 2109, |
| MOVZ_I64_D64 = 2110, |
| MOVZ_I64_I = 2111, |
| MOVZ_I64_I64 = 2112, |
| MOVZ_I64_S = 2113, |
| MOVZ_I_D32 = 2114, |
| MOVZ_I_D32_MM = 2115, |
| MOVZ_I_D64 = 2116, |
| MOVZ_I_I = 2117, |
| MOVZ_I_I64 = 2118, |
| MOVZ_I_MM = 2119, |
| MOVZ_I_S = 2120, |
| MOVZ_I_S_MM = 2121, |
| MSUB = 2122, |
| MSUBF_D = 2123, |
| MSUBF_D_MMR6 = 2124, |
| MSUBF_S = 2125, |
| MSUBF_S_MMR6 = 2126, |
| MSUBR_Q_H = 2127, |
| MSUBR_Q_W = 2128, |
| MSUBU = 2129, |
| MSUBU_DSP = 2130, |
| MSUBU_DSP_MM = 2131, |
| MSUBU_MM = 2132, |
| MSUBV_B = 2133, |
| MSUBV_D = 2134, |
| MSUBV_H = 2135, |
| MSUBV_W = 2136, |
| MSUB_D32 = 2137, |
| MSUB_D32_MM = 2138, |
| MSUB_D64 = 2139, |
| MSUB_DSP = 2140, |
| MSUB_DSP_MM = 2141, |
| MSUB_MM = 2142, |
| MSUB_Q_H = 2143, |
| MSUB_Q_W = 2144, |
| MSUB_S = 2145, |
| MSUB_S_MM = 2146, |
| MTC0 = 2147, |
| MTC0_MMR6 = 2148, |
| MTC1 = 2149, |
| MTC1_D64 = 2150, |
| MTC1_D64_MM = 2151, |
| MTC1_MM = 2152, |
| MTC1_MMR6 = 2153, |
| MTC2 = 2154, |
| MTC2_MMR6 = 2155, |
| MTGC0 = 2156, |
| MTGC0_MM = 2157, |
| MTHC0_MMR6 = 2158, |
| MTHC1_D32 = 2159, |
| MTHC1_D32_MM = 2160, |
| MTHC1_D64 = 2161, |
| MTHC1_D64_MM = 2162, |
| MTHC2_MMR6 = 2163, |
| MTHGC0 = 2164, |
| MTHGC0_MM = 2165, |
| MTHI = 2166, |
| MTHI64 = 2167, |
| MTHI_DSP = 2168, |
| MTHI_DSP_MM = 2169, |
| MTHI_MM = 2170, |
| MTHLIP = 2171, |
| MTHLIP_MM = 2172, |
| MTLO = 2173, |
| MTLO64 = 2174, |
| MTLO_DSP = 2175, |
| MTLO_DSP_MM = 2176, |
| MTLO_MM = 2177, |
| MTM0 = 2178, |
| MTM1 = 2179, |
| MTM2 = 2180, |
| MTP0 = 2181, |
| MTP1 = 2182, |
| MTP2 = 2183, |
| MTTR = 2184, |
| MUH = 2185, |
| MUHU = 2186, |
| MUHU_MMR6 = 2187, |
| MUH_MMR6 = 2188, |
| MUL = 2189, |
| MULEQ_S_W_PHL = 2190, |
| MULEQ_S_W_PHL_MM = 2191, |
| MULEQ_S_W_PHR = 2192, |
| MULEQ_S_W_PHR_MM = 2193, |
| MULEU_S_PH_QBL = 2194, |
| MULEU_S_PH_QBL_MM = 2195, |
| MULEU_S_PH_QBR = 2196, |
| MULEU_S_PH_QBR_MM = 2197, |
| MULQ_RS_PH = 2198, |
| MULQ_RS_PH_MM = 2199, |
| MULQ_RS_W = 2200, |
| MULQ_RS_W_MMR2 = 2201, |
| MULQ_S_PH = 2202, |
| MULQ_S_PH_MMR2 = 2203, |
| MULQ_S_W = 2204, |
| MULQ_S_W_MMR2 = 2205, |
| MULR_PS64 = 2206, |
| MULR_Q_H = 2207, |
| MULR_Q_W = 2208, |
| MULSAQ_S_W_PH = 2209, |
| MULSAQ_S_W_PH_MM = 2210, |
| MULSA_W_PH = 2211, |
| MULSA_W_PH_MMR2 = 2212, |
| MULT = 2213, |
| MULTU_DSP = 2214, |
| MULTU_DSP_MM = 2215, |
| MULT_DSP = 2216, |
| MULT_DSP_MM = 2217, |
| MULT_MM = 2218, |
| MULTu = 2219, |
| MULTu_MM = 2220, |
| MULU = 2221, |
| MULU_MMR6 = 2222, |
| MULV_B = 2223, |
| MULV_D = 2224, |
| MULV_H = 2225, |
| MULV_W = 2226, |
| MUL_MM = 2227, |
| MUL_MMR6 = 2228, |
| MUL_PH = 2229, |
| MUL_PH_MMR2 = 2230, |
| MUL_Q_H = 2231, |
| MUL_Q_W = 2232, |
| MUL_R6 = 2233, |
| MUL_S_PH = 2234, |
| MUL_S_PH_MMR2 = 2235, |
| Mfhi16 = 2236, |
| Mflo16 = 2237, |
| Move32R16 = 2238, |
| MoveR3216 = 2239, |
| NLOC_B = 2240, |
| NLOC_D = 2241, |
| NLOC_H = 2242, |
| NLOC_W = 2243, |
| NLZC_B = 2244, |
| NLZC_D = 2245, |
| NLZC_H = 2246, |
| NLZC_W = 2247, |
| NMADD_D32 = 2248, |
| NMADD_D32_MM = 2249, |
| NMADD_D64 = 2250, |
| NMADD_S = 2251, |
| NMADD_S_MM = 2252, |
| NMSUB_D32 = 2253, |
| NMSUB_D32_MM = 2254, |
| NMSUB_D64 = 2255, |
| NMSUB_S = 2256, |
| NMSUB_S_MM = 2257, |
| NOR = 2258, |
| NOR64 = 2259, |
| NORI_B = 2260, |
| NOR_MM = 2261, |
| NOR_MMR6 = 2262, |
| NOR_V = 2263, |
| NOT16_MM = 2264, |
| NOT16_MMR6 = 2265, |
| NegRxRy16 = 2266, |
| NotRxRy16 = 2267, |
| OR = 2268, |
| OR16_MM = 2269, |
| OR16_MMR6 = 2270, |
| OR64 = 2271, |
| ORI_B = 2272, |
| ORI_MMR6 = 2273, |
| OR_MM = 2274, |
| OR_MMR6 = 2275, |
| OR_V = 2276, |
| ORi = 2277, |
| ORi64 = 2278, |
| ORi_MM = 2279, |
| OrRxRxRy16 = 2280, |
| PACKRL_PH = 2281, |
| PACKRL_PH_MM = 2282, |
| PAUSE = 2283, |
| PAUSE_MM = 2284, |
| PAUSE_MMR6 = 2285, |
| PCKEV_B = 2286, |
| PCKEV_D = 2287, |
| PCKEV_H = 2288, |
| PCKEV_W = 2289, |
| PCKOD_B = 2290, |
| PCKOD_D = 2291, |
| PCKOD_H = 2292, |
| PCKOD_W = 2293, |
| PCNT_B = 2294, |
| PCNT_D = 2295, |
| PCNT_H = 2296, |
| PCNT_W = 2297, |
| PICK_PH = 2298, |
| PICK_PH_MM = 2299, |
| PICK_QB = 2300, |
| PICK_QB_MM = 2301, |
| PLL_PS64 = 2302, |
| PLU_PS64 = 2303, |
| POP = 2304, |
| PRECEQU_PH_QBL = 2305, |
| PRECEQU_PH_QBLA = 2306, |
| PRECEQU_PH_QBLA_MM = 2307, |
| PRECEQU_PH_QBL_MM = 2308, |
| PRECEQU_PH_QBR = 2309, |
| PRECEQU_PH_QBRA = 2310, |
| PRECEQU_PH_QBRA_MM = 2311, |
| PRECEQU_PH_QBR_MM = 2312, |
| PRECEQ_W_PHL = 2313, |
| PRECEQ_W_PHL_MM = 2314, |
| PRECEQ_W_PHR = 2315, |
| PRECEQ_W_PHR_MM = 2316, |
| PRECEU_PH_QBL = 2317, |
| PRECEU_PH_QBLA = 2318, |
| PRECEU_PH_QBLA_MM = 2319, |
| PRECEU_PH_QBL_MM = 2320, |
| PRECEU_PH_QBR = 2321, |
| PRECEU_PH_QBRA = 2322, |
| PRECEU_PH_QBRA_MM = 2323, |
| PRECEU_PH_QBR_MM = 2324, |
| PRECRQU_S_QB_PH = 2325, |
| PRECRQU_S_QB_PH_MM = 2326, |
| PRECRQ_PH_W = 2327, |
| PRECRQ_PH_W_MM = 2328, |
| PRECRQ_QB_PH = 2329, |
| PRECRQ_QB_PH_MM = 2330, |
| PRECRQ_RS_PH_W = 2331, |
| PRECRQ_RS_PH_W_MM = 2332, |
| PRECR_QB_PH = 2333, |
| PRECR_QB_PH_MMR2 = 2334, |
| PRECR_SRA_PH_W = 2335, |
| PRECR_SRA_PH_W_MMR2 = 2336, |
| PRECR_SRA_R_PH_W = 2337, |
| PRECR_SRA_R_PH_W_MMR2 = 2338, |
| PREF = 2339, |
| PREFE = 2340, |
| PREFE_MM = 2341, |
| PREFX_MM = 2342, |
| PREF_MM = 2343, |
| PREF_MMR6 = 2344, |
| PREF_R6 = 2345, |
| PREPEND = 2346, |
| PREPEND_MMR2 = 2347, |
| PUL_PS64 = 2348, |
| PUU_PS64 = 2349, |
| RADDU_W_QB = 2350, |
| RADDU_W_QB_MM = 2351, |
| RDDSP = 2352, |
| RDDSP_MM = 2353, |
| RDHWR = 2354, |
| RDHWR64 = 2355, |
| RDHWR_MM = 2356, |
| RDHWR_MMR6 = 2357, |
| RDPGPR_MMR6 = 2358, |
| RECIP_D32 = 2359, |
| RECIP_D32_MM = 2360, |
| RECIP_D64 = 2361, |
| RECIP_D64_MM = 2362, |
| RECIP_S = 2363, |
| RECIP_S_MM = 2364, |
| REPLV_PH = 2365, |
| REPLV_PH_MM = 2366, |
| REPLV_QB = 2367, |
| REPLV_QB_MM = 2368, |
| REPL_PH = 2369, |
| REPL_PH_MM = 2370, |
| REPL_QB = 2371, |
| REPL_QB_MM = 2372, |
| RINT_D = 2373, |
| RINT_D_MMR6 = 2374, |
| RINT_S = 2375, |
| RINT_S_MMR6 = 2376, |
| ROTR = 2377, |
| ROTRV = 2378, |
| ROTRV_MM = 2379, |
| ROTR_MM = 2380, |
| ROUND_L_D64 = 2381, |
| ROUND_L_D_MMR6 = 2382, |
| ROUND_L_S = 2383, |
| ROUND_L_S_MMR6 = 2384, |
| ROUND_W_D32 = 2385, |
| ROUND_W_D64 = 2386, |
| ROUND_W_D_MMR6 = 2387, |
| ROUND_W_MM = 2388, |
| ROUND_W_S = 2389, |
| ROUND_W_S_MM = 2390, |
| ROUND_W_S_MMR6 = 2391, |
| RSQRT_D32 = 2392, |
| RSQRT_D32_MM = 2393, |
| RSQRT_D64 = 2394, |
| RSQRT_D64_MM = 2395, |
| RSQRT_S = 2396, |
| RSQRT_S_MM = 2397, |
| Restore16 = 2398, |
| RestoreX16 = 2399, |
| SAA = 2400, |
| SAAD = 2401, |
| SAT_S_B = 2402, |
| SAT_S_D = 2403, |
| SAT_S_H = 2404, |
| SAT_S_W = 2405, |
| SAT_U_B = 2406, |
| SAT_U_D = 2407, |
| SAT_U_H = 2408, |
| SAT_U_W = 2409, |
| SB = 2410, |
| SB16_MM = 2411, |
| SB16_MMR6 = 2412, |
| SB64 = 2413, |
| SBE = 2414, |
| SBE_MM = 2415, |
| SB_MM = 2416, |
| SB_MMR6 = 2417, |
| SC = 2418, |
| SC64 = 2419, |
| SC64_R6 = 2420, |
| SCD = 2421, |
| SCD_R6 = 2422, |
| SCE = 2423, |
| SCE_MM = 2424, |
| SC_MM = 2425, |
| SC_MMR6 = 2426, |
| SC_R6 = 2427, |
| SD = 2428, |
| SDBBP = 2429, |
| SDBBP16_MM = 2430, |
| SDBBP16_MMR6 = 2431, |
| SDBBP_MM = 2432, |
| SDBBP_MMR6 = 2433, |
| SDBBP_R6 = 2434, |
| SDC1 = 2435, |
| SDC164 = 2436, |
| SDC1_D64_MMR6 = 2437, |
| SDC1_MM_D32 = 2438, |
| SDC1_MM_D64 = 2439, |
| SDC2 = 2440, |
| SDC2_MMR6 = 2441, |
| SDC2_R6 = 2442, |
| SDC3 = 2443, |
| SDIV = 2444, |
| SDIV_MM = 2445, |
| SDL = 2446, |
| SDR = 2447, |
| SDXC1 = 2448, |
| SDXC164 = 2449, |
| SEB = 2450, |
| SEB64 = 2451, |
| SEB_MM = 2452, |
| SEH = 2453, |
| SEH64 = 2454, |
| SEH_MM = 2455, |
| SELEQZ = 2456, |
| SELEQZ64 = 2457, |
| SELEQZ_D = 2458, |
| SELEQZ_D_MMR6 = 2459, |
| SELEQZ_MMR6 = 2460, |
| SELEQZ_S = 2461, |
| SELEQZ_S_MMR6 = 2462, |
| SELNEZ = 2463, |
| SELNEZ64 = 2464, |
| SELNEZ_D = 2465, |
| SELNEZ_D_MMR6 = 2466, |
| SELNEZ_MMR6 = 2467, |
| SELNEZ_S = 2468, |
| SELNEZ_S_MMR6 = 2469, |
| SEL_D = 2470, |
| SEL_D_MMR6 = 2471, |
| SEL_S = 2472, |
| SEL_S_MMR6 = 2473, |
| SEQ = 2474, |
| SEQi = 2475, |
| SH = 2476, |
| SH16_MM = 2477, |
| SH16_MMR6 = 2478, |
| SH64 = 2479, |
| SHE = 2480, |
| SHE_MM = 2481, |
| SHF_B = 2482, |
| SHF_H = 2483, |
| SHF_W = 2484, |
| SHILO = 2485, |
| SHILOV = 2486, |
| SHILOV_MM = 2487, |
| SHILO_MM = 2488, |
| SHLLV_PH = 2489, |
| SHLLV_PH_MM = 2490, |
| SHLLV_QB = 2491, |
| SHLLV_QB_MM = 2492, |
| SHLLV_S_PH = 2493, |
| SHLLV_S_PH_MM = 2494, |
| SHLLV_S_W = 2495, |
| SHLLV_S_W_MM = 2496, |
| SHLL_PH = 2497, |
| SHLL_PH_MM = 2498, |
| SHLL_QB = 2499, |
| SHLL_QB_MM = 2500, |
| SHLL_S_PH = 2501, |
| SHLL_S_PH_MM = 2502, |
| SHLL_S_W = 2503, |
| SHLL_S_W_MM = 2504, |
| SHRAV_PH = 2505, |
| SHRAV_PH_MM = 2506, |
| SHRAV_QB = 2507, |
| SHRAV_QB_MMR2 = 2508, |
| SHRAV_R_PH = 2509, |
| SHRAV_R_PH_MM = 2510, |
| SHRAV_R_QB = 2511, |
| SHRAV_R_QB_MMR2 = 2512, |
| SHRAV_R_W = 2513, |
| SHRAV_R_W_MM = 2514, |
| SHRA_PH = 2515, |
| SHRA_PH_MM = 2516, |
| SHRA_QB = 2517, |
| SHRA_QB_MMR2 = 2518, |
| SHRA_R_PH = 2519, |
| SHRA_R_PH_MM = 2520, |
| SHRA_R_QB = 2521, |
| SHRA_R_QB_MMR2 = 2522, |
| SHRA_R_W = 2523, |
| SHRA_R_W_MM = 2524, |
| SHRLV_PH = 2525, |
| SHRLV_PH_MMR2 = 2526, |
| SHRLV_QB = 2527, |
| SHRLV_QB_MM = 2528, |
| SHRL_PH = 2529, |
| SHRL_PH_MMR2 = 2530, |
| SHRL_QB = 2531, |
| SHRL_QB_MM = 2532, |
| SH_MM = 2533, |
| SH_MMR6 = 2534, |
| SIGRIE = 2535, |
| SIGRIE_MMR6 = 2536, |
| SLDI_B = 2537, |
| SLDI_D = 2538, |
| SLDI_H = 2539, |
| SLDI_W = 2540, |
| SLD_B = 2541, |
| SLD_D = 2542, |
| SLD_H = 2543, |
| SLD_W = 2544, |
| SLL = 2545, |
| SLL16_MM = 2546, |
| SLL16_MMR6 = 2547, |
| SLL64_32 = 2548, |
| SLL64_64 = 2549, |
| SLLI_B = 2550, |
| SLLI_D = 2551, |
| SLLI_H = 2552, |
| SLLI_W = 2553, |
| SLLV = 2554, |
| SLLV_MM = 2555, |
| SLL_B = 2556, |
| SLL_D = 2557, |
| SLL_H = 2558, |
| SLL_MM = 2559, |
| SLL_MMR6 = 2560, |
| SLL_W = 2561, |
| SLT = 2562, |
| SLT64 = 2563, |
| SLT_MM = 2564, |
| SLTi = 2565, |
| SLTi64 = 2566, |
| SLTi_MM = 2567, |
| SLTiu = 2568, |
| SLTiu64 = 2569, |
| SLTiu_MM = 2570, |
| SLTu = 2571, |
| SLTu64 = 2572, |
| SLTu_MM = 2573, |
| SNE = 2574, |
| SNEi = 2575, |
| SPLATI_B = 2576, |
| SPLATI_D = 2577, |
| SPLATI_H = 2578, |
| SPLATI_W = 2579, |
| SPLAT_B = 2580, |
| SPLAT_D = 2581, |
| SPLAT_H = 2582, |
| SPLAT_W = 2583, |
| SRA = 2584, |
| SRAI_B = 2585, |
| SRAI_D = 2586, |
| SRAI_H = 2587, |
| SRAI_W = 2588, |
| SRARI_B = 2589, |
| SRARI_D = 2590, |
| SRARI_H = 2591, |
| SRARI_W = 2592, |
| SRAR_B = 2593, |
| SRAR_D = 2594, |
| SRAR_H = 2595, |
| SRAR_W = 2596, |
| SRAV = 2597, |
| SRAV_MM = 2598, |
| SRA_B = 2599, |
| SRA_D = 2600, |
| SRA_H = 2601, |
| SRA_MM = 2602, |
| SRA_W = 2603, |
| SRL = 2604, |
| SRL16_MM = 2605, |
| SRL16_MMR6 = 2606, |
| SRLI_B = 2607, |
| SRLI_D = 2608, |
| SRLI_H = 2609, |
| SRLI_W = 2610, |
| SRLRI_B = 2611, |
| SRLRI_D = 2612, |
| SRLRI_H = 2613, |
| SRLRI_W = 2614, |
| SRLR_B = 2615, |
| SRLR_D = 2616, |
| SRLR_H = 2617, |
| SRLR_W = 2618, |
| SRLV = 2619, |
| SRLV_MM = 2620, |
| SRL_B = 2621, |
| SRL_D = 2622, |
| SRL_H = 2623, |
| SRL_MM = 2624, |
| SRL_W = 2625, |
| SSNOP = 2626, |
| SSNOP_MM = 2627, |
| SSNOP_MMR6 = 2628, |
| ST_B = 2629, |
| ST_D = 2630, |
| ST_H = 2631, |
| ST_W = 2632, |
| SUB = 2633, |
| SUBQH_PH = 2634, |
| SUBQH_PH_MMR2 = 2635, |
| SUBQH_R_PH = 2636, |
| SUBQH_R_PH_MMR2 = 2637, |
| SUBQH_R_W = 2638, |
| SUBQH_R_W_MMR2 = 2639, |
| SUBQH_W = 2640, |
| SUBQH_W_MMR2 = 2641, |
| SUBQ_PH = 2642, |
| SUBQ_PH_MM = 2643, |
| SUBQ_S_PH = 2644, |
| SUBQ_S_PH_MM = 2645, |
| SUBQ_S_W = 2646, |
| SUBQ_S_W_MM = 2647, |
| SUBSUS_U_B = 2648, |
| SUBSUS_U_D = 2649, |
| SUBSUS_U_H = 2650, |
| SUBSUS_U_W = 2651, |
| SUBSUU_S_B = 2652, |
| SUBSUU_S_D = 2653, |
| SUBSUU_S_H = 2654, |
| SUBSUU_S_W = 2655, |
| SUBS_S_B = 2656, |
| SUBS_S_D = 2657, |
| SUBS_S_H = 2658, |
| SUBS_S_W = 2659, |
| SUBS_U_B = 2660, |
| SUBS_U_D = 2661, |
| SUBS_U_H = 2662, |
| SUBS_U_W = 2663, |
| SUBU16_MM = 2664, |
| SUBU16_MMR6 = 2665, |
| SUBUH_QB = 2666, |
| SUBUH_QB_MMR2 = 2667, |
| SUBUH_R_QB = 2668, |
| SUBUH_R_QB_MMR2 = 2669, |
| SUBU_MMR6 = 2670, |
| SUBU_PH = 2671, |
| SUBU_PH_MMR2 = 2672, |
| SUBU_QB = 2673, |
| SUBU_QB_MM = 2674, |
| SUBU_S_PH = 2675, |
| SUBU_S_PH_MMR2 = 2676, |
| SUBU_S_QB = 2677, |
| SUBU_S_QB_MM = 2678, |
| SUBVI_B = 2679, |
| SUBVI_D = 2680, |
| SUBVI_H = 2681, |
| SUBVI_W = 2682, |
| SUBV_B = 2683, |
| SUBV_D = 2684, |
| SUBV_H = 2685, |
| SUBV_W = 2686, |
| SUB_MM = 2687, |
| SUB_MMR6 = 2688, |
| SUBu = 2689, |
| SUBu_MM = 2690, |
| SUXC1 = 2691, |
| SUXC164 = 2692, |
| SUXC1_MM = 2693, |
| SW = 2694, |
| SW16_MM = 2695, |
| SW16_MMR6 = 2696, |
| SW64 = 2697, |
| SWC1 = 2698, |
| SWC1_MM = 2699, |
| SWC2 = 2700, |
| SWC2_MMR6 = 2701, |
| SWC2_R6 = 2702, |
| SWC3 = 2703, |
| SWDSP = 2704, |
| SWDSP_MM = 2705, |
| SWE = 2706, |
| SWE_MM = 2707, |
| SWL = 2708, |
| SWL64 = 2709, |
| SWLE = 2710, |
| SWLE_MM = 2711, |
| SWL_MM = 2712, |
| SWM16_MM = 2713, |
| SWM16_MMR6 = 2714, |
| SWM32_MM = 2715, |
| SWP_MM = 2716, |
| SWR = 2717, |
| SWR64 = 2718, |
| SWRE = 2719, |
| SWRE_MM = 2720, |
| SWR_MM = 2721, |
| SWSP_MM = 2722, |
| SWSP_MMR6 = 2723, |
| SWXC1 = 2724, |
| SWXC1_MM = 2725, |
| SW_MM = 2726, |
| SW_MMR6 = 2727, |
| SYNC = 2728, |
| SYNCI = 2729, |
| SYNCI_MM = 2730, |
| SYNCI_MMR6 = 2731, |
| SYNC_MM = 2732, |
| SYNC_MMR6 = 2733, |
| SYSCALL = 2734, |
| SYSCALL_MM = 2735, |
| Save16 = 2736, |
| SaveX16 = 2737, |
| SbRxRyOffMemX16 = 2738, |
| SebRx16 = 2739, |
| SehRx16 = 2740, |
| ShRxRyOffMemX16 = 2741, |
| SllX16 = 2742, |
| SllvRxRy16 = 2743, |
| SltRxRy16 = 2744, |
| SltiRxImm16 = 2745, |
| SltiRxImmX16 = 2746, |
| SltiuRxImm16 = 2747, |
| SltiuRxImmX16 = 2748, |
| SltuRxRy16 = 2749, |
| SraX16 = 2750, |
| SravRxRy16 = 2751, |
| SrlX16 = 2752, |
| SrlvRxRy16 = 2753, |
| SubuRxRyRz16 = 2754, |
| SwRxRyOffMemX16 = 2755, |
| SwRxSpImmX16 = 2756, |
| TEQ = 2757, |
| TEQI = 2758, |
| TEQI_MM = 2759, |
| TEQ_MM = 2760, |
| TGE = 2761, |
| TGEI = 2762, |
| TGEIU = 2763, |
| TGEIU_MM = 2764, |
| TGEI_MM = 2765, |
| TGEU = 2766, |
| TGEU_MM = 2767, |
| TGE_MM = 2768, |
| TLBGINV = 2769, |
| TLBGINVF = 2770, |
| TLBGINVF_MM = 2771, |
| TLBGINV_MM = 2772, |
| TLBGP = 2773, |
| TLBGP_MM = 2774, |
| TLBGR = 2775, |
| TLBGR_MM = 2776, |
| TLBGWI = 2777, |
| TLBGWI_MM = 2778, |
| TLBGWR = 2779, |
| TLBGWR_MM = 2780, |
| TLBINV = 2781, |
| TLBINVF = 2782, |
| TLBINVF_MMR6 = 2783, |
| TLBINV_MMR6 = 2784, |
| TLBP = 2785, |
| TLBP_MM = 2786, |
| TLBR = 2787, |
| TLBR_MM = 2788, |
| TLBWI = 2789, |
| TLBWI_MM = 2790, |
| TLBWR = 2791, |
| TLBWR_MM = 2792, |
| TLT = 2793, |
| TLTI = 2794, |
| TLTIU_MM = 2795, |
| TLTI_MM = 2796, |
| TLTU = 2797, |
| TLTU_MM = 2798, |
| TLT_MM = 2799, |
| TNE = 2800, |
| TNEI = 2801, |
| TNEI_MM = 2802, |
| TNE_MM = 2803, |
| TRUNC_L_D64 = 2804, |
| TRUNC_L_D_MMR6 = 2805, |
| TRUNC_L_S = 2806, |
| TRUNC_L_S_MMR6 = 2807, |
| TRUNC_W_D32 = 2808, |
| TRUNC_W_D64 = 2809, |
| TRUNC_W_D_MMR6 = 2810, |
| TRUNC_W_MM = 2811, |
| TRUNC_W_S = 2812, |
| TRUNC_W_S_MM = 2813, |
| TRUNC_W_S_MMR6 = 2814, |
| TTLTIU = 2815, |
| UDIV = 2816, |
| UDIV_MM = 2817, |
| V3MULU = 2818, |
| VMM0 = 2819, |
| VMULU = 2820, |
| VSHF_B = 2821, |
| VSHF_D = 2822, |
| VSHF_H = 2823, |
| VSHF_W = 2824, |
| WAIT = 2825, |
| WAIT_MM = 2826, |
| WAIT_MMR6 = 2827, |
| WRDSP = 2828, |
| WRDSP_MM = 2829, |
| WRPGPR_MMR6 = 2830, |
| WSBH = 2831, |
| WSBH_MM = 2832, |
| WSBH_MMR6 = 2833, |
| XOR = 2834, |
| XOR16_MM = 2835, |
| XOR16_MMR6 = 2836, |
| XOR64 = 2837, |
| XORI_B = 2838, |
| XORI_MMR6 = 2839, |
| XOR_MM = 2840, |
| XOR_MMR6 = 2841, |
| XOR_V = 2842, |
| XORi = 2843, |
| XORi64 = 2844, |
| XORi_MM = 2845, |
| XorRxRxRy16 = 2846, |
| YIELD = 2847, |
| INSTRUCTION_LIST_END = 2848 |
| }; |
| |
| } // end namespace Mips |
| } // end namespace llvm |
| #endif // GET_INSTRINFO_ENUM |
| |
| #ifdef GET_INSTRINFO_SCHED_ENUM |
| #undef GET_INSTRINFO_SCHED_ENUM |
| namespace llvm { |
| |
| namespace Mips { |
| namespace Sched { |
| enum { |
| NoInstrModel = 0, |
| IIPseudo = 1, |
| II_B = 2, |
| II_BCCZAL = 3, |
| II_MTC1 = 4, |
| II_MFC1 = 5, |
| II_JALR = 6, |
| II_JAL = 7, |
| II_CVT = 8, |
| II_DMULT = 9, |
| II_DMULTU = 10, |
| II_DDIV = 11, |
| II_DDIVU = 12, |
| II_IndirectBranchPseudo = 13, |
| II_MADD = 14, |
| II_MADDU = 15, |
| II_MFHI_MFLO = 16, |
| II_MSUB = 17, |
| II_MSUBU = 18, |
| II_MTHI_MTLO = 19, |
| II_MULT = 20, |
| II_MULTU = 21, |
| II_ReturnPseudo = 22, |
| II_DIV = 23, |
| II_DIVU = 24, |
| II_J = 25, |
| II_JR = 26, |
| II_TRAP = 27, |
| II_ADD = 28, |
| II_ADDIUPC = 29, |
| II_ADDIU = 30, |
| II_ADDR_PS = 31, |
| II_ADDU = 32, |
| II_ADDI = 33, |
| II_ALIGN = 34, |
| II_ALUIPC = 35, |
| II_AND = 36, |
| II_ANDI = 37, |
| II_AUI = 38, |
| II_AUIPC = 39, |
| IIM16Alu = 40, |
| II_BADDU = 41, |
| II_BC = 42, |
| II_BALC = 43, |
| II_BBIT = 44, |
| II_BC1CCZ = 45, |
| II_BC1F = 46, |
| II_BC1FL = 47, |
| II_BC1T = 48, |
| II_BC1TL = 49, |
| II_BC2CCZ = 50, |
| II_BCC = 51, |
| II_BCCC = 52, |
| II_BCCZ = 53, |
| II_BCCZC = 54, |
| II_BCCZALS = 55, |
| II_BITSWAP = 56, |
| II_BREAK = 57, |
| II_CACHE = 58, |
| II_CACHEE = 59, |
| II_CEIL = 60, |
| II_CFC1 = 61, |
| II_CFC2 = 62, |
| II_INS = 63, |
| II_CLASS_D = 64, |
| II_CLASS_S = 65, |
| II_CLO = 66, |
| II_CLZ = 67, |
| II_CMP_CC_D = 68, |
| II_CMP_CC_S = 69, |
| II_CRC32B = 70, |
| II_CRC32CB = 71, |
| II_CRC32CD = 72, |
| II_CRC32CH = 73, |
| II_CRC32CW = 74, |
| II_CRC32D = 75, |
| II_CRC32H = 76, |
| II_CRC32W = 77, |
| II_CTC1 = 78, |
| II_CTC2 = 79, |
| II_C_CC_D = 80, |
| II_C_CC_S = 81, |
| II_DADD = 82, |
| II_DADDI = 83, |
| II_DADDIU = 84, |
| II_DADDU = 85, |
| II_DAHI = 86, |
| II_DALIGN = 87, |
| II_DATI = 88, |
| II_DAUI = 89, |
| II_DBITSWAP = 90, |
| II_DCLO = 91, |
| II_DCLZ = 92, |
| II_DERET = 93, |
| II_EXT = 94, |
| II_DI = 95, |
| II_DLSA = 96, |
| II_DMFC0 = 97, |
| II_DMFC1 = 98, |
| II_DMFC2 = 99, |
| II_DMFGC0 = 100, |
| II_DMOD = 101, |
| II_DMODU = 102, |
| II_DMT = 103, |
| II_DMTC0 = 104, |
| II_DMTC1 = 105, |
| II_DMTC2 = 106, |
| II_DMTGC0 = 107, |
| II_DMUH = 108, |
| II_DMUHU = 109, |
| II_DMUL = 110, |
| II_POP = 111, |
| II_DROTR = 112, |
| II_DROTR32 = 113, |
| II_DROTRV = 114, |
| II_DSBH = 115, |
| II_DSHD = 116, |
| II_DSLL = 117, |
| II_DSLL32 = 118, |
| II_DSLLV = 119, |
| II_DSRA = 120, |
| II_DSRA32 = 121, |
| II_DSRAV = 122, |
| II_DSRL = 123, |
| II_DSRL32 = 124, |
| II_DSRLV = 125, |
| II_DSUB = 126, |
| II_DSUBU = 127, |
| II_DVP = 128, |
| II_DVPE = 129, |
| II_EHB = 130, |
| II_EI = 131, |
| II_EMT = 132, |
| II_ERET = 133, |
| II_ERETNC = 134, |
| II_EVP = 135, |
| II_EVPE = 136, |
| II_ABS = 137, |
| II_SQRT_D = 138, |
| II_ADD_D = 139, |
| II_ADD_PS = 140, |
| II_ADD_S = 141, |
| II_DIV_D = 142, |
| II_DIV_S = 143, |
| II_FLOOR = 144, |
| II_MOV_D = 145, |
| II_MOV_S = 146, |
| II_MUL_D = 147, |
| II_MUL_PS = 148, |
| II_MUL_S = 149, |
| II_NEG = 150, |
| II_FORK = 151, |
| II_SQRT_S = 152, |
| II_SUB_D = 153, |
| II_SUB_PS = 154, |
| II_SUB_S = 155, |
| II_GINVI = 156, |
| II_GINVT = 157, |
| II_HYPCALL = 158, |
| II_JALR_HB = 159, |
| II_JALRC = 160, |
| II_JALRS = 161, |
| II_JALS = 162, |
| II_JIALC = 163, |
| II_JIC = 164, |
| II_JRADDIUSP = 165, |
| II_JRC = 166, |
| II_JR_HB = 167, |
| II_LB = 168, |
| II_LBE = 169, |
| II_LBU = 170, |
| II_LBUE = 171, |
| II_LD = 172, |
| II_LDC1 = 173, |
| II_LDC2 = 174, |
| II_LDC3 = 175, |
| II_LDL = 176, |
| II_LDPC = 177, |
| II_LDR = 178, |
| II_LDXC1 = 179, |
| II_LH = 180, |
| II_LHE = 181, |
| II_LHU = 182, |
| II_LHUE = 183, |
| II_LI = 184, |
| II_LL = 185, |
| II_LLD = 186, |
| II_LLE = 187, |
| II_LSA = 188, |
| II_LUI = 189, |
| II_LUXC1 = 190, |
| II_LW = 191, |
| II_LWC1 = 192, |
| II_LWC2 = 193, |
| II_LWC3 = 194, |
| II_LWE = 195, |
| II_LWL = 196, |
| II_LWLE = 197, |
| II_LWM = 198, |
| II_LWPC = 199, |
| II_LWP = 200, |
| II_LWR = 201, |
| II_LWRE = 202, |
| II_LWUPC = 203, |
| II_LWU = 204, |
| II_LWXC1 = 205, |
| II_LWXS = 206, |
| II_MADDF_D = 207, |
| II_MADDF_S = 208, |
| II_MADD_D = 209, |
| II_MADD_S = 210, |
| II_MAX_D = 211, |
| II_MAXA_D = 212, |
| II_MAX_S = 213, |
| II_MAXA_S = 214, |
| II_MFC0 = 215, |
| II_MFC2 = 216, |
| II_MFGC0 = 217, |
| II_MFHC0 = 218, |
| II_MFHC1 = 219, |
| II_MFHGC0 = 220, |
| II_MFTR = 221, |
| II_MIN_S = 222, |
| II_MINA_D = 223, |
| II_MIN_D = 224, |
| II_MINA_S = 225, |
| II_MOD = 226, |
| II_MODU = 227, |
| II_MOVE = 228, |
| II_MOVF_D = 229, |
| II_MOVF = 230, |
| II_MOVF_S = 231, |
| II_MOVN_D = 232, |
| II_MOVN = 233, |
| II_MOVN_S = 234, |
| II_MOVT_D = 235, |
| II_MOVT = 236, |
| II_MOVT_S = 237, |
| II_MOVZ_D = 238, |
| II_MOVZ = 239, |
| II_MOVZ_S = 240, |
| II_MSUBF_D = 241, |
| II_MSUBF_S = 242, |
| II_MSUB_D = 243, |
| II_MSUB_S = 244, |
| II_MTC0 = 245, |
| II_MTC2 = 246, |
| II_MTGC0 = 247, |
| II_MTHC0 = 248, |
| II_MTHC1 = 249, |
| II_MTHGC0 = 250, |
| II_MTTR = 251, |
| II_MUH = 252, |
| II_MUHU = 253, |
| II_MUL = 254, |
| II_MULR_PS = 255, |
| II_MULU = 256, |
| II_NMADD_D = 257, |
| II_NMADD_S = 258, |
| II_NMSUB_D = 259, |
| II_NMSUB_S = 260, |
| II_NOR = 261, |
| II_NOT = 262, |
| II_OR = 263, |
| II_ORI = 264, |
| II_PAUSE = 265, |
| II_PREF = 266, |
| II_PREFE = 267, |
| II_RDHWR = 268, |
| II_RDPGPR = 269, |
| II_RECIP_D = 270, |
| II_RECIP_S = 271, |
| II_RINT_D = 272, |
| II_RINT_S = 273, |
| II_ROTR = 274, |
| II_ROTRV = 275, |
| II_ROUND = 276, |
| II_RSQRT_D = 277, |
| II_RSQRT_S = 278, |
| II_RESTORE = 279, |
| II_SB = 280, |
| II_SBE = 281, |
| II_SC = 282, |
| II_SCD = 283, |
| II_SCE = 284, |
| II_SD = 285, |
| II_SDBBP = 286, |
| II_SDC1 = 287, |
| II_SDC2 = 288, |
| II_SDC3 = 289, |
| II_SDL = 290, |
| II_SDR = 291, |
| II_SDXC1 = 292, |
| II_SEB = 293, |
| II_SEH = 294, |
| II_SELCCZ = 295, |
| II_SELCCZ_D = 296, |
| II_SELCCZ_S = 297, |
| II_SEL_D = 298, |
| II_SEL_S = 299, |
| II_SEQ_SNE = 300, |
| II_SEQI_SNEI = 301, |
| II_SH = 302, |
| II_SHE = 303, |
| II_SIGRIE = 304, |
| II_SLL = 305, |
| II_SLLV = 306, |
| II_SLT_SLTU = 307, |
| II_SLTI_SLTIU = 308, |
| II_SRA = 309, |
| II_SRAV = 310, |
| II_SRL = 311, |
| II_SRLV = 312, |
| II_SSNOP = 313, |
| II_SUB = 314, |
| II_SUBU = 315, |
| II_SUXC1 = 316, |
| II_SW = 317, |
| II_SWC1 = 318, |
| II_SWC2 = 319, |
| II_SWC3 = 320, |
| II_SWE = 321, |
| II_SWL = 322, |
| II_SWLE = 323, |
| II_SWM = 324, |
| II_SWP = 325, |
| II_SWR = 326, |
| II_SWRE = 327, |
| II_SWXC1 = 328, |
| II_SYNC = 329, |
| II_SYNCI = 330, |
| II_SYSCALL = 331, |
| II_SAVE = 332, |
| II_TEQ = 333, |
| II_TEQI = 334, |
| II_TGE = 335, |
| II_TGEI = 336, |
| II_TGEIU = 337, |
| II_TGEU = 338, |
| II_TLBGINV = 339, |
| II_TLBGINVF = 340, |
| II_TLBGP = 341, |
| II_TLBGR = 342, |
| II_TLBGWI = 343, |
| II_TLBGWR = 344, |
| II_TLBINV = 345, |
| II_TLBINVF = 346, |
| II_TLBP = 347, |
| II_TLBR = 348, |
| II_TLBWI = 349, |
| II_TLBWR = 350, |
| II_TLT = 351, |
| II_TLTI = 352, |
| II_TTLTIU = 353, |
| II_TLTU = 354, |
| II_TNE = 355, |
| II_TNEI = 356, |
| II_TRUNC = 357, |
| II_WAIT = 358, |
| II_WRPGPR = 359, |
| II_WSBH = 360, |
| II_XOR = 361, |
| II_XORI = 362, |
| II_YIELD = 363, |
| AND = 364, |
| LUi = 365, |
| NOR = 366, |
| OR = 367, |
| SLTi_SLTiu = 368, |
| SUB = 369, |
| SUBu = 370, |
| XOR = 371, |
| SSNOP = 372, |
| NOP = 373, |
| B = 374, |
| BAL = 375, |
| BAL_BR_BGEZAL_BGEZALL_BLTZAL_BLTZALL = 376, |
| BEQ_BEQL_BNE_BNEL = 377, |
| BGEZ_BGEZL_BGTZ_BGTZL_BLEZ_BLEZL_BLTZ_BLTZL = 378, |
| BREAK = 379, |
| DERET = 380, |
| ERET = 381, |
| ERet_RetRA = 382, |
| ERETNC = 383, |
| J_TAILCALL = 384, |
| JR_TAILCALLREG_TAILCALLREGHB = 385, |
| JR_HB = 386, |
| PseudoIndirectBranch_PseudoIndirectHazardBranch = 387, |
| PseudoReturn = 388, |
| SDBBP = 389, |
| SYSCALL = 390, |
| TEQ = 391, |
| TEQI = 392, |
| TGE = 393, |
| TGEI = 394, |
| TGEIU = 395, |
| TGEU = 396, |
| TLT = 397, |
| TLTI = 398, |
| TLTU = 399, |
| TNE = 400, |
| TNEI = 401, |
| TRAP = 402, |
| TTLTIU = 403, |
| WAIT = 404, |
| PAUSE = 405, |
| JAL = 406, |
| JALR_JALRHBPseudo_JALRPseudo = 407, |
| JALR_HB = 408, |
| JALX = 409, |
| TLBINV = 410, |
| TLBINVF = 411, |
| TLBP = 412, |
| TLBR = 413, |
| TLBWI = 414, |
| TLBWR = 415, |
| MFC0 = 416, |
| MTC0 = 417, |
| MFC2 = 418, |
| MTC2 = 419, |
| HYPCALL = 420, |
| MFGC0 = 421, |
| MFHGC0 = 422, |
| MTGC0 = 423, |
| MTHGC0 = 424, |
| TLBGINV = 425, |
| TLBGINVF = 426, |
| TLBGP = 427, |
| TLBGR = 428, |
| TLBGWI = 429, |
| TLBGWR = 430, |
| LB = 431, |
| LBu = 432, |
| LH = 433, |
| LHu = 434, |
| LW = 435, |
| LL = 436, |
| LWC2 = 437, |
| LWC3 = 438, |
| LDC2 = 439, |
| LDC3 = 440, |
| LBE = 441, |
| LBuE = 442, |
| LHE = 443, |
| LHuE = 444, |
| LWE = 445, |
| LLE = 446, |
| LWPC = 447, |
| LWL = 448, |
| LWR = 449, |
| LWLE = 450, |
| LWRE = 451, |
| SB = 452, |
| SH = 453, |
| SW = 454, |
| SWC2 = 455, |
| SWC3 = 456, |
| SDC2 = 457, |
| SDC3 = 458, |
| SC = 459, |
| SBE = 460, |
| SHE = 461, |
| SWE = 462, |
| SCE = 463, |
| SWL = 464, |
| SWR = 465, |
| SWLE = 466, |
| SWRE = 467, |
| PREF = 468, |
| PREFE = 469, |
| CACHE = 470, |
| CACHEE = 471, |
| SYNC = 472, |
| SYNCI = 473, |
| CLO = 474, |
| CLZ = 475, |
| DI = 476, |
| EI = 477, |
| MFHI_MFLO_PseudoMFHI_PseudoMFLO = 478, |
| EHB = 479, |
| RDHWR = 480, |
| WSBH = 481, |
| MOVN_I_I = 482, |
| MOVZ_I_I = 483, |
| DIV_PseudoSDIV_SDIV = 484, |
| DIVU_PseudoUDIV_UDIV = 485, |
| MUL = 486, |
| MULT_PseudoMULT = 487, |
| MULTu_PseudoMULTu = 488, |
| MADD_PseudoMADD = 489, |
| MADDU_PseudoMADDU = 490, |
| MSUB_PseudoMSUB = 491, |
| MSUBU_PseudoMSUBU = 492, |
| MTHI_MTLO_PseudoMTLOHI = 493, |
| EXT = 494, |
| INS = 495, |
| ADD = 496, |
| ADDi = 497, |
| ADDiu = 498, |
| ANDi = 499, |
| ORi = 500, |
| ROTR = 501, |
| SEB = 502, |
| SEH = 503, |
| SLT_SLTu = 504, |
| SLL = 505, |
| SRA = 506, |
| SRL = 507, |
| XORi = 508, |
| ADDu = 509, |
| SLLV = 510, |
| SRAV = 511, |
| SRLV = 512, |
| LSA = 513, |
| COPY = 514, |
| VSHF_B_VSHF_D_VSHF_H_VSHF_W = 515, |
| BINSLI_B_BINSLI_D_BINSLI_H_BINSLI_W_BINSL_B_BINSL_D_BINSL_H_BINSL_W = 516, |
| BINSRI_B_BINSRI_D_BINSRI_H_BINSRI_W_BINSR_B_BINSR_D_BINSR_H_BINSR_W = 517, |
| INSERT_B_INSERT_D_INSERT_H_INSERT_W = 518, |
| SLDI_B_SLDI_D_SLDI_H_SLDI_W_SLD_B_SLD_D_SLD_H_SLD_W = 519, |
| BSETI_B_BSETI_D_BSETI_H_BSETI_W_BSET_B_BSET_D_BSET_H_BSET_W = 520, |
| BCLRI_B_BCLRI_D_BCLRI_H_BCLRI_W_BCLR_B_BCLR_D_BCLR_H_BCLR_W = 521, |
| BNEGI_B_BNEGI_D_BNEGI_H_BNEGI_W_BNEG_B_BNEG_D_BNEG_H_BNEG_W = 522, |
| BSELI_B_BSEL_V = 523, |
| BMNZI_B_BMNZ_V_BMZI_B_BMZ_V = 524, |
| BSEL_D_PSEUDO_BSEL_FD_PSEUDO_BSEL_FW_PSEUDO_BSEL_H_PSEUDO_BSEL_W_PSEUDO = 525, |
| PCNT_B_PCNT_D_PCNT_H_PCNT_W = 526, |
| SAT_S_B_SAT_S_D_SAT_S_H_SAT_S_W_SAT_U_B_SAT_U_D_SAT_U_H_SAT_U_W = 527, |
| BNZ_B_BNZ_D_BNZ_H_BNZ_V_BNZ_W_BZ_B_BZ_D_BZ_H_BZ_V_BZ_W = 528, |
| CFCMSA_CTCMSA = 529, |
| FABS_S_FABS_D32_FABS_D64 = 530, |
| MOVF_D32_MOVF_D64 = 531, |
| MOVF_S = 532, |
| MOVT_D32_MOVT_D64 = 533, |
| MOVT_S = 534, |
| FMOV_D32_FMOV_D64 = 535, |
| FMOV_S = 536, |
| FNEG_S_FNEG_D32_FNEG_D64 = 537, |
| ADD_A_B_ADD_A_D_ADD_A_H_ADD_A_W = 538, |
| ADDS_A_B_ADDS_A_D_ADDS_A_H_ADDS_A_W_ADDS_S_B_ADDS_S_D_ADDS_S_H_ADDS_S_W_ADDS_U_B_ADDS_U_D_ADDS_U_H_ADDS_U_W = 539, |
| ADDVI_B_ADDVI_D_ADDVI_H_ADDVI_W_ADDV_B_ADDV_D_ADDV_H_ADDV_W = 540, |
| ASUB_S_B_ASUB_S_D_ASUB_S_H_ASUB_S_W_ASUB_U_B_ASUB_U_D_ASUB_U_H_ASUB_U_W = 541, |
| AVER_S_B_AVER_S_D_AVER_S_H_AVER_S_W_AVER_U_B_AVER_U_D_AVER_U_H_AVER_U_W_AVE_S_B_AVE_S_D_AVE_S_H_AVE_S_W_AVE_U_B_AVE_U_D_AVE_U_H_AVE_U_W = 542, |
| SHF_B_SHF_H_SHF_W = 543, |
| FILL_B_FILL_D_FILL_H_FILL_W = 544, |
| SPLATI_B_SPLATI_D_SPLATI_H_SPLATI_W_SPLAT_B_SPLAT_D_SPLAT_H_SPLAT_W = 545, |
| MOVE_V = 546, |
| LDI_B_LDI_D_LDI_H_LDI_W = 547, |
| AND_V_NOR_V_OR_V_XOR_V = 548, |
| ANDI_B_NORI_B_ORI_B_XORI_B = 549, |
| AND_V_D_PSEUDO_AND_V_H_PSEUDO_AND_V_W_PSEUDO_NOR_V_D_PSEUDO_NOR_V_H_PSEUDO_NOR_V_W_PSEUDO_OR_V_D_PSEUDO_OR_V_H_PSEUDO_OR_V_W_PSEUDO_XOR_V_D_PSEUDO_XOR_V_H_PSEUDO_XOR_V_W_PSEUDO = 550, |
| FILL_FD_PSEUDO_FILL_FW_PSEUDO = 551, |
| INSERT_FD_PSEUDO_INSERT_FW_PSEUDO = 552, |
| FEXP2_D_FEXP2_W = 553, |
| CLTI_S_B_CLTI_S_D_CLTI_S_H_CLTI_S_W_CLTI_U_B_CLTI_U_D_CLTI_U_H_CLTI_U_W_CLT_S_B_CLT_S_D_CLT_S_H_CLT_S_W_CLT_U_B_CLT_U_D_CLT_U_H_CLT_U_W = 554, |
| CLEI_S_B_CLEI_S_D_CLEI_S_H_CLEI_S_W_CLEI_U_B_CLEI_U_D_CLEI_U_H_CLEI_U_W_CLE_S_B_CLE_S_D_CLE_S_H_CLE_S_W_CLE_U_B_CLE_U_D_CLE_U_H_CLE_U_W = 555, |
| CEQI_B_CEQI_D_CEQI_H_CEQI_W_CEQ_B_CEQ_D_CEQ_H_CEQ_W = 556, |
| CMP_UN_D = 557, |
| CMP_UN_S = 558, |
| CMP_UEQ_D = 559, |
| CMP_UEQ_S = 560, |
| CMP_EQ_D = 561, |
| CMP_EQ_S = 562, |
| CMP_LT_D = 563, |
| CMP_LT_S = 564, |
| CMP_ULT_D = 565, |
| CMP_ULT_S = 566, |
| CMP_LE_D = 567, |
| CMP_LE_S = 568, |
| CMP_ULE_D = 569, |
| CMP_ULE_S = 570, |
| FSAF_D_FSAF_W_FSEQ_D_FSEQ_W_FSLE_D_FSLE_W_FSLT_D_FSLT_W_FSNE_D_FSNE_W_FSOR_D_FSOR_W = 571, |
| FSUEQ_D_FSUEQ_W = 572, |
| FSULE_D_FSULE_W = 573, |
| FSULT_D_FSULT_W = 574, |
| FSUNE_D_FSUNE_W = 575, |
| FSUN_D_FSUN_W = 576, |
| FCAF_D_FCAF_W = 577, |
| FCEQ_D_FCEQ_W = 578, |
| FCLE_D_FCLE_W = 579, |
| FCLT_D_FCLT_W = 580, |
| FCNE_D_FCNE_W = 581, |
| FCOR_D_FCOR_W = 582, |
| FCUEQ_D_FCUEQ_W = 583, |
| FCULE_D_FCULE_W = 584, |
| FCULT_D_FCULT_W = 585, |
| FCUNE_D_FCUNE_W = 586, |
| FCUN_D_FCUN_W = 587, |
| FABS_D_FABS_W = 588, |
| FFINT_S_D_FFINT_S_W_FFINT_U_D_FFINT_U_W = 589, |
| FFQL_D_FFQL_W = 590, |
| FFQR_D_FFQR_W = 591, |
| FTINT_S_D_FTINT_S_W_FTINT_U_D_FTINT_U_W = 592, |
| FRINT_D_FRINT_W = 593, |
| FTQ_H_FTQ_W = 594, |
| FTRUNC_S_D_FTRUNC_S_W_FTRUNC_U_D_FTRUNC_U_W = 595, |
| FEXDO_H_FEXDO_W = 596, |
| FEXUPL_D_FEXUPL_W = 597, |
| FEXUPR_D_FEXUPR_W = 598, |
| FCLASS_D_FCLASS_W = 599, |
| FMAX_A_D_FMAX_A_W = 600, |
| FMAX_D_FMAX_W = 601, |
| FMIN_A_D_FMIN_A_W = 602, |
| FMIN_D_FMIN_W = 603, |
| FLOG2_D_FLOG2_W = 604, |
| ILVL_B_ILVL_D_ILVL_H_ILVL_W_ILVR_B_ILVR_D_ILVR_H_ILVR_W = 605, |
| ILVEV_B_ILVEV_D_ILVEV_H_ILVEV_W_ILVOD_B_ILVOD_D_ILVOD_H_ILVOD_W = 606, |
| INSVE_B_INSVE_D_INSVE_H_INSVE_W = 607, |
| SUBS_S_B_SUBS_S_D_SUBS_S_H_SUBS_S_W_SUBS_U_B_SUBS_U_D_SUBS_U_H_SUBS_U_W = 608, |
| SUBSUS_U_B_SUBSUS_U_D_SUBSUS_U_H_SUBSUS_U_W = 609, |
| SUBSUU_S_B_SUBSUU_S_D_SUBSUU_S_H_SUBSUU_S_W = 610, |
| SUBVI_B_SUBVI_D_SUBVI_H_SUBVI_W = 611, |
| SUBV_B_SUBV_D_SUBV_H_SUBV_W = 612, |
| MOD_S_B_MOD_S_D_MOD_S_H_MOD_S_W_MOD_U_B_MOD_U_D_MOD_U_H_MOD_U_W = 613, |
| DIV_S_B_DIV_S_D_DIV_S_H_DIV_S_W_DIV_U_B_DIV_U_D_DIV_U_H_DIV_U_W = 614, |
| HADD_S_D_HADD_S_H_HADD_S_W_HADD_U_D_HADD_U_H_HADD_U_W = 615, |
| HSUB_S_D_HSUB_S_H_HSUB_S_W_HSUB_U_D_HSUB_U_H_HSUB_U_W = 616, |
| MAX_S_B_MAX_S_D_MAX_S_H_MAX_S_W_MIN_S_B_MIN_S_D_MIN_S_H_MIN_S_W = 617, |
| MAX_U_B_MAX_U_D_MAX_U_H_MAX_U_W_MIN_U_B_MIN_U_D_MIN_U_H_MIN_U_W = 618, |
| MAX_A_B_MAX_A_D_MAX_A_H_MAX_A_W_MIN_A_B_MIN_A_D_MIN_A_H_MIN_A_W = 619, |
| MAXI_S_B_MAXI_S_D_MAXI_S_H_MAXI_S_W_MAXI_U_B_MAXI_U_D_MAXI_U_H_MAXI_U_W_MINI_S_B_MINI_S_D_MINI_S_H_MINI_S_W_MINI_U_B_MINI_U_D_MINI_U_H_MINI_U_W = 620, |
| SRAI_B_SRAI_D_SRAI_H_SRAI_W_SRA_B_SRA_D_SRA_H_SRA_W = 621, |
| SRLI_B_SRLI_D_SRLI_H_SRLI_W_SRL_B_SRL_D_SRL_H_SRL_W = 622, |
| SRARI_B_SRARI_D_SRARI_H_SRARI_W_SRAR_B_SRAR_D_SRAR_H_SRAR_W = 623, |
| SRLRI_B_SRLRI_D_SRLRI_H_SRLRI_W_SRLR_B_SRLR_D_SRLR_H_SRLR_W = 624, |
| SLLI_B_SLLI_D_SLLI_H_SLLI_W_SLL_B_SLL_D_SLL_H_SLL_W = 625, |
| PCKEV_B_PCKEV_D_PCKEV_H_PCKEV_W_PCKOD_B_PCKOD_D_PCKOD_H_PCKOD_W = 626, |
| NLOC_B_NLOC_D_NLOC_H_NLOC_W_NLZC_B_NLZC_D_NLZC_H_NLZC_W = 627, |
| FADD_D32_FADD_D64 = 628, |
| FADD_PS64 = 629, |
| FADD_S = 630, |
| FMUL_D32_FMUL_D64 = 631, |
| FMUL_PS64 = 632, |
| FMUL_S = 633, |
| FSUB_D32_FSUB_D64 = 634, |
| FSUB_PS64 = 635, |
| FSUB_S = 636, |
| TRUNC_L_D64_TRUNC_L_S_TRUNC_W_D32_TRUNC_W_D64_TRUNC_W_S = 637, |
| CVT_D32_S_CVT_D32_W_CVT_D64_L_CVT_D64_S_CVT_D64_W_CVT_L_D64_CVT_L_S_CVT_S_D32_CVT_S_D64_CVT_S_L_CVT_S_W_CVT_W_D32_CVT_W_D64_CVT_W_S = 638, |
| CVT_PS_S64_CVT_S_PL64_CVT_S_PU64 = 639, |
| C_EQ_D32_C_EQ_D64_C_F_D32_C_F_D64_C_LE_D32_C_LE_D64_C_LT_D32_C_LT_D64_C_NGE_D32_C_NGE_D64_C_NGLE_D32_C_NGLE_D64_C_NGL_D32_C_NGL_D64_C_NGT_D32_C_NGT_D64_C_OLE_D32_C_OLE_D64_C_OLT_D32_C_OLT_D64_C_SEQ_D32_C_SEQ_D64_C_SF_D32_C_SF_D64_C_UEQ_D32_C_UEQ_D64_C_ULE_D32_C_ULE_D64_C_ULT_D32_C_ULT_D64_C_UN_D32_C_UN_D64 = 640, |
| C_EQ_S_C_F_S_C_LE_S_C_LT_S_C_NGE_S_C_NGLE_S_C_NGL_S_C_NGT_S_C_OLE_S_C_OLT_S_C_SEQ_S_C_SF_S_C_UEQ_S_C_ULE_S_C_ULT_S_C_UN_S = 641, |
| FCMP_D32_FCMP_D64 = 642, |
| FCMP_S32 = 643, |
| PseudoCVT_D32_W_PseudoCVT_D64_L_PseudoCVT_D64_W_PseudoCVT_S_L_PseudoCVT_S_W = 644, |
| PLL_PS64_PLU_PS64_PUL_PS64_PUU_PS64 = 645, |
| FDIV_S = 646, |
| FDIV_D32_FDIV_D64 = 647, |
| FSQRT_S = 648, |
| FSQRT_D32_FSQRT_D64 = 649, |
| FRCP_D_FRCP_W = 650, |
| FRSQRT_D_FRSQRT_W = 651, |
| RECIP_D32_RECIP_D64 = 652, |
| RSQRT_D32_RSQRT_D64 = 653, |
| RECIP_S = 654, |
| RSQRT_S = 655, |
| FMADD_D_FMADD_W = 656, |
| FMSUB_D_FMSUB_W = 657, |
| FDIV_W = 658, |
| FDIV_D = 659, |
| FSQRT_W = 660, |
| FSQRT_D = 661, |
| FMUL_D_FMUL_W = 662, |
| FADD_D_FADD_W = 663, |
| FSUB_D_FSUB_W = 664, |
| DPADD_S_D_DPADD_S_H_DPADD_S_W_DPADD_U_D_DPADD_U_H_DPADD_U_W = 665, |
| DPSUB_S_D_DPSUB_S_H_DPSUB_S_W_DPSUB_U_D_DPSUB_U_H_DPSUB_U_W = 666, |
| DOTP_S_D_DOTP_S_H_DOTP_S_W_DOTP_U_D_DOTP_U_H_DOTP_U_W = 667, |
| MSUBV_B_MSUBV_D_MSUBV_H_MSUBV_W = 668, |
| MADDV_B_MADDV_D_MADDV_H_MADDV_W = 669, |
| MULV_B_MULV_D_MULV_H_MULV_W = 670, |
| MADDR_Q_H_MADDR_Q_W = 671, |
| MADD_Q_H_MADD_Q_W = 672, |
| MSUBR_Q_H_MSUBR_Q_W = 673, |
| MSUB_Q_H_MSUB_Q_W = 674, |
| MULR_Q_H_MULR_Q_W = 675, |
| MUL_Q_H_MUL_Q_W = 676, |
| MADD_D32_MADD_D64 = 677, |
| MADD_S = 678, |
| MSUB_D32_MSUB_D64 = 679, |
| MSUB_S = 680, |
| NMADD_D32_NMADD_D64 = 681, |
| NMADD_S = 682, |
| NMSUB_D32_NMSUB_D64 = 683, |
| NMSUB_S = 684, |
| CTC1 = 685, |
| MTC1_MTC1_D64_BuildPairF64_BuildPairF64_64 = 686, |
| MTHC1_D32_MTHC1_D64 = 687, |
| COPY_U_B_COPY_U_H_COPY_U_W = 688, |
| COPY_S_B_COPY_S_D_COPY_S_H_COPY_S_W = 689, |
| BC1F = 690, |
| BC1FL = 691, |
| BC1T = 692, |
| BC1TL = 693, |
| CFC1 = 694, |
| MFC1_MFC1_D64_ExtractElementF64_ExtractElementF64_64 = 695, |
| MFHC1_D32_MFHC1_D64 = 696, |
| MOVF_I = 697, |
| MOVT_I = 698, |
| SDC1_SDC164 = 699, |
| SDXC1_SDXC164 = 700, |
| SWC1 = 701, |
| SWXC1 = 702, |
| SUXC1_SUXC164 = 703, |
| ST_B_ST_D_ST_H_ST_W = 704, |
| ST_F16 = 705, |
| MOVN_I_D32_MOVN_I_D64 = 706, |
| MOVN_I_S = 707, |
| MOVZ_I_D32_MOVZ_I_D64 = 708, |
| MOVZ_I_S = 709, |
| LDC1_LDC164 = 710, |
| LDXC1_LDXC164 = 711, |
| LWC1 = 712, |
| LWXC1 = 713, |
| LUXC1_LUXC164 = 714, |
| LD_B_LD_D_LD_H_LD_W = 715, |
| LD_F16 = 716, |
| CEIL_L_D64_CEIL_L_S_CEIL_W_D32_CEIL_W_D64_CEIL_W_S = 717, |
| FLOOR_L_D64_FLOOR_L_S_FLOOR_W_D32_FLOOR_W_D64_FLOOR_W_S = 718, |
| ROUND_L_D64_ROUND_L_S_ROUND_W_D32_ROUND_W_D64_ROUND_W_S = 719, |
| ROTRV = 720, |
| ATOMIC_SWAP_I16_POSTRA_ATOMIC_SWAP_I32_POSTRA_ATOMIC_SWAP_I64_POSTRA_ATOMIC_SWAP_I8_POSTRA = 721, |
| ATOMIC_CMP_SWAP_I16_POSTRA_ATOMIC_CMP_SWAP_I32_POSTRA_ATOMIC_CMP_SWAP_I64_POSTRA_ATOMIC_CMP_SWAP_I8_POSTRA = 722, |
| ATOMIC_LOAD_ADD_I16_POSTRA_ATOMIC_LOAD_ADD_I32_POSTRA_ATOMIC_LOAD_ADD_I64_POSTRA_ATOMIC_LOAD_ADD_I8_POSTRA_ATOMIC_LOAD_AND_I16_POSTRA_ATOMIC_LOAD_AND_I32_POSTRA_ATOMIC_LOAD_AND_I64_POSTRA_ATOMIC_LOAD_AND_I8_POSTRA_ATOMIC_LOAD_MAX_I16_POSTRA_ATOMIC_LOAD_MAX_I32_POSTRA_ATOMIC_LOAD_MAX_I64_POSTRA_ATOMIC_LOAD_MAX_I8_POSTRA_ATOMIC_LOAD_MIN_I16_POSTRA_ATOMIC_LOAD_MIN_I32_POSTRA_ATOMIC_LOAD_MIN_I64_POSTRA_ATOMIC_LOAD_MIN_I8_POSTRA_ATOMIC_LOAD_NAND_I16_POSTRA_ATOMIC_LOAD_NAND_I32_POSTRA_ATOMIC_LOAD_NAND_I64_POSTRA_ATOMIC_LOAD_NAND_I8_POSTRA_ATOMIC_LOAD_OR_I16_POSTRA_ATOMIC_LOAD_OR_I32_POSTRA_ATOMIC_LOAD_OR_I64_POSTRA_ATOMIC_LOAD_OR_I8_POSTRA_ATOMIC_LOAD_SUB_I16_POSTRA_ATOMIC_LOAD_SUB_I32_POSTRA_ATOMIC_LOAD_SUB_I64_POSTRA_ATOMIC_LOAD_SUB_I8_POSTRA_ATOMIC_LOAD_UMAX_I16_POSTRA_ATOMIC_LOAD_UMAX_I32_POSTRA_ATOMIC_LOAD_UMAX_I64_POSTRA_ATOMIC_LOAD_UMAX_I8_POSTRA_ATOMIC_LOAD_UMIN_I16_POSTRA_ATOMIC_LOAD_UMIN_I32_POSTRA_ATOMIC_LOAD_UMIN_I64_POSTRA_ATOMIC_LOAD_UMIN_I8_POSTRA_ATOMIC_LOAD_XOR_I16_POSTRA_ATOMIC_LOAD_XOR_I32_POSTRA_ATOMIC_LOAD_XOR_I64_POSTRA_ATOMIC_LOAD_XOR_I8_POSTRA = 723, |
| LEA_ADDiu = 724, |
| ADDIUPC = 725, |
| ALIGN = 726, |
| ALUIPC = 727, |
| AUI = 728, |
| AUIPC = 729, |
| BITSWAP = 730, |
| CLO_R6 = 731, |
| CLZ_R6 = 732, |
| LSA_R6 = 733, |
| SELEQZ_SELNEZ = 734, |
| AddiuRxImmX16_AddiuRxRxImm16_AddiuRxRxImmX16_AddiuRxRyOffMemX16_AddiuRxPcImmX16_AddiuSpImm16_AddiuSpImmX16_AdduRxRyRz16_AndRxRxRy16_CmpRxRy16_CmpiRxImm16_CmpiRxImmX16_LiRxImm16_LiRxImmX16_LiRxImmAlignX16_Move32R16_MoveR3216_Mfhi16_Mflo16_NegRxRy16_NotRxRy16_OrRxRxRy16_SebRx16_SehRx16_SllX16_SllvRxRy16_SltiRxImm16_SltiRxImmX16_SltiuRxImm16_SltiuRxImmX16_SltRxRy16_SltuRxRy16_SravRxRy16_SraX16_SrlvRxRy16_SrlX16_SubuRxRyRz16_XorRxRxRy16 = 735, |
| SltiCCRxImmX16_SltiuCCRxImmX16_SltCCRxRy16_SltuRxRyRz16_SltuCCRxRy16 = 736, |
| Constant32_LwConstant32_GotPrologue16_CONSTPOOL_ENTRY = 737, |
| ADDIUPC_MM_ADDIUR1SP_MM_ADDIUR2_MM_ADDIUS5_MM_ADDIUSP_MM_ADDiu_MM_LEA_ADDiu_MM = 738, |
| ADDU16_MM_ADDu_MM = 739, |
| ADD_MM = 740, |
| ADDi_MM = 741, |
| AND16_MM_ANDI16_MM_AND_MM = 742, |
| ANDi_MM = 743, |
| CLO_MM = 744, |
| CLZ_MM = 745, |
| EXT_MM = 746, |
| INS_MM = 747, |
| LI16_MM = 748, |
| LUi_MM = 749, |
| MOVE16_MM = 750, |
| MOVEP_MM = 751, |
| NOR_MM = 752, |
| NOT16_MM = 753, |
| OR16_MM_OR_MM = 754, |
| ORi_MM = 755, |
| ROTRV_MM = 756, |
| ROTR_MM = 757, |
| SEB_MM = 758, |
| SEH_MM = 759, |
| SLL16_MM_SLL_MM = 760, |
| SLLV_MM = 761, |
| SLT_MM_SLTu_MM = 762, |
| SLTi_MM_SLTiu_MM = 763, |
| SRAV_MM = 764, |
| SRA_MM = 765, |
| SRL16_MM_SRL_MM = 766, |
| SRLV_MM = 767, |
| SSNOP_MM = 768, |
| SUBU16_MM_SUBu_MM = 769, |
| SUB_MM = 770, |
| WSBH_MM = 771, |
| XOR16_MM_XOR_MM = 772, |
| XORi_MM = 773, |
| ADDIUPC_MMR6 = 774, |
| ADDIU_MMR6 = 775, |
| ADDU16_MMR6_ADDU_MMR6 = 776, |
| ADD_MMR6 = 777, |
| ALIGN_MMR6 = 778, |
| ALUIPC_MMR6 = 779, |
| AND16_MMR6_ANDI16_MMR6_AND_MMR6 = 780, |
| ANDI_MMR6 = 781, |
| AUIPC_MMR6 = 782, |
| AUI_MMR6 = 783, |
| BITSWAP_MMR6 = 784, |
| CLO_MMR6 = 785, |
| CLZ_MMR6 = 786, |
| EXT_MMR6 = 787, |
| INS_MMR6 = 788, |
| LI16_MMR6 = 789, |
| LSA_MMR6 = 790, |
| LUI_MMR6 = 791, |
| MOVE16_MMR6 = 792, |
| NOR_MMR6 = 793, |
| NOT16_MMR6 = 794, |
| OR16_MMR6_OR_MMR6 = 795, |
| ORI_MMR6 = 796, |
| SELEQZ_MMR6_SELNEZ_MMR6 = 797, |
| SLL16_MMR6_SLL_MMR6 = 798, |
| SRL16_MMR6 = 799, |
| SSNOP_MMR6 = 800, |
| SUBU16_MMR6_SUBU_MMR6 = 801, |
| SUB_MMR6 = 802, |
| WSBH_MMR6 = 803, |
| XOR16_MMR6_XOR_MMR6 = 804, |
| XORI_MMR6 = 805, |
| AND64_ANDi64 = 806, |
| DEXT64_32 = 807, |
| DSLL64_32 = 808, |
| ORi64 = 809, |
| SEB64 = 810, |
| SEH64 = 811, |
| SLL64_32_SLL64_64 = 812, |
| SLT64_SLTu64 = 813, |
| SLTi64_SLTiu64 = 814, |
| XOR64_XORi64 = 815, |
| DADD = 816, |
| DADDi = 817, |
| DADDiu = 818, |
| DADDu = 819, |
| DCLO = 820, |
| DCLZ = 821, |
| DEXT_DEXTM_DEXTU = 822, |
| DINS_DINSM_DINSU = 823, |
| DROTR = 824, |
| DROTR32 = 825, |
| DROTRV = 826, |
| DSBH = 827, |
| DSHD = 828, |
| DSLL = 829, |
| DSLL32 = 830, |
| DSLLV = 831, |
| DSRA = 832, |
| DSRA32 = 833, |
| DSRAV = 834, |
| DSRL = 835, |
| DSRL32 = 836, |
| DSRLV = 837, |
| DSUB = 838, |
| DSUBu = 839, |
| LEA_ADDiu64 = 840, |
| LUi64 = 841, |
| NOR64 = 842, |
| OR64 = 843, |
| DALIGN = 844, |
| DAHI = 845, |
| DATI = 846, |
| DAUI = 847, |
| DCLO_R6 = 848, |
| DCLZ_R6 = 849, |
| DBITSWAP = 850, |
| DLSA_DLSA_R6 = 851, |
| SELEQZ64_SELNEZ64 = 852, |
| MADD = 853, |
| MADDU = 854, |
| MSUB = 855, |
| MSUBU = 856, |
| PseudoMADD_MM = 857, |
| PseudoMADDU_MM = 858, |
| PseudoMSUB_MM = 859, |
| PseudoMSUBU_MM = 860, |
| PseudoMULT_MM = 861, |
| PseudoMULTu_MM = 862, |
| PseudoMULT = 863, |
| PseudoMULTu = 864, |
| PseudoSDIV_SDIV = 865, |
| PseudoUDIV_UDIV = 866, |
| PseudoMFHI_MM_PseudoMFLO_MM = 867, |
| PseudoMTLOHI_MM = 868, |
| MUH = 869, |
| MUHU = 870, |
| MULU = 871, |
| MUL_R6 = 872, |
| MOD = 873, |
| MODU = 874, |
| MultRxRy16_MultuRxRy16_MultRxRyRz16_MultuRxRyRz16 = 875, |
| DivRxRy16 = 876, |
| DivuRxRy16 = 877, |
| MULT_MM = 878, |
| MULTu_MM = 879, |
| MADD_MM = 880, |
| MADDU_MM = 881, |
| MSUB_MM = 882, |
| MSUBU_MM = 883, |
| MUL_MM = 884, |
| SDIV_MM_SDIV_MM_Pseudo = 885, |
| UDIV_MM_UDIV_MM_Pseudo = 886, |
| MFHI16_MM_MFLO16_MM_MFHI_MM_MFLO_MM = 887, |
| MOVF_I_MM = 888, |
| MOVT_I_MM = 889, |
| MTHI_MM_MTLO_MM = 890, |
| RDHWR_MM = 891, |
| MUHU_MMR6 = 892, |
| MUH_MMR6 = 893, |
| MULU_MMR6 = 894, |
| MUL_MMR6 = 895, |
| MODU_MMR6 = 896, |
| MOD_MMR6 = 897, |
| DIVU_MMR6 = 898, |
| DIV_MMR6 = 899, |
| RDHWR_MMR6 = 900, |
| DMULU = 901, |
| DMULT_PseudoDMULT = 902, |
| DMULTu_PseudoDMULTu = 903, |
| DSDIV_PseudoDSDIV = 904, |
| DUDIV_PseudoDUDIV = 905, |
| MFHI64_MFLO64_PseudoMFHI64_PseudoMFLO64 = 906, |
| PseudoMTLOHI64 = 907, |
| MTHI64_MTLO64 = 908, |
| RDHWR64 = 909, |
| MOVN_I_I64_MOVN_I64_I_MOVN_I64_I64 = 910, |
| MOVZ_I_I64_MOVZ_I64_I_MOVZ_I64_I64 = 911, |
| DMUH = 912, |
| DMUHU = 913, |
| DMUL_R6 = 914, |
| DDIV = 915, |
| DMOD = 916, |
| DDIVU = 917, |
| DMODU = 918, |
| BAL_BR_BLTZAL = 919, |
| BEQ_BNE = 920, |
| BGTZ_BGEZ_BLEZ_BLTZ = 921, |
| J = 922, |
| JR = 923, |
| ERet = 924, |
| BGEZAL = 925, |
| BALC = 926, |
| BEQZALC_BGEZALC_BGTZALC_BLEZALC_BLTZALC_BNEZALC = 927, |
| JIALC = 928, |
| BC = 929, |
| BC2EQZ_BC2NEZ = 930, |
| BEQC_BGEC_BGEUC_BLTC_BLTUC_BNEC_BNVC_BOVC = 931, |
| BEQZC_BGEZC_BGTZC_BLEZC_BLTZC_BNEZC = 932, |
| JIC = 933, |
| JR_HB_R6 = 934, |
| SIGRIE = 935, |
| PseudoIndirectBranchR6_PseudoIndrectHazardBranchR6 = 936, |
| TAILCALLR6REG_TAILCALLHBR6REG = 937, |
| SDBBP_R6 = 938, |
| Bimm16_BimmX16_BeqzRxImm16_BeqzRxImmX16_BnezRxImm16_BnezRxImmX16_Bteqz16_BteqzX16_Btnez16_BtnezX16_JrRa16_JrcRa16_JrcRx16 = 939, |
| BteqzT8CmpX16_BteqzT8CmpiX16_BteqzT8SltX16_BteqzT8SltuX16_BteqzT8SltiX16_BteqzT8SltiuX16_BtnezT8CmpX16_BtnezT8CmpiX16_BtnezT8SltX16_BtnezT8SltuX16_BtnezT8SltiX16_BtnezT8SltiuX16_RetRA16 = 940, |
| Jal16_JalB16 = 941, |
| JumpLinkReg16 = 942, |
| Break16 = 943, |
| SelBeqZ_SelTBteqZCmp_SelTBteqZCmpi_SelTBteqZSlt_SelTBteqZSlti_SelTBteqZSltu_SelTBteqZSltiu_SelBneZ_SelTBtneZCmp_SelTBtneZCmpi_SelTBtneZSlt_SelTBtneZSlti_SelTBtneZSltu_SelTBtneZSltiu = 944, |
| B16_MM_B_MM = 945, |
| BAL_BR_MM = 946, |
| BC1F_MM = 947, |
| BC1T_MM = 948, |
| BEQZ16_MM_BGEZ_MM_BGTZ_MM_BLEZ_MM_BLTZ_MM_BNEZ16_MM = 949, |
| BEQZC_MM_BNEZC_MM = 950, |
| BEQ_MM_BNE_MM = 951, |
| DERET_MM = 952, |
| ERET_MM = 953, |
| JR16_MM_JR_MM = 954, |
| J_MM = 955, |
| B_MM_Pseudo = 956, |
| BGEZALS_MM_BLTZALS_MM = 957, |
| BGEZAL_MM_BLTZAL_MM = 958, |
| JALR16_MM_JALR_MM = 959, |
| JALRS16_MM_JALRS_MM = 960, |
| JALS_MM = 961, |
| JALX_MM_JAL_MM = 962, |
| TAILCALLREG_MM = 963, |
| TAILCALL_MM = 964, |
| PseudoIndirectBranch_MM = 965, |
| BREAK16_MM_BREAK_MM = 966, |
| SDBBP16_MM_SDBBP_MM = 967, |
| SYSCALL_MM = 968, |
| TEQI_MM = 969, |
| TEQ_MM = 970, |
| TGEIU_MM = 971, |
| TGEI_MM = 972, |
| TGEU_MM = 973, |
| TGE_MM = 974, |
| TLTIU_MM = 975, |
| TLTI_MM = 976, |
| TLTU_MM = 977, |
| TLT_MM = 978, |
| TNEI_MM = 979, |
| TNE_MM = 980, |
| TRAP_MM = 981, |
| BC16_MMR6_BC_MMR6 = 982, |
| BC1EQZC_MMR6_BC1NEZC_MMR6 = 983, |
| BC2EQZC_MMR6_BC2NEZC_MMR6 = 984, |
| BEQC_MMR6_BGEC_MMR6_BGEUC_MMR6_BLTC_MMR6_BLTUC_MMR6_BNEC_MMR6_BNVC_MMR6_BOVC_MMR6 = 985, |
| BEQZC16_MMR6_BNEZC16_MMR6 = 986, |
| BEQZC_MMR6_BGEZC_MMR6_BGTZC_MMR6_BLEZC_MMR6_BLTZC_MMR6_BNEZC_MMR6 = 987, |
| DERET_MMR6 = 988, |
| ERETNC_MMR6 = 989, |
| JAL_MMR6 = 990, |
| ERET_MMR6 = 991, |
| JIC_MMR6 = 992, |
| JRADDIUSP_JRCADDIUSP_MMR6 = 993, |
| JRC16_MM = 994, |
| JRC16_MMR6 = 995, |
| SIGRIE_MMR6 = 996, |
| B_MMR6_Pseudo = 997, |
| PseudoIndirectBranch_MMR6 = 998, |
| BALC_MMR6 = 999, |
| BEQZALC_MMR6_BGEZALC_MMR6_BGTZALC_MMR6_BLEZALC_MMR6_BLTZALC_MMR6_BNEZALC_MMR6 = 1000, |
| JALRC16_MMR6 = 1001, |
| JALRC_HB_MMR6 = 1002, |
| JALRC_MMR6 = 1003, |
| JIALC_MMR6 = 1004, |
| TAILCALLREG_MMR6 = 1005, |
| TAILCALL_MMR6 = 1006, |
| BREAK16_MMR6_BREAK_MMR6 = 1007, |
| SDBBP_MMR6_SDBBP16_MMR6 = 1008, |
| BEQ64_BNE64 = 1009, |
| BGEZ64_BGTZ64_BLEZ64_BLTZ64 = 1010, |
| JR64 = 1011, |
| JALR64_JALR64Pseudo_JALRHB64Pseudo = 1012, |
| JALR_HB64 = 1013, |
| JR_HB64 = 1014, |
| TAILCALLREG64_TAILCALLREGHB64 = 1015, |
| PseudoReturn64 = 1016, |
| BEQC64_BGEC64_BGEUC64_BLTC64_BLTUC64_BNEC64 = 1017, |
| BEQZC64_BGEZC64_BGTZC64_BLEZC64_BLTZC64_BNEZC64 = 1018, |
| JIC64 = 1019, |
| PseudoIndirectBranch64_PseudoIndirectHazardBranch64 = 1020, |
| JIALC64 = 1021, |
| JR_HB64_R6 = 1022, |
| TAILCALL64R6REG_TAILCALLHB64R6REG = 1023, |
| PseudoIndirectBranch64R6_PseudoIndrectHazardBranch64R6 = 1024, |
| EVP = 1025, |
| DVP = 1026, |
| TLBP_MM = 1027, |
| TLBR_MM = 1028, |
| TLBWI_MM = 1029, |
| TLBWR_MM = 1030, |
| DI_MM = 1031, |
| EI_MM = 1032, |
| EHB_MM = 1033, |
| PAUSE_MM = 1034, |
| WAIT_MM = 1035, |
| RDPGPR_MMR6 = 1036, |
| WRPGPR_MMR6 = 1037, |
| TLBINV_MMR6 = 1038, |
| TLBINVF_MMR6 = 1039, |
| MFHC0_MMR6 = 1040, |
| MFC0_MMR6 = 1041, |
| MFHC2_MMR6_MFC2_MMR6 = 1042, |
| MTHC0_MMR6 = 1043, |
| MTC0_MMR6 = 1044, |
| MTHC2_MMR6_MTC2_MMR6 = 1045, |
| EVP_MMR6 = 1046, |
| DVP_MMR6 = 1047, |
| DI_MMR6 = 1048, |
| EI_MMR6 = 1049, |
| EHB_MMR6 = 1050, |
| PAUSE_MMR6 = 1051, |
| WAIT_MMR6 = 1052, |
| DMFC0 = 1053, |
| DMTC0 = 1054, |
| DMFC2 = 1055, |
| DMTC2 = 1056, |
| CFC2_MM = 1057, |
| CTC2_MM = 1058, |
| DMT = 1059, |
| DVPE = 1060, |
| EMT = 1061, |
| EVPE = 1062, |
| MFTR = 1063, |
| MTTR = 1064, |
| YIELD = 1065, |
| FORK = 1066, |
| DMFGC0 = 1067, |
| DMTGC0 = 1068, |
| HYPCALL_MM = 1069, |
| TLBGINVF_MM = 1070, |
| TLBGINV_MM = 1071, |
| TLBGP_MM = 1072, |
| TLBGR_MM = 1073, |
| TLBGWI_MM = 1074, |
| TLBGWR_MM = 1075, |
| MFGC0_MM = 1076, |
| MFHGC0_MM = 1077, |
| MTGC0_MM = 1078, |
| MTHGC0_MM = 1079, |
| SC_MMR6 = 1080, |
| LDC2_R6 = 1081, |
| LL_R6 = 1082, |
| LWC2_R6 = 1083, |
| SWC2_R6 = 1084, |
| SDC2_R6 = 1085, |
| SC_R6 = 1086, |
| PREF_R6 = 1087, |
| CACHE_R6 = 1088, |
| GINVI = 1089, |
| GINVT = 1090, |
| LBE_MM = 1091, |
| LBuE_MM = 1092, |
| LHE_MM = 1093, |
| LHuE_MM = 1094, |
| LWE_MM = 1095, |
| LWLE_MM = 1096, |
| LWRE_MM = 1097, |
| LLE_MM = 1098, |
| SBE_MM = 1099, |
| SB_MM = 1100, |
| SHE_MM = 1101, |
| SWE_MM = 1102, |
| SWLE_MM = 1103, |
| SWRE_MM = 1104, |
| SCE_MM = 1105, |
| PREFE_MM = 1106, |
| CACHEE_MM = 1107, |
| Restore16_RestoreX16 = 1108, |
| LbRxRyOffMemX16 = 1109, |
| LbuRxRyOffMemX16 = 1110, |
| LhRxRyOffMemX16 = 1111, |
| LhuRxRyOffMemX16 = 1112, |
| LwRxRyOffMemX16_LwRxSpImmX16_LwRxPcTcp16_LwRxPcTcpX16 = 1113, |
| Save16_SaveX16 = 1114, |
| SbRxRyOffMemX16 = 1115, |
| ShRxRyOffMemX16 = 1116, |
| SwRxRyOffMemX16_SwRxSpImmX16 = 1117, |
| LBU16_MM_LBu_MM = 1118, |
| LB_MM = 1119, |
| LHU16_MM_LHu_MM = 1120, |
| LH_MM = 1121, |
| LL_MM = 1122, |
| LW16_MM_LWGP_MM_LWSP_MM_LW_MM = 1123, |
| LWL_MM = 1124, |
| LWM16_MM_LWM32_MM = 1125, |
| LWP_MM = 1126, |
| LWR_MM = 1127, |
| LWU_MM = 1128, |
| LWXS_MM = 1129, |
| SB16_MM = 1130, |
| SC_MM = 1131, |
| SH16_MM_SH_MM = 1132, |
| SW16_MM_SWSP_MM_SW_MM = 1133, |
| SWL_MM = 1134, |
| SWM16_MM_SWM32_MM = 1135, |
| SWM_MM = 1136, |
| SWP_MM = 1137, |
| SWR_MM = 1138, |
| PREF_MM_PREFX_MM = 1139, |
| CACHE_MM = 1140, |
| SYNC_MM = 1141, |
| SYNCI_MM = 1142, |
| GINVI_MMR6 = 1143, |
| GINVT_MMR6 = 1144, |
| LBU_MMR6 = 1145, |
| LB_MMR6 = 1146, |
| LDC2_MMR6 = 1147, |
| LL_MMR6 = 1148, |
| LWM16_MMR6 = 1149, |
| LWC2_MMR6 = 1150, |
| LWPC_MMR6 = 1151, |
| LW_MMR6 = 1152, |
| SB16_MMR6_SB_MMR6 = 1153, |
| SDC2_MMR6 = 1154, |
| SH16_MMR6_SH_MMR6 = 1155, |
| SW16_MMR6_SWSP_MMR6_SW_MMR6 = 1156, |
| SWC2_MMR6 = 1157, |
| SWM16_MMR6 = 1158, |
| SYNC_MMR6 = 1159, |
| SYNCI_MMR6 = 1160, |
| PREF_MMR6 = 1161, |
| CACHE_MMR6 = 1162, |
| LD = 1163, |
| LL64_LLD = 1164, |
| LWu = 1165, |
| LB64 = 1166, |
| LBu64 = 1167, |
| LH64 = 1168, |
| LHu64 = 1169, |
| LW64 = 1170, |
| LWL64 = 1171, |
| LWR64 = 1172, |
| LDL = 1173, |
| LDR = 1174, |
| SD = 1175, |
| SC64_SCD = 1176, |
| SB64 = 1177, |
| SH64 = 1178, |
| SW64 = 1179, |
| SWL64 = 1180, |
| SWR64 = 1181, |
| SDL = 1182, |
| SDR = 1183, |
| LWUPC = 1184, |
| LDPC = 1185, |
| LLD_R6 = 1186, |
| LL64_R6 = 1187, |
| SC64_R6 = 1188, |
| SCD_R6 = 1189, |
| CRC32B = 1190, |
| CRC32H = 1191, |
| CRC32W = 1192, |
| CRC32CB = 1193, |
| CRC32CH = 1194, |
| CRC32CW = 1195, |
| CRC32D = 1196, |
| CRC32CD = 1197, |
| BADDu = 1198, |
| BBIT0_BBIT032_BBIT1_BBIT132 = 1199, |
| CINS_CINS32_CINS64_32_CINS_i32 = 1200, |
| DMFC2_OCTEON = 1201, |
| DMTC2_OCTEON = 1202, |
| DPOP_POP = 1203, |
| EXTS_EXTS32 = 1204, |
| MTM0_MTM1_MTM2_MTP0_MTP1_MTP2 = 1205, |
| SEQ_SNE = 1206, |
| SEQi_SNEi = 1207, |
| V3MULU_VMM0_VMULU = 1208, |
| DMUL = 1209, |
| SAA_SAAD = 1210, |
| ADDR_PS64 = 1211, |
| CVT_PS_PW64_CVT_PW_PS64 = 1212, |
| MULR_PS64 = 1213, |
| PseudoTRUNC_W_D_PseudoTRUNC_W_D32_PseudoTRUNC_W_S = 1214, |
| MOVT_I64 = 1215, |
| MOVF_I64 = 1216, |
| MOVZ_I64_S = 1217, |
| MOVN_I64_D64 = 1218, |
| MOVN_I64_S = 1219, |
| MOVZ_I64_D64 = 1220, |
| SELEQZ_S_SELNEZ_S = 1221, |
| SELEQZ_D_SELNEZ_D = 1222, |
| MAX_S_MAXA_S = 1223, |
| MAX_D_MAXA_D = 1224, |
| MIN_S_MINA_D = 1225, |
| MIN_D_MINA_S = 1226, |
| CLASS_S = 1227, |
| CLASS_D = 1228, |
| RINT_S = 1229, |
| RINT_D = 1230, |
| BC1EQZ_BC1NEZ = 1231, |
| SEL_D = 1232, |
| SEL_S = 1233, |
| MADDF_S = 1234, |
| MSUBF_S = 1235, |
| MADDF_D = 1236, |
| MSUBF_D = 1237, |
| MOVF_D32_MM = 1238, |
| MOVF_S_MM = 1239, |
| MOVN_I_D32_MM = 1240, |
| MOVN_I_S_MM = 1241, |
| MOVT_D32_MM = 1242, |
| MOVT_S_MM = 1243, |
| MOVZ_I_D32_MM = 1244, |
| MOVZ_I_S_MM = 1245, |
| CVT_D32_S_MM_CVT_D32_W_MM_CVT_D64_S_MM_CVT_D64_W_MM_CVT_L_D64_MM_CVT_L_S_MM_CVT_S_D32_MM_CVT_S_D64_MM_CVT_S_W_MM_CVT_W_D32_MM_CVT_W_D64_MM_CVT_W_S_MM = 1246, |
| CEIL_W_MM_CEIL_W_S_MM = 1247, |
| FLOOR_W_MM_FLOOR_W_S_MM = 1248, |
| NMADD_S_MM = 1249, |
| NMADD_D32_MM = 1250, |
| NMSUB_S_MM = 1251, |
| NMSUB_D32_MM = 1252, |
| MADD_S_MM = 1253, |
| MADD_D32_MM = 1254, |
| ROUND_W_MM_ROUND_W_S_MM = 1255, |
| TRUNC_W_MM_TRUNC_W_S_MM = 1256, |
| C_F_D32_MM_C_F_D64_MM = 1257, |
| C_F_S_MM = 1258, |
| C_EQ_D32_MM_C_EQ_D64_MM_C_LE_D32_MM_C_LE_D64_MM_C_LT_D32_MM_C_LT_D64_MM_C_SF_D32_MM_C_SF_D64_MM_C_UN_D32_MM_C_UN_D64_MM = 1259, |
| C_EQ_S_MM_C_LE_S_MM_C_LT_S_MM_C_SF_S_MM_C_UN_S_MM = 1260, |
| C_NGE_D32_MM_C_NGE_D64_MM_C_NGL_D32_MM_C_NGL_D64_MM_C_NGT_D32_MM_C_NGT_D64_MM_C_OLE_D32_MM_C_OLE_D64_MM_C_OLT_D32_MM_C_OLT_D64_MM_C_SEQ_D32_MM_C_SEQ_D64_MM_C_UEQ_D32_MM_C_UEQ_D64_MM_C_ULE_D32_MM_C_ULE_D64_MM_C_ULT_D32_MM_C_ULT_D64_MM = 1261, |
| C_NGE_S_MM_C_NGL_S_MM_C_NGT_S_MM_C_OLE_S_MM_C_OLT_S_MM_C_SEQ_S_MM_C_UEQ_S_MM_C_ULE_S_MM_C_ULT_S_MM = 1262, |
| C_NGLE_D32_MM_C_NGLE_D64_MM = 1263, |
| C_NGLE_S_MM = 1264, |
| FCMP_S32_MM = 1265, |
| FCMP_D32_MM = 1266, |
| MFC1_MM = 1267, |
| MFHC1_D32_MM_MFHC1_D64_MM = 1268, |
| MTC1_MM_MTC1_D64_MM = 1269, |
| MTHC1_D32_MM_MTHC1_D64_MM = 1270, |
| FABS_D32_MM_FABS_D64_MM = 1271, |
| FABS_S_MM = 1272, |
| FNEG_D32_MM_FNEG_D64_MM_FNEG_S_MM = 1273, |
| FADD_D32_MM_FADD_D64_MM = 1274, |
| FADD_S_MM = 1275, |
| FMOV_D32_MM_FMOV_D64_MM = 1276, |
| FMOV_S_MM = 1277, |
| FMUL_D32_MM_FMUL_D64_MM = 1278, |
| FMUL_S_MM = 1279, |
| FSUB_D32_MM_FSUB_D64_MM = 1280, |
| FSUB_S_MM = 1281, |
| MSUB_S_MM = 1282, |
| MSUB_D32_MM = 1283, |
| FDIV_S_MM = 1284, |
| FDIV_D32_MM_FDIV_D64_MM = 1285, |
| FSQRT_S_MM = 1286, |
| FSQRT_D32_MM_FSQRT_D64_MM = 1287, |
| RECIP_S_MM_RSQRT_S_MM = 1288, |
| RECIP_D32_MM_RECIP_D64_MM_RSQRT_D32_MM_RSQRT_D64_MM = 1289, |
| SDC1_MM_D32_SDC1_MM_D64 = 1290, |
| SWC1_MM = 1291, |
| SUXC1_MM = 1292, |
| SWXC1_MM = 1293, |
| CFC1_MM = 1294, |
| CTC1_MM = 1295, |
| LDC1_MM_D32_LDC1_MM_D64 = 1296, |
| LUXC1_MM = 1297, |
| LWC1_MM = 1298, |
| LWXC1_MM = 1299, |
| FNEG_S_MMR6 = 1300, |
| CMP_AF_D_MMR6_CMP_EQ_D_MMR6_CMP_LE_D_MMR6_CMP_LT_D_MMR6_CMP_UN_D_MMR6 = 1301, |
| CMP_AF_S_MMR6_CMP_EQ_S_MMR6_CMP_LE_S_MMR6_CMP_LT_S_MMR6_CMP_UN_S_MMR6 = 1302, |
| CMP_SAF_D_MMR6_CMP_SEQ_D_MMR6_CMP_SLE_D_MMR6_CMP_SLT_D_MMR6_CMP_SUN_D_MMR6_CMP_UEQ_D_MMR6_CMP_ULE_D_MMR6_CMP_ULT_D_MMR6 = 1303, |
| CMP_SAF_S_MMR6_CMP_SEQ_S_MMR6_CMP_SLE_S_MMR6_CMP_SLT_S_MMR6_CMP_SUN_S_MMR6_CMP_UEQ_S_MMR6_CMP_ULE_S_MMR6_CMP_ULT_S_MMR6 = 1304, |
| CMP_SUEQ_D_MMR6_CMP_SULE_D_MMR6_CMP_SULT_D_MMR6 = 1305, |
| CMP_SUEQ_S_MMR6_CMP_SULE_S_MMR6_CMP_SULT_S_MMR6 = 1306, |
| CVT_D_L_MMR6_CVT_L_D_MMR6_CVT_L_S_MMR6_CVT_S_L_MMR6_CVT_S_W_MMR6_CVT_W_S_MMR6 = 1307, |
| TRUNC_L_D_MMR6_TRUNC_L_S_MMR6_TRUNC_W_D_MMR6_TRUNC_W_S_MMR6 = 1308, |
| ROUND_L_D_MMR6_ROUND_L_S_MMR6_ROUND_W_D_MMR6_ROUND_W_S_MMR6 = 1309, |
| FLOOR_L_D_MMR6_FLOOR_L_S_MMR6_FLOOR_W_D_MMR6_FLOOR_W_S_MMR6 = 1310, |
| CEIL_L_D_MMR6_CEIL_L_S_MMR6_CEIL_W_D_MMR6_CEIL_W_S_MMR6 = 1311, |
| MFC1_MMR6 = 1312, |
| MTC1_MMR6 = 1313, |
| CLASS_S_MMR6_CLASS_D_MMR6 = 1314, |
| FADD_S_MMR6 = 1315, |
| MAX_D_MMR6 = 1316, |
| MAX_S_MMR6 = 1317, |
| MIN_D_MMR6 = 1318, |
| MIN_S_MMR6 = 1319, |
| MAXA_D_MMR6 = 1320, |
| MAXA_S_MMR6 = 1321, |
| MINA_D_MMR6 = 1322, |
| MINA_S_MMR6 = 1323, |
| SELEQZ_D_MMR6_SELNEZ_D_MMR6 = 1324, |
| SELEQZ_S_MMR6_SELNEZ_S_MMR6 = 1325, |
| SEL_D_MMR6 = 1326, |
| SEL_S_MMR6 = 1327, |
| RINT_S_MMR6_RINT_D_MMR6 = 1328, |
| MADDF_D_MMR6 = 1329, |
| MADDF_S_MMR6 = 1330, |
| MSUBF_D_MMR6 = 1331, |
| MSUBF_S_MMR6 = 1332, |
| FMOV_S_MMR6 = 1333, |
| FMUL_S_MMR6 = 1334, |
| FSUB_S_MMR6 = 1335, |
| FMOV_D_MMR6 = 1336, |
| FDIV_S_MMR6 = 1337, |
| SDC1_D64_MMR6 = 1338, |
| LDC1_D64_MMR6 = 1339, |
| DMFC1 = 1340, |
| DMTC1 = 1341, |
| SWDSP = 1342, |
| LWDSP = 1343, |
| PseudoMTLOHI_DSP = 1344, |
| EXTRV_RS_W = 1345, |
| EXTRV_R_W = 1346, |
| EXTRV_S_H = 1347, |
| EXTRV_W = 1348, |
| EXTR_RS_W = 1349, |
| EXTR_R_W = 1350, |
| EXTR_S_H = 1351, |
| EXTR_W = 1352, |
| INSV = 1353, |
| MTHLIP = 1354, |
| MTHI_DSP = 1355, |
| MTLO_DSP = 1356, |
| ABSQ_S_PH = 1357, |
| ABSQ_S_W = 1358, |
| ADDQ_PH = 1359, |
| ADDQ_S_PH = 1360, |
| ADDQ_S_W = 1361, |
| ADDSC = 1362, |
| ADDU_QB = 1363, |
| ADDU_S_QB = 1364, |
| ADDWC = 1365, |
| BITREV = 1366, |
| BPOSGE32 = 1367, |
| CMPGU_EQ_QB = 1368, |
| CMPGU_LE_QB = 1369, |
| CMPGU_LT_QB = 1370, |
| CMPU_EQ_QB = 1371, |
| CMPU_LE_QB = 1372, |
| CMPU_LT_QB = 1373, |
| CMP_EQ_PH = 1374, |
| CMP_LE_PH = 1375, |
| CMP_LT_PH = 1376, |
| DPAQ_SA_L_W = 1377, |
| DPAQ_S_W_PH = 1378, |
| DPAU_H_QBL = 1379, |
| DPAU_H_QBR = 1380, |
| DPSQ_SA_L_W = 1381, |
| DPSQ_S_W_PH = 1382, |
| DPSU_H_QBL = 1383, |
| DPSU_H_QBR = 1384, |
| EXTPDPV = 1385, |
| EXTPDP = 1386, |
| EXTPV = 1387, |
| EXTP = 1388, |
| LBUX = 1389, |
| LHX = 1390, |
| LWX = 1391, |
| MADDU_DSP = 1392, |
| MADD_DSP = 1393, |
| MAQ_SA_W_PHL = 1394, |
| MAQ_SA_W_PHR = 1395, |
| MAQ_S_W_PHL = 1396, |
| MAQ_S_W_PHR = 1397, |
| MFHI_DSP = 1398, |
| MFLO_DSP = 1399, |
| MODSUB = 1400, |
| MSUBU_DSP = 1401, |
| MSUB_DSP = 1402, |
| MULEQ_S_W_PHL = 1403, |
| MULEQ_S_W_PHR = 1404, |
| MULEU_S_PH_QBL = 1405, |
| MULEU_S_PH_QBR = 1406, |
| MULQ_RS_PH = 1407, |
| MULSAQ_S_W_PH = 1408, |
| MULTU_DSP = 1409, |
| MULT_DSP = 1410, |
| PACKRL_PH = 1411, |
| PICK_PH = 1412, |
| PICK_QB = 1413, |
| PRECEQU_PH_QBLA = 1414, |
| PRECEQU_PH_QBL = 1415, |
| PRECEQU_PH_QBRA = 1416, |
| PRECEQU_PH_QBR = 1417, |
| PRECEQ_W_PHL = 1418, |
| PRECEQ_W_PHR = 1419, |
| PRECEU_PH_QBLA = 1420, |
| PRECEU_PH_QBL = 1421, |
| PRECEU_PH_QBRA = 1422, |
| PRECEU_PH_QBR = 1423, |
| PRECRQU_S_QB_PH = 1424, |
| PRECRQ_PH_W = 1425, |
| PRECRQ_QB_PH = 1426, |
| PRECRQ_RS_PH_W = 1427, |
| RADDU_W_QB = 1428, |
| RDDSP = 1429, |
| REPLV_PH = 1430, |
| REPLV_QB = 1431, |
| REPL_PH = 1432, |
| REPL_QB = 1433, |
| SHILOV = 1434, |
| SHILO = 1435, |
| SHLLV_PH = 1436, |
| SHLLV_QB = 1437, |
| SHLLV_S_PH = 1438, |
| SHLLV_S_W = 1439, |
| SHLL_PH = 1440, |
| SHLL_QB = 1441, |
| SHLL_S_PH = 1442, |
| SHLL_S_W = 1443, |
| SHRAV_PH = 1444, |
| SHRAV_R_PH = 1445, |
| SHRAV_R_W = 1446, |
| SHRA_PH = 1447, |
| SHRA_R_PH = 1448, |
| SHRA_R_W = 1449, |
| SHRLV_QB = 1450, |
| SHRL_QB = 1451, |
| SUBQ_PH = 1452, |
| SUBQ_S_PH = 1453, |
| SUBQ_S_W = 1454, |
| SUBU_QB = 1455, |
| SUBU_S_QB = 1456, |
| WRDSP = 1457, |
| PseudoCMPU_EQ_QB_PseudoCMPU_LE_QB_PseudoCMPU_LT_QB_PseudoCMP_EQ_PH_PseudoCMP_LE_PH_PseudoCMP_LT_PH = 1458, |
| PseudoPICK_PH_PseudoPICK_QB = 1459, |
| ABSQ_S_QB = 1460, |
| ADDQH_PH = 1461, |
| ADDQH_R_PH = 1462, |
| ADDQH_R_W = 1463, |
| ADDQH_W = 1464, |
| ADDUH_QB = 1465, |
| ADDUH_R_QB = 1466, |
| ADDU_PH = 1467, |
| ADDU_S_PH = 1468, |
| APPEND = 1469, |
| BALIGN = 1470, |
| CMPGDU_EQ_QB = 1471, |
| CMPGDU_LE_QB = 1472, |
| CMPGDU_LT_QB = 1473, |
| DPA_W_PH = 1474, |
| DPAQX_SA_W_PH = 1475, |
| DPAQX_S_W_PH = 1476, |
| DPAX_W_PH = 1477, |
| DPS_W_PH = 1478, |
| DPSQX_S_W_PH = 1479, |
| DPSQX_SA_W_PH = 1480, |
| DPSX_W_PH = 1481, |
| MUL_PH = 1482, |
| MUL_S_PH = 1483, |
| MULQ_RS_W = 1484, |
| MULQ_S_PH = 1485, |
| MULQ_S_W = 1486, |
| MULSA_W_PH = 1487, |
| PRECR_QB_PH = 1488, |
| PRECR_SRA_PH_W = 1489, |
| PRECR_SRA_R_PH_W = 1490, |
| PREPEND = 1491, |
| SHRA_QB = 1492, |
| SHRA_R_QB = 1493, |
| SHRAV_QB = 1494, |
| SHRAV_R_QB = 1495, |
| SHRL_PH = 1496, |
| SHRLV_PH = 1497, |
| SUBQH_PH = 1498, |
| SUBQH_R_PH = 1499, |
| SUBQH_W = 1500, |
| SUBQH_R_W = 1501, |
| SUBU_PH = 1502, |
| SUBU_S_PH = 1503, |
| SUBUH_QB = 1504, |
| SUBUH_R_QB = 1505, |
| LWDSP_MM = 1506, |
| SWDSP_MM = 1507, |
| ABSQ_S_PH_MM = 1508, |
| ABSQ_S_W_MM = 1509, |
| ADDQ_PH_MM = 1510, |
| ADDQ_S_PH_MM = 1511, |
| ADDQ_S_W_MM = 1512, |
| ADDSC_MM = 1513, |
| ADDU_QB_MM = 1514, |
| ADDU_S_QB_MM = 1515, |
| ADDWC_MM = 1516, |
| BITREV_MM = 1517, |
| BPOSGE32_MM = 1518, |
| CMPGU_EQ_QB_MM = 1519, |
| CMPGU_LE_QB_MM = 1520, |
| CMPGU_LT_QB_MM = 1521, |
| CMPU_EQ_QB_MM = 1522, |
| CMPU_LE_QB_MM = 1523, |
| CMPU_LT_QB_MM = 1524, |
| CMP_EQ_PH_MM = 1525, |
| CMP_LE_PH_MM = 1526, |
| CMP_LT_PH_MM = 1527, |
| DPAQ_SA_L_W_MM = 1528, |
| DPAQ_S_W_PH_MM = 1529, |
| DPAU_H_QBL_MM = 1530, |
| DPAU_H_QBR_MM = 1531, |
| DPSQ_SA_L_W_MM = 1532, |
| DPSQ_S_W_PH_MM = 1533, |
| DPSU_H_QBL_MM = 1534, |
| DPSU_H_QBR_MM = 1535, |
| EXTPDPV_MM = 1536, |
| EXTPDP_MM = 1537, |
| EXTPV_MM = 1538, |
| EXTP_MM = 1539, |
| EXTRV_RS_W_MM = 1540, |
| EXTRV_R_W_MM = 1541, |
| EXTRV_S_H_MM = 1542, |
| EXTRV_W_MM = 1543, |
| EXTR_RS_W_MM = 1544, |
| EXTR_R_W_MM = 1545, |
| EXTR_S_H_MM = 1546, |
| EXTR_W_MM = 1547, |
| INSV_MM = 1548, |
| LBUX_MM = 1549, |
| LHX_MM = 1550, |
| LWX_MM = 1551, |
| MADDU_DSP_MM = 1552, |
| MADD_DSP_MM = 1553, |
| MAQ_SA_W_PHL_MM = 1554, |
| MAQ_SA_W_PHR_MM = 1555, |
| MAQ_S_W_PHL_MM = 1556, |
| MAQ_S_W_PHR_MM = 1557, |
| MFHI_DSP_MM = 1558, |
| MFLO_DSP_MM = 1559, |
| MODSUB_MM = 1560, |
| MOVEP_MMR6 = 1561, |
| MOVN_I_MM = 1562, |
| MOVZ_I_MM = 1563, |
| MSUBU_DSP_MM = 1564, |
| MSUB_DSP_MM = 1565, |
| MTHI_DSP_MM = 1566, |
| MTHLIP_MM = 1567, |
| MTLO_DSP_MM = 1568, |
| MULEQ_S_W_PHL_MM = 1569, |
| MULEQ_S_W_PHR_MM = 1570, |
| MULEU_S_PH_QBL_MM = 1571, |
| MULEU_S_PH_QBR_MM = 1572, |
| MULQ_RS_PH_MM = 1573, |
| MULSAQ_S_W_PH_MM = 1574, |
| MULTU_DSP_MM = 1575, |
| MULT_DSP_MM = 1576, |
| PACKRL_PH_MM = 1577, |
| PICK_PH_MM = 1578, |
| PICK_QB_MM = 1579, |
| PRECEQU_PH_QBLA_MM = 1580, |
| PRECEQU_PH_QBL_MM = 1581, |
| PRECEQU_PH_QBRA_MM = 1582, |
| PRECEQU_PH_QBR_MM = 1583, |
| PRECEQ_W_PHL_MM = 1584, |
| PRECEQ_W_PHR_MM = 1585, |
| PRECEU_PH_QBLA_MM = 1586, |
| PRECEU_PH_QBL_MM = 1587, |
| PRECEU_PH_QBRA_MM = 1588, |
| PRECEU_PH_QBR_MM = 1589, |
| PRECRQU_S_QB_PH_MM = 1590, |
| PRECRQ_PH_W_MM = 1591, |
| PRECRQ_QB_PH_MM = 1592, |
| PRECRQ_RS_PH_W_MM = 1593, |
| RADDU_W_QB_MM = 1594, |
| RDDSP_MM = 1595, |
| REPLV_PH_MM = 1596, |
| REPLV_QB_MM = 1597, |
| REPL_PH_MM = 1598, |
| REPL_QB_MM = 1599, |
| SHILOV_MM = 1600, |
| SHILO_MM = 1601, |
| SHLLV_PH_MM = 1602, |
| SHLLV_QB_MM = 1603, |
| SHLLV_S_PH_MM = 1604, |
| SHLLV_S_W_MM = 1605, |
| SHLL_PH_MM = 1606, |
| SHLL_QB_MM = 1607, |
| SHLL_S_PH_MM = 1608, |
| SHLL_S_W_MM = 1609, |
| SHRAV_PH_MM = 1610, |
| SHRAV_R_PH_MM = 1611, |
| SHRAV_R_W_MM = 1612, |
| SHRA_PH_MM = 1613, |
| SHRA_R_PH_MM = 1614, |
| SHRA_R_W_MM = 1615, |
| SHRLV_QB_MM = 1616, |
| SHRL_QB_MM = 1617, |
| SUBQ_PH_MM = 1618, |
| SUBQ_S_PH_MM = 1619, |
| SUBQ_S_W_MM = 1620, |
| SUBU_QB_MM = 1621, |
| SUBU_S_QB_MM = 1622, |
| WRDSP_MM = 1623, |
| ABSQ_S_QB_MMR2 = 1624, |
| ADDQH_PH_MMR2 = 1625, |
| ADDQH_R_PH_MMR2 = 1626, |
| ADDQH_R_W_MMR2 = 1627, |
| ADDQH_W_MMR2 = 1628, |
| ADDUH_QB_MMR2 = 1629, |
| ADDUH_R_QB_MMR2 = 1630, |
| ADDU_PH_MMR2 = 1631, |
| ADDU_S_PH_MMR2 = 1632, |
| APPEND_MMR2 = 1633, |
| BALIGN_MMR2 = 1634, |
| CMPGDU_EQ_QB_MMR2 = 1635, |
| CMPGDU_LE_QB_MMR2 = 1636, |
| CMPGDU_LT_QB_MMR2 = 1637, |
| DPA_W_PH_MMR2 = 1638, |
| DPAQX_SA_W_PH_MMR2 = 1639, |
| DPAQX_S_W_PH_MMR2 = 1640, |
| DPAX_W_PH_MMR2 = 1641, |
| DPS_W_PH_MMR2 = 1642, |
| DPSQX_S_W_PH_MMR2 = 1643, |
| DPSQX_SA_W_PH_MMR2 = 1644, |
| DPSX_W_PH_MMR2 = 1645, |
| MUL_PH_MMR2 = 1646, |
| MUL_S_PH_MMR2 = 1647, |
| MULQ_RS_W_MMR2 = 1648, |
| MULQ_S_PH_MMR2 = 1649, |
| MULQ_S_W_MMR2 = 1650, |
| MULSA_W_PH_MMR2 = 1651, |
| PRECR_QB_PH_MMR2 = 1652, |
| PRECR_SRA_PH_W_MMR2 = 1653, |
| PRECR_SRA_R_PH_W_MMR2 = 1654, |
| PREPEND_MMR2 = 1655, |
| SHRA_QB_MMR2 = 1656, |
| SHRA_R_QB_MMR2 = 1657, |
| SHRAV_QB_MMR2 = 1658, |
| SHRAV_R_QB_MMR2 = 1659, |
| SHRL_PH_MMR2 = 1660, |
| SHRLV_PH_MMR2 = 1661, |
| SUBQH_PH_MMR2 = 1662, |
| SUBQH_R_PH_MMR2 = 1663, |
| SUBQH_W_MMR2 = 1664, |
| SUBQH_R_W_MMR2 = 1665, |
| SUBU_PH_MMR2 = 1666, |
| SUBU_S_PH_MMR2 = 1667, |
| SUBUH_QB_MMR2 = 1668, |
| SUBUH_R_QB_MMR2 = 1669, |
| BPOSGE32C_MMR3 = 1670, |
| CMP_F_D = 1671, |
| CMP_F_S = 1672, |
| CMP_SAF_D = 1673, |
| CMP_SAF_S = 1674, |
| CMP_SEQ_D = 1675, |
| CMP_SEQ_S = 1676, |
| CMP_SLE_D = 1677, |
| CMP_SLE_S = 1678, |
| CMP_SLT_D = 1679, |
| CMP_SLT_S = 1680, |
| CMP_SUEQ_D = 1681, |
| CMP_SUEQ_S = 1682, |
| CMP_SULE_D = 1683, |
| CMP_SULE_S = 1684, |
| CMP_SULT_D = 1685, |
| CMP_SULT_S = 1686, |
| CMP_SUN_D = 1687, |
| CMP_SUN_S = 1688, |
| SCHED_LIST_END = 1689 |
| }; |
| } // end namespace Sched |
| } // end namespace Mips |
| } // end namespace llvm |
| #endif // GET_INSTRINFO_SCHED_ENUM |
| |
| #ifdef GET_INSTRINFO_MC_DESC |
| #undef GET_INSTRINFO_MC_DESC |
| namespace llvm { |
| |
| static const MCPhysReg ImplicitList1[] = { Mips::SP, Mips::SP }; |
| static const MCPhysReg ImplicitList2[] = { Mips::AT }; |
| static const MCPhysReg ImplicitList3[] = { Mips::RA }; |
| static const MCPhysReg ImplicitList4[] = { Mips::DSPPos }; |
| static const MCPhysReg ImplicitList5[] = { Mips::V0, Mips::V1 }; |
| static const MCPhysReg ImplicitList6[] = { Mips::HI0, Mips::LO0 }; |
| static const MCPhysReg ImplicitList7[] = { Mips::T8 }; |
| static const MCPhysReg ImplicitList8[] = { Mips::DSPOutFlag20 }; |
| static const MCPhysReg ImplicitList9[] = { Mips::DSPCarry }; |
| static const MCPhysReg ImplicitList10[] = { Mips::DSPCarry, Mips::DSPOutFlag20 }; |
| static const MCPhysReg ImplicitList11[] = { Mips::DSPCCond }; |
| static const MCPhysReg ImplicitList12[] = { Mips::HI0, Mips::LO0, Mips::P0, Mips::P1, Mips::P2 }; |
| static const MCPhysReg ImplicitList13[] = { Mips::HI0_64, Mips::LO0_64 }; |
| static const MCPhysReg ImplicitList14[] = { Mips::DSPOutFlag16_19 }; |
| static const MCPhysReg ImplicitList15[] = { Mips::DSPPos, Mips::DSPEFI }; |
| static const MCPhysReg ImplicitList16[] = { Mips::DSPPos, Mips::DSPPos, Mips::DSPEFI }; |
| static const MCPhysReg ImplicitList17[] = { Mips::DSPOutFlag23 }; |
| static const MCPhysReg ImplicitList18[] = { Mips::FCC0 }; |
| static const MCPhysReg ImplicitList19[] = { Mips::DSPPos, Mips::DSPSCount }; |
| static const MCPhysReg ImplicitList20[] = { Mips::HI0, Mips::LO0, Mips::HI0, Mips::LO0 }; |
| static const MCPhysReg ImplicitList21[] = { Mips::AC0 }; |
| static const MCPhysReg ImplicitList22[] = { Mips::AC0_64 }; |
| static const MCPhysReg ImplicitList23[] = { Mips::HI0 }; |
| static const MCPhysReg ImplicitList24[] = { Mips::HI0_64 }; |
| static const MCPhysReg ImplicitList25[] = { Mips::LO0 }; |
| static const MCPhysReg ImplicitList26[] = { Mips::LO0_64 }; |
| static const MCPhysReg ImplicitList27[] = { Mips::MPL0, Mips::P0, Mips::P1, Mips::P2 }; |
| static const MCPhysReg ImplicitList28[] = { Mips::MPL1, Mips::P0, Mips::P1, Mips::P2 }; |
| static const MCPhysReg ImplicitList29[] = { Mips::MPL2, Mips::P0, Mips::P1, Mips::P2 }; |
| static const MCPhysReg ImplicitList30[] = { Mips::P0 }; |
| static const MCPhysReg ImplicitList31[] = { Mips::P1 }; |
| static const MCPhysReg ImplicitList32[] = { Mips::P2 }; |
| static const MCPhysReg ImplicitList33[] = { Mips::DSPOutFlag21 }; |
| static const MCPhysReg ImplicitList34[] = { Mips::DSPOutFlag22 }; |
| static const MCPhysReg ImplicitList35[] = { Mips::P0, Mips::P1, Mips::P2 }; |
| static const MCPhysReg ImplicitList36[] = { Mips::MPL1, Mips::MPL2, Mips::P0, Mips::P1, Mips::P2 }; |
| |
| static const MCOperandInfo OperandInfo2[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo3[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; |
| static const MCOperandInfo OperandInfo4[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; |
| static const MCOperandInfo OperandInfo5[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; |
| static const MCOperandInfo OperandInfo6[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; |
| static const MCOperandInfo OperandInfo7[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo8[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; |
| static const MCOperandInfo OperandInfo9[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, }; |
| static const MCOperandInfo OperandInfo10[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; |
| static const MCOperandInfo OperandInfo11[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; |
| static const MCOperandInfo OperandInfo12[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo13[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; |
| static const MCOperandInfo OperandInfo14[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; |
| static const MCOperandInfo OperandInfo15[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo16[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo17[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, }; |
| static const MCOperandInfo OperandInfo18[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, }; |
| static const MCOperandInfo OperandInfo19[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, }; |
| static const MCOperandInfo OperandInfo20[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, }; |
| static const MCOperandInfo OperandInfo21[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo22[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, }; |
| static const MCOperandInfo OperandInfo23[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, }; |
| static const MCOperandInfo OperandInfo24[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, }; |
| static const MCOperandInfo OperandInfo25[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, }; |
| static const MCOperandInfo OperandInfo26[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; |
| static const MCOperandInfo OperandInfo27[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo28[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo29[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, }; |
| static const MCOperandInfo OperandInfo30[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, }; |
| static const MCOperandInfo OperandInfo31[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, }; |
| static const MCOperandInfo OperandInfo32[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo33[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, }; |
| static const MCOperandInfo OperandInfo34[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, }; |
| static const MCOperandInfo OperandInfo35[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, }; |
| static const MCOperandInfo OperandInfo36[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, }; |
| static const MCOperandInfo OperandInfo37[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, }; |
| static const MCOperandInfo OperandInfo38[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, }; |
| static const MCOperandInfo OperandInfo39[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, }; |
| static const MCOperandInfo OperandInfo40[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, }; |
| static const MCOperandInfo OperandInfo41[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo42[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, }; |
| static const MCOperandInfo OperandInfo43[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, }; |
| static const MCOperandInfo OperandInfo44[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, }; |
| static const MCOperandInfo OperandInfo45[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo46[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo47[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo48[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo49[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo50[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo51[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo52[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo53[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo54[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo55[] = { { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; |
| static const MCOperandInfo OperandInfo56[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; |
| static const MCOperandInfo OperandInfo57[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; |
| static const MCOperandInfo OperandInfo58[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo59[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo60[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo61[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo62[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; |
| static const MCOperandInfo OperandInfo63[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; |
| static const MCOperandInfo OperandInfo64[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo65[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo66[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGRCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo67[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo68[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo69[] = { { Mips::FGRCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo70[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo71[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo72[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo73[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo74[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; |
| static const MCOperandInfo OperandInfo75[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; |
| static const MCOperandInfo OperandInfo76[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo77[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo78[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo79[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo80[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo81[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo82[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo83[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo84[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo85[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo86[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo87[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo88[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo89[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo90[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo91[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo92[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo93[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo94[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo95[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo96[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; |
| static const MCOperandInfo OperandInfo97[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo98[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo99[] = { { Mips::MSA128F16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; |
| static const MCOperandInfo OperandInfo100[] = { { Mips::ACC128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; |
| static const MCOperandInfo OperandInfo101[] = { { Mips::ACC64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; |
| static const MCOperandInfo OperandInfo102[] = { { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; |
| static const MCOperandInfo OperandInfo103[] = { { Mips::DSPCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; |
| static const MCOperandInfo OperandInfo104[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; |
| static const MCOperandInfo OperandInfo105[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; |
| static const MCOperandInfo OperandInfo106[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; |
| static const MCOperandInfo OperandInfo107[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; |
| static const MCOperandInfo OperandInfo108[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; |
| static const MCOperandInfo OperandInfo109[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; |
| static const MCOperandInfo OperandInfo110[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; |
| static const MCOperandInfo OperandInfo111[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; |
| static const MCOperandInfo OperandInfo112[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo113[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; |
| static const MCOperandInfo OperandInfo114[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo115[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo116[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo117[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo118[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo119[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo120[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::COP0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo121[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo122[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo123[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128F16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo124[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128F16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo125[] = { { Mips::MSA128F16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo126[] = { { Mips::MSA128F16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo127[] = { { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo128[] = { { Mips::COP0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo129[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo130[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo131[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo132[] = { { Mips::DSPCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo133[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo134[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo135[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo136[] = { { Mips::ACC128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo137[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo138[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo139[] = { { Mips::ACC64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, }; |
| static const MCOperandInfo OperandInfo140[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo141[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo142[] = { { Mips::ACC64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo143[] = { { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo144[] = { { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo145[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo146[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo147[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo148[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo149[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo150[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo151[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo152[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo153[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo154[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo155[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo156[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo157[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo158[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; |
| static const MCOperandInfo OperandInfo159[] = { { Mips::GPR32NONZERORegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo160[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo161[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo162[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo163[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo164[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo165[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo166[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo167[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo168[] = { { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo169[] = { { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo170[] = { { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo171[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo172[] = { { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo173[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo174[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo175[] = { { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo176[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo177[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo178[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo179[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo180[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo181[] = { { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, }; |
| static const MCOperandInfo OperandInfo182[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, }; |
| static const MCOperandInfo OperandInfo183[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo184[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo185[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsPlusSPRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo186[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo187[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; |
| static const MCOperandInfo OperandInfo188[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; |
| static const MCOperandInfo OperandInfo189[] = { { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; |
| static const MCOperandInfo OperandInfo190[] = { { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; |
| static const MCOperandInfo OperandInfo191[] = { { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; |
| static const MCOperandInfo OperandInfo192[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo193[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo194[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo195[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo196[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo197[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; |
| static const MCOperandInfo OperandInfo198[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; |
| static const MCOperandInfo OperandInfo199[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; |
| static const MCOperandInfo OperandInfo200[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; |
| static const MCOperandInfo OperandInfo201[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; |
| static const MCOperandInfo OperandInfo202[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo203[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo204[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo205[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo206[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo207[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo208[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CCRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo209[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo210[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSACtrlRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo211[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo212[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo213[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo214[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo215[] = { { Mips::FGRCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo216[] = { { Mips::FGRCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo217[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo218[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo219[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo220[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo221[] = { { Mips::CCRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo222[] = { { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo223[] = { { Mips::MSACtrlRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo224[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo225[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo226[] = { { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo227[] = { { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo228[] = { { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo229[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo230[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo231[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, }; |
| static const MCOperandInfo OperandInfo232[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::COP0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo233[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo234[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo235[] = { { Mips::COP0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo236[] = { { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo237[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo238[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo239[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo240[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo241[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo242[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo243[] = { { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, }; |
| static const MCOperandInfo OperandInfo244[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo245[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo246[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo247[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo248[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo249[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo250[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo251[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo252[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo253[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo254[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo255[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo256[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo257[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo258[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo259[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo260[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo261[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo262[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, }; |
| static const MCOperandInfo OperandInfo263[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo264[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo265[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo266[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo267[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo268[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo269[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo270[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo271[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo272[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo273[] = { { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; |
| static const MCOperandInfo OperandInfo274[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo275[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; |
| static const MCOperandInfo OperandInfo276[] = { { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; |
| static const MCOperandInfo OperandInfo277[] = { { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; |
| static const MCOperandInfo OperandInfo278[] = { { Mips::COP3RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; |
| static const MCOperandInfo OperandInfo279[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo280[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo281[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo282[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo283[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, }; |
| static const MCOperandInfo OperandInfo284[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo285[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo286[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; |
| static const MCOperandInfo OperandInfo287[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; |
| static const MCOperandInfo OperandInfo288[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; |
| static const MCOperandInfo OperandInfo289[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; |
| static const MCOperandInfo OperandInfo290[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MipsII::OPERAND_MEM_SIMM9, 0 }, { -1, 0, MipsII::OPERAND_MEM_SIMM9, 0 }, }; |
| static const MCOperandInfo OperandInfo291[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MipsII::OPERAND_MEM_SIMM9, 0 }, { -1, 0, MipsII::OPERAND_MEM_SIMM9, 0 }, }; |
| static const MCOperandInfo OperandInfo292[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; |
| static const MCOperandInfo OperandInfo293[] = { { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; |
| static const MCOperandInfo OperandInfo294[] = { { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 3, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; |
| static const MCOperandInfo OperandInfo295[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, }; |
| static const MCOperandInfo OperandInfo296[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 2, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; |
| static const MCOperandInfo OperandInfo297[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; |
| static const MCOperandInfo OperandInfo298[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 2, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; |
| static const MCOperandInfo OperandInfo299[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo300[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo301[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; |
| static const MCOperandInfo OperandInfo302[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo303[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo304[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo305[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo306[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo307[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo308[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo309[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo310[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo311[] = { { Mips::GPRMM16MovePPairFirstRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16MovePPairSecondRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16MovePRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16MovePRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo312[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo313[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, }; |
| static const MCOperandInfo OperandInfo314[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, }; |
| static const MCOperandInfo OperandInfo315[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, }; |
| static const MCOperandInfo OperandInfo316[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, }; |
| static const MCOperandInfo OperandInfo317[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, }; |
| static const MCOperandInfo OperandInfo318[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, }; |
| static const MCOperandInfo OperandInfo319[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, }; |
| static const MCOperandInfo OperandInfo320[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, }; |
| static const MCOperandInfo OperandInfo321[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, }; |
| static const MCOperandInfo OperandInfo322[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, }; |
| static const MCOperandInfo OperandInfo323[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, }; |
| static const MCOperandInfo OperandInfo324[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, }; |
| static const MCOperandInfo OperandInfo325[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, }; |
| static const MCOperandInfo OperandInfo326[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, }; |
| static const MCOperandInfo OperandInfo327[] = { { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo328[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo329[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo330[] = { { Mips::HI32DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo331[] = { { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, }; |
| static const MCOperandInfo OperandInfo332[] = { { Mips::LO32DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo333[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo334[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo335[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo336[] = { { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo337[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo338[] = { { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo339[] = { { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, }; |
| static const MCOperandInfo OperandInfo340[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo341[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::HWRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo342[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::HWRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo343[] = { { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo344[] = { { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo345[] = { { Mips::GPRMM16ZeroRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; |
| static const MCOperandInfo OperandInfo346[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; |
| static const MCOperandInfo OperandInfo347[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MipsII::OPERAND_MEM_SIMM9, 0 }, { -1, 0, MipsII::OPERAND_MEM_SIMM9, 0 }, }; |
| static const MCOperandInfo OperandInfo348[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; |
| static const MCOperandInfo OperandInfo349[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MipsII::OPERAND_MEM_SIMM9, 0 }, { -1, 0, MipsII::OPERAND_MEM_SIMM9, 0 }, }; |
| static const MCOperandInfo OperandInfo350[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGRCCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo351[] = { { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, }; |
| static const MCOperandInfo OperandInfo352[] = { { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo353[] = { { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo354[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo355[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo356[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo357[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo358[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo359[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo360[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo361[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo362[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo363[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo364[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; |
| static const MCOperandInfo OperandInfo365[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, }; |
| |
| extern const MCInstrDesc MipsInsts[] = { |
| { 2847, 2, 1, 4, 1065, 0, 0, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo45 }, // Inst #2847 = YIELD |
| { 2846, 3, 1, 2, 735, 0, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, OperandInfo186 }, // Inst #2846 = XorRxRxRy16 |
| { 2845, 3, 1, 4, 773, 0, 0, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, OperandInfo73 }, // Inst #2845 = XORi_MM |
| { 2844, 3, 1, 4, 815, 0, 0, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, OperandInfo70 }, // Inst #2844 = XORi64 |
| { 2843, 3, 1, 4, 508, 0, 0, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, OperandInfo73 }, // Inst #2843 = XORi |
| { 2842, 3, 1, 4, 548, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #2842 = XOR_V |
| { 2841, 3, 1, 4, 804, 0, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, OperandInfo72 }, // Inst #2841 = XOR_MMR6 |
| { 2840, 3, 1, 4, 772, 0, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, OperandInfo72 }, // Inst #2840 = XOR_MM |
| { 2839, 3, 1, 4, 805, 0, 0, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, OperandInfo73 }, // Inst #2839 = XORI_MMR6 |
| { 2838, 3, 1, 4, 549, 0, 0, 0, 0x6ULL, nullptr, OperandInfo176 }, // Inst #2838 = XORI_B |
| { 2837, 3, 1, 4, 815, 0, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, OperandInfo71 }, // Inst #2837 = XOR64 |
| { 2836, 3, 1, 2, 804, 0, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo181 }, // Inst #2836 = XOR16_MMR6 |
| { 2835, 3, 1, 2, 772, 0, 0, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo181 }, // Inst #2835 = XOR16_MM |
| { 2834, 3, 1, 4, 371, 0, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, OperandInfo72 }, // Inst #2834 = XOR |
| { 2833, 2, 1, 4, 803, 0, 0, 0, 0x6ULL, nullptr, OperandInfo45 }, // Inst #2833 = WSBH_MMR6 |
| { 2832, 2, 1, 4, 771, 0, 0, 0, 0x1ULL, nullptr, OperandInfo45 }, // Inst #2832 = WSBH_MM |
| { 2831, 2, 1, 4, 481, 0, 0, 0, 0x1ULL, nullptr, OperandInfo45 }, // Inst #2831 = WSBH |
| { 2830, 2, 1, 4, 1037, 0, 0, 0, 0x6ULL, nullptr, OperandInfo45 }, // Inst #2830 = WRPGPR_MMR6 |
| { 2829, 2, 0, 4, 1623, 0, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo114 }, // Inst #2829 = WRDSP_MM |
| { 2828, 2, 0, 4, 1457, 0, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo114 }, // Inst #2828 = WRDSP |
| { 2827, 1, 0, 4, 1052, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo2 }, // Inst #2827 = WAIT_MMR6 |
| { 2826, 1, 0, 4, 1035, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo2 }, // Inst #2826 = WAIT_MM |
| { 2825, 0, 0, 4, 404, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr }, // Inst #2825 = WAIT |
| { 2824, 4, 1, 4, 515, 0, 0, 0, 0x6ULL, nullptr, OperandInfo60 }, // Inst #2824 = VSHF_W |
| { 2823, 4, 1, 4, 515, 0, 0, 0, 0x6ULL, nullptr, OperandInfo61 }, // Inst #2823 = VSHF_H |
| { 2822, 4, 1, 4, 515, 0, 0, 0, 0x6ULL, nullptr, OperandInfo59 }, // Inst #2822 = VSHF_D |
| { 2821, 4, 1, 4, 515, 0, 0, 0, 0x6ULL, nullptr, OperandInfo196 }, // Inst #2821 = VSHF_B |
| { 2820, 3, 1, 4, 1208, 0, 5, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList36, OperandInfo71 }, // Inst #2820 = VMULU |
| { 2819, 3, 1, 4, 1208, 0, 4, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList27, OperandInfo71 }, // Inst #2819 = VMM0 |
| { 2818, 3, 1, 4, 1208, 0, 3, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList35, OperandInfo71 }, // Inst #2818 = V3MULU |
| { 2817, 2, 0, 4, 886, 0, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList6, OperandInfo45 }, // Inst #2817 = UDIV_MM |
| { 2816, 2, 0, 4, 866, 0, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList6, OperandInfo45 }, // Inst #2816 = UDIV |
| { 2815, 2, 0, 4, 403, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo114 }, // Inst #2815 = TTLTIU |
| { 2814, 2, 1, 4, 1308, 0, 0, 0, 0x4ULL, nullptr, OperandInfo207 }, // Inst #2814 = TRUNC_W_S_MMR6 |
| { 2813, 2, 1, 4, 1256, 0, 0, 0, 0x4ULL, nullptr, OperandInfo207 }, // Inst #2813 = TRUNC_W_S_MM |
| { 2812, 2, 1, 4, 637, 0, 0, 0, 0x4ULL, nullptr, OperandInfo207 }, // Inst #2812 = TRUNC_W_S |
| { 2811, 2, 1, 4, 1256, 0, 0, 0, 0x4ULL, nullptr, OperandInfo205 }, // Inst #2811 = TRUNC_W_MM |
| { 2810, 2, 1, 4, 1308, 0, 0, 0, 0x4ULL, nullptr, OperandInfo206 }, // Inst #2810 = TRUNC_W_D_MMR6 |
| { 2809, 2, 1, 4, 637, 0, 0, 0, 0x4ULL, nullptr, OperandInfo206 }, // Inst #2809 = TRUNC_W_D64 |
| { 2808, 2, 1, 4, 637, 0, 0, 0, 0x4ULL, nullptr, OperandInfo205 }, // Inst #2808 = TRUNC_W_D32 |
| { 2807, 2, 1, 4, 1308, 0, 0, 0, 0x4ULL, nullptr, OperandInfo204 }, // Inst #2807 = TRUNC_L_S_MMR6 |
| { 2806, 2, 1, 4, 637, 0, 0, 0, 0x4ULL, nullptr, OperandInfo204 }, // Inst #2806 = TRUNC_L_S |
| { 2805, 2, 1, 4, 1308, 0, 0, 0, 0x4ULL, nullptr, OperandInfo203 }, // Inst #2805 = TRUNC_L_D_MMR6 |
| { 2804, 2, 1, 4, 637, 0, 0, 0, 0x4ULL, nullptr, OperandInfo203 }, // Inst #2804 = TRUNC_L_D64 |
| { 2803, 3, 0, 4, 980, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, OperandInfo73 }, // Inst #2803 = TNE_MM |
| { 2802, 2, 0, 4, 979, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo114 }, // Inst #2802 = TNEI_MM |
| { 2801, 2, 0, 4, 401, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo114 }, // Inst #2801 = TNEI |
| { 2800, 3, 0, 4, 400, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, OperandInfo73 }, // Inst #2800 = TNE |
| { 2799, 3, 0, 4, 978, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, OperandInfo73 }, // Inst #2799 = TLT_MM |
| { 2798, 3, 0, 4, 977, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, OperandInfo73 }, // Inst #2798 = TLTU_MM |
| { 2797, 3, 0, 4, 399, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, OperandInfo73 }, // Inst #2797 = TLTU |
| { 2796, 2, 0, 4, 976, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo114 }, // Inst #2796 = TLTI_MM |
| { 2795, 2, 0, 4, 975, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo114 }, // Inst #2795 = TLTIU_MM |
| { 2794, 2, 0, 4, 398, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo114 }, // Inst #2794 = TLTI |
| { 2793, 3, 0, 4, 397, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, OperandInfo73 }, // Inst #2793 = TLT |
| { 2792, 0, 0, 4, 1030, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr }, // Inst #2792 = TLBWR_MM |
| { 2791, 0, 0, 4, 415, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr }, // Inst #2791 = TLBWR |
| { 2790, 0, 0, 4, 1029, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr }, // Inst #2790 = TLBWI_MM |
| { 2789, 0, 0, 4, 414, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr }, // Inst #2789 = TLBWI |
| { 2788, 0, 0, 4, 1028, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr }, // Inst #2788 = TLBR_MM |
| { 2787, 0, 0, 4, 413, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr }, // Inst #2787 = TLBR |
| { 2786, 0, 0, 4, 1027, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr }, // Inst #2786 = TLBP_MM |
| { 2785, 0, 0, 4, 412, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr }, // Inst #2785 = TLBP |
| { 2784, 0, 0, 4, 1038, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr }, // Inst #2784 = TLBINV_MMR6 |
| { 2783, 0, 0, 4, 1039, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr }, // Inst #2783 = TLBINVF_MMR6 |
| { 2782, 0, 0, 4, 411, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr }, // Inst #2782 = TLBINVF |
| { 2781, 0, 0, 4, 410, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr }, // Inst #2781 = TLBINV |
| { 2780, 0, 0, 4, 1075, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr }, // Inst #2780 = TLBGWR_MM |
| { 2779, 0, 0, 4, 430, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr }, // Inst #2779 = TLBGWR |
| { 2778, 0, 0, 4, 1074, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr }, // Inst #2778 = TLBGWI_MM |
| { 2777, 0, 0, 4, 429, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr }, // Inst #2777 = TLBGWI |
| { 2776, 0, 0, 4, 1073, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr }, // Inst #2776 = TLBGR_MM |
| { 2775, 0, 0, 4, 428, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr }, // Inst #2775 = TLBGR |
| { 2774, 0, 0, 4, 1072, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr }, // Inst #2774 = TLBGP_MM |
| { 2773, 0, 0, 4, 427, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr }, // Inst #2773 = TLBGP |
| { 2772, 0, 0, 4, 1071, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr }, // Inst #2772 = TLBGINV_MM |
| { 2771, 0, 0, 4, 1070, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr }, // Inst #2771 = TLBGINVF_MM |
| { 2770, 0, 0, 4, 426, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr }, // Inst #2770 = TLBGINVF |
| { 2769, 0, 0, 4, 425, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr }, // Inst #2769 = TLBGINV |
| { 2768, 3, 0, 4, 974, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, OperandInfo73 }, // Inst #2768 = TGE_MM |
| { 2767, 3, 0, 4, 973, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, OperandInfo73 }, // Inst #2767 = TGEU_MM |
| { 2766, 3, 0, 4, 396, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, OperandInfo73 }, // Inst #2766 = TGEU |
| { 2765, 2, 0, 4, 972, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo114 }, // Inst #2765 = TGEI_MM |
| { 2764, 2, 0, 4, 971, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo114 }, // Inst #2764 = TGEIU_MM |
| { 2763, 2, 0, 4, 395, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo114 }, // Inst #2763 = TGEIU |
| { 2762, 2, 0, 4, 394, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo114 }, // Inst #2762 = TGEI |
| { 2761, 3, 0, 4, 393, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, OperandInfo73 }, // Inst #2761 = TGE |
| { 2760, 3, 0, 4, 970, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, OperandInfo73 }, // Inst #2760 = TEQ_MM |
| { 2759, 2, 0, 4, 969, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo114 }, // Inst #2759 = TEQI_MM |
| { 2758, 2, 0, 4, 392, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo114 }, // Inst #2758 = TEQI |
| { 2757, 3, 0, 4, 391, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, OperandInfo73 }, // Inst #2757 = TEQ |
| { 2756, 3, 0, 4, 1117, 0, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo185 }, // Inst #2756 = SwRxSpImmX16 |
| { 2755, 3, 0, 4, 1117, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo300 }, // Inst #2755 = SwRxRyOffMemX16 |
| { 2754, 3, 1, 2, 735, 0, 0, 0|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, OperandInfo131 }, // Inst #2754 = SubuRxRyRz16 |
| { 2753, 3, 1, 2, 735, 0, 0, 0, 0x0ULL, nullptr, OperandInfo186 }, // Inst #2753 = SrlvRxRy16 |
| { 2752, 3, 1, 4, 735, 0, 0, 0, 0x0ULL, nullptr, OperandInfo167 }, // Inst #2752 = SrlX16 |
| { 2751, 3, 1, 2, 735, 0, 0, 0, 0x0ULL, nullptr, OperandInfo186 }, // Inst #2751 = SravRxRy16 |
| { 2750, 3, 1, 4, 735, 0, 0, 0, 0x0ULL, nullptr, OperandInfo167 }, // Inst #2750 = SraX16 |
| { 2749, 2, 0, 2, 735, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList7, OperandInfo130 }, // Inst #2749 = SltuRxRy16 |
| { 2748, 2, 0, 4, 735, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList7, OperandInfo183 }, // Inst #2748 = SltiuRxImmX16 |
| { 2747, 2, 0, 2, 735, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList7, OperandInfo183 }, // Inst #2747 = SltiuRxImm16 |
| { 2746, 2, 0, 4, 735, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList7, OperandInfo183 }, // Inst #2746 = SltiRxImmX16 |
| { 2745, 2, 0, 2, 735, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList7, OperandInfo183 }, // Inst #2745 = SltiRxImm16 |
| { 2744, 2, 0, 2, 735, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList7, OperandInfo130 }, // Inst #2744 = SltRxRy16 |
| { 2743, 3, 1, 2, 735, 0, 0, 0, 0x0ULL, nullptr, OperandInfo186 }, // Inst #2743 = SllvRxRy16 |
| { 2742, 3, 1, 4, 735, 0, 0, 0, 0x0ULL, nullptr, OperandInfo167 }, // Inst #2742 = SllX16 |
| { 2741, 3, 0, 4, 1116, 0, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo300 }, // Inst #2741 = ShRxRyOffMemX16 |
| { 2740, 2, 1, 2, 735, 0, 0, 0, 0x0ULL, nullptr, OperandInfo365 }, // Inst #2740 = SehRx16 |
| { 2739, 2, 1, 2, 735, 0, 0, 0, 0x0ULL, nullptr, OperandInfo365 }, // Inst #2739 = SebRx16 |
| { 2738, 3, 0, 4, 1115, 0, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo300 }, // Inst #2738 = SbRxRyOffMemX16 |
| { 2737, 0, 0, 2, 1114, 1, 1, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, nullptr }, // Inst #2737 = SaveX16 |
| { 2736, 0, 0, 2, 1114, 1, 1, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, nullptr }, // Inst #2736 = Save16 |
| { 2735, 1, 0, 4, 968, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, OperandInfo2 }, // Inst #2735 = SYSCALL_MM |
| { 2734, 1, 0, 4, 390, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, OperandInfo2 }, // Inst #2734 = SYSCALL |
| { 2733, 1, 0, 4, 1159, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo2 }, // Inst #2733 = SYNC_MMR6 |
| { 2732, 1, 0, 4, 1141, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo2 }, // Inst #2732 = SYNC_MM |
| { 2731, 2, 0, 4, 1160, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo364 }, // Inst #2731 = SYNCI_MMR6 |
| { 2730, 2, 0, 4, 1142, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo364 }, // Inst #2730 = SYNCI_MM |
| { 2729, 2, 0, 4, 473, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo364 }, // Inst #2729 = SYNCI |
| { 2728, 1, 0, 4, 472, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo2 }, // Inst #2728 = SYNC |
| { 2727, 3, 0, 4, 1156, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo96 }, // Inst #2727 = SW_MMR6 |
| { 2726, 3, 0, 4, 1133, 0, 0, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, OperandInfo96 }, // Inst #2726 = SW_MM |
| { 2725, 3, 0, 4, 1293, 0, 0, 0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, OperandInfo299 }, // Inst #2725 = SWXC1_MM |
| { 2724, 3, 0, 4, 702, 0, 0, 0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, OperandInfo299 }, // Inst #2724 = SWXC1 |
| { 2723, 3, 0, 2, 1156, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo298 }, // Inst #2723 = SWSP_MMR6 |
| { 2722, 3, 0, 2, 1133, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo298 }, // Inst #2722 = SWSP_MM |
| { 2721, 3, 0, 4, 1138, 0, 0, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, OperandInfo96 }, // Inst #2721 = SWR_MM |
| { 2720, 3, 0, 4, 1104, 0, 0, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, OperandInfo96 }, // Inst #2720 = SWRE_MM |
| { 2719, 3, 0, 4, 467, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo96 }, // Inst #2719 = SWRE |
| { 2718, 3, 0, 4, 1181, 0, 0, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, OperandInfo113 }, // Inst #2718 = SWR64 |
| { 2717, 3, 0, 4, 465, 0, 0, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, OperandInfo96 }, // Inst #2717 = SWR |
| { 2716, 4, 0, 4, 1137, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo297 }, // Inst #2716 = SWP_MM |
| { 2715, 3, 0, 4, 1135, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo110 }, // Inst #2715 = SWM32_MM |
| { 2714, 3, 0, 2, 1158, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo296 }, // Inst #2714 = SWM16_MMR6 |
| { 2713, 3, 0, 2, 1135, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo296 }, // Inst #2713 = SWM16_MM |
| { 2712, 3, 0, 4, 1134, 0, 0, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, OperandInfo96 }, // Inst #2712 = SWL_MM |
| { 2711, 3, 0, 4, 1103, 0, 0, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, OperandInfo96 }, // Inst #2711 = SWLE_MM |
| { 2710, 3, 0, 4, 466, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo96 }, // Inst #2710 = SWLE |
| { 2709, 3, 0, 4, 1180, 0, 0, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, OperandInfo113 }, // Inst #2709 = SWL64 |
| { 2708, 3, 0, 4, 464, 0, 0, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, OperandInfo96 }, // Inst #2708 = SWL |
| { 2707, 3, 0, 4, 1102, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo96 }, // Inst #2707 = SWE_MM |
| { 2706, 3, 0, 4, 462, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo96 }, // Inst #2706 = SWE |
| { 2705, 3, 0, 4, 1507, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo293 }, // Inst #2705 = SWDSP_MM |
| { 2704, 3, 0, 4, 1342, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo293 }, // Inst #2704 = SWDSP |
| { 2703, 3, 0, 4, 456, 0, 0, 0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, OperandInfo278 }, // Inst #2703 = SWC3 |
| { 2702, 3, 0, 4, 1084, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo276 }, // Inst #2702 = SWC2_R6 |
| { 2701, 3, 0, 4, 1157, 0, 0, 0|(1ULL<<MCID::MayStore), 0x6ULL, nullptr, OperandInfo277 }, // Inst #2701 = SWC2_MMR6 |
| { 2700, 3, 0, 4, 455, 0, 0, 0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, OperandInfo276 }, // Inst #2700 = SWC2 |
| { 2699, 3, 0, 4, 1291, 0, 0, 0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, OperandInfo292 }, // Inst #2699 = SWC1_MM |
| { 2698, 3, 0, 4, 701, 0, 0, 0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, OperandInfo292 }, // Inst #2698 = SWC1 |
| { 2697, 3, 0, 4, 1179, 0, 0, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, OperandInfo113 }, // Inst #2697 = SW64 |
| { 2696, 3, 0, 2, 1156, 0, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo345 }, // Inst #2696 = SW16_MMR6 |
| { 2695, 3, 0, 2, 1133, 0, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo345 }, // Inst #2695 = SW16_MM |
| { 2694, 3, 0, 4, 454, 0, 0, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, OperandInfo96 }, // Inst #2694 = SW |
| { 2693, 3, 0, 4, 1292, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, nullptr, OperandInfo285 }, // Inst #2693 = SUXC1_MM |
| { 2692, 3, 0, 4, 703, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, nullptr, OperandInfo285 }, // Inst #2692 = SUXC164 |
| { 2691, 3, 0, 4, 703, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, nullptr, OperandInfo284 }, // Inst #2691 = SUXC1 |
| { 2690, 3, 1, 4, 769, 0, 0, 0|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, OperandInfo72 }, // Inst #2690 = SUBu_MM |
| { 2689, 3, 1, 4, 370, 0, 0, 0|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, OperandInfo72 }, // Inst #2689 = SUBu |
| { 2688, 3, 1, 4, 802, 0, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, OperandInfo72 }, // Inst #2688 = SUB_MMR6 |
| { 2687, 3, 1, 4, 770, 0, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, OperandInfo72 }, // Inst #2687 = SUB_MM |
| { 2686, 3, 1, 4, 612, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #2686 = SUBV_W |
| { 2685, 3, 1, 4, 612, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #2685 = SUBV_H |
| { 2684, 3, 1, 4, 612, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #2684 = SUBV_D |
| { 2683, 3, 1, 4, 612, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #2683 = SUBV_B |
| { 2682, 3, 1, 4, 611, 0, 0, 0, 0x6ULL, nullptr, OperandInfo179 }, // Inst #2682 = SUBVI_W |
| { 2681, 3, 1, 4, 611, 0, 0, 0, 0x6ULL, nullptr, OperandInfo178 }, // Inst #2681 = SUBVI_H |
| { 2680, 3, 1, 4, 611, 0, 0, 0, 0x6ULL, nullptr, OperandInfo177 }, // Inst #2680 = SUBVI_D |
| { 2679, 3, 1, 4, 611, 0, 0, 0, 0x6ULL, nullptr, OperandInfo176 }, // Inst #2679 = SUBVI_B |
| { 2678, 3, 1, 4, 1622, 0, 1, 0, 0x6ULL, ImplicitList8, OperandInfo172 }, // Inst #2678 = SUBU_S_QB_MM |
| { 2677, 3, 1, 4, 1456, 0, 1, 0, 0x6ULL, ImplicitList8, OperandInfo172 }, // Inst #2677 = SUBU_S_QB |
| { 2676, 3, 1, 4, 1667, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList8, OperandInfo172 }, // Inst #2676 = SUBU_S_PH_MMR2 |
| { 2675, 3, 1, 4, 1503, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList8, OperandInfo172 }, // Inst #2675 = SUBU_S_PH |
| { 2674, 3, 1, 4, 1621, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList8, OperandInfo172 }, // Inst #2674 = SUBU_QB_MM |
| { 2673, 3, 1, 4, 1455, 0, 1, 0, 0x6ULL, ImplicitList8, OperandInfo172 }, // Inst #2673 = SUBU_QB |
| { 2672, 3, 1, 4, 1666, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList8, OperandInfo172 }, // Inst #2672 = SUBU_PH_MMR2 |
| { 2671, 3, 1, 4, 1502, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList8, OperandInfo172 }, // Inst #2671 = SUBU_PH |
| { 2670, 3, 1, 4, 801, 0, 0, 0|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, OperandInfo72 }, // Inst #2670 = SUBU_MMR6 |
| { 2669, 3, 1, 4, 1669, 0, 0, 0, 0x6ULL, nullptr, OperandInfo172 }, // Inst #2669 = SUBUH_R_QB_MMR2 |
| { 2668, 3, 1, 4, 1505, 0, 0, 0, 0x6ULL, nullptr, OperandInfo172 }, // Inst #2668 = SUBUH_R_QB |
| { 2667, 3, 1, 4, 1668, 0, 0, 0, 0x6ULL, nullptr, OperandInfo172 }, // Inst #2667 = SUBUH_QB_MMR2 |
| { 2666, 3, 1, 4, 1504, 0, 0, 0, 0x6ULL, nullptr, OperandInfo172 }, // Inst #2666 = SUBUH_QB |
| { 2665, 3, 1, 2, 801, 0, 0, 0, 0x0ULL, nullptr, OperandInfo175 }, // Inst #2665 = SUBU16_MMR6 |
| { 2664, 3, 1, 2, 769, 0, 0, 0, 0x0ULL, nullptr, OperandInfo175 }, // Inst #2664 = SUBU16_MM |
| { 2663, 3, 1, 4, 608, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #2663 = SUBS_U_W |
| { 2662, 3, 1, 4, 608, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #2662 = SUBS_U_H |
| { 2661, 3, 1, 4, 608, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #2661 = SUBS_U_D |
| { 2660, 3, 1, 4, 608, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #2660 = SUBS_U_B |
| { 2659, 3, 1, 4, 608, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #2659 = SUBS_S_W |
| { 2658, 3, 1, 4, 608, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #2658 = SUBS_S_H |
| { 2657, 3, 1, 4, 608, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #2657 = SUBS_S_D |
| { 2656, 3, 1, 4, 608, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #2656 = SUBS_S_B |
| { 2655, 3, 1, 4, 610, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #2655 = SUBSUU_S_W |
| { 2654, 3, 1, 4, 610, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #2654 = SUBSUU_S_H |
| { 2653, 3, 1, 4, 610, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #2653 = SUBSUU_S_D |
| { 2652, 3, 1, 4, 610, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #2652 = SUBSUU_S_B |
| { 2651, 3, 1, 4, 609, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #2651 = SUBSUS_U_W |
| { 2650, 3, 1, 4, 609, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #2650 = SUBSUS_U_H |
| { 2649, 3, 1, 4, 609, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #2649 = SUBSUS_U_D |
| { 2648, 3, 1, 4, 609, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #2648 = SUBSUS_U_B |
| { 2647, 3, 1, 4, 1620, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList8, OperandInfo72 }, // Inst #2647 = SUBQ_S_W_MM |
| { 2646, 3, 1, 4, 1454, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList8, OperandInfo72 }, // Inst #2646 = SUBQ_S_W |
| { 2645, 3, 1, 4, 1619, 0, 1, 0, 0x6ULL, ImplicitList8, OperandInfo172 }, // Inst #2645 = SUBQ_S_PH_MM |
| { 2644, 3, 1, 4, 1453, 0, 1, 0, 0x6ULL, ImplicitList8, OperandInfo172 }, // Inst #2644 = SUBQ_S_PH |
| { 2643, 3, 1, 4, 1618, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList8, OperandInfo172 }, // Inst #2643 = SUBQ_PH_MM |
| { 2642, 3, 1, 4, 1452, 0, 1, 0, 0x6ULL, ImplicitList8, OperandInfo172 }, // Inst #2642 = SUBQ_PH |
| { 2641, 3, 1, 4, 1664, 0, 0, 0, 0x6ULL, nullptr, OperandInfo72 }, // Inst #2641 = SUBQH_W_MMR2 |
| { 2640, 3, 1, 4, 1500, 0, 0, 0, 0x6ULL, nullptr, OperandInfo72 }, // Inst #2640 = SUBQH_W |
| { 2639, 3, 1, 4, 1665, 0, 0, 0, 0x6ULL, nullptr, OperandInfo72 }, // Inst #2639 = SUBQH_R_W_MMR2 |
| { 2638, 3, 1, 4, 1501, 0, 0, 0, 0x6ULL, nullptr, OperandInfo72 }, // Inst #2638 = SUBQH_R_W |
| { 2637, 3, 1, 4, 1663, 0, 0, 0, 0x6ULL, nullptr, OperandInfo172 }, // Inst #2637 = SUBQH_R_PH_MMR2 |
| { 2636, 3, 1, 4, 1499, 0, 0, 0, 0x6ULL, nullptr, OperandInfo172 }, // Inst #2636 = SUBQH_R_PH |
| { 2635, 3, 1, 4, 1662, 0, 0, 0, 0x6ULL, nullptr, OperandInfo172 }, // Inst #2635 = SUBQH_PH_MMR2 |
| { 2634, 3, 1, 4, 1498, 0, 0, 0, 0x6ULL, nullptr, OperandInfo172 }, // Inst #2634 = SUBQH_PH |
| { 2633, 3, 1, 4, 369, 0, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, OperandInfo72 }, // Inst #2633 = SUB |
| { 2632, 3, 0, 4, 704, 0, 0, 0|(1ULL<<MCID::MayStore), 0x6ULL, nullptr, OperandInfo289 }, // Inst #2632 = ST_W |
| { 2631, 3, 0, 4, 704, 0, 0, 0|(1ULL<<MCID::MayStore), 0x6ULL, nullptr, OperandInfo288 }, // Inst #2631 = ST_H |
| { 2630, 3, 0, 4, 704, 0, 0, 0|(1ULL<<MCID::MayStore), 0x6ULL, nullptr, OperandInfo287 }, // Inst #2630 = ST_D |
| { 2629, 3, 0, 4, 704, 0, 0, 0|(1ULL<<MCID::MayStore), 0x6ULL, nullptr, OperandInfo286 }, // Inst #2629 = ST_B |
| { 2628, 0, 0, 4, 800, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr }, // Inst #2628 = SSNOP_MMR6 |
| { 2627, 0, 0, 4, 768, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr }, // Inst #2627 = SSNOP_MM |
| { 2626, 0, 0, 4, 372, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr }, // Inst #2626 = SSNOP |
| { 2625, 3, 1, 4, 622, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #2625 = SRL_W |
| { 2624, 3, 1, 4, 766, 0, 0, 0, 0x1ULL, nullptr, OperandInfo73 }, // Inst #2624 = SRL_MM |
| { 2623, 3, 1, 4, 622, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #2623 = SRL_H |
| { 2622, 3, 1, 4, 622, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #2622 = SRL_D |
| { 2621, 3, 1, 4, 622, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #2621 = SRL_B |
| { 2620, 3, 1, 4, 767, 0, 0, 0, 0x1ULL, nullptr, OperandInfo72 }, // Inst #2620 = SRLV_MM |
| { 2619, 3, 1, 4, 512, 0, 0, 0, 0x1ULL, nullptr, OperandInfo72 }, // Inst #2619 = SRLV |
| { 2618, 3, 1, 4, 624, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #2618 = SRLR_W |
| { 2617, 3, 1, 4, 624, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #2617 = SRLR_H |
| { 2616, 3, 1, 4, 624, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #2616 = SRLR_D |
| { 2615, 3, 1, 4, 624, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #2615 = SRLR_B |
| { 2614, 3, 1, 4, 624, 0, 0, 0, 0x6ULL, nullptr, OperandInfo179 }, // Inst #2614 = SRLRI_W |
| { 2613, 3, 1, 4, 624, 0, 0, 0, 0x6ULL, nullptr, OperandInfo178 }, // Inst #2613 = SRLRI_H |
| { 2612, 3, 1, 4, 624, 0, 0, 0, 0x6ULL, nullptr, OperandInfo177 }, // Inst #2612 = SRLRI_D |
| { 2611, 3, 1, 4, 624, 0, 0, 0, 0x6ULL, nullptr, OperandInfo176 }, // Inst #2611 = SRLRI_B |
| { 2610, 3, 1, 4, 622, 0, 0, 0, 0x6ULL, nullptr, OperandInfo179 }, // Inst #2610 = SRLI_W |
| { 2609, 3, 1, 4, 622, 0, 0, 0, 0x6ULL, nullptr, OperandInfo178 }, // Inst #2609 = SRLI_H |
| { 2608, 3, 1, 4, 622, 0, 0, 0, 0x6ULL, nullptr, OperandInfo177 }, // Inst #2608 = SRLI_D |
| { 2607, 3, 1, 4, 622, 0, 0, 0, 0x6ULL, nullptr, OperandInfo176 }, // Inst #2607 = SRLI_B |
| { 2606, 3, 1, 2, 799, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo170 }, // Inst #2606 = SRL16_MMR6 |
| { 2605, 3, 1, 2, 766, 0, 0, 0, 0x0ULL, nullptr, OperandInfo170 }, // Inst #2605 = SRL16_MM |
| { 2604, 3, 1, 4, 507, 0, 0, 0, 0x1ULL, nullptr, OperandInfo73 }, // Inst #2604 = SRL |
| { 2603, 3, 1, 4, 621, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #2603 = SRA_W |
| { 2602, 3, 1, 4, 765, 0, 0, 0, 0x1ULL, nullptr, OperandInfo73 }, // Inst #2602 = SRA_MM |
| { 2601, 3, 1, 4, 621, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #2601 = SRA_H |
| { 2600, 3, 1, 4, 621, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #2600 = SRA_D |
| { 2599, 3, 1, 4, 621, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #2599 = SRA_B |
| { 2598, 3, 1, 4, 764, 0, 0, 0, 0x1ULL, nullptr, OperandInfo72 }, // Inst #2598 = SRAV_MM |
| { 2597, 3, 1, 4, 511, 0, 0, 0, 0x1ULL, nullptr, OperandInfo72 }, // Inst #2597 = SRAV |
| { 2596, 3, 1, 4, 623, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #2596 = SRAR_W |
| { 2595, 3, 1, 4, 623, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #2595 = SRAR_H |
| { 2594, 3, 1, 4, 623, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #2594 = SRAR_D |
| { 2593, 3, 1, 4, 623, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #2593 = SRAR_B |
| { 2592, 3, 1, 4, 623, 0, 0, 0, 0x6ULL, nullptr, OperandInfo179 }, // Inst #2592 = SRARI_W |
| { 2591, 3, 1, 4, 623, 0, 0, 0, 0x6ULL, nullptr, OperandInfo178 }, // Inst #2591 = SRARI_H |
| { 2590, 3, 1, 4, 623, 0, 0, 0, 0x6ULL, nullptr, OperandInfo177 }, // Inst #2590 = SRARI_D |
| { 2589, 3, 1, 4, 623, 0, 0, 0, 0x6ULL, nullptr, OperandInfo176 }, // Inst #2589 = SRARI_B |
| { 2588, 3, 1, 4, 621, 0, 0, 0, 0x6ULL, nullptr, OperandInfo179 }, // Inst #2588 = SRAI_W |
| { 2587, 3, 1, 4, 621, 0, 0, 0, 0x6ULL, nullptr, OperandInfo178 }, // Inst #2587 = SRAI_H |
| { 2586, 3, 1, 4, 621, 0, 0, 0, 0x6ULL, nullptr, OperandInfo177 }, // Inst #2586 = SRAI_D |
| { 2585, 3, 1, 4, 621, 0, 0, 0, 0x6ULL, nullptr, OperandInfo176 }, // Inst #2585 = SRAI_B |
| { 2584, 3, 1, 4, 506, 0, 0, 0, 0x1ULL, nullptr, OperandInfo73 }, // Inst #2584 = SRA |
| { 2583, 3, 1, 4, 545, 0, 0, 0, 0x6ULL, nullptr, OperandInfo363 }, // Inst #2583 = SPLAT_W |
| { 2582, 3, 1, 4, 545, 0, 0, 0, 0x6ULL, nullptr, OperandInfo362 }, // Inst #2582 = SPLAT_H |
| { 2581, 3, 1, 4, 545, 0, 0, 0, 0x6ULL, nullptr, OperandInfo361 }, // Inst #2581 = SPLAT_D |
| { 2580, 3, 1, 4, 545, 0, 0, 0, 0x6ULL, nullptr, OperandInfo360 }, // Inst #2580 = SPLAT_B |
| { 2579, 3, 1, 4, 545, 0, 0, 0, 0x6ULL, nullptr, OperandInfo179 }, // Inst #2579 = SPLATI_W |
| { 2578, 3, 1, 4, 545, 0, 0, 0, 0x6ULL, nullptr, OperandInfo178 }, // Inst #2578 = SPLATI_H |
| { 2577, 3, 1, 4, 545, 0, 0, 0, 0x6ULL, nullptr, OperandInfo177 }, // Inst #2577 = SPLATI_D |
| { 2576, 3, 1, 4, 545, 0, 0, 0, 0x6ULL, nullptr, OperandInfo176 }, // Inst #2576 = SPLATI_B |
| { 2575, 3, 1, 4, 1207, 0, 0, 0, 0x2ULL, nullptr, OperandInfo70 }, // Inst #2575 = SNEi |
| { 2574, 3, 1, 4, 1206, 0, 0, 0, 0x1ULL, nullptr, OperandInfo71 }, // Inst #2574 = SNE |
| { 2573, 3, 1, 4, 762, 0, 0, 0, 0x1ULL, nullptr, OperandInfo72 }, // Inst #2573 = SLTu_MM |
| { 2572, 3, 1, 4, 813, 0, 0, 0, 0x1ULL, nullptr, OperandInfo358 }, // Inst #2572 = SLTu64 |
| { 2571, 3, 1, 4, 504, 0, 0, 0, 0x1ULL, nullptr, OperandInfo72 }, // Inst #2571 = SLTu |
| { 2570, 3, 1, 4, 763, 0, 0, 0, 0x2ULL, nullptr, OperandInfo73 }, // Inst #2570 = SLTiu_MM |
| { 2569, 3, 1, 4, 814, 0, 0, 0, 0x2ULL, nullptr, OperandInfo359 }, // Inst #2569 = SLTiu64 |
| { 2568, 3, 1, 4, 368, 0, 0, 0, 0x2ULL, nullptr, OperandInfo73 }, // Inst #2568 = SLTiu |
| { 2567, 3, 1, 4, 763, 0, 0, 0, 0x2ULL, nullptr, OperandInfo73 }, // Inst #2567 = SLTi_MM |
| { 2566, 3, 1, 4, 814, 0, 0, 0, 0x2ULL, nullptr, OperandInfo359 }, // Inst #2566 = SLTi64 |
| { 2565, 3, 1, 4, 368, 0, 0, 0, 0x2ULL, nullptr, OperandInfo73 }, // Inst #2565 = SLTi |
| { 2564, 3, 1, 4, 762, 0, 0, 0, 0x1ULL, nullptr, OperandInfo72 }, // Inst #2564 = SLT_MM |
| { 2563, 3, 1, 4, 813, 0, 0, 0, 0x1ULL, nullptr, OperandInfo358 }, // Inst #2563 = SLT64 |
| { 2562, 3, 1, 4, 504, 0, 0, 0, 0x1ULL, nullptr, OperandInfo72 }, // Inst #2562 = SLT |
| { 2561, 3, 1, 4, 625, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #2561 = SLL_W |
| { 2560, 3, 1, 4, 798, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, OperandInfo73 }, // Inst #2560 = SLL_MMR6 |
| { 2559, 3, 1, 4, 760, 0, 0, 0, 0x1ULL, nullptr, OperandInfo73 }, // Inst #2559 = SLL_MM |
| { 2558, 3, 1, 4, 625, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #2558 = SLL_H |
| { 2557, 3, 1, 4, 625, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #2557 = SLL_D |
| { 2556, 3, 1, 4, 625, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #2556 = SLL_B |
| { 2555, 3, 1, 4, 761, 0, 0, 0, 0x1ULL, nullptr, OperandInfo72 }, // Inst #2555 = SLLV_MM |
| { 2554, 3, 1, 4, 510, 0, 0, 0, 0x1ULL, nullptr, OperandInfo72 }, // Inst #2554 = SLLV |
| { 2553, 3, 1, 4, 625, 0, 0, 0, 0x6ULL, nullptr, OperandInfo179 }, // Inst #2553 = SLLI_W |
| { 2552, 3, 1, 4, 625, 0, 0, 0, 0x6ULL, nullptr, OperandInfo178 }, // Inst #2552 = SLLI_H |
| { 2551, 3, 1, 4, 625, 0, 0, 0, 0x6ULL, nullptr, OperandInfo177 }, // Inst #2551 = SLLI_D |
| { 2550, 3, 1, 4, 625, 0, 0, 0, 0x6ULL, nullptr, OperandInfo176 }, // Inst #2550 = SLLI_B |
| { 2549, 2, 1, 4, 812, 0, 0, 0|(1ULL<<MCID::MoveReg), 0x1ULL, nullptr, OperandInfo122 }, // Inst #2549 = SLL64_64 |
| { 2548, 2, 1, 4, 812, 0, 0, 0|(1ULL<<MCID::MoveReg), 0x1ULL, nullptr, OperandInfo245 }, // Inst #2548 = SLL64_32 |
| { 2547, 3, 1, 2, 798, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo170 }, // Inst #2547 = SLL16_MMR6 |
| { 2546, 3, 1, 2, 760, 0, 0, 0, 0x0ULL, nullptr, OperandInfo170 }, // Inst #2546 = SLL16_MM |
| { 2545, 3, 1, 4, 505, 0, 0, 0, 0x1ULL, nullptr, OperandInfo73 }, // Inst #2545 = SLL |
| { 2544, 4, 1, 4, 519, 0, 0, 0, 0x6ULL, nullptr, OperandInfo357 }, // Inst #2544 = SLD_W |
| { 2543, 4, 1, 4, 519, 0, 0, 0, 0x6ULL, nullptr, OperandInfo356 }, // Inst #2543 = SLD_H |
| { 2542, 4, 1, 4, 519, 0, 0, 0, 0x6ULL, nullptr, OperandInfo355 }, // Inst #2542 = SLD_D |
| { 2541, 4, 1, 4, 519, 0, 0, 0, 0x6ULL, nullptr, OperandInfo354 }, // Inst #2541 = SLD_B |
| { 2540, 4, 1, 4, 519, 0, 0, 0, 0x6ULL, nullptr, OperandInfo195 }, // Inst #2540 = SLDI_W |
| { 2539, 4, 1, 4, 519, 0, 0, 0, 0x6ULL, nullptr, OperandInfo194 }, // Inst #2539 = SLDI_H |
| { 2538, 4, 1, 4, 519, 0, 0, 0, 0x6ULL, nullptr, OperandInfo193 }, // Inst #2538 = SLDI_D |
| { 2537, 4, 1, 4, 519, 0, 0, 0, 0x6ULL, nullptr, OperandInfo192 }, // Inst #2537 = SLDI_B |
| { 2536, 1, 0, 4, 996, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo2 }, // Inst #2536 = SIGRIE_MMR6 |
| { 2535, 1, 0, 4, 935, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo2 }, // Inst #2535 = SIGRIE |
| { 2534, 3, 0, 4, 1155, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo96 }, // Inst #2534 = SH_MMR6 |
| { 2533, 3, 0, 4, 1132, 0, 0, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, OperandInfo96 }, // Inst #2533 = SH_MM |
| { 2532, 3, 1, 4, 1617, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo353 }, // Inst #2532 = SHRL_QB_MM |
| { 2531, 3, 1, 4, 1451, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo353 }, // Inst #2531 = SHRL_QB |
| { 2530, 3, 1, 4, 1660, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo353 }, // Inst #2530 = SHRL_PH_MMR2 |
| { 2529, 3, 1, 4, 1496, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo353 }, // Inst #2529 = SHRL_PH |
| { 2528, 3, 1, 4, 1616, 0, 0, 0, 0x6ULL, nullptr, OperandInfo352 }, // Inst #2528 = SHRLV_QB_MM |
| { 2527, 3, 1, 4, 1450, 0, 0, 0, 0x6ULL, nullptr, OperandInfo352 }, // Inst #2527 = SHRLV_QB |
| { 2526, 3, 1, 4, 1661, 0, 0, 0, 0x6ULL, nullptr, OperandInfo352 }, // Inst #2526 = SHRLV_PH_MMR2 |
| { 2525, 3, 1, 4, 1497, 0, 0, 0, 0x6ULL, nullptr, OperandInfo352 }, // Inst #2525 = SHRLV_PH |
| { 2524, 3, 1, 4, 1615, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo73 }, // Inst #2524 = SHRA_R_W_MM |
| { 2523, 3, 1, 4, 1449, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo73 }, // Inst #2523 = SHRA_R_W |
| { 2522, 3, 1, 4, 1657, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo353 }, // Inst #2522 = SHRA_R_QB_MMR2 |
| { 2521, 3, 1, 4, 1493, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo353 }, // Inst #2521 = SHRA_R_QB |
| { 2520, 3, 1, 4, 1614, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo353 }, // Inst #2520 = SHRA_R_PH_MM |
| { 2519, 3, 1, 4, 1448, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo353 }, // Inst #2519 = SHRA_R_PH |
| { 2518, 3, 1, 4, 1656, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo353 }, // Inst #2518 = SHRA_QB_MMR2 |
| { 2517, 3, 1, 4, 1492, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo353 }, // Inst #2517 = SHRA_QB |
| { 2516, 3, 1, 4, 1613, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo353 }, // Inst #2516 = SHRA_PH_MM |
| { 2515, 3, 1, 4, 1447, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo353 }, // Inst #2515 = SHRA_PH |
| { 2514, 3, 1, 4, 1612, 0, 0, 0, 0x6ULL, nullptr, OperandInfo72 }, // Inst #2514 = SHRAV_R_W_MM |
| { 2513, 3, 1, 4, 1446, 0, 0, 0, 0x6ULL, nullptr, OperandInfo72 }, // Inst #2513 = SHRAV_R_W |
| { 2512, 3, 1, 4, 1659, 0, 0, 0, 0x6ULL, nullptr, OperandInfo352 }, // Inst #2512 = SHRAV_R_QB_MMR2 |
| { 2511, 3, 1, 4, 1495, 0, 0, 0, 0x6ULL, nullptr, OperandInfo352 }, // Inst #2511 = SHRAV_R_QB |
| { 2510, 3, 1, 4, 1611, 0, 0, 0, 0x6ULL, nullptr, OperandInfo352 }, // Inst #2510 = SHRAV_R_PH_MM |
| { 2509, 3, 1, 4, 1445, 0, 0, 0, 0x6ULL, nullptr, OperandInfo352 }, // Inst #2509 = SHRAV_R_PH |
| { 2508, 3, 1, 4, 1658, 0, 0, 0, 0x6ULL, nullptr, OperandInfo352 }, // Inst #2508 = SHRAV_QB_MMR2 |
| { 2507, 3, 1, 4, 1494, 0, 0, 0, 0x6ULL, nullptr, OperandInfo352 }, // Inst #2507 = SHRAV_QB |
| { 2506, 3, 1, 4, 1610, 0, 0, 0, 0x6ULL, nullptr, OperandInfo352 }, // Inst #2506 = SHRAV_PH_MM |
| { 2505, 3, 1, 4, 1444, 0, 0, 0, 0x6ULL, nullptr, OperandInfo352 }, // Inst #2505 = SHRAV_PH |
| { 2504, 3, 1, 4, 1609, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList34, OperandInfo73 }, // Inst #2504 = SHLL_S_W_MM |
| { 2503, 3, 1, 4, 1443, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList34, OperandInfo73 }, // Inst #2503 = SHLL_S_W |
| { 2502, 3, 1, 4, 1608, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList34, OperandInfo353 }, // Inst #2502 = SHLL_S_PH_MM |
| { 2501, 3, 1, 4, 1442, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList34, OperandInfo353 }, // Inst #2501 = SHLL_S_PH |
| { 2500, 3, 1, 4, 1607, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList34, OperandInfo353 }, // Inst #2500 = SHLL_QB_MM |
| { 2499, 3, 1, 4, 1441, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList34, OperandInfo353 }, // Inst #2499 = SHLL_QB |
| { 2498, 3, 1, 4, 1606, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList34, OperandInfo353 }, // Inst #2498 = SHLL_PH_MM |
| { 2497, 3, 1, 4, 1440, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList34, OperandInfo353 }, // Inst #2497 = SHLL_PH |
| { 2496, 3, 1, 4, 1605, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList34, OperandInfo72 }, // Inst #2496 = SHLLV_S_W_MM |
| { 2495, 3, 1, 4, 1439, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList34, OperandInfo72 }, // Inst #2495 = SHLLV_S_W |
| { 2494, 3, 1, 4, 1604, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList34, OperandInfo352 }, // Inst #2494 = SHLLV_S_PH_MM |
| { 2493, 3, 1, 4, 1438, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList34, OperandInfo352 }, // Inst #2493 = SHLLV_S_PH |
| { 2492, 3, 1, 4, 1603, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList34, OperandInfo352 }, // Inst #2492 = SHLLV_QB_MM |
| { 2491, 3, 1, 4, 1437, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList34, OperandInfo352 }, // Inst #2491 = SHLLV_QB |
| { 2490, 3, 1, 4, 1602, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList34, OperandInfo352 }, // Inst #2490 = SHLLV_PH_MM |
| { 2489, 3, 1, 4, 1436, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList34, OperandInfo352 }, // Inst #2489 = SHLLV_PH |
| { 2488, 3, 1, 4, 1601, 0, 0, 0, 0x6ULL, nullptr, OperandInfo351 }, // Inst #2488 = SHILO_MM |
| { 2487, 3, 1, 4, 1600, 0, 0, 0, 0x6ULL, nullptr, OperandInfo331 }, // Inst #2487 = SHILOV_MM |
| { 2486, 3, 1, 4, 1434, 0, 0, 0, 0x6ULL, nullptr, OperandInfo331 }, // Inst #2486 = SHILOV |
| { 2485, 3, 1, 4, 1435, 0, 0, 0, 0x6ULL, nullptr, OperandInfo351 }, // Inst #2485 = SHILO |
| { 2484, 3, 1, 4, 543, 0, 0, 0, 0x6ULL, nullptr, OperandInfo179 }, // Inst #2484 = SHF_W |
| { 2483, 3, 1, 4, 543, 0, 0, 0, 0x6ULL, nullptr, OperandInfo178 }, // Inst #2483 = SHF_H |
| { 2482, 3, 1, 4, 543, 0, 0, 0, 0x6ULL, nullptr, OperandInfo176 }, // Inst #2482 = SHF_B |
| { 2481, 3, 0, 4, 1101, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo96 }, // Inst #2481 = SHE_MM |
| { 2480, 3, 0, 4, 461, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo96 }, // Inst #2480 = SHE |
| { 2479, 3, 0, 4, 1178, 0, 0, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, OperandInfo113 }, // Inst #2479 = SH64 |
| { 2478, 3, 0, 2, 1155, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo345 }, // Inst #2478 = SH16_MMR6 |
| { 2477, 3, 0, 2, 1132, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo345 }, // Inst #2477 = SH16_MM |
| { 2476, 3, 0, 4, 453, 0, 0, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, OperandInfo96 }, // Inst #2476 = SH |
| { 2475, 3, 1, 4, 1207, 0, 0, 0, 0x2ULL, nullptr, OperandInfo70 }, // Inst #2475 = SEQi |
| { 2474, 3, 1, 4, 1206, 0, 0, 0, 0x1ULL, nullptr, OperandInfo71 }, // Inst #2474 = SEQ |
| { 2473, 4, 1, 4, 1327, 0, 0, 0, 0x6ULL, nullptr, OperandInfo350 }, // Inst #2473 = SEL_S_MMR6 |
| { 2472, 4, 1, 4, 1233, 0, 0, 0, 0x6ULL, nullptr, OperandInfo350 }, // Inst #2472 = SEL_S |
| { 2471, 4, 1, 4, 1326, 0, 0, 0, 0x6ULL, nullptr, OperandInfo302 }, // Inst #2471 = SEL_D_MMR6 |
| { 2470, 4, 1, 4, 1232, 0, 0, 0, 0x6ULL, nullptr, OperandInfo302 }, // Inst #2470 = SEL_D |
| { 2469, 3, 1, 4, 1325, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo250 }, // Inst #2469 = SELNEZ_S_MMR6 |
| { 2468, 3, 1, 4, 1221, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo250 }, // Inst #2468 = SELNEZ_S |
| { 2467, 3, 1, 4, 797, 0, 0, 0, 0x6ULL, nullptr, OperandInfo72 }, // Inst #2467 = SELNEZ_MMR6 |
| { 2466, 3, 1, 4, 1324, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo173 }, // Inst #2466 = SELNEZ_D_MMR6 |
| { 2465, 3, 1, 4, 1222, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo173 }, // Inst #2465 = SELNEZ_D |
| { 2464, 3, 1, 4, 852, 0, 0, 0, 0x6ULL, nullptr, OperandInfo71 }, // Inst #2464 = SELNEZ64 |
| { 2463, 3, 1, 4, 734, 0, 0, 0, 0x6ULL, nullptr, OperandInfo72 }, // Inst #2463 = SELNEZ |
| { 2462, 3, 1, 4, 1325, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo250 }, // Inst #2462 = SELEQZ_S_MMR6 |
| { 2461, 3, 1, 4, 1221, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo250 }, // Inst #2461 = SELEQZ_S |
| { 2460, 3, 1, 4, 797, 0, 0, 0, 0x6ULL, nullptr, OperandInfo72 }, // Inst #2460 = SELEQZ_MMR6 |
| { 2459, 3, 1, 4, 1324, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo173 }, // Inst #2459 = SELEQZ_D_MMR6 |
| { 2458, 3, 1, 4, 1222, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo173 }, // Inst #2458 = SELEQZ_D |
| { 2457, 3, 1, 4, 852, 0, 0, 0, 0x6ULL, nullptr, OperandInfo71 }, // Inst #2457 = SELEQZ64 |
| { 2456, 3, 1, 4, 734, 0, 0, 0, 0x6ULL, nullptr, OperandInfo72 }, // Inst #2456 = SELEQZ |
| { 2455, 2, 1, 4, 759, 0, 0, 0, 0x1ULL, nullptr, OperandInfo45 }, // Inst #2455 = SEH_MM |
| { 2454, 2, 1, 4, 811, 0, 0, 0, 0x1ULL, nullptr, OperandInfo122 }, // Inst #2454 = SEH64 |
| { 2453, 2, 1, 4, 503, 0, 0, 0, 0x1ULL, nullptr, OperandInfo45 }, // Inst #2453 = SEH |
| { 2452, 2, 1, 4, 758, 0, 0, 0, 0x1ULL, nullptr, OperandInfo45 }, // Inst #2452 = SEB_MM |
| { 2451, 2, 1, 4, 810, 0, 0, 0, 0x1ULL, nullptr, OperandInfo122 }, // Inst #2451 = SEB64 |
| { 2450, 2, 1, 4, 502, 0, 0, 0, 0x1ULL, nullptr, OperandInfo45 }, // Inst #2450 = SEB |
| { 2449, 3, 0, 4, 700, 0, 0, 0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, OperandInfo285 }, // Inst #2449 = SDXC164 |
| { 2448, 3, 0, 4, 700, 0, 0, 0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, OperandInfo284 }, // Inst #2448 = SDXC1 |
| { 2447, 3, 0, 4, 1183, 0, 0, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, OperandInfo113 }, // Inst #2447 = SDR |
| { 2446, 3, 0, 4, 1182, 0, 0, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, OperandInfo113 }, // Inst #2446 = SDL |
| { 2445, 2, 0, 4, 885, 0, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList6, OperandInfo45 }, // Inst #2445 = SDIV_MM |
| { 2444, 2, 0, 4, 865, 0, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList6, OperandInfo45 }, // Inst #2444 = SDIV |
| { 2443, 3, 0, 4, 458, 0, 0, 0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, OperandInfo278 }, // Inst #2443 = SDC3 |
| { 2442, 3, 0, 4, 1085, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo276 }, // Inst #2442 = SDC2_R6 |
| { 2441, 3, 0, 4, 1154, 0, 0, 0|(1ULL<<MCID::MayStore), 0x6ULL, nullptr, OperandInfo277 }, // Inst #2441 = SDC2_MMR6 |
| { 2440, 3, 0, 4, 457, 0, 0, 0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, OperandInfo276 }, // Inst #2440 = SDC2 |
| { 2439, 3, 0, 4, 1290, 0, 0, 0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, OperandInfo275 }, // Inst #2439 = SDC1_MM_D64 |
| { 2438, 3, 0, 4, 1290, 0, 0, 0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, OperandInfo158 }, // Inst #2438 = SDC1_MM_D32 |
| { 2437, 3, 0, 4, 1338, 0, 0, 0|(1ULL<<MCID::MayStore), 0x6ULL, nullptr, OperandInfo275 }, // Inst #2437 = SDC1_D64_MMR6 |
| { 2436, 3, 0, 4, 699, 0, 0, 0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, OperandInfo275 }, // Inst #2436 = SDC164 |
| { 2435, 3, 0, 4, 699, 0, 0, 0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, OperandInfo158 }, // Inst #2435 = SDC1 |
| { 2434, 1, 0, 4, 938, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo2 }, // Inst #2434 = SDBBP_R6 |
| { 2433, 1, 0, 4, 1008, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo2 }, // Inst #2433 = SDBBP_MMR6 |
| { 2432, 1, 0, 4, 967, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, OperandInfo2 }, // Inst #2432 = SDBBP_MM |
| { 2431, 1, 0, 2, 1008, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo2 }, // Inst #2431 = SDBBP16_MMR6 |
| { 2430, 1, 0, 2, 967, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo2 }, // Inst #2430 = SDBBP16_MM |
| { 2429, 1, 0, 4, 389, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, OperandInfo2 }, // Inst #2429 = SDBBP |
| { 2428, 3, 0, 4, 1175, 0, 0, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, OperandInfo113 }, // Inst #2428 = SD |
| { 2427, 4, 1, 4, 1086, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo347 }, // Inst #2427 = SC_R6 |
| { 2426, 4, 1, 4, 1080, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo346 }, // Inst #2426 = SC_MMR6 |
| { 2425, 4, 1, 4, 1131, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo346 }, // Inst #2425 = SC_MM |
| { 2424, 4, 1, 4, 1105, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo346 }, // Inst #2424 = SCE_MM |
| { 2423, 4, 1, 4, 463, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo346 }, // Inst #2423 = SCE |
| { 2422, 4, 1, 4, 1189, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo349 }, // Inst #2422 = SCD_R6 |
| { 2421, 4, 1, 4, 1176, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo348 }, // Inst #2421 = SCD |
| { 2420, 4, 1, 4, 1188, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo347 }, // Inst #2420 = SC64_R6 |
| { 2419, 4, 1, 4, 1176, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo346 }, // Inst #2419 = SC64 |
| { 2418, 4, 1, 4, 459, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo346 }, // Inst #2418 = SC |
| { 2417, 3, 0, 4, 1153, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo96 }, // Inst #2417 = SB_MMR6 |
| { 2416, 3, 0, 4, 1100, 0, 0, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, OperandInfo96 }, // Inst #2416 = SB_MM |
| { 2415, 3, 0, 4, 1099, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo96 }, // Inst #2415 = SBE_MM |
| { 2414, 3, 0, 4, 460, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo96 }, // Inst #2414 = SBE |
| { 2413, 3, 0, 4, 1177, 0, 0, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, OperandInfo113 }, // Inst #2413 = SB64 |
| { 2412, 3, 0, 2, 1153, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo345 }, // Inst #2412 = SB16_MMR6 |
| { 2411, 3, 0, 2, 1130, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo345 }, // Inst #2411 = SB16_MM |
| { 2410, 3, 0, 4, 452, 0, 0, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, OperandInfo96 }, // Inst #2410 = SB |
| { 2409, 3, 1, 4, 527, 0, 0, 0, 0x6ULL, nullptr, OperandInfo179 }, // Inst #2409 = SAT_U_W |
| { 2408, 3, 1, 4, 527, 0, 0, 0, 0x6ULL, nullptr, OperandInfo178 }, // Inst #2408 = SAT_U_H |
| { 2407, 3, 1, 4, 527, 0, 0, 0, 0x6ULL, nullptr, OperandInfo177 }, // Inst #2407 = SAT_U_D |
| { 2406, 3, 1, 4, 527, 0, 0, 0, 0x6ULL, nullptr, OperandInfo176 }, // Inst #2406 = SAT_U_B |
| { 2405, 3, 1, 4, 527, 0, 0, 0, 0x6ULL, nullptr, OperandInfo179 }, // Inst #2405 = SAT_S_W |
| { 2404, 3, 1, 4, 527, 0, 0, 0, 0x6ULL, nullptr, OperandInfo178 }, // Inst #2404 = SAT_S_H |
| { 2403, 3, 1, 4, 527, 0, 0, 0, 0x6ULL, nullptr, OperandInfo177 }, // Inst #2403 = SAT_S_D |
| { 2402, 3, 1, 4, 527, 0, 0, 0, 0x6ULL, nullptr, OperandInfo176 }, // Inst #2402 = SAT_S_B |
| { 2401, 2, 0, 4, 1210, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, OperandInfo122 }, // Inst #2401 = SAAD |
| { 2400, 2, 0, 4, 1210, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, OperandInfo122 }, // Inst #2400 = SAA |
| { 2399, 0, 0, 2, 1108, 1, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, nullptr }, // Inst #2399 = RestoreX16 |
| { 2398, 0, 0, 2, 1108, 1, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, nullptr }, // Inst #2398 = Restore16 |
| { 2397, 2, 1, 4, 1288, 0, 0, 0, 0x4ULL, nullptr, OperandInfo207 }, // Inst #2397 = RSQRT_S_MM |
| { 2396, 2, 1, 4, 655, 0, 0, 0, 0x4ULL, nullptr, OperandInfo207 }, // Inst #2396 = RSQRT_S |
| { 2395, 2, 1, 4, 1289, 0, 0, 0, 0x4ULL, nullptr, OperandInfo203 }, // Inst #2395 = RSQRT_D64_MM |
| { 2394, 2, 1, 4, 653, 0, 0, 0, 0x4ULL, nullptr, OperandInfo203 }, // Inst #2394 = RSQRT_D64 |
| { 2393, 2, 1, 4, 1289, 0, 0, 0, 0x4ULL, nullptr, OperandInfo248 }, // Inst #2393 = RSQRT_D32_MM |
| { 2392, 2, 1, 4, 653, 0, 0, 0, 0x4ULL, nullptr, OperandInfo248 }, // Inst #2392 = RSQRT_D32 |
| { 2391, 2, 1, 4, 1309, 0, 0, 0, 0x4ULL, nullptr, OperandInfo207 }, // Inst #2391 = ROUND_W_S_MMR6 |
| { 2390, 2, 1, 4, 1255, 0, 0, 0, 0x4ULL, nullptr, OperandInfo207 }, // Inst #2390 = ROUND_W_S_MM |
| { 2389, 2, 1, 4, 719, 0, 0, 0, 0x4ULL, nullptr, OperandInfo207 }, // Inst #2389 = ROUND_W_S |
| { 2388, 2, 1, 4, 1255, 0, 0, 0, 0x4ULL, nullptr, OperandInfo205 }, // Inst #2388 = ROUND_W_MM |
| { 2387, 2, 1, 4, 1309, 0, 0, 0, 0x4ULL, nullptr, OperandInfo203 }, // Inst #2387 = ROUND_W_D_MMR6 |
| { 2386, 2, 1, 4, 719, 0, 0, 0, 0x4ULL, nullptr, OperandInfo206 }, // Inst #2386 = ROUND_W_D64 |
| { 2385, 2, 1, 4, 719, 0, 0, 0, 0x4ULL, nullptr, OperandInfo205 }, // Inst #2385 = ROUND_W_D32 |
| { 2384, 2, 1, 4, 1309, 0, 0, 0, 0x4ULL, nullptr, OperandInfo204 }, // Inst #2384 = ROUND_L_S_MMR6 |
| { 2383, 2, 1, 4, 719, 0, 0, 0, 0x4ULL, nullptr, OperandInfo204 }, // Inst #2383 = ROUND_L_S |
| { 2382, 2, 1, 4, 1309, 0, 0, 0, 0x4ULL, nullptr, OperandInfo203 }, // Inst #2382 = ROUND_L_D_MMR6 |
| { 2381, 2, 1, 4, 719, 0, 0, 0, 0x4ULL, nullptr, OperandInfo203 }, // Inst #2381 = ROUND_L_D64 |
| { 2380, 3, 1, 4, 757, 0, 0, 0, 0x1ULL, nullptr, OperandInfo73 }, // Inst #2380 = ROTR_MM |
| { 2379, 3, 1, 4, 756, 0, 0, 0, 0x1ULL, nullptr, OperandInfo72 }, // Inst #2379 = ROTRV_MM |
| { 2378, 3, 1, 4, 720, 0, 0, 0, 0x1ULL, nullptr, OperandInfo72 }, // Inst #2378 = ROTRV |
| { 2377, 3, 1, 4, 501, 0, 0, 0, 0x1ULL, nullptr, OperandInfo73 }, // Inst #2377 = ROTR |
| { 2376, 2, 1, 4, 1328, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo207 }, // Inst #2376 = RINT_S_MMR6 |
| { 2375, 2, 1, 4, 1229, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo207 }, // Inst #2375 = RINT_S |
| { 2374, 2, 1, 4, 1328, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo203 }, // Inst #2374 = RINT_D_MMR6 |
| { 2373, 2, 1, 4, 1230, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo203 }, // Inst #2373 = RINT_D |
| { 2372, 2, 1, 4, 1599, 0, 0, 0, 0x6ULL, nullptr, OperandInfo344 }, // Inst #2372 = REPL_QB_MM |
| { 2371, 2, 1, 4, 1433, 0, 0, 0, 0x6ULL, nullptr, OperandInfo344 }, // Inst #2371 = REPL_QB |
| { 2370, 2, 1, 4, 1598, 0, 0, 0, 0x6ULL, nullptr, OperandInfo344 }, // Inst #2370 = REPL_PH_MM |
| { 2369, 2, 1, 4, 1432, 0, 0, 0, 0x6ULL, nullptr, OperandInfo344 }, // Inst #2369 = REPL_PH |
| { 2368, 2, 1, 4, 1597, 0, 0, 0, 0x6ULL, nullptr, OperandInfo343 }, // Inst #2368 = REPLV_QB_MM |
| { 2367, 2, 1, 4, 1431, 0, 0, 0, 0x6ULL, nullptr, OperandInfo343 }, // Inst #2367 = REPLV_QB |
| { 2366, 2, 1, 4, 1596, 0, 0, 0, 0x6ULL, nullptr, OperandInfo343 }, // Inst #2366 = REPLV_PH_MM |
| { 2365, 2, 1, 4, 1430, 0, 0, 0, 0x6ULL, nullptr, OperandInfo343 }, // Inst #2365 = REPLV_PH |
| { 2364, 2, 1, 4, 1288, 0, 0, 0, 0x4ULL, nullptr, OperandInfo207 }, // Inst #2364 = RECIP_S_MM |
| { 2363, 2, 1, 4, 654, 0, 0, 0, 0x4ULL, nullptr, OperandInfo207 }, // Inst #2363 = RECIP_S |
| { 2362, 2, 1, 4, 1289, 0, 0, 0, 0x4ULL, nullptr, OperandInfo203 }, // Inst #2362 = RECIP_D64_MM |
| { 2361, 2, 1, 4, 652, 0, 0, 0, 0x4ULL, nullptr, OperandInfo203 }, // Inst #2361 = RECIP_D64 |
| { 2360, 2, 1, 4, 1289, 0, 0, 0, 0x4ULL, nullptr, OperandInfo248 }, // Inst #2360 = RECIP_D32_MM |
| { 2359, 2, 1, 4, 652, 0, 0, 0, 0x4ULL, nullptr, OperandInfo248 }, // Inst #2359 = RECIP_D32 |
| { 2358, 2, 1, 4, 1036, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo45 }, // Inst #2358 = RDPGPR_MMR6 |
| { 2357, 3, 1, 4, 900, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, OperandInfo341 }, // Inst #2357 = RDHWR_MMR6 |
| { 2356, 3, 1, 4, 891, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, OperandInfo341 }, // Inst #2356 = RDHWR_MM |
| { 2355, 3, 1, 4, 909, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, OperandInfo342 }, // Inst #2355 = RDHWR64 |
| { 2354, 3, 1, 4, 480, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, OperandInfo341 }, // Inst #2354 = RDHWR |
| { 2353, 2, 1, 4, 1595, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, OperandInfo114 }, // Inst #2353 = RDDSP_MM |
| { 2352, 2, 1, 4, 1429, 0, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, OperandInfo114 }, // Inst #2352 = RDDSP |
| { 2351, 2, 1, 4, 1594, 0, 0, 0, 0x6ULL, nullptr, OperandInfo337 }, // Inst #2351 = RADDU_W_QB_MM |
| { 2350, 2, 1, 4, 1428, 0, 0, 0, 0x6ULL, nullptr, OperandInfo337 }, // Inst #2350 = RADDU_W_QB |
| { 2349, 3, 1, 4, 645, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo173 }, // Inst #2349 = PUU_PS64 |
| { 2348, 3, 1, 4, 645, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo173 }, // Inst #2348 = PUL_PS64 |
| { 2347, 4, 1, 4, 1655, 0, 0, 0, 0x6ULL, nullptr, OperandInfo182 }, // Inst #2347 = PREPEND_MMR2 |
| { 2346, 4, 1, 4, 1491, 0, 0, 0, 0x6ULL, nullptr, OperandInfo182 }, // Inst #2346 = PREPEND |
| { 2345, 3, 0, 4, 1087, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo202 }, // Inst #2345 = PREF_R6 |
| { 2344, 3, 0, 4, 1161, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo202 }, // Inst #2344 = PREF_MMR6 |
| { 2343, 3, 0, 4, 1139, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo202 }, // Inst #2343 = PREF_MM |
| { 2342, 3, 0, 4, 1139, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo340 }, // Inst #2342 = PREFX_MM |
| { 2341, 3, 0, 4, 1106, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo202 }, // Inst #2341 = PREFE_MM |
| { 2340, 3, 0, 4, 469, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo202 }, // Inst #2340 = PREFE |
| { 2339, 3, 0, 4, 468, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo202 }, // Inst #2339 = PREF |
| { 2338, 4, 1, 4, 1654, 0, 0, 0, 0x6ULL, nullptr, OperandInfo339 }, // Inst #2338 = PRECR_SRA_R_PH_W_MMR2 |
| { 2337, 4, 1, 4, 1490, 0, 0, 0, 0x6ULL, nullptr, OperandInfo339 }, // Inst #2337 = PRECR_SRA_R_PH_W |
| { 2336, 4, 1, 4, 1653, 0, 0, 0, 0x6ULL, nullptr, OperandInfo339 }, // Inst #2336 = PRECR_SRA_PH_W_MMR2 |
| { 2335, 4, 1, 4, 1489, 0, 0, 0, 0x6ULL, nullptr, OperandInfo339 }, // Inst #2335 = PRECR_SRA_PH_W |
| { 2334, 3, 1, 4, 1652, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo172 }, // Inst #2334 = PRECR_QB_PH_MMR2 |
| { 2333, 3, 1, 4, 1488, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo172 }, // Inst #2333 = PRECR_QB_PH |
| { 2332, 3, 1, 4, 1593, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList34, OperandInfo338 }, // Inst #2332 = PRECRQ_RS_PH_W_MM |
| { 2331, 3, 1, 4, 1427, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList34, OperandInfo338 }, // Inst #2331 = PRECRQ_RS_PH_W |
| { 2330, 3, 1, 4, 1592, 0, 0, 0, 0x6ULL, nullptr, OperandInfo172 }, // Inst #2330 = PRECRQ_QB_PH_MM |
| { 2329, 3, 1, 4, 1426, 0, 0, 0, 0x6ULL, nullptr, OperandInfo172 }, // Inst #2329 = PRECRQ_QB_PH |
| { 2328, 3, 1, 4, 1591, 0, 0, 0, 0x6ULL, nullptr, OperandInfo338 }, // Inst #2328 = PRECRQ_PH_W_MM |
| { 2327, 3, 1, 4, 1425, 0, 0, 0, 0x6ULL, nullptr, OperandInfo338 }, // Inst #2327 = PRECRQ_PH_W |
| { 2326, 3, 1, 4, 1590, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList34, OperandInfo172 }, // Inst #2326 = PRECRQU_S_QB_PH_MM |
| { 2325, 3, 1, 4, 1424, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList34, OperandInfo172 }, // Inst #2325 = PRECRQU_S_QB_PH |
| { 2324, 2, 1, 4, 1589, 0, 0, 0, 0x6ULL, nullptr, OperandInfo168 }, // Inst #2324 = PRECEU_PH_QBR_MM |
| { 2323, 2, 1, 4, 1588, 0, 0, 0, 0x6ULL, nullptr, OperandInfo168 }, // Inst #2323 = PRECEU_PH_QBRA_MM |
| { 2322, 2, 1, 4, 1422, 0, 0, 0, 0x6ULL, nullptr, OperandInfo168 }, // Inst #2322 = PRECEU_PH_QBRA |
| { 2321, 2, 1, 4, 1423, 0, 0, 0, 0x6ULL, nullptr, OperandInfo168 }, // Inst #2321 = PRECEU_PH_QBR |
| { 2320, 2, 1, 4, 1587, 0, 0, 0, 0x6ULL, nullptr, OperandInfo168 }, // Inst #2320 = PRECEU_PH_QBL_MM |
| { 2319, 2, 1, 4, 1586, 0, 0, 0, 0x6ULL, nullptr, OperandInfo168 }, // Inst #2319 = PRECEU_PH_QBLA_MM |
| { 2318, 2, 1, 4, 1420, 0, 0, 0, 0x6ULL, nullptr, OperandInfo168 }, // Inst #2318 = PRECEU_PH_QBLA |
| { 2317, 2, 1, 4, 1421, 0, 0, 0, 0x6ULL, nullptr, OperandInfo168 }, // Inst #2317 = PRECEU_PH_QBL |
| { 2316, 2, 1, 4, 1585, 0, 0, 0, 0x6ULL, nullptr, OperandInfo337 }, // Inst #2316 = PRECEQ_W_PHR_MM |
| { 2315, 2, 1, 4, 1419, 0, 0, 0, 0x6ULL, nullptr, OperandInfo337 }, // Inst #2315 = PRECEQ_W_PHR |
| { 2314, 2, 1, 4, 1584, 0, 0, 0, 0x6ULL, nullptr, OperandInfo337 }, // Inst #2314 = PRECEQ_W_PHL_MM |
| { 2313, 2, 1, 4, 1418, 0, 0, 0, 0x6ULL, nullptr, OperandInfo337 }, // Inst #2313 = PRECEQ_W_PHL |
| { 2312, 2, 1, 4, 1583, 0, 0, 0, 0x6ULL, nullptr, OperandInfo168 }, // Inst #2312 = PRECEQU_PH_QBR_MM |
| { 2311, 2, 1, 4, 1582, 0, 0, 0, 0x6ULL, nullptr, OperandInfo168 }, // Inst #2311 = PRECEQU_PH_QBRA_MM |
| { 2310, 2, 1, 4, 1416, 0, 0, 0, 0x6ULL, nullptr, OperandInfo168 }, // Inst #2310 = PRECEQU_PH_QBRA |
| { 2309, 2, 1, 4, 1417, 0, 0, 0, 0x6ULL, nullptr, OperandInfo168 }, // Inst #2309 = PRECEQU_PH_QBR |
| { 2308, 2, 1, 4, 1581, 0, 0, 0, 0x6ULL, nullptr, OperandInfo168 }, // Inst #2308 = PRECEQU_PH_QBL_MM |
| { 2307, 2, 1, 4, 1580, 0, 0, 0, 0x6ULL, nullptr, OperandInfo168 }, // Inst #2307 = PRECEQU_PH_QBLA_MM |
| { 2306, 2, 1, 4, 1414, 0, 0, 0, 0x6ULL, nullptr, OperandInfo168 }, // Inst #2306 = PRECEQU_PH_QBLA |
| { 2305, 2, 1, 4, 1415, 0, 0, 0, 0x6ULL, nullptr, OperandInfo168 }, // Inst #2305 = PRECEQU_PH_QBL |
| { 2304, 2, 1, 4, 1203, 0, 0, 0, 0x1ULL, nullptr, OperandInfo45 }, // Inst #2304 = POP |
| { 2303, 3, 1, 4, 645, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo173 }, // Inst #2303 = PLU_PS64 |
| { 2302, 3, 1, 4, 645, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo173 }, // Inst #2302 = PLL_PS64 |
| { 2301, 3, 1, 4, 1579, 1, 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL, ImplicitList11, OperandInfo172 }, // Inst #2301 = PICK_QB_MM |
| { 2300, 3, 1, 4, 1413, 1, 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL, ImplicitList11, OperandInfo172 }, // Inst #2300 = PICK_QB |
| { 2299, 3, 1, 4, 1578, 1, 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL, ImplicitList11, OperandInfo172 }, // Inst #2299 = PICK_PH_MM |
| { 2298, 3, 1, 4, 1412, 1, 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL, ImplicitList11, OperandInfo172 }, // Inst #2298 = PICK_PH |
| { 2297, 2, 1, 4, 526, 0, 0, 0, 0x6ULL, nullptr, OperandInfo77 }, // Inst #2297 = PCNT_W |
| { 2296, 2, 1, 4, 526, 0, 0, 0, 0x6ULL, nullptr, OperandInfo335 }, // Inst #2296 = PCNT_H |
| { 2295, 2, 1, 4, 526, 0, 0, 0, 0x6ULL, nullptr, OperandInfo76 }, // Inst #2295 = PCNT_D |
| { 2294, 2, 1, 4, 526, 0, 0, 0, 0x6ULL, nullptr, OperandInfo312 }, // Inst #2294 = PCNT_B |
| { 2293, 3, 1, 4, 626, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #2293 = PCKOD_W |
| { 2292, 3, 1, 4, 626, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #2292 = PCKOD_H |
| { 2291, 3, 1, 4, 626, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #2291 = PCKOD_D |
| { 2290, 3, 1, 4, 626, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #2290 = PCKOD_B |
| { 2289, 3, 1, 4, 626, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #2289 = PCKEV_W |
| { 2288, 3, 1, 4, 626, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #2288 = PCKEV_H |
| { 2287, 3, 1, 4, 626, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #2287 = PCKEV_D |
| { 2286, 3, 1, 4, 626, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #2286 = PCKEV_B |
| { 2285, 0, 0, 4, 1051, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr }, // Inst #2285 = PAUSE_MMR6 |
| { 2284, 0, 0, 4, 1034, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr }, // Inst #2284 = PAUSE_MM |
| { 2283, 0, 0, 4, 405, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr }, // Inst #2283 = PAUSE |
| { 2282, 3, 1, 4, 1577, 0, 0, 0, 0x6ULL, nullptr, OperandInfo172 }, // Inst #2282 = PACKRL_PH_MM |
| { 2281, 3, 1, 4, 1411, 0, 0, 0, 0x6ULL, nullptr, OperandInfo172 }, // Inst #2281 = PACKRL_PH |
| { 2280, 3, 1, 2, 735, 0, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, OperandInfo186 }, // Inst #2280 = OrRxRxRy16 |
| { 2279, 3, 1, 4, 755, 0, 0, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, OperandInfo73 }, // Inst #2279 = ORi_MM |
| { 2278, 3, 1, 4, 809, 0, 0, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, OperandInfo70 }, // Inst #2278 = ORi64 |
| { 2277, 3, 1, 4, 500, 0, 0, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, OperandInfo73 }, // Inst #2277 = ORi |
| { 2276, 3, 1, 4, 548, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #2276 = OR_V |
| { 2275, 3, 1, 4, 795, 0, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, OperandInfo72 }, // Inst #2275 = OR_MMR6 |
| { 2274, 3, 1, 4, 754, 0, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, OperandInfo72 }, // Inst #2274 = OR_MM |
| { 2273, 3, 1, 4, 796, 0, 0, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, OperandInfo73 }, // Inst #2273 = ORI_MMR6 |
| { 2272, 3, 1, 4, 549, 0, 0, 0, 0x6ULL, nullptr, OperandInfo176 }, // Inst #2272 = ORI_B |
| { 2271, 3, 1, 4, 843, 0, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, OperandInfo71 }, // Inst #2271 = OR64 |
| { 2270, 3, 1, 2, 795, 0, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo181 }, // Inst #2270 = OR16_MMR6 |
| { 2269, 3, 1, 2, 754, 0, 0, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo181 }, // Inst #2269 = OR16_MM |
| { 2268, 3, 1, 4, 367, 0, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, OperandInfo72 }, // Inst #2268 = OR |
| { 2267, 2, 1, 2, 735, 0, 0, 0, 0x0ULL, nullptr, OperandInfo130 }, // Inst #2267 = NotRxRy16 |
| { 2266, 2, 1, 2, 735, 0, 0, 0, 0x0ULL, nullptr, OperandInfo130 }, // Inst #2266 = NegRxRy16 |
| { 2265, 2, 1, 2, 794, 0, 0, 0, 0x0ULL, nullptr, OperandInfo336 }, // Inst #2265 = NOT16_MMR6 |
| { 2264, 2, 1, 2, 753, 0, 0, 0, 0x0ULL, nullptr, OperandInfo336 }, // Inst #2264 = NOT16_MM |
| { 2263, 3, 1, 4, 548, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #2263 = NOR_V |
| { 2262, 3, 1, 4, 793, 0, 0, 0|(1ULL<<MCID::Commutable), 0x1ULL, nullptr, OperandInfo72 }, // Inst #2262 = NOR_MMR6 |
| { 2261, 3, 1, 4, 752, 0, 0, 0|(1ULL<<MCID::Commutable), 0x1ULL, nullptr, OperandInfo72 }, // Inst #2261 = NOR_MM |
| { 2260, 3, 1, 4, 549, 0, 0, 0, 0x6ULL, nullptr, OperandInfo176 }, // Inst #2260 = NORI_B |
| { 2259, 3, 1, 4, 842, 0, 0, 0|(1ULL<<MCID::Commutable), 0x1ULL, nullptr, OperandInfo71 }, // Inst #2259 = NOR64 |
| { 2258, 3, 1, 4, 366, 0, 0, 0|(1ULL<<MCID::Commutable), 0x1ULL, nullptr, OperandInfo72 }, // Inst #2258 = NOR |
| { 2257, 4, 1, 4, 1251, 0, 0, 0, 0x4ULL, nullptr, OperandInfo306 }, // Inst #2257 = NMSUB_S_MM |
| { 2256, 4, 1, 4, 684, 0, 0, 0, 0x4ULL, nullptr, OperandInfo306 }, // Inst #2256 = NMSUB_S |
| { 2255, 4, 1, 4, 683, 0, 0, 0, 0x4ULL, nullptr, OperandInfo305 }, // Inst #2255 = NMSUB_D64 |
| { 2254, 4, 1, 4, 1252, 0, 0, 0, 0x4ULL, nullptr, OperandInfo304 }, // Inst #2254 = NMSUB_D32_MM |
| { 2253, 4, 1, 4, 683, 0, 0, 0, 0x4ULL, nullptr, OperandInfo304 }, // Inst #2253 = NMSUB_D32 |
| { 2252, 4, 1, 4, 1249, 0, 0, 0, 0x4ULL, nullptr, OperandInfo306 }, // Inst #2252 = NMADD_S_MM |
| { 2251, 4, 1, 4, 682, 0, 0, 0, 0x4ULL, nullptr, OperandInfo306 }, // Inst #2251 = NMADD_S |
| { 2250, 4, 1, 4, 681, 0, 0, 0, 0x4ULL, nullptr, OperandInfo305 }, // Inst #2250 = NMADD_D64 |
| { 2249, 4, 1, 4, 1250, 0, 0, 0, 0x4ULL, nullptr, OperandInfo304 }, // Inst #2249 = NMADD_D32_MM |
| { 2248, 4, 1, 4, 681, 0, 0, 0, 0x4ULL, nullptr, OperandInfo304 }, // Inst #2248 = NMADD_D32 |
| { 2247, 2, 1, 4, 627, 0, 0, 0, 0x6ULL, nullptr, OperandInfo77 }, // Inst #2247 = NLZC_W |
| { 2246, 2, 1, 4, 627, 0, 0, 0, 0x6ULL, nullptr, OperandInfo335 }, // Inst #2246 = NLZC_H |
| { 2245, 2, 1, 4, 627, 0, 0, 0, 0x6ULL, nullptr, OperandInfo76 }, // Inst #2245 = NLZC_D |
| { 2244, 2, 1, 4, 627, 0, 0, 0, 0x6ULL, nullptr, OperandInfo312 }, // Inst #2244 = NLZC_B |
| { 2243, 2, 1, 4, 627, 0, 0, 0, 0x6ULL, nullptr, OperandInfo77 }, // Inst #2243 = NLOC_W |
| { 2242, 2, 1, 4, 627, 0, 0, 0, 0x6ULL, nullptr, OperandInfo335 }, // Inst #2242 = NLOC_H |
| { 2241, 2, 1, 4, 627, 0, 0, 0, 0x6ULL, nullptr, OperandInfo76 }, // Inst #2241 = NLOC_D |
| { 2240, 2, 1, 4, 627, 0, 0, 0, 0x6ULL, nullptr, OperandInfo312 }, // Inst #2240 = NLOC_B |
| { 2239, 2, 1, 2, 735, 0, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo334 }, // Inst #2239 = MoveR3216 |
| { 2238, 2, 1, 2, 735, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo333 }, // Inst #2238 = Move32R16 |
| { 2237, 1, 1, 2, 735, 1, 0, 0, 0x0ULL, ImplicitList25, OperandInfo272 }, // Inst #2237 = Mflo16 |
| { 2236, 1, 1, 2, 735, 1, 0, 0|(1ULL<<MCID::MoveReg), 0x0ULL, ImplicitList23, OperandInfo272 }, // Inst #2236 = Mfhi16 |
| { 2235, 3, 1, 4, 1647, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList33, OperandInfo172 }, // Inst #2235 = MUL_S_PH_MMR2 |
| { 2234, 3, 1, 4, 1483, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList33, OperandInfo172 }, // Inst #2234 = MUL_S_PH |
| { 2233, 3, 1, 4, 872, 0, 0, 0, 0x6ULL, nullptr, OperandInfo72 }, // Inst #2233 = MUL_R6 |
| { 2232, 3, 1, 4, 676, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #2232 = MUL_Q_W |
| { 2231, 3, 1, 4, 676, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #2231 = MUL_Q_H |
| { 2230, 3, 1, 4, 1646, 0, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList33, OperandInfo172 }, // Inst #2230 = MUL_PH_MMR2 |
| { 2229, 3, 1, 4, 1482, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList33, OperandInfo172 }, // Inst #2229 = MUL_PH |
| { 2228, 3, 1, 4, 895, 0, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, OperandInfo72 }, // Inst #2228 = MUL_MMR6 |
| { 2227, 3, 1, 4, 884, 0, 2, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, ImplicitList6, OperandInfo72 }, // Inst #2227 = MUL_MM |
| { 2226, 3, 1, 4, 670, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #2226 = MULV_W |
| { 2225, 3, 1, 4, 670, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #2225 = MULV_H |
| { 2224, 3, 1, 4, 670, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #2224 = MULV_D |
| { 2223, 3, 1, 4, 670, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #2223 = MULV_B |
| { 2222, 3, 1, 4, 894, 0, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, OperandInfo72 }, // Inst #2222 = MULU_MMR6 |
| { 2221, 3, 1, 4, 871, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo72 }, // Inst #2221 = MULU |
| { 2220, 2, 0, 4, 879, 0, 2, 0|(1ULL<<MCID::Commutable), 0x1ULL, ImplicitList6, OperandInfo45 }, // Inst #2220 = MULTu_MM |
| { 2219, 2, 0, 4, 488, 0, 2, 0|(1ULL<<MCID::Commutable), 0x1ULL, ImplicitList6, OperandInfo45 }, // Inst #2219 = MULTu |
| { 2218, 2, 0, 4, 878, 0, 2, 0|(1ULL<<MCID::Commutable), 0x1ULL, ImplicitList6, OperandInfo45 }, // Inst #2218 = MULT_MM |
| { 2217, 3, 1, 4, 1576, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo143 }, // Inst #2217 = MULT_DSP_MM |
| { 2216, 3, 1, 4, 1410, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo143 }, // Inst #2216 = MULT_DSP |
| { 2215, 3, 1, 4, 1575, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo143 }, // Inst #2215 = MULTU_DSP_MM |
| { 2214, 3, 1, 4, 1409, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo143 }, // Inst #2214 = MULTU_DSP |
| { 2213, 2, 0, 4, 487, 0, 2, 0|(1ULL<<MCID::Commutable), 0x1ULL, ImplicitList6, OperandInfo45 }, // Inst #2213 = MULT |
| { 2212, 4, 1, 4, 1651, 0, 0, 0, 0x6ULL, nullptr, OperandInfo243 }, // Inst #2212 = MULSA_W_PH_MMR2 |
| { 2211, 4, 1, 4, 1487, 0, 0, 0, 0x6ULL, nullptr, OperandInfo243 }, // Inst #2211 = MULSA_W_PH |
| { 2210, 4, 1, 4, 1574, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList14, OperandInfo243 }, // Inst #2210 = MULSAQ_S_W_PH_MM |
| { 2209, 4, 1, 4, 1408, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList14, OperandInfo243 }, // Inst #2209 = MULSAQ_S_W_PH |
| { 2208, 3, 1, 4, 675, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #2208 = MULR_Q_W |
| { 2207, 3, 1, 4, 675, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #2207 = MULR_Q_H |
| { 2206, 3, 1, 4, 1213, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo173 }, // Inst #2206 = MULR_PS64 |
| { 2205, 3, 1, 4, 1650, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList33, OperandInfo72 }, // Inst #2205 = MULQ_S_W_MMR2 |
| { 2204, 3, 1, 4, 1486, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList33, OperandInfo72 }, // Inst #2204 = MULQ_S_W |
| { 2203, 3, 1, 4, 1649, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList33, OperandInfo172 }, // Inst #2203 = MULQ_S_PH_MMR2 |
| { 2202, 3, 1, 4, 1485, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList33, OperandInfo172 }, // Inst #2202 = MULQ_S_PH |
| { 2201, 3, 1, 4, 1648, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList33, OperandInfo72 }, // Inst #2201 = MULQ_RS_W_MMR2 |
| { 2200, 3, 1, 4, 1484, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList33, OperandInfo72 }, // Inst #2200 = MULQ_RS_W |
| { 2199, 3, 1, 4, 1573, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList33, OperandInfo172 }, // Inst #2199 = MULQ_RS_PH_MM |
| { 2198, 3, 1, 4, 1407, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList33, OperandInfo172 }, // Inst #2198 = MULQ_RS_PH |
| { 2197, 3, 1, 4, 1572, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList33, OperandInfo172 }, // Inst #2197 = MULEU_S_PH_QBR_MM |
| { 2196, 3, 1, 4, 1406, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList33, OperandInfo172 }, // Inst #2196 = MULEU_S_PH_QBR |
| { 2195, 3, 1, 4, 1571, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList33, OperandInfo172 }, // Inst #2195 = MULEU_S_PH_QBL_MM |
| { 2194, 3, 1, 4, 1405, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList33, OperandInfo172 }, // Inst #2194 = MULEU_S_PH_QBL |
| { 2193, 3, 1, 4, 1570, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList33, OperandInfo214 }, // Inst #2193 = MULEQ_S_W_PHR_MM |
| { 2192, 3, 1, 4, 1404, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList33, OperandInfo214 }, // Inst #2192 = MULEQ_S_W_PHR |
| { 2191, 3, 1, 4, 1569, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList33, OperandInfo214 }, // Inst #2191 = MULEQ_S_W_PHL_MM |
| { 2190, 3, 1, 4, 1403, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList33, OperandInfo214 }, // Inst #2190 = MULEQ_S_W_PHL |
| { 2189, 3, 1, 4, 486, 0, 2, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, ImplicitList6, OperandInfo72 }, // Inst #2189 = MUL |
| { 2188, 3, 1, 4, 893, 0, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, OperandInfo72 }, // Inst #2188 = MUH_MMR6 |
| { 2187, 3, 1, 4, 892, 0, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, OperandInfo72 }, // Inst #2187 = MUHU_MMR6 |
| { 2186, 3, 1, 4, 870, 0, 0, 0, 0x6ULL, nullptr, OperandInfo72 }, // Inst #2186 = MUHU |
| { 2185, 3, 1, 4, 869, 0, 0, 0, 0x6ULL, nullptr, OperandInfo72 }, // Inst #2185 = MUH |
| { 2184, 5, 1, 4, 1064, 0, 0, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo310 }, // Inst #2184 = MTTR |
| { 2183, 1, 0, 4, 1205, 0, 1, 0|(1ULL<<MCID::MoveReg), 0x1ULL, ImplicitList32, OperandInfo95 }, // Inst #2183 = MTP2 |
| { 2182, 1, 0, 4, 1205, 0, 1, 0|(1ULL<<MCID::MoveReg), 0x1ULL, ImplicitList31, OperandInfo95 }, // Inst #2182 = MTP1 |
| { 2181, 1, 0, 4, 1205, 0, 1, 0|(1ULL<<MCID::MoveReg), 0x1ULL, ImplicitList30, OperandInfo95 }, // Inst #2181 = MTP0 |
| { 2180, 1, 0, 4, 1205, 0, 4, 0|(1ULL<<MCID::MoveReg), 0x1ULL, ImplicitList29, OperandInfo95 }, // Inst #2180 = MTM2 |
| { 2179, 1, 0, 4, 1205, 0, 4, 0|(1ULL<<MCID::MoveReg), 0x1ULL, ImplicitList28, OperandInfo95 }, // Inst #2179 = MTM1 |
| { 2178, 1, 0, 4, 1205, 0, 4, 0|(1ULL<<MCID::MoveReg), 0x1ULL, ImplicitList27, OperandInfo95 }, // Inst #2178 = MTM0 |
| { 2177, 1, 0, 4, 890, 0, 1, 0|(1ULL<<MCID::MoveReg), 0x1ULL, ImplicitList25, OperandInfo58 }, // Inst #2177 = MTLO_MM |
| { 2176, 2, 1, 4, 1568, 0, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo332 }, // Inst #2176 = MTLO_DSP_MM |
| { 2175, 2, 1, 4, 1356, 0, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo332 }, // Inst #2175 = MTLO_DSP |
| { 2174, 1, 0, 4, 908, 0, 1, 0|(1ULL<<MCID::MoveReg), 0x1ULL, ImplicitList26, OperandInfo95 }, // Inst #2174 = MTLO64 |
| { 2173, 1, 0, 4, 493, 0, 1, 0|(1ULL<<MCID::MoveReg), 0x1ULL, ImplicitList25, OperandInfo58 }, // Inst #2173 = MTLO |
| { 2172, 3, 1, 4, 1567, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList4, OperandInfo331 }, // Inst #2172 = MTHLIP_MM |
| { 2171, 3, 1, 4, 1354, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList4, OperandInfo331 }, // Inst #2171 = MTHLIP |
| { 2170, 1, 0, 4, 890, 0, 1, 0|(1ULL<<MCID::MoveReg), 0x1ULL, ImplicitList23, OperandInfo58 }, // Inst #2170 = MTHI_MM |
| { 2169, 2, 1, 4, 1566, 0, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo330 }, // Inst #2169 = MTHI_DSP_MM |
| { 2168, 2, 1, 4, 1355, 0, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo330 }, // Inst #2168 = MTHI_DSP |
| { 2167, 1, 0, 4, 908, 0, 1, 0|(1ULL<<MCID::MoveReg), 0x1ULL, ImplicitList24, OperandInfo95 }, // Inst #2167 = MTHI64 |
| { 2166, 1, 0, 4, 493, 0, 1, 0|(1ULL<<MCID::MoveReg), 0x1ULL, ImplicitList23, OperandInfo58 }, // Inst #2166 = MTHI |
| { 2165, 3, 1, 4, 1079, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, OperandInfo128 }, // Inst #2165 = MTHGC0_MM |
| { 2164, 3, 1, 4, 424, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo128 }, // Inst #2164 = MTHGC0 |
| { 2163, 2, 1, 4, 1045, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo222 }, // Inst #2163 = MTHC2_MMR6 |
| { 2162, 3, 1, 4, 1270, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo329 }, // Inst #2162 = MTHC1_D64_MM |
| { 2161, 3, 1, 4, 687, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo329 }, // Inst #2161 = MTHC1_D64 |
| { 2160, 3, 1, 4, 1270, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo328 }, // Inst #2160 = MTHC1_D32_MM |
| { 2159, 3, 1, 4, 687, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo328 }, // Inst #2159 = MTHC1_D32 |
| { 2158, 3, 1, 4, 1043, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo128 }, // Inst #2158 = MTHC0_MMR6 |
| { 2157, 3, 1, 4, 1078, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, OperandInfo128 }, // Inst #2157 = MTGC0_MM |
| { 2156, 3, 1, 4, 423, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo128 }, // Inst #2156 = MTGC0 |
| { 2155, 2, 1, 4, 1045, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo222 }, // Inst #2155 = MTC2_MMR6 |
| { 2154, 3, 1, 4, 419, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo327 }, // Inst #2154 = MTC2 |
| { 2153, 2, 1, 4, 1313, 0, 0, 0|(1ULL<<MCID::Bitcast), 0x6ULL, nullptr, OperandInfo129 }, // Inst #2153 = MTC1_MMR6 |
| { 2152, 2, 1, 4, 1269, 0, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast), 0x4ULL, nullptr, OperandInfo129 }, // Inst #2152 = MTC1_MM |
| { 2151, 2, 1, 4, 1269, 0, 0, 0|(1ULL<<MCID::MoveReg), 0x4ULL, nullptr, OperandInfo135 }, // Inst #2151 = MTC1_D64_MM |
| { 2150, 2, 1, 4, 686, 0, 0, 0|(1ULL<<MCID::MoveReg), 0x4ULL, nullptr, OperandInfo135 }, // Inst #2150 = MTC1_D64 |
| { 2149, 2, 1, 4, 686, 0, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast), 0x4ULL, nullptr, OperandInfo129 }, // Inst #2149 = MTC1 |
| { 2148, 3, 1, 4, 1044, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo128 }, // Inst #2148 = MTC0_MMR6 |
| { 2147, 3, 1, 4, 417, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo128 }, // Inst #2147 = MTC0 |
| { 2146, 4, 1, 4, 1282, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo306 }, // Inst #2146 = MSUB_S_MM |
| { 2145, 4, 1, 4, 680, 0, 0, 0, 0x4ULL, nullptr, OperandInfo306 }, // Inst #2145 = MSUB_S |
| { 2144, 4, 1, 4, 674, 0, 0, 0, 0x6ULL, nullptr, OperandInfo60 }, // Inst #2144 = MSUB_Q_W |
| { 2143, 4, 1, 4, 674, 0, 0, 0, 0x6ULL, nullptr, OperandInfo61 }, // Inst #2143 = MSUB_Q_H |
| { 2142, 2, 0, 4, 882, 2, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList20, OperandInfo45 }, // Inst #2142 = MSUB_MM |
| { 2141, 4, 1, 4, 1565, 0, 0, 0, 0x6ULL, nullptr, OperandInfo243 }, // Inst #2141 = MSUB_DSP_MM |
| { 2140, 4, 1, 4, 1402, 0, 0, 0, 0x6ULL, nullptr, OperandInfo243 }, // Inst #2140 = MSUB_DSP |
| { 2139, 4, 1, 4, 679, 0, 0, 0, 0x4ULL, nullptr, OperandInfo305 }, // Inst #2139 = MSUB_D64 |
| { 2138, 4, 1, 4, 1283, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo304 }, // Inst #2138 = MSUB_D32_MM |
| { 2137, 4, 1, 4, 679, 0, 0, 0, 0x4ULL, nullptr, OperandInfo304 }, // Inst #2137 = MSUB_D32 |
| { 2136, 4, 1, 4, 668, 0, 0, 0, 0x6ULL, nullptr, OperandInfo60 }, // Inst #2136 = MSUBV_W |
| { 2135, 4, 1, 4, 668, 0, 0, 0, 0x6ULL, nullptr, OperandInfo61 }, // Inst #2135 = MSUBV_H |
| { 2134, 4, 1, 4, 668, 0, 0, 0, 0x6ULL, nullptr, OperandInfo59 }, // Inst #2134 = MSUBV_D |
| { 2133, 4, 1, 4, 668, 0, 0, 0, 0x6ULL, nullptr, OperandInfo196 }, // Inst #2133 = MSUBV_B |
| { 2132, 2, 0, 4, 883, 2, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList20, OperandInfo45 }, // Inst #2132 = MSUBU_MM |
| { 2131, 4, 1, 4, 1564, 0, 0, 0, 0x6ULL, nullptr, OperandInfo243 }, // Inst #2131 = MSUBU_DSP_MM |
| { 2130, 4, 1, 4, 1401, 0, 0, 0, 0x6ULL, nullptr, OperandInfo243 }, // Inst #2130 = MSUBU_DSP |
| { 2129, 2, 0, 4, 856, 2, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList20, OperandInfo45 }, // Inst #2129 = MSUBU |
| { 2128, 4, 1, 4, 673, 0, 0, 0, 0x6ULL, nullptr, OperandInfo60 }, // Inst #2128 = MSUBR_Q_W |
| { 2127, 4, 1, 4, 673, 0, 0, 0, 0x6ULL, nullptr, OperandInfo61 }, // Inst #2127 = MSUBR_Q_H |
| { 2126, 4, 1, 4, 1332, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo303 }, // Inst #2126 = MSUBF_S_MMR6 |
| { 2125, 4, 1, 4, 1235, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo303 }, // Inst #2125 = MSUBF_S |
| { 2124, 4, 1, 4, 1331, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo302 }, // Inst #2124 = MSUBF_D_MMR6 |
| { 2123, 4, 1, 4, 1237, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo302 }, // Inst #2123 = MSUBF_D |
| { 2122, 2, 0, 4, 855, 2, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList20, OperandInfo45 }, // Inst #2122 = MSUB |
| { 2121, 4, 1, 4, 1245, 0, 0, 0, 0x4ULL, nullptr, OperandInfo326 }, // Inst #2121 = MOVZ_I_S_MM |
| { 2120, 4, 1, 4, 709, 0, 0, 0, 0x4ULL, nullptr, OperandInfo326 }, // Inst #2120 = MOVZ_I_S |
| { 2119, 4, 1, 4, 1563, 0, 0, 0, 0x4ULL, nullptr, OperandInfo324 }, // Inst #2119 = MOVZ_I_MM |
| { 2118, 4, 1, 4, 911, 0, 0, 0, 0x4ULL, nullptr, OperandInfo325 }, // Inst #2118 = MOVZ_I_I64 |
| { 2117, 4, 1, 4, 483, 0, 0, 0, 0x4ULL, nullptr, OperandInfo324 }, // Inst #2117 = MOVZ_I_I |
| { 2116, 4, 1, 4, 708, 0, 0, 0, 0x4ULL, nullptr, OperandInfo323 }, // Inst #2116 = MOVZ_I_D64 |
| { 2115, 4, 1, 4, 1244, 0, 0, 0, 0x4ULL, nullptr, OperandInfo322 }, // Inst #2115 = MOVZ_I_D32_MM |
| { 2114, 4, 1, 4, 708, 0, 0, 0, 0x4ULL, nullptr, OperandInfo322 }, // Inst #2114 = MOVZ_I_D32 |
| { 2113, 4, 1, 4, 1217, 0, 0, 0, 0x4ULL, nullptr, OperandInfo321 }, // Inst #2113 = MOVZ_I64_S |
| { 2112, 4, 1, 4, 911, 0, 0, 0, 0x4ULL, nullptr, OperandInfo320 }, // Inst #2112 = MOVZ_I64_I64 |
| { 2111, 4, 1, 4, 911, 0, 0, 0, 0x4ULL, nullptr, OperandInfo319 }, // Inst #2111 = MOVZ_I64_I |
| { 2110, 4, 1, 4, 1220, 0, 0, 0, 0x4ULL, nullptr, OperandInfo318 }, // Inst #2110 = MOVZ_I64_D64 |
| { 2109, 4, 1, 4, 1243, 0, 0, 0, 0x4ULL, nullptr, OperandInfo317 }, // Inst #2109 = MOVT_S_MM |
| { 2108, 4, 1, 4, 534, 0, 0, 0, 0x4ULL, nullptr, OperandInfo317 }, // Inst #2108 = MOVT_S |
| { 2107, 4, 1, 4, 889, 0, 0, 0, 0x4ULL, nullptr, OperandInfo315 }, // Inst #2107 = MOVT_I_MM |
| { 2106, 4, 1, 4, 1215, 0, 0, 0, 0x4ULL, nullptr, OperandInfo316 }, // Inst #2106 = MOVT_I64 |
| { 2105, 4, 1, 4, 698, 0, 0, 0, 0x4ULL, nullptr, OperandInfo315 }, // Inst #2105 = MOVT_I |
| { 2104, 4, 1, 4, 533, 0, 0, 0, 0x4ULL, nullptr, OperandInfo314 }, // Inst #2104 = MOVT_D64 |
| { 2103, 4, 1, 4, 1242, 0, 0, 0, 0x4ULL, nullptr, OperandInfo313 }, // Inst #2103 = MOVT_D32_MM |
| { 2102, 4, 1, 4, 533, 0, 0, 0, 0x4ULL, nullptr, OperandInfo313 }, // Inst #2102 = MOVT_D32 |
| { 2101, 4, 1, 4, 1241, 0, 0, 0, 0x4ULL, nullptr, OperandInfo326 }, // Inst #2101 = MOVN_I_S_MM |
| { 2100, 4, 1, 4, 707, 0, 0, 0, 0x4ULL, nullptr, OperandInfo326 }, // Inst #2100 = MOVN_I_S |
| { 2099, 4, 1, 4, 1562, 0, 0, 0, 0x4ULL, nullptr, OperandInfo324 }, // Inst #2099 = MOVN_I_MM |
| { 2098, 4, 1, 4, 910, 0, 0, 0, 0x4ULL, nullptr, OperandInfo325 }, // Inst #2098 = MOVN_I_I64 |
| { 2097, 4, 1, 4, 482, 0, 0, 0, 0x4ULL, nullptr, OperandInfo324 }, // Inst #2097 = MOVN_I_I |
| { 2096, 4, 1, 4, 706, 0, 0, 0, 0x4ULL, nullptr, OperandInfo323 }, // Inst #2096 = MOVN_I_D64 |
| { 2095, 4, 1, 4, 1240, 0, 0, 0, 0x4ULL, nullptr, OperandInfo322 }, // Inst #2095 = MOVN_I_D32_MM |
| { 2094, 4, 1, 4, 706, 0, 0, 0, 0x4ULL, nullptr, OperandInfo322 }, // Inst #2094 = MOVN_I_D32 |
| { 2093, 4, 1, 4, 1219, 0, 0, 0, 0x4ULL, nullptr, OperandInfo321 }, // Inst #2093 = MOVN_I64_S |
| { 2092, 4, 1, 4, 910, 0, 0, 0, 0x4ULL, nullptr, OperandInfo320 }, // Inst #2092 = MOVN_I64_I64 |
| { 2091, 4, 1, 4, 910, 0, 0, 0, 0x4ULL, nullptr, OperandInfo319 }, // Inst #2091 = MOVN_I64_I |
| { 2090, 4, 1, 4, 1218, 0, 0, 0, 0x4ULL, nullptr, OperandInfo318 }, // Inst #2090 = MOVN_I64_D64 |
| { 2089, 4, 1, 4, 1239, 0, 0, 0, 0x4ULL, nullptr, OperandInfo317 }, // Inst #2089 = MOVF_S_MM |
| { 2088, 4, 1, 4, 532, 0, 0, 0, 0x4ULL, nullptr, OperandInfo317 }, // Inst #2088 = MOVF_S |
| { 2087, 4, 1, 4, 888, 0, 0, 0, 0x4ULL, nullptr, OperandInfo315 }, // Inst #2087 = MOVF_I_MM |
| { 2086, 4, 1, 4, 1216, 0, 0, 0, 0x4ULL, nullptr, OperandInfo316 }, // Inst #2086 = MOVF_I64 |
| { 2085, 4, 1, 4, 697, 0, 0, 0, 0x4ULL, nullptr, OperandInfo315 }, // Inst #2085 = MOVF_I |
| { 2084, 4, 1, 4, 531, 0, 0, 0, 0x4ULL, nullptr, OperandInfo314 }, // Inst #2084 = MOVF_D64 |
| { 2083, 4, 1, 4, 1238, 0, 0, 0, 0x4ULL, nullptr, OperandInfo313 }, // Inst #2083 = MOVF_D32_MM |
| { 2082, 4, 1, 4, 531, 0, 0, 0, 0x4ULL, nullptr, OperandInfo313 }, // Inst #2082 = MOVF_D32 |
| { 2081, 2, 1, 4, 546, 0, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo312 }, // Inst #2081 = MOVE_V |
| { 2080, 4, 2, 2, 1561, 0, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo311 }, // Inst #2080 = MOVEP_MMR6 |
| { 2079, 4, 2, 2, 751, 0, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo311 }, // Inst #2079 = MOVEP_MM |
| { 2078, 2, 1, 2, 792, 0, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo45 }, // Inst #2078 = MOVE16_MMR6 |
| { 2077, 2, 1, 2, 750, 0, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo45 }, // Inst #2077 = MOVE16_MM |
| { 2076, 3, 1, 4, 613, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #2076 = MOD_U_W |
| { 2075, 3, 1, 4, 613, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #2075 = MOD_U_H |
| { 2074, 3, 1, 4, 613, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #2074 = MOD_U_D |
| { 2073, 3, 1, 4, 613, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #2073 = MOD_U_B |
| { 2072, 3, 1, 4, 613, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #2072 = MOD_S_W |
| { 2071, 3, 1, 4, 613, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #2071 = MOD_S_H |
| { 2070, 3, 1, 4, 613, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #2070 = MOD_S_D |
| { 2069, 3, 1, 4, 613, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #2069 = MOD_S_B |
| { 2068, 3, 1, 4, 897, 0, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UsesCustomInserter), 0x6ULL, nullptr, OperandInfo72 }, // Inst #2068 = MOD_MMR6 |
| { 2067, 3, 1, 4, 896, 0, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UsesCustomInserter), 0x6ULL, nullptr, OperandInfo72 }, // Inst #2067 = MODU_MMR6 |
| { 2066, 3, 1, 4, 874, 0, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL, nullptr, OperandInfo72 }, // Inst #2066 = MODU |
| { 2065, 3, 1, 4, 1560, 0, 0, 0, 0x6ULL, nullptr, OperandInfo72 }, // Inst #2065 = MODSUB_MM |
| { 2064, 3, 1, 4, 1400, 0, 0, 0, 0x6ULL, nullptr, OperandInfo72 }, // Inst #2064 = MODSUB |
| { 2063, 3, 1, 4, 873, 0, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL, nullptr, OperandInfo72 }, // Inst #2063 = MOD |
| { 2062, 3, 1, 4, 618, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #2062 = MIN_U_W |
| { 2061, 3, 1, 4, 618, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #2061 = MIN_U_H |
| { 2060, 3, 1, 4, 618, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #2060 = MIN_U_D |
| { 2059, 3, 1, 4, 618, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #2059 = MIN_U_B |
| { 2058, 3, 1, 4, 617, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #2058 = MIN_S_W |
| { 2057, 3, 1, 4, 1319, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo250 }, // Inst #2057 = MIN_S_MMR6 |
| { 2056, 3, 1, 4, 617, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #2056 = MIN_S_H |
| { 2055, 3, 1, 4, 617, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #2055 = MIN_S_D |
| { 2054, 3, 1, 4, 617, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #2054 = MIN_S_B |
| { 2053, 3, 1, 4, 1225, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo250 }, // Inst #2053 = MIN_S |
| { 2052, 3, 1, 4, 1318, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo173 }, // Inst #2052 = MIN_D_MMR6 |
| { 2051, 3, 1, 4, 1226, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo173 }, // Inst #2051 = MIN_D |
| { 2050, 3, 1, 4, 619, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #2050 = MIN_A_W |
| { 2049, 3, 1, 4, 619, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #2049 = MIN_A_H |
| { 2048, 3, 1, 4, 619, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #2048 = MIN_A_D |
| { 2047, 3, 1, 4, 619, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #2047 = MIN_A_B |
| { 2046, 3, 1, 4, 620, 0, 0, 0, 0x6ULL, nullptr, OperandInfo179 }, // Inst #2046 = MINI_U_W |
| { 2045, 3, 1, 4, 620, 0, 0, 0, 0x6ULL, nullptr, OperandInfo178 }, // Inst #2045 = MINI_U_H |
| { 2044, 3, 1, 4, 620, 0, 0, 0, 0x6ULL, nullptr, OperandInfo177 }, // Inst #2044 = MINI_U_D |
| { 2043, 3, 1, 4, 620, 0, 0, 0, 0x6ULL, nullptr, OperandInfo176 }, // Inst #2043 = MINI_U_B |
| { 2042, 3, 1, 4, 620, 0, 0, 0, 0x6ULL, nullptr, OperandInfo179 }, // Inst #2042 = MINI_S_W |
| { 2041, 3, 1, 4, 620, 0, 0, 0, 0x6ULL, nullptr, OperandInfo178 }, // Inst #2041 = MINI_S_H |
| { 2040, 3, 1, 4, 620, 0, 0, 0, 0x6ULL, nullptr, OperandInfo177 }, // Inst #2040 = MINI_S_D |
| { 2039, 3, 1, 4, 620, 0, 0, 0, 0x6ULL, nullptr, OperandInfo176 }, // Inst #2039 = MINI_S_B |
| { 2038, 3, 1, 4, 1323, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo250 }, // Inst #2038 = MINA_S_MMR6 |
| { 2037, 3, 1, 4, 1226, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo250 }, // Inst #2037 = MINA_S |
| { 2036, 3, 1, 4, 1322, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo173 }, // Inst #2036 = MINA_D_MMR6 |
| { 2035, 3, 1, 4, 1225, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo173 }, // Inst #2035 = MINA_D |
| { 2034, 5, 1, 4, 1063, 0, 0, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo310 }, // Inst #2034 = MFTR |
| { 2033, 1, 1, 4, 887, 1, 0, 0|(1ULL<<MCID::MoveReg), 0x1ULL, ImplicitList21, OperandInfo58 }, // Inst #2033 = MFLO_MM |
| { 2032, 2, 1, 4, 1559, 0, 0, 0, 0x6ULL, nullptr, OperandInfo119 }, // Inst #2032 = MFLO_DSP_MM |
| { 2031, 2, 1, 4, 1399, 0, 0, 0|(1ULL<<MCID::MoveReg), 0x6ULL, nullptr, OperandInfo119 }, // Inst #2031 = MFLO_DSP |
| { 2030, 1, 1, 4, 906, 1, 0, 0|(1ULL<<MCID::MoveReg), 0x1ULL, ImplicitList22, OperandInfo95 }, // Inst #2030 = MFLO64 |
| { 2029, 1, 1, 2, 887, 1, 0, 0|(1ULL<<MCID::MoveReg), 0x0ULL, ImplicitList21, OperandInfo58 }, // Inst #2029 = MFLO16_MM |
| { 2028, 1, 1, 4, 478, 1, 0, 0|(1ULL<<MCID::MoveReg), 0x1ULL, ImplicitList21, OperandInfo58 }, // Inst #2028 = MFLO |
| { 2027, 1, 1, 4, 887, 1, 0, 0|(1ULL<<MCID::MoveReg), 0x1ULL, ImplicitList21, OperandInfo58 }, // Inst #2027 = MFHI_MM |
| { 2026, 2, 1, 4, 1558, 0, 0, 0, 0x6ULL, nullptr, OperandInfo119 }, // Inst #2026 = MFHI_DSP_MM |
| { 2025, 2, 1, 4, 1398, 0, 0, 0|(1ULL<<MCID::MoveReg), 0x6ULL, nullptr, OperandInfo119 }, // Inst #2025 = MFHI_DSP |
| { 2024, 1, 1, 4, 906, 1, 0, 0|(1ULL<<MCID::MoveReg), 0x1ULL, ImplicitList22, OperandInfo95 }, // Inst #2024 = MFHI64 |
| { 2023, 1, 1, 2, 887, 1, 0, 0|(1ULL<<MCID::MoveReg), 0x0ULL, ImplicitList21, OperandInfo58 }, // Inst #2023 = MFHI16_MM |
| { 2022, 1, 1, 4, 478, 1, 0, 0|(1ULL<<MCID::MoveReg), 0x1ULL, ImplicitList21, OperandInfo58 }, // Inst #2022 = MFHI |
| { 2021, 3, 1, 4, 1077, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, OperandInfo120 }, // Inst #2021 = MFHGC0_MM |
| { 2020, 3, 1, 4, 422, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo120 }, // Inst #2020 = MFHGC0 |
| { 2019, 2, 1, 4, 1042, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo209 }, // Inst #2019 = MFHC2_MMR6 |
| { 2018, 2, 1, 4, 1268, 0, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo307 }, // Inst #2018 = MFHC1_D64_MM |
| { 2017, 2, 1, 4, 696, 0, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo307 }, // Inst #2017 = MFHC1_D64 |
| { 2016, 2, 1, 4, 1268, 0, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo309 }, // Inst #2016 = MFHC1_D32_MM |
| { 2015, 2, 1, 4, 696, 0, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo309 }, // Inst #2015 = MFHC1_D32 |
| { 2014, 3, 1, 4, 1040, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo120 }, // Inst #2014 = MFHC0_MMR6 |
| { 2013, 3, 1, 4, 1076, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, OperandInfo120 }, // Inst #2013 = MFGC0_MM |
| { 2012, 3, 1, 4, 421, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo120 }, // Inst #2012 = MFGC0 |
| { 2011, 2, 1, 4, 1042, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo209 }, // Inst #2011 = MFC2_MMR6 |
| { 2010, 3, 1, 4, 418, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo308 }, // Inst #2010 = MFC2 |
| { 2009, 2, 1, 4, 1312, 0, 0, 0|(1ULL<<MCID::Bitcast), 0x6ULL, nullptr, OperandInfo121 }, // Inst #2009 = MFC1_MMR6 |
| { 2008, 2, 1, 4, 1267, 0, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast), 0x4ULL, nullptr, OperandInfo121 }, // Inst #2008 = MFC1_MM |
| { 2007, 2, 1, 4, 695, 0, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo307 }, // Inst #2007 = MFC1_D64 |
| { 2006, 2, 1, 4, 695, 0, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast), 0x4ULL, nullptr, OperandInfo121 }, // Inst #2006 = MFC1 |
| { 2005, 3, 1, 4, 1041, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo120 }, // Inst #2005 = MFC0_MMR6 |
| { 2004, 3, 1, 4, 416, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo120 }, // Inst #2004 = MFC0 |
| { 2003, 3, 1, 4, 618, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #2003 = MAX_U_W |
| { 2002, 3, 1, 4, 618, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #2002 = MAX_U_H |
| { 2001, 3, 1, 4, 618, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #2001 = MAX_U_D |
| { 2000, 3, 1, 4, 618, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #2000 = MAX_U_B |
| { 1999, 3, 1, 4, 617, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1999 = MAX_S_W |
| { 1998, 3, 1, 4, 1317, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo250 }, // Inst #1998 = MAX_S_MMR6 |
| { 1997, 3, 1, 4, 617, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #1997 = MAX_S_H |
| { 1996, 3, 1, 4, 617, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1996 = MAX_S_D |
| { 1995, 3, 1, 4, 617, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #1995 = MAX_S_B |
| { 1994, 3, 1, 4, 1223, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo250 }, // Inst #1994 = MAX_S |
| { 1993, 3, 1, 4, 1316, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo173 }, // Inst #1993 = MAX_D_MMR6 |
| { 1992, 3, 1, 4, 1224, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo173 }, // Inst #1992 = MAX_D |
| { 1991, 3, 1, 4, 619, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1991 = MAX_A_W |
| { 1990, 3, 1, 4, 619, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #1990 = MAX_A_H |
| { 1989, 3, 1, 4, 619, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1989 = MAX_A_D |
| { 1988, 3, 1, 4, 619, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #1988 = MAX_A_B |
| { 1987, 3, 1, 4, 620, 0, 0, 0, 0x6ULL, nullptr, OperandInfo179 }, // Inst #1987 = MAXI_U_W |
| { 1986, 3, 1, 4, 620, 0, 0, 0, 0x6ULL, nullptr, OperandInfo178 }, // Inst #1986 = MAXI_U_H |
| { 1985, 3, 1, 4, 620, 0, 0, 0, 0x6ULL, nullptr, OperandInfo177 }, // Inst #1985 = MAXI_U_D |
| { 1984, 3, 1, 4, 620, 0, 0, 0, 0x6ULL, nullptr, OperandInfo176 }, // Inst #1984 = MAXI_U_B |
| { 1983, 3, 1, 4, 620, 0, 0, 0, 0x6ULL, nullptr, OperandInfo179 }, // Inst #1983 = MAXI_S_W |
| { 1982, 3, 1, 4, 620, 0, 0, 0, 0x6ULL, nullptr, OperandInfo178 }, // Inst #1982 = MAXI_S_H |
| { 1981, 3, 1, 4, 620, 0, 0, 0, 0x6ULL, nullptr, OperandInfo177 }, // Inst #1981 = MAXI_S_D |
| { 1980, 3, 1, 4, 620, 0, 0, 0, 0x6ULL, nullptr, OperandInfo176 }, // Inst #1980 = MAXI_S_B |
| { 1979, 3, 1, 4, 1321, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo250 }, // Inst #1979 = MAXA_S_MMR6 |
| { 1978, 3, 1, 4, 1223, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo250 }, // Inst #1978 = MAXA_S |
| { 1977, 3, 1, 4, 1320, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo173 }, // Inst #1977 = MAXA_D_MMR6 |
| { 1976, 3, 1, 4, 1224, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo173 }, // Inst #1976 = MAXA_D |
| { 1975, 4, 1, 4, 1557, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList14, OperandInfo243 }, // Inst #1975 = MAQ_S_W_PHR_MM |
| { 1974, 4, 1, 4, 1397, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList14, OperandInfo243 }, // Inst #1974 = MAQ_S_W_PHR |
| { 1973, 4, 1, 4, 1556, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList14, OperandInfo243 }, // Inst #1973 = MAQ_S_W_PHL_MM |
| { 1972, 4, 1, 4, 1396, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList14, OperandInfo243 }, // Inst #1972 = MAQ_S_W_PHL |
| { 1971, 4, 1, 4, 1555, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList14, OperandInfo243 }, // Inst #1971 = MAQ_SA_W_PHR_MM |
| { 1970, 4, 1, 4, 1395, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList14, OperandInfo243 }, // Inst #1970 = MAQ_SA_W_PHR |
| { 1969, 4, 1, 4, 1554, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList14, OperandInfo243 }, // Inst #1969 = MAQ_SA_W_PHL_MM |
| { 1968, 4, 1, 4, 1394, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList14, OperandInfo243 }, // Inst #1968 = MAQ_SA_W_PHL |
| { 1967, 4, 1, 4, 1253, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo306 }, // Inst #1967 = MADD_S_MM |
| { 1966, 4, 1, 4, 678, 0, 0, 0, 0x4ULL, nullptr, OperandInfo306 }, // Inst #1966 = MADD_S |
| { 1965, 4, 1, 4, 672, 0, 0, 0, 0x6ULL, nullptr, OperandInfo60 }, // Inst #1965 = MADD_Q_W |
| { 1964, 4, 1, 4, 672, 0, 0, 0, 0x6ULL, nullptr, OperandInfo61 }, // Inst #1964 = MADD_Q_H |
| { 1963, 2, 0, 4, 880, 2, 2, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList20, OperandInfo45 }, // Inst #1963 = MADD_MM |
| { 1962, 4, 1, 4, 1553, 0, 0, 0, 0x6ULL, nullptr, OperandInfo243 }, // Inst #1962 = MADD_DSP_MM |
| { 1961, 4, 1, 4, 1393, 0, 0, 0, 0x6ULL, nullptr, OperandInfo243 }, // Inst #1961 = MADD_DSP |
| { 1960, 4, 1, 4, 677, 0, 0, 0, 0x4ULL, nullptr, OperandInfo305 }, // Inst #1960 = MADD_D64 |
| { 1959, 4, 1, 4, 1254, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo304 }, // Inst #1959 = MADD_D32_MM |
| { 1958, 4, 1, 4, 677, 0, 0, 0, 0x4ULL, nullptr, OperandInfo304 }, // Inst #1958 = MADD_D32 |
| { 1957, 4, 1, 4, 669, 0, 0, 0, 0x6ULL, nullptr, OperandInfo60 }, // Inst #1957 = MADDV_W |
| { 1956, 4, 1, 4, 669, 0, 0, 0, 0x6ULL, nullptr, OperandInfo61 }, // Inst #1956 = MADDV_H |
| { 1955, 4, 1, 4, 669, 0, 0, 0, 0x6ULL, nullptr, OperandInfo59 }, // Inst #1955 = MADDV_D |
| { 1954, 4, 1, 4, 669, 0, 0, 0, 0x6ULL, nullptr, OperandInfo196 }, // Inst #1954 = MADDV_B |
| { 1953, 2, 0, 4, 881, 2, 2, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList20, OperandInfo45 }, // Inst #1953 = MADDU_MM |
| { 1952, 4, 1, 4, 1552, 0, 0, 0, 0x6ULL, nullptr, OperandInfo243 }, // Inst #1952 = MADDU_DSP_MM |
| { 1951, 4, 1, 4, 1392, 0, 0, 0, 0x6ULL, nullptr, OperandInfo243 }, // Inst #1951 = MADDU_DSP |
| { 1950, 2, 0, 4, 854, 2, 2, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList20, OperandInfo45 }, // Inst #1950 = MADDU |
| { 1949, 4, 1, 4, 671, 0, 0, 0, 0x6ULL, nullptr, OperandInfo60 }, // Inst #1949 = MADDR_Q_W |
| { 1948, 4, 1, 4, 671, 0, 0, 0, 0x6ULL, nullptr, OperandInfo61 }, // Inst #1948 = MADDR_Q_H |
| { 1947, 4, 1, 4, 1330, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo303 }, // Inst #1947 = MADDF_S_MMR6 |
| { 1946, 4, 1, 4, 1234, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo303 }, // Inst #1946 = MADDF_S |
| { 1945, 4, 1, 4, 1329, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo302 }, // Inst #1945 = MADDF_D_MMR6 |
| { 1944, 4, 1, 4, 1236, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo302 }, // Inst #1944 = MADDF_D |
| { 1943, 2, 0, 4, 853, 2, 2, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList20, OperandInfo45 }, // Inst #1943 = MADD |
| { 1942, 3, 1, 4, 1113, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo185 }, // Inst #1942 = LwRxSpImmX16 |
| { 1941, 3, 1, 4, 1113, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo300 }, // Inst #1941 = LwRxRyOffMemX16 |
| { 1940, 3, 1, 4, 1113, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo301 }, // Inst #1940 = LwRxPcTcpX16 |
| { 1939, 3, 1, 2, 1113, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo301 }, // Inst #1939 = LwRxPcTcp16 |
| { 1938, 2, 1, 4, 735, 0, 0, 0, 0x0ULL, nullptr, OperandInfo183 }, // Inst #1938 = LiRxImmX16 |
| { 1937, 2, 1, 4, 735, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo183 }, // Inst #1937 = LiRxImmAlignX16 |
| { 1936, 2, 1, 2, 735, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo183 }, // Inst #1936 = LiRxImm16 |
| { 1935, 3, 1, 4, 1112, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo300 }, // Inst #1935 = LhuRxRyOffMemX16 |
| { 1934, 3, 1, 4, 1111, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo300 }, // Inst #1934 = LhRxRyOffMemX16 |
| { 1933, 3, 1, 4, 1110, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo300 }, // Inst #1933 = LbuRxRyOffMemX16 |
| { 1932, 3, 1, 4, 1109, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo300 }, // Inst #1932 = LbRxRyOffMemX16 |
| { 1931, 3, 1, 4, 1165, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, OperandInfo113 }, // Inst #1931 = LWu |
| { 1930, 3, 1, 4, 1152, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, OperandInfo96 }, // Inst #1930 = LW_MMR6 |
| { 1929, 3, 1, 4, 1123, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, OperandInfo96 }, // Inst #1929 = LW_MM |
| { 1928, 3, 1, 4, 1551, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, OperandInfo274 }, // Inst #1928 = LWX_MM |
| { 1927, 3, 1, 4, 1129, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, nullptr, OperandInfo274 }, // Inst #1927 = LWXS_MM |
| { 1926, 3, 1, 4, 1299, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, OperandInfo299 }, // Inst #1926 = LWXC1_MM |
| { 1925, 3, 1, 4, 713, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, OperandInfo299 }, // Inst #1925 = LWXC1 |
| { 1924, 3, 1, 4, 1391, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, OperandInfo274 }, // Inst #1924 = LWX |
| { 1923, 3, 1, 4, 1128, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, OperandInfo96 }, // Inst #1923 = LWU_MM |
| { 1922, 2, 1, 4, 1184, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo114 }, // Inst #1922 = LWUPC |
| { 1921, 3, 1, 2, 1123, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo298 }, // Inst #1921 = LWSP_MM |
| { 1920, 4, 1, 4, 1127, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, OperandInfo295 }, // Inst #1920 = LWR_MM |
| { 1919, 4, 1, 4, 1097, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, OperandInfo295 }, // Inst #1919 = LWRE_MM |
| { 1918, 4, 1, 4, 451, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo295 }, // Inst #1918 = LWRE |
| { 1917, 4, 1, 4, 1172, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, OperandInfo283 }, // Inst #1917 = LWR64 |
| { 1916, 4, 1, 4, 449, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, OperandInfo295 }, // Inst #1916 = LWR |
| { 1915, 4, 2, 4, 1126, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo297 }, // Inst #1915 = LWP_MM |
| { 1914, 2, 1, 4, 1151, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo114 }, // Inst #1914 = LWPC_MMR6 |
| { 1913, 2, 1, 4, 447, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo114 }, // Inst #1913 = LWPC |
| { 1912, 3, 1, 4, 1125, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo110 }, // Inst #1912 = LWM32_MM |
| { 1911, 3, 1, 2, 1149, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo296 }, // Inst #1911 = LWM16_MMR6 |
| { 1910, 3, 1, 2, 1125, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo296 }, // Inst #1910 = LWM16_MM |
| { 1909, 4, 1, 4, 1124, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, OperandInfo295 }, // Inst #1909 = LWL_MM |
| { 1908, 4, 1, 4, 1096, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, OperandInfo295 }, // Inst #1908 = LWLE_MM |
| { 1907, 4, 1, 4, 450, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo295 }, // Inst #1907 = LWLE |
| { 1906, 4, 1, 4, 1171, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, OperandInfo283 }, // Inst #1906 = LWL64 |
| { 1905, 4, 1, 4, 448, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, OperandInfo295 }, // Inst #1905 = LWL |
| { 1904, 3, 1, 2, 1123, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo294 }, // Inst #1904 = LWGP_MM |
| { 1903, 3, 1, 4, 1095, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo96 }, // Inst #1903 = LWE_MM |
| { 1902, 3, 1, 4, 445, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo96 }, // Inst #1902 = LWE |
| { 1901, 3, 1, 4, 1506, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo293 }, // Inst #1901 = LWDSP_MM |
| { 1900, 3, 1, 4, 1343, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo293 }, // Inst #1900 = LWDSP |
| { 1899, 3, 1, 4, 438, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, OperandInfo278 }, // Inst #1899 = LWC3 |
| { 1898, 3, 1, 4, 1083, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo276 }, // Inst #1898 = LWC2_R6 |
| { 1897, 3, 1, 4, 1150, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, OperandInfo277 }, // Inst #1897 = LWC2_MMR6 |
| { 1896, 3, 1, 4, 437, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, OperandInfo276 }, // Inst #1896 = LWC2 |
| { 1895, 3, 1, 4, 1298, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, OperandInfo292 }, // Inst #1895 = LWC1_MM |
| { 1894, 3, 1, 4, 712, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, OperandInfo292 }, // Inst #1894 = LWC1 |
| { 1893, 3, 1, 4, 1170, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, OperandInfo113 }, // Inst #1893 = LW64 |
| { 1892, 3, 1, 2, 1123, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo273 }, // Inst #1892 = LW16_MM |
| { 1891, 3, 1, 4, 435, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, OperandInfo96 }, // Inst #1891 = LW |
| { 1890, 2, 1, 4, 749, 0, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2ULL, nullptr, OperandInfo114 }, // Inst #1890 = LUi_MM |
| { 1889, 2, 1, 4, 841, 0, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2ULL, nullptr, OperandInfo112 }, // Inst #1889 = LUi64 |
| { 1888, 2, 1, 4, 365, 0, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2ULL, nullptr, OperandInfo114 }, // Inst #1888 = LUi |
| { 1887, 3, 1, 4, 1297, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, nullptr, OperandInfo285 }, // Inst #1887 = LUXC1_MM |
| { 1886, 3, 1, 4, 714, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, nullptr, OperandInfo285 }, // Inst #1886 = LUXC164 |
| { 1885, 3, 1, 4, 714, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, nullptr, OperandInfo284 }, // Inst #1885 = LUXC1 |
| { 1884, 2, 1, 4, 791, 0, 0, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, OperandInfo114 }, // Inst #1884 = LUI_MMR6 |
| { 1883, 4, 1, 4, 733, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo180 }, // Inst #1883 = LSA_R6 |
| { 1882, 4, 1, 4, 790, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo180 }, // Inst #1882 = LSA_MMR6 |
| { 1881, 4, 1, 4, 513, 0, 0, 0, 0x6ULL, nullptr, OperandInfo180 }, // Inst #1881 = LSA |
| { 1880, 3, 1, 4, 1082, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo290 }, // Inst #1880 = LL_R6 |
| { 1879, 3, 1, 4, 1148, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo96 }, // Inst #1879 = LL_MMR6 |
| { 1878, 3, 1, 4, 1122, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo96 }, // Inst #1878 = LL_MM |
| { 1877, 3, 1, 4, 1098, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo96 }, // Inst #1877 = LLE_MM |
| { 1876, 3, 1, 4, 446, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo96 }, // Inst #1876 = LLE |
| { 1875, 3, 1, 4, 1186, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo291 }, // Inst #1875 = LLD_R6 |
| { 1874, 3, 1, 4, 1164, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo113 }, // Inst #1874 = LLD |
| { 1873, 3, 1, 4, 1187, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo290 }, // Inst #1873 = LL64_R6 |
| { 1872, 3, 1, 4, 1164, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo96 }, // Inst #1872 = LL64 |
| { 1871, 3, 1, 4, 436, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo96 }, // Inst #1871 = LL |
| { 1870, 2, 1, 2, 789, 0, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, OperandInfo169 }, // Inst #1870 = LI16_MMR6 |
| { 1869, 2, 1, 2, 748, 0, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, OperandInfo169 }, // Inst #1869 = LI16_MM |
| { 1868, 3, 1, 4, 1120, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, OperandInfo96 }, // Inst #1868 = LHu_MM |
| { 1867, 3, 1, 4, 1094, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo96 }, // Inst #1867 = LHuE_MM |
| { 1866, 3, 1, 4, 444, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo96 }, // Inst #1866 = LHuE |
| { 1865, 3, 1, 4, 1169, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, OperandInfo113 }, // Inst #1865 = LHu64 |
| { 1864, 3, 1, 4, 434, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, OperandInfo96 }, // Inst #1864 = LHu |
| { 1863, 3, 1, 4, 1121, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, OperandInfo96 }, // Inst #1863 = LH_MM |
| { 1862, 3, 1, 4, 1550, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, OperandInfo274 }, // Inst #1862 = LHX_MM |
| { 1861, 3, 1, 4, 1390, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, OperandInfo274 }, // Inst #1861 = LHX |
| { 1860, 3, 1, 2, 1120, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo273 }, // Inst #1860 = LHU16_MM |
| { 1859, 3, 1, 4, 1093, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo96 }, // Inst #1859 = LHE_MM |
| { 1858, 3, 1, 4, 443, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo96 }, // Inst #1858 = LHE |
| { 1857, 3, 1, 4, 1168, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, OperandInfo113 }, // Inst #1857 = LH64 |
| { 1856, 3, 1, 4, 433, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, OperandInfo96 }, // Inst #1856 = LH |
| { 1855, 3, 1, 4, 738, 0, 0, 0, 0x2ULL, nullptr, OperandInfo96 }, // Inst #1855 = LEA_ADDiu_MM |
| { 1854, 3, 1, 4, 840, 0, 0, 0, 0x2ULL, nullptr, OperandInfo113 }, // Inst #1854 = LEA_ADDiu64 |
| { 1853, 3, 1, 4, 724, 0, 0, 0, 0x2ULL, nullptr, OperandInfo96 }, // Inst #1853 = LEA_ADDiu |
| { 1852, 3, 1, 4, 715, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, OperandInfo289 }, // Inst #1852 = LD_W |
| { 1851, 3, 1, 4, 715, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, OperandInfo288 }, // Inst #1851 = LD_H |
| { 1850, 3, 1, 4, 715, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, OperandInfo287 }, // Inst #1850 = LD_D |
| { 1849, 3, 1, 4, 715, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, OperandInfo286 }, // Inst #1849 = LD_B |
| { 1848, 3, 1, 4, 711, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, OperandInfo285 }, // Inst #1848 = LDXC164 |
| { 1847, 3, 1, 4, 711, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, OperandInfo284 }, // Inst #1847 = LDXC1 |
| { 1846, 4, 1, 4, 1174, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, OperandInfo283 }, // Inst #1846 = LDR |
| { 1845, 2, 1, 4, 1185, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo112 }, // Inst #1845 = LDPC |
| { 1844, 4, 1, 4, 1173, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, OperandInfo283 }, // Inst #1844 = LDL |
| { 1843, 2, 1, 4, 547, 0, 0, 0|(1ULL<<MCID::Rematerializable), 0x6ULL, nullptr, OperandInfo282 }, // Inst #1843 = LDI_W |
| { 1842, 2, 1, 4, 547, 0, 0, 0|(1ULL<<MCID::Rematerializable), 0x6ULL, nullptr, OperandInfo281 }, // Inst #1842 = LDI_H |
| { 1841, 2, 1, 4, 547, 0, 0, 0|(1ULL<<MCID::Rematerializable), 0x6ULL, nullptr, OperandInfo280 }, // Inst #1841 = LDI_D |
| { 1840, 2, 1, 4, 547, 0, 0, 0|(1ULL<<MCID::Rematerializable), 0x6ULL, nullptr, OperandInfo279 }, // Inst #1840 = LDI_B |
| { 1839, 3, 1, 4, 440, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, OperandInfo278 }, // Inst #1839 = LDC3 |
| { 1838, 3, 1, 4, 1081, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo276 }, // Inst #1838 = LDC2_R6 |
| { 1837, 3, 1, 4, 1147, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, OperandInfo277 }, // Inst #1837 = LDC2_MMR6 |
| { 1836, 3, 1, 4, 439, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, OperandInfo276 }, // Inst #1836 = LDC2 |
| { 1835, 3, 1, 4, 1296, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, OperandInfo275 }, // Inst #1835 = LDC1_MM_D64 |
| { 1834, 3, 1, 4, 1296, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, OperandInfo158 }, // Inst #1834 = LDC1_MM_D32 |
| { 1833, 3, 1, 4, 1339, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, OperandInfo275 }, // Inst #1833 = LDC1_D64_MMR6 |
| { 1832, 3, 1, 4, 710, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, OperandInfo275 }, // Inst #1832 = LDC164 |
| { 1831, 3, 1, 4, 710, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, OperandInfo158 }, // Inst #1831 = LDC1 |
| { 1830, 3, 1, 4, 1163, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, OperandInfo113 }, // Inst #1830 = LD |
| { 1829, 3, 1, 4, 1118, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, OperandInfo96 }, // Inst #1829 = LBu_MM |
| { 1828, 3, 1, 4, 1092, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo96 }, // Inst #1828 = LBuE_MM |
| { 1827, 3, 1, 4, 442, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo96 }, // Inst #1827 = LBuE |
| { 1826, 3, 1, 4, 1167, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, OperandInfo113 }, // Inst #1826 = LBu64 |
| { 1825, 3, 1, 4, 432, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, OperandInfo96 }, // Inst #1825 = LBu |
| { 1824, 3, 1, 4, 1146, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo96 }, // Inst #1824 = LB_MMR6 |
| { 1823, 3, 1, 4, 1119, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, OperandInfo96 }, // Inst #1823 = LB_MM |
| { 1822, 3, 1, 4, 1145, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo96 }, // Inst #1822 = LBU_MMR6 |
| { 1821, 3, 1, 4, 1549, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, OperandInfo274 }, // Inst #1821 = LBUX_MM |
| { 1820, 3, 1, 4, 1389, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, OperandInfo274 }, // Inst #1820 = LBUX |
| { 1819, 3, 1, 2, 1118, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo273 }, // Inst #1819 = LBU16_MM |
| { 1818, 3, 1, 4, 1091, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo96 }, // Inst #1818 = LBE_MM |
| { 1817, 3, 1, 4, 441, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo96 }, // Inst #1817 = LBE |
| { 1816, 3, 1, 4, 1166, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, OperandInfo113 }, // Inst #1816 = LB64 |
| { 1815, 3, 1, 4, 431, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, OperandInfo96 }, // Inst #1815 = LB |
| { 1814, 1, 0, 2, 942, 0, 1, 0|(1ULL<<MCID::Call), 0x0ULL, ImplicitList3, OperandInfo272 }, // Inst #1814 = JumpLinkReg16 |
| { 1813, 1, 0, 2, 939, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, OperandInfo272 }, // Inst #1813 = JrcRx16 |
| { 1812, 0, 0, 2, 939, 0, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #1812 = JrcRa16 |
| { 1811, 0, 0, 2, 939, 0, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #1811 = JrRa16 |
| { 1810, 1, 0, 6, 941, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList3, OperandInfo2 }, // Inst #1810 = JalB16 |
| { 1809, 1, 0, 6, 941, 0, 1, 0|(1ULL<<MCID::Call), 0x0ULL, ImplicitList3, OperandInfo2 }, // Inst #1809 = Jal16 |
| { 1808, 1, 0, 4, 955, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x13ULL, ImplicitList2, OperandInfo2 }, // Inst #1808 = J_MM |
| { 1807, 1, 0, 4, 954, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x11ULL, nullptr, OperandInfo58 }, // Inst #1807 = JR_MM |
| { 1806, 1, 0, 4, 934, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo58 }, // Inst #1806 = JR_HB_R6 |
| { 1805, 1, 0, 4, 1022, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo95 }, // Inst #1805 = JR_HB64_R6 |
| { 1804, 1, 0, 4, 1014, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x13ULL, nullptr, OperandInfo95 }, // Inst #1804 = JR_HB64 |
| { 1803, 1, 0, 4, 386, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x13ULL, nullptr, OperandInfo58 }, // Inst #1803 = JR_HB |
| { 1802, 1, 0, 2, 993, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo2 }, // Inst #1802 = JRCADDIUSP_MMR6 |
| { 1801, 1, 0, 2, 995, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo58 }, // Inst #1801 = JRC16_MMR6 |
| { 1800, 1, 0, 2, 994, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo58 }, // Inst #1800 = JRC16_MM |
| { 1799, 1, 0, 2, 993, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo2 }, // Inst #1799 = JRADDIUSP |
| { 1798, 1, 0, 4, 1011, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x11ULL, nullptr, OperandInfo95 }, // Inst #1798 = JR64 |
| { 1797, 1, 0, 2, 954, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo58 }, // Inst #1797 = JR16_MM |
| { 1796, 1, 0, 4, 923, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x11ULL, nullptr, OperandInfo58 }, // Inst #1796 = JR |
| { 1795, 2, 0, 4, 992, 0, 1, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList2, OperandInfo114 }, // Inst #1795 = JIC_MMR6 |
| { 1794, 2, 0, 4, 1019, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, ImplicitList2, OperandInfo112 }, // Inst #1794 = JIC64 |
| { 1793, 2, 0, 4, 933, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, ImplicitList2, OperandInfo114 }, // Inst #1793 = JIC |
| { 1792, 2, 0, 4, 1004, 0, 1, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList3, OperandInfo114 }, // Inst #1792 = JIALC_MMR6 |
| { 1791, 2, 0, 4, 1021, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, ImplicitList3, OperandInfo112 }, // Inst #1791 = JIALC64 |
| { 1790, 2, 0, 4, 928, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, ImplicitList3, OperandInfo114 }, // Inst #1790 = JIALC |
| { 1789, 1, 0, 4, 962, 0, 1, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call), 0x13ULL, ImplicitList3, OperandInfo2 }, // Inst #1789 = JAL_MM |
| { 1788, 1, 0, 4, 962, 0, 1, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call), 0x13ULL, ImplicitList3, OperandInfo2 }, // Inst #1788 = JALX_MM |
| { 1787, 1, 0, 4, 409, 0, 1, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call), 0x13ULL, ImplicitList3, OperandInfo2 }, // Inst #1787 = JALX |
| { 1786, 1, 0, 4, 961, 0, 1, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x3ULL, ImplicitList3, OperandInfo2 }, // Inst #1786 = JALS_MM |
| { 1785, 2, 1, 4, 959, 0, 1, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x11ULL, ImplicitList3, OperandInfo45 }, // Inst #1785 = JALR_MM |
| { 1784, 2, 1, 4, 1013, 0, 0, 0|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x13ULL, nullptr, OperandInfo122 }, // Inst #1784 = JALR_HB64 |
| { 1783, 2, 1, 4, 408, 0, 0, 0|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x13ULL, nullptr, OperandInfo45 }, // Inst #1783 = JALR_HB |
| { 1782, 2, 1, 4, 960, 0, 1, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList3, OperandInfo45 }, // Inst #1782 = JALRS_MM |
| { 1781, 1, 0, 2, 960, 0, 1, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList3, OperandInfo58 }, // Inst #1781 = JALRS16_MM |
| { 1780, 2, 1, 4, 1003, 0, 1, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList3, OperandInfo45 }, // Inst #1780 = JALRC_MMR6 |
| { 1779, 2, 1, 4, 1002, 0, 0, 0|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::UnmodeledSideEffects), 0x3ULL, nullptr, OperandInfo45 }, // Inst #1779 = JALRC_HB_MMR6 |
| { 1778, 1, 0, 2, 1001, 0, 1, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, ImplicitList3, OperandInfo58 }, // Inst #1778 = JALRC16_MMR6 |
| { 1777, 2, 1, 4, 1012, 0, 1, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x11ULL, ImplicitList3, OperandInfo122 }, // Inst #1777 = JALR64 |
| { 1776, 1, 0, 2, 959, 0, 1, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, ImplicitList3, OperandInfo58 }, // Inst #1776 = JALR16_MM |
| { 1775, 2, 1, 4, 407, 0, 1, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x11ULL, ImplicitList3, OperandInfo45 }, // Inst #1775 = JALR |
| { 1774, 1, 0, 4, 406, 0, 1, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call), 0x13ULL, ImplicitList3, OperandInfo2 }, // Inst #1774 = JAL |
| { 1773, 1, 0, 4, 922, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x13ULL, ImplicitList2, OperandInfo2 }, // Inst #1773 = J |
| { 1772, 5, 1, 4, 788, 0, 0, 0, 0x1ULL, nullptr, OperandInfo262 }, // Inst #1772 = INS_MMR6 |
| { 1771, 5, 1, 4, 747, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, OperandInfo262 }, // Inst #1771 = INS_MM |
| { 1770, 3, 1, 4, 1548, 2, 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL, ImplicitList19, OperandInfo267 }, // Inst #1770 = INSV_MM |
| { 1769, 5, 1, 4, 607, 0, 0, 0, 0x6ULL, nullptr, OperandInfo271 }, // Inst #1769 = INSVE_W |
| { 1768, 5, 1, 4, 607, 0, 0, 0, 0x6ULL, nullptr, OperandInfo270 }, // Inst #1768 = INSVE_H |
| { 1767, 5, 1, 4, 607, 0, 0, 0, 0x6ULL, nullptr, OperandInfo269 }, // Inst #1767 = INSVE_D |
| { 1766, 5, 1, 4, 607, 0, 0, 0, 0x6ULL, nullptr, OperandInfo268 }, // Inst #1766 = INSVE_B |
| { 1765, 3, 1, 4, 1353, 2, 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL, ImplicitList19, OperandInfo267 }, // Inst #1765 = INSV |
| { 1764, 4, 1, 4, 518, 0, 0, 0, 0x6ULL, nullptr, OperandInfo266 }, // Inst #1764 = INSERT_W |
| { 1763, 4, 1, 4, 518, 0, 0, 0, 0x6ULL, nullptr, OperandInfo265 }, // Inst #1763 = INSERT_H |
| { 1762, 4, 1, 4, 518, 0, 0, 0, 0x6ULL, nullptr, OperandInfo264 }, // Inst #1762 = INSERT_D |
| { 1761, 4, 1, 4, 518, 0, 0, 0, 0x6ULL, nullptr, OperandInfo263 }, // Inst #1761 = INSERT_B |
| { 1760, 5, 1, 4, 495, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, OperandInfo262 }, // Inst #1760 = INS |
| { 1759, 3, 1, 4, 605, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1759 = ILVR_W |
| { 1758, 3, 1, 4, 605, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #1758 = ILVR_H |
| { 1757, 3, 1, 4, 605, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1757 = ILVR_D |
| { 1756, 3, 1, 4, 605, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #1756 = ILVR_B |
| { 1755, 3, 1, 4, 606, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1755 = ILVOD_W |
| { 1754, 3, 1, 4, 606, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #1754 = ILVOD_H |
| { 1753, 3, 1, 4, 606, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1753 = ILVOD_D |
| { 1752, 3, 1, 4, 606, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #1752 = ILVOD_B |
| { 1751, 3, 1, 4, 605, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1751 = ILVL_W |
| { 1750, 3, 1, 4, 605, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #1750 = ILVL_H |
| { 1749, 3, 1, 4, 605, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1749 = ILVL_D |
| { 1748, 3, 1, 4, 605, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #1748 = ILVL_B |
| { 1747, 3, 1, 4, 606, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1747 = ILVEV_W |
| { 1746, 3, 1, 4, 606, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #1746 = ILVEV_H |
| { 1745, 3, 1, 4, 606, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1745 = ILVEV_D |
| { 1744, 3, 1, 4, 606, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #1744 = ILVEV_B |
| { 1743, 1, 0, 4, 1069, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo2 }, // Inst #1743 = HYPCALL_MM |
| { 1742, 1, 0, 4, 420, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo2 }, // Inst #1742 = HYPCALL |
| { 1741, 3, 1, 4, 616, 0, 0, 0, 0x6ULL, nullptr, OperandInfo239 }, // Inst #1741 = HSUB_U_W |
| { 1740, 3, 1, 4, 616, 0, 0, 0, 0x6ULL, nullptr, OperandInfo238 }, // Inst #1740 = HSUB_U_H |
| { 1739, 3, 1, 4, 616, 0, 0, 0, 0x6ULL, nullptr, OperandInfo237 }, // Inst #1739 = HSUB_U_D |
| { 1738, 3, 1, 4, 616, 0, 0, 0, 0x6ULL, nullptr, OperandInfo239 }, // Inst #1738 = HSUB_S_W |
| { 1737, 3, 1, 4, 616, 0, 0, 0, 0x6ULL, nullptr, OperandInfo238 }, // Inst #1737 = HSUB_S_H |
| { 1736, 3, 1, 4, 616, 0, 0, 0, 0x6ULL, nullptr, OperandInfo237 }, // Inst #1736 = HSUB_S_D |
| { 1735, 3, 1, 4, 615, 0, 0, 0, 0x6ULL, nullptr, OperandInfo239 }, // Inst #1735 = HADD_U_W |
| { 1734, 3, 1, 4, 615, 0, 0, 0, 0x6ULL, nullptr, OperandInfo238 }, // Inst #1734 = HADD_U_H |
| { 1733, 3, 1, 4, 615, 0, 0, 0, 0x6ULL, nullptr, OperandInfo237 }, // Inst #1733 = HADD_U_D |
| { 1732, 3, 1, 4, 615, 0, 0, 0, 0x6ULL, nullptr, OperandInfo239 }, // Inst #1732 = HADD_S_W |
| { 1731, 3, 1, 4, 615, 0, 0, 0, 0x6ULL, nullptr, OperandInfo238 }, // Inst #1731 = HADD_S_H |
| { 1730, 3, 1, 4, 615, 0, 0, 0, 0x6ULL, nullptr, OperandInfo237 }, // Inst #1730 = HADD_S_D |
| { 1729, 2, 0, 4, 1144, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo114 }, // Inst #1729 = GINVT_MMR6 |
| { 1728, 2, 0, 4, 1090, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo114 }, // Inst #1728 = GINVT |
| { 1727, 1, 0, 4, 1143, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo58 }, // Inst #1727 = GINVI_MMR6 |
| { 1726, 1, 0, 4, 1089, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo58 }, // Inst #1726 = GINVI |
| { 1725, 2, 1, 4, 595, 0, 0, 0, 0x6ULL, nullptr, OperandInfo77 }, // Inst #1725 = FTRUNC_U_W |
| { 1724, 2, 1, 4, 595, 0, 0, 0, 0x6ULL, nullptr, OperandInfo76 }, // Inst #1724 = FTRUNC_U_D |
| { 1723, 2, 1, 4, 595, 0, 0, 0, 0x6ULL, nullptr, OperandInfo77 }, // Inst #1723 = FTRUNC_S_W |
| { 1722, 2, 1, 4, 595, 0, 0, 0, 0x6ULL, nullptr, OperandInfo76 }, // Inst #1722 = FTRUNC_S_D |
| { 1721, 3, 1, 4, 594, 0, 0, 0, 0x6ULL, nullptr, OperandInfo255 }, // Inst #1721 = FTQ_W |
| { 1720, 3, 1, 4, 594, 0, 0, 0, 0x6ULL, nullptr, OperandInfo254 }, // Inst #1720 = FTQ_H |
| { 1719, 2, 1, 4, 592, 0, 0, 0, 0x6ULL, nullptr, OperandInfo77 }, // Inst #1719 = FTINT_U_W |
| { 1718, 2, 1, 4, 592, 0, 0, 0, 0x6ULL, nullptr, OperandInfo76 }, // Inst #1718 = FTINT_U_D |
| { 1717, 2, 1, 4, 592, 0, 0, 0, 0x6ULL, nullptr, OperandInfo77 }, // Inst #1717 = FTINT_S_W |
| { 1716, 2, 1, 4, 592, 0, 0, 0, 0x6ULL, nullptr, OperandInfo76 }, // Inst #1716 = FTINT_S_D |
| { 1715, 3, 1, 4, 576, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1715 = FSUN_W |
| { 1714, 3, 1, 4, 576, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1714 = FSUN_D |
| { 1713, 3, 1, 4, 575, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1713 = FSUNE_W |
| { 1712, 3, 1, 4, 575, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1712 = FSUNE_D |
| { 1711, 3, 1, 4, 574, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1711 = FSULT_W |
| { 1710, 3, 1, 4, 574, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1710 = FSULT_D |
| { 1709, 3, 1, 4, 573, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1709 = FSULE_W |
| { 1708, 3, 1, 4, 573, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1708 = FSULE_D |
| { 1707, 3, 1, 4, 572, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1707 = FSUEQ_W |
| { 1706, 3, 1, 4, 572, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1706 = FSUEQ_D |
| { 1705, 3, 1, 4, 664, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1705 = FSUB_W |
| { 1704, 3, 1, 4, 1335, 0, 0, 0, 0x6ULL, nullptr, OperandInfo250 }, // Inst #1704 = FSUB_S_MMR6 |
| { 1703, 3, 1, 4, 1281, 0, 0, 0, 0x4ULL, nullptr, OperandInfo250 }, // Inst #1703 = FSUB_S_MM |
| { 1702, 3, 1, 4, 636, 0, 0, 0, 0x4ULL, nullptr, OperandInfo250 }, // Inst #1702 = FSUB_S |
| { 1701, 3, 1, 4, 635, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo173 }, // Inst #1701 = FSUB_PS64 |
| { 1700, 3, 1, 4, 1280, 0, 0, 0, 0x4ULL, nullptr, OperandInfo173 }, // Inst #1700 = FSUB_D64_MM |
| { 1699, 3, 1, 4, 634, 0, 0, 0, 0x4ULL, nullptr, OperandInfo173 }, // Inst #1699 = FSUB_D64 |
| { 1698, 3, 1, 4, 1280, 0, 0, 0, 0x4ULL, nullptr, OperandInfo249 }, // Inst #1698 = FSUB_D32_MM |
| { 1697, 3, 1, 4, 634, 0, 0, 0, 0x4ULL, nullptr, OperandInfo249 }, // Inst #1697 = FSUB_D32 |
| { 1696, 3, 1, 4, 664, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1696 = FSUB_D |
| { 1695, 2, 1, 4, 660, 0, 0, 0, 0x6ULL, nullptr, OperandInfo77 }, // Inst #1695 = FSQRT_W |
| { 1694, 2, 1, 4, 1286, 0, 0, 0, 0x4ULL, nullptr, OperandInfo207 }, // Inst #1694 = FSQRT_S_MM |
| { 1693, 2, 1, 4, 648, 0, 0, 0, 0x4ULL, nullptr, OperandInfo207 }, // Inst #1693 = FSQRT_S |
| { 1692, 2, 1, 4, 1287, 0, 0, 0, 0x4ULL, nullptr, OperandInfo203 }, // Inst #1692 = FSQRT_D64_MM |
| { 1691, 2, 1, 4, 649, 0, 0, 0, 0x4ULL, nullptr, OperandInfo203 }, // Inst #1691 = FSQRT_D64 |
| { 1690, 2, 1, 4, 1287, 0, 0, 0, 0x4ULL, nullptr, OperandInfo248 }, // Inst #1690 = FSQRT_D32_MM |
| { 1689, 2, 1, 4, 649, 0, 0, 0, 0x4ULL, nullptr, OperandInfo248 }, // Inst #1689 = FSQRT_D32 |
| { 1688, 2, 1, 4, 661, 0, 0, 0, 0x6ULL, nullptr, OperandInfo76 }, // Inst #1688 = FSQRT_D |
| { 1687, 3, 1, 4, 571, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1687 = FSOR_W |
| { 1686, 3, 1, 4, 571, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1686 = FSOR_D |
| { 1685, 3, 1, 4, 571, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1685 = FSNE_W |
| { 1684, 3, 1, 4, 571, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1684 = FSNE_D |
| { 1683, 3, 1, 4, 571, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1683 = FSLT_W |
| { 1682, 3, 1, 4, 571, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1682 = FSLT_D |
| { 1681, 3, 1, 4, 571, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1681 = FSLE_W |
| { 1680, 3, 1, 4, 571, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1680 = FSLE_D |
| { 1679, 3, 1, 4, 571, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1679 = FSEQ_W |
| { 1678, 3, 1, 4, 571, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1678 = FSEQ_D |
| { 1677, 3, 1, 4, 571, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1677 = FSAF_W |
| { 1676, 3, 1, 4, 571, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1676 = FSAF_D |
| { 1675, 2, 1, 4, 651, 0, 0, 0, 0x6ULL, nullptr, OperandInfo77 }, // Inst #1675 = FRSQRT_W |
| { 1674, 2, 1, 4, 651, 0, 0, 0, 0x6ULL, nullptr, OperandInfo76 }, // Inst #1674 = FRSQRT_D |
| { 1673, 2, 1, 4, 593, 0, 0, 0, 0x6ULL, nullptr, OperandInfo77 }, // Inst #1673 = FRINT_W |
| { 1672, 2, 1, 4, 593, 0, 0, 0, 0x6ULL, nullptr, OperandInfo76 }, // Inst #1672 = FRINT_D |
| { 1671, 2, 1, 4, 650, 0, 0, 0, 0x6ULL, nullptr, OperandInfo77 }, // Inst #1671 = FRCP_W |
| { 1670, 2, 1, 4, 650, 0, 0, 0, 0x6ULL, nullptr, OperandInfo76 }, // Inst #1670 = FRCP_D |
| { 1669, 3, 2, 4, 1066, 0, 0, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo72 }, // Inst #1669 = FORK |
| { 1668, 2, 1, 4, 1300, 0, 0, 0, 0x4ULL, nullptr, OperandInfo207 }, // Inst #1668 = FNEG_S_MMR6 |
| { 1667, 2, 1, 4, 1273, 0, 0, 0, 0x4ULL, nullptr, OperandInfo207 }, // Inst #1667 = FNEG_S_MM |
| { 1666, 2, 1, 4, 537, 0, 0, 0, 0x4ULL, nullptr, OperandInfo207 }, // Inst #1666 = FNEG_S |
| { 1665, 2, 1, 4, 1273, 0, 0, 0, 0x4ULL, nullptr, OperandInfo203 }, // Inst #1665 = FNEG_D64_MM |
| { 1664, 2, 1, 4, 537, 0, 0, 0, 0x4ULL, nullptr, OperandInfo203 }, // Inst #1664 = FNEG_D64 |
| { 1663, 2, 1, 4, 1273, 0, 0, 0, 0x4ULL, nullptr, OperandInfo248 }, // Inst #1663 = FNEG_D32_MM |
| { 1662, 2, 1, 4, 537, 0, 0, 0, 0x4ULL, nullptr, OperandInfo248 }, // Inst #1662 = FNEG_D32 |
| { 1661, 3, 1, 4, 662, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1661 = FMUL_W |
| { 1660, 3, 1, 4, 1334, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo250 }, // Inst #1660 = FMUL_S_MMR6 |
| { 1659, 3, 1, 4, 1279, 0, 0, 0|(1ULL<<MCID::Commutable), 0x4ULL, nullptr, OperandInfo250 }, // Inst #1659 = FMUL_S_MM |
| { 1658, 3, 1, 4, 633, 0, 0, 0|(1ULL<<MCID::Commutable), 0x4ULL, nullptr, OperandInfo250 }, // Inst #1658 = FMUL_S |
| { 1657, 3, 1, 4, 632, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo173 }, // Inst #1657 = FMUL_PS64 |
| { 1656, 3, 1, 4, 1278, 0, 0, 0|(1ULL<<MCID::Commutable), 0x4ULL, nullptr, OperandInfo173 }, // Inst #1656 = FMUL_D64_MM |
| { 1655, 3, 1, 4, 631, 0, 0, 0|(1ULL<<MCID::Commutable), 0x4ULL, nullptr, OperandInfo173 }, // Inst #1655 = FMUL_D64 |
| { 1654, 3, 1, 4, 1278, 0, 0, 0|(1ULL<<MCID::Commutable), 0x4ULL, nullptr, OperandInfo249 }, // Inst #1654 = FMUL_D32_MM |
| { 1653, 3, 1, 4, 631, 0, 0, 0|(1ULL<<MCID::Commutable), 0x4ULL, nullptr, OperandInfo249 }, // Inst #1653 = FMUL_D32 |
| { 1652, 3, 1, 4, 662, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1652 = FMUL_D |
| { 1651, 4, 1, 4, 657, 0, 0, 0, 0x6ULL, nullptr, OperandInfo60 }, // Inst #1651 = FMSUB_W |
| { 1650, 4, 1, 4, 657, 0, 0, 0, 0x6ULL, nullptr, OperandInfo59 }, // Inst #1650 = FMSUB_D |
| { 1649, 2, 1, 4, 1333, 0, 0, 0, 0x4ULL, nullptr, OperandInfo207 }, // Inst #1649 = FMOV_S_MMR6 |
| { 1648, 2, 1, 4, 1277, 0, 0, 0|(1ULL<<MCID::MoveReg), 0x4ULL, nullptr, OperandInfo207 }, // Inst #1648 = FMOV_S_MM |
| { 1647, 2, 1, 4, 536, 0, 0, 0|(1ULL<<MCID::MoveReg), 0x4ULL, nullptr, OperandInfo207 }, // Inst #1647 = FMOV_S |
| { 1646, 2, 1, 4, 1336, 0, 0, 0, 0x4ULL, nullptr, OperandInfo203 }, // Inst #1646 = FMOV_D_MMR6 |
| { 1645, 2, 1, 4, 1276, 0, 0, 0, 0x4ULL, nullptr, OperandInfo203 }, // Inst #1645 = FMOV_D64_MM |
| { 1644, 2, 1, 4, 535, 0, 0, 0|(1ULL<<MCID::MoveReg), 0x4ULL, nullptr, OperandInfo203 }, // Inst #1644 = FMOV_D64 |
| { 1643, 2, 1, 4, 1276, 0, 0, 0, 0x4ULL, nullptr, OperandInfo248 }, // Inst #1643 = FMOV_D32_MM |
| { 1642, 2, 1, 4, 535, 0, 0, 0|(1ULL<<MCID::MoveReg), 0x4ULL, nullptr, OperandInfo248 }, // Inst #1642 = FMOV_D32 |
| { 1641, 3, 1, 4, 603, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1641 = FMIN_W |
| { 1640, 3, 1, 4, 603, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1640 = FMIN_D |
| { 1639, 3, 1, 4, 602, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1639 = FMIN_A_W |
| { 1638, 3, 1, 4, 602, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1638 = FMIN_A_D |
| { 1637, 3, 1, 4, 601, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1637 = FMAX_W |
| { 1636, 3, 1, 4, 601, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1636 = FMAX_D |
| { 1635, 3, 1, 4, 600, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1635 = FMAX_A_W |
| { 1634, 3, 1, 4, 600, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1634 = FMAX_A_D |
| { 1633, 4, 1, 4, 656, 0, 0, 0, 0x6ULL, nullptr, OperandInfo60 }, // Inst #1633 = FMADD_W |
| { 1632, 4, 1, 4, 656, 0, 0, 0, 0x6ULL, nullptr, OperandInfo59 }, // Inst #1632 = FMADD_D |
| { 1631, 2, 1, 4, 1310, 0, 0, 0, 0x4ULL, nullptr, OperandInfo207 }, // Inst #1631 = FLOOR_W_S_MMR6 |
| { 1630, 2, 1, 4, 1248, 0, 0, 0, 0x4ULL, nullptr, OperandInfo207 }, // Inst #1630 = FLOOR_W_S_MM |
| { 1629, 2, 1, 4, 718, 0, 0, 0, 0x4ULL, nullptr, OperandInfo207 }, // Inst #1629 = FLOOR_W_S |
| { 1628, 2, 1, 4, 1248, 0, 0, 0, 0x4ULL, nullptr, OperandInfo205 }, // Inst #1628 = FLOOR_W_MM |
| { 1627, 2, 1, 4, 1310, 0, 0, 0, 0x4ULL, nullptr, OperandInfo205 }, // Inst #1627 = FLOOR_W_D_MMR6 |
| { 1626, 2, 1, 4, 718, 0, 0, 0, 0x4ULL, nullptr, OperandInfo206 }, // Inst #1626 = FLOOR_W_D64 |
| { 1625, 2, 1, 4, 718, 0, 0, 0, 0x4ULL, nullptr, OperandInfo205 }, // Inst #1625 = FLOOR_W_D32 |
| { 1624, 2, 1, 4, 1310, 0, 0, 0, 0x4ULL, nullptr, OperandInfo204 }, // Inst #1624 = FLOOR_L_S_MMR6 |
| { 1623, 2, 1, 4, 718, 0, 0, 0, 0x4ULL, nullptr, OperandInfo204 }, // Inst #1623 = FLOOR_L_S |
| { 1622, 2, 1, 4, 1310, 0, 0, 0, 0x4ULL, nullptr, OperandInfo203 }, // Inst #1622 = FLOOR_L_D_MMR6 |
| { 1621, 2, 1, 4, 718, 0, 0, 0, 0x4ULL, nullptr, OperandInfo203 }, // Inst #1621 = FLOOR_L_D64 |
| { 1620, 2, 1, 4, 604, 0, 0, 0, 0x6ULL, nullptr, OperandInfo77 }, // Inst #1620 = FLOG2_W |
| { 1619, 2, 1, 4, 604, 0, 0, 0, 0x6ULL, nullptr, OperandInfo76 }, // Inst #1619 = FLOG2_D |
| { 1618, 2, 1, 4, 544, 0, 0, 0, 0x6ULL, nullptr, OperandInfo261 }, // Inst #1618 = FILL_W |
| { 1617, 2, 1, 4, 544, 0, 0, 0, 0x6ULL, nullptr, OperandInfo260 }, // Inst #1617 = FILL_H |
| { 1616, 2, 1, 4, 544, 0, 0, 0, 0x6ULL, nullptr, OperandInfo259 }, // Inst #1616 = FILL_D |
| { 1615, 2, 1, 4, 544, 0, 0, 0, 0x6ULL, nullptr, OperandInfo258 }, // Inst #1615 = FILL_B |
| { 1614, 2, 1, 4, 591, 0, 0, 0, 0x6ULL, nullptr, OperandInfo257 }, // Inst #1614 = FFQR_W |
| { 1613, 2, 1, 4, 591, 0, 0, 0, 0x6ULL, nullptr, OperandInfo256 }, // Inst #1613 = FFQR_D |
| { 1612, 2, 1, 4, 590, 0, 0, 0, 0x6ULL, nullptr, OperandInfo257 }, // Inst #1612 = FFQL_W |
| { 1611, 2, 1, 4, 590, 0, 0, 0, 0x6ULL, nullptr, OperandInfo256 }, // Inst #1611 = FFQL_D |
| { 1610, 2, 1, 4, 589, 0, 0, 0, 0x6ULL, nullptr, OperandInfo77 }, // Inst #1610 = FFINT_U_W |
| { 1609, 2, 1, 4, 589, 0, 0, 0, 0x6ULL, nullptr, OperandInfo76 }, // Inst #1609 = FFINT_U_D |
| { 1608, 2, 1, 4, 589, 0, 0, 0, 0x6ULL, nullptr, OperandInfo77 }, // Inst #1608 = FFINT_S_W |
| { 1607, 2, 1, 4, 589, 0, 0, 0, 0x6ULL, nullptr, OperandInfo76 }, // Inst #1607 = FFINT_S_D |
| { 1606, 2, 1, 4, 598, 0, 0, 0, 0x6ULL, nullptr, OperandInfo257 }, // Inst #1606 = FEXUPR_W |
| { 1605, 2, 1, 4, 598, 0, 0, 0, 0x6ULL, nullptr, OperandInfo256 }, // Inst #1605 = FEXUPR_D |
| { 1604, 2, 1, 4, 597, 0, 0, 0, 0x6ULL, nullptr, OperandInfo257 }, // Inst #1604 = FEXUPL_W |
| { 1603, 2, 1, 4, 597, 0, 0, 0, 0x6ULL, nullptr, OperandInfo256 }, // Inst #1603 = FEXUPL_D |
| { 1602, 3, 1, 4, 553, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1602 = FEXP2_W |
| { 1601, 3, 1, 4, 553, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1601 = FEXP2_D |
| { 1600, 3, 1, 4, 596, 0, 0, 0, 0x6ULL, nullptr, OperandInfo255 }, // Inst #1600 = FEXDO_W |
| { 1599, 3, 1, 4, 596, 0, 0, 0, 0x6ULL, nullptr, OperandInfo254 }, // Inst #1599 = FEXDO_H |
| { 1598, 3, 1, 4, 658, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1598 = FDIV_W |
| { 1597, 3, 1, 4, 1337, 0, 0, 0, 0x6ULL, nullptr, OperandInfo250 }, // Inst #1597 = FDIV_S_MMR6 |
| { 1596, 3, 1, 4, 1284, 0, 0, 0, 0x4ULL, nullptr, OperandInfo250 }, // Inst #1596 = FDIV_S_MM |
| { 1595, 3, 1, 4, 646, 0, 0, 0, 0x4ULL, nullptr, OperandInfo250 }, // Inst #1595 = FDIV_S |
| { 1594, 3, 1, 4, 1285, 0, 0, 0, 0x4ULL, nullptr, OperandInfo173 }, // Inst #1594 = FDIV_D64_MM |
| { 1593, 3, 1, 4, 647, 0, 0, 0, 0x4ULL, nullptr, OperandInfo173 }, // Inst #1593 = FDIV_D64 |
| { 1592, 3, 1, 4, 1285, 0, 0, 0, 0x4ULL, nullptr, OperandInfo249 }, // Inst #1592 = FDIV_D32_MM |
| { 1591, 3, 1, 4, 647, 0, 0, 0, 0x4ULL, nullptr, OperandInfo249 }, // Inst #1591 = FDIV_D32 |
| { 1590, 3, 1, 4, 659, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1590 = FDIV_D |
| { 1589, 3, 1, 4, 587, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo48 }, // Inst #1589 = FCUN_W |
| { 1588, 3, 1, 4, 587, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo46 }, // Inst #1588 = FCUN_D |
| { 1587, 3, 1, 4, 586, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo48 }, // Inst #1587 = FCUNE_W |
| { 1586, 3, 1, 4, 586, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo46 }, // Inst #1586 = FCUNE_D |
| { 1585, 3, 1, 4, 585, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo48 }, // Inst #1585 = FCULT_W |
| { 1584, 3, 1, 4, 585, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo46 }, // Inst #1584 = FCULT_D |
| { 1583, 3, 1, 4, 584, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo48 }, // Inst #1583 = FCULE_W |
| { 1582, 3, 1, 4, 584, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo46 }, // Inst #1582 = FCULE_D |
| { 1581, 3, 1, 4, 583, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo48 }, // Inst #1581 = FCUEQ_W |
| { 1580, 3, 1, 4, 583, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo46 }, // Inst #1580 = FCUEQ_D |
| { 1579, 3, 1, 4, 582, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo48 }, // Inst #1579 = FCOR_W |
| { 1578, 3, 1, 4, 582, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo46 }, // Inst #1578 = FCOR_D |
| { 1577, 3, 1, 4, 581, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo48 }, // Inst #1577 = FCNE_W |
| { 1576, 3, 1, 4, 581, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo46 }, // Inst #1576 = FCNE_D |
| { 1575, 3, 0, 4, 1265, 0, 1, 0, 0x44ULL, ImplicitList18, OperandInfo253 }, // Inst #1575 = FCMP_S32_MM |
| { 1574, 3, 0, 4, 643, 0, 1, 0, 0x44ULL, ImplicitList18, OperandInfo253 }, // Inst #1574 = FCMP_S32 |
| { 1573, 3, 0, 4, 642, 0, 1, 0, 0x44ULL, ImplicitList18, OperandInfo252 }, // Inst #1573 = FCMP_D64 |
| { 1572, 3, 0, 4, 1266, 0, 1, 0, 0x44ULL, ImplicitList18, OperandInfo251 }, // Inst #1572 = FCMP_D32_MM |
| { 1571, 3, 0, 4, 642, 0, 1, 0, 0x44ULL, ImplicitList18, OperandInfo251 }, // Inst #1571 = FCMP_D32 |
| { 1570, 3, 1, 4, 580, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1570 = FCLT_W |
| { 1569, 3, 1, 4, 580, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1569 = FCLT_D |
| { 1568, 3, 1, 4, 579, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1568 = FCLE_W |
| { 1567, 3, 1, 4, 579, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1567 = FCLE_D |
| { 1566, 2, 1, 4, 599, 0, 0, 0, 0x6ULL, nullptr, OperandInfo77 }, // Inst #1566 = FCLASS_W |
| { 1565, 2, 1, 4, 599, 0, 0, 0, 0x6ULL, nullptr, OperandInfo76 }, // Inst #1565 = FCLASS_D |
| { 1564, 3, 1, 4, 578, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo48 }, // Inst #1564 = FCEQ_W |
| { 1563, 3, 1, 4, 578, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo46 }, // Inst #1563 = FCEQ_D |
| { 1562, 3, 1, 4, 577, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo48 }, // Inst #1562 = FCAF_W |
| { 1561, 3, 1, 4, 577, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo46 }, // Inst #1561 = FCAF_D |
| { 1560, 3, 1, 4, 663, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo48 }, // Inst #1560 = FADD_W |
| { 1559, 3, 1, 4, 1315, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo250 }, // Inst #1559 = FADD_S_MMR6 |
| { 1558, 3, 1, 4, 1275, 0, 0, 0|(1ULL<<MCID::Commutable), 0x4ULL, nullptr, OperandInfo250 }, // Inst #1558 = FADD_S_MM |
| { 1557, 3, 1, 4, 630, 0, 0, 0|(1ULL<<MCID::Commutable), 0x4ULL, nullptr, OperandInfo250 }, // Inst #1557 = FADD_S |
| { 1556, 3, 1, 4, 629, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo173 }, // Inst #1556 = FADD_PS64 |
| { 1555, 3, 1, 4, 1274, 0, 0, 0|(1ULL<<MCID::Commutable), 0x4ULL, nullptr, OperandInfo173 }, // Inst #1555 = FADD_D64_MM |
| { 1554, 3, 1, 4, 628, 0, 0, 0|(1ULL<<MCID::Commutable), 0x4ULL, nullptr, OperandInfo173 }, // Inst #1554 = FADD_D64 |
| { 1553, 3, 1, 4, 1274, 0, 0, 0|(1ULL<<MCID::Commutable), 0x4ULL, nullptr, OperandInfo249 }, // Inst #1553 = FADD_D32_MM |
| { 1552, 3, 1, 4, 628, 0, 0, 0|(1ULL<<MCID::Commutable), 0x4ULL, nullptr, OperandInfo249 }, // Inst #1552 = FADD_D32 |
| { 1551, 3, 1, 4, 663, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo46 }, // Inst #1551 = FADD_D |
| { 1550, 2, 1, 4, 1272, 0, 0, 0, 0x4ULL, nullptr, OperandInfo207 }, // Inst #1550 = FABS_S_MM |
| { 1549, 2, 1, 4, 530, 0, 0, 0, 0x4ULL, nullptr, OperandInfo207 }, // Inst #1549 = FABS_S |
| { 1548, 2, 1, 4, 1271, 0, 0, 0, 0x4ULL, nullptr, OperandInfo203 }, // Inst #1548 = FABS_D64_MM |
| { 1547, 2, 1, 4, 530, 0, 0, 0, 0x4ULL, nullptr, OperandInfo203 }, // Inst #1547 = FABS_D64 |
| { 1546, 2, 1, 4, 1271, 0, 0, 0, 0x4ULL, nullptr, OperandInfo248 }, // Inst #1546 = FABS_D32_MM |
| { 1545, 2, 1, 4, 530, 0, 0, 0, 0x4ULL, nullptr, OperandInfo248 }, // Inst #1545 = FABS_D32 |
| { 1544, 4, 1, 4, 787, 0, 0, 0, 0x1ULL, nullptr, OperandInfo213 }, // Inst #1544 = EXT_MMR6 |
| { 1543, 4, 1, 4, 746, 0, 0, 0, 0x1ULL, nullptr, OperandInfo213 }, // Inst #1543 = EXT_MM |
| { 1542, 4, 1, 4, 1204, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, OperandInfo211 }, // Inst #1542 = EXTS32 |
| { 1541, 4, 1, 4, 1204, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, OperandInfo211 }, // Inst #1541 = EXTS |
| { 1540, 3, 1, 4, 1547, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList17, OperandInfo246 }, // Inst #1540 = EXTR_W_MM |
| { 1539, 3, 1, 4, 1352, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList17, OperandInfo246 }, // Inst #1539 = EXTR_W |
| { 1538, 3, 1, 4, 1546, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList17, OperandInfo246 }, // Inst #1538 = EXTR_S_H_MM |
| { 1537, 3, 1, 4, 1351, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList17, OperandInfo246 }, // Inst #1537 = EXTR_S_H |
| { 1536, 3, 1, 4, 1545, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList17, OperandInfo246 }, // Inst #1536 = EXTR_R_W_MM |
| { 1535, 3, 1, 4, 1350, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList17, OperandInfo246 }, // Inst #1535 = EXTR_R_W |
| { 1534, 3, 1, 4, 1544, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList17, OperandInfo246 }, // Inst #1534 = EXTR_RS_W_MM |
| { 1533, 3, 1, 4, 1349, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList17, OperandInfo246 }, // Inst #1533 = EXTR_RS_W |
| { 1532, 3, 1, 4, 1543, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList17, OperandInfo247 }, // Inst #1532 = EXTRV_W_MM |
| { 1531, 3, 1, 4, 1348, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList17, OperandInfo247 }, // Inst #1531 = EXTRV_W |
| { 1530, 3, 1, 4, 1542, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList17, OperandInfo247 }, // Inst #1530 = EXTRV_S_H_MM |
| { 1529, 3, 1, 4, 1347, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList17, OperandInfo247 }, // Inst #1529 = EXTRV_S_H |
| { 1528, 3, 1, 4, 1541, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList17, OperandInfo247 }, // Inst #1528 = EXTRV_R_W_MM |
| { 1527, 3, 1, 4, 1346, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList17, OperandInfo247 }, // Inst #1527 = EXTRV_R_W |
| { 1526, 3, 1, 4, 1540, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList17, OperandInfo247 }, // Inst #1526 = EXTRV_RS_W_MM |
| { 1525, 3, 1, 4, 1345, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList17, OperandInfo247 }, // Inst #1525 = EXTRV_RS_W |
| { 1524, 3, 1, 4, 1539, 1, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList15, OperandInfo246 }, // Inst #1524 = EXTP_MM |
| { 1523, 3, 1, 4, 1538, 1, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList15, OperandInfo247 }, // Inst #1523 = EXTPV_MM |
| { 1522, 3, 1, 4, 1387, 1, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList15, OperandInfo247 }, // Inst #1522 = EXTPV |
| { 1521, 3, 1, 4, 1537, 1, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList16, OperandInfo246 }, // Inst #1521 = EXTPDP_MM |
| { 1520, 3, 1, 4, 1536, 1, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList16, OperandInfo247 }, // Inst #1520 = EXTPDPV_MM |
| { 1519, 3, 1, 4, 1385, 1, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList16, OperandInfo247 }, // Inst #1519 = EXTPDPV |
| { 1518, 3, 1, 4, 1386, 1, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList16, OperandInfo246 }, // Inst #1518 = EXTPDP |
| { 1517, 3, 1, 4, 1388, 1, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList15, OperandInfo246 }, // Inst #1517 = EXTP |
| { 1516, 4, 1, 4, 494, 0, 0, 0, 0x1ULL, nullptr, OperandInfo213 }, // Inst #1516 = EXT |
| { 1515, 1, 1, 4, 1046, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo58 }, // Inst #1515 = EVP_MMR6 |
| { 1514, 1, 1, 4, 1062, 0, 0, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo58 }, // Inst #1514 = EVPE |
| { 1513, 1, 1, 4, 1025, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo58 }, // Inst #1513 = EVP |
| { 1512, 0, 0, 4, 991, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr }, // Inst #1512 = ERET_MMR6 |
| { 1511, 0, 0, 4, 953, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr }, // Inst #1511 = ERET_MM |
| { 1510, 0, 0, 4, 989, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr }, // Inst #1510 = ERETNC_MMR6 |
| { 1509, 0, 0, 4, 383, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr }, // Inst #1509 = ERETNC |
| { 1508, 0, 0, 4, 381, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr }, // Inst #1508 = ERET |
| { 1507, 1, 1, 4, 1061, 0, 0, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo58 }, // Inst #1507 = EMT |
| { 1506, 1, 1, 4, 1049, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo58 }, // Inst #1506 = EI_MMR6 |
| { 1505, 1, 1, 4, 1032, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo58 }, // Inst #1505 = EI_MM |
| { 1504, 1, 1, 4, 477, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo58 }, // Inst #1504 = EI |
| { 1503, 0, 0, 4, 1050, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr }, // Inst #1503 = EHB_MMR6 |
| { 1502, 0, 0, 4, 1033, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr }, // Inst #1502 = EHB_MM |
| { 1501, 0, 0, 4, 479, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr }, // Inst #1501 = EHB |
| { 1500, 2, 0, 2, 877, 0, 2, 0, 0x0ULL, ImplicitList6, OperandInfo130 }, // Inst #1500 = DivuRxRy16 |
| { 1499, 2, 0, 2, 876, 0, 2, 0, 0x0ULL, ImplicitList6, OperandInfo130 }, // Inst #1499 = DivRxRy16 |
| { 1498, 1, 1, 4, 1047, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo58 }, // Inst #1498 = DVP_MMR6 |
| { 1497, 1, 1, 4, 1060, 0, 0, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo58 }, // Inst #1497 = DVPE |
| { 1496, 1, 1, 4, 1026, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo58 }, // Inst #1496 = DVP |
| { 1495, 2, 0, 4, 905, 0, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList13, OperandInfo122 }, // Inst #1495 = DUDIV |
| { 1494, 3, 1, 4, 839, 0, 0, 0|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, OperandInfo71 }, // Inst #1494 = DSUBu |
| { 1493, 3, 1, 4, 838, 0, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, OperandInfo71 }, // Inst #1493 = DSUB |
| { 1492, 3, 1, 4, 837, 0, 0, 0, 0x1ULL, nullptr, OperandInfo244 }, // Inst #1492 = DSRLV |
| { 1491, 3, 1, 4, 836, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, OperandInfo70 }, // Inst #1491 = DSRL32 |
| { 1490, 3, 1, 4, 835, 0, 0, 0, 0x1ULL, nullptr, OperandInfo70 }, // Inst #1490 = DSRL |
| { 1489, 3, 1, 4, 834, 0, 0, 0, 0x1ULL, nullptr, OperandInfo244 }, // Inst #1489 = DSRAV |
| { 1488, 3, 1, 4, 833, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, OperandInfo70 }, // Inst #1488 = DSRA32 |
| { 1487, 3, 1, 4, 832, 0, 0, 0, 0x1ULL, nullptr, OperandInfo70 }, // Inst #1487 = DSRA |
| { 1486, 3, 1, 4, 831, 0, 0, 0, 0x1ULL, nullptr, OperandInfo244 }, // Inst #1486 = DSLLV |
| { 1485, 2, 1, 4, 808, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, OperandInfo245 }, // Inst #1485 = DSLL64_32 |
| { 1484, 3, 1, 4, 830, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, OperandInfo70 }, // Inst #1484 = DSLL32 |
| { 1483, 3, 1, 4, 829, 0, 0, 0, 0x1ULL, nullptr, OperandInfo70 }, // Inst #1483 = DSLL |
| { 1482, 2, 1, 4, 828, 0, 0, 0, 0x1ULL, nullptr, OperandInfo122 }, // Inst #1482 = DSHD |
| { 1481, 2, 0, 4, 904, 0, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList13, OperandInfo122 }, // Inst #1481 = DSDIV |
| { 1480, 2, 1, 4, 827, 0, 0, 0, 0x1ULL, nullptr, OperandInfo122 }, // Inst #1480 = DSBH |
| { 1479, 3, 1, 4, 826, 0, 0, 0, 0x1ULL, nullptr, OperandInfo244 }, // Inst #1479 = DROTRV |
| { 1478, 3, 1, 4, 825, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, OperandInfo70 }, // Inst #1478 = DROTR32 |
| { 1477, 3, 1, 4, 824, 0, 0, 0, 0x1ULL, nullptr, OperandInfo70 }, // Inst #1477 = DROTR |
| { 1476, 4, 1, 4, 1642, 0, 0, 0, 0x6ULL, nullptr, OperandInfo243 }, // Inst #1476 = DPS_W_PH_MMR2 |
| { 1475, 4, 1, 4, 1478, 0, 0, 0, 0x6ULL, nullptr, OperandInfo243 }, // Inst #1475 = DPS_W_PH |
| { 1474, 4, 1, 4, 1645, 0, 0, 0, 0x6ULL, nullptr, OperandInfo243 }, // Inst #1474 = DPSX_W_PH_MMR2 |
| { 1473, 4, 1, 4, 1481, 0, 0, 0, 0x6ULL, nullptr, OperandInfo243 }, // Inst #1473 = DPSX_W_PH |
| { 1472, 4, 1, 4, 1535, 0, 0, 0, 0x6ULL, nullptr, OperandInfo243 }, // Inst #1472 = DPSU_H_QBR_MM |
| { 1471, 4, 1, 4, 1384, 0, 0, 0, 0x6ULL, nullptr, OperandInfo243 }, // Inst #1471 = DPSU_H_QBR |
| { 1470, 4, 1, 4, 1534, 0, 0, 0, 0x6ULL, nullptr, OperandInfo243 }, // Inst #1470 = DPSU_H_QBL_MM |
| { 1469, 4, 1, 4, 1383, 0, 0, 0, 0x6ULL, nullptr, OperandInfo243 }, // Inst #1469 = DPSU_H_QBL |
| { 1468, 4, 1, 4, 666, 0, 0, 0, 0x6ULL, nullptr, OperandInfo242 }, // Inst #1468 = DPSUB_U_W |
| { 1467, 4, 1, 4, 666, 0, 0, 0, 0x6ULL, nullptr, OperandInfo241 }, // Inst #1467 = DPSUB_U_H |
| { 1466, 4, 1, 4, 666, 0, 0, 0, 0x6ULL, nullptr, OperandInfo240 }, // Inst #1466 = DPSUB_U_D |
| { 1465, 4, 1, 4, 666, 0, 0, 0, 0x6ULL, nullptr, OperandInfo242 }, // Inst #1465 = DPSUB_S_W |
| { 1464, 4, 1, 4, 666, 0, 0, 0, 0x6ULL, nullptr, OperandInfo241 }, // Inst #1464 = DPSUB_S_H |
| { 1463, 4, 1, 4, 666, 0, 0, 0, 0x6ULL, nullptr, OperandInfo240 }, // Inst #1463 = DPSUB_S_D |
| { 1462, 4, 1, 4, 1533, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList14, OperandInfo243 }, // Inst #1462 = DPSQ_S_W_PH_MM |
| { 1461, 4, 1, 4, 1382, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList14, OperandInfo243 }, // Inst #1461 = DPSQ_S_W_PH |
| { 1460, 4, 1, 4, 1532, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList14, OperandInfo243 }, // Inst #1460 = DPSQ_SA_L_W_MM |
| { 1459, 4, 1, 4, 1381, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList14, OperandInfo243 }, // Inst #1459 = DPSQ_SA_L_W |
| { 1458, 4, 1, 4, 1643, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList14, OperandInfo243 }, // Inst #1458 = DPSQX_S_W_PH_MMR2 |
| { 1457, 4, 1, 4, 1479, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList14, OperandInfo243 }, // Inst #1457 = DPSQX_S_W_PH |
| { 1456, 4, 1, 4, 1644, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList14, OperandInfo243 }, // Inst #1456 = DPSQX_SA_W_PH_MMR2 |
| { 1455, 4, 1, 4, 1480, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList14, OperandInfo243 }, // Inst #1455 = DPSQX_SA_W_PH |
| { 1454, 2, 1, 4, 1203, 0, 0, 0, 0x1ULL, nullptr, OperandInfo122 }, // Inst #1454 = DPOP |
| { 1453, 4, 1, 4, 1638, 0, 0, 0, 0x6ULL, nullptr, OperandInfo243 }, // Inst #1453 = DPA_W_PH_MMR2 |
| { 1452, 4, 1, 4, 1474, 0, 0, 0, 0x6ULL, nullptr, OperandInfo243 }, // Inst #1452 = DPA_W_PH |
| { 1451, 4, 1, 4, 1641, 0, 0, 0, 0x6ULL, nullptr, OperandInfo243 }, // Inst #1451 = DPAX_W_PH_MMR2 |
| { 1450, 4, 1, 4, 1477, 0, 0, 0, 0x6ULL, nullptr, OperandInfo243 }, // Inst #1450 = DPAX_W_PH |
| { 1449, 4, 1, 4, 1531, 0, 0, 0, 0x6ULL, nullptr, OperandInfo243 }, // Inst #1449 = DPAU_H_QBR_MM |
| { 1448, 4, 1, 4, 1380, 0, 0, 0, 0x6ULL, nullptr, OperandInfo243 }, // Inst #1448 = DPAU_H_QBR |
| { 1447, 4, 1, 4, 1530, 0, 0, 0, 0x6ULL, nullptr, OperandInfo243 }, // Inst #1447 = DPAU_H_QBL_MM |
| { 1446, 4, 1, 4, 1379, 0, 0, 0, 0x6ULL, nullptr, OperandInfo243 }, // Inst #1446 = DPAU_H_QBL |
| { 1445, 4, 1, 4, 1529, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList14, OperandInfo243 }, // Inst #1445 = DPAQ_S_W_PH_MM |
| { 1444, 4, 1, 4, 1378, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList14, OperandInfo243 }, // Inst #1444 = DPAQ_S_W_PH |
| { 1443, 4, 1, 4, 1528, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList14, OperandInfo243 }, // Inst #1443 = DPAQ_SA_L_W_MM |
| { 1442, 4, 1, 4, 1377, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList14, OperandInfo243 }, // Inst #1442 = DPAQ_SA_L_W |
| { 1441, 4, 1, 4, 1640, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList14, OperandInfo243 }, // Inst #1441 = DPAQX_S_W_PH_MMR2 |
| { 1440, 4, 1, 4, 1476, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList14, OperandInfo243 }, // Inst #1440 = DPAQX_S_W_PH |
| { 1439, 4, 1, 4, 1639, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList14, OperandInfo243 }, // Inst #1439 = DPAQX_SA_W_PH_MMR2 |
| { 1438, 4, 1, 4, 1475, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList14, OperandInfo243 }, // Inst #1438 = DPAQX_SA_W_PH |
| { 1437, 4, 1, 4, 665, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo242 }, // Inst #1437 = DPADD_U_W |
| { 1436, 4, 1, 4, 665, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo241 }, // Inst #1436 = DPADD_U_H |
| { 1435, 4, 1, 4, 665, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo240 }, // Inst #1435 = DPADD_U_D |
| { 1434, 4, 1, 4, 665, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo242 }, // Inst #1434 = DPADD_S_W |
| { 1433, 4, 1, 4, 665, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo241 }, // Inst #1433 = DPADD_S_H |
| { 1432, 4, 1, 4, 665, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo240 }, // Inst #1432 = DPADD_S_D |
| { 1431, 3, 1, 4, 667, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo239 }, // Inst #1431 = DOTP_U_W |
| { 1430, 3, 1, 4, 667, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo238 }, // Inst #1430 = DOTP_U_H |
| { 1429, 3, 1, 4, 667, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo237 }, // Inst #1429 = DOTP_U_D |
| { 1428, 3, 1, 4, 667, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo239 }, // Inst #1428 = DOTP_S_W |
| { 1427, 3, 1, 4, 667, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo238 }, // Inst #1427 = DOTP_S_H |
| { 1426, 3, 1, 4, 667, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo237 }, // Inst #1426 = DOTP_S_D |
| { 1425, 3, 1, 4, 914, 0, 0, 0, 0x6ULL, nullptr, OperandInfo71 }, // Inst #1425 = DMUL_R6 |
| { 1424, 3, 1, 4, 901, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo71 }, // Inst #1424 = DMULU |
| { 1423, 2, 0, 4, 903, 0, 2, 0|(1ULL<<MCID::Commutable), 0x1ULL, ImplicitList13, OperandInfo122 }, // Inst #1423 = DMULTu |
| { 1422, 2, 0, 4, 902, 0, 2, 0|(1ULL<<MCID::Commutable), 0x1ULL, ImplicitList13, OperandInfo122 }, // Inst #1422 = DMULT |
| { 1421, 3, 1, 4, 1209, 0, 5, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, ImplicitList12, OperandInfo71 }, // Inst #1421 = DMUL |
| { 1420, 3, 1, 4, 913, 0, 0, 0, 0x6ULL, nullptr, OperandInfo71 }, // Inst #1420 = DMUHU |
| { 1419, 3, 1, 4, 912, 0, 0, 0, 0x6ULL, nullptr, OperandInfo71 }, // Inst #1419 = DMUH |
| { 1418, 3, 1, 4, 1068, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo235 }, // Inst #1418 = DMTGC0 |
| { 1417, 2, 2, 4, 1202, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo112 }, // Inst #1417 = DMTC2_OCTEON |
| { 1416, 3, 1, 4, 1056, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo236 }, // Inst #1416 = DMTC2 |
| { 1415, 2, 1, 4, 1341, 0, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast), 0x4ULL, nullptr, OperandInfo134 }, // Inst #1415 = DMTC1 |
| { 1414, 3, 1, 4, 1054, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo235 }, // Inst #1414 = DMTC0 |
| { 1413, 1, 1, 4, 1059, 0, 0, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo58 }, // Inst #1413 = DMT |
| { 1412, 3, 1, 4, 918, 0, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL, nullptr, OperandInfo71 }, // Inst #1412 = DMODU |
| { 1411, 3, 1, 4, 916, 0, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL, nullptr, OperandInfo71 }, // Inst #1411 = DMOD |
| { 1410, 3, 1, 4, 1067, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo232 }, // Inst #1410 = DMFGC0 |
| { 1409, 2, 2, 4, 1201, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo112 }, // Inst #1409 = DMFC2_OCTEON |
| { 1408, 3, 1, 4, 1055, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo234 }, // Inst #1408 = DMFC2 |
| { 1407, 2, 1, 4, 1340, 0, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast), 0x4ULL, nullptr, OperandInfo233 }, // Inst #1407 = DMFC1 |
| { 1406, 3, 1, 4, 1053, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo232 }, // Inst #1406 = DMFC0 |
| { 1405, 4, 1, 4, 851, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo230 }, // Inst #1405 = DLSA_R6 |
| { 1404, 4, 1, 4, 851, 0, 0, 0, 0x6ULL, nullptr, OperandInfo230 }, // Inst #1404 = DLSA |
| { 1403, 1, 1, 4, 1048, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo58 }, // Inst #1403 = DI_MMR6 |
| { 1402, 1, 1, 4, 1031, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo58 }, // Inst #1402 = DI_MM |
| { 1401, 3, 1, 4, 614, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1401 = DIV_U_W |
| { 1400, 3, 1, 4, 614, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #1400 = DIV_U_H |
| { 1399, 3, 1, 4, 614, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1399 = DIV_U_D |
| { 1398, 3, 1, 4, 614, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #1398 = DIV_U_B |
| { 1397, 3, 1, 4, 614, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1397 = DIV_S_W |
| { 1396, 3, 1, 4, 614, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #1396 = DIV_S_H |
| { 1395, 3, 1, 4, 614, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1395 = DIV_S_D |
| { 1394, 3, 1, 4, 614, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #1394 = DIV_S_B |
| { 1393, 3, 1, 4, 899, 0, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UsesCustomInserter), 0x6ULL, nullptr, OperandInfo72 }, // Inst #1393 = DIV_MMR6 |
| { 1392, 3, 1, 4, 898, 0, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UsesCustomInserter), 0x6ULL, nullptr, OperandInfo72 }, // Inst #1392 = DIVU_MMR6 |
| { 1391, 3, 1, 4, 485, 0, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL, nullptr, OperandInfo72 }, // Inst #1391 = DIVU |
| { 1390, 3, 1, 4, 484, 0, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL, nullptr, OperandInfo72 }, // Inst #1390 = DIV |
| { 1389, 5, 1, 4, 823, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, OperandInfo231 }, // Inst #1389 = DINSU |
| { 1388, 5, 1, 4, 823, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, OperandInfo231 }, // Inst #1388 = DINSM |
| { 1387, 5, 1, 4, 823, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, OperandInfo231 }, // Inst #1387 = DINS |
| { 1386, 1, 1, 4, 476, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo58 }, // Inst #1386 = DI |
| { 1385, 4, 1, 4, 822, 0, 0, 0, 0x1ULL, nullptr, OperandInfo211 }, // Inst #1385 = DEXTU |
| { 1384, 4, 1, 4, 822, 0, 0, 0, 0x1ULL, nullptr, OperandInfo211 }, // Inst #1384 = DEXTM |
| { 1383, 4, 1, 4, 807, 0, 0, 0, 0x1ULL, nullptr, OperandInfo212 }, // Inst #1383 = DEXT64_32 |
| { 1382, 4, 1, 4, 822, 0, 0, 0, 0x1ULL, nullptr, OperandInfo211 }, // Inst #1382 = DEXT |
| { 1381, 0, 0, 4, 988, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr }, // Inst #1381 = DERET_MMR6 |
| { 1380, 0, 0, 4, 952, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr }, // Inst #1380 = DERET_MM |
| { 1379, 0, 0, 4, 380, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr }, // Inst #1379 = DERET |
| { 1378, 3, 1, 4, 917, 0, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL, nullptr, OperandInfo71 }, // Inst #1378 = DDIVU |
| { 1377, 3, 1, 4, 915, 0, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL, nullptr, OperandInfo71 }, // Inst #1377 = DDIV |
| { 1376, 2, 1, 4, 849, 0, 0, 0, 0x6ULL, nullptr, OperandInfo122 }, // Inst #1376 = DCLZ_R6 |
| { 1375, 2, 1, 4, 821, 0, 0, 0, 0x1ULL, nullptr, OperandInfo122 }, // Inst #1375 = DCLZ |
| { 1374, 2, 1, 4, 848, 0, 0, 0, 0x6ULL, nullptr, OperandInfo122 }, // Inst #1374 = DCLO_R6 |
| { 1373, 2, 1, 4, 820, 0, 0, 0, 0x1ULL, nullptr, OperandInfo122 }, // Inst #1373 = DCLO |
| { 1372, 2, 1, 4, 850, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo122 }, // Inst #1372 = DBITSWAP |
| { 1371, 3, 1, 4, 847, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo70 }, // Inst #1371 = DAUI |
| { 1370, 3, 1, 4, 846, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo229 }, // Inst #1370 = DATI |
| { 1369, 4, 1, 4, 844, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo230 }, // Inst #1369 = DALIGN |
| { 1368, 3, 1, 4, 845, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo229 }, // Inst #1368 = DAHI |
| { 1367, 3, 1, 4, 819, 0, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, OperandInfo71 }, // Inst #1367 = DADDu |
| { 1366, 3, 1, 4, 818, 0, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2ULL, nullptr, OperandInfo70 }, // Inst #1366 = DADDiu |
| { 1365, 3, 1, 4, 817, 0, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo70 }, // Inst #1365 = DADDi |
| { 1364, 3, 1, 4, 816, 0, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, OperandInfo71 }, // Inst #1364 = DADD |
| { 1363, 2, 0, 4, 735, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList7, OperandInfo183 }, // Inst #1363 = CmpiRxImmX16 |
| { 1362, 2, 0, 2, 735, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList7, OperandInfo183 }, // Inst #1362 = CmpiRxImm16 |
| { 1361, 2, 0, 2, 735, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList7, OperandInfo130 }, // Inst #1361 = CmpRxRy16 |
| { 1360, 3, 1, 4, 1260, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo228 }, // Inst #1360 = C_UN_S_MM |
| { 1359, 3, 1, 4, 641, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo228 }, // Inst #1359 = C_UN_S |
| { 1358, 3, 1, 4, 1259, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo227 }, // Inst #1358 = C_UN_D64_MM |
| { 1357, 3, 1, 4, 640, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo227 }, // Inst #1357 = C_UN_D64 |
| { 1356, 3, 1, 4, 1259, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo226 }, // Inst #1356 = C_UN_D32_MM |
| { 1355, 3, 1, 4, 640, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo226 }, // Inst #1355 = C_UN_D32 |
| { 1354, 3, 1, 4, 1262, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo228 }, // Inst #1354 = C_ULT_S_MM |
| { 1353, 3, 1, 4, 641, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo228 }, // Inst #1353 = C_ULT_S |
| { 1352, 3, 1, 4, 1261, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo227 }, // Inst #1352 = C_ULT_D64_MM |
| { 1351, 3, 1, 4, 640, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo227 }, // Inst #1351 = C_ULT_D64 |
| { 1350, 3, 1, 4, 1261, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo226 }, // Inst #1350 = C_ULT_D32_MM |
| { 1349, 3, 1, 4, 640, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo226 }, // Inst #1349 = C_ULT_D32 |
| { 1348, 3, 1, 4, 1262, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo228 }, // Inst #1348 = C_ULE_S_MM |
| { 1347, 3, 1, 4, 641, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo228 }, // Inst #1347 = C_ULE_S |
| { 1346, 3, 1, 4, 1261, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo227 }, // Inst #1346 = C_ULE_D64_MM |
| { 1345, 3, 1, 4, 640, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo227 }, // Inst #1345 = C_ULE_D64 |
| { 1344, 3, 1, 4, 1261, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo226 }, // Inst #1344 = C_ULE_D32_MM |
| { 1343, 3, 1, 4, 640, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo226 }, // Inst #1343 = C_ULE_D32 |
| { 1342, 3, 1, 4, 1262, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo228 }, // Inst #1342 = C_UEQ_S_MM |
| { 1341, 3, 1, 4, 641, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo228 }, // Inst #1341 = C_UEQ_S |
| { 1340, 3, 1, 4, 1261, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo227 }, // Inst #1340 = C_UEQ_D64_MM |
| { 1339, 3, 1, 4, 640, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo227 }, // Inst #1339 = C_UEQ_D64 |
| { 1338, 3, 1, 4, 1261, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo226 }, // Inst #1338 = C_UEQ_D32_MM |
| { 1337, 3, 1, 4, 640, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo226 }, // Inst #1337 = C_UEQ_D32 |
| { 1336, 3, 1, 4, 1260, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo228 }, // Inst #1336 = C_SF_S_MM |
| { 1335, 3, 1, 4, 641, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo228 }, // Inst #1335 = C_SF_S |
| { 1334, 3, 1, 4, 1259, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo227 }, // Inst #1334 = C_SF_D64_MM |
| { 1333, 3, 1, 4, 640, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo227 }, // Inst #1333 = C_SF_D64 |
| { 1332, 3, 1, 4, 1259, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo226 }, // Inst #1332 = C_SF_D32_MM |
| { 1331, 3, 1, 4, 640, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo226 }, // Inst #1331 = C_SF_D32 |
| { 1330, 3, 1, 4, 1262, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo228 }, // Inst #1330 = C_SEQ_S_MM |
| { 1329, 3, 1, 4, 641, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo228 }, // Inst #1329 = C_SEQ_S |
| { 1328, 3, 1, 4, 1261, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo227 }, // Inst #1328 = C_SEQ_D64_MM |
| { 1327, 3, 1, 4, 640, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo227 }, // Inst #1327 = C_SEQ_D64 |
| { 1326, 3, 1, 4, 1261, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo226 }, // Inst #1326 = C_SEQ_D32_MM |
| { 1325, 3, 1, 4, 640, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo226 }, // Inst #1325 = C_SEQ_D32 |
| { 1324, 3, 1, 4, 1262, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo228 }, // Inst #1324 = C_OLT_S_MM |
| { 1323, 3, 1, 4, 641, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo228 }, // Inst #1323 = C_OLT_S |
| { 1322, 3, 1, 4, 1261, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo227 }, // Inst #1322 = C_OLT_D64_MM |
| { 1321, 3, 1, 4, 640, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo227 }, // Inst #1321 = C_OLT_D64 |
| { 1320, 3, 1, 4, 1261, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo226 }, // Inst #1320 = C_OLT_D32_MM |
| { 1319, 3, 1, 4, 640, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo226 }, // Inst #1319 = C_OLT_D32 |
| { 1318, 3, 1, 4, 1262, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo228 }, // Inst #1318 = C_OLE_S_MM |
| { 1317, 3, 1, 4, 641, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo228 }, // Inst #1317 = C_OLE_S |
| { 1316, 3, 1, 4, 1261, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo227 }, // Inst #1316 = C_OLE_D64_MM |
| { 1315, 3, 1, 4, 640, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo227 }, // Inst #1315 = C_OLE_D64 |
| { 1314, 3, 1, 4, 1261, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo226 }, // Inst #1314 = C_OLE_D32_MM |
| { 1313, 3, 1, 4, 640, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo226 }, // Inst #1313 = C_OLE_D32 |
| { 1312, 3, 1, 4, 1262, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo228 }, // Inst #1312 = C_NGT_S_MM |
| { 1311, 3, 1, 4, 641, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo228 }, // Inst #1311 = C_NGT_S |
| { 1310, 3, 1, 4, 1261, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo227 }, // Inst #1310 = C_NGT_D64_MM |
| { 1309, 3, 1, 4, 640, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo227 }, // Inst #1309 = C_NGT_D64 |
| { 1308, 3, 1, 4, 1261, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo226 }, // Inst #1308 = C_NGT_D32_MM |
| { 1307, 3, 1, 4, 640, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo226 }, // Inst #1307 = C_NGT_D32 |
| { 1306, 3, 1, 4, 1262, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo228 }, // Inst #1306 = C_NGL_S_MM |
| { 1305, 3, 1, 4, 641, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo228 }, // Inst #1305 = C_NGL_S |
| { 1304, 3, 1, 4, 1261, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo227 }, // Inst #1304 = C_NGL_D64_MM |
| { 1303, 3, 1, 4, 640, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo227 }, // Inst #1303 = C_NGL_D64 |
| { 1302, 3, 1, 4, 1261, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo226 }, // Inst #1302 = C_NGL_D32_MM |
| { 1301, 3, 1, 4, 640, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo226 }, // Inst #1301 = C_NGL_D32 |
| { 1300, 3, 1, 4, 1264, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo228 }, // Inst #1300 = C_NGLE_S_MM |
| { 1299, 3, 1, 4, 641, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo228 }, // Inst #1299 = C_NGLE_S |
| { 1298, 3, 1, 4, 1263, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo227 }, // Inst #1298 = C_NGLE_D64_MM |
| { 1297, 3, 1, 4, 640, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo227 }, // Inst #1297 = C_NGLE_D64 |
| { 1296, 3, 1, 4, 1263, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo226 }, // Inst #1296 = C_NGLE_D32_MM |
| { 1295, 3, 1, 4, 640, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo226 }, // Inst #1295 = C_NGLE_D32 |
| { 1294, 3, 1, 4, 1262, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo228 }, // Inst #1294 = C_NGE_S_MM |
| { 1293, 3, 1, 4, 641, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo228 }, // Inst #1293 = C_NGE_S |
| { 1292, 3, 1, 4, 1261, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo227 }, // Inst #1292 = C_NGE_D64_MM |
| { 1291, 3, 1, 4, 640, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo227 }, // Inst #1291 = C_NGE_D64 |
| { 1290, 3, 1, 4, 1261, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo226 }, // Inst #1290 = C_NGE_D32_MM |
| { 1289, 3, 1, 4, 640, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo226 }, // Inst #1289 = C_NGE_D32 |
| { 1288, 3, 1, 4, 1260, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo228 }, // Inst #1288 = C_LT_S_MM |
| { 1287, 3, 1, 4, 641, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo228 }, // Inst #1287 = C_LT_S |
| { 1286, 3, 1, 4, 1259, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo227 }, // Inst #1286 = C_LT_D64_MM |
| { 1285, 3, 1, 4, 640, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo227 }, // Inst #1285 = C_LT_D64 |
| { 1284, 3, 1, 4, 1259, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo226 }, // Inst #1284 = C_LT_D32_MM |
| { 1283, 3, 1, 4, 640, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo226 }, // Inst #1283 = C_LT_D32 |
| { 1282, 3, 1, 4, 1260, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo228 }, // Inst #1282 = C_LE_S_MM |
| { 1281, 3, 1, 4, 641, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo228 }, // Inst #1281 = C_LE_S |
| { 1280, 3, 1, 4, 1259, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo227 }, // Inst #1280 = C_LE_D64_MM |
| { 1279, 3, 1, 4, 640, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo227 }, // Inst #1279 = C_LE_D64 |
| { 1278, 3, 1, 4, 1259, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo226 }, // Inst #1278 = C_LE_D32_MM |
| { 1277, 3, 1, 4, 640, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo226 }, // Inst #1277 = C_LE_D32 |
| { 1276, 3, 1, 4, 1258, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo228 }, // Inst #1276 = C_F_S_MM |
| { 1275, 3, 1, 4, 641, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo228 }, // Inst #1275 = C_F_S |
| { 1274, 3, 1, 4, 1257, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo227 }, // Inst #1274 = C_F_D64_MM |
| { 1273, 3, 1, 4, 640, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo227 }, // Inst #1273 = C_F_D64 |
| { 1272, 3, 1, 4, 1257, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo226 }, // Inst #1272 = C_F_D32_MM |
| { 1271, 3, 1, 4, 640, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo226 }, // Inst #1271 = C_F_D32 |
| { 1270, 3, 1, 4, 1260, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo228 }, // Inst #1270 = C_EQ_S_MM |
| { 1269, 3, 1, 4, 641, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo228 }, // Inst #1269 = C_EQ_S |
| { 1268, 3, 1, 4, 1259, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo227 }, // Inst #1268 = C_EQ_D64_MM |
| { 1267, 3, 1, 4, 640, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo227 }, // Inst #1267 = C_EQ_D64 |
| { 1266, 3, 1, 4, 1259, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo226 }, // Inst #1266 = C_EQ_D32_MM |
| { 1265, 3, 1, 4, 640, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo226 }, // Inst #1265 = C_EQ_D32 |
| { 1264, 2, 1, 4, 1307, 0, 0, 0, 0x4ULL, nullptr, OperandInfo207 }, // Inst #1264 = CVT_W_S_MMR6 |
| { 1263, 2, 1, 4, 1246, 0, 0, 0, 0x4ULL, nullptr, OperandInfo207 }, // Inst #1263 = CVT_W_S_MM |
| { 1262, 2, 1, 4, 638, 0, 0, 0, 0x4ULL, nullptr, OperandInfo207 }, // Inst #1262 = CVT_W_S |
| { 1261, 2, 1, 4, 1246, 0, 0, 0, 0x4ULL, nullptr, OperandInfo206 }, // Inst #1261 = CVT_W_D64_MM |
| { 1260, 2, 1, 4, 638, 0, 0, 0, 0x4ULL, nullptr, OperandInfo206 }, // Inst #1260 = CVT_W_D64 |
| { 1259, 2, 1, 4, 1246, 0, 0, 0, 0x4ULL, nullptr, OperandInfo205 }, // Inst #1259 = CVT_W_D32_MM |
| { 1258, 2, 1, 4, 638, 0, 0, 0, 0x4ULL, nullptr, OperandInfo205 }, // Inst #1258 = CVT_W_D32 |
| { 1257, 2, 1, 4, 1307, 0, 0, 0, 0x4ULL, nullptr, OperandInfo207 }, // Inst #1257 = CVT_S_W_MMR6 |
| { 1256, 2, 1, 4, 1246, 0, 0, 0, 0x4ULL, nullptr, OperandInfo207 }, // Inst #1256 = CVT_S_W_MM |
| { 1255, 2, 1, 4, 638, 0, 0, 0, 0x4ULL, nullptr, OperandInfo207 }, // Inst #1255 = CVT_S_W |
| { 1254, 2, 1, 4, 639, 0, 0, 0, 0x4ULL, nullptr, OperandInfo206 }, // Inst #1254 = CVT_S_PU64 |
| { 1253, 2, 1, 4, 639, 0, 0, 0, 0x4ULL, nullptr, OperandInfo206 }, // Inst #1253 = CVT_S_PL64 |
| { 1252, 2, 1, 4, 1307, 0, 0, 0, 0x4ULL, nullptr, OperandInfo204 }, // Inst #1252 = CVT_S_L_MMR6 |
| { 1251, 2, 1, 4, 638, 0, 0, 0, 0x4ULL, nullptr, OperandInfo206 }, // Inst #1251 = CVT_S_L |
| { 1250, 2, 1, 4, 1246, 0, 0, 0, 0x4ULL, nullptr, OperandInfo206 }, // Inst #1250 = CVT_S_D64_MM |
| { 1249, 2, 1, 4, 638, 0, 0, 0, 0x4ULL, nullptr, OperandInfo206 }, // Inst #1249 = CVT_S_D64 |
| { 1248, 2, 1, 4, 1246, 0, 0, 0, 0x4ULL, nullptr, OperandInfo205 }, // Inst #1248 = CVT_S_D32_MM |
| { 1247, 2, 1, 4, 638, 0, 0, 0, 0x4ULL, nullptr, OperandInfo205 }, // Inst #1247 = CVT_S_D32 |
| { 1246, 2, 1, 4, 1212, 0, 0, 0, 0x4ULL, nullptr, OperandInfo203 }, // Inst #1246 = CVT_PW_PS64 |
| { 1245, 3, 1, 4, 639, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo225 }, // Inst #1245 = CVT_PS_S64 |
| { 1244, 2, 1, 4, 1212, 0, 0, 0, 0x4ULL, nullptr, OperandInfo203 }, // Inst #1244 = CVT_PS_PW64 |
| { 1243, 2, 1, 4, 1307, 0, 0, 0, 0x4ULL, nullptr, OperandInfo204 }, // Inst #1243 = CVT_L_S_MMR6 |
| { 1242, 2, 1, 4, 1246, 0, 0, 0, 0x4ULL, nullptr, OperandInfo204 }, // Inst #1242 = CVT_L_S_MM |
| { 1241, 2, 1, 4, 638, 0, 0, 0, 0x4ULL, nullptr, OperandInfo204 }, // Inst #1241 = CVT_L_S |
| { 1240, 2, 1, 4, 1307, 0, 0, 0, 0x4ULL, nullptr, OperandInfo203 }, // Inst #1240 = CVT_L_D_MMR6 |
| { 1239, 2, 1, 4, 1246, 0, 0, 0, 0x4ULL, nullptr, OperandInfo203 }, // Inst #1239 = CVT_L_D64_MM |
| { 1238, 2, 1, 4, 638, 0, 0, 0, 0x4ULL, nullptr, OperandInfo203 }, // Inst #1238 = CVT_L_D64 |
| { 1237, 2, 1, 4, 1307, 0, 0, 0, 0x4ULL, nullptr, OperandInfo203 }, // Inst #1237 = CVT_D_L_MMR6 |
| { 1236, 2, 1, 4, 1246, 0, 0, 0, 0x4ULL, nullptr, OperandInfo204 }, // Inst #1236 = CVT_D64_W_MM |
| { 1235, 2, 1, 4, 638, 0, 0, 0, 0x4ULL, nullptr, OperandInfo204 }, // Inst #1235 = CVT_D64_W |
| { 1234, 2, 1, 4, 1246, 0, 0, 0, 0x4ULL, nullptr, OperandInfo204 }, // Inst #1234 = CVT_D64_S_MM |
| { 1233, 2, 1, 4, 638, 0, 0, 0, 0x4ULL, nullptr, OperandInfo204 }, // Inst #1233 = CVT_D64_S |
| { 1232, 2, 1, 4, 638, 0, 0, 0, 0x4ULL, nullptr, OperandInfo203 }, // Inst #1232 = CVT_D64_L |
| { 1231, 2, 1, 4, 1246, 0, 0, 0, 0x4ULL, nullptr, OperandInfo224 }, // Inst #1231 = CVT_D32_W_MM |
| { 1230, 2, 1, 4, 638, 0, 0, 0, 0x4ULL, nullptr, OperandInfo224 }, // Inst #1230 = CVT_D32_W |
| { 1229, 2, 1, 4, 1246, 0, 0, 0, 0x4ULL, nullptr, OperandInfo224 }, // Inst #1229 = CVT_D32_S_MM |
| { 1228, 2, 1, 4, 638, 0, 0, 0, 0x4ULL, nullptr, OperandInfo224 }, // Inst #1228 = CVT_D32_S |
| { 1227, 2, 0, 4, 529, 0, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo223 }, // Inst #1227 = CTCMSA |
| { 1226, 2, 1, 4, 1058, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo222 }, // Inst #1226 = CTC2_MM |
| { 1225, 2, 1, 4, 1295, 0, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo221 }, // Inst #1225 = CTC1_MM |
| { 1224, 2, 1, 4, 685, 0, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo221 }, // Inst #1224 = CTC1 |
| { 1223, 3, 1, 4, 1192, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo72 }, // Inst #1223 = CRC32W |
| { 1222, 3, 1, 4, 1191, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo72 }, // Inst #1222 = CRC32H |
| { 1221, 3, 1, 4, 1196, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo72 }, // Inst #1221 = CRC32D |
| { 1220, 3, 1, 4, 1195, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo72 }, // Inst #1220 = CRC32CW |
| { 1219, 3, 1, 4, 1194, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo72 }, // Inst #1219 = CRC32CH |
| { 1218, 3, 1, 4, 1197, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo72 }, // Inst #1218 = CRC32CD |
| { 1217, 3, 1, 4, 1193, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo72 }, // Inst #1217 = CRC32CB |
| { 1216, 3, 1, 4, 1190, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo72 }, // Inst #1216 = CRC32B |
| { 1215, 3, 1, 4, 688, 0, 0, 0, 0x6ULL, nullptr, OperandInfo220 }, // Inst #1215 = COPY_U_W |
| { 1214, 3, 1, 4, 688, 0, 0, 0, 0x6ULL, nullptr, OperandInfo219 }, // Inst #1214 = COPY_U_H |
| { 1213, 3, 1, 4, 688, 0, 0, 0, 0x6ULL, nullptr, OperandInfo217 }, // Inst #1213 = COPY_U_B |
| { 1212, 3, 1, 4, 689, 0, 0, 0, 0x6ULL, nullptr, OperandInfo220 }, // Inst #1212 = COPY_S_W |
| { 1211, 3, 1, 4, 689, 0, 0, 0, 0x6ULL, nullptr, OperandInfo219 }, // Inst #1211 = COPY_S_H |
| { 1210, 3, 1, 4, 689, 0, 0, 0, 0x6ULL, nullptr, OperandInfo218 }, // Inst #1210 = COPY_S_D |
| { 1209, 3, 1, 4, 689, 0, 0, 0, 0x6ULL, nullptr, OperandInfo217 }, // Inst #1209 = COPY_S_B |
| { 1208, 3, 1, 4, 1302, 0, 0, 0, 0x16ULL, nullptr, OperandInfo216 }, // Inst #1208 = CMP_UN_S_MMR6 |
| { 1207, 3, 1, 4, 558, 0, 0, 0, 0x16ULL, nullptr, OperandInfo216 }, // Inst #1207 = CMP_UN_S |
| { 1206, 3, 1, 4, 1301, 0, 0, 0, 0x16ULL, nullptr, OperandInfo215 }, // Inst #1206 = CMP_UN_D_MMR6 |
| { 1205, 3, 1, 4, 557, 0, 0, 0, 0x16ULL, nullptr, OperandInfo215 }, // Inst #1205 = CMP_UN_D |
| { 1204, 3, 1, 4, 1304, 0, 0, 0, 0x16ULL, nullptr, OperandInfo216 }, // Inst #1204 = CMP_ULT_S_MMR6 |
| { 1203, 3, 1, 4, 566, 0, 0, 0, 0x16ULL, nullptr, OperandInfo216 }, // Inst #1203 = CMP_ULT_S |
| { 1202, 3, 1, 4, 1303, 0, 0, 0, 0x16ULL, nullptr, OperandInfo215 }, // Inst #1202 = CMP_ULT_D_MMR6 |
| { 1201, 3, 1, 4, 565, 0, 0, 0, 0x16ULL, nullptr, OperandInfo215 }, // Inst #1201 = CMP_ULT_D |
| { 1200, 3, 1, 4, 1304, 0, 0, 0, 0x16ULL, nullptr, OperandInfo216 }, // Inst #1200 = CMP_ULE_S_MMR6 |
| { 1199, 3, 1, 4, 570, 0, 0, 0, 0x16ULL, nullptr, OperandInfo216 }, // Inst #1199 = CMP_ULE_S |
| { 1198, 3, 1, 4, 1303, 0, 0, 0, 0x16ULL, nullptr, OperandInfo215 }, // Inst #1198 = CMP_ULE_D_MMR6 |
| { 1197, 3, 1, 4, 569, 0, 0, 0, 0x16ULL, nullptr, OperandInfo215 }, // Inst #1197 = CMP_ULE_D |
| { 1196, 3, 1, 4, 1304, 0, 0, 0, 0x16ULL, nullptr, OperandInfo216 }, // Inst #1196 = CMP_UEQ_S_MMR6 |
| { 1195, 3, 1, 4, 560, 0, 0, 0, 0x16ULL, nullptr, OperandInfo216 }, // Inst #1195 = CMP_UEQ_S |
| { 1194, 3, 1, 4, 1303, 0, 0, 0, 0x16ULL, nullptr, OperandInfo215 }, // Inst #1194 = CMP_UEQ_D_MMR6 |
| { 1193, 3, 1, 4, 559, 0, 0, 0, 0x16ULL, nullptr, OperandInfo215 }, // Inst #1193 = CMP_UEQ_D |
| { 1192, 3, 1, 4, 1304, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo216 }, // Inst #1192 = CMP_SUN_S_MMR6 |
| { 1191, 3, 1, 4, 1688, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo216 }, // Inst #1191 = CMP_SUN_S |
| { 1190, 3, 1, 4, 1303, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo215 }, // Inst #1190 = CMP_SUN_D_MMR6 |
| { 1189, 3, 1, 4, 1687, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo215 }, // Inst #1189 = CMP_SUN_D |
| { 1188, 3, 1, 4, 1306, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo216 }, // Inst #1188 = CMP_SULT_S_MMR6 |
| { 1187, 3, 1, 4, 1686, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo216 }, // Inst #1187 = CMP_SULT_S |
| { 1186, 3, 1, 4, 1305, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo215 }, // Inst #1186 = CMP_SULT_D_MMR6 |
| { 1185, 3, 1, 4, 1685, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo215 }, // Inst #1185 = CMP_SULT_D |
| { 1184, 3, 1, 4, 1306, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo216 }, // Inst #1184 = CMP_SULE_S_MMR6 |
| { 1183, 3, 1, 4, 1684, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo216 }, // Inst #1183 = CMP_SULE_S |
| { 1182, 3, 1, 4, 1305, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo215 }, // Inst #1182 = CMP_SULE_D_MMR6 |
| { 1181, 3, 1, 4, 1683, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo215 }, // Inst #1181 = CMP_SULE_D |
| { 1180, 3, 1, 4, 1306, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo216 }, // Inst #1180 = CMP_SUEQ_S_MMR6 |
| { 1179, 3, 1, 4, 1682, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo216 }, // Inst #1179 = CMP_SUEQ_S |
| { 1178, 3, 1, 4, 1305, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo215 }, // Inst #1178 = CMP_SUEQ_D_MMR6 |
| { 1177, 3, 1, 4, 1681, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo215 }, // Inst #1177 = CMP_SUEQ_D |
| { 1176, 3, 1, 4, 1304, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo216 }, // Inst #1176 = CMP_SLT_S_MMR6 |
| { 1175, 3, 1, 4, 1680, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo216 }, // Inst #1175 = CMP_SLT_S |
| { 1174, 3, 1, 4, 1303, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo215 }, // Inst #1174 = CMP_SLT_D_MMR6 |
| { 1173, 3, 1, 4, 1679, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo215 }, // Inst #1173 = CMP_SLT_D |
| { 1172, 3, 1, 4, 1304, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo216 }, // Inst #1172 = CMP_SLE_S_MMR6 |
| { 1171, 3, 1, 4, 1678, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo216 }, // Inst #1171 = CMP_SLE_S |
| { 1170, 3, 1, 4, 1303, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo215 }, // Inst #1170 = CMP_SLE_D_MMR6 |
| { 1169, 3, 1, 4, 1677, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo215 }, // Inst #1169 = CMP_SLE_D |
| { 1168, 3, 1, 4, 1304, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo216 }, // Inst #1168 = CMP_SEQ_S_MMR6 |
| { 1167, 3, 1, 4, 1676, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo216 }, // Inst #1167 = CMP_SEQ_S |
| { 1166, 3, 1, 4, 1303, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo215 }, // Inst #1166 = CMP_SEQ_D_MMR6 |
| { 1165, 3, 1, 4, 1675, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo215 }, // Inst #1165 = CMP_SEQ_D |
| { 1164, 3, 1, 4, 1304, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo216 }, // Inst #1164 = CMP_SAF_S_MMR6 |
| { 1163, 3, 1, 4, 1674, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo216 }, // Inst #1163 = CMP_SAF_S |
| { 1162, 3, 1, 4, 1303, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo215 }, // Inst #1162 = CMP_SAF_D_MMR6 |
| { 1161, 3, 1, 4, 1673, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo215 }, // Inst #1161 = CMP_SAF_D |
| { 1160, 3, 1, 4, 1302, 0, 0, 0, 0x16ULL, nullptr, OperandInfo216 }, // Inst #1160 = CMP_LT_S_MMR6 |
| { 1159, 3, 1, 4, 564, 0, 0, 0, 0x16ULL, nullptr, OperandInfo216 }, // Inst #1159 = CMP_LT_S |
| { 1158, 2, 0, 4, 1527, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList11, OperandInfo168 }, // Inst #1158 = CMP_LT_PH_MM |
| { 1157, 2, 0, 4, 1376, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList11, OperandInfo168 }, // Inst #1157 = CMP_LT_PH |
| { 1156, 3, 1, 4, 1301, 0, 0, 0, 0x16ULL, nullptr, OperandInfo215 }, // Inst #1156 = CMP_LT_D_MMR6 |
| { 1155, 3, 1, 4, 563, 0, 0, 0, 0x16ULL, nullptr, OperandInfo215 }, // Inst #1155 = CMP_LT_D |
| { 1154, 3, 1, 4, 1302, 0, 0, 0, 0x16ULL, nullptr, OperandInfo216 }, // Inst #1154 = CMP_LE_S_MMR6 |
| { 1153, 3, 1, 4, 568, 0, 0, 0, 0x16ULL, nullptr, OperandInfo216 }, // Inst #1153 = CMP_LE_S |
| { 1152, 2, 0, 4, 1526, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList11, OperandInfo168 }, // Inst #1152 = CMP_LE_PH_MM |
| { 1151, 2, 0, 4, 1375, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList11, OperandInfo168 }, // Inst #1151 = CMP_LE_PH |
| { 1150, 3, 1, 4, 1301, 0, 0, 0, 0x16ULL, nullptr, OperandInfo215 }, // Inst #1150 = CMP_LE_D_MMR6 |
| { 1149, 3, 1, 4, 567, 0, 0, 0, 0x16ULL, nullptr, OperandInfo215 }, // Inst #1149 = CMP_LE_D |
| { 1148, 3, 1, 4, 1672, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo216 }, // Inst #1148 = CMP_F_S |
| { 1147, 3, 1, 4, 1671, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo215 }, // Inst #1147 = CMP_F_D |
| { 1146, 3, 1, 4, 1302, 0, 0, 0, 0x16ULL, nullptr, OperandInfo216 }, // Inst #1146 = CMP_EQ_S_MMR6 |
| { 1145, 3, 1, 4, 562, 0, 0, 0, 0x16ULL, nullptr, OperandInfo216 }, // Inst #1145 = CMP_EQ_S |
| { 1144, 2, 0, 4, 1525, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList11, OperandInfo168 }, // Inst #1144 = CMP_EQ_PH_MM |
| { 1143, 2, 0, 4, 1374, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList11, OperandInfo168 }, // Inst #1143 = CMP_EQ_PH |
| { 1142, 3, 1, 4, 1301, 0, 0, 0, 0x16ULL, nullptr, OperandInfo215 }, // Inst #1142 = CMP_EQ_D_MMR6 |
| { 1141, 3, 1, 4, 561, 0, 0, 0, 0x16ULL, nullptr, OperandInfo215 }, // Inst #1141 = CMP_EQ_D |
| { 1140, 3, 1, 4, 1302, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo216 }, // Inst #1140 = CMP_AF_S_MMR6 |
| { 1139, 3, 1, 4, 1301, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo215 }, // Inst #1139 = CMP_AF_D_MMR6 |
| { 1138, 2, 0, 4, 1524, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList11, OperandInfo168 }, // Inst #1138 = CMPU_LT_QB_MM |
| { 1137, 2, 0, 4, 1373, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList11, OperandInfo168 }, // Inst #1137 = CMPU_LT_QB |
| { 1136, 2, 0, 4, 1523, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList11, OperandInfo168 }, // Inst #1136 = CMPU_LE_QB_MM |
| { 1135, 2, 0, 4, 1372, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList11, OperandInfo168 }, // Inst #1135 = CMPU_LE_QB |
| { 1134, 2, 0, 4, 1522, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList11, OperandInfo168 }, // Inst #1134 = CMPU_EQ_QB_MM |
| { 1133, 2, 0, 4, 1371, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList11, OperandInfo168 }, // Inst #1133 = CMPU_EQ_QB |
| { 1132, 3, 1, 4, 1521, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo214 }, // Inst #1132 = CMPGU_LT_QB_MM |
| { 1131, 3, 1, 4, 1370, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo214 }, // Inst #1131 = CMPGU_LT_QB |
| { 1130, 3, 1, 4, 1520, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo214 }, // Inst #1130 = CMPGU_LE_QB_MM |
| { 1129, 3, 1, 4, 1369, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo214 }, // Inst #1129 = CMPGU_LE_QB |
| { 1128, 3, 1, 4, 1519, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo214 }, // Inst #1128 = CMPGU_EQ_QB_MM |
| { 1127, 3, 1, 4, 1368, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo214 }, // Inst #1127 = CMPGU_EQ_QB |
| { 1126, 3, 1, 4, 1637, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList11, OperandInfo214 }, // Inst #1126 = CMPGDU_LT_QB_MMR2 |
| { 1125, 3, 1, 4, 1473, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList11, OperandInfo214 }, // Inst #1125 = CMPGDU_LT_QB |
| { 1124, 3, 1, 4, 1636, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList11, OperandInfo214 }, // Inst #1124 = CMPGDU_LE_QB_MMR2 |
| { 1123, 3, 1, 4, 1472, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList11, OperandInfo214 }, // Inst #1123 = CMPGDU_LE_QB |
| { 1122, 3, 1, 4, 1635, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList11, OperandInfo214 }, // Inst #1122 = CMPGDU_EQ_QB_MMR2 |
| { 1121, 3, 1, 4, 1471, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList11, OperandInfo214 }, // Inst #1121 = CMPGDU_EQ_QB |
| { 1120, 2, 1, 4, 732, 0, 0, 0, 0x6ULL, nullptr, OperandInfo45 }, // Inst #1120 = CLZ_R6 |
| { 1119, 2, 1, 4, 786, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo45 }, // Inst #1119 = CLZ_MMR6 |
| { 1118, 2, 1, 4, 745, 0, 0, 0, 0x1ULL, nullptr, OperandInfo45 }, // Inst #1118 = CLZ_MM |
| { 1117, 2, 1, 4, 475, 0, 0, 0, 0x1ULL, nullptr, OperandInfo45 }, // Inst #1117 = CLZ |
| { 1116, 3, 1, 4, 554, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1116 = CLT_U_W |
| { 1115, 3, 1, 4, 554, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #1115 = CLT_U_H |
| { 1114, 3, 1, 4, 554, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1114 = CLT_U_D |
| { 1113, 3, 1, 4, 554, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #1113 = CLT_U_B |
| { 1112, 3, 1, 4, 554, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1112 = CLT_S_W |
| { 1111, 3, 1, 4, 554, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #1111 = CLT_S_H |
| { 1110, 3, 1, 4, 554, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1110 = CLT_S_D |
| { 1109, 3, 1, 4, 554, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #1109 = CLT_S_B |
| { 1108, 3, 1, 4, 554, 0, 0, 0, 0x6ULL, nullptr, OperandInfo179 }, // Inst #1108 = CLTI_U_W |
| { 1107, 3, 1, 4, 554, 0, 0, 0, 0x6ULL, nullptr, OperandInfo178 }, // Inst #1107 = CLTI_U_H |
| { 1106, 3, 1, 4, 554, 0, 0, 0, 0x6ULL, nullptr, OperandInfo177 }, // Inst #1106 = CLTI_U_D |
| { 1105, 3, 1, 4, 554, 0, 0, 0, 0x6ULL, nullptr, OperandInfo176 }, // Inst #1105 = CLTI_U_B |
| { 1104, 3, 1, 4, 554, 0, 0, 0, 0x6ULL, nullptr, OperandInfo179 }, // Inst #1104 = CLTI_S_W |
| { 1103, 3, 1, 4, 554, 0, 0, 0, 0x6ULL, nullptr, OperandInfo178 }, // Inst #1103 = CLTI_S_H |
| { 1102, 3, 1, 4, 554, 0, 0, 0, 0x6ULL, nullptr, OperandInfo177 }, // Inst #1102 = CLTI_S_D |
| { 1101, 3, 1, 4, 554, 0, 0, 0, 0x6ULL, nullptr, OperandInfo176 }, // Inst #1101 = CLTI_S_B |
| { 1100, 2, 1, 4, 731, 0, 0, 0, 0x6ULL, nullptr, OperandInfo45 }, // Inst #1100 = CLO_R6 |
| { 1099, 2, 1, 4, 785, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo45 }, // Inst #1099 = CLO_MMR6 |
| { 1098, 2, 1, 4, 744, 0, 0, 0, 0x1ULL, nullptr, OperandInfo45 }, // Inst #1098 = CLO_MM |
| { 1097, 2, 1, 4, 474, 0, 0, 0, 0x1ULL, nullptr, OperandInfo45 }, // Inst #1097 = CLO |
| { 1096, 3, 1, 4, 555, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1096 = CLE_U_W |
| { 1095, 3, 1, 4, 555, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #1095 = CLE_U_H |
| { 1094, 3, 1, 4, 555, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1094 = CLE_U_D |
| { 1093, 3, 1, 4, 555, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #1093 = CLE_U_B |
| { 1092, 3, 1, 4, 555, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1092 = CLE_S_W |
| { 1091, 3, 1, 4, 555, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #1091 = CLE_S_H |
| { 1090, 3, 1, 4, 555, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1090 = CLE_S_D |
| { 1089, 3, 1, 4, 555, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #1089 = CLE_S_B |
| { 1088, 3, 1, 4, 555, 0, 0, 0, 0x6ULL, nullptr, OperandInfo179 }, // Inst #1088 = CLEI_U_W |
| { 1087, 3, 1, 4, 555, 0, 0, 0, 0x6ULL, nullptr, OperandInfo178 }, // Inst #1087 = CLEI_U_H |
| { 1086, 3, 1, 4, 555, 0, 0, 0, 0x6ULL, nullptr, OperandInfo177 }, // Inst #1086 = CLEI_U_D |
| { 1085, 3, 1, 4, 555, 0, 0, 0, 0x6ULL, nullptr, OperandInfo176 }, // Inst #1085 = CLEI_U_B |
| { 1084, 3, 1, 4, 555, 0, 0, 0, 0x6ULL, nullptr, OperandInfo179 }, // Inst #1084 = CLEI_S_W |
| { 1083, 3, 1, 4, 555, 0, 0, 0, 0x6ULL, nullptr, OperandInfo178 }, // Inst #1083 = CLEI_S_H |
| { 1082, 3, 1, 4, 555, 0, 0, 0, 0x6ULL, nullptr, OperandInfo177 }, // Inst #1082 = CLEI_S_D |
| { 1081, 3, 1, 4, 555, 0, 0, 0, 0x6ULL, nullptr, OperandInfo176 }, // Inst #1081 = CLEI_S_B |
| { 1080, 2, 1, 4, 1314, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo207 }, // Inst #1080 = CLASS_S_MMR6 |
| { 1079, 2, 1, 4, 1227, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo207 }, // Inst #1079 = CLASS_S |
| { 1078, 2, 1, 4, 1314, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo203 }, // Inst #1078 = CLASS_D_MMR6 |
| { 1077, 2, 1, 4, 1228, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo203 }, // Inst #1077 = CLASS_D |
| { 1076, 4, 1, 4, 1200, 0, 0, 0, 0x1ULL, nullptr, OperandInfo213 }, // Inst #1076 = CINS_i32 |
| { 1075, 4, 1, 4, 1200, 0, 0, 0, 0x1ULL, nullptr, OperandInfo212 }, // Inst #1075 = CINS64_32 |
| { 1074, 4, 1, 4, 1200, 0, 0, 0, 0x1ULL, nullptr, OperandInfo211 }, // Inst #1074 = CINS32 |
| { 1073, 4, 1, 4, 1200, 0, 0, 0, 0x1ULL, nullptr, OperandInfo211 }, // Inst #1073 = CINS |
| { 1072, 2, 1, 4, 529, 0, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo210 }, // Inst #1072 = CFCMSA |
| { 1071, 2, 1, 4, 1057, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo209 }, // Inst #1071 = CFC2_MM |
| { 1070, 2, 1, 4, 1294, 0, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo208 }, // Inst #1070 = CFC1_MM |
| { 1069, 2, 1, 4, 694, 0, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo208 }, // Inst #1069 = CFC1 |
| { 1068, 3, 1, 4, 556, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo48 }, // Inst #1068 = CEQ_W |
| { 1067, 3, 1, 4, 556, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo47 }, // Inst #1067 = CEQ_H |
| { 1066, 3, 1, 4, 556, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo46 }, // Inst #1066 = CEQ_D |
| { 1065, 3, 1, 4, 556, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo174 }, // Inst #1065 = CEQ_B |
| { 1064, 3, 1, 4, 556, 0, 0, 0, 0x6ULL, nullptr, OperandInfo179 }, // Inst #1064 = CEQI_W |
| { 1063, 3, 1, 4, 556, 0, 0, 0, 0x6ULL, nullptr, OperandInfo178 }, // Inst #1063 = CEQI_H |
| { 1062, 3, 1, 4, 556, 0, 0, 0, 0x6ULL, nullptr, OperandInfo177 }, // Inst #1062 = CEQI_D |
| { 1061, 3, 1, 4, 556, 0, 0, 0, 0x6ULL, nullptr, OperandInfo176 }, // Inst #1061 = CEQI_B |
| { 1060, 2, 1, 4, 1311, 0, 0, 0, 0x4ULL, nullptr, OperandInfo207 }, // Inst #1060 = CEIL_W_S_MMR6 |
| { 1059, 2, 1, 4, 1247, 0, 0, 0, 0x4ULL, nullptr, OperandInfo207 }, // Inst #1059 = CEIL_W_S_MM |
| { 1058, 2, 1, 4, 717, 0, 0, 0, 0x4ULL, nullptr, OperandInfo207 }, // Inst #1058 = CEIL_W_S |
| { 1057, 2, 1, 4, 1247, 0, 0, 0, 0x4ULL, nullptr, OperandInfo205 }, // Inst #1057 = CEIL_W_MM |
| { 1056, 2, 1, 4, 1311, 0, 0, 0, 0x4ULL, nullptr, OperandInfo205 }, // Inst #1056 = CEIL_W_D_MMR6 |
| { 1055, 2, 1, 4, 717, 0, 0, 0, 0x4ULL, nullptr, OperandInfo206 }, // Inst #1055 = CEIL_W_D64 |
| { 1054, 2, 1, 4, 717, 0, 0, 0, 0x4ULL, nullptr, OperandInfo205 }, // Inst #1054 = CEIL_W_D32 |
| { 1053, 2, 1, 4, 1311, 0, 0, 0, 0x4ULL, nullptr, OperandInfo204 }, // Inst #1053 = CEIL_L_S_MMR6 |
| { 1052, 2, 1, 4, 717, 0, 0, 0, 0x4ULL, nullptr, OperandInfo204 }, // Inst #1052 = CEIL_L_S |
| { 1051, 2, 1, 4, 1311, 0, 0, 0, 0x4ULL, nullptr, OperandInfo203 }, // Inst #1051 = CEIL_L_D_MMR6 |
| { 1050, 2, 1, 4, 717, 0, 0, 0, 0x4ULL, nullptr, OperandInfo203 }, // Inst #1050 = CEIL_L_D64 |
| { 1049, 3, 0, 4, 1088, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo202 }, // Inst #1049 = CACHE_R6 |
| { 1048, 3, 0, 4, 1162, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo202 }, // Inst #1048 = CACHE_MMR6 |
| { 1047, 3, 0, 4, 1140, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo202 }, // Inst #1047 = CACHE_MM |
| { 1046, 3, 0, 4, 1107, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo202 }, // Inst #1046 = CACHEE_MM |
| { 1045, 3, 0, 4, 471, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo202 }, // Inst #1045 = CACHEE |
| { 1044, 3, 0, 4, 470, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo202 }, // Inst #1044 = CACHE |
| { 1043, 1, 0, 4, 939, 1, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList7, OperandInfo2 }, // Inst #1043 = BtnezX16 |
| { 1042, 1, 0, 2, 939, 1, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList7, OperandInfo2 }, // Inst #1042 = Btnez16 |
| { 1041, 1, 0, 4, 939, 1, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList7, OperandInfo2 }, // Inst #1041 = BteqzX16 |
| { 1040, 1, 0, 2, 939, 1, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList7, OperandInfo2 }, // Inst #1040 = Bteqz16 |
| { 1039, 0, 0, 2, 943, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #1039 = Break16 |
| { 1038, 2, 0, 4, 939, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo201 }, // Inst #1038 = BnezRxImmX16 |
| { 1037, 2, 0, 2, 939, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, OperandInfo201 }, // Inst #1037 = BnezRxImm16 |
| { 1036, 1, 0, 4, 939, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo55 }, // Inst #1036 = BimmX16 |
| { 1035, 1, 0, 2, 939, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, OperandInfo55 }, // Inst #1035 = Bimm16 |
| { 1034, 2, 0, 4, 939, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo201 }, // Inst #1034 = BeqzRxImmX16 |
| { 1033, 2, 0, 2, 939, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, OperandInfo201 }, // Inst #1033 = BeqzRxImm16 |
| { 1032, 2, 0, 4, 528, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList2, OperandInfo200 }, // Inst #1032 = BZ_W |
| { 1031, 2, 0, 4, 528, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList2, OperandInfo197 }, // Inst #1031 = BZ_V |
| { 1030, 2, 0, 4, 528, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList2, OperandInfo199 }, // Inst #1030 = BZ_H |
| { 1029, 2, 0, 4, 528, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList2, OperandInfo198 }, // Inst #1029 = BZ_D |
| { 1028, 2, 0, 4, 528, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList2, OperandInfo197 }, // Inst #1028 = BZ_B |
| { 1027, 3, 1, 4, 520, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1027 = BSET_W |
| { 1026, 3, 1, 4, 520, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #1026 = BSET_H |
| { 1025, 3, 1, 4, 520, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1025 = BSET_D |
| { 1024, 3, 1, 4, 520, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #1024 = BSET_B |
| { 1023, 3, 1, 4, 520, 0, 0, 0, 0x6ULL, nullptr, OperandInfo179 }, // Inst #1023 = BSETI_W |
| { 1022, 3, 1, 4, 520, 0, 0, 0, 0x6ULL, nullptr, OperandInfo178 }, // Inst #1022 = BSETI_H |
| { 1021, 3, 1, 4, 520, 0, 0, 0, 0x6ULL, nullptr, OperandInfo177 }, // Inst #1021 = BSETI_D |
| { 1020, 3, 1, 4, 520, 0, 0, 0, 0x6ULL, nullptr, OperandInfo176 }, // Inst #1020 = BSETI_B |
| { 1019, 4, 1, 4, 523, 0, 0, 0, 0x6ULL, nullptr, OperandInfo196 }, // Inst #1019 = BSEL_V |
| { 1018, 4, 1, 4, 523, 0, 0, 0, 0x6ULL, nullptr, OperandInfo192 }, // Inst #1018 = BSELI_B |
| { 1017, 2, 0, 4, 1007, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo7 }, // Inst #1017 = BREAK_MMR6 |
| { 1016, 2, 0, 4, 966, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo7 }, // Inst #1016 = BREAK_MM |
| { 1015, 1, 0, 2, 1007, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo2 }, // Inst #1015 = BREAK16_MMR6 |
| { 1014, 1, 0, 2, 966, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo2 }, // Inst #1014 = BREAK16_MM |
| { 1013, 2, 0, 4, 379, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo7 }, // Inst #1013 = BREAK |
| { 1012, 1, 0, 4, 1518, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo55 }, // Inst #1012 = BPOSGE32_MM |
| { 1011, 1, 0, 4, 1670, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo55 }, // Inst #1011 = BPOSGE32C_MMR3 |
| { 1010, 1, 0, 4, 1367, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo55 }, // Inst #1010 = BPOSGE32 |
| { 1009, 3, 0, 4, 985, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, ImplicitList2, OperandInfo57 }, // Inst #1009 = BOVC_MMR6 |
| { 1008, 3, 0, 4, 931, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, ImplicitList2, OperandInfo57 }, // Inst #1008 = BOVC |
| { 1007, 2, 0, 4, 528, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList2, OperandInfo200 }, // Inst #1007 = BNZ_W |
| { 1006, 2, 0, 4, 528, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList2, OperandInfo197 }, // Inst #1006 = BNZ_V |
| { 1005, 2, 0, 4, 528, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList2, OperandInfo199 }, // Inst #1005 = BNZ_H |
| { 1004, 2, 0, 4, 528, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList2, OperandInfo198 }, // Inst #1004 = BNZ_D |
| { 1003, 2, 0, 4, 528, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList2, OperandInfo197 }, // Inst #1003 = BNZ_B |
| { 1002, 3, 0, 4, 985, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, ImplicitList2, OperandInfo57 }, // Inst #1002 = BNVC_MMR6 |
| { 1001, 3, 0, 4, 931, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, ImplicitList2, OperandInfo57 }, // Inst #1001 = BNVC |
| { 1000, 3, 0, 4, 951, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, ImplicitList2, OperandInfo57 }, // Inst #1000 = BNE_MM |
| { 999, 2, 0, 4, 987, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x36ULL, ImplicitList2, OperandInfo108 }, // Inst #999 = BNEZC_MMR6 |
| { 998, 2, 0, 4, 950, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, ImplicitList2, OperandInfo108 }, // Inst #998 = BNEZC_MM |
| { 997, 2, 0, 4, 1018, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, ImplicitList2, OperandInfo109 }, // Inst #997 = BNEZC64 |
| { 996, 2, 0, 2, 986, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList2, OperandInfo191 }, // Inst #996 = BNEZC16_MMR6 |
| { 995, 2, 0, 4, 932, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, ImplicitList2, OperandInfo108 }, // Inst #995 = BNEZC |
| { 994, 2, 0, 4, 1000, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, ImplicitList3, OperandInfo108 }, // Inst #994 = BNEZALC_MMR6 |
| { 993, 2, 0, 4, 927, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, ImplicitList3, OperandInfo108 }, // Inst #993 = BNEZALC |
| { 992, 2, 0, 2, 949, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList2, OperandInfo191 }, // Inst #992 = BNEZ16_MM |
| { 991, 3, 0, 4, 377, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, ImplicitList2, OperandInfo57 }, // Inst #991 = BNEL |
| { 990, 3, 1, 4, 522, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #990 = BNEG_W |
| { 989, 3, 1, 4, 522, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #989 = BNEG_H |
| { 988, 3, 1, 4, 522, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #988 = BNEG_D |
| { 987, 3, 1, 4, 522, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #987 = BNEG_B |
| { 986, 3, 1, 4, 522, 0, 0, 0, 0x6ULL, nullptr, OperandInfo179 }, // Inst #986 = BNEGI_W |
| { 985, 3, 1, 4, 522, 0, 0, 0, 0x6ULL, nullptr, OperandInfo178 }, // Inst #985 = BNEGI_H |
| { 984, 3, 1, 4, 522, 0, 0, 0, 0x6ULL, nullptr, OperandInfo177 }, // Inst #984 = BNEGI_D |
| { 983, 3, 1, 4, 522, 0, 0, 0, 0x6ULL, nullptr, OperandInfo176 }, // Inst #983 = BNEGI_B |
| { 982, 3, 0, 4, 985, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, ImplicitList2, OperandInfo57 }, // Inst #982 = BNEC_MMR6 |
| { 981, 3, 0, 4, 1017, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, ImplicitList2, OperandInfo106 }, // Inst #981 = BNEC64 |
| { 980, 3, 0, 4, 931, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, ImplicitList2, OperandInfo57 }, // Inst #980 = BNEC |
| { 979, 3, 0, 4, 1009, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, ImplicitList2, OperandInfo106 }, // Inst #979 = BNE64 |
| { 978, 3, 0, 4, 920, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, ImplicitList2, OperandInfo57 }, // Inst #978 = BNE |
| { 977, 4, 1, 4, 524, 0, 0, 0, 0x6ULL, nullptr, OperandInfo196 }, // Inst #977 = BMZ_V |
| { 976, 4, 1, 4, 524, 0, 0, 0, 0x6ULL, nullptr, OperandInfo192 }, // Inst #976 = BMZI_B |
| { 975, 4, 1, 4, 524, 0, 0, 0, 0x6ULL, nullptr, OperandInfo196 }, // Inst #975 = BMNZ_V |
| { 974, 4, 1, 4, 524, 0, 0, 0, 0x6ULL, nullptr, OperandInfo192 }, // Inst #974 = BMNZI_B |
| { 973, 2, 0, 4, 949, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, ImplicitList2, OperandInfo108 }, // Inst #973 = BLTZ_MM |
| { 972, 2, 0, 4, 378, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, ImplicitList2, OperandInfo108 }, // Inst #972 = BLTZL |
| { 971, 2, 0, 4, 987, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, ImplicitList2, OperandInfo108 }, // Inst #971 = BLTZC_MMR6 |
| { 970, 2, 0, 4, 1018, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, ImplicitList2, OperandInfo109 }, // Inst #970 = BLTZC64 |
| { 969, 2, 0, 4, 932, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, ImplicitList2, OperandInfo108 }, // Inst #969 = BLTZC |
| { 968, 2, 0, 4, 958, 0, 1, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, ImplicitList3, OperandInfo108 }, // Inst #968 = BLTZAL_MM |
| { 967, 2, 0, 4, 957, 0, 1, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, ImplicitList3, OperandInfo108 }, // Inst #967 = BLTZALS_MM |
| { 966, 2, 0, 4, 376, 0, 1, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, ImplicitList3, OperandInfo108 }, // Inst #966 = BLTZALL |
| { 965, 2, 0, 4, 1000, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, ImplicitList3, OperandInfo108 }, // Inst #965 = BLTZALC_MMR6 |
| { 964, 2, 0, 4, 927, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, ImplicitList3, OperandInfo108 }, // Inst #964 = BLTZALC |
| { 963, 2, 0, 4, 919, 0, 1, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, ImplicitList3, OperandInfo108 }, // Inst #963 = BLTZAL |
| { 962, 2, 0, 4, 1010, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, ImplicitList2, OperandInfo109 }, // Inst #962 = BLTZ64 |
| { 961, 2, 0, 4, 921, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, ImplicitList2, OperandInfo108 }, // Inst #961 = BLTZ |
| { 960, 3, 0, 4, 985, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, ImplicitList2, OperandInfo57 }, // Inst #960 = BLTUC_MMR6 |
| { 959, 3, 0, 4, 1017, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, ImplicitList2, OperandInfo106 }, // Inst #959 = BLTUC64 |
| { 958, 3, 0, 4, 931, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, ImplicitList2, OperandInfo57 }, // Inst #958 = BLTUC |
| { 957, 3, 0, 4, 985, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, ImplicitList2, OperandInfo57 }, // Inst #957 = BLTC_MMR6 |
| { 956, 3, 0, 4, 1017, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, ImplicitList2, OperandInfo106 }, // Inst #956 = BLTC64 |
| { 955, 3, 0, 4, 931, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, ImplicitList2, OperandInfo57 }, // Inst #955 = BLTC |
| { 954, 2, 0, 4, 949, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, ImplicitList2, OperandInfo108 }, // Inst #954 = BLEZ_MM |
| { 953, 2, 0, 4, 378, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, ImplicitList2, OperandInfo108 }, // Inst #953 = BLEZL |
| { 952, 2, 0, 4, 987, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, ImplicitList2, OperandInfo108 }, // Inst #952 = BLEZC_MMR6 |
| { 951, 2, 0, 4, 1018, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, ImplicitList2, OperandInfo109 }, // Inst #951 = BLEZC64 |
| { 950, 2, 0, 4, 932, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, ImplicitList2, OperandInfo108 }, // Inst #950 = BLEZC |
| { 949, 2, 0, 4, 1000, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, ImplicitList3, OperandInfo108 }, // Inst #949 = BLEZALC_MMR6 |
| { 948, 2, 0, 4, 927, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, ImplicitList3, OperandInfo108 }, // Inst #948 = BLEZALC |
| { 947, 2, 0, 4, 1010, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, ImplicitList2, OperandInfo109 }, // Inst #947 = BLEZ64 |
| { 946, 2, 0, 4, 921, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, ImplicitList2, OperandInfo108 }, // Inst #946 = BLEZ |
| { 945, 2, 1, 4, 784, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo45 }, // Inst #945 = BITSWAP_MMR6 |
| { 944, 2, 1, 4, 730, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo45 }, // Inst #944 = BITSWAP |
| { 943, 2, 1, 4, 1517, 0, 0, 0, 0x6ULL, nullptr, OperandInfo45 }, // Inst #943 = BITREV_MM |
| { 942, 2, 1, 4, 1366, 0, 0, 0, 0x6ULL, nullptr, OperandInfo45 }, // Inst #942 = BITREV |
| { 941, 4, 1, 4, 517, 0, 0, 0, 0x6ULL, nullptr, OperandInfo60 }, // Inst #941 = BINSR_W |
| { 940, 4, 1, 4, 517, 0, 0, 0, 0x6ULL, nullptr, OperandInfo61 }, // Inst #940 = BINSR_H |
| { 939, 4, 1, 4, 517, 0, 0, 0, 0x6ULL, nullptr, OperandInfo59 }, // Inst #939 = BINSR_D |
| { 938, 4, 1, 4, 517, 0, 0, 0, 0x6ULL, nullptr, OperandInfo196 }, // Inst #938 = BINSR_B |
| { 937, 4, 1, 4, 517, 0, 0, 0, 0x6ULL, nullptr, OperandInfo195 }, // Inst #937 = BINSRI_W |
| { 936, 4, 1, 4, 517, 0, 0, 0, 0x6ULL, nullptr, OperandInfo194 }, // Inst #936 = BINSRI_H |
| { 935, 4, 1, 4, 517, 0, 0, 0, 0x6ULL, nullptr, OperandInfo193 }, // Inst #935 = BINSRI_D |
| { 934, 4, 1, 4, 517, 0, 0, 0, 0x6ULL, nullptr, OperandInfo192 }, // Inst #934 = BINSRI_B |
| { 933, 4, 1, 4, 516, 0, 0, 0, 0x6ULL, nullptr, OperandInfo60 }, // Inst #933 = BINSL_W |
| { 932, 4, 1, 4, 516, 0, 0, 0, 0x6ULL, nullptr, OperandInfo61 }, // Inst #932 = BINSL_H |
| { 931, 4, 1, 4, 516, 0, 0, 0, 0x6ULL, nullptr, OperandInfo59 }, // Inst #931 = BINSL_D |
| { 930, 4, 1, 4, 516, 0, 0, 0, 0x6ULL, nullptr, OperandInfo196 }, // Inst #930 = BINSL_B |
| { 929, 4, 1, 4, 516, 0, 0, 0, 0x6ULL, nullptr, OperandInfo195 }, // Inst #929 = BINSLI_W |
| { 928, 4, 1, 4, 516, 0, 0, 0, 0x6ULL, nullptr, OperandInfo194 }, // Inst #928 = BINSLI_H |
| { 927, 4, 1, 4, 516, 0, 0, 0, 0x6ULL, nullptr, OperandInfo193 }, // Inst #927 = BINSLI_D |
| { 926, 4, 1, 4, 516, 0, 0, 0, 0x6ULL, nullptr, OperandInfo192 }, // Inst #926 = BINSLI_B |
| { 925, 2, 0, 4, 949, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, ImplicitList2, OperandInfo108 }, // Inst #925 = BGTZ_MM |
| { 924, 2, 0, 4, 378, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, ImplicitList2, OperandInfo108 }, // Inst #924 = BGTZL |
| { 923, 2, 0, 4, 987, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, ImplicitList2, OperandInfo108 }, // Inst #923 = BGTZC_MMR6 |
| { 922, 2, 0, 4, 1018, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, ImplicitList2, OperandInfo109 }, // Inst #922 = BGTZC64 |
| { 921, 2, 0, 4, 932, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, ImplicitList2, OperandInfo108 }, // Inst #921 = BGTZC |
| { 920, 2, 0, 4, 1000, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, ImplicitList3, OperandInfo108 }, // Inst #920 = BGTZALC_MMR6 |
| { 919, 2, 0, 4, 927, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, ImplicitList3, OperandInfo108 }, // Inst #919 = BGTZALC |
| { 918, 2, 0, 4, 1010, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, ImplicitList2, OperandInfo109 }, // Inst #918 = BGTZ64 |
| { 917, 2, 0, 4, 921, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, ImplicitList2, OperandInfo108 }, // Inst #917 = BGTZ |
| { 916, 2, 0, 4, 949, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, ImplicitList2, OperandInfo108 }, // Inst #916 = BGEZ_MM |
| { 915, 2, 0, 4, 378, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, ImplicitList2, OperandInfo108 }, // Inst #915 = BGEZL |
| { 914, 2, 0, 4, 987, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, ImplicitList2, OperandInfo108 }, // Inst #914 = BGEZC_MMR6 |
| { 913, 2, 0, 4, 1018, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, ImplicitList2, OperandInfo109 }, // Inst #913 = BGEZC64 |
| { 912, 2, 0, 4, 932, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, ImplicitList2, OperandInfo108 }, // Inst #912 = BGEZC |
| { 911, 2, 0, 4, 958, 0, 1, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, ImplicitList3, OperandInfo108 }, // Inst #911 = BGEZAL_MM |
| { 910, 2, 0, 4, 957, 0, 1, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, ImplicitList3, OperandInfo108 }, // Inst #910 = BGEZALS_MM |
| { 909, 2, 0, 4, 376, 0, 1, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, ImplicitList3, OperandInfo108 }, // Inst #909 = BGEZALL |
| { 908, 2, 0, 4, 1000, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, ImplicitList3, OperandInfo108 }, // Inst #908 = BGEZALC_MMR6 |
| { 907, 2, 0, 4, 927, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, ImplicitList3, OperandInfo108 }, // Inst #907 = BGEZALC |
| { 906, 2, 0, 4, 925, 0, 1, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, ImplicitList3, OperandInfo108 }, // Inst #906 = BGEZAL |
| { 905, 2, 0, 4, 1010, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, ImplicitList2, OperandInfo109 }, // Inst #905 = BGEZ64 |
| { 904, 2, 0, 4, 921, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, ImplicitList2, OperandInfo108 }, // Inst #904 = BGEZ |
| { 903, 3, 0, 4, 985, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, ImplicitList2, OperandInfo57 }, // Inst #903 = BGEUC_MMR6 |
| { 902, 3, 0, 4, 1017, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, ImplicitList2, OperandInfo106 }, // Inst #902 = BGEUC64 |
| { 901, 3, 0, 4, 931, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, ImplicitList2, OperandInfo57 }, // Inst #901 = BGEUC |
| { 900, 3, 0, 4, 985, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, ImplicitList2, OperandInfo57 }, // Inst #900 = BGEC_MMR6 |
| { 899, 3, 0, 4, 1017, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, ImplicitList2, OperandInfo106 }, // Inst #899 = BGEC64 |
| { 898, 3, 0, 4, 931, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, ImplicitList2, OperandInfo57 }, // Inst #898 = BGEC |
| { 897, 3, 0, 4, 951, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, ImplicitList2, OperandInfo57 }, // Inst #897 = BEQ_MM |
| { 896, 2, 0, 4, 987, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x36ULL, ImplicitList2, OperandInfo108 }, // Inst #896 = BEQZC_MMR6 |
| { 895, 2, 0, 4, 950, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, ImplicitList2, OperandInfo108 }, // Inst #895 = BEQZC_MM |
| { 894, 2, 0, 4, 1018, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, ImplicitList2, OperandInfo109 }, // Inst #894 = BEQZC64 |
| { 893, 2, 0, 2, 986, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList2, OperandInfo191 }, // Inst #893 = BEQZC16_MMR6 |
| { 892, 2, 0, 4, 932, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, ImplicitList2, OperandInfo108 }, // Inst #892 = BEQZC |
| { 891, 2, 0, 4, 1000, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, ImplicitList3, OperandInfo108 }, // Inst #891 = BEQZALC_MMR6 |
| { 890, 2, 0, 4, 927, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, ImplicitList3, OperandInfo108 }, // Inst #890 = BEQZALC |
| { 889, 2, 0, 2, 949, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList2, OperandInfo191 }, // Inst #889 = BEQZ16_MM |
| { 888, 3, 0, 4, 377, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, ImplicitList2, OperandInfo57 }, // Inst #888 = BEQL |
| { 887, 3, 0, 4, 985, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, ImplicitList2, OperandInfo57 }, // Inst #887 = BEQC_MMR6 |
| { 886, 3, 0, 4, 1017, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, ImplicitList2, OperandInfo106 }, // Inst #886 = BEQC64 |
| { 885, 3, 0, 4, 931, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, ImplicitList2, OperandInfo57 }, // Inst #885 = BEQC |
| { 884, 3, 0, 4, 1009, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, ImplicitList2, OperandInfo106 }, // Inst #884 = BEQ64 |
| { 883, 3, 0, 4, 920, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, ImplicitList2, OperandInfo57 }, // Inst #883 = BEQ |
| { 882, 1, 0, 4, 982, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x16ULL, nullptr, OperandInfo55 }, // Inst #882 = BC_MMR6 |
| { 881, 3, 1, 4, 521, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #881 = BCLR_W |
| { 880, 3, 1, 4, 521, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #880 = BCLR_H |
| { 879, 3, 1, 4, 521, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #879 = BCLR_D |
| { 878, 3, 1, 4, 521, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #878 = BCLR_B |
| { 877, 3, 1, 4, 521, 0, 0, 0, 0x6ULL, nullptr, OperandInfo179 }, // Inst #877 = BCLRI_W |
| { 876, 3, 1, 4, 521, 0, 0, 0, 0x6ULL, nullptr, OperandInfo178 }, // Inst #876 = BCLRI_H |
| { 875, 3, 1, 4, 521, 0, 0, 0, 0x6ULL, nullptr, OperandInfo177 }, // Inst #875 = BCLRI_D |
| { 874, 3, 1, 4, 521, 0, 0, 0, 0x6ULL, nullptr, OperandInfo176 }, // Inst #874 = BCLRI_B |
| { 873, 2, 0, 4, 984, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, ImplicitList2, OperandInfo190 }, // Inst #873 = BC2NEZC_MMR6 |
| { 872, 2, 0, 4, 930, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo190 }, // Inst #872 = BC2NEZ |
| { 871, 2, 0, 4, 984, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, ImplicitList2, OperandInfo190 }, // Inst #871 = BC2EQZC_MMR6 |
| { 870, 2, 0, 4, 930, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo190 }, // Inst #870 = BC2EQZ |
| { 869, 2, 0, 4, 948, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x45ULL, ImplicitList2, OperandInfo189 }, // Inst #869 = BC1T_MM |
| { 868, 2, 0, 4, 693, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x45ULL, ImplicitList2, OperandInfo189 }, // Inst #868 = BC1TL |
| { 867, 2, 0, 4, 692, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x45ULL, ImplicitList2, OperandInfo189 }, // Inst #867 = BC1T |
| { 866, 2, 0, 4, 983, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, ImplicitList2, OperandInfo188 }, // Inst #866 = BC1NEZC_MMR6 |
| { 865, 2, 0, 4, 1231, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo188 }, // Inst #865 = BC1NEZ |
| { 864, 2, 0, 4, 947, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x45ULL, ImplicitList2, OperandInfo189 }, // Inst #864 = BC1F_MM |
| { 863, 2, 0, 4, 691, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x45ULL, ImplicitList2, OperandInfo189 }, // Inst #863 = BC1FL |
| { 862, 2, 0, 4, 690, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x45ULL, ImplicitList2, OperandInfo189 }, // Inst #862 = BC1F |
| { 861, 2, 0, 4, 983, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, ImplicitList2, OperandInfo188 }, // Inst #861 = BC1EQZC_MMR6 |
| { 860, 2, 0, 4, 1231, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo188 }, // Inst #860 = BC1EQZ |
| { 859, 1, 0, 2, 982, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList2, OperandInfo55 }, // Inst #859 = BC16_MMR6 |
| { 858, 1, 0, 4, 929, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo55 }, // Inst #858 = BC |
| { 857, 3, 0, 4, 1199, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x2ULL, ImplicitList2, OperandInfo187 }, // Inst #857 = BBIT132 |
| { 856, 3, 0, 4, 1199, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x2ULL, ImplicitList2, OperandInfo187 }, // Inst #856 = BBIT1 |
| { 855, 3, 0, 4, 1199, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x2ULL, ImplicitList2, OperandInfo187 }, // Inst #855 = BBIT032 |
| { 854, 3, 0, 4, 1199, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x2ULL, ImplicitList2, OperandInfo187 }, // Inst #854 = BBIT0 |
| { 853, 4, 1, 4, 1634, 0, 0, 0, 0x6ULL, nullptr, OperandInfo182 }, // Inst #853 = BALIGN_MMR2 |
| { 852, 4, 1, 4, 1470, 0, 0, 0, 0x6ULL, nullptr, OperandInfo182 }, // Inst #852 = BALIGN |
| { 851, 1, 0, 4, 999, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, ImplicitList3, OperandInfo55 }, // Inst #851 = BALC_MMR6 |
| { 850, 1, 0, 4, 926, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, ImplicitList3, OperandInfo55 }, // Inst #850 = BALC |
| { 849, 1, 0, 4, 375, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, ImplicitList3, OperandInfo55 }, // Inst #849 = BAL |
| { 848, 3, 1, 4, 1198, 0, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, OperandInfo71 }, // Inst #848 = BADDu |
| { 847, 1, 0, 2, 945, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList2, OperandInfo55 }, // Inst #847 = B16_MM |
| { 846, 3, 1, 2, 735, 0, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, OperandInfo186 }, // Inst #846 = AndRxRxRy16 |
| { 845, 3, 1, 2, 735, 0, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, OperandInfo131 }, // Inst #845 = AdduRxRyRz16 |
| { 844, 1, 0, 4, 735, 1, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, OperandInfo2 }, // Inst #844 = AddiuSpImmX16 |
| { 843, 1, 0, 2, 735, 1, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, OperandInfo2 }, // Inst #843 = AddiuSpImm16 |
| { 842, 3, 1, 4, 735, 0, 0, 0, 0x0ULL, nullptr, OperandInfo185 }, // Inst #842 = AddiuRxRyOffMemX16 |
| { 841, 3, 1, 4, 735, 0, 0, 0|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, OperandInfo184 }, // Inst #841 = AddiuRxRxImmX16 |
| { 840, 3, 1, 2, 735, 0, 0, 0|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, OperandInfo184 }, // Inst #840 = AddiuRxRxImm16 |
| { 839, 2, 1, 4, 735, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo183 }, // Inst #839 = AddiuRxPcImmX16 |
| { 838, 2, 1, 4, 735, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo183 }, // Inst #838 = AddiuRxImmX16 |
| { 837, 3, 1, 4, 542, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo48 }, // Inst #837 = AVE_U_W |
| { 836, 3, 1, 4, 542, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo47 }, // Inst #836 = AVE_U_H |
| { 835, 3, 1, 4, 542, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo46 }, // Inst #835 = AVE_U_D |
| { 834, 3, 1, 4, 542, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo174 }, // Inst #834 = AVE_U_B |
| { 833, 3, 1, 4, 542, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo48 }, // Inst #833 = AVE_S_W |
| { 832, 3, 1, 4, 542, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo47 }, // Inst #832 = AVE_S_H |
| { 831, 3, 1, 4, 542, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo46 }, // Inst #831 = AVE_S_D |
| { 830, 3, 1, 4, 542, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo174 }, // Inst #830 = AVE_S_B |
| { 829, 3, 1, 4, 542, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo48 }, // Inst #829 = AVER_U_W |
| { 828, 3, 1, 4, 542, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo47 }, // Inst #828 = AVER_U_H |
| { 827, 3, 1, 4, 542, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo46 }, // Inst #827 = AVER_U_D |
| { 826, 3, 1, 4, 542, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo174 }, // Inst #826 = AVER_U_B |
| { 825, 3, 1, 4, 542, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo48 }, // Inst #825 = AVER_S_W |
| { 824, 3, 1, 4, 542, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo47 }, // Inst #824 = AVER_S_H |
| { 823, 3, 1, 4, 542, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo46 }, // Inst #823 = AVER_S_D |
| { 822, 3, 1, 4, 542, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo174 }, // Inst #822 = AVER_S_B |
| { 821, 3, 1, 4, 783, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo73 }, // Inst #821 = AUI_MMR6 |
| { 820, 2, 1, 4, 782, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo114 }, // Inst #820 = AUIPC_MMR6 |
| { 819, 2, 1, 4, 729, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo114 }, // Inst #819 = AUIPC |
| { 818, 3, 1, 4, 728, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo73 }, // Inst #818 = AUI |
| { 817, 3, 1, 4, 541, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #817 = ASUB_U_W |
| { 816, 3, 1, 4, 541, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #816 = ASUB_U_H |
| { 815, 3, 1, 4, 541, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #815 = ASUB_U_D |
| { 814, 3, 1, 4, 541, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #814 = ASUB_U_B |
| { 813, 3, 1, 4, 541, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #813 = ASUB_S_W |
| { 812, 3, 1, 4, 541, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #812 = ASUB_S_H |
| { 811, 3, 1, 4, 541, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #811 = ASUB_S_D |
| { 810, 3, 1, 4, 541, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #810 = ASUB_S_B |
| { 809, 4, 1, 4, 1633, 0, 0, 0, 0x6ULL, nullptr, OperandInfo182 }, // Inst #809 = APPEND_MMR2 |
| { 808, 4, 1, 4, 1469, 0, 0, 0, 0x6ULL, nullptr, OperandInfo182 }, // Inst #808 = APPEND |
| { 807, 3, 1, 4, 743, 0, 0, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, OperandInfo73 }, // Inst #807 = ANDi_MM |
| { 806, 3, 1, 4, 806, 0, 0, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, OperandInfo70 }, // Inst #806 = ANDi64 |
| { 805, 3, 1, 4, 499, 0, 0, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, OperandInfo73 }, // Inst #805 = ANDi |
| { 804, 3, 1, 4, 548, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #804 = AND_V |
| { 803, 3, 1, 4, 780, 0, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, OperandInfo72 }, // Inst #803 = AND_MMR6 |
| { 802, 3, 1, 4, 742, 0, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, OperandInfo72 }, // Inst #802 = AND_MM |
| { 801, 3, 1, 4, 781, 0, 0, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, OperandInfo73 }, // Inst #801 = ANDI_MMR6 |
| { 800, 3, 1, 4, 549, 0, 0, 0, 0x6ULL, nullptr, OperandInfo176 }, // Inst #800 = ANDI_B |
| { 799, 3, 1, 2, 780, 0, 0, 0, 0x0ULL, nullptr, OperandInfo170 }, // Inst #799 = ANDI16_MMR6 |
| { 798, 3, 1, 2, 742, 0, 0, 0, 0x0ULL, nullptr, OperandInfo170 }, // Inst #798 = ANDI16_MM |
| { 797, 3, 1, 4, 806, 0, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, OperandInfo71 }, // Inst #797 = AND64 |
| { 796, 3, 1, 2, 780, 0, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo181 }, // Inst #796 = AND16_MMR6 |
| { 795, 3, 1, 2, 742, 0, 0, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo181 }, // Inst #795 = AND16_MM |
| { 794, 3, 1, 4, 364, 0, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, OperandInfo72 }, // Inst #794 = AND |
| { 793, 2, 1, 4, 779, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo114 }, // Inst #793 = ALUIPC_MMR6 |
| { 792, 2, 1, 4, 727, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo114 }, // Inst #792 = ALUIPC |
| { 791, 4, 1, 4, 778, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo180 }, // Inst #791 = ALIGN_MMR6 |
| { 790, 4, 1, 4, 726, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo180 }, // Inst #790 = ALIGN |
| { 789, 3, 1, 4, 739, 0, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, OperandInfo72 }, // Inst #789 = ADDu_MM |
| { 788, 3, 1, 4, 509, 0, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, OperandInfo72 }, // Inst #788 = ADDu |
| { 787, 3, 1, 4, 738, 0, 0, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, OperandInfo73 }, // Inst #787 = ADDiu_MM |
| { 786, 3, 1, 4, 498, 0, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2ULL, nullptr, OperandInfo73 }, // Inst #786 = ADDiu |
| { 785, 3, 1, 4, 741, 0, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo73 }, // Inst #785 = ADDi_MM |
| { 784, 3, 1, 4, 497, 0, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo73 }, // Inst #784 = ADDi |
| { 783, 3, 1, 4, 777, 0, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, OperandInfo72 }, // Inst #783 = ADD_MMR6 |
| { 782, 3, 1, 4, 740, 0, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, OperandInfo72 }, // Inst #782 = ADD_MM |
| { 781, 3, 1, 4, 538, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo48 }, // Inst #781 = ADD_A_W |
| { 780, 3, 1, 4, 538, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo47 }, // Inst #780 = ADD_A_H |
| { 779, 3, 1, 4, 538, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo46 }, // Inst #779 = ADD_A_D |
| { 778, 3, 1, 4, 538, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo174 }, // Inst #778 = ADD_A_B |
| { 777, 3, 1, 4, 1516, 1, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList10, OperandInfo72 }, // Inst #777 = ADDWC_MM |
| { 776, 3, 1, 4, 1365, 1, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList10, OperandInfo72 }, // Inst #776 = ADDWC |
| { 775, 3, 1, 4, 540, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo48 }, // Inst #775 = ADDV_W |
| { 774, 3, 1, 4, 540, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo47 }, // Inst #774 = ADDV_H |
| { 773, 3, 1, 4, 540, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo46 }, // Inst #773 = ADDV_D |
| { 772, 3, 1, 4, 540, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo174 }, // Inst #772 = ADDV_B |
| { 771, 3, 1, 4, 540, 0, 0, 0, 0x6ULL, nullptr, OperandInfo179 }, // Inst #771 = ADDVI_W |
| { 770, 3, 1, 4, 540, 0, 0, 0, 0x6ULL, nullptr, OperandInfo178 }, // Inst #770 = ADDVI_H |
| { 769, 3, 1, 4, 540, 0, 0, 0, 0x6ULL, nullptr, OperandInfo177 }, // Inst #769 = ADDVI_D |
| { 768, 3, 1, 4, 540, 0, 0, 0, 0x6ULL, nullptr, OperandInfo176 }, // Inst #768 = ADDVI_B |
| { 767, 3, 1, 4, 1515, 0, 1, 0|(1ULL<<MCID::Commutable), 0x6ULL, ImplicitList8, OperandInfo172 }, // Inst #767 = ADDU_S_QB_MM |
| { 766, 3, 1, 4, 1364, 0, 1, 0|(1ULL<<MCID::Commutable), 0x6ULL, ImplicitList8, OperandInfo172 }, // Inst #766 = ADDU_S_QB |
| { 765, 3, 1, 4, 1632, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList8, OperandInfo172 }, // Inst #765 = ADDU_S_PH_MMR2 |
| { 764, 3, 1, 4, 1468, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList8, OperandInfo172 }, // Inst #764 = ADDU_S_PH |
| { 763, 3, 1, 4, 1514, 0, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList8, OperandInfo172 }, // Inst #763 = ADDU_QB_MM |
| { 762, 3, 1, 4, 1363, 0, 1, 0|(1ULL<<MCID::Commutable), 0x6ULL, ImplicitList8, OperandInfo172 }, // Inst #762 = ADDU_QB |
| { 761, 3, 1, 4, 1631, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList8, OperandInfo172 }, // Inst #761 = ADDU_PH_MMR2 |
| { 760, 3, 1, 4, 1467, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList8, OperandInfo172 }, // Inst #760 = ADDU_PH |
| { 759, 3, 1, 4, 776, 0, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, OperandInfo72 }, // Inst #759 = ADDU_MMR6 |
| { 758, 3, 1, 4, 1630, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo172 }, // Inst #758 = ADDUH_R_QB_MMR2 |
| { 757, 3, 1, 4, 1466, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo172 }, // Inst #757 = ADDUH_R_QB |
| { 756, 3, 1, 4, 1629, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo172 }, // Inst #756 = ADDUH_QB_MMR2 |
| { 755, 3, 1, 4, 1465, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo172 }, // Inst #755 = ADDUH_QB |
| { 754, 3, 1, 2, 776, 0, 0, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo175 }, // Inst #754 = ADDU16_MMR6 |
| { 753, 3, 1, 2, 739, 0, 0, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo175 }, // Inst #753 = ADDU16_MM |
| { 752, 3, 1, 4, 539, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo48 }, // Inst #752 = ADDS_U_W |
| { 751, 3, 1, 4, 539, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo47 }, // Inst #751 = ADDS_U_H |
| { 750, 3, 1, 4, 539, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo46 }, // Inst #750 = ADDS_U_D |
| { 749, 3, 1, 4, 539, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo174 }, // Inst #749 = ADDS_U_B |
| { 748, 3, 1, 4, 539, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo48 }, // Inst #748 = ADDS_S_W |
| { 747, 3, 1, 4, 539, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo47 }, // Inst #747 = ADDS_S_H |
| { 746, 3, 1, 4, 539, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo46 }, // Inst #746 = ADDS_S_D |
| { 745, 3, 1, 4, 539, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo174 }, // Inst #745 = ADDS_S_B |
| { 744, 3, 1, 4, 539, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo48 }, // Inst #744 = ADDS_A_W |
| { 743, 3, 1, 4, 539, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo47 }, // Inst #743 = ADDS_A_H |
| { 742, 3, 1, 4, 539, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo46 }, // Inst #742 = ADDS_A_D |
| { 741, 3, 1, 4, 539, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo174 }, // Inst #741 = ADDS_A_B |
| { 740, 3, 1, 4, 1513, 0, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList9, OperandInfo72 }, // Inst #740 = ADDSC_MM |
| { 739, 3, 1, 4, 1362, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList9, OperandInfo72 }, // Inst #739 = ADDSC |
| { 738, 3, 1, 4, 1211, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo173 }, // Inst #738 = ADDR_PS64 |
| { 737, 3, 1, 4, 1512, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList8, OperandInfo72 }, // Inst #737 = ADDQ_S_W_MM |
| { 736, 3, 1, 4, 1361, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList8, OperandInfo72 }, // Inst #736 = ADDQ_S_W |
| { 735, 3, 1, 4, 1511, 0, 1, 0|(1ULL<<MCID::Commutable), 0x6ULL, ImplicitList8, OperandInfo172 }, // Inst #735 = ADDQ_S_PH_MM |
| { 734, 3, 1, 4, 1360, 0, 1, 0|(1ULL<<MCID::Commutable), 0x6ULL, ImplicitList8, OperandInfo172 }, // Inst #734 = ADDQ_S_PH |
| { 733, 3, 1, 4, 1510, 0, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList8, OperandInfo172 }, // Inst #733 = ADDQ_PH_MM |
| { 732, 3, 1, 4, 1359, 0, 1, 0|(1ULL<<MCID::Commutable), 0x6ULL, ImplicitList8, OperandInfo172 }, // Inst #732 = ADDQ_PH |
| { 731, 3, 1, 4, 1628, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo72 }, // Inst #731 = ADDQH_W_MMR2 |
| { 730, 3, 1, 4, 1464, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo72 }, // Inst #730 = ADDQH_W |
| { 729, 3, 1, 4, 1627, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo72 }, // Inst #729 = ADDQH_R_W_MMR2 |
| { 728, 3, 1, 4, 1463, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo72 }, // Inst #728 = ADDQH_R_W |
| { 727, 3, 1, 4, 1626, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo172 }, // Inst #727 = ADDQH_R_PH_MMR2 |
| { 726, 3, 1, 4, 1462, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo172 }, // Inst #726 = ADDQH_R_PH |
| { 725, 3, 1, 4, 1625, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo172 }, // Inst #725 = ADDQH_PH_MMR2 |
| { 724, 3, 1, 4, 1461, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo172 }, // Inst #724 = ADDQH_PH |
| { 723, 3, 1, 4, 775, 0, 0, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, OperandInfo73 }, // Inst #723 = ADDIU_MMR6 |
| { 722, 1, 0, 2, 738, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo2 }, // Inst #722 = ADDIUSP_MM |
| { 721, 3, 1, 2, 738, 0, 0, 0, 0x0ULL, nullptr, OperandInfo171 }, // Inst #721 = ADDIUS5_MM |
| { 720, 3, 1, 2, 738, 0, 0, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo170 }, // Inst #720 = ADDIUR2_MM |
| { 719, 2, 1, 2, 738, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo169 }, // Inst #719 = ADDIUR1SP_MM |
| { 718, 2, 1, 4, 774, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo114 }, // Inst #718 = ADDIUPC_MMR6 |
| { 717, 2, 1, 4, 738, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, OperandInfo169 }, // Inst #717 = ADDIUPC_MM |
| { 716, 2, 1, 4, 725, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo114 }, // Inst #716 = ADDIUPC |
| { 715, 3, 1, 4, 496, 0, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, OperandInfo72 }, // Inst #715 = ADD |
| { 714, 2, 1, 4, 1509, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList8, OperandInfo45 }, // Inst #714 = ABSQ_S_W_MM |
| { 713, 2, 1, 4, 1358, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList8, OperandInfo45 }, // Inst #713 = ABSQ_S_W |
| { 712, 2, 1, 4, 1624, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList8, OperandInfo168 }, // Inst #712 = ABSQ_S_QB_MMR2 |
| { 711, 2, 1, 4, 1460, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList8, OperandInfo168 }, // Inst #711 = ABSQ_S_QB |
| { 710, 2, 1, 4, 1508, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList8, OperandInfo168 }, // Inst #710 = ABSQ_S_PH_MM |
| { 709, 2, 1, 4, 1357, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList8, OperandInfo168 }, // Inst #709 = ABSQ_S_PH |
| { 708, 3, 1, 4, 550, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo48 }, // Inst #708 = XOR_V_W_PSEUDO |
| { 707, 3, 1, 4, 550, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo47 }, // Inst #707 = XOR_V_H_PSEUDO |
| { 706, 3, 1, 4, 550, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo46 }, // Inst #706 = XOR_V_D_PSEUDO |
| { 705, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo96 }, // Inst #705 = Usw |
| { 704, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo96 }, // Inst #704 = Ush |
| { 703, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo96 }, // Inst #703 = Ulw |
| { 702, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo96 }, // Inst #702 = Ulhu |
| { 701, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo96 }, // Inst #701 = Ulh |
| { 700, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo72 }, // Inst #700 = URemMacro |
| { 699, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo73 }, // Inst #699 = URemIMacro |
| { 698, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo72 }, // Inst #698 = UDivMacro |
| { 697, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo73 }, // Inst #697 = UDivIMacro |
| { 696, 3, 1, 4, 886, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo142 }, // Inst #696 = UDIV_MM_Pseudo |
| { 695, 0, 0, 4, 981, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Trap)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #695 = TRAP_MM |
| { 694, 0, 0, 4, 402, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Trap)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #694 = TRAP |
| { 693, 1, 0, 4, 1006, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, ImplicitList2, OperandInfo2 }, // Inst #693 = TAILCALL_MMR6 |
| { 692, 1, 0, 4, 964, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, ImplicitList2, OperandInfo2 }, // Inst #692 = TAILCALL_MM |
| { 691, 1, 0, 4, 1005, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, ImplicitList2, OperandInfo58 }, // Inst #691 = TAILCALLREG_MMR6 |
| { 690, 1, 0, 4, 963, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, ImplicitList2, OperandInfo58 }, // Inst #690 = TAILCALLREG_MM |
| { 689, 1, 0, 4, 1015, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, ImplicitList2, OperandInfo95 }, // Inst #689 = TAILCALLREGHB64 |
| { 688, 1, 0, 4, 385, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, ImplicitList2, OperandInfo58 }, // Inst #688 = TAILCALLREGHB |
| { 687, 1, 0, 4, 1015, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, ImplicitList2, OperandInfo95 }, // Inst #687 = TAILCALLREG64 |
| { 686, 1, 0, 4, 385, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, ImplicitList2, OperandInfo58 }, // Inst #686 = TAILCALLREG |
| { 685, 1, 0, 4, 937, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, ImplicitList2, OperandInfo58 }, // Inst #685 = TAILCALLR6REG |
| { 684, 1, 0, 4, 937, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, ImplicitList2, OperandInfo58 }, // Inst #684 = TAILCALLHBR6REG |
| { 683, 1, 0, 4, 1023, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, ImplicitList2, OperandInfo95 }, // Inst #683 = TAILCALLHB64R6REG |
| { 682, 1, 0, 4, 1023, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, ImplicitList2, OperandInfo95 }, // Inst #682 = TAILCALL64R6REG |
| { 681, 1, 0, 4, 384, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, ImplicitList2, OperandInfo2 }, // Inst #681 = TAILCALL |
| { 680, 3, 1, 2, 736, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList7, OperandInfo131 }, // Inst #680 = SltuRxRyRz16 |
| { 679, 3, 1, 2, 736, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo131 }, // Inst #679 = SltuCCRxRy16 |
| { 678, 3, 1, 2, 736, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo167 }, // Inst #678 = SltiuCCRxImmX16 |
| { 677, 3, 1, 2, 736, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo167 }, // Inst #677 = SltiCCRxImmX16 |
| { 676, 3, 1, 2, 736, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo131 }, // Inst #676 = SltCCRxRy16 |
| { 675, 5, 1, 2, 944, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo165 }, // Inst #675 = SelTBtneZSltu |
| { 674, 5, 1, 2, 944, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo166 }, // Inst #674 = SelTBtneZSltiu |
| { 673, 5, 1, 2, 944, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo166 }, // Inst #673 = SelTBtneZSlti |
| { 672, 5, 1, 2, 944, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo165 }, // Inst #672 = SelTBtneZSlt |
| { 671, 5, 1, 2, 944, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo166 }, // Inst #671 = SelTBtneZCmpi |
| { 670, 5, 1, 2, 944, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo165 }, // Inst #670 = SelTBtneZCmp |
| { 669, 5, 1, 2, 944, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo165 }, // Inst #669 = SelTBteqZSltu |
| { 668, 5, 1, 2, 944, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo166 }, // Inst #668 = SelTBteqZSltiu |
| { 667, 5, 1, 2, 944, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo166 }, // Inst #667 = SelTBteqZSlti |
| { 666, 5, 1, 2, 944, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo165 }, // Inst #666 = SelTBteqZSlt |
| { 665, 5, 1, 2, 944, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo166 }, // Inst #665 = SelTBteqZCmpi |
| { 664, 5, 1, 2, 944, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo165 }, // Inst #664 = SelTBteqZCmp |
| { 663, 4, 1, 2, 944, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo164 }, // Inst #663 = SelBneZ |
| { 662, 4, 1, 2, 944, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo164 }, // Inst #662 = SelBeqZ |
| { 661, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo113 }, // Inst #661 = SaadAddr |
| { 660, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo113 }, // Inst #660 = SaaAddr |
| { 659, 2, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo163 }, // Inst #659 = SZ_W_PSEUDO |
| { 658, 2, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo160 }, // Inst #658 = SZ_V_PSEUDO |
| { 657, 2, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo162 }, // Inst #657 = SZ_H_PSEUDO |
| { 656, 2, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo161 }, // Inst #656 = SZ_D_PSEUDO |
| { 655, 2, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo160 }, // Inst #655 = SZ_B_PSEUDO |
| { 654, 3, 0, 4, 1136, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo110 }, // Inst #654 = SWM_MM |
| { 653, 3, 0, 4, 705, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo99 }, // Inst #653 = ST_F16 |
| { 652, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo98 }, // Inst #652 = STR_W |
| { 651, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo97 }, // Inst #651 = STR_D |
| { 650, 3, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo103 }, // Inst #650 = STORE_CCOND_DSP |
| { 649, 3, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo102 }, // Inst #649 = STORE_ACC64DSP |
| { 648, 3, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo101 }, // Inst #648 = STORE_ACC64 |
| { 647, 3, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo100 }, // Inst #647 = STORE_ACC128 |
| { 646, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo72 }, // Inst #646 = SRemMacro |
| { 645, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo73 }, // Inst #645 = SRemIMacro |
| { 644, 2, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo163 }, // Inst #644 = SNZ_W_PSEUDO |
| { 643, 2, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo160 }, // Inst #643 = SNZ_V_PSEUDO |
| { 642, 2, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo162 }, // Inst #642 = SNZ_H_PSEUDO |
| { 641, 2, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo161 }, // Inst #641 = SNZ_D_PSEUDO |
| { 640, 2, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo160 }, // Inst #640 = SNZ_B_PSEUDO |
| { 639, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo72 }, // Inst #639 = SNEMacro |
| { 638, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo73 }, // Inst #638 = SNEIMacro |
| { 637, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo70 }, // Inst #637 = SLTUImm64 |
| { 636, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo70 }, // Inst #636 = SLTImm64 |
| { 635, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo70 }, // Inst #635 = SLEUImm64 |
| { 634, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo73 }, // Inst #634 = SLEUImm |
| { 633, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo72 }, // Inst #633 = SLEU |
| { 632, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo70 }, // Inst #632 = SLEImm64 |
| { 631, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo73 }, // Inst #631 = SLEImm |
| { 630, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo72 }, // Inst #630 = SLE |
| { 629, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo70 }, // Inst #629 = SGTUImm64 |
| { 628, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo73 }, // Inst #628 = SGTUImm |
| { 627, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo70 }, // Inst #627 = SGTImm64 |
| { 626, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo73 }, // Inst #626 = SGTImm |
| { 625, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo70 }, // Inst #625 = SGEUImm64 |
| { 624, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo73 }, // Inst #624 = SGEUImm |
| { 623, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo72 }, // Inst #623 = SGEU |
| { 622, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo70 }, // Inst #622 = SGEImm64 |
| { 621, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo73 }, // Inst #621 = SGEImm |
| { 620, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo72 }, // Inst #620 = SGE |
| { 619, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo72 }, // Inst #619 = SEQMacro |
| { 618, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo73 }, // Inst #618 = SEQIMacro |
| { 617, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo159 }, // Inst #617 = SDivMacro |
| { 616, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo73 }, // Inst #616 = SDivIMacro |
| { 615, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo96 }, // Inst #615 = SDMacro |
| { 614, 3, 1, 4, 885, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo142 }, // Inst #614 = SDIV_MM_Pseudo |
| { 613, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo158 }, // Inst #613 = SDC1_M1 |
| { 612, 0, 0, 2, 940, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x0ULL, nullptr, nullptr }, // Inst #612 = RetRA16 |
| { 611, 0, 0, 4, 382, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr }, // Inst #611 = RetRA |
| { 610, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo73 }, // Inst #610 = RORImm |
| { 609, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo72 }, // Inst #609 = ROR |
| { 608, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo73 }, // Inst #608 = ROLImm |
| { 607, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo72 }, // Inst #607 = ROL |
| { 606, 3, 1, 4, 866, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo142 }, // Inst #606 = PseudoUDIV |
| { 605, 3, 1, 4, 1214, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo157 }, // Inst #605 = PseudoTRUNC_W_S |
| { 604, 3, 1, 4, 1214, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo156 }, // Inst #604 = PseudoTRUNC_W_D32 |
| { 603, 3, 1, 4, 1214, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo155 }, // Inst #603 = PseudoTRUNC_W_D |
| { 602, 4, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo154 }, // Inst #602 = PseudoSELECT_S |
| { 601, 4, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo153 }, // Inst #601 = PseudoSELECT_I64 |
| { 600, 4, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo152 }, // Inst #600 = PseudoSELECT_I |
| { 599, 4, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo151 }, // Inst #599 = PseudoSELECT_D64 |
| { 598, 4, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo150 }, // Inst #598 = PseudoSELECT_D32 |
| { 597, 4, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo149 }, // Inst #597 = PseudoSELECTFP_T_S |
| { 596, 4, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo148 }, // Inst #596 = PseudoSELECTFP_T_I64 |
| { 595, 4, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo147 }, // Inst #595 = PseudoSELECTFP_T_I |
| { 594, 4, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo146 }, // Inst #594 = PseudoSELECTFP_T_D64 |
| { 593, 4, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo145 }, // Inst #593 = PseudoSELECTFP_T_D32 |
| { 592, 4, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo149 }, // Inst #592 = PseudoSELECTFP_F_S |
| { 591, 4, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo148 }, // Inst #591 = PseudoSELECTFP_F_I64 |
| { 590, 4, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo147 }, // Inst #590 = PseudoSELECTFP_F_I |
| { 589, 4, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo146 }, // Inst #589 = PseudoSELECTFP_F_D64 |
| { 588, 4, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo145 }, // Inst #588 = PseudoSELECTFP_F_D32 |
| { 587, 3, 1, 4, 865, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo142 }, // Inst #587 = PseudoSDIV |
| { 586, 1, 0, 4, 1016, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, OperandInfo95 }, // Inst #586 = PseudoReturn64 |
| { 585, 1, 0, 4, 388, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, OperandInfo58 }, // Inst #585 = PseudoReturn |
| { 584, 4, 1, 4, 1459, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo144 }, // Inst #584 = PseudoPICK_QB |
| { 583, 4, 1, 4, 1459, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo144 }, // Inst #583 = PseudoPICK_PH |
| { 582, 3, 1, 4, 862, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo142 }, // Inst #582 = PseudoMULTu_MM |
| { 581, 3, 1, 4, 864, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo142 }, // Inst #581 = PseudoMULTu |
| { 580, 3, 1, 4, 861, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo142 }, // Inst #580 = PseudoMULT_MM |
| { 579, 3, 1, 4, 863, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo142 }, // Inst #579 = PseudoMULT |
| { 578, 3, 1, 4, 868, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo142 }, // Inst #578 = PseudoMTLOHI_MM |
| { 577, 3, 1, 4, 1344, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo143 }, // Inst #577 = PseudoMTLOHI_DSP |
| { 576, 3, 1, 4, 907, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo136 }, // Inst #576 = PseudoMTLOHI64 |
| { 575, 3, 1, 4, 493, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo142 }, // Inst #575 = PseudoMTLOHI |
| { 574, 4, 1, 4, 859, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo139 }, // Inst #574 = PseudoMSUB_MM |
| { 573, 4, 1, 4, 860, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo139 }, // Inst #573 = PseudoMSUBU_MM |
| { 572, 4, 1, 4, 492, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo139 }, // Inst #572 = PseudoMSUBU |
| { 571, 4, 1, 4, 491, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo139 }, // Inst #571 = PseudoMSUB |
| { 570, 2, 1, 4, 867, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo140 }, // Inst #570 = PseudoMFLO_MM |
| { 569, 2, 1, 4, 906, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo141 }, // Inst #569 = PseudoMFLO64 |
| { 568, 2, 1, 4, 478, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo140 }, // Inst #568 = PseudoMFLO |
| { 567, 2, 1, 4, 867, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo140 }, // Inst #567 = PseudoMFHI_MM |
| { 566, 2, 1, 4, 906, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo141 }, // Inst #566 = PseudoMFHI64 |
| { 565, 2, 1, 4, 478, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo140 }, // Inst #565 = PseudoMFHI |
| { 564, 4, 1, 4, 857, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo139 }, // Inst #564 = PseudoMADD_MM |
| { 563, 4, 1, 4, 858, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo139 }, // Inst #563 = PseudoMADDU_MM |
| { 562, 4, 1, 4, 490, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo139 }, // Inst #562 = PseudoMADDU |
| { 561, 4, 1, 4, 489, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo139 }, // Inst #561 = PseudoMADD |
| { 560, 1, 0, 4, 936, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, OperandInfo58 }, // Inst #560 = PseudoIndrectHazardBranchR6 |
| { 559, 1, 0, 4, 1024, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, OperandInfo95 }, // Inst #559 = PseudoIndrectHazardBranch64R6 |
| { 558, 1, 0, 4, 1020, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, OperandInfo95 }, // Inst #558 = PseudoIndirectHazardBranch64 |
| { 557, 1, 0, 4, 387, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, OperandInfo58 }, // Inst #557 = PseudoIndirectHazardBranch |
| { 556, 1, 0, 4, 998, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, OperandInfo58 }, // Inst #556 = PseudoIndirectBranch_MMR6 |
| { 555, 1, 0, 4, 965, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, OperandInfo58 }, // Inst #555 = PseudoIndirectBranch_MM |
| { 554, 1, 0, 4, 936, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, OperandInfo58 }, // Inst #554 = PseudoIndirectBranchR6 |
| { 553, 1, 0, 4, 1024, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, OperandInfo95 }, // Inst #553 = PseudoIndirectBranch64R6 |
| { 552, 1, 0, 4, 1020, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, OperandInfo95 }, // Inst #552 = PseudoIndirectBranch64 |
| { 551, 1, 0, 4, 387, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, OperandInfo58 }, // Inst #551 = PseudoIndirectBranch |
| { 550, 7, 2, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo138 }, // Inst #550 = PseudoD_SELECT_I64 |
| { 549, 7, 2, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo137 }, // Inst #549 = PseudoD_SELECT_I |
| { 548, 3, 1, 4, 905, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo136 }, // Inst #548 = PseudoDUDIV |
| { 547, 3, 1, 4, 904, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo136 }, // Inst #547 = PseudoDSDIV |
| { 546, 3, 1, 4, 903, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo136 }, // Inst #546 = PseudoDMULTu |
| { 545, 3, 1, 4, 902, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo136 }, // Inst #545 = PseudoDMULT |
| { 544, 2, 1, 4, 644, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x4ULL, nullptr, OperandInfo129 }, // Inst #544 = PseudoCVT_S_W |
| { 543, 2, 1, 4, 644, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x4ULL, nullptr, OperandInfo134 }, // Inst #543 = PseudoCVT_S_L |
| { 542, 2, 1, 4, 644, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x4ULL, nullptr, OperandInfo135 }, // Inst #542 = PseudoCVT_D64_W |
| { 541, 2, 1, 4, 644, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x4ULL, nullptr, OperandInfo134 }, // Inst #541 = PseudoCVT_D64_L |
| { 540, 2, 1, 4, 644, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x4ULL, nullptr, OperandInfo133 }, // Inst #540 = PseudoCVT_D32_W |
| { 539, 3, 1, 4, 1458, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo132 }, // Inst #539 = PseudoCMP_LT_PH |
| { 538, 3, 1, 4, 1458, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo132 }, // Inst #538 = PseudoCMP_LE_PH |
| { 537, 3, 1, 4, 1458, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo132 }, // Inst #537 = PseudoCMP_EQ_PH |
| { 536, 3, 1, 4, 1458, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo132 }, // Inst #536 = PseudoCMPU_LT_QB |
| { 535, 3, 1, 4, 1458, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo132 }, // Inst #535 = PseudoCMPU_LE_QB |
| { 534, 3, 1, 4, 1458, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo132 }, // Inst #534 = PseudoCMPU_EQ_QB |
| { 533, 3, 1, 4, 550, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo48 }, // Inst #533 = OR_V_W_PSEUDO |
| { 532, 3, 1, 4, 550, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo47 }, // Inst #532 = OR_V_H_PSEUDO |
| { 531, 3, 1, 4, 550, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo46 }, // Inst #531 = OR_V_D_PSEUDO |
| { 530, 3, 1, 4, 550, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo48 }, // Inst #530 = NOR_V_W_PSEUDO |
| { 529, 3, 1, 4, 550, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo47 }, // Inst #529 = NOR_V_H_PSEUDO |
| { 528, 3, 1, 4, 550, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo46 }, // Inst #528 = NOR_V_D_PSEUDO |
| { 527, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo70 }, // Inst #527 = NORImm64 |
| { 526, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo73 }, // Inst #526 = NORImm |
| { 525, 0, 0, 4, 373, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #525 = NOP |
| { 524, 3, 1, 2, 875, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList6, OperandInfo131 }, // Inst #524 = MultuRxRyRz16 |
| { 523, 2, 0, 2, 875, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList6, OperandInfo130 }, // Inst #523 = MultuRxRy16 |
| { 522, 3, 1, 2, 875, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList6, OperandInfo131 }, // Inst #522 = MultRxRyRz16 |
| { 521, 2, 0, 2, 875, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList6, OperandInfo130 }, // Inst #521 = MultRxRy16 |
| { 520, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo72 }, // Inst #520 = MULOUMacro |
| { 519, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo72 }, // Inst #519 = MULOMacro |
| { 518, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo73 }, // Inst #518 = MULImmMacro |
| { 517, 2, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo127 }, // Inst #517 = MTTLO |
| { 516, 2, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo127 }, // Inst #516 = MTTHI |
| { 515, 2, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo129 }, // Inst #515 = MTTHC1 |
| { 514, 2, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo45 }, // Inst #514 = MTTGPR |
| { 513, 1, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo58 }, // Inst #513 = MTTDSP |
| { 512, 2, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo129 }, // Inst #512 = MTTC1 |
| { 511, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo128 }, // Inst #511 = MTTC0 |
| { 510, 2, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo127 }, // Inst #510 = MTTACX |
| { 509, 2, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo126 }, // Inst #509 = MSA_FP_ROUND_W_PSEUDO |
| { 508, 2, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo125 }, // Inst #508 = MSA_FP_ROUND_D_PSEUDO |
| { 507, 2, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo124 }, // Inst #507 = MSA_FP_EXTEND_W_PSEUDO |
| { 506, 2, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo123 }, // Inst #506 = MSA_FP_EXTEND_D_PSEUDO |
| { 505, 2, 0, 4, 1, 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x10ULL, ImplicitList5, OperandInfo122 }, // Inst #505 = MIPSeh_return64 |
| { 504, 2, 0, 4, 1, 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x10ULL, ImplicitList5, OperandInfo45 }, // Inst #504 = MIPSeh_return32 |
| { 503, 2, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo119 }, // Inst #503 = MFTLO |
| { 502, 2, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo119 }, // Inst #502 = MFTHI |
| { 501, 2, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo121 }, // Inst #501 = MFTHC1 |
| { 500, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo73 }, // Inst #500 = MFTGPR |
| { 499, 1, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo58 }, // Inst #499 = MFTDSP |
| { 498, 2, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo121 }, // Inst #498 = MFTC1 |
| { 497, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo120 }, // Inst #497 = MFTC0 |
| { 496, 2, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo119 }, // Inst #496 = MFTACX |
| { 495, 3, 1, 2, 737, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo118 }, // Inst #495 = LwConstant32 |
| { 494, 2, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo114 }, // Inst #494 = LoadImmSingleGPR |
| { 493, 2, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo117 }, // Inst #493 = LoadImmSingleFGR |
| { 492, 2, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo114 }, // Inst #492 = LoadImmDoubleGPR |
| { 491, 2, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo116 }, // Inst #491 = LoadImmDoubleFGR_32 |
| { 490, 2, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo115 }, // Inst #490 = LoadImmDoubleFGR |
| { 489, 2, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo112 }, // Inst #489 = LoadImm64 |
| { 488, 2, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo114 }, // Inst #488 = LoadImm32 |
| { 487, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo113 }, // Inst #487 = LoadAddrReg64 |
| { 486, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo96 }, // Inst #486 = LoadAddrReg32 |
| { 485, 2, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo112 }, // Inst #485 = LoadAddrImm64 |
| { 484, 2, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo111 }, // Inst #484 = LoadAddrImm32 |
| { 483, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo110 }, // Inst #483 = LWM_MM |
| { 482, 2, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo109 }, // Inst #482 = LONG_BRANCH_LUi2Op_64 |
| { 481, 2, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo108 }, // Inst #481 = LONG_BRANCH_LUi2Op |
| { 480, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo107 }, // Inst #480 = LONG_BRANCH_LUi |
| { 479, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo106 }, // Inst #479 = LONG_BRANCH_DADDiu2Op |
| { 478, 4, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo105 }, // Inst #478 = LONG_BRANCH_DADDiu |
| { 477, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo57 }, // Inst #477 = LONG_BRANCH_ADDiu2Op |
| { 476, 4, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo104 }, // Inst #476 = LONG_BRANCH_ADDiu |
| { 475, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo103 }, // Inst #475 = LOAD_CCOND_DSP |
| { 474, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo102 }, // Inst #474 = LOAD_ACC64DSP |
| { 473, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo101 }, // Inst #473 = LOAD_ACC64 |
| { 472, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo100 }, // Inst #472 = LOAD_ACC128 |
| { 471, 3, 1, 4, 716, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo99 }, // Inst #471 = LD_F16 |
| { 470, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo98 }, // Inst #470 = LDR_W |
| { 469, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo97 }, // Inst #469 = LDR_D |
| { 468, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo96 }, // Inst #468 = LDMacro |
| { 467, 2, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo45 }, // Inst #467 = JalTwoReg |
| { 466, 1, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo58 }, // Inst #466 = JalOneReg |
| { 465, 1, 0, 4, 990, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x10ULL, ImplicitList3, OperandInfo2 }, // Inst #465 = JAL_MMR6 |
| { 464, 1, 0, 4, 407, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook), 0x10ULL, ImplicitList3, OperandInfo58 }, // Inst #464 = JALRPseudo |
| { 463, 1, 0, 4, 407, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook), 0x10ULL, ImplicitList3, OperandInfo58 }, // Inst #463 = JALRHBPseudo |
| { 462, 1, 0, 4, 1012, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook), 0x10ULL, ImplicitList3, OperandInfo95 }, // Inst #462 = JALRHB64Pseudo |
| { 461, 1, 0, 4, 1012, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook), 0x10ULL, ImplicitList3, OperandInfo95 }, // Inst #461 = JALR64Pseudo |
| { 460, 4, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo94 }, // Inst #460 = INSERT_W_VIDX_PSEUDO |
| { 459, 4, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo93 }, // Inst #459 = INSERT_W_VIDX64_PSEUDO |
| { 458, 4, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo92 }, // Inst #458 = INSERT_H_VIDX_PSEUDO |
| { 457, 4, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo91 }, // Inst #457 = INSERT_H_VIDX64_PSEUDO |
| { 456, 4, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo90 }, // Inst #456 = INSERT_FW_VIDX_PSEUDO |
| { 455, 4, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo89 }, // Inst #455 = INSERT_FW_VIDX64_PSEUDO |
| { 454, 4, 1, 4, 552, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo88 }, // Inst #454 = INSERT_FW_PSEUDO |
| { 453, 4, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo87 }, // Inst #453 = INSERT_FD_VIDX_PSEUDO |
| { 452, 4, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo86 }, // Inst #452 = INSERT_FD_VIDX64_PSEUDO |
| { 451, 4, 1, 4, 552, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo85 }, // Inst #451 = INSERT_FD_PSEUDO |
| { 450, 4, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo84 }, // Inst #450 = INSERT_D_VIDX_PSEUDO |
| { 449, 4, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo83 }, // Inst #449 = INSERT_D_VIDX64_PSEUDO |
| { 448, 4, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo82 }, // Inst #448 = INSERT_B_VIDX_PSEUDO |
| { 447, 4, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo81 }, // Inst #447 = INSERT_B_VIDX64_PSEUDO |
| { 446, 4, 2, 2, 737, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo80 }, // Inst #446 = GotPrologue16 |
| { 445, 2, 1, 4, 551, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo79 }, // Inst #445 = FILL_FW_PSEUDO |
| { 444, 2, 1, 4, 551, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo78 }, // Inst #444 = FILL_FD_PSEUDO |
| { 443, 2, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo77 }, // Inst #443 = FEXP2_W_1_PSEUDO |
| { 442, 2, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo76 }, // Inst #442 = FEXP2_D_1_PSEUDO |
| { 441, 2, 1, 4, 588, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo77 }, // Inst #441 = FABS_W |
| { 440, 2, 1, 4, 588, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo76 }, // Inst #440 = FABS_D |
| { 439, 3, 1, 4, 695, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo75 }, // Inst #439 = ExtractElementF64_64 |
| { 438, 3, 1, 4, 695, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo74 }, // Inst #438 = ExtractElementF64 |
| { 437, 0, 0, 4, 924, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr }, // Inst #437 = ERet |
| { 436, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo71 }, // Inst #436 = DURemMacro |
| { 435, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo70 }, // Inst #435 = DURemIMacro |
| { 434, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo71 }, // Inst #434 = DUDivMacro |
| { 433, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo70 }, // Inst #433 = DUDivIMacro |
| { 432, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo71 }, // Inst #432 = DSRemMacro |
| { 431, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo70 }, // Inst #431 = DSRemIMacro |
| { 430, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo71 }, // Inst #430 = DSDivMacro |
| { 429, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo70 }, // Inst #429 = DSDivIMacro |
| { 428, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo73 }, // Inst #428 = DRORImm |
| { 427, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo72 }, // Inst #427 = DROR |
| { 426, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo73 }, // Inst #426 = DROLImm |
| { 425, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo72 }, // Inst #425 = DROL |
| { 424, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo71 }, // Inst #424 = DMULOUMacro |
| { 423, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo71 }, // Inst #423 = DMULOMacro |
| { 422, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo71 }, // Inst #422 = DMULMacro |
| { 421, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo70 }, // Inst #421 = DMULImmMacro |
| { 420, 1, 0, 2, 737, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo2 }, // Inst #420 = Constant32 |
| { 419, 2, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo69 }, // Inst #419 = CTTC1 |
| { 418, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo68 }, // Inst #418 = COPY_FW_PSEUDO |
| { 417, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo67 }, // Inst #417 = COPY_FD_PSEUDO |
| { 416, 3, 0, 2, 737, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, OperandInfo4 }, // Inst #416 = CONSTPOOL_ENTRY |
| { 415, 2, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo66 }, // Inst #415 = CFTC1 |
| { 414, 3, 1, 4, 686, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo65 }, // Inst #414 = BuildPairF64_64 |
| { 413, 3, 1, 4, 686, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo64 }, // Inst #413 = BuildPairF64 |
| { 412, 3, 0, 2, 940, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo62 }, // Inst #412 = BtnezT8SltuX16 |
| { 411, 3, 0, 2, 940, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo63 }, // Inst #411 = BtnezT8SltiuX16 |
| { 410, 3, 0, 2, 940, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo63 }, // Inst #410 = BtnezT8SltiX16 |
| { 409, 3, 0, 2, 940, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo62 }, // Inst #409 = BtnezT8SltX16 |
| { 408, 3, 0, 2, 940, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo63 }, // Inst #408 = BtnezT8CmpiX16 |
| { 407, 3, 0, 2, 940, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo62 }, // Inst #407 = BtnezT8CmpX16 |
| { 406, 3, 0, 2, 940, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo62 }, // Inst #406 = BteqzT8SltuX16 |
| { 405, 3, 0, 2, 940, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo63 }, // Inst #405 = BteqzT8SltiuX16 |
| { 404, 3, 0, 2, 940, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo63 }, // Inst #404 = BteqzT8SltiX16 |
| { 403, 3, 0, 2, 940, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo62 }, // Inst #403 = BteqzT8SltX16 |
| { 402, 3, 0, 2, 940, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo63 }, // Inst #402 = BteqzT8CmpiX16 |
| { 401, 3, 0, 2, 940, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo62 }, // Inst #401 = BteqzT8CmpX16 |
| { 400, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, OperandInfo56 }, // Inst #400 = BneImm |
| { 399, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, OperandInfo56 }, // Inst #399 = BeqImm |
| { 398, 1, 0, 4, 956, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo55 }, // Inst #398 = B_MM_Pseudo |
| { 397, 1, 0, 4, 997, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo55 }, // Inst #397 = B_MMR6_Pseudo |
| { 396, 1, 0, 4, 945, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, ImplicitList2, OperandInfo55 }, // Inst #396 = B_MM |
| { 395, 4, 1, 4, 525, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo60 }, // Inst #395 = BSEL_W_PSEUDO |
| { 394, 4, 1, 4, 525, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo61 }, // Inst #394 = BSEL_H_PSEUDO |
| { 393, 4, 1, 4, 525, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo60 }, // Inst #393 = BSEL_FW_PSEUDO |
| { 392, 4, 1, 4, 525, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo59 }, // Inst #392 = BSEL_FD_PSEUDO |
| { 391, 4, 1, 4, 525, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo59 }, // Inst #391 = BSEL_D_PSEUDO |
| { 390, 1, 1, 4, 1, 1, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList4, OperandInfo58 }, // Inst #390 = BPOSGE32_PSEUDO |
| { 389, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, OperandInfo56 }, // Inst #389 = BNELImmMacro |
| { 388, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, OperandInfo56 }, // Inst #388 = BLTULImmMacro |
| { 387, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, OperandInfo57 }, // Inst #387 = BLTUL |
| { 386, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, OperandInfo56 }, // Inst #386 = BLTUImmMacro |
| { 385, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, OperandInfo57 }, // Inst #385 = BLTU |
| { 384, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, OperandInfo56 }, // Inst #384 = BLTLImmMacro |
| { 383, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, OperandInfo57 }, // Inst #383 = BLTL |
| { 382, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, OperandInfo56 }, // Inst #382 = BLTImmMacro |
| { 381, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, OperandInfo57 }, // Inst #381 = BLT |
| { 380, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, OperandInfo56 }, // Inst #380 = BLEULImmMacro |
| { 379, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, OperandInfo57 }, // Inst #379 = BLEUL |
| { 378, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, OperandInfo56 }, // Inst #378 = BLEUImmMacro |
| { 377, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, OperandInfo57 }, // Inst #377 = BLEU |
| { 376, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, OperandInfo56 }, // Inst #376 = BLELImmMacro |
| { 375, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, OperandInfo57 }, // Inst #375 = BLEL |
| { 374, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, OperandInfo56 }, // Inst #374 = BLEImmMacro |
| { 373, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, OperandInfo57 }, // Inst #373 = BLE |
| { 372, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, OperandInfo56 }, // Inst #372 = BGTULImmMacro |
| { 371, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, OperandInfo57 }, // Inst #371 = BGTUL |
| { 370, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, OperandInfo56 }, // Inst #370 = BGTUImmMacro |
| { 369, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, OperandInfo57 }, // Inst #369 = BGTU |
| { 368, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, OperandInfo56 }, // Inst #368 = BGTLImmMacro |
| { 367, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, OperandInfo57 }, // Inst #367 = BGTL |
| { 366, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, OperandInfo56 }, // Inst #366 = BGTImmMacro |
| { 365, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, OperandInfo57 }, // Inst #365 = BGT |
| { 364, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, OperandInfo56 }, // Inst #364 = BGEULImmMacro |
| { 363, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, OperandInfo57 }, // Inst #363 = BGEUL |
| { 362, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, OperandInfo56 }, // Inst #362 = BGEUImmMacro |
| { 361, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, OperandInfo57 }, // Inst #361 = BGEU |
| { 360, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, OperandInfo56 }, // Inst #360 = BGELImmMacro |
| { 359, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, OperandInfo57 }, // Inst #359 = BGEL |
| { 358, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, OperandInfo56 }, // Inst #358 = BGEImmMacro |
| { 357, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, OperandInfo57 }, // Inst #357 = BGE |
| { 356, 3, 0, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, OperandInfo56 }, // Inst #356 = BEQLImmMacro |
| { 355, 1, 0, 4, 946, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, ImplicitList3, OperandInfo55 }, // Inst #355 = BAL_BR_MM |
| { 354, 1, 0, 4, 919, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, ImplicitList3, OperandInfo55 }, // Inst #354 = BAL_BR |
| { 353, 1, 0, 4, 374, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, ImplicitList2, OperandInfo55 }, // Inst #353 = B |
| { 352, 6, 1, 4, 721, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo53 }, // Inst #352 = ATOMIC_SWAP_I8_POSTRA |
| { 351, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo52 }, // Inst #351 = ATOMIC_SWAP_I8 |
| { 350, 3, 1, 4, 721, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo54 }, // Inst #350 = ATOMIC_SWAP_I64_POSTRA |
| { 349, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo54 }, // Inst #349 = ATOMIC_SWAP_I64 |
| { 348, 3, 1, 4, 721, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo52 }, // Inst #348 = ATOMIC_SWAP_I32_POSTRA |
| { 347, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo52 }, // Inst #347 = ATOMIC_SWAP_I32 |
| { 346, 6, 1, 4, 721, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo53 }, // Inst #346 = ATOMIC_SWAP_I16_POSTRA |
| { 345, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo52 }, // Inst #345 = ATOMIC_SWAP_I16 |
| { 344, 6, 1, 4, 723, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo53 }, // Inst #344 = ATOMIC_LOAD_XOR_I8_POSTRA |
| { 343, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo52 }, // Inst #343 = ATOMIC_LOAD_XOR_I8 |
| { 342, 3, 1, 4, 723, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo54 }, // Inst #342 = ATOMIC_LOAD_XOR_I64_POSTRA |
| { 341, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo54 }, // Inst #341 = ATOMIC_LOAD_XOR_I64 |
| { 340, 3, 1, 4, 723, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo52 }, // Inst #340 = ATOMIC_LOAD_XOR_I32_POSTRA |
| { 339, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo52 }, // Inst #339 = ATOMIC_LOAD_XOR_I32 |
| { 338, 6, 1, 4, 723, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo53 }, // Inst #338 = ATOMIC_LOAD_XOR_I16_POSTRA |
| { 337, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo52 }, // Inst #337 = ATOMIC_LOAD_XOR_I16 |
| { 336, 6, 1, 4, 723, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo53 }, // Inst #336 = ATOMIC_LOAD_UMIN_I8_POSTRA |
| { 335, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo52 }, // Inst #335 = ATOMIC_LOAD_UMIN_I8 |
| { 334, 3, 1, 4, 723, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo54 }, // Inst #334 = ATOMIC_LOAD_UMIN_I64_POSTRA |
| { 333, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo54 }, // Inst #333 = ATOMIC_LOAD_UMIN_I64 |
| { 332, 3, 1, 4, 723, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo52 }, // Inst #332 = ATOMIC_LOAD_UMIN_I32_POSTRA |
| { 331, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo52 }, // Inst #331 = ATOMIC_LOAD_UMIN_I32 |
| { 330, 6, 1, 4, 723, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo53 }, // Inst #330 = ATOMIC_LOAD_UMIN_I16_POSTRA |
| { 329, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo52 }, // Inst #329 = ATOMIC_LOAD_UMIN_I16 |
| { 328, 6, 1, 4, 723, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo53 }, // Inst #328 = ATOMIC_LOAD_UMAX_I8_POSTRA |
| { 327, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo52 }, // Inst #327 = ATOMIC_LOAD_UMAX_I8 |
| { 326, 3, 1, 4, 723, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo54 }, // Inst #326 = ATOMIC_LOAD_UMAX_I64_POSTRA |
| { 325, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo54 }, // Inst #325 = ATOMIC_LOAD_UMAX_I64 |
| { 324, 3, 1, 4, 723, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo52 }, // Inst #324 = ATOMIC_LOAD_UMAX_I32_POSTRA |
| { 323, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo52 }, // Inst #323 = ATOMIC_LOAD_UMAX_I32 |
| { 322, 6, 1, 4, 723, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo53 }, // Inst #322 = ATOMIC_LOAD_UMAX_I16_POSTRA |
| { 321, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo52 }, // Inst #321 = ATOMIC_LOAD_UMAX_I16 |
| { 320, 6, 1, 4, 723, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo53 }, // Inst #320 = ATOMIC_LOAD_SUB_I8_POSTRA |
| { 319, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo52 }, // Inst #319 = ATOMIC_LOAD_SUB_I8 |
| { 318, 3, 1, 4, 723, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo54 }, // Inst #318 = ATOMIC_LOAD_SUB_I64_POSTRA |
| { 317, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo54 }, // Inst #317 = ATOMIC_LOAD_SUB_I64 |
| { 316, 3, 1, 4, 723, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo52 }, // Inst #316 = ATOMIC_LOAD_SUB_I32_POSTRA |
| { 315, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo52 }, // Inst #315 = ATOMIC_LOAD_SUB_I32 |
| { 314, 6, 1, 4, 723, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo53 }, // Inst #314 = ATOMIC_LOAD_SUB_I16_POSTRA |
| { 313, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo52 }, // Inst #313 = ATOMIC_LOAD_SUB_I16 |
| { 312, 6, 1, 4, 723, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo53 }, // Inst #312 = ATOMIC_LOAD_OR_I8_POSTRA |
| { 311, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo52 }, // Inst #311 = ATOMIC_LOAD_OR_I8 |
| { 310, 3, 1, 4, 723, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo54 }, // Inst #310 = ATOMIC_LOAD_OR_I64_POSTRA |
| { 309, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo54 }, // Inst #309 = ATOMIC_LOAD_OR_I64 |
| { 308, 3, 1, 4, 723, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo52 }, // Inst #308 = ATOMIC_LOAD_OR_I32_POSTRA |
| { 307, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo52 }, // Inst #307 = ATOMIC_LOAD_OR_I32 |
| { 306, 6, 1, 4, 723, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo53 }, // Inst #306 = ATOMIC_LOAD_OR_I16_POSTRA |
| { 305, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo52 }, // Inst #305 = ATOMIC_LOAD_OR_I16 |
| { 304, 6, 1, 4, 723, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo53 }, // Inst #304 = ATOMIC_LOAD_NAND_I8_POSTRA |
| { 303, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo52 }, // Inst #303 = ATOMIC_LOAD_NAND_I8 |
| { 302, 3, 1, 4, 723, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo54 }, // Inst #302 = ATOMIC_LOAD_NAND_I64_POSTRA |
| { 301, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo54 }, // Inst #301 = ATOMIC_LOAD_NAND_I64 |
| { 300, 3, 1, 4, 723, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo52 }, // Inst #300 = ATOMIC_LOAD_NAND_I32_POSTRA |
| { 299, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo52 }, // Inst #299 = ATOMIC_LOAD_NAND_I32 |
| { 298, 6, 1, 4, 723, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo53 }, // Inst #298 = ATOMIC_LOAD_NAND_I16_POSTRA |
| { 297, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo52 }, // Inst #297 = ATOMIC_LOAD_NAND_I16 |
| { 296, 6, 1, 4, 723, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo53 }, // Inst #296 = ATOMIC_LOAD_MIN_I8_POSTRA |
| { 295, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo52 }, // Inst #295 = ATOMIC_LOAD_MIN_I8 |
| { 294, 3, 1, 4, 723, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo54 }, // Inst #294 = ATOMIC_LOAD_MIN_I64_POSTRA |
| { 293, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo54 }, // Inst #293 = ATOMIC_LOAD_MIN_I64 |
| { 292, 3, 1, 4, 723, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo52 }, // Inst #292 = ATOMIC_LOAD_MIN_I32_POSTRA |
| { 291, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo52 }, // Inst #291 = ATOMIC_LOAD_MIN_I32 |
| { 290, 6, 1, 4, 723, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo53 }, // Inst #290 = ATOMIC_LOAD_MIN_I16_POSTRA |
| { 289, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo52 }, // Inst #289 = ATOMIC_LOAD_MIN_I16 |
| { 288, 6, 1, 4, 723, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo53 }, // Inst #288 = ATOMIC_LOAD_MAX_I8_POSTRA |
| { 287, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo52 }, // Inst #287 = ATOMIC_LOAD_MAX_I8 |
| { 286, 3, 1, 4, 723, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo54 }, // Inst #286 = ATOMIC_LOAD_MAX_I64_POSTRA |
| { 285, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo54 }, // Inst #285 = ATOMIC_LOAD_MAX_I64 |
| { 284, 3, 1, 4, 723, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo52 }, // Inst #284 = ATOMIC_LOAD_MAX_I32_POSTRA |
| { 283, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo52 }, // Inst #283 = ATOMIC_LOAD_MAX_I32 |
| { 282, 6, 1, 4, 723, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo53 }, // Inst #282 = ATOMIC_LOAD_MAX_I16_POSTRA |
| { 281, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo52 }, // Inst #281 = ATOMIC_LOAD_MAX_I16 |
| { 280, 6, 1, 4, 723, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo53 }, // Inst #280 = ATOMIC_LOAD_AND_I8_POSTRA |
| { 279, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo52 }, // Inst #279 = ATOMIC_LOAD_AND_I8 |
| { 278, 3, 1, 4, 723, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo54 }, // Inst #278 = ATOMIC_LOAD_AND_I64_POSTRA |
| { 277, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo54 }, // Inst #277 = ATOMIC_LOAD_AND_I64 |
| { 276, 3, 1, 4, 723, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo52 }, // Inst #276 = ATOMIC_LOAD_AND_I32_POSTRA |
| { 275, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo52 }, // Inst #275 = ATOMIC_LOAD_AND_I32 |
| { 274, 6, 1, 4, 723, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo53 }, // Inst #274 = ATOMIC_LOAD_AND_I16_POSTRA |
| { 273, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo52 }, // Inst #273 = ATOMIC_LOAD_AND_I16 |
| { 272, 6, 1, 4, 723, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo53 }, // Inst #272 = ATOMIC_LOAD_ADD_I8_POSTRA |
| { 271, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo52 }, // Inst #271 = ATOMIC_LOAD_ADD_I8 |
| { 270, 3, 1, 4, 723, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo54 }, // Inst #270 = ATOMIC_LOAD_ADD_I64_POSTRA |
| { 269, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo54 }, // Inst #269 = ATOMIC_LOAD_ADD_I64 |
| { 268, 3, 1, 4, 723, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo52 }, // Inst #268 = ATOMIC_LOAD_ADD_I32_POSTRA |
| { 267, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo52 }, // Inst #267 = ATOMIC_LOAD_ADD_I32 |
| { 266, 6, 1, 4, 723, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo53 }, // Inst #266 = ATOMIC_LOAD_ADD_I16_POSTRA |
| { 265, 3, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo52 }, // Inst #265 = ATOMIC_LOAD_ADD_I16 |
| { 264, 7, 1, 4, 722, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo50 }, // Inst #264 = ATOMIC_CMP_SWAP_I8_POSTRA |
| { 263, 4, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo49 }, // Inst #263 = ATOMIC_CMP_SWAP_I8 |
| { 262, 4, 1, 4, 722, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo51 }, // Inst #262 = ATOMIC_CMP_SWAP_I64_POSTRA |
| { 261, 4, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo51 }, // Inst #261 = ATOMIC_CMP_SWAP_I64 |
| { 260, 4, 1, 4, 722, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo49 }, // Inst #260 = ATOMIC_CMP_SWAP_I32_POSTRA |
| { 259, 4, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo49 }, // Inst #259 = ATOMIC_CMP_SWAP_I32 |
| { 258, 7, 1, 4, 722, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo50 }, // Inst #258 = ATOMIC_CMP_SWAP_I16_POSTRA |
| { 257, 4, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, OperandInfo49 }, // Inst #257 = ATOMIC_CMP_SWAP_I16 |
| { 256, 3, 1, 4, 550, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo48 }, // Inst #256 = AND_V_W_PSEUDO |
| { 255, 3, 1, 4, 550, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo47 }, // Inst #255 = AND_V_H_PSEUDO |
| { 254, 3, 1, 4, 550, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo46 }, // Inst #254 = AND_V_D_PSEUDO |
| { 253, 2, 0, 4, 1, 1, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, OperandInfo10 }, // Inst #253 = ADJCALLSTACKUP |
| { 252, 2, 0, 4, 1, 1, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, OperandInfo10 }, // Inst #252 = ADJCALLSTACKDOWN |
| { 251, 2, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo45 }, // Inst #251 = ABSMacro |
| { 250, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo44 }, // Inst #250 = G_UBFX |
| { 249, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo44 }, // Inst #249 = G_SBFX |
| { 248, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #248 = G_VECREDUCE_UMIN |
| { 247, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #247 = G_VECREDUCE_UMAX |
| { 246, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #246 = G_VECREDUCE_SMIN |
| { 245, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #245 = G_VECREDUCE_SMAX |
| { 244, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #244 = G_VECREDUCE_XOR |
| { 243, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #243 = G_VECREDUCE_OR |
| { 242, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #242 = G_VECREDUCE_AND |
| { 241, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #241 = G_VECREDUCE_MUL |
| { 240, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #240 = G_VECREDUCE_ADD |
| { 239, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #239 = G_VECREDUCE_FMIN |
| { 238, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #238 = G_VECREDUCE_FMAX |
| { 237, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #237 = G_VECREDUCE_FMUL |
| { 236, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #236 = G_VECREDUCE_FADD |
| { 235, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo40 }, // Inst #235 = G_VECREDUCE_SEQ_FMUL |
| { 234, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo40 }, // Inst #234 = G_VECREDUCE_SEQ_FADD |
| { 233, 3, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo22 }, // Inst #233 = G_BZERO |
| { 232, 4, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo43 }, // Inst #232 = G_MEMSET |
| { 231, 4, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo43 }, // Inst #231 = G_MEMMOVE |
| { 230, 3, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo40 }, // Inst #230 = G_MEMCPY_INLINE |
| { 229, 4, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo43 }, // Inst #229 = G_MEMCPY |
| { 228, 2, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, OperandInfo42 }, // Inst #228 = G_WRITE_REGISTER |
| { 227, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, OperandInfo21 }, // Inst #227 = G_READ_REGISTER |
| { 226, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo25 }, // Inst #226 = G_STRICT_FSQRT |
| { 225, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo19 }, // Inst #225 = G_STRICT_FMA |
| { 224, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo18 }, // Inst #224 = G_STRICT_FREM |
| { 223, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo18 }, // Inst #223 = G_STRICT_FDIV |
| { 222, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo18 }, // Inst #222 = G_STRICT_FMUL |
| { 221, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo18 }, // Inst #221 = G_STRICT_FSUB |
| { 220, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo18 }, // Inst #220 = G_STRICT_FADD |
| { 219, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo26 }, // Inst #219 = G_DYN_STACKALLOC |
| { 218, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo21 }, // Inst #218 = G_JUMP_TABLE |
| { 217, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo21 }, // Inst #217 = G_BLOCK_ADDR |
| { 216, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #216 = G_ADDRSPACE_CAST |
| { 215, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #215 = G_FNEARBYINT |
| { 214, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #214 = G_FRINT |
| { 213, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #213 = G_FFLOOR |
| { 212, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #212 = G_FSQRT |
| { 211, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #211 = G_FSIN |
| { 210, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #210 = G_FCOS |
| { 209, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #209 = G_FCEIL |
| { 208, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #208 = G_BITREVERSE |
| { 207, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #207 = G_BSWAP |
| { 206, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #206 = G_CTPOP |
| { 205, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #205 = G_CTLZ_ZERO_UNDEF |
| { 204, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #204 = G_CTLZ |
| { 203, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #203 = G_CTTZ_ZERO_UNDEF |
| { 202, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #202 = G_CTTZ |
| { 201, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo41 }, // Inst #201 = G_SHUFFLE_VECTOR |
| { 200, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo40 }, // Inst #200 = G_EXTRACT_VECTOR_ELT |
| { 199, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo39 }, // Inst #199 = G_INSERT_VECTOR_ELT |
| { 198, 3, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, OperandInfo38 }, // Inst #198 = G_BRJT |
| { 197, 1, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, OperandInfo2 }, // Inst #197 = G_BR |
| { 196, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #196 = G_LLROUND |
| { 195, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #195 = G_LROUND |
| { 194, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #194 = G_ABS |
| { 193, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #193 = G_UMAX |
| { 192, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #192 = G_UMIN |
| { 191, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #191 = G_SMAX |
| { 190, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #190 = G_SMIN |
| { 189, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo33 }, // Inst #189 = G_PTRMASK |
| { 188, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo33 }, // Inst #188 = G_PTR_ADD |
| { 187, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #187 = G_FMAXIMUM |
| { 186, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #186 = G_FMINIMUM |
| { 185, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #185 = G_FMAXNUM_IEEE |
| { 184, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #184 = G_FMINNUM_IEEE |
| { 183, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #183 = G_FMAXNUM |
| { 182, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #182 = G_FMINNUM |
| { 181, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #181 = G_FCANONICALIZE |
| { 180, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo32 }, // Inst #180 = G_IS_FPCLASS |
| { 179, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo33 }, // Inst #179 = G_FCOPYSIGN |
| { 178, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #178 = G_FABS |
| { 177, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #177 = G_UITOFP |
| { 176, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #176 = G_SITOFP |
| { 175, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #175 = G_FPTOUI |
| { 174, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #174 = G_FPTOSI |
| { 173, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #173 = G_FPTRUNC |
| { 172, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #172 = G_FPEXT |
| { 171, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #171 = G_FNEG |
| { 170, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #170 = G_FLOG10 |
| { 169, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #169 = G_FLOG2 |
| { 168, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #168 = G_FLOG |
| { 167, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #167 = G_FEXP2 |
| { 166, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #166 = G_FEXP |
| { 165, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo33 }, // Inst #165 = G_FPOWI |
| { 164, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo18 }, // Inst #164 = G_FPOW |
| { 163, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo18 }, // Inst #163 = G_FREM |
| { 162, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo18 }, // Inst #162 = G_FDIV |
| { 161, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo19 }, // Inst #161 = G_FMAD |
| { 160, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo19 }, // Inst #160 = G_FMA |
| { 159, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #159 = G_FMUL |
| { 158, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo18 }, // Inst #158 = G_FSUB |
| { 157, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #157 = G_FADD |
| { 156, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo37 }, // Inst #156 = G_UDIVFIXSAT |
| { 155, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo37 }, // Inst #155 = G_SDIVFIXSAT |
| { 154, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo37 }, // Inst #154 = G_UDIVFIX |
| { 153, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo37 }, // Inst #153 = G_SDIVFIX |
| { 152, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo37 }, // Inst #152 = G_UMULFIXSAT |
| { 151, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo37 }, // Inst #151 = G_SMULFIXSAT |
| { 150, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo37 }, // Inst #150 = G_UMULFIX |
| { 149, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo37 }, // Inst #149 = G_SMULFIX |
| { 148, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo33 }, // Inst #148 = G_SSHLSAT |
| { 147, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo33 }, // Inst #147 = G_USHLSAT |
| { 146, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo18 }, // Inst #146 = G_SSUBSAT |
| { 145, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo18 }, // Inst #145 = G_USUBSAT |
| { 144, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #144 = G_SADDSAT |
| { 143, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #143 = G_UADDSAT |
| { 142, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #142 = G_SMULH |
| { 141, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #141 = G_UMULH |
| { 140, 4, 2, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo30 }, // Inst #140 = G_SMULO |
| { 139, 4, 2, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo30 }, // Inst #139 = G_UMULO |
| { 138, 5, 2, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo36 }, // Inst #138 = G_SSUBE |
| { 137, 4, 2, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo30 }, // Inst #137 = G_SSUBO |
| { 136, 5, 2, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo36 }, // Inst #136 = G_SADDE |
| { 135, 4, 2, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo30 }, // Inst #135 = G_SADDO |
| { 134, 5, 2, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo36 }, // Inst #134 = G_USUBE |
| { 133, 4, 2, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo30 }, // Inst #133 = G_USUBO |
| { 132, 5, 2, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo36 }, // Inst #132 = G_UADDE |
| { 131, 4, 2, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo30 }, // Inst #131 = G_UADDO |
| { 130, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo30 }, // Inst #130 = G_SELECT |
| { 129, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo35 }, // Inst #129 = G_FCMP |
| { 128, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo35 }, // Inst #128 = G_ICMP |
| { 127, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo33 }, // Inst #127 = G_ROTL |
| { 126, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo33 }, // Inst #126 = G_ROTR |
| { 125, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo34 }, // Inst #125 = G_FSHR |
| { 124, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo34 }, // Inst #124 = G_FSHL |
| { 123, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo33 }, // Inst #123 = G_ASHR |
| { 122, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo33 }, // Inst #122 = G_LSHR |
| { 121, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo33 }, // Inst #121 = G_SHL |
| { 120, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #120 = G_ZEXT |
| { 119, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo17 }, // Inst #119 = G_SEXT_INREG |
| { 118, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #118 = G_SEXT |
| { 117, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo32 }, // Inst #117 = G_VAARG |
| { 116, 1, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo20 }, // Inst #116 = G_VASTART |
| { 115, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo21 }, // Inst #115 = G_FCONSTANT |
| { 114, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo21 }, // Inst #114 = G_CONSTANT |
| { 113, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #113 = G_TRUNC |
| { 112, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #112 = G_ANYEXT |
| { 111, 1, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, OperandInfo2 }, // Inst #111 = G_INTRINSIC_W_SIDE_EFFECTS |
| { 110, 1, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, OperandInfo2 }, // Inst #110 = G_INTRINSIC |
| { 109, 0, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr }, // Inst #109 = G_INVOKE_REGION_START |
| { 108, 1, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, OperandInfo20 }, // Inst #108 = G_BRINDIRECT |
| { 107, 2, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, OperandInfo21 }, // Inst #107 = G_BRCOND |
| { 106, 2, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo10 }, // Inst #106 = G_FENCE |
| { 105, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo31 }, // Inst #105 = G_ATOMICRMW_UDEC_WRAP |
| { 104, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo31 }, // Inst #104 = G_ATOMICRMW_UINC_WRAP |
| { 103, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo31 }, // Inst #103 = G_ATOMICRMW_FMIN |
| { 102, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo31 }, // Inst #102 = G_ATOMICRMW_FMAX |
| { 101, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo31 }, // Inst #101 = G_ATOMICRMW_FSUB |
| { 100, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo31 }, // Inst #100 = G_ATOMICRMW_FADD |
| { 99, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo31 }, // Inst #99 = G_ATOMICRMW_UMIN |
| { 98, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo31 }, // Inst #98 = G_ATOMICRMW_UMAX |
| { 97, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo31 }, // Inst #97 = G_ATOMICRMW_MIN |
| { 96, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo31 }, // Inst #96 = G_ATOMICRMW_MAX |
| { 95, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo31 }, // Inst #95 = G_ATOMICRMW_XOR |
| { 94, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo31 }, // Inst #94 = G_ATOMICRMW_OR |
| { 93, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo31 }, // Inst #93 = G_ATOMICRMW_NAND |
| { 92, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo31 }, // Inst #92 = G_ATOMICRMW_AND |
| { 91, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo31 }, // Inst #91 = G_ATOMICRMW_SUB |
| { 90, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo31 }, // Inst #90 = G_ATOMICRMW_ADD |
| { 89, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo31 }, // Inst #89 = G_ATOMICRMW_XCHG |
| { 88, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo30 }, // Inst #88 = G_ATOMIC_CMPXCHG |
| { 87, 5, 2, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo29 }, // Inst #87 = G_ATOMIC_CMPXCHG_WITH_SUCCESS |
| { 86, 5, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo28 }, // Inst #86 = G_INDEXED_STORE |
| { 85, 2, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo23 }, // Inst #85 = G_STORE |
| { 84, 5, 2, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo27 }, // Inst #84 = G_INDEXED_ZEXTLOAD |
| { 83, 5, 2, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo27 }, // Inst #83 = G_INDEXED_SEXTLOAD |
| { 82, 5, 2, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo27 }, // Inst #82 = G_INDEXED_LOAD |
| { 81, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo23 }, // Inst #81 = G_ZEXTLOAD |
| { 80, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo23 }, // Inst #80 = G_SEXTLOAD |
| { 79, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo23 }, // Inst #79 = G_LOAD |
| { 78, 1, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo20 }, // Inst #78 = G_READCYCLECOUNTER |
| { 77, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #77 = G_INTRINSIC_ROUNDEVEN |
| { 76, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #76 = G_INTRINSIC_LRINT |
| { 75, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #75 = G_INTRINSIC_ROUND |
| { 74, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #74 = G_INTRINSIC_TRUNC |
| { 73, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo26 }, // Inst #73 = G_INTRINSIC_FPTRUNC_ROUND |
| { 72, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo25 }, // Inst #72 = G_FREEZE |
| { 71, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #71 = G_BITCAST |
| { 70, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #70 = G_INTTOPTR |
| { 69, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo23 }, // Inst #69 = G_PTRTOINT |
| { 68, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, OperandInfo23 }, // Inst #68 = G_CONCAT_VECTORS |
| { 67, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, OperandInfo23 }, // Inst #67 = G_BUILD_VECTOR_TRUNC |
| { 66, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, OperandInfo23 }, // Inst #66 = G_BUILD_VECTOR |
| { 65, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, OperandInfo23 }, // Inst #65 = G_MERGE_VALUES |
| { 64, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo24 }, // Inst #64 = G_INSERT |
| { 63, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, OperandInfo23 }, // Inst #63 = G_UNMERGE_VALUES |
| { 62, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo22 }, // Inst #62 = G_EXTRACT |
| { 61, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo21 }, // Inst #61 = G_GLOBAL_VALUE |
| { 60, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo21 }, // Inst #60 = G_FRAME_INDEX |
| { 59, 1, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, OperandInfo20 }, // Inst #59 = G_PHI |
| { 58, 1, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo20 }, // Inst #58 = G_IMPLICIT_DEF |
| { 57, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #57 = G_XOR |
| { 56, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #56 = G_OR |
| { 55, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #55 = G_AND |
| { 54, 4, 2, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo19 }, // Inst #54 = G_UDIVREM |
| { 53, 4, 2, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo19 }, // Inst #53 = G_SDIVREM |
| { 52, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo18 }, // Inst #52 = G_UREM |
| { 51, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo18 }, // Inst #51 = G_SREM |
| { 50, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo18 }, // Inst #50 = G_UDIV |
| { 49, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo18 }, // Inst #49 = G_SDIV |
| { 48, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #48 = G_MUL |
| { 47, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo18 }, // Inst #47 = G_SUB |
| { 46, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo18 }, // Inst #46 = G_ADD |
| { 45, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo17 }, // Inst #45 = G_ASSERT_ALIGN |
| { 44, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo17 }, // Inst #44 = G_ASSERT_ZEXT |
| { 43, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo17 }, // Inst #43 = G_ASSERT_SEXT |
| { 42, 0, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #42 = MEMBARRIER |
| { 41, 0, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #41 = ICALL_BRANCH_FUNNEL |
| { 40, 3, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo16 }, // Inst #40 = PATCHABLE_TYPED_EVENT_CALL |
| { 39, 2, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo15 }, // Inst #39 = PATCHABLE_EVENT_CALL |
| { 38, 0, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #38 = PATCHABLE_TAIL_CALL |
| { 37, 0, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #37 = PATCHABLE_FUNCTION_EXIT |
| { 36, 0, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #36 = PATCHABLE_RET |
| { 35, 0, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #35 = PATCHABLE_FUNCTION_ENTER |
| { 34, 0, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #34 = PATCHABLE_OP |
| { 33, 1, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo2 }, // Inst #33 = FAULTING_OP |
| { 32, 2, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo14 }, // Inst #32 = LOCAL_ESCAPE |
| { 31, 0, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #31 = STATEPOINT |
| { 30, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo13 }, // Inst #30 = PREALLOCATED_ARG |
| { 29, 1, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo3 }, // Inst #29 = PREALLOCATED_SETUP |
| { 28, 1, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, OperandInfo12 }, // Inst #28 = LOAD_STACK_GUARD |
| { 27, 6, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo11 }, // Inst #27 = PATCHPOINT |
| { 26, 0, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #26 = FENTRY_CALL |
| { 25, 2, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo10 }, // Inst #25 = STACKMAP |
| { 24, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL, nullptr, OperandInfo9 }, // Inst #24 = ARITH_FENCE |
| { 23, 4, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo8 }, // Inst #23 = PSEUDO_PROBE |
| { 22, 1, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL, nullptr, OperandInfo3 }, // Inst #22 = LIFETIME_END |
| { 21, 1, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL, nullptr, OperandInfo3 }, // Inst #21 = LIFETIME_START |
| { 20, 0, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr }, // Inst #20 = BUNDLE |
| { 19, 2, 1, 0, 514, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, OperandInfo7 }, // Inst #19 = COPY |
| { 18, 2, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, OperandInfo7 }, // Inst #18 = REG_SEQUENCE |
| { 17, 1, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL, nullptr, OperandInfo2 }, // Inst #17 = DBG_LABEL |
| { 16, 0, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr }, // Inst #16 = DBG_PHI |
| { 15, 0, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr }, // Inst #15 = DBG_INSTR_REF |
| { 14, 0, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr }, // Inst #14 = DBG_VALUE_LIST |
| { 13, 0, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr }, // Inst #13 = DBG_VALUE |
| { 12, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, OperandInfo4 }, // Inst #12 = COPY_TO_REGCLASS |
| { 11, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo6 }, // Inst #11 = SUBREG_TO_REG |
| { 10, 1, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, OperandInfo2 }, // Inst #10 = IMPLICIT_DEF |
| { 9, 4, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo5 }, // Inst #9 = INSERT_SUBREG |
| { 8, 3, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, OperandInfo4 }, // Inst #8 = EXTRACT_SUBREG |
| { 7, 0, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr }, // Inst #7 = KILL |
| { 6, 1, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, OperandInfo3 }, // Inst #6 = ANNOTATION_LABEL |
| { 5, 1, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, OperandInfo3 }, // Inst #5 = GC_LABEL |
| { 4, 1, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, OperandInfo3 }, // Inst #4 = EH_LABEL |
| { 3, 1, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, OperandInfo3 }, // Inst #3 = CFI_INSTRUCTION |
| { 2, 0, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #2 = INLINEASM_BR |
| { 1, 0, 0, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr }, // Inst #1 = INLINEASM |
| { 0, 1, 1, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, OperandInfo2 }, // Inst #0 = PHI |
| }; |
| |
| extern const char MipsInstrNameData[] = { |
| /* 0 */ 'G', '_', 'F', 'L', 'O', 'G', '1', '0', 0, |
| /* 9 */ 'D', 'M', 'F', 'C', '0', 0, |
| /* 15 */ 'D', 'M', 'F', 'G', 'C', '0', 0, |
| /* 22 */ 'M', 'F', 'H', 'G', 'C', '0', 0, |
| /* 29 */ 'M', 'T', 'H', 'G', 'C', '0', 0, |
| /* 36 */ 'D', 'M', 'T', 'G', 'C', '0', 0, |
| /* 43 */ 'M', 'F', 'T', 'C', '0', 0, |
| /* 49 */ 'D', 'M', 'T', 'C', '0', 0, |
| /* 55 */ 'M', 'T', 'T', 'C', '0', 0, |
| /* 61 */ 'V', 'M', 'M', '0', 0, |
| /* 66 */ 'M', 'T', 'M', '0', 0, |
| /* 71 */ 'M', 'T', 'P', '0', 0, |
| /* 76 */ 'B', 'B', 'I', 'T', '0', 0, |
| /* 82 */ 'L', 'D', 'C', '1', 0, |
| /* 87 */ 'S', 'D', 'C', '1', 0, |
| /* 92 */ 'C', 'F', 'C', '1', 0, |
| /* 97 */ 'D', 'M', 'F', 'C', '1', 0, |
| /* 103 */ 'M', 'F', 'T', 'H', 'C', '1', 0, |
| /* 110 */ 'M', 'T', 'T', 'H', 'C', '1', 0, |
| /* 117 */ 'C', 'T', 'C', '1', 0, |
| /* 122 */ 'C', 'F', 'T', 'C', '1', 0, |
| /* 128 */ 'M', 'F', 'T', 'C', '1', 0, |
| /* 134 */ 'D', 'M', 'T', 'C', '1', 0, |
| /* 140 */ 'C', 'T', 'T', 'C', '1', 0, |
| /* 146 */ 'M', 'T', 'T', 'C', '1', 0, |
| /* 152 */ 'L', 'W', 'C', '1', 0, |
| /* 157 */ 'S', 'W', 'C', '1', 0, |
| /* 162 */ 'L', 'D', 'X', 'C', '1', 0, |
| /* 168 */ 'S', 'D', 'X', 'C', '1', 0, |
| /* 174 */ 'L', 'U', 'X', 'C', '1', 0, |
| /* 180 */ 'S', 'U', 'X', 'C', '1', 0, |
| /* 186 */ 'L', 'W', 'X', 'C', '1', 0, |
| /* 192 */ 'S', 'W', 'X', 'C', '1', 0, |
| /* 198 */ 'M', 'T', 'M', '1', 0, |
| /* 203 */ 'S', 'D', 'C', '1', '_', 'M', '1', 0, |
| /* 211 */ 'M', 'T', 'P', '1', 0, |
| /* 216 */ 'B', 'B', 'I', 'T', '1', 0, |
| /* 222 */ 'B', 'B', 'I', 'T', '0', '3', '2', 0, |
| /* 230 */ 'B', 'B', 'I', 'T', '1', '3', '2', 0, |
| /* 238 */ 'D', 'S', 'R', 'A', '3', '2', 0, |
| /* 245 */ 'M', 'F', 'H', 'C', '1', '_', 'D', '3', '2', 0, |
| /* 255 */ 'M', 'T', 'H', 'C', '1', '_', 'D', '3', '2', 0, |
| /* 265 */ 'F', 'S', 'U', 'B', '_', 'D', '3', '2', 0, |
| /* 274 */ 'N', 'M', 'S', 'U', 'B', '_', 'D', '3', '2', 0, |
| /* 284 */ 'F', 'A', 'D', 'D', '_', 'D', '3', '2', 0, |
| /* 293 */ 'N', 'M', 'A', 'D', 'D', '_', 'D', '3', '2', 0, |
| /* 303 */ 'C', '_', 'N', 'G', 'E', '_', 'D', '3', '2', 0, |
| /* 313 */ 'C', '_', 'N', 'G', 'L', 'E', '_', 'D', '3', '2', 0, |
| /* 324 */ 'C', '_', 'O', 'L', 'E', '_', 'D', '3', '2', 0, |
| /* 334 */ 'C', '_', 'U', 'L', 'E', '_', 'D', '3', '2', 0, |
| /* 344 */ 'C', '_', 'L', 'E', '_', 'D', '3', '2', 0, |
| /* 353 */ 'C', '_', 'S', 'F', '_', 'D', '3', '2', 0, |
| /* 362 */ 'M', 'O', 'V', 'F', '_', 'D', '3', '2', 0, |
| /* 371 */ 'C', '_', 'F', '_', 'D', '3', '2', 0, |
| /* 379 */ 'P', 's', 'e', 'u', 'd', 'o', 'S', 'E', 'L', 'E', 'C', 'T', 'F', 'P', '_', 'F', '_', 'D', '3', '2', 0, |
| /* 400 */ 'F', 'N', 'E', 'G', '_', 'D', '3', '2', 0, |
| /* 409 */ 'M', 'O', 'V', 'N', '_', 'I', '_', 'D', '3', '2', 0, |
| /* 420 */ 'M', 'O', 'V', 'Z', '_', 'I', '_', 'D', '3', '2', 0, |
| /* 431 */ 'C', '_', 'N', 'G', 'L', '_', 'D', '3', '2', 0, |
| /* 441 */ 'F', 'M', 'U', 'L', '_', 'D', '3', '2', 0, |
| /* 450 */ 'L', 'D', 'C', '1', '_', 'M', 'M', '_', 'D', '3', '2', 0, |
| /* 462 */ 'S', 'D', 'C', '1', '_', 'M', 'M', '_', 'D', '3', '2', 0, |
| /* 474 */ 'C', '_', 'U', 'N', '_', 'D', '3', '2', 0, |
| /* 483 */ 'R', 'E', 'C', 'I', 'P', '_', 'D', '3', '2', 0, |
| /* 493 */ 'F', 'C', 'M', 'P', '_', 'D', '3', '2', 0, |
| /* 502 */ 'C', '_', 'S', 'E', 'Q', '_', 'D', '3', '2', 0, |
| /* 512 */ 'C', '_', 'U', 'E', 'Q', '_', 'D', '3', '2', 0, |
| /* 522 */ 'C', '_', 'E', 'Q', '_', 'D', '3', '2', 0, |
| /* 531 */ 'F', 'A', 'B', 'S', '_', 'D', '3', '2', 0, |
| /* 540 */ 'C', 'V', 'T', '_', 'S', '_', 'D', '3', '2', 0, |
| /* 550 */ 'P', 's', 'e', 'u', 'd', 'o', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'D', '3', '2', 0, |
| /* 567 */ 'C', '_', 'N', 'G', 'T', '_', 'D', '3', '2', 0, |
| /* 577 */ 'C', '_', 'O', 'L', 'T', '_', 'D', '3', '2', 0, |
| /* 587 */ 'C', '_', 'U', 'L', 'T', '_', 'D', '3', '2', 0, |
| /* 597 */ 'C', '_', 'L', 'T', '_', 'D', '3', '2', 0, |
| /* 606 */ 'F', 'S', 'Q', 'R', 'T', '_', 'D', '3', '2', 0, |
| /* 616 */ 'R', 'S', 'Q', 'R', 'T', '_', 'D', '3', '2', 0, |
| /* 626 */ 'M', 'O', 'V', 'T', '_', 'D', '3', '2', 0, |
| /* 635 */ 'P', 's', 'e', 'u', 'd', 'o', 'S', 'E', 'L', 'E', 'C', 'T', 'F', 'P', '_', 'T', '_', 'D', '3', '2', 0, |
| /* 656 */ 'F', 'D', 'I', 'V', '_', 'D', '3', '2', 0, |
| /* 665 */ 'F', 'M', 'O', 'V', '_', 'D', '3', '2', 0, |
| /* 674 */ 'P', 's', 'e', 'u', 'd', 'o', 'T', 'R', 'U', 'N', 'C', '_', 'W', '_', 'D', '3', '2', 0, |
| /* 692 */ 'R', 'O', 'U', 'N', 'D', '_', 'W', '_', 'D', '3', '2', 0, |
| /* 704 */ 'C', 'E', 'I', 'L', '_', 'W', '_', 'D', '3', '2', 0, |
| /* 715 */ 'F', 'L', 'O', 'O', 'R', '_', 'W', '_', 'D', '3', '2', 0, |
| /* 727 */ 'C', 'V', 'T', '_', 'W', '_', 'D', '3', '2', 0, |
| /* 737 */ 'B', 'P', 'O', 'S', 'G', 'E', '3', '2', 0, |
| /* 746 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'S', 'U', 'B', '_', 'I', '3', '2', 0, |
| /* 766 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'A', 'D', 'D', '_', 'I', '3', '2', 0, |
| /* 786 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'N', 'A', 'N', 'D', '_', 'I', '3', '2', 0, |
| /* 807 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'A', 'N', 'D', '_', 'I', '3', '2', 0, |
| /* 827 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'U', 'M', 'I', 'N', '_', 'I', '3', '2', 0, |
| /* 848 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'M', 'I', 'N', '_', 'I', '3', '2', 0, |
| /* 868 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'S', 'W', 'A', 'P', '_', 'I', '3', '2', 0, |
| /* 884 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'C', 'M', 'P', '_', 'S', 'W', 'A', 'P', '_', 'I', '3', '2', 0, |
| /* 904 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'X', 'O', 'R', '_', 'I', '3', '2', 0, |
| /* 924 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'O', 'R', '_', 'I', '3', '2', 0, |
| /* 943 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'U', 'M', 'A', 'X', '_', 'I', '3', '2', 0, |
| /* 964 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'M', 'A', 'X', '_', 'I', '3', '2', 0, |
| /* 984 */ 'D', 'S', 'L', 'L', '3', '2', 0, |
| /* 991 */ 'D', 'S', 'R', 'L', '3', '2', 0, |
| /* 998 */ 'D', 'R', 'O', 'T', 'R', '3', '2', 0, |
| /* 1006 */ 'C', 'I', 'N', 'S', '3', '2', 0, |
| /* 1013 */ 'E', 'X', 'T', 'S', '3', '2', 0, |
| /* 1020 */ 'F', 'C', 'M', 'P', '_', 'S', '3', '2', 0, |
| /* 1029 */ 'D', 'S', 'L', 'L', '6', '4', '_', '3', '2', 0, |
| /* 1039 */ 'C', 'I', 'N', 'S', '6', '4', '_', '3', '2', 0, |
| /* 1049 */ 'D', 'E', 'X', 'T', '6', '4', '_', '3', '2', 0, |
| /* 1059 */ 'L', 'o', 'a', 'd', 'I', 'm', 'm', 'D', 'o', 'u', 'b', 'l', 'e', 'F', 'G', 'R', '_', '3', '2', 0, |
| /* 1079 */ 'L', 'o', 'a', 'd', 'A', 'd', 'd', 'r', 'R', 'e', 'g', '3', '2', 0, |
| /* 1093 */ 'C', 'I', 'N', 'S', '_', 'i', '3', '2', 0, |
| /* 1102 */ 'L', 'o', 'a', 'd', 'I', 'm', 'm', '3', '2', 0, |
| /* 1112 */ 'L', 'o', 'a', 'd', 'A', 'd', 'd', 'r', 'I', 'm', 'm', '3', '2', 0, |
| /* 1126 */ 'M', 'I', 'P', 'S', 'e', 'h', '_', 'r', 'e', 't', 'u', 'r', 'n', '3', '2', 0, |
| /* 1142 */ 'L', 'w', 'C', 'o', 'n', 's', 't', 'a', 'n', 't', '3', '2', 0, |
| /* 1155 */ 'L', 'D', 'C', '2', 0, |
| /* 1160 */ 'S', 'D', 'C', '2', 0, |
| /* 1165 */ 'D', 'M', 'F', 'C', '2', 0, |
| /* 1171 */ 'D', 'M', 'T', 'C', '2', 0, |
| /* 1177 */ 'L', 'W', 'C', '2', 0, |
| /* 1182 */ 'S', 'W', 'C', '2', 0, |
| /* 1187 */ 'G', '_', 'F', 'L', 'O', 'G', '2', 0, |
| /* 1195 */ 'M', 'T', 'M', '2', 0, |
| /* 1200 */ 'M', 'T', 'P', '2', 0, |
| /* 1205 */ 'G', '_', 'F', 'E', 'X', 'P', '2', 0, |
| /* 1213 */ 'S', 'H', 'R', 'A', '_', 'Q', 'B', '_', 'M', 'M', 'R', '2', 0, |
| /* 1226 */ 'C', 'M', 'P', 'G', 'D', 'U', '_', 'L', 'E', '_', 'Q', 'B', '_', 'M', 'M', 'R', '2', 0, |
| /* 1244 */ 'S', 'U', 'B', 'U', 'H', '_', 'Q', 'B', '_', 'M', 'M', 'R', '2', 0, |
| /* 1258 */ 'A', 'D', 'D', 'U', 'H', '_', 'Q', 'B', '_', 'M', 'M', 'R', '2', 0, |
| /* 1272 */ 'C', 'M', 'P', 'G', 'D', 'U', '_', 'E', 'Q', '_', 'Q', 'B', '_', 'M', 'M', 'R', '2', 0, |
| /* 1290 */ 'S', 'H', 'R', 'A', '_', 'R', '_', 'Q', 'B', '_', 'M', 'M', 'R', '2', 0, |
| /* 1305 */ 'S', 'U', 'B', 'U', 'H', '_', 'R', '_', 'Q', 'B', '_', 'M', 'M', 'R', '2', 0, |
| /* 1321 */ 'A', 'D', 'D', 'U', 'H', '_', 'R', '_', 'Q', 'B', '_', 'M', 'M', 'R', '2', 0, |
| /* 1337 */ 'S', 'H', 'R', 'A', 'V', '_', 'R', '_', 'Q', 'B', '_', 'M', 'M', 'R', '2', 0, |
| /* 1353 */ 'A', 'B', 'S', 'Q', '_', 'S', '_', 'Q', 'B', '_', 'M', 'M', 'R', '2', 0, |
| /* 1368 */ 'C', 'M', 'P', 'G', 'D', 'U', '_', 'L', 'T', '_', 'Q', 'B', '_', 'M', 'M', 'R', '2', 0, |
| /* 1386 */ 'S', 'H', 'R', 'A', 'V', '_', 'Q', 'B', '_', 'M', 'M', 'R', '2', 0, |
| /* 1400 */ 'P', 'R', 'E', 'P', 'E', 'N', 'D', '_', 'M', 'M', 'R', '2', 0, |
| /* 1413 */ 'A', 'P', 'P', 'E', 'N', 'D', '_', 'M', 'M', 'R', '2', 0, |
| /* 1425 */ 'P', 'R', 'E', 'C', 'R', '_', 'Q', 'B', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0, |
| /* 1442 */ 'S', 'U', 'B', 'Q', 'H', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0, |
| /* 1456 */ 'A', 'D', 'D', 'Q', 'H', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0, |
| /* 1470 */ 'S', 'H', 'R', 'L', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0, |
| /* 1483 */ 'M', 'U', 'L', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0, |
| /* 1495 */ 'S', 'U', 'B', 'Q', 'H', '_', 'R', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0, |
| /* 1511 */ 'A', 'D', 'D', 'Q', 'H', '_', 'R', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0, |
| /* 1527 */ 'M', 'U', 'L', '_', 'S', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0, |
| /* 1541 */ 'M', 'U', 'L', 'Q', '_', 'S', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0, |
| /* 1556 */ 'S', 'U', 'B', 'U', '_', 'S', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0, |
| /* 1571 */ 'A', 'D', 'D', 'U', '_', 'S', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0, |
| /* 1586 */ 'S', 'U', 'B', 'U', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0, |
| /* 1599 */ 'A', 'D', 'D', 'U', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0, |
| /* 1612 */ 'S', 'H', 'R', 'L', 'V', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0, |
| /* 1626 */ 'D', 'P', 'A', '_', 'W', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0, |
| /* 1640 */ 'M', 'U', 'L', 'S', 'A', '_', 'W', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0, |
| /* 1656 */ 'D', 'P', 'A', 'Q', 'X', '_', 'S', 'A', '_', 'W', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0, |
| /* 1675 */ 'D', 'P', 'S', 'Q', 'X', '_', 'S', 'A', '_', 'W', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0, |
| /* 1694 */ 'D', 'P', 'S', '_', 'W', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0, |
| /* 1708 */ 'D', 'P', 'A', 'Q', 'X', '_', 'S', '_', 'W', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0, |
| /* 1726 */ 'D', 'P', 'S', 'Q', 'X', '_', 'S', '_', 'W', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0, |
| /* 1744 */ 'D', 'P', 'A', 'X', '_', 'W', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0, |
| /* 1759 */ 'D', 'P', 'S', 'X', '_', 'W', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0, |
| /* 1774 */ 'B', 'A', 'L', 'I', 'G', 'N', '_', 'M', 'M', 'R', '2', 0, |
| /* 1786 */ 'P', 'R', 'E', 'C', 'R', '_', 'S', 'R', 'A', '_', 'P', 'H', '_', 'W', '_', 'M', 'M', 'R', '2', 0, |
| /* 1806 */ 'P', 'R', 'E', 'C', 'R', '_', 'S', 'R', 'A', '_', 'R', '_', 'P', 'H', '_', 'W', '_', 'M', 'M', 'R', '2', 0, |
| /* 1828 */ 'S', 'U', 'B', 'Q', 'H', '_', 'W', '_', 'M', 'M', 'R', '2', 0, |
| /* 1841 */ 'A', 'D', 'D', 'Q', 'H', '_', 'W', '_', 'M', 'M', 'R', '2', 0, |
| /* 1854 */ 'S', 'U', 'B', 'Q', 'H', '_', 'R', '_', 'W', '_', 'M', 'M', 'R', '2', 0, |
| /* 1869 */ 'A', 'D', 'D', 'Q', 'H', '_', 'R', '_', 'W', '_', 'M', 'M', 'R', '2', 0, |
| /* 1884 */ 'M', 'U', 'L', 'Q', '_', 'R', 'S', '_', 'W', '_', 'M', 'M', 'R', '2', 0, |
| /* 1899 */ 'M', 'U', 'L', 'Q', '_', 'S', '_', 'W', '_', 'M', 'M', 'R', '2', 0, |
| /* 1913 */ 'L', 'D', 'C', '3', 0, |
| /* 1918 */ 'S', 'D', 'C', '3', 0, |
| /* 1923 */ 'L', 'W', 'C', '3', 0, |
| /* 1928 */ 'S', 'W', 'C', '3', 0, |
| /* 1933 */ 'B', 'P', 'O', 'S', 'G', 'E', '3', '2', 'C', '_', 'M', 'M', 'R', '3', 0, |
| /* 1948 */ 'L', 'D', 'C', '1', '6', '4', 0, |
| /* 1955 */ 'S', 'D', 'C', '1', '6', '4', 0, |
| /* 1962 */ 'L', 'D', 'X', 'C', '1', '6', '4', 0, |
| /* 1970 */ 'S', 'D', 'X', 'C', '1', '6', '4', 0, |
| /* 1978 */ 'L', 'U', 'X', 'C', '1', '6', '4', 0, |
| /* 1986 */ 'S', 'U', 'X', 'C', '1', '6', '4', 0, |
| /* 1994 */ 'S', 'E', 'B', '6', '4', 0, |
| /* 2000 */ 'T', 'A', 'I', 'L', 'C', 'A', 'L', 'L', 'R', 'E', 'G', 'H', 'B', '6', '4', 0, |
| /* 2016 */ 'J', 'R', '_', 'H', 'B', '6', '4', 0, |
| /* 2024 */ 'J', 'A', 'L', 'R', '_', 'H', 'B', '6', '4', 0, |
| /* 2034 */ 'L', 'B', '6', '4', 0, |
| /* 2039 */ 'S', 'B', '6', '4', 0, |
| /* 2044 */ 'L', 'O', 'A', 'D', '_', 'A', 'C', 'C', '6', '4', 0, |
| /* 2055 */ 'S', 'T', 'O', 'R', 'E', '_', 'A', 'C', 'C', '6', '4', 0, |
| /* 2067 */ 'B', 'G', 'E', 'C', '6', '4', 0, |
| /* 2074 */ 'B', 'N', 'E', 'C', '6', '4', 0, |
| /* 2081 */ 'J', 'I', 'C', '6', '4', 0, |
| /* 2087 */ 'J', 'I', 'A', 'L', 'C', '6', '4', 0, |
| /* 2095 */ 'B', 'E', 'Q', 'C', '6', '4', 0, |
| /* 2102 */ 'S', 'C', '6', '4', 0, |
| /* 2107 */ 'B', 'L', 'T', 'C', '6', '4', 0, |
| /* 2114 */ 'B', 'G', 'E', 'U', 'C', '6', '4', 0, |
| /* 2122 */ 'B', 'L', 'T', 'U', 'C', '6', '4', 0, |
| /* 2130 */ 'B', 'G', 'E', 'Z', 'C', '6', '4', 0, |
| /* 2138 */ 'B', 'L', 'E', 'Z', 'C', '6', '4', 0, |
| /* 2146 */ 'B', 'N', 'E', 'Z', 'C', '6', '4', 0, |
| /* 2154 */ 'B', 'E', 'Q', 'Z', 'C', '6', '4', 0, |
| /* 2162 */ 'B', 'G', 'T', 'Z', 'C', '6', '4', 0, |
| /* 2170 */ 'B', 'L', 'T', 'Z', 'C', '6', '4', 0, |
| /* 2178 */ 'A', 'N', 'D', '6', '4', 0, |
| /* 2184 */ 'M', 'F', 'C', '1', '_', 'D', '6', '4', 0, |
| /* 2193 */ 'M', 'F', 'H', 'C', '1', '_', 'D', '6', '4', 0, |
| /* 2203 */ 'M', 'T', 'H', 'C', '1', '_', 'D', '6', '4', 0, |
| /* 2213 */ 'M', 'T', 'C', '1', '_', 'D', '6', '4', 0, |
| /* 2222 */ 'M', 'O', 'V', 'N', '_', 'I', '6', '4', '_', 'D', '6', '4', 0, |
| /* 2235 */ 'M', 'O', 'V', 'Z', '_', 'I', '6', '4', '_', 'D', '6', '4', 0, |
| /* 2248 */ 'F', 'S', 'U', 'B', '_', 'D', '6', '4', 0, |
| /* 2257 */ 'N', 'M', 'S', 'U', 'B', '_', 'D', '6', '4', 0, |
| /* 2267 */ 'F', 'A', 'D', 'D', '_', 'D', '6', '4', 0, |
| /* 2276 */ 'N', 'M', 'A', 'D', 'D', '_', 'D', '6', '4', 0, |
| /* 2286 */ 'C', '_', 'N', 'G', 'E', '_', 'D', '6', '4', 0, |
| /* 2296 */ 'C', '_', 'N', 'G', 'L', 'E', '_', 'D', '6', '4', 0, |
| /* 2307 */ 'C', '_', 'O', 'L', 'E', '_', 'D', '6', '4', 0, |
| /* 2317 */ 'C', '_', 'U', 'L', 'E', '_', 'D', '6', '4', 0, |
| /* 2327 */ 'C', '_', 'L', 'E', '_', 'D', '6', '4', 0, |
| /* 2336 */ 'C', '_', 'S', 'F', '_', 'D', '6', '4', 0, |
| /* 2345 */ 'M', 'O', 'V', 'F', '_', 'D', '6', '4', 0, |
| /* 2354 */ 'C', '_', 'F', '_', 'D', '6', '4', 0, |
| /* 2362 */ 'P', 's', 'e', 'u', 'd', 'o', 'S', 'E', 'L', 'E', 'C', 'T', 'F', 'P', '_', 'F', '_', 'D', '6', '4', 0, |
| /* 2383 */ 'F', 'N', 'E', 'G', '_', 'D', '6', '4', 0, |
| /* 2392 */ 'M', 'O', 'V', 'N', '_', 'I', '_', 'D', '6', '4', 0, |
| /* 2403 */ 'M', 'O', 'V', 'Z', '_', 'I', '_', 'D', '6', '4', 0, |
| /* 2414 */ 'C', '_', 'N', 'G', 'L', '_', 'D', '6', '4', 0, |
| /* 2424 */ 'F', 'M', 'U', 'L', '_', 'D', '6', '4', 0, |
| /* 2433 */ 'T', 'R', 'U', 'N', 'C', '_', 'L', '_', 'D', '6', '4', 0, |
| /* 2445 */ 'R', 'O', 'U', 'N', 'D', '_', 'L', '_', 'D', '6', '4', 0, |
| /* 2457 */ 'C', 'E', 'I', 'L', '_', 'L', '_', 'D', '6', '4', 0, |
| /* 2468 */ 'F', 'L', 'O', 'O', 'R', '_', 'L', '_', 'D', '6', '4', 0, |
| /* 2480 */ 'C', 'V', 'T', '_', 'L', '_', 'D', '6', '4', 0, |
| /* 2490 */ 'L', 'D', 'C', '1', '_', 'M', 'M', '_', 'D', '6', '4', 0, |
| /* 2502 */ 'S', 'D', 'C', '1', '_', 'M', 'M', '_', 'D', '6', '4', 0, |
| /* 2514 */ 'C', '_', 'U', 'N', '_', 'D', '6', '4', 0, |
| /* 2523 */ 'R', 'E', 'C', 'I', 'P', '_', 'D', '6', '4', 0, |
| /* 2533 */ 'F', 'C', 'M', 'P', '_', 'D', '6', '4', 0, |
| /* 2542 */ 'C', '_', 'S', 'E', 'Q', '_', 'D', '6', '4', 0, |
| /* 2552 */ 'C', '_', 'U', 'E', 'Q', '_', 'D', '6', '4', 0, |
| /* 2562 */ 'C', '_', 'E', 'Q', '_', 'D', '6', '4', 0, |
| /* 2571 */ 'F', 'A', 'B', 'S', '_', 'D', '6', '4', 0, |
| /* 2580 */ 'C', 'V', 'T', '_', 'S', '_', 'D', '6', '4', 0, |
| /* 2590 */ 'P', 's', 'e', 'u', 'd', 'o', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'D', '6', '4', 0, |
| /* 2607 */ 'C', '_', 'N', 'G', 'T', '_', 'D', '6', '4', 0, |
| /* 2617 */ 'C', '_', 'O', 'L', 'T', '_', 'D', '6', '4', 0, |
| /* 2627 */ 'C', '_', 'U', 'L', 'T', '_', 'D', '6', '4', 0, |
| /* 2637 */ 'C', '_', 'L', 'T', '_', 'D', '6', '4', 0, |
| /* 2646 */ 'F', 'S', 'Q', 'R', 'T', '_', 'D', '6', '4', 0, |
| /* 2656 */ 'R', 'S', 'Q', 'R', 'T', '_', 'D', '6', '4', 0, |
| /* 2666 */ 'M', 'O', 'V', 'T', '_', 'D', '6', '4', 0, |
| /* 2675 */ 'P', 's', 'e', 'u', 'd', 'o', 'S', 'E', 'L', 'E', 'C', 'T', 'F', 'P', '_', 'T', '_', 'D', '6', '4', 0, |
| /* 2696 */ 'F', 'D', 'I', 'V', '_', 'D', '6', '4', 0, |
| /* 2705 */ 'F', 'M', 'O', 'V', '_', 'D', '6', '4', 0, |
| /* 2714 */ 'T', 'R', 'U', 'N', 'C', '_', 'W', '_', 'D', '6', '4', 0, |
| /* 2726 */ 'R', 'O', 'U', 'N', 'D', '_', 'W', '_', 'D', '6', '4', 0, |
| /* 2738 */ 'C', 'E', 'I', 'L', '_', 'W', '_', 'D', '6', '4', 0, |
| /* 2749 */ 'F', 'L', 'O', 'O', 'R', '_', 'W', '_', 'D', '6', '4', 0, |
| /* 2761 */ 'C', 'V', 'T', '_', 'W', '_', 'D', '6', '4', 0, |
| /* 2771 */ 'B', 'N', 'E', '6', '4', 0, |
| /* 2777 */ 'B', 'u', 'i', 'l', 'd', 'P', 'a', 'i', 'r', 'F', '6', '4', 0, |
| /* 2790 */ 'E', 'x', 't', 'r', 'a', 'c', 't', 'E', 'l', 'e', 'm', 'e', 'n', 't', 'F', '6', '4', 0, |
| /* 2808 */ 'T', 'A', 'I', 'L', 'C', 'A', 'L', 'L', 'R', 'E', 'G', '6', '4', 0, |
| /* 2822 */ 'S', 'E', 'H', '6', '4', 0, |
| /* 2828 */ 'L', 'H', '6', '4', 0, |
| /* 2833 */ 'S', 'H', '6', '4', 0, |
| /* 2838 */ 'P', 's', 'e', 'u', 'd', 'o', 'M', 'F', 'H', 'I', '6', '4', 0, |
| /* 2851 */ 'P', 's', 'e', 'u', 'd', 'o', 'M', 'T', 'L', 'O', 'H', 'I', '6', '4', 0, |
| /* 2866 */ 'M', 'T', 'H', 'I', '6', '4', 0, |
| /* 2873 */ 'M', 'O', 'V', 'N', '_', 'I', '6', '4', '_', 'I', '6', '4', 0, |
| /* 2886 */ 'M', 'O', 'V', 'Z', '_', 'I', '6', '4', '_', 'I', '6', '4', 0, |
| /* 2899 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'S', 'U', 'B', '_', 'I', '6', '4', 0, |
| /* 2919 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'A', 'D', 'D', '_', 'I', '6', '4', 0, |
| /* 2939 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'N', 'A', 'N', 'D', '_', 'I', '6', '4', 0, |
| /* 2960 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'A', 'N', 'D', '_', 'I', '6', '4', 0, |
| /* 2980 */ 'M', 'O', 'V', 'F', '_', 'I', '6', '4', 0, |
| /* 2989 */ 'P', 's', 'e', 'u', 'd', 'o', 'S', 'E', 'L', 'E', 'C', 'T', 'F', 'P', '_', 'F', '_', 'I', '6', '4', 0, |
| /* 3010 */ 'M', 'O', 'V', 'N', '_', 'I', '_', 'I', '6', '4', 0, |
| /* 3021 */ 'M', 'O', 'V', 'Z', '_', 'I', '_', 'I', '6', '4', 0, |
| /* 3032 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'U', 'M', 'I', 'N', '_', 'I', '6', '4', 0, |
| /* 3053 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'M', 'I', 'N', '_', 'I', '6', '4', 0, |
| /* 3073 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'S', 'W', 'A', 'P', '_', 'I', '6', '4', 0, |
| /* 3089 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'C', 'M', 'P', '_', 'S', 'W', 'A', 'P', '_', 'I', '6', '4', 0, |
| /* 3109 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'X', 'O', 'R', '_', 'I', '6', '4', 0, |
| /* 3129 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'O', 'R', '_', 'I', '6', '4', 0, |
| /* 3148 */ 'P', 's', 'e', 'u', 'd', 'o', 'D', '_', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'I', '6', '4', 0, |
| /* 3167 */ 'P', 's', 'e', 'u', 'd', 'o', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'I', '6', '4', 0, |
| /* 3184 */ 'M', 'O', 'V', 'T', '_', 'I', '6', '4', 0, |
| /* 3193 */ 'P', 's', 'e', 'u', 'd', 'o', 'S', 'E', 'L', 'E', 'C', 'T', 'F', 'P', '_', 'T', '_', 'I', '6', '4', 0, |
| /* 3214 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'U', 'M', 'A', 'X', '_', 'I', '6', '4', 0, |
| /* 3235 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'M', 'A', 'X', '_', 'I', '6', '4', 0, |
| /* 3255 */ 'L', 'L', '6', '4', 0, |
| /* 3260 */ 'C', 'V', 'T', '_', 'S', '_', 'P', 'L', '6', '4', 0, |
| /* 3271 */ 'L', 'W', 'L', '6', '4', 0, |
| /* 3277 */ 'S', 'W', 'L', '6', '4', 0, |
| /* 3283 */ 'P', 's', 'e', 'u', 'd', 'o', 'M', 'F', 'L', 'O', '6', '4', 0, |
| /* 3296 */ 'M', 'T', 'L', 'O', '6', '4', 0, |
| /* 3303 */ 'B', 'E', 'Q', '6', '4', 0, |
| /* 3309 */ 'J', 'R', '6', '4', 0, |
| /* 3314 */ 'J', 'A', 'L', 'R', '6', '4', 0, |
| /* 3321 */ 'N', 'O', 'R', '6', '4', 0, |
| /* 3327 */ 'X', 'O', 'R', '6', '4', 0, |
| /* 3333 */ 'R', 'D', 'H', 'W', 'R', '6', '4', 0, |
| /* 3341 */ 'L', 'W', 'R', '6', '4', 0, |
| /* 3347 */ 'S', 'W', 'R', '6', '4', 0, |
| /* 3353 */ 'F', 'S', 'U', 'B', '_', 'P', 'S', '6', '4', 0, |
| /* 3363 */ 'F', 'A', 'D', 'D', '_', 'P', 'S', '6', '4', 0, |
| /* 3373 */ 'P', 'L', 'L', '_', 'P', 'S', '6', '4', 0, |
| /* 3382 */ 'F', 'M', 'U', 'L', '_', 'P', 'S', '6', '4', 0, |
| /* 3392 */ 'P', 'U', 'L', '_', 'P', 'S', '6', '4', 0, |
| /* 3401 */ 'A', 'D', 'D', 'R', '_', 'P', 'S', '6', '4', 0, |
| /* 3411 */ 'M', 'U', 'L', 'R', '_', 'P', 'S', '6', '4', 0, |
| /* 3421 */ 'P', 'L', 'U', '_', 'P', 'S', '6', '4', 0, |
| /* 3430 */ 'P', 'U', 'U', '_', 'P', 'S', '6', '4', 0, |
| /* 3439 */ 'C', 'V', 'T', '_', 'P', 'W', '_', 'P', 'S', '6', '4', 0, |
| /* 3451 */ 'C', 'V', 'T', '_', 'P', 'S', '_', 'S', '6', '4', 0, |
| /* 3462 */ 'S', 'L', 'T', '6', '4', 0, |
| /* 3468 */ 'C', 'V', 'T', '_', 'S', '_', 'P', 'U', '6', '4', 0, |
| /* 3479 */ 'L', 'W', '6', '4', 0, |
| /* 3484 */ 'C', 'V', 'T', '_', 'P', 'S', '_', 'P', 'W', '6', '4', 0, |
| /* 3496 */ 'S', 'W', '6', '4', 0, |
| /* 3501 */ 'B', 'G', 'E', 'Z', '6', '4', 0, |
| /* 3508 */ 'B', 'L', 'E', 'Z', '6', '4', 0, |
| /* 3515 */ 'S', 'E', 'L', 'N', 'E', 'Z', '6', '4', 0, |
| /* 3524 */ 'S', 'E', 'L', 'E', 'Q', 'Z', '6', '4', 0, |
| /* 3533 */ 'B', 'G', 'T', 'Z', '6', '4', 0, |
| /* 3540 */ 'B', 'L', 'T', 'Z', '6', '4', 0, |
| /* 3547 */ 'B', 'u', 'i', 'l', 'd', 'P', 'a', 'i', 'r', 'F', '6', '4', '_', '6', '4', 0, |
| /* 3563 */ 'E', 'x', 't', 'r', 'a', 'c', 't', 'E', 'l', 'e', 'm', 'e', 'n', 't', 'F', '6', '4', '_', '6', '4', 0, |
| /* 3584 */ 'S', 'L', 'L', '6', '4', '_', '6', '4', 0, |
| /* 3593 */ 'L', 'O', 'N', 'G', '_', 'B', 'R', 'A', 'N', 'C', 'H', '_', 'L', 'U', 'i', '2', 'O', 'p', '_', '6', '4', 0, |
| /* 3615 */ 'L', 'o', 'a', 'd', 'A', 'd', 'd', 'r', 'R', 'e', 'g', '6', '4', 0, |
| /* 3629 */ 'P', 's', 'e', 'u', 'd', 'o', 'I', 'n', 'd', 'i', 'r', 'e', 'c', 't', 'H', 'a', 'z', 'a', 'r', 'd', 'B', 'r', 'a', 'n', 'c', 'h', '6', '4', 0, |
| /* 3658 */ 'P', 's', 'e', 'u', 'd', 'o', 'I', 'n', 'd', 'i', 'r', 'e', 'c', 't', 'B', 'r', 'a', 'n', 'c', 'h', '6', '4', 0, |
| /* 3681 */ 'A', 'N', 'D', 'i', '6', '4', 0, |
| /* 3688 */ 'X', 'O', 'R', 'i', '6', '4', 0, |
| /* 3695 */ 'S', 'L', 'T', 'i', '6', '4', 0, |
| /* 3702 */ 'L', 'U', 'i', '6', '4', 0, |
| /* 3708 */ 'S', 'G', 'E', 'I', 'm', 'm', '6', '4', 0, |
| /* 3717 */ 'S', 'L', 'E', 'I', 'm', 'm', '6', '4', 0, |
| /* 3726 */ 'N', 'O', 'R', 'I', 'm', 'm', '6', '4', 0, |
| /* 3735 */ 'S', 'G', 'T', 'I', 'm', 'm', '6', '4', 0, |
| /* 3744 */ 'S', 'L', 'T', 'I', 'm', 'm', '6', '4', 0, |
| /* 3753 */ 'S', 'G', 'E', 'U', 'I', 'm', 'm', '6', '4', 0, |
| /* 3763 */ 'S', 'L', 'E', 'U', 'I', 'm', 'm', '6', '4', 0, |
| /* 3773 */ 'S', 'G', 'T', 'U', 'I', 'm', 'm', '6', '4', 0, |
| /* 3783 */ 'S', 'L', 'T', 'U', 'I', 'm', 'm', '6', '4', 0, |
| /* 3793 */ 'L', 'o', 'a', 'd', 'I', 'm', 'm', '6', '4', 0, |
| /* 3803 */ 'L', 'o', 'a', 'd', 'A', 'd', 'd', 'r', 'I', 'm', 'm', '6', '4', 0, |
| /* 3817 */ 'P', 's', 'e', 'u', 'd', 'o', 'R', 'e', 't', 'u', 'r', 'n', '6', '4', 0, |
| /* 3832 */ 'M', 'I', 'P', 'S', 'e', 'h', '_', 'r', 'e', 't', 'u', 'r', 'n', '6', '4', 0, |
| /* 3848 */ 'L', 'B', 'u', '6', '4', 0, |
| /* 3854 */ 'L', 'H', 'u', '6', '4', 0, |
| /* 3860 */ 'S', 'L', 'T', 'u', '6', '4', 0, |
| /* 3867 */ 'L', 'E', 'A', '_', 'A', 'D', 'D', 'i', 'u', '6', '4', 0, |
| /* 3879 */ 'S', 'L', 'T', 'i', 'u', '6', '4', 0, |
| /* 3887 */ 'M', 'o', 'v', 'e', 'R', '3', '2', '1', '6', 0, |
| /* 3897 */ 'R', 'e', 't', 'R', 'A', '1', '6', 0, |
| /* 3905 */ 'J', 'a', 'l', 'B', '1', '6', 0, |
| /* 3912 */ 'L', 'D', '_', 'F', '1', '6', 0, |
| /* 3919 */ 'S', 'T', '_', 'F', '1', '6', 0, |
| /* 3926 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'S', 'U', 'B', '_', 'I', '1', '6', 0, |
| /* 3946 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'A', 'D', 'D', '_', 'I', '1', '6', 0, |
| /* 3966 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'N', 'A', 'N', 'D', '_', 'I', '1', '6', 0, |
| /* 3987 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'A', 'N', 'D', '_', 'I', '1', '6', 0, |
| /* 4007 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'U', 'M', 'I', 'N', '_', 'I', '1', '6', 0, |
| /* 4028 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'M', 'I', 'N', '_', 'I', '1', '6', 0, |
| /* 4048 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'S', 'W', 'A', 'P', '_', 'I', '1', '6', 0, |
| /* 4064 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'C', 'M', 'P', '_', 'S', 'W', 'A', 'P', '_', 'I', '1', '6', 0, |
| /* 4084 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'X', 'O', 'R', '_', 'I', '1', '6', 0, |
| /* 4104 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'O', 'R', '_', 'I', '1', '6', 0, |
| /* 4123 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'U', 'M', 'A', 'X', '_', 'I', '1', '6', 0, |
| /* 4144 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'M', 'A', 'X', '_', 'I', '1', '6', 0, |
| /* 4164 */ 'M', 'o', 'v', 'e', '3', '2', 'R', '1', '6', 0, |
| /* 4174 */ 'S', 'r', 'a', 'X', '1', '6', 0, |
| /* 4181 */ 'R', 'e', 's', 't', 'o', 'r', 'e', 'X', '1', '6', 0, |
| /* 4192 */ 'S', 'a', 'v', 'e', 'X', '1', '6', 0, |
| /* 4200 */ 'B', 't', 'n', 'e', 'z', 'T', '8', 'C', 'm', 'p', 'i', 'X', '1', '6', 0, |
| /* 4215 */ 'B', 't', 'e', 'q', 'z', 'T', '8', 'C', 'm', 'p', 'i', 'X', '1', '6', 0, |
| /* 4230 */ 'B', 't', 'n', 'e', 'z', 'T', '8', 'S', 'l', 't', 'i', 'X', '1', '6', 0, |
| /* 4245 */ 'B', 't', 'e', 'q', 'z', 'T', '8', 'S', 'l', 't', 'i', 'X', '1', '6', 0, |
| /* 4260 */ 'S', 'l', 'l', 'X', '1', '6', 0, |
| /* 4267 */ 'S', 'r', 'l', 'X', '1', '6', 0, |
| /* 4274 */ 'L', 'b', 'R', 'x', 'R', 'y', 'O', 'f', 'f', 'M', 'e', 'm', 'X', '1', '6', 0, |
| /* 4290 */ 'S', 'b', 'R', 'x', 'R', 'y', 'O', 'f', 'f', 'M', 'e', 'm', 'X', '1', '6', 0, |
| /* 4306 */ 'L', 'h', 'R', 'x', 'R', 'y', 'O', 'f', 'f', 'M', 'e', 'm', 'X', '1', '6', 0, |
| /* 4322 */ 'S', 'h', 'R', 'x', 'R', 'y', 'O', 'f', 'f', 'M', 'e', 'm', 'X', '1', '6', 0, |
| /* 4338 */ 'L', 'b', 'u', 'R', 'x', 'R', 'y', 'O', 'f', 'f', 'M', 'e', 'm', 'X', '1', '6', 0, |
| /* 4355 */ 'L', 'h', 'u', 'R', 'x', 'R', 'y', 'O', 'f', 'f', 'M', 'e', 'm', 'X', '1', '6', 0, |
| /* 4372 */ 'A', 'd', 'd', 'i', 'u', 'R', 'x', 'R', 'y', 'O', 'f', 'f', 'M', 'e', 'm', 'X', '1', '6', 0, |
| /* 4391 */ 'L', 'w', 'R', 'x', 'R', 'y', 'O', 'f', 'f', 'M', 'e', 'm', 'X', '1', '6', 0, |
| /* 4407 */ 'S', 'w', 'R', 'x', 'R', 'y', 'O', 'f', 'f', 'M', 'e', 'm', 'X', '1', '6', 0, |
| /* 4423 */ 'A', 'd', 'd', 'i', 'u', 'R', 'x', 'P', 'c', 'I', 'm', 'm', 'X', '1', '6', 0, |
| /* 4439 */ 'A', 'd', 'd', 'i', 'u', 'S', 'p', 'I', 'm', 'm', 'X', '1', '6', 0, |
| /* 4453 */ 'L', 'w', 'R', 'x', 'S', 'p', 'I', 'm', 'm', 'X', '1', '6', 0, |
| /* 4466 */ 'S', 'w', 'R', 'x', 'S', 'p', 'I', 'm', 'm', 'X', '1', '6', 0, |
| /* 4479 */ 'S', 'l', 't', 'i', 'C', 'C', 'R', 'x', 'I', 'm', 'm', 'X', '1', '6', 0, |
| /* 4494 */ 'S', 'l', 't', 'i', 'u', 'C', 'C', 'R', 'x', 'I', 'm', 'm', 'X', '1', '6', 0, |
| /* 4510 */ 'L', 'i', 'R', 'x', 'I', 'm', 'm', 'X', '1', '6', 0, |
| /* 4521 */ 'C', 'm', 'p', 'i', 'R', 'x', 'I', 'm', 'm', 'X', '1', '6', 0, |
| /* 4534 */ 'S', 'l', 't', 'i', 'R', 'x', 'I', 'm', 'm', 'X', '1', '6', 0, |
| /* 4547 */ 'A', 'd', 'd', 'i', 'u', 'R', 'x', 'I', 'm', 'm', 'X', '1', '6', 0, |
| /* 4561 */ 'S', 'l', 't', 'i', 'u', 'R', 'x', 'I', 'm', 'm', 'X', '1', '6', 0, |
| /* 4575 */ 'A', 'd', 'd', 'i', 'u', 'R', 'x', 'R', 'x', 'I', 'm', 'm', 'X', '1', '6', 0, |
| /* 4591 */ 'B', 'n', 'e', 'z', 'R', 'x', 'I', 'm', 'm', 'X', '1', '6', 0, |
| /* 4604 */ 'B', 'e', 'q', 'z', 'R', 'x', 'I', 'm', 'm', 'X', '1', '6', 0, |
| /* 4617 */ 'B', 'i', 'm', 'm', 'X', '1', '6', 0, |
| /* 4625 */ 'L', 'i', 'R', 'x', 'I', 'm', 'm', 'A', 'l', 'i', 'g', 'n', 'X', '1', '6', 0, |
| /* 4641 */ 'L', 'w', 'R', 'x', 'P', 'c', 'T', 'c', 'p', 'X', '1', '6', 0, |
| /* 4654 */ 'B', 't', 'n', 'e', 'z', 'T', '8', 'C', 'm', 'p', 'X', '1', '6', 0, |
| /* 4668 */ 'B', 't', 'e', 'q', 'z', 'T', '8', 'C', 'm', 'p', 'X', '1', '6', 0, |
| /* 4682 */ 'B', 't', 'n', 'e', 'z', 'T', '8', 'S', 'l', 't', 'X', '1', '6', 0, |
| /* 4696 */ 'B', 't', 'e', 'q', 'z', 'T', '8', 'S', 'l', 't', 'X', '1', '6', 0, |
| /* 4710 */ 'B', 't', 'n', 'e', 'z', 'T', '8', 'S', 'l', 't', 'i', 'u', 'X', '1', '6', 0, |
| /* 4726 */ 'B', 't', 'e', 'q', 'z', 'T', '8', 'S', 'l', 't', 'i', 'u', 'X', '1', '6', 0, |
| /* 4742 */ 'B', 't', 'n', 'e', 'z', 'T', '8', 'S', 'l', 't', 'u', 'X', '1', '6', 0, |
| /* 4757 */ 'B', 't', 'e', 'q', 'z', 'T', '8', 'S', 'l', 't', 'u', 'X', '1', '6', 0, |
| /* 4772 */ 'B', 't', 'n', 'e', 'z', 'X', '1', '6', 0, |
| /* 4781 */ 'B', 't', 'e', 'q', 'z', 'X', '1', '6', 0, |
| /* 4790 */ 'J', 'r', 'c', 'R', 'a', '1', '6', 0, |
| /* 4798 */ 'J', 'r', 'R', 'a', '1', '6', 0, |
| /* 4805 */ 'R', 'e', 's', 't', 'o', 'r', 'e', '1', '6', 0, |
| /* 4815 */ 'G', 'o', 't', 'P', 'r', 'o', 'l', 'o', 'g', 'u', 'e', '1', '6', 0, |
| /* 4829 */ 'S', 'a', 'v', 'e', '1', '6', 0, |
| /* 4836 */ 'J', 'u', 'm', 'p', 'L', 'i', 'n', 'k', 'R', 'e', 'g', '1', '6', 0, |
| /* 4850 */ 'M', 'f', 'h', 'i', '1', '6', 0, |
| /* 4857 */ 'B', 'r', 'e', 'a', 'k', '1', '6', 0, |
| /* 4865 */ 'J', 'a', 'l', '1', '6', 0, |
| /* 4871 */ 'A', 'd', 'd', 'i', 'u', 'S', 'p', 'I', 'm', 'm', '1', '6', 0, |
| /* 4884 */ 'L', 'i', 'R', 'x', 'I', 'm', 'm', '1', '6', 0, |
| /* 4894 */ 'C', 'm', 'p', 'i', 'R', 'x', 'I', 'm', 'm', '1', '6', 0, |
| /* 4906 */ 'S', 'l', 't', 'i', 'R', 'x', 'I', 'm', 'm', '1', '6', 0, |
| /* 4918 */ 'S', 'l', 't', 'i', 'u', 'R', 'x', 'I', 'm', 'm', '1', '6', 0, |
| /* 4931 */ 'A', 'd', 'd', 'i', 'u', 'R', 'x', 'R', 'x', 'I', 'm', 'm', '1', '6', 0, |
| /* 4946 */ 'B', 'n', 'e', 'z', 'R', 'x', 'I', 'm', 'm', '1', '6', 0, |
| /* 4958 */ 'B', 'e', 'q', 'z', 'R', 'x', 'I', 'm', 'm', '1', '6', 0, |
| /* 4970 */ 'B', 'i', 'm', 'm', '1', '6', 0, |
| /* 4977 */ 'M', 'f', 'l', 'o', '1', '6', 0, |
| /* 4984 */ 'L', 'w', 'R', 'x', 'P', 'c', 'T', 'c', 'p', '1', '6', 0, |
| /* 4996 */ 'S', 'e', 'b', 'R', 'x', '1', '6', 0, |
| /* 5004 */ 'J', 'r', 'c', 'R', 'x', '1', '6', 0, |
| /* 5012 */ 'S', 'e', 'h', 'R', 'x', '1', '6', 0, |
| /* 5020 */ 'S', 'l', 't', 'C', 'C', 'R', 'x', 'R', 'y', '1', '6', 0, |
| /* 5032 */ 'S', 'l', 't', 'u', 'C', 'C', 'R', 'x', 'R', 'y', '1', '6', 0, |
| /* 5045 */ 'N', 'e', 'g', 'R', 'x', 'R', 'y', '1', '6', 0, |
| /* 5055 */ 'C', 'm', 'p', 'R', 'x', 'R', 'y', '1', '6', 0, |
| /* 5065 */ 'S', 'l', 't', 'R', 'x', 'R', 'y', '1', '6', 0, |
| /* 5075 */ 'M', 'u', 'l', 't', 'R', 'x', 'R', 'y', '1', '6', 0, |
| /* 5086 */ 'N', 'o', 't', 'R', 'x', 'R', 'y', '1', '6', 0, |
| /* 5096 */ 'S', 'l', 't', 'u', 'R', 'x', 'R', 'y', '1', '6', 0, |
| /* 5107 */ 'M', 'u', 'l', 't', 'u', 'R', 'x', 'R', 'y', '1', '6', 0, |
| /* 5119 */ 'D', 'i', 'v', 'u', 'R', 'x', 'R', 'y', '1', '6', 0, |
| /* 5130 */ 'S', 'r', 'a', 'v', 'R', 'x', 'R', 'y', '1', '6', 0, |
| /* 5141 */ 'D', 'i', 'v', 'R', 'x', 'R', 'y', '1', '6', 0, |
| /* 5151 */ 'S', 'l', 'l', 'v', 'R', 'x', 'R', 'y', '1', '6', 0, |
| /* 5162 */ 'S', 'r', 'l', 'v', 'R', 'x', 'R', 'y', '1', '6', 0, |
| /* 5173 */ 'A', 'n', 'd', 'R', 'x', 'R', 'x', 'R', 'y', '1', '6', 0, |
| /* 5185 */ 'O', 'r', 'R', 'x', 'R', 'x', 'R', 'y', '1', '6', 0, |
| /* 5196 */ 'X', 'o', 'r', 'R', 'x', 'R', 'x', 'R', 'y', '1', '6', 0, |
| /* 5208 */ 'M', 'u', 'l', 't', 'R', 'x', 'R', 'y', 'R', 'z', '1', '6', 0, |
| /* 5221 */ 'S', 'u', 'b', 'u', 'R', 'x', 'R', 'y', 'R', 'z', '1', '6', 0, |
| /* 5234 */ 'A', 'd', 'd', 'u', 'R', 'x', 'R', 'y', 'R', 'z', '1', '6', 0, |
| /* 5247 */ 'S', 'l', 't', 'u', 'R', 'x', 'R', 'y', 'R', 'z', '1', '6', 0, |
| /* 5260 */ 'M', 'u', 'l', 't', 'u', 'R', 'x', 'R', 'y', 'R', 'z', '1', '6', 0, |
| /* 5274 */ 'B', 't', 'n', 'e', 'z', '1', '6', 0, |
| /* 5282 */ 'B', 't', 'e', 'q', 'z', '1', '6', 0, |
| /* 5290 */ 'P', 's', 'e', 'u', 'd', 'o', 'I', 'n', 'd', 'r', 'e', 'c', 't', 'H', 'a', 'z', 'a', 'r', 'd', 'B', 'r', 'a', 'n', 'c', 'h', '6', '4', 'R', '6', 0, |
| /* 5320 */ 'P', 's', 'e', 'u', 'd', 'o', 'I', 'n', 'd', 'i', 'r', 'e', 'c', 't', 'B', 'r', 'a', 'n', 'c', 'h', '6', '4', 'R', '6', 0, |
| /* 5345 */ 'M', 'F', 'C', '0', '_', 'M', 'M', 'R', '6', 0, |
| /* 5355 */ 'M', 'F', 'H', 'C', '0', '_', 'M', 'M', 'R', '6', 0, |
| /* 5366 */ 'M', 'T', 'H', 'C', '0', '_', 'M', 'M', 'R', '6', 0, |
| /* 5377 */ 'M', 'T', 'C', '0', '_', 'M', 'M', 'R', '6', 0, |
| /* 5387 */ 'M', 'F', 'C', '1', '_', 'M', 'M', 'R', '6', 0, |
| /* 5397 */ 'M', 'T', 'C', '1', '_', 'M', 'M', 'R', '6', 0, |
| /* 5407 */ 'L', 'D', 'C', '2', '_', 'M', 'M', 'R', '6', 0, |
| /* 5417 */ 'S', 'D', 'C', '2', '_', 'M', 'M', 'R', '6', 0, |
| /* 5427 */ 'M', 'F', 'C', '2', '_', 'M', 'M', 'R', '6', 0, |
| /* 5437 */ 'M', 'F', 'H', 'C', '2', '_', 'M', 'M', 'R', '6', 0, |
| /* 5448 */ 'M', 'T', 'H', 'C', '2', '_', 'M', 'M', 'R', '6', 0, |
| /* 5459 */ 'M', 'T', 'C', '2', '_', 'M', 'M', 'R', '6', 0, |
| /* 5469 */ 'L', 'W', 'C', '2', '_', 'M', 'M', 'R', '6', 0, |
| /* 5479 */ 'S', 'W', 'C', '2', '_', 'M', 'M', 'R', '6', 0, |
| /* 5489 */ 'L', 'D', 'C', '1', '_', 'D', '6', '4', '_', 'M', 'M', 'R', '6', 0, |
| /* 5503 */ 'S', 'D', 'C', '1', '_', 'D', '6', '4', '_', 'M', 'M', 'R', '6', 0, |
| /* 5517 */ 'S', 'B', '1', '6', '_', 'M', 'M', 'R', '6', 0, |
| /* 5527 */ 'B', 'C', '1', '6', '_', 'M', 'M', 'R', '6', 0, |
| /* 5537 */ 'J', 'R', 'C', '1', '6', '_', 'M', 'M', 'R', '6', 0, |
| /* 5548 */ 'J', 'A', 'L', 'R', 'C', '1', '6', '_', 'M', 'M', 'R', '6', 0, |
| /* 5561 */ 'B', 'N', 'E', 'Z', 'C', '1', '6', '_', 'M', 'M', 'R', '6', 0, |
| /* 5574 */ 'B', 'E', 'Q', 'Z', 'C', '1', '6', '_', 'M', 'M', 'R', '6', 0, |
| /* 5587 */ 'A', 'N', 'D', '1', '6', '_', 'M', 'M', 'R', '6', 0, |
| /* 5598 */ 'M', 'O', 'V', 'E', '1', '6', '_', 'M', 'M', 'R', '6', 0, |
| /* 5610 */ 'S', 'H', '1', '6', '_', 'M', 'M', 'R', '6', 0, |
| /* 5620 */ 'A', 'N', 'D', 'I', '1', '6', '_', 'M', 'M', 'R', '6', 0, |
| /* 5632 */ 'L', 'I', '1', '6', '_', 'M', 'M', 'R', '6', 0, |
| /* 5642 */ 'B', 'R', 'E', 'A', 'K', '1', '6', '_', 'M', 'M', 'R', '6', 0, |
| /* 5655 */ 'S', 'L', 'L', '1', '6', '_', 'M', 'M', 'R', '6', 0, |
| /* 5666 */ 'S', 'R', 'L', '1', '6', '_', 'M', 'M', 'R', '6', 0, |
| /* 5677 */ 'L', 'W', 'M', '1', '6', '_', 'M', 'M', 'R', '6', 0, |
| /* 5688 */ 'S', 'W', 'M', '1', '6', '_', 'M', 'M', 'R', '6', 0, |
| /* 5699 */ 'S', 'D', 'B', 'B', 'P', '1', '6', '_', 'M', 'M', 'R', '6', 0, |
| /* 5712 */ 'X', 'O', 'R', '1', '6', '_', 'M', 'M', 'R', '6', 0, |
| /* 5723 */ 'N', 'O', 'T', '1', '6', '_', 'M', 'M', 'R', '6', 0, |
| /* 5734 */ 'S', 'U', 'B', 'U', '1', '6', '_', 'M', 'M', 'R', '6', 0, |
| /* 5746 */ 'A', 'D', 'D', 'U', '1', '6', '_', 'M', 'M', 'R', '6', 0, |
| /* 5758 */ 'S', 'W', '1', '6', '_', 'M', 'M', 'R', '6', 0, |
| /* 5768 */ 'L', 'S', 'A', '_', 'M', 'M', 'R', '6', 0, |
| /* 5777 */ 'E', 'H', 'B', '_', 'M', 'M', 'R', '6', 0, |
| /* 5786 */ 'J', 'A', 'L', 'R', 'C', '_', 'H', 'B', '_', 'M', 'M', 'R', '6', 0, |
| /* 5800 */ 'L', 'B', '_', 'M', 'M', 'R', '6', 0, |
| /* 5808 */ 'S', 'B', '_', 'M', 'M', 'R', '6', 0, |
| /* 5816 */ 'S', 'U', 'B', '_', 'M', 'M', 'R', '6', 0, |
| /* 5825 */ 'B', 'C', '_', 'M', 'M', 'R', '6', 0, |
| /* 5833 */ 'B', 'G', 'E', 'C', '_', 'M', 'M', 'R', '6', 0, |
| /* 5843 */ 'B', 'N', 'E', 'C', '_', 'M', 'M', 'R', '6', 0, |
| /* 5853 */ 'J', 'I', 'C', '_', 'M', 'M', 'R', '6', 0, |
| /* 5862 */ 'B', 'A', 'L', 'C', '_', 'M', 'M', 'R', '6', 0, |
| /* 5872 */ 'J', 'I', 'A', 'L', 'C', '_', 'M', 'M', 'R', '6', 0, |
| /* 5883 */ 'B', 'G', 'E', 'Z', 'A', 'L', 'C', '_', 'M', 'M', 'R', '6', 0, |
| /* 5896 */ 'B', 'L', 'E', 'Z', 'A', 'L', 'C', '_', 'M', 'M', 'R', '6', 0, |
| /* 5909 */ 'B', 'N', 'E', 'Z', 'A', 'L', 'C', '_', 'M', 'M', 'R', '6', 0, |
| /* 5922 */ 'B', 'E', 'Q', 'Z', 'A', 'L', 'C', '_', 'M', 'M', 'R', '6', 0, |
| /* 5935 */ 'B', 'G', 'T', 'Z', 'A', 'L', 'C', '_', 'M', 'M', 'R', '6', 0, |
| /* 5948 */ 'B', 'L', 'T', 'Z', 'A', 'L', 'C', '_', 'M', 'M', 'R', '6', 0, |
| /* 5961 */ 'E', 'R', 'E', 'T', 'N', 'C', '_', 'M', 'M', 'R', '6', 0, |
| /* 5973 */ 'S', 'Y', 'N', 'C', '_', 'M', 'M', 'R', '6', 0, |
| /* 5983 */ 'A', 'U', 'I', 'P', 'C', '_', 'M', 'M', 'R', '6', 0, |
| /* 5994 */ 'A', 'L', 'U', 'I', 'P', 'C', '_', 'M', 'M', 'R', '6', 0, |
| /* 6006 */ 'A', 'D', 'D', 'I', 'U', 'P', 'C', '_', 'M', 'M', 'R', '6', 0, |
| /* 6019 */ 'L', 'W', 'P', 'C', '_', 'M', 'M', 'R', '6', 0, |
| /* 6029 */ 'B', 'E', 'Q', 'C', '_', 'M', 'M', 'R', '6', 0, |
| /* 6039 */ 'J', 'A', 'L', 'R', 'C', '_', 'M', 'M', 'R', '6', 0, |
| /* 6050 */ 'S', 'C', '_', 'M', 'M', 'R', '6', 0, |
| /* 6058 */ 'B', 'L', 'T', 'C', '_', 'M', 'M', 'R', '6', 0, |
| /* 6068 */ 'B', 'G', 'E', 'U', 'C', '_', 'M', 'M', 'R', '6', 0, |
| /* 6079 */ 'B', 'L', 'T', 'U', 'C', '_', 'M', 'M', 'R', '6', 0, |
| /* 6090 */ 'B', 'N', 'V', 'C', '_', 'M', 'M', 'R', '6', 0, |
| /* 6100 */ 'B', 'O', 'V', 'C', '_', 'M', 'M', 'R', '6', 0, |
| /* 6110 */ 'B', 'G', 'E', 'Z', 'C', '_', 'M', 'M', 'R', '6', 0, |
| /* 6121 */ 'B', 'L', 'E', 'Z', 'C', '_', 'M', 'M', 'R', '6', 0, |
| /* 6132 */ 'B', 'C', '1', 'N', 'E', 'Z', 'C', '_', 'M', 'M', 'R', '6', 0, |
| /* 6145 */ 'B', 'C', '2', 'N', 'E', 'Z', 'C', '_', 'M', 'M', 'R', '6', 0, |
| /* 6158 */ 'B', 'N', 'E', 'Z', 'C', '_', 'M', 'M', 'R', '6', 0, |
| /* 6169 */ 'B', 'C', '1', 'E', 'Q', 'Z', 'C', '_', 'M', 'M', 'R', '6', 0, |
| /* 6182 */ 'B', 'C', '2', 'E', 'Q', 'Z', 'C', '_', 'M', 'M', 'R', '6', 0, |
| /* 6195 */ 'B', 'E', 'Q', 'Z', 'C', '_', 'M', 'M', 'R', '6', 0, |
| /* 6206 */ 'B', 'G', 'T', 'Z', 'C', '_', 'M', 'M', 'R', '6', 0, |
| /* 6217 */ 'B', 'L', 'T', 'Z', 'C', '_', 'M', 'M', 'R', '6', 0, |
| /* 6228 */ 'A', 'D', 'D', '_', 'M', 'M', 'R', '6', 0, |
| /* 6237 */ 'A', 'N', 'D', '_', 'M', 'M', 'R', '6', 0, |
| /* 6246 */ 'M', 'O', 'D', '_', 'M', 'M', 'R', '6', 0, |
| /* 6255 */ 'M', 'I', 'N', 'A', '_', 'D', '_', 'M', 'M', 'R', '6', 0, |
| /* 6267 */ 'M', 'A', 'X', 'A', '_', 'D', '_', 'M', 'M', 'R', '6', 0, |
| /* 6279 */ 'C', 'M', 'P', '_', 'S', 'L', 'E', '_', 'D', '_', 'M', 'M', 'R', '6', 0, |
| /* 6294 */ 'C', 'M', 'P', '_', 'S', 'U', 'L', 'E', '_', 'D', '_', 'M', 'M', 'R', '6', 0, |
| /* 6310 */ 'C', 'M', 'P', '_', 'U', 'L', 'E', '_', 'D', '_', 'M', 'M', 'R', '6', 0, |
| /* 6325 */ 'C', 'M', 'P', '_', 'L', 'E', '_', 'D', '_', 'M', 'M', 'R', '6', 0, |
| /* 6339 */ 'C', 'M', 'P', '_', 'S', 'A', 'F', '_', 'D', '_', 'M', 'M', 'R', '6', 0, |
| /* 6354 */ 'C', 'M', 'P', '_', 'A', 'F', '_', 'D', '_', 'M', 'M', 'R', '6', 0, |
| /* 6368 */ 'M', 'S', 'U', 'B', 'F', '_', 'D', '_', 'M', 'M', 'R', '6', 0, |
| /* 6381 */ 'M', 'A', 'D', 'D', 'F', '_', 'D', '_', 'M', 'M', 'R', '6', 0, |
| /* 6394 */ 'S', 'E', 'L', '_', 'D', '_', 'M', 'M', 'R', '6', 0, |
| /* 6405 */ 'T', 'R', 'U', 'N', 'C', '_', 'L', '_', 'D', '_', 'M', 'M', 'R', '6', 0, |
| /* 6420 */ 'R', 'O', 'U', 'N', 'D', '_', 'L', '_', 'D', '_', 'M', 'M', 'R', '6', 0, |
| /* 6435 */ 'C', 'E', 'I', 'L', '_', 'L', '_', 'D', '_', 'M', 'M', 'R', '6', 0, |
| /* 6449 */ 'F', 'L', 'O', 'O', 'R', '_', 'L', '_', 'D', '_', 'M', 'M', 'R', '6', 0, |
| /* 6464 */ 'C', 'V', 'T', '_', 'L', '_', 'D', '_', 'M', 'M', 'R', '6', 0, |
| /* 6477 */ 'M', 'I', 'N', '_', 'D', '_', 'M', 'M', 'R', '6', 0, |
| /* 6488 */ 'C', 'M', 'P', '_', 'S', 'U', 'N', '_', 'D', '_', 'M', 'M', 'R', '6', 0, |
| /* 6503 */ 'C', 'M', 'P', '_', 'U', 'N', '_', 'D', '_', 'M', 'M', 'R', '6', 0, |
| /* 6517 */ 'C', 'M', 'P', '_', 'S', 'E', 'Q', '_', 'D', '_', 'M', 'M', 'R', '6', 0, |
| /* 6532 */ 'C', 'M', 'P', '_', 'S', 'U', 'E', 'Q', '_', 'D', '_', 'M', 'M', 'R', '6', 0, |
| /* 6548 */ 'C', 'M', 'P', '_', 'U', 'E', 'Q', '_', 'D', '_', 'M', 'M', 'R', '6', 0, |
| /* 6563 */ 'C', 'M', 'P', '_', 'E', 'Q', '_', 'D', '_', 'M', 'M', 'R', '6', 0, |
| /* 6577 */ 'C', 'L', 'A', 'S', 'S', '_', 'D', '_', 'M', 'M', 'R', '6', 0, |
| /* 6590 */ 'C', 'M', 'P', '_', 'S', 'L', 'T', '_', 'D', '_', 'M', 'M', 'R', '6', 0, |
| /* 6605 */ 'C', 'M', 'P', '_', 'S', 'U', 'L', 'T', '_', 'D', '_', 'M', 'M', 'R', '6', 0, |
| /* 6621 */ 'C', 'M', 'P', '_', 'U', 'L', 'T', '_', 'D', '_', 'M', 'M', 'R', '6', 0, |
| /* 6636 */ 'C', 'M', 'P', '_', 'L', 'T', '_', 'D', '_', 'M', 'M', 'R', '6', 0, |
| /* 6650 */ 'R', 'I', 'N', 'T', '_', 'D', '_', 'M', 'M', 'R', '6', 0, |
| /* 6662 */ 'F', 'M', 'O', 'V', '_', 'D', '_', 'M', 'M', 'R', '6', 0, |
| /* 6674 */ 'T', 'R', 'U', 'N', 'C', '_', 'W', '_', 'D', '_', 'M', 'M', 'R', '6', 0, |
| /* 6689 */ 'R', 'O', 'U', 'N', 'D', '_', 'W', '_', 'D', '_', 'M', 'M', 'R', '6', 0, |
| /* 6704 */ 'C', 'E', 'I', 'L', '_', 'W', '_', 'D', '_', 'M', 'M', 'R', '6', 0, |
| /* 6718 */ 'F', 'L', 'O', 'O', 'R', '_', 'W', '_', 'D', '_', 'M', 'M', 'R', '6', 0, |
| /* 6733 */ 'M', 'A', 'X', '_', 'D', '_', 'M', 'M', 'R', '6', 0, |
| /* 6744 */ 'S', 'E', 'L', 'N', 'E', 'Z', '_', 'D', '_', 'M', 'M', 'R', '6', 0, |
| /* 6758 */ 'S', 'E', 'L', 'E', 'Q', 'Z', '_', 'D', '_', 'M', 'M', 'R', '6', 0, |
| /* 6772 */ 'C', 'A', 'C', 'H', 'E', '_', 'M', 'M', 'R', '6', 0, |
| /* 6783 */ 'S', 'I', 'G', 'R', 'I', 'E', '_', 'M', 'M', 'R', '6', 0, |
| /* 6795 */ 'P', 'A', 'U', 'S', 'E', '_', 'M', 'M', 'R', '6', 0, |
| /* 6806 */ 'P', 'R', 'E', 'F', '_', 'M', 'M', 'R', '6', 0, |
| /* 6816 */ 'T', 'L', 'B', 'I', 'N', 'V', 'F', '_', 'M', 'M', 'R', '6', 0, |
| /* 6829 */ 'T', 'A', 'I', 'L', 'C', 'A', 'L', 'L', 'R', 'E', 'G', '_', 'M', 'M', 'R', '6', 0, |
| /* 6846 */ 'W', 'S', 'B', 'H', '_', 'M', 'M', 'R', '6', 0, |
| /* 6856 */ 'S', 'H', '_', 'M', 'M', 'R', '6', 0, |
| /* 6864 */ 'M', 'U', 'H', '_', 'M', 'M', 'R', '6', 0, |
| /* 6873 */ 'S', 'Y', 'N', 'C', 'I', '_', 'M', 'M', 'R', '6', 0, |
| /* 6884 */ 'A', 'N', 'D', 'I', '_', 'M', 'M', 'R', '6', 0, |
| /* 6894 */ 'E', 'I', '_', 'M', 'M', 'R', '6', 0, |
| /* 6902 */ 'X', 'O', 'R', 'I', '_', 'M', 'M', 'R', '6', 0, |
| /* 6912 */ 'A', 'U', 'I', '_', 'M', 'M', 'R', '6', 0, |
| /* 6921 */ 'L', 'U', 'I', '_', 'M', 'M', 'R', '6', 0, |
| /* 6930 */ 'G', 'I', 'N', 'V', 'I', '_', 'M', 'M', 'R', '6', 0, |
| /* 6941 */ 'B', 'R', 'E', 'A', 'K', '_', 'M', 'M', 'R', '6', 0, |
| /* 6952 */ 'J', 'A', 'L', '_', 'M', 'M', 'R', '6', 0, |
| /* 6961 */ 'T', 'A', 'I', 'L', 'C', 'A', 'L', 'L', '_', 'M', 'M', 'R', '6', 0, |
| /* 6975 */ 'S', 'L', 'L', '_', 'M', 'M', 'R', '6', 0, |
| /* 6984 */ 'M', 'U', 'L', '_', 'M', 'M', 'R', '6', 0, |
| /* 6993 */ 'C', 'V', 'T', '_', 'D', '_', 'L', '_', 'M', 'M', 'R', '6', 0, |
| /* 7006 */ 'C', 'V', 'T', '_', 'S', '_', 'L', '_', 'M', 'M', 'R', '6', 0, |
| /* 7019 */ 'A', 'L', 'I', 'G', 'N', '_', 'M', 'M', 'R', '6', 0, |
| /* 7030 */ 'C', 'L', 'O', '_', 'M', 'M', 'R', '6', 0, |
| /* 7039 */ 'B', 'I', 'T', 'S', 'W', 'A', 'P', '_', 'M', 'M', 'R', '6', 0, |
| /* 7052 */ 'S', 'D', 'B', 'B', 'P', '_', 'M', 'M', 'R', '6', 0, |
| /* 7063 */ 'M', 'O', 'V', 'E', 'P', '_', 'M', 'M', 'R', '6', 0, |
| /* 7074 */ 'S', 'S', 'N', 'O', 'P', '_', 'M', 'M', 'R', '6', 0, |
| /* 7085 */ 'J', 'R', 'C', 'A', 'D', 'D', 'I', 'U', 'S', 'P', '_', 'M', 'M', 'R', '6', 0, |
| /* 7101 */ 'S', 'W', 'S', 'P', '_', 'M', 'M', 'R', '6', 0, |
| /* 7111 */ 'D', 'V', 'P', '_', 'M', 'M', 'R', '6', 0, |
| /* 7120 */ 'E', 'V', 'P', '_', 'M', 'M', 'R', '6', 0, |
| /* 7129 */ 'N', 'O', 'R', '_', 'M', 'M', 'R', '6', 0, |
| /* 7138 */ 'X', 'O', 'R', '_', 'M', 'M', 'R', '6', 0, |
| /* 7147 */ 'R', 'D', 'P', 'G', 'P', 'R', '_', 'M', 'M', 'R', '6', 0, |
| /* 7159 */ 'W', 'R', 'P', 'G', 'P', 'R', '_', 'M', 'M', 'R', '6', 0, |
| /* 7171 */ 'R', 'D', 'H', 'W', 'R', '_', 'M', 'M', 'R', '6', 0, |
| /* 7182 */ 'I', 'N', 'S', '_', 'M', 'M', 'R', '6', 0, |
| /* 7191 */ 'M', 'I', 'N', 'A', '_', 'S', '_', 'M', 'M', 'R', '6', 0, |
| /* 7203 */ 'M', 'A', 'X', 'A', '_', 'S', '_', 'M', 'M', 'R', '6', 0, |
| /* 7215 */ 'F', 'S', 'U', 'B', '_', 'S', '_', 'M', 'M', 'R', '6', 0, |
| /* 7227 */ 'F', 'A', 'D', 'D', '_', 'S', '_', 'M', 'M', 'R', '6', 0, |
| /* 7239 */ 'C', 'M', 'P', '_', 'S', 'L', 'E', '_', 'S', '_', 'M', 'M', 'R', '6', 0, |
| /* 7254 */ 'C', 'M', 'P', '_', 'S', 'U', 'L', 'E', '_', 'S', '_', 'M', 'M', 'R', '6', 0, |
| /* 7270 */ 'C', 'M', 'P', '_', 'U', 'L', 'E', '_', 'S', '_', 'M', 'M', 'R', '6', 0, |
| /* 7285 */ 'C', 'M', 'P', '_', 'L', 'E', '_', 'S', '_', 'M', 'M', 'R', '6', 0, |
| /* 7299 */ 'C', 'M', 'P', '_', 'S', 'A', 'F', '_', 'S', '_', 'M', 'M', 'R', '6', 0, |
| /* 7314 */ 'C', 'M', 'P', '_', 'A', 'F', '_', 'S', '_', 'M', 'M', 'R', '6', 0, |
| /* 7328 */ 'M', 'S', 'U', 'B', 'F', '_', 'S', '_', 'M', 'M', 'R', '6', 0, |
| /* 7341 */ 'M', 'A', 'D', 'D', 'F', '_', 'S', '_', 'M', 'M', 'R', '6', 0, |
| /* 7354 */ 'F', 'N', 'E', 'G', '_', 'S', '_', 'M', 'M', 'R', '6', 0, |
| /* 7366 */ 'S', 'E', 'L', '_', 'S', '_', 'M', 'M', 'R', '6', 0, |
| /* 7377 */ 'F', 'M', 'U', 'L', '_', 'S', '_', 'M', 'M', 'R', '6', 0, |
| /* 7389 */ 'T', 'R', 'U', 'N', 'C', '_', 'L', '_', 'S', '_', 'M', 'M', 'R', '6', 0, |
| /* 7404 */ 'R', 'O', 'U', 'N', 'D', '_', 'L', '_', 'S', '_', 'M', 'M', 'R', '6', 0, |
| /* 7419 */ 'C', 'E', 'I', 'L', '_', 'L', '_', 'S', '_', 'M', 'M', 'R', '6', 0, |
| /* 7433 */ 'F', 'L', 'O', 'O', 'R', '_', 'L', '_', 'S', '_', 'M', 'M', 'R', '6', 0, |
| /* 7448 */ 'C', 'V', 'T', '_', 'L', '_', 'S', '_', 'M', 'M', 'R', '6', 0, |
| /* 7461 */ 'M', 'I', 'N', '_', 'S', '_', 'M', 'M', 'R', '6', 0, |
| /* 7472 */ 'C', 'M', 'P', '_', 'S', 'U', 'N', '_', 'S', '_', 'M', 'M', 'R', '6', 0, |
| /* 7487 */ 'C', 'M', 'P', '_', 'U', 'N', '_', 'S', '_', 'M', 'M', 'R', '6', 0, |
| /* 7501 */ 'C', 'M', 'P', '_', 'S', 'E', 'Q', '_', 'S', '_', 'M', 'M', 'R', '6', 0, |
| /* 7516 */ 'C', 'M', 'P', '_', 'S', 'U', 'E', 'Q', '_', 'S', '_', 'M', 'M', 'R', '6', 0, |
| /* 7532 */ 'C', 'M', 'P', '_', 'U', 'E', 'Q', '_', 'S', '_', 'M', 'M', 'R', '6', 0, |
| /* 7547 */ 'C', 'M', 'P', '_', 'E', 'Q', '_', 'S', '_', 'M', 'M', 'R', '6', 0, |
| /* 7561 */ 'C', 'L', 'A', 'S', 'S', '_', 'S', '_', 'M', 'M', 'R', '6', 0, |
| /* 7574 */ 'C', 'M', 'P', '_', 'S', 'L', 'T', '_', 'S', '_', 'M', 'M', 'R', '6', 0, |
| /* 7589 */ 'C', 'M', 'P', '_', 'S', 'U', 'L', 'T', '_', 'S', '_', 'M', 'M', 'R', '6', 0, |
| /* 7605 */ 'C', 'M', 'P', '_', 'U', 'L', 'T', '_', 'S', '_', 'M', 'M', 'R', '6', 0, |
| /* 7620 */ 'C', 'M', 'P', '_', 'L', 'T', '_', 'S', '_', 'M', 'M', 'R', '6', 0, |
| /* 7634 */ 'R', 'I', 'N', 'T', '_', 'S', '_', 'M', 'M', 'R', '6', 0, |
| /* 7646 */ 'F', 'D', 'I', 'V', '_', 'S', '_', 'M', 'M', 'R', '6', 0, |
| /* 7658 */ 'F', 'M', 'O', 'V', '_', 'S', '_', 'M', 'M', 'R', '6', 0, |
| /* 7670 */ 'T', 'R', 'U', 'N', 'C', '_', 'W', '_', 'S', '_', 'M', 'M', 'R', '6', 0, |
| /* 7685 */ 'R', 'O', 'U', 'N', 'D', '_', 'W', '_', 'S', '_', 'M', 'M', 'R', '6', 0, |
| /* 7700 */ 'C', 'E', 'I', 'L', '_', 'W', '_', 'S', '_', 'M', 'M', 'R', '6', 0, |
| /* 7714 */ 'F', 'L', 'O', 'O', 'R', '_', 'W', '_', 'S', '_', 'M', 'M', 'R', '6', 0, |
| /* 7729 */ 'C', 'V', 'T', '_', 'W', '_', 'S', '_', 'M', 'M', 'R', '6', 0, |
| /* 7742 */ 'M', 'A', 'X', '_', 'S', '_', 'M', 'M', 'R', '6', 0, |
| /* 7753 */ 'S', 'E', 'L', 'N', 'E', 'Z', '_', 'S', '_', 'M', 'M', 'R', '6', 0, |
| /* 7767 */ 'S', 'E', 'L', 'E', 'Q', 'Z', '_', 'S', '_', 'M', 'M', 'R', '6', 0, |
| /* 7781 */ 'D', 'E', 'R', 'E', 'T', '_', 'M', 'M', 'R', '6', 0, |
| /* 7792 */ 'W', 'A', 'I', 'T', '_', 'M', 'M', 'R', '6', 0, |
| /* 7802 */ 'G', 'I', 'N', 'V', 'T', '_', 'M', 'M', 'R', '6', 0, |
| /* 7813 */ 'E', 'X', 'T', '_', 'M', 'M', 'R', '6', 0, |
| /* 7822 */ 'L', 'B', 'U', '_', 'M', 'M', 'R', '6', 0, |
| /* 7831 */ 'S', 'U', 'B', 'U', '_', 'M', 'M', 'R', '6', 0, |
| /* 7841 */ 'A', 'D', 'D', 'U', '_', 'M', 'M', 'R', '6', 0, |
| /* 7851 */ 'M', 'O', 'D', 'U', '_', 'M', 'M', 'R', '6', 0, |
| /* 7861 */ 'M', 'U', 'H', 'U', '_', 'M', 'M', 'R', '6', 0, |
| /* 7871 */ 'A', 'D', 'D', 'I', 'U', '_', 'M', 'M', 'R', '6', 0, |
| /* 7882 */ 'M', 'U', 'L', 'U', '_', 'M', 'M', 'R', '6', 0, |
| /* 7892 */ 'D', 'I', 'V', 'U', '_', 'M', 'M', 'R', '6', 0, |
| /* 7902 */ 'D', 'I', 'V', '_', 'M', 'M', 'R', '6', 0, |
| /* 7911 */ 'T', 'L', 'B', 'I', 'N', 'V', '_', 'M', 'M', 'R', '6', 0, |
| /* 7923 */ 'L', 'W', '_', 'M', 'M', 'R', '6', 0, |
| /* 7931 */ 'S', 'W', '_', 'M', 'M', 'R', '6', 0, |
| /* 7939 */ 'C', 'V', 'T', '_', 'S', '_', 'W', '_', 'M', 'M', 'R', '6', 0, |
| /* 7952 */ 'S', 'E', 'L', 'N', 'E', 'Z', '_', 'M', 'M', 'R', '6', 0, |
| /* 7964 */ 'C', 'L', 'Z', '_', 'M', 'M', 'R', '6', 0, |
| /* 7973 */ 'S', 'E', 'L', 'E', 'Q', 'Z', '_', 'M', 'M', 'R', '6', 0, |
| /* 7985 */ 'P', 's', 'e', 'u', 'd', 'o', 'I', 'n', 'd', 'i', 'r', 'e', 'c', 't', 'B', 'r', 'a', 'n', 'c', 'h', '_', 'M', 'M', 'R', '6', 0, |
| /* 8011 */ 'L', 'D', 'C', '2', '_', 'R', '6', 0, |
| /* 8019 */ 'S', 'D', 'C', '2', '_', 'R', '6', 0, |
| /* 8027 */ 'L', 'W', 'C', '2', '_', 'R', '6', 0, |
| /* 8035 */ 'S', 'W', 'C', '2', '_', 'R', '6', 0, |
| /* 8043 */ 'J', 'R', '_', 'H', 'B', '6', '4', '_', 'R', '6', 0, |
| /* 8054 */ 'S', 'C', '6', '4', '_', 'R', '6', 0, |
| /* 8062 */ 'L', 'L', '6', '4', '_', 'R', '6', 0, |
| /* 8070 */ 'D', 'L', 'S', 'A', '_', 'R', '6', 0, |
| /* 8078 */ 'J', 'R', '_', 'H', 'B', '_', 'R', '6', 0, |
| /* 8087 */ 'S', 'C', '_', 'R', '6', 0, |
| /* 8093 */ 'S', 'C', 'D', '_', 'R', '6', 0, |
| /* 8100 */ 'L', 'L', 'D', '_', 'R', '6', 0, |
| /* 8107 */ 'C', 'A', 'C', 'H', 'E', '_', 'R', '6', 0, |
| /* 8116 */ 'P', 'R', 'E', 'F', '_', 'R', '6', 0, |
| /* 8124 */ 'L', 'L', '_', 'R', '6', 0, |
| /* 8130 */ 'D', 'M', 'U', 'L', '_', 'R', '6', 0, |
| /* 8138 */ 'D', 'C', 'L', 'O', '_', 'R', '6', 0, |
| /* 8146 */ 'S', 'D', 'B', 'B', 'P', '_', 'R', '6', 0, |
| /* 8155 */ 'D', 'C', 'L', 'Z', '_', 'R', '6', 0, |
| /* 8163 */ 'P', 's', 'e', 'u', 'd', 'o', 'I', 'n', 'd', 'r', 'e', 'c', 't', 'H', 'a', 'z', 'a', 'r', 'd', 'B', 'r', 'a', 'n', 'c', 'h', 'R', '6', 0, |
| /* 8191 */ 'P', 's', 'e', 'u', 'd', 'o', 'I', 'n', 'd', 'i', 'r', 'e', 'c', 't', 'B', 'r', 'a', 'n', 'c', 'h', 'R', '6', 0, |
| /* 8214 */ 'L', 'O', 'A', 'D', '_', 'A', 'C', 'C', '1', '2', '8', 0, |
| /* 8226 */ 'S', 'T', 'O', 'R', 'E', '_', 'A', 'C', 'C', '1', '2', '8', 0, |
| /* 8239 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'S', 'U', 'B', '_', 'I', '8', 0, |
| /* 8258 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'A', 'D', 'D', '_', 'I', '8', 0, |
| /* 8277 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'N', 'A', 'N', 'D', '_', 'I', '8', 0, |
| /* 8297 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'A', 'N', 'D', '_', 'I', '8', 0, |
| /* 8316 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'U', 'M', 'I', 'N', '_', 'I', '8', 0, |
| /* 8336 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'M', 'I', 'N', '_', 'I', '8', 0, |
| /* 8355 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'S', 'W', 'A', 'P', '_', 'I', '8', 0, |
| /* 8370 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'C', 'M', 'P', '_', 'S', 'W', 'A', 'P', '_', 'I', '8', 0, |
| /* 8389 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'X', 'O', 'R', '_', 'I', '8', 0, |
| /* 8408 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'O', 'R', '_', 'I', '8', 0, |
| /* 8426 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'U', 'M', 'A', 'X', '_', 'I', '8', 0, |
| /* 8446 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'M', 'A', 'X', '_', 'I', '8', 0, |
| /* 8465 */ 'S', 'A', 'A', 0, |
| /* 8469 */ 'P', 'R', 'E', 'C', 'E', 'U', '_', 'P', 'H', '_', 'Q', 'B', 'L', 'A', 0, |
| /* 8484 */ 'P', 'R', 'E', 'C', 'E', 'Q', 'U', '_', 'P', 'H', '_', 'Q', 'B', 'L', 'A', 0, |
| /* 8500 */ 'G', '_', 'F', 'M', 'A', 0, |
| /* 8506 */ 'G', '_', 'S', 'T', 'R', 'I', 'C', 'T', '_', 'F', 'M', 'A', 0, |
| /* 8519 */ 'P', 'R', 'E', 'C', 'E', 'U', '_', 'P', 'H', '_', 'Q', 'B', 'R', 'A', 0, |
| /* 8534 */ 'P', 'R', 'E', 'C', 'E', 'Q', 'U', '_', 'P', 'H', '_', 'Q', 'B', 'R', 'A', 0, |
| /* 8550 */ 'D', 'S', 'R', 'A', 0, |
| /* 8555 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'S', 'U', 'B', '_', 'I', '3', '2', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0, |
| /* 8582 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'A', 'D', 'D', '_', 'I', '3', '2', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0, |
| /* 8609 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'N', 'A', 'N', 'D', '_', 'I', '3', '2', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0, |
| /* 8637 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'A', 'N', 'D', '_', 'I', '3', '2', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0, |
| /* 8664 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'U', 'M', 'I', 'N', '_', 'I', '3', '2', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0, |
| /* 8692 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'M', 'I', 'N', '_', 'I', '3', '2', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0, |
| /* 8719 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'S', 'W', 'A', 'P', '_', 'I', '3', '2', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0, |
| /* 8742 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'C', 'M', 'P', '_', 'S', 'W', 'A', 'P', '_', 'I', '3', '2', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0, |
| /* 8769 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'X', 'O', 'R', '_', 'I', '3', '2', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0, |
| /* 8796 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'O', 'R', '_', 'I', '3', '2', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0, |
| /* 8822 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'U', 'M', 'A', 'X', '_', 'I', '3', '2', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0, |
| /* 8850 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'M', 'A', 'X', '_', 'I', '3', '2', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0, |
| /* 8877 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'S', 'U', 'B', '_', 'I', '6', '4', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0, |
| /* 8904 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'A', 'D', 'D', '_', 'I', '6', '4', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0, |
| /* 8931 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'N', 'A', 'N', 'D', '_', 'I', '6', '4', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0, |
| /* 8959 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'A', 'N', 'D', '_', 'I', '6', '4', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0, |
| /* 8986 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'U', 'M', 'I', 'N', '_', 'I', '6', '4', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0, |
| /* 9014 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'M', 'I', 'N', '_', 'I', '6', '4', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0, |
| /* 9041 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'S', 'W', 'A', 'P', '_', 'I', '6', '4', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0, |
| /* 9064 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'C', 'M', 'P', '_', 'S', 'W', 'A', 'P', '_', 'I', '6', '4', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0, |
| /* 9091 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'X', 'O', 'R', '_', 'I', '6', '4', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0, |
| /* 9118 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'O', 'R', '_', 'I', '6', '4', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0, |
| /* 9144 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'U', 'M', 'A', 'X', '_', 'I', '6', '4', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0, |
| /* 9172 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'M', 'A', 'X', '_', 'I', '6', '4', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0, |
| /* 9199 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'S', 'U', 'B', '_', 'I', '1', '6', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0, |
| /* 9226 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'A', 'D', 'D', '_', 'I', '1', '6', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0, |
| /* 9253 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'N', 'A', 'N', 'D', '_', 'I', '1', '6', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0, |
| /* 9281 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'A', 'N', 'D', '_', 'I', '1', '6', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0, |
| /* 9308 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'U', 'M', 'I', 'N', '_', 'I', '1', '6', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0, |
| /* 9336 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'M', 'I', 'N', '_', 'I', '1', '6', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0, |
| /* 9363 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'S', 'W', 'A', 'P', '_', 'I', '1', '6', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0, |
| /* 9386 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'C', 'M', 'P', '_', 'S', 'W', 'A', 'P', '_', 'I', '1', '6', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0, |
| /* 9413 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'X', 'O', 'R', '_', 'I', '1', '6', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0, |
| /* 9440 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'O', 'R', '_', 'I', '1', '6', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0, |
| /* 9466 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'U', 'M', 'A', 'X', '_', 'I', '1', '6', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0, |
| /* 9494 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'M', 'A', 'X', '_', 'I', '1', '6', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0, |
| /* 9521 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'S', 'U', 'B', '_', 'I', '8', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0, |
| /* 9547 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'A', 'D', 'D', '_', 'I', '8', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0, |
| /* 9573 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'N', 'A', 'N', 'D', '_', 'I', '8', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0, |
| /* 9600 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'A', 'N', 'D', '_', 'I', '8', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0, |
| /* 9626 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'U', 'M', 'I', 'N', '_', 'I', '8', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0, |
| /* 9653 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'M', 'I', 'N', '_', 'I', '8', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0, |
| /* 9679 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'S', 'W', 'A', 'P', '_', 'I', '8', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0, |
| /* 9701 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'C', 'M', 'P', '_', 'S', 'W', 'A', 'P', '_', 'I', '8', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0, |
| /* 9727 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'X', 'O', 'R', '_', 'I', '8', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0, |
| /* 9753 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'O', 'R', '_', 'I', '8', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0, |
| /* 9778 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'U', 'M', 'A', 'X', '_', 'I', '8', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0, |
| /* 9805 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'M', 'A', 'X', '_', 'I', '8', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0, |
| /* 9831 */ 'R', 'e', 't', 'R', 'A', 0, |
| /* 9837 */ 'D', 'L', 'S', 'A', 0, |
| /* 9842 */ 'C', 'F', 'C', 'M', 'S', 'A', 0, |
| /* 9849 */ 'C', 'T', 'C', 'M', 'S', 'A', 0, |
| /* 9856 */ 'C', 'R', 'C', '3', '2', 'B', 0, |
| /* 9863 */ 'C', 'R', 'C', '3', '2', 'C', 'B', 0, |
| /* 9871 */ 'S', 'E', 'B', 0, |
| /* 9875 */ 'E', 'H', 'B', 0, |
| /* 9879 */ 'T', 'A', 'I', 'L', 'C', 'A', 'L', 'L', 'R', 'E', 'G', 'H', 'B', 0, |
| /* 9893 */ 'J', 'R', '_', 'H', 'B', 0, |
| /* 9899 */ 'J', 'A', 'L', 'R', '_', 'H', 'B', 0, |
| /* 9907 */ 'L', 'B', 0, |
| /* 9910 */ 'S', 'H', 'R', 'A', '_', 'Q', 'B', 0, |
| /* 9918 */ 'C', 'M', 'P', 'G', 'D', 'U', '_', 'L', 'E', '_', 'Q', 'B', 0, |
| /* 9931 */ 'C', 'M', 'P', 'G', 'U', '_', 'L', 'E', '_', 'Q', 'B', 0, |
| /* 9943 */ 'P', 's', 'e', 'u', 'd', 'o', 'C', 'M', 'P', 'U', '_', 'L', 'E', '_', 'Q', 'B', 0, |
| /* 9960 */ 'S', 'U', 'B', 'U', 'H', '_', 'Q', 'B', 0, |
| /* 9969 */ 'A', 'D', 'D', 'U', 'H', '_', 'Q', 'B', 0, |
| /* 9978 */ 'P', 's', 'e', 'u', 'd', 'o', 'P', 'I', 'C', 'K', '_', 'Q', 'B', 0, |
| /* 9992 */ 'S', 'H', 'L', 'L', '_', 'Q', 'B', 0, |
| /* 10000 */ 'R', 'E', 'P', 'L', '_', 'Q', 'B', 0, |
| /* 10008 */ 'S', 'H', 'R', 'L', '_', 'Q', 'B', 0, |
| /* 10016 */ 'C', 'M', 'P', 'G', 'D', 'U', '_', 'E', 'Q', '_', 'Q', 'B', 0, |
| /* 10029 */ 'C', 'M', 'P', 'G', 'U', '_', 'E', 'Q', '_', 'Q', 'B', 0, |
| /* 10041 */ 'P', 's', 'e', 'u', 'd', 'o', 'C', 'M', 'P', 'U', '_', 'E', 'Q', '_', 'Q', 'B', 0, |
| /* 10058 */ 'S', 'H', 'R', 'A', '_', 'R', '_', 'Q', 'B', 0, |
| /* 10068 */ 'S', 'U', 'B', 'U', 'H', '_', 'R', '_', 'Q', 'B', 0, |
| /* 10079 */ 'A', 'D', 'D', 'U', 'H', '_', 'R', '_', 'Q', 'B', 0, |
| /* 10090 */ 'S', 'H', 'R', 'A', 'V', '_', 'R', '_', 'Q', 'B', 0, |
| /* 10101 */ 'A', 'B', 'S', 'Q', '_', 'S', '_', 'Q', 'B', 0, |
| /* 10111 */ 'S', 'U', 'B', 'U', '_', 'S', '_', 'Q', 'B', 0, |
| /* 10121 */ 'A', 'D', 'D', 'U', '_', 'S', '_', 'Q', 'B', 0, |
| /* 10131 */ 'C', 'M', 'P', 'G', 'D', 'U', '_', 'L', 'T', '_', 'Q', 'B', 0, |
| /* 10144 */ 'C', 'M', 'P', 'G', 'U', '_', 'L', 'T', '_', 'Q', 'B', 0, |
| /* 10156 */ 'P', 's', 'e', 'u', 'd', 'o', 'C', 'M', 'P', 'U', '_', 'L', 'T', '_', 'Q', 'B', 0, |
| /* 10173 */ 'S', 'U', 'B', 'U', '_', 'Q', 'B', 0, |
| /* 10181 */ 'A', 'D', 'D', 'U', '_', 'Q', 'B', 0, |
| /* 10189 */ 'S', 'H', 'R', 'A', 'V', '_', 'Q', 'B', 0, |
| /* 10198 */ 'S', 'H', 'L', 'L', 'V', '_', 'Q', 'B', 0, |
| /* 10207 */ 'R', 'E', 'P', 'L', 'V', '_', 'Q', 'B', 0, |
| /* 10216 */ 'S', 'H', 'R', 'L', 'V', '_', 'Q', 'B', 0, |
| /* 10225 */ 'R', 'A', 'D', 'D', 'U', '_', 'W', '_', 'Q', 'B', 0, |
| /* 10236 */ 'S', 'B', 0, |
| /* 10239 */ 'M', 'O', 'D', 'S', 'U', 'B', 0, |
| /* 10246 */ 'G', '_', 'F', 'S', 'U', 'B', 0, |
| /* 10253 */ 'G', '_', 'S', 'T', 'R', 'I', 'C', 'T', '_', 'F', 'S', 'U', 'B', 0, |
| /* 10267 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'F', 'S', 'U', 'B', 0, |
| /* 10284 */ 'P', 's', 'e', 'u', 'd', 'o', 'M', 'S', 'U', 'B', 0, |
| /* 10295 */ 'G', '_', 'S', 'U', 'B', 0, |
| /* 10301 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'S', 'U', 'B', 0, |
| /* 10317 */ 'S', 'R', 'A', '_', 'B', 0, |
| /* 10323 */ 'A', 'D', 'D', '_', 'A', '_', 'B', 0, |
| /* 10331 */ 'M', 'I', 'N', '_', 'A', '_', 'B', 0, |
| /* 10339 */ 'A', 'D', 'D', 'S', '_', 'A', '_', 'B', 0, |
| /* 10348 */ 'M', 'A', 'X', '_', 'A', '_', 'B', 0, |
| /* 10356 */ 'N', 'L', 'O', 'C', '_', 'B', 0, |
| /* 10363 */ 'N', 'L', 'Z', 'C', '_', 'B', 0, |
| /* 10370 */ 'S', 'L', 'D', '_', 'B', 0, |
| /* 10376 */ 'P', 'C', 'K', 'O', 'D', '_', 'B', 0, |
| /* 10384 */ 'I', 'L', 'V', 'O', 'D', '_', 'B', 0, |
| /* 10392 */ 'I', 'N', 'S', 'V', 'E', '_', 'B', 0, |
| /* 10400 */ 'V', 'S', 'H', 'F', '_', 'B', 0, |
| /* 10407 */ 'B', 'N', 'E', 'G', '_', 'B', 0, |
| /* 10414 */ 'S', 'R', 'A', 'I', '_', 'B', 0, |
| /* 10421 */ 'S', 'L', 'D', 'I', '_', 'B', 0, |
| /* 10428 */ 'A', 'N', 'D', 'I', '_', 'B', 0, |
| /* 10435 */ 'B', 'N', 'E', 'G', 'I', '_', 'B', 0, |
| /* 10443 */ 'B', 'S', 'E', 'L', 'I', '_', 'B', 0, |
| /* 10451 */ 'S', 'L', 'L', 'I', '_', 'B', 0, |
| /* 10458 */ 'S', 'R', 'L', 'I', '_', 'B', 0, |
| /* 10465 */ 'B', 'I', 'N', 'S', 'L', 'I', '_', 'B', 0, |
| /* 10474 */ 'C', 'E', 'Q', 'I', '_', 'B', 0, |
| /* 10481 */ 'S', 'R', 'A', 'R', 'I', '_', 'B', 0, |
| /* 10489 */ 'B', 'C', 'L', 'R', 'I', '_', 'B', 0, |
| /* 10497 */ 'S', 'R', 'L', 'R', 'I', '_', 'B', 0, |
| /* 10505 */ 'N', 'O', 'R', 'I', '_', 'B', 0, |
| /* 10512 */ 'X', 'O', 'R', 'I', '_', 'B', 0, |
| /* 10519 */ 'B', 'I', 'N', 'S', 'R', 'I', '_', 'B', 0, |
| /* 10528 */ 'S', 'P', 'L', 'A', 'T', 'I', '_', 'B', 0, |
| /* 10537 */ 'B', 'S', 'E', 'T', 'I', '_', 'B', 0, |
| /* 10545 */ 'S', 'U', 'B', 'V', 'I', '_', 'B', 0, |
| /* 10553 */ 'A', 'D', 'D', 'V', 'I', '_', 'B', 0, |
| /* 10561 */ 'B', 'M', 'Z', 'I', '_', 'B', 0, |
| /* 10568 */ 'B', 'M', 'N', 'Z', 'I', '_', 'B', 0, |
| /* 10576 */ 'F', 'I', 'L', 'L', '_', 'B', 0, |
| /* 10583 */ 'S', 'L', 'L', '_', 'B', 0, |
| /* 10589 */ 'S', 'R', 'L', '_', 'B', 0, |
| /* 10595 */ 'B', 'I', 'N', 'S', 'L', '_', 'B', 0, |
| /* 10603 */ 'I', 'L', 'V', 'L', '_', 'B', 0, |
| /* 10610 */ 'C', 'E', 'Q', '_', 'B', 0, |
| /* 10616 */ 'S', 'R', 'A', 'R', '_', 'B', 0, |
| /* 10623 */ 'B', 'C', 'L', 'R', '_', 'B', 0, |
| /* 10630 */ 'S', 'R', 'L', 'R', '_', 'B', 0, |
| /* 10637 */ 'B', 'I', 'N', 'S', 'R', '_', 'B', 0, |
| /* 10645 */ 'I', 'L', 'V', 'R', '_', 'B', 0, |
| /* 10652 */ 'A', 'S', 'U', 'B', '_', 'S', '_', 'B', 0, |
| /* 10661 */ 'M', 'O', 'D', '_', 'S', '_', 'B', 0, |
| /* 10669 */ 'C', 'L', 'E', '_', 'S', '_', 'B', 0, |
| /* 10677 */ 'A', 'V', 'E', '_', 'S', '_', 'B', 0, |
| /* 10685 */ 'C', 'L', 'E', 'I', '_', 'S', '_', 'B', 0, |
| /* 10694 */ 'M', 'I', 'N', 'I', '_', 'S', '_', 'B', 0, |
| /* 10703 */ 'C', 'L', 'T', 'I', '_', 'S', '_', 'B', 0, |
| /* 10712 */ 'M', 'A', 'X', 'I', '_', 'S', '_', 'B', 0, |
| /* 10721 */ 'M', 'I', 'N', '_', 'S', '_', 'B', 0, |
| /* 10729 */ 'A', 'V', 'E', 'R', '_', 'S', '_', 'B', 0, |
| /* 10738 */ 'S', 'U', 'B', 'S', '_', 'S', '_', 'B', 0, |
| /* 10747 */ 'A', 'D', 'D', 'S', '_', 'S', '_', 'B', 0, |
| /* 10756 */ 'S', 'A', 'T', '_', 'S', '_', 'B', 0, |
| /* 10764 */ 'C', 'L', 'T', '_', 'S', '_', 'B', 0, |
| /* 10772 */ 'S', 'U', 'B', 'S', 'U', 'U', '_', 'S', '_', 'B', 0, |
| /* 10783 */ 'D', 'I', 'V', '_', 'S', '_', 'B', 0, |
| /* 10791 */ 'M', 'A', 'X', '_', 'S', '_', 'B', 0, |
| /* 10799 */ 'C', 'O', 'P', 'Y', '_', 'S', '_', 'B', 0, |
| /* 10808 */ 'S', 'P', 'L', 'A', 'T', '_', 'B', 0, |
| /* 10816 */ 'B', 'S', 'E', 'T', '_', 'B', 0, |
| /* 10823 */ 'P', 'C', 'N', 'T', '_', 'B', 0, |
| /* 10830 */ 'I', 'N', 'S', 'E', 'R', 'T', '_', 'B', 0, |
| /* 10839 */ 'S', 'T', '_', 'B', 0, |
| /* 10844 */ 'A', 'S', 'U', 'B', '_', 'U', '_', 'B', 0, |
| /* 10853 */ 'M', 'O', 'D', '_', 'U', '_', 'B', 0, |
| /* 10861 */ 'C', 'L', 'E', '_', 'U', '_', 'B', 0, |
| /* 10869 */ 'A', 'V', 'E', '_', 'U', '_', 'B', 0, |
| /* 10877 */ 'C', 'L', 'E', 'I', '_', 'U', '_', 'B', 0, |
| /* 10886 */ 'M', 'I', 'N', 'I', '_', 'U', '_', 'B', 0, |
| /* 10895 */ 'C', 'L', 'T', 'I', '_', 'U', '_', 'B', 0, |
| /* 10904 */ 'M', 'A', 'X', 'I', '_', 'U', '_', 'B', 0, |
| /* 10913 */ 'M', 'I', 'N', '_', 'U', '_', 'B', 0, |
| /* 10921 */ 'A', 'V', 'E', 'R', '_', 'U', '_', 'B', 0, |
| /* 10930 */ 'S', 'U', 'B', 'S', '_', 'U', '_', 'B', 0, |
| /* 10939 */ 'A', 'D', 'D', 'S', '_', 'U', '_', 'B', 0, |
| /* 10948 */ 'S', 'U', 'B', 'S', 'U', 'S', '_', 'U', '_', 'B', 0, |
| /* 10959 */ 'S', 'A', 'T', '_', 'U', '_', 'B', 0, |
| /* 10967 */ 'C', 'L', 'T', '_', 'U', '_', 'B', 0, |
| /* 10975 */ 'D', 'I', 'V', '_', 'U', '_', 'B', 0, |
| /* 10983 */ 'M', 'A', 'X', '_', 'U', '_', 'B', 0, |
| /* 10991 */ 'C', 'O', 'P', 'Y', '_', 'U', '_', 'B', 0, |
| /* 11000 */ 'M', 'S', 'U', 'B', 'V', '_', 'B', 0, |
| /* 11008 */ 'M', 'A', 'D', 'D', 'V', '_', 'B', 0, |
| /* 11016 */ 'P', 'C', 'K', 'E', 'V', '_', 'B', 0, |
| /* 11024 */ 'I', 'L', 'V', 'E', 'V', '_', 'B', 0, |
| /* 11032 */ 'M', 'U', 'L', 'V', '_', 'B', 0, |
| /* 11039 */ 'B', 'Z', '_', 'B', 0, |
| /* 11044 */ 'B', 'N', 'Z', '_', 'B', 0, |
| /* 11050 */ 'B', 'C', 0, |
| /* 11053 */ 'B', 'G', 'E', 'C', 0, |
| /* 11058 */ 'B', 'N', 'E', 'C', 0, |
| /* 11063 */ 'J', 'I', 'C', 0, |
| /* 11067 */ 'G', '_', 'I', 'N', 'T', 'R', 'I', 'N', 'S', 'I', 'C', 0, |
| /* 11079 */ 'B', 'A', 'L', 'C', 0, |
| /* 11084 */ 'J', 'I', 'A', 'L', 'C', 0, |
| /* 11090 */ 'B', 'G', 'E', 'Z', 'A', 'L', 'C', 0, |
| /* 11098 */ 'B', 'L', 'E', 'Z', 'A', 'L', 'C', 0, |
| /* 11106 */ 'B', 'N', 'E', 'Z', 'A', 'L', 'C', 0, |
| /* 11114 */ 'B', 'E', 'Q', 'Z', 'A', 'L', 'C', 0, |
| /* 11122 */ 'B', 'G', 'T', 'Z', 'A', 'L', 'C', 0, |
| /* 11130 */ 'B', 'L', 'T', 'Z', 'A', 'L', 'C', 0, |
| /* 11138 */ 'E', 'R', 'E', 'T', 'N', 'C', 0, |
| /* 11145 */ 'G', '_', 'F', 'P', 'T', 'R', 'U', 'N', 'C', 0, |
| /* 11155 */ 'G', '_', 'I', 'N', 'T', 'R', 'I', 'N', 'S', 'I', 'C', '_', 'T', 'R', 'U', 'N', 'C', 0, |
| /* 11173 */ 'G', '_', 'T', 'R', 'U', 'N', 'C', 0, |
| /* 11181 */ 'G', '_', 'B', 'U', 'I', 'L', 'D', '_', 'V', 'E', 'C', 'T', 'O', 'R', '_', 'T', 'R', 'U', 'N', 'C', 0, |
| /* 11202 */ 'S', 'Y', 'N', 'C', 0, |
| /* 11207 */ 'G', '_', 'D', 'Y', 'N', '_', 'S', 'T', 'A', 'C', 'K', 'A', 'L', 'L', 'O', 'C', 0, |
| /* 11224 */ 'L', 'D', 'P', 'C', 0, |
| /* 11229 */ 'A', 'U', 'I', 'P', 'C', 0, |
| /* 11235 */ 'A', 'L', 'U', 'I', 'P', 'C', 0, |
| /* 11242 */ 'A', 'D', 'D', 'I', 'U', 'P', 'C', 0, |
| /* 11250 */ 'L', 'W', 'U', 'P', 'C', 0, |
| /* 11256 */ 'L', 'W', 'P', 'C', 0, |
| /* 11261 */ 'B', 'E', 'Q', 'C', 0, |
| /* 11266 */ 'A', 'D', 'D', 'S', 'C', 0, |
| /* 11272 */ 'B', 'L', 'T', 'C', 0, |
| /* 11277 */ 'B', 'G', 'E', 'U', 'C', 0, |
| /* 11283 */ 'B', 'L', 'T', 'U', 'C', 0, |
| /* 11289 */ 'B', 'N', 'V', 'C', 0, |
| /* 11294 */ 'B', 'O', 'V', 'C', 0, |
| /* 11299 */ 'A', 'D', 'D', 'W', 'C', 0, |
| /* 11305 */ 'B', 'G', 'E', 'Z', 'C', 0, |
| /* 11311 */ 'B', 'L', 'E', 'Z', 'C', 0, |
| /* 11317 */ 'B', 'N', 'E', 'Z', 'C', 0, |
| /* 11323 */ 'B', 'E', 'Q', 'Z', 'C', 0, |
| /* 11329 */ 'B', 'G', 'T', 'Z', 'C', 0, |
| /* 11335 */ 'B', 'L', 'T', 'Z', 'C', 0, |
| /* 11341 */ 'C', 'R', 'C', '3', '2', 'D', 0, |
| /* 11348 */ 'S', 'A', 'A', 'D', 0, |
| /* 11353 */ 'G', '_', 'F', 'M', 'A', 'D', 0, |
| /* 11360 */ 'G', '_', 'I', 'N', 'D', 'E', 'X', 'E', 'D', '_', 'S', 'E', 'X', 'T', 'L', 'O', 'A', 'D', 0, |
| /* 11379 */ 'G', '_', 'S', 'E', 'X', 'T', 'L', 'O', 'A', 'D', 0, |
| /* 11390 */ 'G', '_', 'I', 'N', 'D', 'E', 'X', 'E', 'D', '_', 'Z', 'E', 'X', 'T', 'L', 'O', 'A', 'D', 0, |
| /* 11409 */ 'G', '_', 'Z', 'E', 'X', 'T', 'L', 'O', 'A', 'D', 0, |
| /* 11420 */ 'G', '_', 'I', 'N', 'D', 'E', 'X', 'E', 'D', '_', 'L', 'O', 'A', 'D', 0, |
| /* 11435 */ 'G', '_', 'L', 'O', 'A', 'D', 0, |
| /* 11442 */ 'C', 'R', 'C', '3', '2', 'C', 'D', 0, |
| /* 11450 */ 'S', 'C', 'D', 0, |
| /* 11454 */ 'D', 'A', 'D', 'D', 0, |
| /* 11459 */ 'G', '_', 'V', 'E', 'C', 'R', 'E', 'D', 'U', 'C', 'E', '_', 'F', 'A', 'D', 'D', 0, |
| /* 11476 */ 'G', '_', 'F', 'A', 'D', 'D', 0, |
| /* 11483 */ 'G', '_', 'V', 'E', 'C', 'R', 'E', 'D', 'U', 'C', 'E', '_', 'S', 'E', 'Q', '_', 'F', 'A', 'D', 'D', 0, |
| /* 11504 */ 'G', '_', 'S', 'T', 'R', 'I', 'C', 'T', '_', 'F', 'A', 'D', 'D', 0, |
| /* 11518 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'F', 'A', 'D', 'D', 0, |
| /* 11535 */ 'P', 's', 'e', 'u', 'd', 'o', 'M', 'A', 'D', 'D', 0, |
| /* 11546 */ 'G', '_', 'V', 'E', 'C', 'R', 'E', 'D', 'U', 'C', 'E', '_', 'A', 'D', 'D', 0, |
| /* 11562 */ 'G', '_', 'A', 'D', 'D', 0, |
| /* 11568 */ 'G', '_', 'P', 'T', 'R', '_', 'A', 'D', 'D', 0, |
| /* 11578 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'A', 'D', 'D', 0, |
| /* 11594 */ 'D', 'S', 'H', 'D', 0, |
| /* 11599 */ 'Y', 'I', 'E', 'L', 'D', 0, |
| /* 11605 */ 'L', 'L', 'D', 0, |
| /* 11609 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'N', 'A', 'N', 'D', 0, |
| /* 11626 */ 'G', '_', 'V', 'E', 'C', 'R', 'E', 'D', 'U', 'C', 'E', '_', 'A', 'N', 'D', 0, |
| /* 11642 */ 'G', '_', 'A', 'N', 'D', 0, |
| /* 11648 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'A', 'N', 'D', 0, |
| /* 11664 */ 'P', 'R', 'E', 'P', 'E', 'N', 'D', 0, |
| /* 11672 */ 'A', 'P', 'P', 'E', 'N', 'D', 0, |
| /* 11679 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0, |
| /* 11692 */ 'G', '_', 'B', 'R', 'C', 'O', 'N', 'D', 0, |
| /* 11701 */ 'G', '_', 'L', 'L', 'R', 'O', 'U', 'N', 'D', 0, |
| /* 11711 */ 'G', '_', 'L', 'R', 'O', 'U', 'N', 'D', 0, |
| /* 11720 */ 'G', '_', 'I', 'N', 'T', 'R', 'I', 'N', 'S', 'I', 'C', '_', 'R', 'O', 'U', 'N', 'D', 0, |
| /* 11738 */ 'G', '_', 'I', 'N', 'T', 'R', 'I', 'N', 'S', 'I', 'C', '_', 'F', 'P', 'T', 'R', 'U', 'N', 'C', '_', 'R', 'O', 'U', 'N', 'D', 0, |
| /* 11764 */ 'D', 'M', 'O', 'D', 0, |
| /* 11769 */ 'L', 'O', 'A', 'D', '_', 'S', 'T', 'A', 'C', 'K', '_', 'G', 'U', 'A', 'R', 'D', 0, |
| /* 11786 */ 'S', 'D', 0, |
| /* 11789 */ 'F', 'L', 'O', 'G', '2', '_', 'D', 0, |
| /* 11797 */ 'F', 'E', 'X', 'P', '2', '_', 'D', 0, |
| /* 11805 */ 'M', 'I', 'N', 'A', '_', 'D', 0, |
| /* 11812 */ 'S', 'R', 'A', '_', 'D', 0, |
| /* 11818 */ 'M', 'A', 'X', 'A', '_', 'D', 0, |
| /* 11825 */ 'A', 'D', 'D', '_', 'A', '_', 'D', 0, |
| /* 11833 */ 'F', 'M', 'I', 'N', '_', 'A', '_', 'D', 0, |
| /* 11842 */ 'A', 'D', 'D', 'S', '_', 'A', '_', 'D', 0, |
| /* 11851 */ 'F', 'M', 'A', 'X', '_', 'A', '_', 'D', 0, |
| /* 11860 */ 'F', 'S', 'U', 'B', '_', 'D', 0, |
| /* 11867 */ 'F', 'M', 'S', 'U', 'B', '_', 'D', 0, |
| /* 11875 */ 'N', 'L', 'O', 'C', '_', 'D', 0, |
| /* 11882 */ 'N', 'L', 'Z', 'C', '_', 'D', 0, |
| /* 11889 */ 'F', 'A', 'D', 'D', '_', 'D', 0, |
| /* 11896 */ 'F', 'M', 'A', 'D', 'D', '_', 'D', 0, |
| /* 11904 */ 'S', 'L', 'D', '_', 'D', 0, |
| /* 11910 */ 'P', 'C', 'K', 'O', 'D', '_', 'D', 0, |
| /* 11918 */ 'I', 'L', 'V', 'O', 'D', '_', 'D', 0, |
| /* 11926 */ 'F', 'C', 'L', 'E', '_', 'D', 0, |
| /* 11933 */ 'F', 'S', 'L', 'E', '_', 'D', 0, |
| /* 11940 */ 'C', 'M', 'P', '_', 'S', 'L', 'E', '_', 'D', 0, |
| /* 11950 */ 'F', 'C', 'U', 'L', 'E', '_', 'D', 0, |
| /* 11958 */ 'F', 'S', 'U', 'L', 'E', '_', 'D', 0, |
| /* 11966 */ 'C', 'M', 'P', '_', 'S', 'U', 'L', 'E', '_', 'D', 0, |
| /* 11977 */ 'C', 'M', 'P', '_', 'U', 'L', 'E', '_', 'D', 0, |
| /* 11987 */ 'C', 'M', 'P', '_', 'L', 'E', '_', 'D', 0, |
| /* 11996 */ 'F', 'C', 'N', 'E', '_', 'D', 0, |
| /* 12003 */ 'F', 'S', 'N', 'E', '_', 'D', 0, |
| /* 12010 */ 'F', 'C', 'U', 'N', 'E', '_', 'D', 0, |
| /* 12018 */ 'F', 'S', 'U', 'N', 'E', '_', 'D', 0, |
| /* 12026 */ 'I', 'N', 'S', 'V', 'E', '_', 'D', 0, |
| /* 12034 */ 'F', 'C', 'A', 'F', '_', 'D', 0, |
| /* 12041 */ 'F', 'S', 'A', 'F', '_', 'D', 0, |
| /* 12048 */ 'C', 'M', 'P', '_', 'S', 'A', 'F', '_', 'D', 0, |
| /* 12058 */ 'M', 'S', 'U', 'B', 'F', '_', 'D', 0, |
| /* 12066 */ 'M', 'A', 'D', 'D', 'F', '_', 'D', 0, |
| /* 12074 */ 'V', 'S', 'H', 'F', '_', 'D', 0, |
| /* 12081 */ 'C', 'M', 'P', '_', 'F', '_', 'D', 0, |
| /* 12089 */ 'B', 'N', 'E', 'G', '_', 'D', 0, |
| /* 12096 */ 'S', 'R', 'A', 'I', '_', 'D', 0, |
| /* 12103 */ 'S', 'L', 'D', 'I', '_', 'D', 0, |
| /* 12110 */ 'B', 'N', 'E', 'G', 'I', '_', 'D', 0, |
| /* 12118 */ 'S', 'L', 'L', 'I', '_', 'D', 0, |
| /* 12125 */ 'S', 'R', 'L', 'I', '_', 'D', 0, |
| /* 12132 */ 'B', 'I', 'N', 'S', 'L', 'I', '_', 'D', 0, |
| /* 12141 */ 'C', 'E', 'Q', 'I', '_', 'D', 0, |
| /* 12148 */ 'S', 'R', 'A', 'R', 'I', '_', 'D', 0, |
| /* 12156 */ 'B', 'C', 'L', 'R', 'I', '_', 'D', 0, |
| /* 12164 */ 'S', 'R', 'L', 'R', 'I', '_', 'D', 0, |
| /* 12172 */ 'B', 'I', 'N', 'S', 'R', 'I', '_', 'D', 0, |
| /* 12181 */ 'S', 'P', 'L', 'A', 'T', 'I', '_', 'D', 0, |
| /* 12190 */ 'B', 'S', 'E', 'T', 'I', '_', 'D', 0, |
| /* 12198 */ 'S', 'U', 'B', 'V', 'I', '_', 'D', 0, |
| /* 12206 */ 'A', 'D', 'D', 'V', 'I', '_', 'D', 0, |
| /* 12214 */ 'S', 'E', 'L', '_', 'D', 0, |
| /* 12220 */ 'F', 'I', 'L', 'L', '_', 'D', 0, |
| /* 12227 */ 'S', 'L', 'L', '_', 'D', 0, |
| /* 12233 */ 'F', 'E', 'X', 'U', 'P', 'L', '_', 'D', 0, |
| /* 12242 */ 'F', 'F', 'Q', 'L', '_', 'D', 0, |
| /* 12249 */ 'S', 'R', 'L', '_', 'D', 0, |
| /* 12255 */ 'B', 'I', 'N', 'S', 'L', '_', 'D', 0, |
| /* 12263 */ 'F', 'M', 'U', 'L', '_', 'D', 0, |
| /* 12270 */ 'I', 'L', 'V', 'L', '_', 'D', 0, |
| /* 12277 */ 'F', 'M', 'I', 'N', '_', 'D', 0, |
| /* 12284 */ 'F', 'C', 'U', 'N', '_', 'D', 0, |
| /* 12291 */ 'F', 'S', 'U', 'N', '_', 'D', 0, |
| /* 12298 */ 'C', 'M', 'P', '_', 'S', 'U', 'N', '_', 'D', 0, |
| /* 12308 */ 'C', 'M', 'P', '_', 'U', 'N', '_', 'D', 0, |
| /* 12317 */ 'F', 'R', 'C', 'P', '_', 'D', 0, |
| /* 12324 */ 'F', 'C', 'E', 'Q', '_', 'D', 0, |
| /* 12331 */ 'F', 'S', 'E', 'Q', '_', 'D', 0, |
| /* 12338 */ 'C', 'M', 'P', '_', 'S', 'E', 'Q', '_', 'D', 0, |
| /* 12348 */ 'F', 'C', 'U', 'E', 'Q', '_', 'D', 0, |
| /* 12356 */ 'F', 'S', 'U', 'E', 'Q', '_', 'D', 0, |
| /* 12364 */ 'C', 'M', 'P', '_', 'S', 'U', 'E', 'Q', '_', 'D', 0, |
| /* 12375 */ 'C', 'M', 'P', '_', 'U', 'E', 'Q', '_', 'D', 0, |
| /* 12385 */ 'C', 'M', 'P', '_', 'E', 'Q', '_', 'D', 0, |
| /* 12394 */ 'S', 'R', 'A', 'R', '_', 'D', 0, |
| /* 12401 */ 'L', 'D', 'R', '_', 'D', 0, |
| /* 12407 */ 'B', 'C', 'L', 'R', '_', 'D', 0, |
| /* 12414 */ 'S', 'R', 'L', 'R', '_', 'D', 0, |
| /* 12421 */ 'F', 'C', 'O', 'R', '_', 'D', 0, |
| /* 12428 */ 'F', 'S', 'O', 'R', '_', 'D', 0, |
| /* 12435 */ 'F', 'E', 'X', 'U', 'P', 'R', '_', 'D', 0, |
| /* 12444 */ 'F', 'F', 'Q', 'R', '_', 'D', 0, |
| /* 12451 */ 'B', 'I', 'N', 'S', 'R', '_', 'D', 0, |
| /* 12459 */ 'S', 'T', 'R', '_', 'D', 0, |
| /* 12465 */ 'I', 'L', 'V', 'R', '_', 'D', 0, |
| /* 12472 */ 'F', 'A', 'B', 'S', '_', 'D', 0, |
| /* 12479 */ 'F', 'C', 'L', 'A', 'S', 'S', '_', 'D', 0, |
| /* 12488 */ 'A', 'S', 'U', 'B', '_', 'S', '_', 'D', 0, |
| /* 12497 */ 'H', 'S', 'U', 'B', '_', 'S', '_', 'D', 0, |
| /* 12506 */ 'D', 'P', 'S', 'U', 'B', '_', 'S', '_', 'D', 0, |
| /* 12516 */ 'F', 'T', 'R', 'U', 'N', 'C', '_', 'S', '_', 'D', 0, |
| /* 12527 */ 'H', 'A', 'D', 'D', '_', 'S', '_', 'D', 0, |
| /* 12536 */ 'D', 'P', 'A', 'D', 'D', '_', 'S', '_', 'D', 0, |
| /* 12546 */ 'M', 'O', 'D', '_', 'S', '_', 'D', 0, |
| /* 12554 */ 'C', 'L', 'E', '_', 'S', '_', 'D', 0, |
| /* 12562 */ 'A', 'V', 'E', '_', 'S', '_', 'D', 0, |
| /* 12570 */ 'C', 'L', 'E', 'I', '_', 'S', '_', 'D', 0, |
| /* 12579 */ 'M', 'I', 'N', 'I', '_', 'S', '_', 'D', 0, |
| /* 12588 */ 'C', 'L', 'T', 'I', '_', 'S', '_', 'D', 0, |
| /* 12597 */ 'M', 'A', 'X', 'I', '_', 'S', '_', 'D', 0, |
| /* 12606 */ 'M', 'I', 'N', '_', 'S', '_', 'D', 0, |
| /* 12614 */ 'D', 'O', 'T', 'P', '_', 'S', '_', 'D', 0, |
| /* 12623 */ 'A', 'V', 'E', 'R', '_', 'S', '_', 'D', 0, |
| /* 12632 */ 'S', 'U', 'B', 'S', '_', 'S', '_', 'D', 0, |
| /* 12641 */ 'A', 'D', 'D', 'S', '_', 'S', '_', 'D', 0, |
| /* 12650 */ 'S', 'A', 'T', '_', 'S', '_', 'D', 0, |
| /* 12658 */ 'C', 'L', 'T', '_', 'S', '_', 'D', 0, |
| /* 12666 */ 'F', 'F', 'I', 'N', 'T', '_', 'S', '_', 'D', 0, |
| /* 12676 */ 'F', 'T', 'I', 'N', 'T', '_', 'S', '_', 'D', 0, |
| /* 12686 */ 'S', 'U', 'B', 'S', 'U', 'U', '_', 'S', '_', 'D', 0, |
| /* 12697 */ 'D', 'I', 'V', '_', 'S', '_', 'D', 0, |
| /* 12705 */ 'M', 'A', 'X', '_', 'S', '_', 'D', 0, |
| /* 12713 */ 'C', 'O', 'P', 'Y', '_', 'S', '_', 'D', 0, |
| /* 12722 */ 'S', 'P', 'L', 'A', 'T', '_', 'D', 0, |
| /* 12730 */ 'B', 'S', 'E', 'T', '_', 'D', 0, |
| /* 12737 */ 'F', 'C', 'L', 'T', '_', 'D', 0, |
| /* 12744 */ 'F', 'S', 'L', 'T', '_', 'D', 0, |
| /* 12751 */ 'C', 'M', 'P', '_', 'S', 'L', 'T', '_', 'D', 0, |
| /* 12761 */ 'F', 'C', 'U', 'L', 'T', '_', 'D', 0, |
| /* 12769 */ 'F', 'S', 'U', 'L', 'T', '_', 'D', 0, |
| /* 12777 */ 'C', 'M', 'P', '_', 'S', 'U', 'L', 'T', '_', 'D', 0, |
| /* 12788 */ 'C', 'M', 'P', '_', 'U', 'L', 'T', '_', 'D', 0, |
| /* 12798 */ 'C', 'M', 'P', '_', 'L', 'T', '_', 'D', 0, |
| /* 12807 */ 'P', 'C', 'N', 'T', '_', 'D', 0, |
| /* 12814 */ 'F', 'R', 'I', 'N', 'T', '_', 'D', 0, |
| /* 12822 */ 'I', 'N', 'S', 'E', 'R', 'T', '_', 'D', 0, |
| /* 12831 */ 'F', 'S', 'Q', 'R', 'T', '_', 'D', 0, |
| /* 12839 */ 'F', 'R', 'S', 'Q', 'R', 'T', '_', 'D', 0, |
| /* 12848 */ 'S', 'T', '_', 'D', 0, |
| /* 12853 */ 'A', 'S', 'U', 'B', '_', 'U', '_', 'D', 0, |
| /* 12862 */ 'H', 'S', 'U', 'B', '_', 'U', '_', 'D', 0, |
| /* 12871 */ 'D', 'P', 'S', 'U', 'B', '_', 'U', '_', 'D', 0, |
| /* 12881 */ 'F', 'T', 'R', 'U', 'N', 'C', '_', 'U', '_', 'D', 0, |
| /* 12892 */ 'H', 'A', 'D', 'D', '_', 'U', '_', 'D', 0, |
| /* 12901 */ 'D', 'P', 'A', 'D', 'D', '_', 'U', '_', 'D', 0, |
| /* 12911 */ 'M', 'O', 'D', '_', 'U', '_', 'D', 0, |
| /* 12919 */ 'C', 'L', 'E', '_', 'U', '_', 'D', 0, |
| /* 12927 */ 'A', 'V', 'E', '_', 'U', '_', 'D', 0, |
| /* 12935 */ 'C', 'L', 'E', 'I', '_', 'U', '_', 'D', 0, |
| /* 12944 */ 'M', 'I', 'N', 'I', '_', 'U', '_', 'D', 0, |
| /* 12953 */ 'C', 'L', 'T', 'I', '_', 'U', '_', 'D', 0, |
| /* 12962 */ 'M', 'A', 'X', 'I', '_', 'U', '_', 'D', 0, |
| /* 12971 */ 'M', 'I', 'N', '_', 'U', '_', 'D', 0, |
| /* 12979 */ 'D', 'O', 'T', 'P', '_', 'U', '_', 'D', 0, |
| /* 12988 */ 'A', 'V', 'E', 'R', '_', 'U', '_', 'D', 0, |
| /* 12997 */ 'S', 'U', 'B', 'S', '_', 'U', '_', 'D', 0, |
| /* 13006 */ 'A', 'D', 'D', 'S', '_', 'U', '_', 'D', 0, |
| /* 13015 */ 'S', 'U', 'B', 'S', 'U', 'S', '_', 'U', '_', 'D', 0, |
| /* 13026 */ 'S', 'A', 'T', '_', 'U', '_', 'D', 0, |
| /* 13034 */ 'C', 'L', 'T', '_', 'U', '_', 'D', 0, |
| /* 13042 */ 'F', 'F', 'I', 'N', 'T', '_', 'U', '_', 'D', 0, |
| /* 13052 */ 'F', 'T', 'I', 'N', 'T', '_', 'U', '_', 'D', 0, |
| /* 13062 */ 'D', 'I', 'V', '_', 'U', '_', 'D', 0, |
| /* 13070 */ 'M', 'A', 'X', '_', 'U', '_', 'D', 0, |
| /* 13078 */ 'M', 'S', 'U', 'B', 'V', '_', 'D', 0, |
| /* 13086 */ 'M', 'A', 'D', 'D', 'V', '_', 'D', 0, |
| /* 13094 */ 'P', 'C', 'K', 'E', 'V', '_', 'D', 0, |
| /* 13102 */ 'I', 'L', 'V', 'E', 'V', '_', 'D', 0, |
| /* 13110 */ 'F', 'D', 'I', 'V', '_', 'D', 0, |
| /* 13117 */ 'M', 'U', 'L', 'V', '_', 'D', 0, |
| /* 13124 */ 'P', 's', 'e', 'u', 'd', 'o', 'T', 'R', 'U', 'N', 'C', '_', 'W', '_', 'D', 0, |
| /* 13140 */ 'F', 'M', 'A', 'X', '_', 'D', 0, |
| /* 13147 */ 'B', 'Z', '_', 'D', 0, |
| /* 13152 */ 'S', 'E', 'L', 'N', 'E', 'Z', '_', 'D', 0, |
| /* 13161 */ 'B', 'N', 'Z', '_', 'D', 0, |
| /* 13167 */ 'S', 'E', 'L', 'E', 'Q', 'Z', '_', 'D', 0, |
| /* 13176 */ 'L', 'B', 'E', 0, |
| /* 13180 */ 'P', 'S', 'E', 'U', 'D', 'O', '_', 'P', 'R', 'O', 'B', 'E', 0, |
| /* 13193 */ 'S', 'B', 'E', 0, |
| /* 13197 */ 'G', '_', 'S', 'S', 'U', 'B', 'E', 0, |
| /* 13205 */ 'G', '_', 'U', 'S', 'U', 'B', 'E', 0, |
| /* 13213 */ 'G', '_', 'F', 'E', 'N', 'C', 'E', 0, |
| /* 13221 */ 'A', 'R', 'I', 'T', 'H', '_', 'F', 'E', 'N', 'C', 'E', 0, |
| /* 13233 */ 'R', 'E', 'G', '_', 'S', 'E', 'Q', 'U', 'E', 'N', 'C', 'E', 0, |
| /* 13246 */ 'S', 'C', 'E', 0, |
| /* 13250 */ 'G', '_', 'S', 'A', 'D', 'D', 'E', 0, |
| /* 13258 */ 'G', '_', 'U', 'A', 'D', 'D', 'E', 0, |
| /* 13266 */ 'G', '_', 'F', 'M', 'I', 'N', 'N', 'U', 'M', '_', 'I', 'E', 'E', 'E', 0, |
| /* 13281 */ 'G', '_', 'F', 'M', 'A', 'X', 'N', 'U', 'M', '_', 'I', 'E', 'E', 'E', 0, |
| /* 13296 */ 'C', 'A', 'C', 'H', 'E', 'E', 0, |
| /* 13303 */ 'P', 'R', 'E', 'F', 'E', 0, |
| /* 13309 */ 'B', 'G', 'E', 0, |
| /* 13313 */ 'S', 'G', 'E', 0, |
| /* 13317 */ 'T', 'G', 'E', 0, |
| /* 13321 */ 'C', 'A', 'C', 'H', 'E', 0, |
| /* 13327 */ 'L', 'H', 'E', 0, |
| /* 13331 */ 'S', 'H', 'E', 0, |
| /* 13335 */ 'S', 'I', 'G', 'R', 'I', 'E', 0, |
| /* 13342 */ 'G', '_', 'J', 'U', 'M', 'P', '_', 'T', 'A', 'B', 'L', 'E', 0, |
| /* 13355 */ 'B', 'U', 'N', 'D', 'L', 'E', 0, |
| /* 13362 */ 'L', 'L', 'E', 0, |
| /* 13366 */ 'S', 'L', 'E', 0, |
| /* 13370 */ 'L', 'W', 'L', 'E', 0, |
| /* 13375 */ 'S', 'W', 'L', 'E', 0, |
| /* 13380 */ 'B', 'N', 'E', 0, |
| /* 13384 */ 'G', '_', 'M', 'E', 'M', 'C', 'P', 'Y', '_', 'I', 'N', 'L', 'I', 'N', 'E', 0, |
| /* 13400 */ 'S', 'N', 'E', 0, |
| /* 13404 */ 'T', 'N', 'E', 0, |
| /* 13408 */ 'L', 'O', 'C', 'A', 'L', '_', 'E', 'S', 'C', 'A', 'P', 'E', 0, |
| /* 13421 */ 'D', 'V', 'P', 'E', 0, |
| /* 13426 */ 'E', 'V', 'P', 'E', 0, |
| /* 13431 */ 'G', '_', 'I', 'N', 'D', 'E', 'X', 'E', 'D', '_', 'S', 'T', 'O', 'R', 'E', 0, |
| /* 13447 */ 'G', '_', 'S', 'T', 'O', 'R', 'E', 0, |
| /* 13455 */ 'L', 'W', 'R', 'E', 0, |
| /* 13460 */ 'S', 'W', 'R', 'E', 0, |
| /* 13465 */ 'G', '_', 'B', 'I', 'T', 'R', 'E', 'V', 'E', 'R', 'S', 'E', 0, |
| /* 13478 */ 'P', 'A', 'U', 'S', 'E', 0, |
| /* 13484 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0, |
| /* 13494 */ 'G', '_', 'G', 'L', 'O', 'B', 'A', 'L', '_', 'V', 'A', 'L', 'U', 'E', 0, |
| /* 13509 */ 'G', '_', 'M', 'E', 'M', 'M', 'O', 'V', 'E', 0, |
| /* 13519 */ 'L', 'W', 'E', 0, |
| /* 13523 */ 'S', 'W', 'E', 0, |
| /* 13527 */ 'G', '_', 'F', 'R', 'E', 'E', 'Z', 'E', 0, |
| /* 13536 */ 'G', '_', 'F', 'C', 'A', 'N', 'O', 'N', 'I', 'C', 'A', 'L', 'I', 'Z', 'E', 0, |
| /* 13552 */ 'L', 'B', 'u', 'E', 0, |
| /* 13557 */ 'L', 'H', 'u', 'E', 0, |
| /* 13562 */ 'B', 'C', '1', 'F', 0, |
| /* 13567 */ 'G', '_', 'C', 'T', 'L', 'Z', '_', 'Z', 'E', 'R', 'O', '_', 'U', 'N', 'D', 'E', 'F', 0, |
| /* 13585 */ 'G', '_', 'C', 'T', 'T', 'Z', '_', 'Z', 'E', 'R', 'O', '_', 'U', 'N', 'D', 'E', 'F', 0, |
| /* 13603 */ 'G', '_', 'I', 'M', 'P', 'L', 'I', 'C', 'I', 'T', '_', 'D', 'E', 'F', 0, |
| /* 13618 */ 'P', 'R', 'E', 'F', 0, |
| /* 13623 */ 'D', 'B', 'G', '_', 'I', 'N', 'S', 'T', 'R', '_', 'R', 'E', 'F', 0, |
| /* 13637 */ 'T', 'L', 'B', 'I', 'N', 'V', 'F', 0, |
| /* 13645 */ 'T', 'L', 'B', 'G', 'I', 'N', 'V', 'F', 0, |
| /* 13654 */ 'G', '_', 'F', 'N', 'E', 'G', 0, |
| /* 13661 */ 'T', 'A', 'I', 'L', 'C', 'A', 'L', 'L', 'H', 'B', '6', '4', 'R', '6', 'R', 'E', 'G', 0, |
| /* 13679 */ 'T', 'A', 'I', 'L', 'C', 'A', 'L', 'L', '6', '4', 'R', '6', 'R', 'E', 'G', 0, |
| /* 13695 */ 'T', 'A', 'I', 'L', 'C', 'A', 'L', 'L', 'H', 'B', 'R', '6', 'R', 'E', 'G', 0, |
| /* 13711 */ 'T', 'A', 'I', 'L', 'C', 'A', 'L', 'L', 'R', '6', 'R', 'E', 'G', 0, |
| /* 13725 */ 'E', 'X', 'T', 'R', 'A', 'C', 'T', '_', 'S', 'U', 'B', 'R', 'E', 'G', 0, |
| /* 13740 */ 'I', 'N', 'S', 'E', 'R', 'T', '_', 'S', 'U', 'B', 'R', 'E', 'G', 0, |
| /* 13754 */ 'T', 'A', 'I', 'L', 'C', 'A', 'L', 'L', 'R', 'E', 'G', 0, |
| /* 13766 */ 'G', '_', 'S', 'E', 'X', 'T', '_', 'I', 'N', 'R', 'E', 'G', 0, |
| /* 13779 */ 'S', 'U', 'B', 'R', 'E', 'G', '_', 'T', 'O', '_', 'R', 'E', 'G', 0, |
| /* 13793 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'C', 'M', 'P', 'X', 'C', 'H', 'G', 0, |
| /* 13810 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'X', 'C', 'H', 'G', 0, |
| /* 13827 */ 'G', '_', 'F', 'L', 'O', 'G', 0, |
| /* 13834 */ 'G', '_', 'V', 'A', 'A', 'R', 'G', 0, |
| /* 13842 */ 'P', 'R', 'E', 'A', 'L', 'L', 'O', 'C', 'A', 'T', 'E', 'D', '_', 'A', 'R', 'G', 0, |
| /* 13859 */ 'C', 'R', 'C', '3', '2', 'H', 0, |
| /* 13866 */ 'D', 'S', 'B', 'H', 0, |
| /* 13871 */ 'W', 'S', 'B', 'H', 0, |
| /* 13876 */ 'C', 'R', 'C', '3', '2', 'C', 'H', 0, |
| /* 13884 */ 'S', 'E', 'H', 0, |
| /* 13888 */ 'G', '_', 'S', 'M', 'U', 'L', 'H', 0, |
| /* 13896 */ 'G', '_', 'U', 'M', 'U', 'L', 'H', 0, |
| /* 13904 */ 'S', 'H', 'R', 'A', '_', 'P', 'H', 0, |
| /* 13912 */ 'P', 'R', 'E', 'C', 'R', 'Q', '_', 'Q', 'B', '_', 'P', 'H', 0, |
| /* 13925 */ 'P', 'R', 'E', 'C', 'R', '_', 'Q', 'B', '_', 'P', 'H', 0, |
| /* 13937 */ 'P', 'R', 'E', 'C', 'R', 'Q', 'U', '_', 'S', '_', 'Q', 'B', '_', 'P', 'H', 0, |
| /* 13953 */ 'P', 's', 'e', 'u', 'd', 'o', 'C', 'M', 'P', '_', 'L', 'E', '_', 'P', 'H', 0, |
| /* 13969 */ 'S', 'U', 'B', 'Q', 'H', '_', 'P', 'H', 0, |
| /* 13978 */ 'A', 'D', 'D', 'Q', 'H', '_', 'P', 'H', 0, |
| /* 13987 */ 'P', 's', 'e', 'u', 'd', 'o', 'P', 'I', 'C', 'K', '_', 'P', 'H', 0, |
| /* 14001 */ 'S', 'H', 'L', 'L', '_', 'P', 'H', 0, |
| /* 14009 */ 'R', 'E', 'P', 'L', '_', 'P', 'H', 0, |
| /* 14017 */ 'S', 'H', 'R', 'L', '_', 'P', 'H', 0, |
| /* 14025 */ 'P', 'A', 'C', 'K', 'R', 'L', '_', 'P', 'H', 0, |
| /* 14035 */ 'M', 'U', 'L', '_', 'P', 'H', 0, |
| /* 14042 */ 'S', 'U', 'B', 'Q', '_', 'P', 'H', 0, |
| /* 14050 */ 'A', 'D', 'D', 'Q', '_', 'P', 'H', 0, |
| /* 14058 */ 'P', 's', 'e', 'u', 'd', 'o', 'C', 'M', 'P', '_', 'E', 'Q', '_', 'P', 'H', 0, |
| /* 14074 */ 'S', 'H', 'R', 'A', '_', 'R', '_', 'P', 'H', 0, |
| /* 14084 */ 'S', 'U', 'B', 'Q', 'H', '_', 'R', '_', 'P', 'H', 0, |
| /* 14095 */ 'A', 'D', 'D', 'Q', 'H', '_', 'R', '_', 'P', 'H', 0, |
| /* 14106 */ 'S', 'H', 'R', 'A', 'V', '_', 'R', '_', 'P', 'H', 0, |
| /* 14117 */ 'M', 'U', 'L', 'Q', '_', 'R', 'S', '_', 'P', 'H', 0, |
| /* 14128 */ 'S', 'H', 'L', 'L', '_', 'S', '_', 'P', 'H', 0, |
| /* 14138 */ 'M', 'U', 'L', '_', 'S', '_', 'P', 'H', 0, |
| /* 14147 */ 'S', 'U', 'B', 'Q', '_', 'S', '_', 'P', 'H', 0, |
| /* 14157 */ 'A', 'D', 'D', 'Q', '_', 'S', '_', 'P', 'H', 0, |
| /* 14167 */ 'M', 'U', 'L', 'Q', '_', 'S', '_', 'P', 'H', 0, |
| /* 14177 */ 'A', 'B', 'S', 'Q', '_', 'S', '_', 'P', 'H', 0, |
| /* 14187 */ 'S', 'U', 'B', 'U', '_', 'S', '_', 'P', 'H', 0, |
| /* 14197 */ 'A', 'D', 'D', 'U', '_', 'S', '_', 'P', 'H', 0, |
| /* 14207 */ 'S', 'H', 'L', 'L', 'V', '_', 'S', '_', 'P', 'H', 0, |
| /* 14218 */ 'P', 's', 'e', 'u', 'd', 'o', 'C', 'M', 'P', '_', 'L', 'T', '_', 'P', 'H', 0, |
| /* 14234 */ 'S', 'U', 'B', 'U', '_', 'P', 'H', 0, |
| /* 14242 */ 'A', 'D', 'D', 'U', '_', 'P', 'H', 0, |
| /* 14250 */ 'S', 'H', 'R', 'A', 'V', '_', 'P', 'H', 0, |
| /* 14259 */ 'S', 'H', 'L', 'L', 'V', '_', 'P', 'H', 0, |
| /* 14268 */ 'R', 'E', 'P', 'L', 'V', '_', 'P', 'H', 0, |
| /* 14277 */ 'S', 'H', 'R', 'L', 'V', '_', 'P', 'H', 0, |
| /* 14286 */ 'D', 'P', 'A', '_', 'W', '_', 'P', 'H', 0, |
| /* 14295 */ 'M', 'U', 'L', 'S', 'A', '_', 'W', '_', 'P', 'H', 0, |
| /* 14306 */ 'D', 'P', 'A', 'Q', 'X', '_', 'S', 'A', '_', 'W', '_', 'P', 'H', 0, |
| /* 14320 */ 'D', 'P', 'S', 'Q', 'X', '_', 'S', 'A', '_', 'W', '_', 'P', 'H', 0, |
| /* 14334 */ 'D', 'P', 'S', '_', 'W', '_', 'P', 'H', 0, |
| /* 14343 */ 'D', 'P', 'A', 'Q', '_', 'S', '_', 'W', '_', 'P', 'H', 0, |
| /* 14355 */ 'M', 'U', 'L', 'S', 'A', 'Q', '_', 'S', '_', 'W', '_', 'P', 'H', 0, |
| /* 14369 */ 'D', 'P', 'S', 'Q', '_', 'S', '_', 'W', '_', 'P', 'H', 0, |
| /* 14381 */ 'D', 'P', 'A', 'Q', 'X', '_', 'S', '_', 'W', '_', 'P', 'H', 0, |
| /* 14394 */ 'D', 'P', 'S', 'Q', 'X', '_', 'S', '_', 'W', '_', 'P', 'H', 0, |
| /* 14407 */ 'D', 'P', 'A', 'X', '_', 'W', '_', 'P', 'H', 0, |
| /* 14417 */ 'D', 'P', 'S', 'X', '_', 'W', '_', 'P', 'H', 0, |
| /* 14427 */ 'S', 'H', 0, |
| /* 14430 */ 'D', 'M', 'U', 'H', 0, |
| /* 14435 */ 'S', 'R', 'A', '_', 'H', 0, |
| /* 14441 */ 'A', 'D', 'D', '_', 'A', '_', 'H', 0, |
| /* 14449 */ 'M', 'I', 'N', '_', 'A', '_', 'H', 0, |
| /* 14457 */ 'A', 'D', 'D', 'S', '_', 'A', '_', 'H', 0, |
| /* 14466 */ 'M', 'A', 'X', '_', 'A', '_', 'H', 0, |
| /* 14474 */ 'N', 'L', 'O', 'C', '_', 'H', 0, |
| /* 14481 */ 'N', 'L', 'Z', 'C', '_', 'H', 0, |
| /* 14488 */ 'S', 'L', 'D', '_', 'H', 0, |
| /* 14494 */ 'P', 'C', 'K', 'O', 'D', '_', 'H', 0, |
| /* 14502 */ 'I', 'L', 'V', 'O', 'D', '_', 'H', 0, |
| /* 14510 */ 'I', 'N', 'S', 'V', 'E', '_', 'H', 0, |
| /* 14518 */ 'V', 'S', 'H', 'F', '_', 'H', 0, |
| /* 14525 */ 'B', 'N', 'E', 'G', '_', 'H', 0, |
| /* 14532 */ 'S', 'R', 'A', 'I', '_', 'H', 0, |
| /* 14539 */ 'S', 'L', 'D', 'I', '_', 'H', 0, |
| /* 14546 */ 'B', 'N', 'E', 'G', 'I', '_', 'H', 0, |
| /* 14554 */ 'S', 'L', 'L', 'I', '_', 'H', 0, |
| /* 14561 */ 'S', 'R', 'L', 'I', '_', 'H', 0, |
| /* 14568 */ 'B', 'I', 'N', 'S', 'L', 'I', '_', 'H', 0, |
| /* 14577 */ 'C', 'E', 'Q', 'I', '_', 'H', 0, |
| /* 14584 */ 'S', 'R', 'A', 'R', 'I', '_', 'H', 0, |
| /* 14592 */ 'B', 'C', 'L', 'R', 'I', '_', 'H', 0, |
| /* 14600 */ 'S', 'R', 'L', 'R', 'I', '_', 'H', 0, |
| /* 14608 */ 'B', 'I', 'N', 'S', 'R', 'I', '_', 'H', 0, |
| /* 14617 */ 'S', 'P', 'L', 'A', 'T', 'I', '_', 'H', 0, |
| /* 14626 */ 'B', 'S', 'E', 'T', 'I', '_', 'H', 0, |
| /* 14634 */ 'S', 'U', 'B', 'V', 'I', '_', 'H', 0, |
| /* 14642 */ 'A', 'D', 'D', 'V', 'I', '_', 'H', 0, |
| /* 14650 */ 'F', 'I', 'L', 'L', '_', 'H', 0, |
| /* 14657 */ 'S', 'L', 'L', '_', 'H', 0, |
| /* 14663 */ 'S', 'R', 'L', '_', 'H', 0, |
| /* 14669 */ 'B', 'I', 'N', 'S', 'L', '_', 'H', 0, |
| /* 14677 */ 'I', 'L', 'V', 'L', '_', 'H', 0, |
| /* 14684 */ 'F', 'E', 'X', 'D', 'O', '_', 'H', 0, |
| /* 14692 */ 'C', 'E', 'Q', '_', 'H', 0, |
| /* 14698 */ 'F', 'T', 'Q', '_', 'H', 0, |
| /* 14704 */ 'M', 'S', 'U', 'B', '_', 'Q', '_', 'H', 0, |
| /* 14713 */ 'M', 'A', 'D', 'D', '_', 'Q', '_', 'H', 0, |
| /* 14722 */ 'M', 'U', 'L', '_', 'Q', '_', 'H', 0, |
| /* 14730 */ 'M', 'S', 'U', 'B', 'R', '_', 'Q', '_', 'H', 0, |
| /* 14740 */ 'M', 'A', 'D', 'D', 'R', '_', 'Q', '_', 'H', 0, |
| /* 14750 */ 'M', 'U', 'L', 'R', '_', 'Q', '_', 'H', 0, |
| /* 14759 */ 'S', 'R', 'A', 'R', '_', 'H', 0, |
| /* 14766 */ 'B', 'C', 'L', 'R', '_', 'H', 0, |
| /* 14773 */ 'S', 'R', 'L', 'R', '_', 'H', 0, |
| /* 14780 */ 'B', 'I', 'N', 'S', 'R', '_', 'H', 0, |
| /* 14788 */ 'I', 'L', 'V', 'R', '_', 'H', 0, |
| /* 14795 */ 'A', 'S', 'U', 'B', '_', 'S', '_', 'H', 0, |
| /* 14804 */ 'H', 'S', 'U', 'B', '_', 'S', '_', 'H', 0, |
| /* 14813 */ 'D', 'P', 'S', 'U', 'B', '_', 'S', '_', 'H', 0, |
| /* 14823 */ 'H', 'A', 'D', 'D', '_', 'S', '_', 'H', 0, |
| /* 14832 */ 'D', 'P', 'A', 'D', 'D', '_', 'S', '_', 'H', 0, |
| /* 14842 */ 'M', 'O', 'D', '_', 'S', '_', 'H', 0, |
| /* 14850 */ 'C', 'L', 'E', '_', 'S', '_', 'H', 0, |
| /* 14858 */ 'A', 'V', 'E', '_', 'S', '_', 'H', 0, |
| /* 14866 */ 'C', 'L', 'E', 'I', '_', 'S', '_', 'H', 0, |
| /* 14875 */ 'M', 'I', 'N', 'I', '_', 'S', '_', 'H', 0, |
| /* 14884 */ 'C', 'L', 'T', 'I', '_', 'S', '_', 'H', 0, |
| /* 14893 */ 'M', 'A', 'X', 'I', '_', 'S', '_', 'H', 0, |
| /* 14902 */ 'M', 'I', 'N', '_', 'S', '_', 'H', 0, |
| /* 14910 */ 'D', 'O', 'T', 'P', '_', 'S', '_', 'H', 0, |
| /* 14919 */ 'A', 'V', 'E', 'R', '_', 'S', '_', 'H', 0, |
| /* 14928 */ 'E', 'X', 'T', 'R', '_', 'S', '_', 'H', 0, |
| /* 14937 */ 'S', 'U', 'B', 'S', '_', 'S', '_', 'H', 0, |
| /* 14946 */ 'A', 'D', 'D', 'S', '_', 'S', '_', 'H', 0, |
| /* 14955 */ 'S', 'A', 'T', '_', 'S', '_', 'H', 0, |
| /* 14963 */ 'C', 'L', 'T', '_', 'S', '_', 'H', 0, |
| /* 14971 */ 'S', 'U', 'B', 'S', 'U', 'U', '_', 'S', '_', 'H', 0, |
| /* 14982 */ 'D', 'I', 'V', '_', 'S', '_', 'H', 0, |
| /* 14990 */ 'E', 'X', 'T', 'R', 'V', '_', 'S', '_', 'H', 0, |
| /* 15000 */ 'M', 'A', 'X', '_', 'S', '_', 'H', 0, |
| /* 15008 */ 'C', 'O', 'P', 'Y', '_', 'S', '_', 'H', 0, |
| /* 15017 */ 'S', 'P', 'L', 'A', 'T', '_', 'H', 0, |
| /* 15025 */ 'B', 'S', 'E', 'T', '_', 'H', 0, |
| /* 15032 */ 'P', 'C', 'N', 'T', '_', 'H', 0, |
| /* 15039 */ 'I', 'N', 'S', 'E', 'R', 'T', '_', 'H', 0, |
| /* 15048 */ 'S', 'T', '_', 'H', 0, |
| /* 15053 */ 'A', 'S', 'U', 'B', '_', 'U', '_', 'H', 0, |
| /* 15062 */ 'H', 'S', 'U', 'B', '_', 'U', '_', 'H', 0, |
| /* 15071 */ 'D', 'P', 'S', 'U', 'B', '_', 'U', '_', 'H', 0, |
| /* 15081 */ 'H', 'A', 'D', 'D', '_', 'U', '_', 'H', 0, |
| /* 15090 */ 'D', 'P', 'A', 'D', 'D', '_', 'U', '_', 'H', 0, |
| /* 15100 */ 'M', 'O', 'D', '_', 'U', '_', 'H', 0, |
| /* 15108 */ 'C', 'L', 'E', '_', 'U', '_', 'H', 0, |
| /* 15116 */ 'A', 'V', 'E', '_', 'U', '_', 'H', 0, |
| /* 15124 */ 'C', 'L', 'E', 'I', '_', 'U', '_', 'H', 0, |
| /* 15133 */ 'M', 'I', 'N', 'I', '_', 'U', '_', 'H', 0, |
| /* 15142 */ 'C', 'L', 'T', 'I', '_', 'U', '_', 'H', 0, |
| /* 15151 */ 'M', 'A', 'X', 'I', '_', 'U', '_', 'H', 0, |
| /* 15160 */ 'M', 'I', 'N', '_', 'U', '_', 'H', 0, |
| /* 15168 */ 'D', 'O', 'T', 'P', '_', 'U', '_', 'H', 0, |
| /* 15177 */ 'A', 'V', 'E', 'R', '_', 'U', '_', 'H', 0, |
| /* 15186 */ 'S', 'U', 'B', 'S', '_', 'U', '_', 'H', 0, |
| /* 15195 */ 'A', 'D', 'D', 'S', '_', 'U', '_', 'H', 0, |
| /* 15204 */ 'S', 'U', 'B', 'S', 'U', 'S', '_', 'U', '_', 'H', 0, |
| /* 15215 */ 'S', 'A', 'T', '_', 'U', '_', 'H', 0, |
| /* 15223 */ 'C', 'L', 'T', '_', 'U', '_', 'H', 0, |
| /* 15231 */ 'D', 'I', 'V', '_', 'U', '_', 'H', 0, |
| /* 15239 */ 'M', 'A', 'X', '_', 'U', '_', 'H', 0, |
| /* 15247 */ 'C', 'O', 'P', 'Y', '_', 'U', '_', 'H', 0, |
| /* 15256 */ 'M', 'S', 'U', 'B', 'V', '_', 'H', 0, |
| /* 15264 */ 'M', 'A', 'D', 'D', 'V', '_', 'H', 0, |
| /* 15272 */ 'P', 'C', 'K', 'E', 'V', '_', 'H', 0, |
| /* 15280 */ 'I', 'L', 'V', 'E', 'V', '_', 'H', 0, |
| /* 15288 */ 'M', 'U', 'L', 'V', '_', 'H', 0, |
| /* 15295 */ 'B', 'Z', '_', 'H', 0, |
| /* 15300 */ 'B', 'N', 'Z', '_', 'H', 0, |
| /* 15306 */ 'S', 'Y', 'N', 'C', 'I', 0, |
| /* 15312 */ 'D', 'I', 0, |
| /* 15315 */ 'T', 'G', 'E', 'I', 0, |
| /* 15320 */ 'T', 'N', 'E', 'I', 0, |
| /* 15325 */ 'D', 'A', 'H', 'I', 0, |
| /* 15330 */ 'P', 's', 'e', 'u', 'd', 'o', 'M', 'F', 'H', 'I', 0, |
| /* 15341 */ 'P', 's', 'e', 'u', 'd', 'o', 'M', 'T', 'L', 'O', 'H', 'I', 0, |
| /* 15354 */ 'D', 'B', 'G', '_', 'P', 'H', 'I', 0, |
| /* 15362 */ 'M', 'F', 'T', 'H', 'I', 0, |
| /* 15368 */ 'M', 'T', 'H', 'I', 0, |
| /* 15373 */ 'M', 'T', 'T', 'H', 'I', 0, |
| /* 15379 */ 'T', 'E', 'Q', 'I', 0, |
| /* 15384 */ 'G', '_', 'F', 'P', 'T', 'O', 'S', 'I', 0, |
| /* 15393 */ 'D', 'A', 'T', 'I', 0, |
| /* 15398 */ 'T', 'L', 'T', 'I', 0, |
| /* 15403 */ 'D', 'A', 'U', 'I', 0, |
| /* 15408 */ 'G', '_', 'F', 'P', 'T', 'O', 'U', 'I', 0, |
| /* 15417 */ 'G', 'I', 'N', 'V', 'I', 0, |
| /* 15423 */ 'T', 'L', 'B', 'W', 'I', 0, |
| /* 15429 */ 'T', 'L', 'B', 'G', 'W', 'I', 0, |
| /* 15436 */ 'G', '_', 'F', 'P', 'O', 'W', 'I', 0, |
| /* 15444 */ 'M', 'O', 'V', 'N', '_', 'I', '6', '4', '_', 'I', 0, |
| /* 15455 */ 'M', 'O', 'V', 'Z', '_', 'I', '6', '4', '_', 'I', 0, |
| /* 15466 */ 'M', 'O', 'V', 'F', '_', 'I', 0, |
| /* 15473 */ 'P', 's', 'e', 'u', 'd', 'o', 'S', 'E', 'L', 'E', 'C', 'T', 'F', 'P', '_', 'F', '_', 'I', 0, |
| /* 15492 */ 'M', 'O', 'V', 'N', '_', 'I', '_', 'I', 0, |
| /* 15501 */ 'M', 'O', 'V', 'Z', '_', 'I', '_', 'I', 0, |
| /* 15510 */ 'P', 's', 'e', 'u', 'd', 'o', 'D', '_', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'I', 0, |
| /* 15527 */ 'P', 's', 'e', 'u', 'd', 'o', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'I', 0, |
| /* 15542 */ 'M', 'O', 'V', 'T', '_', 'I', 0, |
| /* 15549 */ 'P', 's', 'e', 'u', 'd', 'o', 'S', 'E', 'L', 'E', 'C', 'T', 'F', 'P', '_', 'T', '_', 'I', 0, |
| /* 15568 */ 'J', 0, |
| /* 15570 */ 'B', 'R', 'E', 'A', 'K', 0, |
| /* 15576 */ 'F', 'O', 'R', 'K', 0, |
| /* 15581 */ 'G', '_', 'P', 'T', 'R', 'M', 'A', 'S', 'K', 0, |
| /* 15591 */ 'B', 'A', 'L', 0, |
| /* 15595 */ 'J', 'A', 'L', 0, |
| /* 15599 */ 'B', 'G', 'E', 'Z', 'A', 'L', 0, |
| /* 15606 */ 'B', 'L', 'T', 'Z', 'A', 'L', 0, |
| /* 15613 */ 'M', 'U', 'L', 'E', 'U', '_', 'S', '_', 'P', 'H', '_', 'Q', 'B', 'L', 0, |
| /* 15628 */ 'P', 'R', 'E', 'C', 'E', 'U', '_', 'P', 'H', '_', 'Q', 'B', 'L', 0, |
| /* 15642 */ 'P', 'R', 'E', 'C', 'E', 'Q', 'U', '_', 'P', 'H', '_', 'Q', 'B', 'L', 0, |
| /* 15657 */ 'D', 'P', 'A', 'U', '_', 'H', '_', 'Q', 'B', 'L', 0, |
| /* 15668 */ 'D', 'P', 'S', 'U', '_', 'H', '_', 'Q', 'B', 'L', 0, |
| /* 15679 */ 'L', 'D', 'L', 0, |
| /* 15683 */ 'S', 'D', 'L', 0, |
| /* 15687 */ 'G', 'C', '_', 'L', 'A', 'B', 'E', 'L', 0, |
| /* 15696 */ 'D', 'B', 'G', '_', 'L', 'A', 'B', 'E', 'L', 0, |
| /* 15706 */ 'E', 'H', '_', 'L', 'A', 'B', 'E', 'L', 0, |
| /* 15715 */ 'A', 'N', 'N', 'O', 'T', 'A', 'T', 'I', 'O', 'N', '_', 'L', 'A', 'B', 'E', 'L', 0, |
| /* 15732 */ 'B', 'G', 'E', 'L', 0, |
| /* 15737 */ 'B', 'L', 'E', 'L', 0, |
| /* 15742 */ 'B', 'N', 'E', 'L', 0, |
| /* 15747 */ 'I', 'C', 'A', 'L', 'L', '_', 'B', 'R', 'A', 'N', 'C', 'H', '_', 'F', 'U', 'N', 'N', 'E', 'L', 0, |
| /* 15767 */ 'B', 'C', '1', 'F', 'L', 0, |
| /* 15773 */ 'M', 'A', 'Q', '_', 'S', 'A', '_', 'W', '_', 'P', 'H', 'L', 0, |
| /* 15786 */ 'P', 'R', 'E', 'C', 'E', 'Q', '_', 'W', '_', 'P', 'H', 'L', 0, |
| /* 15799 */ 'M', 'A', 'Q', '_', 'S', '_', 'W', '_', 'P', 'H', 'L', 0, |
| /* 15811 */ 'M', 'U', 'L', 'E', 'Q', '_', 'S', '_', 'W', '_', 'P', 'H', 'L', 0, |
| /* 15825 */ 'G', '_', 'F', 'S', 'H', 'L', 0, |
| /* 15832 */ 'G', '_', 'S', 'H', 'L', 0, |
| /* 15838 */ 'G', '_', 'F', 'C', 'E', 'I', 'L', 0, |
| /* 15846 */ 'T', 'A', 'I', 'L', 'C', 'A', 'L', 'L', 0, |
| /* 15855 */ 'H', 'Y', 'P', 'C', 'A', 'L', 'L', 0, |
| /* 15863 */ 'S', 'Y', 'S', 'C', 'A', 'L', 'L', 0, |
| /* 15871 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'T', 'A', 'I', 'L', '_', 'C', 'A', 'L', 'L', 0, |
| /* 15891 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'T', 'Y', 'P', 'E', 'D', '_', 'E', 'V', 'E', 'N', 'T', '_', 'C', 'A', 'L', 'L', 0, |
| /* 15918 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'E', 'V', 'E', 'N', 'T', '_', 'C', 'A', 'L', 'L', 0, |
| /* 15939 */ 'F', 'E', 'N', 'T', 'R', 'Y', '_', 'C', 'A', 'L', 'L', 0, |
| /* 15951 */ 'B', 'G', 'E', 'Z', 'A', 'L', 'L', 0, |
| /* 15959 */ 'B', 'L', 'T', 'Z', 'A', 'L', 'L', 0, |
| /* 15967 */ 'K', 'I', 'L', 'L', 0, |
| /* 15972 */ 'D', 'S', 'L', 'L', 0, |
| /* 15977 */ 'D', 'R', 'O', 'L', 0, |
| /* 15982 */ 'B', 'E', 'Q', 'L', 0, |
| /* 15987 */ 'D', 'S', 'R', 'L', 0, |
| /* 15992 */ 'B', 'C', '1', 'T', 'L', 0, |
| /* 15998 */ 'B', 'G', 'T', 'L', 0, |
| /* 16003 */ 'B', 'L', 'T', 'L', 0, |
| /* 16008 */ 'G', '_', 'R', 'O', 'T', 'L', 0, |
| /* 16015 */ 'B', 'G', 'E', 'U', 'L', 0, |
| /* 16021 */ 'B', 'L', 'E', 'U', 'L', 0, |
| /* 16027 */ 'D', 'M', 'U', 'L', 0, |
| /* 16032 */ 'G', '_', 'V', 'E', 'C', 'R', 'E', 'D', 'U', 'C', 'E', '_', 'F', 'M', 'U', 'L', 0, |
| /* 16049 */ 'G', '_', 'F', 'M', 'U', 'L', 0, |
| /* 16056 */ 'G', '_', 'V', 'E', 'C', 'R', 'E', 'D', 'U', 'C', 'E', '_', 'S', 'E', 'Q', '_', 'F', 'M', 'U', 'L', 0, |
| /* 16077 */ 'G', '_', 'S', 'T', 'R', 'I', 'C', 'T', '_', 'F', 'M', 'U', 'L', 0, |
| /* 16091 */ 'G', '_', 'V', 'E', 'C', 'R', 'E', 'D', 'U', 'C', 'E', '_', 'M', 'U', 'L', 0, |
| /* 16107 */ 'G', '_', 'M', 'U', 'L', 0, |
| /* 16113 */ 'B', 'G', 'T', 'U', 'L', 0, |
| /* 16119 */ 'B', 'L', 'T', 'U', 'L', 0, |
| /* 16125 */ 'L', 'W', 'L', 0, |
| /* 16129 */ 'S', 'W', 'L', 0, |
| /* 16133 */ 'B', 'G', 'E', 'Z', 'L', 0, |
| /* 16139 */ 'B', 'L', 'E', 'Z', 'L', 0, |
| /* 16145 */ 'B', 'G', 'T', 'Z', 'L', 0, |
| /* 16151 */ 'B', 'L', 'T', 'Z', 'L', 0, |
| /* 16157 */ 'P', 's', 'e', 'u', 'd', 'o', 'C', 'V', 'T', '_', 'D', '6', '4', '_', 'L', 0, |
| /* 16173 */ 'P', 's', 'e', 'u', 'd', 'o', 'C', 'V', 'T', '_', 'S', '_', 'L', 0, |
| /* 16187 */ 'G', '_', 'F', 'R', 'E', 'M', 0, |
| /* 16194 */ 'G', '_', 'S', 'T', 'R', 'I', 'C', 'T', '_', 'F', 'R', 'E', 'M', 0, |
| /* 16208 */ 'G', '_', 'S', 'R', 'E', 'M', 0, |
| /* 16215 */ 'G', '_', 'U', 'R', 'E', 'M', 0, |
| /* 16222 */ 'G', '_', 'S', 'D', 'I', 'V', 'R', 'E', 'M', 0, |
| /* 16232 */ 'G', '_', 'U', 'D', 'I', 'V', 'R', 'E', 'M', 0, |
| /* 16242 */ 'M', 'F', 'G', 'C', '0', '_', 'M', 'M', 0, |
| /* 16251 */ 'M', 'F', 'H', 'G', 'C', '0', '_', 'M', 'M', 0, |
| /* 16261 */ 'M', 'T', 'H', 'G', 'C', '0', '_', 'M', 'M', 0, |
| /* 16271 */ 'M', 'T', 'G', 'C', '0', '_', 'M', 'M', 0, |
| /* 16280 */ 'C', 'F', 'C', '1', '_', 'M', 'M', 0, |
| /* 16288 */ 'M', 'F', 'C', '1', '_', 'M', 'M', 0, |
| /* 16296 */ 'C', 'T', 'C', '1', '_', 'M', 'M', 0, |
| /* 16304 */ 'M', 'T', 'C', '1', '_', 'M', 'M', 0, |
| /* 16312 */ 'L', 'W', 'C', '1', '_', 'M', 'M', 0, |
| /* 16320 */ 'S', 'W', 'C', '1', '_', 'M', 'M', 0, |
| /* 16328 */ 'L', 'U', 'X', 'C', '1', '_', 'M', 'M', 0, |
| /* 16337 */ 'S', 'U', 'X', 'C', '1', '_', 'M', 'M', 0, |
| /* 16346 */ 'L', 'W', 'X', 'C', '1', '_', 'M', 'M', 0, |
| /* 16355 */ 'S', 'W', 'X', 'C', '1', '_', 'M', 'M', 0, |
| /* 16364 */ 'M', 'F', 'H', 'C', '1', '_', 'D', '3', '2', '_', 'M', 'M', 0, |
| /* 16377 */ 'M', 'T', 'H', 'C', '1', '_', 'D', '3', '2', '_', 'M', 'M', 0, |
| /* 16390 */ 'F', 'S', 'U', 'B', '_', 'D', '3', '2', '_', 'M', 'M', 0, |
| /* 16402 */ 'N', 'M', 'S', 'U', 'B', '_', 'D', '3', '2', '_', 'M', 'M', 0, |
| /* 16415 */ 'F', 'A', 'D', 'D', '_', 'D', '3', '2', '_', 'M', 'M', 0, |
| /* 16427 */ 'N', 'M', 'A', 'D', 'D', '_', 'D', '3', '2', '_', 'M', 'M', 0, |
| /* 16440 */ 'C', '_', 'N', 'G', 'E', '_', 'D', '3', '2', '_', 'M', 'M', 0, |
| /* 16453 */ 'C', '_', 'N', 'G', 'L', 'E', '_', 'D', '3', '2', '_', 'M', 'M', 0, |
| /* 16467 */ 'C', '_', 'O', 'L', 'E', '_', 'D', '3', '2', '_', 'M', 'M', 0, |
| /* 16480 */ 'C', '_', 'U', 'L', 'E', '_', 'D', '3', '2', '_', 'M', 'M', 0, |
| /* 16493 */ 'C', '_', 'L', 'E', '_', 'D', '3', '2', '_', 'M', 'M', 0, |
| /* 16505 */ 'C', '_', 'S', 'F', '_', 'D', '3', '2', '_', 'M', 'M', 0, |
| /* 16517 */ 'M', 'O', 'V', 'F', '_', 'D', '3', '2', '_', 'M', 'M', 0, |
| /* 16529 */ 'C', '_', 'F', '_', 'D', '3', '2', '_', 'M', 'M', 0, |
| /* 16540 */ 'F', 'N', 'E', 'G', '_', 'D', '3', '2', '_', 'M', 'M', 0, |
| /* 16552 */ 'M', 'O', 'V', 'N', '_', 'I', '_', 'D', '3', '2', '_', 'M', 'M', 0, |
| /* 16566 */ 'M', 'O', 'V', 'Z', '_', 'I', '_', 'D', '3', '2', '_', 'M', 'M', 0, |
| /* 16580 */ 'C', '_', 'N', 'G', 'L', '_', 'D', '3', '2', '_', 'M', 'M', 0, |
| /* 16593 */ 'F', 'M', 'U', 'L', '_', 'D', '3', '2', '_', 'M', 'M', 0, |
| /* 16605 */ 'C', '_', 'U', 'N', '_', 'D', '3', '2', '_', 'M', 'M', 0, |
| /* 16617 */ 'R', 'E', 'C', 'I', 'P', '_', 'D', '3', '2', '_', 'M', 'M', 0, |
| /* 16630 */ 'F', 'C', 'M', 'P', '_', 'D', '3', '2', '_', 'M', 'M', 0, |
| /* 16642 */ 'C', '_', 'S', 'E', 'Q', '_', 'D', '3', '2', '_', 'M', 'M', 0, |
| /* 16655 */ 'C', '_', 'U', 'E', 'Q', '_', 'D', '3', '2', '_', 'M', 'M', 0, |
| /* 16668 */ 'C', '_', 'E', 'Q', '_', 'D', '3', '2', '_', 'M', 'M', 0, |
| /* 16680 */ 'F', 'A', 'B', 'S', '_', 'D', '3', '2', '_', 'M', 'M', 0, |
| /* 16692 */ 'C', 'V', 'T', '_', 'S', '_', 'D', '3', '2', '_', 'M', 'M', 0, |
| /* 16705 */ 'C', '_', 'N', 'G', 'T', '_', 'D', '3', '2', '_', 'M', 'M', 0, |
| /* 16718 */ 'C', '_', 'O', 'L', 'T', '_', 'D', '3', '2', '_', 'M', 'M', 0, |
| /* 16731 */ 'C', '_', 'U', 'L', 'T', '_', 'D', '3', '2', '_', 'M', 'M', 0, |
| /* 16744 */ 'C', '_', 'L', 'T', '_', 'D', '3', '2', '_', 'M', 'M', 0, |
| /* 16756 */ 'F', 'S', 'Q', 'R', 'T', '_', 'D', '3', '2', '_', 'M', 'M', 0, |
| /* 16769 */ 'R', 'S', 'Q', 'R', 'T', '_', 'D', '3', '2', '_', 'M', 'M', 0, |
| /* 16782 */ 'M', 'O', 'V', 'T', '_', 'D', '3', '2', '_', 'M', 'M', 0, |
| /* 16794 */ 'F', 'D', 'I', 'V', '_', 'D', '3', '2', '_', 'M', 'M', 0, |
| /* 16806 */ 'F', 'M', 'O', 'V', '_', 'D', '3', '2', '_', 'M', 'M', 0, |
| /* 16818 */ 'C', 'V', 'T', '_', 'W', '_', 'D', '3', '2', '_', 'M', 'M', 0, |
| /* 16831 */ 'B', 'P', 'O', 'S', 'G', 'E', '3', '2', '_', 'M', 'M', 0, |
| /* 16843 */ 'L', 'W', 'M', '3', '2', '_', 'M', 'M', 0, |
| /* 16852 */ 'S', 'W', 'M', '3', '2', '_', 'M', 'M', 0, |
| /* 16861 */ 'F', 'C', 'M', 'P', '_', 'S', '3', '2', '_', 'M', 'M', 0, |
| /* 16873 */ 'C', 'F', 'C', '2', '_', 'M', 'M', 0, |
| /* 16881 */ 'C', 'T', 'C', '2', '_', 'M', 'M', 0, |
| /* 16889 */ 'A', 'D', 'D', 'I', 'U', 'R', '2', '_', 'M', 'M', 0, |
| /* 16900 */ 'M', 'F', 'H', 'C', '1', '_', 'D', '6', '4', '_', 'M', 'M', 0, |
| /* 16913 */ 'M', 'T', 'H', 'C', '1', '_', 'D', '6', '4', '_', 'M', 'M', 0, |
| /* 16926 */ 'M', 'T', 'C', '1', '_', 'D', '6', '4', '_', 'M', 'M', 0, |
| /* 16938 */ 'F', 'S', 'U', 'B', '_', 'D', '6', '4', '_', 'M', 'M', 0, |
| /* 16950 */ 'F', 'A', 'D', 'D', '_', 'D', '6', '4', '_', 'M', 'M', 0, |
| /* 16962 */ 'C', '_', 'N', 'G', 'E', '_', 'D', '6', '4', '_', 'M', 'M', 0, |
| /* 16975 */ 'C', '_', 'N', 'G', 'L', 'E', '_', 'D', '6', '4', '_', 'M', 'M', 0, |
| /* 16989 */ 'C', '_', 'O', 'L', 'E', '_', 'D', '6', '4', '_', 'M', 'M', 0, |
| /* 17002 */ 'C', '_', 'U', 'L', 'E', '_', 'D', '6', '4', '_', 'M', 'M', 0, |
| /* 17015 */ 'C', '_', 'L', 'E', '_', 'D', '6', '4', '_', 'M', 'M', 0, |
| /* 17027 */ 'C', '_', 'S', 'F', '_', 'D', '6', '4', '_', 'M', 'M', 0, |
| /* 17039 */ 'C', '_', 'F', '_', 'D', '6', '4', '_', 'M', 'M', 0, |
| /* 17050 */ 'F', 'N', 'E', 'G', '_', 'D', '6', '4', '_', 'M', 'M', 0, |
| /* 17062 */ 'C', '_', 'N', 'G', 'L', '_', 'D', '6', '4', '_', 'M', 'M', 0, |
| /* 17075 */ 'F', 'M', 'U', 'L', '_', 'D', '6', '4', '_', 'M', 'M', 0, |
| /* 17087 */ 'C', 'V', 'T', '_', 'L', '_', 'D', '6', '4', '_', 'M', 'M', 0, |
| /* 17100 */ 'C', '_', 'U', 'N', '_', 'D', '6', '4', '_', 'M', 'M', 0, |
| /* 17112 */ 'R', 'E', 'C', 'I', 'P', '_', 'D', '6', '4', '_', 'M', 'M', 0, |
| /* 17125 */ 'C', '_', 'S', 'E', 'Q', '_', 'D', '6', '4', '_', 'M', 'M', 0, |
| /* 17138 */ 'C', '_', 'U', 'E', 'Q', '_', 'D', '6', '4', '_', 'M', 'M', 0, |
| /* 17151 */ 'C', '_', 'E', 'Q', '_', 'D', '6', '4', '_', 'M', 'M', 0, |
| /* 17163 */ 'F', 'A', 'B', 'S', '_', 'D', '6', '4', '_', 'M', 'M', 0, |
| /* 17175 */ 'C', 'V', 'T', '_', 'S', '_', 'D', '6', '4', '_', 'M', 'M', 0, |
| /* 17188 */ 'C', '_', 'N', 'G', 'T', '_', 'D', '6', '4', '_', 'M', 'M', 0, |
| /* 17201 */ 'C', '_', 'O', 'L', 'T', '_', 'D', '6', '4', '_', 'M', 'M', 0, |
| /* 17214 */ 'C', '_', 'U', 'L', 'T', '_', 'D', '6', '4', '_', 'M', 'M', 0, |
| /* 17227 */ 'C', '_', 'L', 'T', '_', 'D', '6', '4', '_', 'M', 'M', 0, |
| /* 17239 */ 'F', 'S', 'Q', 'R', 'T', '_', 'D', '6', '4', '_', 'M', 'M', 0, |
| /* 17252 */ 'R', 'S', 'Q', 'R', 'T', '_', 'D', '6', '4', '_', 'M', 'M', 0, |
| /* 17265 */ 'F', 'D', 'I', 'V', '_', 'D', '6', '4', '_', 'M', 'M', 0, |
| /* 17277 */ 'F', 'M', 'O', 'V', '_', 'D', '6', '4', '_', 'M', 'M', 0, |
| /* 17289 */ 'C', 'V', 'T', '_', 'W', '_', 'D', '6', '4', '_', 'M', 'M', 0, |
| /* 17302 */ 'A', 'D', 'D', 'I', 'U', 'S', '5', '_', 'M', 'M', 0, |
| /* 17313 */ 'S', 'B', '1', '6', '_', 'M', 'M', 0, |
| /* 17321 */ 'J', 'R', 'C', '1', '6', '_', 'M', 'M', 0, |
| /* 17330 */ 'A', 'N', 'D', '1', '6', '_', 'M', 'M', 0, |
| /* 17339 */ 'M', 'O', 'V', 'E', '1', '6', '_', 'M', 'M', 0, |
| /* 17349 */ 'S', 'H', '1', '6', '_', 'M', 'M', 0, |
| /* 17357 */ 'A', 'N', 'D', 'I', '1', '6', '_', 'M', 'M', 0, |
| /* 17367 */ 'M', 'F', 'H', 'I', '1', '6', '_', 'M', 'M', 0, |
| /* 17377 */ 'L', 'I', '1', '6', '_', 'M', 'M', 0, |
| /* 17385 */ 'B', 'R', 'E', 'A', 'K', '1', '6', '_', 'M', 'M', 0, |
| /* 17396 */ 'S', 'L', 'L', '1', '6', '_', 'M', 'M', 0, |
| /* 17405 */ 'S', 'R', 'L', '1', '6', '_', 'M', 'M', 0, |
| /* 17414 */ 'L', 'W', 'M', '1', '6', '_', 'M', 'M', 0, |
| /* 17423 */ 'S', 'W', 'M', '1', '6', '_', 'M', 'M', 0, |
| /* 17432 */ 'M', 'F', 'L', 'O', '1', '6', '_', 'M', 'M', 0, |
| /* 17442 */ 'S', 'D', 'B', 'B', 'P', '1', '6', '_', 'M', 'M', 0, |
| /* 17453 */ 'J', 'R', '1', '6', '_', 'M', 'M', 0, |
| /* 17461 */ 'J', 'A', 'L', 'R', '1', '6', '_', 'M', 'M', 0, |
| /* 17471 */ 'X', 'O', 'R', '1', '6', '_', 'M', 'M', 0, |
| /* 17480 */ 'J', 'A', 'L', 'R', 'S', '1', '6', '_', 'M', 'M', 0, |
| /* 17491 */ 'N', 'O', 'T', '1', '6', '_', 'M', 'M', 0, |
| /* 17500 */ 'L', 'B', 'U', '1', '6', '_', 'M', 'M', 0, |
| /* 17509 */ 'S', 'U', 'B', 'U', '1', '6', '_', 'M', 'M', 0, |
| /* 17519 */ 'A', 'D', 'D', 'U', '1', '6', '_', 'M', 'M', 0, |
| /* 17529 */ 'L', 'H', 'U', '1', '6', '_', 'M', 'M', 0, |
| /* 17538 */ 'L', 'W', '1', '6', '_', 'M', 'M', 0, |
| /* 17546 */ 'S', 'W', '1', '6', '_', 'M', 'M', 0, |
| /* 17554 */ 'B', 'N', 'E', 'Z', '1', '6', '_', 'M', 'M', 0, |
| /* 17564 */ 'B', 'E', 'Q', 'Z', '1', '6', '_', 'M', 'M', 0, |
| /* 17574 */ 'P', 'R', 'E', 'C', 'E', 'U', '_', 'P', 'H', '_', 'Q', 'B', 'L', 'A', '_', 'M', 'M', 0, |
| /* 17592 */ 'P', 'R', 'E', 'C', 'E', 'Q', 'U', '_', 'P', 'H', '_', 'Q', 'B', 'L', 'A', '_', 'M', 'M', 0, |
| /* 17611 */ 'P', 'R', 'E', 'C', 'E', 'U', '_', 'P', 'H', '_', 'Q', 'B', 'R', 'A', '_', 'M', 'M', 0, |
| /* 17629 */ 'P', 'R', 'E', 'C', 'E', 'Q', 'U', '_', 'P', 'H', '_', 'Q', 'B', 'R', 'A', '_', 'M', 'M', 0, |
| /* 17648 */ 'S', 'R', 'A', '_', 'M', 'M', 0, |
| /* 17655 */ 'S', 'E', 'B', '_', 'M', 'M', 0, |
| /* 17662 */ 'E', 'H', 'B', '_', 'M', 'M', 0, |
| /* 17669 */ 'L', 'B', '_', 'M', 'M', 0, |
| /* 17675 */ 'C', 'M', 'P', 'G', 'U', '_', 'L', 'E', '_', 'Q', 'B', '_', 'M', 'M', 0, |
| /* 17690 */ 'C', 'M', 'P', 'U', '_', 'L', 'E', '_', 'Q', 'B', '_', 'M', 'M', 0, |
| /* 17704 */ 'P', 'I', 'C', 'K', '_', 'Q', 'B', '_', 'M', 'M', 0, |
| /* 17715 */ 'S', 'H', 'L', 'L', '_', 'Q', 'B', '_', 'M', 'M', 0, |
| /* 17726 */ 'R', 'E', 'P', 'L', '_', 'Q', 'B', '_', 'M', 'M', 0, |
| /* 17737 */ 'S', 'H', 'R', 'L', '_', 'Q', 'B', '_', 'M', 'M', 0, |
| /* 17748 */ 'C', 'M', 'P', 'G', 'U', '_', 'E', 'Q', '_', 'Q', 'B', '_', 'M', 'M', 0, |
| /* 17763 */ 'C', 'M', 'P', 'U', '_', 'E', 'Q', '_', 'Q', 'B', '_', 'M', 'M', 0, |
| /* 17777 */ 'S', 'U', 'B', 'U', '_', 'S', '_', 'Q', 'B', '_', 'M', 'M', 0, |
| /* 17790 */ 'A', 'D', 'D', 'U', '_', 'S', '_', 'Q', 'B', '_', 'M', 'M', 0, |
| /* 17803 */ 'C', 'M', 'P', 'G', 'U', '_', 'L', 'T', '_', 'Q', 'B', '_', 'M', 'M', 0, |
| /* 17818 */ 'C', 'M', 'P', 'U', '_', 'L', 'T', '_', 'Q', 'B', '_', 'M', 'M', 0, |
| /* 17832 */ 'S', 'U', 'B', 'U', '_', 'Q', 'B', '_', 'M', 'M', 0, |
| /* 17843 */ 'A', 'D', 'D', 'U', '_', 'Q', 'B', '_', 'M', 'M', 0, |
| /* 17854 */ 'S', 'H', 'L', 'L', 'V', '_', 'Q', 'B', '_', 'M', 'M', 0, |
| /* 17866 */ 'R', 'E', 'P', 'L', 'V', '_', 'Q', 'B', '_', 'M', 'M', 0, |
| /* 17878 */ 'S', 'H', 'R', 'L', 'V', '_', 'Q', 'B', '_', 'M', 'M', 0, |
| /* 17890 */ 'R', 'A', 'D', 'D', 'U', '_', 'W', '_', 'Q', 'B', '_', 'M', 'M', 0, |
| /* 17904 */ 'S', 'B', '_', 'M', 'M', 0, |
| /* 17910 */ 'M', 'O', 'D', 'S', 'U', 'B', '_', 'M', 'M', 0, |
| /* 17920 */ 'P', 's', 'e', 'u', 'd', 'o', 'M', 'S', 'U', 'B', '_', 'M', 'M', 0, |
| /* 17934 */ 'S', 'Y', 'N', 'C', '_', 'M', 'M', 0, |
| /* 17942 */ 'A', 'D', 'D', 'I', 'U', 'P', 'C', '_', 'M', 'M', 0, |
| /* 17953 */ 'A', 'D', 'D', 'S', 'C', '_', 'M', 'M', 0, |
| /* 17962 */ 'A', 'D', 'D', 'W', 'C', '_', 'M', 'M', 0, |
| /* 17971 */ 'B', 'N', 'E', 'Z', 'C', '_', 'M', 'M', 0, |
| /* 17980 */ 'B', 'E', 'Q', 'Z', 'C', '_', 'M', 'M', 0, |
| /* 17989 */ 'P', 's', 'e', 'u', 'd', 'o', 'M', 'A', 'D', 'D', '_', 'M', 'M', 0, |
| /* 18003 */ 'A', 'N', 'D', '_', 'M', 'M', 0, |
| /* 18010 */ 'L', 'B', 'E', '_', 'M', 'M', 0, |
| /* 18017 */ 'S', 'B', 'E', '_', 'M', 'M', 0, |
| /* 18024 */ 'S', 'C', 'E', '_', 'M', 'M', 0, |
| /* 18031 */ 'C', 'A', 'C', 'H', 'E', 'E', '_', 'M', 'M', 0, |
| /* 18041 */ 'P', 'R', 'E', 'F', 'E', '_', 'M', 'M', 0, |
| /* 18050 */ 'T', 'G', 'E', '_', 'M', 'M', 0, |
| /* 18057 */ 'C', 'A', 'C', 'H', 'E', '_', 'M', 'M', 0, |
| /* 18066 */ 'L', 'H', 'E', '_', 'M', 'M', 0, |
| /* 18073 */ 'S', 'H', 'E', '_', 'M', 'M', 0, |
| /* 18080 */ 'L', 'L', 'E', '_', 'M', 'M', 0, |
| /* 18087 */ 'L', 'W', 'L', 'E', '_', 'M', 'M', 0, |
| /* 18095 */ 'S', 'W', 'L', 'E', '_', 'M', 'M', 0, |
| /* 18103 */ 'B', 'N', 'E', '_', 'M', 'M', 0, |
| /* 18110 */ 'T', 'N', 'E', '_', 'M', 'M', 0, |
| /* 18117 */ 'L', 'W', 'R', 'E', '_', 'M', 'M', 0, |
| /* 18125 */ 'S', 'W', 'R', 'E', '_', 'M', 'M', 0, |
| /* 18133 */ 'P', 'A', 'U', 'S', 'E', '_', 'M', 'M', 0, |
| /* 18142 */ 'L', 'W', 'E', '_', 'M', 'M', 0, |
| /* 18149 */ 'S', 'W', 'E', '_', 'M', 'M', 0, |
| /* 18156 */ 'L', 'B', 'u', 'E', '_', 'M', 'M', 0, |
| /* 18164 */ 'L', 'H', 'u', 'E', '_', 'M', 'M', 0, |
| /* 18172 */ 'B', 'C', '1', 'F', '_', 'M', 'M', 0, |
| /* 18180 */ 'P', 'R', 'E', 'F', '_', 'M', 'M', 0, |
| /* 18188 */ 'T', 'L', 'B', 'G', 'I', 'N', 'V', 'F', '_', 'M', 'M', 0, |
| /* 18200 */ 'T', 'A', 'I', 'L', 'C', 'A', 'L', 'L', 'R', 'E', 'G', '_', 'M', 'M', 0, |
| /* 18215 */ 'W', 'S', 'B', 'H', '_', 'M', 'M', 0, |
| /* 18223 */ 'S', 'E', 'H', '_', 'M', 'M', 0, |
| /* 18230 */ 'L', 'H', '_', 'M', 'M', 0, |
| /* 18236 */ 'S', 'H', 'R', 'A', '_', 'P', 'H', '_', 'M', 'M', 0, |
| /* 18247 */ 'P', 'R', 'E', 'C', 'R', 'Q', '_', 'Q', 'B', '_', 'P', 'H', '_', 'M', 'M', 0, |
| /* 18263 */ 'P', 'R', 'E', 'C', 'R', 'Q', 'U', '_', 'S', '_', 'Q', 'B', '_', 'P', 'H', '_', 'M', 'M', 0, |
| /* 18282 */ 'C', 'M', 'P', '_', 'L', 'E', '_', 'P', 'H', '_', 'M', 'M', 0, |
| /* 18295 */ 'P', 'I', 'C', 'K', '_', 'P', 'H', '_', 'M', 'M', 0, |
| /* 18306 */ 'S', 'H', 'L', 'L', '_', 'P', 'H', '_', 'M', 'M', 0, |
| /* 18317 */ 'R', 'E', 'P', 'L', '_', 'P', 'H', '_', 'M', 'M', 0, |
| /* 18328 */ 'P', 'A', 'C', 'K', 'R', 'L', '_', 'P', 'H', '_', 'M', 'M', 0, |
| /* 18341 */ 'S', 'U', 'B', 'Q', '_', 'P', 'H', '_', 'M', 'M', 0, |
| /* 18352 */ 'A', 'D', 'D', 'Q', '_', 'P', 'H', '_', 'M', 'M', 0, |
| /* 18363 */ 'C', 'M', 'P', '_', 'E', 'Q', '_', 'P', 'H', '_', 'M', 'M', 0, |
| /* 18376 */ 'S', 'H', 'R', 'A', '_', 'R', '_', 'P', 'H', '_', 'M', 'M', 0, |
| /* 18389 */ 'S', 'H', 'R', 'A', 'V', '_', 'R', '_', 'P', 'H', '_', 'M', 'M', 0, |
| /* 18403 */ 'M', 'U', 'L', 'Q', '_', 'R', 'S', '_', 'P', 'H', '_', 'M', 'M', 0, |
| /* 18417 */ 'S', 'H', 'L', 'L', '_', 'S', '_', 'P', 'H', '_', 'M', 'M', 0, |
| /* 18430 */ 'S', 'U', 'B', 'Q', '_', 'S', '_', 'P', 'H', '_', 'M', 'M', 0, |
| /* 18443 */ 'A', 'D', 'D', 'Q', '_', 'S', '_', 'P', 'H', '_', 'M', 'M', 0, |
| /* 18456 */ 'A', 'B', 'S', 'Q', '_', 'S', '_', 'P', 'H', '_', 'M', 'M', 0, |
| /* 18469 */ 'S', 'H', 'L', 'L', 'V', '_', 'S', '_', 'P', 'H', '_', 'M', 'M', 0, |
| /* 18483 */ 'C', 'M', 'P', '_', 'L', 'T', '_', 'P', 'H', '_', 'M', 'M', 0, |
| /* 18496 */ 'S', 'H', 'R', 'A', 'V', '_', 'P', 'H', '_', 'M', 'M', 0, |
| /* 18508 */ 'S', 'H', 'L', 'L', 'V', '_', 'P', 'H', '_', 'M', 'M', 0, |
| /* 18520 */ 'R', 'E', 'P', 'L', 'V', '_', 'P', 'H', '_', 'M', 'M', 0, |
| /* 18532 */ 'D', 'P', 'A', 'Q', '_', 'S', '_', 'W', '_', 'P', 'H', '_', 'M', 'M', 0, |
| /* 18547 */ 'M', 'U', 'L', 'S', 'A', 'Q', '_', 'S', '_', 'W', '_', 'P', 'H', '_', 'M', 'M', 0, |
| /* 18564 */ 'D', 'P', 'S', 'Q', '_', 'S', '_', 'W', '_', 'P', 'H', '_', 'M', 'M', 0, |
| /* 18579 */ 'S', 'H', '_', 'M', 'M', 0, |
| /* 18585 */ 'E', 'X', 'T', 'R', '_', 'S', '_', 'H', '_', 'M', 'M', 0, |
| /* 18597 */ 'E', 'X', 'T', 'R', 'V', '_', 'S', '_', 'H', '_', 'M', 'M', 0, |
| /* 18610 */ 'S', 'Y', 'N', 'C', 'I', '_', 'M', 'M', 0, |
| /* 18619 */ 'D', 'I', '_', 'M', 'M', 0, |
| /* 18625 */ 'T', 'G', 'E', 'I', '_', 'M', 'M', 0, |
| /* 18633 */ 'T', 'N', 'E', 'I', '_', 'M', 'M', 0, |
| /* 18641 */ 'P', 's', 'e', 'u', 'd', 'o', 'M', 'F', 'H', 'I', '_', 'M', 'M', 0, |
| /* 18655 */ 'P', 's', 'e', 'u', 'd', 'o', 'M', 'T', 'L', 'O', 'H', 'I', '_', 'M', 'M', 0, |
| /* 18671 */ 'M', 'T', 'H', 'I', '_', 'M', 'M', 0, |
| /* 18679 */ 'T', 'E', 'Q', 'I', '_', 'M', 'M', 0, |
| /* 18687 */ 'T', 'L', 'T', 'I', '_', 'M', 'M', 0, |
| /* 18695 */ 'T', 'L', 'B', 'W', 'I', '_', 'M', 'M', 0, |
| /* 18704 */ 'T', 'L', 'B', 'G', 'W', 'I', '_', 'M', 'M', 0, |
| /* 18714 */ 'M', 'O', 'V', 'F', '_', 'I', '_', 'M', 'M', 0, |
| /* 18724 */ 'M', 'O', 'V', 'N', '_', 'I', '_', 'M', 'M', 0, |
| /* 18734 */ 'M', 'O', 'V', 'T', '_', 'I', '_', 'M', 'M', 0, |
| /* 18744 */ 'M', 'O', 'V', 'Z', '_', 'I', '_', 'M', 'M', 0, |
| /* 18754 */ 'J', '_', 'M', 'M', 0, |
| /* 18759 */ 'B', 'R', 'E', 'A', 'K', '_', 'M', 'M', 0, |
| /* 18768 */ 'J', 'A', 'L', '_', 'M', 'M', 0, |
| /* 18775 */ 'B', 'G', 'E', 'Z', 'A', 'L', '_', 'M', 'M', 0, |
| /* 18785 */ 'B', 'L', 'T', 'Z', 'A', 'L', '_', 'M', 'M', 0, |
| /* 18795 */ 'M', 'U', 'L', 'E', 'U', '_', 'S', '_', 'P', 'H', '_', 'Q', 'B', 'L', '_', 'M', 'M', 0, |
| /* 18813 */ 'P', 'R', 'E', 'C', 'E', 'U', '_', 'P', 'H', '_', 'Q', 'B', 'L', '_', 'M', 'M', 0, |
| /* 18830 */ 'P', 'R', 'E', 'C', 'E', 'Q', 'U', '_', 'P', 'H', '_', 'Q', 'B', 'L', '_', 'M', 'M', 0, |
| /* 18848 */ 'D', 'P', 'A', 'U', '_', 'H', '_', 'Q', 'B', 'L', '_', 'M', 'M', 0, |
| /* 18862 */ 'D', 'P', 'S', 'U', '_', 'H', '_', 'Q', 'B', 'L', '_', 'M', 'M', 0, |
| /* 18876 */ 'M', 'A', 'Q', '_', 'S', 'A', '_', 'W', '_', 'P', 'H', 'L', '_', 'M', 'M', 0, |
| /* 18892 */ 'P', 'R', 'E', 'C', 'E', 'Q', '_', 'W', '_', 'P', 'H', 'L', '_', 'M', 'M', 0, |
| /* 18908 */ 'M', 'A', 'Q', '_', 'S', '_', 'W', '_', 'P', 'H', 'L', '_', 'M', 'M', 0, |
| /* 18923 */ 'M', 'U', 'L', 'E', 'Q', '_', 'S', '_', 'W', '_', 'P', 'H', 'L', '_', 'M', 'M', 0, |
| /* 18940 */ 'T', 'A', 'I', 'L', 'C', 'A', 'L', 'L', '_', 'M', 'M', 0, |
| /* 18952 */ 'H', 'Y', 'P', 'C', 'A', 'L', 'L', '_', 'M', 'M', 0, |
| /* 18963 */ 'S', 'Y', 'S', 'C', 'A', 'L', 'L', '_', 'M', 'M', 0, |
| /* 18974 */ 'S', 'L', 'L', '_', 'M', 'M', 0, |
| /* 18981 */ 'S', 'R', 'L', '_', 'M', 'M', 0, |
| /* 18988 */ 'M', 'U', 'L', '_', 'M', 'M', 0, |
| /* 18995 */ 'L', 'W', 'L', '_', 'M', 'M', 0, |
| /* 19002 */ 'S', 'W', 'L', '_', 'M', 'M', 0, |
| /* 19009 */ 'L', 'W', 'M', '_', 'M', 'M', 0, |
| /* 19016 */ 'S', 'W', 'M', '_', 'M', 'M', 0, |
| /* 19023 */ 'C', 'L', 'O', '_', 'M', 'M', 0, |
| /* 19030 */ 'P', 's', 'e', 'u', 'd', 'o', 'M', 'F', 'L', 'O', '_', 'M', 'M', 0, |
| /* 19044 */ 'S', 'H', 'I', 'L', 'O', '_', 'M', 'M', 0, |
| /* 19053 */ 'M', 'T', 'L', 'O', '_', 'M', 'M', 0, |
| /* 19061 */ 'T', 'R', 'A', 'P', '_', 'M', 'M', 0, |
| /* 19069 */ 'S', 'D', 'B', 'B', 'P', '_', 'M', 'M', 0, |
| /* 19078 */ 'T', 'L', 'B', 'P', '_', 'M', 'M', 0, |
| /* 19086 */ 'E', 'X', 'T', 'P', 'D', 'P', '_', 'M', 'M', 0, |
| /* 19096 */ 'M', 'O', 'V', 'E', 'P', '_', 'M', 'M', 0, |
| /* 19105 */ 'T', 'L', 'B', 'G', 'P', '_', 'M', 'M', 0, |
| /* 19114 */ 'L', 'W', 'G', 'P', '_', 'M', 'M', 0, |
| /* 19122 */ 'M', 'T', 'H', 'L', 'I', 'P', '_', 'M', 'M', 0, |
| /* 19132 */ 'S', 'S', 'N', 'O', 'P', '_', 'M', 'M', 0, |
| /* 19141 */ 'A', 'D', 'D', 'I', 'U', 'R', '1', 'S', 'P', '_', 'M', 'M', 0, |
| /* 19154 */ 'R', 'D', 'D', 'S', 'P', '_', 'M', 'M', 0, |
| /* 19163 */ 'W', 'R', 'D', 'S', 'P', '_', 'M', 'M', 0, |
| /* 19172 */ 'L', 'W', 'D', 'S', 'P', '_', 'M', 'M', 0, |
| /* 19181 */ 'S', 'W', 'D', 'S', 'P', '_', 'M', 'M', 0, |
| /* 19190 */ 'M', 'S', 'U', 'B', '_', 'D', 'S', 'P', '_', 'M', 'M', 0, |
| /* 19202 */ 'M', 'A', 'D', 'D', '_', 'D', 'S', 'P', '_', 'M', 'M', 0, |
| /* 19214 */ 'M', 'F', 'H', 'I', '_', 'D', 'S', 'P', '_', 'M', 'M', 0, |
| /* 19226 */ 'M', 'T', 'H', 'I', '_', 'D', 'S', 'P', '_', 'M', 'M', 0, |
| /* 19238 */ 'M', 'F', 'L', 'O', '_', 'D', 'S', 'P', '_', 'M', 'M', 0, |
| /* 19250 */ 'M', 'T', 'L', 'O', '_', 'D', 'S', 'P', '_', 'M', 'M', 0, |
| /* 19262 */ 'M', 'U', 'L', 'T', '_', 'D', 'S', 'P', '_', 'M', 'M', 0, |
| /* 19274 */ 'M', 'S', 'U', 'B', 'U', '_', 'D', 'S', 'P', '_', 'M', 'M', 0, |
| /* 19287 */ 'M', 'A', 'D', 'D', 'U', '_', 'D', 'S', 'P', '_', 'M', 'M', 0, |
| /* 19300 */ 'M', 'U', 'L', 'T', 'U', '_', 'D', 'S', 'P', '_', 'M', 'M', 0, |
| /* 19313 */ 'A', 'D', 'D', 'I', 'U', 'S', 'P', '_', 'M', 'M', 0, |
| /* 19324 */ 'L', 'W', 'S', 'P', '_', 'M', 'M', 0, |
| /* 19332 */ 'S', 'W', 'S', 'P', '_', 'M', 'M', 0, |
| /* 19340 */ 'E', 'X', 'T', 'P', '_', 'M', 'M', 0, |
| /* 19348 */ 'L', 'W', 'P', '_', 'M', 'M', 0, |
| /* 19355 */ 'S', 'W', 'P', '_', 'M', 'M', 0, |
| /* 19362 */ 'B', 'E', 'Q', '_', 'M', 'M', 0, |
| /* 19369 */ 'T', 'E', 'Q', '_', 'M', 'M', 0, |
| /* 19376 */ 'T', 'L', 'B', 'R', '_', 'M', 'M', 0, |
| /* 19384 */ 'M', 'U', 'L', 'E', 'U', '_', 'S', '_', 'P', 'H', '_', 'Q', 'B', 'R', '_', 'M', 'M', 0, |
| /* 19402 */ 'P', 'R', 'E', 'C', 'E', 'U', '_', 'P', 'H', '_', 'Q', 'B', 'R', '_', 'M', 'M', 0, |
| /* 19419 */ 'P', 'R', 'E', 'C', 'E', 'Q', 'U', '_', 'P', 'H', '_', 'Q', 'B', 'R', '_', 'M', 'M', 0, |
| /* 19437 */ 'D', 'P', 'A', 'U', '_', 'H', '_', 'Q', 'B', 'R', '_', 'M', 'M', 0, |
| /* 19451 */ 'D', 'P', 'S', 'U', '_', 'H', '_', 'Q', 'B', 'R', '_', 'M', 'M', 0, |
| /* 19465 */ 'B', 'A', 'L', '_', 'B', 'R', '_', 'M', 'M', 0, |
| /* 19475 */ 'T', 'L', 'B', 'G', 'R', '_', 'M', 'M', 0, |
| /* 19484 */ 'M', 'A', 'Q', '_', 'S', 'A', '_', 'W', '_', 'P', 'H', 'R', '_', 'M', 'M', 0, |
| /* 19500 */ 'P', 'R', 'E', 'C', 'E', 'Q', '_', 'W', '_', 'P', 'H', 'R', '_', 'M', 'M', 0, |
| /* 19516 */ 'M', 'A', 'Q', '_', 'S', '_', 'W', '_', 'P', 'H', 'R', '_', 'M', 'M', 0, |
| /* 19531 */ 'M', 'U', 'L', 'E', 'Q', '_', 'S', '_', 'W', '_', 'P', 'H', 'R', '_', 'M', 'M', 0, |
| /* 19548 */ 'J', 'R', '_', 'M', 'M', 0, |
| /* 19554 */ 'J', 'A', 'L', 'R', '_', 'M', 'M', 0, |
| /* 19562 */ 'N', 'O', 'R', '_', 'M', 'M', 0, |
| /* 19569 */ 'X', 'O', 'R', '_', 'M', 'M', 0, |
| /* 19576 */ 'R', 'O', 'T', 'R', '_', 'M', 'M', 0, |
| /* 19584 */ 'T', 'L', 'B', 'W', 'R', '_', 'M', 'M', 0, |
| /* 19593 */ 'T', 'L', 'B', 'G', 'W', 'R', '_', 'M', 'M', 0, |
| /* 19603 */ 'R', 'D', 'H', 'W', 'R', '_', 'M', 'M', 0, |
| /* 19612 */ 'L', 'W', 'R', '_', 'M', 'M', 0, |
| /* 19619 */ 'S', 'W', 'R', '_', 'M', 'M', 0, |
| /* 19626 */ 'J', 'A', 'L', 'S', '_', 'M', 'M', 0, |
| /* 19634 */ 'B', 'G', 'E', 'Z', 'A', 'L', 'S', '_', 'M', 'M', 0, |
| /* 19645 */ 'B', 'L', 'T', 'Z', 'A', 'L', 'S', '_', 'M', 'M', 0, |
| /* 19656 */ 'I', 'N', 'S', '_', 'M', 'M', 0, |
| /* 19663 */ 'J', 'A', 'L', 'R', 'S', '_', 'M', 'M', 0, |
| /* 19672 */ 'L', 'W', 'X', 'S', '_', 'M', 'M', 0, |
| /* 19680 */ 'C', 'V', 'T', '_', 'D', '3', '2', '_', 'S', '_', 'M', 'M', 0, |
| /* 19693 */ 'C', 'V', 'T', '_', 'D', '6', '4', '_', 'S', '_', 'M', 'M', 0, |
| /* 19706 */ 'F', 'S', 'U', 'B', '_', 'S', '_', 'M', 'M', 0, |
| /* 19716 */ 'N', 'M', 'S', 'U', 'B', '_', 'S', '_', 'M', 'M', 0, |
| /* 19727 */ 'F', 'A', 'D', 'D', '_', 'S', '_', 'M', 'M', 0, |
| /* 19737 */ 'N', 'M', 'A', 'D', 'D', '_', 'S', '_', 'M', 'M', 0, |
| /* 19748 */ 'C', '_', 'N', 'G', 'E', '_', 'S', '_', 'M', 'M', 0, |
| /* 19759 */ 'C', '_', 'N', 'G', 'L', 'E', '_', 'S', '_', 'M', 'M', 0, |
| /* 19771 */ 'C', '_', 'O', 'L', 'E', '_', 'S', '_', 'M', 'M', 0, |
| /* 19782 */ 'C', '_', 'U', 'L', 'E', '_', 'S', '_', 'M', 'M', 0, |
| /* 19793 */ 'C', '_', 'L', 'E', '_', 'S', '_', 'M', 'M', 0, |
| /* 19803 */ 'C', '_', 'S', 'F', '_', 'S', '_', 'M', 'M', 0, |
| /* 19813 */ 'M', 'O', 'V', 'F', '_', 'S', '_', 'M', 'M', 0, |
| /* 19823 */ 'C', '_', 'F', '_', 'S', '_', 'M', 'M', 0, |
| /* 19832 */ 'F', 'N', 'E', 'G', '_', 'S', '_', 'M', 'M', 0, |
| /* 19842 */ 'M', 'O', 'V', 'N', '_', 'I', '_', 'S', '_', 'M', 'M', 0, |
| /* 19854 */ 'M', 'O', 'V', 'Z', '_', 'I', '_', 'S', '_', 'M', 'M', 0, |
| /* 19866 */ 'C', '_', 'N', 'G', 'L', '_', 'S', '_', 'M', 'M', 0, |
| /* 19877 */ 'F', 'M', 'U', 'L', '_', 'S', '_', 'M', 'M', 0, |
| /* 19887 */ 'C', 'V', 'T', '_', 'L', '_', 'S', '_', 'M', 'M', 0, |
| /* 19898 */ 'C', '_', 'U', 'N', '_', 'S', '_', 'M', 'M', 0, |
| /* 19908 */ 'R', 'E', 'C', 'I', 'P', '_', 'S', '_', 'M', 'M', 0, |
| /* 19919 */ 'C', '_', 'S', 'E', 'Q', '_', 'S', '_', 'M', 'M', 0, |
| /* 19930 */ 'C', '_', 'U', 'E', 'Q', '_', 'S', '_', 'M', 'M', 0, |
| /* 19941 */ 'C', '_', 'E', 'Q', '_', 'S', '_', 'M', 'M', 0, |
| /* 19951 */ 'F', 'A', 'B', 'S', '_', 'S', '_', 'M', 'M', 0, |
| /* 19961 */ 'C', '_', 'N', 'G', 'T', '_', 'S', '_', 'M', 'M', 0, |
| /* 19972 */ 'C', '_', 'O', 'L', 'T', '_', 'S', '_', 'M', 'M', 0, |
| /* 19983 */ 'C', '_', 'U', 'L', 'T', '_', 'S', '_', 'M', 'M', 0, |
| /* 19994 */ 'C', '_', 'L', 'T', '_', 'S', '_', 'M', 'M', 0, |
| /* 20004 */ 'F', 'S', 'Q', 'R', 'T', '_', 'S', '_', 'M', 'M', 0, |
| /* 20015 */ 'R', 'S', 'Q', 'R', 'T', '_', 'S', '_', 'M', 'M', 0, |
| /* 20026 */ 'M', 'O', 'V', 'T', '_', 'S', '_', 'M', 'M', 0, |
| /* 20036 */ 'F', 'D', 'I', 'V', '_', 'S', '_', 'M', 'M', 0, |
| /* 20046 */ 'F', 'M', 'O', 'V', '_', 'S', '_', 'M', 'M', 0, |
| /* 20056 */ 'T', 'R', 'U', 'N', 'C', '_', 'W', '_', 'S', '_', 'M', 'M', 0, |
| /* 20069 */ 'R', 'O', 'U', 'N', 'D', '_', 'W', '_', 'S', '_', 'M', 'M', 0, |
| /* 20082 */ 'C', 'E', 'I', 'L', '_', 'W', '_', 'S', '_', 'M', 'M', 0, |
| /* 20094 */ 'F', 'L', 'O', 'O', 'R', '_', 'W', '_', 'S', '_', 'M', 'M', 0, |
| /* 20107 */ 'C', 'V', 'T', '_', 'W', '_', 'S', '_', 'M', 'M', 0, |
| /* 20118 */ 'B', 'C', '1', 'T', '_', 'M', 'M', 0, |
| /* 20126 */ 'D', 'E', 'R', 'E', 'T', '_', 'M', 'M', 0, |
| /* 20135 */ 'W', 'A', 'I', 'T', '_', 'M', 'M', 0, |
| /* 20143 */ 'S', 'L', 'T', '_', 'M', 'M', 0, |
| /* 20150 */ 'T', 'L', 'T', '_', 'M', 'M', 0, |
| /* 20157 */ 'P', 's', 'e', 'u', 'd', 'o', 'M', 'U', 'L', 'T', '_', 'M', 'M', 0, |
| /* 20171 */ 'E', 'X', 'T', '_', 'M', 'M', 0, |
| /* 20178 */ 'P', 's', 'e', 'u', 'd', 'o', 'M', 'S', 'U', 'B', 'U', '_', 'M', 'M', 0, |
| /* 20193 */ 'P', 's', 'e', 'u', 'd', 'o', 'M', 'A', 'D', 'D', 'U', '_', 'M', 'M', 0, |
| /* 20208 */ 'T', 'G', 'E', 'U', '_', 'M', 'M', 0, |
| /* 20216 */ 'T', 'G', 'E', 'I', 'U', '_', 'M', 'M', 0, |
| /* 20225 */ 'T', 'L', 'T', 'I', 'U', '_', 'M', 'M', 0, |
| /* 20234 */ 'T', 'L', 'T', 'U', '_', 'M', 'M', 0, |
| /* 20242 */ 'L', 'W', 'U', '_', 'M', 'M', 0, |
| /* 20249 */ 'S', 'R', 'A', 'V', '_', 'M', 'M', 0, |
| /* 20257 */ 'B', 'I', 'T', 'R', 'E', 'V', '_', 'M', 'M', 0, |
| /* 20267 */ 'S', 'D', 'I', 'V', '_', 'M', 'M', 0, |
| /* 20275 */ 'U', 'D', 'I', 'V', '_', 'M', 'M', 0, |
| /* 20283 */ 'S', 'L', 'L', 'V', '_', 'M', 'M', 0, |
| /* 20291 */ 'S', 'R', 'L', 'V', '_', 'M', 'M', 0, |
| /* 20299 */ 'T', 'L', 'B', 'G', 'I', 'N', 'V', '_', 'M', 'M', 0, |
| /* 20310 */ 'S', 'H', 'I', 'L', 'O', 'V', '_', 'M', 'M', 0, |
| /* 20320 */ 'E', 'X', 'T', 'P', 'D', 'P', 'V', '_', 'M', 'M', 0, |
| /* 20331 */ 'E', 'X', 'T', 'P', 'V', '_', 'M', 'M', 0, |
| /* 20340 */ 'R', 'O', 'T', 'R', 'V', '_', 'M', 'M', 0, |
| /* 20349 */ 'I', 'N', 'S', 'V', '_', 'M', 'M', 0, |
| /* 20357 */ 'L', 'W', '_', 'M', 'M', 0, |
| /* 20363 */ 'S', 'W', '_', 'M', 'M', 0, |
| /* 20369 */ 'C', 'V', 'T', '_', 'D', '3', '2', '_', 'W', '_', 'M', 'M', 0, |
| /* 20382 */ 'C', 'V', 'T', '_', 'D', '6', '4', '_', 'W', '_', 'M', 'M', 0, |
| /* 20395 */ 'T', 'R', 'U', 'N', 'C', '_', 'W', '_', 'M', 'M', 0, |
| /* 20406 */ 'R', 'O', 'U', 'N', 'D', '_', 'W', '_', 'M', 'M', 0, |
| /* 20417 */ 'P', 'R', 'E', 'C', 'R', 'Q', '_', 'P', 'H', '_', 'W', '_', 'M', 'M', 0, |
| /* 20432 */ 'P', 'R', 'E', 'C', 'R', 'Q', '_', 'R', 'S', '_', 'P', 'H', '_', 'W', '_', 'M', 'M', 0, |
| /* 20450 */ 'C', 'E', 'I', 'L', '_', 'W', '_', 'M', 'M', 0, |
| /* 20460 */ 'D', 'P', 'A', 'Q', '_', 'S', 'A', '_', 'L', '_', 'W', '_', 'M', 'M', 0, |
| /* 20475 */ 'D', 'P', 'S', 'Q', '_', 'S', 'A', '_', 'L', '_', 'W', '_', 'M', 'M', 0, |
| /* 20490 */ 'F', 'L', 'O', 'O', 'R', '_', 'W', '_', 'M', 'M', 0, |
| /* 20501 */ 'E', 'X', 'T', 'R', '_', 'W', '_', 'M', 'M', 0, |
| /* 20511 */ 'S', 'H', 'R', 'A', '_', 'R', '_', 'W', '_', 'M', 'M', 0, |
| /* 20523 */ 'E', 'X', 'T', 'R', '_', 'R', '_', 'W', '_', 'M', 'M', 0, |
| /* 20535 */ 'S', 'H', 'R', 'A', 'V', '_', 'R', '_', 'W', '_', 'M', 'M', 0, |
| /* 20548 */ 'E', 'X', 'T', 'R', 'V', '_', 'R', '_', 'W', '_', 'M', 'M', 0, |
| /* 20561 */ 'E', 'X', 'T', 'R', '_', 'R', 'S', '_', 'W', '_', 'M', 'M', 0, |
| /* 20574 */ 'E', 'X', 'T', 'R', 'V', '_', 'R', 'S', '_', 'W', '_', 'M', 'M', 0, |
| /* 20588 */ 'S', 'H', 'L', 'L', '_', 'S', '_', 'W', '_', 'M', 'M', 0, |
| /* 20600 */ 'S', 'U', 'B', 'Q', '_', 'S', '_', 'W', '_', 'M', 'M', 0, |
| /* 20612 */ 'A', 'D', 'D', 'Q', '_', 'S', '_', 'W', '_', 'M', 'M', 0, |
| /* 20624 */ 'A', 'B', 'S', 'Q', '_', 'S', '_', 'W', '_', 'M', 'M', 0, |
| /* 20636 */ 'C', 'V', 'T', '_', 'S', '_', 'W', '_', 'M', 'M', 0, |
| /* 20647 */ 'S', 'H', 'L', 'L', 'V', '_', 'S', '_', 'W', '_', 'M', 'M', 0, |
| /* 20660 */ 'E', 'X', 'T', 'R', 'V', '_', 'W', '_', 'M', 'M', 0, |
| /* 20671 */ 'P', 'R', 'E', 'F', 'X', '_', 'M', 'M', 0, |
| /* 20680 */ 'L', 'H', 'X', '_', 'M', 'M', 0, |
| /* 20687 */ 'J', 'A', 'L', 'X', '_', 'M', 'M', 0, |
| /* 20695 */ 'L', 'B', 'U', 'X', '_', 'M', 'M', 0, |
| /* 20703 */ 'L', 'W', 'X', '_', 'M', 'M', 0, |
| /* 20710 */ 'B', 'G', 'E', 'Z', '_', 'M', 'M', 0, |
| /* 20718 */ 'B', 'L', 'E', 'Z', '_', 'M', 'M', 0, |
| /* 20726 */ 'C', 'L', 'Z', '_', 'M', 'M', 0, |
| /* 20733 */ 'B', 'G', 'T', 'Z', '_', 'M', 'M', 0, |
| /* 20741 */ 'B', 'L', 'T', 'Z', '_', 'M', 'M', 0, |
| /* 20749 */ 'P', 's', 'e', 'u', 'd', 'o', 'I', 'n', 'd', 'i', 'r', 'e', 'c', 't', 'B', 'r', 'a', 'n', 'c', 'h', '_', 'M', 'M', 0, |
| /* 20773 */ 'A', 'D', 'D', 'i', '_', 'M', 'M', 0, |
| /* 20781 */ 'A', 'N', 'D', 'i', '_', 'M', 'M', 0, |
| /* 20789 */ 'X', 'O', 'R', 'i', '_', 'M', 'M', 0, |
| /* 20797 */ 'S', 'L', 'T', 'i', '_', 'M', 'M', 0, |
| /* 20805 */ 'L', 'U', 'i', '_', 'M', 'M', 0, |
| /* 20812 */ 'L', 'B', 'u', '_', 'M', 'M', 0, |
| /* 20819 */ 'S', 'U', 'B', 'u', '_', 'M', 'M', 0, |
| /* 20827 */ 'A', 'D', 'D', 'u', '_', 'M', 'M', 0, |
| /* 20835 */ 'L', 'H', 'u', '_', 'M', 'M', 0, |
| /* 20842 */ 'S', 'L', 'T', 'u', '_', 'M', 'M', 0, |
| /* 20850 */ 'P', 's', 'e', 'u', 'd', 'o', 'M', 'U', 'L', 'T', 'u', '_', 'M', 'M', 0, |
| /* 20865 */ 'L', 'E', 'A', '_', 'A', 'D', 'D', 'i', 'u', '_', 'M', 'M', 0, |
| /* 20878 */ 'S', 'L', 'T', 'i', 'u', '_', 'M', 'M', 0, |
| /* 20887 */ 'I', 'N', 'L', 'I', 'N', 'E', 'A', 'S', 'M', 0, |
| /* 20897 */ 'D', 'I', 'N', 'S', 'M', 0, |
| /* 20903 */ 'D', 'E', 'X', 'T', 'M', 0, |
| /* 20909 */ 'G', '_', 'F', 'M', 'I', 'N', 'I', 'M', 'U', 'M', 0, |
| /* 20920 */ 'G', '_', 'F', 'M', 'A', 'X', 'I', 'M', 'U', 'M', 0, |
| /* 20931 */ 'G', '_', 'F', 'M', 'I', 'N', 'N', 'U', 'M', 0, |
| /* 20941 */ 'G', '_', 'F', 'M', 'A', 'X', 'N', 'U', 'M', 0, |
| /* 20951 */ 'G', '_', 'I', 'N', 'T', 'R', 'I', 'N', 'S', 'I', 'C', '_', 'R', 'O', 'U', 'N', 'D', 'E', 'V', 'E', 'N', 0, |
| /* 20973 */ 'B', 'A', 'L', 'I', 'G', 'N', 0, |
| /* 20980 */ 'D', 'A', 'L', 'I', 'G', 'N', 0, |
| /* 20987 */ 'G', '_', 'A', 'S', 'S', 'E', 'R', 'T', '_', 'A', 'L', 'I', 'G', 'N', 0, |
| /* 21002 */ 'G', '_', 'F', 'C', 'O', 'P', 'Y', 'S', 'I', 'G', 'N', 0, |
| /* 21014 */ 'G', '_', 'V', 'E', 'C', 'R', 'E', 'D', 'U', 'C', 'E', '_', 'F', 'M', 'I', 'N', 0, |
| /* 21031 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'F', 'M', 'I', 'N', 0, |
| /* 21048 */ 'G', '_', 'V', 'E', 'C', 'R', 'E', 'D', 'U', 'C', 'E', '_', 'S', 'M', 'I', 'N', 0, |
| /* 21065 */ 'G', '_', 'S', 'M', 'I', 'N', 0, |
| /* 21072 */ 'G', '_', 'V', 'E', 'C', 'R', 'E', 'D', 'U', 'C', 'E', '_', 'U', 'M', 'I', 'N', 0, |
| /* 21089 */ 'G', '_', 'U', 'M', 'I', 'N', 0, |
| /* 21096 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'U', 'M', 'I', 'N', 0, |
| /* 21113 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'M', 'I', 'N', 0, |
| /* 21129 */ 'G', '_', 'F', 'S', 'I', 'N', 0, |
| /* 21136 */ 'D', 'M', 'F', 'C', '2', '_', 'O', 'C', 'T', 'E', 'O', 'N', 0, |
| /* 21149 */ 'D', 'M', 'T', 'C', '2', '_', 'O', 'C', 'T', 'E', 'O', 'N', 0, |
| /* 21162 */ 'C', 'F', 'I', '_', 'I', 'N', 'S', 'T', 'R', 'U', 'C', 'T', 'I', 'O', 'N', 0, |
| /* 21178 */ 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'D', 'O', 'W', 'N', 0, |
| /* 21195 */ 'G', '_', 'S', 'S', 'U', 'B', 'O', 0, |
| /* 21203 */ 'G', '_', 'U', 'S', 'U', 'B', 'O', 0, |
| /* 21211 */ 'G', '_', 'S', 'A', 'D', 'D', 'O', 0, |
| /* 21219 */ 'G', '_', 'U', 'A', 'D', 'D', 'O', 0, |
| /* 21227 */ 'F', 'E', 'X', 'P', '2', '_', 'D', '_', '1', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0, |
| /* 21244 */ 'F', 'E', 'X', 'P', '2', '_', 'W', '_', '1', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0, |
| /* 21261 */ 'B', 'P', 'O', 'S', 'G', 'E', '3', '2', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0, |
| /* 21277 */ 'I', 'N', 'S', 'E', 'R', 'T', '_', 'B', '_', 'V', 'I', 'D', 'X', '6', '4', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0, |
| /* 21300 */ 'I', 'N', 'S', 'E', 'R', 'T', '_', 'F', 'D', '_', 'V', 'I', 'D', 'X', '6', '4', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0, |
| /* 21324 */ 'I', 'N', 'S', 'E', 'R', 'T', '_', 'D', '_', 'V', 'I', 'D', 'X', '6', '4', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0, |
| /* 21347 */ 'I', 'N', 'S', 'E', 'R', 'T', '_', 'H', '_', 'V', 'I', 'D', 'X', '6', '4', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0, |
| /* 21370 */ 'I', 'N', 'S', 'E', 'R', 'T', '_', 'F', 'W', '_', 'V', 'I', 'D', 'X', '6', '4', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0, |
| /* 21394 */ 'I', 'N', 'S', 'E', 'R', 'T', '_', 'W', '_', 'V', 'I', 'D', 'X', '6', '4', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0, |
| /* 21417 */ 'S', 'N', 'Z', '_', 'B', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0, |
| /* 21430 */ 'S', 'Z', '_', 'B', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0, |
| /* 21442 */ 'B', 'S', 'E', 'L', '_', 'F', 'D', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0, |
| /* 21457 */ 'F', 'I', 'L', 'L', '_', 'F', 'D', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0, |
| /* 21472 */ 'I', 'N', 'S', 'E', 'R', 'T', '_', 'F', 'D', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0, |
| /* 21489 */ 'C', 'O', 'P', 'Y', '_', 'F', 'D', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0, |
| /* 21504 */ 'M', 'S', 'A', '_', 'F', 'P', '_', 'E', 'X', 'T', 'E', 'N', 'D', '_', 'D', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0, |
| /* 21527 */ 'M', 'S', 'A', '_', 'F', 'P', '_', 'R', 'O', 'U', 'N', 'D', '_', 'D', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0, |
| /* 21549 */ 'B', 'S', 'E', 'L', '_', 'D', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0, |
| /* 21563 */ 'A', 'N', 'D', '_', 'V', '_', 'D', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0, |
| /* 21578 */ 'N', 'O', 'R', '_', 'V', '_', 'D', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0, |
| /* 21593 */ 'X', 'O', 'R', '_', 'V', '_', 'D', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0, |
| /* 21608 */ 'S', 'N', 'Z', '_', 'D', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0, |
| /* 21621 */ 'S', 'Z', '_', 'D', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0, |
| /* 21633 */ 'B', 'S', 'E', 'L', '_', 'H', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0, |
| /* 21647 */ 'A', 'N', 'D', '_', 'V', '_', 'H', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0, |
| /* 21662 */ 'N', 'O', 'R', '_', 'V', '_', 'H', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0, |
| /* 21677 */ 'X', 'O', 'R', '_', 'V', '_', 'H', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0, |
| /* 21692 */ 'S', 'N', 'Z', '_', 'H', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0, |
| /* 21705 */ 'S', 'Z', '_', 'H', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0, |
| /* 21717 */ 'S', 'N', 'Z', '_', 'V', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0, |
| /* 21730 */ 'S', 'Z', '_', 'V', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0, |
| /* 21742 */ 'B', 'S', 'E', 'L', '_', 'F', 'W', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0, |
| /* 21757 */ 'F', 'I', 'L', 'L', '_', 'F', 'W', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0, |
| /* 21772 */ 'I', 'N', 'S', 'E', 'R', 'T', '_', 'F', 'W', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0, |
| /* 21789 */ 'C', 'O', 'P', 'Y', '_', 'F', 'W', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0, |
| /* 21804 */ 'M', 'S', 'A', '_', 'F', 'P', '_', 'E', 'X', 'T', 'E', 'N', 'D', '_', 'W', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0, |
| /* 21827 */ 'M', 'S', 'A', '_', 'F', 'P', '_', 'R', 'O', 'U', 'N', 'D', '_', 'W', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0, |
| /* 21849 */ 'B', 'S', 'E', 'L', '_', 'W', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0, |
| /* 21863 */ 'A', 'N', 'D', '_', 'V', '_', 'W', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0, |
| /* 21878 */ 'N', 'O', 'R', '_', 'V', '_', 'W', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0, |
| /* 21893 */ 'X', 'O', 'R', '_', 'V', '_', 'W', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0, |
| /* 21908 */ 'S', 'N', 'Z', '_', 'W', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0, |
| /* 21921 */ 'S', 'Z', '_', 'W', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0, |
| /* 21933 */ 'I', 'N', 'S', 'E', 'R', 'T', '_', 'B', '_', 'V', 'I', 'D', 'X', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0, |
| /* 21954 */ 'I', 'N', 'S', 'E', 'R', 'T', '_', 'F', 'D', '_', 'V', 'I', 'D', 'X', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0, |
| /* 21976 */ 'I', 'N', 'S', 'E', 'R', 'T', '_', 'D', '_', 'V', 'I', 'D', 'X', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0, |
| /* 21997 */ 'I', 'N', 'S', 'E', 'R', 'T', '_', 'H', '_', 'V', 'I', 'D', 'X', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0, |
| /* 22018 */ 'I', 'N', 'S', 'E', 'R', 'T', '_', 'F', 'W', '_', 'V', 'I', 'D', 'X', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0, |
| /* 22040 */ 'I', 'N', 'S', 'E', 'R', 'T', '_', 'W', '_', 'V', 'I', 'D', 'X', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0, |
| /* 22061 */ 'D', 'C', 'L', 'O', 0, |
| /* 22066 */ 'P', 's', 'e', 'u', 'd', 'o', 'M', 'F', 'L', 'O', 0, |
| /* 22077 */ 'S', 'H', 'I', 'L', 'O', 0, |
| /* 22083 */ 'M', 'F', 'T', 'L', 'O', 0, |
| /* 22089 */ 'M', 'T', 'L', 'O', 0, |
| /* 22094 */ 'M', 'T', 'T', 'L', 'O', 0, |
| /* 22100 */ 'G', '_', 'S', 'M', 'U', 'L', 'O', 0, |
| /* 22108 */ 'G', '_', 'U', 'M', 'U', 'L', 'O', 0, |
| /* 22116 */ 'G', '_', 'B', 'Z', 'E', 'R', 'O', 0, |
| /* 22124 */ 'S', 'T', 'A', 'C', 'K', 'M', 'A', 'P', 0, |
| /* 22133 */ 'T', 'R', 'A', 'P', 0, |
| /* 22138 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'U', 'D', 'E', 'C', '_', 'W', 'R', 'A', 'P', 0, |
| /* 22160 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'U', 'I', 'N', 'C', '_', 'W', 'R', 'A', 'P', 0, |
| /* 22182 */ 'G', '_', 'B', 'S', 'W', 'A', 'P', 0, |
| /* 22190 */ 'D', 'B', 'I', 'T', 'S', 'W', 'A', 'P', 0, |
| /* 22199 */ 'S', 'D', 'B', 'B', 'P', 0, |
| /* 22205 */ 'T', 'L', 'B', 'P', 0, |
| /* 22210 */ 'E', 'X', 'T', 'P', 'D', 'P', 0, |
| /* 22217 */ 'G', '_', 'S', 'I', 'T', 'O', 'F', 'P', 0, |
| /* 22226 */ 'G', '_', 'U', 'I', 'T', 'O', 'F', 'P', 0, |
| /* 22235 */ 'T', 'L', 'B', 'G', 'P', 0, |
| /* 22241 */ 'M', 'T', 'H', 'L', 'I', 'P', 0, |
| /* 22248 */ 'G', '_', 'F', 'C', 'M', 'P', 0, |
| /* 22255 */ 'G', '_', 'I', 'C', 'M', 'P', 0, |
| /* 22262 */ 'S', 'S', 'N', 'O', 'P', 0, |
| /* 22268 */ 'D', 'P', 'O', 'P', 0, |
| /* 22273 */ 'G', '_', 'C', 'T', 'P', 'O', 'P', 0, |
| /* 22281 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'O', 'P', 0, |
| /* 22294 */ 'F', 'A', 'U', 'L', 'T', 'I', 'N', 'G', '_', 'O', 'P', 0, |
| /* 22306 */ 'L', 'O', 'A', 'D', '_', 'A', 'C', 'C', '6', '4', 'D', 'S', 'P', 0, |
| /* 22320 */ 'S', 'T', 'O', 'R', 'E', '_', 'A', 'C', 'C', '6', '4', 'D', 'S', 'P', 0, |
| /* 22335 */ 'R', 'D', 'D', 'S', 'P', 0, |
| /* 22341 */ 'W', 'R', 'D', 'S', 'P', 0, |
| /* 22347 */ 'M', 'F', 'T', 'D', 'S', 'P', 0, |
| /* 22354 */ 'M', 'T', 'T', 'D', 'S', 'P', 0, |
| /* 22361 */ 'L', 'W', 'D', 'S', 'P', 0, |
| /* 22367 */ 'S', 'W', 'D', 'S', 'P', 0, |
| /* 22373 */ 'M', 'S', 'U', 'B', '_', 'D', 'S', 'P', 0, |
| /* 22382 */ 'M', 'A', 'D', 'D', '_', 'D', 'S', 'P', 0, |
| /* 22391 */ 'L', 'O', 'A', 'D', '_', 'C', 'C', 'O', 'N', 'D', '_', 'D', 'S', 'P', 0, |
| /* 22406 */ 'S', 'T', 'O', 'R', 'E', '_', 'C', 'C', 'O', 'N', 'D', '_', 'D', 'S', 'P', 0, |
| /* 22422 */ 'M', 'F', 'H', 'I', '_', 'D', 'S', 'P', 0, |
| /* 22431 */ 'P', 's', 'e', 'u', 'd', 'o', 'M', 'T', 'L', 'O', 'H', 'I', '_', 'D', 'S', 'P', 0, |
| /* 22448 */ 'M', 'T', 'H', 'I', '_', 'D', 'S', 'P', 0, |
| /* 22457 */ 'M', 'F', 'L', 'O', '_', 'D', 'S', 'P', 0, |
| /* 22466 */ 'M', 'T', 'L', 'O', '_', 'D', 'S', 'P', 0, |
| /* 22475 */ 'M', 'U', 'L', 'T', '_', 'D', 'S', 'P', 0, |
| /* 22484 */ 'M', 'S', 'U', 'B', 'U', '_', 'D', 'S', 'P', 0, |
| /* 22494 */ 'M', 'A', 'D', 'D', 'U', '_', 'D', 'S', 'P', 0, |
| /* 22504 */ 'M', 'U', 'L', 'T', 'U', '_', 'D', 'S', 'P', 0, |
| /* 22514 */ 'J', 'R', 'A', 'D', 'D', 'I', 'U', 'S', 'P', 0, |
| /* 22524 */ 'E', 'X', 'T', 'P', 0, |
| /* 22529 */ 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'U', 'P', 0, |
| /* 22544 */ 'P', 'R', 'E', 'A', 'L', 'L', 'O', 'C', 'A', 'T', 'E', 'D', '_', 'S', 'E', 'T', 'U', 'P', 0, |
| /* 22563 */ 'D', 'V', 'P', 0, |
| /* 22567 */ 'E', 'V', 'P', 0, |
| /* 22571 */ 'G', '_', 'F', 'E', 'X', 'P', 0, |
| /* 22578 */ 'B', 'E', 'Q', 0, |
| /* 22582 */ 'S', 'E', 'Q', 0, |
| /* 22586 */ 'T', 'E', 'Q', 0, |
| /* 22590 */ 'T', 'L', 'B', 'R', 0, |
| /* 22595 */ 'M', 'U', 'L', 'E', 'U', '_', 'S', '_', 'P', 'H', '_', 'Q', 'B', 'R', 0, |
| /* 22610 */ 'P', 'R', 'E', 'C', 'E', 'U', '_', 'P', 'H', '_', 'Q', 'B', 'R', 0, |
| /* 22624 */ 'P', 'R', 'E', 'C', 'E', 'Q', 'U', '_', 'P', 'H', '_', 'Q', 'B', 'R', 0, |
| /* 22639 */ 'D', 'P', 'A', 'U', '_', 'H', '_', 'Q', 'B', 'R', 0, |
| /* 22650 */ 'D', 'P', 'S', 'U', '_', 'H', '_', 'Q', 'B', 'R', 0, |
| /* 22661 */ 'G', '_', 'B', 'R', 0, |
| /* 22666 */ 'B', 'A', 'L', '_', 'B', 'R', 0, |
| /* 22673 */ 'I', 'N', 'L', 'I', 'N', 'E', 'A', 'S', 'M', '_', 'B', 'R', 0, |
| /* 22686 */ 'G', '_', 'B', 'L', 'O', 'C', 'K', '_', 'A', 'D', 'D', 'R', 0, |
| /* 22699 */ 'L', 'D', 'R', 0, |
| /* 22703 */ 'S', 'D', 'R', 0, |
| /* 22707 */ 'M', 'E', 'M', 'B', 'A', 'R', 'R', 'I', 'E', 'R', 0, |
| /* 22718 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'F', 'U', 'N', 'C', 'T', 'I', 'O', 'N', '_', 'E', 'N', 'T', 'E', 'R', 0, |
| /* 22743 */ 'G', '_', 'R', 'E', 'A', 'D', 'C', 'Y', 'C', 'L', 'E', 'C', 'O', 'U', 'N', 'T', 'E', 'R', 0, |
| /* 22762 */ 'G', '_', 'R', 'E', 'A', 'D', '_', 'R', 'E', 'G', 'I', 'S', 'T', 'E', 'R', 0, |
| /* 22778 */ 'G', '_', 'W', 'R', 'I', 'T', 'E', '_', 'R', 'E', 'G', 'I', 'S', 'T', 'E', 'R', 0, |
| /* 22795 */ 'T', 'L', 'B', 'G', 'R', 0, |
| /* 22801 */ 'L', 'o', 'a', 'd', 'I', 'm', 'm', 'D', 'o', 'u', 'b', 'l', 'e', 'F', 'G', 'R', 0, |
| /* 22818 */ 'L', 'o', 'a', 'd', 'I', 'm', 'm', 'S', 'i', 'n', 'g', 'l', 'e', 'F', 'G', 'R', 0, |
| /* 22835 */ 'M', 'A', 'Q', '_', 'S', 'A', '_', 'W', '_', 'P', 'H', 'R', 0, |
| /* 22848 */ 'P', 'R', 'E', 'C', 'E', 'Q', '_', 'W', '_', 'P', 'H', 'R', 0, |
| /* 22861 */ 'M', 'A', 'Q', '_', 'S', '_', 'W', '_', 'P', 'H', 'R', 0, |
| /* 22873 */ 'M', 'U', 'L', 'E', 'Q', '_', 'S', '_', 'W', '_', 'P', 'H', 'R', 0, |
| /* 22887 */ 'G', '_', 'A', 'S', 'H', 'R', 0, |
| /* 22894 */ 'G', '_', 'F', 'S', 'H', 'R', 0, |
| /* 22901 */ 'G', '_', 'L', 'S', 'H', 'R', 0, |
| /* 22908 */ 'J', 'R', 0, |
| /* 22911 */ 'J', 'A', 'L', 'R', 0, |
| /* 22916 */ 'N', 'O', 'R', 0, |
| /* 22920 */ 'G', '_', 'F', 'F', 'L', 'O', 'O', 'R', 0, |
| /* 22929 */ 'D', 'R', 'O', 'R', 0, |
| /* 22934 */ 'G', '_', 'B', 'U', 'I', 'L', 'D', '_', 'V', 'E', 'C', 'T', 'O', 'R', 0, |
| /* 22949 */ 'G', '_', 'S', 'H', 'U', 'F', 'F', 'L', 'E', '_', 'V', 'E', 'C', 'T', 'O', 'R', 0, |
| /* 22966 */ 'G', '_', 'V', 'E', 'C', 'R', 'E', 'D', 'U', 'C', 'E', '_', 'X', 'O', 'R', 0, |
| /* 22982 */ 'G', '_', 'X', 'O', 'R', 0, |
| /* 22988 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'X', 'O', 'R', 0, |
| /* 23004 */ 'G', '_', 'V', 'E', 'C', 'R', 'E', 'D', 'U', 'C', 'E', '_', 'O', 'R', 0, |
| /* 23019 */ 'G', '_', 'O', 'R', 0, |
| /* 23024 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'O', 'R', 0, |
| /* 23039 */ 'M', 'F', 'T', 'G', 'P', 'R', 0, |
| /* 23046 */ 'M', 'T', 'T', 'G', 'P', 'R', 0, |
| /* 23053 */ 'L', 'o', 'a', 'd', 'I', 'm', 'm', 'D', 'o', 'u', 'b', 'l', 'e', 'G', 'P', 'R', 0, |
| /* 23070 */ 'L', 'o', 'a', 'd', 'I', 'm', 'm', 'S', 'i', 'n', 'g', 'l', 'e', 'G', 'P', 'R', 0, |
| /* 23087 */ 'M', 'F', 'T', 'R', 0, |
| /* 23092 */ 'D', 'R', 'O', 'T', 'R', 0, |
| /* 23098 */ 'G', '_', 'R', 'O', 'T', 'R', 0, |
| /* 23105 */ 'G', '_', 'I', 'N', 'T', 'T', 'O', 'P', 'T', 'R', 0, |
| /* 23116 */ 'M', 'T', 'T', 'R', 0, |
| /* 23121 */ 'T', 'L', 'B', 'W', 'R', 0, |
| /* 23127 */ 'T', 'L', 'B', 'G', 'W', 'R', 0, |
| /* 23134 */ 'R', 'D', 'H', 'W', 'R', 0, |
| /* 23140 */ 'L', 'W', 'R', 0, |
| /* 23144 */ 'S', 'W', 'R', 0, |
| /* 23148 */ 'G', '_', 'F', 'A', 'B', 'S', 0, |
| /* 23155 */ 'G', '_', 'A', 'B', 'S', 0, |
| /* 23161 */ 'G', '_', 'U', 'N', 'M', 'E', 'R', 'G', 'E', '_', 'V', 'A', 'L', 'U', 'E', 'S', 0, |
| /* 23178 */ 'G', '_', 'M', 'E', 'R', 'G', 'E', '_', 'V', 'A', 'L', 'U', 'E', 'S', 0, |
| /* 23193 */ 'C', 'I', 'N', 'S', 0, |
| /* 23198 */ 'D', 'I', 'N', 'S', 0, |
| /* 23203 */ 'G', '_', 'F', 'C', 'O', 'S', 0, |
| /* 23210 */ 'G', '_', 'C', 'O', 'N', 'C', 'A', 'T', '_', 'V', 'E', 'C', 'T', 'O', 'R', 'S', 0, |
| /* 23227 */ 'C', 'O', 'P', 'Y', '_', 'T', 'O', '_', 'R', 'E', 'G', 'C', 'L', 'A', 'S', 'S', 0, |
| /* 23244 */ 'G', '_', 'I', 'S', '_', 'F', 'P', 'C', 'L', 'A', 'S', 'S', 0, |
| /* 23257 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'C', 'M', 'P', 'X', 'C', 'H', 'G', '_', 'W', 'I', 'T', 'H', '_', 'S', 'U', 'C', 'C', 'E', 'S', 'S', 0, |
| /* 23287 */ 'G', '_', 'I', 'N', 'T', 'R', 'I', 'N', 'S', 'I', 'C', '_', 'W', '_', 'S', 'I', 'D', 'E', '_', 'E', 'F', 'F', 'E', 'C', 'T', 'S', 0, |
| /* 23314 */ 'E', 'X', 'T', 'S', 0, |
| /* 23319 */ 'C', 'V', 'T', '_', 'D', '3', '2', '_', 'S', 0, |
| /* 23329 */ 'C', 'V', 'T', '_', 'D', '6', '4', '_', 'S', 0, |
| /* 23339 */ 'M', 'O', 'V', 'N', '_', 'I', '6', '4', '_', 'S', 0, |
| /* 23350 */ 'M', 'O', 'V', 'Z', '_', 'I', '6', '4', '_', 'S', 0, |
| /* 23361 */ 'M', 'I', 'N', 'A', '_', 'S', 0, |
| /* 23368 */ 'M', 'A', 'X', 'A', '_', 'S', 0, |
| /* 23375 */ 'F', 'S', 'U', 'B', '_', 'S', 0, |
| /* 23382 */ 'N', 'M', 'S', 'U', 'B', '_', 'S', 0, |
| /* 23390 */ 'F', 'A', 'D', 'D', '_', 'S', 0, |
| /* 23397 */ 'N', 'M', 'A', 'D', 'D', '_', 'S', 0, |
| /* 23405 */ 'C', '_', 'N', 'G', 'E', '_', 'S', 0, |
| /* 23413 */ 'C', '_', 'N', 'G', 'L', 'E', '_', 'S', 0, |
| /* 23422 */ 'C', '_', 'O', 'L', 'E', '_', 'S', 0, |
| /* 23430 */ 'C', 'M', 'P', '_', 'S', 'L', 'E', '_', 'S', 0, |
| /* 23440 */ 'C', 'M', 'P', '_', 'S', 'U', 'L', 'E', '_', 'S', 0, |
| /* 23451 */ 'C', '_', 'U', 'L', 'E', '_', 'S', 0, |
| /* 23459 */ 'C', 'M', 'P', '_', 'U', 'L', 'E', '_', 'S', 0, |
| /* 23469 */ 'C', '_', 'L', 'E', '_', 'S', 0, |
| /* 23476 */ 'C', 'M', 'P', '_', 'L', 'E', '_', 'S', 0, |
| /* 23485 */ 'C', 'M', 'P', '_', 'S', 'A', 'F', '_', 'S', 0, |
| /* 23495 */ 'M', 'S', 'U', 'B', 'F', '_', 'S', 0, |
| /* 23503 */ 'M', 'A', 'D', 'D', 'F', '_', 'S', 0, |
| /* 23511 */ 'C', '_', 'S', 'F', '_', 'S', 0, |
| /* 23518 */ 'M', 'O', 'V', 'F', '_', 'S', 0, |
| /* 23525 */ 'C', '_', 'F', '_', 'S', 0, |
| /* 23531 */ 'P', 's', 'e', 'u', 'd', 'o', 'S', 'E', 'L', 'E', 'C', 'T', 'F', 'P', '_', 'F', '_', 'S', 0, |
| /* 23550 */ 'C', 'M', 'P', '_', 'F', '_', 'S', 0, |
| /* 23558 */ 'F', 'N', 'E', 'G', '_', 'S', 0, |
| /* 23565 */ 'M', 'O', 'V', 'N', '_', 'I', '_', 'S', 0, |
| /* 23574 */ 'M', 'O', 'V', 'Z', '_', 'I', '_', 'S', 0, |
| /* 23583 */ 'S', 'E', 'L', '_', 'S', 0, |
| /* 23589 */ 'C', '_', 'N', 'G', 'L', '_', 'S', 0, |
| /* 23597 */ 'F', 'M', 'U', 'L', '_', 'S', 0, |
| /* 23604 */ 'T', 'R', 'U', 'N', 'C', '_', 'L', '_', 'S', 0, |
| /* 23614 */ 'R', 'O', 'U', 'N', 'D', '_', 'L', '_', 'S', 0, |
| /* 23624 */ 'C', 'E', 'I', 'L', '_', 'L', '_', 'S', 0, |
| /* 23633 */ 'F', 'L', 'O', 'O', 'R', '_', 'L', '_', 'S', 0, |
| /* 23643 */ 'C', 'V', 'T', '_', 'L', '_', 'S', 0, |
| /* 23651 */ 'M', 'I', 'N', '_', 'S', 0, |
| /* 23657 */ 'C', 'M', 'P', '_', 'S', 'U', 'N', '_', 'S', 0, |
| /* 23667 */ 'C', '_', 'U', 'N', '_', 'S', 0, |
| /* 23674 */ 'C', 'M', 'P', '_', 'U', 'N', '_', 'S', 0, |
| /* 23683 */ 'R', 'E', 'C', 'I', 'P', '_', 'S', 0, |
| /* 23691 */ 'C', '_', 'S', 'E', 'Q', '_', 'S', 0, |
| /* 23699 */ 'C', 'M', 'P', '_', 'S', 'E', 'Q', '_', 'S', 0, |
| /* 23709 */ 'C', 'M', 'P', '_', 'S', 'U', 'E', 'Q', '_', 'S', 0, |
| /* 23720 */ 'C', '_', 'U', 'E', 'Q', '_', 'S', 0, |
| /* 23728 */ 'C', 'M', 'P', '_', 'U', 'E', 'Q', '_', 'S', 0, |
| /* 23738 */ 'C', '_', 'E', 'Q', '_', 'S', 0, |
| /* 23745 */ 'C', 'M', 'P', '_', 'E', 'Q', '_', 'S', 0, |
| /* 23754 */ 'F', 'A', 'B', 'S', '_', 'S', 0, |
| /* 23761 */ 'C', 'L', 'A', 'S', 'S', '_', 'S', 0, |
| /* 23769 */ 'P', 's', 'e', 'u', 'd', 'o', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'S', 0, |
| /* 23784 */ 'C', '_', 'N', 'G', 'T', '_', 'S', 0, |
| /* 23792 */ 'C', '_', 'O', 'L', 'T', '_', 'S', 0, |
| /* 23800 */ 'C', 'M', 'P', '_', 'S', 'L', 'T', '_', 'S', 0, |
| /* 23810 */ 'C', 'M', 'P', '_', 'S', 'U', 'L', 'T', '_', 'S', 0, |
| /* 23821 */ 'C', '_', 'U', 'L', 'T', '_', 'S', 0, |
| /* 23829 */ 'C', 'M', 'P', '_', 'U', 'L', 'T', '_', 'S', 0, |
| /* 23839 */ 'C', '_', 'L', 'T', '_', 'S', 0, |
| /* 23846 */ 'C', 'M', 'P', '_', 'L', 'T', '_', 'S', 0, |
| /* 23855 */ 'R', 'I', 'N', 'T', '_', 'S', 0, |
| /* 23862 */ 'F', 'S', 'Q', 'R', 'T', '_', 'S', 0, |
| /* 23870 */ 'R', 'S', 'Q', 'R', 'T', '_', 'S', 0, |
| /* 23878 */ 'M', 'O', 'V', 'T', '_', 'S', 0, |
| /* 23885 */ 'P', 's', 'e', 'u', 'd', 'o', 'S', 'E', 'L', 'E', 'C', 'T', 'F', 'P', '_', 'T', '_', 'S', 0, |
| /* 23904 */ 'F', 'D', 'I', 'V', '_', 'S', 0, |
| /* 23911 */ 'F', 'M', 'O', 'V', '_', 'S', 0, |
| /* 23918 */ 'P', 's', 'e', 'u', 'd', 'o', 'T', 'R', 'U', 'N', 'C', '_', 'W', '_', 'S', 0, |
| /* 23934 */ 'R', 'O', 'U', 'N', 'D', '_', 'W', '_', 'S', 0, |
| /* 23944 */ 'C', 'E', 'I', 'L', '_', 'W', '_', 'S', 0, |
| /* 23953 */ 'F', 'L', 'O', 'O', 'R', '_', 'W', '_', 'S', 0, |
| /* 23963 */ 'C', 'V', 'T', '_', 'W', '_', 'S', 0, |
| /* 23971 */ 'M', 'A', 'X', '_', 'S', 0, |
| /* 23977 */ 'S', 'E', 'L', 'N', 'E', 'Z', '_', 'S', 0, |
| /* 23986 */ 'S', 'E', 'L', 'E', 'Q', 'Z', '_', 'S', 0, |
| /* 23995 */ 'B', 'C', '1', 'T', 0, |
| /* 24000 */ 'G', '_', 'S', 'S', 'U', 'B', 'S', 'A', 'T', 0, |
| /* 24010 */ 'G', '_', 'U', 'S', 'U', 'B', 'S', 'A', 'T', 0, |
| /* 24020 */ 'G', '_', 'S', 'A', 'D', 'D', 'S', 'A', 'T', 0, |
| /* 24030 */ 'G', '_', 'U', 'A', 'D', 'D', 'S', 'A', 'T', 0, |
| /* 24040 */ 'G', '_', 'S', 'S', 'H', 'L', 'S', 'A', 'T', 0, |
| /* 24050 */ 'G', '_', 'U', 'S', 'H', 'L', 'S', 'A', 'T', 0, |
| /* 24060 */ 'G', '_', 'S', 'M', 'U', 'L', 'F', 'I', 'X', 'S', 'A', 'T', 0, |
| /* 24073 */ 'G', '_', 'U', 'M', 'U', 'L', 'F', 'I', 'X', 'S', 'A', 'T', 0, |
| /* 24086 */ 'G', '_', 'S', 'D', 'I', 'V', 'F', 'I', 'X', 'S', 'A', 'T', 0, |
| /* 24099 */ 'G', '_', 'U', 'D', 'I', 'V', 'F', 'I', 'X', 'S', 'A', 'T', 0, |
| /* 24112 */ 'G', '_', 'E', 'X', 'T', 'R', 'A', 'C', 'T', 0, |
| /* 24122 */ 'G', '_', 'S', 'E', 'L', 'E', 'C', 'T', 0, |
| /* 24131 */ 'G', '_', 'B', 'R', 'I', 'N', 'D', 'I', 'R', 'E', 'C', 'T', 0, |
| /* 24144 */ 'D', 'E', 'R', 'E', 'T', 0, |
| /* 24150 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'R', 'E', 'T', 0, |
| /* 24164 */ 'G', '_', 'M', 'E', 'M', 'S', 'E', 'T', 0, |
| /* 24173 */ 'B', 'G', 'T', 0, |
| /* 24177 */ 'W', 'A', 'I', 'T', 0, |
| /* 24182 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'F', 'U', 'N', 'C', 'T', 'I', 'O', 'N', '_', 'E', 'X', 'I', 'T', 0, |
| /* 24206 */ 'G', '_', 'B', 'R', 'J', 'T', 0, |
| /* 24213 */ 'B', 'L', 'T', 0, |
| /* 24217 */ 'G', '_', 'E', 'X', 'T', 'R', 'A', 'C', 'T', '_', 'V', 'E', 'C', 'T', 'O', 'R', '_', 'E', 'L', 'T', 0, |
| /* 24238 */ 'G', '_', 'I', 'N', 'S', 'E', 'R', 'T', '_', 'V', 'E', 'C', 'T', 'O', 'R', '_', 'E', 'L', 'T', 0, |
| /* 24258 */ 'S', 'L', 'T', 0, |
| /* 24262 */ 'T', 'L', 'T', 0, |
| /* 24266 */ 'P', 's', 'e', 'u', 'd', 'o', 'D', 'M', 'U', 'L', 'T', 0, |
| /* 24278 */ 'P', 's', 'e', 'u', 'd', 'o', 'M', 'U', 'L', 'T', 0, |
| /* 24289 */ 'D', 'M', 'T', 0, |
| /* 24293 */ 'E', 'M', 'T', 0, |
| /* 24297 */ 'G', '_', 'F', 'C', 'O', 'N', 'S', 'T', 'A', 'N', 'T', 0, |
| /* 24309 */ 'G', '_', 'C', 'O', 'N', 'S', 'T', 'A', 'N', 'T', 0, |
| /* 24320 */ 'S', 'T', 'A', 'T', 'E', 'P', 'O', 'I', 'N', 'T', 0, |
| /* 24331 */ 'P', 'A', 'T', 'C', 'H', 'P', 'O', 'I', 'N', 'T', 0, |
| /* 24342 */ 'G', '_', 'P', 'T', 'R', 'T', 'O', 'I', 'N', 'T', 0, |
| /* 24353 */ 'G', '_', 'F', 'R', 'I', 'N', 'T', 0, |
| /* 24361 */ 'G', '_', 'I', 'N', 'T', 'R', 'I', 'N', 'S', 'I', 'C', '_', 'L', 'R', 'I', 'N', 'T', 0, |
| /* 24379 */ 'G', '_', 'F', 'N', 'E', 'A', 'R', 'B', 'Y', 'I', 'N', 'T', 0, |
| /* 24392 */ 'G', '_', 'V', 'A', 'S', 'T', 'A', 'R', 'T', 0, |
| /* 24402 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0, |
| /* 24417 */ 'G', '_', 'I', 'N', 'V', 'O', 'K', 'E', '_', 'R', 'E', 'G', 'I', 'O', 'N', '_', 'S', 'T', 'A', 'R', 'T', 0, |
| /* 24439 */ 'G', '_', 'I', 'N', 'S', 'E', 'R', 'T', 0, |
| /* 24448 */ 'G', '_', 'F', 'S', 'Q', 'R', 'T', 0, |
| /* 24456 */ 'G', '_', 'S', 'T', 'R', 'I', 'C', 'T', '_', 'F', 'S', 'Q', 'R', 'T', 0, |
| /* 24471 */ 'G', '_', 'B', 'I', 'T', 'C', 'A', 'S', 'T', 0, |
| /* 24481 */ 'G', '_', 'A', 'D', 'D', 'R', 'S', 'P', 'A', 'C', 'E', '_', 'C', 'A', 'S', 'T', 0, |
| /* 24498 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', '_', 'L', 'I', 'S', 'T', 0, |
| /* 24513 */ 'G', 'I', 'N', 'V', 'T', 0, |
| /* 24519 */ 'D', 'E', 'X', 'T', 0, |
| /* 24524 */ 'G', '_', 'F', 'P', 'E', 'X', 'T', 0, |
| /* 24532 */ 'G', '_', 'S', 'E', 'X', 'T', 0, |
| /* 24539 */ 'G', '_', 'A', 'S', 'S', 'E', 'R', 'T', '_', 'S', 'E', 'X', 'T', 0, |
| /* 24553 */ 'G', '_', 'A', 'N', 'Y', 'E', 'X', 'T', 0, |
| /* 24562 */ 'G', '_', 'Z', 'E', 'X', 'T', 0, |
| /* 24569 */ 'G', '_', 'A', 'S', 'S', 'E', 'R', 'T', '_', 'Z', 'E', 'X', 'T', 0, |
| /* 24583 */ 'P', 's', 'e', 'u', 'd', 'o', 'M', 'S', 'U', 'B', 'U', 0, |
| /* 24595 */ 'P', 's', 'e', 'u', 'd', 'o', 'M', 'A', 'D', 'D', 'U', 0, |
| /* 24607 */ 'D', 'M', 'O', 'D', 'U', 0, |
| /* 24613 */ 'B', 'G', 'E', 'U', 0, |
| /* 24618 */ 'S', 'G', 'E', 'U', 0, |
| /* 24623 */ 'T', 'G', 'E', 'U', 0, |
| /* 24628 */ 'B', 'L', 'E', 'U', 0, |
| /* 24633 */ 'S', 'L', 'E', 'U', 0, |
| /* 24638 */ 'D', 'M', 'U', 'H', 'U', 0, |
| /* 24644 */ 'T', 'G', 'E', 'I', 'U', 0, |
| /* 24650 */ 'T', 'T', 'L', 'T', 'I', 'U', 0, |
| /* 24657 */ 'V', '3', 'M', 'U', 'L', 'U', 0, |
| /* 24664 */ 'D', 'M', 'U', 'L', 'U', 0, |
| /* 24670 */ 'V', 'M', 'U', 'L', 'U', 0, |
| /* 24676 */ 'D', 'I', 'N', 'S', 'U', 0, |
| /* 24682 */ 'B', 'G', 'T', 'U', 0, |
| /* 24687 */ 'B', 'L', 'T', 'U', 0, |
| /* 24692 */ 'T', 'L', 'T', 'U', 0, |
| /* 24697 */ 'D', 'E', 'X', 'T', 'U', 0, |
| /* 24703 */ 'D', 'D', 'I', 'V', 'U', 0, |
| /* 24709 */ 'D', 'S', 'R', 'A', 'V', 0, |
| /* 24715 */ 'B', 'I', 'T', 'R', 'E', 'V', 0, |
| /* 24722 */ 'D', 'D', 'I', 'V', 0, |
| /* 24727 */ 'G', '_', 'F', 'D', 'I', 'V', 0, |
| /* 24734 */ 'G', '_', 'S', 'T', 'R', 'I', 'C', 'T', '_', 'F', 'D', 'I', 'V', 0, |
| /* 24748 */ 'P', 's', 'e', 'u', 'd', 'o', 'D', 'S', 'D', 'I', 'V', 0, |
| /* 24760 */ 'G', '_', 'S', 'D', 'I', 'V', 0, |
| /* 24767 */ 'P', 's', 'e', 'u', 'd', 'o', 'S', 'D', 'I', 'V', 0, |
| /* 24778 */ 'P', 's', 'e', 'u', 'd', 'o', 'D', 'U', 'D', 'I', 'V', 0, |
| /* 24790 */ 'G', '_', 'U', 'D', 'I', 'V', 0, |
| /* 24797 */ 'P', 's', 'e', 'u', 'd', 'o', 'U', 'D', 'I', 'V', 0, |
| /* 24808 */ 'D', 'S', 'L', 'L', 'V', 0, |
| /* 24814 */ 'D', 'S', 'R', 'L', 'V', 0, |
| /* 24820 */ 'T', 'L', 'B', 'I', 'N', 'V', 0, |
| /* 24827 */ 'T', 'L', 'B', 'G', 'I', 'N', 'V', 0, |
| /* 24835 */ 'S', 'H', 'I', 'L', 'O', 'V', 0, |
| /* 24842 */ 'E', 'X', 'T', 'P', 'D', 'P', 'V', 0, |
| /* 24850 */ 'E', 'X', 'T', 'P', 'V', 0, |
| /* 24856 */ 'D', 'R', 'O', 'T', 'R', 'V', 0, |
| /* 24863 */ 'I', 'N', 'S', 'V', 0, |
| /* 24868 */ 'A', 'N', 'D', '_', 'V', 0, |
| /* 24874 */ 'M', 'O', 'V', 'E', '_', 'V', 0, |
| /* 24881 */ 'B', 'S', 'E', 'L', '_', 'V', 0, |
| /* 24888 */ 'N', 'O', 'R', '_', 'V', 0, |
| /* 24894 */ 'X', 'O', 'R', '_', 'V', 0, |
| /* 24900 */ 'B', 'Z', '_', 'V', 0, |
| /* 24905 */ 'B', 'M', 'Z', '_', 'V', 0, |
| /* 24911 */ 'B', 'N', 'Z', '_', 'V', 0, |
| /* 24917 */ 'B', 'M', 'N', 'Z', '_', 'V', 0, |
| /* 24924 */ 'C', 'R', 'C', '3', '2', 'W', 0, |
| /* 24931 */ 'C', 'R', 'C', '3', '2', 'C', 'W', 0, |
| /* 24939 */ 'L', 'W', 0, |
| /* 24942 */ 'G', '_', 'F', 'P', 'O', 'W', 0, |
| /* 24949 */ 'S', 'W', 0, |
| /* 24952 */ 'P', 's', 'e', 'u', 'd', 'o', 'C', 'V', 'T', '_', 'D', '3', '2', '_', 'W', 0, |
| /* 24968 */ 'F', 'L', 'O', 'G', '2', '_', 'W', 0, |
| /* 24976 */ 'F', 'E', 'X', 'P', '2', '_', 'W', 0, |
| /* 24984 */ 'P', 's', 'e', 'u', 'd', 'o', 'C', 'V', 'T', '_', 'D', '6', '4', '_', 'W', 0, |
| /* 25000 */ 'S', 'R', 'A', '_', 'W', 0, |
| /* 25006 */ 'A', 'D', 'D', '_', 'A', '_', 'W', 0, |
| /* 25014 */ 'F', 'M', 'I', 'N', '_', 'A', '_', 'W', 0, |
| /* 25023 */ 'A', 'D', 'D', 'S', '_', 'A', '_', 'W', 0, |
| /* 25032 */ 'F', 'M', 'A', 'X', '_', 'A', '_', 'W', 0, |
| /* 25041 */ 'F', 'S', 'U', 'B', '_', 'W', 0, |
| /* 25048 */ 'F', 'M', 'S', 'U', 'B', '_', 'W', 0, |
| /* 25056 */ 'N', 'L', 'O', 'C', '_', 'W', 0, |
| /* 25063 */ 'N', 'L', 'Z', 'C', '_', 'W', 0, |
| /* 25070 */ 'F', 'A', 'D', 'D', '_', 'W', 0, |
| /* 25077 */ 'F', 'M', 'A', 'D', 'D', '_', 'W', 0, |
| /* 25085 */ 'S', 'L', 'D', '_', 'W', 0, |
| /* 25091 */ 'P', 'C', 'K', 'O', 'D', '_', 'W', 0, |
| /* 25099 */ 'I', 'L', 'V', 'O', 'D', '_', 'W', 0, |
| /* 25107 */ 'F', 'C', 'L', 'E', '_', 'W', 0, |
| /* 25114 */ 'F', 'S', 'L', 'E', '_', 'W', 0, |
| /* 25121 */ 'F', 'C', 'U', 'L', 'E', '_', 'W', 0, |
| /* 25129 */ 'F', 'S', 'U', 'L', 'E', '_', 'W', 0, |
| /* 25137 */ 'F', 'C', 'N', 'E', '_', 'W', 0, |
| /* 25144 */ 'F', 'S', 'N', 'E', '_', 'W', 0, |
| /* 25151 */ 'F', 'C', 'U', 'N', 'E', '_', 'W', 0, |
| /* 25159 */ 'F', 'S', 'U', 'N', 'E', '_', 'W', 0, |
| /* 25167 */ 'I', 'N', 'S', 'V', 'E', '_', 'W', 0, |
| /* 25175 */ 'F', 'C', 'A', 'F', '_', 'W', 0, |
| /* 25182 */ 'F', 'S', 'A', 'F', '_', 'W', 0, |
| /* 25189 */ 'V', 'S', 'H', 'F', '_', 'W', 0, |
| /* 25196 */ 'B', 'N', 'E', 'G', '_', 'W', 0, |
| /* 25203 */ 'P', 'R', 'E', 'C', 'R', '_', 'S', 'R', 'A', '_', 'P', 'H', '_', 'W', 0, |
| /* 25218 */ 'P', 'R', 'E', 'C', 'R', 'Q', '_', 'P', 'H', '_', 'W', 0, |
| /* 25230 */ 'P', 'R', 'E', 'C', 'R', '_', 'S', 'R', 'A', '_', 'R', '_', 'P', 'H', '_', 'W', 0, |
| /* 25247 */ 'P', 'R', 'E', 'C', 'R', 'Q', '_', 'R', 'S', '_', 'P', 'H', '_', 'W', 0, |
| /* 25262 */ 'S', 'U', 'B', 'Q', 'H', '_', 'W', 0, |
| /* 25270 */ 'A', 'D', 'D', 'Q', 'H', '_', 'W', 0, |
| /* 25278 */ 'S', 'R', 'A', 'I', '_', 'W', 0, |
| /* 25285 */ 'S', 'L', 'D', 'I', '_', 'W', 0, |
| /* 25292 */ 'B', 'N', 'E', 'G', 'I', '_', 'W', 0, |
| /* 25300 */ 'S', 'L', 'L', 'I', '_', 'W', 0, |
| /* 25307 */ 'S', 'R', 'L', 'I', '_', 'W', 0, |
| /* 25314 */ 'B', 'I', 'N', 'S', 'L', 'I', '_', 'W', 0, |
| /* 25323 */ 'C', 'E', 'Q', 'I', '_', 'W', 0, |
| /* 25330 */ 'S', 'R', 'A', 'R', 'I', '_', 'W', 0, |
| /* 25338 */ 'B', 'C', 'L', 'R', 'I', '_', 'W', 0, |
| /* 25346 */ 'S', 'R', 'L', 'R', 'I', '_', 'W', 0, |
| /* 25354 */ 'B', 'I', 'N', 'S', 'R', 'I', '_', 'W', 0, |
| /* 25363 */ 'S', 'P', 'L', 'A', 'T', 'I', '_', 'W', 0, |
| /* 25372 */ 'B', 'S', 'E', 'T', 'I', '_', 'W', 0, |
| /* 25380 */ 'S', 'U', 'B', 'V', 'I', '_', 'W', 0, |
| /* 25388 */ 'A', 'D', 'D', 'V', 'I', '_', 'W', 0, |
| /* 25396 */ 'F', 'I', 'L', 'L', '_', 'W', 0, |
| /* 25403 */ 'S', 'L', 'L', '_', 'W', 0, |
| /* 25409 */ 'F', 'E', 'X', 'U', 'P', 'L', '_', 'W', 0, |
| /* 25418 */ 'F', 'F', 'Q', 'L', '_', 'W', 0, |
| /* 25425 */ 'S', 'R', 'L', '_', 'W', 0, |
| /* 25431 */ 'B', 'I', 'N', 'S', 'L', '_', 'W', 0, |
| /* 25439 */ 'F', 'M', 'U', 'L', '_', 'W', 0, |
| /* 25446 */ 'I', 'L', 'V', 'L', '_', 'W', 0, |
| /* 25453 */ 'D', 'P', 'A', 'Q', '_', 'S', 'A', '_', 'L', '_', 'W', 0, |
| /* 25465 */ 'D', 'P', 'S', 'Q', '_', 'S', 'A', '_', 'L', '_', 'W', 0, |
| /* 25477 */ 'F', 'M', 'I', 'N', '_', 'W', 0, |
| /* 25484 */ 'F', 'C', 'U', 'N', '_', 'W', 0, |
| /* 25491 */ 'F', 'S', 'U', 'N', '_', 'W', 0, |
| /* 25498 */ 'F', 'E', 'X', 'D', 'O', '_', 'W', 0, |
| /* 25506 */ 'F', 'R', 'C', 'P', '_', 'W', 0, |
| /* 25513 */ 'F', 'C', 'E', 'Q', '_', 'W', 0, |
| /* 25520 */ 'F', 'S', 'E', 'Q', '_', 'W', 0, |
| /* 25527 */ 'F', 'C', 'U', 'E', 'Q', '_', 'W', 0, |
| /* 25535 */ 'F', 'S', 'U', 'E', 'Q', '_', 'W', 0, |
| /* 25543 */ 'F', 'T', 'Q', '_', 'W', 0, |
| /* 25549 */ 'M', 'S', 'U', 'B', '_', 'Q', '_', 'W', 0, |
| /* 25558 */ 'M', 'A', 'D', 'D', '_', 'Q', '_', 'W', 0, |
| /* 25567 */ 'M', 'U', 'L', '_', 'Q', '_', 'W', 0, |
| /* 25575 */ 'M', 'S', 'U', 'B', 'R', '_', 'Q', '_', 'W', 0, |
| /* 25585 */ 'M', 'A', 'D', 'D', 'R', '_', 'Q', '_', 'W', 0, |
| /* 25595 */ 'M', 'U', 'L', 'R', '_', 'Q', '_', 'W', 0, |
| /* 25604 */ 'S', 'R', 'A', 'R', '_', 'W', 0, |
| /* 25611 */ 'L', 'D', 'R', '_', 'W', 0, |
| /* 25617 */ 'B', 'C', 'L', 'R', '_', 'W', 0, |
| /* 25624 */ 'S', 'R', 'L', 'R', '_', 'W', 0, |
| /* 25631 */ 'F', 'C', 'O', 'R', '_', 'W', 0, |
| /* 25638 */ 'F', 'S', 'O', 'R', '_', 'W', 0, |
| /* 25645 */ 'F', 'E', 'X', 'U', 'P', 'R', '_', 'W', 0, |
| /* 25654 */ 'F', 'F', 'Q', 'R', '_', 'W', 0, |
| /* 25661 */ 'B', 'I', 'N', 'S', 'R', '_', 'W', 0, |
| /* 25669 */ 'S', 'T', 'R', '_', 'W', 0, |
| /* 25675 */ 'E', 'X', 'T', 'R', '_', 'W', 0, |
| /* 25682 */ 'I', 'L', 'V', 'R', '_', 'W', 0, |
| /* 25689 */ 'S', 'H', 'R', 'A', '_', 'R', '_', 'W', 0, |
| /* 25698 */ 'S', 'U', 'B', 'Q', 'H', '_', 'R', '_', 'W', 0, |
| /* 25708 */ 'A', 'D', 'D', 'Q', 'H', '_', 'R', '_', 'W', 0, |
| /* 25718 */ 'E', 'X', 'T', 'R', '_', 'R', '_', 'W', 0, |
| /* 25727 */ 'S', 'H', 'R', 'A', 'V', '_', 'R', '_', 'W', 0, |
| /* 25737 */ 'E', 'X', 'T', 'R', 'V', '_', 'R', '_', 'W', 0, |
| /* 25747 */ 'F', 'A', 'B', 'S', '_', 'W', 0, |
| /* 25754 */ 'M', 'U', 'L', 'Q', '_', 'R', 'S', '_', 'W', 0, |
| /* 25764 */ 'E', 'X', 'T', 'R', '_', 'R', 'S', '_', 'W', 0, |
| /* 25774 */ 'E', 'X', 'T', 'R', 'V', '_', 'R', 'S', '_', 'W', 0, |
| /* 25785 */ 'F', 'C', 'L', 'A', 'S', 'S', '_', 'W', 0, |
| /* 25794 */ 'A', 'S', 'U', 'B', '_', 'S', '_', 'W', 0, |
| /* 25803 */ 'H', 'S', 'U', 'B', '_', 'S', '_', 'W', 0, |
| /* 25812 */ 'D', 'P', 'S', 'U', 'B', '_', 'S', '_', 'W', 0, |
| /* 25822 */ 'F', 'T', 'R', 'U', 'N', 'C', '_', 'S', '_', 'W', 0, |
| /* 25833 */ 'H', 'A', 'D', 'D', '_', 'S', '_', 'W', 0, |
| /* 25842 */ 'D', 'P', 'A', 'D', 'D', '_', 'S', '_', 'W', 0, |
| /* 25852 */ 'M', 'O', 'D', '_', 'S', '_', 'W', 0, |
| /* 25860 */ 'C', 'L', 'E', '_', 'S', '_', 'W', 0, |
| /* 25868 */ 'A', 'V', 'E', '_', 'S', '_', 'W', 0, |
| /* 25876 */ 'C', 'L', 'E', 'I', '_', 'S', '_', 'W', 0, |
| /* 25885 */ 'M', 'I', 'N', 'I', '_', 'S', '_', 'W', 0, |
| /* 25894 */ 'C', 'L', 'T', 'I', '_', 'S', '_', 'W', 0, |
| /* 25903 */ 'M', 'A', 'X', 'I', '_', 'S', '_', 'W', 0, |
| /* 25912 */ 'S', 'H', 'L', 'L', '_', 'S', '_', 'W', 0, |
| /* 25921 */ 'M', 'I', 'N', '_', 'S', '_', 'W', 0, |
| /* 25929 */ 'D', 'O', 'T', 'P', '_', 'S', '_', 'W', 0, |
| /* 25938 */ 'S', 'U', 'B', 'Q', '_', 'S', '_', 'W', 0, |
| /* 25947 */ 'A', 'D', 'D', 'Q', '_', 'S', '_', 'W', 0, |
| /* 25956 */ 'M', 'U', 'L', 'Q', '_', 'S', '_', 'W', 0, |
| /* 25965 */ 'A', 'B', 'S', 'Q', '_', 'S', '_', 'W', 0, |
| /* 25974 */ 'A', 'V', 'E', 'R', '_', 'S', '_', 'W', 0, |
| /* 25983 */ 'S', 'U', 'B', 'S', '_', 'S', '_', 'W', 0, |
| /* 25992 */ 'A', 'D', 'D', 'S', '_', 'S', '_', 'W', 0, |
| /* 26001 */ 'S', 'A', 'T', '_', 'S', '_', 'W', 0, |
| /* 26009 */ 'C', 'L', 'T', '_', 'S', '_', 'W', 0, |
| /* 26017 */ 'F', 'F', 'I', 'N', 'T', '_', 'S', '_', 'W', 0, |
| /* 26027 */ 'F', 'T', 'I', 'N', 'T', '_', 'S', '_', 'W', 0, |
| /* 26037 */ 'P', 's', 'e', 'u', 'd', 'o', 'C', 'V', 'T', '_', 'S', '_', 'W', 0, |
| /* 26051 */ 'S', 'U', 'B', 'S', 'U', 'U', '_', 'S', '_', 'W', 0, |
| /* 26062 */ 'D', 'I', 'V', '_', 'S', '_', 'W', 0, |
| /* 26070 */ 'S', 'H', 'L', 'L', 'V', '_', 'S', '_', 'W', 0, |
| /* 26080 */ 'M', 'A', 'X', '_', 'S', '_', 'W', 0, |
| /* 26088 */ 'C', 'O', 'P', 'Y', '_', 'S', '_', 'W', 0, |
| /* 26097 */ 'S', 'P', 'L', 'A', 'T', '_', 'W', 0, |
| /* 26105 */ 'B', 'S', 'E', 'T', '_', 'W', 0, |
| /* 26112 */ 'F', 'C', 'L', 'T', '_', 'W', 0, |
| /* 26119 */ 'F', 'S', 'L', 'T', '_', 'W', 0, |
| /* 26126 */ 'F', 'C', 'U', 'L', 'T', '_', 'W', 0, |
| /* 26134 */ 'F', 'S', 'U', 'L', 'T', '_', 'W', 0, |
| /* 26142 */ 'P', 'C', 'N', 'T', '_', 'W', 0, |
| /* 26149 */ 'F', 'R', 'I', 'N', 'T', '_', 'W', 0, |
| /* 26157 */ 'I', 'N', 'S', 'E', 'R', 'T', '_', 'W', 0, |
| /* 26166 */ 'F', 'S', 'Q', 'R', 'T', '_', 'W', 0, |
| /* 26174 */ 'F', 'R', 'S', 'Q', 'R', 'T', '_', 'W', 0, |
| /* 26183 */ 'S', 'T', '_', 'W', 0, |
| /* 26188 */ 'A', 'S', 'U', 'B', '_', 'U', '_', 'W', 0, |
| /* 26197 */ 'H', 'S', 'U', 'B', '_', 'U', '_', 'W', 0, |
| /* 26206 */ 'D', 'P', 'S', 'U', 'B', '_', 'U', '_', 'W', 0, |
| /* 26216 */ 'F', 'T', 'R', 'U', 'N', 'C', '_', 'U', '_', 'W', 0, |
| /* 26227 */ 'H', 'A', 'D', 'D', '_', 'U', '_', 'W', 0, |
| /* 26236 */ 'D', 'P', 'A', 'D', 'D', '_', 'U', '_', 'W', 0, |
| /* 26246 */ 'M', 'O', 'D', '_', 'U', '_', 'W', 0, |
| /* 26254 */ 'C', 'L', 'E', '_', 'U', '_', 'W', 0, |
| /* 26262 */ 'A', 'V', 'E', '_', 'U', '_', 'W', 0, |
| /* 26270 */ 'C', 'L', 'E', 'I', '_', 'U', '_', 'W', 0, |
| /* 26279 */ 'M', 'I', 'N', 'I', '_', 'U', '_', 'W', 0, |
| /* 26288 */ 'C', 'L', 'T', 'I', '_', 'U', '_', 'W', 0, |
| /* 26297 */ 'M', 'A', 'X', 'I', '_', 'U', '_', 'W', 0, |
| /* 26306 */ 'M', 'I', 'N', '_', 'U', '_', 'W', 0, |
| /* 26314 */ 'D', 'O', 'T', 'P', '_', 'U', '_', 'W', 0, |
| /* 26323 */ 'A', 'V', 'E', 'R', '_', 'U', '_', 'W', 0, |
| /* 26332 */ 'S', 'U', 'B', 'S', '_', 'U', '_', 'W', 0, |
| /* 26341 */ 'A', 'D', 'D', 'S', '_', 'U', '_', 'W', 0, |
| /* 26350 */ 'S', 'U', 'B', 'S', 'U', 'S', '_', 'U', '_', 'W', 0, |
| /* 26361 */ 'S', 'A', 'T', '_', 'U', '_', 'W', 0, |
| /* 26369 */ 'C', 'L', 'T', '_', 'U', '_', 'W', 0, |
| /* 26377 */ 'F', 'F', 'I', 'N', 'T', '_', 'U', '_', 'W', 0, |
| /* 26387 */ 'F', 'T', 'I', 'N', 'T', '_', 'U', '_', 'W', 0, |
| /* 26397 */ 'D', 'I', 'V', '_', 'U', '_', 'W', 0, |
| /* 26405 */ 'M', 'A', 'X', '_', 'U', '_', 'W', 0, |
| /* 26413 */ 'C', 'O', 'P', 'Y', '_', 'U', '_', 'W', 0, |
| /* 26422 */ 'M', 'S', 'U', 'B', 'V', '_', 'W', 0, |
| /* 26430 */ 'M', 'A', 'D', 'D', 'V', '_', 'W', 0, |
| /* 26438 */ 'P', 'C', 'K', 'E', 'V', '_', 'W', 0, |
| /* 26446 */ 'I', 'L', 'V', 'E', 'V', '_', 'W', 0, |
| /* 26454 */ 'F', 'D', 'I', 'V', '_', 'W', 0, |
| /* 26461 */ 'M', 'U', 'L', 'V', '_', 'W', 0, |
| /* 26468 */ 'E', 'X', 'T', 'R', 'V', '_', 'W', 0, |
| /* 26476 */ 'F', 'M', 'A', 'X', '_', 'W', 0, |
| /* 26483 */ 'B', 'Z', '_', 'W', 0, |
| /* 26488 */ 'B', 'N', 'Z', '_', 'W', 0, |
| /* 26494 */ 'G', '_', 'V', 'E', 'C', 'R', 'E', 'D', 'U', 'C', 'E', '_', 'F', 'M', 'A', 'X', 0, |
| /* 26511 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'F', 'M', 'A', 'X', 0, |
| /* 26528 */ 'G', '_', 'V', 'E', 'C', 'R', 'E', 'D', 'U', 'C', 'E', '_', 'S', 'M', 'A', 'X', 0, |
| /* 26545 */ 'G', '_', 'S', 'M', 'A', 'X', 0, |
| /* 26552 */ 'G', '_', 'V', 'E', 'C', 'R', 'E', 'D', 'U', 'C', 'E', '_', 'U', 'M', 'A', 'X', 0, |
| /* 26569 */ 'G', '_', 'U', 'M', 'A', 'X', 0, |
| /* 26576 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'U', 'M', 'A', 'X', 0, |
| /* 26593 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'M', 'A', 'X', 0, |
| /* 26609 */ 'M', 'F', 'T', 'A', 'C', 'X', 0, |
| /* 26616 */ 'M', 'T', 'T', 'A', 'C', 'X', 0, |
| /* 26623 */ 'G', '_', 'F', 'R', 'A', 'M', 'E', '_', 'I', 'N', 'D', 'E', 'X', 0, |
| /* 26637 */ 'G', '_', 'S', 'B', 'F', 'X', 0, |
| /* 26644 */ 'G', '_', 'U', 'B', 'F', 'X', 0, |
| /* 26651 */ 'L', 'H', 'X', 0, |
| /* 26655 */ 'G', '_', 'S', 'M', 'U', 'L', 'F', 'I', 'X', 0, |
| /* 26665 */ 'G', '_', 'U', 'M', 'U', 'L', 'F', 'I', 'X', 0, |
| /* 26675 */ 'G', '_', 'S', 'D', 'I', 'V', 'F', 'I', 'X', 0, |
| /* 26685 */ 'G', '_', 'U', 'D', 'I', 'V', 'F', 'I', 'X', 0, |
| /* 26695 */ 'J', 'A', 'L', 'X', 0, |
| /* 26700 */ 'L', 'B', 'U', 'X', 0, |
| /* 26705 */ 'L', 'W', 'X', 0, |
| /* 26709 */ 'G', '_', 'M', 'E', 'M', 'C', 'P', 'Y', 0, |
| /* 26718 */ 'C', 'O', 'P', 'Y', 0, |
| /* 26723 */ 'C', 'O', 'N', 'S', 'T', 'P', 'O', 'O', 'L', '_', 'E', 'N', 'T', 'R', 'Y', 0, |
| /* 26739 */ 'B', 'G', 'E', 'Z', 0, |
| /* 26744 */ 'B', 'L', 'E', 'Z', 0, |
| /* 26749 */ 'B', 'C', '1', 'N', 'E', 'Z', 0, |
| /* 26756 */ 'B', 'C', '2', 'N', 'E', 'Z', 0, |
| /* 26763 */ 'S', 'E', 'L', 'N', 'E', 'Z', 0, |
| /* 26770 */ 'D', 'C', 'L', 'Z', 0, |
| /* 26775 */ 'G', '_', 'C', 'T', 'L', 'Z', 0, |
| /* 26782 */ 'B', 'C', '1', 'E', 'Q', 'Z', 0, |
| /* 26789 */ 'B', 'C', '2', 'E', 'Q', 'Z', 0, |
| /* 26796 */ 'S', 'E', 'L', 'E', 'Q', 'Z', 0, |
| /* 26803 */ 'B', 'G', 'T', 'Z', 0, |
| /* 26808 */ 'B', 'L', 'T', 'Z', 0, |
| /* 26813 */ 'G', '_', 'C', 'T', 'T', 'Z', 0, |
| /* 26820 */ 'S', 'e', 'l', 'B', 'n', 'e', 'Z', 0, |
| /* 26828 */ 'S', 'e', 'l', 'B', 'e', 'q', 'Z', 0, |
| /* 26836 */ 'J', 'a', 'l', 'O', 'n', 'e', 'R', 'e', 'g', 0, |
| /* 26846 */ 'J', 'a', 'l', 'T', 'w', 'o', 'R', 'e', 'g', 0, |
| /* 26856 */ 'P', 's', 'e', 'u', 'd', 'o', 'I', 'n', 'd', 'i', 'r', 'e', 'c', 't', 'H', 'a', 'z', 'a', 'r', 'd', 'B', 'r', 'a', 'n', 'c', 'h', 0, |
| /* 26883 */ 'P', 's', 'e', 'u', 'd', 'o', 'I', 'n', 'd', 'i', 'r', 'e', 'c', 't', 'B', 'r', 'a', 'n', 'c', 'h', 0, |
| /* 26904 */ 'U', 'l', 'h', 0, |
| /* 26908 */ 'U', 's', 'h', 0, |
| /* 26912 */ 'D', 'A', 'D', 'D', 'i', 0, |
| /* 26918 */ 'A', 'N', 'D', 'i', 0, |
| /* 26923 */ 'S', 'N', 'E', 'i', 0, |
| /* 26928 */ 'S', 'E', 'Q', 'i', 0, |
| /* 26933 */ 'X', 'O', 'R', 'i', 0, |
| /* 26938 */ 'S', 'L', 'T', 'i', 0, |
| /* 26943 */ 'L', 'O', 'N', 'G', '_', 'B', 'R', 'A', 'N', 'C', 'H', '_', 'L', 'U', 'i', 0, |
| /* 26959 */ 'S', 'e', 'l', 'T', 'B', 't', 'n', 'e', 'Z', 'C', 'm', 'p', 'i', 0, |
| /* 26973 */ 'S', 'e', 'l', 'T', 'B', 't', 'e', 'q', 'Z', 'C', 'm', 'p', 'i', 0, |
| /* 26987 */ 'S', 'e', 'l', 'T', 'B', 't', 'n', 'e', 'Z', 'S', 'l', 't', 'i', 0, |
| /* 27001 */ 'S', 'e', 'l', 'T', 'B', 't', 'e', 'q', 'Z', 'S', 'l', 't', 'i', 0, |
| /* 27015 */ 'S', 'G', 'E', 'I', 'm', 'm', 0, |
| /* 27022 */ 'S', 'L', 'E', 'I', 'm', 'm', 0, |
| /* 27029 */ 'D', 'R', 'O', 'L', 'I', 'm', 'm', 0, |
| /* 27037 */ 'N', 'O', 'R', 'I', 'm', 'm', 0, |
| /* 27044 */ 'D', 'R', 'O', 'R', 'I', 'm', 'm', 0, |
| /* 27052 */ 'S', 'G', 'T', 'I', 'm', 'm', 0, |
| /* 27059 */ 'S', 'G', 'E', 'U', 'I', 'm', 'm', 0, |
| /* 27067 */ 'S', 'L', 'E', 'U', 'I', 'm', 'm', 0, |
| /* 27075 */ 'S', 'G', 'T', 'U', 'I', 'm', 'm', 0, |
| /* 27083 */ 'B', 'n', 'e', 'I', 'm', 'm', 0, |
| /* 27090 */ 'B', 'e', 'q', 'I', 'm', 'm', 0, |
| /* 27097 */ 'P', 's', 'e', 'u', 'd', 'o', 'R', 'e', 't', 'u', 'r', 'n', 0, |
| /* 27110 */ 'J', 'A', 'L', 'R', 'H', 'B', '6', '4', 'P', 's', 'e', 'u', 'd', 'o', 0, |
| /* 27125 */ 'J', 'A', 'L', 'R', '6', '4', 'P', 's', 'e', 'u', 'd', 'o', 0, |
| /* 27138 */ 'J', 'A', 'L', 'R', 'H', 'B', 'P', 's', 'e', 'u', 'd', 'o', 0, |
| /* 27151 */ 'J', 'A', 'L', 'R', 'P', 's', 'e', 'u', 'd', 'o', 0, |
| /* 27162 */ 'B', '_', 'M', 'M', 'R', '6', '_', 'P', 's', 'e', 'u', 'd', 'o', 0, |
| /* 27176 */ 'B', '_', 'M', 'M', '_', 'P', 's', 'e', 'u', 'd', 'o', 0, |
| /* 27188 */ 'S', 'D', 'I', 'V', '_', 'M', 'M', '_', 'P', 's', 'e', 'u', 'd', 'o', 0, |
| /* 27203 */ 'U', 'D', 'I', 'V', '_', 'M', 'M', '_', 'P', 's', 'e', 'u', 'd', 'o', 0, |
| /* 27218 */ 'L', 'D', 'M', 'a', 'c', 'r', 'o', 0, |
| /* 27226 */ 'S', 'D', 'M', 'a', 'c', 'r', 'o', 0, |
| /* 27234 */ 'S', 'N', 'E', 'M', 'a', 'c', 'r', 'o', 0, |
| /* 27243 */ 'S', 'N', 'E', 'I', 'M', 'a', 'c', 'r', 'o', 0, |
| /* 27253 */ 'S', 'E', 'Q', 'I', 'M', 'a', 'c', 'r', 'o', 0, |
| /* 27263 */ 'D', 'S', 'R', 'e', 'm', 'I', 'M', 'a', 'c', 'r', 'o', 0, |
| /* 27275 */ 'D', 'U', 'R', 'e', 'm', 'I', 'M', 'a', 'c', 'r', 'o', 0, |
| /* 27287 */ 'D', 'S', 'D', 'i', 'v', 'I', 'M', 'a', 'c', 'r', 'o', 0, |
| /* 27299 */ 'D', 'U', 'D', 'i', 'v', 'I', 'M', 'a', 'c', 'r', 'o', 0, |
| /* 27311 */ 'D', 'M', 'U', 'L', 'M', 'a', 'c', 'r', 'o', 0, |
| /* 27321 */ 'D', 'M', 'U', 'L', 'O', 'M', 'a', 'c', 'r', 'o', 0, |
| /* 27332 */ 'S', 'E', 'Q', 'M', 'a', 'c', 'r', 'o', 0, |
| /* 27341 */ 'A', 'B', 'S', 'M', 'a', 'c', 'r', 'o', 0, |
| /* 27350 */ 'D', 'M', 'U', 'L', 'O', 'U', 'M', 'a', 'c', 'r', 'o', 0, |
| /* 27362 */ 'D', 'S', 'R', 'e', 'm', 'M', 'a', 'c', 'r', 'o', 0, |
| /* 27373 */ 'D', 'U', 'R', 'e', 'm', 'M', 'a', 'c', 'r', 'o', 0, |
| /* 27384 */ 'B', 'G', 'E', 'I', 'm', 'm', 'M', 'a', 'c', 'r', 'o', 0, |
| /* 27396 */ 'B', 'L', 'E', 'I', 'm', 'm', 'M', 'a', 'c', 'r', 'o', 0, |
| /* 27408 */ 'B', 'G', 'E', 'L', 'I', 'm', 'm', 'M', 'a', 'c', 'r', 'o', 0, |
| /* 27421 */ 'B', 'L', 'E', 'L', 'I', 'm', 'm', 'M', 'a', 'c', 'r', 'o', 0, |
| /* 27434 */ 'B', 'N', 'E', 'L', 'I', 'm', 'm', 'M', 'a', 'c', 'r', 'o', 0, |
| /* 27447 */ 'B', 'E', 'Q', 'L', 'I', 'm', 'm', 'M', 'a', 'c', 'r', 'o', 0, |
| /* 27460 */ 'B', 'G', 'T', 'L', 'I', 'm', 'm', 'M', 'a', 'c', 'r', 'o', 0, |
| /* 27473 */ 'B', 'L', 'T', 'L', 'I', 'm', 'm', 'M', 'a', 'c', 'r', 'o', 0, |
| /* 27486 */ 'B', 'G', 'E', 'U', 'L', 'I', 'm', 'm', 'M', 'a', 'c', 'r', 'o', 0, |
| /* 27500 */ 'B', 'L', 'E', 'U', 'L', 'I', 'm', 'm', 'M', 'a', 'c', 'r', 'o', 0, |
| /* 27514 */ 'D', 'M', 'U', 'L', 'I', 'm', 'm', 'M', 'a', 'c', 'r', 'o', 0, |
| /* 27527 */ 'B', 'G', 'T', 'U', 'L', 'I', 'm', 'm', 'M', 'a', 'c', 'r', 'o', 0, |
| /* 27541 */ 'B', 'L', 'T', 'U', 'L', 'I', 'm', 'm', 'M', 'a', 'c', 'r', 'o', 0, |
| /* 27555 */ 'B', 'G', 'T', 'I', 'm', 'm', 'M', 'a', 'c', 'r', 'o', 0, |
| /* 27567 */ 'B', 'L', 'T', 'I', 'm', 'm', 'M', 'a', 'c', 'r', 'o', 0, |
| /* 27579 */ 'B', 'G', 'E', 'U', 'I', 'm', 'm', 'M', 'a', 'c', 'r', 'o', 0, |
| /* 27592 */ 'B', 'L', 'E', 'U', 'I', 'm', 'm', 'M', 'a', 'c', 'r', 'o', 0, |
| /* 27605 */ 'B', 'G', 'T', 'U', 'I', 'm', 'm', 'M', 'a', 'c', 'r', 'o', 0, |
| /* 27618 */ 'B', 'L', 'T', 'U', 'I', 'm', 'm', 'M', 'a', 'c', 'r', 'o', 0, |
| /* 27631 */ 'D', 'S', 'D', 'i', 'v', 'M', 'a', 'c', 'r', 'o', 0, |
| /* 27642 */ 'D', 'U', 'D', 'i', 'v', 'M', 'a', 'c', 'r', 'o', 0, |
| /* 27653 */ 'L', 'O', 'N', 'G', '_', 'B', 'R', 'A', 'N', 'C', 'H', '_', 'L', 'U', 'i', '2', 'O', 'p', 0, |
| /* 27672 */ 'L', 'O', 'N', 'G', '_', 'B', 'R', 'A', 'N', 'C', 'H', '_', 'D', 'A', 'D', 'D', 'i', 'u', '2', 'O', 'p', 0, |
| /* 27694 */ 'L', 'O', 'N', 'G', '_', 'B', 'R', 'A', 'N', 'C', 'H', '_', 'A', 'D', 'D', 'i', 'u', '2', 'O', 'p', 0, |
| /* 27715 */ 'S', 'e', 'l', 'T', 'B', 't', 'n', 'e', 'Z', 'C', 'm', 'p', 0, |
| /* 27728 */ 'S', 'e', 'l', 'T', 'B', 't', 'e', 'q', 'Z', 'C', 'm', 'p', 0, |
| /* 27741 */ 'S', 'a', 'a', 'A', 'd', 'd', 'r', 0, |
| /* 27749 */ 'S', 'a', 'a', 'd', 'A', 'd', 'd', 'r', 0, |
| /* 27758 */ 'E', 'R', 'e', 't', 0, |
| /* 27763 */ 'S', 'e', 'l', 'T', 'B', 't', 'n', 'e', 'Z', 'S', 'l', 't', 0, |
| /* 27776 */ 'S', 'e', 'l', 'T', 'B', 't', 'e', 'q', 'Z', 'S', 'l', 't', 0, |
| /* 27789 */ 'L', 'B', 'u', 0, |
| /* 27793 */ 'D', 'S', 'U', 'B', 'u', 0, |
| /* 27799 */ 'B', 'A', 'D', 'D', 'u', 0, |
| /* 27805 */ 'D', 'A', 'D', 'D', 'u', 0, |
| /* 27811 */ 'L', 'H', 'u', 0, |
| /* 27815 */ 'S', 'L', 'T', 'u', 0, |
| /* 27820 */ 'P', 's', 'e', 'u', 'd', 'o', 'D', 'M', 'U', 'L', 'T', 'u', 0, |
| /* 27833 */ 'P', 's', 'e', 'u', 'd', 'o', 'M', 'U', 'L', 'T', 'u', 0, |
| /* 27845 */ 'L', 'W', 'u', 0, |
| /* 27849 */ 'U', 'l', 'h', 'u', 0, |
| /* 27854 */ 'L', 'O', 'N', 'G', '_', 'B', 'R', 'A', 'N', 'C', 'H', '_', 'D', 'A', 'D', 'D', 'i', 'u', 0, |
| /* 27873 */ 'L', 'E', 'A', '_', 'A', 'D', 'D', 'i', 'u', 0, |
| /* 27883 */ 'L', 'O', 'N', 'G', '_', 'B', 'R', 'A', 'N', 'C', 'H', '_', 'A', 'D', 'D', 'i', 'u', 0, |
| /* 27901 */ 'S', 'L', 'T', 'i', 'u', 0, |
| /* 27907 */ 'S', 'e', 'l', 'T', 'B', 't', 'n', 'e', 'Z', 'S', 'l', 't', 'i', 'u', 0, |
| /* 27922 */ 'S', 'e', 'l', 'T', 'B', 't', 'e', 'q', 'Z', 'S', 'l', 't', 'i', 'u', 0, |
| /* 27937 */ 'S', 'e', 'l', 'T', 'B', 't', 'n', 'e', 'Z', 'S', 'l', 't', 'u', 0, |
| /* 27951 */ 'S', 'e', 'l', 'T', 'B', 't', 'e', 'q', 'Z', 'S', 'l', 't', 'u', 0, |
| /* 27965 */ 'U', 'l', 'w', 0, |
| /* 27969 */ 'U', 's', 'w', 0, |
| 0 |
| }; |
| |
| extern const unsigned MipsInstrNameIndices[] = { |
| 15358U, 20887U, 22673U, 21162U, 15706U, 15687U, 15715U, 15967U, |
| 13725U, 13740U, 13605U, 13779U, 23227U, 13484U, 24498U, 13623U, |
| 15354U, 15696U, 13233U, 26718U, 13355U, 24402U, 11679U, 13180U, |
| 13221U, 22124U, 15939U, 24331U, 11769U, 22544U, 13842U, 24320U, |
| 13408U, 22294U, 22281U, 22718U, 24150U, 24182U, 15871U, 15918U, |
| 15891U, 15747U, 22707U, 24539U, 24569U, 20987U, 11562U, 10295U, |
| 16107U, 24760U, 24790U, 16208U, 16215U, 16222U, 16232U, 11642U, |
| 23019U, 22982U, 13603U, 15356U, 26623U, 13494U, 24112U, 23161U, |
| 24439U, 23178U, 22934U, 11181U, 23210U, 24342U, 23105U, 24471U, |
| 13527U, 11738U, 11155U, 11720U, 24361U, 20951U, 22743U, 11435U, |
| 11379U, 11409U, 11420U, 11360U, 11390U, 13447U, 13431U, 23257U, |
| 13793U, 13810U, 11578U, 10301U, 11648U, 11609U, 23024U, 22988U, |
| 26593U, 21113U, 26576U, 21096U, 11518U, 10267U, 26511U, 21031U, |
| 22160U, 22138U, 13213U, 11692U, 24131U, 24417U, 11067U, 23287U, |
| 24553U, 11173U, 24309U, 24297U, 24392U, 13834U, 24532U, 13766U, |
| 24562U, 15832U, 22901U, 22887U, 15825U, 22894U, 23098U, 16008U, |
| 22255U, 22248U, 24122U, 21219U, 13258U, 21203U, 13205U, 21211U, |
| 13250U, 21195U, 13197U, 22108U, 22100U, 13896U, 13888U, 24030U, |
| 24020U, 24010U, 24000U, 24050U, 24040U, 26655U, 26665U, 24060U, |
| 24073U, 26675U, 26685U, 24086U, 24099U, 11476U, 10246U, 16049U, |
| 8500U, 11353U, 24727U, 16187U, 24942U, 15436U, 22571U, 1205U, |
| 13827U, 1187U, 0U, 13654U, 24524U, 11145U, 15384U, 15408U, |
| 22217U, 22226U, 23148U, 21002U, 23244U, 13536U, 20931U, 20941U, |
| 13266U, 13281U, 20909U, 20920U, 11568U, 15581U, 21065U, 26545U, |
| 21089U, 26569U, 23155U, 11711U, 11701U, 22661U, 24206U, 24238U, |
| 24217U, 22949U, 26813U, 13585U, 26775U, 13567U, 22273U, 22182U, |
| 13465U, 15838U, 23203U, 21129U, 24448U, 22920U, 24353U, 24379U, |
| 24481U, 22686U, 13342U, 11207U, 11504U, 10253U, 16077U, 24734U, |
| 16194U, 8506U, 24456U, 22762U, 22778U, 26709U, 13384U, 13509U, |
| 24164U, 22116U, 11483U, 16056U, 11459U, 16032U, 26494U, 21014U, |
| 11546U, 16091U, 11626U, 23004U, 22966U, 26528U, 21048U, 26552U, |
| 21072U, 26637U, 26644U, 27341U, 21178U, 22529U, 21563U, 21647U, |
| 21863U, 4064U, 9386U, 884U, 8742U, 3089U, 9064U, 8370U, |
| 9701U, 3946U, 9226U, 766U, 8582U, 2919U, 8904U, 8258U, |
| 9547U, 3987U, 9281U, 807U, 8637U, 2960U, 8959U, 8297U, |
| 9600U, 4144U, 9494U, 964U, 8850U, 3235U, 9172U, 8446U, |
| 9805U, 4028U, 9336U, 848U, 8692U, 3053U, 9014U, 8336U, |
| 9653U, 3966U, 9253U, 786U, 8609U, 2939U, 8931U, 8277U, |
| 9573U, 4104U, 9440U, 924U, 8796U, 3129U, 9118U, 8408U, |
| 9753U, 3926U, 9199U, 746U, 8555U, 2899U, 8877U, 8239U, |
| 9521U, 4123U, 9466U, 943U, 8822U, 3214U, 9144U, 8426U, |
| 9778U, 4007U, 9308U, 827U, 8664U, 3032U, 8986U, 8316U, |
| 9626U, 4084U, 9413U, 904U, 8769U, 3109U, 9091U, 8389U, |
| 9727U, 4048U, 9363U, 868U, 8719U, 3073U, 9041U, 8355U, |
| 9679U, 9861U, 22666U, 19465U, 27447U, 13309U, 27384U, 15732U, |
| 27408U, 24613U, 27579U, 16015U, 27486U, 24173U, 27555U, 15998U, |
| 27460U, 24682U, 27605U, 16113U, 27527U, 13351U, 27396U, 15737U, |
| 27421U, 24628U, 27592U, 16021U, 27500U, 24213U, 27567U, 16003U, |
| 27473U, 24687U, 27618U, 16119U, 27541U, 27434U, 21261U, 21549U, |
| 21442U, 21742U, 21633U, 21849U, 17657U, 27162U, 27176U, 27090U, |
| 27083U, 4668U, 4215U, 4696U, 4245U, 4726U, 4757U, 4654U, |
| 4200U, 4682U, 4230U, 4710U, 4742U, 2777U, 3547U, 122U, |
| 26723U, 21489U, 21789U, 140U, 1144U, 27514U, 27311U, 27321U, |
| 27350U, 15977U, 27029U, 22929U, 27044U, 27287U, 27631U, 27263U, |
| 27362U, 27299U, 27642U, 27275U, 27373U, 27758U, 2790U, 3563U, |
| 12472U, 25747U, 21227U, 21244U, 21457U, 21757U, 4815U, 21277U, |
| 21933U, 21324U, 21976U, 21472U, 21300U, 21954U, 21772U, 21370U, |
| 22018U, 21347U, 21997U, 21394U, 22040U, 27125U, 27110U, 27138U, |
| 27151U, 6952U, 26836U, 26846U, 27218U, 12401U, 25611U, 3912U, |
| 8214U, 2044U, 22306U, 22391U, 27883U, 27694U, 27854U, 27672U, |
| 26943U, 27653U, 3593U, 19009U, 1112U, 3803U, 1079U, 3615U, |
| 1102U, 3793U, 22801U, 1059U, 23053U, 22818U, 23070U, 1142U, |
| 26609U, 43U, 128U, 22347U, 23039U, 103U, 15362U, 22083U, |
| 1126U, 3832U, 21504U, 21804U, 21527U, 21827U, 26616U, 55U, |
| 146U, 22354U, 23046U, 110U, 15373U, 22094U, 27515U, 27322U, |
| 27351U, 5075U, 5208U, 5107U, 5260U, 22264U, 27037U, 3726U, |
| 21578U, 21662U, 21878U, 21579U, 21663U, 21879U, 10041U, 9943U, |
| 10156U, 14058U, 13953U, 14218U, 24952U, 16157U, 24984U, 16173U, |
| 26037U, 24266U, 27820U, 24748U, 24778U, 15510U, 3148U, 26883U, |
| 3658U, 5320U, 8191U, 20749U, 7985U, 26856U, 3629U, 5290U, |
| 8163U, 11535U, 24595U, 20193U, 17989U, 15330U, 2838U, 18641U, |
| 22066U, 3283U, 19030U, 10284U, 24583U, 20178U, 17920U, 15341U, |
| 2851U, 22431U, 18655U, 24278U, 20157U, 27833U, 20850U, 13987U, |
| 9978U, 27097U, 3817U, 24767U, 379U, 2362U, 15473U, 2989U, |
| 23531U, 635U, 2675U, 15549U, 3193U, 23885U, 550U, 2590U, |
| 15527U, 3167U, 23769U, 13124U, 674U, 23918U, 24797U, 15978U, |
| 27030U, 22930U, 27045U, 9831U, 3897U, 203U, 27188U, 27226U, |
| 27288U, 27632U, 27253U, 27332U, 13313U, 27015U, 3708U, 24618U, |
| 27059U, 3753U, 27052U, 3735U, 27075U, 3773U, 13366U, 27022U, |
| 3717U, 24633U, 27067U, 3763U, 3744U, 3783U, 27243U, 27234U, |
| 21417U, 21608U, 21692U, 21717U, 21908U, 27264U, 27363U, 8226U, |
| 2055U, 22320U, 22406U, 12459U, 25669U, 3919U, 19016U, 21430U, |
| 21621U, 21705U, 21730U, 21921U, 27741U, 27749U, 26828U, 26820U, |
| 27728U, 26973U, 27776U, 27001U, 27922U, 27951U, 27715U, 26959U, |
| 27763U, 26987U, 27907U, 27937U, 5020U, 4479U, 4494U, 5032U, |
| 5247U, 15846U, 13679U, 13661U, 13695U, 13711U, 13754U, 2808U, |
| 9879U, 2000U, 18200U, 6829U, 18940U, 6961U, 22133U, 19061U, |
| 27203U, 27300U, 27643U, 27276U, 27374U, 26904U, 27849U, 27965U, |
| 26908U, 27969U, 21593U, 21677U, 21893U, 14177U, 18456U, 10101U, |
| 1353U, 25965U, 20624U, 11455U, 11242U, 17942U, 6006U, 19141U, |
| 16889U, 17302U, 19313U, 7871U, 13978U, 1456U, 14095U, 1511U, |
| 25708U, 1869U, 25270U, 1841U, 14050U, 18352U, 14157U, 18443U, |
| 25947U, 20612U, 3401U, 11266U, 17953U, 10339U, 11842U, 14457U, |
| 25023U, 10747U, 12641U, 14946U, 25992U, 10939U, 13006U, 15195U, |
| 26341U, 17519U, 5746U, 9969U, 1258U, 10079U, 1321U, 7841U, |
| 14242U, 1599U, 10181U, 17843U, 14197U, 1571U, 10121U, 17790U, |
| 10553U, 12206U, 14642U, 25388U, 11009U, 13087U, 15265U, 26431U, |
| 11299U, 17962U, 10323U, 11825U, 14441U, 25006U, 17996U, 6228U, |
| 26913U, 20773U, 27867U, 20869U, 27800U, 20827U, 20974U, 7019U, |
| 11235U, 5994U, 11622U, 17330U, 5587U, 2178U, 17357U, 5620U, |
| 10428U, 6884U, 18003U, 6237U, 24868U, 26918U, 3681U, 20781U, |
| 11672U, 1413U, 10652U, 12488U, 14795U, 25794U, 10844U, 12853U, |
| 15053U, 26188U, 15404U, 11229U, 5983U, 6912U, 10729U, 12623U, |
| 14919U, 25974U, 10921U, 12988U, 15177U, 26323U, 10677U, 12562U, |
| 14858U, 25868U, 10869U, 12927U, 15116U, 26262U, 4547U, 4423U, |
| 4931U, 4575U, 4372U, 4871U, 4439U, 5234U, 5173U, 17314U, |
| 27799U, 15591U, 11079U, 5862U, 20973U, 1774U, 76U, 222U, |
| 216U, 230U, 11050U, 5527U, 26782U, 6169U, 13562U, 15767U, |
| 18172U, 26749U, 6132U, 23995U, 15992U, 20118U, 26789U, 6182U, |
| 26756U, 6145U, 10489U, 12156U, 14592U, 25338U, 10623U, 12407U, |
| 14766U, 25617U, 5825U, 22578U, 3303U, 11261U, 2095U, 6029U, |
| 15982U, 17564U, 11114U, 5922U, 11323U, 5574U, 2154U, 17980U, |
| 6195U, 19362U, 11053U, 2067U, 5833U, 11277U, 2114U, 6068U, |
| 26739U, 3501U, 15599U, 11090U, 5883U, 15951U, 19634U, 18775U, |
| 11305U, 2130U, 6110U, 16133U, 20710U, 26803U, 3533U, 11122U, |
| 5935U, 11329U, 2162U, 6206U, 16145U, 20733U, 10465U, 12132U, |
| 14568U, 25314U, 10595U, 12255U, 14669U, 25431U, 10519U, 12172U, |
| 14608U, 25354U, 10637U, 12451U, 14780U, 25661U, 24715U, 20257U, |
| 22191U, 7039U, 26744U, 3508U, 11098U, 5896U, 11311U, 2138U, |
| 6121U, 16139U, 20718U, 11272U, 2107U, 6058U, 11283U, 2122U, |
| 6079U, 26808U, 3540U, 15606U, 11130U, 5948U, 15959U, 19645U, |
| 18785U, 11335U, 2170U, 6217U, 16151U, 20741U, 10568U, 24917U, |
| 10561U, 24905U, 13380U, 2771U, 11058U, 2074U, 5843U, 10435U, |
| 12110U, 14546U, 25292U, 10407U, 12089U, 14525U, 25196U, 15742U, |
| 17554U, 11106U, 5909U, 11317U, 5561U, 2146U, 17971U, 6158U, |
| 18103U, 11289U, 6090U, 11044U, 13161U, 15300U, 24911U, 26488U, |
| 11294U, 6100U, 737U, 1933U, 16831U, 15570U, 17385U, 5642U, |
| 18759U, 6941U, 10443U, 24881U, 10537U, 12190U, 14626U, 25372U, |
| 10816U, 12730U, 15025U, 26105U, 11039U, 13147U, 15295U, 24900U, |
| 26483U, 4958U, 4604U, 4970U, 4617U, 4946U, 4591U, 4857U, |
| 5282U, 4781U, 5274U, 4772U, 13321U, 13296U, 18031U, 18057U, |
| 6772U, 8107U, 2457U, 6435U, 23624U, 7419U, 704U, 2738U, |
| 6704U, 20450U, 23944U, 20082U, 7700U, 10474U, 12141U, 14577U, |
| 25323U, 10610U, 12325U, 14692U, 25514U, 92U, 16280U, 16873U, |
| 9842U, 23193U, 1006U, 1039U, 1093U, 12480U, 6577U, 23761U, |
| 7561U, 10685U, 12570U, 14866U, 25876U, 10877U, 12935U, 15124U, |
| 26270U, 10669U, 12554U, 14850U, 25860U, 10861U, 12919U, 15108U, |
| 26254U, 22062U, 19023U, 7030U, 8139U, 10703U, 12588U, 14884U, |
| 25894U, 10895U, 12953U, 15142U, 26288U, 10764U, 12658U, 14963U, |
| 26009U, 10967U, 13034U, 15223U, 26369U, 26771U, 20726U, 7964U, |
| 8156U, 10016U, 1272U, 9918U, 1226U, 10131U, 1368U, 10029U, |
| 17748U, 9931U, 17675U, 10144U, 17803U, 10047U, 17763U, 9949U, |
| 17690U, 10162U, 17818U, 6354U, 7314U, 12385U, 6563U, 14064U, |
| 18363U, 23745U, 7547U, 12081U, 23550U, 11987U, 6325U, 13959U, |
| 18282U, 23476U, 7285U, 12798U, 6636U, 14224U, 18483U, 23846U, |
| 7620U, 12048U, 6339U, 23485U, 7299U, 12338U, 6517U, 23699U, |
| 7501U, 11940U, 6279U, 23430U, 7239U, 12751U, 6590U, 23800U, |
| 7574U, 12364U, 6532U, 23709U, 7516U, 11966U, 6294U, 23440U, |
| 7254U, 12777U, 6605U, 23810U, 7589U, 12298U, 6488U, 23657U, |
| 7472U, 12375U, 6548U, 23728U, 7532U, 11977U, 6310U, 23459U, |
| 7270U, 12788U, 6621U, 23829U, 7605U, 12308U, 6503U, 23674U, |
| 7487U, 10799U, 12713U, 15008U, 26088U, 10991U, 15247U, 26413U, |
| 9856U, 9863U, 11442U, 13876U, 24931U, 11341U, 13859U, 24924U, |
| 117U, 16296U, 16881U, 9849U, 23319U, 19680U, 24958U, 20369U, |
| 16163U, 23329U, 19693U, 24990U, 20382U, 6993U, 2480U, 17087U, |
| 6464U, 23643U, 19887U, 7448U, 3484U, 3451U, 3439U, 540U, |
| 16692U, 2580U, 17175U, 16179U, 7006U, 3260U, 3468U, 26043U, |
| 20636U, 7939U, 727U, 16818U, 2761U, 17289U, 23963U, 20107U, |
| 7729U, 522U, 16668U, 2562U, 17151U, 23738U, 19941U, 371U, |
| 16529U, 2354U, 17039U, 23525U, 19823U, 344U, 16493U, 2327U, |
| 17015U, 23469U, 19793U, 597U, 16744U, 2637U, 17227U, 23839U, |
| 19994U, 303U, 16440U, 2286U, 16962U, 23405U, 19748U, 313U, |
| 16453U, 2296U, 16975U, 23413U, 19759U, 431U, 16580U, 2414U, |
| 17062U, 23589U, 19866U, 567U, 16705U, 2607U, 17188U, 23784U, |
| 19961U, 324U, 16467U, 2307U, 16989U, 23422U, 19771U, 577U, |
| 16718U, 2617U, 17201U, 23792U, 19972U, 502U, 16642U, 2542U, |
| 17125U, 23691U, 19919U, 353U, 16505U, 2336U, 17027U, 23511U, |
| 19803U, 512U, 16655U, 2552U, 17138U, 23720U, 19930U, 334U, |
| 16480U, 2317U, 17002U, 23451U, 19782U, 587U, 16731U, 2627U, |
| 17214U, 23821U, 19983U, 474U, 16605U, 2514U, 17100U, 23667U, |
| 19898U, 5055U, 4894U, 4521U, 11454U, 26912U, 27866U, 27805U, |
| 15325U, 20980U, 15393U, 15403U, 22190U, 22061U, 8138U, 26770U, |
| 8155U, 24722U, 24703U, 24144U, 20126U, 7781U, 24519U, 1049U, |
| 20903U, 24697U, 15312U, 23198U, 20897U, 24676U, 24723U, 24704U, |
| 7892U, 7902U, 10783U, 12697U, 14982U, 26062U, 10975U, 13062U, |
| 15231U, 26397U, 18619U, 6886U, 9837U, 8070U, 9U, 97U, |
| 1165U, 21136U, 15U, 11764U, 24607U, 24289U, 49U, 134U, |
| 1171U, 21149U, 36U, 14430U, 24638U, 16027U, 24272U, 27826U, |
| 24664U, 8130U, 12614U, 14910U, 25929U, 12979U, 15168U, 26314U, |
| 12536U, 14832U, 25842U, 12901U, 15090U, 26236U, 14306U, 1656U, |
| 14381U, 1708U, 25453U, 20460U, 14343U, 18532U, 15657U, 18848U, |
| 22639U, 19437U, 14407U, 1744U, 14286U, 1626U, 22268U, 14320U, |
| 1675U, 14394U, 1726U, 25465U, 20475U, 14369U, 18564U, 12506U, |
| 14813U, 25812U, 12871U, 15071U, 26206U, 15668U, 18862U, 22650U, |
| 19451U, 14417U, 1759U, 14334U, 1694U, 23092U, 998U, 24856U, |
| 13866U, 24754U, 11594U, 15972U, 984U, 1029U, 24808U, 8550U, |
| 238U, 24709U, 15987U, 991U, 24814U, 10241U, 27793U, 24784U, |
| 22563U, 13421U, 7111U, 5141U, 5119U, 9875U, 17662U, 5777U, |
| 15317U, 18627U, 6894U, 24293U, 24145U, 11138U, 5961U, 20127U, |
| 7782U, 22567U, 13426U, 7120U, 24520U, 22524U, 22210U, 24842U, |
| 20320U, 19086U, 24850U, 20331U, 19340U, 25774U, 20574U, 25737U, |
| 20548U, 14990U, 18597U, 26468U, 20660U, 25764U, 20561U, 25718U, |
| 20523U, 14928U, 18585U, 25675U, 20501U, 23314U, 1013U, 20171U, |
| 7813U, 531U, 16680U, 2571U, 17163U, 23754U, 19951U, 11889U, |
| 284U, 16415U, 2267U, 16950U, 3363U, 23390U, 19727U, 7227U, |
| 25070U, 12034U, 25175U, 12324U, 25513U, 12479U, 25785U, 11926U, |
| 25107U, 12737U, 26112U, 493U, 16630U, 2533U, 1020U, 16861U, |
| 11996U, 25137U, 12421U, 25631U, 12348U, 25527U, 11950U, 25121U, |
| 12761U, 26126U, 12010U, 25151U, 12284U, 25484U, 13110U, 656U, |
| 16794U, 2696U, 17265U, 23904U, 20036U, 7646U, 26454U, 14684U, |
| 25498U, 11797U, 24976U, 12233U, 25409U, 12435U, 25645U, 12666U, |
| 26017U, 13042U, 26377U, 12242U, 25418U, 12444U, 25654U, 10576U, |
| 12220U, 14650U, 25396U, 11789U, 24968U, 2468U, 6449U, 23633U, |
| 7433U, 715U, 2749U, 6718U, 20490U, 23953U, 20094U, 7714U, |
| 11896U, 25077U, 11851U, 25032U, 13140U, 26476U, 11833U, 25014U, |
| 12277U, 25477U, 665U, 16806U, 2705U, 17277U, 6662U, 23911U, |
| 20046U, 7658U, 11867U, 25048U, 12263U, 441U, 16593U, 2424U, |
| 17075U, 3382U, 23597U, 19877U, 7377U, 25439U, 400U, 16540U, |
| 2383U, 17050U, 23558U, 19832U, 7354U, 15576U, 12317U, 25506U, |
| 12814U, 26149U, 12839U, 26174U, 12041U, 25182U, 12331U, 25520U, |
| 11933U, 25114U, 12744U, 26119U, 12003U, 25144U, 12428U, 25638U, |
| 12831U, 606U, 16756U, 2646U, 17239U, 23862U, 20004U, 26166U, |
| 11860U, 265U, 16390U, 2248U, 16938U, 3353U, 23375U, 19706U, |
| 7215U, 25041U, 12356U, 25535U, 11958U, 25129U, 12769U, 26134U, |
| 12018U, 25159U, 12291U, 25491U, 12676U, 26027U, 13052U, 26387U, |
| 14698U, 25543U, 12516U, 25822U, 12881U, 26216U, 15417U, 6930U, |
| 24513U, 7802U, 12527U, 14823U, 25833U, 12892U, 15081U, 26227U, |
| 12497U, 14804U, 25803U, 12862U, 15062U, 26197U, 15855U, 18952U, |
| 11024U, 13102U, 15280U, 26446U, 10603U, 12270U, 14677U, 25446U, |
| 10384U, 11918U, 14502U, 25099U, 10645U, 12465U, 14788U, 25682U, |
| 23194U, 10830U, 12822U, 15039U, 26157U, 24863U, 10392U, 12026U, |
| 14510U, 25167U, 20349U, 19656U, 7182U, 15568U, 15595U, 22911U, |
| 17461U, 3314U, 5548U, 5786U, 6039U, 17480U, 19663U, 9899U, |
| 2024U, 19554U, 19626U, 26695U, 20687U, 18768U, 11084U, 2087U, |
| 5872U, 11063U, 2081U, 5853U, 22908U, 17453U, 3309U, 22514U, |
| 17321U, 5537U, 7085U, 9893U, 2016U, 8043U, 8078U, 19548U, |
| 18754U, 4865U, 3905U, 4798U, 4790U, 5004U, 4836U, 9907U, |
| 2034U, 13176U, 18010U, 17500U, 26700U, 20695U, 7822U, 17669U, |
| 5800U, 27789U, 3848U, 13552U, 18156U, 20812U, 11602U, 82U, |
| 1948U, 5489U, 450U, 2490U, 1155U, 5407U, 8011U, 1913U, |
| 10422U, 12104U, 14540U, 25286U, 15679U, 11224U, 22699U, 162U, |
| 1962U, 10371U, 11905U, 14489U, 25086U, 27873U, 3867U, 20865U, |
| 13893U, 2828U, 13327U, 18066U, 17529U, 26651U, 20680U, 18230U, |
| 27811U, 3854U, 13557U, 18164U, 20835U, 17377U, 5632U, 15852U, |
| 3255U, 8062U, 11605U, 8100U, 13362U, 18080U, 18946U, 6967U, |
| 8124U, 9838U, 5768U, 8071U, 6921U, 174U, 1978U, 16328U, |
| 26955U, 3702U, 20805U, 24939U, 17538U, 3479U, 152U, 16312U, |
| 1177U, 5469U, 8027U, 1923U, 22361U, 19172U, 13519U, 18142U, |
| 19114U, 16125U, 3271U, 13370U, 18087U, 18995U, 17414U, 5677U, |
| 16843U, 11256U, 6019U, 19348U, 23140U, 3341U, 13455U, 18117U, |
| 19612U, 19324U, 11250U, 20242U, 26705U, 186U, 16346U, 19672U, |
| 20703U, 20357U, 7923U, 27845U, 4274U, 4338U, 4306U, 4355U, |
| 4884U, 4625U, 4510U, 4984U, 4641U, 4391U, 4453U, 11541U, |
| 12066U, 6381U, 23503U, 7341U, 14740U, 25585U, 24601U, 22494U, |
| 19287U, 20199U, 11008U, 13086U, 15264U, 26430U, 294U, 16428U, |
| 2277U, 22382U, 19202U, 17995U, 14713U, 25558U, 23398U, 19738U, |
| 15773U, 18876U, 22835U, 19484U, 15799U, 18908U, 22861U, 19516U, |
| 11818U, 6267U, 23368U, 7203U, 10712U, 12597U, 14893U, 25903U, |
| 10904U, 12962U, 15151U, 26297U, 10348U, 11852U, 14466U, 25033U, |
| 13141U, 6733U, 23971U, 10791U, 12705U, 15000U, 7742U, 26080U, |
| 10983U, 13070U, 15239U, 26405U, 10U, 5345U, 98U, 2184U, |
| 16288U, 5387U, 1166U, 5427U, 16U, 16242U, 5355U, 245U, |
| 16364U, 2193U, 16900U, 5437U, 22U, 16251U, 15336U, 17367U, |
| 2844U, 22422U, 19214U, 18647U, 22072U, 17432U, 3289U, 22457U, |
| 19238U, 19036U, 23087U, 11805U, 6255U, 23361U, 7191U, 10694U, |
| 12579U, 14875U, 25885U, 10886U, 12944U, 15133U, 26279U, 10331U, |
| 11834U, 14449U, 25015U, 12278U, 6477U, 23651U, 10721U, 12606U, |
| 14902U, 7461U, 25921U, 10913U, 12971U, 15160U, 26306U, 11765U, |
| 10239U, 17910U, 24608U, 7851U, 6246U, 10661U, 12546U, 14842U, |
| 25852U, 10853U, 12911U, 15100U, 26246U, 17339U, 5598U, 19096U, |
| 7063U, 24874U, 362U, 16517U, 2345U, 15466U, 2980U, 18714U, |
| 23518U, 19813U, 2222U, 15444U, 2873U, 23339U, 409U, 16552U, |
| 2392U, 15492U, 3010U, 18724U, 23565U, 19842U, 626U, 16782U, |
| 2666U, 15542U, 3184U, 18734U, 23878U, 20026U, 2235U, 15455U, |
| 2886U, 23350U, 420U, 16566U, 2403U, 15501U, 3021U, 18744U, |
| 23574U, 19854U, 10290U, 12058U, 6368U, 23495U, 7328U, 14730U, |
| 25575U, 24589U, 22484U, 19274U, 20184U, 11000U, 13078U, 15256U, |
| 26422U, 275U, 16403U, 2258U, 22373U, 19190U, 17926U, 14704U, |
| 25549U, 23383U, 19717U, 50U, 5377U, 135U, 2213U, 16926U, |
| 16304U, 5397U, 1172U, 5459U, 37U, 16271U, 5366U, 255U, |
| 16377U, 2203U, 16913U, 5448U, 29U, 16261U, 15368U, 2866U, |
| 22448U, 19226U, 18671U, 22241U, 19122U, 22089U, 3296U, 22466U, |
| 19250U, 19053U, 66U, 198U, 1195U, 71U, 211U, 1200U, |
| 23116U, 14431U, 24639U, 7861U, 6864U, 16028U, 15811U, 18923U, |
| 22873U, 19531U, 15613U, 18795U, 22595U, 19384U, 14117U, 18403U, |
| 25754U, 1884U, 14167U, 1541U, 25956U, 1899U, 3411U, 14750U, |
| 25595U, 14355U, 18547U, 14295U, 1640U, 24273U, 22504U, 19300U, |
| 22475U, 19262U, 20163U, 27827U, 20856U, 24659U, 7882U, 11032U, |
| 13117U, 15288U, 26461U, 18988U, 6984U, 14035U, 1483U, 14722U, |
| 25567U, 8131U, 14138U, 1527U, 4850U, 4977U, 4164U, 3887U, |
| 10356U, 11875U, 14474U, 25056U, 10363U, 11882U, 14481U, 25063U, |
| 293U, 16427U, 2276U, 23397U, 19737U, 274U, 16402U, 2257U, |
| 23382U, 19716U, 22916U, 3321U, 10505U, 19562U, 7129U, 24888U, |
| 17491U, 5723U, 5045U, 5086U, 22917U, 17472U, 5713U, 3322U, |
| 10506U, 6903U, 19563U, 7130U, 24889U, 26934U, 3689U, 20790U, |
| 5185U, 14025U, 18328U, 13478U, 18133U, 6795U, 11016U, 13094U, |
| 15272U, 26438U, 10376U, 11910U, 14494U, 25091U, 10823U, 12807U, |
| 15032U, 26142U, 13993U, 18295U, 9984U, 17704U, 3373U, 3421U, |
| 22269U, 15642U, 8484U, 17592U, 18830U, 22624U, 8534U, 17629U, |
| 19419U, 15786U, 18892U, 22848U, 19500U, 15628U, 8469U, 17574U, |
| 18813U, 22610U, 8519U, 17611U, 19402U, 13937U, 18263U, 25218U, |
| 20417U, 13912U, 18247U, 25247U, 20432U, 13925U, 1425U, 25203U, |
| 1786U, 25230U, 1806U, 13618U, 13303U, 18041U, 20671U, 18180U, |
| 6806U, 8116U, 11664U, 1400U, 3392U, 3430U, 10225U, 17890U, |
| 22335U, 19154U, 23134U, 3333U, 19603U, 7171U, 7147U, 483U, |
| 16617U, 2523U, 17112U, 23683U, 19908U, 14268U, 18520U, 10207U, |
| 17866U, 14009U, 18317U, 10000U, 17726U, 12815U, 6650U, 23855U, |
| 7634U, 23093U, 24857U, 20340U, 19576U, 2445U, 6420U, 23614U, |
| 7404U, 692U, 2726U, 6689U, 20406U, 23934U, 20069U, 7685U, |
| 616U, 16769U, 2656U, 17252U, 23870U, 20015U, 4805U, 4181U, |
| 8465U, 11348U, 10756U, 12650U, 14955U, 26001U, 10959U, 13026U, |
| 15215U, 26361U, 10236U, 17313U, 5517U, 2039U, 13193U, 18017U, |
| 17904U, 5808U, 11269U, 2102U, 8054U, 11450U, 8093U, 13246U, |
| 18024U, 17956U, 6050U, 8087U, 11786U, 22199U, 17442U, 5699U, |
| 19069U, 7052U, 8146U, 87U, 1955U, 5503U, 462U, 2502U, |
| 1160U, 5417U, 8019U, 1918U, 24755U, 20267U, 15683U, 22703U, |
| 168U, 1970U, 9871U, 1994U, 17655U, 13884U, 2822U, 18223U, |
| 26796U, 3524U, 13167U, 6758U, 7973U, 23986U, 7767U, 26763U, |
| 3515U, 13152U, 6744U, 7952U, 23977U, 7753U, 12214U, 6394U, |
| 23583U, 7366U, 22582U, 26928U, 14427U, 17349U, 5610U, 2833U, |
| 13331U, 18073U, 10401U, 14519U, 25190U, 22077U, 24835U, 20310U, |
| 19044U, 14259U, 18508U, 10198U, 17854U, 14207U, 18469U, 26070U, |
| 20647U, 14001U, 18306U, 9992U, 17715U, 14128U, 18417U, 25912U, |
| 20588U, 14250U, 18496U, 10189U, 1386U, 14106U, 18389U, 10090U, |
| 1337U, 25727U, 20535U, 13904U, 18236U, 9910U, 1213U, 14074U, |
| 18376U, 10058U, 1290U, 25689U, 20511U, 14277U, 1612U, 10216U, |
| 17878U, 14017U, 1470U, 10008U, 17737U, 18579U, 6856U, 13335U, |
| 6783U, 10421U, 12103U, 14539U, 25285U, 10370U, 11904U, 14488U, |
| 25085U, 15973U, 17396U, 5655U, 1030U, 3584U, 10451U, 12118U, |
| 14554U, 25300U, 24809U, 20283U, 10583U, 12227U, 14657U, 18974U, |
| 6975U, 25403U, 24258U, 3462U, 20143U, 26938U, 3695U, 20797U, |
| 27901U, 3879U, 20878U, 27815U, 3860U, 20842U, 13400U, 26923U, |
| 10528U, 12181U, 14617U, 25363U, 10808U, 12722U, 15017U, 26097U, |
| 8551U, 10414U, 12096U, 14532U, 25278U, 10481U, 12148U, 14584U, |
| 25330U, 10616U, 12394U, 14759U, 25604U, 24710U, 20249U, 10317U, |
| 11812U, 14435U, 17648U, 25000U, 15988U, 17405U, 5666U, 10458U, |
| 12125U, 14561U, 25307U, 10497U, 12164U, 14600U, 25346U, 10630U, |
| 12414U, 14773U, 25624U, 24815U, 20291U, 10589U, 12249U, 14663U, |
| 18981U, 25425U, 22262U, 19132U, 7074U, 10839U, 12848U, 15048U, |
| 26183U, 10242U, 13969U, 1442U, 14084U, 1495U, 25698U, 1854U, |
| 25262U, 1828U, 14042U, 18341U, 14147U, 18430U, 25938U, 20600U, |
| 10948U, 13015U, 15204U, 26350U, 10772U, 12686U, 14971U, 26051U, |
| 10738U, 12632U, 14937U, 25983U, 10930U, 12997U, 15186U, 26332U, |
| 17509U, 5734U, 9960U, 1244U, 10068U, 1305U, 7831U, 14234U, |
| 1586U, 10173U, 17832U, 14187U, 1556U, 10111U, 17777U, 10545U, |
| 12198U, 14634U, 25380U, 11001U, 13079U, 15257U, 26423U, 17913U, |
| 5816U, 27794U, 20819U, 180U, 1986U, 16337U, 24949U, 17546U, |
| 5758U, 3496U, 157U, 16320U, 1182U, 5479U, 8035U, 1928U, |
| 22367U, 19181U, 13523U, 18149U, 16129U, 3277U, 13375U, 18095U, |
| 19002U, 17423U, 5688U, 16852U, 19355U, 23144U, 3347U, 13460U, |
| 18125U, 19619U, 19332U, 7101U, 192U, 16355U, 20363U, 7931U, |
| 11202U, 15306U, 18610U, 6873U, 17934U, 5973U, 15863U, 18963U, |
| 4829U, 4192U, 4290U, 4996U, 5012U, 4322U, 4260U, 5151U, |
| 5065U, 4906U, 4534U, 4918U, 4561U, 5096U, 4174U, 5130U, |
| 4267U, 5162U, 5221U, 4407U, 4466U, 22586U, 15379U, 18679U, |
| 19369U, 13317U, 15315U, 24644U, 20216U, 18625U, 24623U, 20208U, |
| 18050U, 24827U, 13645U, 18188U, 20299U, 22235U, 19105U, 22795U, |
| 19475U, 15429U, 18704U, 23127U, 19593U, 24820U, 13637U, 6816U, |
| 7911U, 22205U, 19078U, 22590U, 19376U, 15423U, 18695U, 23121U, |
| 19584U, 24262U, 15398U, 20225U, 18687U, 24692U, 20234U, 20150U, |
| 13404U, 15320U, 18633U, 18110U, 2433U, 6405U, 23604U, 7389U, |
| 680U, 2714U, 6674U, 20395U, 23924U, 20056U, 7670U, 24650U, |
| 24785U, 20275U, 24657U, 61U, 24670U, 10400U, 12074U, 14518U, |
| 25189U, 24177U, 20135U, 7792U, 22341U, 19163U, 7159U, 13871U, |
| 18215U, 6846U, 22978U, 17471U, 5712U, 3327U, 10512U, 6902U, |
| 19569U, 7138U, 24894U, 26933U, 3688U, 20789U, 5196U, 11599U, |
| }; |
| |
| static inline void InitMipsMCInstrInfo(MCInstrInfo *II) { |
| II->InitMCInstrInfo(MipsInsts, MipsInstrNameIndices, MipsInstrNameData, nullptr, nullptr, 2848); |
| } |
| |
| } // end namespace llvm |
| #endif // GET_INSTRINFO_MC_DESC |
| |
| #ifdef GET_INSTRINFO_HEADER |
| #undef GET_INSTRINFO_HEADER |
| namespace llvm { |
| struct MipsGenInstrInfo : public TargetInstrInfo { |
| explicit MipsGenInstrInfo(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u); |
| ~MipsGenInstrInfo() override = default; |
| |
| }; |
| } // end namespace llvm |
| #endif // GET_INSTRINFO_HEADER |
| |
| #ifdef GET_INSTRINFO_HELPER_DECLS |
| #undef GET_INSTRINFO_HELPER_DECLS |
| |
| |
| #endif // GET_INSTRINFO_HELPER_DECLS |
| |
| #ifdef GET_INSTRINFO_HELPERS |
| #undef GET_INSTRINFO_HELPERS |
| |
| #endif // GET_INSTRINFO_HELPERS |
| |
| #ifdef GET_INSTRINFO_CTOR_DTOR |
| #undef GET_INSTRINFO_CTOR_DTOR |
| namespace llvm { |
| extern const MCInstrDesc MipsInsts[]; |
| extern const unsigned MipsInstrNameIndices[]; |
| extern const char MipsInstrNameData[]; |
| MipsGenInstrInfo::MipsGenInstrInfo(unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode) |
| : TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) { |
| InitMCInstrInfo(MipsInsts, MipsInstrNameIndices, MipsInstrNameData, nullptr, nullptr, 2848); |
| } |
| } // end namespace llvm |
| #endif // GET_INSTRINFO_CTOR_DTOR |
| |
| #ifdef GET_INSTRINFO_OPERAND_ENUM |
| #undef GET_INSTRINFO_OPERAND_ENUM |
| namespace llvm { |
| namespace Mips { |
| namespace OpName { |
| enum { |
| OPERAND_LAST |
| }; |
| } // end namespace OpName |
| } // end namespace Mips |
| } // end namespace llvm |
| #endif //GET_INSTRINFO_OPERAND_ENUM |
| |
| #ifdef GET_INSTRINFO_NAMED_OPS |
| #undef GET_INSTRINFO_NAMED_OPS |
| namespace llvm { |
| namespace Mips { |
| LLVM_READONLY |
| int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) { |
| return -1; |
| } |
| } // end namespace Mips |
| } // end namespace llvm |
| #endif //GET_INSTRINFO_NAMED_OPS |
| |
| #ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM |
| #undef GET_INSTRINFO_OPERAND_TYPES_ENUM |
| namespace llvm { |
| namespace Mips { |
| namespace OpTypes { |
| enum OperandType { |
| InvertedImOperand = 0, |
| InvertedImOperand64 = 1, |
| PtrRC = 2, |
| brtarget = 3, |
| brtarget10_mm = 4, |
| brtarget1SImm16 = 5, |
| brtarget21 = 6, |
| brtarget21_mm = 7, |
| brtarget26 = 8, |
| brtarget26_mm = 9, |
| brtarget7_mm = 10, |
| brtarget_lsl2_mm = 11, |
| brtarget_mm = 12, |
| brtargetr6 = 13, |
| calloffset16 = 14, |
| calltarget = 15, |
| calltarget_mm = 16, |
| condcode = 17, |
| cpinst_operand = 18, |
| f32imm = 19, |
| f64imm = 20, |
| i16imm = 21, |
| i1imm = 22, |
| i32imm = 23, |
| i64imm = 24, |
| i8imm = 25, |
| imm64 = 26, |
| jmpoffset16 = 27, |
| jmptarget = 28, |
| jmptarget_mm = 29, |
| li16_imm = 30, |
| mem = 31, |
| mem16 = 32, |
| mem16_ea = 33, |
| mem16sp = 34, |
| mem_ea = 35, |
| mem_mm_11 = 36, |
| mem_mm_12 = 37, |
| mem_mm_16 = 38, |
| mem_mm_4 = 39, |
| mem_mm_4_lsl1 = 40, |
| mem_mm_4_lsl2 = 41, |
| mem_mm_4sp = 42, |
| mem_mm_9 = 43, |
| mem_mm_gp_simm7_lsl2 = 44, |
| mem_mm_sp_imm5_lsl2 = 45, |
| mem_msa = 46, |
| mem_simm10 = 47, |
| mem_simm10_lsl1 = 48, |
| mem_simm10_lsl2 = 49, |
| mem_simm10_lsl3 = 50, |
| mem_simm11 = 51, |
| mem_simm12 = 52, |
| mem_simm16 = 53, |
| mem_simm9 = 54, |
| mem_simm9_exp = 55, |
| mem_simmptr = 56, |
| pcrel16 = 57, |
| ptype0 = 58, |
| ptype1 = 59, |
| ptype2 = 60, |
| ptype3 = 61, |
| ptype4 = 62, |
| ptype5 = 63, |
| reglist = 64, |
| reglist16 = 65, |
| simm10 = 66, |
| simm10_64 = 67, |
| simm10_lsl1 = 68, |
| simm10_lsl2 = 69, |
| simm10_lsl3 = 70, |
| simm11 = 71, |
| simm12 = 72, |
| simm16 = 73, |
| simm16_64 = 74, |
| simm16_relaxed = 75, |
| simm18_lsl3 = 76, |
| simm19_lsl2 = 77, |
| simm23_lsl2 = 78, |
| simm32 = 79, |
| simm32_relaxed = 80, |
| simm3_lsa2 = 81, |
| simm4 = 82, |
| simm5 = 83, |
| simm6 = 84, |
| simm7_lsl2 = 85, |
| simm9 = 86, |
| simm9_addiusp = 87, |
| size_ins = 88, |
| type0 = 89, |
| type1 = 90, |
| type2 = 91, |
| type3 = 92, |
| type4 = 93, |
| type5 = 94, |
| uimm1 = 95, |
| uimm10 = 96, |
| uimm16 = 97, |
| uimm16_64 = 98, |
| uimm16_64_relaxed = 99, |
| uimm16_altrelaxed = 100, |
| uimm16_relaxed = 101, |
| uimm1_ptr = 102, |
| uimm2 = 103, |
| uimm20 = 104, |
| uimm26 = 105, |
| uimm2_plus1 = 106, |
| uimm2_ptr = 107, |
| uimm3 = 108, |
| uimm32_coerced = 109, |
| uimm3_ptr = 110, |
| uimm3_shift = 111, |
| uimm4 = 112, |
| uimm4_andi = 113, |
| uimm4_ptr = 114, |
| uimm5 = 115, |
| uimm5_64 = 116, |
| uimm5_64_report_uimm6 = 117, |
| uimm5_inssize_plus1 = 118, |
| uimm5_lsl2 = 119, |
| uimm5_plus1 = 120, |
| uimm5_plus1_report_uimm6 = 121, |
| uimm5_plus32 = 122, |
| uimm5_plus32_normalize = 123, |
| uimm5_plus32_normalize_64 = 124, |
| uimm5_plus33 = 125, |
| uimm5_report_uimm6 = 126, |
| uimm6 = 127, |
| uimm6_lsl2 = 128, |
| uimm7 = 129, |
| uimm8 = 130, |
| uimm_range_2_64 = 131, |
| uimmz = 132, |
| untyped_imm_0 = 133, |
| vsplat_simm10 = 134, |
| vsplat_simm5 = 135, |
| vsplat_uimm1 = 136, |
| vsplat_uimm2 = 137, |
| vsplat_uimm3 = 138, |
| vsplat_uimm4 = 139, |
| vsplat_uimm5 = 140, |
| vsplat_uimm6 = 141, |
| vsplat_uimm8 = 142, |
| ACC64DSPOpnd = 143, |
| AFGR64Opnd = 144, |
| CCROpnd = 145, |
| COP0Opnd = 146, |
| COP2Opnd = 147, |
| COP3Opnd = 148, |
| DSPROpnd = 149, |
| FCCRegsOpnd = 150, |
| FGR32Opnd = 151, |
| FGR64Opnd = 152, |
| FGRCCOpnd = 153, |
| GPR32NonZeroOpnd = 154, |
| GPR32Opnd = 155, |
| GPR32ZeroOpnd = 156, |
| GPR64Opnd = 157, |
| GPRMM16Opnd = 158, |
| GPRMM16OpndMoveP = 159, |
| GPRMM16OpndMovePPairFirst = 160, |
| GPRMM16OpndMovePPairSecond = 161, |
| GPRMM16OpndZero = 162, |
| HI32DSPOpnd = 163, |
| HWRegsOpnd = 164, |
| LO32DSPOpnd = 165, |
| MSA128BOpnd = 166, |
| MSA128CROpnd = 167, |
| MSA128DOpnd = 168, |
| MSA128F16Opnd = 169, |
| MSA128HOpnd = 170, |
| MSA128WOpnd = 171, |
| StrictlyAFGR64Opnd = 172, |
| StrictlyFGR32Opnd = 173, |
| StrictlyFGR64Opnd = 174, |
| ACC128 = 175, |
| ACC64 = 176, |
| ACC64DSP = 177, |
| AFGR64 = 178, |
| CCR = 179, |
| COP0 = 180, |
| COP2 = 181, |
| COP3 = 182, |
| CPU16Regs = 183, |
| CPU16RegsPlusSP = 184, |
| CPURAReg = 185, |
| CPUSPReg = 186, |
| DSPCC = 187, |
| DSPR = 188, |
| FCC = 189, |
| FGR32 = 190, |
| FGR64 = 191, |
| FGRCC = 192, |
| GP32 = 193, |
| GP64 = 194, |
| GPR32 = 195, |
| GPR32NONZERO = 196, |
| GPR32ZERO = 197, |
| GPR64 = 198, |
| GPRMM16 = 199, |
| GPRMM16MoveP = 200, |
| GPRMM16MovePPairFirst = 201, |
| GPRMM16MovePPairSecond = 202, |
| GPRMM16Zero = 203, |
| HI32 = 204, |
| HI32DSP = 205, |
| HI64 = 206, |
| HWRegs = 207, |
| LO32 = 208, |
| LO32DSP = 209, |
| LO64 = 210, |
| MSA128B = 211, |
| MSA128D = 212, |
| MSA128F16 = 213, |
| MSA128H = 214, |
| MSA128W = 215, |
| MSA128WEvens = 216, |
| MSACtrl = 217, |
| OCTEON_MPL = 218, |
| OCTEON_P = 219, |
| SP32 = 220, |
| SP64 = 221, |
| OPERAND_TYPE_LIST_END |
| }; |
| } // end namespace OpTypes |
| } // end namespace Mips |
| } // end namespace llvm |
| #endif // GET_INSTRINFO_OPERAND_TYPES_ENUM |
| |
| #ifdef GET_INSTRINFO_OPERAND_TYPE |
| #undef GET_INSTRINFO_OPERAND_TYPE |
| namespace llvm { |
| namespace Mips { |
| LLVM_READONLY |
| static int getOperandType(uint16_t Opcode, uint16_t OpIdx) { |
| const uint16_t Offsets[] = { |
| /* PHI */ |
| 0, |
| /* INLINEASM */ |
| 1, |
| /* INLINEASM_BR */ |
| 1, |
| /* CFI_INSTRUCTION */ |
| 1, |
| /* EH_LABEL */ |
| 2, |
| /* GC_LABEL */ |
| 3, |
| /* ANNOTATION_LABEL */ |
| 4, |
| /* KILL */ |
| 5, |
| /* EXTRACT_SUBREG */ |
| 5, |
| /* INSERT_SUBREG */ |
| 8, |
| /* IMPLICIT_DEF */ |
| 12, |
| /* SUBREG_TO_REG */ |
| 13, |
| /* COPY_TO_REGCLASS */ |
| 17, |
| /* DBG_VALUE */ |
| 20, |
| /* DBG_VALUE_LIST */ |
| 20, |
| /* DBG_INSTR_REF */ |
| 20, |
| /* DBG_PHI */ |
| 20, |
| /* DBG_LABEL */ |
| 20, |
| /* REG_SEQUENCE */ |
| 21, |
| /* COPY */ |
| 23, |
| /* BUNDLE */ |
| 25, |
| /* LIFETIME_START */ |
| 25, |
| /* LIFETIME_END */ |
| 26, |
| /* PSEUDO_PROBE */ |
| 27, |
| /* ARITH_FENCE */ |
| 31, |
| /* STACKMAP */ |
| 33, |
| /* FENTRY_CALL */ |
| 35, |
| /* PATCHPOINT */ |
| 35, |
| /* LOAD_STACK_GUARD */ |
| 41, |
| /* PREALLOCATED_SETUP */ |
| 42, |
| /* PREALLOCATED_ARG */ |
| 43, |
| /* STATEPOINT */ |
| 46, |
| /* LOCAL_ESCAPE */ |
| 46, |
| /* FAULTING_OP */ |
| 48, |
| /* PATCHABLE_OP */ |
| 49, |
| /* PATCHABLE_FUNCTION_ENTER */ |
| 49, |
| /* PATCHABLE_RET */ |
| 49, |
| /* PATCHABLE_FUNCTION_EXIT */ |
| 49, |
| /* PATCHABLE_TAIL_CALL */ |
| 49, |
| /* PATCHABLE_EVENT_CALL */ |
| 49, |
| /* PATCHABLE_TYPED_EVENT_CALL */ |
| 51, |
| /* ICALL_BRANCH_FUNNEL */ |
| 54, |
| /* MEMBARRIER */ |
| 54, |
| /* G_ASSERT_SEXT */ |
| 54, |
| /* G_ASSERT_ZEXT */ |
| 57, |
| /* G_ASSERT_ALIGN */ |
| 60, |
| /* G_ADD */ |
| 63, |
| /* G_SUB */ |
| 66, |
| /* G_MUL */ |
| 69, |
| /* G_SDIV */ |
| 72, |
| /* G_UDIV */ |
| 75, |
| /* G_SREM */ |
| 78, |
| /* G_UREM */ |
| 81, |
| /* G_SDIVREM */ |
| 84, |
| /* G_UDIVREM */ |
| 88, |
| /* G_AND */ |
| 92, |
| /* G_OR */ |
| 95, |
| /* G_XOR */ |
| 98, |
| /* G_IMPLICIT_DEF */ |
| 101, |
| /* G_PHI */ |
| 102, |
| /* G_FRAME_INDEX */ |
| 103, |
| /* G_GLOBAL_VALUE */ |
| 105, |
| /* G_EXTRACT */ |
| 107, |
| /* G_UNMERGE_VALUES */ |
| 110, |
| /* G_INSERT */ |
| 112, |
| /* G_MERGE_VALUES */ |
| 116, |
| /* G_BUILD_VECTOR */ |
| 118, |
| /* G_BUILD_VECTOR_TRUNC */ |
| 120, |
| /* G_CONCAT_VECTORS */ |
| 122, |
| /* G_PTRTOINT */ |
| 124, |
| /* G_INTTOPTR */ |
| 126, |
| /* G_BITCAST */ |
| 128, |
| /* G_FREEZE */ |
| 130, |
| /* G_INTRINSIC_FPTRUNC_ROUND */ |
| 132, |
| /* G_INTRINSIC_TRUNC */ |
| 135, |
| /* G_INTRINSIC_ROUND */ |
| 137, |
| /* G_INTRINSIC_LRINT */ |
| 139, |
| /* G_INTRINSIC_ROUNDEVEN */ |
| 141, |
| /* G_READCYCLECOUNTER */ |
| 143, |
| /* G_LOAD */ |
| 144, |
| /* G_SEXTLOAD */ |
| 146, |
| /* G_ZEXTLOAD */ |
| 148, |
| /* G_INDEXED_LOAD */ |
| 150, |
| /* G_INDEXED_SEXTLOAD */ |
| 155, |
| /* G_INDEXED_ZEXTLOAD */ |
| 160, |
| /* G_STORE */ |
| 165, |
| /* G_INDEXED_STORE */ |
| 167, |
| /* G_ATOMIC_CMPXCHG_WITH_SUCCESS */ |
| 172, |
| /* G_ATOMIC_CMPXCHG */ |
| 177, |
| /* G_ATOMICRMW_XCHG */ |
| 181, |
| /* G_ATOMICRMW_ADD */ |
| 184, |
| /* G_ATOMICRMW_SUB */ |
| 187, |
| /* G_ATOMICRMW_AND */ |
| 190, |
| /* G_ATOMICRMW_NAND */ |
| 193, |
| /* G_ATOMICRMW_OR */ |
| 196, |
| /* G_ATOMICRMW_XOR */ |
| 199, |
| /* G_ATOMICRMW_MAX */ |
| 202, |
| /* G_ATOMICRMW_MIN */ |
| 205, |
| /* G_ATOMICRMW_UMAX */ |
| 208, |
| /* G_ATOMICRMW_UMIN */ |
| 211, |
| /* G_ATOMICRMW_FADD */ |
| 214, |
| /* G_ATOMICRMW_FSUB */ |
| 217, |
| /* G_ATOMICRMW_FMAX */ |
| 220, |
| /* G_ATOMICRMW_FMIN */ |
| 223, |
| /* G_ATOMICRMW_UINC_WRAP */ |
| 226, |
| /* G_ATOMICRMW_UDEC_WRAP */ |
| 229, |
| /* G_FENCE */ |
| 232, |
| /* G_BRCOND */ |
| 234, |
| /* G_BRINDIRECT */ |
| 236, |
| /* G_INVOKE_REGION_START */ |
| 237, |
| /* G_INTRINSIC */ |
| 237, |
| /* G_INTRINSIC_W_SIDE_EFFECTS */ |
| 238, |
| /* G_ANYEXT */ |
| 239, |
| /* G_TRUNC */ |
| 241, |
| /* G_CONSTANT */ |
| 243, |
| /* G_FCONSTANT */ |
| 245, |
| /* G_VASTART */ |
| 247, |
| /* G_VAARG */ |
| 248, |
| /* G_SEXT */ |
| 251, |
| /* G_SEXT_INREG */ |
| 253, |
| /* G_ZEXT */ |
| 256, |
| /* G_SHL */ |
| 258, |
| /* G_LSHR */ |
| 261, |
| /* G_ASHR */ |
| 264, |
| /* G_FSHL */ |
| 267, |
| /* G_FSHR */ |
| 271, |
| /* G_ROTR */ |
| 275, |
| /* G_ROTL */ |
| 278, |
| /* G_ICMP */ |
| 281, |
| /* G_FCMP */ |
| 285, |
| /* G_SELECT */ |
| 289, |
| /* G_UADDO */ |
| 293, |
| /* G_UADDE */ |
| 297, |
| /* G_USUBO */ |
| 302, |
| /* G_USUBE */ |
| 306, |
| /* G_SADDO */ |
| 311, |
| /* G_SADDE */ |
| 315, |
| /* G_SSUBO */ |
| 320, |
| /* G_SSUBE */ |
| 324, |
| /* G_UMULO */ |
| 329, |
| /* G_SMULO */ |
| 333, |
| /* G_UMULH */ |
| 337, |
| /* G_SMULH */ |
| 340, |
| /* G_UADDSAT */ |
| 343, |
| /* G_SADDSAT */ |
| 346, |
| /* G_USUBSAT */ |
| 349, |
| /* G_SSUBSAT */ |
| 352, |
| /* G_USHLSAT */ |
| 355, |
| /* G_SSHLSAT */ |
| 358, |
| /* G_SMULFIX */ |
| 361, |
| /* G_UMULFIX */ |
| 365, |
| /* G_SMULFIXSAT */ |
| 369, |
| /* G_UMULFIXSAT */ |
| 373, |
| /* G_SDIVFIX */ |
| 377, |
| /* G_UDIVFIX */ |
| 381, |
| /* G_SDIVFIXSAT */ |
| 385, |
| /* G_UDIVFIXSAT */ |
| 389, |
| /* G_FADD */ |
| 393, |
| /* G_FSUB */ |
| 396, |
| /* G_FMUL */ |
| 399, |
| /* G_FMA */ |
| 402, |
| /* G_FMAD */ |
| 406, |
| /* G_FDIV */ |
| 410, |
| /* G_FREM */ |
| 413, |
| /* G_FPOW */ |
| 416, |
| /* G_FPOWI */ |
| 419, |
| /* G_FEXP */ |
| 422, |
| /* G_FEXP2 */ |
| 424, |
| /* G_FLOG */ |
| 426, |
| /* G_FLOG2 */ |
| 428, |
| /* G_FLOG10 */ |
| 430, |
| /* G_FNEG */ |
| 432, |
| /* G_FPEXT */ |
| 434, |
| /* G_FPTRUNC */ |
| 436, |
| /* G_FPTOSI */ |
| 438, |
| /* G_FPTOUI */ |
| 440, |
| /* G_SITOFP */ |
| 442, |
| /* G_UITOFP */ |
| 444, |
| /* G_FABS */ |
| 446, |
| /* G_FCOPYSIGN */ |
| 448, |
| /* G_IS_FPCLASS */ |
| 451, |
| /* G_FCANONICALIZE */ |
| 454, |
| /* G_FMINNUM */ |
| 456, |
| /* G_FMAXNUM */ |
| 459, |
| /* G_FMINNUM_IEEE */ |
| 462, |
| /* G_FMAXNUM_IEEE */ |
| 465, |
| /* G_FMINIMUM */ |
| 468, |
| /* G_FMAXIMUM */ |
| 471, |
| /* G_PTR_ADD */ |
| 474, |
| /* G_PTRMASK */ |
| 477, |
| /* G_SMIN */ |
| 480, |
| /* G_SMAX */ |
| 483, |
| /* G_UMIN */ |
| 486, |
| /* G_UMAX */ |
| 489, |
| /* G_ABS */ |
| 492, |
| /* G_LROUND */ |
| 494, |
| /* G_LLROUND */ |
| 496, |
| /* G_BR */ |
| 498, |
| /* G_BRJT */ |
| 499, |
| /* G_INSERT_VECTOR_ELT */ |
| 502, |
| /* G_EXTRACT_VECTOR_ELT */ |
| 506, |
| /* G_SHUFFLE_VECTOR */ |
| 509, |
| /* G_CTTZ */ |
| 513, |
| /* G_CTTZ_ZERO_UNDEF */ |
| 515, |
| /* G_CTLZ */ |
| 517, |
| /* G_CTLZ_ZERO_UNDEF */ |
| 519, |
| /* G_CTPOP */ |
| 521, |
| /* G_BSWAP */ |
| 523, |
| /* G_BITREVERSE */ |
| 525, |
| /* G_FCEIL */ |
| 527, |
| /* G_FCOS */ |
| 529, |
| /* G_FSIN */ |
| 531, |
| /* G_FSQRT */ |
| 533, |
| /* G_FFLOOR */ |
| 535, |
| /* G_FRINT */ |
| 537, |
| /* G_FNEARBYINT */ |
| 539, |
| /* G_ADDRSPACE_CAST */ |
| 541, |
| /* G_BLOCK_ADDR */ |
| 543, |
| /* G_JUMP_TABLE */ |
| 545, |
| /* G_DYN_STACKALLOC */ |
| 547, |
| /* G_STRICT_FADD */ |
| 550, |
| /* G_STRICT_FSUB */ |
| 553, |
| /* G_STRICT_FMUL */ |
| 556, |
| /* G_STRICT_FDIV */ |
| 559, |
| /* G_STRICT_FREM */ |
| 562, |
| /* G_STRICT_FMA */ |
| 565, |
| /* G_STRICT_FSQRT */ |
| 569, |
| /* G_READ_REGISTER */ |
| 571, |
| /* G_WRITE_REGISTER */ |
| 573, |
| /* G_MEMCPY */ |
| 575, |
| /* G_MEMCPY_INLINE */ |
| 579, |
| /* G_MEMMOVE */ |
| 582, |
| /* G_MEMSET */ |
| 586, |
| /* G_BZERO */ |
| 590, |
| /* G_VECREDUCE_SEQ_FADD */ |
| 593, |
| /* G_VECREDUCE_SEQ_FMUL */ |
| 596, |
| /* G_VECREDUCE_FADD */ |
| 599, |
| /* G_VECREDUCE_FMUL */ |
| 601, |
| /* G_VECREDUCE_FMAX */ |
| 603, |
| /* G_VECREDUCE_FMIN */ |
| 605, |
| /* G_VECREDUCE_ADD */ |
| 607, |
| /* G_VECREDUCE_MUL */ |
| 609, |
| /* G_VECREDUCE_AND */ |
| 611, |
| /* G_VECREDUCE_OR */ |
| 613, |
| /* G_VECREDUCE_XOR */ |
| 615, |
| /* G_VECREDUCE_SMAX */ |
| 617, |
| /* G_VECREDUCE_SMIN */ |
| 619, |
| /* G_VECREDUCE_UMAX */ |
| 621, |
| /* G_VECREDUCE_UMIN */ |
| 623, |
| /* G_SBFX */ |
| 625, |
| /* G_UBFX */ |
| 629, |
| /* ABSMacro */ |
| 633, |
| /* ADJCALLSTACKDOWN */ |
| 635, |
| /* ADJCALLSTACKUP */ |
| 637, |
| /* AND_V_D_PSEUDO */ |
| 639, |
| /* AND_V_H_PSEUDO */ |
| 642, |
| /* AND_V_W_PSEUDO */ |
| 645, |
| /* ATOMIC_CMP_SWAP_I16 */ |
| 648, |
| /* ATOMIC_CMP_SWAP_I16_POSTRA */ |
| 652, |
| /* ATOMIC_CMP_SWAP_I32 */ |
| 659, |
| /* ATOMIC_CMP_SWAP_I32_POSTRA */ |
| 663, |
| /* ATOMIC_CMP_SWAP_I64 */ |
| 667, |
| /* ATOMIC_CMP_SWAP_I64_POSTRA */ |
| 671, |
| /* ATOMIC_CMP_SWAP_I8 */ |
| 675, |
| /* ATOMIC_CMP_SWAP_I8_POSTRA */ |
| 679, |
| /* ATOMIC_LOAD_ADD_I16 */ |
| 686, |
| /* ATOMIC_LOAD_ADD_I16_POSTRA */ |
| 689, |
| /* ATOMIC_LOAD_ADD_I32 */ |
| 695, |
| /* ATOMIC_LOAD_ADD_I32_POSTRA */ |
| 698, |
| /* ATOMIC_LOAD_ADD_I64 */ |
| 701, |
| /* ATOMIC_LOAD_ADD_I64_POSTRA */ |
| 704, |
| /* ATOMIC_LOAD_ADD_I8 */ |
| 707, |
| /* ATOMIC_LOAD_ADD_I8_POSTRA */ |
| 710, |
| /* ATOMIC_LOAD_AND_I16 */ |
| 716, |
| /* ATOMIC_LOAD_AND_I16_POSTRA */ |
| 719, |
| /* ATOMIC_LOAD_AND_I32 */ |
| 725, |
| /* ATOMIC_LOAD_AND_I32_POSTRA */ |
| 728, |
| /* ATOMIC_LOAD_AND_I64 */ |
| 731, |
| /* ATOMIC_LOAD_AND_I64_POSTRA */ |
| 734, |
| /* ATOMIC_LOAD_AND_I8 */ |
| 737, |
| /* ATOMIC_LOAD_AND_I8_POSTRA */ |
| 740, |
| /* ATOMIC_LOAD_MAX_I16 */ |
| 746, |
| /* ATOMIC_LOAD_MAX_I16_POSTRA */ |
| 749, |
| /* ATOMIC_LOAD_MAX_I32 */ |
| 755, |
| /* ATOMIC_LOAD_MAX_I32_POSTRA */ |
| 758, |
| /* ATOMIC_LOAD_MAX_I64 */ |
| 761, |
| /* ATOMIC_LOAD_MAX_I64_POSTRA */ |
| 764, |
| /* ATOMIC_LOAD_MAX_I8 */ |
| 767, |
| /* ATOMIC_LOAD_MAX_I8_POSTRA */ |
| 770, |
| /* ATOMIC_LOAD_MIN_I16 */ |
| 776, |
| /* ATOMIC_LOAD_MIN_I16_POSTRA */ |
| 779, |
| /* ATOMIC_LOAD_MIN_I32 */ |
| 785, |
| /* ATOMIC_LOAD_MIN_I32_POSTRA */ |
| 788, |
| /* ATOMIC_LOAD_MIN_I64 */ |
| 791, |
| /* ATOMIC_LOAD_MIN_I64_POSTRA */ |
| 794, |
| /* ATOMIC_LOAD_MIN_I8 */ |
| 797, |
| /* ATOMIC_LOAD_MIN_I8_POSTRA */ |
| 800, |
| /* ATOMIC_LOAD_NAND_I16 */ |
| 806, |
| /* ATOMIC_LOAD_NAND_I16_POSTRA */ |
| 809, |
| /* ATOMIC_LOAD_NAND_I32 */ |
| 815, |
| /* ATOMIC_LOAD_NAND_I32_POSTRA */ |
| 818, |
| /* ATOMIC_LOAD_NAND_I64 */ |
| 821, |
| /* ATOMIC_LOAD_NAND_I64_POSTRA */ |
| 824, |
| /* ATOMIC_LOAD_NAND_I8 */ |
| 827, |
| /* ATOMIC_LOAD_NAND_I8_POSTRA */ |
| 830, |
| /* ATOMIC_LOAD_OR_I16 */ |
| 836, |
| /* ATOMIC_LOAD_OR_I16_POSTRA */ |
| 839, |
| /* ATOMIC_LOAD_OR_I32 */ |
| 845, |
| /* ATOMIC_LOAD_OR_I32_POSTRA */ |
| 848, |
| /* ATOMIC_LOAD_OR_I64 */ |
| 851, |
| /* ATOMIC_LOAD_OR_I64_POSTRA */ |
| 854, |
| /* ATOMIC_LOAD_OR_I8 */ |
| 857, |
| /* ATOMIC_LOAD_OR_I8_POSTRA */ |
| 860, |
| /* ATOMIC_LOAD_SUB_I16 */ |
| 866, |
| /* ATOMIC_LOAD_SUB_I16_POSTRA */ |
| 869, |
| /* ATOMIC_LOAD_SUB_I32 */ |
| 875, |
| /* ATOMIC_LOAD_SUB_I32_POSTRA */ |
| 878, |
| /* ATOMIC_LOAD_SUB_I64 */ |
| 881, |
| /* ATOMIC_LOAD_SUB_I64_POSTRA */ |
| 884, |
| /* ATOMIC_LOAD_SUB_I8 */ |
| 887, |
| /* ATOMIC_LOAD_SUB_I8_POSTRA */ |
| 890, |
| /* ATOMIC_LOAD_UMAX_I16 */ |
| 896, |
| /* ATOMIC_LOAD_UMAX_I16_POSTRA */ |
| 899, |
| /* ATOMIC_LOAD_UMAX_I32 */ |
| 905, |
| /* ATOMIC_LOAD_UMAX_I32_POSTRA */ |
| 908, |
| /* ATOMIC_LOAD_UMAX_I64 */ |
| 911, |
| /* ATOMIC_LOAD_UMAX_I64_POSTRA */ |
| 914, |
| /* ATOMIC_LOAD_UMAX_I8 */ |
| 917, |
| /* ATOMIC_LOAD_UMAX_I8_POSTRA */ |
| 920, |
| /* ATOMIC_LOAD_UMIN_I16 */ |
| 926, |
| /* ATOMIC_LOAD_UMIN_I16_POSTRA */ |
| 929, |
| /* ATOMIC_LOAD_UMIN_I32 */ |
| 935, |
| /* ATOMIC_LOAD_UMIN_I32_POSTRA */ |
| 938, |
| /* ATOMIC_LOAD_UMIN_I64 */ |
| 941, |
| /* ATOMIC_LOAD_UMIN_I64_POSTRA */ |
| 944, |
| /* ATOMIC_LOAD_UMIN_I8 */ |
| 947, |
| /* ATOMIC_LOAD_UMIN_I8_POSTRA */ |
| 950, |
| /* ATOMIC_LOAD_XOR_I16 */ |
| 956, |
| /* ATOMIC_LOAD_XOR_I16_POSTRA */ |
| 959, |
| /* ATOMIC_LOAD_XOR_I32 */ |
| 965, |
| /* ATOMIC_LOAD_XOR_I32_POSTRA */ |
| 968, |
| /* ATOMIC_LOAD_XOR_I64 */ |
| 971, |
| /* ATOMIC_LOAD_XOR_I64_POSTRA */ |
| 974, |
| /* ATOMIC_LOAD_XOR_I8 */ |
| 977, |
| /* ATOMIC_LOAD_XOR_I8_POSTRA */ |
| 980, |
| /* ATOMIC_SWAP_I16 */ |
| 986, |
| /* ATOMIC_SWAP_I16_POSTRA */ |
| 989, |
| /* ATOMIC_SWAP_I32 */ |
| 995, |
| /* ATOMIC_SWAP_I32_POSTRA */ |
| 998, |
| /* ATOMIC_SWAP_I64 */ |
| 1001, |
| /* ATOMIC_SWAP_I64_POSTRA */ |
| 1004, |
| /* ATOMIC_SWAP_I8 */ |
| 1007, |
| /* ATOMIC_SWAP_I8_POSTRA */ |
| 1010, |
| /* B */ |
| 1016, |
| /* BAL_BR */ |
| 1017, |
| /* BAL_BR_MM */ |
| 1018, |
| /* BEQLImmMacro */ |
| 1019, |
| /* BGE */ |
| 1022, |
| /* BGEImmMacro */ |
| 1025, |
| /* BGEL */ |
| 1028, |
| /* BGELImmMacro */ |
| 1031, |
| /* BGEU */ |
| 1034, |
| /* BGEUImmMacro */ |
| 1037, |
| /* BGEUL */ |
| 1040, |
| /* BGEULImmMacro */ |
| 1043, |
| /* BGT */ |
| 1046, |
| /* BGTImmMacro */ |
| 1049, |
| /* BGTL */ |
| 1052, |
| /* BGTLImmMacro */ |
| 1055, |
| /* BGTU */ |
| 1058, |
| /* BGTUImmMacro */ |
| 1061, |
| /* BGTUL */ |
| 1064, |
| /* BGTULImmMacro */ |
| 1067, |
| /* BLE */ |
| 1070, |
| /* BLEImmMacro */ |
| 1073, |
| /* BLEL */ |
| 1076, |
| /* BLELImmMacro */ |
| 1079, |
| /* BLEU */ |
| 1082, |
| /* BLEUImmMacro */ |
| 1085, |
| /* BLEUL */ |
| 1088, |
| /* BLEULImmMacro */ |
| 1091, |
| /* BLT */ |
| 1094, |
| /* BLTImmMacro */ |
| 1097, |
| /* BLTL */ |
| 1100, |
| /* BLTLImmMacro */ |
| 1103, |
| /* BLTU */ |
| 1106, |
| /* BLTUImmMacro */ |
| 1109, |
| /* BLTUL */ |
| 1112, |
| /* BLTULImmMacro */ |
| 1115, |
| /* BNELImmMacro */ |
| 1118, |
| /* BPOSGE32_PSEUDO */ |
| 1121, |
| /* BSEL_D_PSEUDO */ |
| 1122, |
| /* BSEL_FD_PSEUDO */ |
| 1126, |
| /* BSEL_FW_PSEUDO */ |
| 1130, |
| /* BSEL_H_PSEUDO */ |
| 1134, |
| /* BSEL_W_PSEUDO */ |
| 1138, |
| /* B_MM */ |
| 1142, |
| /* B_MMR6_Pseudo */ |
| 1143, |
| /* B_MM_Pseudo */ |
| 1144, |
| /* BeqImm */ |
| 1145, |
| /* BneImm */ |
| 1148, |
| /* BteqzT8CmpX16 */ |
| 1151, |
| /* BteqzT8CmpiX16 */ |
| 1154, |
| /* BteqzT8SltX16 */ |
| 1157, |
| /* BteqzT8SltiX16 */ |
| 1160, |
| /* BteqzT8SltiuX16 */ |
| 1163, |
| /* BteqzT8SltuX16 */ |
| 1166, |
| /* BtnezT8CmpX16 */ |
| 1169, |
| /* BtnezT8CmpiX16 */ |
| 1172, |
| /* BtnezT8SltX16 */ |
| 1175, |
| /* BtnezT8SltiX16 */ |
| 1178, |
| /* BtnezT8SltiuX16 */ |
| 1181, |
| /* BtnezT8SltuX16 */ |
| 1184, |
| /* BuildPairF64 */ |
| 1187, |
| /* BuildPairF64_64 */ |
| 1190, |
| /* CFTC1 */ |
| 1193, |
| /* CONSTPOOL_ENTRY */ |
| 1195, |
| /* COPY_FD_PSEUDO */ |
| 1198, |
| /* COPY_FW_PSEUDO */ |
| 1201, |
| /* CTTC1 */ |
| 1204, |
| /* Constant32 */ |
| 1206, |
| /* DMULImmMacro */ |
| 1207, |
| /* DMULMacro */ |
| 1210, |
| /* DMULOMacro */ |
| 1213, |
| /* DMULOUMacro */ |
| 1216, |
| /* DROL */ |
| 1219, |
| /* DROLImm */ |
| 1222, |
| /* DROR */ |
| 1225, |
| /* DRORImm */ |
| 1228, |
| /* DSDivIMacro */ |
| 1231, |
| /* DSDivMacro */ |
| 1234, |
| /* DSRemIMacro */ |
| 1237, |
| /* DSRemMacro */ |
| 1240, |
| /* DUDivIMacro */ |
| 1243, |
| /* DUDivMacro */ |
| 1246, |
| /* DURemIMacro */ |
| 1249, |
| /* DURemMacro */ |
| 1252, |
| /* ERet */ |
| 1255, |
| /* ExtractElementF64 */ |
| 1255, |
| /* ExtractElementF64_64 */ |
| 1258, |
| /* FABS_D */ |
| 1261, |
| /* FABS_W */ |
| 1263, |
| /* FEXP2_D_1_PSEUDO */ |
| 1265, |
| /* FEXP2_W_1_PSEUDO */ |
| 1267, |
| /* FILL_FD_PSEUDO */ |
| 1269, |
| /* FILL_FW_PSEUDO */ |
| 1271, |
| /* GotPrologue16 */ |
| 1273, |
| /* INSERT_B_VIDX64_PSEUDO */ |
| 1277, |
| /* INSERT_B_VIDX_PSEUDO */ |
| 1281, |
| /* INSERT_D_VIDX64_PSEUDO */ |
| 1285, |
| /* INSERT_D_VIDX_PSEUDO */ |
| 1289, |
| /* INSERT_FD_PSEUDO */ |
| 1293, |
| /* INSERT_FD_VIDX64_PSEUDO */ |
| 1297, |
| /* INSERT_FD_VIDX_PSEUDO */ |
| 1301, |
| /* INSERT_FW_PSEUDO */ |
| 1305, |
| /* INSERT_FW_VIDX64_PSEUDO */ |
| 1309, |
| /* INSERT_FW_VIDX_PSEUDO */ |
| 1313, |
| /* INSERT_H_VIDX64_PSEUDO */ |
| 1317, |
| /* INSERT_H_VIDX_PSEUDO */ |
| 1321, |
| /* INSERT_W_VIDX64_PSEUDO */ |
| 1325, |
| /* INSERT_W_VIDX_PSEUDO */ |
| 1329, |
| /* JALR64Pseudo */ |
| 1333, |
| /* JALRHB64Pseudo */ |
| 1334, |
| /* JALRHBPseudo */ |
| 1335, |
| /* JALRPseudo */ |
| 1336, |
| /* JAL_MMR6 */ |
| 1337, |
| /* JalOneReg */ |
| 1338, |
| /* JalTwoReg */ |
| 1339, |
| /* LDMacro */ |
| 1341, |
| /* LDR_D */ |
| 1344, |
| /* LDR_W */ |
| 1347, |
| /* LD_F16 */ |
| 1350, |
| /* LOAD_ACC128 */ |
| 1353, |
| /* LOAD_ACC64 */ |
| 1356, |
| /* LOAD_ACC64DSP */ |
| 1359, |
| /* LOAD_CCOND_DSP */ |
| 1362, |
| /* LONG_BRANCH_ADDiu */ |
| 1365, |
| /* LONG_BRANCH_ADDiu2Op */ |
| 1369, |
| /* LONG_BRANCH_DADDiu */ |
| 1372, |
| /* LONG_BRANCH_DADDiu2Op */ |
| 1376, |
| /* LONG_BRANCH_LUi */ |
| 1379, |
| /* LONG_BRANCH_LUi2Op */ |
| 1382, |
| /* LONG_BRANCH_LUi2Op_64 */ |
| 1384, |
| /* LWM_MM */ |
| 1386, |
| /* LoadAddrImm32 */ |
| 1389, |
| /* LoadAddrImm64 */ |
| 1391, |
| /* LoadAddrReg32 */ |
| 1393, |
| /* LoadAddrReg64 */ |
| 1396, |
| /* LoadImm32 */ |
| 1399, |
| /* LoadImm64 */ |
| 1401, |
| /* LoadImmDoubleFGR */ |
| 1403, |
| /* LoadImmDoubleFGR_32 */ |
| 1405, |
| /* LoadImmDoubleGPR */ |
| 1407, |
| /* LoadImmSingleFGR */ |
| 1409, |
| /* LoadImmSingleGPR */ |
| 1411, |
| /* LwConstant32 */ |
| 1413, |
| /* MFTACX */ |
| 1416, |
| /* MFTC0 */ |
| 1418, |
| /* MFTC1 */ |
| 1421, |
| /* MFTDSP */ |
| 1423, |
| /* MFTGPR */ |
| 1424, |
| /* MFTHC1 */ |
| 1427, |
| /* MFTHI */ |
| 1429, |
| /* MFTLO */ |
| 1431, |
| /* MIPSeh_return32 */ |
| 1433, |
| /* MIPSeh_return64 */ |
| 1435, |
| /* MSA_FP_EXTEND_D_PSEUDO */ |
| 1437, |
| /* MSA_FP_EXTEND_W_PSEUDO */ |
| 1439, |
| /* MSA_FP_ROUND_D_PSEUDO */ |
| 1441, |
| /* MSA_FP_ROUND_W_PSEUDO */ |
| 1443, |
| /* MTTACX */ |
| 1445, |
| /* MTTC0 */ |
| 1447, |
| /* MTTC1 */ |
| 1450, |
| /* MTTDSP */ |
| 1452, |
| /* MTTGPR */ |
| 1453, |
| /* MTTHC1 */ |
| 1455, |
| /* MTTHI */ |
| 1457, |
| /* MTTLO */ |
| 1459, |
| /* MULImmMacro */ |
| 1461, |
| /* MULOMacro */ |
| 1464, |
| /* MULOUMacro */ |
| 1467, |
| /* MultRxRy16 */ |
| 1470, |
| /* MultRxRyRz16 */ |
| 1472, |
| /* MultuRxRy16 */ |
| 1475, |
| /* MultuRxRyRz16 */ |
| 1477, |
| /* NOP */ |
| 1480, |
| /* NORImm */ |
| 1480, |
| /* NORImm64 */ |
| 1483, |
| /* NOR_V_D_PSEUDO */ |
| 1486, |
| /* NOR_V_H_PSEUDO */ |
| 1489, |
| /* NOR_V_W_PSEUDO */ |
| 1492, |
| /* OR_V_D_PSEUDO */ |
| 1495, |
| /* OR_V_H_PSEUDO */ |
| 1498, |
| /* OR_V_W_PSEUDO */ |
| 1501, |
| /* PseudoCMPU_EQ_QB */ |
| 1504, |
| /* PseudoCMPU_LE_QB */ |
| 1507, |
| /* PseudoCMPU_LT_QB */ |
| 1510, |
| /* PseudoCMP_EQ_PH */ |
| 1513, |
| /* PseudoCMP_LE_PH */ |
| 1516, |
| /* PseudoCMP_LT_PH */ |
| 1519, |
| /* PseudoCVT_D32_W */ |
| 1522, |
| /* PseudoCVT_D64_L */ |
| 1524, |
| /* PseudoCVT_D64_W */ |
| 1526, |
| /* PseudoCVT_S_L */ |
| 1528, |
| /* PseudoCVT_S_W */ |
| 1530, |
| /* PseudoDMULT */ |
| 1532, |
| /* PseudoDMULTu */ |
| 1535, |
| /* PseudoDSDIV */ |
| 1538, |
| /* PseudoDUDIV */ |
| 1541, |
| /* PseudoD_SELECT_I */ |
| 1544, |
| /* PseudoD_SELECT_I64 */ |
| 1551, |
| /* PseudoIndirectBranch */ |
| 1558, |
| /* PseudoIndirectBranch64 */ |
| 1559, |
| /* PseudoIndirectBranch64R6 */ |
| 1560, |
| /* PseudoIndirectBranchR6 */ |
| 1561, |
| /* PseudoIndirectBranch_MM */ |
| 1562, |
| /* PseudoIndirectBranch_MMR6 */ |
| 1563, |
| /* PseudoIndirectHazardBranch */ |
| 1564, |
| /* PseudoIndirectHazardBranch64 */ |
| 1565, |
| /* PseudoIndrectHazardBranch64R6 */ |
| 1566, |
| /* PseudoIndrectHazardBranchR6 */ |
| 1567, |
| /* PseudoMADD */ |
| 1568, |
| /* PseudoMADDU */ |
| 1572, |
| /* PseudoMADDU_MM */ |
| 1576, |
| /* PseudoMADD_MM */ |
| 1580, |
| /* PseudoMFHI */ |
| 1584, |
| /* PseudoMFHI64 */ |
| 1586, |
| /* PseudoMFHI_MM */ |
| 1588, |
| /* PseudoMFLO */ |
| 1590, |
| /* PseudoMFLO64 */ |
| 1592, |
| /* PseudoMFLO_MM */ |
| 1594, |
| /* PseudoMSUB */ |
| 1596, |
| /* PseudoMSUBU */ |
| 1600, |
| /* PseudoMSUBU_MM */ |
| 1604, |
| /* PseudoMSUB_MM */ |
| 1608, |
| /* PseudoMTLOHI */ |
| 1612, |
| /* PseudoMTLOHI64 */ |
| 1615, |
| /* PseudoMTLOHI_DSP */ |
| 1618, |
| /* PseudoMTLOHI_MM */ |
| 1621, |
| /* PseudoMULT */ |
| 1624, |
| /* PseudoMULT_MM */ |
| 1627, |
| /* PseudoMULTu */ |
| 1630, |
| /* PseudoMULTu_MM */ |
| 1633, |
| /* PseudoPICK_PH */ |
| 1636, |
| /* PseudoPICK_QB */ |
| 1640, |
| /* PseudoReturn */ |
| 1644, |
| /* PseudoReturn64 */ |
| 1645, |
| /* PseudoSDIV */ |
| 1646, |
| /* PseudoSELECTFP_F_D32 */ |
| 1649, |
| /* PseudoSELECTFP_F_D64 */ |
| 1653, |
| /* PseudoSELECTFP_F_I */ |
| 1657, |
| /* PseudoSELECTFP_F_I64 */ |
| 1661, |
| /* PseudoSELECTFP_F_S */ |
| 1665, |
| /* PseudoSELECTFP_T_D32 */ |
| 1669, |
| /* PseudoSELECTFP_T_D64 */ |
| 1673, |
| /* PseudoSELECTFP_T_I */ |
| 1677, |
| /* PseudoSELECTFP_T_I64 */ |
| 1681, |
| /* PseudoSELECTFP_T_S */ |
| 1685, |
| /* PseudoSELECT_D32 */ |
| 1689, |
| /* PseudoSELECT_D64 */ |
| 1693, |
| /* PseudoSELECT_I */ |
| 1697, |
| /* PseudoSELECT_I64 */ |
| 1701, |
| /* PseudoSELECT_S */ |
| 1705, |
| /* PseudoTRUNC_W_D */ |
| 1709, |
| /* PseudoTRUNC_W_D32 */ |
| 1712, |
| /* PseudoTRUNC_W_S */ |
| 1715, |
| /* PseudoUDIV */ |
| 1718, |
| /* ROL */ |
| 1721, |
| /* ROLImm */ |
| 1724, |
| /* ROR */ |
| 1727, |
| /* RORImm */ |
| 1730, |
| /* RetRA */ |
| 1733, |
| /* RetRA16 */ |
| 1733, |
| /* SDC1_M1 */ |
| 1733, |
| /* SDIV_MM_Pseudo */ |
| 1736, |
| /* SDMacro */ |
| 1739, |
| /* SDivIMacro */ |
| 1742, |
| /* SDivMacro */ |
| 1745, |
| /* SEQIMacro */ |
| 1748, |
| /* SEQMacro */ |
| 1751, |
| /* SGE */ |
| 1754, |
| /* SGEImm */ |
| 1757, |
| /* SGEImm64 */ |
| 1760, |
| /* SGEU */ |
| 1763, |
| /* SGEUImm */ |
| 1766, |
| /* SGEUImm64 */ |
| 1769, |
| /* SGTImm */ |
| 1772, |
| /* SGTImm64 */ |
| 1775, |
| /* SGTUImm */ |
| 1778, |
| /* SGTUImm64 */ |
| 1781, |
| /* SLE */ |
| 1784, |
| /* SLEImm */ |
| 1787, |
| /* SLEImm64 */ |
| 1790, |
| /* SLEU */ |
| 1793, |
| /* SLEUImm */ |
| 1796, |
| /* SLEUImm64 */ |
| 1799, |
| /* SLTImm64 */ |
| 1802, |
| /* SLTUImm64 */ |
| 1805, |
| /* SNEIMacro */ |
| 1808, |
| /* SNEMacro */ |
| 1811, |
| /* SNZ_B_PSEUDO */ |
| 1814, |
| /* SNZ_D_PSEUDO */ |
| 1816, |
| /* SNZ_H_PSEUDO */ |
| 1818, |
| /* SNZ_V_PSEUDO */ |
| 1820, |
| /* SNZ_W_PSEUDO */ |
| 1822, |
| /* SRemIMacro */ |
| 1824, |
| /* SRemMacro */ |
| 1827, |
| /* STORE_ACC128 */ |
| 1830, |
| /* STORE_ACC64 */ |
| 1833, |
| /* STORE_ACC64DSP */ |
| 1836, |
| /* STORE_CCOND_DSP */ |
| 1839, |
| /* STR_D */ |
| 1842, |
| /* STR_W */ |
| 1845, |
| /* ST_F16 */ |
| 1848, |
| /* SWM_MM */ |
| 1851, |
| /* SZ_B_PSEUDO */ |
| 1854, |
| /* SZ_D_PSEUDO */ |
| 1856, |
| /* SZ_H_PSEUDO */ |
| 1858, |
| /* SZ_V_PSEUDO */ |
| 1860, |
| /* SZ_W_PSEUDO */ |
| 1862, |
| /* SaaAddr */ |
| 1864, |
| /* SaadAddr */ |
| 1867, |
| /* SelBeqZ */ |
| 1870, |
| /* SelBneZ */ |
| 1874, |
| /* SelTBteqZCmp */ |
| 1878, |
| /* SelTBteqZCmpi */ |
| 1883, |
| /* SelTBteqZSlt */ |
| 1888, |
| /* SelTBteqZSlti */ |
| 1893, |
| /* SelTBteqZSltiu */ |
| 1898, |
| /* SelTBteqZSltu */ |
| 1903, |
| /* SelTBtneZCmp */ |
| 1908, |
| /* SelTBtneZCmpi */ |
| 1913, |
| /* SelTBtneZSlt */ |
| 1918, |
| /* SelTBtneZSlti */ |
| 1923, |
| /* SelTBtneZSltiu */ |
| 1928, |
| /* SelTBtneZSltu */ |
| 1933, |
| /* SltCCRxRy16 */ |
| 1938, |
| /* SltiCCRxImmX16 */ |
| 1941, |
| /* SltiuCCRxImmX16 */ |
| 1944, |
| /* SltuCCRxRy16 */ |
| 1947, |
| /* SltuRxRyRz16 */ |
| 1950, |
| /* TAILCALL */ |
| 1953, |
| /* TAILCALL64R6REG */ |
| 1954, |
| /* TAILCALLHB64R6REG */ |
| 1955, |
| /* TAILCALLHBR6REG */ |
| 1956, |
| /* TAILCALLR6REG */ |
| 1957, |
| /* TAILCALLREG */ |
| 1958, |
| /* TAILCALLREG64 */ |
| 1959, |
| /* TAILCALLREGHB */ |
| 1960, |
| /* TAILCALLREGHB64 */ |
| 1961, |
| /* TAILCALLREG_MM */ |
| 1962, |
| /* TAILCALLREG_MMR6 */ |
| 1963, |
| /* TAILCALL_MM */ |
| 1964, |
| /* TAILCALL_MMR6 */ |
| 1965, |
| /* TRAP */ |
| 1966, |
| /* TRAP_MM */ |
| 1966, |
| /* UDIV_MM_Pseudo */ |
| 1966, |
| /* UDivIMacro */ |
| 1969, |
| /* UDivMacro */ |
| 1972, |
| /* URemIMacro */ |
| 1975, |
| /* URemMacro */ |
| 1978, |
| /* Ulh */ |
| 1981, |
| /* Ulhu */ |
| 1984, |
| /* Ulw */ |
| 1987, |
| /* Ush */ |
| 1990, |
| /* Usw */ |
| 1993, |
| /* XOR_V_D_PSEUDO */ |
| 1996, |
| /* XOR_V_H_PSEUDO */ |
| 1999, |
| /* XOR_V_W_PSEUDO */ |
| 2002, |
| /* ABSQ_S_PH */ |
| 2005, |
| /* ABSQ_S_PH_MM */ |
| 2007, |
| /* ABSQ_S_QB */ |
| 2009, |
| /* ABSQ_S_QB_MMR2 */ |
| 2011, |
| /* ABSQ_S_W */ |
| 2013, |
| /* ABSQ_S_W_MM */ |
| 2015, |
| /* ADD */ |
| 2017, |
| /* ADDIUPC */ |
| 2020, |
| /* ADDIUPC_MM */ |
| 2022, |
| /* ADDIUPC_MMR6 */ |
| 2024, |
| /* ADDIUR1SP_MM */ |
| 2026, |
| /* ADDIUR2_MM */ |
| 2028, |
| /* ADDIUS5_MM */ |
| 2031, |
| /* ADDIUSP_MM */ |
| 2034, |
| /* ADDIU_MMR6 */ |
| 2035, |
| /* ADDQH_PH */ |
| 2038, |
| /* ADDQH_PH_MMR2 */ |
| 2041, |
| /* ADDQH_R_PH */ |
| 2044, |
| /* ADDQH_R_PH_MMR2 */ |
| 2047, |
| /* ADDQH_R_W */ |
| 2050, |
| /* ADDQH_R_W_MMR2 */ |
| 2053, |
| /* ADDQH_W */ |
| 2056, |
| /* ADDQH_W_MMR2 */ |
| 2059, |
| /* ADDQ_PH */ |
| 2062, |
| /* ADDQ_PH_MM */ |
| 2065, |
| /* ADDQ_S_PH */ |
| 2068, |
| /* ADDQ_S_PH_MM */ |
| 2071, |
| /* ADDQ_S_W */ |
| 2074, |
| /* ADDQ_S_W_MM */ |
| 2077, |
| /* ADDR_PS64 */ |
| 2080, |
| /* ADDSC */ |
| 2083, |
| /* ADDSC_MM */ |
| 2086, |
| /* ADDS_A_B */ |
| 2089, |
| /* ADDS_A_D */ |
| 2092, |
| /* ADDS_A_H */ |
| 2095, |
| /* ADDS_A_W */ |
| 2098, |
| /* ADDS_S_B */ |
| 2101, |
| /* ADDS_S_D */ |
| 2104, |
| /* ADDS_S_H */ |
| 2107, |
| /* ADDS_S_W */ |
| 2110, |
| /* ADDS_U_B */ |
| 2113, |
| /* ADDS_U_D */ |
| 2116, |
| /* ADDS_U_H */ |
| 2119, |
| /* ADDS_U_W */ |
| 2122, |
| /* ADDU16_MM */ |
| 2125, |
| /* ADDU16_MMR6 */ |
| 2128, |
| /* ADDUH_QB */ |
| 2131, |
| /* ADDUH_QB_MMR2 */ |
| 2134, |
| /* ADDUH_R_QB */ |
| 2137, |
| /* ADDUH_R_QB_MMR2 */ |
| 2140, |
| /* ADDU_MMR6 */ |
| 2143, |
| /* ADDU_PH */ |
| 2146, |
| /* ADDU_PH_MMR2 */ |
| 2149, |
| /* ADDU_QB */ |
| 2152, |
| /* ADDU_QB_MM */ |
| 2155, |
| /* ADDU_S_PH */ |
| 2158, |
| /* ADDU_S_PH_MMR2 */ |
| 2161, |
| /* ADDU_S_QB */ |
| 2164, |
| /* ADDU_S_QB_MM */ |
| 2167, |
| /* ADDVI_B */ |
| 2170, |
| /* ADDVI_D */ |
| 2173, |
| /* ADDVI_H */ |
| 2176, |
| /* ADDVI_W */ |
| 2179, |
| /* ADDV_B */ |
| 2182, |
| /* ADDV_D */ |
| 2185, |
| /* ADDV_H */ |
| 2188, |
| /* ADDV_W */ |
| 2191, |
| /* ADDWC */ |
| 2194, |
| /* ADDWC_MM */ |
| 2197, |
| /* ADD_A_B */ |
| 2200, |
| /* ADD_A_D */ |
| 2203, |
| /* ADD_A_H */ |
| 2206, |
| /* ADD_A_W */ |
| 2209, |
| /* ADD_MM */ |
| 2212, |
| /* ADD_MMR6 */ |
| 2215, |
| /* ADDi */ |
| 2218, |
| /* ADDi_MM */ |
| 2221, |
| /* ADDiu */ |
| 2224, |
| /* ADDiu_MM */ |
| 2227, |
| /* ADDu */ |
| 2230, |
| /* ADDu_MM */ |
| 2233, |
| /* ALIGN */ |
| 2236, |
| /* ALIGN_MMR6 */ |
| 2240, |
| /* ALUIPC */ |
| 2244, |
| /* ALUIPC_MMR6 */ |
| 2246, |
| /* AND */ |
| 2248, |
| /* AND16_MM */ |
| 2251, |
| /* AND16_MMR6 */ |
| 2254, |
| /* AND64 */ |
| 2257, |
| /* ANDI16_MM */ |
| 2260, |
| /* ANDI16_MMR6 */ |
| 2263, |
| /* ANDI_B */ |
| 2266, |
| /* ANDI_MMR6 */ |
| 2269, |
| /* AND_MM */ |
| 2272, |
| /* AND_MMR6 */ |
| 2275, |
| /* AND_V */ |
| 2278, |
| /* ANDi */ |
| 2281, |
| /* ANDi64 */ |
| 2284, |
| /* ANDi_MM */ |
| 2287, |
| /* APPEND */ |
| 2290, |
| /* APPEND_MMR2 */ |
| 2294, |
| /* ASUB_S_B */ |
| 2298, |
| /* ASUB_S_D */ |
| 2301, |
| /* ASUB_S_H */ |
| 2304, |
| /* ASUB_S_W */ |
| 2307, |
| /* ASUB_U_B */ |
| 2310, |
| /* ASUB_U_D */ |
| 2313, |
| /* ASUB_U_H */ |
| 2316, |
| /* ASUB_U_W */ |
| 2319, |
| /* AUI */ |
| 2322, |
| /* AUIPC */ |
| 2325, |
| /* AUIPC_MMR6 */ |
| 2327, |
| /* AUI_MMR6 */ |
| 2329, |
| /* AVER_S_B */ |
| 2332, |
| /* AVER_S_D */ |
| 2335, |
| /* AVER_S_H */ |
| 2338, |
| /* AVER_S_W */ |
| 2341, |
| /* AVER_U_B */ |
| 2344, |
| /* AVER_U_D */ |
| 2347, |
| /* AVER_U_H */ |
| 2350, |
| /* AVER_U_W */ |
| 2353, |
| /* AVE_S_B */ |
| 2356, |
| /* AVE_S_D */ |
| 2359, |
| /* AVE_S_H */ |
| 2362, |
| /* AVE_S_W */ |
| 2365, |
| /* AVE_U_B */ |
| 2368, |
| /* AVE_U_D */ |
| 2371, |
| /* AVE_U_H */ |
| 2374, |
| /* AVE_U_W */ |
| 2377, |
| /* AddiuRxImmX16 */ |
| 2380, |
| /* AddiuRxPcImmX16 */ |
| 2382, |
| /* AddiuRxRxImm16 */ |
| 2384, |
| /* AddiuRxRxImmX16 */ |
| 2387, |
| /* AddiuRxRyOffMemX16 */ |
| 2390, |
| /* AddiuSpImm16 */ |
| 2393, |
| /* AddiuSpImmX16 */ |
| 2394, |
| /* AdduRxRyRz16 */ |
| 2395, |
| /* AndRxRxRy16 */ |
| 2398, |
| /* B16_MM */ |
| 2401, |
| /* BADDu */ |
| 2402, |
| /* BAL */ |
| 2405, |
| /* BALC */ |
| 2406, |
| /* BALC_MMR6 */ |
| 2407, |
| /* BALIGN */ |
| 2408, |
| /* BALIGN_MMR2 */ |
| 2412, |
| /* BBIT0 */ |
| 2416, |
| /* BBIT032 */ |
| 2419, |
| /* BBIT1 */ |
| 2422, |
| /* BBIT132 */ |
| 2425, |
| /* BC */ |
| 2428, |
| /* BC16_MMR6 */ |
| 2429, |
| /* BC1EQZ */ |
| 2430, |
| /* BC1EQZC_MMR6 */ |
| 2432, |
| /* BC1F */ |
| 2434, |
| /* BC1FL */ |
| 2436, |
| /* BC1F_MM */ |
| 2438, |
| /* BC1NEZ */ |
| 2440, |
| /* BC1NEZC_MMR6 */ |
| 2442, |
| /* BC1T */ |
| 2444, |
| /* BC1TL */ |
| 2446, |
| /* BC1T_MM */ |
| 2448, |
| /* BC2EQZ */ |
| 2450, |
| /* BC2EQZC_MMR6 */ |
| 2452, |
| /* BC2NEZ */ |
| 2454, |
| /* BC2NEZC_MMR6 */ |
| 2456, |
| /* BCLRI_B */ |
| 2458, |
| /* BCLRI_D */ |
| 2461, |
| /* BCLRI_H */ |
| 2464, |
| /* BCLRI_W */ |
| 2467, |
| /* BCLR_B */ |
| 2470, |
| /* BCLR_D */ |
| 2473, |
| /* BCLR_H */ |
| 2476, |
| /* BCLR_W */ |
| 2479, |
| /* BC_MMR6 */ |
| 2482, |
| /* BEQ */ |
| 2483, |
| /* BEQ64 */ |
| 2486, |
| /* BEQC */ |
| 2489, |
| /* BEQC64 */ |
| 2492, |
| /* BEQC_MMR6 */ |
| 2495, |
| /* BEQL */ |
| 2498, |
| /* BEQZ16_MM */ |
| 2501, |
| /* BEQZALC */ |
| 2503, |
| /* BEQZALC_MMR6 */ |
| 2505, |
| /* BEQZC */ |
| 2507, |
| /* BEQZC16_MMR6 */ |
| 2509, |
| /* BEQZC64 */ |
| 2511, |
| /* BEQZC_MM */ |
| 2513, |
| /* BEQZC_MMR6 */ |
| 2515, |
| /* BEQ_MM */ |
| 2517, |
| /* BGEC */ |
| 2520, |
| /* BGEC64 */ |
| 2523, |
| /* BGEC_MMR6 */ |
| 2526, |
| /* BGEUC */ |
| 2529, |
| /* BGEUC64 */ |
| 2532, |
| /* BGEUC_MMR6 */ |
| 2535, |
| /* BGEZ */ |
| 2538, |
| /* BGEZ64 */ |
| 2540, |
| /* BGEZAL */ |
| 2542, |
| /* BGEZALC */ |
| 2544, |
| /* BGEZALC_MMR6 */ |
| 2546, |
| /* BGEZALL */ |
| 2548, |
| /* BGEZALS_MM */ |
| 2550, |
| /* BGEZAL_MM */ |
| 2552, |
| /* BGEZC */ |
| 2554, |
| /* BGEZC64 */ |
| 2556, |
| /* BGEZC_MMR6 */ |
| 2558, |
| /* BGEZL */ |
| 2560, |
| /* BGEZ_MM */ |
| 2562, |
| /* BGTZ */ |
| 2564, |
| /* BGTZ64 */ |
| 2566, |
| /* BGTZALC */ |
| 2568, |
| /* BGTZALC_MMR6 */ |
| 2570, |
| /* BGTZC */ |
| 2572, |
| /* BGTZC64 */ |
| 2574, |
| /* BGTZC_MMR6 */ |
| 2576, |
| /* BGTZL */ |
| 2578, |
| /* BGTZ_MM */ |
| 2580, |
| /* BINSLI_B */ |
| 2582, |
| /* BINSLI_D */ |
| 2586, |
| /* BINSLI_H */ |
| 2590, |
| /* BINSLI_W */ |
| 2594, |
| /* BINSL_B */ |
| 2598, |
| /* BINSL_D */ |
| 2602, |
| /* BINSL_H */ |
| 2606, |
| /* BINSL_W */ |
| 2610, |
| /* BINSRI_B */ |
| 2614, |
| /* BINSRI_D */ |
| 2618, |
| /* BINSRI_H */ |
| 2622, |
| /* BINSRI_W */ |
| 2626, |
| /* BINSR_B */ |
| 2630, |
| /* BINSR_D */ |
| 2634, |
| /* BINSR_H */ |
| 2638, |
| /* BINSR_W */ |
| 2642, |
| /* BITREV */ |
| 2646, |
| /* BITREV_MM */ |
| 2648, |
| /* BITSWAP */ |
| 2650, |
| /* BITSWAP_MMR6 */ |
| 2652, |
| /* BLEZ */ |
| 2654, |
| /* BLEZ64 */ |
| 2656, |
| /* BLEZALC */ |
| 2658, |
| /* BLEZALC_MMR6 */ |
| 2660, |
| /* BLEZC */ |
| 2662, |
| /* BLEZC64 */ |
| 2664, |
| /* BLEZC_MMR6 */ |
| 2666, |
| /* BLEZL */ |
| 2668, |
| /* BLEZ_MM */ |
| 2670, |
| /* BLTC */ |
| 2672, |
| /* BLTC64 */ |
| 2675, |
| /* BLTC_MMR6 */ |
| 2678, |
| /* BLTUC */ |
| 2681, |
| /* BLTUC64 */ |
| 2684, |
| /* BLTUC_MMR6 */ |
| 2687, |
| /* BLTZ */ |
| 2690, |
| /* BLTZ64 */ |
| 2692, |
| /* BLTZAL */ |
| 2694, |
| /* BLTZALC */ |
| 2696, |
| /* BLTZALC_MMR6 */ |
| 2698, |
| /* BLTZALL */ |
| 2700, |
| /* BLTZALS_MM */ |
| 2702, |
| /* BLTZAL_MM */ |
| 2704, |
| /* BLTZC */ |
| 2706, |
| /* BLTZC64 */ |
| 2708, |
| /* BLTZC_MMR6 */ |
| 2710, |
| /* BLTZL */ |
| 2712, |
| /* BLTZ_MM */ |
| 2714, |
| /* BMNZI_B */ |
| 2716, |
| /* BMNZ_V */ |
| 2720, |
| /* BMZI_B */ |
| 2724, |
| /* BMZ_V */ |
| 2728, |
| /* BNE */ |
| 2732, |
| /* BNE64 */ |
| 2735, |
| /* BNEC */ |
| 2738, |
| /* BNEC64 */ |
| 2741, |
| /* BNEC_MMR6 */ |
| 2744, |
| /* BNEGI_B */ |
| 2747, |
| /* BNEGI_D */ |
| 2750, |
| /* BNEGI_H */ |
| 2753, |
| /* BNEGI_W */ |
| 2756, |
| /* BNEG_B */ |
| 2759, |
| /* BNEG_D */ |
| 2762, |
| /* BNEG_H */ |
| 2765, |
| /* BNEG_W */ |
| 2768, |
| /* BNEL */ |
| 2771, |
| /* BNEZ16_MM */ |
| 2774, |
| /* BNEZALC */ |
| 2776, |
| /* BNEZALC_MMR6 */ |
| 2778, |
| /* BNEZC */ |
| 2780, |
| /* BNEZC16_MMR6 */ |
| 2782, |
| /* BNEZC64 */ |
| 2784, |
| /* BNEZC_MM */ |
| 2786, |
| /* BNEZC_MMR6 */ |
| 2788, |
| /* BNE_MM */ |
| 2790, |
| /* BNVC */ |
| 2793, |
| /* BNVC_MMR6 */ |
| 2796, |
| /* BNZ_B */ |
| 2799, |
| /* BNZ_D */ |
| 2801, |
| /* BNZ_H */ |
| 2803, |
| /* BNZ_V */ |
| 2805, |
| /* BNZ_W */ |
| 2807, |
| /* BOVC */ |
| 2809, |
| /* BOVC_MMR6 */ |
| 2812, |
| /* BPOSGE32 */ |
| 2815, |
| /* BPOSGE32C_MMR3 */ |
| 2816, |
| /* BPOSGE32_MM */ |
| 2817, |
| /* BREAK */ |
| 2818, |
| /* BREAK16_MM */ |
| 2820, |
| /* BREAK16_MMR6 */ |
| 2821, |
| /* BREAK_MM */ |
| 2822, |
| /* BREAK_MMR6 */ |
| 2824, |
| /* BSELI_B */ |
| 2826, |
| /* BSEL_V */ |
| 2830, |
| /* BSETI_B */ |
| 2834, |
| /* BSETI_D */ |
| 2837, |
| /* BSETI_H */ |
| 2840, |
| /* BSETI_W */ |
| 2843, |
| /* BSET_B */ |
| 2846, |
| /* BSET_D */ |
| 2849, |
| /* BSET_H */ |
| 2852, |
| /* BSET_W */ |
| 2855, |
| /* BZ_B */ |
| 2858, |
| /* BZ_D */ |
| 2860, |
| /* BZ_H */ |
| 2862, |
| /* BZ_V */ |
| 2864, |
| /* BZ_W */ |
| 2866, |
| /* BeqzRxImm16 */ |
| 2868, |
| /* BeqzRxImmX16 */ |
| 2870, |
| /* Bimm16 */ |
| 2872, |
| /* BimmX16 */ |
| 2873, |
| /* BnezRxImm16 */ |
| 2874, |
| /* BnezRxImmX16 */ |
| 2876, |
| /* Break16 */ |
| 2878, |
| /* Bteqz16 */ |
| 2878, |
| /* BteqzX16 */ |
| 2879, |
| /* Btnez16 */ |
| 2880, |
| /* BtnezX16 */ |
| 2881, |
| /* CACHE */ |
| 2882, |
| /* CACHEE */ |
| 2885, |
| /* CACHEE_MM */ |
| 2888, |
| /* CACHE_MM */ |
| 2891, |
| /* CACHE_MMR6 */ |
| 2894, |
| /* CACHE_R6 */ |
| 2897, |
| /* CEIL_L_D64 */ |
| 2900, |
| /* CEIL_L_D_MMR6 */ |
| 2902, |
| /* CEIL_L_S */ |
| 2904, |
| /* CEIL_L_S_MMR6 */ |
| 2906, |
| /* CEIL_W_D32 */ |
| 2908, |
| /* CEIL_W_D64 */ |
| 2910, |
| /* CEIL_W_D_MMR6 */ |
| 2912, |
| /* CEIL_W_MM */ |
| 2914, |
| /* CEIL_W_S */ |
| 2916, |
| /* CEIL_W_S_MM */ |
| 2918, |
| /* CEIL_W_S_MMR6 */ |
| 2920, |
| /* CEQI_B */ |
| 2922, |
| /* CEQI_D */ |
| 2925, |
| /* CEQI_H */ |
| 2928, |
| /* CEQI_W */ |
| 2931, |
| /* CEQ_B */ |
| 2934, |
| /* CEQ_D */ |
| 2937, |
| /* CEQ_H */ |
| 2940, |
| /* CEQ_W */ |
| 2943, |
| /* CFC1 */ |
| 2946, |
| /* CFC1_MM */ |
| 2948, |
| /* CFC2_MM */ |
| 2950, |
| /* CFCMSA */ |
| 2952, |
| /* CINS */ |
| 2954, |
| /* CINS32 */ |
| 2958, |
| /* CINS64_32 */ |
| 2962, |
| /* CINS_i32 */ |
| 2966, |
| /* CLASS_D */ |
| 2970, |
| /* CLASS_D_MMR6 */ |
| 2972, |
| /* CLASS_S */ |
| 2974, |
| /* CLASS_S_MMR6 */ |
| 2976, |
| /* CLEI_S_B */ |
| 2978, |
| /* CLEI_S_D */ |
| 2981, |
| /* CLEI_S_H */ |
| 2984, |
| /* CLEI_S_W */ |
| 2987, |
| /* CLEI_U_B */ |
| 2990, |
| /* CLEI_U_D */ |
| 2993, |
| /* CLEI_U_H */ |
| 2996, |
| /* CLEI_U_W */ |
| 2999, |
| /* CLE_S_B */ |
| 3002, |
| /* CLE_S_D */ |
| 3005, |
| /* CLE_S_H */ |
| 3008, |
| /* CLE_S_W */ |
| 3011, |
| /* CLE_U_B */ |
| 3014, |
| /* CLE_U_D */ |
| 3017, |
| /* CLE_U_H */ |
| 3020, |
| /* CLE_U_W */ |
| 3023, |
| /* CLO */ |
| 3026, |
| /* CLO_MM */ |
| 3028, |
| /* CLO_MMR6 */ |
| 3030, |
| /* CLO_R6 */ |
| 3032, |
| /* CLTI_S_B */ |
| 3034, |
| /* CLTI_S_D */ |
| 3037, |
| /* CLTI_S_H */ |
| 3040, |
| /* CLTI_S_W */ |
| 3043, |
| /* CLTI_U_B */ |
| 3046, |
| /* CLTI_U_D */ |
| 3049, |
| /* CLTI_U_H */ |
| 3052, |
| /* CLTI_U_W */ |
| 3055, |
| /* CLT_S_B */ |
| 3058, |
| /* CLT_S_D */ |
| 3061, |
| /* CLT_S_H */ |
| 3064, |
| /* CLT_S_W */ |
| 3067, |
| /* CLT_U_B */ |
| 3070, |
| /* CLT_U_D */ |
| 3073, |
| /* CLT_U_H */ |
| 3076, |
| /* CLT_U_W */ |
| 3079, |
| /* CLZ */ |
| 3082, |
| /* CLZ_MM */ |
| 3084, |
| /* CLZ_MMR6 */ |
| 3086, |
| /* CLZ_R6 */ |
| 3088, |
| /* CMPGDU_EQ_QB */ |
| 3090, |
| /* CMPGDU_EQ_QB_MMR2 */ |
| 3093, |
| /* CMPGDU_LE_QB */ |
| 3096, |
| /* CMPGDU_LE_QB_MMR2 */ |
| 3099, |
| /* CMPGDU_LT_QB */ |
| 3102, |
| /* CMPGDU_LT_QB_MMR2 */ |
| 3105, |
| /* CMPGU_EQ_QB */ |
| 3108, |
| /* CMPGU_EQ_QB_MM */ |
| 3111, |
| /* CMPGU_LE_QB */ |
| 3114, |
| /* CMPGU_LE_QB_MM */ |
| 3117, |
| /* CMPGU_LT_QB */ |
| 3120, |
| /* CMPGU_LT_QB_MM */ |
| 3123, |
| /* CMPU_EQ_QB */ |
| 3126, |
| /* CMPU_EQ_QB_MM */ |
| 3128, |
| /* CMPU_LE_QB */ |
| 3130, |
| /* CMPU_LE_QB_MM */ |
| 3132, |
| /* CMPU_LT_QB */ |
| 3134, |
| /* CMPU_LT_QB_MM */ |
| 3136, |
| /* CMP_AF_D_MMR6 */ |
| 3138, |
| /* CMP_AF_S_MMR6 */ |
| 3141, |
| /* CMP_EQ_D */ |
| 3144, |
| /* CMP_EQ_D_MMR6 */ |
| 3147, |
| /* CMP_EQ_PH */ |
| 3150, |
| /* CMP_EQ_PH_MM */ |
| 3152, |
| /* CMP_EQ_S */ |
| 3154, |
| /* CMP_EQ_S_MMR6 */ |
| 3157, |
| /* CMP_F_D */ |
| 3160, |
| /* CMP_F_S */ |
| 3163, |
| /* CMP_LE_D */ |
| 3166, |
| /* CMP_LE_D_MMR6 */ |
| 3169, |
| /* CMP_LE_PH */ |
| 3172, |
| /* CMP_LE_PH_MM */ |
| 3174, |
| /* CMP_LE_S */ |
| 3176, |
| /* CMP_LE_S_MMR6 */ |
| 3179, |
| /* CMP_LT_D */ |
| 3182, |
| /* CMP_LT_D_MMR6 */ |
| 3185, |
| /* CMP_LT_PH */ |
| 3188, |
| /* CMP_LT_PH_MM */ |
| 3190, |
| /* CMP_LT_S */ |
| 3192, |
| /* CMP_LT_S_MMR6 */ |
| 3195, |
| /* CMP_SAF_D */ |
| 3198, |
| /* CMP_SAF_D_MMR6 */ |
| 3201, |
| /* CMP_SAF_S */ |
| 3204, |
| /* CMP_SAF_S_MMR6 */ |
| 3207, |
| /* CMP_SEQ_D */ |
| 3210, |
| /* CMP_SEQ_D_MMR6 */ |
| 3213, |
| /* CMP_SEQ_S */ |
| 3216, |
| /* CMP_SEQ_S_MMR6 */ |
| 3219, |
| /* CMP_SLE_D */ |
| 3222, |
| /* CMP_SLE_D_MMR6 */ |
| 3225, |
| /* CMP_SLE_S */ |
| 3228, |
| /* CMP_SLE_S_MMR6 */ |
| 3231, |
| /* CMP_SLT_D */ |
| 3234, |
| /* CMP_SLT_D_MMR6 */ |
| 3237, |
| /* CMP_SLT_S */ |
| 3240, |
| /* CMP_SLT_S_MMR6 */ |
| 3243, |
| /* CMP_SUEQ_D */ |
| 3246, |
| /* CMP_SUEQ_D_MMR6 */ |
| 3249, |
| /* CMP_SUEQ_S */ |
| 3252, |
| /* CMP_SUEQ_S_MMR6 */ |
| 3255, |
| /* CMP_SULE_D */ |
| 3258, |
| /* CMP_SULE_D_MMR6 */ |
| 3261, |
| /* CMP_SULE_S */ |
| 3264, |
| /* CMP_SULE_S_MMR6 */ |
| 3267, |
| /* CMP_SULT_D */ |
| 3270, |
| /* CMP_SULT_D_MMR6 */ |
| 3273, |
| /* CMP_SULT_S */ |
| 3276, |
| /* CMP_SULT_S_MMR6 */ |
| 3279, |
| /* CMP_SUN_D */ |
| 3282, |
| /* CMP_SUN_D_MMR6 */ |
| 3285, |
| /* CMP_SUN_S */ |
| 3288, |
| /* CMP_SUN_S_MMR6 */ |
| 3291, |
| /* CMP_UEQ_D */ |
| 3294, |
| /* CMP_UEQ_D_MMR6 */ |
| 3297, |
| /* CMP_UEQ_S */ |
| 3300, |
| /* CMP_UEQ_S_MMR6 */ |
| 3303, |
| /* CMP_ULE_D */ |
| 3306, |
| /* CMP_ULE_D_MMR6 */ |
| 3309, |
| /* CMP_ULE_S */ |
| 3312, |
| /* CMP_ULE_S_MMR6 */ |
| 3315, |
| /* CMP_ULT_D */ |
| 3318, |
| /* CMP_ULT_D_MMR6 */ |
| 3321, |
| /* CMP_ULT_S */ |
| 3324, |
| /* CMP_ULT_S_MMR6 */ |
| 3327, |
| /* CMP_UN_D */ |
| 3330, |
| /* CMP_UN_D_MMR6 */ |
| 3333, |
| /* CMP_UN_S */ |
| 3336, |
| /* CMP_UN_S_MMR6 */ |
| 3339, |
| /* COPY_S_B */ |
| 3342, |
| /* COPY_S_D */ |
| 3345, |
| /* COPY_S_H */ |
| 3348, |
| /* COPY_S_W */ |
| 3351, |
| /* COPY_U_B */ |
| 3354, |
| /* COPY_U_H */ |
| 3357, |
| /* COPY_U_W */ |
| 3360, |
| /* CRC32B */ |
| 3363, |
| /* CRC32CB */ |
| 3366, |
| /* CRC32CD */ |
| 3369, |
| /* CRC32CH */ |
| 3372, |
| /* CRC32CW */ |
| 3375, |
| /* CRC32D */ |
| 3378, |
| /* CRC32H */ |
| 3381, |
| /* CRC32W */ |
| 3384, |
| /* CTC1 */ |
| 3387, |
| /* CTC1_MM */ |
| 3389, |
| /* CTC2_MM */ |
| 3391, |
| /* CTCMSA */ |
| 3393, |
| /* CVT_D32_S */ |
| 3395, |
| /* CVT_D32_S_MM */ |
| 3397, |
| /* CVT_D32_W */ |
| 3399, |
| /* CVT_D32_W_MM */ |
| 3401, |
| /* CVT_D64_L */ |
| 3403, |
| /* CVT_D64_S */ |
| 3405, |
| /* CVT_D64_S_MM */ |
| 3407, |
| /* CVT_D64_W */ |
| 3409, |
| /* CVT_D64_W_MM */ |
| 3411, |
| /* CVT_D_L_MMR6 */ |
| 3413, |
| /* CVT_L_D64 */ |
| 3415, |
| /* CVT_L_D64_MM */ |
| 3417, |
| /* CVT_L_D_MMR6 */ |
| 3419, |
| /* CVT_L_S */ |
| 3421, |
| /* CVT_L_S_MM */ |
| 3423, |
| /* CVT_L_S_MMR6 */ |
| 3425, |
| /* CVT_PS_PW64 */ |
| 3427, |
| /* CVT_PS_S64 */ |
| 3429, |
| /* CVT_PW_PS64 */ |
| 3432, |
| /* CVT_S_D32 */ |
| 3434, |
| /* CVT_S_D32_MM */ |
| 3436, |
| /* CVT_S_D64 */ |
| 3438, |
| /* CVT_S_D64_MM */ |
| 3440, |
| /* CVT_S_L */ |
| 3442, |
| /* CVT_S_L_MMR6 */ |
| 3444, |
| /* CVT_S_PL64 */ |
| 3446, |
| /* CVT_S_PU64 */ |
| 3448, |
| /* CVT_S_W */ |
| 3450, |
| /* CVT_S_W_MM */ |
| 3452, |
| /* CVT_S_W_MMR6 */ |
| 3454, |
| /* CVT_W_D32 */ |
| 3456, |
| /* CVT_W_D32_MM */ |
| 3458, |
| /* CVT_W_D64 */ |
| 3460, |
| /* CVT_W_D64_MM */ |
| 3462, |
| /* CVT_W_S */ |
| 3464, |
| /* CVT_W_S_MM */ |
| 3466, |
| /* CVT_W_S_MMR6 */ |
| 3468, |
| /* C_EQ_D32 */ |
| 3470, |
| /* C_EQ_D32_MM */ |
| 3473, |
| /* C_EQ_D64 */ |
| 3476, |
| /* C_EQ_D64_MM */ |
| 3479, |
| /* C_EQ_S */ |
| 3482, |
| /* C_EQ_S_MM */ |
| 3485, |
| /* C_F_D32 */ |
| 3488, |
| /* C_F_D32_MM */ |
| 3491, |
| /* C_F_D64 */ |
| 3494, |
| /* C_F_D64_MM */ |
| 3497, |
| /* C_F_S */ |
| 3500, |
| /* C_F_S_MM */ |
| 3503, |
| /* C_LE_D32 */ |
| 3506, |
| /* C_LE_D32_MM */ |
| 3509, |
| /* C_LE_D64 */ |
| 3512, |
| /* C_LE_D64_MM */ |
| 3515, |
| /* C_LE_S */ |
| 3518, |
| /* C_LE_S_MM */ |
| 3521, |
| /* C_LT_D32 */ |
| 3524, |
| /* C_LT_D32_MM */ |
| 3527, |
| /* C_LT_D64 */ |
| 3530, |
| /* C_LT_D64_MM */ |
| 3533, |
| /* C_LT_S */ |
| 3536, |
| /* C_LT_S_MM */ |
| 3539, |
| /* C_NGE_D32 */ |
| 3542, |
| /* C_NGE_D32_MM */ |
| 3545, |
| /* C_NGE_D64 */ |
| 3548, |
| /* C_NGE_D64_MM */ |
| 3551, |
| /* C_NGE_S */ |
| 3554, |
| /* C_NGE_S_MM */ |
| 3557, |
| /* C_NGLE_D32 */ |
| 3560, |
| /* C_NGLE_D32_MM */ |
| 3563, |
| /* C_NGLE_D64 */ |
| 3566, |
| /* C_NGLE_D64_MM */ |
| 3569, |
| /* C_NGLE_S */ |
| 3572, |
| /* C_NGLE_S_MM */ |
| 3575, |
| /* C_NGL_D32 */ |
| 3578, |
| /* C_NGL_D32_MM */ |
| 3581, |
| /* C_NGL_D64 */ |
| 3584, |
| /* C_NGL_D64_MM */ |
| 3587, |
| /* C_NGL_S */ |
| 3590, |
| /* C_NGL_S_MM */ |
| 3593, |
| /* C_NGT_D32 */ |
| 3596, |
| /* C_NGT_D32_MM */ |
| 3599, |
| /* C_NGT_D64 */ |
| 3602, |
| /* C_NGT_D64_MM */ |
| 3605, |
| /* C_NGT_S */ |
| 3608, |
| /* C_NGT_S_MM */ |
| 3611, |
| /* C_OLE_D32 */ |
| 3614, |
| /* C_OLE_D32_MM */ |
| 3617, |
| /* C_OLE_D64 */ |
| 3620, |
| /* C_OLE_D64_MM */ |
| 3623, |
| /* C_OLE_S */ |
| 3626, |
| /* C_OLE_S_MM */ |
| 3629, |
| /* C_OLT_D32 */ |
| 3632, |
| /* C_OLT_D32_MM */ |
| 3635, |
| /* C_OLT_D64 */ |
| 3638, |
| /* C_OLT_D64_MM */ |
| 3641, |
| /* C_OLT_S */ |
| 3644, |
| /* C_OLT_S_MM */ |
| 3647, |
| /* C_SEQ_D32 */ |
| 3650, |
| /* C_SEQ_D32_MM */ |
| 3653, |
| /* C_SEQ_D64 */ |
| 3656, |
| /* C_SEQ_D64_MM */ |
| 3659, |
| /* C_SEQ_S */ |
| 3662, |
| /* C_SEQ_S_MM */ |
| 3665, |
| /* C_SF_D32 */ |
| 3668, |
| /* C_SF_D32_MM */ |
| 3671, |
| /* C_SF_D64 */ |
| 3674, |
| /* C_SF_D64_MM */ |
| 3677, |
| /* C_SF_S */ |
| 3680, |
| /* C_SF_S_MM */ |
| 3683, |
| /* C_UEQ_D32 */ |
| 3686, |
| /* C_UEQ_D32_MM */ |
| 3689, |
| /* C_UEQ_D64 */ |
| 3692, |
| /* C_UEQ_D64_MM */ |
| 3695, |
| /* C_UEQ_S */ |
| 3698, |
| /* C_UEQ_S_MM */ |
| 3701, |
| /* C_ULE_D32 */ |
| 3704, |
| /* C_ULE_D32_MM */ |
| 3707, |
| /* C_ULE_D64 */ |
| 3710, |
| /* C_ULE_D64_MM */ |
| 3713, |
| /* C_ULE_S */ |
| 3716, |
| /* C_ULE_S_MM */ |
| 3719, |
| /* C_ULT_D32 */ |
| 3722, |
| /* C_ULT_D32_MM */ |
| 3725, |
| /* C_ULT_D64 */ |
| 3728, |
| /* C_ULT_D64_MM */ |
| 3731, |
| /* C_ULT_S */ |
| 3734, |
| /* C_ULT_S_MM */ |
| 3737, |
| /* C_UN_D32 */ |
| 3740, |
| /* C_UN_D32_MM */ |
| 3743, |
| /* C_UN_D64 */ |
| 3746, |
| /* C_UN_D64_MM */ |
| 3749, |
| /* C_UN_S */ |
| 3752, |
| /* C_UN_S_MM */ |
| 3755, |
| /* CmpRxRy16 */ |
| 3758, |
| /* CmpiRxImm16 */ |
| 3760, |
| /* CmpiRxImmX16 */ |
| 3762, |
| /* DADD */ |
| 3764, |
| /* DADDi */ |
| 3767, |
| /* DADDiu */ |
| 3770, |
| /* DADDu */ |
| 3773, |
| /* DAHI */ |
| 3776, |
| /* DALIGN */ |
| 3779, |
| /* DATI */ |
| 3783, |
| /* DAUI */ |
| 3786, |
| /* DBITSWAP */ |
| 3789, |
| /* DCLO */ |
| 3791, |
| /* DCLO_R6 */ |
| 3793, |
| /* DCLZ */ |
| 3795, |
| /* DCLZ_R6 */ |
| 3797, |
| /* DDIV */ |
| 3799, |
| /* DDIVU */ |
| 3802, |
| /* DERET */ |
| 3805, |
| /* DERET_MM */ |
| 3805, |
| /* DERET_MMR6 */ |
| 3805, |
| /* DEXT */ |
| 3805, |
| /* DEXT64_32 */ |
| 3809, |
| /* DEXTM */ |
| 3813, |
| /* DEXTU */ |
| 3817, |
| /* DI */ |
| 3821, |
| /* DINS */ |
| 3822, |
| /* DINSM */ |
| 3827, |
| /* DINSU */ |
| 3832, |
| /* DIV */ |
| 3837, |
| /* DIVU */ |
| 3840, |
| /* DIVU_MMR6 */ |
| 3843, |
| /* DIV_MMR6 */ |
| 3846, |
| /* DIV_S_B */ |
| 3849, |
| /* DIV_S_D */ |
| 3852, |
| /* DIV_S_H */ |
| 3855, |
| /* DIV_S_W */ |
| 3858, |
| /* DIV_U_B */ |
| 3861, |
| /* DIV_U_D */ |
| 3864, |
| /* DIV_U_H */ |
| 3867, |
| /* DIV_U_W */ |
| 3870, |
| /* DI_MM */ |
| 3873, |
| /* DI_MMR6 */ |
| 3874, |
| /* DLSA */ |
| 3875, |
| /* DLSA_R6 */ |
| 3879, |
| /* DMFC0 */ |
| 3883, |
| /* DMFC1 */ |
| 3886, |
| /* DMFC2 */ |
| 3888, |
| /* DMFC2_OCTEON */ |
| 3891, |
| /* DMFGC0 */ |
| 3893, |
| /* DMOD */ |
| 3896, |
| /* DMODU */ |
| 3899, |
| /* DMT */ |
| 3902, |
| /* DMTC0 */ |
| 3903, |
| /* DMTC1 */ |
| 3906, |
| /* DMTC2 */ |
| 3908, |
| /* DMTC2_OCTEON */ |
| 3911, |
| /* DMTGC0 */ |
| 3913, |
| /* DMUH */ |
| 3916, |
| /* DMUHU */ |
| 3919, |
| /* DMUL */ |
| 3922, |
| /* DMULT */ |
| 3925, |
| /* DMULTu */ |
| 3927, |
| /* DMULU */ |
| 3929, |
| /* DMUL_R6 */ |
| 3932, |
| /* DOTP_S_D */ |
| 3935, |
| /* DOTP_S_H */ |
| 3938, |
| /* DOTP_S_W */ |
| 3941, |
| /* DOTP_U_D */ |
| 3944, |
| /* DOTP_U_H */ |
| 3947, |
| /* DOTP_U_W */ |
| 3950, |
| /* DPADD_S_D */ |
| 3953, |
| /* DPADD_S_H */ |
| 3957, |
| /* DPADD_S_W */ |
| 3961, |
| /* DPADD_U_D */ |
| 3965, |
| /* DPADD_U_H */ |
| 3969, |
| /* DPADD_U_W */ |
| 3973, |
| /* DPAQX_SA_W_PH */ |
| 3977, |
| /* DPAQX_SA_W_PH_MMR2 */ |
| 3981, |
| /* DPAQX_S_W_PH */ |
| 3985, |
| /* DPAQX_S_W_PH_MMR2 */ |
| 3989, |
| /* DPAQ_SA_L_W */ |
| 3993, |
| /* DPAQ_SA_L_W_MM */ |
| 3997, |
| /* DPAQ_S_W_PH */ |
| 4001, |
| /* DPAQ_S_W_PH_MM */ |
| 4005, |
| /* DPAU_H_QBL */ |
| 4009, |
| /* DPAU_H_QBL_MM */ |
| 4013, |
| /* DPAU_H_QBR */ |
| 4017, |
| /* DPAU_H_QBR_MM */ |
| 4021, |
| /* DPAX_W_PH */ |
| 4025, |
| /* DPAX_W_PH_MMR2 */ |
| 4029, |
| /* DPA_W_PH */ |
| 4033, |
| /* DPA_W_PH_MMR2 */ |
| 4037, |
| /* DPOP */ |
| 4041, |
| /* DPSQX_SA_W_PH */ |
| 4043, |
| /* DPSQX_SA_W_PH_MMR2 */ |
| 4047, |
| /* DPSQX_S_W_PH */ |
| 4051, |
| /* DPSQX_S_W_PH_MMR2 */ |
| 4055, |
| /* DPSQ_SA_L_W */ |
| 4059, |
| /* DPSQ_SA_L_W_MM */ |
| 4063, |
| /* DPSQ_S_W_PH */ |
| 4067, |
| /* DPSQ_S_W_PH_MM */ |
| 4071, |
| /* DPSUB_S_D */ |
| 4075, |
| /* DPSUB_S_H */ |
| 4079, |
| /* DPSUB_S_W */ |
| 4083, |
| /* DPSUB_U_D */ |
| 4087, |
| /* DPSUB_U_H */ |
| 4091, |
| /* DPSUB_U_W */ |
| 4095, |
| /* DPSU_H_QBL */ |
| 4099, |
| /* DPSU_H_QBL_MM */ |
| 4103, |
| /* DPSU_H_QBR */ |
| 4107, |
| /* DPSU_H_QBR_MM */ |
| 4111, |
| /* DPSX_W_PH */ |
| 4115, |
| /* DPSX_W_PH_MMR2 */ |
| 4119, |
| /* DPS_W_PH */ |
| 4123, |
| /* DPS_W_PH_MMR2 */ |
| 4127, |
| /* DROTR */ |
| 4131, |
| /* DROTR32 */ |
| 4134, |
| /* DROTRV */ |
| 4137, |
| /* DSBH */ |
| 4140, |
| /* DSDIV */ |
| 4142, |
| /* DSHD */ |
| 4144, |
| /* DSLL */ |
| 4146, |
| /* DSLL32 */ |
| 4149, |
| /* DSLL64_32 */ |
| 4152, |
| /* DSLLV */ |
| 4154, |
| /* DSRA */ |
| 4157, |
| /* DSRA32 */ |
| 4160, |
| /* DSRAV */ |
| 4163, |
| /* DSRL */ |
| 4166, |
| /* DSRL32 */ |
| 4169, |
| /* DSRLV */ |
| 4172, |
| /* DSUB */ |
| 4175, |
| /* DSUBu */ |
| 4178, |
| /* DUDIV */ |
| 4181, |
| /* DVP */ |
| 4183, |
| /* DVPE */ |
| 4184, |
| /* DVP_MMR6 */ |
| 4185, |
| /* DivRxRy16 */ |
| 4186, |
| /* DivuRxRy16 */ |
| 4188, |
| /* EHB */ |
| 4190, |
| /* EHB_MM */ |
| 4190, |
| /* EHB_MMR6 */ |
| 4190, |
| /* EI */ |
| 4190, |
| /* EI_MM */ |
| 4191, |
| /* EI_MMR6 */ |
| 4192, |
| /* EMT */ |
| 4193, |
| /* ERET */ |
| 4194, |
| /* ERETNC */ |
| 4194, |
| /* ERETNC_MMR6 */ |
| 4194, |
| /* ERET_MM */ |
| 4194, |
| /* ERET_MMR6 */ |
| 4194, |
| /* EVP */ |
| 4194, |
| /* EVPE */ |
| 4195, |
| /* EVP_MMR6 */ |
| 4196, |
| /* EXT */ |
| 4197, |
| /* EXTP */ |
| 4201, |
| /* EXTPDP */ |
| 4204, |
| /* EXTPDPV */ |
| 4207, |
| /* EXTPDPV_MM */ |
| 4210, |
| /* EXTPDP_MM */ |
| 4213, |
| /* EXTPV */ |
| 4216, |
| /* EXTPV_MM */ |
| 4219, |
| /* EXTP_MM */ |
| 4222, |
| /* EXTRV_RS_W */ |
| 4225, |
| /* EXTRV_RS_W_MM */ |
| 4228, |
| /* EXTRV_R_W */ |
| 4231, |
| /* EXTRV_R_W_MM */ |
| 4234, |
| /* EXTRV_S_H */ |
| 4237, |
| /* EXTRV_S_H_MM */ |
| 4240, |
| /* EXTRV_W */ |
| 4243, |
| /* EXTRV_W_MM */ |
| 4246, |
| /* EXTR_RS_W */ |
| 4249, |
| /* EXTR_RS_W_MM */ |
| 4252, |
| /* EXTR_R_W */ |
| 4255, |
| /* EXTR_R_W_MM */ |
| 4258, |
| /* EXTR_S_H */ |
| 4261, |
| /* EXTR_S_H_MM */ |
| 4264, |
| /* EXTR_W */ |
| 4267, |
| /* EXTR_W_MM */ |
| 4270, |
| /* EXTS */ |
| 4273, |
| /* EXTS32 */ |
| 4277, |
| /* EXT_MM */ |
| 4281, |
| /* EXT_MMR6 */ |
| 4285, |
| /* FABS_D32 */ |
| 4289, |
| /* FABS_D32_MM */ |
| 4291, |
| /* FABS_D64 */ |
| 4293, |
| /* FABS_D64_MM */ |
| 4295, |
| /* FABS_S */ |
| 4297, |
| /* FABS_S_MM */ |
| 4299, |
| /* FADD_D */ |
| 4301, |
| /* FADD_D32 */ |
| 4304, |
| /* FADD_D32_MM */ |
| 4307, |
| /* FADD_D64 */ |
| 4310, |
| /* FADD_D64_MM */ |
| 4313, |
| /* FADD_PS64 */ |
| 4316, |
| /* FADD_S */ |
| 4319, |
| /* FADD_S_MM */ |
| 4322, |
| /* FADD_S_MMR6 */ |
| 4325, |
| /* FADD_W */ |
| 4328, |
| /* FCAF_D */ |
| 4331, |
| /* FCAF_W */ |
| 4334, |
| /* FCEQ_D */ |
| 4337, |
| /* FCEQ_W */ |
| 4340, |
| /* FCLASS_D */ |
| 4343, |
| /* FCLASS_W */ |
| 4345, |
| /* FCLE_D */ |
| 4347, |
| /* FCLE_W */ |
| 4350, |
| /* FCLT_D */ |
| 4353, |
| /* FCLT_W */ |
| 4356, |
| /* FCMP_D32 */ |
| 4359, |
| /* FCMP_D32_MM */ |
| 4362, |
| /* FCMP_D64 */ |
| 4365, |
| /* FCMP_S32 */ |
| 4368, |
| /* FCMP_S32_MM */ |
| 4371, |
| /* FCNE_D */ |
| 4374, |
| /* FCNE_W */ |
| 4377, |
| /* FCOR_D */ |
| 4380, |
| /* FCOR_W */ |
| 4383, |
| /* FCUEQ_D */ |
| 4386, |
| /* FCUEQ_W */ |
| 4389, |
| /* FCULE_D */ |
| 4392, |
| /* FCULE_W */ |
| 4395, |
| /* FCULT_D */ |
| 4398, |
| /* FCULT_W */ |
| 4401, |
| /* FCUNE_D */ |
| 4404, |
| /* FCUNE_W */ |
| 4407, |
| /* FCUN_D */ |
| 4410, |
| /* FCUN_W */ |
| 4413, |
| /* FDIV_D */ |
| 4416, |
| /* FDIV_D32 */ |
| 4419, |
| /* FDIV_D32_MM */ |
| 4422, |
| /* FDIV_D64 */ |
| 4425, |
| /* FDIV_D64_MM */ |
| 4428, |
| /* FDIV_S */ |
| 4431, |
| /* FDIV_S_MM */ |
| 4434, |
| /* FDIV_S_MMR6 */ |
| 4437, |
| /* FDIV_W */ |
| 4440, |
| /* FEXDO_H */ |
| 4443, |
| /* FEXDO_W */ |
| 4446, |
| /* FEXP2_D */ |
| 4449, |
| /* FEXP2_W */ |
| 4452, |
| /* FEXUPL_D */ |
| 4455, |
| /* FEXUPL_W */ |
| 4457, |
| /* FEXUPR_D */ |
| 4459, |
| /* FEXUPR_W */ |
| 4461, |
| /* FFINT_S_D */ |
| 4463, |
| /* FFINT_S_W */ |
| 4465, |
| /* FFINT_U_D */ |
| 4467, |
| /* FFINT_U_W */ |
| 4469, |
| /* FFQL_D */ |
| 4471, |
| /* FFQL_W */ |
| 4473, |
| /* FFQR_D */ |
| 4475, |
| /* FFQR_W */ |
| 4477, |
| /* FILL_B */ |
| 4479, |
| /* FILL_D */ |
| 4481, |
| /* FILL_H */ |
| 4483, |
| /* FILL_W */ |
| 4485, |
| /* FLOG2_D */ |
| 4487, |
| /* FLOG2_W */ |
| 4489, |
| /* FLOOR_L_D64 */ |
| 4491, |
| /* FLOOR_L_D_MMR6 */ |
| 4493, |
| /* FLOOR_L_S */ |
| 4495, |
| /* FLOOR_L_S_MMR6 */ |
| 4497, |
| /* FLOOR_W_D32 */ |
| 4499, |
| /* FLOOR_W_D64 */ |
| 4501, |
| /* FLOOR_W_D_MMR6 */ |
| 4503, |
| /* FLOOR_W_MM */ |
| 4505, |
| /* FLOOR_W_S */ |
| 4507, |
| /* FLOOR_W_S_MM */ |
| 4509, |
| /* FLOOR_W_S_MMR6 */ |
| 4511, |
| /* FMADD_D */ |
| 4513, |
| /* FMADD_W */ |
| 4517, |
| /* FMAX_A_D */ |
| 4521, |
| /* FMAX_A_W */ |
| 4524, |
| /* FMAX_D */ |
| 4527, |
| /* FMAX_W */ |
| 4530, |
| /* FMIN_A_D */ |
| 4533, |
| /* FMIN_A_W */ |
| 4536, |
| /* FMIN_D */ |
| 4539, |
| /* FMIN_W */ |
| 4542, |
| /* FMOV_D32 */ |
| 4545, |
| /* FMOV_D32_MM */ |
| 4547, |
| /* FMOV_D64 */ |
| 4549, |
| /* FMOV_D64_MM */ |
| 4551, |
| /* FMOV_D_MMR6 */ |
| 4553, |
| /* FMOV_S */ |
| 4555, |
| /* FMOV_S_MM */ |
| 4557, |
| /* FMOV_S_MMR6 */ |
| 4559, |
| /* FMSUB_D */ |
| 4561, |
| /* FMSUB_W */ |
| 4565, |
| /* FMUL_D */ |
| 4569, |
| /* FMUL_D32 */ |
| 4572, |
| /* FMUL_D32_MM */ |
| 4575, |
| /* FMUL_D64 */ |
| 4578, |
| /* FMUL_D64_MM */ |
| 4581, |
| /* FMUL_PS64 */ |
| 4584, |
| /* FMUL_S */ |
| 4587, |
| /* FMUL_S_MM */ |
| 4590, |
| /* FMUL_S_MMR6 */ |
| 4593, |
| /* FMUL_W */ |
| 4596, |
| /* FNEG_D32 */ |
| 4599, |
| /* FNEG_D32_MM */ |
| 4601, |
| /* FNEG_D64 */ |
| 4603, |
| /* FNEG_D64_MM */ |
| 4605, |
| /* FNEG_S */ |
| 4607, |
| /* FNEG_S_MM */ |
| 4609, |
| /* FNEG_S_MMR6 */ |
| 4611, |
| /* FORK */ |
| 4613, |
| /* FRCP_D */ |
| 4616, |
| /* FRCP_W */ |
| 4618, |
| /* FRINT_D */ |
| 4620, |
| /* FRINT_W */ |
| 4622, |
| /* FRSQRT_D */ |
| 4624, |
| /* FRSQRT_W */ |
| 4626, |
| /* FSAF_D */ |
| 4628, |
| /* FSAF_W */ |
| 4631, |
| /* FSEQ_D */ |
| 4634, |
| /* FSEQ_W */ |
| 4637, |
| /* FSLE_D */ |
| 4640, |
| /* FSLE_W */ |
| 4643, |
| /* FSLT_D */ |
| 4646, |
| /* FSLT_W */ |
| 4649, |
| /* FSNE_D */ |
| 4652, |
| /* FSNE_W */ |
| 4655, |
| /* FSOR_D */ |
| 4658, |
| /* FSOR_W */ |
| 4661, |
| /* FSQRT_D */ |
| 4664, |
| /* FSQRT_D32 */ |
| 4666, |
| /* FSQRT_D32_MM */ |
| 4668, |
| /* FSQRT_D64 */ |
| 4670, |
| /* FSQRT_D64_MM */ |
| 4672, |
| /* FSQRT_S */ |
| 4674, |
| /* FSQRT_S_MM */ |
| 4676, |
| /* FSQRT_W */ |
| 4678, |
| /* FSUB_D */ |
| 4680, |
| /* FSUB_D32 */ |
| 4683, |
| /* FSUB_D32_MM */ |
| 4686, |
| /* FSUB_D64 */ |
| 4689, |
| /* FSUB_D64_MM */ |
| 4692, |
| /* FSUB_PS64 */ |
| 4695, |
| /* FSUB_S */ |
| 4698, |
| /* FSUB_S_MM */ |
| 4701, |
| /* FSUB_S_MMR6 */ |
| 4704, |
| /* FSUB_W */ |
| 4707, |
| /* FSUEQ_D */ |
| 4710, |
| /* FSUEQ_W */ |
| 4713, |
| /* FSULE_D */ |
| 4716, |
| /* FSULE_W */ |
| 4719, |
| /* FSULT_D */ |
| 4722, |
| /* FSULT_W */ |
| 4725, |
| /* FSUNE_D */ |
| 4728, |
| /* FSUNE_W */ |
| 4731, |
| /* FSUN_D */ |
| 4734, |
| /* FSUN_W */ |
| 4737, |
| /* FTINT_S_D */ |
| 4740, |
| /* FTINT_S_W */ |
| 4742, |
| /* FTINT_U_D */ |
| 4744, |
| /* FTINT_U_W */ |
| 4746, |
| /* FTQ_H */ |
| 4748, |
| /* FTQ_W */ |
| 4751, |
| /* FTRUNC_S_D */ |
| 4754, |
| /* FTRUNC_S_W */ |
| 4756, |
| /* FTRUNC_U_D */ |
| 4758, |
| /* FTRUNC_U_W */ |
| 4760, |
| /* GINVI */ |
| 4762, |
| /* GINVI_MMR6 */ |
| 4763, |
| /* GINVT */ |
| 4764, |
| /* GINVT_MMR6 */ |
| 4766, |
| /* HADD_S_D */ |
| 4768, |
| /* HADD_S_H */ |
| 4771, |
| /* HADD_S_W */ |
| 4774, |
| /* HADD_U_D */ |
| 4777, |
| /* HADD_U_H */ |
| 4780, |
| /* HADD_U_W */ |
| 4783, |
| /* HSUB_S_D */ |
| 4786, |
| /* HSUB_S_H */ |
| 4789, |
| /* HSUB_S_W */ |
| 4792, |
| /* HSUB_U_D */ |
| 4795, |
| /* HSUB_U_H */ |
| 4798, |
| /* HSUB_U_W */ |
| 4801, |
| /* HYPCALL */ |
| 4804, |
| /* HYPCALL_MM */ |
| 4805, |
| /* ILVEV_B */ |
| 4806, |
| /* ILVEV_D */ |
| 4809, |
| /* ILVEV_H */ |
| 4812, |
| /* ILVEV_W */ |
| 4815, |
| /* ILVL_B */ |
| 4818, |
| /* ILVL_D */ |
| 4821, |
| /* ILVL_H */ |
| 4824, |
| /* ILVL_W */ |
| 4827, |
| /* ILVOD_B */ |
| 4830, |
| /* ILVOD_D */ |
| 4833, |
| /* ILVOD_H */ |
| 4836, |
| /* ILVOD_W */ |
| 4839, |
| /* ILVR_B */ |
| 4842, |
| /* ILVR_D */ |
| 4845, |
| /* ILVR_H */ |
| 4848, |
| /* ILVR_W */ |
| 4851, |
| /* INS */ |
| 4854, |
| /* INSERT_B */ |
| 4859, |
| /* INSERT_D */ |
| 4863, |
| /* INSERT_H */ |
| 4867, |
| /* INSERT_W */ |
| 4871, |
| /* INSV */ |
| 4875, |
| /* INSVE_B */ |
| 4878, |
| /* INSVE_D */ |
| 4883, |
| /* INSVE_H */ |
| 4888, |
| /* INSVE_W */ |
| 4893, |
| /* INSV_MM */ |
| 4898, |
| /* INS_MM */ |
| 4901, |
| /* INS_MMR6 */ |
| 4906, |
| /* J */ |
| 4911, |
| /* JAL */ |
| 4912, |
| /* JALR */ |
| 4913, |
| /* JALR16_MM */ |
| 4915, |
| /* JALR64 */ |
| 4916, |
| /* JALRC16_MMR6 */ |
| 4918, |
| /* JALRC_HB_MMR6 */ |
| 4919, |
| /* JALRC_MMR6 */ |
| 4921, |
| /* JALRS16_MM */ |
| 4923, |
| /* JALRS_MM */ |
| 4924, |
| /* JALR_HB */ |
| 4926, |
| /* JALR_HB64 */ |
| 4928, |
| /* JALR_MM */ |
| 4930, |
| /* JALS_MM */ |
| 4932, |
| /* JALX */ |
| 4933, |
| /* JALX_MM */ |
| 4934, |
| /* JAL_MM */ |
| 4935, |
| /* JIALC */ |
| 4936, |
| /* JIALC64 */ |
| 4938, |
| /* JIALC_MMR6 */ |
| 4940, |
| /* JIC */ |
| 4942, |
| /* JIC64 */ |
| 4944, |
| /* JIC_MMR6 */ |
| 4946, |
| /* JR */ |
| 4948, |
| /* JR16_MM */ |
| 4949, |
| /* JR64 */ |
| 4950, |
| /* JRADDIUSP */ |
| 4951, |
| /* JRC16_MM */ |
| 4952, |
| /* JRC16_MMR6 */ |
| 4953, |
| /* JRCADDIUSP_MMR6 */ |
| 4954, |
| /* JR_HB */ |
| 4955, |
| /* JR_HB64 */ |
| 4956, |
| /* JR_HB64_R6 */ |
| 4957, |
| /* JR_HB_R6 */ |
| 4958, |
| /* JR_MM */ |
| 4959, |
| /* J_MM */ |
| 4960, |
| /* Jal16 */ |
| 4961, |
| /* JalB16 */ |
| 4962, |
| /* JrRa16 */ |
| 4963, |
| /* JrcRa16 */ |
| 4963, |
| /* JrcRx16 */ |
| 4963, |
| /* JumpLinkReg16 */ |
| 4964, |
| /* LB */ |
| 4965, |
| /* LB64 */ |
| 4968, |
| /* LBE */ |
| 4971, |
| /* LBE_MM */ |
| 4974, |
| /* LBU16_MM */ |
| 4977, |
| /* LBUX */ |
| 4980, |
| /* LBUX_MM */ |
| 4983, |
| /* LBU_MMR6 */ |
| 4986, |
| /* LB_MM */ |
| 4989, |
| /* LB_MMR6 */ |
| 4992, |
| /* LBu */ |
| 4995, |
| /* LBu64 */ |
| 4998, |
| /* LBuE */ |
| 5001, |
| /* LBuE_MM */ |
| 5004, |
| /* LBu_MM */ |
| 5007, |
| /* LD */ |
| 5010, |
| /* LDC1 */ |
| 5013, |
| /* LDC164 */ |
| 5016, |
| /* LDC1_D64_MMR6 */ |
| 5019, |
| /* LDC1_MM_D32 */ |
| 5022, |
| /* LDC1_MM_D64 */ |
| 5025, |
| /* LDC2 */ |
| 5028, |
| /* LDC2_MMR6 */ |
| 5031, |
| /* LDC2_R6 */ |
| 5034, |
| /* LDC3 */ |
| 5037, |
| /* LDI_B */ |
| 5040, |
| /* LDI_D */ |
| 5042, |
| /* LDI_H */ |
| 5044, |
| /* LDI_W */ |
| 5046, |
| /* LDL */ |
| 5048, |
| /* LDPC */ |
| 5052, |
| /* LDR */ |
| 5054, |
| /* LDXC1 */ |
| 5058, |
| /* LDXC164 */ |
| 5061, |
| /* LD_B */ |
| 5064, |
| /* LD_D */ |
| 5067, |
| /* LD_H */ |
| 5070, |
| /* LD_W */ |
| 5073, |
| /* LEA_ADDiu */ |
| 5076, |
| /* LEA_ADDiu64 */ |
| 5079, |
| /* LEA_ADDiu_MM */ |
| 5082, |
| /* LH */ |
| 5085, |
| /* LH64 */ |
| 5088, |
| /* LHE */ |
| 5091, |
| /* LHE_MM */ |
| 5094, |
| /* LHU16_MM */ |
| 5097, |
| /* LHX */ |
| 5100, |
| /* LHX_MM */ |
| 5103, |
| /* LH_MM */ |
| 5106, |
| /* LHu */ |
| 5109, |
| /* LHu64 */ |
| 5112, |
| /* LHuE */ |
| 5115, |
| /* LHuE_MM */ |
| 5118, |
| /* LHu_MM */ |
| 5121, |
| /* LI16_MM */ |
| 5124, |
| /* LI16_MMR6 */ |
| 5126, |
| /* LL */ |
| 5128, |
| /* LL64 */ |
| 5131, |
| /* LL64_R6 */ |
| 5134, |
| /* LLD */ |
| 5137, |
| /* LLD_R6 */ |
| 5140, |
| /* LLE */ |
| 5143, |
| /* LLE_MM */ |
| 5146, |
| /* LL_MM */ |
| 5149, |
| /* LL_MMR6 */ |
| 5152, |
| /* LL_R6 */ |
| 5155, |
| /* LSA */ |
| 5158, |
| /* LSA_MMR6 */ |
| 5162, |
| /* LSA_R6 */ |
| 5166, |
| /* LUI_MMR6 */ |
| 5170, |
| /* LUXC1 */ |
| 5172, |
| /* LUXC164 */ |
| 5175, |
| /* LUXC1_MM */ |
| 5178, |
| /* LUi */ |
| 5181, |
| /* LUi64 */ |
| 5183, |
| /* LUi_MM */ |
| 5185, |
| /* LW */ |
| 5187, |
| /* LW16_MM */ |
| 5190, |
| /* LW64 */ |
| 5193, |
| /* LWC1 */ |
| 5196, |
| /* LWC1_MM */ |
| 5199, |
| /* LWC2 */ |
| 5202, |
| /* LWC2_MMR6 */ |
| 5205, |
| /* LWC2_R6 */ |
| 5208, |
| /* LWC3 */ |
| 5211, |
| /* LWDSP */ |
| 5214, |
| /* LWDSP_MM */ |
| 5217, |
| /* LWE */ |
| 5220, |
| /* LWE_MM */ |
| 5223, |
| /* LWGP_MM */ |
| 5226, |
| /* LWL */ |
| 5229, |
| /* LWL64 */ |
| 5233, |
| /* LWLE */ |
| 5237, |
| /* LWLE_MM */ |
| 5241, |
| /* LWL_MM */ |
| 5245, |
| /* LWM16_MM */ |
| 5249, |
| /* LWM16_MMR6 */ |
| 5252, |
| /* LWM32_MM */ |
| 5255, |
| /* LWPC */ |
| 5258, |
| /* LWPC_MMR6 */ |
| 5260, |
| /* LWP_MM */ |
| 5262, |
| /* LWR */ |
| 5266, |
| /* LWR64 */ |
| 5270, |
| /* LWRE */ |
| 5274, |
| /* LWRE_MM */ |
| 5278, |
| /* LWR_MM */ |
| 5282, |
| /* LWSP_MM */ |
| 5286, |
| /* LWUPC */ |
| 5289, |
| /* LWU_MM */ |
| 5291, |
| /* LWX */ |
| 5294, |
| /* LWXC1 */ |
| 5297, |
| /* LWXC1_MM */ |
| 5300, |
| /* LWXS_MM */ |
| 5303, |
| /* LWX_MM */ |
| 5306, |
| /* LW_MM */ |
| 5309, |
| /* LW_MMR6 */ |
| 5312, |
| /* LWu */ |
| 5315, |
| /* LbRxRyOffMemX16 */ |
| 5318, |
| /* LbuRxRyOffMemX16 */ |
| 5321, |
| /* LhRxRyOffMemX16 */ |
| 5324, |
| /* LhuRxRyOffMemX16 */ |
| 5327, |
| /* LiRxImm16 */ |
| 5330, |
| /* LiRxImmAlignX16 */ |
| 5332, |
| /* LiRxImmX16 */ |
| 5334, |
| /* LwRxPcTcp16 */ |
| 5336, |
| /* LwRxPcTcpX16 */ |
| 5339, |
| /* LwRxRyOffMemX16 */ |
| 5342, |
| /* LwRxSpImmX16 */ |
| 5345, |
| /* MADD */ |
| 5348, |
| /* MADDF_D */ |
| 5350, |
| /* MADDF_D_MMR6 */ |
| 5354, |
| /* MADDF_S */ |
| 5358, |
| /* MADDF_S_MMR6 */ |
| 5362, |
| /* MADDR_Q_H */ |
| 5366, |
| /* MADDR_Q_W */ |
| 5370, |
| /* MADDU */ |
| 5374, |
| /* MADDU_DSP */ |
| 5376, |
| /* MADDU_DSP_MM */ |
| 5380, |
| /* MADDU_MM */ |
| 5384, |
| /* MADDV_B */ |
| 5386, |
| /* MADDV_D */ |
| 5390, |
| /* MADDV_H */ |
| 5394, |
| /* MADDV_W */ |
| 5398, |
| /* MADD_D32 */ |
| 5402, |
| /* MADD_D32_MM */ |
| 5406, |
| /* MADD_D64 */ |
| 5410, |
| /* MADD_DSP */ |
| 5414, |
| /* MADD_DSP_MM */ |
| 5418, |
| /* MADD_MM */ |
| 5422, |
| /* MADD_Q_H */ |
| 5424, |
| /* MADD_Q_W */ |
| 5428, |
| /* MADD_S */ |
| 5432, |
| /* MADD_S_MM */ |
| 5436, |
| /* MAQ_SA_W_PHL */ |
| 5440, |
| /* MAQ_SA_W_PHL_MM */ |
| 5444, |
| /* MAQ_SA_W_PHR */ |
| 5448, |
| /* MAQ_SA_W_PHR_MM */ |
| 5452, |
| /* MAQ_S_W_PHL */ |
| 5456, |
| /* MAQ_S_W_PHL_MM */ |
| 5460, |
| /* MAQ_S_W_PHR */ |
| 5464, |
| /* MAQ_S_W_PHR_MM */ |
| 5468, |
| /* MAXA_D */ |
| 5472, |
| /* MAXA_D_MMR6 */ |
| 5475, |
| /* MAXA_S */ |
| 5478, |
| /* MAXA_S_MMR6 */ |
| 5481, |
| /* MAXI_S_B */ |
| 5484, |
| /* MAXI_S_D */ |
| 5487, |
| /* MAXI_S_H */ |
| 5490, |
| /* MAXI_S_W */ |
| 5493, |
| /* MAXI_U_B */ |
| 5496, |
| /* MAXI_U_D */ |
| 5499, |
| /* MAXI_U_H */ |
| 5502, |
| /* MAXI_U_W */ |
| 5505, |
| /* MAX_A_B */ |
| 5508, |
| /* MAX_A_D */ |
| 5511, |
| /* MAX_A_H */ |
| 5514, |
| /* MAX_A_W */ |
| 5517, |
| /* MAX_D */ |
| 5520, |
| /* MAX_D_MMR6 */ |
| 5523, |
| /* MAX_S */ |
| 5526, |
| /* MAX_S_B */ |
| 5529, |
| /* MAX_S_D */ |
| 5532, |
| /* MAX_S_H */ |
| 5535, |
| /* MAX_S_MMR6 */ |
| 5538, |
| /* MAX_S_W */ |
| 5541, |
| /* MAX_U_B */ |
| 5544, |
| /* MAX_U_D */ |
| 5547, |
| /* MAX_U_H */ |
| 5550, |
| /* MAX_U_W */ |
| 5553, |
| /* MFC0 */ |
| 5556, |
| /* MFC0_MMR6 */ |
| 5559, |
| /* MFC1 */ |
| 5562, |
| /* MFC1_D64 */ |
| 5564, |
| /* MFC1_MM */ |
| 5566, |
| /* MFC1_MMR6 */ |
| 5568, |
| /* MFC2 */ |
| 5570, |
| /* MFC2_MMR6 */ |
| 5573, |
| /* MFGC0 */ |
| 5575, |
| /* MFGC0_MM */ |
| 5578, |
| /* MFHC0_MMR6 */ |
| 5581, |
| /* MFHC1_D32 */ |
| 5584, |
| /* MFHC1_D32_MM */ |
| 5586, |
| /* MFHC1_D64 */ |
| 5588, |
| /* MFHC1_D64_MM */ |
| 5590, |
| /* MFHC2_MMR6 */ |
| 5592, |
| /* MFHGC0 */ |
| 5594, |
| /* MFHGC0_MM */ |
| 5597, |
| /* MFHI */ |
| 5600, |
| /* MFHI16_MM */ |
| 5601, |
| /* MFHI64 */ |
| 5602, |
| /* MFHI_DSP */ |
| 5603, |
| /* MFHI_DSP_MM */ |
| 5605, |
| /* MFHI_MM */ |
| 5607, |
| /* MFLO */ |
| 5608, |
| /* MFLO16_MM */ |
| 5609, |
| /* MFLO64 */ |
| 5610, |
| /* MFLO_DSP */ |
| 5611, |
| /* MFLO_DSP_MM */ |
| 5613, |
| /* MFLO_MM */ |
| 5615, |
| /* MFTR */ |
| 5616, |
| /* MINA_D */ |
| 5621, |
| /* MINA_D_MMR6 */ |
| 5624, |
| /* MINA_S */ |
| 5627, |
| /* MINA_S_MMR6 */ |
| 5630, |
| /* MINI_S_B */ |
| 5633, |
| /* MINI_S_D */ |
| 5636, |
| /* MINI_S_H */ |
| 5639, |
| /* MINI_S_W */ |
| 5642, |
| /* MINI_U_B */ |
| 5645, |
| /* MINI_U_D */ |
| 5648, |
| /* MINI_U_H */ |
| 5651, |
| /* MINI_U_W */ |
| 5654, |
| /* MIN_A_B */ |
| 5657, |
| /* MIN_A_D */ |
| 5660, |
| /* MIN_A_H */ |
| 5663, |
| /* MIN_A_W */ |
| 5666, |
| /* MIN_D */ |
| 5669, |
| /* MIN_D_MMR6 */ |
| 5672, |
| /* MIN_S */ |
| 5675, |
| /* MIN_S_B */ |
| 5678, |
| /* MIN_S_D */ |
| 5681, |
| /* MIN_S_H */ |
| 5684, |
| /* MIN_S_MMR6 */ |
| 5687, |
| /* MIN_S_W */ |
| 5690, |
| /* MIN_U_B */ |
| 5693, |
| /* MIN_U_D */ |
| 5696, |
| /* MIN_U_H */ |
| 5699, |
| /* MIN_U_W */ |
| 5702, |
| /* MOD */ |
| 5705, |
| /* MODSUB */ |
| 5708, |
| /* MODSUB_MM */ |
| 5711, |
| /* MODU */ |
| 5714, |
| /* MODU_MMR6 */ |
| 5717, |
| /* MOD_MMR6 */ |
| 5720, |
| /* MOD_S_B */ |
| 5723, |
| /* MOD_S_D */ |
| 5726, |
| /* MOD_S_H */ |
| 5729, |
| /* MOD_S_W */ |
| 5732, |
| /* MOD_U_B */ |
| 5735, |
| /* MOD_U_D */ |
| 5738, |
| /* MOD_U_H */ |
| 5741, |
| /* MOD_U_W */ |
| 5744, |
| /* MOVE16_MM */ |
| 5747, |
| /* MOVE16_MMR6 */ |
| 5749, |
| /* MOVEP_MM */ |
| 5751, |
| /* MOVEP_MMR6 */ |
| 5755, |
| /* MOVE_V */ |
| 5759, |
| /* MOVF_D32 */ |
| 5761, |
| /* MOVF_D32_MM */ |
| 5765, |
| /* MOVF_D64 */ |
| 5769, |
| /* MOVF_I */ |
| 5773, |
| /* MOVF_I64 */ |
| 5777, |
| /* MOVF_I_MM */ |
| 5781, |
| /* MOVF_S */ |
| 5785, |
| /* MOVF_S_MM */ |
| 5789, |
| /* MOVN_I64_D64 */ |
| 5793, |
| /* MOVN_I64_I */ |
| 5797, |
| /* MOVN_I64_I64 */ |
| 5801, |
| /* MOVN_I64_S */ |
| 5805, |
| /* MOVN_I_D32 */ |
| 5809, |
| /* MOVN_I_D32_MM */ |
| 5813, |
| /* MOVN_I_D64 */ |
| 5817, |
| /* MOVN_I_I */ |
| 5821, |
| /* MOVN_I_I64 */ |
| 5825, |
| /* MOVN_I_MM */ |
| 5829, |
| /* MOVN_I_S */ |
| 5833, |
| /* MOVN_I_S_MM */ |
| 5837, |
| /* MOVT_D32 */ |
| 5841, |
| /* MOVT_D32_MM */ |
| 5845, |
| /* MOVT_D64 */ |
| 5849, |
| /* MOVT_I */ |
| 5853, |
| /* MOVT_I64 */ |
| 5857, |
| /* MOVT_I_MM */ |
| 5861, |
| /* MOVT_S */ |
| 5865, |
| /* MOVT_S_MM */ |
| 5869, |
| /* MOVZ_I64_D64 */ |
| 5873, |
| /* MOVZ_I64_I */ |
| 5877, |
| /* MOVZ_I64_I64 */ |
| 5881, |
| /* MOVZ_I64_S */ |
| 5885, |
| /* MOVZ_I_D32 */ |
| 5889, |
| /* MOVZ_I_D32_MM */ |
| 5893, |
| /* MOVZ_I_D64 */ |
| 5897, |
| /* MOVZ_I_I */ |
| 5901, |
| /* MOVZ_I_I64 */ |
| 5905, |
| /* MOVZ_I_MM */ |
| 5909, |
| /* MOVZ_I_S */ |
| 5913, |
| /* MOVZ_I_S_MM */ |
| 5917, |
| /* MSUB */ |
| 5921, |
| /* MSUBF_D */ |
| 5923, |
| /* MSUBF_D_MMR6 */ |
| 5927, |
| /* MSUBF_S */ |
| 5931, |
| /* MSUBF_S_MMR6 */ |
| 5935, |
| /* MSUBR_Q_H */ |
| 5939, |
| /* MSUBR_Q_W */ |
| 5943, |
| /* MSUBU */ |
| 5947, |
| /* MSUBU_DSP */ |
| 5949, |
| /* MSUBU_DSP_MM */ |
| 5953, |
| /* MSUBU_MM */ |
| 5957, |
| /* MSUBV_B */ |
| 5959, |
| /* MSUBV_D */ |
| 5963, |
| /* MSUBV_H */ |
| 5967, |
| /* MSUBV_W */ |
| 5971, |
| /* MSUB_D32 */ |
| 5975, |
| /* MSUB_D32_MM */ |
| 5979, |
| /* MSUB_D64 */ |
| 5983, |
| /* MSUB_DSP */ |
| 5987, |
| /* MSUB_DSP_MM */ |
| 5991, |
| /* MSUB_MM */ |
| 5995, |
| /* MSUB_Q_H */ |
| 5997, |
| /* MSUB_Q_W */ |
| 6001, |
| /* MSUB_S */ |
| 6005, |
| /* MSUB_S_MM */ |
| 6009, |
| /* MTC0 */ |
| 6013, |
| /* MTC0_MMR6 */ |
| 6016, |
| /* MTC1 */ |
| 6019, |
| /* MTC1_D64 */ |
| 6021, |
| /* MTC1_D64_MM */ |
| 6023, |
| /* MTC1_MM */ |
| 6025, |
| /* MTC1_MMR6 */ |
| 6027, |
| /* MTC2 */ |
| 6029, |
| /* MTC2_MMR6 */ |
| 6032, |
| /* MTGC0 */ |
| 6034, |
| /* MTGC0_MM */ |
| 6037, |
| /* MTHC0_MMR6 */ |
| 6040, |
| /* MTHC1_D32 */ |
| 6043, |
| /* MTHC1_D32_MM */ |
| 6046, |
| /* MTHC1_D64 */ |
| 6049, |
| /* MTHC1_D64_MM */ |
| 6052, |
| /* MTHC2_MMR6 */ |
| 6055, |
| /* MTHGC0 */ |
| 6057, |
| /* MTHGC0_MM */ |
| 6060, |
| /* MTHI */ |
| 6063, |
| /* MTHI64 */ |
| 6064, |
| /* MTHI_DSP */ |
| 6065, |
| /* MTHI_DSP_MM */ |
| 6067, |
| /* MTHI_MM */ |
| 6069, |
| /* MTHLIP */ |
| 6070, |
| /* MTHLIP_MM */ |
| 6073, |
| /* MTLO */ |
| 6076, |
| /* MTLO64 */ |
| 6077, |
| /* MTLO_DSP */ |
| 6078, |
| /* MTLO_DSP_MM */ |
| 6080, |
| /* MTLO_MM */ |
| 6082, |
| /* MTM0 */ |
| 6083, |
| /* MTM1 */ |
| 6084, |
| /* MTM2 */ |
| 6085, |
| /* MTP0 */ |
| 6086, |
| /* MTP1 */ |
| 6087, |
| /* MTP2 */ |
| 6088, |
| /* MTTR */ |
| 6089, |
| /* MUH */ |
| 6094, |
| /* MUHU */ |
| 6097, |
| /* MUHU_MMR6 */ |
| 6100, |
| /* MUH_MMR6 */ |
| 6103, |
| /* MUL */ |
| 6106, |
| /* MULEQ_S_W_PHL */ |
| 6109, |
| /* MULEQ_S_W_PHL_MM */ |
| 6112, |
| /* MULEQ_S_W_PHR */ |
| 6115, |
| /* MULEQ_S_W_PHR_MM */ |
| 6118, |
| /* MULEU_S_PH_QBL */ |
| 6121, |
| /* MULEU_S_PH_QBL_MM */ |
| 6124, |
| /* MULEU_S_PH_QBR */ |
| 6127, |
| /* MULEU_S_PH_QBR_MM */ |
| 6130, |
| /* MULQ_RS_PH */ |
| 6133, |
| /* MULQ_RS_PH_MM */ |
| 6136, |
| /* MULQ_RS_W */ |
| 6139, |
| /* MULQ_RS_W_MMR2 */ |
| 6142, |
| /* MULQ_S_PH */ |
| 6145, |
| /* MULQ_S_PH_MMR2 */ |
| 6148, |
| /* MULQ_S_W */ |
| 6151, |
| /* MULQ_S_W_MMR2 */ |
| 6154, |
| /* MULR_PS64 */ |
| 6157, |
| /* MULR_Q_H */ |
| 6160, |
| /* MULR_Q_W */ |
| 6163, |
| /* MULSAQ_S_W_PH */ |
| 6166, |
| /* MULSAQ_S_W_PH_MM */ |
| 6170, |
| /* MULSA_W_PH */ |
| 6174, |
| /* MULSA_W_PH_MMR2 */ |
| 6178, |
| /* MULT */ |
| 6182, |
| /* MULTU_DSP */ |
| 6184, |
| /* MULTU_DSP_MM */ |
| 6187, |
| /* MULT_DSP */ |
| 6190, |
| /* MULT_DSP_MM */ |
| 6193, |
| /* MULT_MM */ |
| 6196, |
| /* MULTu */ |
| 6198, |
| /* MULTu_MM */ |
| 6200, |
| /* MULU */ |
| 6202, |
| /* MULU_MMR6 */ |
| 6205, |
| /* MULV_B */ |
| 6208, |
| /* MULV_D */ |
| 6211, |
| /* MULV_H */ |
| 6214, |
| /* MULV_W */ |
| 6217, |
| /* MUL_MM */ |
| 6220, |
| /* MUL_MMR6 */ |
| 6223, |
| /* MUL_PH */ |
| 6226, |
| /* MUL_PH_MMR2 */ |
| 6229, |
| /* MUL_Q_H */ |
| 6232, |
| /* MUL_Q_W */ |
| 6235, |
| /* MUL_R6 */ |
| 6238, |
| /* MUL_S_PH */ |
| 6241, |
| /* MUL_S_PH_MMR2 */ |
| 6244, |
| /* Mfhi16 */ |
| 6247, |
| /* Mflo16 */ |
| 6248, |
| /* Move32R16 */ |
| 6249, |
| /* MoveR3216 */ |
| 6251, |
| /* NLOC_B */ |
| 6253, |
| /* NLOC_D */ |
| 6255, |
| /* NLOC_H */ |
| 6257, |
| /* NLOC_W */ |
| 6259, |
| /* NLZC_B */ |
| 6261, |
| /* NLZC_D */ |
| 6263, |
| /* NLZC_H */ |
| 6265, |
| /* NLZC_W */ |
| 6267, |
| /* NMADD_D32 */ |
| 6269, |
| /* NMADD_D32_MM */ |
| 6273, |
| /* NMADD_D64 */ |
| 6277, |
| /* NMADD_S */ |
| 6281, |
| /* NMADD_S_MM */ |
| 6285, |
| /* NMSUB_D32 */ |
| 6289, |
| /* NMSUB_D32_MM */ |
| 6293, |
| /* NMSUB_D64 */ |
| 6297, |
| /* NMSUB_S */ |
| 6301, |
| /* NMSUB_S_MM */ |
| 6305, |
| /* NOR */ |
| 6309, |
| /* NOR64 */ |
| 6312, |
| /* NORI_B */ |
| 6315, |
| /* NOR_MM */ |
| 6318, |
| /* NOR_MMR6 */ |
| 6321, |
| /* NOR_V */ |
| 6324, |
| /* NOT16_MM */ |
| 6327, |
| /* NOT16_MMR6 */ |
| 6329, |
| /* NegRxRy16 */ |
| 6331, |
| /* NotRxRy16 */ |
| 6333, |
| /* OR */ |
| 6335, |
| /* OR16_MM */ |
| 6338, |
| /* OR16_MMR6 */ |
| 6341, |
| /* OR64 */ |
| 6344, |
| /* ORI_B */ |
| 6347, |
| /* ORI_MMR6 */ |
| 6350, |
| /* OR_MM */ |
| 6353, |
| /* OR_MMR6 */ |
| 6356, |
| /* OR_V */ |
| 6359, |
| /* ORi */ |
| 6362, |
| /* ORi64 */ |
| 6365, |
| /* ORi_MM */ |
| 6368, |
| /* OrRxRxRy16 */ |
| 6371, |
| /* PACKRL_PH */ |
| 6374, |
| /* PACKRL_PH_MM */ |
| 6377, |
| /* PAUSE */ |
| 6380, |
| /* PAUSE_MM */ |
| 6380, |
| /* PAUSE_MMR6 */ |
| 6380, |
| /* PCKEV_B */ |
| 6380, |
| /* PCKEV_D */ |
| 6383, |
| /* PCKEV_H */ |
| 6386, |
| /* PCKEV_W */ |
| 6389, |
| /* PCKOD_B */ |
| 6392, |
| /* PCKOD_D */ |
| 6395, |
| /* PCKOD_H */ |
| 6398, |
| /* PCKOD_W */ |
| 6401, |
| /* PCNT_B */ |
| 6404, |
| /* PCNT_D */ |
| 6406, |
| /* PCNT_H */ |
| 6408, |
| /* PCNT_W */ |
| 6410, |
| /* PICK_PH */ |
| 6412, |
| /* PICK_PH_MM */ |
| 6415, |
| /* PICK_QB */ |
| 6418, |
| /* PICK_QB_MM */ |
| 6421, |
| /* PLL_PS64 */ |
| 6424, |
| /* PLU_PS64 */ |
| 6427, |
| /* POP */ |
| 6430, |
| /* PRECEQU_PH_QBL */ |
| 6432, |
| /* PRECEQU_PH_QBLA */ |
| 6434, |
| /* PRECEQU_PH_QBLA_MM */ |
| 6436, |
| /* PRECEQU_PH_QBL_MM */ |
| 6438, |
| /* PRECEQU_PH_QBR */ |
| 6440, |
| /* PRECEQU_PH_QBRA */ |
| 6442, |
| /* PRECEQU_PH_QBRA_MM */ |
| 6444, |
| /* PRECEQU_PH_QBR_MM */ |
| 6446, |
| /* PRECEQ_W_PHL */ |
| 6448, |
| /* PRECEQ_W_PHL_MM */ |
| 6450, |
| /* PRECEQ_W_PHR */ |
| 6452, |
| /* PRECEQ_W_PHR_MM */ |
| 6454, |
| /* PRECEU_PH_QBL */ |
| 6456, |
| /* PRECEU_PH_QBLA */ |
| 6458, |
| /* PRECEU_PH_QBLA_MM */ |
| 6460, |
| /* PRECEU_PH_QBL_MM */ |
| 6462, |
| /* PRECEU_PH_QBR */ |
| 6464, |
| /* PRECEU_PH_QBRA */ |
| 6466, |
| /* PRECEU_PH_QBRA_MM */ |
| 6468, |
| /* PRECEU_PH_QBR_MM */ |
| 6470, |
| /* PRECRQU_S_QB_PH */ |
| 6472, |
| /* PRECRQU_S_QB_PH_MM */ |
| 6475, |
| /* PRECRQ_PH_W */ |
| 6478, |
| /* PRECRQ_PH_W_MM */ |
| 6481, |
| /* PRECRQ_QB_PH */ |
| 6484, |
| /* PRECRQ_QB_PH_MM */ |
| 6487, |
| /* PRECRQ_RS_PH_W */ |
| 6490, |
| /* PRECRQ_RS_PH_W_MM */ |
| 6493, |
| /* PRECR_QB_PH */ |
| 6496, |
| /* PRECR_QB_PH_MMR2 */ |
| 6499, |
| /* PRECR_SRA_PH_W */ |
| 6502, |
| /* PRECR_SRA_PH_W_MMR2 */ |
| 6506, |
| /* PRECR_SRA_R_PH_W */ |
| 6510, |
| /* PRECR_SRA_R_PH_W_MMR2 */ |
| 6514, |
| /* PREF */ |
| 6518, |
| /* PREFE */ |
| 6521, |
| /* PREFE_MM */ |
| 6524, |
| /* PREFX_MM */ |
| 6527, |
| /* PREF_MM */ |
| 6530, |
| /* PREF_MMR6 */ |
| 6533, |
| /* PREF_R6 */ |
| 6536, |
| /* PREPEND */ |
| 6539, |
| /* PREPEND_MMR2 */ |
| 6543, |
| /* PUL_PS64 */ |
| 6547, |
| /* PUU_PS64 */ |
| 6550, |
| /* RADDU_W_QB */ |
| 6553, |
| /* RADDU_W_QB_MM */ |
| 6555, |
| /* RDDSP */ |
| 6557, |
| /* RDDSP_MM */ |
| 6559, |
| /* RDHWR */ |
| 6561, |
| /* RDHWR64 */ |
| 6564, |
| /* RDHWR_MM */ |
| 6567, |
| /* RDHWR_MMR6 */ |
| 6570, |
| /* RDPGPR_MMR6 */ |
| 6573, |
| /* RECIP_D32 */ |
| 6575, |
| /* RECIP_D32_MM */ |
| 6577, |
| /* RECIP_D64 */ |
| 6579, |
| /* RECIP_D64_MM */ |
| 6581, |
| /* RECIP_S */ |
| 6583, |
| /* RECIP_S_MM */ |
| 6585, |
| /* REPLV_PH */ |
| 6587, |
| /* REPLV_PH_MM */ |
| 6589, |
| /* REPLV_QB */ |
| 6591, |
| /* REPLV_QB_MM */ |
| 6593, |
| /* REPL_PH */ |
| 6595, |
| /* REPL_PH_MM */ |
| 6597, |
| /* REPL_QB */ |
| 6599, |
| /* REPL_QB_MM */ |
| 6601, |
| /* RINT_D */ |
| 6603, |
| /* RINT_D_MMR6 */ |
| 6605, |
| /* RINT_S */ |
| 6607, |
| /* RINT_S_MMR6 */ |
| 6609, |
| /* ROTR */ |
| 6611, |
| /* ROTRV */ |
| 6614, |
| /* ROTRV_MM */ |
| 6617, |
| /* ROTR_MM */ |
| 6620, |
| /* ROUND_L_D64 */ |
| 6623, |
| /* ROUND_L_D_MMR6 */ |
| 6625, |
| /* ROUND_L_S */ |
| 6627, |
| /* ROUND_L_S_MMR6 */ |
| 6629, |
| /* ROUND_W_D32 */ |
| 6631, |
| /* ROUND_W_D64 */ |
| 6633, |
| /* ROUND_W_D_MMR6 */ |
| 6635, |
| /* ROUND_W_MM */ |
| 6637, |
| /* ROUND_W_S */ |
| 6639, |
| /* ROUND_W_S_MM */ |
| 6641, |
| /* ROUND_W_S_MMR6 */ |
| 6643, |
| /* RSQRT_D32 */ |
| 6645, |
| /* RSQRT_D32_MM */ |
| 6647, |
| /* RSQRT_D64 */ |
| 6649, |
| /* RSQRT_D64_MM */ |
| 6651, |
| /* RSQRT_S */ |
| 6653, |
| /* RSQRT_S_MM */ |
| 6655, |
| /* Restore16 */ |
| 6657, |
| /* RestoreX16 */ |
| 6657, |
| /* SAA */ |
| 6657, |
| /* SAAD */ |
| 6659, |
| /* SAT_S_B */ |
| 6661, |
| /* SAT_S_D */ |
| 6664, |
| /* SAT_S_H */ |
| 6667, |
| /* SAT_S_W */ |
| 6670, |
| /* SAT_U_B */ |
| 6673, |
| /* SAT_U_D */ |
| 6676, |
| /* SAT_U_H */ |
| 6679, |
| /* SAT_U_W */ |
| 6682, |
| /* SB */ |
| 6685, |
| /* SB16_MM */ |
| 6688, |
| /* SB16_MMR6 */ |
| 6691, |
| /* SB64 */ |
| 6694, |
| /* SBE */ |
| 6697, |
| /* SBE_MM */ |
| 6700, |
| /* SB_MM */ |
| 6703, |
| /* SB_MMR6 */ |
| 6706, |
| /* SC */ |
| 6709, |
| /* SC64 */ |
| 6713, |
| /* SC64_R6 */ |
| 6717, |
| /* SCD */ |
| 6721, |
| /* SCD_R6 */ |
| 6725, |
| /* SCE */ |
| 6729, |
| /* SCE_MM */ |
| 6733, |
| /* SC_MM */ |
| 6737, |
| /* SC_MMR6 */ |
| 6741, |
| /* SC_R6 */ |
| 6745, |
| /* SD */ |
| 6749, |
| /* SDBBP */ |
| 6752, |
| /* SDBBP16_MM */ |
| 6753, |
| /* SDBBP16_MMR6 */ |
| 6754, |
| /* SDBBP_MM */ |
| 6755, |
| /* SDBBP_MMR6 */ |
| 6756, |
| /* SDBBP_R6 */ |
| 6757, |
| /* SDC1 */ |
| 6758, |
| /* SDC164 */ |
| 6761, |
| /* SDC1_D64_MMR6 */ |
| 6764, |
| /* SDC1_MM_D32 */ |
| 6767, |
| /* SDC1_MM_D64 */ |
| 6770, |
| /* SDC2 */ |
| 6773, |
| /* SDC2_MMR6 */ |
| 6776, |
| /* SDC2_R6 */ |
| 6779, |
| /* SDC3 */ |
| 6782, |
| /* SDIV */ |
| 6785, |
| /* SDIV_MM */ |
| 6787, |
| /* SDL */ |
| 6789, |
| /* SDR */ |
| 6792, |
| /* SDXC1 */ |
| 6795, |
| /* SDXC164 */ |
| 6798, |
| /* SEB */ |
| 6801, |
| /* SEB64 */ |
| 6803, |
| /* SEB_MM */ |
| 6805, |
| /* SEH */ |
| 6807, |
| /* SEH64 */ |
| 6809, |
| /* SEH_MM */ |
| 6811, |
| /* SELEQZ */ |
| 6813, |
| /* SELEQZ64 */ |
| 6816, |
| /* SELEQZ_D */ |
| 6819, |
| /* SELEQZ_D_MMR6 */ |
| 6822, |
| /* SELEQZ_MMR6 */ |
| 6825, |
| /* SELEQZ_S */ |
| 6828, |
| /* SELEQZ_S_MMR6 */ |
| 6831, |
| /* SELNEZ */ |
| 6834, |
| /* SELNEZ64 */ |
| 6837, |
| /* SELNEZ_D */ |
| 6840, |
| /* SELNEZ_D_MMR6 */ |
| 6843, |
| /* SELNEZ_MMR6 */ |
| 6846, |
| /* SELNEZ_S */ |
| 6849, |
| /* SELNEZ_S_MMR6 */ |
| 6852, |
| /* SEL_D */ |
| 6855, |
| /* SEL_D_MMR6 */ |
| 6859, |
| /* SEL_S */ |
| 6863, |
| /* SEL_S_MMR6 */ |
| 6867, |
| /* SEQ */ |
| 6871, |
| /* SEQi */ |
| 6874, |
| /* SH */ |
| 6877, |
| /* SH16_MM */ |
| 6880, |
| /* SH16_MMR6 */ |
| 6883, |
| /* SH64 */ |
| 6886, |
| /* SHE */ |
| 6889, |
| /* SHE_MM */ |
| 6892, |
| /* SHF_B */ |
| 6895, |
| /* SHF_H */ |
| 6898, |
| /* SHF_W */ |
| 6901, |
| /* SHILO */ |
| 6904, |
| /* SHILOV */ |
| 6907, |
| /* SHILOV_MM */ |
| 6910, |
| /* SHILO_MM */ |
| 6913, |
| /* SHLLV_PH */ |
| 6916, |
| /* SHLLV_PH_MM */ |
| 6919, |
| /* SHLLV_QB */ |
| 6922, |
| /* SHLLV_QB_MM */ |
| 6925, |
| /* SHLLV_S_PH */ |
| 6928, |
| /* SHLLV_S_PH_MM */ |
| 6931, |
| /* SHLLV_S_W */ |
| 6934, |
| /* SHLLV_S_W_MM */ |
| 6937, |
| /* SHLL_PH */ |
| 6940, |
| /* SHLL_PH_MM */ |
| 6943, |
| /* SHLL_QB */ |
| 6946, |
| /* SHLL_QB_MM */ |
| 6949, |
| /* SHLL_S_PH */ |
| 6952, |
| /* SHLL_S_PH_MM */ |
| 6955, |
| /* SHLL_S_W */ |
| 6958, |
| /* SHLL_S_W_MM */ |
| 6961, |
| /* SHRAV_PH */ |
| 6964, |
| /* SHRAV_PH_MM */ |
| 6967, |
| /* SHRAV_QB */ |
| 6970, |
| /* SHRAV_QB_MMR2 */ |
| 6973, |
| /* SHRAV_R_PH */ |
| 6976, |
| /* SHRAV_R_PH_MM */ |
| 6979, |
| /* SHRAV_R_QB */ |
| 6982, |
| /* SHRAV_R_QB_MMR2 */ |
| 6985, |
| /* SHRAV_R_W */ |
| 6988, |
| /* SHRAV_R_W_MM */ |
| 6991, |
| /* SHRA_PH */ |
| 6994, |
| /* SHRA_PH_MM */ |
| 6997, |
| /* SHRA_QB */ |
| 7000, |
| /* SHRA_QB_MMR2 */ |
| 7003, |
| /* SHRA_R_PH */ |
| 7006, |
| /* SHRA_R_PH_MM */ |
| 7009, |
| /* SHRA_R_QB */ |
| 7012, |
| /* SHRA_R_QB_MMR2 */ |
| 7015, |
| /* SHRA_R_W */ |
| 7018, |
| /* SHRA_R_W_MM */ |
| 7021, |
| /* SHRLV_PH */ |
| 7024, |
| /* SHRLV_PH_MMR2 */ |
| 7027, |
| /* SHRLV_QB */ |
| 7030, |
| /* SHRLV_QB_MM */ |
| 7033, |
| /* SHRL_PH */ |
| 7036, |
| /* SHRL_PH_MMR2 */ |
| 7039, |
| /* SHRL_QB */ |
| 7042, |
| /* SHRL_QB_MM */ |
| 7045, |
| /* SH_MM */ |
| 7048, |
| /* SH_MMR6 */ |
| 7051, |
| /* SIGRIE */ |
| 7054, |
| /* SIGRIE_MMR6 */ |
| 7055, |
| /* SLDI_B */ |
| 7056, |
| /* SLDI_D */ |
| 7060, |
| /* SLDI_H */ |
| 7064, |
| /* SLDI_W */ |
| 7068, |
| /* SLD_B */ |
| 7072, |
| /* SLD_D */ |
| 7076, |
| /* SLD_H */ |
| 7080, |
| /* SLD_W */ |
| 7084, |
| /* SLL */ |
| 7088, |
| /* SLL16_MM */ |
| 7091, |
| /* SLL16_MMR6 */ |
| 7094, |
| /* SLL64_32 */ |
| 7097, |
| /* SLL64_64 */ |
| 7099, |
| /* SLLI_B */ |
| 7101, |
| /* SLLI_D */ |
| 7104, |
| /* SLLI_H */ |
| 7107, |
| /* SLLI_W */ |
| 7110, |
| /* SLLV */ |
| 7113, |
| /* SLLV_MM */ |
| 7116, |
| /* SLL_B */ |
| 7119, |
| /* SLL_D */ |
| 7122, |
| /* SLL_H */ |
| 7125, |
| /* SLL_MM */ |
| 7128, |
| /* SLL_MMR6 */ |
| 7131, |
| /* SLL_W */ |
| 7134, |
| /* SLT */ |
| 7137, |
| /* SLT64 */ |
| 7140, |
| /* SLT_MM */ |
| 7143, |
| /* SLTi */ |
| 7146, |
| /* SLTi64 */ |
| 7149, |
| /* SLTi_MM */ |
| 7152, |
| /* SLTiu */ |
| 7155, |
| /* SLTiu64 */ |
| 7158, |
| /* SLTiu_MM */ |
| 7161, |
| /* SLTu */ |
| 7164, |
| /* SLTu64 */ |
| 7167, |
| /* SLTu_MM */ |
| 7170, |
| /* SNE */ |
| 7173, |
| /* SNEi */ |
| 7176, |
| /* SPLATI_B */ |
| 7179, |
| /* SPLATI_D */ |
| 7182, |
| /* SPLATI_H */ |
| 7185, |
| /* SPLATI_W */ |
| 7188, |
| /* SPLAT_B */ |
| 7191, |
| /* SPLAT_D */ |
| 7194, |
| /* SPLAT_H */ |
| 7197, |
| /* SPLAT_W */ |
| 7200, |
| /* SRA */ |
| 7203, |
| /* SRAI_B */ |
| 7206, |
| /* SRAI_D */ |
| 7209, |
| /* SRAI_H */ |
| 7212, |
| /* SRAI_W */ |
| 7215, |
| /* SRARI_B */ |
| 7218, |
| /* SRARI_D */ |
| 7221, |
| /* SRARI_H */ |
| 7224, |
| /* SRARI_W */ |
| 7227, |
| /* SRAR_B */ |
| 7230, |
| /* SRAR_D */ |
| 7233, |
| /* SRAR_H */ |
| 7236, |
| /* SRAR_W */ |
| 7239, |
| /* SRAV */ |
| 7242, |
| /* SRAV_MM */ |
| 7245, |
| /* SRA_B */ |
| 7248, |
| /* SRA_D */ |
| 7251, |
| /* SRA_H */ |
| 7254, |
| /* SRA_MM */ |
| 7257, |
| /* SRA_W */ |
| 7260, |
| /* SRL */ |
| 7263, |
| /* SRL16_MM */ |
| 7266, |
| /* SRL16_MMR6 */ |
| 7269, |
| /* SRLI_B */ |
| 7272, |
| /* SRLI_D */ |
| 7275, |
| /* SRLI_H */ |
| 7278, |
| /* SRLI_W */ |
| 7281, |
| /* SRLRI_B */ |
| 7284, |
| /* SRLRI_D */ |
| 7287, |
| /* SRLRI_H */ |
| 7290, |
| /* SRLRI_W */ |
| 7293, |
| /* SRLR_B */ |
| 7296, |
| /* SRLR_D */ |
| 7299, |
| /* SRLR_H */ |
| 7302, |
| /* SRLR_W */ |
| 7305, |
| /* SRLV */ |
| 7308, |
| /* SRLV_MM */ |
| 7311, |
| /* SRL_B */ |
| 7314, |
| /* SRL_D */ |
| 7317, |
| /* SRL_H */ |
| 7320, |
| /* SRL_MM */ |
| 7323, |
| /* SRL_W */ |
| 7326, |
| /* SSNOP */ |
| 7329, |
| /* SSNOP_MM */ |
| 7329, |
| /* SSNOP_MMR6 */ |
| 7329, |
| /* ST_B */ |
| 7329, |
| /* ST_D */ |
| 7332, |
| /* ST_H */ |
| 7335, |
| /* ST_W */ |
| 7338, |
| /* SUB */ |
| 7341, |
| /* SUBQH_PH */ |
| 7344, |
| /* SUBQH_PH_MMR2 */ |
| 7347, |
| /* SUBQH_R_PH */ |
| 7350, |
| /* SUBQH_R_PH_MMR2 */ |
| 7353, |
| /* SUBQH_R_W */ |
| 7356, |
| /* SUBQH_R_W_MMR2 */ |
| 7359, |
| /* SUBQH_W */ |
| 7362, |
| /* SUBQH_W_MMR2 */ |
| 7365, |
| /* SUBQ_PH */ |
| 7368, |
| /* SUBQ_PH_MM */ |
| 7371, |
| /* SUBQ_S_PH */ |
| 7374, |
| /* SUBQ_S_PH_MM */ |
| 7377, |
| /* SUBQ_S_W */ |
| 7380, |
| /* SUBQ_S_W_MM */ |
| 7383, |
| /* SUBSUS_U_B */ |
| 7386, |
| /* SUBSUS_U_D */ |
| 7389, |
| /* SUBSUS_U_H */ |
| 7392, |
| /* SUBSUS_U_W */ |
| 7395, |
| /* SUBSUU_S_B */ |
| 7398, |
| /* SUBSUU_S_D */ |
| 7401, |
| /* SUBSUU_S_H */ |
| 7404, |
| /* SUBSUU_S_W */ |
| 7407, |
| /* SUBS_S_B */ |
| 7410, |
| /* SUBS_S_D */ |
| 7413, |
| /* SUBS_S_H */ |
| 7416, |
| /* SUBS_S_W */ |
| 7419, |
| /* SUBS_U_B */ |
| 7422, |
| /* SUBS_U_D */ |
| 7425, |
| /* SUBS_U_H */ |
| 7428, |
| /* SUBS_U_W */ |
| 7431, |
| /* SUBU16_MM */ |
| 7434, |
| /* SUBU16_MMR6 */ |
| 7437, |
| /* SUBUH_QB */ |
| 7440, |
| /* SUBUH_QB_MMR2 */ |
| 7443, |
| /* SUBUH_R_QB */ |
| 7446, |
| /* SUBUH_R_QB_MMR2 */ |
| 7449, |
| /* SUBU_MMR6 */ |
| 7452, |
| /* SUBU_PH */ |
| 7455, |
| /* SUBU_PH_MMR2 */ |
| 7458, |
| /* SUBU_QB */ |
| 7461, |
| /* SUBU_QB_MM */ |
| 7464, |
| /* SUBU_S_PH */ |
| 7467, |
| /* SUBU_S_PH_MMR2 */ |
| 7470, |
| /* SUBU_S_QB */ |
| 7473, |
| /* SUBU_S_QB_MM */ |
| 7476, |
| /* SUBVI_B */ |
| 7479, |
| /* SUBVI_D */ |
| 7482, |
| /* SUBVI_H */ |
| 7485, |
| /* SUBVI_W */ |
| 7488, |
| /* SUBV_B */ |
| 7491, |
| /* SUBV_D */ |
| 7494, |
| /* SUBV_H */ |
| 7497, |
| /* SUBV_W */ |
| 7500, |
| /* SUB_MM */ |
| 7503, |
| /* SUB_MMR6 */ |
| 7506, |
| /* SUBu */ |
| 7509, |
| /* SUBu_MM */ |
| 7512, |
| /* SUXC1 */ |
| 7515, |
| /* SUXC164 */ |
| 7518, |
| /* SUXC1_MM */ |
| 7521, |
| /* SW */ |
| 7524, |
| /* SW16_MM */ |
| 7527, |
| /* SW16_MMR6 */ |
| 7530, |
| /* SW64 */ |
| 7533, |
| /* SWC1 */ |
| 7536, |
| /* SWC1_MM */ |
| 7539, |
| /* SWC2 */ |
| 7542, |
| /* SWC2_MMR6 */ |
| 7545, |
| /* SWC2_R6 */ |
| 7548, |
| /* SWC3 */ |
| 7551, |
| /* SWDSP */ |
| 7554, |
| /* SWDSP_MM */ |
| 7557, |
| /* SWE */ |
| 7560, |
| /* SWE_MM */ |
| 7563, |
| /* SWL */ |
| 7566, |
| /* SWL64 */ |
| 7569, |
| /* SWLE */ |
| 7572, |
| /* SWLE_MM */ |
| 7575, |
| /* SWL_MM */ |
| 7578, |
| /* SWM16_MM */ |
| 7581, |
| /* SWM16_MMR6 */ |
| 7584, |
| /* SWM32_MM */ |
| 7587, |
| /* SWP_MM */ |
| 7590, |
| /* SWR */ |
| 7594, |
| /* SWR64 */ |
| 7597, |
| /* SWRE */ |
| 7600, |
| /* SWRE_MM */ |
| 7603, |
| /* SWR_MM */ |
| 7606, |
| /* SWSP_MM */ |
| 7609, |
| /* SWSP_MMR6 */ |
| 7612, |
| /* SWXC1 */ |
| 7615, |
| /* SWXC1_MM */ |
| 7618, |
| /* SW_MM */ |
| 7621, |
| /* SW_MMR6 */ |
| 7624, |
| /* SYNC */ |
| 7627, |
| /* SYNCI */ |
| 7628, |
| /* SYNCI_MM */ |
| 7630, |
| /* SYNCI_MMR6 */ |
| 7632, |
| /* SYNC_MM */ |
| 7634, |
| /* SYNC_MMR6 */ |
| 7635, |
| /* SYSCALL */ |
| 7636, |
| /* SYSCALL_MM */ |
| 7637, |
| /* Save16 */ |
| 7638, |
| /* SaveX16 */ |
| 7638, |
| /* SbRxRyOffMemX16 */ |
| 7638, |
| /* SebRx16 */ |
| 7641, |
| /* SehRx16 */ |
| 7643, |
| /* ShRxRyOffMemX16 */ |
| 7645, |
| /* SllX16 */ |
| 7648, |
| /* SllvRxRy16 */ |
| 7651, |
| /* SltRxRy16 */ |
| 7654, |
| /* SltiRxImm16 */ |
| 7656, |
| /* SltiRxImmX16 */ |
| 7658, |
| /* SltiuRxImm16 */ |
| 7660, |
| /* SltiuRxImmX16 */ |
| 7662, |
| /* SltuRxRy16 */ |
| 7664, |
| /* SraX16 */ |
| 7666, |
| /* SravRxRy16 */ |
| 7669, |
| /* SrlX16 */ |
| 7672, |
| /* SrlvRxRy16 */ |
| 7675, |
| /* SubuRxRyRz16 */ |
| 7678, |
| /* SwRxRyOffMemX16 */ |
| 7681, |
| /* SwRxSpImmX16 */ |
| 7684, |
| /* TEQ */ |
| 7687, |
| /* TEQI */ |
| 7690, |
| /* TEQI_MM */ |
| 7692, |
| /* TEQ_MM */ |
| 7694, |
| /* TGE */ |
| 7697, |
| /* TGEI */ |
| 7700, |
| /* TGEIU */ |
| 7702, |
| /* TGEIU_MM */ |
| 7704, |
| /* TGEI_MM */ |
| 7706, |
| /* TGEU */ |
| 7708, |
| /* TGEU_MM */ |
| 7711, |
| /* TGE_MM */ |
| 7714, |
| /* TLBGINV */ |
| 7717, |
| /* TLBGINVF */ |
| 7717, |
| /* TLBGINVF_MM */ |
| 7717, |
| /* TLBGINV_MM */ |
| 7717, |
| /* TLBGP */ |
| 7717, |
| /* TLBGP_MM */ |
| 7717, |
| /* TLBGR */ |
| 7717, |
| /* TLBGR_MM */ |
| 7717, |
| /* TLBGWI */ |
| 7717, |
| /* TLBGWI_MM */ |
| 7717, |
| /* TLBGWR */ |
| 7717, |
| /* TLBGWR_MM */ |
| 7717, |
| /* TLBINV */ |
| 7717, |
| /* TLBINVF */ |
| 7717, |
| /* TLBINVF_MMR6 */ |
| 7717, |
| /* TLBINV_MMR6 */ |
| 7717, |
| /* TLBP */ |
| 7717, |
| /* TLBP_MM */ |
| 7717, |
| /* TLBR */ |
| 7717, |
| /* TLBR_MM */ |
| 7717, |
| /* TLBWI */ |
| 7717, |
| /* TLBWI_MM */ |
| 7717, |
| /* TLBWR */ |
| 7717, |
| /* TLBWR_MM */ |
| 7717, |
| /* TLT */ |
| 7717, |
| /* TLTI */ |
| 7720, |
| /* TLTIU_MM */ |
| 7722, |
| /* TLTI_MM */ |
| 7724, |
| /* TLTU */ |
| 7726, |
| /* TLTU_MM */ |
| 7729, |
| /* TLT_MM */ |
| 7732, |
| /* TNE */ |
| 7735, |
| /* TNEI */ |
| 7738, |
| /* TNEI_MM */ |
| 7740, |
| /* TNE_MM */ |
| 7742, |
| /* TRUNC_L_D64 */ |
| 7745, |
| /* TRUNC_L_D_MMR6 */ |
| 7747, |
| /* TRUNC_L_S */ |
| 7749, |
| /* TRUNC_L_S_MMR6 */ |
| 7751, |
| /* TRUNC_W_D32 */ |
| 7753, |
| /* TRUNC_W_D64 */ |
| 7755, |
| /* TRUNC_W_D_MMR6 */ |
| 7757, |
| /* TRUNC_W_MM */ |
| 7759, |
| /* TRUNC_W_S */ |
| 7761, |
| /* TRUNC_W_S_MM */ |
| 7763, |
| /* TRUNC_W_S_MMR6 */ |
| 7765, |
| /* TTLTIU */ |
| 7767, |
| /* UDIV */ |
| 7769, |
| /* UDIV_MM */ |
| 7771, |
| /* V3MULU */ |
| 7773, |
| /* VMM0 */ |
| 7776, |
| /* VMULU */ |
| 7779, |
| /* VSHF_B */ |
| 7782, |
| /* VSHF_D */ |
| 7786, |
| /* VSHF_H */ |
| 7790, |
| /* VSHF_W */ |
| 7794, |
| /* WAIT */ |
| 7798, |
| /* WAIT_MM */ |
| 7798, |
| /* WAIT_MMR6 */ |
| 7799, |
| /* WRDSP */ |
| 7800, |
| /* WRDSP_MM */ |
| 7802, |
| /* WRPGPR_MMR6 */ |
| 7804, |
| /* WSBH */ |
| 7806, |
| /* WSBH_MM */ |
| 7808, |
| /* WSBH_MMR6 */ |
| 7810, |
| /* XOR */ |
| 7812, |
| /* XOR16_MM */ |
| 7815, |
| /* XOR16_MMR6 */ |
| 7818, |
| /* XOR64 */ |
| 7821, |
| /* XORI_B */ |
| 7824, |
| /* XORI_MMR6 */ |
| 7827, |
| /* XOR_MM */ |
| 7830, |
| /* XOR_MMR6 */ |
| 7833, |
| /* XOR_V */ |
| 7836, |
| /* XORi */ |
| 7839, |
| /* XORi64 */ |
| 7842, |
| /* XORi_MM */ |
| 7845, |
| /* XorRxRxRy16 */ |
| 7848, |
| /* YIELD */ |
| 7851, |
| }; |
| |
| using namespace OpTypes; |
| const int16_t OpcodeOperandTypes[] = { |
| |
| /* PHI */ |
| -1, |
| /* INLINEASM */ |
| /* INLINEASM_BR */ |
| /* CFI_INSTRUCTION */ |
| i32imm, |
| /* EH_LABEL */ |
| i32imm, |
| /* GC_LABEL */ |
| i32imm, |
| /* ANNOTATION_LABEL */ |
| i32imm, |
| /* KILL */ |
| /* EXTRACT_SUBREG */ |
| -1, -1, i32imm, |
| /* INSERT_SUBREG */ |
| -1, -1, -1, i32imm, |
| /* IMPLICIT_DEF */ |
| -1, |
| /* SUBREG_TO_REG */ |
| -1, -1, -1, i32imm, |
| /* COPY_TO_REGCLASS */ |
| -1, -1, i32imm, |
| /* DBG_VALUE */ |
| /* DBG_VALUE_LIST */ |
| /* DBG_INSTR_REF */ |
| /* DBG_PHI */ |
| /* DBG_LABEL */ |
| -1, |
| /* REG_SEQUENCE */ |
| -1, -1, |
| /* COPY */ |
| -1, -1, |
| /* BUNDLE */ |
| /* LIFETIME_START */ |
| i32imm, |
| /* LIFETIME_END */ |
| i32imm, |
| /* PSEUDO_PROBE */ |
| i64imm, i64imm, i8imm, i32imm, |
| /* ARITH_FENCE */ |
| -1, -1, |
| /* STACKMAP */ |
| i64imm, i32imm, |
| /* FENTRY_CALL */ |
| /* PATCHPOINT */ |
| -1, i64imm, i32imm, -1, i32imm, i32imm, |
| /* LOAD_STACK_GUARD */ |
| -1, |
| /* PREALLOCATED_SETUP */ |
| i32imm, |
| /* PREALLOCATED_ARG */ |
| -1, i32imm, i32imm, |
| /* STATEPOINT */ |
| /* LOCAL_ESCAPE */ |
| -1, i32imm, |
| /* FAULTING_OP */ |
| -1, |
| /* PATCHABLE_OP */ |
| /* PATCHABLE_FUNCTION_ENTER */ |
| /* PATCHABLE_RET */ |
| /* PATCHABLE_FUNCTION_EXIT */ |
| /* PATCHABLE_TAIL_CALL */ |
| /* PATCHABLE_EVENT_CALL */ |
| -1, -1, |
| /* PATCHABLE_TYPED_EVENT_CALL */ |
| -1, -1, -1, |
| /* ICALL_BRANCH_FUNNEL */ |
| /* MEMBARRIER */ |
| /* G_ASSERT_SEXT */ |
| type0, type0, untyped_imm_0, |
| /* G_ASSERT_ZEXT */ |
| type0, type0, untyped_imm_0, |
| /* G_ASSERT_ALIGN */ |
| type0, type0, untyped_imm_0, |
| /* G_ADD */ |
| type0, type0, type0, |
| /* G_SUB */ |
| type0, type0, type0, |
| /* G_MUL */ |
| type0, type0, type0, |
| /* G_SDIV */ |
| type0, type0, type0, |
| /* G_UDIV */ |
| type0, type0, type0, |
| /* G_SREM */ |
| type0, type0, type0, |
| /* G_UREM */ |
| type0, type0, type0, |
| /* G_SDIVREM */ |
| type0, type0, type0, type0, |
| /* G_UDIVREM */ |
| type0, type0, type0, type0, |
| /* G_AND */ |
| type0, type0, type0, |
| /* G_OR */ |
| type0, type0, type0, |
| /* G_XOR */ |
| type0, type0, type0, |
| /* G_IMPLICIT_DEF */ |
| type0, |
| /* G_PHI */ |
| type0, |
| /* G_FRAME_INDEX */ |
| type0, -1, |
| /* G_GLOBAL_VALUE */ |
| type0, -1, |
| /* G_EXTRACT */ |
| type0, type1, untyped_imm_0, |
| /* G_UNMERGE_VALUES */ |
| type0, type1, |
| /* G_INSERT */ |
| type0, type0, type1, untyped_imm_0, |
| /* G_MERGE_VALUES */ |
| type0, type1, |
| /* G_BUILD_VECTOR */ |
| type0, type1, |
| /* G_BUILD_VECTOR_TRUNC */ |
| type0, type1, |
| /* G_CONCAT_VECTORS */ |
| type0, type1, |
| /* G_PTRTOINT */ |
| type0, type1, |
| /* G_INTTOPTR */ |
| type0, type1, |
| /* G_BITCAST */ |
| type0, type1, |
| /* G_FREEZE */ |
| type0, type0, |
| /* G_INTRINSIC_FPTRUNC_ROUND */ |
| type0, type1, i32imm, |
| /* G_INTRINSIC_TRUNC */ |
| type0, type0, |
| /* G_INTRINSIC_ROUND */ |
| type0, type0, |
| /* G_INTRINSIC_LRINT */ |
| type0, type1, |
| /* G_INTRINSIC_ROUNDEVEN */ |
| type0, type0, |
| /* G_READCYCLECOUNTER */ |
| type0, |
| /* G_LOAD */ |
| type0, ptype1, |
| /* G_SEXTLOAD */ |
| type0, ptype1, |
| /* G_ZEXTLOAD */ |
| type0, ptype1, |
| /* G_INDEXED_LOAD */ |
| type0, ptype1, ptype1, type2, -1, |
| /* G_INDEXED_SEXTLOAD */ |
| type0, ptype1, ptype1, type2, -1, |
| /* G_INDEXED_ZEXTLOAD */ |
| type0, ptype1, ptype1, type2, -1, |
| /* G_STORE */ |
| type0, ptype1, |
| /* G_INDEXED_STORE */ |
| ptype0, type1, ptype0, ptype2, -1, |
| /* G_ATOMIC_CMPXCHG_WITH_SUCCESS */ |
| type0, type1, type2, type0, type0, |
| /* G_ATOMIC_CMPXCHG */ |
| type0, ptype1, type0, type0, |
| /* G_ATOMICRMW_XCHG */ |
| type0, ptype1, type0, |
| /* G_ATOMICRMW_ADD */ |
| type0, ptype1, type0, |
| /* G_ATOMICRMW_SUB */ |
| type0, ptype1, type0, |
| /* G_ATOMICRMW_AND */ |
| type0, ptype1, type0, |
| /* G_ATOMICRMW_NAND */ |
| type0, ptype1, type0, |
| /* G_ATOMICRMW_OR */ |
| type0, ptype1, type0, |
| /* G_ATOMICRMW_XOR */ |
| type0, ptype1, type0, |
| /* G_ATOMICRMW_MAX */ |
| type0, ptype1, type0, |
| /* G_ATOMICRMW_MIN */ |
| type0, ptype1, type0, |
| /* G_ATOMICRMW_UMAX */ |
| type0, ptype1, type0, |
| /* G_ATOMICRMW_UMIN */ |
| type0, ptype1, type0, |
| /* G_ATOMICRMW_FADD */ |
| type0, ptype1, type0, |
| /* G_ATOMICRMW_FSUB */ |
| type0, ptype1, type0, |
| /* G_ATOMICRMW_FMAX */ |
| type0, ptype1, type0, |
| /* G_ATOMICRMW_FMIN */ |
| type0, ptype1, type0, |
| /* G_ATOMICRMW_UINC_WRAP */ |
| type0, ptype1, type0, |
| /* G_ATOMICRMW_UDEC_WRAP */ |
| type0, ptype1, type0, |
| /* G_FENCE */ |
| i32imm, i32imm, |
| /* G_BRCOND */ |
| type0, -1, |
| /* G_BRINDIRECT */ |
| type0, |
| /* G_INVOKE_REGION_START */ |
| /* G_INTRINSIC */ |
| -1, |
| /* G_INTRINSIC_W_SIDE_EFFECTS */ |
| -1, |
| /* G_ANYEXT */ |
| type0, type1, |
| /* G_TRUNC */ |
| type0, type1, |
| /* G_CONSTANT */ |
| type0, -1, |
| /* G_FCONSTANT */ |
| type0, -1, |
| /* G_VASTART */ |
| type0, |
| /* G_VAARG */ |
| type0, type1, -1, |
| /* G_SEXT */ |
| type0, type1, |
| /* G_SEXT_INREG */ |
| type0, type0, untyped_imm_0, |
| /* G_ZEXT */ |
| type0, type1, |
| /* G_SHL */ |
| type0, type0, type1, |
| /* G_LSHR */ |
| type0, type0, type1, |
| /* G_ASHR */ |
| type0, type0, type1, |
| /* G_FSHL */ |
| type0, type0, type0, type1, |
| /* G_FSHR */ |
| type0, type0, type0, type1, |
| /* G_ROTR */ |
| type0, type0, type1, |
| /* G_ROTL */ |
| type0, type0, type1, |
| /* G_ICMP */ |
| type0, -1, type1, type1, |
| /* G_FCMP */ |
| type0, -1, type1, type1, |
| /* G_SELECT */ |
| type0, type1, type0, type0, |
| /* G_UADDO */ |
| type0, type1, type0, type0, |
| /* G_UADDE */ |
| type0, type1, type0, type0, type1, |
| /* G_USUBO */ |
| type0, type1, type0, type0, |
| /* G_USUBE */ |
| type0, type1, type0, type0, type1, |
| /* G_SADDO */ |
| type0, type1, type0, type0, |
| /* G_SADDE */ |
| type0, type1, type0, type0, type1, |
| /* G_SSUBO */ |
| type0, type1, type0, type0, |
| /* G_SSUBE */ |
| type0, type1, type0, type0, type1, |
| /* G_UMULO */ |
| type0, type1, type0, type0, |
| /* G_SMULO */ |
| type0, type1, type0, type0, |
| /* G_UMULH */ |
| type0, type0, type0, |
| /* G_SMULH */ |
| type0, type0, type0, |
| /* G_UADDSAT */ |
| type0, type0, type0, |
| /* G_SADDSAT */ |
| type0, type0, type0, |
| /* G_USUBSAT */ |
| type0, type0, type0, |
| /* G_SSUBSAT */ |
| type0, type0, type0, |
| /* G_USHLSAT */ |
| type0, type0, type1, |
| /* G_SSHLSAT */ |
| type0, type0, type1, |
| /* G_SMULFIX */ |
| type0, type0, type0, untyped_imm_0, |
| /* G_UMULFIX */ |
| type0, type0, type0, untyped_imm_0, |
| /* G_SMULFIXSAT */ |
| type0, type0, type0, untyped_imm_0, |
| /* G_UMULFIXSAT */ |
| type0, type0, type0, untyped_imm_0, |
| /* G_SDIVFIX */ |
| type0, type0, type0, untyped_imm_0, |
| /* G_UDIVFIX */ |
| type0, type0, type0, untyped_imm_0, |
| /* G_SDIVFIXSAT */ |
| type0, type0, type0, untyped_imm_0, |
| /* G_UDIVFIXSAT */ |
| type0, type0, type0, untyped_imm_0, |
| /* G_FADD */ |
| type0, type0, type0, |
| /* G_FSUB */ |
| type0, type0, type0, |
| /* G_FMUL */ |
| type0, type0, type0, |
| /* G_FMA */ |
| type0, type0, type0, type0, |
| /* G_FMAD */ |
| type0, type0, type0, type0, |
| /* G_FDIV */ |
| type0, type0, type0, |
| /* G_FREM */ |
| type0, type0, type0, |
| /* G_FPOW */ |
| type0, type0, type0, |
| /* G_FPOWI */ |
| type0, type0, type1, |
| /* G_FEXP */ |
| type0, type0, |
| /* G_FEXP2 */ |
| type0, type0, |
| /* G_FLOG */ |
| type0, type0, |
| /* G_FLOG2 */ |
| type0, type0, |
| /* G_FLOG10 */ |
| type0, type0, |
| /* G_FNEG */ |
| type0, type0, |
| /* G_FPEXT */ |
| type0, type1, |
| /* G_FPTRUNC */ |
| type0, type1, |
| /* G_FPTOSI */ |
| type0, type1, |
| /* G_FPTOUI */ |
| type0, type1, |
| /* G_SITOFP */ |
| type0, type1, |
| /* G_UITOFP */ |
| type0, type1, |
| /* G_FABS */ |
| type0, type0, |
| /* G_FCOPYSIGN */ |
| type0, type0, type1, |
| /* G_IS_FPCLASS */ |
| type0, type1, -1, |
| /* G_FCANONICALIZE */ |
| type0, type0, |
| /* G_FMINNUM */ |
| type0, type0, type0, |
| /* G_FMAXNUM */ |
| type0, type0, type0, |
| /* G_FMINNUM_IEEE */ |
| type0, type0, type0, |
| /* G_FMAXNUM_IEEE */ |
| type0, type0, type0, |
| /* G_FMINIMUM */ |
| type0, type0, type0, |
| /* G_FMAXIMUM */ |
| type0, type0, type0, |
| /* G_PTR_ADD */ |
| ptype0, ptype0, type1, |
| /* G_PTRMASK */ |
| ptype0, ptype0, type1, |
| /* G_SMIN */ |
| type0, type0, type0, |
| /* G_SMAX */ |
| type0, type0, type0, |
| /* G_UMIN */ |
| type0, type0, type0, |
| /* G_UMAX */ |
| type0, type0, type0, |
| /* G_ABS */ |
| type0, type0, |
| /* G_LROUND */ |
| type0, type1, |
| /* G_LLROUND */ |
| type0, type1, |
| /* G_BR */ |
| -1, |
| /* G_BRJT */ |
| ptype0, -1, type1, |
| /* G_INSERT_VECTOR_ELT */ |
| type0, type0, type1, type2, |
| /* G_EXTRACT_VECTOR_ELT */ |
| type0, type1, type2, |
| /* G_SHUFFLE_VECTOR */ |
| type0, type1, type1, -1, |
| /* G_CTTZ */ |
| type0, type1, |
| /* G_CTTZ_ZERO_UNDEF */ |
| type0, type1, |
| /* G_CTLZ */ |
| type0, type1, |
| /* G_CTLZ_ZERO_UNDEF */ |
| type0, type1, |
| /* G_CTPOP */ |
| type0, type1, |
| /* G_BSWAP */ |
| type0, type0, |
| /* G_BITREVERSE */ |
| type0, type0, |
| /* G_FCEIL */ |
| type0, type0, |
| /* G_FCOS */ |
| type0, type0, |
| /* G_FSIN */ |
| type0, type0, |
| /* G_FSQRT */ |
| type0, type0, |
| /* G_FFLOOR */ |
| type0, type0, |
| /* G_FRINT */ |
| type0, type0, |
| /* G_FNEARBYINT */ |
| type0, type0, |
| /* G_ADDRSPACE_CAST */ |
| type0, type1, |
| /* G_BLOCK_ADDR */ |
| type0, -1, |
| /* G_JUMP_TABLE */ |
| type0, -1, |
| /* G_DYN_STACKALLOC */ |
| ptype0, type1, i32imm, |
| /* G_STRICT_FADD */ |
| type0, type0, type0, |
| /* G_STRICT_FSUB */ |
| type0, type0, type0, |
| /* G_STRICT_FMUL */ |
| type0, type0, type0, |
| /* G_STRICT_FDIV */ |
| type0, type0, type0, |
| /* G_STRICT_FREM */ |
| type0, type0, type0, |
| /* G_STRICT_FMA */ |
| type0, type0, type0, type0, |
| /* G_STRICT_FSQRT */ |
| type0, type0, |
| /* G_READ_REGISTER */ |
| type0, -1, |
| /* G_WRITE_REGISTER */ |
| -1, type0, |
| /* G_MEMCPY */ |
| ptype0, ptype1, type2, untyped_imm_0, |
| /* G_MEMCPY_INLINE */ |
| ptype0, ptype1, type2, |
| /* G_MEMMOVE */ |
| ptype0, ptype1, type2, untyped_imm_0, |
| /* G_MEMSET */ |
| ptype0, type1, type2, untyped_imm_0, |
| /* G_BZERO */ |
| ptype0, type1, untyped_imm_0, |
| /* G_VECREDUCE_SEQ_FADD */ |
| type0, type1, type2, |
| /* G_VECREDUCE_SEQ_FMUL */ |
| type0, type1, type2, |
| /* G_VECREDUCE_FADD */ |
| type0, type1, |
| /* G_VECREDUCE_FMUL */ |
| type0, type1, |
| /* G_VECREDUCE_FMAX */ |
| type0, type1, |
| /* G_VECREDUCE_FMIN */ |
| type0, type1, |
| /* G_VECREDUCE_ADD */ |
| type0, type1, |
| /* G_VECREDUCE_MUL */ |
| type0, type1, |
| /* G_VECREDUCE_AND */ |
| type0, type1, |
| /* G_VECREDUCE_OR */ |
| type0, type1, |
| /* G_VECREDUCE_XOR */ |
| type0, type1, |
| /* G_VECREDUCE_SMAX */ |
| type0, type1, |
| /* G_VECREDUCE_SMIN */ |
| type0, type1, |
| /* G_VECREDUCE_UMAX */ |
| type0, type1, |
| /* G_VECREDUCE_UMIN */ |
| type0, type1, |
| /* G_SBFX */ |
| type0, type0, type1, type1, |
| /* G_UBFX */ |
| type0, type0, type1, type1, |
| /* ABSMacro */ |
| GPR32Opnd, GPR32Opnd, |
| /* ADJCALLSTACKDOWN */ |
| i32imm, i32imm, |
| /* ADJCALLSTACKUP */ |
| i32imm, i32imm, |
| /* AND_V_D_PSEUDO */ |
| MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
| /* AND_V_H_PSEUDO */ |
| MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
| /* AND_V_W_PSEUDO */ |
| MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* ATOMIC_CMP_SWAP_I16 */ |
| GPR32, -1, GPR32, GPR32, |
| /* ATOMIC_CMP_SWAP_I16_POSTRA */ |
| GPR32, -1, GPR32, GPR32, GPR32, GPR32, GPR32, |
| /* ATOMIC_CMP_SWAP_I32 */ |
| GPR32, -1, GPR32, GPR32, |
| /* ATOMIC_CMP_SWAP_I32_POSTRA */ |
| GPR32, -1, GPR32, GPR32, |
| /* ATOMIC_CMP_SWAP_I64 */ |
| GPR64, -1, GPR64, GPR64, |
| /* ATOMIC_CMP_SWAP_I64_POSTRA */ |
| GPR64, -1, GPR64, GPR64, |
| /* ATOMIC_CMP_SWAP_I8 */ |
| GPR32, -1, GPR32, GPR32, |
| /* ATOMIC_CMP_SWAP_I8_POSTRA */ |
| GPR32, -1, GPR32, GPR32, GPR32, GPR32, GPR32, |
| /* ATOMIC_LOAD_ADD_I16 */ |
| GPR32, -1, GPR32, |
| /* ATOMIC_LOAD_ADD_I16_POSTRA */ |
| GPR32, -1, GPR32, GPR32, GPR32, GPR32, |
| /* ATOMIC_LOAD_ADD_I32 */ |
| GPR32, -1, GPR32, |
| /* ATOMIC_LOAD_ADD_I32_POSTRA */ |
| GPR32, -1, GPR32, |
| /* ATOMIC_LOAD_ADD_I64 */ |
| GPR64, -1, GPR64, |
| /* ATOMIC_LOAD_ADD_I64_POSTRA */ |
| GPR64, -1, GPR64, |
| /* ATOMIC_LOAD_ADD_I8 */ |
| GPR32, -1, GPR32, |
| /* ATOMIC_LOAD_ADD_I8_POSTRA */ |
| GPR32, -1, GPR32, GPR32, GPR32, GPR32, |
| /* ATOMIC_LOAD_AND_I16 */ |
| GPR32, -1, GPR32, |
| /* ATOMIC_LOAD_AND_I16_POSTRA */ |
| GPR32, -1, GPR32, GPR32, GPR32, GPR32, |
| /* ATOMIC_LOAD_AND_I32 */ |
| GPR32, -1, GPR32, |
| /* ATOMIC_LOAD_AND_I32_POSTRA */ |
| GPR32, -1, GPR32, |
| /* ATOMIC_LOAD_AND_I64 */ |
| GPR64, -1, GPR64, |
| /* ATOMIC_LOAD_AND_I64_POSTRA */ |
| GPR64, -1, GPR64, |
| /* ATOMIC_LOAD_AND_I8 */ |
| GPR32, -1, GPR32, |
| /* ATOMIC_LOAD_AND_I8_POSTRA */ |
| GPR32, -1, GPR32, GPR32, GPR32, GPR32, |
| /* ATOMIC_LOAD_MAX_I16 */ |
| GPR32, -1, GPR32, |
| /* ATOMIC_LOAD_MAX_I16_POSTRA */ |
| GPR32, -1, GPR32, GPR32, GPR32, GPR32, |
| /* ATOMIC_LOAD_MAX_I32 */ |
| GPR32, -1, GPR32, |
| /* ATOMIC_LOAD_MAX_I32_POSTRA */ |
| GPR32, -1, GPR32, |
| /* ATOMIC_LOAD_MAX_I64 */ |
| GPR64, -1, GPR64, |
| /* ATOMIC_LOAD_MAX_I64_POSTRA */ |
| GPR64, -1, GPR64, |
| /* ATOMIC_LOAD_MAX_I8 */ |
| GPR32, -1, GPR32, |
| /* ATOMIC_LOAD_MAX_I8_POSTRA */ |
| GPR32, -1, GPR32, GPR32, GPR32, GPR32, |
| /* ATOMIC_LOAD_MIN_I16 */ |
| GPR32, -1, GPR32, |
| /* ATOMIC_LOAD_MIN_I16_POSTRA */ |
| GPR32, -1, GPR32, GPR32, GPR32, GPR32, |
| /* ATOMIC_LOAD_MIN_I32 */ |
| GPR32, -1, GPR32, |
| /* ATOMIC_LOAD_MIN_I32_POSTRA */ |
| GPR32, -1, GPR32, |
| /* ATOMIC_LOAD_MIN_I64 */ |
| GPR64, -1, GPR64, |
| /* ATOMIC_LOAD_MIN_I64_POSTRA */ |
| GPR64, -1, GPR64, |
| /* ATOMIC_LOAD_MIN_I8 */ |
| GPR32, -1, GPR32, |
| /* ATOMIC_LOAD_MIN_I8_POSTRA */ |
| GPR32, -1, GPR32, GPR32, GPR32, GPR32, |
| /* ATOMIC_LOAD_NAND_I16 */ |
| GPR32, -1, GPR32, |
| /* ATOMIC_LOAD_NAND_I16_POSTRA */ |
| GPR32, -1, GPR32, GPR32, GPR32, GPR32, |
| /* ATOMIC_LOAD_NAND_I32 */ |
| GPR32, -1, GPR32, |
| /* ATOMIC_LOAD_NAND_I32_POSTRA */ |
| GPR32, -1, GPR32, |
| /* ATOMIC_LOAD_NAND_I64 */ |
| GPR64, -1, GPR64, |
| /* ATOMIC_LOAD_NAND_I64_POSTRA */ |
| GPR64, -1, GPR64, |
| /* ATOMIC_LOAD_NAND_I8 */ |
| GPR32, -1, GPR32, |
| /* ATOMIC_LOAD_NAND_I8_POSTRA */ |
| GPR32, -1, GPR32, GPR32, GPR32, GPR32, |
| /* ATOMIC_LOAD_OR_I16 */ |
| GPR32, -1, GPR32, |
| /* ATOMIC_LOAD_OR_I16_POSTRA */ |
| GPR32, -1, GPR32, GPR32, GPR32, GPR32, |
| /* ATOMIC_LOAD_OR_I32 */ |
| GPR32, -1, GPR32, |
| /* ATOMIC_LOAD_OR_I32_POSTRA */ |
| GPR32, -1, GPR32, |
| /* ATOMIC_LOAD_OR_I64 */ |
| GPR64, -1, GPR64, |
| /* ATOMIC_LOAD_OR_I64_POSTRA */ |
| GPR64, -1, GPR64, |
| /* ATOMIC_LOAD_OR_I8 */ |
| GPR32, -1, GPR32, |
| /* ATOMIC_LOAD_OR_I8_POSTRA */ |
| GPR32, -1, GPR32, GPR32, GPR32, GPR32, |
| /* ATOMIC_LOAD_SUB_I16 */ |
| GPR32, -1, GPR32, |
| /* ATOMIC_LOAD_SUB_I16_POSTRA */ |
| GPR32, -1, GPR32, GPR32, GPR32, GPR32, |
| /* ATOMIC_LOAD_SUB_I32 */ |
| GPR32, -1, GPR32, |
| /* ATOMIC_LOAD_SUB_I32_POSTRA */ |
| GPR32, -1, GPR32, |
| /* ATOMIC_LOAD_SUB_I64 */ |
| GPR64, -1, GPR64, |
| /* ATOMIC_LOAD_SUB_I64_POSTRA */ |
| GPR64, -1, GPR64, |
| /* ATOMIC_LOAD_SUB_I8 */ |
| GPR32, -1, GPR32, |
| /* ATOMIC_LOAD_SUB_I8_POSTRA */ |
| GPR32, -1, GPR32, GPR32, GPR32, GPR32, |
| /* ATOMIC_LOAD_UMAX_I16 */ |
| GPR32, -1, GPR32, |
| /* ATOMIC_LOAD_UMAX_I16_POSTRA */ |
| GPR32, -1, GPR32, GPR32, GPR32, GPR32, |
| /* ATOMIC_LOAD_UMAX_I32 */ |
| GPR32, -1, GPR32, |
| /* ATOMIC_LOAD_UMAX_I32_POSTRA */ |
| GPR32, -1, GPR32, |
| /* ATOMIC_LOAD_UMAX_I64 */ |
| GPR64, -1, GPR64, |
| /* ATOMIC_LOAD_UMAX_I64_POSTRA */ |
| GPR64, -1, GPR64, |
| /* ATOMIC_LOAD_UMAX_I8 */ |
| GPR32, -1, GPR32, |
| /* ATOMIC_LOAD_UMAX_I8_POSTRA */ |
| GPR32, -1, GPR32, GPR32, GPR32, GPR32, |
| /* ATOMIC_LOAD_UMIN_I16 */ |
| GPR32, -1, GPR32, |
| /* ATOMIC_LOAD_UMIN_I16_POSTRA */ |
| GPR32, -1, GPR32, GPR32, GPR32, GPR32, |
| /* ATOMIC_LOAD_UMIN_I32 */ |
| GPR32, -1, GPR32, |
| /* ATOMIC_LOAD_UMIN_I32_POSTRA */ |
| GPR32, -1, GPR32, |
| /* ATOMIC_LOAD_UMIN_I64 */ |
| GPR64, -1, GPR64, |
| /* ATOMIC_LOAD_UMIN_I64_POSTRA */ |
| GPR64, -1, GPR64, |
| /* ATOMIC_LOAD_UMIN_I8 */ |
| GPR32, -1, GPR32, |
| /* ATOMIC_LOAD_UMIN_I8_POSTRA */ |
| GPR32, -1, GPR32, GPR32, GPR32, GPR32, |
| /* ATOMIC_LOAD_XOR_I16 */ |
| GPR32, -1, GPR32, |
| /* ATOMIC_LOAD_XOR_I16_POSTRA */ |
| GPR32, -1, GPR32, GPR32, GPR32, GPR32, |
| /* ATOMIC_LOAD_XOR_I32 */ |
| GPR32, -1, GPR32, |
| /* ATOMIC_LOAD_XOR_I32_POSTRA */ |
| GPR32, -1, GPR32, |
| /* ATOMIC_LOAD_XOR_I64 */ |
| GPR64, -1, GPR64, |
| /* ATOMIC_LOAD_XOR_I64_POSTRA */ |
| GPR64, -1, GPR64, |
| /* ATOMIC_LOAD_XOR_I8 */ |
| GPR32, -1, GPR32, |
| /* ATOMIC_LOAD_XOR_I8_POSTRA */ |
| GPR32, -1, GPR32, GPR32, GPR32, GPR32, |
| /* ATOMIC_SWAP_I16 */ |
| GPR32, -1, GPR32, |
| /* ATOMIC_SWAP_I16_POSTRA */ |
| GPR32, -1, GPR32, GPR32, GPR32, GPR32, |
| /* ATOMIC_SWAP_I32 */ |
| GPR32, -1, GPR32, |
| /* ATOMIC_SWAP_I32_POSTRA */ |
| GPR32, -1, GPR32, |
| /* ATOMIC_SWAP_I64 */ |
| GPR64, -1, GPR64, |
| /* ATOMIC_SWAP_I64_POSTRA */ |
| GPR64, -1, GPR64, |
| /* ATOMIC_SWAP_I8 */ |
| GPR32, -1, GPR32, |
| /* ATOMIC_SWAP_I8_POSTRA */ |
| GPR32, -1, GPR32, GPR32, GPR32, GPR32, |
| /* B */ |
| brtarget, |
| /* BAL_BR */ |
| brtarget, |
| /* BAL_BR_MM */ |
| brtarget_mm, |
| /* BEQLImmMacro */ |
| GPR32Opnd, imm64, brtarget, |
| /* BGE */ |
| GPR32Opnd, GPR32Opnd, brtarget, |
| /* BGEImmMacro */ |
| GPR32Opnd, imm64, brtarget, |
| /* BGEL */ |
| GPR32Opnd, GPR32Opnd, brtarget, |
| /* BGELImmMacro */ |
| GPR32Opnd, imm64, brtarget, |
| /* BGEU */ |
| GPR32Opnd, GPR32Opnd, brtarget, |
| /* BGEUImmMacro */ |
| GPR32Opnd, imm64, brtarget, |
| /* BGEUL */ |
| GPR32Opnd, GPR32Opnd, brtarget, |
| /* BGEULImmMacro */ |
| GPR32Opnd, imm64, brtarget, |
| /* BGT */ |
| GPR32Opnd, GPR32Opnd, brtarget, |
| /* BGTImmMacro */ |
| GPR32Opnd, imm64, brtarget, |
| /* BGTL */ |
| GPR32Opnd, GPR32Opnd, brtarget, |
| /* BGTLImmMacro */ |
| GPR32Opnd, imm64, brtarget, |
| /* BGTU */ |
| GPR32Opnd, GPR32Opnd, brtarget, |
| /* BGTUImmMacro */ |
| GPR32Opnd, imm64, brtarget, |
| /* BGTUL */ |
| GPR32Opnd, GPR32Opnd, brtarget, |
| /* BGTULImmMacro */ |
| GPR32Opnd, imm64, brtarget, |
| /* BLE */ |
| GPR32Opnd, GPR32Opnd, brtarget, |
| /* BLEImmMacro */ |
| GPR32Opnd, imm64, brtarget, |
| /* BLEL */ |
| GPR32Opnd, GPR32Opnd, brtarget, |
| /* BLELImmMacro */ |
| GPR32Opnd, imm64, brtarget, |
| /* BLEU */ |
| GPR32Opnd, GPR32Opnd, brtarget, |
| /* BLEUImmMacro */ |
| GPR32Opnd, imm64, brtarget, |
| /* BLEUL */ |
| GPR32Opnd, GPR32Opnd, brtarget, |
| /* BLEULImmMacro */ |
| GPR32Opnd, imm64, brtarget, |
| /* BLT */ |
| GPR32Opnd, GPR32Opnd, brtarget, |
| /* BLTImmMacro */ |
| GPR32Opnd, imm64, brtarget, |
| /* BLTL */ |
| GPR32Opnd, GPR32Opnd, brtarget, |
| /* BLTLImmMacro */ |
| GPR32Opnd, imm64, brtarget, |
| /* BLTU */ |
| GPR32Opnd, GPR32Opnd, brtarget, |
| /* BLTUImmMacro */ |
| GPR32Opnd, imm64, brtarget, |
| /* BLTUL */ |
| GPR32Opnd, GPR32Opnd, brtarget, |
| /* BLTULImmMacro */ |
| GPR32Opnd, imm64, brtarget, |
| /* BNELImmMacro */ |
| GPR32Opnd, imm64, brtarget, |
| /* BPOSGE32_PSEUDO */ |
| GPR32Opnd, |
| /* BSEL_D_PSEUDO */ |
| MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
| /* BSEL_FD_PSEUDO */ |
| MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
| /* BSEL_FW_PSEUDO */ |
| MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* BSEL_H_PSEUDO */ |
| MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
| /* BSEL_W_PSEUDO */ |
| MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* B_MM */ |
| brtarget, |
| /* B_MMR6_Pseudo */ |
| brtarget_mm, |
| /* B_MM_Pseudo */ |
| brtarget_mm, |
| /* BeqImm */ |
| GPR32Opnd, imm64, brtarget, |
| /* BneImm */ |
| GPR32Opnd, imm64, brtarget, |
| /* BteqzT8CmpX16 */ |
| CPU16Regs, CPU16Regs, brtarget, |
| /* BteqzT8CmpiX16 */ |
| CPU16Regs, simm16, brtarget, |
| /* BteqzT8SltX16 */ |
| CPU16Regs, CPU16Regs, brtarget, |
| /* BteqzT8SltiX16 */ |
| CPU16Regs, simm16, brtarget, |
| /* BteqzT8SltiuX16 */ |
| CPU16Regs, simm16, brtarget, |
| /* BteqzT8SltuX16 */ |
| CPU16Regs, CPU16Regs, brtarget, |
| /* BtnezT8CmpX16 */ |
| CPU16Regs, CPU16Regs, brtarget, |
| /* BtnezT8CmpiX16 */ |
| CPU16Regs, simm16, brtarget, |
| /* BtnezT8SltX16 */ |
| CPU16Regs, CPU16Regs, brtarget, |
| /* BtnezT8SltiX16 */ |
| CPU16Regs, simm16, brtarget, |
| /* BtnezT8SltiuX16 */ |
| CPU16Regs, simm16, brtarget, |
| /* BtnezT8SltuX16 */ |
| CPU16Regs, CPU16Regs, brtarget, |
| /* BuildPairF64 */ |
| AFGR64Opnd, GPR32Opnd, GPR32Opnd, |
| /* BuildPairF64_64 */ |
| FGR64Opnd, GPR32Opnd, GPR32Opnd, |
| /* CFTC1 */ |
| GPR32Opnd, FGRCCOpnd, |
| /* CONSTPOOL_ENTRY */ |
| cpinst_operand, cpinst_operand, i32imm, |
| /* COPY_FD_PSEUDO */ |
| FGR64, MSA128D, uimm1_ptr, |
| /* COPY_FW_PSEUDO */ |
| FGR32, MSA128W, uimm2_ptr, |
| /* CTTC1 */ |
| FGRCCOpnd, GPR32Opnd, |
| /* Constant32 */ |
| simm32, |
| /* DMULImmMacro */ |
| GPR64Opnd, GPR64Opnd, simm32_relaxed, |
| /* DMULMacro */ |
| GPR64Opnd, GPR64Opnd, GPR64Opnd, |
| /* DMULOMacro */ |
| GPR64Opnd, GPR64Opnd, GPR64Opnd, |
| /* DMULOUMacro */ |
| GPR64Opnd, GPR64Opnd, GPR64Opnd, |
| /* DROL */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* DROLImm */ |
| GPR32Opnd, GPR32Opnd, simm16, |
| /* DROR */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* DRORImm */ |
| GPR32Opnd, GPR32Opnd, simm16, |
| /* DSDivIMacro */ |
| GPR64Opnd, GPR64Opnd, imm64, |
| /* DSDivMacro */ |
| GPR64Opnd, GPR64Opnd, GPR64Opnd, |
| /* DSRemIMacro */ |
| GPR64Opnd, GPR64Opnd, simm32_relaxed, |
| /* DSRemMacro */ |
| GPR64Opnd, GPR64Opnd, GPR64Opnd, |
| /* DUDivIMacro */ |
| GPR64Opnd, GPR64Opnd, imm64, |
| /* DUDivMacro */ |
| GPR64Opnd, GPR64Opnd, GPR64Opnd, |
| /* DURemIMacro */ |
| GPR64Opnd, GPR64Opnd, simm32_relaxed, |
| /* DURemMacro */ |
| GPR64Opnd, GPR64Opnd, GPR64Opnd, |
| /* ERet */ |
| /* ExtractElementF64 */ |
| GPR32Opnd, AFGR64Opnd, i32imm, |
| /* ExtractElementF64_64 */ |
| GPR32Opnd, FGR64Opnd, i32imm, |
| /* FABS_D */ |
| MSA128DOpnd, MSA128DOpnd, |
| /* FABS_W */ |
| MSA128WOpnd, MSA128WOpnd, |
| /* FEXP2_D_1_PSEUDO */ |
| MSA128D, MSA128D, |
| /* FEXP2_W_1_PSEUDO */ |
| MSA128W, MSA128W, |
| /* FILL_FD_PSEUDO */ |
| MSA128D, FGR64, |
| /* FILL_FW_PSEUDO */ |
| MSA128W, FGR32, |
| /* GotPrologue16 */ |
| CPU16Regs, CPU16Regs, simm16, simm16, |
| /* INSERT_B_VIDX64_PSEUDO */ |
| MSA128BOpnd, MSA128BOpnd, GPR64Opnd, GPR32Opnd, |
| /* INSERT_B_VIDX_PSEUDO */ |
| MSA128BOpnd, MSA128BOpnd, GPR32Opnd, GPR32Opnd, |
| /* INSERT_D_VIDX64_PSEUDO */ |
| MSA128DOpnd, MSA128DOpnd, GPR64Opnd, GPR64Opnd, |
| /* INSERT_D_VIDX_PSEUDO */ |
| MSA128DOpnd, MSA128DOpnd, GPR32Opnd, GPR64Opnd, |
| /* INSERT_FD_PSEUDO */ |
| MSA128DOpnd, MSA128DOpnd, uimm1, FGR64Opnd, |
| /* INSERT_FD_VIDX64_PSEUDO */ |
| MSA128DOpnd, MSA128DOpnd, GPR64Opnd, FGR64Opnd, |
| /* INSERT_FD_VIDX_PSEUDO */ |
| MSA128DOpnd, MSA128DOpnd, GPR32Opnd, FGR64Opnd, |
| /* INSERT_FW_PSEUDO */ |
| MSA128WOpnd, MSA128WOpnd, uimm2, FGR32Opnd, |
| /* INSERT_FW_VIDX64_PSEUDO */ |
| MSA128WOpnd, MSA128WOpnd, GPR64Opnd, FGR32Opnd, |
| /* INSERT_FW_VIDX_PSEUDO */ |
| MSA128WOpnd, MSA128WOpnd, GPR32Opnd, FGR32Opnd, |
| /* INSERT_H_VIDX64_PSEUDO */ |
| MSA128HOpnd, MSA128HOpnd, GPR64Opnd, GPR32Opnd, |
| /* INSERT_H_VIDX_PSEUDO */ |
| MSA128HOpnd, MSA128HOpnd, GPR32Opnd, GPR32Opnd, |
| /* INSERT_W_VIDX64_PSEUDO */ |
| MSA128WOpnd, MSA128WOpnd, GPR64Opnd, GPR32Opnd, |
| /* INSERT_W_VIDX_PSEUDO */ |
| MSA128WOpnd, MSA128WOpnd, GPR32Opnd, GPR32Opnd, |
| /* JALR64Pseudo */ |
| GPR64Opnd, |
| /* JALRHB64Pseudo */ |
| GPR64Opnd, |
| /* JALRHBPseudo */ |
| GPR32Opnd, |
| /* JALRPseudo */ |
| GPR32Opnd, |
| /* JAL_MMR6 */ |
| calltarget, |
| /* JalOneReg */ |
| GPR32Opnd, |
| /* JalTwoReg */ |
| GPR32Opnd, GPR32Opnd, |
| /* LDMacro */ |
| GPR32Opnd, -1, simm16, |
| /* LDR_D */ |
| MSA128DOpnd, -1, GPR32, |
| /* LDR_W */ |
| MSA128WOpnd, -1, GPR32, |
| /* LD_F16 */ |
| MSA128F16, -1, simm10, |
| /* LOAD_ACC128 */ |
| ACC128, -1, simm16, |
| /* LOAD_ACC64 */ |
| ACC64, -1, simm16, |
| /* LOAD_ACC64DSP */ |
| ACC64DSPOpnd, -1, simm16, |
| /* LOAD_CCOND_DSP */ |
| DSPCC, -1, simm16, |
| /* LONG_BRANCH_ADDiu */ |
| GPR32Opnd, GPR32Opnd, brtarget, brtarget, |
| /* LONG_BRANCH_ADDiu2Op */ |
| GPR32Opnd, GPR32Opnd, brtarget, |
| /* LONG_BRANCH_DADDiu */ |
| GPR64Opnd, GPR64Opnd, brtarget, brtarget, |
| /* LONG_BRANCH_DADDiu2Op */ |
| GPR64Opnd, GPR64Opnd, brtarget, |
| /* LONG_BRANCH_LUi */ |
| GPR32Opnd, brtarget, brtarget, |
| /* LONG_BRANCH_LUi2Op */ |
| GPR32Opnd, brtarget, |
| /* LONG_BRANCH_LUi2Op_64 */ |
| GPR64Opnd, brtarget, |
| /* LWM_MM */ |
| reglist, -1, simm12, |
| /* LoadAddrImm32 */ |
| GPR32Opnd, i32imm, |
| /* LoadAddrImm64 */ |
| GPR64Opnd, imm64, |
| /* LoadAddrReg32 */ |
| GPR32Opnd, -1, simm16, |
| /* LoadAddrReg64 */ |
| GPR64Opnd, -1, simm16, |
| /* LoadImm32 */ |
| GPR32Opnd, uimm32_coerced, |
| /* LoadImm64 */ |
| GPR64Opnd, imm64, |
| /* LoadImmDoubleFGR */ |
| StrictlyFGR64Opnd, imm64, |
| /* LoadImmDoubleFGR_32 */ |
| StrictlyAFGR64Opnd, imm64, |
| /* LoadImmDoubleGPR */ |
| GPR32Opnd, imm64, |
| /* LoadImmSingleFGR */ |
| StrictlyFGR32Opnd, imm64, |
| /* LoadImmSingleGPR */ |
| GPR32Opnd, imm64, |
| /* LwConstant32 */ |
| CPU16Regs, simm32, simm32, |
| /* MFTACX */ |
| GPR32Opnd, ACC64DSPOpnd, |
| /* MFTC0 */ |
| GPR32Opnd, COP0Opnd, uimm3, |
| /* MFTC1 */ |
| GPR32Opnd, FGR32Opnd, |
| /* MFTDSP */ |
| GPR32Opnd, |
| /* MFTGPR */ |
| GPR32Opnd, GPR32Opnd, uimm3, |
| /* MFTHC1 */ |
| GPR32Opnd, FGR32Opnd, |
| /* MFTHI */ |
| GPR32Opnd, ACC64DSPOpnd, |
| /* MFTLO */ |
| GPR32Opnd, ACC64DSPOpnd, |
| /* MIPSeh_return32 */ |
| GPR32, GPR32, |
| /* MIPSeh_return64 */ |
| GPR64, GPR64, |
| /* MSA_FP_EXTEND_D_PSEUDO */ |
| FGR64Opnd, MSA128F16, |
| /* MSA_FP_EXTEND_W_PSEUDO */ |
| FGR32Opnd, MSA128F16, |
| /* MSA_FP_ROUND_D_PSEUDO */ |
| MSA128F16, FGR64Opnd, |
| /* MSA_FP_ROUND_W_PSEUDO */ |
| MSA128F16, FGR32Opnd, |
| /* MTTACX */ |
| ACC64DSPOpnd, GPR32Opnd, |
| /* MTTC0 */ |
| COP0Opnd, GPR32Opnd, uimm3, |
| /* MTTC1 */ |
| FGR32Opnd, GPR32Opnd, |
| /* MTTDSP */ |
| GPR32Opnd, |
| /* MTTGPR */ |
| GPR32Opnd, GPR32Opnd, |
| /* MTTHC1 */ |
| FGR32Opnd, GPR32Opnd, |
| /* MTTHI */ |
| ACC64DSPOpnd, GPR32Opnd, |
| /* MTTLO */ |
| ACC64DSPOpnd, GPR32Opnd, |
| /* MULImmMacro */ |
| GPR32Opnd, GPR32Opnd, simm32_relaxed, |
| /* MULOMacro */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* MULOUMacro */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* MultRxRy16 */ |
| CPU16Regs, CPU16Regs, |
| /* MultRxRyRz16 */ |
| CPU16Regs, CPU16Regs, CPU16Regs, |
| /* MultuRxRy16 */ |
| CPU16Regs, CPU16Regs, |
| /* MultuRxRyRz16 */ |
| CPU16Regs, CPU16Regs, CPU16Regs, |
| /* NOP */ |
| /* NORImm */ |
| GPR32Opnd, GPR32Opnd, simm32_relaxed, |
| /* NORImm64 */ |
| GPR64Opnd, GPR64Opnd, imm64, |
| /* NOR_V_D_PSEUDO */ |
| MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
| /* NOR_V_H_PSEUDO */ |
| MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
| /* NOR_V_W_PSEUDO */ |
| MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* OR_V_D_PSEUDO */ |
| MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
| /* OR_V_H_PSEUDO */ |
| MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
| /* OR_V_W_PSEUDO */ |
| MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* PseudoCMPU_EQ_QB */ |
| DSPCC, DSPROpnd, DSPROpnd, |
| /* PseudoCMPU_LE_QB */ |
| DSPCC, DSPROpnd, DSPROpnd, |
| /* PseudoCMPU_LT_QB */ |
| DSPCC, DSPROpnd, DSPROpnd, |
| /* PseudoCMP_EQ_PH */ |
| DSPCC, DSPROpnd, DSPROpnd, |
| /* PseudoCMP_LE_PH */ |
| DSPCC, DSPROpnd, DSPROpnd, |
| /* PseudoCMP_LT_PH */ |
| DSPCC, DSPROpnd, DSPROpnd, |
| /* PseudoCVT_D32_W */ |
| AFGR64Opnd, GPR32Opnd, |
| /* PseudoCVT_D64_L */ |
| FGR64Opnd, GPR64Opnd, |
| /* PseudoCVT_D64_W */ |
| FGR64Opnd, GPR32Opnd, |
| /* PseudoCVT_S_L */ |
| FGR64Opnd, GPR64Opnd, |
| /* PseudoCVT_S_W */ |
| FGR32Opnd, GPR32Opnd, |
| /* PseudoDMULT */ |
| ACC128, GPR64Opnd, GPR64Opnd, |
| /* PseudoDMULTu */ |
| ACC128, GPR64Opnd, GPR64Opnd, |
| /* PseudoDSDIV */ |
| ACC128, GPR64Opnd, GPR64Opnd, |
| /* PseudoDUDIV */ |
| ACC128, GPR64Opnd, GPR64Opnd, |
| /* PseudoD_SELECT_I */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, GPR32Opnd, GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* PseudoD_SELECT_I64 */ |
| GPR64Opnd, GPR64Opnd, GPR32Opnd, GPR64Opnd, GPR64Opnd, GPR64Opnd, GPR64Opnd, |
| /* PseudoIndirectBranch */ |
| GPR32Opnd, |
| /* PseudoIndirectBranch64 */ |
| GPR64Opnd, |
| /* PseudoIndirectBranch64R6 */ |
| GPR64Opnd, |
| /* PseudoIndirectBranchR6 */ |
| GPR32Opnd, |
| /* PseudoIndirectBranch_MM */ |
| GPR32Opnd, |
| /* PseudoIndirectBranch_MMR6 */ |
| GPR32Opnd, |
| /* PseudoIndirectHazardBranch */ |
| GPR32Opnd, |
| /* PseudoIndirectHazardBranch64 */ |
| GPR64Opnd, |
| /* PseudoIndrectHazardBranch64R6 */ |
| GPR64Opnd, |
| /* PseudoIndrectHazardBranchR6 */ |
| GPR32Opnd, |
| /* PseudoMADD */ |
| ACC64, GPR32Opnd, GPR32Opnd, ACC64, |
| /* PseudoMADDU */ |
| ACC64, GPR32Opnd, GPR32Opnd, ACC64, |
| /* PseudoMADDU_MM */ |
| ACC64, GPR32Opnd, GPR32Opnd, ACC64, |
| /* PseudoMADD_MM */ |
| ACC64, GPR32Opnd, GPR32Opnd, ACC64, |
| /* PseudoMFHI */ |
| GPR32, ACC64, |
| /* PseudoMFHI64 */ |
| GPR64, ACC128, |
| /* PseudoMFHI_MM */ |
| GPR32, ACC64, |
| /* PseudoMFLO */ |
| GPR32, ACC64, |
| /* PseudoMFLO64 */ |
| GPR64, ACC128, |
| /* PseudoMFLO_MM */ |
| GPR32, ACC64, |
| /* PseudoMSUB */ |
| ACC64, GPR32Opnd, GPR32Opnd, ACC64, |
| /* PseudoMSUBU */ |
| ACC64, GPR32Opnd, GPR32Opnd, ACC64, |
| /* PseudoMSUBU_MM */ |
| ACC64, GPR32Opnd, GPR32Opnd, ACC64, |
| /* PseudoMSUB_MM */ |
| ACC64, GPR32Opnd, GPR32Opnd, ACC64, |
| /* PseudoMTLOHI */ |
| ACC64, GPR32, GPR32, |
| /* PseudoMTLOHI64 */ |
| ACC128, GPR64, GPR64, |
| /* PseudoMTLOHI_DSP */ |
| ACC64DSP, GPR32, GPR32, |
| /* PseudoMTLOHI_MM */ |
| ACC64, GPR32, GPR32, |
| /* PseudoMULT */ |
| ACC64, GPR32Opnd, GPR32Opnd, |
| /* PseudoMULT_MM */ |
| ACC64, GPR32Opnd, GPR32Opnd, |
| /* PseudoMULTu */ |
| ACC64, GPR32Opnd, GPR32Opnd, |
| /* PseudoMULTu_MM */ |
| ACC64, GPR32Opnd, GPR32Opnd, |
| /* PseudoPICK_PH */ |
| DSPROpnd, DSPCC, DSPROpnd, DSPROpnd, |
| /* PseudoPICK_QB */ |
| DSPROpnd, DSPCC, DSPROpnd, DSPROpnd, |
| /* PseudoReturn */ |
| GPR32Opnd, |
| /* PseudoReturn64 */ |
| GPR64Opnd, |
| /* PseudoSDIV */ |
| ACC64, GPR32Opnd, GPR32Opnd, |
| /* PseudoSELECTFP_F_D32 */ |
| AFGR64Opnd, FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, |
| /* PseudoSELECTFP_F_D64 */ |
| FGR64Opnd, FCCRegsOpnd, FGR64Opnd, FGR64Opnd, |
| /* PseudoSELECTFP_F_I */ |
| GPR32Opnd, FCCRegsOpnd, GPR32Opnd, GPR32Opnd, |
| /* PseudoSELECTFP_F_I64 */ |
| GPR64Opnd, FCCRegsOpnd, GPR64Opnd, GPR64Opnd, |
| /* PseudoSELECTFP_F_S */ |
| FGR32Opnd, FCCRegsOpnd, FGR32Opnd, FGR32Opnd, |
| /* PseudoSELECTFP_T_D32 */ |
| AFGR64Opnd, FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, |
| /* PseudoSELECTFP_T_D64 */ |
| FGR64Opnd, FCCRegsOpnd, FGR64Opnd, FGR64Opnd, |
| /* PseudoSELECTFP_T_I */ |
| GPR32Opnd, FCCRegsOpnd, GPR32Opnd, GPR32Opnd, |
| /* PseudoSELECTFP_T_I64 */ |
| GPR64Opnd, FCCRegsOpnd, GPR64Opnd, GPR64Opnd, |
| /* PseudoSELECTFP_T_S */ |
| FGR32Opnd, FCCRegsOpnd, FGR32Opnd, FGR32Opnd, |
| /* PseudoSELECT_D32 */ |
| AFGR64Opnd, GPR32Opnd, AFGR64Opnd, AFGR64Opnd, |
| /* PseudoSELECT_D64 */ |
| FGR64Opnd, GPR32Opnd, FGR64Opnd, FGR64Opnd, |
| /* PseudoSELECT_I */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* PseudoSELECT_I64 */ |
| GPR64Opnd, GPR32Opnd, GPR64Opnd, GPR64Opnd, |
| /* PseudoSELECT_S */ |
| FGR32Opnd, GPR32Opnd, FGR32Opnd, FGR32Opnd, |
| /* PseudoTRUNC_W_D */ |
| FGR32Opnd, FGR64Opnd, GPR32Opnd, |
| /* PseudoTRUNC_W_D32 */ |
| FGR32Opnd, AFGR64Opnd, GPR32Opnd, |
| /* PseudoTRUNC_W_S */ |
| FGR32Opnd, FGR32Opnd, GPR32Opnd, |
| /* PseudoUDIV */ |
| ACC64, GPR32Opnd, GPR32Opnd, |
| /* ROL */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* ROLImm */ |
| GPR32Opnd, GPR32Opnd, simm16, |
| /* ROR */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* RORImm */ |
| GPR32Opnd, GPR32Opnd, simm16, |
| /* RetRA */ |
| /* RetRA16 */ |
| /* SDC1_M1 */ |
| AFGR64Opnd, -1, simm16, |
| /* SDIV_MM_Pseudo */ |
| ACC64, GPR32Opnd, GPR32Opnd, |
| /* SDMacro */ |
| GPR32Opnd, -1, simm16, |
| /* SDivIMacro */ |
| GPR32Opnd, GPR32Opnd, simm32, |
| /* SDivMacro */ |
| GPR32NonZeroOpnd, GPR32Opnd, GPR32Opnd, |
| /* SEQIMacro */ |
| GPR32Opnd, GPR32Opnd, simm32_relaxed, |
| /* SEQMacro */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* SGE */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* SGEImm */ |
| GPR32Opnd, GPR32Opnd, simm32, |
| /* SGEImm64 */ |
| GPR64Opnd, GPR64Opnd, imm64, |
| /* SGEU */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* SGEUImm */ |
| GPR32Opnd, GPR32Opnd, uimm32_coerced, |
| /* SGEUImm64 */ |
| GPR64Opnd, GPR64Opnd, imm64, |
| /* SGTImm */ |
| GPR32Opnd, GPR32Opnd, simm32, |
| /* SGTImm64 */ |
| GPR64Opnd, GPR64Opnd, imm64, |
| /* SGTUImm */ |
| GPR32Opnd, GPR32Opnd, uimm32_coerced, |
| /* SGTUImm64 */ |
| GPR64Opnd, GPR64Opnd, imm64, |
| /* SLE */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* SLEImm */ |
| GPR32Opnd, GPR32Opnd, simm32, |
| /* SLEImm64 */ |
| GPR64Opnd, GPR64Opnd, imm64, |
| /* SLEU */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* SLEUImm */ |
| GPR32Opnd, GPR32Opnd, uimm32_coerced, |
| /* SLEUImm64 */ |
| GPR64Opnd, GPR64Opnd, imm64, |
| /* SLTImm64 */ |
| GPR64Opnd, GPR64Opnd, imm64, |
| /* SLTUImm64 */ |
| GPR64Opnd, GPR64Opnd, imm64, |
| /* SNEIMacro */ |
| GPR32Opnd, GPR32Opnd, simm32_relaxed, |
| /* SNEMacro */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* SNZ_B_PSEUDO */ |
| GPR32, MSA128B, |
| /* SNZ_D_PSEUDO */ |
| GPR32, MSA128D, |
| /* SNZ_H_PSEUDO */ |
| GPR32, MSA128H, |
| /* SNZ_V_PSEUDO */ |
| GPR32, MSA128B, |
| /* SNZ_W_PSEUDO */ |
| GPR32, MSA128W, |
| /* SRemIMacro */ |
| GPR32Opnd, GPR32Opnd, simm32_relaxed, |
| /* SRemMacro */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* STORE_ACC128 */ |
| ACC128, -1, simm16, |
| /* STORE_ACC64 */ |
| ACC64, -1, simm16, |
| /* STORE_ACC64DSP */ |
| ACC64DSPOpnd, -1, simm16, |
| /* STORE_CCOND_DSP */ |
| DSPCC, -1, simm16, |
| /* STR_D */ |
| MSA128DOpnd, -1, GPR32, |
| /* STR_W */ |
| MSA128WOpnd, -1, GPR32, |
| /* ST_F16 */ |
| MSA128F16, -1, simm10, |
| /* SWM_MM */ |
| reglist, -1, simm12, |
| /* SZ_B_PSEUDO */ |
| GPR32, MSA128B, |
| /* SZ_D_PSEUDO */ |
| GPR32, MSA128D, |
| /* SZ_H_PSEUDO */ |
| GPR32, MSA128H, |
| /* SZ_V_PSEUDO */ |
| GPR32, MSA128B, |
| /* SZ_W_PSEUDO */ |
| GPR32, MSA128W, |
| /* SaaAddr */ |
| GPR64Opnd, -1, simm16, |
| /* SaadAddr */ |
| GPR64Opnd, -1, simm16, |
| /* SelBeqZ */ |
| CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, |
| /* SelBneZ */ |
| CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, |
| /* SelTBteqZCmp */ |
| CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, |
| /* SelTBteqZCmpi */ |
| CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, simm16, |
| /* SelTBteqZSlt */ |
| CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, |
| /* SelTBteqZSlti */ |
| CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, simm16, |
| /* SelTBteqZSltiu */ |
| CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, simm16, |
| /* SelTBteqZSltu */ |
| CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, |
| /* SelTBtneZCmp */ |
| CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, |
| /* SelTBtneZCmpi */ |
| CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, simm16, |
| /* SelTBtneZSlt */ |
| CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, |
| /* SelTBtneZSlti */ |
| CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, simm16, |
| /* SelTBtneZSltiu */ |
| CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, simm16, |
| /* SelTBtneZSltu */ |
| CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, |
| /* SltCCRxRy16 */ |
| CPU16Regs, CPU16Regs, CPU16Regs, |
| /* SltiCCRxImmX16 */ |
| CPU16Regs, CPU16Regs, simm16, |
| /* SltiuCCRxImmX16 */ |
| CPU16Regs, CPU16Regs, simm16, |
| /* SltuCCRxRy16 */ |
| CPU16Regs, CPU16Regs, CPU16Regs, |
| /* SltuRxRyRz16 */ |
| CPU16Regs, CPU16Regs, CPU16Regs, |
| /* TAILCALL */ |
| calltarget, |
| /* TAILCALL64R6REG */ |
| GPR64Opnd, |
| /* TAILCALLHB64R6REG */ |
| GPR64Opnd, |
| /* TAILCALLHBR6REG */ |
| GPR32Opnd, |
| /* TAILCALLR6REG */ |
| GPR32Opnd, |
| /* TAILCALLREG */ |
| GPR32Opnd, |
| /* TAILCALLREG64 */ |
| GPR64Opnd, |
| /* TAILCALLREGHB */ |
| GPR32Opnd, |
| /* TAILCALLREGHB64 */ |
| GPR64Opnd, |
| /* TAILCALLREG_MM */ |
| GPR32Opnd, |
| /* TAILCALLREG_MMR6 */ |
| GPR32Opnd, |
| /* TAILCALL_MM */ |
| calltarget, |
| /* TAILCALL_MMR6 */ |
| calltarget, |
| /* TRAP */ |
| /* TRAP_MM */ |
| /* UDIV_MM_Pseudo */ |
| ACC64, GPR32Opnd, GPR32Opnd, |
| /* UDivIMacro */ |
| GPR32Opnd, GPR32Opnd, simm32, |
| /* UDivMacro */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* URemIMacro */ |
| GPR32Opnd, GPR32Opnd, simm32_relaxed, |
| /* URemMacro */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* Ulh */ |
| GPR32Opnd, -1, simm16, |
| /* Ulhu */ |
| GPR32Opnd, -1, simm16, |
| /* Ulw */ |
| GPR32Opnd, -1, simm16, |
| /* Ush */ |
| GPR32Opnd, -1, simm16, |
| /* Usw */ |
| GPR32Opnd, -1, simm16, |
| /* XOR_V_D_PSEUDO */ |
| MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
| /* XOR_V_H_PSEUDO */ |
| MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
| /* XOR_V_W_PSEUDO */ |
| MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* ABSQ_S_PH */ |
| DSPROpnd, DSPROpnd, |
| /* ABSQ_S_PH_MM */ |
| DSPROpnd, DSPROpnd, |
| /* ABSQ_S_QB */ |
| DSPROpnd, DSPROpnd, |
| /* ABSQ_S_QB_MMR2 */ |
| DSPROpnd, DSPROpnd, |
| /* ABSQ_S_W */ |
| GPR32Opnd, GPR32Opnd, |
| /* ABSQ_S_W_MM */ |
| GPR32Opnd, GPR32Opnd, |
| /* ADD */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* ADDIUPC */ |
| GPR32Opnd, simm19_lsl2, |
| /* ADDIUPC_MM */ |
| GPRMM16Opnd, simm23_lsl2, |
| /* ADDIUPC_MMR6 */ |
| GPR32Opnd, simm19_lsl2, |
| /* ADDIUR1SP_MM */ |
| GPRMM16Opnd, uimm6_lsl2, |
| /* ADDIUR2_MM */ |
| GPRMM16Opnd, GPRMM16Opnd, simm3_lsa2, |
| /* ADDIUS5_MM */ |
| GPR32Opnd, GPR32Opnd, simm4, |
| /* ADDIUSP_MM */ |
| simm9_addiusp, |
| /* ADDIU_MMR6 */ |
| GPR32Opnd, GPR32Opnd, simm16, |
| /* ADDQH_PH */ |
| DSPROpnd, DSPROpnd, DSPROpnd, |
| /* ADDQH_PH_MMR2 */ |
| DSPROpnd, DSPROpnd, DSPROpnd, |
| /* ADDQH_R_PH */ |
| DSPROpnd, DSPROpnd, DSPROpnd, |
| /* ADDQH_R_PH_MMR2 */ |
| DSPROpnd, DSPROpnd, DSPROpnd, |
| /* ADDQH_R_W */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* ADDQH_R_W_MMR2 */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* ADDQH_W */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* ADDQH_W_MMR2 */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* ADDQ_PH */ |
| DSPROpnd, DSPROpnd, DSPROpnd, |
| /* ADDQ_PH_MM */ |
| DSPROpnd, DSPROpnd, DSPROpnd, |
| /* ADDQ_S_PH */ |
| DSPROpnd, DSPROpnd, DSPROpnd, |
| /* ADDQ_S_PH_MM */ |
| DSPROpnd, DSPROpnd, DSPROpnd, |
| /* ADDQ_S_W */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* ADDQ_S_W_MM */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* ADDR_PS64 */ |
| FGR64Opnd, FGR64Opnd, FGR64Opnd, |
| /* ADDSC */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* ADDSC_MM */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* ADDS_A_B */ |
| MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
| /* ADDS_A_D */ |
| MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
| /* ADDS_A_H */ |
| MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
| /* ADDS_A_W */ |
| MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* ADDS_S_B */ |
| MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
| /* ADDS_S_D */ |
| MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
| /* ADDS_S_H */ |
| MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
| /* ADDS_S_W */ |
| MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* ADDS_U_B */ |
| MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
| /* ADDS_U_D */ |
| MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
| /* ADDS_U_H */ |
| MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
| /* ADDS_U_W */ |
| MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* ADDU16_MM */ |
| GPRMM16Opnd, GPRMM16Opnd, GPRMM16Opnd, |
| /* ADDU16_MMR6 */ |
| GPRMM16Opnd, GPRMM16Opnd, GPRMM16Opnd, |
| /* ADDUH_QB */ |
| DSPROpnd, DSPROpnd, DSPROpnd, |
| /* ADDUH_QB_MMR2 */ |
| DSPROpnd, DSPROpnd, DSPROpnd, |
| /* ADDUH_R_QB */ |
| DSPROpnd, DSPROpnd, DSPROpnd, |
| /* ADDUH_R_QB_MMR2 */ |
| DSPROpnd, DSPROpnd, DSPROpnd, |
| /* ADDU_MMR6 */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* ADDU_PH */ |
| DSPROpnd, DSPROpnd, DSPROpnd, |
| /* ADDU_PH_MMR2 */ |
| DSPROpnd, DSPROpnd, DSPROpnd, |
| /* ADDU_QB */ |
| DSPROpnd, DSPROpnd, DSPROpnd, |
| /* ADDU_QB_MM */ |
| DSPROpnd, DSPROpnd, DSPROpnd, |
| /* ADDU_S_PH */ |
| DSPROpnd, DSPROpnd, DSPROpnd, |
| /* ADDU_S_PH_MMR2 */ |
| DSPROpnd, DSPROpnd, DSPROpnd, |
| /* ADDU_S_QB */ |
| DSPROpnd, DSPROpnd, DSPROpnd, |
| /* ADDU_S_QB_MM */ |
| DSPROpnd, DSPROpnd, DSPROpnd, |
| /* ADDVI_B */ |
| MSA128BOpnd, MSA128BOpnd, vsplat_uimm5, |
| /* ADDVI_D */ |
| MSA128DOpnd, MSA128DOpnd, vsplat_uimm5, |
| /* ADDVI_H */ |
| MSA128HOpnd, MSA128HOpnd, vsplat_uimm5, |
| /* ADDVI_W */ |
| MSA128WOpnd, MSA128WOpnd, vsplat_uimm5, |
| /* ADDV_B */ |
| MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
| /* ADDV_D */ |
| MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
| /* ADDV_H */ |
| MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
| /* ADDV_W */ |
| MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* ADDWC */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* ADDWC_MM */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* ADD_A_B */ |
| MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
| /* ADD_A_D */ |
| MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
| /* ADD_A_H */ |
| MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
| /* ADD_A_W */ |
| MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* ADD_MM */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* ADD_MMR6 */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* ADDi */ |
| GPR32Opnd, GPR32Opnd, simm16_relaxed, |
| /* ADDi_MM */ |
| GPR32Opnd, GPR32Opnd, simm16, |
| /* ADDiu */ |
| GPR32Opnd, GPR32Opnd, simm16_relaxed, |
| /* ADDiu_MM */ |
| GPR32Opnd, GPR32Opnd, simm16, |
| /* ADDu */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* ADDu_MM */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* ALIGN */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, uimm2, |
| /* ALIGN_MMR6 */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, uimm2, |
| /* ALUIPC */ |
| GPR32Opnd, simm16, |
| /* ALUIPC_MMR6 */ |
| GPR32Opnd, simm16, |
| /* AND */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* AND16_MM */ |
| GPRMM16Opnd, GPRMM16Opnd, GPRMM16Opnd, |
| /* AND16_MMR6 */ |
| GPRMM16Opnd, GPRMM16Opnd, GPRMM16Opnd, |
| /* AND64 */ |
| GPR64Opnd, GPR64Opnd, GPR64Opnd, |
| /* ANDI16_MM */ |
| GPRMM16Opnd, GPRMM16Opnd, uimm4_andi, |
| /* ANDI16_MMR6 */ |
| GPRMM16Opnd, GPRMM16Opnd, uimm4_andi, |
| /* ANDI_B */ |
| MSA128BOpnd, MSA128BOpnd, vsplat_uimm8, |
| /* ANDI_MMR6 */ |
| GPR32Opnd, GPR32Opnd, uimm16, |
| /* AND_MM */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* AND_MMR6 */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* AND_V */ |
| MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
| /* ANDi */ |
| GPR32Opnd, GPR32Opnd, uimm16, |
| /* ANDi64 */ |
| GPR64Opnd, GPR64Opnd, uimm16_64, |
| /* ANDi_MM */ |
| GPR32Opnd, GPR32Opnd, uimm16, |
| /* APPEND */ |
| GPR32Opnd, GPR32Opnd, uimm5, GPR32Opnd, |
| /* APPEND_MMR2 */ |
| GPR32Opnd, GPR32Opnd, uimm5, GPR32Opnd, |
| /* ASUB_S_B */ |
| MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
| /* ASUB_S_D */ |
| MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
| /* ASUB_S_H */ |
| MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
| /* ASUB_S_W */ |
| MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* ASUB_U_B */ |
| MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
| /* ASUB_U_D */ |
| MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
| /* ASUB_U_H */ |
| MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
| /* ASUB_U_W */ |
| MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* AUI */ |
| GPR32Opnd, GPR32Opnd, uimm16, |
| /* AUIPC */ |
| GPR32Opnd, simm16, |
| /* AUIPC_MMR6 */ |
| GPR32Opnd, simm16, |
| /* AUI_MMR6 */ |
| GPR32Opnd, GPR32Opnd, uimm16, |
| /* AVER_S_B */ |
| MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
| /* AVER_S_D */ |
| MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
| /* AVER_S_H */ |
| MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
| /* AVER_S_W */ |
| MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* AVER_U_B */ |
| MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
| /* AVER_U_D */ |
| MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
| /* AVER_U_H */ |
| MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
| /* AVER_U_W */ |
| MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* AVE_S_B */ |
| MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
| /* AVE_S_D */ |
| MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
| /* AVE_S_H */ |
| MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
| /* AVE_S_W */ |
| MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* AVE_U_B */ |
| MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
| /* AVE_U_D */ |
| MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
| /* AVE_U_H */ |
| MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
| /* AVE_U_W */ |
| MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* AddiuRxImmX16 */ |
| CPU16Regs, simm16, |
| /* AddiuRxPcImmX16 */ |
| CPU16Regs, simm16, |
| /* AddiuRxRxImm16 */ |
| CPU16Regs, CPU16Regs, simm16, |
| /* AddiuRxRxImmX16 */ |
| CPU16Regs, CPU16Regs, simm16, |
| /* AddiuRxRyOffMemX16 */ |
| CPU16Regs, CPU16RegsPlusSP, simm16, |
| /* AddiuSpImm16 */ |
| simm16, |
| /* AddiuSpImmX16 */ |
| simm16, |
| /* AdduRxRyRz16 */ |
| CPU16Regs, CPU16Regs, CPU16Regs, |
| /* AndRxRxRy16 */ |
| CPU16Regs, CPU16Regs, CPU16Regs, |
| /* B16_MM */ |
| brtarget10_mm, |
| /* BADDu */ |
| GPR64Opnd, GPR64Opnd, GPR64Opnd, |
| /* BAL */ |
| brtarget, |
| /* BALC */ |
| brtarget26, |
| /* BALC_MMR6 */ |
| brtarget26_mm, |
| /* BALIGN */ |
| GPR32Opnd, GPR32Opnd, uimm2, GPR32Opnd, |
| /* BALIGN_MMR2 */ |
| GPR32Opnd, GPR32Opnd, uimm2, GPR32Opnd, |
| /* BBIT0 */ |
| GPR64Opnd, uimm5_64_report_uimm6, brtarget, |
| /* BBIT032 */ |
| GPR64Opnd, uimm5_64, brtarget, |
| /* BBIT1 */ |
| GPR64Opnd, uimm5_64_report_uimm6, brtarget, |
| /* BBIT132 */ |
| GPR64Opnd, uimm5_64, brtarget, |
| /* BC */ |
| brtarget26, |
| /* BC16_MMR6 */ |
| brtarget10_mm, |
| /* BC1EQZ */ |
| FGR64Opnd, brtarget, |
| /* BC1EQZC_MMR6 */ |
| FGR64Opnd, brtarget_mm, |
| /* BC1F */ |
| FCCRegsOpnd, brtarget, |
| /* BC1FL */ |
| FCCRegsOpnd, brtarget, |
| /* BC1F_MM */ |
| FCCRegsOpnd, brtarget_mm, |
| /* BC1NEZ */ |
| FGR64Opnd, brtarget, |
| /* BC1NEZC_MMR6 */ |
| FGR64Opnd, brtarget_mm, |
| /* BC1T */ |
| FCCRegsOpnd, brtarget, |
| /* BC1TL */ |
| FCCRegsOpnd, brtarget, |
| /* BC1T_MM */ |
| FCCRegsOpnd, brtarget_mm, |
| /* BC2EQZ */ |
| COP2Opnd, brtarget, |
| /* BC2EQZC_MMR6 */ |
| COP2Opnd, brtarget_mm, |
| /* BC2NEZ */ |
| COP2Opnd, brtarget, |
| /* BC2NEZC_MMR6 */ |
| COP2Opnd, brtarget_mm, |
| /* BCLRI_B */ |
| MSA128BOpnd, MSA128BOpnd, vsplat_uimm3, |
| /* BCLRI_D */ |
| MSA128DOpnd, MSA128DOpnd, vsplat_uimm6, |
| /* BCLRI_H */ |
| MSA128HOpnd, MSA128HOpnd, vsplat_uimm4, |
| /* BCLRI_W */ |
| MSA128WOpnd, MSA128WOpnd, vsplat_uimm5, |
| /* BCLR_B */ |
| MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
| /* BCLR_D */ |
| MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
| /* BCLR_H */ |
| MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
| /* BCLR_W */ |
| MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* BC_MMR6 */ |
| brtarget26_mm, |
| /* BEQ */ |
| GPR32Opnd, GPR32Opnd, brtarget, |
| /* BEQ64 */ |
| GPR64Opnd, GPR64Opnd, brtarget, |
| /* BEQC */ |
| GPR32Opnd, GPR32Opnd, brtarget, |
| /* BEQC64 */ |
| GPR64Opnd, GPR64Opnd, brtarget, |
| /* BEQC_MMR6 */ |
| GPR32Opnd, GPR32Opnd, brtarget_lsl2_mm, |
| /* BEQL */ |
| GPR32Opnd, GPR32Opnd, brtarget, |
| /* BEQZ16_MM */ |
| GPRMM16Opnd, brtarget7_mm, |
| /* BEQZALC */ |
| GPR32Opnd, brtarget, |
| /* BEQZALC_MMR6 */ |
| GPR32Opnd, brtarget_mm, |
| /* BEQZC */ |
| GPR32Opnd, brtarget21, |
| /* BEQZC16_MMR6 */ |
| GPRMM16Opnd, brtarget7_mm, |
| /* BEQZC64 */ |
| GPR64Opnd, brtarget21, |
| /* BEQZC_MM */ |
| GPR32Opnd, brtarget_mm, |
| /* BEQZC_MMR6 */ |
| GPR32Opnd, brtarget21_mm, |
| /* BEQ_MM */ |
| GPR32Opnd, GPR32Opnd, brtarget_mm, |
| /* BGEC */ |
| GPR32Opnd, GPR32Opnd, brtarget, |
| /* BGEC64 */ |
| GPR64Opnd, GPR64Opnd, brtarget, |
| /* BGEC_MMR6 */ |
| GPR32Opnd, GPR32Opnd, brtarget_lsl2_mm, |
| /* BGEUC */ |
| GPR32Opnd, GPR32Opnd, brtarget, |
| /* BGEUC64 */ |
| GPR64Opnd, GPR64Opnd, brtarget, |
| /* BGEUC_MMR6 */ |
| GPR32Opnd, GPR32Opnd, brtarget_lsl2_mm, |
| /* BGEZ */ |
| GPR32Opnd, brtarget, |
| /* BGEZ64 */ |
| GPR64Opnd, brtarget, |
| /* BGEZAL */ |
| GPR32Opnd, brtarget, |
| /* BGEZALC */ |
| GPR32Opnd, brtarget, |
| /* BGEZALC_MMR6 */ |
| GPR32Opnd, brtarget_mm, |
| /* BGEZALL */ |
| GPR32Opnd, brtarget, |
| /* BGEZALS_MM */ |
| GPR32Opnd, brtarget_mm, |
| /* BGEZAL_MM */ |
| GPR32Opnd, brtarget_mm, |
| /* BGEZC */ |
| GPR32Opnd, brtarget, |
| /* BGEZC64 */ |
| GPR64Opnd, brtarget, |
| /* BGEZC_MMR6 */ |
| GPR32Opnd, brtarget_lsl2_mm, |
| /* BGEZL */ |
| GPR32Opnd, brtarget, |
| /* BGEZ_MM */ |
| GPR32Opnd, brtarget_mm, |
| /* BGTZ */ |
| GPR32Opnd, brtarget, |
| /* BGTZ64 */ |
| GPR64Opnd, brtarget, |
| /* BGTZALC */ |
| GPR32Opnd, brtarget, |
| /* BGTZALC_MMR6 */ |
| GPR32Opnd, brtarget_mm, |
| /* BGTZC */ |
| GPR32Opnd, brtarget, |
| /* BGTZC64 */ |
| GPR64Opnd, brtarget, |
| /* BGTZC_MMR6 */ |
| GPR32Opnd, brtarget_lsl2_mm, |
| /* BGTZL */ |
| GPR32Opnd, brtarget, |
| /* BGTZ_MM */ |
| GPR32Opnd, brtarget_mm, |
| /* BINSLI_B */ |
| MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, vsplat_uimm3, |
| /* BINSLI_D */ |
| MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, vsplat_uimm6, |
| /* BINSLI_H */ |
| MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, vsplat_uimm4, |
| /* BINSLI_W */ |
| MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, vsplat_uimm5, |
| /* BINSL_B */ |
| MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
| /* BINSL_D */ |
| MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
| /* BINSL_H */ |
| MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
| /* BINSL_W */ |
| MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* BINSRI_B */ |
| MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, vsplat_uimm3, |
| /* BINSRI_D */ |
| MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, vsplat_uimm6, |
| /* BINSRI_H */ |
| MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, vsplat_uimm4, |
| /* BINSRI_W */ |
| MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, vsplat_uimm5, |
| /* BINSR_B */ |
| MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
| /* BINSR_D */ |
| MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
| /* BINSR_H */ |
| MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
| /* BINSR_W */ |
| MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* BITREV */ |
| GPR32Opnd, GPR32Opnd, |
| /* BITREV_MM */ |
| GPR32Opnd, GPR32Opnd, |
| /* BITSWAP */ |
| GPR32Opnd, GPR32Opnd, |
| /* BITSWAP_MMR6 */ |
| GPR32Opnd, GPR32Opnd, |
| /* BLEZ */ |
| GPR32Opnd, brtarget, |
| /* BLEZ64 */ |
| GPR64Opnd, brtarget, |
| /* BLEZALC */ |
| GPR32Opnd, brtarget, |
| /* BLEZALC_MMR6 */ |
| GPR32Opnd, brtarget_mm, |
| /* BLEZC */ |
| GPR32Opnd, brtarget, |
| /* BLEZC64 */ |
| GPR64Opnd, brtarget, |
| /* BLEZC_MMR6 */ |
| GPR32Opnd, brtarget_lsl2_mm, |
| /* BLEZL */ |
| GPR32Opnd, brtarget, |
| /* BLEZ_MM */ |
| GPR32Opnd, brtarget_mm, |
| /* BLTC */ |
| GPR32Opnd, GPR32Opnd, brtarget, |
| /* BLTC64 */ |
| GPR64Opnd, GPR64Opnd, brtarget, |
| /* BLTC_MMR6 */ |
| GPR32Opnd, GPR32Opnd, brtarget_lsl2_mm, |
| /* BLTUC */ |
| GPR32Opnd, GPR32Opnd, brtarget, |
| /* BLTUC64 */ |
| GPR64Opnd, GPR64Opnd, brtarget, |
| /* BLTUC_MMR6 */ |
| GPR32Opnd, GPR32Opnd, brtarget_lsl2_mm, |
| /* BLTZ */ |
| GPR32Opnd, brtarget, |
| /* BLTZ64 */ |
| GPR64Opnd, brtarget, |
| /* BLTZAL */ |
| GPR32Opnd, brtarget, |
| /* BLTZALC */ |
| GPR32Opnd, brtarget, |
| /* BLTZALC_MMR6 */ |
| GPR32Opnd, brtarget_mm, |
| /* BLTZALL */ |
| GPR32Opnd, brtarget, |
| /* BLTZALS_MM */ |
| GPR32Opnd, brtarget_mm, |
| /* BLTZAL_MM */ |
| GPR32Opnd, brtarget_mm, |
| /* BLTZC */ |
| GPR32Opnd, brtarget, |
| /* BLTZC64 */ |
| GPR64Opnd, brtarget, |
| /* BLTZC_MMR6 */ |
| GPR32Opnd, brtarget_lsl2_mm, |
| /* BLTZL */ |
| GPR32Opnd, brtarget, |
| /* BLTZ_MM */ |
| GPR32Opnd, brtarget_mm, |
| /* BMNZI_B */ |
| MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, vsplat_uimm8, |
| /* BMNZ_V */ |
| MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
| /* BMZI_B */ |
| MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, vsplat_uimm8, |
| /* BMZ_V */ |
| MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
| /* BNE */ |
| GPR32Opnd, GPR32Opnd, brtarget, |
| /* BNE64 */ |
| GPR64Opnd, GPR64Opnd, brtarget, |
| /* BNEC */ |
| GPR32Opnd, GPR32Opnd, brtarget, |
| /* BNEC64 */ |
| GPR64Opnd, GPR64Opnd, brtarget, |
| /* BNEC_MMR6 */ |
| GPR32Opnd, GPR32Opnd, brtarget_lsl2_mm, |
| /* BNEGI_B */ |
| MSA128BOpnd, MSA128BOpnd, vsplat_uimm3, |
| /* BNEGI_D */ |
| MSA128DOpnd, MSA128DOpnd, vsplat_uimm6, |
| /* BNEGI_H */ |
| MSA128HOpnd, MSA128HOpnd, vsplat_uimm4, |
| /* BNEGI_W */ |
| MSA128WOpnd, MSA128WOpnd, vsplat_uimm5, |
| /* BNEG_B */ |
| MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
| /* BNEG_D */ |
| MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
| /* BNEG_H */ |
| MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
| /* BNEG_W */ |
| MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* BNEL */ |
| GPR32Opnd, GPR32Opnd, brtarget, |
| /* BNEZ16_MM */ |
| GPRMM16Opnd, brtarget7_mm, |
| /* BNEZALC */ |
| GPR32Opnd, brtarget, |
| /* BNEZALC_MMR6 */ |
| GPR32Opnd, brtarget_mm, |
| /* BNEZC */ |
| GPR32Opnd, brtarget21, |
| /* BNEZC16_MMR6 */ |
| GPRMM16Opnd, brtarget7_mm, |
| /* BNEZC64 */ |
| GPR64Opnd, brtarget21, |
| /* BNEZC_MM */ |
| GPR32Opnd, brtarget_mm, |
| /* BNEZC_MMR6 */ |
| GPR32Opnd, brtarget21_mm, |
| /* BNE_MM */ |
| GPR32Opnd, GPR32Opnd, brtarget_mm, |
| /* BNVC */ |
| GPR32Opnd, GPR32Opnd, brtarget, |
| /* BNVC_MMR6 */ |
| GPR32Opnd, GPR32Opnd, brtargetr6, |
| /* BNZ_B */ |
| MSA128BOpnd, brtarget, |
| /* BNZ_D */ |
| MSA128DOpnd, brtarget, |
| /* BNZ_H */ |
| MSA128HOpnd, brtarget, |
| /* BNZ_V */ |
| MSA128BOpnd, brtarget, |
| /* BNZ_W */ |
| MSA128WOpnd, brtarget, |
| /* BOVC */ |
| GPR32Opnd, GPR32Opnd, brtarget, |
| /* BOVC_MMR6 */ |
| GPR32Opnd, GPR32Opnd, brtargetr6, |
| /* BPOSGE32 */ |
| brtarget, |
| /* BPOSGE32C_MMR3 */ |
| brtarget1SImm16, |
| /* BPOSGE32_MM */ |
| brtarget_mm, |
| /* BREAK */ |
| uimm10, uimm10, |
| /* BREAK16_MM */ |
| uimm4, |
| /* BREAK16_MMR6 */ |
| uimm4, |
| /* BREAK_MM */ |
| uimm10, uimm10, |
| /* BREAK_MMR6 */ |
| uimm10, uimm10, |
| /* BSELI_B */ |
| MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, vsplat_uimm8, |
| /* BSEL_V */ |
| MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
| /* BSETI_B */ |
| MSA128BOpnd, MSA128BOpnd, vsplat_uimm3, |
| /* BSETI_D */ |
| MSA128DOpnd, MSA128DOpnd, vsplat_uimm6, |
| /* BSETI_H */ |
| MSA128HOpnd, MSA128HOpnd, vsplat_uimm4, |
| /* BSETI_W */ |
| MSA128WOpnd, MSA128WOpnd, vsplat_uimm5, |
| /* BSET_B */ |
| MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
| /* BSET_D */ |
| MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
| /* BSET_H */ |
| MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
| /* BSET_W */ |
| MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* BZ_B */ |
| MSA128BOpnd, brtarget, |
| /* BZ_D */ |
| MSA128DOpnd, brtarget, |
| /* BZ_H */ |
| MSA128HOpnd, brtarget, |
| /* BZ_V */ |
| MSA128BOpnd, brtarget, |
| /* BZ_W */ |
| MSA128WOpnd, brtarget, |
| /* BeqzRxImm16 */ |
| CPU16Regs, brtarget, |
| /* BeqzRxImmX16 */ |
| CPU16Regs, brtarget, |
| /* Bimm16 */ |
| brtarget, |
| /* BimmX16 */ |
| brtarget, |
| /* BnezRxImm16 */ |
| CPU16Regs, brtarget, |
| /* BnezRxImmX16 */ |
| CPU16Regs, brtarget, |
| /* Break16 */ |
| /* Bteqz16 */ |
| simm16, |
| /* BteqzX16 */ |
| simm16, |
| /* Btnez16 */ |
| simm16, |
| /* BtnezX16 */ |
| simm16, |
| /* CACHE */ |
| -1, simm16, uimm5, |
| /* CACHEE */ |
| -1, simm9, uimm5, |
| /* CACHEE_MM */ |
| -1, simm9, uimm5, |
| /* CACHE_MM */ |
| -1, simm12, uimm5, |
| /* CACHE_MMR6 */ |
| -1, simm12, uimm5, |
| /* CACHE_R6 */ |
| -1, simm9, uimm5, |
| /* CEIL_L_D64 */ |
| FGR64Opnd, FGR64Opnd, |
| /* CEIL_L_D_MMR6 */ |
| FGR64Opnd, FGR64Opnd, |
| /* CEIL_L_S */ |
| FGR64Opnd, FGR32Opnd, |
| /* CEIL_L_S_MMR6 */ |
| FGR64Opnd, FGR32Opnd, |
| /* CEIL_W_D32 */ |
| FGR32Opnd, AFGR64Opnd, |
| /* CEIL_W_D64 */ |
| FGR32Opnd, FGR64Opnd, |
| /* CEIL_W_D_MMR6 */ |
| FGR32Opnd, AFGR64Opnd, |
| /* CEIL_W_MM */ |
| FGR32Opnd, AFGR64Opnd, |
| /* CEIL_W_S */ |
| FGR32Opnd, FGR32Opnd, |
| /* CEIL_W_S_MM */ |
| FGR32Opnd, FGR32Opnd, |
| /* CEIL_W_S_MMR6 */ |
| FGR32Opnd, FGR32Opnd, |
| /* CEQI_B */ |
| MSA128BOpnd, MSA128BOpnd, vsplat_simm5, |
| /* CEQI_D */ |
| MSA128DOpnd, MSA128DOpnd, vsplat_simm5, |
| /* CEQI_H */ |
| MSA128HOpnd, MSA128HOpnd, vsplat_simm5, |
| /* CEQI_W */ |
| MSA128WOpnd, MSA128WOpnd, vsplat_simm5, |
| /* CEQ_B */ |
| MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
| /* CEQ_D */ |
| MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
| /* CEQ_H */ |
| MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
| /* CEQ_W */ |
| MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* CFC1 */ |
| GPR32Opnd, CCROpnd, |
| /* CFC1_MM */ |
| GPR32Opnd, CCROpnd, |
| /* CFC2_MM */ |
| GPR32Opnd, COP2Opnd, |
| /* CFCMSA */ |
| GPR32Opnd, MSA128CROpnd, |
| /* CINS */ |
| GPR64Opnd, GPR64Opnd, uimm5, uimm5, |
| /* CINS32 */ |
| GPR64Opnd, GPR64Opnd, uimm5, uimm5, |
| /* CINS64_32 */ |
| GPR64Opnd, GPR32Opnd, uimm5, uimm5, |
| /* CINS_i32 */ |
| GPR32Opnd, GPR32Opnd, uimm5, uimm5, |
| /* CLASS_D */ |
| FGR64Opnd, FGR64Opnd, |
| /* CLASS_D_MMR6 */ |
| FGR64Opnd, FGR64Opnd, |
| /* CLASS_S */ |
| FGR32Opnd, FGR32Opnd, |
| /* CLASS_S_MMR6 */ |
| FGR32Opnd, FGR32Opnd, |
| /* CLEI_S_B */ |
| MSA128BOpnd, MSA128BOpnd, vsplat_simm5, |
| /* CLEI_S_D */ |
| MSA128DOpnd, MSA128DOpnd, vsplat_simm5, |
| /* CLEI_S_H */ |
| MSA128HOpnd, MSA128HOpnd, vsplat_simm5, |
| /* CLEI_S_W */ |
| MSA128WOpnd, MSA128WOpnd, vsplat_simm5, |
| /* CLEI_U_B */ |
| MSA128BOpnd, MSA128BOpnd, vsplat_uimm5, |
| /* CLEI_U_D */ |
| MSA128DOpnd, MSA128DOpnd, vsplat_uimm5, |
| /* CLEI_U_H */ |
| MSA128HOpnd, MSA128HOpnd, vsplat_uimm5, |
| /* CLEI_U_W */ |
| MSA128WOpnd, MSA128WOpnd, vsplat_uimm5, |
| /* CLE_S_B */ |
| MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
| /* CLE_S_D */ |
| MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
| /* CLE_S_H */ |
| MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
| /* CLE_S_W */ |
| MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* CLE_U_B */ |
| MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
| /* CLE_U_D */ |
| MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
| /* CLE_U_H */ |
| MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
| /* CLE_U_W */ |
| MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* CLO */ |
| GPR32Opnd, GPR32Opnd, |
| /* CLO_MM */ |
| GPR32Opnd, GPR32Opnd, |
| /* CLO_MMR6 */ |
| GPR32Opnd, GPR32Opnd, |
| /* CLO_R6 */ |
| GPR32Opnd, GPR32Opnd, |
| /* CLTI_S_B */ |
| MSA128BOpnd, MSA128BOpnd, vsplat_simm5, |
| /* CLTI_S_D */ |
| MSA128DOpnd, MSA128DOpnd, vsplat_simm5, |
| /* CLTI_S_H */ |
| MSA128HOpnd, MSA128HOpnd, vsplat_simm5, |
| /* CLTI_S_W */ |
| MSA128WOpnd, MSA128WOpnd, vsplat_simm5, |
| /* CLTI_U_B */ |
| MSA128BOpnd, MSA128BOpnd, vsplat_uimm5, |
| /* CLTI_U_D */ |
| MSA128DOpnd, MSA128DOpnd, vsplat_uimm5, |
| /* CLTI_U_H */ |
| MSA128HOpnd, MSA128HOpnd, vsplat_uimm5, |
| /* CLTI_U_W */ |
| MSA128WOpnd, MSA128WOpnd, vsplat_uimm5, |
| /* CLT_S_B */ |
| MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
| /* CLT_S_D */ |
| MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
| /* CLT_S_H */ |
| MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
| /* CLT_S_W */ |
| MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* CLT_U_B */ |
| MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
| /* CLT_U_D */ |
| MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
| /* CLT_U_H */ |
| MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
| /* CLT_U_W */ |
| MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* CLZ */ |
| GPR32Opnd, GPR32Opnd, |
| /* CLZ_MM */ |
| GPR32Opnd, GPR32Opnd, |
| /* CLZ_MMR6 */ |
| GPR32Opnd, GPR32Opnd, |
| /* CLZ_R6 */ |
| GPR32Opnd, GPR32Opnd, |
| /* CMPGDU_EQ_QB */ |
| GPR32Opnd, DSPROpnd, DSPROpnd, |
| /* CMPGDU_EQ_QB_MMR2 */ |
| GPR32Opnd, DSPROpnd, DSPROpnd, |
| /* CMPGDU_LE_QB */ |
| GPR32Opnd, DSPROpnd, DSPROpnd, |
| /* CMPGDU_LE_QB_MMR2 */ |
| GPR32Opnd, DSPROpnd, DSPROpnd, |
| /* CMPGDU_LT_QB */ |
| GPR32Opnd, DSPROpnd, DSPROpnd, |
| /* CMPGDU_LT_QB_MMR2 */ |
| GPR32Opnd, DSPROpnd, DSPROpnd, |
| /* CMPGU_EQ_QB */ |
| GPR32Opnd, DSPROpnd, DSPROpnd, |
| /* CMPGU_EQ_QB_MM */ |
| GPR32Opnd, DSPROpnd, DSPROpnd, |
| /* CMPGU_LE_QB */ |
| GPR32Opnd, DSPROpnd, DSPROpnd, |
| /* CMPGU_LE_QB_MM */ |
| GPR32Opnd, DSPROpnd, DSPROpnd, |
| /* CMPGU_LT_QB */ |
| GPR32Opnd, DSPROpnd, DSPROpnd, |
| /* CMPGU_LT_QB_MM */ |
| GPR32Opnd, DSPROpnd, DSPROpnd, |
| /* CMPU_EQ_QB */ |
| DSPROpnd, DSPROpnd, |
| /* CMPU_EQ_QB_MM */ |
| DSPROpnd, DSPROpnd, |
| /* CMPU_LE_QB */ |
| DSPROpnd, DSPROpnd, |
| /* CMPU_LE_QB_MM */ |
| DSPROpnd, DSPROpnd, |
| /* CMPU_LT_QB */ |
| DSPROpnd, DSPROpnd, |
| /* CMPU_LT_QB_MM */ |
| DSPROpnd, DSPROpnd, |
| /* CMP_AF_D_MMR6 */ |
| FGRCCOpnd, FGR64Opnd, FGR64Opnd, |
| /* CMP_AF_S_MMR6 */ |
| FGRCCOpnd, FGR32Opnd, FGR32Opnd, |
| /* CMP_EQ_D */ |
| FGRCCOpnd, FGR64Opnd, FGR64Opnd, |
| /* CMP_EQ_D_MMR6 */ |
| FGRCCOpnd, FGR64Opnd, FGR64Opnd, |
| /* CMP_EQ_PH */ |
| DSPROpnd, DSPROpnd, |
| /* CMP_EQ_PH_MM */ |
| DSPROpnd, DSPROpnd, |
| /* CMP_EQ_S */ |
| FGRCCOpnd, FGR32Opnd, FGR32Opnd, |
| /* CMP_EQ_S_MMR6 */ |
| FGRCCOpnd, FGR32Opnd, FGR32Opnd, |
| /* CMP_F_D */ |
| FGRCCOpnd, FGR64Opnd, FGR64Opnd, |
| /* CMP_F_S */ |
| FGRCCOpnd, FGR32Opnd, FGR32Opnd, |
| /* CMP_LE_D */ |
| FGRCCOpnd, FGR64Opnd, FGR64Opnd, |
| /* CMP_LE_D_MMR6 */ |
| FGRCCOpnd, FGR64Opnd, FGR64Opnd, |
| /* CMP_LE_PH */ |
| DSPROpnd, DSPROpnd, |
| /* CMP_LE_PH_MM */ |
| DSPROpnd, DSPROpnd, |
| /* CMP_LE_S */ |
| FGRCCOpnd, FGR32Opnd, FGR32Opnd, |
| /* CMP_LE_S_MMR6 */ |
| FGRCCOpnd, FGR32Opnd, FGR32Opnd, |
| /* CMP_LT_D */ |
| FGRCCOpnd, FGR64Opnd, FGR64Opnd, |
| /* CMP_LT_D_MMR6 */ |
| FGRCCOpnd, FGR64Opnd, FGR64Opnd, |
| /* CMP_LT_PH */ |
| DSPROpnd, DSPROpnd, |
| /* CMP_LT_PH_MM */ |
| DSPROpnd, DSPROpnd, |
| /* CMP_LT_S */ |
| FGRCCOpnd, FGR32Opnd, FGR32Opnd, |
| /* CMP_LT_S_MMR6 */ |
| FGRCCOpnd, FGR32Opnd, FGR32Opnd, |
| /* CMP_SAF_D */ |
| FGRCCOpnd, FGR64Opnd, FGR64Opnd, |
| /* CMP_SAF_D_MMR6 */ |
| FGRCCOpnd, FGR64Opnd, FGR64Opnd, |
| /* CMP_SAF_S */ |
| FGRCCOpnd, FGR32Opnd, FGR32Opnd, |
| /* CMP_SAF_S_MMR6 */ |
| FGRCCOpnd, FGR32Opnd, FGR32Opnd, |
| /* CMP_SEQ_D */ |
| FGRCCOpnd, FGR64Opnd, FGR64Opnd, |
| /* CMP_SEQ_D_MMR6 */ |
| FGRCCOpnd, FGR64Opnd, FGR64Opnd, |
| /* CMP_SEQ_S */ |
| FGRCCOpnd, FGR32Opnd, FGR32Opnd, |
| /* CMP_SEQ_S_MMR6 */ |
| FGRCCOpnd, FGR32Opnd, FGR32Opnd, |
| /* CMP_SLE_D */ |
| FGRCCOpnd, FGR64Opnd, FGR64Opnd, |
| /* CMP_SLE_D_MMR6 */ |
| FGRCCOpnd, FGR64Opnd, FGR64Opnd, |
| /* CMP_SLE_S */ |
| FGRCCOpnd, FGR32Opnd, FGR32Opnd, |
| /* CMP_SLE_S_MMR6 */ |
| FGRCCOpnd, FGR32Opnd, FGR32Opnd, |
| /* CMP_SLT_D */ |
| FGRCCOpnd, FGR64Opnd, FGR64Opnd, |
| /* CMP_SLT_D_MMR6 */ |
| FGRCCOpnd, FGR64Opnd, FGR64Opnd, |
| /* CMP_SLT_S */ |
| FGRCCOpnd, FGR32Opnd, FGR32Opnd, |
| /* CMP_SLT_S_MMR6 */ |
| FGRCCOpnd, FGR32Opnd, FGR32Opnd, |
| /* CMP_SUEQ_D */ |
| FGRCCOpnd, FGR64Opnd, FGR64Opnd, |
| /* CMP_SUEQ_D_MMR6 */ |
| FGRCCOpnd, FGR64Opnd, FGR64Opnd, |
| /* CMP_SUEQ_S */ |
| FGRCCOpnd, FGR32Opnd, FGR32Opnd, |
| /* CMP_SUEQ_S_MMR6 */ |
| FGRCCOpnd, FGR32Opnd, FGR32Opnd, |
| /* CMP_SULE_D */ |
| FGRCCOpnd, FGR64Opnd, FGR64Opnd, |
| /* CMP_SULE_D_MMR6 */ |
| FGRCCOpnd, FGR64Opnd, FGR64Opnd, |
| /* CMP_SULE_S */ |
| FGRCCOpnd, FGR32Opnd, FGR32Opnd, |
| /* CMP_SULE_S_MMR6 */ |
| FGRCCOpnd, FGR32Opnd, FGR32Opnd, |
| /* CMP_SULT_D */ |
| FGRCCOpnd, FGR64Opnd, FGR64Opnd, |
| /* CMP_SULT_D_MMR6 */ |
| FGRCCOpnd, FGR64Opnd, FGR64Opnd, |
| /* CMP_SULT_S */ |
| FGRCCOpnd, FGR32Opnd, FGR32Opnd, |
| /* CMP_SULT_S_MMR6 */ |
| FGRCCOpnd, FGR32Opnd, FGR32Opnd, |
| /* CMP_SUN_D */ |
| FGRCCOpnd, FGR64Opnd, FGR64Opnd, |
| /* CMP_SUN_D_MMR6 */ |
| FGRCCOpnd, FGR64Opnd, FGR64Opnd, |
| /* CMP_SUN_S */ |
| FGRCCOpnd, FGR32Opnd, FGR32Opnd, |
| /* CMP_SUN_S_MMR6 */ |
| FGRCCOpnd, FGR32Opnd, FGR32Opnd, |
| /* CMP_UEQ_D */ |
| FGRCCOpnd, FGR64Opnd, FGR64Opnd, |
| /* CMP_UEQ_D_MMR6 */ |
| FGRCCOpnd, FGR64Opnd, FGR64Opnd, |
| /* CMP_UEQ_S */ |
| FGRCCOpnd, FGR32Opnd, FGR32Opnd, |
| /* CMP_UEQ_S_MMR6 */ |
| FGRCCOpnd, FGR32Opnd, FGR32Opnd, |
| /* CMP_ULE_D */ |
| FGRCCOpnd, FGR64Opnd, FGR64Opnd, |
| /* CMP_ULE_D_MMR6 */ |
| FGRCCOpnd, FGR64Opnd, FGR64Opnd, |
| /* CMP_ULE_S */ |
| FGRCCOpnd, FGR32Opnd, FGR32Opnd, |
| /* CMP_ULE_S_MMR6 */ |
| FGRCCOpnd, FGR32Opnd, FGR32Opnd, |
| /* CMP_ULT_D */ |
| FGRCCOpnd, FGR64Opnd, FGR64Opnd, |
| /* CMP_ULT_D_MMR6 */ |
| FGRCCOpnd, FGR64Opnd, FGR64Opnd, |
| /* CMP_ULT_S */ |
| FGRCCOpnd, FGR32Opnd, FGR32Opnd, |
| /* CMP_ULT_S_MMR6 */ |
| FGRCCOpnd, FGR32Opnd, FGR32Opnd, |
| /* CMP_UN_D */ |
| FGRCCOpnd, FGR64Opnd, FGR64Opnd, |
| /* CMP_UN_D_MMR6 */ |
| FGRCCOpnd, FGR64Opnd, FGR64Opnd, |
| /* CMP_UN_S */ |
| FGRCCOpnd, FGR32Opnd, FGR32Opnd, |
| /* CMP_UN_S_MMR6 */ |
| FGRCCOpnd, FGR32Opnd, FGR32Opnd, |
| /* COPY_S_B */ |
| GPR32Opnd, MSA128BOpnd, uimm4_ptr, |
| /* COPY_S_D */ |
| GPR64Opnd, MSA128DOpnd, uimm1_ptr, |
| /* COPY_S_H */ |
| GPR32Opnd, MSA128HOpnd, uimm3_ptr, |
| /* COPY_S_W */ |
| GPR32Opnd, MSA128WOpnd, uimm2_ptr, |
| /* COPY_U_B */ |
| GPR32Opnd, MSA128BOpnd, uimm4_ptr, |
| /* COPY_U_H */ |
| GPR32Opnd, MSA128HOpnd, uimm3_ptr, |
| /* COPY_U_W */ |
| GPR32Opnd, MSA128WOpnd, uimm2_ptr, |
| /* CRC32B */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* CRC32CB */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* CRC32CD */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* CRC32CH */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* CRC32CW */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* CRC32D */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* CRC32H */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* CRC32W */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* CTC1 */ |
| CCROpnd, GPR32Opnd, |
| /* CTC1_MM */ |
| CCROpnd, GPR32Opnd, |
| /* CTC2_MM */ |
| COP2Opnd, GPR32Opnd, |
| /* CTCMSA */ |
| MSA128CROpnd, GPR32Opnd, |
| /* CVT_D32_S */ |
| AFGR64Opnd, FGR32Opnd, |
| /* CVT_D32_S_MM */ |
| AFGR64Opnd, FGR32Opnd, |
| /* CVT_D32_W */ |
| AFGR64Opnd, FGR32Opnd, |
| /* CVT_D32_W_MM */ |
| AFGR64Opnd, FGR32Opnd, |
| /* CVT_D64_L */ |
| FGR64Opnd, FGR64Opnd, |
| /* CVT_D64_S */ |
| FGR64Opnd, FGR32Opnd, |
| /* CVT_D64_S_MM */ |
| FGR64Opnd, FGR32Opnd, |
| /* CVT_D64_W */ |
| FGR64Opnd, FGR32Opnd, |
| /* CVT_D64_W_MM */ |
| FGR64Opnd, FGR32Opnd, |
| /* CVT_D_L_MMR6 */ |
| FGR64Opnd, FGR64Opnd, |
| /* CVT_L_D64 */ |
| FGR64Opnd, FGR64Opnd, |
| /* CVT_L_D64_MM */ |
| FGR64Opnd, FGR64Opnd, |
| /* CVT_L_D_MMR6 */ |
| FGR64Opnd, FGR64Opnd, |
| /* CVT_L_S */ |
| FGR64Opnd, FGR32Opnd, |
| /* CVT_L_S_MM */ |
| FGR64Opnd, FGR32Opnd, |
| /* CVT_L_S_MMR6 */ |
| FGR64Opnd, FGR32Opnd, |
| /* CVT_PS_PW64 */ |
| FGR64Opnd, FGR64Opnd, |
| /* CVT_PS_S64 */ |
| FGR64Opnd, FGR32Opnd, FGR32Opnd, |
| /* CVT_PW_PS64 */ |
| FGR64Opnd, FGR64Opnd, |
| /* CVT_S_D32 */ |
| FGR32Opnd, AFGR64Opnd, |
| /* CVT_S_D32_MM */ |
| FGR32Opnd, AFGR64Opnd, |
| /* CVT_S_D64 */ |
| FGR32Opnd, FGR64Opnd, |
| /* CVT_S_D64_MM */ |
| FGR32Opnd, FGR64Opnd, |
| /* CVT_S_L */ |
| FGR32Opnd, FGR64Opnd, |
| /* CVT_S_L_MMR6 */ |
| FGR64Opnd, FGR32Opnd, |
| /* CVT_S_PL64 */ |
| FGR32Opnd, FGR64Opnd, |
| /* CVT_S_PU64 */ |
| FGR32Opnd, FGR64Opnd, |
| /* CVT_S_W */ |
| FGR32Opnd, FGR32Opnd, |
| /* CVT_S_W_MM */ |
| FGR32Opnd, FGR32Opnd, |
| /* CVT_S_W_MMR6 */ |
| FGR32Opnd, FGR32Opnd, |
| /* CVT_W_D32 */ |
| FGR32Opnd, AFGR64Opnd, |
| /* CVT_W_D32_MM */ |
| FGR32Opnd, AFGR64Opnd, |
| /* CVT_W_D64 */ |
| FGR32Opnd, FGR64Opnd, |
| /* CVT_W_D64_MM */ |
| FGR32Opnd, FGR64Opnd, |
| /* CVT_W_S */ |
| FGR32Opnd, FGR32Opnd, |
| /* CVT_W_S_MM */ |
| FGR32Opnd, FGR32Opnd, |
| /* CVT_W_S_MMR6 */ |
| FGR32Opnd, FGR32Opnd, |
| /* C_EQ_D32 */ |
| FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, |
| /* C_EQ_D32_MM */ |
| FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, |
| /* C_EQ_D64 */ |
| FCCRegsOpnd, FGR64Opnd, FGR64Opnd, |
| /* C_EQ_D64_MM */ |
| FCCRegsOpnd, FGR64Opnd, FGR64Opnd, |
| /* C_EQ_S */ |
| FCCRegsOpnd, FGR32Opnd, FGR32Opnd, |
| /* C_EQ_S_MM */ |
| FCCRegsOpnd, FGR32Opnd, FGR32Opnd, |
| /* C_F_D32 */ |
| FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, |
| /* C_F_D32_MM */ |
| FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, |
| /* C_F_D64 */ |
| FCCRegsOpnd, FGR64Opnd, FGR64Opnd, |
| /* C_F_D64_MM */ |
| FCCRegsOpnd, FGR64Opnd, FGR64Opnd, |
| /* C_F_S */ |
| FCCRegsOpnd, FGR32Opnd, FGR32Opnd, |
| /* C_F_S_MM */ |
| FCCRegsOpnd, FGR32Opnd, FGR32Opnd, |
| /* C_LE_D32 */ |
| FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, |
| /* C_LE_D32_MM */ |
| FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, |
| /* C_LE_D64 */ |
| FCCRegsOpnd, FGR64Opnd, FGR64Opnd, |
| /* C_LE_D64_MM */ |
| FCCRegsOpnd, FGR64Opnd, FGR64Opnd, |
| /* C_LE_S */ |
| FCCRegsOpnd, FGR32Opnd, FGR32Opnd, |
| /* C_LE_S_MM */ |
| FCCRegsOpnd, FGR32Opnd, FGR32Opnd, |
| /* C_LT_D32 */ |
| FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, |
| /* C_LT_D32_MM */ |
| FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, |
| /* C_LT_D64 */ |
| FCCRegsOpnd, FGR64Opnd, FGR64Opnd, |
| /* C_LT_D64_MM */ |
| FCCRegsOpnd, FGR64Opnd, FGR64Opnd, |
| /* C_LT_S */ |
| FCCRegsOpnd, FGR32Opnd, FGR32Opnd, |
| /* C_LT_S_MM */ |
| FCCRegsOpnd, FGR32Opnd, FGR32Opnd, |
| /* C_NGE_D32 */ |
| FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, |
| /* C_NGE_D32_MM */ |
| FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, |
| /* C_NGE_D64 */ |
| FCCRegsOpnd, FGR64Opnd, FGR64Opnd, |
| /* C_NGE_D64_MM */ |
| FCCRegsOpnd, FGR64Opnd, FGR64Opnd, |
| /* C_NGE_S */ |
| FCCRegsOpnd, FGR32Opnd, FGR32Opnd, |
| /* C_NGE_S_MM */ |
| FCCRegsOpnd, FGR32Opnd, FGR32Opnd, |
| /* C_NGLE_D32 */ |
| FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, |
| /* C_NGLE_D32_MM */ |
| FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, |
| /* C_NGLE_D64 */ |
| FCCRegsOpnd, FGR64Opnd, FGR64Opnd, |
| /* C_NGLE_D64_MM */ |
| FCCRegsOpnd, FGR64Opnd, FGR64Opnd, |
| /* C_NGLE_S */ |
| FCCRegsOpnd, FGR32Opnd, FGR32Opnd, |
| /* C_NGLE_S_MM */ |
| FCCRegsOpnd, FGR32Opnd, FGR32Opnd, |
| /* C_NGL_D32 */ |
| FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, |
| /* C_NGL_D32_MM */ |
| FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, |
| /* C_NGL_D64 */ |
| FCCRegsOpnd, FGR64Opnd, FGR64Opnd, |
| /* C_NGL_D64_MM */ |
| FCCRegsOpnd, FGR64Opnd, FGR64Opnd, |
| /* C_NGL_S */ |
| FCCRegsOpnd, FGR32Opnd, FGR32Opnd, |
| /* C_NGL_S_MM */ |
| FCCRegsOpnd, FGR32Opnd, FGR32Opnd, |
| /* C_NGT_D32 */ |
| FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, |
| /* C_NGT_D32_MM */ |
| FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, |
| /* C_NGT_D64 */ |
| FCCRegsOpnd, FGR64Opnd, FGR64Opnd, |
| /* C_NGT_D64_MM */ |
| FCCRegsOpnd, FGR64Opnd, FGR64Opnd, |
| /* C_NGT_S */ |
| FCCRegsOpnd, FGR32Opnd, FGR32Opnd, |
| /* C_NGT_S_MM */ |
| FCCRegsOpnd, FGR32Opnd, FGR32Opnd, |
| /* C_OLE_D32 */ |
| FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, |
| /* C_OLE_D32_MM */ |
| FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, |
| /* C_OLE_D64 */ |
| FCCRegsOpnd, FGR64Opnd, FGR64Opnd, |
| /* C_OLE_D64_MM */ |
| FCCRegsOpnd, FGR64Opnd, FGR64Opnd, |
| /* C_OLE_S */ |
| FCCRegsOpnd, FGR32Opnd, FGR32Opnd, |
| /* C_OLE_S_MM */ |
| FCCRegsOpnd, FGR32Opnd, FGR32Opnd, |
| /* C_OLT_D32 */ |
| FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, |
| /* C_OLT_D32_MM */ |
| FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, |
| /* C_OLT_D64 */ |
| FCCRegsOpnd, FGR64Opnd, FGR64Opnd, |
| /* C_OLT_D64_MM */ |
| FCCRegsOpnd, FGR64Opnd, FGR64Opnd, |
| /* C_OLT_S */ |
| FCCRegsOpnd, FGR32Opnd, FGR32Opnd, |
| /* C_OLT_S_MM */ |
| FCCRegsOpnd, FGR32Opnd, FGR32Opnd, |
| /* C_SEQ_D32 */ |
| FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, |
| /* C_SEQ_D32_MM */ |
| FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, |
| /* C_SEQ_D64 */ |
| FCCRegsOpnd, FGR64Opnd, FGR64Opnd, |
| /* C_SEQ_D64_MM */ |
| FCCRegsOpnd, FGR64Opnd, FGR64Opnd, |
| /* C_SEQ_S */ |
| FCCRegsOpnd, FGR32Opnd, FGR32Opnd, |
| /* C_SEQ_S_MM */ |
| FCCRegsOpnd, FGR32Opnd, FGR32Opnd, |
| /* C_SF_D32 */ |
| FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, |
| /* C_SF_D32_MM */ |
| FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, |
| /* C_SF_D64 */ |
| FCCRegsOpnd, FGR64Opnd, FGR64Opnd, |
| /* C_SF_D64_MM */ |
| FCCRegsOpnd, FGR64Opnd, FGR64Opnd, |
| /* C_SF_S */ |
| FCCRegsOpnd, FGR32Opnd, FGR32Opnd, |
| /* C_SF_S_MM */ |
| FCCRegsOpnd, FGR32Opnd, FGR32Opnd, |
| /* C_UEQ_D32 */ |
| FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, |
| /* C_UEQ_D32_MM */ |
| FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, |
| /* C_UEQ_D64 */ |
| FCCRegsOpnd, FGR64Opnd, FGR64Opnd, |
| /* C_UEQ_D64_MM */ |
| FCCRegsOpnd, FGR64Opnd, FGR64Opnd, |
| /* C_UEQ_S */ |
| FCCRegsOpnd, FGR32Opnd, FGR32Opnd, |
| /* C_UEQ_S_MM */ |
| FCCRegsOpnd, FGR32Opnd, FGR32Opnd, |
| /* C_ULE_D32 */ |
| FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, |
| /* C_ULE_D32_MM */ |
| FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, |
| /* C_ULE_D64 */ |
| FCCRegsOpnd, FGR64Opnd, FGR64Opnd, |
| /* C_ULE_D64_MM */ |
| FCCRegsOpnd, FGR64Opnd, FGR64Opnd, |
| /* C_ULE_S */ |
| FCCRegsOpnd, FGR32Opnd, FGR32Opnd, |
| /* C_ULE_S_MM */ |
| FCCRegsOpnd, FGR32Opnd, FGR32Opnd, |
| /* C_ULT_D32 */ |
| FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, |
| /* C_ULT_D32_MM */ |
| FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, |
| /* C_ULT_D64 */ |
| FCCRegsOpnd, FGR64Opnd, FGR64Opnd, |
| /* C_ULT_D64_MM */ |
| FCCRegsOpnd, FGR64Opnd, FGR64Opnd, |
| /* C_ULT_S */ |
| FCCRegsOpnd, FGR32Opnd, FGR32Opnd, |
| /* C_ULT_S_MM */ |
| FCCRegsOpnd, FGR32Opnd, FGR32Opnd, |
| /* C_UN_D32 */ |
| FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, |
| /* C_UN_D32_MM */ |
| FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, |
| /* C_UN_D64 */ |
| FCCRegsOpnd, FGR64Opnd, FGR64Opnd, |
| /* C_UN_D64_MM */ |
| FCCRegsOpnd, FGR64Opnd, FGR64Opnd, |
| /* C_UN_S */ |
| FCCRegsOpnd, FGR32Opnd, FGR32Opnd, |
| /* C_UN_S_MM */ |
| FCCRegsOpnd, FGR32Opnd, FGR32Opnd, |
| /* CmpRxRy16 */ |
| CPU16Regs, CPU16Regs, |
| /* CmpiRxImm16 */ |
| CPU16Regs, simm16, |
| /* CmpiRxImmX16 */ |
| CPU16Regs, simm16, |
| /* DADD */ |
| GPR64Opnd, GPR64Opnd, GPR64Opnd, |
| /* DADDi */ |
| GPR64Opnd, GPR64Opnd, simm16_64, |
| /* DADDiu */ |
| GPR64Opnd, GPR64Opnd, simm16_64, |
| /* DADDu */ |
| GPR64Opnd, GPR64Opnd, GPR64Opnd, |
| /* DAHI */ |
| GPR64Opnd, GPR64Opnd, uimm16_altrelaxed, |
| /* DALIGN */ |
| GPR64Opnd, GPR64Opnd, GPR64Opnd, uimm3, |
| /* DATI */ |
| GPR64Opnd, GPR64Opnd, uimm16_altrelaxed, |
| /* DAUI */ |
| GPR64Opnd, GPR64Opnd, uimm16, |
| /* DBITSWAP */ |
| GPR64Opnd, GPR64Opnd, |
| /* DCLO */ |
| GPR64Opnd, GPR64Opnd, |
| /* DCLO_R6 */ |
| GPR64Opnd, GPR64Opnd, |
| /* DCLZ */ |
| GPR64Opnd, GPR64Opnd, |
| /* DCLZ_R6 */ |
| GPR64Opnd, GPR64Opnd, |
| /* DDIV */ |
| GPR64Opnd, GPR64Opnd, GPR64Opnd, |
| /* DDIVU */ |
| GPR64Opnd, GPR64Opnd, GPR64Opnd, |
| /* DERET */ |
| /* DERET_MM */ |
| /* DERET_MMR6 */ |
| /* DEXT */ |
| GPR64Opnd, GPR64Opnd, uimm5_report_uimm6, uimm5_plus1_report_uimm6, |
| /* DEXT64_32 */ |
| GPR64Opnd, GPR32Opnd, uimm5_report_uimm6, uimm5_plus1, |
| /* DEXTM */ |
| GPR64Opnd, GPR64Opnd, uimm5, uimm5_plus33, |
| /* DEXTU */ |
| GPR64Opnd, GPR64Opnd, uimm5_plus32, uimm5_plus1, |
| /* DI */ |
| GPR32Opnd, |
| /* DINS */ |
| GPR64Opnd, GPR64Opnd, uimm6, uimm5_inssize_plus1, GPR64Opnd, |
| /* DINSM */ |
| GPR64Opnd, GPR64Opnd, uimm5, uimm_range_2_64, GPR64Opnd, |
| /* DINSU */ |
| GPR64Opnd, GPR64Opnd, uimm5_plus32, uimm5_inssize_plus1, GPR64Opnd, |
| /* DIV */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* DIVU */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* DIVU_MMR6 */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* DIV_MMR6 */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* DIV_S_B */ |
| MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
| /* DIV_S_D */ |
| MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
| /* DIV_S_H */ |
| MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
| /* DIV_S_W */ |
| MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* DIV_U_B */ |
| MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
| /* DIV_U_D */ |
| MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
| /* DIV_U_H */ |
| MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
| /* DIV_U_W */ |
| MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* DI_MM */ |
| GPR32Opnd, |
| /* DI_MMR6 */ |
| GPR32Opnd, |
| /* DLSA */ |
| GPR64Opnd, GPR64Opnd, GPR64Opnd, uimm2_plus1, |
| /* DLSA_R6 */ |
| GPR64Opnd, GPR64Opnd, GPR64Opnd, uimm2_plus1, |
| /* DMFC0 */ |
| GPR64Opnd, COP0Opnd, uimm3, |
| /* DMFC1 */ |
| GPR64Opnd, FGR64Opnd, |
| /* DMFC2 */ |
| GPR64Opnd, COP2Opnd, uimm3, |
| /* DMFC2_OCTEON */ |
| GPR64Opnd, uimm16, |
| /* DMFGC0 */ |
| GPR64Opnd, COP0Opnd, uimm3, |
| /* DMOD */ |
| GPR64Opnd, GPR64Opnd, GPR64Opnd, |
| /* DMODU */ |
| GPR64Opnd, GPR64Opnd, GPR64Opnd, |
| /* DMT */ |
| GPR32Opnd, |
| /* DMTC0 */ |
| COP0Opnd, GPR64Opnd, uimm3, |
| /* DMTC1 */ |
| FGR64Opnd, GPR64Opnd, |
| /* DMTC2 */ |
| COP2Opnd, GPR64Opnd, uimm3, |
| /* DMTC2_OCTEON */ |
| GPR64Opnd, uimm16, |
| /* DMTGC0 */ |
| COP0Opnd, GPR64Opnd, uimm3, |
| /* DMUH */ |
| GPR64Opnd, GPR64Opnd, GPR64Opnd, |
| /* DMUHU */ |
| GPR64Opnd, GPR64Opnd, GPR64Opnd, |
| /* DMUL */ |
| GPR64Opnd, GPR64Opnd, GPR64Opnd, |
| /* DMULT */ |
| GPR64Opnd, GPR64Opnd, |
| /* DMULTu */ |
| GPR64Opnd, GPR64Opnd, |
| /* DMULU */ |
| GPR64Opnd, GPR64Opnd, GPR64Opnd, |
| /* DMUL_R6 */ |
| GPR64Opnd, GPR64Opnd, GPR64Opnd, |
| /* DOTP_S_D */ |
| MSA128DOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* DOTP_S_H */ |
| MSA128HOpnd, MSA128BOpnd, MSA128BOpnd, |
| /* DOTP_S_W */ |
| MSA128WOpnd, MSA128HOpnd, MSA128HOpnd, |
| /* DOTP_U_D */ |
| MSA128DOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* DOTP_U_H */ |
| MSA128HOpnd, MSA128BOpnd, MSA128BOpnd, |
| /* DOTP_U_W */ |
| MSA128WOpnd, MSA128HOpnd, MSA128HOpnd, |
| /* DPADD_S_D */ |
| MSA128DOpnd, MSA128DOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* DPADD_S_H */ |
| MSA128HOpnd, MSA128HOpnd, MSA128BOpnd, MSA128BOpnd, |
| /* DPADD_S_W */ |
| MSA128WOpnd, MSA128WOpnd, MSA128HOpnd, MSA128HOpnd, |
| /* DPADD_U_D */ |
| MSA128DOpnd, MSA128DOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* DPADD_U_H */ |
| MSA128HOpnd, MSA128HOpnd, MSA128BOpnd, MSA128BOpnd, |
| /* DPADD_U_W */ |
| MSA128WOpnd, MSA128WOpnd, MSA128HOpnd, MSA128HOpnd, |
| /* DPAQX_SA_W_PH */ |
| ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
| /* DPAQX_SA_W_PH_MMR2 */ |
| ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
| /* DPAQX_S_W_PH */ |
| ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
| /* DPAQX_S_W_PH_MMR2 */ |
| ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
| /* DPAQ_SA_L_W */ |
| ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
| /* DPAQ_SA_L_W_MM */ |
| ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
| /* DPAQ_S_W_PH */ |
| ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
| /* DPAQ_S_W_PH_MM */ |
| ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
| /* DPAU_H_QBL */ |
| ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
| /* DPAU_H_QBL_MM */ |
| ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
| /* DPAU_H_QBR */ |
| ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
| /* DPAU_H_QBR_MM */ |
| ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
| /* DPAX_W_PH */ |
| ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
| /* DPAX_W_PH_MMR2 */ |
| ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
| /* DPA_W_PH */ |
| ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
| /* DPA_W_PH_MMR2 */ |
| ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
| /* DPOP */ |
| GPR64Opnd, GPR64Opnd, |
| /* DPSQX_SA_W_PH */ |
| ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
| /* DPSQX_SA_W_PH_MMR2 */ |
| ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
| /* DPSQX_S_W_PH */ |
| ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
| /* DPSQX_S_W_PH_MMR2 */ |
| ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
| /* DPSQ_SA_L_W */ |
| ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
| /* DPSQ_SA_L_W_MM */ |
| ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
| /* DPSQ_S_W_PH */ |
| ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
| /* DPSQ_S_W_PH_MM */ |
| ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
| /* DPSUB_S_D */ |
| MSA128DOpnd, MSA128DOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* DPSUB_S_H */ |
| MSA128HOpnd, MSA128HOpnd, MSA128BOpnd, MSA128BOpnd, |
| /* DPSUB_S_W */ |
| MSA128WOpnd, MSA128WOpnd, MSA128HOpnd, MSA128HOpnd, |
| /* DPSUB_U_D */ |
| MSA128DOpnd, MSA128DOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* DPSUB_U_H */ |
| MSA128HOpnd, MSA128HOpnd, MSA128BOpnd, MSA128BOpnd, |
| /* DPSUB_U_W */ |
| MSA128WOpnd, MSA128WOpnd, MSA128HOpnd, MSA128HOpnd, |
| /* DPSU_H_QBL */ |
| ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
| /* DPSU_H_QBL_MM */ |
| ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
| /* DPSU_H_QBR */ |
| ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
| /* DPSU_H_QBR_MM */ |
| ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
| /* DPSX_W_PH */ |
| ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
| /* DPSX_W_PH_MMR2 */ |
| ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
| /* DPS_W_PH */ |
| ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
| /* DPS_W_PH_MMR2 */ |
| ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
| /* DROTR */ |
| GPR64Opnd, GPR64Opnd, uimm6, |
| /* DROTR32 */ |
| GPR64Opnd, GPR64Opnd, uimm5, |
| /* DROTRV */ |
| GPR64Opnd, GPR64Opnd, GPR32Opnd, |
| /* DSBH */ |
| GPR64Opnd, GPR64Opnd, |
| /* DSDIV */ |
| GPR64Opnd, GPR64Opnd, |
| /* DSHD */ |
| GPR64Opnd, GPR64Opnd, |
| /* DSLL */ |
| GPR64Opnd, GPR64Opnd, uimm6, |
| /* DSLL32 */ |
| GPR64Opnd, GPR64Opnd, uimm5, |
| /* DSLL64_32 */ |
| GPR64, GPR32, |
| /* DSLLV */ |
| GPR64Opnd, GPR64Opnd, GPR32Opnd, |
| /* DSRA */ |
| GPR64Opnd, GPR64Opnd, uimm6, |
| /* DSRA32 */ |
| GPR64Opnd, GPR64Opnd, uimm5, |
| /* DSRAV */ |
| GPR64Opnd, GPR64Opnd, GPR32Opnd, |
| /* DSRL */ |
| GPR64Opnd, GPR64Opnd, uimm6, |
| /* DSRL32 */ |
| GPR64Opnd, GPR64Opnd, uimm5, |
| /* DSRLV */ |
| GPR64Opnd, GPR64Opnd, GPR32Opnd, |
| /* DSUB */ |
| GPR64Opnd, GPR64Opnd, GPR64Opnd, |
| /* DSUBu */ |
| GPR64Opnd, GPR64Opnd, GPR64Opnd, |
| /* DUDIV */ |
| GPR64Opnd, GPR64Opnd, |
| /* DVP */ |
| GPR32Opnd, |
| /* DVPE */ |
| GPR32Opnd, |
| /* DVP_MMR6 */ |
| GPR32Opnd, |
| /* DivRxRy16 */ |
| CPU16Regs, CPU16Regs, |
| /* DivuRxRy16 */ |
| CPU16Regs, CPU16Regs, |
| /* EHB */ |
| /* EHB_MM */ |
| /* EHB_MMR6 */ |
| /* EI */ |
| GPR32Opnd, |
| /* EI_MM */ |
| GPR32Opnd, |
| /* EI_MMR6 */ |
| GPR32Opnd, |
| /* EMT */ |
| GPR32Opnd, |
| /* ERET */ |
| /* ERETNC */ |
| /* ERETNC_MMR6 */ |
| /* ERET_MM */ |
| /* ERET_MMR6 */ |
| /* EVP */ |
| GPR32Opnd, |
| /* EVPE */ |
| GPR32Opnd, |
| /* EVP_MMR6 */ |
| GPR32Opnd, |
| /* EXT */ |
| GPR32Opnd, GPR32Opnd, uimm5, uimm5_plus1, |
| /* EXTP */ |
| GPR32Opnd, ACC64DSPOpnd, uimm5, |
| /* EXTPDP */ |
| GPR32Opnd, ACC64DSPOpnd, uimm5, |
| /* EXTPDPV */ |
| GPR32Opnd, ACC64DSPOpnd, GPR32Opnd, |
| /* EXTPDPV_MM */ |
| GPR32Opnd, ACC64DSPOpnd, GPR32Opnd, |
| /* EXTPDP_MM */ |
| GPR32Opnd, ACC64DSPOpnd, uimm5, |
| /* EXTPV */ |
| GPR32Opnd, ACC64DSPOpnd, GPR32Opnd, |
| /* EXTPV_MM */ |
| GPR32Opnd, ACC64DSPOpnd, GPR32Opnd, |
| /* EXTP_MM */ |
| GPR32Opnd, ACC64DSPOpnd, uimm5, |
| /* EXTRV_RS_W */ |
| GPR32Opnd, ACC64DSPOpnd, GPR32Opnd, |
| /* EXTRV_RS_W_MM */ |
| GPR32Opnd, ACC64DSPOpnd, GPR32Opnd, |
| /* EXTRV_R_W */ |
| GPR32Opnd, ACC64DSPOpnd, GPR32Opnd, |
| /* EXTRV_R_W_MM */ |
| GPR32Opnd, ACC64DSPOpnd, GPR32Opnd, |
| /* EXTRV_S_H */ |
| GPR32Opnd, ACC64DSPOpnd, GPR32Opnd, |
| /* EXTRV_S_H_MM */ |
| GPR32Opnd, ACC64DSPOpnd, GPR32Opnd, |
| /* EXTRV_W */ |
| GPR32Opnd, ACC64DSPOpnd, GPR32Opnd, |
| /* EXTRV_W_MM */ |
| GPR32Opnd, ACC64DSPOpnd, GPR32Opnd, |
| /* EXTR_RS_W */ |
| GPR32Opnd, ACC64DSPOpnd, uimm5, |
| /* EXTR_RS_W_MM */ |
| GPR32Opnd, ACC64DSPOpnd, uimm5, |
| /* EXTR_R_W */ |
| GPR32Opnd, ACC64DSPOpnd, uimm5, |
| /* EXTR_R_W_MM */ |
| GPR32Opnd, ACC64DSPOpnd, uimm5, |
| /* EXTR_S_H */ |
| GPR32Opnd, ACC64DSPOpnd, uimm5, |
| /* EXTR_S_H_MM */ |
| GPR32Opnd, ACC64DSPOpnd, uimm5, |
| /* EXTR_W */ |
| GPR32Opnd, ACC64DSPOpnd, uimm5, |
| /* EXTR_W_MM */ |
| GPR32Opnd, ACC64DSPOpnd, uimm5, |
| /* EXTS */ |
| GPR64Opnd, GPR64Opnd, uimm5, uimm5, |
| /* EXTS32 */ |
| GPR64Opnd, GPR64Opnd, uimm5, uimm5, |
| /* EXT_MM */ |
| GPR32Opnd, GPR32Opnd, uimm5, uimm5_plus1, |
| /* EXT_MMR6 */ |
| GPR32Opnd, GPR32Opnd, uimm5, uimm5_plus1, |
| /* FABS_D32 */ |
| AFGR64Opnd, AFGR64Opnd, |
| /* FABS_D32_MM */ |
| AFGR64Opnd, AFGR64Opnd, |
| /* FABS_D64 */ |
| FGR64Opnd, FGR64Opnd, |
| /* FABS_D64_MM */ |
| FGR64Opnd, FGR64Opnd, |
| /* FABS_S */ |
| FGR32Opnd, FGR32Opnd, |
| /* FABS_S_MM */ |
| FGR32Opnd, FGR32Opnd, |
| /* FADD_D */ |
| MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
| /* FADD_D32 */ |
| AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, |
| /* FADD_D32_MM */ |
| AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, |
| /* FADD_D64 */ |
| FGR64Opnd, FGR64Opnd, FGR64Opnd, |
| /* FADD_D64_MM */ |
| FGR64Opnd, FGR64Opnd, FGR64Opnd, |
| /* FADD_PS64 */ |
| FGR64Opnd, FGR64Opnd, FGR64Opnd, |
| /* FADD_S */ |
| FGR32Opnd, FGR32Opnd, FGR32Opnd, |
| /* FADD_S_MM */ |
| FGR32Opnd, FGR32Opnd, FGR32Opnd, |
| /* FADD_S_MMR6 */ |
| FGR32Opnd, FGR32Opnd, FGR32Opnd, |
| /* FADD_W */ |
| MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* FCAF_D */ |
| MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
| /* FCAF_W */ |
| MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* FCEQ_D */ |
| MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
| /* FCEQ_W */ |
| MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* FCLASS_D */ |
| MSA128DOpnd, MSA128DOpnd, |
| /* FCLASS_W */ |
| MSA128WOpnd, MSA128WOpnd, |
| /* FCLE_D */ |
| MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
| /* FCLE_W */ |
| MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* FCLT_D */ |
| MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
| /* FCLT_W */ |
| MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* FCMP_D32 */ |
| AFGR64, AFGR64, condcode, |
| /* FCMP_D32_MM */ |
| AFGR64, AFGR64, condcode, |
| /* FCMP_D64 */ |
| FGR64, FGR64, condcode, |
| /* FCMP_S32 */ |
| FGR32, FGR32, condcode, |
| /* FCMP_S32_MM */ |
| FGR32, FGR32, condcode, |
| /* FCNE_D */ |
| MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
| /* FCNE_W */ |
| MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* FCOR_D */ |
| MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
| /* FCOR_W */ |
| MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* FCUEQ_D */ |
| MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
| /* FCUEQ_W */ |
| MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* FCULE_D */ |
| MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
| /* FCULE_W */ |
| MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* FCULT_D */ |
| MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
| /* FCULT_W */ |
| MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* FCUNE_D */ |
| MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
| /* FCUNE_W */ |
| MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* FCUN_D */ |
| MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
| /* FCUN_W */ |
| MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* FDIV_D */ |
| MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
| /* FDIV_D32 */ |
| AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, |
| /* FDIV_D32_MM */ |
| AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, |
| /* FDIV_D64 */ |
| FGR64Opnd, FGR64Opnd, FGR64Opnd, |
| /* FDIV_D64_MM */ |
| FGR64Opnd, FGR64Opnd, FGR64Opnd, |
| /* FDIV_S */ |
| FGR32Opnd, FGR32Opnd, FGR32Opnd, |
| /* FDIV_S_MM */ |
| FGR32Opnd, FGR32Opnd, FGR32Opnd, |
| /* FDIV_S_MMR6 */ |
| FGR32Opnd, FGR32Opnd, FGR32Opnd, |
| /* FDIV_W */ |
| MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* FEXDO_H */ |
| MSA128HOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* FEXDO_W */ |
| MSA128WOpnd, MSA128DOpnd, MSA128DOpnd, |
| /* FEXP2_D */ |
| MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
| /* FEXP2_W */ |
| MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* FEXUPL_D */ |
| MSA128DOpnd, MSA128WOpnd, |
| /* FEXUPL_W */ |
| MSA128WOpnd, MSA128HOpnd, |
| /* FEXUPR_D */ |
| MSA128DOpnd, MSA128WOpnd, |
| /* FEXUPR_W */ |
| MSA128WOpnd, MSA128HOpnd, |
| /* FFINT_S_D */ |
| MSA128DOpnd, MSA128DOpnd, |
| /* FFINT_S_W */ |
| MSA128WOpnd, MSA128WOpnd, |
| /* FFINT_U_D */ |
| MSA128DOpnd, MSA128DOpnd, |
| /* FFINT_U_W */ |
| MSA128WOpnd, MSA128WOpnd, |
| /* FFQL_D */ |
| MSA128DOpnd, MSA128WOpnd, |
| /* FFQL_W */ |
| MSA128WOpnd, MSA128HOpnd, |
| /* FFQR_D */ |
| MSA128DOpnd, MSA128WOpnd, |
| /* FFQR_W */ |
| MSA128WOpnd, MSA128HOpnd, |
| /* FILL_B */ |
| MSA128BOpnd, GPR32Opnd, |
| /* FILL_D */ |
| MSA128DOpnd, GPR64Opnd, |
| /* FILL_H */ |
| MSA128HOpnd, GPR32Opnd, |
| /* FILL_W */ |
| MSA128WOpnd, GPR32Opnd, |
| /* FLOG2_D */ |
| MSA128DOpnd, MSA128DOpnd, |
| /* FLOG2_W */ |
| MSA128WOpnd, MSA128WOpnd, |
| /* FLOOR_L_D64 */ |
| FGR64Opnd, FGR64Opnd, |
| /* FLOOR_L_D_MMR6 */ |
| FGR64Opnd, FGR64Opnd, |
| /* FLOOR_L_S */ |
| FGR64Opnd, FGR32Opnd, |
| /* FLOOR_L_S_MMR6 */ |
| FGR64Opnd, FGR32Opnd, |
| /* FLOOR_W_D32 */ |
| FGR32Opnd, AFGR64Opnd, |
| /* FLOOR_W_D64 */ |
| FGR32Opnd, FGR64Opnd, |
| /* FLOOR_W_D_MMR6 */ |
| FGR32Opnd, AFGR64Opnd, |
| /* FLOOR_W_MM */ |
| FGR32Opnd, AFGR64Opnd, |
| /* FLOOR_W_S */ |
| FGR32Opnd, FGR32Opnd, |
| /* FLOOR_W_S_MM */ |
| FGR32Opnd, FGR32Opnd, |
| /* FLOOR_W_S_MMR6 */ |
| FGR32Opnd, FGR32Opnd, |
| /* FMADD_D */ |
| MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
| /* FMADD_W */ |
| MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* FMAX_A_D */ |
| MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
| /* FMAX_A_W */ |
| MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* FMAX_D */ |
| MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
| /* FMAX_W */ |
| MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* FMIN_A_D */ |
| MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
| /* FMIN_A_W */ |
| MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* FMIN_D */ |
| MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
| /* FMIN_W */ |
| MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* FMOV_D32 */ |
| AFGR64Opnd, AFGR64Opnd, |
| /* FMOV_D32_MM */ |
| AFGR64Opnd, AFGR64Opnd, |
| /* FMOV_D64 */ |
| FGR64Opnd, FGR64Opnd, |
| /* FMOV_D64_MM */ |
| FGR64Opnd, FGR64Opnd, |
| /* FMOV_D_MMR6 */ |
| FGR64Opnd, FGR64Opnd, |
| /* FMOV_S */ |
| FGR32Opnd, FGR32Opnd, |
| /* FMOV_S_MM */ |
| FGR32Opnd, FGR32Opnd, |
| /* FMOV_S_MMR6 */ |
| FGR32Opnd, FGR32Opnd, |
| /* FMSUB_D */ |
| MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
| /* FMSUB_W */ |
| MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* FMUL_D */ |
| MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
| /* FMUL_D32 */ |
| AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, |
| /* FMUL_D32_MM */ |
| AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, |
| /* FMUL_D64 */ |
| FGR64Opnd, FGR64Opnd, FGR64Opnd, |
| /* FMUL_D64_MM */ |
| FGR64Opnd, FGR64Opnd, FGR64Opnd, |
| /* FMUL_PS64 */ |
| FGR64Opnd, FGR64Opnd, FGR64Opnd, |
| /* FMUL_S */ |
| FGR32Opnd, FGR32Opnd, FGR32Opnd, |
| /* FMUL_S_MM */ |
| FGR32Opnd, FGR32Opnd, FGR32Opnd, |
| /* FMUL_S_MMR6 */ |
| FGR32Opnd, FGR32Opnd, FGR32Opnd, |
| /* FMUL_W */ |
| MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* FNEG_D32 */ |
| AFGR64Opnd, AFGR64Opnd, |
| /* FNEG_D32_MM */ |
| AFGR64Opnd, AFGR64Opnd, |
| /* FNEG_D64 */ |
| FGR64Opnd, FGR64Opnd, |
| /* FNEG_D64_MM */ |
| FGR64Opnd, FGR64Opnd, |
| /* FNEG_S */ |
| FGR32Opnd, FGR32Opnd, |
| /* FNEG_S_MM */ |
| FGR32Opnd, FGR32Opnd, |
| /* FNEG_S_MMR6 */ |
| FGR32Opnd, FGR32Opnd, |
| /* FORK */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* FRCP_D */ |
| MSA128DOpnd, MSA128DOpnd, |
| /* FRCP_W */ |
| MSA128WOpnd, MSA128WOpnd, |
| /* FRINT_D */ |
| MSA128DOpnd, MSA128DOpnd, |
| /* FRINT_W */ |
| MSA128WOpnd, MSA128WOpnd, |
| /* FRSQRT_D */ |
| MSA128DOpnd, MSA128DOpnd, |
| /* FRSQRT_W */ |
| MSA128WOpnd, MSA128WOpnd, |
| /* FSAF_D */ |
| MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
| /* FSAF_W */ |
| MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* FSEQ_D */ |
| MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
| /* FSEQ_W */ |
| MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* FSLE_D */ |
| MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
| /* FSLE_W */ |
| MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* FSLT_D */ |
| MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
| /* FSLT_W */ |
| MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* FSNE_D */ |
| MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
| /* FSNE_W */ |
| MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* FSOR_D */ |
| MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
| /* FSOR_W */ |
| MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* FSQRT_D */ |
| MSA128DOpnd, MSA128DOpnd, |
| /* FSQRT_D32 */ |
| AFGR64Opnd, AFGR64Opnd, |
| /* FSQRT_D32_MM */ |
| AFGR64Opnd, AFGR64Opnd, |
| /* FSQRT_D64 */ |
| FGR64Opnd, FGR64Opnd, |
| /* FSQRT_D64_MM */ |
| FGR64Opnd, FGR64Opnd, |
| /* FSQRT_S */ |
| FGR32Opnd, FGR32Opnd, |
| /* FSQRT_S_MM */ |
| FGR32Opnd, FGR32Opnd, |
| /* FSQRT_W */ |
| MSA128WOpnd, MSA128WOpnd, |
| /* FSUB_D */ |
| MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
| /* FSUB_D32 */ |
| AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, |
| /* FSUB_D32_MM */ |
| AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, |
| /* FSUB_D64 */ |
| FGR64Opnd, FGR64Opnd, FGR64Opnd, |
| /* FSUB_D64_MM */ |
| FGR64Opnd, FGR64Opnd, FGR64Opnd, |
| /* FSUB_PS64 */ |
| FGR64Opnd, FGR64Opnd, FGR64Opnd, |
| /* FSUB_S */ |
| FGR32Opnd, FGR32Opnd, FGR32Opnd, |
| /* FSUB_S_MM */ |
| FGR32Opnd, FGR32Opnd, FGR32Opnd, |
| /* FSUB_S_MMR6 */ |
| FGR32Opnd, FGR32Opnd, FGR32Opnd, |
| /* FSUB_W */ |
| MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* FSUEQ_D */ |
| MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
| /* FSUEQ_W */ |
| MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* FSULE_D */ |
| MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
| /* FSULE_W */ |
| MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* FSULT_D */ |
| MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
| /* FSULT_W */ |
| MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* FSUNE_D */ |
| MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
| /* FSUNE_W */ |
| MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* FSUN_D */ |
| MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
| /* FSUN_W */ |
| MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* FTINT_S_D */ |
| MSA128DOpnd, MSA128DOpnd, |
| /* FTINT_S_W */ |
| MSA128WOpnd, MSA128WOpnd, |
| /* FTINT_U_D */ |
| MSA128DOpnd, MSA128DOpnd, |
| /* FTINT_U_W */ |
| MSA128WOpnd, MSA128WOpnd, |
| /* FTQ_H */ |
| MSA128HOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* FTQ_W */ |
| MSA128WOpnd, MSA128DOpnd, MSA128DOpnd, |
| /* FTRUNC_S_D */ |
| MSA128DOpnd, MSA128DOpnd, |
| /* FTRUNC_S_W */ |
| MSA128WOpnd, MSA128WOpnd, |
| /* FTRUNC_U_D */ |
| MSA128DOpnd, MSA128DOpnd, |
| /* FTRUNC_U_W */ |
| MSA128WOpnd, MSA128WOpnd, |
| /* GINVI */ |
| GPR32Opnd, |
| /* GINVI_MMR6 */ |
| GPR32Opnd, |
| /* GINVT */ |
| GPR32Opnd, uimm2, |
| /* GINVT_MMR6 */ |
| GPR32Opnd, uimm2, |
| /* HADD_S_D */ |
| MSA128DOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* HADD_S_H */ |
| MSA128HOpnd, MSA128BOpnd, MSA128BOpnd, |
| /* HADD_S_W */ |
| MSA128WOpnd, MSA128HOpnd, MSA128HOpnd, |
| /* HADD_U_D */ |
| MSA128DOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* HADD_U_H */ |
| MSA128HOpnd, MSA128BOpnd, MSA128BOpnd, |
| /* HADD_U_W */ |
| MSA128WOpnd, MSA128HOpnd, MSA128HOpnd, |
| /* HSUB_S_D */ |
| MSA128DOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* HSUB_S_H */ |
| MSA128HOpnd, MSA128BOpnd, MSA128BOpnd, |
| /* HSUB_S_W */ |
| MSA128WOpnd, MSA128HOpnd, MSA128HOpnd, |
| /* HSUB_U_D */ |
| MSA128DOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* HSUB_U_H */ |
| MSA128HOpnd, MSA128BOpnd, MSA128BOpnd, |
| /* HSUB_U_W */ |
| MSA128WOpnd, MSA128HOpnd, MSA128HOpnd, |
| /* HYPCALL */ |
| uimm10, |
| /* HYPCALL_MM */ |
| uimm10, |
| /* ILVEV_B */ |
| MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
| /* ILVEV_D */ |
| MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
| /* ILVEV_H */ |
| MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
| /* ILVEV_W */ |
| MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* ILVL_B */ |
| MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
| /* ILVL_D */ |
| MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
| /* ILVL_H */ |
| MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
| /* ILVL_W */ |
| MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* ILVOD_B */ |
| MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
| /* ILVOD_D */ |
| MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
| /* ILVOD_H */ |
| MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
| /* ILVOD_W */ |
| MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* ILVR_B */ |
| MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
| /* ILVR_D */ |
| MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
| /* ILVR_H */ |
| MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
| /* ILVR_W */ |
| MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* INS */ |
| GPR32Opnd, GPR32Opnd, uimm5, uimm5_inssize_plus1, GPR32Opnd, |
| /* INSERT_B */ |
| MSA128BOpnd, MSA128BOpnd, GPR32Opnd, uimm4, |
| /* INSERT_D */ |
| MSA128DOpnd, MSA128DOpnd, GPR64Opnd, uimm1, |
| /* INSERT_H */ |
| MSA128HOpnd, MSA128HOpnd, GPR32Opnd, uimm3, |
| /* INSERT_W */ |
| MSA128WOpnd, MSA128WOpnd, GPR32Opnd, uimm2, |
| /* INSV */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* INSVE_B */ |
| MSA128BOpnd, MSA128BOpnd, uimm4, MSA128BOpnd, uimmz, |
| /* INSVE_D */ |
| MSA128DOpnd, MSA128DOpnd, uimm1, MSA128DOpnd, uimmz, |
| /* INSVE_H */ |
| MSA128HOpnd, MSA128HOpnd, uimm3, MSA128HOpnd, uimmz, |
| /* INSVE_W */ |
| MSA128WOpnd, MSA128WOpnd, uimm2, MSA128WOpnd, uimmz, |
| /* INSV_MM */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* INS_MM */ |
| GPR32Opnd, GPR32Opnd, uimm5, uimm5_inssize_plus1, GPR32Opnd, |
| /* INS_MMR6 */ |
| GPR32Opnd, GPR32Opnd, uimm5, uimm5_inssize_plus1, GPR32Opnd, |
| /* J */ |
| jmptarget, |
| /* JAL */ |
| calltarget, |
| /* JALR */ |
| GPR32Opnd, GPR32Opnd, |
| /* JALR16_MM */ |
| GPR32Opnd, |
| /* JALR64 */ |
| GPR64Opnd, GPR64Opnd, |
| /* JALRC16_MMR6 */ |
| GPR32Opnd, |
| /* JALRC_HB_MMR6 */ |
| GPR32Opnd, GPR32Opnd, |
| /* JALRC_MMR6 */ |
| GPR32Opnd, GPR32Opnd, |
| /* JALRS16_MM */ |
| GPR32Opnd, |
| /* JALRS_MM */ |
| GPR32Opnd, GPR32Opnd, |
| /* JALR_HB */ |
| GPR32Opnd, GPR32Opnd, |
| /* JALR_HB64 */ |
| GPR64Opnd, GPR64Opnd, |
| /* JALR_MM */ |
| GPR32Opnd, GPR32Opnd, |
| /* JALS_MM */ |
| calltarget_mm, |
| /* JALX */ |
| calltarget, |
| /* JALX_MM */ |
| calltarget, |
| /* JAL_MM */ |
| calltarget_mm, |
| /* JIALC */ |
| GPR32Opnd, calloffset16, |
| /* JIALC64 */ |
| GPR64Opnd, calloffset16, |
| /* JIALC_MMR6 */ |
| GPR32Opnd, calloffset16, |
| /* JIC */ |
| GPR32Opnd, jmpoffset16, |
| /* JIC64 */ |
| GPR64Opnd, jmpoffset16, |
| /* JIC_MMR6 */ |
| GPR32Opnd, jmpoffset16, |
| /* JR */ |
| GPR32Opnd, |
| /* JR16_MM */ |
| GPR32Opnd, |
| /* JR64 */ |
| GPR64Opnd, |
| /* JRADDIUSP */ |
| uimm5_lsl2, |
| /* JRC16_MM */ |
| GPR32Opnd, |
| /* JRC16_MMR6 */ |
| GPR32Opnd, |
| /* JRCADDIUSP_MMR6 */ |
| uimm5_lsl2, |
| /* JR_HB */ |
| GPR32Opnd, |
| /* JR_HB64 */ |
| GPR64Opnd, |
| /* JR_HB64_R6 */ |
| GPR64Opnd, |
| /* JR_HB_R6 */ |
| GPR32Opnd, |
| /* JR_MM */ |
| GPR32Opnd, |
| /* J_MM */ |
| jmptarget_mm, |
| /* Jal16 */ |
| uimm26, |
| /* JalB16 */ |
| uimm26, |
| /* JrRa16 */ |
| /* JrcRa16 */ |
| /* JrcRx16 */ |
| CPU16Regs, |
| /* JumpLinkReg16 */ |
| CPU16Regs, |
| /* LB */ |
| GPR32Opnd, -1, simm16, |
| /* LB64 */ |
| GPR64Opnd, -1, simm16, |
| /* LBE */ |
| GPR32Opnd, -1, simm9, |
| /* LBE_MM */ |
| GPR32Opnd, -1, simm16, |
| /* LBU16_MM */ |
| GPRMM16Opnd, -1, simm4, |
| /* LBUX */ |
| GPR32Opnd, -1, -1, |
| /* LBUX_MM */ |
| GPR32Opnd, -1, -1, |
| /* LBU_MMR6 */ |
| GPR32Opnd, -1, simm16, |
| /* LB_MM */ |
| GPR32Opnd, -1, simm16, |
| /* LB_MMR6 */ |
| GPR32Opnd, -1, simm16, |
| /* LBu */ |
| GPR32Opnd, -1, simm16, |
| /* LBu64 */ |
| GPR64Opnd, -1, simm16, |
| /* LBuE */ |
| GPR32Opnd, -1, simm9, |
| /* LBuE_MM */ |
| GPR32Opnd, -1, simm16, |
| /* LBu_MM */ |
| GPR32Opnd, -1, simm16, |
| /* LD */ |
| GPR64Opnd, -1, simm16, |
| /* LDC1 */ |
| AFGR64Opnd, -1, simm16, |
| /* LDC164 */ |
| FGR64Opnd, -1, simm16, |
| /* LDC1_D64_MMR6 */ |
| FGR64Opnd, -1, simm16, |
| /* LDC1_MM_D32 */ |
| AFGR64Opnd, -1, simm16, |
| /* LDC1_MM_D64 */ |
| FGR64Opnd, -1, simm16, |
| /* LDC2 */ |
| COP2Opnd, -1, simm16, |
| /* LDC2_MMR6 */ |
| COP2Opnd, GPR32, simm11, |
| /* LDC2_R6 */ |
| COP2Opnd, -1, simm11, |
| /* LDC3 */ |
| COP3Opnd, -1, simm16, |
| /* LDI_B */ |
| MSA128BOpnd, vsplat_simm10, |
| /* LDI_D */ |
| MSA128DOpnd, vsplat_simm10, |
| /* LDI_H */ |
| MSA128HOpnd, vsplat_simm10, |
| /* LDI_W */ |
| MSA128WOpnd, vsplat_simm10, |
| /* LDL */ |
| GPR64Opnd, -1, simm16, GPR64Opnd, |
| /* LDPC */ |
| GPR64Opnd, simm18_lsl3, |
| /* LDR */ |
| GPR64Opnd, -1, simm16, GPR64Opnd, |
| /* LDXC1 */ |
| AFGR64Opnd, -1, -1, |
| /* LDXC164 */ |
| FGR64Opnd, -1, -1, |
| /* LD_B */ |
| MSA128BOpnd, -1, simm10, |
| /* LD_D */ |
| MSA128DOpnd, -1, simm10_lsl3, |
| /* LD_H */ |
| MSA128HOpnd, -1, simm10_lsl1, |
| /* LD_W */ |
| MSA128WOpnd, -1, simm10_lsl2, |
| /* LEA_ADDiu */ |
| GPR32Opnd, -1, simm16, |
| /* LEA_ADDiu64 */ |
| GPR64Opnd, -1, simm16, |
| /* LEA_ADDiu_MM */ |
| GPR32Opnd, -1, simm16, |
| /* LH */ |
| GPR32Opnd, -1, simm16, |
| /* LH64 */ |
| GPR64Opnd, -1, simm16, |
| /* LHE */ |
| GPR32Opnd, -1, simm9, |
| /* LHE_MM */ |
| GPR32Opnd, -1, simm9, |
| /* LHU16_MM */ |
| GPRMM16Opnd, -1, simm4, |
| /* LHX */ |
| GPR32Opnd, -1, -1, |
| /* LHX_MM */ |
| GPR32Opnd, -1, -1, |
| /* LH_MM */ |
| GPR32Opnd, -1, simm16, |
| /* LHu */ |
| GPR32Opnd, -1, simm16, |
| /* LHu64 */ |
| GPR64Opnd, -1, simm16, |
| /* LHuE */ |
| GPR32Opnd, -1, simm9, |
| /* LHuE_MM */ |
| GPR32Opnd, -1, simm9, |
| /* LHu_MM */ |
| GPR32Opnd, -1, simm16, |
| /* LI16_MM */ |
| GPRMM16Opnd, li16_imm, |
| /* LI16_MMR6 */ |
| GPRMM16Opnd, li16_imm, |
| /* LL */ |
| GPR32Opnd, -1, simm16, |
| /* LL64 */ |
| GPR32Opnd, -1, simm16, |
| /* LL64_R6 */ |
| GPR32Opnd, -1, simm9, |
| /* LLD */ |
| GPR64Opnd, -1, simm16, |
| /* LLD_R6 */ |
| GPR64Opnd, -1, simm9, |
| /* LLE */ |
| GPR32Opnd, -1, simm9, |
| /* LLE_MM */ |
| GPR32Opnd, -1, simm9, |
| /* LL_MM */ |
| GPR32Opnd, -1, simm12, |
| /* LL_MMR6 */ |
| GPR32Opnd, -1, simm9, |
| /* LL_R6 */ |
| GPR32Opnd, -1, simm9, |
| /* LSA */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, uimm2_plus1, |
| /* LSA_MMR6 */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, uimm2_plus1, |
| /* LSA_R6 */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, uimm2_plus1, |
| /* LUI_MMR6 */ |
| GPR32Opnd, uimm16, |
| /* LUXC1 */ |
| AFGR64Opnd, -1, -1, |
| /* LUXC164 */ |
| FGR64Opnd, -1, -1, |
| /* LUXC1_MM */ |
| FGR64Opnd, -1, -1, |
| /* LUi */ |
| GPR32Opnd, uimm16_relaxed, |
| /* LUi64 */ |
| GPR64Opnd, uimm16_64_relaxed, |
| /* LUi_MM */ |
| GPR32Opnd, uimm16_relaxed, |
| /* LW */ |
| GPR32Opnd, -1, simm16, |
| /* LW16_MM */ |
| GPRMM16Opnd, -1, simm4, |
| /* LW64 */ |
| GPR64Opnd, -1, simm16, |
| /* LWC1 */ |
| FGR32Opnd, -1, simm16, |
| /* LWC1_MM */ |
| FGR32Opnd, -1, simm16, |
| /* LWC2 */ |
| COP2Opnd, -1, simm16, |
| /* LWC2_MMR6 */ |
| COP2Opnd, GPR32, simm11, |
| /* LWC2_R6 */ |
| COP2Opnd, -1, simm11, |
| /* LWC3 */ |
| COP3Opnd, -1, simm16, |
| /* LWDSP */ |
| DSPROpnd, -1, simm16, |
| /* LWDSP_MM */ |
| DSPROpnd, -1, simm16, |
| /* LWE */ |
| GPR32Opnd, -1, simm9, |
| /* LWE_MM */ |
| GPR32Opnd, -1, simm9, |
| /* LWGP_MM */ |
| GPRMM16Opnd, -1, simm7_lsl2, |
| /* LWL */ |
| GPR32Opnd, -1, simm16, GPR32Opnd, |
| /* LWL64 */ |
| GPR64Opnd, -1, simm16, GPR64Opnd, |
| /* LWLE */ |
| GPR32Opnd, -1, simm9, GPR32Opnd, |
| /* LWLE_MM */ |
| GPR32Opnd, -1, simm9, GPR32Opnd, |
| /* LWL_MM */ |
| GPR32Opnd, -1, simm12, GPR32Opnd, |
| /* LWM16_MM */ |
| reglist16, -1, uimm8, |
| /* LWM16_MMR6 */ |
| reglist16, -1, uimm8, |
| /* LWM32_MM */ |
| reglist, -1, simm12, |
| /* LWPC */ |
| GPR32Opnd, simm19_lsl2, |
| /* LWPC_MMR6 */ |
| GPR32Opnd, simm19_lsl2, |
| /* LWP_MM */ |
| GPR32Opnd, GPR32Opnd, -1, simm12, |
| /* LWR */ |
| GPR32Opnd, -1, simm16, GPR32Opnd, |
| /* LWR64 */ |
| GPR64Opnd, -1, simm16, GPR64Opnd, |
| /* LWRE */ |
| GPR32Opnd, -1, simm9, GPR32Opnd, |
| /* LWRE_MM */ |
| GPR32Opnd, -1, simm9, GPR32Opnd, |
| /* LWR_MM */ |
| GPR32Opnd, -1, simm12, GPR32Opnd, |
| /* LWSP_MM */ |
| GPR32Opnd, -1, simm5, |
| /* LWUPC */ |
| GPR32Opnd, simm19_lsl2, |
| /* LWU_MM */ |
| GPR32Opnd, -1, simm12, |
| /* LWX */ |
| GPR32Opnd, -1, -1, |
| /* LWXC1 */ |
| FGR32Opnd, -1, -1, |
| /* LWXC1_MM */ |
| FGR32Opnd, -1, -1, |
| /* LWXS_MM */ |
| GPR32Opnd, -1, -1, |
| /* LWX_MM */ |
| GPR32Opnd, -1, -1, |
| /* LW_MM */ |
| GPR32Opnd, -1, simm16, |
| /* LW_MMR6 */ |
| GPR32Opnd, -1, simm16, |
| /* LWu */ |
| GPR64Opnd, -1, simm16, |
| /* LbRxRyOffMemX16 */ |
| CPU16Regs, CPU16Regs, simm16, |
| /* LbuRxRyOffMemX16 */ |
| CPU16Regs, CPU16Regs, simm16, |
| /* LhRxRyOffMemX16 */ |
| CPU16Regs, CPU16Regs, simm16, |
| /* LhuRxRyOffMemX16 */ |
| CPU16Regs, CPU16Regs, simm16, |
| /* LiRxImm16 */ |
| CPU16Regs, simm16, |
| /* LiRxImmAlignX16 */ |
| CPU16Regs, simm16, |
| /* LiRxImmX16 */ |
| CPU16Regs, simm16, |
| /* LwRxPcTcp16 */ |
| CPU16Regs, pcrel16, i32imm, |
| /* LwRxPcTcpX16 */ |
| CPU16Regs, pcrel16, i32imm, |
| /* LwRxRyOffMemX16 */ |
| CPU16Regs, CPU16Regs, simm16, |
| /* LwRxSpImmX16 */ |
| CPU16Regs, CPU16RegsPlusSP, simm16, |
| /* MADD */ |
| GPR32Opnd, GPR32Opnd, |
| /* MADDF_D */ |
| FGR64Opnd, FGR64Opnd, FGR64Opnd, FGR64Opnd, |
| /* MADDF_D_MMR6 */ |
| FGR64Opnd, FGR64Opnd, FGR64Opnd, FGR64Opnd, |
| /* MADDF_S */ |
| FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd, |
| /* MADDF_S_MMR6 */ |
| FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd, |
| /* MADDR_Q_H */ |
| MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
| /* MADDR_Q_W */ |
| MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* MADDU */ |
| GPR32Opnd, GPR32Opnd, |
| /* MADDU_DSP */ |
| ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
| /* MADDU_DSP_MM */ |
| ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
| /* MADDU_MM */ |
| GPR32Opnd, GPR32Opnd, |
| /* MADDV_B */ |
| MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
| /* MADDV_D */ |
| MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
| /* MADDV_H */ |
| MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
| /* MADDV_W */ |
| MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* MADD_D32 */ |
| AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, |
| /* MADD_D32_MM */ |
| AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, |
| /* MADD_D64 */ |
| FGR64Opnd, FGR64Opnd, FGR64Opnd, FGR64Opnd, |
| /* MADD_DSP */ |
| ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
| /* MADD_DSP_MM */ |
| ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
| /* MADD_MM */ |
| GPR32Opnd, GPR32Opnd, |
| /* MADD_Q_H */ |
| MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
| /* MADD_Q_W */ |
| MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* MADD_S */ |
| FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd, |
| /* MADD_S_MM */ |
| FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd, |
| /* MAQ_SA_W_PHL */ |
| ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
| /* MAQ_SA_W_PHL_MM */ |
| ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
| /* MAQ_SA_W_PHR */ |
| ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
| /* MAQ_SA_W_PHR_MM */ |
| ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
| /* MAQ_S_W_PHL */ |
| ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
| /* MAQ_S_W_PHL_MM */ |
| ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
| /* MAQ_S_W_PHR */ |
| ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
| /* MAQ_S_W_PHR_MM */ |
| ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
| /* MAXA_D */ |
| FGR64Opnd, FGR64Opnd, FGR64Opnd, |
| /* MAXA_D_MMR6 */ |
| FGR64Opnd, FGR64Opnd, FGR64Opnd, |
| /* MAXA_S */ |
| FGR32Opnd, FGR32Opnd, FGR32Opnd, |
| /* MAXA_S_MMR6 */ |
| FGR32Opnd, FGR32Opnd, FGR32Opnd, |
| /* MAXI_S_B */ |
| MSA128BOpnd, MSA128BOpnd, vsplat_simm5, |
| /* MAXI_S_D */ |
| MSA128DOpnd, MSA128DOpnd, vsplat_simm5, |
| /* MAXI_S_H */ |
| MSA128HOpnd, MSA128HOpnd, vsplat_simm5, |
| /* MAXI_S_W */ |
| MSA128WOpnd, MSA128WOpnd, vsplat_simm5, |
| /* MAXI_U_B */ |
| MSA128BOpnd, MSA128BOpnd, vsplat_uimm5, |
| /* MAXI_U_D */ |
| MSA128DOpnd, MSA128DOpnd, vsplat_uimm5, |
| /* MAXI_U_H */ |
| MSA128HOpnd, MSA128HOpnd, vsplat_uimm5, |
| /* MAXI_U_W */ |
| MSA128WOpnd, MSA128WOpnd, vsplat_uimm5, |
| /* MAX_A_B */ |
| MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
| /* MAX_A_D */ |
| MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
| /* MAX_A_H */ |
| MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
| /* MAX_A_W */ |
| MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* MAX_D */ |
| FGR64Opnd, FGR64Opnd, FGR64Opnd, |
| /* MAX_D_MMR6 */ |
| FGR64Opnd, FGR64Opnd, FGR64Opnd, |
| /* MAX_S */ |
| FGR32Opnd, FGR32Opnd, FGR32Opnd, |
| /* MAX_S_B */ |
| MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
| /* MAX_S_D */ |
| MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
| /* MAX_S_H */ |
| MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
| /* MAX_S_MMR6 */ |
| FGR32Opnd, FGR32Opnd, FGR32Opnd, |
| /* MAX_S_W */ |
| MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* MAX_U_B */ |
| MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
| /* MAX_U_D */ |
| MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
| /* MAX_U_H */ |
| MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
| /* MAX_U_W */ |
| MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* MFC0 */ |
| GPR32Opnd, COP0Opnd, uimm3, |
| /* MFC0_MMR6 */ |
| GPR32Opnd, COP0Opnd, uimm3, |
| /* MFC1 */ |
| GPR32Opnd, FGR32Opnd, |
| /* MFC1_D64 */ |
| GPR32Opnd, FGR64Opnd, |
| /* MFC1_MM */ |
| GPR32Opnd, FGR32Opnd, |
| /* MFC1_MMR6 */ |
| GPR32Opnd, FGR32Opnd, |
| /* MFC2 */ |
| GPR32Opnd, COP2Opnd, uimm3, |
| /* MFC2_MMR6 */ |
| GPR32Opnd, COP2Opnd, |
| /* MFGC0 */ |
| GPR32Opnd, COP0Opnd, uimm3, |
| /* MFGC0_MM */ |
| GPR32Opnd, COP0Opnd, uimm3, |
| /* MFHC0_MMR6 */ |
| GPR32Opnd, COP0Opnd, uimm3, |
| /* MFHC1_D32 */ |
| GPR32Opnd, AFGR64Opnd, |
| /* MFHC1_D32_MM */ |
| GPR32Opnd, AFGR64Opnd, |
| /* MFHC1_D64 */ |
| GPR32Opnd, FGR64Opnd, |
| /* MFHC1_D64_MM */ |
| GPR32Opnd, FGR64Opnd, |
| /* MFHC2_MMR6 */ |
| GPR32Opnd, COP2Opnd, |
| /* MFHGC0 */ |
| GPR32Opnd, COP0Opnd, uimm3, |
| /* MFHGC0_MM */ |
| GPR32Opnd, COP0Opnd, uimm3, |
| /* MFHI */ |
| GPR32Opnd, |
| /* MFHI16_MM */ |
| GPR32Opnd, |
| /* MFHI64 */ |
| GPR64Opnd, |
| /* MFHI_DSP */ |
| GPR32Opnd, ACC64DSPOpnd, |
| /* MFHI_DSP_MM */ |
| GPR32Opnd, ACC64DSPOpnd, |
| /* MFHI_MM */ |
| GPR32Opnd, |
| /* MFLO */ |
| GPR32Opnd, |
| /* MFLO16_MM */ |
| GPR32Opnd, |
| /* MFLO64 */ |
| GPR64Opnd, |
| /* MFLO_DSP */ |
| GPR32Opnd, ACC64DSPOpnd, |
| /* MFLO_DSP_MM */ |
| GPR32Opnd, ACC64DSPOpnd, |
| /* MFLO_MM */ |
| GPR32Opnd, |
| /* MFTR */ |
| GPR32Opnd, GPR32Opnd, uimm1, uimm3, uimm1, |
| /* MINA_D */ |
| FGR64Opnd, FGR64Opnd, FGR64Opnd, |
| /* MINA_D_MMR6 */ |
| FGR64Opnd, FGR64Opnd, FGR64Opnd, |
| /* MINA_S */ |
| FGR32Opnd, FGR32Opnd, FGR32Opnd, |
| /* MINA_S_MMR6 */ |
| FGR32Opnd, FGR32Opnd, FGR32Opnd, |
| /* MINI_S_B */ |
| MSA128BOpnd, MSA128BOpnd, vsplat_simm5, |
| /* MINI_S_D */ |
| MSA128DOpnd, MSA128DOpnd, vsplat_simm5, |
| /* MINI_S_H */ |
| MSA128HOpnd, MSA128HOpnd, vsplat_simm5, |
| /* MINI_S_W */ |
| MSA128WOpnd, MSA128WOpnd, vsplat_simm5, |
| /* MINI_U_B */ |
| MSA128BOpnd, MSA128BOpnd, vsplat_uimm5, |
| /* MINI_U_D */ |
| MSA128DOpnd, MSA128DOpnd, vsplat_uimm5, |
| /* MINI_U_H */ |
| MSA128HOpnd, MSA128HOpnd, vsplat_uimm5, |
| /* MINI_U_W */ |
| MSA128WOpnd, MSA128WOpnd, vsplat_uimm5, |
| /* MIN_A_B */ |
| MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
| /* MIN_A_D */ |
| MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
| /* MIN_A_H */ |
| MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
| /* MIN_A_W */ |
| MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* MIN_D */ |
| FGR64Opnd, FGR64Opnd, FGR64Opnd, |
| /* MIN_D_MMR6 */ |
| FGR64Opnd, FGR64Opnd, FGR64Opnd, |
| /* MIN_S */ |
| FGR32Opnd, FGR32Opnd, FGR32Opnd, |
| /* MIN_S_B */ |
| MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
| /* MIN_S_D */ |
| MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
| /* MIN_S_H */ |
| MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
| /* MIN_S_MMR6 */ |
| FGR32Opnd, FGR32Opnd, FGR32Opnd, |
| /* MIN_S_W */ |
| MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* MIN_U_B */ |
| MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
| /* MIN_U_D */ |
| MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
| /* MIN_U_H */ |
| MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
| /* MIN_U_W */ |
| MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* MOD */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* MODSUB */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* MODSUB_MM */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* MODU */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* MODU_MMR6 */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* MOD_MMR6 */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* MOD_S_B */ |
| MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
| /* MOD_S_D */ |
| MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
| /* MOD_S_H */ |
| MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
| /* MOD_S_W */ |
| MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* MOD_U_B */ |
| MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
| /* MOD_U_D */ |
| MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
| /* MOD_U_H */ |
| MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
| /* MOD_U_W */ |
| MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* MOVE16_MM */ |
| GPR32Opnd, GPR32Opnd, |
| /* MOVE16_MMR6 */ |
| GPR32Opnd, GPR32Opnd, |
| /* MOVEP_MM */ |
| GPRMM16OpndMovePPairFirst, GPRMM16OpndMovePPairSecond, GPRMM16OpndMoveP, GPRMM16OpndMoveP, |
| /* MOVEP_MMR6 */ |
| GPRMM16OpndMovePPairFirst, GPRMM16OpndMovePPairSecond, GPRMM16OpndMoveP, GPRMM16OpndMoveP, |
| /* MOVE_V */ |
| MSA128BOpnd, MSA128BOpnd, |
| /* MOVF_D32 */ |
| AFGR64Opnd, AFGR64Opnd, FCCRegsOpnd, AFGR64Opnd, |
| /* MOVF_D32_MM */ |
| AFGR64Opnd, AFGR64Opnd, FCCRegsOpnd, AFGR64Opnd, |
| /* MOVF_D64 */ |
| FGR64Opnd, FGR64Opnd, FCCRegsOpnd, FGR64Opnd, |
| /* MOVF_I */ |
| GPR32Opnd, GPR32Opnd, FCCRegsOpnd, GPR32Opnd, |
| /* MOVF_I64 */ |
| GPR64Opnd, GPR64Opnd, FCCRegsOpnd, GPR64Opnd, |
| /* MOVF_I_MM */ |
| GPR32Opnd, GPR32Opnd, FCCRegsOpnd, GPR32Opnd, |
| /* MOVF_S */ |
| FGR32Opnd, FGR32Opnd, FCCRegsOpnd, FGR32Opnd, |
| /* MOVF_S_MM */ |
| FGR32Opnd, FGR32Opnd, FCCRegsOpnd, FGR32Opnd, |
| /* MOVN_I64_D64 */ |
| FGR64Opnd, FGR64Opnd, GPR64Opnd, FGR64Opnd, |
| /* MOVN_I64_I */ |
| GPR32Opnd, GPR32Opnd, GPR64Opnd, GPR32Opnd, |
| /* MOVN_I64_I64 */ |
| GPR64Opnd, GPR64Opnd, GPR64Opnd, GPR64Opnd, |
| /* MOVN_I64_S */ |
| FGR32Opnd, FGR32Opnd, GPR64Opnd, FGR32Opnd, |
| /* MOVN_I_D32 */ |
| AFGR64Opnd, AFGR64Opnd, GPR32Opnd, AFGR64Opnd, |
| /* MOVN_I_D32_MM */ |
| AFGR64Opnd, AFGR64Opnd, GPR32Opnd, AFGR64Opnd, |
| /* MOVN_I_D64 */ |
| FGR64Opnd, FGR64Opnd, GPR32Opnd, FGR64Opnd, |
| /* MOVN_I_I */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* MOVN_I_I64 */ |
| GPR64Opnd, GPR64Opnd, GPR32Opnd, GPR64Opnd, |
| /* MOVN_I_MM */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* MOVN_I_S */ |
| FGR32Opnd, FGR32Opnd, GPR32Opnd, FGR32Opnd, |
| /* MOVN_I_S_MM */ |
| FGR32Opnd, FGR32Opnd, GPR32Opnd, FGR32Opnd, |
| /* MOVT_D32 */ |
| AFGR64Opnd, AFGR64Opnd, FCCRegsOpnd, AFGR64Opnd, |
| /* MOVT_D32_MM */ |
| AFGR64Opnd, AFGR64Opnd, FCCRegsOpnd, AFGR64Opnd, |
| /* MOVT_D64 */ |
| FGR64Opnd, FGR64Opnd, FCCRegsOpnd, FGR64Opnd, |
| /* MOVT_I */ |
| GPR32Opnd, GPR32Opnd, FCCRegsOpnd, GPR32Opnd, |
| /* MOVT_I64 */ |
| GPR64Opnd, GPR64Opnd, FCCRegsOpnd, GPR64Opnd, |
| /* MOVT_I_MM */ |
| GPR32Opnd, GPR32Opnd, FCCRegsOpnd, GPR32Opnd, |
| /* MOVT_S */ |
| FGR32Opnd, FGR32Opnd, FCCRegsOpnd, FGR32Opnd, |
| /* MOVT_S_MM */ |
| FGR32Opnd, FGR32Opnd, FCCRegsOpnd, FGR32Opnd, |
| /* MOVZ_I64_D64 */ |
| FGR64Opnd, FGR64Opnd, GPR64Opnd, FGR64Opnd, |
| /* MOVZ_I64_I */ |
| GPR32Opnd, GPR32Opnd, GPR64Opnd, GPR32Opnd, |
| /* MOVZ_I64_I64 */ |
| GPR64Opnd, GPR64Opnd, GPR64Opnd, GPR64Opnd, |
| /* MOVZ_I64_S */ |
| FGR32Opnd, FGR32Opnd, GPR64Opnd, FGR32Opnd, |
| /* MOVZ_I_D32 */ |
| AFGR64Opnd, AFGR64Opnd, GPR32Opnd, AFGR64Opnd, |
| /* MOVZ_I_D32_MM */ |
| AFGR64Opnd, AFGR64Opnd, GPR32Opnd, AFGR64Opnd, |
| /* MOVZ_I_D64 */ |
| FGR64Opnd, FGR64Opnd, GPR32Opnd, FGR64Opnd, |
| /* MOVZ_I_I */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* MOVZ_I_I64 */ |
| GPR64Opnd, GPR64Opnd, GPR32Opnd, GPR64Opnd, |
| /* MOVZ_I_MM */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* MOVZ_I_S */ |
| FGR32Opnd, FGR32Opnd, GPR32Opnd, FGR32Opnd, |
| /* MOVZ_I_S_MM */ |
| FGR32Opnd, FGR32Opnd, GPR32Opnd, FGR32Opnd, |
| /* MSUB */ |
| GPR32Opnd, GPR32Opnd, |
| /* MSUBF_D */ |
| FGR64Opnd, FGR64Opnd, FGR64Opnd, FGR64Opnd, |
| /* MSUBF_D_MMR6 */ |
| FGR64Opnd, FGR64Opnd, FGR64Opnd, FGR64Opnd, |
| /* MSUBF_S */ |
| FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd, |
| /* MSUBF_S_MMR6 */ |
| FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd, |
| /* MSUBR_Q_H */ |
| MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
| /* MSUBR_Q_W */ |
| MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* MSUBU */ |
| GPR32Opnd, GPR32Opnd, |
| /* MSUBU_DSP */ |
| ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
| /* MSUBU_DSP_MM */ |
| ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
| /* MSUBU_MM */ |
| GPR32Opnd, GPR32Opnd, |
| /* MSUBV_B */ |
| MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
| /* MSUBV_D */ |
| MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
| /* MSUBV_H */ |
| MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
| /* MSUBV_W */ |
| MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* MSUB_D32 */ |
| AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, |
| /* MSUB_D32_MM */ |
| AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, |
| /* MSUB_D64 */ |
| FGR64Opnd, FGR64Opnd, FGR64Opnd, FGR64Opnd, |
| /* MSUB_DSP */ |
| ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
| /* MSUB_DSP_MM */ |
| ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
| /* MSUB_MM */ |
| GPR32Opnd, GPR32Opnd, |
| /* MSUB_Q_H */ |
| MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
| /* MSUB_Q_W */ |
| MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* MSUB_S */ |
| FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd, |
| /* MSUB_S_MM */ |
| FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd, |
| /* MTC0 */ |
| COP0Opnd, GPR32Opnd, uimm3, |
| /* MTC0_MMR6 */ |
| COP0Opnd, GPR32Opnd, uimm3, |
| /* MTC1 */ |
| FGR32Opnd, GPR32Opnd, |
| /* MTC1_D64 */ |
| FGR64Opnd, GPR32Opnd, |
| /* MTC1_D64_MM */ |
| FGR64Opnd, GPR32Opnd, |
| /* MTC1_MM */ |
| FGR32Opnd, GPR32Opnd, |
| /* MTC1_MMR6 */ |
| FGR32Opnd, GPR32Opnd, |
| /* MTC2 */ |
| COP2Opnd, GPR32Opnd, uimm3, |
| /* MTC2_MMR6 */ |
| COP2Opnd, GPR32Opnd, |
| /* MTGC0 */ |
| COP0Opnd, GPR32Opnd, uimm3, |
| /* MTGC0_MM */ |
| COP0Opnd, GPR32Opnd, uimm3, |
| /* MTHC0_MMR6 */ |
| COP0Opnd, GPR32Opnd, uimm3, |
| /* MTHC1_D32 */ |
| AFGR64Opnd, AFGR64Opnd, GPR32Opnd, |
| /* MTHC1_D32_MM */ |
| AFGR64Opnd, AFGR64Opnd, GPR32Opnd, |
| /* MTHC1_D64 */ |
| FGR64Opnd, FGR64Opnd, GPR32Opnd, |
| /* MTHC1_D64_MM */ |
| FGR64Opnd, FGR64Opnd, GPR32Opnd, |
| /* MTHC2_MMR6 */ |
| COP2Opnd, GPR32Opnd, |
| /* MTHGC0 */ |
| COP0Opnd, GPR32Opnd, uimm3, |
| /* MTHGC0_MM */ |
| COP0Opnd, GPR32Opnd, uimm3, |
| /* MTHI */ |
| GPR32Opnd, |
| /* MTHI64 */ |
| GPR64Opnd, |
| /* MTHI_DSP */ |
| HI32DSPOpnd, GPR32Opnd, |
| /* MTHI_DSP_MM */ |
| HI32DSPOpnd, GPR32Opnd, |
| /* MTHI_MM */ |
| GPR32Opnd, |
| /* MTHLIP */ |
| ACC64DSPOpnd, GPR32Opnd, ACC64DSPOpnd, |
| /* MTHLIP_MM */ |
| ACC64DSPOpnd, GPR32Opnd, ACC64DSPOpnd, |
| /* MTLO */ |
| GPR32Opnd, |
| /* MTLO64 */ |
| GPR64Opnd, |
| /* MTLO_DSP */ |
| LO32DSPOpnd, GPR32Opnd, |
| /* MTLO_DSP_MM */ |
| LO32DSPOpnd, GPR32Opnd, |
| /* MTLO_MM */ |
| GPR32Opnd, |
| /* MTM0 */ |
| GPR64Opnd, |
| /* MTM1 */ |
| GPR64Opnd, |
| /* MTM2 */ |
| GPR64Opnd, |
| /* MTP0 */ |
| GPR64Opnd, |
| /* MTP1 */ |
| GPR64Opnd, |
| /* MTP2 */ |
| GPR64Opnd, |
| /* MTTR */ |
| GPR32Opnd, GPR32Opnd, uimm1, uimm3, uimm1, |
| /* MUH */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* MUHU */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* MUHU_MMR6 */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* MUH_MMR6 */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* MUL */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* MULEQ_S_W_PHL */ |
| GPR32Opnd, DSPROpnd, DSPROpnd, |
| /* MULEQ_S_W_PHL_MM */ |
| GPR32Opnd, DSPROpnd, DSPROpnd, |
| /* MULEQ_S_W_PHR */ |
| GPR32Opnd, DSPROpnd, DSPROpnd, |
| /* MULEQ_S_W_PHR_MM */ |
| GPR32Opnd, DSPROpnd, DSPROpnd, |
| /* MULEU_S_PH_QBL */ |
| DSPROpnd, DSPROpnd, DSPROpnd, |
| /* MULEU_S_PH_QBL_MM */ |
| DSPROpnd, DSPROpnd, DSPROpnd, |
| /* MULEU_S_PH_QBR */ |
| DSPROpnd, DSPROpnd, DSPROpnd, |
| /* MULEU_S_PH_QBR_MM */ |
| DSPROpnd, DSPROpnd, DSPROpnd, |
| /* MULQ_RS_PH */ |
| DSPROpnd, DSPROpnd, DSPROpnd, |
| /* MULQ_RS_PH_MM */ |
| DSPROpnd, DSPROpnd, DSPROpnd, |
| /* MULQ_RS_W */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* MULQ_RS_W_MMR2 */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* MULQ_S_PH */ |
| DSPROpnd, DSPROpnd, DSPROpnd, |
| /* MULQ_S_PH_MMR2 */ |
| DSPROpnd, DSPROpnd, DSPROpnd, |
| /* MULQ_S_W */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* MULQ_S_W_MMR2 */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* MULR_PS64 */ |
| FGR64Opnd, FGR64Opnd, FGR64Opnd, |
| /* MULR_Q_H */ |
| MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
| /* MULR_Q_W */ |
| MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* MULSAQ_S_W_PH */ |
| ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
| /* MULSAQ_S_W_PH_MM */ |
| ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
| /* MULSA_W_PH */ |
| ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
| /* MULSA_W_PH_MMR2 */ |
| ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
| /* MULT */ |
| GPR32Opnd, GPR32Opnd, |
| /* MULTU_DSP */ |
| ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, |
| /* MULTU_DSP_MM */ |
| ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, |
| /* MULT_DSP */ |
| ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, |
| /* MULT_DSP_MM */ |
| ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, |
| /* MULT_MM */ |
| GPR32Opnd, GPR32Opnd, |
| /* MULTu */ |
| GPR32Opnd, GPR32Opnd, |
| /* MULTu_MM */ |
| GPR32Opnd, GPR32Opnd, |
| /* MULU */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* MULU_MMR6 */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* MULV_B */ |
| MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
| /* MULV_D */ |
| MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
| /* MULV_H */ |
| MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
| /* MULV_W */ |
| MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* MUL_MM */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* MUL_MMR6 */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* MUL_PH */ |
| DSPROpnd, DSPROpnd, DSPROpnd, |
| /* MUL_PH_MMR2 */ |
| DSPROpnd, DSPROpnd, DSPROpnd, |
| /* MUL_Q_H */ |
| MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
| /* MUL_Q_W */ |
| MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* MUL_R6 */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* MUL_S_PH */ |
| DSPROpnd, DSPROpnd, DSPROpnd, |
| /* MUL_S_PH_MMR2 */ |
| DSPROpnd, DSPROpnd, DSPROpnd, |
| /* Mfhi16 */ |
| CPU16Regs, |
| /* Mflo16 */ |
| CPU16Regs, |
| /* Move32R16 */ |
| GPR32, CPU16Regs, |
| /* MoveR3216 */ |
| CPU16Regs, GPR32, |
| /* NLOC_B */ |
| MSA128BOpnd, MSA128BOpnd, |
| /* NLOC_D */ |
| MSA128DOpnd, MSA128DOpnd, |
| /* NLOC_H */ |
| MSA128HOpnd, MSA128HOpnd, |
| /* NLOC_W */ |
| MSA128WOpnd, MSA128WOpnd, |
| /* NLZC_B */ |
| MSA128BOpnd, MSA128BOpnd, |
| /* NLZC_D */ |
| MSA128DOpnd, MSA128DOpnd, |
| /* NLZC_H */ |
| MSA128HOpnd, MSA128HOpnd, |
| /* NLZC_W */ |
| MSA128WOpnd, MSA128WOpnd, |
| /* NMADD_D32 */ |
| AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, |
| /* NMADD_D32_MM */ |
| AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, |
| /* NMADD_D64 */ |
| FGR64Opnd, FGR64Opnd, FGR64Opnd, FGR64Opnd, |
| /* NMADD_S */ |
| FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd, |
| /* NMADD_S_MM */ |
| FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd, |
| /* NMSUB_D32 */ |
| AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, |
| /* NMSUB_D32_MM */ |
| AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, |
| /* NMSUB_D64 */ |
| FGR64Opnd, FGR64Opnd, FGR64Opnd, FGR64Opnd, |
| /* NMSUB_S */ |
| FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd, |
| /* NMSUB_S_MM */ |
| FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd, |
| /* NOR */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* NOR64 */ |
| GPR64Opnd, GPR64Opnd, GPR64Opnd, |
| /* NORI_B */ |
| MSA128BOpnd, MSA128BOpnd, vsplat_uimm8, |
| /* NOR_MM */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* NOR_MMR6 */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* NOR_V */ |
| MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
| /* NOT16_MM */ |
| GPRMM16Opnd, GPRMM16Opnd, |
| /* NOT16_MMR6 */ |
| GPRMM16Opnd, GPRMM16Opnd, |
| /* NegRxRy16 */ |
| CPU16Regs, CPU16Regs, |
| /* NotRxRy16 */ |
| CPU16Regs, CPU16Regs, |
| /* OR */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* OR16_MM */ |
| GPRMM16Opnd, GPRMM16Opnd, GPRMM16Opnd, |
| /* OR16_MMR6 */ |
| GPRMM16Opnd, GPRMM16Opnd, GPRMM16Opnd, |
| /* OR64 */ |
| GPR64Opnd, GPR64Opnd, GPR64Opnd, |
| /* ORI_B */ |
| MSA128BOpnd, MSA128BOpnd, vsplat_uimm8, |
| /* ORI_MMR6 */ |
| GPR32Opnd, GPR32Opnd, uimm16, |
| /* OR_MM */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* OR_MMR6 */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* OR_V */ |
| MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
| /* ORi */ |
| GPR32Opnd, GPR32Opnd, uimm16, |
| /* ORi64 */ |
| GPR64Opnd, GPR64Opnd, uimm16_64, |
| /* ORi_MM */ |
| GPR32Opnd, GPR32Opnd, uimm16, |
| /* OrRxRxRy16 */ |
| CPU16Regs, CPU16Regs, CPU16Regs, |
| /* PACKRL_PH */ |
| DSPROpnd, DSPROpnd, DSPROpnd, |
| /* PACKRL_PH_MM */ |
| DSPROpnd, DSPROpnd, DSPROpnd, |
| /* PAUSE */ |
| /* PAUSE_MM */ |
| /* PAUSE_MMR6 */ |
| /* PCKEV_B */ |
| MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
| /* PCKEV_D */ |
| MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
| /* PCKEV_H */ |
| MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
| /* PCKEV_W */ |
| MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* PCKOD_B */ |
| MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
| /* PCKOD_D */ |
| MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
| /* PCKOD_H */ |
| MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
| /* PCKOD_W */ |
| MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* PCNT_B */ |
| MSA128BOpnd, MSA128BOpnd, |
| /* PCNT_D */ |
| MSA128DOpnd, MSA128DOpnd, |
| /* PCNT_H */ |
| MSA128HOpnd, MSA128HOpnd, |
| /* PCNT_W */ |
| MSA128WOpnd, MSA128WOpnd, |
| /* PICK_PH */ |
| DSPROpnd, DSPROpnd, DSPROpnd, |
| /* PICK_PH_MM */ |
| DSPROpnd, DSPROpnd, DSPROpnd, |
| /* PICK_QB */ |
| DSPROpnd, DSPROpnd, DSPROpnd, |
| /* PICK_QB_MM */ |
| DSPROpnd, DSPROpnd, DSPROpnd, |
| /* PLL_PS64 */ |
| FGR64Opnd, FGR64Opnd, FGR64Opnd, |
| /* PLU_PS64 */ |
| FGR64Opnd, FGR64Opnd, FGR64Opnd, |
| /* POP */ |
| GPR32Opnd, GPR32Opnd, |
| /* PRECEQU_PH_QBL */ |
| DSPROpnd, DSPROpnd, |
| /* PRECEQU_PH_QBLA */ |
| DSPROpnd, DSPROpnd, |
| /* PRECEQU_PH_QBLA_MM */ |
| DSPROpnd, DSPROpnd, |
| /* PRECEQU_PH_QBL_MM */ |
| DSPROpnd, DSPROpnd, |
| /* PRECEQU_PH_QBR */ |
| DSPROpnd, DSPROpnd, |
| /* PRECEQU_PH_QBRA */ |
| DSPROpnd, DSPROpnd, |
| /* PRECEQU_PH_QBRA_MM */ |
| DSPROpnd, DSPROpnd, |
| /* PRECEQU_PH_QBR_MM */ |
| DSPROpnd, DSPROpnd, |
| /* PRECEQ_W_PHL */ |
| GPR32Opnd, DSPROpnd, |
| /* PRECEQ_W_PHL_MM */ |
| GPR32Opnd, DSPROpnd, |
| /* PRECEQ_W_PHR */ |
| GPR32Opnd, DSPROpnd, |
| /* PRECEQ_W_PHR_MM */ |
| GPR32Opnd, DSPROpnd, |
| /* PRECEU_PH_QBL */ |
| DSPROpnd, DSPROpnd, |
| /* PRECEU_PH_QBLA */ |
| DSPROpnd, DSPROpnd, |
| /* PRECEU_PH_QBLA_MM */ |
| DSPROpnd, DSPROpnd, |
| /* PRECEU_PH_QBL_MM */ |
| DSPROpnd, DSPROpnd, |
| /* PRECEU_PH_QBR */ |
| DSPROpnd, DSPROpnd, |
| /* PRECEU_PH_QBRA */ |
| DSPROpnd, DSPROpnd, |
| /* PRECEU_PH_QBRA_MM */ |
| DSPROpnd, DSPROpnd, |
| /* PRECEU_PH_QBR_MM */ |
| DSPROpnd, DSPROpnd, |
| /* PRECRQU_S_QB_PH */ |
| DSPROpnd, DSPROpnd, DSPROpnd, |
| /* PRECRQU_S_QB_PH_MM */ |
| DSPROpnd, DSPROpnd, DSPROpnd, |
| /* PRECRQ_PH_W */ |
| DSPROpnd, GPR32Opnd, GPR32Opnd, |
| /* PRECRQ_PH_W_MM */ |
| DSPROpnd, GPR32Opnd, GPR32Opnd, |
| /* PRECRQ_QB_PH */ |
| DSPROpnd, DSPROpnd, DSPROpnd, |
| /* PRECRQ_QB_PH_MM */ |
| DSPROpnd, DSPROpnd, DSPROpnd, |
| /* PRECRQ_RS_PH_W */ |
| DSPROpnd, GPR32Opnd, GPR32Opnd, |
| /* PRECRQ_RS_PH_W_MM */ |
| DSPROpnd, GPR32Opnd, GPR32Opnd, |
| /* PRECR_QB_PH */ |
| DSPROpnd, DSPROpnd, DSPROpnd, |
| /* PRECR_QB_PH_MMR2 */ |
| DSPROpnd, DSPROpnd, DSPROpnd, |
| /* PRECR_SRA_PH_W */ |
| DSPROpnd, GPR32Opnd, uimm5, GPR32Opnd, |
| /* PRECR_SRA_PH_W_MMR2 */ |
| DSPROpnd, GPR32Opnd, uimm5, GPR32Opnd, |
| /* PRECR_SRA_R_PH_W */ |
| DSPROpnd, GPR32Opnd, uimm5, GPR32Opnd, |
| /* PRECR_SRA_R_PH_W_MMR2 */ |
| DSPROpnd, GPR32Opnd, uimm5, GPR32Opnd, |
| /* PREF */ |
| -1, simm16, uimm5, |
| /* PREFE */ |
| -1, simm9, uimm5, |
| /* PREFE_MM */ |
| -1, simm9, uimm5, |
| /* PREFX_MM */ |
| -1, -1, uimm5, |
| /* PREF_MM */ |
| -1, simm12, uimm5, |
| /* PREF_MMR6 */ |
| -1, simm12, uimm5, |
| /* PREF_R6 */ |
| -1, simm9, uimm5, |
| /* PREPEND */ |
| GPR32Opnd, GPR32Opnd, uimm5, GPR32Opnd, |
| /* PREPEND_MMR2 */ |
| GPR32Opnd, GPR32Opnd, uimm5, GPR32Opnd, |
| /* PUL_PS64 */ |
| FGR64Opnd, FGR64Opnd, FGR64Opnd, |
| /* PUU_PS64 */ |
| FGR64Opnd, FGR64Opnd, FGR64Opnd, |
| /* RADDU_W_QB */ |
| GPR32Opnd, DSPROpnd, |
| /* RADDU_W_QB_MM */ |
| GPR32Opnd, DSPROpnd, |
| /* RDDSP */ |
| GPR32Opnd, uimm10, |
| /* RDDSP_MM */ |
| GPR32Opnd, uimm7, |
| /* RDHWR */ |
| GPR32Opnd, HWRegsOpnd, uimm8, |
| /* RDHWR64 */ |
| GPR64Opnd, HWRegsOpnd, uimm8, |
| /* RDHWR_MM */ |
| GPR32Opnd, HWRegsOpnd, uimm8, |
| /* RDHWR_MMR6 */ |
| GPR32Opnd, HWRegsOpnd, uimm3, |
| /* RDPGPR_MMR6 */ |
| GPR32Opnd, GPR32Opnd, |
| /* RECIP_D32 */ |
| AFGR64Opnd, AFGR64Opnd, |
| /* RECIP_D32_MM */ |
| AFGR64Opnd, AFGR64Opnd, |
| /* RECIP_D64 */ |
| FGR64Opnd, FGR64Opnd, |
| /* RECIP_D64_MM */ |
| FGR64Opnd, FGR64Opnd, |
| /* RECIP_S */ |
| FGR32Opnd, FGR32Opnd, |
| /* RECIP_S_MM */ |
| FGR32Opnd, FGR32Opnd, |
| /* REPLV_PH */ |
| DSPROpnd, GPR32Opnd, |
| /* REPLV_PH_MM */ |
| DSPROpnd, GPR32Opnd, |
| /* REPLV_QB */ |
| DSPROpnd, GPR32Opnd, |
| /* REPLV_QB_MM */ |
| DSPROpnd, GPR32Opnd, |
| /* REPL_PH */ |
| DSPROpnd, simm10, |
| /* REPL_PH_MM */ |
| DSPROpnd, simm10, |
| /* REPL_QB */ |
| DSPROpnd, uimm8, |
| /* REPL_QB_MM */ |
| DSPROpnd, uimm8, |
| /* RINT_D */ |
| FGR64Opnd, FGR64Opnd, |
| /* RINT_D_MMR6 */ |
| FGR64Opnd, FGR64Opnd, |
| /* RINT_S */ |
| FGR32Opnd, FGR32Opnd, |
| /* RINT_S_MMR6 */ |
| FGR32Opnd, FGR32Opnd, |
| /* ROTR */ |
| GPR32Opnd, GPR32Opnd, uimm5, |
| /* ROTRV */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* ROTRV_MM */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* ROTR_MM */ |
| GPR32Opnd, GPR32Opnd, uimm5, |
| /* ROUND_L_D64 */ |
| FGR64Opnd, FGR64Opnd, |
| /* ROUND_L_D_MMR6 */ |
| FGR64Opnd, FGR64Opnd, |
| /* ROUND_L_S */ |
| FGR64Opnd, FGR32Opnd, |
| /* ROUND_L_S_MMR6 */ |
| FGR64Opnd, FGR32Opnd, |
| /* ROUND_W_D32 */ |
| FGR32Opnd, AFGR64Opnd, |
| /* ROUND_W_D64 */ |
| FGR32Opnd, FGR64Opnd, |
| /* ROUND_W_D_MMR6 */ |
| FGR64Opnd, FGR64Opnd, |
| /* ROUND_W_MM */ |
| FGR32Opnd, AFGR64Opnd, |
| /* ROUND_W_S */ |
| FGR32Opnd, FGR32Opnd, |
| /* ROUND_W_S_MM */ |
| FGR32Opnd, FGR32Opnd, |
| /* ROUND_W_S_MMR6 */ |
| FGR32Opnd, FGR32Opnd, |
| /* RSQRT_D32 */ |
| AFGR64Opnd, AFGR64Opnd, |
| /* RSQRT_D32_MM */ |
| AFGR64Opnd, AFGR64Opnd, |
| /* RSQRT_D64 */ |
| FGR64Opnd, FGR64Opnd, |
| /* RSQRT_D64_MM */ |
| FGR64Opnd, FGR64Opnd, |
| /* RSQRT_S */ |
| FGR32Opnd, FGR32Opnd, |
| /* RSQRT_S_MM */ |
| FGR32Opnd, FGR32Opnd, |
| /* Restore16 */ |
| /* RestoreX16 */ |
| /* SAA */ |
| GPR64Opnd, GPR64Opnd, |
| /* SAAD */ |
| GPR64Opnd, GPR64Opnd, |
| /* SAT_S_B */ |
| MSA128BOpnd, MSA128BOpnd, uimm3, |
| /* SAT_S_D */ |
| MSA128DOpnd, MSA128DOpnd, uimm6, |
| /* SAT_S_H */ |
| MSA128HOpnd, MSA128HOpnd, uimm4, |
| /* SAT_S_W */ |
| MSA128WOpnd, MSA128WOpnd, uimm5, |
| /* SAT_U_B */ |
| MSA128BOpnd, MSA128BOpnd, uimm3, |
| /* SAT_U_D */ |
| MSA128DOpnd, MSA128DOpnd, uimm6, |
| /* SAT_U_H */ |
| MSA128HOpnd, MSA128HOpnd, uimm4, |
| /* SAT_U_W */ |
| MSA128WOpnd, MSA128WOpnd, uimm5, |
| /* SB */ |
| GPR32Opnd, -1, simm16, |
| /* SB16_MM */ |
| GPRMM16OpndZero, -1, simm4, |
| /* SB16_MMR6 */ |
| GPRMM16OpndZero, -1, simm4, |
| /* SB64 */ |
| GPR64Opnd, -1, simm16, |
| /* SBE */ |
| GPR32Opnd, -1, simm9, |
| /* SBE_MM */ |
| GPR32Opnd, -1, simm9, |
| /* SB_MM */ |
| GPR32Opnd, -1, simm16, |
| /* SB_MMR6 */ |
| GPR32Opnd, -1, simm16, |
| /* SC */ |
| GPR32Opnd, GPR32Opnd, -1, simm16, |
| /* SC64 */ |
| GPR32Opnd, GPR32Opnd, -1, simm16, |
| /* SC64_R6 */ |
| GPR32Opnd, GPR32Opnd, -1, simm9, |
| /* SCD */ |
| GPR64Opnd, GPR64Opnd, -1, simm16, |
| /* SCD_R6 */ |
| GPR64Opnd, GPR64Opnd, -1, simm9, |
| /* SCE */ |
| GPR32Opnd, GPR32Opnd, -1, simm9, |
| /* SCE_MM */ |
| GPR32Opnd, GPR32Opnd, -1, simm9, |
| /* SC_MM */ |
| GPR32Opnd, GPR32Opnd, -1, simm12, |
| /* SC_MMR6 */ |
| GPR32Opnd, GPR32Opnd, -1, simm9, |
| /* SC_R6 */ |
| GPR32Opnd, GPR32Opnd, -1, simm9, |
| /* SD */ |
| GPR64Opnd, -1, simm16, |
| /* SDBBP */ |
| uimm20, |
| /* SDBBP16_MM */ |
| uimm4, |
| /* SDBBP16_MMR6 */ |
| uimm4, |
| /* SDBBP_MM */ |
| uimm10, |
| /* SDBBP_MMR6 */ |
| uimm20, |
| /* SDBBP_R6 */ |
| uimm20, |
| /* SDC1 */ |
| AFGR64Opnd, -1, simm16, |
| /* SDC164 */ |
| FGR64Opnd, -1, simm16, |
| /* SDC1_D64_MMR6 */ |
| FGR64Opnd, -1, simm16, |
| /* SDC1_MM_D32 */ |
| AFGR64Opnd, -1, simm16, |
| /* SDC1_MM_D64 */ |
| FGR64Opnd, -1, simm16, |
| /* SDC2 */ |
| COP2Opnd, -1, simm16, |
| /* SDC2_MMR6 */ |
| COP2Opnd, GPR32, simm11, |
| /* SDC2_R6 */ |
| COP2Opnd, -1, simm11, |
| /* SDC3 */ |
| COP3Opnd, -1, simm16, |
| /* SDIV */ |
| GPR32Opnd, GPR32Opnd, |
| /* SDIV_MM */ |
| GPR32Opnd, GPR32Opnd, |
| /* SDL */ |
| GPR64Opnd, -1, simm16, |
| /* SDR */ |
| GPR64Opnd, -1, simm16, |
| /* SDXC1 */ |
| AFGR64Opnd, -1, -1, |
| /* SDXC164 */ |
| FGR64Opnd, -1, -1, |
| /* SEB */ |
| GPR32Opnd, GPR32Opnd, |
| /* SEB64 */ |
| GPR64Opnd, GPR64Opnd, |
| /* SEB_MM */ |
| GPR32Opnd, GPR32Opnd, |
| /* SEH */ |
| GPR32Opnd, GPR32Opnd, |
| /* SEH64 */ |
| GPR64Opnd, GPR64Opnd, |
| /* SEH_MM */ |
| GPR32Opnd, GPR32Opnd, |
| /* SELEQZ */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* SELEQZ64 */ |
| GPR64Opnd, GPR64Opnd, GPR64Opnd, |
| /* SELEQZ_D */ |
| FGR64Opnd, FGR64Opnd, FGR64Opnd, |
| /* SELEQZ_D_MMR6 */ |
| FGR64Opnd, FGR64Opnd, FGR64Opnd, |
| /* SELEQZ_MMR6 */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* SELEQZ_S */ |
| FGR32Opnd, FGR32Opnd, FGR32Opnd, |
| /* SELEQZ_S_MMR6 */ |
| FGR32Opnd, FGR32Opnd, FGR32Opnd, |
| /* SELNEZ */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* SELNEZ64 */ |
| GPR64Opnd, GPR64Opnd, GPR64Opnd, |
| /* SELNEZ_D */ |
| FGR64Opnd, FGR64Opnd, FGR64Opnd, |
| /* SELNEZ_D_MMR6 */ |
| FGR64Opnd, FGR64Opnd, FGR64Opnd, |
| /* SELNEZ_MMR6 */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* SELNEZ_S */ |
| FGR32Opnd, FGR32Opnd, FGR32Opnd, |
| /* SELNEZ_S_MMR6 */ |
| FGR32Opnd, FGR32Opnd, FGR32Opnd, |
| /* SEL_D */ |
| FGR64Opnd, FGR64Opnd, FGR64Opnd, FGR64Opnd, |
| /* SEL_D_MMR6 */ |
| FGR64Opnd, FGR64Opnd, FGR64Opnd, FGR64Opnd, |
| /* SEL_S */ |
| FGR32Opnd, FGRCCOpnd, FGR32Opnd, FGR32Opnd, |
| /* SEL_S_MMR6 */ |
| FGR32Opnd, FGRCCOpnd, FGR32Opnd, FGR32Opnd, |
| /* SEQ */ |
| GPR64Opnd, GPR64Opnd, GPR64Opnd, |
| /* SEQi */ |
| GPR64Opnd, GPR64Opnd, simm10_64, |
| /* SH */ |
| GPR32Opnd, -1, simm16, |
| /* SH16_MM */ |
| GPRMM16OpndZero, -1, simm4, |
| /* SH16_MMR6 */ |
| GPRMM16OpndZero, -1, simm4, |
| /* SH64 */ |
| GPR64Opnd, -1, simm16, |
| /* SHE */ |
| GPR32Opnd, -1, simm9, |
| /* SHE_MM */ |
| GPR32Opnd, -1, simm9, |
| /* SHF_B */ |
| MSA128BOpnd, MSA128BOpnd, uimm8, |
| /* SHF_H */ |
| MSA128HOpnd, MSA128HOpnd, uimm8, |
| /* SHF_W */ |
| MSA128WOpnd, MSA128WOpnd, uimm8, |
| /* SHILO */ |
| ACC64DSPOpnd, simm6, ACC64DSPOpnd, |
| /* SHILOV */ |
| ACC64DSPOpnd, GPR32Opnd, ACC64DSPOpnd, |
| /* SHILOV_MM */ |
| ACC64DSPOpnd, GPR32Opnd, ACC64DSPOpnd, |
| /* SHILO_MM */ |
| ACC64DSPOpnd, simm6, ACC64DSPOpnd, |
| /* SHLLV_PH */ |
| DSPROpnd, DSPROpnd, GPR32Opnd, |
| /* SHLLV_PH_MM */ |
| DSPROpnd, DSPROpnd, GPR32Opnd, |
| /* SHLLV_QB */ |
| DSPROpnd, DSPROpnd, GPR32Opnd, |
| /* SHLLV_QB_MM */ |
| DSPROpnd, DSPROpnd, GPR32Opnd, |
| /* SHLLV_S_PH */ |
| DSPROpnd, DSPROpnd, GPR32Opnd, |
| /* SHLLV_S_PH_MM */ |
| DSPROpnd, DSPROpnd, GPR32Opnd, |
| /* SHLLV_S_W */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* SHLLV_S_W_MM */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* SHLL_PH */ |
| DSPROpnd, DSPROpnd, uimm4, |
| /* SHLL_PH_MM */ |
| DSPROpnd, DSPROpnd, uimm4, |
| /* SHLL_QB */ |
| DSPROpnd, DSPROpnd, uimm3, |
| /* SHLL_QB_MM */ |
| DSPROpnd, DSPROpnd, uimm3, |
| /* SHLL_S_PH */ |
| DSPROpnd, DSPROpnd, uimm4, |
| /* SHLL_S_PH_MM */ |
| DSPROpnd, DSPROpnd, uimm4, |
| /* SHLL_S_W */ |
| GPR32Opnd, GPR32Opnd, uimm5, |
| /* SHLL_S_W_MM */ |
| GPR32Opnd, GPR32Opnd, uimm5, |
| /* SHRAV_PH */ |
| DSPROpnd, DSPROpnd, GPR32Opnd, |
| /* SHRAV_PH_MM */ |
| DSPROpnd, DSPROpnd, GPR32Opnd, |
| /* SHRAV_QB */ |
| DSPROpnd, DSPROpnd, GPR32Opnd, |
| /* SHRAV_QB_MMR2 */ |
| DSPROpnd, DSPROpnd, GPR32Opnd, |
| /* SHRAV_R_PH */ |
| DSPROpnd, DSPROpnd, GPR32Opnd, |
| /* SHRAV_R_PH_MM */ |
| DSPROpnd, DSPROpnd, GPR32Opnd, |
| /* SHRAV_R_QB */ |
| DSPROpnd, DSPROpnd, GPR32Opnd, |
| /* SHRAV_R_QB_MMR2 */ |
| DSPROpnd, DSPROpnd, GPR32Opnd, |
| /* SHRAV_R_W */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* SHRAV_R_W_MM */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* SHRA_PH */ |
| DSPROpnd, DSPROpnd, uimm4, |
| /* SHRA_PH_MM */ |
| DSPROpnd, DSPROpnd, uimm4, |
| /* SHRA_QB */ |
| DSPROpnd, DSPROpnd, uimm3, |
| /* SHRA_QB_MMR2 */ |
| DSPROpnd, DSPROpnd, uimm3, |
| /* SHRA_R_PH */ |
| DSPROpnd, DSPROpnd, uimm4, |
| /* SHRA_R_PH_MM */ |
| DSPROpnd, DSPROpnd, uimm4, |
| /* SHRA_R_QB */ |
| DSPROpnd, DSPROpnd, uimm3, |
| /* SHRA_R_QB_MMR2 */ |
| DSPROpnd, DSPROpnd, uimm3, |
| /* SHRA_R_W */ |
| GPR32Opnd, GPR32Opnd, uimm5, |
| /* SHRA_R_W_MM */ |
| GPR32Opnd, GPR32Opnd, uimm5, |
| /* SHRLV_PH */ |
| DSPROpnd, DSPROpnd, GPR32Opnd, |
| /* SHRLV_PH_MMR2 */ |
| DSPROpnd, DSPROpnd, GPR32Opnd, |
| /* SHRLV_QB */ |
| DSPROpnd, DSPROpnd, GPR32Opnd, |
| /* SHRLV_QB_MM */ |
| DSPROpnd, DSPROpnd, GPR32Opnd, |
| /* SHRL_PH */ |
| DSPROpnd, DSPROpnd, uimm4, |
| /* SHRL_PH_MMR2 */ |
| DSPROpnd, DSPROpnd, uimm4, |
| /* SHRL_QB */ |
| DSPROpnd, DSPROpnd, uimm3, |
| /* SHRL_QB_MM */ |
| DSPROpnd, DSPROpnd, uimm3, |
| /* SH_MM */ |
| GPR32Opnd, -1, simm16, |
| /* SH_MMR6 */ |
| GPR32Opnd, -1, simm16, |
| /* SIGRIE */ |
| uimm16, |
| /* SIGRIE_MMR6 */ |
| uimm16, |
| /* SLDI_B */ |
| MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, uimm4, |
| /* SLDI_D */ |
| MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, uimm1, |
| /* SLDI_H */ |
| MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, uimm3, |
| /* SLDI_W */ |
| MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, uimm2, |
| /* SLD_B */ |
| MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, GPR32Opnd, |
| /* SLD_D */ |
| MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, GPR32Opnd, |
| /* SLD_H */ |
| MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, GPR32Opnd, |
| /* SLD_W */ |
| MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, GPR32Opnd, |
| /* SLL */ |
| GPR32Opnd, GPR32Opnd, uimm5, |
| /* SLL16_MM */ |
| GPRMM16Opnd, GPRMM16Opnd, uimm3_shift, |
| /* SLL16_MMR6 */ |
| GPRMM16Opnd, GPRMM16Opnd, uimm3_shift, |
| /* SLL64_32 */ |
| GPR64, GPR32, |
| /* SLL64_64 */ |
| GPR64, GPR64, |
| /* SLLI_B */ |
| MSA128BOpnd, MSA128BOpnd, vsplat_uimm3, |
| /* SLLI_D */ |
| MSA128DOpnd, MSA128DOpnd, vsplat_uimm6, |
| /* SLLI_H */ |
| MSA128HOpnd, MSA128HOpnd, vsplat_uimm4, |
| /* SLLI_W */ |
| MSA128WOpnd, MSA128WOpnd, vsplat_uimm5, |
| /* SLLV */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* SLLV_MM */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* SLL_B */ |
| MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
| /* SLL_D */ |
| MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
| /* SLL_H */ |
| MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
| /* SLL_MM */ |
| GPR32Opnd, GPR32Opnd, uimm5, |
| /* SLL_MMR6 */ |
| GPR32Opnd, GPR32Opnd, uimm5, |
| /* SLL_W */ |
| MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* SLT */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* SLT64 */ |
| GPR32Opnd, GPR64Opnd, GPR64Opnd, |
| /* SLT_MM */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* SLTi */ |
| GPR32Opnd, GPR32Opnd, simm16, |
| /* SLTi64 */ |
| GPR32Opnd, GPR64Opnd, simm16_64, |
| /* SLTi_MM */ |
| GPR32Opnd, GPR32Opnd, simm16, |
| /* SLTiu */ |
| GPR32Opnd, GPR32Opnd, simm16, |
| /* SLTiu64 */ |
| GPR32Opnd, GPR64Opnd, simm16_64, |
| /* SLTiu_MM */ |
| GPR32Opnd, GPR32Opnd, simm16, |
| /* SLTu */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* SLTu64 */ |
| GPR32Opnd, GPR64Opnd, GPR64Opnd, |
| /* SLTu_MM */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* SNE */ |
| GPR64Opnd, GPR64Opnd, GPR64Opnd, |
| /* SNEi */ |
| GPR64Opnd, GPR64Opnd, simm10_64, |
| /* SPLATI_B */ |
| MSA128BOpnd, MSA128BOpnd, vsplat_uimm4, |
| /* SPLATI_D */ |
| MSA128DOpnd, MSA128DOpnd, vsplat_uimm1, |
| /* SPLATI_H */ |
| MSA128HOpnd, MSA128HOpnd, vsplat_uimm3, |
| /* SPLATI_W */ |
| MSA128WOpnd, MSA128WOpnd, vsplat_uimm2, |
| /* SPLAT_B */ |
| MSA128BOpnd, MSA128BOpnd, GPR32Opnd, |
| /* SPLAT_D */ |
| MSA128DOpnd, MSA128DOpnd, GPR32Opnd, |
| /* SPLAT_H */ |
| MSA128HOpnd, MSA128HOpnd, GPR32Opnd, |
| /* SPLAT_W */ |
| MSA128WOpnd, MSA128WOpnd, GPR32Opnd, |
| /* SRA */ |
| GPR32Opnd, GPR32Opnd, uimm5, |
| /* SRAI_B */ |
| MSA128BOpnd, MSA128BOpnd, vsplat_uimm3, |
| /* SRAI_D */ |
| MSA128DOpnd, MSA128DOpnd, vsplat_uimm6, |
| /* SRAI_H */ |
| MSA128HOpnd, MSA128HOpnd, vsplat_uimm4, |
| /* SRAI_W */ |
| MSA128WOpnd, MSA128WOpnd, vsplat_uimm5, |
| /* SRARI_B */ |
| MSA128BOpnd, MSA128BOpnd, uimm3, |
| /* SRARI_D */ |
| MSA128DOpnd, MSA128DOpnd, uimm6, |
| /* SRARI_H */ |
| MSA128HOpnd, MSA128HOpnd, uimm4, |
| /* SRARI_W */ |
| MSA128WOpnd, MSA128WOpnd, uimm5, |
| /* SRAR_B */ |
| MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
| /* SRAR_D */ |
| MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
| /* SRAR_H */ |
| MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
| /* SRAR_W */ |
| MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* SRAV */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* SRAV_MM */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* SRA_B */ |
| MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
| /* SRA_D */ |
| MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
| /* SRA_H */ |
| MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
| /* SRA_MM */ |
| GPR32Opnd, GPR32Opnd, uimm5, |
| /* SRA_W */ |
| MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* SRL */ |
| GPR32Opnd, GPR32Opnd, uimm5, |
| /* SRL16_MM */ |
| GPRMM16Opnd, GPRMM16Opnd, uimm3_shift, |
| /* SRL16_MMR6 */ |
| GPRMM16Opnd, GPRMM16Opnd, uimm3_shift, |
| /* SRLI_B */ |
| MSA128BOpnd, MSA128BOpnd, vsplat_uimm3, |
| /* SRLI_D */ |
| MSA128DOpnd, MSA128DOpnd, vsplat_uimm6, |
| /* SRLI_H */ |
| MSA128HOpnd, MSA128HOpnd, vsplat_uimm4, |
| /* SRLI_W */ |
| MSA128WOpnd, MSA128WOpnd, vsplat_uimm5, |
| /* SRLRI_B */ |
| MSA128BOpnd, MSA128BOpnd, uimm3, |
| /* SRLRI_D */ |
| MSA128DOpnd, MSA128DOpnd, uimm6, |
| /* SRLRI_H */ |
| MSA128HOpnd, MSA128HOpnd, uimm4, |
| /* SRLRI_W */ |
| MSA128WOpnd, MSA128WOpnd, uimm5, |
| /* SRLR_B */ |
| MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
| /* SRLR_D */ |
| MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
| /* SRLR_H */ |
| MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
| /* SRLR_W */ |
| MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* SRLV */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* SRLV_MM */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* SRL_B */ |
| MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
| /* SRL_D */ |
| MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
| /* SRL_H */ |
| MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
| /* SRL_MM */ |
| GPR32Opnd, GPR32Opnd, uimm5, |
| /* SRL_W */ |
| MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* SSNOP */ |
| /* SSNOP_MM */ |
| /* SSNOP_MMR6 */ |
| /* ST_B */ |
| MSA128BOpnd, -1, simm10, |
| /* ST_D */ |
| MSA128DOpnd, -1, simm10_lsl3, |
| /* ST_H */ |
| MSA128HOpnd, -1, simm10_lsl1, |
| /* ST_W */ |
| MSA128WOpnd, -1, simm10_lsl2, |
| /* SUB */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* SUBQH_PH */ |
| DSPROpnd, DSPROpnd, DSPROpnd, |
| /* SUBQH_PH_MMR2 */ |
| DSPROpnd, DSPROpnd, DSPROpnd, |
| /* SUBQH_R_PH */ |
| DSPROpnd, DSPROpnd, DSPROpnd, |
| /* SUBQH_R_PH_MMR2 */ |
| DSPROpnd, DSPROpnd, DSPROpnd, |
| /* SUBQH_R_W */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* SUBQH_R_W_MMR2 */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* SUBQH_W */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* SUBQH_W_MMR2 */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* SUBQ_PH */ |
| DSPROpnd, DSPROpnd, DSPROpnd, |
| /* SUBQ_PH_MM */ |
| DSPROpnd, DSPROpnd, DSPROpnd, |
| /* SUBQ_S_PH */ |
| DSPROpnd, DSPROpnd, DSPROpnd, |
| /* SUBQ_S_PH_MM */ |
| DSPROpnd, DSPROpnd, DSPROpnd, |
| /* SUBQ_S_W */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* SUBQ_S_W_MM */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* SUBSUS_U_B */ |
| MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
| /* SUBSUS_U_D */ |
| MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
| /* SUBSUS_U_H */ |
| MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
| /* SUBSUS_U_W */ |
| MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* SUBSUU_S_B */ |
| MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
| /* SUBSUU_S_D */ |
| MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
| /* SUBSUU_S_H */ |
| MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
| /* SUBSUU_S_W */ |
| MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* SUBS_S_B */ |
| MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
| /* SUBS_S_D */ |
| MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
| /* SUBS_S_H */ |
| MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
| /* SUBS_S_W */ |
| MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* SUBS_U_B */ |
| MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
| /* SUBS_U_D */ |
| MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
| /* SUBS_U_H */ |
| MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
| /* SUBS_U_W */ |
| MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* SUBU16_MM */ |
| GPRMM16Opnd, GPRMM16Opnd, GPRMM16Opnd, |
| /* SUBU16_MMR6 */ |
| GPRMM16Opnd, GPRMM16Opnd, GPRMM16Opnd, |
| /* SUBUH_QB */ |
| DSPROpnd, DSPROpnd, DSPROpnd, |
| /* SUBUH_QB_MMR2 */ |
| DSPROpnd, DSPROpnd, DSPROpnd, |
| /* SUBUH_R_QB */ |
| DSPROpnd, DSPROpnd, DSPROpnd, |
| /* SUBUH_R_QB_MMR2 */ |
| DSPROpnd, DSPROpnd, DSPROpnd, |
| /* SUBU_MMR6 */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* SUBU_PH */ |
| DSPROpnd, DSPROpnd, DSPROpnd, |
| /* SUBU_PH_MMR2 */ |
| DSPROpnd, DSPROpnd, DSPROpnd, |
| /* SUBU_QB */ |
| DSPROpnd, DSPROpnd, DSPROpnd, |
| /* SUBU_QB_MM */ |
| DSPROpnd, DSPROpnd, DSPROpnd, |
| /* SUBU_S_PH */ |
| DSPROpnd, DSPROpnd, DSPROpnd, |
| /* SUBU_S_PH_MMR2 */ |
| DSPROpnd, DSPROpnd, DSPROpnd, |
| /* SUBU_S_QB */ |
| DSPROpnd, DSPROpnd, DSPROpnd, |
| /* SUBU_S_QB_MM */ |
| DSPROpnd, DSPROpnd, DSPROpnd, |
| /* SUBVI_B */ |
| MSA128BOpnd, MSA128BOpnd, vsplat_uimm5, |
| /* SUBVI_D */ |
| MSA128DOpnd, MSA128DOpnd, vsplat_uimm5, |
| /* SUBVI_H */ |
| MSA128HOpnd, MSA128HOpnd, vsplat_uimm5, |
| /* SUBVI_W */ |
| MSA128WOpnd, MSA128WOpnd, vsplat_uimm5, |
| /* SUBV_B */ |
| MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
| /* SUBV_D */ |
| MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
| /* SUBV_H */ |
| MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
| /* SUBV_W */ |
| MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* SUB_MM */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* SUB_MMR6 */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* SUBu */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* SUBu_MM */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* SUXC1 */ |
| AFGR64Opnd, -1, -1, |
| /* SUXC164 */ |
| FGR64Opnd, -1, -1, |
| /* SUXC1_MM */ |
| FGR64Opnd, -1, -1, |
| /* SW */ |
| GPR32Opnd, -1, simm16, |
| /* SW16_MM */ |
| GPRMM16OpndZero, -1, simm4, |
| /* SW16_MMR6 */ |
| GPRMM16OpndZero, -1, simm4, |
| /* SW64 */ |
| GPR64Opnd, -1, simm16, |
| /* SWC1 */ |
| FGR32Opnd, -1, simm16, |
| /* SWC1_MM */ |
| FGR32Opnd, -1, simm16, |
| /* SWC2 */ |
| COP2Opnd, -1, simm16, |
| /* SWC2_MMR6 */ |
| COP2Opnd, GPR32, simm11, |
| /* SWC2_R6 */ |
| COP2Opnd, -1, simm11, |
| /* SWC3 */ |
| COP3Opnd, -1, simm16, |
| /* SWDSP */ |
| DSPROpnd, -1, simm16, |
| /* SWDSP_MM */ |
| DSPROpnd, -1, simm16, |
| /* SWE */ |
| GPR32Opnd, -1, simm9, |
| /* SWE_MM */ |
| GPR32Opnd, -1, simm9, |
| /* SWL */ |
| GPR32Opnd, -1, simm16, |
| /* SWL64 */ |
| GPR64Opnd, -1, simm16, |
| /* SWLE */ |
| GPR32Opnd, -1, simm9, |
| /* SWLE_MM */ |
| GPR32Opnd, -1, simm9, |
| /* SWL_MM */ |
| GPR32Opnd, -1, simm12, |
| /* SWM16_MM */ |
| reglist16, -1, uimm8, |
| /* SWM16_MMR6 */ |
| reglist16, -1, uimm8, |
| /* SWM32_MM */ |
| reglist, -1, simm12, |
| /* SWP_MM */ |
| GPR32Opnd, GPR32Opnd, -1, simm12, |
| /* SWR */ |
| GPR32Opnd, -1, simm16, |
| /* SWR64 */ |
| GPR64Opnd, -1, simm16, |
| /* SWRE */ |
| GPR32Opnd, -1, simm9, |
| /* SWRE_MM */ |
| GPR32Opnd, -1, simm9, |
| /* SWR_MM */ |
| GPR32Opnd, -1, simm12, |
| /* SWSP_MM */ |
| GPR32Opnd, -1, simm5, |
| /* SWSP_MMR6 */ |
| GPR32Opnd, -1, simm5, |
| /* SWXC1 */ |
| FGR32Opnd, -1, -1, |
| /* SWXC1_MM */ |
| FGR32Opnd, -1, -1, |
| /* SW_MM */ |
| GPR32Opnd, -1, simm16, |
| /* SW_MMR6 */ |
| GPR32Opnd, -1, simm16, |
| /* SYNC */ |
| uimm5, |
| /* SYNCI */ |
| -1, simm16, |
| /* SYNCI_MM */ |
| -1, simm16, |
| /* SYNCI_MMR6 */ |
| -1, simm16, |
| /* SYNC_MM */ |
| uimm5, |
| /* SYNC_MMR6 */ |
| uimm5, |
| /* SYSCALL */ |
| uimm20, |
| /* SYSCALL_MM */ |
| uimm10, |
| /* Save16 */ |
| /* SaveX16 */ |
| /* SbRxRyOffMemX16 */ |
| CPU16Regs, CPU16Regs, simm16, |
| /* SebRx16 */ |
| CPU16Regs, CPU16Regs, |
| /* SehRx16 */ |
| CPU16Regs, CPU16Regs, |
| /* ShRxRyOffMemX16 */ |
| CPU16Regs, CPU16Regs, simm16, |
| /* SllX16 */ |
| CPU16Regs, CPU16Regs, uimm5, |
| /* SllvRxRy16 */ |
| CPU16Regs, CPU16Regs, CPU16Regs, |
| /* SltRxRy16 */ |
| CPU16Regs, CPU16Regs, |
| /* SltiRxImm16 */ |
| CPU16Regs, simm16, |
| /* SltiRxImmX16 */ |
| CPU16Regs, simm16, |
| /* SltiuRxImm16 */ |
| CPU16Regs, simm16, |
| /* SltiuRxImmX16 */ |
| CPU16Regs, simm16, |
| /* SltuRxRy16 */ |
| CPU16Regs, CPU16Regs, |
| /* SraX16 */ |
| CPU16Regs, CPU16Regs, uimm5, |
| /* SravRxRy16 */ |
| CPU16Regs, CPU16Regs, CPU16Regs, |
| /* SrlX16 */ |
| CPU16Regs, CPU16Regs, uimm5, |
| /* SrlvRxRy16 */ |
| CPU16Regs, CPU16Regs, CPU16Regs, |
| /* SubuRxRyRz16 */ |
| CPU16Regs, CPU16Regs, CPU16Regs, |
| /* SwRxRyOffMemX16 */ |
| CPU16Regs, CPU16Regs, simm16, |
| /* SwRxSpImmX16 */ |
| CPU16Regs, CPU16RegsPlusSP, simm16, |
| /* TEQ */ |
| GPR32Opnd, GPR32Opnd, uimm10, |
| /* TEQI */ |
| GPR32Opnd, simm16, |
| /* TEQI_MM */ |
| GPR32Opnd, simm16, |
| /* TEQ_MM */ |
| GPR32Opnd, GPR32Opnd, uimm4, |
| /* TGE */ |
| GPR32Opnd, GPR32Opnd, uimm10, |
| /* TGEI */ |
| GPR32Opnd, simm16, |
| /* TGEIU */ |
| GPR32Opnd, simm16, |
| /* TGEIU_MM */ |
| GPR32Opnd, simm16, |
| /* TGEI_MM */ |
| GPR32Opnd, simm16, |
| /* TGEU */ |
| GPR32Opnd, GPR32Opnd, uimm10, |
| /* TGEU_MM */ |
| GPR32Opnd, GPR32Opnd, uimm4, |
| /* TGE_MM */ |
| GPR32Opnd, GPR32Opnd, uimm4, |
| /* TLBGINV */ |
| /* TLBGINVF */ |
| /* TLBGINVF_MM */ |
| /* TLBGINV_MM */ |
| /* TLBGP */ |
| /* TLBGP_MM */ |
| /* TLBGR */ |
| /* TLBGR_MM */ |
| /* TLBGWI */ |
| /* TLBGWI_MM */ |
| /* TLBGWR */ |
| /* TLBGWR_MM */ |
| /* TLBINV */ |
| /* TLBINVF */ |
| /* TLBINVF_MMR6 */ |
| /* TLBINV_MMR6 */ |
| /* TLBP */ |
| /* TLBP_MM */ |
| /* TLBR */ |
| /* TLBR_MM */ |
| /* TLBWI */ |
| /* TLBWI_MM */ |
| /* TLBWR */ |
| /* TLBWR_MM */ |
| /* TLT */ |
| GPR32Opnd, GPR32Opnd, uimm10, |
| /* TLTI */ |
| GPR32Opnd, simm16, |
| /* TLTIU_MM */ |
| GPR32Opnd, simm16, |
| /* TLTI_MM */ |
| GPR32Opnd, simm16, |
| /* TLTU */ |
| GPR32Opnd, GPR32Opnd, uimm10, |
| /* TLTU_MM */ |
| GPR32Opnd, GPR32Opnd, uimm4, |
| /* TLT_MM */ |
| GPR32Opnd, GPR32Opnd, uimm4, |
| /* TNE */ |
| GPR32Opnd, GPR32Opnd, uimm10, |
| /* TNEI */ |
| GPR32Opnd, simm16, |
| /* TNEI_MM */ |
| GPR32Opnd, simm16, |
| /* TNE_MM */ |
| GPR32Opnd, GPR32Opnd, uimm4, |
| /* TRUNC_L_D64 */ |
| FGR64Opnd, FGR64Opnd, |
| /* TRUNC_L_D_MMR6 */ |
| FGR64Opnd, FGR64Opnd, |
| /* TRUNC_L_S */ |
| FGR64Opnd, FGR32Opnd, |
| /* TRUNC_L_S_MMR6 */ |
| FGR64Opnd, FGR32Opnd, |
| /* TRUNC_W_D32 */ |
| FGR32Opnd, AFGR64Opnd, |
| /* TRUNC_W_D64 */ |
| FGR32Opnd, FGR64Opnd, |
| /* TRUNC_W_D_MMR6 */ |
| FGR32Opnd, FGR64Opnd, |
| /* TRUNC_W_MM */ |
| FGR32Opnd, AFGR64Opnd, |
| /* TRUNC_W_S */ |
| FGR32Opnd, FGR32Opnd, |
| /* TRUNC_W_S_MM */ |
| FGR32Opnd, FGR32Opnd, |
| /* TRUNC_W_S_MMR6 */ |
| FGR32Opnd, FGR32Opnd, |
| /* TTLTIU */ |
| GPR32Opnd, simm16, |
| /* UDIV */ |
| GPR32Opnd, GPR32Opnd, |
| /* UDIV_MM */ |
| GPR32Opnd, GPR32Opnd, |
| /* V3MULU */ |
| GPR64Opnd, GPR64Opnd, GPR64Opnd, |
| /* VMM0 */ |
| GPR64Opnd, GPR64Opnd, GPR64Opnd, |
| /* VMULU */ |
| GPR64Opnd, GPR64Opnd, GPR64Opnd, |
| /* VSHF_B */ |
| MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
| /* VSHF_D */ |
| MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
| /* VSHF_H */ |
| MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
| /* VSHF_W */ |
| MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
| /* WAIT */ |
| /* WAIT_MM */ |
| uimm10, |
| /* WAIT_MMR6 */ |
| uimm10, |
| /* WRDSP */ |
| GPR32Opnd, uimm10, |
| /* WRDSP_MM */ |
| GPR32Opnd, uimm7, |
| /* WRPGPR_MMR6 */ |
| GPR32Opnd, GPR32Opnd, |
| /* WSBH */ |
| GPR32Opnd, GPR32Opnd, |
| /* WSBH_MM */ |
| GPR32Opnd, GPR32Opnd, |
| /* WSBH_MMR6 */ |
| GPR32Opnd, GPR32Opnd, |
| /* XOR */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* XOR16_MM */ |
| GPRMM16Opnd, GPRMM16Opnd, GPRMM16Opnd, |
| /* XOR16_MMR6 */ |
| GPRMM16Opnd, GPRMM16Opnd, GPRMM16Opnd, |
| /* XOR64 */ |
| GPR64Opnd, GPR64Opnd, GPR64Opnd, |
| /* XORI_B */ |
| MSA128BOpnd, MSA128BOpnd, vsplat_uimm8, |
| /* XORI_MMR6 */ |
| GPR32Opnd, GPR32Opnd, uimm16, |
| /* XOR_MM */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* XOR_MMR6 */ |
| GPR32Opnd, GPR32Opnd, GPR32Opnd, |
| /* XOR_V */ |
| MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
| /* XORi */ |
| GPR32Opnd, GPR32Opnd, uimm16, |
| /* XORi64 */ |
| GPR64Opnd, GPR64Opnd, uimm16_64, |
| /* XORi_MM */ |
| GPR32Opnd, GPR32Opnd, uimm16, |
| /* XorRxRxRy16 */ |
| CPU16Regs, CPU16Regs, CPU16Regs, |
| /* YIELD */ |
| GPR32Opnd, GPR32Opnd, |
| }; |
| return OpcodeOperandTypes[Offsets[Opcode] + OpIdx]; |
| } |
| } // end namespace Mips |
| } // end namespace llvm |
| #endif // GET_INSTRINFO_OPERAND_TYPE |
| |
| #ifdef GET_INSTRINFO_MEM_OPERAND_SIZE |
| #undef GET_INSTRINFO_MEM_OPERAND_SIZE |
| namespace llvm { |
| namespace Mips { |
| LLVM_READONLY |
| static int getMemOperandSize(int OpType) { |
| switch (OpType) { |
| default: return 0; |
| } |
| } |
| } // end namespace Mips |
| } // end namespace llvm |
| #endif // GET_INSTRINFO_MEM_OPERAND_SIZE |
| |
| #ifdef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP |
| #undef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP |
| namespace llvm { |
| namespace Mips { |
| LLVM_READONLY static unsigned |
| getLogicalOperandSize(uint16_t Opcode, uint16_t LogicalOpIdx) { |
| return LogicalOpIdx; |
| } |
| LLVM_READONLY static inline unsigned |
| getLogicalOperandIdx(uint16_t Opcode, uint16_t LogicalOpIdx) { |
| auto S = 0U; |
| for (auto i = 0U; i < LogicalOpIdx; ++i) |
| S += getLogicalOperandSize(Opcode, i); |
| return S; |
| } |
| } // end namespace Mips |
| } // end namespace llvm |
| #endif // GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP |
| |
| #ifdef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP |
| #undef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP |
| namespace llvm { |
| namespace Mips { |
| LLVM_READONLY static int |
| getLogicalOperandType(uint16_t Opcode, uint16_t LogicalOpIdx) { |
| return -1; |
| } |
| } // end namespace Mips |
| } // end namespace llvm |
| #endif // GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP |
| |
| #ifdef GET_INSTRINFO_MC_HELPER_DECLS |
| #undef GET_INSTRINFO_MC_HELPER_DECLS |
| |
| namespace llvm { |
| class MCInst; |
| class FeatureBitset; |
| |
| namespace Mips_MC { |
| |
| void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features); |
| |
| } // end namespace Mips_MC |
| } // end namespace llvm |
| |
| #endif // GET_INSTRINFO_MC_HELPER_DECLS |
| |
| #ifdef GET_INSTRINFO_MC_HELPERS |
| #undef GET_INSTRINFO_MC_HELPERS |
| |
| namespace llvm { |
| namespace Mips_MC { |
| |
| } // end namespace Mips_MC |
| } // end namespace llvm |
| |
| #endif // GET_GENISTRINFO_MC_HELPERS |
| |
| #ifdef ENABLE_INSTR_PREDICATE_VERIFIER |
| #undef ENABLE_INSTR_PREDICATE_VERIFIER |
| #include <sstream> |
| |
| namespace llvm { |
| namespace Mips_MC { |
| |
| // Bits for subtarget features that participate in instruction matching. |
| enum SubtargetFeatureBits : uint8_t { |
| Feature_HasMips2Bit = 11, |
| Feature_HasMips3_32Bit = 18, |
| Feature_HasMips3_32r2Bit = 19, |
| Feature_HasMips3Bit = 12, |
| Feature_NotMips3Bit = 47, |
| Feature_HasMips4_32Bit = 20, |
| Feature_NotMips4_32Bit = 49, |
| Feature_HasMips4_32r2Bit = 21, |
| Feature_HasMips5_32r2Bit = 22, |
| Feature_HasMips32Bit = 13, |
| Feature_HasMips32r2Bit = 14, |
| Feature_HasMips32r5Bit = 15, |
| Feature_HasMips32r6Bit = 16, |
| Feature_NotMips32r6Bit = 48, |
| Feature_IsGP64bitBit = 33, |
| Feature_IsGP32bitBit = 32, |
| Feature_IsPTR64bitBit = 37, |
| Feature_IsPTR32bitBit = 36, |
| Feature_HasMips64Bit = 23, |
| Feature_NotMips64Bit = 50, |
| Feature_HasMips64r2Bit = 24, |
| Feature_HasMips64r5Bit = 25, |
| Feature_HasMips64r6Bit = 26, |
| Feature_NotMips64r6Bit = 51, |
| Feature_InMips16ModeBit = 30, |
| Feature_NotInMips16ModeBit = 46, |
| Feature_HasCnMipsBit = 1, |
| Feature_NotCnMipsBit = 42, |
| Feature_HasCnMipsPBit = 2, |
| Feature_NotCnMipsPBit = 43, |
| Feature_IsSym32Bit = 39, |
| Feature_IsSym64Bit = 40, |
| Feature_HasStdEncBit = 27, |
| Feature_InMicroMipsBit = 29, |
| Feature_NotInMicroMipsBit = 45, |
| Feature_HasEVABit = 6, |
| Feature_HasMSABit = 8, |
| Feature_HasMadd4Bit = 10, |
| Feature_HasMTBit = 9, |
| Feature_UseIndirectJumpsHazardBit = 52, |
| Feature_NoIndirectJumpGuardsBit = 41, |
| Feature_HasCRCBit = 0, |
| Feature_HasVirtBit = 28, |
| Feature_HasGINVBit = 7, |
| Feature_IsFP64bitBit = 31, |
| Feature_NotFP64bitBit = 44, |
| Feature_IsSingleFloatBit = 38, |
| Feature_IsNotSingleFloatBit = 34, |
| Feature_IsNotSoftFloatBit = 35, |
| Feature_HasMips3DBit = 17, |
| Feature_HasDSPBit = 3, |
| Feature_HasDSPR2Bit = 4, |
| Feature_HasDSPR3Bit = 5, |
| }; |
| |
| #ifndef NDEBUG |
| static const char *SubtargetFeatureNames[] = { |
| "Feature_HasCRC", |
| "Feature_HasCnMips", |
| "Feature_HasCnMipsP", |
| "Feature_HasDSP", |
| "Feature_HasDSPR2", |
| "Feature_HasDSPR3", |
| "Feature_HasEVA", |
| "Feature_HasGINV", |
| "Feature_HasMSA", |
| "Feature_HasMT", |
| "Feature_HasMadd4", |
| "Feature_HasMips2", |
| "Feature_HasMips3", |
| "Feature_HasMips32", |
| "Feature_HasMips32r2", |
| "Feature_HasMips32r5", |
| "Feature_HasMips32r6", |
| "Feature_HasMips3D", |
| "Feature_HasMips3_32", |
| "Feature_HasMips3_32r2", |
| "Feature_HasMips4_32", |
| "Feature_HasMips4_32r2", |
| "Feature_HasMips5_32r2", |
| "Feature_HasMips64", |
| "Feature_HasMips64r2", |
| "Feature_HasMips64r5", |
| "Feature_HasMips64r6", |
| "Feature_HasStdEnc", |
| "Feature_HasVirt", |
| "Feature_InMicroMips", |
| "Feature_InMips16Mode", |
| "Feature_IsFP64bit", |
| "Feature_IsGP32bit", |
| "Feature_IsGP64bit", |
| "Feature_IsNotSingleFloat", |
| "Feature_IsNotSoftFloat", |
| "Feature_IsPTR32bit", |
| "Feature_IsPTR64bit", |
| "Feature_IsSingleFloat", |
| "Feature_IsSym32", |
| "Feature_IsSym64", |
| "Feature_NoIndirectJumpGuards", |
| "Feature_NotCnMips", |
| "Feature_NotCnMipsP", |
| "Feature_NotFP64bit", |
| "Feature_NotInMicroMips", |
| "Feature_NotInMips16Mode", |
| "Feature_NotMips3", |
| "Feature_NotMips32r6", |
| "Feature_NotMips4_32", |
| "Feature_NotMips64", |
| "Feature_NotMips64r6", |
| "Feature_UseIndirectJumpsHazard", |
| nullptr |
| }; |
| |
| #endif // NDEBUG |
| |
| FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) { |
| FeatureBitset Features; |
| if (FB[Mips::FeatureMips2]) |
| Features.set(Feature_HasMips2Bit); |
| if (FB[Mips::FeatureMips3_32]) |
| Features.set(Feature_HasMips3_32Bit); |
| if (FB[Mips::FeatureMips3_32r2]) |
| Features.set(Feature_HasMips3_32r2Bit); |
| if (FB[Mips::FeatureMips3]) |
| Features.set(Feature_HasMips3Bit); |
| if (!FB[Mips::FeatureMips3]) |
| Features.set(Feature_NotMips3Bit); |
| if (FB[Mips::FeatureMips4_32]) |
| Features.set(Feature_HasMips4_32Bit); |
| if (!FB[Mips::FeatureMips4_32]) |
| Features.set(Feature_NotMips4_32Bit); |
| if (FB[Mips::FeatureMips4_32r2]) |
| Features.set(Feature_HasMips4_32r2Bit); |
| if (FB[Mips::FeatureMips5_32r2]) |
| Features.set(Feature_HasMips5_32r2Bit); |
| if (FB[Mips::FeatureMips32]) |
| Features.set(Feature_HasMips32Bit); |
| if (FB[Mips::FeatureMips32r2]) |
| Features.set(Feature_HasMips32r2Bit); |
| if (FB[Mips::FeatureMips32r5]) |
| Features.set(Feature_HasMips32r5Bit); |
| if (FB[Mips::FeatureMips32r6]) |
| Features.set(Feature_HasMips32r6Bit); |
| if (!FB[Mips::FeatureMips32r6]) |
| Features.set(Feature_NotMips32r6Bit); |
| if (FB[Mips::FeatureGP64Bit]) |
| Features.set(Feature_IsGP64bitBit); |
| if (!FB[Mips::FeatureGP64Bit]) |
| Features.set(Feature_IsGP32bitBit); |
| if (FB[Mips::FeaturePTR64Bit]) |
| Features.set(Feature_IsPTR64bitBit); |
| if (!FB[Mips::FeaturePTR64Bit]) |
| Features.set(Feature_IsPTR32bitBit); |
| if (FB[Mips::FeatureMips64]) |
| Features.set(Feature_HasMips64Bit); |
| if (!FB[Mips::FeatureMips64]) |
| Features.set(Feature_NotMips64Bit); |
| if (FB[Mips::FeatureMips64r2]) |
| Features.set(Feature_HasMips64r2Bit); |
| if (FB[Mips::FeatureMips64r5]) |
| Features.set(Feature_HasMips64r5Bit); |
| if (FB[Mips::FeatureMips64r6]) |
| Features.set(Feature_HasMips64r6Bit); |
| if (!FB[Mips::FeatureMips64r6]) |
| Features.set(Feature_NotMips64r6Bit); |
| if (FB[Mips::FeatureMips16]) |
| Features.set(Feature_InMips16ModeBit); |
| if (!FB[Mips::FeatureMips16]) |
| Features.set(Feature_NotInMips16ModeBit); |
| if (FB[Mips::FeatureCnMips]) |
| Features.set(Feature_HasCnMipsBit); |
| if (!FB[Mips::FeatureCnMips]) |
| Features.set(Feature_NotCnMipsBit); |
| if (FB[Mips::FeatureCnMipsP]) |
| Features.set(Feature_HasCnMipsPBit); |
| if (!FB[Mips::FeatureCnMipsP]) |
| Features.set(Feature_NotCnMipsPBit); |
| if (FB[Mips::FeatureSym32]) |
| Features.set(Feature_IsSym32Bit); |
| if (!FB[Mips::FeatureSym32]) |
| Features.set(Feature_IsSym64Bit); |
| if (!FB[Mips::FeatureMips16]) |
| Features.set(Feature_HasStdEncBit); |
| if (FB[Mips::FeatureMicroMips]) |
| Features.set(Feature_InMicroMipsBit); |
| if (!FB[Mips::FeatureMicroMips]) |
| Features.set(Feature_NotInMicroMipsBit); |
| if (FB[Mips::FeatureEVA]) |
| Features.set(Feature_HasEVABit); |
| if (FB[Mips::FeatureMSA]) |
| Features.set(Feature_HasMSABit); |
| if (!FB[Mips::FeatureNoMadd4]) |
| Features.set(Feature_HasMadd4Bit); |
| if (FB[Mips::FeatureMT]) |
| Features.set(Feature_HasMTBit); |
| if (FB[Mips::FeatureUseIndirectJumpsHazard]) |
| Features.set(Feature_UseIndirectJumpsHazardBit); |
| if (!FB[Mips::FeatureUseIndirectJumpsHazard]) |
| Features.set(Feature_NoIndirectJumpGuardsBit); |
| if (FB[Mips::FeatureCRC]) |
| Features.set(Feature_HasCRCBit); |
| if (FB[Mips::FeatureVirt]) |
| Features.set(Feature_HasVirtBit); |
| if (FB[Mips::FeatureGINV]) |
| Features.set(Feature_HasGINVBit); |
| if (FB[Mips::FeatureFP64Bit]) |
| Features.set(Feature_IsFP64bitBit); |
| if (!FB[Mips::FeatureFP64Bit]) |
| Features.set(Feature_NotFP64bitBit); |
| if (FB[Mips::FeatureSingleFloat]) |
| Features.set(Feature_IsSingleFloatBit); |
| if (!FB[Mips::FeatureSingleFloat]) |
| Features.set(Feature_IsNotSingleFloatBit); |
| if (!FB[Mips::FeatureSoftFloat]) |
| Features.set(Feature_IsNotSoftFloatBit); |
| if (FB[Mips::FeatureMips3D]) |
| Features.set(Feature_HasMips3DBit); |
| if (FB[Mips::FeatureDSP]) |
| Features.set(Feature_HasDSPBit); |
| if (FB[Mips::FeatureDSPR2]) |
| Features.set(Feature_HasDSPR2Bit); |
| if (FB[Mips::FeatureDSPR3]) |
| Features.set(Feature_HasDSPR3Bit); |
| return Features; |
| } |
| |
| #ifndef NDEBUG |
| // Feature bitsets. |
| enum : uint8_t { |
| CEFBS_None, |
| CEFBS_HasCnMips, |
| CEFBS_HasCnMipsP, |
| CEFBS_HasDSP, |
| CEFBS_HasDSPR2, |
| CEFBS_HasMSA, |
| CEFBS_HasMT, |
| CEFBS_InMicroMips, |
| CEFBS_InMips16Mode, |
| CEFBS_IsGP32bit, |
| CEFBS_IsGP64bit, |
| CEFBS_IsNotSoftFloat, |
| CEFBS_NotCnMips, |
| CEFBS_NotInMips16Mode, |
| CEFBS_HasDSP_NotInMicroMips, |
| CEFBS_HasStdEnc_HasMSA, |
| CEFBS_HasStdEnc_HasMips32, |
| CEFBS_HasStdEnc_HasMips32r6, |
| CEFBS_HasStdEnc_HasMips64, |
| CEFBS_HasStdEnc_HasMips64r6, |
| CEFBS_HasStdEnc_IsNotSoftFloat, |
| CEFBS_HasStdEnc_NotInMicroMips, |
| CEFBS_HasStdEnc_NotMips3, |
| CEFBS_HasStdEnc_NotMips4_32, |
| CEFBS_InMicroMips_HasDSP, |
| CEFBS_InMicroMips_HasDSPR2, |
| CEFBS_InMicroMips_HasDSPR3, |
| CEFBS_InMicroMips_HasEVA, |
| CEFBS_InMicroMips_HasMips32r6, |
| CEFBS_InMicroMips_IsNotSoftFloat, |
| CEFBS_InMicroMips_NotMips32r6, |
| CEFBS_IsFP64bit_IsNotSoftFloat, |
| CEFBS_IsGP32bit_NotInMicroMips, |
| CEFBS_NotFP64bit_IsNotSoftFloat, |
| CEFBS_NotInMips16Mode_HasDSP, |
| CEFBS_NotInMips16Mode_IsGP64bit, |
| CEFBS_NotInMips16Mode_IsNotSoftFloat, |
| CEFBS_NotInMips16Mode_IsPTR64bit, |
| CEFBS_HasMips3_NotMips64r6_NotCnMips, |
| CEFBS_HasMips64_HasCnMips_NotInMicroMips, |
| CEFBS_HasStdEnc_HasMSA_HasMips64, |
| CEFBS_HasStdEnc_HasMT_NotInMicroMips, |
| CEFBS_HasStdEnc_HasMips2_NotInMicroMips, |
| CEFBS_HasStdEnc_HasMips3_NotInMicroMips, |
| CEFBS_HasStdEnc_HasMips32_NotInMicroMips, |
| CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, |
| CEFBS_HasStdEnc_HasMips32r5_NotInMicroMips, |
| CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, |
| CEFBS_HasStdEnc_HasMips3_32_NotInMicroMips, |
| CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, |
| CEFBS_HasStdEnc_HasMips64r5_HasVirt, |
| CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, |
| CEFBS_HasStdEnc_IsFP64bit_NotMips4_32, |
| CEFBS_HasStdEnc_IsGP64bit_HasMips3, |
| CEFBS_HasStdEnc_IsGP64bit_HasMips32r2, |
| CEFBS_HasStdEnc_IsGP64bit_HasMips32r6, |
| CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, |
| CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, |
| CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat, |
| CEFBS_HasStdEnc_NotFP64bit_NotMips4_32, |
| CEFBS_HasStdEnc_NotInMicroMips_NoIndirectJumpGuards, |
| CEFBS_HasStdEnc_NotInMips16Mode_NotInMicroMips, |
| CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, |
| CEFBS_InMicroMips_HasMips32r5_HasVirt, |
| CEFBS_InMicroMips_HasMips32r6_HasGINV, |
| CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, |
| CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, |
| CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, |
| CEFBS_InMicroMips_NotMips32r6_HasDSP, |
| CEFBS_InMicroMips_NotMips32r6_HasEVA, |
| CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, |
| CEFBS_InMicroMips_NotMips32r6_NotMips64r6, |
| CEFBS_NotInMips16Mode_IsFP64bit_IsNotSoftFloat, |
| CEFBS_NotInMips16Mode_IsGP64bit_NotInMicroMips, |
| CEFBS_NotInMips16Mode_IsPTR64bit_NoIndirectJumpGuards, |
| CEFBS_NotInMips16Mode_IsPTR64bit_NotInMicroMips, |
| CEFBS_NotInMips16Mode_IsPTR64bit_UseIndirectJumpsHazard, |
| CEFBS_NotInMips16Mode_NotFP64bit_IsNotSoftFloat, |
| CEFBS_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, |
| CEFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips, |
| CEFBS_HasStdEnc_HasMips2_NotCnMips_NotInMicroMips, |
| CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, |
| CEFBS_HasStdEnc_HasMips3_IsNotSoftFloat_NotInMicroMips, |
| CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, |
| CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6, |
| CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, |
| CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6, |
| CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, |
| CEFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, |
| CEFBS_HasStdEnc_HasMips32r6_HasGINV_NotInMicroMips, |
| CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, |
| CEFBS_HasStdEnc_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, |
| CEFBS_HasStdEnc_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, |
| CEFBS_HasStdEnc_HasMips64_NotMips64r6_NotInMicroMips, |
| CEFBS_HasStdEnc_HasMips64r6_HasCRC_NotInMicroMips, |
| CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, |
| CEFBS_HasStdEnc_IsGP32bit_HasMips32r6_NotInMicroMips, |
| CEFBS_HasStdEnc_IsPTR32bit_HasMips32r6_NotInMicroMips, |
| CEFBS_HasStdEnc_IsPTR64bit_HasMips64r6_NotInMicroMips, |
| CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, |
| CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, |
| CEFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat, |
| CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, |
| CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, |
| CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4, |
| CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, |
| CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, |
| CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, |
| CEFBS_HasStdEnc_HasMips32r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, |
| CEFBS_HasStdEnc_HasMips32r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, |
| CEFBS_HasStdEnc_HasMips3_32_NotMips32r6_NotMips64r6_NotInMicroMips, |
| CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, |
| CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat, |
| CEFBS_HasStdEnc_HasMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, |
| CEFBS_HasStdEnc_HasMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, |
| CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, |
| CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips, |
| CEFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips, |
| CEFBS_HasStdEnc_IsFP64bit_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, |
| CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, |
| CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat, |
| CEFBS_HasStdEnc_IsGP64bit_HasMips64_NotMips64r6_NotInMicroMips, |
| CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, |
| CEFBS_HasStdEnc_NotFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips, |
| CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, |
| CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, |
| CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotCnMips_NotInMicroMips, |
| CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat_HasMadd4, |
| CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, |
| CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips, |
| CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, |
| CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat, |
| CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, |
| CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, |
| CEFBS_HasStdEnc_IsPTR32bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, |
| CEFBS_HasStdEnc_IsPTR64bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, |
| CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, |
| CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, |
| CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, |
| CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, |
| CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, |
| CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, |
| CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, |
| CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D, |
| CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, |
| CEFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, |
| CEFBS_HasStdEnc_IsFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, |
| CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, |
| CEFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, |
| CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, |
| CEFBS_HasStdEnc_NotFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, |
| CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, |
| CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, |
| CEFBS_HasStdEnc_IsGP64bit_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, |
| CEFBS_HasStdEnc_IsPTR64bit_HasMips3_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, |
| CEFBS_HasStdEnc_IsPTR64bit_HasMips32r2_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, |
| CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, |
| CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, |
| }; |
| |
| static constexpr FeatureBitset FeatureBitsets[] = { |
| {}, // CEFBS_None |
| {Feature_HasCnMipsBit, }, |
| {Feature_HasCnMipsPBit, }, |
| {Feature_HasDSPBit, }, |
| {Feature_HasDSPR2Bit, }, |
| {Feature_HasMSABit, }, |
| {Feature_HasMTBit, }, |
| {Feature_InMicroMipsBit, }, |
| {Feature_InMips16ModeBit, }, |
| {Feature_IsGP32bitBit, }, |
| {Feature_IsGP64bitBit, }, |
| {Feature_IsNotSoftFloatBit, }, |
| {Feature_NotCnMipsBit, }, |
| {Feature_NotInMips16ModeBit, }, |
| {Feature_HasDSPBit, Feature_NotInMicroMipsBit, }, |
| {Feature_HasStdEncBit, Feature_HasMSABit, }, |
| {Feature_HasStdEncBit, Feature_HasMips32Bit, }, |
| {Feature_HasStdEncBit, Feature_HasMips32r6Bit, }, |
| {Feature_HasStdEncBit, Feature_HasMips64Bit, }, |
| {Feature_HasStdEncBit, Feature_HasMips64r6Bit, }, |
| {Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, }, |
| {Feature_HasStdEncBit, Feature_NotInMicroMipsBit, }, |
| {Feature_HasStdEncBit, Feature_NotMips3Bit, }, |
| {Feature_HasStdEncBit, Feature_NotMips4_32Bit, }, |
| {Feature_InMicroMipsBit, Feature_HasDSPBit, }, |
| {Feature_InMicroMipsBit, Feature_HasDSPR2Bit, }, |
| {Feature_InMicroMipsBit, Feature_HasDSPR3Bit, }, |
| {Feature_InMicroMipsBit, Feature_HasEVABit, }, |
| {Feature_InMicroMipsBit, Feature_HasMips32r6Bit, }, |
| {Feature_InMicroMipsBit, Feature_IsNotSoftFloatBit, }, |
| {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, }, |
| {Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, }, |
| {Feature_IsGP32bitBit, Feature_NotInMicroMipsBit, }, |
| {Feature_NotFP64bitBit, Feature_IsNotSoftFloatBit, }, |
| {Feature_NotInMips16ModeBit, Feature_HasDSPBit, }, |
| {Feature_NotInMips16ModeBit, Feature_IsGP64bitBit, }, |
| {Feature_NotInMips16ModeBit, Feature_IsNotSoftFloatBit, }, |
| {Feature_NotInMips16ModeBit, Feature_IsPTR64bitBit, }, |
| {Feature_HasMips3Bit, Feature_NotMips64r6Bit, Feature_NotCnMipsBit, }, |
| {Feature_HasMips64Bit, Feature_HasCnMipsBit, Feature_NotInMicroMipsBit, }, |
| {Feature_HasStdEncBit, Feature_HasMSABit, Feature_HasMips64Bit, }, |
| {Feature_HasStdEncBit, Feature_HasMTBit, Feature_NotInMicroMipsBit, }, |
| {Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotInMicroMipsBit, }, |
| {Feature_HasStdEncBit, Feature_HasMips3Bit, Feature_NotInMicroMipsBit, }, |
| {Feature_HasStdEncBit, Feature_HasMips32Bit, Feature_NotInMicroMipsBit, }, |
| {Feature_HasStdEncBit, Feature_HasMips32r2Bit, Feature_NotInMicroMipsBit, }, |
| {Feature_HasStdEncBit, Feature_HasMips32r5Bit, Feature_NotInMicroMipsBit, }, |
| {Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_NotInMicroMipsBit, }, |
| {Feature_HasStdEncBit, Feature_HasMips3_32Bit, Feature_NotInMicroMipsBit, }, |
| {Feature_HasStdEncBit, Feature_HasMips64r2Bit, Feature_NotInMicroMipsBit, }, |
| {Feature_HasStdEncBit, Feature_HasMips64r5Bit, Feature_HasVirtBit, }, |
| {Feature_HasStdEncBit, Feature_HasMips64r6Bit, Feature_NotInMicroMipsBit, }, |
| {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NotMips4_32Bit, }, |
| {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips3Bit, }, |
| {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips32r2Bit, }, |
| {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips32r6Bit, }, |
| {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips64r6Bit, }, |
| {Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_IsNotSoftFloatBit, }, |
| {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_NotMips4_32Bit, }, |
| {Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_NoIndirectJumpGuardsBit, }, |
| {Feature_HasStdEncBit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, }, |
| {Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, |
| {Feature_InMicroMipsBit, Feature_HasMips32r5Bit, Feature_HasVirtBit, }, |
| {Feature_InMicroMipsBit, Feature_HasMips32r6Bit, Feature_HasGINVBit, }, |
| {Feature_InMicroMipsBit, Feature_HasMips32r6Bit, Feature_IsNotSoftFloatBit, }, |
| {Feature_InMicroMipsBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, }, |
| {Feature_InMicroMipsBit, Feature_NotFP64bitBit, Feature_IsNotSoftFloatBit, }, |
| {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_HasDSPBit, }, |
| {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_HasEVABit, }, |
| {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_IsNotSoftFloatBit, }, |
| {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, |
| {Feature_NotInMips16ModeBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, }, |
| {Feature_NotInMips16ModeBit, Feature_IsGP64bitBit, Feature_NotInMicroMipsBit, }, |
| {Feature_NotInMips16ModeBit, Feature_IsPTR64bitBit, Feature_NoIndirectJumpGuardsBit, }, |
| {Feature_NotInMips16ModeBit, Feature_IsPTR64bitBit, Feature_NotInMicroMipsBit, }, |
| {Feature_NotInMips16ModeBit, Feature_IsPTR64bitBit, Feature_UseIndirectJumpsHazardBit, }, |
| {Feature_NotInMips16ModeBit, Feature_NotFP64bitBit, Feature_IsNotSoftFloatBit, }, |
| {Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_UseIndirectJumpsHazardBit, }, |
| {Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| {Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotCnMipsBit, Feature_NotInMicroMipsBit, }, |
| {Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, |
| {Feature_HasStdEncBit, Feature_HasMips3Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| {Feature_HasStdEncBit, Feature_HasMips3Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, |
| {Feature_HasStdEncBit, Feature_HasMips32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, |
| {Feature_HasStdEncBit, Feature_HasMips32r2Bit, Feature_HasEVABit, Feature_NotInMicroMipsBit, }, |
| {Feature_HasStdEncBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, |
| {Feature_HasStdEncBit, Feature_HasMips32r5Bit, Feature_HasVirtBit, Feature_NotInMicroMipsBit, }, |
| {Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_HasCRCBit, Feature_NotInMicroMipsBit, }, |
| {Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_HasGINVBit, Feature_NotInMicroMipsBit, }, |
| {Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| {Feature_HasStdEncBit, Feature_HasMips3_32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| {Feature_HasStdEncBit, Feature_HasMips4_32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| {Feature_HasStdEncBit, Feature_HasMips64Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, |
| {Feature_HasStdEncBit, Feature_HasMips64r6Bit, Feature_HasCRCBit, Feature_NotInMicroMipsBit, }, |
| {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| {Feature_HasStdEncBit, Feature_IsGP32bitBit, Feature_HasMips32r6Bit, Feature_NotInMicroMipsBit, }, |
| {Feature_HasStdEncBit, Feature_IsPTR32bitBit, Feature_HasMips32r6Bit, Feature_NotInMicroMipsBit, }, |
| {Feature_HasStdEncBit, Feature_IsPTR64bitBit, Feature_HasMips64r6Bit, Feature_NotInMicroMipsBit, }, |
| {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| {Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, |
| {Feature_InMicroMipsBit, Feature_IsFP64bitBit, Feature_HasMips32r6Bit, Feature_IsNotSoftFloatBit, }, |
| {Feature_InMicroMipsBit, Feature_IsFP64bitBit, Feature_NotMips32r6Bit, Feature_IsNotSoftFloatBit, }, |
| {Feature_InMicroMipsBit, Feature_NotFP64bitBit, Feature_NotMips32r6Bit, Feature_IsNotSoftFloatBit, }, |
| {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMadd4Bit, }, |
| {Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, |
| {Feature_HasStdEncBit, Feature_HasMips3Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, |
| {Feature_HasStdEncBit, Feature_HasMips32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, |
| {Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_NoIndirectJumpGuardsBit, }, |
| {Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_UseIndirectJumpsHazardBit, }, |
| {Feature_HasStdEncBit, Feature_HasMips3_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, |
| {Feature_HasStdEncBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, |
| {Feature_HasStdEncBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, }, |
| {Feature_HasStdEncBit, Feature_HasMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_NoIndirectJumpGuardsBit, }, |
| {Feature_HasStdEncBit, Feature_HasMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_UseIndirectJumpsHazardBit, }, |
| {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips3_32Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips3_32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips4_32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, }, |
| {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips64Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, |
| {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips4_32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| {Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| {Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotCnMipsBit, Feature_NotInMicroMipsBit, }, |
| {Feature_InMicroMipsBit, Feature_NotFP64bitBit, Feature_NotMips32r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMadd4Bit, }, |
| {Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| {Feature_HasStdEncBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_HasEVABit, Feature_NotInMicroMipsBit, }, |
| {Feature_HasStdEncBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, }, |
| {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, |
| {Feature_HasStdEncBit, Feature_IsPTR32bitBit, Feature_HasMips2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, |
| {Feature_HasStdEncBit, Feature_IsPTR64bitBit, Feature_HasMips2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, |
| {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| {Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_NoIndirectJumpGuardsBit, }, |
| {Feature_HasStdEncBit, Feature_HasMips3Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_NoIndirectJumpGuardsBit, }, |
| {Feature_HasStdEncBit, Feature_HasMips32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_UseIndirectJumpsHazardBit, }, |
| {Feature_HasStdEncBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_UseIndirectJumpsHazardBit, }, |
| {Feature_HasStdEncBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMadd4Bit, Feature_NotInMicroMipsBit, }, |
| {Feature_HasStdEncBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_HasMadd4Bit, }, |
| {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMips3DBit, }, |
| {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips5_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips5_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMadd4Bit, Feature_NotInMicroMipsBit, }, |
| {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_HasMadd4Bit, }, |
| {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_IsFP64bitBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
| {Feature_HasStdEncBit, Feature_IsPTR64bitBit, Feature_HasMips3Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_NoIndirectJumpGuardsBit, }, |
| {Feature_HasStdEncBit, Feature_IsPTR64bitBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_UseIndirectJumpsHazardBit, }, |
| {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMadd4Bit, Feature_NotInMicroMipsBit, }, |
| {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_HasMadd4Bit, }, |
| }; |
| #endif // NDEBUG |
| |
| void verifyInstructionPredicates( |
| unsigned Opcode, const FeatureBitset &Features) { |
| #ifndef NDEBUG |
| static uint8_t RequiredFeaturesRefs[] = { |
| CEFBS_None, // PHI = 0 |
| CEFBS_None, // INLINEASM = 1 |
| CEFBS_None, // INLINEASM_BR = 2 |
| CEFBS_None, // CFI_INSTRUCTION = 3 |
| CEFBS_None, // EH_LABEL = 4 |
| CEFBS_None, // GC_LABEL = 5 |
| CEFBS_None, // ANNOTATION_LABEL = 6 |
| CEFBS_None, // KILL = 7 |
| CEFBS_None, // EXTRACT_SUBREG = 8 |
| CEFBS_None, // INSERT_SUBREG = 9 |
| CEFBS_None, // IMPLICIT_DEF = 10 |
| CEFBS_None, // SUBREG_TO_REG = 11 |
| CEFBS_None, // COPY_TO_REGCLASS = 12 |
| CEFBS_None, // DBG_VALUE = 13 |
| CEFBS_None, // DBG_VALUE_LIST = 14 |
| CEFBS_None, // DBG_INSTR_REF = 15 |
| CEFBS_None, // DBG_PHI = 16 |
| CEFBS_None, // DBG_LABEL = 17 |
| CEFBS_None, // REG_SEQUENCE = 18 |
| CEFBS_None, // COPY = 19 |
| CEFBS_None, // BUNDLE = 20 |
| CEFBS_None, // LIFETIME_START = 21 |
| CEFBS_None, // LIFETIME_END = 22 |
| CEFBS_None, // PSEUDO_PROBE = 23 |
| CEFBS_None, // ARITH_FENCE = 24 |
| CEFBS_None, // STACKMAP = 25 |
| CEFBS_None, // FENTRY_CALL = 26 |
| CEFBS_None, // PATCHPOINT = 27 |
| CEFBS_None, // LOAD_STACK_GUARD = 28 |
| CEFBS_None, // PREALLOCATED_SETUP = 29 |
| CEFBS_None, // PREALLOCATED_ARG = 30 |
| CEFBS_None, // STATEPOINT = 31 |
| CEFBS_None, // LOCAL_ESCAPE = 32 |
| CEFBS_None, // FAULTING_OP = 33 |
| CEFBS_None, // PATCHABLE_OP = 34 |
| CEFBS_None, // PATCHABLE_FUNCTION_ENTER = 35 |
| CEFBS_None, // PATCHABLE_RET = 36 |
| CEFBS_None, // PATCHABLE_FUNCTION_EXIT = 37 |
| CEFBS_None, // PATCHABLE_TAIL_CALL = 38 |
| CEFBS_None, // PATCHABLE_EVENT_CALL = 39 |
| CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL = 40 |
| CEFBS_None, // ICALL_BRANCH_FUNNEL = 41 |
| CEFBS_None, // MEMBARRIER = 42 |
| CEFBS_None, // G_ASSERT_SEXT = 43 |
| CEFBS_None, // G_ASSERT_ZEXT = 44 |
| CEFBS_None, // G_ASSERT_ALIGN = 45 |
| CEFBS_None, // G_ADD = 46 |
| CEFBS_None, // G_SUB = 47 |
| CEFBS_None, // G_MUL = 48 |
| CEFBS_None, // G_SDIV = 49 |
| CEFBS_None, // G_UDIV = 50 |
| CEFBS_None, // G_SREM = 51 |
| CEFBS_None, // G_UREM = 52 |
| CEFBS_None, // G_SDIVREM = 53 |
| CEFBS_None, // G_UDIVREM = 54 |
| CEFBS_None, // G_AND = 55 |
| CEFBS_None, // G_OR = 56 |
| CEFBS_None, // G_XOR = 57 |
| CEFBS_None, // G_IMPLICIT_DEF = 58 |
| CEFBS_None, // G_PHI = 59 |
| CEFBS_None, // G_FRAME_INDEX = 60 |
| CEFBS_None, // G_GLOBAL_VALUE = 61 |
| CEFBS_None, // G_EXTRACT = 62 |
| CEFBS_None, // G_UNMERGE_VALUES = 63 |
| CEFBS_None, // G_INSERT = 64 |
| CEFBS_None, // G_MERGE_VALUES = 65 |
| CEFBS_None, // G_BUILD_VECTOR = 66 |
| CEFBS_None, // G_BUILD_VECTOR_TRUNC = 67 |
| CEFBS_None, // G_CONCAT_VECTORS = 68 |
| CEFBS_None, // G_PTRTOINT = 69 |
| CEFBS_None, // G_INTTOPTR = 70 |
| CEFBS_None, // G_BITCAST = 71 |
| CEFBS_None, // G_FREEZE = 72 |
| CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND = 73 |
| CEFBS_None, // G_INTRINSIC_TRUNC = 74 |
| CEFBS_None, // G_INTRINSIC_ROUND = 75 |
| CEFBS_None, // G_INTRINSIC_LRINT = 76 |
| CEFBS_None, // G_INTRINSIC_ROUNDEVEN = 77 |
| CEFBS_None, // G_READCYCLECOUNTER = 78 |
| CEFBS_None, // G_LOAD = 79 |
| CEFBS_None, // G_SEXTLOAD = 80 |
| CEFBS_None, // G_ZEXTLOAD = 81 |
| CEFBS_None, // G_INDEXED_LOAD = 82 |
| CEFBS_None, // G_INDEXED_SEXTLOAD = 83 |
| CEFBS_None, // G_INDEXED_ZEXTLOAD = 84 |
| CEFBS_None, // G_STORE = 85 |
| CEFBS_None, // G_INDEXED_STORE = 86 |
| CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS = 87 |
| CEFBS_None, // G_ATOMIC_CMPXCHG = 88 |
| CEFBS_None, // G_ATOMICRMW_XCHG = 89 |
| CEFBS_None, // G_ATOMICRMW_ADD = 90 |
| CEFBS_None, // G_ATOMICRMW_SUB = 91 |
| CEFBS_None, // G_ATOMICRMW_AND = 92 |
| CEFBS_None, // G_ATOMICRMW_NAND = 93 |
| CEFBS_None, // G_ATOMICRMW_OR = 94 |
| CEFBS_None, // G_ATOMICRMW_XOR = 95 |
| CEFBS_None, // G_ATOMICRMW_MAX = 96 |
| CEFBS_None, // G_ATOMICRMW_MIN = 97 |
| CEFBS_None, // G_ATOMICRMW_UMAX = 98 |
| CEFBS_None, // G_ATOMICRMW_UMIN = 99 |
| CEFBS_None, // G_ATOMICRMW_FADD = 100 |
| CEFBS_None, // G_ATOMICRMW_FSUB = 101 |
| CEFBS_None, // G_ATOMICRMW_FMAX = 102 |
| CEFBS_None, // G_ATOMICRMW_FMIN = 103 |
| CEFBS_None, // G_ATOMICRMW_UINC_WRAP = 104 |
| CEFBS_None, // G_ATOMICRMW_UDEC_WRAP = 105 |
| CEFBS_None, // G_FENCE = 106 |
| CEFBS_None, // G_BRCOND = 107 |
| CEFBS_None, // G_BRINDIRECT = 108 |
| CEFBS_None, // G_INVOKE_REGION_START = 109 |
| CEFBS_None, // G_INTRINSIC = 110 |
| CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS = 111 |
| CEFBS_None, // G_ANYEXT = 112 |
| CEFBS_None, // G_TRUNC = 113 |
| CEFBS_None, // G_CONSTANT = 114 |
| CEFBS_None, // G_FCONSTANT = 115 |
| CEFBS_None, // G_VASTART = 116 |
| CEFBS_None, // G_VAARG = 117 |
| CEFBS_None, // G_SEXT = 118 |
| CEFBS_None, // G_SEXT_INREG = 119 |
| CEFBS_None, // G_ZEXT = 120 |
| CEFBS_None, // G_SHL = 121 |
| CEFBS_None, // G_LSHR = 122 |
| CEFBS_None, // G_ASHR = 123 |
| CEFBS_None, // G_FSHL = 124 |
| CEFBS_None, // G_FSHR = 125 |
| CEFBS_None, // G_ROTR = 126 |
| CEFBS_None, // G_ROTL = 127 |
| CEFBS_None, // G_ICMP = 128 |
| CEFBS_None, // G_FCMP = 129 |
| CEFBS_None, // G_SELECT = 130 |
| CEFBS_None, // G_UADDO = 131 |
| CEFBS_None, // G_UADDE = 132 |
| CEFBS_None, // G_USUBO = 133 |
| CEFBS_None, // G_USUBE = 134 |
| CEFBS_None, // G_SADDO = 135 |
| CEFBS_None, // G_SADDE = 136 |
| CEFBS_None, // G_SSUBO = 137 |
| CEFBS_None, // G_SSUBE = 138 |
| CEFBS_None, // G_UMULO = 139 |
| CEFBS_None, // G_SMULO = 140 |
| CEFBS_None, // G_UMULH = 141 |
| CEFBS_None, // G_SMULH = 142 |
| CEFBS_None, // G_UADDSAT = 143 |
| CEFBS_None, // G_SADDSAT = 144 |
| CEFBS_None, // G_USUBSAT = 145 |
| CEFBS_None, // G_SSUBSAT = 146 |
| CEFBS_None, // G_USHLSAT = 147 |
| CEFBS_None, // G_SSHLSAT = 148 |
| CEFBS_None, // G_SMULFIX = 149 |
| CEFBS_None, // G_UMULFIX = 150 |
| CEFBS_None, // G_SMULFIXSAT = 151 |
| CEFBS_None, // G_UMULFIXSAT = 152 |
| CEFBS_None, // G_SDIVFIX = 153 |
| CEFBS_None, // G_UDIVFIX = 154 |
| CEFBS_None, // G_SDIVFIXSAT = 155 |
| CEFBS_None, // G_UDIVFIXSAT = 156 |
| CEFBS_None, // G_FADD = 157 |
| CEFBS_None, // G_FSUB = 158 |
| CEFBS_None, // G_FMUL = 159 |
| CEFBS_None, // G_FMA = 160 |
| CEFBS_None, // G_FMAD = 161 |
| CEFBS_None, // G_FDIV = 162 |
| CEFBS_None, // G_FREM = 163 |
| CEFBS_None, // G_FPOW = 164 |
| CEFBS_None, // G_FPOWI = 165 |
| CEFBS_None, // G_FEXP = 166 |
| CEFBS_None, // G_FEXP2 = 167 |
| CEFBS_None, // G_FLOG = 168 |
| CEFBS_None, // G_FLOG2 = 169 |
| CEFBS_None, // G_FLOG10 = 170 |
| CEFBS_None, // G_FNEG = 171 |
| CEFBS_None, // G_FPEXT = 172 |
| CEFBS_None, // G_FPTRUNC = 173 |
| CEFBS_None, // G_FPTOSI = 174 |
| CEFBS_None, // G_FPTOUI = 175 |
| CEFBS_None, // G_SITOFP = 176 |
| CEFBS_None, // G_UITOFP = 177 |
| CEFBS_None, // G_FABS = 178 |
| CEFBS_None, // G_FCOPYSIGN = 179 |
| CEFBS_None, // G_IS_FPCLASS = 180 |
| CEFBS_None, // G_FCANONICALIZE = 181 |
| CEFBS_None, // G_FMINNUM = 182 |
| CEFBS_None, // G_FMAXNUM = 183 |
| CEFBS_None, // G_FMINNUM_IEEE = 184 |
| CEFBS_None, // G_FMAXNUM_IEEE = 185 |
| CEFBS_None, // G_FMINIMUM = 186 |
| CEFBS_None, // G_FMAXIMUM = 187 |
| CEFBS_None, // G_PTR_ADD = 188 |
| CEFBS_None, // G_PTRMASK = 189 |
| CEFBS_None, // G_SMIN = 190 |
| CEFBS_None, // G_SMAX = 191 |
| CEFBS_None, // G_UMIN = 192 |
| CEFBS_None, // G_UMAX = 193 |
| CEFBS_None, // G_ABS = 194 |
| CEFBS_None, // G_LROUND = 195 |
| CEFBS_None, // G_LLROUND = 196 |
| CEFBS_None, // G_BR = 197 |
| CEFBS_None, // G_BRJT = 198 |
| CEFBS_None, // G_INSERT_VECTOR_ELT = 199 |
| CEFBS_None, // G_EXTRACT_VECTOR_ELT = 200 |
| CEFBS_None, // G_SHUFFLE_VECTOR = 201 |
| CEFBS_None, // G_CTTZ = 202 |
| CEFBS_None, // G_CTTZ_ZERO_UNDEF = 203 |
| CEFBS_None, // G_CTLZ = 204 |
| CEFBS_None, // G_CTLZ_ZERO_UNDEF = 205 |
| CEFBS_None, // G_CTPOP = 206 |
| CEFBS_None, // G_BSWAP = 207 |
| CEFBS_None, // G_BITREVERSE = 208 |
| CEFBS_None, // G_FCEIL = 209 |
| CEFBS_None, // G_FCOS = 210 |
| CEFBS_None, // G_FSIN = 211 |
| CEFBS_None, // G_FSQRT = 212 |
| CEFBS_None, // G_FFLOOR = 213 |
| CEFBS_None, // G_FRINT = 214 |
| CEFBS_None, // G_FNEARBYINT = 215 |
| CEFBS_None, // G_ADDRSPACE_CAST = 216 |
| CEFBS_None, // G_BLOCK_ADDR = 217 |
| CEFBS_None, // G_JUMP_TABLE = 218 |
| CEFBS_None, // G_DYN_STACKALLOC = 219 |
| CEFBS_None, // G_STRICT_FADD = 220 |
| CEFBS_None, // G_STRICT_FSUB = 221 |
| CEFBS_None, // G_STRICT_FMUL = 222 |
| CEFBS_None, // G_STRICT_FDIV = 223 |
| CEFBS_None, // G_STRICT_FREM = 224 |
| CEFBS_None, // G_STRICT_FMA = 225 |
| CEFBS_None, // G_STRICT_FSQRT = 226 |
| CEFBS_None, // G_READ_REGISTER = 227 |
| CEFBS_None, // G_WRITE_REGISTER = 228 |
| CEFBS_None, // G_MEMCPY = 229 |
| CEFBS_None, // G_MEMCPY_INLINE = 230 |
| CEFBS_None, // G_MEMMOVE = 231 |
| CEFBS_None, // G_MEMSET = 232 |
| CEFBS_None, // G_BZERO = 233 |
| CEFBS_None, // G_VECREDUCE_SEQ_FADD = 234 |
| CEFBS_None, // G_VECREDUCE_SEQ_FMUL = 235 |
| CEFBS_None, // G_VECREDUCE_FADD = 236 |
| CEFBS_None, // G_VECREDUCE_FMUL = 237 |
| CEFBS_None, // G_VECREDUCE_FMAX = 238 |
| CEFBS_None, // G_VECREDUCE_FMIN = 239 |
| CEFBS_None, // G_VECREDUCE_ADD = 240 |
| CEFBS_None, // G_VECREDUCE_MUL = 241 |
| CEFBS_None, // G_VECREDUCE_AND = 242 |
| CEFBS_None, // G_VECREDUCE_OR = 243 |
| CEFBS_None, // G_VECREDUCE_XOR = 244 |
| CEFBS_None, // G_VECREDUCE_SMAX = 245 |
| CEFBS_None, // G_VECREDUCE_SMIN = 246 |
| CEFBS_None, // G_VECREDUCE_UMAX = 247 |
| CEFBS_None, // G_VECREDUCE_UMIN = 248 |
| CEFBS_None, // G_SBFX = 249 |
| CEFBS_None, // G_UBFX = 250 |
| CEFBS_None, // ABSMacro = 251 |
| CEFBS_None, // ADJCALLSTACKDOWN = 252 |
| CEFBS_None, // ADJCALLSTACKUP = 253 |
| CEFBS_HasStdEnc_HasMSA, // AND_V_D_PSEUDO = 254 |
| CEFBS_HasStdEnc_HasMSA, // AND_V_H_PSEUDO = 255 |
| CEFBS_HasStdEnc_HasMSA, // AND_V_W_PSEUDO = 256 |
| CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I16 = 257 |
| CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I16_POSTRA = 258 |
| CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I32 = 259 |
| CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I32_POSTRA = 260 |
| CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I64 = 261 |
| CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I64_POSTRA = 262 |
| CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I8 = 263 |
| CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I8_POSTRA = 264 |
| CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I16 = 265 |
| CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I16_POSTRA = 266 |
| CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I32 = 267 |
| CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I32_POSTRA = 268 |
| CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I64 = 269 |
| CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I64_POSTRA = 270 |
| CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I8 = 271 |
| CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I8_POSTRA = 272 |
| CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I16 = 273 |
| CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I16_POSTRA = 274 |
| CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I32 = 275 |
| CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I32_POSTRA = 276 |
| CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I64 = 277 |
| CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I64_POSTRA = 278 |
| CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I8 = 279 |
| CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I8_POSTRA = 280 |
| CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I16 = 281 |
| CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I16_POSTRA = 282 |
| CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I32 = 283 |
| CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I32_POSTRA = 284 |
| CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I64 = 285 |
| CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I64_POSTRA = 286 |
| CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I8 = 287 |
| CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I8_POSTRA = 288 |
| CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I16 = 289 |
| CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I16_POSTRA = 290 |
| CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I32 = 291 |
| CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I32_POSTRA = 292 |
| CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I64 = 293 |
| CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I64_POSTRA = 294 |
| CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I8 = 295 |
| CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I8_POSTRA = 296 |
| CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I16 = 297 |
| CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I16_POSTRA = 298 |
| CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I32 = 299 |
| CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I32_POSTRA = 300 |
| CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I64 = 301 |
| CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I64_POSTRA = 302 |
| CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I8 = 303 |
| CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I8_POSTRA = 304 |
| CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I16 = 305 |
| CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I16_POSTRA = 306 |
| CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I32 = 307 |
| CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I32_POSTRA = 308 |
| CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I64 = 309 |
| CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I64_POSTRA = 310 |
| CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I8 = 311 |
| CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I8_POSTRA = 312 |
| CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I16 = 313 |
| CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I16_POSTRA = 314 |
| CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I32 = 315 |
| CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I32_POSTRA = 316 |
| CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I64 = 317 |
| CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I64_POSTRA = 318 |
| CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I8 = 319 |
| CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I8_POSTRA = 320 |
| CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I16 = 321 |
| CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I16_POSTRA = 322 |
| CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I32 = 323 |
| CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I32_POSTRA = 324 |
| CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I64 = 325 |
| CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I64_POSTRA = 326 |
| CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I8 = 327 |
| CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I8_POSTRA = 328 |
| CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I16 = 329 |
| CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I16_POSTRA = 330 |
| CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I32 = 331 |
| CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I32_POSTRA = 332 |
| CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I64 = 333 |
| CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I64_POSTRA = 334 |
| CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I8 = 335 |
| CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I8_POSTRA = 336 |
| CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I16 = 337 |
| CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I16_POSTRA = 338 |
| CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I32 = 339 |
| CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I32_POSTRA = 340 |
| CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I64 = 341 |
| CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I64_POSTRA = 342 |
| CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I8 = 343 |
| CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I8_POSTRA = 344 |
| CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I16 = 345 |
| CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I16_POSTRA = 346 |
| CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I32 = 347 |
| CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I32_POSTRA = 348 |
| CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I64 = 349 |
| CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I64_POSTRA = 350 |
| CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I8 = 351 |
| CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I8_POSTRA = 352 |
| CEFBS_HasStdEnc_NotInMicroMips, // B = 353 |
| CEFBS_HasStdEnc_NotInMicroMips, // BAL_BR = 354 |
| CEFBS_InMicroMips_NotMips32r6, // BAL_BR_MM = 355 |
| CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BEQLImmMacro = 356 |
| CEFBS_None, // BGE = 357 |
| CEFBS_None, // BGEImmMacro = 358 |
| CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGEL = 359 |
| CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGELImmMacro = 360 |
| CEFBS_None, // BGEU = 361 |
| CEFBS_None, // BGEUImmMacro = 362 |
| CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGEUL = 363 |
| CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGEULImmMacro = 364 |
| CEFBS_None, // BGT = 365 |
| CEFBS_None, // BGTImmMacro = 366 |
| CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGTL = 367 |
| CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGTLImmMacro = 368 |
| CEFBS_None, // BGTU = 369 |
| CEFBS_None, // BGTUImmMacro = 370 |
| CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGTUL = 371 |
| CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGTULImmMacro = 372 |
| CEFBS_None, // BLE = 373 |
| CEFBS_None, // BLEImmMacro = 374 |
| CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLEL = 375 |
| CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLELImmMacro = 376 |
| CEFBS_None, // BLEU = 377 |
| CEFBS_None, // BLEUImmMacro = 378 |
| CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLEUL = 379 |
| CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLEULImmMacro = 380 |
| CEFBS_None, // BLT = 381 |
| CEFBS_None, // BLTImmMacro = 382 |
| CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLTL = 383 |
| CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLTLImmMacro = 384 |
| CEFBS_None, // BLTU = 385 |
| CEFBS_None, // BLTUImmMacro = 386 |
| CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLTUL = 387 |
| CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLTULImmMacro = 388 |
| CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BNELImmMacro = 389 |
| CEFBS_None, // BPOSGE32_PSEUDO = 390 |
| CEFBS_HasStdEnc_HasMSA, // BSEL_D_PSEUDO = 391 |
| CEFBS_HasStdEnc_HasMSA, // BSEL_FD_PSEUDO = 392 |
| CEFBS_HasStdEnc_HasMSA, // BSEL_FW_PSEUDO = 393 |
| CEFBS_HasStdEnc_HasMSA, // BSEL_H_PSEUDO = 394 |
| CEFBS_HasStdEnc_HasMSA, // BSEL_W_PSEUDO = 395 |
| CEFBS_InMicroMips_NotMips32r6, // B_MM = 396 |
| CEFBS_None, // B_MMR6_Pseudo = 397 |
| CEFBS_InMicroMips, // B_MM_Pseudo = 398 |
| CEFBS_None, // BeqImm = 399 |
| CEFBS_None, // BneImm = 400 |
| CEFBS_InMips16Mode, // BteqzT8CmpX16 = 401 |
| CEFBS_InMips16Mode, // BteqzT8CmpiX16 = 402 |
| CEFBS_InMips16Mode, // BteqzT8SltX16 = 403 |
| CEFBS_InMips16Mode, // BteqzT8SltiX16 = 404 |
| CEFBS_InMips16Mode, // BteqzT8SltiuX16 = 405 |
| CEFBS_InMips16Mode, // BteqzT8SltuX16 = 406 |
| CEFBS_InMips16Mode, // BtnezT8CmpX16 = 407 |
| CEFBS_InMips16Mode, // BtnezT8CmpiX16 = 408 |
| CEFBS_InMips16Mode, // BtnezT8SltX16 = 409 |
| CEFBS_InMips16Mode, // BtnezT8SltiX16 = 410 |
| CEFBS_InMips16Mode, // BtnezT8SltiuX16 = 411 |
| CEFBS_InMips16Mode, // BtnezT8SltuX16 = 412 |
| CEFBS_NotInMips16Mode_NotFP64bit_IsNotSoftFloat, // BuildPairF64 = 413 |
| CEFBS_NotInMips16Mode_IsFP64bit_IsNotSoftFloat, // BuildPairF64_64 = 414 |
| CEFBS_HasMT, // CFTC1 = 415 |
| CEFBS_InMips16Mode, // CONSTPOOL_ENTRY = 416 |
| CEFBS_HasStdEnc_HasMSA, // COPY_FD_PSEUDO = 417 |
| CEFBS_HasStdEnc_HasMSA, // COPY_FW_PSEUDO = 418 |
| CEFBS_HasMT, // CTTC1 = 419 |
| CEFBS_InMips16Mode, // Constant32 = 420 |
| CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // DMULImmMacro = 421 |
| CEFBS_HasMips3_NotMips64r6_NotCnMips, // DMULMacro = 422 |
| CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // DMULOMacro = 423 |
| CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // DMULOUMacro = 424 |
| CEFBS_HasStdEnc_HasMips64, // DROL = 425 |
| CEFBS_HasStdEnc_HasMips64, // DROLImm = 426 |
| CEFBS_HasStdEnc_HasMips64, // DROR = 427 |
| CEFBS_HasStdEnc_HasMips64, // DRORImm = 428 |
| CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DSDivIMacro = 429 |
| CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DSDivMacro = 430 |
| CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DSRemIMacro = 431 |
| CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DSRemMacro = 432 |
| CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DUDivIMacro = 433 |
| CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DUDivMacro = 434 |
| CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DURemIMacro = 435 |
| CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DURemMacro = 436 |
| CEFBS_NotInMips16Mode, // ERet = 437 |
| CEFBS_NotInMips16Mode_NotFP64bit_IsNotSoftFloat, // ExtractElementF64 = 438 |
| CEFBS_NotInMips16Mode_IsFP64bit_IsNotSoftFloat, // ExtractElementF64_64 = 439 |
| CEFBS_HasStdEnc_HasMSA, // FABS_D = 440 |
| CEFBS_HasStdEnc_HasMSA, // FABS_W = 441 |
| CEFBS_HasStdEnc_HasMSA, // FEXP2_D_1_PSEUDO = 442 |
| CEFBS_HasStdEnc_HasMSA, // FEXP2_W_1_PSEUDO = 443 |
| CEFBS_HasStdEnc_HasMSA, // FILL_FD_PSEUDO = 444 |
| CEFBS_HasStdEnc_HasMSA, // FILL_FW_PSEUDO = 445 |
| CEFBS_InMips16Mode, // GotPrologue16 = 446 |
| CEFBS_HasStdEnc_HasMSA, // INSERT_B_VIDX64_PSEUDO = 447 |
| CEFBS_HasStdEnc_HasMSA, // INSERT_B_VIDX_PSEUDO = 448 |
| CEFBS_HasStdEnc_HasMSA, // INSERT_D_VIDX64_PSEUDO = 449 |
| CEFBS_HasStdEnc_HasMSA, // INSERT_D_VIDX_PSEUDO = 450 |
| CEFBS_HasStdEnc_HasMSA, // INSERT_FD_PSEUDO = 451 |
| CEFBS_HasStdEnc_HasMSA, // INSERT_FD_VIDX64_PSEUDO = 452 |
| CEFBS_HasStdEnc_HasMSA, // INSERT_FD_VIDX_PSEUDO = 453 |
| CEFBS_HasStdEnc_HasMSA, // INSERT_FW_PSEUDO = 454 |
| CEFBS_HasStdEnc_HasMSA, // INSERT_FW_VIDX64_PSEUDO = 455 |
| CEFBS_HasStdEnc_HasMSA, // INSERT_FW_VIDX_PSEUDO = 456 |
| CEFBS_HasStdEnc_HasMSA, // INSERT_H_VIDX64_PSEUDO = 457 |
| CEFBS_HasStdEnc_HasMSA, // INSERT_H_VIDX_PSEUDO = 458 |
| CEFBS_HasStdEnc_HasMSA, // INSERT_W_VIDX64_PSEUDO = 459 |
| CEFBS_HasStdEnc_HasMSA, // INSERT_W_VIDX_PSEUDO = 460 |
| CEFBS_NotInMips16Mode_IsPTR64bit_NoIndirectJumpGuards, // JALR64Pseudo = 461 |
| CEFBS_NotInMips16Mode_IsPTR64bit_UseIndirectJumpsHazard, // JALRHB64Pseudo = 462 |
| CEFBS_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // JALRHBPseudo = 463 |
| CEFBS_HasStdEnc_NotInMicroMips_NoIndirectJumpGuards, // JALRPseudo = 464 |
| CEFBS_InMicroMips_HasMips32r6, // JAL_MMR6 = 465 |
| CEFBS_None, // JalOneReg = 466 |
| CEFBS_None, // JalTwoReg = 467 |
| CEFBS_HasStdEnc_NotMips3, // LDMacro = 468 |
| CEFBS_NotInMips16Mode, // LDR_D = 469 |
| CEFBS_NotInMips16Mode, // LDR_W = 470 |
| CEFBS_HasMSA, // LD_F16 = 471 |
| CEFBS_NotInMips16Mode, // LOAD_ACC128 = 472 |
| CEFBS_NotInMips16Mode, // LOAD_ACC64 = 473 |
| CEFBS_NotInMips16Mode, // LOAD_ACC64DSP = 474 |
| CEFBS_NotInMips16Mode, // LOAD_CCOND_DSP = 475 |
| CEFBS_NotInMips16Mode, // LONG_BRANCH_ADDiu = 476 |
| CEFBS_NotInMips16Mode, // LONG_BRANCH_ADDiu2Op = 477 |
| CEFBS_NotInMips16Mode_IsGP64bit, // LONG_BRANCH_DADDiu = 478 |
| CEFBS_NotInMips16Mode_IsGP64bit, // LONG_BRANCH_DADDiu2Op = 479 |
| CEFBS_NotInMips16Mode, // LONG_BRANCH_LUi = 480 |
| CEFBS_NotInMips16Mode, // LONG_BRANCH_LUi2Op = 481 |
| CEFBS_NotInMips16Mode_IsGP64bit, // LONG_BRANCH_LUi2Op_64 = 482 |
| CEFBS_InMicroMips, // LWM_MM = 483 |
| CEFBS_None, // LoadAddrImm32 = 484 |
| CEFBS_None, // LoadAddrImm64 = 485 |
| CEFBS_None, // LoadAddrReg32 = 486 |
| CEFBS_None, // LoadAddrReg64 = 487 |
| CEFBS_None, // LoadImm32 = 488 |
| CEFBS_None, // LoadImm64 = 489 |
| CEFBS_IsFP64bit_IsNotSoftFloat, // LoadImmDoubleFGR = 490 |
| CEFBS_NotFP64bit_IsNotSoftFloat, // LoadImmDoubleFGR_32 = 491 |
| CEFBS_None, // LoadImmDoubleGPR = 492 |
| CEFBS_IsNotSoftFloat, // LoadImmSingleFGR = 493 |
| CEFBS_None, // LoadImmSingleGPR = 494 |
| CEFBS_InMips16Mode, // LwConstant32 = 495 |
| CEFBS_HasMT, // MFTACX = 496 |
| CEFBS_HasMT, // MFTC0 = 497 |
| CEFBS_HasMT, // MFTC1 = 498 |
| CEFBS_HasMT, // MFTDSP = 499 |
| CEFBS_HasMT, // MFTGPR = 500 |
| CEFBS_HasMT, // MFTHC1 = 501 |
| CEFBS_HasMT, // MFTHI = 502 |
| CEFBS_HasMT, // MFTLO = 503 |
| CEFBS_None, // MIPSeh_return32 = 504 |
| CEFBS_None, // MIPSeh_return64 = 505 |
| CEFBS_HasMSA, // MSA_FP_EXTEND_D_PSEUDO = 506 |
| CEFBS_HasMSA, // MSA_FP_EXTEND_W_PSEUDO = 507 |
| CEFBS_HasMSA, // MSA_FP_ROUND_D_PSEUDO = 508 |
| CEFBS_HasMSA, // MSA_FP_ROUND_W_PSEUDO = 509 |
| CEFBS_HasMT, // MTTACX = 510 |
| CEFBS_HasMT, // MTTC0 = 511 |
| CEFBS_HasMT, // MTTC1 = 512 |
| CEFBS_HasMT, // MTTDSP = 513 |
| CEFBS_HasMT, // MTTGPR = 514 |
| CEFBS_HasMT, // MTTHC1 = 515 |
| CEFBS_HasMT, // MTTHI = 516 |
| CEFBS_HasMT, // MTTLO = 517 |
| CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // MULImmMacro = 518 |
| CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // MULOMacro = 519 |
| CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // MULOUMacro = 520 |
| CEFBS_InMips16Mode, // MultRxRy16 = 521 |
| CEFBS_InMips16Mode, // MultRxRyRz16 = 522 |
| CEFBS_InMips16Mode, // MultuRxRy16 = 523 |
| CEFBS_InMips16Mode, // MultuRxRyRz16 = 524 |
| CEFBS_HasStdEnc_NotInMicroMips, // NOP = 525 |
| CEFBS_IsGP32bit, // NORImm = 526 |
| CEFBS_IsGP64bit, // NORImm64 = 527 |
| CEFBS_HasStdEnc_HasMSA, // NOR_V_D_PSEUDO = 528 |
| CEFBS_HasStdEnc_HasMSA, // NOR_V_H_PSEUDO = 529 |
| CEFBS_HasStdEnc_HasMSA, // NOR_V_W_PSEUDO = 530 |
| CEFBS_HasStdEnc_HasMSA, // OR_V_D_PSEUDO = 531 |
| CEFBS_HasStdEnc_HasMSA, // OR_V_H_PSEUDO = 532 |
| CEFBS_HasStdEnc_HasMSA, // OR_V_W_PSEUDO = 533 |
| CEFBS_HasDSP, // PseudoCMPU_EQ_QB = 534 |
| CEFBS_HasDSP, // PseudoCMPU_LE_QB = 535 |
| CEFBS_HasDSP, // PseudoCMPU_LT_QB = 536 |
| CEFBS_HasDSP, // PseudoCMP_EQ_PH = 537 |
| CEFBS_HasDSP, // PseudoCMP_LE_PH = 538 |
| CEFBS_HasDSP, // PseudoCMP_LT_PH = 539 |
| CEFBS_NotInMips16Mode_IsNotSoftFloat, // PseudoCVT_D32_W = 540 |
| CEFBS_NotInMips16Mode_IsNotSoftFloat, // PseudoCVT_D64_L = 541 |
| CEFBS_NotInMips16Mode_IsNotSoftFloat, // PseudoCVT_D64_W = 542 |
| CEFBS_NotInMips16Mode_IsNotSoftFloat, // PseudoCVT_S_L = 543 |
| CEFBS_NotInMips16Mode_IsNotSoftFloat, // PseudoCVT_S_W = 544 |
| CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // PseudoDMULT = 545 |
| CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // PseudoDMULTu = 546 |
| CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // PseudoDSDIV = 547 |
| CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // PseudoDUDIV = 548 |
| CEFBS_HasStdEnc_NotMips4_32, // PseudoD_SELECT_I = 549 |
| CEFBS_HasStdEnc_NotMips4_32, // PseudoD_SELECT_I64 = 550 |
| CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // PseudoIndirectBranch = 551 |
| CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // PseudoIndirectBranch64 = 552 |
| CEFBS_HasStdEnc_HasMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // PseudoIndirectBranch64R6 = 553 |
| CEFBS_HasStdEnc_HasMips32r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // PseudoIndirectBranchR6 = 554 |
| CEFBS_InMicroMips_NotMips32r6, // PseudoIndirectBranch_MM = 555 |
| CEFBS_InMicroMips_HasMips32r6, // PseudoIndirectBranch_MMR6 = 556 |
| CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // PseudoIndirectHazardBranch = 557 |
| CEFBS_HasStdEnc_IsPTR64bit_HasMips32r2_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // PseudoIndirectHazardBranch64 = 558 |
| CEFBS_HasStdEnc_HasMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // PseudoIndrectHazardBranch64R6 = 559 |
| CEFBS_HasStdEnc_HasMips32r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // PseudoIndrectHazardBranchR6 = 560 |
| CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6, // PseudoMADD = 561 |
| CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6, // PseudoMADDU = 562 |
| CEFBS_InMicroMips_NotMips32r6, // PseudoMADDU_MM = 563 |
| CEFBS_InMicroMips_NotMips32r6, // PseudoMADD_MM = 564 |
| CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // PseudoMFHI = 565 |
| CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // PseudoMFHI64 = 566 |
| CEFBS_InMicroMips_NotMips32r6, // PseudoMFHI_MM = 567 |
| CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // PseudoMFLO = 568 |
| CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // PseudoMFLO64 = 569 |
| CEFBS_InMicroMips_NotMips32r6, // PseudoMFLO_MM = 570 |
| CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6, // PseudoMSUB = 571 |
| CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6, // PseudoMSUBU = 572 |
| CEFBS_InMicroMips_NotMips32r6, // PseudoMSUBU_MM = 573 |
| CEFBS_InMicroMips_NotMips32r6, // PseudoMSUB_MM = 574 |
| CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // PseudoMTLOHI = 575 |
| CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // PseudoMTLOHI64 = 576 |
| CEFBS_NotInMips16Mode_HasDSP, // PseudoMTLOHI_DSP = 577 |
| CEFBS_InMicroMips_NotMips32r6, // PseudoMTLOHI_MM = 578 |
| CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // PseudoMULT = 579 |
| CEFBS_InMicroMips_NotMips32r6, // PseudoMULT_MM = 580 |
| CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // PseudoMULTu = 581 |
| CEFBS_InMicroMips_NotMips32r6, // PseudoMULTu_MM = 582 |
| CEFBS_HasDSP, // PseudoPICK_PH = 583 |
| CEFBS_HasDSP, // PseudoPICK_QB = 584 |
| CEFBS_None, // PseudoReturn = 585 |
| CEFBS_IsGP64bit, // PseudoReturn64 = 586 |
| CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // PseudoSDIV = 587 |
| CEFBS_HasStdEnc_NotFP64bit_NotMips4_32, // PseudoSELECTFP_F_D32 = 588 |
| CEFBS_HasStdEnc_IsFP64bit_NotMips4_32, // PseudoSELECTFP_F_D64 = 589 |
| CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECTFP_F_I = 590 |
| CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECTFP_F_I64 = 591 |
| CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECTFP_F_S = 592 |
| CEFBS_HasStdEnc_NotFP64bit_NotMips4_32, // PseudoSELECTFP_T_D32 = 593 |
| CEFBS_HasStdEnc_IsFP64bit_NotMips4_32, // PseudoSELECTFP_T_D64 = 594 |
| CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECTFP_T_I = 595 |
| CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECTFP_T_I64 = 596 |
| CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECTFP_T_S = 597 |
| CEFBS_HasStdEnc_NotFP64bit_NotMips4_32, // PseudoSELECT_D32 = 598 |
| CEFBS_HasStdEnc_IsFP64bit_NotMips4_32, // PseudoSELECT_D64 = 599 |
| CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECT_I = 600 |
| CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECT_I64 = 601 |
| CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECT_S = 602 |
| CEFBS_IsFP64bit_IsNotSoftFloat, // PseudoTRUNC_W_D = 603 |
| CEFBS_NotFP64bit_IsNotSoftFloat, // PseudoTRUNC_W_D32 = 604 |
| CEFBS_None, // PseudoTRUNC_W_S = 605 |
| CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // PseudoUDIV = 606 |
| CEFBS_None, // ROL = 607 |
| CEFBS_None, // ROLImm = 608 |
| CEFBS_None, // ROR = 609 |
| CEFBS_None, // RORImm = 610 |
| CEFBS_NotInMips16Mode, // RetRA = 611 |
| CEFBS_InMips16Mode, // RetRA16 = 612 |
| CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat, // SDC1_M1 = 613 |
| CEFBS_InMicroMips_NotMips32r6_NotMips64r6, // SDIV_MM_Pseudo = 614 |
| CEFBS_HasStdEnc_NotMips3, // SDMacro = 615 |
| CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // SDivIMacro = 616 |
| CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // SDivMacro = 617 |
| CEFBS_NotCnMips, // SEQIMacro = 618 |
| CEFBS_NotCnMips, // SEQMacro = 619 |
| CEFBS_HasStdEnc_NotInMicroMips, // SGE = 620 |
| CEFBS_IsGP32bit_NotInMicroMips, // SGEImm = 621 |
| CEFBS_IsGP64bit, // SGEImm64 = 622 |
| CEFBS_HasStdEnc_NotInMicroMips, // SGEU = 623 |
| CEFBS_IsGP32bit_NotInMicroMips, // SGEUImm = 624 |
| CEFBS_IsGP64bit, // SGEUImm64 = 625 |
| CEFBS_IsGP32bit_NotInMicroMips, // SGTImm = 626 |
| CEFBS_IsGP64bit, // SGTImm64 = 627 |
| CEFBS_IsGP32bit_NotInMicroMips, // SGTUImm = 628 |
| CEFBS_IsGP64bit, // SGTUImm64 = 629 |
| CEFBS_HasStdEnc_NotInMicroMips, // SLE = 630 |
| CEFBS_IsGP32bit_NotInMicroMips, // SLEImm = 631 |
| CEFBS_IsGP64bit, // SLEImm64 = 632 |
| CEFBS_HasStdEnc_NotInMicroMips, // SLEU = 633 |
| CEFBS_IsGP32bit_NotInMicroMips, // SLEUImm = 634 |
| CEFBS_IsGP64bit, // SLEUImm64 = 635 |
| CEFBS_IsGP64bit, // SLTImm64 = 636 |
| CEFBS_IsGP64bit, // SLTUImm64 = 637 |
| CEFBS_NotCnMips, // SNEIMacro = 638 |
| CEFBS_NotCnMips, // SNEMacro = 639 |
| CEFBS_None, // SNZ_B_PSEUDO = 640 |
| CEFBS_None, // SNZ_D_PSEUDO = 641 |
| CEFBS_None, // SNZ_H_PSEUDO = 642 |
| CEFBS_None, // SNZ_V_PSEUDO = 643 |
| CEFBS_None, // SNZ_W_PSEUDO = 644 |
| CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // SRemIMacro = 645 |
| CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // SRemMacro = 646 |
| CEFBS_NotInMips16Mode, // STORE_ACC128 = 647 |
| CEFBS_NotInMips16Mode, // STORE_ACC64 = 648 |
| CEFBS_NotInMips16Mode, // STORE_ACC64DSP = 649 |
| CEFBS_NotInMips16Mode, // STORE_CCOND_DSP = 650 |
| CEFBS_NotInMips16Mode, // STR_D = 651 |
| CEFBS_NotInMips16Mode, // STR_W = 652 |
| CEFBS_HasMSA, // ST_F16 = 653 |
| CEFBS_InMicroMips, // SWM_MM = 654 |
| CEFBS_None, // SZ_B_PSEUDO = 655 |
| CEFBS_None, // SZ_D_PSEUDO = 656 |
| CEFBS_None, // SZ_H_PSEUDO = 657 |
| CEFBS_None, // SZ_V_PSEUDO = 658 |
| CEFBS_None, // SZ_W_PSEUDO = 659 |
| CEFBS_HasCnMipsP, // SaaAddr = 660 |
| CEFBS_HasCnMipsP, // SaadAddr = 661 |
| CEFBS_InMips16Mode, // SelBeqZ = 662 |
| CEFBS_InMips16Mode, // SelBneZ = 663 |
| CEFBS_InMips16Mode, // SelTBteqZCmp = 664 |
| CEFBS_InMips16Mode, // SelTBteqZCmpi = 665 |
| CEFBS_InMips16Mode, // SelTBteqZSlt = 666 |
| CEFBS_InMips16Mode, // SelTBteqZSlti = 667 |
| CEFBS_InMips16Mode, // SelTBteqZSltiu = 668 |
| CEFBS_InMips16Mode, // SelTBteqZSltu = 669 |
| CEFBS_InMips16Mode, // SelTBtneZCmp = 670 |
| CEFBS_InMips16Mode, // SelTBtneZCmpi = 671 |
| CEFBS_InMips16Mode, // SelTBtneZSlt = 672 |
| CEFBS_InMips16Mode, // SelTBtneZSlti = 673 |
| CEFBS_InMips16Mode, // SelTBtneZSltiu = 674 |
| CEFBS_InMips16Mode, // SelTBtneZSltu = 675 |
| CEFBS_InMips16Mode, // SltCCRxRy16 = 676 |
| CEFBS_InMips16Mode, // SltiCCRxImmX16 = 677 |
| CEFBS_InMips16Mode, // SltiuCCRxImmX16 = 678 |
| CEFBS_InMips16Mode, // SltuCCRxRy16 = 679 |
| CEFBS_InMips16Mode, // SltuRxRyRz16 = 680 |
| CEFBS_HasStdEnc_NotInMips16Mode_NotInMicroMips, // TAILCALL = 681 |
| CEFBS_HasStdEnc_HasMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // TAILCALL64R6REG = 682 |
| CEFBS_HasStdEnc_HasMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // TAILCALLHB64R6REG = 683 |
| CEFBS_HasStdEnc_HasMips32r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // TAILCALLHBR6REG = 684 |
| CEFBS_HasStdEnc_HasMips32r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // TAILCALLR6REG = 685 |
| CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // TAILCALLREG = 686 |
| CEFBS_HasStdEnc_IsPTR64bit_HasMips3_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // TAILCALLREG64 = 687 |
| CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // TAILCALLREGHB = 688 |
| CEFBS_HasStdEnc_IsPTR64bit_HasMips32r2_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // TAILCALLREGHB64 = 689 |
| CEFBS_InMicroMips_NotMips32r6, // TAILCALLREG_MM = 690 |
| CEFBS_InMicroMips_HasMips32r6, // TAILCALLREG_MMR6 = 691 |
| CEFBS_InMicroMips_NotMips32r6, // TAILCALL_MM = 692 |
| CEFBS_InMicroMips_HasMips32r6, // TAILCALL_MMR6 = 693 |
| CEFBS_HasStdEnc_NotInMicroMips, // TRAP = 694 |
| CEFBS_InMicroMips, // TRAP_MM = 695 |
| CEFBS_InMicroMips_NotMips32r6_NotMips64r6, // UDIV_MM_Pseudo = 696 |
| CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // UDivIMacro = 697 |
| CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // UDivMacro = 698 |
| CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // URemIMacro = 699 |
| CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // URemMacro = 700 |
| CEFBS_None, // Ulh = 701 |
| CEFBS_None, // Ulhu = 702 |
| CEFBS_None, // Ulw = 703 |
| CEFBS_None, // Ush = 704 |
| CEFBS_None, // Usw = 705 |
| CEFBS_HasStdEnc_HasMSA, // XOR_V_D_PSEUDO = 706 |
| CEFBS_HasStdEnc_HasMSA, // XOR_V_H_PSEUDO = 707 |
| CEFBS_HasStdEnc_HasMSA, // XOR_V_W_PSEUDO = 708 |
| CEFBS_HasDSP, // ABSQ_S_PH = 709 |
| CEFBS_InMicroMips_HasDSP, // ABSQ_S_PH_MM = 710 |
| CEFBS_HasDSPR2, // ABSQ_S_QB = 711 |
| CEFBS_InMicroMips_HasDSPR2, // ABSQ_S_QB_MMR2 = 712 |
| CEFBS_HasDSP, // ABSQ_S_W = 713 |
| CEFBS_InMicroMips_HasDSP, // ABSQ_S_W_MM = 714 |
| CEFBS_HasStdEnc_NotInMicroMips, // ADD = 715 |
| CEFBS_HasStdEnc_HasMips32r6, // ADDIUPC = 716 |
| CEFBS_InMicroMips_NotMips32r6, // ADDIUPC_MM = 717 |
| CEFBS_InMicroMips_HasMips32r6, // ADDIUPC_MMR6 = 718 |
| CEFBS_InMicroMips, // ADDIUR1SP_MM = 719 |
| CEFBS_InMicroMips, // ADDIUR2_MM = 720 |
| CEFBS_InMicroMips, // ADDIUS5_MM = 721 |
| CEFBS_InMicroMips, // ADDIUSP_MM = 722 |
| CEFBS_InMicroMips_HasMips32r6, // ADDIU_MMR6 = 723 |
| CEFBS_HasDSPR2, // ADDQH_PH = 724 |
| CEFBS_InMicroMips_HasDSPR2, // ADDQH_PH_MMR2 = 725 |
| CEFBS_HasDSPR2, // ADDQH_R_PH = 726 |
| CEFBS_InMicroMips_HasDSPR2, // ADDQH_R_PH_MMR2 = 727 |
| CEFBS_HasDSPR2, // ADDQH_R_W = 728 |
| CEFBS_InMicroMips_HasDSPR2, // ADDQH_R_W_MMR2 = 729 |
| CEFBS_HasDSPR2, // ADDQH_W = 730 |
| CEFBS_InMicroMips_HasDSPR2, // ADDQH_W_MMR2 = 731 |
| CEFBS_HasDSP, // ADDQ_PH = 732 |
| CEFBS_InMicroMips_HasDSP, // ADDQ_PH_MM = 733 |
| CEFBS_HasDSP, // ADDQ_S_PH = 734 |
| CEFBS_InMicroMips_HasDSP, // ADDQ_S_PH_MM = 735 |
| CEFBS_HasDSP, // ADDQ_S_W = 736 |
| CEFBS_InMicroMips_HasDSP, // ADDQ_S_W_MM = 737 |
| CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D, // ADDR_PS64 = 738 |
| CEFBS_HasDSP, // ADDSC = 739 |
| CEFBS_InMicroMips_HasDSP, // ADDSC_MM = 740 |
| CEFBS_HasStdEnc_HasMSA, // ADDS_A_B = 741 |
| CEFBS_HasStdEnc_HasMSA, // ADDS_A_D = 742 |
| CEFBS_HasStdEnc_HasMSA, // ADDS_A_H = 743 |
| CEFBS_HasStdEnc_HasMSA, // ADDS_A_W = 744 |
| CEFBS_HasStdEnc_HasMSA, // ADDS_S_B = 745 |
| CEFBS_HasStdEnc_HasMSA, // ADDS_S_D = 746 |
| CEFBS_HasStdEnc_HasMSA, // ADDS_S_H = 747 |
| CEFBS_HasStdEnc_HasMSA, // ADDS_S_W = 748 |
| CEFBS_HasStdEnc_HasMSA, // ADDS_U_B = 749 |
| CEFBS_HasStdEnc_HasMSA, // ADDS_U_D = 750 |
| CEFBS_HasStdEnc_HasMSA, // ADDS_U_H = 751 |
| CEFBS_HasStdEnc_HasMSA, // ADDS_U_W = 752 |
| CEFBS_InMicroMips_NotMips32r6, // ADDU16_MM = 753 |
| CEFBS_InMicroMips_HasMips32r6, // ADDU16_MMR6 = 754 |
| CEFBS_HasDSPR2, // ADDUH_QB = 755 |
| CEFBS_InMicroMips_HasDSPR2, // ADDUH_QB_MMR2 = 756 |
| CEFBS_HasDSPR2, // ADDUH_R_QB = 757 |
| CEFBS_InMicroMips_HasDSPR2, // ADDUH_R_QB_MMR2 = 758 |
| CEFBS_InMicroMips_HasMips32r6, // ADDU_MMR6 = 759 |
| CEFBS_HasDSPR2, // ADDU_PH = 760 |
| CEFBS_InMicroMips_HasDSPR2, // ADDU_PH_MMR2 = 761 |
| CEFBS_HasDSP, // ADDU_QB = 762 |
| CEFBS_InMicroMips_HasDSP, // ADDU_QB_MM = 763 |
| CEFBS_HasDSPR2, // ADDU_S_PH = 764 |
| CEFBS_InMicroMips_HasDSPR2, // ADDU_S_PH_MMR2 = 765 |
| CEFBS_HasDSP, // ADDU_S_QB = 766 |
| CEFBS_InMicroMips_HasDSP, // ADDU_S_QB_MM = 767 |
| CEFBS_HasStdEnc_HasMSA, // ADDVI_B = 768 |
| CEFBS_HasStdEnc_HasMSA, // ADDVI_D = 769 |
| CEFBS_HasStdEnc_HasMSA, // ADDVI_H = 770 |
| CEFBS_HasStdEnc_HasMSA, // ADDVI_W = 771 |
| CEFBS_HasStdEnc_HasMSA, // ADDV_B = 772 |
| CEFBS_HasStdEnc_HasMSA, // ADDV_D = 773 |
| CEFBS_HasStdEnc_HasMSA, // ADDV_H = 774 |
| CEFBS_HasStdEnc_HasMSA, // ADDV_W = 775 |
| CEFBS_HasDSP, // ADDWC = 776 |
| CEFBS_InMicroMips_HasDSP, // ADDWC_MM = 777 |
| CEFBS_HasStdEnc_HasMSA, // ADD_A_B = 778 |
| CEFBS_HasStdEnc_HasMSA, // ADD_A_D = 779 |
| CEFBS_HasStdEnc_HasMSA, // ADD_A_H = 780 |
| CEFBS_HasStdEnc_HasMSA, // ADD_A_W = 781 |
| CEFBS_InMicroMips_NotMips32r6, // ADD_MM = 782 |
| CEFBS_InMicroMips_HasMips32r6, // ADD_MMR6 = 783 |
| CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // ADDi = 784 |
| CEFBS_InMicroMips_NotMips32r6, // ADDi_MM = 785 |
| CEFBS_HasStdEnc_NotInMicroMips, // ADDiu = 786 |
| CEFBS_InMicroMips_NotMips32r6, // ADDiu_MM = 787 |
| CEFBS_HasStdEnc_NotInMicroMips, // ADDu = 788 |
| CEFBS_InMicroMips_NotMips32r6, // ADDu_MM = 789 |
| CEFBS_HasStdEnc_HasMips32r6, // ALIGN = 790 |
| CEFBS_InMicroMips_HasMips32r6, // ALIGN_MMR6 = 791 |
| CEFBS_HasStdEnc_HasMips32r6, // ALUIPC = 792 |
| CEFBS_InMicroMips_HasMips32r6, // ALUIPC_MMR6 = 793 |
| CEFBS_HasStdEnc_NotInMicroMips, // AND = 794 |
| CEFBS_InMicroMips_NotMips32r6, // AND16_MM = 795 |
| CEFBS_InMicroMips_HasMips32r6, // AND16_MMR6 = 796 |
| CEFBS_NotInMips16Mode_IsGP64bit, // AND64 = 797 |
| CEFBS_InMicroMips_NotMips32r6, // ANDI16_MM = 798 |
| CEFBS_InMicroMips_HasMips32r6, // ANDI16_MMR6 = 799 |
| CEFBS_HasStdEnc_HasMSA, // ANDI_B = 800 |
| CEFBS_InMicroMips_HasMips32r6, // ANDI_MMR6 = 801 |
| CEFBS_InMicroMips_NotMips32r6, // AND_MM = 802 |
| CEFBS_InMicroMips_HasMips32r6, // AND_MMR6 = 803 |
| CEFBS_HasStdEnc_HasMSA, // AND_V = 804 |
| CEFBS_HasStdEnc_NotInMicroMips, // ANDi = 805 |
| CEFBS_NotInMips16Mode_IsGP64bit, // ANDi64 = 806 |
| CEFBS_InMicroMips_NotMips32r6, // ANDi_MM = 807 |
| CEFBS_HasDSPR2, // APPEND = 808 |
| CEFBS_InMicroMips_HasDSPR2, // APPEND_MMR2 = 809 |
| CEFBS_HasStdEnc_HasMSA, // ASUB_S_B = 810 |
| CEFBS_HasStdEnc_HasMSA, // ASUB_S_D = 811 |
| CEFBS_HasStdEnc_HasMSA, // ASUB_S_H = 812 |
| CEFBS_HasStdEnc_HasMSA, // ASUB_S_W = 813 |
| CEFBS_HasStdEnc_HasMSA, // ASUB_U_B = 814 |
| CEFBS_HasStdEnc_HasMSA, // ASUB_U_D = 815 |
| CEFBS_HasStdEnc_HasMSA, // ASUB_U_H = 816 |
| CEFBS_HasStdEnc_HasMSA, // ASUB_U_W = 817 |
| CEFBS_HasStdEnc_HasMips32r6, // AUI = 818 |
| CEFBS_HasStdEnc_HasMips32r6, // AUIPC = 819 |
| CEFBS_InMicroMips_HasMips32r6, // AUIPC_MMR6 = 820 |
| CEFBS_InMicroMips_HasMips32r6, // AUI_MMR6 = 821 |
| CEFBS_HasStdEnc_HasMSA, // AVER_S_B = 822 |
| CEFBS_HasStdEnc_HasMSA, // AVER_S_D = 823 |
| CEFBS_HasStdEnc_HasMSA, // AVER_S_H = 824 |
| CEFBS_HasStdEnc_HasMSA, // AVER_S_W = 825 |
| CEFBS_HasStdEnc_HasMSA, // AVER_U_B = 826 |
| CEFBS_HasStdEnc_HasMSA, // AVER_U_D = 827 |
| CEFBS_HasStdEnc_HasMSA, // AVER_U_H = 828 |
| CEFBS_HasStdEnc_HasMSA, // AVER_U_W = 829 |
| CEFBS_HasStdEnc_HasMSA, // AVE_S_B = 830 |
| CEFBS_HasStdEnc_HasMSA, // AVE_S_D = 831 |
| CEFBS_HasStdEnc_HasMSA, // AVE_S_H = 832 |
| CEFBS_HasStdEnc_HasMSA, // AVE_S_W = 833 |
| CEFBS_HasStdEnc_HasMSA, // AVE_U_B = 834 |
| CEFBS_HasStdEnc_HasMSA, // AVE_U_D = 835 |
| CEFBS_HasStdEnc_HasMSA, // AVE_U_H = 836 |
| CEFBS_HasStdEnc_HasMSA, // AVE_U_W = 837 |
| CEFBS_InMips16Mode, // AddiuRxImmX16 = 838 |
| CEFBS_InMips16Mode, // AddiuRxPcImmX16 = 839 |
| CEFBS_InMips16Mode, // AddiuRxRxImm16 = 840 |
| CEFBS_InMips16Mode, // AddiuRxRxImmX16 = 841 |
| CEFBS_InMips16Mode, // AddiuRxRyOffMemX16 = 842 |
| CEFBS_InMips16Mode, // AddiuSpImm16 = 843 |
| CEFBS_InMips16Mode, // AddiuSpImmX16 = 844 |
| CEFBS_InMips16Mode, // AdduRxRyRz16 = 845 |
| CEFBS_InMips16Mode, // AndRxRxRy16 = 846 |
| CEFBS_InMicroMips, // B16_MM = 847 |
| CEFBS_HasCnMips, // BADDu = 848 |
| CEFBS_HasStdEnc_HasMips32r6, // BAL = 849 |
| CEFBS_HasStdEnc_HasMips32r6, // BALC = 850 |
| CEFBS_InMicroMips_HasMips32r6, // BALC_MMR6 = 851 |
| CEFBS_HasDSPR2, // BALIGN = 852 |
| CEFBS_InMicroMips_HasDSPR2, // BALIGN_MMR2 = 853 |
| CEFBS_HasCnMips, // BBIT0 = 854 |
| CEFBS_HasCnMips, // BBIT032 = 855 |
| CEFBS_HasCnMips, // BBIT1 = 856 |
| CEFBS_HasCnMips, // BBIT132 = 857 |
| CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BC = 858 |
| CEFBS_InMicroMips_HasMips32r6, // BC16_MMR6 = 859 |
| CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // BC1EQZ = 860 |
| CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // BC1EQZC_MMR6 = 861 |
| CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // BC1F = 862 |
| CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // BC1FL = 863 |
| CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // BC1F_MM = 864 |
| CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // BC1NEZ = 865 |
| CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // BC1NEZC_MMR6 = 866 |
| CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // BC1T = 867 |
| CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // BC1TL = 868 |
| CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // BC1T_MM = 869 |
| CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BC2EQZ = 870 |
| CEFBS_InMicroMips_HasMips32r6, // BC2EQZC_MMR6 = 871 |
| CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BC2NEZ = 872 |
| CEFBS_InMicroMips_HasMips32r6, // BC2NEZC_MMR6 = 873 |
| CEFBS_HasStdEnc_HasMSA, // BCLRI_B = 874 |
| CEFBS_HasStdEnc_HasMSA, // BCLRI_D = 875 |
| CEFBS_HasStdEnc_HasMSA, // BCLRI_H = 876 |
| CEFBS_HasStdEnc_HasMSA, // BCLRI_W = 877 |
| CEFBS_HasStdEnc_HasMSA, // BCLR_B = 878 |
| CEFBS_HasStdEnc_HasMSA, // BCLR_D = 879 |
| CEFBS_HasStdEnc_HasMSA, // BCLR_H = 880 |
| CEFBS_HasStdEnc_HasMSA, // BCLR_W = 881 |
| CEFBS_InMicroMips_HasMips32r6, // BC_MMR6 = 882 |
| CEFBS_HasStdEnc_NotInMicroMips, // BEQ = 883 |
| CEFBS_NotInMips16Mode_IsGP64bit, // BEQ64 = 884 |
| CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BEQC = 885 |
| CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BEQC64 = 886 |
| CEFBS_InMicroMips_HasMips32r6, // BEQC_MMR6 = 887 |
| CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BEQL = 888 |
| CEFBS_InMicroMips_NotMips32r6, // BEQZ16_MM = 889 |
| CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BEQZALC = 890 |
| CEFBS_InMicroMips_HasMips32r6, // BEQZALC_MMR6 = 891 |
| CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BEQZC = 892 |
| CEFBS_InMicroMips_HasMips32r6, // BEQZC16_MMR6 = 893 |
| CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BEQZC64 = 894 |
| CEFBS_InMicroMips_NotMips32r6, // BEQZC_MM = 895 |
| CEFBS_InMicroMips_HasMips32r6, // BEQZC_MMR6 = 896 |
| CEFBS_InMicroMips_NotMips32r6, // BEQ_MM = 897 |
| CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BGEC = 898 |
| CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BGEC64 = 899 |
| CEFBS_InMicroMips_HasMips32r6, // BGEC_MMR6 = 900 |
| CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BGEUC = 901 |
| CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BGEUC64 = 902 |
| CEFBS_InMicroMips_HasMips32r6, // BGEUC_MMR6 = 903 |
| CEFBS_HasStdEnc_NotInMicroMips, // BGEZ = 904 |
| CEFBS_NotInMips16Mode_IsGP64bit, // BGEZ64 = 905 |
| CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // BGEZAL = 906 |
| CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BGEZALC = 907 |
| CEFBS_InMicroMips_HasMips32r6, // BGEZALC_MMR6 = 908 |
| CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BGEZALL = 909 |
| CEFBS_InMicroMips_NotMips32r6, // BGEZALS_MM = 910 |
| CEFBS_InMicroMips_NotMips32r6, // BGEZAL_MM = 911 |
| CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BGEZC = 912 |
| CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BGEZC64 = 913 |
| CEFBS_InMicroMips_HasMips32r6, // BGEZC_MMR6 = 914 |
| CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BGEZL = 915 |
| CEFBS_InMicroMips_NotMips32r6, // BGEZ_MM = 916 |
| CEFBS_HasStdEnc_NotInMicroMips, // BGTZ = 917 |
| CEFBS_NotInMips16Mode_IsGP64bit, // BGTZ64 = 918 |
| CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BGTZALC = 919 |
| CEFBS_InMicroMips_HasMips32r6, // BGTZALC_MMR6 = 920 |
| CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BGTZC = 921 |
| CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BGTZC64 = 922 |
| CEFBS_InMicroMips_HasMips32r6, // BGTZC_MMR6 = 923 |
| CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BGTZL = 924 |
| CEFBS_InMicroMips_NotMips32r6, // BGTZ_MM = 925 |
| CEFBS_HasStdEnc_HasMSA, // BINSLI_B = 926 |
| CEFBS_HasStdEnc_HasMSA, // BINSLI_D = 927 |
| CEFBS_HasStdEnc_HasMSA, // BINSLI_H = 928 |
| CEFBS_HasStdEnc_HasMSA, // BINSLI_W = 929 |
| CEFBS_HasStdEnc_HasMSA, // BINSL_B = 930 |
| CEFBS_HasStdEnc_HasMSA, // BINSL_D = 931 |
| CEFBS_HasStdEnc_HasMSA, // BINSL_H = 932 |
| CEFBS_HasStdEnc_HasMSA, // BINSL_W = 933 |
| CEFBS_HasStdEnc_HasMSA, // BINSRI_B = 934 |
| CEFBS_HasStdEnc_HasMSA, // BINSRI_D = 935 |
| CEFBS_HasStdEnc_HasMSA, // BINSRI_H = 936 |
| CEFBS_HasStdEnc_HasMSA, // BINSRI_W = 937 |
| CEFBS_HasStdEnc_HasMSA, // BINSR_B = 938 |
| CEFBS_HasStdEnc_HasMSA, // BINSR_D = 939 |
| CEFBS_HasStdEnc_HasMSA, // BINSR_H = 940 |
| CEFBS_HasStdEnc_HasMSA, // BINSR_W = 941 |
| CEFBS_HasDSP, // BITREV = 942 |
| CEFBS_InMicroMips_HasDSP, // BITREV_MM = 943 |
| CEFBS_HasStdEnc_HasMips32r6, // BITSWAP = 944 |
| CEFBS_InMicroMips_HasMips32r6, // BITSWAP_MMR6 = 945 |
| CEFBS_HasStdEnc_NotInMicroMips, // BLEZ = 946 |
| CEFBS_NotInMips16Mode_IsGP64bit, // BLEZ64 = 947 |
| CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BLEZALC = 948 |
| CEFBS_InMicroMips_HasMips32r6, // BLEZALC_MMR6 = 949 |
| CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BLEZC = 950 |
| CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BLEZC64 = 951 |
| CEFBS_InMicroMips_HasMips32r6, // BLEZC_MMR6 = 952 |
| CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BLEZL = 953 |
| CEFBS_InMicroMips_NotMips32r6, // BLEZ_MM = 954 |
| CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BLTC = 955 |
| CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BLTC64 = 956 |
| CEFBS_InMicroMips_HasMips32r6, // BLTC_MMR6 = 957 |
| CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BLTUC = 958 |
| CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BLTUC64 = 959 |
| CEFBS_InMicroMips_HasMips32r6, // BLTUC_MMR6 = 960 |
| CEFBS_HasStdEnc_NotInMicroMips, // BLTZ = 961 |
| CEFBS_NotInMips16Mode_IsGP64bit, // BLTZ64 = 962 |
| CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // BLTZAL = 963 |
| CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BLTZALC = 964 |
| CEFBS_InMicroMips_HasMips32r6, // BLTZALC_MMR6 = 965 |
| CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BLTZALL = 966 |
| CEFBS_InMicroMips_NotMips32r6, // BLTZALS_MM = 967 |
| CEFBS_InMicroMips_NotMips32r6, // BLTZAL_MM = 968 |
| CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BLTZC = 969 |
| CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BLTZC64 = 970 |
| CEFBS_InMicroMips_HasMips32r6, // BLTZC_MMR6 = 971 |
| CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BLTZL = 972 |
| CEFBS_InMicroMips_NotMips32r6, // BLTZ_MM = 973 |
| CEFBS_HasStdEnc_HasMSA, // BMNZI_B = 974 |
| CEFBS_HasStdEnc_HasMSA, // BMNZ_V = 975 |
| CEFBS_HasStdEnc_HasMSA, // BMZI_B = 976 |
| CEFBS_HasStdEnc_HasMSA, // BMZ_V = 977 |
| CEFBS_HasStdEnc_NotInMicroMips, // BNE = 978 |
| CEFBS_NotInMips16Mode_IsGP64bit, // BNE64 = 979 |
| CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BNEC = 980 |
| CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BNEC64 = 981 |
| CEFBS_InMicroMips_HasMips32r6, // BNEC_MMR6 = 982 |
| CEFBS_HasStdEnc_HasMSA, // BNEGI_B = 983 |
| CEFBS_HasStdEnc_HasMSA, // BNEGI_D = 984 |
| CEFBS_HasStdEnc_HasMSA, // BNEGI_H = 985 |
| CEFBS_HasStdEnc_HasMSA, // BNEGI_W = 986 |
| CEFBS_HasStdEnc_HasMSA, // BNEG_B = 987 |
| CEFBS_HasStdEnc_HasMSA, // BNEG_D = 988 |
| CEFBS_HasStdEnc_HasMSA, // BNEG_H = 989 |
| CEFBS_HasStdEnc_HasMSA, // BNEG_W = 990 |
| CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BNEL = 991 |
| CEFBS_InMicroMips_NotMips32r6, // BNEZ16_MM = 992 |
| CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BNEZALC = 993 |
| CEFBS_InMicroMips_HasMips32r6, // BNEZALC_MMR6 = 994 |
| CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BNEZC = 995 |
| CEFBS_InMicroMips_HasMips32r6, // BNEZC16_MMR6 = 996 |
| CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BNEZC64 = 997 |
| CEFBS_InMicroMips_NotMips32r6, // BNEZC_MM = 998 |
| CEFBS_InMicroMips_HasMips32r6, // BNEZC_MMR6 = 999 |
| CEFBS_InMicroMips_NotMips32r6, // BNE_MM = 1000 |
| CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BNVC = 1001 |
| CEFBS_InMicroMips_HasMips32r6, // BNVC_MMR6 = 1002 |
| CEFBS_HasStdEnc_HasMSA, // BNZ_B = 1003 |
| CEFBS_HasStdEnc_HasMSA, // BNZ_D = 1004 |
| CEFBS_HasStdEnc_HasMSA, // BNZ_H = 1005 |
| CEFBS_HasStdEnc_HasMSA, // BNZ_V = 1006 |
| CEFBS_HasStdEnc_HasMSA, // BNZ_W = 1007 |
| CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BOVC = 1008 |
| CEFBS_InMicroMips_HasMips32r6, // BOVC_MMR6 = 1009 |
| CEFBS_HasDSP_NotInMicroMips, // BPOSGE32 = 1010 |
| CEFBS_InMicroMips_HasDSPR3, // BPOSGE32C_MMR3 = 1011 |
| CEFBS_InMicroMips_NotMips32r6_HasDSP, // BPOSGE32_MM = 1012 |
| CEFBS_HasStdEnc_NotInMicroMips, // BREAK = 1013 |
| CEFBS_InMicroMips_NotMips32r6, // BREAK16_MM = 1014 |
| CEFBS_InMicroMips_HasMips32r6, // BREAK16_MMR6 = 1015 |
| CEFBS_InMicroMips, // BREAK_MM = 1016 |
| CEFBS_InMicroMips_HasMips32r6, // BREAK_MMR6 = 1017 |
| CEFBS_HasStdEnc_HasMSA, // BSELI_B = 1018 |
| CEFBS_HasStdEnc_HasMSA, // BSEL_V = 1019 |
| CEFBS_HasStdEnc_HasMSA, // BSETI_B = 1020 |
| CEFBS_HasStdEnc_HasMSA, // BSETI_D = 1021 |
| CEFBS_HasStdEnc_HasMSA, // BSETI_H = 1022 |
| CEFBS_HasStdEnc_HasMSA, // BSETI_W = 1023 |
| CEFBS_HasStdEnc_HasMSA, // BSET_B = 1024 |
| CEFBS_HasStdEnc_HasMSA, // BSET_D = 1025 |
| CEFBS_HasStdEnc_HasMSA, // BSET_H = 1026 |
| CEFBS_HasStdEnc_HasMSA, // BSET_W = 1027 |
| CEFBS_HasStdEnc_HasMSA, // BZ_B = 1028 |
| CEFBS_HasStdEnc_HasMSA, // BZ_D = 1029 |
| CEFBS_HasStdEnc_HasMSA, // BZ_H = 1030 |
| CEFBS_HasStdEnc_HasMSA, // BZ_V = 1031 |
| CEFBS_HasStdEnc_HasMSA, // BZ_W = 1032 |
| CEFBS_InMips16Mode, // BeqzRxImm16 = 1033 |
| CEFBS_InMips16Mode, // BeqzRxImmX16 = 1034 |
| CEFBS_InMips16Mode, // Bimm16 = 1035 |
| CEFBS_InMips16Mode, // BimmX16 = 1036 |
| CEFBS_InMips16Mode, // BnezRxImm16 = 1037 |
| CEFBS_InMips16Mode, // BnezRxImmX16 = 1038 |
| CEFBS_InMips16Mode, // Break16 = 1039 |
| CEFBS_InMips16Mode, // Bteqz16 = 1040 |
| CEFBS_InMips16Mode, // BteqzX16 = 1041 |
| CEFBS_InMips16Mode, // Btnez16 = 1042 |
| CEFBS_InMips16Mode, // BtnezX16 = 1043 |
| CEFBS_HasStdEnc_HasMips3_32_NotMips32r6_NotMips64r6_NotInMicroMips, // CACHE = 1044 |
| CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // CACHEE = 1045 |
| CEFBS_InMicroMips_HasEVA, // CACHEE_MM = 1046 |
| CEFBS_InMicroMips_NotMips32r6, // CACHE_MM = 1047 |
| CEFBS_InMicroMips_HasMips32r6, // CACHE_MMR6 = 1048 |
| CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // CACHE_R6 = 1049 |
| CEFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips, // CEIL_L_D64 = 1050 |
| CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CEIL_L_D_MMR6 = 1051 |
| CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // CEIL_L_S = 1052 |
| CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CEIL_L_S_MMR6 = 1053 |
| CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // CEIL_W_D32 = 1054 |
| CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // CEIL_W_D64 = 1055 |
| CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CEIL_W_D_MMR6 = 1056 |
| CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // CEIL_W_MM = 1057 |
| CEFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips, // CEIL_W_S = 1058 |
| CEFBS_InMicroMips_IsNotSoftFloat, // CEIL_W_S_MM = 1059 |
| CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CEIL_W_S_MMR6 = 1060 |
| CEFBS_HasStdEnc_HasMSA, // CEQI_B = 1061 |
| CEFBS_HasStdEnc_HasMSA, // CEQI_D = 1062 |
| CEFBS_HasStdEnc_HasMSA, // CEQI_H = 1063 |
| CEFBS_HasStdEnc_HasMSA, // CEQI_W = 1064 |
| CEFBS_HasStdEnc_HasMSA, // CEQ_B = 1065 |
| CEFBS_HasStdEnc_HasMSA, // CEQ_D = 1066 |
| CEFBS_HasStdEnc_HasMSA, // CEQ_H = 1067 |
| CEFBS_HasStdEnc_HasMSA, // CEQ_W = 1068 |
| CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // CFC1 = 1069 |
| CEFBS_InMicroMips_IsNotSoftFloat, // CFC1_MM = 1070 |
| CEFBS_InMicroMips, // CFC2_MM = 1071 |
| CEFBS_HasStdEnc_HasMSA, // CFCMSA = 1072 |
| CEFBS_HasMips64_HasCnMips_NotInMicroMips, // CINS = 1073 |
| CEFBS_HasMips64_HasCnMips_NotInMicroMips, // CINS32 = 1074 |
| CEFBS_HasMips64_HasCnMips_NotInMicroMips, // CINS64_32 = 1075 |
| CEFBS_HasMips64_HasCnMips_NotInMicroMips, // CINS_i32 = 1076 |
| CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CLASS_D = 1077 |
| CEFBS_InMicroMips_HasMips32r6, // CLASS_D_MMR6 = 1078 |
| CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CLASS_S = 1079 |
| CEFBS_InMicroMips_HasMips32r6, // CLASS_S_MMR6 = 1080 |
| CEFBS_HasStdEnc_HasMSA, // CLEI_S_B = 1081 |
| CEFBS_HasStdEnc_HasMSA, // CLEI_S_D = 1082 |
| CEFBS_HasStdEnc_HasMSA, // CLEI_S_H = 1083 |
| CEFBS_HasStdEnc_HasMSA, // CLEI_S_W = 1084 |
| CEFBS_HasStdEnc_HasMSA, // CLEI_U_B = 1085 |
| CEFBS_HasStdEnc_HasMSA, // CLEI_U_D = 1086 |
| CEFBS_HasStdEnc_HasMSA, // CLEI_U_H = 1087 |
| CEFBS_HasStdEnc_HasMSA, // CLEI_U_W = 1088 |
| CEFBS_HasStdEnc_HasMSA, // CLE_S_B = 1089 |
| CEFBS_HasStdEnc_HasMSA, // CLE_S_D = 1090 |
| CEFBS_HasStdEnc_HasMSA, // CLE_S_H = 1091 |
| CEFBS_HasStdEnc_HasMSA, // CLE_S_W = 1092 |
| CEFBS_HasStdEnc_HasMSA, // CLE_U_B = 1093 |
| CEFBS_HasStdEnc_HasMSA, // CLE_U_D = 1094 |
| CEFBS_HasStdEnc_HasMSA, // CLE_U_H = 1095 |
| CEFBS_HasStdEnc_HasMSA, // CLE_U_W = 1096 |
| CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // CLO = 1097 |
| CEFBS_InMicroMips, // CLO_MM = 1098 |
| CEFBS_InMicroMips_HasMips32r6, // CLO_MMR6 = 1099 |
| CEFBS_HasStdEnc_HasMips32r6, // CLO_R6 = 1100 |
| CEFBS_HasStdEnc_HasMSA, // CLTI_S_B = 1101 |
| CEFBS_HasStdEnc_HasMSA, // CLTI_S_D = 1102 |
| CEFBS_HasStdEnc_HasMSA, // CLTI_S_H = 1103 |
| CEFBS_HasStdEnc_HasMSA, // CLTI_S_W = 1104 |
| CEFBS_HasStdEnc_HasMSA, // CLTI_U_B = 1105 |
| CEFBS_HasStdEnc_HasMSA, // CLTI_U_D = 1106 |
| CEFBS_HasStdEnc_HasMSA, // CLTI_U_H = 1107 |
| CEFBS_HasStdEnc_HasMSA, // CLTI_U_W = 1108 |
| CEFBS_HasStdEnc_HasMSA, // CLT_S_B = 1109 |
| CEFBS_HasStdEnc_HasMSA, // CLT_S_D = 1110 |
| CEFBS_HasStdEnc_HasMSA, // CLT_S_H = 1111 |
| CEFBS_HasStdEnc_HasMSA, // CLT_S_W = 1112 |
| CEFBS_HasStdEnc_HasMSA, // CLT_U_B = 1113 |
| CEFBS_HasStdEnc_HasMSA, // CLT_U_D = 1114 |
| CEFBS_HasStdEnc_HasMSA, // CLT_U_H = 1115 |
| CEFBS_HasStdEnc_HasMSA, // CLT_U_W = 1116 |
| CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // CLZ = 1117 |
| CEFBS_InMicroMips, // CLZ_MM = 1118 |
| CEFBS_InMicroMips_HasMips32r6, // CLZ_MMR6 = 1119 |
| CEFBS_HasStdEnc_HasMips32r6, // CLZ_R6 = 1120 |
| CEFBS_HasDSPR2, // CMPGDU_EQ_QB = 1121 |
| CEFBS_InMicroMips_HasDSPR2, // CMPGDU_EQ_QB_MMR2 = 1122 |
| CEFBS_HasDSPR2, // CMPGDU_LE_QB = 1123 |
| CEFBS_InMicroMips_HasDSPR2, // CMPGDU_LE_QB_MMR2 = 1124 |
| CEFBS_HasDSPR2, // CMPGDU_LT_QB = 1125 |
| CEFBS_InMicroMips_HasDSPR2, // CMPGDU_LT_QB_MMR2 = 1126 |
| CEFBS_HasDSP, // CMPGU_EQ_QB = 1127 |
| CEFBS_InMicroMips_HasDSP, // CMPGU_EQ_QB_MM = 1128 |
| CEFBS_HasDSP, // CMPGU_LE_QB = 1129 |
| CEFBS_InMicroMips_HasDSP, // CMPGU_LE_QB_MM = 1130 |
| CEFBS_HasDSP, // CMPGU_LT_QB = 1131 |
| CEFBS_InMicroMips_HasDSP, // CMPGU_LT_QB_MM = 1132 |
| CEFBS_HasDSP, // CMPU_EQ_QB = 1133 |
| CEFBS_InMicroMips_HasDSP, // CMPU_EQ_QB_MM = 1134 |
| CEFBS_HasDSP, // CMPU_LE_QB = 1135 |
| CEFBS_InMicroMips_HasDSP, // CMPU_LE_QB_MM = 1136 |
| CEFBS_HasDSP, // CMPU_LT_QB = 1137 |
| CEFBS_InMicroMips_HasDSP, // CMPU_LT_QB_MM = 1138 |
| CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_AF_D_MMR6 = 1139 |
| CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_AF_S_MMR6 = 1140 |
| CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_EQ_D = 1141 |
| CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_EQ_D_MMR6 = 1142 |
| CEFBS_HasDSP, // CMP_EQ_PH = 1143 |
| CEFBS_InMicroMips_HasDSP, // CMP_EQ_PH_MM = 1144 |
| CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_EQ_S = 1145 |
| CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_EQ_S_MMR6 = 1146 |
| CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_F_D = 1147 |
| CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_F_S = 1148 |
| CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_LE_D = 1149 |
| CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_LE_D_MMR6 = 1150 |
| CEFBS_HasDSP, // CMP_LE_PH = 1151 |
| CEFBS_InMicroMips_HasDSP, // CMP_LE_PH_MM = 1152 |
| CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_LE_S = 1153 |
| CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_LE_S_MMR6 = 1154 |
| CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_LT_D = 1155 |
| CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_LT_D_MMR6 = 1156 |
| CEFBS_HasDSP, // CMP_LT_PH = 1157 |
| CEFBS_InMicroMips_HasDSP, // CMP_LT_PH_MM = 1158 |
| CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_LT_S = 1159 |
| CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_LT_S_MMR6 = 1160 |
| CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SAF_D = 1161 |
| CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SAF_D_MMR6 = 1162 |
| CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SAF_S = 1163 |
| CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SAF_S_MMR6 = 1164 |
| CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SEQ_D = 1165 |
| CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SEQ_D_MMR6 = 1166 |
| CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SEQ_S = 1167 |
| CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SEQ_S_MMR6 = 1168 |
| CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SLE_D = 1169 |
| CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SLE_D_MMR6 = 1170 |
| CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SLE_S = 1171 |
| CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SLE_S_MMR6 = 1172 |
| CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SLT_D = 1173 |
| CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SLT_D_MMR6 = 1174 |
| CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SLT_S = 1175 |
| CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SLT_S_MMR6 = 1176 |
| CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SUEQ_D = 1177 |
| CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SUEQ_D_MMR6 = 1178 |
| CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SUEQ_S = 1179 |
| CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SUEQ_S_MMR6 = 1180 |
| CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SULE_D = 1181 |
| CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SULE_D_MMR6 = 1182 |
| CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SULE_S = 1183 |
| CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SULE_S_MMR6 = 1184 |
| CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SULT_D = 1185 |
| CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SULT_D_MMR6 = 1186 |
| CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SULT_S = 1187 |
| CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SULT_S_MMR6 = 1188 |
| CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SUN_D = 1189 |
| CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SUN_D_MMR6 = 1190 |
| CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SUN_S = 1191 |
| CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SUN_S_MMR6 = 1192 |
| CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_UEQ_D = 1193 |
| CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_UEQ_D_MMR6 = 1194 |
| CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_UEQ_S = 1195 |
| CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_UEQ_S_MMR6 = 1196 |
| CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_ULE_D = 1197 |
| CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_ULE_D_MMR6 = 1198 |
| CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_ULE_S = 1199 |
| CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_ULE_S_MMR6 = 1200 |
| CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_ULT_D = 1201 |
| CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_ULT_D_MMR6 = 1202 |
| CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_ULT_S = 1203 |
| CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_ULT_S_MMR6 = 1204 |
| CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_UN_D = 1205 |
| CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_UN_D_MMR6 = 1206 |
| CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_UN_S = 1207 |
| CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_UN_S_MMR6 = 1208 |
| CEFBS_HasStdEnc_HasMSA, // COPY_S_B = 1209 |
| CEFBS_HasStdEnc_HasMSA_HasMips64, // COPY_S_D = 1210 |
| CEFBS_HasStdEnc_HasMSA, // COPY_S_H = 1211 |
| CEFBS_HasStdEnc_HasMSA, // COPY_S_W = 1212 |
| CEFBS_HasStdEnc_HasMSA, // COPY_U_B = 1213 |
| CEFBS_HasStdEnc_HasMSA, // COPY_U_H = 1214 |
| CEFBS_HasStdEnc_HasMSA_HasMips64, // COPY_U_W = 1215 |
| CEFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, // CRC32B = 1216 |
| CEFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, // CRC32CB = 1217 |
| CEFBS_HasStdEnc_HasMips64r6_HasCRC_NotInMicroMips, // CRC32CD = 1218 |
| CEFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, // CRC32CH = 1219 |
| CEFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, // CRC32CW = 1220 |
| CEFBS_HasStdEnc_HasMips64r6_HasCRC_NotInMicroMips, // CRC32D = 1221 |
| CEFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, // CRC32H = 1222 |
| CEFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, // CRC32W = 1223 |
| CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // CTC1 = 1224 |
| CEFBS_InMicroMips_IsNotSoftFloat, // CTC1_MM = 1225 |
| CEFBS_InMicroMips, // CTC2_MM = 1226 |
| CEFBS_HasStdEnc_HasMSA, // CTCMSA = 1227 |
| CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_D32_S = 1228 |
| CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // CVT_D32_S_MM = 1229 |
| CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_D32_W = 1230 |
| CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // CVT_D32_W_MM = 1231 |
| CEFBS_HasStdEnc_IsFP64bit_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, // CVT_D64_L = 1232 |
| CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_D64_S = 1233 |
| CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // CVT_D64_S_MM = 1234 |
| CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_D64_W = 1235 |
| CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // CVT_D64_W_MM = 1236 |
| CEFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat, // CVT_D_L_MMR6 = 1237 |
| CEFBS_HasStdEnc_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, // CVT_L_D64 = 1238 |
| CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // CVT_L_D64_MM = 1239 |
| CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CVT_L_D_MMR6 = 1240 |
| CEFBS_HasStdEnc_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, // CVT_L_S = 1241 |
| CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // CVT_L_S_MM = 1242 |
| CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CVT_L_S_MMR6 = 1243 |
| CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D, // CVT_PS_PW64 = 1244 |
| CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // CVT_PS_S64 = 1245 |
| CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D, // CVT_PW_PS64 = 1246 |
| CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_S_D32 = 1247 |
| CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // CVT_S_D32_MM = 1248 |
| CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_S_D64 = 1249 |
| CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // CVT_S_D64_MM = 1250 |
| CEFBS_HasStdEnc_IsFP64bit_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, // CVT_S_L = 1251 |
| CEFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat, // CVT_S_L_MMR6 = 1252 |
| CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // CVT_S_PL64 = 1253 |
| CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // CVT_S_PU64 = 1254 |
| CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // CVT_S_W = 1255 |
| CEFBS_InMicroMips_IsNotSoftFloat, // CVT_S_W_MM = 1256 |
| CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CVT_S_W_MMR6 = 1257 |
| CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_W_D32 = 1258 |
| CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // CVT_W_D32_MM = 1259 |
| CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_W_D64 = 1260 |
| CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // CVT_W_D64_MM = 1261 |
| CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // CVT_W_S = 1262 |
| CEFBS_InMicroMips_IsNotSoftFloat, // CVT_W_S_MM = 1263 |
| CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CVT_W_S_MMR6 = 1264 |
| CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_EQ_D32 = 1265 |
| CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_EQ_D32_MM = 1266 |
| CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_EQ_D64 = 1267 |
| CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_EQ_D64_MM = 1268 |
| CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_EQ_S = 1269 |
| CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_EQ_S_MM = 1270 |
| CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_F_D32 = 1271 |
| CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_F_D32_MM = 1272 |
| CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_F_D64 = 1273 |
| CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_F_D64_MM = 1274 |
| CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_F_S = 1275 |
| CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_F_S_MM = 1276 |
| CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_LE_D32 = 1277 |
| CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_LE_D32_MM = 1278 |
| CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_LE_D64 = 1279 |
| CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_LE_D64_MM = 1280 |
| CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_LE_S = 1281 |
| CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_LE_S_MM = 1282 |
| CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_LT_D32 = 1283 |
| CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_LT_D32_MM = 1284 |
| CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_LT_D64 = 1285 |
| CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_LT_D64_MM = 1286 |
| CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_LT_S = 1287 |
| CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_LT_S_MM = 1288 |
| CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGE_D32 = 1289 |
| CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGE_D32_MM = 1290 |
| CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGE_D64 = 1291 |
| CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGE_D64_MM = 1292 |
| CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGE_S = 1293 |
| CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_NGE_S_MM = 1294 |
| CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGLE_D32 = 1295 |
| CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGLE_D32_MM = 1296 |
| CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGLE_D64 = 1297 |
| CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGLE_D64_MM = 1298 |
| CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGLE_S = 1299 |
| CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_NGLE_S_MM = 1300 |
| CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGL_D32 = 1301 |
| CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGL_D32_MM = 1302 |
| CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGL_D64 = 1303 |
| CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGL_D64_MM = 1304 |
| CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGL_S = 1305 |
| CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_NGL_S_MM = 1306 |
| CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGT_D32 = 1307 |
| CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGT_D32_MM = 1308 |
| CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGT_D64 = 1309 |
| CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGT_D64_MM = 1310 |
| CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGT_S = 1311 |
| CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_NGT_S_MM = 1312 |
| CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_OLE_D32 = 1313 |
| CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_OLE_D32_MM = 1314 |
| CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_OLE_D64 = 1315 |
| CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_OLE_D64_MM = 1316 |
| CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_OLE_S = 1317 |
| CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_OLE_S_MM = 1318 |
| CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_OLT_D32 = 1319 |
| CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_OLT_D32_MM = 1320 |
| CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_OLT_D64 = 1321 |
| CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_OLT_D64_MM = 1322 |
| CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_OLT_S = 1323 |
| CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_OLT_S_MM = 1324 |
| CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_SEQ_D32 = 1325 |
| CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_SEQ_D32_MM = 1326 |
| CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_SEQ_D64 = 1327 |
| CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_SEQ_D64_MM = 1328 |
| CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_SEQ_S = 1329 |
| CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_SEQ_S_MM = 1330 |
| CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_SF_D32 = 1331 |
| CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_SF_D32_MM = 1332 |
| CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_SF_D64 = 1333 |
| CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_SF_D64_MM = 1334 |
| CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_SF_S = 1335 |
| CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_SF_S_MM = 1336 |
| CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_UEQ_D32 = 1337 |
| CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_UEQ_D32_MM = 1338 |
| CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_UEQ_D64 = 1339 |
| CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_UEQ_D64_MM = 1340 |
| CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_UEQ_S = 1341 |
| CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_UEQ_S_MM = 1342 |
| CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_ULE_D32 = 1343 |
| CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_ULE_D32_MM = 1344 |
| CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_ULE_D64 = 1345 |
| CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_ULE_D64_MM = 1346 |
| CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_ULE_S = 1347 |
| CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_ULE_S_MM = 1348 |
| CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_ULT_D32 = 1349 |
| CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_ULT_D32_MM = 1350 |
| CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_ULT_D64 = 1351 |
| CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_ULT_D64_MM = 1352 |
| CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_ULT_S = 1353 |
| CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_ULT_S_MM = 1354 |
| CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_UN_D32 = 1355 |
| CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_UN_D32_MM = 1356 |
| CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_UN_D64 = 1357 |
| CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_UN_D64_MM = 1358 |
| CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_UN_S = 1359 |
| CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_UN_S_MM = 1360 |
| CEFBS_InMips16Mode, // CmpRxRy16 = 1361 |
| CEFBS_InMips16Mode, // CmpiRxImm16 = 1362 |
| CEFBS_InMips16Mode, // CmpiRxImmX16 = 1363 |
| CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DADD = 1364 |
| CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // DADDi = 1365 |
| CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DADDiu = 1366 |
| CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DADDu = 1367 |
| CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DAHI = 1368 |
| CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DALIGN = 1369 |
| CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DATI = 1370 |
| CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DAUI = 1371 |
| CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DBITSWAP = 1372 |
| CEFBS_HasStdEnc_IsGP64bit_HasMips64_NotMips64r6_NotInMicroMips, // DCLO = 1373 |
| CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DCLO_R6 = 1374 |
| CEFBS_HasStdEnc_IsGP64bit_HasMips64_NotMips64r6_NotInMicroMips, // DCLZ = 1375 |
| CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DCLZ_R6 = 1376 |
| CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DDIV = 1377 |
| CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DDIVU = 1378 |
| CEFBS_HasStdEnc_HasMips32_NotInMicroMips, // DERET = 1379 |
| CEFBS_InMicroMips, // DERET_MM = 1380 |
| CEFBS_InMicroMips_HasMips32r6, // DERET_MMR6 = 1381 |
| CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DEXT = 1382 |
| CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DEXT64_32 = 1383 |
| CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DEXTM = 1384 |
| CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DEXTU = 1385 |
| CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // DI = 1386 |
| CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DINS = 1387 |
| CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DINSM = 1388 |
| CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DINSU = 1389 |
| CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // DIV = 1390 |
| CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // DIVU = 1391 |
| CEFBS_InMicroMips_HasMips32r6, // DIVU_MMR6 = 1392 |
| CEFBS_InMicroMips_HasMips32r6, // DIV_MMR6 = 1393 |
| CEFBS_HasStdEnc_HasMSA, // DIV_S_B = 1394 |
| CEFBS_HasStdEnc_HasMSA, // DIV_S_D = 1395 |
| CEFBS_HasStdEnc_HasMSA, // DIV_S_H = 1396 |
| CEFBS_HasStdEnc_HasMSA, // DIV_S_W = 1397 |
| CEFBS_HasStdEnc_HasMSA, // DIV_U_B = 1398 |
| CEFBS_HasStdEnc_HasMSA, // DIV_U_D = 1399 |
| CEFBS_HasStdEnc_HasMSA, // DIV_U_H = 1400 |
| CEFBS_HasStdEnc_HasMSA, // DIV_U_W = 1401 |
| CEFBS_InMicroMips, // DI_MM = 1402 |
| CEFBS_InMicroMips_HasMips32r6, // DI_MMR6 = 1403 |
| CEFBS_HasStdEnc_HasMSA_HasMips64, // DLSA = 1404 |
| CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DLSA_R6 = 1405 |
| CEFBS_HasStdEnc_IsGP64bit_HasMips3, // DMFC0 = 1406 |
| CEFBS_HasStdEnc_HasMips3_IsNotSoftFloat_NotInMicroMips, // DMFC1 = 1407 |
| CEFBS_HasStdEnc_IsGP64bit_HasMips3, // DMFC2 = 1408 |
| CEFBS_HasCnMips, // DMFC2_OCTEON = 1409 |
| CEFBS_HasStdEnc_HasMips64r5_HasVirt, // DMFGC0 = 1410 |
| CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DMOD = 1411 |
| CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DMODU = 1412 |
| CEFBS_HasStdEnc_HasMT_NotInMicroMips, // DMT = 1413 |
| CEFBS_HasStdEnc_IsGP64bit_HasMips3, // DMTC0 = 1414 |
| CEFBS_HasStdEnc_HasMips3_IsNotSoftFloat_NotInMicroMips, // DMTC1 = 1415 |
| CEFBS_HasStdEnc_IsGP64bit_HasMips3, // DMTC2 = 1416 |
| CEFBS_HasCnMips, // DMTC2_OCTEON = 1417 |
| CEFBS_HasStdEnc_HasMips64r5_HasVirt, // DMTGC0 = 1418 |
| CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DMUH = 1419 |
| CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DMUHU = 1420 |
| CEFBS_HasCnMips, // DMUL = 1421 |
| CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DMULT = 1422 |
| CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DMULTu = 1423 |
| CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DMULU = 1424 |
| CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DMUL_R6 = 1425 |
| CEFBS_HasStdEnc_HasMSA, // DOTP_S_D = 1426 |
| CEFBS_HasStdEnc_HasMSA, // DOTP_S_H = 1427 |
| CEFBS_HasStdEnc_HasMSA, // DOTP_S_W = 1428 |
| CEFBS_HasStdEnc_HasMSA, // DOTP_U_D = 1429 |
| CEFBS_HasStdEnc_HasMSA, // DOTP_U_H = 1430 |
| CEFBS_HasStdEnc_HasMSA, // DOTP_U_W = 1431 |
| CEFBS_HasStdEnc_HasMSA, // DPADD_S_D = 1432 |
| CEFBS_HasStdEnc_HasMSA, // DPADD_S_H = 1433 |
| CEFBS_HasStdEnc_HasMSA, // DPADD_S_W = 1434 |
| CEFBS_HasStdEnc_HasMSA, // DPADD_U_D = 1435 |
| CEFBS_HasStdEnc_HasMSA, // DPADD_U_H = 1436 |
| CEFBS_HasStdEnc_HasMSA, // DPADD_U_W = 1437 |
| CEFBS_HasDSPR2, // DPAQX_SA_W_PH = 1438 |
| CEFBS_InMicroMips_HasDSPR2, // DPAQX_SA_W_PH_MMR2 = 1439 |
| CEFBS_HasDSPR2, // DPAQX_S_W_PH = 1440 |
| CEFBS_InMicroMips_HasDSPR2, // DPAQX_S_W_PH_MMR2 = 1441 |
| CEFBS_HasDSP, // DPAQ_SA_L_W = 1442 |
| CEFBS_InMicroMips_HasDSP, // DPAQ_SA_L_W_MM = 1443 |
| CEFBS_HasDSP, // DPAQ_S_W_PH = 1444 |
| CEFBS_InMicroMips_HasDSP, // DPAQ_S_W_PH_MM = 1445 |
| CEFBS_HasDSP, // DPAU_H_QBL = 1446 |
| CEFBS_InMicroMips_HasDSP, // DPAU_H_QBL_MM = 1447 |
| CEFBS_HasDSP, // DPAU_H_QBR = 1448 |
| CEFBS_InMicroMips_HasDSP, // DPAU_H_QBR_MM = 1449 |
| CEFBS_HasDSPR2, // DPAX_W_PH = 1450 |
| CEFBS_InMicroMips_HasDSPR2, // DPAX_W_PH_MMR2 = 1451 |
| CEFBS_HasDSPR2, // DPA_W_PH = 1452 |
| CEFBS_InMicroMips_HasDSPR2, // DPA_W_PH_MMR2 = 1453 |
| CEFBS_HasCnMips, // DPOP = 1454 |
| CEFBS_HasDSPR2, // DPSQX_SA_W_PH = 1455 |
| CEFBS_InMicroMips_HasDSPR2, // DPSQX_SA_W_PH_MMR2 = 1456 |
| CEFBS_HasDSPR2, // DPSQX_S_W_PH = 1457 |
| CEFBS_InMicroMips_HasDSPR2, // DPSQX_S_W_PH_MMR2 = 1458 |
| CEFBS_HasDSP, // DPSQ_SA_L_W = 1459 |
| CEFBS_InMicroMips_HasDSP, // DPSQ_SA_L_W_MM = 1460 |
| CEFBS_HasDSP, // DPSQ_S_W_PH = 1461 |
| CEFBS_InMicroMips_HasDSP, // DPSQ_S_W_PH_MM = 1462 |
| CEFBS_HasStdEnc_HasMSA, // DPSUB_S_D = 1463 |
| CEFBS_HasStdEnc_HasMSA, // DPSUB_S_H = 1464 |
| CEFBS_HasStdEnc_HasMSA, // DPSUB_S_W = 1465 |
| CEFBS_HasStdEnc_HasMSA, // DPSUB_U_D = 1466 |
| CEFBS_HasStdEnc_HasMSA, // DPSUB_U_H = 1467 |
| CEFBS_HasStdEnc_HasMSA, // DPSUB_U_W = 1468 |
| CEFBS_HasDSP, // DPSU_H_QBL = 1469 |
| CEFBS_InMicroMips_HasDSP, // DPSU_H_QBL_MM = 1470 |
| CEFBS_HasDSP, // DPSU_H_QBR = 1471 |
| CEFBS_InMicroMips_HasDSP, // DPSU_H_QBR_MM = 1472 |
| CEFBS_HasDSPR2, // DPSX_W_PH = 1473 |
| CEFBS_InMicroMips_HasDSPR2, // DPSX_W_PH_MMR2 = 1474 |
| CEFBS_HasDSPR2, // DPS_W_PH = 1475 |
| CEFBS_InMicroMips_HasDSPR2, // DPS_W_PH_MMR2 = 1476 |
| CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DROTR = 1477 |
| CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DROTR32 = 1478 |
| CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DROTRV = 1479 |
| CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DSBH = 1480 |
| CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DSDIV = 1481 |
| CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DSHD = 1482 |
| CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSLL = 1483 |
| CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSLL32 = 1484 |
| CEFBS_NotInMips16Mode_IsGP64bit, // DSLL64_32 = 1485 |
| CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSLLV = 1486 |
| CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSRA = 1487 |
| CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSRA32 = 1488 |
| CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSRAV = 1489 |
| CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSRL = 1490 |
| CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSRL32 = 1491 |
| CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSRLV = 1492 |
| CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSUB = 1493 |
| CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSUBu = 1494 |
| CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DUDIV = 1495 |
| CEFBS_HasStdEnc_HasMips32r6, // DVP = 1496 |
| CEFBS_HasStdEnc_HasMT_NotInMicroMips, // DVPE = 1497 |
| CEFBS_InMicroMips_HasMips32r6, // DVP_MMR6 = 1498 |
| CEFBS_InMips16Mode, // DivRxRy16 = 1499 |
| CEFBS_InMips16Mode, // DivuRxRy16 = 1500 |
| CEFBS_HasStdEnc_NotInMicroMips, // EHB = 1501 |
| CEFBS_InMicroMips, // EHB_MM = 1502 |
| CEFBS_InMicroMips_HasMips32r6, // EHB_MMR6 = 1503 |
| CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // EI = 1504 |
| CEFBS_InMicroMips, // EI_MM = 1505 |
| CEFBS_InMicroMips_HasMips32r6, // EI_MMR6 = 1506 |
| CEFBS_HasStdEnc_HasMT_NotInMicroMips, // EMT = 1507 |
| CEFBS_HasStdEnc_HasMips3_32_NotInMicroMips, // ERET = 1508 |
| CEFBS_HasStdEnc_HasMips32r5_NotInMicroMips, // ERETNC = 1509 |
| CEFBS_InMicroMips_HasMips32r6, // ERETNC_MMR6 = 1510 |
| CEFBS_InMicroMips, // ERET_MM = 1511 |
| CEFBS_InMicroMips_HasMips32r6, // ERET_MMR6 = 1512 |
| CEFBS_HasStdEnc_HasMips32r6, // EVP = 1513 |
| CEFBS_HasStdEnc_HasMT_NotInMicroMips, // EVPE = 1514 |
| CEFBS_InMicroMips_HasMips32r6, // EVP_MMR6 = 1515 |
| CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // EXT = 1516 |
| CEFBS_HasDSP, // EXTP = 1517 |
| CEFBS_HasDSP, // EXTPDP = 1518 |
| CEFBS_HasDSP, // EXTPDPV = 1519 |
| CEFBS_InMicroMips_HasDSP, // EXTPDPV_MM = 1520 |
| CEFBS_InMicroMips_HasDSP, // EXTPDP_MM = 1521 |
| CEFBS_HasDSP, // EXTPV = 1522 |
| CEFBS_InMicroMips_HasDSP, // EXTPV_MM = 1523 |
| CEFBS_InMicroMips_HasDSP, // EXTP_MM = 1524 |
| CEFBS_HasDSP, // EXTRV_RS_W = 1525 |
| CEFBS_InMicroMips_HasDSP, // EXTRV_RS_W_MM = 1526 |
| CEFBS_HasDSP, // EXTRV_R_W = 1527 |
| CEFBS_InMicroMips_HasDSP, // EXTRV_R_W_MM = 1528 |
| CEFBS_HasDSP, // EXTRV_S_H = 1529 |
| CEFBS_InMicroMips_HasDSP, // EXTRV_S_H_MM = 1530 |
| CEFBS_HasDSP, // EXTRV_W = 1531 |
| CEFBS_InMicroMips_HasDSP, // EXTRV_W_MM = 1532 |
| CEFBS_HasDSP, // EXTR_RS_W = 1533 |
| CEFBS_InMicroMips_HasDSP, // EXTR_RS_W_MM = 1534 |
| CEFBS_HasDSP, // EXTR_R_W = 1535 |
| CEFBS_InMicroMips_HasDSP, // EXTR_R_W_MM = 1536 |
| CEFBS_HasDSP, // EXTR_S_H = 1537 |
| CEFBS_InMicroMips_HasDSP, // EXTR_S_H_MM = 1538 |
| CEFBS_HasDSP, // EXTR_W = 1539 |
| CEFBS_InMicroMips_HasDSP, // EXTR_W_MM = 1540 |
| CEFBS_HasMips64_HasCnMips_NotInMicroMips, // EXTS = 1541 |
| CEFBS_HasMips64_HasCnMips_NotInMicroMips, // EXTS32 = 1542 |
| CEFBS_InMicroMips_NotMips32r6, // EXT_MM = 1543 |
| CEFBS_InMicroMips_HasMips32r6, // EXT_MMR6 = 1544 |
| CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // FABS_D32 = 1545 |
| CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FABS_D32_MM = 1546 |
| CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // FABS_D64 = 1547 |
| CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FABS_D64_MM = 1548 |
| CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // FABS_S = 1549 |
| CEFBS_InMicroMips_IsNotSoftFloat, // FABS_S_MM = 1550 |
| CEFBS_HasStdEnc_HasMSA, // FADD_D = 1551 |
| CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // FADD_D32 = 1552 |
| CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FADD_D32_MM = 1553 |
| CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // FADD_D64 = 1554 |
| CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FADD_D64_MM = 1555 |
| CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // FADD_PS64 = 1556 |
| CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // FADD_S = 1557 |
| CEFBS_InMicroMips_IsNotSoftFloat, // FADD_S_MM = 1558 |
| CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FADD_S_MMR6 = 1559 |
| CEFBS_HasStdEnc_HasMSA, // FADD_W = 1560 |
| CEFBS_HasStdEnc_HasMSA, // FCAF_D = 1561 |
| CEFBS_HasStdEnc_HasMSA, // FCAF_W = 1562 |
| CEFBS_HasStdEnc_HasMSA, // FCEQ_D = 1563 |
| CEFBS_HasStdEnc_HasMSA, // FCEQ_W = 1564 |
| CEFBS_HasStdEnc_HasMSA, // FCLASS_D = 1565 |
| CEFBS_HasStdEnc_HasMSA, // FCLASS_W = 1566 |
| CEFBS_HasStdEnc_HasMSA, // FCLE_D = 1567 |
| CEFBS_HasStdEnc_HasMSA, // FCLE_W = 1568 |
| CEFBS_HasStdEnc_HasMSA, // FCLT_D = 1569 |
| CEFBS_HasStdEnc_HasMSA, // FCLT_W = 1570 |
| CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // FCMP_D32 = 1571 |
| CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // FCMP_D32_MM = 1572 |
| CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat, // FCMP_D64 = 1573 |
| CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // FCMP_S32 = 1574 |
| CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // FCMP_S32_MM = 1575 |
| CEFBS_HasStdEnc_HasMSA, // FCNE_D = 1576 |
| CEFBS_HasStdEnc_HasMSA, // FCNE_W = 1577 |
| CEFBS_HasStdEnc_HasMSA, // FCOR_D = 1578 |
| CEFBS_HasStdEnc_HasMSA, // FCOR_W = 1579 |
| CEFBS_HasStdEnc_HasMSA, // FCUEQ_D = 1580 |
| CEFBS_HasStdEnc_HasMSA, // FCUEQ_W = 1581 |
| CEFBS_HasStdEnc_HasMSA, // FCULE_D = 1582 |
| CEFBS_HasStdEnc_HasMSA, // FCULE_W = 1583 |
| CEFBS_HasStdEnc_HasMSA, // FCULT_D = 1584 |
| CEFBS_HasStdEnc_HasMSA, // FCULT_W = 1585 |
| CEFBS_HasStdEnc_HasMSA, // FCUNE_D = 1586 |
| CEFBS_HasStdEnc_HasMSA, // FCUNE_W = 1587 |
| CEFBS_HasStdEnc_HasMSA, // FCUN_D = 1588 |
| CEFBS_HasStdEnc_HasMSA, // FCUN_W = 1589 |
| CEFBS_HasStdEnc_HasMSA, // FDIV_D = 1590 |
| CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // FDIV_D32 = 1591 |
| CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FDIV_D32_MM = 1592 |
| CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // FDIV_D64 = 1593 |
| CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FDIV_D64_MM = 1594 |
| CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // FDIV_S = 1595 |
| CEFBS_InMicroMips_IsNotSoftFloat, // FDIV_S_MM = 1596 |
| CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FDIV_S_MMR6 = 1597 |
| CEFBS_HasStdEnc_HasMSA, // FDIV_W = 1598 |
| CEFBS_HasStdEnc_HasMSA, // FEXDO_H = 1599 |
| CEFBS_HasStdEnc_HasMSA, // FEXDO_W = 1600 |
| CEFBS_HasStdEnc_HasMSA, // FEXP2_D = 1601 |
| CEFBS_HasStdEnc_HasMSA, // FEXP2_W = 1602 |
| CEFBS_HasStdEnc_HasMSA, // FEXUPL_D = 1603 |
| CEFBS_HasStdEnc_HasMSA, // FEXUPL_W = 1604 |
| CEFBS_HasStdEnc_HasMSA, // FEXUPR_D = 1605 |
| CEFBS_HasStdEnc_HasMSA, // FEXUPR_W = 1606 |
| CEFBS_HasStdEnc_HasMSA, // FFINT_S_D = 1607 |
| CEFBS_HasStdEnc_HasMSA, // FFINT_S_W = 1608 |
| CEFBS_HasStdEnc_HasMSA, // FFINT_U_D = 1609 |
| CEFBS_HasStdEnc_HasMSA, // FFINT_U_W = 1610 |
| CEFBS_HasStdEnc_HasMSA, // FFQL_D = 1611 |
| CEFBS_HasStdEnc_HasMSA, // FFQL_W = 1612 |
| CEFBS_HasStdEnc_HasMSA, // FFQR_D = 1613 |
| CEFBS_HasStdEnc_HasMSA, // FFQR_W = 1614 |
| CEFBS_HasStdEnc_HasMSA, // FILL_B = 1615 |
| CEFBS_HasStdEnc_HasMSA_HasMips64, // FILL_D = 1616 |
| CEFBS_HasStdEnc_HasMSA, // FILL_H = 1617 |
| CEFBS_HasStdEnc_HasMSA, // FILL_W = 1618 |
| CEFBS_HasStdEnc_HasMSA, // FLOG2_D = 1619 |
| CEFBS_HasStdEnc_HasMSA, // FLOG2_W = 1620 |
| CEFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips, // FLOOR_L_D64 = 1621 |
| CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FLOOR_L_D_MMR6 = 1622 |
| CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // FLOOR_L_S = 1623 |
| CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FLOOR_L_S_MMR6 = 1624 |
| CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // FLOOR_W_D32 = 1625 |
| CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // FLOOR_W_D64 = 1626 |
| CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FLOOR_W_D_MMR6 = 1627 |
| CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FLOOR_W_MM = 1628 |
| CEFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips, // FLOOR_W_S = 1629 |
| CEFBS_InMicroMips_IsNotSoftFloat, // FLOOR_W_S_MM = 1630 |
| CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FLOOR_W_S_MMR6 = 1631 |
| CEFBS_HasStdEnc_HasMSA, // FMADD_D = 1632 |
| CEFBS_HasStdEnc_HasMSA, // FMADD_W = 1633 |
| CEFBS_HasStdEnc_HasMSA, // FMAX_A_D = 1634 |
| CEFBS_HasStdEnc_HasMSA, // FMAX_A_W = 1635 |
| CEFBS_HasStdEnc_HasMSA, // FMAX_D = 1636 |
| CEFBS_HasStdEnc_HasMSA, // FMAX_W = 1637 |
| CEFBS_HasStdEnc_HasMSA, // FMIN_A_D = 1638 |
| CEFBS_HasStdEnc_HasMSA, // FMIN_A_W = 1639 |
| CEFBS_HasStdEnc_HasMSA, // FMIN_D = 1640 |
| CEFBS_HasStdEnc_HasMSA, // FMIN_W = 1641 |
| CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // FMOV_D32 = 1642 |
| CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FMOV_D32_MM = 1643 |
| CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // FMOV_D64 = 1644 |
| CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FMOV_D64_MM = 1645 |
| CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FMOV_D_MMR6 = 1646 |
| CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // FMOV_S = 1647 |
| CEFBS_InMicroMips_IsNotSoftFloat, // FMOV_S_MM = 1648 |
| CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FMOV_S_MMR6 = 1649 |
| CEFBS_HasStdEnc_HasMSA, // FMSUB_D = 1650 |
| CEFBS_HasStdEnc_HasMSA, // FMSUB_W = 1651 |
| CEFBS_HasStdEnc_HasMSA, // FMUL_D = 1652 |
| CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // FMUL_D32 = 1653 |
| CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FMUL_D32_MM = 1654 |
| CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // FMUL_D64 = 1655 |
| CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FMUL_D64_MM = 1656 |
| CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // FMUL_PS64 = 1657 |
| CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // FMUL_S = 1658 |
| CEFBS_InMicroMips_IsNotSoftFloat, // FMUL_S_MM = 1659 |
| CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FMUL_S_MMR6 = 1660 |
| CEFBS_HasStdEnc_HasMSA, // FMUL_W = 1661 |
| CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // FNEG_D32 = 1662 |
| CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FNEG_D32_MM = 1663 |
| CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // FNEG_D64 = 1664 |
| CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FNEG_D64_MM = 1665 |
| CEFBS_HasStdEnc_IsNotSoftFloat, // FNEG_S = 1666 |
| CEFBS_InMicroMips_IsNotSoftFloat, // FNEG_S_MM = 1667 |
| CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FNEG_S_MMR6 = 1668 |
| CEFBS_HasStdEnc_HasMT_NotInMicroMips, // FORK = 1669 |
| CEFBS_HasStdEnc_HasMSA, // FRCP_D = 1670 |
| CEFBS_HasStdEnc_HasMSA, // FRCP_W = 1671 |
| CEFBS_HasStdEnc_HasMSA, // FRINT_D = 1672 |
| CEFBS_HasStdEnc_HasMSA, // FRINT_W = 1673 |
| CEFBS_HasStdEnc_HasMSA, // FRSQRT_D = 1674 |
| CEFBS_HasStdEnc_HasMSA, // FRSQRT_W = 1675 |
| CEFBS_HasStdEnc_HasMSA, // FSAF_D = 1676 |
| CEFBS_HasStdEnc_HasMSA, // FSAF_W = 1677 |
| CEFBS_HasStdEnc_HasMSA, // FSEQ_D = 1678 |
| CEFBS_HasStdEnc_HasMSA, // FSEQ_W = 1679 |
| CEFBS_HasStdEnc_HasMSA, // FSLE_D = 1680 |
| CEFBS_HasStdEnc_HasMSA, // FSLE_W = 1681 |
| CEFBS_HasStdEnc_HasMSA, // FSLT_D = 1682 |
| CEFBS_HasStdEnc_HasMSA, // FSLT_W = 1683 |
| CEFBS_HasStdEnc_HasMSA, // FSNE_D = 1684 |
| CEFBS_HasStdEnc_HasMSA, // FSNE_W = 1685 |
| CEFBS_HasStdEnc_HasMSA, // FSOR_D = 1686 |
| CEFBS_HasStdEnc_HasMSA, // FSOR_W = 1687 |
| CEFBS_HasStdEnc_HasMSA, // FSQRT_D = 1688 |
| CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // FSQRT_D32 = 1689 |
| CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FSQRT_D32_MM = 1690 |
| CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // FSQRT_D64 = 1691 |
| CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FSQRT_D64_MM = 1692 |
| CEFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips, // FSQRT_S = 1693 |
| CEFBS_InMicroMips_IsNotSoftFloat, // FSQRT_S_MM = 1694 |
| CEFBS_HasStdEnc_HasMSA, // FSQRT_W = 1695 |
| CEFBS_HasStdEnc_HasMSA, // FSUB_D = 1696 |
| CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // FSUB_D32 = 1697 |
| CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FSUB_D32_MM = 1698 |
| CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // FSUB_D64 = 1699 |
| CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FSUB_D64_MM = 1700 |
| CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // FSUB_PS64 = 1701 |
| CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // FSUB_S = 1702 |
| CEFBS_InMicroMips_IsNotSoftFloat, // FSUB_S_MM = 1703 |
| CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FSUB_S_MMR6 = 1704 |
| CEFBS_HasStdEnc_HasMSA, // FSUB_W = 1705 |
| CEFBS_HasStdEnc_HasMSA, // FSUEQ_D = 1706 |
| CEFBS_HasStdEnc_HasMSA, // FSUEQ_W = 1707 |
| CEFBS_HasStdEnc_HasMSA, // FSULE_D = 1708 |
| CEFBS_HasStdEnc_HasMSA, // FSULE_W = 1709 |
| CEFBS_HasStdEnc_HasMSA, // FSULT_D = 1710 |
| CEFBS_HasStdEnc_HasMSA, // FSULT_W = 1711 |
| CEFBS_HasStdEnc_HasMSA, // FSUNE_D = 1712 |
| CEFBS_HasStdEnc_HasMSA, // FSUNE_W = 1713 |
| CEFBS_HasStdEnc_HasMSA, // FSUN_D = 1714 |
| CEFBS_HasStdEnc_HasMSA, // FSUN_W = 1715 |
| CEFBS_HasStdEnc_HasMSA, // FTINT_S_D = 1716 |
| CEFBS_HasStdEnc_HasMSA, // FTINT_S_W = 1717 |
| CEFBS_HasStdEnc_HasMSA, // FTINT_U_D = 1718 |
| CEFBS_HasStdEnc_HasMSA, // FTINT_U_W = 1719 |
| CEFBS_HasStdEnc_HasMSA, // FTQ_H = 1720 |
| CEFBS_HasStdEnc_HasMSA, // FTQ_W = 1721 |
| CEFBS_HasStdEnc_HasMSA, // FTRUNC_S_D = 1722 |
| CEFBS_HasStdEnc_HasMSA, // FTRUNC_S_W = 1723 |
| CEFBS_HasStdEnc_HasMSA, // FTRUNC_U_D = 1724 |
| CEFBS_HasStdEnc_HasMSA, // FTRUNC_U_W = 1725 |
| CEFBS_HasStdEnc_HasMips32r6_HasGINV_NotInMicroMips, // GINVI = 1726 |
| CEFBS_InMicroMips_HasMips32r6_HasGINV, // GINVI_MMR6 = 1727 |
| CEFBS_HasStdEnc_HasMips32r6_HasGINV_NotInMicroMips, // GINVT = 1728 |
| CEFBS_InMicroMips_HasMips32r6_HasGINV, // GINVT_MMR6 = 1729 |
| CEFBS_HasStdEnc_HasMSA, // HADD_S_D = 1730 |
| CEFBS_HasStdEnc_HasMSA, // HADD_S_H = 1731 |
| CEFBS_HasStdEnc_HasMSA, // HADD_S_W = 1732 |
| CEFBS_HasStdEnc_HasMSA, // HADD_U_D = 1733 |
| CEFBS_HasStdEnc_HasMSA, // HADD_U_H = 1734 |
| CEFBS_HasStdEnc_HasMSA, // HADD_U_W = 1735 |
| CEFBS_HasStdEnc_HasMSA, // HSUB_S_D = 1736 |
| CEFBS_HasStdEnc_HasMSA, // HSUB_S_H = 1737 |
| CEFBS_HasStdEnc_HasMSA, // HSUB_S_W = 1738 |
| CEFBS_HasStdEnc_HasMSA, // HSUB_U_D = 1739 |
| CEFBS_HasStdEnc_HasMSA, // HSUB_U_H = 1740 |
| CEFBS_HasStdEnc_HasMSA, // HSUB_U_W = 1741 |
| CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // HYPCALL = 1742 |
| CEFBS_InMicroMips_HasMips32r5_HasVirt, // HYPCALL_MM = 1743 |
| CEFBS_HasStdEnc_HasMSA, // ILVEV_B = 1744 |
| CEFBS_HasStdEnc_HasMSA, // ILVEV_D = 1745 |
| CEFBS_HasStdEnc_HasMSA, // ILVEV_H = 1746 |
| CEFBS_HasStdEnc_HasMSA, // ILVEV_W = 1747 |
| CEFBS_HasStdEnc_HasMSA, // ILVL_B = 1748 |
| CEFBS_HasStdEnc_HasMSA, // ILVL_D = 1749 |
| CEFBS_HasStdEnc_HasMSA, // ILVL_H = 1750 |
| CEFBS_HasStdEnc_HasMSA, // ILVL_W = 1751 |
| CEFBS_HasStdEnc_HasMSA, // ILVOD_B = 1752 |
| CEFBS_HasStdEnc_HasMSA, // ILVOD_D = 1753 |
| CEFBS_HasStdEnc_HasMSA, // ILVOD_H = 1754 |
| CEFBS_HasStdEnc_HasMSA, // ILVOD_W = 1755 |
| CEFBS_HasStdEnc_HasMSA, // ILVR_B = 1756 |
| CEFBS_HasStdEnc_HasMSA, // ILVR_D = 1757 |
| CEFBS_HasStdEnc_HasMSA, // ILVR_H = 1758 |
| CEFBS_HasStdEnc_HasMSA, // ILVR_W = 1759 |
| CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // INS = 1760 |
| CEFBS_HasStdEnc_HasMSA, // INSERT_B = 1761 |
| CEFBS_HasStdEnc_HasMSA_HasMips64, // INSERT_D = 1762 |
| CEFBS_HasStdEnc_HasMSA, // INSERT_H = 1763 |
| CEFBS_HasStdEnc_HasMSA, // INSERT_W = 1764 |
| CEFBS_HasDSP, // INSV = 1765 |
| CEFBS_HasStdEnc_HasMSA, // INSVE_B = 1766 |
| CEFBS_HasStdEnc_HasMSA, // INSVE_D = 1767 |
| CEFBS_HasStdEnc_HasMSA, // INSVE_H = 1768 |
| CEFBS_HasStdEnc_HasMSA, // INSVE_W = 1769 |
| CEFBS_InMicroMips_HasDSP, // INSV_MM = 1770 |
| CEFBS_InMicroMips_NotMips32r6, // INS_MM = 1771 |
| CEFBS_InMicroMips_HasMips32r6, // INS_MMR6 = 1772 |
| CEFBS_HasStdEnc_NotInMicroMips, // J = 1773 |
| CEFBS_HasStdEnc_NotInMicroMips, // JAL = 1774 |
| CEFBS_HasStdEnc_NotInMicroMips_NoIndirectJumpGuards, // JALR = 1775 |
| CEFBS_InMicroMips_NotMips32r6, // JALR16_MM = 1776 |
| CEFBS_NotInMips16Mode_IsPTR64bit, // JALR64 = 1777 |
| CEFBS_InMicroMips_HasMips32r6, // JALRC16_MMR6 = 1778 |
| CEFBS_InMicroMips_HasMips32r6, // JALRC_HB_MMR6 = 1779 |
| CEFBS_InMicroMips_HasMips32r6, // JALRC_MMR6 = 1780 |
| CEFBS_InMicroMips_NotMips32r6, // JALRS16_MM = 1781 |
| CEFBS_InMicroMips_NotMips32r6, // JALRS_MM = 1782 |
| CEFBS_HasStdEnc_HasMips32, // JALR_HB = 1783 |
| CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // JALR_HB64 = 1784 |
| CEFBS_InMicroMips_NotMips32r6, // JALR_MM = 1785 |
| CEFBS_InMicroMips_NotMips32r6, // JALS_MM = 1786 |
| CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // JALX = 1787 |
| CEFBS_InMicroMips_NotMips32r6, // JALX_MM = 1788 |
| CEFBS_InMicroMips_NotMips32r6, // JAL_MM = 1789 |
| CEFBS_HasStdEnc_HasMips32r6, // JIALC = 1790 |
| CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // JIALC64 = 1791 |
| CEFBS_InMicroMips_HasMips32r6, // JIALC_MMR6 = 1792 |
| CEFBS_HasStdEnc_HasMips32r6, // JIC = 1793 |
| CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // JIC64 = 1794 |
| CEFBS_InMicroMips_HasMips32r6, // JIC_MMR6 = 1795 |
| CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // JR = 1796 |
| CEFBS_InMicroMips_NotMips32r6, // JR16_MM = 1797 |
| CEFBS_NotInMips16Mode_IsPTR64bit_NotInMicroMips, // JR64 = 1798 |
| CEFBS_InMicroMips_NotMips32r6, // JRADDIUSP = 1799 |
| CEFBS_InMicroMips_NotMips32r6, // JRC16_MM = 1800 |
| CEFBS_InMicroMips_HasMips32r6, // JRC16_MMR6 = 1801 |
| CEFBS_InMicroMips_HasMips32r6, // JRCADDIUSP_MMR6 = 1802 |
| CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6, // JR_HB = 1803 |
| CEFBS_HasStdEnc_HasMips64_NotMips64r6_NotInMicroMips, // JR_HB64 = 1804 |
| CEFBS_HasStdEnc_HasMips32r6, // JR_HB64_R6 = 1805 |
| CEFBS_HasStdEnc_HasMips32r6, // JR_HB_R6 = 1806 |
| CEFBS_InMicroMips_NotMips32r6, // JR_MM = 1807 |
| CEFBS_InMicroMips_NotMips32r6, // J_MM = 1808 |
| CEFBS_InMips16Mode, // Jal16 = 1809 |
| CEFBS_InMips16Mode, // JalB16 = 1810 |
| CEFBS_InMips16Mode, // JrRa16 = 1811 |
| CEFBS_InMips16Mode, // JrcRa16 = 1812 |
| CEFBS_InMips16Mode, // JrcRx16 = 1813 |
| CEFBS_InMips16Mode, // JumpLinkReg16 = 1814 |
| CEFBS_HasStdEnc_NotInMicroMips, // LB = 1815 |
| CEFBS_NotInMips16Mode_IsGP64bit, // LB64 = 1816 |
| CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // LBE = 1817 |
| CEFBS_InMicroMips_HasEVA, // LBE_MM = 1818 |
| CEFBS_InMicroMips, // LBU16_MM = 1819 |
| CEFBS_HasDSP, // LBUX = 1820 |
| CEFBS_InMicroMips_HasDSP, // LBUX_MM = 1821 |
| CEFBS_InMicroMips_HasMips32r6, // LBU_MMR6 = 1822 |
| CEFBS_InMicroMips, // LB_MM = 1823 |
| CEFBS_InMicroMips_HasMips32r6, // LB_MMR6 = 1824 |
| CEFBS_HasStdEnc_NotInMicroMips, // LBu = 1825 |
| CEFBS_NotInMips16Mode_IsGP64bit, // LBu64 = 1826 |
| CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // LBuE = 1827 |
| CEFBS_InMicroMips_HasEVA, // LBuE_MM = 1828 |
| CEFBS_InMicroMips, // LBu_MM = 1829 |
| CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // LD = 1830 |
| CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // LDC1 = 1831 |
| CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // LDC164 = 1832 |
| CEFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat, // LDC1_D64_MMR6 = 1833 |
| CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // LDC1_MM_D32 = 1834 |
| CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // LDC1_MM_D64 = 1835 |
| CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // LDC2 = 1836 |
| CEFBS_InMicroMips_HasMips32r6, // LDC2_MMR6 = 1837 |
| CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // LDC2_R6 = 1838 |
| CEFBS_HasStdEnc_HasMips2_NotCnMips_NotInMicroMips, // LDC3 = 1839 |
| CEFBS_HasStdEnc_HasMSA, // LDI_B = 1840 |
| CEFBS_HasStdEnc_HasMSA, // LDI_D = 1841 |
| CEFBS_HasStdEnc_HasMSA, // LDI_H = 1842 |
| CEFBS_HasStdEnc_HasMSA, // LDI_W = 1843 |
| CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // LDL = 1844 |
| CEFBS_HasStdEnc_HasMips64r6, // LDPC = 1845 |
| CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // LDR = 1846 |
| CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // LDXC1 = 1847 |
| CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat, // LDXC164 = 1848 |
| CEFBS_HasStdEnc_HasMSA, // LD_B = 1849 |
| CEFBS_HasStdEnc_HasMSA, // LD_D = 1850 |
| CEFBS_HasStdEnc_HasMSA, // LD_H = 1851 |
| CEFBS_HasStdEnc_HasMSA, // LD_W = 1852 |
| CEFBS_HasStdEnc_NotInMicroMips, // LEA_ADDiu = 1853 |
| CEFBS_NotInMips16Mode_IsGP64bit_NotInMicroMips, // LEA_ADDiu64 = 1854 |
| CEFBS_InMicroMips, // LEA_ADDiu_MM = 1855 |
| CEFBS_HasStdEnc_NotInMicroMips, // LH = 1856 |
| CEFBS_NotInMips16Mode_IsGP64bit, // LH64 = 1857 |
| CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // LHE = 1858 |
| CEFBS_InMicroMips_HasEVA, // LHE_MM = 1859 |
| CEFBS_InMicroMips, // LHU16_MM = 1860 |
| CEFBS_HasDSP, // LHX = 1861 |
| CEFBS_InMicroMips_HasDSP, // LHX_MM = 1862 |
| CEFBS_InMicroMips, // LH_MM = 1863 |
| CEFBS_HasStdEnc_NotInMicroMips, // LHu = 1864 |
| CEFBS_NotInMips16Mode_IsGP64bit, // LHu64 = 1865 |
| CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // LHuE = 1866 |
| CEFBS_InMicroMips_HasEVA, // LHuE_MM = 1867 |
| CEFBS_InMicroMips, // LHu_MM = 1868 |
| CEFBS_InMicroMips_NotMips32r6, // LI16_MM = 1869 |
| CEFBS_InMicroMips_HasMips32r6, // LI16_MMR6 = 1870 |
| CEFBS_HasStdEnc_IsPTR32bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // LL = 1871 |
| CEFBS_HasStdEnc_IsPTR64bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // LL64 = 1872 |
| CEFBS_HasStdEnc_IsPTR64bit_HasMips64r6_NotInMicroMips, // LL64_R6 = 1873 |
| CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // LLD = 1874 |
| CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // LLD_R6 = 1875 |
| CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // LLE = 1876 |
| CEFBS_InMicroMips_HasEVA, // LLE_MM = 1877 |
| CEFBS_InMicroMips_NotMips32r6, // LL_MM = 1878 |
| CEFBS_InMicroMips_HasMips32r6, // LL_MMR6 = 1879 |
| CEFBS_HasStdEnc_IsPTR32bit_HasMips32r6_NotInMicroMips, // LL_R6 = 1880 |
| CEFBS_HasStdEnc_HasMSA, // LSA = 1881 |
| CEFBS_InMicroMips_HasMips32r6, // LSA_MMR6 = 1882 |
| CEFBS_HasStdEnc_HasMips32r6, // LSA_R6 = 1883 |
| CEFBS_InMicroMips_HasMips32r6, // LUI_MMR6 = 1884 |
| CEFBS_HasStdEnc_NotFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // LUXC1 = 1885 |
| CEFBS_HasStdEnc_IsFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // LUXC164 = 1886 |
| CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // LUXC1_MM = 1887 |
| CEFBS_HasStdEnc_NotInMicroMips, // LUi = 1888 |
| CEFBS_NotInMips16Mode_IsGP64bit, // LUi64 = 1889 |
| CEFBS_InMicroMips_NotMips32r6, // LUi_MM = 1890 |
| CEFBS_HasStdEnc_NotInMicroMips, // LW = 1891 |
| CEFBS_InMicroMips, // LW16_MM = 1892 |
| CEFBS_NotInMips16Mode_IsGP64bit, // LW64 = 1893 |
| CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // LWC1 = 1894 |
| CEFBS_InMicroMips_IsNotSoftFloat, // LWC1_MM = 1895 |
| CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // LWC2 = 1896 |
| CEFBS_InMicroMips_HasMips32r6, // LWC2_MMR6 = 1897 |
| CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // LWC2_R6 = 1898 |
| CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotCnMips_NotInMicroMips, // LWC3 = 1899 |
| CEFBS_NotInMips16Mode_HasDSP, // LWDSP = 1900 |
| CEFBS_InMicroMips_HasDSP, // LWDSP_MM = 1901 |
| CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // LWE = 1902 |
| CEFBS_InMicroMips_HasEVA, // LWE_MM = 1903 |
| CEFBS_InMicroMips, // LWGP_MM = 1904 |
| CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // LWL = 1905 |
| CEFBS_NotInMips16Mode_IsGP64bit, // LWL64 = 1906 |
| CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips, // LWLE = 1907 |
| CEFBS_InMicroMips_NotMips32r6_HasEVA, // LWLE_MM = 1908 |
| CEFBS_InMicroMips_NotMips32r6, // LWL_MM = 1909 |
| CEFBS_InMicroMips_NotMips32r6, // LWM16_MM = 1910 |
| CEFBS_InMicroMips_HasMips32r6, // LWM16_MMR6 = 1911 |
| CEFBS_InMicroMips, // LWM32_MM = 1912 |
| CEFBS_HasStdEnc_HasMips32r6, // LWPC = 1913 |
| CEFBS_InMicroMips_HasMips32r6, // LWPC_MMR6 = 1914 |
| CEFBS_InMicroMips, // LWP_MM = 1915 |
| CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // LWR = 1916 |
| CEFBS_NotInMips16Mode_IsGP64bit, // LWR64 = 1917 |
| CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips, // LWRE = 1918 |
| CEFBS_InMicroMips_NotMips32r6_HasEVA, // LWRE_MM = 1919 |
| CEFBS_InMicroMips_NotMips32r6, // LWR_MM = 1920 |
| CEFBS_InMicroMips, // LWSP_MM = 1921 |
| CEFBS_HasStdEnc_HasMips64r6, // LWUPC = 1922 |
| CEFBS_InMicroMips_NotMips32r6, // LWU_MM = 1923 |
| CEFBS_HasDSP, // LWX = 1924 |
| CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat, // LWXC1 = 1925 |
| CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // LWXC1_MM = 1926 |
| CEFBS_InMicroMips, // LWXS_MM = 1927 |
| CEFBS_InMicroMips_HasDSP, // LWX_MM = 1928 |
| CEFBS_InMicroMips, // LW_MM = 1929 |
| CEFBS_InMicroMips_HasMips32r6, // LW_MMR6 = 1930 |
| CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // LWu = 1931 |
| CEFBS_InMips16Mode, // LbRxRyOffMemX16 = 1932 |
| CEFBS_InMips16Mode, // LbuRxRyOffMemX16 = 1933 |
| CEFBS_InMips16Mode, // LhRxRyOffMemX16 = 1934 |
| CEFBS_InMips16Mode, // LhuRxRyOffMemX16 = 1935 |
| CEFBS_InMips16Mode, // LiRxImm16 = 1936 |
| CEFBS_InMips16Mode, // LiRxImmAlignX16 = 1937 |
| CEFBS_InMips16Mode, // LiRxImmX16 = 1938 |
| CEFBS_InMips16Mode, // LwRxPcTcp16 = 1939 |
| CEFBS_InMips16Mode, // LwRxPcTcpX16 = 1940 |
| CEFBS_InMips16Mode, // LwRxRyOffMemX16 = 1941 |
| CEFBS_InMips16Mode, // LwRxSpImmX16 = 1942 |
| CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // MADD = 1943 |
| CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MADDF_D = 1944 |
| CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MADDF_D_MMR6 = 1945 |
| CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MADDF_S = 1946 |
| CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MADDF_S_MMR6 = 1947 |
| CEFBS_HasStdEnc_HasMSA, // MADDR_Q_H = 1948 |
| CEFBS_HasStdEnc_HasMSA, // MADDR_Q_W = 1949 |
| CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // MADDU = 1950 |
| CEFBS_HasDSP, // MADDU_DSP = 1951 |
| CEFBS_InMicroMips_HasDSP, // MADDU_DSP_MM = 1952 |
| CEFBS_InMicroMips_NotMips32r6, // MADDU_MM = 1953 |
| CEFBS_HasStdEnc_HasMSA, // MADDV_B = 1954 |
| CEFBS_HasStdEnc_HasMSA, // MADDV_D = 1955 |
| CEFBS_HasStdEnc_HasMSA, // MADDV_H = 1956 |
| CEFBS_HasStdEnc_HasMSA, // MADDV_W = 1957 |
| CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, // MADD_D32 = 1958 |
| CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat_HasMadd4, // MADD_D32_MM = 1959 |
| CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, // MADD_D64 = 1960 |
| CEFBS_HasDSP, // MADD_DSP = 1961 |
| CEFBS_InMicroMips_HasDSP, // MADD_DSP_MM = 1962 |
| CEFBS_InMicroMips_NotMips32r6, // MADD_MM = 1963 |
| CEFBS_HasStdEnc_HasMSA, // MADD_Q_H = 1964 |
| CEFBS_HasStdEnc_HasMSA, // MADD_Q_W = 1965 |
| CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, // MADD_S = 1966 |
| CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4, // MADD_S_MM = 1967 |
| CEFBS_HasDSP, // MAQ_SA_W_PHL = 1968 |
| CEFBS_InMicroMips_HasDSP, // MAQ_SA_W_PHL_MM = 1969 |
| CEFBS_HasDSP, // MAQ_SA_W_PHR = 1970 |
| CEFBS_InMicroMips_HasDSP, // MAQ_SA_W_PHR_MM = 1971 |
| CEFBS_HasDSP, // MAQ_S_W_PHL = 1972 |
| CEFBS_InMicroMips_HasDSP, // MAQ_S_W_PHL_MM = 1973 |
| CEFBS_HasDSP, // MAQ_S_W_PHR = 1974 |
| CEFBS_InMicroMips_HasDSP, // MAQ_S_W_PHR_MM = 1975 |
| CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MAXA_D = 1976 |
| CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MAXA_D_MMR6 = 1977 |
| CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MAXA_S = 1978 |
| CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MAXA_S_MMR6 = 1979 |
| CEFBS_HasStdEnc_HasMSA, // MAXI_S_B = 1980 |
| CEFBS_HasStdEnc_HasMSA, // MAXI_S_D = 1981 |
| CEFBS_HasStdEnc_HasMSA, // MAXI_S_H = 1982 |
| CEFBS_HasStdEnc_HasMSA, // MAXI_S_W = 1983 |
| CEFBS_HasStdEnc_HasMSA, // MAXI_U_B = 1984 |
| CEFBS_HasStdEnc_HasMSA, // MAXI_U_D = 1985 |
| CEFBS_HasStdEnc_HasMSA, // MAXI_U_H = 1986 |
| CEFBS_HasStdEnc_HasMSA, // MAXI_U_W = 1987 |
| CEFBS_HasStdEnc_HasMSA, // MAX_A_B = 1988 |
| CEFBS_HasStdEnc_HasMSA, // MAX_A_D = 1989 |
| CEFBS_HasStdEnc_HasMSA, // MAX_A_H = 1990 |
| CEFBS_HasStdEnc_HasMSA, // MAX_A_W = 1991 |
| CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MAX_D = 1992 |
| CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MAX_D_MMR6 = 1993 |
| CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MAX_S = 1994 |
| CEFBS_HasStdEnc_HasMSA, // MAX_S_B = 1995 |
| CEFBS_HasStdEnc_HasMSA, // MAX_S_D = 1996 |
| CEFBS_HasStdEnc_HasMSA, // MAX_S_H = 1997 |
| CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MAX_S_MMR6 = 1998 |
| CEFBS_HasStdEnc_HasMSA, // MAX_S_W = 1999 |
| CEFBS_HasStdEnc_HasMSA, // MAX_U_B = 2000 |
| CEFBS_HasStdEnc_HasMSA, // MAX_U_D = 2001 |
| CEFBS_HasStdEnc_HasMSA, // MAX_U_H = 2002 |
| CEFBS_HasStdEnc_HasMSA, // MAX_U_W = 2003 |
| CEFBS_HasStdEnc_NotInMicroMips, // MFC0 = 2004 |
| CEFBS_InMicroMips_HasMips32r6, // MFC0_MMR6 = 2005 |
| CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // MFC1 = 2006 |
| CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // MFC1_D64 = 2007 |
| CEFBS_InMicroMips_IsNotSoftFloat, // MFC1_MM = 2008 |
| CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MFC1_MMR6 = 2009 |
| CEFBS_HasStdEnc_NotInMicroMips, // MFC2 = 2010 |
| CEFBS_InMicroMips_HasMips32r6, // MFC2_MMR6 = 2011 |
| CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // MFGC0 = 2012 |
| CEFBS_InMicroMips_HasMips32r5_HasVirt, // MFGC0_MM = 2013 |
| CEFBS_InMicroMips_HasMips32r6, // MFHC0_MMR6 = 2014 |
| CEFBS_HasStdEnc_NotFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips, // MFHC1_D32 = 2015 |
| CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // MFHC1_D32_MM = 2016 |
| CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips, // MFHC1_D64 = 2017 |
| CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // MFHC1_D64_MM = 2018 |
| CEFBS_InMicroMips_HasMips32r6, // MFHC2_MMR6 = 2019 |
| CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // MFHGC0 = 2020 |
| CEFBS_InMicroMips_HasMips32r5_HasVirt, // MFHGC0_MM = 2021 |
| CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // MFHI = 2022 |
| CEFBS_InMicroMips_NotMips32r6, // MFHI16_MM = 2023 |
| CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // MFHI64 = 2024 |
| CEFBS_HasDSP, // MFHI_DSP = 2025 |
| CEFBS_InMicroMips_HasDSP, // MFHI_DSP_MM = 2026 |
| CEFBS_InMicroMips_NotMips32r6, // MFHI_MM = 2027 |
| CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // MFLO = 2028 |
| CEFBS_InMicroMips_NotMips32r6, // MFLO16_MM = 2029 |
| CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // MFLO64 = 2030 |
| CEFBS_HasDSP, // MFLO_DSP = 2031 |
| CEFBS_InMicroMips_HasDSP, // MFLO_DSP_MM = 2032 |
| CEFBS_InMicroMips_NotMips32r6, // MFLO_MM = 2033 |
| CEFBS_HasStdEnc_HasMT_NotInMicroMips, // MFTR = 2034 |
| CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MINA_D = 2035 |
| CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MINA_D_MMR6 = 2036 |
| CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MINA_S = 2037 |
| CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MINA_S_MMR6 = 2038 |
| CEFBS_HasStdEnc_HasMSA, // MINI_S_B = 2039 |
| CEFBS_HasStdEnc_HasMSA, // MINI_S_D = 2040 |
| CEFBS_HasStdEnc_HasMSA, // MINI_S_H = 2041 |
| CEFBS_HasStdEnc_HasMSA, // MINI_S_W = 2042 |
| CEFBS_HasStdEnc_HasMSA, // MINI_U_B = 2043 |
| CEFBS_HasStdEnc_HasMSA, // MINI_U_D = 2044 |
| CEFBS_HasStdEnc_HasMSA, // MINI_U_H = 2045 |
| CEFBS_HasStdEnc_HasMSA, // MINI_U_W = 2046 |
| CEFBS_HasStdEnc_HasMSA, // MIN_A_B = 2047 |
| CEFBS_HasStdEnc_HasMSA, // MIN_A_D = 2048 |
| CEFBS_HasStdEnc_HasMSA, // MIN_A_H = 2049 |
| CEFBS_HasStdEnc_HasMSA, // MIN_A_W = 2050 |
| CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MIN_D = 2051 |
| CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MIN_D_MMR6 = 2052 |
| CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MIN_S = 2053 |
| CEFBS_HasStdEnc_HasMSA, // MIN_S_B = 2054 |
| CEFBS_HasStdEnc_HasMSA, // MIN_S_D = 2055 |
| CEFBS_HasStdEnc_HasMSA, // MIN_S_H = 2056 |
| CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MIN_S_MMR6 = 2057 |
| CEFBS_HasStdEnc_HasMSA, // MIN_S_W = 2058 |
| CEFBS_HasStdEnc_HasMSA, // MIN_U_B = 2059 |
| CEFBS_HasStdEnc_HasMSA, // MIN_U_D = 2060 |
| CEFBS_HasStdEnc_HasMSA, // MIN_U_H = 2061 |
| CEFBS_HasStdEnc_HasMSA, // MIN_U_W = 2062 |
| CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // MOD = 2063 |
| CEFBS_HasDSP, // MODSUB = 2064 |
| CEFBS_InMicroMips_HasDSP, // MODSUB_MM = 2065 |
| CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // MODU = 2066 |
| CEFBS_InMicroMips_HasMips32r6, // MODU_MMR6 = 2067 |
| CEFBS_InMicroMips_HasMips32r6, // MOD_MMR6 = 2068 |
| CEFBS_HasStdEnc_HasMSA, // MOD_S_B = 2069 |
| CEFBS_HasStdEnc_HasMSA, // MOD_S_D = 2070 |
| CEFBS_HasStdEnc_HasMSA, // MOD_S_H = 2071 |
| CEFBS_HasStdEnc_HasMSA, // MOD_S_W = 2072 |
| CEFBS_HasStdEnc_HasMSA, // MOD_U_B = 2073 |
| CEFBS_HasStdEnc_HasMSA, // MOD_U_D = 2074 |
| CEFBS_HasStdEnc_HasMSA, // MOD_U_H = 2075 |
| CEFBS_HasStdEnc_HasMSA, // MOD_U_W = 2076 |
| CEFBS_InMicroMips_NotMips32r6, // MOVE16_MM = 2077 |
| CEFBS_InMicroMips_HasMips32r6, // MOVE16_MMR6 = 2078 |
| CEFBS_InMicroMips_NotMips32r6, // MOVEP_MM = 2079 |
| CEFBS_InMicroMips_HasMips32r6, // MOVEP_MMR6 = 2080 |
| CEFBS_HasStdEnc_HasMSA, // MOVE_V = 2081 |
| CEFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVF_D32 = 2082 |
| CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // MOVF_D32_MM = 2083 |
| CEFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVF_D64 = 2084 |
| CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVF_I = 2085 |
| CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVF_I64 = 2086 |
| CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // MOVF_I_MM = 2087 |
| CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVF_S = 2088 |
| CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // MOVF_S_MM = 2089 |
| CEFBS_HasStdEnc_IsGP64bit_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVN_I64_D64 = 2090 |
| CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVN_I64_I = 2091 |
| CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVN_I64_I64 = 2092 |
| CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVN_I64_S = 2093 |
| CEFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVN_I_D32 = 2094 |
| CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // MOVN_I_D32_MM = 2095 |
| CEFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVN_I_D64 = 2096 |
| CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVN_I_I = 2097 |
| CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVN_I_I64 = 2098 |
| CEFBS_InMicroMips_NotMips32r6, // MOVN_I_MM = 2099 |
| CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVN_I_S = 2100 |
| CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // MOVN_I_S_MM = 2101 |
| CEFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVT_D32 = 2102 |
| CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // MOVT_D32_MM = 2103 |
| CEFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVT_D64 = 2104 |
| CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVT_I = 2105 |
| CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVT_I64 = 2106 |
| CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // MOVT_I_MM = 2107 |
| CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVT_S = 2108 |
| CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // MOVT_S_MM = 2109 |
| CEFBS_HasStdEnc_IsGP64bit_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVZ_I64_D64 = 2110 |
| CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVZ_I64_I = 2111 |
| CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVZ_I64_I64 = 2112 |
| CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVZ_I64_S = 2113 |
| CEFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVZ_I_D32 = 2114 |
| CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // MOVZ_I_D32_MM = 2115 |
| CEFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVZ_I_D64 = 2116 |
| CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVZ_I_I = 2117 |
| CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVZ_I_I64 = 2118 |
| CEFBS_InMicroMips_NotMips32r6, // MOVZ_I_MM = 2119 |
| CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVZ_I_S = 2120 |
| CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // MOVZ_I_S_MM = 2121 |
| CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // MSUB = 2122 |
| CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MSUBF_D = 2123 |
| CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MSUBF_D_MMR6 = 2124 |
| CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MSUBF_S = 2125 |
| CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MSUBF_S_MMR6 = 2126 |
| CEFBS_HasStdEnc_HasMSA, // MSUBR_Q_H = 2127 |
| CEFBS_HasStdEnc_HasMSA, // MSUBR_Q_W = 2128 |
| CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // MSUBU = 2129 |
| CEFBS_HasDSP, // MSUBU_DSP = 2130 |
| CEFBS_InMicroMips_HasDSP, // MSUBU_DSP_MM = 2131 |
| CEFBS_InMicroMips_NotMips32r6, // MSUBU_MM = 2132 |
| CEFBS_HasStdEnc_HasMSA, // MSUBV_B = 2133 |
| CEFBS_HasStdEnc_HasMSA, // MSUBV_D = 2134 |
| CEFBS_HasStdEnc_HasMSA, // MSUBV_H = 2135 |
| CEFBS_HasStdEnc_HasMSA, // MSUBV_W = 2136 |
| CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, // MSUB_D32 = 2137 |
| CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat_HasMadd4, // MSUB_D32_MM = 2138 |
| CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, // MSUB_D64 = 2139 |
| CEFBS_HasDSP, // MSUB_DSP = 2140 |
| CEFBS_InMicroMips_HasDSP, // MSUB_DSP_MM = 2141 |
| CEFBS_InMicroMips_NotMips32r6, // MSUB_MM = 2142 |
| CEFBS_HasStdEnc_HasMSA, // MSUB_Q_H = 2143 |
| CEFBS_HasStdEnc_HasMSA, // MSUB_Q_W = 2144 |
| CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, // MSUB_S = 2145 |
| CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4, // MSUB_S_MM = 2146 |
| CEFBS_HasStdEnc_NotInMicroMips, // MTC0 = 2147 |
| CEFBS_InMicroMips_HasMips32r6, // MTC0_MMR6 = 2148 |
| CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // MTC1 = 2149 |
| CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // MTC1_D64 = 2150 |
| CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // MTC1_D64_MM = 2151 |
| CEFBS_InMicroMips_IsNotSoftFloat, // MTC1_MM = 2152 |
| CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MTC1_MMR6 = 2153 |
| CEFBS_HasStdEnc_NotInMicroMips, // MTC2 = 2154 |
| CEFBS_InMicroMips_HasMips32r6, // MTC2_MMR6 = 2155 |
| CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // MTGC0 = 2156 |
| CEFBS_InMicroMips_HasMips32r5_HasVirt, // MTGC0_MM = 2157 |
| CEFBS_InMicroMips_HasMips32r6, // MTHC0_MMR6 = 2158 |
| CEFBS_HasStdEnc_NotFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips, // MTHC1_D32 = 2159 |
| CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // MTHC1_D32_MM = 2160 |
| CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips, // MTHC1_D64 = 2161 |
| CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // MTHC1_D64_MM = 2162 |
| CEFBS_InMicroMips_HasMips32r6, // MTHC2_MMR6 = 2163 |
| CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // MTHGC0 = 2164 |
| CEFBS_InMicroMips_HasMips32r5_HasVirt, // MTHGC0_MM = 2165 |
| CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // MTHI = 2166 |
| CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // MTHI64 = 2167 |
| CEFBS_HasDSP, // MTHI_DSP = 2168 |
| CEFBS_InMicroMips_HasDSP, // MTHI_DSP_MM = 2169 |
| CEFBS_InMicroMips_NotMips32r6, // MTHI_MM = 2170 |
| CEFBS_HasDSP, // MTHLIP = 2171 |
| CEFBS_InMicroMips_HasDSP, // MTHLIP_MM = 2172 |
| CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // MTLO = 2173 |
| CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // MTLO64 = 2174 |
| CEFBS_HasDSP, // MTLO_DSP = 2175 |
| CEFBS_InMicroMips_HasDSP, // MTLO_DSP_MM = 2176 |
| CEFBS_InMicroMips_NotMips32r6, // MTLO_MM = 2177 |
| CEFBS_HasCnMips, // MTM0 = 2178 |
| CEFBS_HasCnMips, // MTM1 = 2179 |
| CEFBS_HasCnMips, // MTM2 = 2180 |
| CEFBS_HasCnMips, // MTP0 = 2181 |
| CEFBS_HasCnMips, // MTP1 = 2182 |
| CEFBS_HasCnMips, // MTP2 = 2183 |
| CEFBS_HasStdEnc_HasMT_NotInMicroMips, // MTTR = 2184 |
| CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // MUH = 2185 |
| CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // MUHU = 2186 |
| CEFBS_InMicroMips_HasMips32r6, // MUHU_MMR6 = 2187 |
| CEFBS_InMicroMips_HasMips32r6, // MUH_MMR6 = 2188 |
| CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // MUL = 2189 |
| CEFBS_HasDSP, // MULEQ_S_W_PHL = 2190 |
| CEFBS_InMicroMips_HasDSP, // MULEQ_S_W_PHL_MM = 2191 |
| CEFBS_HasDSP, // MULEQ_S_W_PHR = 2192 |
| CEFBS_InMicroMips_HasDSP, // MULEQ_S_W_PHR_MM = 2193 |
| CEFBS_HasDSP, // MULEU_S_PH_QBL = 2194 |
| CEFBS_InMicroMips_HasDSP, // MULEU_S_PH_QBL_MM = 2195 |
| CEFBS_HasDSP, // MULEU_S_PH_QBR = 2196 |
| CEFBS_InMicroMips_HasDSP, // MULEU_S_PH_QBR_MM = 2197 |
| CEFBS_HasDSP, // MULQ_RS_PH = 2198 |
| CEFBS_InMicroMips_HasDSP, // MULQ_RS_PH_MM = 2199 |
| CEFBS_HasDSPR2, // MULQ_RS_W = 2200 |
| CEFBS_InMicroMips_HasDSPR2, // MULQ_RS_W_MMR2 = 2201 |
| CEFBS_HasDSPR2, // MULQ_S_PH = 2202 |
| CEFBS_InMicroMips_HasDSPR2, // MULQ_S_PH_MMR2 = 2203 |
| CEFBS_HasDSPR2, // MULQ_S_W = 2204 |
| CEFBS_InMicroMips_HasDSPR2, // MULQ_S_W_MMR2 = 2205 |
| CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D, // MULR_PS64 = 2206 |
| CEFBS_HasStdEnc_HasMSA, // MULR_Q_H = 2207 |
| CEFBS_HasStdEnc_HasMSA, // MULR_Q_W = 2208 |
| CEFBS_HasDSP, // MULSAQ_S_W_PH = 2209 |
| CEFBS_InMicroMips_HasDSP, // MULSAQ_S_W_PH_MM = 2210 |
| CEFBS_HasDSPR2, // MULSA_W_PH = 2211 |
| CEFBS_InMicroMips_HasDSPR2, // MULSA_W_PH_MMR2 = 2212 |
| CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // MULT = 2213 |
| CEFBS_HasDSP, // MULTU_DSP = 2214 |
| CEFBS_InMicroMips_HasDSP, // MULTU_DSP_MM = 2215 |
| CEFBS_HasDSP, // MULT_DSP = 2216 |
| CEFBS_InMicroMips_HasDSP, // MULT_DSP_MM = 2217 |
| CEFBS_InMicroMips_NotMips32r6, // MULT_MM = 2218 |
| CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // MULTu = 2219 |
| CEFBS_InMicroMips_NotMips32r6, // MULTu_MM = 2220 |
| CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // MULU = 2221 |
| CEFBS_InMicroMips_HasMips32r6, // MULU_MMR6 = 2222 |
| CEFBS_HasStdEnc_HasMSA, // MULV_B = 2223 |
| CEFBS_HasStdEnc_HasMSA, // MULV_D = 2224 |
| CEFBS_HasStdEnc_HasMSA, // MULV_H = 2225 |
| CEFBS_HasStdEnc_HasMSA, // MULV_W = 2226 |
| CEFBS_InMicroMips_NotMips32r6, // MUL_MM = 2227 |
| CEFBS_InMicroMips_HasMips32r6, // MUL_MMR6 = 2228 |
| CEFBS_HasDSPR2, // MUL_PH = 2229 |
| CEFBS_InMicroMips_HasDSPR2, // MUL_PH_MMR2 = 2230 |
| CEFBS_HasStdEnc_HasMSA, // MUL_Q_H = 2231 |
| CEFBS_HasStdEnc_HasMSA, // MUL_Q_W = 2232 |
| CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // MUL_R6 = 2233 |
| CEFBS_HasDSPR2, // MUL_S_PH = 2234 |
| CEFBS_InMicroMips_HasDSPR2, // MUL_S_PH_MMR2 = 2235 |
| CEFBS_InMips16Mode, // Mfhi16 = 2236 |
| CEFBS_InMips16Mode, // Mflo16 = 2237 |
| CEFBS_InMips16Mode, // Move32R16 = 2238 |
| CEFBS_InMips16Mode, // MoveR3216 = 2239 |
| CEFBS_HasStdEnc_HasMSA, // NLOC_B = 2240 |
| CEFBS_HasStdEnc_HasMSA, // NLOC_D = 2241 |
| CEFBS_HasStdEnc_HasMSA, // NLOC_H = 2242 |
| CEFBS_HasStdEnc_HasMSA, // NLOC_W = 2243 |
| CEFBS_HasStdEnc_HasMSA, // NLZC_B = 2244 |
| CEFBS_HasStdEnc_HasMSA, // NLZC_D = 2245 |
| CEFBS_HasStdEnc_HasMSA, // NLZC_H = 2246 |
| CEFBS_HasStdEnc_HasMSA, // NLZC_W = 2247 |
| CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, // NMADD_D32 = 2248 |
| CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat_HasMadd4, // NMADD_D32_MM = 2249 |
| CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, // NMADD_D64 = 2250 |
| CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, // NMADD_S = 2251 |
| CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4, // NMADD_S_MM = 2252 |
| CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, // NMSUB_D32 = 2253 |
| CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat_HasMadd4, // NMSUB_D32_MM = 2254 |
| CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, // NMSUB_D64 = 2255 |
| CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, // NMSUB_S = 2256 |
| CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4, // NMSUB_S_MM = 2257 |
| CEFBS_HasStdEnc_NotInMicroMips, // NOR = 2258 |
| CEFBS_NotInMips16Mode_IsGP64bit, // NOR64 = 2259 |
| CEFBS_HasStdEnc_HasMSA, // NORI_B = 2260 |
| CEFBS_InMicroMips_NotMips32r6, // NOR_MM = 2261 |
| CEFBS_InMicroMips_HasMips32r6, // NOR_MMR6 = 2262 |
| CEFBS_HasStdEnc_HasMSA, // NOR_V = 2263 |
| CEFBS_InMicroMips_NotMips32r6, // NOT16_MM = 2264 |
| CEFBS_InMicroMips_HasMips32r6, // NOT16_MMR6 = 2265 |
| CEFBS_InMips16Mode, // NegRxRy16 = 2266 |
| CEFBS_InMips16Mode, // NotRxRy16 = 2267 |
| CEFBS_HasStdEnc_NotInMicroMips, // OR = 2268 |
| CEFBS_InMicroMips_NotMips32r6, // OR16_MM = 2269 |
| CEFBS_InMicroMips_HasMips32r6, // OR16_MMR6 = 2270 |
| CEFBS_NotInMips16Mode_IsGP64bit, // OR64 = 2271 |
| CEFBS_HasStdEnc_HasMSA, // ORI_B = 2272 |
| CEFBS_InMicroMips_HasMips32r6, // ORI_MMR6 = 2273 |
| CEFBS_InMicroMips_NotMips32r6, // OR_MM = 2274 |
| CEFBS_InMicroMips_HasMips32r6, // OR_MMR6 = 2275 |
| CEFBS_HasStdEnc_HasMSA, // OR_V = 2276 |
| CEFBS_HasStdEnc_NotInMicroMips, // ORi = 2277 |
| CEFBS_NotInMips16Mode_IsGP64bit, // ORi64 = 2278 |
| CEFBS_InMicroMips_NotMips32r6, // ORi_MM = 2279 |
| CEFBS_InMips16Mode, // OrRxRxRy16 = 2280 |
| CEFBS_HasDSP, // PACKRL_PH = 2281 |
| CEFBS_InMicroMips_HasDSP, // PACKRL_PH_MM = 2282 |
| CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // PAUSE = 2283 |
| CEFBS_InMicroMips, // PAUSE_MM = 2284 |
| CEFBS_InMicroMips_HasMips32r6, // PAUSE_MMR6 = 2285 |
| CEFBS_HasStdEnc_HasMSA, // PCKEV_B = 2286 |
| CEFBS_HasStdEnc_HasMSA, // PCKEV_D = 2287 |
| CEFBS_HasStdEnc_HasMSA, // PCKEV_H = 2288 |
| CEFBS_HasStdEnc_HasMSA, // PCKEV_W = 2289 |
| CEFBS_HasStdEnc_HasMSA, // PCKOD_B = 2290 |
| CEFBS_HasStdEnc_HasMSA, // PCKOD_D = 2291 |
| CEFBS_HasStdEnc_HasMSA, // PCKOD_H = 2292 |
| CEFBS_HasStdEnc_HasMSA, // PCKOD_W = 2293 |
| CEFBS_HasStdEnc_HasMSA, // PCNT_B = 2294 |
| CEFBS_HasStdEnc_HasMSA, // PCNT_D = 2295 |
| CEFBS_HasStdEnc_HasMSA, // PCNT_H = 2296 |
| CEFBS_HasStdEnc_HasMSA, // PCNT_W = 2297 |
| CEFBS_HasDSP, // PICK_PH = 2298 |
| CEFBS_InMicroMips_HasDSP, // PICK_PH_MM = 2299 |
| CEFBS_HasDSP, // PICK_QB = 2300 |
| CEFBS_InMicroMips_HasDSP, // PICK_QB_MM = 2301 |
| CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // PLL_PS64 = 2302 |
| CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // PLU_PS64 = 2303 |
| CEFBS_HasCnMips, // POP = 2304 |
| CEFBS_HasDSP, // PRECEQU_PH_QBL = 2305 |
| CEFBS_HasDSP, // PRECEQU_PH_QBLA = 2306 |
| CEFBS_InMicroMips_HasDSP, // PRECEQU_PH_QBLA_MM = 2307 |
| CEFBS_InMicroMips_HasDSP, // PRECEQU_PH_QBL_MM = 2308 |
| CEFBS_HasDSP, // PRECEQU_PH_QBR = 2309 |
| CEFBS_HasDSP, // PRECEQU_PH_QBRA = 2310 |
| CEFBS_InMicroMips_HasDSP, // PRECEQU_PH_QBRA_MM = 2311 |
| CEFBS_InMicroMips_HasDSP, // PRECEQU_PH_QBR_MM = 2312 |
| CEFBS_HasDSP, // PRECEQ_W_PHL = 2313 |
| CEFBS_InMicroMips_HasDSP, // PRECEQ_W_PHL_MM = 2314 |
| CEFBS_HasDSP, // PRECEQ_W_PHR = 2315 |
| CEFBS_InMicroMips_HasDSP, // PRECEQ_W_PHR_MM = 2316 |
| CEFBS_HasDSP, // PRECEU_PH_QBL = 2317 |
| CEFBS_HasDSP, // PRECEU_PH_QBLA = 2318 |
| CEFBS_InMicroMips_HasDSP, // PRECEU_PH_QBLA_MM = 2319 |
| CEFBS_InMicroMips_HasDSP, // PRECEU_PH_QBL_MM = 2320 |
| CEFBS_HasDSP, // PRECEU_PH_QBR = 2321 |
| CEFBS_HasDSP, // PRECEU_PH_QBRA = 2322 |
| CEFBS_InMicroMips_HasDSP, // PRECEU_PH_QBRA_MM = 2323 |
| CEFBS_InMicroMips_HasDSP, // PRECEU_PH_QBR_MM = 2324 |
| CEFBS_HasDSP, // PRECRQU_S_QB_PH = 2325 |
| CEFBS_InMicroMips_HasDSP, // PRECRQU_S_QB_PH_MM = 2326 |
| CEFBS_HasDSP, // PRECRQ_PH_W = 2327 |
| CEFBS_InMicroMips_HasDSP, // PRECRQ_PH_W_MM = 2328 |
| CEFBS_HasDSP, // PRECRQ_QB_PH = 2329 |
| CEFBS_InMicroMips_HasDSP, // PRECRQ_QB_PH_MM = 2330 |
| CEFBS_HasDSP, // PRECRQ_RS_PH_W = 2331 |
| CEFBS_InMicroMips_HasDSP, // PRECRQ_RS_PH_W_MM = 2332 |
| CEFBS_HasDSPR2, // PRECR_QB_PH = 2333 |
| CEFBS_InMicroMips_HasDSPR2, // PRECR_QB_PH_MMR2 = 2334 |
| CEFBS_HasDSPR2, // PRECR_SRA_PH_W = 2335 |
| CEFBS_InMicroMips_HasDSPR2, // PRECR_SRA_PH_W_MMR2 = 2336 |
| CEFBS_HasDSPR2, // PRECR_SRA_R_PH_W = 2337 |
| CEFBS_InMicroMips_HasDSPR2, // PRECR_SRA_R_PH_W_MMR2 = 2338 |
| CEFBS_HasStdEnc_HasMips3_32_NotMips32r6_NotMips64r6_NotInMicroMips, // PREF = 2339 |
| CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // PREFE = 2340 |
| CEFBS_InMicroMips_HasEVA, // PREFE_MM = 2341 |
| CEFBS_InMicroMips_NotMips32r6, // PREFX_MM = 2342 |
| CEFBS_InMicroMips_NotMips32r6, // PREF_MM = 2343 |
| CEFBS_InMicroMips_HasMips32r6, // PREF_MMR6 = 2344 |
| CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // PREF_R6 = 2345 |
| CEFBS_HasDSPR2, // PREPEND = 2346 |
| CEFBS_InMicroMips_HasDSPR2, // PREPEND_MMR2 = 2347 |
| CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // PUL_PS64 = 2348 |
| CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // PUU_PS64 = 2349 |
| CEFBS_HasDSP, // RADDU_W_QB = 2350 |
| CEFBS_InMicroMips_HasDSP, // RADDU_W_QB_MM = 2351 |
| CEFBS_HasDSP, // RDDSP = 2352 |
| CEFBS_InMicroMips_HasDSP, // RDDSP_MM = 2353 |
| CEFBS_HasStdEnc_NotInMicroMips, // RDHWR = 2354 |
| CEFBS_NotInMips16Mode_IsGP64bit, // RDHWR64 = 2355 |
| CEFBS_InMicroMips_NotMips32r6, // RDHWR_MM = 2356 |
| CEFBS_InMicroMips_HasMips32r6, // RDHWR_MMR6 = 2357 |
| CEFBS_InMicroMips_HasMips32r6, // RDPGPR_MMR6 = 2358 |
| CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, // RECIP_D32 = 2359 |
| CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // RECIP_D32_MM = 2360 |
| CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, // RECIP_D64 = 2361 |
| CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // RECIP_D64_MM = 2362 |
| CEFBS_HasStdEnc_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, // RECIP_S = 2363 |
| CEFBS_InMicroMips_IsNotSoftFloat, // RECIP_S_MM = 2364 |
| CEFBS_HasDSP, // REPLV_PH = 2365 |
| CEFBS_InMicroMips_HasDSP, // REPLV_PH_MM = 2366 |
| CEFBS_HasDSP, // REPLV_QB = 2367 |
| CEFBS_InMicroMips_HasDSP, // REPLV_QB_MM = 2368 |
| CEFBS_HasDSP, // REPL_PH = 2369 |
| CEFBS_InMicroMips_HasDSP, // REPL_PH_MM = 2370 |
| CEFBS_HasDSP, // REPL_QB = 2371 |
| CEFBS_InMicroMips_HasDSP, // REPL_QB_MM = 2372 |
| CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // RINT_D = 2373 |
| CEFBS_InMicroMips_HasMips32r6, // RINT_D_MMR6 = 2374 |
| CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // RINT_S = 2375 |
| CEFBS_InMicroMips_HasMips32r6, // RINT_S_MMR6 = 2376 |
| CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // ROTR = 2377 |
| CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // ROTRV = 2378 |
| CEFBS_InMicroMips, // ROTRV_MM = 2379 |
| CEFBS_InMicroMips, // ROTR_MM = 2380 |
| CEFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips, // ROUND_L_D64 = 2381 |
| CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // ROUND_L_D_MMR6 = 2382 |
| CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // ROUND_L_S = 2383 |
| CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // ROUND_L_S_MMR6 = 2384 |
| CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // ROUND_W_D32 = 2385 |
| CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // ROUND_W_D64 = 2386 |
| CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // ROUND_W_D_MMR6 = 2387 |
| CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // ROUND_W_MM = 2388 |
| CEFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips, // ROUND_W_S = 2389 |
| CEFBS_InMicroMips_IsNotSoftFloat, // ROUND_W_S_MM = 2390 |
| CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // ROUND_W_S_MMR6 = 2391 |
| CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, // RSQRT_D32 = 2392 |
| CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // RSQRT_D32_MM = 2393 |
| CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, // RSQRT_D64 = 2394 |
| CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // RSQRT_D64_MM = 2395 |
| CEFBS_HasStdEnc_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, // RSQRT_S = 2396 |
| CEFBS_InMicroMips_IsNotSoftFloat, // RSQRT_S_MM = 2397 |
| CEFBS_InMips16Mode, // Restore16 = 2398 |
| CEFBS_InMips16Mode, // RestoreX16 = 2399 |
| CEFBS_HasCnMipsP, // SAA = 2400 |
| CEFBS_HasCnMipsP, // SAAD = 2401 |
| CEFBS_HasStdEnc_HasMSA, // SAT_S_B = 2402 |
| CEFBS_HasStdEnc_HasMSA, // SAT_S_D = 2403 |
| CEFBS_HasStdEnc_HasMSA, // SAT_S_H = 2404 |
| CEFBS_HasStdEnc_HasMSA, // SAT_S_W = 2405 |
| CEFBS_HasStdEnc_HasMSA, // SAT_U_B = 2406 |
| CEFBS_HasStdEnc_HasMSA, // SAT_U_D = 2407 |
| CEFBS_HasStdEnc_HasMSA, // SAT_U_H = 2408 |
| CEFBS_HasStdEnc_HasMSA, // SAT_U_W = 2409 |
| CEFBS_HasStdEnc_NotInMicroMips, // SB = 2410 |
| CEFBS_InMicroMips_NotMips32r6, // SB16_MM = 2411 |
| CEFBS_InMicroMips_HasMips32r6, // SB16_MMR6 = 2412 |
| CEFBS_NotInMips16Mode_IsGP64bit, // SB64 = 2413 |
| CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // SBE = 2414 |
| CEFBS_InMicroMips_HasEVA, // SBE_MM = 2415 |
| CEFBS_InMicroMips, // SB_MM = 2416 |
| CEFBS_InMicroMips_HasMips32r6, // SB_MMR6 = 2417 |
| CEFBS_HasStdEnc_IsPTR32bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // SC = 2418 |
| CEFBS_HasStdEnc_IsPTR64bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // SC64 = 2419 |
| CEFBS_HasStdEnc_IsPTR64bit_HasMips64r6_NotInMicroMips, // SC64_R6 = 2420 |
| CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // SCD = 2421 |
| CEFBS_HasStdEnc_HasMips32r6, // SCD_R6 = 2422 |
| CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // SCE = 2423 |
| CEFBS_InMicroMips_HasEVA, // SCE_MM = 2424 |
| CEFBS_InMicroMips_NotMips32r6, // SC_MM = 2425 |
| CEFBS_InMicroMips_HasMips32r6, // SC_MMR6 = 2426 |
| CEFBS_HasStdEnc_IsPTR32bit_HasMips32r6_NotInMicroMips, // SC_R6 = 2427 |
| CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // SD = 2428 |
| CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // SDBBP = 2429 |
| CEFBS_InMicroMips_NotMips32r6, // SDBBP16_MM = 2430 |
| CEFBS_InMicroMips_HasMips32r6, // SDBBP16_MMR6 = 2431 |
| CEFBS_InMicroMips, // SDBBP_MM = 2432 |
| CEFBS_InMicroMips_HasMips32r6, // SDBBP_MMR6 = 2433 |
| CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // SDBBP_R6 = 2434 |
| CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // SDC1 = 2435 |
| CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // SDC164 = 2436 |
| CEFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat, // SDC1_D64_MMR6 = 2437 |
| CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // SDC1_MM_D32 = 2438 |
| CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // SDC1_MM_D64 = 2439 |
| CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // SDC2 = 2440 |
| CEFBS_InMicroMips_HasMips32r6, // SDC2_MMR6 = 2441 |
| CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // SDC2_R6 = 2442 |
| CEFBS_HasStdEnc_HasMips2_NotCnMips_NotInMicroMips, // SDC3 = 2443 |
| CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // SDIV = 2444 |
| CEFBS_InMicroMips_NotMips32r6, // SDIV_MM = 2445 |
| CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // SDL = 2446 |
| CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // SDR = 2447 |
| CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // SDXC1 = 2448 |
| CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat, // SDXC164 = 2449 |
| CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // SEB = 2450 |
| CEFBS_HasStdEnc_IsGP64bit_HasMips32r2, // SEB64 = 2451 |
| CEFBS_InMicroMips, // SEB_MM = 2452 |
| CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // SEH = 2453 |
| CEFBS_HasStdEnc_IsGP64bit_HasMips32r2, // SEH64 = 2454 |
| CEFBS_InMicroMips, // SEH_MM = 2455 |
| CEFBS_HasStdEnc_IsGP32bit_HasMips32r6_NotInMicroMips, // SELEQZ = 2456 |
| CEFBS_HasStdEnc_IsGP64bit_HasMips32r6, // SELEQZ64 = 2457 |
| CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // SELEQZ_D = 2458 |
| CEFBS_InMicroMips_HasMips32r6, // SELEQZ_D_MMR6 = 2459 |
| CEFBS_InMicroMips_HasMips32r6, // SELEQZ_MMR6 = 2460 |
| CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // SELEQZ_S = 2461 |
| CEFBS_InMicroMips_HasMips32r6, // SELEQZ_S_MMR6 = 2462 |
| CEFBS_HasStdEnc_IsGP32bit_HasMips32r6_NotInMicroMips, // SELNEZ = 2463 |
| CEFBS_HasStdEnc_IsGP64bit_HasMips32r6, // SELNEZ64 = 2464 |
| CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // SELNEZ_D = 2465 |
| CEFBS_InMicroMips_HasMips32r6, // SELNEZ_D_MMR6 = 2466 |
| CEFBS_InMicroMips_HasMips32r6, // SELNEZ_MMR6 = 2467 |
| CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // SELNEZ_S = 2468 |
| CEFBS_InMicroMips_HasMips32r6, // SELNEZ_S_MMR6 = 2469 |
| CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // SEL_D = 2470 |
| CEFBS_InMicroMips_HasMips32r6, // SEL_D_MMR6 = 2471 |
| CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // SEL_S = 2472 |
| CEFBS_InMicroMips_HasMips32r6, // SEL_S_MMR6 = 2473 |
| CEFBS_HasCnMips, // SEQ = 2474 |
| CEFBS_HasCnMips, // SEQi = 2475 |
| CEFBS_HasStdEnc_NotInMicroMips, // SH = 2476 |
| CEFBS_InMicroMips_NotMips32r6, // SH16_MM = 2477 |
| CEFBS_InMicroMips_HasMips32r6, // SH16_MMR6 = 2478 |
| CEFBS_NotInMips16Mode_IsGP64bit, // SH64 = 2479 |
| CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // SHE = 2480 |
| CEFBS_InMicroMips_HasEVA, // SHE_MM = 2481 |
| CEFBS_HasStdEnc_HasMSA, // SHF_B = 2482 |
| CEFBS_HasStdEnc_HasMSA, // SHF_H = 2483 |
| CEFBS_HasStdEnc_HasMSA, // SHF_W = 2484 |
| CEFBS_HasDSP, // SHILO = 2485 |
| CEFBS_HasDSP, // SHILOV = 2486 |
| CEFBS_InMicroMips_HasDSP, // SHILOV_MM = 2487 |
| CEFBS_InMicroMips_HasDSP, // SHILO_MM = 2488 |
| CEFBS_HasDSP, // SHLLV_PH = 2489 |
| CEFBS_InMicroMips_HasDSP, // SHLLV_PH_MM = 2490 |
| CEFBS_HasDSP, // SHLLV_QB = 2491 |
| CEFBS_InMicroMips_HasDSP, // SHLLV_QB_MM = 2492 |
| CEFBS_HasDSP, // SHLLV_S_PH = 2493 |
| CEFBS_InMicroMips_HasDSP, // SHLLV_S_PH_MM = 2494 |
| CEFBS_HasDSP, // SHLLV_S_W = 2495 |
| CEFBS_InMicroMips_HasDSP, // SHLLV_S_W_MM = 2496 |
| CEFBS_HasDSP, // SHLL_PH = 2497 |
| CEFBS_InMicroMips_HasDSP, // SHLL_PH_MM = 2498 |
| CEFBS_HasDSP, // SHLL_QB = 2499 |
| CEFBS_InMicroMips_HasDSP, // SHLL_QB_MM = 2500 |
| CEFBS_HasDSP, // SHLL_S_PH = 2501 |
| CEFBS_InMicroMips_HasDSP, // SHLL_S_PH_MM = 2502 |
| CEFBS_HasDSP, // SHLL_S_W = 2503 |
| CEFBS_InMicroMips_HasDSP, // SHLL_S_W_MM = 2504 |
| CEFBS_HasDSP, // SHRAV_PH = 2505 |
| CEFBS_InMicroMips_HasDSP, // SHRAV_PH_MM = 2506 |
| CEFBS_HasDSPR2, // SHRAV_QB = 2507 |
| CEFBS_InMicroMips_HasDSPR2, // SHRAV_QB_MMR2 = 2508 |
| CEFBS_HasDSP, // SHRAV_R_PH = 2509 |
| CEFBS_InMicroMips_HasDSP, // SHRAV_R_PH_MM = 2510 |
| CEFBS_HasDSPR2, // SHRAV_R_QB = 2511 |
| CEFBS_InMicroMips_HasDSPR2, // SHRAV_R_QB_MMR2 = 2512 |
| CEFBS_HasDSP, // SHRAV_R_W = 2513 |
| CEFBS_InMicroMips_HasDSP, // SHRAV_R_W_MM = 2514 |
| CEFBS_HasDSP, // SHRA_PH = 2515 |
| CEFBS_InMicroMips_HasDSP, // SHRA_PH_MM = 2516 |
| CEFBS_HasDSPR2, // SHRA_QB = 2517 |
| CEFBS_InMicroMips_HasDSPR2, // SHRA_QB_MMR2 = 2518 |
| CEFBS_HasDSP, // SHRA_R_PH = 2519 |
| CEFBS_InMicroMips_HasDSP, // SHRA_R_PH_MM = 2520 |
| CEFBS_HasDSPR2, // SHRA_R_QB = 2521 |
| CEFBS_InMicroMips_HasDSPR2, // SHRA_R_QB_MMR2 = 2522 |
| CEFBS_HasDSP, // SHRA_R_W = 2523 |
| CEFBS_InMicroMips_HasDSP, // SHRA_R_W_MM = 2524 |
| CEFBS_HasDSPR2, // SHRLV_PH = 2525 |
| CEFBS_InMicroMips_HasDSPR2, // SHRLV_PH_MMR2 = 2526 |
| CEFBS_HasDSP, // SHRLV_QB = 2527 |
| CEFBS_InMicroMips_HasDSP, // SHRLV_QB_MM = 2528 |
| CEFBS_HasDSPR2, // SHRL_PH = 2529 |
| CEFBS_InMicroMips_HasDSPR2, // SHRL_PH_MMR2 = 2530 |
| CEFBS_HasDSP, // SHRL_QB = 2531 |
| CEFBS_InMicroMips_HasDSP, // SHRL_QB_MM = 2532 |
| CEFBS_InMicroMips, // SH_MM = 2533 |
| CEFBS_InMicroMips_HasMips32r6, // SH_MMR6 = 2534 |
| CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // SIGRIE = 2535 |
| CEFBS_InMicroMips_HasMips32r6, // SIGRIE_MMR6 = 2536 |
| CEFBS_HasStdEnc_HasMSA, // SLDI_B = 2537 |
| CEFBS_HasStdEnc_HasMSA, // SLDI_D = 2538 |
| CEFBS_HasStdEnc_HasMSA, // SLDI_H = 2539 |
| CEFBS_HasStdEnc_HasMSA, // SLDI_W = 2540 |
| CEFBS_HasStdEnc_HasMSA, // SLD_B = 2541 |
| CEFBS_HasStdEnc_HasMSA, // SLD_D = 2542 |
| CEFBS_HasStdEnc_HasMSA, // SLD_H = 2543 |
| CEFBS_HasStdEnc_HasMSA, // SLD_W = 2544 |
| CEFBS_HasStdEnc_NotInMicroMips, // SLL = 2545 |
| CEFBS_InMicroMips_NotMips32r6, // SLL16_MM = 2546 |
| CEFBS_InMicroMips_HasMips32r6, // SLL16_MMR6 = 2547 |
| CEFBS_NotInMips16Mode_IsGP64bit, // SLL64_32 = 2548 |
| CEFBS_NotInMips16Mode_IsGP64bit, // SLL64_64 = 2549 |
| CEFBS_HasStdEnc_HasMSA, // SLLI_B = 2550 |
| CEFBS_HasStdEnc_HasMSA, // SLLI_D = 2551 |
| CEFBS_HasStdEnc_HasMSA, // SLLI_H = 2552 |
| CEFBS_HasStdEnc_HasMSA, // SLLI_W = 2553 |
| CEFBS_HasStdEnc_NotInMicroMips, // SLLV = 2554 |
| CEFBS_InMicroMips, // SLLV_MM = 2555 |
| CEFBS_HasStdEnc_HasMSA, // SLL_B = 2556 |
| CEFBS_HasStdEnc_HasMSA, // SLL_D = 2557 |
| CEFBS_HasStdEnc_HasMSA, // SLL_H = 2558 |
| CEFBS_InMicroMips, // SLL_MM = 2559 |
| CEFBS_InMicroMips_HasMips32r6, // SLL_MMR6 = 2560 |
| CEFBS_HasStdEnc_HasMSA, // SLL_W = 2561 |
| CEFBS_HasStdEnc_NotInMicroMips, // SLT = 2562 |
| CEFBS_NotInMips16Mode_IsGP64bit, // SLT64 = 2563 |
| CEFBS_InMicroMips, // SLT_MM = 2564 |
| CEFBS_HasStdEnc_NotInMicroMips, // SLTi = 2565 |
| CEFBS_NotInMips16Mode_IsGP64bit, // SLTi64 = 2566 |
| CEFBS_InMicroMips, // SLTi_MM = 2567 |
| CEFBS_HasStdEnc_NotInMicroMips, // SLTiu = 2568 |
| CEFBS_NotInMips16Mode_IsGP64bit, // SLTiu64 = 2569 |
| CEFBS_InMicroMips, // SLTiu_MM = 2570 |
| CEFBS_HasStdEnc_NotInMicroMips, // SLTu = 2571 |
| CEFBS_NotInMips16Mode_IsGP64bit, // SLTu64 = 2572 |
| CEFBS_InMicroMips, // SLTu_MM = 2573 |
| CEFBS_HasCnMips, // SNE = 2574 |
| CEFBS_HasCnMips, // SNEi = 2575 |
| CEFBS_HasStdEnc_HasMSA, // SPLATI_B = 2576 |
| CEFBS_HasStdEnc_HasMSA, // SPLATI_D = 2577 |
| CEFBS_HasStdEnc_HasMSA, // SPLATI_H = 2578 |
| CEFBS_HasStdEnc_HasMSA, // SPLATI_W = 2579 |
| CEFBS_HasStdEnc_HasMSA, // SPLAT_B = 2580 |
| CEFBS_HasStdEnc_HasMSA, // SPLAT_D = 2581 |
| CEFBS_HasStdEnc_HasMSA, // SPLAT_H = 2582 |
| CEFBS_HasStdEnc_HasMSA, // SPLAT_W = 2583 |
| CEFBS_HasStdEnc_NotInMicroMips, // SRA = 2584 |
| CEFBS_HasStdEnc_HasMSA, // SRAI_B = 2585 |
| CEFBS_HasStdEnc_HasMSA, // SRAI_D = 2586 |
| CEFBS_HasStdEnc_HasMSA, // SRAI_H = 2587 |
| CEFBS_HasStdEnc_HasMSA, // SRAI_W = 2588 |
| CEFBS_HasStdEnc_HasMSA, // SRARI_B = 2589 |
| CEFBS_HasStdEnc_HasMSA, // SRARI_D = 2590 |
| CEFBS_HasStdEnc_HasMSA, // SRARI_H = 2591 |
| CEFBS_HasStdEnc_HasMSA, // SRARI_W = 2592 |
| CEFBS_HasStdEnc_HasMSA, // SRAR_B = 2593 |
| CEFBS_HasStdEnc_HasMSA, // SRAR_D = 2594 |
| CEFBS_HasStdEnc_HasMSA, // SRAR_H = 2595 |
| CEFBS_HasStdEnc_HasMSA, // SRAR_W = 2596 |
| CEFBS_HasStdEnc_NotInMicroMips, // SRAV = 2597 |
| CEFBS_InMicroMips, // SRAV_MM = 2598 |
| CEFBS_HasStdEnc_HasMSA, // SRA_B = 2599 |
| CEFBS_HasStdEnc_HasMSA, // SRA_D = 2600 |
| CEFBS_HasStdEnc_HasMSA, // SRA_H = 2601 |
| CEFBS_InMicroMips, // SRA_MM = 2602 |
| CEFBS_HasStdEnc_HasMSA, // SRA_W = 2603 |
| CEFBS_HasStdEnc_NotInMicroMips, // SRL = 2604 |
| CEFBS_InMicroMips_NotMips32r6, // SRL16_MM = 2605 |
| CEFBS_InMicroMips_HasMips32r6, // SRL16_MMR6 = 2606 |
| CEFBS_HasStdEnc_HasMSA, // SRLI_B = 2607 |
| CEFBS_HasStdEnc_HasMSA, // SRLI_D = 2608 |
| CEFBS_HasStdEnc_HasMSA, // SRLI_H = 2609 |
| CEFBS_HasStdEnc_HasMSA, // SRLI_W = 2610 |
| CEFBS_HasStdEnc_HasMSA, // SRLRI_B = 2611 |
| CEFBS_HasStdEnc_HasMSA, // SRLRI_D = 2612 |
| CEFBS_HasStdEnc_HasMSA, // SRLRI_H = 2613 |
| CEFBS_HasStdEnc_HasMSA, // SRLRI_W = 2614 |
| CEFBS_HasStdEnc_HasMSA, // SRLR_B = 2615 |
| CEFBS_HasStdEnc_HasMSA, // SRLR_D = 2616 |
| CEFBS_HasStdEnc_HasMSA, // SRLR_H = 2617 |
| CEFBS_HasStdEnc_HasMSA, // SRLR_W = 2618 |
| CEFBS_HasStdEnc_NotInMicroMips, // SRLV = 2619 |
| CEFBS_InMicroMips, // SRLV_MM = 2620 |
| CEFBS_HasStdEnc_HasMSA, // SRL_B = 2621 |
| CEFBS_HasStdEnc_HasMSA, // SRL_D = 2622 |
| CEFBS_HasStdEnc_HasMSA, // SRL_H = 2623 |
| CEFBS_InMicroMips, // SRL_MM = 2624 |
| CEFBS_HasStdEnc_HasMSA, // SRL_W = 2625 |
| CEFBS_HasStdEnc_NotInMicroMips, // SSNOP = 2626 |
| CEFBS_InMicroMips, // SSNOP_MM = 2627 |
| CEFBS_InMicroMips_HasMips32r6, // SSNOP_MMR6 = 2628 |
| CEFBS_HasStdEnc_HasMSA, // ST_B = 2629 |
| CEFBS_HasStdEnc_HasMSA, // ST_D = 2630 |
| CEFBS_HasStdEnc_HasMSA, // ST_H = 2631 |
| CEFBS_HasStdEnc_HasMSA, // ST_W = 2632 |
| CEFBS_HasStdEnc_NotInMicroMips, // SUB = 2633 |
| CEFBS_HasDSPR2, // SUBQH_PH = 2634 |
| CEFBS_InMicroMips_HasDSPR2, // SUBQH_PH_MMR2 = 2635 |
| CEFBS_HasDSPR2, // SUBQH_R_PH = 2636 |
| CEFBS_InMicroMips_HasDSPR2, // SUBQH_R_PH_MMR2 = 2637 |
| CEFBS_HasDSPR2, // SUBQH_R_W = 2638 |
| CEFBS_InMicroMips_HasDSPR2, // SUBQH_R_W_MMR2 = 2639 |
| CEFBS_HasDSPR2, // SUBQH_W = 2640 |
| CEFBS_InMicroMips_HasDSPR2, // SUBQH_W_MMR2 = 2641 |
| CEFBS_HasDSP, // SUBQ_PH = 2642 |
| CEFBS_InMicroMips_HasDSP, // SUBQ_PH_MM = 2643 |
| CEFBS_HasDSP, // SUBQ_S_PH = 2644 |
| CEFBS_InMicroMips_HasDSP, // SUBQ_S_PH_MM = 2645 |
| CEFBS_HasDSP, // SUBQ_S_W = 2646 |
| CEFBS_InMicroMips_HasDSP, // SUBQ_S_W_MM = 2647 |
| CEFBS_HasStdEnc_HasMSA, // SUBSUS_U_B = 2648 |
| CEFBS_HasStdEnc_HasMSA, // SUBSUS_U_D = 2649 |
| CEFBS_HasStdEnc_HasMSA, // SUBSUS_U_H = 2650 |
| CEFBS_HasStdEnc_HasMSA, // SUBSUS_U_W = 2651 |
| CEFBS_HasStdEnc_HasMSA, // SUBSUU_S_B = 2652 |
| CEFBS_HasStdEnc_HasMSA, // SUBSUU_S_D = 2653 |
| CEFBS_HasStdEnc_HasMSA, // SUBSUU_S_H = 2654 |
| CEFBS_HasStdEnc_HasMSA, // SUBSUU_S_W = 2655 |
| CEFBS_HasStdEnc_HasMSA, // SUBS_S_B = 2656 |
| CEFBS_HasStdEnc_HasMSA, // SUBS_S_D = 2657 |
| CEFBS_HasStdEnc_HasMSA, // SUBS_S_H = 2658 |
| CEFBS_HasStdEnc_HasMSA, // SUBS_S_W = 2659 |
| CEFBS_HasStdEnc_HasMSA, // SUBS_U_B = 2660 |
| CEFBS_HasStdEnc_HasMSA, // SUBS_U_D = 2661 |
| CEFBS_HasStdEnc_HasMSA, // SUBS_U_H = 2662 |
| CEFBS_HasStdEnc_HasMSA, // SUBS_U_W = 2663 |
| CEFBS_InMicroMips_NotMips32r6, // SUBU16_MM = 2664 |
| CEFBS_InMicroMips_HasMips32r6, // SUBU16_MMR6 = 2665 |
| CEFBS_HasDSPR2, // SUBUH_QB = 2666 |
| CEFBS_InMicroMips_HasDSPR2, // SUBUH_QB_MMR2 = 2667 |
| CEFBS_HasDSPR2, // SUBUH_R_QB = 2668 |
| CEFBS_InMicroMips_HasDSPR2, // SUBUH_R_QB_MMR2 = 2669 |
| CEFBS_InMicroMips_HasMips32r6, // SUBU_MMR6 = 2670 |
| CEFBS_HasDSPR2, // SUBU_PH = 2671 |
| CEFBS_InMicroMips_HasDSPR2, // SUBU_PH_MMR2 = 2672 |
| CEFBS_HasDSP, // SUBU_QB = 2673 |
| CEFBS_InMicroMips_HasDSP, // SUBU_QB_MM = 2674 |
| CEFBS_HasDSPR2, // SUBU_S_PH = 2675 |
| CEFBS_InMicroMips_HasDSPR2, // SUBU_S_PH_MMR2 = 2676 |
| CEFBS_HasDSP, // SUBU_S_QB = 2677 |
| CEFBS_InMicroMips_HasDSP, // SUBU_S_QB_MM = 2678 |
| CEFBS_HasStdEnc_HasMSA, // SUBVI_B = 2679 |
| CEFBS_HasStdEnc_HasMSA, // SUBVI_D = 2680 |
| CEFBS_HasStdEnc_HasMSA, // SUBVI_H = 2681 |
| CEFBS_HasStdEnc_HasMSA, // SUBVI_W = 2682 |
| CEFBS_HasStdEnc_HasMSA, // SUBV_B = 2683 |
| CEFBS_HasStdEnc_HasMSA, // SUBV_D = 2684 |
| CEFBS_HasStdEnc_HasMSA, // SUBV_H = 2685 |
| CEFBS_HasStdEnc_HasMSA, // SUBV_W = 2686 |
| CEFBS_InMicroMips_NotMips32r6, // SUB_MM = 2687 |
| CEFBS_InMicroMips_HasMips32r6, // SUB_MMR6 = 2688 |
| CEFBS_HasStdEnc_NotInMicroMips, // SUBu = 2689 |
| CEFBS_InMicroMips_NotMips32r6, // SUBu_MM = 2690 |
| CEFBS_HasStdEnc_NotFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // SUXC1 = 2691 |
| CEFBS_HasStdEnc_IsFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // SUXC164 = 2692 |
| CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // SUXC1_MM = 2693 |
| CEFBS_HasStdEnc_NotInMicroMips, // SW = 2694 |
| CEFBS_InMicroMips_NotMips32r6, // SW16_MM = 2695 |
| CEFBS_InMicroMips_HasMips32r6, // SW16_MMR6 = 2696 |
| CEFBS_NotInMips16Mode_IsGP64bit, // SW64 = 2697 |
| CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // SWC1 = 2698 |
| CEFBS_InMicroMips_IsNotSoftFloat, // SWC1_MM = 2699 |
| CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // SWC2 = 2700 |
| CEFBS_InMicroMips_HasMips32r6, // SWC2_MMR6 = 2701 |
| CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // SWC2_R6 = 2702 |
| CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotCnMips_NotInMicroMips, // SWC3 = 2703 |
| CEFBS_NotInMips16Mode_HasDSP, // SWDSP = 2704 |
| CEFBS_InMicroMips_HasDSP, // SWDSP_MM = 2705 |
| CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // SWE = 2706 |
| CEFBS_InMicroMips_HasEVA, // SWE_MM = 2707 |
| CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // SWL = 2708 |
| CEFBS_NotInMips16Mode_IsGP64bit, // SWL64 = 2709 |
| CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips, // SWLE = 2710 |
| CEFBS_InMicroMips_NotMips32r6_HasEVA, // SWLE_MM = 2711 |
| CEFBS_InMicroMips_NotMips32r6, // SWL_MM = 2712 |
| CEFBS_InMicroMips_NotMips32r6, // SWM16_MM = 2713 |
| CEFBS_InMicroMips_HasMips32r6, // SWM16_MMR6 = 2714 |
| CEFBS_InMicroMips, // SWM32_MM = 2715 |
| CEFBS_InMicroMips, // SWP_MM = 2716 |
| CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // SWR = 2717 |
| CEFBS_NotInMips16Mode_IsGP64bit, // SWR64 = 2718 |
| CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips, // SWRE = 2719 |
| CEFBS_InMicroMips_NotMips32r6_HasEVA, // SWRE_MM = 2720 |
| CEFBS_InMicroMips_NotMips32r6, // SWR_MM = 2721 |
| CEFBS_InMicroMips_NotMips32r6, // SWSP_MM = 2722 |
| CEFBS_InMicroMips_HasMips32r6, // SWSP_MMR6 = 2723 |
| CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat, // SWXC1 = 2724 |
| CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // SWXC1_MM = 2725 |
| CEFBS_InMicroMips, // SW_MM = 2726 |
| CEFBS_InMicroMips_HasMips32r6, // SW_MMR6 = 2727 |
| CEFBS_HasStdEnc_HasMips2_NotInMicroMips, // SYNC = 2728 |
| CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // SYNCI = 2729 |
| CEFBS_InMicroMips_NotMips32r6, // SYNCI_MM = 2730 |
| CEFBS_InMicroMips_HasMips32r6, // SYNCI_MMR6 = 2731 |
| CEFBS_InMicroMips, // SYNC_MM = 2732 |
| CEFBS_InMicroMips_HasMips32r6, // SYNC_MMR6 = 2733 |
| CEFBS_HasStdEnc_NotInMicroMips, // SYSCALL = 2734 |
| CEFBS_InMicroMips, // SYSCALL_MM = 2735 |
| CEFBS_InMips16Mode, // Save16 = 2736 |
| CEFBS_InMips16Mode, // SaveX16 = 2737 |
| CEFBS_InMips16Mode, // SbRxRyOffMemX16 = 2738 |
| CEFBS_InMips16Mode, // SebRx16 = 2739 |
| CEFBS_InMips16Mode, // SehRx16 = 2740 |
| CEFBS_InMips16Mode, // ShRxRyOffMemX16 = 2741 |
| CEFBS_InMips16Mode, // SllX16 = 2742 |
| CEFBS_InMips16Mode, // SllvRxRy16 = 2743 |
| CEFBS_InMips16Mode, // SltRxRy16 = 2744 |
| CEFBS_InMips16Mode, // SltiRxImm16 = 2745 |
| CEFBS_InMips16Mode, // SltiRxImmX16 = 2746 |
| CEFBS_InMips16Mode, // SltiuRxImm16 = 2747 |
| CEFBS_InMips16Mode, // SltiuRxImmX16 = 2748 |
| CEFBS_InMips16Mode, // SltuRxRy16 = 2749 |
| CEFBS_InMips16Mode, // SraX16 = 2750 |
| CEFBS_InMips16Mode, // SravRxRy16 = 2751 |
| CEFBS_InMips16Mode, // SrlX16 = 2752 |
| CEFBS_InMips16Mode, // SrlvRxRy16 = 2753 |
| CEFBS_InMips16Mode, // SubuRxRyRz16 = 2754 |
| CEFBS_InMips16Mode, // SwRxRyOffMemX16 = 2755 |
| CEFBS_InMips16Mode, // SwRxSpImmX16 = 2756 |
| CEFBS_HasStdEnc_HasMips2_NotInMicroMips, // TEQ = 2757 |
| CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // TEQI = 2758 |
| CEFBS_InMicroMips_NotMips32r6, // TEQI_MM = 2759 |
| CEFBS_InMicroMips, // TEQ_MM = 2760 |
| CEFBS_HasStdEnc_HasMips2_NotInMicroMips, // TGE = 2761 |
| CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // TGEI = 2762 |
| CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // TGEIU = 2763 |
| CEFBS_InMicroMips_NotMips32r6, // TGEIU_MM = 2764 |
| CEFBS_InMicroMips_NotMips32r6, // TGEI_MM = 2765 |
| CEFBS_HasStdEnc_HasMips2_NotInMicroMips, // TGEU = 2766 |
| CEFBS_InMicroMips, // TGEU_MM = 2767 |
| CEFBS_InMicroMips, // TGE_MM = 2768 |
| CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // TLBGINV = 2769 |
| CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // TLBGINVF = 2770 |
| CEFBS_InMicroMips_HasMips32r5_HasVirt, // TLBGINVF_MM = 2771 |
| CEFBS_InMicroMips_HasMips32r5_HasVirt, // TLBGINV_MM = 2772 |
| CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // TLBGP = 2773 |
| CEFBS_InMicroMips_HasMips32r5_HasVirt, // TLBGP_MM = 2774 |
| CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // TLBGR = 2775 |
| CEFBS_InMicroMips_HasMips32r5_HasVirt, // TLBGR_MM = 2776 |
| CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // TLBGWI = 2777 |
| CEFBS_InMicroMips_HasMips32r5_HasVirt, // TLBGWI_MM = 2778 |
| CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // TLBGWR = 2779 |
| CEFBS_InMicroMips_HasMips32r5_HasVirt, // TLBGWR_MM = 2780 |
| CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // TLBINV = 2781 |
| CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // TLBINVF = 2782 |
| CEFBS_InMicroMips_HasMips32r6, // TLBINVF_MMR6 = 2783 |
| CEFBS_InMicroMips_HasMips32r6, // TLBINV_MMR6 = 2784 |
| CEFBS_HasStdEnc_NotInMicroMips, // TLBP = 2785 |
| CEFBS_InMicroMips, // TLBP_MM = 2786 |
| CEFBS_HasStdEnc_NotInMicroMips, // TLBR = 2787 |
| CEFBS_InMicroMips, // TLBR_MM = 2788 |
| CEFBS_HasStdEnc_NotInMicroMips, // TLBWI = 2789 |
| CEFBS_InMicroMips, // TLBWI_MM = 2790 |
| CEFBS_HasStdEnc_NotInMicroMips, // TLBWR = 2791 |
| CEFBS_InMicroMips, // TLBWR_MM = 2792 |
| CEFBS_HasStdEnc_HasMips2_NotInMicroMips, // TLT = 2793 |
| CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // TLTI = 2794 |
| CEFBS_InMicroMips_NotMips32r6, // TLTIU_MM = 2795 |
| CEFBS_InMicroMips_NotMips32r6, // TLTI_MM = 2796 |
| CEFBS_HasStdEnc_HasMips2_NotInMicroMips, // TLTU = 2797 |
| CEFBS_InMicroMips, // TLTU_MM = 2798 |
| CEFBS_InMicroMips, // TLT_MM = 2799 |
| CEFBS_HasStdEnc_HasMips2_NotInMicroMips, // TNE = 2800 |
| CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // TNEI = 2801 |
| CEFBS_InMicroMips_NotMips32r6, // TNEI_MM = 2802 |
| CEFBS_InMicroMips, // TNE_MM = 2803 |
| CEFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips, // TRUNC_L_D64 = 2804 |
| CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // TRUNC_L_D_MMR6 = 2805 |
| CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // TRUNC_L_S = 2806 |
| CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // TRUNC_L_S_MMR6 = 2807 |
| CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // TRUNC_W_D32 = 2808 |
| CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // TRUNC_W_D64 = 2809 |
| CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // TRUNC_W_D_MMR6 = 2810 |
| CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // TRUNC_W_MM = 2811 |
| CEFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips, // TRUNC_W_S = 2812 |
| CEFBS_InMicroMips_IsNotSoftFloat, // TRUNC_W_S_MM = 2813 |
| CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // TRUNC_W_S_MMR6 = 2814 |
| CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // TTLTIU = 2815 |
| CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // UDIV = 2816 |
| CEFBS_InMicroMips_NotMips32r6, // UDIV_MM = 2817 |
| CEFBS_HasCnMips, // V3MULU = 2818 |
| CEFBS_HasCnMips, // VMM0 = 2819 |
| CEFBS_HasCnMips, // VMULU = 2820 |
| CEFBS_HasStdEnc_HasMSA, // VSHF_B = 2821 |
| CEFBS_HasStdEnc_HasMSA, // VSHF_D = 2822 |
| CEFBS_HasStdEnc_HasMSA, // VSHF_H = 2823 |
| CEFBS_HasStdEnc_HasMSA, // VSHF_W = 2824 |
| CEFBS_HasStdEnc_HasMips3_32_NotInMicroMips, // WAIT = 2825 |
| CEFBS_InMicroMips, // WAIT_MM = 2826 |
| CEFBS_InMicroMips_HasMips32r6, // WAIT_MMR6 = 2827 |
| CEFBS_HasDSP_NotInMicroMips, // WRDSP = 2828 |
| CEFBS_InMicroMips_HasDSP, // WRDSP_MM = 2829 |
| CEFBS_InMicroMips_HasMips32r6, // WRPGPR_MMR6 = 2830 |
| CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // WSBH = 2831 |
| CEFBS_InMicroMips, // WSBH_MM = 2832 |
| CEFBS_InMicroMips_HasMips32r6, // WSBH_MMR6 = 2833 |
| CEFBS_HasStdEnc_NotInMicroMips, // XOR = 2834 |
| CEFBS_InMicroMips_NotMips32r6, // XOR16_MM = 2835 |
| CEFBS_InMicroMips_HasMips32r6, // XOR16_MMR6 = 2836 |
| CEFBS_NotInMips16Mode_IsGP64bit, // XOR64 = 2837 |
| CEFBS_HasStdEnc_HasMSA, // XORI_B = 2838 |
| CEFBS_InMicroMips_HasMips32r6, // XORI_MMR6 = 2839 |
| CEFBS_InMicroMips_NotMips32r6, // XOR_MM = 2840 |
| CEFBS_InMicroMips_HasMips32r6, // XOR_MMR6 = 2841 |
| CEFBS_HasStdEnc_HasMSA, // XOR_V = 2842 |
| CEFBS_HasStdEnc_NotInMicroMips, // XORi = 2843 |
| CEFBS_NotInMips16Mode_IsGP64bit, // XORi64 = 2844 |
| CEFBS_InMicroMips_NotMips32r6, // XORi_MM = 2845 |
| CEFBS_InMips16Mode, // XorRxRxRy16 = 2846 |
| CEFBS_HasStdEnc_HasMT_NotInMicroMips, // YIELD = 2847 |
| }; |
| |
| assert(Opcode < 2848); |
| FeatureBitset AvailableFeatures = computeAvailableFeatures(Features); |
| const FeatureBitset &RequiredFeatures = FeatureBitsets[RequiredFeaturesRefs[Opcode]]; |
| FeatureBitset MissingFeatures = |
| (AvailableFeatures & RequiredFeatures) ^ |
| RequiredFeatures; |
| if (MissingFeatures.any()) { |
| std::ostringstream Msg; |
| Msg << "Attempting to emit " << &MipsInstrNameData[MipsInstrNameIndices[Opcode]] |
| << " instruction but the "; |
| for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i) |
| if (MissingFeatures.test(i)) |
| Msg << SubtargetFeatureNames[i] << " "; |
| Msg << "predicate(s) are not met"; |
| report_fatal_error(Msg.str().c_str()); |
| } |
| #endif // NDEBUG |
| } |
| } // end namespace Mips_MC |
| } // end namespace llvm |
| #endif // ENABLE_INSTR_PREDICATE_VERIFIER |
| |
| #ifdef GET_INSTRMAP_INFO |
| #undef GET_INSTRMAP_INFO |
| namespace llvm { |
| |
| namespace Mips { |
| |
| enum Arch { |
| Arch_dsp, |
| Arch_mmdsp, |
| Arch_mipsr6, |
| Arch_micromipsr6, |
| Arch_se, |
| Arch_micromips |
| }; |
| |
| // Dsp2MicroMips |
| LLVM_READONLY |
| int Dsp2MicroMips(uint16_t Opcode, enum Arch inArch) { |
| static const uint16_t Dsp2MicroMipsTable[][3] = { |
| { Mips::ABSQ_S_PH, Mips::ABSQ_S_PH, Mips::ABSQ_S_PH_MM }, |
| { Mips::ABSQ_S_QB, Mips::ABSQ_S_QB, Mips::ABSQ_S_QB_MMR2 }, |
| { Mips::ABSQ_S_W, Mips::ABSQ_S_W, Mips::ABSQ_S_W_MM }, |
| { Mips::ADDQH_PH, Mips::ADDQH_PH, Mips::ADDQH_PH_MMR2 }, |
| { Mips::ADDQH_R_PH, Mips::ADDQH_R_PH, Mips::ADDQH_R_PH_MMR2 }, |
| { Mips::ADDQH_R_W, Mips::ADDQH_R_W, Mips::ADDQH_R_W_MMR2 }, |
| { Mips::ADDQH_W, Mips::ADDQH_W, Mips::ADDQH_W_MMR2 }, |
| { Mips::ADDQ_PH, Mips::ADDQ_PH, Mips::ADDQ_PH_MM }, |
| { Mips::ADDQ_S_PH, Mips::ADDQ_S_PH, Mips::ADDQ_S_PH_MM }, |
| { Mips::ADDQ_S_W, Mips::ADDQ_S_W, Mips::ADDQ_S_W_MM }, |
| { Mips::ADDSC, Mips::ADDSC, Mips::ADDSC_MM }, |
| { Mips::ADDUH_QB, Mips::ADDUH_QB, Mips::ADDUH_QB_MMR2 }, |
| { Mips::ADDUH_R_QB, Mips::ADDUH_R_QB, Mips::ADDUH_R_QB_MMR2 }, |
| { Mips::ADDU_PH, Mips::ADDU_PH, Mips::ADDU_PH_MMR2 }, |
| { Mips::ADDU_QB, Mips::ADDU_QB, Mips::ADDU_QB_MM }, |
| { Mips::ADDU_S_PH, Mips::ADDU_S_PH, Mips::ADDU_S_PH_MMR2 }, |
| { Mips::ADDU_S_QB, Mips::ADDU_S_QB, Mips::ADDU_S_QB_MM }, |
| { Mips::ADDWC, Mips::ADDWC, Mips::ADDWC_MM }, |
| { Mips::APPEND, Mips::APPEND, Mips::APPEND_MMR2 }, |
| { Mips::BALIGN, Mips::BALIGN, Mips::BALIGN_MMR2 }, |
| { Mips::BITREV, Mips::BITREV, Mips::BITREV_MM }, |
| { Mips::BPOSGE32, Mips::BPOSGE32, Mips::BPOSGE32_MM }, |
| { Mips::CMPGDU_EQ_QB, Mips::CMPGDU_EQ_QB, Mips::CMPGDU_EQ_QB_MMR2 }, |
| { Mips::CMPGDU_LE_QB, Mips::CMPGDU_LE_QB, Mips::CMPGDU_LE_QB_MMR2 }, |
| { Mips::CMPGDU_LT_QB, Mips::CMPGDU_LT_QB, Mips::CMPGDU_LT_QB_MMR2 }, |
| { Mips::CMPGU_EQ_QB, Mips::CMPGU_EQ_QB, Mips::CMPGU_EQ_QB_MM }, |
| { Mips::CMPGU_LE_QB, Mips::CMPGU_LE_QB, Mips::CMPGU_LE_QB_MM }, |
| { Mips::CMPGU_LT_QB, Mips::CMPGU_LT_QB, Mips::CMPGU_LT_QB_MM }, |
| { Mips::CMPU_EQ_QB, Mips::CMPU_EQ_QB, Mips::CMPU_EQ_QB_MM }, |
| { Mips::CMPU_LE_QB, Mips::CMPU_LE_QB, Mips::CMPU_LE_QB_MM }, |
| { Mips::CMPU_LT_QB, Mips::CMPU_LT_QB, Mips::CMPU_LT_QB_MM }, |
| { Mips::CMP_EQ_PH, Mips::CMP_EQ_PH, Mips::CMP_EQ_PH_MM }, |
| { Mips::CMP_LE_PH, Mips::CMP_LE_PH, Mips::CMP_LE_PH_MM }, |
| { Mips::CMP_LT_PH, Mips::CMP_LT_PH, Mips::CMP_LT_PH_MM }, |
| { Mips::DPAQX_SA_W_PH, Mips::DPAQX_SA_W_PH, Mips::DPAQX_SA_W_PH_MMR2 }, |
| { Mips::DPAQX_S_W_PH, Mips::DPAQX_S_W_PH, Mips::DPAQX_S_W_PH_MMR2 }, |
| { Mips::DPAQ_SA_L_W, Mips::DPAQ_SA_L_W, Mips::DPAQ_SA_L_W_MM }, |
| { Mips::DPAQ_S_W_PH, Mips::DPAQ_S_W_PH, Mips::DPAQ_S_W_PH_MM }, |
| { Mips::DPAU_H_QBL, Mips::DPAU_H_QBL, Mips::DPAU_H_QBL_MM }, |
| { Mips::DPAU_H_QBR, Mips::DPAU_H_QBR, Mips::DPAU_H_QBR_MM }, |
| { Mips::DPAX_W_PH, Mips::DPAX_W_PH, Mips::DPAX_W_PH_MMR2 }, |
| { Mips::DPA_W_PH, Mips::DPA_W_PH, Mips::DPA_W_PH_MMR2 }, |
| { Mips::DPSQX_SA_W_PH, Mips::DPSQX_SA_W_PH, Mips::DPSQX_SA_W_PH_MMR2 }, |
| { Mips::DPSQX_S_W_PH, Mips::DPSQX_S_W_PH, Mips::DPSQX_S_W_PH_MMR2 }, |
| { Mips::DPSQ_SA_L_W, Mips::DPSQ_SA_L_W, Mips::DPSQ_SA_L_W_MM }, |
| { Mips::DPSQ_S_W_PH, Mips::DPSQ_S_W_PH, Mips::DPSQ_S_W_PH_MM }, |
| { Mips::DPSU_H_QBL, Mips::DPSU_H_QBL, Mips::DPSU_H_QBL_MM }, |
| { Mips::DPSU_H_QBR, Mips::DPSU_H_QBR, Mips::DPSU_H_QBR_MM }, |
| { Mips::DPSX_W_PH, Mips::DPSX_W_PH, Mips::DPSX_W_PH_MMR2 }, |
| { Mips::DPS_W_PH, Mips::DPS_W_PH, Mips::DPS_W_PH_MMR2 }, |
| { Mips::EXTP, Mips::EXTP, Mips::EXTP_MM }, |
| { Mips::EXTPDP, Mips::EXTPDP, Mips::EXTPDP_MM }, |
| { Mips::EXTPDPV, Mips::EXTPDPV, Mips::EXTPDPV_MM }, |
| { Mips::EXTPV, Mips::EXTPV, Mips::EXTPV_MM }, |
| { Mips::EXTRV_RS_W, Mips::EXTRV_RS_W, Mips::EXTRV_RS_W_MM }, |
| { Mips::EXTRV_R_W, Mips::EXTRV_R_W, Mips::EXTRV_R_W_MM }, |
| { Mips::EXTRV_S_H, Mips::EXTRV_S_H, Mips::EXTRV_S_H_MM }, |
| { Mips::EXTRV_W, Mips::EXTRV_W, Mips::EXTRV_W_MM }, |
| { Mips::EXTR_RS_W, Mips::EXTR_RS_W, Mips::EXTR_RS_W_MM }, |
| { Mips::EXTR_R_W, Mips::EXTR_R_W, Mips::EXTR_R_W_MM }, |
| { Mips::EXTR_S_H, Mips::EXTR_S_H, Mips::EXTR_S_H_MM }, |
| { Mips::EXTR_W, Mips::EXTR_W, Mips::EXTR_W_MM }, |
| { Mips::INSV, Mips::INSV, Mips::INSV_MM }, |
| { Mips::LBUX, Mips::LBUX, Mips::LBUX_MM }, |
| { Mips::LHX, Mips::LHX, Mips::LHX_MM }, |
| { Mips::LWDSP, Mips::LWDSP, Mips::LWDSP_MM }, |
| { Mips::LWX, Mips::LWX, Mips::LWX_MM }, |
| { Mips::MADDU_DSP, Mips::MADDU_DSP, Mips::MADDU_DSP_MM }, |
| { Mips::MADD_DSP, Mips::MADD_DSP, Mips::MADD_DSP_MM }, |
| { Mips::MAQ_SA_W_PHL, Mips::MAQ_SA_W_PHL, Mips::MAQ_SA_W_PHL_MM }, |
| { Mips::MAQ_SA_W_PHR, Mips::MAQ_SA_W_PHR, Mips::MAQ_SA_W_PHR_MM }, |
| { Mips::MAQ_S_W_PHL, Mips::MAQ_S_W_PHL, Mips::MAQ_S_W_PHL_MM }, |
| { Mips::MAQ_S_W_PHR, Mips::MAQ_S_W_PHR, Mips::MAQ_S_W_PHR_MM }, |
| { Mips::MFHI_DSP, Mips::MFHI_DSP, Mips::MFHI_DSP_MM }, |
| { Mips::MFLO_DSP, Mips::MFLO_DSP, Mips::MFLO_DSP_MM }, |
| { Mips::MODSUB, Mips::MODSUB, Mips::MODSUB_MM }, |
| { Mips::MSUBU_DSP, Mips::MSUBU_DSP, Mips::MSUBU_DSP_MM }, |
| { Mips::MSUB_DSP, Mips::MSUB_DSP, Mips::MSUB_DSP_MM }, |
| { Mips::MTHI_DSP, Mips::MTHI_DSP, Mips::MTHI_DSP_MM }, |
| { Mips::MTHLIP, Mips::MTHLIP, Mips::MTHLIP_MM }, |
| { Mips::MTLO_DSP, Mips::MTLO_DSP, Mips::MTLO_DSP_MM }, |
| { Mips::MULEQ_S_W_PHL, Mips::MULEQ_S_W_PHL, Mips::MULEQ_S_W_PHL_MM }, |
| { Mips::MULEQ_S_W_PHR, Mips::MULEQ_S_W_PHR, Mips::MULEQ_S_W_PHR_MM }, |
| { Mips::MULEU_S_PH_QBL, Mips::MULEU_S_PH_QBL, Mips::MULEU_S_PH_QBL_MM }, |
| { Mips::MULEU_S_PH_QBR, Mips::MULEU_S_PH_QBR, Mips::MULEU_S_PH_QBR_MM }, |
| { Mips::MULQ_RS_PH, Mips::MULQ_RS_PH, Mips::MULQ_RS_PH_MM }, |
| { Mips::MULQ_RS_W, Mips::MULQ_RS_W, Mips::MULQ_RS_W_MMR2 }, |
| { Mips::MULQ_S_PH, Mips::MULQ_S_PH, Mips::MULQ_S_PH_MMR2 }, |
| { Mips::MULQ_S_W, Mips::MULQ_S_W, Mips::MULQ_S_W_MMR2 }, |
| { Mips::MULSAQ_S_W_PH, Mips::MULSAQ_S_W_PH, Mips::MULSAQ_S_W_PH_MM }, |
| { Mips::MULSA_W_PH, Mips::MULSA_W_PH, Mips::MULSA_W_PH_MMR2 }, |
| { Mips::MULTU_DSP, Mips::MULTU_DSP, Mips::MULTU_DSP_MM }, |
| { Mips::MULT_DSP, Mips::MULT_DSP, Mips::MULT_DSP_MM }, |
| { Mips::MUL_PH, Mips::MUL_PH, Mips::MUL_PH_MMR2 }, |
| { Mips::MUL_S_PH, Mips::MUL_S_PH, Mips::MUL_S_PH_MMR2 }, |
| { Mips::PACKRL_PH, Mips::PACKRL_PH, Mips::PACKRL_PH_MM }, |
| { Mips::PICK_PH, Mips::PICK_PH, Mips::PICK_PH_MM }, |
| { Mips::PICK_QB, Mips::PICK_QB, Mips::PICK_QB_MM }, |
| { Mips::PRECEQU_PH_QBL, Mips::PRECEQU_PH_QBL, Mips::PRECEQU_PH_QBL_MM }, |
| { Mips::PRECEQU_PH_QBLA, Mips::PRECEQU_PH_QBLA, Mips::PRECEQU_PH_QBLA_MM }, |
| { Mips::PRECEQU_PH_QBR, Mips::PRECEQU_PH_QBR, Mips::PRECEQU_PH_QBR_MM }, |
| { Mips::PRECEQU_PH_QBRA, Mips::PRECEQU_PH_QBRA, Mips::PRECEQU_PH_QBRA_MM }, |
| { Mips::PRECEQ_W_PHL, Mips::PRECEQ_W_PHL, Mips::PRECEQ_W_PHL_MM }, |
| { Mips::PRECEQ_W_PHR, Mips::PRECEQ_W_PHR, Mips::PRECEQ_W_PHR_MM }, |
| { Mips::PRECEU_PH_QBL, Mips::PRECEU_PH_QBL, Mips::PRECEU_PH_QBL_MM }, |
| { Mips::PRECEU_PH_QBLA, Mips::PRECEU_PH_QBLA, Mips::PRECEU_PH_QBLA_MM }, |
| { Mips::PRECEU_PH_QBR, Mips::PRECEU_PH_QBR, Mips::PRECEU_PH_QBR_MM }, |
| { Mips::PRECEU_PH_QBRA, Mips::PRECEU_PH_QBRA, Mips::PRECEU_PH_QBRA_MM }, |
| { Mips::PRECRQU_S_QB_PH, Mips::PRECRQU_S_QB_PH, Mips::PRECRQU_S_QB_PH_MM }, |
| { Mips::PRECRQ_PH_W, Mips::PRECRQ_PH_W, Mips::PRECRQ_PH_W_MM }, |
| { Mips::PRECRQ_QB_PH, Mips::PRECRQ_QB_PH, Mips::PRECRQ_QB_PH_MM }, |
| { Mips::PRECRQ_RS_PH_W, Mips::PRECRQ_RS_PH_W, Mips::PRECRQ_RS_PH_W_MM }, |
| { Mips::PRECR_QB_PH, Mips::PRECR_QB_PH, Mips::PRECR_QB_PH_MMR2 }, |
| { Mips::PRECR_SRA_PH_W, Mips::PRECR_SRA_PH_W, Mips::PRECR_SRA_PH_W_MMR2 }, |
| { Mips::PRECR_SRA_R_PH_W, Mips::PRECR_SRA_R_PH_W, Mips::PRECR_SRA_R_PH_W_MMR2 }, |
| { Mips::PREPEND, Mips::PREPEND, Mips::PREPEND_MMR2 }, |
| { Mips::RADDU_W_QB, Mips::RADDU_W_QB, Mips::RADDU_W_QB_MM }, |
| { Mips::RDDSP, Mips::RDDSP, Mips::RDDSP_MM }, |
| { Mips::REPLV_PH, Mips::REPLV_PH, Mips::REPLV_PH_MM }, |
| { Mips::REPLV_QB, Mips::REPLV_QB, Mips::REPLV_QB_MM }, |
| { Mips::REPL_PH, Mips::REPL_PH, Mips::REPL_PH_MM }, |
| { Mips::REPL_QB, Mips::REPL_QB, Mips::REPL_QB_MM }, |
| { Mips::SHILO, Mips::SHILO, Mips::SHILO_MM }, |
| { Mips::SHILOV, Mips::SHILOV, Mips::SHILOV_MM }, |
| { Mips::SHLLV_PH, Mips::SHLLV_PH, Mips::SHLLV_PH_MM }, |
| { Mips::SHLLV_QB, Mips::SHLLV_QB, Mips::SHLLV_QB_MM }, |
| { Mips::SHLLV_S_PH, Mips::SHLLV_S_PH, Mips::SHLLV_S_PH_MM }, |
| { Mips::SHLLV_S_W, Mips::SHLLV_S_W, Mips::SHLLV_S_W_MM }, |
| { Mips::SHLL_PH, Mips::SHLL_PH, Mips::SHLL_PH_MM }, |
| { Mips::SHLL_QB, Mips::SHLL_QB, Mips::SHLL_QB_MM }, |
| { Mips::SHLL_S_PH, Mips::SHLL_S_PH, Mips::SHLL_S_PH_MM }, |
| { Mips::SHLL_S_W, Mips::SHLL_S_W, Mips::SHLL_S_W_MM }, |
| { Mips::SHRAV_PH, Mips::SHRAV_PH, Mips::SHRAV_PH_MM }, |
| { Mips::SHRAV_QB, Mips::SHRAV_QB, Mips::SHRAV_QB_MMR2 }, |
| { Mips::SHRAV_R_PH, Mips::SHRAV_R_PH, Mips::SHRAV_R_PH_MM }, |
| { Mips::SHRAV_R_QB, Mips::SHRAV_R_QB, Mips::SHRAV_R_QB_MMR2 }, |
| { Mips::SHRAV_R_W, Mips::SHRAV_R_W, Mips::SHRAV_R_W_MM }, |
| { Mips::SHRA_PH, Mips::SHRA_PH, Mips::SHRA_PH_MM }, |
| { Mips::SHRA_QB, Mips::SHRA_QB, Mips::SHRA_QB_MMR2 }, |
| { Mips::SHRA_R_PH, Mips::SHRA_R_PH, Mips::SHRA_R_PH_MM }, |
| { Mips::SHRA_R_QB, Mips::SHRA_R_QB, Mips::SHRA_R_QB_MMR2 }, |
| { Mips::SHRA_R_W, Mips::SHRA_R_W, Mips::SHRA_R_W_MM }, |
| { Mips::SHRLV_PH, Mips::SHRLV_PH, Mips::SHRLV_PH_MMR2 }, |
| { Mips::SHRLV_QB, Mips::SHRLV_QB, Mips::SHRLV_QB_MM }, |
| { Mips::SHRL_PH, Mips::SHRL_PH, Mips::SHRL_PH_MMR2 }, |
| { Mips::SHRL_QB, Mips::SHRL_QB, Mips::SHRL_QB_MM }, |
| { Mips::SUBQH_PH, Mips::SUBQH_PH, Mips::SUBQH_PH_MMR2 }, |
| { Mips::SUBQH_R_PH, Mips::SUBQH_R_PH, Mips::SUBQH_R_PH_MMR2 }, |
| { Mips::SUBQH_R_W, Mips::SUBQH_R_W, Mips::SUBQH_R_W_MMR2 }, |
| { Mips::SUBQH_W, Mips::SUBQH_W, Mips::SUBQH_W_MMR2 }, |
| { Mips::SUBQ_PH, Mips::SUBQ_PH, Mips::SUBQ_PH_MM }, |
| { Mips::SUBQ_S_PH, Mips::SUBQ_S_PH, Mips::SUBQ_S_PH_MM }, |
| { Mips::SUBQ_S_W, Mips::SUBQ_S_W, Mips::SUBQ_S_W_MM }, |
| { Mips::SUBUH_QB, Mips::SUBUH_QB, Mips::SUBUH_QB_MMR2 }, |
| { Mips::SUBUH_R_QB, Mips::SUBUH_R_QB, Mips::SUBUH_R_QB_MMR2 }, |
| { Mips::SUBU_PH, Mips::SUBU_PH, Mips::SUBU_PH_MMR2 }, |
| { Mips::SUBU_QB, Mips::SUBU_QB, Mips::SUBU_QB_MM }, |
| { Mips::SUBU_S_PH, Mips::SUBU_S_PH, Mips::SUBU_S_PH_MMR2 }, |
| { Mips::SUBU_S_QB, Mips::SUBU_S_QB, Mips::SUBU_S_QB_MM }, |
| { Mips::SWDSP, Mips::SWDSP, Mips::SWDSP_MM }, |
| }; // End of Dsp2MicroMipsTable |
| |
| unsigned mid; |
| unsigned start = 0; |
| unsigned end = 160; |
| while (start < end) { |
| mid = start + (end - start) / 2; |
| if (Opcode == Dsp2MicroMipsTable[mid][0]) { |
| break; |
| } |
| if (Opcode < Dsp2MicroMipsTable[mid][0]) |
| end = mid; |
| else |
| start = mid + 1; |
| } |
| if (start == end) |
| return -1; // Instruction doesn't exist in this table. |
| |
| if (inArch == Arch_dsp) |
| return Dsp2MicroMipsTable[mid][1]; |
| if (inArch == Arch_mmdsp) |
| return Dsp2MicroMipsTable[mid][2]; |
| return -1;} |
| |
| // MipsR62MicroMipsR6 |
| LLVM_READONLY |
| int MipsR62MicroMipsR6(uint16_t Opcode, enum Arch inArch) { |
| static const uint16_t MipsR62MicroMipsR6Table[][3] = { |
| { Mips::ADDIUPC, Mips::ADDIUPC, Mips::ADDIUPC_MMR6 }, |
| { Mips::ALIGN, Mips::ALIGN, Mips::ALIGN_MMR6 }, |
| { Mips::ALUIPC, Mips::ALUIPC, Mips::ALUIPC_MMR6 }, |
| { Mips::AUI, Mips::AUI, Mips::AUI_MMR6 }, |
| { Mips::AUIPC, Mips::AUIPC, Mips::AUIPC_MMR6 }, |
| { Mips::BALC, Mips::BALC, Mips::BALC_MMR6 }, |
| { Mips::BC, Mips::BC, Mips::BC_MMR6 }, |
| { Mips::BEQC, Mips::BEQC, Mips::BEQC_MMR6 }, |
| { Mips::BEQZALC, Mips::BEQZALC, Mips::BEQZALC_MMR6 }, |
| { Mips::BEQZC, Mips::BEQZC, Mips::BEQZC_MMR6 }, |
| { Mips::BGEC, Mips::BGEC, Mips::BGEC_MMR6 }, |
| { Mips::BGEUC, Mips::BGEUC, Mips::BGEUC_MMR6 }, |
| { Mips::BGEZALC, Mips::BGEZALC, Mips::BGEZALC_MMR6 }, |
| { Mips::BGEZC, Mips::BGEZC, Mips::BGEZC_MMR6 }, |
| { Mips::BGTZALC, Mips::BGTZALC, Mips::BGTZALC_MMR6 }, |
| { Mips::BGTZC, Mips::BGTZC, Mips::BGTZC_MMR6 }, |
| { Mips::BITSWAP, Mips::BITSWAP, Mips::BITSWAP_MMR6 }, |
| { Mips::BLEZALC, Mips::BLEZALC, Mips::BLEZALC_MMR6 }, |
| { Mips::BLEZC, Mips::BLEZC, Mips::BLEZC_MMR6 }, |
| { Mips::BLTC, Mips::BLTC, Mips::BLTC_MMR6 }, |
| { Mips::BLTUC, Mips::BLTUC, Mips::BLTUC_MMR6 }, |
| { Mips::BLTZALC, Mips::BLTZALC, Mips::BLTZALC_MMR6 }, |
| { Mips::BLTZC, Mips::BLTZC, Mips::BLTZC_MMR6 }, |
| { Mips::BNEC, Mips::BNEC, Mips::BNEC_MMR6 }, |
| { Mips::BNEZALC, Mips::BNEZALC, Mips::BNEZALC_MMR6 }, |
| { Mips::BNEZC, Mips::BNEZC, Mips::BNEZC_MMR6 }, |
| { Mips::BNVC, Mips::BNVC, Mips::BNVC_MMR6 }, |
| { Mips::BOVC, Mips::BOVC, Mips::BOVC_MMR6 }, |
| { Mips::CACHE_R6, Mips::CACHE_R6, Mips::CACHE_MMR6 }, |
| { Mips::CLO_R6, Mips::CLO_R6, Mips::CLO_MMR6 }, |
| { Mips::CLZ_R6, Mips::CLZ_R6, Mips::CLZ_MMR6 }, |
| { Mips::CMP_EQ_D, Mips::CMP_EQ_D, Mips::CMP_EQ_D_MMR6 }, |
| { Mips::CMP_EQ_S, Mips::CMP_EQ_S, Mips::CMP_EQ_S_MMR6 }, |
| { Mips::CMP_F_D, Mips::CMP_F_D, Mips::CMP_AF_D_MMR6 }, |
| { Mips::CMP_F_S, Mips::CMP_F_S, Mips::CMP_AF_S_MMR6 }, |
| { Mips::CMP_LE_D, Mips::CMP_LE_D, Mips::CMP_LE_D_MMR6 }, |
| { Mips::CMP_LE_S, Mips::CMP_LE_S, Mips::CMP_LE_S_MMR6 }, |
| { Mips::CMP_LT_D, Mips::CMP_LT_D, Mips::CMP_LT_D_MMR6 }, |
| { Mips::CMP_LT_S, Mips::CMP_LT_S, Mips::CMP_LT_S_MMR6 }, |
| { Mips::CMP_SAF_D, Mips::CMP_SAF_D, Mips::CMP_SAF_D_MMR6 }, |
| { Mips::CMP_SAF_S, Mips::CMP_SAF_S, Mips::CMP_SAF_S_MMR6 }, |
| { Mips::CMP_SEQ_D, Mips::CMP_SEQ_D, Mips::CMP_SEQ_D_MMR6 }, |
| { Mips::CMP_SEQ_S, Mips::CMP_SEQ_S, Mips::CMP_SEQ_S_MMR6 }, |
| { Mips::CMP_SLE_D, Mips::CMP_SLE_D, Mips::CMP_SLE_D_MMR6 }, |
| { Mips::CMP_SLE_S, Mips::CMP_SLE_S, Mips::CMP_SLE_S_MMR6 }, |
| { Mips::CMP_SLT_D, Mips::CMP_SLT_D, Mips::CMP_SLT_D_MMR6 }, |
| { Mips::CMP_SLT_S, Mips::CMP_SLT_S, Mips::CMP_SLT_S_MMR6 }, |
| { Mips::CMP_SUEQ_D, Mips::CMP_SUEQ_D, Mips::CMP_SUEQ_D_MMR6 }, |
| { Mips::CMP_SUEQ_S, Mips::CMP_SUEQ_S, Mips::CMP_SUEQ_S_MMR6 }, |
| { Mips::CMP_SULE_D, Mips::CMP_SULE_D, Mips::CMP_SULE_D_MMR6 }, |
| { Mips::CMP_SULE_S, Mips::CMP_SULE_S, Mips::CMP_SULE_S_MMR6 }, |
| { Mips::CMP_SULT_D, Mips::CMP_SULT_D, Mips::CMP_SULT_D_MMR6 }, |
| { Mips::CMP_SULT_S, Mips::CMP_SULT_S, Mips::CMP_SULT_S_MMR6 }, |
| { Mips::CMP_SUN_D, Mips::CMP_SUN_D, Mips::CMP_SUN_D_MMR6 }, |
| { Mips::CMP_SUN_S, Mips::CMP_SUN_S, Mips::CMP_SUN_S_MMR6 }, |
| { Mips::CMP_UEQ_D, Mips::CMP_UEQ_D, Mips::CMP_UEQ_D_MMR6 }, |
| { Mips::CMP_UEQ_S, Mips::CMP_UEQ_S, Mips::CMP_UEQ_S_MMR6 }, |
| { Mips::CMP_ULE_D, Mips::CMP_ULE_D, Mips::CMP_ULE_D_MMR6 }, |
| { Mips::CMP_ULE_S, Mips::CMP_ULE_S, Mips::CMP_ULE_S_MMR6 }, |
| { Mips::CMP_ULT_D, Mips::CMP_ULT_D, Mips::CMP_ULT_D_MMR6 }, |
| { Mips::CMP_ULT_S, Mips::CMP_ULT_S, Mips::CMP_ULT_S_MMR6 }, |
| { Mips::CMP_UN_D, Mips::CMP_UN_D, Mips::CMP_UN_D_MMR6 }, |
| { Mips::CMP_UN_S, Mips::CMP_UN_S, Mips::CMP_UN_S_MMR6 }, |
| { Mips::CRC32B, Mips::CRC32B, (uint16_t)-1U }, |
| { Mips::CRC32CB, Mips::CRC32CB, (uint16_t)-1U }, |
| { Mips::CRC32CD, Mips::CRC32CD, (uint16_t)-1U }, |
| { Mips::CRC32CH, Mips::CRC32CH, (uint16_t)-1U }, |
| { Mips::CRC32CW, Mips::CRC32CW, (uint16_t)-1U }, |
| { Mips::CRC32D, Mips::CRC32D, (uint16_t)-1U }, |
| { Mips::CRC32H, Mips::CRC32H, (uint16_t)-1U }, |
| { Mips::CRC32W, Mips::CRC32W, (uint16_t)-1U }, |
| { Mips::DIV, Mips::DIV, Mips::DIV_MMR6 }, |
| { Mips::DIVU, Mips::DIVU, Mips::DIVU_MMR6 }, |
| { Mips::DVP, Mips::DVP, Mips::DVP_MMR6 }, |
| { Mips::EVP, Mips::EVP, Mips::EVP_MMR6 }, |
| { Mips::GINVI, Mips::GINVI, Mips::GINVI_MMR6 }, |
| { Mips::GINVT, Mips::GINVT, Mips::GINVT_MMR6 }, |
| { Mips::JIALC, Mips::JIALC, Mips::JIALC_MMR6 }, |
| { Mips::JIC, Mips::JIC, Mips::JIC_MMR6 }, |
| { Mips::LSA_R6, Mips::LSA_R6, Mips::LSA_MMR6 }, |
| { Mips::LWPC, Mips::LWPC, Mips::LWPC_MMR6 }, |
| { Mips::MOD, Mips::MOD, Mips::MOD_MMR6 }, |
| { Mips::MODU, Mips::MODU, Mips::MODU_MMR6 }, |
| { Mips::MUH, Mips::MUH, Mips::MUH_MMR6 }, |
| { Mips::MUHU, Mips::MUHU, Mips::MUHU_MMR6 }, |
| { Mips::MULU, Mips::MULU, Mips::MULU_MMR6 }, |
| { Mips::MUL_R6, Mips::MUL_R6, Mips::MUL_MMR6 }, |
| { Mips::PREF_R6, Mips::PREF_R6, Mips::PREF_MMR6 }, |
| { Mips::SELEQZ, Mips::SELEQZ, Mips::SELEQZ_MMR6 }, |
| { Mips::SELEQZ_D, Mips::SELEQZ_D, Mips::SELEQZ_D_MMR6 }, |
| { Mips::SELEQZ_S, Mips::SELEQZ_S, Mips::SELEQZ_S_MMR6 }, |
| { Mips::SELNEZ, Mips::SELNEZ, Mips::SELNEZ_MMR6 }, |
| { Mips::SELNEZ_D, Mips::SELNEZ_D, Mips::SELNEZ_D_MMR6 }, |
| { Mips::SELNEZ_S, Mips::SELNEZ_S, Mips::SELNEZ_S_MMR6 }, |
| { Mips::SEL_D, Mips::SEL_D, Mips::SEL_D_MMR6 }, |
| { Mips::SEL_S, Mips::SEL_S, Mips::SEL_S_MMR6 }, |
| }; // End of MipsR62MicroMipsR6Table |
| |
| unsigned mid; |
| unsigned start = 0; |
| unsigned end = 96; |
| while (start < end) { |
| mid = start + (end - start) / 2; |
| if (Opcode == MipsR62MicroMipsR6Table[mid][0]) { |
| break; |
| } |
| if (Opcode < MipsR62MicroMipsR6Table[mid][0]) |
| end = mid; |
| else |
| start = mid + 1; |
| } |
| if (start == end) |
| return -1; // Instruction doesn't exist in this table. |
| |
| if (inArch == Arch_mipsr6) |
| return MipsR62MicroMipsR6Table[mid][1]; |
| if (inArch == Arch_micromipsr6) |
| return MipsR62MicroMipsR6Table[mid][2]; |
| return -1;} |
| |
| // Std2MicroMips |
| LLVM_READONLY |
| int Std2MicroMips(uint16_t Opcode, enum Arch inArch) { |
| static const uint16_t Std2MicroMipsTable[][3] = { |
| { Mips::ADD, Mips::ADD, Mips::ADD_MM }, |
| { Mips::ADDi, Mips::ADDi, Mips::ADDi_MM }, |
| { Mips::ADDiu, Mips::ADDiu, Mips::ADDiu_MM }, |
| { Mips::ADDu, Mips::ADDu, Mips::ADDu_MM }, |
| { Mips::AND, Mips::AND, Mips::AND_MM }, |
| { Mips::ANDi, Mips::ANDi, Mips::ANDi_MM }, |
| { Mips::BC1F, Mips::BC1F, Mips::BC1F_MM }, |
| { Mips::BC1FL, Mips::BC1FL, (uint16_t)-1U }, |
| { Mips::BC1T, Mips::BC1T, Mips::BC1T_MM }, |
| { Mips::BC1TL, Mips::BC1TL, (uint16_t)-1U }, |
| { Mips::BEQ, Mips::BEQ, Mips::BEQ_MM }, |
| { Mips::BEQL, Mips::BEQL, (uint16_t)-1U }, |
| { Mips::BGEZ, Mips::BGEZ, Mips::BGEZ_MM }, |
| { Mips::BGEZAL, Mips::BGEZAL, Mips::BGEZAL_MM }, |
| { Mips::BGEZALL, Mips::BGEZALL, (uint16_t)-1U }, |
| { Mips::BGEZL, Mips::BGEZL, (uint16_t)-1U }, |
| { Mips::BGTZ, Mips::BGTZ, Mips::BGTZ_MM }, |
| { Mips::BGTZL, Mips::BGTZL, (uint16_t)-1U }, |
| { Mips::BLEZ, Mips::BLEZ, Mips::BLEZ_MM }, |
| { Mips::BLEZL, Mips::BLEZL, (uint16_t)-1U }, |
| { Mips::BLTZ, Mips::BLTZ, Mips::BLTZ_MM }, |
| { Mips::BLTZAL, Mips::BLTZAL, Mips::BLTZAL_MM }, |
| { Mips::BLTZALL, Mips::BLTZALL, (uint16_t)-1U }, |
| { Mips::BLTZL, Mips::BLTZL, (uint16_t)-1U }, |
| { Mips::BNE, Mips::BNE, Mips::BNE_MM }, |
| { Mips::BNEL, Mips::BNEL, (uint16_t)-1U }, |
| { Mips::BREAK, Mips::BREAK, Mips::BREAK_MM }, |
| { Mips::CACHE, Mips::CACHE, Mips::CACHE_MM }, |
| { Mips::CACHEE, Mips::CACHEE, Mips::CACHEE_MM }, |
| { Mips::CEIL_W_D32, Mips::CEIL_W_D32, Mips::CEIL_W_MM }, |
| { Mips::CEIL_W_S, Mips::CEIL_W_S, Mips::CEIL_W_S_MM }, |
| { Mips::CFC1, Mips::CFC1, Mips::CFC1_MM }, |
| { Mips::CLO, Mips::CLO, Mips::CLO_MM }, |
| { Mips::CLZ, Mips::CLZ, Mips::CLZ_MM }, |
| { Mips::CTC1, Mips::CTC1, Mips::CTC1_MM }, |
| { Mips::CVT_D32_S, Mips::CVT_D32_S, Mips::CVT_D32_S_MM }, |
| { Mips::CVT_D32_W, Mips::CVT_D32_W, Mips::CVT_D32_W_MM }, |
| { Mips::CVT_L_D64, Mips::CVT_L_D64, Mips::CVT_L_D64_MM }, |
| { Mips::CVT_L_S, Mips::CVT_L_S, Mips::CVT_L_S_MM }, |
| { Mips::CVT_S_D32, Mips::CVT_S_D32, Mips::CVT_S_D32_MM }, |
| { Mips::CVT_S_W, Mips::CVT_S_W, Mips::CVT_S_W_MM }, |
| { Mips::CVT_W_D32, Mips::CVT_W_D32, Mips::CVT_W_D32_MM }, |
| { Mips::CVT_W_S, Mips::CVT_W_S, Mips::CVT_W_S_MM }, |
| { Mips::C_EQ_D32, Mips::C_EQ_D32, Mips::C_EQ_D32_MM }, |
| { Mips::C_EQ_D64, Mips::C_EQ_D64, Mips::C_EQ_D64_MM }, |
| { Mips::C_EQ_S, Mips::C_EQ_S, Mips::C_EQ_S_MM }, |
| { Mips::C_F_D32, Mips::C_F_D32, Mips::C_F_D32_MM }, |
| { Mips::C_F_D64, Mips::C_F_D64, Mips::C_F_D64_MM }, |
| { Mips::C_F_S, Mips::C_F_S, Mips::C_F_S_MM }, |
| { Mips::C_LE_D32, Mips::C_LE_D32, Mips::C_LE_D32_MM }, |
| { Mips::C_LE_D64, Mips::C_LE_D64, Mips::C_LE_D64_MM }, |
| { Mips::C_LE_S, Mips::C_LE_S, Mips::C_LE_S_MM }, |
| { Mips::C_LT_D32, Mips::C_LT_D32, Mips::C_LT_D32_MM }, |
| { Mips::C_LT_D64, Mips::C_LT_D64, Mips::C_LT_D64_MM }, |
| { Mips::C_LT_S, Mips::C_LT_S, Mips::C_LT_S_MM }, |
| { Mips::C_NGE_D32, Mips::C_NGE_D32, Mips::C_NGE_D32_MM }, |
| { Mips::C_NGE_D64, Mips::C_NGE_D64, Mips::C_NGE_D64_MM }, |
| { Mips::C_NGE_S, Mips::C_NGE_S, Mips::C_NGE_S_MM }, |
| { Mips::C_NGLE_D32, Mips::C_NGLE_D32, Mips::C_NGLE_D32_MM }, |
| { Mips::C_NGLE_D64, Mips::C_NGLE_D64, Mips::C_NGLE_D64_MM }, |
| { Mips::C_NGLE_S, Mips::C_NGLE_S, Mips::C_NGLE_S_MM }, |
| { Mips::C_NGL_D32, Mips::C_NGL_D32, Mips::C_NGL_D32_MM }, |
| { Mips::C_NGL_D64, Mips::C_NGL_D64, Mips::C_NGL_D64_MM }, |
| { Mips::C_NGL_S, Mips::C_NGL_S, Mips::C_NGL_S_MM }, |
| { Mips::C_NGT_D32, Mips::C_NGT_D32, Mips::C_NGT_D32_MM }, |
| { Mips::C_NGT_D64, Mips::C_NGT_D64, Mips::C_NGT_D64_MM }, |
| { Mips::C_NGT_S, Mips::C_NGT_S, Mips::C_NGT_S_MM }, |
| { Mips::C_OLE_D32, Mips::C_OLE_D32, Mips::C_OLE_D32_MM }, |
| { Mips::C_OLE_D64, Mips::C_OLE_D64, Mips::C_OLE_D64_MM }, |
| { Mips::C_OLE_S, Mips::C_OLE_S, Mips::C_OLE_S_MM }, |
| { Mips::C_OLT_D32, Mips::C_OLT_D32, Mips::C_OLT_D32_MM }, |
| { Mips::C_OLT_D64, Mips::C_OLT_D64, Mips::C_OLT_D64_MM }, |
| { Mips::C_OLT_S, Mips::C_OLT_S, Mips::C_OLT_S_MM }, |
| { Mips::C_SEQ_D32, Mips::C_SEQ_D32, Mips::C_SEQ_D32_MM }, |
| { Mips::C_SEQ_D64, Mips::C_SEQ_D64, Mips::C_SEQ_D64_MM }, |
| { Mips::C_SEQ_S, Mips::C_SEQ_S, Mips::C_SEQ_S_MM }, |
| { Mips::C_SF_D32, Mips::C_SF_D32, Mips::C_SF_D32_MM }, |
| { Mips::C_SF_D64, Mips::C_SF_D64, Mips::C_SF_D64_MM }, |
| { Mips::C_SF_S, Mips::C_SF_S, Mips::C_SF_S_MM }, |
| { Mips::C_UEQ_D32, Mips::C_UEQ_D32, Mips::C_UEQ_D32_MM }, |
| { Mips::C_UEQ_D64, Mips::C_UEQ_D64, Mips::C_UEQ_D64_MM }, |
| { Mips::C_UEQ_S, Mips::C_UEQ_S, Mips::C_UEQ_S_MM }, |
| { Mips::C_ULE_D32, Mips::C_ULE_D32, Mips::C_ULE_D32_MM }, |
| { Mips::C_ULE_D64, Mips::C_ULE_D64, Mips::C_ULE_D64_MM }, |
| { Mips::C_ULE_S, Mips::C_ULE_S, Mips::C_ULE_S_MM }, |
| { Mips::C_ULT_D32, Mips::C_ULT_D32, Mips::C_ULT_D32_MM }, |
| { Mips::C_ULT_D64, Mips::C_ULT_D64, Mips::C_ULT_D64_MM }, |
| { Mips::C_ULT_S, Mips::C_ULT_S, Mips::C_ULT_S_MM }, |
| { Mips::C_UN_D32, Mips::C_UN_D32, Mips::C_UN_D32_MM }, |
| { Mips::C_UN_D64, Mips::C_UN_D64, Mips::C_UN_D64_MM }, |
| { Mips::C_UN_S, Mips::C_UN_S, Mips::C_UN_S_MM }, |
| { Mips::DERET, Mips::DERET, Mips::DERET_MM }, |
| { Mips::DI, Mips::DI, Mips::DI_MM }, |
| { Mips::EHB, Mips::EHB, Mips::EHB_MM }, |
| { Mips::EI, Mips::EI, Mips::EI_MM }, |
| { Mips::ERET, Mips::ERET, Mips::ERET_MM }, |
| { Mips::ERETNC, Mips::ERETNC, (uint16_t)-1U }, |
| { Mips::EXT, Mips::EXT, Mips::EXT_MM }, |
| { Mips::FABS_D32, Mips::FABS_D32, Mips::FABS_D32_MM }, |
| { Mips::FABS_S, Mips::FABS_S, Mips::FABS_S_MM }, |
| { Mips::FADD_D32, Mips::FADD_D32, Mips::FADD_D32_MM }, |
| { Mips::FADD_S, Mips::FADD_S, Mips::FADD_S_MM }, |
| { Mips::FCMP_D32, Mips::FCMP_D32, Mips::FCMP_D32_MM }, |
| { Mips::FCMP_S32, Mips::FCMP_S32, Mips::FCMP_S32_MM }, |
| { Mips::FDIV_D32, Mips::FDIV_D32, Mips::FDIV_D32_MM }, |
| { Mips::FDIV_S, Mips::FDIV_S, Mips::FDIV_S_MM }, |
| { Mips::FLOOR_W_D32, Mips::FLOOR_W_D32, Mips::FLOOR_W_MM }, |
| { Mips::FLOOR_W_S, Mips::FLOOR_W_S, Mips::FLOOR_W_S_MM }, |
| { Mips::FMOV_D32, Mips::FMOV_D32, Mips::FMOV_D32_MM }, |
| { Mips::FMOV_S, Mips::FMOV_S, Mips::FMOV_S_MM }, |
| { Mips::FMUL_D32, Mips::FMUL_D32, Mips::FMUL_D32_MM }, |
| { Mips::FMUL_S, Mips::FMUL_S, Mips::FMUL_S_MM }, |
| { Mips::FNEG_D32, Mips::FNEG_D32, Mips::FNEG_D32_MM }, |
| { Mips::FNEG_S, Mips::FNEG_S, Mips::FNEG_S_MM }, |
| { Mips::FSQRT_D32, Mips::FSQRT_D32, Mips::FSQRT_D32_MM }, |
| { Mips::FSQRT_S, Mips::FSQRT_S, Mips::FSQRT_S_MM }, |
| { Mips::FSUB_D32, Mips::FSUB_D32, Mips::FSUB_D32_MM }, |
| { Mips::FSUB_S, Mips::FSUB_S, Mips::FSUB_S_MM }, |
| { Mips::HYPCALL, Mips::HYPCALL, Mips::HYPCALL_MM }, |
| { Mips::INS, Mips::INS, Mips::INS_MM }, |
| { Mips::J, Mips::J, Mips::J_MM }, |
| { Mips::JAL, Mips::JAL, Mips::JAL_MM }, |
| { Mips::JALX, Mips::JALX, Mips::JALX_MM }, |
| { Mips::JR, Mips::JR, Mips::JR_MM }, |
| { Mips::LB, Mips::LB, Mips::LB_MM }, |
| { Mips::LBE, Mips::LBE, Mips::LBE_MM }, |
| { Mips::LBu, Mips::LBu, Mips::LBu_MM }, |
| { Mips::LBuE, Mips::LBuE, Mips::LBuE_MM }, |
| { Mips::LDC1, Mips::LDC1, Mips::LDC1_MM_D32 }, |
| { Mips::LEA_ADDiu, Mips::LEA_ADDiu, Mips::LEA_ADDiu_MM }, |
| { Mips::LH, Mips::LH, Mips::LH_MM }, |
| { Mips::LHE, Mips::LHE, Mips::LHE_MM }, |
| { Mips::LHu, Mips::LHu, Mips::LHu_MM }, |
| { Mips::LHuE, Mips::LHuE, Mips::LHuE_MM }, |
| { Mips::LLE, Mips::LLE, Mips::LLE_MM }, |
| { Mips::LUXC1, Mips::LUXC1, Mips::LUXC1_MM }, |
| { Mips::LUi, Mips::LUi, Mips::LUi_MM }, |
| { Mips::LW, Mips::LW, Mips::LW_MM }, |
| { Mips::LWC1, Mips::LWC1, Mips::LWC1_MM }, |
| { Mips::LWE, Mips::LWE, Mips::LWE_MM }, |
| { Mips::LWL, Mips::LWL, Mips::LWL_MM }, |
| { Mips::LWLE, Mips::LWLE, Mips::LWLE_MM }, |
| { Mips::LWR, Mips::LWR, Mips::LWR_MM }, |
| { Mips::LWRE, Mips::LWRE, Mips::LWRE_MM }, |
| { Mips::LWXC1, Mips::LWXC1, Mips::LWXC1_MM }, |
| { Mips::LWu, Mips::LWu, Mips::LWU_MM }, |
| { Mips::MADD, Mips::MADD, Mips::MADD_MM }, |
| { Mips::MADDU, Mips::MADDU, Mips::MADDU_MM }, |
| { Mips::MADD_D32, Mips::MADD_D32, Mips::MADD_D32_MM }, |
| { Mips::MADD_S, Mips::MADD_S, Mips::MADD_S_MM }, |
| { Mips::MFC1, Mips::MFC1, Mips::MFC1_MM }, |
| { Mips::MFGC0, Mips::MFGC0, Mips::MFGC0_MM }, |
| { Mips::MFHC1_D32, Mips::MFHC1_D32, Mips::MFHC1_D32_MM }, |
| { Mips::MFHGC0, Mips::MFHGC0, Mips::MFHGC0_MM }, |
| { Mips::MFHI, Mips::MFHI, Mips::MFHI_MM }, |
| { Mips::MFLO, Mips::MFLO, Mips::MFLO_MM }, |
| { Mips::MOVF_D32, Mips::MOVF_D32, Mips::MOVF_D32_MM }, |
| { Mips::MOVF_I, Mips::MOVF_I, Mips::MOVF_I_MM }, |
| { Mips::MOVF_S, Mips::MOVF_S, Mips::MOVF_S_MM }, |
| { Mips::MOVN_I_D32, Mips::MOVN_I_D32, Mips::MOVN_I_D32_MM }, |
| { Mips::MOVN_I_I, Mips::MOVN_I_I, Mips::MOVN_I_MM }, |
| { Mips::MOVN_I_S, Mips::MOVN_I_S, Mips::MOVN_I_S_MM }, |
| { Mips::MOVT_D32, Mips::MOVT_D32, Mips::MOVT_D32_MM }, |
| { Mips::MOVT_I, Mips::MOVT_I, Mips::MOVT_I_MM }, |
| { Mips::MOVT_S, Mips::MOVT_S, Mips::MOVT_S_MM }, |
| { Mips::MOVZ_I_D32, Mips::MOVZ_I_D32, Mips::MOVZ_I_D32_MM }, |
| { Mips::MOVZ_I_I, Mips::MOVZ_I_I, Mips::MOVZ_I_MM }, |
| { Mips::MOVZ_I_S, Mips::MOVZ_I_S, Mips::MOVZ_I_S_MM }, |
| { Mips::MSUB, Mips::MSUB, Mips::MSUB_MM }, |
| { Mips::MSUBU, Mips::MSUBU, Mips::MSUBU_MM }, |
| { Mips::MSUB_D32, Mips::MSUB_D32, Mips::MSUB_D32_MM }, |
| { Mips::MSUB_S, Mips::MSUB_S, Mips::MSUB_S_MM }, |
| { Mips::MTC1, Mips::MTC1, Mips::MTC1_MM }, |
| { Mips::MTGC0, Mips::MTGC0, Mips::MTGC0_MM }, |
| { Mips::MTHC1_D32, Mips::MTHC1_D32, Mips::MTHC1_D32_MM }, |
| { Mips::MTHGC0, Mips::MTHGC0, Mips::MTHGC0_MM }, |
| { Mips::MTHI, Mips::MTHI, Mips::MTHI_MM }, |
| { Mips::MTLO, Mips::MTLO, Mips::MTLO_MM }, |
| { Mips::MUL, Mips::MUL, Mips::MUL_MM }, |
| { Mips::MULT, Mips::MULT, Mips::MULT_MM }, |
| { Mips::MULTu, Mips::MULTu, Mips::MULTu_MM }, |
| { Mips::NMADD_D32, Mips::NMADD_D32, Mips::NMADD_D32_MM }, |
| { Mips::NMADD_S, Mips::NMADD_S, Mips::NMADD_S_MM }, |
| { Mips::NMSUB_D32, Mips::NMSUB_D32, Mips::NMSUB_D32_MM }, |
| { Mips::NMSUB_S, Mips::NMSUB_S, Mips::NMSUB_S_MM }, |
| { Mips::NOR, Mips::NOR, Mips::NOR_MM }, |
| { Mips::OR, Mips::OR, Mips::OR_MM }, |
| { Mips::ORi, Mips::ORi, Mips::ORi_MM }, |
| { Mips::PAUSE, Mips::PAUSE, Mips::PAUSE_MM }, |
| { Mips::PREF, Mips::PREF, Mips::PREF_MM }, |
| { Mips::PREFE, Mips::PREFE, Mips::PREFE_MM }, |
| { Mips::RDHWR, Mips::RDHWR, Mips::RDHWR_MM }, |
| { Mips::RECIP_D32, Mips::RECIP_D32, Mips::RECIP_D32_MM }, |
| { Mips::RECIP_D64, Mips::RECIP_D64, Mips::RECIP_D64_MM }, |
| { Mips::RECIP_S, Mips::RECIP_S, Mips::RECIP_S_MM }, |
| { Mips::ROTR, Mips::ROTR, Mips::ROTR_MM }, |
| { Mips::ROTRV, Mips::ROTRV, Mips::ROTRV_MM }, |
| { Mips::ROUND_W_D32, Mips::ROUND_W_D32, Mips::ROUND_W_MM }, |
| { Mips::ROUND_W_S, Mips::ROUND_W_S, Mips::ROUND_W_S_MM }, |
| { Mips::RSQRT_D32, Mips::RSQRT_D32, Mips::RSQRT_D32_MM }, |
| { Mips::RSQRT_D64, Mips::RSQRT_D64, Mips::RSQRT_D64_MM }, |
| { Mips::RSQRT_S, Mips::RSQRT_S, Mips::RSQRT_S_MM }, |
| { Mips::SB, Mips::SB, Mips::SB_MM }, |
| { Mips::SBE, Mips::SBE, Mips::SBE_MM }, |
| { Mips::SCE, Mips::SCE, Mips::SCE_MM }, |
| { Mips::SDBBP, Mips::SDBBP, Mips::SDBBP_MM }, |
| { Mips::SDC1, Mips::SDC1, (uint16_t)-1U }, |
| { Mips::SDIV, Mips::SDIV, Mips::SDIV_MM }, |
| { Mips::SEB, Mips::SEB, Mips::SEB_MM }, |
| { Mips::SEH, Mips::SEH, Mips::SEH_MM }, |
| { Mips::SH, Mips::SH, Mips::SH_MM }, |
| { Mips::SHE, Mips::SHE, Mips::SHE_MM }, |
| { Mips::SLL, Mips::SLL, Mips::SLL_MM }, |
| { Mips::SLLV, Mips::SLLV, Mips::SLLV_MM }, |
| { Mips::SLT, Mips::SLT, Mips::SLT_MM }, |
| { Mips::SLTi, Mips::SLTi, Mips::SLTi_MM }, |
| { Mips::SLTiu, Mips::SLTiu, Mips::SLTiu_MM }, |
| { Mips::SLTu, Mips::SLTu, Mips::SLTu_MM }, |
| { Mips::SRA, Mips::SRA, Mips::SRA_MM }, |
| { Mips::SRAV, Mips::SRAV, Mips::SRAV_MM }, |
| { Mips::SRL, Mips::SRL, Mips::SRL_MM }, |
| { Mips::SRLV, Mips::SRLV, Mips::SRLV_MM }, |
| { Mips::SSNOP, Mips::SSNOP, Mips::SSNOP_MM }, |
| { Mips::SUB, Mips::SUB, Mips::SUB_MM }, |
| { Mips::SUBu, Mips::SUBu, Mips::SUBu_MM }, |
| { Mips::SUXC1, Mips::SUXC1, Mips::SUXC1_MM }, |
| { Mips::SW, Mips::SW, Mips::SW_MM }, |
| { Mips::SWC1, Mips::SWC1, Mips::SWC1_MM }, |
| { Mips::SWE, Mips::SWE, Mips::SWE_MM }, |
| { Mips::SWL, Mips::SWL, Mips::SWL_MM }, |
| { Mips::SWLE, Mips::SWLE, Mips::SWLE_MM }, |
| { Mips::SWR, Mips::SWR, Mips::SWR_MM }, |
| { Mips::SWRE, Mips::SWRE, Mips::SWRE_MM }, |
| { Mips::SWXC1, Mips::SWXC1, Mips::SWXC1_MM }, |
| { Mips::SYNC, Mips::SYNC, Mips::SYNC_MM }, |
| { Mips::SYNCI, Mips::SYNCI, Mips::SYNCI_MM }, |
| { Mips::SYSCALL, Mips::SYSCALL, Mips::SYSCALL_MM }, |
| { Mips::TEQ, Mips::TEQ, Mips::TEQ_MM }, |
| { Mips::TEQI, Mips::TEQI, Mips::TEQI_MM }, |
| { Mips::TGE, Mips::TGE, Mips::TGE_MM }, |
| { Mips::TGEI, Mips::TGEI, Mips::TGEI_MM }, |
| { Mips::TGEIU, Mips::TGEIU, Mips::TGEIU_MM }, |
| { Mips::TGEU, Mips::TGEU, Mips::TGEU_MM }, |
| { Mips::TLBGINV, Mips::TLBGINV, Mips::TLBGINV_MM }, |
| { Mips::TLBGINVF, Mips::TLBGINVF, Mips::TLBGINVF_MM }, |
| { Mips::TLBGP, Mips::TLBGP, Mips::TLBGP_MM }, |
| { Mips::TLBGR, Mips::TLBGR, Mips::TLBGR_MM }, |
| { Mips::TLBGWI, Mips::TLBGWI, Mips::TLBGWI_MM }, |
| { Mips::TLBGWR, Mips::TLBGWR, Mips::TLBGWR_MM }, |
| { Mips::TLBP, Mips::TLBP, Mips::TLBP_MM }, |
| { Mips::TLBR, Mips::TLBR, Mips::TLBR_MM }, |
| { Mips::TLBWI, Mips::TLBWI, Mips::TLBWI_MM }, |
| { Mips::TLBWR, Mips::TLBWR, Mips::TLBWR_MM }, |
| { Mips::TLT, Mips::TLT, Mips::TLT_MM }, |
| { Mips::TLTI, Mips::TLTI, Mips::TLTI_MM }, |
| { Mips::TLTU, Mips::TLTU, Mips::TLTU_MM }, |
| { Mips::TNE, Mips::TNE, Mips::TNE_MM }, |
| { Mips::TNEI, Mips::TNEI, Mips::TNEI_MM }, |
| { Mips::TRUNC_W_D32, Mips::TRUNC_W_D32, Mips::TRUNC_W_MM }, |
| { Mips::TRUNC_W_S, Mips::TRUNC_W_S, Mips::TRUNC_W_S_MM }, |
| { Mips::TTLTIU, Mips::TTLTIU, Mips::TLTIU_MM }, |
| { Mips::UDIV, Mips::UDIV, Mips::UDIV_MM }, |
| { Mips::WAIT, Mips::WAIT, Mips::WAIT_MM }, |
| { Mips::WSBH, Mips::WSBH, Mips::WSBH_MM }, |
| { Mips::XOR, Mips::XOR, Mips::XOR_MM }, |
| { Mips::XORi, Mips::XORi, Mips::XORi_MM }, |
| }; // End of Std2MicroMipsTable |
| |
| unsigned mid; |
| unsigned start = 0; |
| unsigned end = 266; |
| while (start < end) { |
| mid = start + (end - start) / 2; |
| if (Opcode == Std2MicroMipsTable[mid][0]) { |
| break; |
| } |
| if (Opcode < Std2MicroMipsTable[mid][0]) |
| end = mid; |
| else |
| start = mid + 1; |
| } |
| if (start == end) |
| return -1; // Instruction doesn't exist in this table. |
| |
| if (inArch == Arch_se) |
| return Std2MicroMipsTable[mid][1]; |
| if (inArch == Arch_micromips) |
| return Std2MicroMipsTable[mid][2]; |
| return -1;} |
| |
| // Std2MicroMipsR6 |
| LLVM_READONLY |
| int Std2MicroMipsR6(uint16_t Opcode, enum Arch inArch) { |
| static const uint16_t Std2MicroMipsR6Table[][3] = { |
| { Mips::ADD, Mips::ADD, Mips::ADD_MMR6 }, |
| { Mips::ADDiu, Mips::ADDiu, Mips::ADDIU_MMR6 }, |
| { Mips::ADDu, Mips::ADDu, Mips::ADDU_MMR6 }, |
| { Mips::AND, Mips::AND, Mips::AND_MMR6 }, |
| { Mips::ANDi, Mips::ANDi, Mips::ANDI_MMR6 }, |
| { Mips::BREAK, Mips::BREAK, Mips::BREAK_MMR6 }, |
| { Mips::CEIL_W_D64, Mips::CEIL_W_D64, Mips::CEIL_W_D_MMR6 }, |
| { Mips::CEIL_W_S, Mips::CEIL_W_S, Mips::CEIL_W_S_MMR6 }, |
| { Mips::CVT_W_D64, Mips::CVT_W_D64, (uint16_t)-1U }, |
| { Mips::DI, Mips::DI, Mips::DI_MMR6 }, |
| { Mips::EI, Mips::EI, Mips::EI_MMR6 }, |
| { Mips::EXT, Mips::EXT, Mips::EXT_MMR6 }, |
| { Mips::FABS_D64, Mips::FABS_D64, (uint16_t)-1U }, |
| { Mips::FLOOR_W_D64, Mips::FLOOR_W_D64, Mips::FLOOR_W_D_MMR6 }, |
| { Mips::FLOOR_W_S, Mips::FLOOR_W_S, Mips::FLOOR_W_S_MMR6 }, |
| { Mips::FMOV_D64, Mips::FMOV_D64, Mips::FMOV_D_MMR6 }, |
| { Mips::FNEG_D64, Mips::FNEG_D64, (uint16_t)-1U }, |
| { Mips::FSQRT_D64, Mips::FSQRT_D64, (uint16_t)-1U }, |
| { Mips::FSQRT_S, Mips::FSQRT_S, (uint16_t)-1U }, |
| { Mips::INS, Mips::INS, Mips::INS_MMR6 }, |
| { Mips::LDC1, Mips::LDC1, (uint16_t)-1U }, |
| { Mips::LDC164, Mips::LDC164, Mips::LDC1_D64_MMR6 }, |
| { Mips::LDC2, Mips::LDC2, Mips::LDC2_MMR6 }, |
| { Mips::LW, Mips::LW, Mips::LW_MMR6 }, |
| { Mips::LWC2, Mips::LWC2, Mips::LWC2_MMR6 }, |
| { Mips::MFC1, Mips::MFC1, Mips::MFC1_MMR6 }, |
| { Mips::MTC1, Mips::MTC1, Mips::MTC1_MMR6 }, |
| { Mips::MTHC1_D32, Mips::MTHC1_D32, (uint16_t)-1U }, |
| { Mips::NOR, Mips::NOR, Mips::NOR_MMR6 }, |
| { Mips::OR, Mips::OR, Mips::OR_MMR6 }, |
| { Mips::ORi, Mips::ORi, Mips::ORI_MMR6 }, |
| { Mips::PAUSE, Mips::PAUSE, Mips::PAUSE_MMR6 }, |
| { Mips::ROUND_W_D64, Mips::ROUND_W_D64, Mips::ROUND_W_D_MMR6 }, |
| { Mips::ROUND_W_S, Mips::ROUND_W_S, Mips::ROUND_W_S_MMR6 }, |
| { Mips::SB, Mips::SB, Mips::SB_MMR6 }, |
| { Mips::SDC164, Mips::SDC164, Mips::SDC1_D64_MMR6 }, |
| { Mips::SDC2, Mips::SDC2, Mips::SDC2_MMR6 }, |
| { Mips::SEB, Mips::SEB, (uint16_t)-1U }, |
| { Mips::SEH, Mips::SEH, (uint16_t)-1U }, |
| { Mips::SSNOP, Mips::SSNOP, Mips::SSNOP_MMR6 }, |
| { Mips::SUB, Mips::SUB, Mips::SUB_MMR6 }, |
| { Mips::SUBu, Mips::SUBu, Mips::SUBU_MMR6 }, |
| { Mips::SW, Mips::SW, Mips::SW_MMR6 }, |
| { Mips::SWC2, Mips::SWC2, Mips::SWC2_MMR6 }, |
| { Mips::SYNC, Mips::SYNC, Mips::SYNC_MMR6 }, |
| { Mips::SYNCI, Mips::SYNCI, Mips::SYNCI_MMR6 }, |
| { Mips::TRUNC_W_D64, Mips::TRUNC_W_D64, Mips::TRUNC_W_D_MMR6 }, |
| { Mips::TRUNC_W_S, Mips::TRUNC_W_S, Mips::TRUNC_W_S_MMR6 }, |
| { Mips::WAIT, Mips::WAIT, Mips::WAIT_MMR6 }, |
| { Mips::XOR, Mips::XOR, Mips::XOR_MMR6 }, |
| { Mips::XORi, Mips::XORi, Mips::XORI_MMR6 }, |
| }; // End of Std2MicroMipsR6Table |
| |
| unsigned mid; |
| unsigned start = 0; |
| unsigned end = 51; |
| while (start < end) { |
| mid = start + (end - start) / 2; |
| if (Opcode == Std2MicroMipsR6Table[mid][0]) { |
| break; |
| } |
| if (Opcode < Std2MicroMipsR6Table[mid][0]) |
| end = mid; |
| else |
| start = mid + 1; |
| } |
| if (start == end) |
| return -1; // Instruction doesn't exist in this table. |
| |
| if (inArch == Arch_se) |
| return Std2MicroMipsR6Table[mid][1]; |
| if (inArch == Arch_micromipsr6) |
| return Std2MicroMipsR6Table[mid][2]; |
| return -1;} |
| |
| } // end namespace Mips |
| } // end namespace llvm |
| #endif // GET_INSTRMAP_INFO |
| |
