| /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
| |* *| |
| |* Assembly Matcher Source Fragment *| |
| |* *| |
| |* Automatically generated file, do not edit! *| |
| |* *| |
| \*===----------------------------------------------------------------------===*/ |
| |
| |
| #ifdef GET_ASSEMBLER_HEADER |
| #undef GET_ASSEMBLER_HEADER |
| // This should be included into the middle of the declaration of |
| // your subclasses implementation of MCTargetAsmParser. |
| FeatureBitset ComputeAvailableFeatures(const FeatureBitset &FB) const; |
| void convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode, |
| const OperandVector &Operands); |
| void convertToMapAndConstraints(unsigned Kind, |
| const OperandVector &Operands) override; |
| unsigned MatchInstructionImpl(const OperandVector &Operands, |
| MCInst &Inst, |
| uint64_t &ErrorInfo, |
| FeatureBitset &MissingFeatures, |
| bool matchingInlineAsm, |
| unsigned VariantID = 0); |
| unsigned MatchInstructionImpl(const OperandVector &Operands, |
| MCInst &Inst, |
| uint64_t &ErrorInfo, |
| bool matchingInlineAsm, |
| unsigned VariantID = 0) { |
| FeatureBitset MissingFeatures; |
| return MatchInstructionImpl(Operands, Inst, ErrorInfo, MissingFeatures, |
| matchingInlineAsm, VariantID); |
| } |
| |
| OperandMatchResultTy MatchOperandParserImpl( |
| OperandVector &Operands, |
| StringRef Mnemonic, |
| bool ParseForAllFeatures = false); |
| OperandMatchResultTy tryCustomParseOperand( |
| OperandVector &Operands, |
| unsigned MCK); |
| |
| #endif // GET_ASSEMBLER_HEADER_INFO |
| |
| |
| #ifdef GET_OPERAND_DIAGNOSTIC_TYPES |
| #undef GET_OPERAND_DIAGNOSTIC_TYPES |
| |
| Match_Immz, |
| Match_MemSImm10, |
| Match_MemSImm10Lsl1, |
| Match_MemSImm10Lsl2, |
| Match_MemSImm10Lsl3, |
| Match_MemSImm11, |
| Match_MemSImm12, |
| Match_MemSImm16, |
| Match_MemSImm9, |
| Match_MemSImmPtr, |
| Match_SImm10_0, |
| Match_SImm10_Lsl1, |
| Match_SImm10_Lsl2, |
| Match_SImm10_Lsl3, |
| Match_SImm11_0, |
| Match_SImm16, |
| Match_SImm16_Relaxed, |
| Match_SImm19_Lsl2, |
| Match_SImm32, |
| Match_SImm32_Relaxed, |
| Match_SImm4_0, |
| Match_SImm5_0, |
| Match_SImm6_0, |
| Match_SImm7_Lsl2, |
| Match_SImm9_0, |
| Match_UImm10_0, |
| Match_UImm16, |
| Match_UImm16_AltRelaxed, |
| Match_UImm16_Relaxed, |
| Match_UImm1_0, |
| Match_UImm20_0, |
| Match_UImm26_0, |
| Match_UImm2_0, |
| Match_UImm2_1, |
| Match_UImm32_Coerced, |
| Match_UImm3_0, |
| Match_UImm4_0, |
| Match_UImm5_0, |
| Match_UImm5_0_Report_UImm6, |
| Match_UImm5_1, |
| Match_UImm5_32, |
| Match_UImm5_33, |
| Match_UImm5_Lsl2, |
| Match_UImm6_0, |
| Match_UImm6_Lsl2, |
| Match_UImm7_0, |
| Match_UImm7_N1, |
| Match_UImm8_0, |
| Match_UImmRange2_64, |
| END_OPERAND_DIAGNOSTIC_TYPES |
| #endif // GET_OPERAND_DIAGNOSTIC_TYPES |
| |
| |
| #ifdef GET_REGISTER_MATCHER |
| #undef GET_REGISTER_MATCHER |
| |
| // Bits for subtarget features that participate in instruction matching. |
| enum SubtargetFeatureBits : uint8_t { |
| Feature_HasMips2Bit = 11, |
| Feature_HasMips3_32Bit = 18, |
| Feature_HasMips3_32r2Bit = 19, |
| Feature_HasMips3Bit = 12, |
| Feature_NotMips3Bit = 47, |
| Feature_HasMips4_32Bit = 20, |
| Feature_NotMips4_32Bit = 49, |
| Feature_HasMips4_32r2Bit = 21, |
| Feature_HasMips5_32r2Bit = 22, |
| Feature_HasMips32Bit = 13, |
| Feature_HasMips32r2Bit = 14, |
| Feature_HasMips32r5Bit = 15, |
| Feature_HasMips32r6Bit = 16, |
| Feature_NotMips32r6Bit = 48, |
| Feature_IsGP64bitBit = 33, |
| Feature_IsGP32bitBit = 32, |
| Feature_IsPTR64bitBit = 37, |
| Feature_IsPTR32bitBit = 36, |
| Feature_HasMips64Bit = 23, |
| Feature_NotMips64Bit = 50, |
| Feature_HasMips64r2Bit = 24, |
| Feature_HasMips64r5Bit = 25, |
| Feature_HasMips64r6Bit = 26, |
| Feature_NotMips64r6Bit = 51, |
| Feature_InMips16ModeBit = 30, |
| Feature_NotInMips16ModeBit = 46, |
| Feature_HasCnMipsBit = 1, |
| Feature_NotCnMipsBit = 42, |
| Feature_HasCnMipsPBit = 2, |
| Feature_NotCnMipsPBit = 43, |
| Feature_IsSym32Bit = 39, |
| Feature_IsSym64Bit = 40, |
| Feature_HasStdEncBit = 27, |
| Feature_InMicroMipsBit = 29, |
| Feature_NotInMicroMipsBit = 45, |
| Feature_HasEVABit = 6, |
| Feature_HasMSABit = 8, |
| Feature_HasMadd4Bit = 10, |
| Feature_HasMTBit = 9, |
| Feature_UseIndirectJumpsHazardBit = 52, |
| Feature_NoIndirectJumpGuardsBit = 41, |
| Feature_HasCRCBit = 0, |
| Feature_HasVirtBit = 28, |
| Feature_HasGINVBit = 7, |
| Feature_IsFP64bitBit = 31, |
| Feature_NotFP64bitBit = 44, |
| Feature_IsSingleFloatBit = 38, |
| Feature_IsNotSingleFloatBit = 34, |
| Feature_IsNotSoftFloatBit = 35, |
| Feature_HasMips3DBit = 17, |
| Feature_HasDSPBit = 3, |
| Feature_HasDSPR2Bit = 4, |
| Feature_HasDSPR3Bit = 5, |
| }; |
| |
| #endif // GET_REGISTER_MATCHER |
| |
| |
| #ifdef GET_SUBTARGET_FEATURE_NAME |
| #undef GET_SUBTARGET_FEATURE_NAME |
| |
| // User-level names for subtarget features that participate in |
| // instruction matching. |
| static const char *getSubtargetFeatureName(uint64_t Val) { |
| switch(Val) { |
| case Feature_HasMips2Bit: return ""; |
| case Feature_HasMips3_32Bit: return ""; |
| case Feature_HasMips3_32r2Bit: return ""; |
| case Feature_HasMips3Bit: return ""; |
| case Feature_NotMips3Bit: return ""; |
| case Feature_HasMips4_32Bit: return ""; |
| case Feature_NotMips4_32Bit: return ""; |
| case Feature_HasMips4_32r2Bit: return ""; |
| case Feature_HasMips5_32r2Bit: return ""; |
| case Feature_HasMips32Bit: return ""; |
| case Feature_HasMips32r2Bit: return ""; |
| case Feature_HasMips32r5Bit: return ""; |
| case Feature_HasMips32r6Bit: return ""; |
| case Feature_NotMips32r6Bit: return ""; |
| case Feature_IsGP64bitBit: return ""; |
| case Feature_IsGP32bitBit: return ""; |
| case Feature_IsPTR64bitBit: return ""; |
| case Feature_IsPTR32bitBit: return ""; |
| case Feature_HasMips64Bit: return ""; |
| case Feature_NotMips64Bit: return ""; |
| case Feature_HasMips64r2Bit: return ""; |
| case Feature_HasMips64r5Bit: return ""; |
| case Feature_HasMips64r6Bit: return ""; |
| case Feature_NotMips64r6Bit: return ""; |
| case Feature_InMips16ModeBit: return ""; |
| case Feature_NotInMips16ModeBit: return ""; |
| case Feature_HasCnMipsBit: return ""; |
| case Feature_NotCnMipsBit: return ""; |
| case Feature_HasCnMipsPBit: return ""; |
| case Feature_NotCnMipsPBit: return ""; |
| case Feature_IsSym32Bit: return ""; |
| case Feature_IsSym64Bit: return ""; |
| case Feature_HasStdEncBit: return ""; |
| case Feature_InMicroMipsBit: return ""; |
| case Feature_NotInMicroMipsBit: return ""; |
| case Feature_HasEVABit: return ""; |
| case Feature_HasMSABit: return ""; |
| case Feature_HasMadd4Bit: return ""; |
| case Feature_HasMTBit: return ""; |
| case Feature_UseIndirectJumpsHazardBit: return ""; |
| case Feature_NoIndirectJumpGuardsBit: return ""; |
| case Feature_HasCRCBit: return ""; |
| case Feature_HasVirtBit: return ""; |
| case Feature_HasGINVBit: return ""; |
| case Feature_IsFP64bitBit: return ""; |
| case Feature_NotFP64bitBit: return ""; |
| case Feature_IsSingleFloatBit: return ""; |
| case Feature_IsNotSingleFloatBit: return ""; |
| case Feature_IsNotSoftFloatBit: return ""; |
| case Feature_HasMips3DBit: return ""; |
| case Feature_HasDSPBit: return ""; |
| case Feature_HasDSPR2Bit: return ""; |
| case Feature_HasDSPR3Bit: return ""; |
| default: return "(unknown)"; |
| } |
| } |
| |
| #endif // GET_SUBTARGET_FEATURE_NAME |
| |
| |
| #ifdef GET_MATCHER_IMPLEMENTATION |
| #undef GET_MATCHER_IMPLEMENTATION |
| |
| enum { |
| Tie0_1_1, |
| Tie0_1_2, |
| }; |
| |
| static const uint8_t TiedAsmOperandTable[][3] = { |
| /* Tie0_1_1 */ { 0, 1, 1 }, |
| /* Tie0_1_2 */ { 0, 1, 2 }, |
| }; |
| |
| namespace { |
| enum OperatorConversionKind { |
| CVT_Done, |
| CVT_Reg, |
| CVT_Tied, |
| CVT_95_addGPR32AsmRegOperands, |
| CVT_95_addAFGR64AsmRegOperands, |
| CVT_95_addFGR64AsmRegOperands, |
| CVT_95_addFGR32AsmRegOperands, |
| CVT_95_addSImmOperands_LT_32_GT_, |
| CVT_95_addMSA128AsmRegOperands, |
| CVT_95_addSImmOperands_LT_16_GT_, |
| CVT_95_Reg, |
| CVT_95_addImmOperands, |
| CVT_95_addGPRMM16AsmRegOperands, |
| CVT_95_addConstantSImmOperands_LT_4_44__32_0_GT_, |
| CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, |
| CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, |
| CVT_95_addUImmOperands_LT_16_GT_, |
| CVT_95_addGPR64AsmRegOperands, |
| CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_, |
| CVT_regZERO, |
| CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_, |
| CVT_regFCC0, |
| CVT_95_addFCCAsmRegOperands, |
| CVT_95_addCOP2AsmRegOperands, |
| CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, |
| CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_, |
| CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, |
| CVT_imm_95_0, |
| CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, |
| CVT_95_addMemOperands, |
| CVT_95_addConstantSImmOperands_LT_5_44__32_0_GT_, |
| CVT_95_addCCRAsmRegOperands, |
| CVT_95_addMSACtrlAsmRegOperands, |
| CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, |
| CVT_95_addConstantUImmOperands_LT_5_44__32_33_GT_, |
| CVT_95_addConstantUImmOperands_LT_5_44__32_32_GT_, |
| CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, |
| CVT_95_addGPR32NonZeroAsmRegOperands, |
| CVT_95_addGPR32ZeroAsmRegOperands, |
| CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_, |
| CVT_95_addCOP0AsmRegOperands, |
| CVT_regZERO_64, |
| CVT_95_addACC64DSPAsmRegOperands, |
| CVT_95_addConstantUImmOperands_LT_1_GT_, |
| CVT_regRA, |
| CVT_regRA_64, |
| CVT_95_addMicroMipsMemOperands, |
| CVT_95_addCOP3AsmRegOperands, |
| CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_, |
| CVT_95_addConstantUImmOperands_LT_32_GT_, |
| CVT_95_addStrictlyAFGR64AsmRegOperands, |
| CVT_95_addStrictlyFGR64AsmRegOperands, |
| CVT_95_addStrictlyFGR32AsmRegOperands, |
| CVT_95_addConstantUImmOperands_LT_7_44__32__MINUS_1_GT_, |
| CVT_95_addRegListOperands, |
| CVT_ConvertXWPOperands, |
| CVT_regAC0, |
| CVT_95_addGPRMM16AsmRegMovePPairFirstOperands, |
| CVT_95_addGPRMM16AsmRegMovePPairSecondOperands, |
| CVT_95_addGPRMM16AsmRegMovePOperands, |
| CVT_95_addHI32DSPAsmRegOperands, |
| CVT_95_addLO32DSPAsmRegOperands, |
| CVT_regS0, |
| CVT_95_addConstantUImmOperands_LT_7_44__32_0_GT_, |
| CVT_95_addHWRegsAsmRegOperands, |
| CVT_95_addGPRMM16AsmRegZeroOperands, |
| CVT_95_addConstantUImmOperands_LT_20_44__32_0_GT_, |
| CVT_95_addConstantSImmOperands_LT_6_44__32_0_GT_, |
| CVT_imm_95_2, |
| CVT_imm_95_6, |
| CVT_imm_95_4, |
| CVT_imm_95_5, |
| CVT_imm_95_31, |
| CVT_NUM_CONVERTERS |
| }; |
| |
| enum InstructionConversionKind { |
| Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, |
| Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, |
| Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, |
| Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, |
| Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, |
| Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, |
| Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, |
| Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, |
| Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, |
| Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, |
| Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, |
| Convert__FGR32AsmReg1_0__FGR32AsmReg1_2__FGR32AsmReg1_1, |
| Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, |
| Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1, |
| Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm16_Relaxed1_1, |
| Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, |
| Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm16_Relaxed1_2, |
| Convert__SImm161_1, |
| Convert__Reg1_0__SImm161_1, |
| Convert__Reg1_0__SImm161_2, |
| Convert__Reg1_0__Reg1_1__SImm161_2, |
| Convert__Reg1_0__Tie0_1_1__SImm161_1, |
| Convert__GPR32AsmReg1_0__Simm19_Lsl21_1, |
| Convert__GPRMM16AsmReg1_0__Imm1_1, |
| Convert__GPRMM16AsmReg1_0__UImm6Lsl21_1, |
| Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2, |
| Convert__GPR32AsmReg1_0__Tie0_1_1__ConstantSImm4_01_1, |
| Convert__Imm1_0, |
| Convert__Reg1_0__Reg1_1__Reg1_2, |
| Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__GPRMM16AsmReg1_2, |
| Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, |
| Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_01_3, |
| Convert__GPR32AsmReg1_0__SImm161_1, |
| Convert__Reg1_0__Tie0_1_1__Reg1_1, |
| Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, |
| Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, |
| Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, |
| Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, |
| Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0_1_1, |
| Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2, |
| Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1, |
| Convert__regZERO__regZERO__JumpTarget1_0, |
| Convert__JumpTarget1_0, |
| Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, |
| Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, |
| Convert__regZERO__JumpTarget1_0, |
| Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm2_01_2__Tie0_1_1, |
| Convert__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__JumpTarget1_2, |
| Convert__GPR64AsmReg1_0__ConstantUImm5_0_Report_UImm61_1__JumpTarget1_2, |
| Convert__GPR64AsmReg1_0__ConstantUImm5_01_1__JumpTarget1_2, |
| Convert__FGR64AsmReg1_0__JumpTarget1_1, |
| Convert__regFCC0__JumpTarget1_0, |
| Convert__FCCAsmReg1_0__JumpTarget1_1, |
| Convert__COP2AsmReg1_0__JumpTarget1_1, |
| Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, |
| Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, |
| Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, |
| Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, |
| Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, |
| Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__JumpTarget1_2, |
| Convert__Reg1_0__JumpTarget1_1, |
| Convert__GPR32AsmReg1_0__regZERO__JumpTarget1_1, |
| Convert__GPRMM16AsmReg1_0__JumpTarget1_1, |
| Convert__GPR32AsmReg1_0__JumpTarget1_1, |
| Convert__GPR64AsmReg1_0__JumpTarget1_1, |
| Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, |
| Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm3_01_2, |
| Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm6_01_2, |
| Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm4_01_2, |
| Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm5_01_2, |
| Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm8_01_2, |
| Convert__MSA128AsmReg1_0__JumpTarget1_1, |
| Convert__imm_95_0__imm_95_0, |
| Convert_NoOperands, |
| Convert__ConstantUImm10_01_0__imm_95_0, |
| Convert__ConstantUImm10_01_0__ConstantUImm10_01_1, |
| Convert__ConstantUImm4_01_0, |
| Convert__SImm161_0, |
| Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, |
| Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, |
| Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, |
| Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, |
| Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, |
| Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, |
| Convert__MemOffsetSimm9_02_1__ConstantUImm5_01_0, |
| Convert__Mem2_1__ConstantUImm5_01_0, |
| Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, |
| Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, |
| Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, |
| Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, |
| Convert__GPR32AsmReg1_0__CCRAsmReg1_1, |
| Convert__GPR32AsmReg1_0__COP2AsmReg1_1, |
| Convert__GPR32AsmReg1_0__MSACtrlAsmReg1_1, |
| Convert__GPR32AsmReg1_0__FGR32AsmReg1_1, |
| Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1__ConstantUImm5_01_2, |
| Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__ConstantUImm5_01_2, |
| Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_01_3, |
| Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_32_Norm1_2__ConstantUImm5_01_3, |
| Convert__Reg1_0__Reg1_1, |
| Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, |
| Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_3, |
| Convert__GPR64AsmReg1_0__MSA128AsmReg1_1__ConstantUImm1_01_3, |
| Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_3, |
| Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm2_01_3, |
| Convert__CCRAsmReg1_1__GPR32AsmReg1_0, |
| Convert__COP2AsmReg1_1__GPR32AsmReg1_0, |
| Convert__MSACtrlAsmReg1_0__GPR32AsmReg1_1, |
| Convert__FGR32AsmReg1_1__GPR32AsmReg1_0, |
| Convert__AFGR64AsmReg1_0__FGR32AsmReg1_1, |
| Convert__FGR64AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, |
| Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm161_1, |
| Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm161_2, |
| Convert__GPR64AsmReg1_0__Tie0_1_2__UImm16_AltRelaxed1_2, |
| Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm3_01_3, |
| Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__UImm161_2, |
| Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, |
| Convert__GPR64AsmReg1_1__GPR64AsmReg1_2, |
| Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_331_3, |
| Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3, |
| Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_0_Report_UImm61_2__ConstantUImm5_Plus1_Report_UImm61_3, |
| Convert__regZERO, |
| Convert__GPR32AsmReg1_0, |
| Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImmRange2_641_3__Tie0_1_1, |
| Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3__Tie0_1_1, |
| Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2__ConstantUImm5_11_3__Tie0_1_1, |
| Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm321_1, |
| Convert__GPR32NonZeroAsmReg1_0__GPR32NonZeroAsmReg1_0__GPR32AsmReg1_1, |
| Convert__GPR32ZeroAsmReg1_0__GPR32AsmReg1_1, |
| Convert__Reg1_1__Reg1_2, |
| Convert__GPR32AsmReg1_1__GPR32AsmReg1_2, |
| Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm321_2, |
| Convert__GPR32NonZeroAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, |
| Convert__GPR64AsmReg1_0__Imm1_1, |
| Convert__GPR64AsmReg1_0__Mem2_1, |
| Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm2_11_3, |
| Convert__GPR64AsmReg1_0__COP0AsmReg1_1__imm_95_0, |
| Convert__GPR64AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, |
| Convert__GPR64AsmReg1_0__FGR64AsmReg1_1, |
| Convert__GPR64AsmReg1_0__COP2AsmReg1_1__imm_95_0, |
| Convert__GPR64AsmReg1_0__UImm161_1, |
| Convert__GPR64AsmReg1_0__COP2AsmReg1_1__ConstantUImm3_01_2, |
| Convert__COP0AsmReg1_1__GPR64AsmReg1_0__imm_95_0, |
| Convert__COP0AsmReg1_1__GPR64AsmReg1_0__ConstantUImm3_01_2, |
| Convert__FGR64AsmReg1_1__GPR64AsmReg1_0, |
| Convert__COP2AsmReg1_1__GPR64AsmReg1_0__imm_95_0, |
| Convert__COP2AsmReg1_1__GPR64AsmReg1_0__ConstantUImm3_01_2, |
| Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm32_Relaxed1_2, |
| Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_0, |
| Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_1, |
| Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, |
| Convert__GPR64AsmReg1_0__GPR64AsmReg1_0, |
| Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm32_Relaxed1_1, |
| Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm6_01_1, |
| Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2, |
| Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1, |
| Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2, |
| Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, |
| Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR32AsmReg1_1, |
| Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__InvNum1_1, |
| Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__InvNum1_2, |
| Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3, |
| Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, |
| Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, |
| Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, |
| Convert__MSA128AsmReg1_0__GPR32AsmReg1_1, |
| Convert__MSA128AsmReg1_0__GPR64AsmReg1_1, |
| Convert__GPR32AsmReg1_1__GPR32AsmReg1_0__GPR32AsmReg1_2, |
| Convert__GPR32AsmReg1_0__ConstantUImm2_01_1, |
| Convert__imm_95_0, |
| Convert__ConstantUImm10_01_0, |
| Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3__Tie0_1_1, |
| Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm4_01_2, |
| Convert__MSA128AsmReg1_0__Tie0_1_1__GPR64AsmReg1_4__ConstantUImm1_01_2, |
| Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm3_01_2, |
| Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm2_01_2, |
| Convert__GPR32AsmReg1_0__Tie0_1_1__GPR32AsmReg1_1, |
| Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm4_01_2__MSA128AsmReg1_4__ConstantImmz1_6, |
| Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm1_01_2__MSA128AsmReg1_4__ConstantImmz1_6, |
| Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm3_01_2__MSA128AsmReg1_4__ConstantImmz1_6, |
| Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm2_01_2__MSA128AsmReg1_4__ConstantImmz1_6, |
| Convert__regRA__GPR32AsmReg1_0, |
| Convert__regRA_64__GPR64AsmReg1_0, |
| Convert__Reg1_0, |
| Convert__GPR32AsmReg1_0__imm_95_0, |
| Convert__GPR64AsmReg1_0__imm_95_0, |
| Convert__regZERO__GPR32AsmReg1_0, |
| Convert__GPR64AsmReg1_0, |
| Convert__regZERO_64__GPR64AsmReg1_0, |
| Convert__UImm5Lsl21_0, |
| Convert__AFGR64AsmReg1_0__MemOffsetSimm16_02_1, |
| Convert__FGR64AsmReg1_0__MemOffsetSimm16_02_1, |
| Convert__FGR32AsmReg1_0__MemOffsetSimm16_02_1, |
| Convert__GPR32AsmReg1_0__Imm1_1, |
| Convert__GPR32AsmReg1_0__Mem2_1, |
| Convert__GPR32AsmReg1_0__MemOffsetSimmPtr2_1, |
| Convert__GPR32AsmReg1_0__MemOffsetSimm16_02_1, |
| Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1, |
| Convert__GPRMM16AsmReg1_0__MicroMipsMem2_1, |
| Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, |
| Convert__GPR64AsmReg1_0__MemOffsetSimmPtr2_1, |
| Convert__MSA128AsmReg1_0__MemOffsetSimm10_02_1, |
| Convert__MSA128AsmReg1_0__MemOffsetSimm10_32_1, |
| Convert__MSA128AsmReg1_0__MemOffsetSimm10_12_1, |
| Convert__MSA128AsmReg1_0__MemOffsetSimm10_22_1, |
| Convert__COP2AsmReg1_0__MemOffsetSimm11_02_1, |
| Convert__COP2AsmReg1_0__MemOffsetSimm16_02_1, |
| Convert__COP3AsmReg1_0__Mem2_1, |
| Convert__MSA128AsmReg1_0__ConstantSImm10_01_1, |
| Convert__GPR64AsmReg1_0__Mem2_1__Tie0_1_1, |
| Convert__AFGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, |
| Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, |
| Convert__GPR32AsmReg1_0__UImm32_Coerced1_1, |
| Convert__StrictlyAFGR64AsmReg1_0__Imm1_1, |
| Convert__StrictlyFGR64AsmReg1_0__Imm1_1, |
| Convert__StrictlyFGR32AsmReg1_0__Imm1_1, |
| Convert__GPRMM16AsmReg1_0__UImm7_N11_1, |
| Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_11_3, |
| Convert__GPR32AsmReg1_2__GPR32AsmReg1_1__GPR32AsmReg1_0__ConstantUImm2_11_3, |
| Convert__GPR32AsmReg1_0__UImm161_1, |
| Convert__GPR32AsmReg1_0__UImm16_Relaxed1_1, |
| Convert__Reg1_0__Imm1_1__imm_95_0, |
| Convert__GPR32AsmReg1_0__MicroMipsMemSP2_1, |
| Convert__GPRMM16AsmReg1_0__MicroMipsMemGP2_1, |
| Convert__GPR32AsmReg1_0__Mem2_1__Tie0_1_1, |
| Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1__Tie0_1_1, |
| Convert__RegList1_0__Mem2_1, |
| Convert__RegList161_0__MemOffsetUimm42_1, |
| ConvertCustom_ConvertXWPOperands, |
| Convert__GPR32AsmReg1_0__MemOffsetSimm12_02_1, |
| Convert__FGR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, |
| Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3, |
| Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2__FGR64AsmReg1_3, |
| Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3, |
| Convert__FGR64AsmReg1_0__Tie0_1_1__FGR64AsmReg1_1__FGR64AsmReg1_2, |
| Convert__FGR32AsmReg1_0__Tie0_1_1__FGR32AsmReg1_1__FGR32AsmReg1_2, |
| Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, |
| Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, |
| Convert__GPR32AsmReg1_0__FGR64AsmReg1_1, |
| Convert__GPR32AsmReg1_0__COP2AsmReg1_1__imm_95_0, |
| Convert__GPR32AsmReg1_0__COP2AsmReg1_1__ConstantUImm3_01_2, |
| Convert__GPR32AsmReg1_0__AFGR64AsmReg1_1, |
| Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1, |
| Convert__GPR32AsmReg1_0__regAC0, |
| Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, |
| Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm1_01_2__ConstantUImm3_01_3__ConstantUImm1_01_4, |
| Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__regZERO, |
| Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__regZERO_64, |
| Convert__GPRMM16AsmRegMovePPairFirst1_0__GPRMM16AsmRegMovePPairSecond1_1__GPRMM16AsmRegMoveP1_2__GPRMM16AsmRegMoveP1_3, |
| Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, |
| Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, |
| Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, |
| Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, |
| Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, |
| Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, |
| Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, |
| Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, |
| Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, |
| Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, |
| Convert__FGR64AsmReg1_1__GPR32AsmReg1_0, |
| Convert__COP2AsmReg1_1__GPR32AsmReg1_0__imm_95_0, |
| Convert__COP2AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, |
| Convert__AFGR64AsmReg1_1__Tie0_1_1__GPR32AsmReg1_0, |
| Convert__FGR64AsmReg1_1__Tie0_1_1__GPR32AsmReg1_0, |
| Convert__HI32DSPAsmReg1_1__GPR32AsmReg1_0, |
| Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0__Tie0_1_1, |
| Convert__LO32DSPAsmReg1_1__GPR32AsmReg1_0, |
| Convert__regAC0__GPR32AsmReg1_0, |
| Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0, |
| Convert__GPR32AsmReg1_1__GPR32AsmReg1_0, |
| Convert__GPR32AsmReg1_1__GPR32AsmReg1_0__ConstantUImm1_01_2__ConstantUImm3_01_3__ConstantUImm1_01_4, |
| Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, |
| Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_0, |
| Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_1, |
| Convert__regZERO__regZERO__imm_95_0, |
| Convert__regZERO__regS0, |
| Convert__regZERO__regZERO, |
| Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__regZERO, |
| Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1, |
| Convert__GPR32AsmReg1_0__GPR32AsmReg1_0, |
| Convert__GPR32AsmReg1_3__GPR32AsmReg1_1__ConstantUImm5_01_0, |
| Convert__GPR32AsmReg1_0__ConstantUImm7_01_1, |
| Convert__GPR32AsmReg1_0__ConstantUImm10_01_1, |
| Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__imm_95_0, |
| Convert__GPR64AsmReg1_0__HWRegsAsmReg1_1__imm_95_0, |
| Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__ConstantUImm3_01_2, |
| Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__ConstantUImm8_01_2, |
| Convert__GPR32AsmReg1_0__ConstantSImm10_01_1, |
| Convert__GPR32AsmReg1_0__ConstantUImm8_01_1, |
| Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, |
| Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, |
| Convert__GPR64AsmReg1_0__GPR64AsmReg1_2, |
| Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1, |
| Convert__GPR32AsmReg1_0__Tie0_1_1__MemOffsetSimmPtr2_1, |
| Convert__GPR32AsmReg1_0__Tie0_1_1__MemOffsetSimm9_02_1, |
| Convert__GPR32AsmReg1_0__Tie0_1_1__Mem2_1, |
| Convert__GPR64AsmReg1_0__Tie0_1_1__MemOffsetSimmPtr2_1, |
| Convert__GPR64AsmReg1_0__Tie0_1_1__Mem2_1, |
| Convert__ConstantUImm20_01_0, |
| Convert__Reg1_0__Tie0_1_1, |
| Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantSImm10_01_1, |
| Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantSImm10_01_2, |
| Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm32_Coerced1_1, |
| Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm32_Coerced1_2, |
| Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_0, |
| Convert__GPR32AsmReg1_0__GPR32AsmReg1_2__GPR32AsmReg1_1, |
| Convert__ACC64DSPAsmReg1_0__ConstantSImm6_01_1__Tie0_1_1, |
| Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__Tie0_1_1, |
| Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, |
| Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, |
| Convert__UImm161_0, |
| Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__GPR32AsmReg1_3, |
| Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm4_01_3, |
| Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm1_01_3, |
| Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm3_01_3, |
| Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm2_01_3, |
| Convert__Reg1_0__Reg1_1__ConstantUImm5_01_2, |
| Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__GPR32AsmReg1_3, |
| Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_3, |
| Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm1_01_3, |
| Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_3, |
| Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm2_01_3, |
| Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__InvNum1_1, |
| Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__InvNum1_2, |
| Convert__ConstantUImm5_01_0, |
| Convert__MemOffsetSimm16_02_0, |
| Convert__imm_95_2, |
| Convert__imm_95_6, |
| Convert__imm_95_4, |
| Convert__imm_95_5, |
| Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2, |
| Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2, |
| Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2, |
| Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2, |
| Convert__GPR32AsmReg1_0__imm_95_31, |
| CVT_NUM_SIGNATURES |
| }; |
| |
| } // end anonymous namespace |
| |
| static const uint8_t ConversionTable[CVT_NUM_SIGNATURES][11] = { |
| // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1 |
| { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done }, |
| // Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1 |
| { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_Done }, |
| // Convert__FGR64AsmReg1_0__FGR64AsmReg1_1 |
| { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_Done }, |
| // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1 |
| { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done }, |
| // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1 |
| { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done }, |
| // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1 |
| { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addSImmOperands_LT_32_GT_, 2, CVT_Done }, |
| // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2 |
| { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done }, |
| // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2 |
| { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addSImmOperands_LT_32_GT_, 3, CVT_Done }, |
| // Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2 |
| { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addAFGR64AsmRegOperands, 3, CVT_Done }, |
| // Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2 |
| { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFGR64AsmRegOperands, 3, CVT_Done }, |
| // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2 |
| { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addFGR32AsmRegOperands, 3, CVT_Done }, |
| // Convert__FGR32AsmReg1_0__FGR32AsmReg1_2__FGR32AsmReg1_1 |
| { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 3, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done }, |
| // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2 |
| { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addMSA128AsmRegOperands, 3, CVT_Done }, |
| // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1 |
| { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done }, |
| // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm16_Relaxed1_1 |
| { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done }, |
| // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2 |
| { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addSImmOperands_LT_16_GT_, 3, CVT_Done }, |
| // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm16_Relaxed1_2 |
| { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addSImmOperands_LT_16_GT_, 3, CVT_Done }, |
| // Convert__SImm161_1 |
| { CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done }, |
| // Convert__Reg1_0__SImm161_1 |
| { CVT_95_Reg, 1, CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done }, |
| // Convert__Reg1_0__SImm161_2 |
| { CVT_95_Reg, 1, CVT_95_addSImmOperands_LT_16_GT_, 3, CVT_Done }, |
| // Convert__Reg1_0__Reg1_1__SImm161_2 |
| { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addSImmOperands_LT_16_GT_, 3, CVT_Done }, |
| // Convert__Reg1_0__Tie0_1_1__SImm161_1 |
| { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done }, |
| // Convert__GPR32AsmReg1_0__Simm19_Lsl21_1 |
| { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, |
| // Convert__GPRMM16AsmReg1_0__Imm1_1 |
| { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, |
| // Convert__GPRMM16AsmReg1_0__UImm6Lsl21_1 |
| { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, |
| // Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2 |
| { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addGPRMM16AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done }, |
| // Convert__GPR32AsmReg1_0__Tie0_1_1__ConstantSImm4_01_1 |
| { CVT_95_addGPR32AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addConstantSImmOperands_LT_4_44__32_0_GT_, 2, CVT_Done }, |
| // Convert__Imm1_0 |
| { CVT_95_addImmOperands, 1, CVT_Done }, |
| // Convert__Reg1_0__Reg1_1__Reg1_2 |
| { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done }, |
| // Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__GPRMM16AsmReg1_2 |
| { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addGPRMM16AsmRegOperands, 2, CVT_95_addGPRMM16AsmRegOperands, 3, CVT_Done }, |
| // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2 |
| { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done }, |
| // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_01_3 |
| { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 4, CVT_Done }, |
| // Convert__GPR32AsmReg1_0__SImm161_1 |
| { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done }, |
| // Convert__Reg1_0__Tie0_1_1__Reg1_1 |
| { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_Done }, |
| // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1 |
| { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addUImmOperands_LT_16_GT_, 2, CVT_Done }, |
| // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1 |
| { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, |
| // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2 |
| { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addUImmOperands_LT_16_GT_, 3, CVT_Done }, |
| // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2 |
| { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done }, |
| // Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0_1_1 |
| { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addGPRMM16AsmRegOperands, 2, CVT_Tied, Tie0_1_1, CVT_Done }, |
| // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2 |
| { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_, 3, CVT_Done }, |
| // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1 |
| { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Tied, Tie0_1_1, CVT_Done }, |
| // Convert__regZERO__regZERO__JumpTarget1_0 |
| { CVT_regZERO, 0, CVT_regZERO, 0, CVT_95_addImmOperands, 1, CVT_Done }, |
| // Convert__JumpTarget1_0 |
| { CVT_95_addImmOperands, 1, CVT_Done }, |
| // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1 |
| { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_Done }, |
| // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2 |
| { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 3, CVT_Done }, |
| // Convert__regZERO__JumpTarget1_0 |
| { CVT_regZERO, 0, CVT_95_addImmOperands, 1, CVT_Done }, |
| // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm2_01_2__Tie0_1_1 |
| { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 3, CVT_Tied, Tie0_1_1, CVT_Done }, |
| // Convert__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__JumpTarget1_2 |
| { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_, 2, CVT_95_addImmOperands, 3, CVT_Done }, |
| // Convert__GPR64AsmReg1_0__ConstantUImm5_0_Report_UImm61_1__JumpTarget1_2 |
| { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 2, CVT_95_addImmOperands, 3, CVT_Done }, |
| // Convert__GPR64AsmReg1_0__ConstantUImm5_01_1__JumpTarget1_2 |
| { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 2, CVT_95_addImmOperands, 3, CVT_Done }, |
| // Convert__FGR64AsmReg1_0__JumpTarget1_1 |
| { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, |
| // Convert__regFCC0__JumpTarget1_0 |
| { CVT_regFCC0, 0, CVT_95_addImmOperands, 1, CVT_Done }, |
| // Convert__FCCAsmReg1_0__JumpTarget1_1 |
| { CVT_95_addFCCAsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, |
| // Convert__COP2AsmReg1_0__JumpTarget1_1 |
| { CVT_95_addCOP2AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, |
| // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2 |
| { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done }, |
| // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2 |
| { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_, 3, CVT_Done }, |
| // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2 |
| { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 3, CVT_Done }, |
| // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2 |
| { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done }, |
| // Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2 |
| { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_Done }, |
| // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__JumpTarget1_2 |
| { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done }, |
| // Convert__Reg1_0__JumpTarget1_1 |
| { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done }, |
| // Convert__GPR32AsmReg1_0__regZERO__JumpTarget1_1 |
| { CVT_95_addGPR32AsmRegOperands, 1, CVT_regZERO, 0, CVT_95_addImmOperands, 2, CVT_Done }, |
| // Convert__GPRMM16AsmReg1_0__JumpTarget1_1 |
| { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, |
| // Convert__GPR32AsmReg1_0__JumpTarget1_1 |
| { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, |
| // Convert__GPR64AsmReg1_0__JumpTarget1_1 |
| { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, |
| // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2 |
| { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addMSA128AsmRegOperands, 3, CVT_Done }, |
| // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm3_01_2 |
| { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done }, |
| // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm6_01_2 |
| { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_, 3, CVT_Done }, |
| // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm4_01_2 |
| { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 3, CVT_Done }, |
| // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm5_01_2 |
| { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done }, |
| // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm8_01_2 |
| { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_, 3, CVT_Done }, |
| // Convert__MSA128AsmReg1_0__JumpTarget1_1 |
| { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, |
| // Convert__imm_95_0__imm_95_0 |
| { CVT_imm_95_0, 0, CVT_imm_95_0, 0, CVT_Done }, |
| // Convert_NoOperands |
| { CVT_Done }, |
| // Convert__ConstantUImm10_01_0__imm_95_0 |
| { CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 1, CVT_imm_95_0, 0, CVT_Done }, |
| // Convert__ConstantUImm10_01_0__ConstantUImm10_01_1 |
| { CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 1, CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 2, CVT_Done }, |
| // Convert__ConstantUImm4_01_0 |
| { CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 1, CVT_Done }, |
| // Convert__SImm161_0 |
| { CVT_95_addSImmOperands_LT_16_GT_, 1, CVT_Done }, |
| // Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1 |
| { CVT_regFCC0, 0, CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_Done }, |
| // Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1 |
| { CVT_regFCC0, 0, CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_Done }, |
| // Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2 |
| { CVT_95_addFCCAsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addAFGR64AsmRegOperands, 3, CVT_Done }, |
| // Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2 |
| { CVT_95_addFCCAsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFGR64AsmRegOperands, 3, CVT_Done }, |
| // Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1 |
| { CVT_regFCC0, 0, CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done }, |
| // Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2 |
| { CVT_95_addFCCAsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addFGR32AsmRegOperands, 3, CVT_Done }, |
| // Convert__MemOffsetSimm9_02_1__ConstantUImm5_01_0 |
| { CVT_95_addMemOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 1, CVT_Done }, |
| // Convert__Mem2_1__ConstantUImm5_01_0 |
| { CVT_95_addMemOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 1, CVT_Done }, |
| // Convert__FGR64AsmReg1_0__FGR32AsmReg1_1 |
| { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done }, |
| // Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1 |
| { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_Done }, |
| // Convert__FGR32AsmReg1_0__FGR64AsmReg1_1 |
| { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_Done }, |
| // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2 |
| { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantSImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done }, |
| // Convert__GPR32AsmReg1_0__CCRAsmReg1_1 |
| { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCCRAsmRegOperands, 2, CVT_Done }, |
| // Convert__GPR32AsmReg1_0__COP2AsmReg1_1 |
| { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCOP2AsmRegOperands, 2, CVT_Done }, |
| // Convert__GPR32AsmReg1_0__MSACtrlAsmReg1_1 |
| { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMSACtrlAsmRegOperands, 2, CVT_Done }, |
| // Convert__GPR32AsmReg1_0__FGR32AsmReg1_1 |
| { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done }, |
| // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1__ConstantUImm5_01_2 |
| { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done }, |
| // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__ConstantUImm5_01_2 |
| { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done }, |
| // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_01_3 |
| { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 4, CVT_Done }, |
| // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_32_Norm1_2__ConstantUImm5_01_3 |
| { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 4, CVT_Done }, |
| // Convert__Reg1_0__Reg1_1 |
| { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Done }, |
| // Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2 |
| { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFGR64AsmRegOperands, 3, CVT_Done }, |
| // Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_3 |
| { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 4, CVT_Done }, |
| // Convert__GPR64AsmReg1_0__MSA128AsmReg1_1__ConstantUImm1_01_3 |
| { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 4, CVT_Done }, |
| // Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_3 |
| { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 4, CVT_Done }, |
| // Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm2_01_3 |
| { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 4, CVT_Done }, |
| // Convert__CCRAsmReg1_1__GPR32AsmReg1_0 |
| { CVT_95_addCCRAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done }, |
| // Convert__COP2AsmReg1_1__GPR32AsmReg1_0 |
| { CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done }, |
| // Convert__MSACtrlAsmReg1_0__GPR32AsmReg1_1 |
| { CVT_95_addMSACtrlAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done }, |
| // Convert__FGR32AsmReg1_1__GPR32AsmReg1_0 |
| { CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done }, |
| // Convert__AFGR64AsmReg1_0__FGR32AsmReg1_1 |
| { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done }, |
| // Convert__FGR64AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2 |
| { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addFGR32AsmRegOperands, 3, CVT_Done }, |
| // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm161_1 |
| { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done }, |
| // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm161_2 |
| { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addSImmOperands_LT_16_GT_, 3, CVT_Done }, |
| // Convert__GPR64AsmReg1_0__Tie0_1_2__UImm16_AltRelaxed1_2 |
| { CVT_95_addGPR64AsmRegOperands, 1, CVT_Tied, Tie0_1_2, CVT_95_addSImmOperands_LT_16_GT_, 3, CVT_Done }, |
| // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm3_01_3 |
| { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 3, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 4, CVT_Done }, |
| // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__UImm161_2 |
| { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addUImmOperands_LT_16_GT_, 3, CVT_Done }, |
| // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1 |
| { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_Done }, |
| // Convert__GPR64AsmReg1_1__GPR64AsmReg1_2 |
| { CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 3, CVT_Done }, |
| // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_331_3 |
| { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_33_GT_, 4, CVT_Done }, |
| // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3 |
| { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_32_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Done }, |
| // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_0_Report_UImm61_2__ConstantUImm5_Plus1_Report_UImm61_3 |
| { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Done }, |
| // Convert__regZERO |
| { CVT_regZERO, 0, CVT_Done }, |
| // Convert__GPR32AsmReg1_0 |
| { CVT_95_addGPR32AsmRegOperands, 1, CVT_Done }, |
| // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImmRange2_641_3__Tie0_1_1 |
| { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addImmOperands, 4, CVT_Tied, Tie0_1_1, CVT_Done }, |
| // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3__Tie0_1_1 |
| { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_32_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Tied, Tie0_1_1, CVT_Done }, |
| // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2__ConstantUImm5_11_3__Tie0_1_1 |
| { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Tied, Tie0_1_1, CVT_Done }, |
| // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm321_1 |
| { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addSImmOperands_LT_32_GT_, 2, CVT_Done }, |
| // Convert__GPR32NonZeroAsmReg1_0__GPR32NonZeroAsmReg1_0__GPR32AsmReg1_1 |
| { CVT_95_addGPR32NonZeroAsmRegOperands, 1, CVT_95_addGPR32NonZeroAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done }, |
| // Convert__GPR32ZeroAsmReg1_0__GPR32AsmReg1_1 |
| { CVT_95_addGPR32ZeroAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done }, |
| // Convert__Reg1_1__Reg1_2 |
| { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done }, |
| // Convert__GPR32AsmReg1_1__GPR32AsmReg1_2 |
| { CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done }, |
| // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm321_2 |
| { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addSImmOperands_LT_32_GT_, 3, CVT_Done }, |
| // Convert__GPR32NonZeroAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2 |
| { CVT_95_addGPR32NonZeroAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done }, |
| // Convert__GPR64AsmReg1_0__Imm1_1 |
| { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, |
| // Convert__GPR64AsmReg1_0__Mem2_1 |
| { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, |
| // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm2_11_3 |
| { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 3, CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_, 4, CVT_Done }, |
| // Convert__GPR64AsmReg1_0__COP0AsmReg1_1__imm_95_0 |
| { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addCOP0AsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done }, |
| // Convert__GPR64AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2 |
| { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done }, |
| // Convert__GPR64AsmReg1_0__FGR64AsmReg1_1 |
| { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_Done }, |
| // Convert__GPR64AsmReg1_0__COP2AsmReg1_1__imm_95_0 |
| { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addCOP2AsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done }, |
| // Convert__GPR64AsmReg1_0__UImm161_1 |
| { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addUImmOperands_LT_16_GT_, 2, CVT_Done }, |
| // Convert__GPR64AsmReg1_0__COP2AsmReg1_1__ConstantUImm3_01_2 |
| { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done }, |
| // Convert__COP0AsmReg1_1__GPR64AsmReg1_0__imm_95_0 |
| { CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done }, |
| // Convert__COP0AsmReg1_1__GPR64AsmReg1_0__ConstantUImm3_01_2 |
| { CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done }, |
| // Convert__FGR64AsmReg1_1__GPR64AsmReg1_0 |
| { CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 1, CVT_Done }, |
| // Convert__COP2AsmReg1_1__GPR64AsmReg1_0__imm_95_0 |
| { CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done }, |
| // Convert__COP2AsmReg1_1__GPR64AsmReg1_0__ConstantUImm3_01_2 |
| { CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done }, |
| // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm32_Relaxed1_2 |
| { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addSImmOperands_LT_32_GT_, 3, CVT_Done }, |
| // Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_0 |
| { CVT_95_addGPR64AsmRegOperands, 1, CVT_regZERO_64, 0, CVT_95_addGPR64AsmRegOperands, 1, CVT_Done }, |
| // Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_1 |
| { CVT_95_addGPR64AsmRegOperands, 1, CVT_regZERO_64, 0, CVT_95_addGPR64AsmRegOperands, 2, CVT_Done }, |
| // Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1 |
| { CVT_95_addACC64DSPAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done }, |
| // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0 |
| { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_Done }, |
| // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm32_Relaxed1_1 |
| { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addSImmOperands_LT_32_GT_, 2, CVT_Done }, |
| // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm6_01_1 |
| { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_, 2, CVT_Done }, |
| // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2 |
| { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_, 3, CVT_Done }, |
| // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1 |
| { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 2, CVT_Done }, |
| // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2 |
| { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done }, |
| // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2 |
| { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done }, |
| // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR32AsmReg1_1 |
| { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done }, |
| // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__InvNum1_1 |
| { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, |
| // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__InvNum1_2 |
| { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done }, |
| // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3 |
| { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Done }, |
| // Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2 |
| { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addACC64DSPAsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done }, |
| // Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2 |
| { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addACC64DSPAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done }, |
| // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1 |
| { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_Done }, |
| // Convert__MSA128AsmReg1_0__GPR32AsmReg1_1 |
| { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done }, |
| // Convert__MSA128AsmReg1_0__GPR64AsmReg1_1 |
| { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_Done }, |
| // Convert__GPR32AsmReg1_1__GPR32AsmReg1_0__GPR32AsmReg1_2 |
| { CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done }, |
| // Convert__GPR32AsmReg1_0__ConstantUImm2_01_1 |
| { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 2, CVT_Done }, |
| // Convert__imm_95_0 |
| { CVT_imm_95_0, 0, CVT_Done }, |
| // Convert__ConstantUImm10_01_0 |
| { CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 1, CVT_Done }, |
| // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3__Tie0_1_1 |
| { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Tied, Tie0_1_1, CVT_Done }, |
| // Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm4_01_2 |
| { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addGPR32AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 3, CVT_Done }, |
| // Convert__MSA128AsmReg1_0__Tie0_1_1__GPR64AsmReg1_4__ConstantUImm1_01_2 |
| { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addGPR64AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 3, CVT_Done }, |
| // Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm3_01_2 |
| { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addGPR32AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done }, |
| // Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm2_01_2 |
| { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addGPR32AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 3, CVT_Done }, |
| // Convert__GPR32AsmReg1_0__Tie0_1_1__GPR32AsmReg1_1 |
| { CVT_95_addGPR32AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done }, |
| // Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm4_01_2__MSA128AsmReg1_4__ConstantImmz1_6 |
| { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 3, CVT_95_addMSA128AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_1_GT_, 7, CVT_Done }, |
| // Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm1_01_2__MSA128AsmReg1_4__ConstantImmz1_6 |
| { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 3, CVT_95_addMSA128AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_1_GT_, 7, CVT_Done }, |
| // Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm3_01_2__MSA128AsmReg1_4__ConstantImmz1_6 |
| { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_95_addMSA128AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_1_GT_, 7, CVT_Done }, |
| // Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm2_01_2__MSA128AsmReg1_4__ConstantImmz1_6 |
| { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 3, CVT_95_addMSA128AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_1_GT_, 7, CVT_Done }, |
| // Convert__regRA__GPR32AsmReg1_0 |
| { CVT_regRA, 0, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done }, |
| // Convert__regRA_64__GPR64AsmReg1_0 |
| { CVT_regRA_64, 0, CVT_95_addGPR64AsmRegOperands, 1, CVT_Done }, |
| // Convert__Reg1_0 |
| { CVT_95_Reg, 1, CVT_Done }, |
| // Convert__GPR32AsmReg1_0__imm_95_0 |
| { CVT_95_addGPR32AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done }, |
| // Convert__GPR64AsmReg1_0__imm_95_0 |
| { CVT_95_addGPR64AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done }, |
| // Convert__regZERO__GPR32AsmReg1_0 |
| { CVT_regZERO, 0, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done }, |
| // Convert__GPR64AsmReg1_0 |
| { CVT_95_addGPR64AsmRegOperands, 1, CVT_Done }, |
| // Convert__regZERO_64__GPR64AsmReg1_0 |
| { CVT_regZERO_64, 0, CVT_95_addGPR64AsmRegOperands, 1, CVT_Done }, |
| // Convert__UImm5Lsl21_0 |
| { CVT_95_addImmOperands, 1, CVT_Done }, |
| // Convert__AFGR64AsmReg1_0__MemOffsetSimm16_02_1 |
| { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, |
| // Convert__FGR64AsmReg1_0__MemOffsetSimm16_02_1 |
| { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, |
| // Convert__FGR32AsmReg1_0__MemOffsetSimm16_02_1 |
| { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, |
| // Convert__GPR32AsmReg1_0__Imm1_1 |
| { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, |
| // Convert__GPR32AsmReg1_0__Mem2_1 |
| { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, |
| // Convert__GPR32AsmReg1_0__MemOffsetSimmPtr2_1 |
| { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, |
| // Convert__GPR32AsmReg1_0__MemOffsetSimm16_02_1 |
| { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, |
| // Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1 |
| { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, |
| // Convert__GPRMM16AsmReg1_0__MicroMipsMem2_1 |
| { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addMicroMipsMemOperands, 2, CVT_Done }, |
| // Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1 |
| { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 4, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done }, |
| // Convert__GPR64AsmReg1_0__MemOffsetSimmPtr2_1 |
| { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, |
| // Convert__MSA128AsmReg1_0__MemOffsetSimm10_02_1 |
| { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, |
| // Convert__MSA128AsmReg1_0__MemOffsetSimm10_32_1 |
| { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, |
| // Convert__MSA128AsmReg1_0__MemOffsetSimm10_12_1 |
| { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, |
| // Convert__MSA128AsmReg1_0__MemOffsetSimm10_22_1 |
| { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, |
| // Convert__COP2AsmReg1_0__MemOffsetSimm11_02_1 |
| { CVT_95_addCOP2AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, |
| // Convert__COP2AsmReg1_0__MemOffsetSimm16_02_1 |
| { CVT_95_addCOP2AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, |
| // Convert__COP3AsmReg1_0__Mem2_1 |
| { CVT_95_addCOP3AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, |
| // Convert__MSA128AsmReg1_0__ConstantSImm10_01_1 |
| { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_, 2, CVT_Done }, |
| // Convert__GPR64AsmReg1_0__Mem2_1__Tie0_1_1 |
| { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Tied, Tie0_1_1, CVT_Done }, |
| // Convert__AFGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1 |
| { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 4, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done }, |
| // Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1 |
| { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 4, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done }, |
| // Convert__GPR32AsmReg1_0__UImm32_Coerced1_1 |
| { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_32_GT_, 2, CVT_Done }, |
| // Convert__StrictlyAFGR64AsmReg1_0__Imm1_1 |
| { CVT_95_addStrictlyAFGR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, |
| // Convert__StrictlyFGR64AsmReg1_0__Imm1_1 |
| { CVT_95_addStrictlyFGR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, |
| // Convert__StrictlyFGR32AsmReg1_0__Imm1_1 |
| { CVT_95_addStrictlyFGR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, |
| // Convert__GPRMM16AsmReg1_0__UImm7_N11_1 |
| { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_7_44__32__MINUS_1_GT_, 2, CVT_Done }, |
| // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_11_3 |
| { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_, 4, CVT_Done }, |
| // Convert__GPR32AsmReg1_2__GPR32AsmReg1_1__GPR32AsmReg1_0__ConstantUImm2_11_3 |
| { CVT_95_addGPR32AsmRegOperands, 3, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_, 4, CVT_Done }, |
| // Convert__GPR32AsmReg1_0__UImm161_1 |
| { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addUImmOperands_LT_16_GT_, 2, CVT_Done }, |
| // Convert__GPR32AsmReg1_0__UImm16_Relaxed1_1 |
| { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addUImmOperands_LT_16_GT_, 2, CVT_Done }, |
| // Convert__Reg1_0__Imm1_1__imm_95_0 |
| { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_imm_95_0, 0, CVT_Done }, |
| // Convert__GPR32AsmReg1_0__MicroMipsMemSP2_1 |
| { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, |
| // Convert__GPRMM16AsmReg1_0__MicroMipsMemGP2_1 |
| { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, |
| // Convert__GPR32AsmReg1_0__Mem2_1__Tie0_1_1 |
| { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Tied, Tie0_1_1, CVT_Done }, |
| // Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1__Tie0_1_1 |
| { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Tied, Tie0_1_1, CVT_Done }, |
| // Convert__RegList1_0__Mem2_1 |
| { CVT_95_addRegListOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, |
| // Convert__RegList161_0__MemOffsetUimm42_1 |
| { CVT_95_addRegListOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, |
| // ConvertCustom_ConvertXWPOperands |
| { CVT_ConvertXWPOperands, 0, CVT_Done }, |
| // Convert__GPR32AsmReg1_0__MemOffsetSimm12_02_1 |
| { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, |
| // Convert__FGR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1 |
| { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 4, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done }, |
| // Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3 |
| { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addAFGR64AsmRegOperands, 3, CVT_95_addAFGR64AsmRegOperands, 4, CVT_Done }, |
| // Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2__FGR64AsmReg1_3 |
| { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFGR64AsmRegOperands, 3, CVT_95_addFGR64AsmRegOperands, 4, CVT_Done }, |
| // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3 |
| { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addFGR32AsmRegOperands, 3, CVT_95_addFGR32AsmRegOperands, 4, CVT_Done }, |
| // Convert__FGR64AsmReg1_0__Tie0_1_1__FGR64AsmReg1_1__FGR64AsmReg1_2 |
| { CVT_95_addFGR64AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFGR64AsmRegOperands, 3, CVT_Done }, |
| // Convert__FGR32AsmReg1_0__Tie0_1_1__FGR32AsmReg1_1__FGR32AsmReg1_2 |
| { CVT_95_addFGR32AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addFGR32AsmRegOperands, 3, CVT_Done }, |
| // Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0 |
| { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCOP0AsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done }, |
| // Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2 |
| { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done }, |
| // Convert__GPR32AsmReg1_0__FGR64AsmReg1_1 |
| { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_Done }, |
| // Convert__GPR32AsmReg1_0__COP2AsmReg1_1__imm_95_0 |
| { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCOP2AsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done }, |
| // Convert__GPR32AsmReg1_0__COP2AsmReg1_1__ConstantUImm3_01_2 |
| { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done }, |
| // Convert__GPR32AsmReg1_0__AFGR64AsmReg1_1 |
| { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_Done }, |
| // Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1 |
| { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addACC64DSPAsmRegOperands, 2, CVT_Done }, |
| // Convert__GPR32AsmReg1_0__regAC0 |
| { CVT_95_addGPR32AsmRegOperands, 1, CVT_regAC0, 0, CVT_Done }, |
| // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0 |
| { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done }, |
| // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm1_01_2__ConstantUImm3_01_3__ConstantUImm1_01_4 |
| { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 4, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 5, CVT_Done }, |
| // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__regZERO |
| { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_regZERO, 0, CVT_Done }, |
| // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__regZERO_64 |
| { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_regZERO_64, 0, CVT_Done }, |
| // Convert__GPRMM16AsmRegMovePPairFirst1_0__GPRMM16AsmRegMovePPairSecond1_1__GPRMM16AsmRegMoveP1_2__GPRMM16AsmRegMoveP1_3 |
| { CVT_95_addGPRMM16AsmRegMovePPairFirstOperands, 1, CVT_95_addGPRMM16AsmRegMovePPairSecondOperands, 2, CVT_95_addGPRMM16AsmRegMovePOperands, 3, CVT_95_addGPRMM16AsmRegMovePOperands, 4, CVT_Done }, |
| // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1 |
| { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addFCCAsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done }, |
| // Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1 |
| { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addFCCAsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done }, |
| // Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1 |
| { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFCCAsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done }, |
| // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1 |
| { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addFCCAsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done }, |
| // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1 |
| { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done }, |
| // Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1 |
| { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done }, |
| // Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1 |
| { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done }, |
| // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1 |
| { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done }, |
| // Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0 |
| { CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done }, |
| // Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2 |
| { CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done }, |
| // Convert__FGR64AsmReg1_1__GPR32AsmReg1_0 |
| { CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done }, |
| // Convert__COP2AsmReg1_1__GPR32AsmReg1_0__imm_95_0 |
| { CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done }, |
| // Convert__COP2AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2 |
| { CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done }, |
| // Convert__AFGR64AsmReg1_1__Tie0_1_1__GPR32AsmReg1_0 |
| { CVT_95_addAFGR64AsmRegOperands, 2, CVT_Tied, Tie0_1_1, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done }, |
| // Convert__FGR64AsmReg1_1__Tie0_1_1__GPR32AsmReg1_0 |
| { CVT_95_addFGR64AsmRegOperands, 2, CVT_Tied, Tie0_1_1, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done }, |
| // Convert__HI32DSPAsmReg1_1__GPR32AsmReg1_0 |
| { CVT_95_addHI32DSPAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done }, |
| // Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0__Tie0_1_1 |
| { CVT_95_addACC64DSPAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_Done }, |
| // Convert__LO32DSPAsmReg1_1__GPR32AsmReg1_0 |
| { CVT_95_addLO32DSPAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done }, |
| // Convert__regAC0__GPR32AsmReg1_0 |
| { CVT_regAC0, 0, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done }, |
| // Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0 |
| { CVT_95_addACC64DSPAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done }, |
| // Convert__GPR32AsmReg1_1__GPR32AsmReg1_0 |
| { CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done }, |
| // Convert__GPR32AsmReg1_1__GPR32AsmReg1_0__ConstantUImm1_01_2__ConstantUImm3_01_3__ConstantUImm1_01_4 |
| { CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 4, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 5, CVT_Done }, |
| // Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2 |
| { CVT_95_addACC64DSPAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done }, |
| // Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_0 |
| { CVT_95_addGPR32AsmRegOperands, 1, CVT_regZERO, 0, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done }, |
| // Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_1 |
| { CVT_95_addGPR32AsmRegOperands, 1, CVT_regZERO, 0, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done }, |
| // Convert__regZERO__regZERO__imm_95_0 |
| { CVT_regZERO, 0, CVT_regZERO, 0, CVT_imm_95_0, 0, CVT_Done }, |
| // Convert__regZERO__regS0 |
| { CVT_regZERO, 0, CVT_regS0, 0, CVT_Done }, |
| // Convert__regZERO__regZERO |
| { CVT_regZERO, 0, CVT_regZERO, 0, CVT_Done }, |
| // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__regZERO |
| { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_regZERO, 0, CVT_Done }, |
| // Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1 |
| { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addGPRMM16AsmRegOperands, 2, CVT_Done }, |
| // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0 |
| { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done }, |
| // Convert__GPR32AsmReg1_3__GPR32AsmReg1_1__ConstantUImm5_01_0 |
| { CVT_95_addGPR32AsmRegOperands, 4, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 1, CVT_Done }, |
| // Convert__GPR32AsmReg1_0__ConstantUImm7_01_1 |
| { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_7_44__32_0_GT_, 2, CVT_Done }, |
| // Convert__GPR32AsmReg1_0__ConstantUImm10_01_1 |
| { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 2, CVT_Done }, |
| // Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__imm_95_0 |
| { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addHWRegsAsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done }, |
| // Convert__GPR64AsmReg1_0__HWRegsAsmReg1_1__imm_95_0 |
| { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addHWRegsAsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done }, |
| // Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__ConstantUImm3_01_2 |
| { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addHWRegsAsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done }, |
| // Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__ConstantUImm8_01_2 |
| { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addHWRegsAsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_, 3, CVT_Done }, |
| // Convert__GPR32AsmReg1_0__ConstantSImm10_01_1 |
| { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_, 2, CVT_Done }, |
| // Convert__GPR32AsmReg1_0__ConstantUImm8_01_1 |
| { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_, 2, CVT_Done }, |
| // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1 |
| { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 2, CVT_Done }, |
| // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2 |
| { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done }, |
| // Convert__GPR64AsmReg1_0__GPR64AsmReg1_2 |
| { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 3, CVT_Done }, |
| // Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1 |
| { CVT_95_addGPRMM16AsmRegZeroOperands, 1, CVT_95_addMicroMipsMemOperands, 2, CVT_Done }, |
| // Convert__GPR32AsmReg1_0__Tie0_1_1__MemOffsetSimmPtr2_1 |
| { CVT_95_addGPR32AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_Done }, |
| // Convert__GPR32AsmReg1_0__Tie0_1_1__MemOffsetSimm9_02_1 |
| { CVT_95_addGPR32AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_Done }, |
| // Convert__GPR32AsmReg1_0__Tie0_1_1__Mem2_1 |
| { CVT_95_addGPR32AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_Done }, |
| // Convert__GPR64AsmReg1_0__Tie0_1_1__MemOffsetSimmPtr2_1 |
| { CVT_95_addGPR64AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_Done }, |
| // Convert__GPR64AsmReg1_0__Tie0_1_1__Mem2_1 |
| { CVT_95_addGPR64AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_Done }, |
| // Convert__ConstantUImm20_01_0 |
| { CVT_95_addConstantUImmOperands_LT_20_44__32_0_GT_, 1, CVT_Done }, |
| // Convert__Reg1_0__Tie0_1_1 |
| { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_Done }, |
| // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantSImm10_01_1 |
| { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_, 2, CVT_Done }, |
| // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantSImm10_01_2 |
| { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_, 3, CVT_Done }, |
| // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm32_Coerced1_1 |
| { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_32_GT_, 2, CVT_Done }, |
| // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm32_Coerced1_2 |
| { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_32_GT_, 3, CVT_Done }, |
| // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_0 |
| { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done }, |
| // Convert__GPR32AsmReg1_0__GPR32AsmReg1_2__GPR32AsmReg1_1 |
| { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 3, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done }, |
| // Convert__ACC64DSPAsmReg1_0__ConstantSImm6_01_1__Tie0_1_1 |
| { CVT_95_addACC64DSPAsmRegOperands, 1, CVT_95_addConstantSImmOperands_LT_6_44__32_0_GT_, 2, CVT_Tied, Tie0_1_1, CVT_Done }, |
| // Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__Tie0_1_1 |
| { CVT_95_addACC64DSPAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Tied, Tie0_1_1, CVT_Done }, |
| // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2 |
| { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 3, CVT_Done }, |
| // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2 |
| { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done }, |
| // Convert__UImm161_0 |
| { CVT_95_addUImmOperands_LT_16_GT_, 1, CVT_Done }, |
| // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__GPR32AsmReg1_3 |
| { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 4, CVT_Done }, |
| // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm4_01_3 |
| { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 4, CVT_Done }, |
| // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm1_01_3 |
| { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 4, CVT_Done }, |
| // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm3_01_3 |
| { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 4, CVT_Done }, |
| // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm2_01_3 |
| { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 4, CVT_Done }, |
| // Convert__Reg1_0__Reg1_1__ConstantUImm5_01_2 |
| { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done }, |
| // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__GPR32AsmReg1_3 |
| { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 4, CVT_Done }, |
| // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_3 |
| { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 4, CVT_Done }, |
| // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm1_01_3 |
| { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 4, CVT_Done }, |
| // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_3 |
| { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 4, CVT_Done }, |
| // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm2_01_3 |
| { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 4, CVT_Done }, |
| // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__InvNum1_1 |
| { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, |
| // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__InvNum1_2 |
| { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done }, |
| // Convert__ConstantUImm5_01_0 |
| { CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 1, CVT_Done }, |
| // Convert__MemOffsetSimm16_02_0 |
| { CVT_95_addMemOperands, 1, CVT_Done }, |
| // Convert__imm_95_2 |
| { CVT_imm_95_2, 0, CVT_Done }, |
| // Convert__imm_95_6 |
| { CVT_imm_95_6, 0, CVT_Done }, |
| // Convert__imm_95_4 |
| { CVT_imm_95_4, 0, CVT_Done }, |
| // Convert__imm_95_5 |
| { CVT_imm_95_5, 0, CVT_Done }, |
| // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2 |
| { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 3, CVT_Done }, |
| // Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2 |
| { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done }, |
| // Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2 |
| { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done }, |
| // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2 |
| { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done }, |
| // Convert__GPR32AsmReg1_0__imm_95_31 |
| { CVT_95_addGPR32AsmRegOperands, 1, CVT_imm_95_31, 0, CVT_Done }, |
| }; |
| |
| void MipsAsmParser:: |
| convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode, |
| const OperandVector &Operands) { |
| assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!"); |
| const uint8_t *Converter = ConversionTable[Kind]; |
| unsigned OpIdx; |
| Inst.setOpcode(Opcode); |
| for (const uint8_t *p = Converter; *p; p += 2) { |
| OpIdx = *(p + 1); |
| switch (*p) { |
| default: llvm_unreachable("invalid conversion entry!"); |
| case CVT_Reg: |
| static_cast<MipsOperand &>(*Operands[OpIdx]).addRegOperands(Inst, 1); |
| break; |
| case CVT_Tied: { |
| assert(OpIdx < (size_t)(std::end(TiedAsmOperandTable) - |
| std::begin(TiedAsmOperandTable)) && |
| "Tied operand not found"); |
| unsigned TiedResOpnd = TiedAsmOperandTable[OpIdx][0]; |
| if (TiedResOpnd != (uint8_t)-1) |
| Inst.addOperand(Inst.getOperand(TiedResOpnd)); |
| break; |
| } |
| case CVT_95_addGPR32AsmRegOperands: |
| static_cast<MipsOperand &>(*Operands[OpIdx]).addGPR32AsmRegOperands(Inst, 1); |
| break; |
| case CVT_95_addAFGR64AsmRegOperands: |
| static_cast<MipsOperand &>(*Operands[OpIdx]).addAFGR64AsmRegOperands(Inst, 1); |
| break; |
| case CVT_95_addFGR64AsmRegOperands: |
| static_cast<MipsOperand &>(*Operands[OpIdx]).addFGR64AsmRegOperands(Inst, 1); |
| break; |
| case CVT_95_addFGR32AsmRegOperands: |
| static_cast<MipsOperand &>(*Operands[OpIdx]).addFGR32AsmRegOperands(Inst, 1); |
| break; |
| case CVT_95_addSImmOperands_LT_32_GT_: |
| static_cast<MipsOperand &>(*Operands[OpIdx]).addSImmOperands<32>(Inst, 1); |
| break; |
| case CVT_95_addMSA128AsmRegOperands: |
| static_cast<MipsOperand &>(*Operands[OpIdx]).addMSA128AsmRegOperands(Inst, 1); |
| break; |
| case CVT_95_addSImmOperands_LT_16_GT_: |
| static_cast<MipsOperand &>(*Operands[OpIdx]).addSImmOperands<16>(Inst, 1); |
| break; |
| case CVT_95_Reg: |
| static_cast<MipsOperand &>(*Operands[OpIdx]).addRegOperands(Inst, 1); |
| break; |
| case CVT_95_addImmOperands: |
| static_cast<MipsOperand &>(*Operands[OpIdx]).addImmOperands(Inst, 1); |
| break; |
| case CVT_95_addGPRMM16AsmRegOperands: |
| static_cast<MipsOperand &>(*Operands[OpIdx]).addGPRMM16AsmRegOperands(Inst, 1); |
| break; |
| case CVT_95_addConstantSImmOperands_LT_4_44__32_0_GT_: |
| static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantSImmOperands<4, 0>(Inst, 1); |
| break; |
| case CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_: |
| static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantUImmOperands<5, 0>(Inst, 1); |
| break; |
| case CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_: |
| static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantUImmOperands<2, 0>(Inst, 1); |
| break; |
| case CVT_95_addUImmOperands_LT_16_GT_: |
| static_cast<MipsOperand &>(*Operands[OpIdx]).addUImmOperands<16>(Inst, 1); |
| break; |
| case CVT_95_addGPR64AsmRegOperands: |
| static_cast<MipsOperand &>(*Operands[OpIdx]).addGPR64AsmRegOperands(Inst, 1); |
| break; |
| case CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_: |
| static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantUImmOperands<8, 0>(Inst, 1); |
| break; |
| case CVT_regZERO: |
| Inst.addOperand(MCOperand::createReg(Mips::ZERO)); |
| break; |
| case CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_: |
| static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantUImmOperands<5, 32, -32>(Inst, 1); |
| break; |
| case CVT_regFCC0: |
| Inst.addOperand(MCOperand::createReg(Mips::FCC0)); |
| break; |
| case CVT_95_addFCCAsmRegOperands: |
| static_cast<MipsOperand &>(*Operands[OpIdx]).addFCCAsmRegOperands(Inst, 1); |
| break; |
| case CVT_95_addCOP2AsmRegOperands: |
| static_cast<MipsOperand &>(*Operands[OpIdx]).addCOP2AsmRegOperands(Inst, 1); |
| break; |
| case CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_: |
| static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantUImmOperands<3, 0>(Inst, 1); |
| break; |
| case CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_: |
| static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantUImmOperands<6, 0>(Inst, 1); |
| break; |
| case CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_: |
| static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantUImmOperands<4, 0>(Inst, 1); |
| break; |
| case CVT_imm_95_0: |
| Inst.addOperand(MCOperand::createImm(0)); |
| break; |
| case CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_: |
| static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantUImmOperands<10, 0>(Inst, 1); |
| break; |
| case CVT_95_addMemOperands: |
| static_cast<MipsOperand &>(*Operands[OpIdx]).addMemOperands(Inst, 2); |
| break; |
| case CVT_95_addConstantSImmOperands_LT_5_44__32_0_GT_: |
| static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantSImmOperands<5, 0>(Inst, 1); |
| break; |
| case CVT_95_addCCRAsmRegOperands: |
| static_cast<MipsOperand &>(*Operands[OpIdx]).addCCRAsmRegOperands(Inst, 1); |
| break; |
| case CVT_95_addMSACtrlAsmRegOperands: |
| static_cast<MipsOperand &>(*Operands[OpIdx]).addMSACtrlAsmRegOperands(Inst, 1); |
| break; |
| case CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_: |
| static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantUImmOperands<1, 0>(Inst, 1); |
| break; |
| case CVT_95_addConstantUImmOperands_LT_5_44__32_33_GT_: |
| static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantUImmOperands<5, 33>(Inst, 1); |
| break; |
| case CVT_95_addConstantUImmOperands_LT_5_44__32_32_GT_: |
| static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantUImmOperands<5, 32>(Inst, 1); |
| break; |
| case CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_: |
| static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantUImmOperands<5, 1>(Inst, 1); |
| break; |
| case CVT_95_addGPR32NonZeroAsmRegOperands: |
| static_cast<MipsOperand &>(*Operands[OpIdx]).addGPR32NonZeroAsmRegOperands(Inst, 1); |
| break; |
| case CVT_95_addGPR32ZeroAsmRegOperands: |
| static_cast<MipsOperand &>(*Operands[OpIdx]).addGPR32ZeroAsmRegOperands(Inst, 1); |
| break; |
| case CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_: |
| static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantUImmOperands<2, 1>(Inst, 1); |
| break; |
| case CVT_95_addCOP0AsmRegOperands: |
| static_cast<MipsOperand &>(*Operands[OpIdx]).addCOP0AsmRegOperands(Inst, 1); |
| break; |
| case CVT_regZERO_64: |
| Inst.addOperand(MCOperand::createReg(Mips::ZERO_64)); |
| break; |
| case CVT_95_addACC64DSPAsmRegOperands: |
| static_cast<MipsOperand &>(*Operands[OpIdx]).addACC64DSPAsmRegOperands(Inst, 1); |
| break; |
| case CVT_95_addConstantUImmOperands_LT_1_GT_: |
| static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantUImmOperands<1>(Inst, 1); |
| break; |
| case CVT_regRA: |
| Inst.addOperand(MCOperand::createReg(Mips::RA)); |
| break; |
| case CVT_regRA_64: |
| Inst.addOperand(MCOperand::createReg(Mips::RA_64)); |
| break; |
| case CVT_95_addMicroMipsMemOperands: |
| static_cast<MipsOperand &>(*Operands[OpIdx]).addMicroMipsMemOperands(Inst, 2); |
| break; |
| case CVT_95_addCOP3AsmRegOperands: |
| static_cast<MipsOperand &>(*Operands[OpIdx]).addCOP3AsmRegOperands(Inst, 1); |
| break; |
| case CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_: |
| static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantSImmOperands<10, 0>(Inst, 1); |
| break; |
| case CVT_95_addConstantUImmOperands_LT_32_GT_: |
| static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantUImmOperands<32>(Inst, 1); |
| break; |
| case CVT_95_addStrictlyAFGR64AsmRegOperands: |
| static_cast<MipsOperand &>(*Operands[OpIdx]).addStrictlyAFGR64AsmRegOperands(Inst, 1); |
| break; |
| case CVT_95_addStrictlyFGR64AsmRegOperands: |
| static_cast<MipsOperand &>(*Operands[OpIdx]).addStrictlyFGR64AsmRegOperands(Inst, 1); |
| break; |
| case CVT_95_addStrictlyFGR32AsmRegOperands: |
| static_cast<MipsOperand &>(*Operands[OpIdx]).addStrictlyFGR32AsmRegOperands(Inst, 1); |
| break; |
| case CVT_95_addConstantUImmOperands_LT_7_44__32__MINUS_1_GT_: |
| static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantUImmOperands<7, -1>(Inst, 1); |
| break; |
| case CVT_95_addRegListOperands: |
| static_cast<MipsOperand &>(*Operands[OpIdx]).addRegListOperands(Inst, 1); |
| break; |
| case CVT_ConvertXWPOperands: |
| ConvertXWPOperands(Inst, Operands); |
| break; |
| case CVT_regAC0: |
| Inst.addOperand(MCOperand::createReg(Mips::AC0)); |
| break; |
| case CVT_95_addGPRMM16AsmRegMovePPairFirstOperands: |
| static_cast<MipsOperand &>(*Operands[OpIdx]).addGPRMM16AsmRegMovePPairFirstOperands(Inst, 1); |
| break; |
| case CVT_95_addGPRMM16AsmRegMovePPairSecondOperands: |
| static_cast<MipsOperand &>(*Operands[OpIdx]).addGPRMM16AsmRegMovePPairSecondOperands(Inst, 1); |
| break; |
| case CVT_95_addGPRMM16AsmRegMovePOperands: |
| static_cast<MipsOperand &>(*Operands[OpIdx]).addGPRMM16AsmRegMovePOperands(Inst, 1); |
| break; |
| case CVT_95_addHI32DSPAsmRegOperands: |
| static_cast<MipsOperand &>(*Operands[OpIdx]).addHI32DSPAsmRegOperands(Inst, 1); |
| break; |
| case CVT_95_addLO32DSPAsmRegOperands: |
| static_cast<MipsOperand &>(*Operands[OpIdx]).addLO32DSPAsmRegOperands(Inst, 1); |
| break; |
| case CVT_regS0: |
| Inst.addOperand(MCOperand::createReg(Mips::S0)); |
| break; |
| case CVT_95_addConstantUImmOperands_LT_7_44__32_0_GT_: |
| static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantUImmOperands<7, 0>(Inst, 1); |
| break; |
| case CVT_95_addHWRegsAsmRegOperands: |
| static_cast<MipsOperand &>(*Operands[OpIdx]).addHWRegsAsmRegOperands(Inst, 1); |
| break; |
| case CVT_95_addGPRMM16AsmRegZeroOperands: |
| static_cast<MipsOperand &>(*Operands[OpIdx]).addGPRMM16AsmRegZeroOperands(Inst, 1); |
| break; |
| case CVT_95_addConstantUImmOperands_LT_20_44__32_0_GT_: |
| static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantUImmOperands<20, 0>(Inst, 1); |
| break; |
| case CVT_95_addConstantSImmOperands_LT_6_44__32_0_GT_: |
| static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantSImmOperands<6, 0>(Inst, 1); |
| break; |
| case CVT_imm_95_2: |
| Inst.addOperand(MCOperand::createImm(2)); |
| break; |
| case CVT_imm_95_6: |
| Inst.addOperand(MCOperand::createImm(6)); |
| break; |
| case CVT_imm_95_4: |
| Inst.addOperand(MCOperand::createImm(4)); |
| break; |
| case CVT_imm_95_5: |
| Inst.addOperand(MCOperand::createImm(5)); |
| break; |
| case CVT_imm_95_31: |
| Inst.addOperand(MCOperand::createImm(31)); |
| break; |
| } |
| } |
| } |
| |
| void MipsAsmParser:: |
| convertToMapAndConstraints(unsigned Kind, |
| const OperandVector &Operands) { |
| assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!"); |
| unsigned NumMCOperands = 0; |
| const uint8_t *Converter = ConversionTable[Kind]; |
| for (const uint8_t *p = Converter; *p; p += 2) { |
| switch (*p) { |
| default: llvm_unreachable("invalid conversion entry!"); |
| case CVT_Reg: |
| Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| Operands[*(p + 1)]->setConstraint("r"); |
| ++NumMCOperands; |
| break; |
| case CVT_Tied: |
| ++NumMCOperands; |
| break; |
| case CVT_95_addGPR32AsmRegOperands: |
| Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| Operands[*(p + 1)]->setConstraint("m"); |
| NumMCOperands += 1; |
| break; |
| case CVT_95_addAFGR64AsmRegOperands: |
| Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| Operands[*(p + 1)]->setConstraint("m"); |
| NumMCOperands += 1; |
| break; |
| case CVT_95_addFGR64AsmRegOperands: |
| Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| Operands[*(p + 1)]->setConstraint("m"); |
| NumMCOperands += 1; |
| break; |
| case CVT_95_addFGR32AsmRegOperands: |
| Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| Operands[*(p + 1)]->setConstraint("m"); |
| NumMCOperands += 1; |
| break; |
| case CVT_95_addSImmOperands_LT_32_GT_: |
| Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| Operands[*(p + 1)]->setConstraint("m"); |
| NumMCOperands += 1; |
| break; |
| case CVT_95_addMSA128AsmRegOperands: |
| Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| Operands[*(p + 1)]->setConstraint("m"); |
| NumMCOperands += 1; |
| break; |
| case CVT_95_addSImmOperands_LT_16_GT_: |
| Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| Operands[*(p + 1)]->setConstraint("m"); |
| NumMCOperands += 1; |
| break; |
| case CVT_95_Reg: |
| Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| Operands[*(p + 1)]->setConstraint("r"); |
| NumMCOperands += 1; |
| break; |
| case CVT_95_addImmOperands: |
| Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| Operands[*(p + 1)]->setConstraint("m"); |
| NumMCOperands += 1; |
| break; |
| case CVT_95_addGPRMM16AsmRegOperands: |
| Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| Operands[*(p + 1)]->setConstraint("m"); |
| NumMCOperands += 1; |
| break; |
| case CVT_95_addConstantSImmOperands_LT_4_44__32_0_GT_: |
| Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| Operands[*(p + 1)]->setConstraint("m"); |
| NumMCOperands += 1; |
| break; |
| case CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_: |
| Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| Operands[*(p + 1)]->setConstraint("m"); |
| NumMCOperands += 1; |
| break; |
| case CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_: |
| Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| Operands[*(p + 1)]->setConstraint("m"); |
| NumMCOperands += 1; |
| break; |
| case CVT_95_addUImmOperands_LT_16_GT_: |
| Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| Operands[*(p + 1)]->setConstraint("m"); |
| NumMCOperands += 1; |
| break; |
| case CVT_95_addGPR64AsmRegOperands: |
| Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| Operands[*(p + 1)]->setConstraint("m"); |
| NumMCOperands += 1; |
| break; |
| case CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_: |
| Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| Operands[*(p + 1)]->setConstraint("m"); |
| NumMCOperands += 1; |
| break; |
| case CVT_regZERO: |
| Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| Operands[*(p + 1)]->setConstraint("m"); |
| ++NumMCOperands; |
| break; |
| case CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_: |
| Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| Operands[*(p + 1)]->setConstraint("m"); |
| NumMCOperands += 1; |
| break; |
| case CVT_regFCC0: |
| Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| Operands[*(p + 1)]->setConstraint("m"); |
| ++NumMCOperands; |
| break; |
| case CVT_95_addFCCAsmRegOperands: |
| Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| Operands[*(p + 1)]->setConstraint("m"); |
| NumMCOperands += 1; |
| break; |
| case CVT_95_addCOP2AsmRegOperands: |
| Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| Operands[*(p + 1)]->setConstraint("m"); |
| NumMCOperands += 1; |
| break; |
| case CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_: |
| Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| Operands[*(p + 1)]->setConstraint("m"); |
| NumMCOperands += 1; |
| break; |
| case CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_: |
| Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| Operands[*(p + 1)]->setConstraint("m"); |
| NumMCOperands += 1; |
| break; |
| case CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_: |
| Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| Operands[*(p + 1)]->setConstraint("m"); |
| NumMCOperands += 1; |
| break; |
| case CVT_imm_95_0: |
| Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| Operands[*(p + 1)]->setConstraint(""); |
| ++NumMCOperands; |
| break; |
| case CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_: |
| Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| Operands[*(p + 1)]->setConstraint("m"); |
| NumMCOperands += 1; |
| break; |
| case CVT_95_addMemOperands: |
| Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| Operands[*(p + 1)]->setConstraint("m"); |
| NumMCOperands += 2; |
| break; |
| case CVT_95_addConstantSImmOperands_LT_5_44__32_0_GT_: |
| Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| Operands[*(p + 1)]->setConstraint("m"); |
| NumMCOperands += 1; |
| break; |
| case CVT_95_addCCRAsmRegOperands: |
| Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| Operands[*(p + 1)]->setConstraint("m"); |
| NumMCOperands += 1; |
| break; |
| case CVT_95_addMSACtrlAsmRegOperands: |
| Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| Operands[*(p + 1)]->setConstraint("m"); |
| NumMCOperands += 1; |
| break; |
| case CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_: |
| Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| Operands[*(p + 1)]->setConstraint("m"); |
| NumMCOperands += 1; |
| break; |
| case CVT_95_addConstantUImmOperands_LT_5_44__32_33_GT_: |
| Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| Operands[*(p + 1)]->setConstraint("m"); |
| NumMCOperands += 1; |
| break; |
| case CVT_95_addConstantUImmOperands_LT_5_44__32_32_GT_: |
| Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| Operands[*(p + 1)]->setConstraint("m"); |
| NumMCOperands += 1; |
| break; |
| case CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_: |
| Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| Operands[*(p + 1)]->setConstraint("m"); |
| NumMCOperands += 1; |
| break; |
| case CVT_95_addGPR32NonZeroAsmRegOperands: |
| Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| Operands[*(p + 1)]->setConstraint("m"); |
| NumMCOperands += 1; |
| break; |
| case CVT_95_addGPR32ZeroAsmRegOperands: |
| Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| Operands[*(p + 1)]->setConstraint("m"); |
| NumMCOperands += 1; |
| break; |
| case CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_: |
| Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| Operands[*(p + 1)]->setConstraint("m"); |
| NumMCOperands += 1; |
| break; |
| case CVT_95_addCOP0AsmRegOperands: |
| Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| Operands[*(p + 1)]->setConstraint("m"); |
| NumMCOperands += 1; |
| break; |
| case CVT_regZERO_64: |
| Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| Operands[*(p + 1)]->setConstraint("m"); |
| ++NumMCOperands; |
| break; |
| case CVT_95_addACC64DSPAsmRegOperands: |
| Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| Operands[*(p + 1)]->setConstraint("m"); |
| NumMCOperands += 1; |
| break; |
| case CVT_95_addConstantUImmOperands_LT_1_GT_: |
| Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| Operands[*(p + 1)]->setConstraint("m"); |
| NumMCOperands += 1; |
| break; |
| case CVT_regRA: |
| Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| Operands[*(p + 1)]->setConstraint("m"); |
| ++NumMCOperands; |
| break; |
| case CVT_regRA_64: |
| Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| Operands[*(p + 1)]->setConstraint("m"); |
| ++NumMCOperands; |
| break; |
| case CVT_95_addMicroMipsMemOperands: |
| Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| Operands[*(p + 1)]->setConstraint("m"); |
| NumMCOperands += 2; |
| break; |
| case CVT_95_addCOP3AsmRegOperands: |
| Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| Operands[*(p + 1)]->setConstraint("m"); |
| NumMCOperands += 1; |
| break; |
| case CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_: |
| Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| Operands[*(p + 1)]->setConstraint("m"); |
| NumMCOperands += 1; |
| break; |
| case CVT_95_addConstantUImmOperands_LT_32_GT_: |
| Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| Operands[*(p + 1)]->setConstraint("m"); |
| NumMCOperands += 1; |
| break; |
| case CVT_95_addStrictlyAFGR64AsmRegOperands: |
| Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| Operands[*(p + 1)]->setConstraint("m"); |
| NumMCOperands += 1; |
| break; |
| case CVT_95_addStrictlyFGR64AsmRegOperands: |
| Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| Operands[*(p + 1)]->setConstraint("m"); |
| NumMCOperands += 1; |
| break; |
| case CVT_95_addStrictlyFGR32AsmRegOperands: |
| Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| Operands[*(p + 1)]->setConstraint("m"); |
| NumMCOperands += 1; |
| break; |
| case CVT_95_addConstantUImmOperands_LT_7_44__32__MINUS_1_GT_: |
| Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| Operands[*(p + 1)]->setConstraint("m"); |
| NumMCOperands += 1; |
| break; |
| case CVT_95_addRegListOperands: |
| Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| Operands[*(p + 1)]->setConstraint("m"); |
| NumMCOperands += 1; |
| break; |
| case CVT_regAC0: |
| Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| Operands[*(p + 1)]->setConstraint("m"); |
| ++NumMCOperands; |
| break; |
| case CVT_95_addGPRMM16AsmRegMovePPairFirstOperands: |
| Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| Operands[*(p + 1)]->setConstraint("m"); |
| NumMCOperands += 1; |
| break; |
| case CVT_95_addGPRMM16AsmRegMovePPairSecondOperands: |
| Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| Operands[*(p + 1)]->setConstraint("m"); |
| NumMCOperands += 1; |
| break; |
| case CVT_95_addGPRMM16AsmRegMovePOperands: |
| Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| Operands[*(p + 1)]->setConstraint("m"); |
| NumMCOperands += 1; |
| break; |
| case CVT_95_addHI32DSPAsmRegOperands: |
| Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| Operands[*(p + 1)]->setConstraint("m"); |
| NumMCOperands += 1; |
| break; |
| case CVT_95_addLO32DSPAsmRegOperands: |
| Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| Operands[*(p + 1)]->setConstraint("m"); |
| NumMCOperands += 1; |
| break; |
| case CVT_regS0: |
| Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| Operands[*(p + 1)]->setConstraint("m"); |
| ++NumMCOperands; |
| break; |
| case CVT_95_addConstantUImmOperands_LT_7_44__32_0_GT_: |
| Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| Operands[*(p + 1)]->setConstraint("m"); |
| NumMCOperands += 1; |
| break; |
| case CVT_95_addHWRegsAsmRegOperands: |
| Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| Operands[*(p + 1)]->setConstraint("m"); |
| NumMCOperands += 1; |
| break; |
| case CVT_95_addGPRMM16AsmRegZeroOperands: |
| Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| Operands[*(p + 1)]->setConstraint("m"); |
| NumMCOperands += 1; |
| break; |
| case CVT_95_addConstantUImmOperands_LT_20_44__32_0_GT_: |
| Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| Operands[*(p + 1)]->setConstraint("m"); |
| NumMCOperands += 1; |
| break; |
| case CVT_95_addConstantSImmOperands_LT_6_44__32_0_GT_: |
| Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| Operands[*(p + 1)]->setConstraint("m"); |
| NumMCOperands += 1; |
| break; |
| case CVT_imm_95_2: |
| Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| Operands[*(p + 1)]->setConstraint(""); |
| ++NumMCOperands; |
| break; |
| case CVT_imm_95_6: |
| Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| Operands[*(p + 1)]->setConstraint(""); |
| ++NumMCOperands; |
| break; |
| case CVT_imm_95_4: |
| Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| Operands[*(p + 1)]->setConstraint(""); |
| ++NumMCOperands; |
| break; |
| case CVT_imm_95_5: |
| Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| Operands[*(p + 1)]->setConstraint(""); |
| ++NumMCOperands; |
| break; |
| case CVT_imm_95_31: |
| Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
| Operands[*(p + 1)]->setConstraint(""); |
| ++NumMCOperands; |
| break; |
| } |
| } |
| } |
| |
| namespace { |
| |
| /// MatchClassKind - The kinds of classes which participate in |
| /// instruction matching. |
| enum MatchClassKind { |
| InvalidMatchClass = 0, |
| OptionalMatchClass = 1, |
| MCK__HASH_, // '#' |
| MCK__40_, // '(' |
| MCK__41_, // ')' |
| MCK_0, // '0' |
| MCK_16, // '16' |
| MCK__91_, // '[' |
| MCK__93_, // ']' |
| MCK_bit, // 'bit' |
| MCK_inst, // 'inst' |
| MCK_LAST_TOKEN = MCK_inst, |
| MCK_Reg37, // derived register class |
| MCK_Reg19, // derived register class |
| MCK_ACC128, // register class 'ACC128' |
| MCK_ACC64, // register class 'ACC64' |
| MCK_CPURAReg, // register class 'CPURAReg,RA' |
| MCK_CPUSPReg, // register class 'CPUSPReg,SP32,SP' |
| MCK_DSPCC, // register class 'DSPCC' |
| MCK_GP32, // register class 'GP32' |
| MCK_GP64, // register class 'GP64' |
| MCK_GPR32ZERO, // register class 'GPR32ZERO,ZERO' |
| MCK_HI32, // register class 'HI32' |
| MCK_HI64, // register class 'HI64' |
| MCK_LO32, // register class 'LO32' |
| MCK_LO64, // register class 'LO64' |
| MCK_PC, // register class 'PC' |
| MCK_SP64, // register class 'SP64' |
| MCK_Reg32, // derived register class |
| MCK_Reg13, // derived register class |
| MCK_Reg33, // derived register class |
| MCK_Reg31, // derived register class |
| MCK_Reg30, // derived register class |
| MCK_Reg14, // derived register class |
| MCK_Reg11, // derived register class |
| MCK_GPRMM16MovePPairFirst, // register class 'GPRMM16MovePPairFirst' |
| MCK_OCTEON_MPL, // register class 'OCTEON_MPL' |
| MCK_OCTEON_P, // register class 'OCTEON_P' |
| MCK_Reg28, // derived register class |
| MCK_Reg23, // derived register class |
| MCK_Reg9, // derived register class |
| MCK_Reg4, // derived register class |
| MCK_ACC64DSP, // register class 'ACC64DSP' |
| MCK_HI32DSP, // register class 'HI32DSP' |
| MCK_LO32DSP, // register class 'LO32DSP' |
| MCK_Reg34, // derived register class |
| MCK_GPRMM16MovePPairSecond, // register class 'GPRMM16MovePPairSecond' |
| MCK_Reg29, // derived register class |
| MCK_Reg27, // derived register class |
| MCK_Reg10, // derived register class |
| MCK_Reg8, // derived register class |
| MCK_Reg25, // derived register class |
| MCK_Reg22, // derived register class |
| MCK_Reg21, // derived register class |
| MCK_CPU16Regs, // register class 'CPU16Regs,GPRMM16' |
| MCK_FCC, // register class 'FCC' |
| MCK_GPRMM16MoveP, // register class 'GPRMM16MoveP' |
| MCK_GPRMM16Zero, // register class 'GPRMM16Zero' |
| MCK_Reg26, // derived register class |
| MCK_CPU16RegsPlusSP, // register class 'CPU16RegsPlusSP' |
| MCK_AFGR64, // register class 'AFGR64' |
| MCK_MSA128WEvens, // register class 'MSA128WEvens' |
| MCK_Reg24, // derived register class |
| MCK_GPR32NONZERO, // register class 'GPR32NONZERO' |
| MCK_CCR, // register class 'CCR' |
| MCK_COP0, // register class 'COP0' |
| MCK_COP2, // register class 'COP2' |
| MCK_COP3, // register class 'COP3' |
| MCK_DSPR, // register class 'DSPR,GPR32' |
| MCK_FGR32, // register class 'FGR32,FGRCC' |
| MCK_FGR64, // register class 'FGR64' |
| MCK_GPR64, // register class 'GPR64' |
| MCK_HWRegs, // register class 'HWRegs' |
| MCK_MSA128F16, // register class 'MSA128F16,MSA128B,MSA128D,MSA128H,MSA128W' |
| MCK_MSACtrl, // register class 'MSACtrl' |
| MCK_LAST_REGISTER = MCK_MSACtrl, |
| MCK_ACC64DSPAsmReg, // user defined class 'ACC64DSPAsmOperand' |
| MCK_AFGR64AsmReg, // user defined class 'AFGR64AsmOperand' |
| MCK_CCRAsmReg, // user defined class 'CCRAsmOperand' |
| MCK_COP0AsmReg, // user defined class 'COP0AsmOperand' |
| MCK_COP2AsmReg, // user defined class 'COP2AsmOperand' |
| MCK_COP3AsmReg, // user defined class 'COP3AsmOperand' |
| MCK_FCCAsmReg, // user defined class 'FCCRegsAsmOperand' |
| MCK_FGR32AsmReg, // user defined class 'FGR32AsmOperand' |
| MCK_FGR64AsmReg, // user defined class 'FGR64AsmOperand' |
| MCK_GPR32AsmReg, // user defined class 'GPR32AsmOperand' |
| MCK_GPR32NonZeroAsmReg, // user defined class 'GPR32NonZeroAsmOperand' |
| MCK_GPR32ZeroAsmReg, // user defined class 'GPR32ZeroAsmOperand' |
| MCK_GPR64AsmReg, // user defined class 'GPR64AsmOperand' |
| MCK_GPRMM16AsmReg, // user defined class 'GPRMM16AsmOperand' |
| MCK_GPRMM16AsmRegMoveP, // user defined class 'GPRMM16AsmOperandMoveP' |
| MCK_GPRMM16AsmRegMovePPairFirst, // user defined class 'GPRMM16AsmOperandMovePPairFirst' |
| MCK_GPRMM16AsmRegMovePPairSecond, // user defined class 'GPRMM16AsmOperandMovePPairSecond' |
| MCK_GPRMM16AsmRegZero, // user defined class 'GPRMM16AsmOperandZero' |
| MCK_HI32DSPAsmReg, // user defined class 'HI32DSPAsmOperand' |
| MCK_HWRegsAsmReg, // user defined class 'HWRegsAsmOperand' |
| MCK_Imm, // user defined class 'ImmAsmOperand' |
| MCK_LO32DSPAsmReg, // user defined class 'LO32DSPAsmOperand' |
| MCK_MSA128AsmReg, // user defined class 'MSA128AsmOperand' |
| MCK_MSACtrlAsmReg, // user defined class 'MSACtrlAsmOperand' |
| MCK_MicroMipsMemGP, // user defined class 'MicroMipsMemGPAsmOperand' |
| MCK_MicroMipsMem, // user defined class 'MicroMipsMemGPRMM16AsmOperand' |
| MCK_MicroMipsMemSP, // user defined class 'MicroMipsMemSPAsmOperand' |
| MCK_InvNum, // user defined class 'MipsInvertedImmoperand' |
| MCK_JumpTarget, // user defined class 'MipsJumpTargetAsmOperand' |
| MCK_MemOffsetSimmPtr, // user defined class 'MipsMemSimmPtrAsmOperand' |
| MCK_MemOffsetUimm4, // user defined class 'MipsMemUimm4AsmOperand' |
| MCK_MemOffsetSimm9_0, // user defined class 'anonymous_4283' |
| MCK_MemOffsetSimm10_0, // user defined class 'anonymous_4284' |
| MCK_MemOffsetSimm11_0, // user defined class 'anonymous_4285' |
| MCK_MemOffsetSimm12_0, // user defined class 'anonymous_4286' |
| MCK_MemOffsetSimm16_0, // user defined class 'anonymous_4287' |
| MCK_MemOffsetSimm10_1, // user defined class 'anonymous_4288' |
| MCK_MemOffsetSimm10_2, // user defined class 'anonymous_4289' |
| MCK_MemOffsetSimm10_3, // user defined class 'anonymous_4290' |
| MCK_Mem, // user defined class 'MipsMemAsmOperand' |
| MCK_RegList16, // user defined class 'RegList16AsmOperand' |
| MCK_RegList, // user defined class 'RegListAsmOperand' |
| MCK_Simm19_Lsl2, // user defined class 'Simm19Lsl2AsmOperand' |
| MCK_StrictlyAFGR64AsmReg, // user defined class 'StrictlyAFGR64AsmOperand' |
| MCK_StrictlyFGR32AsmReg, // user defined class 'StrictlyFGR32AsmOperand' |
| MCK_StrictlyFGR64AsmReg, // user defined class 'StrictlyFGR64AsmOperand' |
| MCK_ConstantImmz, // user defined class 'ConstantImmzAsmOperandClass' |
| MCK_ConstantUImm1_0, // user defined class 'ConstantUImm1AsmOperandClass' |
| MCK_ConstantUImm2_0, // user defined class 'ConstantUImm2AsmOperandClass' |
| MCK_ConstantUImm2_1, // user defined class 'ConstantUImm2Plus1AsmOperandClass' |
| MCK_ConstantUImm3_0, // user defined class 'ConstantUImm3AsmOperandClass' |
| MCK_ConstantSImm4_0, // user defined class 'ConstantSImm4AsmOperandClass' |
| MCK_ConstantUImm4_0, // user defined class 'ConstantUImm4AsmOperandClass' |
| MCK_ConstantSImm5_0, // user defined class 'ConstantSImm5AsmOperandClass' |
| MCK_ConstantUImm5_0, // user defined class 'ConstantUImm5AsmOperandClass' |
| MCK_ConstantUImm5_1, // user defined class 'ConstantUImm5Plus1AsmOperandClass' |
| MCK_ConstantUImm5_Plus1_Report_UImm6, // user defined class 'ConstantUImm5Plus1ReportUImm6AsmOperandClass' |
| MCK_ConstantUImm5_32_Norm, // user defined class 'ConstantUImm5Plus32NormalizeAsmOperandClass' |
| MCK_ConstantUImm5_32, // user defined class 'ConstantUImm5Plus32AsmOperandClass' |
| MCK_ConstantUImm5_0_Report_UImm6, // user defined class 'ConstantUImm5ReportUImm6AsmOperandClass' |
| MCK_ConstantUImm5_33, // user defined class 'ConstantUImm5Plus33AsmOperandClass' |
| MCK_ConstantUImmRange2_64, // user defined class 'ConstantUImm5_Range2_64AsmOperandClass' |
| MCK_UImm5Lsl2, // user defined class 'ConstantUImm5Lsl2AsmOperandClass' |
| MCK_ConstantSImm6_0, // user defined class 'ConstantSImm6AsmOperandClass' |
| MCK_ConstantUImm6_0, // user defined class 'ConstantUImm6AsmOperandClass' |
| MCK_UImm6Lsl2, // user defined class 'ConstantUImm6Lsl2AsmOperandClass' |
| MCK_ConstantUImm7_0, // user defined class 'ConstantUImm7AsmOperandClass' |
| MCK_UImm7_N1, // user defined class 'ConstantUImm7Sub1AsmOperandClass' |
| MCK_ConstantUImm8_0, // user defined class 'ConstantUImm8AsmOperandClass' |
| MCK_SImm7Lsl2, // user defined class 'ConstantSImm7Lsl2AsmOperandClass' |
| MCK_ConstantSImm9_0, // user defined class 'ConstantSImm9AsmOperandClass' |
| MCK_ConstantSImm10_0, // user defined class 'ConstantSImm10AsmOperandClass' |
| MCK_ConstantUImm10_0, // user defined class 'ConstantUImm10AsmOperandClass' |
| MCK_SImm10Lsl1, // user defined class 'ConstantSImm10Lsl1AsmOperandClass' |
| MCK_ConstantSImm11_0, // user defined class 'ConstantSImm11AsmOperandClass' |
| MCK_SImm10Lsl2, // user defined class 'ConstantSImm10Lsl2AsmOperandClass' |
| MCK_SImm10Lsl3, // user defined class 'ConstantSImm10Lsl3AsmOperandClass' |
| MCK_SImm16, // user defined class 'SImm16AsmOperandClass' |
| MCK_SImm16_Relaxed, // user defined class 'SImm16RelaxedAsmOperandClass' |
| MCK_UImm16_AltRelaxed, // user defined class 'UImm16AltRelaxedAsmOperandClass' |
| MCK_UImm16, // user defined class 'UImm16AsmOperandClass' |
| MCK_SImm19Lsl2, // user defined class 'ConstantSImm19Lsl2AsmOperandClass' |
| MCK_UImm16_Relaxed, // user defined class 'UImm16RelaxedAsmOperandClass' |
| MCK_ConstantUImm20_0, // user defined class 'ConstantUImm20AsmOperandClass' |
| MCK_ConstantUImm26_0, // user defined class 'ConstantUImm26AsmOperandClass' |
| MCK_SImm32, // user defined class 'SImm32AsmOperandClass' |
| MCK_SImm32_Relaxed, // user defined class 'SImm32RelaxedAsmOperandClass' |
| MCK_UImm32_Coerced, // user defined class 'UImm32CoercedAsmOperandClass' |
| NumMatchClassKinds |
| }; |
| |
| } // end anonymous namespace |
| |
| static unsigned getDiagKindFromRegisterClass(MatchClassKind RegisterClass) { |
| return MCTargetAsmParser::Match_InvalidOperand; |
| } |
| |
| static MatchClassKind matchTokenString(StringRef Name) { |
| switch (Name.size()) { |
| default: break; |
| case 1: // 6 strings to match. |
| switch (Name[0]) { |
| default: break; |
| case '#': // 1 string to match. |
| return MCK__HASH_; // "#" |
| case '(': // 1 string to match. |
| return MCK__40_; // "(" |
| case ')': // 1 string to match. |
| return MCK__41_; // ")" |
| case '0': // 1 string to match. |
| return MCK_0; // "0" |
| case '[': // 1 string to match. |
| return MCK__91_; // "[" |
| case ']': // 1 string to match. |
| return MCK__93_; // "]" |
| } |
| break; |
| case 2: // 1 string to match. |
| if (memcmp(Name.data()+0, "16", 2) != 0) |
| break; |
| return MCK_16; // "16" |
| case 3: // 1 string to match. |
| if (memcmp(Name.data()+0, "bit", 3) != 0) |
| break; |
| return MCK_bit; // "bit" |
| case 4: // 1 string to match. |
| if (memcmp(Name.data()+0, "inst", 4) != 0) |
| break; |
| return MCK_inst; // "inst" |
| } |
| return InvalidMatchClass; |
| } |
| |
| /// isSubclass - Compute whether \p A is a subclass of \p B. |
| static bool isSubclass(MatchClassKind A, MatchClassKind B) { |
| if (A == B) |
| return true; |
| |
| switch (A) { |
| default: |
| return false; |
| |
| case MCK_Reg37: |
| switch (B) { |
| default: return false; |
| case MCK_Reg24: return true; |
| case MCK_GPR64: return true; |
| } |
| |
| case MCK_Reg19: |
| switch (B) { |
| default: return false; |
| case MCK_Reg23: return true; |
| case MCK_Reg22: return true; |
| case MCK_Reg21: return true; |
| case MCK_GPR64: return true; |
| } |
| |
| case MCK_ACC64: |
| return B == MCK_ACC64DSP; |
| |
| case MCK_CPURAReg: |
| switch (B) { |
| default: return false; |
| case MCK_GPR32NONZERO: return true; |
| case MCK_DSPR: return true; |
| } |
| |
| case MCK_CPUSPReg: |
| switch (B) { |
| default: return false; |
| case MCK_CPU16RegsPlusSP: return true; |
| case MCK_GPR32NONZERO: return true; |
| case MCK_DSPR: return true; |
| } |
| |
| case MCK_GP32: |
| switch (B) { |
| default: return false; |
| case MCK_GPR32NONZERO: return true; |
| case MCK_DSPR: return true; |
| } |
| |
| case MCK_GP64: |
| switch (B) { |
| default: return false; |
| case MCK_Reg24: return true; |
| case MCK_GPR64: return true; |
| } |
| |
| case MCK_GPR32ZERO: |
| switch (B) { |
| default: return false; |
| case MCK_Reg4: return true; |
| case MCK_GPRMM16MoveP: return true; |
| case MCK_GPRMM16Zero: return true; |
| case MCK_DSPR: return true; |
| } |
| |
| case MCK_HI32: |
| return B == MCK_HI32DSP; |
| |
| case MCK_LO32: |
| return B == MCK_LO32DSP; |
| |
| case MCK_SP64: |
| switch (B) { |
| default: return false; |
| case MCK_Reg26: return true; |
| case MCK_Reg24: return true; |
| case MCK_GPR64: return true; |
| } |
| |
| case MCK_Reg32: |
| switch (B) { |
| default: return false; |
| case MCK_Reg33: return true; |
| case MCK_Reg31: return true; |
| case MCK_Reg34: return true; |
| case MCK_Reg27: return true; |
| case MCK_Reg25: return true; |
| case MCK_Reg21: return true; |
| case MCK_Reg26: return true; |
| case MCK_Reg24: return true; |
| case MCK_GPR64: return true; |
| } |
| |
| case MCK_Reg13: |
| switch (B) { |
| default: return false; |
| case MCK_Reg14: return true; |
| case MCK_GPRMM16MovePPairFirst: return true; |
| case MCK_GPRMM16MovePPairSecond: return true; |
| case MCK_Reg8: return true; |
| case MCK_CPU16Regs: return true; |
| case MCK_GPRMM16Zero: return true; |
| case MCK_CPU16RegsPlusSP: return true; |
| case MCK_GPR32NONZERO: return true; |
| case MCK_DSPR: return true; |
| } |
| |
| case MCK_Reg33: |
| switch (B) { |
| default: return false; |
| case MCK_Reg34: return true; |
| case MCK_Reg27: return true; |
| case MCK_Reg25: return true; |
| case MCK_Reg21: return true; |
| case MCK_Reg26: return true; |
| case MCK_Reg24: return true; |
| case MCK_GPR64: return true; |
| } |
| |
| case MCK_Reg31: |
| switch (B) { |
| default: return false; |
| case MCK_Reg27: return true; |
| case MCK_Reg25: return true; |
| case MCK_Reg21: return true; |
| case MCK_Reg26: return true; |
| case MCK_Reg24: return true; |
| case MCK_GPR64: return true; |
| } |
| |
| case MCK_Reg30: |
| switch (B) { |
| default: return false; |
| case MCK_Reg28: return true; |
| case MCK_Reg23: return true; |
| case MCK_Reg29: return true; |
| case MCK_Reg27: return true; |
| case MCK_Reg25: return true; |
| case MCK_Reg22: return true; |
| case MCK_Reg21: return true; |
| case MCK_Reg26: return true; |
| case MCK_Reg24: return true; |
| case MCK_GPR64: return true; |
| } |
| |
| case MCK_Reg14: |
| switch (B) { |
| default: return false; |
| case MCK_GPRMM16MovePPairSecond: return true; |
| case MCK_Reg8: return true; |
| case MCK_CPU16Regs: return true; |
| case MCK_GPRMM16Zero: return true; |
| case MCK_CPU16RegsPlusSP: return true; |
| case MCK_GPR32NONZERO: return true; |
| case MCK_DSPR: return true; |
| } |
| |
| case MCK_Reg11: |
| switch (B) { |
| default: return false; |
| case MCK_Reg9: return true; |
| case MCK_Reg4: return true; |
| case MCK_Reg10: return true; |
| case MCK_Reg8: return true; |
| case MCK_CPU16Regs: return true; |
| case MCK_GPRMM16MoveP: return true; |
| case MCK_GPRMM16Zero: return true; |
| case MCK_CPU16RegsPlusSP: return true; |
| case MCK_GPR32NONZERO: return true; |
| case MCK_DSPR: return true; |
| } |
| |
| case MCK_GPRMM16MovePPairFirst: |
| switch (B) { |
| default: return false; |
| case MCK_Reg8: return true; |
| case MCK_CPU16Regs: return true; |
| case MCK_GPRMM16Zero: return true; |
| case MCK_CPU16RegsPlusSP: return true; |
| case MCK_GPR32NONZERO: return true; |
| case MCK_DSPR: return true; |
| } |
| |
| case MCK_Reg28: |
| switch (B) { |
| default: return false; |
| case MCK_Reg29: return true; |
| case MCK_Reg25: return true; |
| case MCK_Reg22: return true; |
| case MCK_Reg26: return true; |
| case MCK_Reg24: return true; |
| case MCK_GPR64: return true; |
| } |
| |
| case MCK_Reg23: |
| switch (B) { |
| default: return false; |
| case MCK_Reg22: return true; |
| case MCK_Reg21: return true; |
| case MCK_GPR64: return true; |
| } |
| |
| case MCK_Reg9: |
| switch (B) { |
| default: return false; |
| case MCK_Reg10: return true; |
| case MCK_CPU16Regs: return true; |
| case MCK_GPRMM16MoveP: return true; |
| case MCK_CPU16RegsPlusSP: return true; |
| case MCK_GPR32NONZERO: return true; |
| case MCK_DSPR: return true; |
| } |
| |
| case MCK_Reg4: |
| switch (B) { |
| default: return false; |
| case MCK_GPRMM16MoveP: return true; |
| case MCK_GPRMM16Zero: return true; |
| case MCK_DSPR: return true; |
| } |
| |
| case MCK_Reg34: |
| switch (B) { |
| default: return false; |
| case MCK_Reg24: return true; |
| case MCK_GPR64: return true; |
| } |
| |
| case MCK_GPRMM16MovePPairSecond: |
| switch (B) { |
| default: return false; |
| case MCK_GPR32NONZERO: return true; |
| case MCK_DSPR: return true; |
| } |
| |
| case MCK_Reg29: |
| switch (B) { |
| default: return false; |
| case MCK_Reg22: return true; |
| case MCK_Reg24: return true; |
| case MCK_GPR64: return true; |
| } |
| |
| case MCK_Reg27: |
| switch (B) { |
| default: return false; |
| case MCK_Reg25: return true; |
| case MCK_Reg21: return true; |
| case MCK_Reg26: return true; |
| case MCK_Reg24: return true; |
| case MCK_GPR64: return true; |
| } |
| |
| case MCK_Reg10: |
| switch (B) { |
| default: return false; |
| case MCK_GPRMM16MoveP: return true; |
| case MCK_GPR32NONZERO: return true; |
| case MCK_DSPR: return true; |
| } |
| |
| case MCK_Reg8: |
| switch (B) { |
| default: return false; |
| case MCK_CPU16Regs: return true; |
| case MCK_GPRMM16Zero: return true; |
| case MCK_CPU16RegsPlusSP: return true; |
| case MCK_GPR32NONZERO: return true; |
| case MCK_DSPR: return true; |
| } |
| |
| case MCK_Reg25: |
| switch (B) { |
| default: return false; |
| case MCK_Reg26: return true; |
| case MCK_Reg24: return true; |
| case MCK_GPR64: return true; |
| } |
| |
| case MCK_Reg22: |
| return B == MCK_GPR64; |
| |
| case MCK_Reg21: |
| return B == MCK_GPR64; |
| |
| case MCK_CPU16Regs: |
| switch (B) { |
| default: return false; |
| case MCK_CPU16RegsPlusSP: return true; |
| case MCK_GPR32NONZERO: return true; |
| case MCK_DSPR: return true; |
| } |
| |
| case MCK_GPRMM16MoveP: |
| return B == MCK_DSPR; |
| |
| case MCK_GPRMM16Zero: |
| return B == MCK_DSPR; |
| |
| case MCK_Reg26: |
| switch (B) { |
| default: return false; |
| case MCK_Reg24: return true; |
| case MCK_GPR64: return true; |
| } |
| |
| case MCK_CPU16RegsPlusSP: |
| switch (B) { |
| default: return false; |
| case MCK_GPR32NONZERO: return true; |
| case MCK_DSPR: return true; |
| } |
| |
| case MCK_MSA128WEvens: |
| return B == MCK_MSA128F16; |
| |
| case MCK_Reg24: |
| return B == MCK_GPR64; |
| |
| case MCK_GPR32NONZERO: |
| return B == MCK_DSPR; |
| |
| case MCK_MemOffsetSimmPtr: |
| return B == MCK_Mem; |
| |
| case MCK_MemOffsetUimm4: |
| return B == MCK_Mem; |
| |
| case MCK_MemOffsetSimm9_0: |
| return B == MCK_Mem; |
| |
| case MCK_MemOffsetSimm10_0: |
| return B == MCK_Mem; |
| |
| case MCK_MemOffsetSimm11_0: |
| return B == MCK_Mem; |
| |
| case MCK_MemOffsetSimm12_0: |
| return B == MCK_Mem; |
| |
| case MCK_MemOffsetSimm16_0: |
| return B == MCK_Mem; |
| |
| case MCK_MemOffsetSimm10_1: |
| return B == MCK_Mem; |
| |
| case MCK_MemOffsetSimm10_2: |
| return B == MCK_Mem; |
| |
| case MCK_MemOffsetSimm10_3: |
| return B == MCK_Mem; |
| |
| case MCK_ConstantImmz: |
| switch (B) { |
| default: return false; |
| case MCK_ConstantUImm1_0: return true; |
| case MCK_ConstantUImm2_0: return true; |
| case MCK_ConstantUImm3_0: return true; |
| case MCK_ConstantSImm4_0: return true; |
| case MCK_ConstantUImm4_0: return true; |
| case MCK_ConstantSImm5_0: return true; |
| case MCK_ConstantUImm5_0: return true; |
| case MCK_ConstantUImm5_1: return true; |
| case MCK_ConstantUImm5_Plus1_Report_UImm6: return true; |
| case MCK_ConstantUImm5_32_Norm: return true; |
| case MCK_ConstantUImm5_32: return true; |
| case MCK_ConstantUImm5_0_Report_UImm6: return true; |
| case MCK_ConstantUImm5_33: return true; |
| case MCK_ConstantUImmRange2_64: return true; |
| case MCK_UImm5Lsl2: return true; |
| case MCK_ConstantSImm6_0: return true; |
| case MCK_ConstantUImm6_0: return true; |
| case MCK_UImm6Lsl2: return true; |
| case MCK_ConstantUImm7_0: return true; |
| case MCK_UImm7_N1: return true; |
| case MCK_ConstantUImm8_0: return true; |
| case MCK_SImm7Lsl2: return true; |
| case MCK_ConstantSImm9_0: return true; |
| case MCK_ConstantSImm10_0: return true; |
| case MCK_ConstantUImm10_0: return true; |
| case MCK_SImm10Lsl1: return true; |
| case MCK_ConstantSImm11_0: return true; |
| case MCK_SImm10Lsl2: return true; |
| case MCK_SImm10Lsl3: return true; |
| case MCK_SImm16: return true; |
| case MCK_SImm16_Relaxed: return true; |
| case MCK_UImm16_Relaxed: return true; |
| case MCK_ConstantUImm20_0: return true; |
| case MCK_ConstantUImm26_0: return true; |
| case MCK_SImm32: return true; |
| case MCK_SImm32_Relaxed: return true; |
| case MCK_UImm32_Coerced: return true; |
| } |
| |
| case MCK_ConstantUImm1_0: |
| switch (B) { |
| default: return false; |
| case MCK_ConstantUImm2_0: return true; |
| case MCK_ConstantUImm3_0: return true; |
| case MCK_ConstantSImm4_0: return true; |
| case MCK_ConstantUImm4_0: return true; |
| case MCK_ConstantSImm5_0: return true; |
| case MCK_ConstantUImm5_0: return true; |
| case MCK_ConstantUImm5_1: return true; |
| case MCK_ConstantUImm5_Plus1_Report_UImm6: return true; |
| case MCK_ConstantUImm5_32_Norm: return true; |
| case MCK_ConstantUImm5_32: return true; |
| case MCK_ConstantUImm5_0_Report_UImm6: return true; |
| case MCK_ConstantUImm5_33: return true; |
| case |
