| /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
| |* *| |
| |* Assembly Writer Source Fragment *| |
| |* *| |
| |* Automatically generated file, do not edit! *| |
| |* *| |
| \*===----------------------------------------------------------------------===*/ |
| |
| /// getMnemonic - This method is automatically generated by tablegen |
| /// from the instruction set description. |
| std::pair<const char *, uint64_t> LoongArchInstPrinter::getMnemonic(const MCInst *MI) { |
| |
| #ifdef __GNUC__ |
| #pragma GCC diagnostic push |
| #pragma GCC diagnostic ignored "-Woverlength-strings" |
| #endif |
| static const char AsmStrs[] = { |
| /* 0 */ "ld.b\t\0" |
| /* 6 */ "iocsrrd.b\t\0" |
| /* 17 */ "ldle.b\t\0" |
| /* 25 */ "stle.b\t\0" |
| /* 33 */ "iocsrwr.b\t\0" |
| /* 44 */ "ldgt.b\t\0" |
| /* 52 */ "stgt.b\t\0" |
| /* 60 */ "st.b\t\0" |
| /* 66 */ "ext.w.b\t\0" |
| /* 75 */ "ldx.b\t\0" |
| /* 82 */ "stx.b\t\0" |
| /* 89 */ "bitrev.4b\t\0" |
| /* 100 */ "bitrev.8b\t\0" |
| /* 111 */ "invtlb\t\0" |
| /* 119 */ "fmina.d\t\0" |
| /* 128 */ "sra.d\t\0" |
| /* 135 */ "fmaxa.d\t\0" |
| /* 144 */ "amadd_db.d\t\0" |
| /* 156 */ "amand_db.d\t\0" |
| /* 168 */ "ammin_db.d\t\0" |
| /* 180 */ "amswap_db.d\t\0" |
| /* 193 */ "amor_db.d\t\0" |
| /* 204 */ "amxor_db.d\t\0" |
| /* 216 */ "ammax_db.d\t\0" |
| /* 228 */ "fscaleb.d\t\0" |
| /* 239 */ "flogb.d\t\0" |
| /* 248 */ "fsub.d\t\0" |
| /* 256 */ "fmsub.d\t\0" |
| /* 265 */ "fnmsub.d\t\0" |
| /* 275 */ "revb.d\t\0" |
| /* 283 */ "sc.d\t\0" |
| /* 289 */ "fadd.d\t\0" |
| /* 297 */ "amadd.d\t\0" |
| /* 306 */ "fmadd.d\t\0" |
| /* 315 */ "fnmadd.d\t\0" |
| /* 325 */ "fld.d\t\0" |
| /* 332 */ "amand.d\t\0" |
| /* 341 */ "mod.d\t\0" |
| /* 348 */ "iocsrrd.d\t\0" |
| /* 359 */ "fcmp.cle.d\t\0" |
| /* 371 */ "fldle.d\t\0" |
| /* 380 */ "fcmp.sle.d\t\0" |
| /* 392 */ "asrtle.d\t\0" |
| /* 402 */ "fstle.d\t\0" |
| /* 411 */ "fcmp.cule.d\t\0" |
| /* 424 */ "fcmp.sule.d\t\0" |
| /* 437 */ "rdtime.d\t\0" |
| /* 447 */ "fcmp.cne.d\t\0" |
| /* 459 */ "fcmp.sne.d\t\0" |
| /* 471 */ "fcmp.cune.d\t\0" |
| /* 484 */ "fcmp.sune.d\t\0" |
| /* 497 */ "fcmp.caf.d\t\0" |
| /* 509 */ "fcmp.saf.d\t\0" |
| /* 521 */ "fneg.d\t\0" |
| /* 529 */ "mulh.d\t\0" |
| /* 537 */ "revh.d\t\0" |
| /* 545 */ "lu32i.d\t\0" |
| /* 554 */ "lu52i.d\t\0" |
| /* 563 */ "addu16i.d\t\0" |
| /* 574 */ "srai.d\t\0" |
| /* 582 */ "addi.d\t\0" |
| /* 590 */ "slli.d\t\0" |
| /* 598 */ "srli.d\t\0" |
| /* 606 */ "rotri.d\t\0" |
| /* 615 */ "bytepick.d\t\0" |
| /* 627 */ "bstrpick.d\t\0" |
| /* 639 */ "ftintrne.l.d\t\0" |
| /* 653 */ "ftintrm.l.d\t\0" |
| /* 666 */ "ftintrp.l.d\t\0" |
| /* 679 */ "ftint.l.d\t\0" |
| /* 690 */ "ftintrz.l.d\t\0" |
| /* 703 */ "sll.d\t\0" |
| /* 710 */ "srl.d\t\0" |
| /* 717 */ "alsl.d\t\0" |
| /* 725 */ "fmul.d\t\0" |
| /* 733 */ "fcopysign.d\t\0" |
| /* 746 */ "fmin.d\t\0" |
| /* 754 */ "ammin.d\t\0" |
| /* 763 */ "fcmp.cun.d\t\0" |
| /* 775 */ "fcmp.sun.d\t\0" |
| /* 787 */ "clo.d\t\0" |
| /* 794 */ "cto.d\t\0" |
| /* 801 */ "amswap.d\t\0" |
| /* 811 */ "frecip.d\t\0" |
| /* 821 */ "fcmp.ceq.d\t\0" |
| /* 833 */ "fcmp.seq.d\t\0" |
| /* 845 */ "fcmp.cueq.d\t\0" |
| /* 858 */ "fcmp.sueq.d\t\0" |
| /* 871 */ "movgr2fr.d\t\0" |
| /* 883 */ "movfr2gr.d\t\0" |
| /* 895 */ "fcmp.cor.d\t\0" |
| /* 907 */ "amor.d\t\0" |
| /* 915 */ "fcmp.sor.d\t\0" |
| /* 927 */ "amxor.d\t\0" |
| /* 936 */ "rotr.d\t\0" |
| /* 944 */ "ldptr.d\t\0" |
| /* 953 */ "stptr.d\t\0" |
| /* 962 */ "iocsrwr.d\t\0" |
| /* 973 */ "fcvt.s.d\t\0" |
| /* 983 */ "fabs.d\t\0" |
| /* 991 */ "bstrins.d\t\0" |
| /* 1002 */ "fclass.d\t\0" |
| /* 1012 */ "fldgt.d\t\0" |
| /* 1021 */ "asrtgt.d\t\0" |
| /* 1031 */ "fstgt.d\t\0" |
| /* 1040 */ "fcmp.clt.d\t\0" |
| /* 1052 */ "fcmp.slt.d\t\0" |
| /* 1064 */ "fcmp.cult.d\t\0" |
| /* 1077 */ "fcmp.sult.d\t\0" |
| /* 1090 */ "frint.d\t\0" |
| /* 1099 */ "fsqrt.d\t\0" |
| /* 1108 */ "frsqrt.d\t\0" |
| /* 1118 */ "fst.d\t\0" |
| /* 1125 */ "bitrev.d\t\0" |
| /* 1135 */ "fdiv.d\t\0" |
| /* 1143 */ "fmov.d\t\0" |
| /* 1151 */ "ftintrne.w.d\t\0" |
| /* 1165 */ "ftintrm.w.d\t\0" |
| /* 1178 */ "ftintrp.w.d\t\0" |
| /* 1191 */ "ftint.w.d\t\0" |
| /* 1202 */ "ftintrz.w.d\t\0" |
| /* 1215 */ "fmax.d\t\0" |
| /* 1223 */ "ammax.d\t\0" |
| /* 1232 */ "fldx.d\t\0" |
| /* 1240 */ "fstx.d\t\0" |
| /* 1248 */ "clz.d\t\0" |
| /* 1255 */ "ctz.d\t\0" |
| /* 1262 */ "la.tls.gd\t\0" |
| /* 1273 */ "la.tls.ld\t\0" |
| /* 1284 */ "preld\t\0" |
| /* 1291 */ "and\t\0" |
| /* 1296 */ "tlbrd\t\0" |
| /* 1303 */ "csrrd\t\0" |
| /* 1310 */ "bge\t\0" |
| /* 1315 */ "la.tls.ie\t\0" |
| /* 1326 */ "la.tls.le\t\0" |
| /* 1337 */ "idle\t\0" |
| /* 1343 */ "bne\t\0" |
| /* 1348 */ "ldpte\t\0" |
| /* 1355 */ "movfr2cf\t\0" |
| /* 1365 */ "movgr2cf\t\0" |
| /* 1375 */ "cpucfg\t\0" |
| /* 1383 */ "csrxchg\t\0" |
| /* 1392 */ "ld.h\t\0" |
| /* 1398 */ "iocsrrd.h\t\0" |
| /* 1409 */ "ldle.h\t\0" |
| /* 1417 */ "stle.h\t\0" |
| /* 1425 */ "iocsrwr.h\t\0" |
| /* 1436 */ "ldgt.h\t\0" |
| /* 1444 */ "stgt.h\t\0" |
| /* 1452 */ "st.h\t\0" |
| /* 1458 */ "ext.w.h\t\0" |
| /* 1467 */ "ldx.h\t\0" |
| /* 1474 */ "stx.h\t\0" |
| /* 1481 */ "revb.2h\t\0" |
| /* 1490 */ "revb.4h\t\0" |
| /* 1499 */ "tlbsrch\t\0" |
| /* 1508 */ "tlbflush\t\0" |
| /* 1518 */ "pcalau12i\t\0" |
| /* 1529 */ "pcaddu12i\t\0" |
| /* 1540 */ "pcaddu18i\t\0" |
| /* 1551 */ "pcaddi\t\0" |
| /* 1559 */ "andi\t\0" |
| /* 1565 */ "xori\t\0" |
| /* 1571 */ "slti\t\0" |
| /* 1577 */ "sltui\t\0" |
| /* 1584 */ "break\t\0" |
| /* 1591 */ "ffint.d.l\t\0" |
| /* 1602 */ "ffint.s.l\t\0" |
| /* 1613 */ "bl\t\0" |
| /* 1617 */ "dbcl\t\0" |
| /* 1623 */ "la.pcrel\t\0" |
| /* 1633 */ "fsel\t\0" |
| /* 1639 */ "syscall\t\0" |
| /* 1648 */ "tlbfill\t\0" |
| /* 1657 */ "jirl\t\0" |
| /* 1663 */ "andn\t\0" |
| /* 1669 */ "orn\t\0" |
| /* 1674 */ "ertn\t\0" |
| /* 1680 */ "cacop\t\0" |
| /* 1687 */ "beq\t\0" |
| /* 1692 */ "dbar\t\0" |
| /* 1698 */ "ibar\t\0" |
| /* 1704 */ "movcf2fr\t\0" |
| /* 1714 */ "movcf2gr\t\0" |
| /* 1724 */ "movfcsr2gr\t\0" |
| /* 1736 */ "lddir\t\0" |
| /* 1743 */ "tlbclr\t\0" |
| /* 1751 */ "nor\t\0" |
| /* 1756 */ "xor\t\0" |
| /* 1761 */ "movgr2fcsr\t\0" |
| /* 1773 */ "tlbwr\t\0" |
| /* 1780 */ "csrwr\t\0" |
| /* 1787 */ "fmina.s\t\0" |
| /* 1796 */ "fmaxa.s\t\0" |
| /* 1805 */ "fscaleb.s\t\0" |
| /* 1816 */ "flogb.s\t\0" |
| /* 1825 */ "fsub.s\t\0" |
| /* 1833 */ "fmsub.s\t\0" |
| /* 1842 */ "fnmsub.s\t\0" |
| /* 1852 */ "fcvt.d.s\t\0" |
| /* 1862 */ "fadd.s\t\0" |
| /* 1870 */ "fmadd.s\t\0" |
| /* 1879 */ "fnmadd.s\t\0" |
| /* 1889 */ "fld.s\t\0" |
| /* 1896 */ "fcmp.cle.s\t\0" |
| /* 1908 */ "fldle.s\t\0" |
| /* 1917 */ "fcmp.sle.s\t\0" |
| /* 1929 */ "fstle.s\t\0" |
| /* 1938 */ "fcmp.cule.s\t\0" |
| /* 1951 */ "fcmp.sule.s\t\0" |
| /* 1964 */ "fcmp.cne.s\t\0" |
| /* 1976 */ "fcmp.sne.s\t\0" |
| /* 1988 */ "fcmp.cune.s\t\0" |
| /* 2001 */ "fcmp.sune.s\t\0" |
| /* 2014 */ "fcmp.caf.s\t\0" |
| /* 2026 */ "fcmp.saf.s\t\0" |
| /* 2038 */ "fneg.s\t\0" |
| /* 2046 */ "ftintrne.l.s\t\0" |
| /* 2060 */ "ftintrm.l.s\t\0" |
| /* 2073 */ "ftintrp.l.s\t\0" |
| /* 2086 */ "ftint.l.s\t\0" |
| /* 2097 */ "ftintrz.l.s\t\0" |
| /* 2110 */ "fmul.s\t\0" |
| /* 2118 */ "fcopysign.s\t\0" |
| /* 2131 */ "fmin.s\t\0" |
| /* 2139 */ "fcmp.cun.s\t\0" |
| /* 2151 */ "fcmp.sun.s\t\0" |
| /* 2163 */ "frecip.s\t\0" |
| /* 2173 */ "fcmp.ceq.s\t\0" |
| /* 2185 */ "fcmp.seq.s\t\0" |
| /* 2197 */ "fcmp.cueq.s\t\0" |
| /* 2210 */ "fcmp.sueq.s\t\0" |
| /* 2223 */ "movfrh2gr.s\t\0" |
| /* 2236 */ "movfr2gr.s\t\0" |
| /* 2248 */ "fcmp.cor.s\t\0" |
| /* 2260 */ "fcmp.sor.s\t\0" |
| /* 2272 */ "fabs.s\t\0" |
| /* 2280 */ "fclass.s\t\0" |
| /* 2290 */ "fldgt.s\t\0" |
| /* 2299 */ "fstgt.s\t\0" |
| /* 2308 */ "fcmp.clt.s\t\0" |
| /* 2320 */ "fcmp.slt.s\t\0" |
| /* 2332 */ "fcmp.cult.s\t\0" |
| /* 2345 */ "fcmp.sult.s\t\0" |
| /* 2358 */ "frint.s\t\0" |
| /* 2367 */ "fsqrt.s\t\0" |
| /* 2376 */ "frsqrt.s\t\0" |
| /* 2386 */ "fst.s\t\0" |
| /* 2393 */ "fdiv.s\t\0" |
| /* 2401 */ "fmov.s\t\0" |
| /* 2409 */ "ftintrne.w.s\t\0" |
| /* 2423 */ "ftintrm.w.s\t\0" |
| /* 2436 */ "ftintrp.w.s\t\0" |
| /* 2449 */ "ftint.w.s\t\0" |
| /* 2460 */ "ftintrz.w.s\t\0" |
| /* 2473 */ "fmax.s\t\0" |
| /* 2481 */ "fldx.s\t\0" |
| /* 2489 */ "fstx.s\t\0" |
| /* 2497 */ "la.abs\t\0" |
| /* 2505 */ "blt\t\0" |
| /* 2510 */ "slt\t\0" |
| /* 2515 */ "la.got\t\0" |
| /* 2523 */ "ld.bu\t\0" |
| /* 2530 */ "ldx.bu\t\0" |
| /* 2538 */ "ammin_db.du\t\0" |
| /* 2551 */ "ammax_db.du\t\0" |
| /* 2564 */ "mod.du\t\0" |
| /* 2572 */ "mulh.du\t\0" |
| /* 2581 */ "ammin.du\t\0" |
| /* 2591 */ "div.du\t\0" |
| /* 2599 */ "ammax.du\t\0" |
| /* 2609 */ "bgeu\t\0" |
| /* 2615 */ "ld.hu\t\0" |
| /* 2622 */ "ldx.hu\t\0" |
| /* 2630 */ "bltu\t\0" |
| /* 2636 */ "sltu\t\0" |
| /* 2642 */ "ammin_db.wu\t\0" |
| /* 2655 */ "ammax_db.wu\t\0" |
| /* 2668 */ "mulw.d.wu\t\0" |
| /* 2679 */ "ld.wu\t\0" |
| /* 2686 */ "mod.wu\t\0" |
| /* 2694 */ "mulh.wu\t\0" |
| /* 2703 */ "alsl.wu\t\0" |
| /* 2712 */ "ammin.wu\t\0" |
| /* 2722 */ "div.wu\t\0" |
| /* 2730 */ "ammax.wu\t\0" |
| /* 2740 */ "ldx.wu\t\0" |
| /* 2748 */ "sra.w\t\0" |
| /* 2755 */ "crcc.w.b.w\t\0" |
| /* 2767 */ "crc.w.b.w\t\0" |
| /* 2778 */ "amadd_db.w\t\0" |
| /* 2790 */ "amand_db.w\t\0" |
| /* 2802 */ "ammin_db.w\t\0" |
| /* 2814 */ "amswap_db.w\t\0" |
| /* 2827 */ "amor_db.w\t\0" |
| /* 2838 */ "amxor_db.w\t\0" |
| /* 2850 */ "ammax_db.w\t\0" |
| /* 2862 */ "sub.w\t\0" |
| /* 2869 */ "sc.w\t\0" |
| /* 2875 */ "ffint.d.w\t\0" |
| /* 2886 */ "crcc.w.d.w\t\0" |
| /* 2898 */ "crc.w.d.w\t\0" |
| /* 2909 */ "mulw.d.w\t\0" |
| /* 2919 */ "amadd.w\t\0" |
| /* 2928 */ "ld.w\t\0" |
| /* 2934 */ "amand.w\t\0" |
| /* 2943 */ "mod.w\t\0" |
| /* 2950 */ "iocsrrd.w\t\0" |
| /* 2961 */ "ldle.w\t\0" |
| /* 2969 */ "stle.w\t\0" |
| /* 2977 */ "crcc.w.h.w\t\0" |
| /* 2989 */ "crc.w.h.w\t\0" |
| /* 3000 */ "rdtimeh.w\t\0" |
| /* 3011 */ "mulh.w\t\0" |
| /* 3019 */ "movgr2frh.w\t\0" |
| /* 3032 */ "lu12i.w\t\0" |
| /* 3041 */ "srai.w\t\0" |
| /* 3049 */ "addi.w\t\0" |
| /* 3057 */ "slli.w\t\0" |
| /* 3065 */ "srli.w\t\0" |
| /* 3073 */ "rotri.w\t\0" |
| /* 3082 */ "bytepick.w\t\0" |
| /* 3094 */ "bstrpick.w\t\0" |
| /* 3106 */ "rdtimel.w\t\0" |
| /* 3117 */ "sll.w\t\0" |
| /* 3124 */ "srl.w\t\0" |
| /* 3131 */ "alsl.w\t\0" |
| /* 3139 */ "mul.w\t\0" |
| /* 3146 */ "ammin.w\t\0" |
| /* 3155 */ "clo.w\t\0" |
| /* 3162 */ "cto.w\t\0" |
| /* 3169 */ "amswap.w\t\0" |
| /* 3179 */ "movgr2fr.w\t\0" |
| /* 3191 */ "amor.w\t\0" |
| /* 3199 */ "amxor.w\t\0" |
| /* 3208 */ "rotr.w\t\0" |
| /* 3216 */ "ldptr.w\t\0" |
| /* 3225 */ "stptr.w\t\0" |
| /* 3234 */ "iocsrwr.w\t\0" |
| /* 3245 */ "ffint.s.w\t\0" |
| /* 3256 */ "bstrins.w\t\0" |
| /* 3267 */ "ldgt.w\t\0" |
| /* 3275 */ "stgt.w\t\0" |
| /* 3283 */ "st.w\t\0" |
| /* 3289 */ "bitrev.w\t\0" |
| /* 3299 */ "div.w\t\0" |
| /* 3306 */ "crcc.w.w.w\t\0" |
| /* 3318 */ "crc.w.w.w\t\0" |
| /* 3329 */ "ammax.w\t\0" |
| /* 3338 */ "ldx.w\t\0" |
| /* 3345 */ "stx.w\t\0" |
| /* 3352 */ "clz.w\t\0" |
| /* 3359 */ "ctz.w\t\0" |
| /* 3366 */ "revb.2w\t\0" |
| /* 3375 */ "revh.2w\t\0" |
| /* 3384 */ "preldx\t\0" |
| /* 3392 */ "bnez\t\0" |
| /* 3398 */ "bcnez\t\0" |
| /* 3405 */ "masknez\t\0" |
| /* 3414 */ "beqz\t\0" |
| /* 3420 */ "bceqz\t\0" |
| /* 3427 */ "maskeqz\t\0" |
| /* 3436 */ "# XRay Function Patchable RET.\0" |
| /* 3467 */ "# XRay Typed Event Log.\0" |
| /* 3491 */ "# XRay Custom Event Log.\0" |
| /* 3516 */ "# XRay Function Enter.\0" |
| /* 3539 */ "# XRay Tail Call Exit.\0" |
| /* 3562 */ "# XRay Function Exit.\0" |
| /* 3584 */ "LIFETIME_END\0" |
| /* 3597 */ "PSEUDO_PROBE\0" |
| /* 3610 */ "BUNDLE\0" |
| /* 3617 */ "DBG_VALUE\0" |
| /* 3627 */ "DBG_INSTR_REF\0" |
| /* 3641 */ "DBG_PHI\0" |
| /* 3649 */ "DBG_LABEL\0" |
| /* 3659 */ "LIFETIME_START\0" |
| /* 3674 */ "DBG_VALUE_LIST\0" |
| /* 3689 */ "# FEntry call\0" |
| }; |
| #ifdef __GNUC__ |
| #pragma GCC diagnostic pop |
| #endif |
| |
| static const uint16_t OpInfo0[] = { |
| 0U, // PHI |
| 0U, // INLINEASM |
| 0U, // INLINEASM_BR |
| 0U, // CFI_INSTRUCTION |
| 0U, // EH_LABEL |
| 0U, // GC_LABEL |
| 0U, // ANNOTATION_LABEL |
| 0U, // KILL |
| 0U, // EXTRACT_SUBREG |
| 0U, // INSERT_SUBREG |
| 0U, // IMPLICIT_DEF |
| 0U, // SUBREG_TO_REG |
| 0U, // COPY_TO_REGCLASS |
| 3618U, // DBG_VALUE |
| 3675U, // DBG_VALUE_LIST |
| 3628U, // DBG_INSTR_REF |
| 3642U, // DBG_PHI |
| 3650U, // DBG_LABEL |
| 0U, // REG_SEQUENCE |
| 0U, // COPY |
| 3611U, // BUNDLE |
| 3660U, // LIFETIME_START |
| 3585U, // LIFETIME_END |
| 3598U, // PSEUDO_PROBE |
| 0U, // ARITH_FENCE |
| 0U, // STACKMAP |
| 3690U, // FENTRY_CALL |
| 0U, // PATCHPOINT |
| 0U, // LOAD_STACK_GUARD |
| 0U, // PREALLOCATED_SETUP |
| 0U, // PREALLOCATED_ARG |
| 0U, // STATEPOINT |
| 0U, // LOCAL_ESCAPE |
| 0U, // FAULTING_OP |
| 0U, // PATCHABLE_OP |
| 3517U, // PATCHABLE_FUNCTION_ENTER |
| 3437U, // PATCHABLE_RET |
| 3563U, // PATCHABLE_FUNCTION_EXIT |
| 3540U, // PATCHABLE_TAIL_CALL |
| 3492U, // PATCHABLE_EVENT_CALL |
| 3468U, // PATCHABLE_TYPED_EVENT_CALL |
| 0U, // ICALL_BRANCH_FUNNEL |
| 0U, // MEMBARRIER |
| 0U, // G_ASSERT_SEXT |
| 0U, // G_ASSERT_ZEXT |
| 0U, // G_ASSERT_ALIGN |
| 0U, // G_ADD |
| 0U, // G_SUB |
| 0U, // G_MUL |
| 0U, // G_SDIV |
| 0U, // G_UDIV |
| 0U, // G_SREM |
| 0U, // G_UREM |
| 0U, // G_SDIVREM |
| 0U, // G_UDIVREM |
| 0U, // G_AND |
| 0U, // G_OR |
| 0U, // G_XOR |
| 0U, // G_IMPLICIT_DEF |
| 0U, // G_PHI |
| 0U, // G_FRAME_INDEX |
| 0U, // G_GLOBAL_VALUE |
| 0U, // G_EXTRACT |
| 0U, // G_UNMERGE_VALUES |
| 0U, // G_INSERT |
| 0U, // G_MERGE_VALUES |
| 0U, // G_BUILD_VECTOR |
| 0U, // G_BUILD_VECTOR_TRUNC |
| 0U, // G_CONCAT_VECTORS |
| 0U, // G_PTRTOINT |
| 0U, // G_INTTOPTR |
| 0U, // G_BITCAST |
| 0U, // G_FREEZE |
| 0U, // G_INTRINSIC_FPTRUNC_ROUND |
| 0U, // G_INTRINSIC_TRUNC |
| 0U, // G_INTRINSIC_ROUND |
| 0U, // G_INTRINSIC_LRINT |
| 0U, // G_INTRINSIC_ROUNDEVEN |
| 0U, // G_READCYCLECOUNTER |
| 0U, // G_LOAD |
| 0U, // G_SEXTLOAD |
| 0U, // G_ZEXTLOAD |
| 0U, // G_INDEXED_LOAD |
| 0U, // G_INDEXED_SEXTLOAD |
| 0U, // G_INDEXED_ZEXTLOAD |
| 0U, // G_STORE |
| 0U, // G_INDEXED_STORE |
| 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS |
| 0U, // G_ATOMIC_CMPXCHG |
| 0U, // G_ATOMICRMW_XCHG |
| 0U, // G_ATOMICRMW_ADD |
| 0U, // G_ATOMICRMW_SUB |
| 0U, // G_ATOMICRMW_AND |
| 0U, // G_ATOMICRMW_NAND |
| 0U, // G_ATOMICRMW_OR |
| 0U, // G_ATOMICRMW_XOR |
| 0U, // G_ATOMICRMW_MAX |
| 0U, // G_ATOMICRMW_MIN |
| 0U, // G_ATOMICRMW_UMAX |
| 0U, // G_ATOMICRMW_UMIN |
| 0U, // G_ATOMICRMW_FADD |
| 0U, // G_ATOMICRMW_FSUB |
| 0U, // G_ATOMICRMW_FMAX |
| 0U, // G_ATOMICRMW_FMIN |
| 0U, // G_ATOMICRMW_UINC_WRAP |
| 0U, // G_ATOMICRMW_UDEC_WRAP |
| 0U, // G_FENCE |
| 0U, // G_BRCOND |
| 0U, // G_BRINDIRECT |
| 0U, // G_INVOKE_REGION_START |
| 0U, // G_INTRINSIC |
| 0U, // G_INTRINSIC_W_SIDE_EFFECTS |
| 0U, // G_ANYEXT |
| 0U, // G_TRUNC |
| 0U, // G_CONSTANT |
| 0U, // G_FCONSTANT |
| 0U, // G_VASTART |
| 0U, // G_VAARG |
| 0U, // G_SEXT |
| 0U, // G_SEXT_INREG |
| 0U, // G_ZEXT |
| 0U, // G_SHL |
| 0U, // G_LSHR |
| 0U, // G_ASHR |
| 0U, // G_FSHL |
| 0U, // G_FSHR |
| 0U, // G_ROTR |
| 0U, // G_ROTL |
| 0U, // G_ICMP |
| 0U, // G_FCMP |
| 0U, // G_SELECT |
| 0U, // G_UADDO |
| 0U, // G_UADDE |
| 0U, // G_USUBO |
| 0U, // G_USUBE |
| 0U, // G_SADDO |
| 0U, // G_SADDE |
| 0U, // G_SSUBO |
| 0U, // G_SSUBE |
| 0U, // G_UMULO |
| 0U, // G_SMULO |
| 0U, // G_UMULH |
| 0U, // G_SMULH |
| 0U, // G_UADDSAT |
| 0U, // G_SADDSAT |
| 0U, // G_USUBSAT |
| 0U, // G_SSUBSAT |
| 0U, // G_USHLSAT |
| 0U, // G_SSHLSAT |
| 0U, // G_SMULFIX |
| 0U, // G_UMULFIX |
| 0U, // G_SMULFIXSAT |
| 0U, // G_UMULFIXSAT |
| 0U, // G_SDIVFIX |
| 0U, // G_UDIVFIX |
| 0U, // G_SDIVFIXSAT |
| 0U, // G_UDIVFIXSAT |
| 0U, // G_FADD |
| 0U, // G_FSUB |
| 0U, // G_FMUL |
| 0U, // G_FMA |
| 0U, // G_FMAD |
| 0U, // G_FDIV |
| 0U, // G_FREM |
| 0U, // G_FPOW |
| 0U, // G_FPOWI |
| 0U, // G_FEXP |
| 0U, // G_FEXP2 |
| 0U, // G_FLOG |
| 0U, // G_FLOG2 |
| 0U, // G_FLOG10 |
| 0U, // G_FNEG |
| 0U, // G_FPEXT |
| 0U, // G_FPTRUNC |
| 0U, // G_FPTOSI |
| 0U, // G_FPTOUI |
| 0U, // G_SITOFP |
| 0U, // G_UITOFP |
| 0U, // G_FABS |
| 0U, // G_FCOPYSIGN |
| 0U, // G_IS_FPCLASS |
| 0U, // G_FCANONICALIZE |
| 0U, // G_FMINNUM |
| 0U, // G_FMAXNUM |
| 0U, // G_FMINNUM_IEEE |
| 0U, // G_FMAXNUM_IEEE |
| 0U, // G_FMINIMUM |
| 0U, // G_FMAXIMUM |
| 0U, // G_PTR_ADD |
| 0U, // G_PTRMASK |
| 0U, // G_SMIN |
| 0U, // G_SMAX |
| 0U, // G_UMIN |
| 0U, // G_UMAX |
| 0U, // G_ABS |
| 0U, // G_LROUND |
| 0U, // G_LLROUND |
| 0U, // G_BR |
| 0U, // G_BRJT |
| 0U, // G_INSERT_VECTOR_ELT |
| 0U, // G_EXTRACT_VECTOR_ELT |
| 0U, // G_SHUFFLE_VECTOR |
| 0U, // G_CTTZ |
| 0U, // G_CTTZ_ZERO_UNDEF |
| 0U, // G_CTLZ |
| 0U, // G_CTLZ_ZERO_UNDEF |
| 0U, // G_CTPOP |
| 0U, // G_BSWAP |
| 0U, // G_BITREVERSE |
| 0U, // G_FCEIL |
| 0U, // G_FCOS |
| 0U, // G_FSIN |
| 0U, // G_FSQRT |
| 0U, // G_FFLOOR |
| 0U, // G_FRINT |
| 0U, // G_FNEARBYINT |
| 0U, // G_ADDRSPACE_CAST |
| 0U, // G_BLOCK_ADDR |
| 0U, // G_JUMP_TABLE |
| 0U, // G_DYN_STACKALLOC |
| 0U, // G_STRICT_FADD |
| 0U, // G_STRICT_FSUB |
| 0U, // G_STRICT_FMUL |
| 0U, // G_STRICT_FDIV |
| 0U, // G_STRICT_FREM |
| 0U, // G_STRICT_FMA |
| 0U, // G_STRICT_FSQRT |
| 0U, // G_READ_REGISTER |
| 0U, // G_WRITE_REGISTER |
| 0U, // G_MEMCPY |
| 0U, // G_MEMCPY_INLINE |
| 0U, // G_MEMMOVE |
| 0U, // G_MEMSET |
| 0U, // G_BZERO |
| 0U, // G_VECREDUCE_SEQ_FADD |
| 0U, // G_VECREDUCE_SEQ_FMUL |
| 0U, // G_VECREDUCE_FADD |
| 0U, // G_VECREDUCE_FMUL |
| 0U, // G_VECREDUCE_FMAX |
| 0U, // G_VECREDUCE_FMIN |
| 0U, // G_VECREDUCE_ADD |
| 0U, // G_VECREDUCE_MUL |
| 0U, // G_VECREDUCE_AND |
| 0U, // G_VECREDUCE_OR |
| 0U, // G_VECREDUCE_XOR |
| 0U, // G_VECREDUCE_SMAX |
| 0U, // G_VECREDUCE_SMIN |
| 0U, // G_VECREDUCE_UMAX |
| 0U, // G_VECREDUCE_UMIN |
| 0U, // G_SBFX |
| 0U, // G_UBFX |
| 5U, // ADJCALLSTACKDOWN |
| 5U, // ADJCALLSTACKUP |
| 5U, // PseudoAtomicLoadAdd32 |
| 5U, // PseudoAtomicLoadAnd32 |
| 5U, // PseudoAtomicLoadNand32 |
| 5U, // PseudoAtomicLoadNand64 |
| 5U, // PseudoAtomicLoadOr32 |
| 5U, // PseudoAtomicLoadSub32 |
| 5U, // PseudoAtomicLoadXor32 |
| 5U, // PseudoAtomicStoreD |
| 5U, // PseudoAtomicStoreW |
| 5U, // PseudoAtomicSwap32 |
| 5U, // PseudoBR |
| 5U, // PseudoBRIND |
| 5U, // PseudoB_TAIL |
| 5U, // PseudoCALL |
| 5U, // PseudoCALLIndirect |
| 5U, // PseudoCmpXchg32 |
| 5U, // PseudoCmpXchg64 |
| 5U, // PseudoJIRL_CALL |
| 5U, // PseudoJIRL_TAIL |
| 6594U, // PseudoLA_ABS |
| 39362U, // PseudoLA_ABS_LARGE |
| 6612U, // PseudoLA_GOT |
| 6612U, // PseudoLA_GOT_LARGE |
| 5720U, // PseudoLA_PCREL |
| 5720U, // PseudoLA_PCREL_LARGE |
| 5359U, // PseudoLA_TLS_GD |
| 5359U, // PseudoLA_TLS_GD_LARGE |
| 5412U, // PseudoLA_TLS_IE |
| 5412U, // PseudoLA_TLS_IE_LARGE |
| 5370U, // PseudoLA_TLS_LD |
| 5370U, // PseudoLA_TLS_LD_LARGE |
| 5423U, // PseudoLA_TLS_LE |
| 5U, // PseudoLD_CFR |
| 4689U, // PseudoLI_D |
| 7156U, // PseudoLI_W |
| 5U, // PseudoMaskedAtomicLoadAdd32 |
| 5U, // PseudoMaskedAtomicLoadMax32 |
| 5U, // PseudoMaskedAtomicLoadMin32 |
| 5U, // PseudoMaskedAtomicLoadNand32 |
| 5U, // PseudoMaskedAtomicLoadSub32 |
| 5U, // PseudoMaskedAtomicLoadUMax32 |
| 5U, // PseudoMaskedAtomicLoadUMin32 |
| 5U, // PseudoMaskedAtomicSwap32 |
| 5U, // PseudoMaskedCmpXchg32 |
| 5U, // PseudoRET |
| 5U, // PseudoST_CFR |
| 5U, // PseudoTAIL |
| 5U, // PseudoTAILIndirect |
| 5U, // PseudoUNIMP |
| 5U, // RDFCSR |
| 5U, // WRFCSR |
| 4679U, // ADDI_D |
| 7146U, // ADDI_W |
| 4660U, // ADDU16I_D |
| 4387U, // ADD_D |
| 7018U, // ADD_W |
| 4814U, // ALSL_D |
| 7228U, // ALSL_W |
| 6800U, // ALSL_WU |
| 4394U, // AMADD_D |
| 4241U, // AMADD_DB_D |
| 6875U, // AMADD_DB_W |
| 7016U, // AMADD_W |
| 4429U, // AMAND_D |
| 4253U, // AMAND_DB_D |
| 6887U, // AMAND_DB_W |
| 7031U, // AMAND_W |
| 5320U, // AMMAX_D |
| 4313U, // AMMAX_DB_D |
| 6648U, // AMMAX_DB_DU |
| 6947U, // AMMAX_DB_W |
| 6752U, // AMMAX_DB_WU |
| 6696U, // AMMAX_DU |
| 7426U, // AMMAX_W |
| 6827U, // AMMAX_WU |
| 4851U, // AMMIN_D |
| 4265U, // AMMIN_DB_D |
| 6635U, // AMMIN_DB_DU |
| 6899U, // AMMIN_DB_W |
| 6739U, // AMMIN_DB_WU |
| 6678U, // AMMIN_DU |
| 7243U, // AMMIN_W |
| 6809U, // AMMIN_WU |
| 5004U, // AMOR_D |
| 4290U, // AMOR_DB_D |
| 6924U, // AMOR_DB_W |
| 7288U, // AMOR_W |
| 4898U, // AMSWAP_D |
| 4277U, // AMSWAP_DB_D |
| 6911U, // AMSWAP_DB_W |
| 7266U, // AMSWAP_W |
| 5024U, // AMXOR_D |
| 4301U, // AMXOR_DB_D |
| 6935U, // AMXOR_DB_W |
| 7296U, // AMXOR_W |
| 5388U, // AND |
| 5656U, // ANDI |
| 5760U, // ANDN |
| 5118U, // ASRTGT_D |
| 4489U, // ASRTLE_D |
| 20484U, // B |
| 7517U, // BCEQZ |
| 7495U, // BCNEZ |
| 5784U, // BEQ |
| 7511U, // BEQZ |
| 5407U, // BGE |
| 6706U, // BGEU |
| 4186U, // BITREV_4B |
| 4197U, // BITREV_8B |
| 5222U, // BITREV_D |
| 7386U, // BITREV_W |
| 22094U, // BL |
| 6602U, // BLT |
| 6727U, // BLTU |
| 5440U, // BNE |
| 7489U, // BNEZ |
| 22065U, // BREAK |
| 9184U, // BSTRINS_D |
| 11449U, // BSTRINS_W |
| 4724U, // BSTRPICK_D |
| 7191U, // BSTRPICK_W |
| 4712U, // BYTEPICK_D |
| 7179U, // BYTEPICK_W |
| 5777U, // CACOP |
| 4884U, // CLO_D |
| 7252U, // CLO_W |
| 5345U, // CLZ_D |
| 7449U, // CLZ_W |
| 5472U, // CPUCFG |
| 6852U, // CRCC_W_B_W |
| 6983U, // CRCC_W_D_W |
| 7074U, // CRCC_W_H_W |
| 7403U, // CRCC_W_W_W |
| 6864U, // CRC_W_B_W |
| 6995U, // CRC_W_D_W |
| 7086U, // CRC_W_H_W |
| 7415U, // CRC_W_W_W |
| 5400U, // CSRRD |
| 26357U, // CSRWR |
| 9576U, // CSRXCHG |
| 4891U, // CTO_D |
| 7259U, // CTO_W |
| 5352U, // CTZ_D |
| 7456U, // CTZ_W |
| 22173U, // DBAR |
| 22098U, // DBCL |
| 5233U, // DIV_D |
| 6688U, // DIV_DU |
| 7396U, // DIV_W |
| 6819U, // DIV_WU |
| 1675U, // ERTN |
| 4163U, // EXT_W_B |
| 5555U, // EXT_W_H |
| 5080U, // FABS_D |
| 6369U, // FABS_S |
| 4386U, // FADD_D |
| 5959U, // FADD_S |
| 5099U, // FCLASS_D |
| 6377U, // FCLASS_S |
| 4594U, // FCMP_CAF_D |
| 6111U, // FCMP_CAF_S |
| 4918U, // FCMP_CEQ_D |
| 6270U, // FCMP_CEQ_S |
| 4456U, // FCMP_CLE_D |
| 5993U, // FCMP_CLE_S |
| 5137U, // FCMP_CLT_D |
| 6405U, // FCMP_CLT_S |
| 4544U, // FCMP_CNE_D |
| 6061U, // FCMP_CNE_S |
| 4992U, // FCMP_COR_D |
| 6345U, // FCMP_COR_S |
| 4942U, // FCMP_CUEQ_D |
| 6294U, // FCMP_CUEQ_S |
| 4508U, // FCMP_CULE_D |
| 6035U, // FCMP_CULE_S |
| 5161U, // FCMP_CULT_D |
| 6429U, // FCMP_CULT_S |
| 4568U, // FCMP_CUNE_D |
| 6085U, // FCMP_CUNE_S |
| 4860U, // FCMP_CUN_D |
| 6236U, // FCMP_CUN_S |
| 4606U, // FCMP_SAF_D |
| 6123U, // FCMP_SAF_S |
| 4930U, // FCMP_SEQ_D |
| 6282U, // FCMP_SEQ_S |
| 4477U, // FCMP_SLE_D |
| 6014U, // FCMP_SLE_S |
| 5149U, // FCMP_SLT_D |
| 6417U, // FCMP_SLT_S |
| 4556U, // FCMP_SNE_D |
| 6073U, // FCMP_SNE_S |
| 5012U, // FCMP_SOR_D |
| 6357U, // FCMP_SOR_S |
| 4955U, // FCMP_SUEQ_D |
| 6307U, // FCMP_SUEQ_S |
| 4521U, // FCMP_SULE_D |
| 6048U, // FCMP_SULE_S |
| 5174U, // FCMP_SULT_D |
| 6442U, // FCMP_SULT_S |
| 4581U, // FCMP_SUNE_D |
| 6098U, // FCMP_SUNE_S |
| 4872U, // FCMP_SUN_D |
| 6248U, // FCMP_SUN_S |
| 4830U, // FCOPYSIGN_D |
| 6215U, // FCOPYSIGN_S |
| 5949U, // FCVT_D_S |
| 5070U, // FCVT_S_D |
| 5232U, // FDIV_D |
| 6490U, // FDIV_S |
| 5688U, // FFINT_D_L |
| 6972U, // FFINT_D_W |
| 5699U, // FFINT_S_L |
| 7342U, // FFINT_S_W |
| 5109U, // FLDGT_D |
| 6387U, // FLDGT_S |
| 4468U, // FLDLE_D |
| 6005U, // FLDLE_S |
| 5329U, // FLDX_D |
| 6578U, // FLDX_S |
| 4422U, // FLD_D |
| 5986U, // FLD_S |
| 4336U, // FLOGB_D |
| 5913U, // FLOGB_S |
| 4403U, // FMADD_D |
| 5967U, // FMADD_S |
| 4232U, // FMAXA_D |
| 5893U, // FMAXA_S |
| 5312U, // FMAX_D |
| 6570U, // FMAX_S |
| 4216U, // FMINA_D |
| 5884U, // FMINA_S |
| 4843U, // FMIN_D |
| 6228U, // FMIN_S |
| 5240U, // FMOV_D |
| 6498U, // FMOV_S |
| 4353U, // FMSUB_D |
| 5930U, // FMSUB_S |
| 4822U, // FMUL_D |
| 6207U, // FMUL_S |
| 4618U, // FNEG_D |
| 6135U, // FNEG_S |
| 4412U, // FNMADD_D |
| 5976U, // FNMADD_S |
| 4362U, // FNMSUB_D |
| 5939U, // FNMSUB_S |
| 4908U, // FRECIP_D |
| 6260U, // FRECIP_S |
| 5187U, // FRINT_D |
| 6455U, // FRINT_S |
| 5205U, // FRSQRT_D |
| 6473U, // FRSQRT_S |
| 4325U, // FSCALEB_D |
| 5902U, // FSCALEB_S |
| 5730U, // FSEL_D |
| 5730U, // FSEL_S |
| 5196U, // FSQRT_D |
| 6464U, // FSQRT_S |
| 5128U, // FSTGT_D |
| 6396U, // FSTGT_S |
| 4499U, // FSTLE_D |
| 6026U, // FSTLE_S |
| 5337U, // FSTX_D |
| 6586U, // FSTX_S |
| 5215U, // FST_D |
| 6483U, // FST_S |
| 4345U, // FSUB_D |
| 5922U, // FSUB_S |
| 4750U, // FTINTRM_L_D |
| 6157U, // FTINTRM_L_S |
| 5262U, // FTINTRM_W_D |
| 6520U, // FTINTRM_W_S |
| 4736U, // FTINTRNE_L_D |
| 6143U, // FTINTRNE_L_S |
| 5248U, // FTINTRNE_W_D |
| 6506U, // FTINTRNE_W_S |
| 4763U, // FTINTRP_L_D |
| 6170U, // FTINTRP_L_S |
| 5275U, // FTINTRP_W_D |
| 6533U, // FTINTRP_W_S |
| 4787U, // FTINTRZ_L_D |
| 6194U, // FTINTRZ_L_S |
| 5299U, // FTINTRZ_W_D |
| 6557U, // FTINTRZ_W_S |
| 4776U, // FTINT_L_D |
| 6183U, // FTINT_L_S |
| 5288U, // FTINT_W_D |
| 6546U, // FTINT_W_S |
| 22179U, // IBAR |
| 21818U, // IDLE |
| 12400U, // INVTLB |
| 4103U, // IOCSRRD_B |
| 4445U, // IOCSRRD_D |
| 5495U, // IOCSRRD_H |
| 7047U, // IOCSRRD_W |
| 4130U, // IOCSRWR_B |
| 5059U, // IOCSRWR_D |
| 5522U, // IOCSRWR_H |
| 7331U, // IOCSRWR_W |
| 5754U, // JIRL |
| 5833U, // LDDIR |
| 4141U, // LDGT_B |
| 5110U, // LDGT_D |
| 5533U, // LDGT_H |
| 7364U, // LDGT_W |
| 4114U, // LDLE_B |
| 4469U, // LDLE_D |
| 5506U, // LDLE_H |
| 7058U, // LDLE_W |
| 5445U, // LDPTE |
| 5041U, // LDPTR_D |
| 7313U, // LDPTR_W |
| 4172U, // LDX_B |
| 6627U, // LDX_BU |
| 5330U, // LDX_D |
| 5564U, // LDX_H |
| 6719U, // LDX_HU |
| 7435U, // LDX_W |
| 6837U, // LDX_WU |
| 4097U, // LD_B |
| 6620U, // LD_BU |
| 4423U, // LD_D |
| 5489U, // LD_H |
| 6712U, // LD_HU |
| 7025U, // LD_W |
| 6776U, // LD_WU |
| 4801U, // LL_D |
| 7215U, // LL_W |
| 7129U, // LU12I_W |
| 25122U, // LU32I_D |
| 4651U, // LU52I_D |
| 7524U, // MASKEQZ |
| 7502U, // MASKNEZ |
| 4438U, // MOD_D |
| 6661U, // MOD_DU |
| 7040U, // MOD_W |
| 6783U, // MOD_WU |
| 5801U, // MOVCF2FR_S |
| 5811U, // MOVCF2GR |
| 5821U, // MOVFCSR2GR |
| 5452U, // MOVFR2CF_S |
| 4980U, // MOVFR2GR_D |
| 6333U, // MOVFR2GR_S |
| 6333U, // MOVFR2GR_S_64 |
| 6320U, // MOVFRH2GR_S |
| 5462U, // MOVGR2CF |
| 5858U, // MOVGR2FCSR |
| 27596U, // MOVGR2FRH_W |
| 4968U, // MOVGR2FR_D |
| 7276U, // MOVGR2FR_W |
| 7276U, // MOVGR2FR_W_64 |
| 4626U, // MULH_D |
| 6669U, // MULH_DU |
| 7108U, // MULH_W |
| 6791U, // MULH_WU |
| 7006U, // MULW_D_W |
| 6765U, // MULW_D_WU |
| 4823U, // MUL_D |
| 7236U, // MUL_W |
| 5848U, // NOR |
| 5849U, // OR |
| 5663U, // ORI |
| 5766U, // ORN |
| 5648U, // PCADDI |
| 5626U, // PCADDU12I |
| 5637U, // PCADDU18I |
| 5615U, // PCALAU12I |
| 5381U, // PRELD |
| 7481U, // PRELDX |
| 7097U, // RDTIMEH_W |
| 7203U, // RDTIMEL_W |
| 4534U, // RDTIME_D |
| 5578U, // REVB_2H |
| 7463U, // REVB_2W |
| 5587U, // REVB_4H |
| 4372U, // REVB_D |
| 7472U, // REVH_2W |
| 4634U, // REVH_D |
| 4703U, // ROTRI_D |
| 7170U, // ROTRI_W |
| 5033U, // ROTR_D |
| 7305U, // ROTR_W |
| 8476U, // SC_D |
| 11062U, // SC_W |
| 4687U, // SLLI_D |
| 7154U, // SLLI_W |
| 4800U, // SLL_D |
| 7214U, // SLL_W |
| 6607U, // SLT |
| 5668U, // SLTI |
| 6733U, // SLTU |
| 5674U, // SLTUI |
| 4671U, // SRAI_D |
| 7138U, // SRAI_W |
| 4225U, // SRA_D |
| 6845U, // SRA_W |
| 4695U, // SRLI_D |
| 7162U, // SRLI_W |
| 4807U, // SRL_D |
| 7221U, // SRL_W |
| 4149U, // STGT_B |
| 5129U, // STGT_D |
| 5541U, // STGT_H |
| 7372U, // STGT_W |
| 4122U, // STLE_B |
| 4500U, // STLE_D |
| 5514U, // STLE_H |
| 7066U, // STLE_W |
| 5050U, // STPTR_D |
| 7322U, // STPTR_W |
| 4179U, // STX_B |
| 5338U, // STX_D |
| 5571U, // STX_H |
| 7442U, // STX_W |
| 4157U, // ST_B |
| 5216U, // ST_D |
| 5549U, // ST_H |
| 7380U, // ST_W |
| 4346U, // SUB_D |
| 6959U, // SUB_W |
| 22120U, // SYSCALL |
| 1744U, // TLBCLR |
| 1649U, // TLBFILL |
| 1509U, // TLBFLUSH |
| 1297U, // TLBRD |
| 1500U, // TLBSRCH |
| 1774U, // TLBWR |
| 5853U, // XOR |
| 5662U, // XORI |
| }; |
| |
| static const uint8_t OpInfo1[] = { |
| 0U, // PHI |
| 0U, // INLINEASM |
| 0U, // INLINEASM_BR |
| 0U, // CFI_INSTRUCTION |
| 0U, // EH_LABEL |
| 0U, // GC_LABEL |
| 0U, // ANNOTATION_LABEL |
| 0U, // KILL |
| 0U, // EXTRACT_SUBREG |
| 0U, // INSERT_SUBREG |
| 0U, // IMPLICIT_DEF |
| 0U, // SUBREG_TO_REG |
| 0U, // COPY_TO_REGCLASS |
| 0U, // DBG_VALUE |
| 0U, // DBG_VALUE_LIST |
| 0U, // DBG_INSTR_REF |
| 0U, // DBG_PHI |
| 0U, // DBG_LABEL |
| 0U, // REG_SEQUENCE |
| 0U, // COPY |
| 0U, // BUNDLE |
| 0U, // LIFETIME_START |
| 0U, // LIFETIME_END |
| 0U, // PSEUDO_PROBE |
| 0U, // ARITH_FENCE |
| 0U, // STACKMAP |
| 0U, // FENTRY_CALL |
| 0U, // PATCHPOINT |
| 0U, // LOAD_STACK_GUARD |
| 0U, // PREALLOCATED_SETUP |
| 0U, // PREALLOCATED_ARG |
| 0U, // STATEPOINT |
| 0U, // LOCAL_ESCAPE |
| 0U, // FAULTING_OP |
| 0U, // PATCHABLE_OP |
| 0U, // PATCHABLE_FUNCTION_ENTER |
| 0U, // PATCHABLE_RET |
| 0U, // PATCHABLE_FUNCTION_EXIT |
| 0U, // PATCHABLE_TAIL_CALL |
| 0U, // PATCHABLE_EVENT_CALL |
| 0U, // PATCHABLE_TYPED_EVENT_CALL |
| 0U, // ICALL_BRANCH_FUNNEL |
| 0U, // MEMBARRIER |
| 0U, // G_ASSERT_SEXT |
| 0U, // G_ASSERT_ZEXT |
| 0U, // G_ASSERT_ALIGN |
| 0U, // G_ADD |
| 0U, // G_SUB |
| 0U, // G_MUL |
| 0U, // G_SDIV |
| 0U, // G_UDIV |
| 0U, // G_SREM |
| 0U, // G_UREM |
| 0U, // G_SDIVREM |
| 0U, // G_UDIVREM |
| 0U, // G_AND |
| 0U, // G_OR |
| 0U, // G_XOR |
| 0U, // G_IMPLICIT_DEF |
| 0U, // G_PHI |
| 0U, // G_FRAME_INDEX |
| 0U, // G_GLOBAL_VALUE |
| 0U, // G_EXTRACT |
| 0U, // G_UNMERGE_VALUES |
| 0U, // G_INSERT |
| 0U, // G_MERGE_VALUES |
| 0U, // G_BUILD_VECTOR |
| 0U, // G_BUILD_VECTOR_TRUNC |
| 0U, // G_CONCAT_VECTORS |
| 0U, // G_PTRTOINT |
| 0U, // G_INTTOPTR |
| 0U, // G_BITCAST |
| 0U, // G_FREEZE |
| 0U, // G_INTRINSIC_FPTRUNC_ROUND |
| 0U, // G_INTRINSIC_TRUNC |
| 0U, // G_INTRINSIC_ROUND |
| 0U, // G_INTRINSIC_LRINT |
| 0U, // G_INTRINSIC_ROUNDEVEN |
| 0U, // G_READCYCLECOUNTER |
| 0U, // G_LOAD |
| 0U, // G_SEXTLOAD |
| 0U, // G_ZEXTLOAD |
| 0U, // G_INDEXED_LOAD |
| 0U, // G_INDEXED_SEXTLOAD |
| 0U, // G_INDEXED_ZEXTLOAD |
| 0U, // G_STORE |
| 0U, // G_INDEXED_STORE |
| 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS |
| 0U, // G_ATOMIC_CMPXCHG |
| 0U, // G_ATOMICRMW_XCHG |
| 0U, // G_ATOMICRMW_ADD |
| 0U, // G_ATOMICRMW_SUB |
| 0U, // G_ATOMICRMW_AND |
| 0U, // G_ATOMICRMW_NAND |
| 0U, // G_ATOMICRMW_OR |
| 0U, // G_ATOMICRMW_XOR |
| 0U, // G_ATOMICRMW_MAX |
| 0U, // G_ATOMICRMW_MIN |
| 0U, // G_ATOMICRMW_UMAX |
| 0U, // G_ATOMICRMW_UMIN |
| 0U, // G_ATOMICRMW_FADD |
| 0U, // G_ATOMICRMW_FSUB |
| 0U, // G_ATOMICRMW_FMAX |
| 0U, // G_ATOMICRMW_FMIN |
| 0U, // G_ATOMICRMW_UINC_WRAP |
| 0U, // G_ATOMICRMW_UDEC_WRAP |
| 0U, // G_FENCE |
| 0U, // G_BRCOND |
| 0U, // G_BRINDIRECT |
| 0U, // G_INVOKE_REGION_START |
| 0U, // G_INTRINSIC |
| 0U, // G_INTRINSIC_W_SIDE_EFFECTS |
| 0U, // G_ANYEXT |
| 0U, // G_TRUNC |
| 0U, // G_CONSTANT |
| 0U, // G_FCONSTANT |
| 0U, // G_VASTART |
| 0U, // G_VAARG |
| 0U, // G_SEXT |
| 0U, // G_SEXT_INREG |
| 0U, // G_ZEXT |
| 0U, // G_SHL |
| 0U, // G_LSHR |
| 0U, // G_ASHR |
| 0U, // G_FSHL |
| 0U, // G_FSHR |
| 0U, // G_ROTR |
| 0U, // G_ROTL |
| 0U, // G_ICMP |
| 0U, // G_FCMP |
| 0U, // G_SELECT |
| 0U, // G_UADDO |
| 0U, // G_UADDE |
| 0U, // G_USUBO |
| 0U, // G_USUBE |
| 0U, // G_SADDO |
| 0U, // G_SADDE |
| 0U, // G_SSUBO |
| 0U, // G_SSUBE |
| 0U, // G_UMULO |
| 0U, // G_SMULO |
| 0U, // G_UMULH |
| 0U, // G_SMULH |
| 0U, // G_UADDSAT |
| 0U, // G_SADDSAT |
| 0U, // G_USUBSAT |
| 0U, // G_SSUBSAT |
| 0U, // G_USHLSAT |
| 0U, // G_SSHLSAT |
| 0U, // G_SMULFIX |
| 0U, // G_UMULFIX |
| 0U, // G_SMULFIXSAT |
| 0U, // G_UMULFIXSAT |
| 0U, // G_SDIVFIX |
| 0U, // G_UDIVFIX |
| 0U, // G_SDIVFIXSAT |
| 0U, // G_UDIVFIXSAT |
| 0U, // G_FADD |
| 0U, // G_FSUB |
| 0U, // G_FMUL |
| 0U, // G_FMA |
| 0U, // G_FMAD |
| 0U, // G_FDIV |
| 0U, // G_FREM |
| 0U, // G_FPOW |
| 0U, // G_FPOWI |
| 0U, // G_FEXP |
| 0U, // G_FEXP2 |
| 0U, // G_FLOG |
| 0U, // G_FLOG2 |
| 0U, // G_FLOG10 |
| 0U, // G_FNEG |
| 0U, // G_FPEXT |
| 0U, // G_FPTRUNC |
| 0U, // G_FPTOSI |
| 0U, // G_FPTOUI |
| 0U, // G_SITOFP |
| 0U, // G_UITOFP |
| 0U, // G_FABS |
| 0U, // G_FCOPYSIGN |
| 0U, // G_IS_FPCLASS |
| 0U, // G_FCANONICALIZE |
| 0U, // G_FMINNUM |
| 0U, // G_FMAXNUM |
| 0U, // G_FMINNUM_IEEE |
| 0U, // G_FMAXNUM_IEEE |
| 0U, // G_FMINIMUM |
| 0U, // G_FMAXIMUM |
| 0U, // G_PTR_ADD |
| 0U, // G_PTRMASK |
| 0U, // G_SMIN |
| 0U, // G_SMAX |
| 0U, // G_UMIN |
| 0U, // G_UMAX |
| 0U, // G_ABS |
| 0U, // G_LROUND |
| 0U, // G_LLROUND |
| 0U, // G_BR |
| 0U, // G_BRJT |
| 0U, // G_INSERT_VECTOR_ELT |
| 0U, // G_EXTRACT_VECTOR_ELT |
| 0U, // G_SHUFFLE_VECTOR |
| 0U, // G_CTTZ |
| 0U, // G_CTTZ_ZERO_UNDEF |
| 0U, // G_CTLZ |
| 0U, // G_CTLZ_ZERO_UNDEF |
| 0U, // G_CTPOP |
| 0U, // G_BSWAP |
| 0U, // G_BITREVERSE |
| 0U, // G_FCEIL |
| 0U, // G_FCOS |
| 0U, // G_FSIN |
| 0U, // G_FSQRT |
| 0U, // G_FFLOOR |
| 0U, // G_FRINT |
| 0U, // G_FNEARBYINT |
| 0U, // G_ADDRSPACE_CAST |
| 0U, // G_BLOCK_ADDR |
| 0U, // G_JUMP_TABLE |
| 0U, // G_DYN_STACKALLOC |
| 0U, // G_STRICT_FADD |
| 0U, // G_STRICT_FSUB |
| 0U, // G_STRICT_FMUL |
| 0U, // G_STRICT_FDIV |
| 0U, // G_STRICT_FREM |
| 0U, // G_STRICT_FMA |
| 0U, // G_STRICT_FSQRT |
| 0U, // G_READ_REGISTER |
| 0U, // G_WRITE_REGISTER |
| 0U, // G_MEMCPY |
| 0U, // G_MEMCPY_INLINE |
| 0U, // G_MEMMOVE |
| 0U, // G_MEMSET |
| 0U, // G_BZERO |
| 0U, // G_VECREDUCE_SEQ_FADD |
| 0U, // G_VECREDUCE_SEQ_FMUL |
| 0U, // G_VECREDUCE_FADD |
| 0U, // G_VECREDUCE_FMUL |
| 0U, // G_VECREDUCE_FMAX |
| 0U, // G_VECREDUCE_FMIN |
| 0U, // G_VECREDUCE_ADD |
| 0U, // G_VECREDUCE_MUL |
| 0U, // G_VECREDUCE_AND |
| 0U, // G_VECREDUCE_OR |
| 0U, // G_VECREDUCE_XOR |
| 0U, // G_VECREDUCE_SMAX |
| 0U, // G_VECREDUCE_SMIN |
| 0U, // G_VECREDUCE_UMAX |
| 0U, // G_VECREDUCE_UMIN |
| 0U, // G_SBFX |
| 0U, // G_UBFX |
| 0U, // ADJCALLSTACKDOWN |
| 0U, // ADJCALLSTACKUP |
| 0U, // PseudoAtomicLoadAdd32 |
| 0U, // PseudoAtomicLoadAnd32 |
| 0U, // PseudoAtomicLoadNand32 |
| 0U, // PseudoAtomicLoadNand64 |
| 0U, // PseudoAtomicLoadOr32 |
| 0U, // PseudoAtomicLoadSub32 |
| 0U, // PseudoAtomicLoadXor32 |
| 0U, // PseudoAtomicStoreD |
| 0U, // PseudoAtomicStoreW |
| 0U, // PseudoAtomicSwap32 |
| 0U, // PseudoBR |
| 0U, // PseudoBRIND |
| 0U, // PseudoB_TAIL |
| 0U, // PseudoCALL |
| 0U, // PseudoCALLIndirect |
| 0U, // PseudoCmpXchg32 |
| 0U, // PseudoCmpXchg64 |
| 0U, // PseudoJIRL_CALL |
| 0U, // PseudoJIRL_TAIL |
| 0U, // PseudoLA_ABS |
| 0U, // PseudoLA_ABS_LARGE |
| 0U, // PseudoLA_GOT |
| 2U, // PseudoLA_GOT_LARGE |
| 0U, // PseudoLA_PCREL |
| 2U, // PseudoLA_PCREL_LARGE |
| 0U, // PseudoLA_TLS_GD |
| 2U, // PseudoLA_TLS_GD_LARGE |
| 0U, // PseudoLA_TLS_IE |
| 2U, // PseudoLA_TLS_IE_LARGE |
| 0U, // PseudoLA_TLS_LD |
| 2U, // PseudoLA_TLS_LD_LARGE |
| 0U, // PseudoLA_TLS_LE |
| 0U, // PseudoLD_CFR |
| 0U, // PseudoLI_D |
| 0U, // PseudoLI_W |
| 0U, // PseudoMaskedAtomicLoadAdd32 |
| 0U, // PseudoMaskedAtomicLoadMax32 |
| 0U, // PseudoMaskedAtomicLoadMin32 |
| 0U, // PseudoMaskedAtomicLoadNand32 |
| 0U, // PseudoMaskedAtomicLoadSub32 |
| 0U, // PseudoMaskedAtomicLoadUMax32 |
| 0U, // PseudoMaskedAtomicLoadUMin32 |
| 0U, // PseudoMaskedAtomicSwap32 |
| 0U, // PseudoMaskedCmpXchg32 |
| 0U, // PseudoRET |
| 0U, // PseudoST_CFR |
| 0U, // PseudoTAIL |
| 0U, // PseudoTAILIndirect |
| 0U, // PseudoUNIMP |
| 0U, // RDFCSR |
| 0U, // WRFCSR |
| 2U, // ADDI_D |
| 2U, // ADDI_W |
| 2U, // ADDU16I_D |
| 2U, // ADD_D |
| 2U, // ADD_W |
| 18U, // ALSL_D |
| 18U, // ALSL_W |
| 18U, // ALSL_WU |
| 6U, // AMADD_D |
| 6U, // AMADD_DB_D |
| 6U, // AMADD_DB_W |
| 6U, // AMADD_W |
| 6U, // AMAND_D |
| 6U, // AMAND_DB_D |
| 6U, // AMAND_DB_W |
| 6U, // AMAND_W |
| 6U, // AMMAX_D |
| 6U, // AMMAX_DB_D |
| 6U, // AMMAX_DB_DU |
| 6U, // AMMAX_DB_W |
| 6U, // AMMAX_DB_WU |
| 6U, // AMMAX_DU |
| 6U, // AMMAX_W |
| 6U, // AMMAX_WU |
| 6U, // AMMIN_D |
| 6U, // AMMIN_DB_D |
| 6U, // AMMIN_DB_DU |
| 6U, // AMMIN_DB_W |
| 6U, // AMMIN_DB_WU |
| 6U, // AMMIN_DU |
| 6U, // AMMIN_W |
| 6U, // AMMIN_WU |
| 6U, // AMOR_D |
| 6U, // AMOR_DB_D |
| 6U, // AMOR_DB_W |
| 6U, // AMOR_W |
| 6U, // AMSWAP_D |
| 6U, // AMSWAP_DB_D |
| 6U, // AMSWAP_DB_W |
| 6U, // AMSWAP_W |
| 6U, // AMXOR_D |
| 6U, // AMXOR_DB_D |
| 6U, // AMXOR_DB_W |
| 6U, // AMXOR_W |
| 2U, // AND |
| 2U, // ANDI |
| 2U, // ANDN |
| 0U, // ASRTGT_D |
| 0U, // ASRTLE_D |
| 0U, // B |
| 0U, // BCEQZ |
| 0U, // BCNEZ |
| 2U, // BEQ |
| 0U, // BEQZ |
| 2U, // BGE |
| 2U, // BGEU |
| 0U, // BITREV_4B |
| 0U, // BITREV_8B |
| 0U, // BITREV_D |
| 0U, // BITREV_W |
| 0U, // BL |
| 2U, // BLT |
| 2U, // BLTU |
| 2U, // BNE |
| 0U, // BNEZ |
| 0U, // BREAK |
| 11U, // BSTRINS_D |
| 11U, // BSTRINS_W |
| 18U, // BSTRPICK_D |
| 18U, // BSTRPICK_W |
| 18U, // BYTEPICK_D |
| 18U, // BYTEPICK_W |
| 2U, // CACOP |
| 0U, // CLO_D |
| 0U, // CLO_W |
| 0U, // CLZ_D |
| 0U, // CLZ_W |
| 0U, // CPUCFG |
| 2U, // CRCC_W_B_W |
| 2U, // CRCC_W_D_W |
| 2U, // CRCC_W_H_W |
| 2U, // CRCC_W_W_W |
| 2U, // CRC_W_B_W |
| 2U, // CRC_W_D_W |
| 2U, // CRC_W_H_W |
| 2U, // CRC_W_W_W |
| 0U, // CSRRD |
| 0U, // CSRWR |
| 1U, // CSRXCHG |
| 0U, // CTO_D |
| 0U, // CTO_W |
| 0U, // CTZ_D |
| 0U, // CTZ_W |
| 0U, // DBAR |
| 0U, // DBCL |
| 2U, // DIV_D |
| 2U, // DIV_DU |
| 2U, // DIV_W |
| 2U, // DIV_WU |
| 0U, // ERTN |
| 0U, // EXT_W_B |
| 0U, // EXT_W_H |
| 0U, // FABS_D |
| 0U, // FABS_S |
| 2U, // FADD_D |
| 2U, // FADD_S |
| 0U, // FCLASS_D |
| 0U, // FCLASS_S |
| 2U, // FCMP_CAF_D |
| 2U, // FCMP_CAF_S |
| 2U, // FCMP_CEQ_D |
| 2U, // FCMP_CEQ_S |
| 2U, // FCMP_CLE_D |
| 2U, // FCMP_CLE_S |
| 2U, // FCMP_CLT_D |
| 2U, // FCMP_CLT_S |
| 2U, // FCMP_CNE_D |
| 2U, // FCMP_CNE_S |
| 2U, // FCMP_COR_D |
| 2U, // FCMP_COR_S |
| 2U, // FCMP_CUEQ_D |
| 2U, // FCMP_CUEQ_S |
| 2U, // FCMP_CULE_D |
| 2U, // FCMP_CULE_S |
| 2U, // FCMP_CULT_D |
| 2U, // FCMP_CULT_S |
| 2U, // FCMP_CUNE_D |
| 2U, // FCMP_CUNE_S |
| 2U, // FCMP_CUN_D |
| 2U, // FCMP_CUN_S |
| 2U, // FCMP_SAF_D |
| 2U, // FCMP_SAF_S |
| 2U, // FCMP_SEQ_D |
| 2U, // FCMP_SEQ_S |
| 2U, // FCMP_SLE_D |
| 2U, // FCMP_SLE_S |
| 2U, // FCMP_SLT_D |
| 2U, // FCMP_SLT_S |
| 2U, // FCMP_SNE_D |
| 2U, // FCMP_SNE_S |
| 2U, // FCMP_SOR_D |
| 2U, // FCMP_SOR_S |
| 2U, // FCMP_SUEQ_D |
| 2U, // FCMP_SUEQ_S |
| 2U, // FCMP_SULE_D |
| 2U, // FCMP_SULE_S |
| 2U, // FCMP_SULT_D |
| 2U, // FCMP_SULT_S |
| 2U, // FCMP_SUNE_D |
| 2U, // FCMP_SUNE_S |
| 2U, // FCMP_SUN_D |
| 2U, // FCMP_SUN_S |
| 2U, // FCOPYSIGN_D |
| 2U, // FCOPYSIGN_S |
| 0U, // FCVT_D_S |
| 0U, // FCVT_S_D |
| 2U, // FDIV_D |
| 2U, // FDIV_S |
| 0U, // FFINT_D_L |
| 0U, // FFINT_D_W |
| 0U, // FFINT_S_L |
| 0U, // FFINT_S_W |
| 2U, // FLDGT_D |
| 2U, // FLDGT_S |
| 2U, // FLDLE_D |
| 2U, // FLDLE_S |
| 2U, // FLDX_D |
| 2U, // FLDX_S |
| 2U, // FLD_D |
| 2U, // FLD_S |
| 0U, // FLOGB_D |
| 0U, // FLOGB_S |
| 18U, // FMADD_D |
| 18U, // FMADD_S |
| 2U, // FMAXA_D |
| 2U, // FMAXA_S |
| 2U, // FMAX_D |
| 2U, // FMAX_S |
| 2U, // FMINA_D |
| 2U, // FMINA_S |
| 2U, // FMIN_D |
| 2U, // FMIN_S |
| 0U, // FMOV_D |
| 0U, // FMOV_S |
| 18U, // FMSUB_D |
| 18U, // FMSUB_S |
| 2U, // FMUL_D |
| 2U, // FMUL_S |
| 0U, // FNEG_D |
| 0U, // FNEG_S |
| 18U, // FNMADD_D |
| 18U, // FNMADD_S |
| 18U, // FNMSUB_D |
| 18U, // FNMSUB_S |
| 0U, // FRECIP_D |
| 0U, // FRECIP_S |
| 0U, // FRINT_D |
| 0U, // FRINT_S |
| 0U, // FRSQRT_D |
| 0U, // FRSQRT_S |
| 2U, // FSCALEB_D |
| 2U, // FSCALEB_S |
| 18U, // FSEL_D |
| 18U, // FSEL_S |
| 0U, // FSQRT_D |
| 0U, // FSQRT_S |
| 2U, // FSTGT_D |
| 2U, // FSTGT_S |
| 2U, // FSTLE_D |
| 2U, // FSTLE_S |
| 2U, // FSTX_D |
| 2U, // FSTX_S |
| 2U, // FST_D |
| 2U, // FST_S |
| 2U, // FSUB_D |
| 2U, // FSUB_S |
| 0U, // FTINTRM_L_D |
| 0U, // FTINTRM_L_S |
| 0U, // FTINTRM_W_D |
| 0U, // FTINTRM_W_S |
| 0U, // FTINTRNE_L_D |
| 0U, // FTINTRNE_L_S |
| 0U, // FTINTRNE_W_D |
| 0U, // FTINTRNE_W_S |
| 0U, // FTINTRP_L_D |
| 0U, // FTINTRP_L_S |
| 0U, // FTINTRP_W_D |
| 0U, // FTINTRP_W_S |
| 0U, // FTINTRZ_L_D |
| 0U, // FTINTRZ_L_S |
| 0U, // FTINTRZ_W_D |
| 0U, // FTINTRZ_W_S |
| 0U, // FTINT_L_D |
| 0U, // FTINT_L_S |
| 0U, // FTINT_W_D |
| 0U, // FTINT_W_S |
| 0U, // IBAR |
| 0U, // IDLE |
| 0U, // INVTLB |
| 0U, // IOCSRRD_B |
| 0U, // IOCSRRD_D |
| 0U, // IOCSRRD_H |
| 0U, // IOCSRRD_W |
| 0U, // IOCSRWR_B |
| 0U, // IOCSRWR_D |
| 0U, // IOCSRWR_H |
| 0U, // IOCSRWR_W |
| 2U, // JIRL |
| 2U, // LDDIR |
| 2U, // LDGT_B |
| 2U, // LDGT_D |
| 2U, // LDGT_H |
| 2U, // LDGT_W |
| 2U, // LDLE_B |
| 2U, // LDLE_D |
| 2U, // LDLE_H |
| 2U, // LDLE_W |
| 0U, // LDPTE |
| 2U, // LDPTR_D |
| 2U, // LDPTR_W |
| 2U, // LDX_B |
| 2U, // LDX_BU |
| 2U, // LDX_D |
| 2U, // LDX_H |
| 2U, // LDX_HU |
| 2U, // LDX_W |
| 2U, // LDX_WU |
| 2U, // LD_B |
| 2U, // LD_BU |
| 2U, // LD_D |
| 2U, // LD_H |
| 2U, // LD_HU |
| 2U, // LD_W |
| 2U, // LD_WU |
| 2U, // LL_D |
| 2U, // LL_W |
| 0U, // LU12I_W |
| 0U, // LU32I_D |
| 2U, // LU52I_D |
| 2U, // MASKEQZ |
| 2U, // MASKNEZ |
| 2U, // MOD_D |
| 2U, // MOD_DU |
| 2U, // MOD_W |
| 2U, // MOD_WU |
| 0U, // MOVCF2FR_S |
| 0U, // MOVCF2GR |
| 0U, // MOVFCSR2GR |
| 0U, // MOVFR2CF_S |
| 0U, // MOVFR2GR_D |
| 0U, // MOVFR2GR_S |
| 0U, // MOVFR2GR_S_64 |
| 0U, // MOVFRH2GR_S |
| 0U, // MOVGR2CF |
| 0U, // MOVGR2FCSR |
| 0U, // MOVGR2FRH_W |
| 0U, // MOVGR2FR_D |
| 0U, // MOVGR2FR_W |
| 0U, // MOVGR2FR_W_64 |
| 2U, // MULH_D |
| 2U, // MULH_DU |
| 2U, // MULH_W |
| 2U, // MULH_WU |
| 2U, // MULW_D_W |
| 2U, // MULW_D_WU |
| 2U, // MUL_D |
| 2U, // MUL_W |
| 2U, // NOR |
| 2U, // OR |
| 2U, // ORI |
| 2U, // ORN |
| 0U, // PCADDI |
| 0U, // PCADDU12I |
| 0U, // PCADDU18I |
| 0U, // PCALAU12I |
| 2U, // PRELD |
| 2U, // PRELDX |
| 0U, // RDTIMEH_W |
| 0U, // RDTIMEL_W |
| 0U, // RDTIME_D |
| 0U, // REVB_2H |
| 0U, // REVB_2W |
| 0U, // REVB_4H |
| 0U, // REVB_D |
| 0U, // REVH_2W |
| 0U, // REVH_D |
| 2U, // ROTRI_D |
| 2U, // ROTRI_W |
| 2U, // ROTR_D |
| 2U, // ROTR_W |
| 1U, // SC_D |
| 1U, // SC_W |
| 2U, // SLLI_D |
| 2U, // SLLI_W |
| 2U, // SLL_D |
| 2U, // SLL_W |
| 2U, // SLT |
| 2U, // SLTI |
| 2U, // SLTU |
| 2U, // SLTUI |
| 2U, // SRAI_D |
| 2U, // SRAI_W |
| 2U, // SRA_D |
| 2U, // SRA_W |
| 2U, // SRLI_D |
| 2U, // SRLI_W |
| 2U, // SRL_D |
| 2U, // SRL_W |
| 2U, // STGT_B |
| 2U, // STGT_D |
| 2U, // STGT_H |
| 2U, // STGT_W |
| 2U, // STLE_B |
| 2U, // STLE_D |
| 2U, // STLE_H |
| 2U, // STLE_W |
| 2U, // STPTR_D |
| 2U, // STPTR_W |
| 2U, // STX_B |
| 2U, // STX_D |
| 2U, // STX_H |
| 2U, // STX_W |
| 2U, // ST_B |
| 2U, // ST_D |
| 2U, // ST_H |
| 2U, // ST_W |
| 2U, // SUB_D |
| 2U, // SUB_W |
| 0U, // SYSCALL |
| 0U, // TLBCLR |
| 0U, // TLBFILL |
| 0U, // TLBFLUSH |
| 0U, // TLBRD |
| 0U, // TLBSRCH |
| 0U, // TLBWR |
| 2U, // XOR |
| 2U, // XORI |
| }; |
| |
| // Emit the opcode for the instruction. |
| uint32_t Bits = 0; |
| Bits |= OpInfo0[MI->getOpcode()] << 0; |
| Bits |= OpInfo1[MI->getOpcode()] << 16; |
| return {AsmStrs+(Bits & 4095)-1, Bits}; |
| |
| } |
| /// printInstruction - This method is automatically generated by tablegen |
| /// from the instruction set description. |
| LLVM_NO_PROFILE_INSTRUMENT_FUNCTION |
| void LoongArchInstPrinter::printInstruction(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &O) { |
| O << "\t"; |
| |
| auto MnemonicInfo = getMnemonic(MI); |
| |
| O << MnemonicInfo.first; |
| |
| uint32_t Bits = MnemonicInfo.second; |
| assert(Bits != 0 && "Cannot print this instruction."); |
| |
| // Fragment 0 encoded into 2 bits for 4 unique commands. |
| switch ((Bits >> 12) & 3) { |
| default: llvm_unreachable("Invalid command number."); |
| case 0: |
| // DBG_VALUE, DBG_VALUE_LIST, DBG_INSTR_REF, DBG_PHI, DBG_LABEL, BUNDLE, ... |
| return; |
| break; |
| case 1: |
| // PseudoLA_ABS, PseudoLA_ABS_LARGE, PseudoLA_GOT, PseudoLA_GOT_LARGE, Ps... |
| printOperand(MI, 0, STI, O); |
| break; |
| case 2: |
| // BSTRINS_D, BSTRINS_W, CSRWR, CSRXCHG, LU32I_D, MOVGR2FRH_W, SC_D, SC_W |
| printOperand(MI, 1, STI, O); |
| O << ", "; |
| printOperand(MI, 2, STI, O); |
| break; |
| case 3: |
| // INVTLB |
| printOperand(MI, 2, STI, O); |
| O << ", "; |
| printOperand(MI, 1, STI, O); |
| O << ", "; |
| printOperand(MI, 0, STI, O); |
| return; |
| break; |
| } |
| |
| |
| // Fragment 1 encoded into 1 bits for 2 unique commands. |
| if ((Bits >> 14) & 1) { |
| // B, BL, BREAK, CSRWR, DBAR, DBCL, IBAR, IDLE, LU32I_D, MOVGR2FRH_W, SYS... |
| return; |
| } else { |
| // PseudoLA_ABS, PseudoLA_ABS_LARGE, PseudoLA_GOT, PseudoLA_GOT_LARGE, Ps... |
| O << ", "; |
| } |
| |
| |
| // Fragment 2 encoded into 2 bits for 3 unique commands. |
| switch ((Bits >> 15) & 3) { |
| default: llvm_unreachable("Invalid command number."); |
| case 0: |
| // PseudoLA_ABS, PseudoLA_GOT, PseudoLA_GOT_LARGE, PseudoLA_PCREL, Pseudo... |
| printOperand(MI, 1, STI, O); |
| break; |
| case 1: |
| // PseudoLA_ABS_LARGE |
| printOperand(MI, 2, STI, O); |
| return; |
| break; |
| case 2: |
| // BSTRINS_D, BSTRINS_W, CSRXCHG, SC_D, SC_W |
| printOperand(MI, 3, STI, O); |
| break; |
| } |
| |
| |
| // Fragment 3 encoded into 1 bits for 2 unique commands. |
| if ((Bits >> 17) & 1) { |
| // PseudoLA_GOT_LARGE, PseudoLA_PCREL_LARGE, PseudoLA_TLS_GD_LARGE, Pseud... |
| O << ", "; |
| } else { |
| // PseudoLA_ABS, PseudoLA_GOT, PseudoLA_PCREL, PseudoLA_TLS_GD, PseudoLA_... |
| return; |
| } |
| |
| |
| // Fragment 4 encoded into 2 bits for 3 unique commands. |
| switch ((Bits >> 18) & 3) { |
| default: llvm_unreachable("Invalid command number."); |
| case 0: |
| // PseudoLA_GOT_LARGE, PseudoLA_PCREL_LARGE, PseudoLA_TLS_GD_LARGE, Pseud... |
| printOperand(MI, 2, STI, O); |
| break; |
| case 1: |
| // AMADD_D, AMADD_DB_D, AMADD_DB_W, AMADD_W, AMAND_D, AMAND_DB_D, AMAND_D... |
| printAtomicMemOp(MI, 2, STI, O); |
| return; |
| break; |
| case 2: |
| // BSTRINS_D, BSTRINS_W |
| printOperand(MI, 4, STI, O); |
| return; |
| break; |
| } |
| |
| |
| // Fragment 5 encoded into 1 bits for 2 unique commands. |
| if ((Bits >> 20) & 1) { |
| // ALSL_D, ALSL_W, ALSL_WU, BSTRPICK_D, BSTRPICK_W, BYTEPICK_D, BYTEPICK_... |
| O << ", "; |
| printOperand(MI, 3, STI, O); |
| return; |
| } else { |
| // PseudoLA_GOT_LARGE, PseudoLA_PCREL_LARGE, PseudoLA_TLS_GD_LARGE, Pseud... |
| return; |
| } |
| |
| } |
| |
| |
| /// getRegisterName - This method is automatically generated by tblgen |
| /// from the register set description. This returns the assembler name |
| /// for the specified register. |
| const char *LoongArchInstPrinter:: |
| getRegisterName(MCRegister Reg, unsigned AltIdx) { |
| unsigned RegNo = Reg.id(); |
| assert(RegNo && RegNo < 109 && "Invalid register number!"); |
| |
| |
| #ifdef __GNUC__ |
| #pragma GCC diagnostic push |
| #pragma GCC diagnostic ignored "-Woverlength-strings" |
| #endif |
| static const char AsmStrsNoRegAltName[] = { |
| /* 0 */ "f10\0" |
| /* 4 */ "r10\0" |
| /* 8 */ "f20\0" |
| /* 12 */ "r20\0" |
| /* 16 */ "f30\0" |
| /* 20 */ "r30\0" |
| /* 24 */ "fcc0\0" |
| /* 29 */ "f0\0" |
| /* 32 */ "fcsr0\0" |
| /* 38 */ "f11\0" |
| /* 42 */ "r11\0" |
| /* 46 */ "f21\0" |
| /* 50 */ "r21\0" |
| /* 54 */ "f31\0" |
| /* 58 */ "r31\0" |
| /* 62 */ "fcc1\0" |
| /* 67 */ "f1\0" |
| /* 70 */ "fcsr1\0" |
| /* 76 */ "f12\0" |
| /* 80 */ "r12\0" |
| /* 84 */ "f22\0" |
| /* 88 */ "r22\0" |
| /* 92 */ "fcc2\0" |
| /* 97 */ "f2\0" |
| /* 100 */ "fcsr2\0" |
| /* 106 */ "f13\0" |
| /* 110 */ "r13\0" |
| /* 114 */ "f23\0" |
| /* 118 */ "r23\0" |
| /* 122 */ "fcc3\0" |
| /* 127 */ "f3\0" |
| /* 130 */ "fcsr3\0" |
| /* 136 */ "f14\0" |
| /* 140 */ "r14\0" |
| /* 144 */ "f24\0" |
| /* 148 */ "r24\0" |
| /* 152 */ "fcc4\0" |
| /* 157 */ "f4\0" |
| /* 160 */ "r4\0" |
| /* 163 */ "f15\0" |
| /* 167 */ "r15\0" |
| /* 171 */ "f25\0" |
| /* 175 */ "r25\0" |
| /* 179 */ "fcc5\0" |
| /* 184 */ "f5\0" |
| /* 187 */ "r5\0" |
| /* 190 */ "f16\0" |
| /* 194 */ "r16\0" |
| /* 198 */ "f26\0" |
| /* 202 */ "r26\0" |
| /* 206 */ "fcc6\0" |
| /* 211 */ "f6\0" |
| /* 214 */ "r6\0" |
| /* 217 */ "f17\0" |
| /* 221 */ "r17\0" |
| /* 225 */ "f27\0" |
| /* 229 */ "r27\0" |
| /* 233 */ "fcc7\0" |
| /* 238 */ "f7\0" |
| /* 241 */ "r7\0" |
| /* 244 */ "f18\0" |
| /* 248 */ "r18\0" |
| /* 252 */ "f28\0" |
| /* 256 */ "r28\0" |
| /* 260 */ "f8\0" |
| /* 263 */ "r8\0" |
| /* 266 */ "f19\0" |
| /* 270 */ "r19\0" |
| /* 274 */ "f29\0" |
| /* 278 */ "r29\0" |
| /* 282 */ "f9\0" |
| /* 285 */ "r9\0" |
| }; |
| #ifdef __GNUC__ |
| #pragma GCC diagnostic pop |
| #endif |
| |
| static const uint16_t RegAsmOffsetNoRegAltName[] = { |
| 29, 67, 97, 127, 157, 184, 211, 238, 260, 282, 0, 38, 76, 106, |
| 136, 163, 190, 217, 244, 266, 8, 46, 84, 114, 144, 171, 198, 225, |
| 252, 274, 16, 54, 24, 62, 92, 122, 152, 179, 206, 233, 32, 70, |
| 100, 130, 35, 73, 103, 133, 160, 187, 214, 241, 263, 285, 4, 42, |
| 80, 110, 140, 167, 194, 221, 248, 270, 12, 50, 88, 118, 148, 175, |
| 202, 229, 256, 278, 20, 58, 29, 67, 97, 127, 157, 184, 211, 238, |
| 260, 282, 0, 38, 76, 106, 136, 163, 190, 217, 244, 266, 8, 46, |
| 84, 114, 144, 171, 198, 225, 252, 274, 16, 54, |
| }; |
| |
| |
| #ifdef __GNUC__ |
| #pragma GCC diagnostic push |
| #pragma GCC diagnostic ignored "-Woverlength-strings" |
| #endif |
| static const char AsmStrsRegAliasName[] = { |
| /* 0 */ "ft10\0" |
| /* 5 */ "fa0\0" |
| /* 9 */ "fs0\0" |
| /* 13 */ "ft0\0" |
| /* 17 */ "ft11\0" |
| /* 22 */ "fa1\0" |
| /* 26 */ "fs1\0" |
| /* 30 */ "ft1\0" |
| /* 34 */ "ft12\0" |
| /* 39 */ "fa2\0" |
| /* 43 */ "fs2\0" |
| /* 47 */ "ft2\0" |
| /* 51 */ "ft13\0" |
| /* 56 */ "fa3\0" |
| /* 60 */ "fs3\0" |
| /* 64 */ "ft3\0" |
| /* 68 */ "ft14\0" |
| /* 73 */ "fa4\0" |
| /* 77 */ "fs4\0" |
| /* 81 */ "ft4\0" |
| /* 85 */ "ft15\0" |
| /* 90 */ "fa5\0" |
| /* 94 */ "fs5\0" |
| /* 98 */ "ft5\0" |
| /* 102 */ "fa6\0" |
| /* 106 */ "fs6\0" |
| /* 110 */ "ft6\0" |
| /* 114 */ "fa7\0" |
| /* 118 */ "fs7\0" |
| /* 122 */ "ft7\0" |
| /* 126 */ "s8\0" |
| /* 129 */ "ft8\0" |
| /* 133 */ "ft9\0" |
| /* 137 */ "ra\0" |
| /* 140 */ "zero\0" |
| /* 145 */ "fp\0" |
| /* 148 */ "sp\0" |
| /* 151 */ "tp\0" |
| }; |
| #ifdef __GNUC__ |
| #pragma GCC diagnostic pop |
| #endif |
| |
| static const uint8_t RegAsmOffsetRegAliasName[] = { |
| 5, 22, 39, 56, 73, 90, 102, 114, 13, 30, 47, 64, 81, 98, |
| 110, 122, 129, 133, 0, 17, 34, 51, 68, 85, 9, 26, 43, 60, |
| 77, 94, 106, 118, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, |
| 4, 4, 140, 137, 151, 148, 6, 23, 40, 57, 74, 91, 103, 115, |
| 14, 31, 48, 65, 82, 99, 111, 123, 130, 4, 145, 10, 27, 44, |
| 61, 78, 95, 107, 119, 126, 5, 22, 39, 56, 73, 90, 102, 114, |
| 13, 30, 47, 64, 81, 98, 110, 122, 129, 133, 0, 17, 34, 51, |
| 68, 85, 9, 26, 43, 60, 77, 94, 106, 118, |
| }; |
| |
| switch(AltIdx) { |
| default: llvm_unreachable("Invalid register alt name index!"); |
| case LoongArch::NoRegAltName: |
| assert(*(AsmStrsNoRegAltName+RegAsmOffsetNoRegAltName[RegNo-1]) && |
| "Invalid alt name index for register!"); |
| return AsmStrsNoRegAltName+RegAsmOffsetNoRegAltName[RegNo-1]; |
| case LoongArch::RegAliasName: |
| if (!*(AsmStrsRegAliasName+RegAsmOffsetRegAliasName[RegNo-1])) |
| return getRegisterName(RegNo, LoongArch::NoRegAltName); |
| return AsmStrsRegAliasName+RegAsmOffsetRegAliasName[RegNo-1]; |
| } |
| } |
| |
| #ifdef PRINT_ALIAS_INSTR |
| #undef PRINT_ALIAS_INSTR |
| |
| bool LoongArchInstPrinter::printAliasInstr(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &OS) { |
| static const PatternsForOpcode OpToPatterns[] = { |
| {LoongArch::PseudoLA_ABS, 0, 1 }, |
| {LoongArch::PseudoLA_GOT_LARGE, 1, 1 }, |
| {LoongArch::PseudoLA_PCREL, 2, 1 }, |
| {LoongArch::PseudoLA_PCREL_LARGE, 3, 2 }, |
| {LoongArch::ANDI, 5, 1 }, |
| {LoongArch::JIRL, 6, 2 }, |
| {LoongArch::OR, 8, 1 }, |
| }; |
| |
| static const AliasPattern Patterns[] = { |
| // LoongArch::PseudoLA_ABS - 0 |
| {0, 0, 2, 2 }, |
| // LoongArch::PseudoLA_GOT_LARGE - 1 |
| {16, 2, 3, 2 }, |
| // LoongArch::PseudoLA_PCREL - 2 |
| {0, 4, 2, 1 }, |
| // LoongArch::PseudoLA_PCREL_LARGE - 3 |
| {37, 5, 3, 2 }, |
| {16, 7, 3, 3 }, |
| // LoongArch::ANDI - 5 |
| {57, 10, 3, 3 }, |
| // LoongArch::JIRL - 6 |
| {61, 13, 3, 3 }, |
| {65, 16, 3, 3 }, |
| // LoongArch::OR - 8 |
| {71, 19, 3, 3 }, |
| }; |
| |
| static const AliasPatternCond Conds[] = { |
| // (PseudoLA_ABS GPR:$dst, bare_symbol:$src) - 0 |
| {AliasPatternCond::K_RegClass, LoongArch::GPRRegClassID}, |
| {AliasPatternCond::K_Feature, LoongArch::LaLocalWithAbs}, |
| // (PseudoLA_GOT_LARGE GPR:$dst, GPR:$tmp, bare_symbol:$src) - 2 |
| {AliasPatternCond::K_RegClass, LoongArch::GPRRegClassID}, |
| {AliasPatternCond::K_RegClass, LoongArch::GPRRegClassID}, |
| // (PseudoLA_PCREL GPR:$dst, bare_symbol:$src) - 4 |
| {AliasPatternCond::K_RegClass, LoongArch::GPRRegClassID}, |
| // (PseudoLA_PCREL_LARGE GPR:$dst, GPR:$tmp, bare_symbol:$src) - 5 |
| {AliasPatternCond::K_RegClass, LoongArch::GPRRegClassID}, |
| {AliasPatternCond::K_RegClass, LoongArch::GPRRegClassID}, |
| // (PseudoLA_PCREL_LARGE GPR:$dst, GPR:$tmp, bare_symbol:$src) - 7 |
| {AliasPatternCond::K_RegClass, LoongArch::GPRRegClassID}, |
| {AliasPatternCond::K_RegClass, LoongArch::GPRRegClassID}, |
| {AliasPatternCond::K_Feature, LoongArch::LaGlobalWithPcrel}, |
| // (ANDI R0, R0, 0) - 10 |
| {AliasPatternCond::K_Reg, LoongArch::R0}, |
| {AliasPatternCond::K_Reg, LoongArch::R0}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (JIRL R0, R1, 0) - 13 |
| {AliasPatternCond::K_Reg, LoongArch::R0}, |
| {AliasPatternCond::K_Reg, LoongArch::R1}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (JIRL R0, GPR:$rj, 0) - 16 |
| {AliasPatternCond::K_Reg, LoongArch::R0}, |
| {AliasPatternCond::K_RegClass, LoongArch::GPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (OR GPR:$dst, GPR:$src, R0) - 19 |
| {AliasPatternCond::K_RegClass, LoongArch::GPRRegClassID}, |
| {AliasPatternCond::K_RegClass, LoongArch::GPRRegClassID}, |
| {AliasPatternCond::K_Reg, LoongArch::R0}, |
| }; |
| |
| static const char AsmStrings[] = |
| /* 0 */ "la.local $\x01, $\x02\0" |
| /* 16 */ "la.global $\x01, $\x02, $\x03\0" |
| /* 37 */ "la.local $\x01, $\x02, $\x03\0" |
| /* 57 */ "nop\0" |
| /* 61 */ "ret\0" |
| /* 65 */ "jr $\x02\0" |
| /* 71 */ "move $\x01, $\x02\0" |
| ; |
| |
| #ifndef NDEBUG |
| static struct SortCheck { |
| SortCheck(ArrayRef<PatternsForOpcode> OpToPatterns) { |
| assert(std::is_sorted( |
| OpToPatterns.begin(), OpToPatterns.end(), |
| [](const PatternsForOpcode &L, const PatternsForOpcode &R) { |
| return L.Opcode < R.Opcode; |
| }) && |
| "tablegen failed to sort opcode patterns"); |
| } |
| } sortCheckVar(OpToPatterns); |
| #endif |
| |
| AliasMatchingData M { |
| ArrayRef(OpToPatterns), |
| ArrayRef(Patterns), |
| ArrayRef(Conds), |
| StringRef(AsmStrings, std::size(AsmStrings)), |
| nullptr, |
| }; |
| const char *AsmString = matchAliasPatterns(MI, &STI, M); |
| if (!AsmString) return false; |
| |
| unsigned I = 0; |
| while (AsmString[I] != ' ' && AsmString[I] != '\t' && |
| AsmString[I] != '$' && AsmString[I] != '\0') |
| ++I; |
| OS << '\t' << StringRef(AsmString, I); |
| if (AsmString[I] != '\0') { |
| if (AsmString[I] == ' ' || AsmString[I] == '\t') { |
| OS << '\t'; |
| ++I; |
| } |
| do { |
| if (AsmString[I] == '$') { |
| ++I; |
| if (AsmString[I] == (char)0xff) { |
| ++I; |
| int OpIdx = AsmString[I++] - 1; |
| int PrintMethodIdx = AsmString[I++] - 1; |
| printCustomAliasOperand(MI, Address, OpIdx, PrintMethodIdx, STI, OS); |
| } else |
| printOperand(MI, unsigned(AsmString[I++]) - 1, STI, OS); |
| } else { |
| OS << AsmString[I++]; |
| } |
| } while (AsmString[I] != '\0'); |
| } |
| |
| return true; |
| } |
| |
| void LoongArchInstPrinter::printCustomAliasOperand( |
| const MCInst *MI, uint64_t Address, unsigned OpIdx, |
| unsigned PrintMethodIdx, |
| const MCSubtargetInfo &STI, |
| raw_ostream &OS) { |
| llvm_unreachable("Unknown PrintMethod kind"); |
| } |
| |
| #endif // PRINT_ALIAS_INSTR |