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/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|* *|
|* Global Instruction Selector for the ARM target *|
|* *|
|* Automatically generated file, do not edit! *|
|* *|
\*===----------------------------------------------------------------------===*/
#ifdef GET_GLOBALISEL_PREDICATE_BITSET
const unsigned MAX_SUBTARGET_PREDICATES = 80;
using PredicateBitset = llvm::PredicateBitsetImpl<MAX_SUBTARGET_PREDICATES>;
#endif // ifdef GET_GLOBALISEL_PREDICATE_BITSET
#ifdef GET_GLOBALISEL_TEMPORARIES_DECL
mutable MatcherState State;
typedef ComplexRendererFns(ARMInstructionSelector::*ComplexMatcherMemFn)(MachineOperand &) const;
typedef void(ARMInstructionSelector::*CustomRendererFn)(MachineInstrBuilder &, const MachineInstr &, int) const;
const ISelInfoTy<PredicateBitset, ComplexMatcherMemFn, CustomRendererFn> ISelInfo;
static ARMInstructionSelector::ComplexMatcherMemFn ComplexPredicateFns[];
static ARMInstructionSelector::CustomRendererFn CustomRenderers[];
bool testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const override;
bool testImmPredicate_APInt(unsigned PredicateID, const APInt &Imm) const override;
bool testImmPredicate_APFloat(unsigned PredicateID, const APFloat &Imm) const override;
const int64_t *getMatchTable() const override;
bool testMIPredicate_MI(unsigned PredicateID, const MachineInstr &MI, const std::array<const MachineOperand *, 3> &Operands) const override;
#endif // ifdef GET_GLOBALISEL_TEMPORARIES_DECL
#ifdef GET_GLOBALISEL_TEMPORARIES_INIT
, State(0),
ISelInfo(TypeObjects, NumTypeObjects, FeatureBitsets, ComplexPredicateFns, CustomRenderers)
#endif // ifdef GET_GLOBALISEL_TEMPORARIES_INIT
#ifdef GET_GLOBALISEL_IMPL
// Bits for subtarget features that participate in instruction matching.
enum SubtargetFeatureBits : uint8_t {
Feature_NoHonorSignDependentRoundingBit = 71,
Feature_HasV4TBit = 6,
Feature_NoV4TBit = 7,
Feature_HasV5TBit = 13,
Feature_NoV5TBit = 65,
Feature_HasV5TEBit = 11,
Feature_HasV6Bit = 0,
Feature_NoV6Bit = 9,
Feature_HasV6MBit = 29,
Feature_HasV8MBaselineBit = 34,
Feature_HasV8_1MMainlineBit = 40,
Feature_HasMVEIntBit = 63,
Feature_HasMVEFloatBit = 64,
Feature_HasCDEBit = 79,
Feature_HasFPRegsBit = 41,
Feature_HasFPRegs16Bit = 42,
Feature_HasNoFPRegs16Bit = 70,
Feature_HasFPRegs64Bit = 51,
Feature_HasV6T2Bit = 8,
Feature_HasV6KBit = 19,
Feature_HasV7Bit = 3,
Feature_HasV8Bit = 15,
Feature_PreV8Bit = 20,
Feature_HasV8_1aBit = 73,
Feature_HasV8_3aBit = 74,
Feature_NoVFPBit = 23,
Feature_HasVFP2Bit = 22,
Feature_HasVFP3Bit = 52,
Feature_HasVFP4Bit = 49,
Feature_HasDPVFPBit = 43,
Feature_HasFPARMv8Bit = 46,
Feature_HasNEONBit = 53,
Feature_HasSHA2Bit = 61,
Feature_HasAESBit = 54,
Feature_HasDotProdBit = 55,
Feature_HasCRCBit = 14,
Feature_HasLOBBit = 39,
Feature_HasFP16Bit = 60,
Feature_HasFullFP16Bit = 45,
Feature_HasBF16Bit = 62,
Feature_HasMatMulInt8Bit = 56,
Feature_HasDivideInThumbBit = 36,
Feature_HasDivideInARMBit = 12,
Feature_HasDSPBit = 35,
Feature_HasDBBit = 16,
Feature_HasV7ClrexBit = 18,
Feature_HasAcquireReleaseBit = 17,
Feature_HasMPBit = 2,
Feature_Has8MSecExtBit = 30,
Feature_HasZCZBit = 57,
Feature_UseNEONForFPBit = 77,
Feature_DontUseNEONForFPBit = 44,
Feature_IsThumbBit = 27,
Feature_IsThumb1OnlyBit = 28,
Feature_IsThumb2Bit = 33,
Feature_IsNotMClassBit = 37,
Feature_IsARMBit = 1,
Feature_IsWindowsBit = 31,
Feature_IsNotWindowsBit = 32,
Feature_IsReadTPHardBit = 68,
Feature_IsReadTPSoftBit = 21,
Feature_UseNaClTrapBit = 4,
Feature_DontUseNaClTrapBit = 5,
Feature_UseMovtBit = 38,
Feature_DontUseMovtBit = 24,
Feature_UseMovtInPicBit = 25,
Feature_DontUseMovtInPicBit = 26,
Feature_UseFPVMLxBit = 48,
Feature_SLSBLRMitigationBit = 67,
Feature_NoSLSBLRMitigationBit = 66,
Feature_UseMulOpsBit = 10,
Feature_UseFusedMACBit = 50,
Feature_HasFastVGETLNi32Bit = 58,
Feature_HasSlowVGETLNi32Bit = 75,
Feature_HasFastVDUP32Bit = 59,
Feature_HasSlowVDUP32Bit = 76,
Feature_UseVMOVSRBit = 47,
Feature_DontUseVMOVSRBit = 78,
Feature_IsLEBit = 69,
Feature_IsBEBit = 72,
};
PredicateBitset ARMInstructionSelector::
computeAvailableModuleFeatures(const ARMSubtarget *Subtarget) const {
PredicateBitset Features;
if (!TM.Options.HonorSignDependentRoundingFPMath())
Features.set(Feature_NoHonorSignDependentRoundingBit);
if (Subtarget->hasV4TOps())
Features.set(Feature_HasV4TBit);
if (!Subtarget->hasV4TOps())
Features.set(Feature_NoV4TBit);
if (Subtarget->hasV5TOps())
Features.set(Feature_HasV5TBit);
if (!Subtarget->hasV5TOps())
Features.set(Feature_NoV5TBit);
if (Subtarget->hasV5TEOps())
Features.set(Feature_HasV5TEBit);
if (Subtarget->hasV6Ops())
Features.set(Feature_HasV6Bit);
if (!Subtarget->hasV6Ops())
Features.set(Feature_NoV6Bit);
if (Subtarget->hasV6MOps())
Features.set(Feature_HasV6MBit);
if (Subtarget->hasV8MBaselineOps())
Features.set(Feature_HasV8MBaselineBit);
if (Subtarget->hasV8_1MMainlineOps())
Features.set(Feature_HasV8_1MMainlineBit);
if (Subtarget->hasMVEIntegerOps())
Features.set(Feature_HasMVEIntBit);
if (Subtarget->hasMVEFloatOps())
Features.set(Feature_HasMVEFloatBit);
if (Subtarget->hasCDEOps())
Features.set(Feature_HasCDEBit);
if (Subtarget->hasFPRegs())
Features.set(Feature_HasFPRegsBit);
if (Subtarget->hasFPRegs16())
Features.set(Feature_HasFPRegs16Bit);
if (!Subtarget->hasFPRegs16())
Features.set(Feature_HasNoFPRegs16Bit);
if (Subtarget->hasFPRegs64())
Features.set(Feature_HasFPRegs64Bit);
if (Subtarget->hasV6T2Ops())
Features.set(Feature_HasV6T2Bit);
if (Subtarget->hasV6KOps())
Features.set(Feature_HasV6KBit);
if (Subtarget->hasV7Ops())
Features.set(Feature_HasV7Bit);
if (Subtarget->hasV8Ops())
Features.set(Feature_HasV8Bit);
if (!Subtarget->hasV8Ops())
Features.set(Feature_PreV8Bit);
if (Subtarget->hasV8_1aOps())
Features.set(Feature_HasV8_1aBit);
if (Subtarget->hasV8_3aOps())
Features.set(Feature_HasV8_3aBit);
if (!Subtarget->hasVFP2Base())
Features.set(Feature_NoVFPBit);
if (Subtarget->hasVFP2Base())
Features.set(Feature_HasVFP2Bit);
if (Subtarget->hasVFP3Base())
Features.set(Feature_HasVFP3Bit);
if (Subtarget->hasVFP4Base())
Features.set(Feature_HasVFP4Bit);
if (Subtarget->hasFP64())
Features.set(Feature_HasDPVFPBit);
if (Subtarget->hasFPARMv8Base())
Features.set(Feature_HasFPARMv8Bit);
if (Subtarget->hasNEON())
Features.set(Feature_HasNEONBit);
if (Subtarget->hasSHA2())
Features.set(Feature_HasSHA2Bit);
if (Subtarget->hasAES())
Features.set(Feature_HasAESBit);
if (Subtarget->hasDotProd())
Features.set(Feature_HasDotProdBit);
if (Subtarget->hasCRC())
Features.set(Feature_HasCRCBit);
if (Subtarget->hasLOB())
Features.set(Feature_HasLOBBit);
if (Subtarget->hasFP16())
Features.set(Feature_HasFP16Bit);
if (Subtarget->hasFullFP16())
Features.set(Feature_HasFullFP16Bit);
if (Subtarget->hasBF16())
Features.set(Feature_HasBF16Bit);
if (Subtarget->hasMatMulInt8())
Features.set(Feature_HasMatMulInt8Bit);
if (Subtarget->hasDivideInThumbMode())
Features.set(Feature_HasDivideInThumbBit);
if (Subtarget->hasDivideInARMMode())
Features.set(Feature_HasDivideInARMBit);
if (Subtarget->hasDSP())
Features.set(Feature_HasDSPBit);
if (Subtarget->hasDataBarrier())
Features.set(Feature_HasDBBit);
if (Subtarget->hasV7Clrex())
Features.set(Feature_HasV7ClrexBit);
if (Subtarget->hasAcquireRelease())
Features.set(Feature_HasAcquireReleaseBit);
if (Subtarget->hasMPExtension())
Features.set(Feature_HasMPBit);
if (Subtarget->has8MSecExt())
Features.set(Feature_Has8MSecExtBit);
if (Subtarget->hasZeroCycleZeroing())
Features.set(Feature_HasZCZBit);
if (Subtarget->useNEONForSinglePrecisionFP())
Features.set(Feature_UseNEONForFPBit);
if (!Subtarget->useNEONForSinglePrecisionFP())
Features.set(Feature_DontUseNEONForFPBit);
if (Subtarget->isThumb())
Features.set(Feature_IsThumbBit);
if (Subtarget->isThumb1Only())
Features.set(Feature_IsThumb1OnlyBit);
if (Subtarget->isThumb2())
Features.set(Feature_IsThumb2Bit);
if (!Subtarget->isMClass())
Features.set(Feature_IsNotMClassBit);
if (!Subtarget->isThumb())
Features.set(Feature_IsARMBit);
if (Subtarget->isTargetWindows())
Features.set(Feature_IsWindowsBit);
if (!Subtarget->isTargetWindows())
Features.set(Feature_IsNotWindowsBit);
if (Subtarget->isReadTPHard())
Features.set(Feature_IsReadTPHardBit);
if (!Subtarget->isReadTPHard())
Features.set(Feature_IsReadTPSoftBit);
if (Subtarget->useNaClTrap())
Features.set(Feature_UseNaClTrapBit);
if (!Subtarget->useNaClTrap())
Features.set(Feature_DontUseNaClTrapBit);
if (Subtarget->useMulOps())
Features.set(Feature_UseMulOpsBit);
if (TM.Options.AllowFPOpFusion == FPOpFusion::Fast && Subtarget->useFPVFMx())
Features.set(Feature_UseFusedMACBit);
if (!Subtarget->hasSlowVGETLNi32())
Features.set(Feature_HasFastVGETLNi32Bit);
if (Subtarget->hasSlowVGETLNi32())
Features.set(Feature_HasSlowVGETLNi32Bit);
if (!Subtarget->hasSlowVDUP32())
Features.set(Feature_HasFastVDUP32Bit);
if (Subtarget->hasSlowVDUP32())
Features.set(Feature_HasSlowVDUP32Bit);
if (Subtarget->preferVMOVSR() ||!Subtarget->useNEONForSinglePrecisionFP())
Features.set(Feature_UseVMOVSRBit);
if (!Subtarget->preferVMOVSR() &&Subtarget->useNEONForSinglePrecisionFP())
Features.set(Feature_DontUseVMOVSRBit);
return Features;
}
void ARMInstructionSelector::setupGeneratedPerFunctionState(MachineFunction &MF) {
AvailableFunctionFeatures = computeAvailableFunctionFeatures((const ARMSubtarget *)&MF.getSubtarget(), &MF);
}
PredicateBitset ARMInstructionSelector::
computeAvailableFunctionFeatures(const ARMSubtarget *Subtarget, const MachineFunction *MF) const {
PredicateBitset Features;
if (Subtarget->useMovt())
Features.set(Feature_UseMovtBit);
if (!Subtarget->useMovt())
Features.set(Feature_DontUseMovtBit);
if (Subtarget->useMovt() && Subtarget->allowPositionIndependentMovt())
Features.set(Feature_UseMovtInPicBit);
if (!Subtarget->useMovt() || !Subtarget->allowPositionIndependentMovt())
Features.set(Feature_DontUseMovtInPicBit);
if (((Subtarget->useFPVMLx() && TM.Options.AllowFPOpFusion != FPOpFusion::Fast) ||Subtarget->hasMinSize()))
Features.set(Feature_UseFPVMLxBit);
if ( MF->getSubtarget<ARMSubtarget>().hardenSlsBlr() )
Features.set(Feature_SLSBLRMitigationBit);
if ( !MF->getSubtarget<ARMSubtarget>().hardenSlsBlr() )
Features.set(Feature_NoSLSBLRMitigationBit);
if (MF->getDataLayout().isLittleEndian())
Features.set(Feature_IsLEBit);
if (MF->getDataLayout().isBigEndian())
Features.set(Feature_IsBEBit);
return Features;
}
// LLT Objects.
enum {
GILLT_s16,
GILLT_s32,
GILLT_s64,
GILLT_v2s1,
GILLT_v2s32,
GILLT_v2s64,
GILLT_v4s1,
GILLT_v4s16,
GILLT_v4s32,
GILLT_v4s64,
GILLT_v8s1,
GILLT_v8s8,
GILLT_v8s16,
GILLT_v8s64,
GILLT_v16s1,
GILLT_v16s8,
};
const static size_t NumTypeObjects = 16;
const static LLT TypeObjects[] = {
LLT::scalar(16),
LLT::scalar(32),
LLT::scalar(64),
LLT::vector(ElementCount::getFixed(2), 1),
LLT::vector(ElementCount::getFixed(2), 32),
LLT::vector(ElementCount::getFixed(2), 64),
LLT::vector(ElementCount::getFixed(4), 1),
LLT::vector(ElementCount::getFixed(4), 16),
LLT::vector(ElementCount::getFixed(4), 32),
LLT::vector(ElementCount::getFixed(4), 64),
LLT::vector(ElementCount::getFixed(8), 1),
LLT::vector(ElementCount::getFixed(8), 8),
LLT::vector(ElementCount::getFixed(8), 16),
LLT::vector(ElementCount::getFixed(8), 64),
LLT::vector(ElementCount::getFixed(16), 1),
LLT::vector(ElementCount::getFixed(16), 8),
};
// Feature bitsets.
enum {
GIFBS_Invalid,
GIFBS_HasDotProd,
GIFBS_HasFP16,
GIFBS_HasFPARMv8,
GIFBS_HasFPRegs,
GIFBS_HasFullFP16,
GIFBS_HasMVEFloat,
GIFBS_HasMVEInt,
GIFBS_HasMatMulInt8,
GIFBS_HasNEON,
GIFBS_HasVFP2,
GIFBS_HasVFP3,
GIFBS_HasVFP4,
GIFBS_IsARM,
GIFBS_IsThumb,
GIFBS_IsThumb2,
GIFBS_NoHonorSignDependentRounding,
GIFBS_DontUseNEONForFP_HasVFP2,
GIFBS_DontUseVMOVSR_HasNEON,
GIFBS_Has8MSecExt_IsThumb,
GIFBS_HasAES_HasV8,
GIFBS_HasBF16_HasNEON,
GIFBS_HasDB_IsARM,
GIFBS_HasDB_IsThumb,
GIFBS_HasDPVFP_HasFPARMv8,
GIFBS_HasDPVFP_HasVFP2,
GIFBS_HasDPVFP_HasVFP3,
GIFBS_HasDPVFP_HasVFP4,
GIFBS_HasDPVFP_NoHonorSignDependentRounding,
GIFBS_HasDSP_IsThumb2,
GIFBS_HasDivideInARM_IsARM,
GIFBS_HasFP16_HasNEON,
GIFBS_HasFPRegs_HasFastVGETLNi32,
GIFBS_HasFPRegs_UseVMOVSR,
GIFBS_HasFullFP16_HasNEON,
GIFBS_HasMVEInt_HasV8_1MMainline,
GIFBS_HasMVEInt_IsBE,
GIFBS_HasMVEInt_IsLE,
GIFBS_HasNEON_HasV8,
GIFBS_HasNEON_HasV8_1a,
GIFBS_HasNEON_HasV8_3a,
GIFBS_HasNEON_HasVFP4,
GIFBS_HasNEON_IsBE,
GIFBS_HasNEON_IsLE,
GIFBS_HasNEON_UseNEONForFP,
GIFBS_HasSHA2_HasV8,
GIFBS_HasV5T_IsARM,
GIFBS_HasV5TE_IsARM,
GIFBS_HasV6_IsARM,
GIFBS_HasV6K_IsARM,
GIFBS_HasV6M_IsThumb,
GIFBS_HasV6T2_IsARM,
GIFBS_HasV7_IsARM,
GIFBS_HasV7Clrex_IsThumb,
GIFBS_HasV8MBaseline_IsThumb,
GIFBS_IsARM_NoV6,
GIFBS_IsARM_PreV8,
GIFBS_IsThumb_IsThumb1Only,
GIFBS_IsThumb_IsWindows,
GIFBS_IsThumb_UseMovt,
GIFBS_IsThumb2_PreV8,
GIFBS_IsThumb2_UseMulOps,
GIFBS_HasCRC_HasV8_IsARM,
GIFBS_HasCRC_HasV8_IsThumb2,
GIFBS_HasDSP_IsThumb2_UseMulOps,
GIFBS_HasDivideInThumb_HasV8MBaseline_IsThumb,
GIFBS_HasFullFP16_HasNEON_HasV8,
GIFBS_HasFullFP16_HasNEON_HasV8_3a,
GIFBS_HasFullFP16_HasNEON_UseFPVMLx,
GIFBS_HasFullFP16_HasNEON_UseFusedMAC,
GIFBS_HasLOB_HasV8_1MMainline_IsThumb2,
GIFBS_HasNEON_UseFPVMLx_UseNEONForFP,
GIFBS_HasV5TE_IsARM_UseMulOps,
GIFBS_HasV6_IsARM_UseMulOps,
GIFBS_HasV6_IsThumb_IsThumb1Only,
GIFBS_HasV6T2_IsARM_UseMulOps,
GIFBS_HasVFP4_UseFusedMAC_UseNEONForFP,
GIFBS_IsARM_NoV6_UseMulOps,
};
const static PredicateBitset FeatureBitsets[] {
{}, // GIFBS_Invalid
{Feature_HasDotProdBit, },
{Feature_HasFP16Bit, },
{Feature_HasFPARMv8Bit, },
{Feature_HasFPRegsBit, },
{Feature_HasFullFP16Bit, },
{Feature_HasMVEFloatBit, },
{Feature_HasMVEIntBit, },
{Feature_HasMatMulInt8Bit, },
{Feature_HasNEONBit, },
{Feature_HasVFP2Bit, },
{Feature_HasVFP3Bit, },
{Feature_HasVFP4Bit, },
{Feature_IsARMBit, },
{Feature_IsThumbBit, },
{Feature_IsThumb2Bit, },
{Feature_NoHonorSignDependentRoundingBit, },
{Feature_DontUseNEONForFPBit, Feature_HasVFP2Bit, },
{Feature_DontUseVMOVSRBit, Feature_HasNEONBit, },
{Feature_Has8MSecExtBit, Feature_IsThumbBit, },
{Feature_HasAESBit, Feature_HasV8Bit, },
{Feature_HasBF16Bit, Feature_HasNEONBit, },
{Feature_HasDBBit, Feature_IsARMBit, },
{Feature_HasDBBit, Feature_IsThumbBit, },
{Feature_HasDPVFPBit, Feature_HasFPARMv8Bit, },
{Feature_HasDPVFPBit, Feature_HasVFP2Bit, },
{Feature_HasDPVFPBit, Feature_HasVFP3Bit, },
{Feature_HasDPVFPBit, Feature_HasVFP4Bit, },
{Feature_HasDPVFPBit, Feature_NoHonorSignDependentRoundingBit, },
{Feature_HasDSPBit, Feature_IsThumb2Bit, },
{Feature_HasDivideInARMBit, Feature_IsARMBit, },
{Feature_HasFP16Bit, Feature_HasNEONBit, },
{Feature_HasFPRegsBit, Feature_HasFastVGETLNi32Bit, },
{Feature_HasFPRegsBit, Feature_UseVMOVSRBit, },
{Feature_HasFullFP16Bit, Feature_HasNEONBit, },
{Feature_HasMVEIntBit, Feature_HasV8_1MMainlineBit, },
{Feature_HasMVEIntBit, Feature_IsBEBit, },
{Feature_HasMVEIntBit, Feature_IsLEBit, },
{Feature_HasNEONBit, Feature_HasV8Bit, },
{Feature_HasNEONBit, Feature_HasV8_1aBit, },
{Feature_HasNEONBit, Feature_HasV8_3aBit, },
{Feature_HasNEONBit, Feature_HasVFP4Bit, },
{Feature_HasNEONBit, Feature_IsBEBit, },
{Feature_HasNEONBit, Feature_IsLEBit, },
{Feature_HasNEONBit, Feature_UseNEONForFPBit, },
{Feature_HasSHA2Bit, Feature_HasV8Bit, },
{Feature_HasV5TBit, Feature_IsARMBit, },
{Feature_HasV5TEBit, Feature_IsARMBit, },
{Feature_HasV6Bit, Feature_IsARMBit, },
{Feature_HasV6KBit, Feature_IsARMBit, },
{Feature_HasV6MBit, Feature_IsThumbBit, },
{Feature_HasV6T2Bit, Feature_IsARMBit, },
{Feature_HasV7Bit, Feature_IsARMBit, },
{Feature_HasV7ClrexBit, Feature_IsThumbBit, },
{Feature_HasV8MBaselineBit, Feature_IsThumbBit, },
{Feature_IsARMBit, Feature_NoV6Bit, },
{Feature_IsARMBit, Feature_PreV8Bit, },
{Feature_IsThumbBit, Feature_IsThumb1OnlyBit, },
{Feature_IsThumbBit, Feature_IsWindowsBit, },
{Feature_IsThumbBit, Feature_UseMovtBit, },
{Feature_IsThumb2Bit, Feature_PreV8Bit, },
{Feature_IsThumb2Bit, Feature_UseMulOpsBit, },
{Feature_HasCRCBit, Feature_HasV8Bit, Feature_IsARMBit, },
{Feature_HasCRCBit, Feature_HasV8Bit, Feature_IsThumb2Bit, },
{Feature_HasDSPBit, Feature_IsThumb2Bit, Feature_UseMulOpsBit, },
{Feature_HasDivideInThumbBit, Feature_HasV8MBaselineBit, Feature_IsThumbBit, },
{Feature_HasFullFP16Bit, Feature_HasNEONBit, Feature_HasV8Bit, },
{Feature_HasFullFP16Bit, Feature_HasNEONBit, Feature_HasV8_3aBit, },
{Feature_HasFullFP16Bit, Feature_HasNEONBit, Feature_UseFPVMLxBit, },
{Feature_HasFullFP16Bit, Feature_HasNEONBit, Feature_UseFusedMACBit, },
{Feature_HasLOBBit, Feature_HasV8_1MMainlineBit, Feature_IsThumb2Bit, },
{Feature_HasNEONBit, Feature_UseFPVMLxBit, Feature_UseNEONForFPBit, },
{Feature_HasV5TEBit, Feature_IsARMBit, Feature_UseMulOpsBit, },
{Feature_HasV6Bit, Feature_IsARMBit, Feature_UseMulOpsBit, },
{Feature_HasV6Bit, Feature_IsThumbBit, Feature_IsThumb1OnlyBit, },
{Feature_HasV6T2Bit, Feature_IsARMBit, Feature_UseMulOpsBit, },
{Feature_HasVFP4Bit, Feature_UseFusedMACBit, Feature_UseNEONForFPBit, },
{Feature_IsARMBit, Feature_NoV6Bit, Feature_UseMulOpsBit, },
};
// ComplexPattern predicates.
enum {
GICP_Invalid,
};
// See constructor for table contents
// PatFrag predicates.
enum {
GIPFP_I64_Predicate_VectorIndex16 = GIPFP_I64_Invalid + 1,
GIPFP_I64_Predicate_VectorIndex32,
GIPFP_I64_Predicate_VectorIndex64,
GIPFP_I64_Predicate_VectorIndex8,
GIPFP_I64_Predicate_asr_imm,
GIPFP_I64_Predicate_imm0_15,
GIPFP_I64_Predicate_imm0_239,
GIPFP_I64_Predicate_imm0_255,
GIPFP_I64_Predicate_imm0_31,
GIPFP_I64_Predicate_imm0_32,
GIPFP_I64_Predicate_imm0_4095,
GIPFP_I64_Predicate_imm0_63,
GIPFP_I64_Predicate_imm0_65535,
GIPFP_I64_Predicate_imm0_65535_neg,
GIPFP_I64_Predicate_imm0_7,
GIPFP_I64_Predicate_imm16,
GIPFP_I64_Predicate_imm16_31,
GIPFP_I64_Predicate_imm1_15,
GIPFP_I64_Predicate_imm1_16,
GIPFP_I64_Predicate_imm1_31,
GIPFP_I64_Predicate_imm1_7,
GIPFP_I64_Predicate_imm24b,
GIPFP_I64_Predicate_imm256_510,
GIPFP_I64_Predicate_imm32,
GIPFP_I64_Predicate_imm8,
GIPFP_I64_Predicate_imm8_255,
GIPFP_I64_Predicate_imm8_or_16,
GIPFP_I64_Predicate_imm_11b,
GIPFP_I64_Predicate_imm_12b,
GIPFP_I64_Predicate_imm_13b,
GIPFP_I64_Predicate_imm_3b,
GIPFP_I64_Predicate_imm_4b,
GIPFP_I64_Predicate_imm_6b,
GIPFP_I64_Predicate_imm_7b,
GIPFP_I64_Predicate_imm_9b,
GIPFP_I64_Predicate_imm_even,
GIPFP_I64_Predicate_imm_odd,
GIPFP_I64_Predicate_long_shift,
GIPFP_I64_Predicate_mod_imm,
GIPFP_I64_Predicate_pkh_asr_amt,
GIPFP_I64_Predicate_pkh_lsl_amt,
GIPFP_I64_Predicate_shr_imm16,
GIPFP_I64_Predicate_shr_imm32,
GIPFP_I64_Predicate_shr_imm64,
GIPFP_I64_Predicate_shr_imm8,
GIPFP_I64_Predicate_t2_so_imm,
GIPFP_I64_Predicate_t2_so_imm_neg,
};
bool ARMInstructionSelector::testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const {
switch (PredicateID) {
case GIPFP_I64_Predicate_VectorIndex16: {
return ((uint64_t)Imm) < 4;
llvm_unreachable("ImmediateCode should have returned");
return false;
}
case GIPFP_I64_Predicate_VectorIndex32: {
return ((uint64_t)Imm) < 2;
llvm_unreachable("ImmediateCode should have returned");
return false;
}
case GIPFP_I64_Predicate_VectorIndex64: {
return ((uint64_t)Imm) < 1;
llvm_unreachable("ImmediateCode should have returned");
return false;
}
case GIPFP_I64_Predicate_VectorIndex8: {
return ((uint64_t)Imm) < 8;
llvm_unreachable("ImmediateCode should have returned");
return false;
}
case GIPFP_I64_Predicate_asr_imm: {
return Imm > 0 && Imm <= 32;
llvm_unreachable("ImmediateCode should have returned");
return false;
}
case GIPFP_I64_Predicate_imm0_15: {
return Imm >= 0 && Imm < 16;
llvm_unreachable("ImmediateCode should have returned");
return false;
}
case GIPFP_I64_Predicate_imm0_239: {
return Imm >= 0 && Imm < 240;
llvm_unreachable("ImmediateCode should have returned");
return false;
}
case GIPFP_I64_Predicate_imm0_255: {
return Imm >= 0 && Imm < 256;
llvm_unreachable("ImmediateCode should have returned");
return false;
}
case GIPFP_I64_Predicate_imm0_31: {
return Imm >= 0 && Imm < 32;
llvm_unreachable("ImmediateCode should have returned");
return false;
}
case GIPFP_I64_Predicate_imm0_32: {
return Imm >= 0 && Imm < 33;
llvm_unreachable("ImmediateCode should have returned");
return false;
}
case GIPFP_I64_Predicate_imm0_4095: {
return Imm >= 0 && Imm < 4096;
llvm_unreachable("ImmediateCode should have returned");
return false;
}
case GIPFP_I64_Predicate_imm0_63: {
return Imm >= 0 && Imm < 64;
llvm_unreachable("ImmediateCode should have returned");
return false;
}
case GIPFP_I64_Predicate_imm0_65535: {
return Imm >= 0 && Imm < 65536;
llvm_unreachable("ImmediateCode should have returned");
return false;
}
case GIPFP_I64_Predicate_imm0_65535_neg: {
return -Imm >= 0 && -Imm < 65536;
llvm_unreachable("ImmediateCode should have returned");
return false;
}
case GIPFP_I64_Predicate_imm0_7: {
return Imm >= 0 && Imm < 8;
llvm_unreachable("ImmediateCode should have returned");
return false;
}
case GIPFP_I64_Predicate_imm16: {
return Imm == 16;
llvm_unreachable("ImmediateCode should have returned");
return false;
}
case GIPFP_I64_Predicate_imm16_31: {
return (int32_t)Imm >= 16 && (int32_t)Imm < 32;
llvm_unreachable("ImmediateCode should have returned");
return false;
}
case GIPFP_I64_Predicate_imm1_15: {
return Imm > 0 && Imm < 16;
llvm_unreachable("ImmediateCode should have returned");
return false;
}
case GIPFP_I64_Predicate_imm1_16: {
return Imm > 0 && Imm <= 16;
llvm_unreachable("ImmediateCode should have returned");
return false;
}
case GIPFP_I64_Predicate_imm1_31: {
return Imm > 0 && Imm < 32;
llvm_unreachable("ImmediateCode should have returned");
return false;
}
case GIPFP_I64_Predicate_imm1_7: {
return Imm > 0 && Imm < 8;
llvm_unreachable("ImmediateCode should have returned");
return false;
}
case GIPFP_I64_Predicate_imm24b: {
return Imm >= 0 && Imm <= 0xffffff;
llvm_unreachable("ImmediateCode should have returned");
return false;
}
case GIPFP_I64_Predicate_imm256_510: {
return Imm >= 256 && Imm < 511;
llvm_unreachable("ImmediateCode should have returned");
return false;
}
case GIPFP_I64_Predicate_imm32: {
return Imm == 32;
llvm_unreachable("ImmediateCode should have returned");
return false;
}
case GIPFP_I64_Predicate_imm8: {
return Imm == 8;
llvm_unreachable("ImmediateCode should have returned");
return false;
}
case GIPFP_I64_Predicate_imm8_255: {
return Imm >= 8 && Imm < 256;
llvm_unreachable("ImmediateCode should have returned");
return false;
}
case GIPFP_I64_Predicate_imm8_or_16: {
return Imm == 8 || Imm == 16;
llvm_unreachable("ImmediateCode should have returned");
return false;
}
case GIPFP_I64_Predicate_imm_11b: {
{ return Imm >= 0 && Imm < (1 << 11); }
llvm_unreachable("ImmediateCode should have returned");
return false;
}
case GIPFP_I64_Predicate_imm_12b: {
{ return Imm >= 0 && Imm < (1 << 12); }
llvm_unreachable("ImmediateCode should have returned");
return false;
}
case GIPFP_I64_Predicate_imm_13b: {
{ return Imm >= 0 && Imm < (1 << 13); }
llvm_unreachable("ImmediateCode should have returned");
return false;
}
case GIPFP_I64_Predicate_imm_3b: {
{ return Imm >= 0 && Imm < (1 << 3); }
llvm_unreachable("ImmediateCode should have returned");
return false;
}
case GIPFP_I64_Predicate_imm_4b: {
{ return Imm >= 0 && Imm < (1 << 4); }
llvm_unreachable("ImmediateCode should have returned");
return false;
}
case GIPFP_I64_Predicate_imm_6b: {
{ return Imm >= 0 && Imm < (1 << 6); }
llvm_unreachable("ImmediateCode should have returned");
return false;
}
case GIPFP_I64_Predicate_imm_7b: {
{ return Imm >= 0 && Imm < (1 << 7); }
llvm_unreachable("ImmediateCode should have returned");
return false;
}
case GIPFP_I64_Predicate_imm_9b: {
{ return Imm >= 0 && Imm < (1 << 9); }
llvm_unreachable("ImmediateCode should have returned");
return false;
}
case GIPFP_I64_Predicate_imm_even: {
return (Imm & 1) == 0;
llvm_unreachable("ImmediateCode should have returned");
return false;
}
case GIPFP_I64_Predicate_imm_odd: {
return (Imm & 1) == 1;
llvm_unreachable("ImmediateCode should have returned");
return false;
}
case GIPFP_I64_Predicate_long_shift: {
return Imm > 0 && Imm <= 32;
llvm_unreachable("ImmediateCode should have returned");
return false;
}
case GIPFP_I64_Predicate_mod_imm: {
return ARM_AM::getSOImmVal(Imm) != -1;
llvm_unreachable("ImmediateCode should have returned");
return false;
}
case GIPFP_I64_Predicate_pkh_asr_amt: {
return Imm > 0 && Imm <= 32;
llvm_unreachable("ImmediateCode should have returned");
return false;
}
case GIPFP_I64_Predicate_pkh_lsl_amt: {
return Imm >= 0 && Imm < 32;
llvm_unreachable("ImmediateCode should have returned");
return false;
}
case GIPFP_I64_Predicate_shr_imm16: {
return Imm > 0 && Imm <= 16;
llvm_unreachable("ImmediateCode should have returned");
return false;
}
case GIPFP_I64_Predicate_shr_imm32: {
return Imm > 0 && Imm <= 32;
llvm_unreachable("ImmediateCode should have returned");
return false;
}
case GIPFP_I64_Predicate_shr_imm64: {
return Imm > 0 && Imm <= 64;
llvm_unreachable("ImmediateCode should have returned");
return false;
}
case GIPFP_I64_Predicate_shr_imm8: {
return Imm > 0 && Imm <= 8;
llvm_unreachable("ImmediateCode should have returned");
return false;
}
case GIPFP_I64_Predicate_t2_so_imm: {
return ARM_AM::getT2SOImmVal(Imm) != -1;
llvm_unreachable("ImmediateCode should have returned");
return false;
}
case GIPFP_I64_Predicate_t2_so_imm_neg: {
return Imm && ARM_AM::getT2SOImmVal(-(uint32_t)Imm) != -1;
llvm_unreachable("ImmediateCode should have returned");
return false;
}
}
llvm_unreachable("Unknown predicate");
return false;
}
bool ARMInstructionSelector::testImmPredicate_APFloat(unsigned PredicateID, const APFloat & Imm) const {
llvm_unreachable("Unknown predicate");
return false;
}
// PatFrag predicates.
enum {
GIPFP_APInt_Predicate_arm_i32imm = GIPFP_APInt_Invalid + 1,
};
bool ARMInstructionSelector::testImmPredicate_APInt(unsigned PredicateID, const APInt & Imm) const {
switch (PredicateID) {
case GIPFP_APInt_Predicate_arm_i32imm: {
if (Subtarget->useMovt())
return true;
if (ARM_AM::isSOImmTwoPartVal(Imm.getZExtValue()))
return true;
return ARM_AM::isSOImmTwoPartValNeg(Imm.getZExtValue());
llvm_unreachable("ImmediateCode should have returned");
return false;
}
}
llvm_unreachable("Unknown predicate");
return false;
}
// PatFrag predicates.
enum {
GIPFP_MI_Predicate_bf_inv_mask_imm = GIPFP_MI_Invalid + 1,
GIPFP_MI_Predicate_vfp_f32imm,
GIPFP_MI_Predicate_vfp_f64imm,
};
bool ARMInstructionSelector::testMIPredicate_MI(unsigned PredicateID, const MachineInstr & MI, const std::array<const MachineOperand *, 3> &Operands) const {
const MachineFunction &MF = *MI.getParent()->getParent();
const MachineRegisterInfo &MRI = MF.getRegInfo();
(void)MRI;
switch (PredicateID) {
case GIPFP_MI_Predicate_bf_inv_mask_imm: {
// There's better methods of implementing this check. IntImmLeaf<> would be
// equivalent and have less boilerplate but we need a test for C++
// predicates and this one causes new rules to be imported into GlobalISel
// without requiring additional features first.
const auto &MO = MI.getOperand(1);
if (!MO.isCImm())
return false;
return ARM::isBitFieldInvertedMask(MO.getCImm()->getZExtValue());
llvm_unreachable("GISelPredicateCode should have returned");
return false;
}
case GIPFP_MI_Predicate_vfp_f32imm: {
const auto &MO = MI.getOperand(1);
if (!MO.isFPImm())
return false;
return ARM_AM::getFP32Imm(MO.getFPImm()->getValueAPF()) != -1;
llvm_unreachable("GISelPredicateCode should have returned");
return false;
}
case GIPFP_MI_Predicate_vfp_f64imm: {
const auto &MO = MI.getOperand(1);
if (!MO.isFPImm())
return false;
return ARM_AM::getFP64Imm(MO.getFPImm()->getValueAPF()) != -1;
llvm_unreachable("GISelPredicateCode should have returned");
return false;
}
}
llvm_unreachable("Unknown predicate");
return false;
}
ARMInstructionSelector::ComplexMatcherMemFn
ARMInstructionSelector::ComplexPredicateFns[] = {
nullptr, // GICP_Invalid
};
// Custom renderers.
enum {
GICR_Invalid,
GICR_renderVFPF32Imm,
GICR_renderVFPF64Imm,
};
ARMInstructionSelector::CustomRendererFn
ARMInstructionSelector::CustomRenderers[] = {
nullptr, // GICR_Invalid
&ARMInstructionSelector::renderVFPF32Imm,
&ARMInstructionSelector::renderVFPF64Imm,
};
bool ARMInstructionSelector::selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const {
MachineFunction &MF = *I.getParent()->getParent();
MachineRegisterInfo &MRI = MF.getRegInfo();
const PredicateBitset AvailableFeatures = getAvailableFeatures();
NewMIVector OutMIs;
State.MIs.clear();
State.MIs.push_back(&I);
if (executeMatchTable(*this, OutMIs, State, ISelInfo, getMatchTable(), TII, MRI, TRI, RBI, AvailableFeatures, CoverageInfo)) {
return true;
}
return false;
}
const int64_t *ARMInstructionSelector::getMatchTable() const {
constexpr static int64_t MatchTable0[] = {
GIM_SwitchOpcode, /*MI*/0, /*[*/46, 216, /*)*//*default:*//*Label 65*/ 129518,
/*TargetOpcode::G_ADD*//*Label 0*/ 175,
/*TargetOpcode::G_SUB*//*Label 1*/ 8383,
/*TargetOpcode::G_MUL*//*Label 2*/ 11424,
/*TargetOpcode::G_SDIV*//*Label 3*/ 12269,
/*TargetOpcode::G_UDIV*//*Label 4*/ 12371, 0, 0, 0, 0,
/*TargetOpcode::G_AND*//*Label 5*/ 12473,
/*TargetOpcode::G_OR*//*Label 6*/ 15233,
/*TargetOpcode::G_XOR*//*Label 7*/ 20473, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/*TargetOpcode::G_CONCAT_VECTORS*//*Label 8*/ 21991, 0, 0,
/*TargetOpcode::G_BITCAST*//*Label 9*/ 22385, 0, 0,
/*TargetOpcode::G_INTRINSIC_TRUNC*//*Label 10*/ 33295,
/*TargetOpcode::G_INTRINSIC_ROUND*//*Label 11*/ 33551, 0, 0, 0, 0,
/*TargetOpcode::G_SEXTLOAD*//*Label 12*/ 33759, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/*TargetOpcode::G_FENCE*//*Label 13*/ 33905, 0, 0, 0,
/*TargetOpcode::G_INTRINSIC*//*Label 14*/ 33927,
/*TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS*//*Label 15*/ 94676,
/*TargetOpcode::G_ANYEXT*//*Label 16*/ 103121,
/*TargetOpcode::G_TRUNC*//*Label 17*/ 103256,
/*TargetOpcode::G_CONSTANT*//*Label 18*/ 103391,
/*TargetOpcode::G_FCONSTANT*//*Label 19*/ 103588, 0, 0,
/*TargetOpcode::G_SEXT*//*Label 20*/ 103667, 0,
/*TargetOpcode::G_ZEXT*//*Label 21*/ 103802,
/*TargetOpcode::G_SHL*//*Label 22*/ 104324,
/*TargetOpcode::G_LSHR*//*Label 23*/ 104433,
/*TargetOpcode::G_ASHR*//*Label 24*/ 104493, 0, 0,
/*TargetOpcode::G_ROTR*//*Label 25*/ 104711, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/*TargetOpcode::G_UMULH*//*Label 26*/ 104979,
/*TargetOpcode::G_SMULH*//*Label 27*/ 105204,
/*TargetOpcode::G_UADDSAT*//*Label 28*/ 105534,
/*TargetOpcode::G_SADDSAT*//*Label 29*/ 106163,
/*TargetOpcode::G_USUBSAT*//*Label 30*/ 107430,
/*TargetOpcode::G_SSUBSAT*//*Label 31*/ 108059, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/*TargetOpcode::G_FADD*//*Label 32*/ 109054,
/*TargetOpcode::G_FSUB*//*Label 33*/ 111200,
/*TargetOpcode::G_FMUL*//*Label 34*/ 112758,
/*TargetOpcode::G_FMA*//*Label 35*/ 113696, 0,
/*TargetOpcode::G_FDIV*//*Label 36*/ 115397, 0, 0, 0, 0, 0, 0, 0, 0,
/*TargetOpcode::G_FNEG*//*Label 37*/ 115563,
/*TargetOpcode::G_FPEXT*//*Label 38*/ 116881,
/*TargetOpcode::G_FPTRUNC*//*Label 39*/ 117085,
/*TargetOpcode::G_FPTOSI*//*Label 40*/ 117325,
/*TargetOpcode::G_FPTOUI*//*Label 41*/ 118564,
/*TargetOpcode::G_SITOFP*//*Label 42*/ 119803,
/*TargetOpcode::G_UITOFP*//*Label 43*/ 120385,
/*TargetOpcode::G_FABS*//*Label 44*/ 120967, 0, 0, 0,
/*TargetOpcode::G_FMINNUM*//*Label 45*/ 121567,
/*TargetOpcode::G_FMAXNUM*//*Label 46*/ 122087, 0, 0,
/*TargetOpcode::G_FMINIMUM*//*Label 47*/ 122607,
/*TargetOpcode::G_FMAXIMUM*//*Label 48*/ 123261, 0, 0,
/*TargetOpcode::G_SMIN*//*Label 49*/ 123915,
/*TargetOpcode::G_SMAX*//*Label 50*/ 124438,
/*TargetOpcode::G_UMIN*//*Label 51*/ 124961,
/*TargetOpcode::G_UMAX*//*Label 52*/ 125850,
/*TargetOpcode::G_ABS*//*Label 53*/ 126739, 0, 0,
/*TargetOpcode::G_BR*//*Label 54*/ 127168, 0, 0,
/*TargetOpcode::G_EXTRACT_VECTOR_ELT*//*Label 55*/ 127232, 0, 0, 0,
/*TargetOpcode::G_CTLZ*//*Label 56*/ 127374, 0,
/*TargetOpcode::G_CTPOP*//*Label 57*/ 127882,
/*TargetOpcode::G_BSWAP*//*Label 58*/ 127974,
/*TargetOpcode::G_BITREVERSE*//*Label 59*/ 128222,
/*TargetOpcode::G_FCEIL*//*Label 60*/ 128586, 0, 0,
/*TargetOpcode::G_FSQRT*//*Label 61*/ 128794,
/*TargetOpcode::G_FFLOOR*//*Label 62*/ 128924,
/*TargetOpcode::G_FRINT*//*Label 63*/ 129132,
/*TargetOpcode::G_FNEARBYINT*//*Label 64*/ 129388,
// Label 0: @175
GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 16, /*)*//*default:*//*Label 75*/ 8382,
/*GILLT_s32*//*Label 66*/ 196,
/*GILLT_s64*//*Label 67*/ 2179, 0,
/*GILLT_v2s32*//*Label 68*/ 2231,
/*GILLT_v2s64*//*Label 69*/ 2698, 0,
/*GILLT_v4s16*//*Label 70*/ 3726,
/*GILLT_v4s32*//*Label 71*/ 4193, 0, 0,
/*GILLT_v8s8*//*Label 72*/ 5778,
/*GILLT_v8s16*//*Label 73*/ 6245, 0, 0,
/*GILLT_v16s8*//*Label 74*/ 7830,
// Label 66: @196
GIM_Try, /*On fail goto*//*Label 76*/ 2178,
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
GIM_Try, /*On fail goto*//*Label 77*/ 273, // Rule ID 5770 //
GIM_CheckFeatures, GIFBS_HasV6_IsARM,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRRegClassID,
GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 255,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
GIM_CheckIsSafeToFold, /*InsnID*/1,
// (add:{ *:[i32] } (and:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 255:{ *:[i32] }), GPR:{ *:[i32] }:$Rn) => (UXTAB:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UXTAB,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
GIR_AddImm, /*InsnID*/0, /*Imm*/0,
GIR_AddImm, /*InsnID*/0, /*Imm*/14,
GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
GIR_EraseFromParent, /*InsnID*/0,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 5770,
GIR_Done,
// Label 77: @273
GIM_Try, /*On fail goto*//*Label 78*/ 340, // Rule ID 5771 //
GIM_CheckFeatures, GIFBS_HasV6_IsARM,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRRegClassID,
GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 65535,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
GIM_CheckIsSafeToFold, /*InsnID*/1,
// (add:{ *:[i32] } (and:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] }), GPR:{ *:[i32] }:$Rn) => (UXTAH:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UXTAH,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
GIR_AddImm, /*InsnID*/0, /*Imm*/0,
GIR_AddImm, /*InsnID*/0, /*Imm*/14,
GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
GIR_EraseFromParent, /*InsnID*/0,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 5771,
GIR_Done,
// Label 78: @340
GIM_Try, /*On fail goto*//*Label 79*/ 407, // Rule ID 5805 //
GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 255,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
GIM_CheckIsSafeToFold, /*InsnID*/1,
// (add:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 255:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn) => (t2UXTAB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UXTAB,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
GIR_AddImm, /*InsnID*/0, /*Imm*/0,
GIR_AddImm, /*InsnID*/0, /*Imm*/14,
GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
GIR_EraseFromParent, /*InsnID*/0,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 5805,
GIR_Done,
// Label 79: @407
GIM_Try, /*On fail goto*//*Label 80*/ 474, // Rule ID 5806 //
GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 65535,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
GIM_CheckIsSafeToFold, /*InsnID*/1,
// (add:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn) => (t2UXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UXTAH,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
GIR_AddImm, /*InsnID*/0, /*Imm*/0,
GIR_AddImm, /*InsnID*/0, /*Imm*/14,
GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
GIR_EraseFromParent, /*InsnID*/0,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 5806,
GIR_Done,
// Label 80: @474
GIM_Try, /*On fail goto*//*Label 81*/ 541, // Rule ID 2015 //
GIM_CheckFeatures, GIFBS_HasV6_IsARM,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRRegClassID,
GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 255,
GIM_CheckIsSafeToFold, /*InsnID*/1,
// (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (and:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 255:{ *:[i32] })) => (UXTAB:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UXTAB,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
GIR_AddImm, /*InsnID*/0, /*Imm*/0,
GIR_AddImm, /*InsnID*/0, /*Imm*/14,
GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
GIR_EraseFromParent, /*InsnID*/0,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 2015,
GIR_Done,
// Label 81: @541
GIM_Try, /*On fail goto*//*Label 82*/ 608, // Rule ID 2016 //
GIM_CheckFeatures, GIFBS_HasV6_IsARM,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRRegClassID,
GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 65535,
GIM_CheckIsSafeToFold, /*InsnID*/1,
// (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (and:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] })) => (UXTAH:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::UXTAH,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
GIR_AddImm, /*InsnID*/0, /*Imm*/0,
GIR_AddImm, /*InsnID*/0, /*Imm*/14,
GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
GIR_EraseFromParent, /*InsnID*/0,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 2016,
GIR_Done,
// Label 82: @608
GIM_Try, /*On fail goto*//*Label 83*/ 675, // Rule ID 2239 //
GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 255,
GIM_CheckIsSafeToFold, /*InsnID*/1,
// (add:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 255:{ *:[i32] })) => (t2UXTAB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UXTAB,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
GIR_AddImm, /*InsnID*/0, /*Imm*/0,
GIR_AddImm, /*InsnID*/0, /*Imm*/14,
GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
GIR_EraseFromParent, /*InsnID*/0,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 2239,
GIR_Done,
// Label 83: @675
GIM_Try, /*On fail goto*//*Label 84*/ 742, // Rule ID 2240 //
GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_AND,
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
GIM_CheckConstantInt, /*MI*/1, /*Op*/2, 65535,
GIM_CheckIsSafeToFold, /*InsnID*/1,
// (add:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] })) => (t2UXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2UXTAH,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
GIR_AddImm, /*InsnID*/0, /*Imm*/0,
GIR_AddImm, /*InsnID*/0, /*Imm*/14,
GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
GIR_EraseFromParent, /*InsnID*/0,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 2240,
GIR_Done,
// Label 84: @742
GIM_Try, /*On fail goto*//*Label 85*/ 852, // Rule ID 5549 //
GIM_CheckFeatures, GIFBS_HasV5TE_IsARM_UseMulOps,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ASHR,
GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 16,
GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ASHR,
GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
GIM_CheckConstantInt, /*MI*/3, /*Op*/2, 16,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
GIM_CheckIsSafeToFold, /*InsnID*/1,
GIM_CheckIsSafeToFold, /*InsnID*/2,
GIM_CheckIsSafeToFold, /*InsnID*/3,
// (add:{ *:[i32] } (mul:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, 16:{ *:[i32] })), GPR:{ *:[i32] }:$Ra) => (SMLATT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)
GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMLATT,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra
GIR_AddImm, /*InsnID*/0, /*Imm*/14,
GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
GIR_EraseFromParent, /*InsnID*/0,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 5549,
GIR_Done,
// Label 85: @852
GIM_Try, /*On fail goto*//*Label 86*/ 962, // Rule ID 5586 //
GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2_UseMulOps,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ASHR,
GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 16,
GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ASHR,
GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
GIM_CheckConstantInt, /*MI*/3, /*Op*/2, 16,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
GIM_CheckIsSafeToFold, /*InsnID*/1,
GIM_CheckIsSafeToFold, /*InsnID*/2,
GIM_CheckIsSafeToFold, /*InsnID*/3,
// (add:{ *:[i32] } (mul:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16:{ *:[i32] })), rGPR:{ *:[i32] }:$Ra) => (t2SMLATT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMLATT,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra
GIR_AddImm, /*InsnID*/0, /*Imm*/14,
GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
GIR_EraseFromParent, /*InsnID*/0,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 5586,
GIR_Done,
// Label 86: @962
GIM_Try, /*On fail goto*//*Label 87*/ 1072, // Rule ID 192 //
GIM_CheckFeatures, GIFBS_HasV5TE_IsARM_UseMulOps,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ASHR,
GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 16,
GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ASHR,
GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
GIM_CheckConstantInt, /*MI*/3, /*Op*/2, 16,
GIM_CheckIsSafeToFold, /*InsnID*/1,
GIM_CheckIsSafeToFold, /*InsnID*/2,
GIM_CheckIsSafeToFold, /*InsnID*/3,
// (add:{ *:[i32] } GPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, 16:{ *:[i32] }))) => (SMLATT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)
GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMLATT,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
GIR_AddImm, /*InsnID*/0, /*Imm*/14,
GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
GIR_EraseFromParent, /*InsnID*/0,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 192,
GIR_Done,
// Label 87: @1072
GIM_Try, /*On fail goto*//*Label 88*/ 1182, // Rule ID 528 //
GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2_UseMulOps,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ASHR,
GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
GIM_CheckConstantInt, /*MI*/2, /*Op*/2, 16,
GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
GIM_CheckOpcode, /*MI*/3, TargetOpcode::G_ASHR,
GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
GIM_CheckConstantInt, /*MI*/3, /*Op*/2, 16,
GIM_CheckIsSafeToFold, /*InsnID*/1,
GIM_CheckIsSafeToFold, /*InsnID*/2,
GIM_CheckIsSafeToFold, /*InsnID*/3,
// (add:{ *:[i32] } rGPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16:{ *:[i32] }))) => (t2SMLATT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMLATT,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
GIR_AddImm, /*InsnID*/0, /*Imm*/14,
GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
GIR_EraseFromParent, /*InsnID*/0,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 528,
GIR_Done,
// Label 88: @1182
GIM_Try, /*On fail goto*//*Label 89*/ 1236, // Rule ID 72 //
GIM_CheckFeatures, GIFBS_IsARM,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_mod_imm,
// MIs[1] Operand 1
// No operand predicates
GIM_CheckIsSafeToFold, /*InsnID*/1,
// (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm) => (ADDri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::ADDri,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
GIR_AddImm, /*InsnID*/0, /*Imm*/14,
GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
GIR_EraseFromParent, /*InsnID*/0,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 72,
GIR_Done,
// Label 89: @1236
GIM_Try, /*On fail goto*//*Label 90*/ 1290, // Rule ID 414 //
GIM_CheckFeatures, GIFBS_IsThumb2,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_t2_so_imm,
// MIs[1] Operand 1
// No operand predicates
GIM_CheckIsSafeToFold, /*InsnID*/1,
// (add:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm) => (t2ADDri:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ADDri,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
GIR_AddImm, /*InsnID*/0, /*Imm*/14,
GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
GIR_EraseFromParent, /*InsnID*/0,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 414,
GIR_Done,
// Label 90: @1290
GIM_Try, /*On fail goto*//*Label 91*/ 1340, // Rule ID 415 //
GIM_CheckFeatures, GIFBS_IsThumb2,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_imm0_4095,
// MIs[1] Operand 1
// No operand predicates
GIM_CheckIsSafeToFold, /*InsnID*/1,
// (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_imm0_4095>>:$imm) => (t2ADDri12:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ADDri12,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
GIR_AddImm, /*InsnID*/0, /*Imm*/14,
GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
GIR_EraseFromParent, /*InsnID*/0,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 415,
GIR_Done,
// Label 91: @1340
GIM_Try, /*On fail goto*//*Label 92*/ 1412, // Rule ID 171 //
GIM_CheckFeatures, GIFBS_HasV6_IsARM_UseMulOps,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
GIM_CheckIsSafeToFold, /*InsnID*/1,
// (add:{ *:[i32] } (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm), GPRnopc:{ *:[i32] }:$Ra) => (MLA:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra)
GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MLA,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra
GIR_AddImm, /*InsnID*/0, /*Imm*/14,
GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
GIR_EraseFromParent, /*InsnID*/0,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 171,
GIR_Done,
// Label 92: @1412
GIM_Try, /*On fail goto*//*Label 93*/ 1484, // Rule ID 172 //
GIM_CheckFeatures, GIFBS_IsARM_NoV6,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
GIM_CheckIsSafeToFold, /*InsnID*/1,
// (add:{ *:[i32] } (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm), GPRnopc:{ *:[i32] }:$Ra) => (MLAv5:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra)
GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MLAv5,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra
GIR_AddImm, /*InsnID*/0, /*Imm*/14,
GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
GIR_EraseFromParent, /*InsnID*/0,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 172,
GIR_Done,
// Label 93: @1484
GIM_Try, /*On fail goto*//*Label 94*/ 1552, // Rule ID 510 //
GIM_CheckFeatures, GIFBS_IsThumb2_UseMulOps,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
GIM_CheckIsSafeToFold, /*InsnID*/1,
// (add:{ *:[i32] } (mul:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm), rGPR:{ *:[i32] }:$Ra) => (t2MLA:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MLA,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra
GIR_AddImm, /*InsnID*/0, /*Imm*/14,
GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
GIR_EraseFromParent, /*InsnID*/0,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 510,
GIR_Done,
// Label 94: @1552
GIM_Try, /*On fail goto*//*Label 95*/ 1620, // Rule ID 180 //
GIM_CheckFeatures, GIFBS_HasV6_IsARM_UseMulOps,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SMULH,
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRRegClassID,
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::GPRRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
GIM_CheckIsSafeToFold, /*InsnID*/1,
// (add:{ *:[i32] } (mulhs:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm), GPR:{ *:[i32] }:$Ra) => (SMMLA:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)
GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMMLA,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra
GIR_AddImm, /*InsnID*/0, /*Imm*/14,
GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
GIR_EraseFromParent, /*InsnID*/0,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 180,
GIR_Done,
// Label 95: @1620
GIM_Try, /*On fail goto*//*Label 96*/ 1688, // Rule ID 516 //
GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2_UseMulOps,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SMULH,
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
GIM_CheckIsSafeToFold, /*InsnID*/1,
// (add:{ *:[i32] } (mulhs:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn), rGPR:{ *:[i32] }:$Ra) => (t2SMMLA:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMMLA,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Ra
GIR_AddImm, /*InsnID*/0, /*Imm*/14,
GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
GIR_EraseFromParent, /*InsnID*/0,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 516,
GIR_Done,
// Label 96: @1688
GIM_Try, /*On fail goto*//*Label 97*/ 1760, // Rule ID 5543 //
GIM_CheckFeatures, GIFBS_HasV6_IsARM_UseMulOps,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
GIM_CheckIsSafeToFold, /*InsnID*/1,
// (add:{ *:[i32] } GPRnopc:{ *:[i32] }:$Ra, (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)) => (MLA:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra)
GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MLA,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
GIR_AddImm, /*InsnID*/0, /*Imm*/14,
GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
GIR_EraseFromParent, /*InsnID*/0,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 5543,
GIR_Done,
// Label 97: @1760
GIM_Try, /*On fail goto*//*Label 98*/ 1832, // Rule ID 5544 //
GIM_CheckFeatures, GIFBS_IsARM_NoV6,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
GIM_CheckIsSafeToFold, /*InsnID*/1,
// (add:{ *:[i32] } GPRnopc:{ *:[i32] }:$Ra, (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)) => (MLAv5:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra)
GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::MLAv5,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
GIR_AddImm, /*InsnID*/0, /*Imm*/14,
GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
GIR_EraseFromParent, /*InsnID*/0,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 5544,
GIR_Done,
// Label 98: @1832
GIM_Try, /*On fail goto*//*Label 99*/ 1900, // Rule ID 5581 //
GIM_CheckFeatures, GIFBS_IsThumb2_UseMulOps,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
GIM_CheckIsSafeToFold, /*InsnID*/1,
// (add:{ *:[i32] } rGPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)) => (t2MLA:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2MLA,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
GIR_AddImm, /*InsnID*/0, /*Imm*/14,
GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
GIR_EraseFromParent, /*InsnID*/0,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 5581,
GIR_Done,
// Label 99: @1900
GIM_Try, /*On fail goto*//*Label 100*/ 1968, // Rule ID 5545 //
GIM_CheckFeatures, GIFBS_HasV6_IsARM_UseMulOps,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SMULH,
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::GPRRegClassID,
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::GPRRegClassID,
GIM_CheckIsSafeToFold, /*InsnID*/1,
// (add:{ *:[i32] } GPR:{ *:[i32] }:$Ra, (mulhs:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)) => (SMMLA:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)
GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::SMMLA,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
GIR_AddImm, /*InsnID*/0, /*Imm*/14,
GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
GIR_EraseFromParent, /*InsnID*/0,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 5545,
GIR_Done,
// Label 100: @1968
GIM_Try, /*On fail goto*//*Label 101*/ 2036, // Rule ID 5582 //
GIM_CheckFeatures, GIFBS_HasDSP_IsThumb2_UseMulOps,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::rGPRRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SMULH,
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
GIM_CheckIsSafeToFold, /*InsnID*/1,
// (add:{ *:[i32] } rGPR:{ *:[i32] }:$Ra, (mulhs:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)) => (t2SMMLA:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2SMMLA,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Ra
GIR_AddImm, /*InsnID*/0, /*Imm*/14,
GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
GIR_EraseFromParent, /*InsnID*/0,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 5582,
GIR_Done,
// Label 101: @2036
GIM_Try, /*On fail goto*//*Label 102*/ 2083, // Rule ID 73 //
GIM_CheckFeatures, GIFBS_IsARM,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRRegClassID,
// (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (ADDrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::ADDrr,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
GIR_AddImm, /*InsnID*/0, /*Imm*/14,
GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
GIR_EraseFromParent, /*InsnID*/0,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 73,
GIR_Done,
// Label 102: @2083
GIM_Try, /*On fail goto*//*Label 103*/ 2130, // Rule ID 416 //
GIM_CheckFeatures, GIFBS_IsThumb2,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::GPRnopcRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::rGPRRegClassID,
// (add:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2ADDrr:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ADDrr,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rn
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rm
GIR_AddImm, /*InsnID*/0, /*Imm*/14,
GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
GIR_EraseFromParent, /*InsnID*/0,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 416,
GIR_Done,
// Label 103: @2130
GIM_Try, /*On fail goto*//*Label 104*/ 2177, // Rule ID 5563 //
GIM_CheckFeatures, GIFBS_IsThumb2,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::GPRnopcRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::rGPRRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::GPRnopcRegClassID,
// (add:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn) => (t2ADDrr:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::t2ADDrr,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Rd
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Rn
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Rm
GIR_AddImm, /*InsnID*/0, /*Imm*/14,
GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
GIR_EraseFromParent, /*InsnID*/0,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 5563,
GIR_Done,
// Label 104: @2177
GIM_Reject,
// Label 76: @2178
GIM_Reject,
// Label 67: @2179
GIM_Try, /*On fail goto*//*Label 105*/ 2230, // Rule ID 778 //
GIM_CheckFeatures, GIFBS_HasNEON,
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
// (add:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) => (VADDv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)
GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDv1i64,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
GIR_AddImm, /*InsnID*/0, /*Imm*/14,
GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
GIR_EraseFromParent, /*InsnID*/0,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 778,
GIR_Done,
// Label 105: @2230
GIM_Reject,
// Label 68: @2231
GIM_Try, /*On fail goto*//*Label 106*/ 2697,
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
GIM_Try, /*On fail goto*//*Label 107*/ 2316, // Rule ID 5702 //
GIM_CheckFeatures, GIFBS_HasNEON,
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds,
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
GIM_CheckIsSafeToFold, /*InsnID*/1,
// (add:{ *:[v2i32] } (intrinsic_wo_chain:{ *:[v2i32] } 2574:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm), DPR:{ *:[v2i32] }:$src1) => (VABAsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv2i32,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
GIR_AddImm, /*InsnID*/0, /*Imm*/14,
GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
GIR_EraseFromParent, /*InsnID*/0,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 5702,
GIR_Done,
// Label 107: @2316
GIM_Try, /*On fail goto*//*Label 108*/ 2387, // Rule ID 5708 //
GIM_CheckFeatures, GIFBS_HasNEON,
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu,
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
GIM_CheckIsSafeToFold, /*InsnID*/1,
// (add:{ *:[v2i32] } (intrinsic_wo_chain:{ *:[v2i32] } 2575:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm), DPR:{ *:[v2i32] }:$src1) => (VABAuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv2i32,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
GIR_AddImm, /*InsnID*/0, /*Imm*/14,
GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
GIR_EraseFromParent, /*InsnID*/0,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 5708,
GIR_Done,
// Label 108: @2387
GIM_Try, /*On fail goto*//*Label 109*/ 2458, // Rule ID 1199 //
GIM_CheckFeatures, GIFBS_HasNEON,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabds,
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
GIM_CheckIsSafeToFold, /*InsnID*/1,
// (add:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, (intrinsic_wo_chain:{ *:[v2i32] } 2574:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)) => (VABAsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAsv2i32,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
GIR_AddImm, /*InsnID*/0, /*Imm*/14,
GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
GIR_EraseFromParent, /*InsnID*/0,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 1199,
GIR_Done,
// Label 109: @2458
GIM_Try, /*On fail goto*//*Label 110*/ 2529, // Rule ID 1205 //
GIM_CheckFeatures, GIFBS_HasNEON,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC,
GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::arm_neon_vabdu,
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/ARM::DPRRegClassID,
GIM_CheckIsSafeToFold, /*InsnID*/1,
// (add:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, (intrinsic_wo_chain:{ *:[v2i32] } 2575:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)) => (VABAuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABAuv2i32,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
GIR_AddImm, /*InsnID*/0, /*Imm*/14,
GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
GIR_EraseFromParent, /*InsnID*/0,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 1205,
GIR_Done,
// Label 110: @2529
GIM_Try, /*On fail goto*//*Label 111*/ 2593, // Rule ID 5632 //
GIM_CheckFeatures, GIFBS_HasNEON,
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
GIM_CheckIsSafeToFold, /*InsnID*/1,
// (add:{ *:[v2i32] } (mul:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm), DPR:{ *:[v2i32] }:$src1) => (VMLAv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv2i32,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
GIR_AddImm, /*InsnID*/0, /*Imm*/14,
GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
GIR_EraseFromParent, /*InsnID*/0,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 5632,
GIR_Done,
// Label 111: @2593
GIM_Try, /*On fail goto*//*Label 112*/ 2657, // Rule ID 905 //
GIM_CheckFeatures, GIFBS_HasNEON,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/ARM::DPRRegClassID,
GIM_CheckIsSafeToFold, /*InsnID*/1,
// (add:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, (mul:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)) => (VMLAv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VMLAv2i32,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
GIR_AddImm, /*InsnID*/0, /*Imm*/14,
GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
GIR_EraseFromParent, /*InsnID*/0,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 905,
GIR_Done,
// Label 112: @2657
GIM_Try, /*On fail goto*//*Label 113*/ 2696, // Rule ID 774 //
GIM_CheckFeatures, GIFBS_HasNEON,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::DPRRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::DPRRegClassID,
// (add:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VADDv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDv2i32,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
GIR_AddImm, /*InsnID*/0, /*Imm*/14,
GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
GIR_EraseFromParent, /*InsnID*/0,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 774,
GIR_Done,
// Label 113: @2696
GIM_Reject,
// Label 106: @2697
GIM_Reject,
// Label 69: @2698
GIM_Try, /*On fail goto*//*Label 114*/ 3725,
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::QPRRegClassID,
GIM_Try, /*On fail goto*//*Label 115*/ 2796, // Rule ID 5714 //
GIM_CheckFeatures, GIFBS_HasNEON,
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::arm_neon_vabds,
GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v2s32,
GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/ARM::DPRRegClassID,
GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/ARM::DPRRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
GIM_CheckIsSafeToFold, /*InsnID*/1,
GIM_CheckIsSafeToFold, /*InsnID*/2,
// (add:{ *:[v2i64] } (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 2574:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)), QPR:{ *:[v2i64] }:$src1) => (VABALsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALsv2i64,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm
GIR_AddImm, /*InsnID*/0, /*Imm*/14,
GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
GIR_EraseFromParent, /*InsnID*/0,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 5714,
GIR_Done,
// Label 115: @2796
GIM_Try, /*On fail goto*//*Label 116*/ 2880, // Rule ID 5717 //
GIM_CheckFeatures, GIFBS_HasNEON,
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::arm_neon_vabdu,
GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v2s32,
GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/ARM::DPRRegClassID,
GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/ARM::DPRRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
GIM_CheckIsSafeToFold, /*InsnID*/1,
GIM_CheckIsSafeToFold, /*InsnID*/2,
// (add:{ *:[v2i64] } (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 2575:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)), QPR:{ *:[v2i64] }:$src1) => (VABALuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALuv2i64,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm
GIR_AddImm, /*InsnID*/0, /*Imm*/14,
GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
GIR_EraseFromParent, /*InsnID*/0,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 5717,
GIR_Done,
// Label 116: @2880
GIM_Try, /*On fail goto*//*Label 117*/ 2964, // Rule ID 1211 //
GIM_CheckFeatures, GIFBS_HasNEON,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::arm_neon_vabds,
GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v2s32,
GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/ARM::DPRRegClassID,
GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/ARM::DPRRegClassID,
GIM_CheckIsSafeToFold, /*InsnID*/1,
GIM_CheckIsSafeToFold, /*InsnID*/2,
// (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 2574:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm))) => (VABALsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALsv2i64,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm
GIR_AddImm, /*InsnID*/0, /*Imm*/14,
GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
GIR_EraseFromParent, /*InsnID*/0,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 1211,
GIR_Done,
// Label 117: @2964
GIM_Try, /*On fail goto*//*Label 118*/ 3048, // Rule ID 1214 //
GIM_CheckFeatures, GIFBS_HasNEON,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_INTRINSIC,
GIM_CheckNumOperands, /*MI*/2, /*Expected*/4,
GIM_CheckIntrinsicID, /*MI*/2, /*Op*/1, Intrinsic::arm_neon_vabdu,
GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_v2s32,
GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/ARM::DPRRegClassID,
GIM_CheckRegBankForClass, /*MI*/2, /*Op*/3, /*RC*/ARM::DPRRegClassID,
GIM_CheckIsSafeToFold, /*InsnID*/1,
GIM_CheckIsSafeToFold, /*InsnID*/2,
// (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 2575:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm))) => (VABALuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VABALuv2i64,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vn
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/3, // Vm
GIR_AddImm, /*InsnID*/0, /*Imm*/14,
GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
GIR_EraseFromParent, /*InsnID*/0,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 1214,
GIR_Done,
// Label 118: @3048
GIM_Try, /*On fail goto*//*Label 119*/ 3113, // Rule ID 798 //
GIM_CheckFeatures, GIFBS_HasNEON,
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT,
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ANYEXT,
GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
GIM_CheckIsSafeToFold, /*InsnID*/1,
GIM_CheckIsSafeToFold, /*InsnID*/2,
// (add:{ *:[v2i64] } (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VADDLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDLuv2i64,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
GIR_AddImm, /*InsnID*/0, /*Imm*/14,
GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
GIR_EraseFromParent, /*InsnID*/0,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 798,
GIR_Done,
// Label 119: @3113
GIM_Try, /*On fail goto*//*Label 120*/ 3178, // Rule ID 797 //
GIM_CheckFeatures, GIFBS_HasNEON,
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT,
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
GIM_CheckIsSafeToFold, /*InsnID*/1,
GIM_CheckIsSafeToFold, /*InsnID*/2,
// (add:{ *:[v2i64] } (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VADDLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDLuv2i64,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
GIR_AddImm, /*InsnID*/0, /*Imm*/14,
GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
GIR_EraseFromParent, /*InsnID*/0,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 797,
GIR_Done,
// Label 120: @3178
GIM_Try, /*On fail goto*//*Label 121*/ 3243, // Rule ID 786 //
GIM_CheckFeatures, GIFBS_HasNEON,
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_SEXT,
GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
GIM_CheckIsSafeToFold, /*InsnID*/1,
GIM_CheckIsSafeToFold, /*InsnID*/2,
// (add:{ *:[v2i64] } (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VADDLsv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDLsv2i64,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
GIR_AddImm, /*InsnID*/0, /*Imm*/14,
GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
GIR_EraseFromParent, /*InsnID*/0,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 786,
GIR_Done,
// Label 121: @3243
GIM_Try, /*On fail goto*//*Label 122*/ 3308, // Rule ID 796 //
GIM_CheckFeatures, GIFBS_HasNEON,
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ANYEXT,
GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
GIM_CheckIsSafeToFold, /*InsnID*/1,
GIM_CheckIsSafeToFold, /*InsnID*/2,
// (add:{ *:[v2i64] } (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VADDLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDLuv2i64,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
GIR_AddImm, /*InsnID*/0, /*Imm*/14,
GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
GIR_EraseFromParent, /*InsnID*/0,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 796,
GIR_Done,
// Label 122: @3308
GIM_Try, /*On fail goto*//*Label 123*/ 3373, // Rule ID 795 //
GIM_CheckFeatures, GIFBS_HasNEON,
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_ZEXT,
GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/ARM::DPRRegClassID,
GIM_CheckIsSafeToFold, /*InsnID*/1,
GIM_CheckIsSafeToFold, /*InsnID*/2,
// (add:{ *:[v2i64] } (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VADDLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDLuv2i64,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
GIR_AddImm, /*InsnID*/0, /*Imm*/14,
GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
GIR_EraseFromParent, /*InsnID*/0,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 795,
GIR_Done,
// Label 123: @3373
GIM_Try, /*On fail goto*//*Label 124*/ 3425, // Rule ID 5611 //
GIM_CheckFeatures, GIFBS_HasNEON,
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT,
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
GIM_CheckIsSafeToFold, /*InsnID*/1,
// (add:{ *:[v2i64] } (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm), QPR:{ *:[v2i64] }:$Vn) => (VADDWuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWuv2i64,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
GIR_AddImm, /*InsnID*/0, /*Imm*/14,
GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
GIR_EraseFromParent, /*InsnID*/0,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 5611,
GIR_Done,
// Label 124: @3425
GIM_Try, /*On fail goto*//*Label 125*/ 3477, // Rule ID 5605 //
GIM_CheckFeatures, GIFBS_HasNEON,
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
GIM_CheckIsSafeToFold, /*InsnID*/1,
// (add:{ *:[v2i64] } (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm), QPR:{ *:[v2i64] }:$Vn) => (VADDWsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWsv2i64,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
GIR_AddImm, /*InsnID*/0, /*Imm*/14,
GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
GIR_EraseFromParent, /*InsnID*/0,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 5605,
GIR_Done,
// Label 125: @3477
GIM_Try, /*On fail goto*//*Label 126*/ 3529, // Rule ID 5610 //
GIM_CheckFeatures, GIFBS_HasNEON,
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
GIM_CheckIsSafeToFold, /*InsnID*/1,
// (add:{ *:[v2i64] } (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm), QPR:{ *:[v2i64] }:$Vn) => (VADDWuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWuv2i64,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vn
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
GIR_AddImm, /*InsnID*/0, /*Imm*/14,
GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
GIR_EraseFromParent, /*InsnID*/0,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 5610,
GIR_Done,
// Label 126: @3529
GIM_Try, /*On fail goto*//*Label 127*/ 3581, // Rule ID 807 //
GIM_CheckFeatures, GIFBS_HasNEON,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ANYEXT,
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
GIM_CheckIsSafeToFold, /*InsnID*/1,
// (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VADDWuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWuv2i64,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
GIR_AddImm, /*InsnID*/0, /*Imm*/14,
GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
GIR_EraseFromParent, /*InsnID*/0,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 807,
GIR_Done,
// Label 127: @3581
GIM_Try, /*On fail goto*//*Label 128*/ 3633, // Rule ID 801 //
GIM_CheckFeatures, GIFBS_HasNEON,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SEXT,
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
GIM_CheckIsSafeToFold, /*InsnID*/1,
// (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VADDWsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWsv2i64,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
GIR_AddImm, /*InsnID*/0, /*Imm*/14,
GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
GIR_EraseFromParent, /*InsnID*/0,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 801,
GIR_Done,
// Label 128: @3633
GIM_Try, /*On fail goto*//*Label 129*/ 3685, // Rule ID 806 //
GIM_CheckFeatures, GIFBS_HasNEON,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ZEXT,
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/ARM::DPRRegClassID,
GIM_CheckIsSafeToFold, /*InsnID*/1,
// (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VADDWuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDWuv2i64,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
GIR_AddImm, /*InsnID*/0, /*Imm*/14,
GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
GIR_EraseFromParent, /*InsnID*/0,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 806,
GIR_Done,
// Label 129: @3685
GIM_Try, /*On fail goto*//*Label 130*/ 3724, // Rule ID 779 //
GIM_CheckFeatures, GIFBS_HasNEON,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/ARM::QPRRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/ARM::QPRRegClassID,
// (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) => (VADDv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)
GIR_BuildMI, /*InsnID*/0, /*Opcode*/ARM::VADDv2i64,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // Vd
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Vn
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
GIR_AddImm, /*InsnID*/0, /*Imm*/14,
GIR_AddRegister, /*InsnID*/0, ARM::NoRegister, /*AddRegisterRegFlags*/0,
GIR_EraseFromParent, /*InsnID*/0,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 779,
GIR_Done,
// Label 130: @3724
GIM_Reject,
// Label 114: @3725
GIM_Reject,
// Label 70: @3726
GIM_Try, /*On fail goto*//*Label 131*/ 4192,
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/ARM::DPRRegClassID,
GIM_Try, /*On fail goto*//*Label 132*/ 3811, // Rule ID 5701 //
GIM_CheckFeatures, GIFBS_HasNEON,