| //===- MipsISelLowering.cpp - Mips DAG Lowering Implementation ------------===// |
| // |
| // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
| // See https://llvm.org/LICENSE.txt for license information. |
| // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
| // |
| //===----------------------------------------------------------------------===// |
| // |
| // This file defines the interfaces that Mips uses to lower LLVM code into a |
| // selection DAG. |
| // |
| //===----------------------------------------------------------------------===// |
| |
| #include "MipsISelLowering.h" |
| #include "MCTargetDesc/MipsBaseInfo.h" |
| #include "MCTargetDesc/MipsInstPrinter.h" |
| #include "MCTargetDesc/MipsMCTargetDesc.h" |
| #include "MipsCCState.h" |
| #include "MipsInstrInfo.h" |
| #include "MipsMachineFunction.h" |
| #include "MipsRegisterInfo.h" |
| #include "MipsSubtarget.h" |
| #include "MipsTargetMachine.h" |
| #include "MipsTargetObjectFile.h" |
| #include "llvm/ADT/APFloat.h" |
| #include "llvm/ADT/ArrayRef.h" |
| #include "llvm/ADT/SmallVector.h" |
| #include "llvm/ADT/Statistic.h" |
| #include "llvm/ADT/StringRef.h" |
| #include "llvm/ADT/StringSwitch.h" |
| #include "llvm/CodeGen/CallingConvLower.h" |
| #include "llvm/CodeGen/FunctionLoweringInfo.h" |
| #include "llvm/CodeGen/ISDOpcodes.h" |
| #include "llvm/CodeGen/MachineBasicBlock.h" |
| #include "llvm/CodeGen/MachineFrameInfo.h" |
| #include "llvm/CodeGen/MachineFunction.h" |
| #include "llvm/CodeGen/MachineInstr.h" |
| #include "llvm/CodeGen/MachineInstrBuilder.h" |
| #include "llvm/CodeGen/MachineJumpTableInfo.h" |
| #include "llvm/CodeGen/MachineMemOperand.h" |
| #include "llvm/CodeGen/MachineOperand.h" |
| #include "llvm/CodeGen/MachineRegisterInfo.h" |
| #include "llvm/CodeGen/RuntimeLibcalls.h" |
| #include "llvm/CodeGen/SelectionDAG.h" |
| #include "llvm/CodeGen/SelectionDAGNodes.h" |
| #include "llvm/CodeGen/TargetFrameLowering.h" |
| #include "llvm/CodeGen/TargetInstrInfo.h" |
| #include "llvm/CodeGen/TargetRegisterInfo.h" |
| #include "llvm/CodeGen/ValueTypes.h" |
| #include "llvm/IR/CallingConv.h" |
| #include "llvm/IR/Constants.h" |
| #include "llvm/IR/DataLayout.h" |
| #include "llvm/IR/DebugLoc.h" |
| #include "llvm/IR/DerivedTypes.h" |
| #include "llvm/IR/Function.h" |
| #include "llvm/IR/GlobalValue.h" |
| #include "llvm/IR/Type.h" |
| #include "llvm/IR/Value.h" |
| #include "llvm/MC/MCContext.h" |
| #include "llvm/MC/MCRegisterInfo.h" |
| #include "llvm/Support/Casting.h" |
| #include "llvm/Support/CodeGen.h" |
| #include "llvm/Support/CommandLine.h" |
| #include "llvm/Support/Compiler.h" |
| #include "llvm/Support/ErrorHandling.h" |
| #include "llvm/Support/MachineValueType.h" |
| #include "llvm/Support/MathExtras.h" |
| #include "llvm/Target/TargetMachine.h" |
| #include "llvm/Target/TargetOptions.h" |
| #include <algorithm> |
| #include <cassert> |
| #include <cctype> |
| #include <cstdint> |
| #include <deque> |
| #include <iterator> |
| #include <utility> |
| #include <vector> |
| |
| using namespace llvm; |
| |
| #define DEBUG_TYPE "mips-lower" |
| |
| STATISTIC(NumTailCalls, "Number of tail calls"); |
| |
| static cl::opt<bool> |
| NoZeroDivCheck("mno-check-zero-division", cl::Hidden, |
| cl::desc("MIPS: Don't trap on integer division by zero."), |
| cl::init(false)); |
| |
| extern cl::opt<bool> EmitJalrReloc; |
| |
| static const MCPhysReg Mips64DPRegs[8] = { |
| Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64, |
| Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64 |
| }; |
| |
| // If I is a shifted mask, set the size (Size) and the first bit of the |
| // mask (Pos), and return true. |
| // For example, if I is 0x003ff800, (Pos, Size) = (11, 11). |
| static bool isShiftedMask(uint64_t I, uint64_t &Pos, uint64_t &Size) { |
| if (!isShiftedMask_64(I)) |
| return false; |
| |
| Size = countPopulation(I); |
| Pos = countTrailingZeros(I); |
| return true; |
| } |
| |
| // The MIPS MSA ABI passes vector arguments in the integer register set. |
| // The number of integer registers used is dependant on the ABI used. |
| MVT MipsTargetLowering::getRegisterTypeForCallingConv(LLVMContext &Context, |
| CallingConv::ID CC, |
| EVT VT) const { |
| if (!VT.isVector()) |
| return getRegisterType(Context, VT); |
| |
| return Subtarget.isABI_O32() || VT.getSizeInBits() == 32 ? MVT::i32 |
| : MVT::i64; |
| } |
| |
| unsigned MipsTargetLowering::getNumRegistersForCallingConv(LLVMContext &Context, |
| CallingConv::ID CC, |
| EVT VT) const { |
| if (VT.isVector()) |
| return std::max(((unsigned)VT.getSizeInBits() / |
| (Subtarget.isABI_O32() ? 32 : 64)), |
| 1U); |
| return MipsTargetLowering::getNumRegisters(Context, VT); |
| } |
| |
| unsigned MipsTargetLowering::getVectorTypeBreakdownForCallingConv( |
| LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, |
| unsigned &NumIntermediates, MVT &RegisterVT) const { |
| // Break down vector types to either 2 i64s or 4 i32s. |
| RegisterVT = getRegisterTypeForCallingConv(Context, CC, VT); |
| IntermediateVT = RegisterVT; |
| NumIntermediates = VT.getSizeInBits() < RegisterVT.getSizeInBits() |
| ? VT.getVectorNumElements() |
| : VT.getSizeInBits() / RegisterVT.getSizeInBits(); |
| |
| return NumIntermediates; |
| } |
| |
| SDValue MipsTargetLowering::getGlobalReg(SelectionDAG &DAG, EVT Ty) const { |
| MipsFunctionInfo *FI = DAG.getMachineFunction().getInfo<MipsFunctionInfo>(); |
| return DAG.getRegister(FI->getGlobalBaseReg(), Ty); |
| } |
| |
| SDValue MipsTargetLowering::getTargetNode(GlobalAddressSDNode *N, EVT Ty, |
| SelectionDAG &DAG, |
| unsigned Flag) const { |
| return DAG.getTargetGlobalAddress(N->getGlobal(), SDLoc(N), Ty, 0, Flag); |
| } |
| |
| SDValue MipsTargetLowering::getTargetNode(ExternalSymbolSDNode *N, EVT Ty, |
| SelectionDAG &DAG, |
| unsigned Flag) const { |
| return DAG.getTargetExternalSymbol(N->getSymbol(), Ty, Flag); |
| } |
| |
| SDValue MipsTargetLowering::getTargetNode(BlockAddressSDNode *N, EVT Ty, |
| SelectionDAG &DAG, |
| unsigned Flag) const { |
| return DAG.getTargetBlockAddress(N->getBlockAddress(), Ty, 0, Flag); |
| } |
| |
| SDValue MipsTargetLowering::getTargetNode(JumpTableSDNode *N, EVT Ty, |
| SelectionDAG &DAG, |
| unsigned Flag) const { |
| return DAG.getTargetJumpTable(N->getIndex(), Ty, Flag); |
| } |
| |
| SDValue MipsTargetLowering::getTargetNode(ConstantPoolSDNode *N, EVT Ty, |
| SelectionDAG &DAG, |
| unsigned Flag) const { |
| return DAG.getTargetConstantPool(N->getConstVal(), Ty, N->getAlignment(), |
| N->getOffset(), Flag); |
| } |
| |
| const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const { |
| switch ((MipsISD::NodeType)Opcode) { |
| case MipsISD::FIRST_NUMBER: break; |
| case MipsISD::JmpLink: return "MipsISD::JmpLink"; |
| case MipsISD::TailCall: return "MipsISD::TailCall"; |
| case MipsISD::Highest: return "MipsISD::Highest"; |
| case MipsISD::Higher: return "MipsISD::Higher"; |
| case MipsISD::Hi: return "MipsISD::Hi"; |
| case MipsISD::Lo: return "MipsISD::Lo"; |
| case MipsISD::GotHi: return "MipsISD::GotHi"; |
| case MipsISD::TlsHi: return "MipsISD::TlsHi"; |
| case MipsISD::GPRel: return "MipsISD::GPRel"; |
| case MipsISD::ThreadPointer: return "MipsISD::ThreadPointer"; |
| case MipsISD::Ret: return "MipsISD::Ret"; |
| case MipsISD::ERet: return "MipsISD::ERet"; |
| case MipsISD::EH_RETURN: return "MipsISD::EH_RETURN"; |
| case MipsISD::FMS: return "MipsISD::FMS"; |
| case MipsISD::FPBrcond: return "MipsISD::FPBrcond"; |
| case MipsISD::FPCmp: return "MipsISD::FPCmp"; |
| case MipsISD::FSELECT: return "MipsISD::FSELECT"; |
| case MipsISD::MTC1_D64: return "MipsISD::MTC1_D64"; |
| case MipsISD::CMovFP_T: return "MipsISD::CMovFP_T"; |
| case MipsISD::CMovFP_F: return "MipsISD::CMovFP_F"; |
| case MipsISD::TruncIntFP: return "MipsISD::TruncIntFP"; |
| case MipsISD::MFHI: return "MipsISD::MFHI"; |
| case MipsISD::MFLO: return "MipsISD::MFLO"; |
| case MipsISD::MTLOHI: return "MipsISD::MTLOHI"; |
| case MipsISD::Mult: return "MipsISD::Mult"; |
| case MipsISD::Multu: return "MipsISD::Multu"; |
| case MipsISD::MAdd: return "MipsISD::MAdd"; |
| case MipsISD::MAddu: return "MipsISD::MAddu"; |
| case MipsISD::MSub: return "MipsISD::MSub"; |
| case MipsISD::MSubu: return "MipsISD::MSubu"; |
| case MipsISD::DivRem: return "MipsISD::DivRem"; |
| case MipsISD::DivRemU: return "MipsISD::DivRemU"; |
| case MipsISD::DivRem16: return "MipsISD::DivRem16"; |
| case MipsISD::DivRemU16: return "MipsISD::DivRemU16"; |
| case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64"; |
| case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64"; |
| case MipsISD::Wrapper: return "MipsISD::Wrapper"; |
| case MipsISD::DynAlloc: return "MipsISD::DynAlloc"; |
| case MipsISD::Sync: return "MipsISD::Sync"; |
| case MipsISD::Ext: return "MipsISD::Ext"; |
| case MipsISD::Ins: return "MipsISD::Ins"; |
| case MipsISD::CIns: return "MipsISD::CIns"; |
| case MipsISD::LWL: return "MipsISD::LWL"; |
| case MipsISD::LWR: return "MipsISD::LWR"; |
| case MipsISD::SWL: return "MipsISD::SWL"; |
| case MipsISD::SWR: return "MipsISD::SWR"; |
| case MipsISD::LDL: return "MipsISD::LDL"; |
| case MipsISD::LDR: return "MipsISD::LDR"; |
| case MipsISD::SDL: return "MipsISD::SDL"; |
| case MipsISD::SDR: return "MipsISD::SDR"; |
| case MipsISD::EXTP: return "MipsISD::EXTP"; |
| case MipsISD::EXTPDP: return "MipsISD::EXTPDP"; |
| case MipsISD::EXTR_S_H: return "MipsISD::EXTR_S_H"; |
| case MipsISD::EXTR_W: return "MipsISD::EXTR_W"; |
| case MipsISD::EXTR_R_W: return "MipsISD::EXTR_R_W"; |
| case MipsISD::EXTR_RS_W: return "MipsISD::EXTR_RS_W"; |
| case MipsISD::SHILO: return "MipsISD::SHILO"; |
| case MipsISD::MTHLIP: return "MipsISD::MTHLIP"; |
| case MipsISD::MULSAQ_S_W_PH: return "MipsISD::MULSAQ_S_W_PH"; |
| case MipsISD::MAQ_S_W_PHL: return "MipsISD::MAQ_S_W_PHL"; |
| case MipsISD::MAQ_S_W_PHR: return "MipsISD::MAQ_S_W_PHR"; |
| case MipsISD::MAQ_SA_W_PHL: return "MipsISD::MAQ_SA_W_PHL"; |
| case MipsISD::MAQ_SA_W_PHR: return "MipsISD::MAQ_SA_W_PHR"; |
| case MipsISD::DPAU_H_QBL: return "MipsISD::DPAU_H_QBL"; |
| case MipsISD::DPAU_H_QBR: return "MipsISD::DPAU_H_QBR"; |
| case MipsISD::DPSU_H_QBL: return "MipsISD::DPSU_H_QBL"; |
| case MipsISD::DPSU_H_QBR: return "MipsISD::DPSU_H_QBR"; |
| case MipsISD::DPAQ_S_W_PH: return "MipsISD::DPAQ_S_W_PH"; |
| case MipsISD::DPSQ_S_W_PH: return "MipsISD::DPSQ_S_W_PH"; |
| case MipsISD::DPAQ_SA_L_W: return "MipsISD::DPAQ_SA_L_W"; |
| case MipsISD::DPSQ_SA_L_W: return "MipsISD::DPSQ_SA_L_W"; |
| case MipsISD::DPA_W_PH: return "MipsISD::DPA_W_PH"; |
| case MipsISD::DPS_W_PH: return "MipsISD::DPS_W_PH"; |
| case MipsISD::DPAQX_S_W_PH: return "MipsISD::DPAQX_S_W_PH"; |
| case MipsISD::DPAQX_SA_W_PH: return "MipsISD::DPAQX_SA_W_PH"; |
| case MipsISD::DPAX_W_PH: return "MipsISD::DPAX_W_PH"; |
| case MipsISD::DPSX_W_PH: return "MipsISD::DPSX_W_PH"; |
| case MipsISD::DPSQX_S_W_PH: return "MipsISD::DPSQX_S_W_PH"; |
| case MipsISD::DPSQX_SA_W_PH: return "MipsISD::DPSQX_SA_W_PH"; |
| case MipsISD::MULSA_W_PH: return "MipsISD::MULSA_W_PH"; |
| case MipsISD::MULT: return "MipsISD::MULT"; |
| case MipsISD::MULTU: return "MipsISD::MULTU"; |
| case MipsISD::MADD_DSP: return "MipsISD::MADD_DSP"; |
| case MipsISD::MADDU_DSP: return "MipsISD::MADDU_DSP"; |
| case MipsISD::MSUB_DSP: return "MipsISD::MSUB_DSP"; |
| case MipsISD::MSUBU_DSP: return "MipsISD::MSUBU_DSP"; |
| case MipsISD::SHLL_DSP: return "MipsISD::SHLL_DSP"; |
| case MipsISD::SHRA_DSP: return "MipsISD::SHRA_DSP"; |
| case MipsISD::SHRL_DSP: return "MipsISD::SHRL_DSP"; |
| case MipsISD::SETCC_DSP: return "MipsISD::SETCC_DSP"; |
| case MipsISD::SELECT_CC_DSP: return "MipsISD::SELECT_CC_DSP"; |
| case MipsISD::VALL_ZERO: return "MipsISD::VALL_ZERO"; |
| case MipsISD::VANY_ZERO: return "MipsISD::VANY_ZERO"; |
| case MipsISD::VALL_NONZERO: return "MipsISD::VALL_NONZERO"; |
| case MipsISD::VANY_NONZERO: return "MipsISD::VANY_NONZERO"; |
| case MipsISD::VCEQ: return "MipsISD::VCEQ"; |
| case MipsISD::VCLE_S: return "MipsISD::VCLE_S"; |
| case MipsISD::VCLE_U: return "MipsISD::VCLE_U"; |
| case MipsISD::VCLT_S: return "MipsISD::VCLT_S"; |
| case MipsISD::VCLT_U: return "MipsISD::VCLT_U"; |
| case MipsISD::VEXTRACT_SEXT_ELT: return "MipsISD::VEXTRACT_SEXT_ELT"; |
| case MipsISD::VEXTRACT_ZEXT_ELT: return "MipsISD::VEXTRACT_ZEXT_ELT"; |
| case MipsISD::VNOR: return "MipsISD::VNOR"; |
| case MipsISD::VSHF: return "MipsISD::VSHF"; |
| case MipsISD::SHF: return "MipsISD::SHF"; |
| case MipsISD::ILVEV: return "MipsISD::ILVEV"; |
| case MipsISD::ILVOD: return "MipsISD::ILVOD"; |
| case MipsISD::ILVL: return "MipsISD::ILVL"; |
| case MipsISD::ILVR: return "MipsISD::ILVR"; |
| case MipsISD::PCKEV: return "MipsISD::PCKEV"; |
| case MipsISD::PCKOD: return "MipsISD::PCKOD"; |
| case MipsISD::INSVE: return "MipsISD::INSVE"; |
| } |
| return nullptr; |
| } |
| |
| MipsTargetLowering::MipsTargetLowering(const MipsTargetMachine &TM, |
| const MipsSubtarget &STI) |
| : TargetLowering(TM), Subtarget(STI), ABI(TM.getABI()) { |
| // Mips does not have i1 type, so use i32 for |
| // setcc operations results (slt, sgt, ...). |
| setBooleanContents(ZeroOrOneBooleanContent); |
| setBooleanVectorContents(ZeroOrNegativeOneBooleanContent); |
| // The cmp.cond.fmt instruction in MIPS32r6/MIPS64r6 uses 0 and -1 like MSA |
| // does. Integer booleans still use 0 and 1. |
| if (Subtarget.hasMips32r6()) |
| setBooleanContents(ZeroOrOneBooleanContent, |
| ZeroOrNegativeOneBooleanContent); |
| |
| // Load extented operations for i1 types must be promoted |
| for (MVT VT : MVT::integer_valuetypes()) { |
| setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); |
| setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); |
| setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); |
| } |
| |
| // MIPS doesn't have extending float->double load/store. Set LoadExtAction |
| // for f32, f16 |
| for (MVT VT : MVT::fp_valuetypes()) { |
| setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand); |
| setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand); |
| } |
| |
| // Set LoadExtAction for f16 vectors to Expand |
| for (MVT VT : MVT::fp_fixedlen_vector_valuetypes()) { |
| MVT F16VT = MVT::getVectorVT(MVT::f16, VT.getVectorNumElements()); |
| if (F16VT.isValid()) |
| setLoadExtAction(ISD::EXTLOAD, VT, F16VT, Expand); |
| } |
| |
| setTruncStoreAction(MVT::f32, MVT::f16, Expand); |
| setTruncStoreAction(MVT::f64, MVT::f16, Expand); |
| |
| setTruncStoreAction(MVT::f64, MVT::f32, Expand); |
| |
| // Used by legalize types to correctly generate the setcc result. |
| // Without this, every float setcc comes with a AND/OR with the result, |
| // we don't want this, since the fpcmp result goes to a flag register, |
| // which is used implicitly by brcond and select operations. |
| AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32); |
| |
| // Mips Custom Operations |
| setOperationAction(ISD::BR_JT, MVT::Other, Expand); |
| setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); |
| setOperationAction(ISD::BlockAddress, MVT::i32, Custom); |
| setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); |
| setOperationAction(ISD::JumpTable, MVT::i32, Custom); |
| setOperationAction(ISD::ConstantPool, MVT::i32, Custom); |
| setOperationAction(ISD::SELECT, MVT::f32, Custom); |
| setOperationAction(ISD::SELECT, MVT::f64, Custom); |
| setOperationAction(ISD::SELECT, MVT::i32, Custom); |
| setOperationAction(ISD::SETCC, MVT::f32, Custom); |
| setOperationAction(ISD::SETCC, MVT::f64, Custom); |
| setOperationAction(ISD::BRCOND, MVT::Other, Custom); |
| setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); |
| setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); |
| setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); |
| |
| if (!(TM.Options.NoNaNsFPMath || Subtarget.inAbs2008Mode())) { |
| setOperationAction(ISD::FABS, MVT::f32, Custom); |
| setOperationAction(ISD::FABS, MVT::f64, Custom); |
| } |
| |
| if (Subtarget.isGP64bit()) { |
| setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); |
| setOperationAction(ISD::BlockAddress, MVT::i64, Custom); |
| setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); |
| setOperationAction(ISD::JumpTable, MVT::i64, Custom); |
| setOperationAction(ISD::ConstantPool, MVT::i64, Custom); |
| setOperationAction(ISD::SELECT, MVT::i64, Custom); |
| setOperationAction(ISD::LOAD, MVT::i64, Custom); |
| setOperationAction(ISD::STORE, MVT::i64, Custom); |
| setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); |
| setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom); |
| setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom); |
| setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom); |
| } |
| |
| if (!Subtarget.isGP64bit()) { |
| setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); |
| setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom); |
| setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom); |
| } |
| |
| setOperationAction(ISD::EH_DWARF_CFA, MVT::i32, Custom); |
| if (Subtarget.isGP64bit()) |
| setOperationAction(ISD::EH_DWARF_CFA, MVT::i64, Custom); |
| |
| setOperationAction(ISD::SDIV, MVT::i32, Expand); |
| setOperationAction(ISD::SREM, MVT::i32, Expand); |
| setOperationAction(ISD::UDIV, MVT::i32, Expand); |
| setOperationAction(ISD::UREM, MVT::i32, Expand); |
| setOperationAction(ISD::SDIV, MVT::i64, Expand); |
| setOperationAction(ISD::SREM, MVT::i64, Expand); |
| setOperationAction(ISD::UDIV, MVT::i64, Expand); |
| setOperationAction(ISD::UREM, MVT::i64, Expand); |
| |
| // Operations not directly supported by Mips. |
| setOperationAction(ISD::BR_CC, MVT::f32, Expand); |
| setOperationAction(ISD::BR_CC, MVT::f64, Expand); |
| setOperationAction(ISD::BR_CC, MVT::i32, Expand); |
| setOperationAction(ISD::BR_CC, MVT::i64, Expand); |
| setOperationAction(ISD::SELECT_CC, MVT::i32, Expand); |
| setOperationAction(ISD::SELECT_CC, MVT::i64, Expand); |
| setOperationAction(ISD::SELECT_CC, MVT::f32, Expand); |
| setOperationAction(ISD::SELECT_CC, MVT::f64, Expand); |
| setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); |
| setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); |
| setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); |
| setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand); |
| setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); |
| if (Subtarget.hasCnMips()) { |
| setOperationAction(ISD::CTPOP, MVT::i32, Legal); |
| setOperationAction(ISD::CTPOP, MVT::i64, Legal); |
| } else { |
| setOperationAction(ISD::CTPOP, MVT::i32, Expand); |
| setOperationAction(ISD::CTPOP, MVT::i64, Expand); |
| } |
| setOperationAction(ISD::CTTZ, MVT::i32, Expand); |
| setOperationAction(ISD::CTTZ, MVT::i64, Expand); |
| setOperationAction(ISD::ROTL, MVT::i32, Expand); |
| setOperationAction(ISD::ROTL, MVT::i64, Expand); |
| setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand); |
| setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand); |
| |
| if (!Subtarget.hasMips32r2()) |
| setOperationAction(ISD::ROTR, MVT::i32, Expand); |
| |
| if (!Subtarget.hasMips64r2()) |
| setOperationAction(ISD::ROTR, MVT::i64, Expand); |
| |
| setOperationAction(ISD::FSIN, MVT::f32, Expand); |
| setOperationAction(ISD::FSIN, MVT::f64, Expand); |
| setOperationAction(ISD::FCOS, MVT::f32, Expand); |
| setOperationAction(ISD::FCOS, MVT::f64, Expand); |
| setOperationAction(ISD::FSINCOS, MVT::f32, Expand); |
| setOperationAction(ISD::FSINCOS, MVT::f64, Expand); |
| setOperationAction(ISD::FPOW, MVT::f32, Expand); |
| setOperationAction(ISD::FPOW, MVT::f64, Expand); |
| setOperationAction(ISD::FLOG, MVT::f32, Expand); |
| setOperationAction(ISD::FLOG2, MVT::f32, Expand); |
| setOperationAction(ISD::FLOG10, MVT::f32, Expand); |
| setOperationAction(ISD::FEXP, MVT::f32, Expand); |
| setOperationAction(ISD::FMA, MVT::f32, Expand); |
| setOperationAction(ISD::FMA, MVT::f64, Expand); |
| setOperationAction(ISD::FREM, MVT::f32, Expand); |
| setOperationAction(ISD::FREM, MVT::f64, Expand); |
| |
| // Lower f16 conversion operations into library calls |
| setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand); |
| setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand); |
| setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand); |
| setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand); |
| |
| setOperationAction(ISD::EH_RETURN, MVT::Other, Custom); |
| |
| setOperationAction(ISD::VASTART, MVT::Other, Custom); |
| setOperationAction(ISD::VAARG, MVT::Other, Custom); |
| setOperationAction(ISD::VACOPY, MVT::Other, Expand); |
| setOperationAction(ISD::VAEND, MVT::Other, Expand); |
| |
| // Use the default for now |
| setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); |
| setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); |
| |
| if (!Subtarget.isGP64bit()) { |
| setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand); |
| setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand); |
| } |
| |
| if (!Subtarget.hasMips32r2()) { |
| setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); |
| setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); |
| } |
| |
| // MIPS16 lacks MIPS32's clz and clo instructions. |
| if (!Subtarget.hasMips32() || Subtarget.inMips16Mode()) |
| setOperationAction(ISD::CTLZ, MVT::i32, Expand); |
| if (!Subtarget.hasMips64()) |
| setOperationAction(ISD::CTLZ, MVT::i64, Expand); |
| |
| if (!Subtarget.hasMips32r2()) |
| setOperationAction(ISD::BSWAP, MVT::i32, Expand); |
| if (!Subtarget.hasMips64r2()) |
| setOperationAction(ISD::BSWAP, MVT::i64, Expand); |
| |
| if (Subtarget.isGP64bit()) { |
| setLoadExtAction(ISD::SEXTLOAD, MVT::i64, MVT::i32, Custom); |
| setLoadExtAction(ISD::ZEXTLOAD, MVT::i64, MVT::i32, Custom); |
| setLoadExtAction(ISD::EXTLOAD, MVT::i64, MVT::i32, Custom); |
| setTruncStoreAction(MVT::i64, MVT::i32, Custom); |
| } |
| |
| setOperationAction(ISD::TRAP, MVT::Other, Legal); |
| |
| setTargetDAGCombine(ISD::SDIVREM); |
| setTargetDAGCombine(ISD::UDIVREM); |
| setTargetDAGCombine(ISD::SELECT); |
| setTargetDAGCombine(ISD::AND); |
| setTargetDAGCombine(ISD::OR); |
| setTargetDAGCombine(ISD::ADD); |
| setTargetDAGCombine(ISD::SUB); |
| setTargetDAGCombine(ISD::AssertZext); |
| setTargetDAGCombine(ISD::SHL); |
| |
| if (ABI.IsO32()) { |
| // These libcalls are not available in 32-bit. |
| setLibcallName(RTLIB::SHL_I128, nullptr); |
| setLibcallName(RTLIB::SRL_I128, nullptr); |
| setLibcallName(RTLIB::SRA_I128, nullptr); |
| } |
| |
| setMinFunctionAlignment(Subtarget.isGP64bit() ? Align(8) : Align(4)); |
| |
| // The arguments on the stack are defined in terms of 4-byte slots on O32 |
| // and 8-byte slots on N32/N64. |
| setMinStackArgumentAlignment((ABI.IsN32() || ABI.IsN64()) ? Align(8) |
| : Align(4)); |
| |
| setStackPointerRegisterToSaveRestore(ABI.IsN64() ? Mips::SP_64 : Mips::SP); |
| |
| MaxStoresPerMemcpy = 16; |
| |
| isMicroMips = Subtarget.inMicroMipsMode(); |
| } |
| |
| const MipsTargetLowering * |
| MipsTargetLowering::create(const MipsTargetMachine &TM, |
| const MipsSubtarget &STI) { |
| if (STI.inMips16Mode()) |
| return createMips16TargetLowering(TM, STI); |
| |
| return createMipsSETargetLowering(TM, STI); |
| } |
| |
| // Create a fast isel object. |
| FastISel * |
| MipsTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo, |
| const TargetLibraryInfo *libInfo) const { |
| const MipsTargetMachine &TM = |
| static_cast<const MipsTargetMachine &>(funcInfo.MF->getTarget()); |
| |
| // We support only the standard encoding [MIPS32,MIPS32R5] ISAs. |
| bool UseFastISel = TM.Options.EnableFastISel && Subtarget.hasMips32() && |
| !Subtarget.hasMips32r6() && !Subtarget.inMips16Mode() && |
| !Subtarget.inMicroMipsMode(); |
| |
| // Disable if either of the following is true: |
| // We do not generate PIC, the ABI is not O32, XGOT is being used. |
| if (!TM.isPositionIndependent() || !TM.getABI().IsO32() || |
| Subtarget.useXGOT()) |
| UseFastISel = false; |
| |
| return UseFastISel ? Mips::createFastISel(funcInfo, libInfo) : nullptr; |
| } |
| |
| EVT MipsTargetLowering::getSetCCResultType(const DataLayout &, LLVMContext &, |
| EVT VT) const { |
| if (!VT.isVector()) |
| return MVT::i32; |
| return VT.changeVectorElementTypeToInteger(); |
| } |
| |
| static SDValue performDivRemCombine(SDNode *N, SelectionDAG &DAG, |
| TargetLowering::DAGCombinerInfo &DCI, |
| const MipsSubtarget &Subtarget) { |
| if (DCI.isBeforeLegalizeOps()) |
| return SDValue(); |
| |
| EVT Ty = N->getValueType(0); |
| unsigned LO = (Ty == MVT::i32) ? Mips::LO0 : Mips::LO0_64; |
| unsigned HI = (Ty == MVT::i32) ? Mips::HI0 : Mips::HI0_64; |
| unsigned Opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem16 : |
| MipsISD::DivRemU16; |
| SDLoc DL(N); |
| |
| SDValue DivRem = DAG.getNode(Opc, DL, MVT::Glue, |
| N->getOperand(0), N->getOperand(1)); |
| SDValue InChain = DAG.getEntryNode(); |
| SDValue InGlue = DivRem; |
| |
| // insert MFLO |
| if (N->hasAnyUseOfValue(0)) { |
| SDValue CopyFromLo = DAG.getCopyFromReg(InChain, DL, LO, Ty, |
| InGlue); |
| DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo); |
| InChain = CopyFromLo.getValue(1); |
| InGlue = CopyFromLo.getValue(2); |
| } |
| |
| // insert MFHI |
| if (N->hasAnyUseOfValue(1)) { |
| SDValue CopyFromHi = DAG.getCopyFromReg(InChain, DL, |
| HI, Ty, InGlue); |
| DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi); |
| } |
| |
| return SDValue(); |
| } |
| |
| static Mips::CondCode condCodeToFCC(ISD::CondCode CC) { |
| switch (CC) { |
| default: llvm_unreachable("Unknown fp condition code!"); |
| case ISD::SETEQ: |
| case ISD::SETOEQ: return Mips::FCOND_OEQ; |
| case ISD::SETUNE: return Mips::FCOND_UNE; |
| case ISD::SETLT: |
| case ISD::SETOLT: return Mips::FCOND_OLT; |
| case ISD::SETGT: |
| case ISD::SETOGT: return Mips::FCOND_OGT; |
| case ISD::SETLE: |
| case ISD::SETOLE: return Mips::FCOND_OLE; |
| case ISD::SETGE: |
| case ISD::SETOGE: return Mips::FCOND_OGE; |
| case ISD::SETULT: return Mips::FCOND_ULT; |
| case ISD::SETULE: return Mips::FCOND_ULE; |
| case ISD::SETUGT: return Mips::FCOND_UGT; |
| case ISD::SETUGE: return Mips::FCOND_UGE; |
| case ISD::SETUO: return Mips::FCOND_UN; |
| case ISD::SETO: return Mips::FCOND_OR; |
| case ISD::SETNE: |
| case ISD::SETONE: return Mips::FCOND_ONE; |
| case ISD::SETUEQ: return Mips::FCOND_UEQ; |
| } |
| } |
| |
| /// This function returns true if the floating point conditional branches and |
| /// conditional moves which use condition code CC should be inverted. |
| static bool invertFPCondCodeUser(Mips::CondCode CC) { |
| if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT) |
| return false; |
| |
| assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) && |
| "Illegal Condition Code"); |
| |
| return true; |
| } |
| |
| // Creates and returns an FPCmp node from a setcc node. |
| // Returns Op if setcc is not a floating point comparison. |
| static SDValue createFPCmp(SelectionDAG &DAG, const SDValue &Op) { |
| // must be a SETCC node |
| if (Op.getOpcode() != ISD::SETCC) |
| return Op; |
| |
| SDValue LHS = Op.getOperand(0); |
| |
| if (!LHS.getValueType().isFloatingPoint()) |
| return Op; |
| |
| SDValue RHS = Op.getOperand(1); |
| SDLoc DL(Op); |
| |
| // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of |
| // node if necessary. |
| ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); |
| |
| return DAG.getNode(MipsISD::FPCmp, DL, MVT::Glue, LHS, RHS, |
| DAG.getConstant(condCodeToFCC(CC), DL, MVT::i32)); |
| } |
| |
| // Creates and returns a CMovFPT/F node. |
| static SDValue createCMovFP(SelectionDAG &DAG, SDValue Cond, SDValue True, |
| SDValue False, const SDLoc &DL) { |
| ConstantSDNode *CC = cast<ConstantSDNode>(Cond.getOperand(2)); |
| bool invert = invertFPCondCodeUser((Mips::CondCode)CC->getSExtValue()); |
| SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32); |
| |
| return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL, |
| True.getValueType(), True, FCC0, False, Cond); |
| } |
| |
| static SDValue performSELECTCombine(SDNode *N, SelectionDAG &DAG, |
| TargetLowering::DAGCombinerInfo &DCI, |
| const MipsSubtarget &Subtarget) { |
| if (DCI.isBeforeLegalizeOps()) |
| return SDValue(); |
| |
| SDValue SetCC = N->getOperand(0); |
| |
| if ((SetCC.getOpcode() != ISD::SETCC) || |
| !SetCC.getOperand(0).getValueType().isInteger()) |
| return SDValue(); |
| |
| SDValue False = N->getOperand(2); |
| EVT FalseTy = False.getValueType(); |
| |
| if (!FalseTy.isInteger()) |
| return SDValue(); |
| |
| ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(False); |
| |
| // If the RHS (False) is 0, we swap the order of the operands |
| // of ISD::SELECT (obviously also inverting the condition) so that we can |
| // take advantage of conditional moves using the $0 register. |
| // Example: |
| // return (a != 0) ? x : 0; |
| // load $reg, x |
| // movz $reg, $0, a |
| if (!FalseC) |
| return SDValue(); |
| |
| const SDLoc DL(N); |
| |
| if (!FalseC->getZExtValue()) { |
| ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get(); |
| SDValue True = N->getOperand(1); |
| |
| SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0), |
| SetCC.getOperand(1), |
| ISD::getSetCCInverse(CC, SetCC.getValueType())); |
| |
| return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True); |
| } |
| |
| // If both operands are integer constants there's a possibility that we |
| // can do some interesting optimizations. |
| SDValue True = N->getOperand(1); |
| ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(True); |
| |
| if (!TrueC || !True.getValueType().isInteger()) |
| return SDValue(); |
| |
| // We'll also ignore MVT::i64 operands as this optimizations proves |
| // to be ineffective because of the required sign extensions as the result |
| // of a SETCC operator is always MVT::i32 for non-vector types. |
| if (True.getValueType() == MVT::i64) |
| return SDValue(); |
| |
| int64_t Diff = TrueC->getSExtValue() - FalseC->getSExtValue(); |
| |
| // 1) (a < x) ? y : y-1 |
| // slti $reg1, a, x |
| // addiu $reg2, $reg1, y-1 |
| if (Diff == 1) |
| return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, False); |
| |
| // 2) (a < x) ? y-1 : y |
| // slti $reg1, a, x |
| // xor $reg1, $reg1, 1 |
| // addiu $reg2, $reg1, y-1 |
| if (Diff == -1) { |
| ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get(); |
| SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0), |
| SetCC.getOperand(1), |
| ISD::getSetCCInverse(CC, SetCC.getValueType())); |
| return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, True); |
| } |
| |
| // Could not optimize. |
| return SDValue(); |
| } |
| |
| static SDValue performCMovFPCombine(SDNode *N, SelectionDAG &DAG, |
| TargetLowering::DAGCombinerInfo &DCI, |
| const MipsSubtarget &Subtarget) { |
| if (DCI.isBeforeLegalizeOps()) |
| return SDValue(); |
| |
| SDValue ValueIfTrue = N->getOperand(0), ValueIfFalse = N->getOperand(2); |
| |
| ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(ValueIfFalse); |
| if (!FalseC || FalseC->getZExtValue()) |
| return SDValue(); |
| |
| // Since RHS (False) is 0, we swap the order of the True/False operands |
| // (obviously also inverting the condition) so that we can |
| // take advantage of conditional moves using the $0 register. |
| // Example: |
| // return (a != 0) ? x : 0; |
| // load $reg, x |
| // movz $reg, $0, a |
| unsigned Opc = (N->getOpcode() == MipsISD::CMovFP_T) ? MipsISD::CMovFP_F : |
| MipsISD::CMovFP_T; |
| |
| SDValue FCC = N->getOperand(1), Glue = N->getOperand(3); |
| return DAG.getNode(Opc, SDLoc(N), ValueIfFalse.getValueType(), |
| ValueIfFalse, FCC, ValueIfTrue, Glue); |
| } |
| |
| static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG, |
| TargetLowering::DAGCombinerInfo &DCI, |
| const MipsSubtarget &Subtarget) { |
| if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert()) |
| return SDValue(); |
| |
| SDValue FirstOperand = N->getOperand(0); |
| unsigned FirstOperandOpc = FirstOperand.getOpcode(); |
| SDValue Mask = N->getOperand(1); |
| EVT ValTy = N->getValueType(0); |
| SDLoc DL(N); |
| |
| uint64_t Pos = 0, SMPos, SMSize; |
| ConstantSDNode *CN; |
| SDValue NewOperand; |
| unsigned Opc; |
| |
| // Op's second operand must be a shifted mask. |
| if (!(CN = dyn_cast<ConstantSDNode>(Mask)) || |
| !isShiftedMask(CN->getZExtValue(), SMPos, SMSize)) |
| return SDValue(); |
| |
| if (FirstOperandOpc == ISD::SRA || FirstOperandOpc == ISD::SRL) { |
| // Pattern match EXT. |
| // $dst = and ((sra or srl) $src , pos), (2**size - 1) |
| // => ext $dst, $src, pos, size |
| |
| // The second operand of the shift must be an immediate. |
| if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.getOperand(1)))) |
| return SDValue(); |
| |
| Pos = CN->getZExtValue(); |
| |
| // Return if the shifted mask does not start at bit 0 or the sum of its size |
| // and Pos exceeds the word's size. |
| if (SMPos != 0 || Pos + SMSize > ValTy.getSizeInBits()) |
| return SDValue(); |
| |
| Opc = MipsISD::Ext; |
| NewOperand = FirstOperand.getOperand(0); |
| } else if (FirstOperandOpc == ISD::SHL && Subtarget.hasCnMips()) { |
| // Pattern match CINS. |
| // $dst = and (shl $src , pos), mask |
| // => cins $dst, $src, pos, size |
| // mask is a shifted mask with consecutive 1's, pos = shift amount, |
| // size = population count. |
| |
| // The second operand of the shift must be an immediate. |
| if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.getOperand(1)))) |
| return SDValue(); |
| |
| Pos = CN->getZExtValue(); |
| |
| if (SMPos != Pos || Pos >= ValTy.getSizeInBits() || SMSize >= 32 || |
| Pos + SMSize > ValTy.getSizeInBits()) |
| return SDValue(); |
| |
| NewOperand = FirstOperand.getOperand(0); |
| // SMSize is 'location' (position) in this case, not size. |
| SMSize--; |
| Opc = MipsISD::CIns; |
| } else { |
| // Pattern match EXT. |
| // $dst = and $src, (2**size - 1) , if size > 16 |
| // => ext $dst, $src, pos, size , pos = 0 |
| |
| // If the mask is <= 0xffff, andi can be used instead. |
| if (CN->getZExtValue() <= 0xffff) |
| return SDValue(); |
| |
| // Return if the mask doesn't start at position 0. |
| if (SMPos) |
| return SDValue(); |
| |
| Opc = MipsISD::Ext; |
| NewOperand = FirstOperand; |
| } |
| return DAG.getNode(Opc, DL, ValTy, NewOperand, |
| DAG.getConstant(Pos, DL, MVT::i32), |
| DAG.getConstant(SMSize, DL, MVT::i32)); |
| } |
| |
| static SDValue performORCombine(SDNode *N, SelectionDAG &DAG, |
| TargetLowering::DAGCombinerInfo &DCI, |
| const MipsSubtarget &Subtarget) { |
| // Pattern match INS. |
| // $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1), |
| // where mask1 = (2**size - 1) << pos, mask0 = ~mask1 |
| // => ins $dst, $src, size, pos, $src1 |
| if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert()) |
| return SDValue(); |
| |
| SDValue And0 = N->getOperand(0), And1 = N->getOperand(1); |
| uint64_t SMPos0, SMSize0, SMPos1, SMSize1; |
| ConstantSDNode *CN, *CN1; |
| |
| // See if Op's first operand matches (and $src1 , mask0). |
| if (And0.getOpcode() != ISD::AND) |
| return SDValue(); |
| |
| if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) || |
| !isShiftedMask(~CN->getSExtValue(), SMPos0, SMSize0)) |
| return SDValue(); |
| |
| // See if Op's second operand matches (and (shl $src, pos), mask1). |
| if (And1.getOpcode() == ISD::AND && |
| And1.getOperand(0).getOpcode() == ISD::SHL) { |
| |
| if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) || |
| !isShiftedMask(CN->getZExtValue(), SMPos1, SMSize1)) |
| return SDValue(); |
| |
| // The shift masks must have the same position and size. |
| if (SMPos0 != SMPos1 || SMSize0 != SMSize1) |
| return SDValue(); |
| |
| SDValue Shl = And1.getOperand(0); |
| |
| if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1)))) |
| return SDValue(); |
| |
| unsigned Shamt = CN->getZExtValue(); |
| |
| // Return if the shift amount and the first bit position of mask are not the |
| // same. |
| EVT ValTy = N->getValueType(0); |
| if ((Shamt != SMPos0) || (SMPos0 + SMSize0 > ValTy.getSizeInBits())) |
| return SDValue(); |
| |
| SDLoc DL(N); |
| return DAG.getNode(MipsISD::Ins, DL, ValTy, Shl.getOperand(0), |
| DAG.getConstant(SMPos0, DL, MVT::i32), |
| DAG.getConstant(SMSize0, DL, MVT::i32), |
| And0.getOperand(0)); |
| } else { |
| // Pattern match DINS. |
| // $dst = or (and $src, mask0), mask1 |
| // where mask0 = ((1 << SMSize0) -1) << SMPos0 |
| // => dins $dst, $src, pos, size |
| if (~CN->getSExtValue() == ((((int64_t)1 << SMSize0) - 1) << SMPos0) && |
| ((SMSize0 + SMPos0 <= 64 && Subtarget.hasMips64r2()) || |
| (SMSize0 + SMPos0 <= 32))) { |
| // Check if AND instruction has constant as argument |
| bool isConstCase = And1.getOpcode() != ISD::AND; |
| if (And1.getOpcode() == ISD::AND) { |
| if (!(CN1 = dyn_cast<ConstantSDNode>(And1->getOperand(1)))) |
| return SDValue(); |
| } else { |
| if (!(CN1 = dyn_cast<ConstantSDNode>(N->getOperand(1)))) |
| return SDValue(); |
| } |
| // Don't generate INS if constant OR operand doesn't fit into bits |
| // cleared by constant AND operand. |
| if (CN->getSExtValue() & CN1->getSExtValue()) |
| return SDValue(); |
| |
| SDLoc DL(N); |
| EVT ValTy = N->getOperand(0)->getValueType(0); |
| SDValue Const1; |
| SDValue SrlX; |
| if (!isConstCase) { |
| Const1 = DAG.getConstant(SMPos0, DL, MVT::i32); |
| SrlX = DAG.getNode(ISD::SRL, DL, And1->getValueType(0), And1, Const1); |
| } |
| return DAG.getNode( |
| MipsISD::Ins, DL, N->getValueType(0), |
| isConstCase |
| ? DAG.getConstant(CN1->getSExtValue() >> SMPos0, DL, ValTy) |
| : SrlX, |
| DAG.getConstant(SMPos0, DL, MVT::i32), |
| DAG.getConstant(ValTy.getSizeInBits() / 8 < 8 ? SMSize0 & 31 |
| : SMSize0, |
| DL, MVT::i32), |
| And0->getOperand(0)); |
| |
| } |
| return SDValue(); |
| } |
| } |
| |
| static SDValue performMADD_MSUBCombine(SDNode *ROOTNode, SelectionDAG &CurDAG, |
| const MipsSubtarget &Subtarget) { |
| // ROOTNode must have a multiplication as an operand for the match to be |
| // successful. |
| if (ROOTNode->getOperand(0).getOpcode() != ISD::MUL && |
| ROOTNode->getOperand(1).getOpcode() != ISD::MUL) |
| return SDValue(); |
| |
| // We don't handle vector types here. |
| if (ROOTNode->getValueType(0).isVector()) |
| return SDValue(); |
| |
| // For MIPS64, madd / msub instructions are inefficent to use with 64 bit |
| // arithmetic. E.g. |
| // (add (mul a b) c) => |
| // let res = (madd (mthi (drotr c 32))x(mtlo c) a b) in |
| // MIPS64: (or (dsll (mfhi res) 32) (dsrl (dsll (mflo res) 32) 32) |
| // or |
| // MIPS64R2: (dins (mflo res) (mfhi res) 32 32) |
| // |
| // The overhead of setting up the Hi/Lo registers and reassembling the |
| // result makes this a dubious optimzation for MIPS64. The core of the |
| // problem is that Hi/Lo contain the upper and lower 32 bits of the |
| // operand and result. |
| // |
| // It requires a chain of 4 add/mul for MIPS64R2 to get better code |
| // density than doing it naively, 5 for MIPS64. Additionally, using |
| // madd/msub on MIPS64 requires the operands actually be 32 bit sign |
| // extended operands, not true 64 bit values. |
| // |
| // FIXME: For the moment, disable this completely for MIPS64. |
| if (Subtarget.hasMips64()) |
| return SDValue(); |
| |
| SDValue Mult = ROOTNode->getOperand(0).getOpcode() == ISD::MUL |
| ? ROOTNode->getOperand(0) |
| : ROOTNode->getOperand(1); |
| |
| SDValue AddOperand = ROOTNode->getOperand(0).getOpcode() == ISD::MUL |
| ? ROOTNode->getOperand(1) |
| : ROOTNode->getOperand(0); |
| |
| // Transform this to a MADD only if the user of this node is the add. |
| // If there are other users of the mul, this function returns here. |
| if (!Mult.hasOneUse()) |
| return SDValue(); |
| |
| // maddu and madd are unusual instructions in that on MIPS64 bits 63..31 |
| // must be in canonical form, i.e. sign extended. For MIPS32, the operands |
| // of the multiply must have 32 or more sign bits, otherwise we cannot |
| // perform this optimization. We have to check this here as we're performing |
| // this optimization pre-legalization. |
| SDValue MultLHS = Mult->getOperand(0); |
| SDValue MultRHS = Mult->getOperand(1); |
| |
| bool IsSigned = MultLHS->getOpcode() == ISD::SIGN_EXTEND && |
| MultRHS->getOpcode() == ISD::SIGN_EXTEND; |
| bool IsUnsigned = MultLHS->getOpcode() == ISD::ZERO_EXTEND && |
| MultRHS->getOpcode() == ISD::ZERO_EXTEND; |
| |
| if (!IsSigned && !IsUnsigned) |
| return SDValue(); |
| |
| // Initialize accumulator. |
| SDLoc DL(ROOTNode); |
| SDValue TopHalf; |
| SDValue BottomHalf; |
| BottomHalf = CurDAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, AddOperand, |
| CurDAG.getIntPtrConstant(0, DL)); |
| |
| TopHalf = CurDAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, AddOperand, |
| CurDAG.getIntPtrConstant(1, DL)); |
| SDValue ACCIn = CurDAG.getNode(MipsISD::MTLOHI, DL, MVT::Untyped, |
| BottomHalf, |
| TopHalf); |
| |
| // Create MipsMAdd(u) / MipsMSub(u) node. |
| bool IsAdd = ROOTNode->getOpcode() == ISD::ADD; |
| unsigned Opcode = IsAdd ? (IsUnsigned ? MipsISD::MAddu : MipsISD::MAdd) |
| : (IsUnsigned ? MipsISD::MSubu : MipsISD::MSub); |
| SDValue MAddOps[3] = { |
| CurDAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Mult->getOperand(0)), |
| CurDAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Mult->getOperand(1)), ACCIn}; |
| EVT VTs[2] = {MVT::i32, MVT::i32}; |
| SDValue MAdd = CurDAG.getNode(Opcode, DL, VTs, MAddOps); |
| |
| SDValue ResLo = CurDAG.getNode(MipsISD::MFLO, DL, MVT::i32, MAdd); |
| SDValue ResHi = CurDAG.getNode(MipsISD::MFHI, DL, MVT::i32, MAdd); |
| SDValue Combined = |
| CurDAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, ResLo, ResHi); |
| return Combined; |
| } |
| |
| static SDValue performSUBCombine(SDNode *N, SelectionDAG &DAG, |
| TargetLowering::DAGCombinerInfo &DCI, |
| const MipsSubtarget &Subtarget) { |
| // (sub v0 (mul v1, v2)) => (msub v1, v2, v0) |
| if (DCI.isBeforeLegalizeOps()) { |
| if (Subtarget.hasMips32() && !Subtarget.hasMips32r6() && |
| !Subtarget.inMips16Mode() && N->getValueType(0) == MVT::i64) |
| return performMADD_MSUBCombine(N, DAG, Subtarget); |
| |
| return SDValue(); |
| } |
| |
| return SDValue(); |
| } |
| |
| static SDValue performADDCombine(SDNode *N, SelectionDAG &DAG, |
| TargetLowering::DAGCombinerInfo &DCI, |
| const MipsSubtarget &Subtarget) { |
| // (add v0 (mul v1, v2)) => (madd v1, v2, v0) |
| if (DCI.isBeforeLegalizeOps()) { |
| if (Subtarget.hasMips32() && !Subtarget.hasMips32r6() && |
| !Subtarget.inMips16Mode() && N->getValueType(0) == MVT::i64) |
| return performMADD_MSUBCombine(N, DAG, Subtarget); |
| |
| return SDValue(); |
| } |
| |
| // (add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt)) |
| SDValue Add = N->getOperand(1); |
| |
| if (Add.getOpcode() != ISD::ADD) |
| return SDValue(); |
| |
| SDValue Lo = Add.getOperand(1); |
| |
| if ((Lo.getOpcode() != MipsISD::Lo) || |
| (Lo.getOperand(0).getOpcode() != ISD::TargetJumpTable)) |
| return SDValue(); |
| |
| EVT ValTy = N->getValueType(0); |
| SDLoc DL(N); |
| |
| SDValue Add1 = DAG.getNode(ISD::ADD, DL, ValTy, N->getOperand(0), |
| Add.getOperand(0)); |
| return DAG.getNode(ISD::ADD, DL, ValTy, Add1, Lo); |
| } |
| |
| static SDValue performSHLCombine(SDNode *N, SelectionDAG &DAG, |
| TargetLowering::DAGCombinerInfo &DCI, |
| const MipsSubtarget &Subtarget) { |
| // Pattern match CINS. |
| // $dst = shl (and $src , imm), pos |
| // => cins $dst, $src, pos, size |
| |
| if (DCI.isBeforeLegalizeOps() || !Subtarget.hasCnMips()) |
| return SDValue(); |
| |
| SDValue FirstOperand = N->getOperand(0); |
| unsigned FirstOperandOpc = FirstOperand.getOpcode(); |
| SDValue SecondOperand = N->getOperand(1); |
| EVT ValTy = N->getValueType(0); |
| SDLoc DL(N); |
| |
| uint64_t Pos = 0, SMPos, SMSize; |
| ConstantSDNode *CN; |
| SDValue NewOperand; |
| |
| // The second operand of the shift must be an immediate. |
| if (!(CN = dyn_cast<ConstantSDNode>(SecondOperand))) |
| return SDValue(); |
| |
| Pos = CN->getZExtValue(); |
| |
| if (Pos >= ValTy.getSizeInBits()) |
| return SDValue(); |
| |
| if (FirstOperandOpc != ISD::AND) |
| return SDValue(); |
| |
| // AND's second operand must be a shifted mask. |
| if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.getOperand(1))) || |
| !isShiftedMask(CN->getZExtValue(), SMPos, SMSize)) |
| return SDValue(); |
| |
| // Return if the shifted mask does not start at bit 0 or the sum of its size |
| // and Pos exceeds the word's size. |
| if (SMPos != 0 || SMSize > 32 || Pos + SMSize > ValTy.getSizeInBits()) |
| return SDValue(); |
| |
| NewOperand = FirstOperand.getOperand(0); |
| // SMSize is 'location' (position) in this case, not size. |
| SMSize--; |
| |
| return DAG.getNode(MipsISD::CIns, DL, ValTy, NewOperand, |
| DAG.getConstant(Pos, DL, MVT::i32), |
| DAG.getConstant(SMSize, DL, MVT::i32)); |
| } |
| |
| SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) |
| const { |
| SelectionDAG &DAG = DCI.DAG; |
| unsigned Opc = N->getOpcode(); |
| |
| switch (Opc) { |
| default: break; |
| case ISD::SDIVREM: |
| case ISD::UDIVREM: |
| return performDivRemCombine(N, DAG, DCI, Subtarget); |
| case ISD::SELECT: |
| return performSELECTCombine(N, DAG, DCI, Subtarget); |
| case MipsISD::CMovFP_F: |
| case MipsISD::CMovFP_T: |
| return performCMovFPCombine(N, DAG, DCI, Subtarget); |
| case ISD::AND: |
| return performANDCombine(N, DAG, DCI, Subtarget); |
| case ISD::OR: |
| return performORCombine(N, DAG, DCI, Subtarget); |
| case ISD::ADD: |
| return performADDCombine(N, DAG, DCI, Subtarget); |
| case ISD::SHL: |
| return performSHLCombine(N, DAG, DCI, Subtarget); |
| case ISD::SUB: |
| return performSUBCombine(N, DAG, DCI, Subtarget); |
| } |
| |
| return SDValue(); |
| } |
| |
| bool MipsTargetLowering::isCheapToSpeculateCttz() const { |
| return Subtarget.hasMips32(); |
| } |
| |
| bool MipsTargetLowering::isCheapToSpeculateCtlz() const { |
| return Subtarget.hasMips32(); |
| } |
| |
| bool MipsTargetLowering::shouldFoldConstantShiftPairToMask( |
| const SDNode *N, CombineLevel Level) const { |
| if (N->getOperand(0).getValueType().isVector()) |
| return false; |
| return true; |
| } |
| |
| void |
| MipsTargetLowering::LowerOperationWrapper(SDNode *N, |
| SmallVectorImpl<SDValue> &Results, |
| SelectionDAG &DAG) const { |
| SDValue Res = LowerOperation(SDValue(N, 0), DAG); |
| |
| if (Res) |
| for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I) |
| Results.push_back(Res.getValue(I)); |
| } |
| |
| void |
| MipsTargetLowering::ReplaceNodeResults(SDNode *N, |
| SmallVectorImpl<SDValue> &Results, |
| SelectionDAG &DAG) const { |
| return LowerOperationWrapper(N, Results, DAG); |
| } |
| |
| SDValue MipsTargetLowering:: |
| LowerOperation(SDValue Op, SelectionDAG &DAG) const |
| { |
| switch (Op.getOpcode()) |
| { |
| case ISD::BRCOND: return lowerBRCOND(Op, DAG); |
| case ISD::ConstantPool: return lowerConstantPool(Op, DAG); |
| case ISD::GlobalAddress: return lowerGlobalAddress(Op, DAG); |
| case ISD::BlockAddress: return lowerBlockAddress(Op, DAG); |
| case ISD::GlobalTLSAddress: return lowerGlobalTLSAddress(Op, DAG); |
| case ISD::JumpTable: return lowerJumpTable(Op, DAG); |
| case ISD::SELECT: return lowerSELECT(Op, DAG); |
| case ISD::SETCC: return lowerSETCC(Op, DAG); |
| case ISD::VASTART: return lowerVASTART(Op, DAG); |
| case ISD::VAARG: return lowerVAARG(Op, DAG); |
| case ISD::FCOPYSIGN: return lowerFCOPYSIGN(Op, DAG); |
| case ISD::FABS: return lowerFABS(Op, DAG); |
| case ISD::FRAMEADDR: return lowerFRAMEADDR(Op, DAG); |
| case ISD::RETURNADDR: return lowerRETURNADDR(Op, DAG); |
| case ISD::EH_RETURN: return lowerEH_RETURN(Op, DAG); |
| case ISD::ATOMIC_FENCE: return lowerATOMIC_FENCE(Op, DAG); |
| case ISD::SHL_PARTS: return lowerShiftLeftParts(Op, DAG); |
| case ISD::SRA_PARTS: return lowerShiftRightParts(Op, DAG, true); |
| case ISD::SRL_PARTS: return lowerShiftRightParts(Op, DAG, false); |
| case ISD::LOAD: return lowerLOAD(Op, DAG); |
| case ISD::STORE: return lowerSTORE(Op, DAG); |
| case ISD::EH_DWARF_CFA: return lowerEH_DWARF_CFA(Op, DAG); |
| case ISD::FP_TO_SINT: return lowerFP_TO_SINT(Op, DAG); |
| } |
| return SDValue(); |
| } |
| |
| //===----------------------------------------------------------------------===// |
| // Lower helper functions |
| //===----------------------------------------------------------------------===// |
| |
| // addLiveIn - This helper function adds the specified physical register to the |
| // MachineFunction as a live in value. It also creates a corresponding |
| // virtual register for it. |
| static unsigned |
| addLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC) |
| { |
| Register VReg = MF.getRegInfo().createVirtualRegister(RC); |
| MF.getRegInfo().addLiveIn(PReg, VReg); |
| return VReg; |
| } |
| |
| static MachineBasicBlock *insertDivByZeroTrap(MachineInstr &MI, |
| MachineBasicBlock &MBB, |
| const TargetInstrInfo &TII, |
| bool Is64Bit, bool IsMicroMips) { |
| if (NoZeroDivCheck) |
| return &MBB; |
| |
| // Insert instruction "teq $divisor_reg, $zero, 7". |
| MachineBasicBlock::iterator I(MI); |
| MachineInstrBuilder MIB; |
| MachineOperand &Divisor = MI.getOperand(2); |
| MIB = BuildMI(MBB, std::next(I), MI.getDebugLoc(), |
| TII.get(IsMicroMips ? Mips::TEQ_MM : Mips::TEQ)) |
| .addReg(Divisor.getReg(), getKillRegState(Divisor.isKill())) |
| .addReg(Mips::ZERO) |
| .addImm(7); |
| |
| // Use the 32-bit sub-register if this is a 64-bit division. |
| if (Is64Bit) |
| MIB->getOperand(0).setSubReg(Mips::sub_32); |
| |
| // Clear Divisor's kill flag. |
| Divisor.setIsKill(false); |
| |
| // We would normally delete the original instruction here but in this case |
| // we only needed to inject an additional instruction rather than replace it. |
| |
| return &MBB; |
| } |
| |
| MachineBasicBlock * |
| MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, |
| MachineBasicBlock *BB) const { |
| switch (MI.getOpcode()) { |
| default: |
| llvm_unreachable("Unexpected instr type to insert"); |
| case Mips::ATOMIC_LOAD_ADD_I8: |
| return emitAtomicBinaryPartword(MI, BB, 1); |
| case Mips::ATOMIC_LOAD_ADD_I16: |
| return emitAtomicBinaryPartword(MI, BB, 2); |
| case Mips::ATOMIC_LOAD_ADD_I32: |
| return emitAtomicBinary(MI, BB); |
| case Mips::ATOMIC_LOAD_ADD_I64: |
| return emitAtomicBinary(MI, BB); |
| |
| case Mips::ATOMIC_LOAD_AND_I8: |
| return emitAtomicBinaryPartword(MI, BB, 1); |
| case Mips::ATOMIC_LOAD_AND_I16: |
| return emitAtomicBinaryPartword(MI, BB, 2); |
| case Mips::ATOMIC_LOAD_AND_I32: |
| return emitAtomicBinary(MI, BB); |
| case Mips::ATOMIC_LOAD_AND_I64: |
| return emitAtomicBinary(MI, BB); |
| |
| case Mips::ATOMIC_LOAD_OR_I8: |
| return emitAtomicBinaryPartword(MI, BB, 1); |
| case Mips::ATOMIC_LOAD_OR_I16: |
| return emitAtomicBinaryPartword(MI, BB, 2); |
| case Mips::ATOMIC_LOAD_OR_I32: |
| return emitAtomicBinary(MI, BB); |
| case Mips::ATOMIC_LOAD_OR_I64: |
| return emitAtomicBinary(MI, BB); |
| |
| case Mips::ATOMIC_LOAD_XOR_I8: |
| return emitAtomicBinaryPartword(MI, BB, 1); |
| case Mips::ATOMIC_LOAD_XOR_I16: |
| return emitAtomicBinaryPartword(MI, BB, 2); |
| case Mips::ATOMIC_LOAD_XOR_I32: |
| return emitAtomicBinary(MI, BB); |
| case Mips::ATOMIC_LOAD_XOR_I64: |
| return emitAtomicBinary(MI, BB); |
| |
| case Mips::ATOMIC_LOAD_NAND_I8: |
| return emitAtomicBinaryPartword(MI, BB, 1); |
| case Mips::ATOMIC_LOAD_NAND_I16: |
| return emitAtomicBinaryPartword(MI, BB, 2); |
| case Mips::ATOMIC_LOAD_NAND_I32: |
| return emitAtomicBinary(MI, BB); |
| case Mips::ATOMIC_LOAD_NAND_I64: |
| return emitAtomicBinary(MI, BB); |
| |
| case Mips::ATOMIC_LOAD_SUB_I8: |
| return emitAtomicBinaryPartword(MI, BB, 1); |
| case Mips::ATOMIC_LOAD_SUB_I16: |
| return emitAtomicBinaryPartword(MI, BB, 2); |
| case Mips::ATOMIC_LOAD_SUB_I32: |
| return emitAtomicBinary(MI, BB); |
| case Mips::ATOMIC_LOAD_SUB_I64: |
| return emitAtomicBinary(MI, BB); |
| |
| case Mips::ATOMIC_SWAP_I8: |
| return emitAtomicBinaryPartword(MI, BB, 1); |
| case Mips::ATOMIC_SWAP_I16: |
| return emitAtomicBinaryPartword(MI, BB, 2); |
| case Mips::ATOMIC_SWAP_I32: |
| return emitAtomicBinary(MI, BB); |
| case Mips::ATOMIC_SWAP_I64: |
| return emitAtomicBinary(MI, BB); |
| |
| case Mips::ATOMIC_CMP_SWAP_I8: |
| return emitAtomicCmpSwapPartword(MI, BB, 1); |
| case Mips::ATOMIC_CMP_SWAP_I16: |
| return emitAtomicCmpSwapPartword(MI, BB, 2); |
| case Mips::ATOMIC_CMP_SWAP_I32: |
| return emitAtomicCmpSwap(MI, BB); |
| case Mips::ATOMIC_CMP_SWAP_I64: |
| return emitAtomicCmpSwap(MI, BB); |
| |
| case Mips::ATOMIC_LOAD_MIN_I8: |
| return emitAtomicBinaryPartword(MI, BB, 1); |
| case Mips::ATOMIC_LOAD_MIN_I16: |
| return emitAtomicBinaryPartword(MI, BB, 2); |
| case Mips::ATOMIC_LOAD_MIN_I32: |
| return emitAtomicBinary(MI, BB); |
| case Mips::ATOMIC_LOAD_MIN_I64: |
| return emitAtomicBinary(MI, BB); |
| |
| case Mips::ATOMIC_LOAD_MAX_I8: |
| return emitAtomicBinaryPartword(MI, BB, 1); |
| case Mips::ATOMIC_LOAD_MAX_I16: |
| return emitAtomicBinaryPartword(MI, BB, 2); |
| case Mips::ATOMIC_LOAD_MAX_I32: |
| return emitAtomicBinary(MI, BB); |
| case Mips::ATOMIC_LOAD_MAX_I64: |
| return emitAtomicBinary(MI, BB); |
| |
| case Mips::ATOMIC_LOAD_UMIN_I8: |
| return emitAtomicBinaryPartword(MI, BB, 1); |
| case Mips::ATOMIC_LOAD_UMIN_I16: |
| return emitAtomicBinaryPartword(MI, BB, 2); |
| case Mips::ATOMIC_LOAD_UMIN_I32: |
| return emitAtomicBinary(MI, BB); |
| case Mips::ATOMIC_LOAD_UMIN_I64: |
| return emitAtomicBinary(MI, BB); |
| |
| case Mips::ATOMIC_LOAD_UMAX_I8: |
| return emitAtomicBinaryPartword(MI, BB, 1); |
| case Mips::ATOMIC_LOAD_UMAX_I16: |
| return emitAtomicBinaryPartword(MI, BB, 2); |
| case Mips::ATOMIC_LOAD_UMAX_I32: |
| return emitAtomicBinary(MI, BB); |
| case Mips::ATOMIC_LOAD_UMAX_I64: |
| return emitAtomicBinary(MI, BB); |
| |
| case Mips::PseudoSDIV: |
| case Mips::PseudoUDIV: |
| case Mips::DIV: |
| case Mips::DIVU: |
| case Mips::MOD: |
| case Mips::MODU: |
| return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), false, |
| false); |
| case Mips::SDIV_MM_Pseudo: |
| case Mips::UDIV_MM_Pseudo: |
| case Mips::SDIV_MM: |
| case Mips::UDIV_MM: |
| case Mips::DIV_MMR6: |
| case Mips::DIVU_MMR6: |
| case Mips::MOD_MMR6: |
| case Mips::MODU_MMR6: |
| return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), false, true); |
| case Mips::PseudoDSDIV: |
| case Mips::PseudoDUDIV: |
| case Mips::DDIV: |
| case Mips::DDIVU: |
| case Mips::DMOD: |
| case Mips::DMODU: |
| return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), true, false); |
| |
| case Mips::PseudoSELECT_I: |
| case Mips::PseudoSELECT_I64: |
| case Mips::PseudoSELECT_S: |
| case Mips::PseudoSELECT_D32: |
| case Mips::PseudoSELECT_D64: |
| return emitPseudoSELECT(MI, BB, false, Mips::BNE); |
| case Mips::PseudoSELECTFP_F_I: |
| case Mips::PseudoSELECTFP_F_I64: |
| case Mips::PseudoSELECTFP_F_S: |
| case Mips::PseudoSELECTFP_F_D32: |
| case Mips::PseudoSELECTFP_F_D64: |
| return emitPseudoSELECT(MI, BB, true, Mips::BC1F); |
| case Mips::PseudoSELECTFP_T_I: |
| case Mips::PseudoSELECTFP_T_I64: |
| case Mips::PseudoSELECTFP_T_S: |
| case Mips::PseudoSELECTFP_T_D32: |
| case Mips::PseudoSELECTFP_T_D64: |
| return emitPseudoSELECT(MI, BB, true, Mips::BC1T); |
| case Mips::PseudoD_SELECT_I: |
| case Mips::PseudoD_SELECT_I64: |
| return emitPseudoD_SELECT(MI, BB); |
| } |
| } |
| |
| // This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and |
| // Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true) |
| MachineBasicBlock * |
| MipsTargetLowering::emitAtomicBinary(MachineInstr &MI, |
| MachineBasicBlock *BB) const { |
| |
| MachineFunction *MF = BB->getParent(); |
| MachineRegisterInfo &RegInfo = MF->getRegInfo(); |
| const TargetInstrInfo *TII = Subtarget.getInstrInfo(); |
| DebugLoc DL = MI.getDebugLoc(); |
| |
| unsigned AtomicOp; |
| bool NeedsAdditionalReg = false; |
| switch (MI.getOpcode()) { |
| case Mips::ATOMIC_LOAD_ADD_I32: |
| AtomicOp = Mips::ATOMIC_LOAD_ADD_I32_POSTRA; |
| break; |
| case Mips::ATOMIC_LOAD_SUB_I32: |
| AtomicOp = Mips::ATOMIC_LOAD_SUB_I32_POSTRA; |
| break; |
| case Mips::ATOMIC_LOAD_AND_I32: |
| AtomicOp = Mips::ATOMIC_LOAD_AND_I32_POSTRA; |
| break; |
| case Mips::ATOMIC_LOAD_OR_I32: |
| AtomicOp = Mips::ATOMIC_LOAD_OR_I32_POSTRA; |
| break; |
| case Mips::ATOMIC_LOAD_XOR_I32: |
| AtomicOp = Mips::ATOMIC_LOAD_XOR_I32_POSTRA; |
| break; |
| case Mips::ATOMIC_LOAD_NAND_I32: |
| AtomicOp = Mips::ATOMIC_LOAD_NAND_I32_POSTRA; |
| break; |
| case Mips::ATOMIC_SWAP_I32: |
| AtomicOp = Mips::ATOMIC_SWAP_I32_POSTRA; |
| break; |
| case Mips::ATOMIC_LOAD_ADD_I64: |
| AtomicOp = Mips::ATOMIC_LOAD_ADD_I64_POSTRA; |
| break; |
| case Mips::ATOMIC_LOAD_SUB_I64: |
| AtomicOp = Mips::ATOMIC_LOAD_SUB_I64_POSTRA; |
| break; |
| case Mips::ATOMIC_LOAD_AND_I64: |
| AtomicOp = Mips::ATOMIC_LOAD_AND_I64_POSTRA; |
| break; |
| case Mips::ATOMIC_LOAD_OR_I64: |
| AtomicOp = Mips::ATOMIC_LOAD_OR_I64_POSTRA; |
| break; |
| case Mips::ATOMIC_LOAD_XOR_I64: |
| AtomicOp = Mips::ATOMIC_LOAD_XOR_I64_POSTRA; |
| break; |
| case Mips::ATOMIC_LOAD_NAND_I64: |
| AtomicOp = Mips::ATOMIC_LOAD_NAND_I64_POSTRA; |
| break; |
| case Mips::ATOMIC_SWAP_I64: |
| AtomicOp = Mips::ATOMIC_SWAP_I64_POSTRA; |
| break; |
| case Mips::ATOMIC_LOAD_MIN_I32: |
| AtomicOp = Mips::ATOMIC_LOAD_MIN_I32_POSTRA; |
| NeedsAdditionalReg = true; |
| break; |
| case Mips::ATOMIC_LOAD_MAX_I32: |
| AtomicOp = Mips::ATOMIC_LOAD_MAX_I32_POSTRA; |
| NeedsAdditionalReg = true; |
| break; |
| case Mips::ATOMIC_LOAD_UMIN_I32: |
| AtomicOp = Mips::ATOMIC_LOAD_UMIN_I32_POSTRA; |
| NeedsAdditionalReg = true; |
| break; |
| case Mips::ATOMIC_LOAD_UMAX_I32: |
| AtomicOp = Mips::ATOMIC_LOAD_UMAX_I32_POSTRA; |
| NeedsAdditionalReg = true; |
| break; |
| case Mips::ATOMIC_LOAD_MIN_I64: |
| AtomicOp = Mips::ATOMIC_LOAD_MIN_I64_POSTRA; |
| NeedsAdditionalReg = true; |
| break; |
| case Mips::ATOMIC_LOAD_MAX_I64: |
| AtomicOp = Mips::ATOMIC_LOAD_MAX_I64_POSTRA; |
| NeedsAdditionalReg = true; |
| break; |
| case Mips::ATOMIC_LOAD_UMIN_I64: |
| AtomicOp = Mips::ATOMIC_LOAD_UMIN_I64_POSTRA; |
| NeedsAdditionalReg = true; |
| break; |
| case Mips::ATOMIC_LOAD_UMAX_I64: |
| AtomicOp = Mips::ATOMIC_LOAD_UMAX_I64_POSTRA; |
| NeedsAdditionalReg = true; |
| break; |
| default: |
| llvm_unreachable("Unknown pseudo atomic for replacement!"); |
| } |
| |
| Register OldVal = MI.getOperand(0).getReg(); |
| Register Ptr = MI.getOperand(1).getReg(); |
| Register Incr = MI.getOperand(2).getReg(); |
| Register Scratch = RegInfo.createVirtualRegister(RegInfo.getRegClass(OldVal)); |
| |
| MachineBasicBlock::iterator II(MI); |
| |
| // The scratch registers here with the EarlyClobber | Define | Implicit |
| // flags is used to persuade the register allocator and the machine |
| // verifier to accept the usage of this register. This has to be a real |
| // register which has an UNDEF value but is dead after the instruction which |
| // is unique among the registers chosen for the instruction. |
| |
| // The EarlyClobber flag has the semantic properties that the operand it is |
| // attached to is clobbered before the rest of the inputs are read. Hence it |
| // must be unique among the operands to the instruction. |
| // The Define flag is needed to coerce the machine verifier that an Undef |
| // value isn't a problem. |
| // The Dead flag is needed as the value in scratch isn't used by any other |
| // instruction. Kill isn't used as Dead is more precise. |
| // The implicit flag is here due to the interaction between the other flags |
| // and the machine verifier. |
| |
| // For correctness purpose, a new pseudo is introduced here. We need this |
| // new pseudo, so that FastRegisterAllocator does not see an ll/sc sequence |
| // that is spread over >1 basic blocks. A register allocator which |
| // introduces (or any codegen infact) a store, can violate the expectations |
| // of the hardware. |
| // |
| // An atomic read-modify-write sequence starts with a linked load |
| // instruction and ends with a store conditional instruction. The atomic |
| // read-modify-write sequence fails if any of the following conditions |
| // occur between the execution of ll and sc: |
| // * A coherent store is completed by another process or coherent I/O |
| // module into the block of synchronizable physical memory containing |
| // the word. The size and alignment of the block is |
| // implementation-dependent. |
| // * A coherent store is executed between an LL and SC sequence on the |
| // same processor to the block of synchornizable physical memory |
| // containing the word. |
| // |
| |
| Register PtrCopy = RegInfo.createVirtualRegister(RegInfo.getRegClass(Ptr)); |
| Register IncrCopy = RegInfo.createVirtualRegister(RegInfo.getRegClass(Incr)); |
| |
| BuildMI(*BB, II, DL, TII->get(Mips::COPY), IncrCopy).addReg(Incr); |
| BuildMI(*BB, II, DL, TII->get(Mips::COPY), PtrCopy).addReg(Ptr); |
| |
| MachineInstrBuilder MIB = |
| BuildMI(*BB, II, DL, TII->get(AtomicOp)) |
| .addReg(OldVal, RegState::Define | RegState::EarlyClobber) |
| .addReg(PtrCopy) |
| .addReg(IncrCopy) |
| .addReg(Scratch, RegState::Define | RegState::EarlyClobber | |
| RegState::Implicit | RegState::Dead); |
| if (NeedsAdditionalReg) { |
| Register Scratch2 = |
| RegInfo.createVirtualRegister(RegInfo.getRegClass(OldVal)); |
| MIB.addReg(Scratch2, RegState::Define | RegState::EarlyClobber | |
| RegState::Implicit | RegState::Dead); |
| } |
| |
| MI.eraseFromParent(); |
| |
| return BB; |
| } |
| |
| MachineBasicBlock *MipsTargetLowering::emitSignExtendToI32InReg( |
| MachineInstr &MI, MachineBasicBlock *BB, unsigned Size, unsigned DstReg, |
| unsigned SrcReg) const { |
| const TargetInstrInfo *TII = Subtarget.getInstrInfo(); |
| const DebugLoc &DL = MI.getDebugLoc(); |
| |
| if (Subtarget.hasMips32r2() && Size == 1) { |
| BuildMI(BB, DL, TII->get(Mips::SEB), DstReg).addReg(SrcReg); |
| return BB; |
| } |
| |
| if (Subtarget.hasMips32r2() && Size == 2) { |
| BuildMI(BB, DL, TII->get(Mips::SEH), DstReg).addReg(SrcReg); |
| return BB; |
| } |
| |
| MachineFunction *MF = BB->getParent(); |
| MachineRegisterInfo &RegInfo = MF->getRegInfo(); |
| const TargetRegisterClass *RC = getRegClassFor(MVT::i32); |
| Register ScrReg = RegInfo.createVirtualRegister(RC); |
| |
| assert(Size < 32); |
| int64_t ShiftImm = 32 - (Size * 8); |
| |
| BuildMI(BB, DL, TII->get(Mips::SLL), ScrReg).addReg(SrcReg).addImm(ShiftImm); |
| BuildMI(BB, DL, TII->get(Mips::SRA), DstReg).addReg(ScrReg).addImm(ShiftImm); |
| |
| return BB; |
| } |
| |
| MachineBasicBlock *MipsTargetLowering::emitAtomicBinaryPartword( |
| MachineInstr &MI, MachineBasicBlock *BB, unsigned Size) const { |
| assert((Size == 1 || Size == 2) && |
| "Unsupported size for EmitAtomicBinaryPartial."); |
| |
| MachineFunction *MF = BB->getParent(); |
| MachineRegisterInfo &RegInfo = MF->getRegInfo(); |
| const TargetRegisterClass *RC = getRegClassFor(MVT::i32); |
| const bool ArePtrs64bit = ABI.ArePtrs64bit(); |
| const TargetRegisterClass *RCp = |
| getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32); |
| const TargetInstrInfo *TII = Subtarget.getInstrInfo(); |
| DebugLoc DL = MI.getDebugLoc(); |
| |
| Register Dest = MI.getOperand(0).getReg(); |
| Register Ptr = MI.getOperand(1).getReg(); |
| Register Incr = MI.getOperand(2).getReg(); |
| |
| Register AlignedAddr = RegInfo.createVirtualRegister(RCp); |
| Register ShiftAmt = RegInfo.createVirtualRegister(RC); |
| Register Mask = RegInfo.createVirtualRegister(RC); |
| Register Mask2 = RegInfo.createVirtualRegister(RC); |
| Register Incr2 = RegInfo.createVirtualRegister(RC); |
| Register MaskLSB2 = RegInfo.createVirtualRegister(RCp); |
| Register PtrLSB2 = RegInfo.createVirtualRegister(RC); |
| Register MaskUpper = RegInfo.createVirtualRegister(RC); |
| Register Scratch = RegInfo.createVirtualRegister(RC); |
| Register Scratch2 = RegInfo.createVirtualRegister(RC); |
| Register Scratch3 = RegInfo.createVirtualRegister(RC); |
| |
| unsigned AtomicOp = 0; |
| bool NeedsAdditionalReg = false; |
| switch (MI.getOpcode()) { |
| case Mips::ATOMIC_LOAD_NAND_I8: |
| AtomicOp = Mips::ATOMIC_LOAD_NAND_I8_POSTRA; |
| break; |
| case Mips::ATOMIC_LOAD_NAND_I16: |
| AtomicOp = Mips::ATOMIC_LOAD_NAND_I16_POSTRA; |
| break; |
| case Mips::ATOMIC_SWAP_I8: |
| AtomicOp = Mips::ATOMIC_SWAP_I8_POSTRA; |
| break; |
| case Mips::ATOMIC_SWAP_I16: |
| AtomicOp = Mips::ATOMIC_SWAP_I16_POSTRA; |
| break; |
| case Mips::ATOMIC_LOAD_ADD_I8: |
| AtomicOp = Mips::ATOMIC_LOAD_ADD_I8_POSTRA; |
| break; |
| case Mips::ATOMIC_LOAD_ADD_I16: |
| AtomicOp = Mips::ATOMIC_LOAD_ADD_I16_POSTRA; |
| break; |
| case Mips::ATOMIC_LOAD_SUB_I8: |
| AtomicOp = Mips::ATOMIC_LOAD_SUB_I8_POSTRA; |
| break; |
| case Mips::ATOMIC_LOAD_SUB_I16: |
| AtomicOp = Mips::ATOMIC_LOAD_SUB_I16_POSTRA; |
| break; |
| case Mips::ATOMIC_LOAD_AND_I8: |
| AtomicOp = Mips::ATOMIC_LOAD_AND_I8_POSTRA; |
| break; |
| case Mips::ATOMIC_LOAD_AND_I16: |
| AtomicOp = Mips::ATOMIC_LOAD_AND_I16_POSTRA; |
| break; |
| case Mips::ATOMIC_LOAD_OR_I8: |
| AtomicOp = Mips::ATOMIC_LOAD_OR_I8_POSTRA; |
| break; |
| case Mips::ATOMIC_LOAD_OR_I16: |
| AtomicOp = Mips::ATOMIC_LOAD_OR_I16_POSTRA; |
| break; |
| case Mips::ATOMIC_LOAD_XOR_I8: |
| AtomicOp = Mips::ATOMIC_LOAD_XOR_I8_POSTRA; |
| break; |
| case Mips::ATOMIC_LOAD_XOR_I16: |
| AtomicOp = Mips::ATOMIC_LOAD_XOR_I16_POSTRA; |
| break; |
| case Mips::ATOMIC_LOAD_MIN_I8: |
| AtomicOp = Mips::ATOMIC_LOAD_MIN_I8_POSTRA; |
| NeedsAdditionalReg = true; |
| break; |
| case Mips::ATOMIC_LOAD_MIN_I16: |
| AtomicOp = Mips::ATOMIC_LOAD_MIN_I16_POSTRA; |
| NeedsAdditionalReg = true; |
| break; |
| case Mips::ATOMIC_LOAD_MAX_I8: |
| AtomicOp = Mips::ATOMIC_LOAD_MAX_I8_POSTRA; |
| NeedsAdditionalReg = true; |
| break; |
| case Mips::ATOMIC_LOAD_MAX_I16: |
| AtomicOp = Mips::ATOMIC_LOAD_MAX_I16_POSTRA; |
| NeedsAdditionalReg = true; |
| break; |
| case Mips::ATOMIC_LOAD_UMIN_I8: |
| AtomicOp = Mips::ATOMIC_LOAD_UMIN_I8_POSTRA; |
| NeedsAdditionalReg = true; |
| break; |
| case Mips::ATOMIC_LOAD_UMIN_I16: |
| AtomicOp = Mips::ATOMIC_LOAD_UMIN_I16_POSTRA; |
| NeedsAdditionalReg = true; |
| break; |
| case Mips::ATOMIC_LOAD_UMAX_I8: |
| AtomicOp = Mips::ATOMIC_LOAD_UMAX_I8_POSTRA; |
| NeedsAdditionalReg = true; |
| break; |
| case Mips::ATOMIC_LOAD_UMAX_I16: |
| AtomicOp = Mips::ATOMIC_LOAD_UMAX_I16_POSTRA; |
| NeedsAdditionalReg = true; |
| break; |
| default: |
| llvm_unreachable("Unknown subword atomic pseudo for expansion!"); |
| } |
| |
| // insert new blocks after the current block |
| const BasicBlock *LLVM_BB = BB->getBasicBlock(); |
| MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); |
| MachineFunction::iterator It = ++BB->getIterator(); |
| MF->insert(It, exitMBB); |
| |
| // Transfer the remainder of BB and its successor edges to exitMBB. |
| exitMBB->splice(exitMBB->begin(), BB, |
| std::next(MachineBasicBlock::iterator(MI)), BB->end()); |
| exitMBB->transferSuccessorsAndUpdatePHIs(BB); |
| |
| BB->addSuccessor(exitMBB, BranchProbability::getOne()); |
| |
| // thisMBB: |
| // addiu masklsb2,$0,-4 # 0xfffffffc |
| // and alignedaddr,ptr,masklsb2 |
| // andi ptrlsb2,ptr,3 |
| // sll shiftamt,ptrlsb2,3 |
| // ori maskupper,$0,255 # 0xff |
| // sll mask,maskupper,shiftamt |
| // nor mask2,$0,mask |
| // sll incr2,incr,shiftamt |
| |
| int64_t MaskImm = (Size == 1) ? 255 : 65535; |
| BuildMI(BB, DL, TII->get(ABI.GetPtrAddiuOp()), MaskLSB2) |
| .addReg(ABI.GetNullPtr()).addImm(-4); |
| BuildMI(BB, DL, TII->get(ABI.GetPtrAndOp()), AlignedAddr) |
| .addReg(Ptr).addReg(MaskLSB2); |
| BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2) |
| .addReg(Ptr, 0, ArePtrs64bit ? Mips::sub_32 : 0).addImm(3); |
| if (Subtarget.isLittle()) { |
| BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); |
| } else { |
| Register Off = RegInfo.createVirtualRegister(RC); |
| BuildMI(BB, DL, TII->get(Mips::XORi), Off) |
| .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2); |
| BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3); |
| } |
| BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper) |
| .addReg(Mips::ZERO).addImm(MaskImm); |
| BuildMI(BB, DL, TII->get(Mips::SLLV), Mask) |
| .addReg(MaskUpper).addReg(ShiftAmt); |
| BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); |
| BuildMI(BB, DL, TII->get(Mips::SLLV), Incr2).addReg(Incr).addReg(ShiftAmt); |
| |
| |
| // The purposes of the flags on the scratch registers is explained in |
| // emitAtomicBinary. In summary, we need a scratch register which is going to |
| // be undef, that is unique among registers chosen for the instruction. |
| |
| MachineInstrBuilder MIB = |
| BuildMI(BB, DL, TII->get(AtomicOp)) |
| .addReg(Dest, RegState::Define | RegState::EarlyClobber) |
| .addReg(AlignedAddr) |
| .addReg(Incr2) |
| .addReg(Mask) |
| .addReg(Mask2) |
| .addReg(ShiftAmt) |
| .addReg(Scratch, RegState::EarlyClobber | RegState::Define | |
| RegState::Dead | RegState::Implicit) |
| .addReg(Scratch2, RegState::EarlyClobber | RegState::Define | |
| RegState::Dead | RegState::Implicit) |
| .addReg(Scratch3, RegState::EarlyClobber | RegState::Define | |
| RegState::Dead | RegState::Implicit); |
| if (NeedsAdditionalReg) { |
| Register Scratch4 = RegInfo.createVirtualRegister(RC); |
| MIB.addReg(Scratch4, RegState::EarlyClobber | RegState::Define | |
| RegState::Dead | RegState::Implicit); |
| } |
| |
| MI.eraseFromParent(); // The instruction is gone now. |
| |
| return exitMBB; |
| } |
| |
| // Lower atomic compare and swap to a pseudo instruction, taking care to |
| // define a scratch register for the pseudo instruction's expansion. The |
| // instruction is expanded after the register allocator as to prevent |
| // the insertion of stores between the linked load and the store conditional. |
| |
| MachineBasicBlock * |
| MipsTargetLowering::emitAtomicCmpSwap(MachineInstr &MI, |
| MachineBasicBlock *BB) const { |
| |
| assert((MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I32 || |
| MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I64) && |
| "Unsupported atomic pseudo for EmitAtomicCmpSwap."); |
| |
| const unsigned Size = MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I32 ? 4 : 8; |
| |
| MachineFunction *MF = BB->getParent(); |
| MachineRegisterInfo &MRI = MF->getRegInfo(); |
| const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8)); |
| const TargetInstrInfo *TII = Subtarget.getInstrInfo(); |
| DebugLoc DL = MI.getDebugLoc(); |
| |
| unsigned AtomicOp = MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I32 |
| ? Mips::ATOMIC_CMP_SWAP_I32_POSTRA |
| : Mips::ATOMIC_CMP_SWAP_I64_POSTRA; |
| Register Dest = MI.getOperand(0).getReg(); |
| Register Ptr = MI.getOperand(1).getReg(); |
| Register OldVal = MI.getOperand(2).getReg(); |
| Register NewVal = MI.getOperand(3).getReg(); |
| |
| Register Scratch = MRI.createVirtualRegister(RC); |
| MachineBasicBlock::iterator II(MI); |
| |
| // We need to create copies of the various registers and kill them at the |
| // atomic pseudo. If the copies are not made, when the atomic is expanded |
| // after fast register allocation, the spills will end up outside of the |
| // blocks that their values are defined in, causing livein errors. |
| |
| Register PtrCopy = MRI.createVirtualRegister(MRI.getRegClass(Ptr)); |
| Register OldValCopy = MRI.createVirtualRegister(MRI.getRegClass(OldVal)); |
| Register NewValCopy = MRI.createVirtualRegister(MRI.getRegClass(NewVal)); |
| |
| BuildMI(*BB, II, DL, TII->get(Mips::COPY), PtrCopy).addReg(Ptr); |
| BuildMI(*BB, II, DL, TII->get(Mips::COPY), OldValCopy).addReg(OldVal); |
| BuildMI(*BB, II, DL, TII->get(Mips::COPY), NewValCopy).addReg(NewVal); |
| |
| // The purposes of the flags on the scratch registers is explained in |
| // emitAtomicBinary. In summary, we need a scratch register which is going to |
| // be undef, that is unique among registers chosen for the instruction. |
| |
| BuildMI(*BB, II, DL, TII->get(AtomicOp)) |
| .addReg(Dest, RegState::Define | RegState::EarlyClobber) |
| .addReg(PtrCopy, RegState::Kill) |
| .addReg(OldValCopy, RegState::Kill) |
| .addReg(NewValCopy, RegState::Kill) |
| .addReg(Scratch, RegState::EarlyClobber | RegState::Define | |
| RegState::Dead | RegState::Implicit); |
| |
| MI.eraseFromParent(); // The instruction is gone now. |
| |
| return BB; |
| } |
| |
| MachineBasicBlock *MipsTargetLowering::emitAtomicCmpSwapPartword( |
| MachineInstr &MI, MachineBasicBlock *BB, unsigned Size) const { |
| assert((Size == 1 || Size == 2) && |
| "Unsupported size for EmitAtomicCmpSwapPartial."); |
| |
| MachineFunction *MF = BB->getParent(); |
| MachineRegisterInfo &RegInfo = MF->getRegInfo(); |
| const TargetRegisterClass *RC = getRegClassFor(MVT::i32); |
| const bool ArePtrs64bit = ABI.ArePtrs64bit(); |
| const TargetRegisterClass *RCp = |
| getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32); |
| const TargetInstrInfo *TII = Subtarget.getInstrInfo(); |
| DebugLoc DL = MI.getDebugLoc(); |
| |
| Register Dest = MI.getOperand(0).getReg(); |
| Register Ptr = MI.getOperand(1).getReg(); |
| Register CmpVal = MI.getOperand(2).getReg(); |
| Register NewVal = MI.getOperand(3).getReg(); |
| |
| Register AlignedAddr = RegInfo.createVirtualRegister(RCp); |
| Register ShiftAmt = RegInfo.createVirtualRegister(RC); |
| Register Mask = RegInfo.createVirtualRegister(RC); |
| Register Mask2 = RegInfo.createVirtualRegister(RC); |
| Register ShiftedCmpVal = RegInfo.createVirtualRegister(RC); |
| Register ShiftedNewVal = RegInfo.createVirtualRegister(RC); |
| Register MaskLSB2 = RegInfo.createVirtualRegister(RCp); |
| Register PtrLSB2 = RegInfo.createVirtualRegister(RC); |
| Register MaskUpper = RegInfo.createVirtualRegister(RC); |
| Register MaskedCmpVal = RegInfo.createVirtualRegister(RC); |
| Register MaskedNewVal = RegInfo.createVirtualRegister(RC); |
| unsigned AtomicOp = MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I8 |
| ? Mips::ATOMIC_CMP_SWAP_I8_POSTRA |
| : Mips::ATOMIC_CMP_SWAP_I16_POSTRA; |
| |
| // The scratch registers here with the EarlyClobber | Define | Dead | Implicit |
| // flags are used to coerce the register allocator and the machine verifier to |
| // accept the usage of these registers. |
| // The EarlyClobber flag has the semantic properties that the operand it is |
| // attached to is clobbered before the rest of the inputs are read. Hence it |
| // must be unique among the operands to the instruction. |
| // The Define flag is needed to coerce the machine verifier that an Undef |
| // value isn't a problem. |
| // The Dead flag is needed as the value in scratch isn't used by any other |
| // instruction. Kill isn't used as Dead is more precise. |
| Register Scratch = RegInfo.createVirtualRegister(RC); |
| Register Scratch2 = RegInfo.createVirtualRegister(RC); |
| |
| // insert new blocks after the current block |
| const BasicBlock *LLVM_BB = BB->getBasicBlock(); |
| MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); |
| MachineFunction::iterator It = ++BB->getIterator(); |
| MF->insert(It, exitMBB); |
| |
| // Transfer the remainder of BB and its successor edges to exitMBB. |
| exitMBB->splice(exitMBB->begin(), BB, |
| std::next(MachineBasicBlock::iterator(MI)), BB->end()); |
| exitMBB->transferSuccessorsAndUpdatePHIs(BB); |
| |
| BB->addSuccessor(exitMBB, BranchProbability::getOne()); |
| |
| // thisMBB: |
| // addiu masklsb2,$0,-4 # 0xfffffffc |
| // and alignedaddr,ptr,masklsb2 |
| // andi ptrlsb2,ptr,3 |
| // xori ptrlsb2,ptrlsb2,3 # Only for BE |
| // sll shiftamt,ptrlsb2,3 |
| // ori maskupper,$0,255 # 0xff |
| // sll mask,maskupper,shiftamt |
| // nor mask2,$0,mask |
| // andi maskedcmpval,cmpval,255 |
| // sll shiftedcmpval,maskedcmpval,shiftamt |
| // andi maskednewval,newval,255 |
| // sll shiftednewval,maskednewval,shiftamt |
| int64_t MaskImm = (Size == 1) ? 255 : 65535; |
| BuildMI(BB, DL, TII->get(ArePtrs64bit ? Mips::DADDiu : Mips::ADDiu), MaskLSB2) |
| .addReg(ABI.GetNullPtr()).addImm(-4); |
| BuildMI(BB, DL, TII->get(ArePtrs64bit ? Mips::AND64 : Mips::AND), AlignedAddr) |
| .addReg(Ptr).addReg(MaskLSB2); |
| BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2) |
| .addReg(Ptr, 0, ArePtrs64bit ? Mips::sub_32 : 0).addImm(3); |
| if (Subtarget.isLittle()) { |
| BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); |
| } else { |
| Register Off = RegInfo.createVirtualRegister(RC); |
| BuildMI(BB, DL, TII->get(Mips::XORi), Off) |
| .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2); |
| BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3); |
| } |
| BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper) |
| .addReg(Mips::ZERO).addImm(MaskImm); |
| BuildMI(BB, DL, TII->get(Mips::SLLV), Mask) |
| .addReg(MaskUpper).addReg(ShiftAmt); |
| BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); |
| BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedCmpVal) |
| .addReg(CmpVal).addImm(MaskImm); |
| BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedCmpVal) |
| .addReg(MaskedCmpVal).addReg(ShiftAmt); |
| BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedNewVal) |
| .addReg(NewVal).addImm(MaskImm); |
| BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedNewVal) |
| .addReg(MaskedNewVal).addReg(ShiftAmt); |
| |
| // The purposes of the flags on the scratch registers are explained in |
| // emitAtomicBinary. In summary, we need a scratch register which is going to |
| // be undef, that is unique among the register chosen for the instruction. |
| |
| BuildMI(BB, DL, TII->get(AtomicOp)) |
| .addReg(Dest, RegState::Define | RegState::EarlyClobber) |
| .addReg(AlignedAddr) |
| .addReg(Mask) |
| .addReg(ShiftedCmpVal) |
| .addReg(Mask2) |
| .addReg(ShiftedNewVal) |
| .addReg(ShiftAmt) |
| .addReg(Scratch, RegState::EarlyClobber | RegState::Define | |
| RegState::Dead | RegState::Implicit) |
| .addReg(Scratch2, RegState::EarlyClobber | RegState::Define | |
| RegState::Dead | RegState::Implicit); |
| |
| MI.eraseFromParent(); // The instruction is gone now. |
| |
| return exitMBB; |
| } |
| |
| SDValue MipsTargetLowering::lowerBRCOND(SDValue Op, SelectionDAG &DAG) const { |
| // The first operand is the chain, the second is the condition, the third is |
| // the block to branch to if the condition is true. |
| SDValue Chain = Op.getOperand(0); |
| SDValue Dest = Op.getOperand(2); |
| SDLoc DL(Op); |
| |
| assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6()); |
| SDValue CondRes = createFPCmp(DAG, Op.getOperand(1)); |
| |
| // Return if flag is not set by a floating point comparison. |
| if (CondRes.getOpcode() != MipsISD::FPCmp) |
| return Op; |
| |
| SDValue CCNode = CondRes.getOperand(2); |
| Mips::CondCode CC = |
| (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue(); |
| unsigned Opc = invertFPCondCodeUser(CC) ? Mips::BRANCH_F : Mips::BRANCH_T; |
| SDValue BrCode = DAG.getConstant(Opc, DL, MVT::i32); |
| SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32); |
| return DAG.getNode(MipsISD::FPBrcond, DL, Op.getValueType(), Chain, BrCode, |
| FCC0, Dest, CondRes); |
| } |
| |
| SDValue MipsTargetLowering:: |
| lowerSELECT(SDValue Op, SelectionDAG &DAG) const |
| { |
| assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6()); |
| SDValue Cond = createFPCmp(DAG, Op.getOperand(0)); |
| |
| // Return if flag is not set by a floating point comparison. |
| if (Cond.getOpcode() != MipsISD::FPCmp) |
| return Op; |
| |
| return createCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2), |
| SDLoc(Op)); |
| } |
| |
| SDValue MipsTargetLowering::lowerSETCC(SDValue Op, SelectionDAG &DAG) const { |
| assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6()); |
| SDValue Cond = createFPCmp(DAG, Op); |
| |
| assert(Cond.getOpcode() == MipsISD::FPCmp && |
| "Floating point operand expected."); |
| |
| SDLoc DL(Op); |
| SDValue True = DAG.getConstant(1, DL, MVT::i32); |
| SDValue False = DAG.getConstant(0, DL, MVT::i32); |
| |
| return createCMovFP(DAG, Cond, True, False, DL); |
| } |
| |
| SDValue MipsTargetLowering::lowerGlobalAddress(SDValue Op, |
| SelectionDAG &DAG) const { |
| EVT Ty = Op.getValueType(); |
| GlobalAddressSDNode *N = cast<GlobalAddressSDNode>(Op); |
| const GlobalValue *GV = N->getGlobal(); |
| |
| if (!isPositionIndependent()) { |
| const MipsTargetObjectFile *TLOF = |
| static_cast<const MipsTargetObjectFile *>( |
| getTargetMachine().getObjFileLowering()); |
| const GlobalObject *GO = GV->getBaseObject(); |
| if (GO && TLOF->IsGlobalInSmallSection(GO, getTargetMachine())) |
| // %gp_rel relocation |
| return getAddrGPRel(N, SDLoc(N), Ty, DAG, ABI.IsN64()); |
| |
| // %hi/%lo relocation |
| return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG) |
| // %highest/%higher/%hi/%lo relocation |
| : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG); |
| } |
| |
| // Every other architecture would use shouldAssumeDSOLocal in here, but |
| // mips is special. |
| // * In PIC code mips requires got loads even for local statics! |
| // * To save on got entries, for local statics the got entry contains the |
| // page and an additional add instruction takes care of the low bits. |
| // * It is legal to access a hidden symbol with a non hidden undefined, |
| // so one cannot guarantee that all access to a hidden symbol will know |
| // it is hidden. |
| // * Mips linkers don't support creating a page and a full got entry for |
| // the same symbol. |
| // * Given all that, we have to use a full got entry for hidden symbols :-( |
| if (GV->hasLocalLinkage()) |
| return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64()); |
| |
| if (Subtarget.useXGOT()) |
| return getAddrGlobalLargeGOT( |
| N, SDLoc(N), Ty, DAG, MipsII::MO_GOT_HI16, MipsII::MO_GOT_LO16, |
| DAG.getEntryNode(), |
| MachinePointerInfo::getGOT(DAG.getMachineFunction())); |
| |
| return getAddrGlobal( |
| N, SDLoc(N), Ty, DAG, |
| (ABI.IsN32() || ABI.IsN64()) ? MipsII::MO_GOT_DISP : MipsII::MO_GOT, |
| DAG.getEntryNode(), MachinePointerInfo::getGOT(DAG.getMachineFunction())); |
| } |
| |
| SDValue MipsTargetLowering::lowerBlockAddress(SDValue Op, |
| SelectionDAG &DAG) const { |
| BlockAddressSDNode *N = cast<BlockAddressSDNode>(Op); |
| EVT Ty = Op.getValueType(); |
| |
| if (!isPositionIndependent()) |
| return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG) |
| : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG); |
| |
| return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64()); |
| } |
| |
| SDValue MipsTargetLowering:: |
| lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const |
| { |
| // If the relocation model is PIC, use the General Dynamic TLS Model or |
| // Local Dynamic TLS model, otherwise use the Initial Exec or |
| // Local Exec TLS Model. |
| |
| GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); |
| if (DAG.getTarget().useEmulatedTLS()) |
| return LowerToTLSEmulatedModel(GA, DAG); |
| |
| SDLoc DL(GA); |
| const GlobalValue *GV = GA->getGlobal(); |
| EVT PtrVT = getPointerTy(DAG.getDataLayout()); |
| |
| TLSModel::Model model = getTargetMachine().getTLSModel(GV); |
| |
| if (model == TLSModel::GeneralDynamic || model == TLSModel::LocalDynamic) { |
| // General Dynamic and Local Dynamic TLS Model. |
| unsigned Flag = (model == TLSModel::LocalDynamic) ? MipsII::MO_TLSLDM |
| : MipsII::MO_TLSGD; |
| |
| SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, Flag); |
| SDValue Argument = DAG.getNode(MipsISD::Wrapper, DL, PtrVT, |
| getGlobalReg(DAG, PtrVT), TGA); |
| unsigned PtrSize = PtrVT.getSizeInBits(); |
| IntegerType *PtrTy = Type::getIntNTy(*DAG.getContext(), PtrSize); |
| |
| SDValue TlsGetAddr = DAG.getExternalSymbol("__tls_get_addr", PtrVT); |
| |
| ArgListTy Args; |
| ArgListEntry Entry; |
| Entry.Node = Argument; |
| Entry.Ty = PtrTy; |
| Args.push_back(Entry); |
| |
| TargetLowering::CallLoweringInfo CLI(DAG); |
| CLI.setDebugLoc(DL) |
| .setChain(DAG.getEntryNode()) |
| .setLibCallee(CallingConv::C, PtrTy, TlsGetAddr, std::move(Args)); |
| std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI); |
| |
| SDValue Ret = CallResult.first; |
| |
| if (model != TLSModel::LocalDynamic) |
| return Ret; |
| |
| SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, |
| MipsII::MO_DTPREL_HI); |
| SDValue Hi = DAG.getNode(MipsISD::TlsHi, DL, PtrVT, TGAHi); |
| SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, |
| MipsII::MO_DTPREL_LO); |
| SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo); |
| SDValue Add = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Ret); |
| return DAG.getNode(ISD::ADD, DL, PtrVT, Add, Lo); |
| } |
| |
| SDValue Offset; |
| if (model == TLSModel::InitialExec) { |
| // Initial Exec TLS Model |
| SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, |
| MipsII::MO_GOTTPREL); |
| TGA = DAG.getNode(MipsISD::Wrapper, DL, PtrVT, getGlobalReg(DAG, PtrVT), |
| TGA); |
| Offset = |
| DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), TGA, MachinePointerInfo()); |
| } else { |
| // Local Exec TLS Model |
| assert(model == TLSModel::LocalExec); |
| SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, |
| MipsII::MO_TPREL_HI); |
| SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, |
| MipsII::MO_TPREL_LO); |
| SDValue Hi = DAG.getNode(MipsISD::TlsHi, DL, PtrVT, TGAHi); |
| SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo); |
| Offset = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo); |
| } |
| |
| SDValue ThreadPointer = DAG.getNode(MipsISD::ThreadPointer, DL, PtrVT); |
| return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadPointer, Offset); |
| } |
| |
| SDValue MipsTargetLowering:: |
| lowerJumpTable(SDValue Op, SelectionDAG &DAG) const |
| { |
| JumpTableSDNode *N = cast<JumpTableSDNode>(Op); |
| EVT Ty = Op.getValueType(); |
| |
| if (!isPositionIndependent()) |
| return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG) |
| : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG); |
| |
| return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64()); |
| } |
| |
| SDValue MipsTargetLowering:: |
| lowerConstantPool(SDValue Op, SelectionDAG &DAG) const |
| { |
| ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op); |
| EVT Ty = Op.getValueType(); |
| |
| if (!isPositionIndependent()) { |
| const MipsTargetObjectFile *TLOF = |
| static_cast<const MipsTargetObjectFile *>( |
| getTargetMachine().getObjFileLowering()); |
| |
| if (TLOF->IsConstantInSmallSection(DAG.getDataLayout(), N->getConstVal(), |
| getTargetMachine())) |
| // %gp_rel relocation |
| return getAddrGPRel(N, SDLoc(N), Ty, DAG, ABI.IsN64()); |
| |
| return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG) |
| : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG); |
| } |
| |
| return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64()); |
| } |
| |
| SDValue MipsTargetLowering::lowerVASTART(SDValue Op, SelectionDAG &DAG) const { |
| MachineFunction &MF = DAG.getMachineFunction(); |
| MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>(); |
| |
| SDLoc DL(Op); |
| SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), |
| getPointerTy(MF.getDataLayout())); |
| |
| // vastart just stores the address of the VarArgsFrameIndex slot into the |
| // memory location argument. |
| const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); |
| return DAG.getStore(Op.getOperand(0), DL, FI, Op.getOperand(1), |
| MachinePointerInfo(SV)); |
| } |
| |
| SDValue MipsTargetLowering::lowerVAARG(SDValue Op, SelectionDAG &DAG) const { |
| SDNode *Node = Op.getNode(); |
| EVT VT = Node->getValueType(0); |
| SDValue Chain = Node->getOperand(0); |
| SDValue VAListPtr = Node->getOperand(1); |
| const Align Align = |
| llvm::MaybeAlign(Node->getConstantOperandVal(3)).valueOrOne(); |
| const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); |
| SDLoc DL(Node); |
| unsigned ArgSlotSizeInBytes = (ABI.IsN32() || ABI.IsN64()) ? 8 : 4; |
| |
| SDValue VAListLoad = DAG.getLoad(getPointerTy(DAG.getDataLayout()), DL, Chain, |
| VAListPtr, MachinePointerInfo(SV)); |
| SDValue VAList = VAListLoad; |
| |
| // Re-align the pointer if necessary. |
| // It should only ever be necessary for 64-bit types on O32 since the minimum |
| // argument alignment is the same as the maximum type alignment for N32/N64. |
| // |
| // FIXME: We currently align too often. The code generator doesn't notice |
| // when the pointer is still aligned from the last va_arg (or pair of |
| // va_args for the i64 on O32 case). |
| if (Align > getMinStackArgumentAlignment()) { |
| VAList = DAG.getNode( |
| ISD::ADD, DL, VAList.getValueType(), VAList, |
| DAG.getConstant(Align.value() - 1, DL, VAList.getValueType())); |
| |
| VAList = DAG.getNode( |
| ISD::AND, DL, VAList.getValueType(), VAList, |
| DAG.getConstant(-(int64_t)Align.value(), DL, VAList.getValueType())); |
| } |
| |
| // Increment the pointer, VAList, to the next vaarg. |
| auto &TD = DAG.getDataLayout(); |
| unsigned ArgSizeInBytes = |
| TD.getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext())); |
| SDValue Tmp3 = |
| DAG.getNode(ISD::ADD, DL, VAList.getValueType(), VAList, |
| DAG.getConstant(alignTo(ArgSizeInBytes, ArgSlotSizeInBytes), |
| DL, VAList.getValueType())); |
| // Store the incremented VAList to the legalized pointer |
| Chain = DAG.getStore(VAListLoad.getValue(1), DL, Tmp3, VAListPtr, |
| MachinePointerInfo(SV)); |
| |
| // In big-endian mode we must adjust the pointer when the load size is smaller |
| // than the argument slot size. We must also reduce the known alignment to |
| // match. For example in the N64 ABI, we must add 4 bytes to the offset to get |
| // the correct half of the slot, and reduce the alignment from 8 (slot |
| // alignment) down to 4 (type alignment). |
| if (!Subtarget.isLittle() && ArgSizeInBytes < ArgSlotSizeInBytes) { |
| unsigned Adjustment = ArgSlotSizeInBytes - ArgSizeInBytes; |
| VAList = DAG.getNode(ISD::ADD, DL, VAListPtr.getValueType(), VAList, |
| DAG.getIntPtrConstant(Adjustment, DL)); |
| } |
| // Load the actual argument out of the pointer VAList |
| return DAG.getLoad(VT, DL, Chain, VAList, MachinePointerInfo()); |
| } |
| |
| static SDValue lowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG, |
| bool HasExtractInsert) { |
| EVT TyX = Op.getOperand(0).getValueType(); |
| EVT TyY = Op.getOperand(1).getValueType(); |
| SDLoc DL(Op); |
| SDValue Const1 = DAG.getConstant(1, DL, MVT::i32); |
| SDValue Const31 = DAG.getConstant(31, DL, MVT::i32); |
| SDValue Res; |
| |
| // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it |
| // to i32. |
| SDValue X = (TyX == MVT::f32) ? |
| DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) : |
| DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0), |
| Const1); |
| SDValue Y = (TyY == MVT::f32) ? |
| DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(1)) : |
| DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(1), |
| Const1); |
| |
| if (HasExtractInsert) { |
| // ext E, Y, 31, 1 ; extract bit31 of Y |
| // ins X, E, 31, 1 ; insert extracted bit at bit31 of X |
| SDValue E = DAG.getNode(MipsISD::Ext, DL, MVT::i32, Y, Const31, Const1); |
| Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, E, Const31, Const1, X); |
| } else { |
| // sll SllX, X, 1 |
| // srl SrlX, SllX, 1 |
| // srl SrlY, Y, 31 |
| // sll SllY, SrlX, 31 |
| // or Or, SrlX, SllY |
| SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1); |
| SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1); |
| SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31); |
| SDValue SllY = DAG.getNode(ISD::SHL, DL, MVT::i32, SrlY, Const31); |
| Res = DAG.getNode(ISD::OR, DL, MVT::i32, SrlX, SllY); |
| } |
| |
| if (TyX == MVT::f32) |
| return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Res); |
| |
| SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, |
| Op.getOperand(0), |
| DAG.getConstant(0, DL, MVT::i32)); |
| return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res); |
| } |
| |
| static SDValue lowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG, |
| bool HasExtractInsert) { |
| unsigned WidthX = Op.getOperand(0).getValueSizeInBits(); |
| unsigned WidthY = Op.getOperand(1).getValueSizeInBits(); |
| EVT TyX = MVT::getIntegerVT(WidthX), TyY = MVT::getIntegerVT(WidthY); |
| SDLoc DL(Op); |
| SDValue Const1 = DAG.getConstant(1, DL, MVT::i32); |
| |
| // Bitcast to integer nodes. |
| SDValue X = DAG.getNode(ISD::BITCAST, DL, TyX, Op.getOperand(0)); |
| SDValue Y = DAG.getNode(ISD::BITCAST, DL, TyY, Op.getOperand(1)); |
| |
| if (HasExtractInsert) { |
| // ext E, Y, width(Y) - 1, 1 ; extract bit width(Y)-1 of Y |
| // ins X, E, width(X) - 1, 1 ; insert extracted bit at bit width(X)-1 of X |
| SDValue E = DAG.getNode(MipsISD::Ext, DL, TyY, Y, |
| DAG.getConstant(WidthY - 1, DL, MVT::i32), Const1); |
| |
| if (WidthX > WidthY) |
| E = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, E); |
| else if (WidthY > WidthX) |
| E = DAG.getNode(ISD::TRUNCATE, DL, TyX, E); |
| |
| SDValue I = DAG.getNode(MipsISD::Ins, DL, TyX, E, |
| DAG.getConstant(WidthX - 1, DL, MVT::i32), Const1, |
| X); |
| return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), I); |
| } |
| |
| // (d)sll SllX, X, 1 |
| // (d)srl SrlX, SllX, 1 |
| // (d)srl SrlY, Y, width(Y)-1 |
| // (d)sll SllY, SrlX, width(Y)-1 |
| // or Or, SrlX, SllY |
| SDValue SllX = DAG.getNode(ISD::SHL, DL, TyX, X, Const1); |
| SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1); |
| SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y, |
| DAG.getConstant(WidthY - 1, DL, MVT::i32)); |
| |
| if (WidthX > WidthY) |
| SrlY = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, SrlY); |
| else if (WidthY > WidthX) |
| SrlY = DAG.getNode(ISD::TRUNCATE, DL, TyX, SrlY); |
| |
| SDValue SllY = DAG.getNode(ISD::SHL, DL, TyX, SrlY, |
| DAG.getConstant(WidthX - 1, DL, MVT::i32)); |
| SDValue Or = DAG.getNode(ISD::OR, DL, TyX, SrlX, SllY); |
| return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Or); |
| } |
| |
| SDValue |
| MipsTargetLowering::lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const { |
| if (Subtarget.isGP64bit()) |
| return lowerFCOPYSIGN64(Op, DAG, Subtarget.hasExtractInsert()); |
| |
| return lowerFCOPYSIGN32(Op, DAG, Subtarget.hasExtractInsert()); |
| } |
| |
| static SDValue lowerFABS32(SDValue Op, SelectionDAG &DAG, |
| bool HasExtractInsert) { |
| SDLoc DL(Op); |
| SDValue Res, Const1 = DAG.getConstant(1, DL, MVT::i32); |
| |
| // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it |
| // to i32. |
| SDValue X = (Op.getValueType() == MVT::f32) |
| ? DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) |
| : DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, |
| Op.getOperand(0), Const1); |
| |
| // Clear MSB. |
| if (HasExtractInsert) |
| Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, |
| DAG.getRegister(Mips::ZERO, MVT::i32), |
| DAG.getConstant(31, DL, MVT::i32), Const1, X); |
| else { |
| // TODO: Provide DAG patterns which transform (and x, cst) |
| // back to a (shl (srl x (clz cst)) (clz cst)) sequence. |
| SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1); |
| Res = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1); |
| } |
|