| //===----------------------------------------------------------------------===// |
| // |
| // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
| // See https://llvm.org/LICENSE.txt for license information. |
| // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
| // |
| //===----------------------------------------------------------------------===// |
| // Automatically generated file, please consult code owner before editing. |
| //===----------------------------------------------------------------------===// |
| |
| def A2_abs : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32), |
| "$Rd32 = abs($Rs32)", |
| tc_cf8126ae, TypeS_2op>, Enc_5e2823 { |
| let Inst{13-5} = 0b000000100; |
| let Inst{31-21} = 0b10001100100; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let prefersSlot3 = 1; |
| } |
| def A2_absp : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rss32), |
| "$Rdd32 = abs($Rss32)", |
| tc_cf8126ae, TypeS_2op>, Enc_b9c5fb { |
| let Inst{13-5} = 0b000000110; |
| let Inst{31-21} = 0b10000000100; |
| let prefersSlot3 = 1; |
| } |
| def A2_abssat : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32), |
| "$Rd32 = abs($Rs32):sat", |
| tc_cf8126ae, TypeS_2op>, Enc_5e2823 { |
| let Inst{13-5} = 0b000000101; |
| let Inst{31-21} = 0b10001100100; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let prefersSlot3 = 1; |
| let Defs = [USR_OVF]; |
| } |
| def A2_add : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32, IntRegs:$Rt32), |
| "$Rd32 = add($Rs32,$Rt32)", |
| tc_5a2711e5, TypeALU32_3op>, Enc_5ab2be, PredNewRel, ImmRegRel { |
| let Inst{7-5} = 0b000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11110011000; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let CextOpcode = "A2_add"; |
| let InputType = "reg"; |
| let BaseOpcode = "A2_add"; |
| let isCommutable = 1; |
| let isPredicable = 1; |
| } |
| def A2_addh_h16_hh : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rt32, IntRegs:$Rs32), |
| "$Rd32 = add($Rt32.h,$Rs32.h):<<16", |
| tc_679309b8, TypeALU64>, Enc_bd6011 { |
| let Inst{7-5} = 0b011; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010101010; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let prefersSlot3 = 1; |
| } |
| def A2_addh_h16_hl : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rt32, IntRegs:$Rs32), |
| "$Rd32 = add($Rt32.h,$Rs32.l):<<16", |
| tc_679309b8, TypeALU64>, Enc_bd6011 { |
| let Inst{7-5} = 0b010; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010101010; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let prefersSlot3 = 1; |
| } |
| def A2_addh_h16_lh : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rt32, IntRegs:$Rs32), |
| "$Rd32 = add($Rt32.l,$Rs32.h):<<16", |
| tc_679309b8, TypeALU64>, Enc_bd6011 { |
| let Inst{7-5} = 0b001; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010101010; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let prefersSlot3 = 1; |
| } |
| def A2_addh_h16_ll : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rt32, IntRegs:$Rs32), |
| "$Rd32 = add($Rt32.l,$Rs32.l):<<16", |
| tc_679309b8, TypeALU64>, Enc_bd6011 { |
| let Inst{7-5} = 0b000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010101010; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let prefersSlot3 = 1; |
| } |
| def A2_addh_h16_sat_hh : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rt32, IntRegs:$Rs32), |
| "$Rd32 = add($Rt32.h,$Rs32.h):sat:<<16", |
| tc_779080bf, TypeALU64>, Enc_bd6011 { |
| let Inst{7-5} = 0b111; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010101010; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let prefersSlot3 = 1; |
| let Defs = [USR_OVF]; |
| } |
| def A2_addh_h16_sat_hl : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rt32, IntRegs:$Rs32), |
| "$Rd32 = add($Rt32.h,$Rs32.l):sat:<<16", |
| tc_779080bf, TypeALU64>, Enc_bd6011 { |
| let Inst{7-5} = 0b110; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010101010; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let prefersSlot3 = 1; |
| let Defs = [USR_OVF]; |
| } |
| def A2_addh_h16_sat_lh : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rt32, IntRegs:$Rs32), |
| "$Rd32 = add($Rt32.l,$Rs32.h):sat:<<16", |
| tc_779080bf, TypeALU64>, Enc_bd6011 { |
| let Inst{7-5} = 0b101; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010101010; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let prefersSlot3 = 1; |
| let Defs = [USR_OVF]; |
| } |
| def A2_addh_h16_sat_ll : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rt32, IntRegs:$Rs32), |
| "$Rd32 = add($Rt32.l,$Rs32.l):sat:<<16", |
| tc_779080bf, TypeALU64>, Enc_bd6011 { |
| let Inst{7-5} = 0b100; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010101010; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let prefersSlot3 = 1; |
| let Defs = [USR_OVF]; |
| } |
| def A2_addh_l16_hl : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rt32, IntRegs:$Rs32), |
| "$Rd32 = add($Rt32.l,$Rs32.h)", |
| tc_4414d8b1, TypeALU64>, Enc_bd6011 { |
| let Inst{7-5} = 0b010; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010101000; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let prefersSlot3 = 1; |
| } |
| def A2_addh_l16_ll : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rt32, IntRegs:$Rs32), |
| "$Rd32 = add($Rt32.l,$Rs32.l)", |
| tc_4414d8b1, TypeALU64>, Enc_bd6011 { |
| let Inst{7-5} = 0b000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010101000; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let prefersSlot3 = 1; |
| } |
| def A2_addh_l16_sat_hl : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rt32, IntRegs:$Rs32), |
| "$Rd32 = add($Rt32.l,$Rs32.h):sat", |
| tc_779080bf, TypeALU64>, Enc_bd6011 { |
| let Inst{7-5} = 0b110; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010101000; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let prefersSlot3 = 1; |
| let Defs = [USR_OVF]; |
| } |
| def A2_addh_l16_sat_ll : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rt32, IntRegs:$Rs32), |
| "$Rd32 = add($Rt32.l,$Rs32.l):sat", |
| tc_779080bf, TypeALU64>, Enc_bd6011 { |
| let Inst{7-5} = 0b100; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010101000; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let prefersSlot3 = 1; |
| let Defs = [USR_OVF]; |
| } |
| def A2_addi : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32, s32_0Imm:$Ii), |
| "$Rd32 = add($Rs32,#$Ii)", |
| tc_5a2711e5, TypeALU32_ADDI>, Enc_cb9321, PredNewRel, ImmRegRel { |
| let Inst{31-28} = 0b1011; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let CextOpcode = "A2_add"; |
| let InputType = "imm"; |
| let BaseOpcode = "A2_addi"; |
| let isPredicable = 1; |
| let isAdd = 1; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 16; |
| let opExtentAlign = 0; |
| } |
| def A2_addp : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Rdd32 = add($Rss32,$Rtt32)", |
| tc_946df596, TypeALU64>, Enc_a56825 { |
| let Inst{7-5} = 0b111; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011000; |
| let isCommutable = 1; |
| let isAdd = 1; |
| } |
| def A2_addpsat : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Rdd32 = add($Rss32,$Rtt32):sat", |
| tc_779080bf, TypeALU64>, Enc_a56825 { |
| let Inst{7-5} = 0b101; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011011; |
| let prefersSlot3 = 1; |
| let Defs = [USR_OVF]; |
| let isCommutable = 1; |
| } |
| def A2_addsat : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32, IntRegs:$Rt32), |
| "$Rd32 = add($Rs32,$Rt32):sat", |
| tc_61830035, TypeALU32_3op>, Enc_5ab2be { |
| let Inst{7-5} = 0b000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11110110010; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let prefersSlot3 = 1; |
| let Defs = [USR_OVF]; |
| let InputType = "reg"; |
| let isCommutable = 1; |
| } |
| def A2_addsp : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins IntRegs:$Rs32, DoubleRegs:$Rtt32), |
| "$Rdd32 = add($Rs32,$Rtt32)", |
| tc_679309b8, TypeALU64> { |
| let isPseudo = 1; |
| } |
| def A2_addsph : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Rdd32 = add($Rss32,$Rtt32):raw:hi", |
| tc_679309b8, TypeALU64>, Enc_a56825 { |
| let Inst{7-5} = 0b111; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011011; |
| let prefersSlot3 = 1; |
| } |
| def A2_addspl : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Rdd32 = add($Rss32,$Rtt32):raw:lo", |
| tc_679309b8, TypeALU64>, Enc_a56825 { |
| let Inst{7-5} = 0b110; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011011; |
| let prefersSlot3 = 1; |
| } |
| def A2_and : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32, IntRegs:$Rt32), |
| "$Rd32 = and($Rs32,$Rt32)", |
| tc_5a2711e5, TypeALU32_3op>, Enc_5ab2be, PredNewRel, ImmRegRel { |
| let Inst{7-5} = 0b000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11110001000; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let CextOpcode = "A2_and"; |
| let InputType = "reg"; |
| let BaseOpcode = "A2_and"; |
| let isCommutable = 1; |
| let isPredicable = 1; |
| } |
| def A2_andir : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32, s32_0Imm:$Ii), |
| "$Rd32 = and($Rs32,#$Ii)", |
| tc_5a2711e5, TypeALU32_2op>, Enc_140c83, ImmRegRel { |
| let Inst{31-22} = 0b0111011000; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let CextOpcode = "A2_and"; |
| let InputType = "imm"; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 10; |
| let opExtentAlign = 0; |
| } |
| def A2_andp : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Rdd32 = and($Rss32,$Rtt32)", |
| tc_946df596, TypeALU64>, Enc_a56825 { |
| let Inst{7-5} = 0b000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011111; |
| let isCommutable = 1; |
| } |
| def A2_aslh : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32), |
| "$Rd32 = aslh($Rs32)", |
| tc_57890846, TypeALU32_2op>, Enc_5e2823, PredNewRel { |
| let Inst{13-5} = 0b000000000; |
| let Inst{31-21} = 0b01110000000; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let BaseOpcode = "A2_aslh"; |
| let isPredicable = 1; |
| } |
| def A2_asrh : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32), |
| "$Rd32 = asrh($Rs32)", |
| tc_57890846, TypeALU32_2op>, Enc_5e2823, PredNewRel { |
| let Inst{13-5} = 0b000000000; |
| let Inst{31-21} = 0b01110000001; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let BaseOpcode = "A2_asrh"; |
| let isPredicable = 1; |
| } |
| def A2_combine_hh : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rt32, IntRegs:$Rs32), |
| "$Rd32 = combine($Rt32.h,$Rs32.h)", |
| tc_5a2711e5, TypeALU32_3op>, Enc_bd6011 { |
| let Inst{7-5} = 0b000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11110011100; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let InputType = "reg"; |
| } |
| def A2_combine_hl : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rt32, IntRegs:$Rs32), |
| "$Rd32 = combine($Rt32.h,$Rs32.l)", |
| tc_5a2711e5, TypeALU32_3op>, Enc_bd6011 { |
| let Inst{7-5} = 0b000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11110011101; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let InputType = "reg"; |
| } |
| def A2_combine_lh : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rt32, IntRegs:$Rs32), |
| "$Rd32 = combine($Rt32.l,$Rs32.h)", |
| tc_5a2711e5, TypeALU32_3op>, Enc_bd6011 { |
| let Inst{7-5} = 0b000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11110011110; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let InputType = "reg"; |
| } |
| def A2_combine_ll : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rt32, IntRegs:$Rs32), |
| "$Rd32 = combine($Rt32.l,$Rs32.l)", |
| tc_5a2711e5, TypeALU32_3op>, Enc_bd6011 { |
| let Inst{7-5} = 0b000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11110011111; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let InputType = "reg"; |
| } |
| def A2_combineii : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins s32_0Imm:$Ii, s8_0Imm:$II), |
| "$Rdd32 = combine(#$Ii,#$II)", |
| tc_5a2711e5, TypeALU32_2op>, Enc_18c338 { |
| let Inst{31-23} = 0b011111000; |
| let isReMaterializable = 1; |
| let isAsCheapAsAMove = 1; |
| let isMoveImm = 1; |
| let isExtendable = 1; |
| let opExtendable = 1; |
| let isExtentSigned = 1; |
| let opExtentBits = 8; |
| let opExtentAlign = 0; |
| } |
| def A2_combinew : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins IntRegs:$Rs32, IntRegs:$Rt32), |
| "$Rdd32 = combine($Rs32,$Rt32)", |
| tc_5a2711e5, TypeALU32_3op>, Enc_be32a5, PredNewRel { |
| let Inst{7-5} = 0b000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11110101000; |
| let InputType = "reg"; |
| let BaseOpcode = "A2_combinew"; |
| let isPredicable = 1; |
| } |
| def A2_max : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32, IntRegs:$Rt32), |
| "$Rd32 = max($Rs32,$Rt32)", |
| tc_779080bf, TypeALU64>, Enc_5ab2be { |
| let Inst{7-5} = 0b000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010101110; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let prefersSlot3 = 1; |
| } |
| def A2_maxp : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Rdd32 = max($Rss32,$Rtt32)", |
| tc_779080bf, TypeALU64>, Enc_a56825 { |
| let Inst{7-5} = 0b100; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011110; |
| let prefersSlot3 = 1; |
| } |
| def A2_maxu : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32, IntRegs:$Rt32), |
| "$Rd32 = maxu($Rs32,$Rt32)", |
| tc_779080bf, TypeALU64>, Enc_5ab2be { |
| let Inst{7-5} = 0b100; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010101110; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let prefersSlot3 = 1; |
| } |
| def A2_maxup : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Rdd32 = maxu($Rss32,$Rtt32)", |
| tc_779080bf, TypeALU64>, Enc_a56825 { |
| let Inst{7-5} = 0b101; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011110; |
| let prefersSlot3 = 1; |
| } |
| def A2_min : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rt32, IntRegs:$Rs32), |
| "$Rd32 = min($Rt32,$Rs32)", |
| tc_779080bf, TypeALU64>, Enc_bd6011 { |
| let Inst{7-5} = 0b000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010101101; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let prefersSlot3 = 1; |
| } |
| def A2_minp : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), |
| "$Rdd32 = min($Rtt32,$Rss32)", |
| tc_779080bf, TypeALU64>, Enc_ea23e4 { |
| let Inst{7-5} = 0b110; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011101; |
| let prefersSlot3 = 1; |
| } |
| def A2_minu : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rt32, IntRegs:$Rs32), |
| "$Rd32 = minu($Rt32,$Rs32)", |
| tc_779080bf, TypeALU64>, Enc_bd6011 { |
| let Inst{7-5} = 0b100; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010101101; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let prefersSlot3 = 1; |
| } |
| def A2_minup : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), |
| "$Rdd32 = minu($Rtt32,$Rss32)", |
| tc_779080bf, TypeALU64>, Enc_ea23e4 { |
| let Inst{7-5} = 0b111; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011101; |
| let prefersSlot3 = 1; |
| } |
| def A2_neg : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32), |
| "$Rd32 = neg($Rs32)", |
| tc_57890846, TypeALU32_2op> { |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isPseudo = 1; |
| let isCodeGenOnly = 1; |
| } |
| def A2_negp : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rss32), |
| "$Rdd32 = neg($Rss32)", |
| tc_0ae0825c, TypeS_2op>, Enc_b9c5fb { |
| let Inst{13-5} = 0b000000101; |
| let Inst{31-21} = 0b10000000100; |
| } |
| def A2_negsat : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32), |
| "$Rd32 = neg($Rs32):sat", |
| tc_cf8126ae, TypeS_2op>, Enc_5e2823 { |
| let Inst{13-5} = 0b000000110; |
| let Inst{31-21} = 0b10001100100; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let prefersSlot3 = 1; |
| let Defs = [USR_OVF]; |
| } |
| def A2_nop : HInst< |
| (outs), |
| (ins), |
| "nop", |
| tc_2eabeebe, TypeALU32_2op>, Enc_e3b0c4 { |
| let Inst{13-0} = 0b00000000000000; |
| let Inst{31-16} = 0b0111111100000000; |
| } |
| def A2_not : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32), |
| "$Rd32 = not($Rs32)", |
| tc_57890846, TypeALU32_2op> { |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isPseudo = 1; |
| let isCodeGenOnly = 1; |
| } |
| def A2_notp : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rss32), |
| "$Rdd32 = not($Rss32)", |
| tc_0ae0825c, TypeS_2op>, Enc_b9c5fb { |
| let Inst{13-5} = 0b000000100; |
| let Inst{31-21} = 0b10000000100; |
| } |
| def A2_or : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32, IntRegs:$Rt32), |
| "$Rd32 = or($Rs32,$Rt32)", |
| tc_5a2711e5, TypeALU32_3op>, Enc_5ab2be, PredNewRel, ImmRegRel { |
| let Inst{7-5} = 0b000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11110001001; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let CextOpcode = "A2_or"; |
| let InputType = "reg"; |
| let BaseOpcode = "A2_or"; |
| let isCommutable = 1; |
| let isPredicable = 1; |
| } |
| def A2_orir : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32, s32_0Imm:$Ii), |
| "$Rd32 = or($Rs32,#$Ii)", |
| tc_5a2711e5, TypeALU32_2op>, Enc_140c83, ImmRegRel { |
| let Inst{31-22} = 0b0111011010; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let CextOpcode = "A2_or"; |
| let InputType = "imm"; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 10; |
| let opExtentAlign = 0; |
| } |
| def A2_orp : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Rdd32 = or($Rss32,$Rtt32)", |
| tc_946df596, TypeALU64>, Enc_a56825 { |
| let Inst{7-5} = 0b010; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011111; |
| let isCommutable = 1; |
| } |
| def A2_paddf : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), |
| "if (!$Pu4) $Rd32 = add($Rs32,$Rt32)", |
| tc_4c5ba658, TypeALU32_3op>, Enc_ea4c54, PredNewRel, ImmRegRel { |
| let Inst{7-7} = 0b1; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11111011000; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let CextOpcode = "A2_add"; |
| let InputType = "reg"; |
| let BaseOpcode = "A2_add"; |
| } |
| def A2_paddfnew : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), |
| "if (!$Pu4.new) $Rd32 = add($Rs32,$Rt32)", |
| tc_05c070ec, TypeALU32_3op>, Enc_ea4c54, PredNewRel, ImmRegRel { |
| let Inst{7-7} = 0b1; |
| let Inst{13-13} = 0b1; |
| let Inst{31-21} = 0b11111011000; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isPredicatedNew = 1; |
| let CextOpcode = "A2_add"; |
| let InputType = "reg"; |
| let BaseOpcode = "A2_add"; |
| } |
| def A2_paddif : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pu4, IntRegs:$Rs32, s32_0Imm:$Ii), |
| "if (!$Pu4) $Rd32 = add($Rs32,#$Ii)", |
| tc_4c5ba658, TypeALU32_2op>, Enc_e38e1f, PredNewRel, ImmRegRel { |
| let Inst{13-13} = 0b0; |
| let Inst{31-23} = 0b011101001; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let CextOpcode = "A2_add"; |
| let InputType = "imm"; |
| let BaseOpcode = "A2_addi"; |
| let isExtendable = 1; |
| let opExtendable = 3; |
| let isExtentSigned = 1; |
| let opExtentBits = 8; |
| let opExtentAlign = 0; |
| } |
| def A2_paddifnew : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pu4, IntRegs:$Rs32, s32_0Imm:$Ii), |
| "if (!$Pu4.new) $Rd32 = add($Rs32,#$Ii)", |
| tc_05c070ec, TypeALU32_2op>, Enc_e38e1f, PredNewRel, ImmRegRel { |
| let Inst{13-13} = 0b1; |
| let Inst{31-23} = 0b011101001; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isPredicatedNew = 1; |
| let CextOpcode = "A2_add"; |
| let InputType = "imm"; |
| let BaseOpcode = "A2_addi"; |
| let isExtendable = 1; |
| let opExtendable = 3; |
| let isExtentSigned = 1; |
| let opExtentBits = 8; |
| let opExtentAlign = 0; |
| } |
| def A2_paddit : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pu4, IntRegs:$Rs32, s32_0Imm:$Ii), |
| "if ($Pu4) $Rd32 = add($Rs32,#$Ii)", |
| tc_4c5ba658, TypeALU32_2op>, Enc_e38e1f, PredNewRel, ImmRegRel { |
| let Inst{13-13} = 0b0; |
| let Inst{31-23} = 0b011101000; |
| let isPredicated = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let CextOpcode = "A2_add"; |
| let InputType = "imm"; |
| let BaseOpcode = "A2_addi"; |
| let isExtendable = 1; |
| let opExtendable = 3; |
| let isExtentSigned = 1; |
| let opExtentBits = 8; |
| let opExtentAlign = 0; |
| } |
| def A2_padditnew : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pu4, IntRegs:$Rs32, s32_0Imm:$Ii), |
| "if ($Pu4.new) $Rd32 = add($Rs32,#$Ii)", |
| tc_05c070ec, TypeALU32_2op>, Enc_e38e1f, PredNewRel, ImmRegRel { |
| let Inst{13-13} = 0b1; |
| let Inst{31-23} = 0b011101000; |
| let isPredicated = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isPredicatedNew = 1; |
| let CextOpcode = "A2_add"; |
| let InputType = "imm"; |
| let BaseOpcode = "A2_addi"; |
| let isExtendable = 1; |
| let opExtendable = 3; |
| let isExtentSigned = 1; |
| let opExtentBits = 8; |
| let opExtentAlign = 0; |
| } |
| def A2_paddt : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), |
| "if ($Pu4) $Rd32 = add($Rs32,$Rt32)", |
| tc_4c5ba658, TypeALU32_3op>, Enc_ea4c54, PredNewRel, ImmRegRel { |
| let Inst{7-7} = 0b0; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11111011000; |
| let isPredicated = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let CextOpcode = "A2_add"; |
| let InputType = "reg"; |
| let BaseOpcode = "A2_add"; |
| } |
| def A2_paddtnew : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), |
| "if ($Pu4.new) $Rd32 = add($Rs32,$Rt32)", |
| tc_05c070ec, TypeALU32_3op>, Enc_ea4c54, PredNewRel, ImmRegRel { |
| let Inst{7-7} = 0b0; |
| let Inst{13-13} = 0b1; |
| let Inst{31-21} = 0b11111011000; |
| let isPredicated = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isPredicatedNew = 1; |
| let CextOpcode = "A2_add"; |
| let InputType = "reg"; |
| let BaseOpcode = "A2_add"; |
| } |
| def A2_pandf : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), |
| "if (!$Pu4) $Rd32 = and($Rs32,$Rt32)", |
| tc_4c5ba658, TypeALU32_3op>, Enc_ea4c54, PredNewRel { |
| let Inst{7-7} = 0b1; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11111001000; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let BaseOpcode = "A2_and"; |
| } |
| def A2_pandfnew : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), |
| "if (!$Pu4.new) $Rd32 = and($Rs32,$Rt32)", |
| tc_05c070ec, TypeALU32_3op>, Enc_ea4c54, PredNewRel { |
| let Inst{7-7} = 0b1; |
| let Inst{13-13} = 0b1; |
| let Inst{31-21} = 0b11111001000; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isPredicatedNew = 1; |
| let BaseOpcode = "A2_and"; |
| } |
| def A2_pandt : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), |
| "if ($Pu4) $Rd32 = and($Rs32,$Rt32)", |
| tc_4c5ba658, TypeALU32_3op>, Enc_ea4c54, PredNewRel { |
| let Inst{7-7} = 0b0; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11111001000; |
| let isPredicated = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let BaseOpcode = "A2_and"; |
| } |
| def A2_pandtnew : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), |
| "if ($Pu4.new) $Rd32 = and($Rs32,$Rt32)", |
| tc_05c070ec, TypeALU32_3op>, Enc_ea4c54, PredNewRel { |
| let Inst{7-7} = 0b0; |
| let Inst{13-13} = 0b1; |
| let Inst{31-21} = 0b11111001000; |
| let isPredicated = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isPredicatedNew = 1; |
| let BaseOpcode = "A2_and"; |
| } |
| def A2_porf : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), |
| "if (!$Pu4) $Rd32 = or($Rs32,$Rt32)", |
| tc_4c5ba658, TypeALU32_3op>, Enc_ea4c54, PredNewRel { |
| let Inst{7-7} = 0b1; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11111001001; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let BaseOpcode = "A2_or"; |
| } |
| def A2_porfnew : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), |
| "if (!$Pu4.new) $Rd32 = or($Rs32,$Rt32)", |
| tc_05c070ec, TypeALU32_3op>, Enc_ea4c54, PredNewRel { |
| let Inst{7-7} = 0b1; |
| let Inst{13-13} = 0b1; |
| let Inst{31-21} = 0b11111001001; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isPredicatedNew = 1; |
| let BaseOpcode = "A2_or"; |
| } |
| def A2_port : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), |
| "if ($Pu4) $Rd32 = or($Rs32,$Rt32)", |
| tc_4c5ba658, TypeALU32_3op>, Enc_ea4c54, PredNewRel { |
| let Inst{7-7} = 0b0; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11111001001; |
| let isPredicated = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let BaseOpcode = "A2_or"; |
| } |
| def A2_portnew : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), |
| "if ($Pu4.new) $Rd32 = or($Rs32,$Rt32)", |
| tc_05c070ec, TypeALU32_3op>, Enc_ea4c54, PredNewRel { |
| let Inst{7-7} = 0b0; |
| let Inst{13-13} = 0b1; |
| let Inst{31-21} = 0b11111001001; |
| let isPredicated = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isPredicatedNew = 1; |
| let BaseOpcode = "A2_or"; |
| } |
| def A2_psubf : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pu4, IntRegs:$Rt32, IntRegs:$Rs32), |
| "if (!$Pu4) $Rd32 = sub($Rt32,$Rs32)", |
| tc_4c5ba658, TypeALU32_3op>, Enc_9b0bc1, PredNewRel { |
| let Inst{7-7} = 0b1; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11111011001; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let BaseOpcode = "A2_sub"; |
| } |
| def A2_psubfnew : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pu4, IntRegs:$Rt32, IntRegs:$Rs32), |
| "if (!$Pu4.new) $Rd32 = sub($Rt32,$Rs32)", |
| tc_05c070ec, TypeALU32_3op>, Enc_9b0bc1, PredNewRel { |
| let Inst{7-7} = 0b1; |
| let Inst{13-13} = 0b1; |
| let Inst{31-21} = 0b11111011001; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isPredicatedNew = 1; |
| let BaseOpcode = "A2_sub"; |
| } |
| def A2_psubt : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pu4, IntRegs:$Rt32, IntRegs:$Rs32), |
| "if ($Pu4) $Rd32 = sub($Rt32,$Rs32)", |
| tc_4c5ba658, TypeALU32_3op>, Enc_9b0bc1, PredNewRel { |
| let Inst{7-7} = 0b0; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11111011001; |
| let isPredicated = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let BaseOpcode = "A2_sub"; |
| } |
| def A2_psubtnew : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pu4, IntRegs:$Rt32, IntRegs:$Rs32), |
| "if ($Pu4.new) $Rd32 = sub($Rt32,$Rs32)", |
| tc_05c070ec, TypeALU32_3op>, Enc_9b0bc1, PredNewRel { |
| let Inst{7-7} = 0b0; |
| let Inst{13-13} = 0b1; |
| let Inst{31-21} = 0b11111011001; |
| let isPredicated = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isPredicatedNew = 1; |
| let BaseOpcode = "A2_sub"; |
| } |
| def A2_pxorf : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), |
| "if (!$Pu4) $Rd32 = xor($Rs32,$Rt32)", |
| tc_4c5ba658, TypeALU32_3op>, Enc_ea4c54, PredNewRel { |
| let Inst{7-7} = 0b1; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11111001011; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let BaseOpcode = "A2_xor"; |
| } |
| def A2_pxorfnew : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), |
| "if (!$Pu4.new) $Rd32 = xor($Rs32,$Rt32)", |
| tc_05c070ec, TypeALU32_3op>, Enc_ea4c54, PredNewRel { |
| let Inst{7-7} = 0b1; |
| let Inst{13-13} = 0b1; |
| let Inst{31-21} = 0b11111001011; |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isPredicatedNew = 1; |
| let BaseOpcode = "A2_xor"; |
| } |
| def A2_pxort : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), |
| "if ($Pu4) $Rd32 = xor($Rs32,$Rt32)", |
| tc_4c5ba658, TypeALU32_3op>, Enc_ea4c54, PredNewRel { |
| let Inst{7-7} = 0b0; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11111001011; |
| let isPredicated = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let BaseOpcode = "A2_xor"; |
| } |
| def A2_pxortnew : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pu4, IntRegs:$Rs32, IntRegs:$Rt32), |
| "if ($Pu4.new) $Rd32 = xor($Rs32,$Rt32)", |
| tc_05c070ec, TypeALU32_3op>, Enc_ea4c54, PredNewRel { |
| let Inst{7-7} = 0b0; |
| let Inst{13-13} = 0b1; |
| let Inst{31-21} = 0b11111001011; |
| let isPredicated = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isPredicatedNew = 1; |
| let BaseOpcode = "A2_xor"; |
| } |
| def A2_roundsat : HInst< |
| (outs IntRegs:$Rd32), |
| (ins DoubleRegs:$Rss32), |
| "$Rd32 = round($Rss32):sat", |
| tc_cf8126ae, TypeS_2op>, Enc_90cd8b { |
| let Inst{13-5} = 0b000000001; |
| let Inst{31-21} = 0b10001000110; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let prefersSlot3 = 1; |
| let Defs = [USR_OVF]; |
| } |
| def A2_sat : HInst< |
| (outs IntRegs:$Rd32), |
| (ins DoubleRegs:$Rss32), |
| "$Rd32 = sat($Rss32)", |
| tc_0ae0825c, TypeS_2op>, Enc_90cd8b { |
| let Inst{13-5} = 0b000000000; |
| let Inst{31-21} = 0b10001000110; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let Defs = [USR_OVF]; |
| } |
| def A2_satb : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32), |
| "$Rd32 = satb($Rs32)", |
| tc_0ae0825c, TypeS_2op>, Enc_5e2823 { |
| let Inst{13-5} = 0b000000111; |
| let Inst{31-21} = 0b10001100110; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let Defs = [USR_OVF]; |
| } |
| def A2_sath : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32), |
| "$Rd32 = sath($Rs32)", |
| tc_0ae0825c, TypeS_2op>, Enc_5e2823 { |
| let Inst{13-5} = 0b000000100; |
| let Inst{31-21} = 0b10001100110; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let Defs = [USR_OVF]; |
| } |
| def A2_satub : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32), |
| "$Rd32 = satub($Rs32)", |
| tc_0ae0825c, TypeS_2op>, Enc_5e2823 { |
| let Inst{13-5} = 0b000000110; |
| let Inst{31-21} = 0b10001100110; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let Defs = [USR_OVF]; |
| } |
| def A2_satuh : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32), |
| "$Rd32 = satuh($Rs32)", |
| tc_0ae0825c, TypeS_2op>, Enc_5e2823 { |
| let Inst{13-5} = 0b000000101; |
| let Inst{31-21} = 0b10001100110; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let Defs = [USR_OVF]; |
| } |
| def A2_sub : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rt32, IntRegs:$Rs32), |
| "$Rd32 = sub($Rt32,$Rs32)", |
| tc_5a2711e5, TypeALU32_3op>, Enc_bd6011, PredNewRel, ImmRegRel { |
| let Inst{7-5} = 0b000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11110011001; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let CextOpcode = "A2_sub"; |
| let InputType = "reg"; |
| let BaseOpcode = "A2_sub"; |
| let isPredicable = 1; |
| } |
| def A2_subh_h16_hh : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rt32, IntRegs:$Rs32), |
| "$Rd32 = sub($Rt32.h,$Rs32.h):<<16", |
| tc_679309b8, TypeALU64>, Enc_bd6011 { |
| let Inst{7-5} = 0b011; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010101011; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let prefersSlot3 = 1; |
| } |
| def A2_subh_h16_hl : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rt32, IntRegs:$Rs32), |
| "$Rd32 = sub($Rt32.h,$Rs32.l):<<16", |
| tc_679309b8, TypeALU64>, Enc_bd6011 { |
| let Inst{7-5} = 0b010; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010101011; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let prefersSlot3 = 1; |
| } |
| def A2_subh_h16_lh : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rt32, IntRegs:$Rs32), |
| "$Rd32 = sub($Rt32.l,$Rs32.h):<<16", |
| tc_679309b8, TypeALU64>, Enc_bd6011 { |
| let Inst{7-5} = 0b001; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010101011; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let prefersSlot3 = 1; |
| } |
| def A2_subh_h16_ll : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rt32, IntRegs:$Rs32), |
| "$Rd32 = sub($Rt32.l,$Rs32.l):<<16", |
| tc_679309b8, TypeALU64>, Enc_bd6011 { |
| let Inst{7-5} = 0b000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010101011; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let prefersSlot3 = 1; |
| } |
| def A2_subh_h16_sat_hh : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rt32, IntRegs:$Rs32), |
| "$Rd32 = sub($Rt32.h,$Rs32.h):sat:<<16", |
| tc_779080bf, TypeALU64>, Enc_bd6011 { |
| let Inst{7-5} = 0b111; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010101011; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let prefersSlot3 = 1; |
| let Defs = [USR_OVF]; |
| } |
| def A2_subh_h16_sat_hl : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rt32, IntRegs:$Rs32), |
| "$Rd32 = sub($Rt32.h,$Rs32.l):sat:<<16", |
| tc_779080bf, TypeALU64>, Enc_bd6011 { |
| let Inst{7-5} = 0b110; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010101011; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let prefersSlot3 = 1; |
| let Defs = [USR_OVF]; |
| } |
| def A2_subh_h16_sat_lh : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rt32, IntRegs:$Rs32), |
| "$Rd32 = sub($Rt32.l,$Rs32.h):sat:<<16", |
| tc_779080bf, TypeALU64>, Enc_bd6011 { |
| let Inst{7-5} = 0b101; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010101011; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let prefersSlot3 = 1; |
| let Defs = [USR_OVF]; |
| } |
| def A2_subh_h16_sat_ll : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rt32, IntRegs:$Rs32), |
| "$Rd32 = sub($Rt32.l,$Rs32.l):sat:<<16", |
| tc_779080bf, TypeALU64>, Enc_bd6011 { |
| let Inst{7-5} = 0b100; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010101011; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let prefersSlot3 = 1; |
| let Defs = [USR_OVF]; |
| } |
| def A2_subh_l16_hl : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rt32, IntRegs:$Rs32), |
| "$Rd32 = sub($Rt32.l,$Rs32.h)", |
| tc_4414d8b1, TypeALU64>, Enc_bd6011 { |
| let Inst{7-5} = 0b010; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010101001; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let prefersSlot3 = 1; |
| } |
| def A2_subh_l16_ll : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rt32, IntRegs:$Rs32), |
| "$Rd32 = sub($Rt32.l,$Rs32.l)", |
| tc_4414d8b1, TypeALU64>, Enc_bd6011 { |
| let Inst{7-5} = 0b000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010101001; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let prefersSlot3 = 1; |
| } |
| def A2_subh_l16_sat_hl : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rt32, IntRegs:$Rs32), |
| "$Rd32 = sub($Rt32.l,$Rs32.h):sat", |
| tc_779080bf, TypeALU64>, Enc_bd6011 { |
| let Inst{7-5} = 0b110; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010101001; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let prefersSlot3 = 1; |
| let Defs = [USR_OVF]; |
| } |
| def A2_subh_l16_sat_ll : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rt32, IntRegs:$Rs32), |
| "$Rd32 = sub($Rt32.l,$Rs32.l):sat", |
| tc_779080bf, TypeALU64>, Enc_bd6011 { |
| let Inst{7-5} = 0b100; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010101001; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let prefersSlot3 = 1; |
| let Defs = [USR_OVF]; |
| } |
| def A2_subp : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), |
| "$Rdd32 = sub($Rtt32,$Rss32)", |
| tc_946df596, TypeALU64>, Enc_ea23e4 { |
| let Inst{7-5} = 0b111; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011001; |
| } |
| def A2_subri : HInst< |
| (outs IntRegs:$Rd32), |
| (ins s32_0Imm:$Ii, IntRegs:$Rs32), |
| "$Rd32 = sub(#$Ii,$Rs32)", |
| tc_5a2711e5, TypeALU32_2op>, Enc_140c83, PredNewRel, ImmRegRel { |
| let Inst{31-22} = 0b0111011001; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let CextOpcode = "A2_sub"; |
| let InputType = "imm"; |
| let isExtendable = 1; |
| let opExtendable = 1; |
| let isExtentSigned = 1; |
| let opExtentBits = 10; |
| let opExtentAlign = 0; |
| } |
| def A2_subsat : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rt32, IntRegs:$Rs32), |
| "$Rd32 = sub($Rt32,$Rs32):sat", |
| tc_61830035, TypeALU32_3op>, Enc_bd6011 { |
| let Inst{7-5} = 0b000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11110110110; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let prefersSlot3 = 1; |
| let Defs = [USR_OVF]; |
| let InputType = "reg"; |
| } |
| def A2_svaddh : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32, IntRegs:$Rt32), |
| "$Rd32 = vaddh($Rs32,$Rt32)", |
| tc_5a2711e5, TypeALU32_3op>, Enc_5ab2be { |
| let Inst{7-5} = 0b000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11110110000; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let InputType = "reg"; |
| let isCommutable = 1; |
| } |
| def A2_svaddhs : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32, IntRegs:$Rt32), |
| "$Rd32 = vaddh($Rs32,$Rt32):sat", |
| tc_61830035, TypeALU32_3op>, Enc_5ab2be { |
| let Inst{7-5} = 0b000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11110110001; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let prefersSlot3 = 1; |
| let Defs = [USR_OVF]; |
| let InputType = "reg"; |
| let isCommutable = 1; |
| } |
| def A2_svadduhs : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32, IntRegs:$Rt32), |
| "$Rd32 = vadduh($Rs32,$Rt32):sat", |
| tc_61830035, TypeALU32_3op>, Enc_5ab2be { |
| let Inst{7-5} = 0b000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11110110011; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let prefersSlot3 = 1; |
| let Defs = [USR_OVF]; |
| let InputType = "reg"; |
| let isCommutable = 1; |
| } |
| def A2_svavgh : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32, IntRegs:$Rt32), |
| "$Rd32 = vavgh($Rs32,$Rt32)", |
| tc_1c80410a, TypeALU32_3op>, Enc_5ab2be { |
| let Inst{7-5} = 0b000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11110111000; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let prefersSlot3 = 1; |
| let InputType = "reg"; |
| let isCommutable = 1; |
| } |
| def A2_svavghs : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32, IntRegs:$Rt32), |
| "$Rd32 = vavgh($Rs32,$Rt32):rnd", |
| tc_d08ee0f4, TypeALU32_3op>, Enc_5ab2be { |
| let Inst{7-5} = 0b000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11110111001; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let prefersSlot3 = 1; |
| let InputType = "reg"; |
| let isCommutable = 1; |
| } |
| def A2_svnavgh : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rt32, IntRegs:$Rs32), |
| "$Rd32 = vnavgh($Rt32,$Rs32)", |
| tc_1c80410a, TypeALU32_3op>, Enc_bd6011 { |
| let Inst{7-5} = 0b000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11110111011; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let prefersSlot3 = 1; |
| let InputType = "reg"; |
| } |
| def A2_svsubh : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rt32, IntRegs:$Rs32), |
| "$Rd32 = vsubh($Rt32,$Rs32)", |
| tc_5a2711e5, TypeALU32_3op>, Enc_bd6011 { |
| let Inst{7-5} = 0b000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11110110100; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let InputType = "reg"; |
| } |
| def A2_svsubhs : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rt32, IntRegs:$Rs32), |
| "$Rd32 = vsubh($Rt32,$Rs32):sat", |
| tc_61830035, TypeALU32_3op>, Enc_bd6011 { |
| let Inst{7-5} = 0b000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11110110101; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let prefersSlot3 = 1; |
| let Defs = [USR_OVF]; |
| let InputType = "reg"; |
| } |
| def A2_svsubuhs : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rt32, IntRegs:$Rs32), |
| "$Rd32 = vsubuh($Rt32,$Rs32):sat", |
| tc_61830035, TypeALU32_3op>, Enc_bd6011 { |
| let Inst{7-5} = 0b000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11110110111; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let prefersSlot3 = 1; |
| let Defs = [USR_OVF]; |
| let InputType = "reg"; |
| } |
| def A2_swiz : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32), |
| "$Rd32 = swiz($Rs32)", |
| tc_0ae0825c, TypeS_2op>, Enc_5e2823 { |
| let Inst{13-5} = 0b000000111; |
| let Inst{31-21} = 0b10001100100; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| } |
| def A2_sxtb : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32), |
| "$Rd32 = sxtb($Rs32)", |
| tc_57890846, TypeALU32_2op>, Enc_5e2823, PredNewRel { |
| let Inst{13-5} = 0b000000000; |
| let Inst{31-21} = 0b01110000101; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let BaseOpcode = "A2_sxtb"; |
| let isPredicable = 1; |
| } |
| def A2_sxth : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32), |
| "$Rd32 = sxth($Rs32)", |
| tc_57890846, TypeALU32_2op>, Enc_5e2823, PredNewRel { |
| let Inst{13-5} = 0b000000000; |
| let Inst{31-21} = 0b01110000111; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let BaseOpcode = "A2_sxth"; |
| let isPredicable = 1; |
| } |
| def A2_sxtw : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins IntRegs:$Rs32), |
| "$Rdd32 = sxtw($Rs32)", |
| tc_0ae0825c, TypeS_2op>, Enc_3a3d62 { |
| let Inst{13-5} = 0b000000000; |
| let Inst{31-21} = 0b10000100010; |
| } |
| def A2_tfr : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32), |
| "$Rd32 = $Rs32", |
| tc_57890846, TypeALU32_2op>, Enc_5e2823, PredNewRel { |
| let Inst{13-5} = 0b000000000; |
| let Inst{31-21} = 0b01110000011; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let InputType = "reg"; |
| let BaseOpcode = "A2_tfr"; |
| let isPredicable = 1; |
| } |
| def A2_tfrcrr : HInst< |
| (outs IntRegs:$Rd32), |
| (ins CtrRegs:$Cs32), |
| "$Rd32 = $Cs32", |
| tc_b9272d6c, TypeCR>, Enc_0cb018 { |
| let Inst{13-5} = 0b000000000; |
| let Inst{31-21} = 0b01101010000; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| } |
| def A2_tfrf : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pu4, IntRegs:$Rs32), |
| "if (!$Pu4) $Rd32 = $Rs32", |
| tc_4c5ba658, TypeALU32_2op>, PredNewRel, ImmRegRel { |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let CextOpcode = "A2_tfr"; |
| let InputType = "reg"; |
| let BaseOpcode = "A2_tfr"; |
| let isPseudo = 1; |
| let isCodeGenOnly = 1; |
| } |
| def A2_tfrfnew : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pu4, IntRegs:$Rs32), |
| "if (!$Pu4.new) $Rd32 = $Rs32", |
| tc_05c070ec, TypeALU32_2op>, PredNewRel, ImmRegRel { |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isPredicatedNew = 1; |
| let CextOpcode = "A2_tfr"; |
| let InputType = "reg"; |
| let BaseOpcode = "A2_tfr"; |
| let isPseudo = 1; |
| let isCodeGenOnly = 1; |
| } |
| def A2_tfrih : HInst< |
| (outs IntRegs:$Rx32), |
| (ins IntRegs:$Rx32in, u16_0Imm:$Ii), |
| "$Rx32.h = #$Ii", |
| tc_5a2711e5, TypeALU32_2op>, Enc_51436c { |
| let Inst{21-21} = 0b1; |
| let Inst{31-24} = 0b01110010; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let Constraints = "$Rx32 = $Rx32in"; |
| } |
| def A2_tfril : HInst< |
| (outs IntRegs:$Rx32), |
| (ins IntRegs:$Rx32in, u16_0Imm:$Ii), |
| "$Rx32.l = #$Ii", |
| tc_5a2711e5, TypeALU32_2op>, Enc_51436c { |
| let Inst{21-21} = 0b1; |
| let Inst{31-24} = 0b01110001; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let Constraints = "$Rx32 = $Rx32in"; |
| } |
| def A2_tfrp : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rss32), |
| "$Rdd32 = $Rss32", |
| tc_5a2711e5, TypeALU32_2op>, PredNewRel { |
| let BaseOpcode = "A2_tfrp"; |
| let isPredicable = 1; |
| let isPseudo = 1; |
| } |
| def A2_tfrpf : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins PredRegs:$Pu4, DoubleRegs:$Rss32), |
| "if (!$Pu4) $Rdd32 = $Rss32", |
| tc_5a2711e5, TypeALU32_2op>, PredNewRel { |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let BaseOpcode = "A2_tfrp"; |
| let isPseudo = 1; |
| } |
| def A2_tfrpfnew : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins PredRegs:$Pu4, DoubleRegs:$Rss32), |
| "if (!$Pu4.new) $Rdd32 = $Rss32", |
| tc_1ae57e39, TypeALU32_2op>, PredNewRel { |
| let isPredicated = 1; |
| let isPredicatedFalse = 1; |
| let isPredicatedNew = 1; |
| let BaseOpcode = "A2_tfrp"; |
| let isPseudo = 1; |
| } |
| def A2_tfrpi : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins s8_0Imm:$Ii), |
| "$Rdd32 = #$Ii", |
| tc_5a2711e5, TypeALU64> { |
| let isReMaterializable = 1; |
| let isAsCheapAsAMove = 1; |
| let isMoveImm = 1; |
| let isPseudo = 1; |
| } |
| def A2_tfrpt : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins PredRegs:$Pu4, DoubleRegs:$Rss32), |
| "if ($Pu4) $Rdd32 = $Rss32", |
| tc_5a2711e5, TypeALU32_2op>, PredNewRel { |
| let isPredicated = 1; |
| let BaseOpcode = "A2_tfrp"; |
| let isPseudo = 1; |
| } |
| def A2_tfrptnew : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins PredRegs:$Pu4, DoubleRegs:$Rss32), |
| "if ($Pu4.new) $Rdd32 = $Rss32", |
| tc_1ae57e39, TypeALU32_2op>, PredNewRel { |
| let isPredicated = 1; |
| let isPredicatedNew = 1; |
| let BaseOpcode = "A2_tfrp"; |
| let isPseudo = 1; |
| } |
| def A2_tfrrcr : HInst< |
| (outs CtrRegs:$Cd32), |
| (ins IntRegs:$Rs32), |
| "$Cd32 = $Rs32", |
| tc_434c8e1e, TypeCR>, Enc_bd811a { |
| let Inst{13-5} = 0b000000000; |
| let Inst{31-21} = 0b01100010001; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| } |
| def A2_tfrsi : HInst< |
| (outs IntRegs:$Rd32), |
| (ins s32_0Imm:$Ii), |
| "$Rd32 = #$Ii", |
| tc_57890846, TypeALU32_2op>, Enc_5e87ce, PredNewRel, ImmRegRel { |
| let Inst{21-21} = 0b0; |
| let Inst{31-24} = 0b01111000; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let CextOpcode = "A2_tfr"; |
| let InputType = "imm"; |
| let BaseOpcode = "A2_tfrsi"; |
| let isPredicable = 1; |
| let isReMaterializable = 1; |
| let isAsCheapAsAMove = 1; |
| let isMoveImm = 1; |
| let isExtendable = 1; |
| let opExtendable = 1; |
| let isExtentSigned = 1; |
| let opExtentBits = 16; |
| let opExtentAlign = 0; |
| } |
| def A2_tfrt : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pu4, IntRegs:$Rs32), |
| "if ($Pu4) $Rd32 = $Rs32", |
| tc_4c5ba658, TypeALU32_2op>, PredNewRel, ImmRegRel { |
| let isPredicated = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let CextOpcode = "A2_tfr"; |
| let InputType = "reg"; |
| let BaseOpcode = "A2_tfr"; |
| let isPseudo = 1; |
| let isCodeGenOnly = 1; |
| } |
| def A2_tfrtnew : HInst< |
| (outs IntRegs:$Rd32), |
| (ins PredRegs:$Pu4, IntRegs:$Rs32), |
| "if ($Pu4.new) $Rd32 = $Rs32", |
| tc_05c070ec, TypeALU32_2op>, PredNewRel, ImmRegRel { |
| let isPredicated = 1; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let isPredicatedNew = 1; |
| let CextOpcode = "A2_tfr"; |
| let InputType = "reg"; |
| let BaseOpcode = "A2_tfr"; |
| let isPseudo = 1; |
| let isCodeGenOnly = 1; |
| } |
| def A2_vabsh : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rss32), |
| "$Rdd32 = vabsh($Rss32)", |
| tc_cf8126ae, TypeS_2op>, Enc_b9c5fb { |
| let Inst{13-5} = 0b000000100; |
| let Inst{31-21} = 0b10000000010; |
| let prefersSlot3 = 1; |
| } |
| def A2_vabshsat : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rss32), |
| "$Rdd32 = vabsh($Rss32):sat", |
| tc_cf8126ae, TypeS_2op>, Enc_b9c5fb { |
| let Inst{13-5} = 0b000000101; |
| let Inst{31-21} = 0b10000000010; |
| let prefersSlot3 = 1; |
| let Defs = [USR_OVF]; |
| } |
| def A2_vabsw : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rss32), |
| "$Rdd32 = vabsw($Rss32)", |
| tc_cf8126ae, TypeS_2op>, Enc_b9c5fb { |
| let Inst{13-5} = 0b000000110; |
| let Inst{31-21} = 0b10000000010; |
| let prefersSlot3 = 1; |
| } |
| def A2_vabswsat : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rss32), |
| "$Rdd32 = vabsw($Rss32):sat", |
| tc_cf8126ae, TypeS_2op>, Enc_b9c5fb { |
| let Inst{13-5} = 0b000000111; |
| let Inst{31-21} = 0b10000000010; |
| let prefersSlot3 = 1; |
| let Defs = [USR_OVF]; |
| } |
| def A2_vaddb_map : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Rdd32 = vaddb($Rss32,$Rtt32)", |
| tc_946df596, TypeMAPPING> { |
| let isPseudo = 1; |
| let isCodeGenOnly = 1; |
| } |
| def A2_vaddh : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Rdd32 = vaddh($Rss32,$Rtt32)", |
| tc_946df596, TypeALU64>, Enc_a56825 { |
| let Inst{7-5} = 0b010; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011000; |
| } |
| def A2_vaddhs : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Rdd32 = vaddh($Rss32,$Rtt32):sat", |
| tc_779080bf, TypeALU64>, Enc_a56825 { |
| let Inst{7-5} = 0b011; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011000; |
| let prefersSlot3 = 1; |
| let Defs = [USR_OVF]; |
| } |
| def A2_vaddub : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Rdd32 = vaddub($Rss32,$Rtt32)", |
| tc_946df596, TypeALU64>, Enc_a56825 { |
| let Inst{7-5} = 0b000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011000; |
| } |
| def A2_vaddubs : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Rdd32 = vaddub($Rss32,$Rtt32):sat", |
| tc_779080bf, TypeALU64>, Enc_a56825 { |
| let Inst{7-5} = 0b001; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011000; |
| let prefersSlot3 = 1; |
| let Defs = [USR_OVF]; |
| } |
| def A2_vadduhs : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Rdd32 = vadduh($Rss32,$Rtt32):sat", |
| tc_779080bf, TypeALU64>, Enc_a56825 { |
| let Inst{7-5} = 0b100; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011000; |
| let prefersSlot3 = 1; |
| let Defs = [USR_OVF]; |
| } |
| def A2_vaddw : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Rdd32 = vaddw($Rss32,$Rtt32)", |
| tc_946df596, TypeALU64>, Enc_a56825 { |
| let Inst{7-5} = 0b101; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011000; |
| } |
| def A2_vaddws : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Rdd32 = vaddw($Rss32,$Rtt32):sat", |
| tc_779080bf, TypeALU64>, Enc_a56825 { |
| let Inst{7-5} = 0b110; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011000; |
| let prefersSlot3 = 1; |
| let Defs = [USR_OVF]; |
| } |
| def A2_vavgh : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Rdd32 = vavgh($Rss32,$Rtt32)", |
| tc_6132ba3d, TypeALU64>, Enc_a56825 { |
| let Inst{7-5} = 0b010; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011010; |
| let prefersSlot3 = 1; |
| } |
| def A2_vavghcr : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Rdd32 = vavgh($Rss32,$Rtt32):crnd", |
| tc_002cb246, TypeALU64>, Enc_a56825 { |
| let Inst{7-5} = 0b100; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011010; |
| let prefersSlot3 = 1; |
| } |
| def A2_vavghr : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Rdd32 = vavgh($Rss32,$Rtt32):rnd", |
| tc_e4a7f9f0, TypeALU64>, Enc_a56825 { |
| let Inst{7-5} = 0b011; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011010; |
| let prefersSlot3 = 1; |
| } |
| def A2_vavgub : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Rdd32 = vavgub($Rss32,$Rtt32)", |
| tc_6132ba3d, TypeALU64>, Enc_a56825 { |
| let Inst{7-5} = 0b000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011010; |
| let prefersSlot3 = 1; |
| } |
| def A2_vavgubr : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Rdd32 = vavgub($Rss32,$Rtt32):rnd", |
| tc_e4a7f9f0, TypeALU64>, Enc_a56825 { |
| let Inst{7-5} = 0b001; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011010; |
| let prefersSlot3 = 1; |
| } |
| def A2_vavguh : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Rdd32 = vavguh($Rss32,$Rtt32)", |
| tc_6132ba3d, TypeALU64>, Enc_a56825 { |
| let Inst{7-5} = 0b101; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011010; |
| let prefersSlot3 = 1; |
| } |
| def A2_vavguhr : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Rdd32 = vavguh($Rss32,$Rtt32):rnd", |
| tc_e4a7f9f0, TypeALU64>, Enc_a56825 { |
| let Inst{7-5} = 0b110; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011010; |
| let prefersSlot3 = 1; |
| } |
| def A2_vavguw : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Rdd32 = vavguw($Rss32,$Rtt32)", |
| tc_6132ba3d, TypeALU64>, Enc_a56825 { |
| let Inst{7-5} = 0b011; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011011; |
| let prefersSlot3 = 1; |
| } |
| def A2_vavguwr : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Rdd32 = vavguw($Rss32,$Rtt32):rnd", |
| tc_e4a7f9f0, TypeALU64>, Enc_a56825 { |
| let Inst{7-5} = 0b100; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011011; |
| let prefersSlot3 = 1; |
| } |
| def A2_vavgw : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Rdd32 = vavgw($Rss32,$Rtt32)", |
| tc_6132ba3d, TypeALU64>, Enc_a56825 { |
| let Inst{7-5} = 0b000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011011; |
| let prefersSlot3 = 1; |
| } |
| def A2_vavgwcr : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Rdd32 = vavgw($Rss32,$Rtt32):crnd", |
| tc_002cb246, TypeALU64>, Enc_a56825 { |
| let Inst{7-5} = 0b010; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011011; |
| let prefersSlot3 = 1; |
| } |
| def A2_vavgwr : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Rdd32 = vavgw($Rss32,$Rtt32):rnd", |
| tc_e4a7f9f0, TypeALU64>, Enc_a56825 { |
| let Inst{7-5} = 0b001; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011011; |
| let prefersSlot3 = 1; |
| } |
| def A2_vcmpbeq : HInst< |
| (outs PredRegs:$Pd4), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Pd4 = vcmpb.eq($Rss32,$Rtt32)", |
| tc_85d5d03f, TypeALU64>, Enc_fcf7a7 { |
| let Inst{7-2} = 0b110000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010010000; |
| } |
| def A2_vcmpbgtu : HInst< |
| (outs PredRegs:$Pd4), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Pd4 = vcmpb.gtu($Rss32,$Rtt32)", |
| tc_85d5d03f, TypeALU64>, Enc_fcf7a7 { |
| let Inst{7-2} = 0b111000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010010000; |
| } |
| def A2_vcmpheq : HInst< |
| (outs PredRegs:$Pd4), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Pd4 = vcmph.eq($Rss32,$Rtt32)", |
| tc_85d5d03f, TypeALU64>, Enc_fcf7a7 { |
| let Inst{7-2} = 0b011000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010010000; |
| } |
| def A2_vcmphgt : HInst< |
| (outs PredRegs:$Pd4), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Pd4 = vcmph.gt($Rss32,$Rtt32)", |
| tc_85d5d03f, TypeALU64>, Enc_fcf7a7 { |
| let Inst{7-2} = 0b100000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010010000; |
| } |
| def A2_vcmphgtu : HInst< |
| (outs PredRegs:$Pd4), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Pd4 = vcmph.gtu($Rss32,$Rtt32)", |
| tc_85d5d03f, TypeALU64>, Enc_fcf7a7 { |
| let Inst{7-2} = 0b101000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010010000; |
| } |
| def A2_vcmpweq : HInst< |
| (outs PredRegs:$Pd4), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Pd4 = vcmpw.eq($Rss32,$Rtt32)", |
| tc_85d5d03f, TypeALU64>, Enc_fcf7a7 { |
| let Inst{7-2} = 0b000000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010010000; |
| } |
| def A2_vcmpwgt : HInst< |
| (outs PredRegs:$Pd4), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Pd4 = vcmpw.gt($Rss32,$Rtt32)", |
| tc_85d5d03f, TypeALU64>, Enc_fcf7a7 { |
| let Inst{7-2} = 0b001000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010010000; |
| } |
| def A2_vcmpwgtu : HInst< |
| (outs PredRegs:$Pd4), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Pd4 = vcmpw.gtu($Rss32,$Rtt32)", |
| tc_85d5d03f, TypeALU64>, Enc_fcf7a7 { |
| let Inst{7-2} = 0b010000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010010000; |
| } |
| def A2_vconj : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rss32), |
| "$Rdd32 = vconj($Rss32):sat", |
| tc_cf8126ae, TypeS_2op>, Enc_b9c5fb { |
| let Inst{13-5} = 0b000000111; |
| let Inst{31-21} = 0b10000000100; |
| let prefersSlot3 = 1; |
| let Defs = [USR_OVF]; |
| } |
| def A2_vmaxb : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), |
| "$Rdd32 = vmaxb($Rtt32,$Rss32)", |
| tc_779080bf, TypeALU64>, Enc_ea23e4 { |
| let Inst{7-5} = 0b110; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011110; |
| let prefersSlot3 = 1; |
| } |
| def A2_vmaxh : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), |
| "$Rdd32 = vmaxh($Rtt32,$Rss32)", |
| tc_779080bf, TypeALU64>, Enc_ea23e4 { |
| let Inst{7-5} = 0b001; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011110; |
| let prefersSlot3 = 1; |
| } |
| def A2_vmaxub : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), |
| "$Rdd32 = vmaxub($Rtt32,$Rss32)", |
| tc_779080bf, TypeALU64>, Enc_ea23e4 { |
| let Inst{7-5} = 0b000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011110; |
| let prefersSlot3 = 1; |
| } |
| def A2_vmaxuh : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), |
| "$Rdd32 = vmaxuh($Rtt32,$Rss32)", |
| tc_779080bf, TypeALU64>, Enc_ea23e4 { |
| let Inst{7-5} = 0b010; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011110; |
| let prefersSlot3 = 1; |
| } |
| def A2_vmaxuw : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), |
| "$Rdd32 = vmaxuw($Rtt32,$Rss32)", |
| tc_779080bf, TypeALU64>, Enc_ea23e4 { |
| let Inst{7-5} = 0b101; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011101; |
| let prefersSlot3 = 1; |
| } |
| def A2_vmaxw : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), |
| "$Rdd32 = vmaxw($Rtt32,$Rss32)", |
| tc_779080bf, TypeALU64>, Enc_ea23e4 { |
| let Inst{7-5} = 0b011; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011110; |
| let prefersSlot3 = 1; |
| } |
| def A2_vminb : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), |
| "$Rdd32 = vminb($Rtt32,$Rss32)", |
| tc_779080bf, TypeALU64>, Enc_ea23e4 { |
| let Inst{7-5} = 0b111; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011110; |
| let prefersSlot3 = 1; |
| } |
| def A2_vminh : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), |
| "$Rdd32 = vminh($Rtt32,$Rss32)", |
| tc_779080bf, TypeALU64>, Enc_ea23e4 { |
| let Inst{7-5} = 0b001; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011101; |
| let prefersSlot3 = 1; |
| } |
| def A2_vminub : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), |
| "$Rdd32 = vminub($Rtt32,$Rss32)", |
| tc_779080bf, TypeALU64>, Enc_ea23e4 { |
| let Inst{7-5} = 0b000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011101; |
| let prefersSlot3 = 1; |
| } |
| def A2_vminuh : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), |
| "$Rdd32 = vminuh($Rtt32,$Rss32)", |
| tc_779080bf, TypeALU64>, Enc_ea23e4 { |
| let Inst{7-5} = 0b010; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011101; |
| let prefersSlot3 = 1; |
| } |
| def A2_vminuw : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), |
| "$Rdd32 = vminuw($Rtt32,$Rss32)", |
| tc_779080bf, TypeALU64>, Enc_ea23e4 { |
| let Inst{7-5} = 0b100; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011101; |
| let prefersSlot3 = 1; |
| } |
| def A2_vminw : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), |
| "$Rdd32 = vminw($Rtt32,$Rss32)", |
| tc_779080bf, TypeALU64>, Enc_ea23e4 { |
| let Inst{7-5} = 0b011; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011101; |
| let prefersSlot3 = 1; |
| } |
| def A2_vnavgh : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), |
| "$Rdd32 = vnavgh($Rtt32,$Rss32)", |
| tc_6132ba3d, TypeALU64>, Enc_ea23e4 { |
| let Inst{7-5} = 0b000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011100; |
| let prefersSlot3 = 1; |
| } |
| def A2_vnavghcr : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), |
| "$Rdd32 = vnavgh($Rtt32,$Rss32):crnd:sat", |
| tc_002cb246, TypeALU64>, Enc_ea23e4 { |
| let Inst{7-5} = 0b010; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011100; |
| let prefersSlot3 = 1; |
| let Defs = [USR_OVF]; |
| } |
| def A2_vnavghr : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), |
| "$Rdd32 = vnavgh($Rtt32,$Rss32):rnd:sat", |
| tc_002cb246, TypeALU64>, Enc_ea23e4 { |
| let Inst{7-5} = 0b001; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011100; |
| let prefersSlot3 = 1; |
| let Defs = [USR_OVF]; |
| } |
| def A2_vnavgw : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), |
| "$Rdd32 = vnavgw($Rtt32,$Rss32)", |
| tc_6132ba3d, TypeALU64>, Enc_ea23e4 { |
| let Inst{7-5} = 0b011; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011100; |
| let prefersSlot3 = 1; |
| } |
| def A2_vnavgwcr : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), |
| "$Rdd32 = vnavgw($Rtt32,$Rss32):crnd:sat", |
| tc_002cb246, TypeALU64>, Enc_ea23e4 { |
| let Inst{7-5} = 0b110; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011100; |
| let prefersSlot3 = 1; |
| let Defs = [USR_OVF]; |
| } |
| def A2_vnavgwr : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), |
| "$Rdd32 = vnavgw($Rtt32,$Rss32):rnd:sat", |
| tc_002cb246, TypeALU64>, Enc_ea23e4 { |
| let Inst{7-5} = 0b100; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011100; |
| let prefersSlot3 = 1; |
| let Defs = [USR_OVF]; |
| } |
| def A2_vraddub : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Rdd32 = vraddub($Rss32,$Rtt32)", |
| tc_bafaade3, TypeM>, Enc_a56825 { |
| let Inst{7-5} = 0b001; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11101000010; |
| let prefersSlot3 = 1; |
| } |
| def A2_vraddub_acc : HInst< |
| (outs DoubleRegs:$Rxx32), |
| (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Rxx32 += vraddub($Rss32,$Rtt32)", |
| tc_d773585a, TypeM>, Enc_88c16c { |
| let Inst{7-5} = 0b001; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11101010010; |
| let prefersSlot3 = 1; |
| let Constraints = "$Rxx32 = $Rxx32in"; |
| } |
| def A2_vrsadub : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Rdd32 = vrsadub($Rss32,$Rtt32)", |
| tc_bafaade3, TypeM>, Enc_a56825 { |
| let Inst{7-5} = 0b010; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11101000010; |
| let prefersSlot3 = 1; |
| } |
| def A2_vrsadub_acc : HInst< |
| (outs DoubleRegs:$Rxx32), |
| (ins DoubleRegs:$Rxx32in, DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Rxx32 += vrsadub($Rss32,$Rtt32)", |
| tc_d773585a, TypeM>, Enc_88c16c { |
| let Inst{7-5} = 0b010; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11101010010; |
| let prefersSlot3 = 1; |
| let Constraints = "$Rxx32 = $Rxx32in"; |
| } |
| def A2_vsubb_map : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Rdd32 = vsubb($Rss32,$Rtt32)", |
| tc_946df596, TypeMAPPING> { |
| let isPseudo = 1; |
| let isCodeGenOnly = 1; |
| } |
| def A2_vsubh : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), |
| "$Rdd32 = vsubh($Rtt32,$Rss32)", |
| tc_946df596, TypeALU64>, Enc_ea23e4 { |
| let Inst{7-5} = 0b010; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011001; |
| } |
| def A2_vsubhs : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), |
| "$Rdd32 = vsubh($Rtt32,$Rss32):sat", |
| tc_779080bf, TypeALU64>, Enc_ea23e4 { |
| let Inst{7-5} = 0b011; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011001; |
| let prefersSlot3 = 1; |
| let Defs = [USR_OVF]; |
| } |
| def A2_vsubub : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), |
| "$Rdd32 = vsubub($Rtt32,$Rss32)", |
| tc_946df596, TypeALU64>, Enc_ea23e4 { |
| let Inst{7-5} = 0b000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011001; |
| } |
| def A2_vsububs : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), |
| "$Rdd32 = vsubub($Rtt32,$Rss32):sat", |
| tc_779080bf, TypeALU64>, Enc_ea23e4 { |
| let Inst{7-5} = 0b001; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011001; |
| let prefersSlot3 = 1; |
| let Defs = [USR_OVF]; |
| } |
| def A2_vsubuhs : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), |
| "$Rdd32 = vsubuh($Rtt32,$Rss32):sat", |
| tc_779080bf, TypeALU64>, Enc_ea23e4 { |
| let Inst{7-5} = 0b100; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011001; |
| let prefersSlot3 = 1; |
| let Defs = [USR_OVF]; |
| } |
| def A2_vsubw : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), |
| "$Rdd32 = vsubw($Rtt32,$Rss32)", |
| tc_946df596, TypeALU64>, Enc_ea23e4 { |
| let Inst{7-5} = 0b101; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011001; |
| } |
| def A2_vsubws : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), |
| "$Rdd32 = vsubw($Rtt32,$Rss32):sat", |
| tc_779080bf, TypeALU64>, Enc_ea23e4 { |
| let Inst{7-5} = 0b110; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011001; |
| let prefersSlot3 = 1; |
| let Defs = [USR_OVF]; |
| } |
| def A2_xor : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32, IntRegs:$Rt32), |
| "$Rd32 = xor($Rs32,$Rt32)", |
| tc_5a2711e5, TypeALU32_3op>, Enc_5ab2be, PredNewRel { |
| let Inst{7-5} = 0b000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11110001011; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let InputType = "reg"; |
| let BaseOpcode = "A2_xor"; |
| let isCommutable = 1; |
| let isPredicable = 1; |
| } |
| def A2_xorp : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Rdd32 = xor($Rss32,$Rtt32)", |
| tc_946df596, TypeALU64>, Enc_a56825 { |
| let Inst{7-5} = 0b100; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011111; |
| let isCommutable = 1; |
| } |
| def A2_zxtb : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32), |
| "$Rd32 = zxtb($Rs32)", |
| tc_5a2711e5, TypeALU32_2op>, PredNewRel { |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let BaseOpcode = "A2_zxtb"; |
| let isPredicable = 1; |
| let isPseudo = 1; |
| let isCodeGenOnly = 1; |
| } |
| def A2_zxth : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32), |
| "$Rd32 = zxth($Rs32)", |
| tc_57890846, TypeALU32_2op>, Enc_5e2823, PredNewRel { |
| let Inst{13-5} = 0b000000000; |
| let Inst{31-21} = 0b01110000110; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let BaseOpcode = "A2_zxth"; |
| let isPredicable = 1; |
| } |
| def A4_addp_c : HInst< |
| (outs DoubleRegs:$Rdd32, PredRegs:$Px4), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32, PredRegs:$Px4in), |
| "$Rdd32 = add($Rss32,$Rtt32,$Px4):carry", |
| tc_9c3ecd83, TypeS_3op>, Enc_2b3f60 { |
| let Inst{7-7} = 0b0; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11000010110; |
| let isPredicateLate = 1; |
| let Constraints = "$Px4 = $Px4in"; |
| } |
| def A4_andn : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rt32, IntRegs:$Rs32), |
| "$Rd32 = and($Rt32,~$Rs32)", |
| tc_5a2711e5, TypeALU32_3op>, Enc_bd6011 { |
| let Inst{7-5} = 0b000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11110001100; |
| let hasNewValue = 1; |
| let opNewValue = 0; |
| let InputType = "reg"; |
| } |
| def A4_andnp : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins DoubleRegs:$Rtt32, DoubleRegs:$Rss32), |
| "$Rdd32 = and($Rtt32,~$Rss32)", |
| tc_946df596, TypeALU64>, Enc_ea23e4 { |
| let Inst{7-5} = 0b001; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010011111; |
| } |
| def A4_bitsplit : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins IntRegs:$Rs32, IntRegs:$Rt32), |
| "$Rdd32 = bitsplit($Rs32,$Rt32)", |
| tc_4414d8b1, TypeALU64>, Enc_be32a5 { |
| let Inst{7-5} = 0b000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11010100001; |
| let prefersSlot3 = 1; |
| } |
| def A4_bitspliti : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins IntRegs:$Rs32, u5_0Imm:$Ii), |
| "$Rdd32 = bitsplit($Rs32,#$Ii)", |
| tc_4414d8b1, TypeS_2op>, Enc_311abd { |
| let Inst{7-5} = 0b100; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b10001000110; |
| let prefersSlot3 = 1; |
| } |
| def A4_boundscheck : HInst< |
| (outs PredRegs:$Pd4), |
| (ins IntRegs:$Rs32, DoubleRegs:$Rtt32), |
| "$Pd4 = boundscheck($Rs32,$Rtt32)", |
| tc_85d5d03f, TypeALU64> { |
| let isPseudo = 1; |
| } |
| def A4_boundscheck_hi : HInst< |
| (outs PredRegs:$Pd4), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Pd4 = boundscheck($Rss32,$Rtt32):raw:hi", |
| tc_85d5d03f, TypeALU64>, Enc_fcf7a7 { |
| let Inst{7-2} = 0b101000; |
| let Inst{13-13} = 0b1; |
| let Inst{31-21} = 0b11010010000; |
| } |
| def A4_boundscheck_lo : HInst< |
| (outs PredRegs:$Pd4), |
| (ins DoubleRegs:$Rss32, DoubleRegs:$Rtt32), |
| "$Pd4 = boundscheck($Rss32,$Rtt32):raw:lo", |
| tc_85d5d03f, TypeALU64>, Enc_fcf7a7 { |
| let Inst{7-2} = 0b100000; |
| let Inst{13-13} = 0b1; |
| let Inst{31-21} = 0b11010010000; |
| } |
| def A4_cmpbeq : HInst< |
| (outs PredRegs:$Pd4), |
| (ins IntRegs:$Rs32, IntRegs:$Rt32), |
| "$Pd4 = cmpb.eq($Rs32,$Rt32)", |
| tc_85d5d03f, TypeS_3op>, Enc_c2b48e, ImmRegRel { |
| let Inst{7-2} = 0b110000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11000111110; |
| let CextOpcode = "A4_cmpbeq"; |
| let InputType = "reg"; |
| let isCommutable = 1; |
| let isCompare = 1; |
| } |
| def A4_cmpbeqi : HInst< |
| (outs PredRegs:$Pd4), |
| (ins IntRegs:$Rs32, u8_0Imm:$Ii), |
| "$Pd4 = cmpb.eq($Rs32,#$Ii)", |
| tc_643b4717, TypeALU64>, Enc_08d755, ImmRegRel { |
| let Inst{4-2} = 0b000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11011101000; |
| let CextOpcode = "A4_cmpbeq"; |
| let InputType = "imm"; |
| let isCommutable = 1; |
| let isCompare = 1; |
| } |
| def A4_cmpbgt : HInst< |
| (outs PredRegs:$Pd4), |
| (ins IntRegs:$Rs32, IntRegs:$Rt32), |
| "$Pd4 = cmpb.gt($Rs32,$Rt32)", |
| tc_85d5d03f, TypeS_3op>, Enc_c2b48e, ImmRegRel { |
| let Inst{7-2} = 0b010000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11000111110; |
| let CextOpcode = "A4_cmpbgt"; |
| let InputType = "reg"; |
| let isCompare = 1; |
| } |
| def A4_cmpbgti : HInst< |
| (outs PredRegs:$Pd4), |
| (ins IntRegs:$Rs32, s8_0Imm:$Ii), |
| "$Pd4 = cmpb.gt($Rs32,#$Ii)", |
| tc_643b4717, TypeALU64>, Enc_08d755, ImmRegRel { |
| let Inst{4-2} = 0b000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11011101001; |
| let CextOpcode = "A4_cmpbgt"; |
| let InputType = "imm"; |
| let isCompare = 1; |
| } |
| def A4_cmpbgtu : HInst< |
| (outs PredRegs:$Pd4), |
| (ins IntRegs:$Rs32, IntRegs:$Rt32), |
| "$Pd4 = cmpb.gtu($Rs32,$Rt32)", |
| tc_85d5d03f, TypeS_3op>, Enc_c2b48e, ImmRegRel { |
| let Inst{7-2} = 0b111000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11000111110; |
| let CextOpcode = "A4_cmpbgtu"; |
| let InputType = "reg"; |
| let isCompare = 1; |
| } |
| def A4_cmpbgtui : HInst< |
| (outs PredRegs:$Pd4), |
| (ins IntRegs:$Rs32, u32_0Imm:$Ii), |
| "$Pd4 = cmpb.gtu($Rs32,#$Ii)", |
| tc_643b4717, TypeALU64>, Enc_02553a, ImmRegRel { |
| let Inst{4-2} = 0b000; |
| let Inst{13-12} = 0b00; |
| let Inst{31-21} = 0b11011101010; |
| let CextOpcode = "A4_cmpbgtu"; |
| let InputType = "imm"; |
| let isCompare = 1; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 0; |
| let opExtentBits = 7; |
| let opExtentAlign = 0; |
| } |
| def A4_cmpheq : HInst< |
| (outs PredRegs:$Pd4), |
| (ins IntRegs:$Rs32, IntRegs:$Rt32), |
| "$Pd4 = cmph.eq($Rs32,$Rt32)", |
| tc_85d5d03f, TypeS_3op>, Enc_c2b48e, ImmRegRel { |
| let Inst{7-2} = 0b011000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11000111110; |
| let CextOpcode = "A4_cmpheq"; |
| let InputType = "reg"; |
| let isCommutable = 1; |
| let isCompare = 1; |
| } |
| def A4_cmpheqi : HInst< |
| (outs PredRegs:$Pd4), |
| (ins IntRegs:$Rs32, s32_0Imm:$Ii), |
| "$Pd4 = cmph.eq($Rs32,#$Ii)", |
| tc_643b4717, TypeALU64>, Enc_08d755, ImmRegRel { |
| let Inst{4-2} = 0b010; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11011101000; |
| let CextOpcode = "A4_cmpheq"; |
| let InputType = "imm"; |
| let isCommutable = 1; |
| let isCompare = 1; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 8; |
| let opExtentAlign = 0; |
| } |
| def A4_cmphgt : HInst< |
| (outs PredRegs:$Pd4), |
| (ins IntRegs:$Rs32, IntRegs:$Rt32), |
| "$Pd4 = cmph.gt($Rs32,$Rt32)", |
| tc_85d5d03f, TypeS_3op>, Enc_c2b48e, ImmRegRel { |
| let Inst{7-2} = 0b100000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11000111110; |
| let CextOpcode = "A4_cmphgt"; |
| let InputType = "reg"; |
| let isCompare = 1; |
| } |
| def A4_cmphgti : HInst< |
| (outs PredRegs:$Pd4), |
| (ins IntRegs:$Rs32, s32_0Imm:$Ii), |
| "$Pd4 = cmph.gt($Rs32,#$Ii)", |
| tc_643b4717, TypeALU64>, Enc_08d755, ImmRegRel { |
| let Inst{4-2} = 0b010; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11011101001; |
| let CextOpcode = "A4_cmphgt"; |
| let InputType = "imm"; |
| let isCompare = 1; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 8; |
| let opExtentAlign = 0; |
| } |
| def A4_cmphgtu : HInst< |
| (outs PredRegs:$Pd4), |
| (ins IntRegs:$Rs32, IntRegs:$Rt32), |
| "$Pd4 = cmph.gtu($Rs32,$Rt32)", |
| tc_85d5d03f, TypeS_3op>, Enc_c2b48e, ImmRegRel { |
| let Inst{7-2} = 0b101000; |
| let Inst{13-13} = 0b0; |
| let Inst{31-21} = 0b11000111110; |
| let CextOpcode = "A4_cmphgtu"; |
| let InputType = "reg"; |
| let isCompare = 1; |
| } |
| def A4_cmphgtui : HInst< |
| (outs PredRegs:$Pd4), |
| (ins IntRegs:$Rs32, u32_0Imm:$Ii), |
| "$Pd4 = cmph.gtu($Rs32,#$Ii)", |
| tc_643b4717, TypeALU64>, Enc_02553a, ImmRegRel { |
| let Inst{4-2} = 0b010; |
| let Inst{13-12} = 0b00; |
| let Inst{31-21} = 0b11011101010; |
| let CextOpcode = "A4_cmphgtu"; |
| let InputType = "imm"; |
| let isCompare = 1; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 0; |
| let opExtentBits = 7; |
| let opExtentAlign = 0; |
| } |
| def A4_combineii : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins s8_0Imm:$Ii, u32_0Imm:$II), |
| "$Rdd32 = combine(#$Ii,#$II)", |
| tc_5a2711e5, TypeALU32_2op>, Enc_f0cca7 { |
| let Inst{31-21} = 0b01111100100; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 0; |
| let opExtentBits = 6; |
| let opExtentAlign = 0; |
| } |
| def A4_combineir : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins s32_0Imm:$Ii, IntRegs:$Rs32), |
| "$Rdd32 = combine(#$Ii,$Rs32)", |
| tc_5a2711e5, TypeALU32_2op>, Enc_9cdba7 { |
| let Inst{13-13} = 0b1; |
| let Inst{31-21} = 0b01110011001; |
| let isExtendable = 1; |
| let opExtendable = 1; |
| let isExtentSigned = 1; |
| let opExtentBits = 8; |
| let opExtentAlign = 0; |
| } |
| def A4_combineri : HInst< |
| (outs DoubleRegs:$Rdd32), |
| (ins IntRegs:$Rs32, s32_0Imm:$Ii), |
| "$Rdd32 = combine($Rs32,#$Ii)", |
| tc_5a2711e5, TypeALU32_2op>, Enc_9cdba7 { |
| let Inst{13-13} = 0b1; |
| let Inst{31-21} = 0b01110011000; |
| let isExtendable = 1; |
| let opExtendable = 2; |
| let isExtentSigned = 1; |
| let opExtentBits = 8; |
| let opExtentAlign = 0; |
| } |
| def A4_cround_ri : HInst< |
| (outs IntRegs:$Rd32), |
| (ins IntRegs:$Rs32, u5_0Imm:$Ii), |
| "$Rd32 = cround($Rs32,#$Ii)", |
| tc_002cb246, TypeS_2op>, Enc_a05677 { |
| let Inst{7-5} = 0b000; |
|
