| /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
| |* *| |
| |* Target Register Enum Values *| |
| |* *| |
| |* Automatically generated file, do not edit! *| |
| |* *| |
| \*===----------------------------------------------------------------------===*/ |
| |
| |
| #ifdef GET_REGINFO_ENUM |
| #undef GET_REGINFO_ENUM |
| |
| namespace llvm { |
| |
| class MCRegisterClass; |
| extern const MCRegisterClass MipsMCRegisterClasses[]; |
| |
| namespace Mips { |
| enum { |
| NoRegister, |
| AT = 1, |
| DSPCCond = 2, |
| DSPCarry = 3, |
| DSPEFI = 4, |
| DSPOutFlag = 5, |
| DSPPos = 6, |
| DSPSCount = 7, |
| FP = 8, |
| GP = 9, |
| MSAAccess = 10, |
| MSACSR = 11, |
| MSAIR = 12, |
| MSAMap = 13, |
| MSAModify = 14, |
| MSARequest = 15, |
| MSASave = 16, |
| MSAUnmap = 17, |
| PC = 18, |
| RA = 19, |
| SP = 20, |
| ZERO = 21, |
| A0 = 22, |
| A1 = 23, |
| A2 = 24, |
| A3 = 25, |
| AC0 = 26, |
| AC1 = 27, |
| AC2 = 28, |
| AC3 = 29, |
| AT_64 = 30, |
| COP00 = 31, |
| COP01 = 32, |
| COP02 = 33, |
| COP03 = 34, |
| COP04 = 35, |
| COP05 = 36, |
| COP06 = 37, |
| COP07 = 38, |
| COP08 = 39, |
| COP09 = 40, |
| COP20 = 41, |
| COP21 = 42, |
| COP22 = 43, |
| COP23 = 44, |
| COP24 = 45, |
| COP25 = 46, |
| COP26 = 47, |
| COP27 = 48, |
| COP28 = 49, |
| COP29 = 50, |
| COP30 = 51, |
| COP31 = 52, |
| COP32 = 53, |
| COP33 = 54, |
| COP34 = 55, |
| COP35 = 56, |
| COP36 = 57, |
| COP37 = 58, |
| COP38 = 59, |
| COP39 = 60, |
| COP010 = 61, |
| COP011 = 62, |
| COP012 = 63, |
| COP013 = 64, |
| COP014 = 65, |
| COP015 = 66, |
| COP016 = 67, |
| COP017 = 68, |
| COP018 = 69, |
| COP019 = 70, |
| COP020 = 71, |
| COP021 = 72, |
| COP022 = 73, |
| COP023 = 74, |
| COP024 = 75, |
| COP025 = 76, |
| COP026 = 77, |
| COP027 = 78, |
| COP028 = 79, |
| COP029 = 80, |
| COP030 = 81, |
| COP031 = 82, |
| COP210 = 83, |
| COP211 = 84, |
| COP212 = 85, |
| COP213 = 86, |
| COP214 = 87, |
| COP215 = 88, |
| COP216 = 89, |
| COP217 = 90, |
| COP218 = 91, |
| COP219 = 92, |
| COP220 = 93, |
| COP221 = 94, |
| COP222 = 95, |
| COP223 = 96, |
| COP224 = 97, |
| COP225 = 98, |
| COP226 = 99, |
| COP227 = 100, |
| COP228 = 101, |
| COP229 = 102, |
| COP230 = 103, |
| COP231 = 104, |
| COP310 = 105, |
| COP311 = 106, |
| COP312 = 107, |
| COP313 = 108, |
| COP314 = 109, |
| COP315 = 110, |
| COP316 = 111, |
| COP317 = 112, |
| COP318 = 113, |
| COP319 = 114, |
| COP320 = 115, |
| COP321 = 116, |
| COP322 = 117, |
| COP323 = 118, |
| COP324 = 119, |
| COP325 = 120, |
| COP326 = 121, |
| COP327 = 122, |
| COP328 = 123, |
| COP329 = 124, |
| COP330 = 125, |
| COP331 = 126, |
| D0 = 127, |
| D1 = 128, |
| D2 = 129, |
| D3 = 130, |
| D4 = 131, |
| D5 = 132, |
| D6 = 133, |
| D7 = 134, |
| D8 = 135, |
| D9 = 136, |
| D10 = 137, |
| D11 = 138, |
| D12 = 139, |
| D13 = 140, |
| D14 = 141, |
| D15 = 142, |
| DSPOutFlag20 = 143, |
| DSPOutFlag21 = 144, |
| DSPOutFlag22 = 145, |
| DSPOutFlag23 = 146, |
| F0 = 147, |
| F1 = 148, |
| F2 = 149, |
| F3 = 150, |
| F4 = 151, |
| F5 = 152, |
| F6 = 153, |
| F7 = 154, |
| F8 = 155, |
| F9 = 156, |
| F10 = 157, |
| F11 = 158, |
| F12 = 159, |
| F13 = 160, |
| F14 = 161, |
| F15 = 162, |
| F16 = 163, |
| F17 = 164, |
| F18 = 165, |
| F19 = 166, |
| F20 = 167, |
| F21 = 168, |
| F22 = 169, |
| F23 = 170, |
| F24 = 171, |
| F25 = 172, |
| F26 = 173, |
| F27 = 174, |
| F28 = 175, |
| F29 = 176, |
| F30 = 177, |
| F31 = 178, |
| FCC0 = 179, |
| FCC1 = 180, |
| FCC2 = 181, |
| FCC3 = 182, |
| FCC4 = 183, |
| FCC5 = 184, |
| FCC6 = 185, |
| FCC7 = 186, |
| FCR0 = 187, |
| FCR1 = 188, |
| FCR2 = 189, |
| FCR3 = 190, |
| FCR4 = 191, |
| FCR5 = 192, |
| FCR6 = 193, |
| FCR7 = 194, |
| FCR8 = 195, |
| FCR9 = 196, |
| FCR10 = 197, |
| FCR11 = 198, |
| FCR12 = 199, |
| FCR13 = 200, |
| FCR14 = 201, |
| FCR15 = 202, |
| FCR16 = 203, |
| FCR17 = 204, |
| FCR18 = 205, |
| FCR19 = 206, |
| FCR20 = 207, |
| FCR21 = 208, |
| FCR22 = 209, |
| FCR23 = 210, |
| FCR24 = 211, |
| FCR25 = 212, |
| FCR26 = 213, |
| FCR27 = 214, |
| FCR28 = 215, |
| FCR29 = 216, |
| FCR30 = 217, |
| FCR31 = 218, |
| FP_64 = 219, |
| F_HI0 = 220, |
| F_HI1 = 221, |
| F_HI2 = 222, |
| F_HI3 = 223, |
| F_HI4 = 224, |
| F_HI5 = 225, |
| F_HI6 = 226, |
| F_HI7 = 227, |
| F_HI8 = 228, |
| F_HI9 = 229, |
| F_HI10 = 230, |
| F_HI11 = 231, |
| F_HI12 = 232, |
| F_HI13 = 233, |
| F_HI14 = 234, |
| F_HI15 = 235, |
| F_HI16 = 236, |
| F_HI17 = 237, |
| F_HI18 = 238, |
| F_HI19 = 239, |
| F_HI20 = 240, |
| F_HI21 = 241, |
| F_HI22 = 242, |
| F_HI23 = 243, |
| F_HI24 = 244, |
| F_HI25 = 245, |
| F_HI26 = 246, |
| F_HI27 = 247, |
| F_HI28 = 248, |
| F_HI29 = 249, |
| F_HI30 = 250, |
| F_HI31 = 251, |
| GP_64 = 252, |
| HI0 = 253, |
| HI1 = 254, |
| HI2 = 255, |
| HI3 = 256, |
| HWR0 = 257, |
| HWR1 = 258, |
| HWR2 = 259, |
| HWR3 = 260, |
| HWR4 = 261, |
| HWR5 = 262, |
| HWR6 = 263, |
| HWR7 = 264, |
| HWR8 = 265, |
| HWR9 = 266, |
| HWR10 = 267, |
| HWR11 = 268, |
| HWR12 = 269, |
| HWR13 = 270, |
| HWR14 = 271, |
| HWR15 = 272, |
| HWR16 = 273, |
| HWR17 = 274, |
| HWR18 = 275, |
| HWR19 = 276, |
| HWR20 = 277, |
| HWR21 = 278, |
| HWR22 = 279, |
| HWR23 = 280, |
| HWR24 = 281, |
| HWR25 = 282, |
| HWR26 = 283, |
| HWR27 = 284, |
| HWR28 = 285, |
| HWR29 = 286, |
| HWR30 = 287, |
| HWR31 = 288, |
| K0 = 289, |
| K1 = 290, |
| LO0 = 291, |
| LO1 = 292, |
| LO2 = 293, |
| LO3 = 294, |
| MPL0 = 295, |
| MPL1 = 296, |
| MPL2 = 297, |
| P0 = 298, |
| P1 = 299, |
| P2 = 300, |
| RA_64 = 301, |
| S0 = 302, |
| S1 = 303, |
| S2 = 304, |
| S3 = 305, |
| S4 = 306, |
| S5 = 307, |
| S6 = 308, |
| S7 = 309, |
| SP_64 = 310, |
| T0 = 311, |
| T1 = 312, |
| T2 = 313, |
| T3 = 314, |
| T4 = 315, |
| T5 = 316, |
| T6 = 317, |
| T7 = 318, |
| T8 = 319, |
| T9 = 320, |
| V0 = 321, |
| V1 = 322, |
| W0 = 323, |
| W1 = 324, |
| W2 = 325, |
| W3 = 326, |
| W4 = 327, |
| W5 = 328, |
| W6 = 329, |
| W7 = 330, |
| W8 = 331, |
| W9 = 332, |
| W10 = 333, |
| W11 = 334, |
| W12 = 335, |
| W13 = 336, |
| W14 = 337, |
| W15 = 338, |
| W16 = 339, |
| W17 = 340, |
| W18 = 341, |
| W19 = 342, |
| W20 = 343, |
| W21 = 344, |
| W22 = 345, |
| W23 = 346, |
| W24 = 347, |
| W25 = 348, |
| W26 = 349, |
| W27 = 350, |
| W28 = 351, |
| W29 = 352, |
| W30 = 353, |
| W31 = 354, |
| ZERO_64 = 355, |
| A0_64 = 356, |
| A1_64 = 357, |
| A2_64 = 358, |
| A3_64 = 359, |
| AC0_64 = 360, |
| D0_64 = 361, |
| D1_64 = 362, |
| D2_64 = 363, |
| D3_64 = 364, |
| D4_64 = 365, |
| D5_64 = 366, |
| D6_64 = 367, |
| D7_64 = 368, |
| D8_64 = 369, |
| D9_64 = 370, |
| D10_64 = 371, |
| D11_64 = 372, |
| D12_64 = 373, |
| D13_64 = 374, |
| D14_64 = 375, |
| D15_64 = 376, |
| D16_64 = 377, |
| D17_64 = 378, |
| D18_64 = 379, |
| D19_64 = 380, |
| D20_64 = 381, |
| D21_64 = 382, |
| D22_64 = 383, |
| D23_64 = 384, |
| D24_64 = 385, |
| D25_64 = 386, |
| D26_64 = 387, |
| D27_64 = 388, |
| D28_64 = 389, |
| D29_64 = 390, |
| D30_64 = 391, |
| D31_64 = 392, |
| DSPOutFlag16_19 = 393, |
| HI0_64 = 394, |
| K0_64 = 395, |
| K1_64 = 396, |
| LO0_64 = 397, |
| S0_64 = 398, |
| S1_64 = 399, |
| S2_64 = 400, |
| S3_64 = 401, |
| S4_64 = 402, |
| S5_64 = 403, |
| S6_64 = 404, |
| S7_64 = 405, |
| T0_64 = 406, |
| T1_64 = 407, |
| T2_64 = 408, |
| T3_64 = 409, |
| T4_64 = 410, |
| T5_64 = 411, |
| T6_64 = 412, |
| T7_64 = 413, |
| T8_64 = 414, |
| T9_64 = 415, |
| V0_64 = 416, |
| V1_64 = 417, |
| NUM_TARGET_REGS // 418 |
| }; |
| } // end namespace Mips |
| |
| // Register classes |
| |
| namespace Mips { |
| enum { |
| MSA128F16RegClassID = 0, |
| MSA128F16_with_sub_64_in_OddSPRegClassID = 1, |
| OddSPRegClassID = 2, |
| CCRRegClassID = 3, |
| COP0RegClassID = 4, |
| COP2RegClassID = 5, |
| COP3RegClassID = 6, |
| DSPRRegClassID = 7, |
| FGR32RegClassID = 8, |
| FGRCCRegClassID = 9, |
| FGRH32RegClassID = 10, |
| GPR32RegClassID = 11, |
| HWRegsRegClassID = 12, |
| GPR32NONZERORegClassID = 13, |
| OddSP_with_sub_hiRegClassID = 14, |
| FGR32_and_OddSPRegClassID = 15, |
| FGRH32_and_OddSPRegClassID = 16, |
| OddSP_with_sub_hi_with_sub_hi_in_FGRH32RegClassID = 17, |
| CPU16RegsPlusSPRegClassID = 18, |
| CPU16RegsRegClassID = 19, |
| FCCRegClassID = 20, |
| GPRMM16RegClassID = 21, |
| GPRMM16MovePRegClassID = 22, |
| GPRMM16ZeroRegClassID = 23, |
| MSACtrlRegClassID = 24, |
| OddSP_with_sub_hi_with_sub_hi_in_FGR32RegClassID = 25, |
| CPU16Regs_and_GPRMM16ZeroRegClassID = 26, |
| GPR32NONZERO_and_GPRMM16MovePRegClassID = 27, |
| CPU16Regs_and_GPRMM16MovePRegClassID = 28, |
| GPRMM16MoveP_and_GPRMM16ZeroRegClassID = 29, |
| HI32DSPRegClassID = 30, |
| LO32DSPRegClassID = 31, |
| GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID = 32, |
| CPURARegRegClassID = 33, |
| CPUSPRegRegClassID = 34, |
| DSPCCRegClassID = 35, |
| GP32RegClassID = 36, |
| GPR32ZERORegClassID = 37, |
| HI32RegClassID = 38, |
| LO32RegClassID = 39, |
| SP32RegClassID = 40, |
| FGR64RegClassID = 41, |
| GPR64RegClassID = 42, |
| GPR64_with_sub_32_in_GPR32NONZERORegClassID = 43, |
| AFGR64RegClassID = 44, |
| FGR64_and_OddSPRegClassID = 45, |
| GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID = 46, |
| AFGR64_and_OddSPRegClassID = 47, |
| GPR64_with_sub_32_in_CPU16RegsRegClassID = 48, |
| GPR64_with_sub_32_in_GPRMM16MovePRegClassID = 49, |
| GPR64_with_sub_32_in_GPRMM16ZeroRegClassID = 50, |
| GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClassID = 51, |
| GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClassID = 52, |
| ACC64DSPRegClassID = 53, |
| GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClassID = 54, |
| GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClassID = 55, |
| GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID = 56, |
| OCTEON_MPLRegClassID = 57, |
| OCTEON_PRegClassID = 58, |
| ACC64RegClassID = 59, |
| GP64RegClassID = 60, |
| GPR64_with_sub_32_in_CPURARegRegClassID = 61, |
| GPR64_with_sub_32_in_GPR32ZERORegClassID = 62, |
| HI64RegClassID = 63, |
| LO64RegClassID = 64, |
| SP64RegClassID = 65, |
| MSA128BRegClassID = 66, |
| MSA128DRegClassID = 67, |
| MSA128HRegClassID = 68, |
| MSA128WRegClassID = 69, |
| MSA128B_with_sub_64_in_OddSPRegClassID = 70, |
| MSA128WEvensRegClassID = 71, |
| ACC128RegClassID = 72, |
| |
| }; |
| } // end namespace Mips |
| |
| |
| // Subregister indices |
| |
| namespace Mips { |
| enum { |
| NoSubRegister, |
| sub_32, // 1 |
| sub_64, // 2 |
| sub_dsp16_19, // 3 |
| sub_dsp20, // 4 |
| sub_dsp21, // 5 |
| sub_dsp22, // 6 |
| sub_dsp23, // 7 |
| sub_hi, // 8 |
| sub_lo, // 9 |
| sub_hi_then_sub_32, // 10 |
| sub_32_sub_hi_then_sub_32, // 11 |
| NUM_TARGET_SUBREGS |
| }; |
| } // end namespace Mips |
| |
| } // end namespace llvm |
| |
| #endif // GET_REGINFO_ENUM |
| |
| /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
| |* *| |
| |* MC Register Information *| |
| |* *| |
| |* Automatically generated file, do not edit! *| |
| |* *| |
| \*===----------------------------------------------------------------------===*/ |
| |
| |
| #ifdef GET_REGINFO_MC_DESC |
| #undef GET_REGINFO_MC_DESC |
| |
| namespace llvm { |
| |
| extern const MCPhysReg MipsRegDiffLists[] = { |
| /* 0 */ 0, 0, |
| /* 2 */ 4, 1, 1, 1, 1, 0, |
| /* 8 */ 388, 65286, 1, 1, 1, 0, |
| /* 14 */ 20, 1, 0, |
| /* 17 */ 21, 1, 0, |
| /* 20 */ 22, 1, 0, |
| /* 23 */ 23, 1, 0, |
| /* 26 */ 24, 1, 0, |
| /* 29 */ 25, 1, 0, |
| /* 32 */ 26, 1, 0, |
| /* 35 */ 27, 1, 0, |
| /* 38 */ 28, 1, 0, |
| /* 41 */ 29, 1, 0, |
| /* 44 */ 30, 1, 0, |
| /* 47 */ 31, 1, 0, |
| /* 50 */ 32, 1, 0, |
| /* 53 */ 33, 1, 0, |
| /* 56 */ 34, 1, 0, |
| /* 59 */ 35, 1, 0, |
| /* 62 */ 65415, 1, 0, |
| /* 65 */ 65513, 1, 0, |
| /* 68 */ 3, 0, |
| /* 70 */ 4, 0, |
| /* 72 */ 6, 0, |
| /* 74 */ 11, 0, |
| /* 76 */ 12, 0, |
| /* 78 */ 22, 0, |
| /* 80 */ 23, 0, |
| /* 82 */ 29, 0, |
| /* 84 */ 30, 0, |
| /* 86 */ 65308, 72, 0, |
| /* 89 */ 65346, 72, 0, |
| /* 92 */ 38, 65322, 73, 0, |
| /* 96 */ 95, 0, |
| /* 98 */ 96, 0, |
| /* 100 */ 106, 0, |
| /* 102 */ 211, 0, |
| /* 104 */ 243, 0, |
| /* 106 */ 282, 0, |
| /* 108 */ 290, 0, |
| /* 110 */ 334, 0, |
| /* 112 */ 64983, 0, |
| /* 114 */ 65060, 0, |
| /* 116 */ 65148, 0, |
| /* 118 */ 65202, 0, |
| /* 120 */ 65205, 0, |
| /* 122 */ 65246, 0, |
| /* 124 */ 65254, 0, |
| /* 126 */ 65271, 0, |
| /* 128 */ 65293, 0, |
| /* 130 */ 37, 65430, 103, 65395, 65309, 0, |
| /* 136 */ 65325, 0, |
| /* 138 */ 65395, 0, |
| /* 140 */ 65396, 0, |
| /* 142 */ 65397, 0, |
| /* 144 */ 65398, 0, |
| /* 146 */ 65410, 0, |
| /* 148 */ 65415, 0, |
| /* 150 */ 65430, 0, |
| /* 152 */ 65440, 0, |
| /* 154 */ 65441, 0, |
| /* 156 */ 141, 65498, 0, |
| /* 159 */ 65516, 234, 65498, 0, |
| /* 163 */ 65515, 235, 65498, 0, |
| /* 167 */ 65514, 236, 65498, 0, |
| /* 171 */ 65513, 237, 65498, 0, |
| /* 175 */ 65512, 238, 65498, 0, |
| /* 179 */ 65511, 239, 65498, 0, |
| /* 183 */ 65510, 240, 65498, 0, |
| /* 187 */ 65509, 241, 65498, 0, |
| /* 191 */ 65508, 242, 65498, 0, |
| /* 195 */ 65507, 243, 65498, 0, |
| /* 199 */ 65506, 244, 65498, 0, |
| /* 203 */ 65505, 245, 65498, 0, |
| /* 207 */ 65504, 246, 65498, 0, |
| /* 211 */ 65503, 247, 65498, 0, |
| /* 215 */ 65502, 248, 65498, 0, |
| /* 219 */ 65501, 249, 65498, 0, |
| /* 223 */ 65500, 250, 65498, 0, |
| /* 227 */ 265, 65498, 0, |
| /* 230 */ 65271, 371, 65499, 0, |
| /* 234 */ 65309, 368, 65502, 0, |
| /* 238 */ 65507, 0, |
| /* 240 */ 65510, 0, |
| /* 242 */ 65511, 0, |
| /* 244 */ 65512, 0, |
| /* 246 */ 65516, 0, |
| /* 248 */ 65521, 0, |
| /* 250 */ 65522, 0, |
| /* 252 */ 65535, 0, |
| }; |
| |
| extern const LaneBitmask MipsLaneMaskLists[] = { |
| /* 0 */ LaneBitmask(0x00000000), LaneBitmask::getAll(), |
| /* 2 */ LaneBitmask(0x00000001), LaneBitmask::getAll(), |
| /* 4 */ LaneBitmask(0x00000002), LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000010), LaneBitmask(0x00000020), LaneBitmask::getAll(), |
| /* 10 */ LaneBitmask(0x00000001), LaneBitmask(0x00000040), LaneBitmask::getAll(), |
| }; |
| |
| extern const uint16_t MipsSubRegIdxLists[] = { |
| /* 0 */ 1, 0, |
| /* 2 */ 3, 4, 5, 6, 7, 0, |
| /* 8 */ 2, 9, 8, 0, |
| /* 12 */ 9, 1, 8, 10, 11, 0, |
| }; |
| |
| extern const MCRegisterInfo::SubRegCoveredBits MipsSubRegIdxRanges[] = { |
| { 65535, 65535 }, |
| { 0, 32 }, // sub_32 |
| { 0, 64 }, // sub_64 |
| { 16, 4 }, // sub_dsp16_19 |
| { 20, 1 }, // sub_dsp20 |
| { 21, 1 }, // sub_dsp21 |
| { 22, 1 }, // sub_dsp22 |
| { 23, 1 }, // sub_dsp23 |
| { 32, 32 }, // sub_hi |
| { 0, 32 }, // sub_lo |
| { 32, 32 }, // sub_hi_then_sub_32 |
| { 0, 64 }, // sub_32_sub_hi_then_sub_32 |
| }; |
| |
| extern const char MipsRegStrings[] = { |
| /* 0 */ 'C', 'O', 'P', '0', '0', 0, |
| /* 6 */ 'C', 'O', 'P', '0', '1', '0', 0, |
| /* 13 */ 'C', 'O', 'P', '2', '1', '0', 0, |
| /* 20 */ 'C', 'O', 'P', '3', '1', '0', 0, |
| /* 27 */ 'D', '1', '0', 0, |
| /* 31 */ 'F', '1', '0', 0, |
| /* 35 */ 'F', '_', 'H', 'I', '1', '0', 0, |
| /* 42 */ 'F', 'C', 'R', '1', '0', 0, |
| /* 48 */ 'H', 'W', 'R', '1', '0', 0, |
| /* 54 */ 'W', '1', '0', 0, |
| /* 58 */ 'C', 'O', 'P', '0', '2', '0', 0, |
| /* 65 */ 'C', 'O', 'P', '2', '2', '0', 0, |
| /* 72 */ 'C', 'O', 'P', '3', '2', '0', 0, |
| /* 79 */ 'F', '2', '0', 0, |
| /* 83 */ 'F', '_', 'H', 'I', '2', '0', 0, |
| /* 90 */ 'C', 'O', 'P', '2', '0', 0, |
| /* 96 */ 'F', 'C', 'R', '2', '0', 0, |
| /* 102 */ 'H', 'W', 'R', '2', '0', 0, |
| /* 108 */ 'W', '2', '0', 0, |
| /* 112 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '2', '0', 0, |
| /* 125 */ 'C', 'O', 'P', '0', '3', '0', 0, |
| /* 132 */ 'C', 'O', 'P', '2', '3', '0', 0, |
| /* 139 */ 'C', 'O', 'P', '3', '3', '0', 0, |
| /* 146 */ 'F', '3', '0', 0, |
| /* 150 */ 'F', '_', 'H', 'I', '3', '0', 0, |
| /* 157 */ 'C', 'O', 'P', '3', '0', 0, |
| /* 163 */ 'F', 'C', 'R', '3', '0', 0, |
| /* 169 */ 'H', 'W', 'R', '3', '0', 0, |
| /* 175 */ 'W', '3', '0', 0, |
| /* 179 */ 'A', '0', 0, |
| /* 182 */ 'A', 'C', '0', 0, |
| /* 186 */ 'F', 'C', 'C', '0', 0, |
| /* 191 */ 'D', '0', 0, |
| /* 194 */ 'F', '0', 0, |
| /* 197 */ 'F', '_', 'H', 'I', '0', 0, |
| /* 203 */ 'K', '0', 0, |
| /* 206 */ 'M', 'P', 'L', '0', 0, |
| /* 211 */ 'L', 'O', '0', 0, |
| /* 215 */ 'P', '0', 0, |
| /* 218 */ 'F', 'C', 'R', '0', 0, |
| /* 223 */ 'H', 'W', 'R', '0', 0, |
| /* 228 */ 'S', '0', 0, |
| /* 231 */ 'T', '0', 0, |
| /* 234 */ 'V', '0', 0, |
| /* 237 */ 'W', '0', 0, |
| /* 240 */ 'C', 'O', 'P', '0', '1', 0, |
| /* 246 */ 'C', 'O', 'P', '0', '1', '1', 0, |
| /* 253 */ 'C', 'O', 'P', '2', '1', '1', 0, |
| /* 260 */ 'C', 'O', 'P', '3', '1', '1', 0, |
| /* 267 */ 'D', '1', '1', 0, |
| /* 271 */ 'F', '1', '1', 0, |
| /* 275 */ 'F', '_', 'H', 'I', '1', '1', 0, |
| /* 282 */ 'F', 'C', 'R', '1', '1', 0, |
| /* 288 */ 'H', 'W', 'R', '1', '1', 0, |
| /* 294 */ 'W', '1', '1', 0, |
| /* 298 */ 'C', 'O', 'P', '0', '2', '1', 0, |
| /* 305 */ 'C', 'O', 'P', '2', '2', '1', 0, |
| /* 312 */ 'C', 'O', 'P', '3', '2', '1', 0, |
| /* 319 */ 'F', '2', '1', 0, |
| /* 323 */ 'F', '_', 'H', 'I', '2', '1', 0, |
| /* 330 */ 'C', 'O', 'P', '2', '1', 0, |
| /* 336 */ 'F', 'C', 'R', '2', '1', 0, |
| /* 342 */ 'H', 'W', 'R', '2', '1', 0, |
| /* 348 */ 'W', '2', '1', 0, |
| /* 352 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '2', '1', 0, |
| /* 365 */ 'C', 'O', 'P', '0', '3', '1', 0, |
| /* 372 */ 'C', 'O', 'P', '2', '3', '1', 0, |
| /* 379 */ 'C', 'O', 'P', '3', '3', '1', 0, |
| /* 386 */ 'F', '3', '1', 0, |
| /* 390 */ 'F', '_', 'H', 'I', '3', '1', 0, |
| /* 397 */ 'C', 'O', 'P', '3', '1', 0, |
| /* 403 */ 'F', 'C', 'R', '3', '1', 0, |
| /* 409 */ 'H', 'W', 'R', '3', '1', 0, |
| /* 415 */ 'W', '3', '1', 0, |
| /* 419 */ 'A', '1', 0, |
| /* 422 */ 'A', 'C', '1', 0, |
| /* 426 */ 'F', 'C', 'C', '1', 0, |
| /* 431 */ 'D', '1', 0, |
| /* 434 */ 'F', '1', 0, |
| /* 437 */ 'F', '_', 'H', 'I', '1', 0, |
| /* 443 */ 'K', '1', 0, |
| /* 446 */ 'M', 'P', 'L', '1', 0, |
| /* 451 */ 'L', 'O', '1', 0, |
| /* 455 */ 'P', '1', 0, |
| /* 458 */ 'F', 'C', 'R', '1', 0, |
| /* 463 */ 'H', 'W', 'R', '1', 0, |
| /* 468 */ 'S', '1', 0, |
| /* 471 */ 'T', '1', 0, |
| /* 474 */ 'V', '1', 0, |
| /* 477 */ 'W', '1', 0, |
| /* 480 */ 'C', 'O', 'P', '0', '2', 0, |
| /* 486 */ 'C', 'O', 'P', '0', '1', '2', 0, |
| /* 493 */ 'C', 'O', 'P', '2', '1', '2', 0, |
| /* 500 */ 'C', 'O', 'P', '3', '1', '2', 0, |
| /* 507 */ 'D', '1', '2', 0, |
| /* 511 */ 'F', '1', '2', 0, |
| /* 515 */ 'F', '_', 'H', 'I', '1', '2', 0, |
| /* 522 */ 'F', 'C', 'R', '1', '2', 0, |
| /* 528 */ 'H', 'W', 'R', '1', '2', 0, |
| /* 534 */ 'W', '1', '2', 0, |
| /* 538 */ 'C', 'O', 'P', '0', '2', '2', 0, |
| /* 545 */ 'C', 'O', 'P', '2', '2', '2', 0, |
| /* 552 */ 'C', 'O', 'P', '3', '2', '2', 0, |
| /* 559 */ 'F', '2', '2', 0, |
| /* 563 */ 'F', '_', 'H', 'I', '2', '2', 0, |
| /* 570 */ 'C', 'O', 'P', '2', '2', 0, |
| /* 576 */ 'F', 'C', 'R', '2', '2', 0, |
| /* 582 */ 'H', 'W', 'R', '2', '2', 0, |
| /* 588 */ 'W', '2', '2', 0, |
| /* 592 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '2', '2', 0, |
| /* 605 */ 'C', 'O', 'P', '3', '2', 0, |
| /* 611 */ 'A', '2', 0, |
| /* 614 */ 'A', 'C', '2', 0, |
| /* 618 */ 'F', 'C', 'C', '2', 0, |
| /* 623 */ 'D', '2', 0, |
| /* 626 */ 'F', '2', 0, |
| /* 629 */ 'F', '_', 'H', 'I', '2', 0, |
| /* 635 */ 'M', 'P', 'L', '2', 0, |
| /* 640 */ 'L', 'O', '2', 0, |
| /* 644 */ 'P', '2', 0, |
| /* 647 */ 'F', 'C', 'R', '2', 0, |
| /* 652 */ 'H', 'W', 'R', '2', 0, |
| /* 657 */ 'S', '2', 0, |
| /* 660 */ 'T', '2', 0, |
| /* 663 */ 'W', '2', 0, |
| /* 666 */ 'C', 'O', 'P', '0', '3', 0, |
| /* 672 */ 'C', 'O', 'P', '0', '1', '3', 0, |
| /* 679 */ 'C', 'O', 'P', '2', '1', '3', 0, |
| /* 686 */ 'C', 'O', 'P', '3', '1', '3', 0, |
| /* 693 */ 'D', '1', '3', 0, |
| /* 697 */ 'F', '1', '3', 0, |
| /* 701 */ 'F', '_', 'H', 'I', '1', '3', 0, |
| /* 708 */ 'F', 'C', 'R', '1', '3', 0, |
| /* 714 */ 'H', 'W', 'R', '1', '3', 0, |
| /* 720 */ 'W', '1', '3', 0, |
| /* 724 */ 'C', 'O', 'P', '0', '2', '3', 0, |
| /* 731 */ 'C', 'O', 'P', '2', '2', '3', 0, |
| /* 738 */ 'C', 'O', 'P', '3', '2', '3', 0, |
| /* 745 */ 'F', '2', '3', 0, |
| /* 749 */ 'F', '_', 'H', 'I', '2', '3', 0, |
| /* 756 */ 'C', 'O', 'P', '2', '3', 0, |
| /* 762 */ 'F', 'C', 'R', '2', '3', 0, |
| /* 768 */ 'H', 'W', 'R', '2', '3', 0, |
| /* 774 */ 'W', '2', '3', 0, |
| /* 778 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '2', '3', 0, |
| /* 791 */ 'C', 'O', 'P', '3', '3', 0, |
| /* 797 */ 'A', '3', 0, |
| /* 800 */ 'A', 'C', '3', 0, |
| /* 804 */ 'F', 'C', 'C', '3', 0, |
| /* 809 */ 'D', '3', 0, |
| /* 812 */ 'F', '3', 0, |
| /* 815 */ 'F', '_', 'H', 'I', '3', 0, |
| /* 821 */ 'L', 'O', '3', 0, |
| /* 825 */ 'F', 'C', 'R', '3', 0, |
| /* 830 */ 'H', 'W', 'R', '3', 0, |
| /* 835 */ 'S', '3', 0, |
| /* 838 */ 'T', '3', 0, |
| /* 841 */ 'W', '3', 0, |
| /* 844 */ 'C', 'O', 'P', '0', '4', 0, |
| /* 850 */ 'C', 'O', 'P', '0', '1', '4', 0, |
| /* 857 */ 'C', 'O', 'P', '2', '1', '4', 0, |
| /* 864 */ 'C', 'O', 'P', '3', '1', '4', 0, |
| /* 871 */ 'D', '1', '4', 0, |
| /* 875 */ 'F', '1', '4', 0, |
| /* 879 */ 'F', '_', 'H', 'I', '1', '4', 0, |
| /* 886 */ 'F', 'C', 'R', '1', '4', 0, |
| /* 892 */ 'H', 'W', 'R', '1', '4', 0, |
| /* 898 */ 'W', '1', '4', 0, |
| /* 902 */ 'C', 'O', 'P', '0', '2', '4', 0, |
| /* 909 */ 'C', 'O', 'P', '2', '2', '4', 0, |
| /* 916 */ 'C', 'O', 'P', '3', '2', '4', 0, |
| /* 923 */ 'F', '2', '4', 0, |
| /* 927 */ 'F', '_', 'H', 'I', '2', '4', 0, |
| /* 934 */ 'C', 'O', 'P', '2', '4', 0, |
| /* 940 */ 'F', 'C', 'R', '2', '4', 0, |
| /* 946 */ 'H', 'W', 'R', '2', '4', 0, |
| /* 952 */ 'W', '2', '4', 0, |
| /* 956 */ 'C', 'O', 'P', '3', '4', 0, |
| /* 962 */ 'D', '1', '0', '_', '6', '4', 0, |
| /* 969 */ 'D', '2', '0', '_', '6', '4', 0, |
| /* 976 */ 'D', '3', '0', '_', '6', '4', 0, |
| /* 983 */ 'A', '0', '_', '6', '4', 0, |
| /* 989 */ 'A', 'C', '0', '_', '6', '4', 0, |
| /* 996 */ 'D', '0', '_', '6', '4', 0, |
| /* 1002 */ 'H', 'I', '0', '_', '6', '4', 0, |
| /* 1009 */ 'K', '0', '_', '6', '4', 0, |
| /* 1015 */ 'L', 'O', '0', '_', '6', '4', 0, |
| /* 1022 */ 'S', '0', '_', '6', '4', 0, |
| /* 1028 */ 'T', '0', '_', '6', '4', 0, |
| /* 1034 */ 'V', '0', '_', '6', '4', 0, |
| /* 1040 */ 'D', '1', '1', '_', '6', '4', 0, |
| /* 1047 */ 'D', '2', '1', '_', '6', '4', 0, |
| /* 1054 */ 'D', '3', '1', '_', '6', '4', 0, |
| /* 1061 */ 'A', '1', '_', '6', '4', 0, |
| /* 1067 */ 'D', '1', '_', '6', '4', 0, |
| /* 1073 */ 'K', '1', '_', '6', '4', 0, |
| /* 1079 */ 'S', '1', '_', '6', '4', 0, |
| /* 1085 */ 'T', '1', '_', '6', '4', 0, |
| /* 1091 */ 'V', '1', '_', '6', '4', 0, |
| /* 1097 */ 'D', '1', '2', '_', '6', '4', 0, |
| /* 1104 */ 'D', '2', '2', '_', '6', '4', 0, |
| /* 1111 */ 'A', '2', '_', '6', '4', 0, |
| /* 1117 */ 'D', '2', '_', '6', '4', 0, |
| /* 1123 */ 'S', '2', '_', '6', '4', 0, |
| /* 1129 */ 'T', '2', '_', '6', '4', 0, |
| /* 1135 */ 'D', '1', '3', '_', '6', '4', 0, |
| /* 1142 */ 'D', '2', '3', '_', '6', '4', 0, |
| /* 1149 */ 'A', '3', '_', '6', '4', 0, |
| /* 1155 */ 'D', '3', '_', '6', '4', 0, |
| /* 1161 */ 'S', '3', '_', '6', '4', 0, |
| /* 1167 */ 'T', '3', '_', '6', '4', 0, |
| /* 1173 */ 'D', '1', '4', '_', '6', '4', 0, |
| /* 1180 */ 'D', '2', '4', '_', '6', '4', 0, |
| /* 1187 */ 'D', '4', '_', '6', '4', 0, |
| /* 1193 */ 'S', '4', '_', '6', '4', 0, |
| /* 1199 */ 'T', '4', '_', '6', '4', 0, |
| /* 1205 */ 'D', '1', '5', '_', '6', '4', 0, |
| /* 1212 */ 'D', '2', '5', '_', '6', '4', 0, |
| /* 1219 */ 'D', '5', '_', '6', '4', 0, |
| /* 1225 */ 'S', '5', '_', '6', '4', 0, |
| /* 1231 */ 'T', '5', '_', '6', '4', 0, |
| /* 1237 */ 'D', '1', '6', '_', '6', '4', 0, |
| /* 1244 */ 'D', '2', '6', '_', '6', '4', 0, |
| /* 1251 */ 'D', '6', '_', '6', '4', 0, |
| /* 1257 */ 'S', '6', '_', '6', '4', 0, |
| /* 1263 */ 'T', '6', '_', '6', '4', 0, |
| /* 1269 */ 'D', '1', '7', '_', '6', '4', 0, |
| /* 1276 */ 'D', '2', '7', '_', '6', '4', 0, |
| /* 1283 */ 'D', '7', '_', '6', '4', 0, |
| /* 1289 */ 'S', '7', '_', '6', '4', 0, |
| /* 1295 */ 'T', '7', '_', '6', '4', 0, |
| /* 1301 */ 'D', '1', '8', '_', '6', '4', 0, |
| /* 1308 */ 'D', '2', '8', '_', '6', '4', 0, |
| /* 1315 */ 'D', '8', '_', '6', '4', 0, |
| /* 1321 */ 'T', '8', '_', '6', '4', 0, |
| /* 1327 */ 'D', '1', '9', '_', '6', '4', 0, |
| /* 1334 */ 'D', '2', '9', '_', '6', '4', 0, |
| /* 1341 */ 'D', '9', '_', '6', '4', 0, |
| /* 1347 */ 'T', '9', '_', '6', '4', 0, |
| /* 1353 */ 'R', 'A', '_', '6', '4', 0, |
| /* 1359 */ 'Z', 'E', 'R', 'O', '_', '6', '4', 0, |
| /* 1367 */ 'F', 'P', '_', '6', '4', 0, |
| /* 1373 */ 'G', 'P', '_', '6', '4', 0, |
| /* 1379 */ 'S', 'P', '_', '6', '4', 0, |
| /* 1385 */ 'A', 'T', '_', '6', '4', 0, |
| /* 1391 */ 'F', 'C', 'C', '4', 0, |
| /* 1396 */ 'D', '4', 0, |
| /* 1399 */ 'F', '4', 0, |
| /* 1402 */ 'F', '_', 'H', 'I', '4', 0, |
| /* 1408 */ 'F', 'C', 'R', '4', 0, |
| /* 1413 */ 'H', 'W', 'R', '4', 0, |
| /* 1418 */ 'S', '4', 0, |
| /* 1421 */ 'T', '4', 0, |
| /* 1424 */ 'W', '4', 0, |
| /* 1427 */ 'C', 'O', 'P', '0', '5', 0, |
| /* 1433 */ 'C', 'O', 'P', '0', '1', '5', 0, |
| /* 1440 */ 'C', 'O', 'P', '2', '1', '5', 0, |
| /* 1447 */ 'C', 'O', 'P', '3', '1', '5', 0, |
| /* 1454 */ 'D', '1', '5', 0, |
| /* 1458 */ 'F', '1', '5', 0, |
| /* 1462 */ 'F', '_', 'H', 'I', '1', '5', 0, |
| /* 1469 */ 'F', 'C', 'R', '1', '5', 0, |
| /* 1475 */ 'H', 'W', 'R', '1', '5', 0, |
| /* 1481 */ 'W', '1', '5', 0, |
| /* 1485 */ 'C', 'O', 'P', '0', '2', '5', 0, |
| /* 1492 */ 'C', 'O', 'P', '2', '2', '5', 0, |
| /* 1499 */ 'C', 'O', 'P', '3', '2', '5', 0, |
| /* 1506 */ 'F', '2', '5', 0, |
| /* 1510 */ 'F', '_', 'H', 'I', '2', '5', 0, |
| /* 1517 */ 'C', 'O', 'P', '2', '5', 0, |
| /* 1523 */ 'F', 'C', 'R', '2', '5', 0, |
| /* 1529 */ 'H', 'W', 'R', '2', '5', 0, |
| /* 1535 */ 'W', '2', '5', 0, |
| /* 1539 */ 'C', 'O', 'P', '3', '5', 0, |
| /* 1545 */ 'F', 'C', 'C', '5', 0, |
| /* 1550 */ 'D', '5', 0, |
| /* 1553 */ 'F', '5', 0, |
| /* 1556 */ 'F', '_', 'H', 'I', '5', 0, |
| /* 1562 */ 'F', 'C', 'R', '5', 0, |
| /* 1567 */ 'H', 'W', 'R', '5', 0, |
| /* 1572 */ 'S', '5', 0, |
| /* 1575 */ 'T', '5', 0, |
| /* 1578 */ 'W', '5', 0, |
| /* 1581 */ 'C', 'O', 'P', '0', '6', 0, |
| /* 1587 */ 'C', 'O', 'P', '0', '1', '6', 0, |
| /* 1594 */ 'C', 'O', 'P', '2', '1', '6', 0, |
| /* 1601 */ 'C', 'O', 'P', '3', '1', '6', 0, |
| /* 1608 */ 'F', '1', '6', 0, |
| /* 1612 */ 'F', '_', 'H', 'I', '1', '6', 0, |
| /* 1619 */ 'F', 'C', 'R', '1', '6', 0, |
| /* 1625 */ 'H', 'W', 'R', '1', '6', 0, |
| /* 1631 */ 'W', '1', '6', 0, |
| /* 1635 */ 'C', 'O', 'P', '0', '2', '6', 0, |
| /* 1642 */ 'C', 'O', 'P', '2', '2', '6', 0, |
| /* 1649 */ 'C', 'O', 'P', '3', '2', '6', 0, |
| /* 1656 */ 'F', '2', '6', 0, |
| /* 1660 */ 'F', '_', 'H', 'I', '2', '6', 0, |
| /* 1667 */ 'C', 'O', 'P', '2', '6', 0, |
| /* 1673 */ 'F', 'C', 'R', '2', '6', 0, |
| /* 1679 */ 'H', 'W', 'R', '2', '6', 0, |
| /* 1685 */ 'W', '2', '6', 0, |
| /* 1689 */ 'C', 'O', 'P', '3', '6', 0, |
| /* 1695 */ 'F', 'C', 'C', '6', 0, |
| /* 1700 */ 'D', '6', 0, |
| /* 1703 */ 'F', '6', 0, |
| /* 1706 */ 'F', '_', 'H', 'I', '6', 0, |
| /* 1712 */ 'F', 'C', 'R', '6', 0, |
| /* 1717 */ 'H', 'W', 'R', '6', 0, |
| /* 1722 */ 'S', '6', 0, |
| /* 1725 */ 'T', '6', 0, |
| /* 1728 */ 'W', '6', 0, |
| /* 1731 */ 'C', 'O', 'P', '0', '7', 0, |
| /* 1737 */ 'C', 'O', 'P', '0', '1', '7', 0, |
| /* 1744 */ 'C', 'O', 'P', '2', '1', '7', 0, |
| /* 1751 */ 'C', 'O', 'P', '3', '1', '7', 0, |
| /* 1758 */ 'F', '1', '7', 0, |
| /* 1762 */ 'F', '_', 'H', 'I', '1', '7', 0, |
| /* 1769 */ 'F', 'C', 'R', '1', '7', 0, |
| /* 1775 */ 'H', 'W', 'R', '1', '7', 0, |
| /* 1781 */ 'W', '1', '7', 0, |
| /* 1785 */ 'C', 'O', 'P', '0', '2', '7', 0, |
| /* 1792 */ 'C', 'O', 'P', '2', '2', '7', 0, |
| /* 1799 */ 'C', 'O', 'P', '3', '2', '7', 0, |
| /* 1806 */ 'F', '2', '7', 0, |
| /* 1810 */ 'F', '_', 'H', 'I', '2', '7', 0, |
| /* 1817 */ 'C', 'O', 'P', '2', '7', 0, |
| /* 1823 */ 'F', 'C', 'R', '2', '7', 0, |
| /* 1829 */ 'H', 'W', 'R', '2', '7', 0, |
| /* 1835 */ 'W', '2', '7', 0, |
| /* 1839 */ 'C', 'O', 'P', '3', '7', 0, |
| /* 1845 */ 'F', 'C', 'C', '7', 0, |
| /* 1850 */ 'D', '7', 0, |
| /* 1853 */ 'F', '7', 0, |
| /* 1856 */ 'F', '_', 'H', 'I', '7', 0, |
| /* 1862 */ 'F', 'C', 'R', '7', 0, |
| /* 1867 */ 'H', 'W', 'R', '7', 0, |
| /* 1872 */ 'S', '7', 0, |
| /* 1875 */ 'T', '7', 0, |
| /* 1878 */ 'W', '7', 0, |
| /* 1881 */ 'C', 'O', 'P', '0', '8', 0, |
| /* 1887 */ 'C', 'O', 'P', '0', '1', '8', 0, |
| /* 1894 */ 'C', 'O', 'P', '2', '1', '8', 0, |
| /* 1901 */ 'C', 'O', 'P', '3', '1', '8', 0, |
| /* 1908 */ 'F', '1', '8', 0, |
| /* 1912 */ 'F', '_', 'H', 'I', '1', '8', 0, |
| /* 1919 */ 'F', 'C', 'R', '1', '8', 0, |
| /* 1925 */ 'H', 'W', 'R', '1', '8', 0, |
| /* 1931 */ 'W', '1', '8', 0, |
| /* 1935 */ 'C', 'O', 'P', '0', '2', '8', 0, |
| /* 1942 */ 'C', 'O', 'P', '2', '2', '8', 0, |
| /* 1949 */ 'C', 'O', 'P', '3', '2', '8', 0, |
| /* 1956 */ 'F', '2', '8', 0, |
| /* 1960 */ 'F', '_', 'H', 'I', '2', '8', 0, |
| /* 1967 */ 'C', 'O', 'P', '2', '8', 0, |
| /* 1973 */ 'F', 'C', 'R', '2', '8', 0, |
| /* 1979 */ 'H', 'W', 'R', '2', '8', 0, |
| /* 1985 */ 'W', '2', '8', 0, |
| /* 1989 */ 'C', 'O', 'P', '3', '8', 0, |
| /* 1995 */ 'D', '8', 0, |
| /* 1998 */ 'F', '8', 0, |
| /* 2001 */ 'F', '_', 'H', 'I', '8', 0, |
| /* 2007 */ 'F', 'C', 'R', '8', 0, |
| /* 2012 */ 'H', 'W', 'R', '8', 0, |
| /* 2017 */ 'T', '8', 0, |
| /* 2020 */ 'W', '8', 0, |
| /* 2023 */ 'C', 'O', 'P', '0', '9', 0, |
| /* 2029 */ 'C', 'O', 'P', '0', '1', '9', 0, |
| /* 2036 */ 'C', 'O', 'P', '2', '1', '9', 0, |
| /* 2043 */ 'C', 'O', 'P', '3', '1', '9', 0, |
| /* 2050 */ 'F', '1', '9', 0, |
| /* 2054 */ 'F', '_', 'H', 'I', '1', '9', 0, |
| /* 2061 */ 'F', 'C', 'R', '1', '9', 0, |
| /* 2067 */ 'H', 'W', 'R', '1', '9', 0, |
| /* 2073 */ 'W', '1', '9', 0, |
| /* 2077 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '1', '6', '_', '1', '9', 0, |
| /* 2093 */ 'C', 'O', 'P', '0', '2', '9', 0, |
| /* 2100 */ 'C', 'O', 'P', '2', '2', '9', 0, |
| /* 2107 */ 'C', 'O', 'P', '3', '2', '9', 0, |
| /* 2114 */ 'F', '2', '9', 0, |
| /* 2118 */ 'F', '_', 'H', 'I', '2', '9', 0, |
| /* 2125 */ 'C', 'O', 'P', '2', '9', 0, |
| /* 2131 */ 'F', 'C', 'R', '2', '9', 0, |
| /* 2137 */ 'H', 'W', 'R', '2', '9', 0, |
| /* 2143 */ 'W', '2', '9', 0, |
| /* 2147 */ 'C', 'O', 'P', '3', '9', 0, |
| /* 2153 */ 'D', '9', 0, |
| /* 2156 */ 'F', '9', 0, |
| /* 2159 */ 'F', '_', 'H', 'I', '9', 0, |
| /* 2165 */ 'F', 'C', 'R', '9', 0, |
| /* 2170 */ 'H', 'W', 'R', '9', 0, |
| /* 2175 */ 'T', '9', 0, |
| /* 2178 */ 'W', '9', 0, |
| /* 2181 */ 'R', 'A', 0, |
| /* 2184 */ 'P', 'C', 0, |
| /* 2187 */ 'D', 'S', 'P', 'E', 'F', 'I', 0, |
| /* 2194 */ 'Z', 'E', 'R', 'O', 0, |
| /* 2199 */ 'F', 'P', 0, |
| /* 2202 */ 'G', 'P', 0, |
| /* 2205 */ 'S', 'P', 0, |
| /* 2208 */ 'M', 'S', 'A', 'I', 'R', 0, |
| /* 2214 */ 'M', 'S', 'A', 'C', 'S', 'R', 0, |
| /* 2221 */ 'A', 'T', 0, |
| /* 2224 */ 'D', 'S', 'P', 'C', 'C', 'o', 'n', 'd', 0, |
| /* 2233 */ 'M', 'S', 'A', 'S', 'a', 'v', 'e', 0, |
| /* 2241 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', 0, |
| /* 2252 */ 'M', 'S', 'A', 'M', 'a', 'p', 0, |
| /* 2259 */ 'M', 'S', 'A', 'U', 'n', 'm', 'a', 'p', 0, |
| /* 2268 */ 'D', 'S', 'P', 'P', 'o', 's', 0, |
| /* 2275 */ 'M', 'S', 'A', 'A', 'c', 'c', 'e', 's', 's', 0, |
| /* 2285 */ 'D', 'S', 'P', 'S', 'C', 'o', 'u', 'n', 't', 0, |
| /* 2295 */ 'M', 'S', 'A', 'R', 'e', 'q', 'u', 'e', 's', 't', 0, |
| /* 2306 */ 'M', 'S', 'A', 'M', 'o', 'd', 'i', 'f', 'y', 0, |
| /* 2316 */ 'D', 'S', 'P', 'C', 'a', 'r', 'r', 'y', 0, |
| }; |
| |
| extern const MCRegisterDesc MipsRegDesc[] = { // Descriptors |
| { 5, 0, 0, 0, 0, 0 }, |
| { 2221, 1, 82, 1, 4033, 0 }, |
| { 2224, 1, 1, 1, 4033, 0 }, |
| { 2316, 1, 1, 1, 4033, 0 }, |
| { 2187, 1, 1, 1, 4033, 0 }, |
| { 2241, 8, 1, 2, 32, 4 }, |
| { 2268, 1, 1, 1, 1089, 0 }, |
| { 2285, 1, 1, 1, 1089, 0 }, |
| { 2199, 1, 102, 1, 1089, 0 }, |
| { 2202, 1, 104, 1, 1089, 0 }, |
| { 2275, 1, 1, 1, 1089, 0 }, |
| { 2214, 1, 1, 1, 1089, 0 }, |
| { 2208, 1, 1, 1, 1089, 0 }, |
| { 2252, 1, 1, 1, 1089, 0 }, |
| { 2306, 1, 1, 1, 1089, 0 }, |
| { 2295, 1, 1, 1, 1089, 0 }, |
| { 2233, 1, 1, 1, 1089, 0 }, |
| { 2259, 1, 1, 1, 1089, 0 }, |
| { 2184, 1, 1, 1, 1089, 0 }, |
| { 2181, 1, 106, 1, 1089, 0 }, |
| { 2205, 1, 108, 1, 1089, 0 }, |
| { 2194, 1, 110, 1, 1089, 0 }, |
| { 179, 1, 110, 1, 1089, 0 }, |
| { 419, 1, 110, 1, 1089, 0 }, |
| { 611, 1, 110, 1, 1089, 0 }, |
| { 797, 1, 110, 1, 1089, 0 }, |
| { 182, 227, 110, 9, 1042, 10 }, |
| { 422, 227, 1, 9, 1042, 10 }, |
| { 614, 227, 1, 9, 1042, 10 }, |
| { 800, 227, 1, 9, 1042, 10 }, |
| { 1385, 238, 1, 0, 0, 2 }, |
| { 0, 1, 1, 1, 1153, 0 }, |
| { 240, 1, 1, 1, 1153, 0 }, |
| { 480, 1, 1, 1, 1153, 0 }, |
| { 666, 1, 1, 1, 1153, 0 }, |
| { 844, 1, 1, 1, 1153, 0 }, |
| { 1427, 1, 1, 1, 1153, 0 }, |
| { 1581, 1, 1, 1, 1153, 0 }, |
| { 1731, 1, 1, 1, 1153, 0 }, |
| { 1881, 1, 1, 1, 1153, 0 }, |
| { 2023, 1, 1, 1, 1153, 0 }, |
| { 90, 1, 1, 1, 1153, 0 }, |
| { 330, 1, 1, 1, 1153, 0 }, |
| { 570, 1, 1, 1, 1153, 0 }, |
| { 756, 1, 1, 1, 1153, 0 }, |
| { 934, 1, 1, 1, 1153, 0 }, |
| { 1517, 1, 1, 1, 1153, 0 }, |
| { 1667, 1, 1, 1, 1153, 0 }, |
| { 1817, 1, 1, 1, 1153, 0 }, |
| { 1967, 1, 1, 1, 1153, 0 }, |
| { 2125, 1, 1, 1, 1153, 0 }, |
| { 157, 1, 1, 1, 1153, 0 }, |
| { 397, 1, 1, 1, 1153, 0 }, |
| { 605, 1, 1, 1, 1153, 0 }, |
| { 791, 1, 1, 1, 1153, 0 }, |
| { 956, 1, 1, 1, 1153, 0 }, |
| { 1539, 1, 1, 1, 1153, 0 }, |
| { 1689, 1, 1, 1, 1153, 0 }, |
| { 1839, 1, 1, 1, 1153, 0 }, |
| { 1989, 1, 1, 1, 1153, 0 }, |
| { 2147, 1, 1, 1, 1153, 0 }, |
| { 6, 1, 1, 1, 1153, 0 }, |
| { 246, 1, 1, 1, 1153, 0 }, |
| { 486, 1, 1, 1, 1153, 0 }, |
| { 672, 1, 1, 1, 1153, 0 }, |
| { 850, 1, 1, 1, 1153, 0 }, |
| { 1433, 1, 1, 1, 1153, 0 }, |
| { 1587, 1, 1, 1, 1153, 0 }, |
| { 1737, 1, 1, 1, 1153, 0 }, |
| { 1887, 1, 1, 1, 1153, 0 }, |
| { 2029, 1, 1, 1, 1153, 0 }, |
| { 58, 1, 1, 1, 1153, 0 }, |
| { 298, 1, 1, 1, 1153, 0 }, |
| { 538, 1, 1, 1, 1153, 0 }, |
| { 724, 1, 1, 1, 1153, 0 }, |
| { 902, 1, 1, 1, 1153, 0 }, |
| { 1485, 1, 1, 1, 1153, 0 }, |
| { 1635, 1, 1, 1, 1153, 0 }, |
| { 1785, 1, 1, 1, 1153, 0 }, |
| { 1935, 1, 1, 1, 1153, 0 }, |
| { 2093, 1, 1, 1, 1153, 0 }, |
| { 125, 1, 1, 1, 1153, 0 }, |
| { 365, 1, 1, 1, 1153, 0 }, |
| { 13, 1, 1, 1, 1153, 0 }, |
| { 253, 1, 1, 1, 1153, 0 }, |
| { 493, 1, 1, 1, 1153, 0 }, |
| { 679, 1, 1, 1, 1153, 0 }, |
| { 857, 1, 1, 1, 1153, 0 }, |
| { 1440, 1, 1, 1, 1153, 0 }, |
| { 1594, 1, 1, 1, 1153, 0 }, |
| { 1744, 1, 1, 1, 1153, 0 }, |
| { 1894, 1, 1, 1, 1153, 0 }, |
| { 2036, 1, 1, 1, 1153, 0 }, |
| { 65, 1, 1, 1, 1153, 0 }, |
| { 305, 1, 1, 1, 1153, 0 }, |
| { 545, 1, 1, 1, 1153, 0 }, |
| { 731, 1, 1, 1, 1153, 0 }, |
| { 909, 1, 1, 1, 1153, 0 }, |
| { 1492, 1, 1, 1, 1153, 0 }, |
| { 1642, 1, 1, 1, 1153, 0 }, |
| { 1792, 1, 1, 1, 1153, 0 }, |
| { 1942, 1, 1, 1, 1153, 0 }, |
| { 2100, 1, 1, 1, 1153, 0 }, |
| { 132, 1, 1, 1, 1153, 0 }, |
| { 372, 1, 1, 1, 1153, 0 }, |
| { 20, 1, 1, 1, 1153, 0 }, |
| { 260, 1, 1, 1, 1153, 0 }, |
| { 500, 1, 1, 1, 1153, 0 }, |
| { 686, 1, 1, 1, 1153, 0 }, |
| { 864, 1, 1, 1, 1153, 0 }, |
| { 1447, 1, 1, 1, 1153, 0 }, |
| { 1601, 1, 1, 1, 1153, 0 }, |
| { 1751, 1, 1, 1, 1153, 0 }, |
| { 1901, 1, 1, 1, 1153, 0 }, |
| { 2043, 1, 1, 1, 1153, 0 }, |
| { 72, 1, 1, 1, 1153, 0 }, |
| { 312, 1, 1, 1, 1153, 0 }, |
| { 552, 1, 1, 1, 1153, 0 }, |
| { 738, 1, 1, 1, 1153, 0 }, |
| { 916, 1, 1, 1, 1153, 0 }, |
| { 1499, 1, 1, 1, 1153, 0 }, |
| { 1649, 1, 1, 1, 1153, 0 }, |
| { 1799, 1, 1, 1, 1153, 0 }, |
| { 1949, 1, 1, 1, 1153, 0 }, |
| { 2107, 1, 1, 1, 1153, 0 }, |
| { 139, 1, 1, 1, 1153, 0 }, |
| { 379, 1, 1, 1, 1153, 0 }, |
| { 191, 14, 1, 9, 994, 10 }, |
| { 431, 17, 1, 9, 994, 10 }, |
| { 623, 20, 1, 9, 994, 10 }, |
| { 809, 23, 1, 9, 994, 10 }, |
| { 1396, 26, 1, 9, 994, 10 }, |
| { 1550, 29, 1, 9, 994, 10 }, |
| { 1700, 32, 1, 9, 994, 10 }, |
| { 1850, 35, 1, 9, 994, 10 }, |
| { 1995, 38, 1, 9, 994, 10 }, |
| { 2153, 41, 1, 9, 994, 10 }, |
| { 27, 44, 1, 9, 994, 10 }, |
| { 267, 47, 1, 9, 994, 10 }, |
| { 507, 50, 1, 9, 994, 10 }, |
| { 693, 53, 1, 9, 994, 10 }, |
| { 871, 56, 1, 9, 994, 10 }, |
| { 1454, 59, 1, 9, 994, 10 }, |
| { 112, 1, 144, 1, 2305, 0 }, |
| { 352, 1, 142, 1, 2305, 0 }, |
| { 592, 1, 140, 1, 2305, 0 }, |
| { 778, 1, 138, 1, 2305, 0 }, |
| { 194, 1, 159, 1, 4001, 0 }, |
| { 434, 1, 163, 1, 4001, 0 }, |
| { 626, 1, 163, 1, 4001, 0 }, |
| { 812, 1, 167, 1, 4001, 0 }, |
| { 1399, 1, 167, 1, 4001, 0 }, |
| { 1553, 1, 171, 1, 4001, 0 }, |
| { 1703, 1, 171, 1, 4001, 0 }, |
| { 1853, 1, 175, 1, 4001, 0 }, |
| { 1998, 1, 175, 1, 4001, 0 }, |
| { 2156, 1, 179, 1, 4001, 0 }, |
| { 31, 1, 179, 1, 4001, 0 }, |
| { 271, 1, 183, 1, 4001, 0 }, |
| { 511, 1, 183, 1, 4001, 0 }, |
| { 697, 1, 187, 1, 4001, 0 }, |
| { 875, 1, 187, 1, 4001, 0 }, |
| { 1458, 1, 191, 1, 4001, 0 }, |
| { 1608, 1, 191, 1, 4001, 0 }, |
| { 1758, 1, 195, 1, 4001, 0 }, |
| { 1908, 1, 195, 1, 4001, 0 }, |
| { 2050, 1, 199, 1, 4001, 0 }, |
| { 79, 1, 199, 1, 4001, 0 }, |
| { 319, 1, 203, 1, 4001, 0 }, |
| { 559, 1, 203, 1, 4001, 0 }, |
| { 745, 1, 207, 1, 4001, 0 }, |
| { 923, 1, 207, 1, 4001, 0 }, |
| { 1506, 1, 211, 1, 4001, 0 }, |
| { 1656, 1, 211, 1, 4001, 0 }, |
| { 1806, 1, 215, 1, 4001, 0 }, |
| { 1956, 1, 215, 1, 4001, 0 }, |
| { 2114, 1, 219, 1, 4001, 0 }, |
| { 146, 1, 219, 1, 4001, 0 }, |
| { 386, 1, 223, 1, 4001, 0 }, |
| { 186, 1, 1, 1, 4001, 0 }, |
| { 426, 1, 1, 1, 4001, 0 }, |
| { 618, 1, 1, 1, 4001, 0 }, |
| { 804, 1, 1, 1, 4001, 0 }, |
| { 1391, 1, 1, 1, 4001, 0 }, |
| { 1545, 1, 1, 1, 4001, 0 }, |
| { 1695, 1, 1, 1, 4001, 0 }, |
| { 1845, 1, 1, 1, 4001, 0 }, |
| { 218, 1, 1, 1, 4001, 0 }, |
| { 458, 1, 1, 1, 4001, 0 }, |
| { 647, 1, 1, 1, 4001, 0 }, |
| { 825, 1, 1, 1, 4001, 0 }, |
| { 1408, 1, 1, 1, 4001, 0 }, |
| { 1562, 1, 1, 1, 4001, 0 }, |
| { 1712, 1, 1, 1, 4001, 0 }, |
| { 1862, 1, 1, 1, 4001, 0 }, |
| { 2007, 1, 1, 1, 4001, 0 }, |
| { 2165, 1, 1, 1, 4001, 0 }, |
| { 42, 1, 1, 1, 4001, 0 }, |
| { 282, 1, 1, 1, 4001, 0 }, |
| { 522, 1, 1, 1, 4001, 0 }, |
| { 708, 1, 1, 1, 4001, 0 }, |
| { 886, 1, 1, 1, 4001, 0 }, |
| { 1469, 1, 1, 1, 4001, 0 }, |
| { 1619, 1, 1, 1, 4001, 0 }, |
| { 1769, 1, 1, 1, 4001, 0 }, |
| { 1919, 1, 1, 1, 4001, 0 }, |
| { 2061, 1, 1, 1, 4001, 0 }, |
| { 96, 1, 1, 1, 4001, 0 }, |
| { 336, 1, 1, 1, 4001, 0 }, |
| { 576, 1, 1, 1, 4001, 0 }, |
| { 762, 1, 1, 1, 4001, 0 }, |
| { 940, 1, 1, 1, 4001, 0 }, |
| { 1523, 1, 1, 1, 4001, 0 }, |
| { 1673, 1, 1, 1, 4001, 0 }, |
| { 1823, 1, 1, 1, 4001, 0 }, |
| { 1973, 1, 1, 1, 4001, 0 }, |
| { 2131, 1, 1, 1, 4001, 0 }, |
| { 163, 1, 1, 1, 4001, 0 }, |
| { 403, 1, 1, 1, 4001, 0 }, |
| { 1367, 136, 1, 0, 1184, 2 }, |
| { 197, 1, 156, 1, 3969, 0 }, |
| { 437, 1, 156, 1, 3969, 0 }, |
| { 629, 1, 156, 1, 3969, 0 }, |
| { 815, 1, 156, 1, 3969, 0 }, |
| { 1402, 1, 156, 1, 3969, 0 }, |
| { 1556, 1, 156, 1, 3969, 0 }, |
| { 1706, 1, 156, 1, 3969, 0 }, |
| { 1856, 1, 156, 1, 3969, 0 }, |
| { 2001, 1, 156, 1, 3969, 0 }, |
| { 2159, 1, 156, 1, 3969, 0 }, |
| { 35, 1, 156, 1, 3969, 0 }, |
| { 275, 1, 156, 1, 3969, 0 }, |
| { 515, 1, 156, 1, 3969, 0 }, |
| { 701, 1, 156, 1, 3969, 0 }, |
| { 879, 1, 156, 1, 3969, 0 }, |
| { 1462, 1, 156, 1, 3969, 0 }, |
| { 1612, 1, 156, 1, 3969, 0 }, |
| { 1762, 1, 156, 1, 3969, 0 }, |
| { 1912, 1, 156, 1, 3969, 0 }, |
| { 2054, 1, 156, 1, 3969, 0 }, |
| { 83, 1, 156, 1, 3969, 0 }, |
| { 323, 1, 156, 1, 3969, 0 }, |
| { 563, 1, 156, 1, 3969, 0 }, |
| { 749, 1, 156, 1, 3969, 0 }, |
| { 927, 1, 156, 1, 3969, 0 }, |
| { 1510, 1, 156, 1, 3969, 0 }, |
| { 1660, 1, 156, 1, 3969, 0 }, |
| { 1810, 1, 156, 1, 3969, 0 }, |
| { 1960, 1, 156, 1, 3969, 0 }, |
| { 2118, 1, 156, 1, 3969, 0 }, |
| { 150, 1, 156, 1, 3969, 0 }, |
| { 390, 1, 156, 1, 3969, 0 }, |
| { 1373, 128, 1, 0, 1216, 2 }, |
| { 199, 1, 234, 1, 1826, 0 }, |
| { 439, 1, 134, 1, 1826, 0 }, |
| { 631, 1, 134, 1, 1826, 0 }, |
| { 817, 1, 134, 1, 1826, 0 }, |
| { 223, 1, 1, 1, 3937, 0 }, |
| { 463, 1, 1, 1, 3937, 0 }, |
| { 652, 1, 1, 1, 3937, 0 }, |
| { 830, 1, 1, 1, 3937, 0 }, |
| { 1413, 1, 1, 1, 3937, 0 }, |
| { 1567, 1, 1, 1, 3937, 0 }, |
| { 1717, 1, 1, 1, 3937, 0 }, |
| { 1867, 1, 1, 1, 3937, 0 }, |
| { 2012, 1, 1, 1, 3937, 0 }, |
| { 2170, 1, 1, 1, 3937, 0 }, |
| { 48, 1, 1, 1, 3937, 0 }, |
| { 288, 1, 1, 1, 3937, 0 }, |
| { 528, 1, 1, 1, 3937, 0 }, |
| { 714, 1, 1, 1, 3937, 0 }, |
| { 892, 1, 1, 1, 3937, 0 }, |
| { 1475, 1, 1, 1, 3937, 0 }, |
| { 1625, 1, 1, 1, 3937, 0 }, |
| { 1775, 1, 1, 1, 3937, 0 }, |
| { 1925, 1, 1, 1, 3937, 0 }, |
| { 2067, 1, 1, 1, 3937, 0 }, |
| { 102, 1, 1, 1, 3937, 0 }, |
| { 342, 1, 1, 1, 3937, 0 }, |
| { 582, 1, 1, 1, 3937, 0 }, |
| { 768, 1, 1, 1, 3937, 0 }, |
| { 946, 1, 1, 1, 3937, 0 }, |
| { 1529, 1, 1, 1, 3937, 0 }, |
| { 1679, 1, 1, 1, 3937, 0 }, |
| { 1829, 1, 1, 1, 3937, 0 }, |
| { 1979, 1, 1, 1, 3937, 0 }, |
| { 2137, 1, 1, 1, 3937, 0 }, |
| { 169, 1, 1, 1, 3937, 0 }, |
| { 409, 1, 1, 1, 3937, 0 }, |
| { 203, 1, 100, 1, 3937, 0 }, |
| { 443, 1, 100, 1, 3937, 0 }, |
| { 211, 1, 230, 1, 1794, 0 }, |
| { 451, 1, 126, 1, 1794, 0 }, |
| { 640, 1, 126, 1, 1794, 0 }, |
| { 821, 1, 126, 1, 1794, 0 }, |
| { 206, 1, 1, 1, 3905, 0 }, |
| { 446, 1, 1, 1, 3905, 0 }, |
| { 635, 1, 1, 1, 3905, 0 }, |
| { 215, 1, 1, 1, 3905, 0 }, |
| { 455, 1, 1, 1, 3905, 0 }, |
| { 644, 1, 1, 1, 3905, 0 }, |
| { 1353, 124, 1, 0, 1248, 2 }, |
| { 228, 1, 98, 1, 3873, 0 }, |
| { 468, 1, 98, 1, 3873, 0 }, |
| { 657, 1, 98, 1, 3873, 0 }, |
| { 835, 1, 98, 1, 3873, 0 }, |
| { 1418, 1, 98, 1, 3873, 0 }, |
| { 1572, 1, 98, 1, 3873, 0 }, |
| { 1722, 1, 98, 1, 3873, 0 }, |
| { 1872, 1, 98, 1, 3873, 0 }, |
| { 1379, 122, 1, 0, 1280, 2 }, |
| { 231, 1, 96, 1, 3841, 0 }, |
| { 471, 1, 96, 1, 3841, 0 }, |
| { 660, 1, 96, 1, 3841, 0 }, |
| { 838, 1, 96, 1, 3841, 0 }, |
| { 1421, 1, 96, 1, 3841, 0 }, |
| { 1575, 1, 96, 1, 3841, 0 }, |
| { 1725, 1, 96, 1, 3841, 0 }, |
| { 1875, 1, 96, 1, 3841, 0 }, |
| { 2017, 1, 96, 1, 3841, 0 }, |
| { 2175, 1, 96, 1, 3841, 0 }, |
| { 234, 1, 96, 1, 3841, 0 }, |
| { 474, 1, 96, 1, 3841, 0 }, |
| { 237, 92, 1, 8, 1425, 10 }, |
| { 477, 92, 1, 8, 1425, 10 }, |
| { 663, 92, 1, 8, 1425, 10 }, |
| { 841, 92, 1, 8, 1425, 10 }, |
| { 1424, 92, 1, 8, 1425, 10 }, |
| { 1578, 92, 1, 8, 1425, 10 }, |
| { 1728, 92, 1, 8, 1425, 10 }, |
| { 1878, 92, 1, 8, 1425, 10 }, |
| { 2020, 92, 1, 8, 1425, 10 }, |
| { 2178, 92, 1, 8, 1425, 10 }, |
| { 54, 92, 1, 8, 1425, 10 }, |
| { 294, 92, 1, 8, 1425, 10 }, |
| { 534, 92, 1, 8, 1425, 10 }, |
| { 720, 92, 1, 8, 1425, 10 }, |
| { 898, 92, 1, 8, 1425, 10 }, |
| { 1481, 92, 1, 8, 1425, 10 }, |
| { 1631, 92, 1, 8, 1425, 10 }, |
| { 1781, 92, 1, 8, 1425, 10 }, |
| { 1931, 92, 1, 8, 1425, 10 }, |
| { 2073, 92, 1, 8, 1425, 10 }, |
| { 108, 92, 1, 8, 1425, 10 }, |
| { 348, 92, 1, 8, 1425, 10 }, |
| { 588, 92, 1, 8, 1425, 10 }, |
| { 774, 92, 1, 8, 1425, 10 }, |
| { 952, 92, 1, 8, 1425, 10 }, |
| { 1535, 92, 1, 8, 1425, 10 }, |
| { 1685, 92, 1, 8, 1425, 10 }, |
| { 1835, 92, 1, 8, 1425, 10 }, |
| { 1985, 92, 1, 8, 1425, 10 }, |
| { 2143, 92, 1, 8, 1425, 10 }, |
| { 175, 92, 1, 8, 1425, 10 }, |
| { 415, 92, 1, 8, 1425, 10 }, |
| { 1359, 118, 1, 0, 1921, 2 }, |
| { 983, 118, 1, 0, 1921, 2 }, |
| { 1061, 118, 1, 0, 1921, 2 }, |
| { 1111, 118, 1, 0, 1921, 2 }, |
| { 1149, 118, 1, 0, 1921, 2 }, |
| { 989, 130, 1, 12, 656, 10 }, |
| { 996, 93, 157, 9, 1377, 10 }, |
| { 1067, 93, 157, 9, 1377, 10 }, |
| { 1117, 93, 157, 9, 1377, 10 }, |
| { 1155, 93, 157, 9, 1377, 10 }, |
| { 1187, 93, 157, 9, 1377, 10 }, |
| { 1219, 93, 157, 9, 1377, 10 }, |
| { 1251, 93, 157, 9, 1377, 10 }, |
| { 1283, 93, 157, 9, 1377, 10 }, |
| { 1315, 93, 157, 9, 1377, 10 }, |
| { 1341, 93, 157, 9, 1377, 10 }, |
| { 962, 93, 157, 9, 1377, 10 }, |
| { 1040, 93, 157, 9, 1377, 10 }, |
| { 1097, 93, 157, 9, 1377, 10 }, |
| { 1135, 93, 157, 9, 1377, 10 }, |
| { 1173, 93, 157, 9, 1377, 10 }, |
| { 1205, 93, 157, 9, 1377, 10 }, |
| { 1237, 93, 157, 9, 1377, 10 }, |
| { 1269, 93, 157, 9, 1377, 10 }, |
| { 1301, 93, 157, 9, 1377, 10 }, |
| { 1327, 93, 157, 9, 1377, 10 }, |
| { 969, 93, 157, 9, 1377, 10 }, |
| { 1047, 93, 157, 9, 1377, 10 }, |
| { 1104, 93, 157, 9, 1377, 10 }, |
| { 1142, 93, 157, 9, 1377, 10 }, |
| { 1180, 93, 157, 9, 1377, 10 }, |
| { 1212, 93, 157, 9, 1377, 10 }, |
| { 1244, 93, 157, 9, 1377, 10 }, |
| { 1276, 93, 157, 9, 1377, 10 }, |
| { 1308, 93, 157, 9, 1377, 10 }, |
| { 1334, 93, 157, 9, 1377, 10 }, |
| { 976, 93, 157, 9, 1377, 10 }, |
| { 1054, 93, 157, 9, 1377, 10 }, |
| { 2077, 1, 116, 1, 1120, 0 }, |
| { 1002, 138, 236, 0, 1344, 2 }, |
| { 1009, 150, 1, 0, 2337, 2 }, |
| { 1073, 150, 1, 0, 2337, 2 }, |
| { 1015, 150, 232, 0, 1312, 2 }, |
| { 1022, 152, 1, 0, 2369, 2 }, |
| { 1079, 152, 1, 0, 2369, 2 }, |
| { 1123, 152, 1, 0, 2369, 2 }, |
| { 1161, 152, 1, 0, 2369, 2 }, |
| { 1193, 152, 1, 0, 2369, 2 }, |
| { 1225, 152, 1, 0, 2369, 2 }, |
| { 1257, 152, 1, 0, 2369, 2 }, |
| { 1289, 152, 1, 0, 2369, 2 }, |
| { 1028, 154, 1, 0, 2369, 2 }, |
| { 1085, 154, 1, 0, 2369, 2 }, |
| { 1129, 154, 1, 0, 2369, 2 }, |
| { 1167, 154, 1, 0, 2369, 2 }, |
| { 1199, 154, 1, 0, 2369, 2 }, |
| { 1231, 154, 1, 0, 2369, 2 }, |
| { 1263, 154, 1, 0, 2369, 2 }, |
| { 1295, 154, 1, 0, 2369, 2 }, |
| { 1321, 154, 1, 0, 2369, 2 }, |
| { 1347, 154, 1, 0, 2369, 2 }, |
| { 1034, 154, 1, 0, 2369, 2 }, |
| { 1091, 154, 1, 0, 2369, 2 }, |
| }; |
| |
| extern const MCPhysReg MipsRegUnitRoots[][2] = { |
| { Mips::AT }, |
| { Mips::DSPCCond }, |
| { Mips::DSPCarry }, |
| { Mips::DSPEFI }, |
| { Mips::DSPOutFlag16_19 }, |
| { Mips::DSPOutFlag20 }, |
| { Mips::DSPOutFlag21 }, |
| { Mips::DSPOutFlag22 }, |
| { Mips::DSPOutFlag23 }, |
| { Mips::DSPPos }, |
| { Mips::DSPSCount }, |
| { Mips::FP }, |
| { Mips::GP }, |
| { Mips::MSAAccess }, |
| { Mips::MSACSR }, |
| { Mips::MSAIR }, |
| { Mips::MSAMap }, |
| { Mips::MSAModify }, |
| { Mips::MSARequest }, |
| { Mips::MSASave }, |
| { Mips::MSAUnmap }, |
| { Mips::PC }, |
| { Mips::RA }, |
| { Mips::SP }, |
| { Mips::ZERO }, |
| { Mips::A0 }, |
| { Mips::A1 }, |
| { Mips::A2 }, |
| { Mips::A3 }, |
| { Mips::LO0 }, |
| { Mips::HI0 }, |
| { Mips::LO1 }, |
| { Mips::HI1 }, |
| { Mips::LO2 }, |
| { Mips::HI2 }, |
| { Mips::LO3 }, |
| { Mips::HI3 }, |
| { Mips::COP00 }, |
| { Mips::COP01 }, |
| { Mips::COP02 }, |
| { Mips::COP03 }, |
| { Mips::COP04 }, |
| { Mips::COP05 }, |
| { Mips::COP06 }, |
| { Mips::COP07 }, |
| { Mips::COP08 }, |
| { Mips::COP09 }, |
| { Mips::COP20 }, |
| { Mips::COP21 }, |
| { Mips::COP22 }, |
| { Mips::COP23 }, |
| { Mips::COP24 }, |
| { Mips::COP25 }, |
| { Mips::COP26 }, |
| { Mips::COP27 }, |
| { Mips::COP28 }, |
| { Mips::COP29 }, |
| { Mips::COP30 }, |
| { Mips::COP31 }, |
| { Mips::COP32 }, |
| { Mips::COP33 }, |
| { Mips::COP34 }, |
| { Mips::COP35 }, |
| { Mips::COP36 }, |
| { Mips::COP37 }, |
| { Mips::COP38 }, |
| { Mips::COP39 }, |
| { Mips::COP010 }, |
| { Mips::COP011 }, |
| { Mips::COP012 }, |
| { Mips::COP013 }, |
| { Mips::COP014 }, |
| { Mips::COP015 }, |
| { Mips::COP016 }, |
| { Mips::COP017 }, |
| { Mips::COP018 }, |
| { Mips::COP019 }, |
| { Mips::COP020 }, |
| { Mips::COP021 }, |
| { Mips::COP022 }, |
| { Mips::COP023 }, |
| { Mips::COP024 }, |
| { Mips::COP025 }, |
| { Mips::COP026 }, |
| { Mips::COP027 }, |
| { Mips::COP028 }, |
| { Mips::COP029 }, |
| { Mips::COP030 }, |
| { Mips::COP031 }, |
| { Mips::COP210 }, |
| { Mips::COP211 }, |
| { Mips::COP212 }, |
| { Mips::COP213 }, |
| { Mips::COP214 }, |
| { Mips::COP215 }, |
| { Mips::COP216 }, |
| { Mips::COP217 }, |
| { Mips::COP218 }, |
| { Mips::COP219 }, |
| { Mips::COP220 }, |
| { Mips::COP221 }, |
| { Mips::COP222 }, |
| { Mips::COP223 }, |
| { Mips::COP224 }, |
| { Mips::COP225 }, |
| { Mips::COP226 }, |
| { Mips::COP227 }, |
| { Mips::COP228 }, |
| { Mips::COP229 }, |
| { Mips::COP230 }, |
| { Mips::COP231 }, |
| { Mips::COP310 }, |
| { Mips::COP311 }, |
| { Mips::COP312 }, |
| { Mips::COP313 }, |
| { Mips::COP314 }, |
| { Mips::COP315 }, |
| { Mips::COP316 }, |
| { Mips::COP317 }, |
| { Mips::COP318 }, |
| { Mips::COP319 }, |
| { Mips::COP320 }, |
| { Mips::COP321 }, |
| { Mips::COP322 }, |
| { Mips::COP323 }, |
| { Mips::COP324 }, |
| { Mips::COP325 }, |
| { Mips::COP326 }, |
| { Mips::COP327 }, |
| { Mips::COP328 }, |
| { Mips::COP329 }, |
| { Mips::COP330 }, |
| { Mips::COP331 }, |
| { Mips::F0 }, |
| { Mips::F1 }, |
| { Mips::F2 }, |
| { Mips::F3 }, |
| { Mips::F4 }, |
| { Mips::F5 }, |
| { Mips::F6 }, |
| { Mips::F7 }, |
| { Mips::F8 }, |
| { Mips::F9 }, |
| { Mips::F10 }, |
| { Mips::F11 }, |
| { Mips::F12 }, |
| { Mips::F13 }, |
| { Mips::F14 }, |
| { Mips::F15 }, |
| { Mips::F16 }, |
| { Mips::F17 }, |
| { Mips::F18 }, |
| { Mips::F19 }, |
| { Mips::F20 }, |
| { Mips::F21 }, |
| { Mips::F22 }, |
| { Mips::F23 }, |
| { Mips::F24 }, |
| { Mips::F25 }, |
| { Mips::F26 }, |
| { Mips::F27 }, |
| { Mips::F28 }, |
| { Mips::F29 }, |
| { Mips::F30 }, |
| { Mips::F31 }, |
| { Mips::FCC0 }, |
| { Mips::FCC1 }, |
| { Mips::FCC2 }, |
| { Mips::FCC3 }, |
| { Mips::FCC4 }, |
| { Mips::FCC5 }, |
| { Mips::FCC6 }, |
| { Mips::FCC7 }, |
| { Mips::FCR0 }, |
| { Mips::FCR1 }, |
| { Mips::FCR2 }, |
| { Mips::FCR3 }, |
| { Mips::FCR4 }, |
| { Mips::FCR5 }, |
| { Mips::FCR6 }, |
| { Mips::FCR7 }, |
| { Mips::FCR8 }, |
| { Mips::FCR9 }, |
| { Mips::FCR10 }, |
| { Mips::FCR11 }, |
| { Mips::FCR12 }, |
| { Mips::FCR13 }, |
| { Mips::FCR14 }, |
| { Mips::FCR15 }, |
| { Mips::FCR16 }, |
| { Mips::FCR17 }, |
| { Mips::FCR18 }, |
| { Mips::FCR19 }, |
| { Mips::FCR20 }, |
| { Mips::FCR21 }, |
| { Mips::FCR22 }, |
| { Mips::FCR23 }, |
| { Mips::FCR24 }, |
| { Mips::FCR25 }, |
| { Mips::FCR26 }, |
| { Mips::FCR27 }, |
| { Mips::FCR28 }, |
| { Mips::FCR29 }, |
| { Mips::FCR30 }, |
| { Mips::FCR31 }, |
| { Mips::F_HI0 }, |
| { Mips::F_HI1 }, |
| { Mips::F_HI2 }, |
| { Mips::F_HI3 }, |
| { Mips::F_HI4 }, |
| { Mips::F_HI5 }, |
| { Mips::F_HI6 }, |
| { Mips::F_HI7 }, |
| { Mips::F_HI8 }, |
| { Mips::F_HI9 }, |
| { Mips::F_HI10 }, |
| { Mips::F_HI11 }, |
| { Mips::F_HI12 }, |
| { Mips::F_HI13 }, |
| { Mips::F_HI14 }, |
| { Mips::F_HI15 }, |
| { Mips::F_HI16 }, |
| { Mips::F_HI17 }, |
| { Mips::F_HI18 }, |
| { Mips::F_HI19 }, |
| { Mips::F_HI20 }, |
| { Mips::F_HI21 }, |
| { Mips::F_HI22 }, |
| { Mips::F_HI23 }, |
| { Mips::F_HI24 }, |
| { Mips::F_HI25 }, |
| { Mips::F_HI26 }, |
| { Mips::F_HI27 }, |
| { Mips::F_HI28 }, |
| { Mips::F_HI29 }, |
| { Mips::F_HI30 }, |
| { Mips::F_HI31 }, |
| { Mips::HWR0 }, |
| { Mips::HWR1 }, |
| { Mips::HWR2 }, |
| { Mips::HWR3 }, |
| { Mips::HWR4 }, |
| { Mips::HWR5 }, |
| { Mips::HWR6 }, |
| { Mips::HWR7 }, |
| { Mips::HWR8 }, |
| { Mips::HWR9 }, |
| { Mips::HWR10 }, |
| { Mips::HWR11 }, |
| { Mips::HWR12 }, |
| { Mips::HWR13 }, |
| { Mips::HWR14 }, |
| { Mips::HWR15 }, |
| { Mips::HWR16 }, |
| { Mips::HWR17 }, |
| { Mips::HWR18 }, |
| { Mips::HWR19 }, |
| { Mips::HWR20 }, |
| { Mips::HWR21 }, |
| { Mips::HWR22 }, |
| { Mips::HWR23 }, |
| { Mips::HWR24 }, |
| { Mips::HWR25 }, |
| { Mips::HWR26 }, |
| { Mips::HWR27 }, |
| { Mips::HWR28 }, |
| { Mips::HWR29 }, |
| { Mips::HWR30 }, |
| { Mips::HWR31 }, |
| { Mips::K0 }, |
| { Mips::K1 }, |
| { Mips::MPL0 }, |
| { Mips::MPL1 }, |
| { Mips::MPL2 }, |
| { Mips::P0 }, |
| { Mips::P1 }, |
| { Mips::P2 }, |
| { Mips::S0 }, |
| { Mips::S1 }, |
| { Mips::S2 }, |
| { Mips::S3 }, |
| { Mips::S4 }, |
| { Mips::S5 }, |
| { Mips::S6 }, |
| { Mips::S7 }, |
| { Mips::T0 }, |
| { Mips::T1 }, |
| { Mips::T2 }, |
| { Mips::T3 }, |
| { Mips::T4 }, |
| { Mips::T5 }, |
| { Mips::T6 }, |
| { Mips::T7 }, |
| { Mips::T8 }, |
| { Mips::T9 }, |
| { Mips::V0 }, |
| { Mips::V1 }, |
| }; |
| |
| namespace { // Register classes... |
| // MSA128F16 Register Class... |
| const MCPhysReg MSA128F16[] = { |
| Mips::W0, Mips::W1, Mips::W2, Mips::W3, Mips::W4, Mips::W5, Mips::W6, Mips::W7, Mips::W8, Mips::W9, Mips::W10, Mips::W11, Mips::W12, Mips::W13, Mips::W14, Mips::W15, Mips::W16, Mips::W17, Mips::W18, Mips::W19, Mips::W20, Mips::W21, Mips::W22, Mips::W23, Mips::W24, Mips::W25, Mips::W26, Mips::W27, Mips::W28, Mips::W29, Mips::W30, Mips::W31, |
| }; |
| |
| // MSA128F16 Bit set. |
| const uint8_t MSA128F16Bits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, |
| }; |
| |
| // MSA128F16_with_sub_64_in_OddSP Register Class... |
| const MCPhysReg MSA128F16_with_sub_64_in_OddSP[] = { |
| Mips::W1, Mips::W3, Mips::W5, Mips::W7, Mips::W9, Mips::W11, Mips::W13, Mips::W15, Mips::W17, Mips::W19, Mips::W21, Mips::W23, Mips::W25, Mips::W27, Mips::W29, Mips::W31, |
| }; |
| |
| // MSA128F16_with_sub_64_in_OddSP Bit set. |
| const uint8_t MSA128F16_with_sub_64_in_OddSPBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x55, 0x55, 0x55, 0x05, |
| }; |
| |
| // OddSP Register Class... |
| const MCPhysReg OddSP[] = { |
| Mips::F1, Mips::F3, Mips::F5, Mips::F7, Mips::F9, Mips::F11, Mips::F13, Mips::F15, Mips::F17, Mips::F19, Mips::F21, Mips::F23, Mips::F25, Mips::F27, Mips::F29, Mips::F31, Mips::F_HI1, Mips::F_HI3, Mips::F_HI5, Mips::F_HI7, Mips::F_HI9, Mips::F_HI11, Mips::F_HI13, Mips::F_HI15, Mips::F_HI17, Mips::F_HI19, Mips::F_HI21, Mips::F_HI23, Mips::F_HI25, Mips::F_HI27, Mips::F_HI29, Mips::F_HI31, Mips::D1, Mips::D3, Mips::D5, Mips::D7, Mips::D9, Mips::D11, Mips::D13, Mips::D15, Mips::D1_64, Mips::D3_64, Mips::D5_64, Mips::D7_64, Mips::D9_64, Mips::D11_64, Mips::D13_64, Mips::D15_64, Mips::D17_64, Mips::D19_64, Mips::D21_64, Mips::D23_64, Mips::D25_64, Mips::D27_64, Mips::D29_64, Mips::D31_64, |
| }; |
| |
| // OddSP Bit set. |
| const uint8_t OddSPBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, 0x50, 0x55, 0x55, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0xa0, 0xaa, 0xaa, 0xaa, 0x0a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x55, 0x55, 0x01, |
| }; |
| |
| // CCR Register Class... |
| const MCPhysReg CCR[] = { |
| Mips::FCR0, Mips::FCR1, Mips::FCR2, Mips::FCR3, Mips::FCR4, Mips::FCR5, Mips::FCR6, Mips::FCR7, Mips::FCR8, Mips::FCR9, Mips::FCR10, Mips::FCR11, Mips::FCR12, Mips::FCR13, Mips::FCR14, Mips::FCR15, Mips::FCR16, Mips::FCR17, Mips::FCR18, Mips::FCR19, Mips::FCR20, Mips::FCR21, Mips::FCR22, Mips::FCR23, Mips::FCR24, Mips::FCR25, Mips::FCR26, Mips::FCR27, Mips::FCR28, Mips::FCR29, Mips::FCR30, Mips::FCR31, |
| }; |
| |
| // CCR Bit set. |
| const uint8_t CCRBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, |
| }; |
| |
| // COP0 Register Class... |
| const MCPhysReg COP0[] = { |
| Mips::COP00, Mips::COP01, Mips::COP02, Mips::COP03, Mips::COP04, Mips::COP05, Mips::COP06, Mips::COP07, Mips::COP08, Mips::COP09, Mips::COP010, Mips::COP011, Mips::COP012, Mips::COP013, Mips::COP014, Mips::COP015, Mips::COP016, Mips::COP017, Mips::COP018, Mips::COP019, Mips::COP020, Mips::COP021, Mips::COP022, Mips::COP023, Mips::COP024, Mips::COP025, Mips::COP026, Mips::COP027, Mips::COP028, Mips::COP029, Mips::COP030, Mips::COP031, |
| }; |
| |
| // COP0 Bit set. |
| const uint8_t COP0Bits[] = { |
| 0x00, 0x00, 0x00, 0x80, 0xff, 0x01, 0x00, 0xe0, 0xff, 0xff, 0x07, |
| }; |
| |
| // COP2 Register Class... |
| const MCPhysReg COP2[] = { |
| Mips::COP20, Mips::COP21, Mips::COP22, Mips::COP23, Mips::COP24, Mips::COP25, Mips::COP26, Mips::COP27, Mips::COP28, Mips::COP29, Mips::COP210, Mips::COP211, Mips::COP212, Mips::COP213, Mips::COP214, Mips::COP215, Mips::COP216, Mips::COP217, Mips::COP218, Mips::COP219, Mips::COP220, Mips::COP221, Mips::COP222, Mips::COP223, Mips::COP224, Mips::COP225, Mips::COP226, Mips::COP227, Mips::COP228, Mips::COP229, Mips::COP230, Mips::COP231, |
| }; |
| |
| // COP2 Bit set. |
| const uint8_t COP2Bits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x07, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0x01, |
| }; |
| |
| // COP3 Register Class... |
| const MCPhysReg COP3[] = { |
| Mips::COP30, Mips::COP31, Mips::COP32, Mips::COP33, Mips::COP34, Mips::COP35, Mips::COP36, Mips::COP37, Mips::COP38, Mips::COP39, Mips::COP310, Mips::COP311, Mips::COP312, Mips::COP313, Mips::COP314, Mips::COP315, Mips::COP316, Mips::COP317, Mips::COP318, Mips::COP319, Mips::COP320, Mips::COP321, Mips::COP322, Mips::COP323, Mips::COP324, Mips::COP325, Mips::COP326, Mips::COP327, Mips::COP328, Mips::COP329, Mips::COP330, Mips::COP331, |
| }; |
| |
| // COP3 Bit set. |
| const uint8_t COP3Bits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0x7f, |
| }; |
| |
| // DSPR Register Class... |
| const MCPhysReg DSPR[] = { |
| Mips::ZERO, Mips::AT, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::T0, Mips::T1, Mips::T2, Mips::T3, Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7, Mips::T8, Mips::T9, Mips::K0, Mips::K1, Mips::GP, Mips::SP, Mips::FP, Mips::RA, |
| }; |
| |
| // DSPR Bit set. |
| const uint8_t DSPRBits[] = { |
| 0x02, 0x03, 0xf8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0xc0, 0xbf, 0xff, 0x07, |
| }; |
| |
| // FGR32 Register Class... |
| const MCPhysReg FGR32[] = { |
| Mips::F0, Mips::F1, Mips::F2, Mips::F3, Mips::F4, Mips::F5, Mips::F6, Mips::F7, Mips::F8, Mips::F9, Mips::F10, Mips::F11, Mips::F12, Mips::F13, Mips::F14, Mips::F15, Mips::F16, Mips::F17, Mips::F18, Mips::F19, Mips::F20, Mips::F21, Mips::F22, Mips::F23, Mips::F24, Mips::F25, Mips::F26, Mips::F27, Mips::F28, Mips::F29, Mips::F30, Mips::F31, |
| }; |
| |
| // FGR32 Bit set. |
| const uint8_t FGR32Bits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, |
| }; |
| |
| // FGRCC Register Class... |
| const MCPhysReg FGRCC[] = { |
| Mips::F0, Mips::F1, Mips::F2, Mips::F3, Mips::F4, Mips::F5, Mips::F6, Mips::F7, Mips::F8, Mips::F9, Mips::F10, Mips::F11, Mips::F12, Mips::F13, Mips::F14, Mips::F15, Mips::F16, Mips::F17, Mips::F18, Mips::F19, Mips::F20, Mips::F21, Mips::F22, Mips::F23, Mips::F24, Mips::F25, Mips::F26, Mips::F27, Mips::F28, Mips::F29, Mips::F30, Mips::F31, |
| }; |
| |
| // FGRCC Bit set. |
| const uint8_t FGRCCBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, |
| }; |
| |
| // FGRH32 Register Class... |
| const MCPhysReg FGRH32[] = { |
| Mips::F_HI0, Mips::F_HI1, Mips::F_HI2, Mips::F_HI3, Mips::F_HI4, Mips::F_HI5, Mips::F_HI6, Mips::F_HI7, Mips::F_HI8, Mips::F_HI9, Mips::F_HI10, Mips::F_HI11, Mips::F_HI12, Mips::F_HI13, Mips::F_HI14, Mips::F_HI15, Mips::F_HI16, Mips::F_HI17, Mips::F_HI18, Mips::F_HI19, Mips::F_HI20, Mips::F_HI21, Mips::F_HI22, Mips::F_HI23, Mips::F_HI24, Mips::F_HI25, Mips::F_HI26, Mips::F_HI27, Mips::F_HI28, Mips::F_HI29, Mips::F_HI30, Mips::F_HI31, |
| }; |
| |
| // FGRH32 Bit set. |
| const uint8_t FGRH32Bits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f, |
| }; |
| |
| // GPR32 Register Class... |
| const MCPhysReg GPR32[] = { |
| Mips::ZERO, Mips::AT, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::T0, Mips::T1, Mips::T2, Mips::T3, Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7, Mips::T8, Mips::T9, Mips::K0, Mips::K1, Mips::GP, Mips::SP, Mips::FP, Mips::RA, |
| }; |
| |
| // GPR32 Bit set. |
| const uint8_t GPR32Bits[] = { |
| 0x02, 0x03, 0xf8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0xc0, 0xbf, 0xff, 0x07, |
| }; |
| |
| // HWRegs Register Class... |
| const MCPhysReg HWRegs[] = { |
| Mips::HWR0, Mips::HWR1, Mips::HWR2, Mips::HWR3, Mips::HWR4, Mips::HWR5, Mips::HWR6, Mips::HWR7, Mips::HWR8, Mips::HWR9, Mips::HWR10, Mips::HWR11, Mips::HWR12, Mips::HWR13, Mips::HWR14, Mips::HWR15, Mips::HWR16, Mips::HWR17, Mips::HWR18, Mips::HWR19, Mips::HWR20, Mips::HWR21, Mips::HWR22, Mips::HWR23, Mips::HWR24, Mips::HWR25, Mips::HWR26, Mips::HWR27, Mips::HWR28, Mips::HWR29, Mips::HWR30, Mips::HWR31, |
| }; |
| |
| // HWRegs Bit set. |
| const uint8_t HWRegsBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, |
| }; |
| |
| // GPR32NONZERO Register Class... |
| const MCPhysReg GPR32NONZERO[] = { |
| Mips::AT, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::T0, Mips::T1, Mips::T2, Mips::T3, Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7, Mips::T8, Mips::T9, Mips::K0, Mips::K1, Mips::GP, Mips::SP, Mips::FP, Mips::RA, |
| }; |
| |
| // GPR32NONZERO Bit set. |
| const uint8_t GPR32NONZEROBits[] = { |
| 0x02, 0x03, 0xd8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0xc0, 0xbf, 0xff, 0x07, |
| }; |
| |
| // OddSP_with_sub_hi Register Class... |
| const MCPhysReg OddSP_with_sub_hi[] = { |
| Mips::D1, Mips::D3, Mips::D5, Mips::D7, Mips::D9, Mips::D11, Mips::D13, Mips::D15, Mips::D1_64, Mips::D3_64, Mips::D5_64, Mips::D7_64, Mips::D9_64, Mips::D11_64, Mips::D13_64, Mips::D15_64, Mips::D17_64, Mips::D19_64, Mips::D21_64, Mips::D23_64, Mips::D25_64, Mips::D27_64, Mips::D29_64, Mips::D31_64, |
| }; |
| |
| // OddSP_with_sub_hi Bit set. |
| const uint8_t OddSP_with_sub_hiBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x55, 0x55, 0x01, |
| }; |
| |
| // FGR32_and_OddSP Register Class... |
| const MCPhysReg FGR32_and_OddSP[] = { |
| Mips::F1, Mips::F3, Mips::F5, Mips::F7, Mips::F9, Mips::F11, Mips::F13, Mips::F15, Mips::F17, Mips::F19, Mips::F21, Mips::F23, Mips::F25, Mips::F27, Mips::F29, Mips::F31, |
| }; |
| |
| // FGR32_and_OddSP Bit set. |
| const uint8_t FGR32_and_OddSPBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x55, 0x55, 0x55, 0x05, |
| }; |
| |
| // FGRH32_and_OddSP Register Class... |
| const MCPhysReg FGRH32_and_OddSP[] = { |
| Mips::F_HI1, Mips::F_HI3, Mips::F_HI5, Mips::F_HI7, Mips::F_HI9, Mips::F_HI11, Mips::F_HI13, Mips::F_HI15, Mips::F_HI17, Mips::F_HI19, Mips::F_HI21, Mips::F_HI23, Mips::F_HI25, Mips::F_HI27, Mips::F_HI29, Mips::F_HI31, |
| }; |
| |
| // FGRH32_and_OddSP Bit set. |
| const uint8_t FGRH32_and_OddSPBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa0, 0xaa, 0xaa, 0xaa, 0x0a, |
| }; |
| |
| // OddSP_with_sub_hi_with_sub_hi_in_FGRH32 Register Class... |
| const MCPhysReg OddSP_with_sub_hi_with_sub_hi_in_FGRH32[] = { |
| Mips::D1_64, Mips::D3_64, Mips::D5_64, Mips::D7_64, Mips::D9_64, Mips::D11_64, Mips::D13_64, Mips::D15_64, Mips::D17_64, Mips::D19_64, Mips::D21_64, Mips::D23_64, Mips::D25_64, Mips::D27_64, Mips::D29_64, Mips::D31_64, |
| }; |
| |
| // OddSP_with_sub_hi_with_sub_hi_in_FGRH32 Bit set. |
| const uint8_t OddSP_with_sub_hi_with_sub_hi_in_FGRH32Bits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x55, 0x55, 0x01, |
| }; |
| |
| // CPU16RegsPlusSP Register Class... |
| const MCPhysReg CPU16RegsPlusSP[] = { |
| Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::S0, Mips::S1, Mips::SP, |
| }; |
| |
| // CPU16RegsPlusSP Bit set. |
| const uint8_t CPU16RegsPlusSPBits[] = { |
| 0x00, 0x00, 0xd0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06, |
| }; |
| |
| // CPU16Regs Register Class... |
| const MCPhysReg CPU16Regs[] = { |
| Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::S0, Mips::S1, |
| }; |
| |
| // CPU16Regs Bit set. |
| const uint8_t CPU16RegsBits[] = { |
| 0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06, |
| }; |
| |
| // FCC Register Class... |
| const MCPhysReg FCC[] = { |
| Mips::FCC0, Mips::FCC1, Mips::FCC2, Mips::FCC3, Mips::FCC4, Mips::FCC5, Mips::FCC6, Mips::FCC7, |
| }; |
| |
| // FCC Bit set. |
| const uint8_t FCCBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07, |
| }; |
| |
| // GPRMM16 Register Class... |
| const MCPhysReg GPRMM16[] = { |
| Mips::S0, Mips::S1, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, |
| }; |
| |
| // GPRMM16 Bit set. |
| const uint8_t GPRMM16Bits[] = { |
| 0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06, |
| }; |
| |
| // GPRMM16MoveP Register Class... |
| const MCPhysReg GPRMM16MoveP[] = { |
| Mips::ZERO, Mips::S1, Mips::V0, Mips::V1, Mips::S0, Mips::S2, Mips::S3, Mips::S4, |
| }; |
| |
| // GPRMM16MoveP Bit set. |
| const uint8_t GPRMM16MovePBits[] = { |
| 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x06, |
| }; |
| |
| // GPRMM16Zero Register Class... |
| const MCPhysReg GPRMM16Zero[] = { |
| Mips::ZERO, Mips::S1, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, |
| }; |
| |
| // GPRMM16Zero Bit set. |
| const uint8_t GPRMM16ZeroBits[] = { |
| 0x00, 0x00, 0xe0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06, |
| }; |
| |
| // MSACtrl Register Class... |
| const MCPhysReg MSACtrl[] = { |
| Mips::MSAIR, Mips::MSACSR, Mips::MSAAccess, Mips::MSASave, Mips::MSAModify, Mips::MSARequest, Mips::MSAMap, Mips::MSAUnmap, |
| }; |
| |
| // MSACtrl Bit set. |
| const uint8_t MSACtrlBits[] = { |
| 0x00, 0xfc, 0x03, |
| }; |
| |
| // OddSP_with_sub_hi_with_sub_hi_in_FGR32 Register Class... |
| const MCPhysReg OddSP_with_sub_hi_with_sub_hi_in_FGR32[] = { |
| Mips::D1, Mips::D3, Mips::D5, Mips::D7, Mips::D9, Mips::D11, Mips::D13, Mips::D15, |
| }; |
| |
| // OddSP_with_sub_hi_with_sub_hi_in_FGR32 Bit set. |
| const uint8_t OddSP_with_sub_hi_with_sub_hi_in_FGR32Bits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, |
| }; |
| |
| // CPU16Regs_and_GPRMM16Zero Register Class... |
| const MCPhysReg CPU16Regs_and_GPRMM16Zero[] = { |
| Mips::S1, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, |
| }; |
| |
| // CPU16Regs_and_GPRMM16Zero Bit set. |
| const uint8_t CPU16Regs_and_GPRMM16ZeroBits[] = { |
| 0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06, |
| }; |
| |
| // GPR32NONZERO_and_GPRMM16MoveP Register Class... |
| const MCPhysReg GPR32NONZERO_and_GPRMM16MoveP[] = { |
| Mips::S1, Mips::V0, Mips::V1, Mips::S0, Mips::S2, Mips::S3, Mips::S4, |
| }; |
| |
| // GPR32NONZERO_and_GPRMM16MoveP Bit set. |
| const uint8_t GPR32NONZERO_and_GPRMM16MovePBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x06, |
| }; |
| |
| // CPU16Regs_and_GPRMM16MoveP Register Class... |
| const MCPhysReg CPU16Regs_and_GPRMM16MoveP[] = { |
| Mips::S1, Mips::V0, Mips::V1, Mips::S0, |
| }; |
| |
| // CPU16Regs_and_GPRMM16MoveP Bit set. |
| const uint8_t CPU16Regs_and_GPRMM16MovePBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06, |
| }; |
| |
| // GPRMM16MoveP_and_GPRMM16Zero Register Class... |
| const MCPhysReg GPRMM16MoveP_and_GPRMM16Zero[] = { |
| Mips::ZERO, Mips::S1, Mips::V0, Mips::V1, |
| }; |
| |
| // GPRMM16MoveP_and_GPRMM16Zero Bit set. |
| const uint8_t GPRMM16MoveP_and_GPRMM16ZeroBits[] = { |
| 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06, |
| }; |
| |
| // HI32DSP Register Class... |
| const MCPhysReg HI32DSP[] = { |
| Mips::HI0, Mips::HI1, Mips::HI2, Mips::HI3, |
| }; |
| |
| // HI32DSP Bit set. |
| const uint8_t HI32DSPBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01, |
| }; |
| |
| // LO32DSP Register Class... |
| const MCPhysReg LO32DSP[] = { |
| Mips::LO0, Mips::LO1, Mips::LO2, Mips::LO3, |
| }; |
| |
| // LO32DSP Bit set. |
| const uint8_t LO32DSPBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, |
| }; |
| |
| // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Register Class... |
| const MCPhysReg GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero[] = { |
| Mips::S1, Mips::V0, Mips::V1, |
| }; |
| |
| // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Bit set. |
| const uint8_t GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06, |
| }; |
| |
| // CPURAReg Register Class... |
| const MCPhysReg CPURAReg[] = { |
| Mips::RA, |
| }; |
| |
| // CPURAReg Bit set. |
| const uint8_t CPURARegBits[] = { |
| 0x00, 0x00, 0x08, |
| }; |
| |
| // CPUSPReg Register Class... |
| const MCPhysReg CPUSPReg[] = { |
| Mips::SP, |
| }; |
| |
| // CPUSPReg Bit set. |
| const uint8_t CPUSPRegBits[] = { |
| 0x00, 0x00, 0x10, |
| }; |
| |
| // DSPCC Register Class... |
| const MCPhysReg DSPCC[] = { |
| Mips::DSPCCond, |
| }; |
| |
| // DSPCC Bit set. |
| const uint8_t DSPCCBits[] = { |
| 0x04, |
| }; |
| |
| // GP32 Register Class... |
| const MCPhysReg GP32[] = { |
| Mips::GP, |
| }; |
| |
| // GP32 Bit set. |
| const uint8_t GP32Bits[] = { |
| 0x00, 0x02, |
| }; |
| |
| // GPR32ZERO Register Class... |
| const MCPhysReg GPR32ZERO[] = { |
| Mips::ZERO, |
| }; |
| |
| // GPR32ZERO Bit set. |
| const uint8_t GPR32ZEROBits[] = { |
| 0x00, 0x00, 0x20, |
| }; |
| |
| // HI32 Register Class... |
| const MCPhysReg HI32[] = { |
| Mips::HI0, |
| }; |
| |
| // HI32 Bit set. |
| const uint8_t HI32Bits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, |
| }; |
| |
| // LO32 Register Class... |
| const MCPhysReg LO32[] = { |
| Mips::LO0, |
| }; |
| |
| // LO32 Bit set. |
| const uint8_t LO32Bits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, |
| }; |
| |
| // SP32 Register Class... |
| const MCPhysReg SP32[] = { |
| Mips::SP, |
| }; |
| |
| // SP32 Bit set. |
| const uint8_t SP32Bits[] = { |
| 0x00, 0x00, 0x10, |
| }; |
| |
| // FGR64 Register Class... |
| const MCPhysReg FGR64[] = { |
| Mips::D0_64, Mips::D1_64, Mips::D2_64, Mips::D3_64, Mips::D4_64, Mips::D5_64, Mips::D6_64, Mips::D7_64, Mips::D8_64, Mips::D9_64, Mips::D10_64, Mips::D11_64, Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64, Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64, Mips::D20_64, Mips::D21_64, Mips::D22_64, Mips::D23_64, Mips::D24_64, Mips::D25_64, Mips::D26_64, Mips::D27_64, Mips::D28_64, Mips::D29_64, Mips::D30_64, Mips::D31_64, |
| }; |
| |
| // FGR64 Bit set. |
| const uint8_t FGR64Bits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, |
| }; |
| |
| // GPR64 Register Class... |
| const MCPhysReg GPR64[] = { |
| Mips::ZERO_64, Mips::AT_64, Mips::V0_64, Mips::V1_64, Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64, Mips::T4_64, Mips::T5_64, Mips::T6_64, Mips::T7_64, Mips::S0_64, Mips::S1_64, Mips::S2_64, Mips::S3_64, Mips::S4_64, Mips::S5_64, Mips::S6_64, Mips::S7_64, Mips::T8_64, Mips::T9_64, Mips::K0_64, Mips::K1_64, Mips::GP_64, Mips::SP_64, Mips::FP_64, Mips::RA_64, |
| }; |
| |
| // GPR64 Bit set. |
| const uint8_t GPR64Bits[] = { |
| 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x00, 0x00, 0x00, 0x00, 0xd8, 0xff, 0xff, 0x03, |
| }; |
| |
| // GPR64_with_sub_32_in_GPR32NONZERO Register Class... |
| const MCPhysReg GPR64_with_sub_32_in_GPR32NONZERO[] = { |
| Mips::AT_64, Mips::V0_64, Mips::V1_64, Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64, Mips::T4_64, Mips::T5_64, Mips::T6_64, Mips::T7_64, Mips::S0_64, Mips::S1_64, Mips::S2_64, Mips::S3_64, Mips::S4_64, Mips::S5_64, Mips::S6_64, Mips::S7_64, Mips::T8_64, Mips::T9_64, Mips::K0_64, Mips::K1_64, Mips::GP_64, Mips::SP_64, Mips::FP_64, Mips::RA_64, |
| }; |
| |
| // GPR64_with_sub_32_in_GPR32NONZERO Bit set. |
| const uint8_t GPR64_with_sub_32_in_GPR32NONZEROBits[] = { |
| 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0xd8, 0xff, 0xff, 0x03, |
| }; |
| |
| // AFGR64 Register Class... |
| const MCPhysReg AFGR64[] = { |
| Mips::D0, Mips::D1, Mips::D2, Mips::D3, Mips::D4, Mips::D5, Mips::D6, Mips::D7, Mips::D8, Mips::D9, Mips::D10, Mips::D11, Mips::D12, Mips::D13, Mips::D14, Mips::D15, |
| }; |
| |
| // AFGR64 Bit set. |
| const uint8_t AFGR64Bits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, |
| }; |
| |
| // FGR64_and_OddSP Register Class... |
| const MCPhysReg FGR64_and_OddSP[] = { |
| Mips::D1_64, Mips::D3_64, Mips::D5_64, Mips::D7_64, Mips::D9_64, Mips::D11_64, Mips::D13_64, Mips::D15_64, Mips::D17_64, Mips::D19_64, Mips::D21_64, Mips::D23_64, Mips::D25_64, Mips::D27_64, Mips::D29_64, Mips::D31_64, |
| }; |
| |
| // FGR64_and_OddSP Bit set. |
| const uint8_t FGR64_and_OddSPBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x55, 0x55, 0x01, |
| }; |
| |
| // GPR64_with_sub_32_in_CPU16RegsPlusSP Register Class... |
| const MCPhysReg GPR64_with_sub_32_in_CPU16RegsPlusSP[] = { |
| Mips::V0_64, Mips::V1_64, Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::S0_64, Mips::S1_64, Mips::SP_64, |
| }; |
| |
| // GPR64_with_sub_32_in_CPU16RegsPlusSP Bit set. |
| const uint8_t GPR64_with_sub_32_in_CPU16RegsPlusSPBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03, |
| }; |
| |
| // AFGR64_and_OddSP Register Class... |
| const MCPhysReg AFGR64_and_OddSP[] = { |
| Mips::D1, Mips::D3, Mips::D5, Mips::D7, Mips::D9, Mips::D11, Mips::D13, Mips::D15, |
| }; |
| |
| // AFGR64_and_OddSP Bit set. |
| const uint8_t AFGR64_and_OddSPBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, |
| }; |
| |
| // GPR64_with_sub_32_in_CPU16Regs Register Class... |
| const MCPhysReg GPR64_with_sub_32_in_CPU16Regs[] = { |
| Mips::V0_64, Mips::V1_64, Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::S0_64, Mips::S1_64, |
| }; |
| |
| // GPR64_with_sub_32_in_CPU16Regs Bit set. |
| const uint8_t GPR64_with_sub_32_in_CPU16RegsBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03, |
| }; |
| |
| // GPR64_with_sub_32_in_GPRMM16MoveP Register Class... |
| const MCPhysReg GPR64_with_sub_32_in_GPRMM16MoveP[] = { |
| Mips::ZERO_64, Mips::V0_64, Mips::V1_64, Mips::S0_64, Mips::S1_64, Mips::S2_64, Mips::S3_64, Mips::S4_64, |
| }; |
| |
| // GPR64_with_sub_32_in_GPRMM16MoveP Bit set. |
| const uint8_t GPR64_with_sub_32_in_GPRMM16MovePBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x03, |
| }; |
| |
| // GPR64_with_sub_32_in_GPRMM16Zero Register Class... |
| const MCPhysReg GPR64_with_sub_32_in_GPRMM16Zero[] = { |
| Mips::ZERO_64, Mips::V0_64, Mips::V1_64, Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::S1_64, |
| }; |
| |
| // GPR64_with_sub_32_in_GPRMM16Zero Bit set. |
| const uint8_t GPR64_with_sub_32_in_GPRMM16ZeroBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03, |
| }; |
| |
| // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero Register Class... |
| const MCPhysReg GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero[] = { |
| Mips::V0_64, Mips::V1_64, Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::S1_64, |
| }; |
| |
| // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero Bit set. |
| const uint8_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03, |
| }; |
| |
| // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP Register Class... |
| const MCPhysReg GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP[] = { |
| Mips::V0_64, Mips::V1_64, Mips::S0_64, Mips::S1_64, Mips::S2_64, Mips::S3_64, Mips::S4_64, |
| }; |
| |
| // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP Bit set. |
| const uint8_t GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x03, |
| }; |
| |
| // ACC64DSP Register Class... |
| const MCPhysReg ACC64DSP[] = { |
| Mips::AC0, Mips::AC1, Mips::AC2, Mips::AC3, |
| }; |
| |
| // ACC64DSP Bit set. |
| const uint8_t ACC64DSPBits[] = { |
| 0x00, 0x00, 0x00, 0x3c, |
| }; |
| |
| // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP Register Class... |
| const MCPhysReg GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP[] = { |
| Mips::V0_64, Mips::V1_64, Mips::S0_64, Mips::S1_64, |
| }; |
| |
| // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP Bit set. |
| const uint8_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03, |
| }; |
| |
| // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero Register Class... |
| const MCPhysReg GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero[] = { |
| Mips::ZERO_64, Mips::V0_64, Mips::V1_64, Mips::S1_64, |
| }; |
| |
| // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero Bit set. |
| const uint8_t GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03, |
| }; |
| |
| // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Register Class... |
| const MCPhysReg GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero[] = { |
| Mips::V0_64, Mips::V1_64, Mips::S1_64, |
| }; |
| |
| // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Bit set. |
| const uint8_t GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03, |
| }; |
| |
| // OCTEON_MPL Register Class... |
| const MCPhysReg OCTEON_MPL[] = { |
| Mips::MPL0, Mips::MPL1, Mips::MPL2, |
| }; |
| |
| // OCTEON_MPL Bit set. |
| const uint8_t OCTEON_MPLBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x03, |
| }; |
| |
| // OCTEON_P Register Class... |
| const MCPhysReg OCTEON_P[] = { |
| Mips::P0, Mips::P1, Mips::P2, |
| }; |
| |
| // OCTEON_P Bit set. |
| const uint8_t OCTEON_PBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c, |
| }; |
| |
| // ACC64 Register Class... |
| const MCPhysReg ACC64[] = { |
| Mips::AC0, |
| }; |
| |
| // ACC64 Bit set. |
| const uint8_t ACC64Bits[] = { |
| 0x00, 0x00, 0x00, 0x04, |
| }; |
| |
| // GP64 Register Class... |
| const MCPhysReg GP64[] = { |
| Mips::GP_64, |
| }; |
| |
| // GP64 Bit set. |
| const uint8_t GP64Bits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, |
| }; |
| |
| // GPR64_with_sub_32_in_CPURAReg Register Class... |
| const MCPhysReg GPR64_with_sub_32_in_CPURAReg[] = { |
| Mips::RA_64, |
| }; |
| |
| // GPR64_with_sub_32_in_CPURAReg Bit set. |
| const uint8_t GPR64_with_sub_32_in_CPURARegBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, |
| }; |
| |
| // GPR64_with_sub_32_in_GPR32ZERO Register Class... |
| const MCPhysReg GPR64_with_sub_32_in_GPR32ZERO[] = { |
| Mips::ZERO_64, |
| }; |
| |
| // GPR64_with_sub_32_in_GPR32ZERO Bit set. |
| const uint8_t GPR64_with_sub_32_in_GPR32ZEROBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, |
| }; |
| |
| // HI64 Register Class... |
| const MCPhysReg HI64[] = { |
| Mips::HI0_64, |
| }; |
| |
| // HI64 Bit set. |
| const uint8_t HI64Bits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, |
| }; |
| |
| // LO64 Register Class... |
| const MCPhysReg LO64[] = { |
| Mips::LO0_64, |
| }; |
| |
| // LO64 Bit set. |
| const uint8_t LO64Bits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, |
| }; |
| |
| // SP64 Register Class... |
| const MCPhysReg SP64[] = { |
| Mips::SP_64, |
| }; |
| |
| // SP64 Bit set. |
| const uint8_t SP64Bits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, |
| }; |
| |
| // MSA128B Register Class... |
| const MCPhysReg MSA128B[] = { |
| Mips::W0, Mips::W1, Mips::W2, Mips::W3, Mips::W4, Mips::W5, Mips::W6, Mips::W7, Mips::W8, Mips::W9, Mips::W10, Mips::W11, Mips::W12, Mips::W13, Mips::W14, Mips::W15, Mips::W16, Mips::W17, Mips::W18, Mips::W19, Mips::W20, Mips::W21, Mips::W22, Mips::W23, Mips::W24, Mips::W25, Mips::W26, Mips::W27, Mips::W28, Mips::W29, Mips::W30, Mips::W31, |
| }; |
| |
| // MSA128B Bit set. |
| const uint8_t MSA128BBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, |
| }; |
| |
| // MSA128D Register Class... |
| const MCPhysReg MSA128D[] = { |
| Mips::W0, Mips::W1, Mips::W2, Mips::W3, Mips::W4, Mips::W5, Mips::W6, Mips::W7, Mips::W8, Mips::W9, Mips::W10, Mips::W11, Mips::W12, Mips::W13, Mips::W14, Mips::W15, Mips::W16, Mips::W17, Mips::W18, Mips::W19, Mips::W20, Mips::W21, Mips::W22, Mips::W23, Mips::W24, Mips::W25, Mips::W26, Mips::W27, Mips::W28, Mips::W29, Mips::W30, Mips::W31, |
| }; |
| |
| // MSA128D Bit set. |
| const uint8_t MSA128DBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, |
| }; |
| |
| // MSA128H Register Class... |
| const MCPhysReg MSA128H[] = { |
| Mips::W0, Mips::W1, Mips::W2, Mips::W3, Mips::W4, Mips::W5, Mips::W6, Mips::W7, Mips::W8, Mips::W9, Mips::W10, Mips::W11, Mips::W12, Mips::W13, Mips::W14, Mips::W15, Mips::W16, Mips::W17, Mips::W18, Mips::W19, Mips::W20, Mips::W21, Mips::W22, Mips::W23, Mips::W24, Mips::W25, Mips::W26, Mips::W27, Mips::W28, Mips::W29, Mips::W30, Mips::W31, |
| }; |
| |
| // MSA128H Bit set. |
| const uint8_t MSA128HBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, |
| }; |
| |
| // MSA128W Register Class... |
| const MCPhysReg MSA128W[] = { |
| Mips::W0, Mips::W1, Mips::W2, Mips::W3, Mips::W4, Mips::W5, Mips::W6, Mips::W7, Mips::W8, Mips::W9, Mips::W10, Mips::W11, Mips::W12, Mips::W13, Mips::W14, Mips::W15, Mips::W16, Mips::W17, Mips::W18, Mips::W19, Mips::W20, Mips::W21, Mips::W22, Mips::W23, Mips::W24, Mips::W25, Mips::W26, Mips::W27, Mips::W28, Mips::W29, Mips::W30, Mips::W31, |
| }; |
| |
| // MSA128W Bit set. |
| const uint8_t MSA128WBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, |
| }; |
| |
| // MSA128B_with_sub_64_in_OddSP Register Class... |
| const MCPhysReg MSA128B_with_sub_64_in_OddSP[] = { |
| Mips::W1, Mips::W3, Mips::W5, Mips::W7, Mips::W9, Mips::W11, Mips::W13, Mips::W15, Mips::W17, Mips::W19, Mips::W21, Mips::W23, Mips::W25, Mips::W27, Mips::W29, Mips::W31, |
| }; |
| |
| // MSA128B_with_sub_64_in_OddSP Bit set. |
| const uint8_t MSA128B_with_sub_64_in_OddSPBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x55, 0x55, 0x55, 0x05, |
| }; |
| |
| // MSA128WEvens Register Class... |
| const MCPhysReg MSA128WEvens[] = { |
| Mips::W0, Mips::W2, Mips::W4, Mips::W6, Mips::W8, Mips::W10, Mips::W12, Mips::W14, Mips::W16, Mips::W18, Mips::W20, Mips::W22, Mips::W24, Mips::W26, Mips::W28, Mips::W30, |
| }; |
| |
| // MSA128WEvens Bit set. |
| const uint8_t MSA128WEvensBits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa8, 0xaa, 0xaa, 0xaa, 0x02, |
| }; |
| |
| // ACC128 Register Class... |
| const MCPhysReg ACC128[] = { |
| Mips::AC0_64, |
| }; |
| |
| // ACC128 Bit set. |
| const uint8_t ACC128Bits[] = { |
| 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, |
| }; |
| |
| } // end anonymous namespace |
| |
| extern const char MipsRegClassStrings[] = { |
| /* 0 */ 'C', 'O', 'P', '0', 0, |
| /* 5 */ 'O', 'd', 'd', 'S', 'P', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', 'h', 'i', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', 'h', 'i', '_', 'i', 'n', '_', 'F', 'G', 'R', 'H', '3', '2', 0, |
| /* 45 */ 'H', 'I', '3', '2', 0, |
| /* 50 */ 'L', 'O', '3', '2', 0, |
| /* 55 */ 'G', 'P', '3', '2', 0, |
| /* 60 */ 'S', 'P', '3', '2', 0, |
| /* 65 */ 'O', 'd', 'd', 'S', 'P', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', 'h', 'i', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', 'h', 'i', '_', 'i', 'n', '_', 'F', 'G', 'R', '3', '2', 0, |
| /* 104 */ 'G', 'P', 'R', '3', '2', 0, |
| /* 110 */ 'C', 'O', 'P', '2', 0, |
| /* 115 */ 'C', 'O', 'P', '3', 0, |
| /* 120 */ 'A', 'C', 'C', '6', '4', 0, |
| /* 126 */ 'H', 'I', '6', '4', 0, |
| /* 131 */ 'L', 'O', '6', '4', 0, |
| /* 136 */ 'G', 'P', '6', '4', 0, |
| /* 141 */ 'S', 'P', '6', '4', 0, |
| /* 146 */ 'A', 'F', 'G', 'R', '6', '4', 0, |
| /* 153 */ 'G', 'P', 'R', '6', '4', 0, |
| /* 159 */ 'M', 'S', 'A', '1', '2', '8', 'F', '1', '6', 0, |
| /* 169 */ 'G', 'P', 'R', 'M', 'M', '1', '6', 0, |
| /* 177 */ 'A', 'C', 'C', '1', '2', '8', 0, |
| /* 184 */ 'M', 'S', 'A', '1', '2', '8', 'B', 0, |
| /* 192 */ 'F', 'C', 'C', 0, |
| /* 196 */ 'D', 'S', 'P', 'C', 'C', 0, |
| /* 202 */ 'F', 'G', 'R', 'C', 'C', 0, |
| /* 208 */ 'M', 'S', 'A', '1', '2', '8', 'D', 0, |
| /* 216 */ 'M', 'S', 'A', '1', '2', '8', 'H', 0, |
| /* 224 */ 'O', 'C', 'T', 'E', 'O', 'N', '_', 'M', 'P', 'L', 0, |
| /* 235 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', '3', '2', 'Z', 'E', 'R', 'O', 0, |
| /* 266 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', '3', '2', 'N', 'O', 'N', 'Z', 'E', 'R', 'O', 0, |
| /* 300 */ 'H', 'I', '3', '2', 'D', 'S', 'P', 0, |
| /* 308 */ 'L', 'O', '3', '2', 'D', 'S', 'P', 0, |
| /* 316 */ 'A', 'C', 'C', '6', '4', 'D', 'S', 'P', 0, |
| /* 325 */ 'F', 'G', 'R', 'H', '3', '2', '_', 'a', 'n', 'd', '_', 'O', 'd', 'd', 'S', 'P', 0, |
| /* 342 */ 'F', 'G', 'R', '3', '2', '_', 'a', 'n', 'd', '_', 'O', 'd', 'd', 'S', 'P', 0, |
| /* 358 */ 'A', 'F', 'G', 'R', '6', '4', '_', 'a', 'n', 'd', '_', 'O', 'd', 'd', 'S', 'P', 0, |
| /* 375 */ 'M', 'S', 'A', '1', '2', '8', 'F', '1', '6', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '6', '4', '_', 'i', 'n', '_', 'O', 'd', 'd', 'S', 'P', 0, |
| /* 406 */ 'M', 'S', 'A', '1', '2', '8', 'B', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '6', '4', '_', 'i', 'n', '_', 'O', 'd', 'd', 'S', 'P', 0, |
| /* 435 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'C', 'P', 'U', '1', '6', 'R', 'e', 'g', 's', 'P', 'l', 'u', 's', 'S', 'P', 0, |
| /* 472 */ 'O', 'C', 'T', 'E', 'O', 'N', '_', 'P', 0, |
| /* 481 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', '3', '2', 'N', 'O', 'N', 'Z', 'E', 'R', 'O', '_', 'a', 'n', 'd', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'M', 'o', 'v', 'e', 'P', 0, |
| /* 532 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'C', 'P', 'U', '1', '6', 'R', 'e', 'g', 's', '_', 'a', 'n', 'd', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'M', 'o', 'v', 'e', 'P', 0, |
| /* 580 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'M', 'o', 'v', 'e', 'P', 0, |
| /* 614 */ 'C', 'C', 'R', 0, |
| /* 618 */ 'D', 'S', 'P', 'R', 0, |
| /* 623 */ 'M', 'S', 'A', '1', '2', '8', 'W', 0, |
| /* 631 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'C', 'P', 'U', 'R', 'A', 'R', 'e', 'g', 0, |
| /* 661 */ 'C', 'P', 'U', 'S', 'P', 'R', 'e', 'g', 0, |
| /* 670 */ 'O', 'd', 'd', 'S', 'P', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', 'h', 'i', 0, |
| /* 688 */ 'M', 'S', 'A', 'C', 't', 'r', 'l', 0, |
| /* 696 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'M', 'o', 'v', 'e', 'P', '_', 'a', 'n', 'd', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'Z', 'e', 'r', 'o', 0, |
| /* 746 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'M', 'o', 'v', 'e', 'P', '_', 'a', 'n', 'd', '_', 'C', 'P', 'U', '1', '6', 'R', 'e', 'g', 's', '_', 'a', 'n', 'd', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'Z', 'e', 'r', 'o', 0, |
| /* 810 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'C', 'P', 'U', '1', '6', 'R', 'e', 'g', 's', '_', 'a', 'n', 'd', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'Z', 'e', 'r', 'o', 0, |
| /* 857 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'Z', 'e', 'r', 'o', 0, |
| /* 890 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'C', 'P', 'U', '1', '6', 'R', 'e', 'g', 's', 0, |
| /* 921 */ 'H', 'W', 'R', 'e', 'g', 's', 0, |
| /* 928 */ 'M', 'S', 'A', '1', '2', '8', 'W', 'E', 'v', 'e', 'n', 's', 0, |
| }; |
| |
| extern const MCRegisterClass MipsMCRegisterClasses[] = { |
| { MSA128F16, MSA128F16Bits, 159, 32, sizeof(MSA128F16Bits), Mips::MSA128F16RegClassID, 2, 1, true }, |
| { MSA128F16_with_sub_64_in_OddSP, MSA128F16_with_sub_64_in_OddSPBits, 375, 16, sizeof(MSA128F16_with_sub_64_in_OddSPBits), Mips::MSA128F16_with_sub_64_in_OddSPRegClassID, 2, 1, true }, |
| { OddSP, OddSPBits, 336, 56, sizeof(OddSPBits), Mips::OddSPRegClassID, 4, 1, false }, |
| { CCR, CCRBits, 614, 32, sizeof(CCRBits), Mips::CCRRegClassID, 4, 1, false }, |
| { COP0, COP0Bits, 0, 32, sizeof(COP0Bits), Mips::COP0RegClassID, 4, 1, false }, |
| { COP2, COP2Bits, 110, 32, sizeof(COP2Bits), Mips::COP2RegClassID, 4, 1, false }, |
| { COP3, COP3Bits, 115, 32, sizeof(COP3Bits), Mips::COP3RegClassID, 4, 1, false }, |
| { DSPR, DSPRBits, 618, 32, sizeof(DSPRBits), Mips::DSPRRegClassID, 4, 1, true }, |
| { FGR32, FGR32Bits, 98, 32, sizeof(FGR32Bits), Mips::FGR32RegClassID, 4, 1, true }, |
| { FGRCC, FGRCCBits, 202, 32, sizeof(FGRCCBits), Mips::FGRCCRegClassID, 4, 1, true }, |
| { FGRH32, FGRH32Bits, 38, 32, sizeof(FGRH32Bits), Mips::FGRH32RegClassID, 4, 1, false }, |
| { GPR32, GPR32Bits, 104, 32, sizeof(GPR32Bits), Mips::GPR32RegClassID, 4, 1, true }, |
| { HWRegs, HWRegsBits, 921, 32, sizeof(HWRegsBits), Mips::HWRegsRegClassID, 4, 1, false }, |
| { GPR32NONZERO, GPR32NONZEROBits, 287, 31, sizeof(GPR32NONZEROBits), Mips::GPR32NONZERORegClassID, 4, 1, true }, |
| { OddSP_with_sub_hi, OddSP_with_sub_hiBits, 670, 24, sizeof(OddSP_with_sub_hiBits), Mips::OddSP_with_sub_hiRegClassID, 4, 1, false }, |
| { FGR32_and_OddSP, FGR32_and_OddSPBits, 342, 16, sizeof(FGR32_and_OddSPBits), Mips::FGR32_and_OddSPRegClassID, 4, 1, true }, |
| { FGRH32_and_OddSP, FGRH32_and_OddSPBits, 325, 16, sizeof(FGRH32_and_OddSPBits), Mips::FGRH32_and_OddSPRegClassID, 4, 1, false }, |
| { OddSP_with_sub_hi_with_sub_hi_in_FGRH32, OddSP_with_sub_hi_with_sub_hi_in_FGRH32Bits, 5, 16, sizeof(OddSP_with_sub_hi_with_sub_hi_in_FGRH32Bits), Mips::OddSP_with_sub_hi_with_sub_hi_in_FGRH32RegClassID, 4, 1, false }, |
| { CPU16RegsPlusSP, CPU16RegsPlusSPBits, 456, 9, sizeof(CPU16RegsPlusSPBits), Mips::CPU16RegsPlusSPRegClassID, 4, 1, true }, |
| { CPU16Regs, CPU16RegsBits, 911, 8, sizeof(CPU16RegsBits), Mips::CPU16RegsRegClassID, 4, 1, true }, |
| { FCC, FCCBits, 192, 8, sizeof(FCCBits), Mips::FCCRegClassID, 4, 1, false }, |
| { GPRMM16, GPRMM16Bits, 169, 8, sizeof(GPRMM16Bits), Mips::GPRMM16RegClassID, 4, 1, true }, |
| { GPRMM16MoveP, GPRMM16MovePBits, 519, 8, sizeof(GPRMM16MovePBits), Mips::GPRMM16MovePRegClassID, 4, 1, true }, |
| { GPRMM16Zero, GPRMM16ZeroBits, 734, 8, sizeof(GPRMM16ZeroBits), Mips::GPRMM16ZeroRegClassID, 4, 1, true }, |
| { MSACtrl, MSACtrlBits, 688, 8, sizeof(MSACtrlBits), Mips::MSACtrlRegClassID, 4, 1, true }, |
| { OddSP_with_sub_hi_with_sub_hi_in_FGR32, OddSP_with_sub_hi_with_sub_hi_in_FGR32Bits, 65, 8, sizeof(OddSP_with_sub_hi_with_sub_hi_in_FGR32Bits), Mips::OddSP_with_sub_hi_with_sub_hi_in_FGR32RegClassID, 4, 1, false }, |
| { CPU16Regs_and_GPRMM16Zero, CPU16Regs_and_GPRMM16ZeroBits, 784, 7, sizeof(CPU16Regs_and_GPRMM16ZeroBits), Mips::CPU16Regs_and_GPRMM16ZeroRegClassID, 4, 1, true }, |
| { GPR32NONZERO_and_GPRMM16MoveP, GPR32NONZERO_and_GPRMM16MovePBits, 502, 7, sizeof(GPR32NONZERO_and_GPRMM16MovePBits), Mips::GPR32NONZERO_and_GPRMM16MovePRegClassID, 4, 1, true }, |
| { CPU16Regs_and_GPRMM16MoveP, CPU16Regs_and_GPRMM16MovePBits, 553, 4, sizeof(CPU16Regs_and_GPRMM16MovePBits), Mips::CPU16Regs_and_GPRMM16MovePRegClassID, 4, 1, true }, |
| { GPRMM16MoveP_and_GPRMM16Zero, GPRMM16MoveP_and_GPRMM16ZeroBits, 717, 4, sizeof(GPRMM16MoveP_and_GPRMM16ZeroBits), Mips::GPRMM16MoveP_and_GPRMM16ZeroRegClassID, 4, 1, true }, |
| { HI32DSP, HI32DSPBits, 300, 4, sizeof(HI32DSPBits), Mips::HI32DSPRegClassID, 4, 1, true }, |
| { LO32DSP, LO32DSPBits, 308, 4, sizeof(LO32DSPBits), Mips::LO32DSPRegClassID, 4, 1, true }, |
| { GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero, GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits, 767, 3, sizeof(GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits), Mips::GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID, 4, 1, true }, |
| { CPURAReg, CPURARegBits, 652, 1, sizeof(CPURARegBits), Mips::CPURARegRegClassID, 4, 1, false }, |
| { CPUSPReg, CPUSPRegBits, 661, 1, sizeof(CPUSPRegBits), Mips::CPUSPRegRegClassID, 4, 1, false }, |
| { DSPCC, DSPCCBits, 196, 1, sizeof(DSPCCBits), Mips::DSPCCRegClassID, 4, 1, true }, |
| { GP32, GP32Bits, 55, 1, sizeof(GP32Bits), Mips::GP32RegClassID, 4, 1, false }, |
| { GPR32ZERO, GPR32ZEROBits, 256, 1, sizeof(GPR32ZEROBits), Mips::GPR32ZERORegClassID, 4, 1, true }, |
| { HI32, HI32Bits, 45, 1, sizeof(HI32Bits), Mips::HI32RegClassID, 4, 1, true }, |
| { LO32, LO32Bits, 50, 1, sizeof(LO32Bits), Mips::LO32RegClassID, 4, 1, true }, |
| { SP32, SP32Bits, 60, 1, sizeof(SP32Bits), Mips::SP32RegClassID, 4, 1, false }, |
| { FGR64, FGR64Bits, 147, 32, sizeof(FGR64Bits), Mips::FGR64RegClassID, 8, 1, true }, |
| { GPR64, GPR64Bits, 153, 32, sizeof(GPR64Bits), Mips::GPR64RegClassID, 8, 1, true }, |
| { GPR64_with_sub_32_in_GPR32NONZERO, GPR64_with_sub_32_in_GPR32NONZEROBits, 266, 31, sizeof(GPR64_with_sub_32_in_GPR32NONZEROBits), Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID, 8, 1, true }, |
| { AFGR64, AFGR64Bits, 146, 16, sizeof(AFGR64Bits), Mips::AFGR64RegClassID, 8, 1, true }, |
| { FGR64_and_OddSP, FGR64_and_OddSPBits, 359, 16, sizeof(FGR64_and_OddSPBits), Mips::FGR64_and_OddSPRegClassID, 8, 1, true }, |
| { GPR64_with_sub_32_in_CPU16RegsPlusSP, GPR64_with_sub_32_in_CPU16RegsPlusSPBits, 435, 9, sizeof(GPR64_with_sub_32_in_CPU16RegsPlusSPBits), Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID, 8, 1, true }, |
| { AFGR64_and_OddSP, AFGR64_and_OddSPBits, 358, 8, sizeof(AFGR64_and_OddSPBits), Mips::AFGR64_and_OddSPRegClassID, 8, 1, true }, |
| { GPR64_with_sub_32_in_CPU16Regs, GPR64_with_sub_32_in_CPU16RegsBits, 890, 8, sizeof(GPR64_with_sub_32_in_CPU16RegsBits), Mips::GPR64_with_sub_32_in_CPU16RegsRegClassID, 8, 1, true }, |
| { GPR64_with_sub_32_in_GPRMM16MoveP, GPR64_with_sub_32_in_GPRMM16MovePBits, 580, 8, sizeof(GPR64_with_sub_32_in_GPRMM16MovePBits), Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClassID, 8, 1, true }, |
| { GPR64_with_sub_32_in_GPRMM16Zero, GPR64_with_sub_32_in_GPRMM16ZeroBits, 857, 8, sizeof(GPR64_with_sub_32_in_GPRMM16ZeroBits), Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClassID, 8, 1, true }, |
| { GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero, GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroBits, 810, 7, sizeof(GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroBits), Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClassID, 8, 1, true }, |
| { GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP, GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePBits, 481, 7, sizeof(GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePBits), Mips::GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClassID, 8, 1, true }, |
| { ACC64DSP, ACC64DSPBits, 316, 4, sizeof(ACC64DSPBits), Mips::ACC64DSPRegClassID, 8, 1, true }, |
| { GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP, GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePBits, 532, 4, sizeof(GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePBits), Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClassID, 8, 1, true }, |
| { GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero, GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroBits, 696, 4, sizeof(GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroBits), Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClassID, 8, 1, true }, |
| { GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero, GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits, 746, 3, sizeof(GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits), Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID, 8, 1, true }, |
| { OCTEON_MPL, OCTEON_MPLBits, 224, 3, sizeof(OCTEON_MPLBits), Mips::OCTEON_MPLRegClassID, 8, 1, false }, |
| { OCTEON_P, OCTEON_PBits, 472, 3, sizeof(OCTEON_PBits), Mips::OCTEON_PRegClassID, 8, 1, false }, |
| { ACC64, ACC64Bits, 120, 1, sizeof(ACC64Bits), Mips::ACC64RegClassID, 8, 1, true }, |
| { GP64, GP64Bits, 136, 1, sizeof(GP64Bits), Mips::GP64RegClassID, 8, 1, false }, |
| { GPR64_with_sub_32_in_CPURAReg, GPR64_with_sub_32_in_CPURARegBits, 631, 1, sizeof(GPR64_with_sub_32_in_CPURARegBits), Mips::GPR64_with_sub_32_in_CPURARegRegClassID, 8, 1, true }, |
| { GPR64_with_sub_32_in_GPR32ZERO, GPR64_with_sub_32_in_GPR32ZEROBits, 235, 1, sizeof(GPR64_with_sub_32_in_GPR32ZEROBits), Mips::GPR64_with_sub_32_in_GPR32ZERORegClassID, 8, 1, true }, |
| { HI64, HI64Bits, 126, 1, sizeof(HI64Bits), Mips::HI64RegClassID, 8, 1, true }, |
| { LO64, LO64Bits, 131, 1, sizeof(LO64Bits), Mips::LO64RegClassID, 8, 1, true }, |
| { SP64, SP64Bits, 141, 1, sizeof(SP64Bits), Mips::SP64RegClassID, 8, 1, false }, |
| { MSA128B, MSA128BBits, 184, 32, sizeof(MSA128BBits), Mips::MSA128BRegClassID, 16, 1, true }, |
| { MSA128D, MSA128DBits, 208, 32, sizeof(MSA128DBits), Mips::MSA128DRegClassID, 16, 1, true }, |
| { MSA128H, MSA128HBits, 216, 32, sizeof(MSA128HBits), Mips::MSA128HRegClassID, 16, 1, true }, |
| { MSA128W, MSA128WBits, 623, 32, sizeof(MSA128WBits), Mips::MSA128WRegClassID, 16, 1, true }, |
| { MSA128B_with_sub_64_in_OddSP, MSA128B_with_sub_64_in_OddSPBits, 406, 16, sizeof(MSA128B_with_sub_64_in_OddSPBits), Mips::MSA128B_with_sub_64_in_OddSPRegClassID, 16, 1, true }, |
| { MSA128WEvens, MSA128WEvensBits, 928, 16, sizeof(MSA128WEvensBits), Mips::MSA128WEvensRegClassID, 16, 1, true }, |
| { ACC128, ACC128Bits, 177, 1, sizeof(ACC128Bits), Mips::ACC128RegClassID, 16, 1, true }, |
| }; |
| |
| // Mips Dwarf<->LLVM register mappings. |
| extern const MCRegisterInfo::DwarfLLVMRegPair MipsDwarfFlavour0Dwarf2L[] = { |
| { 0U, Mips::ZERO_64 }, |
| { 1U, Mips::AT_64 }, |
| { 2U, Mips::V0_64 }, |
| { 3U, Mips::V1_64 }, |
| { 4U, Mips::A0_64 }, |
| { 5U, Mips::A1_64 }, |
| { 6U, Mips::A2_64 }, |
| { 7U, Mips::A3_64 }, |
| { 8U, Mips::T0_64 }, |
| { 9U, Mips::T1_64 }, |
| { 10U, Mips::T2_64 }, |
| { 11U, Mips::T3_64 }, |
| { 12U, Mips::T4_64 }, |
| { 13U, Mips::T5_64 }, |
| { 14U, Mips::T6_64 }, |
| { 15U, Mips::T7_64 }, |
| { 16U, Mips::S0_64 }, |
| { 17U, Mips::S1_64 }, |
| { 18U, Mips::S2_64 }, |
| { 19U, Mips::S3_64 }, |
| { 20U, Mips::S4_64 }, |
| { 21U, Mips::S5_64 }, |
| { 22U, Mips::S6_64 }, |
| { 23U, Mips::S7_64 }, |
| { 24U, Mips::T8_64 }, |
| { 25U, Mips::T9_64 }, |
| { 26U, Mips::K0_64 }, |
| { 27U, Mips::K1_64 }, |
| { 28U, Mips::GP_64 }, |
| { 29U, Mips::SP_64 }, |
| { 30U, Mips::FP_64 }, |
| { 31U, Mips::RA_64 }, |
| { 32U, Mips::D0_64 }, |
| { 33U, Mips::D1_64 }, |
| { 34U, Mips::D2_64 }, |
| { 35U, Mips::D3_64 }, |
| { 36U, Mips::D4_64 }, |
| { 37U, Mips::D5_64 }, |
| { 38U, Mips::D6_64 }, |
| { 39U, Mips::D7_64 }, |
| { 40U, Mips::D8_64 }, |
| { 41U, Mips::D9_64 }, |
| { 42U, Mips::D10_64 }, |
| { 43U, Mips::D11_64 }, |
| { 44U, Mips::D12_64 }, |
| { 45U, Mips::D13_64 }, |
| { 46U, Mips::D14_64 }, |
| { 47U, Mips::D15_64 }, |
| { 48U, Mips::D16_64 }, |
| { 49U, Mips::D17_64 }, |
| { 50U, Mips::D18_64 }, |
| { 51U, Mips::D19_64 }, |
| { 52U, Mips::D20_64 }, |
| { 53U, Mips::D21_64 }, |
| { 54U, Mips::D22_64 }, |
| { 55U, Mips::D23_64 }, |
| { 56U, Mips::D24_64 }, |
| { 57U, Mips::D25_64 }, |
| { 58U, Mips::D26_64 }, |
| { 59U, Mips::D27_64 }, |
| { 60U, Mips::D28_64 }, |
| { 61U, Mips::D29_64 }, |
| { 62U, Mips::D30_64 }, |
| { 63U, Mips::D31_64 }, |
| { 64U, Mips::HI0 }, |
| { 65U, Mips::LO0 }, |
| { 176U, Mips::HI1 }, |
| { 177U, Mips::LO1 }, |
| { 178U, Mips::HI2 }, |
| { 179U, Mips::LO2 }, |
| { 180U, Mips::HI3 }, |
| { 181U, Mips::LO3 }, |
| }; |
| extern const unsigned MipsDwarfFlavour0Dwarf2LSize = array_lengthof(MipsDwarfFlavour0Dwarf2L); |
| |
| extern const MCRegisterInfo::DwarfLLVMRegPair MipsEHFlavour0Dwarf2L[] = { |
| { 0U, Mips::ZERO_64 }, |
| { 1U, Mips::AT_64 }, |
| { 2U, Mips::V0_64 }, |
| { 3U, Mips::V1_64 }, |
| { 4U, Mips::A0_64 }, |
| { 5U, Mips::A1_64 }, |
| { 6U, Mips::A2_64 }, |
| { 7U, Mips::A3_64 }, |
| { 8U, Mips::T0_64 }, |
| { 9U, Mips::T1_64 }, |
| { 10U, Mips::T2_64 }, |
| { 11U, Mips::T3_64 }, |
| { 12U, Mips::T4_64 }, |
| { 13U, Mips::T5_64 }, |
| { 14U, Mips::T6_64 }, |
| { 15U, Mips::T7_64 }, |
| { 16U, Mips::S0_64 }, |
| { 17U, Mips::S1_64 }, |
| { 18U, Mips::S2_64 }, |
| { 19U, Mips::S3_64 }, |
| { 20U, Mips::S4_64 }, |
| { 21U, Mips::S5_64 }, |
| { 22U, Mips::S6_64 }, |
| { 23U, Mips::S7_64 }, |
| { 24U, Mips::T8_64 }, |
| { 25U, Mips::T9_64 }, |
| { 26U, Mips::K0_64 }, |
| { 27U, Mips::K1_64 }, |
| { 28U, Mips::GP_64 }, |
| { 29U, Mips::SP_64 }, |
| { 30U, Mips::FP_64 }, |
| { 31U, Mips::RA_64 }, |
| { 32U, Mips::D0_64 }, |
| { 33U, Mips::D1_64 }, |
| { 34U, Mips::D2_64 }, |
| { 35U, Mips::D3_64 }, |
| { 36U, Mips::D4_64 }, |
| { 37U, Mips::D5_64 }, |
| { 38U, Mips::D6_64 }, |
| { 39U, Mips::D7_64 }, |
| { 40U, Mips::D8_64 }, |
| { 41U, Mips::D9_64 }, |
| { 42U, Mips::D10_64 }, |
| { 43U, Mips::D11_64 }, |
| { 44U, Mips::D12_64 }, |
| { 45U, Mips::D13_64 }, |
| { 46U, Mips::D14_64 }, |
| { 47U, Mips::D15_64 }, |
| { 48U, Mips::D16_64 }, |
| { 49U, Mips::D17_64 }, |
| { 50U, Mips::D18_64 }, |
| { 51U, Mips::D19_64 }, |
| { 52U, Mips::D20_64 }, |
| { 53U, Mips::D21_64 }, |
| { 54U, Mips::D22_64 }, |
| { 55U, Mips::D23_64 }, |
| { 56U, Mips::D24_64 }, |
| { 57U, Mips::D25_64 }, |
| { 58U, Mips::D26_64 }, |
| { 59U, Mips::D27_64 }, |
| { 60U, Mips::D28_64 }, |
| { 61U, Mips::D29_64 }, |
| { 62U, Mips::D30_64 }, |
| { 63U, Mips::D31_64 }, |
| { 64U, Mips::HI0 }, |
| { 65U, Mips::LO0 }, |
| { 176U, Mips::HI1 }, |
| { 177U, Mips::LO1 }, |
| { 178U, Mips::HI2 }, |
| { 179U, Mips::LO2 }, |
| { 180U, Mips::HI3 }, |
| { 181U, Mips::LO3 }, |
| }; |
| extern const unsigned MipsEHFlavour0Dwarf2LSize = array_lengthof(MipsEHFlavour0Dwarf2L); |
| |
| extern const MCRegisterInfo::DwarfLLVMRegPair MipsDwarfFlavour0L2Dwarf[] = { |
| { Mips::AT, 1U }, |
| { Mips::FP, 30U }, |
| { Mips::GP, 28U }, |
| { Mips::RA, 31U }, |
| { Mips::SP, 29U }, |
| { Mips::ZERO, 0U }, |
| { Mips::A0, 4U }, |
| { Mips::A1, 5U }, |
| { Mips::A2, 6U }, |
| { Mips::A3, 7U }, |
| { Mips::AT_64, 1U }, |
| { Mips::F0, 32U }, |
| { Mips::F1, 33U }, |
| { Mips::F2, 34U }, |
| { Mips::F3, 35U }, |
| { Mips::F4, 36U }, |
| { Mips::F5, 37U }, |
| { Mips::F6, 38U }, |
| { Mips::F7, 39U }, |
| { Mips::F8, 40U }, |
| { Mips::F9, 41U }, |
| { Mips::F10, 42U }, |
| { Mips::F11, 43U }, |
| { Mips::F12, 44U }, |
| { Mips::F13, 45U }, |
| { Mips::F14, 46U }, |
| { Mips::F15, 47U }, |
| { Mips::F16, 48U }, |
| { Mips::F17, 49U }, |
| { Mips::F18, 50U }, |
| { Mips::F19, 51U }, |
| { Mips::F20, 52U }, |
| { Mips::F21, 53U }, |
| { Mips::F22, 54U }, |
| { Mips::F23, 55U }, |
| { Mips::F24, 56U }, |
| { Mips::F25, 57U }, |
| { Mips::F26, 58U }, |
| { Mips::F27, 59U }, |
| { Mips::F28, 60U }, |
| { Mips::F29, 61U }, |
| { Mips::F30, 62U }, |
| { Mips::F31, 63U }, |
| { Mips::FP_64, 30U }, |
| { Mips::F_HI0, 32U }, |
| { Mips::F_HI1, 33U }, |
| { Mips::F_HI2, 34U }, |
| { Mips::F_HI3, 35U }, |
| { Mips::F_HI4, 36U }, |
| { Mips::F_HI5, 37U }, |
| { Mips::F_HI6, 38U }, |
| { Mips::F_HI7, 39U }, |
| { Mips::F_HI8, 40U }, |
| { Mips::F_HI9, 41U }, |
| { Mips::F_HI10, 42U }, |
| { Mips::F_HI11, 43U }, |
| { Mips::F_HI12, 44U }, |
| { Mips::F_HI13, 45U }, |
| { Mips::F_HI14, 46U }, |
| { Mips::F_HI15, 47U }, |
| { Mips::F_HI16, 48U }, |
| { Mips::F_HI17, 49U }, |
| { Mips::F_HI18, 50U }, |
| { Mips::F_HI19, 51U }, |
| { Mips::F_HI20, 52U }, |
| { Mips::F_HI21, 53U }, |
| { Mips::F_HI22, 54U }, |
| { Mips::F_HI23, 55U }, |
| { Mips::F_HI24, 56U }, |
| { Mips::F_HI25, 57U }, |
| { Mips::F_HI26, 58U }, |
| { Mips::F_HI27, 59U }, |
| { Mips::F_HI28, 60U }, |
| { Mips::F_HI29, 61U }, |
| { Mips::F_HI30, 62U }, |
| { Mips::F_HI31, 63U }, |
| { Mips::GP_64, 28U }, |
| { Mips::HI0, 64U }, |
| { Mips::HI1, 176U }, |
| { Mips::HI2, 178U }, |
| { Mips::HI3, 180U }, |
| { Mips::K0, 26U }, |
| { Mips::K1, 27U }, |
| { Mips::LO0, 65U }, |
| { Mips::LO1, 177U }, |
| { Mips::LO2, 179U }, |
| { Mips::LO3, 181U }, |
| { Mips::RA_64, 31U }, |
| { Mips::S0, 16U }, |
| { Mips::S1, 17U }, |
| { Mips::S2, 18U }, |
| { Mips::S3, 19U }, |
| { Mips::S4, 20U }, |
| { Mips::S5, 21U }, |
| { Mips::S6, 22U }, |
| { Mips::S7, 23U }, |
| { Mips::SP_64, 29U }, |
| { Mips::T0, 8U }, |
| { Mips::T1, 9U }, |
| { Mips::T2, 10U }, |
| { Mips::T3, 11U }, |
| { Mips::T4, 12U }, |
| { Mips::T5, 13U }, |
| { Mips::T6, 14U }, |
| { Mips::T7, 15U }, |
| { Mips::T8, 24U }, |
| { Mips::T9, 25U }, |
| { Mips::V0, 2U }, |
| { Mips::V1, 3U }, |
| { Mips::W0, 32U }, |
| { Mips::W1, 33U }, |
| { Mips::W2, 34U }, |
| { Mips::W3, 35U }, |
| { Mips::W4, 36U }, |
| { Mips::W5, 37U }, |
| { Mips::W6, 38U }, |
| { Mips::W7, 39U }, |
| { Mips::W8, 40U }, |
| { Mips::W9, 41U }, |
| { Mips::W10, 42U }, |
| { Mips::W11, 43U }, |
| { Mips::W12, 44U }, |
| { Mips::W13, 45U }, |
| { Mips::W14, 46U }, |
| { Mips::W15, 47U }, |
| { Mips::W16, 48U }, |
| { Mips::W17, 49U }, |
| { Mips::W18, 50U }, |
| { Mips::W19, 51U }, |
| { Mips::W20, 52U }, |
| { Mips::W21, 53U }, |
| { Mips::W22, 54U }, |
| { Mips::W23, 55U }, |
| { Mips::W24, 56U }, |
| { Mips::W25, 57U }, |
| { Mips::W26, 58U }, |
| { Mips::W27, 59U }, |
| { Mips::W28, 60U }, |
| { Mips::W29, 61U }, |
| { Mips::W30, 62U }, |
| { Mips::W31, 63U }, |
| { Mips::ZERO_64, 0U }, |
| { Mips::A0_64, 4U }, |
| { Mips::A1_64, 5U }, |
| { Mips::A2_64, 6U }, |
| { Mips::A3_64, 7U }, |
| { Mips::D0_64, 32U }, |
| { Mips::D1_64, 33U }, |
| { Mips::D2_64, 34U }, |
| { Mips::D3_64, 35U }, |
| { Mips::D4_64, 36U }, |
| { Mips::D5_64, 37U }, |
| { Mips::D6_64, 38U }, |
| { Mips::D7_64, 39U }, |
| { Mips::D8_64, 40U }, |
| { Mips::D9_64, 41U }, |
| { Mips::D10_64, 42U }, |
| { Mips::D11_64, 43U }, |
| { Mips::D12_64, 44U }, |
| { Mips::D13_64, 45U }, |
| { Mips::D14_64, 46U }, |
| { Mips::D15_64, 47U }, |
| { Mips::D16_64, 48U }, |
| { Mips::D17_64, 49U }, |
| { Mips::D18_64, 50U }, |
| { Mips::D19_64, 51U }, |
| { Mips::D20_64, 52U }, |
| { Mips::D21_64, 53U }, |
| { Mips::D22_64, 54U }, |
| { Mips::D23_64, 55U }, |
| { Mips::D24_64, 56U }, |
| { Mips::D25_64, 57U }, |
| { Mips::D26_64, 58U }, |
| { Mips::D27_64, 59U }, |
| { Mips::D28_64, 60U }, |
| { Mips::D29_64, 61U }, |
| { Mips::D30_64, 62U }, |
| { Mips::D31_64, 63U }, |
| { Mips::K0_64, 26U }, |
| { Mips::K1_64, 27U }, |
| { Mips::S0_64, 16U }, |
| { Mips::S1_64, 17U }, |
| { Mips::S2_64, 18U }, |
| { Mips::S3_64, 19U }, |
| { Mips::S4_64, 20U }, |
| { Mips::S5_64, 21U }, |
| { Mips::S6_64, 22U }, |
| { Mips::S7_64, 23U }, |
| { Mips::T0_64, 8U }, |
| { Mips::T1_64, 9U }, |
| { Mips::T2_64, 10U }, |
| { Mips::T3_64, 11U }, |
| { Mips::T4_64, 12U }, |
| { Mips::T5_64, 13U }, |
| { Mips::T6_64, 14U }, |
| { Mips::T7_64, 15U }, |
| { Mips::T8_64, 24U }, |
| { Mips::T9_64, 25U }, |
| { Mips::V0_64, 2U }, |
| { Mips::V1_64, 3U }, |
| }; |
| extern const unsigned MipsDwarfFlavour0L2DwarfSize = array_lengthof(MipsDwarfFlavour0L2Dwarf); |
| |
| extern const MCRegisterInfo::DwarfLLVMRegPair MipsEHFlavour0L2Dwarf[] = { |
| { Mips::AT, 1U }, |
| { Mips::FP, 30U }, |
| { Mips::GP, 28U }, |
| { Mips::RA, 31U }, |
| { Mips::SP, 29U }, |
| { Mips::ZERO, 0U }, |
| { Mips::A0, 4U }, |
| { Mips::A1, 5U }, |
| { Mips::A2, 6U }, |
| { Mips::A3, 7U }, |
| { Mips::AT_64, 1U }, |
| { Mips::F0, 32U }, |
| { Mips::F1, 33U }, |
| { Mips::F2, 34U }, |
| { Mips::F3, 35U }, |
| { Mips::F4, 36U }, |
| { Mips::F5, 37U }, |
| { Mips::F6, 38U }, |
| { Mips::F7, 39U }, |
| { Mips::F8, 40U }, |
| { Mips::F9, 41U }, |
| { Mips::F10, 42U }, |
| { Mips::F11, 43U }, |
| { Mips::F12, 44U }, |
| { Mips::F13, 45U }, |
| { Mips::F14, 46U }, |
| { Mips::F15, 47U }, |
| { Mips::F16, 48U }, |
| { Mips::F17, 49U }, |
| { Mips::F18, 50U }, |
| { Mips::F19, 51U }, |
| { Mips::F20, 52U }, |
| { Mips::F21, 53U }, |
| { Mips::F22, 54U }, |
| { Mips::F23, 55U }, |
| { Mips::F24, 56U }, |
| { Mips::F25, 57U }, |
| { Mips::F26, 58U }, |
| { Mips::F27, 59U }, |
| { Mips::F28, 60U }, |
| { Mips::F29, 61U }, |
| { Mips::F30, 62U }, |
| { Mips::F31, 63U }, |
| { Mips::FP_64, 30U }, |
| { Mips::F_HI0, 32U }, |
| { Mips::F_HI1, 33U }, |
| { Mips::F_HI2, 34U }, |
| { Mips::F_HI3, 35U }, |
| { Mips::F_HI4, 36U }, |
| { Mips::F_HI5, 37U }, |
| { Mips::F_HI6, 38U }, |
| { Mips::F_HI7, 39U }, |
| { Mips::F_HI8, 40U }, |
| { Mips::F_HI9, 41U }, |
| { Mips::F_HI10, 42U }, |
| { Mips::F_HI11, 43U }, |
| { Mips::F_HI12, 44U }, |
| { Mips::F_HI13, 45U }, |
| { Mips::F_HI14, 46U }, |
| { Mips::F_HI15, 47U }, |
| { Mips::F_HI16, 48U }, |
| { Mips::F_HI17, 49U }, |
| { Mips::F_HI18, 50U }, |
| { Mips::F_HI19, 51U }, |
| { Mips::F_HI20, 52U }, |
| { Mips::F_HI21, 53U }, |
| { Mips::F_HI22, 54U }, |
| { Mips::F_HI23, 55U }, |
| { Mips::F_HI24, 56U }, |
| { Mips::F_HI25, 57U }, |
| { Mips::F_HI26, 58U }, |
| { Mips::F_HI27, 59U }, |
| { Mips::F_HI28, 60U }, |
| { Mips::F_HI29, 61U }, |
| { Mips::F_HI30, 62U }, |
| { Mips::F_HI31, 63U }, |
| { Mips::GP_64, 28U }, |
| { Mips::HI0, 64U }, |
| { Mips::HI1, 176U }, |
| { Mips::HI2, 178U }, |
| { Mips::HI3, 180U }, |
| { Mips::K0, 26U }, |
| { Mips::K1, 27U }, |
| { Mips::LO0, 65U }, |
| { Mips::LO1, 177U }, |
| { Mips::LO2, 179U }, |
| { Mips::LO3, 181U }, |
| { Mips::RA_64, 31U }, |
| { Mips::S0, 16U }, |
| { Mips::S1, 17U }, |
| { Mips::S2, 18U }, |
| { Mips::S3, 19U }, |
| { Mips::S4, 20U }, |
| { Mips::S5, 21U }, |
| { Mips::S6, 22U }, |
| { Mips::S7, 23U }, |
| { Mips::SP_64, 29U }, |
| { Mips::T0, 8U }, |
| { Mips::T1, 9U }, |
| { Mips::T2, 10U }, |
| { Mips::T3, 11U }, |
| { Mips::T4, 12U }, |
| { Mips::T5, 13U }, |
| { Mips::T6, 14U }, |
| { Mips::T7, 15U }, |
| { Mips::T8, 24U }, |
| { Mips::T9, 25U }, |
| { Mips::V0, 2U }, |
| { Mips::V1, 3U }, |
| { Mips::W0, 32U }, |
| { Mips::W1, 33U }, |
| { Mips::W2, 34U }, |
| { Mips::W3, 35U }, |
| { Mips::W4, 36U }, |
| { Mips::W5, 37U }, |
| { Mips::W6, 38U }, |
| { Mips::W7, 39U }, |
| { Mips::W8, 40U }, |
| { Mips::W9, 41U }, |
| { Mips::W10, 42U }, |
| { Mips::W11, 43U }, |
| { Mips::W12, 44U }, |
| { Mips::W13, 45U }, |
| { Mips::W14, 46U }, |
| { Mips::W15, 47U }, |
| { Mips::W16, 48U }, |
| { Mips::W17, 49U }, |
| { Mips::W18, 50U }, |
| { Mips::W19, 51U }, |
| { Mips::W20, 52U }, |
| { Mips::W21, 53U }, |
| { Mips::W22, 54U }, |
| { Mips::W23, 55U }, |
| { Mips::W24, 56U }, |
| { Mips::W25, 57U }, |
| { Mips::W26, 58U }, |
| { Mips::W27, 59U }, |
| { Mips::W28, 60U }, |
| { Mips::W29, 61U }, |
| { Mips::W30, 62U }, |
| { Mips::W31, 63U }, |
| { Mips::ZERO_64, 0U }, |
| { Mips::A0_64, 4U }, |
| { Mips::A1_64, 5U }, |
| { Mips::A2_64, 6U }, |
| { Mips::A3_64, 7U }, |
| { Mips::D0_64, 32U }, |
| { Mips::D1_64, 33U }, |
| { Mips::D2_64, 34U }, |
| { Mips::D3_64, 35U }, |
| { Mips::D4_64, 36U }, |
| { Mips::D5_64, 37U }, |
| { Mips::D6_64, 38U }, |
| { Mips::D7_64, 39U }, |
| { Mips::D8_64, 40U }, |
| { Mips::D9_64, 41U }, |
| { Mips::D10_64, 42U }, |
| { Mips::D11_64, 43U }, |
| { Mips::D12_64, 44U }, |
| { Mips::D13_64, 45U }, |
| { Mips::D14_64, 46U }, |
| { Mips::D15_64, 47U }, |
| { Mips::D16_64, 48U }, |
| { Mips::D17_64, 49U }, |
| { Mips::D18_64, 50U }, |
| { Mips::D19_64, 51U }, |
| { Mips::D20_64, 52U }, |
| { Mips::D21_64, 53U }, |
| { Mips::D22_64, 54U }, |
| { Mips::D23_64, 55U }, |
| { Mips::D24_64, 56U }, |
| { Mips::D25_64, 57U }, |
| { Mips::D26_64, 58U }, |
| { Mips::D27_64, 59U }, |
| { Mips::D28_64, 60U }, |
| { Mips::D29_64, 61U }, |
| { Mips::D30_64, 62U }, |
| { Mips::D31_64, 63U }, |
| { Mips::K0_64, 26U }, |
| { Mips::K1_64, 27U }, |
| { Mips::S0_64, 16U }, |
| { Mips::S1_64, 17U }, |
| { Mips::S2_64, 18U }, |
| { Mips::S3_64, 19U }, |
| { Mips::S4_64, 20U }, |
| { Mips::S5_64, 21U }, |
| { Mips::S6_64, 22U }, |
| { Mips::S7_64, 23U }, |
| { Mips::T0_64, 8U }, |
| { Mips::T1_64, 9U }, |
| { Mips::T2_64, 10U }, |
| { Mips::T3_64, 11U }, |
| { Mips::T4_64, 12U }, |
| { Mips::T5_64, 13U }, |
| { Mips::T6_64, 14U }, |
| { Mips::T7_64, 15U }, |
| { Mips::T8_64, 24U }, |
| { Mips::T9_64, 25U }, |
| { Mips::V0_64, 2U }, |
| { Mips::V1_64, 3U }, |
| }; |
| extern const unsigned MipsEHFlavour0L2DwarfSize = array_lengthof(MipsEHFlavour0L2Dwarf); |
| |
| extern const uint16_t MipsRegEncodingTable[] = { |
| 0, |
| 1, |
| 0, |
| 0, |
| 0, |
| 0, |
| 0, |
| 0, |
| 30, |
| 28, |
| 2, |
| 1, |
| 0, |
| 6, |
| 4, |
| 5, |
| 3, |
| 7, |
| 0, |
| 31, |
| 29, |
| 0, |
| 4, |
| 5, |
| 6, |
| 7, |
| 0, |
| 1, |
| 2, |
| 3, |
| 1, |
| 0, |
| 1, |
| 2, |
| 3, |
| 4, |
| 5, |
| 6, |
| 7, |
| 8, |
| 9, |
| 0, |
| 1, |
| 2, |
| 3, |
| 4, |
| 5, |
| 6, |
| 7, |
| 8, |
| 9, |
| 0, |
| 1, |
| 2, |
| 3, |
| 4, |
| 5, |
| 6, |
| 7, |
| 8, |
| 9, |
| 10, |
| 11, |
| 12, |
| 13, |
| 14, |
| 15, |
| 16, |
| 17, |
| 18, |
| 19, |
| 20, |
| 21, |
| 22, |
| 23, |
| 24, |
| 25, |
| 26, |
| 27, |
| 28, |
| 29, |
| 30, |
| 31, |
| 10, |
| 11, |
| 12, |
| 13, |
| 14, |
| 15, |
| 16, |
| 17, |
| 18, |
| 19, |
| 20, |
| 21, |
| 22, |
| 23, |
| 24, |
| 25, |
| 26, |
| 27, |
| 28, |
| 29, |
| 30, |
| 31, |
| 10, |
| 11, |
| 12, |
| 13, |
| 14, |
| 15, |
| 16, |
| 17, |
| 18, |
| 19, |
| 20, |
| 21, |
| 22, |
| 23, |
| 24, |
| 25, |
| 26, |
| 27, |
| 28, |
| 29, |
| 30, |
| 31, |
| 0, |
| 2, |
| 4, |
| 6, |
| 8, |
| 10, |
| 12, |
| 14, |
| 16, |
| 18, |
| 20, |
| 22, |
| 24, |
| 26, |
| 28, |
| 30, |
| 0, |
| 0, |
| 0, |
| 0, |
| 0, |
| 1, |
| 2, |
| 3, |
| 4, |
| 5, |
| 6, |
| 7, |
| 8, |
| 9, |
| 10, |
| 11, |
| 12, |
| 13, |
| 14, |
| 15, |
| 16, |
| 17, |
| 18, |
| 19, |
| 20, |
| 21, |
| 22, |
| 23, |
| 24, |
| 25, |
| 26, |
| 27, |
| 28, |
| 29, |
| 30, |
| 31, |
| 0, |
| 1, |
| 2, |
| 3, |
| 4, |
| 5, |
| 6, |
| 7, |
| 0, |
| 1, |
| 2, |
| 3, |
| 4, |
| 5, |
| 6, |
| 7, |
| 8, |
| 9, |
| 10, |
| 11, |
| 12, |
| 13, |
| 14, |
| 15, |
| 16, |
| 17, |
| 18, |
| 19, |
| 20, |
| 21, |
| 22, |
| 23, |
| 24, |
| 25, |
| 26, |
| 27, |
| 28, |
| 29, |
| 30, |
| 31, |
| 30, |
| 0, |
| 1, |
| 2, |
| 3, |
| 4, |
| 5, |
| 6, |
| 7, |
| 8, |
| 9, |
| 10, |
| 11, |
| 12, |
| 13, |
| 14, |
| 15, |
| 16, |
| 17, |
| 18, |
| 19, |
| 20, |
| 21, |
| 22, |
| 23, |
| 24, |
| 25, |
| 26, |
| 27, |
| 28, |
| 29, |
| 30, |
| 31, |
| 28, |
| 0, |
| 1, |
| 2, |
| 3, |
| 0, |
| 1, |
| 2, |
| 3, |
| 4, |
| 5, |
| 6, |
| 7, |
| 8, |
| 9, |
| 10, |
| 11, |
| 12, |
| 13, |
| 14, |
| 15, |
| 16, |
| 17, |
| 18, |
| 19, |
| 20, |
| 21, |
| 22, |
| 23, |
| 24, |
| 25, |
| 26, |
| 27, |
| 28, |
| 29, |
| 30, |
| 31, |
| 26, |
| 27, |
| 0, |
| 1, |
| 2, |
| 3, |
| 0, |
| 1, |
| 2, |
| 0, |
| 1, |
| 2, |
| 31, |
| 16, |
| 17, |
| 18, |
| 19, |
| 20, |
| 21, |
| 22, |
| 23, |
| 29, |
| 8, |
| 9, |
| 10, |
| 11, |
| 12, |
| 13, |
| 14, |
| 15, |
| 24, |
| 25, |
| 2, |
| 3, |
| 0, |
| 1, |
| 2, |
| 3, |
| 4, |
| 5, |
| 6, |
| 7, |
| 8, |
| 9, |
| 10, |
| 11, |
| 12, |
| 13, |
| 14, |
| 15, |
| 16, |
| 17, |
| 18, |
| 19, |
| 20, |
| 21, |
| 22, |
| 23, |
| 24, |
| 25, |
| 26, |
| 27, |
| 28, |
| 29, |
| 30, |
| 31, |
| 0, |
| 4, |
| 5, |
| 6, |
| 7, |
| 0, |
| 0, |
| 1, |
| 2, |
| 3, |
| 4, |
| 5, |
| 6, |
| 7, |
| 8, |
| 9, |
| 10, |
| 11, |
| 12, |
| 13, |
| 14, |
| 15, |
| 16, |
| 17, |
| 18, |
| 19, |
| 20, |
| 21, |
| 22, |
| 23, |
| 24, |
| 25, |
| 26, |
| 27, |
| 28, |
| 29, |
| 30, |
| 31, |
| 0, |
| 0, |
| 26, |
| 27, |
| 0, |
| 16, |
| 17, |
| 18, |
| 19, |
| 20, |
| 21, |
| 22, |
| 23, |
| 8, |
| 9, |
| 10, |
| 11, |
| 12, |
| 13, |
| 14, |
| 15, |
| 24, |
| 25, |
| 2, |
| 3, |
| }; |
| static inline void InitMipsMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) { |
| RI->InitMCRegisterInfo(MipsRegDesc, 418, RA, PC, MipsMCRegisterClasses, 73, MipsRegUnitRoots, 297, MipsRegDiffLists, MipsLaneMaskLists, MipsRegStrings, MipsRegClassStrings, MipsSubRegIdxLists, 12, |
| MipsSubRegIdxRanges, MipsRegEncodingTable); |
| |
| switch (DwarfFlavour) { |
| default: |
| llvm_unreachable("Unknown DWARF flavour"); |
| case 0: |
| RI->mapDwarfRegsToLLVMRegs(MipsDwarfFlavour0Dwarf2L, MipsDwarfFlavour0Dwarf2LSize, false); |
| break; |
| } |
| switch (EHFlavour) { |
| default: |
| llvm_unreachable("Unknown DWARF flavour"); |
| case 0: |
| RI->mapDwarfRegsToLLVMRegs(MipsEHFlavour0Dwarf2L, MipsEHFlavour0Dwarf2LSize, true); |
| break; |
| } |
| switch (DwarfFlavour) { |
| default: |
| llvm_unreachable("Unknown DWARF flavour"); |
| case 0: |
| RI->mapLLVMRegsToDwarfRegs(MipsDwarfFlavour0L2Dwarf, MipsDwarfFlavour0L2DwarfSize, false); |
| break; |
| } |
| switch (EHFlavour) { |
| default: |
| llvm_unreachable("Unknown DWARF flavour"); |
| case 0: |
| RI->mapLLVMRegsToDwarfRegs(MipsEHFlavour0L2Dwarf, MipsEHFlavour0L2DwarfSize, true); |
| break; |
| } |
| } |
| |
| } // end namespace llvm |
| |
| #endif // GET_REGINFO_MC_DESC |
| |
| /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
| |* *| |
| |* Register Information Header Fragment *| |
| |* *| |
| |* Automatically generated file, do not edit! *| |
| |* *| |
| \*===----------------------------------------------------------------------===*/ |
| |
| |
| #ifdef GET_REGINFO_HEADER |
| #undef GET_REGINFO_HEADER |
| |
| #include "llvm/CodeGen/TargetRegisterInfo.h" |
| |
| namespace llvm { |
| |
| class MipsFrameLowering; |
| |
| struct MipsGenRegisterInfo : public TargetRegisterInfo { |
| explicit MipsGenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0, |
| unsigned PC = 0, unsigned HwMode = 0); |
| unsigned composeSubRegIndicesImpl(unsigned, unsigned) const override; |
| LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override; |
| LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override; |
| const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const override; |
| const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override; |
| unsigned getRegUnitWeight(unsigned RegUnit) const override; |
| unsigned getNumRegPressureSets() const override; |
| const char *getRegPressureSetName(unsigned Idx) const override; |
| unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override; |
| const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override; |
| const int *getRegUnitPressureSets(unsigned RegUnit) const override; |
| ArrayRef<const char *> getRegMaskNames() const override; |
| ArrayRef<const uint32_t *> getRegMasks() const override; |
| /// Devirtualized TargetFrameLowering. |
| static const MipsFrameLowering *getFrameLowering( |
| const MachineFunction &MF); |
| }; |
| |
| namespace Mips { // Register classes |
| extern const TargetRegisterClass MSA128F16RegClass; |
| extern const TargetRegisterClass MSA128F16_with_sub_64_in_OddSPRegClass; |
| extern const TargetRegisterClass OddSPRegClass; |
| extern const TargetRegisterClass CCRRegClass; |
| extern const TargetRegisterClass COP0RegClass; |
| extern const TargetRegisterClass COP2RegClass; |
| extern const TargetRegisterClass COP3RegClass; |
| extern const TargetRegisterClass DSPRRegClass; |
| extern const TargetRegisterClass FGR32RegClass; |
| extern const TargetRegisterClass FGRCCRegClass; |
| extern const TargetRegisterClass FGRH32RegClass; |
| extern const TargetRegisterClass GPR32RegClass; |
| extern const TargetRegisterClass HWRegsRegClass; |
| extern const TargetRegisterClass GPR32NONZERORegClass; |
| extern const TargetRegisterClass OddSP_with_sub_hiRegClass; |
| extern const TargetRegisterClass FGR32_and_OddSPRegClass; |
| extern const TargetRegisterClass FGRH32_and_OddSPRegClass; |
| extern const TargetRegisterClass OddSP_with_sub_hi_with_sub_hi_in_FGRH32RegClass; |
| extern const TargetRegisterClass CPU16RegsPlusSPRegClass; |
| extern const TargetRegisterClass CPU16RegsRegClass; |
| extern const TargetRegisterClass FCCRegClass; |
| extern const TargetRegisterClass GPRMM16RegClass; |
| extern const TargetRegisterClass GPRMM16MovePRegClass; |
| extern const TargetRegisterClass GPRMM16ZeroRegClass; |
| extern const TargetRegisterClass MSACtrlRegClass; |
| extern const TargetRegisterClass OddSP_with_sub_hi_with_sub_hi_in_FGR32RegClass; |
| extern const TargetRegisterClass CPU16Regs_and_GPRMM16ZeroRegClass; |
| extern const TargetRegisterClass GPR32NONZERO_and_GPRMM16MovePRegClass; |
| extern const TargetRegisterClass CPU16Regs_and_GPRMM16MovePRegClass; |
| extern const TargetRegisterClass GPRMM16MoveP_and_GPRMM16ZeroRegClass; |
| extern const TargetRegisterClass HI32DSPRegClass; |
| extern const TargetRegisterClass LO32DSPRegClass; |
| extern const TargetRegisterClass GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass; |
| extern const TargetRegisterClass CPURARegRegClass; |
| extern const TargetRegisterClass CPUSPRegRegClass; |
| extern const TargetRegisterClass DSPCCRegClass; |
| extern const TargetRegisterClass GP32RegClass; |
| extern const TargetRegisterClass GPR32ZERORegClass; |
| extern const TargetRegisterClass HI32RegClass; |
| extern const TargetRegisterClass LO32RegClass; |
| extern const TargetRegisterClass SP32RegClass; |
| extern const TargetRegisterClass FGR64RegClass; |
| extern const TargetRegisterClass GPR64RegClass; |
| extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32NONZERORegClass; |
| extern const TargetRegisterClass AFGR64RegClass; |
| extern const TargetRegisterClass FGR64_and_OddSPRegClass; |
| extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass; |
| extern const TargetRegisterClass AFGR64_and_OddSPRegClass; |
| extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16RegsRegClass; |
| extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePRegClass; |
| extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16ZeroRegClass; |
| extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClass; |
| extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClass; |
| extern const TargetRegisterClass ACC64DSPRegClass; |
| extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClass; |
| extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClass; |
| extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass; |
| extern const TargetRegisterClass OCTEON_MPLRegClass; |
| extern const TargetRegisterClass OCTEON_PRegClass; |
| extern const TargetRegisterClass ACC64RegClass; |
| extern const TargetRegisterClass GP64RegClass; |
| extern const TargetRegisterClass GPR64_with_sub_32_in_CPURARegRegClass; |
| extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32ZERORegClass; |
| extern const TargetRegisterClass HI64RegClass; |
| extern const TargetRegisterClass LO64RegClass; |
| extern const TargetRegisterClass SP64RegClass; |
| extern const TargetRegisterClass MSA128BRegClass; |
| extern const TargetRegisterClass MSA128DRegClass; |
| extern const TargetRegisterClass MSA128HRegClass; |
| extern const TargetRegisterClass MSA128WRegClass; |
| extern const TargetRegisterClass MSA128B_with_sub_64_in_OddSPRegClass; |
| extern const TargetRegisterClass MSA128WEvensRegClass; |
| extern const TargetRegisterClass ACC128RegClass; |
| } // end namespace Mips |
| |
| } // end namespace llvm |
| |
| #endif // GET_REGINFO_HEADER |
| |
| /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
| |* *| |
| |* Target Register and Register Classes Information *| |
| |* *| |
| |* Automatically generated file, do not edit! *| |
| |* *| |
| \*===----------------------------------------------------------------------===*/ |
| |
| |
| #ifdef GET_REGINFO_TARGET_DESC |
| #undef GET_REGINFO_TARGET_DESC |
| |
| namespace llvm { |
| |
| extern const MCRegisterClass MipsMCRegisterClasses[]; |
| |
| static const MVT::SimpleValueType VTLists[] = { |
| /* 0 */ MVT::i32, MVT::Other, |
| /* 2 */ MVT::i64, MVT::Other, |
| /* 4 */ MVT::f16, MVT::Other, |
| /* 6 */ MVT::f32, MVT::Other, |
| /* 8 */ MVT::f64, MVT::Other, |
| /* 10 */ MVT::v16i8, MVT::Other, |
| /* 12 */ MVT::v4i8, MVT::v2i16, MVT::Other, |
| /* 15 */ MVT::v8i16, MVT::v8f16, MVT::Other, |
| /* 18 */ MVT::v4i32, MVT::v4f32, MVT::Other, |
| /* 21 */ MVT::v2i64, MVT::v2f64, MVT::Other, |
| /* 24 */ MVT::Untyped, MVT::Other, |
| }; |
| |
| static const char *const SubRegIndexNameTable[] = { "sub_32", "sub_64", "sub_dsp16_19", "sub_dsp20", "sub_dsp21", "sub_dsp22", "sub_dsp23", "sub_hi", "sub_lo", "sub_hi_then_sub_32", "sub_32_sub_hi_then_sub_32", "" }; |
| |
| |
| static const LaneBitmask SubRegIndexLaneMaskTable[] = { |
| LaneBitmask::getAll(), |
| LaneBitmask(0x00000001), // sub_32 |
| LaneBitmask(0x00000041), // sub_64 |
| LaneBitmask(0x00000002), // sub_dsp16_19 |
| LaneBitmask(0x00000004), // sub_dsp20 |
| LaneBitmask(0x00000008), // sub_dsp21 |
| LaneBitmask(0x00000010), // sub_dsp22 |
| LaneBitmask(0x00000020), // sub_dsp23 |
| LaneBitmask(0x00000040), // sub_hi |
| LaneBitmask(0x00000001), // sub_lo |
| LaneBitmask(0x00000040), // sub_hi_then_sub_32 |
| LaneBitmask(0x00000041), // sub_32_sub_hi_then_sub_32 |
| }; |
| |
| |
| |
| static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = { |
| // Mode = 0 (Default) |
| { 16, 16, 128, VTLists+4 }, // MSA128F16 |
| { 16, 16, 128, VTLists+4 }, // MSA128F16_with_sub_64_in_OddSP |
| { 32, 32, 32, VTLists+6 }, // OddSP |
| { 32, 32, 32, VTLists+0 }, // CCR |
| { 32, 32, 32, VTLists+0 }, // COP0 |
| { 32, 32, 32, VTLists+0 }, // COP2 |
| { 32, 32, 32, VTLists+0 }, // COP3 |
| { 32, 32, 32, VTLists+12 }, // DSPR |
| { 32, 32, 32, VTLists+6 }, // FGR32 |
| { 32, 32, 32, VTLists+0 }, // FGRCC |
| { 32, 32, 32, VTLists+6 }, // FGRH32 |
| { 32, 32, 32, VTLists+0 }, // GPR32 |
| { 32, 32, 32, VTLists+0 }, // HWRegs |
| { 32, 32, 32, VTLists+0 }, // GPR32NONZERO |
| { 32, 32, 32, VTLists+6 }, // OddSP_with_sub_hi |
| { 32, 32, 32, VTLists+0 }, // FGR32_and_OddSP |
| { 32, 32, 32, VTLists+6 }, // FGRH32_and_OddSP |
| { 32, 32, 32, VTLists+6 }, // OddSP_with_sub_hi_with_sub_hi_in_FGRH32 |
| { 32, 32, 32, VTLists+0 }, // CPU16RegsPlusSP |
| { 32, 32, 32, VTLists+0 }, // CPU16Regs |
| { 32, 32, 32, VTLists+0 }, // FCC |
| { 32, 32, 32, VTLists+0 }, // GPRMM16 |
| { 32, 32, 32, VTLists+0 }, // GPRMM16MoveP |
| { 32, 32, 32, VTLists+0 }, // GPRMM16Zero |
| { 32, 32, 32, VTLists+0 }, // MSACtrl |
| { 32, 32, 32, VTLists+6 }, // OddSP_with_sub_hi_with_sub_hi_in_FGR32 |
| { 32, 32, 32, VTLists+0 }, // CPU16Regs_and_GPRMM16Zero |
| { 32, 32, 32, VTLists+0 }, // GPR32NONZERO_and_GPRMM16MoveP |
| { 32, 32, 32, VTLists+0 }, // CPU16Regs_and_GPRMM16MoveP |
| { 32, 32, 32, VTLists+0 }, // GPRMM16MoveP_and_GPRMM16Zero |
| { 32, 32, 32, VTLists+0 }, // HI32DSP |
| { 32, 32, 32, VTLists+0 }, // LO32DSP |
| { 32, 32, 32, VTLists+0 }, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero |
| { 32, 32, 32, VTLists+0 }, // CPURAReg |
| { 32, 32, 32, VTLists+0 }, // CPUSPReg |
| { 32, 32, 32, VTLists+12 }, // DSPCC |
| { 32, 32, 32, VTLists+0 }, // GP32 |
| { 32, 32, 32, VTLists+0 }, // GPR32ZERO |
| { 32, 32, 32, VTLists+0 }, // HI32 |
| { 32, 32, 32, VTLists+0 }, // LO32 |
| { 32, 32, 32, VTLists+0 }, // SP32 |
| { 64, 64, 64, VTLists+8 }, // FGR64 |
| { 64, 64, 64, VTLists+2 }, // GPR64 |
| { 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_GPR32NONZERO |
| { 64, 64, 64, VTLists+8 }, // AFGR64 |
| { 64, 64, 64, VTLists+8 }, // FGR64_and_OddSP |
| { 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_CPU16RegsPlusSP |
| { 64, 64, 64, VTLists+8 }, // AFGR64_and_OddSP |
| { 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_CPU16Regs |
| { 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_GPRMM16MoveP |
| { 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_GPRMM16Zero |
| { 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero |
| { 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP |
| { 64, 64, 64, VTLists+24 }, // ACC64DSP |
| { 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP |
| { 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero |
| { 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero |
| { 64, 64, 64, VTLists+2 }, // OCTEON_MPL |
| { 64, 64, 64, VTLists+2 }, // OCTEON_P |
| { 64, 64, 64, VTLists+24 }, // ACC64 |
| { 64, 64, 64, VTLists+2 }, // GP64 |
| { 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_CPURAReg |
| { 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_GPR32ZERO |
| { 64, 64, 64, VTLists+2 }, // HI64 |
| { 64, 64, 64, VTLists+2 }, // LO64 |
| { 64, 64, 64, VTLists+2 }, // SP64 |
| { 128, 128, 128, VTLists+10 }, // MSA128B |
| { 128, 128, 128, VTLists+21 }, // MSA128D |
| { 128, 128, 128, VTLists+15 }, // MSA128H |
| { 128, 128, 128, VTLists+18 }, // MSA128W |
| { 128, 128, 128, VTLists+18 }, // MSA128B_with_sub_64_in_OddSP |
| { 128, 128, 128, VTLists+18 }, // MSA128WEvens |
| { 128, 128, 128, VTLists+24 }, // ACC128 |
| }; |
| |
| static const TargetRegisterClass *const NullRegClasses[] = { nullptr }; |
| |
| static const uint32_t MSA128F16SubClassMask[] = { |
| 0x00000003, 0x00000000, 0x000000fc, |
| }; |
| |
| static const uint32_t MSA128F16_with_sub_64_in_OddSPSubClassMask[] = { |
| 0x00000002, 0x00000000, 0x00000040, |
| }; |
| |
| static const uint32_t OddSPSubClassMask[] = { |
| 0x0203c004, 0x0000a000, 0x00000000, |
| 0x00000002, 0x00000000, 0x00000040, // sub_64 |
| 0x02024002, 0x0000b000, 0x00000040, // sub_hi |
| 0x00020002, 0x00002000, 0x00000040, // sub_lo |
| }; |
| |
| static const uint32_t CCRSubClassMask[] = { |
| 0x00000008, 0x00000000, 0x00000000, |
| }; |
| |
| static const uint32_t COP0SubClassMask[] = { |
| 0x00000010, 0x00000000, 0x00000000, |
| }; |
| |
| static const uint32_t COP2SubClassMask[] = { |
| 0x00000020, 0x00000000, 0x00000000, |
| }; |
| |
| static const uint32_t COP3SubClassMask[] = { |
| 0x00000040, 0x00000000, 0x00000000, |
| }; |
| |
| static const uint32_t DSPRSubClassMask[] = { |
| 0x3cec2880, 0x00000137, 0x00000000, |
| 0x00000000, 0x71df4c00, 0x00000002, // sub_32 |
| }; |
| |
| static const uint32_t FGR32SubClassMask[] = { |
| 0x00008300, 0x00000000, 0x00000000, |
| 0x02000000, 0x00009000, 0x00000000, // sub_hi |
| 0x02024003, 0x0000b200, 0x000000fc, // sub_lo |
| }; |
| |
| static const uint32_t FGRCCSubClassMask[] = { |
| 0x00008300, 0x00000000, 0x00000000, |
| 0x02000000, 0x00009000, 0x00000000, // sub_hi |
| 0x02024003, 0x0000b200, 0x000000fc, // sub_lo |
| }; |
| |
| static const uint32_t FGRH32SubClassMask[] = { |
| 0x00010400, 0x00000000, 0x00000000, |
| 0x00020003, 0x00002200, 0x000000fc, // sub_hi |
| }; |
| |
| static const uint32_t GPR32SubClassMask[] = { |
| 0x3cec2800, 0x00000137, 0x00000000, |
| 0x00000000, 0x71df4c00, 0x00000002, // sub_32 |
| }; |
| |
| static const uint32_t HWRegsSubClassMask[] = { |
| 0x00001000, 0x00000000, 0x00000000, |
| }; |
| |
| static const uint32_t GPR32NONZEROSubClassMask[] = { |
| 0x1c2c2000, 0x00000117, 0x00000000, |
| 0x00000000, 0x31594800, 0x00000002, // sub_32 |
| }; |
| |
| static const uint32_t OddSP_with_sub_hiSubClassMask[] = { |
| 0x02024000, 0x0000a000, 0x00000000, |
| 0x00000002, 0x00000000, 0x00000040, // sub_64 |
| }; |
| |
| static const uint32_t FGR32_and_OddSPSubClassMask[] = { |
| 0x00008000, 0x00000000, 0x00000000, |
| 0x02000000, 0x00009000, 0x00000000, // sub_hi |
| 0x00020002, 0x00002000, 0x00000040, // sub_lo |
| }; |
| |
| static const uint32_t FGRH32_and_OddSPSubClassMask[] = { |
| 0x00010000, 0x00000000, 0x00000000, |
| 0x00020002, 0x00002000, 0x00000040, // sub_hi |
| }; |
| |
| static const uint32_t OddSP_with_sub_hi_with_sub_hi_in_FGRH32SubClassMask[] = { |
| 0x00020000, 0x00002000, 0x00000000, |
| 0x00000002, 0x00000000, 0x00000040, // sub_64 |
| }; |
| |
| static const uint32_t CPU16RegsPlusSPSubClassMask[] = { |
| 0x142c0000, 0x00000105, 0x00000000, |
| 0x00000000, 0x01494000, 0x00000002, // sub_32 |
| }; |
| |
| static const uint32_t CPU16RegsSubClassMask[] = { |
| 0x14280000, 0x00000001, 0x00000000, |
| 0x00000000, 0x01490000, 0x00000000, // sub_32 |
| }; |
| |
| static const uint32_t FCCSubClassMask[] = { |
| 0x00100000, 0x00000000, 0x00000000, |
| }; |
| |
| static const uint32_t GPRMM16SubClassMask[] = { |
| 0x14200000, 0x00000001, 0x00000000, |
| 0x00000000, 0x01490000, 0x00000000, // sub_32 |
| }; |
| |
| static const uint32_t GPRMM16MovePSubClassMask[] = { |
| 0x38400000, 0x00000021, 0x00000000, |
| 0x00000000, 0x41d20000, 0x00000000, // sub_32 |
| }; |
| |
| static const uint32_t GPRMM16ZeroSubClassMask[] = { |
| 0x24800000, 0x00000021, 0x00000000, |
| 0x00000000, 0x418c0000, 0x00000000, // sub_32 |
| }; |
| |
| static const uint32_t MSACtrlSubClassMask[] = { |
| 0x01000000, 0x00000000, 0x00000000, |
| }; |
| |
| static const uint32_t OddSP_with_sub_hi_with_sub_hi_in_FGR32SubClassMask[] = { |
| 0x02000000, 0x00008000, 0x00000000, |
| }; |
| |
| static const uint32_t CPU16Regs_and_GPRMM16ZeroSubClassMask[] = { |
| 0x04000000, 0x00000001, 0x00000000, |
| 0x00000000, 0x01080000, 0x00000000, // sub_32 |
| }; |
| |
| static const uint32_t GPR32NONZERO_and_GPRMM16MovePSubClassMask[] = { |
| 0x18000000, 0x00000001, 0x00000000, |
| 0x00000000, 0x01500000, 0x00000000, // sub_32 |
| }; |
| |
| static const uint32_t CPU16Regs_and_GPRMM16MovePSubClassMask[] = { |
| 0x10000000, 0x00000001, 0x00000000, |
| 0x00000000, 0x01400000, 0x00000000, // sub_32 |
| }; |
| |
| static const uint32_t GPRMM16MoveP_and_GPRMM16ZeroSubClassMask[] = { |
| 0x20000000, 0x00000021, 0x00000000, |
| 0x00000000, 0x41800000, 0x00000000, // sub_32 |
| }; |
| |
| static const uint32_t HI32DSPSubClassMask[] = { |
| 0x40000000, 0x00000040, 0x00000000, |
| 0x00000000, 0x80000000, 0x00000000, // sub_32 |
| 0x00000000, 0x08200000, 0x00000000, // sub_hi |
| 0x00000000, 0x00000000, 0x00000100, // sub_hi_then_sub_32 |
| }; |
| |
| static const uint32_t LO32DSPSubClassMask[] = { |
| 0x80000000, 0x00000080, 0x00000000, |
| 0x00000000, 0x00000000, 0x00000101, // sub_32 |
| 0x00000000, 0x08200000, 0x00000000, // sub_lo |
| }; |
| |
| static const uint32_t GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSubClassMask[] = { |
| 0x00000000, 0x00000001, 0x00000000, |
| 0x00000000, 0x01000000, 0x00000000, // sub_32 |
| }; |
| |
| static const uint32_t CPURARegSubClassMask[] = { |
| 0x00000000, 0x00000002, 0x00000000, |
| 0x00000000, 0x20000000, 0x00000000, // sub_32 |
| }; |
| |
| static const uint32_t CPUSPRegSubClassMask[] = { |
| 0x00000000, 0x00000104, 0x00000000, |
| 0x00000000, 0x00000000, 0x00000002, // sub_32 |
| }; |
| |
| static const uint32_t DSPCCSubClassMask[] = { |
| 0x00000000, 0x00000008, 0x00000000, |
| }; |
| |
| static const uint32_t GP32SubClassMask[] = { |
| 0x00000000, 0x00000010, 0x00000000, |
| 0x00000000, 0x10000000, 0x00000000, // sub_32 |
| }; |
| |
| static const uint32_t GPR32ZEROSubClassMask[] = { |
| 0x00000000, 0x00000020, 0x00000000, |
| 0x00000000, 0x40000000, 0x00000000, // sub_32 |
| }; |
| |
| static const uint32_t HI32SubClassMask[] = { |
| 0x00000000, 0x00000040, 0x00000000, |
| 0x00000000, 0x80000000, 0x00000000, // sub_32 |
| 0x00000000, 0x08000000, 0x00000000, // sub_hi |
| 0x00000000, 0x00000000, 0x00000100, // sub_hi_then_sub_32 |
| }; |
| |
| static const uint32_t LO32SubClassMask[] = { |
| 0x00000000, 0x00000080, 0x00000000, |
| 0x00000000, 0x00000000, 0x00000101, // sub_32 |
| 0x00000000, 0x08000000, 0x00000000, // sub_lo |
| }; |
| |
| static const uint32_t SP32SubClassMask[] = { |
| 0x00000000, 0x00000100, 0x00000000, |
| 0x00000000, 0x00000000, 0x00000002, // sub_32 |
| }; |
| |
| static const uint32_t FGR64SubClassMask[] = { |
| 0x00000000, 0x00002200, 0x00000000, |
| 0x00000003, 0x00000000, 0x000000fc, // sub_64 |
| }; |
| |
| static const uint32_t GPR64SubClassMask[] = { |
| 0x00000000, 0x71df4c00, 0x00000002, |
| }; |
| |
| static const uint32_t GPR64_with_sub_32_in_GPR32NONZEROSubClassMask[] = { |
| 0x00000000, 0x31594800, 0x00000002, |
| }; |
| |
| static const uint32_t AFGR64SubClassMask[] = { |
| 0x00000000, 0x00009000, 0x00000000, |
| }; |
| |
| static const uint32_t FGR64_and_OddSPSubClassMask[] = { |
| 0x00000000, 0x00002000, 0x00000000, |
| 0x00000002, 0x00000000, 0x00000040, // sub_64 |
| }; |
| |
| static const uint32_t GPR64_with_sub_32_in_CPU16RegsPlusSPSubClassMask[] = { |
| 0x00000000, 0x01494000, 0x00000002, |
| }; |
| |
| static const uint32_t AFGR64_and_OddSPSubClassMask[] = { |
| 0x00000000, 0x00008000, 0x00000000, |
| }; |
| |
| static const uint32_t GPR64_with_sub_32_in_CPU16RegsSubClassMask[] = { |
| 0x00000000, 0x01490000, 0x00000000, |
| }; |
| |
| static const uint32_t GPR64_with_sub_32_in_GPRMM16MovePSubClassMask[] = { |
| 0x00000000, 0x41d20000, 0x00000000, |
| }; |
| |
| static const uint32_t GPR64_with_sub_32_in_GPRMM16ZeroSubClassMask[] = { |
| 0x00000000, 0x418c0000, 0x00000000, |
| }; |
| |
| static const uint32_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroSubClassMask[] = { |
| 0x00000000, 0x01080000, 0x00000000, |
| }; |
| |
| static const uint32_t GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePSubClassMask[] = { |
| 0x00000000, 0x01500000, 0x00000000, |
| }; |
| |
| static const uint32_t ACC64DSPSubClassMask[] = { |
| 0x00000000, 0x08200000, 0x00000000, |
| 0x00000000, 0x00000000, 0x00000100, // sub_32_sub_hi_then_sub_32 |
| }; |
| |
| static const uint32_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePSubClassMask[] = { |
| 0x00000000, 0x01400000, 0x00000000, |
| }; |
| |
| static const uint32_t GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroSubClassMask[] = { |
| 0x00000000, 0x41800000, 0x00000000, |
| }; |
| |
| static const uint32_t GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSubClassMask[] = { |
| 0x00000000, 0x01000000, 0x00000000, |
| }; |
| |
| static const uint32_t OCTEON_MPLSubClassMask[] = { |
| 0x00000000, 0x02000000, 0x00000000, |
| }; |
| |
| static const uint32_t OCTEON_PSubClassMask[] = { |
| 0x00000000, 0x04000000, 0x00000000, |
| }; |
| |
| static const uint32_t ACC64SubClassMask[] = { |
| 0x00000000, 0x08000000, 0x00000000, |
| 0x00000000, 0x00000000, 0x00000100, // sub_32_sub_hi_then_sub_32 |
| }; |
| |
| static const uint32_t GP64SubClassMask[] = { |
| 0x00000000, 0x10000000, 0x00000000, |
| }; |
| |
| static const uint32_t GPR64_with_sub_32_in_CPURARegSubClassMask[] = { |
| 0x00000000, 0x20000000, 0x00000000, |
| }; |
| |
| static const uint32_t GPR64_with_sub_32_in_GPR32ZEROSubClassMask[] = { |
| 0x00000000, 0x40000000, 0x00000000, |
| }; |
| |
| static const uint32_t HI64SubClassMask[] = { |
| 0x00000000, 0x80000000, 0x00000000, |
| 0x00000000, 0x00000000, 0x00000100, // sub_hi |
| }; |
| |
| static const uint32_t LO64SubClassMask[] = { |
| 0x00000000, 0x00000000, 0x00000001, |
| 0x00000000, 0x00000000, 0x00000100, // sub_lo |
| }; |
| |
| static const uint32_t SP64SubClassMask[] = { |
| 0x00000000, 0x00000000, 0x00000002, |
| }; |
| |
| static const uint32_t MSA128BSubClassMask[] = { |
| 0x00000000, 0x00000000, 0x000000fc, |
| }; |
| |
| static const uint32_t MSA128DSubClassMask[] = { |
| 0x00000000, 0x00000000, 0x000000fc, |
| }; |
| |
| static const uint32_t MSA128HSubClassMask[] = { |
| 0x00000000, 0x00000000, 0x000000fc, |
| }; |
| |
| static const uint32_t MSA128WSubClassMask[] = { |
| 0x00000000, 0x00000000, 0x000000fc, |
| }; |
| |
| static const uint32_t MSA128B_with_sub_64_in_OddSPSubClassMask[] = { |
| 0x00000000, 0x00000000, 0x00000040, |
| }; |
| |
| static const uint32_t MSA128WEvensSubClassMask[] = { |
| 0x00000000, 0x00000000, 0x00000080, |
| }; |
| |
| static const uint32_t ACC128SubClassMask[] = { |
| 0x00000000, 0x00000000, 0x00000100, |
| }; |
| |
| static const uint16_t SuperRegIdxSeqs[] = { |
| /* 0 */ 1, 0, |
| /* 2 */ 2, 0, |
| /* 4 */ 8, 0, |
| /* 6 */ 1, 9, 0, |
| /* 9 */ 2, 8, 9, 0, |
| /* 13 */ 1, 8, 10, 0, |
| /* 17 */ 11, 0, |
| }; |
| |
| static const TargetRegisterClass *const MSA128F16_with_sub_64_in_OddSPSuperclasses[] = { |
| &Mips::MSA128F16RegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const FGR32Superclasses[] = { |
| &Mips::FGRCCRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const FGRCCSuperclasses[] = { |
| &Mips::FGR32RegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const GPR32Superclasses[] = { |
| &Mips::DSPRRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const GPR32NONZEROSuperclasses[] = { |
| &Mips::DSPRRegClass, |
| &Mips::GPR32RegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const OddSP_with_sub_hiSuperclasses[] = { |
| &Mips::OddSPRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const FGR32_and_OddSPSuperclasses[] = { |
| &Mips::OddSPRegClass, |
| &Mips::FGR32RegClass, |
| &Mips::FGRCCRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const FGRH32_and_OddSPSuperclasses[] = { |
| &Mips::OddSPRegClass, |
| &Mips::FGRH32RegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const OddSP_with_sub_hi_with_sub_hi_in_FGRH32Superclasses[] = { |
| &Mips::OddSPRegClass, |
| &Mips::OddSP_with_sub_hiRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const CPU16RegsPlusSPSuperclasses[] = { |
| &Mips::DSPRRegClass, |
| &Mips::GPR32RegClass, |
| &Mips::GPR32NONZERORegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const CPU16RegsSuperclasses[] = { |
| &Mips::DSPRRegClass, |
| &Mips::GPR32RegClass, |
| &Mips::GPR32NONZERORegClass, |
| &Mips::CPU16RegsPlusSPRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const GPRMM16Superclasses[] = { |
| &Mips::DSPRRegClass, |
| &Mips::GPR32RegClass, |
| &Mips::GPR32NONZERORegClass, |
| &Mips::CPU16RegsPlusSPRegClass, |
| &Mips::CPU16RegsRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const GPRMM16MovePSuperclasses[] = { |
| &Mips::DSPRRegClass, |
| &Mips::GPR32RegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const GPRMM16ZeroSuperclasses[] = { |
| &Mips::DSPRRegClass, |
| &Mips::GPR32RegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const OddSP_with_sub_hi_with_sub_hi_in_FGR32Superclasses[] = { |
| &Mips::OddSPRegClass, |
| &Mips::OddSP_with_sub_hiRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const CPU16Regs_and_GPRMM16ZeroSuperclasses[] = { |
| &Mips::DSPRRegClass, |
| &Mips::GPR32RegClass, |
| &Mips::GPR32NONZERORegClass, |
| &Mips::CPU16RegsPlusSPRegClass, |
| &Mips::CPU16RegsRegClass, |
| &Mips::GPRMM16RegClass, |
| &Mips::GPRMM16ZeroRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const GPR32NONZERO_and_GPRMM16MovePSuperclasses[] = { |
| &Mips::DSPRRegClass, |
| &Mips::GPR32RegClass, |
| &Mips::GPR32NONZERORegClass, |
| &Mips::GPRMM16MovePRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const CPU16Regs_and_GPRMM16MovePSuperclasses[] = { |
| &Mips::DSPRRegClass, |
| &Mips::GPR32RegClass, |
| &Mips::GPR32NONZERORegClass, |
| &Mips::CPU16RegsPlusSPRegClass, |
| &Mips::CPU16RegsRegClass, |
| &Mips::GPRMM16RegClass, |
| &Mips::GPRMM16MovePRegClass, |
| &Mips::GPR32NONZERO_and_GPRMM16MovePRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const GPRMM16MoveP_and_GPRMM16ZeroSuperclasses[] = { |
| &Mips::DSPRRegClass, |
| &Mips::GPR32RegClass, |
| &Mips::GPRMM16MovePRegClass, |
| &Mips::GPRMM16ZeroRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSuperclasses[] = { |
| &Mips::DSPRRegClass, |
| &Mips::GPR32RegClass, |
| &Mips::GPR32NONZERORegClass, |
| &Mips::CPU16RegsPlusSPRegClass, |
| &Mips::CPU16RegsRegClass, |
| &Mips::GPRMM16RegClass, |
| &Mips::GPRMM16MovePRegClass, |
| &Mips::GPRMM16ZeroRegClass, |
| &Mips::CPU16Regs_and_GPRMM16ZeroRegClass, |
| &Mips::GPR32NONZERO_and_GPRMM16MovePRegClass, |
| &Mips::CPU16Regs_and_GPRMM16MovePRegClass, |
| &Mips::GPRMM16MoveP_and_GPRMM16ZeroRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const CPURARegSuperclasses[] = { |
| &Mips::DSPRRegClass, |
| &Mips::GPR32RegClass, |
| &Mips::GPR32NONZERORegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const CPUSPRegSuperclasses[] = { |
| &Mips::DSPRRegClass, |
| &Mips::GPR32RegClass, |
| &Mips::GPR32NONZERORegClass, |
| &Mips::CPU16RegsPlusSPRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const GP32Superclasses[] = { |
| &Mips::DSPRRegClass, |
| &Mips::GPR32RegClass, |
| &Mips::GPR32NONZERORegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const GPR32ZEROSuperclasses[] = { |
| &Mips::DSPRRegClass, |
| &Mips::GPR32RegClass, |
| &Mips::GPRMM16MovePRegClass, |
| &Mips::GPRMM16ZeroRegClass, |
| &Mips::GPRMM16MoveP_and_GPRMM16ZeroRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const HI32Superclasses[] = { |
| &Mips::HI32DSPRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const LO32Superclasses[] = { |
| &Mips::LO32DSPRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const SP32Superclasses[] = { |
| &Mips::DSPRRegClass, |
| &Mips::GPR32RegClass, |
| &Mips::GPR32NONZERORegClass, |
| &Mips::CPU16RegsPlusSPRegClass, |
| &Mips::CPUSPRegRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const GPR64_with_sub_32_in_GPR32NONZEROSuperclasses[] = { |
| &Mips::GPR64RegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const FGR64_and_OddSPSuperclasses[] = { |
| &Mips::OddSPRegClass, |
| &Mips::OddSP_with_sub_hiRegClass, |
| &Mips::OddSP_with_sub_hi_with_sub_hi_in_FGRH32RegClass, |
| &Mips::FGR64RegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const GPR64_with_sub_32_in_CPU16RegsPlusSPSuperclasses[] = { |
| &Mips::GPR64RegClass, |
| &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const AFGR64_and_OddSPSuperclasses[] = { |
| &Mips::OddSPRegClass, |
| &Mips::OddSP_with_sub_hiRegClass, |
| &Mips::OddSP_with_sub_hi_with_sub_hi_in_FGR32RegClass, |
| &Mips::AFGR64RegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const GPR64_with_sub_32_in_CPU16RegsSuperclasses[] = { |
| &Mips::GPR64RegClass, |
| &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass, |
| &Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const GPR64_with_sub_32_in_GPRMM16MovePSuperclasses[] = { |
| &Mips::GPR64RegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const GPR64_with_sub_32_in_GPRMM16ZeroSuperclasses[] = { |
| &Mips::GPR64RegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroSuperclasses[] = { |
| &Mips::GPR64RegClass, |
| &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass, |
| &Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass, |
| &Mips::GPR64_with_sub_32_in_CPU16RegsRegClass, |
| &Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePSuperclasses[] = { |
| &Mips::GPR64RegClass, |
| &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass, |
| &Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePSuperclasses[] = { |
| &Mips::GPR64RegClass, |
| &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass, |
| &Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass, |
| &Mips::GPR64_with_sub_32_in_CPU16RegsRegClass, |
| &Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClass, |
| &Mips::GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroSuperclasses[] = { |
| &Mips::GPR64RegClass, |
| &Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClass, |
| &Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSuperclasses[] = { |
| &Mips::GPR64RegClass, |
| &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass, |
| &Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass, |
| &Mips::GPR64_with_sub_32_in_CPU16RegsRegClass, |
| &Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClass, |
| &Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass, |
| &Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClass, |
| &Mips::GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClass, |
| &Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClass, |
| &Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const ACC64Superclasses[] = { |
| &Mips::ACC64DSPRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const GP64Superclasses[] = { |
| &Mips::GPR64RegClass, |
| &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const GPR64_with_sub_32_in_CPURARegSuperclasses[] = { |
| &Mips::GPR64RegClass, |
| &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const GPR64_with_sub_32_in_GPR32ZEROSuperclasses[] = { |
| &Mips::GPR64RegClass, |
| &Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClass, |
| &Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass, |
| &Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const SP64Superclasses[] = { |
| &Mips::GPR64RegClass, |
| &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass, |
| &Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const MSA128BSuperclasses[] = { |
| &Mips::MSA128F16RegClass, |
| &Mips::MSA128DRegClass, |
| &Mips::MSA128HRegClass, |
| &Mips::MSA128WRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const MSA128DSuperclasses[] = { |
| &Mips::MSA128F16RegClass, |
| &Mips::MSA128BRegClass, |
| &Mips::MSA128HRegClass, |
| &Mips::MSA128WRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const MSA128HSuperclasses[] = { |
| &Mips::MSA128F16RegClass, |
| &Mips::MSA128BRegClass, |
| &Mips::MSA128DRegClass, |
| &Mips::MSA128WRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const MSA128WSuperclasses[] = { |
| &Mips::MSA128F16RegClass, |
| &Mips::MSA128BRegClass, |
| &Mips::MSA128DRegClass, |
| &Mips::MSA128HRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const MSA128B_with_sub_64_in_OddSPSuperclasses[] = { |
| &Mips::MSA128F16RegClass, |
| &Mips::MSA128F16_with_sub_64_in_OddSPRegClass, |
| &Mips::MSA128BRegClass, |
| &Mips::MSA128DRegClass, |
| &Mips::MSA128HRegClass, |
| &Mips::MSA128WRegClass, |
| nullptr |
| }; |
| |
| static const TargetRegisterClass *const MSA128WEvensSuperclasses[] = { |
| &Mips::MSA128F16RegClass, |
| &Mips::MSA128BRegClass, |
| &Mips::MSA128DRegClass, |
| &Mips::MSA128HRegClass, |
| &Mips::MSA128WRegClass, |
| nullptr |
| }; |
| |
| |
| namespace Mips { // Register class instances |
| extern const TargetRegisterClass MSA128F16RegClass = { |
| &MipsMCRegisterClasses[MSA128F16RegClassID], |
| MSA128F16SubClassMask, |
| SuperRegIdxSeqs + 1, |
| LaneBitmask(0x00000041), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| NullRegClasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass MSA128F16_with_sub_64_in_OddSPRegClass = { |
| &MipsMCRegisterClasses[MSA128F16_with_sub_64_in_OddSPRegClassID], |
| MSA128F16_with_sub_64_in_OddSPSubClassMask, |
| SuperRegIdxSeqs + 1, |
| LaneBitmask(0x00000041), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| MSA128F16_with_sub_64_in_OddSPSuperclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass OddSPRegClass = { |
| &MipsMCRegisterClasses[OddSPRegClassID], |
| OddSPSubClassMask, |
| SuperRegIdxSeqs + 9, |
| LaneBitmask(0x00000041), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| NullRegClasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass CCRRegClass = { |
| &MipsMCRegisterClasses[CCRRegClassID], |
| CCRSubClassMask, |
| SuperRegIdxSeqs + 1, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| NullRegClasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass COP0RegClass = { |
| &MipsMCRegisterClasses[COP0RegClassID], |
| COP0SubClassMask, |
| SuperRegIdxSeqs + 1, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| NullRegClasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass COP2RegClass = { |
| &MipsMCRegisterClasses[COP2RegClassID], |
| COP2SubClassMask, |
| SuperRegIdxSeqs + 1, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| NullRegClasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass COP3RegClass = { |
| &MipsMCRegisterClasses[COP3RegClassID], |
| COP3SubClassMask, |
| SuperRegIdxSeqs + 1, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| NullRegClasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass DSPRRegClass = { |
| &MipsMCRegisterClasses[DSPRRegClassID], |
| DSPRSubClassMask, |
| SuperRegIdxSeqs + 0, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| NullRegClasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass FGR32RegClass = { |
| &MipsMCRegisterClasses[FGR32RegClassID], |
| FGR32SubClassMask, |
| SuperRegIdxSeqs + 10, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| FGR32Superclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass FGRCCRegClass = { |
| &MipsMCRegisterClasses[FGRCCRegClassID], |
| FGRCCSubClassMask, |
| SuperRegIdxSeqs + 10, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| FGRCCSuperclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass FGRH32RegClass = { |
| &MipsMCRegisterClasses[FGRH32RegClassID], |
| FGRH32SubClassMask, |
| SuperRegIdxSeqs + 4, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| NullRegClasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass GPR32RegClass = { |
| &MipsMCRegisterClasses[GPR32RegClassID], |
| GPR32SubClassMask, |
| SuperRegIdxSeqs + 0, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| GPR32Superclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass HWRegsRegClass = { |
| &MipsMCRegisterClasses[HWRegsRegClassID], |
| HWRegsSubClassMask, |
| SuperRegIdxSeqs + 1, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| NullRegClasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass GPR32NONZERORegClass = { |
| &MipsMCRegisterClasses[GPR32NONZERORegClassID], |
| GPR32NONZEROSubClassMask, |
| SuperRegIdxSeqs + 0, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| GPR32NONZEROSuperclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass OddSP_with_sub_hiRegClass = { |
| &MipsMCRegisterClasses[OddSP_with_sub_hiRegClassID], |
| OddSP_with_sub_hiSubClassMask, |
| SuperRegIdxSeqs + 2, |
| LaneBitmask(0x00000041), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| OddSP_with_sub_hiSuperclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass FGR32_and_OddSPRegClass = { |
| &MipsMCRegisterClasses[FGR32_and_OddSPRegClassID], |
| FGR32_and_OddSPSubClassMask, |
| SuperRegIdxSeqs + 10, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| FGR32_and_OddSPSuperclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass FGRH32_and_OddSPRegClass = { |
| &MipsMCRegisterClasses[FGRH32_and_OddSPRegClassID], |
| FGRH32_and_OddSPSubClassMask, |
| SuperRegIdxSeqs + 4, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| FGRH32_and_OddSPSuperclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass OddSP_with_sub_hi_with_sub_hi_in_FGRH32RegClass = { |
| &MipsMCRegisterClasses[OddSP_with_sub_hi_with_sub_hi_in_FGRH32RegClassID], |
| OddSP_with_sub_hi_with_sub_hi_in_FGRH32SubClassMask, |
| SuperRegIdxSeqs + 2, |
| LaneBitmask(0x00000041), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| OddSP_with_sub_hi_with_sub_hi_in_FGRH32Superclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass CPU16RegsPlusSPRegClass = { |
| &MipsMCRegisterClasses[CPU16RegsPlusSPRegClassID], |
| CPU16RegsPlusSPSubClassMask, |
| SuperRegIdxSeqs + 0, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| CPU16RegsPlusSPSuperclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass CPU16RegsRegClass = { |
| &MipsMCRegisterClasses[CPU16RegsRegClassID], |
| CPU16RegsSubClassMask, |
| SuperRegIdxSeqs + 0, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| CPU16RegsSuperclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass FCCRegClass = { |
| &MipsMCRegisterClasses[FCCRegClassID], |
| FCCSubClassMask, |
| SuperRegIdxSeqs + 1, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| NullRegClasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass GPRMM16RegClass = { |
| &MipsMCRegisterClasses[GPRMM16RegClassID], |
| GPRMM16SubClassMask, |
| SuperRegIdxSeqs + 0, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| GPRMM16Superclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass GPRMM16MovePRegClass = { |
| &MipsMCRegisterClasses[GPRMM16MovePRegClassID], |
| GPRMM16MovePSubClassMask, |
| SuperRegIdxSeqs + 0, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| GPRMM16MovePSuperclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass GPRMM16ZeroRegClass = { |
| &MipsMCRegisterClasses[GPRMM16ZeroRegClassID], |
| GPRMM16ZeroSubClassMask, |
| SuperRegIdxSeqs + 0, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| GPRMM16ZeroSuperclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass MSACtrlRegClass = { |
| &MipsMCRegisterClasses[MSACtrlRegClassID], |
| MSACtrlSubClassMask, |
| SuperRegIdxSeqs + 1, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| NullRegClasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass OddSP_with_sub_hi_with_sub_hi_in_FGR32RegClass = { |
| &MipsMCRegisterClasses[OddSP_with_sub_hi_with_sub_hi_in_FGR32RegClassID], |
| OddSP_with_sub_hi_with_sub_hi_in_FGR32SubClassMask, |
| SuperRegIdxSeqs + 1, |
| LaneBitmask(0x00000041), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| OddSP_with_sub_hi_with_sub_hi_in_FGR32Superclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass CPU16Regs_and_GPRMM16ZeroRegClass = { |
| &MipsMCRegisterClasses[CPU16Regs_and_GPRMM16ZeroRegClassID], |
| CPU16Regs_and_GPRMM16ZeroSubClassMask, |
| SuperRegIdxSeqs + 0, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| CPU16Regs_and_GPRMM16ZeroSuperclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass GPR32NONZERO_and_GPRMM16MovePRegClass = { |
| &MipsMCRegisterClasses[GPR32NONZERO_and_GPRMM16MovePRegClassID], |
| GPR32NONZERO_and_GPRMM16MovePSubClassMask, |
| SuperRegIdxSeqs + 0, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| GPR32NONZERO_and_GPRMM16MovePSuperclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass CPU16Regs_and_GPRMM16MovePRegClass = { |
| &MipsMCRegisterClasses[CPU16Regs_and_GPRMM16MovePRegClassID], |
| CPU16Regs_and_GPRMM16MovePSubClassMask, |
| SuperRegIdxSeqs + 0, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| CPU16Regs_and_GPRMM16MovePSuperclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass GPRMM16MoveP_and_GPRMM16ZeroRegClass = { |
| &MipsMCRegisterClasses[GPRMM16MoveP_and_GPRMM16ZeroRegClassID], |
| GPRMM16MoveP_and_GPRMM16ZeroSubClassMask, |
| SuperRegIdxSeqs + 0, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| GPRMM16MoveP_and_GPRMM16ZeroSuperclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass HI32DSPRegClass = { |
| &MipsMCRegisterClasses[HI32DSPRegClassID], |
| HI32DSPSubClassMask, |
| SuperRegIdxSeqs + 13, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| NullRegClasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass LO32DSPRegClass = { |
| &MipsMCRegisterClasses[LO32DSPRegClassID], |
| LO32DSPSubClassMask, |
| SuperRegIdxSeqs + 6, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| NullRegClasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass = { |
| &MipsMCRegisterClasses[GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID], |
| GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSubClassMask, |
| SuperRegIdxSeqs + 0, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSuperclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass CPURARegRegClass = { |
| &MipsMCRegisterClasses[CPURARegRegClassID], |
| CPURARegSubClassMask, |
| SuperRegIdxSeqs + 0, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| CPURARegSuperclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass CPUSPRegRegClass = { |
| &MipsMCRegisterClasses[CPUSPRegRegClassID], |
| CPUSPRegSubClassMask, |
| SuperRegIdxSeqs + 0, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| CPUSPRegSuperclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass DSPCCRegClass = { |
| &MipsMCRegisterClasses[DSPCCRegClassID], |
| DSPCCSubClassMask, |
| SuperRegIdxSeqs + 1, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| NullRegClasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass GP32RegClass = { |
| &MipsMCRegisterClasses[GP32RegClassID], |
| GP32SubClassMask, |
| SuperRegIdxSeqs + 0, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| GP32Superclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass GPR32ZERORegClass = { |
| &MipsMCRegisterClasses[GPR32ZERORegClassID], |
| GPR32ZEROSubClassMask, |
| SuperRegIdxSeqs + 0, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| GPR32ZEROSuperclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass HI32RegClass = { |
| &MipsMCRegisterClasses[HI32RegClassID], |
| HI32SubClassMask, |
| SuperRegIdxSeqs + 13, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| HI32Superclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass LO32RegClass = { |
| &MipsMCRegisterClasses[LO32RegClassID], |
| LO32SubClassMask, |
| SuperRegIdxSeqs + 6, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| LO32Superclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass SP32RegClass = { |
| &MipsMCRegisterClasses[SP32RegClassID], |
| SP32SubClassMask, |
| SuperRegIdxSeqs + 0, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| SP32Superclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass FGR64RegClass = { |
| &MipsMCRegisterClasses[FGR64RegClassID], |
| FGR64SubClassMask, |
| SuperRegIdxSeqs + 2, |
| LaneBitmask(0x00000041), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| NullRegClasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass GPR64RegClass = { |
| &MipsMCRegisterClasses[GPR64RegClassID], |
| GPR64SubClassMask, |
| SuperRegIdxSeqs + 1, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| NullRegClasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32NONZERORegClass = { |
| &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPR32NONZERORegClassID], |
| GPR64_with_sub_32_in_GPR32NONZEROSubClassMask, |
| SuperRegIdxSeqs + 1, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| GPR64_with_sub_32_in_GPR32NONZEROSuperclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass AFGR64RegClass = { |
| &MipsMCRegisterClasses[AFGR64RegClassID], |
| AFGR64SubClassMask, |
| SuperRegIdxSeqs + 1, |
| LaneBitmask(0x00000041), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| NullRegClasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass FGR64_and_OddSPRegClass = { |
| &MipsMCRegisterClasses[FGR64_and_OddSPRegClassID], |
| FGR64_and_OddSPSubClassMask, |
| SuperRegIdxSeqs + 2, |
| LaneBitmask(0x00000041), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| FGR64_and_OddSPSuperclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass = { |
| &MipsMCRegisterClasses[GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID], |
| GPR64_with_sub_32_in_CPU16RegsPlusSPSubClassMask, |
| SuperRegIdxSeqs + 1, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| GPR64_with_sub_32_in_CPU16RegsPlusSPSuperclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass AFGR64_and_OddSPRegClass = { |
| &MipsMCRegisterClasses[AFGR64_and_OddSPRegClassID], |
| AFGR64_and_OddSPSubClassMask, |
| SuperRegIdxSeqs + 1, |
| LaneBitmask(0x00000041), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| AFGR64_and_OddSPSuperclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16RegsRegClass = { |
| &MipsMCRegisterClasses[GPR64_with_sub_32_in_CPU16RegsRegClassID], |
| GPR64_with_sub_32_in_CPU16RegsSubClassMask, |
| SuperRegIdxSeqs + 1, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| GPR64_with_sub_32_in_CPU16RegsSuperclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePRegClass = { |
| &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16MovePRegClassID], |
| GPR64_with_sub_32_in_GPRMM16MovePSubClassMask, |
| SuperRegIdxSeqs + 1, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| GPR64_with_sub_32_in_GPRMM16MovePSuperclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16ZeroRegClass = { |
| &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16ZeroRegClassID], |
| GPR64_with_sub_32_in_GPRMM16ZeroSubClassMask, |
| SuperRegIdxSeqs + 1, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| GPR64_with_sub_32_in_GPRMM16ZeroSuperclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClass = { |
| &MipsMCRegisterClasses[GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClassID], |
| GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroSubClassMask, |
| SuperRegIdxSeqs + 1, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroSuperclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClass = { |
| &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClassID], |
| GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePSubClassMask, |
| SuperRegIdxSeqs + 1, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePSuperclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass ACC64DSPRegClass = { |
| &MipsMCRegisterClasses[ACC64DSPRegClassID], |
| ACC64DSPSubClassMask, |
| SuperRegIdxSeqs + 17, |
| LaneBitmask(0x00000041), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| NullRegClasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClass = { |
| &MipsMCRegisterClasses[GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClassID], |
| GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePSubClassMask, |
| SuperRegIdxSeqs + 1, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePSuperclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClass = { |
| &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClassID], |
| GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroSubClassMask, |
| SuperRegIdxSeqs + 1, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroSuperclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass = { |
| &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID], |
| GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSubClassMask, |
| SuperRegIdxSeqs + 1, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSuperclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass OCTEON_MPLRegClass = { |
| &MipsMCRegisterClasses[OCTEON_MPLRegClassID], |
| OCTEON_MPLSubClassMask, |
| SuperRegIdxSeqs + 1, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| NullRegClasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass OCTEON_PRegClass = { |
| &MipsMCRegisterClasses[OCTEON_PRegClassID], |
| OCTEON_PSubClassMask, |
| SuperRegIdxSeqs + 1, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| NullRegClasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass ACC64RegClass = { |
| &MipsMCRegisterClasses[ACC64RegClassID], |
| ACC64SubClassMask, |
| SuperRegIdxSeqs + 17, |
| LaneBitmask(0x00000041), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| ACC64Superclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass GP64RegClass = { |
| &MipsMCRegisterClasses[GP64RegClassID], |
| GP64SubClassMask, |
| SuperRegIdxSeqs + 1, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| GP64Superclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass GPR64_with_sub_32_in_CPURARegRegClass = { |
| &MipsMCRegisterClasses[GPR64_with_sub_32_in_CPURARegRegClassID], |
| GPR64_with_sub_32_in_CPURARegSubClassMask, |
| SuperRegIdxSeqs + 1, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| GPR64_with_sub_32_in_CPURARegSuperclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32ZERORegClass = { |
| &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPR32ZERORegClassID], |
| GPR64_with_sub_32_in_GPR32ZEROSubClassMask, |
| SuperRegIdxSeqs + 1, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| GPR64_with_sub_32_in_GPR32ZEROSuperclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass HI64RegClass = { |
| &MipsMCRegisterClasses[HI64RegClassID], |
| HI64SubClassMask, |
| SuperRegIdxSeqs + 4, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| NullRegClasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass LO64RegClass = { |
| &MipsMCRegisterClasses[LO64RegClassID], |
| LO64SubClassMask, |
| SuperRegIdxSeqs + 7, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| NullRegClasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass SP64RegClass = { |
| &MipsMCRegisterClasses[SP64RegClassID], |
| SP64SubClassMask, |
| SuperRegIdxSeqs + 1, |
| LaneBitmask(0x00000001), |
| 0, |
| false, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| SP64Superclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass MSA128BRegClass = { |
| &MipsMCRegisterClasses[MSA128BRegClassID], |
| MSA128BSubClassMask, |
| SuperRegIdxSeqs + 1, |
| LaneBitmask(0x00000041), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| MSA128BSuperclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass MSA128DRegClass = { |
| &MipsMCRegisterClasses[MSA128DRegClassID], |
| MSA128DSubClassMask, |
| SuperRegIdxSeqs + 1, |
| LaneBitmask(0x00000041), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| MSA128DSuperclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass MSA128HRegClass = { |
| &MipsMCRegisterClasses[MSA128HRegClassID], |
| MSA128HSubClassMask, |
| SuperRegIdxSeqs + 1, |
| LaneBitmask(0x00000041), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| MSA128HSuperclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass MSA128WRegClass = { |
| &MipsMCRegisterClasses[MSA128WRegClassID], |
| MSA128WSubClassMask, |
| SuperRegIdxSeqs + 1, |
| LaneBitmask(0x00000041), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| MSA128WSuperclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass MSA128B_with_sub_64_in_OddSPRegClass = { |
| &MipsMCRegisterClasses[MSA128B_with_sub_64_in_OddSPRegClassID], |
| MSA128B_with_sub_64_in_OddSPSubClassMask, |
| SuperRegIdxSeqs + 1, |
| LaneBitmask(0x00000041), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| MSA128B_with_sub_64_in_OddSPSuperclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass MSA128WEvensRegClass = { |
| &MipsMCRegisterClasses[MSA128WEvensRegClassID], |
| MSA128WEvensSubClassMask, |
| SuperRegIdxSeqs + 1, |
| LaneBitmask(0x00000041), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| false, /* CoveredBySubRegs */ |
| MSA128WEvensSuperclasses, |
| nullptr |
| }; |
| |
| extern const TargetRegisterClass ACC128RegClass = { |
| &MipsMCRegisterClasses[ACC128RegClassID], |
| ACC128SubClassMask, |
| SuperRegIdxSeqs + 1, |
| LaneBitmask(0x00000041), |
| 0, |
| true, /* HasDisjunctSubRegs */ |
| true, /* CoveredBySubRegs */ |
| NullRegClasses, |
| nullptr |
| }; |
| |
| } // end namespace Mips |
| |
| namespace { |
| const TargetRegisterClass* const RegisterClasses[] = { |
| &Mips::MSA128F16RegClass, |
| &Mips::MSA128F16_with_sub_64_in_OddSPRegClass, |
| &Mips::OddSPRegClass, |
| &Mips::CCRRegClass, |
| &Mips::COP0RegClass, |
| &Mips::COP2RegClass, |
| &Mips::COP3RegClass, |
| &Mips::DSPRRegClass, |
| &Mips::FGR32RegClass, |
| &Mips::FGRCCRegClass, |
| &Mips::FGRH32RegClass, |
| &Mips::GPR32RegClass, |
| &Mips::HWRegsRegClass, |
| &Mips::GPR32NONZERORegClass, |
| &Mips::OddSP_with_sub_hiRegClass, |
| &Mips::FGR32_and_OddSPRegClass, |
| &Mips::FGRH32_and_OddSPRegClass, |
| &Mips::OddSP_with_sub_hi_with_sub_hi_in_FGRH32RegClass, |
| &Mips::CPU16RegsPlusSPRegClass, |
| &Mips::CPU16RegsRegClass, |
| &Mips::FCCRegClass, |
| &Mips::GPRMM16RegClass, |
| &Mips::GPRMM16MovePRegClass, |
| &Mips::GPRMM16ZeroRegClass, |
| &Mips::MSACtrlRegClass, |
| &Mips::OddSP_with_sub_hi_with_sub_hi_in_FGR32RegClass, |
| &Mips::CPU16Regs_and_GPRMM16ZeroRegClass, |
| &Mips::GPR32NONZERO_and_GPRMM16MovePRegClass, |
| &Mips::CPU16Regs_and_GPRMM16MovePRegClass, |
| &Mips::GPRMM16MoveP_and_GPRMM16ZeroRegClass, |
| &Mips::HI32DSPRegClass, |
| &Mips::LO32DSPRegClass, |
| &Mips::GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass, |
| &Mips::CPURARegRegClass, |
| &Mips::CPUSPRegRegClass, |
| &Mips::DSPCCRegClass, |
| &Mips::GP32RegClass, |
| &Mips::GPR32ZERORegClass, |
| &Mips::HI32RegClass, |
| &Mips::LO32RegClass, |
| &Mips::SP32RegClass, |
| &Mips::FGR64RegClass, |
| &Mips::GPR64RegClass, |
| &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass, |
| &Mips::AFGR64RegClass, |
| &Mips::FGR64_and_OddSPRegClass, |
| &Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass, |
| &Mips::AFGR64_and_OddSPRegClass, |
| &Mips::GPR64_with_sub_32_in_CPU16RegsRegClass, |
| &Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClass, |
| &Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass, |
| &Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClass, |
| &Mips::GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClass, |
| &Mips::ACC64DSPRegClass, |
| &Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClass, |
| &Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClass, |
| &Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass, |
| &Mips::OCTEON_MPLRegClass, |
| &Mips::OCTEON_PRegClass, |
| &Mips::ACC64RegClass, |
| &Mips::GP64RegClass, |
| &Mips::GPR64_with_sub_32_in_CPURARegRegClass, |
| &Mips::GPR64_with_sub_32_in_GPR32ZERORegClass, |
| &Mips::HI64RegClass, |
| &Mips::LO64RegClass, |
| &Mips::SP64RegClass, |
| &Mips::MSA128BRegClass, |
| &Mips::MSA128DRegClass, |
| &Mips::MSA128HRegClass, |
| &Mips::MSA128WRegClass, |
| &Mips::MSA128B_with_sub_64_in_OddSPRegClass, |
| &Mips::MSA128WEvensRegClass, |
| &Mips::ACC128RegClass, |
| }; |
| } // end anonymous namespace |
| |
| static const TargetRegisterInfoDesc MipsRegInfoDesc[] = { // Extra Descriptors |
| { 0, false }, |
| { 0, true }, |
| { 0, true }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, false }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, true }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, false }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, false }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| { 0, true }, |
| }; |
| unsigned MipsGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const { |
| static const uint8_t RowMap[11] = { |
| 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, |
| }; |
| static const uint8_t Rows[2][11] = { |
| { 10, 0, 0, 0, 0, 0, 0, 8, 9, 0, 0, }, |
| { 1, 0, 0, 0, 0, 0, 0, 10, 1, 0, 0, }, |
| }; |
| |
| --IdxA; assert(IdxA < 11); |
| --IdxB; assert(IdxB < 11); |
| return Rows[RowMap[IdxA]][IdxB]; |
| } |
| |
| struct MaskRolOp { |
| LaneBitmask Mask; |
| uint8_t RotateLeft; |
| }; |
| static const MaskRolOp LaneMaskComposeSequences[] = { |
| { LaneBitmask(0xFFFFFFFF), 0 }, { LaneBitmask::getNone(), 0 }, // Sequence 0 |
| { LaneBitmask(0xFFFFFFFF), 1 }, { LaneBitmask::getNone(), 0 }, // Sequence 2 |
| { LaneBitmask(0xFFFFFFFF), 2 }, { LaneBitmask::getNone(), 0 }, // Sequence 4 |
| { LaneBitmask(0xFFFFFFFF), 3 }, { LaneBitmask::getNone(), 0 }, // Sequence 6 |
| { LaneBitmask(0xFFFFFFFF), 4 }, { LaneBitmask::getNone(), 0 }, // Sequence 8 |
| { LaneBitmask(0xFFFFFFFF), 5 }, { LaneBitmask::getNone(), 0 }, // Sequence 10 |
| { LaneBitmask(0xFFFFFFFF), 6 }, { LaneBitmask::getNone(), 0 } // Sequence 12 |
| }; |
| static const MaskRolOp *const CompositeSequences[] = { |
| &LaneMaskComposeSequences[0], // to sub_32 |
| &LaneMaskComposeSequences[0], // to sub_64 |
| &LaneMaskComposeSequences[2], // to sub_dsp16_19 |
| &LaneMaskComposeSequences[4], // to sub_dsp20 |
| &LaneMaskComposeSequences[6], // to sub_dsp21 |
| &LaneMaskComposeSequences[8], // to sub_dsp22 |
| &LaneMaskComposeSequences[10], // to sub_dsp23 |
| &LaneMaskComposeSequences[12], // to sub_hi |
| &LaneMaskComposeSequences[0], // to sub_lo |
| &LaneMaskComposeSequences[12], // to sub_hi_then_sub_32 |
| &LaneMaskComposeSequences[0] // to sub_32_sub_hi_then_sub_32 |
| }; |
| |
| LaneBitmask MipsGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const { |
| --IdxA; assert(IdxA < 11 && "Subregister index out of bounds"); |
| LaneBitmask Result; |
| for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) { |
| LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger(); |
| if (unsigned S = Ops->RotateLeft) |
| Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S))); |
| else |
| Result |= LaneBitmask(M); |
| } |
| return Result; |
| } |
| |
| LaneBitmask MipsGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const { |
| LaneMask &= getSubRegIndexLaneMask(IdxA); |
| --IdxA; assert(IdxA < 11 && "Subregister index out of bounds"); |
| LaneBitmask Result; |
| for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) { |
| LaneBitmask::Type M = LaneMask.getAsInteger(); |
| if (unsigned S = Ops->RotateLeft) |
| Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S))); |
| else |
| Result |= LaneBitmask(M); |
| } |
| return Result; |
| } |
| |
| const TargetRegisterClass *MipsGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const { |
| static const uint8_t Table[73][11] = { |
| { // MSA128F16 |
| 0, // sub_32 |
| 1, // sub_64 -> MSA128F16 |
| 0, // sub_dsp16_19 |
| 0, // sub_dsp20 |
| 0, // sub_dsp21 |
| 0, // sub_dsp22 |
| 0, // sub_dsp23 |
| 1, // sub_hi -> MSA128F16 |
| 1, // sub_lo -> MSA128F16 |
| 0, // sub_hi_then_sub_32 |
| 0, // sub_32_sub_hi_then_sub_32 |
| }, |
| { // MSA128F16_with_sub_64_in_OddSP |
| 0, // sub_32 |
| 2, // sub_64 -> MSA128F16_with_sub_64_in_OddSP |
| 0, // sub_dsp16_19 |
| 0, // sub_dsp20 |
| 0, // sub_dsp21 |
| 0, // sub_dsp22 |
| 0, // sub_dsp23 |
| 2, // sub_hi -> MSA128F16_with_sub_64_in_OddSP |
| 2, // sub_lo -> MSA128F16_with_sub_64_in_OddSP |
| 0, // sub_hi_then_sub_32 |
| 0, // sub_32_sub_hi_then_sub_32 |
| }, |
| { // OddSP |
| 0, // sub_32 |
| 0, // sub_64 |
| 0, // sub_dsp16_19 |
| 0, // sub_dsp20 |
| 0, // sub_dsp21 |
| 0, // sub_dsp22 |
| 0, // sub_dsp23 |
| 15, // sub_hi -> OddSP_with_sub_hi |
| 15, // sub_lo -> OddSP_with_sub_hi |
| 0, // sub_hi_then_sub_32 |
| 0, // sub_32_sub_hi_then_sub_32 |
| }, |
| { // CCR |
| 0, // sub_32 |
| 0, // sub_64 |
| 0, // sub_dsp16_19 |
| 0, // sub_dsp20 |
| 0, // sub_dsp21 |
| 0, // sub_dsp22 |
| 0, // sub_dsp23 |
| 0, // sub_hi |
| 0, // sub_lo |
| 0, // sub_hi_then_sub_32 |
| 0, // sub_32_sub_hi_then_sub_32 |
| }, |
| { // COP0 |
| 0, // sub_32 |
| 0, // sub_64 |
| 0, // sub_dsp16_19 |
| 0, // sub_dsp20 |
| 0, // sub_dsp21 |
| 0, // sub_dsp22 |
| 0, // sub_dsp23 |
| 0, // sub_hi |
| 0, // sub_lo |
| 0, // sub_hi_then_sub_32 |
| 0, // sub_32_sub_hi_then_sub_32 |
| }, |
| { // COP2 |
| 0, // sub_32 |
| 0, // sub_64 |
| 0, // sub_dsp16_19 |
| 0, // sub_dsp20 |
| 0, // sub_dsp21 |
| 0, // sub_dsp22 |
| 0, // sub_dsp23 |
| 0, // sub_hi |
| 0, // sub_lo |
| 0, // sub_hi_then_sub_32 |
| 0, // sub_32_sub_hi_then_sub_32 |
| }, |
| { // COP3 |
| 0, // sub_32 |
| 0, // sub_64 |
| 0, // sub_dsp16_19 |
| 0, // sub_dsp20 |
| 0, // sub_dsp21 |
| 0, // sub_dsp22 |
| 0, // sub_dsp23 |
| 0, // sub_hi |
| 0, // sub_lo |
| 0, // sub_hi_then_sub_32 |
| 0, // sub_32_sub_hi_then_sub_32 |
| }, |
| { // DSPR |
| 0, // sub_32 |
| 0, // sub_64 |
| 0, // sub_dsp16_19 |
| 0, // sub_dsp20 |
| 0, // sub_dsp21 |
| 0, // sub_dsp22 |
| 0, // sub_dsp23 |
| 0, // sub_hi |
| 0, // sub_lo |
| 0, // sub_hi_then_sub_32 |
| 0, // sub_32_sub_hi_then_sub_32 |
| }, |
| { // FGR32 |
| 0, // sub_32 |
| 0, // sub_64 |
| 0, // sub_dsp16_19 |
| 0, // sub_dsp20 |
| 0, // sub_dsp21 |
| 0, // sub_dsp22 |
| 0, // sub_dsp23 |
| 0, // sub_hi |
| 0, // sub_lo |
| 0, // sub_hi_then_sub_32 |
| 0, // sub_32_sub_hi_then_sub_32 |
| }, |
| { // FGRCC |
| 0, // sub_32 |
| 0, // sub_64 |
| 0, // sub_dsp16_19 |
| 0, // sub_dsp20 |
| 0, // sub_dsp21 |
| 0, // sub_dsp22 |
| 0, // sub_dsp23 |
| 0, // sub_hi |
| 0, // sub_lo |
| 0, // sub_hi_then_sub_32 |
| 0, // sub_32_sub_hi_then_sub_32 |
| }, |
| { // FGRH32 |
| 0, // sub_32 |
| 0, // sub_64 |
| 0, // sub_dsp16_19 |
| 0, // sub_dsp20 |
| 0, // sub_dsp21 |
| 0, // sub_dsp22 |
| 0, // sub_dsp23 |
| 0, // sub_hi |
| 0, // sub_lo |
| 0, // sub_hi_then_sub_32 |
| 0, // sub_32_sub_hi_then_sub_32 |
| }, |
| { // GPR32 |
| 0, // sub_32 |
| 0, // sub_64 |
| 0, // sub_dsp16_19 |
| 0, // sub_dsp20 |
| 0, // sub_dsp21 |
| 0, // sub_dsp22 |
| 0, // sub_dsp23 |
| 0, // sub_hi |
| 0, // sub_lo |
| 0, // sub_hi_then_sub_32 |
| 0, // sub_32_sub_hi_then_sub_32 |
| }, |
| { // HWRegs |
| 0, // sub_32 |
| 0, // sub_64 |
| 0, // sub_dsp16_19 |
| 0, // sub_dsp20 |
| 0, // sub_dsp21 |
| 0, // sub_dsp22 |
| 0, // sub_dsp23 |
| 0, // sub_hi |
| 0, // sub_lo |
| 0, // sub_hi_then_sub_32 |
| 0, // sub_32_sub_hi_then_sub_32 |
| }, |
| { // GPR32NONZERO |
| 0, // sub_32 |
| 0, // sub_64 |
| 0, // sub_dsp16_19 |
| 0, // sub_dsp20 |
| 0, // sub_dsp21 |
| 0, // sub_dsp22 |
| 0, // sub_dsp23 |
| 0, // sub_hi |
| 0, // sub_lo |
| 0, // sub_hi_then_sub_32 |
| 0, // sub_32_sub_hi_then_sub_32 |
| }, |
| { // OddSP_with_sub_hi |
| 0, // sub_32 |
| 0, // sub_64 |
| 0, // sub_dsp16_19 |
| 0, // sub_dsp20 |
| 0, // sub_dsp21 |
| 0, // sub_dsp22 |
| 0, // sub_dsp23 |
| 15, // sub_hi -> OddSP_with_sub_hi |
| 15, // sub_lo -> OddSP_with_sub_hi |
| 0, // sub_hi_then_sub_32 |
| 0, // sub_32_sub_hi_then_sub_32 |
| }, |
| { // FGR32_and_OddSP |
| 0, // sub_32 |
| 0, // sub_64 |
| 0, // sub_dsp16_19 |
| 0, // sub_dsp20 |
| 0, // sub_dsp21 |
| 0, // sub_dsp22 |
| 0, // sub_dsp23 |
| 0, // sub_hi |
| 0, // sub_lo |
| 0, // sub_hi_then_sub_32 |
| 0, // sub_32_sub_hi_then_sub_32 |
| }, |
| { // FGRH32_and_OddSP |
| 0, // sub_32 |
| 0, // sub_64 |
| 0, // sub_dsp16_19 |
| 0, // sub_dsp20 |
| 0, // sub_dsp21 |
| 0, // sub_dsp22 |
| 0, // sub_dsp23 |
| 0, // sub_hi |
| 0, // sub_lo |
| 0, // sub_hi_then_sub_32 |
| 0, // sub_32_sub_hi_then_sub_32 |
| }, |
| { // OddSP_with_sub_hi_with_sub_hi_in_FGRH32 |
| 0, // sub_32 |
| 0, // sub_64 |
| 0, // sub_dsp16_19 |
| 0, // sub_dsp20 |
| 0, // sub_dsp21 |
| 0, // sub_dsp22 |
| 0, // sub_dsp23 |
| 18, // sub_hi -> OddSP_with_sub_hi_with_sub_hi_in_FGRH32 |
| 18, // sub_lo -> OddSP_with_sub_hi_with_sub_hi_in_FGRH32 |
| 0, // sub_hi_then_sub_32 |
| 0, // sub_32_sub_hi_then_sub_32 |
| }, |
| { // CPU16RegsPlusSP |
| 0, // sub_32 |
| 0, // sub_64 |
| 0, // sub_dsp16_19 |
| 0, // sub_dsp20 |
| 0, // sub_dsp21 |
| 0, // sub_dsp22 |
| 0, // sub_dsp23 |
| 0, // sub_hi |
| 0, // sub_lo |
| 0, // sub_hi_then_sub_32 |
| 0, // sub_32_sub_hi_then_sub_32 |
| }, |
| { // CPU16Regs |
| 0, // sub_32 |
| 0, // sub_64 |
| 0, // sub_dsp16_19 |
| 0, // sub_dsp20 |
| 0, // sub_dsp21 |
| 0, // sub_dsp22 |
| 0, // sub_dsp23 |
| 0, // sub_hi |
| 0, // sub_lo |
| 0, // sub_hi_then_sub_32 |
| 0, // sub_32_sub_hi_then_sub_32 |
| }, |
| { // FCC |
| 0, // sub_32 |
| 0, // sub_64 |
| 0, // sub_dsp16_19 |
| 0, // sub_dsp20 |
| 0, // sub_dsp21 |
| 0, // sub_dsp22 |
| 0, // sub_dsp23 |
| 0, // sub_hi |
| 0, // sub_lo |
| 0, // sub_hi_then_sub_32 |
| 0, // sub_32_sub_hi_then_sub_32 |
| }, |
| { // GPRMM16 |
| 0, // sub_32 |
| 0, // sub_64 |
| 0, // sub_dsp16_19 |
| 0, // sub_dsp20 |
| 0, // sub_dsp21 |
| 0, // sub_dsp22 |
| 0, // sub_dsp23 |
| 0, // sub_hi |
| 0, // sub_lo |
| 0, // sub_hi_then_sub_32 |
| 0, // sub_32_sub_hi_then_sub_32 |
| }, |
| { // GPRMM16MoveP |
| 0, // sub_32 |
| 0, // sub_64 |
| 0, // sub_dsp16_19 |
| 0, // sub_dsp20 |
| 0, // sub_dsp21 |
| 0, // sub_dsp22 |
| 0, // sub_dsp23 |
| 0, // sub_hi |
| 0, // sub_lo |
| 0, // sub_hi_then_sub_32 |
| 0, // sub_32_sub_hi_then_sub_32 |
| }, |
| { // GPRMM16Zero |
| 0, // sub_32 |
| 0, // sub_64 |
| 0, // sub_dsp16_19 |
| 0, // sub_dsp20 |
| 0, // sub_dsp21 |
| 0, // sub_dsp22 |
| 0, // sub_dsp23 |
| 0, // sub_hi |
| 0, // sub_lo |
| 0, // sub_hi_then_sub_32 |
| 0, // sub_32_sub_hi_then_sub_32 |
| }, |
| { // MSACtrl |
| 0, // sub_32 |
| 0, // sub_64 |
| 0, // sub_dsp16_19 |
| 0, // sub_dsp20 |
| 0, // sub_dsp21 |
| 0, // sub_dsp22 |
| 0, // sub_dsp23 |
| 0, // sub_hi |
| 0, // sub_lo |
| 0, // sub_hi_then_sub_32 |
| 0, // sub_32_sub_hi_then_sub_32 |
| }, |
| { // OddSP_with_sub_hi_with_sub_hi_in_FGR32 |
| 0, // sub_32 |
| 0, // sub_64 |
| 0, // sub_dsp16_19 |
| 0, // sub_dsp20 |
| 0, // sub_dsp21 |
| 0, // sub_dsp22 |
| 0, // sub_dsp23 |
| 26, // sub_hi -> OddSP_with_sub_hi_with_sub_hi_in_FGR32 |
| 26, // sub_lo -> OddSP_with_sub_hi_with_sub_hi_in_FGR32 |
| 0, // sub_hi_then_sub_32 |
| 0, // sub_32_sub_hi_then_sub_32 |
| }, |
| { // CPU16Regs_and_GPRMM16Zero |
| 0, // sub_32 |
| 0, // sub_64 |
| 0, // sub_dsp16_19 |
| 0, // sub_dsp20 |
| 0, // sub_dsp21 |
| 0, // sub_dsp22 |
| 0, // sub_dsp23 |
| 0, // sub_hi |
| 0, // sub_lo |
| 0, // sub_hi_then_sub_32 |
| 0, // sub_32_sub_hi_then_sub_32 |
| }, |
| { // GPR32NONZERO_and_GPRMM16MoveP |
| 0, // sub_32 |
| 0, // sub_64 |
| 0, // sub_dsp16_19 |
| 0, // sub_dsp20 |
| 0, // sub_dsp21 |
| 0, // sub_dsp22 |
| 0, // sub_dsp23 |
| 0, // sub_hi |
| 0, // sub_lo |
| 0, // sub_hi_then_sub_32 |
| 0, // sub_32_sub_hi_then_sub_32 |
| }, |
| { // CPU16Regs_and_GPRMM16MoveP |
| 0, // sub_32 |
| 0, // sub_64 |
| 0, // sub_dsp16_19 |
| 0, // sub_dsp20 |
| 0, // sub_dsp21 |
| 0, // sub_dsp22 |
| 0, // sub_dsp23 |
| 0, // sub_hi |
| 0, // sub_lo |
| 0, // sub_hi_then_sub_32 |
| 0, // sub_32_sub_hi_then_sub_32 |
| }, |
| { // GPRMM16MoveP_and_GPRMM16Zero |
| 0, // sub_32 |
| 0, // sub_64 |
| 0, // sub_dsp16_19 |
| 0, // sub_dsp20 |
| 0, // sub_dsp21 |
| 0, // sub_dsp22 |
| 0, // sub_dsp23 |
| 0, // sub_hi |
| 0, // sub_lo |
| 0, // sub_hi_then_sub_32 |
| 0, // sub_32_sub_hi_then_sub_32 |
| }, |
| { // HI32DSP |
| 0, // sub_32 |
| 0, // sub_64 |
| 0, // sub_dsp16_19 |
| 0, // sub_dsp20 |
| 0, // sub_dsp21 |
| 0, // sub_dsp22 |
| 0, // sub_dsp23 |
| 0, // sub_hi |
| 0, // sub_lo |
| 0, // sub_hi_then_sub_32 |
| 0, // sub_32_sub_hi_then_sub_32 |
| }, |
| { // LO32DSP |
| 0, // sub_32 |
| 0, // sub_64 |
| 0, // sub_dsp16_19 |
| 0, // sub_dsp20 |
| 0, // sub_dsp21 |
| 0, // sub_dsp22 |
| 0, // sub_dsp23 |
| 0, // sub_hi |
| 0, // sub_lo |
| 0, // sub_hi_then_sub_32 |
| 0, // sub_32_sub_hi_then_sub_32 |
| }, |
| { // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero |
| 0, // sub_32 |
| 0, // sub_64 |
| 0, // sub_dsp16_19 |
| 0, // sub_dsp20 |
| 0, // sub_dsp21 |
| 0, // sub_dsp22 |
| 0, // sub_dsp23 |
| 0, // sub_hi |
| 0, // sub_lo |
| 0, // sub_hi_then_sub_32 |
| 0, // sub_32_sub_hi_then_sub_32 |
| }, |
| { // CPURAReg |
| 0, // sub_32 |
| 0, // sub_64 |
| 0, // sub_dsp16_19 |
| 0, // sub_dsp20 |
| 0, // sub_dsp21 |
| 0, // sub_dsp22 |
| 0, // sub_dsp23 |
| 0, // sub_hi |
| 0, // sub_lo |
| 0, // sub_hi_then_sub_32 |
| 0, // sub_32_sub_hi_then_sub_32 |
| }, |
| { // CPUSPReg |
| 0, // sub_32 |
| 0, // sub_64 |
| 0, // sub_dsp16_19 |
| 0, // sub_dsp20 |
| 0, // sub_dsp21 |
| 0, // sub_dsp22 |
| 0, // sub_dsp23 |
| 0, // sub_hi |
| 0, // sub_lo |
| 0, // sub_hi_then_sub_32 |
| 0, // sub_32_sub_hi_then_sub_32 |
| }, |
| { // DSPCC |
| 0, // sub_32 |
| 0, // sub_64 |
| 0, // sub_dsp16_19 |
| 0, // sub_dsp20 |
| 0, // sub_dsp21 |
| 0, // sub_dsp22 |
| 0, // sub_dsp23 |
| 0, // sub_hi |
| 0, // sub_lo |
| 0, // sub_hi_then_sub_32 |
| 0, // sub_32_sub_hi_then_sub_32 |
| }, |
| { // GP32 |
| 0, // sub_32 |
| 0, // sub_64 |
| 0, // sub_dsp16_19 |
| 0, // sub_dsp20 |
| 0, // sub_dsp21 |
| 0, // sub_dsp22 |
| 0, // sub_dsp23 |
| 0, // sub_hi |
| 0, // sub_lo |
| 0, // sub_hi_then_sub_32 |
| 0, // sub_32_sub_hi_then_sub_32 |
| }, |
| { // GPR32ZERO |
| 0, // sub_32 |
| 0, // sub_64 |
| 0, // sub_dsp16_19 |
| 0, // sub_dsp20 |
| 0, // sub_dsp21 |
| 0, // sub_dsp22 |
| 0, // sub_dsp23 |
| 0, // sub_hi |
| 0, // sub_lo |
| 0, // sub_hi_then_sub_32 |
| 0, // sub_32_sub_hi_then_sub_32 |
| }, |
| { // HI32 |
| 0, // sub_32 |
| 0, // sub_64 |
| 0, // sub_dsp16_19 |
| 0, // sub_dsp20 |
| 0, // sub_dsp21 |
| 0, // sub_dsp22 |
| 0, // sub_dsp23 |
| 0, // sub_hi |
| 0, // sub_lo |
| 0, // sub_hi_then_sub_32 |
| 0, // sub_32_sub_hi_then_sub_32 |
| }, |
| { // LO32 |
| 0, // sub_32 |
| 0, // sub_64 |
| 0, // sub_dsp16_19 |
| 0, // sub_dsp20 |
| 0, // sub_dsp21 |
| 0, // sub_dsp22 |
| 0, // sub_dsp23 |
| 0, // sub_hi |
| 0, // sub_lo |
| 0, // sub_hi_then_sub_32 |
| 0, // sub_32_sub_hi_then_sub_32 |
| }, |
| { // SP32 |
| 0, // sub_32 |
| 0, // sub_64 |
| 0, // sub_dsp16_19 |
| 0, // sub_dsp20 |
| 0, // sub_dsp21 |
| 0, // sub_dsp22 |
| 0, // sub_dsp23 |
| 0, // sub_hi |
| 0, // sub_lo |
| 0, // sub_hi_then_sub_32 |
| 0, // sub_32_sub_hi_then_sub_32 |
| }, |
| { // FGR64 |
| 0, // sub_32 |
| 0, // sub_64 |
| 0, // sub_dsp16_19 |
| 0, // sub_dsp20 |
| 0, // sub_dsp21 |
| 0, // sub_dsp22 |
| 0, // sub_dsp23 |
| 42, // sub_hi -> FGR64 |
| 42, // sub_lo -> FGR64 |
| 0, // sub_hi_then_sub_32 |
| 0, // sub_32_sub_hi_then_sub_32 |
| }, |
| { // GPR64 |
| 43, // sub_32 -> GPR64 |
| 0, // sub_64 |
| 0, // sub_dsp16_19 |
| 0, // sub_dsp20 |
| 0, // sub_dsp21 |
| 0, // sub_dsp22 |
| 0, // sub_dsp23 |
| 0, // sub_hi |
| 0, // sub_lo |
| 0, // sub_hi_then_sub_32 |
| 0, // sub_32_sub_hi_then_sub_32 |
| }, |
| { // GPR64_with_sub_32_in_GPR32NONZERO |
| 44, // sub_32 -> GPR64_with_sub_32_in_GPR32NONZERO |
| 0, // sub_64 |
| 0, // sub_dsp16_19 |
| 0, // sub_dsp20 |
| 0, // sub_dsp21 |
| 0, // sub_dsp22 |
| 0, // sub_dsp23 |
| 0, // sub_hi |
| 0, // sub_lo |
| 0, // sub_hi_then_sub_32 |
| 0, // sub_32_sub_hi_then_sub_32 |
| }, |
| { // AFGR64 |
| 0, // sub_32 |
| 0, // sub_64 |
| 0, // sub_dsp16_19 |
| 0, // sub_dsp20 |
| 0, // sub_dsp21 |
| 0, // sub_dsp22 |
| 0, // sub_dsp23 |
| 45, // sub_hi -> AFGR64 |
| 45, // sub_lo -> AFGR64 |
| 0, // sub_hi_then_sub_32 |
| 0, // sub_32_sub_hi_then_sub_32 |
| }, |
| { // FGR64_and_OddSP |
| 0, // sub_32 |
| 0, // sub_64 |
| 0, // sub_dsp16_19 |
| 0, // sub_dsp20 |
| 0, // sub_dsp21 |
| 0, // sub_dsp22 |
| 0, // sub_dsp23 |
| 46, // sub_hi -> FGR64_and_OddSP |
| 46, // sub_lo -> FGR64_and_OddSP |
| 0, // sub_hi_then_sub_32 |
| 0, // sub_32_sub_hi_then_sub_32 |
| }, |
| { // GPR64_with_sub_32_in_CPU16RegsPlusSP |
| 47, // sub_32 -> GPR64_with_sub_32_in_CPU16RegsPlusSP |
| 0, // sub_64 |
| 0, // sub_dsp16_19 |
| 0, // sub_dsp20 |
| 0, // sub_dsp21 |
| 0, // sub_dsp22 |
| 0, // sub_dsp23 |
| 0, // sub_hi |
| 0, // sub_lo |
| 0, // sub_hi_then_sub_32 |
| 0, // sub_32_sub_hi_then_sub_32 |
| }, |
| { // AFGR64_and_OddSP |
| 0, // sub_32 |
| 0, // sub_64 |
| 0, // sub_dsp16_19 |
| 0, // sub_dsp20 |
| 0, // sub_dsp21 |
| 0, // sub_dsp22 |
| 0, // sub_dsp23 |
| 48, // sub_hi -> AFGR64_and_OddSP |
| 48, // sub_lo -> AFGR64_and_OddSP |
| 0, // sub_hi_then_sub_32 |
| 0, // sub_32_sub_hi_then_sub_32 |
| }, |
| { // GPR64_with_sub_32_in_CPU16Regs |
| 49, // sub_32 -> GPR64_with_sub_32_in_CPU16Regs |
| 0, // sub_64 |
| 0, // sub_dsp16_19 |
| 0, // sub_dsp20 |
| 0, // sub_dsp21 |
| 0, // sub_dsp22 |
| 0, // sub_dsp23 |
| 0, // sub_hi |
| 0, // sub_lo |
| 0, // sub_hi_then_sub_32 |
| 0, // sub_32_sub_hi_then_sub_32 |
| }, |
| { // GPR64_with_sub_32_in_GPRMM16MoveP |
| 50, // sub_32 -> GPR64_with_sub_32_in_GPRMM16MoveP |
| 0, // sub_64 |
| 0, // sub_dsp16_19 |
| 0, // sub_dsp20 |
| 0, // sub_dsp21 |
| 0, // sub_dsp22 |
| 0, // sub_dsp23 |
| 0, // sub_hi |
| 0, // sub_lo |
| 0, // sub_hi_then_sub_32 |
| 0, // sub_32_sub_hi_then_sub_32 |
| }, |
| { // GPR64_with_sub_32_in_GPRMM16Zero |
| 51, // sub_32 -> GPR64_with_sub_32_in_GPRMM16Zero |
| 0, // sub_64 |
| 0, // sub_dsp16_19 |
| 0, // sub_dsp20 |
| 0, // sub_dsp21 |
| 0, // sub_dsp22 |
| 0, // sub_dsp23 |
| 0, // sub_hi |
| 0, // sub_lo |
| 0, // sub_hi_then_sub_32 |
| 0, // sub_32_sub_hi_then_sub_32 |
| }, |
| { // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero |
| 52, // sub_32 -> GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero |
| 0, // sub_64 |
| 0, // sub_dsp16_19 |
| 0, // sub_dsp20 |
| 0, // sub_dsp21 |
| 0, // sub_dsp22 |
| 0, // sub_dsp23 |
| 0, // sub_hi |
| 0, // sub_lo |
| 0, // sub_hi_then_sub_32 |
| 0, // sub_32_sub_hi_then_sub_32 |
| }, |
| { // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP |
| 53, // sub_32 -> GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP |
| 0, // sub_64 |
| 0, // sub_dsp16_19 |
| 0, // sub_dsp20 |
| 0, // sub_dsp21 |
| 0, // sub_dsp22 |
| 0, // sub_dsp23 |
| 0, // sub_hi |
| 0, // sub_lo |
| 0, // sub_hi_then_sub_32 |
| 0, // sub_32_sub_hi_then_sub_32 |
| }, |
| { // ACC64DSP |
| 0, // sub_32 |
| 0, // sub_64 |
| 0, // sub_dsp16_19 |
| 0, // sub_dsp20 |
| 0, // sub_dsp21 |
| 0, // sub_dsp22 |
| 0, // sub_dsp23 |
| 54, // sub_hi -> ACC64DSP |
| 54, // sub_lo -> ACC64DSP |
| 0, // sub_hi_then_sub_32 |
| 0, // sub_32_sub_hi_then_sub_32 |
| }, |
| { // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP |
| 55, // sub_32 -> GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP |
| 0, // sub_64 |
| 0, // sub_dsp16_19 |
| 0, // sub_dsp20 |
| 0, // sub_dsp21 |
| 0, // sub_dsp22 |
| 0, // sub_dsp23 |
| 0, // sub_hi |
| 0, // sub_lo |
| 0, // sub_hi_then_sub_32 |
| 0, // sub_32_sub_hi_then_sub_32 |
| }, |
| { // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero |
| 56, // sub_32 -> GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero |
| 0, // sub_64 |
| 0, // sub_dsp16_19 |
| 0, // sub_dsp20 |
| 0, // sub_dsp21 |
| 0, // sub_dsp22 |
| 0, // sub_dsp23 |
| 0, // sub_hi |
| 0, // sub_lo |
| 0, // sub_hi_then_sub_32 |
| 0, // sub_32_sub_hi_then_sub_32 |
| }, |
| { // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero |
| 57, // sub_32 -> GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero |
| 0, // sub_64 |
| 0, // sub_dsp16_19 |
| 0, // sub_dsp20 |
| 0, // sub_dsp21 |
| 0, // sub_dsp22 |
| 0, // sub_dsp23 |
| 0, // sub_hi |
| 0, // sub_lo |
| 0, // sub_hi_then_sub_32 |
| 0, // sub_32_sub_hi_then_sub_32 |
| }, |
| { // OCTEON_MPL |
| 0, // sub_32 |
| 0, // sub_64 |
| 0, // sub_dsp16_19 |
| 0, // sub_dsp20 |
| 0, // sub_dsp21 |
| 0, // sub_dsp22 |
| 0, // sub_dsp23 |
| 0, // sub_hi |
| 0, // sub_lo |
| 0, // sub_hi_then_sub_32 |
| 0, // sub_32_sub_hi_then_sub_32 |
| }, |
| { // OCTEON_P |
| 0, // sub_32 |
| 0, // sub_64 |
| 0, // sub_dsp16_19 |
| 0, // sub_dsp20 |
| 0, // sub_dsp21 |
| 0, // sub_dsp22 |
| 0, // sub_dsp23 |
| 0, // sub_hi |
| 0, // sub_lo |
| 0, // sub_hi_then_sub_32 |
| 0, // sub_32_sub_hi_then_sub_32 |
| }, |
| { // ACC64 |
| 0, // sub_32 |
| 0, // sub_64 |
| 0, // sub_dsp16_19 |
| 0, // sub_dsp20 |
| 0, // sub_dsp21 |
| 0, // sub_dsp22 |
| 0, // sub_dsp23 |
| 60, // sub_hi -> ACC64 |
| 60, // sub_lo -> ACC64 |
| 0, // sub_hi_then_sub_32 |
| 0, // sub_32_sub_hi_then_sub_32 |
| }, |
| { // GP64 |
| 61, // sub_32 -> GP64 |
| 0, // sub_64 |
| 0, // sub_dsp16_19 |
| 0, // sub_dsp20 |
| 0, // sub_dsp21 |
| 0, // sub_dsp22 |
| 0, // sub_dsp23 |
| 0, // sub_hi |
| 0, // sub_lo |
| 0, // sub_hi_then_sub_32 |
| 0, // sub_32_sub_hi_then_sub_32 |
| }, |
| { // GPR64_with_sub_32_in_CPURAReg |
| 62, // sub_32 -> GPR64_with_sub_32_in_CPURAReg |
| 0, // sub_64 |
| 0, // sub_dsp16_19 |
| 0, // sub_dsp20 |
| 0, // sub_dsp21 |
| 0, // sub_dsp22 |
| 0, // sub_dsp23 |
| 0, // sub_hi |
| 0, // sub_lo |
| 0, // sub_hi_then_sub_32 |
| 0, // sub_32_sub_hi_then_sub_32 |
| }, |
| { // GPR64_with_sub_32_in_GPR32ZERO |
| 63, // sub_32 -> GPR64_with_sub_32_in_GPR32ZERO |
| 0, // sub_64 |
| 0, // sub_dsp16_19 |
| 0, // sub_dsp20 |
| 0, // sub_dsp21 |
| 0, // sub_dsp22 |
| 0, // sub_dsp23 |
| 0, // sub_hi |
| 0, // sub_lo |
| 0, // sub_hi_then_sub_32 |
| 0, // sub_32_sub_hi_then_sub_32 |
| }, |
| { // HI64 |
| 64, // sub_32 -> HI64 |
| 0, // sub_64 |
| 0, // sub_dsp16_19 |
| 0, // sub_dsp20 |
| 0, // sub_dsp21 |
| 0, // sub_dsp22 |
| 0, // sub_dsp23 |
| 0, // sub_hi |
| 0, // sub_lo |
| 0, // sub_hi_then_sub_32 |
| 0, // sub_32_sub_hi_then_sub_32 |
| }, |
| { // LO64 |
| 65, // sub_32 -> LO64 |
| 0, // sub_64 |
| 0, // sub_dsp16_19 |
| 0, // sub_dsp20 |
| 0, // sub_dsp21 |
| 0, // sub_dsp22 |
| 0, // sub_dsp23 |
| 0, // sub_hi |
| 0, // sub_lo |
| 0, // sub_hi_then_sub_32 |
| 0, // sub_32_sub_hi_then_sub_32 |
| }, |
| { // SP64 |
| 66, // sub_32 -> SP64 |
| 0, // sub_64 |
| 0, // sub_dsp16_19 |
| 0, // sub_dsp20 |
| 0, // sub_dsp21 |
| 0, // sub_dsp22 |
| 0, // sub_dsp23 |
| 0, // sub_hi |
| 0, // sub_lo |
| 0, // sub_hi_then_sub_32 |
| 0, // sub_32_sub_hi_then_sub_32 |
| }, |
| { // MSA128B |
| 0, // sub_32 |
| 67, // sub_64 -> MSA128B |
| 0, // sub_dsp16_19 |
| 0, // sub_dsp20 |
| 0, // sub_dsp21 |
| 0, // sub_dsp22 |
| 0, // sub_dsp23 |
| 67, // sub_hi -> MSA128B |
| 67, // sub_lo -> MSA128B |
| 0, // sub_hi_then_sub_32 |
| 0, // sub_32_sub_hi_then_sub_32 |
| }, |
| { // MSA128D |
| 0, // sub_32 |
| 68, // sub_64 -> MSA128D |
| 0, // sub_dsp16_19 |
| 0, // sub_dsp20 |
| 0, // sub_dsp21 |
| 0, // sub_dsp22 |
| 0, // sub_dsp23 |
| 68, // sub_hi -> MSA128D |
| 68, // sub_lo -> MSA128D |
| 0, // sub_hi_then_sub_32 |
| 0, // sub_32_sub_hi_then_sub_32 |
| }, |
| { // MSA128H |
| 0, // sub_32 |
| 69, // sub_64 -> MSA128H |
| 0, // sub_dsp16_19 |
| 0, // sub_dsp20 |
| 0, // sub_dsp21 |
| 0, // sub_dsp22 |
| 0, // sub_dsp23 |
| 69, // sub_hi -> MSA128H |
| 69, // sub_lo -> MSA128H |
| 0, // sub_hi_then_sub_32 |
| 0, // sub_32_sub_hi_then_sub_32 |
| }, |
| { // MSA128W |
| 0, // sub_32 |
| 70, // sub_64 -> MSA128W |
| 0, // sub_dsp16_19 |
| 0, // sub_dsp20 |
| 0, // sub_dsp21 |
| 0, // sub_dsp22 |
| 0, // sub_dsp23 |
| 70, // sub_hi -> MSA128W |
| 70, // sub_lo -> MSA128W |
| 0, // sub_hi_then_sub_32 |
| 0, // sub_32_sub_hi_then_sub_32 |
| }, |
| { // MSA128B_with_sub_64_in_OddSP |
| 0, // sub_32 |
| 71, // sub_64 -> MSA128B_with_sub_64_in_OddSP |
| 0, // sub_dsp16_19 |
| 0, // sub_dsp20 |
| 0, // sub_dsp21 |
| 0, // sub_dsp22 |
| 0, // sub_dsp23 |
| 71, // sub_hi -> MSA128B_with_sub_64_in_OddSP |
| 71, // sub_lo -> MSA128B_with_sub_64_in_OddSP |
| 0, // sub_hi_then_sub_32 |
| 0, // sub_32_sub_hi_then_sub_32 |
| }, |
| { // MSA128WEvens |
| 0, // sub_32 |
| 72, // sub_64 -> MSA128WEvens |
| 0, // sub_dsp16_19 |
| 0, // sub_dsp20 |
| 0, // sub_dsp21 |
| 0, // sub_dsp22 |
| 0, // sub_dsp23 |
| 72, // sub_hi -> MSA128WEvens |
| 72, // sub_lo -> MSA128WEvens |
| 0, // sub_hi_then_sub_32 |
| 0, // sub_32_sub_hi_then_sub_32 |
| }, |
| { // ACC128 |
| 73, // sub_32 -> ACC128 |
| 0, // sub_64 |
| 0, // sub_dsp16_19 |
| 0, // sub_dsp20 |
| 0, // sub_dsp21 |
| 0, // sub_dsp22 |
| 0, // sub_dsp23 |
| 73, // sub_hi -> ACC128 |
| 73, // sub_lo -> ACC128 |
| 73, // sub_hi_then_sub_32 -> ACC128 |
| 73, // sub_32_sub_hi_then_sub_32 -> ACC128 |
| }, |
| }; |
| assert(RC && "Missing regclass"); |
| if (!Idx) return RC; |
| --Idx; |
| assert(Idx < 11 && "Bad subreg"); |
| unsigned TV = Table[RC->getID()][Idx]; |
| return TV ? getRegClass(TV - 1) : nullptr; |
| } |
| |
| /// Get the weight in units of pressure for this register class. |
| const RegClassWeight &MipsGenRegisterInfo:: |
| getRegClassWeight(const TargetRegisterClass *RC) const { |
| static const RegClassWeight RCWeightTable[] = { |
| {2, 64}, // MSA128F16 |
| {2, 32}, // MSA128F16_with_sub_64_in_OddSP |
| {2, 40}, // OddSP |
| {0, 0}, // CCR |
| {0, 0}, // COP0 |
| {0, 0}, // COP2 |
| {0, 0}, // COP3 |
| {1, 32}, // DSPR |
| {1, 32}, // FGR32 |
| {1, 32}, // FGRCC |
| {1, 32}, // FGRH32 |
| {1, 32}, // GPR32 |
| {0, 0}, // HWRegs |
| {1, 31}, // GPR32NONZERO |
| {2, 40}, // OddSP_with_sub_hi |
| {1, 16}, // FGR32_and_OddSP |
| {1, 16}, // FGRH32_and_OddSP |
| {2, 32}, // OddSP_with_sub_hi_with_sub_hi_in_FGRH32 |
| {1, 9}, // CPU16RegsPlusSP |
| {1, 8}, // CPU16Regs |
| {0, 0}, // FCC |
| {1, 8}, // GPRMM16 |
| {1, 8}, // GPRMM16MoveP |
| {1, 8}, // GPRMM16Zero |
| {1, 8}, // MSACtrl |
| {2, 16}, // OddSP_with_sub_hi_with_sub_hi_in_FGR32 |
| {1, 7}, // CPU16Regs_and_GPRMM16Zero |
| {1, 7}, // GPR32NONZERO_and_GPRMM16MoveP |
| {1, 4}, // CPU16Regs_and_GPRMM16MoveP |
| {1, 4}, // GPRMM16MoveP_and_GPRMM16Zero |
| {1, 4}, // HI32DSP |
| {1, 4}, // LO32DSP |
| {1, 3}, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero |
| {1, 1}, // CPURAReg |
| {1, 1}, // CPUSPReg |
| {1, 1}, // DSPCC |
| {1, 1}, // GP32 |
| {1, 1}, // GPR32ZERO |
| {1, 1}, // HI32 |
| {1, 1}, // LO32 |
| {1, 1}, // SP32 |
| {2, 64}, // FGR64 |
| {1, 32}, // GPR64 |
| {1, 31}, // GPR64_with_sub_32_in_GPR32NONZERO |
| {2, 32}, // AFGR64 |
| {2, 32}, // FGR64_and_OddSP |
| {1, 9}, // GPR64_with_sub_32_in_CPU16RegsPlusSP |
| {2, 16}, // AFGR64_and_OddSP |
| {1, 8}, // GPR64_with_sub_32_in_CPU16Regs |
| {1, 8}, // GPR64_with_sub_32_in_GPRMM16MoveP |
| {1, 8}, // GPR64_with_sub_32_in_GPRMM16Zero |
| {1, 7}, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero |
| {1, 7}, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP |
| {2, 8}, // ACC64DSP |
| {1, 4}, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP |
| {1, 4}, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero |
| {1, 3}, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero |
| {0, 0}, // OCTEON_MPL |
| {0, 0}, // OCTEON_P |
| {2, 2}, // ACC64 |
| {1, 1}, // GP64 |
| {1, 1}, // GPR64_with_sub_32_in_CPURAReg |
| {1, 1}, // GPR64_with_sub_32_in_GPR32ZERO |
| {1, 1}, // HI64 |
| {1, 1}, // LO64 |
| {1, 1}, // SP64 |
| {2, 64}, // MSA128B |
| {2, 64}, // MSA128D |
| {2, 64}, // MSA128H |
| {2, 64}, // MSA128W |
| {2, 32}, // MSA128B_with_sub_64_in_OddSP |
| {2, 32}, // MSA128WEvens |
| {2, 2}, // ACC128 |
| }; |
| return RCWeightTable[RC->getID()]; |
| } |
| |
| /// Get the weight in units of pressure for this register unit. |
| unsigned MipsGenRegisterInfo:: |
| getRegUnitWeight(unsigned RegUnit) const { |
| assert(RegUnit < 297 && "invalid register unit"); |
| // All register units have unit weight. |
| return 1; |
| } |
| |
| |
| // Get the number of dimensions of register pressure. |
| unsigned MipsGenRegisterInfo::getNumRegPressureSets() const { |
| return 24; |
| } |
| |
| // Get the name of this register unit pressure set. |
| const char *MipsGenRegisterInfo:: |
| getRegPressureSetName(unsigned Idx) const { |
| static const char *const PressureNameTable[] = { |
| "DSPCC", |
| "GPR32ZERO", |
| "GPR64_with_sub_32_in_CPURAReg", |
| "HI32", |
| "CPU16Regs_and_GPRMM16MoveP", |
| "HI32DSP", |
| "LO32DSP", |
| "GPRMM16MoveP", |
| "MSACtrl", |
| "ACC64DSP", |
| "CPU16Regs", |
| "CPU16Regs+GPRMM16MoveP", |
| "FGR32_and_OddSP", |
| "AFGR64_and_OddSP", |
| "FGR32_and_OddSP+AFGR64_and_OddSP", |
| "MSA128F16_with_sub_64_in_OddSP", |
| "DSPR", |
| "FGR32", |
| "MSA128WEvens", |
| "MSA128F16_with_sub_64_in_OddSP+AFGR64_and_OddSP", |
| "AFGR64_and_OddSP+MSA128WEvens", |
| "MSA128F16_with_sub_64_in_OddSP+FGR32", |
| "FGR32+MSA128WEvens", |
| "MSA128F16", |
| }; |
| return PressureNameTable[Idx]; |
| } |
| |
| // Get the register unit pressure limit for this dimension. |
| // This limit must be adjusted dynamically for reserved registers. |
| unsigned MipsGenRegisterInfo:: |
| getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const { |
| static const uint8_t PressureLimitTable[] = { |
| 1, // 0: DSPCC |
| 1, // 1: GPR32ZERO |
| 1, // 2: GPR64_with_sub_32_in_CPURAReg |
| 2, // 3: HI32 |
| 5, // 4: CPU16Regs_and_GPRMM16MoveP |
| 5, // 5: HI32DSP |
| 5, // 6: LO32DSP |
| 8, // 7: GPRMM16MoveP |
| 8, // 8: MSACtrl |
| 8, // 9: ACC64DSP |
| 10, // 10: CPU16Regs |
| 13, // 11: CPU16Regs+GPRMM16MoveP |
| 16, // 12: FGR32_and_OddSP |
| 16, // 13: AFGR64_and_OddSP |
| 24, // 14: FGR32_and_OddSP+AFGR64_and_OddSP |
| 32, // 15: MSA128F16_with_sub_64_in_OddSP |
| 32, // 16: DSPR |
| 32, // 17: FGR32 |
| 32, // 18: MSA128WEvens |
| 40, // 19: MSA128F16_with_sub_64_in_OddSP+AFGR64_and_OddSP |
| 40, // 20: AFGR64_and_OddSP+MSA128WEvens |
| 48, // 21: MSA128F16_with_sub_64_in_OddSP+FGR32 |
| 48, // 22: FGR32+MSA128WEvens |
| 64, // 23: MSA128F16 |
| }; |
| return PressureLimitTable[Idx]; |
| } |
| |
| /// Table of pressure sets per register class or unit. |
| static const int RCSetsTable[] = { |
| /* 0 */ 0, -1, |
| /* 2 */ 8, -1, |
| /* 4 */ 5, 9, -1, |
| /* 7 */ 3, 5, 6, 9, -1, |
| /* 12 */ 2, 16, -1, |
| /* 15 */ 7, 11, 16, -1, |
| /* 19 */ 1, 4, 7, 10, 11, 16, -1, |
| /* 26 */ 15, 19, 21, 23, -1, |
| /* 31 */ 18, 20, 22, 23, -1, |
| /* 36 */ 17, 21, 22, 23, -1, |
| /* 41 */ 12, 14, 15, 17, 19, 21, 22, 23, -1, |
| /* 50 */ 17, 18, 20, 21, 22, 23, -1, |
| /* 57 */ 13, 14, 17, 19, 20, 21, 22, 23, -1, |
| /* 66 */ 12, 13, 14, 15, 17, 19, 20, 21, 22, 23, -1, |
| /* 77 */ 13, 14, 17, 18, 19, 20, 21, 22, 23, -1, |
| }; |
| |
| /// Get the dimensions of register pressure impacted by this register class. |
| /// Returns a -1 terminated array of pressure set IDs |
| const int* MipsGenRegisterInfo:: |
| getRegClassPressureSets(const TargetRegisterClass *RC) const { |
| static const uint8_t RCSetStartTable[] = { |
| 29,26,1,1,1,1,1,13,36,36,1,13,1,13,1,41,1,1,22,22,1,22,15,22,2,1,22,15,20,20,4,9,20,1,1,0,1,19,7,7,1,29,13,13,36,26,22,57,22,15,22,22,15,5,20,20,20,1,1,7,1,12,19,7,7,1,29,29,29,29,26,31,7,}; |
| return &RCSetsTable[RCSetStartTable[RC->getID()]]; |
| } |
| |
| /// Get the dimensions of register pressure impacted by this register unit. |
| /// Returns a -1 terminated array of pressure set IDs |
| const int* MipsGenRegisterInfo:: |
| getRegUnitPressureSets(unsigned RegUnit) const { |
| assert(RegUnit < 297 && "invalid register unit"); |
| static const uint8_t RUSetStartTable[] = { |
| 13,0,1,1,1,1,1,1,1,1,1,13,13,2,2,2,2,2,2,2,2,1,12,22,19,22,22,22,22,7,7,9,4,9,4,9,4,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,50,41,77,66,50,41,77,66,50,41,77,66,50,41,77,66,50,41,77,66,50,41,77,66,50,41,77,66,50,41,77,66,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,31,26,31,26,31,26,31,26,31,26,31,26,31,26,31,26,31,26,31,26,31,26,31,26,31,26,31,26,31,26,31,26,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,13,13,1,1,1,1,1,1,20,20,15,15,15,13,13,13,13,13,13,13,13,13,13,13,13,13,20,20,}; |
| return &RCSetsTable[RUSetStartTable[RegUnit]]; |
| } |
| |
| extern const MCRegisterDesc MipsRegDesc[]; |
| extern const MCPhysReg MipsRegDiffLists[]; |
| extern const LaneBitmask MipsLaneMaskLists[]; |
| extern const char MipsRegStrings[]; |
| extern const char MipsRegClassStrings[]; |
| extern const MCPhysReg MipsRegUnitRoots[][2]; |
| extern const uint16_t MipsSubRegIdxLists[]; |
| extern const MCRegisterInfo::SubRegCoveredBits MipsSubRegIdxRanges[]; |
| extern const uint16_t MipsRegEncodingTable[]; |
| // Mips Dwarf<->LLVM register mappings. |
| extern const MCRegisterInfo::DwarfLLVMRegPair MipsDwarfFlavour0Dwarf2L[]; |
| extern const unsigned MipsDwarfFlavour0Dwarf2LSize; |
| |
| extern const MCRegisterInfo::DwarfLLVMRegPair MipsEHFlavour0Dwarf2L[]; |
| extern const unsigned MipsEHFlavour0Dwarf2LSize; |
| |
| extern const MCRegisterInfo::DwarfLLVMRegPair MipsDwarfFlavour0L2Dwarf[]; |
| extern const unsigned MipsDwarfFlavour0L2DwarfSize; |
| |
| extern const MCRegisterInfo::DwarfLLVMRegPair MipsEHFlavour0L2Dwarf[]; |
| extern const unsigned MipsEHFlavour0L2DwarfSize; |
| |
| MipsGenRegisterInfo:: |
| MipsGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour, |
| unsigned PC, unsigned HwMode) |
| : TargetRegisterInfo(MipsRegInfoDesc, RegisterClasses, RegisterClasses+73, |
| SubRegIndexNameTable, SubRegIndexLaneMaskTable, |
| LaneBitmask(0xFFFFFF80), RegClassInfos, HwMode) { |
| InitMCRegisterInfo(MipsRegDesc, 418, RA, PC, |
| MipsMCRegisterClasses, 73, |
| MipsRegUnitRoots, |
| 297, |
| MipsRegDiffLists, |
| MipsLaneMaskLists, |
| MipsRegStrings, |
| MipsRegClassStrings, |
| MipsSubRegIdxLists, |
| 12, |
| MipsSubRegIdxRanges, |
| MipsRegEncodingTable); |
| |
| switch (DwarfFlavour) { |
| default: |
| llvm_unreachable("Unknown DWARF flavour"); |
| case 0: |
| mapDwarfRegsToLLVMRegs(MipsDwarfFlavour0Dwarf2L, MipsDwarfFlavour0Dwarf2LSize, false); |
| break; |
| } |
| switch (EHFlavour) { |
| default: |
| llvm_unreachable("Unknown DWARF flavour"); |
| case 0: |
| mapDwarfRegsToLLVMRegs(MipsEHFlavour0Dwarf2L, MipsEHFlavour0Dwarf2LSize, true); |
| break; |
| } |
| switch (DwarfFlavour) { |
| default: |
| llvm_unreachable("Unknown DWARF flavour"); |
| case 0: |
| mapLLVMRegsToDwarfRegs(MipsDwarfFlavour0L2Dwarf, MipsDwarfFlavour0L2DwarfSize, false); |
| break; |
| } |
| switch (EHFlavour) { |
| default: |
| llvm_unreachable("Unknown DWARF flavour"); |
| case 0: |
| mapLLVMRegsToDwarfRegs(MipsEHFlavour0L2Dwarf, MipsEHFlavour0L2DwarfSize, true); |
| break; |
| } |
| } |
| |
| static const MCPhysReg CSR_Interrupt_32_SaveList[] = { Mips::A3, Mips::A2, Mips::A1, Mips::A0, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, Mips::V1, Mips::V0, Mips::T9, Mips::T8, Mips::T7, Mips::T6, Mips::T5, Mips::T4, Mips::T3, Mips::T2, Mips::T1, Mips::T0, Mips::RA, Mips::FP, Mips::GP, Mips::AT, Mips::LO0, Mips::HI0, 0 }; |
| static const uint32_t CSR_Interrupt_32_RegMask[] = { 0x07c80302, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x20000000, 0x00000000, 0xffbfc008, 0x00000007, 0x00000000, 0x00000000, 0x00000000, }; |
| static const MCPhysReg CSR_Interrupt_32R6_SaveList[] = { Mips::A3, Mips::A2, Mips::A1, Mips::A0, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, Mips::V1, Mips::V0, Mips::T9, Mips::T8, Mips::T7, Mips::T6, Mips::T5, Mips::T4, Mips::T3, Mips::T2, Mips::T1, Mips::T0, Mips::RA, Mips::FP, Mips::GP, Mips::AT, 0 }; |
| static const uint32_t CSR_Interrupt_32R6_RegMask[] = { 0x03c80302, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffbfc000, 0x00000007, 0x00000000, 0x00000000, 0x00000000, }; |
| static const MCPhysReg CSR_Interrupt_64_SaveList[] = { Mips::A3_64, Mips::A2_64, Mips::A1_64, Mips::A0_64, Mips::S7_64, Mips::S6_64, Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64, Mips::S0_64, Mips::T9_64, Mips::T8_64, Mips::T7_64, Mips::T6_64, Mips::T5_64, Mips::T4_64, Mips::T3_64, Mips::T2_64, Mips::T1_64, Mips::T0_64, Mips::V1_64, Mips::V0_64, Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::AT_64, Mips::LO0_64, Mips::HI0_64, 0 }; |
| static const uint32_t CSR_Interrupt_64_RegMask[] = { 0x47c80302, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x08000000, 0x30000000, 0x00000000, 0xffbfe008, 0x00000007, 0x000001f0, 0xffffe400, 0x00000003, }; |
| static const MCPhysReg CSR_Interrupt_64R6_SaveList[] = { Mips::A3_64, Mips::A2_64, Mips::A1_64, Mips::A0_64, Mips::V1_64, Mips::V0_64, Mips::S7_64, Mips::S6_64, Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64, Mips::S0_64, Mips::T9_64, Mips::T8_64, Mips::T7_64, Mips::T6_64, Mips::T5_64, Mips::T4_64, Mips::T3_64, Mips::T2_64, Mips::T1_64, Mips::T0_64, Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::AT_64, 0 }; |
| static const uint32_t CSR_Interrupt_64R6_RegMask[] = { 0x43c80302, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x08000000, 0x10000000, 0x00000000, 0xffbfe000, 0x00000007, 0x000000f0, 0xffffc000, 0x00000003, }; |
| static const MCPhysReg CSR_Mips16RetHelper_SaveList[] = { Mips::V0, Mips::V1, Mips::FP, Mips::A3, Mips::A2, Mips::A1, Mips::A0, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, Mips::D15, Mips::D14, Mips::D13, Mips::D12, Mips::D11, Mips::D10, 0 }; |
| static const uint32_t CSR_Mips16RetHelper_RegMask[] = { 0x03c00100, 0x00000000, 0x00000000, 0x00000000, 0x00007e00, 0x0007ff80, 0x00000000, 0x00000000, 0x00000000, 0x003fc000, 0x00000006, 0x00000000, 0x00000000, 0x00000000, }; |
| static const MCPhysReg CSR_N32_SaveList[] = { Mips::D20_64, Mips::D22_64, Mips::D24_64, Mips::D26_64, Mips::D28_64, Mips::D30_64, Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::S7_64, Mips::S6_64, Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64, Mips::S0_64, 0 }; |
| static const uint32_t CSR_N32_RegMask[] = { 0x00080300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0002aa80, 0x08000000, 0x15550000, 0x00000000, 0x003fe000, 0x00000000, 0xa0000000, 0x003fc0aa, 0x00000000, }; |
| static const MCPhysReg CSR_N64_SaveList[] = { Mips::D31_64, Mips::D30_64, Mips::D29_64, Mips::D28_64, Mips::D27_64, Mips::D26_64, Mips::D25_64, Mips::D24_64, Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::S7_64, Mips::S6_64, Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64, Mips::S0_64, 0 }; |
| static const uint32_t CSR_N64_RegMask[] = { 0x00080300, 0x00000000, 0x00000000, 0x00000000, 0x00007800, 0x0007f800, 0x08000000, 0x1ff00000, 0x00000000, 0x003fe000, 0x00000000, 0x00000000, 0x003fc1fe, 0x00000000, }; |
| static const MCPhysReg CSR_O32_SaveList[] = { Mips::D15, Mips::D14, Mips::D13, Mips::D12, Mips::D11, Mips::D10, Mips::RA, Mips::FP, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, 0 }; |
| static const uint32_t CSR_O32_RegMask[] = { 0x00080100, 0x00000000, 0x00000000, 0x00000000, 0x00007e00, 0x0007ff80, 0x00000000, 0x00000000, 0x00000000, 0x003fc000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }; |
| static const MCPhysReg CSR_O32_FP64_SaveList[] = { Mips::D30_64, Mips::D28_64, Mips::D26_64, Mips::D24_64, Mips::D22_64, Mips::D20_64, Mips::RA, Mips::FP, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, 0 }; |
| static const uint32_t CSR_O32_FP64_RegMask[] = { 0x00080100, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0002aa80, 0x00000000, 0x05550000, 0x00000000, 0x003fc000, 0x00000000, 0xa0000000, 0x000000aa, 0x00000000, }; |
| static const MCPhysReg CSR_O32_FPXX_SaveList[] = { Mips::D15, Mips::D14, Mips::D13, Mips::D12, Mips::D11, Mips::D10, Mips::RA, Mips::FP, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, 0 }; |
| static const uint32_t CSR_O32_FPXX_RegMask[] = { 0x00080100, 0x00000000, 0x00000000, 0x00000000, 0x00007e00, 0x0007ff80, 0x00000000, 0x00000000, 0x00000000, 0x003fc000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }; |
| static const MCPhysReg CSR_SingleFloatOnly_SaveList[] = { Mips::F31, Mips::F30, Mips::F29, Mips::F28, Mips::F27, Mips::F26, Mips::F25, Mips::F24, Mips::F23, Mips::F22, Mips::F21, Mips::F20, Mips::RA, Mips::FP, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, 0 }; |
| static const uint32_t CSR_SingleFloatOnly_RegMask[] = { 0x00080100, 0x00000000, 0x00000000, 0x00000000, 0x00007e00, 0x0007ff80, 0x00000000, 0x00000000, 0x00000000, 0x003fc000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }; |
| |
| |
| ArrayRef<const uint32_t *> MipsGenRegisterInfo::getRegMasks() const { |
| static const uint32_t *const Masks[] = { |
| CSR_Interrupt_32_RegMask, |
| CSR_Interrupt_32R6_RegMask, |
| CSR_Interrupt_64_RegMask, |
| CSR_Interrupt_64R6_RegMask, |
| CSR_Mips16RetHelper_RegMask, |
| CSR_N32_RegMask, |
| CSR_N64_RegMask, |
| CSR_O32_RegMask, |
| CSR_O32_FP64_RegMask, |
| CSR_O32_FPXX_RegMask, |
| CSR_SingleFloatOnly_RegMask, |
| }; |
| return makeArrayRef(Masks); |
| } |
| |
| ArrayRef<const char *> MipsGenRegisterInfo::getRegMaskNames() const { |
| static const char *const Names[] = { |
| "CSR_Interrupt_32", |
| "CSR_Interrupt_32R6", |
| "CSR_Interrupt_64", |
| "CSR_Interrupt_64R6", |
| "CSR_Mips16RetHelper", |
| "CSR_N32", |
| "CSR_N64", |
| "CSR_O32", |
| "CSR_O32_FP64", |
| "CSR_O32_FPXX", |
| "CSR_SingleFloatOnly", |
| }; |
| return makeArrayRef(Names); |
| } |
| |
| const MipsFrameLowering * |
| MipsGenRegisterInfo::getFrameLowering(const MachineFunction &MF) { |
| return static_cast<const MipsFrameLowering *>( |
| MF.getSubtarget().getFrameLowering()); |
| } |
| |
| } // end namespace llvm |
| |
| #endif // GET_REGINFO_TARGET_DESC |
| |