Refactor AsmAddress creation
Instead of using target lowering methods such as stackVarToAsmAddress()
for creating AsmAddress objects, which requires assembler-specific
knowledge, move this logic into AsmAddress constructors and encapsulate
its details.
This will facilitate moving the assembler traits into the assembler
header and source files.
Bug: b/192890685
Change-Id: I59eef85c03ab71e2ac9396e60cbb4c3c59151cd4
Reviewed-on: https://swiftshader-review.googlesource.com/c/SwiftShader/+/55808
Presubmit-Ready: Nicolas Capens <nicolascapens@google.com>
Kokoro-Result: kokoro <noreply+kokoro@google.com>
Tested-by: Nicolas Capens <nicolascapens@google.com>
Reviewed-by: Sean Risser <srisser@google.com>
Reviewed-by: Nicolas Capens <nicolascapens@google.com>
diff --git a/third_party/subzero/src/IceAssemblerX8632.cpp b/third_party/subzero/src/IceAssemblerX8632.cpp
index 03696de..dbe6da2 100644
--- a/third_party/subzero/src/IceAssemblerX8632.cpp
+++ b/third_party/subzero/src/IceAssemblerX8632.cpp
@@ -24,10 +24,97 @@
#include "IceCfg.h"
#include "IceCfgNode.h"
#include "IceOperand.h"
+#include "IceTargetLoweringX8632.h"
namespace Ice {
namespace X8632 {
+AsmAddress::AsmAddress(const Variable *Var, const TargetX8632 *Target) {
+ if (Var->hasReg())
+ llvm::report_fatal_error("Stack Variable has a register assigned");
+ if (Var->mustHaveReg()) {
+ llvm::report_fatal_error("Infinite-weight Variable (" + Var->getName() +
+ ") has no register assigned - function " +
+ Target->getFunc()->getFunctionName());
+ }
+ int32_t Offset = Var->getStackOffset();
+ auto BaseRegNum = Var->getBaseRegNum();
+ if (Var->getBaseRegNum().hasNoValue()) {
+ // If the stack pointer needs alignment, we must use the frame pointer
+ // for arguments. For locals, getFrameOrStackReg will return the stack
+ // pointer in this case.
+ if (Target->needsStackPointerAlignment() && Var->getIsArg()) {
+ assert(Target->hasFramePointer());
+ BaseRegNum = Target->getFrameReg();
+ } else {
+ BaseRegNum = Target->getFrameOrStackReg();
+ }
+ }
+
+ GPRRegister Base = Traits::getEncodedGPR(BaseRegNum);
+
+ if (Utils::IsInt(8, Offset)) {
+ SetModRM(1, Base);
+ if (Base == RegX8632::Encoded_Reg_esp)
+ SetSIB(TIMES_1, RegX8632::Encoded_Reg_esp, Base);
+ SetDisp8(Offset);
+ } else {
+ SetModRM(2, Base);
+ if (Base == RegX8632::Encoded_Reg_esp)
+ SetSIB(TIMES_1, RegX8632::Encoded_Reg_esp, Base);
+ SetDisp32(Offset);
+ }
+}
+
+AsmAddress::AsmAddress(const X86OperandMem *Mem, Ice::Assembler *Asm,
+ const Ice::TargetLowering *Target) {
+ Mem->validateMemOperandPIC();
+ int32_t Disp = 0;
+ if (Mem->getBase() && Mem->getBase()->isRematerializable()) {
+ Disp += Mem->getBase()->getRematerializableOffset(Target);
+ }
+ // The index should never be rematerializable. But if we ever allow it, then
+ // we should make sure the rematerialization offset is shifted by the Shift
+ // value.
+ assert(!Mem->getIndex() || !Mem->getIndex()->isRematerializable());
+
+ AssemblerFixup *Fixup = nullptr;
+ // Determine the offset (is it relocatable?)
+ if (Mem->getOffset()) {
+ if (const auto *CI = llvm::dyn_cast<ConstantInteger32>(Mem->getOffset())) {
+ Disp += static_cast<int32_t>(CI->getValue());
+ } else if (const auto CR =
+ llvm::dyn_cast<ConstantRelocatable>(Mem->getOffset())) {
+ Disp += CR->getOffset();
+ Fixup = Asm->createFixup(Traits::FK_Abs, CR);
+ } else {
+ llvm_unreachable("Unexpected offset type");
+ }
+ }
+
+ // Now convert to the various possible forms.
+ if (Mem->getBase() && Mem->getIndex()) {
+ SetBaseIndex(getEncodedGPR(Mem->getBase()->getRegNum()),
+ getEncodedGPR(Mem->getIndex()->getRegNum()),
+ X8632::Traits::ScaleFactor(Mem->getShift()), Disp, Fixup);
+ } else if (Mem->getBase()) {
+ SetBase(getEncodedGPR(Mem->getBase()->getRegNum()), Disp, Fixup);
+ } else if (Mem->getIndex()) {
+ SetIndex(getEncodedGPR(Mem->getIndex()->getRegNum()),
+ X8632::Traits::ScaleFactor(Mem->getShift()), Disp, Fixup);
+ } else {
+ SetAbsolute(Disp, Fixup);
+ }
+}
+
+AsmAddress::AsmAddress(const VariableSplit *Split, const Cfg *Func) {
+ assert(!Split->getVar()->hasReg());
+ const ::Ice::TargetLowering *Target = Func->getTarget();
+ int32_t Offset = Split->getVar()->getStackOffset() + Split->getOffset();
+ SetBase(getEncodedGPR(Target->getFrameOrStackReg()), Offset,
+ AssemblerFixup::NoFixup);
+}
+
AssemblerX8632::~AssemblerX8632() {
if (BuildDefs::asserts()) {
for (const Label *Label : CfgNodeLabels) {
@@ -616,7 +703,8 @@
emitXmmRegisterOperand(dst, src);
}
-void AssemblerX8632::pand(Type /* Ty */, XmmRegister dst, const AsmAddress &src) {
+void AssemblerX8632::pand(Type /* Ty */, XmmRegister dst,
+ const AsmAddress &src) {
AssemblerBuffer::EnsureCapacity ensured(&Buffer);
emitUint8(0x66);
emitUint8(0x0F);
@@ -632,7 +720,8 @@
emitXmmRegisterOperand(dst, src);
}
-void AssemblerX8632::pandn(Type /* Ty */, XmmRegister dst, const AsmAddress &src) {
+void AssemblerX8632::pandn(Type /* Ty */, XmmRegister dst,
+ const AsmAddress &src) {
AssemblerBuffer::EnsureCapacity ensured(&Buffer);
emitUint8(0x66);
emitUint8(0x0F);
@@ -753,7 +842,8 @@
emitXmmRegisterOperand(dst, src);
}
-void AssemblerX8632::por(Type /* Ty */, XmmRegister dst, const AsmAddress &src) {
+void AssemblerX8632::por(Type /* Ty */, XmmRegister dst,
+ const AsmAddress &src) {
AssemblerBuffer::EnsureCapacity ensured(&Buffer);
emitUint8(0x66);
emitUint8(0x0F);
@@ -853,7 +943,8 @@
emitXmmRegisterOperand(dst, src);
}
-void AssemblerX8632::pxor(Type /* Ty */, XmmRegister dst, const AsmAddress &src) {
+void AssemblerX8632::pxor(Type /* Ty */, XmmRegister dst,
+ const AsmAddress &src) {
AssemblerBuffer::EnsureCapacity ensured(&Buffer);
emitUint8(0x66);
emitUint8(0x0F);
@@ -1001,7 +1092,8 @@
emitXmmRegisterOperand(dst, src);
}
-void AssemblerX8632::addps(Type /* Ty */, XmmRegister dst, const AsmAddress &src) {
+void AssemblerX8632::addps(Type /* Ty */, XmmRegister dst,
+ const AsmAddress &src) {
AssemblerBuffer::EnsureCapacity ensured(&Buffer);
emitUint8(0x0F);
emitUint8(0x58);
@@ -1015,7 +1107,8 @@
emitXmmRegisterOperand(dst, src);
}
-void AssemblerX8632::subps(Type /* Ty */, XmmRegister dst, const AsmAddress &src) {
+void AssemblerX8632::subps(Type /* Ty */, XmmRegister dst,
+ const AsmAddress &src) {
AssemblerBuffer::EnsureCapacity ensured(&Buffer);
emitUint8(0x0F);
emitUint8(0x5C);
@@ -1029,7 +1122,8 @@
emitXmmRegisterOperand(dst, src);
}
-void AssemblerX8632::divps(Type /* Ty */, XmmRegister dst, const AsmAddress &src) {
+void AssemblerX8632::divps(Type /* Ty */, XmmRegister dst,
+ const AsmAddress &src) {
AssemblerBuffer::EnsureCapacity ensured(&Buffer);
emitUint8(0x0F);
emitUint8(0x5E);
@@ -1043,7 +1137,8 @@
emitXmmRegisterOperand(dst, src);
}
-void AssemblerX8632::mulps(Type /* Ty */, XmmRegister dst, const AsmAddress &src) {
+void AssemblerX8632::mulps(Type /* Ty */, XmmRegister dst,
+ const AsmAddress &src) {
AssemblerBuffer::EnsureCapacity ensured(&Buffer);
emitUint8(0x0F);
emitUint8(0x59);
@@ -1338,8 +1433,8 @@
emitUint8(imm.value());
}
-void AssemblerX8632::pshufd(Type /* Ty */, XmmRegister dst, const AsmAddress &src,
- const Immediate &imm) {
+void AssemblerX8632::pshufd(Type /* Ty */, XmmRegister dst,
+ const AsmAddress &src, const Immediate &imm) {
AssemblerBuffer::EnsureCapacity ensured(&Buffer);
emitUint8(0x66);
emitUint8(0x0F);
@@ -1482,8 +1577,8 @@
emitUint8(imm.value());
}
-void AssemblerX8632::shufps(Type /* Ty */, XmmRegister dst, const AsmAddress &src,
- const Immediate &imm) {
+void AssemblerX8632::shufps(Type /* Ty */, XmmRegister dst,
+ const AsmAddress &src, const Immediate &imm) {
AssemblerBuffer::EnsureCapacity ensured(&Buffer);
emitUint8(0x0F);
emitUint8(0xC6);
@@ -2140,7 +2235,8 @@
arith_int<1>(Ty, address, reg);
}
-void AssemblerX8632::Or(Type Ty, const AsmAddress &address, const Immediate &imm) {
+void AssemblerX8632::Or(Type Ty, const AsmAddress &address,
+ const Immediate &imm) {
arith_int<1>(Ty, address, imm);
}
@@ -2456,7 +2552,8 @@
emitGenericShift(0, Ty, AsmOperand(operand), shifter);
}
-void AssemblerX8632::rol(Type Ty, const AsmAddress &operand, GPRRegister shifter) {
+void AssemblerX8632::rol(Type Ty, const AsmAddress &operand,
+ GPRRegister shifter) {
emitGenericShift(0, Ty, operand, shifter);
}
@@ -2468,7 +2565,8 @@
emitGenericShift(4, Ty, AsmOperand(operand), shifter);
}
-void AssemblerX8632::shl(Type Ty, const AsmAddress &operand, GPRRegister shifter) {
+void AssemblerX8632::shl(Type Ty, const AsmAddress &operand,
+ GPRRegister shifter) {
emitGenericShift(4, Ty, operand, shifter);
}
@@ -2480,7 +2578,8 @@
emitGenericShift(5, Ty, AsmOperand(operand), shifter);
}
-void AssemblerX8632::shr(Type Ty, const AsmAddress &operand, GPRRegister shifter) {
+void AssemblerX8632::shr(Type Ty, const AsmAddress &operand,
+ GPRRegister shifter) {
emitGenericShift(5, Ty, operand, shifter);
}
@@ -2492,7 +2591,8 @@
emitGenericShift(7, Ty, AsmOperand(operand), shifter);
}
-void AssemblerX8632::sar(Type Ty, const AsmAddress &address, GPRRegister shifter) {
+void AssemblerX8632::sar(Type Ty, const AsmAddress &address,
+ GPRRegister shifter) {
emitGenericShift(7, Ty, address, shifter);
}
@@ -2831,8 +2931,8 @@
emitUint8(0xF0);
}
-void AssemblerX8632::cmpxchg(Type Ty, const AsmAddress &address, GPRRegister reg,
- bool Locked) {
+void AssemblerX8632::cmpxchg(Type Ty, const AsmAddress &address,
+ GPRRegister reg, bool Locked) {
AssemblerBuffer::EnsureCapacity ensured(&Buffer);
if (Ty == IceType_i16)
emitOperandSizeOverride();
@@ -3112,7 +3212,8 @@
}
}
-void AssemblerX8632::emitGenericShift(int rm, Type Ty, const AsmOperand &operand,
+void AssemblerX8632::emitGenericShift(int rm, Type Ty,
+ const AsmOperand &operand,
GPRRegister shifter) {
AssemblerBuffer::EnsureCapacity ensured(&Buffer);
assert(shifter == Traits::Encoded_Reg_Counter);
diff --git a/third_party/subzero/src/IceAssemblerX8632.h b/third_party/subzero/src/IceAssemblerX8632.h
index b0a375b..d4c1716 100644
--- a/third_party/subzero/src/IceAssemblerX8632.h
+++ b/third_party/subzero/src/IceAssemblerX8632.h
@@ -34,6 +34,15 @@
namespace Ice {
namespace X8632 {
+using Traits = TargetX8632Traits;
+using AsmAddress = typename Traits::AsmAddress;
+using ByteRegister = typename Traits::ByteRegister;
+using BrCond = CondX86::BrCond;
+using CmppsCond = CondX86::CmppsCond;
+using GPRRegister = typename Traits::GPRRegister;
+using AsmOperand = typename Traits::AsmOperand;
+using XmmRegister = typename Traits::XmmRegister;
+
class AssemblerX8632 : public ::Ice::Assembler {
AssemblerX8632(const AssemblerX8632 &) = delete;
AssemblerX8632 &operator=(const AssemblerX8632 &) = delete;
@@ -42,15 +51,6 @@
explicit AssemblerX8632() : Assembler(Asm_X8632) {}
public:
- using Traits = TargetX8632Traits;
- using AsmAddress = typename Traits::AsmAddress;
- using ByteRegister = typename Traits::ByteRegister;
- using BrCond = CondX86::BrCond;
- using CmppsCond = CondX86::CmppsCond;
- using GPRRegister = typename Traits::GPRRegister;
- using AsmOperand = typename Traits::AsmOperand;
- using XmmRegister = typename Traits::XmmRegister;
-
static constexpr int MAX_NOP_SIZE = 8;
static bool classof(const Assembler *Asm) {
@@ -447,16 +447,19 @@
void cvtps2dq(Type, XmmRegister dst, const AsmAddress &src);
void cvtsi2ss(Type DestTy, XmmRegister dst, Type SrcTy, GPRRegister src);
- void cvtsi2ss(Type DestTy, XmmRegister dst, Type SrcTy, const AsmAddress &src);
+ void cvtsi2ss(Type DestTy, XmmRegister dst, Type SrcTy,
+ const AsmAddress &src);
void cvtfloat2float(Type SrcTy, XmmRegister dst, XmmRegister src);
void cvtfloat2float(Type SrcTy, XmmRegister dst, const AsmAddress &src);
void cvttss2si(Type DestTy, GPRRegister dst, Type SrcTy, XmmRegister src);
- void cvttss2si(Type DestTy, GPRRegister dst, Type SrcTy, const AsmAddress &src);
+ void cvttss2si(Type DestTy, GPRRegister dst, Type SrcTy,
+ const AsmAddress &src);
void cvtss2si(Type DestTy, GPRRegister dst, Type SrcTy, XmmRegister src);
- void cvtss2si(Type DestTy, GPRRegister dst, Type SrcTy, const AsmAddress &src);
+ void cvtss2si(Type DestTy, GPRRegister dst, Type SrcTy,
+ const AsmAddress &src);
void ucomiss(Type Ty, XmmRegister a, XmmRegister b);
void ucomiss(Type Ty, XmmRegister a, const AsmAddress &b);
@@ -661,7 +664,8 @@
void mfence();
void lock();
- void cmpxchg(Type Ty, const AsmAddress &address, GPRRegister reg, bool Locked);
+ void cmpxchg(Type Ty, const AsmAddress &address, GPRRegister reg,
+ bool Locked);
void cmpxchg8b(const AsmAddress &address, bool Locked);
void xadd(Type Ty, const AsmAddress &address, GPRRegister reg, bool Locked);
void xchg(Type Ty, GPRRegister reg0, GPRRegister reg1);
diff --git a/third_party/subzero/src/IceAssemblerX8664.cpp b/third_party/subzero/src/IceAssemblerX8664.cpp
index f730760..24c4c10 100644
--- a/third_party/subzero/src/IceAssemblerX8664.cpp
+++ b/third_party/subzero/src/IceAssemblerX8664.cpp
@@ -24,10 +24,82 @@
#include "IceCfg.h"
#include "IceCfgNode.h"
#include "IceOperand.h"
+#include "IceTargetLoweringX8664.h"
namespace Ice {
namespace X8664 {
+AsmAddress::AsmAddress(const Variable *Var, const TargetX8664 *Target) {
+ if (Var->hasReg())
+ llvm::report_fatal_error("Stack Variable has a register assigned");
+ if (Var->mustHaveReg()) {
+ llvm::report_fatal_error("Infinite-weight Variable (" + Var->getName() +
+ ") has no register assigned - function " +
+ Target->getFunc()->getFunctionName());
+ }
+ int32_t Offset = Var->getStackOffset();
+ auto BaseRegNum = Var->getBaseRegNum();
+ if (Var->getBaseRegNum().hasNoValue()) {
+ // If the stack pointer needs alignment, we must use the frame pointer for
+ // arguments. For locals, getFrameOrStackReg will return the stack pointer
+ // in this case.
+ if (Target->needsStackPointerAlignment() && Var->getIsArg()) {
+ assert(Target->hasFramePointer());
+ BaseRegNum = Target->getFrameReg();
+ } else {
+ BaseRegNum = Target->getFrameOrStackReg();
+ }
+ }
+ SetBase(Traits::getEncodedGPR(BaseRegNum), Offset, AssemblerFixup::NoFixup);
+}
+
+AsmAddress::AsmAddress(const X86OperandMem *Mem, Ice::Assembler *Asm,
+ const Ice::TargetLowering *Target) {
+ int32_t Disp = 0;
+ if (Mem->getBase() && Mem->getBase()->isRematerializable()) {
+ Disp += Mem->getBase()->getRematerializableOffset(Target);
+ }
+ // The index should never be rematerializable. But if we ever allow it, then
+ // we should make sure the rematerialization offset is shifted by the Shift
+ // value.
+ assert(!Mem->getIndex() || !Mem->getIndex()->isRematerializable());
+
+ AssemblerFixup *Fixup = nullptr;
+ // Determine the offset (is it relocatable?)
+ if (Mem->getOffset() != nullptr) {
+ if (const auto *CI = llvm::dyn_cast<ConstantInteger32>(Mem->getOffset())) {
+ Disp += static_cast<int32_t>(CI->getValue());
+ } else if (const auto *CR =
+ llvm::dyn_cast<ConstantRelocatable>(Mem->getOffset())) {
+ const auto FixupKind =
+ (Mem->getBase() != nullptr || Mem->getIndex() != nullptr) ? FK_Abs
+ : FK_PcRel;
+ const RelocOffsetT DispAdjustment = FixupKind == FK_PcRel ? 4 : 0;
+ Fixup = Asm->createFixup(FixupKind, CR);
+ Fixup->set_addend(-DispAdjustment);
+ Disp = CR->getOffset();
+ } else {
+ llvm_unreachable("Unexpected offset type");
+ }
+ }
+
+ // Now convert to the various possible forms.
+ if (Mem->getBase() && Mem->getIndex()) {
+ SetBaseIndex(getEncodedGPR(Mem->getBase()->getRegNum()),
+ getEncodedGPR(Mem->getIndex()->getRegNum()),
+ X8664::Traits::ScaleFactor(Mem->getShift()), Disp, Fixup);
+ } else if (Mem->getBase()) {
+ SetBase(getEncodedGPR(Mem->getBase()->getRegNum()), Disp, Fixup);
+ } else if (Mem->getIndex()) {
+ SetIndex(getEncodedGPR(Mem->getIndex()->getRegNum()),
+ X8664::Traits::ScaleFactor(Mem->getShift()), Disp, Fixup);
+ } else if (Fixup == nullptr) {
+ SetAbsolute(Disp);
+ } else {
+ SetRipRelative(Disp, Fixup);
+ }
+}
+
AssemblerX8664::~AssemblerX8664() {
if (BuildDefs::asserts()) {
for (const Label *Label : CfgNodeLabels) {
@@ -672,7 +744,8 @@
emitXmmRegisterOperand(dst, src);
}
-void AssemblerX8664::pand(Type /* Ty */, XmmRegister dst, const AsmAddress &src) {
+void AssemblerX8664::pand(Type /* Ty */, XmmRegister dst,
+ const AsmAddress &src) {
AssemblerBuffer::EnsureCapacity ensured(&Buffer);
emitUint8(0x66);
emitRex(RexTypeIrrelevant, src, dst);
@@ -690,7 +763,8 @@
emitXmmRegisterOperand(dst, src);
}
-void AssemblerX8664::pandn(Type /* Ty */, XmmRegister dst, const AsmAddress &src) {
+void AssemblerX8664::pandn(Type /* Ty */, XmmRegister dst,
+ const AsmAddress &src) {
AssemblerBuffer::EnsureCapacity ensured(&Buffer);
emitUint8(0x66);
emitRex(RexTypeIrrelevant, src, dst);
@@ -823,7 +897,8 @@
emitXmmRegisterOperand(dst, src);
}
-void AssemblerX8664::por(Type /* Ty */, XmmRegister dst, const AsmAddress &src) {
+void AssemblerX8664::por(Type /* Ty */, XmmRegister dst,
+ const AsmAddress &src) {
AssemblerBuffer::EnsureCapacity ensured(&Buffer);
emitUint8(0x66);
emitRex(RexTypeIrrelevant, src, dst);
@@ -931,7 +1006,8 @@
emitXmmRegisterOperand(dst, src);
}
-void AssemblerX8664::pxor(Type /* Ty */, XmmRegister dst, const AsmAddress &src) {
+void AssemblerX8664::pxor(Type /* Ty */, XmmRegister dst,
+ const AsmAddress &src) {
AssemblerBuffer::EnsureCapacity ensured(&Buffer);
emitUint8(0x66);
emitRex(RexTypeIrrelevant, src, dst);
@@ -1090,7 +1166,8 @@
emitXmmRegisterOperand(dst, src);
}
-void AssemblerX8664::addps(Type /* Ty */, XmmRegister dst, const AsmAddress &src) {
+void AssemblerX8664::addps(Type /* Ty */, XmmRegister dst,
+ const AsmAddress &src) {
AssemblerBuffer::EnsureCapacity ensured(&Buffer);
emitRex(RexTypeIrrelevant, src, dst);
emitUint8(0x0F);
@@ -1106,7 +1183,8 @@
emitXmmRegisterOperand(dst, src);
}
-void AssemblerX8664::subps(Type /* Ty */, XmmRegister dst, const AsmAddress &src) {
+void AssemblerX8664::subps(Type /* Ty */, XmmRegister dst,
+ const AsmAddress &src) {
AssemblerBuffer::EnsureCapacity ensured(&Buffer);
emitRex(RexTypeIrrelevant, src, dst);
emitUint8(0x0F);
@@ -1122,7 +1200,8 @@
emitXmmRegisterOperand(dst, src);
}
-void AssemblerX8664::divps(Type /* Ty */, XmmRegister dst, const AsmAddress &src) {
+void AssemblerX8664::divps(Type /* Ty */, XmmRegister dst,
+ const AsmAddress &src) {
AssemblerBuffer::EnsureCapacity ensured(&Buffer);
emitRex(RexTypeIrrelevant, src, dst);
emitUint8(0x0F);
@@ -1138,7 +1217,8 @@
emitXmmRegisterOperand(dst, src);
}
-void AssemblerX8664::mulps(Type /* Ty */, XmmRegister dst, const AsmAddress &src) {
+void AssemblerX8664::mulps(Type /* Ty */, XmmRegister dst,
+ const AsmAddress &src) {
AssemblerBuffer::EnsureCapacity ensured(&Buffer);
emitRex(RexTypeIrrelevant, src, dst);
emitUint8(0x0F);
@@ -1466,8 +1546,8 @@
emitUint8(imm.value());
}
-void AssemblerX8664::pshufd(Type /* Ty */, XmmRegister dst, const AsmAddress &src,
- const Immediate &imm) {
+void AssemblerX8664::pshufd(Type /* Ty */, XmmRegister dst,
+ const AsmAddress &src, const Immediate &imm) {
AssemblerBuffer::EnsureCapacity ensured(&Buffer);
emitUint8(0x66);
emitRex(RexTypeIrrelevant, src, dst);
@@ -1620,8 +1700,8 @@
emitUint8(imm.value());
}
-void AssemblerX8664::shufps(Type /* Ty */, XmmRegister dst, const AsmAddress &src,
- const Immediate &imm) {
+void AssemblerX8664::shufps(Type /* Ty */, XmmRegister dst,
+ const AsmAddress &src, const Immediate &imm) {
AssemblerBuffer::EnsureCapacity ensured(&Buffer);
emitRex(RexTypeIrrelevant, src, dst);
emitUint8(0x0F);
@@ -2283,7 +2363,8 @@
arith_int<1>(Ty, address, reg);
}
-void AssemblerX8664::Or(Type Ty, const AsmAddress &address, const Immediate &imm) {
+void AssemblerX8664::Or(Type Ty, const AsmAddress &address,
+ const Immediate &imm) {
arith_int<1>(Ty, address, imm);
}
@@ -2610,7 +2691,8 @@
emitGenericShift(0, Ty, AsmOperand(operand), shifter);
}
-void AssemblerX8664::rol(Type Ty, const AsmAddress &operand, GPRRegister shifter) {
+void AssemblerX8664::rol(Type Ty, const AsmAddress &operand,
+ GPRRegister shifter) {
emitGenericShift(0, Ty, operand, shifter);
}
@@ -2622,7 +2704,8 @@
emitGenericShift(4, Ty, AsmOperand(operand), shifter);
}
-void AssemblerX8664::shl(Type Ty, const AsmAddress &operand, GPRRegister shifter) {
+void AssemblerX8664::shl(Type Ty, const AsmAddress &operand,
+ GPRRegister shifter) {
emitGenericShift(4, Ty, operand, shifter);
}
@@ -2634,7 +2717,8 @@
emitGenericShift(5, Ty, AsmOperand(operand), shifter);
}
-void AssemblerX8664::shr(Type Ty, const AsmAddress &operand, GPRRegister shifter) {
+void AssemblerX8664::shr(Type Ty, const AsmAddress &operand,
+ GPRRegister shifter) {
emitGenericShift(5, Ty, operand, shifter);
}
@@ -2646,7 +2730,8 @@
emitGenericShift(7, Ty, AsmOperand(operand), shifter);
}
-void AssemblerX8664::sar(Type Ty, const AsmAddress &address, GPRRegister shifter) {
+void AssemblerX8664::sar(Type Ty, const AsmAddress &address,
+ GPRRegister shifter) {
emitGenericShift(7, Ty, address, shifter);
}
@@ -3001,8 +3086,8 @@
emitUint8(0xF0);
}
-void AssemblerX8664::cmpxchg(Type Ty, const AsmAddress &address, GPRRegister reg,
- bool Locked) {
+void AssemblerX8664::cmpxchg(Type Ty, const AsmAddress &address,
+ GPRRegister reg, bool Locked) {
AssemblerBuffer::EnsureCapacity ensured(&Buffer);
if (Ty == IceType_i16)
emitOperandSizeOverride();
@@ -3292,7 +3377,8 @@
}
}
-void AssemblerX8664::emitGenericShift(int rm, Type Ty, const AsmOperand &operand,
+void AssemblerX8664::emitGenericShift(int rm, Type Ty,
+ const AsmOperand &operand,
GPRRegister shifter) {
AssemblerBuffer::EnsureCapacity ensured(&Buffer);
assert(shifter == Traits::Encoded_Reg_Counter);
diff --git a/third_party/subzero/src/IceAssemblerX8664.h b/third_party/subzero/src/IceAssemblerX8664.h
index 22f8292..457a572 100644
--- a/third_party/subzero/src/IceAssemblerX8664.h
+++ b/third_party/subzero/src/IceAssemblerX8664.h
@@ -34,6 +34,15 @@
namespace Ice {
namespace X8664 {
+using Traits = TargetX8664Traits;
+using AsmAddress = typename Traits::AsmAddress;
+using ByteRegister = typename Traits::ByteRegister;
+using BrCond = CondX86::BrCond;
+using CmppsCond = CondX86::CmppsCond;
+using GPRRegister = typename Traits::GPRRegister;
+using AsmOperand = typename Traits::AsmOperand;
+using XmmRegister = typename Traits::XmmRegister;
+
class AssemblerX8664 : public ::Ice::Assembler {
AssemblerX8664(const AssemblerX8664 &) = delete;
AssemblerX8664 &operator=(const AssemblerX8664 &) = delete;
@@ -42,15 +51,6 @@
explicit AssemblerX8664() : Assembler(Asm_X8664) {}
public:
- using Traits = TargetX8664Traits;
- using AsmAddress = typename Traits::AsmAddress;
- using ByteRegister = typename Traits::ByteRegister;
- using BrCond = CondX86::BrCond;
- using CmppsCond = CondX86::CmppsCond;
- using GPRRegister = typename Traits::GPRRegister;
- using AsmOperand = typename Traits::AsmOperand;
- using XmmRegister = typename Traits::XmmRegister;
-
static constexpr int MAX_NOP_SIZE = 8;
static bool classof(const Assembler *Asm) {
@@ -446,16 +446,19 @@
void cvtps2dq(Type, XmmRegister dst, const AsmAddress &src);
void cvtsi2ss(Type DestTy, XmmRegister dst, Type SrcTy, GPRRegister src);
- void cvtsi2ss(Type DestTy, XmmRegister dst, Type SrcTy, const AsmAddress &src);
+ void cvtsi2ss(Type DestTy, XmmRegister dst, Type SrcTy,
+ const AsmAddress &src);
void cvtfloat2float(Type SrcTy, XmmRegister dst, XmmRegister src);
void cvtfloat2float(Type SrcTy, XmmRegister dst, const AsmAddress &src);
void cvttss2si(Type DestTy, GPRRegister dst, Type SrcTy, XmmRegister src);
- void cvttss2si(Type DestTy, GPRRegister dst, Type SrcTy, const AsmAddress &src);
+ void cvttss2si(Type DestTy, GPRRegister dst, Type SrcTy,
+ const AsmAddress &src);
void cvtss2si(Type DestTy, GPRRegister dst, Type SrcTy, XmmRegister src);
- void cvtss2si(Type DestTy, GPRRegister dst, Type SrcTy, const AsmAddress &src);
+ void cvtss2si(Type DestTy, GPRRegister dst, Type SrcTy,
+ const AsmAddress &src);
void ucomiss(Type Ty, XmmRegister a, XmmRegister b);
void ucomiss(Type Ty, XmmRegister a, const AsmAddress &b);
@@ -637,7 +640,8 @@
void mfence();
void lock();
- void cmpxchg(Type Ty, const AsmAddress &address, GPRRegister reg, bool Locked);
+ void cmpxchg(Type Ty, const AsmAddress &address, GPRRegister reg,
+ bool Locked);
void cmpxchg8b(const AsmAddress &address, bool Locked);
void xadd(Type Ty, const AsmAddress &address, GPRRegister reg, bool Locked);
void xchg(Type Ty, GPRRegister reg0, GPRRegister reg1);
@@ -749,8 +753,7 @@
// Addr's size.
template <typename RegType, typename RmType>
void assembleAndEmitRex(const Type TyReg, const RegType Reg, const Type TyRm,
- const RmType Rm,
- const AsmAddress *Addr = nullptr) {
+ const RmType Rm, const AsmAddress *Addr = nullptr) {
const uint8_t W = (TyReg == IceType_i64 || TyRm == IceType_i64)
? AsmOperand::RexW
: AsmOperand::RexNone;
diff --git a/third_party/subzero/src/IceInstX8632.cpp b/third_party/subzero/src/IceInstX8632.cpp
index 29bef3b..f82679c 100644
--- a/third_party/subzero/src/IceInstX8632.cpp
+++ b/third_party/subzero/src/IceInstX8632.cpp
@@ -527,11 +527,11 @@
if (Var->hasReg()) {
Asm->call(Traits::getEncodedGPR(Var->getRegNum()));
} else {
- Asm->call(Target->stackVarToAsmAddress(Var, Target));
+ Asm->call(AsmAddress(Var, Target));
}
} else if (const auto *Mem = llvm::dyn_cast<X86OperandMem>(CallTarget)) {
assert(Mem->getSegmentRegister() == X86OperandMem::DefaultSegment);
- Asm->call(Mem->toAsmAddress(Mem, Asm, Target));
+ Asm->call(AsmAddress(Mem, Asm, Target));
} else if (const auto *CR = llvm::dyn_cast<ConstantRelocatable>(CallTarget)) {
Asm->call(CR);
} else if (const auto *Imm = llvm::dyn_cast<ConstantInteger32>(CallTarget)) {
@@ -584,21 +584,20 @@
GPRRegister VarReg = Traits::getEncodedGPR(Var->getRegNum());
(Asm->*(Emitter.Reg))(Ty, VarReg);
} else {
- AsmAddress StackAddr(Target->stackVarToAsmAddress(Var, Target));
+ AsmAddress StackAddr(AsmAddress(Var, Target));
(Asm->*(Emitter.Addr))(Ty, StackAddr);
}
} else if (const auto *Mem = llvm::dyn_cast<X86OperandMem>(Op)) {
Mem->emitSegmentOverride(Asm);
- (Asm->*(Emitter.Addr))(Ty, Mem->toAsmAddress(Mem, Asm, Target));
+ (Asm->*(Emitter.Addr))(Ty, AsmAddress(Mem, Asm, Target));
} else {
llvm_unreachable("Unexpected operand type");
}
}
template <bool VarCanBeByte, bool SrcCanBeByte>
-void emitIASRegOpTyGPR(const Cfg *Func, bool IsLea, Type Ty,
- const Variable *Var, const Operand *Src,
- const GPREmitterRegOp &Emitter) {
+void emitIASRegOpTyGPR(const Cfg *Func, Type Ty, const Variable *Var,
+ const Operand *Src, const GPREmitterRegOp &Emitter) {
auto *Target = InstX86Base::getTarget(Func);
Assembler *Asm = Func->getAssembler<Assembler>();
assert(Var->hasReg());
@@ -612,24 +611,23 @@
: Traits::getEncodedGPR(SrcVar->getRegNum());
(Asm->*(Emitter.GPRGPR))(Ty, VarReg, SrcReg);
} else {
- AsmAddress SrcStackAddr = Target->stackVarToAsmAddress(SrcVar, Target);
+ AsmAddress SrcStackAddr = AsmAddress(SrcVar, Target);
(Asm->*(Emitter.GPRAddr))(Ty, VarReg, SrcStackAddr);
}
} else if (const auto *Mem = llvm::dyn_cast<X86OperandMem>(Src)) {
Mem->emitSegmentOverride(Asm);
- (Asm->*(Emitter.GPRAddr))(Ty, VarReg,
- Mem->toAsmAddress(Mem, Asm, Target, IsLea));
+ (Asm->*(Emitter.GPRAddr))(Ty, VarReg, AsmAddress(Mem, Asm, Target));
} else if (const auto *Imm = llvm::dyn_cast<ConstantInteger32>(Src)) {
(Asm->*(Emitter.GPRImm))(Ty, VarReg, AssemblerImmediate(Imm->getValue()));
} else if (const auto *Reloc = llvm::dyn_cast<ConstantRelocatable>(Src)) {
const auto FixupKind = (Reloc->getName().hasStdString() &&
Reloc->getName().toString() == GlobalOffsetTable)
? Traits::FK_GotPC
- : Traits::TargetLowering::getAbsFixup();
+ : Traits::FK_Abs;
AssemblerFixup *Fixup = Asm->createFixup(FixupKind, Reloc);
(Asm->*(Emitter.GPRImm))(Ty, VarReg, AssemblerImmediate(Fixup));
} else if (const auto *Split = llvm::dyn_cast<VariableSplit>(Src)) {
- (Asm->*(Emitter.GPRAddr))(Ty, VarReg, Split->toAsmAddress(Split, Func));
+ (Asm->*(Emitter.GPRAddr))(Ty, VarReg, AsmAddress(Split, Func));
} else {
llvm_unreachable("Unexpected operand type");
}
@@ -649,7 +647,7 @@
const auto FixupKind = (Reloc->getName().hasStdString() &&
Reloc->getName().toString() == GlobalOffsetTable)
? Traits::FK_GotPC
- : Traits::TargetLowering::getAbsFixup();
+ : Traits::FK_Abs;
AssemblerFixup *Fixup = Asm->createFixup(FixupKind, Reloc);
(Asm->*(Emitter.AddrImm))(Ty, Addr, AssemblerImmediate(Fixup));
} else {
@@ -662,16 +660,14 @@
auto *Target = InstX86Base::getTarget(Func);
if (const auto *Op0Var = llvm::dyn_cast<Variable>(Op0)) {
assert(!Op0Var->hasReg());
- AsmAddress StackAddr(Target->stackVarToAsmAddress(Op0Var, Target));
+ AsmAddress StackAddr(AsmAddress(Op0Var, Target));
emitIASAddrOpTyGPR(Func, Ty, StackAddr, Op1, Emitter);
} else if (const auto *Op0Mem = llvm::dyn_cast<X86OperandMem>(Op0)) {
Assembler *Asm = Func->getAssembler<Assembler>();
Op0Mem->emitSegmentOverride(Asm);
- emitIASAddrOpTyGPR(Func, Ty, Op0Mem->toAsmAddress(Op0Mem, Asm, Target), Op1,
- Emitter);
+ emitIASAddrOpTyGPR(Func, Ty, AsmAddress(Op0Mem, Asm, Target), Op1, Emitter);
} else if (const auto *Split = llvm::dyn_cast<VariableSplit>(Op0)) {
- emitIASAddrOpTyGPR(Func, Ty, Split->toAsmAddress(Split, Func), Op1,
- Emitter);
+ emitIASAddrOpTyGPR(Func, Ty, AsmAddress(Split, Func), Op1, Emitter);
} else {
llvm_unreachable("Unexpected operand type");
}
@@ -730,12 +726,12 @@
XmmRegister SrcReg = Traits::getEncodedXmm(SrcVar->getRegNum());
(Asm->*(Emitter.XmmXmm))(Ty, VarReg, SrcReg);
} else {
- AsmAddress SrcStackAddr = Target->stackVarToAsmAddress(SrcVar, Target);
+ AsmAddress SrcStackAddr = AsmAddress(SrcVar, Target);
(Asm->*(Emitter.XmmAddr))(Ty, VarReg, SrcStackAddr);
}
} else if (const auto *Mem = llvm::dyn_cast<X86OperandMem>(Src)) {
assert(Mem->getSegmentRegister() == X86OperandMem::DefaultSegment);
- (Asm->*(Emitter.XmmAddr))(Ty, VarReg, Mem->toAsmAddress(Mem, Asm, Target));
+ (Asm->*(Emitter.XmmAddr))(Ty, VarReg, AsmAddress(Mem, Asm, Target));
} else if (const auto *Imm = llvm::dyn_cast<ConstantInteger32>(Src)) {
(Asm->*(Emitter.XmmImm))(Ty, VarReg, AssemblerImmediate(Imm->getValue()));
} else {
@@ -754,14 +750,14 @@
XmmRegister SrcReg = Traits::getEncodedXmm(SrcVar->getRegNum());
(Asm->*(Emitter.XmmXmm))(Ty, VarReg, SrcReg);
} else {
- AsmAddress SrcStackAddr = Target->stackVarToAsmAddress(SrcVar, Target);
+ AsmAddress SrcStackAddr = AsmAddress(SrcVar, Target);
(Asm->*(Emitter.XmmAddr))(Ty, VarReg, SrcStackAddr);
}
} else if (const auto *Mem = llvm::dyn_cast<X86OperandMem>(Src)) {
assert(Mem->getSegmentRegister() == X86OperandMem::DefaultSegment);
- (Asm->*(Emitter.XmmAddr))(Ty, VarReg, Mem->toAsmAddress(Mem, Asm, Target));
+ (Asm->*(Emitter.XmmAddr))(Ty, VarReg, AsmAddress(Mem, Asm, Target));
} else if (const auto *Imm = llvm::dyn_cast<Constant>(Src)) {
- (Asm->*(Emitter.XmmAddr))(Ty, VarReg, AsmAddress::ofConstPool(Asm, Imm));
+ (Asm->*(Emitter.XmmAddr))(Ty, VarReg, AsmAddress(Imm, Asm));
} else {
llvm_unreachable("Unexpected operand type");
}
@@ -781,13 +777,13 @@
SReg_t SrcReg = srcEnc(SrcVar->getRegNum());
(Asm->*(Emitter.RegReg))(DestTy, DestReg, SrcTy, SrcReg);
} else {
- AsmAddress SrcStackAddr = Target->stackVarToAsmAddress(SrcVar, Target);
+ AsmAddress SrcStackAddr = AsmAddress(SrcVar, Target);
(Asm->*(Emitter.RegAddr))(DestTy, DestReg, SrcTy, SrcStackAddr);
}
} else if (const auto *Mem = llvm::dyn_cast<X86OperandMem>(Src)) {
Mem->emitSegmentOverride(Asm);
(Asm->*(Emitter.RegAddr))(DestTy, DestReg, SrcTy,
- Mem->toAsmAddress(Mem, Asm, Target));
+ AsmAddress(Mem, Asm, Target));
} else {
llvm_unreachable("Unexpected operand type");
}
@@ -810,13 +806,13 @@
SReg_t SrcReg = srcEnc(SrcVar->getRegNum());
(Asm->*(Emitter.RegRegImm))(DispatchTy, DestReg, SrcReg, Imm);
} else {
- AsmAddress SrcStackAddr = Target->stackVarToAsmAddress(SrcVar, Target);
+ AsmAddress SrcStackAddr = AsmAddress(SrcVar, Target);
(Asm->*(Emitter.RegAddrImm))(DispatchTy, DestReg, SrcStackAddr, Imm);
}
} else if (const auto *Mem = llvm::dyn_cast<X86OperandMem>(Src0)) {
Mem->emitSegmentOverride(Asm);
(Asm->*(Emitter.RegAddrImm))(DispatchTy, DestReg,
- Mem->toAsmAddress(Mem, Asm, Target), Imm);
+ AsmAddress(Mem, Asm, Target), Imm);
} else {
llvm_unreachable("Unexpected operand type");
}
@@ -833,18 +829,17 @@
(Asm->*(Emitter.XmmXmm))(DestReg,
Traits::getEncodedXmm(SrcVar->getRegNum()));
} else {
- AsmAddress StackAddr(Target->stackVarToAsmAddress(SrcVar, Target));
+ AsmAddress StackAddr(AsmAddress(SrcVar, Target));
(Asm->*(Emitter.XmmAddr))(DestReg, StackAddr);
}
} else if (const auto *SrcMem = llvm::dyn_cast<X86OperandMem>(Src)) {
assert(SrcMem->getSegmentRegister() == X86OperandMem::DefaultSegment);
- (Asm->*(Emitter.XmmAddr))(DestReg,
- SrcMem->toAsmAddress(SrcMem, Asm, Target));
+ (Asm->*(Emitter.XmmAddr))(DestReg, AsmAddress(SrcMem, Asm, Target));
} else {
llvm_unreachable("Unexpected operand type");
}
} else {
- AsmAddress StackAddr(Target->stackVarToAsmAddress(Dest, Target));
+ AsmAddress StackAddr(AsmAddress(Dest, Target));
// Src must be a register in this case.
const auto *SrcVar = llvm::cast<Variable>(Src);
assert(SrcVar->hasReg());
@@ -1052,8 +1047,7 @@
assert(Var == this->getSrc(0));
static const GPREmitterRegOp Emitter = {&Assembler::imul, &Assembler::imul,
&Assembler::imul};
- constexpr bool NotLea = false;
- emitIASRegOpTyGPR(Func, NotLea, Ty, Var, Src, Emitter);
+ emitIASRegOpTyGPR(Func, Ty, Var, Src, Emitter);
}
}
@@ -1309,13 +1303,13 @@
} else {
Asm->cmov(SrcTy, Condition,
Traits::getEncodedGPR(this->getDest()->getRegNum()),
- Target->stackVarToAsmAddress(SrcVar, Target));
+ AsmAddress(SrcVar, Target));
}
} else if (const auto *Mem = llvm::dyn_cast<X86OperandMem>(Src)) {
assert(Mem->getSegmentRegister() == X86OperandMem::DefaultSegment);
Asm->cmov(SrcTy, Condition,
Traits::getEncodedGPR(this->getDest()->getRegNum()),
- Mem->toAsmAddress(Mem, Asm, Target));
+ AsmAddress(Mem, Asm, Target));
} else {
llvm_unreachable("Unexpected operand type");
}
@@ -1362,7 +1356,7 @@
Traits::getEncodedXmm(this->getDest()->getRegNum()),
Traits::getEncodedXmm(SrcVar->getRegNum()), Condition);
} else {
- AsmAddress SrcStackAddr = Target->stackVarToAsmAddress(SrcVar, Target);
+ AsmAddress SrcStackAddr = AsmAddress(SrcVar, Target);
Asm->cmpps(this->getDest()->getType(),
Traits::getEncodedXmm(this->getDest()->getRegNum()),
SrcStackAddr, Condition);
@@ -1405,7 +1399,7 @@
auto *Target = InstX86Base::getTarget(Func);
const auto Mem = llvm::cast<X86OperandMem>(this->getSrc(0));
assert(Mem->getSegmentRegister() == X86OperandMem::DefaultSegment);
- const AsmAddress Addr = Mem->toAsmAddress(Mem, Asm, Target);
+ const AsmAddress Addr = AsmAddress(Mem, Asm, Target);
const auto *VarReg = llvm::cast<Variable>(this->getSrc(2));
assert(VarReg->hasReg());
const GPRRegister Reg = Traits::getEncodedGPR(VarReg->getRegNum());
@@ -1443,7 +1437,7 @@
const auto Mem = llvm::cast<X86OperandMem>(this->getSrc(0));
assert(Mem->getSegmentRegister() == X86OperandMem::DefaultSegment);
auto *Target = InstX86Base::getTarget(Func);
- const AsmAddress Addr = Mem->toAsmAddress(Mem, Asm, Target);
+ const AsmAddress Addr = AsmAddress(Mem, Asm, Target);
Asm->cmpxchg8b(Addr, this->Locked);
}
@@ -1613,8 +1607,7 @@
&Assembler::cmp};
if (const auto *SrcVar0 = llvm::dyn_cast<Variable>(Src0)) {
if (SrcVar0->hasReg()) {
- constexpr bool NotLea = false;
- emitIASRegOpTyGPR(Func, NotLea, Ty, SrcVar0, Src1, RegEmitter);
+ emitIASRegOpTyGPR(Func, Ty, SrcVar0, Src1, RegEmitter);
return;
}
}
@@ -1729,8 +1722,7 @@
&Assembler::test};
if (const auto *SrcVar0 = llvm::dyn_cast<Variable>(Src0)) {
if (SrcVar0->hasReg()) {
- constexpr bool NotLea = false;
- emitIASRegOpTyGPR(Func, NotLea, Ty, SrcVar0, Src1, RegEmitter);
+ emitIASRegOpTyGPR(Func, Ty, SrcVar0, Src1, RegEmitter);
return;
}
}
@@ -1795,12 +1787,12 @@
auto *Target = InstX86Base::getTarget(Func);
if (const auto *DestVar = llvm::dyn_cast<Variable>(Dest)) {
assert(!DestVar->hasReg());
- AsmAddress StackAddr(Target->stackVarToAsmAddress(DestVar, Target));
+ AsmAddress StackAddr(AsmAddress(DestVar, Target));
Asm->movss(DestTy, StackAddr, SrcReg);
} else {
const auto DestMem = llvm::cast<X86OperandMem>(Dest);
assert(DestMem->getSegmentRegister() == X86OperandMem::DefaultSegment);
- Asm->movss(DestTy, DestMem->toAsmAddress(DestMem, Asm, Target), SrcReg);
+ Asm->movss(DestTy, AsmAddress(DestMem, Asm, Target), SrcReg);
}
return;
} else {
@@ -1842,7 +1834,7 @@
assert(DestMem->getSegmentRegister() == X86OperandMem::DefaultSegment);
assert(SrcVar->hasReg());
auto *Target = InstX86Base::getTarget(Func);
- Asm->movups(DestMem->toAsmAddress(DestMem, Asm, Target),
+ Asm->movups(AsmAddress(DestMem, Asm, Target),
Traits::getEncodedXmm(SrcVar->getRegNum()));
}
@@ -1879,7 +1871,7 @@
assert(DestMem->getSegmentRegister() == X86OperandMem::DefaultSegment);
assert(SrcVar->hasReg());
auto *Target = InstX86Base::getTarget(Func);
- Asm->movq(DestMem->toAsmAddress(DestMem, Asm, Target),
+ Asm->movq(AsmAddress(DestMem, Asm, Target),
Traits::getEncodedXmm(SrcVar->getRegNum()));
}
@@ -1916,7 +1908,7 @@
assert(DestMem->getSegmentRegister() == X86OperandMem::DefaultSegment);
assert(SrcVar->hasReg());
auto *Target = InstX86Base::getTarget(Func);
- Asm->movd(SrcVar->getType(), DestMem->toAsmAddress(DestMem, Asm, Target),
+ Asm->movd(SrcVar->getType(), AsmAddress(DestMem, Asm, Target),
Traits::getEncodedXmm(SrcVar->getRegNum()));
}
@@ -1963,14 +1955,13 @@
const Variable *Var = this->getDest();
Type Ty = Var->getType();
const Operand *Src = this->getSrc(0);
- bool IsLea = true;
if (auto *Add = this->deoptToAddOrNull(Func)) {
Add->emitIAS(Func);
return;
}
- emitIASRegOpTyGPR(Func, IsLea, Ty, Var, Src, Emitter);
+ emitIASRegOpTyGPR(Func, Ty, Var, Src, Emitter);
}
Inst *InstX86Lea::deoptToAddOrNull(const Cfg *Func) const {
@@ -2061,14 +2052,13 @@
if (isScalarIntegerType(SrcTy)) {
SrcTy = DestTy;
}
- constexpr bool NotLea = false;
- emitIASRegOpTyGPR(Func, NotLea, DestTy, Dest, Src, GPRRegEmitter);
+ emitIASRegOpTyGPR(Func, DestTy, Dest, Src, GPRRegEmitter);
return;
}
} else {
// Dest must be Stack and Src *could* be a register. Use Src's type to
// decide on the emitters.
- AsmAddress StackAddr(Target->stackVarToAsmAddress(Dest, Target));
+ AsmAddress StackAddr(AsmAddress(Dest, Target));
if (isScalarFloatingType(SrcTy)) {
// Src must be a register.
const auto *SrcVar = llvm::cast<Variable>(Src);
@@ -2134,7 +2124,7 @@
Asm->movd(SrcVar->getType(), DestReg,
Traits::getEncodedGPR(SrcVar->getRegNum()));
} else {
- AsmAddress StackAddr(Target->stackVarToAsmAddress(SrcVar, Target));
+ AsmAddress StackAddr(AsmAddress(SrcVar, Target));
Asm->movd(SrcVar->getType(), DestReg, StackAddr);
}
} else {
@@ -2149,7 +2139,7 @@
Asm->movd(Dest->getType(), Traits::getEncodedGPR(Dest->getRegNum()),
SrcReg);
} else {
- AsmAddress StackAddr(Target->stackVarToAsmAddress(Dest, Target));
+ AsmAddress StackAddr(AsmAddress(Dest, Target));
Asm->movd(Dest->getType(), StackAddr, SrcReg);
}
}
@@ -2157,7 +2147,7 @@
assert(Dest->hasReg());
XmmRegister DestReg = Traits::getEncodedXmm(Dest->getRegNum());
auto *Mem = llvm::cast<X86OperandMem>(this->getSrc(0));
- Asm->movd(Mem->getType(), DestReg, Mem->toAsmAddress(Mem, Asm, Target));
+ Asm->movd(Mem->getType(), DestReg, AsmAddress(Mem, Asm, Target));
}
}
@@ -2236,8 +2226,7 @@
Type SrcTy = Src->getType();
assert(typeWidthInBytes(Dest->getType()) > 1);
assert(typeWidthInBytes(Dest->getType()) > typeWidthInBytes(SrcTy));
- constexpr bool NotLea = false;
- emitIASRegOpTyGPR<false, true>(Func, NotLea, SrcTy, Dest, Src, this->Emitter);
+ emitIASRegOpTyGPR<false, true>(Func, SrcTy, Dest, Src, this->Emitter);
}
void InstX86Movzx::emit(const Cfg *Func) const {
@@ -2253,8 +2242,7 @@
Type SrcTy = Src->getType();
assert(typeWidthInBytes(Dest->getType()) > 1);
assert(typeWidthInBytes(Dest->getType()) > typeWidthInBytes(SrcTy));
- constexpr bool NotLea = false;
- emitIASRegOpTyGPR<false, true>(Func, NotLea, SrcTy, Dest, Src, this->Emitter);
+ emitIASRegOpTyGPR<false, true>(Func, SrcTy, Dest, Src, this->Emitter);
}
void InstX86Nop::emit(const Cfg *Func) const {
@@ -2320,19 +2308,18 @@
// This is a physical xmm register, so we need to spill it to a temporary
// stack slot. Function prolog emission guarantees that there is
// sufficient space to do this.
- AsmAddress StackSlot =
- AsmAddress(RegisterSet::Encoded_Reg_esp, 0, AssemblerFixup::NoFixup);
+ AsmAddress StackSlot = AsmAddress(RegisterSet::Encoded_Reg_esp, 0);
Asm->movss(Ty, StackSlot, Traits::getEncodedXmm(Var->getRegNum()));
Asm->fld(Ty, StackSlot);
} else {
- AsmAddress StackAddr(Target->stackVarToAsmAddress(Var, Target));
+ AsmAddress StackAddr(AsmAddress(Var, Target));
Asm->fld(Ty, StackAddr);
}
} else if (const auto *Mem = llvm::dyn_cast<X86OperandMem>(Src)) {
assert(Mem->getSegmentRegister() == X86OperandMem::DefaultSegment);
- Asm->fld(Ty, Mem->toAsmAddress(Mem, Asm, Target));
+ Asm->fld(Ty, AsmAddress(Mem, Asm, Target));
} else if (const auto *Imm = llvm::dyn_cast<Constant>(Src)) {
- Asm->fld(Ty, AsmAddress::ofConstPool(Asm, Imm));
+ Asm->fld(Ty, AsmAddress(Imm, Asm));
} else {
llvm_unreachable("Unexpected operand type");
}
@@ -2398,14 +2385,13 @@
auto *Target = InstX86Base::getTarget(Func);
Type Ty = Dest->getType();
if (!Dest->hasReg()) {
- AsmAddress StackAddr(Target->stackVarToAsmAddress(Dest, Target));
+ AsmAddress StackAddr(AsmAddress(Dest, Target));
Asm->fstp(Ty, StackAddr);
} else {
// Dest is a physical (xmm) register, so st(0) needs to go through memory.
// Hack this by using caller-reserved memory at the top of stack, spilling
// st(0) there, and loading it into the xmm register.
- AsmAddress StackSlot =
- AsmAddress(RegisterSet::Encoded_Reg_esp, 0, AssemblerFixup::NoFixup);
+ AsmAddress StackSlot = AsmAddress(RegisterSet::Encoded_Reg_esp, 0);
Asm->fstp(Ty, StackSlot);
Asm->movss(Ty, Traits::getEncodedXmm(Dest->getRegNum()), StackSlot);
}
@@ -2553,7 +2539,7 @@
Asm->popl(Traits::getEncodedGPR(this->getDest()->getRegNum()));
} else {
auto *Target = InstX86Base::getTarget(Func);
- Asm->popl(Target->stackVarToAsmAddress(this->getDest(), Target));
+ Asm->popl(AsmAddress(this->getDest(), Target));
}
}
@@ -2645,8 +2631,7 @@
Asm->setcc(Condition,
Traits::getEncodedByteReg(this->getDest()->getRegNum()));
else
- Asm->setcc(Condition,
- Target->stackVarToAsmAddress(this->getDest(), Target));
+ Asm->setcc(Condition, AsmAddress(this->getDest(), Target));
return;
}
@@ -2681,7 +2666,7 @@
const auto Mem = llvm::cast<X86OperandMem>(this->getSrc(0));
assert(Mem->getSegmentRegister() == X86OperandMem::DefaultSegment);
auto *Target = InstX86Base::getTarget(Func);
- const AsmAddress Addr = Mem->toAsmAddress(Mem, Asm, Target);
+ const AsmAddress Addr = AsmAddress(Mem, Asm, Target);
const auto *VarReg = llvm::cast<Variable>(this->getSrc(1));
assert(VarReg->hasReg());
const GPRRegister Reg = Traits::getEncodedGPR(VarReg->getRegNum());
@@ -2730,7 +2715,7 @@
const auto *Mem = llvm::cast<X86OperandMem>(this->getSrc(0));
assert(Mem->getSegmentRegister() == X86OperandMem::DefaultSegment);
auto *Target = InstX86Base::getTarget(Func);
- const AsmAddress Addr = Mem->toAsmAddress(Mem, Asm, Target);
+ const AsmAddress Addr = AsmAddress(Mem, Asm, Target);
Asm->xchg(Ty, Addr, Reg1);
}
@@ -2851,44 +2836,17 @@
}
}
-namespace {
-
-int32_t getRematerializableOffset(Variable *Var,
- const Ice::X8632::TargetX8632 *Target) {
- int32_t Disp = Var->getStackOffset();
- const auto RegNum = Var->getRegNum();
- if (RegNum == Target->getFrameReg()) {
- Disp += Target->getFrameFixedAllocaOffset();
- } else if (RegNum != Target->getStackReg()) {
- llvm::report_fatal_error("Unexpected rematerializable register type");
- }
- return Disp;
-}
-
-void validateMemOperandPIC(const TargetX8632Traits::X86OperandMem *Mem) {
- if (!BuildDefs::asserts())
- return;
- const bool HasCR =
- Mem->getOffset() && llvm::isa<ConstantRelocatable>(Mem->getOffset());
- (void)HasCR;
- const bool IsRebased = Mem->getIsRebased();
- (void)IsRebased;
- assert(!IsRebased);
-}
-
-} // end of anonymous namespace
-
void TargetX8632Traits::X86OperandMem::emit(const Cfg *Func) const {
if (!BuildDefs::dump())
return;
- validateMemOperandPIC(this);
+ validateMemOperandPIC();
const auto *Target =
static_cast<const ::Ice::X8632::TargetX8632 *>(Func->getTarget());
// If the base is rematerializable, we need to replace it with the correct
// physical register (esp or ebp), and update the Offset.
int32_t Disp = 0;
if (getBase() && getBase()->isRematerializable()) {
- Disp += getRematerializableOffset(getBase(), Target);
+ Disp += getBase()->getRematerializableOffset(Target);
}
// The index should never be rematerializable. But if we ever allow it, then
// we should make sure the rematerialization offset is shifted by the Shift
@@ -2948,7 +2906,7 @@
const auto *Target =
static_cast<const ::Ice::X8632::TargetX8632 *>(Func->getTarget());
if (getBase() && getBase()->isRematerializable()) {
- Disp += getRematerializableOffset(getBase(), Target);
+ Disp += getBase()->getRematerializableOffset(Target);
}
if (getBase()) {
if (Func)
@@ -3007,60 +2965,6 @@
}
}
-AsmAddress TargetX8632Traits::X86OperandMem::toAsmAddress(
- const X86OperandMem *Mem, TargetX8632Traits::Assembler *Asm,
- const Ice::TargetLowering *TargetLowering, bool /*IsLeaAddr*/) {
- const auto *Target =
- static_cast<const ::Ice::X8632::TargetX8632 *>(TargetLowering);
- validateMemOperandPIC(Mem);
- int32_t Disp = 0;
- if (Mem->getBase() && Mem->getBase()->isRematerializable()) {
- Disp += getRematerializableOffset(Mem->getBase(), Target);
- }
- // The index should never be rematerializable. But if we ever allow it, then
- // we should make sure the rematerialization offset is shifted by the Shift
- // value.
- if (Mem->getIndex())
- assert(!Mem->getIndex()->isRematerializable());
- AssemblerFixup *Fixup = nullptr;
- // Determine the offset (is it relocatable?)
- if (Mem->getOffset()) {
- if (const auto *CI = llvm::dyn_cast<ConstantInteger32>(Mem->getOffset())) {
- Disp += static_cast<int32_t>(CI->getValue());
- } else if (const auto CR =
- llvm::dyn_cast<ConstantRelocatable>(Mem->getOffset())) {
- Disp += CR->getOffset();
- Fixup = Asm->createFixup(Target->getAbsFixup(), CR);
- } else {
- llvm_unreachable("Unexpected offset type");
- }
- }
-
- // Now convert to the various possible forms.
- if (Mem->getBase() && Mem->getIndex()) {
- return AsmAddress(getEncodedGPR(Mem->getBase()->getRegNum()),
- getEncodedGPR(Mem->getIndex()->getRegNum()),
- X8632::Traits::ScaleFactor(Mem->getShift()), Disp, Fixup);
- } else if (Mem->getBase()) {
- return AsmAddress(getEncodedGPR(Mem->getBase()->getRegNum()), Disp, Fixup);
- } else if (Mem->getIndex()) {
- return AsmAddress(getEncodedGPR(Mem->getIndex()->getRegNum()),
- X8632::Traits::ScaleFactor(Mem->getShift()), Disp, Fixup);
- } else {
- return AsmAddress(Disp, Fixup);
- }
-}
-
-AsmAddress
-TargetX8632Traits::VariableSplit::toAsmAddress(const VariableSplit *Split,
- const Cfg *Func) {
- assert(!Split->getVar()->hasReg());
- const ::Ice::TargetLowering *Target = Func->getTarget();
- int32_t Offset = Split->getVar()->getStackOffset() + Split->getOffset();
- return AsmAddress(getEncodedGPR(Target->getFrameOrStackReg()), Offset,
- AssemblerFixup::NoFixup);
-}
-
void TargetX8632Traits::VariableSplit::emit(const Cfg *Func) const {
if (!BuildDefs::dump())
return;
diff --git a/third_party/subzero/src/IceInstX8632.h b/third_party/subzero/src/IceInstX8632.h
index ce0b44a..e38d627 100644
--- a/third_party/subzero/src/IceInstX8632.h
+++ b/third_party/subzero/src/IceInstX8632.h
@@ -516,9 +516,8 @@
/// Emit a two-operand (GPR) instruction, where the dest operand is a Variable
/// that's guaranteed to be a register.
template <bool VarCanBeByte = true, bool SrcCanBeByte = true>
-void emitIASRegOpTyGPR(const Cfg *Func, bool IsLea, Type Ty,
- const Variable *Dst, const Operand *Src,
- const GPREmitterRegOp &Emitter);
+void emitIASRegOpTyGPR(const Cfg *Func, Type Ty, const Variable *Dst,
+ const Operand *Src, const GPREmitterRegOp &Emitter);
/// Instructions of the form x := op(x).
template <typename InstX86Base::InstKindX86 K>
@@ -600,8 +599,7 @@
const Variable *Var = this->getDest();
Type Ty = Var->getType();
const Operand *Src = this->getSrc(0);
- bool IsLea = false;
- emitIASRegOpTyGPR(Func, IsLea, Ty, Var, Src, Emitter);
+ emitIASRegOpTyGPR(Func, Ty, Var, Src, Emitter);
}
void dump(const Cfg *Func) const override {
if (!BuildDefs::dump())
@@ -732,10 +730,8 @@
void emitIAS(const Cfg *Func) const override {
Type Ty = this->getDest()->getType();
assert(this->getSrcSize() == 2);
- constexpr bool ThisIsLEA = K == InstX86Base::Lea;
- static_assert(!ThisIsLEA, "Lea should be a unaryop.");
- emitIASRegOpTyGPR(Func, !ThisIsLEA, Ty, this->getDest(), this->getSrc(1),
- Emitter);
+ static_assert(K != InstX86Base::Lea, "Lea should be a unaryop.");
+ emitIASRegOpTyGPR(Func, Ty, this->getDest(), this->getSrc(1), Emitter);
}
void dump(const Cfg *Func) const override {
if (!BuildDefs::dump())
diff --git a/third_party/subzero/src/IceInstX8664.cpp b/third_party/subzero/src/IceInstX8664.cpp
index 4f5a53a..39f5212 100644
--- a/third_party/subzero/src/IceInstX8664.cpp
+++ b/third_party/subzero/src/IceInstX8664.cpp
@@ -527,11 +527,11 @@
if (Var->hasReg()) {
Asm->call(Traits::getEncodedGPR(Var->getRegNum()));
} else {
- Asm->call(Target->stackVarToAsmAddress(Var, Target));
+ Asm->call(AsmAddress(Var, Target));
}
} else if (const auto *Mem = llvm::dyn_cast<X86OperandMem>(CallTarget)) {
assert(Mem->getSegmentRegister() == X86OperandMem::DefaultSegment);
- Asm->call(Mem->toAsmAddress(Mem, Asm, Target));
+ Asm->call(AsmAddress(Mem, Asm, Target));
} else if (const auto *CR = llvm::dyn_cast<ConstantRelocatable>(CallTarget)) {
Asm->call(CR);
} else if (const auto *Imm = llvm::dyn_cast<ConstantInteger32>(CallTarget)) {
@@ -584,21 +584,20 @@
GPRRegister VarReg = Traits::getEncodedGPR(Var->getRegNum());
(Asm->*(Emitter.Reg))(Ty, VarReg);
} else {
- AsmAddress StackAddr(Target->stackVarToAsmAddress(Var, Target));
+ AsmAddress StackAddr(AsmAddress(Var, Target));
(Asm->*(Emitter.Addr))(Ty, StackAddr);
}
} else if (const auto *Mem = llvm::dyn_cast<X86OperandMem>(Op)) {
Mem->emitSegmentOverride(Asm);
- (Asm->*(Emitter.Addr))(Ty, Mem->toAsmAddress(Mem, Asm, Target));
+ (Asm->*(Emitter.Addr))(Ty, AsmAddress(Mem, Asm, Target));
} else {
llvm_unreachable("Unexpected operand type");
}
}
template <bool VarCanBeByte, bool SrcCanBeByte>
-void emitIASRegOpTyGPR(const Cfg *Func, bool IsLea, Type Ty,
- const Variable *Var, const Operand *Src,
- const GPREmitterRegOp &Emitter) {
+void emitIASRegOpTyGPR(const Cfg *Func, Type Ty, const Variable *Var,
+ const Operand *Src, const GPREmitterRegOp &Emitter) {
auto *Target = InstX86Base::getTarget(Func);
Assembler *Asm = Func->getAssembler<Assembler>();
assert(Var->hasReg());
@@ -612,13 +611,12 @@
: Traits::getEncodedGPR(SrcVar->getRegNum());
(Asm->*(Emitter.GPRGPR))(Ty, VarReg, SrcReg);
} else {
- AsmAddress SrcStackAddr = Target->stackVarToAsmAddress(SrcVar, Target);
+ AsmAddress SrcStackAddr = AsmAddress(SrcVar, Target);
(Asm->*(Emitter.GPRAddr))(Ty, VarReg, SrcStackAddr);
}
} else if (const auto *Mem = llvm::dyn_cast<X86OperandMem>(Src)) {
Mem->emitSegmentOverride(Asm);
- (Asm->*(Emitter.GPRAddr))(Ty, VarReg,
- Mem->toAsmAddress(Mem, Asm, Target, IsLea));
+ (Asm->*(Emitter.GPRAddr))(Ty, VarReg, AsmAddress(Mem, Asm, Target));
} else if (const auto *Imm = llvm::dyn_cast<ConstantInteger32>(Src)) {
(Asm->*(Emitter.GPRImm))(Ty, VarReg, AssemblerImmediate(Imm->getValue()));
} else if (const auto *Imm = llvm::dyn_cast<ConstantInteger64>(Src)) {
@@ -628,7 +626,7 @@
const auto FixupKind = (Reloc->getName().hasStdString() &&
Reloc->getName().toString() == GlobalOffsetTable)
? Traits::FK_GotPC
- : Traits::TargetLowering::getAbsFixup();
+ : Traits::FK_Abs;
AssemblerFixup *Fixup = Asm->createFixup(FixupKind, Reloc);
(Asm->*(Emitter.GPRImm))(Ty, VarReg, AssemblerImmediate(Fixup));
} else {
@@ -653,7 +651,7 @@
const auto FixupKind = (Reloc->getName().hasStdString() &&
Reloc->getName().toString() == GlobalOffsetTable)
? Traits::FK_GotPC
- : Traits::TargetLowering::getAbsFixup();
+ : Traits::FK_Abs;
AssemblerFixup *Fixup = Asm->createFixup(FixupKind, Reloc);
(Asm->*(Emitter.AddrImm))(Ty, Addr, AssemblerImmediate(Fixup));
} else {
@@ -666,13 +664,12 @@
auto *Target = InstX86Base::getTarget(Func);
if (const auto *Op0Var = llvm::dyn_cast<Variable>(Op0)) {
assert(!Op0Var->hasReg());
- AsmAddress StackAddr(Target->stackVarToAsmAddress(Op0Var, Target));
+ AsmAddress StackAddr(AsmAddress(Op0Var, Target));
emitIASAddrOpTyGPR(Func, Ty, StackAddr, Op1, Emitter);
} else if (const auto *Op0Mem = llvm::dyn_cast<X86OperandMem>(Op0)) {
Assembler *Asm = Func->getAssembler<Assembler>();
Op0Mem->emitSegmentOverride(Asm);
- emitIASAddrOpTyGPR(Func, Ty, Op0Mem->toAsmAddress(Op0Mem, Asm, Target), Op1,
- Emitter);
+ emitIASAddrOpTyGPR(Func, Ty, AsmAddress(Op0Mem, Asm, Target), Op1, Emitter);
} else {
llvm_unreachable("Unexpected operand type");
}
@@ -734,12 +731,12 @@
XmmRegister SrcReg = Traits::getEncodedXmm(SrcVar->getRegNum());
(Asm->*(Emitter.XmmXmm))(Ty, VarReg, SrcReg);
} else {
- AsmAddress SrcStackAddr = Target->stackVarToAsmAddress(SrcVar, Target);
+ AsmAddress SrcStackAddr = AsmAddress(SrcVar, Target);
(Asm->*(Emitter.XmmAddr))(Ty, VarReg, SrcStackAddr);
}
} else if (const auto *Mem = llvm::dyn_cast<X86OperandMem>(Src)) {
assert(Mem->getSegmentRegister() == X86OperandMem::DefaultSegment);
- (Asm->*(Emitter.XmmAddr))(Ty, VarReg, Mem->toAsmAddress(Mem, Asm, Target));
+ (Asm->*(Emitter.XmmAddr))(Ty, VarReg, AsmAddress(Mem, Asm, Target));
} else if (const auto *Imm = llvm::dyn_cast<ConstantInteger32>(Src)) {
(Asm->*(Emitter.XmmImm))(Ty, VarReg, AssemblerImmediate(Imm->getValue()));
} else {
@@ -758,14 +755,14 @@
XmmRegister SrcReg = Traits::getEncodedXmm(SrcVar->getRegNum());
(Asm->*(Emitter.XmmXmm))(Ty, VarReg, SrcReg);
} else {
- AsmAddress SrcStackAddr = Target->stackVarToAsmAddress(SrcVar, Target);
+ AsmAddress SrcStackAddr = AsmAddress(SrcVar, Target);
(Asm->*(Emitter.XmmAddr))(Ty, VarReg, SrcStackAddr);
}
} else if (const auto *Mem = llvm::dyn_cast<X86OperandMem>(Src)) {
assert(Mem->getSegmentRegister() == X86OperandMem::DefaultSegment);
- (Asm->*(Emitter.XmmAddr))(Ty, VarReg, Mem->toAsmAddress(Mem, Asm, Target));
+ (Asm->*(Emitter.XmmAddr))(Ty, VarReg, AsmAddress(Mem, Asm, Target));
} else if (const auto *Imm = llvm::dyn_cast<Constant>(Src)) {
- (Asm->*(Emitter.XmmAddr))(Ty, VarReg, AsmAddress::ofConstPool(Asm, Imm));
+ (Asm->*(Emitter.XmmAddr))(Ty, VarReg, AsmAddress(Imm, Asm));
} else {
llvm_unreachable("Unexpected operand type");
}
@@ -785,13 +782,13 @@
SReg_t SrcReg = srcEnc(SrcVar->getRegNum());
(Asm->*(Emitter.RegReg))(DestTy, DestReg, SrcTy, SrcReg);
} else {
- AsmAddress SrcStackAddr = Target->stackVarToAsmAddress(SrcVar, Target);
+ AsmAddress SrcStackAddr = AsmAddress(SrcVar, Target);
(Asm->*(Emitter.RegAddr))(DestTy, DestReg, SrcTy, SrcStackAddr);
}
} else if (const auto *Mem = llvm::dyn_cast<X86OperandMem>(Src)) {
Mem->emitSegmentOverride(Asm);
(Asm->*(Emitter.RegAddr))(DestTy, DestReg, SrcTy,
- Mem->toAsmAddress(Mem, Asm, Target));
+ AsmAddress(Mem, Asm, Target));
} else {
llvm_unreachable("Unexpected operand type");
}
@@ -814,13 +811,13 @@
SReg_t SrcReg = srcEnc(SrcVar->getRegNum());
(Asm->*(Emitter.RegRegImm))(DispatchTy, DestReg, SrcReg, Imm);
} else {
- AsmAddress SrcStackAddr = Target->stackVarToAsmAddress(SrcVar, Target);
+ AsmAddress SrcStackAddr = AsmAddress(SrcVar, Target);
(Asm->*(Emitter.RegAddrImm))(DispatchTy, DestReg, SrcStackAddr, Imm);
}
} else if (const auto *Mem = llvm::dyn_cast<X86OperandMem>(Src0)) {
Mem->emitSegmentOverride(Asm);
(Asm->*(Emitter.RegAddrImm))(DispatchTy, DestReg,
- Mem->toAsmAddress(Mem, Asm, Target), Imm);
+ AsmAddress(Mem, Asm, Target), Imm);
} else {
llvm_unreachable("Unexpected operand type");
}
@@ -837,18 +834,17 @@
(Asm->*(Emitter.XmmXmm))(DestReg,
Traits::getEncodedXmm(SrcVar->getRegNum()));
} else {
- AsmAddress StackAddr(Target->stackVarToAsmAddress(SrcVar, Target));
+ AsmAddress StackAddr(AsmAddress(SrcVar, Target));
(Asm->*(Emitter.XmmAddr))(DestReg, StackAddr);
}
} else if (const auto *SrcMem = llvm::dyn_cast<X86OperandMem>(Src)) {
assert(SrcMem->getSegmentRegister() == X86OperandMem::DefaultSegment);
- (Asm->*(Emitter.XmmAddr))(DestReg,
- SrcMem->toAsmAddress(SrcMem, Asm, Target));
+ (Asm->*(Emitter.XmmAddr))(DestReg, AsmAddress(SrcMem, Asm, Target));
} else {
llvm_unreachable("Unexpected operand type");
}
} else {
- AsmAddress StackAddr(Target->stackVarToAsmAddress(Dest, Target));
+ AsmAddress StackAddr(AsmAddress(Dest, Target));
// Src must be a register in this case.
const auto *SrcVar = llvm::cast<Variable>(Src);
assert(SrcVar->hasReg());
@@ -1056,8 +1052,7 @@
assert(Var == this->getSrc(0));
static const GPREmitterRegOp Emitter = {&Assembler::imul, &Assembler::imul,
&Assembler::imul};
- constexpr bool NotLea = false;
- emitIASRegOpTyGPR(Func, NotLea, Ty, Var, Src, Emitter);
+ emitIASRegOpTyGPR(Func, Ty, Var, Src, Emitter);
}
}
@@ -1323,13 +1318,13 @@
} else {
Asm->cmov(SrcTy, Condition,
Traits::getEncodedGPR(this->getDest()->getRegNum()),
- Target->stackVarToAsmAddress(SrcVar, Target));
+ AsmAddress(SrcVar, Target));
}
} else if (const auto *Mem = llvm::dyn_cast<X86OperandMem>(Src)) {
assert(Mem->getSegmentRegister() == X86OperandMem::DefaultSegment);
Asm->cmov(SrcTy, Condition,
Traits::getEncodedGPR(this->getDest()->getRegNum()),
- Mem->toAsmAddress(Mem, Asm, Target));
+ AsmAddress(Mem, Asm, Target));
} else {
llvm_unreachable("Unexpected operand type");
}
@@ -1376,7 +1371,7 @@
Traits::getEncodedXmm(this->getDest()->getRegNum()),
Traits::getEncodedXmm(SrcVar->getRegNum()), Condition);
} else {
- AsmAddress SrcStackAddr = Target->stackVarToAsmAddress(SrcVar, Target);
+ AsmAddress SrcStackAddr = AsmAddress(SrcVar, Target);
Asm->cmpps(this->getDest()->getType(),
Traits::getEncodedXmm(this->getDest()->getRegNum()),
SrcStackAddr, Condition);
@@ -1419,7 +1414,7 @@
auto *Target = InstX86Base::getTarget(Func);
const auto Mem = llvm::cast<X86OperandMem>(this->getSrc(0));
assert(Mem->getSegmentRegister() == X86OperandMem::DefaultSegment);
- const AsmAddress Addr = Mem->toAsmAddress(Mem, Asm, Target);
+ const AsmAddress Addr = AsmAddress(Mem, Asm, Target);
const auto *VarReg = llvm::cast<Variable>(this->getSrc(2));
assert(VarReg->hasReg());
const GPRRegister Reg = Traits::getEncodedGPR(VarReg->getRegNum());
@@ -1457,7 +1452,7 @@
const auto Mem = llvm::cast<X86OperandMem>(this->getSrc(0));
assert(Mem->getSegmentRegister() == X86OperandMem::DefaultSegment);
auto *Target = InstX86Base::getTarget(Func);
- const AsmAddress Addr = Mem->toAsmAddress(Mem, Asm, Target);
+ const AsmAddress Addr = AsmAddress(Mem, Asm, Target);
Asm->cmpxchg8b(Addr, this->Locked);
}
@@ -1627,8 +1622,7 @@
&Assembler::cmp};
if (const auto *SrcVar0 = llvm::dyn_cast<Variable>(Src0)) {
if (SrcVar0->hasReg()) {
- constexpr bool NotLea = false;
- emitIASRegOpTyGPR(Func, NotLea, Ty, SrcVar0, Src1, RegEmitter);
+ emitIASRegOpTyGPR(Func, Ty, SrcVar0, Src1, RegEmitter);
return;
}
}
@@ -1743,8 +1737,7 @@
&Assembler::test};
if (const auto *SrcVar0 = llvm::dyn_cast<Variable>(Src0)) {
if (SrcVar0->hasReg()) {
- constexpr bool NotLea = false;
- emitIASRegOpTyGPR(Func, NotLea, Ty, SrcVar0, Src1, RegEmitter);
+ emitIASRegOpTyGPR(Func, Ty, SrcVar0, Src1, RegEmitter);
return;
}
}
@@ -1809,12 +1802,12 @@
auto *Target = InstX86Base::getTarget(Func);
if (const auto *DestVar = llvm::dyn_cast<Variable>(Dest)) {
assert(!DestVar->hasReg());
- AsmAddress StackAddr(Target->stackVarToAsmAddress(DestVar, Target));
+ AsmAddress StackAddr(AsmAddress(DestVar, Target));
Asm->movss(DestTy, StackAddr, SrcReg);
} else {
const auto DestMem = llvm::cast<X86OperandMem>(Dest);
assert(DestMem->getSegmentRegister() == X86OperandMem::DefaultSegment);
- Asm->movss(DestTy, DestMem->toAsmAddress(DestMem, Asm, Target), SrcReg);
+ Asm->movss(DestTy, AsmAddress(DestMem, Asm, Target), SrcReg);
}
return;
} else {
@@ -1856,7 +1849,7 @@
assert(DestMem->getSegmentRegister() == X86OperandMem::DefaultSegment);
assert(SrcVar->hasReg());
auto *Target = InstX86Base::getTarget(Func);
- Asm->movups(DestMem->toAsmAddress(DestMem, Asm, Target),
+ Asm->movups(AsmAddress(DestMem, Asm, Target),
Traits::getEncodedXmm(SrcVar->getRegNum()));
}
@@ -1893,7 +1886,7 @@
assert(DestMem->getSegmentRegister() == X86OperandMem::DefaultSegment);
assert(SrcVar->hasReg());
auto *Target = InstX86Base::getTarget(Func);
- Asm->movq(DestMem->toAsmAddress(DestMem, Asm, Target),
+ Asm->movq(AsmAddress(DestMem, Asm, Target),
Traits::getEncodedXmm(SrcVar->getRegNum()));
}
@@ -1930,7 +1923,7 @@
assert(DestMem->getSegmentRegister() == X86OperandMem::DefaultSegment);
assert(SrcVar->hasReg());
auto *Target = InstX86Base::getTarget(Func);
- Asm->movd(SrcVar->getType(), DestMem->toAsmAddress(DestMem, Asm, Target),
+ Asm->movd(SrcVar->getType(), AsmAddress(DestMem, Asm, Target),
Traits::getEncodedXmm(SrcVar->getRegNum()));
}
@@ -1977,14 +1970,13 @@
const Variable *Var = this->getDest();
Type Ty = Var->getType();
const Operand *Src = this->getSrc(0);
- bool IsLea = true;
if (auto *Add = this->deoptToAddOrNull(Func)) {
Add->emitIAS(Func);
return;
}
- emitIASRegOpTyGPR(Func, IsLea, Ty, Var, Src, Emitter);
+ emitIASRegOpTyGPR(Func, Ty, Var, Src, Emitter);
}
Inst *InstX86Lea::deoptToAddOrNull(const Cfg *Func) const {
@@ -2089,14 +2081,13 @@
if (isScalarIntegerType(SrcTy)) {
SrcTy = DestTy;
}
- constexpr bool NotLea = false;
- emitIASRegOpTyGPR(Func, NotLea, DestTy, Dest, Src, GPRRegEmitter);
+ emitIASRegOpTyGPR(Func, DestTy, Dest, Src, GPRRegEmitter);
return;
}
} else {
// Dest must be Stack and Src *could* be a register. Use Src's type to
// decide on the emitters.
- AsmAddress StackAddr(Target->stackVarToAsmAddress(Dest, Target));
+ AsmAddress StackAddr(AsmAddress(Dest, Target));
if (isScalarFloatingType(SrcTy)) {
// Src must be a register.
const auto *SrcVar = llvm::cast<Variable>(Src);
@@ -2162,7 +2153,7 @@
Asm->movd(SrcVar->getType(), DestReg,
Traits::getEncodedGPR(SrcVar->getRegNum()));
} else {
- AsmAddress StackAddr(Target->stackVarToAsmAddress(SrcVar, Target));
+ AsmAddress StackAddr(AsmAddress(SrcVar, Target));
Asm->movd(SrcVar->getType(), DestReg, StackAddr);
}
} else {
@@ -2177,7 +2168,7 @@
Asm->movd(Dest->getType(), Traits::getEncodedGPR(Dest->getRegNum()),
SrcReg);
} else {
- AsmAddress StackAddr(Target->stackVarToAsmAddress(Dest, Target));
+ AsmAddress StackAddr(AsmAddress(Dest, Target));
Asm->movd(Dest->getType(), StackAddr, SrcReg);
}
}
@@ -2185,7 +2176,7 @@
assert(Dest->hasReg());
XmmRegister DestReg = Traits::getEncodedXmm(Dest->getRegNum());
auto *Mem = llvm::cast<X86OperandMem>(this->getSrc(0));
- Asm->movd(Mem->getType(), DestReg, Mem->toAsmAddress(Mem, Asm, Target));
+ Asm->movd(Mem->getType(), DestReg, AsmAddress(Mem, Asm, Target));
}
}
@@ -2264,8 +2255,7 @@
Type SrcTy = Src->getType();
assert(typeWidthInBytes(Dest->getType()) > 1);
assert(typeWidthInBytes(Dest->getType()) > typeWidthInBytes(SrcTy));
- constexpr bool NotLea = false;
- emitIASRegOpTyGPR<false, true>(Func, NotLea, SrcTy, Dest, Src, this->Emitter);
+ emitIASRegOpTyGPR<false, true>(Func, SrcTy, Dest, Src, this->Emitter);
}
bool InstX86Movzx::mayBeElided(const Variable *Dest,
@@ -2329,8 +2319,7 @@
mayBeElided(Dest, Src)) {
return;
}
- constexpr bool NotLea = false;
- emitIASRegOpTyGPR<false, true>(Func, NotLea, SrcTy, Dest, Src, this->Emitter);
+ emitIASRegOpTyGPR<false, true>(Func, SrcTy, Dest, Src, this->Emitter);
}
void InstX86Nop::emit(const Cfg *Func) const {
@@ -2490,7 +2479,7 @@
Asm->popl(Traits::getEncodedGPR(this->getDest()->getRegNum()));
} else {
auto *Target = InstX86Base::getTarget(Func);
- Asm->popl(Target->stackVarToAsmAddress(this->getDest(), Target));
+ Asm->popl(AsmAddress(this->getDest(), Target));
}
}
@@ -2582,8 +2571,7 @@
Asm->setcc(Condition,
Traits::getEncodedByteReg(this->getDest()->getRegNum()));
else
- Asm->setcc(Condition,
- Target->stackVarToAsmAddress(this->getDest(), Target));
+ Asm->setcc(Condition, AsmAddress(this->getDest(), Target));
return;
}
@@ -2618,7 +2606,7 @@
const auto Mem = llvm::cast<X86OperandMem>(this->getSrc(0));
assert(Mem->getSegmentRegister() == X86OperandMem::DefaultSegment);
auto *Target = InstX86Base::getTarget(Func);
- const AsmAddress Addr = Mem->toAsmAddress(Mem, Asm, Target);
+ const AsmAddress Addr = AsmAddress(Mem, Asm, Target);
const auto *VarReg = llvm::cast<Variable>(this->getSrc(1));
assert(VarReg->hasReg());
const GPRRegister Reg = Traits::getEncodedGPR(VarReg->getRegNum());
@@ -2667,7 +2655,7 @@
const auto *Mem = llvm::cast<X86OperandMem>(this->getSrc(0));
assert(Mem->getSegmentRegister() == X86OperandMem::DefaultSegment);
auto *Target = InstX86Base::getTarget(Func);
- const AsmAddress Addr = Mem->toAsmAddress(Mem, Asm, Target);
+ const AsmAddress Addr = AsmAddress(Mem, Asm, Target);
Asm->xchg(Ty, Addr, Reg1);
}
@@ -2778,30 +2766,15 @@
}
}
-namespace {
-int32_t getRematerializableOffset(Variable *Var,
- const ::Ice::X8664::TargetX8664 *Target) {
- int32_t Disp = Var->getStackOffset();
- const auto RegNum = Var->getRegNum();
- if (RegNum == Target->getFrameReg()) {
- Disp += Target->getFrameFixedAllocaOffset();
- } else if (RegNum != Target->getStackReg()) {
- llvm::report_fatal_error("Unexpected rematerializable register type");
- }
- return Disp;
-}
-} // end of anonymous namespace
-
void TargetX8664Traits::X86OperandMem::emit(const Cfg *Func) const {
if (!BuildDefs::dump())
return;
- const auto *Target =
- static_cast<const ::Ice::X8664::TargetX8664 *>(Func->getTarget());
+ const auto *Target = Func->getTarget();
// If the base is rematerializable, we need to replace it with the correct
// physical register (stack or base pointer), and update the Offset.
int32_t Disp = 0;
if (getBase() && getBase()->isRematerializable()) {
- Disp += getRematerializableOffset(getBase(), Target);
+ Disp += getBase()->getRematerializableOffset(Target);
}
// The index should never be rematerializable. But if we ever allow it, then
// we should make sure the rematerialization offset is shifted by the Shift
@@ -2878,7 +2851,7 @@
const auto *Target =
static_cast<const ::Ice::X8664::TargetX8664 *>(Func->getTarget());
if (getBase() && getBase()->isRematerializable()) {
- Disp += getRematerializableOffset(getBase(), Target);
+ Disp += getBase()->getRematerializableOffset(Target);
}
if (Base) {
if (Func)
@@ -2928,59 +2901,5 @@
Str << "]";
}
-AsmAddress TargetX8664Traits::X86OperandMem::toAsmAddress(
- const X86OperandMem *Mem, TargetX8664Traits::Assembler *Asm,
- const Ice::TargetLowering *TargetLowering, bool IsLeaAddr) {
- (void)IsLeaAddr;
- const auto *Target =
- static_cast<const ::Ice::X8664::TargetX8664 *>(TargetLowering);
- int32_t Disp = 0;
- if (Mem->getBase() && Mem->getBase()->isRematerializable()) {
- Disp += getRematerializableOffset(Mem->getBase(), Target);
- }
- assert(!Mem->getIndex() || !Mem->getIndex()->isRematerializable());
-
- AssemblerFixup *Fixup = nullptr;
- // Determine the offset (is it relocatable?)
- if (Mem->getOffset() != nullptr) {
- if (const auto *CI = llvm::dyn_cast<ConstantInteger32>(Mem->getOffset())) {
- Disp += static_cast<int32_t>(CI->getValue());
- } else if (const auto *CR =
- llvm::dyn_cast<ConstantRelocatable>(Mem->getOffset())) {
- const auto FixupKind =
- (Mem->getBase() != nullptr || Mem->getIndex() != nullptr) ? FK_Abs
- : FK_PcRel;
- const RelocOffsetT DispAdjustment = FixupKind == FK_PcRel ? 4 : 0;
- Fixup = Asm->createFixup(FixupKind, CR);
- Fixup->set_addend(-DispAdjustment);
- Disp = CR->getOffset();
- } else {
- llvm_unreachable("Unexpected offset type");
- }
- }
-
- // Now convert to the various possible forms.
- if (Mem->getBase() && Mem->getIndex()) {
- return AsmAddress(getEncodedGPR(Mem->getBase()->getRegNum()),
- getEncodedGPR(Mem->getIndex()->getRegNum()),
- X8664::Traits::ScaleFactor(Mem->getShift()), Disp, Fixup);
- }
-
- if (Mem->getBase()) {
- return AsmAddress(getEncodedGPR(Mem->getBase()->getRegNum()), Disp, Fixup);
- }
-
- if (Mem->getIndex()) {
- return AsmAddress(getEncodedGPR(Mem->getIndex()->getRegNum()),
- X8664::Traits::ScaleFactor(Mem->getShift()), Disp, Fixup);
- }
-
- if (Fixup == nullptr) {
- return AsmAddress::Absolute(Disp);
- }
-
- return AsmAddress::RipRelative(Disp, Fixup);
-}
-
} // namespace X8664
} // end of namespace Ice
diff --git a/third_party/subzero/src/IceInstX8664.h b/third_party/subzero/src/IceInstX8664.h
index 5e29545..f0aa3fa 100644
--- a/third_party/subzero/src/IceInstX8664.h
+++ b/third_party/subzero/src/IceInstX8664.h
@@ -513,9 +513,8 @@
/// Emit a two-operand (GPR) instruction, where the dest operand is a Variable
/// that's guaranteed to be a register.
template <bool VarCanBeByte = true, bool SrcCanBeByte = true>
-void emitIASRegOpTyGPR(const Cfg *Func, bool IsLea, Type Ty,
- const Variable *Dst, const Operand *Src,
- const GPREmitterRegOp &Emitter);
+void emitIASRegOpTyGPR(const Cfg *Func, Type Ty, const Variable *Dst,
+ const Operand *Src, const GPREmitterRegOp &Emitter);
/// Instructions of the form x := op(x).
template <typename InstX86Base::InstKindX86 K>
@@ -597,8 +596,7 @@
const Variable *Var = this->getDest();
Type Ty = Var->getType();
const Operand *Src = this->getSrc(0);
- bool IsLea = false;
- emitIASRegOpTyGPR(Func, IsLea, Ty, Var, Src, Emitter);
+ emitIASRegOpTyGPR(Func, Ty, Var, Src, Emitter);
}
void dump(const Cfg *Func) const override {
if (!BuildDefs::dump())
@@ -729,10 +727,8 @@
void emitIAS(const Cfg *Func) const override {
Type Ty = this->getDest()->getType();
assert(this->getSrcSize() == 2);
- constexpr bool ThisIsLEA = K == InstX86Base::Lea;
- static_assert(!ThisIsLEA, "Lea should be a unaryop.");
- emitIASRegOpTyGPR(Func, !ThisIsLEA, Ty, this->getDest(), this->getSrc(1),
- Emitter);
+ static_assert(K != InstX86Base::Lea, "Lea should be a unaryop.");
+ emitIASRegOpTyGPR(Func, Ty, this->getDest(), this->getSrc(1), Emitter);
}
void dump(const Cfg *Func) const override {
if (!BuildDefs::dump())
@@ -2270,7 +2266,7 @@
Source1) {}
};
-/// Base class for a lockable x86-32 instruction (emits a locked prefix).
+/// Base class for a lockable x86-64 instruction (emits a locked prefix).
class InstX86BaseLockable : public InstX86Base {
InstX86BaseLockable() = delete;
InstX86BaseLockable(const InstX86BaseLockable &) = delete;
diff --git a/third_party/subzero/src/IceOperand.cpp b/third_party/subzero/src/IceOperand.cpp
index 1e98324..0758f7d 100644
--- a/third_party/subzero/src/IceOperand.cpp
+++ b/third_party/subzero/src/IceOperand.cpp
@@ -222,6 +222,17 @@
return Func->getVMetadata()->getUseWeight(this);
}
+int32_t
+Variable::getRematerializableOffset(const ::Ice::TargetLowering *Target) {
+ int32_t Disp = getStackOffset();
+ const auto RegNum = getRegNum();
+ if (RegNum == Target->getFrameReg()) {
+ Disp += Target->getFrameFixedAllocaOffset();
+ } else if (RegNum != Target->getStackReg()) {
+ llvm::report_fatal_error("Unexpected rematerializable register type");
+ }
+ return Disp;
+}
void VariableTracking::markUse(MetadataKind TrackingKind, const Inst *Instr,
CfgNode *Node, bool IsImplicit) {
(void)TrackingKind;
diff --git a/third_party/subzero/src/IceOperand.h b/third_party/subzero/src/IceOperand.h
index 9229656..36f845d 100644
--- a/third_party/subzero/src/IceOperand.h
+++ b/third_party/subzero/src/IceOperand.h
@@ -765,6 +765,7 @@
setMustHaveReg();
}
bool isRematerializable() const { return IsRematerializable; }
+ int32_t getRematerializableOffset(const ::Ice::TargetLowering *Target);
void setRegClass(uint8_t RC) { RegisterClass = static_cast<RegClass>(RC); }
RegClass getRegClass() const { return RegisterClass; }
diff --git a/third_party/subzero/src/IceTargetLoweringX8632.cpp b/third_party/subzero/src/IceTargetLoweringX8632.cpp
index abf47ae..3489fec 100644
--- a/third_party/subzero/src/IceTargetLoweringX8632.cpp
+++ b/third_party/subzero/src/IceTargetLoweringX8632.cpp
@@ -871,32 +871,6 @@
Str << "(%" << getRegName(BaseRegNum, FrameSPTy) << ")";
}
-AsmAddress TargetX8632::stackVarToAsmAddress(const Variable *Var,
- const TargetX8632 *Target) {
- if (Var->hasReg())
- llvm::report_fatal_error("Stack Variable has a register assigned");
- if (Var->mustHaveReg()) {
- llvm::report_fatal_error("Infinite-weight Variable (" + Var->getName() +
- ") has no register assigned - function " +
- Target->getFunc()->getFunctionName());
- }
- int32_t Offset = Var->getStackOffset();
- auto BaseRegNum = Var->getBaseRegNum();
- if (Var->getBaseRegNum().hasNoValue()) {
- // If the stack pointer needs alignment, we must use the frame pointer for
- // arguments. For locals, getFrameOrStackReg will return the stack pointer
- // in this case.
- if (Target->needsStackPointerAlignment() && Var->getIsArg()) {
- assert(Target->hasFramePointer());
- BaseRegNum = Target->getFrameReg();
- } else {
- BaseRegNum = Target->getFrameOrStackReg();
- }
- }
- return AsmAddress(Traits::getEncodedGPR(BaseRegNum), Offset,
- AssemblerFixup::NoFixup);
-}
-
void TargetX8632::addProlog(CfgNode *Node) {
// Stack frame layout:
//
diff --git a/third_party/subzero/src/IceTargetLoweringX8632.h b/third_party/subzero/src/IceTargetLoweringX8632.h
index 9976e1c..463ae2e 100644
--- a/third_party/subzero/src/IceTargetLoweringX8632.h
+++ b/third_party/subzero/src/IceTargetLoweringX8632.h
@@ -141,9 +141,6 @@
static bool shouldBePooled(const Constant *C);
static ::Ice::Type getPointerType();
- static FixupKind getPcRelFixup() { return PcRelFixup; }
- static FixupKind getAbsFixup() { return AbsFixup; }
-
void translateOm1() override;
void translateO2() override;
void doLoadOpt();
@@ -272,8 +269,6 @@
size_t BasicFrameOffset, size_t StackAdjBytes,
size_t &InArgsSizeBytes);
void addEpilog(CfgNode *Node) override;
- static AsmAddress stackVarToAsmAddress(const Variable *Var,
- const TargetX8632 *Target);
Operand *legalizeUndef(Operand *From, RegNumT RegNum = RegNumT());
diff --git a/third_party/subzero/src/IceTargetLoweringX8632Traits.h b/third_party/subzero/src/IceTargetLoweringX8632Traits.h
index a662331..4fa67b2 100644
--- a/third_party/subzero/src/IceTargetLoweringX8632Traits.h
+++ b/third_party/subzero/src/IceTargetLoweringX8632Traits.h
@@ -35,7 +35,6 @@
struct Insts;
class TargetX8632;
class AssemblerX8632;
-
class TargetX8632;
struct TargetX8632Traits {
@@ -68,6 +67,9 @@
static constexpr FixupKind FK_Gotoff = llvm::ELF::R_386_GOTOFF;
static constexpr FixupKind FK_GotPC = llvm::ELF::R_386_GOTPC;
+ class X86OperandMem;
+ class VariableSplit;
+
class AsmOperand {
public:
AsmOperand(const AsmOperand &other)
@@ -105,14 +107,6 @@
return static_cast<int8_t>(encoding_[length_ - 1]);
}
- int32_t disp32() const {
- assert(length_ >= 5);
- // TODO(stichnot): This method is not currently used. Delete it along
- // with other unused methods, or use a safe version of bitCopy().
- llvm::report_fatal_error("Unexpected call to disp32()");
- // return Utils::bitCopy<int32_t>(encoding_[length_ - 4]);
- }
-
AssemblerFixup *fixup() const { return fixup_; }
protected:
@@ -174,6 +168,23 @@
AsmAddress() = delete;
public:
+ AsmAddress(GPRRegister Base, int32_t Disp,
+ AssemblerFixup *Fixup = nullptr) {
+ SetBase(Base, Disp, Fixup);
+ }
+ AsmAddress(const Variable *Var, const TargetX8632 *Target);
+ AsmAddress(const X86OperandMem *Mem, Ice::Assembler *Asm,
+ const Ice::TargetLowering *Target);
+ AsmAddress(const VariableSplit *Split, const Cfg *Func);
+
+ // Address into the constant pool.
+ AsmAddress(const Constant *Imm, Ice::Assembler *Asm) {
+ AssemblerFixup *Fixup = Asm->createFixup(llvm::ELF::R_386_32, Imm);
+ const RelocOffsetT Offset = 0;
+ SetAbsolute(Offset, Fixup);
+ }
+
+ private:
AsmAddress(const AsmAddress &other) : AsmOperand(other) {}
AsmAddress &operator=(const AsmAddress &other) {
@@ -181,7 +192,7 @@
return *this;
}
- AsmAddress(GPRRegister Base, int32_t Disp, AssemblerFixup *Fixup) {
+ void SetBase(GPRRegister Base, int32_t Disp, AssemblerFixup *Fixup) {
if (Fixup == nullptr && Disp == 0 && Base != RegX8632::Encoded_Reg_ebp) {
SetModRM(0, Base);
if (Base == RegX8632::Encoded_Reg_esp)
@@ -201,8 +212,8 @@
}
}
- AsmAddress(GPRRegister Index, ScaleFactor Scale, int32_t Disp,
- AssemblerFixup *Fixup) {
+ void SetIndex(GPRRegister Index, ScaleFactor Scale, int32_t Disp,
+ AssemblerFixup *Fixup) {
assert(Index != RegX8632::Encoded_Reg_esp); // Illegal addressing mode.
SetModRM(0, RegX8632::Encoded_Reg_esp);
SetSIB(Scale, Index, RegX8632::Encoded_Reg_ebp);
@@ -211,8 +222,8 @@
SetFixup(Fixup);
}
- AsmAddress(GPRRegister Base, GPRRegister Index, ScaleFactor Scale,
- int32_t Disp, AssemblerFixup *Fixup) {
+ void SetBaseIndex(GPRRegister Base, GPRRegister Index, ScaleFactor Scale,
+ int32_t Disp, AssemblerFixup *Fixup) {
assert(Index != RegX8632::Encoded_Reg_esp); // Illegal addressing mode.
if (Fixup == nullptr && Disp == 0 && Base != RegX8632::Encoded_Reg_ebp) {
SetModRM(0, RegX8632::Encoded_Reg_esp);
@@ -231,7 +242,7 @@
}
/// Generate an absolute address expression on x86-32.
- AsmAddress(RelocOffsetT Offset, AssemblerFixup *Fixup) {
+ void SetAbsolute(RelocOffsetT Offset, AssemblerFixup *Fixup) {
SetModRM(0, RegX8632::Encoded_Reg_ebp);
// Use the Offset in the displacement for now. If we decide to process
// fixups later, we'll need to patch up the emitted displacement.
@@ -239,12 +250,6 @@
if (Fixup)
SetFixup(Fixup);
}
-
- static AsmAddress ofConstPool(Assembler *Asm, const Constant *Imm) {
- AssemblerFixup *Fixup = Asm->createFixup(llvm::ELF::R_386_32, Imm);
- const RelocOffsetT Offset = 0;
- return AsmAddress(Offset, Fixup);
- }
};
//----------------------------------------------------------------------------
@@ -785,9 +790,17 @@
SegmentRegisters getSegmentRegister() const { return SegmentReg; }
void emitSegmentOverride(Assembler *Asm) const;
bool getIsRebased() const { return IsRebased; }
- static AsmAddress toAsmAddress(const X86OperandMem *Mem, Assembler *Asm,
- const Ice::TargetLowering *Target,
- bool LeaAddr = false);
+
+ void validateMemOperandPIC() const {
+ if (!BuildDefs::asserts())
+ return;
+ const bool HasCR =
+ getOffset() && llvm::isa<ConstantRelocatable>(getOffset());
+ (void)HasCR;
+ const bool IsRebased = getIsRebased();
+ (void)IsRebased;
+ assert(!IsRebased);
+ }
void emit(const Cfg *Func) const override;
using X86Operand::dump;
@@ -831,7 +844,6 @@
const Variable *getVar() const { return Var; }
int32_t getOffset() const { return Part == High ? 4 : 0; }
- static AsmAddress toAsmAddress(const VariableSplit *Split, const Cfg *Func);
void emit(const Cfg *Func) const override;
using X86Operand::dump;
void dump(const Cfg *Func, Ostream &Str) const override;
diff --git a/third_party/subzero/src/IceTargetLoweringX8664.cpp b/third_party/subzero/src/IceTargetLoweringX8664.cpp
index 07c9fa4..c411d12 100644
--- a/third_party/subzero/src/IceTargetLoweringX8664.cpp
+++ b/third_party/subzero/src/IceTargetLoweringX8664.cpp
@@ -885,32 +885,6 @@
Str << "(%" << getRegName(BaseRegNum, FrameSPTy) << ")";
}
-AsmAddress TargetX8664::stackVarToAsmAddress(const Variable *Var,
- const TargetX8664 *Target) {
- if (Var->hasReg())
- llvm::report_fatal_error("Stack Variable has a register assigned");
- if (Var->mustHaveReg()) {
- llvm::report_fatal_error("Infinite-weight Variable (" + Var->getName() +
- ") has no register assigned - function " +
- Target->getFunc()->getFunctionName());
- }
- int32_t Offset = Var->getStackOffset();
- auto BaseRegNum = Var->getBaseRegNum();
- if (Var->getBaseRegNum().hasNoValue()) {
- // If the stack pointer needs alignment, we must use the frame pointer for
- // arguments. For locals, getFrameOrStackReg will return the stack pointer
- // in this case.
- if (Target->needsStackPointerAlignment() && Var->getIsArg()) {
- assert(Target->hasFramePointer());
- BaseRegNum = Target->getFrameReg();
- } else {
- BaseRegNum = Target->getFrameOrStackReg();
- }
- }
- return AsmAddress(Traits::getEncodedGPR(BaseRegNum), Offset,
- AssemblerFixup::NoFixup);
-}
-
void TargetX8664::addProlog(CfgNode *Node) {
// Stack frame layout:
//
diff --git a/third_party/subzero/src/IceTargetLoweringX8664.h b/third_party/subzero/src/IceTargetLoweringX8664.h
index 9ea7bfb..e84d29d 100644
--- a/third_party/subzero/src/IceTargetLoweringX8664.h
+++ b/third_party/subzero/src/IceTargetLoweringX8664.h
@@ -142,9 +142,6 @@
static bool shouldBePooled(const Constant *C);
static ::Ice::Type getPointerType();
- static FixupKind getPcRelFixup() { return PcRelFixup; }
- static FixupKind getAbsFixup() { return AbsFixup; }
-
void translateOm1() override;
void translateO2() override;
void doLoadOpt();
@@ -268,8 +265,6 @@
size_t BasicFrameOffset, size_t StackAdjBytes,
size_t &InArgsSizeBytes);
void addEpilog(CfgNode *Node) override;
- static AsmAddress stackVarToAsmAddress(const Variable *Var,
- const TargetX8664 *Target);
Operand *legalizeUndef(Operand *From, RegNumT RegNum = RegNumT());
diff --git a/third_party/subzero/src/IceTargetLoweringX8664Traits.h b/third_party/subzero/src/IceTargetLoweringX8664Traits.h
index eba550f..bba2281 100644
--- a/third_party/subzero/src/IceTargetLoweringX8664Traits.h
+++ b/third_party/subzero/src/IceTargetLoweringX8664Traits.h
@@ -36,7 +36,6 @@
class AssemblerX8664;
struct Insts;
class TargetX8664;
-
class TargetX8664;
struct TargetX8664Traits {
@@ -68,6 +67,8 @@
static constexpr FixupKind FK_Gotoff = llvm::ELF::R_X86_64_GOTOFF64;
static constexpr FixupKind FK_GotPC = llvm::ELF::R_X86_64_GOTPC32;
+ class X86OperandMem;
+
class AsmOperand {
public:
enum RexBits {
@@ -180,12 +181,25 @@
AsmAddress() = default;
public:
+ AsmAddress(const Variable *Var, const TargetX8664 *Target);
+ AsmAddress(const X86OperandMem *Mem, Ice::Assembler *Asm,
+ const Ice::TargetLowering *Target);
+
+ // Address into the constant pool.
+ AsmAddress(const Constant *Imm, Ice::Assembler *Asm) {
+ // TODO(jpp): ???
+ AssemblerFixup *Fixup = Asm->createFixup(FK_Abs, Imm);
+ const RelocOffsetT Offset = 4;
+ SetRipRelative(Offset, Fixup);
+ }
+
+ private:
AsmAddress(const AsmAddress &) = default;
AsmAddress(AsmAddress &&) = default;
AsmAddress &operator=(const AsmAddress &) = default;
AsmAddress &operator=(AsmAddress &&) = default;
- AsmAddress(GPRRegister Base, int32_t Disp, AssemblerFixup *Fixup) {
+ void SetBase(GPRRegister Base, int32_t Disp, AssemblerFixup *Fixup) {
if (Fixup == nullptr && Disp == 0 &&
(Base & 7) != RegX8664::Encoded_Reg_rbp) {
SetModRM(0, Base);
@@ -206,8 +220,8 @@
}
}
- AsmAddress(GPRRegister Index, ScaleFactor Scale, int32_t Disp,
- AssemblerFixup *Fixup) {
+ void SetIndex(GPRRegister Index, ScaleFactor Scale, int32_t Disp,
+ AssemblerFixup *Fixup) {
assert(Index != RegX8664::Encoded_Reg_rsp); // Illegal addressing mode.
SetModRM(0, RegX8664::Encoded_Reg_rsp);
SetSIB(Scale, Index, RegX8664::Encoded_Reg_rbp);
@@ -216,8 +230,8 @@
SetFixup(Fixup);
}
- AsmAddress(GPRRegister Base, GPRRegister Index, ScaleFactor Scale,
- int32_t Disp, AssemblerFixup *Fixup) {
+ void SetBaseIndex(GPRRegister Base, GPRRegister Index, ScaleFactor Scale,
+ int32_t Disp, AssemblerFixup *Fixup) {
assert(Index != RegX8664::Encoded_Reg_rsp); // Illegal addressing mode.
if (Fixup == nullptr && Disp == 0 &&
(Base & 7) != RegX8664::Encoded_Reg_rbp) {
@@ -237,37 +251,25 @@
}
/// Generate a RIP-relative address expression on x86-64.
- static AsmAddress RipRelative(RelocOffsetT Offset, AssemblerFixup *Fixup) {
+ void SetRipRelative(RelocOffsetT Offset, AssemblerFixup *Fixup) {
assert(Fixup != nullptr);
assert(Fixup->kind() == FK_PcRel);
- AsmAddress NewAddress;
- NewAddress.SetModRM(0x0, RegX8664::Encoded_Reg_rbp);
+
+ SetModRM(0x0, RegX8664::Encoded_Reg_rbp);
// Use the Offset in the displacement for now. If we decide to process
// fixups later, we'll need to patch up the emitted displacement.
- NewAddress.SetDisp32(Offset);
+ SetDisp32(Offset);
if (Fixup)
- NewAddress.SetFixup(Fixup);
-
- return NewAddress;
+ SetFixup(Fixup);
}
/// Generate an absolute address.
- static AsmAddress Absolute(RelocOffsetT Addr) {
- AsmAddress NewAddress;
- NewAddress.SetModRM(0x0, RegX8664::Encoded_Reg_rsp);
+ void SetAbsolute(RelocOffsetT Addr) {
+ SetModRM(0x0, RegX8664::Encoded_Reg_rsp);
static constexpr ScaleFactor NoScale = TIMES_1;
- NewAddress.SetSIB(NoScale, RegX8664::Encoded_Reg_rsp,
- RegX8664::Encoded_Reg_rbp);
- NewAddress.SetDisp32(Addr);
- return NewAddress;
- }
-
- static AsmAddress ofConstPool(Assembler *Asm, const Constant *Imm) {
- // TODO(jpp): ???
- AssemblerFixup *Fixup = Asm->createFixup(FK_Abs, Imm);
- const RelocOffsetT Offset = 4;
- return AsmAddress::RipRelative(Offset, Fixup);
+ SetSIB(NoScale, RegX8664::Encoded_Reg_rsp, RegX8664::Encoded_Reg_rbp);
+ SetDisp32(Addr);
}
};
@@ -866,9 +868,6 @@
SegmentRegisters getSegmentRegister() const { return DefaultSegment; }
void emitSegmentOverride(Assembler *) const {}
bool getIsRebased() const { return IsRebased; }
- static AsmAddress toAsmAddress(const X86OperandMem *Mem, Assembler *Asm,
- const Ice::TargetLowering *Target,
- bool IsLeaAddr = false);
void emit(const Cfg *Func) const override;
using X86Operand::dump;
