Use more inclusive terms
third_party/subzero is a fork which we are responsible for. Many of the
non-PC words were in files we actually have no use for, so they've been
removed altogether.
Bug: b/162338339
Bug: chromium:1097202
Change-Id: Iaa531dd8788efaf25a640786b78d15d4648b2dd9
Reviewed-on: https://swiftshader-review.googlesource.com/c/SwiftShader/+/47208
Reviewed-by: Alexis Hétu <sugoi@google.com>
Kokoro-Result: kokoro <noreply+kokoro@google.com>
Tested-by: Nicolas Capens <nicolascapens@google.com>
diff --git a/src/Device/BC_Decoder.cpp b/src/Device/BC_Decoder.cpp
index 7a7b969..3a0c220 100644
--- a/src/Device/BC_Decoder.cpp
+++ b/src/Device/BC_Decoder.cpp
@@ -944,7 +944,7 @@
int partition = 0;
ModeDesc modeDesc;
- // For sanity checks
+ // For assertion checks
modeDesc.number = -1;
for(auto desc : blockDescs[mode])
{
@@ -952,7 +952,6 @@
{
case Mode:
modeDesc = desc.modeDesc;
- // Sanity check
ASSERT(modeDesc.number == mode);
e[0].size[0] = e[0].size[1] = e[0].size[2] = modeDesc.endpointBits;
@@ -1146,18 +1145,18 @@
/**/ { -1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x00, 0x0 },
};
-static_assert(Modes[0].NumColors() == 6, "BC7 sanity checks failed");
-static_assert(Modes[0].Partition() == Bitfield{ 1, 4 }, "BC7 sanity checks failed");
-static_assert(Modes[0].Red(0) == Bitfield{ 5, 4 }, "BC7 sanity checks failed");
-static_assert(Modes[0].Red(5) == Bitfield{ 25, 4 }, "BC7 sanity checks failed");
-static_assert(Modes[0].Green(0) == Bitfield{ 29, 4 }, "BC7 sanity checks failed");
-static_assert(Modes[0].Green(5) == Bitfield{ 49, 4 }, "BC7 sanity checks failed");
-static_assert(Modes[0].Blue(0) == Bitfield{ 53, 4 }, "BC7 sanity checks failed");
-static_assert(Modes[0].Blue(5) == Bitfield{ 73, 4 }, "BC7 sanity checks failed");
-static_assert(Modes[0].EndpointPBit(0) == Bitfield{ 77, 1 }, "BC7 sanity checks failed");
-static_assert(Modes[0].EndpointPBit(5) == Bitfield{ 82, 1 }, "BC7 sanity checks failed");
-static_assert(Modes[0].PrimaryIndex(0, 2) == Bitfield{ 83, 2 }, "BC7 sanity checks failed");
-static_assert(Modes[0].PrimaryIndex(43, 1) == Bitfield{ 126, 1 }, "BC7 sanity checks failed");
+static_assert(Modes[0].NumColors() == 6, "BC7 static assertion failed");
+static_assert(Modes[0].Partition() == Bitfield{ 1, 4 }, "BC7 static assertion failed");
+static_assert(Modes[0].Red(0) == Bitfield{ 5, 4 }, "BC7 static assertion failed");
+static_assert(Modes[0].Red(5) == Bitfield{ 25, 4 }, "BC7 static assertion failed");
+static_assert(Modes[0].Green(0) == Bitfield{ 29, 4 }, "BC7 static assertion failed");
+static_assert(Modes[0].Green(5) == Bitfield{ 49, 4 }, "BC7 static assertion failed");
+static_assert(Modes[0].Blue(0) == Bitfield{ 53, 4 }, "BC7 static assertion failed");
+static_assert(Modes[0].Blue(5) == Bitfield{ 73, 4 }, "BC7 static assertion failed");
+static_assert(Modes[0].EndpointPBit(0) == Bitfield{ 77, 1 }, "BC7 static assertion failed");
+static_assert(Modes[0].EndpointPBit(5) == Bitfield{ 82, 1 }, "BC7 static assertion failed");
+static_assert(Modes[0].PrimaryIndex(0, 2) == Bitfield{ 83, 2 }, "BC7 static asassertionsert failed");
+static_assert(Modes[0].PrimaryIndex(43, 1) == Bitfield{ 126, 1 }, "BC7 static assertion failed");
static constexpr int MaxPartitions = 64;
static constexpr int MaxSubsets = 3;
diff --git a/src/Device/ETC_Decoder.cpp b/src/Device/ETC_Decoder.cpp
index 0f8ecaa..a5c8549 100644
--- a/src/Device/ETC_Decoder.cpp
+++ b/src/Device/ETC_Decoder.cpp
@@ -221,9 +221,9 @@
{
// Byte 1
unsigned char TR1b : 2;
- unsigned char TdummyB : 1;
+ unsigned char TunusedB : 1;
unsigned char TR1a : 2;
- unsigned char TdummyA : 3;
+ unsigned char TunusedA : 3;
// Byte 2
unsigned char TB1 : 4;
@@ -246,14 +246,14 @@
// Byte 1
unsigned char HG1a : 3;
unsigned char HR1 : 4;
- unsigned char HdummyA : 1;
+ unsigned char HunusedA : 1;
// Byte 2
unsigned char HB1b : 2;
- unsigned char HdummyC : 1;
+ unsigned char HunusedC : 1;
unsigned char HB1a : 1;
unsigned char HG1b : 1;
- unsigned char HdummyB : 3;
+ unsigned char HunusedB : 3;
// Byte 3
unsigned char HG2a : 3;
@@ -279,18 +279,18 @@
// Byte 1
unsigned char GO1 : 1;
unsigned char RO : 6;
- unsigned char PdummyA : 1;
+ unsigned char PunusedA : 1;
// Byte 2
unsigned char BO1 : 1;
unsigned char GO2 : 6;
- unsigned char PdummyB : 1;
+ unsigned char PunusedB : 1;
// Byte 3
unsigned char BO3a : 2;
- unsigned char PdummyD : 1;
+ unsigned char PunusedD : 1;
unsigned char BO2 : 2;
- unsigned char PdummyC : 3;
+ unsigned char PunusedC : 3;
// Byte 4
unsigned char RH2 : 1;
diff --git a/src/Pipeline/SpirvShader.hpp b/src/Pipeline/SpirvShader.hpp
index 8a88646..07127aa 100644
--- a/src/Pipeline/SpirvShader.hpp
+++ b/src/Pipeline/SpirvShader.hpp
@@ -439,7 +439,7 @@
};
struct TypeOrObject
- {}; // Dummy struct to represent a Type or Object.
+ {};
// TypeOrObjectID is an identifier that represents a Type or an Object,
// and supports implicit casting to and from Type::ID or Object::ID.
diff --git a/src/System/Build.cpp b/src/System/Build.cpp
index 5552ae5..002bbeb 100644
--- a/src/System/Build.cpp
+++ b/src/System/Build.cpp
@@ -24,7 +24,7 @@
# error "Unable to identify C++ language version"
#endif
-// The template and dummy function below verifies the compiler is using at least
+// The template and unused function below verifies the compiler is using at least
// C++14. It will print an error message containing the actual C++ version if
// the version is < 14.
@@ -39,7 +39,7 @@
void check_cpp_version()
{
cpp<CPP_VERSION / 100>();
- (void)&check_cpp_version; // dummy reference to avoid unreferenced function warning.
+ (void)&check_cpp_version; // Unused reference to avoid unreferenced function warning.
}
} // namespace
diff --git a/src/System/SharedLibrary.hpp b/src/System/SharedLibrary.hpp
index e3b1e16..fc12842 100644
--- a/src/System/SharedLibrary.hpp
+++ b/src/System/SharedLibrary.hpp
@@ -88,25 +88,6 @@
{
return (void *)GetProcAddress((HMODULE)library, name);
}
-
-inline std::string getModuleDirectory()
-{
- static int dummy_symbol = 0;
-
- HMODULE module = NULL;
- GetModuleHandleEx(GET_MODULE_HANDLE_EX_FLAG_FROM_ADDRESS, (LPCTSTR)&dummy_symbol, &module);
-
- char filename[1024];
- if(module && (GetModuleFileName(module, filename, sizeof(filename)) != 0))
- {
- std::string directory(filename);
- return directory.substr(0, directory.find_last_of("\\/") + 1).c_str();
- }
- else
- {
- return "";
- }
-}
#else
inline void *loadLibrary(const char *path)
{
@@ -150,22 +131,6 @@
return symbol;
}
-
-inline std::string getModuleDirectory()
-{
- static int dummy_symbol = 0;
-
- Dl_info dl_info;
- if(dladdr(&dummy_symbol, &dl_info) != 0)
- {
- std::string directory(dl_info.dli_fname);
- return directory.substr(0, directory.find_last_of("\\/") + 1).c_str();
- }
- else
- {
- return "";
- }
-}
#endif
#endif // SharedLibrary_hpp
diff --git a/src/Vulkan/VkStringify.cpp b/src/Vulkan/VkStringify.cpp
index 0d71f25..898583b 100644
--- a/src/Vulkan/VkStringify.cpp
+++ b/src/Vulkan/VkStringify.cpp
@@ -28,14 +28,6 @@
std::string Stringify(VkStructureType value)
{
#ifndef NDEBUG
- // Since C++ hasn't given us introspection on enums, we can't just "get" an
- // enum name from an enum value (at least not without some crazy header
- // file hacks). So I copied the entire list of VK_STRUCTURE_TYPE defined in
- // vulkan/vulkan_core.h.
- //
- // If vulkan_core.h is updated to include new structure types, and this list
- // becomes out of date, then this function will throw a warning if someone
- // tries to stringify that enum value.
static const std::map<VkStructureType, const char *> strings = {
# define INSERT_ELEMENT(p) std::make_pair(p, # p)
INSERT_ELEMENT(VK_STRUCTURE_TYPE_APPLICATION_INFO),
diff --git a/third_party/llvm-subzero/include/llvm/ADT/SmallVector.h b/third_party/llvm-subzero/include/llvm/ADT/SmallVector.h
index c1c5c81..ee9cd8b 100644
--- a/third_party/llvm-subzero/include/llvm/ADT/SmallVector.h
+++ b/third_party/llvm-subzero/include/llvm/ADT/SmallVector.h
@@ -61,8 +61,8 @@
};
/// This is the part of SmallVectorTemplateBase which does not depend on whether
-/// the type T is a POD. The extra dummy template argument is used by ArrayRef
-/// to avoid unnecessarily requiring T to be complete.
+/// the type T is a POD. The extra template argument is used by ArrayRef to
+/// avoid unnecessarily requiring T to be complete.
template <typename T, typename = void>
class SmallVectorTemplateCommon : public SmallVectorBase {
private:
diff --git a/third_party/subzero/Makefile.standalone b/third_party/subzero/Makefile.standalone
deleted file mode 100644
index 602616d..0000000
--- a/third_party/subzero/Makefile.standalone
+++ /dev/null
@@ -1,861 +0,0 @@
-# The following variables will likely need to be modified, depending on where
-# and how you built LLVM & Clang. They can be overridden in a command-line
-# invocation of make, like:
-#
-# make LLVM_SRC_PATH=<path> LIBCXX_INSTALL_PATH=<path> CLANG_PATH=<path> \
-# PNACL_BIN_PATH=<path> ...
-#
-
-# LLVM_SRC_PATH is the path to the root of the checked out source code. This
-# directory should contain the configure script, the include/ and lib/
-# directories of LLVM, Clang in tools/clang/, etc.
-# Alternatively, if you're building vs. a binary download of LLVM, then
-# LLVM_SRC_PATH can point to the main untarred directory.
-LLVM_SRC_PATH ?= ../llvm
-
-# The x86-32-specific sandboxed translator directory.
-# It holds sandboxed versions of libraries and binaries.
-SB_LLVM_PATH ?= $(shell readlink -e \
- ../../out/sandboxed_translators_work/translator-i686/llvm-sb/Release)
-
-# NACL_ROOT is the root of the native client repository.
-NACL_ROOT ?= $(shell python -c "import sys; sys.path.insert(0, 'pydir'); \
- import utils; print utils.FindBaseNaCl()")
-
-# TOOLCHAIN_ROOT is the location of NaCl/PNaCl toolchains and other
-# tools like qemu.
-TOOLCHAIN_ROOT ?= $(shell readlink -e $(NACL_ROOT)/toolchain/linux_x86)
-
-# PNACL_TOOLCHAIN_ROOT is the location of the PNaCl toolchain.
-# This is used as the default root for finding binutils, libcxx, etc.
-PNACL_TOOLCHAIN_ROOT ?= $(shell readlink -e $(TOOLCHAIN_ROOT)/pnacl_newlib_raw)
-
-# The location of PNaCl tools (e.g., binutils objdump, pnacl-clang++, etc.).
-PNACL_BIN_PATH ?= $(shell readlink -e $(PNACL_TOOLCHAIN_ROOT)/bin)
-
-# Allow tests to be overridden, e.g.:
-# make -f Makefile.standalone check-lit \
-# CHECK_LIT_TESTS="tests_lit/llvm2ice_tests/{alloc,arith}.ll"
-# make -f Makefile.standalone check-xtest \
-# CHECK_XTEST_TESTS=crosstest/Output/simple_loop_x8632_native_O2_sse2.xtest
-CHECK_LIT_TESTS ?= tests_lit
-CHECK_XTEST_TESTS ?= crosstest/Output
-
-# Hack to auto-detect autoconf versus cmake build of LLVM. If the LLVM tools
-# were dynamically linked with something like libLLVM-3.7svn.so, it is an
-# autoconf build, otherwise it is a cmake build. AUTOCONF is set to 0 for
-# cmake, nonzero for autoconf.
-AUTOCONF ?= $(shell ldd $(PNACL_BIN_PATH)/opt | grep -c libLLVM-)
-
-# CLANG_PATH is the location of the clang compiler to use for building
-# the host binaries.
-CLANG_PATH ?= $(shell readlink -e \
- $(NACL_ROOT)/../third_party/llvm-build/Release+Asserts/bin)
-
-# LIBCXX_INSTALL_PATH is the directory where libc++ is located. It should
-# contain header files and corresponding libraries. This is used for
-# building the host binaries in conjuction with clang.
-LIBCXX_INSTALL_PATH ?= $(PNACL_TOOLCHAIN_ROOT)
-STDLIB_FLAGS := -stdlib=libc++ -I$(LIBCXX_INSTALL_PATH)/include/c++/v1
-
-HOST_ARCH ?= x86_64
-ifeq ($(HOST_ARCH),x86_64)
- HOST_FLAGS = -m64
-else
- ifeq ($(HOST_ARCH),x86)
- HOST_FLAGS = -m32
- endif
-endif
-
-ifdef DEBUG
- OBJDIR = build/Debug
- OPTLEVEL = -O0
- LINKOPTLEVEL = -O0
-else
- OBJDIR = build/Release
- OPTLEVEL = -O2 -ffunction-sections -fdata-sections
- LINKOPTLEVEL = -O2
-endif
-
-# The list of CXX defines that are dependent on build parameters.
-BASE_CXX_DEFINES =
-CXX_EXTRA =
-LD_EXTRA =
-
-ifdef MINIMAL
- NOASSERT = 1
- NODUMP = 1
- OBJDIR := $(OBJDIR)+Min
- BASE_CXX_DEFINES += -DALLOW_LLVM_CL=0 -DALLOW_LLVM_IR=0 \
- -DALLOW_LLVM_IR_AS_INPUT=0 -DALLOW_TIMERS=0 -DALLOW_MINIMAL_BUILD=1
-else
- BASE_CXX_DEFINES += -DALLOW_LLVM_CL=1 -DALLOW_LLVM_IR=1 \
- -DALLOW_LLVM_IR_AS_INPUT=1 -DALLOW_TIMERS=1 -DALLOW_MINIMAL_BUILD=0
-endif
-
-ifdef NODUMP
- OBJDIR := $(OBJDIR)+NoDump
- BASE_CXX_DEFINES += -DALLOW_DUMP=0
-else
- BASE_CXX_DEFINES += -DALLOW_DUMP=1
-endif
-
-# Restrict to a single supported target. Current options:
-# SZTARGET=ARM32
-# SZTARGET=MIPS32
-# SZTARGET=X8632
-# SZTARGET=X8664
-ifdef SZTARGET
- OBJDIR := $(OBJDIR)+T_$(SZTARGET)
- BASE_CXX_DEFINES += -DSZTARGET=$(SZTARGET)
-endif
-
-BASE_CXX_DEFINES += -DPNACL_LLVM
-SZ_COMMIT_COUNT := $(shell git rev-list --count HEAD)
-SZ_GIT_HASH := $(shell git rev-parse HEAD)
-BASE_CXX_DEFINES += -DSUBZERO_REVISION=$(SZ_COMMIT_COUNT)_$(SZ_GIT_HASH)
-
-CXX_DEFINES := $(BASE_CXX_DEFINES) -DPNACL_BROWSER_TRANSLATOR=0
-
-ifdef NOASSERT
- ASSERTIONS = -DNDEBUG
-else
- ASSERTIONS =
- OBJDIR := $(OBJDIR)+Asserts
-endif
-
-ifdef UBSAN
- OBJDIR := $(OBJDIR)+UBSan
- CXX_EXTRA += -fsanitize=undefined -fno-sanitize=vptr \
- -fno-sanitize=nonnull-attribute
- LD_EXTRA += -fsanitize=undefined
-endif
-
-ifdef UBSAN_TRAP
- OBJDIR := $(OBJDIR)+UBSan_Trap
- CXX_EXTRA += -fsanitize=undefined-trap -fsanitize-undefined-trap-on-error \
- -fno-sanitize=vptr -fno-sanitize=nonnull-attribute
- LD_EXTRA += -fsanitize=undefined-trap
-endif
-
-ifdef TSAN
- OBJDIR := $(OBJDIR)+TSan
- CXX_EXTRA += -fsanitize=thread
- LD_EXTRA += -fsanitize=thread
-endif
-
-ifdef ASAN
- OBJDIR := $(OBJDIR)+ASan
- CXX_EXTRA += -fsanitize=address
- LD_EXTRA += -fsanitize=address
-endif
-
-ifdef MSAN
- # TODO(ascull): this has an as yet undiagnosed uninitialized memory access
- OBJDIR := $(OBJDIR)+MSan
- CXX_EXTRA += -fsanitize=memory
- LD_EXTRA += -fsanitize=memory
-endif
-
-ifdef FORCEASM
- FORCEASM_FLAG = --filetype=asm
- # With --filetype=asm and --sandbox, the llvm-mc assembler emits the lock and
- # 16-bit prefixes in the "wrong" order, causing the validator to reject the
- # resulting nexe. So we just disable those tests for now.
- FORCEASM_XTEST_EXCLUDES = -e x8632,sandbox,test_sync_atomic
- FORCEASM_LIT_PARAM = --param=FORCEASM
- # x86 sandboxing lit tests are disabled because filetype=asm does not
- # handle bundle_lock pad-to-end correctly.
- # TODO(jpp): fix this.
- FORCEASM_LIT_TEST_EXCLUDES = --filter='^(?!.*/x86/sandboxing.ll).*'
-else
- FORCEASM_FLAG =
- FORCEASM_XTEST_EXCLUDES =
- FORCEASM_LIT_PARAM =
- FORCEASM_LIT_TEST_EXCLUDES =
-endif
-
-ifdef LINUX_MALLOC_PROFILE
- OBJDIR := $(OBJDIR)+MalProf
- CXX_EXTRA += -DALLOW_LINUX_MALLOC_PROFILE=1
- LD_EXTRA += -Wl,--export-dynamic
-endif
-
-SB_OBJDIR := $(OBJDIR)+Sandboxed
-SBB_OBJDIR := $(OBJDIR)+SandboxedBrowser
-
-V8_DIR = $(NACL_ROOT)/../v8
-V8_CXXFLAGS := -I$(V8_DIR)
-
-$(info -----------------------------------------------)
-$(info Using LLVM_SRC_PATH = $(LLVM_SRC_PATH))
-$(info Using SB_LLVM_PATH = $(SB_LLVM_PATH))
-$(info Using NACL_ROOT = $(NACL_ROOT))
-$(info Using TOOLCHAIN_ROOT = $(TOOLCHAIN_ROOT))
-$(info Using PNACL_TOOLCHAIN_ROOT = $(PNACL_TOOLCHAIN_ROOT))
-$(info Using PNACL_BIN_PATH = $(PNACL_BIN_PATH))
-$(info Using CLANG_PATH = $(CLANG_PATH))
-$(info Using LIBCXX_INSTALL_PATH = $(LIBCXX_INSTALL_PATH))
-$(info Using HOST_ARCH = $(HOST_ARCH))
-$(info -----------------------------------------------)
-
-LLVM_CXXFLAGS := `$(PNACL_BIN_PATH)/llvm-config --cxxflags`
-SB_LLVM_CXXFLAGS := $(LLVM_CXXFLAGS)
-
-# Listing specific libraries that are needed for pnacl-sz
-# and the unittests, since we build "tools-only" for the
-# sandboxed_translators (which doesn't include every library
-# listed by llvm-config).
-
-LLVM_LIBS_LIST := -lLLVMIRReader -lLLVMBitReader -lLLVMNaClBitTestUtils \
- -lLLVMNaClBitReader -lLLVMNaClBitAnalysis -lLLVMNaClBitWriter \
- -lLLVMAsmParser -lLLVMNaClAnalysis -lLLVMCore -lLLVMSupport
-
-ifeq ($(AUTOCONF), 0)
- # LLVM cmake build
- LLVM_LIBS := $(LLVM_LIBS_LIST)
- # For the cmake build, the gtest libs end up in the same place as the LLVM
- # libs, so no "-L..." arg is needed.
- GTEST_LIB_PATH ?=
- CLANG_FORMAT_PATH ?= $(PNACL_BIN_PATH)
-else
- # LLVM autoconf build
- LLVM_LIBS := -lLLVM-3.7svn
- GTEST_LIB_PATH ?= -L../../out/llvm_x86_64_linux_work/Release+Asserts/lib
- ifneq ($(wildcard \
- ../../out/llvm_x86_64_linux_work/Release+Asserts/bin/clang-format),)
- CLANG_FORMAT_PATH ?= ../../out/llvm_x86_64_linux_work/Release+Asserts/bin
- else
- CLANG_FORMAT_PATH ?= \
- ../../out/llvm_x86_64_linux_debug_work/Debug+Asserts/bin
- endif
-endif
-
-LLVM_LDFLAGS := $(LLVM_LIBS) \
- `$(PNACL_BIN_PATH)/llvm-config --ldflags` \
- `$(PNACL_BIN_PATH)/llvm-config --system-libs`
-SB_LLVM_LDFLAGS := -Wl,--start-group $(LLVM_LIBS_LIST) -Wl,--end-group \
- -L$(SB_LLVM_PATH)/lib
-
-CCACHE := `command -v ccache`
-CXX := CCACHE_CPP2=yes $(CCACHE) $(CLANG_PATH)/clang++
-SB_CXX := CCACHE_CPP2=yes $(CCACHE) $(PNACL_BIN_PATH)/pnacl-clang++
-SB_TRANSLATE := $(PNACL_BIN_PATH)/pnacl-translate
-SB_FINALIZE := $(PNACL_BIN_PATH)/pnacl-finalize --no-strip-syms
-
-# Extra warnings that LLVM's build system adds in addition to -Wall.
-LLVM_EXTRA_WARNINGS := -Wcovered-switch-default
-
-# Use g++ to compile, to check for errors/warnings that clang++ might have
-# missed. It's unlikely to link, unless LLVM was also built with g++, so the
-# compile_only target should be used. Note: This ifdef section is deliberately
-# placed here instead of with the other ifdef sections, so that its redefinition
-# of CXX/STDLIB_FLAGS/LLVM_EXTRA_WARNINGS follows their normal definitions.
-ifdef GPLUSPLUS
- CXX := CCACHE_CPP2=yes $(CCACHE) g++
- STDLIB_FLAGS :=
- LLVM_EXTRA_WARNINGS := \
- -Wcast-qual \
- -Wno-comment \
- -Wno-long-long \
- -Wno-maybe-uninitialized \
- -Wno-missing-field-initializers \
- -Wno-unused-parameter \
- -Wwrite-strings
- OBJDIR := $(OBJDIR)+Gplusplus
-endif
-
-BASE_CXXFLAGS := -std=gnu++11 -Wall -Wextra -fno-rtti \
- -fno-exceptions $(OPTLEVEL) $(ASSERTIONS) -g -pedantic \
- $(LLVM_EXTRA_WARNINGS) $(CXX_EXTRA) -MP -MD -Werror
-
-ifdef WASM
- BASE_CXXFLAGS := $(BASE_CXXFLAGS) $(V8_CXXFLAGS) -DALLOW_WASM=1
- OBJDIR := $(OBJDIR)+Wasm
-else
- BASE_CXXFLAGS := $(BASE_CXXFLAGS) -DALLOW_WASM=0
-endif
-
-# TODO(stichnot,jpp): Restructure static fields in template classes to avoid
-# needing -Wno-undefined-var-template .
-CXXFLAGS := $(LLVM_CXXFLAGS) $(BASE_CXXFLAGS) $(CXX_DEFINES) $(HOST_FLAGS) \
- $(STDLIB_FLAGS) -Wno-undefined-var-template
-SB_CXXFLAGS := $(SB_LLVM_CXXFLAGS) $(BASE_CXXFLAGS) $(BASE_CXX_DEFINES) \
- -Wno-unknown-pragmas -I$(NACL_ROOT) -I$(NACL_ROOT)/..
-
-LDFLAGS := $(HOST_FLAGS) -L$(LIBCXX_INSTALL_PATH)/lib -Wl,--gc-sections \
- $(LD_EXTRA) $(STDLIB_FLAGS)
-# Not specifying -Wl,--gc-sections but instead doing bitcode linking GC w/ LTO.
-SB_LDFLAGS := $(LINKOPTLEVEL) $(LD_EXTRA)
-
-# List the target-specific source files first, which generally take longer to
-# compile, in the hope of improving parallel build time.
-SRCS = \
- IceAssemblerARM32.cpp \
- IceAssemblerMIPS32.cpp \
- IceInstARM32.cpp \
- IceInstMIPS32.cpp \
- IceInstX8632.cpp \
- IceInstX8664.cpp \
- IceTargetLowering.cpp \
- IceTargetLoweringARM32.cpp \
- IceTargetLoweringMIPS32.cpp \
- IceTargetLoweringX86.cpp \
- IceTargetLoweringX8632.cpp \
- IceTargetLoweringX8664.cpp \
- IceAssembler.cpp \
- IceBrowserCompileServer.cpp \
- IceCfg.cpp \
- IceCfgNode.cpp \
- IceClFlags.cpp \
- IceCompiler.cpp \
- IceCompileServer.cpp \
- IceELFObjectWriter.cpp \
- IceELFSection.cpp \
- IceFixups.cpp \
- IceGlobalContext.cpp \
- IceGlobalInits.cpp \
- IceInst.cpp \
- IceIntrinsics.cpp \
- IceLiveness.cpp \
- IceLoopAnalyzer.cpp \
- IceMangling.cpp \
- IceMemory.cpp \
- IceOperand.cpp \
- IceRangeSpec.cpp \
- IceRegAlloc.cpp \
- IceRevision.cpp \
- IceRNG.cpp \
- IceSwitchLowering.cpp \
- IceThreading.cpp \
- IceTimerTree.cpp \
- IceTranslator.cpp \
- IceTypes.cpp \
- IceVariableSplitting.cpp \
- LinuxMallocProfiling.cpp \
- main.cpp \
- PNaClTranslator.cpp
-
-ifndef MINIMAL
- SRCS += \
- IceASanInstrumentation.cpp \
- IceConverter.cpp \
- IceInstrumentation.cpp \
- IceTypeConverter.cpp
-endif
-
-ifdef WASM
- SRCS += \
- WasmTranslator.cpp
-endif
-
-OBJS=$(patsubst %.cpp, $(OBJDIR)/%.o, $(SRCS))
-SB_OBJS=$(patsubst %.cpp, $(SB_OBJDIR)/%.o, $(SRCS))
-SBB_OBJS=$(patsubst %.cpp, $(SBB_OBJDIR)/%.o, $(SRCS))
-
-UNITTEST_SRCS = \
- BitcodeMunge.cpp \
- IceELFSectionTest.cpp \
- IceParseInstsTest.cpp
-
-# The X86 assembler tests take too long to compile. Given how infrequently the
-# assembler will change, we disable them.
-ifdef CHECK_X86_ASM
- ifndef DEBUG
- $(error Run check-unit with DEBUG=1 lest your machine perish)
- endif
- UNITTEST_SRCS += AssemblerX8632/LowLevel.cpp \
- AssemblerX8632/DataMov.cpp \
- AssemblerX8632/Locked.cpp \
- AssemblerX8632/GPRArith.cpp \
- AssemblerX8632/XmmArith.cpp \
- AssemblerX8632/ControlFlow.cpp \
- AssemblerX8632/Other.cpp \
- AssemblerX8632/X87.cpp \
- AssemblerX8664/LowLevel.cpp \
- AssemblerX8664/DataMov.cpp \
- AssemblerX8664/Locked.cpp \
- AssemblerX8664/GPRArith.cpp \
- AssemblerX8664/XmmArith.cpp \
- AssemblerX8664/ControlFlow.cpp \
- AssemblerX8664/Other.cpp
-endif
-
-UNITTEST_OBJS = $(patsubst %.cpp, $(OBJDIR)/unittest/%.o, $(UNITTEST_SRCS))
-UNITTEST_LIB_OBJS = $(filter-out $(OBJDIR)/main.o,$(OBJS))
-
-NEXES = $(SB_OBJDIR)/pnacl-sz.x8632.nexe \
- $(SB_OBJDIR)/pnacl-sz.x8664.nexe \
- $(SBB_OBJDIR)/pnacl_public_x86_32_pnacl_sz_nexe \
- $(SBB_OBJDIR)/pnacl_public_x86_64_pnacl_sz_nexe
-NEXES_LITE = $(SB_OBJDIR)/pnacl-sz.x8664.nexe
-
-# Keep all the first target so it's the default.
-all: $(OBJDIR)/pnacl-sz make_symlink runtime
-
-ifdef TSAN
-sb sb-lite:
- @echo "Skipping pnacl-sz.*.nexe: TSAN isn't supported under NaCl."
-else
-sb: $(NEXES) sb_make_symlink exists-sbtc
-sb-lite: $(NEXES_LITE) exists-sbtc
-endif
-
-# SHOW_BUILD_ATTS is an executable that is run to show what build
-# attributes were used to build pnacl-sz.
-SHOW_BUILD_ATTS = $(OBJDIR)/pnacl-sz --build-atts
-
-# Creates symbolic link so that testing is easier. Also runs
-# pnacl-sz to verify that the defines flags have valid values,
-# as well as describe the corresponding build attributes.
-make_symlink: $(OBJDIR)/pnacl-sz
- rm -rf pnacl-sz
- ln -s $(OBJDIR)/pnacl-sz
- @echo "Build Attributes:"
- @$(SHOW_BUILD_ATTS)
-
-sb_make_symlink: $(NEXES)
- $(foreach nexe,$(NEXES),rm -rf $(notdir $(nexe)); ln -s $(nexe);)
-
-%.pexe : %.nonfinal.pexe
- $(SB_FINALIZE) -o $@ $<
-
-.PHONY: all compile_only make_symlink runtime bloat sb docs help \
- help-check-lit help-check-xtest exists-nonsfi-x8632 \
- exists-nonsfi-arm32 exists-sbtc exists-spec
-
-compile_only: $(OBJS)
-
-V8_LIBDIR=$(V8_DIR)/out/native/lib.target
-
-ifdef WASM
- V8_LIBS := \
- $(V8_LIBDIR)/libv8.so \
- $(V8_LIBDIR)/libicuuc.so \
- $(V8_LIBDIR)/libicui18n.so
-endif
-
-$(OBJDIR)/pnacl-sz: $(OBJS)
- $(CXX) $(LDFLAGS) -o $@ $^ $(LLVM_LDFLAGS) \
- -Wl,-rpath=$(abspath $(LIBCXX_INSTALL_PATH)/lib) $(V8_LIBS)
-
-$(SB_OBJDIR)/pnacl-sz.nonfinal.pexe: $(SB_OBJS)
- $(SB_CXX) $(SB_LDFLAGS) -o $@ $^ $(SB_LLVM_LDFLAGS)
-
-$(SBB_OBJDIR)/pnacl-sz.nonfinal.pexe: $(SBB_OBJS)
- $(SB_CXX) $(SB_LDFLAGS) -o $@ $^ $(SB_LLVM_LDFLAGS) \
- --pnacl-disable-abi-check
-
-$(SB_OBJDIR)/pnacl-sz.x8632.nexe: $(SB_OBJDIR)/pnacl-sz.pexe
- $(SB_TRANSLATE) -arch x86-32 $^ -o $@
-
-$(SB_OBJDIR)/pnacl-sz.x8664.nexe: $(SB_OBJDIR)/pnacl-sz.pexe
- $(SB_TRANSLATE) -arch x86-64 $^ -o $@
-
-$(SBB_OBJDIR)/pnacl_public_x86_32_pnacl_sz_nexe: $(SBB_OBJDIR)/pnacl-sz.pexe
- $(SB_TRANSLATE) -arch x86-32 $^ -o $@
-
-$(SBB_OBJDIR)/pnacl_public_x86_64_pnacl_sz_nexe: $(SBB_OBJDIR)/pnacl-sz.pexe
- $(SB_TRANSLATE) -arch x86-64 $^ -o $@
-
-src/IceRegistersARM32.def: pydir/gen_arm32_reg_tables.py
- python $< > $@
-
--include $(foreach dep,$(SRCS:.cpp=.d),$(OBJDIR)/$(dep))
-$(OBJS): $(OBJDIR)/%.o: src/%.cpp
- $(CXX) -c $(CXXFLAGS) $< -o $@
-
--include $(foreach dep,$(SRCS:.cpp=.d),$(SB_OBJDIR)/$(dep))
-$(SB_OBJS): $(SB_OBJDIR)/%.o: src/%.cpp
- $(SB_CXX) -c $(SB_CXXFLAGS) -DPNACL_BROWSER_TRANSLATOR=0 $< -o $@
-
--include $(foreach dep,$(SRCS:.cpp=.d),$(SBB_OBJDIR)/$(dep))
-$(SBB_OBJS): $(SBB_OBJDIR)/%.o: src/%.cpp
- $(SB_CXX) -c $(SB_CXXFLAGS) -DPNACL_BROWSER_TRANSLATOR=1 $< -o $@
-
-$(OBJDIR)/run_unittests: $(UNITTEST_OBJS) $(UNITTEST_LIB_OBJS)
- $(CXX) $(GTEST_LIB_PATH) $(LDFLAGS) -o $@ $^ $(LLVM_LDFLAGS) \
- -lgtest -lgtest_main -ldl \
- -Wl,-rpath=$(abspath $(LIBCXX_INSTALL_PATH)/lib)
-
--include $(foreach dep,$(UNITTEST_SRCS:.cpp=.d),$(OBJDIR)/unittest/$(dep))
-$(UNITTEST_OBJS): $(OBJDIR)/unittest/%.o: unittest/%.cpp
- $(CXX) -c $(CXXFLAGS) \
- -Isrc/ \
- -Iunittest/ \
- -I$(LLVM_SRC_PATH)/utils/unittest/googletest/include \
- -I$(LLVM_SRC_PATH) \
- -DGTEST_HAS_RTTI=0 -DGTEST_USE_OWN_TR1_TUPLE \
- -Wno-expansion-to-defined \
- $< -o $@
-
-$(OBJS): | $(OBJDIR)
-$(SB_OBJS): | $(SB_OBJDIR)
-$(SBB_OBJS): | $(SBB_OBJDIR)
-
-$(UNITTEST_OBJS): | $(OBJDIR)/unittest $(OBJDIR)/unittest/AssemblerX8632 \
- $(OBJDIR)/unittest/AssemblerX8664
-
-$(OBJDIR):
- @mkdir -p $@
-$(SB_OBJDIR):
- @mkdir -p $@
-$(SBB_OBJDIR):
- @mkdir -p $@
-
-$(OBJDIR)/unittest: $(OBJDIR)
- @mkdir -p $@
-
-$(OBJDIR)/unittest/AssemblerX8632: $(OBJDIR)/unittest
- @mkdir -p $@
-$(OBJDIR)/unittest/AssemblerX8664: $(OBJDIR)/unittest
- @mkdir -p $@
-
-RT_SRC := runtime/szrt.c runtime/szrt_ll.ll runtime/szrt_profiler.c \
- runtime/szrt_asm_x8632.s runtime/szrt_asm_x8664.s \
- runtime/szrt_asm_arm32.s runtime/szrt_asan.c
-RT_OBJ := build/runtime/szrt_native_x8632.o build/runtime/szrt_sb_x8632.o \
- build/runtime/szrt_nonsfi_x8632.o \
- build/runtime/szrt_native_x8664.o build/runtime/szrt_sb_x8664.o \
- build/runtime/szrt_nonsfi_x8664.o \
- build/runtime/szrt_native_arm32.o build/runtime/szrt_sb_arm32.o \
- build/runtime/szrt_nonsfi_arm32.o \
- build/runtime/szrt_asan_x8632.o build/runtime/szrt_asan_x8664.o \
- build/runtime/szrt_asan_arm32.o
-
-EXCLUDED_RT :=
-ifdef MIPS
-RT_SRC += runtime/szrt_asm_mips32.s
-RT_OBJ += build/runtime/szrt_native_mips32.o build/runtime/szrt_sb_mips32.o
-else
-EXCLUDED_RT += --exclude-target=mips32
-endif
-
-runtime: $(RT_OBJ)
-
-# Use runtime.is.built so that build-runtime.py is invoked only once
-# even in a parallel build.
-.INTERMEDIATE: runtime.is.built
-$(RT_OBJ): runtime.is.built
-runtime.is.built: $(RT_SRC) pydir/build-runtime.py
- @echo ================ Building Subzero runtime ================
- ./pydir/build-runtime.py -v --pnacl-root $(PNACL_TOOLCHAIN_ROOT) \
- $(EXCLUDED_RT)
-
-check-lit: $(OBJDIR)/pnacl-sz make_symlink runtime
- PNACL_BIN_PATH=$(PNACL_BIN_PATH) \
- $(LLVM_SRC_PATH)/utils/lit/lit.py -sv $(CHECK_LIT_TESTS) \
- $(FORCEASM_LIT_TEST_EXCLUDES) $(FORCEASM_LIT_PARAM)
-
-ifdef MINIMAL
-check-xtest check-xtest-lite: $(OBJDIR)/pnacl-sz make_symlink runtime
- @echo "Crosstests disabled, minimal build"
-else
-ifdef MIPS
-check-xtest check-xtest-lite: $(OBJDIR)/pnacl-sz make_symlink runtime \
- crosstest/test_arith_ll.ll
- # Do all x8664/native/sse2 tests as a smoke test.
- # Add in mips32 tests as they come online.
- ./pydir/crosstest_generator.py -v --lit \
- --toolchain-root $(TOOLCHAIN_ROOT) \
- $(FORCEASM_FLAG) \
- $(FORCEASM_XTEST_EXCLUDES) \
- -i x8664,native,sse2 \
- -i mips32,native,Om1,simple_loop \
- -i mips32,native,Om1,test_strengthreduce
- PNACL_BIN_PATH=$(PNACL_BIN_PATH) \
- $(LLVM_SRC_PATH)/utils/lit/lit.py -sv $(CHECK_XTEST_TESTS)
-else
-check-xtest: $(OBJDIR)/pnacl-sz make_symlink runtime \
- exists-nonsfi-x8632 exists-nonsfi-arm32 crosstest/test_arith_ll.ll
- # Do all native/sse2 tests, but only test_vector_ops for native/sse4.1.
- # For (slow) sandboxed tests, limit to Om1/sse4.1.
- # run.py (used to run the sandboxed xtests) does not support
- # specifying -cpu cortex-a15 to qemu, hence we disable the
- # hwdiv-arm tests.
- ./pydir/crosstest_generator.py -v --lit \
- --toolchain-root $(TOOLCHAIN_ROOT) \
- $(FORCEASM_FLAG) \
- $(FORCEASM_XTEST_EXCLUDES) \
- -i x8632,native,sse2 \
- -i x8632,native,sse4.1,test_vector_ops \
- -i x8632,sandbox,sse4.1,Om1 \
- -i x8632,nonsfi,sse2,O2 \
- -i x8664,native,sse2 \
- -i x8664,native,sse4.1,test_vector_ops \
- -i x8664,sandbox,sse4.1,Om1 \
- -i arm32 \
- -e arm32,sandbox,hwdiv-arm
- PNACL_BIN_PATH=$(PNACL_BIN_PATH) \
- $(LLVM_SRC_PATH)/utils/lit/lit.py -sv $(CHECK_XTEST_TESTS)
-check-xtest-lite: $(OBJDIR)/pnacl-sz make_symlink runtime \
- exists-nonsfi-x8632 exists-nonsfi-arm32 crosstest/test_arith_ll.ll
- # Do all native/sse2/neon tests, which are relatively fast.
- # Limit to test_global+mem_intrin for sandbox+nonsfi because sandbox and
- # nonsfi builds are slow, and test_global and mem_intrin are the most
- # common sources of problems.
- ./pydir/crosstest_generator.py -v --lit \
- --toolchain-root $(TOOLCHAIN_ROOT) \
- $(FORCEASM_FLAG) \
- $(FORCEASM_XTEST_EXCLUDES) \
- -i x8632,native,sse2,O2 \
- -i x8664,native,sse2,O2 \
- -i arm32,native,neon,O2 \
- -i x8632,sse2,O2,test_global \
- -i x8632,sse2,O2,mem_intrin \
- -i x8664,sse2,O2,test_global \
- -i x8664,sse2,O2,mem_intrin \
- -i arm32,neon,O2,test_global \
- -i arm32,neon,O2,mem_intrin \
- -e x8664,nonsfi
- PNACL_BIN_PATH=$(PNACL_BIN_PATH) \
- $(LLVM_SRC_PATH)/utils/lit/lit.py -sv $(CHECK_XTEST_TESTS)
-crosstest/test_arith_ll.ll: pydir/gen_test_arith_ll.py
- python $< > $@
-endif
-endif
-
-check-unit: $(OBJDIR)/run_unittests
- $(OBJDIR)/run_unittests
-
-# List the spec2k components in roughly reverse order of runtime, to help with
-# parallel execution speed.
-ALLSPEC := 253.perlbmk 177.mesa 188.ammp 256.bzip2 164.gzip 179.art 183.equake \
- 175.vpr 176.gcc 181.mcf 186.crafty 197.parser 254.gap 255.vortex \
- 300.twolf 252.eon
-.PHONY: $(ALLSPEC)
-
-TARGET := x8632
-ifeq ($(TARGET),x8632)
- TARGETFLAG=x8632
- SETUP=SetupGccX8632Opt
- SPEC := --filetype=obj
-endif
-ifeq ($(TARGET),x8664)
- TARGETFLAG=x8664
- SETUP=SetupGccX8664Opt
- SPEC := --filetype=obj
-endif
-ifeq ($(TARGET),arm32)
- TARGETFLAG=arm32
- SETUP=SetupGccArmOpt
- SPEC := --filetype=obj
-endif
-ifeq ($(TARGET),mips32)
- # native_client/tests/spec2k/{Makefile.common,run_all.sh} do not currently
- # have MIPS configs, so those would need to be added for proper Subzero
- # testing.
- TARGETFLAG=mips32
- SETUP=SetupGccMipsOpt
- SPEC := --filetype=asm
-endif
-SPECFLAGS := -O2
-SPECRUN := --run
-%.spec2k: % $(OBJDIR)/pnacl-sz make_symlink runtime
- ./pydir/szbuild_spec2k.py -v \
- $(SPECFLAGS) --target=$(TARGETFLAG) $(SPEC) $< $(SPECRUN)
-
-ifdef MIPS
-# Don't test spec2k on mips32, at least not yet.
-check-spec:
-else
-check-spec: exists-spec $(ALLSPEC:=.spec2k)
-endif
-
-check: check-lit check-unit check-xtest
-
-NONSFI_LOADER_X8632 = \
- $(NACL_ROOT)/scons-out/opt-linux-x86-32/obj/src/nonsfi/loader/nonsfi_loader
-NONSFI_LOADER_ARM32 = \
- $(NACL_ROOT)/scons-out/opt-linux-arm/obj/src/nonsfi/loader/nonsfi_loader
-SBTC_LIBFILE = $(SB_LLVM_PATH)/lib/libLLVMSupport.a
-SPEC_SAMPLE_PEXE = $(NACL_ROOT)/tests/spec2k/176.gcc/gcc.opt.stripped.pexe
-
-exists-nonsfi-x8632:
- @if [ ! -f $(NONSFI_LOADER_X8632) ] ; then \
- echo "Missing file $(NONSFI_LOADER_X8632)"; \
- echo "Consider running './scons nonsfi_loader'" \
- "in the native_client directory."; \
- exit 1 ; \
- fi
-
-exists-nonsfi-arm32:
- @if [ ! -f $(NONSFI_LOADER_ARM32) ] ; then \
- echo "Missing file $(NONSFI_LOADER_ARM32)"; \
- echo "Consider running './scons platform=arm nonsfi_loader'" \
- "in the native_client directory."; \
- exit 1 ; \
- fi
-
-exists-sbtc:
- @if [ ! -f $(SBTC_LIBFILE) ] ; then \
- echo "Missing file $(SBTC_LIBFILE)"; \
- echo "Consider running 'toolchain_build_pnacl.py --build-sbtc'."; \
- exit 1 ; \
- fi
-
-exists-spec:
- @if [ ! -f $(SPEC_SAMPLE_PEXE) ] ; then \
- echo "Missing file $(SPEC_SAMPLE_PEXE)"; \
- echo "Consider running" \
- "'./run_all.sh BuildBenchmarks 0 SetupPnaclX8632Opt'" \
- "in the native_client/tests/spec2k directory."; \
- exit 1 ; \
- fi
-
-ifdef MIPS
-check-presubmit presubmit: exists-sbtc
-# Make sure clang-format gets run.
- +make -f Makefile.standalone format
-# Verify MINIMAL build, plus proper usage of REQUIRES in lit tests.
- +make -f Makefile.standalone \
- MINIMAL=1 check
-# Check that there are no g++ build errors or warnings.
- +make -f Makefile.standalone \
- GPLUSPLUS=1 compile_only
-# Run lit tests, cross tests, and unit tests.
- +make -f Makefile.standalone \
- check
-# Check a sandboxed translator build.
- +make -f Makefile.standalone \
- DEBUG=1 sb
-# Provide validation of user awesomeness!
- echo Success
-else
-check-presubmit presubmit: exists-nonsfi-x8632 exists-nonsfi-arm32 \
- exists-sbtc exists-spec
-# Make sure clang-format gets run.
- +make -f Makefile.standalone format
-# Verify MINIMAL build, plus proper usage of REQUIRES in lit tests.
- +make -f Makefile.standalone \
- MINIMAL=1 check
-# Check that there are no g++ build errors or warnings.
- +make -f Makefile.standalone \
- GPLUSPLUS=1 compile_only
-# Check the x86 assembler unit tests.
- +make -f Makefile.standalone \
- DEBUG=1 CHECK_X86_ASM=1 check-unit sb
-# Run lit tests, cross tests, unit tests, and spec2k/x86-32.
- +make -f Makefile.standalone \
- check check-spec
-# Run spec2k/x86-64.
- +make -f Makefile.standalone \
- TARGET=x8664 check-spec
-# Run spec2k/x86-64 with sandboxing.
- +make -f Makefile.standalone \
- SPECFLAGS='-O2 --sandbox' TARGET=x8664 check-spec
-# Build spec2k under -Om1/x86-32, to check for liveness errors.
- +make -f Makefile.standalone \
- SPECFLAGS='-Om1' SPECRUN= check-spec
-# Build spec2k under -Om1/x86-64, to check for liveness errors.
- +make -f Makefile.standalone \
- SPECFLAGS='-Om1' TARGET=x8664 SPECRUN= check-spec
-# Run spec2k for x86-32 without advanced phi lowering.
- +make -f Makefile.standalone \
- SPECFLAGS='-O2 --sz=--phi-edge-split=0' check-spec
-# Run spec2k for x86-64 without advanced phi lowering.
- +make -f Makefile.standalone \
- SPECFLAGS='-O2 --sz=--phi-edge-split=0' TARGET=x8664 check-spec
-# Run cross tests and lit tests to validate filetype=asm output.
- +make -f Makefile.standalone \
- FORCEASM=1 check-xtest check-lit
-# Build spec2k for arm32.
- +make -f Makefile.standalone \
- TARGET=arm32 SPECRUN= check-spec
-# Build spec2k under -Om1/arm32.
- +make -f Makefile.standalone \
- TARGET=arm32 SPECFLAGS='-Om1' SPECRUN= check-spec
-# Run a few spec2k tests for arm32 using qemu. Keep the list sorted in
-# roughly reverse order of runtime.
- +make -f Makefile.standalone \
- TARGET=arm32 ALLSPEC='252.eon 254.gap 176.gcc 181.mcf' check-spec
-# Provide validation of user awesomeness!
- echo Success
-endif
-
-presubmit-lite: exists-nonsfi-x8632 exists-nonsfi-arm32 \
- exists-sbtc exists-spec
-# Make sure clang-format gets run.
- +make -f Makefile.standalone format
-# Verify MINIMAL build, plus proper usage of REQUIRES in lit tests.
- +make -f Makefile.standalone \
- MINIMAL=1 check sb-lite
-# Check that there are no g++ build errors or warnings.
- +make -f Makefile.standalone \
- GPLUSPLUS=1 compile_only
-# Run lit tests, cross tests, unit tests, and spec2k/x86-32.
- +make -f Makefile.standalone \
- check-lit check-unit check-spec
- +make -f Makefile.standalone \
- check-xtest-lite
-# Run spec2k/x86-64.
- +make -f Makefile.standalone \
- TARGET=x8664 check-spec
-# Build spec2k under -Om1/x86-32, to check for liveness errors.
- +make -f Makefile.standalone \
- SPECFLAGS='-Om1' SPECRUN= check-spec
-# Build spec2k under -Om1/x86-64, to check for liveness errors.
- +make -f Makefile.standalone \
- SPECFLAGS='-Om1' TARGET=x8664 SPECRUN= check-spec
-# Run cross tests and lit tests to validate filetype=asm output.
- +make -f Makefile.standalone \
- FORCEASM=1 check-lit
- +make -f Makefile.standalone \
- FORCEASM=1 check-xtest-lite
-# Build spec2k under -Om1/arm32.
- +make -f Makefile.standalone \
- TARGET=arm32 SPECFLAGS='-Om1' SPECRUN= check-spec
-# Run a few spec2k tests for arm32 using qemu. Keep the list sorted in
-# roughly reverse order of runtime.
- +make -f Makefile.standalone \
- TARGET=arm32 ALLSPEC='254.gap 176.gcc 181.mcf' check-spec
-# Provide validation of user awesomeness!
- echo Success
-
-FORMAT_BLACKLIST =
-# Add one of the following lines for each source file to ignore.
-FORMAT_BLACKLIST += ! -name IceParseInstsTest.cpp
-FORMAT_BLACKLIST += ! -name IceParseTypesTest.cpp
-FORMAT_BLACKLIST += ! -name assembler_arm.h
-FORMAT_BLACKLIST += ! -name assembler_arm.cc
-FORMAT_BLACKLIST += ! -path "./wasm-install/*"
-FORMAT_BLACKLIST += ! -path "./pnacl-llvm/*"
-format:
- $(CLANG_FORMAT_PATH)/clang-format -style=LLVM -i \
- `find . -regex '.*\.\(c\|h\|cpp\)' $(FORMAT_BLACKLIST)`
-
-format-diff:
- git diff -U0 `git merge-base HEAD master` | \
- PATH=$(PNACL_BIN_PATH):$(PATH) \
- $(LLVM_SRC_PATH)/../clang/tools/clang-format/clang-format-diff.py \
- -p1 -style=LLVM -i
-
-bloat: make_symlink
- nm -C -S -l pnacl-sz | \
- bloat/bloat.py --nm-output=/dev/stdin syms > build/pnacl-sz.bloat.json
- @echo See Subzero size breakdown in bloat/pnacl-sz.bloat.html
-
-bloat-sb: sb_make_symlink
- $(foreach nexe,$(NEXES),nm -C -S -l $(nexe) | bloat/bloat.py \
- --nm-output=/dev/stdin syms > build/$(notdir $(nexe)).bloat.json;)
- @echo "See Subzero size breakdown in:"
- @$(foreach nexe,$(NEXES),echo " bloat/$(notdir $(nexe)).bloat.html";)
-
-docs:
- make -C docs -f Makefile.standalone
-
-help:
- @cat Makefile.standalone-help/help.txt
-
-help-check-lit:
- @cat Makefile.standalone-help/check-lit.txt
-
-help-check-xtest:
- @cat Makefile.standalone-help/check-xtest.txt
-
-clean:
- rm -rf pnacl-sz *.o $(foreach nexe,$(NEXES),$(notdir $(nexe))) \
- $(OBJDIR) $(SB_OBJDIR) $(SBB_OBJDIR) build/*.bloat.json
-
-clean-all: clean
- rm -rf build/ crosstest/Output/
diff --git a/third_party/subzero/Makefile.standalone-help/check-lit.txt b/third_party/subzero/Makefile.standalone-help/check-lit.txt
deleted file mode 100644
index 472a8fc..0000000
--- a/third_party/subzero/Makefile.standalone-help/check-lit.txt
+++ /dev/null
@@ -1,4 +0,0 @@
-check-lit - run the lit tests
-To check a specific test, override CHECK_LIT_TESTS, e.g.:
- make -f Makefile.standalone check-lit \
- CHECK_LIT_TESTS=tests_lit/llvm2ice_tests/arith.ll
diff --git a/third_party/subzero/Makefile.standalone-help/check-xtest.txt b/third_party/subzero/Makefile.standalone-help/check-xtest.txt
deleted file mode 100644
index d193393..0000000
--- a/third_party/subzero/Makefile.standalone-help/check-xtest.txt
+++ /dev/null
@@ -1,5 +0,0 @@
-check-xtest - run the cross tests
-
-To check a specific test, override CHECK_XTEST_TESTS, e.g.:
- make -f Makefile.standalone check-xtest \
- CHECK_XTEST_TESTS=crosstest/Output/mem_intrin_x8632_nonsfi_O2_sse2.xtest
diff --git a/third_party/subzero/Makefile.standalone-help/help.txt b/third_party/subzero/Makefile.standalone-help/help.txt
deleted file mode 100644
index d005fc7..0000000
--- a/third_party/subzero/Makefile.standalone-help/help.txt
+++ /dev/null
@@ -1,34 +0,0 @@
-Targets:
-
-check-lit - run the lit tests
-check-xtest - run the cross tests
-
-Additional 'make' command options:
- MINIMAL=1
- Create a minimal build, as small and fast as possible
- DEBUG=1
- Compile with -O0 instead of -O2
- NODUMP=1
- Disable textual dump/emission support and other verbose options
- NOASSERT=1
- Disable assert() calls, via -DNDEBUG
- UBSAN=1
- Enable UBSan support, i.e. -fsanitize=undefined
- UBSAN_TRAP=1
- Enable UBSan support, trapping on errors
- TSAN=1
- Enable TSan support, i.e. -fsanitize=thread
- ASAN=1
- Enable ASan support, i.e. -fsanitize=address
- MSAN=1
- Enable MSan support, i.e. -fsanitize=memory
- SZTARGET=<target>
- Restrict support to a single processor target,
- where <target> is one of {ARM32,MIPS32,X8632,X8664}
-Most of these options can be combined, e.g.
- make -f Makefile.standalone NOASSERT=1 NODUMP=1
-
-For more detailed help on a 'make' target:
-
- make -f Makefile.standalone help-<target> , e.g:
- make -f Makefile.standalone help-check-lit
diff --git a/third_party/subzero/docs/DESIGN.rst b/third_party/subzero/docs/DESIGN.rst
index 363c19c..115d645 100644
--- a/third_party/subzero/docs/DESIGN.rst
+++ b/third_party/subzero/docs/DESIGN.rst
@@ -1430,11 +1430,10 @@
functions) that yield incorrect behavior. For this, we have a bisection
debugging framework. Here, we initially translate the entire application once
with Subzero and once with ``pnacl-llc``. We then use ``objdump`` to
-selectively weaken symbols based on a whitelist or blacklist provided on the
-command line. The two object files can then be linked together without link
-errors, with the desired version of each method "winning". Then the binary is
-tested, and bisection proceeds based on whether the binary produces correct
-output.
+selectively weaken symbols based on a list provided on the command line. The
+two object files can then be linked together without link errors, with the
+desired version of each method "winning". Then the binary is tested, and
+bisection proceeds based on whether the binary produces correct output.
When the bisection completes, we are left with a minimal set of
Subzero-translated functions that cause the failure. Usually it is a single
@@ -1442,7 +1441,7 @@
to cause a failure; this may be due to an incorrect call ABI, for example.
However, Murphy's Law implies that the single failing function is enormous and
impractical to debug. In that case, we can restart the bisection, explicitly
-blacklisting the enormous function, and try to find another candidate to debug.
+ignoring the enormous function, and try to find another candidate to debug.
(Future work is to automate this to find all minimal sets of functions, so that
debugging can focus on the simplest example.)
diff --git a/third_party/subzero/pydir/bisection-test.py b/third_party/subzero/pydir/bisection-test.py
deleted file mode 100755
index 81ae639..0000000
--- a/third_party/subzero/pydir/bisection-test.py
+++ /dev/null
@@ -1,55 +0,0 @@
-#!/usr/bin/env python2
-import argparse
-import sys
-
-def main():
- desc = 'Crash simulator script, useful for testing the bisection tool.\
- bisection-tool.py --cmd "./pydir/bisection-test.py -c 2x3" \
- --end 1000 --timeout 60'
- argparser = argparse.ArgumentParser(description=desc)
- argparser.add_argument('--include', '-i', default=[], dest='include',
- action='append',
- help='Include list, single values or ranges')
- argparser.add_argument('--exclude', '-e', default=[], dest='exclude',
- action='append',
- help='Exclude list, single values or ranges')
- argparser.add_argument('--crash', '-c', default=[], dest='crash',
- action='append',
- help='Crash list, single values or x-separated combinations like 2x4')
-
- args = argparser.parse_args()
-
- included = {-1}
- for string in args.include:
- include_range = string.split(':')
- if len(include_range) == 1:
- included.add(int(include_range[0]))
- else:
- for num in range(int(include_range[0]), int(include_range[1])):
- included.add(num)
-
- for string in args.exclude:
- exclude_range = string.split(':')
- if len(exclude_range) == 1:
- try:
- included.remove(int(exclude_range[0]))
- except KeyError:
- pass # Exclude works without a matching include
- else:
- for num in range(int(exclude_range[0]), int(exclude_range[1])):
- included.remove(num)
-
- for string in args.crash:
- crash_combination = string.split('x')
- fail = True
- for crash in crash_combination:
- if not int(crash) in included:
- fail = False
- if fail:
- print 'Fail'
- exit(1)
- print 'Success'
- exit(0)
-
-if __name__ == '__main__':
- main()
diff --git a/third_party/subzero/pydir/bisection-tool.py b/third_party/subzero/pydir/bisection-tool.py
deleted file mode 100755
index 6e6c666..0000000
--- a/third_party/subzero/pydir/bisection-tool.py
+++ /dev/null
@@ -1,201 +0,0 @@
-#!/usr/bin/env python2
-
-import argparse
-import math
-import os
-import re
-import signal
-import subprocess
-
-class Runner(object):
- def __init__(self, input_cmd, timeout, comma_join, template, find_all):
- self._input_cmd = input_cmd
- self._timeout = timeout
- self._num_tries = 0
- self._comma_join = comma_join
- self._template = template
- self._find_all = find_all
-
- def estimate(self, included_ranges):
- result = 0
- for i in included_ranges:
- if isinstance(i, int):
- result += 1
- else:
- if i[1] - i[0] > 2:
- result += int(math.log(i[1] - i[0], 2))
- else:
- result += (i[1] - i[0])
- if self._find_all:
- return 2 * result
- else:
- return result
-
- def Run(self, included_ranges):
- def timeout_handler(signum, frame):
- raise RuntimeError('Timeout')
-
- self._num_tries += 1
- cmd_addition = ''
- for i in included_ranges:
- if isinstance(i, int):
- range_str = str(i)
- else:
- range_str = '{start}:{end}'.format(start=i[0], end=i[1])
- if self._comma_join:
- cmd_addition += ',' + range_str
- else:
- cmd_addition += ' -i ' + range_str
-
- if self._template:
- cmd = cmd_addition.join(re.split(r'%i' ,self._input_cmd))
- else:
- cmd = self._input_cmd + cmd_addition
-
- print cmd
- p = subprocess.Popen(cmd, shell = True, cwd = None,
- stdout = subprocess.PIPE, stderr = subprocess.PIPE, env = None)
- if self._timeout != -1:
- signal.signal(signal.SIGALRM, timeout_handler)
- signal.alarm(self._timeout)
-
- try:
- _, _ = p.communicate()
- if self._timeout != -1:
- signal.alarm(0)
- except:
- try:
- os.kill(p.pid, signal.SIGKILL)
- except OSError:
- pass
- print 'Timeout'
- return -9
- print '===Return Code===: ' + str(p.returncode)
- print '===Remaining Steps (approx)===: ' \
- + str(self.estimate(included_ranges))
- return p.returncode
-
-def flatten(tree):
- if isinstance(tree, list):
- result = []
- for node in tree:
- result.extend(flatten(node))
- return result
- else:
- return [tree] # leaf
-
-def find_failures(runner, current_interval, include_ranges, find_all):
- if current_interval[0] == current_interval[1]:
- return []
- mid = (current_interval[0] + current_interval[1]) / 2
-
- first_half = (current_interval[0], mid)
- second_half = (mid, current_interval[1])
-
- exit_code_2 = 0
-
- exit_code_1 = runner.Run([first_half] + include_ranges)
- if find_all or exit_code_1 == 0:
- exit_code_2 = runner.Run([second_half] + include_ranges)
-
- if exit_code_1 == 0 and exit_code_2 == 0:
- # Whole range fails but both halves pass
- # So, some conjunction of functions cause a failure, but none individually.
- partial_result = flatten(find_failures(runner, first_half, [second_half]
- + include_ranges, find_all))
- # Heavy list concatenation, but this is insignificant compared to the
- # process run times
- partial_result.extend(flatten(find_failures(runner, second_half,
- partial_result + include_ranges, find_all)))
- return [partial_result]
- else:
- result = []
- if exit_code_1 != 0:
- if first_half[1] == first_half[0] + 1:
- result.append(first_half[0])
- else:
- result.extend(find_failures(runner, first_half,
- include_ranges, find_all))
- if exit_code_2 != 0:
- if second_half[1] == second_half[0] + 1:
- result.append(second_half[0])
- else:
- result.extend(find_failures(runner, second_half,
- include_ranges, find_all))
- return result
-
-
-def main():
- '''
- Helper Script for Automating Bisection Debugging
-
- Example Invocation:
- bisection-tool.py --cmd 'bisection-test.py -c 2x3' --end 1000 --timeout 60
-
- This will invoke 'bisection-test.py -c 2x3' starting with the range -i 0:1000
- If that fails, it will subdivide the range (initially 0:500 and 500:1000)
- recursively to pinpoint a combination of singletons that are needed to cause
- the input to return a non zero exit code or timeout.
-
- For investigating an error in the generated code:
- bisection-tool.py --cmd './pydir/szbuild_spec2k.py --run 188.ammp'
-
- For Subzero itself crashing,
- bisection-tool.py --cmd 'pnacl-sz -translate-only=' --comma-join=1
- The --comma-join flag ensures the ranges are formatted in the manner pnacl-sz
- expects.
-
- If the range specification is not to be appended on the input:
- bisection-tool.py --cmd 'echo %i; cmd-main %i; cmd-post' --template=1
-
- '''
- argparser = argparse.ArgumentParser(main.__doc__)
- argparser.add_argument('--cmd', required=True, dest='cmd',
- help='Runnable command')
-
- argparser.add_argument('--start', dest='start', default=0,
- help='Start of initial range')
-
- argparser.add_argument('--end', dest='end', default=50000,
- help='End of initial range')
-
- argparser.add_argument('--timeout', dest='timeout', default=60,
- help='Timeout for each invocation of the input')
-
- argparser.add_argument('--all', type=int, choices=[0,1], default=1,
- dest='all', help='Find all failures')
-
- argparser.add_argument('--comma-join', type=int, choices=[0,1], default=0,
- dest='comma_join', help='Use comma to join ranges')
-
- argparser.add_argument('--template', type=int, choices=[0,1], default=0,
- dest='template',
- help='Replace %%i in the cmd string with the ranges')
-
-
- args = argparser.parse_args()
-
- fail_list = []
-
- initial_range = (int(args.start), int(args.end))
- timeout = int(args.timeout)
- runner = Runner(args.cmd, timeout, args.comma_join, args.template, args.all)
- if runner.Run([initial_range]) != 0:
- fail_list = find_failures(runner, initial_range, [], args.all)
- else:
- print 'Pass'
- # The whole input range works, maybe check subzero build flags?
- # Also consider widening the initial range (control with --start and --end)
-
- if fail_list:
- print 'Failing Items:'
- for fail in fail_list:
- if isinstance(fail, list):
- fail.sort()
- print '[' + ','.join(str(x) for x in fail) + ']'
- else:
- print fail
- print 'Number of tries: ' + str(runner._num_tries)
-
-if __name__ == '__main__':
- main()
diff --git a/third_party/subzero/pydir/build-pnacl-ir.py b/third_party/subzero/pydir/build-pnacl-ir.py
deleted file mode 100755
index 2ced17a..0000000
--- a/third_party/subzero/pydir/build-pnacl-ir.py
+++ /dev/null
@@ -1,47 +0,0 @@
-#!/usr/bin/env python2
-
-import argparse
-import errno
-import os
-import shutil
-import tempfile
-from utils import shellcmd
-from utils import FindBaseNaCl
-
-if __name__ == '__main__':
- argparser = argparse.ArgumentParser()
- argparser.add_argument('cfile', nargs='+', type=str,
- help='C file(s) to convert')
- argparser.add_argument('--dir', nargs='?', type=str, default='.',
- help='Output directory. Default "%(default)s".')
- argparser.add_argument('--disable-verify', action='store_true')
- args = argparser.parse_args()
-
- nacl_root = FindBaseNaCl()
- # Prepend bin to $PATH.
- os.environ['PATH'] = (
- nacl_root + '/toolchain/linux_x86/pnacl_newlib_raw/bin' + os.pathsep +
- os.pathsep + os.environ['PATH'])
-
- try:
- tempdir = tempfile.mkdtemp()
-
- for cname in args.cfile:
- basename = os.path.splitext(cname)[0]
- llname = os.path.join(tempdir, basename + '.ll')
- pnaclname = basename + '.pnacl.ll'
- pnaclname = os.path.join(args.dir, pnaclname)
-
- shellcmd('pnacl-clang -O2 -c {0} -o {1}'.format(cname, llname))
- shellcmd('pnacl-opt ' +
- '-pnacl-abi-simplify-preopt -pnacl-abi-simplify-postopt' +
- ('' if args.disable_verify else
- ' -verify-pnaclabi-module -verify-pnaclabi-functions') +
- ' -pnaclabi-allow-debug-metadata'
- ' {0} -S -o {1}'.format(llname, pnaclname))
- finally:
- try:
- shutil.rmtree(tempdir)
- except OSError as exc:
- if exc.errno != errno.ENOENT: # ENOENT - no such file or directory
- raise # re-raise exception
diff --git a/third_party/subzero/pydir/build-runtime.py b/third_party/subzero/pydir/build-runtime.py
deleted file mode 100755
index a351fd6..0000000
--- a/third_party/subzero/pydir/build-runtime.py
+++ /dev/null
@@ -1,232 +0,0 @@
-#!/usr/bin/env python2
-
-import argparse
-import os
-import shutil
-import tempfile
-
-import targets
-from utils import FindBaseNaCl, GetObjcopyCmd, shellcmd
-
-
-def Translate(ll_files, extra_args, obj, verbose, target):
- """Translate a set of input bitcode files into a single object file.
-
- Use pnacl-llc to translate textual bitcode input ll_files into object file
- obj, using extra_args as the architectural flags.
- """
- externalize = ['-externalize']
- shellcmd(['cat'] + ll_files + ['|',
- 'pnacl-llc',
- '-function-sections',
- '-O2',
- '-filetype=obj',
- '-bitcode-format=llvm',
- '-o', obj
- ] + extra_args + externalize, echo=verbose)
- localize_syms = ['nacl_tp_tdb_offset', 'nacl_tp_tls_offset']
-
- shellcmd([GetObjcopyCmd(target), obj] +
- [('--localize-symbol=' + sym) for sym in localize_syms])
-
-
-def PartialLink(obj_files, extra_args, lib, verbose):
- """Partially links a set of obj files into a final obj library."""
- shellcmd(['le32-nacl-ld',
- '-o', lib,
- '-r',
- ] + extra_args + obj_files, echo=verbose)
-
-
-def MakeRuntimesForTarget(target_info, ll_files,
- srcdir, tempdir, rtdir, verbose, excluded_targets):
- """Builds native, sandboxed, and nonsfi runtimes for the given target."""
- if target_info.target in excluded_targets:
- return
- # File-mangling helper functions.
- def TmpFile(template):
- return template.format(dir=tempdir, target=target_info.target)
- def OutFile(template):
- return template.format(rtdir=rtdir, target=target_info.target)
- # Helper function for building the native unsandboxed runtime.
- def MakeNativeRuntime():
- """Builds just the native runtime."""
- # Translate tempdir/szrt.ll and tempdir/szrt_ll.ll to
- # szrt_native_{target}.tmp.o.
- Translate(ll_files,
- ['-mtriple=' + target_info.triple] + target_info.llc_flags,
- TmpFile('{dir}/szrt_native_{target}.tmp.o'),
- verbose, target_info.target)
- # Compile srcdir/szrt_profiler.c to
- # tempdir/szrt_profiler_native_{target}.o.
- shellcmd(['clang',
- '-O2',
- '-target=' + target_info.triple,
- '-c',
- '{srcdir}/szrt_profiler.c'.format(srcdir=srcdir),
- '-o', TmpFile('{dir}/szrt_native_profiler_{target}.o')
- ], echo=verbose)
- # Assemble srcdir/szrt_asm_{target}.s to tempdir/szrt_asm_{target}.o.
- shellcmd(['llvm-mc',
- '-triple=' + target_info.triple, '--defsym NATIVE=1',
- '-filetype=obj',
- '-o', TmpFile('{dir}/szrt_native_asm_{target}.o'),
- '{srcdir}/szrt_asm_{target}.s'.format(
- srcdir=srcdir, target=target_info.target)
- ], echo=verbose)
- # Write full szrt_native_{target}.o.
- PartialLink([TmpFile('{dir}/szrt_native_{target}.tmp.o'),
- TmpFile('{dir}/szrt_native_asm_{target}.o'),
- TmpFile('{dir}/szrt_native_profiler_{target}.o')],
- ['-m {ld_emu}'.format(ld_emu=target_info.ld_emu)],
- OutFile('{rtdir}/szrt_native_{target}.o'),
- verbose)
- shellcmd([GetObjcopyCmd(target_info.target),
- '--strip-symbol=NATIVE',
- OutFile('{rtdir}/szrt_native_{target}.o')])
- # Compile srcdir/szrt_asan.c to szrt_asan_{target}.o
- shellcmd(['clang',
- '-O2',
- '-target=' + target_info.triple,
- '-c',
- '{srcdir}/szrt_asan.c'.format(srcdir=srcdir),
- '-o', OutFile('{rtdir}/szrt_asan_{target}.o')
- ], echo=verbose)
-
- # Helper function for building the sandboxed runtime.
- def MakeSandboxedRuntime():
- """Builds just the sandboxed runtime."""
- # Translate tempdir/szrt.ll and tempdir/szrt_ll.ll to szrt_sb_{target}.o.
- # The sandboxed library does not get the profiler helper function as the
- # binaries are linked with -nostdlib.
- Translate(ll_files,
- ['-mtriple=' + targets.ConvertTripleToNaCl(target_info.triple)] +
- target_info.llc_flags,
- TmpFile('{dir}/szrt_sb_{target}.tmp.o'),
- verbose,target_info.target)
- # Assemble srcdir/szrt_asm_{target}.s to tempdir/szrt_asm_{target}.o.
- shellcmd(['llvm-mc',
- '-triple=' + targets.ConvertTripleToNaCl(target_info.triple),
- '--defsym NACL=1',
- '-filetype=obj',
- '-o', TmpFile('{dir}/szrt_sb_asm_{target}.o'),
- '{srcdir}/szrt_asm_{target}.s'.format(
- srcdir=srcdir, target=target_info.target)
- ], echo=verbose)
- PartialLink([TmpFile('{dir}/szrt_sb_{target}.tmp.o'),
- TmpFile('{dir}/szrt_sb_asm_{target}.o')],
- ['-m {ld_emu}'.format(ld_emu=target_info.sb_emu)],
- OutFile('{rtdir}/szrt_sb_{target}.o'),
- verbose)
- shellcmd([GetObjcopyCmd(target_info.target),
- '--strip-symbol=NACL',
- OutFile('{rtdir}/szrt_sb_{target}.o')])
-
- # Helper function for building the Non-SFI runtime.
- def MakeNonsfiRuntime():
- """Builds just the nonsfi runtime."""
- # Translate tempdir/szrt.ll and tempdir/szrt_ll.ll to
- # szrt_nonsfi_{target}.tmp.o.
- Translate(ll_files,
- ['-mtriple=' + target_info.triple] + target_info.llc_flags +
- ['-relocation-model=pic', '-force-tls-non-pic', '-malign-double'],
- TmpFile('{dir}/szrt_nonsfi_{target}.tmp.o'),
- verbose, target_info.target)
- # Assemble srcdir/szrt_asm_{target}.s to tempdir/szrt_asm_{target}.o.
- shellcmd(['llvm-mc',
- '-triple=' + target_info.triple, '--defsym NONSFI=1',
- '-filetype=obj',
- '-o', TmpFile('{dir}/szrt_nonsfi_asm_{target}.o'),
- '{srcdir}/szrt_asm_{target}.s'.format(
- srcdir=srcdir, target=target_info.target)
- ], echo=verbose)
- # Write full szrt_nonsfi_{target}.o.
- PartialLink([TmpFile('{dir}/szrt_nonsfi_{target}.tmp.o'),
- TmpFile('{dir}/szrt_nonsfi_asm_{target}.o')],
- ['-m {ld_emu}'.format(ld_emu=target_info.ld_emu)],
- OutFile('{rtdir}/szrt_nonsfi_{target}.o'),
- verbose)
- shellcmd([GetObjcopyCmd(target_info.target),
- '--strip-symbol=NONSFI',
- OutFile('{rtdir}/szrt_nonsfi_{target}.o')])
-
-
- # Run the helper functions.
- MakeNativeRuntime()
- MakeSandboxedRuntime()
- MakeNonsfiRuntime()
-
-
-def main():
- """Build the Subzero runtime support library for all architectures.
- """
- nacl_root = FindBaseNaCl()
- argparser = argparse.ArgumentParser(
- description=' ' + main.__doc__,
- formatter_class=argparse.RawTextHelpFormatter)
- argparser.add_argument('--verbose', '-v', dest='verbose',
- action='store_true',
- help='Display some extra debugging output')
- argparser.add_argument('--pnacl-root', dest='pnacl_root',
- default=(
- '{root}/toolchain/linux_x86/pnacl_newlib_raw'
- ).format(root=nacl_root),
- help='Path to PNaCl toolchain binaries.')
- argparser.add_argument('--exclude-target', dest='excluded_targets',
- default=[], action='append',
- help='Target whose runtime should not be built')
- args = argparser.parse_args()
- os.environ['PATH'] = ('{root}/bin{sep}{path}'
- ).format(root=args.pnacl_root, sep=os.pathsep, path=os.environ['PATH'])
- srcdir = (
- '{root}/toolchain_build/src/subzero/runtime'
- ).format(root=nacl_root)
- rtdir = (
- '{root}/toolchain_build/src/subzero/build/runtime'
- ).format(root=nacl_root)
- try:
- tempdir = tempfile.mkdtemp()
- if os.path.exists(rtdir) and not os.path.isdir(rtdir):
- os.remove(rtdir)
- if not os.path.exists(rtdir):
- os.makedirs(rtdir)
- # Compile srcdir/szrt.c to tempdir/szrt.ll
- shellcmd(['pnacl-clang',
- '-O2',
- '-c',
- '{srcdir}/szrt.c'.format(srcdir=srcdir),
- '-o', '{dir}/szrt.tmp.bc'.format(dir=tempdir)
- ], echo=args.verbose)
- shellcmd(['pnacl-opt',
- '-pnacl-abi-simplify-preopt',
- '-pnacl-abi-simplify-postopt',
- '-pnaclabi-allow-debug-metadata',
- '{dir}/szrt.tmp.bc'.format(dir=tempdir),
- '-S',
- '-o', '{dir}/szrt.ll'.format(dir=tempdir)
- ], echo=args.verbose)
- ll_files = ['{dir}/szrt.ll'.format(dir=tempdir),
- '{srcdir}/szrt_ll.ll'.format(srcdir=srcdir)]
-
- MakeRuntimesForTarget(targets.X8632Target, ll_files,
- srcdir, tempdir, rtdir, args.verbose,
- args.excluded_targets)
- MakeRuntimesForTarget(targets.X8664Target, ll_files,
- srcdir, tempdir, rtdir, args.verbose,
- args.excluded_targets)
- MakeRuntimesForTarget(targets.ARM32Target, ll_files,
- srcdir, tempdir, rtdir, args.verbose,
- args.excluded_targets)
- MakeRuntimesForTarget(targets.MIPS32Target, ll_files,
- srcdir, tempdir, rtdir, args.verbose,
- args.excluded_targets)
-
- finally:
- try:
- shutil.rmtree(tempdir)
- except OSError as exc:
- if exc.errno != errno.ENOENT: # ENOENT - no such file or directory
- raise # re-raise exception
-
-if __name__ == '__main__':
- main()
diff --git a/third_party/subzero/pydir/crosstest.py b/third_party/subzero/pydir/crosstest.py
deleted file mode 100755
index 6f8ed57..0000000
--- a/third_party/subzero/pydir/crosstest.py
+++ /dev/null
@@ -1,281 +0,0 @@
-#!/usr/bin/env python2
-
-import argparse
-import os
-import subprocess
-import sys
-import tempfile
-
-import targets
-from szbuild import LinkNonsfi
-from utils import FindBaseNaCl, GetObjcopyCmd, get_sfi_string, shellcmd
-
-def main():
- """Builds a cross-test binary for comparing Subzero and llc translation.
-
- Each --test argument is compiled once by llc and once by Subzero. C/C++
- tests are first compiled down to PNaCl bitcode using pnacl-clang and
- pnacl-opt. The --prefix argument ensures that symbol names are different
- between the two object files, to avoid linking errors.
-
- There is also a --driver argument that specifies the C/C++ file that calls
- the test functions with a variety of interesting inputs and compares their
- results.
-
- """
- # arch_map maps a Subzero target string to TargetInfo (e.g., triple).
- arch_map = { 'x8632': targets.X8632Target,
- 'x8664': targets.X8664Target,
- 'arm32': targets.ARM32Target,
- 'mips32': targets.MIPS32Target}
- arch_sz_flags = { 'x8632': [],
- 'x8664': [],
- # For ARM, test a large stack offset as well. +/- 4095 is
- # the limit, so test somewhere near that boundary.
- 'arm32': ['--test-stack-extra', '4084'],
- 'mips32': ['--test-stack-extra', '4084']
- }
- arch_llc_flags_extra = {
- # Use sse2 instructions regardless of input -mattr
- # argument to avoid differences in (undefined) behavior of
- # converting NaN to int.
- 'x8632': ['-mattr=sse2'],
- 'x8664': ['-mattr=sse2'],
- 'arm32': [],
- 'mips32':[],
- }
- desc = 'Build a cross-test that compares Subzero and llc translation.'
- argparser = argparse.ArgumentParser(description=desc)
- argparser.add_argument('--test', required=True, action='append',
- metavar='TESTFILE_LIST',
- help='List of C/C++/.ll files with test functions')
- argparser.add_argument('--driver', required=True,
- metavar='DRIVER',
- help='Driver program')
- argparser.add_argument('--target', required=False, default='x8632',
- choices=arch_map.keys(),
- metavar='TARGET',
- help='Translation target architecture.' +
- ' Default %(default)s.')
- argparser.add_argument('-O', required=False, default='2', dest='optlevel',
- choices=['m1', '-1', '0', '1', '2'],
- metavar='OPTLEVEL',
- help='Optimization level for llc and Subzero ' +
- '(m1 and -1 are equivalent).' +
- ' Default %(default)s.')
- argparser.add_argument('--clang-opt', required=False, default=True,
- dest='clang_opt')
- argparser.add_argument('--mattr', required=False, default='sse2',
- dest='attr', choices=['sse2', 'sse4.1',
- 'neon', 'hwdiv-arm',
- 'base'],
- metavar='ATTRIBUTE',
- help='Target attribute. Default %(default)s.')
- argparser.add_argument('--sandbox', required=False, default=0, type=int,
- dest='sandbox',
- help='Use sandboxing. Default "%(default)s".')
- argparser.add_argument('--nonsfi', required=False, default=0, type=int,
- dest='nonsfi',
- help='Use Non-SFI mode. Default "%(default)s".')
- argparser.add_argument('--prefix', required=True,
- metavar='SZ_PREFIX',
- help='String prepended to Subzero symbol names')
- argparser.add_argument('--output', '-o', required=True,
- metavar='EXECUTABLE',
- help='Executable to produce')
- argparser.add_argument('--dir', required=False, default='.',
- metavar='OUTPUT_DIR',
- help='Output directory for all files.' +
- ' Default "%(default)s".')
- argparser.add_argument('--filetype', default='obj', dest='filetype',
- choices=['obj', 'asm', 'iasm'],
- help='Output file type. Default %(default)s.')
- argparser.add_argument('--sz', dest='sz_args', action='append', default=[],
- help='Extra arguments to pass to pnacl-sz.')
- args = argparser.parse_args()
-
- nacl_root = FindBaseNaCl()
- bindir = ('{root}/toolchain/linux_x86/pnacl_newlib_raw/bin'
- .format(root=nacl_root))
- target_info = arch_map[args.target]
- triple = target_info.triple
- if args.sandbox:
- triple = targets.ConvertTripleToNaCl(triple)
- llc_flags = target_info.llc_flags + arch_llc_flags_extra[args.target]
- if args.nonsfi:
- llc_flags.extend(['-relocation-model=pic',
- '-malign-double',
- '-force-tls-non-pic',
- '-mtls-use-call'])
- mypath = os.path.abspath(os.path.dirname(sys.argv[0]))
-
- # Construct a "unique key" for each test so that tests can be run in
- # parallel without race conditions on temporary file creation.
- key = '{sb}.O{opt}.{attr}.{target}'.format(
- target=args.target,
- sb=get_sfi_string(args, 'sb', 'nonsfi', 'nat'),
- opt=args.optlevel, attr=args.attr)
- objs = []
- for arg in args.test:
- base, ext = os.path.splitext(arg)
- if ext == '.ll':
- bitcode = arg
- else:
- # Use pnacl-clang and pnacl-opt to produce PNaCl bitcode.
- bitcode_nonfinal = os.path.join(args.dir, base + '.' + key + '.bc')
- bitcode = os.path.join(args.dir, base + '.' + key + '.pnacl.ll')
- shellcmd(['{bin}/pnacl-clang'.format(bin=bindir),
- ('-O2' if args.clang_opt else '-O0'),
- ('-DARM32' if args.target == 'arm32' else ''), '-c', arg,
- ('-DMIPS32' if args.target == 'mips32' else ''),
- '-o', bitcode_nonfinal])
- shellcmd(['{bin}/pnacl-opt'.format(bin=bindir),
- '-pnacl-abi-simplify-preopt',
- '-pnacl-abi-simplify-postopt',
- '-pnaclabi-allow-debug-metadata',
- '-strip-metadata',
- '-strip-module-flags',
- '-strip-debug',
- bitcode_nonfinal, '-S', '-o', bitcode])
-
- base_sz = '{base}.{key}'.format(base=base, key=key)
- asm_sz = os.path.join(args.dir, base_sz + '.sz.s')
- obj_sz = os.path.join(args.dir, base_sz + '.sz.o')
- obj_llc = os.path.join(args.dir, base_sz + '.llc.o')
-
- shellcmd(['{path}/pnacl-sz'.format(path=os.path.dirname(mypath)),
- ] + args.sz_args + [
- '-O' + args.optlevel,
- '-mattr=' + args.attr,
- '--target=' + args.target,
- '--sandbox=' + str(args.sandbox),
- '--nonsfi=' + str(args.nonsfi),
- '--prefix=' + args.prefix,
- '-allow-uninitialized-globals',
- '-externalize',
- '-filetype=' + args.filetype,
- '-o=' + (obj_sz if args.filetype == 'obj' else asm_sz),
- bitcode] + arch_sz_flags[args.target])
- if args.filetype != 'obj':
- shellcmd(['{bin}/llvm-mc'.format(bin=bindir),
- '-triple=' + ('mipsel-linux-gnu'
- if args.target == 'mips32' and args.sandbox
- else triple),
- '-filetype=obj',
- '-o=' + obj_sz,
- asm_sz])
-
- # Each separately translated Subzero object file contains its own
- # definition of the __Sz_block_profile_info profiling symbol. Avoid
- # linker errors (multiply defined symbol) by making all copies weak.
- # (This could also be done by Subzero if it supported weak symbol
- # definitions.) This approach should be OK because cross tests are
- # currently the only situation where multiple translated files are
- # linked into the executable, but when PNaCl supports shared nexe
- # libraries, this would need to change. (Note: the same issue applies
- # to the __Sz_revision symbol.)
- shellcmd(['{bin}/{objcopy}'.format(bin=bindir,
- objcopy=GetObjcopyCmd(args.target)),
- '--weaken-symbol=__Sz_block_profile_info',
- '--weaken-symbol=__Sz_revision',
- '--strip-symbol=nacl_tp_tdb_offset',
- '--strip-symbol=nacl_tp_tls_offset',
- obj_sz])
- objs.append(obj_sz)
- shellcmd(['{bin}/pnacl-llc'.format(bin=bindir),
- '-mtriple=' + triple,
- '-externalize',
- '-filetype=obj',
- '-bitcode-format=llvm',
- '-o=' + obj_llc,
- bitcode] + llc_flags)
- strip_syms = [] if args.target == 'mips32' else ['nacl_tp_tdb_offset',
- 'nacl_tp_tls_offset']
- shellcmd(['{bin}/{objcopy}'.format(bin=bindir,
- objcopy=GetObjcopyCmd(args.target)),
- obj_llc] +
- [('--strip-symbol=' + sym) for sym in strip_syms])
- objs.append(obj_llc)
-
- # Add szrt_sb_${target}.o or szrt_native_${target}.o.
- if not args.nonsfi:
- objs.append((
- '{root}/toolchain_build/src/subzero/build/runtime/' +
- 'szrt_{sb}_' + args.target + '.o'
- ).format(root=nacl_root,
- sb=get_sfi_string(args, 'sb', 'nonsfi', 'native')))
-
- target_params = []
-
- if args.target == 'arm32':
- target_params.append('-DARM32')
- target_params.append('-static')
-
- if args.target == 'mips32':
- target_params.append('-DMIPS32')
-
- pure_c = os.path.splitext(args.driver)[1] == '.c'
- if not args.nonsfi:
- # Set compiler to clang, clang++, pnacl-clang, or pnacl-clang++.
- compiler = '{bin}/{prefix}{cc}'.format(
- bin=bindir, prefix=get_sfi_string(args, 'pnacl-', '', ''),
- cc='clang' if pure_c else 'clang++')
- sb_native_args = (['-O0', '--pnacl-allow-native',
- '-arch', target_info.compiler_arch,
- '-Wn,-defsym=__Sz_AbsoluteZero=0']
- if args.sandbox else
- ['-g', '-target=' + triple,
- '-lm', '-lpthread',
- '-Wl,--defsym=__Sz_AbsoluteZero=0'] +
- target_info.cross_headers)
- shellcmd([compiler] + target_params + [args.driver] + objs +
- ['-o', os.path.join(args.dir, args.output)] + sb_native_args)
- return 0
-
- base, ext = os.path.splitext(args.driver)
- bitcode_nonfinal = os.path.join(args.dir, base + '.' + key + '.bc')
- bitcode = os.path.join(args.dir, base + '.' + key + '.pnacl.ll')
- asm_sz = os.path.join(args.dir, base + '.' + key + '.s')
- obj_llc = os.path.join(args.dir, base + '.' + key + '.o')
- compiler = '{bin}/{prefix}{cc}'.format(
- bin=bindir, prefix='pnacl-',
- cc='clang' if pure_c else 'clang++')
- shellcmd([compiler] + target_params + [
- args.driver,
- '-O2',
- '-o', bitcode_nonfinal,
- '-Wl,-r'
- ])
- shellcmd(['{bin}/pnacl-opt'.format(bin=bindir),
- '-pnacl-abi-simplify-preopt',
- '-pnacl-abi-simplify-postopt',
- '-pnaclabi-allow-debug-metadata',
- '-strip-metadata',
- '-strip-module-flags',
- '-strip-debug',
- '-disable-opt',
- bitcode_nonfinal, '-S', '-o', bitcode])
- shellcmd(['{bin}/pnacl-llc'.format(bin=bindir),
- '-mtriple=' + triple,
- '-externalize',
- '-filetype=obj',
- '-O2',
- '-bitcode-format=llvm',
- '-o', obj_llc,
- bitcode] + llc_flags)
- if not args.sandbox and not args.nonsfi:
- shellcmd(['{bin}/{objcopy}'.format(bin=bindir,
- objcopy=GetObjcopyCmd(args.target)),
- '--redefine-sym', '_start=_user_start',
- obj_llc
- ])
- objs.append(obj_llc)
- if args.nonsfi:
- LinkNonsfi(objs, os.path.join(args.dir, args.output), args.target)
- elif args.sandbox:
- LinkSandbox(objs, os.path.join(args.dir, args.output), args.target)
- else:
- LinkNative(objs, os.path.join(args.dir, args.output), args.target)
-
-if __name__ == '__main__':
- main()
diff --git a/third_party/subzero/pydir/crosstest_generator.py b/third_party/subzero/pydir/crosstest_generator.py
deleted file mode 100755
index d2e5652..0000000
--- a/third_party/subzero/pydir/crosstest_generator.py
+++ /dev/null
@@ -1,234 +0,0 @@
-#!/usr/bin/env python2
-
-import argparse
-import collections
-import ConfigParser
-import os
-import shutil
-import sys
-
-from utils import shellcmd
-from utils import FindBaseNaCl
-
-def Match(desc, includes, excludes, default_match):
- """Determines whether desc is a match against includes and excludes.
-
- 'desc' is a set of attributes, and 'includes' and 'excludes' are lists of sets
- of attributes.
-
- If 'desc' matches any element from 'excludes', the result is False.
- Otherwise, if 'desc' matches any element from 'includes', the result is True.
- Otherwise, the 'default_match' value is returned.
- """
- for exclude in excludes:
- if exclude <= desc:
- return False
- for include in includes:
- if include <= desc:
- return True
- return default_match
-
-
-def RunNativePrefix(toolchain_root, target, attr, run_cmd):
- """Returns a prefix for running an executable for the target.
-
- For example, we may be running an ARM or MIPS target executable on an
- x86 machine and need to use an emulator.
- """
- arch_map = { 'x8632' : '',
- 'x8664' : '',
- 'arm32' : os.path.join(toolchain_root, 'arm_trusted',
- 'run_under_qemu_arm'),
- 'mips32': os.path.join(toolchain_root, 'mips_trusted',
- 'run_under_qemu_mips32'),
- }
- attr_map = collections.defaultdict(str, {
- 'arm32-neon': ' -cpu cortex-a9',
- 'arm32-hwdiv-arm': ' -cpu cortex-a15',
- 'mips32-base': ' -cpu mips32r5-generic'})
- prefix = arch_map[target] + attr_map[target + '-' + attr]
- if target == 'mips32':
- prefix = 'QEMU_SET_ENV=LD_LIBRARY_PATH=/usr/mipsel-linux-gnu/lib/ ' + prefix
- return (prefix + ' ' + run_cmd) if prefix else run_cmd
-
-def NonsfiLoaderArch(target):
- """Returns the arch for the nonsfi_loader"""
- arch_map = { 'arm32' : 'arm',
- 'x8632' : 'x86-32',
- 'mips32' : 'mips32',
- }
- return arch_map[target]
-
-
-def main():
- """Framework for cross test generation and execution.
-
- Builds and executes cross tests from the space of all possible attribute
- combinations. The space can be restricted by providing subsets of attributes
- to specifically include or exclude.
- """
- # pypath is where to find other Subzero python scripts.
- pypath = os.path.abspath(os.path.dirname(sys.argv[0]))
- root = FindBaseNaCl()
-
- # The rest of the attribute sets.
- targets = [ 'x8632', 'x8664', 'arm32', 'mips32' ]
- sandboxing = [ 'native', 'sandbox', 'nonsfi' ]
- opt_levels = [ 'Om1', 'O2' ]
- arch_attrs = { 'x8632': [ 'sse2', 'sse4.1' ],
- 'x8664': [ 'sse2', 'sse4.1' ],
- 'arm32': [ 'neon', 'hwdiv-arm' ],
- 'mips32': [ 'base' ]
- }
- flat_attrs = []
- for v in arch_attrs.values():
- flat_attrs += v
- arch_flags = { 'x8632': [],
- 'x8664': [],
- 'arm32': [],
- 'mips32': []
- }
- # all_keys is only used in the help text.
- all_keys = '; '.join([' '.join(targets), ' '.join(sandboxing),
- ' '.join(opt_levels), ' '.join(flat_attrs)])
-
- argparser = argparse.ArgumentParser(
- description=' ' + main.__doc__ +
- 'The set of attributes is the set of tests plus the following:\n' +
- all_keys, formatter_class=argparse.RawTextHelpFormatter)
- argparser.add_argument('--config', default='crosstest.cfg', dest='config',
- metavar='FILE', help='Test configuration file')
- argparser.add_argument('--print-tests', default=False, action='store_true',
- help='Print the set of test names and exit')
- argparser.add_argument('--include', '-i', default=[], dest='include',
- action='append', metavar='ATTR_LIST',
- help='Attributes to include (comma-separated). ' +
- 'Can be used multiple times.')
- argparser.add_argument('--exclude', '-e', default=[], dest='exclude',
- action='append', metavar='ATTR_LIST',
- help='Attributes to include (comma-separated). ' +
- 'Can be used multiple times.')
- argparser.add_argument('--verbose', '-v', default=False, action='store_true',
- help='Use verbose output')
- argparser.add_argument('--defer', default=False, action='store_true',
- help='Defer execution until all executables are built')
- argparser.add_argument('--no-compile', '-n', default=False,
- action='store_true',
- help="Don't build; reuse binaries from the last run")
- argparser.add_argument('--dir', dest='dir', metavar='DIRECTORY',
- default=('{root}/toolchain_build/src/subzero/' +
- 'crosstest/Output').format(root=root),
- help='Output directory')
- argparser.add_argument('--lit', default=False, action='store_true',
- help='Generate files for lit testing')
- argparser.add_argument('--toolchain-root', dest='toolchain_root',
- default=(
- '{root}/toolchain/linux_x86/pnacl_newlib_raw/bin'
- ).format(root=root),
- help='Path to toolchain binaries.')
- argparser.add_argument('--filetype', default=None, dest='filetype',
- help='File type override, one of {asm, iasm, obj}.')
- args = argparser.parse_args()
-
- # Run from the crosstest directory to make it easy to grab inputs.
- crosstest_dir = '{root}/toolchain_build/src/subzero/crosstest'.format(
- root=root)
- os.chdir(crosstest_dir)
-
- tests = ConfigParser.RawConfigParser()
- tests.read('crosstest.cfg')
-
- if args.print_tests:
- print 'Test name attributes: ' + ' '.join(sorted(tests.sections()))
- sys.exit(0)
-
- # includes and excludes are both lists of sets.
- includes = [ set(item.split(',')) for item in args.include ]
- excludes = [ set(item.split(',')) for item in args.exclude ]
- # If any --include args are provided, the default is to not match.
- default_match = not args.include
-
- # Delete and recreate the output directory, unless --no-compile was specified.
- if not args.no_compile:
- if os.path.exists(args.dir):
- if os.path.isdir(args.dir):
- shutil.rmtree(args.dir)
- else:
- os.remove(args.dir)
- if not os.path.exists(args.dir):
- os.makedirs(args.dir)
-
- # If --defer is specified, collect the run commands into deferred_cmds for
- # later execution.
- deferred_cmds = []
- for test in sorted(tests.sections()):
- for target in targets:
- for sb in sandboxing:
- for opt in opt_levels:
- for attr in arch_attrs[target]:
- desc = [ test, target, sb, opt, attr ]
- if Match(set(desc), includes, excludes, default_match):
- exe = '{test}_{target}_{sb}_{opt}_{attr}'.format(
- test=test, target=target, sb=sb, opt=opt,
- attr=attr)
- extra = (tests.get(test, 'flags').split(' ')
- if tests.has_option(test, 'flags') else [])
- if args.filetype:
- extra += ['--filetype={ftype}'.format(ftype=args.filetype)]
- # Generate the compile command.
- cmp_cmd = (
- ['{path}/crosstest.py'.format(path=pypath),
- '-{opt}'.format(opt=opt),
- '--mattr={attr}'.format(attr=attr),
- '--prefix=Subzero_',
- '--target={target}'.format(target=target),
- '--nonsfi={nsfi}'.format(nsfi='1' if sb=='nonsfi' else '0'),
- '--sandbox={sb}'.format(sb='1' if sb=='sandbox' else '0'),
- '--dir={dir}'.format(dir=args.dir),
- '--output={exe}'.format(exe=exe),
- '--driver={drv}'.format(drv=tests.get(test, 'driver'))] +
- extra +
- ['--test=' + t
- for t in tests.get(test, 'test').split(' ')] +
- arch_flags[target])
- run_cmd_base = os.path.join(args.dir, exe)
- # Generate the run command.
- run_cmd = run_cmd_base
- if sb == 'sandbox':
- run_cmd = '{root}/run.py -q '.format(root=root) + run_cmd
- elif sb == 'nonsfi':
- run_cmd = (
- '{root}/scons-out/opt-linux-{arch}/obj/src/nonsfi/' +
- 'loader/nonsfi_loader ').format(
- root=root, arch=NonsfiLoaderArch(target)) + run_cmd
- run_cmd = RunNativePrefix(args.toolchain_root, target, attr,
- run_cmd)
- else:
- run_cmd = RunNativePrefix(args.toolchain_root, target, attr,
- run_cmd)
- if args.lit:
- # Create a file to drive the lit test.
- with open(run_cmd_base + '.xtest', 'w') as f:
- f.write('# RUN: sh %s | FileCheck %s\n')
- f.write('cd ' + crosstest_dir + ' && \\\n')
- f.write(' '.join(cmp_cmd) + ' && \\\n')
- f.write(run_cmd + '\n')
- f.write('echo Recreate a failure using ' + __file__ +
- ' --toolchain-root=' + args.toolchain_root +
- (' --filetype=' + args.filetype
- if args.filetype else '') +
- ' --include=' + ','.join(desc) + '\n')
- f.write('# CHECK: Failures=0\n')
- else:
- if not args.no_compile:
- shellcmd(cmp_cmd,
- echo=args.verbose)
- if (args.defer):
- deferred_cmds.append(run_cmd)
- else:
- shellcmd(run_cmd, echo=True)
- for run_cmd in deferred_cmds:
- shellcmd(run_cmd, echo=True)
-
-if __name__ == '__main__':
- main()
diff --git a/third_party/subzero/pydir/gen_arm32_reg_tables.py b/third_party/subzero/pydir/gen_arm32_reg_tables.py
deleted file mode 100644
index 40b61e5..0000000
--- a/third_party/subzero/pydir/gen_arm32_reg_tables.py
+++ /dev/null
@@ -1,229 +0,0 @@
-import os
-import sys
-
-class RegAliases(object):
- def __init__(self, AliasesStr):
- self.Aliases = list(Alias.strip() for Alias in AliasesStr.split(','))
-
- def __str__(self):
- return 'REGLIST{AliasCount}(RegARM32, {Aliases})'.format(
- AliasCount=len(self.Aliases), Aliases=', '.join(self.Aliases))
-
-def _ArgumentNames(Method):
- import inspect
- return (ArgName for ArgName in inspect.getargspec(Method).args
- if ArgName != 'self')
-
-class RegFeatures(object):
- def __init__(self, AsmStr=None, CCArg=0, IsScratch=0, IsPreserved=0,
- IsStackPtr=0, IsFramePtr=0, IsGPR=0, IsInt=0, IsI64Pair=0,
- IsFP32=0, IsFP64=0, IsVec128=0, Aliases=None):
- assert (not IsInt) or IsGPR
- assert (not IsI64Pair) or (not IsGPR)
- assert not (IsInt and IsI64Pair)
- assert not (IsFP32 and IsFP64)
- assert not (IsFP32 and IsVec128)
- assert not (IsFP64 and IsVec128)
- assert not ((IsGPR) and (IsFP32 or IsFP64 or IsVec128))
- assert (not IsFramePtr) or IsGPR
- assert (not IsStackPtr) or IsGPR
- assert not (IsScratch and IsPreserved)
- self.Features = [x for x in _ArgumentNames(self.__init__)]
- self.FeaturesDict = {}
- # The argument Aliases is a string with the register aliasing information.
- # The next line convert it to a RegAlias object, for pretty printing.
- Aliases = RegAliases(Aliases)
- AsmStr = '"%s"' % AsmStr
- for Feature in self.Features:
- self.FeaturesDict[Feature] = locals()[Feature]
-
- def __str__(self):
- return '%s' % (', '.join(str(self.FeaturesDict[Feature]) for
- Feature in self.Features))
-
- def Aliases(self):
- return self.FeaturesDict['Aliases']
-
- def LivesInGPR(self):
- return (any(self.FeaturesDict[IntFeature] for IntFeature in (
- 'IsInt', 'IsI64Pair', 'IsStackPtr', 'IsFramePtr')) or
- not self.LivesInVFP())
-
- def LivesInVFP(self):
- return any(self.FeaturesDict[FpFeature] for FpFeature in (
- 'IsFP32', 'IsFP64', 'IsVec128'))
-
- def DefiningXMacro(self, OtherFeatures):
- return 'define X({parameters})'.format(
- parameters=', '.join(OtherFeatures + self.Features))
-
-class Reg(object):
- def __init__(self, Name, Encode, AsmStr=None, **Features):
- self.Name = Name
- self.Encode = Encode
- if not AsmStr:
- AsmStr = '%s' % Name
- self.Features = RegFeatures(AsmStr=AsmStr, **Features)
-
- def __str__(self):
- return 'Reg_{Name}, {Encode}, {Features}'.format(Name=self.Name,
- Encode=self.Encode, Features=self.Features)
-
- def IsAnAliasOf(self, Other):
- return Other.Name in self.Features.Aliases().Aliases
-
- def DefiningXMacro(self):
- return self.Features.DefiningXMacro(['Tag', 'Encoding'])
-
-# Note: The following tables break the usual 80-col on purpose -- it is easier
-# to read the register tables if each register entry is contained on a single
-# line.
-GPRs = [
- Reg( 'r0', 0, IsScratch=1, CCArg=1, IsGPR = 1, IsInt=1, Aliases= 'r0, r0r1'),
- Reg( 'r1', 1, IsScratch=1, CCArg=2, IsGPR = 1, IsInt=1, Aliases= 'r1, r0r1'),
- Reg( 'r2', 2, IsScratch=1, CCArg=3, IsGPR = 1, IsInt=1, Aliases= 'r2, r2r3'),
- Reg( 'r3', 3, IsScratch=1, CCArg=4, IsGPR = 1, IsInt=1, Aliases= 'r3, r2r3'),
- Reg( 'r4', 4, IsPreserved=1, IsGPR = 1, IsInt=1, Aliases= 'r4, r4r5'),
- Reg( 'r5', 5, IsPreserved=1, IsGPR = 1, IsInt=1, Aliases= 'r5, r4r5'),
- Reg( 'r6', 6, IsPreserved=1, IsGPR = 1, IsInt=1, Aliases= 'r6, r6r7'),
- Reg( 'r7', 7, IsPreserved=1, IsGPR = 1, IsInt=1, Aliases= 'r7, r6r7'),
- Reg( 'r8', 8, IsPreserved=1, IsGPR = 1, IsInt=1, Aliases= 'r8, r8r9'),
- Reg( 'r9', 9, IsPreserved=1, IsGPR = 1, IsInt=0, Aliases= 'r9, r8r9'),
- Reg('r10', 10, IsPreserved=1, IsGPR = 1, IsInt=1, Aliases='r10, r10fp'),
- Reg( 'fp', 11, IsPreserved=1, IsGPR = 1, IsInt=1, IsFramePtr=1, Aliases= 'fp, r10fp'),
- Reg( 'ip', 12, IsScratch=1, IsGPR = 1, IsInt=0, Aliases= 'ip'),
- Reg( 'sp', 13, IsScratch=0, IsGPR = 1, IsInt=0, IsStackPtr=1, Aliases= 'sp'),
- Reg( 'lr', 14, IsScratch=0, IsGPR = 1, IsInt=0, Aliases= 'lr'),
- Reg( 'pc', 15, IsScratch=0, IsGPR = 1, IsInt=0, Aliases= 'pc'),
-]
-
-I64Pairs = [
- Reg( 'r0r1', 0, AsmStr= 'r0, r1', IsScratch=1, CCArg=1, IsI64Pair=1, Aliases= 'r0r1, r0, r1'),
- Reg( 'r2r3', 2, AsmStr= 'r2, r3', IsScratch=1, CCArg=2, IsI64Pair=1, Aliases= 'r2r3, r2, r3'),
- Reg( 'r4r5', 4, AsmStr= 'r4, r5', IsPreserved=1, IsI64Pair=1, Aliases= 'r4r5, r4, r5'),
- Reg( 'r6r7', 6, AsmStr= 'r6, r7', IsPreserved=1, IsI64Pair=1, Aliases= 'r6r7, r6, r7'),
- Reg( 'r8r9', 8, AsmStr= 'r8, r9', IsPreserved=1, IsI64Pair=0, Aliases= 'r8r9, r8, r9'),
- Reg('r10fp', 10, AsmStr='r10, fp', IsPreserved=1, IsI64Pair=0, Aliases='r10fp, r10, fp'),
-]
-
-FP32 = [
- Reg( 's0', 0, IsScratch=1, CCArg=1, IsFP32=1, Aliases= 's0, d0 , q0'),
- Reg( 's1', 1, IsScratch=1, CCArg=2, IsFP32=1, Aliases= 's1, d0 , q0'),
- Reg( 's2', 2, IsScratch=1, CCArg=3, IsFP32=1, Aliases= 's2, d1 , q0'),
- Reg( 's3', 3, IsScratch=1, CCArg=4, IsFP32=1, Aliases= 's3, d1 , q0'),
- Reg( 's4', 4, IsScratch=1, CCArg=5, IsFP32=1, Aliases= 's4, d2 , q1'),
- Reg( 's5', 5, IsScratch=1, CCArg=6, IsFP32=1, Aliases= 's5, d2 , q1'),
- Reg( 's6', 6, IsScratch=1, CCArg=7, IsFP32=1, Aliases= 's6, d3 , q1'),
- Reg( 's7', 7, IsScratch=1, CCArg=8, IsFP32=1, Aliases= 's7, d3 , q1'),
- Reg( 's8', 8, IsScratch=1, CCArg=9, IsFP32=1, Aliases= 's8, d4 , q2'),
- Reg( 's9', 9, IsScratch=1, CCArg=10, IsFP32=1, Aliases= 's9, d4 , q2'),
- Reg('s10', 10, IsScratch=1, CCArg=11, IsFP32=1, Aliases='s10, d5 , q2'),
- Reg('s11', 11, IsScratch=1, CCArg=12, IsFP32=1, Aliases='s11, d5 , q2'),
- Reg('s12', 12, IsScratch=1, CCArg=13, IsFP32=1, Aliases='s12, d6 , q3'),
- Reg('s13', 13, IsScratch=1, CCArg=14, IsFP32=1, Aliases='s13, d6 , q3'),
- Reg('s14', 14, IsScratch=1, CCArg=15, IsFP32=1, Aliases='s14, d7 , q3'),
- Reg('s15', 15, IsScratch=1, CCArg=16, IsFP32=1, Aliases='s15, d7 , q3'),
- Reg('s16', 16, IsPreserved=1, IsFP32=1, Aliases='s16, d8 , q4'),
- Reg('s17', 17, IsPreserved=1, IsFP32=1, Aliases='s17, d8 , q4'),
- Reg('s18', 18, IsPreserved=1, IsFP32=1, Aliases='s18, d9 , q4'),
- Reg('s19', 19, IsPreserved=1, IsFP32=1, Aliases='s19, d9 , q4'),
- Reg('s20', 20, IsPreserved=1, IsFP32=1, Aliases='s20, d10, q5'),
- Reg('s21', 21, IsPreserved=1, IsFP32=1, Aliases='s21, d10, q5'),
- Reg('s22', 22, IsPreserved=1, IsFP32=1, Aliases='s22, d11, q5'),
- Reg('s23', 23, IsPreserved=1, IsFP32=1, Aliases='s23, d11, q5'),
- Reg('s24', 24, IsPreserved=1, IsFP32=1, Aliases='s24, d12, q6'),
- Reg('s25', 25, IsPreserved=1, IsFP32=1, Aliases='s25, d12, q6'),
- Reg('s26', 26, IsPreserved=1, IsFP32=1, Aliases='s26, d13, q6'),
- Reg('s27', 27, IsPreserved=1, IsFP32=1, Aliases='s27, d13, q6'),
- Reg('s28', 28, IsPreserved=1, IsFP32=1, Aliases='s28, d14, q7'),
- Reg('s29', 29, IsPreserved=1, IsFP32=1, Aliases='s29, d14, q7'),
- Reg('s30', 30, IsPreserved=1, IsFP32=1, Aliases='s30, d15, q7'),
- Reg('s31', 31, IsPreserved=1, IsFP32=1, Aliases='s31, d15, q7'),
-]
-
-FP64 = [
- Reg( 'd0', 0, IsScratch=1, CCArg=1, IsFP64=1, Aliases= 'd0, q0, s0, s1'),
- Reg( 'd1', 1, IsScratch=1, CCArg=2, IsFP64=1, Aliases= 'd1, q0, s2, s3'),
- Reg( 'd2', 2, IsScratch=1, CCArg=3, IsFP64=1, Aliases= 'd2, q1, s4, s5'),
- Reg( 'd3', 3, IsScratch=1, CCArg=4, IsFP64=1, Aliases= 'd3, q1, s6, s7'),
- Reg( 'd4', 4, IsScratch=1, CCArg=5, IsFP64=1, Aliases= 'd4, q2, s8, s9'),
- Reg( 'd5', 5, IsScratch=1, CCArg=6, IsFP64=1, Aliases= 'd5, q2, s10, s11'),
- Reg( 'd6', 6, IsScratch=1, CCArg=7, IsFP64=1, Aliases= 'd6, q3, s12, s13'),
- Reg( 'd7', 7, IsScratch=1, CCArg=8, IsFP64=1, Aliases= 'd7, q3, s14, s15'),
- Reg( 'd8', 8, IsPreserved=1, IsFP64=1, Aliases= 'd8, q4, s16, s17'),
- Reg( 'd9', 9, IsPreserved=1, IsFP64=1, Aliases= 'd9, q4, s18, s19'),
- Reg('d10', 10, IsPreserved=1, IsFP64=1, Aliases='d10, q5, s20, s21'),
- Reg('d11', 11, IsPreserved=1, IsFP64=1, Aliases='d11, q5, s22, s23'),
- Reg('d12', 12, IsPreserved=1, IsFP64=1, Aliases='d12, q6, s24, s25'),
- Reg('d13', 13, IsPreserved=1, IsFP64=1, Aliases='d13, q6, s26, s27'),
- Reg('d14', 14, IsPreserved=1, IsFP64=1, Aliases='d14, q7, s28, s29'),
- Reg('d15', 15, IsPreserved=1, IsFP64=1, Aliases='d15, q7, s30, s31'),
- Reg('d16', 16, IsScratch=1, IsFP64=1, Aliases='d16, q8'),
- Reg('d17', 17, IsScratch=1, IsFP64=1, Aliases='d17, q8'),
- Reg('d18', 18, IsScratch=1, IsFP64=1, Aliases='d18, q9'),
- Reg('d19', 19, IsScratch=1, IsFP64=1, Aliases='d19, q9'),
- Reg('d20', 20, IsScratch=1, IsFP64=1, Aliases='d20, q10'),
- Reg('d21', 21, IsScratch=1, IsFP64=1, Aliases='d21, q10'),
- Reg('d22', 22, IsScratch=1, IsFP64=1, Aliases='d22, q11'),
- Reg('d23', 23, IsScratch=1, IsFP64=1, Aliases='d23, q11'),
- Reg('d24', 24, IsScratch=1, IsFP64=1, Aliases='d24, q12'),
- Reg('d25', 25, IsScratch=1, IsFP64=1, Aliases='d25, q12'),
- Reg('d26', 26, IsScratch=1, IsFP64=1, Aliases='d26, q13'),
- Reg('d27', 27, IsScratch=1, IsFP64=1, Aliases='d27, q13'),
- Reg('d28', 28, IsScratch=1, IsFP64=1, Aliases='d28, q14'),
- Reg('d29', 29, IsScratch=1, IsFP64=1, Aliases='d29, q14'),
- Reg('d30', 30, IsScratch=1, IsFP64=1, Aliases='d30, q15'),
- Reg('d31', 31, IsScratch=1, IsFP64=1, Aliases='d31, q15'),
-]
-
-Vec128 = [
- Reg( 'q0', 0, IsScratch=1, CCArg=1, IsVec128=1, Aliases= 'q0, d0, d1, s0, s1, s2, s3'),
- Reg( 'q1', 1, IsScratch=1, CCArg=2, IsVec128=1, Aliases= 'q1, d2, d3, s4, s5, s6, s7'),
- Reg( 'q2', 2, IsScratch=1, CCArg=3, IsVec128=1, Aliases= 'q2, d4, d5, s8, s9, s10, s11'),
- Reg( 'q3', 3, IsScratch=1, CCArg=4, IsVec128=1, Aliases= 'q3, d6, d7, s12, s13, s14, s15'),
- Reg( 'q4', 4, IsPreserved=1, IsVec128=1, Aliases= 'q4, d8, d9, s16, s17, s18, s19'),
- Reg( 'q5', 5, IsPreserved=1, IsVec128=1, Aliases= 'q5, d10, d11, s20, s21, s22, s23'),
- Reg( 'q6', 6, IsPreserved=1, IsVec128=1, Aliases= 'q6, d12, d13, s24, s25, s26, s27'),
- Reg( 'q7', 7, IsPreserved=1, IsVec128=1, Aliases= 'q7, d14, d15, s28, s29, s30, s31'),
- Reg( 'q8', 8, IsScratch=1, IsVec128=1, Aliases= 'q8, d16, d17'),
- Reg( 'q9', 9, IsScratch=1, IsVec128=1, Aliases= 'q9, d18, d19'),
- Reg('q10', 10, IsScratch=1, IsVec128=1, Aliases='q10, d20, d21'),
- Reg('q11', 11, IsScratch=1, IsVec128=1, Aliases='q11, d22, d23'),
- Reg('q12', 12, IsScratch=1, IsVec128=1, Aliases='q12, d24, d25'),
- Reg('q13', 13, IsScratch=1, IsVec128=1, Aliases='q13, d26, d27'),
- Reg('q14', 14, IsScratch=1, IsVec128=1, Aliases='q14, d28, d29'),
- Reg('q15', 15, IsScratch=1, IsVec128=1, Aliases='q15, d30, d31'),
-]
-
-# TODO(jpp): Fix the pop emission, then emit FP64/Vec128 reverted.
-RegClasses = [('GPR', GPRs), ('I64PAIR', I64Pairs), ('FP32', FP32),
- ('FP64', FP64), ('VEC128', Vec128)]
-
-AllRegs = {}
-for _, RegClass in RegClasses:
- for Reg in RegClass:
- assert Reg.Name not in AllRegs
- AllRegs[Reg.Name] = Reg
-
-for _, RegClass in RegClasses:
- for Reg in RegClass:
- for Alias in AllRegs[Reg.Name].Features.Aliases().Aliases:
- assert AllRegs[Alias].IsAnAliasOf(Reg), '%s VS %s' % (Reg, AllRegs[Alias])
- assert (AllRegs[Alias].Features.LivesInGPR() ==
- Reg.Features.LivesInGPR()), '%s VS %s' % (Reg, AllRegs[Alias])
- assert (AllRegs[Alias].Features.LivesInVFP() ==
- Reg.Features.LivesInVFP()), '%s VS %s' % (Reg, AllRegs[Alias])
-
-print ("// This file was auto generated by the {script} script.\n"
- "// Do not modify it: modify the script instead.\n"
- "\n"
- "#ifndef SUBZERO_SRC_ICEREGISTERSARM32_DEF\n"
- "#define SUBZERO_SRC_ICEREGISTERSARM32_DEF\n".format(script=os.path.basename(sys.argv[0])))
-
-for Name, RegClass in RegClasses:
- print '//{xmacro}'.format(xmacro=Reg.DefiningXMacro())
- print "#define REGARM32_%s_TABLE" % Name,
- for Reg in RegClass:
- sys.stdout.write(' \\\n X({Reg})'.format(Reg=Reg))
- print '\n'
-print "#endif // SUBZERO_SRC_ICEREGISTERSARM32_DEF",
diff --git a/third_party/subzero/pydir/gen_test_arith_ll.py b/third_party/subzero/pydir/gen_test_arith_ll.py
deleted file mode 100644
index 05ed9a5..0000000
--- a/third_party/subzero/pydir/gen_test_arith_ll.py
+++ /dev/null
@@ -1,56 +0,0 @@
-def mangle(op, op_type, signed):
- # suffixMap gives the C++ name-mangling suffixes for a function that takes two
- # arguments of the given type. The first entry is for the unsigned version of
- # the type, and the second entry is for the signed version.
- suffixMap = { 'i1': ['bb', 'bb'],
- 'i8': ['hh', 'aa'],
- 'i16': ['tt', 'ss'],
- 'i32': ['jj', 'ii'],
- 'i64': ['yy', 'xx'],
- 'float': ['ff', 'ff'],
- 'double': ['dd', 'dd'],
- '<4 x i32>': ['Dv4_jS_', 'Dv4_iS_'],
- '<8 x i16>': ['Dv8_tS_', 'Dv8_sS_'],
- '<16 x i8>': ['Dv16_hS_', 'Dv16_aS_'],
- '<4 x float>': ['Dv4_fS_', 'Dv4_fS_'],
- }
- base = 'test' + op.capitalize()
- return '_Z' + str(len(base)) + base + suffixMap[op_type][signed]
-
-def arith(Native, Type, Op):
- _TEMPLATE_ = """
-define internal {{native}} @{{name}}({{native}} %a, {{native}} %b) {{{{
- {trunc_a}
- {trunc_b}
- %result{{trunc}} = {{op}} {{type}} %a{{trunc}}, %b{{trunc}}
- {zext}
- ret {{native}} %result
-}}}}"""
-
- Signed = Op in {'sdiv', 'srem', 'ashr'}
- Name = mangle(Op, Type, Signed)
- # Most i1 operations are invalid for PNaCl, so map them to i32.
- if Type == 'i1' and (Op not in {'and', 'or', 'xor'}):
- Type = 'i32'
- x = _TEMPLATE_.format(
- trunc_a = '%a.trunc = trunc {native} %a to {type}' if
- Native != Type else '',
- trunc_b = '%b.trunc = trunc {native} %b to {type}' if
- Native != Type else '',
- zext = '%result = ' + ('sext' if Signed else 'zext') +
- ' {type} %result.trunc to {native}' if Native != Type else '')
- lines = x.format(native=Native, type=Type, op=Op, name=Name,
- trunc='.trunc' if Native != Type else '')
- # Strip trailing whitespace from each line to keep git happy.
- print '\n'.join([line.rstrip() for line in lines.splitlines()])
-
-for op in ['add', 'sub', 'mul', 'sdiv', 'udiv', 'srem', 'urem', 'shl', 'lshr',
- 'ashr', 'and', 'or', 'xor']:
- for op_type in ['i1', 'i8', 'i16', 'i32']:
- arith('i32', op_type, op)
- for op_type in ['i64', '<4 x i32>', '<8 x i16>', '<16 x i8>']:
- arith(op_type, op_type, op)
-
-for op in ['fadd', 'fsub', 'fmul', 'fdiv', 'frem']:
- for op_type in ['float', 'double', '<4 x float>']:
- arith(op_type, op_type, op)
diff --git a/third_party/subzero/pydir/if.py b/third_party/subzero/pydir/if.py
deleted file mode 100755
index 86923c6..0000000
--- a/third_party/subzero/pydir/if.py
+++ /dev/null
@@ -1,48 +0,0 @@
-#!/usr/bin/env python2
-
-import argparse
-import os
-import sys
-
-from utils import shellcmd
-
-def main():
- """Run the specified command only if conditions are met.
-
- Two conditions are checked. First, the CONDITION must be true.
- Secondly, all NEED names must be in the set of HAVE names.
- If both conditions are met, the command defined by the remaining
- arguments is run in a shell.
- """
- argparser = argparse.ArgumentParser(
- description=' ' + main.__doc__,
- formatter_class=argparse.ArgumentDefaultsHelpFormatter)
- argparser.add_argument('--cond', choices={'true', 'false'} , required=False,
- default='true', metavar='CONDITION',
- help='Condition to test.')
- argparser.add_argument('--need', required=False, default=[],
- action='append', metavar='NEED',
- help='Needed name. May be repeated.')
- argparser.add_argument('--have', required=False, default=[],
- action='append', metavar='HAVE',
- help='Name you have. May be repeated.')
- argparser.add_argument('--echo-cmd', required=False,
- action='store_true',
- help='Trace the command before running.')
- argparser.add_argument('--command', nargs=argparse.REMAINDER,
- help='Command to run if attributes found.')
-
- args = argparser.parse_args()
-
- # Quit early if no command to run.
- if not args.command:
- raise RuntimeError("No command argument(s) specified for ifatts")
-
- if args.cond == 'true' and set(args.need) <= set(args.have):
- stdout_result = shellcmd(args.command, echo=args.echo_cmd)
- if not args.echo_cmd:
- sys.stdout.write(stdout_result)
-
-if __name__ == '__main__':
- main()
- sys.exit(0)
diff --git a/third_party/subzero/pydir/run-pnacl-sz.py b/third_party/subzero/pydir/run-pnacl-sz.py
deleted file mode 100755
index eee5b49..0000000
--- a/third_party/subzero/pydir/run-pnacl-sz.py
+++ /dev/null
@@ -1,221 +0,0 @@
-#!/usr/bin/env python2
-
-import argparse
-import itertools
-import os
-import re
-import subprocess
-import sys
-import tempfile
-
-from utils import FindBaseNaCl, GetObjdumpCmd, shellcmd
-
-
-def TargetAssemblerFlags(target, sandboxed):
- # TODO(reed kotler). Need to find out exactly we need to
- # add here for Mips32.
- flags = { 'x8632': ['-triple=%s' % ('i686-nacl' if sandboxed else 'i686')],
- 'x8664': ['-triple=%s' % (
- 'x86_64-nacl' if sandboxed else 'x86_64')],
- 'arm32': ['-triple=%s' % (
- 'armv7a-nacl' if sandboxed else 'armv7a'),
- '-mcpu=cortex-a9', '-mattr=+neon'],
- 'mips32': ['-triple=%s' % (
- 'mipsel-nacl' if sandboxed else 'mipsel'),
- '-mcpu=mips32'] }
- return flags[target]
-
-
-def TargetDisassemblerFlags(target):
- flags = { 'x8632': ['-Mintel'],
- 'x8664': ['-Mintel'],
- 'arm32': [],
- 'mips32':[] }
- return flags[target]
-
-def main():
- """Run the pnacl-sz compiler on an llvm file.
-
- Takes an llvm input file, freezes it into a pexe file, converts
- it to a Subzero program, and finally compiles it.
- """
- argparser = argparse.ArgumentParser(
- description=' ' + main.__doc__,
- formatter_class=argparse.ArgumentDefaultsHelpFormatter)
- argparser.add_argument('--input', '-i', required=True,
- help='LLVM source file to compile')
- argparser.add_argument('--output', '-o', required=False,
- help='Output file to write')
- argparser.add_argument('--insts', required=False,
- action='store_true',
- help='Stop after translating to ' +
- 'Subzero instructions')
- argparser.add_argument('--no-local-syms', required=False,
- action='store_true',
- help="Don't keep local symbols in the pexe file")
- argparser.add_argument('--llvm', required=False,
- action='store_true',
- help='Parse pexe into llvm IR first, then ' +
- 'convert to Subzero')
- argparser.add_argument('--llvm-source', required=False,
- action='store_true',
- help='Parse source directly into llvm IR ' +
- '(without generating a pexe), then ' +
- 'convert to Subzero')
- argparser.add_argument(
- '--pnacl-sz', required=False, default='./pnacl-sz', metavar='PNACL-SZ',
- help="Subzero translator 'pnacl-sz'")
- argparser.add_argument('--pnacl-bin-path', required=False,
- default=(
- '{root}/toolchain/linux_x86/pnacl_newlib_raw/bin'
- ).format(root=FindBaseNaCl()),
- metavar='PNACL_BIN_PATH',
- help='Path to LLVM & Binutils executables ' +
- '(e.g. for building PEXE files)')
- argparser.add_argument('--assemble', required=False,
- action='store_true',
- help='Assemble the output')
- argparser.add_argument('--disassemble', required=False,
- action='store_true',
- help='Disassemble the assembled output')
- argparser.add_argument('--dis-flags', required=False,
- action='append', default=[],
- help='Add a disassembler flag')
- argparser.add_argument('--filetype', default='iasm', dest='filetype',
- choices=['obj', 'asm', 'iasm'],
- help='Output file type. Default %(default)s')
- argparser.add_argument('--forceasm', required=False, action='store_true',
- help='Force --filetype=asm')
- argparser.add_argument('--target', default='x8632', dest='target',
- choices=['x8632','x8664','arm32','mips32'],
- help='Target architecture. Default %(default)s')
- argparser.add_argument('--echo-cmd', required=False,
- action='store_true',
- help='Trace command that generates ICE instructions')
- argparser.add_argument('--tbc', required=False, action='store_true',
- help='Input is textual bitcode (not .ll)')
- argparser.add_argument('--expect-fail', required=False, action='store_true',
- help='Negate success of run by using LLVM not')
- argparser.add_argument('--allow-pnacl-reader-error-recovery',
- action='store_true',
- help='Continue parsing after first error')
- argparser.add_argument('--args', '-a', nargs=argparse.REMAINDER,
- default=[],
- help='Remaining arguments are passed to pnacl-sz')
- argparser.add_argument('--sandbox', required=False, action='store_true',
- help='Sandboxes the generated code')
-
- args = argparser.parse_args()
- pnacl_bin_path = args.pnacl_bin_path
- llfile = args.input
-
- if args.llvm and args.llvm_source:
- raise RuntimeError("Can't specify both '--llvm' and '--llvm-source'")
-
- if args.llvm_source and args.no_local_syms:
- raise RuntimeError("Can't specify both '--llvm-source' and " +
- "'--no-local-syms'")
-
- if args.llvm_source and args.tbc:
- raise RuntimeError("Can't specify both '--tbc' and '--llvm-source'")
-
- if args.llvm and args.tbc:
- raise RuntimeError("Can't specify both '--tbc' and '--llvm'")
-
- if args.forceasm:
- if args.expect_fail:
- args.forceasm = False
- elif args.filetype == 'asm':
- pass
- elif args.filetype == 'iasm':
- # TODO(sehr) implement forceasm for iasm.
- pass
- elif args.filetype == 'obj':
- args.filetype = 'asm'
- args.assemble = True
-
- cmd = []
- if args.tbc:
- cmd = [os.path.join(pnacl_bin_path, 'pnacl-bcfuzz'), llfile,
- '-bitcode-as-text', '-output', '-', '|']
- elif not args.llvm_source:
- cmd = [os.path.join(pnacl_bin_path, 'llvm-as'), llfile, '-o', '-', '|',
- os.path.join(pnacl_bin_path, 'pnacl-freeze')]
- if not args.no_local_syms:
- cmd += ['--allow-local-symbol-tables']
- cmd += ['|']
- if args.expect_fail:
- cmd += [os.path.join(pnacl_bin_path, 'not')]
- cmd += [args.pnacl_sz]
- cmd += ['--target', args.target]
- if args.sandbox:
- cmd += ['-sandbox']
- if args.insts:
- # If the tests are based on '-verbose inst' output, force
- # single-threaded translation because dump output does not get
- # reassembled into order.
- cmd += ['-verbose', 'inst,global_init', '-notranslate', '-threads=0']
- elif args.allow_pnacl_reader_error_recovery:
- cmd += ['-allow-pnacl-reader-error-recovery', '-threads=0']
- if not args.llvm_source:
- cmd += ['--bitcode-format=pnacl']
- if not args.no_local_syms:
- cmd += ['--allow-local-symbol-tables']
- if args.llvm or args.llvm_source:
- cmd += ['--build-on-read=0']
- else:
- cmd += ['--build-on-read=1']
- cmd += ['--filetype=' + args.filetype]
- cmd += ['--emit-revision=0']
- script_name = os.path.basename(sys.argv[0])
- for _, arg in enumerate(args.args):
- # Redirecting the output file needs to be done through the script
- # because forceasm may introduce a new temporary file between pnacl-sz
- # and llvm-mc. Similar issues could occur when setting filetype, target,
- # or sandbox through --args. Filter and report an error.
- if re.search('^-?-(o|output|filetype|target|sandbox)(=.+)?$', arg):
- preferred_option = '--output' if re.search('^-?-o(=.+)?$', arg) else arg
- print 'Option should be set using:'
- print ' %s ... %s ... --args' % (script_name, preferred_option)
- print 'rather than:'
- print ' %s ... --args %s ...' % (script_name, arg)
- exit(1)
- asm_temp = None
- output_file_name = None
- keep_output_file = False
- if args.output:
- output_file_name = args.output
- keep_output_file = True
- cmd += args.args
- if args.llvm_source:
- cmd += [llfile]
- if args.assemble or args.disassemble:
- if not output_file_name:
- # On windows we may need to close the file first before it can be
- # re-opened by the other tools, so don't do delete-on-close,
- # and instead manually delete.
- asm_temp = tempfile.NamedTemporaryFile(delete=False)
- asm_temp.close()
- output_file_name = asm_temp.name
- if args.assemble and args.filetype != 'obj':
- cmd += (['|', os.path.join(pnacl_bin_path, 'llvm-mc')] +
- TargetAssemblerFlags(args.target, args.sandbox) +
- ['-filetype=obj', '-o', output_file_name])
- elif output_file_name:
- cmd += ['-o', output_file_name]
- if args.disassemble:
- # Show wide instruction encodings, diassemble, show relocs and
- # dissasemble zeros.
- cmd += (['&&', os.path.join(pnacl_bin_path, GetObjdumpCmd(args.target))] +
- args.dis_flags +
- ['-w', '-d', '-r', '-z'] + TargetDisassemblerFlags(args.target) +
- [output_file_name])
-
- stdout_result = shellcmd(cmd, echo=args.echo_cmd)
- if not args.echo_cmd:
- sys.stdout.write(stdout_result)
- if asm_temp and not keep_output_file:
- os.remove(output_file_name)
-
-if __name__ == '__main__':
- main()
diff --git a/third_party/subzero/pydir/sz-clang++.py b/third_party/subzero/pydir/sz-clang++.py
deleted file mode 100755
index 121dd5a..0000000
--- a/third_party/subzero/pydir/sz-clang++.py
+++ /dev/null
@@ -1,6 +0,0 @@
-#!/usr/bin/env python2
-
-import sz_driver
-
-if __name__ == '__main__':
- sz_driver.run(is_cpp=True)
diff --git a/third_party/subzero/pydir/sz-clang.py b/third_party/subzero/pydir/sz-clang.py
deleted file mode 100755
index 7b93ea0..0000000
--- a/third_party/subzero/pydir/sz-clang.py
+++ /dev/null
@@ -1,6 +0,0 @@
-#!/usr/bin/env python2
-
-import sz_driver
-
-if __name__ == '__main__':
- sz_driver.run(is_cpp=False)
diff --git a/third_party/subzero/pydir/sz_clang_dummies.c b/third_party/subzero/pydir/sz_clang_dummies.c
deleted file mode 100644
index d0abc94..0000000
--- a/third_party/subzero/pydir/sz_clang_dummies.c
+++ /dev/null
@@ -1,13 +0,0 @@
-#include <stdlib.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-void *__asan_dummy_calloc(size_t nmemb, size_t size) {
- return calloc(nmemb, size);
-}
-
-#ifdef __cplusplus
-} // extern "C"
-#endif
diff --git a/third_party/subzero/pydir/sz_driver.py b/third_party/subzero/pydir/sz_driver.py
deleted file mode 100644
index f27d678..0000000
--- a/third_party/subzero/pydir/sz_driver.py
+++ /dev/null
@@ -1,88 +0,0 @@
-import os
-import shutil
-import subprocess
-import sys
-import tempfile
-
-from utils import FindBaseNaCl, shellcmd
-
-def subsToMacros(subs, src):
- macros = ['#include <stddef.h>',
- '#ifdef __cplusplus',
- 'extern "C" {',
- '#endif']
- for func in subs:
- args = [('{atype} a{num}').format(atype=atype, num=i) for
- i, atype in enumerate(subs[func]['sig'][1:])]
- macros.append((
- '{ftype} {name}({args});'
- ).format(ftype=subs[func]['sig'][0],
- name=subs[func]['sub'],
- args=', '.join(args)))
- macros.append((
- '#define {func}(args...) ({sub}(args))'
- ).format(func=func, sub=subs[func]['sub']))
- macros += ['#ifdef __cplusplus',
- '} // extern "C"',
- '#endif',
- '#line 1 "{src}"'.format(src=src)]
- return '\n'.join(macros) + '\n'
-
-def run(is_cpp):
- """Passes its arguments directly to pnacl-clang.
-
- If -fsanitize-address is specified, extra information is passed to
- pnacl-clang to ensure that later instrumentation in pnacl-sz can be
- performed. For example, clang automatically inlines many memory allocation
- functions, so this script will redefine them at compile time to make sure
- they can be correctly instrumented by pnacl-sz.
- """
- pnacl_root = FindBaseNaCl()
- dummy_subs = {'calloc': {'sig': ['void *', 'size_t', 'size_t'],
- 'sub': '__asan_dummy_calloc'},
- '_calloc': {'sig': ['void *', 'size_t', 'size_t'],
- 'sub': '__asan_dummy_calloc'}}
- subs_src = (
- '{root}/toolchain_build/src/subzero/pydir/sz_clang_dummies.c'
- ).format(root=pnacl_root)
- clang = (
- '{root}/toolchain/linux_x86/pnacl_newlib_raw/bin/pnacl-clang{pp}'
- ).format(root=pnacl_root, pp='++' if is_cpp else '')
- args = sys.argv
- args[0] = clang
- tmp_dir = ''
- if '-fsanitize-address' in args:
- args.remove('-fsanitize-address')
- include_dirs = set()
- tmp_dir = tempfile.mkdtemp()
- for i, arg in enumerate(args[1:], 1):
- if not os.path.isfile(arg):
- continue
- src = os.path.basename(arg)
- ext = os.path.splitext(arg)[1]
- if ext in ['.c', '.cc', '.cpp']:
- include_dirs |= {os.path.dirname(arg)}
- dest_name = os.path.join(tmp_dir, src)
- with open(dest_name, 'w') as dest:
- dest.write(subsToMacros(dummy_subs, arg))
- with open(arg) as src:
- for line in src:
- dest.write(line)
- args[i] = dest_name
- # If linking (not single file compilation) then add dummy definitions
- if not ('-o' in args and
- ('-c' in args or '-S' in args or '-E' in args)):
- args.append(subs_src)
- for d in include_dirs:
- args.append('-iquote {d}'.format(d=d))
- if '-fno-inline' not in args:
- args.append('-fno-inline')
- err_code = 0
- try:
- shellcmd(args, echo=True)
- except subprocess.CalledProcessError as e:
- print e.output
- err_code = e.returncode
- if tmp_dir != '':
- shutil.rmtree(tmp_dir)
- exit(err_code)
diff --git a/third_party/subzero/pydir/szbuild.py b/third_party/subzero/pydir/szbuild.py
deleted file mode 100755
index 3b8a1f5..0000000
--- a/third_party/subzero/pydir/szbuild.py
+++ /dev/null
@@ -1,475 +0,0 @@
-#!/usr/bin/env python2
-
-import argparse
-import os
-import pipes
-import re
-import sys
-
-from utils import FindBaseNaCl, GetObjcopyCmd, get_sfi_string, shellcmd
-
-def NewerThanOrNotThere(old_path, new_path):
- """Returns whether old_path is newer than new_path.
-
- Also returns true if either path doesn't exist.
- """
- if not (os.path.exists(old_path) and os.path.exists(new_path)):
- return True
- return os.path.getmtime(old_path) > os.path.getmtime(new_path)
-
-def BuildRegex(patterns, syms):
- """Build a regular expression string for inclusion or exclusion.
-
- Creates a regex string from an array of patterns and an array
- of symbol names. Each element in the patterns array is either a
- regex, or a range of entries in the symbol name array, e.g. '2:9'.
- """
- pattern_list = []
- for pattern in patterns:
- if pattern[0].isdigit() or pattern[0] == ':':
- # Legitimate symbols or regexes shouldn't start with a
- # digit or a ':', so interpret the pattern as a range.
- interval = pattern.split(':')
- if len(interval) == 1:
- # Treat singleton 'n' as 'n:n+1'.
- lower = int(interval[0])
- upper = lower + 1
- elif len(interval) == 2:
- # Handle 'a:b', 'a:', and ':b' with suitable defaults.
- lower = int(interval[0]) if len(interval[0]) else 0
- upper = int(interval[1]) if len(interval[1]) else len(syms)
- else:
- print 'Invalid range syntax: {p}'.format(p=pattern)
- exit(1)
- pattern = '$|^'.join([re.escape(p) for p in syms[lower:upper]])
- pattern_list.append('^' + pattern + '$')
- return '|'.join(pattern_list) if len(pattern_list) else '^$'
-
-def MatchSymbol(sym, re_include, re_exclude, default_match):
- """Match a symbol name against inclusion/exclusion rules.
-
- Returns True or False depending on whether the given symbol
- matches the compiled include or exclude regexes. The default is
- returned if neither the include nor the exclude regex matches.
- """
- if re_exclude.match(sym):
- # Always honor an explicit exclude before considering
- # includes.
- return False
- if re_include.match(sym):
- return True
- return default_match
-
-def AddOptionalArgs(argparser):
- argparser.add_argument('--force', dest='force', type=int, choices=[0, 1],
- default=1,
- help='Force all re-translations of the pexe.' +
- ' Default %(default)s.')
- argparser.add_argument('--include', '-i', default=[], dest='include',
- action='append',
- help='Subzero symbols to include ' +
- '(regex or line range)')
- argparser.add_argument('--exclude', '-e', default=[], dest='exclude',
- action='append',
- help='Subzero symbols to exclude ' +
- '(regex or line range)')
- argparser.add_argument('--output', '-o', default='a.out', dest='output',
- action='store',
- help='Output executable. Default %(default)s.')
- argparser.add_argument('-O', default='2', dest='optlevel',
- choices=['m1', '-1', '0', '1', '2'],
- help='Optimization level ' +
- '(m1 and -1 are equivalent).' +
- ' Default %(default)s.')
- argparser.add_argument('--filetype', default='iasm', dest='filetype',
- choices=['obj', 'asm', 'iasm'],
- help='Output file type. Default %(default)s.')
- argparser.add_argument('--sandbox', dest='sandbox', action='store_true',
- help='Enable sandboxing in the translator')
- argparser.add_argument('--nonsfi', dest='nonsfi', action='store_true',
- help='Enable Non-SFI in the translator')
- argparser.add_argument('--enable-block-profile',
- dest='enable_block_profile', action='store_true',
- help='Enable basic block profiling.')
- argparser.add_argument('--target', default='x8632', dest='target',
- choices=['arm32', 'x8632', 'x8664'],
- help='Generate code for specified target.')
- argparser.add_argument('--verbose', '-v', dest='verbose',
- action='store_true',
- help='Display some extra debugging output')
- argparser.add_argument('--sz', dest='sz_args', action='append', default=[],
- help='Extra arguments for Subzero')
- argparser.add_argument('--llc', dest='llc_args', action='append',
- default=[], help='Extra arguments for llc')
- argparser.add_argument('--no-sz', dest='nosz', action='store_true',
- help='Run only post-Subzero build steps')
- argparser.add_argument('--fsanitize-address', dest='asan',
- action='store_true',
- help='Instrument with AddressSanitizer')
-
-def LinkSandbox(objs, exe, target, verbose=True):
- assert target in ('x8632', 'x8664', 'arm32'), \
- '-sandbox is not available for %s' % target
- nacl_root = FindBaseNaCl()
- gold = ('{root}/toolchain/linux_x86/pnacl_newlib_raw/bin/' +
- 'le32-nacl-ld.gold').format(root=nacl_root)
- target_lib_dir = {
- 'arm32': 'arm',
- 'x8632': 'x86-32',
- 'x8664': 'x86-64',
- }[target]
- linklib = ('{root}/toolchain/linux_x86/pnacl_newlib_raw/translator/' +
- '{target_dir}/lib').format(root=nacl_root,
- target_dir=target_lib_dir)
- shellcmd([gold,
- '-nostdlib',
- '--no-fix-cortex-a8',
- '--eh-frame-hdr',
- '-z', 'text',
- #'-z', 'noexecstack',
- '--build-id',
- '--entry=__pnacl_start',
- '-static', #'-pie',
- '{linklib}/crtbegin.o'.format(linklib=linklib)] +
- objs +
- [('{root}/toolchain_build/src/subzero/build/runtime/' +
- 'szrt_sb_{target}.o').format(root=nacl_root, target=target),
- '{linklib}/libpnacl_irt_shim_dummy.a'.format(linklib=linklib),
- '--start-group',
- '{linklib}/libgcc.a'.format(linklib=linklib),
- '{linklib}/libcrt_platform.a'.format(linklib=linklib),
- '--end-group',
- '{linklib}/crtend.o'.format(linklib=linklib),
- '--undefined=_start',
- '--defsym=__Sz_AbsoluteZero=0',
- #'--defsym=_begin=0',
- '-o', exe
- ], echo=verbose)
-
-def LinkNonsfi(objs, exe, target, verbose=True):
- nacl_root = FindBaseNaCl()
- gold = ('{root}/toolchain/linux_x86/pnacl_newlib_raw/bin/' +
- 'le32-nacl-ld.gold').format(root=nacl_root)
- target_lib_dir = {
- 'arm32': 'arm-nonsfi',
- 'x8632': 'x86-32-nonsfi',
- }[target]
- linklib = ('{root}/toolchain/linux_x86/pnacl_newlib_raw/translator/' +
- '{target_dir}/lib').format(root=nacl_root,
- target_dir=target_lib_dir)
- shellcmd([gold,
- '-nostdlib',
- '--no-fix-cortex-a8',
- '--eh-frame-hdr',
- '-z', 'text',
- '-z', 'noexecstack',
- '--build-id',
- '--entry=__pnacl_start',
- '-pie',
- '{linklib}/crtbegin.o'.format(linklib=linklib)] +
- objs +
- [('{root}/toolchain_build/src/subzero/build/runtime/' +
- 'szrt_nonsfi_{target}.o').format(root=nacl_root, target=target),
- '{linklib}/libpnacl_irt_shim_dummy.a'.format(linklib=linklib),
- '--start-group',
- '{linklib}/libgcc.a'.format(linklib=linklib),
- '{linklib}/libcrt_platform.a'.format(linklib=linklib),
- '--end-group',
- '{linklib}/crtend.o'.format(linklib=linklib),
- '--undefined=_start',
- '--defsym=__Sz_AbsoluteZero=0',
- '--defsym=_begin=0',
- '-o', exe
- ], echo=verbose)
-
-def LinkNative(objs, exe, target, verbose=True):
- nacl_root = FindBaseNaCl()
- linker = {
- 'arm32': '/usr/bin/arm-linux-gnueabihf-g++',
- 'mips32': '/usr/bin/mipsel-linux-gnu-g++',
- 'x8632': ('{root}/../third_party/llvm-build/Release+Asserts/bin/clang'
- ).format(root=nacl_root),
- 'x8664': ('{root}/../third_party/llvm-build/Release+Asserts/bin/clang'
- ).format(root=nacl_root)
- }[target]
-
- extra_linker_args = {
- 'arm32': ['-mcpu=cortex-a9'],
- 'x8632': ['-m32'],
- 'x8664': ['-mx32']
- }[target]
-
- lib_dir = {
- 'arm32': 'arm-linux',
- 'x8632': 'x86-32-linux',
- 'x8664': 'x86-64-linux',
- }[target]
-
- shellcmd([linker] +
- extra_linker_args +
- objs +
- ['-o', exe,
- ('{root}/toolchain/linux_x86/pnacl_newlib_raw/translator/' +
- '{lib_dir}/lib/' +
- '{{unsandboxed_irt,irt_random,irt_query_list}}.o').format(
- root=nacl_root, lib_dir=lib_dir),
- ('{root}/toolchain_build/src/subzero/build/runtime/' +
- 'szrt_native_{target}.o').format(root=nacl_root, target=target),
- '-lm', '-lpthread', '-lrt',
- '-Wl,--defsym=__Sz_AbsoluteZero=0'
- ], echo=verbose)
-
-def main():
- """Create a hybrid translation from Subzero and llc.
-
- Takes a finalized pexe and builds a native executable as a hybrid of Subzero
- and llc translated bitcode. Linker tricks are used to determine whether
- Subzero or llc generated symbols are used, on a per-symbol basis.
-
- By default, for every symbol, its Subzero version is used. Subzero and llc
- symbols can be selectively enabled/disabled via regular expressions on the
- symbol name, or by ranges of lines in this program's auto-generated symbol
- file.
-
- For each symbol, the --exclude arguments are first checked (the symbol is
- 'rejected' on a match), followed by the --include arguments (the symbol is
- 'accepted' on a match), followed by unconditional 'rejection'. The Subzero
- version is used for an 'accepted' symbol, and the llc version is used for a
- 'rejected' symbol.
-
- Each --include and --exclude argument can be a regular expression or a range
- of lines in the symbol file. Each regular expression is wrapped inside
- '^$', so if you want a substring match on 'foo', use '.*foo.*' instead.
- Ranges use python-style 'first:last' notation, so e.g. use '0:10' or ':10'
- for the first 10 lines of the file, or '1' for the second line of the file.
-
- If no --include or --exclude arguments are given, the executable is produced
- entirely using Subzero, without using llc or linker tricks.
-
- When using the --force=0 option, this script uses file modification
- timestamps to determine whether llc and Subzero re-translation are needed.
- It checks timestamps of llc, pnacl-sz, and the pexe against the translated
- object files to determine the minimal work necessary. The --force=1 option
- (default) suppresses those checks and re-translates everything.
-
- This script expects various PNaCl and LLVM tools to be found within the
- native_client tree. When changes are made to these tools, copy them this
- way:
- cd native_client
- toolchain_build/toolchain_build_pnacl.py llvm_x86_64_linux \\
- --install=toolchain/linux_x86/pnacl_newlib_raw
- """
- argparser = argparse.ArgumentParser(
- description=' ' + main.__doc__,
- formatter_class=argparse.RawTextHelpFormatter)
- AddOptionalArgs(argparser)
- argparser.add_argument('pexe', help='Finalized pexe to translate')
- args = argparser.parse_args()
- pexe = args.pexe
- exe = args.output
- ProcessPexe(args, pexe, exe)
-
-def ProcessPexe(args, pexe, exe):
- [pexe_base, ext] = os.path.splitext(pexe)
- if ext != '.pexe':
- pexe_base = pexe
- pexe_base_unescaped = pexe_base
- pexe_base = pipes.quote(pexe_base)
- pexe = pipes.quote(pexe)
-
- nacl_root = FindBaseNaCl()
- path_addition = (
- '{root}/toolchain/linux_x86/pnacl_newlib_raw/bin'
- ).format(root=nacl_root)
- obj_llc = pexe_base + '.llc.o'
- obj_sz = pexe_base + '.sz.o'
- asm_sz = pexe_base + '.sz.s'
- obj_llc_weak = pexe_base + '.weak.llc.o'
- obj_sz_weak = pexe_base + '.weak.sz.o'
- obj_partial = obj_sz # overridden for hybrid mode
- sym_llc = pexe_base + '.sym.llc.txt'
- sym_sz = pexe_base + '.sym.sz.txt'
- sym_sz_unescaped = pexe_base_unescaped + '.sym.sz.txt'
- whitelist_sz = pexe_base + '.wl.sz.txt'
- whitelist_sz_unescaped = pexe_base_unescaped + '.wl.sz.txt'
- pnacl_sz = (
- '{root}/toolchain_build/src/subzero/pnacl-sz'
- ).format(root=nacl_root)
- llcbin = '{base}/pnacl-llc'.format(base=path_addition)
- gold = '{base}/le32-nacl-ld.gold'.format(base=path_addition)
- objcopy = '{base}/{objcopy}'.format(base=path_addition,
- objcopy=GetObjcopyCmd(args.target))
- opt_level = args.optlevel
- opt_level_map = { 'm1':'0', '-1':'0', '0':'0', '1':'1', '2':'2' }
- hybrid = args.include or args.exclude
- native = not args.sandbox and not args.nonsfi
- if args.asan:
- if args.sandbox or args.nonsfi:
- print 'Can only use AddressSanitizer with a native build'
- exit(1)
- if '-fsanitize-address' not in args.sz_args:
- args.sz_args.append('-fsanitize-address')
-
- if hybrid and (args.force or
- NewerThanOrNotThere(pexe, obj_llc) or
- NewerThanOrNotThere(llcbin, obj_llc)):
- arch = {
- 'arm32': 'arm' + get_sfi_string(args, 'v7', '-nonsfi', '-nonsfi'),
- 'x8632': 'x86-32' + get_sfi_string(args, '', '-nonsfi', '-linux'),
- 'x8664': 'x86-64' + get_sfi_string(args, '', '', '-linux')
- }[args.target]
-
- # Only run pnacl-translate in hybrid mode.
- shellcmd(['{base}/pnacl-translate'.format(base=path_addition),
- '-split-module=1',
- '-ffunction-sections',
- '-fdata-sections',
- '-c',
- '-arch', arch,
- '-O' + opt_level_map[opt_level],
- '--pnacl-driver-append-LLC_FLAGS_EXTRA=-externalize',
- '-o', obj_llc] +
- (['--pnacl-driver-verbose'] if args.verbose else []) +
- args.llc_args +
- [pexe],
- echo=args.verbose)
- if native:
- shellcmd((
- '{objcopy} --redefine-sym _start=_user_start {obj}'
- ).format(objcopy=objcopy, obj=obj_llc), echo=args.verbose)
- # Generate llc syms file for consistency, even though it's not used.
- shellcmd((
- 'nm {obj} | sed -n "s/.* [a-zA-Z] //p" > {sym}'
- ).format(obj=obj_llc, sym=sym_llc), echo=args.verbose)
-
- if (args.force or
- NewerThanOrNotThere(pexe, obj_sz) or
- NewerThanOrNotThere(pnacl_sz, obj_sz)):
- if not args.nosz:
- # Run pnacl-sz regardless of hybrid mode.
- shellcmd([pnacl_sz,
- '-O' + opt_level,
- '-bitcode-format=pnacl',
- '-filetype=' + args.filetype,
- '-o', obj_sz if args.filetype == 'obj' else asm_sz,
- '-target=' + args.target] +
- (['-externalize',
- '-ffunction-sections',
- '-fdata-sections'] if hybrid else []) +
- (['-sandbox'] if args.sandbox else []) +
- (['-nonsfi'] if args.nonsfi else []) +
- (['-enable-block-profile'] if
- args.enable_block_profile and not args.sandbox
- else []) +
- args.sz_args +
- [pexe],
- echo=args.verbose)
- if args.filetype != 'obj':
- triple = {
- 'arm32': 'arm' + get_sfi_string(args, '-nacl', '', ''),
- 'x8632': 'i686' + get_sfi_string(args, '-nacl', '', ''),
- 'x8664': 'x86_64' +
- get_sfi_string(args, '-nacl', '-linux-gnux32',
- '-linux-gnux32'),
- }[args.target]
-
- shellcmd((
- '{base}/llvm-mc -triple={triple} -filetype=obj -o {obj} {asm}'
- ).format(base=path_addition, asm=asm_sz, obj=obj_sz,
- triple=triple),
- echo=args.verbose)
- if native:
- shellcmd((
- '{objcopy} --redefine-sym _start=_user_start {obj}'
- ).format(objcopy=objcopy, obj=obj_sz), echo=args.verbose)
- if hybrid:
- shellcmd((
- 'nm {obj} | sed -n "s/.* [a-zA-Z] //p" > {sym}'
- ).format(obj=obj_sz, sym=sym_sz), echo=args.verbose)
-
- if hybrid:
- with open(sym_sz_unescaped) as f:
- sz_syms = f.read().splitlines()
- re_include_str = BuildRegex(args.include, sz_syms)
- re_exclude_str = BuildRegex(args.exclude, sz_syms)
- re_include = re.compile(re_include_str)
- re_exclude = re.compile(re_exclude_str)
- # If a symbol doesn't explicitly match re_include or re_exclude,
- # the default MatchSymbol() result is True, unless some --include
- # args are provided.
- default_match = not args.include
-
- whitelist_has_items = False
- with open(whitelist_sz_unescaped, 'w') as f:
- for sym in sz_syms:
- if MatchSymbol(sym, re_include, re_exclude, default_match):
- f.write(sym + '\n')
- whitelist_has_items = True
- shellcmd((
- '{objcopy} --weaken {obj} {weak}'
- ).format(objcopy=objcopy, obj=obj_sz, weak=obj_sz_weak),
- echo=args.verbose)
- if whitelist_has_items:
- # objcopy returns an error if the --weaken-symbols file is empty.
- shellcmd((
- '{objcopy} --weaken-symbols={whitelist} {obj} {weak}'
- ).format(objcopy=objcopy,
- whitelist=whitelist_sz, obj=obj_llc,
- weak=obj_llc_weak),
- echo=args.verbose)
- else:
- shellcmd((
- '{objcopy} {obj} {weak}'
- ).format(objcopy=objcopy, obj=obj_llc, weak=obj_llc_weak),
- echo=args.verbose)
- obj_partial = pexe_base + '.o'
- ld = {
- 'arm32': 'arm-linux-gnueabihf-ld',
- 'x8632': 'ld',
- 'x8664': 'ld',
- }[args.target]
- emulation = {
- 'arm32': 'armelf_linux_eabi',
- 'x8632': 'elf_i386',
- 'x8664': 'elf32_x86_64' if not args.sandbox else 'elf_x86_64',
- }[args.target]
- shellcmd((
- '{ld} -r -m {emulation} -o {partial} {sz} {llc}'
- ).format(ld=ld, emulation=emulation, partial=obj_partial,
- sz=obj_sz_weak, llc=obj_llc_weak),
- echo=args.verbose)
- shellcmd((
- '{objcopy} -w --localize-symbol="*" {partial}'
- ).format(objcopy=objcopy, partial=obj_partial),
- echo=args.verbose)
- shellcmd((
- '{objcopy} --globalize-symbol={start} ' +
- '--globalize-symbol=__Sz_block_profile_info {partial}'
- ).format(objcopy=objcopy, partial=obj_partial,
- start=get_sfi_string(args, '_start', '_start',
- '_user_start')),
- echo=args.verbose)
-
- # Run the linker regardless of hybrid mode.
- if args.sandbox:
- LinkSandbox([obj_partial], exe, args.target, args.verbose)
- elif args.nonsfi:
- LinkNonsfi([obj_partial], exe, args.target, args.verbose)
- else:
- objs = [obj_partial]
- if args.asan:
- objs.append(
- ('{root}/toolchain_build/src/subzero/build/runtime/' +
- 'szrt_asan_{target}.o').format(root=nacl_root,
- target=args.target))
- LinkNative(objs, exe, args.target, args.verbose)
-
- # Put the extra verbose printing at the end.
- if args.verbose and hybrid:
- print 'include={regex}'.format(regex=re_include_str)
- print 'exclude={regex}'.format(regex=re_exclude_str)
- print 'default_match={dm}'.format(dm=default_match)
- print 'Number of Subzero syms = {num}'.format(num=len(sz_syms))
-
-if __name__ == '__main__':
- main()
diff --git a/third_party/subzero/pydir/szbuild_spec2k.py b/third_party/subzero/pydir/szbuild_spec2k.py
deleted file mode 100755
index b9cf15d..0000000
--- a/third_party/subzero/pydir/szbuild_spec2k.py
+++ /dev/null
@@ -1,80 +0,0 @@
-#!/usr/bin/env python2
-
-import argparse
-import os
-import sys
-
-import szbuild
-
-from utils import FindBaseNaCl, shellcmd
-
-def main():
- """Build native gcc-style executables for one or all Spec2K components.
-
- Afterwards, the executables can be run from the
- native_client/tests/spec2k/ directory as:
- './run_all.sh RunBenchmarks SetupGccX8632Opt {train|ref} ...'
- -- or --
- './run_all.sh RunBenchmarks SetupPnaclX8632Opt {train|ref} ...'
- -- or --
- './run_all.sh RunBenchmarks SetupNonsfiX8632Opt {train|ref} ...'
- """
- nacl_root = FindBaseNaCl()
- # Use the same default ordering as spec2k/run_all.sh.
- components = [ '177.mesa', '179.art', '183.equake', '188.ammp', '164.gzip',
- '175.vpr', '176.gcc', '181.mcf', '186.crafty', '197.parser',
- '253.perlbmk', '254.gap', '255.vortex', '256.bzip2',
- '300.twolf', '252.eon' ]
-
- argparser = argparse.ArgumentParser(description=main.__doc__)
- szbuild.AddOptionalArgs(argparser)
- argparser.add_argument('--run', dest='run', action='store_true',
- help='Run after building')
- argparser.add_argument('comps', nargs='*', default=components)
- args = argparser.parse_args()
- bad = set(args.comps) - set(components)
- if bad:
- print 'Unknown component{s}: '.format(s='s' if len(bad) > 1 else '') + \
- ' '.join(x for x in bad)
- sys.exit(1)
-
- # Fix up Subzero target strings for the run_all.sh script.
- target_map = {
- 'arm32':'arm',
- 'x8632':'x8632',
- 'x8664':'x8664'
- }
- run_all_target = target_map[args.target] # fail if target not listed above
-
- suffix = (
- 'pnacl.opt.{target}' if args.sandbox else
- 'nonsfi.opt.{target}' if args.nonsfi else
- 'gcc.opt.{target}').format(
- target=run_all_target);
- for comp in args.comps:
- name = os.path.splitext(comp)[1] or comp
- if name[0] == '.':
- name = name[1:]
- szbuild.ProcessPexe(args,
- ('{root}/tests/spec2k/{comp}/' +
- '{name}.opt.stripped.pexe'
- ).format(root=nacl_root, comp=comp, name=name),
- ('{root}/tests/spec2k/{comp}/' +
- '{name}.{suffix}'
- ).format(root=nacl_root, comp=comp, name=name,
- suffix=suffix))
- if args.run:
- os.chdir('{root}/tests/spec2k'.format(root=FindBaseNaCl()))
- setup = 'Setup' + ('Pnacl' if args.sandbox else
- 'Nonsfi' if args.nonsfi else
- 'Gcc') + {
- 'arm32': 'Arm',
- 'x8632': 'X8632',
- 'x8664': 'X8664'}[args.target] + 'Opt'
- shellcmd(['./run_all.sh',
- 'RunTimedBenchmarks',
- setup,
- 'train'] + args.comps)
-
-if __name__ == '__main__':
- main()
diff --git a/third_party/subzero/pydir/targets.py b/third_party/subzero/pydir/targets.py
deleted file mode 100644
index 1f73db1..0000000
--- a/third_party/subzero/pydir/targets.py
+++ /dev/null
@@ -1,64 +0,0 @@
-#!/usr/bin/env python2
-
-from collections import namedtuple
-import glob
-
-
-# Why have 'cross_headers':
-# For some reason, clang doesn't know how to find some of the libstdc++
-# headers (c++config.h). Manually add in one of the paths:
-# https://llvm.org/bugs/show_bug.cgi?id=22937
-# Otherwise, we could assume the system has arm-linux-gnueabihf-g++ and
-# use that instead of clang, but so far we've just been using clang for
-# the unsandboxed build.
-def FindARMCrossInclude():
- return glob.glob(
- '/usr/arm-linux-gnueabihf/include/c++/*/arm-linux-gnueabihf')[-1]
-
-def FindMIPSCrossInclude():
- globs = glob.glob('/usr/mipsel-linux-gnu/include/c++/*/mipsel-linux-gnu')
- return globs[-1] if globs else '/invalid/mips/include/path'
-
-TargetInfo = namedtuple('TargetInfo',
- ['target', 'compiler_arch', 'triple', 'llc_flags',
- 'ld_emu', 'sb_emu', 'cross_headers'])
-
-X8632Target = TargetInfo(target='x8632',
- compiler_arch='x8632',
- triple='i686-none-linux',
- llc_flags=['-mcpu=pentium4m'],
- ld_emu='elf_i386_nacl',
- sb_emu='elf_i386_nacl',
- cross_headers=[])
-
-X8664Target = TargetInfo(target='x8664',
- compiler_arch='x8664',
- triple='x86_64-none-linux-gnux32',
- llc_flags=['-mcpu=x86-64'],
- ld_emu='elf32_x86_64_nacl',
- sb_emu='elf_x86_64_nacl',
- cross_headers=[])
-
-ARM32Target = TargetInfo(target='arm32',
- compiler_arch='armv7',
- triple='armv7a-none-linux-gnueabihf',
- llc_flags=['-mcpu=cortex-a9',
- '-float-abi=hard',
- '-mattr=+neon',
- '-arm-enable-dwarf-eh=1'],
- ld_emu='armelf_nacl',
- sb_emu='armelf_nacl',
- cross_headers=['-isystem', FindARMCrossInclude()])
-
-# Investigate:
-# ld_emu script mips_nacl is not present in binutils. How to get it?
-MIPS32Target = TargetInfo(target='mips32',
- compiler_arch='mips32',
- triple='mipsel-linux-gnu',
- llc_flags=[],
- ld_emu='mips_nacl',
- sb_emu='mips_nacl',
- cross_headers=['-isystem', FindMIPSCrossInclude()])
-
-def ConvertTripleToNaCl(nonsfi_triple):
- return nonsfi_triple[:nonsfi_triple.find('-linux')] + '-nacl'
diff --git a/third_party/subzero/pydir/utils.py b/third_party/subzero/pydir/utils.py
deleted file mode 100644
index 121e2e2..0000000
--- a/third_party/subzero/pydir/utils.py
+++ /dev/null
@@ -1,49 +0,0 @@
-import os
-import subprocess
-import sys
-
-def GetObjcopyCmd(target):
- """Return a suitable objcopy command."""
- if target == 'mips32':
- return 'mipsel-nacl-objcopy'
- return 'arm-nacl-objcopy'
-
-def GetObjdumpCmd(target):
- """Return a suitable objdump command."""
- if target == 'mips32':
- return 'mipsel-nacl-objdump'
- return 'arm-nacl-objdump'
-
-def shellcmd(command, echo=True):
- if not isinstance(command, str):
- command = ' '.join(command)
-
- if echo:
- print >> sys.stderr, '[cmd]'
- print >> sys.stderr, command
- print >> sys.stderr
-
- stdout_result = subprocess.check_output(command, shell=True)
- if echo: sys.stdout.write(stdout_result)
- return stdout_result
-
-def FindBaseNaCl():
- """Find the base native_client/ directory."""
- nacl = 'native_client'
- path_list = os.getcwd().split(os.sep)
- """Use the executable path if cwd does not contain 'native_client' """
- path_list = path_list if nacl in path_list else sys.argv[0].split(os.sep)
- if nacl not in path_list:
- print "Script must be executed from within 'native_client' directory"
- exit(1)
- last_index = len(path_list) - path_list[::-1].index(nacl)
- return os.sep.join(path_list[:last_index])
-
-def get_sfi_string(args, sb_ret, nonsfi_ret, native_ret):
- """Return a value depending on args.sandbox and args.nonsfi."""
- if args.sandbox:
- assert(not args.nonsfi)
- return sb_ret
- if args.nonsfi:
- return nonsfi_ret
- return native_ret
diff --git a/third_party/subzero/pydir/wasm-run-torture-tests.py b/third_party/subzero/pydir/wasm-run-torture-tests.py
deleted file mode 100755
index fb8c8cf..0000000
--- a/third_party/subzero/pydir/wasm-run-torture-tests.py
+++ /dev/null
@@ -1,229 +0,0 @@
-#!/usr/bin/env python2
-
-#===- subzero/wasm-run-torture-tests.py - Subzero WASM Torture Test Driver ===//
-#
-# The Subzero Code Generator
-#
-# This file is distributed under the University of Illinois Open Source
-# License. See LICENSE.TXT for details.
-#
-#===-----------------------------------------------------------------------===//
-
-from __future__ import print_function
-import argparse
-import glob
-import multiprocessing
-import os
-import Queue
-import shutil
-import StringIO
-import sys
-import threading
-
-IGNORED_TESTS = set([
- # The remaining tests are known waterfall failures
-
- '20010122-1.c.wasm',
- '20031003-1.c.wasm',
- '20071018-1.c.wasm',
- '20071120-1.c.wasm',
- '20071220-1.c.wasm',
- '20071220-2.c.wasm',
- '20101011-1.c.wasm',
- 'alloca-1.c.wasm',
- 'bitfld-3.c.wasm',
- 'bitfld-5.c.wasm',
- 'builtin-bitops-1.c.wasm',
- 'conversion.c.wasm',
- 'eeprof-1.c.wasm',
- 'frame-address.c.wasm',
- 'pr17377.c.wasm',
- 'pr32244-1.c.wasm',
- 'pr34971.c.wasm',
- 'pr36765.c.wasm',
- 'pr39228.c.wasm',
- 'pr43008.c.wasm',
- 'pr47237.c.wasm',
- 'pr60960.c.wasm',
- 'va-arg-pack-1.c.wasm',
-
- '20000717-5.c.wasm', # abort() (also works without emcc)
- '20001203-2.c.wasm', # assert fail (works without emcc)
- '20040811-1.c.wasm', # OOB trap
- '20070824-1.c.wasm', # abort() (also works without emcc)
- 'arith-rand-ll.c.wasm', # abort() (works without emcc)
- 'arith-rand.c.wasm', # abort() (works without emcc)
- 'pr23135.c.wasm', # OOB trap (works without emcc)
- 'pr34415.c.wasm', # (empty output?)
- 'pr36339.c.wasm', # abort() (works without emcc)
- 'pr38048-2.c.wasm', # abort() (works without emcc)
- 'pr42691.c.wasm', # abort() (works without emcc)
- 'pr43220.c.wasm', # OOB trap (works without emcc)
- 'pr43269.c.wasm', # abort() (works without emcc)
- 'vla-dealloc-1.c.wasm', # OOB trap (works without emcc)
- '20051012-1.c.wasm', # error reading binary
- '921208-2.c.wasm', # error reading binary
- '920501-1.c.wasm', # error reading binary
- 'call-trap-1.c.wasm', # error reading binary
- 'pr44942.c.wasm', # error reading binary
-
- '920625-1.c.wasm', # abort() (also fails without emcc)
- '931004-10.c.wasm', # abort() (also fails without emcc)
- '931004-12.c.wasm', # abort() (also fails without emcc)
- '931004-14.c.wasm', # abort() (also fails without emcc)
- '931004-6.c.wasm', # abort() (also fails without emcc)
- 'pr38051.c.wasm', # (empty output?) (fails without emcc)
- 'pr38151.c.wasm', # abort() (fails without emcc)
- 'pr44575.c.wasm', # abort() (fails without emcc)
- 'strct-stdarg-1.c.wasm', # abort() (fails without emcc)
- 'strct-varg-1.c.wasm', # abort() (fails without emcc)
- 'va-arg-22.c.wasm', # abort() (fails without emcc)
- 'stdarg-3.c.wasm', # abort() (fails without emcc)
- 'pr56982.c.wasm', # missing setjmp (wasm.js check did not catch)
-
- '20010605-2.c.wasm', # missing __netf2
- '20020413-1.c.wasm', # missing __lttf2
- '20030914-1.c.wasm', # missing __floatsitf
- '20040709-1.c.wasm', # missing __netf2
- '20040709-2.c.wasm', # missing __netf2
- '20050121-1.c.wasm', # missing __floatsitf
- '20080502-1.c.wasm', # missing __eqtf2
- '920501-8.c.wasm', # missing __extenddftf2
- '930513-1.c.wasm', # missing __extenddftf2
- '930622-2.c.wasm', # missing __floatditf
- '960215-1.c.wasm', # missing __addtf3
- '960405-1.c.wasm', # missing __eqtf2
- '960513-1.c.wasm', # missing __subtf3
- 'align-2.c.wasm', # missing __eqtf2
- 'complex-6.c.wasm', # missing __subtf3
- 'complex-7.c.wasm', # missing __netf2
- 'pr49218.c.wasm', # missing __fixsfti
- 'pr54471.c.wasm', # missing __multi3
- 'regstack-1.c.wasm', # missing __addtf3
- 'stdarg-1.c.wasm', # missing __netf2
- 'stdarg-2.c.wasm', # missing __floatsitf
- 'va-arg-5.c.wasm', # missing __eqtf2
- 'va-arg-6.c.wasm', # missing __eqtf2
- 'struct-ret-1.c.wasm', # missing __extenddftf2
-])
-
-parser = argparse.ArgumentParser()
-parser.add_argument('-v', '--verbose', action='store_true')
-parser.add_argument('--translate-only', action='store_true')
-parser.add_argument('tests', nargs='*')
-args = parser.parse_args()
-
-OUT_DIR = "./build/wasm-torture"
-
-results_lock = threading.Lock()
-
-compile_count = 0
-compile_failures = []
-
-run_count = 0
-run_failures = []
-
-def run_test(test_file, verbose=False):
- global args
- global compile_count
- global compile_failures
- global results_lock
- global run_count
- global run_failures
- global OUT_DIR
- global IGNORED_TESTS
-
- run_test = not args.translate_only
-
- test_name = os.path.basename(test_file)
- obj_file = os.path.join(OUT_DIR, test_name + ".o")
- exe_file = os.path.join(OUT_DIR, test_name + ".exe")
-
- if not verbose and test_name in IGNORED_TESTS:
- print("\033[1;34mSkipping {}\033[1;m".format(test_file))
- return
-
- cmd = """LD_LIBRARY_PATH=../../../../v8/out/native/lib.target ./pnacl-sz \
- -filetype=obj -target=x8632 {} -threads=0 -O2 \
- -verbose=wasm -o {}""".format(test_file, obj_file)
-
- if not verbose:
- cmd += " &> /dev/null"
-
- out = StringIO.StringIO()
-
- out.write(test_file + " ...");
- status = os.system(cmd);
- if status != 0:
- print('\033[1;31m[compile fail]\033[1;m', file=out)
- with results_lock:
- compile_failures.append(test_file)
- else:
- compile_count += 1
-
- # Try to link and run the program.
- cmd = "clang -g -m32 {} -o {} " + \
- "./runtime/szrt.c ./runtime/wasm-runtime.cpp -lm -lstdc++"
- cmd = cmd.format(obj_file, exe_file)
-
- if not run_test or os.system(cmd) == 0:
- if not run_test or os.system(exe_file) == 0:
- with results_lock:
- run_count += 1
- print('\033[1;32m[ok]\033[1;m', file=out)
- else:
- with results_lock:
- run_failures.append(test_file)
- print('\033[1;33m[run fail]\033[1;m', file=out)
- else:
- with results_lock:
- run_failures.append(test_file)
- print('\033[1;33m[run fail]\033[1;m', file=out)
-
- sys.stdout.write(out.getvalue())
-
-verbose = args.verbose
-
-if len(args.tests) > 0:
- test_files = args.tests
-else:
- test_files = glob.glob("./emwasm-torture-out/*.wasm")
-
-if os.path.exists(OUT_DIR):
- shutil.rmtree(OUT_DIR)
-os.mkdir(OUT_DIR)
-
-tasks = Queue.Queue()
-
-def worker():
- while True:
- run_test(tasks.get(), verbose)
- tasks.task_done()
-
-for i in range(multiprocessing.cpu_count()):
- t = threading.Thread(target=worker)
- t.daemon = True
- t.start()
-
-for test_file in test_files:
- tasks.put(test_file)
-
-tasks.join()
-
-if len(compile_failures) > 0:
- print()
- print("Compilation failures:")
- print("=====================\n")
- for f in compile_failures:
- print(" \033[1;31m" + f + "\033[1;m")
-
-if len(run_failures) > 0:
- print()
- print("Run failures:")
- print("=============\n")
- for f in run_failures:
- print(" \033[1;33m" + f + "\033[1;m")
-
-print("\n\033[1;32m{}\033[1;m / \033[1;33m{}\033[1;m / {} tests passed"
- .format(run_count, compile_count - run_count,
- run_count + len(compile_failures) + len(run_failures)))
diff --git a/third_party/subzero/src/IceASanInstrumentation.cpp b/third_party/subzero/src/IceASanInstrumentation.cpp
index 0531558..659fce1 100644
--- a/third_party/subzero/src/IceASanInstrumentation.cpp
+++ b/third_party/subzero/src/IceASanInstrumentation.cpp
@@ -54,7 +54,7 @@
{"calloc", "__asan_calloc"},
{"__asan_dummy_calloc", "__asan_calloc"},
{"realloc", "__asan_realloc"}};
-const StringSet FuncBlackList = {"_Balloc"};
+const StringSet FuncIgnoreList = {"_Balloc"};
llvm::NaClBitcodeRecord::RecordVector sizeToByteVec(SizeT Size) {
llvm::NaClBitcodeRecord::RecordVector SizeContents;
@@ -75,8 +75,8 @@
bool ASanInstrumentation::isInstrumentable(Cfg *Func) {
std::string FuncName = Func->getFunctionName().toStringOrEmpty();
- return FuncName == "" ||
- (FuncBlackList.count(FuncName) == 0 && FuncName.find(ASanPrefix) != 0);
+ return FuncName == "" || (FuncIgnoreList.count(FuncName) == 0 &&
+ FuncName.find(ASanPrefix) != 0);
}
// Create redzones around all global variables, ensuring that the initializer
diff --git a/third_party/subzero/src/IceAssemblerX86Base.h b/third_party/subzero/src/IceAssemblerX86Base.h
index 9fd9bae..86a93fc 100644
--- a/third_party/subzero/src/IceAssemblerX86Base.h
+++ b/third_party/subzero/src/IceAssemblerX86Base.h
@@ -830,7 +830,7 @@
// At this point in the assembler, we have encoded regs, so it is not
// possible to distinguish between the "new" low byte registers introduced
// in x86-64 and the legacy [abcd]h registers. Because x86, we may still
- // see ah (div) in the assembler, so we whitelist it here.
+ // see ah (div) in the assembler, so we allow it here.
//
// The "local" uint32_t Encoded_Reg_ah is needed because RegType is an
// enum that is not necessarily the same type of
diff --git a/third_party/subzero/src/IceTargetLoweringARM32.cpp b/third_party/subzero/src/IceTargetLoweringARM32.cpp
index d820bca..af41375 100644
--- a/third_party/subzero/src/IceTargetLoweringARM32.cpp
+++ b/third_party/subzero/src/IceTargetLoweringARM32.cpp
@@ -3098,7 +3098,7 @@
default:
UnimplementedLoweringError(this, Instr);
return;
- // Explicitly whitelist vector instructions we have implemented/enabled.
+ // Explicitly allow vector instructions we have implemented/enabled.
case InstArithmetic::Add:
case InstArithmetic::And:
case InstArithmetic::Ashr:
diff --git a/third_party/subzero/tests_lit/.gitignore b/third_party/subzero/tests_lit/.gitignore
deleted file mode 100644
index 83260f8..0000000
--- a/third_party/subzero/tests_lit/.gitignore
+++ /dev/null
@@ -1 +0,0 @@
-Output
diff --git a/third_party/subzero/tests_lit/asan_tests/Input/calloc.c b/third_party/subzero/tests_lit/asan_tests/Input/calloc.c
deleted file mode 100644
index 16dd6d7..0000000
--- a/third_party/subzero/tests_lit/asan_tests/Input/calloc.c
+++ /dev/null
@@ -1,10 +0,0 @@
-#include <stdlib.h>
-#include <string.h>
-#include <stdio.h>
-
-int main(void) {
- void *buf = calloc(14, sizeof(int));
- strcpy(buf, "Hello, world!");
- printf("%s\n", buf);
- free(buf);
-}
diff --git a/third_party/subzero/tests_lit/asan_tests/Input/calloc_err.c b/third_party/subzero/tests_lit/asan_tests/Input/calloc_err.c
deleted file mode 100644
index 3dbf902..0000000
--- a/third_party/subzero/tests_lit/asan_tests/Input/calloc_err.c
+++ /dev/null
@@ -1 +0,0 @@
-int main(void) { not_defined(); }
diff --git a/third_party/subzero/tests_lit/asan_tests/alignment.ll b/third_party/subzero/tests_lit/asan_tests/alignment.ll
deleted file mode 100644
index b28ee4b..0000000
--- a/third_party/subzero/tests_lit/asan_tests/alignment.ll
+++ /dev/null
@@ -1,31 +0,0 @@
-; Translate with -fsanitize-address and -O2 to test alignment and ordering of
-; redzones when allocas are coalesced.
-
-; REQUIRES: no_minimal_build
-
-; RUN: %p2i --filetype=obj --disassemble --target x8632 -i %s --args -O2 \
-; RUN: -allow-externally-defined-symbols -fsanitize-address | FileCheck %s
-
-define internal i32 @func(i32 %arg1, i32 %arg2) {
- %l1 = alloca i8, i32 4, align 4
- %l2 = alloca i8, i32 5, align 1
- ret i32 42
-}
-
-; CHECK: func
-; CHECK-NEXT: sub esp,0xac
-; CHECK-NEXT: lea eax,[esp]
-; CHECK-NEXT: shr eax,0x3
-; CHECK-NEXT: mov DWORD PTR [eax+0x20000000],0xffffffff
-; CHECK-NEXT: mov DWORD PTR [eax+0x20000004],0xffffff04
-; CHECK-NEXT: mov DWORD PTR [eax+0x20000008],0xffffffff
-; CHECK-NEXT: mov DWORD PTR [eax+0x2000000c],0xffffff05
-; CHECK-NEXT: mov DWORD PTR [eax+0x20000010],0xffffffff
-; CHECK-NEXT: mov DWORD PTR [eax+0x20000000],0x0
-; CHECK-NEXT: mov DWORD PTR [eax+0x20000004],0x0
-; CHECK-NEXT: mov DWORD PTR [eax+0x20000008],0x0
-; CHECK-NEXT: mov DWORD PTR [eax+0x2000000c],0x0
-; CHECK-NEXT: mov DWORD PTR [eax+0x20000010],0x0
-; CHECK-NEXT: mov eax,0x2a
-; CHECK-NEXT: add esp,0xac
-; CHECK-NEXT: ret
diff --git a/third_party/subzero/tests_lit/asan_tests/blacklist.ll b/third_party/subzero/tests_lit/asan_tests/blacklist.ll
deleted file mode 100644
index 1281721..0000000
--- a/third_party/subzero/tests_lit/asan_tests/blacklist.ll
+++ /dev/null
@@ -1,55 +0,0 @@
-; Test to ensure that blacklisted functions are not instrumented and others are.
-
-; REQUIRES: allow_dump
-
-; RUN: %p2i -i %s --args -verbose=inst -threads=0 -fsanitize-address \
-; RUN: -allow-externally-defined-symbols | FileCheck --check-prefix=DUMP %s
-
-declare external i32 @malloc(i32)
-declare external void @free(i32)
-
-; A black listed function
-define internal void @_Balloc() {
- %local = alloca i8, i32 4, align 4
- %heapvar = call i32 @malloc(i32 42)
- call void @free(i32 %heapvar)
- ret void
-}
-
-; DUMP-LABEL: ================ Instrumented CFG ================
-; DUMP-NEXT: define internal void @_Balloc() {
-; DUMP-NEXT: __0:
-; DUMP-NEXT: %local = alloca i8, i32 4, align 4
-; DUMP-NEXT: %heapvar = call i32 @malloc(i32 42)
-; DUMP-NEXT: call void @free(i32 %heapvar)
-; DUMP-NEXT: ret void
-; DUMP-NEXT: }
-
-; A non black listed function
-define internal void @func() {
- %local = alloca i8, i32 4, align 4
- %heapvar = call i32 @malloc(i32 42)
- call void @free(i32 %heapvar)
- ret void
-}
-
-; DUMP-LABEL: ================ Instrumented CFG ================
-; DUMP-NEXT: define internal void @func() {
-; DUMP-NEXT: __0:
-; DUMP-NEXT: %__$rz0 = alloca i8, i32 32, align 8
-; DUMP-NEXT: %local = alloca i8, i32 64, align 8
-; DUMP-NEXT: %shadowIndex = lshr i32 %__$rz0, 3
-; DUMP-NEXT: %firstShadowLoc = add i32 %shadowIndex, 536870912
-; DUMP-NEXT: %__5 = add i32 %firstShadowLoc, 0
-; DUMP-NEXT: store i32 -1, i32* %__5, align 1
-; DUMP-NEXT: %__6 = add i32 %firstShadowLoc, 4
-; DUMP-NEXT: store i32 -252, i32* %__6, align 1
-; DUMP-NEXT: %__7 = add i32 %firstShadowLoc, 8
-; DUMP-NEXT: store i32 -1, i32* %__7, align 1
-; DUMP-NEXT: %heapvar = call i32 @__asan_malloc(i32 42)
-; DUMP-NEXT: call void @__asan_free(i32 %heapvar)
-; DUMP-NEXT: store i32 0, i32* %__5, align 1
-; DUMP-NEXT: store i32 0, i32* %__6, align 1
-; DUMP-NEXT: store i32 0, i32* %__7, align 1
-; DUMP-NEXT: ret void
-; DUMP-NEXT: }
diff --git a/third_party/subzero/tests_lit/asan_tests/calloc.ll b/third_party/subzero/tests_lit/asan_tests/calloc.ll
deleted file mode 100644
index a6d7c4c..0000000
--- a/third_party/subzero/tests_lit/asan_tests/calloc.ll
+++ /dev/null
@@ -1,14 +0,0 @@
-; Test that sz-clang.py and sz-clang++.py successfully replace calls to calloc
-
-; RUN: %S/../../pydir/sz-clang.py -fsanitize-address %S/Input/calloc.c -E \
-; RUN: | FileCheck %s
-
-; RUN: %S/../../pydir/sz-clang++.py -fsanitize-address %S/Input/calloc.c -E \
-; RUN: | FileCheck %s
-
-; CHECK-LABEL: int main(void) {
-; CHECK-NEXT: void *buf = (__asan_dummy_calloc(14, sizeof(int)));
-; CHECK-NEXT: strcpy(buf, "Hello, world!");
-; CHECK-NEXT: printf("%s\n", buf);
-; CHECK-NEXT: free(buf);
-; CHECK-NEXT: }
diff --git a/third_party/subzero/tests_lit/asan_tests/calloc_err.ll b/third_party/subzero/tests_lit/asan_tests/calloc_err.ll
deleted file mode 100644
index f492dbb..0000000
--- a/third_party/subzero/tests_lit/asan_tests/calloc_err.ll
+++ /dev/null
@@ -1,11 +0,0 @@
-; Test that errors in source files are transparently reported by
-; sz-clang.py and sz-clang++.py
-
-; RUN: not %S/../../pydir/sz-clang.py -fsanitize-address %S/Input/calloc_err.c \
-; RUN: 2>&1 | FileCheck %s
-
-; RUN: not %S/../../pydir/sz-clang\+\+.py -fsanitize-address \
-; RUN: %S/Input/calloc_err.c 2>&1 | FileCheck %s
-
-; CHECK-LABEL: Input/calloc_err.c:1:18: warning:
-; CHECK-SAME: implicit declaration of function 'not_defined' is invalid in C99
diff --git a/third_party/subzero/tests_lit/asan_tests/doublefree.ll b/third_party/subzero/tests_lit/asan_tests/doublefree.ll
deleted file mode 100644
index 88e03e9..0000000
--- a/third_party/subzero/tests_lit/asan_tests/doublefree.ll
+++ /dev/null
@@ -1,25 +0,0 @@
-; Test that double frees are detected
-
-; REQUIRES: no_minimal_build
-
-; RUN: llvm-as %s -o - | pnacl-freeze > %t.pexe && %S/../../pydir/szbuild.py \
-; RUN: --fsanitize-address --sz=-allow-externally-defined-symbols \
-; RUN: %t.pexe -o %t && %t 2>&1 | FileCheck --check-prefix=ERR %s
-; RUN: llvm-as %s -o - | pnacl-freeze > %t.pexe && %S/../../pydir/szbuild.py \
-; RUN: --fsanitize-address --sz=-allow-externally-defined-symbols -O2 \
-; RUN: %t.pexe -o %t && %t 2>&1 | FileCheck --check-prefix=ERR %s
-
-declare external i32 @malloc(i32)
-declare external void @free(i32)
-declare external void @exit(i32)
-
-define void @_start(i32 %arg) {
- %alloc = call i32 @malloc(i32 42)
- call void @free(i32 %alloc)
- call void @free(i32 %alloc)
- call void @exit(i32 1)
- ret void
-}
-
-; ERR: Double free of object at
-; ERR-NEXT: address of __asan_error symbol is
diff --git a/third_party/subzero/tests_lit/asan_tests/elidelocalchecks.ll b/third_party/subzero/tests_lit/asan_tests/elidelocalchecks.ll
deleted file mode 100644
index ab14c13..0000000
--- a/third_party/subzero/tests_lit/asan_tests/elidelocalchecks.ll
+++ /dev/null
@@ -1,107 +0,0 @@
-; Test that direct loads and stores of local variables are not checked.
-; Also test that redundant checks of the same variable are elided.
-
-; REQUIRES: allow_dump
-
-; RUN: %p2i -i %s --args -verbose=inst -threads=0 -fsanitize-address \
-; RUN: | FileCheck --check-prefix=DUMP %s
-
-define internal void @foo() {
- %ptr8 = alloca i8, i32 1, align 4
- %ptr16 = alloca i8, i32 2, align 4
- %ptr32 = alloca i8, i32 4, align 4
- %ptr64 = alloca i8, i32 8, align 4
- %ptr128 = alloca i8, i32 16, align 4
-
- %target8 = bitcast i8* %ptr8 to i8*
- %target16 = bitcast i8* %ptr16 to i16*
- %target32 = bitcast i8* %ptr32 to i32*
- %target64 = bitcast i8* %ptr64 to i64*
- %target128 = bitcast i8* %ptr128 to <4 x i32>*
-
- ; unchecked loads
- %loaded8 = load i8, i8* %target8, align 1
- %loaded16 = load i16, i16* %target16, align 1
- %loaded32 = load i32, i32* %target32, align 1
- %loaded64 = load i64, i64* %target64, align 1
- %loaded128 = load <4 x i32>, <4 x i32>* %target128, align 4
-
- ; unchecked stores
- store i8 %loaded8, i8* %target8, align 1
- store i16 %loaded16, i16* %target16, align 1
- store i32 %loaded32, i32* %target32, align 1
- store i64 %loaded64, i64* %target64, align 1
- store <4 x i32> %loaded128, <4 x i32>* %target128, align 4
-
- %addr8 = ptrtoint i8* %ptr8 to i32
- %addr16 = ptrtoint i8* %ptr16 to i32
- %addr32 = ptrtoint i8* %ptr32 to i32
- %addr64 = ptrtoint i8* %ptr64 to i32
- %addr128 = ptrtoint i8* %ptr128 to i32
-
- %off8 = add i32 %addr8, -1
- %off16 = add i32 %addr16, -1
- %off32 = add i32 %addr32, -1
- %off64 = add i32 %addr64, -1
- %off128 = add i32 %addr128, -1
-
- %offtarget8 = inttoptr i32 %off8 to i8*
- %offtarget16 = inttoptr i32 %off16 to i16*
- %offtarget32 = inttoptr i32 %off32 to i32*
- %offtarget64 = inttoptr i32 %off64 to i64*
- %offtarget128 = inttoptr i32 %off128 to <4 x i32>*
-
- ; checked stores
- store i8 42, i8* %offtarget8, align 1
- store i16 42, i16* %offtarget16, align 1
- store i32 42, i32* %offtarget32, align 1
-
- ; checked loads
- %offloaded64 = load i64, i64* %offtarget64, align 1
- %offloaded128 = load <4 x i32>, <4 x i32>* %offtarget128, align 4
-
- ; loads and stores with elided redundant checks
- %offloaded8 = load i8, i8* %offtarget8, align 1
- %offloaded16 = load i16, i16* %offtarget16, align 1
- %offloaded32 = load i32, i32* %offtarget32, align 1
- store i64 %offloaded64, i64* %offtarget64, align 1
- store <4 x i32> %offloaded128, <4 x i32>* %offtarget128, align 4
-
- ret void
-}
-
-; DUMP-LABEL: ================ Instrumented CFG ================
-; DUMP-NEXT: define internal void @foo() {
-
-; Direct unchecked loads and stores
-; DUMP: %loaded8 = load i8, i8* %ptr8, align 1
-; DUMP-NEXT: %loaded16 = load i16, i16* %ptr16, align 1
-; DUMP-NEXT: %loaded32 = load i32, i32* %ptr32, align 1
-; DUMP-NEXT: %loaded64 = load i64, i64* %ptr64, align 1
-; DUMP-NEXT: %loaded128 = load <4 x i32>, <4 x i32>* %ptr128, align 4
-; DUMP-NEXT: store i8 %loaded8, i8* %ptr8, align 1
-; DUMP-NEXT: store i16 %loaded16, i16* %ptr16, align 1
-; DUMP-NEXT: store i32 %loaded32, i32* %ptr32, align 1
-; DUMP-NEXT: store i64 %loaded64, i64* %ptr64, align 1
-; DUMP-NEXT: store <4 x i32> %loaded128, <4 x i32>* %ptr128, align 4
-
-; Checked stores
-; DUMP: call void @__asan_check_store(i32 %off8, i32 1)
-; DUMP-NEXT: store i8 42, i8* %off8, align 1
-; DUMP-NEXT: call void @__asan_check_store(i32 %off16, i32 2)
-; DUMP-NEXT: store i16 42, i16* %off16, align 1
-; DUMP-NEXT: call void @__asan_check_store(i32 %off32, i32 4)
-; DUMP-NEXT: store i32 42, i32* %off32, align 1
-
-; Checked loads
-; DUMP-NEXT: call void @__asan_check_load(i32 %off64, i32 8)
-; DUMP-NEXT: %offloaded64 = load i64, i64* %off64, align 1
-; DUMP-NEXT: call void @__asan_check_load(i32 %off128, i32 16)
-; DUMP-NEXT: %offloaded128 = load <4 x i32>, <4 x i32>* %off128, align 4
-
-; Loads and stores with elided redundant checks
-; DUMP-NEXT: %offloaded8 = load i8, i8* %off8, align 1
-; DUMP-NEXT: %offloaded16 = load i16, i16* %off16, align 1
-; DUMP-NEXT: %offloaded32 = load i32, i32* %off32, align 1
-; DUMP-NEXT: store i64 %offloaded64, i64* %off64, align 1, beacon %offloaded64
-; DUMP-NEXT: store <4 x i32> %offloaded128, <4 x i32>* %off128, align 4, beacon %offloaded128
diff --git a/third_party/subzero/tests_lit/asan_tests/errors.ll b/third_party/subzero/tests_lit/asan_tests/errors.ll
deleted file mode 100644
index d058ab2..0000000
--- a/third_party/subzero/tests_lit/asan_tests/errors.ll
+++ /dev/null
@@ -1,232 +0,0 @@
-; Verify that ASan properly catches and reports bugs
-
-; REQUIRES: no_minimal_build
-
-; check with a one off the end local load
-; RUN: llvm-as %s -o - | pnacl-freeze > %t.pexe && %S/../../pydir/szbuild.py \
-; RUN: --fsanitize-address --sz=-allow-externally-defined-symbols \
-; RUN: %t.pexe -o %t && %t 2>&1 | FileCheck --check-prefix=LOCAL-LOAD %s
-; RUN: llvm-as %s -o - | pnacl-freeze > %t.pexe && %S/../../pydir/szbuild.py \
-; RUN: --fsanitize-address --sz=-allow-externally-defined-symbols -O2 \
-; RUN: %t.pexe -o %t && %t 2>&1 | FileCheck --check-prefix=LOCAL-LOAD %s
-
-; check with a many off the end local load
-; RUN: llvm-as %s -o - | pnacl-freeze > %t.pexe && %S/../../pydir/szbuild.py \
-; RUN: --fsanitize-address --sz=-allow-externally-defined-symbols \
-; RUN: %t.pexe -o %t && %t 1 2>&1 | FileCheck --check-prefix=LOCAL-LOAD %s
-; RUN: llvm-as %s -o - | pnacl-freeze > %t.pexe && %S/../../pydir/szbuild.py \
-; RUN: --fsanitize-address --sz=-allow-externally-defined-symbols -O2 \
-; RUN: %t.pexe -o %t && %t 1 2>&1 | FileCheck --check-prefix=LOCAL-LOAD %s
-
-; check with a one before the front local load
-; RUN: llvm-as %s -o - | pnacl-freeze > %t.pexe && %S/../../pydir/szbuild.py \
-; RUN: --fsanitize-address --sz=-allow-externally-defined-symbols \
-; RUN: %t.pexe -o %t && %t 1 2 2>&1 | FileCheck --check-prefix=LOCAL-LOAD %s
-; RUN: llvm-as %s -o - | pnacl-freeze > %t.pexe && %S/../../pydir/szbuild.py \
-; RUN: --fsanitize-address --sz=-allow-externally-defined-symbols -O2\
-; RUN: %t.pexe -o %t && %t 1 2 2>&1 | FileCheck --check-prefix=LOCAL-LOAD %s
-
-; check with a one off the end global load
-; RUN: llvm-as %s -o - | pnacl-freeze > %t.pexe && %S/../../pydir/szbuild.py \
-; RUN: --fsanitize-address --sz=-allow-externally-defined-symbols \
-; RUN: %t.pexe -o %t && %t 1 2 3 2>&1 | FileCheck \
-; RUN: --check-prefix=GLOBAL-LOAD %s
-; RUN: llvm-as %s -o - | pnacl-freeze > %t.pexe && %S/../../pydir/szbuild.py \
-; RUN: --fsanitize-address --sz=-allow-externally-defined-symbols -O2 \
-; RUN: %t.pexe -o %t && %t 1 2 3 2>&1 | FileCheck \
-; RUN: --check-prefix=GLOBAL-LOAD %s
-
-; check with a many off the end global load
-; RUN: llvm-as %s -o - | pnacl-freeze > %t.pexe && %S/../../pydir/szbuild.py \
-; RUN: --fsanitize-address --sz=-allow-externally-defined-symbols \
-; RUN: %t.pexe -o %t && %t 1 2 3 4 2>&1 | FileCheck \
-; RUN: --check-prefix=GLOBAL-LOAD %s
-; RUN: llvm-as %s -o - | pnacl-freeze > %t.pexe && %S/../../pydir/szbuild.py \
-; RUN: --fsanitize-address --sz=-allow-externally-defined-symbols -O2 \
-; RUN: %t.pexe -o %t && %t 1 2 3 4 2>&1 | FileCheck \
-; RUN: --check-prefix=GLOBAL-LOAD %s
-
-; check with a one before the front global load
-; RUN: llvm-as %s -o - | pnacl-freeze > %t.pexe && %S/../../pydir/szbuild.py \
-; RUN: --fsanitize-address --sz=-allow-externally-defined-symbols \
-; RUN: %t.pexe -o %t && %t 1 2 3 4 5 2>&1 | FileCheck \
-; RUN: --check-prefix=GLOBAL-LOAD %s
-; RUN: llvm-as %s -o - | pnacl-freeze > %t.pexe && %S/../../pydir/szbuild.py \
-; RUN: --fsanitize-address --sz=-allow-externally-defined-symbols -O2 \
-; RUN: %t.pexe -o %t && %t 1 2 3 4 5 2>&1 | FileCheck \
-; RUN: --check-prefix=GLOBAL-LOAD %s
-
-; check with a one off the end local store
-; RUN: llvm-as %s -o - | pnacl-freeze > %t.pexe && %S/../../pydir/szbuild.py \
-; RUN: --fsanitize-address --sz=-allow-externally-defined-symbols \
-; RUN: %t.pexe -o %t && %t 1 2 3 4 5 6 2>&1 | FileCheck \
-; RUN: --check-prefix=LOCAL-STORE %s
-; RUN: llvm-as %s -o - | pnacl-freeze > %t.pexe && %S/../../pydir/szbuild.py \
-; RUN: --fsanitize-address --sz=-allow-externally-defined-symbols -O2 \
-; RUN: %t.pexe -o %t && %t 1 2 3 4 5 6 2>&1 | FileCheck \
-; RUN: --check-prefix=LOCAL-STORE %s
-
-; check with a many off the end local store
-; RUN: llvm-as %s -o - | pnacl-freeze > %t.pexe && %S/../../pydir/szbuild.py \
-; RUN: --fsanitize-address --sz=-allow-externally-defined-symbols \
-; RUN: %t.pexe -o %t && %t 1 2 3 4 5 6 7 2>&1 | FileCheck \
-; RUN: --check-prefix=LOCAL-STORE %s
-; RUN: llvm-as %s -o - | pnacl-freeze > %t.pexe && %S/../../pydir/szbuild.py \
-; RUN: --fsanitize-address --sz=-allow-externally-defined-symbols -O2 \
-; RUN: %t.pexe -o %t && %t 1 2 3 4 5 6 7 2>&1 | FileCheck \
-; RUN: --check-prefix=LOCAL-STORE %s
-
-; check with a one before the front local store
-; RUN: llvm-as %s -o - | pnacl-freeze > %t.pexe && %S/../../pydir/szbuild.py \
-; RUN: --fsanitize-address --sz=-allow-externally-defined-symbols \
-; RUN: %t.pexe -o %t && %t 1 2 3 4 5 6 7 8 2>&1 | FileCheck \
-; RUN: --check-prefix=LOCAL-STORE %s
-; RUN: llvm-as %s -o - | pnacl-freeze > %t.pexe && %S/../../pydir/szbuild.py \
-; RUN: --fsanitize-address --sz=-allow-externally-defined-symbols -O2 \
-; RUN: %t.pexe -o %t && %t 1 2 3 4 5 6 7 8 2>&1 | FileCheck \
-; RUN: --check-prefix=LOCAL-STORE %s
-
-; check with a one off the end global store
-; RUN: llvm-as %s -o - | pnacl-freeze > %t.pexe && %S/../../pydir/szbuild.py \
-; RUN: --fsanitize-address --sz=-allow-externally-defined-symbols \
-; RUN: %t.pexe -o %t && %t 1 2 3 4 5 6 7 8 9 2>&1 | FileCheck \
-; RUN: --check-prefix=GLOBAL-STORE %s
-; RUN: llvm-as %s -o - | pnacl-freeze > %t.pexe && %S/../../pydir/szbuild.py \
-; RUN: --fsanitize-address --sz=-allow-externally-defined-symbols -O2 \
-; RUN: %t.pexe -o %t && %t 1 2 3 4 5 6 7 8 9 2>&1 | FileCheck \
-; RUN: --check-prefix=GLOBAL-STORE %s
-
-; check with a many off the end global store
-; RUN: llvm-as %s -o - | pnacl-freeze > %t.pexe && %S/../../pydir/szbuild.py \
-; RUN: --fsanitize-address --sz=-allow-externally-defined-symbols \
-; RUN: %t.pexe -o %t && %t 1 2 3 4 5 6 7 8 9 10 2>&1 | FileCheck \
-; RUN: --check-prefix=GLOBAL-STORE %s
-; RUN: llvm-as %s -o - | pnacl-freeze > %t.pexe && %S/../../pydir/szbuild.py \
-; RUN: --fsanitize-address --sz=-allow-externally-defined-symbols -O2 \
-; RUN: %t.pexe -o %t && %t 1 2 3 4 5 6 7 8 9 10 2>&1 | FileCheck \
-; RUN: --check-prefix=GLOBAL-STORE %s
-
-; check with a one before the front global store
-; RUN: llvm-as %s -o - | pnacl-freeze > %t.pexe && %S/../../pydir/szbuild.py \
-; RUN: --fsanitize-address --sz=-allow-externally-defined-symbols \
-; RUN: %t.pexe -o %t && %t 1 2 3 4 5 6 7 8 9 10 11 2>&1 | FileCheck \
-; RUN: --check-prefix=GLOBAL-STORE %s
-; RUN: llvm-as %s -o - | pnacl-freeze > %t.pexe && %S/../../pydir/szbuild.py \
-; RUN: --fsanitize-address --sz=-allow-externally-defined-symbols -O2 \
-; RUN: %t.pexe -o %t && %t 1 2 3 4 5 6 7 8 9 10 11 2>&1 | FileCheck \
-; RUN: --check-prefix=GLOBAL-STORE %s
-
-declare external void @exit(i32)
-
-; A global array
-@array = internal constant [12 x i8] zeroinitializer
-
-define void @access(i32 %is_local_i, i32 %is_load_i, i32 %err) {
- ; get the base pointer to either the local or global array
- %local = alloca i8, i32 12, align 1
- %global = bitcast [12 x i8]* @array to i8*
- %is_local = icmp ne i32 %is_local_i, 0
- %arr = select i1 %is_local, i8* %local, i8* %global
-
- ; determine the offset to access
- %err_offset = mul i32 %err, 4
- %pos_offset = add i32 %err_offset, 12
- %pos = icmp sge i32 %err_offset, 0
- %offset = select i1 %pos, i32 %pos_offset, i32 %err
-
- ; calculate the address to access
- %arraddr = ptrtoint i8* %arr to i32
- %badaddr = add i32 %arraddr, %offset
- %badptr = inttoptr i32 %badaddr to i8*
-
- ; determine load or store
- %is_load = icmp ne i32 %is_load_i, 0
- br i1 %is_load, label %bad_load, label %bad_store
-
-bad_load:
- %result = load i8, i8* %badptr, align 1
- ret void
-
-bad_store:
- store i8 42, i8* %badptr, align 1
- ret void
-}
-
-; use argc to determine which test routine to run
-define void @_start(i32 %arg) {
- %argcaddr = add i32 %arg, 8
- %argcptr = inttoptr i32 %argcaddr to i32*
- %argc = load i32, i32* %argcptr, align 1
- switch i32 %argc, label %error [i32 1, label %one_local_load
- i32 2, label %many_local_load
- i32 3, label %neg_local_load
- i32 4, label %one_global_load
- i32 5, label %many_global_load
- i32 6, label %neg_global_load
- i32 7, label %one_local_store
- i32 8, label %many_local_store
- i32 9, label %neg_local_store
- i32 10, label %one_global_store
- i32 11, label %many_global_store
- i32 12, label %neg_global_store]
-one_local_load:
- ; Access one past the end of a local
- call void @access(i32 1, i32 1, i32 0)
- br label %error
-many_local_load:
- ; Access five past the end of a local
- call void @access(i32 1, i32 1, i32 4)
- br label %error
-neg_local_load:
- ; Access one before the beginning of a local
- call void @access(i32 1, i32 1, i32 -1)
- br label %error
-one_global_load:
- ; Access one past the end of a global
- call void @access(i32 0, i32 1, i32 0)
- br label %error
-many_global_load:
- ; Access five past the end of a global
- call void @access(i32 0, i32 1, i32 4)
- br label %error
-neg_global_load:
- ; Access one before the beginning of a global
- call void @access(i32 0, i32 1, i32 -1)
- br label %error
-one_local_store:
- ; Access one past the end of a local
- call void @access(i32 1, i32 0, i32 0)
- br label %error
-many_local_store:
- ; Access five past the end of a local
- call void @access(i32 1, i32 0, i32 4)
- br label %error
-neg_local_store:
- ; Access one before the beginning of a local
- call void @access(i32 1, i32 0, i32 -1)
- br label %error
-one_global_store:
- ; Access one past the end of a global
- call void @access(i32 0, i32 0, i32 0)
- br label %error
-many_global_store:
- ; Access five past the end of a global
- call void @access(i32 0, i32 0, i32 4)
- br label %error
-neg_global_store:
- ; Access one before the beginning of a global
- call void @access(i32 0, i32 0, i32 -1)
- br label %error
-error:
- call void @exit(i32 1)
- unreachable
-}
-
-; LOCAL-LOAD: Illegal 1 byte load from stack object at
-; LOCAL-LOAD-NEXT: address of __asan_error symbol is
-; LOCAL-STORE: Illegal 1 byte store to stack object at
-; LOCAL-STORE-NEXT: address of __asan_error symbol is
-; GLOBAL-LOAD: Illegal 1 byte load from global object at
-; GLOBAL-LOAD-NEXT: address of __asan_error symbol is
-; GLOBAL-STORE: Illegal 1 byte store to global object at
-; GLOBAL-STORE-NEXT: address of __asan_error symbol is
diff --git a/third_party/subzero/tests_lit/asan_tests/func_ptr.ll b/third_party/subzero/tests_lit/asan_tests/func_ptr.ll
deleted file mode 100644
index 53d89b9..0000000
--- a/third_party/subzero/tests_lit/asan_tests/func_ptr.ll
+++ /dev/null
@@ -1,25 +0,0 @@
-; Test that calls made through pointers are unchanged by ASan
-
-; REQUIRES: allow_dump
-
-; RUN: %p2i -i %s --args -verbose=inst -threads=0 -fsanitize-address \
-; RUN: | FileCheck --check-prefix=DUMP %s
-
-define internal i32 @caller(i32 %callee_addr, i32 %arg) {
- %callee = inttoptr i32 %callee_addr to i32 (i32)*
- %result = call i32 %callee(i32 %arg)
- ret i32 %result
-}
-
-; DUMP-LABEL: ================ Initial CFG ================
-; DUMP-NEXT: define internal i32 @caller(i32 %callee_addr, i32 %arg) {
-; DUMP-NEXT: __0:
-; DUMP-NEXT: %result = call i32 %callee_addr(i32 %arg)
-; DUMP-NEXT: ret i32 %result
-; DUMP-NEXT: }
-; DUMP-LABEL: ================ Instrumented CFG ================
-; DUMP-NEXT: define internal i32 @caller(i32 %callee_addr, i32 %arg) {
-; DUMP-NEXT: __0:
-; DUMP-NEXT: %result = call i32 %callee_addr(i32 %arg)
-; DUMP-NEXT: ret i32 %result
-; DUMP-NEXT: }
diff --git a/third_party/subzero/tests_lit/asan_tests/globalredzones.ll b/third_party/subzero/tests_lit/asan_tests/globalredzones.ll
deleted file mode 100644
index 154ce87..0000000
--- a/third_party/subzero/tests_lit/asan_tests/globalredzones.ll
+++ /dev/null
@@ -1,122 +0,0 @@
-; Test of global redzone layout
-
-; REQUIRES: allow_dump
-
-; RUN: %p2i -i %s --args -threads=0 -fsanitize-address \
-; RUN: | FileCheck %s
-; RUN: %p2i -i %s --args -verbose=global_init,inst -threads=0 \
-; RUN: -fsanitize-address | FileCheck --check-prefix=DUMP %s
-
-; The array of redzones
-
-; DUMP-LABEL: ========= Instrumented Globals =========
-; DUMP: @__$rz_array = internal constant <{ i32, i32, i32, i32, i32, i32 }>
-; DUMP: <{ i32 ptrtoint ([32 x i8]* @__$rz0 to i32), i32 ptrtoint ([32 x i8]* @__$rz1 to i32),
-; DUMP: i32 ptrtoint ([32 x i8]* @__$rz2 to i32), i32 ptrtoint ([32 x i8]* @__$rz3 to i32),
-; DUMP: i32 ptrtoint ([32 x i8]* @__$rz4 to i32), i32 ptrtoint ([32 x i8]* @__$rz5 to i32) }>
-
-; (SPACE is 32 ascii)
-; DUMP-NEXT: @__$rz_sizes = internal constant <{ [4 x i8], [4 x i8], [4 x i8], [4 x i8], [4 x i8],
-; DUMP-SAME: [4 x i8] }> <{ [4 x i8] c" \00\00\00", [4 x i8] c" \00\00\00", [4 x i8] c" \00\00\00",
-; DUMP-SAME: [4 x i8] c" \00\00\00", [4 x i8] c" \00\00\00", [4 x i8] c" \00\00\00" }>
-
-; CHECK-LABEL: .type __$rz_array,%object
-; CHECK-NEXT: .section .rodata
-; CHECK-NEXT: __$rz_array:
-; CHECK-NEXT: .long __$rz0
-; CHECK-NEXT: .long __$rz1
-; CHECK-NEXT: .long __$rz2
-; CHECK-NEXT: .long __$rz3
-; CHECK-NEXT: .long __$rz4
-; CHECK-NEXT: .long __$rz5
-; CHECK-LABEL: .type __$rz_sizes,%object
-; CHECK-NEXT: .section .rodata
-; CHECK-NEXT: __$rz_sizes:
-; CHECK-NEXT: .byte 32
-; CHECK-NEXT: .byte 0
-; CHECK-NEXT: .byte 0
-; CHECK-NEXT: .byte 0
-; CHECK-NEXT: .byte 32
-; CHECK-NEXT: .byte 0
-; CHECK-NEXT: .byte 0
-; CHECK-NEXT: .byte 0
-; CHECK-NEXT: .byte 32
-; CHECK-NEXT: .byte 0
-; CHECK-NEXT: .byte 0
-; CHECK-NEXT: .byte 0
-; CHECK-NEXT: .byte 32
-; CHECK-NEXT: .byte 0
-; CHECK-NEXT: .byte 0
-; CHECK-NEXT: .byte 0
-; CHECK-NEXT: .byte 32
-; CHECK-NEXT: .byte 0
-; CHECK-NEXT: .byte 0
-; CHECK-NEXT: .byte 0
-; CHECK-NEXT: .byte 32
-; CHECK-NEXT: .byte 0
-; CHECK-NEXT: .byte 0
-; CHECK-NEXT: .byte 0
-
-; A zero-initialized global
-@zeroInitGlobal = internal global [32 x i8] zeroinitializer
-
-; DUMP-NEXT: @__$rz0 = internal global [32 x i8] zeroinitializer
-; DUMP-NEXT: @zeroInitGlobal = internal global [32 x i8] zeroinitializer
-; DUMP-NEXT: @__$rz1 = internal global [32 x i8] zeroinitializer
-
-; CHECK-LABEL: .type __$rz0,%object
-; CHECK-NEXT: .section .bss
-; CHECK-NEXT: .p2align 5
-; CHECK-NEXT: __$rz0:
-; CHECK-LABEL: .type zeroInitGlobal,%object
-; CHECK-NEXT: .section .bss
-; CHECK-NEXT: .p2align 5
-; CHECK-NEXT: zeroInitGlobal:
-; CHECK-LABEL: .type __$rz1,%object
-; CHECK-NEXT: .section .bss
-; CHECK-NEXT: __$rz1:
-
-; A constant-initialized global
-@constInitGlobal = internal constant [32 x i8] c"ABCDEFGHIJKLMNOPQRSTUVWXYZ012345"
-
-; CHECK-LABEL: .type __$rz2,%object
-; CHECK-NEXT: .section .rodata
-; CHECK-NEXT: .p2align 5
-; CHECK-NEXT: __$rz2:
-; CHECK-LABEL: .type constInitGlobal,%object
-; CHECK-NEXT: .section .rodata
-; CHECK-NEXT: .p2align 5
-; CHECK-NEXT: constInitGlobal:
-; CHECK-LABEL: .type __$rz3,%object
-; CHECK-NEXT: .section .rodata
-; CHECK-NEXT: __$rz3:
-
-; DUMP-NEXT: @__$rz2 = internal constant [32 x i8] c"RRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRR"
-; DUMP-NEXT: @constInitGlobal = internal constant [32 x i8] c"ABCDEFGHIJKLMNOPQRSTUVWXYZ012345"
-; DUMP-NEXT: @__$rz3 = internal constant [32 x i8] c"RRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRR"
-
-; A regular global
-@regInitGlobal = internal global [32 x i8] c"ABCDEFGHIJKLMNOPQRSTUVWXYZ012345"
-
-; DUMP-NEXT: @__$rz4 = internal global [32 x i8] c"RRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRR"
-; DUMP-NEXT: @regInitGlobal = internal global [32 x i8] c"ABCDEFGHIJKLMNOPQRSTUVWXYZ012345"
-; DUMP-NEXT: @__$rz5 = internal global [32 x i8] c"RRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRR"
-
-; CHECK-LABEL: .type __$rz4,%object
-; CHECK-NEXT: .section .data
-; CHECK-NEXT: .p2align 5
-; CHECK-NEXT: __$rz4:
-; CHECK-LABEL: .type regInitGlobal,%object
-; CHECK-NEXT: .section .data
-; CHECK-NEXT: .p2align 5
-; CHECK-NEXT: regInitGlobal:
-; CHECK-LABEL: .type __$rz5,%object
-; CHECK-NEXT: .section .data
-; CHECK-NEXT: __$rz5:
-
-define internal void @func() {
- ret void
-}
-
-; DUMP-LABEL: define internal void @func() {
-; CHECK-LABEL: func:
\ No newline at end of file
diff --git a/third_party/subzero/tests_lit/asan_tests/globalreplacement.ll b/third_party/subzero/tests_lit/asan_tests/globalreplacement.ll
deleted file mode 100644
index d0f23d4..0000000
--- a/third_party/subzero/tests_lit/asan_tests/globalreplacement.ll
+++ /dev/null
@@ -1,79 +0,0 @@
-; Test that global pointers to allocation functions are replaced
-
-; REQUIRES: allow_dump
-
-; RUN: %p2i -i %s --args -verbose=global_init -threads=0 -fsanitize-address \
-; RUN: -allow-externally-defined-symbols | FileCheck --check-prefix=DUMP %s
-
-declare external i32 @malloc(i32)
-declare external i32 @realloc(i32, i32)
-declare external i32 @calloc(i32, i32)
-declare external void @free(i32)
-declare external void @foo()
-
-@global_malloc = internal global i32 ptrtoint (i32 (i32)* @malloc to i32)
-@global_realloc = internal global i32 ptrtoint (i32 (i32, i32)* @realloc to i32)
-@global_calloc = internal global i32 ptrtoint (i32 (i32, i32)* @calloc to i32)
-@global_free = internal global i32 ptrtoint (void (i32)* @free to i32)
-@global_foo = internal global i32 ptrtoint (void ()* @foo to i32)
-
-@constant_malloc = internal constant i32 ptrtoint (i32 (i32)* @malloc to i32)
-@constant_realloc = internal constant i32 ptrtoint (i32 (i32, i32)* @realloc to i32)
-@constant_calloc = internal constant i32 ptrtoint (i32 (i32, i32)* @calloc to i32)
-@constant_free = internal constant i32 ptrtoint (void (i32)* @free to i32)
-@constant_foo = internal constant i32 ptrtoint (void ()* @foo to i32)
-
-@multiple_initializers = internal global <{i32, i32}> <{i32 ptrtoint (i32 (i32)* @malloc to i32), i32 ptrtoint (void (i32)* @free to i32)}>
-
-define void @func() {
- ret void
-}
-
-; DUMP: Instrumented Globals
-; DUMP-NEXT: @__$rz_array
-; DUMP-NEXT: @__$rz_sizes
-; DUMP-NEXT: @__$rz0
-; DUMP-NEXT: @global_malloc = internal global i32
-; DUMP-SAME: ptrtoint (i32 (i32)* @__asan_malloc to i32)
-; DUMP-NEXT: @__$rz1
-; DUMP-NEXT: @__$rz2
-; DUMP-NEXT: @global_realloc = internal global i32
-; DUMP-SAME: ptrtoint (i32 (i32, i32)* @__asan_realloc to i32)
-; DUMP-NEXT: @__$rz3
-; DUMP-NEXT: @__$rz4
-; DUMP-NEXT: @global_calloc = internal global i32
-; DUMP-SAME: ptrtoint (i32 (i32, i32)* @__asan_calloc to i32)
-; DUMP-NEXT: @__$rz5
-; DUMP-NEXT: @__$rz6
-; DUMP-NEXT: @global_free = internal global i32
-; DUMP-SAME: ptrtoint (void (i32)* @__asan_free to i32)
-; DUMP-NEXT: @__$rz7
-; DUMP-NEXT: @__$rz8
-; DUMP-NEXT: @global_foo = internal global i32
-; DUMP-SAME: ptrtoint (void ()* @foo to i32)
-; DUMP-NEXT: @__$rz9
-; DUMP-NEXT: @__$rz10
-; DUMP-NEXT: @constant_malloc = internal constant i32
-; DUMP-SAME: ptrtoint (i32 (i32)* @__asan_malloc to i32)
-; DUMP-NEXT: @__$rz11
-; DUMP-NEXT: @__$rz12
-; DUMP-NEXT: @constant_realloc = internal constant i32
-; DUMP-SAME: ptrtoint (i32 (i32, i32)* @__asan_realloc to i32)
-; DUMP-NEXT: @__$rz13
-; DUMP-NEXT: @__$rz14
-; DUMP-NEXT: @constant_calloc = internal constant i32
-; DUMP-SAME: ptrtoint (i32 (i32, i32)* @__asan_calloc to i32)
-; DUMP-NEXT: @__$rz15
-; DUMP-NEXT: @__$rz16
-; DUMP-NEXT: @constant_free = internal constant i32
-; DUMP-SAME: ptrtoint (void (i32)* @__asan_free to i32)
-; DUMP-NEXT: @__$rz17
-; DUMP-NEXT: @__$rz18
-; DUMP-NEXT: @constant_foo = internal constant i32
-; DUMP-SAME: ptrtoint (void ()* @foo to i32)
-; DUMP-NEXT: @__$rz19
-; DUMP-NEXT: @__$rz20
-; DUMP-NEXT: @multiple_initializers = internal global <{ i32, i32 }>
-; DUMP-SAME: <{ i32 ptrtoint (i32 (i32)* @__asan_malloc to i32),
-; DUMP-SAME: i32 ptrtoint (void (i32)* @__asan_free to i32) }>
-; DUMP-NEXT: @__$rz21
\ No newline at end of file
diff --git a/third_party/subzero/tests_lit/asan_tests/instrumentload.ll b/third_party/subzero/tests_lit/asan_tests/instrumentload.ll
deleted file mode 100644
index fae7ea6..0000000
--- a/third_party/subzero/tests_lit/asan_tests/instrumentload.ll
+++ /dev/null
@@ -1,40 +0,0 @@
-; Test for a call to __asan_check() preceding loads
-
-; REQUIRES: allow_dump
-
-; RUN: %p2i -i %s --args -verbose=inst -threads=0 -fsanitize-address \
-; RUN: | FileCheck --check-prefix=DUMP %s
-
-; A function with a local variable that does the loads
-define internal void @doLoads(i32 %arg8, i32 %arg16, i32 %arg32, i32 %arg64,
- i32 %arg128) {
- %srcLocal8 = inttoptr i32 %arg8 to i8*
- %srcLocal16 = inttoptr i32 %arg16 to i16*
- %srcLocal32 = inttoptr i32 %arg32 to i32*
- %srcLocal64 = inttoptr i32 %arg64 to i64*
- %srcLocal128 = inttoptr i32 %arg128 to <4 x i32>*
-
- %dest11 = load i8, i8* %srcLocal8, align 1
- %dest12 = load i16, i16* %srcLocal16, align 1
- %dest13 = load i32, i32* %srcLocal32, align 1
- %dest14 = load i64, i64* %srcLocal64, align 1
- %dest15 = load <4 x i32>, <4 x i32>* %srcLocal128, align 4
-
- ret void
-}
-
-; DUMP-LABEL: ================ Instrumented CFG ================
-; DUMP-NEXT: define internal void @doLoads(
-; DUMP-NEXT: __0:
-; DUMP-NEXT: call void @__asan_check_load(i32 %arg8, i32 1)
-; DUMP-NEXT: %dest11 = load i8, i8* %arg8, align 1
-; DUMP-NEXT: call void @__asan_check_load(i32 %arg16, i32 2)
-; DUMP-NEXT: %dest12 = load i16, i16* %arg16, align 1
-; DUMP-NEXT: call void @__asan_check_load(i32 %arg32, i32 4)
-; DUMP-NEXT: %dest13 = load i32, i32* %arg32, align 1
-; DUMP-NEXT: call void @__asan_check_load(i32 %arg64, i32 8)
-; DUMP-NEXT: %dest14 = load i64, i64* %arg64, align 1
-; DUMP-NEXT: call void @__asan_check_load(i32 %arg128, i32 16)
-; DUMP-NEXT: %dest15 = load <4 x i32>, <4 x i32>* %arg128, align 4
-; DUMP: ret void
-; DUMP-NEXT: }
diff --git a/third_party/subzero/tests_lit/asan_tests/instrumentlocals.ll b/third_party/subzero/tests_lit/asan_tests/instrumentlocals.ll
deleted file mode 100644
index 38688fe..0000000
--- a/third_party/subzero/tests_lit/asan_tests/instrumentlocals.ll
+++ /dev/null
@@ -1,74 +0,0 @@
-; Test for insertion of redzones around local variables
-
-; REQUIRES: allow_dump
-
-; RUN: %p2i -i %s --args -verbose=inst -threads=0 -fsanitize-address \
-; RUN: -allow-externally-defined-symbols | FileCheck --check-prefix=DUMP %s
-
-; Function with local variables to be instrumented
-define internal void @func() {
- %local1 = alloca i8, i32 4, align 4
- %local2 = alloca i8, i32 32, align 1
- %local3 = alloca i8, i32 13, align 2
- %local4 = alloca i8, i32 75, align 4
- %local5 = alloca i8, i32 64, align 8
- %i1 = ptrtoint i8* %local1 to i32
- %i2 = ptrtoint i8* %local2 to i32
- %i3 = ptrtoint i8* %local3 to i32
- %i4 = ptrtoint i8* %local4 to i32
- %i5 = ptrtoint i8* %local5 to i32
- call void @foo(i32 %i1)
- call void @foo(i32 %i2)
- call void @foo(i32 %i3)
- call void @foo(i32 %i4)
- call void @foo(i32 %i5)
- ret void
-}
-
-declare external void @foo(i32)
-
-; DUMP-LABEL: ================ Instrumented CFG ================
-; DUMP-NEXT: define internal void @func() {
-; DUMP-NEXT: __0:
-; DUMP-NEXT: %__$rz0 = alloca i8, i32 32, align 8
-; DUMP-NEXT: %local1 = alloca i8, i32 64, align 8
-; DUMP-NEXT: %local2 = alloca i8, i32 64, align 8
-; DUMP-NEXT: %local3 = alloca i8, i32 64, align 8
-; DUMP-NEXT: %local4 = alloca i8, i32 128, align 8
-; DUMP-NEXT: %local5 = alloca i8, i32 96, align 8
-; DUMP-NEXT: %shadowIndex = lshr i32 %__$rz0, 3
-; DUMP-NEXT: %firstShadowLoc = add i32 %shadowIndex, 536870912
-; DUMP-NEXT: %__8 = add i32 %firstShadowLoc, 0
-; DUMP-NEXT: store i32 -1, i32* %__8, align 1
-; DUMP-NEXT: %__9 = add i32 %firstShadowLoc, 4
-; DUMP-NEXT: store i32 -252, i32* %__9, align 1
-; DUMP-NEXT: %__10 = add i32 %firstShadowLoc, 8
-; DUMP-NEXT: store i32 -1, i32* %__10, align 1
-; DUMP-NEXT: %__11 = add i32 %firstShadowLoc, 16
-; DUMP-NEXT: store i32 -1, i32* %__11, align 1
-; DUMP-NEXT: %__12 = add i32 %firstShadowLoc, 20
-; DUMP-NEXT: store i32 -64256, i32* %__12, align 1
-; DUMP-NEXT: %__13 = add i32 %firstShadowLoc, 24
-; DUMP-NEXT: store i32 -1, i32* %__13, align 1
-; DUMP-NEXT: %__14 = add i32 %firstShadowLoc, 36
-; DUMP-NEXT: store i32 -64768, i32* %__14, align 1
-; DUMP-NEXT: %__15 = add i32 %firstShadowLoc, 40
-; DUMP-NEXT: store i32 -1, i32* %__15, align 1
-; DUMP-NEXT: %__16 = add i32 %firstShadowLoc, 52
-; DUMP-NEXT: store i32 -1, i32* %__16, align 1
-; DUMP-NEXT: call void @foo(i32 %local1)
-; DUMP-NEXT: call void @foo(i32 %local2)
-; DUMP-NEXT: call void @foo(i32 %local3)
-; DUMP-NEXT: call void @foo(i32 %local4)
-; DUMP-NEXT: call void @foo(i32 %local5)
-; DUMP-NEXT: store i32 0, i32* %__8, align 1
-; DUMP-NEXT: store i32 0, i32* %__9, align 1
-; DUMP-NEXT: store i32 0, i32* %__10, align 1
-; DUMP-NEXT: store i32 0, i32* %__11, align 1
-; DUMP-NEXT: store i32 0, i32* %__12, align 1
-; DUMP-NEXT: store i32 0, i32* %__13, align 1
-; DUMP-NEXT: store i32 0, i32* %__14, align 1
-; DUMP-NEXT: store i32 0, i32* %__15, align 1
-; DUMP-NEXT: store i32 0, i32* %__16, align 1
-; DUMP-NEXT: ret void
-; DUMP-NEXT: }
diff --git a/third_party/subzero/tests_lit/asan_tests/instrumentmalloc.ll b/third_party/subzero/tests_lit/asan_tests/instrumentmalloc.ll
deleted file mode 100644
index 6cdd9fa..0000000
--- a/third_party/subzero/tests_lit/asan_tests/instrumentmalloc.ll
+++ /dev/null
@@ -1,29 +0,0 @@
-; Test that calls to malloc() and free() are replaced
-
-; REQUIRES: allow_dump
-
-; RUN: %p2i -i %s --args -verbose=inst -threads=0 -fsanitize-address \
-; RUN: --allow-externally-defined-symbols | FileCheck --check-prefix=DUMP %s
-
-declare external i32 @malloc(i32)
-declare external i32 @calloc(i32, i32)
-declare external i32 @realloc(i32, i32)
-declare external void @free(i32)
-
-define internal void @func() {
- %ptr1 = call i32 @malloc(i32 42)
- %ptr2 = call i32 @calloc(i32 12, i32 42)
- %ptr3 = call i32 @realloc(i32 0, i32 100)
- call void @free(i32 %ptr1)
- ret void
-}
-
-; DUMP-LABEL: ================ Instrumented CFG ================
-; DUMP-NEXT: define internal void @func() {
-; DUMP-NEXT: __0:
-; DUMP-NEXT: %ptr1 = call i32 @__asan_malloc(i32 42)
-; DUMP-NEXT: %ptr2 = call i32 @__asan_calloc(i32 12, i32 42)
-; DUMP-NEXT: %ptr3 = call i32 @__asan_realloc(i32 0, i32 100)
-; DUMP-NEXT: call void @__asan_free(i32 %ptr1)
-; DUMP-NEXT: ret void
-; DUMP-NEXT: }
diff --git a/third_party/subzero/tests_lit/asan_tests/instrumentstore.ll b/third_party/subzero/tests_lit/asan_tests/instrumentstore.ll
deleted file mode 100644
index d486f91..0000000
--- a/third_party/subzero/tests_lit/asan_tests/instrumentstore.ll
+++ /dev/null
@@ -1,40 +0,0 @@
-; Test for a call to __asan_check() preceding stores
-
-; REQUIRES: allow_dump
-
-; RUN: %p2i -i %s --args -verbose=inst -threads=0 -fsanitize-address \
-; RUN: | FileCheck --check-prefix=DUMP %s
-
-; A function with a local variable that does the stores
-define internal void @doStores(<4 x i32> %vecSrc, i32 %arg8, i32 %arg16,
- i32 %arg32, i32 %arg64, i32 %arg128) {
- %destLocal8 = inttoptr i32 %arg8 to i8*
- %destLocal16 = inttoptr i32 %arg16 to i16*
- %destLocal32 = inttoptr i32 %arg32 to i32*
- %destLocal64 = inttoptr i32 %arg64 to i64*
- %destLocal128 = inttoptr i32 %arg128 to <4 x i32>*
-
- store i8 42, i8* %destLocal8, align 1
- store i16 42, i16* %destLocal16, align 1
- store i32 42, i32* %destLocal32, align 1
- store i64 42, i64* %destLocal64, align 1
- store <4 x i32> %vecSrc, <4 x i32>* %destLocal128, align 4
-
- ret void
-}
-
-; DUMP-LABEL: ================ Instrumented CFG ================
-; DUMP-NEXT: define internal void @doStores(
-; DUMP-NEXT: __0:
-; DUMP-NEXT: call void @__asan_check_store(i32 %arg8, i32 1)
-; DUMP-NEXT: store i8 42, i8* %arg8, align 1
-; DUMP-NEXT: call void @__asan_check_store(i32 %arg16, i32 2)
-; DUMP-NEXT: store i16 42, i16* %arg16, align 1
-; DUMP-NEXT: call void @__asan_check_store(i32 %arg32, i32 4)
-; DUMP-NEXT: store i32 42, i32* %arg32, align 1
-; DUMP-NEXT: call void @__asan_check_store(i32 %arg64, i32 8)
-; DUMP-NEXT: store i64 42, i64* %arg64, align 1
-; DUMP-NEXT: call void @__asan_check_store(i32 %arg128, i32 16)
-; DUMP-NEXT: store <4 x i32> %vecSrc, <4 x i32>* %arg128, align 4
-; DUMP: ret void
-; DUMP-NEXT: }
diff --git a/third_party/subzero/tests_lit/asan_tests/localreplacement.ll b/third_party/subzero/tests_lit/asan_tests/localreplacement.ll
deleted file mode 100644
index b2c1216..0000000
--- a/third_party/subzero/tests_lit/asan_tests/localreplacement.ll
+++ /dev/null
@@ -1,66 +0,0 @@
-; Test that loads of local pointers to allocation functions and stores
-; of pointers to allocation functions are instrumented.
-
-; REQUIRES: allow_dump
-
-; RUN: %p2i -i %s --args -verbose=inst -threads=0 -fsanitize-address \
-; RUN: -allow-externally-defined-symbols | FileCheck --check-prefix=DUMP %s
-
-declare external i32 @malloc(i32)
-declare external i32 @realloc(i32, i32)
-declare external i32 @calloc(i32, i32)
-declare external void @free(i32)
-
-define internal void @func(i32 %store_loc) {
- %store_dest = inttoptr i32 %store_loc to i32*
-
- %malloc_ptr = bitcast i32 (i32)* @malloc to i32*
- %realloc_ptr = bitcast i32 (i32, i32)* @realloc to i32*
- %calloc_ptr = bitcast i32 (i32, i32)* @calloc to i32*
- %free_ptr = bitcast void (i32)* @free to i32*
-
- %malloc_addr = ptrtoint i32 (i32)* @malloc to i32
- %realloc_addr = ptrtoint i32 (i32, i32)* @realloc to i32
- %calloc_addr = ptrtoint i32 (i32, i32)* @calloc to i32
- %free_addr = ptrtoint void (i32)* @free to i32
-
- store i32 %malloc_addr, i32* %store_dest, align 1
- store i32 %realloc_addr, i32* %store_dest, align 1
- store i32 %calloc_addr, i32* %store_dest, align 1
- store i32 %free_addr, i32* %store_dest, align 1
-
- %local_malloc = load i32, i32* %malloc_ptr, align 1
- %local_realloc = load i32, i32* %realloc_ptr, align 1
- %local_calloc = load i32, i32* %calloc_ptr, align 1
- %local_free = load i32, i32* %free_ptr, align 1
-
- %local_mallocfunc = inttoptr i32 %local_malloc to i32 (i32)*
- %local_reallocfunc = inttoptr i32 %local_realloc to i32 (i32, i32)*
- %local_callocfunc = inttoptr i32 %local_calloc to i32 (i32, i32)*
- %local_freefunc = inttoptr i32 %local_free to void (i32)*
-
- %buf = call i32 %local_mallocfunc(i32 42)
- call void %local_freefunc(i32 %buf)
- ret void
-}
-
-; DUMP-LABEL: ================ Instrumented CFG ================
-; DUMP-NEXT: @func(i32 %store_loc) {
-; DUMP-NEXT: __0:
-; DUMP-NEXT: call void @__asan_check_store(i32 %store_loc, i32 4)
-; DUMP-NEXT: store i32 @__asan_malloc, i32* %store_loc, align 1
-; DUMP-NEXT: store i32 @__asan_realloc, i32* %store_loc, align 1
-; DUMP-NEXT: store i32 @__asan_calloc, i32* %store_loc, align 1
-; DUMP-NEXT: store i32 @__asan_free, i32* %store_loc, align 1
-; DUMP-NEXT: call void @__asan_check_load(i32 @__asan_malloc, i32 4)
-; DUMP-NEXT: %local_malloc = load i32, i32* @__asan_malloc, align 1
-; DUMP-NEXT: call void @__asan_check_load(i32 @__asan_realloc, i32 4)
-; DUMP-NEXT: %local_realloc = load i32, i32* @__asan_realloc, align 1
-; DUMP-NEXT: call void @__asan_check_load(i32 @__asan_calloc, i32 4)
-; DUMP-NEXT: %local_calloc = load i32, i32* @__asan_calloc, align 1
-; DUMP-NEXT: call void @__asan_check_load(i32 @__asan_free, i32 4)
-; DUMP-NEXT: %local_free = load i32, i32* @__asan_free, align 1
-; DUMP-NEXT: %buf = call i32 %local_malloc(i32 42)
-; DUMP-NEXT: call void %local_free(i32 %buf)
-; DUMP-NEXT: ret void
-; DUMP-NEXT: }
diff --git a/third_party/subzero/tests_lit/asan_tests/multiple_returns.ll b/third_party/subzero/tests_lit/asan_tests/multiple_returns.ll
deleted file mode 100644
index ec5ed6a..0000000
--- a/third_party/subzero/tests_lit/asan_tests/multiple_returns.ll
+++ /dev/null
@@ -1,53 +0,0 @@
-; Check that functions with multiple returns are correctly instrumented
-
-; REQUIRES: allow_dump
-
-; RUN: %p2i -i %s --args -verbose=inst -threads=0 -fsanitize-address \
-; RUN: | FileCheck --check-prefix=DUMP %s
-
-define internal void @ret_twice(i32 %condarg) {
- %local1 = alloca i8, i32 4, align 4
- %local2 = alloca i8, i32 4, align 4
- %cond = icmp ne i32 %condarg, 0
- br i1 %cond, label %yes, label %no
-yes:
- ret void
-no:
- ret void
-}
-
-; DUMP-LABEL:================ Instrumented CFG ================
-; DUMP-NEXT: define internal void @ret_twice(i32 %condarg) {
-; DUMP-NEXT: __0:
-; DUMP-NEXT: %__$rz0 = alloca i8, i32 32, align 8
-; DUMP-NEXT: %local1 = alloca i8, i32 64, align 8
-; DUMP-NEXT: %local2 = alloca i8, i32 64, align 8
-; DUMP-NEXT: %shadowIndex = lshr i32 %__$rz0, 3
-; DUMP-NEXT: %firstShadowLoc = add i32 %shadowIndex, 53687091
-; DUMP-NEXT: %__7 = add i32 %firstShadowLoc, 0
-; DUMP-NEXT: store i32 -1, i32* %__7, align 1
-; DUMP-NEXT: %__8 = add i32 %firstShadowLoc, 4
-; DUMP-NEXT: store i32 -252, i32* %__8, align 1
-; DUMP-NEXT: %__9 = add i32 %firstShadowLoc, 8
-; DUMP-NEXT: store i32 -1, i32* %__9, align 1
-; DUMP-NEXT: %__10 = add i32 %firstShadowLoc, 12
-; DUMP-NEXT: store i32 -252, i32* %__10, align 1
-; DUMP-NEXT: %__11 = add i32 %firstShadowLoc, 16
-; DUMP-NEXT: store i32 -1, i32* %__11, align 1
-; DUMP-NEXT: %cond = icmp ne i32 %condarg, 0
-; DUMP-NEXT: br i1 %cond, label %yes, label %no
-; DUMP-NEXT: yes:
-; DUMP-NEXT: store i32 0, i32* %__7, align 1
-; DUMP-NEXT: store i32 0, i32* %__8, align 1
-; DUMP-NEXT: store i32 0, i32* %__9, align 1
-; DUMP-NEXT: store i32 0, i32* %__10, align 1
-; DUMP-NEXT: store i32 0, i32* %__11, align 1
-; DUMP-NEXT: ret void
-; DUMP-NEXT: no:
-; DUMP-NEXT: store i32 0, i32* %__7, align 1
-; DUMP-NEXT: store i32 0, i32* %__8, align 1
-; DUMP-NEXT: store i32 0, i32* %__9, align 1
-; DUMP-NEXT: store i32 0, i32* %__10, align 1
-; DUMP-NEXT: store i32 0, i32* %__11, align 1
-; DUMP-NEXT: ret void
-; DUMP-NEXT: }
diff --git a/third_party/subzero/tests_lit/asan_tests/no_globals.ll b/third_party/subzero/tests_lit/asan_tests/no_globals.ll
deleted file mode 100644
index 1a3d7f9..0000000
--- a/third_party/subzero/tests_lit/asan_tests/no_globals.ll
+++ /dev/null
@@ -1,19 +0,0 @@
-; Check that Subzero can instrument _start when there are no globals.
-; Previously Subzero would deadlock when _start was the first function. Also
-; test that instrumenting start does not deadlock waiting for nonexistent
-; global initializers to be lowered.
-
-; REQUIRES: no_minimal_build
-
-; RUN: %p2i -i %s --args -verbose=inst -fsanitize-address \
-; RUN: | FileCheck --check-prefix=DUMP %s
-
-; RUN: %p2i -i %s --args -verbose=inst -fsanitize-address -threads=0 \
-; RUN: | FileCheck --check-prefix=DUMP %s
-
-
-define void @_start(i32 %arg) {
- ret void
-}
-
-; DUMP: __asan_init
diff --git a/third_party/subzero/tests_lit/asan_tests/quarantine.ll b/third_party/subzero/tests_lit/asan_tests/quarantine.ll
deleted file mode 100644
index 91ff3a6..0000000
--- a/third_party/subzero/tests_lit/asan_tests/quarantine.ll
+++ /dev/null
@@ -1,69 +0,0 @@
-; Test that the quarantine for recently freed objects works
-
-; REQUIRES: no_minimal_build
-
-; Test with an illegal load from a freed block
-; RUN: llvm-as %s -o - | pnacl-freeze > %t.pexe && %S/../../pydir/szbuild.py \
-; RUN: --fsanitize-address --sz=-allow-externally-defined-symbols \
-; RUN: %t.pexe -o %t && %t 2>&1 | FileCheck --check-prefix=LOAD %s
-; RUN: llvm-as %s -o - | pnacl-freeze > %t.pexe && %S/../../pydir/szbuild.py \
-; RUN: --fsanitize-address --sz=-allow-externally-defined-symbols -O2 \
-; RUN: %t.pexe -o %t && %t 2>&1 | FileCheck --check-prefix=LOAD %s
-
-; Test with an illegal store to a freed block
-; RUN: llvm-as %s -o - | pnacl-freeze > %t.pexe && %S/../../pydir/szbuild.py \
-; RUN: --fsanitize-address --sz=-allow-externally-defined-symbols \
-; RUN: %t.pexe -o %t && %t 1 2>&1 | FileCheck --check-prefix=STORE %s
-; RUN: llvm-as %s -o - | pnacl-freeze > %t.pexe && %S/../../pydir/szbuild.py \
-; RUN: --fsanitize-address --sz=-allow-externally-defined-symbols -O2 \
-; RUN: %t.pexe -o %t && %t 1 2>&1 | FileCheck --check-prefix=STORE %s
-
-; Test that freed objects eventually get out of quarantine and are unpoisoned
-; RUN: llvm-as %s -o - | pnacl-freeze > %t.pexe && %S/../../pydir/szbuild.py \
-; RUN: --fsanitize-address --sz=-allow-externally-defined-symbols \
-; RUN: %t.pexe -o %t && %t 1 2 2>&1 | FileCheck --check-prefix=NONE %s \
-; RUN: --allow-empty
-; RUN: llvm-as %s -o - | pnacl-freeze > %t.pexe && %S/../../pydir/szbuild.py \
-; RUN: --fsanitize-address --sz=-allow-externally-defined-symbols -O2 \
-; RUN: %t.pexe -o %t && %t 1 2 2>&1 | FileCheck --check-prefix=NONE %s \
-; RUN: --allow-empty
-
-declare external i32 @malloc(i32)
-declare external void @free(i32)
-declare external void @exit(i32)
-
-; make three 100MB allocations
-define void @_start(i32 %arg) {
- %argcaddr = add i32 %arg, 8
- %argcptr = inttoptr i32 %argcaddr to i32*
- %argc = load i32, i32* %argcptr, align 1
- %alloc1addr = call i32 @malloc(i32 104857600)
- %alloc2addr = call i32 @malloc(i32 104857600)
- %alloc3addr = call i32 @malloc(i32 104857600)
- %alloc1 = inttoptr i32 %alloc1addr to i32*
- %alloc2 = inttoptr i32 %alloc2addr to i32*
- %alloc3 = inttoptr i32 %alloc3addr to i32*
- call void @free(i32 %alloc1addr)
- call void @free(i32 %alloc2addr)
- call void @free(i32 %alloc3addr)
- switch i32 %argc, label %error [i32 1, label %bad_load
- i32 2, label %bad_store
- i32 3, label %no_err]
-bad_load:
- %result_load = load i32, i32* %alloc2, align 1
- br label %error
-bad_store:
- store i32 42, i32* %alloc3, align 1
- br label %error
-no_err:
- %result_no_err = load i32, i32* %alloc1, align 1
- call void @exit(i32 0)
- unreachable
-error:
- call void @exit(i32 1)
- unreachable
-}
-
-; LOAD: Illegal 4 byte load from freed object at
-; STORE: Illegal 4 byte store to freed object at
-; NONE-NOT: Illegal
diff --git a/third_party/subzero/tests_lit/asan_tests/realloc_shrink.ll b/third_party/subzero/tests_lit/asan_tests/realloc_shrink.ll
deleted file mode 100644
index 9db05fa..0000000
--- a/third_party/subzero/tests_lit/asan_tests/realloc_shrink.ll
+++ /dev/null
@@ -1,26 +0,0 @@
-; Test that shrinking an allocation updates the redzones
-
-; REQUIRES: no_minimal_build
-
-; RUN: llvm-as %s -o - | pnacl-freeze > %t.pexe && %S/../../pydir/szbuild.py \
-; RUN: --fsanitize-address --sz=-allow-externally-defined-symbols \
-; RUN: %t.pexe -o %t && %t 2>&1 | FileCheck %s
-
-
-declare external i32 @malloc(i32)
-declare external i32 @realloc(i32, i32)
-declare external void @free(i32)
-
-define void @_start(i32 %arg) {
- %ptr16 = call i32 @malloc(i32 16)
- %off12a = add i32 %ptr16, 12
- %offptra = inttoptr i32 %off12a to i32*
- %resa = load i32, i32* %offptra, align 1
- %ptr8 = call i32 @realloc(i32 %ptr16, i32 8)
- %off12b = add i32 %ptr8, 12
- %offptrb = inttoptr i32 %off12b to i8*
- %resb = load i8, i8* %offptrb, align 1
- ret void
-}
-
-; CHECK: Illegal 1 byte load from heap object at
diff --git a/third_party/subzero/tests_lit/asan_tests/scatteredallocas.ll b/third_party/subzero/tests_lit/asan_tests/scatteredallocas.ll
deleted file mode 100644
index 5c4588c..0000000
--- a/third_party/subzero/tests_lit/asan_tests/scatteredallocas.ll
+++ /dev/null
@@ -1,63 +0,0 @@
-; Test that static allocas throughout the entry block are instrumented correctly
-
-; REQUIRES: allow_dump
-
-; RUN: %p2i -i %s --args -verbose=inst -threads=0 -fsanitize-address \
-; RUN: -allow-externally-defined-symbols | FileCheck --check-prefix=DUMP %s
-
-declare external i32 @malloc(i32)
-declare external void @free(i32)
-
-define void @func() {
- %a = alloca i8, i32 4, align 4
- %m1 = call i32 @malloc(i32 42)
- %b = alloca i8, i32 16, align 4
- store i8 50, i8* %a, align 1
- %c = alloca i8, i32 8, align 8
- call void @free(i32 %m1)
- %d = alloca i8, i32 12, align 4
- ret void
-}
-
-; DUMP-LABEL: ================ Instrumented CFG ================
-; DUMP-NEXT: define void @func() {
-; DUMP-NEXT: __0:
-; DUMP-NEXT: %__$rz0 = alloca i8, i32 32, align 8
-; DUMP-NEXT: %a = alloca i8, i32 64, align 8
-; DUMP-NEXT: %b = alloca i8, i32 64, align 8
-; DUMP-NEXT: %c = alloca i8, i32 64, align 8
-; DUMP-NEXT: %d = alloca i8, i32 64, align 8
-; DUMP-NEXT: %shadowIndex = lshr i32 %__$rz0, 3
-; DUMP-NEXT: %firstShadowLoc = add i32 %shadowIndex, 536870912
-; DUMP-NEXT: %__8 = add i32 %firstShadowLoc, 0
-; DUMP-NEXT: store i32 -1, i32* %__8, align 1
-; DUMP-NEXT: %__9 = add i32 %firstShadowLoc, 4
-; DUMP-NEXT: store i32 -252, i32* %__9, align 1
-; DUMP-NEXT: %__10 = add i32 %firstShadowLoc, 8
-; DUMP-NEXT: store i32 -1, i32* %__10, align 1
-; DUMP-NEXT: %__11 = add i32 %firstShadowLoc, 12
-; DUMP-NEXT: store i32 -65536, i32* %__11, align 1
-; DUMP-NEXT: %__12 = add i32 %firstShadowLoc, 16
-; DUMP-NEXT: store i32 -1, i32* %__12, align 1
-; DUMP-NEXT: %__13 = add i32 %firstShadowLoc, 20
-; DUMP-NEXT: store i32 -256, i32* %__13, align 1
-; DUMP-NEXT: %__14 = add i32 %firstShadowLoc, 24
-; DUMP-NEXT: store i32 -1, i32* %__14, align 1
-; DUMP-NEXT: %__15 = add i32 %firstShadowLoc, 28
-; DUMP-NEXT: store i32 -64512, i32* %__15, align 1
-; DUMP-NEXT: %__16 = add i32 %firstShadowLoc, 32
-; DUMP-NEXT: store i32 -1, i32* %__16, align 1
-; DUMP-NEXT: %m1 = call i32 @__asan_malloc(i32 42)
-; DUMP-NEXT: store i8 50, i8* %a, align 1
-; DUMP-NEXT: call void @__asan_free(i32 %m1)
-; DUMP-NEXT: store i32 0, i32* %__8, align 1
-; DUMP-NEXT: store i32 0, i32* %__9, align 1
-; DUMP-NEXT: store i32 0, i32* %__10, align 1
-; DUMP-NEXT: store i32 0, i32* %__11, align 1
-; DUMP-NEXT: store i32 0, i32* %__12, align 1
-; DUMP-NEXT: store i32 0, i32* %__13, align 1
-; DUMP-NEXT: store i32 0, i32* %__14, align 1
-; DUMP-NEXT: store i32 0, i32* %__15, align 1
-; DUMP-NEXT: store i32 0, i32* %__16, align 1
-; DUMP-NEXT: ret void
-; DUMP-NEXT: }
\ No newline at end of file
diff --git a/third_party/subzero/tests_lit/asan_tests/startinitcall.ll b/third_party/subzero/tests_lit/asan_tests/startinitcall.ll
deleted file mode 100644
index a30f149..0000000
--- a/third_party/subzero/tests_lit/asan_tests/startinitcall.ll
+++ /dev/null
@@ -1,30 +0,0 @@
-; Test for a call to __asan_init in _start
-
-; REQUIRES: allow_dump
-
-; RUN: %p2i -i %s --args -verbose=inst -threads=0 -fsanitize-address \
-; RUN: | FileCheck --check-prefix=DUMP %s
-
-; notStart() should not be instrumented
-define internal void @notStart() {
- ret void
-}
-
-; DUMP-LABEL: ================ Instrumented CFG ================
-; DUMP-NEXT: define internal void @notStart() {
-; DUMP-NEXT: __0:
-; DUMP-NOT: __asan_init()
-; DUMP: ret void
-; DUMP-NEXT: }
-
-; _start() should be instrumented
-define void @_start() {
- ret void
-}
-
-; DUMP-LABEL: ================ Instrumented CFG ================
-; DUMP-NEXT: define void @_start() {
-; DUMP-NEXT: __0:
-; DUMP-NEXT: call void @__asan_init(i32 0, i32 @__$rz_array, i32 @__$rz_sizes)
-; DUMP-NEXT: ret void
-; DUMP-NEXT: }
diff --git a/third_party/subzero/tests_lit/asan_tests/wideloads.ll b/third_party/subzero/tests_lit/asan_tests/wideloads.ll
deleted file mode 100644
index 9b8d15e..0000000
--- a/third_party/subzero/tests_lit/asan_tests/wideloads.ll
+++ /dev/null
@@ -1,55 +0,0 @@
-; Test that potentially widened loads to not trigger an error report
-
-; REQUIRES: no_minimal_build
-
-; check for wide load exception
-; RUN: llvm-as %s -o - | pnacl-freeze > %t.pexe && %S/../../pydir/szbuild.py \
-; RUN: --fsanitize-address --sz=-allow-externally-defined-symbols \
-; RUN: %t.pexe -o %t && %t | FileCheck %s --check-prefix=WIDE --allow-empty
-
-; check for error reporting
-; RUN: llvm-as %s -o - | pnacl-freeze > %t.pexe && %S/../../pydir/szbuild.py \
-; RUN: --fsanitize-address --sz=-allow-externally-defined-symbols \
-; RUN: %t.pexe -o %t && %t 1 2>&1 | FileCheck %s --check-prefix=NOWIDE
-
-
-declare external void @exit(i32)
-
-define internal void @wide_load() {
- %str = alloca i8, i32 1, align 1
- %str4 = bitcast i8* %str to i32*
- %contents = load i32, i32* %str4, align 1
- call void @exit(i32 0)
- unreachable
-}
-
-define internal void @no_wide_load() {
- %str = alloca i8, i32 1, align 1
- %straddr = ptrtoint i8* %str to i32
- %off1addr = add i32 %straddr, 1
- %off1 = inttoptr i32 %off1addr to i8*
- %contents = load i8, i8* %off1, align 1
- call void @exit(i32 1)
- unreachable
-}
-
-; WIDE-NOT: Illegal
-; NOWIDE: Illegal 1 byte load from stack object at
-
-; use argc to determine which test routine to run
-define void @_start(i32 %arg) {
- %argcaddr = add i32 %arg, 8
- %argcptr = inttoptr i32 %argcaddr to i32*
- %argc = load i32, i32* %argcptr, align 1
- switch i32 %argc, label %error [i32 1, label %wide_load
- i32 2, label %no_wide_load]
-wide_load:
- call void @wide_load()
- br label %error
-no_wide_load:
- call void @no_wide_load()
- br label %error
-error:
- call void @exit(i32 1)
- unreachable
-}
\ No newline at end of file
diff --git a/third_party/subzero/tests_lit/assembler/arm32/add-vec.ll b/third_party/subzero/tests_lit/assembler/arm32/add-vec.ll
deleted file mode 100644
index ca64b46..0000000
--- a/third_party/subzero/tests_lit/assembler/arm32/add-vec.ll
+++ /dev/null
@@ -1,85 +0,0 @@
-; Show that we know how to translate vadd vector instructions.
-
-; REQUIRES: allow_dump
-
-; Compile using standalone assembler.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -O2 \
-; RUN: -reg-use q10,q11 \
-; RUN: | FileCheck %s --check-prefix=ASM
-
-; Show bytes in assembled standalone code.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -O2 \
-; RUN: -reg-use q10,q11 \
-; RUN: | FileCheck %s --check-prefix=DIS
-
-; Compile using integrated assembler.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -O2 \
-; RUN: -reg-use q10,q11 \
-; RUN: | FileCheck %s --check-prefix=IASM
-
-; Show bytes in assembled integrated code.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -O2 \
-; RUN: -reg-use q10,q11 \
-; RUN: | FileCheck %s --check-prefix=DIS
-
-define internal <4 x float> @testVaddFloat4(<4 x float> %v1, <4 x float> %v2) {
-; ASM-LABEL: testVaddFloat4:
-; DIS-LABEL: 00000000 <testVaddFloat4>:
-; IASM-LABEL: testVaddFloat4:
-
-entry:
- %res = fadd <4 x float> %v1, %v2
-
-; ASM: vadd.f32 q10, q10, q11
-; DIS: 8: f2444de6
-; IASM-NOT: vadd.f32
-
- ret <4 x float> %res
-}
-
-define internal <4 x i32> @testVadd4i32(<4 x i32> %v1, <4 x i32> %v2) {
-; ASM-LABEL: testVadd4i32:
-; DIS-LABEL: 00000020 <testVadd4i32>:
-; IASM-LABEL: testVadd4i32:
-
-entry:
- %res = add <4 x i32> %v1, %v2
-
-; ASM: vadd.i32 q10, q10, q11
-; DIS: 28: f26448e6
-; IASM-NOT: vadd.i32
-
- ret <4 x i32> %res
-}
-
-define internal <8 x i16> @testVadd8i16(<8 x i16> %v1, <8 x i16> %v2) {
-; ASM-LABEL: testVadd8i16:
-; DIS-LABEL: 00000040 <testVadd8i16>:
-; IASM-LABEL: testVadd8i16:
-
-entry:
- %res = add <8 x i16> %v1, %v2
-
-; ASM: vadd.i16 q10, q10, q11
-; DIS: 48: f25448e6
-; IASM-NOT: vadd.i16
-
- ret <8 x i16> %res
-}
-
-define internal <16 x i8> @testVadd16i8(<16 x i8> %v1, <16 x i8> %v2) {
-; ASM-LABEL: testVadd16i8:
-; DIS-LABEL: 00000060 <testVadd16i8>:
-; IASM-LABEL: testVadd16i8:
-
-entry:
- %res = add <16 x i8> %v1, %v2
-
-; ASM: vadd.i8 q10, q10, q11
-; DIS: 68: f24448e6
-; IASM-NOT: vadd.i8
-
- ret <16 x i8> %res
-}
diff --git a/third_party/subzero/tests_lit/assembler/arm32/add.ll b/third_party/subzero/tests_lit/assembler/arm32/add.ll
deleted file mode 100644
index b5e8b37..0000000
--- a/third_party/subzero/tests_lit/assembler/arm32/add.ll
+++ /dev/null
@@ -1,123 +0,0 @@
-; Show that we know how to translate add.
-
-; NOTE: We use -O2 to get rid of memory stores.
-
-; REQUIRES: allow_dump
-
-; Compile using standalone assembler.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -O2 \
-; RUN: | FileCheck %s --check-prefix=ASM
-
-; Show bytes in assembled standalone code.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -O2 | FileCheck %s --check-prefix=DIS
-
-; Compile using integrated assembler.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -O2 \
-; RUN: | FileCheck %s --check-prefix=IASM
-
-; Show bytes in assembled integrated code.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -O2 | FileCheck %s --check-prefix=DIS
-
-define internal i32 @add1ToR0(i32 %p) {
- %v = add i32 %p, 1
- ret i32 %v
-}
-
-; ASM-LABEL: add1ToR0:
-; ASM-NEXT: .Ladd1ToR0$__0:
-; ASM-NEXT: add r0, r0, #1
-; ASM-NEXT: bx lr
-
-; DIS-LABEL:00000000 <add1ToR0>:
-; DIS-NEXT: 0: e2800001
-; DIS-NEXT: 4: e12fff1e
-
-; IASM-LABEL: add1ToR0:
-; IASM-LABEL: .Ladd1ToR0$__0:
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x80
-; IASM-NEXT: .byte 0xe2
-
-; IASM-NEXT: .byte 0x1e
-; IASM-NEXT: .byte 0xff
-; IASM-NEXT: .byte 0x2f
-; IASM-NEXT: .byte 0xe1
-
-define internal i32 @Add2Regs(i32 %p1, i32 %p2) {
- %v = add i32 %p1, %p2
- ret i32 %v
-}
-
-; ASM-LABEL: Add2Regs:
-; ASM-NEXT: .LAdd2Regs$__0:
-; ASM-NEXT: add r0, r0, r1
-; ASM-NEXT: bx lr
-
-; DIS-LABEL:00000010 <Add2Regs>:
-; DIS-NEXT: 10: e0800001
-; DIS-NEXT: 14: e12fff1e
-
-; IASM-LABEL: Add2Regs:
-; IASM-NEXT: .LAdd2Regs$__0:
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x80
-; IASM-NEXT: .byte 0xe0
-
-; IASM-NEXT: .byte 0x1e
-; IASM-NEXT: .byte 0xff
-; IASM-NEXT: .byte 0x2f
-; IASM-NEXT: .byte 0xe1
-
-define internal i64 @addI64ToR0R1(i64 %p) {
- %v = add i64 %p, 1
- ret i64 %v
-}
-
-; ASM-LABEL:addI64ToR0R1:
-; ASM-NEXT:.LaddI64ToR0R1$__0:
-; ASM-NEXT: adds r0, r0, #1
-; ASM-NEXT: adc r1, r1, #0
-
-; DIS-LABEL:00000020 <addI64ToR0R1>:
-; DIS-NEXT: 20: e2900001
-; DIS-NEXT: 24: e2a11000
-
-; IASM-LABEL:addI64ToR0R1:
-; IASM-NEXT:.LaddI64ToR0R1$__0:
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x90
-; IASM-NEXT: .byte 0xe2
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0xa1
-; IASM-NEXT: .byte 0xe2
-
-define internal i64 @AddI64Regs(i64 %p1, i64 %p2) {
- %v = add i64 %p1, %p2
- ret i64 %v
-}
-
-; ASM-LABEL:AddI64Regs:
-; ASM-NEXT:.LAddI64Regs$__0:
-; ASM-NEXT: adds r0, r0, r2
-; ASM-NEXT: adc r1, r1, r3
-
-; DIS-LABEL:00000030 <AddI64Regs>:
-; DIS-NEXT: 30: e0900002
-; DIS-NEXT: 34: e0a11003
-
-; IASM-LABEL:AddI64Regs:
-; IASM-NEXT:.LAddI64Regs$__0:
-; IASM-NEXT: .byte 0x2
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x90
-; IASM-NEXT: .byte 0xe0
-; IASM-NEXT: .byte 0x3
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0xa1
-; IASM-NEXT: .byte 0xe0
diff --git a/third_party/subzero/tests_lit/assembler/arm32/and-vec.ll b/third_party/subzero/tests_lit/assembler/arm32/and-vec.ll
deleted file mode 100644
index 48f28a5..0000000
--- a/third_party/subzero/tests_lit/assembler/arm32/and-vec.ll
+++ /dev/null
@@ -1,115 +0,0 @@
-; Show that we know how to translate vand vector instructions.
-
-; REQUIRES: allow_dump
-
-; Compile using standalone assembler.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -O2 \
-; RUN: | FileCheck %s --check-prefix=ASM
-
-; Show bytes in assembled standalone code.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -O2 \
-; RUN: | FileCheck %s --check-prefix=DIS
-
-; Compile using integrated assembler.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -O2 \
-; RUN: | FileCheck %s --check-prefix=IASM
-
-; Show bytes in assembled integrated code.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -O2 \
-; RUN: | FileCheck %s --check-prefix=DIS
-
-define internal <4 x i32> @testVand4i32(<4 x i32> %v1, <4 x i32> %v2) {
-; ASM-LABEL: testVand4i32:
-; DIS-LABEL: 00000000 <testVand4i32>:
-; IASM-LABEL: testVand4i32:
-
-entry:
- %res = and <4 x i32> %v1, %v2
-
-; ASM: vand.i32 q0, q0, q1
-; DIS: 0: f2000152
-; IASM-NOT: vand
-
- ret <4 x i32> %res
-}
-
-define internal <8 x i16> @testVand8i16(<8 x i16> %v1, <8 x i16> %v2) {
-; ASM-LABEL: testVand8i16:
-; DIS-LABEL: 00000010 <testVand8i16>:
-; IASM-LABEL: testVand8i16:
-
-entry:
- %res = and <8 x i16> %v1, %v2
-
-; ASM: vand.i16 q0, q0, q1
-; DIS: 10: f2000152
-; IASM-NOT: vand
-
- ret <8 x i16> %res
-}
-
-define internal <16 x i8> @testVand16i8(<16 x i8> %v1, <16 x i8> %v2) {
-; ASM-LABEL: testVand16i8:
-; DIS-LABEL: 00000020 <testVand16i8>:
-; IASM-LABEL: testVand16i8:
-
-entry:
- %res = and <16 x i8> %v1, %v2
-
-; ASM: vand.i8 q0, q0, q1
-; DIS: 20: f2000152
-; IASM-NOT: vand
-
- ret <16 x i8> %res
-}
-
-;;
-;; The following tests make sure logical and works on predicate vectors.
-;;
-
-define internal <4 x i1> @testVand4i1(<4 x i1> %v1, <4 x i1> %v2) {
-; ASM-LABEL: testVand4i1:
-; DIS-LABEL: 00000030 <testVand4i1>:
-; IASM-LABEL: testVand4i1:
-
-entry:
- %res = and <4 x i1> %v1, %v2
-
-; ASM: vand.i32 q0, q0, q1
-; DIS: 30: f2000152
-; IASM-NOT: vand
-
- ret <4 x i1> %res
-}
-
-define internal <8 x i1> @testVand8i1(<8 x i1> %v1, <8 x i1> %v2) {
-; ASM-LABEL: testVand8i1:
-; DIS-LABEL: 00000040 <testVand8i1>:
-; IASM-LABEL: testVand8i1:
-
-entry:
- %res = and <8 x i1> %v1, %v2
-
-; ASM: vand.i16 q0, q0, q1
-; DIS: 40: f2000152
-; IASM-NOT: vand
-
- ret <8 x i1> %res
-}
-
-define internal <16 x i1> @testVand16i1(<16 x i1> %v1, <16 x i1> %v2) {
-; ASM-LABEL: testVand16i1:
-; DIS-LABEL: 00000050 <testVand16i1>:
-; IASM-LABEL: testVand16i1:
-
-entry:
- %res = and <16 x i1> %v1, %v2
-
-; ASM: vand.i8 q0, q0, q1
-; DIS: 50: f2000152
-; IASM-NOT: vand
-
- ret <16 x i1> %res
-}
diff --git a/third_party/subzero/tests_lit/assembler/arm32/and.ll b/third_party/subzero/tests_lit/assembler/arm32/and.ll
deleted file mode 100644
index ec563e8..0000000
--- a/third_party/subzero/tests_lit/assembler/arm32/and.ll
+++ /dev/null
@@ -1,109 +0,0 @@
-; Show that we know how to translate and.
-
-; NOTE: We use -O2 to get rid of memory stores.
-
-; REQUIRES: allow_dump
-
-; Compile using standalone assembler.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -O2 \
-; RUN: | FileCheck %s --check-prefix=ASM
-
-; Show bytes in assembled standalone code.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -O2 | FileCheck %s --check-prefix=DIS
-
-; Compile using integrated assembler.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -O2 \
-; RUN: | FileCheck %s --check-prefix=IASM
-
-; Show bytes in assembled integrated code.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -O2 | FileCheck %s --check-prefix=DIS
-
-define internal i32 @And1WithR0(i32 %p) {
- %v = and i32 %p, 1
- ret i32 %v
-}
-
-; ASM-LABEL:And1WithR0:
-; ASM-NEXT:.LAnd1WithR0$__0:
-; ASM-NEXT: and r0, r0, #1
-
-; DIS-LABEL:00000000 <And1WithR0>:
-; DIS-NEXT: 0: e2000001
-
-; IASM-LABEL:And1WithR0:
-; IASM-NEXT:.LAnd1WithR0$__0:
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xe2
-
-define internal i32 @And2Regs(i32 %p1, i32 %p2) {
- %v = and i32 %p1, %p2
- ret i32 %v
-}
-
-; ASM-LABEL:And2Regs:
-; ASM-NEXT:.LAnd2Regs$__0:
-; ASM-NEXT: and r0, r0, r1
-
-; DIS-LABEL:00000010 <And2Regs>:
-; DIS-NEXT: 10: e0000001
-
-; IASM-LABEL:And2Regs:
-; IASM-NEXT:.LAnd2Regs$__0:
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xe0
-
-define internal i64 @AndI64WithR0R1(i64 %p) {
- %v = and i64 %p, 1
- ret i64 %v
-}
-
-; ASM-LABEL:AndI64WithR0R1:
-; ASM-NEXT:.LAndI64WithR0R1$__0:
-; ASM-NEXT: and r0, r0, #1
-; ASM-NEXT: and r1, r1, #0
-
-; DIS-LABEL:00000020 <AndI64WithR0R1>:
-; DIS-NEXT: 20: e2000001
-; DIS-NEXT: 24: e2011000
-
-; IASM-LABEL:AndI64WithR0R1:
-; IASM-NEXT:.LAndI64WithR0R1$__0:
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xe2
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0xe2
-
-define internal i64 @AndI64Regs(i64 %p1, i64 %p2) {
- %v = and i64 %p1, %p2
- ret i64 %v
-}
-
-; ASM-LABEL:AndI64Regs:
-; ASM-NEXT:.LAndI64Regs$__0:
-; ASM-NEXT: and r0, r0, r2
-; ASM-NEXT: and r1, r1, r3
-
-; DIS-LABEL:00000030 <AndI64Regs>:
-; DIS-NEXT: 30: e0000002
-; DIS-NEXT: 34: e0011003
-
-; IASM-LABEL:AndI64Regs:
-; IASM-NEXT:.LAndI64Regs$__0:
-; IASM-NEXT: .byte 0x2
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xe0
-; IASM-NEXT: .byte 0x3
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0xe0
diff --git a/third_party/subzero/tests_lit/assembler/arm32/asr.ll b/third_party/subzero/tests_lit/assembler/arm32/asr.ll
deleted file mode 100644
index 40a5894..0000000
--- a/third_party/subzero/tests_lit/assembler/arm32/asr.ll
+++ /dev/null
@@ -1,118 +0,0 @@
-; Show that we know how to translate asr.
-
-; NOTE: We use -O2 to get rid of memory stores.
-
-; REQUIRES: allow_dump
-
-; Compile using standalone assembler.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -O2 \
-; RUN: | FileCheck %s --check-prefix=ASM
-
-; Show bytes in assembled standalone code.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -O2 | FileCheck %s --check-prefix=DIS
-
-; Compile using integrated assembler.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -O2 \
-; RUN: | FileCheck %s --check-prefix=IASM
-
-; Show bytes in assembled integrated code.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -O2 | FileCheck %s --check-prefix=DIS
-
-define internal i32 @AshrAmt(i32 %a) {
-; ASM-LABEL:AshrAmt:
-; DIS-LABEL:00000000 <AshrAmt>:
-; IASM-LABEL:AshrAmt:
-
-entry:
-; ASM-NEXT:.LAshrAmt$entry:
-; IASM-NEXT:.LAshrAmt$entry:
-
- %v = ashr i32 %a, 23
-
-; ASM-NEXT: asr r0, r0, #23
-; DIS-NEXT: 0: e1a00bc0
-; IASM-NOT: asr
-; IASM-NEXT: .byte 0xc0
-; IASM-NEXT: .byte 0xb
-; IASM-NEXT: .byte 0xa0
-; IASM-NEXT: .byte 0xe1
-
- ret i32 %v
-}
-
-define internal i32 @AshrReg(i32 %a, i32 %b) {
-; ASM-LABEL:AshrReg:
-; DIS-LABEL:00000010 <AshrReg>:
-; IASM-LABEL:AshrReg:
-
-entry:
-; ASM-NEXT:.LAshrReg$entry:
-; IASM-NEXT:.LAshrReg$entry:
-
- %v = ashr i32 %a, %b
-
-; ASM-NEXT: asr r0, r0, r1
-; DIS-NEXT: 10: e1a00150
-; IASM-NOT: asr
-; IASM-NEXT: .byte 0x50
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0xa0
-; IASM-NEXT: .byte 0xe1
-
- ret i32 %v
-}
-
-define internal <4 x i32> @AshrVeci32(<4 x i32> %a, <4 x i32> %b) {
-; ASM-LABEL:AshrVeci32:
-; DIS-LABEL:00000020 <AshrVeci32>:
-; IASM-LABEL:AshrVeci32:
-
-entry:
-
- %v = ashr <4 x i32> %a, %b
-
-; ASM: vneg.s32 q1, q1
-; ASM-NEXT: vshl.s32 q0, q0, q1
-; DIS: 20: f3b923c2
-; DIS: 24: f2220440
-; IASM-NOT: vneg
-; IASM-NOT: vshl
-
- ret <4 x i32> %v
-}
-
-define internal <8 x i16> @AshrVeci16(<8 x i16> %a, <8 x i16> %b) {
-; ASM-LABEL:AshrVeci16:
-
-entry:
-
- %v = ashr <8 x i16> %a, %b
-
-; ASM: vneg.s16 q1, q1
-; ASM-NEXT: vshl.s16 q0, q0, q1
-; DIS: 30: f3b523c2
-; DIS: 34: f2120440
-; IASM-NOT: vneg
-; IASM-NOT: vshl
-
- ret <8 x i16> %v
-}
-
-define internal <16 x i8> @AshrVeci8(<16 x i8> %a, <16 x i8> %b) {
-; ASM-LABEL:AshrVeci8:
-
-entry:
-
- %v = ashr <16 x i8> %a, %b
-
-; ASM: vneg.s8 q1, q1
-; ASM-NEXT: vshl.s8 q0, q0, q1
-; DIS: 40: f3b123c2
-; DIS: 44: f2020440
-; IASM-NOT: vneg
-; IASM-NOT: vshl
-
- ret <16 x i8> %v
-}
diff --git a/third_party/subzero/tests_lit/assembler/arm32/bic.ll b/third_party/subzero/tests_lit/assembler/arm32/bic.ll
deleted file mode 100644
index 0ba7eb1..0000000
--- a/third_party/subzero/tests_lit/assembler/arm32/bic.ll
+++ /dev/null
@@ -1,93 +0,0 @@
-; Show that we know how to translate bic.
-
-; NOTE: We use -O2 to get rid of memory stores.
-
-; REQUIRES: allow_dump
-
-; Compile using standalone assembler.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -O2 \
-; RUN: | FileCheck %s --check-prefix=ASM
-
-; Show bytes in assembled standalone code.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -O2 | FileCheck %s --check-prefix=DIS
-
-; Compile using integrated assembler.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -O2 \
-; RUN: | FileCheck %s --check-prefix=IASM
-
-; Show bytes in assembled integrated code.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -O2 | FileCheck %s --check-prefix=DIS
-
-define internal i32 @AllocBigAlign() {
- %addr = alloca i8, align 32
- %v = ptrtoint i8* %addr to i32
- ret i32 %v
-}
-
-; ASM-LABEL:AllocBigAlign:
-; ASM-NEXT:.LAllocBigAlign$__0:
-; DIS-LABEL:00000000 <AllocBigAlign>:
-; IASM-LABEL:AllocBigAlign:
-; IASM-NEXT:.LAllocBigAlign$__0:
-
-; ASM-NEXT: push {fp}
-; DIS-NEXT: 0: e52db004
-; IASM-NEXT: .byte 0x4
-; IASM-NEXT: .byte 0xb0
-; IASM-NEXT: .byte 0x2d
-; IASM-NEXT: .byte 0xe5
-
-; ASM-NEXT: mov fp, sp
-; DIS-NEXT: 4: e1a0b00d
-; IASM: .byte 0xd
-; IASM-NEXT: .byte 0xb0
-; IASM-NEXT: .byte 0xa0
-; IASM-NEXT: .byte 0xe1
-
-; ASM-NEXT: sub sp, sp, #32
-; DIS-NEXT: 8: e24dd020
-; IASM: .byte 0x20
-; IASM-NEXT: .byte 0xd0
-; IASM-NEXT: .byte 0x4d
-; IASM-NEXT: .byte 0xe2
-
-; ASM-NEXT: bic sp, sp, #31
-; DIS-NEXT: c: e3cdd01f
-; IASM: .byte 0x1f
-; IASM-NEXT: .byte 0xd0
-; IASM-NEXT: .byte 0xcd
-; IASM-NEXT: .byte 0xe3
-
-; ASM-NEXT: # sp = def.pseudo
-
-; ASM-NEXT: add r0, sp, #0
-; DIS-NEXT: 10: e28d0000
-; IASM: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x8d
-; IASM-NEXT: .byte 0xe2
-
-; ASM-NEXT: mov sp, fp
-; DIS-NEXT: 14: e1a0d00b
-; IASM: .byte 0xb
-; IASM-NEXT: .byte 0xd0
-; IASM-NEXT: .byte 0xa0
-; IASM-NEXT: .byte 0xe1
-
-; ASM-NEXT: pop {fp}
-; DIS-NEXT: 18: e49db004
-; IASM-NEXT: .byte 0x4
-; IASM-NEXT: .byte 0xb0
-; IASM-NEXT: .byte 0x9d
-; IASM-NEXT: .byte 0xe4
-
-; ASM-NEXT: # fp = def.pseudo
-
-; ASM-NEXT: bx lr
-; DIS-NEXT: 1c: e12fff1e
-; IASM: .byte 0x1e
-; IASM-NEXT: .byte 0xff
-; IASM-NEXT: .byte 0x2f
-; IASM-NEXT: .byte 0xe1
diff --git a/third_party/subzero/tests_lit/assembler/arm32/blx.ll b/third_party/subzero/tests_lit/assembler/arm32/blx.ll
deleted file mode 100644
index f3107dc..0000000
--- a/third_party/subzero/tests_lit/assembler/arm32/blx.ll
+++ /dev/null
@@ -1,64 +0,0 @@
-; Show that we know how to translate blx.
-
-; NOTE: We use -O2 to get rid of memory stores.
-
-; REQUIRES: allow_dump
-
-; Compile using standalone assembler.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -O2 \
-; RUN: | FileCheck %s --check-prefix=ASM
-
-; Show bytes in assembled standalone code.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -O2 | FileCheck %s --check-prefix=DIS
-
-; Compile using integrated assembler.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -O2 \
-; RUN: | FileCheck %s --check-prefix=IASM
-
-; Show bytes in assembled integrated code.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -O2 | FileCheck %s --check-prefix=DIS
-
-define internal void @callIndirect(i32 %addr) {
-; ASM-LABEL:callIndirect:
-; DIS-LABEL:00000000 <callIndirect>:
-; IASM-LABEL:callIndirect:
-
-entry:
-; ASM-NEXT:.LcallIndirect$entry:
-; IASM-NEXT:.LcallIndirect$entry:
-; ASM-NEXT: push {lr}
-; DIS-NEXT: 0: e52de004
-; IASM-NEXT: .byte 0x4
-; IASM-NEXT: .byte 0xe0
-; IASM-NEXT: .byte 0x2d
-; IASM-NEXT: .byte 0xe5
-
-; ASM-NEXT: sub sp, sp, #12
-; DIS-NEXT: 4: e24dd00c
-; IASM-NEXT: .byte 0xc
-; IASM-NEXT: .byte 0xd0
-; IASM-NEXT: .byte 0x4d
-; IASM-NEXT: .byte 0xe2
-
- %calladdr = inttoptr i32 %addr to void (i32)*
-
-; ASM-NEXT: mov r1, r0
-; DIS-NEXT: 8: e1a01000
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0xa0
-; IASM-NEXT: .byte 0xe1
-
- call void %calladdr(i32 %addr)
-
-; ASM-NEXT: blx r1
-; DIS-NEXT: c: e12fff31
-; IASM-NEXT: .byte 0x31
-; IASM-NEXT: .byte 0xff
-; IASM-NEXT: .byte 0x2f
-; IASM-NEXT: .byte 0xe1
-
- ret void
-}
diff --git a/third_party/subzero/tests_lit/assembler/arm32/branch-mult-fwd.ll b/third_party/subzero/tests_lit/assembler/arm32/branch-mult-fwd.ll
deleted file mode 100644
index 6f87f8a..0000000
--- a/third_party/subzero/tests_lit/assembler/arm32/branch-mult-fwd.ll
+++ /dev/null
@@ -1,172 +0,0 @@
-; Test that we correctly fix multiple forward branches.
-
-; Compile using standalone assembler.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -Om1 \
-; RUN: | FileCheck %s --check-prefix=ASM
-
-; Show bytes in assembled standalone code.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -Om1 | FileCheck %s --check-prefix=DIS
-
-; Compile using integrated assembler.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -Om1 \
-; RUN: | FileCheck %s --check-prefix=IASM
-
-; Show bytes in assembled integrated code.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -Om1 | FileCheck %s --check-prefix=DIS
-
-; REQUIRES: allow_dump
-
-define internal void @mult_fwd_branches(i32 %a, i32 %b) {
-; ASM-LABEL:mult_fwd_branches:
-; DIS-LABEL:00000000 <mult_fwd_branches>:
-; IASM-LABEL:mult_fwd_branches:
-
-; ASM-LABEL:.Lmult_fwd_branches$__0:
-; IASM-LABEL:.Lmult_fwd_branches$__0:
-
-; ASM-NEXT: sub sp, sp, #12
-; DIS-NEXT: 0: e24dd00c
-; IASM-NEXT: .byte 0xc
-; IASM-NEXT: .byte 0xd0
-; IASM-NEXT: .byte 0x4d
-; IASM-NEXT: .byte 0xe2
-
-; ASM-NEXT: str r0, [sp, #8]
-; ASM-NEXT: # [sp, #8] = def.pseudo
-; DIS-NEXT: 4: e58d0008
-; IASM-NEXT: .byte 0x8
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x8d
-; IASM-NEXT: .byte 0xe5
-
-; ASM-NEXT: str r1, [sp, #4]
-; ASM-NEXT: # [sp, #4] = def.pseudo
-; DIS-NEXT: 8: e58d1004
-; IASM-NEXT: .byte 0x4
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0x8d
-; IASM-NEXT: .byte 0xe5
-
- %cmp = icmp slt i32 %a, %b
-
-; ASM-NEXT: mov r0, #0
-; DIS-NEXT: c: e3a00000
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xa0
-; IASM-NEXT: .byte 0xe3
-
-; ASM-NEXT: ldr r1, [sp, #8]
-; DIS-NEXT: 10: e59d1008
-; IASM-NEXT: .byte 0x8
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0x9d
-; IASM-NEXT: .byte 0xe5
-
-; ASM-NEXT: ldr r2, [sp, #4]
-; DIS-NEXT: 14: e59d2004
-; IASM-NEXT: .byte 0x4
-; IASM-NEXT: .byte 0x20
-; IASM-NEXT: .byte 0x9d
-; IASM-NEXT: .byte 0xe5
-
-; ASM-NEXT: cmp r1, r2
-; DIS-NEXT: 18: e1510002
-; IASM-NEXT: .byte 0x2
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x51
-; IASM-NEXT: .byte 0xe1
-
-; ASM-NEXT: movlt r0, #1
-; DIS-NEXT: 1c: b3a00001
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xa0
-; IASM-NEXT: .byte 0xb3
-
-; ASM-NEXT: strb r0, [sp]
-; ASM-NEXT: # [sp] = def.pseudo
-; DIS-NEXT: 20: e5cd0000
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xcd
-; IASM-NEXT: .byte 0xe5
-
- br i1 %cmp, label %then, label %else
-
-; ASM-NEXT: ldrb r0, [sp]
-; DIS-NEXT: 24: e5dd0000
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xdd
-; IASM-NEXT: .byte 0xe5
-
-; ASM-NEXT: tst r0, #1
-; DIS-NEXT: 28: e3100001
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0xe3
-
-; ASM-NEXT: bne .Lmult_fwd_branches$then
-; DIS-NEXT: 2c: 1a000000
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x1a
-
-; ASM-NEXT: b .Lmult_fwd_branches$else
-; DIS-NEXT: 30: ea000000
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xea
-
-then:
-; ASM-LABEL:.Lmult_fwd_branches$then:
-; IASM-LABEL:.Lmult_fwd_branches$then:
-
- br label %end
-
-; ASM-NEXT: b .Lmult_fwd_branches$end
-; DIS-NEXT: 34: ea000000
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xea
-
-else:
-; ASM-LABEL:.Lmult_fwd_branches$else:
-; IASM-LABEL:.Lmult_fwd_branches$else:
-
- br label %end
-; ASM-NEXT: b .Lmult_fwd_branches$end
-; DIS-NEXT: 38: eaffffff
-; IASM-NEXT: .byte 0xff
-; IASM-NEXT: .byte 0xff
-; IASM-NEXT: .byte 0xff
-; IASM-NEXT: .byte 0xea
-
-
-end:
-; ASM-LABEL:.Lmult_fwd_branches$end:
-; IASM-LABEL: .Lmult_fwd_branches$end:
-
- ret void
-
-; ASM-NEXT: add sp, sp, #12
-; DIS-NEXT: 3c: e28dd00c
-; IASM-NEXT: .byte 0xc
-; IASM-NEXT: .byte 0xd0
-; IASM-NEXT: .byte 0x8d
-; IASM-NEXT: .byte 0xe2
-
-; ASM-NEXT: bx lr
-; DIS-NEXT: 40: e12fff1e
-; IASM-NEXT: .byte 0x1e
-; IASM-NEXT: .byte 0xff
-; IASM-NEXT: .byte 0x2f
-; IASM-NEXT: .byte 0xe1
-}
diff --git a/third_party/subzero/tests_lit/assembler/arm32/branch-simple.ll b/third_party/subzero/tests_lit/assembler/arm32/branch-simple.ll
deleted file mode 100644
index fb4a645..0000000
--- a/third_party/subzero/tests_lit/assembler/arm32/branch-simple.ll
+++ /dev/null
@@ -1,74 +0,0 @@
-; Test branching instructions.
-; TODO(kschimpf): Get this working.
-
-; REQUIRES: allow_dump
-
-; Compile using standalone assembler.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -Om1 \
-; RUN: | FileCheck %s --check-prefix=ASM
-
-; Show bytes in assembled standalone code.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -Om1 | FileCheck %s --check-prefix=DIS
-
-; Compile using integrated assembler.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -Om1 \
-; RUN: | FileCheck %s --check-prefix=IASM
-
-; Show bytes in assembled integrated code.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -Om1 | FileCheck %s --check-prefix=DIS
-
-define internal void @simple_uncond_branch() {
-; DIS-LABEL: 00000000 <simple_uncond_branch>:
-; ASM-LABEL: simple_uncond_branch:
-; IASM-LABEL:simple_uncond_branch:
-
-; ASM-NEXT: .Lsimple_uncond_branch$__0:
-; IASM-NEXT: .Lsimple_uncond_branch$__0:
-
- br label %l2
-; ASM-NEXT: b .Lsimple_uncond_branch$l2
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xea
-; DIS-NEXT: 0: ea000000
-
-l1:
-; ASM-NEXT: .Lsimple_uncond_branch$l1:
-; IASM-NEXT: .Lsimple_uncond_branch$l1:
-
- br label %l3
-; ASM-NEXT: b .Lsimple_uncond_branch$l3
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xea
-; DIS-NEXT: 4: ea000000
-
-l2:
-; ASM-NEXT: .Lsimple_uncond_branch$l2:
-; IASM-NEXT: .Lsimple_uncond_branch$l2:
-
- br label %l1
-; ASM-NEXT: b .Lsimple_uncond_branch$l1
-; IASM-NEXT: .byte 0xfd
-; IASM-NEXT: .byte 0xff
-; IASM-NEXT: .byte 0xff
-; IASM-NEXT: .byte 0xea
-; DIS-NEXT: 8: eafffffd
-
-l3:
-; ASM-NEXT: .Lsimple_uncond_branch$l3:
-; IASM-NEXT: .Lsimple_uncond_branch$l3:
-
- ret void
-; ASM-NEXT: bx lr
-; IASM-NEXT: .byte 0x1e
-; IASM-NEXT: .byte 0xff
-; IASM-NEXT: .byte 0x2f
-; IASM-NEXT: .byte 0xe1
-; DIS-NEXT: c: e12fff1e
-
-}
diff --git a/third_party/subzero/tests_lit/assembler/arm32/check-reg-classes.ll b/third_party/subzero/tests_lit/assembler/arm32/check-reg-classes.ll
deleted file mode 100644
index a0956fa..0000000
--- a/third_party/subzero/tests_lit/assembler/arm32/check-reg-classes.ll
+++ /dev/null
@@ -1,12 +0,0 @@
-; Show that all register classes are defined for ARM32.
-
-
-; REQUIRES: allow_dump
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -Om1 \
-; RUN: --verbose=registers | FileCheck %s
-
-define internal void @f() {
- ret void
-}
-
-; CHECK: Registers available for register allocation:
diff --git a/third_party/subzero/tests_lit/assembler/arm32/clz.ll b/third_party/subzero/tests_lit/assembler/arm32/clz.ll
deleted file mode 100644
index b18dced..0000000
--- a/third_party/subzero/tests_lit/assembler/arm32/clz.ll
+++ /dev/null
@@ -1,64 +0,0 @@
-; Show that we know how to translate clz.
-
-; REQUIRES: allow_dump
-
-; Compile using standalone assembler.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -Om1 \
-; RUN: | FileCheck %s --check-prefix=ASM
-
-; Show bytes in assembled standalone code.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -Om1 | FileCheck %s --check-prefix=DIS
-
-; Compile using integrated assembler.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -Om1 \
-; RUN: | FileCheck %s --check-prefix=IASM
-
-; Show bytes in assembled integrated code.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -Om1 | FileCheck %s --check-prefix=DIS
-
-declare i32 @llvm.ctlz.i32(i32, i1)
-
-define internal i32 @testClz(i32 %a) {
-; ASM-LABEL:testClz:
-; DIS-LABEL:00000000 <testClz>:
-; IASM-LABEL:testClz:
-
-entry:
-; ASM-NEXT:.LtestClz$entry:
-; IASM-NEXT:.LtestClz$entry:
-
-; ASM-NEXT: sub sp, sp, #8
-; DIS-NEXT: 0: e24dd008
-; IASM-NEXT: .byte 0x8
-; IASM-NEXT: .byte 0xd0
-; IASM-NEXT: .byte 0x4d
-; IASM-NEXT: .byte 0xe2
-
-; ASM-NEXT: str r0, [sp, #4]
-; ASM-NEXT: # [sp, #4] = def.pseudo
-; DIS-NEXT: 4: e58d0004
-; IASM-NEXT: .byte 0x4
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x8d
-; IASM-NEXT: .byte 0xe5
-
- %x = call i32 @llvm.ctlz.i32(i32 %a, i1 0)
-
-; ASM-NEXT: ldr r0, [sp, #4]
-; DIS-NEXT: 8: e59d0004
-; IASM-NEXT: .byte 0x4
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x9d
-; IASM-NEXT: .byte 0xe5
-
-; ASM-NEXT: clz r0, r0
-; DIS-NEXT: c: e16f0f10
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0xf
-; IASM-NEXT: .byte 0x6f
-; IASM-NEXT: .byte 0xe1
-
- ret i32 %x
-}
diff --git a/third_party/subzero/tests_lit/assembler/arm32/cmn.ll b/third_party/subzero/tests_lit/assembler/arm32/cmn.ll
deleted file mode 100644
index 887ce83..0000000
--- a/third_party/subzero/tests_lit/assembler/arm32/cmn.ll
+++ /dev/null
@@ -1,70 +0,0 @@
-; Show that we know how to encode CMN in the ARM integrated assembler.
-
-; REQUIRES: allow_dump
-
-; Compile using standalone assembler.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -Om1 \
-; RUN: | FileCheck %s --check-prefix=ASM
-
-; Show bytes in assembled standalone code.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -Om1 | FileCheck %s --check-prefix=DIS
-
-; Compile using integrated assembler.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -Om1 \
-; RUN: | FileCheck %s --check-prefix=IASM
-
-; Show bytes in assembled integrated code.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -Om1 | FileCheck %s --check-prefix=DIS
-
-define internal i32 @testCmn(i32 %a) {
-; ASM-LABEL:testCmn:
-; DIS-LABEL:00000000 <testCmn>:
-; IASM-LABEL:testCmn:
-
-entry:
-; ASM-NEXT:.LtestCmn$entry:
-; IASM-NEXT:.LtestCmn$entry:
-
-; ASM-NEXT: sub sp, sp, #12
-; DIS-NEXT: 0: e24dd00c
-; IASM-NEXT: .byte 0xc
-; IASM-NEXT: .byte 0xd0
-; IASM-NEXT: .byte 0x4d
-; IASM-NEXT: .byte 0xe2
-
-; ASM-NEXT: str r0, [sp, #8]
-; ASM-NEXT: # [sp, #8] = def.pseudo
-; DIS-NEXT: 4: e58d0008
-; IASM-NEXT: .byte 0x8
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x8d
-; IASM-NEXT: .byte 0xe5
-
- %cmp = icmp sgt i32 %a, -1
-
-; ASM-NEXT: mov r0, #0
-; DIS-NEXT: 8: e3a00000
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xa0
-; IASM-NEXT: .byte 0xe3
-
-; ASM-NEXT: ldr r1, [sp, #8]
-; DIS-NEXT: c: e59d1008
-; IASM-NEXT: .byte 0x8
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0x9d
-; IASM-NEXT: .byte 0xe5
-
-; ASM-NEXT: cmn r1, #1
-; DIS-NEXT: 10: e3710001
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x71
-; IASM-NEXT: .byte 0xe3
-
- %cmp.ret_ext = zext i1 %cmp to i32
- ret i32 %cmp.ret_ext
-}
diff --git a/third_party/subzero/tests_lit/assembler/arm32/cmp-vec.ll b/third_party/subzero/tests_lit/assembler/arm32/cmp-vec.ll
deleted file mode 100644
index ab25cb3..0000000
--- a/third_party/subzero/tests_lit/assembler/arm32/cmp-vec.ll
+++ /dev/null
@@ -1,1438 +0,0 @@
-; Test that we handle icmp and fcmp on vectors.
-
-; REQUIRES: allow_dump
-
-; Compile using standalone assembler.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -O2 \
-; RUN: | FileCheck %s --check-prefix=ASM
-
-; Show bytes in assembled standalone code.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -O2 | FileCheck %s --check-prefix=DIS
-
-; Compile using integrated assembler.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -O2 \
-; RUN: | FileCheck %s --check-prefix=IASM
-
-; Show bytes in assembled integrated code.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -O2 | FileCheck %s --check-prefix=DIS
-
-define internal <4 x i32> @cmpEqV4I32(<4 x i32> %a, <4 x i32> %b) {
-; ASM-LABEL:cmpEqV4I32:
-; DIS-LABEL:00000000 <cmpEqV4I32>:
-; IASM-LABEL:cmpEqV4I32:
-
-entry:
- %cmp = icmp eq <4 x i32> %a, %b
-
-; ASM: vceq.i32 q0, q0, q1
-; DIS: 0: f3200852
-; IASM-NOT: vceq
-
- %cmp.ret_ext = zext <4 x i1> %cmp to <4 x i32>
- ret <4 x i32> %cmp.ret_ext
-}
-
-define internal <4 x i32> @cmpNeV4I32(<4 x i32> %a, <4 x i32> %b) {
-; ASM-LABEL:cmpNeV4I32:
-; DIS-LABEL:00000010 <cmpNeV4I32>:
-; IASM-LABEL:cmpNeV4I32:
-
-entry:
- %cmp = icmp ne <4 x i32> %a, %b
-
-; ASM: vceq.i32 q0, q0, q1
-; ASM-NEXT: vmvn.i32 q0, q0
-; DIS: 10: f3200852
-; DIS-NEXT: 14: f3b005c0
-; IASM-NOT: vceq
-; IASM-NOT: vmvn
-
- %cmp.ret_ext = zext <4 x i1> %cmp to <4 x i32>
- ret <4 x i32> %cmp.ret_ext
-}
-
-define internal <4 x i32> @cmpUgtV4I32(<4 x i32> %a, <4 x i32> %b) {
-; ASM-LABEL:cmpUgtV4I32:
-; DIS-LABEL:00000030 <cmpUgtV4I32>:
-; IASM-LABEL:cmpUgtV4I32:
-
-entry:
- %cmp = icmp ugt <4 x i32> %a, %b
-
-; ASM: vcgt.u32 q0, q0, q1
-; DIS: 30: f3200342
-; IASM-NOT: vcgt
-
- %cmp.ret_ext = zext <4 x i1> %cmp to <4 x i32>
- ret <4 x i32> %cmp.ret_ext
-}
-
-define internal <4 x i32> @cmpUgeV4I32(<4 x i32> %a, <4 x i32> %b) {
-; ASM-LABEL:cmpUgeV4I32:
-; DIS-LABEL:00000040 <cmpUgeV4I32>:
-; IASM-LABEL:cmpUgeV4I32:
-
-entry:
- %cmp = icmp uge <4 x i32> %a, %b
-
-; ASM: vcge.u32 q0, q0, q1
-; DIS: 40: f3200352
-; IASM-NOT: vcge
-
- %cmp.ret_ext = zext <4 x i1> %cmp to <4 x i32>
- ret <4 x i32> %cmp.ret_ext
-}
-
-define internal <4 x i32> @cmpUltV4I32(<4 x i32> %a, <4 x i32> %b) {
-; ASM-LABEL:cmpUltV4I32:
-; DIS-LABEL:00000050 <cmpUltV4I32>:
-; IASM-LABEL:cmpUltV4I32:
-
-entry:
- %cmp = icmp ult <4 x i32> %a, %b
-
-; ASM: vcgt.u32 q1, q1, q0
-; DIS: 50: f3222340
-; IASM-NOT: vcgt
-
- %cmp.ret_ext = zext <4 x i1> %cmp to <4 x i32>
- ret <4 x i32> %cmp.ret_ext
-}
-
-define internal <4 x i32> @cmpUleV4I32(<4 x i32> %a, <4 x i32> %b) {
-; ASM-LABEL:cmpUleV4I32:
-; DIS-LABEL:00000070 <cmpUleV4I32>:
-; IASM-LABEL:cmpUleV4I32:
-
-entry:
- %cmp = icmp ule <4 x i32> %a, %b
-
-; ASM: vcge.u32 q1, q1, q0
-; DIS: 70: f3222350
-; IASM-NOT: vcge
-
- %cmp.ret_ext = zext <4 x i1> %cmp to <4 x i32>
- ret <4 x i32> %cmp.ret_ext
-}
-
-define internal <4 x i32> @cmpSgtV4I32(<4 x i32> %a, <4 x i32> %b) {
-; ASM-LABEL:cmpSgtV4I32:
-; DIS-LABEL:00000090 <cmpSgtV4I32>:
-; IASM-LABEL:cmpSgtV4I32:
-
-entry:
- %cmp = icmp sgt <4 x i32> %a, %b
-
-; ASM: vcgt.s32 q0, q0, q1
-; DIS: 90: f2200342
-; IASM-NOT: vcgt
-
- %cmp.ret_ext = zext <4 x i1> %cmp to <4 x i32>
- ret <4 x i32> %cmp.ret_ext
-}
-
-define internal <4 x i32> @cmpSgeV4I32(<4 x i32> %a, <4 x i32> %b) {
-; ASM-LABEL:cmpSgeV4I32:
-; DIS-LABEL:000000a0 <cmpSgeV4I32>:
-; IASM-LABEL:cmpSgeV4I32:
-
-entry:
- %cmp = icmp sge <4 x i32> %a, %b
-
-; ASM: vcge.s32 q0, q0, q1
-; DIS: a0: f2200352
-; IASM-NOT: vcge
-
- %cmp.ret_ext = zext <4 x i1> %cmp to <4 x i32>
- ret <4 x i32> %cmp.ret_ext
-}
-
-define internal <4 x i32> @cmpSltV4I32(<4 x i32> %a, <4 x i32> %b) {
-; ASM-LABEL:cmpSltV4I32:
-; DIS-LABEL:000000b0 <cmpSltV4I32>:
-; IASM-LABEL:cmpSltV4I32:
-
-entry:
- %cmp = icmp slt <4 x i32> %a, %b
-
-; ASM: vcgt.s32 q1, q1, q0
-; DIS: b0: f2222340
-; IASM-NOT: vcgt
-
- %cmp.ret_ext = zext <4 x i1> %cmp to <4 x i32>
- ret <4 x i32> %cmp.ret_ext
-}
-
-define internal <4 x i32> @cmpSleV4I32(<4 x i32> %a, <4 x i32> %b) {
-; ASM-LABEL:cmpSleV4I32:
-; DIS-LABEL:000000d0 <cmpSleV4I32>:
-; IASM-LABEL:cmpSleV4I32:
-
-entry:
- %cmp = icmp sle <4 x i32> %a, %b
-
-; ASM: vcge.s32 q1, q1, q0
-; DIS: d0: f2222350
-; IASM-NOT: vcge
-
- %cmp.ret_ext = zext <4 x i1> %cmp to <4 x i32>
- ret <4 x i32> %cmp.ret_ext
-}
-
-define internal <4 x i32> @cmpEqV4I1(<4 x i32> %a, <4 x i32> %b) {
-; ASM-LABEL:cmpEqV4I1:
-; DIS-LABEL:000000f0 <cmpEqV4I1>:
-; IASM-LABEL:cmpEqV4I1:
-
-entry:
- %a1 = trunc <4 x i32> %a to <4 x i1>
- %b1 = trunc <4 x i32> %b to <4 x i1>
- %cmp = icmp eq <4 x i1> %a1, %b1
-
-; ASM: vshl.u32 q0, q0, #31
-; ASM-NEXT: vshl.u32 q1, q1, #31
-; ASM-NEXT: vceq.i32 q0, q0, q1
-; DIS: f0: f2bf0550
-; DIS-NEXT: f4: f2bf2552
-; DIS-NEXT: f8: f3200852
-; IASM-NOT: vshl
-; IASM-NOT: vceq
-
- %cmp.ret_ext = zext <4 x i1> %cmp to <4 x i32>
- ret <4 x i32> %cmp.ret_ext
-}
-
-define internal <4 x i32> @cmpNeV4I1(<4 x i32> %a, <4 x i32> %b) {
-; ASM-LABEL:cmpNeV4I1:
-; DIS-LABEL:00000110 <cmpNeV4I1>:
-; IASM-LABEL:cmpNeV4I1:
-
-entry:
- %a1 = trunc <4 x i32> %a to <4 x i1>
- %b1 = trunc <4 x i32> %b to <4 x i1>
- %cmp = icmp ne <4 x i1> %a1, %b1
-
-; ASM: vshl.u32 q0, q0, #31
-; ASM-NEXT: vshl.u32 q1, q1, #31
-; ASM-NEXT: vceq.i32 q0, q0, q1
-; ASM-NEXT: vmvn.i32 q0, q0
-; DIS: 110: f2bf0550
-; DIS-NEXT: 114: f2bf2552
-; DIS-NEXT: 118: f3200852
-; DIS-NEXT: 11c: f3b005c0
-; IASM-NOT: vshl
-; IASM-NOT: vceq
-; IASM-NOT: vmvn
-
- %cmp.ret_ext = zext <4 x i1> %cmp to <4 x i32>
- ret <4 x i32> %cmp.ret_ext
-}
-
-define internal <4 x i32> @cmpUgtV4I1(<4 x i32> %a, <4 x i32> %b) {
-; ASM-LABEL:cmpUgtV4I1:
-; DIS-LABEL:00000130 <cmpUgtV4I1>:
-; IASM-LABEL:cmpUgtV4I1:
-
-entry:
- %a1 = trunc <4 x i32> %a to <4 x i1>
- %b1 = trunc <4 x i32> %b to <4 x i1>
- %cmp = icmp ugt <4 x i1> %a1, %b1
-
-; ASM: vshl.u32 q0, q0, #31
-; ASM-NEXT: vshl.u32 q1, q1, #31
-; ASM-NEXT: vcgt.u32 q0, q0, q1
-; DIS: 130: f2bf0550
-; DIS-NEXT: 134: f2bf2552
-; DIS-NEXT: 138: f3200342
-; IASM-NOT: vshl
-; IASM-NOT: vcgt
-
- %cmp.ret_ext = zext <4 x i1> %cmp to <4 x i32>
- ret <4 x i32> %cmp.ret_ext
-}
-
-define internal <4 x i32> @cmpUgeV4I1(<4 x i32> %a, <4 x i32> %b) {
-; ASM-LABEL:cmpUgeV4I1:
-; DIS-LABEL:00000150 <cmpUgeV4I1>:
-; IASM-LABEL:cmpUgeV4I1:
-
-entry:
- %a1 = trunc <4 x i32> %a to <4 x i1>
- %b1 = trunc <4 x i32> %b to <4 x i1>
- %cmp = icmp uge <4 x i1> %a1, %b1
-
-; ASM: vshl.u32 q0, q0, #31
-; ASM-NEXT: vshl.u32 q1, q1, #31
-; ASM-NEXT: vcge.u32 q0, q0, q1
-; DIS: 150: f2bf0550
-; DIS-NEXT: 154: f2bf2552
-; DIS-NEXT: 158: f3200352
-; IASM-NOT: vshl
-; IASM-NOT: vcge
-
- %cmp.ret_ext = zext <4 x i1> %cmp to <4 x i32>
- ret <4 x i32> %cmp.ret_ext
-}
-
-define internal <4 x i32> @cmpUltV4I1(<4 x i32> %a, <4 x i32> %b) {
-; ASM-LABEL:cmpUltV4I1:
-; DIS-LABEL:00000170 <cmpUltV4I1>:
-; IASM-LABEL:cmpUltV4I1:
-
-entry:
- %a1 = trunc <4 x i32> %a to <4 x i1>
- %b1 = trunc <4 x i32> %b to <4 x i1>
- %cmp = icmp ult <4 x i1> %a1, %b1
-
-; ASM: vshl.u32 q0, q0, #31
-; ASM-NEXT: vshl.u32 q1, q1, #31
-; ASM-NEXT: vcgt.u32 q1, q1, q0
-; DIS: 170: f2bf0550
-; DIS-NEXT: 174: f2bf2552
-; DIS-NEXT: 178: f3222340
-; IASM-NOT: vshl
-; IASM-NOT: vcgt
-
- %cmp.ret_ext = zext <4 x i1> %cmp to <4 x i32>
- ret <4 x i32> %cmp.ret_ext
-}
-
-define internal <4 x i32> @cmpUleV4I1(<4 x i32> %a, <4 x i32> %b) {
-; ASM-LABEL:cmpUleV4I1:
-; DIS-LABEL:00000190 <cmpUleV4I1>:
-; IASM-LABEL:cmpUleV4I1:
-
-entry:
- %a1 = trunc <4 x i32> %a to <4 x i1>
- %b1 = trunc <4 x i32> %b to <4 x i1>
- %cmp = icmp ule <4 x i1> %a1, %b1
-
-; ASM: vshl.u32 q0, q0, #31
-; ASM-NEXT: vshl.u32 q1, q1, #31
-; ASM-NEXT: vcge.u32 q1, q1, q0
-; DIS: 190: f2bf0550
-; DIS-NEXT: 194: f2bf2552
-; DIS-NEXT: 198: f3222350
-; IASM-NOT: vshl
-; IASM-NOT: vcge
-
- %cmp.ret_ext = zext <4 x i1> %cmp to <4 x i32>
- ret <4 x i32> %cmp.ret_ext
-}
-
-define internal <4 x i32> @cmpSgtV4I1(<4 x i32> %a, <4 x i32> %b) {
-; ASM-LABEL:cmpSgtV4I1:
-; DIS-LABEL:000001b0 <cmpSgtV4I1>:
-; IASM-LABEL:cmpSgtV4I1:
-
-entry:
- %a1 = trunc <4 x i32> %a to <4 x i1>
- %b1 = trunc <4 x i32> %b to <4 x i1>
- %cmp = icmp sgt <4 x i1> %a1, %b1
-
-; ASM: vshl.u32 q0, q0, #31
-; ASM-NEXT: vshl.u32 q1, q1, #31
-; ASM-NEXT: vcgt.s32 q0, q0, q1
-; DIS: 1b0: f2bf0550
-; DIS-NEXT: 1b4: f2bf2552
-; DIS-NEXT: 1b8: f2200342
-; IASM-NOT: vshl
-; IASM-NOT: vcgt
-
- %cmp.ret_ext = zext <4 x i1> %cmp to <4 x i32>
- ret <4 x i32> %cmp.ret_ext
-}
-
-define internal <4 x i32> @cmpSgeV4I1(<4 x i32> %a, <4 x i32> %b) {
-; ASM-LABEL:cmpSgeV4I1:
-; DIS-LABEL:000001d0 <cmpSgeV4I1>:
-; IASM-LABEL:cmpSgeV4I1:
-
-entry:
- %a1 = trunc <4 x i32> %a to <4 x i1>
- %b1 = trunc <4 x i32> %b to <4 x i1>
- %cmp = icmp sge <4 x i1> %a1, %b1
-
-; ASM: vshl.u32 q0, q0, #31
-; ASM-NEXT: vshl.u32 q1, q1, #31
-; ASM-NEXT: vcge.s32 q0, q0, q1
-; DIS: 1d0: f2bf0550
-; DIS-NEXT: 1d4: f2bf2552
-; DIS-NEXT: 1d8: f2200352
-; IASM-NOT: vshl
-; IASM-NOT: vcge
-
- %cmp.ret_ext = zext <4 x i1> %cmp to <4 x i32>
- ret <4 x i32> %cmp.ret_ext
-}
-
-define internal <4 x i32> @cmpSltV4I1(<4 x i32> %a, <4 x i32> %b) {
-; ASM-LABEL:cmpSltV4I1:
-; DIS-LABEL:000001f0 <cmpSltV4I1>:
-; IASM-LABEL:cmpSltV4I1:
-
-entry:
- %a1 = trunc <4 x i32> %a to <4 x i1>
- %b1 = trunc <4 x i32> %b to <4 x i1>
- %cmp = icmp slt <4 x i1> %a1, %b1
-
-; ASM: vshl.u32 q0, q0, #31
-; ASM-NEXT: vshl.u32 q1, q1, #31
-; ASM-NEXT: vcgt.s32 q1, q1, q0
-; DIS: 1f0: f2bf0550
-; DIS-NEXT: 1f4: f2bf2552
-; DIS-NEXT: 1f8: f2222340
-; IASM-NOT: vshl
-; IASM-NOT: vcgt
-
- %cmp.ret_ext = zext <4 x i1> %cmp to <4 x i32>
- ret <4 x i32> %cmp.ret_ext
-}
-
-define internal <4 x i32> @cmpSleV4I1(<4 x i32> %a, <4 x i32> %b) {
-; ASM-LABEL:cmpSleV4I1:
-; DIS-LABEL:00000210 <cmpSleV4I1>:
-; IASM-LABEL:cmpSleV4I1:
-
-entry:
- %a1 = trunc <4 x i32> %a to <4 x i1>
- %b1 = trunc <4 x i32> %b to <4 x i1>
- %cmp = icmp sle <4 x i1> %a1, %b1
-
-; ASM: vshl.u32 q0, q0, #31
-; ASM-NEXT: vshl.u32 q1, q1, #31
-; ASM-NEXT: vcge.s32 q1, q1, q0
-; DIS: 210: f2bf0550
-; DIS-NEXT: 214: f2bf2552
-; DIS-NEXT: 218: f2222350
-; IASM-NOT: vshl
-; IASM-NOT: vcge
-
- %cmp.ret_ext = zext <4 x i1> %cmp to <4 x i32>
- ret <4 x i32> %cmp.ret_ext
-}
-
-define internal <8 x i16> @cmpEqV8I16(<8 x i16> %a, <8 x i16> %b) {
-; ASM-LABEL:cmpEqV8I16:
-; DIS-LABEL:00000230 <cmpEqV8I16>:
-; IASM-LABEL:cmpEqV8I16:
-
-entry:
- %cmp = icmp eq <8 x i16> %a, %b
-
-; ASM: vceq.i16 q0, q0, q1
-; DIS: 230: f3100852
-; IASM-NOT: vceq
-
- %cmp.ret_ext = zext <8 x i1> %cmp to <8 x i16>
- ret <8 x i16> %cmp.ret_ext
-}
-
-define internal <8 x i16> @cmpNeV8I16(<8 x i16> %a, <8 x i16> %b) {
-; ASM-LABEL:cmpNeV8I16:
-; DIS-LABEL:00000240 <cmpNeV8I16>:
-; IASM-LABEL:cmpNeV8I16:
-
-entry:
- %cmp = icmp ne <8 x i16> %a, %b
-
-; ASM: vceq.i16 q0, q0, q1
-; ASM-NEXT: vmvn.i16 q0, q0
-; DIS: 240: f3100852
-; DIS-NEXT: 244: f3b005c0
-; IASM-NOT: vceq
-; IASM-NOT: vmvn
-
- %cmp.ret_ext = zext <8 x i1> %cmp to <8 x i16>
- ret <8 x i16> %cmp.ret_ext
-}
-
-define internal <8 x i16> @cmpUgtV8I16(<8 x i16> %a, <8 x i16> %b) {
-; ASM-LABEL:cmpUgtV8I16:
-; DIS-LABEL:00000260 <cmpUgtV8I16>:
-; IASM-LABEL:cmpUgtV8I16:
-
-entry:
- %cmp = icmp ugt <8 x i16> %a, %b
-
-; ASM: vcgt.u16 q0, q0, q1
-; DIS: 260: f3100342
-; IASM-NOT: vcgt
-
- %cmp.ret_ext = zext <8 x i1> %cmp to <8 x i16>
- ret <8 x i16> %cmp.ret_ext
-}
-
-define internal <8 x i16> @cmpUgeV8I16(<8 x i16> %a, <8 x i16> %b) {
-; ASM-LABEL:cmpUgeV8I16:
-; DIS-LABEL:00000270 <cmpUgeV8I16>:
-; IASM-LABEL:cmpUgeV8I16:
-
-entry:
- %cmp = icmp uge <8 x i16> %a, %b
-
-; ASM: vcge.u16 q0, q0, q1
-; DIS: 270: f3100352
-; IASM-NOT: vcge
-
- %cmp.ret_ext = zext <8 x i1> %cmp to <8 x i16>
- ret <8 x i16> %cmp.ret_ext
-}
-
-define internal <8 x i16> @cmpUltV8I16(<8 x i16> %a, <8 x i16> %b) {
-; ASM-LABEL:cmpUltV8I16:
-; DIS-LABEL:00000280 <cmpUltV8I16>:
-; IASM-LABEL:cmpUltV8I16:
-
-entry:
- %cmp = icmp ult <8 x i16> %a, %b
-
-; ASM: vcgt.u16 q1, q1, q0
-; DIS: 280: f3122340
-; IASM-NOT: vcgt
-
- %cmp.ret_ext = zext <8 x i1> %cmp to <8 x i16>
- ret <8 x i16> %cmp.ret_ext
-}
-
-define internal <8 x i16> @cmpUleV8I16(<8 x i16> %a, <8 x i16> %b) {
-; ASM-LABEL:cmpUleV8I16:
-; DIS-LABEL:000002a0 <cmpUleV8I16>:
-; IASM-LABEL:cmpUleV8I16:
-
-entry:
- %cmp = icmp ule <8 x i16> %a, %b
-
-; ASM: vcge.u16 q1, q1, q0
-; DIS: 2a0: f3122350
-; IASM-NOT: vcge
-
- %cmp.ret_ext = zext <8 x i1> %cmp to <8 x i16>
- ret <8 x i16> %cmp.ret_ext
-}
-
-define internal <8 x i16> @cmpSgtV8I16(<8 x i16> %a, <8 x i16> %b) {
-; ASM-LABEL:cmpSgtV8I16:
-; DIS-LABEL:000002c0 <cmpSgtV8I16>:
-; IASM-LABEL:cmpSgtV8I16:
-
-entry:
- %cmp = icmp sgt <8 x i16> %a, %b
-
-; ASM: vcgt.s16 q0, q0, q1
-; DIS: 2c0: f2100342
-; IASM-NOT: vcgt
-
- %cmp.ret_ext = zext <8 x i1> %cmp to <8 x i16>
- ret <8 x i16> %cmp.ret_ext
-}
-
-define internal <8 x i16> @cmpSgeV8I16(<8 x i16> %a, <8 x i16> %b) {
-; ASM-LABEL:cmpSgeV8I16:
-; DIS-LABEL:000002d0 <cmpSgeV8I16>:
-; IASM-LABEL:cmpSgeV8I16:
-
-entry:
- %cmp = icmp sge <8 x i16> %a, %b
-
-; ASM: vcge.s16 q0, q0, q1
-; DIS: 2d0: f2100352
-; IASM-NOT: vcge
-
- %cmp.ret_ext = zext <8 x i1> %cmp to <8 x i16>
- ret <8 x i16> %cmp.ret_ext
-}
-
-define internal <8 x i16> @cmpSltV8I16(<8 x i16> %a, <8 x i16> %b) {
-; ASM-LABEL:cmpSltV8I16:
-; DIS-LABEL:000002e0 <cmpSltV8I16>:
-; IASM-LABEL:cmpSltV8I16:
-
-entry:
- %cmp = icmp slt <8 x i16> %a, %b
-
-; ASM: vcgt.s16 q1, q1, q0
-; DIS: 2e0: f2122340
-; IASM-NOT: vcgt
-
- %cmp.ret_ext = zext <8 x i1> %cmp to <8 x i16>
- ret <8 x i16> %cmp.ret_ext
-}
-
-define internal <8 x i16> @cmpSleV8I16(<8 x i16> %a, <8 x i16> %b) {
-; ASM-LABEL:cmpSleV8I16:
-; DIS-LABEL:00000300 <cmpSleV8I16>:
-; IASM-LABEL:cmpSleV8I16:
-
-entry:
- %cmp = icmp sle <8 x i16> %a, %b
-
-; ASM: vcge.s16 q1, q1, q0
-; DIS: 300: f2122350
-; IASM-NOT: vcge
-
- %cmp.ret_ext = zext <8 x i1> %cmp to <8 x i16>
- ret <8 x i16> %cmp.ret_ext
-}
-
-define internal <8 x i16> @cmpEqV8I1(<8 x i16> %a, <8 x i16> %b) {
-; ASM-LABEL:cmpEqV8I1:
-; DIS-LABEL:00000320 <cmpEqV8I1>:
-; IASM-LABEL:cmpEqV8I1:
-
-entry:
- %a1 = trunc <8 x i16> %a to <8 x i1>
- %b1 = trunc <8 x i16> %b to <8 x i1>
- %cmp = icmp eq <8 x i1> %a1, %b1
-
-; ASM: vshl.u16 q0, q0, #15
-; ASM-NEXT: vshl.u16 q1, q1, #15
-; ASM-NEXT: vceq.i16 q0, q0, q1
-; DIS: 320: f29f0550
-; DIS-NEXT: 324: f29f2552
-; DIS-NEXT: 328: f3100852
-; IASM-NOT: vshl
-; IASM-NOT: vceq
-
- %cmp.ret_ext = zext <8 x i1> %cmp to <8 x i16>
- ret <8 x i16> %cmp.ret_ext
-}
-
-define internal <8 x i16> @cmpNeV8I1(<8 x i16> %a, <8 x i16> %b) {
-; ASM-LABEL:cmpNeV8I1:
-; DIS-LABEL:00000340 <cmpNeV8I1>:
-; IASM-LABEL:cmpNeV8I1:
-
-entry:
- %a1 = trunc <8 x i16> %a to <8 x i1>
- %b1 = trunc <8 x i16> %b to <8 x i1>
- %cmp = icmp ne <8 x i1> %a1, %b1
-
-; ASM: vshl.u16 q0, q0, #15
-; ASM-NEXT: vshl.u16 q1, q1, #15
-; ASM-NEXT: vceq.i16 q0, q0, q1
-; ASM-NEXT: vmvn.i16 q0, q0
-; DIS: 340: f29f0550
-; DIS-NEXT: 344: f29f2552
-; DIS-NEXT: 348: f3100852
-; DIS-NEXT: 34c: f3b005c0
-; IASM-NOT: vshl
-; IASM-NOT: vceq
-; IASM-NOT: vmvn
-
- %cmp.ret_ext = zext <8 x i1> %cmp to <8 x i16>
- ret <8 x i16> %cmp.ret_ext
-}
-
-define internal <8 x i16> @cmpUgtV8I1(<8 x i16> %a, <8 x i16> %b) {
-; ASM-LABEL:cmpUgtV8I1:
-; DIS-LABEL:00000360 <cmpUgtV8I1>:
-; IASM-LABEL:cmpUgtV8I1:
-
-entry:
- %a1 = trunc <8 x i16> %a to <8 x i1>
- %b1 = trunc <8 x i16> %b to <8 x i1>
- %cmp = icmp ugt <8 x i1> %a1, %b1
-
-; ASM: vshl.u16 q0, q0, #15
-; ASM-NEXT: vshl.u16 q1, q1, #15
-; ASM-NEXT: vcgt.u16 q0, q0, q1
-; DIS: 360: f29f0550
-; DIS-NEXT: 364: f29f2552
-; DIS-NEXT: 368: f3100342
-; IASM-NOT: vshl
-; IASM-NOT: vcgt
-
- %cmp.ret_ext = zext <8 x i1> %cmp to <8 x i16>
- ret <8 x i16> %cmp.ret_ext
-}
-
-define internal <8 x i16> @cmpUgeV8I1(<8 x i16> %a, <8 x i16> %b) {
-; ASM-LABEL:cmpUgeV8I1:
-; DIS-LABEL:00000380 <cmpUgeV8I1>:
-; IASM-LABEL:cmpUgeV8I1:
-
-entry:
- %a1 = trunc <8 x i16> %a to <8 x i1>
- %b1 = trunc <8 x i16> %b to <8 x i1>
- %cmp = icmp uge <8 x i1> %a1, %b1
-
-; ASM: vshl.u16 q0, q0, #15
-; ASM-NEXT: vshl.u16 q1, q1, #15
-; ASM-NEXT: vcge.u16 q0, q0, q1
-; DIS: 380: f29f0550
-; DIS-NEXT: 384: f29f2552
-; DIS-NEXT: 388: f3100352
-; IASM-NOT: vshl
-; IASM-NOT: vcge
-
- %cmp.ret_ext = zext <8 x i1> %cmp to <8 x i16>
- ret <8 x i16> %cmp.ret_ext
-}
-
-define internal <8 x i16> @cmpUltV8I1(<8 x i16> %a, <8 x i16> %b) {
-; ASM-LABEL:cmpUltV8I1:
-; DIS-LABEL:000003a0 <cmpUltV8I1>:
-; IASM-LABEL:cmpUltV8I1:
-
-entry:
- %a1 = trunc <8 x i16> %a to <8 x i1>
- %b1 = trunc <8 x i16> %b to <8 x i1>
- %cmp = icmp ult <8 x i1> %a1, %b1
-
-; ASM: vshl.u16 q0, q0, #15
-; ASM-NEXT: vshl.u16 q1, q1, #15
-; ASM-NEXT: vcgt.u16 q1, q1, q0
-; DIS: 3a0: f29f0550
-; DIS-NEXT: 3a4: f29f2552
-; DIS-NEXT: 3a8: f3122340
-; IASM-NOT: vshl
-; IASM-NOT: vcgt
-
- %cmp.ret_ext = zext <8 x i1> %cmp to <8 x i16>
- ret <8 x i16> %cmp.ret_ext
-}
-
-define internal <8 x i16> @cmpUleV8I1(<8 x i16> %a, <8 x i16> %b) {
-; ASM-LABEL:cmpUleV8I1:
-; DIS-LABEL:000003c0 <cmpUleV8I1>:
-; IASM-LABEL:cmpUleV8I1:
-
-entry:
- %a1 = trunc <8 x i16> %a to <8 x i1>
- %b1 = trunc <8 x i16> %b to <8 x i1>
- %cmp = icmp ule <8 x i1> %a1, %b1
-
-; ASM: vshl.u16 q0, q0, #15
-; ASM-NEXT: vshl.u16 q1, q1, #15
-; ASM-NEXT: vcge.u16 q1, q1, q0
-; DIS: 3c0: f29f0550
-; DIS-NEXT: 3c4: f29f2552
-; DIS-NEXT: 3c8: f3122350
-; IASM-NOT: vshl
-; IASM-NOT: vcge
-
- %cmp.ret_ext = zext <8 x i1> %cmp to <8 x i16>
- ret <8 x i16> %cmp.ret_ext
-}
-
-define internal <8 x i16> @cmpSgtV8I1(<8 x i16> %a, <8 x i16> %b) {
-; ASM-LABEL:cmpSgtV8I1:
-; DIS-LABEL:000003e0 <cmpSgtV8I1>:
-; IASM-LABEL:cmpSgtV8I1:
-
-entry:
- %a1 = trunc <8 x i16> %a to <8 x i1>
- %b1 = trunc <8 x i16> %b to <8 x i1>
- %cmp = icmp sgt <8 x i1> %a1, %b1
-
-; ASM: vshl.u16 q0, q0, #15
-; ASM-NEXT: vshl.u16 q1, q1, #15
-; ASM-NEXT: vcgt.s16 q0, q0, q1
-; DIS: 3e0: f29f0550
-; DIS-NEXT: 3e4: f29f2552
-; DIS-NEXT: 3e8: f2100342
-; IASM-NOT: vshl
-; IASM-NOT: vcgt
-
- %cmp.ret_ext = zext <8 x i1> %cmp to <8 x i16>
- ret <8 x i16> %cmp.ret_ext
-}
-
-define internal <8 x i16> @cmpSgeV8I1(<8 x i16> %a, <8 x i16> %b) {
-; ASM-LABEL:cmpSgeV8I1:
-; DIS-LABEL:00000400 <cmpSgeV8I1>:
-; IASM-LABEL:cmpSgeV8I1:
-
-entry:
- %a1 = trunc <8 x i16> %a to <8 x i1>
- %b1 = trunc <8 x i16> %b to <8 x i1>
- %cmp = icmp sge <8 x i1> %a1, %b1
-
-; ASM: vshl.u16 q0, q0, #15
-; ASM-NEXT: vshl.u16 q1, q1, #15
-; ASM-NEXT: vcge.s16 q0, q0, q1
-; DIS: 400: f29f0550
-; DIS-NEXT: 404: f29f2552
-; DIS-NEXT: 408: f2100352
-; IASM-NOT: vshl
-; IASM-NOT: vcge
-
- %cmp.ret_ext = zext <8 x i1> %cmp to <8 x i16>
- ret <8 x i16> %cmp.ret_ext
-}
-
-define internal <8 x i16> @cmpSltV8I1(<8 x i16> %a, <8 x i16> %b) {
-; ASM-LABEL:cmpSltV8I1:
-; DIS-LABEL:00000420 <cmpSltV8I1>:
-; IASM-LABEL:cmpSltV8I1:
-
-entry:
- %a1 = trunc <8 x i16> %a to <8 x i1>
- %b1 = trunc <8 x i16> %b to <8 x i1>
- %cmp = icmp slt <8 x i1> %a1, %b1
-
-; ASM: vshl.u16 q0, q0, #15
-; ASM-NEXT: vshl.u16 q1, q1, #15
-; ASM-NEXT: vcgt.s16 q1, q1, q0
-; DIS: 420: f29f0550
-; DIS-NEXT: 424: f29f2552
-; DIS-NEXT: 428: f2122340
-; IASM-NOT: vshl
-; IASM-NOT: vcgt
-
- %cmp.ret_ext = zext <8 x i1> %cmp to <8 x i16>
- ret <8 x i16> %cmp.ret_ext
-}
-
-define internal <8 x i16> @cmpSleV8I1(<8 x i16> %a, <8 x i16> %b) {
-; ASM-LABEL:cmpSleV8I1:
-; DIS-LABEL:00000440 <cmpSleV8I1>:
-; IASM-LABEL:cmpSleV8I1:
-
-entry:
- %a1 = trunc <8 x i16> %a to <8 x i1>
- %b1 = trunc <8 x i16> %b to <8 x i1>
- %cmp = icmp sle <8 x i1> %a1, %b1
-
-; ASM: vshl.u16 q0, q0, #15
-; ASM-NEXT: vshl.u16 q1, q1, #15
-; ASM-NEXT: vcge.s16 q1, q1, q0
-; DIS: 440: f29f0550
-; DIS-NEXT: 444: f29f2552
-; DIS-NEXT: 448: f2122350
-; IASM-NOT: vshl
-; IASM-NOT: vcge
-
- %cmp.ret_ext = zext <8 x i1> %cmp to <8 x i16>
- ret <8 x i16> %cmp.ret_ext
-}
-
-define internal <16 x i8> @cmpEqV16I8(<16 x i8> %a, <16 x i8> %b) {
-; ASM-LABEL:cmpEqV16I8:
-; DIS-LABEL:00000460 <cmpEqV16I8>:
-; IASM-LABEL:cmpEqV16I8:
-
-entry:
- %cmp = icmp eq <16 x i8> %a, %b
-
-; ASM: vceq.i8 q0, q0, q1
-; DIS: 460: f3000852
-; IASM-NOT: vceq
-
- %cmp.ret_ext = zext <16 x i1> %cmp to <16 x i8>
- ret <16 x i8> %cmp.ret_ext
-}
-
-define internal <16 x i8> @cmpNeV16I8(<16 x i8> %a, <16 x i8> %b) {
-; ASM-LABEL:cmpNeV16I8:
-; DIS-LABEL:00000470 <cmpNeV16I8>:
-; IASM-LABEL:cmpNeV16I8:
-
-entry:
- %cmp = icmp ne <16 x i8> %a, %b
-
-; ASM: vceq.i8 q0, q0, q1
-; ASM-NEXT: vmvn.i8 q0, q0
-; DIS: 470: f3000852
-; DIS-NEXT: 474: f3b005c0
-; IASM-NOT: vceq
-; IASM-NOT: vmvn
-
- %cmp.ret_ext = zext <16 x i1> %cmp to <16 x i8>
- ret <16 x i8> %cmp.ret_ext
-}
-
-define internal <16 x i8> @cmpUgtV16I8(<16 x i8> %a, <16 x i8> %b) {
-; ASM-LABEL:cmpUgtV16I8:
-; DIS-LABEL:00000490 <cmpUgtV16I8>:
-; IASM-LABEL:cmpUgtV16I8:
-
-entry:
- %cmp = icmp ugt <16 x i8> %a, %b
-
-; ASM: vcgt.u8 q0, q0, q1
-; DIS: 490: f3000342
-; IASM-NOT: vcgt
-
- %cmp.ret_ext = zext <16 x i1> %cmp to <16 x i8>
- ret <16 x i8> %cmp.ret_ext
-}
-
-define internal <16 x i8> @cmpUgeV16I8(<16 x i8> %a, <16 x i8> %b) {
-; ASM-LABEL:cmpUgeV16I8:
-; DIS-LABEL:000004a0 <cmpUgeV16I8>:
-; IASM-LABEL:cmpUgeV16I8:
-
-entry:
- %cmp = icmp uge <16 x i8> %a, %b
-
-; ASM: vcge.u8 q0, q0, q1
-; DIS: 4a0: f3000352
-; IASM-NOT: vcge
-
- %cmp.ret_ext = zext <16 x i1> %cmp to <16 x i8>
- ret <16 x i8> %cmp.ret_ext
-}
-
-define internal <16 x i8> @cmpUltV16I8(<16 x i8> %a, <16 x i8> %b) {
-; ASM-LABEL:cmpUltV16I8:
-; DIS-LABEL:000004b0 <cmpUltV16I8>:
-; IASM-LABEL:cmpUltV16I8:
-
-entry:
- %cmp = icmp ult <16 x i8> %a, %b
-
-; ASM: vcgt.u8 q1, q1, q0
-; DIS: 4b0: f3022340
-; IASM-NOT: vcgt
-
- %cmp.ret_ext = zext <16 x i1> %cmp to <16 x i8>
- ret <16 x i8> %cmp.ret_ext
-}
-
-define internal <16 x i8> @cmpUleV16I8(<16 x i8> %a, <16 x i8> %b) {
-; ASM-LABEL:cmpUleV16I8:
-; DIS-LABEL:000004d0 <cmpUleV16I8>:
-; IASM-LABEL:cmpUleV16I8:
-
-entry:
- %cmp = icmp ule <16 x i8> %a, %b
-
-; ASM: vcge.u8 q1, q1, q0
-; DIS: 4d0: f3022350
-; IASM-NOT: vcge
-
- %cmp.ret_ext = zext <16 x i1> %cmp to <16 x i8>
- ret <16 x i8> %cmp.ret_ext
-}
-
-define internal <16 x i8> @cmpSgtV16I8(<16 x i8> %a, <16 x i8> %b) {
-; ASM-LABEL:cmpSgtV16I8:
-; DIS-LABEL:000004f0 <cmpSgtV16I8>:
-; IASM-LABEL:cmpSgtV16I8:
-
-entry:
- %cmp = icmp sgt <16 x i8> %a, %b
-
-; ASM: vcgt.s8 q0, q0, q1
-; DIS: 4f0: f2000342
-; IASM-NOT: vcgt
-
- %cmp.ret_ext = zext <16 x i1> %cmp to <16 x i8>
- ret <16 x i8> %cmp.ret_ext
-}
-
-define internal <16 x i8> @cmpSgeV16I8(<16 x i8> %a, <16 x i8> %b) {
-; ASM-LABEL:cmpSgeV16I8:
-; DIS-LABEL:00000500 <cmpSgeV16I8>:
-; IASM-LABEL:cmpSgeV16I8:
-
-entry:
- %cmp = icmp sge <16 x i8> %a, %b
-
-; ASM: vcge.s8 q0, q0, q1
-; DIS: 500: f2000352
-; IASM-NOT: vcge
-
- %cmp.ret_ext = zext <16 x i1> %cmp to <16 x i8>
- ret <16 x i8> %cmp.ret_ext
-}
-
-define internal <16 x i8> @cmpSltV16I8(<16 x i8> %a, <16 x i8> %b) {
-; ASM-LABEL:cmpSltV16I8:
-; DIS-LABEL:00000510 <cmpSltV16I8>:
-; IASM-LABEL:cmpSltV16I8:
-
-entry:
- %cmp = icmp slt <16 x i8> %a, %b
-
-; ASM: vcgt.s8 q1, q1, q0
-; DIS: 510: f2022340
-; IASM-NOT: vcgt
-
- %cmp.ret_ext = zext <16 x i1> %cmp to <16 x i8>
- ret <16 x i8> %cmp.ret_ext
-}
-
-define internal <16 x i8> @cmpSleV16I8(<16 x i8> %a, <16 x i8> %b) {
-; ASM-LABEL:cmpSleV16I8:
-; DIS-LABEL:00000530 <cmpSleV16I8>:
-; IASM-LABEL:cmpSleV16I8:
-
-entry:
- %cmp = icmp sle <16 x i8> %a, %b
-
-; ASM: vcge.s8 q1, q1, q0
-; DIS: 530: f2022350
-; IASM-NOT: vcge
-
- %cmp.ret_ext = zext <16 x i1> %cmp to <16 x i8>
- ret <16 x i8> %cmp.ret_ext
-}
-
-define internal <16 x i8> @cmpEqV16I1(<16 x i8> %a, <16 x i8> %b) {
-; ASM-LABEL:cmpEqV16I1:
-; DIS-LABEL:00000550 <cmpEqV16I1>:
-; IASM-LABEL:cmpEqV16I1:
-
-entry:
- %a1 = trunc <16 x i8> %a to <16 x i1>
- %b1 = trunc <16 x i8> %b to <16 x i1>
- %cmp = icmp eq <16 x i1> %a1, %b1
-
-; ASM: vshl.u8 q0, q0, #7
-; ASM-NEXT: vshl.u8 q1, q1, #7
-; ASM-NEXT: vceq.i8 q0, q0, q1
-; DIS: 550: f28f0550
-; DIS-NEXT: 554: f28f2552
-; DIS-NEXT: 558: f3000852
-; IASM-NOT: vshl
-; IASM-NOT: vceq
-
- %cmp.ret_ext = zext <16 x i1> %cmp to <16 x i8>
- ret <16 x i8> %cmp.ret_ext
-}
-
-define internal <16 x i8> @cmpNeV16I1(<16 x i8> %a, <16 x i8> %b) {
-; ASM-LABEL:cmpNeV16I1:
-; DIS-LABEL:00000570 <cmpNeV16I1>:
-; IASM-LABEL:cmpNeV16I1:
-
-entry:
- %a1 = trunc <16 x i8> %a to <16 x i1>
- %b1 = trunc <16 x i8> %b to <16 x i1>
- %cmp = icmp ne <16 x i1> %a1, %b1
-
-; ASM: vshl.u8 q0, q0, #7
-; ASM-NEXT: vshl.u8 q1, q1, #7
-; ASM-NEXT: vceq.i8 q0, q0, q1
-; ASM-NEXT: vmvn.i8 q0, q0
-; DIS: 570: f28f0550
-; DIS-NEXT: 574: f28f2552
-; DIS-NEXT: 578: f3000852
-; DIS-NEXT: 57c: f3b005c0
-; IASM-NOT: vshl
-; IASM-NOT: vceq
-; IASM-NOT: vmvn
-
- %cmp.ret_ext = zext <16 x i1> %cmp to <16 x i8>
- ret <16 x i8> %cmp.ret_ext
-}
-
-define internal <16 x i8> @cmpUgtV16I1(<16 x i8> %a, <16 x i8> %b) {
-; ASM-LABEL:cmpUgtV16I1:
-; DIS-LABEL:00000590 <cmpUgtV16I1>:
-; IASM-LABEL:cmpUgtV16I1:
-
-entry:
- %a1 = trunc <16 x i8> %a to <16 x i1>
- %b1 = trunc <16 x i8> %b to <16 x i1>
- %cmp = icmp ugt <16 x i1> %a1, %b1
-
-; ASM: vshl.u8 q0, q0, #7
-; ASM-NEXT: vshl.u8 q1, q1, #7
-; ASM-NEXT: vcgt.u8 q0, q0, q1
-; DIS: 590: f28f0550
-; DIS-NEXT: 594: f28f2552
-; DIS-NEXT: 598: f3000342
-; IASM-NOT: vshl
-; IASM-NOT: vcgt
-
- %cmp.ret_ext = zext <16 x i1> %cmp to <16 x i8>
- ret <16 x i8> %cmp.ret_ext
-}
-
-define internal <16 x i8> @cmpUgeV16I1(<16 x i8> %a, <16 x i8> %b) {
-; ASM-LABEL:cmpUgeV16I1:
-; DIS-LABEL:000005b0 <cmpUgeV16I1>:
-; IASM-LABEL:cmpUgeV16I1:
-
-entry:
- %a1 = trunc <16 x i8> %a to <16 x i1>
- %b1 = trunc <16 x i8> %b to <16 x i1>
- %cmp = icmp uge <16 x i1> %a1, %b1
-
-; ASM: vshl.u8 q0, q0, #7
-; ASM-NEXT: vshl.u8 q1, q1, #7
-; ASM-NEXT: vcge.u8 q0, q0, q1
-; DIS: 5b0: f28f0550
-; DIS-NEXT: 5b4: f28f2552
-; DIS-NEXT: 5b8: f3000352
-; IASM-NOT: vshl
-; IASM-NOT: vcge
-
- %cmp.ret_ext = zext <16 x i1> %cmp to <16 x i8>
- ret <16 x i8> %cmp.ret_ext
-}
-
-define internal <16 x i8> @cmpUltV16I1(<16 x i8> %a, <16 x i8> %b) {
-; ASM-LABEL:cmpUltV16I1:
-; DIS-LABEL:000005d0 <cmpUltV16I1>:
-; IASM-LABEL:cmpUltV16I1:
-
-entry:
- %a1 = trunc <16 x i8> %a to <16 x i1>
- %b1 = trunc <16 x i8> %b to <16 x i1>
- %cmp = icmp ult <16 x i1> %a1, %b1
-
-; ASM: vshl.u8 q0, q0, #7
-; ASM-NEXT: vshl.u8 q1, q1, #7
-; ASM-NEXT: vcgt.u8 q1, q1, q0
-; DIS: 5d0: f28f0550
-; DIS-NEXT: 5d4: f28f2552
-; DIS-NEXT: 5d8: f3022340
-; IASM-NOT: vshl
-; IASM-NOT: vcgt
-
- %cmp.ret_ext = zext <16 x i1> %cmp to <16 x i8>
- ret <16 x i8> %cmp.ret_ext
-}
-
-define internal <16 x i8> @cmpUleV16I1(<16 x i8> %a, <16 x i8> %b) {
-; ASM-LABEL:cmpUleV16I1:
-; DIS-LABEL:000005f0 <cmpUleV16I1>:
-; IASM-LABEL:cmpUleV16I1:
-
-entry:
- %a1 = trunc <16 x i8> %a to <16 x i1>
- %b1 = trunc <16 x i8> %b to <16 x i1>
- %cmp = icmp ule <16 x i1> %a1, %b1
-
-; ASM: vshl.u8 q0, q0, #7
-; ASM-NEXT: vshl.u8 q1, q1, #7
-; ASM-NEXT: vcge.u8 q1, q1, q0
-; DIS: 5f0: f28f0550
-; DIS-NEXT: 5f4: f28f2552
-; DIS-NEXT: 5f8: f3022350
-; IASM-NOT: vshl
-; IASM-NOT: vcge
-
- %cmp.ret_ext = zext <16 x i1> %cmp to <16 x i8>
- ret <16 x i8> %cmp.ret_ext
-}
-
-define internal <16 x i8> @cmpSgtV16I1(<16 x i8> %a, <16 x i8> %b) {
-; ASM-LABEL:cmpSgtV16I1:
-; DIS-LABEL:00000610 <cmpSgtV16I1>:
-; IASM-LABEL:cmpSgtV16I1:
-
-entry:
- %a1 = trunc <16 x i8> %a to <16 x i1>
- %b1 = trunc <16 x i8> %b to <16 x i1>
- %cmp = icmp sgt <16 x i1> %a1, %b1
-
-; ASM: vshl.u8 q0, q0, #7
-; ASM-NEXT: vshl.u8 q1, q1, #7
-; ASM-NEXT: vcgt.s8 q0, q0, q1
-; DIS: 610: f28f0550
-; DIS-NEXT: 614: f28f2552
-; DIS-NEXT: 618: f2000342
-; IASM-NOT: vshl
-; IASM-NOT: vcgt
-
- %cmp.ret_ext = zext <16 x i1> %cmp to <16 x i8>
- ret <16 x i8> %cmp.ret_ext
-}
-
-define internal <16 x i8> @cmpSgeV16I1(<16 x i8> %a, <16 x i8> %b) {
-; ASM-LABEL:cmpSgeV16I1:
-; DIS-LABEL:00000630 <cmpSgeV16I1>:
-; IASM-LABEL:cmpSgeV16I1:
-
-entry:
- %a1 = trunc <16 x i8> %a to <16 x i1>
- %b1 = trunc <16 x i8> %b to <16 x i1>
- %cmp = icmp sge <16 x i1> %a1, %b1
-
-; ASM: vshl.u8 q0, q0, #7
-; ASM-NEXT: vshl.u8 q1, q1, #7
-; ASM-NEXT: vcge.s8 q0, q0, q1
-; DIS: 630: f28f0550
-; DIS-NEXT: 634: f28f2552
-; DIS-NEXT: 638: f2000352
-; IASM-NOT: vshl
-; IASM-NOT: vcge
-
- %cmp.ret_ext = zext <16 x i1> %cmp to <16 x i8>
- ret <16 x i8> %cmp.ret_ext
-}
-
-define internal <16 x i8> @cmpSltV16I1(<16 x i8> %a, <16 x i8> %b) {
-; ASM-LABEL:cmpSltV16I1:
-; DIS-LABEL:00000650 <cmpSltV16I1>:
-; IASM-LABEL:cmpSltV16I1:
-
-entry:
- %a1 = trunc <16 x i8> %a to <16 x i1>
- %b1 = trunc <16 x i8> %b to <16 x i1>
- %cmp = icmp slt <16 x i1> %a1, %b1
-
-; ASM: vshl.u8 q0, q0, #7
-; ASM-NEXT: vshl.u8 q1, q1, #7
-; ASM-NEXT: vcgt.s8 q1, q1, q0
-; DIS: 650: f28f0550
-; DIS-NEXT: 654: f28f2552
-; DIS-NEXT: 658: f2022340
-; IASM-NOT: vshl
-; IASM-NOT: vcgt
-
- %cmp.ret_ext = zext <16 x i1> %cmp to <16 x i8>
- ret <16 x i8> %cmp.ret_ext
-}
-
-define internal <16 x i8> @cmpSleV16I1(<16 x i8> %a, <16 x i8> %b) {
-; ASM-LABEL:cmpSleV16I1:
-; DIS-LABEL:00000670 <cmpSleV16I1>:
-; IASM-LABEL:cmpSleV16I1:
-
-entry:
- %a1 = trunc <16 x i8> %a to <16 x i1>
- %b1 = trunc <16 x i8> %b to <16 x i1>
- %cmp = icmp sle <16 x i1> %a1, %b1
-
-; ASM: vshl.u8 q0, q0, #7
-; ASM-NEXT: vshl.u8 q1, q1, #7
-; ASM-NEXT: vcge.s8 q1, q1, q0
-; DIS: 670: f28f0550
-; DIS-NEXT: 674: f28f2552
-; DIS-NEXT: 678: f2022350
-; IASM-NOT: vshl
-; IASM-NOT: vcge
-
- %cmp.ret_ext = zext <16 x i1> %cmp to <16 x i8>
- ret <16 x i8> %cmp.ret_ext
-}
-
-define internal <4 x i32> @cmpFalseV4Float(<4 x float> %a, <4 x float> %b) {
-; ASM-LABEL:cmpFalseV4Float:
-; DIS-LABEL:00000690 <cmpFalseV4Float>:
-; IASM-LABEL:cmpFalseV4Float:
-
-entry:
- %cmp = fcmp false <4 x float> %a, %b
-
-; ASM: vmov.i32 q0, #0
-; DIS: 690: f2800050
-; IASM-NOT: vmov
-
- %zext = zext <4 x i1> %cmp to <4 x i32>
- ret <4 x i32> %zext
-}
-
-define internal <4 x i32> @cmpOeqV4Float(<4 x float> %a, <4 x float> %b) {
-; ASM-LABEL:cmpOeqV4Float:
-; DIS-LABEL:000006a0 <cmpOeqV4Float>:
-; IASM-LABEL:cmpOeqV4Float:
-
-entry:
- %cmp = fcmp oeq <4 x float> %a, %b
-
-; ASM: vceq.f32 q0, q0, q1
-; DIS: 6a0: f2000e42
-; IASM-NOT: vceq
-
- %zext = zext <4 x i1> %cmp to <4 x i32>
- ret <4 x i32> %zext
-}
-
-define internal <4 x i32> @cmpOgtV4Float(<4 x float> %a, <4 x float> %b) {
-; ASM-LABEL:cmpOgtV4Float:
-; DIS-LABEL:000006b0 <cmpOgtV4Float>:
-; IASM-LABEL:cmpOgtV4Float:
-
-entry:
- %cmp = fcmp ogt <4 x float> %a, %b
-
-; ASM: vcgt.f32 q0, q0, q1
-; DIS: 6b0: f3200e42
-; IASM-NOT: vcgt
-
- %zext = zext <4 x i1> %cmp to <4 x i32>
- ret <4 x i32> %zext
-}
-
-define internal <4 x i32> @cmpOgeV4Float(<4 x float> %a, <4 x float> %b) {
-; ASM-LABEL:cmpOgeV4Float:
-; DIS-LABEL:000006c0 <cmpOgeV4Float>:
-; IASM-LABEL:cmpOgeV4Float:
-
-entry:
- %cmp = fcmp oge <4 x float> %a, %b
-
-; ASM: vcge.f32 q0, q0, q1
-; DIS: 6c0: f3000e42
-; IASM-NOT: vcge
-
- %zext = zext <4 x i1> %cmp to <4 x i32>
- ret <4 x i32> %zext
-}
-
-define internal <4 x i32> @cmpOltV4Float(<4 x float> %a, <4 x float> %b) {
-; ASM-LABEL:cmpOltV4Float:
-; DIS-LABEL:000006d0 <cmpOltV4Float>:
-; IASM-LABEL:cmpOltV4Float:
-
-entry:
- %cmp = fcmp olt <4 x float> %a, %b
-
-; ASM: vcgt.f32 q1, q1, q0
-; DIS: 6d0: f3222e40
-; IASM-NOT: vcgt
-
- %zext = zext <4 x i1> %cmp to <4 x i32>
- ret <4 x i32> %zext
-}
-
-define internal <4 x i32> @cmpOleV4Float(<4 x float> %a, <4 x float> %b) {
-; ASM-LABEL:cmpOleV4Float:
-; DIS-LABEL:000006f0 <cmpOleV4Float>:
-; IASM-LABEL:cmpOleV4Float:
-
-entry:
- %cmp = fcmp ole <4 x float> %a, %b
-
-; ASM: vcge.f32 q1, q1, q0
-; DIS: 6f0: f3022e40
-; IASM-NOT: vcge
-
- %zext = zext <4 x i1> %cmp to <4 x i32>
- ret <4 x i32> %zext
-}
-
-define internal <4 x i32> @cmpOrdV4Float(<4 x float> %a, <4 x float> %b) {
-; ASM-LABEL:cmpOrdV4Float:
-; DIS-LABEL:00000710 <cmpOrdV4Float>:
-; IASM-LABEL:cmpOrdV4Float:
-
-entry:
- %cmp = fcmp ord <4 x float> %a, %b
-
-; ASM: vcge.f32 q2, q0, q1
-; ASM-NEXT: vcgt.f32 q1, q1, q0
-; DIS: 710: f3004e42
-; DIS-NEXT: 714: f3222e40
-; IASM-NOT: vcge
-; IASM-NOT: vcgt
-
- %zext = zext <4 x i1> %cmp to <4 x i32>
- ret <4 x i32> %zext
-}
-
-define internal <4 x i32> @cmpUeqV4Float(<4 x float> %a, <4 x float> %b) {
-; ASM-LABEL:cmpUeqV4Float:
-; DIS-LABEL:00000730 <cmpUeqV4Float>:
-; IASM-LABEL:cmpUeqV4Float:
-
-entry:
- %cmp = fcmp ueq <4 x float> %a, %b
-
-; ASM: vcgt.f32 q2, q0, q1
-; ASM-NEXT: vcgt.f32 q1, q1, q0
-; ASM-NEXT: vorr.i32 q2, q2, q1
-; ASM-NEXT: vmvn.i32 q2, q2
-; DIS: 730: f3204e42
-; DIS-NEXT: 734: f3222e40
-; DIS-NEXT: 738: f2244152
-; DIS-NEXT: 73c: f3b045c4
-; IASM-NOT: vcgt
-; IASM-NOT: vorr
-; IASM-NOT: vmvn
-
- %zext = zext <4 x i1> %cmp to <4 x i32>
- ret <4 x i32> %zext
-}
-
-define internal <4 x i32> @cmpUgtV4Float(<4 x float> %a, <4 x float> %b) {
-; ASM-LABEL:cmpUgtV4Float:
-; DIS-LABEL:00000750 <cmpUgtV4Float>:
-; IASM-LABEL:cmpUgtV4Float:
-
-entry:
- %cmp = fcmp ugt <4 x float> %a, %b
-
-; ASM: vcge.f32 q1, q1, q0
-; ASM-NEXT: vmvn.i32 q1, q1
-; DIS: 750: f3022e40
-; DIS-NEXT: 754: f3b025c2
-; IASM-NOT: vcge
-; IASM-NOT: vmvn
-
- %zext = zext <4 x i1> %cmp to <4 x i32>
- ret <4 x i32> %zext
-}
-
-define internal <4 x i32> @cmpUgeV4Float(<4 x float> %a, <4 x float> %b) {
-; ASM-LABEL:cmpUgeV4Float:
-; DIS-LABEL:00000770 <cmpUgeV4Float>:
-; IASM-LABEL:cmpUgeV4Float:
-
-entry:
- %cmp = fcmp uge <4 x float> %a, %b
-
-; ASM: vcgt.f32 q1, q1, q0
-; ASM-NEXT: vmvn.i32 q1, q1
-; DIS: 770: f3222e40
-; DIS-NEXT: 774: f3b025c2
-; IASM-NOT: vcgt
-; IASM-NOT: vmvn
-
- %zext = zext <4 x i1> %cmp to <4 x i32>
- ret <4 x i32> %zext
-}
-
-define internal <4 x i32> @cmpUltV4Float(<4 x float> %a, <4 x float> %b) {
-; ASM-LABEL:cmpUltV4Float:
-; DIS-LABEL:00000790 <cmpUltV4Float>:
-; IASM-LABEL:cmpUltV4Float:
-
-entry:
- %cmp = fcmp ult <4 x float> %a, %b
-
-; ASM: vcge.f32 q0, q0, q1
-; ASM-NEXT: vmvn.i32 q0, q0
-; DIS: 790: f3000e42
-; DIS-NEXT: 794: f3b005c0
-; IASM-NOT: vcge
-; IASM-NOT: vmvn
-
- %zext = zext <4 x i1> %cmp to <4 x i32>
- ret <4 x i32> %zext
-}
-
-define internal <4 x i32> @cmpUleV4Float(<4 x float> %a, <4 x float> %b) {
-; ASM-LABEL:cmpUleV4Float:
-; DIS-LABEL:000007b0 <cmpUleV4Float>:
-; IASM-LABEL:cmpUleV4Float:
-
-entry:
- %cmp = fcmp ule <4 x float> %a, %b
-
-; ASM: vcgt.f32 q0, q0, q1
-; ASM-NEXT: vmvn.i32 q0, q0
-; DIS: 7b0: f3200e42
-; DIS-NEXT: 7b4: f3b005c0
-; IASM-NOT: vcgt
-; IASM-NOT: vmvn
-
- %zext = zext <4 x i1> %cmp to <4 x i32>
- ret <4 x i32> %zext
-}
-
-define internal <4 x i32> @cmpTrueV4Float(<4 x float> %a, <4 x float> %b) {
-; ASM-LABEL:cmpTrueV4Float:
-; DIS-LABEL:000007d0 <cmpTrueV4Float>:
-; IASM-LABEL:cmpTrueV4Float:
-
-entry:
- %cmp = fcmp true <4 x float> %a, %b
-
-; ASM: vmov.i32 q0, #1
-; DIS: 7d0: f2800051
-; IASM-NOT: vmov
-
- %zext = zext <4 x i1> %cmp to <4 x i32>
- ret <4 x i32> %zext
-}
diff --git a/third_party/subzero/tests_lit/assembler/arm32/cmp.ll b/third_party/subzero/tests_lit/assembler/arm32/cmp.ll
deleted file mode 100644
index 34847e7..0000000
--- a/third_party/subzero/tests_lit/assembler/arm32/cmp.ll
+++ /dev/null
@@ -1,196 +0,0 @@
-; Test that we handle cmp (register) and cmp (immediate).
-
-; REQUIRES: allow_dump
-
-; Compile using standalone assembler.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -Om1 \
-; RUN: | FileCheck %s --check-prefix=ASM
-
-; Show bytes in assembled standalone code.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -Om1 | FileCheck %s --check-prefix=DIS
-
-; Compile using integrated assembler.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -Om1 \
-; RUN: | FileCheck %s --check-prefix=IASM
-
-; Show bytes in assembled integrated code.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -Om1 | FileCheck %s --check-prefix=DIS
-
-define internal i32 @cmpEqI8(i32 %a, i32 %b) {
-; ASM-LABEL:cmpEqI8:
-; DIS-LABEL:00000000 <cmpEqI8>:
-; IASM-LABEL:cmpEqI8:
-
-
-entry:
-; ASM-NEXT:.LcmpEqI8$entry:
-; IASM-NEXT:.LcmpEqI8$entry:
-
- %b.arg_trunc = trunc i32 %b to i8
- %a.arg_trunc = trunc i32 %a to i8
-
-; ASM-NEXT: sub sp, sp, #24
-; DIS-NEXT: 0: e24dd018
-; IASM-NEXT: .byte 0x18
-; IASM-NEXT: .byte 0xd0
-; IASM-NEXT: .byte 0x4d
-; IASM-NEXT: .byte 0xe2
-
-; ASM-NEXT: str r0, [sp, #20]
-; ASM-NEXT: # [sp, #20] = def.pseudo
-; DIS-NEXT: 4: e58d0014
-; IASM-NEXT: .byte 0x14
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x8d
-; IASM-NEXT: .byte 0xe5
-
-; ASM-NEXT: str r1, [sp, #16]
-; ASM-NEXT: # [sp, #16] = def.pseudo
-; DIS-NEXT: 8: e58d1010
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0x8d
-; IASM-NEXT: .byte 0xe5
-
-; ASM-NEXT: ldr r0, [sp, #16]
-; DIS-NEXT: c: e59d0010
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x9d
-; IASM-NEXT: .byte 0xe5
-
-; ASM-NEXT: strb r0, [sp, #12]
-; ASM-NEXT: # [sp, #12] = def.pseudo
-; DIS-NEXT: 10: e5cd000c
-; IASM-NEXT: .byte 0xc
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xcd
-; IASM-NEXT: .byte 0xe5
-
-; ASM-NEXT: ldr r0, [sp, #20]
-; DIS-NEXT: 14: e59d0014
-; IASM-NEXT: .byte 0x14
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x9d
-; IASM-NEXT: .byte 0xe5
-
-; ASM-NEXT: strb r0, [sp, #8]
-; ASM-NEXT: # [sp, #8] = def.pseudo
-; DIS-NEXT: 18: e5cd0008
-; IASM-NEXT: .byte 0x8
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xcd
-; IASM-NEXT: .byte 0xe5
-
-; ASM-NEXT: mov r0, #0
-; DIS-NEXT: 1c: e3a00000
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xa0
-; IASM-NEXT: .byte 0xe3
-
-; ASM-NEXT: ldrb r1, [sp, #8]
-; DIS-NEXT: 20: e5dd1008
-; IASM-NEXT: .byte 0x8
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0xdd
-; IASM-NEXT: .byte 0xe5
-
-; ASM-NEXT: lsl r1, r1, #24
-; DIS-NEXT: 24: e1a01c01
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x1c
-; IASM-NEXT: .byte 0xa0
-; IASM-NEXT: .byte 0xe1
-
-; ASM-NEXT: ldrb r2, [sp, #12]
-; DIS-NEXT: 28: e5dd200c
-; IASM-NEXT: .byte 0xc
-; IASM-NEXT: .byte 0x20
-; IASM-NEXT: .byte 0xdd
-; IASM-NEXT: .byte 0xe5
-
-; ******** CMP instruction test **************
-
- %cmp = icmp eq i8 %a.arg_trunc, %b.arg_trunc
-
-; ASM-NEXT: cmp r1, r2, lsl #24
-; DIS-NEXT: 2c: e1510c02
-; IASM-NEXT: .byte 0x2
-; IASM-NEXT: .byte 0xc
-; IASM-NEXT: .byte 0x51
-; IASM-NEXT: .byte 0xe1
-
- %cmp.ret_ext = zext i1 %cmp to i32
- ret i32 %cmp.ret_ext
-}
-
-define internal i32 @cmpEqI32(i32 %a, i32 %b) {
-; ASM-LABEL:cmpEqI32:
-; DIS-LABEL:00000050 <cmpEqI32>:
-; IASM-LABEL:cmpEqI32:
-
-entry:
-; ASM-NEXT:.LcmpEqI32$entry:
-; IASM-NEXT:.LcmpEqI32$entry:
-
-; ASM-NEXT: sub sp, sp, #16
-; DIS-NEXT: 50: e24dd010
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0xd0
-; IASM-NEXT: .byte 0x4d
-; IASM-NEXT: .byte 0xe2
-
-; ASM-NEXT: str r0, [sp, #12]
-; ASM-NEXT: # [sp, #12] = def.pseudo
-; DIS-NEXT: 54: e58d000c
-; IASM-NEXT: .byte 0xc
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x8d
-; IASM-NEXT: .byte 0xe5
-
-; ASM-NEXT: str r1, [sp, #8]
-; ASM-NEXT: # [sp, #8] = def.pseudo
-; DIS-NEXT: 58: e58d1008
-; IASM-NEXT: .byte 0x8
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0x8d
-; IASM-NEXT: .byte 0xe5
-
-; ASM-NEXT: mov r0, #0
-; DIS-NEXT: 5c: e3a00000
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xa0
-; IASM-NEXT: .byte 0xe3
-
-; ASM-NEXT: ldr r1, [sp, #12]
-; DIS-NEXT: 60: e59d100c
-; IASM-NEXT: .byte 0xc
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0x9d
-; IASM-NEXT: .byte 0xe5
-
-; ASM-NEXT: ldr r2, [sp, #8]
-; DIS-NEXT: 64: e59d2008
-; IASM-NEXT: .byte 0x8
-; IASM-NEXT: .byte 0x20
-; IASM-NEXT: .byte 0x9d
-; IASM-NEXT: .byte 0xe5
-
-; ******** CMP instruction test **************
-
- %cmp = icmp eq i32 %a, %b
-
-; ASM-NEXT: cmp r1, r2
-; DIS-NEXT: 68: e1510002
-; IASM-NEXT: .byte 0x2
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x51
-; IASM-NEXT: .byte 0xe1
-
- %cmp.ret_ext = zext i1 %cmp to i32
- ret i32 %cmp.ret_ext
-}
diff --git a/third_party/subzero/tests_lit/assembler/arm32/div-vec.ll b/third_party/subzero/tests_lit/assembler/arm32/div-vec.ll
deleted file mode 100644
index 91b953b..0000000
--- a/third_party/subzero/tests_lit/assembler/arm32/div-vec.ll
+++ /dev/null
@@ -1,367 +0,0 @@
-; Show that we know how to translate vector division instructions.
-
-; REQUIRES: allow_dump
-
-; Compile using standalone assembler.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -O2 -mattr=hwdiv-arm \
-; RUN: | FileCheck %s --check-prefix=ASM
-
-; Show bytes in assembled standalone code.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -O2 -mattr=hwdiv-arm \
-; RUN: | FileCheck %s --check-prefix=DIS
-
-; Compile using integrated assembler.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -O2 -mattr=hwdiv-arm \
-; RUN: | FileCheck %s --check-prefix=IASM
-
-; Show bytes in assembled integrated code.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -O2 -mattr=hwdiv-arm \
-; RUN: | FileCheck %s --check-prefix=DIS
-
-define internal <4 x float> @testVdivFloat4(<4 x float> %v1, <4 x float> %v2) {
-; ASM-LABEL: testVdivFloat4:
-; DIS-LABEL: 00000000 <testVdivFloat4>:
-; IASM-LABEL: testVdivFloat4:
-
-entry:
- %res = fdiv <4 x float> %v1, %v2
-
-; TODO(eholk): this code could be a lot better. Fix the code generator
-; and update the test. Same for the rest of the tests.
-
-; ASM: vdiv.f32 s12, s12, s13
-; ASM-NEXT: vmov.f32 s8, s12
-; ASM: vdiv.f32 s12, s12, s13
-; ASM-NEXT: vmov.f32 s9, s12
-; ASM: vdiv.f32 s12, s12, s13
-; ASM-NEXT: vmov.f32 s10, s12
-; ASM: vdiv.f32 s0, s0, s4
-; ASM-NEXT: vmov.f32 s11, s0
-
-; DIS: 8: ee866a26
-; DIS: 18: ee866a26
-; DIS: 28: ee866a26
-; DIS: 38: ee800a02
-
-; IASM-NOT: vdiv
-
- ret <4 x float> %res
-}
-
-define internal <4 x i32> @testVdiv4i32(<4 x i32> %v1, <4 x i32> %v2) {
-; ASM-LABEL: testVdiv4i32:
-; DIS-LABEL: 00000050 <testVdiv4i32>:
-; IASM-LABEL: testVdiv4i32:
-
-entry:
- %res = udiv <4 x i32> %v1, %v2
-
-; ASM: udiv r0, r0, r1
-; ASM: udiv r0, r0, r1
-; ASM: udiv r0, r0, r1
-; ASM: udiv r0, r0, r1
-
-; DIS: 64: e730f110
-; DIS: 80: e730f110
-; DIS: 9c: e730f110
-; DIS: b8: e730f110
-
-; IASM-NOT: udiv
-
- ret <4 x i32> %res
-}
-
-define internal <8 x i16> @testVdiv8i16(<8 x i16> %v1, <8 x i16> %v2) {
-; ASM-LABEL: testVdiv8i16:
-; DIS-LABEL: 000000d0 <testVdiv8i16>:
-; IASM-LABEL: testVdiv8i16:
-
-entry:
- %res = udiv <8 x i16> %v1, %v2
-
-; ASM: uxth r0, r0
-; ASM: uxth r1, r1
-; ASM: udiv r0, r0, r1
-; ASM: uxth r0, r0
-; ASM: uxth r1, r1
-; ASM: udiv r0, r0, r1
-; ASM: uxth r0, r0
-; ASM: uxth r1, r1
-; ASM: udiv r0, r0, r1
-; ASM: uxth r0, r0
-; ASM: uxth r1, r1
-; ASM: udiv r0, r0, r1
-; ASM: uxth r0, r0
-; ASM: uxth r1, r1
-; ASM: udiv r0, r0, r1
-; ASM: uxth r0, r0
-; ASM: uxth r1, r1
-; ASM: udiv r0, r0, r1
-; ASM: uxth r0, r0
-; ASM: uxth r1, r1
-; ASM: udiv r0, r0, r1
-; ASM: uxth r0, r0
-; ASM: uxth r1, r1
-; ASM: udiv r0, r0, r1
-
-; DIS: e4: e6ff0070
-; DIS: e8: e6ff1071
-; DIS: ec: e730f110
-; DIS: 108: e6ff0070
-; DIS: 10c: e6ff1071
-; DIS: 110: e730f110
-; DIS: 12c: e6ff0070
-; DIS: 130: e6ff1071
-; DIS: 134: e730f110
-; DIS: 150: e6ff0070
-; DIS: 154: e6ff1071
-; DIS: 158: e730f110
-; DIS: 174: e6ff0070
-; DIS: 178: e6ff1071
-; DIS: 17c: e730f110
-; DIS: 198: e6ff0070
-; DIS: 19c: e6ff1071
-; DIS: 1a0: e730f110
-; DIS: 1bc: e6ff0070
-; DIS: 1c0: e6ff1071
-; DIS: 1c4: e730f110
-; DIS: 1e0: e6ff0070
-; DIS: 1e4: e6ff1071
-; DIS: 1e8: e730f110
-
-; IASM-NOT: uxth
-; IASM-NOT: udiv
-
- ret <8 x i16> %res
-}
-
-define internal <16 x i8> @testVdiv16i8(<16 x i8> %v1, <16 x i8> %v2) {
-; ASM-LABEL: testVdiv16i8:
-; DIS-LABEL: 00000200 <testVdiv16i8>:
-; IASM-LABEL: testVdiv16i8:
-
-entry:
- %res = udiv <16 x i8> %v1, %v2
-
-; ASM: uxtb r0, r0
-; ASM: uxtb r1, r1
-; ASM: udiv r0, r0, r1
-; ASM: uxtb r0, r0
-; ASM: uxtb r1, r1
-; ASM: udiv r0, r0, r1
-; ASM: uxtb r0, r0
-; ASM: uxtb r1, r1
-; ASM: udiv r0, r0, r1
-; ASM: uxtb r0, r0
-; ASM: uxtb r1, r1
-; ASM: udiv r0, r0, r1
-; ASM: uxtb r0, r0
-; ASM: uxtb r1, r1
-; ASM: udiv r0, r0, r1
-; ASM: uxtb r0, r0
-; ASM: uxtb r1, r1
-; ASM: udiv r0, r0, r1
-; ASM: uxtb r0, r0
-; ASM: uxtb r1, r1
-; ASM: udiv r0, r0, r1
-; ASM: uxtb r0, r0
-; ASM: uxtb r1, r1
-; ASM: udiv r0, r0, r1
-; ASM: uxtb r0, r0
-; ASM: uxtb r1, r1
-; ASM: udiv r0, r0, r1
-; ASM: uxtb r0, r0
-; ASM: uxtb r1, r1
-; ASM: udiv r0, r0, r1
-; ASM: uxtb r0, r0
-; ASM: uxtb r1, r1
-; ASM: udiv r0, r0, r1
-; ASM: uxtb r0, r0
-; ASM: uxtb r1, r1
-; ASM: udiv r0, r0, r1
-; ASM: uxtb r0, r0
-; ASM: uxtb r1, r1
-; ASM: udiv r0, r0, r1
-; ASM: uxtb r0, r0
-; ASM: uxtb r1, r1
-; ASM: udiv r0, r0, r1
-; ASM: uxtb r0, r0
-; ASM: uxtb r1, r1
-; ASM: udiv r0, r0, r1
-; ASM: uxtb r0, r0
-; ASM: uxtb r1, r1
-; ASM: udiv r0, r0, r1
-
-; DIS: 214: e6ef0070
-; DIS: 218: e6ef1071
-; DIS: 21c: e730f110
-; DIS: 238: e6ef0070
-; DIS: 23c: e6ef1071
-; DIS: 240: e730f110
-; DIS: 25c: e6ef0070
-; DIS: 260: e6ef1071
-; DIS: 264: e730f110
-; DIS: 280: e6ef0070
-; DIS: 284: e6ef1071
-; DIS: 288: e730f110
-; DIS: 2a4: e6ef0070
-; DIS: 2a8: e6ef1071
-; DIS: 2ac: e730f110
-; DIS: 2c8: e6ef0070
-; DIS: 2cc: e6ef1071
-; DIS: 2d0: e730f110
-; DIS: 2ec: e6ef0070
-; DIS: 2f0: e6ef1071
-; DIS: 2f4: e730f110
-; DIS: 310: e6ef0070
-; DIS: 314: e6ef1071
-; DIS: 318: e730f110
-; DIS: 334: e6ef0070
-; DIS: 338: e6ef1071
-; DIS: 33c: e730f110
-; DIS: 358: e6ef0070
-; DIS: 35c: e6ef1071
-; DIS: 360: e730f110
-; DIS: 37c: e6ef0070
-; DIS: 380: e6ef1071
-; DIS: 384: e730f110
-; DIS: 3a0: e6ef0070
-; DIS: 3a4: e6ef1071
-; DIS: 3a8: e730f110
-; DIS: 3c4: e6ef0070
-; DIS: 3c8: e6ef1071
-; DIS: 3cc: e730f110
-; DIS: 3e8: e6ef0070
-; DIS: 3ec: e6ef1071
-; DIS: 3f0: e730f110
-; DIS: 40c: e6ef0070
-; DIS: 410: e6ef1071
-; DIS: 414: e730f110
-; DIS: 430: e6ef0070
-; DIS: 434: e6ef1071
-; DIS: 438: e730f110
-
-; IASM-NOT: uxtb
-; IASM-NOT: udiv
-
- ret <16 x i8> %res
-}
-
-define internal <4 x i32> @testSdiv4i32(<4 x i32> %v1, <4 x i32> %v2) {
-; ASM-LABEL: testSdiv4i32:
-; IASM-LABEL: testSdiv4i32:
-
-entry:
- %res = sdiv <4 x i32> %v1, %v2
-
-; ASM: sdiv r0, r0, r1
-; ASM: sdiv r0, r0, r1
-; ASM: sdiv r0, r0, r1
-; ASM: sdiv r0, r0, r1
-
-; IASM-NOT: sdiv
-
- ret <4 x i32> %res
-}
-
-define internal <8 x i16> @testSdiv8i16(<8 x i16> %v1, <8 x i16> %v2) {
-; ASM-LABEL: testSdiv8i16:
-; IASM-LABEL: testSdiv8i16:
-
-entry:
- %res = sdiv <8 x i16> %v1, %v2
-
-; ASM: sxth r0, r0
-; ASM: sxth r1, r1
-; ASM: sdiv r0, r0, r1
-; ASM: sxth r0, r0
-; ASM: sxth r1, r1
-; ASM: sdiv r0, r0, r1
-; ASM: sxth r0, r0
-; ASM: sxth r1, r1
-; ASM: sdiv r0, r0, r1
-; ASM: sxth r0, r0
-; ASM: sxth r1, r1
-; ASM: sdiv r0, r0, r1
-; ASM: sxth r0, r0
-; ASM: sxth r1, r1
-; ASM: sdiv r0, r0, r1
-; ASM: sxth r0, r0
-; ASM: sxth r1, r1
-; ASM: sdiv r0, r0, r1
-; ASM: sxth r0, r0
-; ASM: sxth r1, r1
-; ASM: sdiv r0, r0, r1
-; ASM: sxth r0, r0
-; ASM: sxth r1, r1
-; ASM: sdiv r0, r0, r1
-
-; IASM-NOT: sxth
-; IASM-NOT: sdiv
-
- ret <8 x i16> %res
-}
-
-define internal <16 x i8> @testSdiv16i8(<16 x i8> %v1, <16 x i8> %v2) {
-; ASM-LABEL: testSdiv16i8:
-; IASM-LABEL: testSdiv16i8:
-
-entry:
- %res = sdiv <16 x i8> %v1, %v2
-
-; ASM: sxtb r0, r0
-; ASM: sxtb r1, r1
-; ASM: sdiv r0, r0, r1
-; ASM: sxtb r0, r0
-; ASM: sxtb r1, r1
-; ASM: sdiv r0, r0, r1
-; ASM: sxtb r0, r0
-; ASM: sxtb r1, r1
-; ASM: sdiv r0, r0, r1
-; ASM: sxtb r0, r0
-; ASM: sxtb r1, r1
-; ASM: sdiv r0, r0, r1
-; ASM: sxtb r0, r0
-; ASM: sxtb r1, r1
-; ASM: sdiv r0, r0, r1
-; ASM: sxtb r0, r0
-; ASM: sxtb r1, r1
-; ASM: sdiv r0, r0, r1
-; ASM: sxtb r0, r0
-; ASM: sxtb r1, r1
-; ASM: sdiv r0, r0, r1
-; ASM: sxtb r0, r0
-; ASM: sxtb r1, r1
-; ASM: sdiv r0, r0, r1
-; ASM: sxtb r0, r0
-; ASM: sxtb r1, r1
-; ASM: sdiv r0, r0, r1
-; ASM: sxtb r0, r0
-; ASM: sxtb r1, r1
-; ASM: sdiv r0, r0, r1
-; ASM: sxtb r0, r0
-; ASM: sxtb r1, r1
-; ASM: sdiv r0, r0, r1
-; ASM: sxtb r0, r0
-; ASM: sxtb r1, r1
-; ASM: sdiv r0, r0, r1
-; ASM: sxtb r0, r0
-; ASM: sxtb r1, r1
-; ASM: sdiv r0, r0, r1
-; ASM: sxtb r0, r0
-; ASM: sxtb r1, r1
-; ASM: sdiv r0, r0, r1
-; ASM: sxtb r0, r0
-; ASM: sxtb r1, r1
-; ASM: sdiv r0, r0, r1
-; ASM: sxtb r0, r0
-; ASM: sxtb r1, r1
-; ASM: sdiv r0, r0, r1
-
-; IASM-NOT: sxtb
-; IASM-NOT: sdiv
-
- ret <16 x i8> %res
-}
diff --git a/third_party/subzero/tests_lit/assembler/arm32/dmb.ll b/third_party/subzero/tests_lit/assembler/arm32/dmb.ll
deleted file mode 100644
index cf0078a..0000000
--- a/third_party/subzero/tests_lit/assembler/arm32/dmb.ll
+++ /dev/null
@@ -1,74 +0,0 @@
-; Show that we know how to encode the dmb instruction.
-
-; REQUIRES: allow_dump
-
-; Compile using standalone assembler.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -Om1 \
-; RUN: | FileCheck %s --check-prefix=ASM
-
-; Show bytes in assembled standalone code.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -Om1 | FileCheck %s --check-prefix=DIS
-
-; Compile using integrated assembler.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -Om1 \
-; RUN: | FileCheck %s --check-prefix=IASM
-
-; Show bytes in assembled integrated code.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -Om1 | FileCheck %s --check-prefix=DIS
-
-declare i8 @llvm.nacl.atomic.load.i8(i8*, i32)
-
-define internal i32 @test_atomic_load_8(i32 %iptr) {
-; ASM-LABEL:test_atomic_load_8:
-; DIS-LABEL:00000000 <test_atomic_load_8>:
-; IASM-LABEL:test_atomic_load_8:
-
-entry:
-; ASM-NEXT:.Ltest_atomic_load_8$entry:
-; IASM-NEXT:.Ltest_atomic_load_8$entry:
-
-; ASM-NEXT: sub sp, sp, #12
-; DIS-NEXT: 0: e24dd00c
-; IASM-NEXT: .byte 0xc
-; IASM-NEXT: .byte 0xd0
-; IASM-NEXT: .byte 0x4d
-; IASM-NEXT: .byte 0xe2
-
-; ASM-NEXT: str r0, [sp, #8]
-; ASM-NEXT: # [sp, #8] = def.pseudo
-; DIS-NEXT: 4: e58d0008
-; IASM-NEXT: .byte 0x8
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x8d
-; IASM-NEXT: .byte 0xe5
-
- %ptr = inttoptr i32 %iptr to i8*
- ; parameter value "6" is for the sequential consistency memory order.
- %i = call i8 @llvm.nacl.atomic.load.i8(i8* %ptr, i32 6)
-
-; ASM-NEXT: ldr r0, [sp, #8]
-; DIS-NEXT: 8: e59d0008
-; IASM-NEXT: .byte 0x8
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x9d
-; IASM-NEXT: .byte 0xe5
-
-; ASM-NEXT: ldrb r0, [r0]
-; DIS-NEXT: c: e5d00000
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xd0
-; IASM-NEXT: .byte 0xe5
-
-; ASM-NEXT: dmb sy
-; DIS-NEXT: 10: f57ff05f
-; IASM-NEXT: .byte 0x5f
-; IASM-NEXT: .byte 0xf0
-; IASM-NEXT: .byte 0x7f
-; IASM-NEXT: .byte 0xf5
-
- %r = zext i8 %i to i32
- ret i32 %r
-}
diff --git a/third_party/subzero/tests_lit/assembler/arm32/eor.ll b/third_party/subzero/tests_lit/assembler/arm32/eor.ll
deleted file mode 100644
index 95cf47e..0000000
--- a/third_party/subzero/tests_lit/assembler/arm32/eor.ll
+++ /dev/null
@@ -1,109 +0,0 @@
-; Show that we know how to translate eor.
-
-; NOTE: We use -O2 to get rid of memory stores.
-
-; REQUIRES: allow_dump
-
-; Compile using standalone assembler.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -O2 \
-; RUN: | FileCheck %s --check-prefix=ASM
-
-; Show bytes in assembled standalone code.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -O2 | FileCheck %s --check-prefix=DIS
-
-; Compile using integrated assembler.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -O2 \
-; RUN: | FileCheck %s --check-prefix=IASM
-
-; Show bytes in assembled integrated code.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -O2 | FileCheck %s --check-prefix=DIS
-
-define internal i32 @Eor1WithR0(i32 %p) {
- %v = xor i32 %p, 1
- ret i32 %v
-}
-
-; ASM-LABEL:Eor1WithR0:
-; ASM-NEXT:.LEor1WithR0$__0:
-; ASM-NEXT: eor r0, r0, #1
-
-; DIS-LABEL:00000000 <Eor1WithR0>:
-; DIS-NEXT: 0: e2200001
-
-; IASM-LABEL:Eor1WithR0:
-; IASM-NEXT:.LEor1WithR0$__0:
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x20
-; IASM-NEXT: .byte 0xe2
-
-define internal i32 @Eor2Regs(i32 %p1, i32 %p2) {
- %v = xor i32 %p1, %p2
- ret i32 %v
-}
-
-; ASM-LABEL:Eor2Regs:
-; ASM-NEXT:.LEor2Regs$__0:
-; ASM-NEXT: eor r0, r0, r1
-
-; DIS-LABEL:00000010 <Eor2Regs>:
-; DIS-NEXT: 10: e0200001
-
-; IASM-LABEL:Eor2Regs:
-; IASM-NEXT:.LEor2Regs$__0:
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x20
-; IASM-NEXT: .byte 0xe0
-
-define internal i64 @EorI64WithR0R1(i64 %p) {
- %v = xor i64 %p, 1
- ret i64 %v
-}
-
-; ASM-LABEL:EorI64WithR0R1:
-; ASM-NEXT:.LEorI64WithR0R1$__0:
-; ASM-NEXT: eor r0, r0, #1
-; ASM-NEXT: eor r1, r1, #0
-
-; DIS-LABEL:00000020 <EorI64WithR0R1>:
-; DIS-NEXT: 20: e2200001
-; DIS-NEXT: 24: e2211000
-
-; IASM-LABEL:EorI64WithR0R1:
-; IASM-NEXT:.LEorI64WithR0R1$__0:
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x20
-; IASM-NEXT: .byte 0xe2
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0x21
-; IASM-NEXT: .byte 0xe2
-
-define internal i64 @EorI64Regs(i64 %p1, i64 %p2) {
- %v = xor i64 %p1, %p2
- ret i64 %v
-}
-
-; ASM-LABEL:EorI64Regs:
-; ASM-NEXT:.LEorI64Regs$__0:
-; ASM-NEXT: eor r0, r0, r2
-; ASM-NEXT: eor r1, r1, r3
-
-; DIS-LABEL:00000030 <EorI64Regs>:
-; DIS-NEXT: 30: e0200002
-; DIS-NEXT: 34: e0211003
-
-; IASM-LABEL:EorI64Regs:
-; IASM-NEXT:.LEorI64Regs$__0:
-; IASM-NEXT: .byte 0x2
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x20
-; IASM-NEXT: .byte 0xe0
-; IASM-NEXT: .byte 0x3
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0x21
-; IASM-NEXT: .byte 0xe0
diff --git a/third_party/subzero/tests_lit/assembler/arm32/global-load-store.ll b/third_party/subzero/tests_lit/assembler/arm32/global-load-store.ll
deleted file mode 100644
index 3f7f6a7..0000000
--- a/third_party/subzero/tests_lit/assembler/arm32/global-load-store.ll
+++ /dev/null
@@ -1,99 +0,0 @@
-; TODO(kschimpf): Show that we can handle global variable loads/stores.
-
-; REQUIRES: allow_dump
-
-; Compile using standalone assembler.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -O2 \
-; RUN: | FileCheck %s --check-prefix=ASM
-
-; Show bytes in assembled standalone code.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -O2 | FileCheck %s --check-prefix=DIS
-
-; Compile using integrated assembler.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -O2 \
-; RUN: | FileCheck %s --check-prefix=IASM
-
-; Show bytes in assembled integrated code.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -O2 | FileCheck %s --check-prefix=DIS
-
-@filler = internal global [128 x i8] zeroinitializer, align 4
-
-@global1 = internal global [4 x i8] zeroinitializer, align 4
-
-; ASM-LABEL: global1:
-; ASM-NEXT: .zero 4
-; ASM-NEXT: .size global1, 4
-; ASM-NEXT: .text
-; ASM-NEXT: .p2alignl 4,0xe7fedef0
-
-; IASM-LABEL:global1:
-; IASM-NEXT: .zero 4
-; IASM-NEXT: .size global1, 4
-; IASM-NEXT: .text
-; IASM-NEXT: .p2alignl 4,0xe7fedef0
-
-define internal i32 @load() {
- %addr = bitcast [4 x i8]* @global1 to i32*
- %v = load i32, i32* %addr, align 1
- ret i32 %v
-}
-
-; ASM-LABEL: load:
-; ASM-NEXT: .Lload$__0:
-; ASM-NEXT: movw r0, #:lower16:global1
-; ASM-NEXT: movt r0, #:upper16:global1
-; ASM-NEXT: ldr r0, [r0]
-; ASM-NEXT: bx lr
-
-; DIS-LABEL:00000000 <load>:
-; DIS-NEXT: 0: e3000000
-; DIS-NEXT: 4: e3400000
-; DIS-NEXT: 8: e5900000
-; DIS-NEXT: c: e12fff1e
-
-; IASM-LABEL:load:
-; IASM-NEXT: .Lload$__0:
-; IASM-NEXT: movw r0, #:lower16:global1 @ .word e3000000
-; IASM-NEXT: movt r0, #:upper16:global1 @ .word e3400000
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x90
-; IASM-NEXT: .byte 0xe5
-; IASM-NEXT: .byte 0x1e
-; IASM-NEXT: .byte 0xff
-; IASM-NEXT: .byte 0x2f
-; IASM-NEXT: .byte 0xe1
-
-define internal void @store(i32 %v) {
- %addr = bitcast [4 x i8]* @global1 to i32*
- store i32 %v, i32* %addr, align 1
- ret void
-}
-
-; ASM-LABEL:store:
-; ASM-NEXT: .Lstore$__0:
-; ASM-NEXT: movw r1, #:lower16:global1
-; ASM-NEXT: movt r1, #:upper16:global1
-; ASM-NEXT: str r0, [r1]
-; ASM-NEXT: bx lr
-
-; DIS-LABEL:00000010 <store>:
-; DIS-NEXT: 10: e3001000
-; DIS-NEXT: 14: e3401000
-; DIS-NEXT: 18: e5810000
-; DIS-NEXT: 1c: e12fff1e
-
-; IASM-LABEL:store:
-; IASM-NEXT: .Lstore$__0:
-; IASM-NEXT: movw r1, #:lower16:global1 @ .word e3001000
-; IASM-NEXT: movt r1, #:upper16:global1 @ .word e3401000
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x81
-; IASM-NEXT: .byte 0xe5
-; IASM-NEXT: .byte 0x1e
-; IASM-NEXT: .byte 0xff
-; IASM-NEXT: .byte 0x2f
-; IASM-NEXT: .byte 0xe1
diff --git a/third_party/subzero/tests_lit/assembler/arm32/insert-extract.ll b/third_party/subzero/tests_lit/assembler/arm32/insert-extract.ll
deleted file mode 100644
index 5bbb18b..0000000
--- a/third_party/subzero/tests_lit/assembler/arm32/insert-extract.ll
+++ /dev/null
@@ -1,252 +0,0 @@
-; Show that we know how to translate insertelement and extractelement.
-
-; REQUIRES: allow_dump
-
-; Compile using standalone assembler.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -Om1 \
-; RUN: | FileCheck %s --check-prefix=ASM
-
-; Show bytes in assembled standalone code.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -Om1 \
-; RUN: | FileCheck %s --check-prefix=DIS
-
-; Compile using integrated assembler.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -Om1 \
-; RUN: | FileCheck %s --check-prefix=IASM
-
-; Show bytes in assembled integrated code.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -Om1 \
-; RUN: | FileCheck %s --check-prefix=DIS
-
-define internal i32 @extract1_v4i32(<4 x i32> %src) {
-; ASM-LABEL: extract1_v4i32:
-; DIS-LABEL: 00000000 <extract1_v4i32>:
-; IASM-LABEL: extract1_v4i32:
-
- %1 = extractelement <4 x i32> %src, i32 1
-
-; ASM: vmov.32 r0, d0[1]
-; DIS: 10: ee300b10
-; IASM-NOT: vmov.32 r0, d0[1]
- ret i32 %1
-}
-
-define internal i32 @extract2_v4i32(<4 x i32> %src) {
-; ASM-LABEL: extract2_v4i32:
-; DIS-LABEL: 00000030 <extract2_v4i32>:
-; IASM-LABEL: extract2_v4i32:
-
- %1 = extractelement <4 x i32> %src, i32 2
-
-; ASM: vmov.32 r0, d1[0]
-; DIS: 40: ee110b10
-; IASM-NOT: vmov.32 r0, d1[0]
-
- ret i32 %1
-}
-
-define internal i32 @extract3_v8i16(<8 x i16> %src) {
-; ASM-LABEL: extract3_v8i16:
-; DIS-LABEL: 00000060 <extract3_v8i16>:
-; IASM-LABEL: extract3_v8i16:
-
- %1 = extractelement <8 x i16> %src, i32 3
-
-; ASM: vmov.s16 r0, d0[3]
-; DIS: 70: ee300b70
-; IASM-NOT: vmov.s16 r0, d0[3]
-
- %2 = sext i16 %1 to i32
- ret i32 %2
-}
-
-define internal i32 @extract4_v8i16(<8 x i16> %src) {
-; ASM-LABEL: extract4_v8i16:
-; DIS-LABEL: 00000090 <extract4_v8i16>:
-; IASM-LABEL: extract4_v8i16:
-
- %1 = extractelement <8 x i16> %src, i32 4
-
-; ASM: vmov.s16 r0, d1[0]
-; DIS: a0: ee110b30
-; IASM-NOT: vmov.s16 r0, d1[0]
-
- %2 = sext i16 %1 to i32
- ret i32 %2
-}
-
-define internal i32 @extract7_v4i8(<16 x i8> %src) {
-; ASM-LABEL: extract7_v4i8:
-; DIS-LABEL: 000000c0 <extract7_v4i8>:
-; IASM-LABEL: extract7_v4i8:
-
- %1 = extractelement <16 x i8> %src, i32 7
-
-; ASM: vmov.s8 r0, d0[7]
-; DIS: d0: ee700b70
-; IASM-NOT: vmov.s8 r0, d0[7]
-
- %2 = sext i8 %1 to i32
- ret i32 %2
-}
-
-define internal i32 @extract8_v16i8(<16 x i8> %src) {
-; ASM-LABEL: extract8_v16i8:
-; DIS-LABEL: 000000f0 <extract8_v16i8>:
-; IASM-LABEL: extract8_v16i8:
-
- %1 = extractelement <16 x i8> %src, i32 8
-
-; ASM: vmov.s8 r0, d1[0]
-; DIS: 100: ee510b10
-; IASM-NOT: vmov.s8 r0, d1[0]
-
- %2 = sext i8 %1 to i32
- ret i32 %2
-}
-
-define internal float @extract1_v4float(<4 x float> %src) {
-; ASM-LABEL: extract1_v4float:
-; DIS-LABEL: 00000120 <extract1_v4float>:
-; IASM-LABEL: extract1_v4float:
-
- %1 = extractelement <4 x float> %src, i32 1
-
-; ASM: vmov.f32 s0, s1
-; DIS: 130: eeb00a60
-; IASM-NOT: vmov.f32 s0, s1
-
- ret float %1
-}
-
-define internal float @extract2_v4float(<4 x float> %src) {
-; ASM-LABEL: extract2_v4float:
-; DIS-LABEL: 00000150 <extract2_v4float>:
-; IASM-LABEL: extract2_v4float:
-
- %1 = extractelement <4 x float> %src, i32 2
-
-; ASM: vmov.f32 s0, s2
-; DIS: 160: eeb00a41
-; IASM-NOT: vmov.f32 s0, s2
-
- ret float %1
-}
-
-define internal <4 x i32> @insert1_v4i32(<4 x i32> %src, i32 %s) {
-; ASM-LABEL: insert1_v4i32:
-; DIS-LABEL: 00000180 <insert1_v4i32>:
-; IASM-LABEL: insert1_v4i32:
-
- %1 = insertelement <4 x i32> %src, i32 %s, i32 1
-
-; ASM: vmov.32 d0[1], r0
-; DIS: 198: ee200b10
-; IASM-NOT: vmov.32 d0[1], r0
-
- ret <4 x i32> %1
-}
-
-define internal <4 x i32> @insert2_v4i32(<4 x i32> %src, i32 %s) {
-; ASM-LABEL: insert2_v4i32:
-; DIS-LABEL: 000001b0 <insert2_v4i32>:
-; IASM-LABEL: insert2_v4i32:
-
- %1 = insertelement <4 x i32> %src, i32 %s, i32 2
-
-; ASM: vmov.32 d1[0], r0
-; DIS: 1c8: ee010b10
-; IASM-NOT: vmov.32 d1[0], r0
-
- ret <4 x i32> %1
-}
-
-define internal <8 x i16> @insert3_v8i16(<8 x i16> %src, i32 %s) {
-; ASM-LABEL: insert3_v8i16:
-; DIS-LABEL: 000001e0 <insert3_v8i16>:
-; IASM-LABEL: insert3_v8i16:
-
- %s2 = trunc i32 %s to i16
- %1 = insertelement <8 x i16> %src, i16 %s2, i32 3
-
-; ASM: vmov.16 d0[3], r0
-; DIS: 200: ee200b70
-; IASM-NOT: vmov.16 d0[3], r0
-
- ret <8 x i16> %1
-}
-
-define internal <8 x i16> @insert4_v8i16(<8 x i16> %src, i32 %s) {
-; ASM-LABEL: insert4_v8i16:
-; DIS-LABEL: 00000220 <insert4_v8i16>:
-; IASM-LABEL: insert4_v8i16:
-
- %s2 = trunc i32 %s to i16
- %1 = insertelement <8 x i16> %src, i16 %s2, i32 4
-
-; ASM: vmov.16 d1[0], r0
-; DIS: 240: ee010b30
-; IASM-NOT: vmov.16 d1[0], r0
-
- ret <8 x i16> %1
-}
-
-define internal <16 x i8> @insert7_v4i8(<16 x i8> %src, i32 %s) {
-; ASM-LABEL: insert7_v4i8:
-; DIS-LABEL: 00000260 <insert7_v4i8>:
-; IASM-LABEL: insert7_v4i8:
-
- %s2 = trunc i32 %s to i8
- %1 = insertelement <16 x i8> %src, i8 %s2, i32 7
-
-; ASM: vmov.8 d0[7], r0
-; DIS: 280: ee600b70
-; IASM-NOT: vmov.8 d0[7], r0
-
- ret <16 x i8> %1
-}
-
-define internal <16 x i8> @insert8_v16i8(<16 x i8> %src, i32 %s) {
-; ASM-LABEL: insert8_v16i8:
-; DIS-LABEL: 000002a0 <insert8_v16i8>:
-; IASM-LABEL: insert8_v16i8:
-
- %s2 = trunc i32 %s to i8
- %1 = insertelement <16 x i8> %src, i8 %s2, i32 8
-
-; ASM: vmov.8 d1[0], r0
-; DIS: 2c0: ee410b10
-; IASM-NOT: vmov.8 d1[0], r0
-
- ret <16 x i8> %1
-}
-
-define internal <4 x float> @insert1_v4float(<4 x float> %src, float %s) {
-; ASM-LABEL: insert1_v4float:
-; DIS-LABEL: 000002e0 <insert1_v4float>:
-; IASM-LABEL: insert1_v4float:
-
- %1 = insertelement <4 x float> %src, float %s, i32 1
-
-; ASM: vmov.f32 s1, s4
-; DIS: 2f8: eef00a42
-; IASM-NOT: vmov.f32 s1, s4
-
- ret <4 x float> %1
-}
-
-define internal <4 x float> @insert2_v4float(<4 x float> %src, float %s) {
-; ASM-LABEL: insert2_v4float:
-; DIS-LABEL: 00000310 <insert2_v4float>:
-; IASM-LABEL: insert2_v4float:
-
- %1 = insertelement <4 x float> %src, float %s, i32 2
-
-; ASM: vmov.f32 s2, s4
-; DIS: 328: eeb01a42
-; IASM-NOT: vmov.f32 s2, s4
-
- ret <4 x float> %1
-}
diff --git a/third_party/subzero/tests_lit/assembler/arm32/int-extend.ll b/third_party/subzero/tests_lit/assembler/arm32/int-extend.ll
deleted file mode 100644
index 5ea1365..0000000
--- a/third_party/subzero/tests_lit/assembler/arm32/int-extend.ll
+++ /dev/null
@@ -1,113 +0,0 @@
-; Tests signed/unsigned extend to 32 bits.
-
-; Show that we know how to translate add.
-
-; NOTE: We use -O2 to get rid of memory stores.
-
-; REQUIRES: allow_dump
-
-; Compile using standalone assembler.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -O2 \
-; RUN: | FileCheck %s --check-prefix=ASM
-
-; NOTE: We use -O2 to get rid of memory stores.
-
-; Show bytes in assembled standalone code.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -O2 | FileCheck %s --check-prefix=DIS
-
-; Compile using integrated assembler.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -O2 \
-; RUN: | FileCheck %s --check-prefix=IASM
-
-; Show bytes in assembled integrated code.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -O2 | FileCheck %s --check-prefix=DIS
-
-define internal i32 @testUxtb(i32 %v) {
-; ASM-LABEL:testUxtb:
-; DIS-LABEL:00000000 <testUxtb>:
-; IASM-LABEL:testUxtb:
-
-entry:
-; ASM-NEXT:.LtestUxtb$entry:
-; IASM-NEXT:.LtestUxtb$entry:
-
- %v.b = trunc i32 %v to i8
- %res = zext i8 %v.b to i32
-
-; ASM-NEXT: uxtb r0, r0
-; DIS-NEXT: 0: e6ef0070
-; IASM-NEXT: .byte 0x70
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xef
-; IASM-NEXT: .byte 0xe6
-
- ret i32 %res
-}
-
-define internal i32 @testSxtb(i32 %v) {
-; ASM-LABEL:testSxtb:
-; DIS-LABEL:00000010 <testSxtb>:
-; IASM-LABEL:testSxtb:
-
-entry:
-; ASM-NEXT:.LtestSxtb$entry:
-; IASM-NEXT:.LtestSxtb$entry:
-
- %v.b = trunc i32 %v to i8
- %res = sext i8 %v.b to i32
-
-; ASM-NEXT: sxtb r0, r0
-; DIS-NEXT: 10: e6af0070
-; IASM-NEXT: .byte 0x70
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xaf
-; IASM-NEXT: .byte 0xe6
-
- ret i32 %res
-}
-
-define internal i32 @testUxth(i32 %v) {
-; ASM-LABEL:testUxth:
-; DIS-LABEL:00000020 <testUxth>:
-; IASM-LABEL:testUxth:
-
-entry:
-; ASM-NEXT:.LtestUxth$entry:
-; IASM-NEXT:.LtestUxth$entry:
-
- %v.h = trunc i32 %v to i16
- %res = zext i16 %v.h to i32
-
-; ASM-NEXT: uxth r0, r0
-; DIS-NEXT: 20: e6ff0070
-; IASM-NEXT: .byte 0x70
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xff
-; IASM-NEXT: .byte 0xe6
-
- ret i32 %res
-}
-
-define internal i32 @testSxth(i32 %v) {
-; ASM-LABEL:testSxth:
-; DIS-LABEL:00000030 <testSxth>:
-; IASM-LABEL:testSxth:
-
-entry:
-; ASM-NEXT:.LtestSxth$entry:
-; IASM-NEXT:.LtestSxth$entry:
-
- %v.h = trunc i32 %v to i16
- %res = sext i16 %v.h to i32
-
-; ASM-NEXT: sxth r0, r0
-; DIS-NEXT: 30: e6bf0070
-; IASM-NEXT: .byte 0x70
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xbf
-; IASM-NEXT: .byte 0xe6
-
- ret i32 %res
-}
diff --git a/third_party/subzero/tests_lit/assembler/arm32/ldr-shift.ll b/third_party/subzero/tests_lit/assembler/arm32/ldr-shift.ll
deleted file mode 100644
index 815b903..0000000
--- a/third_party/subzero/tests_lit/assembler/arm32/ldr-shift.ll
+++ /dev/null
@@ -1,116 +0,0 @@
-; Show that we know how to translate LDR/LDRH (register) instructions.
-
-; NOTE: We use -O2 to get rid of memory stores.
-
-; REQUIRES: allow_dump
-
-; Compile using standalone assembler.
-; RUN: %lc2i --filetype=asm -i %s --target=arm32 --args -O2 \
-; RUN: | FileCheck %s --check-prefix=ASM
-
-; Show bytes in assembled standalone code.
-; RUN: %lc2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -O2 | FileCheck %s --check-prefix=DIS
-
-; Compile using integrated assembler.
-; RUN: %lc2i --filetype=iasm -i %s --target=arm32 --args -O2 \
-; RUN: | FileCheck %s --check-prefix=IASM
-
-; Show bytes in assembled integrated code.
-; RUN: %lc2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -O2 | FileCheck %s --check-prefix=DIS
-
-; Define some global arrays to access.
-@ArrayInitPartial = internal global [40 x i8] c"<\00\00\00F\00\00\00P\00\00\00Z\00\00\00d\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00", align 4
-
-@Arrays = internal constant <{ i32, [4 x i8] }> <{ i32 ptrtoint ([40 x i8]* @ArrayInitPartial to i32), [4 x i8] c"\14\00\00\00" }>, align 4
-
-; Index elements of an array.
-define internal i32 @IndexArray(i32 %WhichArray, i32 %Len) {
-; ASM-LABEL:IndexArray:
-; DIS-LABEL:00000000 <IndexArray>:
-; IASM-LABEL:IndexArray:
-
-entry:
-; ASM-NEXT:.LIndexArray$entry:
-; IASM-NEXT:.LIndexArray$entry:
-
- %gep_array = mul i32 %WhichArray, 8
-
-; ASM-NEXT: push {r4}
-; DIS-NEXT: 0: e52d4004
-; IASM-NEXT: .byte 0x4
-; IASM-NEXT: .byte 0x40
-; IASM-NEXT: .byte 0x2d
-; IASM-NEXT: .byte 0xe5
-
-; ASM-NEXT: lsl r2, r0, #3
-; DIS-NEXT: 4: e1a02180
-; IASM-NEXT: .byte 0x80
-; IASM-NEXT: .byte 0x21
-; IASM-NEXT: .byte 0xa0
-; IASM-NEXT: .byte 0xe1
-
- %expanded1 = ptrtoint <{ i32, [4 x i8] }>* @Arrays to i32
- %gep = add i32 %expanded1, %gep_array
-
-; ASM-NEXT: movw r3, #:lower16:Arrays
-; DIS-NEXT: 8: e3003000
-; IASM-NEXT: movw r3, #:lower16:Arrays @ .word e3003000
-
-; ASM-NEXT: movt r3, #:upper16:Arrays
-; DIS-NEXT: c: e3403000
-; IASM-NEXT: movt r3, #:upper16:Arrays @ .word e3403000
-
- %gep3 = add i32 %gep, 4
-
-; ASM-NEXT: add r4, r3, #4
-; DIS-NEXT: 10: e2834004
-; IASM-NEXT: .byte 0x4
-; IASM-NEXT: .byte 0x40
-; IASM-NEXT: .byte 0x83
-; IASM-NEXT: .byte 0xe2
-
-; ***** Here is the use of a LDR (register) instruction.
- %gep3.asptr = inttoptr i32 %gep3 to i32*
- %v1 = load i32, i32* %gep3.asptr, align 1
-
-; ASM-NEXT: ldr r4, [r4, r0, lsl #3]
-; DIS-NEXT: 14: e7944180
-; IASM-NEXT: .byte 0x80
-; IASM-NEXT: .byte 0x41
-; IASM-NEXT: .byte 0x94
-; IASM-NEXT: .byte 0xe7
-
- %Len.asptr3 = inttoptr i32 %Len to i32*
- store i32 %v1, i32* %Len.asptr3, align 1
-
-; ASM-NEXT: str r4, [r1]
-; DIS-NEXT: 18: e5814000
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x40
-; IASM-NEXT: .byte 0x81
-; IASM-NEXT: .byte 0xe5
-
- ; Now read the value as an i16 to test ldrh (register).
- %gep3.i16ptr = inttoptr i32 %gep3 to i16*
- %v16 = load i16, i16* %gep3.i16ptr, align 1
-
-; ASM-NEXT: add r3, r3, #4
-; DIS-NEXT: 1c: e2833004
-; IASM-NEXT: .byte 0x4
-; IASM-NEXT: .byte 0x30
-; IASM-NEXT: .byte 0x83
-; IASM-NEXT: .byte 0xe2
-
-; ***** Here is the use of a LDRH (register) instruction.
-; ASM-NEXT: ldrh r3, [r3, r2]
-; DIS-NEXT: 20: e19330b2
-; IASM-NEXT: .byte 0xb2
-; IASM-NEXT: .byte 0x30
-; IASM-NEXT: .byte 0x93
-; IASM-NEXT: .byte 0xe1
-
- %ret = sext i16 %v16 to i32
- ret i32 %ret
-}
diff --git a/third_party/subzero/tests_lit/assembler/arm32/ldr-str-more.ll b/third_party/subzero/tests_lit/assembler/arm32/ldr-str-more.ll
deleted file mode 100644
index 25ed0e9..0000000
--- a/third_party/subzero/tests_lit/assembler/arm32/ldr-str-more.ll
+++ /dev/null
@@ -1,459 +0,0 @@
-; More ldr/str examples (byte and half word).
-
-; REQUIRES: allow_dump
-
-; Compile using standalone assembler.
-; RUN: %lc2i --filetype=asm -i %s --target=arm32 --args -Om1 \
-; RUN: | FileCheck %s --check-prefix=ASM
-
-; Show bytes in assembled standalone code.
-; RUN: %lc2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -Om1 | FileCheck %s --check-prefix=DIS
-
-; Compile using integrated assembler.
-; RUN: %lc2i --filetype=iasm -i %s --target=arm32 --args -Om1 \
-; RUN: | FileCheck %s --check-prefix=IASM
-
-; Show bytes in assembled integrated code.
-; RUN: %lc2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -Om1 | FileCheck %s --check-prefix=DIS
-
-
-define internal i32 @LoadStoreI1(i32 %a, i32 %b) {
-; ASM-LABEL:LoadStoreI1:
-; DIS-LABEL:00000000 <LoadStoreI1>:
-; IASM-LABEL:LoadStoreI1:
-
-entry:
-; ASM-NEXT:.LLoadStoreI1$entry:
-; IASM-NEXT:.LLoadStoreI1$entry:
-
-; ASM-NEXT: sub sp, sp, #32
-; DIS-NEXT: 0: e24dd020
-; IASM-NEXT: .byte 0x20
-; IASM-NEXT: .byte 0xd0
-; IASM-NEXT: .byte 0x4d
-; IASM-NEXT: .byte 0xe2
-
-; ASM-NEXT: str r0, [sp, #28]
-; ASM-NEXT: # [sp, #28] = def.pseudo
-; DIS-NEXT: 4: e58d001c
-; IASM-NEXT: .byte 0x1c
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x8d
-; IASM-NEXT: .byte 0xe5
-
-; ASM-NEXT: str r1, [sp, #24]
-; ASM-NEXT: # [sp, #24] = def.pseudo
-; DIS-NEXT: 8: e58d1018
-; IASM-NEXT: .byte 0x18
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0x8d
-; IASM-NEXT: .byte 0xe5
-
- %b.arg_trunc = trunc i32 %b to i1
-
-; ASM-NEXT: ldr r0, [sp, #24]
-; DIS-NEXT: c: e59d0018
-; IASM-NEXT: .byte 0x18
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x9d
-; IASM-NEXT: .byte 0xe5
-
-; ASM-NEXT: and r0, r0, #1
-; DIS-NEXT: 10: e2000001
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xe2
-
-; ASM-NEXT: strb r0, [sp, #20]
-; ASM-NEXT: # [sp, #20] = def.pseudo
-; DIS-NEXT: 14: e5cd0014
-; IASM-NEXT: .byte 0x14
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xcd
-; IASM-NEXT: .byte 0xe5
-
- %a.arg_trunc = trunc i32 %a to i1
- %conv = zext i1 %a.arg_trunc to i32
-
-; ASM-NEXT: ldr r0, [sp, #28]
-; DIS-NEXT: 18: e59d001c
-; IASM-NEXT: .byte 0x1c
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x9d
-; IASM-NEXT: .byte 0xe5
-
-; ASM-NEXT: and r0, r0, #1
-; DIS-NEXT: 1c: e2000001
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xe2
-
-; ASM-NEXT: strb r0, [sp, #16]
-; ASM-NEXT: # [sp, #16] = def.pseudo
-; DIS-NEXT: 20: e5cd0010
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xcd
-; IASM-NEXT: .byte 0xe5
-
- %add = sext i1 %b.arg_trunc to i32
-
-; ASM-NEXT: ldrb r0, [sp, #16]
-; DIS-NEXT: 24: e5dd0010
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xdd
-; IASM-NEXT: .byte 0xe5
-
-; ASM-NEXT: str r0, [sp, #12]
-; ASM-NEXT: # [sp, #12] = def.pseudo
-; DIS-NEXT: 28: e58d000c
-; IASM-NEXT: .byte 0xc
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x8d
-; IASM-NEXT: .byte 0xe5
-
- %tobool4 = icmp ne i32 %conv, %add
-
-; ASM-NEXT: mov r0, #0
-; DIS-NEXT: 2c: e3a00000
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xa0
-; IASM-NEXT: .byte 0xe3
-
-; ASM-NEXT: ldrb r1, [sp, #20]
-; DIS-NEXT: 30: e5dd1014
-; IASM-NEXT: .byte 0x14
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0xdd
-; IASM-NEXT: .byte 0xe5
-
-; ASM-NEXT: tst r1, #1
-; DIS-NEXT: 34: e3110001
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x11
-; IASM-NEXT: .byte 0xe3
-
-; ASM-NEXT: mvn r1, #0
-; DIS-NEXT: 38: e3e01000
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0xe0
-; IASM-NEXT: .byte 0xe3
-
-; ASM-NEXT: movne r0, r1
-; DIS-NEXT: 3c: 11a00001
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xa0
-; IASM-NEXT: .byte 0x11
-
-; ASM-NEXT: str r0, [sp, #8]
-; ASM-NEXT: # [sp, #8] = def.pseudo
-; DIS-NEXT: 40: e58d0008
-; IASM-NEXT: .byte 0x8
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x8d
-; IASM-NEXT: .byte 0xe5
-
- %tobool4.ret_ext = zext i1 %tobool4 to i32
-
-; ASM-NEXT: mov r0, #0
-; DIS-NEXT: 44: e3a00000
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xa0
-; IASM-NEXT: .byte 0xe3
-
-; ASM-NEXT: ldr r1, [sp, #12]
-; DIS-NEXT: 48: e59d100c
-; IASM-NEXT: .byte 0xc
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0x9d
-; IASM-NEXT: .byte 0xe5
-
-; ASM-NEXT: ldr r2, [sp, #8]
-; DIS-NEXT: 4c: e59d2008
-; IASM-NEXT: .byte 0x8
-; IASM-NEXT: .byte 0x20
-; IASM-NEXT: .byte 0x9d
-; IASM-NEXT: .byte 0xe5
-
-; ASM-NEXT: cmp r1, r2
-; DIS-NEXT: 50: e1510002
-; IASM-NEXT: .byte 0x2
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x51
-; IASM-NEXT: .byte 0xe1
-
-; ASM-NEXT: movne r0, #1
-; DIS-NEXT: 54: 13a00001
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xa0
-; IASM-NEXT: .byte 0x13
-
-; ASM-NEXT: strb r0, [sp, #4]
-; ASM-NEXT: # [sp, #4] = def.pseudo
-; DIS-NEXT: 58: e5cd0004
-; IASM-NEXT: .byte 0x4
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xcd
-; IASM-NEXT: .byte 0xe5
-
- ret i32 %tobool4.ret_ext
-
-; ASM-NEXT: ldrb r0, [sp, #4]
-; DIS-NEXT: 5c: e5dd0004
-; IASM-NEXT: .byte 0x4
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xdd
-; IASM-NEXT: .byte 0xe5
-
-; ASM-NEXT: str r0, [sp]
-; ASM-NEXT: # [sp] = def.pseudo
-; DIS-NEXT: 60: e58d0000
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x8d
-; IASM-NEXT: .byte 0xe5
-
-; ASM-NEXT: ldr r0, [sp]
-; DIS-NEXT: 64: e59d0000
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x9d
-; IASM-NEXT: .byte 0xe5
-
-; ASM-NEXT: add sp, sp, #32
-; DIS-NEXT: 68: e28dd020
-; IASM-NEXT: .byte 0x20
-; IASM-NEXT: .byte 0xd0
-; IASM-NEXT: .byte 0x8d
-; IASM-NEXT: .byte 0xe2
-
-; ASM-NEXT: bx lr
-; DIS-NEXT: 6c: e12fff1e
-; IASM-NEXT: .byte 0x1e
-; IASM-NEXT: .byte 0xff
-; IASM-NEXT: .byte 0x2f
-; IASM-NEXT: .byte 0xe1
-}
-
-
-define internal i32 @LoadStoreI16(i32 %a, i32 %b) {
-; ASM-LABEL:LoadStoreI16:
-; DIS-LABEL:00000070 <LoadStoreI16>:
-; IASM-LABEL:LoadStoreI16:
-
-entry:
-; ASM-NEXT:.LLoadStoreI16$entry:
-; IASM-NEXT:.LLoadStoreI16$entry:
-
-; ASM-NEXT: sub sp, sp, #36
-; DIS-NEXT: 70: e24dd024
-; IASM-NEXT: .byte 0x24
-; IASM-NEXT: .byte 0xd0
-; IASM-NEXT: .byte 0x4d
-; IASM-NEXT: .byte 0xe2
-
-; ASM-NEXT: str r0, [sp, #32]
-; ASM-NEXT: # [sp, #32] = def.pseudo
-; DIS-NEXT: 74: e58d0020
-; IASM-NEXT: .byte 0x20
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x8d
-; IASM-NEXT: .byte 0xe5
-
-; ASM-NEXT: str r1, [sp, #28]
-; ASM-NEXT: # [sp, #28] = def.pseudo
-; DIS-NEXT: 78: e58d101c
-; IASM-NEXT: .byte 0x1c
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0x8d
-; IASM-NEXT: .byte 0xe5
-
- %b.arg_trunc = trunc i32 %b to i16
-
-; ASM-NEXT: ldr r0, [sp, #28]
-; DIS-NEXT: 7c: e59d001c
-; IASM-NEXT: .byte 0x1c
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x9d
-; IASM-NEXT: .byte 0xe5
-
-; ASM-NEXT: strh r0, [sp, #24]
-; ASM-NEXT: # [sp, #24] = def.pseudo
-; DIS-NEXT: 80: e1cd01b8
-; IASM-NEXT: .byte 0xb8
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0xcd
-; IASM-NEXT: .byte 0xe1
-
- %a.arg_trunc = trunc i32 %a to i16
-
-; ASM-NEXT: ldr r0, [sp, #32]
-; DIS-NEXT: 84: e59d0020
-; IASM-NEXT: .byte 0x20
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x9d
-; IASM-NEXT: .byte 0xe5
-
-; ASM-NEXT: strh r0, [sp, #20]
-; ASM-NEXT: # [sp, #20] = def.pseudo
-; DIS-NEXT: 88: e1cd01b4
-; IASM-NEXT: .byte 0xb4
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0xcd
-; IASM-NEXT: .byte 0xe1
-
- %conv = zext i16 %a.arg_trunc to i32
-
-; ASM-NEXT: ldrh r0, [sp, #20]
-; DIS-NEXT: 8c: e1dd01b4
-; IASM-NEXT: .byte 0xb4
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0xdd
-; IASM-NEXT: .byte 0xe1
-
-; ASM-NEXT: uxth r0, r0
-; DIS-NEXT: 90: e6ff0070
-; IASM-NEXT: .byte 0x70
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xff
-; IASM-NEXT: .byte 0xe6
-
-; ASM-NEXT: str r0, [sp, #16]
-; ASM-NEXT: # [sp, #16] = def.pseudo
-; DIS-NEXT: 94: e58d0010
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x8d
-; IASM-NEXT: .byte 0xe5
-
- %conv1 = zext i16 %b.arg_trunc to i32
-
-; ASM-NEXT: ldrh r0, [sp, #24]
-; DIS-NEXT: 98: e1dd01b8
-; IASM-NEXT: .byte 0xb8
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0xdd
-; IASM-NEXT: .byte 0xe1
-
-; ASM-NEXT: uxth r0, r0
-; DIS-NEXT: 9c: e6ff0070
-; IASM-NEXT: .byte 0x70
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xff
-; IASM-NEXT: .byte 0xe6
-
-; ASM-NEXT: str r0, [sp, #12]
-; ASM-NEXT: # [sp, #12] = def.pseudo
-; DIS-NEXT: a0: e58d000c
-; IASM-NEXT: .byte 0xc
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x8d
-; IASM-NEXT: .byte 0xe5
-
- %add = add i32 %conv1, %conv
-
-; ASM-NEXT: ldr r0, [sp, #12]
-; DIS-NEXT: a4: e59d000c
-; IASM-NEXT: .byte 0xc
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x9d
-; IASM-NEXT: .byte 0xe5
-
-; ASM-NEXT: ldr r1, [sp, #16]
-; DIS-NEXT: a8: e59d1010
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0x9d
-; IASM-NEXT: .byte 0xe5
-
-; ASM-NEXT: add r0, r0, r1
-; DIS-NEXT: ac: e0800001
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x80
-; IASM-NEXT: .byte 0xe0
-
-; ASM-NEXT: str r0, [sp, #8]
-; ASM-NEXT: # [sp, #8] = def.pseudo
-; DIS-NEXT: b0: e58d0008
-; IASM-NEXT: .byte 0x8
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x8d
-; IASM-NEXT: .byte 0xe5
-
- %conv2 = trunc i32 %add to i16
-
-; ASM-NEXT: ldr r0, [sp, #8]
-; DIS-NEXT: b4: e59d0008
-; IASM-NEXT: .byte 0x8
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x9d
-; IASM-NEXT: .byte 0xe5
-
-; ASM-NEXT: strh r0, [sp, #4]
-; ASM-NEXT: # [sp, #4] = def.pseudo
-; DIS-NEXT: b8: e1cd00b4
-; IASM-NEXT: .byte 0xb4
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xcd
-; IASM-NEXT: .byte 0xe1
-
- %conv2.ret_ext = zext i16 %conv2 to i32
-
-; ASM-NEXT: ldrh r0, [sp, #4]
-; DIS-NEXT: bc: e1dd00b4
-; IASM-NEXT: .byte 0xb4
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xdd
-; IASM-NEXT: .byte 0xe1
-
-; ASM-NEXT: uxth r0, r0
-; DIS-NEXT: c0: e6ff0070
-; IASM-NEXT: .byte 0x70
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xff
-; IASM-NEXT: .byte 0xe6
-
-; ASM-NEXT: str r0, [sp]
-; ASM-NEXT: # [sp] = def.pseudo
-; DIS-NEXT: c4: e58d0000
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x8d
-; IASM-NEXT: .byte 0xe5
-
- ret i32 %conv2.ret_ext
-
-; ASM-NEXT: ldr r0, [sp]
-; DIS-NEXT: c8: e59d0000
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x9d
-; IASM-NEXT: .byte 0xe5
-
-; ASM-NEXT: add sp, sp, #36
-; DIS-NEXT: cc: e28dd024
-; IASM-NEXT: .byte 0x24
-; IASM-NEXT: .byte 0xd0
-; IASM-NEXT: .byte 0x8d
-; IASM-NEXT: .byte 0xe2
-
-; ASM-NEXT: bx lr
-; DIS-NEXT: d0: e12fff1e
-; IASM-NEXT: .byte 0x1e
-; IASM-NEXT: .byte 0xff
-; IASM-NEXT: .byte 0x2f
-; IASM-NEXT: .byte 0xe1
-
-}
diff --git a/third_party/subzero/tests_lit/assembler/arm32/ldrex-strex.ll b/third_party/subzero/tests_lit/assembler/arm32/ldrex-strex.ll
deleted file mode 100644
index 47e99f3..0000000
--- a/third_party/subzero/tests_lit/assembler/arm32/ldrex-strex.ll
+++ /dev/null
@@ -1,156 +0,0 @@
-; Tests assembly of ldrex and strex instructions
-
-; REQUIRES: allow_dump
-
-; Compile using standalone assembler.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -Om1 \
-; RUN: | FileCheck %s --check-prefix=ASM
-
-; Show bytes in assembled standalone code.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -Om1 | FileCheck %s --check-prefix=DIS
-
-; Compile using integrated assembler.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -Om1 \
-; RUN: | FileCheck %s --check-prefix=IASM
-
-; Show bytes in assembled integrated code.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -Om1 | FileCheck %s --check-prefix=DIS
-
-declare i8 @llvm.nacl.atomic.rmw.i8(i32, i8*, i8, i32)
-
-declare i16 @llvm.nacl.atomic.rmw.i16(i32, i16*, i16, i32)
-
-declare i32 @llvm.nacl.atomic.rmw.i32(i32, i32*, i32, i32) #0
-
-declare i64 @llvm.nacl.atomic.rmw.i64(i32, i64*, i64, i32) #0
-
-define internal i32 @testI8Form(i32 %ptr, i32 %a) {
-; ASM-LABEL:testI8Form:
-; DIS-LABEL:<testI8Form>:
-; IASM-LABEL:testI8Form:
-
-entry:
- %ptr.asptr = inttoptr i32 %ptr to i8*
- %a.arg_trunc = trunc i32 %a to i8
-
- %v = call i8 @llvm.nacl.atomic.rmw.i8(i32 1, i8* %ptr.asptr,
- i8 %a.arg_trunc, i32 6)
-
-; ****** Example of dmb *******
-; ASM: dmb sy
-; DIS: 1c: f57ff05f
-; IASM: .byte 0x5f
-; IASM-NEXT: .byte 0xf0
-; IASM-NEXT: .byte 0x7f
-; IASM-NEXT: .byte 0xf5
-
-; ***** Example of ldrexb *****
-; ASM: ldrexb r1, [r2]
-; DIS: 24: e1d21f9f
-; IASM: .byte 0x9f
-; IASM-NEXT: .byte 0x1f
-; IASM-NEXT: .byte 0xd2
-; IASM-NEXT: .byte 0xe1
-
-; ***** Example of strexb *****
-; ASM: strexb r4, r3, [r2]
-; DIS: 2c: e1c24f93
-; IASM: .byte 0x93
-; IASM-NEXT: .byte 0x4f
-; IASM-NEXT: .byte 0xc2
-; IASM-NEXT: .byte 0xe1
-
- %retval = zext i8 %v to i32
- ret i32 %retval
-}
-
-define internal i32 @testI16Form(i32 %ptr, i32 %a) {
-; ASM-LABEL:testI16Form:
-; DIS-LABEL:<testI16Form>:
-; IASM-LABEL:testI16Form:
-
-entry:
- %ptr.asptr = inttoptr i32 %ptr to i16*
- %a.arg_trunc = trunc i32 %a to i16
-
- %v = call i16 @llvm.nacl.atomic.rmw.i16(i32 1, i16* %ptr.asptr,
- i16 %a.arg_trunc, i32 6)
-; ***** Example of ldrexh *****
-; ASM: ldrexh r1, [r2]
-; DIS: 84: e1f21f9f
-; IASM: .byte 0x9f
-; IASM-NEXT: .byte 0x1f
-; IASM-NEXT: .byte 0xf2
-; IASM-NEXT: .byte 0xe1
-
-; ***** Example of strexh *****
-; ASM: strexh r4, r3, [r2]
-; DIS: 8c: e1e24f93
-; IASM: .byte 0x93
-; IASM-NEXT: .byte 0x4f
-; IASM-NEXT: .byte 0xe2
-; IASM-NEXT: .byte 0xe1
-
- %retval = zext i16 %v to i32
- ret i32 %retval
-}
-
-define internal i32 @testI32Form(i32 %ptr, i32 %a) {
-; ASM-LABEL:testI32Form:
-; DIS-LABEL:<testI32Form>:
-; IASM-LABEL:testI32Form:
-
-entry:
- %ptr.asptr = inttoptr i32 %ptr to i32*
- %v = call i32 @llvm.nacl.atomic.rmw.i32(i32 1, i32* %ptr.asptr,
- i32 %a, i32 6)
-
-; ***** Example of ldrex *****
-; ASM: ldrex r1, [r2]
-; DIS: dc: e1921f9f
-; IASM: .byte 0x9f
-; IASM-NEXT: .byte 0x1f
-; IASM-NEXT: .byte 0x92
-; IASM-NEXT: .byte 0xe1
-
-; ***** Example of strex *****
-; ASM: strex r4, r3, [r2]
-; DIS: e4: e1824f93
-; IASM: .byte 0x93
-; IASM-NEXT: .byte 0x4f
-; IASM-NEXT: .byte 0x82
-; IASM-NEXT: .byte 0xe1
-
- ret i32 %v
-}
-
-define internal i64 @testI64Form(i32 %ptr, i64 %a) {
-; ASM-LABEL:testI64Form:
-; DIS-LABEL:<testI64Form>:
-; IASM-LABEL:testI64Form:
-
-entry:
- %ptr.asptr = inttoptr i32 %ptr to i64*
- %v = call i64 @llvm.nacl.atomic.rmw.i64(i32 1, i64* %ptr.asptr,
- i64 %a, i32 6)
-
-; ***** Example of ldrexd *****
-; ASM: ldrexd r4, r5, [r6]
-; DIS: 13c: e1b64f9f
-; IASM: .byte 0x9f
-; IASM-NEXT: .byte 0x4f
-; IASM-NEXT: .byte 0xb6
-; IASM-NEXT: .byte 0xe1
-
-; ***** Example of strexd *****
-; ASM: strexd r4, r0, r1, [r6]
-; DIS: 158: e1a64f90
-; IASM: .byte 0x90
-; IASM-NEXT: .byte 0x4f
-; IASM-NEXT: .byte 0xa6
-; IASM-NEXT: .byte 0xe1
-
- ret i64 %v
-}
diff --git a/third_party/subzero/tests_lit/assembler/arm32/load-store.ll b/third_party/subzero/tests_lit/assembler/arm32/load-store.ll
deleted file mode 100644
index 9f80f69..0000000
--- a/third_party/subzero/tests_lit/assembler/arm32/load-store.ll
+++ /dev/null
@@ -1,86 +0,0 @@
-; Show that we can handle variable (i.e. stack) spills.
-
-; REQUIRES: allow_dump
-
-; Compile using standalone assembler.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -Om1 \
-; RUN: | FileCheck %s --check-prefix=ASM
-
-; Show bytes in assembled standalone code.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -Om1 | FileCheck %s --check-prefix=DIS
-
-; Compile using integrated assembler.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -Om1 \
-; RUN: | FileCheck %s --check-prefix=IASM
-
-; Show bytes in assembled integrated code.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -Om1 | FileCheck %s --check-prefix=DIS
-
-define internal i32 @add1ToR0(i32 %p) {
- %v = add i32 %p, 1
- ret i32 %v
-}
-
-; ASM-LABEL: add1ToR0:
-; IASM-LABEL: add1ToR0:
-; DIS-LABEL:00000000 <add1ToR0>:
-
-; ASM: sub sp, sp, #8
-; DIS-NEXT: 0: e24dd008
-; IASM: .byte 0x8
-; IASM-NEXT: .byte 0xd0
-; IASM-NEXT: .byte 0x4d
-; IASM-NEXT: .byte 0xe2
-
-; ASM-NEXT: str r0, [sp, #4]
-; ASM-NEXT: # [sp, #4] = def.pseudo
-; DIS-NEXT: 4: e58d0004
-; IASM-NEXT: .byte 0x4
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x8d
-; IASM-NEXT: .byte 0xe5
-
-; ASM-NEXT: ldr r0, [sp, #4]
-; DIS-NEXT: 8: e59d0004
-; IASM-NEXT: .byte 0x4
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x9d
-; IASM-NEXT: .byte 0xe5
-
-; ASM-NEXT: add r0, r0, #1
-; DIS-NEXT: c: e2800001
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x80
-; IASM-NEXT: .byte 0xe2
-
-; ASM-NEXT: str r0, [sp]
-; ASM-NEXT: # [sp] = def.pseudo
-; DIS-NEXT: 10: e58d0000
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x8d
-; IASM-NEXT: .byte 0xe5
-
-; ASM-NEXT: ldr r0, [sp]
-; DIS-NEXT: 14: e59d0000
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x9d
-; IASM-NEXT: .byte 0xe5
-
-; ASM-NEXT: add sp, sp, #8
-; DIS-NEXT: 18: e28dd008
-; IASM-NEXT: .byte 0x8
-; IASM-NEXT: .byte 0xd0
-; IASM-NEXT: .byte 0x8d
-; IASM-NEXT: .byte 0xe2
-
-; ASM-NEXT: bx lr
-; DIS-NEXT: 1c: e12fff1e
-; IASM-NEXT: .byte 0x1e
-; IASM-NEXT: .byte 0xff
-; IASM-NEXT: .byte 0x2f
-; IASM-NEXT: .byte 0xe1
diff --git a/third_party/subzero/tests_lit/assembler/arm32/lsl.ll b/third_party/subzero/tests_lit/assembler/arm32/lsl.ll
deleted file mode 100644
index 35e65c4..0000000
--- a/third_party/subzero/tests_lit/assembler/arm32/lsl.ll
+++ /dev/null
@@ -1,103 +0,0 @@
-; Show that we know how to translate lsl.
-
-; NOTE: We use -O2 to get rid of memory stores.
-
-; REQUIRES: allow_dump
-
-; Compile using standalone assembler.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -O2 \
-; RUN: | FileCheck %s --check-prefix=ASM
-
-; Show bytes in assembled standalone code.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -O2 | FileCheck %s --check-prefix=DIS
-
-; Compile using integrated assembler.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -O2 \
-; RUN: | FileCheck %s --check-prefix=IASM
-
-; Show bytes in assembled integrated code.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -O2 | FileCheck %s --check-prefix=DIS
-
-define internal i32 @ShlAmt(i32 %a) {
-; ASM-LABEL:ShlAmt:
-; DIS-LABEL:00000000 <ShlAmt>:
-; IASM-LABEL:ShlAmt:
-
-entry:
-; ASM-NEXT:.LShlAmt$entry:
-; IASM-NEXT:.LShlAmt$entry:
-
- %shl = shl i32 %a, 23
-
-; ASM-NEXT: lsl r0, r0, #23
-; DIS-NEXT: 0: e1a00b80
-; IASM-NOT: lsl
-
- ret i32 %shl
-}
-
-define internal i32 @ShlReg(i32 %a, i32 %b) {
-; ASM-LABEL:ShlReg:
-; DIS-LABEL:00000010 <ShlReg>:
-; IASM-LABEL:ShlReg:
-
-entry:
-; ASM-NEXT:.LShlReg$entry:
-; IASM-NEXT:.LShlReg$entry:
-
- %shl = shl i32 %a, %b
-
-; ASM-NEXT: lsl r0, r0, r1
-; DIS-NEXT: 10: e1a00110
-; IASM-NOT: lsl
-
- ret i32 %shl
-}
-
-define internal <4 x i32> @ShlVec(<4 x i32> %a, <4 x i32> %b) {
-; ASM-LABEL:ShlVec:
-; DIS-LABEL:00000020 <ShlVec>:
-; IASM-LABEL:ShlVec:
-
-entry:
-; ASM-NEXT:.LShlVec$entry:
-; IASM-NEXT:.LShlVec$entry:
-
- %shl = shl <4 x i32> %a, %b
-
-; ASM: vshl.u32 q0, q0, q1
-; DIS: 20: f3220440
-; IASM-NOT: vshl
-
- ret <4 x i32> %shl
-}
-
-define internal <8 x i16> @ShlVeci16(<8 x i16> %a, <8 x i16> %b) {
-; ASM-LABEL:ShlVeci16:
-
-entry:
-
- %v = shl <8 x i16> %a, %b
-
-; ASM: vshl.u16 q0, q0, q1
-; DIS: 30: f3120440
-; IASM-NOT: vshl
-
- ret <8 x i16> %v
-}
-
-define internal <16 x i8> @ShlVeci8(<16 x i8> %a, <16 x i8> %b) {
-; ASM-LABEL:ShlVeci8:
-
-entry:
-
- %v = shl <16 x i8> %a, %b
-
-; ASM: vshl.u8 q0, q0, q1
-; DIS: 40: f3020440
-; IASM-NOT: vshl
-
- ret <16 x i8> %v
-}
diff --git a/third_party/subzero/tests_lit/assembler/arm32/lsr.ll b/third_party/subzero/tests_lit/assembler/arm32/lsr.ll
deleted file mode 100644
index 193d0aa..0000000
--- a/third_party/subzero/tests_lit/assembler/arm32/lsr.ll
+++ /dev/null
@@ -1,112 +0,0 @@
-; Show that we know how to translate lsr.
-
-; NOTE: We use -O2 to get rid of memory stores.
-
-; REQUIRES: allow_dump
-
-; Compile using standalone assembler.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -O2 \
-; RUN: | FileCheck %s --check-prefix=ASM
-
-; Show bytes in assembled standalone code.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -O2 | FileCheck %s --check-prefix=DIS
-
-; Compile using integrated assembler.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -O2 \
-; RUN: | FileCheck %s --check-prefix=IASM
-
-; Show bytes in assembled integrated code.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -O2 | FileCheck %s --check-prefix=DIS
-
-define internal i32 @LshrAmt(i32 %a) {
-; ASM-LABEL:LshrAmt:
-; DIS-LABEL:00000000 <LshrAmt>:
-; IASM-LABEL:LshrAmt:
-
-entry:
-; ASM-NEXT:.LLshrAmt$entry:
-; IASM-NEXT:.LLshrAmt$entry:
-
- %v = lshr i32 %a, 23
-
-; ASM-NEXT: lsr r0, r0, #23
-; DIS-NEXT: 0: e1a00ba0
-; IASM-NOT: lsr
-
- ret i32 %v
-}
-
-define internal i32 @LshrReg(i32 %a, i32 %b) {
-; ASM-LABEL:LshrReg:
-; DIS-LABEL:00000010 <LshrReg>:
-; IASM-LABEL:LshrReg:
-
-entry:
-; ASM-NEXT:.LLshrReg$entry:
-; IASM-NEXT:.LLshrReg$entry:
-
- %v = lshr i32 %a, %b
-
-; ASM-NEXT: lsr r0, r0, r1
-; DIS-NEXT: 10: e1a00130
-; IASM-NOT: lsr
-
- ret i32 %v
-}
-
-define internal <4 x i32> @LshrVec(<4 x i32> %a, <4 x i32> %b) {
-; ASM-LABEL:LshrVec:
-; DIS-LABEL:00000020 <LshrVec>:
-; IASM-LABEL:LshrVec:
-
-entry:
-; ASM-NEXT:.LLshrVec$entry:
-; IASM-NEXT:.LLshrVec$entry:
-
- %v = lshr <4 x i32> %a, %b
-
-; ASM: vneg.s32 q1, q1
-; ASM-NEXT: vshl.u32 q0, q0, q1
-; DIS: 20: f3b923c2
-; DIS: 24: f3220440
-; IASM-NOT: vneg
-; IASM-NOT: vshl
-
- ret <4 x i32> %v
-}
-
-define internal <8 x i16> @LshrVeci16(<8 x i16> %a, <8 x i16> %b) {
-; ASM-LABEL:LshrVeci16:
-
-entry:
-
- %v = lshr <8 x i16> %a, %b
-
-; ASM: vneg.s16 q1, q1
-; ASM-NEXT: vshl.u16 q0, q0, q1
-; DIS: 30: f3b523c2
-; DIS: 34: f3120440
-; IASM-NOT: vneg
-; IASM-NOT: vshl
-
- ret <8 x i16> %v
-}
-
-define internal <16 x i8> @LshrVeci8(<16 x i8> %a, <16 x i8> %b) {
-; ASM-LABEL:LshrVeci8:
-
-entry:
-
- %v = lshr <16 x i8> %a, %b
-
-; ASM: vneg.s8 q1, q1
-; ASM-NEXT: vshl.u8 q0, q0, q1
-; DIS: 40: f3b123c2
-; DIS: 44: f3020440
-; IASM-NOT: vneg
-; IASM-NOT: vshl
-
- ret <16 x i8> %v
-}
diff --git a/third_party/subzero/tests_lit/assembler/arm32/mls.ll b/third_party/subzero/tests_lit/assembler/arm32/mls.ll
deleted file mode 100644
index c9ded32..0000000
--- a/third_party/subzero/tests_lit/assembler/arm32/mls.ll
+++ /dev/null
@@ -1,115 +0,0 @@
-; Show that we know how to translate mls.
-
-; REQUIRES: allow_dump
-
-; Compile using standalone assembler.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -Om1 --mattr=hwdiv-arm \
-; RUN: | FileCheck %s --check-prefix=ASM
-
-; Show bytes in assembled standalone code.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -Om1 --mattr=hwdiv-arm | FileCheck %s --check-prefix=DIS
-
-; Compile using integrated assembler.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -Om1 --mattr=hwdiv-arm \
-; RUN: | FileCheck %s --check-prefix=IASM
-
-; Show bytes in assembled integrated code.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -Om1 --mattr=hwdiv-arm | FileCheck %s --check-prefix=DIS
-
-define internal i32 @testMls(i32 %a, i32 %b) {
-; ASM-LABEL: testMls:
-; DIS-LABEL: 00000000 <testMls>:
-; IASM-LABEL: testMls:
-
-entry:
-; ASM-NEXT: .LtestMls$entry:
-; IASM-NEXT: .LtestMls$entry:
-
-; ASM-NEXT: sub sp, sp, #12
-; DIS-NEXT: 0: e24dd00c
-; IASM-NEXT: .byte 0xc
-; IASM-NEXT: .byte 0xd0
-; IASM-NEXT: .byte 0x4d
-; IASM-NEXT: .byte 0xe2
-
-; ASM-NEXT: str r0, [sp, #8]
-; ASM-NEXT: # [sp, #8] = def.pseudo
-; DIS-NEXT: 4: e58d0008
-; IASM-NEXT: .byte 0x8
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x8d
-; IASM-NEXT: .byte 0xe5
-
-; ASM-NEXT: str r1, [sp, #4]
-; ASM-NEXT: # [sp, #4] = def.pseudo
-; DIS-NEXT: 8: e58d1004
-; IASM-NEXT: .byte 0x4
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0x8d
-; IASM-NEXT: .byte 0xe5
-
- %rem = srem i32 %a, %b
-
-; ASM-NEXT: ldr r0, [sp, #8]
-; DIS-NEXT: c: e59d0008
-; IASM-NEXT: .byte 0x8
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x9d
-; IASM-NEXT: .byte 0xe5
-
-; ASM-NEXT: ldr r1, [sp, #4]
-; DIS-NEXT: 10: e59d1004
-; IASM-NEXT: .byte 0x4
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0x9d
-; IASM-NEXT: .byte 0xe5
-
-; ASM-NEXT: tst r1, r1
-; DIS-NEXT: 14: e1110001
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x11
-; IASM-NEXT: .byte 0xe1
-
-; ASM-NEXT: bne .LtestMls$local$__0
-; DIS-NEXT: 18: 1a000000
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x1a
-
-; ASM-NEXT: .long 0xe7fedef0
-; DIS-NEXT: 1c: e7fedef0
-; IASM-NEXT: .byte 0xf0
-; IASM-NEXT: .byte 0xde
-; IASM-NEXT: .byte 0xfe
-; IASM-NEXT: .byte 0xe7
-
-; ASM-NEXT: .LtestMls$local$__0:
-; IASM-NEXT: .LtestMls$local$__0:
-
-; ASM-NEXT: ldr r1, [sp, #4]
-; DIS-NEXT: 20: e59d1004
-; IASM-NEXT: .byte 0x4
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0x9d
-; IASM-NEXT: .byte 0xe5
-
-; ASM-NEXT: sdiv r2, r0, r1
-; DIS-NEXT: 24: e712f110
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0xf1
-; IASM-NEXT: .byte 0x12
-; IASM-NEXT: .byte 0xe7
-
-; ASM-NEXT: mls r0, r2, r1, r0
-; DIS-NEXT: 28: e0600192
-; IASM-NEXT: .byte 0x92
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x60
-; IASM-NEXT: .byte 0xe0
-
- ret i32 %rem
-}
diff --git a/third_party/subzero/tests_lit/assembler/arm32/mov-const.ll b/third_party/subzero/tests_lit/assembler/arm32/mov-const.ll
deleted file mode 100644
index c5ccbdc..0000000
--- a/third_party/subzero/tests_lit/assembler/arm32/mov-const.ll
+++ /dev/null
@@ -1,204 +0,0 @@
-; Show that we handle constants in movw and mvt, when it isn't represented as
-; ConstantRelocatable (see mov-imm.ll for the ConstantRelocatable case).
-
-; REQUIRES: allow_dump
-
-; Compile using standalone assembler.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -Om1 \
-; RUN: --test-stack-extra 4084 | FileCheck %s --check-prefix=ASM
-
-; Show bytes in assembled standalone code.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -Om1 --test-stack-extra 4084 | FileCheck %s --check-prefix=DIS
-
-; Compile using integrated assembler.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -Om1 \
-; RUN: --test-stack-extra 4084 | FileCheck %s --check-prefix=IASM
-
-; Show bytes in assembled integrated code.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -Om1 --test-stack-extra 4084 \
-; RUN: | FileCheck %s --check-prefix=DIS
-
-define internal i32 @foo(i32 %x) {
-entry:
-
-; ASM-LABEL: foo:
-; DIS-LABEL: 00000000 <foo>:
-; IASM-LABEL: foo:
-
-; ASM-NEXT: .Lfoo$entry:
-; IASM-NEXT: .Lfoo$entry:
-
-; ASM-NEXT: movw ip, #4092
-; DIS-NEXT: 0: e300cffc
-; IASM-NEXT: .byte 0xfc
-; IASM-NEXT: .byte 0xcf
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xe3
-
-; ASM-NEXT: sub sp, sp, ip
-; DIS-NEXT: 4: e04dd00c
-; IASM-NEXT: .byte 0xc
-; IASM-NEXT: .byte 0xd0
-; IASM-NEXT: .byte 0x4d
-; IASM-NEXT: .byte 0xe0
-
-; ASM-NEXT: str r0, [sp, #4088]
-; DIS-NEXT: 8: e58d0ff8
-; IASM-NEXT: .byte 0xf8
-; IASM-NEXT: .byte 0xf
-; IASM-NEXT: .byte 0x8d
-; IASM-NEXT: .byte 0xe5
-
-; ASM-NEXT: # [sp, #4088] = def.pseudo
-
- %mul = mul i32 %x, %x
-
-; ASM-NEXT: ldr r0, [sp, #4088]
-; DIS-NEXT: c: e59d0ff8
-; IASM-NEXT: .byte 0xf8
-; IASM-NEXT: .byte 0xf
-; IASM-NEXT: .byte 0x9d
-; IASM-NEXT: .byte 0xe5
-
-; ASM-NEXT: ldr r1, [sp, #4088]
-; DIS-NEXT: 10: e59d1ff8
-; IASM-NEXT: .byte 0xf8
-; IASM-NEXT: .byte 0x1f
-; IASM-NEXT: .byte 0x9d
-; IASM-NEXT: .byte 0xe5
-
-; ASM-NEXT: mul r0, r0, r1
-; DIS-NEXT: 14: e0000190
-; IASM-NEXT: .byte 0x90
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xe0
-
-; ASM-NEXT: str r0, [sp, #4084]
-; DIS-NEXT: 18: e58d0ff4
-; IASM-NEXT: .byte 0xf4
-; IASM-NEXT: .byte 0xf
-; IASM-NEXT: .byte 0x8d
-; IASM-NEXT: .byte 0xe5
-
-; ASM-NEXT: # [sp, #4084] = def.pseudo
-
- ret i32 %mul
-
-; ASM-NEXT: ldr r0, [sp, #4084]
-; DIS-NEXT: 1c: e59d0ff4
-; IASM-NEXT: .byte 0xf4
-; IASM-NEXT: .byte 0xf
-; IASM-NEXT: .byte 0x9d
-; IASM-NEXT: .byte 0xe5
-
-; ASM-NEXT: movw ip, #4092
-; DIS-NEXT: 20: e300cffc
-; IASM-NEXT: .byte 0xfc
-; IASM-NEXT: .byte 0xcf
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xe3
-
-; ASM-NEXT: add sp, sp, ip
-; DIS-NEXT: 24: e08dd00c
-; IASM-NEXT: .byte 0xc
-; IASM-NEXT: .byte 0xd0
-; IASM-NEXT: .byte 0x8d
-; IASM-NEXT: .byte 0xe0
-
-; ASM-NEXT: bx lr
-; DIS-NEXT: 28: e12fff1e
-; IASM-NEXT: .byte 0x1e
-; IASM-NEXT: .byte 0xff
-; IASM-NEXT: .byte 0x2f
-; IASM-NEXT: .byte 0xe1
-
-}
-
-define internal void @saveConstI32(i32 %loc) {
-; ASM-LABEL:saveConstI32:
-; DIS-LABEL:00000030 <saveConstI32>:
-; IASM-LABEL:saveConstI32:
-
-entry:
-; ASM-NEXT:.LsaveConstI32$entry:
-; IASM-NEXT:.LsaveConstI32$entry:
-
-; ASM-NEXT: movw ip, #4088
-; DIS-NEXT: 30: e300cff8
-; IASM-NEXT: .byte 0xf8
-; IASM-NEXT: .byte 0xcf
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xe3
-
-; ASM-NEXT: sub sp, sp, ip
-; DIS-NEXT: 34: e04dd00c
-; IASM-NEXT: .byte 0xc
-; IASM-NEXT: .byte 0xd0
-; IASM-NEXT: .byte 0x4d
-; IASM-NEXT: .byte 0xe0
-
-; ASM-NEXT: str r0, [sp, #4084]
-; ASM-NEXT: # [sp, #4084] = def.pseudo
-; DIS-NEXT: 38: e58d0ff4
-; IASM-NEXT: .byte 0xf4
-; IASM-NEXT: .byte 0xf
-; IASM-NEXT: .byte 0x8d
-; IASM-NEXT: .byte 0xe5
-
- %loc.asptr = inttoptr i32 %loc to i32*
- store i32 524289, i32* %loc.asptr, align 1
-
-; ASM-NEXT: ldr r0, [sp, #4084]
-; DIS-NEXT: 3c: e59d0ff4
-; IASM-NEXT: .byte 0xf4
-; IASM-NEXT: .byte 0xf
-; IASM-NEXT: .byte 0x9d
-; IASM-NEXT: .byte 0xe5
-
-; ASM-NEXT: movw r1, #1
-; DIS-NEXT: 40: e3001001
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xe3
-
-; ASM-NEXT: movt r1, #8
-; DIS-NEXT: 44: e3401008
-; IASM-NEXT: .byte 0x8
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0x40
-; IASM-NEXT: .byte 0xe3
-
-; ASM-NEXT: str r1, [r0]
-; DIS-NEXT: 48: e5801000
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0x80
-; IASM-NEXT: .byte 0xe5
-
- ret void
-
-; ASM-NEXT: movw ip, #4088
-; DIS-NEXT: 4c: e300cff8
-; IASM-NEXT: .byte 0xf8
-; IASM-NEXT: .byte 0xcf
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xe3
-
-; ASM-NEXT: add sp, sp, ip
-; DIS-NEXT: 50: e08dd00c
-; IASM-NEXT: .byte 0xc
-; IASM-NEXT: .byte 0xd0
-; IASM-NEXT: .byte 0x8d
-; IASM-NEXT: .byte 0xe0
-
-; ASM-NEXT: bx lr
-; DIS-NEXT: 54: e12fff1e
-; IASM-NEXT: .byte 0x1e
-; IASM-NEXT: .byte 0xff
-; IASM-NEXT: .byte 0x2f
-; IASM-NEXT: .byte 0xe1
-}
diff --git a/third_party/subzero/tests_lit/assembler/arm32/mov-imm.ll b/third_party/subzero/tests_lit/assembler/arm32/mov-imm.ll
deleted file mode 100644
index f307701..0000000
--- a/third_party/subzero/tests_lit/assembler/arm32/mov-imm.ll
+++ /dev/null
@@ -1,308 +0,0 @@
-; Show that we know how to translate move (immediate) ARM instruction.
-
-; REQUIRES: allow_dump
-
-; Compile using standalone assembler.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -O2 \
-; RUN: | FileCheck %s --check-prefix=ASM
-
-; Show bytes in assembled standalone code.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -O2 | FileCheck %s --check-prefix=DIS
-
-; Compile using integrated assembler.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -O2 \
-; RUN: | FileCheck %s --check-prefix=IASM
-
-; Show bytes in assembled integrated code.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -O2 | FileCheck %s --check-prefix=DIS
-
-define internal i32 @Imm1() {
- ret i32 1
-}
-
-; ASM-LABEL: Imm1:
-; ASM: mov r0, #1
-
-; DIS-LABEL:00000000 <Imm1>:
-; DIS-NEXT: 0: e3a00001
-
-; IASM-LABEL: Imm1:
-; IASM: .byte 0x1
-; IASM: .byte 0x0
-; IASM: .byte 0xa0
-; IASM: .byte 0xe3
-
-
-define internal i32 @rotateFImmAA() {
- ; immediate = 0x000002a8 = b 0000 0000 0000 0000 0000 0010 1010 1000
- ret i32 680
-}
-
-; ASM-LABEL: rotateFImmAA:
-; ASM: mov r0, #680
-
-; DIS-LABEL:00000010 <rotateFImmAA>:
-; DIS-NEXT: 10: e3a00faa
-
-; IASM-LABEL: rotateFImmAA:
-; IASM: .byte 0xaa
-; IASM: .byte 0xf
-; IASM: .byte 0xa0
-; IASM: .byte 0xe3
-
-define internal i32 @rotateEImmAA() {
- ; immediate = 0x00000aa0 = b 0000 0000 0000 0000 0000 1010 1010 0000
- ret i32 2720
-}
-
-; ASM-LABEL: rotateEImmAA:
-; ASM: mov r0, #2720
-
-; DIS-LABEL:00000020 <rotateEImmAA>:
-; DIS-NEXT: 20: e3a00eaa
-
-; IASM-LABEL: rotateEImmAA:
-; IASM: .byte 0xaa
-; IASM: .byte 0xe
-; IASM: .byte 0xa0
-; IASM: .byte 0xe3
-
-define internal i32 @rotateDImmAA() {
- ; immediate = 0x00002a80 = b 0000 0000 0000 0000 0010 1010 1000 0000
- ret i32 10880
-}
-
-; ASM-LABEL: rotateDImmAA:
-; ASM: mov r0, #10880
-
-; DIS-LABEL:00000030 <rotateDImmAA>:
-; DIS-NEXT: 30: e3a00daa
-
-; IASM-LABEL: rotateDImmAA:
-; IASM: .byte 0xaa
-; IASM: .byte 0xd
-; IASM: .byte 0xa0
-; IASM: .byte 0xe3
-
-define internal i32 @rotateCImmAA() {
- ; immediate = 0x0000aa00 = b 0000 0000 0000 0000 1010 1010 0000 0000
- ret i32 43520
-}
-
-; ASM-LABEL: rotateCImmAA:
-; ASM: mov r0, #43520
-
-; DIS-LABEL:00000040 <rotateCImmAA>:
-; DIS-NEXT: 40: e3a00caa
-
-; IASM-LABEL: rotateCImmAA:
-; IASM: .byte 0xaa
-; IASM: .byte 0xc
-; IASM: .byte 0xa0
-; IASM: .byte 0xe3
-
-define internal i32 @rotateBImmAA() {
- ; immediate = 0x0002a800 = b 0000 0000 0000 0010 1010 1000 0000 0000
- ret i32 174080
-}
-
-; ASM-LABEL: rotateBImmAA:
-; ASM: mov r0, #174080
-
-; DIS-LABEL:00000050 <rotateBImmAA>:
-; DIS-NEXT: 50: e3a00baa
-
-; IASM-LABEL: rotateBImmAA:
-; IASM: .byte 0xaa
-; IASM: .byte 0xb
-; IASM: .byte 0xa0
-; IASM: .byte 0xe3
-
-define internal i32 @rotateAImmAA() {
- ; immediate = 0x000aa000 = b 0000 0000 0000 1010 1010 0000 0000 0000
- ret i32 696320
-}
-
-; ASM-LABEL: rotateAImmAA:
-; ASM: mov r0, #696320
-
-; DIS-LABEL:00000060 <rotateAImmAA>:
-; DIS-NEXT: 60: e3a00aaa
-
-; IASM-LABEL: rotateAImmAA:
-; IASM: .byte 0xaa
-; IASM: .byte 0xa
-; IASM: .byte 0xa0
-; IASM: .byte 0xe3
-
-define internal i32 @rotate9ImmAA() {
- ; immediate = 0x002a8000 = b 0000 0000 0010 1010 1000 0000 0000 0000
- ret i32 2785280
-}
-
-; ASM-LABEL: rotate9ImmAA:
-; ASM: mov r0, #2785280
-
-; DIS-LABEL:00000070 <rotate9ImmAA>:
-; DIS-NEXT: 70: e3a009aa
-
-; IASM-LABEL: rotate9ImmAA:
-; IASM: .byte 0xaa
-; IASM: .byte 0x9
-; IASM: .byte 0xa0
-; IASM: .byte 0xe3
-
-define internal i32 @rotate8ImmAA() {
- ; immediate = 0x00aa0000 = b 0000 0000 1010 1010 0000 0000 0000 0000
- ret i32 11141120
-}
-
-; ASM-LABEL: rotate8ImmAA:
-; ASM: mov r0, #11141120
-
-; DIS-LABEL:00000080 <rotate8ImmAA>:
-; DIS-NEXT: 80: e3a008aa
-
-; IASM-LABEL: rotate8ImmAA:
-; IASM: .byte 0xaa
-; IASM: .byte 0x8
-; IASM: .byte 0xa0
-; IASM: .byte 0xe3
-
-define internal i32 @rotate7ImmAA() {
- ; immediate = 0x02a80000 = b 0000 0010 1010 1000 0000 0000 0000 0000
- ret i32 44564480
-}
-
-; ASM-LABEL: rotate7ImmAA:
-; ASM: mov r0, #44564480
-
-; DIS-LABEL:00000090 <rotate7ImmAA>:
-; DIS-NEXT: 90: e3a007aa
-
-; IASM-LABEL: rotate7ImmAA:
-; IASM: .byte 0xaa
-; IASM: .byte 0x7
-; IASM: .byte 0xa0
-; IASM: .byte 0xe3
-
-define internal i32 @rotate6ImmAA() {
- ; immediate = 0x0aa00000 = b 0000 1010 1010 0000 0000 0000 0000 0000
- ret i32 178257920
-}
-
-; ASM-LABEL: rotate6ImmAA:
-; ASM: mov r0, #178257920
-
-; DIS-LABEL:000000a0 <rotate6ImmAA>:
-; DIS-NEXT: a0: e3a006aa
-
-; IASM-LABEL: rotate6ImmAA:
-; IASM: .byte 0xaa
-; IASM: .byte 0x6
-; IASM: .byte 0xa0
-; IASM: .byte 0xe3
-
-define internal i32 @rotate5ImmAA() {
- ; immediate = 0x2a800000 = b 0010 1010 1000 0000 0000 0000 0000 0000
- ret i32 713031680
-}
-
-; ASM-LABEL: rotate5ImmAA:
-; ASM: mov r0, #713031680
-
-; DIS-LABEL:000000b0 <rotate5ImmAA>:
-; DIS-NEXT: b0: e3a005aa
-
-; IASM-LABEL: rotate5ImmAA:
-; IASM: .byte 0xaa
-; IASM: .byte 0x5
-; IASM: .byte 0xa0
-; IASM: .byte 0xe3
-
-define internal i32 @rotate4ImmAA() {
- ; immediate = 0xaa000000 = b 1010 1010 0000 0000 0000 0000 0000 0000
- ret i32 2852126720
-}
-
-; ASM-LABEL: rotate4ImmAA:
-; ASM: mov r0, #2852126720
-
-; DIS-LABEL:000000c0 <rotate4ImmAA>:
-; DIS-NEXT: c0: e3a004aa
-
-; IASM-LABEL: rotate4ImmAA:
-; IASM: .byte 0xaa
-; IASM: .byte 0x4
-; IASM: .byte 0xa0
-; IASM: .byte 0xe3
-
-define internal i32 @rotate3ImmAA() {
- ; immediate = 0xa8000002 = b 1010 1000 0000 0000 0000 0000 0000 0010
- ret i32 2818572290
-}
-
-; ASM-LABEL: rotate3ImmAA:
-; ASM: mov r0, #2818572290
-
-; DIS-LABEL:000000d0 <rotate3ImmAA>:
-; DIS-NEXT: d0: e3a003aa
-
-; IASM-LABEL: rotate3ImmAA:
-; IASM: .byte 0xaa
-; IASM: .byte 0x3
-; IASM: .byte 0xa0
-; IASM: .byte 0xe3
-
-define internal i32 @rotate2ImmAA() {
- ; immediate = 0xa000000a = b 1010 0000 0000 0000 0000 0000 0000 1010
- ret i32 2684354570
-}
-
-; ASM-LABEL: rotate2ImmAA:
-; ASM: mov r0, #2684354570
-
-; DIS-LABEL:000000e0 <rotate2ImmAA>:
-; DIS-NEXT: e0: e3a002aa
-
-; IASM-LABEL: rotate2ImmAA:
-; IASM: .byte 0xaa
-; IASM: .byte 0x2
-; IASM: .byte 0xa0
-; IASM: .byte 0xe3
-
-define internal i32 @rotate1ImmAA() {
- ; immediate = 0x8000002a = b 1000 1000 0000 0000 0000 0000 0010 1010
- ret i32 2147483690
-}
-
-; ASM-LABEL: rotate1ImmAA:
-; ASM: mov r0, #2147483690
-
-; DIS-LABEL:000000f0 <rotate1ImmAA>:
-; DIS-NEXT: f0: e3a001aa
-
-; IASM-LABEL: rotate1ImmAA:
-; IASM: .byte 0xaa
-; IASM: .byte 0x1
-; IASM: .byte 0xa0
-; IASM: .byte 0xe3
-
-define internal i32 @rotate0ImmAA() {
- ; immediate = 0x000000aa = b 0000 0000 0000 0000 0000 0000 1010 1010
- ret i32 170
-}
-
-; ASM-LABEL: rotate0ImmAA:
-; ASM: mov r0, #170
-
-; DIS-LABEL:00000100 <rotate0ImmAA>:
-; DIS-NEXT: 100: e3a000aa
-
-; IASM-LABEL: rotate0ImmAA:
-; IASM: .byte 0xaa
-; IASM: .byte 0x0
-; IASM: .byte 0xa0
-; IASM: .byte 0xe3
diff --git a/third_party/subzero/tests_lit/assembler/arm32/mov-reg.ll b/third_party/subzero/tests_lit/assembler/arm32/mov-reg.ll
deleted file mode 100644
index fbfd897..0000000
--- a/third_party/subzero/tests_lit/assembler/arm32/mov-reg.ll
+++ /dev/null
@@ -1,54 +0,0 @@
-; Show that we know how to translate mov (shifted register), which
-; are pseudo instructions for ASR, LSR, ROR, and RRX.
-
-; NOTE: We use -O2 to get rid of memory stores.
-
-; REQUIRES: allow_dump
-
-; Compile using standalone assembler.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -O2 \
-; RUN: | FileCheck %s --check-prefix=ASM
-
-; Show bytes in assembled standalone code.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -O2 | FileCheck %s --check-prefix=DIS
-
-; Compile using integrated assembler.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -O2 \
-; RUN: | FileCheck %s --check-prefix=IASM
-
-; Show bytes in assembled integrated code.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -O2 | FileCheck %s --check-prefix=DIS
-
-define internal i64 @testMovWithAsr(i32 %a) {
-; ASM-LABEL:testMovWithAsr:
-; DIS-LABEL:00000000 <testMovWithAsr>:
-; IASM-LABEL:testMovWithAsr:
-
-entry:
-; ASM-NEXT:.LtestMovWithAsr$entry:
-; IASM-NEXT:.LtestMovWithAsr$entry:
-
- %a.arg_trunc = trunc i32 %a to i8
- %conv = sext i8 %a.arg_trunc to i64
- ret i64 %conv
-
-; ASM-NEXT: sxtb r0, r0
-; DIS-NEXT: 0: e6af0070
-; IASM-NEXT: .byte 0x70
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xaf
-; IASM-NEXT: .byte 0xe6
-
-; ***** Example of mov pseudo instruction.
-; ASM-NEXT: mov r1, r0, asr #31
-; DIS-NEXT: 4: e1a01fc0
-; IASM-NEXT: .byte 0xc0
-; IASM-NEXT: .byte 0x1f
-; IASM-NEXT: .byte 0xa0
-; IASM-NEXT: .byte 0xe1
-
-; ASM-NEXT: bx lr
-
-}
diff --git a/third_party/subzero/tests_lit/assembler/arm32/mul-vec.ll b/third_party/subzero/tests_lit/assembler/arm32/mul-vec.ll
deleted file mode 100644
index a009135..0000000
--- a/third_party/subzero/tests_lit/assembler/arm32/mul-vec.ll
+++ /dev/null
@@ -1,85 +0,0 @@
-; Show that we know how to translate vmul vector instructions.
-
-; REQUIRES: allow_dump
-
-; Compile using standalone assembler.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -O2 \
-; RUN: -reg-use q10,q11 \
-; RUN: | FileCheck %s --check-prefix=ASM
-
-; Show bytes in assembled standalone code.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -O2 \
-; RUN: -reg-use q10,q11 \
-; RUN: | FileCheck %s --check-prefix=DIS
-
-; Compile using integrated assembler.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -O2 \
-; RUN: -reg-use q10,q11 \
-; RUN: | FileCheck %s --check-prefix=IASM
-
-; Show bytes in assembled integrated code.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -O2 \
-; RUN: -reg-use q10,q11 \
-; RUN: | FileCheck %s --check-prefix=DIS
-
-define internal <4 x float> @testVmulFloat4(<4 x float> %v1, <4 x float> %v2) {
-; ASM-LABEL: testVmulFloat4:
-; DIS-LABEL: 00000000 <testVmulFloat4>:
-; IASM-LABEL: testVmulFloat4:
-
-entry:
- %res = fmul <4 x float> %v1, %v2
-
-; ASM: vmul.f32 q10, q10, q11
-; DIS: 8: f3444df6
-; IASM-NOT: vmul.f32
-
- ret <4 x float> %res
-}
-
-define internal <4 x i32> @testVmul4i32(<4 x i32> %v1, <4 x i32> %v2) {
-; ASM-LABEL: testVmul4i32:
-; DIS-LABEL: 00000020 <testVmul4i32>:
-; IASM-LABEL: testVmul4i32:
-
-entry:
- %res = mul <4 x i32> %v1, %v2
-
-; ASM: vmul.i32 q10, q10, q11
-; DIS: 28: f26449f6
-; IASM-NOT: vmul.i32
-
- ret <4 x i32> %res
-}
-
-define internal <8 x i16> @testVmul8i16(<8 x i16> %v1, <8 x i16> %v2) {
-; ASM-LABEL: testVmul8i16:
-; DIS-LABEL: 00000040 <testVmul8i16>:
-; IASM-LABEL: testVmul8i16:
-
-entry:
- %res = mul <8 x i16> %v1, %v2
-
-; ASM: vmul.i16 q10, q10, q11
-; DIS: 48: f25449f6
-; IASM-NOT: vmul.i16
-
- ret <8 x i16> %res
-}
-
-define internal <16 x i8> @testVmul16i8(<16 x i8> %v1, <16 x i8> %v2) {
-; ASM-LABEL: testVmul16i8:
-; DIS-LABEL: 00000060 <testVmul16i8>:
-; IASM-LABEL: testVmul16i8:
-
-entry:
- %res = mul <16 x i8> %v1, %v2
-
-; ASM: vmul.i8 q10, q10, q11
-; DIS: 68: f24449f6
-; IASM-NOT: vmul.i8
-
- ret <16 x i8> %res
-}
diff --git a/third_party/subzero/tests_lit/assembler/arm32/mul.ll b/third_party/subzero/tests_lit/assembler/arm32/mul.ll
deleted file mode 100644
index 5c8ffab..0000000
--- a/third_party/subzero/tests_lit/assembler/arm32/mul.ll
+++ /dev/null
@@ -1,60 +0,0 @@
-; Show that we know how to translate mul.
-
-; NOTE: We use -O2 to get rid of memory stores.
-
-; REQUIRES: allow_dump
-
-; Compile using standalone assembler.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -O2 \
-; RUN: | FileCheck %s --check-prefix=ASM
-
-; Show bytes in assembled standalone code.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -O2 | FileCheck %s --check-prefix=DIS
-
-; Compile using integrated assembler.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -O2 \
-; RUN: | FileCheck %s --check-prefix=IASM
-
-; Show bytes in assembled integrated code.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -O2 | FileCheck %s --check-prefix=DIS
-
-define internal i32 @MulTwoRegs(i32 %a, i32 %b) {
- %v = mul i32 %a, %b
- ret i32 %v
-}
-
-; ASM-LABEL:MulTwoRegs:
-; DIS-LABEL:<MulTwoRegs>:
-; IASM-LABEL:MulTwoRegs:
-
-; ASM: mul r0, r0, r1
-; DIS: e0000190
-; IASM-NOT: mul
-
-define internal i64 @MulTwoI64Regs(i64 %a, i64 %b) {
- %v = mul i64 %a, %b
- ret i64 %v
-}
-
-; ASM-LABEL:MulTwoI64Regs:
-; DIS-LABEL:<MulTwoI64Regs>:
-; IASM-LABEL:MulTwoI64Regs:
-
-; ASM: mul r3, r0, r3
-; ASM-NEXT: mla r1, r2, r1, r3
-; ASM-NEXT: # r3 = def.pseudo
-; ASM-NEXT: umull r0, r3, r0, r2
-; ASM-NEXT: # r3 = def.pseudo r0
-; ASM-NEXT: add r3, r3, r1
-
-; DIS: e0030390
-; DIS-NEXT: e0213192
-; DIS-NEXT: e0830290
-; DIS-NEXT: e0833001
-
-; IASM-NOT: mul
-; IASM-NOT: mla
-; IASM-NOT: umull
-; IASM-NOT: add
diff --git a/third_party/subzero/tests_lit/assembler/arm32/mvn.ll b/third_party/subzero/tests_lit/assembler/arm32/mvn.ll
deleted file mode 100644
index 70a2d0d..0000000
--- a/third_party/subzero/tests_lit/assembler/arm32/mvn.ll
+++ /dev/null
@@ -1,157 +0,0 @@
-; Tests MVN instruction.
-
-; REQUIRES: allow_dump
-
-; Compile using standalone assembler.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -Om1 \
-; RUN: | FileCheck %s --check-prefix=ASM
-
-; Show bytes in assembled standalone code.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -Om1 | FileCheck %s --check-prefix=DIS
-
-; Compile using integrated assembler.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -Om1 \
-; RUN: | FileCheck %s --check-prefix=IASM
-
-; Show bytes in assembled integrated code.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -Om1 | FileCheck %s --check-prefix=DIS
-
-define internal void @mvnEx(i32 %a, i32 %b) {
-; ASM-LABEL:mvnEx:
-; DIS-LABEL:00000000 <mvnEx>:
-; IASM-LABEL:mvnEx:
-
-entry:
-; ASM-NEXT:.LmvnEx$entry:
-; IASM-NEXT:.LmvnEx$entry:
-
-; ASM-NEXT: sub sp, sp, #24
-; DIS-NEXT: 0: e24dd018
-; IASM-NEXT: .byte 0x18
-; IASM-NEXT: .byte 0xd0
-; IASM-NEXT: .byte 0x4d
-; IASM-NEXT: .byte 0xe2
-
-; ASM-NEXT: str r0, [sp, #20]
-; ASM-NEXT: # [sp, #20] = def.pseudo
-; DIS-NEXT: 4: e58d0014
-; IASM-NEXT: .byte 0x14
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x8d
-; IASM-NEXT: .byte 0xe5
-
-; ASM-NEXT: str r1, [sp, #16]
-; ASM-NEXT: # [sp, #16] = def.pseudo
-; DIS-NEXT: 8: e58d1010
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0x8d
-; IASM-NEXT: .byte 0xe5
-
- %b.arg_trunc = trunc i32 %b to i1
-
-; ASM-NEXT: ldr r0, [sp, #16]
-; DIS-NEXT: c: e59d0010
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x9d
-; IASM-NEXT: .byte 0xe5
-
-; ASM-NEXT: and r0, r0, #1
-; DIS-NEXT: 10: e2000001
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xe2
-
-; ASM-NEXT: strb r0, [sp, #12]
-; ASM-NEXT: # [sp, #12] = def.pseudo
-; DIS-NEXT: 14: e5cd000c
-; IASM-NEXT: .byte 0xc
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xcd
-; IASM-NEXT: .byte 0xe5
-
- %a.arg_trunc = trunc i32 %a to i1
-
-; ASM-NEXT: ldr r0, [sp, #20]
-; DIS-NEXT: 18: e59d0014
-; IASM-NEXT: .byte 0x14
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x9d
-; IASM-NEXT: .byte 0xe5
-
-; ASM-NEXT: and r0, r0, #1
-; DIS-NEXT: 1c: e2000001
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xe2
-
-; ASM-NEXT: strb r0, [sp, #8]
-; ASM-NEXT: # [sp, #8] = def.pseudo
-; DIS-NEXT: 20: e5cd0008
-; IASM-NEXT: .byte 0x8
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xcd
-; IASM-NEXT: .byte 0xe5
-
- %conv = zext i1 %a.arg_trunc to i32
-
-; ASM-NEXT: ldrb r0, [sp, #8]
-; DIS-NEXT: 24: e5dd0008
-; IASM-NEXT: .byte 0x8
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xdd
-; IASM-NEXT: .byte 0xe5
-
-; ASM-NEXT: str r0, [sp, #4]
-; ASM-NEXT: # [sp, #4] = def.pseudo
-; DIS-NEXT: 28: e58d0004
-; IASM-NEXT: .byte 0x4
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x8d
-; IASM-NEXT: .byte 0xe5
-
- %ignore = sext i1 %b.arg_trunc to i32
-
-; ASM-NEXT: mov r0, #0
-; DIS-NEXT: 2c: e3a00000
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xa0
-; IASM-NEXT: .byte 0xe3
-
-; ASM-NEXT: ldrb r1, [sp, #12]
-; DIS-NEXT: 30: e5dd100c
-; IASM-NEXT: .byte 0xc
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0xdd
-; IASM-NEXT: .byte 0xe5
-
-; ASM-NEXT: tst r1, #1
-; DIS-NEXT: 34: e3110001
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x11
-; IASM-NEXT: .byte 0xe3
-
-; ********* Use of MVN ********
-; ASM-NEXT: mvn r1, #0
-; DIS-NEXT: 38: e3e01000
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0xe0
-; IASM-NEXT: .byte 0xe3
-
-; ASM-NEXT: movne r0, r1
-; DIS-NEXT: 3c: 11a00001
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xa0
-; IASM-NEXT: .byte 0x11
-
- ret void
-}
diff --git a/third_party/subzero/tests_lit/assembler/arm32/or-vec.ll b/third_party/subzero/tests_lit/assembler/arm32/or-vec.ll
deleted file mode 100644
index b6cf580..0000000
--- a/third_party/subzero/tests_lit/assembler/arm32/or-vec.ll
+++ /dev/null
@@ -1,115 +0,0 @@
-; Show that we know how to translate vorr vector instructions.
-
-; REQUIRES: allow_dump
-
-; Compile using standalone assembler.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -O2 \
-; RUN: | FileCheck %s --check-prefix=ASM
-
-; Show bytes in assembled standalone code.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -O2 \
-; RUN: | FileCheck %s --check-prefix=DIS
-
-; Compile using integrated assembler.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -O2 \
-; RUN: | FileCheck %s --check-prefix=IASM
-
-; Show bytes in assembled integrated code.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -O2 \
-; RUN: | FileCheck %s --check-prefix=DIS
-
-define internal <4 x i32> @testVor4i32(<4 x i32> %v1, <4 x i32> %v2) {
-; ASM-LABEL: testVor4i32:
-; DIS-LABEL: 00000000 <testVor4i32>:
-; IASM-LABEL: testVor4i32:
-
-entry:
- %res = or <4 x i32> %v1, %v2
-
-; ASM: vorr.i32 q0, q0, q1
-; DIS: 0: f2200152
-; IASM-NOT: vorr.i32
-
- ret <4 x i32> %res
-}
-
-define internal <8 x i16> @testVor8i16(<8 x i16> %v1, <8 x i16> %v2) {
-; ASM-LABEL: testVor8i16:
-; DIS-LABEL: 00000010 <testVor8i16>:
-; IASM-LABEL: testVor8i16:
-
-entry:
- %res = or <8 x i16> %v1, %v2
-
-; ASM: vorr.i16 q0, q0, q1
-; DIS: 10: f2200152
-; IASM-NOT: vorr.i16
-
- ret <8 x i16> %res
-}
-
-define internal <16 x i8> @testVor16i8(<16 x i8> %v1, <16 x i8> %v2) {
-; ASM-LABEL: testVor16i8:
-; DIS-LABEL: 00000020 <testVor16i8>:
-; IASM-LABEL: testVor16i8:
-
-entry:
- %res = or <16 x i8> %v1, %v2
-
-; ASM: vorr.i8 q0, q0, q1
-; DIS: 20: f2200152
-; IASM-NOT: vorr.i8
-
- ret <16 x i8> %res
-}
-
-;;
-;; The following tests make sure logical or works on predicate vectors.
-;;
-
-define internal <4 x i1> @testVor4i1(<4 x i1> %v1, <4 x i1> %v2) {
-; ASM-LABEL: testVor4i1:
-; DIS-LABEL: 00000030 <testVor4i1>:
-; IASM-LABEL: testVor4i1:
-
-entry:
- %res = or <4 x i1> %v1, %v2
-
-; ASM: vorr.i32 q0, q0, q1
-; DIS: 30: f2200152
-; IASM-NOT: vorr.i32
-
- ret <4 x i1> %res
-}
-
-define internal <8 x i1> @testVor8i1(<8 x i1> %v1, <8 x i1> %v2) {
-; ASM-LABEL: testVor8i1:
-; DIS-LABEL: 00000040 <testVor8i1>:
-; IASM-LABEL: testVor8i1:
-
-entry:
- %res = or <8 x i1> %v1, %v2
-
-; ASM: vorr.i16 q0, q0, q1
-; DIS: 40: f2200152
-; IASM-NOT: vorr.i16
-
- ret <8 x i1> %res
-}
-
-define internal <16 x i1> @testVor16i1(<16 x i1> %v1, <16 x i1> %v2) {
-; ASM-LABEL: testVor16i1:
-; DIS-LABEL: 00000050 <testVor16i1>:
-; IASM-LABEL: testVor16i1:
-
-entry:
- %res = or <16 x i1> %v1, %v2
-
-; ASM: vorr.i8 q0, q0, q1
-; DIS: 50: f2200152
-; IASM-NOT: vorr.i8
-
- ret <16 x i1> %res
-}
diff --git a/third_party/subzero/tests_lit/assembler/arm32/orr.ll b/third_party/subzero/tests_lit/assembler/arm32/orr.ll
deleted file mode 100644
index 480b99a..0000000
--- a/third_party/subzero/tests_lit/assembler/arm32/orr.ll
+++ /dev/null
@@ -1,110 +0,0 @@
-; Show that we know how to translate or.
-
-; NOTE: We use -O2 to get rid of memory stores.
-
-; REQUIRES: allow_dump
-
-; Compile using standalone assembler.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -O2 \
-; RUN: | FileCheck %s --check-prefix=ASM
-
-; Show bytes in assembled standalone code.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -O2 | FileCheck %s --check-prefix=DIS
-
-; Compile using integrated assembler.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -O2 \
-; RUN: | FileCheck %s --check-prefix=IASM
-
-; Show bytes in assembled integrated code.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -O2 | FileCheck %s --check-prefix=DIS
-
-define internal i32 @Or1WithR0(i32 %p) {
- %v = or i32 %p, 1
- ret i32 %v
-}
-
-; ASM-LABEL:Or1WithR0:
-; ASM-NEXT:.LOr1WithR0$__0:
-; ASM-NEXT: orr r0, r0, #1
-
-; DIS-LABEL:00000000 <Or1WithR0>:
-; DIS-NEXT: 0: e3800001
-
-; IASM-LABEL:Or1WithR0:
-; IASM-NEXT:.LOr1WithR0$__0:
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x80
-; IASM-NEXT: .byte 0xe3
-
-define internal i32 @Or2Regs(i32 %p1, i32 %p2) {
- %v = or i32 %p1, %p2
- ret i32 %v
-}
-
-; ASM-LABEL:Or2Regs:
-; ASM-NEXT:.LOr2Regs$__0:
-; ASM-NEXT: orr r0, r0, r1
-
-; DIS-LABEL:00000010 <Or2Regs>:
-; DIS-NEXT: 10: e1800001
-
-; IASM-LABEL:Or2Regs:
-; IASM-NEXT:.LOr2Regs$__0:
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x80
-; IASM-NEXT: .byte 0xe1
-
-define internal i64 @OrI64WithR0R1(i64 %p) {
- %v = or i64 %p, 1
- ret i64 %v
-}
-
-; ASM-LABEL:OrI64WithR0R1:
-; ASM-NEXT:.LOrI64WithR0R1$__0:
-; ASM-NEXT: orr r0, r0, #1
-; ASM-NEXT: orr r1, r1, #0
-
-; DIS-LABEL:00000020 <OrI64WithR0R1>:
-; DIS-NEXT: 20: e3800001
-; DIS-NEXT: 24: e3811000
-
-; IASM-LABEL:OrI64WithR0R1:
-; IASM-NEXT:.LOrI64WithR0R1$__0:
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x80
-; IASM-NEXT: .byte 0xe3
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0x81
-; IASM-NEXT: .byte 0xe3
-
-
-define internal i64 @OrI64Regs(i64 %p1, i64 %p2) {
- %v = or i64 %p1, %p2
- ret i64 %v
-}
-
-; ASM-LABEL:OrI64Regs:
-; ASM-NEXT:.LOrI64Regs$__0:
-; ASM-NEXT: orr r0, r0, r2
-; ASM-NEXT: orr r1, r1, r3
-
-; DIS-LABEL:00000030 <OrI64Regs>:
-; DIS-NEXT: 30: e1800002
-; DIS-NEXT: 34: e1811003
-
-; IASM-LABEL:OrI64Regs:
-; IASM-NEXT:.LOrI64Regs$__0:
-; IASM-NEXT: .byte 0x2
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x80
-; IASM-NEXT: .byte 0xe1
-; IASM-NEXT: .byte 0x3
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0x81
-; IASM-NEXT: .byte 0xe1
diff --git a/third_party/subzero/tests_lit/assembler/arm32/popmult.ll b/third_party/subzero/tests_lit/assembler/arm32/popmult.ll
deleted file mode 100644
index d7d1c45..0000000
--- a/third_party/subzero/tests_lit/assembler/arm32/popmult.ll
+++ /dev/null
@@ -1,70 +0,0 @@
-; Show that pops are generated in reverse order of pushes.
-
-; NOTE: Restricts to nonconsecutive S registers to force the generation of
-; multiple vpush/vpop instructions. Also tests that we generate them in the
-; right order (the reverse of the corresponding push). Uses -O2 to keep all
-; results in S registers.
-
-; REQUIRES: allow_dump
-
-; Compile using standalone assembler.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -O2 -allow-extern \
-; RUN: -reg-use s20,s22,s23 \
-; RUN: | FileCheck %s --check-prefix=ASM
-
-; Show bytes in assembled standalone code.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -O2 -allow-extern \
-; RUN: -reg-use s20,s22,s23 \
-; RUN: | FileCheck %s --check-prefix=DIS
-
-; Compile using integrated assembler.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -O2 -allow-extern \
-; RUN: -reg-use s20,s22,s23 \
-; RUN: | FileCheck %s --check-prefix=IASM
-
-; Show bytes in assembled integrated code.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -O2 -allow-extern \
-; RUN: -reg-use s20,s22,s23 \
-; RUN: | FileCheck %s --check-prefix=DIS
-
-declare external void @f()
-
-define internal float @test2SPops(float %p1, float %p2) {
-; ASM-LABEL: test2SPops:
-; DIS-LABEL: 00000000 <test2SPops>:
-; IASM-LABEL: test2SPops:
-
-; ASM: vpush {s20}
-; ASM-NEXT: vpush {s22, s23}
-; ASM-NEXT: push {lr}
-
-; DIS: 0: ed2daa01
-; DIS-NEXT: 4: ed2dba02
-; DIS-NEXT: 8: e52de004
-
-; IASM-NOT: vpush
-; IASM-NOT: push
-
- %v1 = fadd float %p1, %p2
- %v2 = fsub float %p1, %p2
- %v3 = fsub float %p2, %p1
- call void @f()
- %v4 = fadd float %v1, %v2
- %res = fadd float %v3, %v4
-
-; ASM: pop {lr}
-; ASM-NEXT: # lr = def.pseudo
-; ASM-NEXT: vpop {s22, s23}
-; ASM-NEXT: vpop {s20}
-
-; DIS: 40: e49de004
-; DIS-NEXT: 44: ecbdba02
-; DIS-NEXT: 48: ecbdaa01
-
-; IASM-NOT: pop
-; IASM-NOT: vpop
-
- ret float %res
-}
diff --git a/third_party/subzero/tests_lit/assembler/arm32/push-pop.ll b/third_party/subzero/tests_lit/assembler/arm32/push-pop.ll
deleted file mode 100644
index 7b4b749..0000000
--- a/third_party/subzero/tests_lit/assembler/arm32/push-pop.ll
+++ /dev/null
@@ -1,161 +0,0 @@
-; Show that we know how to translate push and pop.
-; TODO(kschimpf) Translate pop instructions.
-
-; NOTE: We use -O2 to get rid of memory stores.
-
-; REQUIRES: allow_dump
-
-; Compile using standalone assembler.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -O2 -allow-extern \
-; RUN: | FileCheck %s --check-prefix=ASM
-
-; Show bytes in assembled standalone code.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -O2 -allow-extern | FileCheck %s --check-prefix=DIS
-
-; Compile using integrated assembler.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -O2 \
-; RUN: -allow-extern | FileCheck %s --check-prefix=IASM
-
-; Show bytes in assembled integrated code.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -O2 -allow-extern | FileCheck %s --check-prefix=DIS
-
-declare external void @DoSomething()
-
-define internal void @SinglePushPop() {
- call void @DoSomething();
- ret void
-}
-
-; ASM-LABEL:SinglePushPop:
-; ASM-NEXT:.LSinglePushPop$__0:
-; ASM-NEXT: push {lr}
-; ASM-NEXT: sub sp, sp, #12
-; ASM-NEXT: bl DoSomething
-; ASM-NEXT: add sp, sp, #12
-; ASM-NEXT: pop {lr}
-; ASM-NEXT: # lr = def.pseudo
-; ASM-NEXT: bx lr
-
-; DIS-LABEL:00000000 <SinglePushPop>:
-; DIS-NEXT: 0: e52de004
-; DIS-NEXT: 4: e24dd00c
-; DIS-NEXT: 8: ebfffffe
-; DIS-NEXT: c: e28dd00c
-; DIS-NEXT: 10: e49de004
-; DIS-NEXT: 14: e12fff1e
-
-; IASM-LABEL:SinglePushPop:
-; IASM-NEXT:.LSinglePushPop$__0:
-; IASM-NEXT: .byte 0x4
-; IASM-NEXT: .byte 0xe0
-; IASM-NEXT: .byte 0x2d
-; IASM-NEXT: .byte 0xe5
-
-; IASM-NEXT: .byte 0xc
-; IASM-NEXT: .byte 0xd0
-; IASM-NEXT: .byte 0x4d
-; IASM-NEXT: .byte 0xe2
-; IASM-NEXT: bl DoSomething @ .word ebfffffe
-; IASM-NEXT: .byte 0xc
-; IASM-NEXT: .byte 0xd0
-; IASM-NEXT: .byte 0x8d
-; IASM-NEXT: .byte 0xe2
-
-; IASM-NEXT: .byte 0x4
-; IASM-NEXT: .byte 0xe0
-; IASM-NEXT: .byte 0x9d
-; IASM-NEXT: .byte 0xe4
-
-; IASM: .byte 0x1e
-; IASM-NEXT: .byte 0xff
-; IASM-NEXT: .byte 0x2f
-; IASM-NEXT: .byte 0xe1
-
-; This test is based on taking advantage of the over-eager -O2
-; register allocator that puts V1 and V2 into callee-save registers,
-; since the call instruction kills the scratch registers. This
-; requires the callee-save registers to be pushed/popped in the
-; prolog/epilog.
-define internal i32 @MultPushPop(i32 %v1, i32 %v2) {
- call void @DoSomething();
- %v3 = add i32 %v1, %v2
- ret i32 %v3
-}
-
-; ASM-LABEL:MultPushPop:
-; ASM-NEXT:.LMultPushPop$__0:
-; ASM-NEXT: push {r4, r5, lr}
-; ASM-NEXT: sub sp, sp, #4
-; ASM-NEXT: mov r4, r0
-; ASM-NEXT: mov r5, r1
-; ASM-NEXT: bl DoSomething
-; ASM-NEXT: add r4, r4, r5
-; ASM-NEXT: mov r0, r4
-; ASM-NEXT: add sp, sp, #4
-; ASM-NEXT: pop {r4, r5, lr}
-; ASM-NEXT: # r4 = def.pseudo
-; ASM-NEXT: # r5 = def.pseudo
-; ASM-NEXT: # lr = def.pseudo
-; ASM-NEXT: bx lr
-
-; DIS-LABEL:00000020 <MultPushPop>:
-; DIS-NEXT: 20: e92d4030
-; DIS-NEXT: 24: e24dd004
-; DIS-NEXT: 28: e1a04000
-; DIS-NEXT: 2c: e1a05001
-; DIS-NEXT: 30: ebfffffe
-; DIS-NEXT: 34: e0844005
-; DIS-NEXT: 38: e1a00004
-; DIS-NEXT: 3c: e28dd004
-; DIS-NEXT: 40: e8bd4030
-; DIS-NEXT: 44: e12fff1e
-
-; IASM-LABEL:MultPushPop:
-; IASM-NEXT:.LMultPushPop$__0:
-; IASM-NEXT: .byte 0x30
-; IASM-NEXT: .byte 0x40
-; IASM-NEXT: .byte 0x2d
-; IASM-NEXT: .byte 0xe9
-
-; IASM-NEXT: .byte 0x4
-; IASM-NEXT: .byte 0xd0
-; IASM-NEXT: .byte 0x4d
-; IASM-NEXT: .byte 0xe2
-
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x40
-; IASM-NEXT: .byte 0xa0
-; IASM-NEXT: .byte 0xe1
-
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x50
-; IASM-NEXT: .byte 0xa0
-; IASM-NEXT: .byte 0xe1
-
-; IASM-NEXT: bl DoSomething @ .word ebfffffe
-; IASM-NEXT: .byte 0x5
-; IASM-NEXT: .byte 0x40
-; IASM-NEXT: .byte 0x84
-; IASM-NEXT: .byte 0xe0
-
-; IASM-NEXT: .byte 0x4
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xa0
-; IASM-NEXT: .byte 0xe1
-
-; IASM-NEXT: .byte 0x4
-; IASM-NEXT: .byte 0xd0
-; IASM-NEXT: .byte 0x8d
-; IASM-NEXT: .byte 0xe2
-
-; IASM-NEXT: .byte 0x30
-; IASM-NEXT: .byte 0x40
-; IASM-NEXT: .byte 0xbd
-; IASM-NEXT: .byte 0xe8
-
-; IASM: .byte 0x1e
-; IASM-NEXT: .byte 0xff
-; IASM-NEXT: .byte 0x2f
-; IASM-NEXT: .byte 0xe1
diff --git a/third_party/subzero/tests_lit/assembler/arm32/rbit.ll b/third_party/subzero/tests_lit/assembler/arm32/rbit.ll
deleted file mode 100644
index 8f217bd..0000000
--- a/third_party/subzero/tests_lit/assembler/arm32/rbit.ll
+++ /dev/null
@@ -1,44 +0,0 @@
-; Show that we know how to translate rbit.
-
-; NOTE: We use -O2 to get rid of memory stores.
-
-; REQUIRES: allow_dump
-
-; Compile using standalone assembler.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -O2 \
-; RUN: | FileCheck %s --check-prefix=ASM
-
-; Show bytes in assembled standalone code.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -O2 | FileCheck %s --check-prefix=DIS
-
-; Compile using integrated assembler.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -O2 \
-; RUN: | FileCheck %s --check-prefix=IASM
-
-; Show bytes in assembled integrated code.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -O2 | FileCheck %s --check-prefix=DIS
-
-declare i32 @llvm.cttz.i32(i32, i1)
-
-define internal i32 @testRbit(i32 %a) {
-; ASM-LABEL: testRbit:
-; DIS-LABEL: 00000000 <testRbit>:
-; IASM-LABEL: testRbit:
-
-entry:
-; ASM-NEXT: .LtestRbit$entry:
-; IASM-NEXT: .LtestRbit$entry:
-
- %x = call i32 @llvm.cttz.i32(i32 %a, i1 0)
-
-; ASM-NEXT: rbit r0, r0
-; DIS-NEXT: 0: e6ff0f30
-; IASM-NEXT: .byte 0x30
-; IASM-NEXT: .byte 0xf
-; IASM-NEXT: .byte 0xff
-; IASM-NEXT: .byte 0xe6
-
- ret i32 %x
-}
diff --git a/third_party/subzero/tests_lit/assembler/arm32/rem-vec.ll b/third_party/subzero/tests_lit/assembler/arm32/rem-vec.ll
deleted file mode 100644
index 00190cf..0000000
--- a/third_party/subzero/tests_lit/assembler/arm32/rem-vec.ll
+++ /dev/null
@@ -1,98 +0,0 @@
-; Show that we know how to translate vector urem, srem and frem.
-
-; NOTE: We use -O2 to get rid of memory stores.
-
-; REQUIRES: allow_dump
-
-; Compile using standalone assembler.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -O2 -mattr=hwdiv-arm \
-; RUN: | FileCheck %s --check-prefix=ASM
-
-define internal <4 x i32> @Urem4i32(<4 x i32> %a, <4 x i32> %b) {
-; ASM-LABEL:Urem4i32:
-
-entry:
-; ASM-NEXT:.LUrem4i32$entry:
-
- %v = urem <4 x i32> %a, %b
-
-; ASM-LABEL:.LUrem4i32$local$__0:
-; ASM-NEXT: udiv r2, r0, r1
-; ASM-NEXT: mls r2, r2, r1, r0
-; ASM-NEXT: vmov.32 d4[0], r2
-
-; ASM-LABEL:.LUrem4i32$local$__1:
-; ASM-NEXT: udiv r2, r0, r1
-; ASM-NEXT: mls r2, r2, r1, r0
-; ASM-NEXT: vmov.32 d4[1], r2
-
-; ASM-LABEL:.LUrem4i32$local$__2:
-; ASM-NEXT: udiv r2, r0, r1
-; ASM-NEXT: mls r2, r2, r1, r0
-; ASM-NEXT: vmov.32 d5[0], r2
-
-; ASM-LABEL:.LUrem4i32$local$__3:
-; ASM-NEXT: udiv r2, r0, r1
-; ASM-NEXT: mls r2, r2, r1, r0
-; ASM-NEXT: vmov.32 d5[1], r2
-
- ret <4 x i32> %v
-}
-
-define internal <4 x i32> @Srem4i32(<4 x i32> %a, <4 x i32> %b) {
-; ASM-LABEL:Srem4i32:
-
-entry:
-; ASM-NEXT:.LSrem4i32$entry:
-
- %v = srem <4 x i32> %a, %b
-
-; ASM-LABEL:.LSrem4i32$local$__0:
-; ASM-NEXT: sdiv r2, r0, r1
-; ASM-NEXT: mls r2, r2, r1, r0
-; ASM-NEXT: vmov.32 d4[0], r2
-
-; ASM-LABEL:.LSrem4i32$local$__1:
-; ASM-NEXT: sdiv r2, r0, r1
-; ASM-NEXT: mls r2, r2, r1, r0
-; ASM-NEXT: vmov.32 d4[1], r2
-
-; ASM-LABEL:.LSrem4i32$local$__2:
-; ASM-NEXT: sdiv r2, r0, r1
-; ASM-NEXT: mls r2, r2, r1, r0
-; ASM-NEXT: vmov.32 d5[0], r2
-
-; ASM-LABEL:.LSrem4i32$local$__3:
-; ASM-NEXT: sdiv r2, r0, r1
-; ASM-NEXT: mls r2, r2, r1, r0
-; ASM-NEXT: vmov.32 d5[1], r2
-
- ret <4 x i32> %v
-}
-
-define internal <4 x float> @Frem4float(<4 x float> %a, <4 x float> %b) {
-; ASM-LABEL:Frem4float:
-
-entry:
-; ASM-NEXT:.LFrem4float$entry:
-
- %v = frem <4 x float> %a, %b
-
-; ASM: vmov.f32 s0, s16
-; ASM-NEXT: vmov.f32 s1, s20
-; ASM-NEXT: bl fmodf
-
-; ASM: vmov.f32 s0, s17
-; ASM-NEXT: vmov.f32 s1, s21
-; ASM-NEXT: bl fmodf
-
-; ASM: vmov.f32 s0, s18
-; ASM-NEXT: vmov.f32 s1, s22
-; ASM-NEXT: bl fmodf
-
-; ASM: vmov.f32 s16, s19
-; ASM-NEXT: vmov.f32 s20, s23
-; ASM: bl fmodf
-
- ret <4 x float> %v
-}
diff --git a/third_party/subzero/tests_lit/assembler/arm32/ret.ll b/third_party/subzero/tests_lit/assembler/arm32/ret.ll
deleted file mode 100644
index ad8eef8..0000000
--- a/third_party/subzero/tests_lit/assembler/arm32/ret.ll
+++ /dev/null
@@ -1,64 +0,0 @@
-; Shows that the ARM integrated assembler can translate a trivial,
-; bundle-aligned function.
-
-; REQUIRES: allow_dump
-
-; Compile using standalone assembler.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -Om1 \
-; RUN: | FileCheck %s --check-prefix=ASM
-
-; Show bytes in assembled standalone code.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -Om1 | FileCheck %s --check-prefix=DIS
-
-; Compile using integrated assembler.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -Om1 \
-; RUN: | FileCheck %s --check-prefix=IASM
-
-; Show bytes in assembled integrated code.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -Om1 | FileCheck %s --check-prefix=DIS
-
-define internal void @f() {
- ret void
-}
-
-; ASM-LABEL:f:
-; ASM-NEXT: .Lf$__0:
-; ASM-NEXT: bx lr
-
-; DIS-LABEL:00000000 <f>:
-; IASM-LABEL:f:
-; IASM-NEXT:.Lf$__0:
-
-; DIS-NEXT: 0: e12fff1e
-; IASM-NEXT: .byte 0x1e
-; IASM-NEXT: .byte 0xff
-; IASM-NEXT: .byte 0x2f
-; IASM-NEXT: .byte 0xe1
-
-; DIS-NEXT: 4: e7fedef0
-; IASM-NEXT: .byte 0xf0
-; IASM-NEXT: .byte 0xde
-; IASM-NEXT: .byte 0xfe
-; IASM-NEXT: .byte 0xe7
-
-; DIS-NEXT: 8: e7fedef0
-; IASM-NEXT: .byte 0xf0
-; IASM-NEXT: .byte 0xde
-; IASM-NEXT: .byte 0xfe
-; IASM-NEXT: .byte 0xe7
-
-; DIS-NEXT: c: e7fedef0
-; IASM-NEXT: .byte 0xf0
-; IASM-NEXT: .byte 0xde
-; IASM-NEXT: .byte 0xfe
-; IASM-NEXT: .byte 0xe7
-
-define internal void @ignore() {
- ret void
-}
-
-; ASM-LABEL:ignore:
-; DIS-LABEL:00000010 <ignore>:
-; IASM-LABEL:ignore:
diff --git a/third_party/subzero/tests_lit/assembler/arm32/rev.ll b/third_party/subzero/tests_lit/assembler/arm32/rev.ll
deleted file mode 100644
index 6634813..0000000
--- a/third_party/subzero/tests_lit/assembler/arm32/rev.ll
+++ /dev/null
@@ -1,49 +0,0 @@
-; Show that we know how to translate rev (used in bswap).
-
-; NOTE: We use -O2 to get rid of memory stores.
-
-; REQUIRES: allow_dump
-
-; Compile using standalone assembler.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -O2 \
-; RUN: | FileCheck %s --check-prefix=ASM
-
-; Show bytes in assembled standalone code.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -O2 | FileCheck %s --check-prefix=DIS
-
-; Compile using integrated assembler.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -O2 \
-; RUN: | FileCheck %s --check-prefix=IASM
-
-; Show bytes in assembled integrated code.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -O2 | FileCheck %s --check-prefix=DIS
-
-declare i16 @llvm.bswap.i16(i16)
-
-define internal i32 @testRev(i32 %a) {
-; ASM-LABEL:testRev:
-; DIS-LABEL:00000000 <testRev>:
-; IASM-LABEL:testRev:
-
-entry:
-; ASM-NEXT:.LtestRev$entry:
-; IASM-NEXT:.LtestRev$entry:
-
- %a.arg_trunc = trunc i32 %a to i16
- %v = tail call i16 @llvm.bswap.i16(i16 %a.arg_trunc)
-
-; ***** Example of rev instruction. *****
-; ASM-NEXT: rev r0, r0
-; DIS-NEXT: 0: e6bf0f30
-; IASM-NEXT: .byte 0x30
-; IASM-NEXT: .byte 0xf
-; IASM-NEXT: .byte 0xbf
-; IASM-NEXT: .byte 0xe6
-
-; ASM-NEXT: lsr r0, r0, #16
-
- %.ret_ext = zext i16 %v to i32
- ret i32 %.ret_ext
-}
diff --git a/third_party/subzero/tests_lit/assembler/arm32/rsb.ll b/third_party/subzero/tests_lit/assembler/arm32/rsb.ll
deleted file mode 100644
index 962c0ed..0000000
--- a/third_party/subzero/tests_lit/assembler/arm32/rsb.ll
+++ /dev/null
@@ -1,140 +0,0 @@
-; Show that we know how to translate rsb. Uses shl as example, because it
-; uses rsb for type i64.
-
-; Also shows an example of a register-shifted register (data) operation.
-
-; REQUIRES: allow_dump
-
-; Compile using standalone assembler.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -Om1 \
-; RUN: | FileCheck %s --check-prefix=ASM
-
-; Show bytes in assembled standalone code.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -Om1 | FileCheck %s --check-prefix=DIS
-
-; Compile using integrated assembler.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -Om1 \
-; RUN: | FileCheck %s --check-prefix=IASM
-
-; Show bytes in assembled integrated code.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -Om1 | FileCheck %s --check-prefix=DIS
-
-define internal i64 @shiftLeft(i64 %v, i64 %l) {
-; ASM-LABEL:shiftLeft:
-; DIS-LABEL:00000000 <shiftLeft>:
-; IASM-LABEL:shiftLeft:
-
-entry:
-; ASM-NEXT:.LshiftLeft$entry:
-; IASM-NEXT:.LshiftLeft$entry:
-
-; ASM-NEXT: sub sp, sp, #24
-; DIS-NEXT: 0: e24dd018
-; IASM-NEXT: .byte 0x18
-; IASM-NEXT: .byte 0xd0
-; IASM-NEXT: .byte 0x4d
-; IASM-NEXT: .byte 0xe2
-
-; ASM-NEXT: str r0, [sp, #20]
-; ASM-NEXT: # [sp, #20] = def.pseudo
-; DIS-NEXT: 4: e58d0014
-; IASM-NEXT: .byte 0x14
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x8d
-; IASM-NEXT: .byte 0xe5
-
-; ASM-NEXT: mov r0, r1
-; DIS-NEXT: 8: e1a00001
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xa0
-; IASM-NEXT: .byte 0xe1
-
-; ASM-NEXT: str r0, [sp, #16]
-; ASM-NEXT: # [sp, #16] = def.pseudo
-; DIS-NEXT: c: e58d0010
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x8d
-; IASM-NEXT: .byte 0xe5
-
-; ASM-NEXT: mov r0, r2
-; DIS-NEXT: 10: e1a00002
-; IASM-NEXT: .byte 0x2
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xa0
-; IASM-NEXT: .byte 0xe1
-
-; ASM-NEXT: str r0, [sp, #12]
-; ASM-NEXT: # [sp, #12] = def.pseudo
-; DIS-NEXT: 14: e58d000c
-; IASM-NEXT: .byte 0xc
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x8d
-; IASM-NEXT: .byte 0xe5
-
-; ASM-NEXT: mov r0, r3
-; DIS-NEXT: 18: e1a00003
-; IASM-NEXT: .byte 0x3
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xa0
-; IASM-NEXT: .byte 0xe1
-
-; ASM-NEXT: str r0, [sp, #8]
-; ASM-NEXT: # [sp, #8] = def.pseudo
-; DIS-NEXT: 1c: e58d0008
-; IASM-NEXT: .byte 0x8
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x8d
-; IASM-NEXT: .byte 0xe5
-
- %result = shl i64 %v, %l
-
-; ASM-NEXT: ldr r0, [sp, #20]
-; DIS-NEXT: 20: e59d0014
-; IASM-NEXT: .byte 0x14
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x9d
-; IASM-NEXT: .byte 0xe5
-
-; ASM-NEXT: ldr r1, [sp, #16]
-; DIS-NEXT: 24: e59d1010
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0x9d
-; IASM-NEXT: .byte 0xe5
-
-; ASM-NEXT: ldr r2, [sp, #12]
-; DIS-NEXT: 28: e59d200c
-; IASM-NEXT: .byte 0xc
-; IASM-NEXT: .byte 0x20
-; IASM-NEXT: .byte 0x9d
-; IASM-NEXT: .byte 0xe5
-
-; ****** Here is the example of rsb *****
-; ASM-NEXT: rsb r3, r2, #32
-; DIS-NEXT: 2c: e2623020
-; IASM-NEXT: .byte 0x20
-; IASM-NEXT: .byte 0x30
-; IASM-NEXT: .byte 0x62
-; IASM-NEXT: .byte 0xe2
-
-; ASM-NEXT: lsr r3, r0, r3
-; DIS-NEXT: 30: e1a03330
-; IASM-NEXT: .byte 0x30
-; IASM-NEXT: .byte 0x33
-; IASM-NEXT: .byte 0xa0
-; IASM-NEXT: .byte 0xe1
-
-; ***** Here is an example of a register-shifted register *****
-; ASM-NEXT: orr r1, r3, r1, lsl r2
-; DIS-NEXT: 34: e1831211
-; IASM-NEXT: .byte 0x11
-; IASM-NEXT: .byte 0x12
-; IASM-NEXT: .byte 0x83
-; IASM-NEXT: .byte 0xe1
-
- ret i64 %result
-}
diff --git a/third_party/subzero/tests_lit/assembler/arm32/rsc.ll b/third_party/subzero/tests_lit/assembler/arm32/rsc.ll
deleted file mode 100644
index f79fc04..0000000
--- a/third_party/subzero/tests_lit/assembler/arm32/rsc.ll
+++ /dev/null
@@ -1,49 +0,0 @@
-; Show that we know how to translate rsc
-
-; NOTE: We use -O2 to get rid of memory stores.
-
-; REQUIRES: allow_dump
-
-; Compile using standalone assembler.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -O2 \
-; RUN: | FileCheck %s --check-prefix=ASM
-
-; Show bytes in assembled standalone code.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -O2 | FileCheck %s --check-prefix=DIS
-
-; Compile using integrated assembler.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -O2 \
-; RUN: | FileCheck %s --check-prefix=IASM
-
-; Show bytes in assembled integrated code.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -O2 | FileCheck %s --check-prefix=DIS
-
-define internal i64 @NegateI64(i64 %a) {
-; ASM-LABEL:NegateI64:
-; DIS-LABEL:00000000 <NegateI64>:
-; IASM-LABEL:NegateI64:
-
-entry:
-; ASM-NEXT:.LNegateI64$entry:
-; IASM-NEXT:.LNegateI64$entry:
-
- %res = sub i64 0, %a
-
-; ASM-NEXT: rsbs r0, r0, #0
-; DIS-NEXT: 0: e2700000
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x70
-; IASM-NEXT: .byte 0xe2
-
-; ASM-NEXT: rsc r1, r1, #0
-; DIS-NEXT: 4: e2e11000
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0xe1
-; IASM-NEXT: .byte 0xe2
-
- ret i64 %res
-}
diff --git a/third_party/subzero/tests_lit/assembler/arm32/sandboxing.ll b/third_party/subzero/tests_lit/assembler/arm32/sandboxing.ll
deleted file mode 100644
index 3ff27cb..0000000
--- a/third_party/subzero/tests_lit/assembler/arm32/sandboxing.ll
+++ /dev/null
@@ -1,307 +0,0 @@
-; Tests basics and corner cases of arm32 sandboxing, using -Om1 in the hope that
-; the output will remain stable. When packing bundles, we try to limit to a few
-; instructions with well known sizes and minimal use of registers and stack
-; slots in the lowering sequence.
-
-; REQUIRES: allow_dump, target_ARM32
-; RUN: %p2i -i %s --sandbox --filetype=asm --target=arm32 --assemble \
-; RUN: --disassemble --args -Om1 -allow-externally-defined-symbols \
-; RUN: -ffunction-sections -reg-use r0,r1,r3 | FileCheck %s
-
-declare void @call_target()
-declare void @call_target1(i32 %arg0)
-declare void @call_target2(i32 %arg0, i32 %arg1)
-declare void @call_target3(i32 %arg0, i32 %arg1, i32 %arg2)
-@global_short = internal global [2 x i8] zeroinitializer
-
-; A direct call sequence uses the right mask and register-call sequence.
-define internal void @test_direct_call() {
-entry:
- call void @call_target()
- ; bundle aigned.
- ret void
-}
-
-; CHECK-LABEL:<test_direct_call>:
-; Search for bundle alignment of first call.
-; CHECK: {{[0-9a-f]*}}c: {{.*}} bl {{.*}} call_target
-
-; Same as above, but force bundle padding by adding three (branch) instruction
-; before the tested call.
-define internal void @test_direct_call_with_padding_1() {
-entry:
- call void @call_target()
- ; bundle aigned.
-
- br label %next1 ; add 1 inst.
-next1:
- br label %next2 ; add 1 inst.
-next2:
- call void @call_target()
- ret void
-}
-; CHECK-LABEL:<test_direct_call_with_padding_1>:
-; Search for bundle alignment of first call.
-; CHECK: {{[0-9a-f]*}}c: {{.+}} bl
-; CHECK-NEXT: b
-; CHECK-NEXT: b
-; CHECK-NEXT: nop
-; CHECK-NEXT: bl {{.*}} call_target
-; CHECK-NEXT: {{[0-9a-f]*}}0:
-
-; Same as above, but force bundle padding by adding two (branch) instruction
-; before the tested call.
-define internal void @test_direct_call_with_padding_2() {
-entry:
- call void @call_target()
- ; bundle aigned.
-
- br label %next1 ; add 1 inst.
-next1:
- call void @call_target()
- ret void
-}
-
-; CHECK-LABEL:<test_direct_call_with_padding_2>:
-; Search for bundle alignment of first call.
-; CHECK: {{[0-9a-f]*}}c: {{.+}} bl
-; CHECK-NEXT: b
-; CHECK-NEXT: nop
-; CHECK-NEXT: nop
-; CHECK-NEXT: bl {{.*}} call_target
-; CHECK-NEXT: {{[0-9a-f]*}}0:
-
-; Same as above, but force bundle padding by adding single (branch) instruction
-; before the tested call.
-define internal void @test_direct_call_with_padding_3() {
-entry:
- call void @call_target()
- ; bundle aigned.
-
- call void @call_target()
- ret void
-}
-
-; CHECK-LABEL:<test_direct_call_with_padding_3>:
-; Search for bundle alignment of first call.
-; CHECK: {{[0-9a-f]*}}c: {{.+}} bl
-; CHECK-NEXT: nop
-; CHECK-NEXT: nop
-; CHECK-NEXT: nop
-; CHECK-NEXT: bl {{.*}} call_target
-; CHECK-NEXT: {{[0-9a-f]*}}0:
-
-; An indirect call sequence uses the right mask and register-call sequence.
-define internal void @test_indirect_call(i32 %target) {
-entry:
- %__1 = inttoptr i32 %target to void ()*
- call void @call_target();
- ; bundle aigned.
-
- br label %next ; add 1 inst.
-next:
- call void %__1() ; requires 3 insts.
- ret void
-}
-
-; CHECK-LABEL:<test_indirect_call>:
-; Search for bundle alignment of first call.
-; CHECK: {{[0-9a-f]*}}c: {{.+}} bl
-; CHECK-NEXT: b
-; CHECK-NEXT: ldr
-; CHECK-NEXT: bic [[REG:r[0-3]]], [[REG]], {{.*}} 0xc000000f
-; CHECK-NEXT: blx [[REG]]
-; CHECK-NEXT: {{[0-9]+}}0:
-
-; An indirect call sequence uses the right mask and register-call sequence.
-; Forces bundling before the tested call.
-define internal void @test_indirect_call_with_padding_1(i32 %target) {
-entry:
- %__1 = inttoptr i32 %target to void ()*
- call void @call_target();
- ; bundle aigned.
- call void %__1() ; requires 3 insts.
- ret void
-}
-
-; CHECK-LABEL: <test_indirect_call_with_padding_1>:
-; Search for bundle alignment of first call.
-; CHECK: {{[0-9a-f]*}}c: {{.+}} bl
-; CHECK-NEXT: ldr
-; CHECK-NEXT: nop
-; CHECK-NEXT: bic [[REG:r[0-3]]], [[REG]], {{.*}} 0xc000000f
-; CHECK-NEXT: blx [[REG]]
-; CHECK-NEXT: {{[0-9]+}}0:
-
-; An indirect call sequence uses the right mask and register-call sequence.
-; Forces bundling by adding three (branch) instructions befor the tested call.
-define internal void @test_indirect_call_with_padding_2(i32 %target) {
-entry:
- %__1 = inttoptr i32 %target to void ()*
- call void @call_target();
- ; bundle aigned.
-
- br label %next1 ; add 1 inst.
-next1:
- br label %next2 ; add 1 inst.
-next2:
- br label %next3 ; add 1 inst.
-next3:
- call void %__1() ; requires 3 insts.
- ret void
-}
-
-; CHECK-LABEL: <test_indirect_call_with_padding_2>:
-; Search for bundle alignment of first call.
-; CHECK: {{[0-9a-f]*}}c: {{.+}} bl
-; CHECK-NEXT: b
-; CHECK-NEXT: b
-; CHECK-NEXT: b
-; CHECK-NEXT: ldr
-; CHECK-NEXT: nop
-; CHECK-NEXT: nop
-; CHECK-NEXT: bic [[REG:r[0-3]]], [[REG]], {{.*}} 0xc000000f
-; CHECK-NEXT: blx [[REG]]
-; CHECK-NEXT: {{[0-9]+}}0:
-
-; An indirect call sequence uses the right mask and register-call sequence.
-; Forces bundling by adding two (branch) instructions befor the tested call.
-define internal void @test_indirect_call_with_padding_3(i32 %target) {
-entry:
- %__1 = inttoptr i32 %target to void ()*
- call void @call_target();
- ; bundle aigned.
-
- br label %next1 ; add 1 inst
-next1:
- br label %next2 ; add 1 inst
-next2:
- call void %__1() ; requires 3 insts.
- ret void
-}
-; CHECK-LABEL: <test_indirect_call_with_padding_3>:
-; Search for bundle alignment of first call.
-; CHECK: {{[0-9a-f]*}}c: {{.+}} bl
-; CHECK-NEXT: b
-; CHECK-NEXT: b
-; CHECK-NEXT: ldr
-; CHECK-NEXT: nop
-; CHECK-NEXT: nop
-; CHECK-NEXT: nop
-; CHECK-NEXT: bic [[REG:r[0-3]]], [[REG]], {{.*}} 0xc000000f
-; CHECK-NEXT: blx [[REG]]
-; CHECK-NEXT: {{[0-9]+}}0:
-
-; A return sequences uses the right pop / mask / jmp sequence.
-define internal void @test_ret() {
-entry:
- call void @call_target()
- ; Bundle boundary.
- br label %next ; add 1 inst.
-next:
- ret void
-}
-; CHECK-LABEL:<test_ret>:
-; Search for bundle alignment of first call.
-; CHECK: {{[0-9a-f]*}}c: {{.+}} bl
-; CHECK-NEXT: b
-; CHECK-NEXT: add sp, sp
-; CHECK-NEXT: bic sp, sp, {{.+}} ; 0xc0000000
-; CHECK-NEXT: pop {lr}
-; CHECK-NEXT: {{[0-9a-f]*}}0: {{.+}} bic lr, lr, {{.+}} ; 0xc000000f
-; CHECK-NEXT: bx lr
-
-; A return sequence with padding for bundle lock.
-define internal void @test_ret_with_padding() {
- call void @call_target()
- ; Bundle boundary.
- ret void
-}
-
-; CHECK-LABEL:<test_ret_with_padding>:
-; Search for bundle alignment of first call.
-; CHECK: {{[0-9a-f]*}}c: {{.+}} bl
-; CHECK-NEXT: add sp, sp
-; CHECK-NEXT: bic sp, sp, {{.+}} ; 0xc0000000
-; CHECK-NEXT: pop {lr}
-; CHECK-NEXT: nop
-; CHECK-NEXT: {{[0-9a-f]*}}0: {{.+}} bic lr, lr, {{.+}} ; 0xc000000f
-; CHECK-NEXT: bx lr
-
-; Store without bundle padding.
-define internal void @test_store() {
-entry:
- call void @call_target()
- ; Bundle boundary
- store i16 1, i16* undef, align 1 ; 3 insts + bic.
- ret void
-}
-
-; CHECK-LABEL: test_store
-; Search for call at end of bundle.
-; CHECK: {{[0-9a-f]*}}c: {{.+}} bl
-; CHECK-NEXT: mov [[REG:r[0-9]]], #0
-; CHECK-NEXT: mov
-; CHECK-NEXT: bic [[REG]], [[REG]], {{.+}} ; 0xc0000000
-; CHECK-NEXT: strh r{{.+}}[[REG]]
-
-; Store with bundle padding. Force padding by adding a single branch
-; instruction.
-define internal void @test_store_with_padding() {
-entry:
- call void @call_target()
- ; bundle boundary
- br label %next ; add 1 inst.
-next:
- store i16 0, i16* undef, align 1 ; 3 insts
- ret void
-}
-; CHECK-LABEL: test_store_with_padding
-; Search for call at end of bundle.
-; CHECK: {{[0-9a-f]*}}c: {{.+}} bl
-; CHECK-NEXT: b
-; CHECK-NEXT: mov [[REG:r[0-9]]], #0
-; CHECK-NEXT: mov
-; CHECK-NEXT: nop
-; CHECK-NEXT: bic [[REG]], [[REG]], {{.+}} ; 0xc0000000
-; CHECK-NEXT: strh r{{.+}}[[REG]]
-
-
-; Store without bundle padding.
-define internal i32 @test_load() {
-entry:
- call void @call_target()
- ; Bundle boundary
- %v = load i32, i32* undef, align 1 ; 4 insts, bundling middle 2.
- ret i32 %v
-}
-
-; CHECK-LABEL: test_load
-; Search for call at end of bundle.
-; CHECK: {{[0-9a-f]*}}c: {{.+}} bl
-; CHECK-NEXT: mov [[REG:r[0-9]]], #0
-; CHECK-NEXT: bic [[REG]], [[REG]], {{.+}} ; 0xc0000000
-; CHECK-NEXT: ldr r{{.+}}[[REG]]
-
-; Store with bundle padding.
-define internal i32 @test_load_with_padding() {
-entry:
- call void @call_target()
- ; Bundle boundary
- br label %next1 ; add 1 inst.
-next1:
- br label %next2 ; add 1 inst.
-next2:
- %v = load i32, i32* undef, align 1 ; 4 insts, bundling middle 2.
- ret i32 %v
-}
-
-; CHECK-LABEL: test_load_with_padding
-; Search for call at end of bundle.
-; CHECK: {{[0-9a-f]*}}c: {{.+}} bl
-; CHECK-NEXT: b
-; CHECK-NEXT: b
-; CHECK-NEXT: mov [[REG:r[0-9]]], #0
-; CHECK-NEXT: nop
-; CHECK-NEXT: bic [[REG]], [[REG]], {{.+}} ; 0xc0000000
-; CHECK-NEXT: ldr r{{.+}}[[REG]]
diff --git a/third_party/subzero/tests_lit/assembler/arm32/sdiv.ll b/third_party/subzero/tests_lit/assembler/arm32/sdiv.ll
deleted file mode 100644
index c365b76..0000000
--- a/third_party/subzero/tests_lit/assembler/arm32/sdiv.ll
+++ /dev/null
@@ -1,72 +0,0 @@
-; Show that we know how to translate sdiv
-
-; NOTE: We use -O2 to get rid of memory stores.
-
-; REQUIRES: allow_dump
-
-; Compile using standalone assembler.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -O2 -mattr=hwdiv-arm \
-; RUN: | FileCheck %s --check-prefix=ASM
-
-; Show bytes in assembled standalone code.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -O2 -mattr=hwdiv-arm | FileCheck %s --check-prefix=DIS
-
-; Compile using integrated assembler.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -O2 -mattr=hwdiv-arm \
-; RUN: | FileCheck %s --check-prefix=IASM
-
-; Show bytes in assembled integrated code.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -O2 -mattr=hwdiv-arm \
-; RUN: | FileCheck %s --check-prefix=DIS
-
-define internal i32 @SdivTwoRegs(i32 %a, i32 %b) {
- %v = sdiv i32 %a, %b
- ret i32 %v
-}
-
-; ASM-LABEL:SdivTwoRegs:
-; ASM-NEXT:.LSdivTwoRegs$__0:
-; ASM-NEXT: tst r1, r1
-; ASM-NEXT: bne .LSdivTwoRegs$local$__0
-; ASM-NEXT: .long 0xe7fedef0
-; ASM-NEXT:.LSdivTwoRegs$local$__0:
-; ASM-NEXT: sdiv r0, r0, r1
-; ASM-NEXT: bx lr
-
-; DIS-LABEL:00000000 <SdivTwoRegs>:
-; DIS-NEXT: 0: e1110001
-; DIS-NEXT: 4: 1a000000
-; DIS-NEXT: 8: e7fedef0
-; DIS-NEXT: c: e710f110
-; DIS-NEXT: 10: e12fff1e
-
-; IASM-LABEL:SdivTwoRegs:
-; IASM-NEXT:.LSdivTwoRegs$__0:
-
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x11
-; IASM-NEXT: .byte 0xe1
-
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x1a
-
-; IASM-NEXT: .byte 0xf0
-; IASM-NEXT: .byte 0xde
-; IASM-NEXT: .byte 0xfe
-; IASM-NEXT: .byte 0xe7
-
-; IASM-NEXT:.LSdivTwoRegs$local$__0:
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0xf1
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0xe7
-
-; IASM-NEXT: .byte 0x1e
-; IASM-NEXT: .byte 0xff
-; IASM-NEXT: .byte 0x2f
-; IASM-NEXT: .byte 0xe1
diff --git a/third_party/subzero/tests_lit/assembler/arm32/select-vec.ll b/third_party/subzero/tests_lit/assembler/arm32/select-vec.ll
deleted file mode 100644
index 415f936..0000000
--- a/third_party/subzero/tests_lit/assembler/arm32/select-vec.ll
+++ /dev/null
@@ -1,106 +0,0 @@
-; Test that we handle select on vectors.
-
-; REQUIRES: allow_dump
-
-; Compile using standalone assembler.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -O2 \
-; RUN: | FileCheck %s --check-prefix=ASM
-
-; Show bytes in assembled standalone code.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -O2 --reg-use=s20 | FileCheck %s --check-prefix=DIS
-
-; Compile using integrated assembler.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -O2 \
-; RUN: --reg-use=s20 \
-; RUN: | FileCheck %s --check-prefix=IASM
-
-; Show bytes in assembled integrated code.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -O2 --reg-use=s20 | FileCheck %s --check-prefix=DIS
-
-define internal <4 x float> @select4float(<4 x i1> %s, <4 x float> %a,
- <4 x float> %b) {
-; ASM-LABEL:select4float:
-; DIS-LABEL:00000000 <select4float>:
-; IASM-LABEL:select4float:
-
-entry:
- %res = select <4 x i1> %s, <4 x float> %a, <4 x float> %b
-
-; ASM: vshl.u32 [[M:.*]], {{.*}}, #31
-; ASM-NEXT: vshr.s32 [[M:.*]], {{.*}}, #31
-; ASM-NEXT: vbsl.i32 [[M]], {{.*}}
-; DIS: 0: f2bf0550
-; DIS-NEXT: 4: f2a10050
-; DIS-NEXT: 8: f3120154
-; IASM-NOT: vshl
-; IASM-NOT: vshr
-; IASM-NOT: vbsl
-
- ret <4 x float> %res
-}
-
-define internal <4 x i32> @select4i32(<4 x i1> %s, <4 x i32> %a, <4 x i32> %b) {
-; ASM-LABEL:select4i32:
-; DIS-LABEL:00000010 <select4i32>:
-; IASM-LABEL:select4i32:
-
-entry:
- %res = select <4 x i1> %s, <4 x i32> %a, <4 x i32> %b
-
-; ASM: vshl.u32 [[M:.*]], {{.*}}, #31
-; ASM-NEXT: vshr.s32 [[M:.*]], {{.*}}, #31
-; ASM-NEXT: vbsl.i32 [[M]], {{.*}}
-; DIS: 10: f2bf0550
-; DIS-NEXT: 14: f2a10050
-; DIS_NEXT: 18: f3120154
-; IASM-NOT: vshl
-; IASM-NOT: vshr
-; IASM-NOT: vbsl
-
- ret <4 x i32> %res
-}
-
-define internal <8 x i16> @select8i16(<8 x i1> %s, <8 x i16> %a, <8 x i16> %b) {
-; ASM-LABEL:select8i16:
-; DIS-LABEL:00000020 <select8i16>:
-; IASM-LABEL:select8i16:
-
-entry:
- %res = select <8 x i1> %s, <8 x i16> %a, <8 x i16> %b
-
-; ASM: vshl.u16 [[M:.*]], {{.*}}, #15
-; ASM-NEXT: vshr.s16 [[M:.*]], {{.*}}, #15
-; ASM-NEXT: vbsl.i16 [[M]], {{.*}}
-; DIS: 20: f29f0550
-; DIS-NEXT: 24: f2910050
-; DIS-NEXT: 28: f3120154
-; IASM-NOT: vshl
-; IASM-NOT: vshr
-; IASM-NOT: vbsl
-
- ret <8 x i16> %res
-}
-
-define internal <16 x i8> @select16i8(<16 x i1> %s, <16 x i8> %a,
- <16 x i8> %b) {
-; ASM-LABEL:select16i8:
-; DIS-LABEL:00000030 <select16i8>:
-; IASM-LABEL:select16i8:
-
-entry:
- %res = select <16 x i1> %s, <16 x i8> %a, <16 x i8> %b
-
-; ASM: vshl.u8 [[M:.*]], {{.*}}, #7
-; ASM-NEXT: vshr.s8 [[M:.*]], {{.*}}, #7
-; ASM-NEXT: vbsl.i8 [[M]], {{.*}}
-; DIS: 30: f28f0550
-; DIS-NEXT: 34: f2890050
-; DIS-NEXT: 38: f3120154
-; IASM-NOT: vshl
-; IASM-NOT: vshr
-; IASM-NOT: vbsl
-
- ret <16 x i8> %res
-}
diff --git a/third_party/subzero/tests_lit/assembler/arm32/store-sf.ll b/third_party/subzero/tests_lit/assembler/arm32/store-sf.ll
deleted file mode 100644
index fe76000..0000000
--- a/third_party/subzero/tests_lit/assembler/arm32/store-sf.ll
+++ /dev/null
@@ -1,77 +0,0 @@
-; Sample program that generates "str reg, [fp, #CCCC]", to show that we
-; recognize that "fp" should be used instead of "sp".
-
-; REQUIRES: allow_dump
-
-; Compile using standalone assembler.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -Om1 \
-; RUN: | FileCheck %s --check-prefix=ASM
-
-; Show bytes in assembled standalone code.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -Om1 | FileCheck %s --check-prefix=DIS
-
-; Compile using integrated assembler.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -Om1 \
-; RUN: | FileCheck %s --check-prefix=IASM
-
-; Show bytes in assembled integrated code.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -Om1 | FileCheck %s --check-prefix=DIS
-
-define internal void @test_vla_in_loop(i32 %n) {
-; ASM-LABEL: test_vla_in_loop:
-; DIS-LABEL: 00000000 <test_vla_in_loop>:
-; IASM-LABEL: test_vla_in_loop:
-
-entry:
-
-; ASM-NEXT: .Ltest_vla_in_loop$entry:
-; IASM-NEXT: .Ltest_vla_in_loop$entry:
-
-; ASM-NEXT: push {fp}
-; DIS-NEXT: 0: e52db004
-; IASM-NEXT: .byte 0x4
-; IASM-NEXT: .byte 0xb0
-; IASM-NEXT: .byte 0x2d
-; IASM-NEXT: .byte 0xe5
-
-; ASM-NEXT: mov fp, sp
-; DIS-NEXT: 4: e1a0b00d
-; IASM-NEXT: .byte 0xd
-; IASM-NEXT: .byte 0xb0
-; IASM-NEXT: .byte 0xa0
-; IASM-NEXT: .byte 0xe1
-
-; ASM-NEXT: sub sp, sp, #12
-; DIS-NEXT: 8: e24dd00c
-; IASM-NEXT: .byte 0xc
-; IASM-NEXT: .byte 0xd0
-; IASM-NEXT: .byte 0x4d
-; IASM-NEXT: .byte 0xe2
-
-; **** Example of fixed instruction.
-; ASM-NEXT: str r0, [fp, #-4]
-; DIS-NEXT: c: e50b0004
-; IASM-NEXT: .byte 0x4
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xb
-; IASM-NEXT: .byte 0xe5
-; ASM-NEXT: # [fp, #-4] = def.pseudo
- br label %next
-
-; ASM-NEXT: b .Ltest_vla_in_loop$next
-; DIS-NEXT: 10: eaffffff
-
-; IASM-NEXT: .byte 0xff
-; IASM-NEXT: .byte 0xff
-; IASM-NEXT: .byte 0xff
-; IASM-NEXT: .byte 0xea
-
-; Put the variable-length alloca in a non-entry block, to reduce the
-; chance the optimizer putting it before the regular frame creation.
-
-next:
- %v = alloca i8, i32 %n, align 4
- ret void
-}
diff --git a/third_party/subzero/tests_lit/assembler/arm32/sub-vec.ll b/third_party/subzero/tests_lit/assembler/arm32/sub-vec.ll
deleted file mode 100644
index 923766b..0000000
--- a/third_party/subzero/tests_lit/assembler/arm32/sub-vec.ll
+++ /dev/null
@@ -1,85 +0,0 @@
-; Show that we know how to translate vsub vector instructions.
-
-; REQUIRES: allow_dump
-
-; Compile using standalone assembler.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -O2 \
-; RUN: -reg-use q10,q11 \
-; RUN: | FileCheck %s --check-prefix=ASM
-
-; Show bytes in assembled standalone code.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -O2 \
-; RUN: -reg-use q10,q11 \
-; RUN: | FileCheck %s --check-prefix=DIS
-
-; Compile using integrated assembler.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -O2 \
-; RUN: -reg-use q10,q11 \
-; RUN: | FileCheck %s --check-prefix=IASM
-
-; Show bytes in assembled integrated code.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -O2 \
-; RUN: -reg-use q10,q11 \
-; RUN: | FileCheck %s --check-prefix=DIS
-
-define internal <4 x float> @testVsubFloat4(<4 x float> %v1, <4 x float> %v2) {
-; ASM-LABEL: testVsubFloat4:
-; DIS-LABEL: 00000000 <testVsubFloat4>:
-; IASM-LABEL: testVsubFloat4:
-
-entry:
- %res = fsub <4 x float> %v1, %v2
-
-; ASM: vsub.f32 q10, q10, q11
-; DIS: 8: f2644de6
-; IASM-NOT: vsub.f32
-
- ret <4 x float> %res
-}
-
-define internal <4 x i32> @testVsub4i32(<4 x i32> %v1, <4 x i32> %v2) {
-; ASM-LABEL: testVsub4i32:
-; DIS-LABEL: 00000020 <testVsub4i32>:
-; IASM-LABEL: testVsub4i32:
-
-entry:
- %res = sub <4 x i32> %v1, %v2
-
-; ASM: vsub.i32 q10, q10, q11
-; DIS: 28: f36448e6
-; IASM-NOT: vsub.i32
-
- ret <4 x i32> %res
-}
-
-define internal <8 x i16> @testVsub8i16(<8 x i16> %v1, <8 x i16> %v2) {
-; ASM-LABEL: testVsub8i16:
-; DIS-LABEL: 00000040 <testVsub8i16>:
-; IASM-LABEL: testVsub8i16:
-
-entry:
- %res = sub <8 x i16> %v1, %v2
-
-; ASM: vsub.i16 q10, q10, q11
-; DIS: 48: f35448e6
-; IASM-NOT: vsub.i16
-
- ret <8 x i16> %res
-}
-
-define internal <16 x i8> @testVsub16i8(<16 x i8> %v1, <16 x i8> %v2) {
-; ASM-LABEL: testVsub16i8:
-; DIS-LABEL: 00000060 <testVsub16i8>:
-; IASM-LABEL: testVsub16i8:
-
-entry:
- %res = sub <16 x i8> %v1, %v2
-
-; ASM: vsub.i8 q10, q10, q11
-; DIS: 68: f34448e6
-; IASM-NOT: vsub.i8
-
- ret <16 x i8> %res
-}
diff --git a/third_party/subzero/tests_lit/assembler/arm32/sub.ll b/third_party/subzero/tests_lit/assembler/arm32/sub.ll
deleted file mode 100644
index 51db745..0000000
--- a/third_party/subzero/tests_lit/assembler/arm32/sub.ll
+++ /dev/null
@@ -1,123 +0,0 @@
-; Show that we know how to translate sub.
-
-; NOTE: We use -O2 to get rid of memory stores.
-
-; REQUIRES: allow_dump
-
-; Compile using standalone assembler.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -O2 \
-; RUN: | FileCheck %s --check-prefix=ASM
-
-; Show bytes in assembled standalone code.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -O2 | FileCheck %s --check-prefix=DIS
-
-; Compile using integrated assembler.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -O2 \
-; RUN: | FileCheck %s --check-prefix=IASM
-
-; Show bytes in assembled integrated code.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -O2 | FileCheck %s --check-prefix=DIS
-
-define internal i32 @Sub1FromR0(i32 %p) {
- %v = sub i32 %p, 1
- ret i32 %v
-}
-
-; ASM-LABEL: Sub1FromR0:
-; ASM-NEXT: .LSub1FromR0$__0:
-; ASM-NEXT: sub r0, r0, #1
-; ASM-NEXT: bx lr
-
-; DIS-LABEL:00000000 <Sub1FromR0>:
-; DIS-NEXT: 0: e2400001
-; DIS-NEXT: 4: e12fff1e
-
-; IASM-LABEL: Sub1FromR0:
-; IASM-LABEL: .LSub1FromR0$__0:
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x40
-; IASM-NEXT: .byte 0xe2
-
-; IASM-NEXT: .byte 0x1e
-; IASM-NEXT: .byte 0xff
-; IASM-NEXT: .byte 0x2f
-; IASM-NEXT: .byte 0xe1
-
-define internal i32 @Sub2Regs(i32 %p1, i32 %p2) {
- %v = sub i32 %p1, %p2
- ret i32 %v
-}
-
-; ASM-LABEL: Sub2Regs:
-; ASM-NEXT: .LSub2Regs$__0:
-; ASM-NEXT: sub r0, r0, r1
-; ASM-NEXT: bx lr
-
-; DIS-LABEL:00000010 <Sub2Regs>:
-; DIS-NEXT: 10: e0400001
-; DIS-NEXT: 14: e12fff1e
-
-; IASM-LABEL: Sub2Regs:
-; IASM-NEXT: .LSub2Regs$__0:
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x40
-; IASM-NEXT: .byte 0xe0
-
-; IASM-NEXT: .byte 0x1e
-; IASM-NEXT: .byte 0xff
-; IASM-NEXT: .byte 0x2f
-; IASM-NEXT: .byte 0xe1
-
-define internal i64 @SubI64FromR0R1(i64 %p) {
- %v = sub i64 %p, 1
- ret i64 %v
-}
-
-; ASM-LABEL:SubI64FromR0R1:
-; ASM-NEXT:.LSubI64FromR0R1$__0:
-; ASM-NEXT: subs r0, r0, #1
-; ASM-NEXT: sbc r1, r1, #0
-
-; DIS-LABEL:00000020 <SubI64FromR0R1>:
-; DIS-NEXT: 20: e2500001
-; DIS-NEXT: 24: e2c11000
-
-; IASM-LABEL:SubI64FromR0R1:
-; IASM-NEXT:.LSubI64FromR0R1$__0:
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x50
-; IASM-NEXT: .byte 0xe2
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0xc1
-; IASM-NEXT: .byte 0xe2
-
-define internal i64 @SubI64Regs(i64 %p1, i64 %p2) {
- %v = sub i64 %p1, %p2
- ret i64 %v
-}
-
-; ASM-LABEL:SubI64Regs:
-; ASM-NEXT:.LSubI64Regs$__0:
-; ASM-NEXT: subs r0, r0, r2
-; ASM-NEXT: sbc r1, r1, r3
-
-; DIS-LABEL:00000030 <SubI64Regs>:
-; DIS-NEXT: 30: e0500002
-; DIS-NEXT: 34: e0c11003
-
-; IASM-LABEL:SubI64Regs:
-; IASM-NEXT:.LSubI64Regs$__0:
-; IASM-NEXT: .byte 0x2
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x50
-; IASM-NEXT: .byte 0xe0
-; IASM-NEXT: .byte 0x3
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0xc1
-; IASM-NEXT: .byte 0xe0
diff --git a/third_party/subzero/tests_lit/assembler/arm32/trap.ll b/third_party/subzero/tests_lit/assembler/arm32/trap.ll
deleted file mode 100644
index 52a5a12..0000000
--- a/third_party/subzero/tests_lit/assembler/arm32/trap.ll
+++ /dev/null
@@ -1,55 +0,0 @@
-; Show that we can translate IR instruction "trap".
-
-; REQUIRES: allow_dump
-
-; Compile using standalone assembler.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -Om1 \
-; RUN: | FileCheck %s --check-prefix=ASM
-
-; Show bytes in assembled standalone code.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -Om1 \
-; RUN: | FileCheck %s --check-prefix=DIS
-
-; Compile using integrated assembler.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -Om1 \
-; RUN: | FileCheck %s --check-prefix=IASM
-
-; Show bytes in assembled integrated code.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -Om1 \
-; RUN: | FileCheck %s --check-prefix=DIS
-
-; testUnreachable generates a trap for the unreachable instruction.
-
-define internal void @testUnreachable() {
-; ASM-LABEL: testUnreachable:
-; DIS-LABEL: 00000000 <testUnreachable>:
-
- unreachable
-
-; ASM: .long 0xe7fedef0
-; DIS-NEXT: 0: e7fedef0
-; IASM-NOT: .long 0xe7fedef0
-}
-
-; testTrap uses integer division to test this, since a trap is
-; inserted if one divides by zero.
-
-define internal i32 @testTrap(i32 %v1, i32 %v2) {
-; ASM-LABEL: testTrap:
-; DIS-LABEL: 00000010 <testTrap>:
-; IASM-LABEL: testTrap:
-
- %res = udiv i32 %v1, %v2
-
-; ASM: bne
-; DIS: 28: 1a000000
-; IASM-NOT: bne
-
-; ASM-NEXT: .long 0xe7fedef0
-; DIS-NEXT: 2c: e7fedef0
-; IASM-NOT: .long 0xe7fedef0
-
- ret i32 %res
-}
diff --git a/third_party/subzero/tests_lit/assembler/arm32/udiv.ll b/third_party/subzero/tests_lit/assembler/arm32/udiv.ll
deleted file mode 100644
index 7a41e12..0000000
--- a/third_party/subzero/tests_lit/assembler/arm32/udiv.ll
+++ /dev/null
@@ -1,72 +0,0 @@
-; Show that we know how to translate udiv
-
-; NOTE: We use -O2 to get rid of memory stores.
-
-; REQUIRES: allow_dump
-
-; Compile using standalone assembler.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -O2 -mattr=hwdiv-arm \
-; RUN: | FileCheck %s --check-prefix=ASM
-
-; Show bytes in assembled standalone code.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -O2 -mattr=hwdiv-arm | FileCheck %s --check-prefix=DIS
-
-; Compile using integrated assembler.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -O2 -mattr=hwdiv-arm \
-; RUN: | FileCheck %s --check-prefix=IASM
-
-; Show bytes in assembled integrated code.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -O2 -mattr=hwdiv-arm \
-; RUN: | FileCheck %s --check-prefix=DIS
-
-define internal i32 @UdivTwoRegs(i32 %a, i32 %b) {
- %v = udiv i32 %a, %b
- ret i32 %v
-}
-
-; ASM-LABEL:UdivTwoRegs:
-; ASM-NEXT:.LUdivTwoRegs$__0:
-; ASM-NEXT: tst r1, r1
-; ASM-NEXT: bne .LUdivTwoRegs$local$__0
-; ASM-NEXT: .long 0xe7fedef0
-; ASM-NEXT:.LUdivTwoRegs$local$__0:
-; ASM-NEXT: udiv r0, r0, r1
-; ASM-NEXT: bx lr
-
-; DIS-LABEL:00000000 <UdivTwoRegs>:
-; DIS-NEXT: 0: e1110001
-; DIS-NEXT: 4: 1a000000
-; DIS-NEXT: 8: e7fedef0
-; DIS-NEXT: c: e730f110
-; DIS-NEXT: 10: e12fff1e
-
-; IASM-LABEL:UdivTwoRegs:
-; IASM-NEXT:.LUdivTwoRegs$__0:
-
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x11
-; IASM-NEXT: .byte 0xe1
-
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x1a
-
-; IASM-NEXT: .byte 0xf0
-; IASM-NEXT: .byte 0xde
-; IASM-NEXT: .byte 0xfe
-; IASM-NEXT: .byte 0xe7
-
-; IASM-NEXT:.LUdivTwoRegs$local$__0:
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0xf1
-; IASM-NEXT: .byte 0x30
-; IASM-NEXT: .byte 0xe7
-
-; IASM-NEXT: .byte 0x1e
-; IASM-NEXT: .byte 0xff
-; IASM-NEXT: .byte 0x2f
-; IASM-NEXT: .byte 0xe1
diff --git a/third_party/subzero/tests_lit/assembler/arm32/uxtb.ll b/third_party/subzero/tests_lit/assembler/arm32/uxtb.ll
deleted file mode 100644
index e140283..0000000
--- a/third_party/subzero/tests_lit/assembler/arm32/uxtb.ll
+++ /dev/null
@@ -1,89 +0,0 @@
-; Test the UXTB and UXTH instructions.
-
-; NOTE: We use -O2 to get rid of memory stores.
-
-; REQUIRES: allow_dump
-
-; Compile using standalone assembler.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -O2 \
-; RUN: | FileCheck %s --check-prefix=ASM
-
-; Show bytes in assembled standalone code.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -O2 | FileCheck %s --check-prefix=DIS
-
-; Compile using integrated assembler.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -O2 \
-; RUN: | FileCheck %s --check-prefix=IASM
-
-; Show bytes in assembled integrated code.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -O2 | FileCheck %s --check-prefix=DIS
-
-define internal i32 @_Z7testAddhh(i32 %a, i32 %b) {
-; ASM-LABEL: _Z7testAddhh:
-; DIS-LABEL: 00000000 <_Z7testAddhh>:
-; IASM-LABEL: _Z7testAddhh:
-
-entry:
-
-; ASM-NEXT: .L_Z7testAddhh$entry:
-; IASM-NEXT: .L_Z7testAddhh$entry:
-
- %a.arg_trunc = trunc i32 %a to i8
- %conv = zext i8 %a.arg_trunc to i32
-
-; ASM-NEXT: uxtb r0, r0
-; DIS-NEXT: 0: e6ef0070
-; IASM-NEXT: .byte 0x70
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xef
-; IASM-NEXT: .byte 0xe6
-
- %b.arg_trunc = trunc i32 %b to i8
- %conv1 = zext i8 %b.arg_trunc to i32
-
-; ASM-NEXT: uxtb r1, r1
-; DIS-NEXT: 4: e6ef1071
-; IASM-NEXT: .byte 0x71
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0xef
-; IASM-NEXT: .byte 0xe6
-
- %add = add i32 %conv1, %conv
-
-; ASM-NEXT: add r1, r1, r0
-; DIS-NEXT: 8: e0811000
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0x81
-; IASM-NEXT: .byte 0xe0
-
- %conv2 = trunc i32 %add to i16
- %conv2.ret_ext = zext i16 %conv2 to i32
-
-; ASM-NEXT: uxth r1, r1
-; DIS-NEXT: c: e6ff1071
-; IASM-NEXT: .byte 0x71
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0xff
-; IASM-NEXT: .byte 0xe6
-
- ret i32 %conv2.ret_ext
-
-; ASM-NEXT: mov r0, r1
-; DIS-NEXT: 10: e1a00001
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xa0
-; IASM-NEXT: .byte 0xe1
-
-
-; ASM-NEXT: bx lr
-; DIS-NEXT: 14: e12fff1e
-; IASM-NEXT: .byte 0x1e
-; IASM-NEXT: .byte 0xff
-; IASM-NEXT: .byte 0x2f
-; IASM-NEXT: .byte 0xe1
-
-}
diff --git a/third_party/subzero/tests_lit/assembler/arm32/vabs-vec.ll b/third_party/subzero/tests_lit/assembler/arm32/vabs-vec.ll
deleted file mode 100644
index fc47d39..0000000
--- a/third_party/subzero/tests_lit/assembler/arm32/vabs-vec.ll
+++ /dev/null
@@ -1,41 +0,0 @@
-; Show that we know how to translate the fabs intrinsic on float vectors.
-
-; REQUIRES: allow_dump
-
-; Compile using standalone assembler.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -Om1 \
-; RUN: -reg-use q5 \
-; RUN: | FileCheck %s --check-prefix=ASM
-
-; Show bytes in assembled standalone code.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -Om1 \
-; RUN: -reg-use q5 \
-; RUN: | FileCheck %s --check-prefix=DIS
-
-; Compile using integrated assembler.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -Om1 \
-; RUN: -reg-use q5 \
-; RUN: | FileCheck %s --check-prefix=IASM
-
-; Show bytes in assembled integrated code.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -Om1 \
-; RUN: -reg-use q5 \
-; RUN: | FileCheck %s --check-prefix=DIS
-
-declare <4 x float> @llvm.fabs.v4f32(<4 x float>)
-
-define internal <4 x float> @_Z6myFabsDv4_f(<4 x float> %a) {
-; ASM-LABEL: _Z6myFabsDv4_f:
-; DIS-LABEL: {{.+}} <_Z6myFabsDv4_f>:
-; IASM-LABEL: _Z6myFabsDv4_f:
-
- %x = call <4 x float> @llvm.fabs.v4f32(<4 x float> %a)
-
-; ASM: vabs.f32 q5, q5
-; DIS: {{.+}}: f3b9a74a
-; IASM-NOT: vabs.f32
-
- ret <4 x float> %x
-}
diff --git a/third_party/subzero/tests_lit/assembler/arm32/vabs.ll b/third_party/subzero/tests_lit/assembler/arm32/vabs.ll
deleted file mode 100644
index f773673..0000000
--- a/third_party/subzero/tests_lit/assembler/arm32/vabs.ll
+++ /dev/null
@@ -1,74 +0,0 @@
-; Show that we translate intrinsics for fabs on float, double and float vectors.
-
-; REQUIRES: allow_dump
-
-; Compile using standalone assembler.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -Om1 \
-; RUN: -reg-use s20,d22 \
-; RUN: | FileCheck %s --check-prefix=ASM
-
-; Show bytes in assembled standalone code.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -Om1 \
-; RUN: -reg-use s20,d22 \
-; RUN: | FileCheck %s --check-prefix=DIS
-
-; Compile using integrated assembler.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -Om1 \
-; RUN: -reg-use s20,d22 \
-; RUN: | FileCheck %s --check-prefix=IASM
-
-; Show bytes in assembled integrated code.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -Om1 \
-; RUN: -reg-use s20,d22 \
-; RUN: | FileCheck %s --check-prefix=DIS
-
-declare float @llvm.fabs.f32(float)
-declare double @llvm.fabs.f64(double)
-declare <4 x float> @llvm.fabs.v4f32(<4 x float>)
-
-define internal float @test_fabs_float(float %x) {
-; ASM-LABEL: test_fabs_float:
-; DIS-LABEL: 00000000 <test_fabs_float>:
-; IASM-LABEL: test_fabs_float:
-
-entry:
- %r = call float @llvm.fabs.f32(float %x)
-
-; ASM: vabs.f32 s20, s20
-; DIS: 10: eeb0aaca
-; IASM-NOT: vabs.f32
-
- ret float %r
-}
-
-define internal double @test_fabs_double(double %x) {
-; ASM-LABEL: test_fabs_double:
-; DIS-LABEL: 00000030 <test_fabs_double>:
-; IASM-LABEL: test_fabs_double:
-
-entry:
- %r = call double @llvm.fabs.f64(double %x)
-
-; ASM: vabs.f64 d22, d22
-; DIS: 3c: eef06be6
-; IASM-NOT: vabs.64
-
- ret double %r
-}
-
-define internal <4 x float> @test_fabs_4float(<4 x float> %x) {
-; ASM-LABEL: test_fabs_4float:
-; DIS-LABEL: 00000050 <test_fabs_4float>:
-; IASM-LABEL: test_fabs_4float:
-
-entry:
- %r = call <4 x float> @llvm.fabs.v4f32(<4 x float> %x)
-
-; ASM: vabs.f32 q0, q0
-; DIS: 60: f3b90740
-; IASM-NOT: vabs.f32
-
- ret <4 x float> %r
-}
diff --git a/third_party/subzero/tests_lit/assembler/arm32/vadd.ll b/third_party/subzero/tests_lit/assembler/arm32/vadd.ll
deleted file mode 100644
index b219a71..0000000
--- a/third_party/subzero/tests_lit/assembler/arm32/vadd.ll
+++ /dev/null
@@ -1,58 +0,0 @@
-; Show that we know how to translate vadd.
-
-; NOTE: Restricts S and D registers to ones that will better test S/D
-; register encodings.
-
-; REQUIRES: allow_dump
-
-; Compile using standalone assembler.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -Om1 \
-; RUN: -reg-use s20,s22,d20,d22 \
-; RUN: | FileCheck %s --check-prefix=ASM
-
-; Show bytes in assembled standalone code.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -Om1 \
-; RUN: -reg-use s20,s22,d20,d22 \
-; RUN: | FileCheck %s --check-prefix=DIS
-
-; Compile using integrated assembler.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -Om1 \
-; RUN: -reg-use s20,s22,d20,d22 \
-; RUN: | FileCheck %s --check-prefix=IASM
-
-; Show bytes in assembled integrated code.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -Om1 \
-; RUN: -reg-use s20,s22,d20,d22 \
-; RUN: | FileCheck %s --check-prefix=DIS
-
-define internal float @testVaddFloat(float %v1, float %v2) {
-; ASM-LABEL: testVaddFloat:
-; DIS-LABEL: 00000000 <testVaddFloat>:
-; IASM-LABEL: testVaddFloat:
-
-entry:
- %res = fadd float %v1, %v2
-
-; ASM: vadd.f32 s20, s20, s22
-; DIS: 1c: ee3aaa0b
-; IASM-NOT: vadd
-
- ret float %res
-}
-
-define internal double @testVaddDouble(double %v1, double %v2) {
-; ASM-LABEL: testVaddDouble:
-; DIS-LABEL: 00000040 <testVaddDouble>:
-; IASM-LABEL: .LtestVaddDouble$entry:
-
-entry:
- %res = fadd double %v1, %v2
-
-; ASM: vadd.f64 d20, d20, d22
-; DIS: 54: ee744ba6
-; IASM-NOT: vadd
-
- ret double %res
-}
diff --git a/third_party/subzero/tests_lit/assembler/arm32/vcmp.ll b/third_party/subzero/tests_lit/assembler/arm32/vcmp.ll
deleted file mode 100644
index cb1fb10..0000000
--- a/third_party/subzero/tests_lit/assembler/arm32/vcmp.ll
+++ /dev/null
@@ -1,98 +0,0 @@
-; Show that we know how to translate vcmp.
-
-; REQUIRES: allow_dump
-
-; TODO(kschimpf): Use include registers for compare instructions, so that the
-; test is less brittle.
-
-; Compile using standalone assembler.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -Om1 \
-; RUN: | FileCheck %s --check-prefix=ASM
-
-; Show bytes in assembled standalone code.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -Om1 | FileCheck %s --check-prefix=DIS
-
-; Compile using integrated assembler.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -Om1 \
-; RUN: | FileCheck %s --check-prefix=IASM
-
-; Show bytes in assembled integrated code.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -Om1 | FileCheck %s --check-prefix=DIS
-
-define internal i32 @vcmpFloat(float %v1, float %v2) {
-; ASM-LABEL: vcmpFloat:
-; DIS-LABEL: 00000000 <vcmpFloat>:
-; IASM-LABEL: vcmpFloat:
-
-entry:
-; ASM-NEXT: .LvcmpFloat$entry:
-; IASM-NEXT: .LvcmpFloat$entry:
-
- %cmp = fcmp olt float %v1, %v2
-
-; ASM: vcmp.f32 s0, s1
-; DIS: 14: eeb40a60
-; IASM-NOT: vcmp
-
- %res = zext i1 %cmp to i32
- ret i32 %res
-}
-
-define internal i32 @vcmpFloatToZero(float %v) {
-; ASM-LABEL: vcmpFloatToZero:
-; DIS-LABEL: 00000040 <vcmpFloatToZero>:
-; IASM-LABEL: vcmpFloatToZero:
-
-entry:
-; ASM-NEXT: .LvcmpFloatToZero$entry:
-; IASM-NEXT: .LvcmpFloatToZero$entry:
-
- %cmp = fcmp olt float %v, 0.0
-
-; ASM: vcmp.f32 s0, #0.0
-; DIS: 4c: eeb50a40
-; IASM-NOT: vcmp
-
- %res = zext i1 %cmp to i32
- ret i32 %res
-}
-
-define internal i32 @vcmpDouble(double %v1, double %v2) {
-; ASM-LABEL: vcmpDouble:
-; DIS-LABEL: 00000080 <vcmpDouble>:
-; IASM-LABEL: vcmpDouble:
-
-entry:
-; ASM-NEXT: .LvcmpDouble$entry:
-; IASM-NEXT: .LvcmpDouble$entry:
-
- %cmp = fcmp olt double %v1, %v2
-
-; ASM: vcmp.f64 d0, d1
-; DIS: 94: eeb40b41
-; IASM-NOT: vcmp
-
- %res = zext i1 %cmp to i32
- ret i32 %res
-}
-
-define internal i32 @vcmpDoubleToZero(double %v) {
-; ASM-LABEL: vcmpDoubleToZero:
-; DIS-LABEL: 000000c0 <vcmpDoubleToZero>:
-; IASM-LABEL: vcmpDoubleToZero:
-
-entry:
-; ASM-NEXT: .LvcmpDoubleToZero$entry:
-; IASM-NEXT: .LvcmpDoubleToZero$entry:
-
- %cmp = fcmp olt double %v, 0.0
-
-; ASM: vcmp.f64 d0, #0.0
-; DIS: cc: eeb50b40
-; IASM-NOT: vcmp
-
- %res = zext i1 %cmp to i32
- ret i32 %res
-}
diff --git a/third_party/subzero/tests_lit/assembler/arm32/vcvt.f32.s32.ll b/third_party/subzero/tests_lit/assembler/arm32/vcvt.f32.s32.ll
deleted file mode 100644
index 8481e87..0000000
--- a/third_party/subzero/tests_lit/assembler/arm32/vcvt.f32.s32.ll
+++ /dev/null
@@ -1,52 +0,0 @@
-; Show that we know how to translate converting signed integer to floast.
-
-; REQUIRES: allow_dump
-
-; Compile using standalone assembler.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -Om1 \
-; RUN: --reg-use=s20 | FileCheck %s --check-prefix=ASM
-
-; Show bytes in assembled standalone code.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -Om1 --reg-use=s20 | FileCheck %s --check-prefix=DIS
-
-; Compile using integrated assembler.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -Om1 \
-; RUN: --reg-use=s20 \
-; RUN: | FileCheck %s --check-prefix=IASM
-
-; Show bytes in assembled integrated code.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -Om1 --reg-use=s20 | FileCheck %s --check-prefix=DIS
-
-define internal float @SignedIntToFloat() {
-; ASM-LABEL: SignedIntToFloat:
-; DIS-LABEL: 00000000 <SignedIntToFloat>:
-; IASM-LABEL: SignedIntToFloat:
-
-entry:
-; ASM: .LSignedIntToFloat$entry:
-; IASM: .LSignedIntToFloat$entry:
-
- %v = sitofp i32 17 to float
-
-; ASM: vcvt.f32.s32 s20, s20
-; DIS: 10: eeb8aaca
-; IASM-NOT: vcvt
-
- ret float %v
-}
-
-define internal <4 x float> @IntVecToFloatVec(<4 x i32> %a) {
-; ASM-LABEL: IntVecToFloatVec:
-; DIS-LABEL: 00000030 <IntVecToFloatVec>:
-; IASM-LABEL: IntVecToFloatVec:
-
- %v = sitofp <4 x i32> %a to <4 x float>
-
-; ASM: vcvt.f32.s32 q0, q0
-; DIS: 40: f3bb0640
-; IASM-NOT: vcvt
-
- ret <4 x float> %v
-}
diff --git a/third_party/subzero/tests_lit/assembler/arm32/vcvt.f32.u32.ll b/third_party/subzero/tests_lit/assembler/arm32/vcvt.f32.u32.ll
deleted file mode 100644
index 56fd7c8..0000000
--- a/third_party/subzero/tests_lit/assembler/arm32/vcvt.f32.u32.ll
+++ /dev/null
@@ -1,52 +0,0 @@
-; Show that we know how to translate converting unsigned integer to float.
-
-; REQUIRES: allow_dump
-
-; Compile using standalone assembler.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -Om1 \
-; RUN: --reg-use=s20 | FileCheck %s --check-prefix=ASM
-
-; Show bytes in assembled standalone code.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -Om1 --reg-use=s20 | FileCheck %s --check-prefix=DIS
-
-; Compile using integrated assembler.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -Om1 \
-; RUN: --reg-use=s20 \
-; RUN: | FileCheck %s --check-prefix=IASM
-
-; Show bytes in assembled integrated code.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -Om1 --reg-use=s20 | FileCheck %s --check-prefix=DIS
-
-define internal float @SignedIntToFloat() {
-; ASM-LABEL: SignedIntToFloat:
-; DIS-LABEL: 00000000 <SignedIntToFloat>:
-; IASM-LABEL: SignedIntToFloat:
-
-entry:
-; ASM: .LSignedIntToFloat$entry:
-; IASM: .LSignedIntToFloat$entry:
-
- %v = uitofp i32 17 to float
-
-; ASM: vcvt.f32.u32 s20, s20
-; DIS: 10: eeb8aa4a
-; IASM-NOT: vcvt
-
- ret float %v
-}
-
-define internal <4 x float> @UIntVecToFloatVec(<4 x i32> %a) {
-; ASM-LABEL: UIntVecToFloatVec:
-; DIS-LABEL: 00000030 <UIntVecToFloatVec>:
-; IASM-LABEL: UIntVecToFloatVec:
-
- %v = uitofp <4 x i32> %a to <4 x float>
-
-; ASM: vcvt.f32.u32 q0, q0
-; DIS: 40: f3bb06c0
-; IASM-NOT: vcvt
-
- ret <4 x float> %v
-}
diff --git a/third_party/subzero/tests_lit/assembler/arm32/vcvt.f64.s32.ll b/third_party/subzero/tests_lit/assembler/arm32/vcvt.f64.s32.ll
deleted file mode 100644
index 34e94ef..0000000
--- a/third_party/subzero/tests_lit/assembler/arm32/vcvt.f64.s32.ll
+++ /dev/null
@@ -1,38 +0,0 @@
-; Show that we know how to translate converting signed integer to double.
-
-; REQUIRES: allow_dump
-
-; Compile using standalone assembler.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -Om1 \
-; RUN: --reg-use=s20 | FileCheck %s --check-prefix=ASM
-
-; Show bytes in assembled standalone code.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -Om1 --reg-use=s20 | FileCheck %s --check-prefix=DIS
-
-; Compile using integrated assembler.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -Om1 \
-; RUN: --reg-use=s20 \
-; RUN: | FileCheck %s --check-prefix=IASM
-
-; Show bytes in assembled integrated code.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -Om1 --reg-use=s20 | FileCheck %s --check-prefix=DIS
-
-define internal double @SignedIntToDouble() {
-; ASM-LABEL: SignedIntToDouble:
-; DIS-LABEL: 00000000 <SignedIntToDouble>:
-; IASM-LABEL: SignedIntToDouble:
-
-entry:
-; ASM: .LSignedIntToDouble$entry:
-; IASM: .LSignedIntToDouble$entry:
-
- %v = sitofp i32 17 to double
-
-; ASM: vcvt.f64.s32 d0, s20
-; DIS: 10: eeb80bca
-; IASM-NOT: vcvt
-
- ret double %v
-}
diff --git a/third_party/subzero/tests_lit/assembler/arm32/vcvt.f64.u32.ll b/third_party/subzero/tests_lit/assembler/arm32/vcvt.f64.u32.ll
deleted file mode 100644
index 12a24a2..0000000
--- a/third_party/subzero/tests_lit/assembler/arm32/vcvt.f64.u32.ll
+++ /dev/null
@@ -1,38 +0,0 @@
-; Show that we know how to translate converting unsigned integer to double.
-
-; REQUIRES: allow_dump
-
-; Compile using standalone assembler.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -Om1 \
-; RUN: --reg-use=s20 | FileCheck %s --check-prefix=ASM
-
-; Show bytes in assembled standalone code.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -Om1 --reg-use=s20 | FileCheck %s --check-prefix=DIS
-
-; Compile using integrated assembler.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -Om1 \
-; RUN: --reg-use=s20 \
-; RUN: | FileCheck %s --check-prefix=IASM
-
-; Show bytes in assembled integrated code.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -Om1 --reg-use=s20 | FileCheck %s --check-prefix=DIS
-
-define internal double @UnsignedIntToDouble() {
-; ASM-LABEL: UnsignedIntToDouble:
-; DIS-LABEL: 00000000 <UnsignedIntToDouble>:
-; IASM-LABEL: UnsignedIntToDouble:
-
-entry:
-; ASM: .LUnsignedIntToDouble$entry:
-; IASM: .LUnsignedIntToDouble$entry:
-
- %v = uitofp i32 17 to double
-
-; ASM: vcvt.f64.u32 d0, s20
-; DIS: 10: eeb80b4a
-; IASM-NOT: vcvt
-
- ret double %v
-}
diff --git a/third_party/subzero/tests_lit/assembler/arm32/vcvt.s32.f32.ll b/third_party/subzero/tests_lit/assembler/arm32/vcvt.s32.f32.ll
deleted file mode 100644
index 656ba04..0000000
--- a/third_party/subzero/tests_lit/assembler/arm32/vcvt.s32.f32.ll
+++ /dev/null
@@ -1,52 +0,0 @@
-; Show that we know how to translate converting float to signed integer.
-
-; REQUIRES: allow_dump
-
-; Compile using standalone assembler.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -Om1 \
-; RUN: --reg-use=s20 | FileCheck %s --check-prefix=ASM
-
-; Show bytes in assembled standalone code.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -Om1 --reg-use=s20 | FileCheck %s --check-prefix=DIS
-
-; Compile using integrated assembler.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -Om1 \
-; RUN: --reg-use=s20 \
-; RUN: | FileCheck %s --check-prefix=IASM
-
-; Show bytes in assembled integrated code.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -Om1 --reg-use=s20 | FileCheck %s --check-prefix=DIS
-
-define internal i32 @FloatToSignedInt() {
-; ASM-LABEL: FloatToSignedInt:
-; DIS-LABEL: 00000000 <FloatToSignedInt>:
-; IASM-LABEL: FloatToSignedInt:
-
-entry:
-; ASM-NEXT: .LFloatToSignedInt$entry:
-; IASM-NEXT: .LFloatToSignedInt$entry:
-
- %v = fptosi float 0.0 to i32
-
-; ASM: vcvt.s32.f32 s20, s20
-; DIS: 14: eebdaaca
-; IASM-NOT: vcvt
-
- ret i32 %v
-}
-
-define internal <4 x i32> @FloatVecToIntVec(<4 x float> %a) {
-; ASM-LABEL: FloatVecToIntVec:
-; DIS-LABEL: 00000030 <FloatVecToIntVec>:
-; IASM-LABEL: FloatVecToIntVec:
-
- %v = fptosi <4 x float> %a to <4 x i32>
-
-; ASM: vcvt.s32.f32 q0, q0
-; DIS: 40: f3bb0740
-; IASM-NOT: vcvt
-
- ret <4 x i32> %v
-}
diff --git a/third_party/subzero/tests_lit/assembler/arm32/vcvt.s32.f64.ll b/third_party/subzero/tests_lit/assembler/arm32/vcvt.s32.f64.ll
deleted file mode 100644
index 5b60bce..0000000
--- a/third_party/subzero/tests_lit/assembler/arm32/vcvt.s32.f64.ll
+++ /dev/null
@@ -1,38 +0,0 @@
-; Show that we know how to translate converting double to signed integer.
-
-; REQUIRES: allow_dump
-
-; Compile using standalone assembler.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -Om1 \
-; RUN: --reg-use=s20 | FileCheck %s --check-prefix=ASM
-
-; Show bytes in assembled standalone code.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -Om1 --reg-use=s20 | FileCheck %s --check-prefix=DIS
-
-; Compile using integrated assembler.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -Om1 \
-; RUN: --reg-use=s20 \
-; RUN: | FileCheck %s --check-prefix=IASM
-
-; Show bytes in assembled integrated code.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -Om1 --reg-use=s20 | FileCheck %s --check-prefix=DIS
-
-define internal i32 @DoubleToSignedInt() {
-; ASM-LABEL: DoubleToSignedInt:
-; DIS-LABEL: 00000000 <DoubleToSignedInt>:
-; IASM-LABEL: DoubleToSignedInt:
-
-entry:
-; ASM: .LDoubleToSignedInt$entry:
-; IASM: .LDoubleToSignedInt$entry:
-
- %v = fptosi double 0.0 to i32
-
-; ASM: vcvt.s32.f64 s20, d0
-; DIS: c: eebdabc0
-; IASM-NOT: vcvt
-
- ret i32 %v
-}
diff --git a/third_party/subzero/tests_lit/assembler/arm32/vcvt.u32.f32.ll b/third_party/subzero/tests_lit/assembler/arm32/vcvt.u32.f32.ll
deleted file mode 100644
index 2fae0f5..0000000
--- a/third_party/subzero/tests_lit/assembler/arm32/vcvt.u32.f32.ll
+++ /dev/null
@@ -1,51 +0,0 @@
-; Show that we know how to translate converting float to unsigned integer.
-
-; REQUIRES: allow_dump
-
-; Compile using standalone assembler.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -Om1 \
-; RUN: --reg-use=s20 | FileCheck %s --check-prefix=ASM
-
-; Show bytes in assembled standalone code.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -Om1 --reg-use=s20 | FileCheck %s --check-prefix=DIS
-
-; Compile using integrated assembler.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -Om1 \
-; RUN: --reg-use=s20 \
-; RUN: | FileCheck %s --check-prefix=IASM
-
-; Show bytes in assembled integrated code.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -Om1 --reg-use=s20 | FileCheck %s --check-prefix=DIS
-
-define internal i32 @FloatToUnsignedInt() {
-; ASM-LABEL: FloatToUnsignedInt:
-; DIS-LABEL: 00000000 <FloatToUnsignedInt>:
-; IASM-LABEL: FloatToUnsignedInt:
-
-entry:
-; ASM-NEXT: .LFloatToUnsignedInt$entry:
-; IASM-NEXT: .LFloatToUnsignedInt$entry:
-
- %v = fptoui float 0.0 to i32
-; ASM: vcvt.u32.f32 s20, s20
-; DIS: 14: eebcaaca
-; IASM-NOT: vcvt
-
- ret i32 %v
-}
-
-define internal <4 x i32> @FloatVecToUIntVec(<4 x float> %a) {
-; ASM-LABEL: FloatVecToUIntVec:
-; DIS-LABEL: 00000030 <FloatVecToUIntVec>:
-; IASM-LABEL: FloatVecToUIntVec:
-
- %v = fptoui <4 x float> %a to <4 x i32>
-
-; ASM: vcvt.u32.f32 q0, q0
-; DIS: 40: f3bb07c0
-; IASM-NOT: vcvt
-
- ret <4 x i32> %v
-}
diff --git a/third_party/subzero/tests_lit/assembler/arm32/vcvt.u32.f64.ll b/third_party/subzero/tests_lit/assembler/arm32/vcvt.u32.f64.ll
deleted file mode 100644
index bc4ed78..0000000
--- a/third_party/subzero/tests_lit/assembler/arm32/vcvt.u32.f64.ll
+++ /dev/null
@@ -1,36 +0,0 @@
-; Show that we know how to translate converting double to unsigned integer.
-
-; REQUIRES: allow_dump
-
-; Compile using standalone assembler.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -Om1 \
-; RUN: --reg-use=s20 | FileCheck %s --check-prefix=ASM
-
-; Show bytes in assembled standalone code.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -Om1 --reg-use=s20 | FileCheck %s --check-prefix=DIS
-
-; Compile using integrated assembler.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -Om1 \
-; RUN: --reg-use=s20 \
-; RUN: | FileCheck %s --check-prefix=IASM
-
-; Show bytes in assembled integrated code.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -Om1 --reg-use=s20 | FileCheck %s --check-prefix=DIS
-
-define internal i32 @DoubleToUnsignedInt() {
-; ASM-LABEL: DoubleToUnsignedInt:
-; DIS-LABEL: 00000000 <DoubleToUnsignedInt>:
-
-entry:
-; ASM: .LDoubleToUnsignedInt$entry:
-
- %v = fptoui double 0.0 to i32
-
-; ASM: vcvt.u32.f64 s20, d0
-; DIS: c: eebcabc0
-; IASM-NOT: vcvt
-
- ret i32 %v
-}
diff --git a/third_party/subzero/tests_lit/assembler/arm32/vcvt_f32_f64.ll b/third_party/subzero/tests_lit/assembler/arm32/vcvt_f32_f64.ll
deleted file mode 100644
index e320588..0000000
--- a/third_party/subzero/tests_lit/assembler/arm32/vcvt_f32_f64.ll
+++ /dev/null
@@ -1,62 +0,0 @@
-; Show that we know how to translate vcvt between float and double.
-
-; NOTE: We use -O2 to get rid of memory stores.
-
-; REQUIRES: allow_dump
-
-; Compile using standalone assembler.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -O2 \
-; RUN: | FileCheck %s --check-prefix=ASM
-
-; Show bytes in assembled standalone code.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -O2 | FileCheck %s --check-prefix=DIS
-
-; Compile using integrated assembler.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -O2 \
-; RUN: | FileCheck %s --check-prefix=IASM
-
-; Show bytes in assembled integrated code.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -O2 | FileCheck %s --check-prefix=DIS
-
-define internal double @testVcvtFloatToDouble(float %v) {
-; ASM-LABEL: testVcvtFloatToDouble:
-; DIS-LABEL: 00000000 <testVcvtFloatToDouble>:
-; IASM-LABEL: testVcvtFloatToDouble:
-
-entry:
-; ASM-NEXT: .LtestVcvtFloatToDouble$entry:
-; IASM-NEXT: .LtestVcvtFloatToDouble$entry:
-
- %res = fpext float %v to double
-
-; ASM-NEXT: vcvt.f64.f32 d0, s0
-; DIS-NEXT: 0: eeb70ac0
-; IASM-NEXT: .byte 0xc0
-; IASM-NEXT: .byte 0xa
-; IASM-NEXT: .byte 0xb7
-; IASM-NEXT: .byte 0xee
-
- ret double %res
-}
-
-define internal float @testVcvtDoubleToFloat(double %v) {
-; ASM-LABEL: testVcvtDoubleToFloat:
-; DIS-LABEL: 00000010 <testVcvtDoubleToFloat>:
-; IASM-LABEL: testVcvtDoubleToFloat:
-
-entry:
-; ASM-NEXT: .LtestVcvtDoubleToFloat$entry:
-; IASM-NEXT: .LtestVcvtDoubleToFloat$entry:
-
- %res = fptrunc double %v to float
-; ASM-NEXT: vcvt.f32.f64 s0, d0
-; DIS-NEXT: 10: eeb70bc0
-; IASM-NEXT: .byte 0xc0
-; IASM-NEXT: .byte 0xb
-; IASM-NEXT: .byte 0xb7
-; IASM-NEXT: .byte 0xee
-
- ret float %res
-}
diff --git a/third_party/subzero/tests_lit/assembler/arm32/vdiv.ll b/third_party/subzero/tests_lit/assembler/arm32/vdiv.ll
deleted file mode 100644
index 774d183..0000000
--- a/third_party/subzero/tests_lit/assembler/arm32/vdiv.ll
+++ /dev/null
@@ -1,63 +0,0 @@
-; Show that we know how to translate vdiv.
-
-; NOTE: We use -O2 to get rid of memory stores.
-
-; REQUIRES: allow_dump
-
-; Compile using standalone assembler.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -O2 \
-; RUN: | FileCheck %s --check-prefix=ASM
-
-; Show bytes in assembled standalone code.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -O2 | FileCheck %s --check-prefix=DIS
-
-; Compile using integrated assembler.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -O2 \
-; RUN: | FileCheck %s --check-prefix=IASM
-
-; Show bytes in assembled integrated code.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -O2 | FileCheck %s --check-prefix=DIS
-
-define internal float @testVdivFloat(float %v1, float %v2) {
-; ASM-LABEL: testVdivFloat:
-; DIS-LABEL: 00000000 <testVdivFloat>:
-; IASM-LABEL: testVdivFloat:
-
-entry:
-; ASM-NEXT: .LtestVdivFloat$entry:
-; IASM-NEXT: .LtestVdivFloat$entry:
-
- %res = fdiv float %v1, %v2
-
-; ASM-NEXT: vdiv.f32 s0, s0, s1
-; DIS-NEXT: 0: ee800a20
-; IASM-NEXT: .byte 0x20
-; IASM-NEXT: .byte 0xa
-; IASM-NEXT: .byte 0x80
-; IASM-NEXT: .byte 0xee
-
- ret float %res
-}
-
-define internal double @testVdivDouble(double %v1, double %v2) {
-; ASM-LABEL: testVdivDouble:
-; DIS-LABEL: 00000010 <testVdivDouble>:
-; IASM-LABEL: testVdivDouble:
-
-entry:
-; ASM-NEXT: .LtestVdivDouble$entry:
-; IASM-NEXT: .LtestVdivDouble$entry:
-
- %res = fdiv double %v1, %v2
-
-; ASM-NEXT: vdiv.f64 d0, d0, d1
-; DIS-NEXT: 10: ee800b01
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0xb
-; IASM-NEXT: .byte 0x80
-; IASM-NEXT: .byte 0xee
-
- ret double %res
-}
diff --git a/third_party/subzero/tests_lit/assembler/arm32/vec-move.ll b/third_party/subzero/tests_lit/assembler/arm32/vec-move.ll
deleted file mode 100644
index df8d906..0000000
--- a/third_party/subzero/tests_lit/assembler/arm32/vec-move.ll
+++ /dev/null
@@ -1,41 +0,0 @@
-; Test that we handle a vector move.
-
-; NOTE: We use -O2 to force a vector move for the return value.
-
-; REQUIRES: allow_dump
-
-; Compile using standalone assembler.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -O2 \
-; RUN: | FileCheck %s --check-prefix=ASM
-
-; Show bytes in assembled standalone code.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -O2 \
-; RUN: | FileCheck %s --check-prefix=DIS
-
-; Compile using integrated assembler.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -O2 \
-; RUN: | FileCheck %s --check-prefix=IASM
-
-; Show bytes in assembled integrated code.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -O2 \
-; RUN: | FileCheck %s --check-prefix=DIS
-
-
-define internal <4 x float> @testMoveVector(<4 x i32> %a, <4 x i32> %b) {
-; ASM-LABEL: testMoveVector:
-; DIS-LABEL:{{.+}} <testMoveVector>:
-; IASM-LABEL: testMoveVector:
-
-entry:
- %0 = bitcast <4 x i32> %b to <4 x float>
- ret <4 x float> %0
-
-; ASM: vmov.f32 q0, q1
-; The integrated assembler emits a vorr instead of a vmov.
-; DIS: 0: f2220152
-; IASM-NOT: vmov.f32 q0, q1
-; IASM-NOT: vorr q0, q1, q1
-
-}
diff --git a/third_party/subzero/tests_lit/assembler/arm32/vec-sh-imm.ll b/third_party/subzero/tests_lit/assembler/arm32/vec-sh-imm.ll
deleted file mode 100644
index c2c5ebc..0000000
--- a/third_party/subzero/tests_lit/assembler/arm32/vec-sh-imm.ll
+++ /dev/null
@@ -1,71 +0,0 @@
-; Show that we know how to translate vshl and vshr with immediate shift amounts.
-; We abuse sign extension of vectors of i1 because that's the only way to force
-; Subzero to emit these instructions.
-
-; NOTE: We use -O2 to get rid of memory stores.
-
-; REQUIRES: allow_dump
-
-; Compile using standalone assembler.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -O2 \
-; RUN: | FileCheck %s --check-prefix=ASM
-
-; Show bytes in assembled standalone code.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -O2 | FileCheck %s --check-prefix=DIS
-
-; Compile using integrated assembler.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -O2 \
-; RUN: | FileCheck %s --check-prefix=IASM
-
-; Show bytes in assembled integrated code.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -O2 | FileCheck %s --check-prefix=DIS
-
-define internal <4 x i32> @SextV4I1(<4 x i32> %a) {
-; ASM-LABEL:SextV4I1
-; DIS-LABEL:00000000 <SextV4I1>:
-; IASM-LABEL:SextV4I1:
-
- %trunc = trunc <4 x i32> %a to <4 x i1>
- %sext = sext <4 x i1> %trunc to <4 x i32>
- ret <4 x i32> %sext
-; ASM: vshl.u32 {{.*}}, #31
-; ASM-NEXT: vshr.s32 {{.*}}, #31
-; DIS: 0: f2bf0550
-; DIS-NEXT: 4: f2a10050
-; IASM-NOT: vshl
-; IASM-NOT: vshr
-}
-
-define internal <8 x i16> @SextV8I1(<8 x i16> %a) {
-; ASM-LABEL:SextV8I1
-; DIS-LABEL:00000010 <SextV8I1>:
-; IASM-LABEL:SextV8I1:
-
- %trunc = trunc <8 x i16> %a to <8 x i1>
- %sext = sext <8 x i1> %trunc to <8 x i16>
- ret <8 x i16> %sext
-; ASM: vshl.u16 {{.*}}, #15
-; ASM-NEXT: vshr.s16 {{.*}}, #15
-; DIS: 10: f29f0550
-; DIS-NEXT: 14: f2910050
-; IASM-NOT: vshl
-; IASM-NOT: vshr
-}
-
-define internal <16 x i8> @SextV16I1(<16 x i8> %a) {
-; ASM-LABEL:SextV16I1
-; DIS-LABEL:00000020 <SextV16I1>:
-; IASM-LABEL:SextV16I1:
-
- %trunc = trunc <16 x i8> %a to <16 x i1>
- %sext = sext <16 x i1> %trunc to <16 x i8>
- ret <16 x i8> %sext
-; ASM: vshl.u8 {{.*}}, #7
-; ASM-NEXT: vshr.s8 {{.*}}, #7
-; DIS: 20: f28f0550
-; DIS-NEXT: 24: f2890050
-; IASM-NOT: vshl
-; IASM-NOT: vshr
-}
diff --git a/third_party/subzero/tests_lit/assembler/arm32/veor.ll b/third_party/subzero/tests_lit/assembler/arm32/veor.ll
deleted file mode 100644
index 8b138a1..0000000
--- a/third_party/subzero/tests_lit/assembler/arm32/veor.ll
+++ /dev/null
@@ -1,37 +0,0 @@
-; Show that we know how to translate veor. Does this by noting that
-; loading a double 0.0 introduces a veor.
-
-; REQUIRES: allow_dump
-
-; Compile using standalone assembler.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -Om1 \
-; RUN: | FileCheck %s --check-prefix=ASM
-
-; Show bytes in assembled standalone code.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -Om1 \
-; RUN: | FileCheck %s --check-prefix=DIS
-
-; Compile using integrated assembler.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -Om1 \
-; RUN: | FileCheck %s --check-prefix=IASM
-
-; Show bytes in assembled integrated code.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -Om1 \
-; RUN: | FileCheck %s --check-prefix=DIS
-
-define internal double @testVeor() {
-; ASM-LABEL: testVeor:
-; DIS: 00000000 <testVeor>:
-
-entry:
-; ASM: .LtestVeor$entry:
-
- ret double 0.0
-
-; ASM: veor.f64 d0, d0, d0
-; DIS: 0: f3000110
-; IASM-NOT: veor
-
-}
diff --git a/third_party/subzero/tests_lit/assembler/arm32/vldr-vector.ll b/third_party/subzero/tests_lit/assembler/arm32/vldr-vector.ll
deleted file mode 100644
index 60ebf05..0000000
--- a/third_party/subzero/tests_lit/assembler/arm32/vldr-vector.ll
+++ /dev/null
@@ -1,84 +0,0 @@
-; Show that we know how to translate vector load instructions.
-
-; Note: Uses -O2 to remove unnecessary loads/stores, resulting in only one VLD1
-; instruction per function.
-
-; REQUIRES: allow_dump
-
-; Compile using standalone assembler.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -O2 \
-; RUN: -reg-use=q11,r5 \
-; RUN: | FileCheck %s --check-prefix=ASM
-
-; Show bytes in assembled standalone code.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -O2 \
-; RUN: -reg-use=q11,r5 \
-; RUN: | FileCheck %s --check-prefix=DIS
-
-; Compile using integrated assembler.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -O2 \
-; RUN: -reg-use=q11,r5 \
-; RUN: | FileCheck %s --check-prefix=IASM
-
-; Show bytes in assembled integrated code.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -O2 \
-; RUN: -reg-use=q11,r5 \
-; RUN: | FileCheck %s --check-prefix=DIS
-
-define internal <4 x float> @testDerefFloat4(<4 x float> *%p) {
-; ASM-LABEL: testDerefFloat4:
-; DIS-LABEL: {{.+}} <testDerefFloat4>:
-; IASM-LABEL: testDerefFloat4:
-
-entry:
- %ret = load <4 x float>, <4 x float>* %p, align 4
-; ASM: vld1.32 q11, [r5]
-; DIS: {{.*}}: f4656a8f
-; IASM-NOT: vld1.32
-
- ret <4 x float> %ret
-}
-
-define internal <4 x i32> @testDeref4i32(<4 x i32> *%p) {
-; ASM-LABEL: testDeref4i32:
-; DIS-LABEL: {{.+}} <testDeref4i32>:
-; IASM-LABEL: testDeref4i32:
-
-entry:
- %ret = load <4 x i32>, <4 x i32>* %p, align 4
-; ASM: vld1.32 q11, [r5]
-; DIS: {{.+}}: f4656a8f
-; IASM-NOT: vld1.32
-
- ret <4 x i32> %ret
-}
-
-define internal <8 x i16> @testDeref8i16(<8 x i16> *%p) {
-; ASM-LABEL: testDeref8i16:
-; DIS-LABEL: {{.+}} <testDeref8i16>:
-; IASM-LABEL: testDeref8i16:
-
-entry:
- %ret = load <8 x i16>, <8 x i16>* %p, align 2
-; ASM: vld1.16 q11, [r5]
-; DIS: {{.+}}: f4656a4f
-; IASM-NOT: vld1.16
-
- ret <8 x i16> %ret
-}
-
-define internal <16 x i8> @testDeref16i8(<16 x i8> *%p) {
-; ASM-LABEL: testDeref16i8:
-; DIS-LABEL: {{.+}} <testDeref16i8>:
-; IASM-LABEL: testDeref16i8:
-
-entry:
- %ret = load <16 x i8>, <16 x i8>* %p, align 1
-; ASM: vld1.8 q11, [r5]
-; DIS: {{.+}}: f4656a0f
-; IASM-NOT: vld1.8
-
- ret <16 x i8> %ret
-}
diff --git a/third_party/subzero/tests_lit/assembler/arm32/vldr.ll b/third_party/subzero/tests_lit/assembler/arm32/vldr.ll
deleted file mode 100644
index f71cf37..0000000
--- a/third_party/subzero/tests_lit/assembler/arm32/vldr.ll
+++ /dev/null
@@ -1,60 +0,0 @@
-; Show that we know how to translate (floating point) vldr.
-
-; REQUIRES: allow_dump
-
-; Compile using standalone assembler.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -O2 \
-; RUN: -reg-use r5,s20,d20 \
-; RUN: | FileCheck %s --check-prefix=ASM
-
-; Show bytes in assembled standalone code.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -O2 \
-; RUN: -reg-use r5,s20,d20 \
-; RUN: | FileCheck %s --check-prefix=DIS
-
-; Compile using integrated assembler.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -O2 \
-; RUN: -reg-use r5,s20,d20 \
-; RUN: | FileCheck %s --check-prefix=IASM
-
-; Show bytes in assembled integrated code.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -O2 \
-; RUN: -reg-use r5,s20,d20 \
-; RUN: | FileCheck %s --check-prefix=DIS
-
-define internal float @testFloat() {
-; ASM-LABEL: testFloat:
-; DIS-LABEL: 00000000 <testFloat>:
-
-entry:
-; ASM: .LtestFloat$entry:
-
- %vaddr = inttoptr i32 0 to float*
- %v = load float, float* %vaddr, align 1
-
-; ASM: vldr s20, [r5]
-; DIS: c: ed95aa00
-; IASM-NOT: vldr
-
- ret float %v
-}
-
-define internal double @testDouble() {
-; ASM-LABEL: testDouble:
-; DIS-LABEL: 00000020 <testDouble>:
-
-entry:
-; ASM: .LtestDouble$entry:
-
-; %vaddr = bitcast [8 x i8]* @doubleVal to double*
- %vaddr = inttoptr i32 0 to double*
- %v = load double, double* %vaddr, align 1
-
-; ASM: vldr d20, [r5]
-; DIS: 28: edd54b00
-; IASM-NOT: vldr
-
- ret double %v
-}
diff --git a/third_party/subzero/tests_lit/assembler/arm32/vldr.vstr.imm.ll b/third_party/subzero/tests_lit/assembler/arm32/vldr.vstr.imm.ll
deleted file mode 100644
index 053dae8..0000000
--- a/third_party/subzero/tests_lit/assembler/arm32/vldr.vstr.imm.ll
+++ /dev/null
@@ -1,69 +0,0 @@
-; Test vldr{s,d} and vstr{s,d} when address is offset with an immediate.
-
-; REQUIRES: allow_dump
-
-; Compile using standalone assembler.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -Om1 \
-; RUN: -reg-use d20 \
-; RUN: | FileCheck %s --check-prefix=ASM
-
-; Show bytes in assembled standalone code.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -Om1 \
-; RUN: -reg-use d20 \
-; RUN: | FileCheck %s --check-prefix=DIS
-
-; Compile using integrated assembler.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -Om1 \
-; RUN: -reg-use d20 \
-; RUN: | FileCheck %s --check-prefix=IASM
-
-; Show bytes in assembled integrated code.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -Om1 \
-; RUN: -reg-use d20 \
-; RUN: | FileCheck %s --check-prefix=DIS
-
-define internal i32 @testFloatImm(float %f) {
-; ASM-LABEL: testFloatImm:
-; DIS-LABEL: 00000000 <testFloatImm>:
-; IASM-LABEL: testFloatImm:
-
-entry:
-; ASM: .LtestFloatImm$entry:
-; IASM: .LtestFloatImm$entry:
-
-; ASM: vstr s0, [sp, #4]
-; DIS: 4: ed8d0a01
-; IASM-NOT: vstr
-
- %v = bitcast float %f to i32
-
-; ASM: vldr s0, [sp, #4]
-; DIS: 8: ed9d0a01
-; IASM-NOT: vldr
-
- ret i32 %v
-}
-
-define internal i64 @testDoubleImm(double %d) {
-; ASM-LABEL: testDoubleImm:
-; DIS-LABEL: 00000020 <testDoubleImm>:
-; IASM-LABEL: testDoubleImm:
-
-entry:
-; ASM: .LtestDoubleImm$entry:
-; IASM: .LtestDoubleImm$entry:
-
-; ASM: vstr d0, [sp, #8]
-; DIS: 24: ed8d0b02
-; IASM-NOT: vstr
-
- %v = bitcast double %d to i64
-
-; ASM: vldr d20, [sp, #8]
-; DIS: 28: eddd4b02
-; IASM-NOT: vldr
-
- ret i64 %v
-}
diff --git a/third_party/subzero/tests_lit/assembler/arm32/vmla.ll b/third_party/subzero/tests_lit/assembler/arm32/vmla.ll
deleted file mode 100644
index 04797ee..0000000
--- a/third_party/subzero/tests_lit/assembler/arm32/vmla.ll
+++ /dev/null
@@ -1,56 +0,0 @@
-; Show that we can take advantage of the vmla instruction for floating point
-; operations during optimization.
-
-; Note that we use -O2 to force the result of the fmul to be (immediately)
-; available for the fadd. When using -Om1, the merge of fmul and fadd does not
-; happen due to intervening register spill code.
-
-; REQUIRES: allow_dump
-
-; Compile using standalone assembler.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -O2 \
-; RUN: -reg-use=s20,s21,s22,d20,d21,d22 \
-; RUN: | FileCheck %s --check-prefix=ASM
-
-; Show bytes in assembled standalone code.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -O2 -reg-use=s20,s21,s22,d20,d21,d22 \
-; RUN: | FileCheck %s --check-prefix=DIS
-
-; Compile using integrated assembler.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -O2 \
-; RUN: -reg-use=s20,s21,s22,d20,d21,d22 \
-; RUN: | FileCheck %s --check-prefix=IASM
-
-; Show bytes in assembled integrated code.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -O2 -reg-use=s20,s21,s22,d20,d21,d22 \
-; RUN: | FileCheck %s --check-prefix=DIS
-
-define internal float @mulAddFloat(float %f1, float %f2) {
-; ASM-LABEL: mulAddFloat:
-; DIS-LABEL: 00000000 <mulAddFloat>:
-
- %v1 = fmul float %f1, 1.5
- %v2 = fadd float %f2, %v1
-
-; ASM: vmla.f32 s21, s20, s22
-; DIS: 10: ee4aaa0b
-; IASM-NOT: vmla
-
- ret float %v2
-}
-
-define internal double @mulAddDouble(double %f1, double %f2) {
-; ASM-LABEL: mulAddDouble:
-; DIS-LABEL: 00000020 <mulAddDouble>:
-
- %v1 = fmul double %f1, 1.5
- %v2 = fadd double %f2, %v1
-
-; ASM: vmla.f64 d21, d20, d22
-; DIS: 2c: ee445ba6
-; IASM-NOT: vmla
-
- ret double %v2
-}
diff --git a/third_party/subzero/tests_lit/assembler/arm32/vmls.ll b/third_party/subzero/tests_lit/assembler/arm32/vmls.ll
deleted file mode 100644
index d1243cc..0000000
--- a/third_party/subzero/tests_lit/assembler/arm32/vmls.ll
+++ /dev/null
@@ -1,56 +0,0 @@
-; Show that we can take advantage of the vmls instruction for floating point
-; operations during optimization.
-
-; Note that we use -O2 to force the result of the fmul to be
-; (immediately) available for the fsub. When using -Om1, the merge of
-; fmul and fsub does not happen.
-
-; REQUIRES: allow_dump
-
-; Compile using standalone assembler.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -O2 \
-; RUN: -reg-use=s20,s21,s22,d20,d21,d22 \
-; RUN: | FileCheck %s --check-prefix=ASM
-
-; Show bytes in assembled standalone code.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -O2 -reg-use=s20,s21,s22,d20,d21,d22 \
-; RUN: | FileCheck %s --check-prefix=DIS
-
-; Compile using integrated assembler.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -O2 \
-; RUN: -reg-use=s20,s21,s22,d20,d21,d22 \
-; RUN: | FileCheck %s --check-prefix=IASM
-
-; Show bytes in assembled integrated code.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -O2 -reg-use=s20,s21,s22,d20,d21,d22 \
-; RUN: | FileCheck %s --check-prefix=DIS
-
-define internal float @mulSubFloat(float %f1, float %f2) {
-; ASM-LABEL: mulSubFloat:
-; DIS-LABEL: 00000000 <mulSubFloat>:
-
- %v1 = fmul float %f1, 1.5
- %v2 = fsub float %f2, %v1
-
-; ASM: vmls.f32 s21, s20, s22
-; DIS: 10: ee4aaa4b
-; IASM-NOT: vmls.f32
-
- ret float %v2
-}
-
-define internal double @mulSubDouble(double %f1, double %f2) {
-; ASM-LABEL: mulSubDouble:
-; DIS-LABEL: 00000020 <mulSubDouble>:
-
- %v1 = fmul double %f1, 1.5
- %v2 = fsub double %f2, %v1
-
-; ASM: vmls.f64 d21, d20, d22
-; DIS: 2c: ee445be6
-; IASM-NOT: vmls.f64
-
- ret double %v2
-}
diff --git a/third_party/subzero/tests_lit/assembler/arm32/vmov-cast.ll b/third_party/subzero/tests_lit/assembler/arm32/vmov-cast.ll
deleted file mode 100644
index 2fa59d1..0000000
--- a/third_party/subzero/tests_lit/assembler/arm32/vmov-cast.ll
+++ /dev/null
@@ -1,45 +0,0 @@
-; Show that we know how to translate vmov for casts.
-
-; NOTE: Restricts S register to one that will better test S register encodings.
-
-; REQUIRES: allow_dump
-
-; Compile using standalone assembler.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -Om1 \
-; RUN: -reg-use s20,s22,d20,d22 \
-; RUN: | FileCheck %s --check-prefix=ASM
-
-; Show bytes in assembled standalone code.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -Om1 \
-; RUN: -reg-use s20,s22,d20,d22 \
-; RUN: | FileCheck %s --check-prefix=DIS
-
-; Compile using integrated assembler.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -Om1 \
-; RUN: -reg-use s20,s22,d20,d22 \
-; RUN: | FileCheck %s --check-prefix=IASM
-
-; Show bytes in assembled integrated code.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -Om1 \
-; RUN: -reg-use s20,s22,d20,d22 \
-; RUN: | FileCheck %s --check-prefix=DIS
-
-define internal float @castToFloat(i32 %a) {
-; ASM-LABEL: castToFloat:
-; DIS-LABEL: 00000000 <castToFloat>:
-; IASM-LABEL: castToFloat:
-
-entry:
-; ASM: .LcastToFloat$entry:
-; IASM: .LcastToFloat$entry:
-
- %0 = bitcast i32 %a to float
-
-; ASM: vmov s20, r0
-; DIS: 10: ee0a0a10
-; IASM-NOT: vmov
-
- ret float %0
-}
diff --git a/third_party/subzero/tests_lit/assembler/arm32/vmov-dbl.ll b/third_party/subzero/tests_lit/assembler/arm32/vmov-dbl.ll
deleted file mode 100644
index 4e86af9..0000000
--- a/third_party/subzero/tests_lit/assembler/arm32/vmov-dbl.ll
+++ /dev/null
@@ -1,57 +0,0 @@
-; Show that we can generate vmov for bitcasts between i64 and double.
-
-; REQUIRES: allow_dump
-
-; Compile using standalone assembler.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -Om1 \
-; RUN: -allow-extern -reg-use r5,r10,d20 \
-; RUN: | FileCheck %s --check-prefix=ASM
-
-; Show bytes in assembled standalone code.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -Om1 \
-; RUN: -allow-extern -reg-use r5,r10,d20 \
-; RUN: | FileCheck %s --check-prefix=DIS
-
-; Compile using integrated assembler.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -Om1 \
-; RUN: -allow-extern -reg-use r5,r10,d20 \
-; RUN: | FileCheck %s --check-prefix=IASM
-
-; Show bytes in assembled integrated code.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -Om1 \
-; RUN: -allow-extern -reg-use r5,r10,d20 \
-; RUN: | FileCheck %s --check-prefix=DIS
-
-define internal i64 @convertDoubleToI64(double %d) {
-; ASM-LABEL: convertDoubleToI64:
-; DIS-LABEL: {{.+}} <convertDoubleToI64>:
-
- %v = bitcast double %d to i64
-
-; ASM: vmov r5, r10, d20
-; DIS: {{.+}}: ec5a5b34
-; IASM-NOT: vmov
-
- ret i64 %v
-}
-
-define internal double @convertI64ToDouble(i64 %i) {
-; ASM-LABEL: convertI64ToDouble:
-; DIS-LABEL: {{.+}} <convertI64ToDouble>:
-
- %v = bitcast i64 %i to double
-
-; ASM: vmov d20, r5, r10
-; DIS: {{.+}}: ec4a5b34
-; IASM-NOT: vmov
-
- ; Note: This call is added to allow %v to be put into d20 (instead of
- ; return register d0).
- call void @ignore(double %v)
-
- ret double %v
-}
-
-declare external void @ignore(double)
diff --git a/third_party/subzero/tests_lit/assembler/arm32/vmov-f2i.ll b/third_party/subzero/tests_lit/assembler/arm32/vmov-f2i.ll
deleted file mode 100644
index c8b8504..0000000
--- a/third_party/subzero/tests_lit/assembler/arm32/vmov-f2i.ll
+++ /dev/null
@@ -1,124 +0,0 @@
-; Show that we can move between float (S) and integer (GPR) registers.
-
-; REQUIRES: allow_dump
-
-; Compile using standalone assembler.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -Om1 \
-; RUN: --reg-use=s20,r5,r6 | FileCheck %s --check-prefix=ASM
-
-; Show bytes in assembled standalone code.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -Om1 --reg-use=s20,r5,r6 | FileCheck %s --check-prefix=DIS
-
-; Compile using integrated assembler.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -Om1 \
-; RUN: --reg-use=s20,r5,r6 \
-; RUN: | FileCheck %s --check-prefix=IASM
-
-; Show bytes in assembled integrated code.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -Om1 --reg-use=s20,r5,r6 | FileCheck %s --check-prefix=DIS
-
-define internal void @FloatToI1() {
-; ASM-LABEL: FloatToI1:
-; DIS-LABEL: {{.+}} <FloatToI1>:
-
- %v = fptoui float 0.0 to i1
-
-; ASM: vmov r5, s20
-; DIS: {{.+}}: ee1a5a10
-; IASM-NOT: vmov
-
- ret void
-}
-
-define internal void @FloatToI8() {
-; ASM-LABEL: FloatToI8:
-; DIS-LABEL: {{.+}} <FloatToI8>:
-
- %v = fptoui float 0.0 to i8
-
-; ASM: vmov r5, s20
-; DIS: {{.+}}: ee1a5a10
-; IASM-NOT: vmov
-
- ret void
-}
-
-define internal void @FloatToI16() {
-; ASM-LABEL: FloatToI16:
-; DIS-LABEL: {{.+}} <FloatToI16>:
-
- %v = fptoui float 0.0 to i16
-
-; ASM: vmov r5, s20
-; DIS: {{.+}}: ee1a5a10
-; IASM-NOT: vmov
-
- ret void
-}
-
-define internal void @FloatToI32() {
-; ASM-LABEL: FloatToI32:
-; DIS-LABEL: {{.+}} <FloatToI32>:
-
- %v = fptoui float 0.0 to i32
-
-; ASM: vmov r5, s20
-; DIS: {{.+}}: ee1a5a10
-; IASM-NOT: vmov
-
- ret void
-}
-
-define internal float @I1ToFloat() {
-; ASM-LABEL: I1ToFloat:
-; DIS-LABEL: {{.+}} <I1ToFloat>:
-
- %v = uitofp i1 1 to float
-
-; ASM: vmov s20, r5
-; DIS: {{.+}}: ee0a5a10
-; IASM-NOT: vmov
-
- ret float %v
-}
-
-define internal float @I8ToFloat() {
-; ASM-LABEL: I8ToFloat:
-; DIS-LABEL: {{.+}} <I8ToFloat>:
-
- %v = uitofp i8 1 to float
-
-; ASM: vmov s20, r5
-; DIS: {{.+}}: ee0a5a10
-; IASM-NOT: vmov
-
- ret float %v
-}
-
-define internal float @I16ToFloat() {
-; ASM-LABEL: I16ToFloat:
-; DIS-LABEL: {{.+}} <I16ToFloat>:
-
- %v = uitofp i16 1 to float
-
-; ASM: vmov s20, r5
-; DIS: {{.+}}: ee0a5a10
-; IASM-NOT: vmov
-
- ret float %v
-}
-
-define internal float @I32ToFloat() {
-; ASM-LABEL: I32ToFloat:
-; DIS-LABEL: {{.+}} <I32ToFloat>:
-
- %v = uitofp i32 17 to float
-
-; ASM: vmov s20, r5
-; DIS: {{.+}}: ee0a5a10
-; IASM-NOT: vmov
-
- ret float %v
-}
diff --git a/third_party/subzero/tests_lit/assembler/arm32/vmov-fp.ll b/third_party/subzero/tests_lit/assembler/arm32/vmov-fp.ll
deleted file mode 100644
index 277632a..0000000
--- a/third_party/subzero/tests_lit/assembler/arm32/vmov-fp.ll
+++ /dev/null
@@ -1,57 +0,0 @@
-; Show that we know how to move between floating point registers.
-
-; NOTE: We use the select instruction to fire this in -Om1, since a
-; vmovne is generated (after a branch) to (conditionally) assign the
-; else value.
-
-; REQUIRES: allow_dump
-
-; Compile using standalone assembler.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -Om1 \
-; RUN: -reg-use s20,s22,d20,d22 \
-; RUN: | FileCheck %s --check-prefix=ASM
-
-; Show bytes in assembled standalone code.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -Om1 \
-; RUN: -reg-use s20,s22,d20,d22 \
-; RUN: | FileCheck %s --check-prefix=DIS
-
-; Compile using integrated assembler.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -Om1 \
-; RUN: -reg-use s20,s22,d20,d22 \
-; RUN: | FileCheck %s --check-prefix=IASM
-
-; Show bytes in assembled integrated code.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -Om1 \
-; RUN: -reg-use s20,s22,d20,d22 \
-; RUN: | FileCheck %s --check-prefix=DIS
-
-define internal float @moveFloat() {
-; ASM-LABEL: moveFloat:
-; DIS-LABEL: 00000000 <moveFloat>:
-; IASM-LABEL: moveFloat:
-
- %v = select i1 true, float 0.5, float 1.5
-
-; ASM: vmovne.f32 s20, s22
-; DIS: 1c: 1eb0aa4b
-; IASM-NOT: vmovnew.f32
-
- ret float %v
-}
-
-define internal double @moveDouble() {
-; ASM-LABEL: moveDouble:
-; DIS-LABEL: 00000040 <moveDouble>:
-; IASM-LABEL: moveDouble:
-
- %v = select i1 true, double 0.5, double 1.5
-
-; ASM: vmovne.f64 d20, d22
-; DIS: 54: 1ef04b66
-; IASM-NOT: vmovne.f64
-
- ret double %v
-}
diff --git a/third_party/subzero/tests_lit/assembler/arm32/vmov-imm.ll b/third_party/subzero/tests_lit/assembler/arm32/vmov-imm.ll
deleted file mode 100644
index 9e3c80e..0000000
--- a/third_party/subzero/tests_lit/assembler/arm32/vmov-imm.ll
+++ /dev/null
@@ -1,50 +0,0 @@
-; Test moving constants into VPF registers.
-
-; REQUIRES: allow_dump
-
-; Compile using standalone assembler.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -Om1 -reg-use=d21,s20 \
-; RUN: | FileCheck %s --check-prefix=ASM
-
-; Show bytes in assembled standalone code.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -Om1 -reg-use=d21,s20 \
-; RUN: | FileCheck %s --check-prefix=DIS
-
-; Compile using integrated assembler.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -Om1 -reg-use=d21,s20 \
-; RUN: | FileCheck %s --check-prefix=IASM
-
-; Show bytes in assembled integrated code.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -Om1 -reg-use=d21,s20 \
-; RUN: | FileCheck %s --check-prefix=DIS
-
-define internal void @testMoveDouble() {
-; ASM-LABEL: testMoveDouble:
-; DIS-LABEL: 00000000 <testMoveDouble>:
-
-entry:
- store double 1.5, double* undef, align 8
-
-; ASM: vmov.f64 d21, #1.500000e+00
-; DIS: 4: eef75b08
-; IASM-NOT: vmov.f64
-
- ret void
-}
-
-define internal void @testMoveFloat() {
-; ASM-LABEL: testMoveFloat:
-; DIS-LABEL: 00000010 <testMoveFloat>:
-
-entry:
- %addr = inttoptr i32 0 to float*
- store float 1.5, float* %addr, align 4
-
-; ASM: vmov.f32 s20, #1.500000e+00
-; DIS: 18: eeb7aa08
-; IASM-NOT: vmov.f32
-
- ret void
-}
diff --git a/third_party/subzero/tests_lit/assembler/arm32/vmrs.ll b/third_party/subzero/tests_lit/assembler/arm32/vmrs.ll
deleted file mode 100644
index f635389..0000000
--- a/third_party/subzero/tests_lit/assembler/arm32/vmrs.ll
+++ /dev/null
@@ -1,38 +0,0 @@
-; Test the "vmrs APSR_nzcv, FPSCR" form of the VMRS instruction.
-
-; REQUIRES: allow_dump
-
-; Compile using standalone assembler.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -Om1 \
-; RUN: | FileCheck %s --check-prefix=ASM
-
-; Show bytes in assembled standalone code.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -Om1 \
-; RUN: | FileCheck %s --check-prefix=DIS
-
-; Compile using integrated assembler.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -Om1 \
-; RUN: | FileCheck %s --check-prefix=IASM
-
-; Show bytes in assembled integrated code.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -Om1 \
-; RUN: | FileCheck %s --check-prefix=DIS
-
-define internal i32 @testVmrsASPR_nzcv() {
-; ASM-LABEL: testVmrsASPR_nzcv:
-; DIS-LABEL: 00000000 <testVmrsASPR_nzcv>:
-
-entry:
-; ASM: .LtestVmrsASPR_nzcv$entry:
-
- %test = fcmp olt float 0.0, 0.0
-
-; ASM: vmrs APSR_nzcv, FPSCR
-; DIS: 14: eef1fa10
-; IASM-NOT: vmrs
-
- %result = zext i1 %test to i32
- ret i32 %result
-}
diff --git a/third_party/subzero/tests_lit/assembler/arm32/vmul.ll b/third_party/subzero/tests_lit/assembler/arm32/vmul.ll
deleted file mode 100644
index 7d53279..0000000
--- a/third_party/subzero/tests_lit/assembler/arm32/vmul.ll
+++ /dev/null
@@ -1,63 +0,0 @@
-; Show that we know how to translate vmul.
-
-; NOTE: We use -O2 to get rid of memory stores.
-
-; REQUIRES: allow_dump
-
-; Compile using standalone assembler.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -O2 \
-; RUN: | FileCheck %s --check-prefix=ASM
-
-; Show bytes in assembled standalone code.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -O2 | FileCheck %s --check-prefix=DIS
-
-; Compile using integrated assembler.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -O2 \
-; RUN: | FileCheck %s --check-prefix=IASM
-
-; Show bytes in assembled integrated code.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -O2 | FileCheck %s --check-prefix=DIS
-
-define internal float @testVmulFloat(float %a, float %b) {
-; ASM-LABEL: testVmulFloat:
-; DIS-LABEL: 00000000 <testVmulFloat>:
-; IASM-LABEL: testVmulFloat:
-
-entry:
-; ASM-NEXT: .LtestVmulFloat$entry:
-; IASM-NEXT: .LtestVmulFloat$entry:
-
- %mul = fmul float %a, %b
-
-; ASM-NEXT: vmul.f32 s0, s0, s1
-; DIS-NEXT: 0: ee200a20
-; IASM-NEXT: .byte 0x20
-; IASM-NEXT: .byte 0xa
-; IASM-NEXT: .byte 0x20
-; IASM-NEXT: .byte 0xee
-
- ret float %mul
-}
-
-define internal double @testVmulDouble(double %a, double %b) {
-; ASM-LABEL: testVmulDouble:
-; DIS-LABEL: 00000010 <testVmulDouble>:
-; IASM-LABEL: testVmulDouble:
-
-entry:
-; ASM-NEXT: .LtestVmulDouble$entry:
-; IASM-NEXT: .LtestVmulDouble$entry:
-
- %mul = fmul double %a, %b
-
-; ASM-NEXT: vmul.f64 d0, d0, d1
-; DIS-NEXT: 10: ee200b01
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0xb
-; IASM-NEXT: .byte 0x20
-; IASM-NEXT: .byte 0xee
-
- ret double %mul
-}
diff --git a/third_party/subzero/tests_lit/assembler/arm32/vpush.ll b/third_party/subzero/tests_lit/assembler/arm32/vpush.ll
deleted file mode 100644
index 1aa9c7a..0000000
--- a/third_party/subzero/tests_lit/assembler/arm32/vpush.ll
+++ /dev/null
@@ -1,47 +0,0 @@
-; Show that we know how to translate vpush and vpop.
-
-; NOTE: We use -O2 because vpush/vpop only occur if optimized. Uses
-; simple call with double parameters to cause the insertion of
-; vpush/vpop.
-
-; REQUIRES: allow_dump
-
-; Compile using standalone assembler.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -O2 -reg-use=d9,d10 \
-; RUN: | FileCheck %s --check-prefix=ASM
-
-; Show bytes in assembled standalone code.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -O2 -reg-use=d9,d10 \
-; RUN: | FileCheck %s --check-prefix=DIS
-
-; Compile using integrated assembler.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -O2 -reg-use=d9,d10 \
-; RUN: | FileCheck %s --check-prefix=IASM
-
-; Show bytes in assembled integrated code.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -O2 -reg-use=d9,d10 \
-; RUN: | FileCheck %s --check-prefix=DIS
-
-define internal double @testVpushVpop(double %v1, double %v2) {
-; ASM-LABEL: testVpushVpop:
-; DIS-LABEL: 00000000 <testVpushVpop>:
-
-; ASM: vpush {s18, s19, s20, s21}
-; DIS: 0: ed2d9a04
-; IASM-NOT: vpush
-
- call void @foo()
- %res = fadd double %v1, %v2
- ret double %res
-
-; ASM: vpop {s18, s19, s20, s21}
-; DIS: 28: ecbd9a04
-; IASM-NOT: vpopd
-
-}
-
-define internal void @foo() {
- ret void
-}
diff --git a/third_party/subzero/tests_lit/assembler/arm32/vsqrt.ll b/third_party/subzero/tests_lit/assembler/arm32/vsqrt.ll
deleted file mode 100644
index a9408d2..0000000
--- a/third_party/subzero/tests_lit/assembler/arm32/vsqrt.ll
+++ /dev/null
@@ -1,52 +0,0 @@
-; Show that we can translate intrinsic vsqrt into a binary instruction.
-
-; REQUIRES: allow_dump
-
-; Compile using standalone assembler.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -Om1 -allow-extern \
-; RUN: -reg-use s20,d20 | FileCheck %s --check-prefix=ASM
-
-; Show bytes in assembled standalone code.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -Om1 -allow-extern -reg-use s20,d20 \
-; RUN: | FileCheck %s --check-prefix=DIS
-
-; Compile using integrated assembler.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -Om1 -allow-extern \
-; RUN: -reg-use s20,d20 | FileCheck %s --check-prefix=IASM
-
-; Show bytes in assembled integrated code.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -Om1 -allow-extern -reg-use s20,d20 \
-; RUN: | FileCheck %s --check-prefix=DIS
-
-declare float @llvm.sqrt.f32(float)
-declare double @llvm.sqrt.f64(double)
-
-define internal float @sqrtFloat() {
-; ASM-LABEL: sqrtFloat:
-; DIS-LABEL: 00000000 <sqrtFloat>:
-; IASM-LABEL: sqrtFloat:
-
- %v = call float @llvm.sqrt.f32(float 0.5);
-
-; ASM: vsqrt.f32 s20, s20
-; DIS: c: eeb1aaca
-; IASM-NOT: vsqrt.f32
-
- ret float %v
-}
-
-define internal double @sqrtDouble() {
-; ASM-LABEL: sqrtDouble:
-; DIS-LABEL: 00000030 <sqrtDouble>:
-; IASM-LABEL: sqrtDouble:
-
- %v = call double @llvm.sqrt.f64(double 0.5);
-
-; ASM: vsqrt.f64 d20, d20
-; DIS: 38: eef14be4
-; IASM-NOT: vsqrt.f64
-
- ret double %v
-}
diff --git a/third_party/subzero/tests_lit/assembler/arm32/vstr-vector.ll b/third_party/subzero/tests_lit/assembler/arm32/vstr-vector.ll
deleted file mode 100644
index ea810bc..0000000
--- a/third_party/subzero/tests_lit/assembler/arm32/vstr-vector.ll
+++ /dev/null
@@ -1,78 +0,0 @@
-; Show that we know how to translate vector store instructions.
-
-; Note: Uses -O2 to remove unnecessary loads/stores, resulting in only one VST1
-; instruction per function.
-
-; REQUIRES: allow_dump
-
-; Compile using standalone assembler.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -O2 \
-; RUN: -reg-use=q11,r5 \
-; RUN: | FileCheck %s --check-prefix=ASM
-
-; Show bytes in assembled standalone code.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -O2 \
-; RUN: -reg-use=q11,r5 \
-; RUN: | FileCheck %s --check-prefix=DIS
-
-; Compile using integrated assembler.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -O2 \
-; RUN: -reg-use=q11,r5 \
-; RUN: | FileCheck %s --check-prefix=IASM
-
-; Show bytes in assembled integrated code.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -O2 \
-; RUN: -reg-use=q11,r5 \
-; RUN: | FileCheck %s --check-prefix=DIS
-
-define internal void @testDerefFloat4(<4 x float>* %p, <4 x float> %v) {
-; ASM-LABEL: testDerefFloat4:
-; DIS-LABEL: {{.+}} <testDerefFloat4>:
-
-entry:
- store <4 x float> %v, <4 x float>* %p, align 4
-; ASM: vst1.32 q11, [r5]
-; DIS: {{.+}}: f4456a8f
-; IASM-NOT: vst1.32
-
- ret void
-}
-
-define internal void @testDeref4i32(<4 x i32> *%p, <4 x i32> %v) {
-; ASM-LABEL: testDeref4i32:
-; DIS-LABEL: {{.+}} <testDeref4i32>:
-
-entry:
- store <4 x i32> %v, <4 x i32>* %p, align 4
-; ASM: vst1.32 q11, [r5]
-; DIS: {{.+}}: f4456a8f
-; IASM-NOT: vst1.32
-
- ret void
-}
-
-define internal void @testDeref8i16(<8 x i16> *%p, <8 x i16> %v) {
-; ASM-LABEl: testDeref8i16:
-; DIS-LABEL: {{.+}} <testDeref8i16>:
-
- store <8 x i16> %v, <8 x i16>* %p, align 2
-; ASM: vst1.16 q11, [r5]
-; DIS: {{.+}}: f4456a4f
-; IASM-NOT: vst1.16
-
- ret void
-}
-
-define internal void @testDeref16i8(<16 x i8> *%p, <16 x i8> %v) {
-; ASM-LABEL: testDeref16i8:
-; DIS-LABEL: {{.+}} <testDeref16i8>:
-
- store <16 x i8> %v, <16 x i8>* %p, align 1
-; ASM: vst1.8 q11, [r5]
-; DIS: {{.+}}: f4456a0f
-; IASM-NOT: vst1.8
-
- ret void
-}
diff --git a/third_party/subzero/tests_lit/assembler/arm32/vstr.ll b/third_party/subzero/tests_lit/assembler/arm32/vstr.ll
deleted file mode 100644
index df6f397..0000000
--- a/third_party/subzero/tests_lit/assembler/arm32/vstr.ll
+++ /dev/null
@@ -1,61 +0,0 @@
-; Show that we know how to translate (floating point) vstr.
-
-; REQUIRES: allow_dump
-
-; Compile using standalone assembler.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -O2 \
-; RUN: -reg-use r5,r6,s20,d20 \
-; RUN: | FileCheck %s --check-prefix=ASM
-
-; Show bytes in assembled standalone code.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -O2 \
-; RUN: -reg-use r5,r6,s20,d20 \
-; RUN: | FileCheck %s --check-prefix=DIS
-
-; Compile using integrated assembler.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -O2 \
-; RUN: -reg-use r5,r6,s20,d20 \
-; RUN: | FileCheck %s --check-prefix=IASM
-
-; Show bytes in assembled integrated code.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -O2 \
-; RUN: -reg-use r5,r6,s20,d20 \
-; RUN: | FileCheck %s --check-prefix=DIS
-
-define internal void @testFloat() {
-; ASM-LABEL: testFloat:
-; DIS-LABEL: 00000000 <testFloat>:
-; IASM-LABEL: testFloat:
-
-entry:
-; ASM: .LtestFloat$entry:
-
- %vaddr = inttoptr i32 0 to float*
- store float 0.0, float* %vaddr, align 1
-
-; ASM: vstr s20, [r5]
-; DIS: 14: ed96aa00
-; IASM-NOT: vstr
-
- ret void
-}
-
-define internal void @testDouble() {
-; ASM-LABEL: testDouble:
-; DIS-LABEL: 00000030 <testDouble>:
-; IASM-LABEL: testDouble:
-
-entry:
-; ASM: .LtestDouble$entry:
-
- %vaddr = inttoptr i32 0 to double*
- store double 0.0, double* %vaddr, align 1
-
-; ASM: vstr d20, [r5]
-; DIS: 3c: edc54b00
-; IASM-NOT: vstr
-
- ret void
-}
diff --git a/third_party/subzero/tests_lit/assembler/arm32/vsub.ll b/third_party/subzero/tests_lit/assembler/arm32/vsub.ll
deleted file mode 100644
index dc70726..0000000
--- a/third_party/subzero/tests_lit/assembler/arm32/vsub.ll
+++ /dev/null
@@ -1,63 +0,0 @@
-; Show that we know how to translate vsub.
-
-; NOTE: We use -O2 to get rid of memory stores.
-
-; REQUIRES: allow_dump
-
-; Compile using standalone assembler.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -O2 \
-; RUN: | FileCheck %s --check-prefix=ASM
-
-; Show bytes in assembled standalone code.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -O2 | FileCheck %s --check-prefix=DIS
-
-; Compile using integrated assembler.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -O2 \
-; RUN: | FileCheck %s --check-prefix=IASM
-
-; Show bytes in assembled integrated code.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -O2 | FileCheck %s --check-prefix=DIS
-
-define internal float @testVsubFloat(float %v1, float %v2) {
-; ASM-LABEL: testVsubFloat:
-; DIS-LABEL: 00000000 <testVsubFloat>:
-; IASM-LABEL: testVsubFloat:
-
-entry:
-; ASM-NEXT: .LtestVsubFloat$entry:
-; IASM-NEXT: .LtestVsubFloat$entry:
-
- %res = fsub float %v1, %v2
-
-; ASM-NEXT: vsub.f32 s0, s0, s1
-; DIS-NEXT: 0: ee300a60
-; IASM-NEXT: .byte 0x60
-; IASM-NEXT: .byte 0xa
-; IASM-NEXT: .byte 0x30
-; IASM-NEXT: .byte 0xee
-
- ret float %res
-}
-
-define internal double @testVsubDouble(double %v1, double %v2) {
-; ASM-LABEL: testVsubDouble:
-; DIS-LABEL: 00000010 <testVsubDouble>:
-; IASM-LABEL: testVsubDouble:
-
-entry:
-; ASM-NEXT: .LtestVsubDouble$entry:
-; IASM-NEXT: .LtestVsubDouble$entry:
-
- %res = fsub double %v1, %v2
-
-; ASM-NEXT: vsub.f64 d0, d0, d1
-; DIS-NEXT: 10: ee300b41
-; IASM-NEXT: .byte 0x41
-; IASM-NEXT: .byte 0xb
-; IASM-NEXT: .byte 0x30
-; IASM-NEXT: .byte 0xee
-
- ret double %res
-}
diff --git a/third_party/subzero/tests_lit/assembler/arm32/xor-vec.ll b/third_party/subzero/tests_lit/assembler/arm32/xor-vec.ll
deleted file mode 100644
index eef201e..0000000
--- a/third_party/subzero/tests_lit/assembler/arm32/xor-vec.ll
+++ /dev/null
@@ -1,115 +0,0 @@
-; Show that we know how to translate veor vector instructions.
-
-; REQUIRES: allow_dump
-
-; Compile using standalone assembler.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -O2 \
-; RUN: | FileCheck %s --check-prefix=ASM
-
-; Show bytes in assembled standalone code.
-; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -O2 \
-; RUN: | FileCheck %s --check-prefix=DIS
-
-; Compile using integrated assembler.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -O2 \
-; RUN: | FileCheck %s --check-prefix=IASM
-
-; Show bytes in assembled integrated code.
-; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
-; RUN: --args -O2 \
-; RUN: | FileCheck %s --check-prefix=DIS
-
-define internal <4 x i32> @testVxor4i32(<4 x i32> %v1, <4 x i32> %v2) {
-; ASM-LABEL: testVxor4i32:
-; DIS-LABEL: 00000000 <testVxor4i32>:
-; IASM-LABEL: testVxor4i32:
-
-entry:
- %res = xor <4 x i32> %v1, %v2
-
-; ASM: veor.i32 q0, q0, q1
-; DIS: 0: f3000152
-; IASM-NOT: veor.i32
-
- ret <4 x i32> %res
-}
-
-define internal <8 x i16> @testVxor8i16(<8 x i16> %v1, <8 x i16> %v2) {
-; ASM-LABEL: testVxor8i16:
-; DIS-LABEL: 00000010 <testVxor8i16>:
-; IASM-LABEL: testVxor8i16:
-
-entry:
- %res = xor <8 x i16> %v1, %v2
-
-; ASM: veor.i16 q0, q0, q1
-; DIS: 10: f3000152
-; IASM-NOT: veor.i16
-
- ret <8 x i16> %res
-}
-
-define internal <16 x i8> @testVxor16i8(<16 x i8> %v1, <16 x i8> %v2) {
-; ASM-LABEL: testVxor16i8:
-; DIS-LABEL: 00000020 <testVxor16i8>:
-; IASM-LABEL: testVxor16i8:
-
-entry:
- %res = xor <16 x i8> %v1, %v2
-
-; ASM: veor.i8 q0, q0, q1
-; DIS: 20: f3000152
-; IASM-NOT: veor.i8
-
- ret <16 x i8> %res
-}
-
-;;
-;; The following tests make sure logical xor works on predicate vectors.
-;;
-
-define internal <4 x i1> @testVxor4i1(<4 x i1> %v1, <4 x i1> %v2) {
-; ASM-LABEL: testVxor4i1:
-; DIS-LABEL: 00000030 <testVxor4i1>:
-; IASM-LABEL: testVxor4i1:
-
-entry:
- %res = xor <4 x i1> %v1, %v2
-
-; ASM: veor.i32 q0, q0, q1
-; DIS: 30: f3000152
-; IASM-NOT: veor.i32
-
- ret <4 x i1> %res
-}
-
-define internal <8 x i1> @testVxor8i1(<8 x i1> %v1, <8 x i1> %v2) {
-; ASM-LABEL: testVxor8i1:
-; DIS-LABEL: 00000040 <testVxor8i1>:
-; IASM-LABEL: testVxor8i1:
-
-entry:
- %res = xor <8 x i1> %v1, %v2
-
-; ASM: veor.i16 q0, q0, q1
-; DIS: 40: f3000152
-; IASM-NOT: veor.i16
-
- ret <8 x i1> %res
-}
-
-define internal <16 x i1> @testVxor16i1(<16 x i1> %v1, <16 x i1> %v2) {
-; ASM-LABEL: testVxor16i1:
-; DIS-LABEL: 00000050 <testVxor16i1>:
-; IASM-LABEL: testVxor16i1:
-
-entry:
- %res = xor <16 x i1> %v1, %v2
-
-; ASM: veor.i8 q0, q0, q1
-; DIS: 50: f3000152
-; IASM-NOT: veor.i8
-
- ret <16 x i1> %res
-}
diff --git a/third_party/subzero/tests_lit/assembler/mips32/encoding_intrinsics.ll b/third_party/subzero/tests_lit/assembler/mips32/encoding_intrinsics.ll
deleted file mode 100644
index 7d18f3e..0000000
--- a/third_party/subzero/tests_lit/assembler/mips32/encoding_intrinsics.ll
+++ /dev/null
@@ -1,1091 +0,0 @@
-; Test encoding of MIPS32 instructions used in intrinsic calls
-
-; REQUIRES: allow_dump
-
-; Compile using standalone assembler.
-; RUN: %p2i --filetype=asm -i %s --target=mips32 --args -O2 \
-; RUN: --allow-externally-defined-symbols \
-; RUN: | FileCheck %s --check-prefix=ASM
-
-; Show bytes in assembled standalone code.
-; RUN: %p2i --filetype=asm -i %s --target=mips32 --assemble --disassemble \
-; RUN: --args -O2 --allow-externally-defined-symbols \
-; RUN: | FileCheck %s --check-prefix=DIS
-
-; Compile using integrated assembler.
-; RUN: %p2i --filetype=iasm -i %s --target=mips32 --args -O2 \
-; RUN: --allow-externally-defined-symbols \
-; RUN: | FileCheck %s --check-prefix=IASM
-
-; Show bytes in assembled integrated code.
-; RUN: %p2i --filetype=iasm -i %s --target=mips32 --assemble --disassemble \
-; RUN: --args -O2 --allow-externally-defined-symbols \
-; RUN: | FileCheck %s --check-prefix=DIS
-
-declare i16 @llvm.bswap.i16(i16)
-declare i32 @llvm.bswap.i32(i32)
-declare i64 @llvm.bswap.i64(i64)
-declare i32 @llvm.ctlz.i32(i32, i1)
-declare i64 @llvm.ctlz.i64(i64, i1)
-declare i32 @llvm.cttz.i32(i32, i1)
-declare i64 @llvm.cttz.i64(i64, i1)
-declare void @llvm.trap()
-
-define internal i32 @encBswap16(i32 %x) {
-entry:
- %x_trunc = trunc i32 %x to i16
- %r = call i16 @llvm.bswap.i16(i16 %x_trunc)
- %r_zext = zext i16 %r to i32
- ret i32 %r_zext
-}
-
-; ASM-LABEL: encBswap16
-; ASM-NEXT: .LencBswap16$entry:
-; ASM-NEXT: andi $a0, $a0, 65535
-; ASM-NEXT: sll $v0, $a0, 8
-; ASM-NEXT: lui $v1, 255
-; ASM-NEXT: and $v0, $v0, $v1
-; ASM-NEXT: sll $a0, $a0, 24
-; ASM-NEXT: or $v0, $a0, $v0
-; ASM-NEXT: srl $v0, $v0, 16
-; ASM-NEXT: andi $v0, $v0, 65535
-; ASM-NEXT: jr $ra
-
-; DIS-LABEL: <encBswap16>:
-; DIS-NEXT: 3084ffff andi a0,a0,0xffff
-; DIS-NEXT: 00041200 sll v0,a0,0x8
-; DIS-NEXT: 3c0300ff lui v1,0xff
-; DIS-NEXT: 00431024 and v0,v0,v1
-; DIS-NEXT: 00042600 sll a0,a0,0x18
-; DIS-NEXT: 00821025 or v0,a0,v0
-; DIS-NEXT: 00021402 srl v0,v0,0x10
-; DIS-NEXT: 3042ffff andi v0,v0,0xffff
-; DIS-NEXT: 03e00008 jr ra
-
-; IASM-LABEL: encBswap16
-; IASM-NEXT: .LencBswap16$entry:
-; IASM-NEXT: .byte 0xff
-; IASM-NEXT: .byte 0xff
-; IASM-NEXT: .byte 0x84
-; IASM-NEXT: .byte 0x30
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x12
-; IASM-NEXT: .byte 0x4
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xff
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x3
-; IASM-NEXT: .byte 0x3c
-; IASM-NEXT: .byte 0x24
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0x43
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x26
-; IASM-NEXT: .byte 0x4
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x25
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0x82
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x2
-; IASM-NEXT: .byte 0x14
-; IASM-NEXT: .byte 0x2
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xff
-; IASM-NEXT: .byte 0xff
-; IASM-NEXT: .byte 0x42
-; IASM-NEXT: .byte 0x30
-; IASM-NEXT: .byte 0x8
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xe0
-; IASM-NEXT: .byte 0x3
-
-define internal i32 @encBswap32(i32 %x) {
-entry:
- %r = call i32 @llvm.bswap.i32(i32 %x)
- ret i32 %r
-}
-
-; ASM-LABEL: encBswap32
-; ASM-NEXT: .LencBswap32$entry:
-; ASM-NEXT: srl $v0, $a0, 24
-; ASM-NEXT: srl $v1, $a0, 8
-; ASM-NEXT: andi $v1, $v1, 65280
-; ASM-NEXT: or $v0, $v1, $v0
-; ASM-NEXT: sll $v1, $a0, 8
-; ASM-NEXT: lui $a1, 255
-; ASM-NEXT: and $v1, $v1, $a1
-; ASM-NEXT: sll $a0, $a0, 24
-; ASM-NEXT: or $v1, $a0, $v1
-; ASM-NEXT: or $v1, $v1, $v0
-; ASM-NEXT: move $v0, $v1
-; ASM-NEXT: jr $ra
-
-; DIS-LABEL: <encBswap32>:
-; DIS-NEXT: 00041602 srl v0,a0,0x18
-; DIS-NEXT: 00041a02 srl v1,a0,0x8
-; DIS-NEXT: 3063ff00 andi v1,v1,0xff00
-; DIS-NEXT: 00621025 or v0,v1,v0
-; DIS-NEXT: 00041a00 sll v1,a0,0x8
-; DIS-NEXT: 3c0500ff lui a1,0xff
-; DIS-NEXT: 00651824 and v1,v1,a1
-; DIS-NEXT: 00042600 sll a0,a0,0x18
-; DIS-NEXT: 00831825 or v1,a0,v1
-; DIS-NEXT: 00621825 or v1,v1,v0
-; DIS-NEXT: 00601021 move v0,v1
-; DIS-NEXT: 03e00008 jr ra
-
-; IASM-LABEL: encBswap32
-; IASM-NEXT: .LencBswap32$entry:
-; IASM-NEXT: .byte 0x2
-; IASM-NEXT: .byte 0x16
-; IASM-NEXT: .byte 0x4
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x2
-; IASM-NEXT: .byte 0x1a
-; IASM-NEXT: .byte 0x4
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xff
-; IASM-NEXT: .byte 0x63
-; IASM-NEXT: .byte 0x30
-; IASM-NEXT: .byte 0x25
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0x62
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x1a
-; IASM-NEXT: .byte 0x4
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xff
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x5
-; IASM-NEXT: .byte 0x3c
-; IASM-NEXT: .byte 0x24
-; IASM-NEXT: .byte 0x18
-; IASM-NEXT: .byte 0x65
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x26
-; IASM-NEXT: .byte 0x4
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x25
-; IASM-NEXT: .byte 0x18
-; IASM-NEXT: .byte 0x83
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x25
-; IASM-NEXT: .byte 0x18
-; IASM-NEXT: .byte 0x62
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x21
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0x60
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x8
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xe0
-; IASM-NEXT: .byte 0x3
-
-define internal i64 @encBswap64(i64 %x) {
-entry:
- %r = call i64 @llvm.bswap.i64(i64 %x)
- ret i64 %r
-}
-
-; ASM-LABEL: encBswap64
-; ASM-NEXT: .LencBswap64$entry:
-; ASM-NEXT: sll $v0, $a1, 8
-; ASM-NEXT: srl $v1, $a1, 24
-; ASM-NEXT: srl $a2, $a1, 8
-; ASM-NEXT: andi $a2, $a2, 65280
-; ASM-NEXT: lui $a3, 255
-; ASM-NEXT: or $a2, $a2, $v1
-; ASM-NEXT: and $v0, $v0, $a3
-; ASM-NEXT: sll $a1, $a1, 24
-; ASM-NEXT: or $a1, $a1, $v0
-; ASM-NEXT: srl $v0, $a0, 24
-; ASM-NEXT: srl $v1, $a0, 8
-; ASM-NEXT: andi $v1, $v1, 65280
-; ASM-NEXT: or $a1, $a1, $a2
-; ASM-NEXT: or $v1, $v1, $v0
-; ASM-NEXT: sll $v0, $a0, 8
-; ASM-NEXT: and $v0, $v0, $a3
-; ASM-NEXT: sll $a0, $a0, 24
-; ASM-NEXT: or $a0, $a0, $v0
-; ASM-NEXT: or $a0, $a0, $v1
-; ASM-NEXT: move $v0, $a1
-; ASM-NEXT: move $v1, $a0
-; ASM-NEXT: jr $ra
-
-; DIS-LABEL: <encBswap64>:
-; DIS-NEXT: 00051200 sll v0,a1,0x8
-; DIS-NEXT: 00051e02 srl v1,a1,0x18
-; DIS-NEXT: 00053202 srl a2,a1,0x8
-; DIS-NEXT: 30c6ff00 andi a2,a2,0xff00
-; DIS-NEXT: 3c0700ff lui a3,0xff
-; DIS-NEXT: 00c33025 or a2,a2,v1
-; DIS-NEXT: 00471024 and v0,v0,a3
-; DIS-NEXT: 00052e00 sll a1,a1,0x18
-; DIS-NEXT: 00a22825 or a1,a1,v0
-; DIS-NEXT: 00041602 srl v0,a0,0x18
-; DIS-NEXT: 00041a02 srl v1,a0,0x8
-; DIS-NEXT: 3063ff00 andi v1,v1,0xff00
-; DIS-NEXT: 00a62825 or a1,a1,a2
-; DIS-NEXT: 00621825 or v1,v1,v0
-; DIS-NEXT: 00041200 sll v0,a0,0x8
-; DIS-NEXT: 00471024 and v0,v0,a3
-; DIS-NEXT: 00042600 sll a0,a0,0x18
-; DIS-NEXT: 00822025 or a0,a0,v0
-; DIS-NEXT: 00832025 or a0,a0,v1
-; DIS-NEXT: 00a01021 move v0,a1
-; DIS-NEXT: 00801821 move v1,a0
-; DIS-NEXT: 03e00008 jr ra
-
-
-; IASM-LABEL: encBswap64
-; IASM-NEXT: .LencBswap64$entry:
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x12
-; IASM-NEXT: .byte 0x5
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x2
-; IASM-NEXT: .byte 0x1e
-; IASM-NEXT: .byte 0x5
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x2
-; IASM-NEXT: .byte 0x32
-; IASM-NEXT: .byte 0x5
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xff
-; IASM-NEXT: .byte 0xc6
-; IASM-NEXT: .byte 0x30
-; IASM-NEXT: .byte 0xff
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x7
-; IASM-NEXT: .byte 0x3c
-; IASM-NEXT: .byte 0x25
-; IASM-NEXT: .byte 0x30
-; IASM-NEXT: .byte 0xc3
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x24
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0x47
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x2e
-; IASM-NEXT: .byte 0x5
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x25
-; IASM-NEXT: .byte 0x28
-; IASM-NEXT: .byte 0xa2
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x2
-; IASM-NEXT: .byte 0x16
-; IASM-NEXT: .byte 0x4
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x2
-; IASM-NEXT: .byte 0x1a
-; IASM-NEXT: .byte 0x4
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xff
-; IASM-NEXT: .byte 0x63
-; IASM-NEXT: .byte 0x30
-; IASM-NEXT: .byte 0x25
-; IASM-NEXT: .byte 0x28
-; IASM-NEXT: .byte 0xa6
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x25
-; IASM-NEXT: .byte 0x18
-; IASM-NEXT: .byte 0x62
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x12
-; IASM-NEXT: .byte 0x4
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x24
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0x47
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x26
-; IASM-NEXT: .byte 0x4
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x25
-; IASM-NEXT: .byte 0x20
-; IASM-NEXT: .byte 0x82
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x25
-; IASM-NEXT: .byte 0x20
-; IASM-NEXT: .byte 0x83
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x21
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0xa0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x21
-; IASM-NEXT: .byte 0x18
-; IASM-NEXT: .byte 0x80
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x8
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xe0
-; IASM-NEXT: .byte 0x3
-
-define internal i64 @encBswap64Undef() {
-entry:
- %r = call i64 @llvm.bswap.i64(i64 undef)
- ret i64 %r
-}
-
-; ASM-LABEL: encBswap64Undef
-; ASM-NEXT: .LencBswap64Undef$entry:
-; ASM-NEXT: # $zero = def.pseudo
-; ASM-NEXT: addiu $v0, $zero, 0
-; ASM-NEXT: # $zero = def.pseudo
-; ASM-NEXT: addiu $v1, $zero, 0
-; ASM-NEXT: sll $a0, $v1, 8
-; ASM-NEXT: srl $a1, $v1, 24
-; ASM-NEXT: srl $a2, $v1, 8
-; ASM-NEXT: andi $a2, $a2, 65280
-; ASM-NEXT: lui $a3, 255
-; ASM-NEXT: or $a2, $a2, $a1
-; ASM-NEXT: and $a0, $a0, $a3
-; ASM-NEXT: sll $v1, $v1, 24
-; ASM-NEXT: or $v1, $v1, $a0
-; ASM-NEXT: srl $a0, $v0, 24
-; ASM-NEXT: srl $a1, $v0, 8
-; ASM-NEXT: andi $a1, $a1, 65280
-; ASM-NEXT: or $v1, $v1, $a2
-; ASM-NEXT: or $a1, $a1, $a0
-; ASM-NEXT: sll $a0, $v0, 8
-; ASM-NEXT: and $a0, $a0, $a3
-; ASM-NEXT: sll $v0, $v0, 24
-; ASM-NEXT: or $v0, $v0, $a0
-; ASM-NEXT: or $v0, $v0, $a1
-; ASM-NEXT: move $a0, $v0
-; ASM-NEXT: move $v0, $v1
-; ASM-NEXT: move $v1, $a0
-; ASM-NEXT: jr $ra
-
-; DIS-LABEL: <encBswap64Undef>:
-; DIS-NEXT: 24020000 li v0,0
-; DIS-NEXT: 24030000 li v1,0
-; DIS-NEXT: 00032200 sll a0,v1,0x8
-; DIS-NEXT: 00032e02 srl a1,v1,0x18
-; DIS-NEXT: 00033202 srl a2,v1,0x8
-; DIS-NEXT: 30c6ff00 andi a2,a2,0xff00
-; DIS-NEXT: 3c0700ff lui a3,0xff
-; DIS-NEXT: 00c53025 or a2,a2,a1
-; DIS-NEXT: 00872024 and a0,a0,a3
-; DIS-NEXT: 00031e00 sll v1,v1,0x18
-; DIS-NEXT: 00641825 or v1,v1,a0
-; DIS-NEXT: 00022602 srl a0,v0,0x18
-; DIS-NEXT: 00022a02 srl a1,v0,0x8
-; DIS-NEXT: 30a5ff00 andi a1,a1,0xff00
-; DIS-NEXT: 00661825 or v1,v1,a2
-; DIS-NEXT: 00a42825 or a1,a1,a0
-; DIS-NEXT: 00022200 sll a0,v0,0x8
-; DIS-NEXT: 00872024 and a0,a0,a3
-; DIS-NEXT: 00021600 sll v0,v0,0x18
-; DIS-NEXT: 00441025 or v0,v0,a0
-; DIS-NEXT: 00451025 or v0,v0,a1
-; DIS-NEXT: 00402021 move a0,v0
-; DIS-NEXT: 00601021 move v0,v1
-; DIS-NEXT: 00801821 move v1,a0
-; DIS-NEXT: 03e00008 jr ra
-
-; IASM-LABEL: encBswap64Undef
-; IASM-NEXT: .LencBswap64Undef$entry:
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x2
-; IASM-NEXT: .byte 0x24
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x3
-; IASM-NEXT: .byte 0x24
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x22
-; IASM-NEXT: .byte 0x3
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x2
-; IASM-NEXT: .byte 0x2e
-; IASM-NEXT: .byte 0x3
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x2
-; IASM-NEXT: .byte 0x32
-; IASM-NEXT: .byte 0x3
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xff
-; IASM-NEXT: .byte 0xc6
-; IASM-NEXT: .byte 0x30
-; IASM-NEXT: .byte 0xff
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x7
-; IASM-NEXT: .byte 0x3c
-; IASM-NEXT: .byte 0x25
-; IASM-NEXT: .byte 0x30
-; IASM-NEXT: .byte 0xc5
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x24
-; IASM-NEXT: .byte 0x20
-; IASM-NEXT: .byte 0x87
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x1e
-; IASM-NEXT: .byte 0x3
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x25
-; IASM-NEXT: .byte 0x18
-; IASM-NEXT: .byte 0x64
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x2
-; IASM-NEXT: .byte 0x26
-; IASM-NEXT: .byte 0x2
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x2
-; IASM-NEXT: .byte 0x2a
-; IASM-NEXT: .byte 0x2
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xff
-; IASM-NEXT: .byte 0xa5
-; IASM-NEXT: .byte 0x30
-; IASM-NEXT: .byte 0x25
-; IASM-NEXT: .byte 0x18
-; IASM-NEXT: .byte 0x66
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x25
-; IASM-NEXT: .byte 0x28
-; IASM-NEXT: .byte 0xa4
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x22
-; IASM-NEXT: .byte 0x2
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x24
-; IASM-NEXT: .byte 0x20
-; IASM-NEXT: .byte 0x87
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x16
-; IASM-NEXT: .byte 0x2
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x25
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0x44
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x25
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0x45
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x21
-; IASM-NEXT: .byte 0x20
-; IASM-NEXT: .byte 0x40
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x21
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0x60
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x21
-; IASM-NEXT: .byte 0x18
-; IASM-NEXT: .byte 0x80
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x8
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xe0
-; IASM-NEXT: .byte 0x3
-
-define internal i32 @encCtlz32(i32 %x) {
-entry:
- %r = call i32 @llvm.ctlz.i32(i32 %x, i1 false)
- ret i32 %r
-}
-
-; ASM-LABEL: encCtlz32
-; ASM-NEXT: .LencCtlz32$entry:
-; ASM-NEXT: clz $a0, $a0
-; ASM-NEXT: move $v0, $a0
-; ASM-NEXT: jr $ra
-
-; DIS-LABEL: <encCtlz32>:
-; DIS-NEXT: 70842020 clz a0,a0
-; DIS-NEXT: 00801021 move v0,a0
-; DIS-NEXT: 03e00008 jr ra
-
-; IASM-LABEL: encCtlz32
-; IASM-NEXT: .LencCtlz32$entry:
-; IASM-NEXT: .byte 0x20
-; IASM-NEXT: .byte 0x20
-; IASM-NEXT: .byte 0x84
-; IASM-NEXT: .byte 0x70
-; IASM-NEXT: .byte 0x21
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0x80
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x8
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xe0
-; IASM-NEXT: .byte 0x3
-
-define internal i32 @encCtlz32Const() {
-entry:
- %r = call i32 @llvm.ctlz.i32(i32 123456, i1 false)
- ret i32 %r
-}
-
-; ASM-LABEL: encCtlz32Const
-; ASM-NEXT: .LencCtlz32Const$entry:
-; ASM-NEXT: lui $v0, 1
-; ASM-NEXT: ori $v0, $v0, 57920
-; ASM-NEXT: clz $v0, $v0
-; ASM-NEXT: jr $ra
-
-; DIS-LABEL: <encCtlz32Const>:
-; DIS-NEXT: 3c020001 lui v0,0x1
-; DIS-NEXT: 3442e240 ori v0,v0,0xe240
-; DIS-NEXT: 70421020 clz v0,v0
-; DIS-NEXT: 03e00008 jr ra
-
-; IASM-LABEL: encCtlz32Const
-; IASM-NEXT: .LencCtlz32Const$entry:
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x2
-; IASM-NEXT: .byte 0x3c
-; IASM-NEXT: .byte 0x40
-; IASM-NEXT: .byte 0xe2
-; IASM-NEXT: .byte 0x42
-; IASM-NEXT: .byte 0x34
-; IASM-NEXT: .byte 0x20
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0x42
-; IASM-NEXT: .byte 0x70
-; IASM-NEXT: .byte 0x8
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xe0
-; IASM-NEXT: .byte 0x3
-
-define internal i64 @encCtlz64(i64 %x) {
-entry:
- %r = call i64 @llvm.ctlz.i64(i64 %x, i1 false)
- ret i64 %r
-}
-
-; ASM-LABEL: encCtlz64
-; ASM-NEXT: .LencCtlz64$entry:
-; ASM-NEXT: clz $v0, $a1
-; ASM-NEXT: clz $a0, $a0
-; ASM-NEXT: addiu $a0, $a0, 32
-; ASM-NEXT: movn $a0, $v0, $a1
-; ASM: addiu $v0, $zero, 0
-; ASM-NEXT: move $v1, $v0
-; ASM-NEXT: move $v0, $a0
-; ASM-NEXT: jr $ra
-
-; DIS-LABEL: <encCtlz64>:
-; DIS-NEXT: 70a21020 clz v0,a1
-; DIS-NEXT: 70842020 clz a0,a0
-; DIS-NEXT: 24840020 addiu a0,a0,32
-; DIS-NEXT: 0045200b movn a0,v0,a1
-; DIS-NEXT: 24020000 li v0,0
-; DIS-NEXT: 00401821 move v1,v0
-; DIS-NEXT: 00801021 move v0,a0
-; DIS-NEXT: 03e00008 jr ra
-
-; IASM-LABEL: encCtlz64
-; IASM-NEXT: .LencCtlz64$entry:
-; IASM-NEXT: .byte 0x20
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0xa2
-; IASM-NEXT: .byte 0x70
-; IASM-NEXT: .byte 0x20
-; IASM-NEXT: .byte 0x20
-; IASM-NEXT: .byte 0x84
-; IASM-NEXT: .byte 0x70
-; IASM-NEXT: .byte 0x20
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x84
-; IASM-NEXT: .byte 0x24
-; IASM-NEXT: .byte 0xb
-; IASM-NEXT: .byte 0x20
-; IASM-NEXT: .byte 0x45
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x2
-; IASM-NEXT: .byte 0x24
-; IASM-NEXT: .byte 0x21
-; IASM-NEXT: .byte 0x18
-; IASM-NEXT: .byte 0x40
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x21
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0x80
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x8
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xe0
-; IASM-NEXT: .byte 0x3
-
-define internal i32 @encCtlz64Const(i64 %x) {
-entry:
- %r = call i64 @llvm.ctlz.i64(i64 123456789012, i1 false)
- %r2 = trunc i64 %r to i32
- ret i32 %r2
-}
-
-; ASM-LABEL: encCtlz64Const
-; ASM-NEXT: .LencCtlz64Const$entry:
-; ASM-NEXT: # $zero = def.pseudo
-; ASM-NEXT: addiu $v0, $zero, 28
-; ASM-NEXT: lui $v1, 48793
-; ASM-NEXT: ori $v1, $v1, 6676
-; ASM-NEXT: clz $a0, $v0
-; ASM-NEXT: clz $v1, $v1
-; ASM-NEXT: addiu $v1, $v1, 32
-; ASM-NEXT: movn $v1, $a0, $v0
-; ASM-NEXT: move $v0, $v1
-; ASM-NEXT: jr $ra
-
-; DIS-LABEL: <encCtlz64Const>:
-; DIS-NEXT: 2402001c li v0,28
-; DIS-NEXT: 3c03be99 lui v1,0xbe99
-; DIS-NEXT: 34631a14 ori v1,v1,0x1a14
-; DIS-NEXT: 70442020 clz a0,v0
-; DIS-NEXT: 70631820 clz v1,v1
-; DIS-NEXT: 24630020 addiu v1,v1,32
-; DIS-NEXT: 0082180b movn v1,a0,v0
-; DIS-NEXT: 00601021 move v0,v1
-; DIS-NEXT: 03e00008 jr ra
-
-; IASM-LABEL: encCtlz64Const
-; IASM-NEXT: .LencCtlz64Const$entry:
-; IASM-NEXT: .byte 0x1c
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x2
-; IASM-NEXT: .byte 0x24
-; IASM-NEXT: .byte 0x99
-; IASM-NEXT: .byte 0xbe
-; IASM-NEXT: .byte 0x3
-; IASM-NEXT: .byte 0x3c
-; IASM-NEXT: .byte 0x14
-; IASM-NEXT: .byte 0x1a
-; IASM-NEXT: .byte 0x63
-; IASM-NEXT: .byte 0x34
-; IASM-NEXT: .byte 0x20
-; IASM-NEXT: .byte 0x20
-; IASM-NEXT: .byte 0x44
-; IASM-NEXT: .byte 0x70
-; IASM-NEXT: .byte 0x20
-; IASM-NEXT: .byte 0x18
-; IASM-NEXT: .byte 0x63
-; IASM-NEXT: .byte 0x70
-; IASM-NEXT: .byte 0x20
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x63
-; IASM-NEXT: .byte 0x24
-; IASM-NEXT: .byte 0xb
-; IASM-NEXT: .byte 0x18
-; IASM-NEXT: .byte 0x82
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x21
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0x60
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x8
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xe0
-; IASM-NEXT: .byte 0x3
-
-define internal i32 @encCttz32(i32 %x) {
-entry:
- %r = call i32 @llvm.cttz.i32(i32 %x, i1 false)
- ret i32 %r
-}
-
-; ASM-LABEL: encCttz32
-; ASM-NEXT: .LencCttz32$entry:
-; ASM-NEXT: addiu $v0, $a0, -1
-; ASM: nor $a0, $a0, $zero
-; ASM-NEXT: and $a0, $a0, $v0
-; ASM-NEXT: clz $a0, $a0
-; ASM: addiu $v0, $zero, 32
-; ASM-NEXT: subu $v0, $v0, $a0
-; ASM-NEXT: jr $ra
-
-; DIS-LABEL: <encCttz32>:
-; DIS-NEXT: 2482ffff addiu v0,a0,-1
-; DIS-NEXT: 00802027 nor a0,a0,zero
-; DIS-NEXT: 00822024 and a0,a0,v0
-; DIS-NEXT: 70842020 clz a0,a0
-; DIS-NEXT: 24020020 li v0,32
-; DIS-NEXT: 00441023 subu v0,v0,a0
-; DIS-NEXT: 03e00008 jr ra
-
-; IASM-LABEL: encCttz32
-; IASM-NEXT: .LencCttz32$entry:
-; IASM-NEXT: .byte 0xff
-; IASM-NEXT: .byte 0xff
-; IASM-NEXT: .byte 0x82
-; IASM-NEXT: .byte 0x24
-; IASM-NEXT: .byte 0x27
-; IASM-NEXT: .byte 0x20
-; IASM-NEXT: .byte 0x80
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x24
-; IASM-NEXT: .byte 0x20
-; IASM-NEXT: .byte 0x82
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x20
-; IASM-NEXT: .byte 0x20
-; IASM-NEXT: .byte 0x84
-; IASM-NEXT: .byte 0x70
-; IASM-NEXT: .byte 0x20
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x2
-; IASM-NEXT: .byte 0x24
-; IASM-NEXT: .byte 0x23
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0x44
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x8
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xe0
-; IASM-NEXT: .byte 0x3
-
-define internal i32 @encCttz32Const() {
-entry:
- %r = call i32 @llvm.cttz.i32(i32 123456, i1 false)
- ret i32 %r
-}
-
-; ASM-LABEL: encCttz32Const
-; ASM-NEXT: .LencCttz32Const$entry:
-; ASM-NEXT: lui $v0, 1
-; ASM-NEXT: ori $v0, $v0, 57920
-; ASM-NEXT: addiu $v1, $v0, -1
-; ASM: nor $v0, $v0, $zero
-; ASM-NEXT: and $v0, $v0, $v1
-; ASM-NEXT: clz $v0, $v0
-; ASM: addiu $v1, $zero, 32
-; ASM-NEXT: subu $v1, $v1, $v0
-; ASM-NEXT: move $v0, $v1
-; ASM-NEXT: jr $ra
-
-; DIS-LABEL: <encCttz32Const>:
-; DIS-NEXT: 3c020001 lui v0,0x1
-; DIS-NEXT: 3442e240 ori v0,v0,0xe240
-; DIS-NEXT: 2443ffff addiu v1,v0,-1
-; DIS-NEXT: 00401027 nor v0,v0,zero
-; DIS-NEXT: 00431024 and v0,v0,v1
-; DIS-NEXT: 70421020 clz v0,v0
-; DIS-NEXT: 24030020 li v1,32
-; DIS-NEXT: 00621823 subu v1,v1,v0
-; DIS-NEXT: 00601021 move v0,v1
-; DIS-NEXT: 03e00008 jr ra
-
-; IASM-LABEL: encCttz32Const:
-; IASM-NEXT: .LencCttz32Const$entry:
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x2
-; IASM-NEXT: .byte 0x3c
-; IASM-NEXT: .byte 0x40
-; IASM-NEXT: .byte 0xe2
-; IASM-NEXT: .byte 0x42
-; IASM-NEXT: .byte 0x34
-; IASM-NEXT: .byte 0xff
-; IASM-NEXT: .byte 0xff
-; IASM-NEXT: .byte 0x43
-; IASM-NEXT: .byte 0x24
-; IASM-NEXT: .byte 0x27
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0x40
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x24
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0x43
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x20
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0x42
-; IASM-NEXT: .byte 0x70
-; IASM-NEXT: .byte 0x20
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x3
-; IASM-NEXT: .byte 0x24
-; IASM-NEXT: .byte 0x23
-; IASM-NEXT: .byte 0x18
-; IASM-NEXT: .byte 0x62
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x21
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0x60
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x8
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xe0
-; IASM-NEXT: .byte 0x3
-
-define internal i64 @encCttz64(i64 %x) {
-entry:
- %r = call i64 @llvm.cttz.i64(i64 %x, i1 false)
- ret i64 %r
-}
-
-; ASM-LABEL: encCttz64
-; ASM-NEXT: .LencCttz64$entry:
-; ASM-NEXT: addiu $v0, $a1, -1
-; ASM: nor $a1, $a1, $zero
-; ASM-NEXT: and $a1, $a1, $v0
-; ASM-NEXT: clz $a1, $a1
-; ASM: addiu $v0, $zero, 64
-; ASM-NEXT: subu $v0, $v0, $a1
-; ASM-NEXT: addiu $v1, $a0, -1
-; ASM: nor $a1, $a0, $zero
-; ASM-NEXT: and $a1, $a1, $v1
-; ASM-NEXT: clz $a1, $a1
-; ASM: addiu $v1, $zero, 32
-; ASM-NEXT: subu $v1, $v1, $a1
-; ASM-NEXT: movn $v0, $v1, $a0
-; ASM: addiu $v1, $zero, 0
-; ASM-NEXT: jr $ra
-
-; DIS-LABEL: <encCttz64>:
-; DIS-NEXT: 24a2ffff addiu v0,a1,-1
-; DIS-NEXT: 00a02827 nor a1,a1,zero
-; DIS-NEXT: 00a22824 and a1,a1,v0
-; DIS-NEXT: 70a52820 clz a1,a1
-; DIS-NEXT: 24020040 li v0,64
-; DIS-NEXT: 00451023 subu v0,v0,a1
-; DIS-NEXT: 2483ffff addiu v1,a0,-1
-; DIS-NEXT: 00802827 nor a1,a0,zero
-; DIS-NEXT: 00a32824 and a1,a1,v1
-; DIS-NEXT: 70a52820 clz a1,a1
-; DIS-NEXT: 24030020 li v1,32
-; DIS-NEXT: 00651823 subu v1,v1,a1
-; DIS-NEXT: 0064100b movn v0,v1,a0
-; DIS-NEXT: 24030000 li v1,0
-; DIS-NEXT: 03e00008 jr ra
-; DIS-NEXT: 00000000 nop
-
-; IASM-LABEL: encCttz64:
-; IASM-NEXT: .LencCttz64$entry:
-; IASM-NEXT: .byte 0xff
-; IASM-NEXT: .byte 0xff
-; IASM-NEXT: .byte 0xa2
-; IASM-NEXT: .byte 0x24
-; IASM-NEXT: .byte 0x27
-; IASM-NEXT: .byte 0x28
-; IASM-NEXT: .byte 0xa0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x24
-; IASM-NEXT: .byte 0x28
-; IASM-NEXT: .byte 0xa2
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x20
-; IASM-NEXT: .byte 0x28
-; IASM-NEXT: .byte 0xa5
-; IASM-NEXT: .byte 0x70
-; IASM-NEXT: .byte 0x40
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x2
-; IASM-NEXT: .byte 0x24
-; IASM-NEXT: .byte 0x23
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0x45
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xff
-; IASM-NEXT: .byte 0xff
-; IASM-NEXT: .byte 0x83
-; IASM-NEXT: .byte 0x24
-; IASM-NEXT: .byte 0x27
-; IASM-NEXT: .byte 0x28
-; IASM-NEXT: .byte 0x80
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x24
-; IASM-NEXT: .byte 0x28
-; IASM-NEXT: .byte 0xa3
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x20
-; IASM-NEXT: .byte 0x28
-; IASM-NEXT: .byte 0xa5
-; IASM-NEXT: .byte 0x70
-; IASM-NEXT: .byte 0x20
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x3
-; IASM-NEXT: .byte 0x24
-; IASM-NEXT: .byte 0x23
-; IASM-NEXT: .byte 0x18
-; IASM-NEXT: .byte 0x65
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xb
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0x64
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x3
-; IASM-NEXT: .byte 0x24
-; IASM-NEXT: .byte 0x8
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xe0
-; IASM-NEXT: .byte 0x3
-
-define internal i64 @encCttz64Const(i64 %x) {
-entry:
- %r = call i64 @llvm.cttz.i64(i64 123456789012, i1 false)
- ret i64 %r
-}
-
-; ASM-LABEL: encCttz64Const
-; ASM-NEXT: .LencCttz64Const$entry:
-; ASM-NEXT: # $zero = def.pseudo
-; ASM-NEXT: addiu $v0, $zero, 28
-; ASM-NEXT: lui $v1, 48793
-; ASM-NEXT: ori $v1, $v1, 6676
-; ASM-NEXT: addiu $a0, $v0, -1
-; ASM: nor $v0, $v0, $zero
-; ASM-NEXT: and $v0, $v0, $a0
-; ASM-NEXT: clz $v0, $v0
-; ASM: addiu $a0, $zero, 64
-; ASM-NEXT: subu $a0, $a0, $v0
-; ASM-NEXT: addiu $v0, $v1, -1
-; ASM: nor $a1, $v1, $zero
-; ASM-NEXT: and $a1, $a1, $v0
-; ASM-NEXT: clz $a1, $a1
-; ASM: addiu $v0, $zero, 32
-; ASM-NEXT: subu $v0, $v0, $a1
-; ASM-NEXT: movn $a0, $v0, $v1
-; ASM: addiu $v0, $zero, 0
-; ASM-NEXT: move $v1, $v0
-; ASM-NEXT: move $v0, $a0
-; ASM-NEXT: jr $ra
-
-; DIS-LABEL: <encCttz64Const>:
-; DIS-NEXT: 2402001c li v0,28
-; DIS-NEXT: 3c03be99 lui v1,0xbe99
-; DIS-NEXT: 34631a14 ori v1,v1,0x1a14
-; DIS-NEXT: 2444ffff addiu a0,v0,-1
-; DIS-NEXT: 00401027 nor v0,v0,zero
-; DIS-NEXT: 00441024 and v0,v0,a0
-; DIS-NEXT: 70421020 clz v0,v0
-; DIS-NEXT: 24040040 li a0,64
-; DIS-NEXT: 00822023 subu a0,a0,v0
-; DIS-NEXT: 2462ffff addiu v0,v1,-1
-; DIS-NEXT: 00602827 nor a1,v1,zero
-; DIS-NEXT: 00a22824 and a1,a1,v0
-; DIS-NEXT: 70a52820 clz a1,a1
-; DIS-NEXT: 24020020 li v0,32
-; DIS-NEXT: 00451023 subu v0,v0,a1
-; DIS-NEXT: 0043200b movn a0,v0,v1
-; DIS-NEXT: 24020000 li v0,0
-; DIS-NEXT: 00401821 move v1,v0
-; DIS-NEXT: 00801021 move v0,a0
-; DIS-NEXT: 03e00008 jr ra
-
-; IASM-LABEL: encCttz64Const:
-; IASM-NEXT: .LencCttz64Const$entry:
-; IASM-NEXT: .byte 0x1c
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x2
-; IASM-NEXT: .byte 0x24
-; IASM-NEXT: .byte 0x99
-; IASM-NEXT: .byte 0xbe
-; IASM-NEXT: .byte 0x3
-; IASM-NEXT: .byte 0x3c
-; IASM-NEXT: .byte 0x14
-; IASM-NEXT: .byte 0x1a
-; IASM-NEXT: .byte 0x63
-; IASM-NEXT: .byte 0x34
-; IASM-NEXT: .byte 0xff
-; IASM-NEXT: .byte 0xff
-; IASM-NEXT: .byte 0x44
-; IASM-NEXT: .byte 0x24
-; IASM-NEXT: .byte 0x27
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0x40
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x24
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0x44
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x20
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0x42
-; IASM-NEXT: .byte 0x70
-; IASM-NEXT: .byte 0x40
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x4
-; IASM-NEXT: .byte 0x24
-; IASM-NEXT: .byte 0x23
-; IASM-NEXT: .byte 0x20
-; IASM-NEXT: .byte 0x82
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xff
-; IASM-NEXT: .byte 0xff
-; IASM-NEXT: .byte 0x62
-; IASM-NEXT: .byte 0x24
-; IASM-NEXT: .byte 0x27
-; IASM-NEXT: .byte 0x28
-; IASM-NEXT: .byte 0x60
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x24
-; IASM-NEXT: .byte 0x28
-; IASM-NEXT: .byte 0xa2
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x20
-; IASM-NEXT: .byte 0x28
-; IASM-NEXT: .byte 0xa5
-; IASM-NEXT: .byte 0x70
-; IASM-NEXT: .byte 0x20
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x2
-; IASM-NEXT: .byte 0x24
-; IASM-NEXT: .byte 0x23
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0x45
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xb
-; IASM-NEXT: .byte 0x20
-; IASM-NEXT: .byte 0x43
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x2
-; IASM-NEXT: .byte 0x24
-; IASM-NEXT: .byte 0x21
-; IASM-NEXT: .byte 0x18
-; IASM-NEXT: .byte 0x40
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x21
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0x80
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x8
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xe0
-; IASM-NEXT: .byte 0x3
-
-define internal void @encTrap() {
- unreachable
-}
-
-; ASM-LABEL: encTrap
-; ASM-NEXT: .LencTrap$__0:
-; ASM: teq $zero, $zero, 0
-
-; DIS-LABEL: <encTrap>:
-; DIS-NEXT: 00000034 teq zero,zero
-
-; IASM-LABEL: encTrap:
-; IASM-NEXT: .LencTrap$__0:
-; IASM-NEXT: .byte 0x34
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
diff --git a/third_party/subzero/tests_lit/assembler/mips32/encoding_test_arith.ll b/third_party/subzero/tests_lit/assembler/mips32/encoding_test_arith.ll
deleted file mode 100644
index eb8266e..0000000
--- a/third_party/subzero/tests_lit/assembler/mips32/encoding_test_arith.ll
+++ /dev/null
@@ -1,172 +0,0 @@
-; Test encoding of MIPS32 arithmetic instructions
-
-; REQUIRES: allow_dump
-
-; Compile using standalone assembler.
-; RUN: %p2i --filetype=asm -i %s --target=mips32 --args -O2 \
-; RUN: --allow-externally-defined-symbols \
-; RUN: | FileCheck %s --check-prefix=ASM
-
-; Show bytes in assembled standalone code.
-; RUN: %p2i --filetype=asm -i %s --target=mips32 --assemble --disassemble \
-; RUN: --args -O2 --allow-externally-defined-symbols \
-; RUN: | FileCheck %s --check-prefix=DIS
-
-; Compile using integrated assembler.
-; RUN: %p2i --filetype=iasm -i %s --target=mips32 --args -O2 \
-; RUN: --allow-externally-defined-symbols \
-; RUN: | FileCheck %s --check-prefix=IASM
-
-; Show bytes in assembled integrated code.
-; RUN: %p2i --filetype=iasm -i %s --target=mips32 --assemble --disassemble \
-; RUN: --args -O2 --allow-externally-defined-symbols \
-; RUN: | FileCheck %s --check-prefix=DIS
-
-define internal i32 @test_01(i32 %a) {
- %v = add i32 %a, 1
- %v1 = and i32 %v, 1
- %v2 = or i32 %v1, 1
- %v3 = xor i32 %v2, 1
- ret i32 %v3
-}
-
-; ASM-LABEL: test_01:
-; ASM-NEXT: .Ltest_01$__0:
-; ASM-NEXT: addiu $a0, $a0, 1
-; ASM-NEXT: andi $a0, $a0, 1
-; ASM-NEXT: ori $a0, $a0, 1
-; ASM-NEXT: xori $a0, $a0, 1
-; ASM-NEXT: move $v0, $a0
-; ASM-NEXT: jr $ra
-
-; DIS-LABEL:00000000 <test_01>:
-; DIS-NEXT: 0: 24840001 addiu a0,a0,1
-; DIS-NEXT: 4: 30840001 andi a0,a0,0x1
-; DIS-NEXT: 8: 34840001 ori a0,a0,0x1
-; DIS-NEXT: c: 38840001 xori a0,a0,0x1
-; DIS-NEXT: 10: 00801021 move v0,a0
-; DIS-NEXT: 14: 03e00008 jr ra
-; DIS-NEXT: 18: 00000000 nop
-
-; IASM-LABEL: test_01:
-; IASM-LABEL: .Ltest_01$__0:
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x84
-; IASM-NEXT: .byte 0x24
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x84
-; IASM-NEXT: .byte 0x30
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x84
-; IASM-NEXT: .byte 0x34
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x84
-; IASM-NEXT: .byte 0x38
-; IASM-NEXT: .byte 0x21
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0x80
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x8
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xe0
-; IASM-NEXT: .byte 0x3
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-
-define internal i32 @test_02(i32 %a) {
- %cmp = icmp eq i32 %a, 9
- %cmp.ret_ext = zext i1 %cmp to i32
- ret i32 %cmp.ret_ext
-}
-
-; ASM-LABEL: test_02:
-; ASM-NEXT: .Ltest_02$__0:
-; ASM-NEXT: # $zero = def.pseudo
-; ASM-NEXT: addiu $v0, $zero, 9
-; ASM-NEXT: xor $a0, $a0, $v0
-; ASM-NEXT: sltiu $a0, $a0, 1
-; ASM-NEXT: andi $a0, $a0, 1
-; ASM-NEXT: move $v0, $a0
-; ASM-NEXT: jr $ra
-
-; DIS-LABEL:00000020 <test_02>:
-; DIS-NEXT: 20: 24020009 li v0,9
-; DIS-NEXT: 24: 00822026 xor a0,a0,v0
-; DIS-NEXT: 28: 2c840001 sltiu a0,a0,1
-; DIS-NEXT: 2c: 30840001 andi a0,a0,0x1
-; DIS-NEXT: 30: 00801021 move v0,a0
-; DIS-NEXT: 34: 03e00008 jr ra
-; DIS-NEXT: 38: 00000000 nop
-
-; IASM-LABEL: test_02:
-; IASM-LABEL: .Ltest_02$__0:
-; IASM-NEXT: .byte 0x9
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x2
-; IASM-NEXT: .byte 0x24
-; IASM-NEXT: .byte 0x26
-; IASM-NEXT: .byte 0x20
-; IASM-NEXT: .byte 0x82
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x84
-; IASM-NEXT: .byte 0x2c
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x84
-; IASM-NEXT: .byte 0x30
-; IASM-NEXT: .byte 0x21
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0x80
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x8
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xe0
-; IASM-NEXT: .byte 0x3
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-
-define internal i32 @ashrImm(i32 %val, i32 %shift) {
-entry:
- %result = ashr i32 %val, %shift
- ret i32 %result
-}
-
-; ASM-LABEL: ashrImm:
-; ASM-NEXT: .LashrImm$entry:
-; ASM-NEXT: srav $a0, $a0, $a1
-; ASM-NEXT: move $v0, $a0
-; ASM-NEXT: jr $ra
-
-; DIS-LABEL: <ashrImm>:
-; DIS-NEXT: 00a42007 srav a0,a0,a1
-; DIS-NEXT: 00801021 move v0,a0
-; DIS-NEXT: 03e00008 jr ra
-
-; IASM-LABEL: ashrImm:
-; IASM-NEXT: .LashrImm$entry:
-; IASM-NEXT: .byte 0x7
-; IASM-NEXT: .byte 0x20
-; IASM-NEXT: .byte 0xa4
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x21
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0x80
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x8
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xe0
-; IASM-NEXT: .byte 0x3
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
diff --git a/third_party/subzero/tests_lit/assembler/mips32/encoding_test_arith_fp.ll b/third_party/subzero/tests_lit/assembler/mips32/encoding_test_arith_fp.ll
deleted file mode 100644
index 4e2ea84..0000000
--- a/third_party/subzero/tests_lit/assembler/mips32/encoding_test_arith_fp.ll
+++ /dev/null
@@ -1,545 +0,0 @@
-; Test encoding of MIPS32 floating point arithmetic instructions
-
-; REQUIRES: allow_dump
-
-; Compile using standalone assembler.
-; RUN: %p2i --filetype=asm -i %s --target=mips32 --args -O2 \
-; RUN: --allow-externally-defined-symbols \
-; RUN: | FileCheck %s --check-prefix=ASM
-
-; Show bytes in assembled standalone code.
-; RUN: %p2i --filetype=asm -i %s --target=mips32 --assemble --disassemble \
-; RUN: --args -O2 --allow-externally-defined-symbols \
-; RUN: | FileCheck %s --check-prefix=DIS
-
-; Compile using integrated assembler.
-; RUN: %p2i --filetype=iasm -i %s --target=mips32 --args -O2 \
-; RUN: --allow-externally-defined-symbols \
-; RUN: | FileCheck %s --check-prefix=IASM
-
-; Show bytes in assembled integrated code.
-; RUN: %p2i --filetype=iasm -i %s --target=mips32 --assemble --disassemble \
-; RUN: --args -O2 --allow-externally-defined-symbols \
-; RUN: | FileCheck %s --check-prefix=DIS
-
-declare float @llvm.fabs.f32(float)
-declare double @llvm.fabs.f64(double)
-declare float @llvm.sqrt.f32(float)
-declare double @llvm.sqrt.f64(double)
-
-define internal float @encAbsFloat(float %a) {
-entry:
- %c = call float @llvm.fabs.f32(float %a)
- ret float %c
-}
-
-; ASM-LABEL: encAbsFloat
-; ASM-NEXT: .LencAbsFloat$entry:
-; ASM-NEXT: abs.s $f12, $f12
-; ASM-NEXT: mov.s $f0, $f12
-; ASM-NEXT: jr $ra
-
-; DIS-LABEL: 00000000 <encAbsFloat>:
-; DIS-NEXT: 0: 46006305 abs.s $f12,$f12
-; DIS-NEXT: 4: 46006006 mov.s $f0,$f12
-; DIS-NEXT: 8: 03e00008 jr ra
-; DIS-NEXT: c: 00000000 nop
-
-; IASM-LABEL: encAbsFloat:
-; IASM-NEXT: .LencAbsFloat$entry:
-; IASM-NEXT: .byte 0x5
-; IASM-NEXT: .byte 0x63
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x46
-; IASM-NEXT: .byte 0x6
-; IASM-NEXT: .byte 0x60
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x46
-; IASM-NEXT: .byte 0x8
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xe0
-; IASM-NEXT: .byte 0x3
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-
-define internal double @encAbsDouble(double %a) {
-entry:
- %c = call double @llvm.fabs.f64(double %a)
- ret double %c
-}
-
-; ASM-LABEL: encAbsDouble:
-; ASM-NEXT: .LencAbsDouble$entry:
-; ASM-NEXT: abs.d $f12, $f12
-; ASM-NEXT: mov.d $f0, $f12
-; ASM-NEXT: jr $ra
-
-; DIS-LABEL: 00000010 <encAbsDouble>:
-; DIS-NEXT: 10: 46206305 abs.d $f12,$f12
-; DIS-NEXT: 14: 46206006 mov.d $f0,$f12
-; DIS-NEXT: 18: 03e00008 jr ra
-; DIS-NEXT: 1c: 00000000 nop
-
-; IASM-LABEL: encAbsDouble:
-; IASM-NEXT: .LencAbsDouble$entry:
-; IASM-NEXT: .byte 0x5
-; IASM-NEXT: .byte 0x63
-; IASM-NEXT: .byte 0x20
-; IASM-NEXT: .byte 0x46
-; IASM-NEXT: .byte 0x6
-; IASM-NEXT: .byte 0x60
-; IASM-NEXT: .byte 0x20
-; IASM-NEXT: .byte 0x46
-; IASM-NEXT: .byte 0x8
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xe0
-; IASM-NEXT: .byte 0x3
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-
-define internal float @encAddFloat(float %a, float %b) {
-entry:
- %c = fadd float %a, %b
- ret float %c
-}
-
-; ASM-LABEL: encAddFloat
-; ASM-NEXT: .LencAddFloat$entry:
-; ASM-NEXT: add.s $f12, $f12, $f14
-; ASM-NEXT: mov.s $f0, $f12
-; ASM-NEXT: jr $ra
-
-; DIS-LABEL: 00000020 <encAddFloat>:
-; DIS-NEXT: 20: 460e6300 add.s $f12,$f12,$f14
-; DIS-NEXT: 24: 46006006 mov.s $f0,$f12
-; DIS-NEXT: 28: 03e00008 jr ra
-; DIS-NEXT: 2c: 00000000 nop
-
-; IASM-LABEL: encAddFloat:
-; IASM-NEXT: .LencAddFloat$entry:
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x63
-; IASM-NEXT: .byte 0xe
-; IASM-NEXT: .byte 0x46
-; IASM-NEXT: .byte 0x6
-; IASM-NEXT: .byte 0x60
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x46
-; IASM-NEXT: .byte 0x8
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xe0
-; IASM-NEXT: .byte 0x3
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-
-define internal double @encAddDouble(double %a, double %b) {
-entry:
- %c = fadd double %a, %b
- ret double %c
-}
-
-; ASM-LABEL: encAddDouble
-; ASM-NEXT: .LencAddDouble$entry:
-; ASM-NEXT: add.d $f12, $f12, $f14
-; ASM-NEXT: mov.d $f0, $f12
-; ASM-NEXT: jr $ra
-
-; DIS-LABEL: 00000030 <encAddDouble>:
-; DIS-NEXT: 30: 462e6300 add.d $f12,$f12,$f14
-; DIS-NEXT: 34: 46206006 mov.d $f0,$f12
-; DIS-NEXT: 38: 03e00008 jr ra
-; DIS-NEXT: 3c: 00000000 nop
-
-; IASM-LABEL: encAddDouble:
-; IASM-NEXT: .LencAddDouble$entry:
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x63
-; IASM-NEXT: .byte 0x2e
-; IASM-NEXT: .byte 0x46
-; IASM-NEXT: .byte 0x6
-; IASM-NEXT: .byte 0x60
-; IASM-NEXT: .byte 0x20
-; IASM-NEXT: .byte 0x46
-; IASM-NEXT: .byte 0x8
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xe0
-; IASM-NEXT: .byte 0x3
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-
-define internal float @encDivFloat(float %a, float %b) {
-entry:
- %c = fdiv float %a, %b
- ret float %c
-}
-
-; ASM-LABEL: encDivFloat
-; ASM-NEXT: .LencDivFloat$entry:
-; ASM-NEXT: div.s $f12, $f12, $f14
-; ASM-NEXT: mov.s $f0, $f12
-; ASM-NEXT: jr $ra
-
-; DIS-LABEL: 00000040 <encDivFloat>:
-; DIS-NEXT: 40: 460e6303 div.s $f12,$f12,$f14
-; DIS-NEXT: 44: 46006006 mov.s $f0,$f12
-; DIS-NEXT: 48: 03e00008 jr ra
-; DIS-NEXT: 4c: 00000000 nop
-
-; IASM-LABEL: encDivFloat:
-; IASM-NEXT: .LencDivFloat$entry:
-; IASM-NEXT: .byte 0x3
-; IASM-NEXT: .byte 0x63
-; IASM-NEXT: .byte 0xe
-; IASM-NEXT: .byte 0x46
-; IASM-NEXT: .byte 0x6
-; IASM-NEXT: .byte 0x60
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x46
-; IASM-NEXT: .byte 0x8
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xe0
-; IASM-NEXT: .byte 0x3
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-
-define internal double @encDivDouble(double %a, double %b) {
-entry:
- %c = fdiv double %a, %b
- ret double %c
-}
-
-; ASM-LABEL: encDivDouble
-; ASM-NEXT: .LencDivDouble$entry:
-; ASM-NEXT: div.d $f12, $f12, $f14
-; ASM-NEXT: mov.d $f0, $f12
-; ASM-NEXT: jr $ra
-
-; DIS-LABEL: 00000050 <encDivDouble>:
-; DIS-NEXT: 50: 462e6303 div.d $f12,$f12,$f14
-; DIS-NEXT: 54: 46206006 mov.d $f0,$f12
-; DIS-NEXT: 58: 03e00008 jr ra
-; DIS-NEXT: 5c: 00000000 nop
-
-; IASM-LABEL: encDivDouble:
-; IASM-NEXT: .LencDivDouble$entry:
-; IASM-NEXT: .byte 0x3
-; IASM-NEXT: .byte 0x63
-; IASM-NEXT: .byte 0x2e
-; IASM-NEXT: .byte 0x46
-; IASM-NEXT: .byte 0x6
-; IASM-NEXT: .byte 0x60
-; IASM-NEXT: .byte 0x20
-; IASM-NEXT: .byte 0x46
-; IASM-NEXT: .byte 0x8
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xe0
-; IASM-NEXT: .byte 0x3
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-
-define internal float @encMulFloat(float %a, float %b) {
-entry:
- %c = fmul float %a, %b
- ret float %c
-}
-
-; ASM-LABEL: encMulFloat
-; ASM-NEXT: .LencMulFloat$entry:
-; ASM-NEXT: mul.s $f12, $f12, $f14
-; ASM-NEXT: mov.s $f0, $f12
-; ASM-NEXT: jr $ra
-
-; DIS-LABEL: 00000060 <encMulFloat>:
-; DIS-NEXT: 60: 460e6302 mul.s $f12,$f12,$f14
-; DIS-NEXT: 64: 46006006 mov.s $f0,$f12
-; DIS-NEXT: 68: 03e00008 jr ra
-; DIS-NEXT: 6c: 00000000 nop
-
-; IASM-LABEL: encMulFloat:
-; IASM-NEXT: .LencMulFloat$entry:
-; IASM-NEXT: .byte 0x2
-; IASM-NEXT: .byte 0x63
-; IASM-NEXT: .byte 0xe
-; IASM-NEXT: .byte 0x46
-; IASM-NEXT: .byte 0x6
-; IASM-NEXT: .byte 0x60
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x46
-; IASM-NEXT: .byte 0x8
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xe0
-; IASM-NEXT: .byte 0x3
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-
-define internal double @encMulDouble(double %a, double %b) {
-entry:
- %c = fmul double %a, %b
- ret double %c
-}
-
-; ASM-LABEL: encMulDouble
-; ASM-NEXT: .LencMulDouble$entry:
-; ASM-NEXT: mul.d $f12, $f12, $f14
-; ASM-NEXT: mov.d $f0, $f12
-; ASM-NEXT: jr $ra
-
-; DIS-LABEL: 00000070 <encMulDouble>:
-; DIS-NEXT: 70: 462e6302 mul.d $f12,$f12,$f14
-; DIS-NEXT: 74: 46206006 mov.d $f0,$f12
-; DIS-NEXT: 78: 03e00008 jr ra
-; DIS-NEXT: 7c: 00000000 nop
-
-; IASM-LABEL: encMulDouble:
-; IASM-NEXT: .LencMulDouble$entry:
-; IASM-NEXT: .byte 0x2
-; IASM-NEXT: .byte 0x63
-; IASM-NEXT: .byte 0x2e
-; IASM-NEXT: .byte 0x46
-; IASM-NEXT: .byte 0x6
-; IASM-NEXT: .byte 0x60
-; IASM-NEXT: .byte 0x20
-; IASM-NEXT: .byte 0x46
-; IASM-NEXT: .byte 0x8
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xe0
-; IASM-NEXT: .byte 0x3
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-
-define internal float @encSqrtFloat(float %a) {
-entry:
- %c = call float @llvm.sqrt.f32(float %a)
- ret float %c
-}
-
-; ASM-LABEL: encSqrtFloat
-; ASM-NEXT: .LencSqrtFloat$entry:
-; ASM-NEXT: sqrt.s $f12, $f12
-; ASM-NEXT: mov.s $f0, $f12
-; ASM-NEXT: jr $ra
-
-; DIS-LABEL: 00000080 <encSqrtFloat>:
-; DIS-NEXT: 80: 46006304 sqrt.s $f12,$f12
-; DIS-NEXT: 84: 46006006 mov.s $f0,$f12
-; DIS-NEXT: 88: 03e00008 jr ra
-; DIS-NEXT: 8c: 00000000 nop
-
-; IASM-LABEL: encSqrtFloat:
-; IASM-NEXT: .LencSqrtFloat$entry:
-; IASM-NEXT: .byte 0x4
-; IASM-NEXT: .byte 0x63
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x46
-; IASM-NEXT: .byte 0x6
-; IASM-NEXT: .byte 0x60
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x46
-; IASM-NEXT: .byte 0x8
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xe0
-; IASM-NEXT: .byte 0x3
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-
-define internal double @encSqrtDouble(double %a) {
-entry:
- %c = call double @llvm.sqrt.f64(double %a)
- ret double %c
-}
-
-; ASM-LABEL: encSqrtDouble
-; ASM-NEXT: .LencSqrtDouble$entry:
-; ASM-NEXT: sqrt.d $f12, $f12
-; ASM-NEXT: mov.d $f0, $f12
-; ASM-NEXT: jr $ra
-
-; DIS-LABEL: 00000090 <encSqrtDouble>:
-; DIS-NEXT: 90: 46206304 sqrt.d $f12,$f12
-; DIS-NEXT: 94: 46206006 mov.d $f0,$f12
-; DIS-NEXT: 98: 03e00008 jr ra
-; DIS-NEXT: 9c: 00000000 nop
-
-; IASM-LABEL: encSqrtDouble:
-; IASM-NEXT: .LencSqrtDouble$entry:
-; IASM-NEXT: .byte 0x4
-; IASM-NEXT: .byte 0x63
-; IASM-NEXT: .byte 0x20
-; IASM-NEXT: .byte 0x46
-; IASM-NEXT: .byte 0x6
-; IASM-NEXT: .byte 0x60
-; IASM-NEXT: .byte 0x20
-; IASM-NEXT: .byte 0x46
-; IASM-NEXT: .byte 0x8
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xe0
-; IASM-NEXT: .byte 0x3
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-
-define internal float @encSubFloat(float %a, float %b) {
-entry:
- %c = fsub float %a, %b
- ret float %c
-}
-
-; ASM-LABEL: encSubFloat
-; ASM-NEXT: .LencSubFloat$entry:
-; ASM-NEXT: sub.s $f12, $f12, $f14
-; ASM-NEXT: mov.s $f0, $f12
-; ASM-NEXT: jr $ra
-
-; DIS-LABEL: 000000a0 <encSubFloat>:
-; DIS-NEXT: a0: 460e6301 sub.s $f12,$f12,$f14
-; DIS-NEXT: a4: 46006006 mov.s $f0,$f12
-; DIS-NEXT: a8: 03e00008 jr ra
-; DIS-NEXT: ac: 00000000 nop
-
-; IASM-LABEL: encSubFloat:
-; IASM-NEXT: .LencSubFloat$entry:
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x63
-; IASM-NEXT: .byte 0xe
-; IASM-NEXT: .byte 0x46
-; IASM-NEXT: .byte 0x6
-; IASM-NEXT: .byte 0x60
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x46
-; IASM-NEXT: .byte 0x8
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xe0
-; IASM-NEXT: .byte 0x3
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-
-define internal double @encSubDouble(double %a, double %b) {
-entry:
- %c = fsub double %a, %b
- ret double %c
-}
-
-; ASM-LABEL: encSubDouble
-; ASM-NEXT: .LencSubDouble$entry:
-; ASM-NEXT: sub.d $f12, $f12, $f14
-; ASM-NEXT: mov.d $f0, $f12
-; ASM-NEXT: jr $ra
-
-; DIS-LABEL: 000000b0 <encSubDouble>:
-; DIS-NEXT: b0: 462e6301 sub.d $f12,$f12,$f14
-; DIS-NEXT: b4: 46206006 mov.d $f0,$f12
-; DIS-NEXT: b8: 03e00008 jr ra
-; DIS-NEXT: bc: 00000000 nop
-
-; IASM-LABEL: encSubDouble:
-; IASM-NEXT: .LencSubDouble$entry:
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x63
-; IASM-NEXT: .byte 0x2e
-; IASM-NEXT: .byte 0x46
-; IASM-NEXT: .byte 0x6
-; IASM-NEXT: .byte 0x60
-; IASM-NEXT: .byte 0x20
-; IASM-NEXT: .byte 0x46
-; IASM-NEXT: .byte 0x8
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xe0
-; IASM-NEXT: .byte 0x3
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-
-define internal i64 @cast_d2ll_const() {
-entry:
- %v0 = bitcast double 0x12345678901234 to i64
- ret i64 %v0
-}
-; ASM-LABEL: cast_d2ll_const
-; ASM-LABEL: .Lcast_d2ll_const$entry:
-; ASM: lui $[[REG:.*]], %hi({{.*}})
-; ASM-NEXT: ldc1 $[[FREG:.*]], %lo({{.*}})($[[REG]])
-
-; DIS-LABEL: <cast_d2ll_const>:
-; DIS: 3c020000 lui v0,0x0
-; DIS-NEXT: d4400000 ldc1 $f0,0(v0)
-
-; IASM-LABEL: cast_d2ll_const:
-; IASM-LABEL: .Lcast_d2ll_const$entry:
-; IASM-NEXT: .byte 0xf0
-; IASM-NEXT: .byte 0xff
-; IASM-NEXT: .byte 0xbd
-; IASM-NEXT: .byte 0x27
-; IASM-NEXT: .word 0x3c020000 # R_MIPS_HI16 [[LAB:.*]]
-; IASM-NEXT: .word 0xd4400000 # R_MIPS_LO16 [[LAB]]
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xa1
-; IASM-NEXT: .byte 0xe7
-; IASM-NEXT: .byte 0x4
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xa0
-; IASM-NEXT: .byte 0xe7
-; IASM-NEXT: .byte 0x4
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xa2
-; IASM-NEXT: .byte 0x8f
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xa3
-; IASM-NEXT: .byte 0x8f
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xbd
-; IASM-NEXT: .byte 0x27
-; IASM-NEXT: .byte 0x8
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xe0
-; IASM-NEXT: .byte 0x3
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x34
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x34
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-
-declare void @bar(i32 %a1, i32 %a2)
-define internal void @Call() {
- call void @bar(i32 1, i32 2)
- ret void
-}
-; ASM-LABEL: Call
-; ASM: jal bar
-
-; DIS-LABEL: 000000f0 <Call>:
-; DIS: 100: 0c000000 jal 0
-
-; IASM-LABEL: Call:
-; IASM: .word 0xc000000 # R_MIPS_26 bar
diff --git a/third_party/subzero/tests_lit/assembler/mips32/encoding_test_branch.ll b/third_party/subzero/tests_lit/assembler/mips32/encoding_test_branch.ll
deleted file mode 100644
index 36c0611..0000000
--- a/third_party/subzero/tests_lit/assembler/mips32/encoding_test_branch.ll
+++ /dev/null
@@ -1,255 +0,0 @@
-; Test encoding of MIPS32 branch instructions
-
-; REQUIRES: allow_dump
-
-; Compile using standalone assembler.
-; RUN: %p2i --filetype=asm -i %s --target=mips32 --args -O2 \
-; RUN: --allow-externally-defined-symbols \
-; RUN: | FileCheck %s --check-prefix=ASM
-
-; Show bytes in assembled standalone code.
-; RUN: %p2i --filetype=asm -i %s --target=mips32 --assemble --disassemble \
-; RUN: --args -O2 --allow-externally-defined-symbols \
-; RUN: | FileCheck %s --check-prefix=DIS
-
-; Compile using integrated assembler.
-; RUN: %p2i --filetype=iasm -i %s --target=mips32 --args -O2 \
-; RUN: --allow-externally-defined-symbols \
-; RUN: | FileCheck %s --check-prefix=IASM
-
-; Show bytes in assembled integrated code.
-; RUN: %p2i --filetype=iasm -i %s --target=mips32 --assemble --disassemble \
-; RUN: --args -O2 --allow-externally-defined-symbols \
-; RUN: | FileCheck %s --check-prefix=DIS
-
-define internal void @test_01(i32 %a) {
- %cmp = icmp eq i32 %a, 1
- br i1 %cmp, label %then, label %else
-then:
- br label %end
-else:
- br label %end
-end:
- ret void
-}
-
-; ASM-LABEL: test_01:
-; ASM-LABEL: .Ltest_01$__0:
-; ASM-NEXT: # $zero = def.pseudo
-; ASM-NEXT: addiu $v0, $zero, 1
-; ASM-NEXT: bne $a0, $v0, .Ltest_01$end
-; ASM-LABEL: .Ltest_01$end:
-; ASM-NEXT: jr $ra
-; ASM-LABEL: .Ltest_01$then:
-; ASM-LABEL: .Ltest_01$else:
-
-; DIS-LABEL:00000000 <test_01>:
-; DIS-NEXT: 0: 24020001 li v0,1
-; DIS-NEXT: 4: 14820001 bne a0,v0,c <.Ltest_01$end>
-; DIS-NEXT: 8: 00000000 nop
-; DIS-LABEL:0000000c <.Ltest_01$end>:
-; DIS-NEXT: c: 03e00008 jr ra
-; DIS-NEXT: 10: 00000000 nop
-
-; IASM-LABEL: test_01:
-; IASM-LABEL: .Ltest_01$__0:
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x2
-; IASM-NEXT: .byte 0x24
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x82
-; IASM-NEXT: .byte 0x14
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-LABEL: .Ltest_01$end:
-; IASM-NEXT: .byte 0x8
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xe0
-; IASM-NEXT: .byte 0x3
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-LABEL: .Ltest_01$then:
-; IASM-LABEL: .Ltest_01$else:
-
-define internal void @test_02(i32 %a) {
- %cmp = icmp ne i32 %a, 2
- br i1 %cmp, label %then, label %else
-then:
- br label %end
-else:
- br label %end
-end:
- ret void
-}
-
-; ASM-LABEL: test_02:
-; ASM-LABEL: .Ltest_02$__0:
-; ASM-NEXT: # $zero = def.pseudo
-; ASM-NEXT: addiu $v0, $zero, 2
-; ASM-NEXT: beq $a0, $v0, .Ltest_02$end
-; ASM-LABEL: .Ltest_02$end:
-; ASM-NEXT: jr $ra
-; ASM-LABEL: .Ltest_02$then:
-; ASM-LABEL: .Ltest_02$else:
-
-; DIS-LABEL:00000020 <test_02>:
-; DIS-NEXT: 20: 24020002 li v0,2
-; DIS-NEXT: 24: 10820001 beq a0,v0,2c <.Ltest_02$end>
-; DIS-NEXT: 28: 00000000 nop
-; DIS-LABEL:0000002c <.Ltest_02$end>:
-; DIS-NEXT: 2c: 03e00008 jr ra
-; DIS-NEXT: 30: 00000000 nop
-
-; IASM-LABEL: test_02:
-; IASM-LABEL: .Ltest_02$__0:
-; IASM-NEXT: .byte 0x2
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x2
-; IASM-NEXT: .byte 0x24
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x82
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-LABEL: .Ltest_02$end:
-; IASM-NEXT: .byte 0x8
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xe0
-; IASM-NEXT: .byte 0x3
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-LABEL: .Ltest_02$then:
-; IASM-LABEL: .Ltest_02$else:
-
-define internal void @test_03(i32 %a) {
- %cmp = icmp ugt i32 %a, 3
- br i1 %cmp, label %then, label %else
-then:
- br label %end
-else:
- br label %end
-end:
- ret void
-}
-
-; ASM-LABEL: test_03:
-; ASM-LABEL: .Ltest_03$__0:
-; ASM-NEXT: # $zero = def.pseudo
-; ASM-NEXT: addiu $v0, $zero, 3
-; ASM-NEXT: sltu $v0, $v0, $a0
-; ASM-NEXT: beqz $v0, .Ltest_03$end
-; ASM-LABEL: .Ltest_03$end:
-; ASM-NEXT: jr $ra
-; ASM-LABEL: .Ltest_03$then:
-; ASM-LABEL: .Ltest_03$else:
-
-; DIS-LABEL:00000040 <test_03>:
-; DIS-NEXT: 40: 24020003 li v0,3
-; DIS-NEXT: 44: 0044102b sltu v0,v0,a0
-; DIS-NEXT: 48: 10400001 beqz v0,50 <.Ltest_03$end>
-; DIS-NEXT: 4c: 00000000 nop
-; DIS-LABEL:00000050 <.Ltest_03$end>:
-; DIS-NEXT: 50: 03e00008 jr ra
-; DIS-NEXT: 54: 00000000 nop
-
-; IASM-LABEL: test_03:
-; IASM-LABEL: .Ltest_03$__0:
-; IASM-NEXT: .byte 0x3
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x2
-; IASM-NEXT: .byte 0x24
-; IASM-NEXT: .byte 0x2b
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0x44
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x40
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-LABEL: .Ltest_03$end:
-; IASM-NEXT: .byte 0x8
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xe0
-; IASM-NEXT: .byte 0x3
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-LABEL: .Ltest_03$then:
-; IASM-LABEL: .Ltest_03$else:
-
-define internal void @test_04(i32 %a) {
- %cmp = icmp uge i32 %a, 4
- br i1 %cmp, label %then, label %else
-then:
- br label %end
-else:
- br label %end
-end:
- ret void
-}
-
-; ASM-LABEL: test_04:
-; ASM-LABEL: .Ltest_04$__0:
-; ASM-NEXT: # $zero = def.pseudo
-; ASM-NEXT: addiu $v0, $zero, 4
-; ASM-NEXT: sltu $a0, $a0, $v0
-; ASM-NEXT: bnez $a0, .Ltest_04$end
-; ASM-LABEL: .Ltest_04$end:
-; ASM-NEXT: jr $ra
-; ASM-LABEL: .Ltest_04$then:
-; ASM-LABEL: .Ltest_04$else:
-
-; DIS-LABEL:00000060 <test_04>:
-; DIS-NEXT: 60: 24020004 li v0,4
-; DIS-NEXT: 64: 0082202b sltu a0,a0,v0
-; DIS-NEXT: 68: 14800001 bnez a0,70 <.Ltest_04$end>
-; DIS-NEXT: 6c: 00000000 nop
-; DIS-LABEL:00000070 <.Ltest_04$end>:
-; DIS-NEXT: 70: 03e00008 jr ra
-; DIS-NEXT: 74: 00000000 nop
-
-; IASM-LABEL: test_04:
-; IASM-LABEL: .Ltest_04$__0:
-; IASM-NEXT: .byte 0x4
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x2
-; IASM-NEXT: .byte 0x24
-; IASM-NEXT: .byte 0x2b
-; IASM-NEXT: .byte 0x20
-; IASM-NEXT: .byte 0x82
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x80
-; IASM-NEXT: .byte 0x14
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-LABEL: .Ltest_04$end:
-; IASM-NEXT: .byte 0x8
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xe0
-; IASM-NEXT: .byte 0x3
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-LABEL: .Ltest_04$then:
-; IASM-LABEL: .Ltest_04$else:
diff --git a/third_party/subzero/tests_lit/assembler/mips32/encoding_test_fcmp.ll b/third_party/subzero/tests_lit/assembler/mips32/encoding_test_fcmp.ll
deleted file mode 100644
index 4a2bc81..0000000
--- a/third_party/subzero/tests_lit/assembler/mips32/encoding_test_fcmp.ll
+++ /dev/null
@@ -1,1415 +0,0 @@
-; Test encoding of MIPS32 floating point comparison
-
-; REQUIRES: allow_dump
-
-; Compile using standalone assembler.
-; RUN: %p2i --filetype=asm -i %s --target=mips32 --args -O2 \
-; RUN: --allow-externally-defined-symbols \
-; RUN: | FileCheck %s --check-prefix=ASM
-
-; Show bytes in assembled standalone code.
-; RUN: %p2i --filetype=asm -i %s --target=mips32 --assemble --disassemble \
-; RUN: --args -O2 --allow-externally-defined-symbols \
-; RUN: | FileCheck %s --check-prefix=DIS
-
-; Compile using integrated assembler.
-; RUN: %p2i --filetype=iasm -i %s --target=mips32 --args -O2 \
-; RUN: --allow-externally-defined-symbols \
-; RUN: | FileCheck %s --check-prefix=IASM
-
-; Show bytes in assembled integrated code.
-; RUN: %p2i --filetype=iasm -i %s --target=mips32 --assemble --disassemble \
-; RUN: --args -O2 --allow-externally-defined-symbols \
-; RUN: | FileCheck %s --check-prefix=DIS
-
-define internal i32 @fcmpFalseFloat(float %a, float %b) {
-entry:
- %cmp = fcmp false float %a, %b
- %cmp.ret_ext = zext i1 %cmp to i32
- ret i32 %cmp.ret_ext
-}
-
-; ASM-LABEL: fcmpFalseFloat:
-; ASM-NEXT: .LfcmpFalseFloat$entry:
-; ASM: addiu $v0, $zero, 0
-; ASM-NEXT: andi $v0, $v0, 1
-; ASM-NEXT: jr $ra
-
-; DIS-LABEL: 00000000 <fcmpFalseFloat>:
-; DIS-NEXT: 0: 24020000 li v0,0
-; DIS-NEXT: 4: 30420001 andi v0,v0,0x1
-; DIS-NEXT: 8: 03e00008 jr ra
-
-; IASM-LABEL: fcmpFalseFloat:
-; IASM-NEXT: .LfcmpFalseFloat$entry:
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x2
-; IASM-NEXT: .byte 0x24
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x42
-; IASM-NEXT: .byte 0x30
-; IASM-NEXT: .byte 0x8
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xe0
-; IASM-NEXT: .byte 0x3
-
-define internal i32 @fcmpFalseDouble(double %a, double %b) {
-entry:
- %cmp = fcmp false double %a, %b
- %cmp.ret_ext = zext i1 %cmp to i32
- ret i32 %cmp.ret_ext
-}
-
-; ASM-LABEL: fcmpFalseDouble:
-; ASM-NEXT: .LfcmpFalseDouble$entry:
-; ASM: addiu $v0, $zero, 0
-; ASM-NEXT: andi $v0, $v0, 1
-; ASM-NEXT: jr $ra
-
-; DIS-LABEL: 00000010 <fcmpFalseDouble>:
-; DIS-NEXT: 10: 24020000 li v0,0
-; DIS-NEXT: 14: 30420001 andi v0,v0,0x1
-; DIS-NEXT: 18: 03e00008 jr ra
-
-; IASM-LABEL: fcmpFalseDouble:
-; IASM-NEXT: .LfcmpFalseDouble$entry:
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x2
-; IASM-NEXT: .byte 0x24
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x42
-; IASM-NEXT: .byte 0x30
-; IASM-NEXT: .byte 0x8
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xe0
-; IASM-NEXT: .byte 0x3
-
-define internal i32 @fcmpOeqFloat(float %a, float %b) {
-entry:
- %cmp = fcmp oeq float %a, %b
- %cmp.ret_ext = zext i1 %cmp to i32
- ret i32 %cmp.ret_ext
-}
-
-; ASM-LABEL: fcmpOeqFloat
-; ASM-NEXT: .LfcmpOeqFloat$entry:
-; ASM: c.eq.s $f12, $f14
-; ASM: addiu $v0, $zero, 1
-; ASM: movf $v0, $zero, $fcc0
-; ASM-NEXT: andi $v0, $v0, 1
-; ASM-NEXT: jr $ra
-
-; DIS-LABEL: 00000020 <fcmpOeqFloat>:
-; DIS-NEXT: 20: 460e6032 c.eq.s $f12,$f14
-; DIS-NEXT: 24: 24020001 li v0,1
-; DIS-NEXT: 28: 00001001 movf v0,zero,$fcc0
-; DIS-NEXT: 2c: 30420001 andi v0,v0,0x1
-; DIS-NEXT: 30: 03e00008 jr ra
-
-; IASM-LABEL: fcmpOeqFloat:
-; IASM-NEXT: .LfcmpOeqFloat$entry:
-; IASM-NEXT: .byte 0x32
-; IASM-NEXT: .byte 0x60
-; IASM-NEXT: .byte 0xe
-; IASM-NEXT: .byte 0x46
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x2
-; IASM-NEXT: .byte 0x24
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x42
-; IASM-NEXT: .byte 0x30
-; IASM-NEXT: .byte 0x8
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xe0
-; IASM-NEXT: .byte 0x3
-
-define internal i32 @fcmpOeqDouble(double %a, double %b) {
-entry:
- %cmp = fcmp oeq double %a, %b
- %cmp.ret_ext = zext i1 %cmp to i32
- ret i32 %cmp.ret_ext
-}
-
-; ASM-LABEL: fcmpOeqDouble
-; ASM-NEXT: .LfcmpOeqDouble$entry:
-; ASM: c.eq.d $f12, $f14
-; ASM: addiu $v0, $zero, 1
-; ASM: movf $v0, $zero, $fcc0
-; ASM-NEXT: andi $v0, $v0, 1
-; ASM-NEXT: jr $ra
-
-; DIS-LABEL: 00000040 <fcmpOeqDouble>:
-; DIS-NEXT: 40: 462e6032 c.eq.d $f12,$f14
-; DIS-NEXT: 44: 24020001 li v0,1
-; DIS-NEXT: 48: 00001001 movf v0,zero,$fcc0
-; DIS-NEXT: 4c: 30420001 andi v0,v0,0x1
-; DIS-NEXT: 50: 03e00008 jr ra
-
-; IASM-LABEL: fcmpOeqDouble:
-; IASM-NEXT: .LfcmpOeqDouble$entry:
-; IASM-NEXT: .byte 0x32
-; IASM-NEXT: .byte 0x60
-; IASM-NEXT: .byte 0x2e
-; IASM-NEXT: .byte 0x46
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x2
-; IASM-NEXT: .byte 0x24
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x42
-; IASM-NEXT: .byte 0x30
-; IASM-NEXT: .byte 0x8
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xe0
-; IASM-NEXT: .byte 0x3
-
-define internal i32 @fcmpOgtFloat(float %a, float %b) {
-entry:
- %cmp = fcmp ogt float %a, %b
- %cmp.ret_ext = zext i1 %cmp to i32
- ret i32 %cmp.ret_ext
-}
-
-; ASM-LABEL: fcmpOgtFloat
-; ASM-NEXT: .LfcmpOgtFloat$entry:
-; ASM: c.ule.s $f12, $f14
-; ASM: addiu $v0, $zero, 1
-; ASM: movt $v0, $zero, $fcc0
-; ASM-NEXT: andi $v0, $v0, 1
-; ASM-NEXT: jr $ra
-
-; DIS-LABEL: 00000060 <fcmpOgtFloat>:
-; DIS-NEXT: 60: 460e6037 c.ule.s $f12,$f14
-; DIS-NEXT: 64: 24020001 li v0,1
-; DIS-NEXT: 68: 00011001 movt v0,zero,$fcc0
-; DIS-NEXT: 6c: 30420001 andi v0,v0,0x1
-; DIS-NEXT: 70: 03e00008 jr ra
-
-; IASM-LABEL: fcmpOgtFloat:
-; IASM-NEXT: .LfcmpOgtFloat$entry:
-; IASM-NEXT: .byte 0x37
-; IASM-NEXT: .byte 0x60
-; IASM-NEXT: .byte 0xe
-; IASM-NEXT: .byte 0x46
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x2
-; IASM-NEXT: .byte 0x24
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x42
-; IASM-NEXT: .byte 0x30
-; IASM-NEXT: .byte 0x8
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xe0
-; IASM-NEXT: .byte 0x3
-
-define internal i32 @fcmpOgtDouble(double %a, double %b) {
-entry:
- %cmp = fcmp ogt double %a, %b
- %cmp.ret_ext = zext i1 %cmp to i32
- ret i32 %cmp.ret_ext
-}
-
-; ASM-LABEL: fcmpOgtDouble
-; ASM-NEXT: .LfcmpOgtDouble$entry:
-; ASM: c.ule.d $f12, $f14
-; ASM: addiu $v0, $zero, 1
-; ASM: movt $v0, $zero, $fcc0
-; ASM-NEXT: andi $v0, $v0, 1
-; ASM-NEXT: jr $ra
-
-; DIS-LABEL: 00000080 <fcmpOgtDouble>:
-; DIS-NEXT: 80: 462e6037 c.ule.d $f12,$f14
-; DIS-NEXT: 84: 24020001 li v0,1
-; DIS-NEXT: 88: 00011001 movt v0,zero,$fcc0
-; DIS-NEXT: 8c: 30420001 andi v0,v0,0x1
-; DIS-NEXT: 90: 03e00008 jr ra
-
-; IASM-LABEL: fcmpOgtDouble:
-; IASM-NEXT: .LfcmpOgtDouble$entry:
-; IASM-NEXT: .byte 0x37
-; IASM-NEXT: .byte 0x60
-; IASM-NEXT: .byte 0x2e
-; IASM-NEXT: .byte 0x46
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x2
-; IASM-NEXT: .byte 0x24
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x42
-; IASM-NEXT: .byte 0x30
-; IASM-NEXT: .byte 0x8
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xe0
-; IASM-NEXT: .byte 0x3
-
-define internal i32 @fcmpOgeFloat(float %a, float %b) {
-entry:
- %cmp = fcmp oge float %a, %b
- %cmp.ret_ext = zext i1 %cmp to i32
- ret i32 %cmp.ret_ext
-}
-
-; ASM-LABEL: fcmpOgeFloat
-; ASM-NEXT: .LfcmpOgeFloat$entry:
-; ASM: c.ult.s $f12, $f14
-; ASM: addiu $v0, $zero, 1
-; ASM: movt $v0, $zero, $fcc0
-; ASM-NEXT: andi $v0, $v0, 1
-; ASM-NEXT: jr $ra
-
-; DIS-LABEL: 000000a0 <fcmpOgeFloat>:
-; DIS-NEXT: a0: 460e6035 c.ult.s $f12,$f14
-; DIS-NEXT: a4: 24020001 li v0,1
-; DIS-NEXT: a8: 00011001 movt v0,zero,$fcc0
-; DIS-NEXT: ac: 30420001 andi v0,v0,0x1
-; DIS-NEXT: b0: 03e00008 jr ra
-
-; IASM-LABEL: fcmpOgeFloat:
-; IASM-NEXT: .LfcmpOgeFloat$entry:
-; IASM-NEXT: .byte 0x35
-; IASM-NEXT: .byte 0x60
-; IASM-NEXT: .byte 0xe
-; IASM-NEXT: .byte 0x46
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x2
-; IASM-NEXT: .byte 0x24
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x42
-; IASM-NEXT: .byte 0x30
-; IASM-NEXT: .byte 0x8
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xe0
-; IASM-NEXT: .byte 0x3
-
-define internal i32 @fcmpOgeDouble(double %a, double %b) {
-entry:
- %cmp = fcmp oge double %a, %b
- %cmp.ret_ext = zext i1 %cmp to i32
- ret i32 %cmp.ret_ext
-}
-
-; ASM-LABEL: fcmpOgeDouble
-; ASM-NEXT: .LfcmpOgeDouble$entry:
-; ASM: c.ult.d $f12, $f14
-; ASM: addiu $v0, $zero, 1
-; ASM: movt $v0, $zero, $fcc0
-; ASM-NEXT: andi $v0, $v0, 1
-; ASM-NEXT: jr $ra
-
-; DIS-LABEL: 000000c0 <fcmpOgeDouble>:
-; DIS-NEXT: c0: 462e6035 c.ult.d $f12,$f14
-; DIS-NEXT: c4: 24020001 li v0,1
-; DIS-NEXT: c8: 00011001 movt v0,zero,$fcc0
-; DIS-NEXT: cc: 30420001 andi v0,v0,0x1
-; DIS-NEXT: d0: 03e00008 jr ra
-
-; IASM-LABEL: fcmpOgeDouble:
-; IASM-NEXT: .LfcmpOgeDouble$entry:
-; IASM-NEXT: .byte 0x35
-; IASM-NEXT: .byte 0x60
-; IASM-NEXT: .byte 0x2e
-; IASM-NEXT: .byte 0x46
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x2
-; IASM-NEXT: .byte 0x24
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x42
-; IASM-NEXT: .byte 0x30
-; IASM-NEXT: .byte 0x8
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xe0
-; IASM-NEXT: .byte 0x3
-
-define internal i32 @fcmpOltFloat(float %a, float %b) {
-entry:
- %cmp = fcmp olt float %a, %b
- %cmp.ret_ext = zext i1 %cmp to i32
- ret i32 %cmp.ret_ext
-}
-
-; ASM-LABEL: fcmpOltFloat
-; ASM-NEXT: .LfcmpOltFloat$entry:
-; ASM: c.olt.s $f12, $f14
-; ASM: addiu $v0, $zero, 1
-; ASM: movf $v0, $zero, $fcc0
-; ASM-NEXT: andi $v0, $v0, 1
-; ASM-NEXT: jr $ra
-
-; DIS-LABEL: 000000e0 <fcmpOltFloat>:
-; DIS-NEXT: e0: 460e6034 c.olt.s $f12,$f14
-; DIS-NEXT: e4: 24020001 li v0,1
-; DIS-NEXT: e8: 00001001 movf v0,zero,$fcc0
-; DIS-NEXT: ec: 30420001 andi v0,v0,0x1
-; DIS-NEXT: f0: 03e00008 jr ra
-
-; IASM-LABEL: fcmpOltFloat:
-; IASM-NEXT: .LfcmpOltFloat$entry:
-; IASM-NEXT: .byte 0x34
-; IASM-NEXT: .byte 0x60
-; IASM-NEXT: .byte 0xe
-; IASM-NEXT: .byte 0x46
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x2
-; IASM-NEXT: .byte 0x24
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x42
-; IASM-NEXT: .byte 0x30
-; IASM-NEXT: .byte 0x8
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xe0
-; IASM-NEXT: .byte 0x3
-
-define internal i32 @fcmpOltDouble(double %a, double %b) {
-entry:
- %cmp = fcmp olt double %a, %b
- %cmp.ret_ext = zext i1 %cmp to i32
- ret i32 %cmp.ret_ext
-}
-
-; ASM-LABEL: fcmpOltDouble
-; ASM-NEXT: .LfcmpOltDouble$entry:
-; ASM: c.olt.d $f12, $f14
-; ASM: addiu $v0, $zero, 1
-; ASM: movf $v0, $zero, $fcc0
-; ASM-NEXT: andi $v0, $v0, 1
-; ASM-NEXT: jr $ra
-
-; DIS-LABEL: 00000100 <fcmpOltDouble>:
-; DIS-NEXT: 100: 462e6034 c.olt.d $f12,$f14
-; DIS-NEXT: 104: 24020001 li v0,1
-; DIS-NEXT: 108: 00001001 movf v0,zero,$fcc0
-; DIS-NEXT: 10c: 30420001 andi v0,v0,0x1
-; DIS-NEXT: 110: 03e00008 jr ra
-
-; IASM-LABEL: fcmpOltDouble:
-; IASM-NEXT: .LfcmpOltDouble$entry:
-; IASM-NEXT: .byte 0x34
-; IASM-NEXT: .byte 0x60
-; IASM-NEXT: .byte 0x2e
-; IASM-NEXT: .byte 0x46
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x2
-; IASM-NEXT: .byte 0x24
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x42
-; IASM-NEXT: .byte 0x30
-; IASM-NEXT: .byte 0x8
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xe0
-; IASM-NEXT: .byte 0x3
-
-define internal i32 @fcmpOleFloat(float %a, float %b) {
-entry:
- %cmp = fcmp ole float %a, %b
- %cmp.ret_ext = zext i1 %cmp to i32
- ret i32 %cmp.ret_ext
-}
-
-; ASM-LABEL: fcmpOleFloat
-; ASM-NEXT: .LfcmpOleFloat$entry:
-; ASM: c.ole.s $f12, $f14
-; ASM: addiu $v0, $zero, 1
-; ASM: movf $v0, $zero, $fcc0
-; ASM-NEXT: andi $v0, $v0, 1
-; ASM-NEXT: jr $ra
-
-; DIS-LABEL: 00000120 <fcmpOleFloat>:
-; DIS-NEXT: 120: 460e6036 c.ole.s $f12,$f14
-; DIS-NEXT: 124: 24020001 li v0,1
-; DIS-NEXT: 128: 00001001 movf v0,zero,$fcc0
-; DIS-NEXT: 12c: 30420001 andi v0,v0,0x1
-; DIS-NEXT: 130: 03e00008 jr ra
-
-; IASM-LABEL: fcmpOleFloat:
-; IASM-NEXT: .LfcmpOleFloat$entry:
-; IASM-NEXT: .byte 0x36
-; IASM-NEXT: .byte 0x60
-; IASM-NEXT: .byte 0xe
-; IASM-NEXT: .byte 0x46
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x2
-; IASM-NEXT: .byte 0x24
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x42
-; IASM-NEXT: .byte 0x30
-; IASM-NEXT: .byte 0x8
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xe0
-; IASM-NEXT: .byte 0x3
-
-define internal i32 @fcmpOleDouble(double %a, double %b) {
-entry:
- %cmp = fcmp ole double %a, %b
- %cmp.ret_ext = zext i1 %cmp to i32
- ret i32 %cmp.ret_ext
-}
-
-; ASM-LABEL: fcmpOleDouble
-; ASM-NEXT: .LfcmpOleDouble$entry:
-; ASM: c.ole.d $f12, $f14
-; ASM: addiu $v0, $zero, 1
-; ASM: movf $v0, $zero, $fcc0
-; ASM-NEXT: andi $v0, $v0, 1
-; ASM-NEXT: jr $ra
-
-; DIS-LABEL: 00000140 <fcmpOleDouble>:
-; DIS-NEXT: 140: 462e6036 c.ole.d $f12,$f14
-; DIS-NEXT: 144: 24020001 li v0,1
-; DIS-NEXT: 148: 00001001 movf v0,zero,$fcc0
-; DIS-NEXT: 14c: 30420001 andi v0,v0,0x1
-; DIS-NEXT: 150: 03e00008 jr ra
-
-; IASM-LABEL: fcmpOleDouble:
-; IASM-NEXT: .LfcmpOleDouble$entry:
-; IASM-NEXT: .byte 0x36
-; IASM-NEXT: .byte 0x60
-; IASM-NEXT: .byte 0x2e
-; IASM-NEXT: .byte 0x46
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x2
-; IASM-NEXT: .byte 0x24
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x42
-; IASM-NEXT: .byte 0x30
-; IASM-NEXT: .byte 0x8
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xe0
-; IASM-NEXT: .byte 0x3
-
-define internal i32 @fcmpOneFloat(float %a, float %b) {
-entry:
- %cmp = fcmp one float %a, %b
- %cmp.ret_ext = zext i1 %cmp to i32
- ret i32 %cmp.ret_ext
-}
-
-; ASM-LABEL: fcmpOneFloat
-; ASM-NEXT: .LfcmpOneFloat$entry:
-; ASM: c.ueq.s $f12, $f14
-; ASM: addiu $v0, $zero, 1
-; ASM: movt $v0, $zero, $fcc0
-; ASM-NEXT: andi $v0, $v0, 1
-; ASM-NEXT: jr $ra
-
-; DIS-LABEL: 00000160 <fcmpOneFloat>:
-; DIS-NEXT: 160: 460e6033 c.ueq.s $f12,$f14
-; DIS-NEXT: 164: 24020001 li v0,1
-; DIS-NEXT: 168: 00011001 movt v0,zero,$fcc0
-; DIS-NEXT: 16c: 30420001 andi v0,v0,0x1
-; DIS-NEXT: 170: 03e00008 jr ra
-
-; IASM-LABEL: fcmpOneFloat:
-; IASM-NEXT: .LfcmpOneFloat$entry:
-; IASM-NEXT: .byte 0x33
-; IASM-NEXT: .byte 0x60
-; IASM-NEXT: .byte 0xe
-; IASM-NEXT: .byte 0x46
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x2
-; IASM-NEXT: .byte 0x24
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x42
-; IASM-NEXT: .byte 0x30
-; IASM-NEXT: .byte 0x8
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xe0
-; IASM-NEXT: .byte 0x3
-
-define internal i32 @fcmpOneDouble(double %a, double %b) {
-entry:
- %cmp = fcmp one double %a, %b
- %cmp.ret_ext = zext i1 %cmp to i32
- ret i32 %cmp.ret_ext
-}
-
-; ASM-LABEL: fcmpOneDouble
-; ASM-NEXT: .LfcmpOneDouble$entry:
-; ASM: c.ueq.d $f12, $f14
-; ASM: addiu $v0, $zero, 1
-; ASM: movt $v0, $zero, $fcc0
-; ASM-NEXT: andi $v0, $v0, 1
-; ASM-NEXT: jr $ra
-
-; DIS-LABEL: 00000180 <fcmpOneDouble>:
-; DIS-NEXT: 180: 462e6033 c.ueq.d $f12,$f14
-; DIS-NEXT: 184: 24020001 li v0,1
-; DIS-NEXT: 188: 00011001 movt v0,zero,$fcc0
-; DIS-NEXT: 18c: 30420001 andi v0,v0,0x1
-; DIS-NEXT: 190: 03e00008 jr ra
-
-; IASM-LABEL: fcmpOneDouble:
-; IASM-NEXT: .LfcmpOneDouble$entry:
-; IASM-NEXT: .byte 0x33
-; IASM-NEXT: .byte 0x60
-; IASM-NEXT: .byte 0x2e
-; IASM-NEXT: .byte 0x46
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x2
-; IASM-NEXT: .byte 0x24
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x42
-; IASM-NEXT: .byte 0x30
-; IASM-NEXT: .byte 0x8
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xe0
-; IASM-NEXT: .byte 0x3
-
-define internal i32 @fcmpOrdFloat(float %a, float %b) {
-entry:
- %cmp = fcmp ord float %a, %b
- %cmp.ret_ext = zext i1 %cmp to i32
- ret i32 %cmp.ret_ext
-}
-
-; ASM-LABEL: fcmpOrdFloat:
-; ASM-NEXT: .LfcmpOrdFloat$entry:
-; ASM: c.un.s $f12, $f14
-; ASM: addiu $v0, $zero, 1
-; ASM: movt $v0, $zero, $fcc0
-; ASM-NEXT: andi $v0, $v0, 1
-; ASM-NEXT: jr $ra
-
-; DIS-LABEL: 000001a0 <fcmpOrdFloat>:
-; DIS-NEXT: 1a0: 460e6031 c.un.s $f12,$f14
-; DIS-NEXT: 1a4: 24020001 li v0,1
-; DIS-NEXT: 1a8: 00011001 movt v0,zero,$fcc0
-; DIS-NEXT: 1ac: 30420001 andi v0,v0,0x1
-; DIS-NEXT: 1b0: 03e00008 jr ra
-
-; IASM-LABEL: fcmpOrdFloat:
-; IASM-NEXT: .LfcmpOrdFloat$entry:
-; IASM-NEXT: .byte 0x31
-; IASM-NEXT: .byte 0x60
-; IASM-NEXT: .byte 0xe
-; IASM-NEXT: .byte 0x46
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x2
-; IASM-NEXT: .byte 0x24
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x42
-; IASM-NEXT: .byte 0x30
-; IASM-NEXT: .byte 0x8
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xe0
-; IASM-NEXT: .byte 0x3
-
-define internal i32 @fcmpOrdDouble(double %a, double %b) {
-entry:
- %cmp = fcmp ord double %a, %b
- %cmp.ret_ext = zext i1 %cmp to i32
- ret i32 %cmp.ret_ext
-}
-
-; ASM-LABEL: fcmpOrdDouble:
-; ASM-NEXT: .LfcmpOrdDouble$entry:
-; ASM: c.un.d $f12, $f14
-; ASM: addiu $v0, $zero, 1
-; ASM: movt $v0, $zero, $fcc0
-; ASM-NEXT: andi $v0, $v0, 1
-; ASM-NEXT: jr $ra
-
-; DIS-LABEL: 000001c0 <fcmpOrdDouble>:
-; DIS-NEXT: 1c0: 462e6031 c.un.d $f12,$f14
-; DIS-NEXT: 1c4: 24020001 li v0,1
-; DIS-NEXT: 1c8: 00011001 movt v0,zero,$fcc0
-; DIS-NEXT: 1cc: 30420001 andi v0,v0,0x1
-; DIS-NEXT: 1d0: 03e00008 jr ra
-
-; IASM-LABEL: fcmpOrdDouble:
-; IASM-NEXT: .LfcmpOrdDouble$entry:
-; IASM-NEXT: .byte 0x31
-; IASM-NEXT: .byte 0x60
-; IASM-NEXT: .byte 0x2e
-; IASM-NEXT: .byte 0x46
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x2
-; IASM-NEXT: .byte 0x24
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x42
-; IASM-NEXT: .byte 0x30
-; IASM-NEXT: .byte 0x8
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xe0
-; IASM-NEXT: .byte 0x3
-
-define internal i32 @fcmpUeqFloat(float %a, float %b) {
-entry:
- %cmp = fcmp ueq float %a, %b
- %cmp.ret_ext = zext i1 %cmp to i32
- ret i32 %cmp.ret_ext
-}
-
-; ASM-LABEL: fcmpUeqFloat
-; ASM-NEXT: .LfcmpUeqFloat$entry:
-; ASM: c.ueq.s $f12, $f14
-; ASM: addiu $v0, $zero, 1
-; ASM: movf $v0, $zero, $fcc0
-; ASM-NEXT: andi $v0, $v0, 1
-; ASM-NEXT: jr $ra
-
-; DIS-LABEL: 000001e0 <fcmpUeqFloat>:
-; DIS-NEXT: 1e0: 460e6033 c.ueq.s $f12,$f14
-; DIS-NEXT: 1e4: 24020001 li v0,1
-; DIS-NEXT: 1e8: 00001001 movf v0,zero,$fcc0
-; DIS-NEXT: 1ec: 30420001 andi v0,v0,0x1
-; DIS-NEXT: 1f0: 03e00008 jr ra
-
-; IASM-LABEL: fcmpUeqFloat:
-; IASM-NEXT: .LfcmpUeqFloat$entry:
-; IASM-NEXT: .byte 0x33
-; IASM-NEXT: .byte 0x60
-; IASM-NEXT: .byte 0xe
-; IASM-NEXT: .byte 0x46
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x2
-; IASM-NEXT: .byte 0x24
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x42
-; IASM-NEXT: .byte 0x30
-; IASM-NEXT: .byte 0x8
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xe0
-; IASM-NEXT: .byte 0x3
-
-define internal i32 @fcmpUeqDouble(double %a, double %b) {
-entry:
- %cmp = fcmp ueq double %a, %b
- %cmp.ret_ext = zext i1 %cmp to i32
- ret i32 %cmp.ret_ext
-}
-
-; ASM-LABEL: fcmpUeqDouble
-; ASM-NEXT: .LfcmpUeqDouble$entry:
-; ASM: c.ueq.d $f12, $f14
-; ASM: addiu $v0, $zero, 1
-; ASM: movf $v0, $zero, $fcc0
-; ASM-NEXT: andi $v0, $v0, 1
-; ASM-NEXT: jr $ra
-
-; DIS-LABEL: 00000200 <fcmpUeqDouble>:
-; DIS-NEXT: 200: 462e6033 c.ueq.d $f12,$f14
-; DIS-NEXT: 204: 24020001 li v0,1
-; DIS-NEXT: 208: 00001001 movf v0,zero,$fcc0
-; DIS-NEXT: 20c: 30420001 andi v0,v0,0x1
-; DIS-NEXT: 210: 03e00008 jr ra
-
-; IASM-LABEL: fcmpUeqDouble:
-; IASM-NEXT: .LfcmpUeqDouble$entry:
-; IASM-NEXT: .byte 0x33
-; IASM-NEXT: .byte 0x60
-; IASM-NEXT: .byte 0x2e
-; IASM-NEXT: .byte 0x46
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x2
-; IASM-NEXT: .byte 0x24
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x42
-; IASM-NEXT: .byte 0x30
-; IASM-NEXT: .byte 0x8
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xe0
-; IASM-NEXT: .byte 0x3
-
-define internal i32 @fcmpUgtFloat(float %a, float %b) {
-entry:
- %cmp = fcmp ugt float %a, %b
- %cmp.ret_ext = zext i1 %cmp to i32
- ret i32 %cmp.ret_ext
-}
-
-; ASM-LABEL: fcmpUgtFloat
-; ASM-NEXT: .LfcmpUgtFloat$entry:
-; ASM: c.ole.s $f12, $f14
-; ASM: addiu $v0, $zero, 1
-; ASM: movt $v0, $zero, $fcc0
-; ASM-NEXT: andi $v0, $v0, 1
-; ASM-NEXT: jr $ra
-
-; DIS-LABEL: 00000220 <fcmpUgtFloat>:
-; DIS-NEXT: 220: 460e6036 c.ole.s $f12,$f14
-; DIS-NEXT: 224: 24020001 li v0,1
-; DIS-NEXT: 228: 00011001 movt v0,zero,$fcc0
-; DIS-NEXT: 22c: 30420001 andi v0,v0,0x1
-; DIS-NEXT: 230: 03e00008 jr ra
-
-; IASM-LABEL: fcmpUgtFloat:
-; IASM-NEXT: .LfcmpUgtFloat$entry:
-; IASM-NEXT: .byte 0x36
-; IASM-NEXT: .byte 0x60
-; IASM-NEXT: .byte 0xe
-; IASM-NEXT: .byte 0x46
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x2
-; IASM-NEXT: .byte 0x24
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x42
-; IASM-NEXT: .byte 0x30
-; IASM-NEXT: .byte 0x8
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xe0
-; IASM-NEXT: .byte 0x3
-
-define internal i32 @fcmpUgtDouble(double %a, double %b) {
-entry:
- %cmp = fcmp ugt double %a, %b
- %cmp.ret_ext = zext i1 %cmp to i32
- ret i32 %cmp.ret_ext
-}
-
-; ASM-LABEL: fcmpUgtDouble
-; ASM-NEXT: .LfcmpUgtDouble$entry:
-; ASM: c.ole.d $f12, $f14
-; ASM: addiu $v0, $zero, 1
-; ASM: movt $v0, $zero, $fcc0
-; ASM-NEXT: andi $v0, $v0, 1
-; ASM-NEXT: jr $ra
-
-; DIS-LABEL: 00000240 <fcmpUgtDouble>:
-; DIS-NEXT: 240: 462e6036 c.ole.d $f12,$f14
-; DIS-NEXT: 244: 24020001 li v0,1
-; DIS-NEXT: 248: 00011001 movt v0,zero,$fcc0
-; DIS-NEXT: 24c: 30420001 andi v0,v0,0x1
-; DIS-NEXT: 250: 03e00008 jr ra
-
-; IASM-LABEL: fcmpUgtDouble:
-; IASM-NEXT: .LfcmpUgtDouble$entry:
-; IASM-NEXT: .byte 0x36
-; IASM-NEXT: .byte 0x60
-; IASM-NEXT: .byte 0x2e
-; IASM-NEXT: .byte 0x46
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x2
-; IASM-NEXT: .byte 0x24
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x42
-; IASM-NEXT: .byte 0x30
-; IASM-NEXT: .byte 0x8
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xe0
-; IASM-NEXT: .byte 0x3
-
-define internal i32 @fcmpUgeFloat(float %a, float %b) {
-entry:
- %cmp = fcmp uge float %a, %b
- %cmp.ret_ext = zext i1 %cmp to i32
- ret i32 %cmp.ret_ext
-}
-
-; ASM-LABEL: fcmpUgeFloat
-; ASM-NEXT: .LfcmpUgeFloat$entry:
-; ASM: c.olt.s $f12, $f14
-; ASM: addiu $v0, $zero, 1
-; ASM: movt $v0, $zero, $fcc0
-; ASM-NEXT: andi $v0, $v0, 1
-; ASM-NEXT: jr $ra
-
-; DIS-LABEL: 00000260 <fcmpUgeFloat>:
-; DIS-NEXT: 260: 460e6034 c.olt.s $f12,$f14
-; DIS-NEXT: 264: 24020001 li v0,1
-; DIS-NEXT: 268: 00011001 movt v0,zero,$fcc0
-; DIS-NEXT: 26c: 30420001 andi v0,v0,0x1
-; DIS-NEXT: 270: 03e00008 jr ra
-
-; IASM-LABEL: fcmpUgeFloat:
-; IASM-NEXT: .LfcmpUgeFloat$entry:
-; IASM-NEXT: .byte 0x34
-; IASM-NEXT: .byte 0x60
-; IASM-NEXT: .byte 0xe
-; IASM-NEXT: .byte 0x46
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x2
-; IASM-NEXT: .byte 0x24
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x42
-; IASM-NEXT: .byte 0x30
-; IASM-NEXT: .byte 0x8
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xe0
-; IASM-NEXT: .byte 0x3
-
-define internal i32 @fcmpUgeDouble(double %a, double %b) {
-entry:
- %cmp = fcmp uge double %a, %b
- %cmp.ret_ext = zext i1 %cmp to i32
- ret i32 %cmp.ret_ext
-}
-
-; ASM-LABEL: fcmpUgeDouble
-; ASM-NEXT: .LfcmpUgeDouble$entry:
-; ASM: c.olt.d $f12, $f14
-; ASM: addiu $v0, $zero, 1
-; ASM: movt $v0, $zero, $fcc0
-; ASM-NEXT: andi $v0, $v0, 1
-; ASM-NEXT: jr $ra
-
-; DIS-LABEL: 00000280 <fcmpUgeDouble>:
-; DIS-NEXT: 280: 462e6034 c.olt.d $f12,$f14
-; DIS-NEXT: 284: 24020001 li v0,1
-; DIS-NEXT: 288: 00011001 movt v0,zero,$fcc0
-; DIS-NEXT: 28c: 30420001 andi v0,v0,0x1
-; DIS-NEXT: 290: 03e00008 jr ra
-
-; IASM-LABEL: fcmpUgeDouble:
-; IASM-NEXT: .LfcmpUgeDouble$entry:
-; IASM-NEXT: .byte 0x34
-; IASM-NEXT: .byte 0x60
-; IASM-NEXT: .byte 0x2e
-; IASM-NEXT: .byte 0x46
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x2
-; IASM-NEXT: .byte 0x24
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x42
-; IASM-NEXT: .byte 0x30
-; IASM-NEXT: .byte 0x8
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xe0
-; IASM-NEXT: .byte 0x3
-
-define internal i32 @fcmpUltFloat(float %a, float %b) {
-entry:
- %cmp = fcmp ult float %a, %b
- %cmp.ret_ext = zext i1 %cmp to i32
- ret i32 %cmp.ret_ext
-}
-
-; ASM-LABEL: fcmpUltFloat
-; ASM-NEXT: .LfcmpUltFloat$entry:
-; ASM: c.ult.s $f12, $f14
-; ASM: addiu $v0, $zero, 1
-; ASM: movf $v0, $zero, $fcc0
-; ASM-NEXT: andi $v0, $v0, 1
-; ASM-NEXT: jr $ra
-
-; DIS-LABEL: 000002a0 <fcmpUltFloat>:
-; DIS-NEXT: 2a0: 460e6035 c.ult.s $f12,$f14
-; DIS-NEXT: 2a4: 24020001 li v0,1
-; DIS-NEXT: 2a8: 00001001 movf v0,zero,$fcc0
-; DIS-NEXT: 2ac: 30420001 andi v0,v0,0x1
-; DIS-NEXT: 2b0: 03e00008 jr ra
-
-; IASM-LABEL: fcmpUltFloat:
-; IASM-NEXT: .LfcmpUltFloat$entry:
-; IASM-NEXT: .byte 0x35
-; IASM-NEXT: .byte 0x60
-; IASM-NEXT: .byte 0xe
-; IASM-NEXT: .byte 0x46
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x2
-; IASM-NEXT: .byte 0x24
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x42
-; IASM-NEXT: .byte 0x30
-; IASM-NEXT: .byte 0x8
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xe0
-; IASM-NEXT: .byte 0x3
-
-define internal i32 @fcmpUltDouble(double %a, double %b) {
-entry:
- %cmp = fcmp ult double %a, %b
- %cmp.ret_ext = zext i1 %cmp to i32
- ret i32 %cmp.ret_ext
-}
-
-; ASM-LABEL: fcmpUltDouble
-; ASM-NEXT: .LfcmpUltDouble$entry:
-; ASM: c.ult.d $f12, $f14
-; ASM: addiu $v0, $zero, 1
-; ASM: movf $v0, $zero, $fcc0
-; ASM-NEXT: andi $v0, $v0, 1
-; ASM-NEXT: jr $ra
-
-; DIS-LABEL: 000002c0 <fcmpUltDouble>:
-; DIS-NEXT: 2c0: 462e6035 c.ult.d $f12,$f14
-; DIS-NEXT: 2c4: 24020001 li v0,1
-; DIS-NEXT: 2c8: 00001001 movf v0,zero,$fcc0
-; DIS-NEXT: 2cc: 30420001 andi v0,v0,0x1
-; DIS-NEXT: 2d0: 03e00008 jr ra
-
-; IASM-LABEL: fcmpUltDouble:
-; IASM-NEXT: .LfcmpUltDouble$entry:
-; IASM-NEXT: .byte 0x35
-; IASM-NEXT: .byte 0x60
-; IASM-NEXT: .byte 0x2e
-; IASM-NEXT: .byte 0x46
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x2
-; IASM-NEXT: .byte 0x24
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x42
-; IASM-NEXT: .byte 0x30
-; IASM-NEXT: .byte 0x8
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xe0
-; IASM-NEXT: .byte 0x3
-
-define internal i32 @fcmpUleFloat(float %a, float %b) {
-entry:
- %cmp = fcmp ule float %a, %b
- %cmp.ret_ext = zext i1 %cmp to i32
- ret i32 %cmp.ret_ext
-}
-
-; ASM-LABEL: fcmpUleFloat
-; ASM-NEXT: .LfcmpUleFloat$entry:
-; ASM: c.ule.s $f12, $f14
-; ASM: addiu $v0, $zero, 1
-; ASM: movf $v0, $zero, $fcc0
-; ASM-NEXT: andi $v0, $v0, 1
-; ASM-NEXT: jr $ra
-
-; DIS-LABEL: 000002e0 <fcmpUleFloat>:
-; DIS-NEXT: 2e0: 460e6037 c.ule.s $f12,$f14
-; DIS-NEXT: 2e4: 24020001 li v0,1
-; DIS-NEXT: 2e8: 00001001 movf v0,zero,$fcc0
-; DIS-NEXT: 2ec: 30420001 andi v0,v0,0x1
-; DIS-NEXT: 2f0: 03e00008 jr ra
-
-; IASM-LABEL: fcmpUleFloat:
-; IASM-NEXT: .LfcmpUleFloat$entry:
-; IASM-NEXT: .byte 0x37
-; IASM-NEXT: .byte 0x60
-; IASM-NEXT: .byte 0xe
-; IASM-NEXT: .byte 0x46
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x2
-; IASM-NEXT: .byte 0x24
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x42
-; IASM-NEXT: .byte 0x30
-; IASM-NEXT: .byte 0x8
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xe0
-; IASM-NEXT: .byte 0x3
-
-define internal i32 @fcmpUleDouble(double %a, double %b) {
-entry:
- %cmp = fcmp ule double %a, %b
- %cmp.ret_ext = zext i1 %cmp to i32
- ret i32 %cmp.ret_ext
-}
-
-; ASM-LABEL: fcmpUleDouble
-; ASM-NEXT: .LfcmpUleDouble$entry:
-; ASM: c.ule.d $f12, $f14
-; ASM: addiu $v0, $zero, 1
-; ASM: movf $v0, $zero, $fcc0
-; ASM-NEXT: andi $v0, $v0, 1
-; ASM-NEXT: jr $ra
-
-; DIS-LABEL: 00000300 <fcmpUleDouble>:
-; DIS-NEXT: 300: 462e6037 c.ule.d $f12,$f14
-; DIS-NEXT: 304: 24020001 li v0,1
-; DIS-NEXT: 308: 00001001 movf v0,zero,$fcc0
-; DIS-NEXT: 30c: 30420001 andi v0,v0,0x1
-; DIS-NEXT: 310: 03e00008 jr ra
-
-; IASM-LABEL: fcmpUleDouble:
-; IASM-NEXT: .LfcmpUleDouble$entry:
-; IASM-NEXT: .byte 0x37
-; IASM-NEXT: .byte 0x60
-; IASM-NEXT: .byte 0x2e
-; IASM-NEXT: .byte 0x46
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x2
-; IASM-NEXT: .byte 0x24
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x42
-; IASM-NEXT: .byte 0x30
-; IASM-NEXT: .byte 0x8
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xe0
-; IASM-NEXT: .byte 0x3
-
-define internal i32 @fcmpUneFloat(float %a, float %b) {
-entry:
- %cmp = fcmp une float %a, %b
- %cmp.ret_ext = zext i1 %cmp to i32
- ret i32 %cmp.ret_ext
-}
-
-; ASM-LABEL: fcmpUneFloat
-; ASM-NEXT: .LfcmpUneFloat$entry:
-; ASM: c.eq.s $f12, $f14
-; ASM: addiu $v0, $zero, 1
-; ASM: movt $v0, $zero, $fcc0
-; ASM-NEXT: andi $v0, $v0, 1
-; ASM-NEXT: jr $ra
-
-; DIS-LABEL: 00000320 <fcmpUneFloat>:
-; DIS-NEXT: 320: 460e6032 c.eq.s $f12,$f14
-; DIS-NEXT: 324: 24020001 li v0,1
-; DIS-NEXT: 328: 00011001 movt v0,zero,$fcc0
-; DIS-NEXT: 32c: 30420001 andi v0,v0,0x1
-; DIS-NEXT: 330: 03e00008 jr ra
-
-; IASM-LABEL: fcmpUneFloat:
-; IASM-NEXT: .LfcmpUneFloat$entry:
-; IASM-NEXT: .byte 0x32
-; IASM-NEXT: .byte 0x60
-; IASM-NEXT: .byte 0xe
-; IASM-NEXT: .byte 0x46
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x2
-; IASM-NEXT: .byte 0x24
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x42
-; IASM-NEXT: .byte 0x30
-; IASM-NEXT: .byte 0x8
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xe0
-; IASM-NEXT: .byte 0x3
-
-define internal i32 @fcmpUneDouble(double %a, double %b) {
-entry:
- %cmp = fcmp une double %a, %b
- %cmp.ret_ext = zext i1 %cmp to i32
- ret i32 %cmp.ret_ext
-}
-
-; ASM-LABEL: fcmpUneDouble
-; ASM-NEXT: .LfcmpUneDouble$entry:
-; ASM: c.eq.d $f12, $f14
-; ASM: addiu $v0, $zero, 1
-; ASM: movt $v0, $zero, $fcc0
-; ASM-NEXT: andi $v0, $v0, 1
-; ASM-NEXT: jr $ra
-
-; DIS-LABEL: 00000340 <fcmpUneDouble>:
-; DIS-NEXT: 340: 462e6032 c.eq.d $f12,$f14
-; DIS-NEXT: 344: 24020001 li v0,1
-; DIS-NEXT: 348: 00011001 movt v0,zero,$fcc0
-; DIS-NEXT: 34c: 30420001 andi v0,v0,0x1
-; DIS-NEXT: 350: 03e00008 jr ra
-
-; IASM-LABEL: fcmpUneDouble:
-; IASM-NEXT: .LfcmpUneDouble$entry:
-; IASM-NEXT: .byte 0x32
-; IASM-NEXT: .byte 0x60
-; IASM-NEXT: .byte 0x2e
-; IASM-NEXT: .byte 0x46
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x2
-; IASM-NEXT: .byte 0x24
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x42
-; IASM-NEXT: .byte 0x30
-; IASM-NEXT: .byte 0x8
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xe0
-; IASM-NEXT: .byte 0x3
-
-define internal i32 @fcmpUnoFloat(float %a, float %b) {
-entry:
- %cmp = fcmp uno float %a, %b
- %cmp.ret_ext = zext i1 %cmp to i32
- ret i32 %cmp.ret_ext
-}
-
-; ASM-LABEL: fcmpUnoFloat
-; ASM-NEXT: .LfcmpUnoFloat$entry:
-; ASM: c.un.s $f12, $f14
-; ASM: addiu $v0, $zero, 1
-; ASM: movf $v0, $zero, $fcc0
-; ASM-NEXT: andi $v0, $v0, 1
-; ASM-NEXT: jr $ra
-
-; DIS-LABEL: 00000360 <fcmpUnoFloat>:
-; DIS-NEXT: 360: 460e6031 c.un.s $f12,$f14
-; DIS-NEXT: 364: 24020001 li v0,1
-; DIS-NEXT: 368: 00001001 movf v0,zero,$fcc0
-; DIS-NEXT: 36c: 30420001 andi v0,v0,0x1
-; DIS-NEXT: 370: 03e00008 jr ra
-
-; IASM-LABEL: fcmpUnoFloat:
-; IASM-NEXT: .LfcmpUnoFloat$entry:
-; IASM-NEXT: .byte 0x31
-; IASM-NEXT: .byte 0x60
-; IASM-NEXT: .byte 0xe
-; IASM-NEXT: .byte 0x46
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x2
-; IASM-NEXT: .byte 0x24
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x42
-; IASM-NEXT: .byte 0x30
-; IASM-NEXT: .byte 0x8
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xe0
-; IASM-NEXT: .byte 0x3
-
-define internal i32 @fcmpUnoDouble(double %a, double %b) {
-entry:
- %cmp = fcmp uno double %a, %b
- %cmp.ret_ext = zext i1 %cmp to i32
- ret i32 %cmp.ret_ext
-}
-
-; ASM-LABEL: fcmpUnoDouble
-; ASM-NEXT: .LfcmpUnoDouble$entry:
-; ASM: c.un.d $f12, $f14
-; ASM: addiu $v0, $zero, 1
-; ASM: movf $v0, $zero, $fcc0
-; ASM-NEXT: andi $v0, $v0, 1
-; ASM-NEXT: jr $ra
-
-; DIS-LABEL: 00000380 <fcmpUnoDouble>:
-; DIS-NEXT: 380: 462e6031 c.un.d $f12,$f14
-; DIS-NEXT: 384: 24020001 li v0,1
-; DIS-NEXT: 388: 00001001 movf v0,zero,$fcc0
-; DIS-NEXT: 38c: 30420001 andi v0,v0,0x1
-; DIS-NEXT: 390: 03e00008 jr ra
-
-; IASM-LABEL: fcmpUnoDouble:
-; IASM-NEXT: .LfcmpUnoDouble$entry:
-; IASM-NEXT: .byte 0x31
-; IASM-NEXT: .byte 0x60
-; IASM-NEXT: .byte 0x2e
-; IASM-NEXT: .byte 0x46
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x2
-; IASM-NEXT: .byte 0x24
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x10
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x42
-; IASM-NEXT: .byte 0x30
-; IASM-NEXT: .byte 0x8
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xe0
-; IASM-NEXT: .byte 0x3
-
-define internal i32 @fcmpTrueFloat(float %a, float %b) {
-entry:
- %cmp = fcmp true float %a, %b
- %cmp.ret_ext = zext i1 %cmp to i32
- ret i32 %cmp.ret_ext
-}
-
-; ASM-LABEL: fcmpTrueFloat
-; ASM-NEXT: .LfcmpTrueFloat$entry:
-; ASM: addiu $v0, $zero, 1
-; ASM-NEXT: andi $v0, $v0, 1
-; ASM-NEXT: jr $ra
-
-; DIS-LABEL: 000003a0 <fcmpTrueFloat>:
-; DIS-NEXT: 3a0: 24020001 li v0,1
-; DIS-NEXT: 3a4: 30420001 andi v0,v0,0x1
-; DIS-NEXT: 3a8: 03e00008 jr ra
-
-; IASM-LABEL: fcmpTrueFloat:
-; IASM-NEXT: .LfcmpTrueFloat$entry:
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x2
-; IASM-NEXT: .byte 0x24
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x42
-; IASM-NEXT: .byte 0x30
-; IASM-NEXT: .byte 0x8
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xe0
-; IASM-NEXT: .byte 0x3
-
-define internal i32 @fcmpTrueDouble(double %a, double %b) {
-entry:
- %cmp = fcmp true double %a, %b
- %cmp.ret_ext = zext i1 %cmp to i32
- ret i32 %cmp.ret_ext
-}
-
-; ASM-LABEL: fcmpTrueDouble
-; ASM-NEXT: .LfcmpTrueDouble$entry:
-; ASM: addiu $v0, $zero, 1
-; ASM-NEXT: andi $v0, $v0, 1
-; ASM-NEXT: jr $ra
-
-; DIS-LABEL: 000003b0 <fcmpTrueDouble>:
-; DIS-NEXT: 3b0: 24020001 li v0,1
-; DIS-NEXT: 3b4: 30420001 andi v0,v0,0x1
-; DIS-NEXT: 3b8: 03e00008 jr ra
-
-; IASM-LABEL: fcmpTrueDouble:
-; IASM-NEXT: .LfcmpTrueDouble$entry:
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x2
-; IASM-NEXT: .byte 0x24
-; IASM-NEXT: .byte 0x1
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x42
-; IASM-NEXT: .byte 0x30
-; IASM-NEXT: .byte 0x8
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0xe0
-; IASM-NEXT: .byte 0x3
diff --git a/third_party/subzero/tests_lit/assembler/mips32/encoding_trap.ll b/third_party/subzero/tests_lit/assembler/mips32/encoding_trap.ll
deleted file mode 100644
index a65e6a3..0000000
--- a/third_party/subzero/tests_lit/assembler/mips32/encoding_trap.ll
+++ /dev/null
@@ -1,41 +0,0 @@
-; Test encoding of MIPS32 floating point arithmetic instructions
-
-; REQUIRES: allow_dump
-
-; Compile using standalone assembler.
-; RUN: %p2i --filetype=asm -i %s --target=mips32 --args -O2 \
-; RUN: --allow-externally-defined-symbols \
-; RUN: | FileCheck %s --check-prefix=ASM
-
-; Show bytes in assembled standalone code.
-; RUN: %p2i --filetype=asm -i %s --target=mips32 --assemble --disassemble \
-; RUN: --args -O2 --allow-externally-defined-symbols \
-; RUN: | FileCheck %s --check-prefix=DIS
-
-; Compile using integrated assembler.
-; RUN: %p2i --filetype=iasm -i %s --target=mips32 --args -O2 \
-; RUN: --allow-externally-defined-symbols \
-; RUN: | FileCheck %s --check-prefix=IASM
-
-; Show bytes in assembled integrated code.
-; RUN: %p2i --filetype=iasm -i %s --target=mips32 --assemble --disassemble \
-; RUN: --args -O2 --allow-externally-defined-symbols \
-; RUN: | FileCheck %s --check-prefix=DIS
-
-define internal void @encTrap() {
- unreachable
-}
-
-; ASM-LABEL: encTrap
-; ASM-NEXT: .LencTrap$__0:
-; ASM: teq $zero, $zero, 0
-
-; DIS-LABEL: 00000000 <encTrap>:
-; DIS-NEXT: 0: 00000034 teq zero,zero
-
-; IASM-LABEL: encTrap:
-; IASM-NEXT: .LencTrap$__0:
-; IASM-NEXT: .byte 0x34
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
-; IASM-NEXT: .byte 0x0
diff --git a/third_party/subzero/tests_lit/assembler/x86/immediate_encodings.ll b/third_party/subzero/tests_lit/assembler/x86/immediate_encodings.ll
deleted file mode 100644
index 5a35285..0000000
--- a/third_party/subzero/tests_lit/assembler/x86/immediate_encodings.ll
+++ /dev/null
@@ -1,390 +0,0 @@
-; Tests various aspects of x86 immediate encoding. Some encodings are shorter.
-; For example, the encoding is shorter for 8-bit immediates or when using EAX.
-; This assumes that EAX is chosen as the first free register in O2 mode.
-
-; RUN: %p2i --filetype=obj --disassemble -i %s --args -O2 | FileCheck %s
-
-define internal i32 @testXor8Imm8(i32 %arg) {
-entry:
- %arg_i8 = trunc i32 %arg to i8
- %result_i8 = xor i8 %arg_i8, 127
- %result = zext i8 %result_i8 to i32
- ret i32 %result
-}
-; CHECK-LABEL: testXor8Imm8
-; CHECK: 34 7f xor al
-
-define internal i32 @testXor8Imm8Neg(i32 %arg) {
-entry:
- %arg_i8 = trunc i32 %arg to i8
- %result_i8 = xor i8 %arg_i8, -128
- %result = zext i8 %result_i8 to i32
- ret i32 %result
-}
-; CHECK-LABEL: testXor8Imm8Neg
-; CHECK: 34 80 xor al
-
-define internal i32 @testXor8Imm8NotEAX(i32 %arg, i32 %arg2, i32 %arg3) {
-entry:
- %arg_i8 = trunc i32 %arg to i8
- %arg2_i8 = trunc i32 %arg2 to i8
- %arg3_i8 = trunc i32 %arg3 to i8
- %x1 = xor i8 %arg_i8, 127
- %x2 = xor i8 %arg2_i8, 127
- %x3 = xor i8 %arg3_i8, 127
- %x4 = add i8 %x1, %x2
- %x5 = add i8 %x4, %x3
- %result = zext i8 %x5 to i32
- ret i32 %result
-}
-; CHECK-LABEL: testXor8Imm8NotEAX
-; CHECK: 80 f{{[1-3]}} 7f xor {{[^a]}}l
-
-define internal i32 @testXor16Imm8(i32 %arg) {
-entry:
- %arg_i16 = trunc i32 %arg to i16
- %result_i16 = xor i16 %arg_i16, 127
- %result = zext i16 %result_i16 to i32
- ret i32 %result
-}
-; CHECK-LABEL: testXor16Imm8
-; CHECK: 66 83 f0 7f xor ax
-
-define internal i32 @testXor16Imm8Neg(i32 %arg) {
-entry:
- %arg_i16 = trunc i32 %arg to i16
- %result_i16 = xor i16 %arg_i16, -128
- %result = zext i16 %result_i16 to i32
- ret i32 %result
-}
-; CHECK-LABEL: testXor16Imm8Neg
-; CHECK: 66 83 f0 80 xor ax
-
-define internal i32 @testXor16Imm16Eax(i32 %arg) {
-entry:
- %arg_i16 = trunc i32 %arg to i16
- %tmp = xor i16 %arg_i16, 1024
- %result_i16 = add i16 %tmp, 1
- %result = zext i16 %result_i16 to i32
- ret i32 %result
-}
-; CHECK-LABEL: testXor16Imm16Eax
-; CHECK: 66 35 00 04 xor ax
-; CHECK-NEXT: add ax,0x1
-
-define internal i32 @testXor16Imm16NegEax(i32 %arg) {
-entry:
- %arg_i16 = trunc i32 %arg to i16
- %tmp = xor i16 %arg_i16, -256
- %result_i16 = add i16 %tmp, 1
- %result = zext i16 %result_i16 to i32
- ret i32 %result
-}
-; CHECK-LABEL: testXor16Imm16NegEax
-; CHECK: 66 35 00 ff xor ax
-; CHECK-NEXT: add ax,0x1
-
-define internal i32 @testXor16Imm16NotEAX(i32 %arg_i32, i32 %arg2_i32, i32 %arg3_i32) {
-entry:
- %arg = trunc i32 %arg_i32 to i16
- %arg2 = trunc i32 %arg2_i32 to i16
- %arg3 = trunc i32 %arg3_i32 to i16
- %x = xor i16 %arg, 32767
- %x2 = xor i16 %arg2, 32767
- %x3 = xor i16 %arg3, 32767
- %add1 = add i16 %x, %x2
- %add2 = add i16 %add1, %x3
- %result = zext i16 %add2 to i32
- ret i32 %result
-}
-; CHECK-LABEL: testXor16Imm16NotEAX
-; CHECK: 66 81 f{{[1-3]}} ff 7f xor {{[^a]}}x
-; CHECK-NEXT: 66 81 f{{[1-3]}} ff 7f xor {{[^a]}}x
-
-define internal i32 @testXor32Imm8(i32 %arg) {
-entry:
- %result = xor i32 %arg, 127
- ret i32 %result
-}
-; CHECK-LABEL: testXor32Imm8
-; CHECK: 83 f0 7f xor eax
-
-define internal i32 @testXor32Imm8Neg(i32 %arg) {
-entry:
- %result = xor i32 %arg, -128
- ret i32 %result
-}
-; CHECK-LABEL: testXor32Imm8Neg
-; CHECK: 83 f0 80 xor eax
-
-define internal i32 @testXor32Imm32Eax(i32 %arg) {
-entry:
- %result = xor i32 %arg, 16777216
- ret i32 %result
-}
-; CHECK-LABEL: testXor32Imm32Eax
-; CHECK: 35 00 00 00 01 xor eax
-
-define internal i32 @testXor32Imm32NegEax(i32 %arg) {
-entry:
- %result = xor i32 %arg, -256
- ret i32 %result
-}
-; CHECK-LABEL: testXor32Imm32NegEax
-; CHECK: 35 00 ff ff ff xor eax
-
-define internal i32 @testXor32Imm32NotEAX(i32 %arg, i32 %arg2, i32 %arg3) {
-entry:
- %x = xor i32 %arg, 32767
- %x2 = xor i32 %arg2, 32767
- %x3 = xor i32 %arg3, 32767
- %add1 = add i32 %x, %x2
- %add2 = add i32 %add1, %x3
- ret i32 %add2
-}
-; CHECK-LABEL: testXor32Imm32NotEAX
-; CHECK: 81 f{{[1-3]}} ff 7f 00 00 xor e{{[^a]}}x,
-
-; Should be similar for add, sub, etc., so sample a few.
-
-define internal i32 @testAdd8Imm8(i32 %arg) {
-entry:
- %arg_i8 = trunc i32 %arg to i8
- %result_i8 = add i8 %arg_i8, 126
- %result = zext i8 %result_i8 to i32
- ret i32 %result
-}
-; CHECK-LABEL: testAdd8Imm8
-; CHECK: 04 7e add al
-
-define internal i32 @testSub8Imm8(i32 %arg) {
-entry:
- %arg_i8 = trunc i32 %arg to i8
- %result_i8 = sub i8 %arg_i8, 125
- %result = zext i8 %result_i8 to i32
- ret i32 %result
-}
-; CHECK-LABEL: testSub8Imm8
-; CHECK: 2c 7d sub al
-
-; imul has some shorter 8-bit immediate encodings.
-; It also has a shorter encoding for eax, but we don't do that yet.
-
-define internal i32 @testMul16Imm8(i32 %arg) {
-entry:
- %arg_i16 = trunc i32 %arg to i16
- %tmp = mul i16 %arg_i16, 99
- %result_i16 = add i16 %tmp, 1
- %result = zext i16 %result_i16 to i32
- ret i32 %result
-}
-; CHECK-LABEL: testMul16Imm8
-; CHECK: 66 6b c0 63 imul ax,ax
-; CHECK-NEXT: add ax,0x1
-
-define internal i32 @testMul16Imm8Neg(i32 %arg) {
-entry:
- %arg_i16 = trunc i32 %arg to i16
- %tmp = mul i16 %arg_i16, -111
- %result_i16 = add i16 %tmp, 1
- %result = zext i16 %result_i16 to i32
- ret i32 %result
-}
-; CHECK-LABEL: testMul16Imm8Neg
-; CHECK: 66 6b c0 91 imul ax,ax
-; CHECK-NEXT: add ax,0x1
-
-define internal i32 @testMul16Imm16(i32 %arg) {
-entry:
- %arg_i16 = trunc i32 %arg to i16
- %tmp = mul i16 %arg_i16, 1025
- %result_i16 = add i16 %tmp, 1
- %result = zext i16 %result_i16 to i32
- ret i32 %result
-}
-; CHECK-LABEL: testMul16Imm16
-; CHECK: 66 69 c0 01 04 imul ax,ax
-; CHECK-NEXT: add ax,0x1
-
-define internal i32 @testMul16Imm16Neg(i32 %arg) {
-entry:
- %arg_i16 = trunc i32 %arg to i16
- %tmp = mul i16 %arg_i16, -255
- %result_i16 = add i16 %tmp, 1
- %result = zext i16 %result_i16 to i32
- ret i32 %result
-}
-; CHECK-LABEL: testMul16Imm16Neg
-; CHECK: 66 69 c0 01 ff imul ax,ax,0xff01
-; CHECK-NEXT: add ax,0x1
-
-define internal i32 @testMul32Imm8(i32 %arg) {
-entry:
- %result = mul i32 %arg, 99
- ret i32 %result
-}
-; CHECK-LABEL: testMul32Imm8
-; CHECK: 6b c0 63 imul eax,eax
-
-define internal i32 @testMul32Imm8Neg(i32 %arg) {
-entry:
- %result = mul i32 %arg, -111
- ret i32 %result
-}
-; CHECK-LABEL: testMul32Imm8Neg
-; CHECK: 6b c0 91 imul eax,eax
-
-define internal i32 @testMul32Imm16(i32 %arg) {
-entry:
- %result = mul i32 %arg, 1025
- ret i32 %result
-}
-; CHECK-LABEL: testMul32Imm16
-; CHECK: 69 c0 01 04 00 00 imul eax,eax
-
-define internal i32 @testMul32Imm16Neg(i32 %arg) {
-entry:
- %result = mul i32 %arg, -255
- ret i32 %result
-}
-; CHECK-LABEL: testMul32Imm16Neg
-; CHECK: 69 c0 01 ff ff ff imul eax,eax,0xffffff01
-
-define internal i32 @testMul32Imm32ThreeAddress(i32 %a) {
-entry:
- %mul = mul i32 232, %a
- %add = add i32 %mul, %a
- ret i32 %add
-}
-; CHECK-LABEL: testMul32Imm32ThreeAddress
-; CHECK: 69 c8 e8 00 00 00 imul ecx,eax,0xe8
-
-define internal i32 @testMul32Mem32Imm32ThreeAddress(i32 %addr_arg) {
-entry:
- %__1 = inttoptr i32 %addr_arg to i32*
- %a = load i32, i32* %__1, align 1
- %mul = mul i32 232, %a
- ret i32 %mul
-}
-; CHECK-LABEL: testMul32Mem32Imm32ThreeAddress
-; CHECK: 69 00 e8 00 00 00 imul eax,DWORD PTR [eax],0xe8
-
-define internal i32 @testMul32Imm8ThreeAddress(i32 %a) {
-entry:
- %mul = mul i32 127, %a
- %add = add i32 %mul, %a
- ret i32 %add
-}
-; CHECK-LABEL: testMul32Imm8ThreeAddress
-; CHECK: 6b c8 7f imul ecx,eax,0x7f
-
-define internal i32 @testMul32Mem32Imm8ThreeAddress(i32 %addr_arg) {
-entry:
- %__1 = inttoptr i32 %addr_arg to i32*
- %a = load i32, i32* %__1, align 1
- %mul = mul i32 127, %a
- ret i32 %mul
-}
-; CHECK-LABEL: testMul32Mem32Imm8ThreeAddress
-; CHECK: 6b 00 7f imul eax,DWORD PTR [eax],0x7f
-
-define internal i32 @testMul16Imm16ThreeAddress(i32 %a) {
-entry:
- %arg_i16 = trunc i32 %a to i16
- %mul = mul i16 232, %arg_i16
- %add = add i16 %mul, %arg_i16
- %result = zext i16 %add to i32
- ret i32 %result
-}
-; CHECK-LABEL: testMul16Imm16ThreeAddress
-; CHECK: 66 69 c8 e8 00 imul cx,ax,0xe8
-
-define internal i32 @testMul16Mem16Imm16ThreeAddress(i32 %addr_arg) {
-entry:
- %__1 = inttoptr i32 %addr_arg to i16*
- %a = load i16, i16* %__1, align 1
- %mul = mul i16 232, %a
- %result = zext i16 %mul to i32
- ret i32 %result
-}
-; CHECK-LABEL: testMul16Mem16Imm16ThreeAddress
-; CHECK: 66 69 00 e8 00 imul ax,WORD PTR [eax],0xe8
-
-define internal i32 @testMul16Imm8ThreeAddress(i32 %a) {
-entry:
- %arg_i16 = trunc i32 %a to i16
- %mul = mul i16 127, %arg_i16
- %add = add i16 %mul, %arg_i16
- %result = zext i16 %add to i32
- ret i32 %result
-}
-; CHECK-LABEL: testMul16Imm8ThreeAddress
-; CHECK: 66 6b c8 7f imul cx,ax,0x7f
-
-define internal i32 @testMul16Mem16Imm8ThreeAddress(i32 %addr_arg) {
-entry:
- %__1 = inttoptr i32 %addr_arg to i16*
- %a = load i16, i16* %__1, align 1
- %mul = mul i16 127, %a
- %result = zext i16 %mul to i32
- ret i32 %result
-}
-; CHECK-LABEL: testMul16Mem16Imm8ThreeAddress
-; CHECK: 66 6b 00 7f imul ax,WORD PTR [eax],0x7f
-
-; The GPR shift instructions either allow an 8-bit immediate or
-; have a special encoding for "1".
-define internal i32 @testShl16Imm8(i32 %arg) {
-entry:
- %arg_i16 = trunc i32 %arg to i16
- %tmp = shl i16 %arg_i16, 13
- %result = zext i16 %tmp to i32
- ret i32 %result
-}
-; CHECK-LABEL: testShl16Imm8
-; CHECK: 66 c1 e0 0d shl ax,0xd
-
-define internal i32 @testShl16Imm1(i32 %arg) {
-entry:
- %arg_i16 = trunc i32 %arg to i16
- %tmp = shl i16 %arg_i16, 1
- %result = zext i16 %tmp to i32
- ret i32 %result
-}
-; CHECK-LABEL: testShl16Imm1
-; CHECK: 66 d1 e0 shl ax
-
-; Currently the "test" instruction is used for 64-bit shifts, and
-; for ctlz 64-bit, so we use those to test the "test" instruction.
-; One optimization for "test": the "test" instruction is essentially a
-; bitwise AND that doesn't modify the two source operands, so for immediates
-; under 8-bits and registers with 8-bit variants we can use the shorter form.
-
-define internal i64 @test_via_shl64Bit(i64 %a, i64 %b) {
-entry:
- %shl = shl i64 %a, %b
- ret i64 %shl
-}
-; CHECK-LABEL: test_via_shl64Bit
-; CHECK: 0f a5 c2 shld edx,eax,cl
-; CHECK: d3 e0 shl eax,cl
-; CHECK: f6 c1 20 test cl,0x20
-
-; Test a few register encodings of "test".
-declare i64 @llvm.ctlz.i64(i64, i1)
-
-define internal i64 @test_via_ctlz_64(i64 %x, i64 %y, i64 %z, i64 %w) {
-entry:
- %r = call i64 @llvm.ctlz.i64(i64 %x, i1 false)
- %r2 = call i64 @llvm.ctlz.i64(i64 %y, i1 false)
- %r3 = call i64 @llvm.ctlz.i64(i64 %z, i1 false)
- %r4 = call i64 @llvm.ctlz.i64(i64 %w, i1 false)
- %res1 = add i64 %r, %r2
- %res2 = add i64 %r3, %r4
- %res = add i64 %res1, %res2
- ret i64 %res
-}
-; CHECK-LABEL: test_via_ctlz_64
-; CHECK-DAG: 85 c0 test eax,eax
-; CHECK-DAG: 85 db test ebx,ebx
-; CHECK-DAG: 85 f6 test esi,esi
diff --git a/third_party/subzero/tests_lit/assembler/x86/jump_encodings.ll b/third_party/subzero/tests_lit/assembler/x86/jump_encodings.ll
deleted file mode 100644
index e7d444e..0000000
--- a/third_party/subzero/tests_lit/assembler/x86/jump_encodings.ll
+++ /dev/null
@@ -1,203 +0,0 @@
-; Tests various aspects of x86 branch encodings (near vs far,
-; forward vs backward, using CFG labels, or local labels).
-
-; Use -ffunction-sections so that the offsets reset for each function.
-; RUN: %p2i --filetype=obj --disassemble -i %s --args -O2 \
-; RUN: -ffunction-sections | FileCheck %s
-
-; Use atomic ops as filler, which shouldn't get optimized out.
-declare void @llvm.nacl.atomic.store.i32(i32, i32*, i32)
-declare i32 @llvm.nacl.atomic.load.i32(i32*, i32)
-declare i32 @llvm.nacl.atomic.rmw.i32(i32, i32*, i32, i32)
-
-define internal void @test_near_backward(i32 %iptr, i32 %val) {
-entry:
- br label %next
-next:
- %ptr = inttoptr i32 %iptr to i32*
- call void @llvm.nacl.atomic.store.i32(i32 %val, i32* %ptr, i32 6)
- br label %next2
-next2:
- call void @llvm.nacl.atomic.store.i32(i32 %val, i32* %ptr, i32 6)
- %cmp = icmp ult i32 %val, 1
- br i1 %cmp, label %next2, label %next
-}
-
-; CHECK-LABEL: test_near_backward
-; CHECK: 8: {{.*}} mov DWORD PTR
-; CHECK-NEXT: a: {{.*}} mfence
-; CHECK-NEXT: d: {{.*}} mov DWORD PTR
-; CHECK-NEXT: f: {{.*}} mfence
-; CHECK-NEXT: 12: {{.*}} cmp
-; CHECK-NEXT: 15: 72 f6 jb d
-; CHECK-NEXT: 17: eb ef jmp 8
-
-; Test one of the backward branches being too large for 8 bits
-; and one being just okay.
-define internal void @test_far_backward1(i32 %iptr, i32 %val) {
-entry:
- br label %next
-next:
- %ptr = inttoptr i32 %iptr to i32*
- %tmp = call i32 @llvm.nacl.atomic.load.i32(i32* %ptr, i32 6)
- br label %next2
-next2:
- call void @llvm.nacl.atomic.store.i32(i32 %tmp, i32* %ptr, i32 6)
- call void @llvm.nacl.atomic.store.i32(i32 %val, i32* %ptr, i32 6)
- call void @llvm.nacl.atomic.store.i32(i32 %val, i32* %ptr, i32 6)
- call void @llvm.nacl.atomic.store.i32(i32 %val, i32* %ptr, i32 6)
- call void @llvm.nacl.atomic.store.i32(i32 %val, i32* %ptr, i32 6)
- call void @llvm.nacl.atomic.store.i32(i32 %val, i32* %ptr, i32 6)
- call void @llvm.nacl.atomic.store.i32(i32 %val, i32* %ptr, i32 6)
- call void @llvm.nacl.atomic.store.i32(i32 %val, i32* %ptr, i32 6)
- call void @llvm.nacl.atomic.store.i32(i32 %val, i32* %ptr, i32 6)
- call void @llvm.nacl.atomic.store.i32(i32 %val, i32* %ptr, i32 6)
- call void @llvm.nacl.atomic.store.i32(i32 %val, i32* %ptr, i32 6)
- call void @llvm.nacl.atomic.store.i32(i32 %val, i32* %ptr, i32 6)
- call void @llvm.nacl.atomic.store.i32(i32 %val, i32* %ptr, i32 6)
- call void @llvm.nacl.atomic.store.i32(i32 %val, i32* %ptr, i32 6)
- call void @llvm.nacl.atomic.store.i32(i32 %val, i32* %ptr, i32 6)
- call void @llvm.nacl.atomic.store.i32(i32 %val, i32* %ptr, i32 6)
- call void @llvm.nacl.atomic.store.i32(i32 %val, i32* %ptr, i32 6)
- call void @llvm.nacl.atomic.store.i32(i32 %val, i32* %ptr, i32 6)
- call void @llvm.nacl.atomic.store.i32(i32 %val, i32* %ptr, i32 6)
- call void @llvm.nacl.atomic.store.i32(i32 %val, i32* %ptr, i32 6)
- call void @llvm.nacl.atomic.store.i32(i32 %val, i32* %ptr, i32 6)
- call void @llvm.nacl.atomic.store.i32(i32 %val, i32* %ptr, i32 6)
- call void @llvm.nacl.atomic.store.i32(i32 %val, i32* %ptr, i32 6)
- call void @llvm.nacl.atomic.store.i32(i32 %val, i32* %ptr, i32 6)
- %cmp = icmp ugt i32 %val, 0
- br i1 %cmp, label %next2, label %next
-}
-
-; CHECK-LABEL: test_far_backward1
-; CHECK: 8: {{.*}} mov {{.*}},DWORD PTR [e{{[^s]}}
-; CHECK-NEXT: a: {{.*}} mov DWORD PTR
-; CHECK-NEXT: c: {{.*}} mfence
-; CHECK: 85: 77 83 ja a
-; CHECK-NEXT: 87: e9 7c ff ff ff jmp 8
-
-; Same as test_far_backward1, but with the conditional branch being
-; the one that is too far.
-define internal void @test_far_backward2(i32 %iptr, i32 %val) {
-entry:
- br label %next
-next:
- %ptr = inttoptr i32 %iptr to i32*
- %tmp = call i32 @llvm.nacl.atomic.load.i32(i32* %ptr, i32 6)
- %tmp2 = call i32 @llvm.nacl.atomic.load.i32(i32* %ptr, i32 6)
- %tmp3 = call i32 @llvm.nacl.atomic.load.i32(i32* %ptr, i32 6)
- %tmp4 = call i32 @llvm.nacl.atomic.load.i32(i32* %ptr, i32 6)
- %tmp5 = call i32 @llvm.nacl.atomic.load.i32(i32* %ptr, i32 6)
- br label %next2
-next2:
- call void @llvm.nacl.atomic.store.i32(i32 %tmp, i32* %ptr, i32 6)
- call void @llvm.nacl.atomic.store.i32(i32 %tmp2, i32* %ptr, i32 6)
- call void @llvm.nacl.atomic.store.i32(i32 %tmp3, i32* %ptr, i32 6)
- call void @llvm.nacl.atomic.store.i32(i32 %tmp4, i32* %ptr, i32 6)
- call void @llvm.nacl.atomic.store.i32(i32 %tmp5, i32* %ptr, i32 6)
- call void @llvm.nacl.atomic.store.i32(i32 %val, i32* %ptr, i32 6)
- call void @llvm.nacl.atomic.store.i32(i32 %val, i32* %ptr, i32 6)
- call void @llvm.nacl.atomic.store.i32(i32 %val, i32* %ptr, i32 6)
- call void @llvm.nacl.atomic.store.i32(i32 %val, i32* %ptr, i32 6)
- call void @llvm.nacl.atomic.store.i32(i32 %val, i32* %ptr, i32 6)
- call void @llvm.nacl.atomic.store.i32(i32 %val, i32* %ptr, i32 6)
- call void @llvm.nacl.atomic.store.i32(i32 %val, i32* %ptr, i32 6)
- call void @llvm.nacl.atomic.store.i32(i32 %val, i32* %ptr, i32 6)
- call void @llvm.nacl.atomic.store.i32(i32 %val, i32* %ptr, i32 6)
- call void @llvm.nacl.atomic.store.i32(i32 %val, i32* %ptr, i32 6)
- call void @llvm.nacl.atomic.store.i32(i32 %val, i32* %ptr, i32 6)
- call void @llvm.nacl.atomic.store.i32(i32 %val, i32* %ptr, i32 6)
- call void @llvm.nacl.atomic.store.i32(i32 %val, i32* %ptr, i32 6)
- call void @llvm.nacl.atomic.store.i32(i32 %val, i32* %ptr, i32 6)
- call void @llvm.nacl.atomic.store.i32(i32 %val, i32* %ptr, i32 6)
- call void @llvm.nacl.atomic.store.i32(i32 %val, i32* %ptr, i32 6)
- call void @llvm.nacl.atomic.store.i32(i32 %val, i32* %ptr, i32 6)
- call void @llvm.nacl.atomic.store.i32(i32 %val, i32* %ptr, i32 6)
- %cmp = icmp sle i32 %val, 0
- br i1 %cmp, label %next, label %next2
-}
-
-; CHECK-LABEL: test_far_backward2
-; CHECK: c: {{.*}} mov {{.*}},DWORD PTR [e{{[^s]}}
-; CHECK: 14: {{.*}} mov {{.*}},DWORD PTR
-; CHECK-NEXT: 16: {{.*}} mov DWORD PTR
-; CHECK-NEXT: 18: {{.*}} mfence
-; CHECK: 8c: 0f 8e 7a ff ff ff jle c
-; CHECK-NEXT: 92: eb 82 jmp 16
-
-define internal void @test_near_forward(i32 %iptr, i32 %val) {
-entry:
- br label %next1
-next1:
- %ptr = inttoptr i32 %iptr to i32*
- %cmp = icmp ult i32 %val, 1
- br i1 %cmp, label %next3, label %next2
-next2:
- call void @llvm.nacl.atomic.store.i32(i32 %val, i32* %ptr, i32 6)
- br label %next3
-next3:
- call void @llvm.nacl.atomic.store.i32(i32 %val, i32* %ptr, i32 6)
- br label %next1
-}
-; Note: forward branches for non-local labels in Subzero currently use the fully
-; relaxed form (4-byte offset) to avoid needing a relaxation pass. When we use
-; llvm-mc, it performs the relaxation pass and uses a 1-byte offset.
-; CHECK-LABEL: test_near_forward
-; CHECK: [[BACKLABEL:[0-9a-f]+]]: {{.*}} cmp
-; CHECK-NEXT: {{.*}} jb [[FORWARDLABEL:[0-9a-f]+]]
-; CHECK-NEXT: {{.*}} mov DWORD PTR
-; CHECK-NEXT: {{.*}} mfence
-; CHECK-NEXT: [[FORWARDLABEL]]: {{.*}} mov DWORD PTR
-; CHECK: {{.*}} jmp [[BACKLABEL]]
-
-
-; Unlike forward branches to cfg nodes, "local" forward branches
-; always use a 1 byte displacement.
-; Check local forward branches, followed by a near backward branch
-; to make sure that the instruction size accounting for the forward
-; branches are correct, by the time the backward branch is hit.
-; A 64-bit compare happens to use local forward branches.
-define internal void @test_local_forward_then_back(i64 %val64, i32 %iptr,
- i32 %val) {
-entry:
- br label %next
-next:
- %ptr = inttoptr i32 %iptr to i32*
- call void @llvm.nacl.atomic.store.i32(i32 %val, i32* %ptr, i32 6)
- br label %next2
-next2:
- %cmp = icmp ult i64 %val64, 1
- br i1 %cmp, label %next, label %next2
-}
-; CHECK-LABEL: test_local_forward_then_back
-; CHECK: {{.*}} mov DWORD PTR
-; CHECK-NEXT: {{.*}} mfence
-; CHECK-NEXT: [[LABEL:[0-9a-f]+]]: {{.*}} cmp
-; CHECK-NEXT: {{.*}} jb
-; CHECK-NEXT: {{.*}} ja
-; CHECK-NEXT: {{.*}} cmp
-; CHECK-NEXT: {{.*}} jb
-; CHECK-NEXT: {{.*}} jmp [[LABEL]]
-
-
-; Test that backward local branches also work and are small.
-; Some of the atomic instructions use a cmpxchg loop.
-define internal void @test_local_backward(i64 %val64, i32 %iptr, i32 %val) {
-entry:
- br label %next
-next:
- %ptr = inttoptr i32 %iptr to i32*
- %a = call i32 @llvm.nacl.atomic.rmw.i32(i32 5, i32* %ptr, i32 %val, i32 6)
- br label %next2
-next2:
- %success = icmp eq i32 1, %a
- br i1 %success, label %next, label %next2
-}
-; CHECK-LABEL: test_local_backward
-; CHECK: 9: {{.*}} mov {{.*}},DWORD
-; CHECK: b: {{.*}} mov
-; CHECK-NEXT: d: {{.*}} xor
-; CHECK-NEXT: f: {{.*}} lock cmpxchg
-; CHECK-NEXT: 13: 75 f6 jne b
-; CHECK: 1c: 74 eb je 9
diff --git a/third_party/subzero/tests_lit/assembler/x86/opcode_register_encodings.ll b/third_party/subzero/tests_lit/assembler/x86/opcode_register_encodings.ll
deleted file mode 100644
index f0a9006..0000000
--- a/third_party/subzero/tests_lit/assembler/x86/opcode_register_encodings.ll
+++ /dev/null
@@ -1,307 +0,0 @@
-; Tests various aspects of x86 opcode encodings. E.g., some opcodes like
-; those for pmull vary more wildly depending on operand size (rather than
-; follow a usual pattern).
-
-; RUN: %p2i --filetype=obj --disassemble --sandbox -i %s --args -O2 \
-; RUN: -mattr=sse4.1 -split-local-vars=0 | FileCheck %s
-
-define internal <8 x i16> @test_mul_v8i16(<8 x i16> %arg0, <8 x i16> %arg1) {
-entry:
- %res = mul <8 x i16> %arg0, %arg1
- ret <8 x i16> %res
-; CHECK-LABEL: test_mul_v8i16
-; CHECK: 66 0f d5 c1 pmullw xmm0,xmm1
-}
-
-; Test register and address mode encoding.
-define internal <8 x i16> @test_mul_v8i16_more_regs(
- <8 x i1> %cond, <8 x i16> %arg0, <8 x i16> %arg1, <8 x i16> %arg2,
- <8 x i16> %arg3, <8 x i16> %arg4, <8 x i16> %arg5, <8 x i16> %arg6,
- <8 x i16> %arg7, <8 x i16> %arg8) {
-entry:
- %res1 = sub <8 x i16> %arg0, %arg1
- %res2 = sub <8 x i16> %arg0, %arg2
- %res3 = sub <8 x i16> %arg0, %arg3
- %res4 = sub <8 x i16> %arg0, %arg4
- %res5 = sub <8 x i16> %arg0, %arg5
- %res6 = sub <8 x i16> %arg0, %arg6
- %res7 = sub <8 x i16> %arg0, %arg7
- %res8 = sub <8 x i16> %arg0, %arg8
- %res_acc1 = select <8 x i1> %cond, <8 x i16> %res1, <8 x i16> %res2
- %res_acc2 = select <8 x i1> %cond, <8 x i16> %res3, <8 x i16> %res4
- %res_acc3 = select <8 x i1> %cond, <8 x i16> %res5, <8 x i16> %res6
- %res_acc4 = select <8 x i1> %cond, <8 x i16> %res7, <8 x i16> %res8
- %res_acc1_3 = select <8 x i1> %cond, <8 x i16> %res_acc1, <8 x i16> %res_acc3
- %res_acc2_4 = select <8 x i1> %cond, <8 x i16> %res_acc2, <8 x i16> %res_acc4
- %res = select <8 x i1> %cond, <8 x i16> %res_acc1_3, <8 x i16> %res_acc2_4
- ret <8 x i16> %res
-; CHECK-LABEL: test_mul_v8i16_more_regs
-; CHECK-DAG: psubw xmm0,{{xmm[0-7]|xmmword ptr\[esp}}
-; CHECK-DAG: psubw xmm0,{{xmm[0-7]|xmmword ptr\[esp}}
-; CHECK-DAG: psubw xmm0,{{xmm[0-7]|xmmword ptr\[esp}}
-; CHECK-DAG: psubw xmm0,{{xmm[0-7]|xmmword ptr\[esp}}
-; CHECK-DAG: psubw xmm0,{{xmm[0-7]|xmmword ptr\[esp}}
-; CHECK-DAG: psubw xmm0,{{xmm[0-7]|xmmword ptr\[esp}}
-; CHECK-DAG: psubw xmm0,XMMWORD PTR [esp
-; CHECK-DAG: psubw xmm1,XMMWORD PTR [esp
-}
-
-define internal <4 x i32> @test_mul_v4i32(<4 x i32> %arg0, <4 x i32> %arg1) {
-entry:
- %res = mul <4 x i32> %arg0, %arg1
- ret <4 x i32> %res
-; CHECK-LABEL: test_mul_v4i32
-; CHECK: 66 0f 38 40 c1 pmulld xmm0,xmm1
-}
-
-define internal <4 x i32> @test_mul_v4i32_more_regs(
- <4 x i1> %cond, <4 x i32> %arg0, <4 x i32> %arg1, <4 x i32> %arg2,
- <4 x i32> %arg3, <4 x i32> %arg4, <4 x i32> %arg5, <4 x i32> %arg6,
- <4 x i32> %arg7, <4 x i32> %arg8) {
-entry:
- %res1 = sub <4 x i32> %arg0, %arg1
- %res2 = sub <4 x i32> %arg0, %arg2
- %res3 = sub <4 x i32> %arg0, %arg3
- %res4 = sub <4 x i32> %arg0, %arg4
- %res5 = sub <4 x i32> %arg0, %arg5
- %res6 = sub <4 x i32> %arg0, %arg6
- %res7 = sub <4 x i32> %arg0, %arg7
- %res8 = sub <4 x i32> %arg0, %arg8
- %res_acc1 = select <4 x i1> %cond, <4 x i32> %res1, <4 x i32> %res2
- %res_acc2 = select <4 x i1> %cond, <4 x i32> %res3, <4 x i32> %res4
- %res_acc3 = select <4 x i1> %cond, <4 x i32> %res5, <4 x i32> %res6
- %res_acc4 = select <4 x i1> %cond, <4 x i32> %res7, <4 x i32> %res8
- %res_acc1_3 = select <4 x i1> %cond, <4 x i32> %res_acc1, <4 x i32> %res_acc3
- %res_acc2_4 = select <4 x i1> %cond, <4 x i32> %res_acc2, <4 x i32> %res_acc4
- %res = select <4 x i1> %cond, <4 x i32> %res_acc1_3, <4 x i32> %res_acc2_4
- ret <4 x i32> %res
-; CHECK-LABEL: test_mul_v4i32_more_regs
-; CHECK-DAG: psubd xmm0,{{xmm[0-7]|xmmword ptr\[esp}}
-; CHECK-DAG: psubd xmm0,{{xmm[0-7]|xmmword ptr\[esp}}
-; CHECK-DAG: psubd xmm0,{{xmm[0-7]|xmmword ptr\[esp}}
-; CHECK-DAG: psubd xmm0,{{xmm[0-7]|xmmword ptr\[esp}}
-; CHECK-DAG: psubd xmm0,{{xmm[0-7]|xmmword ptr\[esp}}
-; CHECK-DAG: psubd xmm0,{{xmm[0-7]|xmmword ptr\[esp}}
-; CHECK-DAG: psubd xmm0,XMMWORD PTR [esp
-; CHECK-DAG: psubd xmm1,XMMWORD PTR [esp
-}
-
-; Test movq, which is used by atomic stores.
-declare void @llvm.nacl.atomic.store.i64(i64, i64*, i32)
-
-define internal void @test_atomic_store_64(i32 %iptr, i32 %iptr2,
- i32 %iptr3, i64 %v) {
-entry:
- %ptr = inttoptr i32 %iptr to i64*
- %ptr2 = inttoptr i32 %iptr2 to i64*
- %ptr3 = inttoptr i32 %iptr3 to i64*
- call void @llvm.nacl.atomic.store.i64(i64 %v, i64* %ptr2, i32 6)
- call void @llvm.nacl.atomic.store.i64(i64 1234567891024, i64* %ptr, i32 6)
- call void @llvm.nacl.atomic.store.i64(i64 %v, i64* %ptr3, i32 6)
- ret void
-}
-; CHECK-LABEL: test_atomic_store_64
-; CHECK-DAG: f3 0f 7e 04 24 movq xmm0,QWORD PTR [esp]
-; CHECK-DAG: f3 0f 7e 44 24 08 movq xmm0,QWORD PTR [esp
-; CHECK-DAG: 66 0f d6 0{{.*}} movq QWORD PTR [e{{.*}}],xmm0
-
-; Test "movups" via vector stores and loads.
-define internal void @store_v16xI8(i32 %addr, i32 %addr2, i32 %addr3,
- <16 x i8> %v) {
- %addr_v16xI8 = inttoptr i32 %addr to <16 x i8>*
- %addr2_v16xI8 = inttoptr i32 %addr2 to <16 x i8>*
- %addr3_v16xI8 = inttoptr i32 %addr3 to <16 x i8>*
- store <16 x i8> %v, <16 x i8>* %addr2_v16xI8, align 1
- store <16 x i8> %v, <16 x i8>* %addr_v16xI8, align 1
- store <16 x i8> %v, <16 x i8>* %addr3_v16xI8, align 1
- ret void
-}
-; CHECK-LABEL: store_v16xI8
-; CHECK: 0f 11 0{{.*}} movups XMMWORD PTR [e{{.*}}],xmm0
-
-define internal <16 x i8> @load_v16xI8(i32 %addr, i32 %addr2, i32 %addr3) {
- %addr_v16xI8 = inttoptr i32 %addr to <16 x i8>*
- %addr2_v16xI8 = inttoptr i32 %addr2 to <16 x i8>*
- %addr3_v16xI8 = inttoptr i32 %addr3 to <16 x i8>*
- %res1 = load <16 x i8>, <16 x i8>* %addr2_v16xI8, align 1
- %res2 = load <16 x i8>, <16 x i8>* %addr_v16xI8, align 1
- %res3 = load <16 x i8>, <16 x i8>* %addr3_v16xI8, align 1
- %res12 = add <16 x i8> %res1, %res2
- %res123 = add <16 x i8> %res12, %res3
- ret <16 x i8> %res123
-}
-; CHECK-LABEL: load_v16xI8
-; CHECK: 0f 10 0{{.*}} movups xmm0,XMMWORD PTR [e{{.*}}]
-
-; Test segment override prefix. This happens w/ nacl.read.tp.
-declare i8* @llvm.nacl.read.tp()
-
-; Also test more address complex operands via address-mode-optimization.
-define internal i32 @test_nacl_read_tp_more_addressing() {
-entry:
- %ptr = call i8* @llvm.nacl.read.tp()
- %__1 = ptrtoint i8* %ptr to i32
- %x = add i32 %__1, %__1
- %__3 = inttoptr i32 %x to i32*
- %v = load i32, i32* %__3, align 1
- %v_add = add i32 %v, 1
-
- %ptr2 = call i8* @llvm.nacl.read.tp()
- %__6 = ptrtoint i8* %ptr2 to i32
- %y = add i32 %__6, -128
- %__8 = inttoptr i32 %y to i32*
- %v_add2 = add i32 %v, 4
- store i32 %v_add2, i32* %__8, align 1
-
- %z = add i32 %__6, 256
- %__9 = inttoptr i32 %z to i32*
- %v_add3 = add i32 %v, 91
- store i32 %v_add2, i32* %__9, align 1
-
- ret i32 %v
-}
-; CHECK-LABEL: test_nacl_read_tp_more_addressing
-; CHECK: mov eax,{{(DWORD PTR )?}}gs:0x0
-; CHECK: 8b 04 00 mov eax,DWORD PTR [eax+eax*1]
-; CHECK: 65 8b 0d 00 00 00 00 mov ecx,DWORD PTR gs:0x0
-; CHECK: 89 51 80 mov DWORD PTR [ecx-0x80],edx
-; CHECK: 89 91 00 01 00 00 mov DWORD PTR [ecx+0x100],edx
-
-; The 16-bit pinsrw/pextrw (SSE2) are quite different from
-; the pinsr{b,d}/pextr{b,d} (SSE4.1).
-
-define internal <4 x i32> @test_pinsrd(<4 x i32> %vec, i32 %elt1, i32 %elt2,
- i32 %elt3, i32 %elt4) {
-entry:
- %elt12 = add i32 %elt1, %elt2
- %elt34 = add i32 %elt3, %elt4
- %res1 = insertelement <4 x i32> %vec, i32 %elt12, i32 1
- %res2 = insertelement <4 x i32> %res1, i32 %elt34, i32 2
- %res3 = insertelement <4 x i32> %res2, i32 %elt1, i32 3
- ret <4 x i32> %res3
-}
-; CHECK-LABEL: test_pinsrd
-; CHECK-DAG: 66 0f 3a 22 c{{.*}} 01 pinsrd xmm0,e{{.*}}
-; CHECK-DAG: 66 0f 3a 22 c{{.*}} 02 pinsrd xmm0,e{{.*}}
-; CHECK-DAG: 66 0f 3a 22 c{{.*}} 03 pinsrd xmm0,e{{.*}}
-
-define internal <16 x i8> @test_pinsrb(<16 x i8> %vec, i32 %elt1_w, i32 %elt2_w,
- i32 %elt3_w, i32 %elt4_w) {
-entry:
- %elt1 = trunc i32 %elt1_w to i8
- %elt2 = trunc i32 %elt2_w to i8
- %elt3 = trunc i32 %elt3_w to i8
- %elt4 = trunc i32 %elt4_w to i8
- %elt12 = add i8 %elt1, %elt2
- %elt34 = add i8 %elt3, %elt4
- %res1 = insertelement <16 x i8> %vec, i8 %elt12, i32 1
- %res2 = insertelement <16 x i8> %res1, i8 %elt34, i32 7
- %res3 = insertelement <16 x i8> %res2, i8 %elt1, i32 15
- ret <16 x i8> %res3
-}
-; CHECK-LABEL: test_pinsrb
-; CHECK-DAG: 66 0f 3a 20 c{{.*}} 01 pinsrb xmm0,e{{.*}}
-; CHECK-DAG: 66 0f 3a 20 c{{.*}} 07 pinsrb xmm0,e{{.*}}
-; CHECK-DAG: 66 0f 3a 20 c{{.*}} 0f pinsrb xmm0,e{{.*}}
-
-define internal <8 x i16> @test_pinsrw(<8 x i16> %vec, i32 %elt1_w, i32 %elt2_w,
- i32 %elt3_w, i32 %elt4_w) {
-entry:
- %elt1 = trunc i32 %elt1_w to i16
- %elt2 = trunc i32 %elt2_w to i16
- %elt3 = trunc i32 %elt3_w to i16
- %elt4 = trunc i32 %elt4_w to i16
- %elt12 = add i16 %elt1, %elt2
- %elt34 = add i16 %elt3, %elt4
- %res1 = insertelement <8 x i16> %vec, i16 %elt12, i32 1
- %res2 = insertelement <8 x i16> %res1, i16 %elt34, i32 4
- %res3 = insertelement <8 x i16> %res2, i16 %elt1, i32 7
- ret <8 x i16> %res3
-}
-; CHECK-LABEL: test_pinsrw
-; CHECK-DAG: 66 0f c4 c{{.*}} 01 pinsrw xmm0,e{{.*}}
-; CHECK-DAG: 66 0f c4 c{{.*}} 04 pinsrw xmm0,e{{.*}}
-; CHECK-DAG: 66 0f c4 c{{.*}} 07 pinsrw xmm0,e{{.*}}
-
-define internal i32 @test_pextrd(i32 %c, <4 x i32> %vec1, <4 x i32> %vec2,
- <4 x i32> %vec3, <4 x i32> %vec4) {
-entry:
- switch i32 %c, label %three [i32 0, label %zero
- i32 1, label %one
- i32 2, label %two]
-zero:
- %res0 = extractelement <4 x i32> %vec1, i32 0
- ret i32 %res0
-one:
- %res1 = extractelement <4 x i32> %vec2, i32 1
- ret i32 %res1
-two:
- %res2 = extractelement <4 x i32> %vec3, i32 2
- ret i32 %res2
-three:
- %res3 = extractelement <4 x i32> %vec4, i32 3
- ret i32 %res3
-}
-; CHECK-LABEL: test_pextrd
-; CHECK-DAG: 66 0f 3a 16 c0 00 pextrd eax,xmm0
-; CHECK-DAG: 66 0f 3a 16 c8 01 pextrd eax,xmm1
-; CHECK-DAG: 66 0f 3a 16 d0 02 pextrd eax,xmm2
-; CHECK-DAG: 66 0f 3a 16 d8 03 pextrd eax,xmm3
-
-define internal i32 @test_pextrb(i32 %c, <16 x i8> %vec1, <16 x i8> %vec2,
- <16 x i8> %vec3, <16 x i8> %vec4) {
-entry:
- switch i32 %c, label %three [i32 0, label %zero
- i32 1, label %one
- i32 2, label %two]
-zero:
- %res0 = extractelement <16 x i8> %vec1, i32 0
- %res0_ext = zext i8 %res0 to i32
- ret i32 %res0_ext
-one:
- %res1 = extractelement <16 x i8> %vec2, i32 6
- %res1_ext = zext i8 %res1 to i32
- ret i32 %res1_ext
-two:
- %res2 = extractelement <16 x i8> %vec3, i32 12
- %res2_ext = zext i8 %res2 to i32
- ret i32 %res2_ext
-three:
- %res3 = extractelement <16 x i8> %vec4, i32 15
- %res3_ext = zext i8 %res3 to i32
- ret i32 %res3_ext
-}
-; CHECK-LABEL: test_pextrb
-; CHECK-DAG: 66 0f 3a 14 c0 00 pextrb eax,xmm0
-; CHECK-DAG: 66 0f 3a 14 c8 06 pextrb eax,xmm1
-; CHECK-DAG: 66 0f 3a 14 d0 0c pextrb eax,xmm2
-; CHECK-DAG: 66 0f 3a 14 d8 0f pextrb eax,xmm3
-
-define internal i32 @test_pextrw(i32 %c, <8 x i16> %vec1, <8 x i16> %vec2,
- <8 x i16> %vec3, <8 x i16> %vec4) {
-entry:
- switch i32 %c, label %three [i32 0, label %zero
- i32 1, label %one
- i32 2, label %two]
-zero:
- %res0 = extractelement <8 x i16> %vec1, i32 0
- %res0_ext = zext i16 %res0 to i32
- ret i32 %res0_ext
-one:
- %res1 = extractelement <8 x i16> %vec2, i32 2
- %res1_ext = zext i16 %res1 to i32
- ret i32 %res1_ext
-two:
- %res2 = extractelement <8 x i16> %vec3, i32 5
- %res2_ext = zext i16 %res2 to i32
- ret i32 %res2_ext
-three:
- %res3 = extractelement <8 x i16> %vec4, i32 7
- %res3_ext = zext i16 %res3 to i32
- ret i32 %res3_ext
-}
-; CHECK-LABEL: test_pextrw
-; CHECK-DAG: 66 0f c5 c0 00 pextrw eax,xmm0
-; CHECK-DAG: 66 0f c5 c1 02 pextrw eax,xmm1
-; CHECK-DAG: 66 0f c5 c2 05 pextrw eax,xmm2
-; CHECK-DAG: 66 0f c5 c3 07 pextrw eax,xmm3
diff --git a/third_party/subzero/tests_lit/assembler/x86/sandboxing.ll b/third_party/subzero/tests_lit/assembler/x86/sandboxing.ll
deleted file mode 100644
index 97a44d1..0000000
--- a/third_party/subzero/tests_lit/assembler/x86/sandboxing.ll
+++ /dev/null
@@ -1,332 +0,0 @@
-; Tests basics and corner cases of x86-32 sandboxing, using -Om1 in
-; the hope that the output will remain stable. When packing bundles,
-; we try to limit to a few instructions with well known sizes and
-; minimal use of registers and stack slots in the lowering sequence.
-
-; XFAIL: filtype=asm
-; RUN: %p2i -i %s --sandbox --filetype=obj --disassemble --args -Om1 \
-; RUN: -allow-externally-defined-symbols \
-; RUN: -ffunction-sections | FileCheck %s
-
-; RUN: %p2i -i %s --sandbox --filetype=obj --disassemble --target=x8664 \
-; RUN: --args -Om1 -allow-externally-defined-symbols \
-; RUN: -ffunction-sections | FileCheck %s --check-prefix X8664
-
-declare void @call_target()
-@global_byte = internal global [1 x i8] zeroinitializer
-@global_short = internal global [2 x i8] zeroinitializer
-@global_int = internal global [4 x i8] zeroinitializer
-
-; A direct call sequence uses the right mask and register-call sequence.
-define internal void @test_direct_call() {
-entry:
- call void @call_target()
- ret void
-}
-; CHECK-LABEL: test_direct_call
-; CHECK: nop
-; CHECK: 1b: {{.*}} call 1c
-; CHECK-NEXT: 20:
-; X8664-LABEL: test_direct_call
-; X8664: push {{.*}} R_X86_64_32S test_direct_call+{{.*}}20
-; X8664: jmp {{.*}} call_target
-
-; An indirect call sequence uses the right mask and register-call sequence.
-define internal void @test_indirect_call(i32 %target) {
-entry:
- %__1 = inttoptr i32 %target to void ()*
- call void %__1()
- ret void
-}
-; CHECK-LABEL: test_indirect_call
-; CHECK: mov [[REG:.*]],DWORD PTR [esp
-; CHECK-NEXT: nop
-; CHECK: 1b: {{.*}} and [[REG]],0xffffffe0
-; CHECK-NEXT: call [[REG]]
-; CHECk-NEXT: 20:
-; X8664-LABEL: test_indirect_call
-; X8664: push {{.*}} R_X86_64_32S test_indirect_call+{{.*}}20
-; X8664: {{.*}} and e[[REG:..]],0xffffffe0
-; X8664: add r[[REG]],r15
-; X8664: jmp r[[REG]]
-
-; A return sequence uses the right pop / mask / jmp sequence.
-define internal void @test_ret() {
-entry:
- ret void
-}
-; CHECK-LABEL: test_ret
-; CHECK: pop ecx
-; CHECK-NEXT: and ecx,0xffffffe0
-; CHECK-NEXT: jmp ecx
-; X8664-LABEL: test_ret
-; X8664: pop rcx
-; X8664: and ecx,0xffffffe0
-; X8664: add rcx,r15
-; X8664: jmp rcx
-
-; A perfectly packed bundle should not have nops at the end.
-define internal void @packed_bundle() {
-entry:
- call void @call_target()
- ; bundle boundary
- %addr_byte = bitcast [1 x i8]* @global_byte to i8*
- %addr_short = bitcast [2 x i8]* @global_short to i16*
- store i8 0, i8* %addr_byte, align 1 ; 7-byte instruction
- store i16 0, i16* %addr_short, align 1 ; 9-byte instruction
- store i8 0, i8* %addr_byte, align 1 ; 7-byte instruction
- store i16 0, i16* %addr_short, align 1 ; 9-byte instruction
- ; bundle boundary
- store i8 0, i8* %addr_byte, align 1 ; 7-byte instruction
- store i16 0, i16* %addr_short, align 1 ; 9-byte instruction
- ret void
-}
-; CHECK-LABEL: packed_bundle
-; CHECK: call
-; CHECK-NEXT: 20: {{.*}} mov BYTE PTR
-; CHECK-NEXT: 27: {{.*}} mov WORD PTR
-; CHECK-NEXT: 30: {{.*}} mov BYTE PTR
-; CHECK-NEXT: 37: {{.*}} mov WORD PTR
-; CHECK-NEXT: 40: {{.*}} mov BYTE PTR
-; CHECK-NEXT: 47: {{.*}} mov WORD PTR
-
-; An imperfectly packed bundle should have one or more nops at the end.
-define internal void @nonpacked_bundle() {
-entry:
- call void @call_target()
- ; bundle boundary
- %addr_short = bitcast [2 x i8]* @global_short to i16*
- store i16 0, i16* %addr_short, align 1 ; 9-byte instruction
- store i16 0, i16* %addr_short, align 1 ; 9-byte instruction
- store i16 0, i16* %addr_short, align 1 ; 9-byte instruction
- ; nop padding
- ; bundle boundary
- store i16 0, i16* %addr_short, align 1 ; 9-byte instruction
- ret void
-}
-; CHECK-LABEL: nonpacked_bundle
-; CHECK: call
-; CHECK-NEXT: 20: {{.*}} mov WORD PTR
-; CHECK-NEXT: 29: {{.*}} mov WORD PTR
-; CHECK-NEXT: 32: {{.*}} mov WORD PTR
-; CHECK-NEXT: 3b: {{.*}} nop
-; CHECK: 40: {{.*}} mov WORD PTR
-
-; A zero-byte instruction (e.g. local label definition) at a bundle
-; boundary should not trigger nop padding.
-define internal void @label_at_boundary(i32 %arg, float %farg1, float %farg2) {
-entry:
- %argi8 = trunc i32 %arg to i8
- call void @call_target()
- ; bundle boundary
- %addr_short = bitcast [2 x i8]* @global_short to i16*
- %addr_int = bitcast [4 x i8]* @global_int to i32*
- store i32 0, i32* %addr_int, align 1 ; 10-byte instruction
- %blah = select i1 true, i8 %argi8, i8 %argi8 ; 22-byte lowering sequence
- ; label is here
- store i16 0, i16* %addr_short, align 1 ; 9-byte instruction
- ret void
-}
-; CHECK-LABEL: label_at_boundary
-; CHECK: call
-; We rely on a particular 7-instruction 22-byte Om1 lowering sequence
-; for select.
-; CHECK-NEXT: 20: {{.*}} mov DWORD PTR
-; CHECK-NEXT: 2a: {{.*}} mov {{.*}},0x1
-; CHECK-NEXT: 2c: {{.*}} cmp {{.*}},0x0
-; CHECK-NEXT: 2e: {{.*}} mov {{.*}},BYTE PTR
-; CHECK-NEXT: 32: {{.*}} mov BYTE PTR
-; CHECK-NEXT: 36: {{.*}} jne 40
-; CHECK-NEXT: 38: {{.*}} mov {{.*}},BYTE PTR
-; CHECK-NEXT: 3c: {{.*}} mov BYTE PTR
-; CHECK-NEXT: 40: {{.*}} mov WORD PTR
-
-; Bundle lock without padding.
-define internal void @bundle_lock_without_padding() {
-entry:
- %addr_short = bitcast [2 x i8]* @global_short to i16*
- store i16 0, i16* %addr_short, align 1 ; 9-byte instruction
- ret void
-}
-; CHECK-LABEL: bundle_lock_without_padding
-; CHECK: mov WORD PTR
-; CHECK-NEXT: pop ecx
-; CHECK-NEXT: and ecx,0xffffffe0
-; CHECK-NEXT: jmp ecx
-
-; Bundle lock with padding.
-define internal void @bundle_lock_with_padding() {
-entry:
- call void @call_target()
- ; bundle boundary
- %addr_byte = bitcast [1 x i8]* @global_byte to i8*
- %addr_short = bitcast [2 x i8]* @global_short to i16*
- store i8 0, i8* %addr_byte, align 1 ; 7-byte instruction
- store i16 0, i16* %addr_short, align 1 ; 9-byte instruction
- store i16 0, i16* %addr_short, align 1 ; 9-byte instruction
- ret void
- ; 3 bytes to restore stack pointer
- ; 1 byte to pop ecx
- ; bundle_lock
- ; 3 bytes to mask ecx
- ; This is now 32 bytes from the beginning of the bundle, so
- ; a 3-byte nop will need to be emitted before the bundle_lock.
- ; 2 bytes to jump to ecx
- ; bundle_unlock
-}
-; CHECK-LABEL: bundle_lock_with_padding
-; CHECK: call
-; CHECK-NEXT: 20: {{.*}} mov BYTE PTR
-; CHECK-NEXT: 27: {{.*}} mov WORD PTR
-; CHECK-NEXT: 30: {{.*}} mov WORD PTR
-; CHECK-NEXT: 39: {{.*}} add esp,
-; CHECK-NEXT: 3c: {{.*}} pop ecx
-; CHECK-NEXT: 3d: {{.*}} nop
-; CHECK-NEXT: 40: {{.*}} and ecx,0xffffffe0
-; CHECK-NEXT: 43: {{.*}} jmp ecx
-
-; Bundle lock align_to_end without any padding.
-define internal void @bundle_lock_align_to_end_padding_0() {
-entry:
- call void @call_target()
- ; bundle boundary
- %addr_short = bitcast [2 x i8]* @global_short to i16*
- store i16 0, i16* %addr_short, align 1 ; 9-byte instruction
- store i16 0, i16* %addr_short, align 1 ; 9-byte instruction
- store i16 0, i16* %addr_short, align 1 ; 9-byte instruction
- call void @call_target() ; 5-byte instruction
- ret void
-}
-; CHECK-LABEL: bundle_lock_align_to_end_padding_0
-; CHECK: call
-; CHECK-NEXT: 20: {{.*}} mov WORD PTR
-; CHECK-NEXT: 29: {{.*}} mov WORD PTR
-; CHECK-NEXT: 32: {{.*}} mov WORD PTR
-; CHECK-NEXT: 3b: {{.*}} call
-
-; Bundle lock align_to_end with one bunch of padding.
-define internal void @bundle_lock_align_to_end_padding_1() {
-entry:
- call void @call_target()
- ; bundle boundary
- %addr_byte = bitcast [1 x i8]* @global_byte to i8*
- store i8 0, i8* %addr_byte, align 1 ; 7-byte instruction
- store i8 0, i8* %addr_byte, align 1 ; 7-byte instruction
- store i8 0, i8* %addr_byte, align 1 ; 7-byte instruction
- call void @call_target() ; 5-byte instruction
- ret void
-}
-; CHECK-LABEL: bundle_lock_align_to_end_padding_1
-; CHECK: call
-; CHECK-NEXT: 20: {{.*}} mov BYTE PTR
-; CHECK-NEXT: 27: {{.*}} mov BYTE PTR
-; CHECK-NEXT: 2e: {{.*}} mov BYTE PTR
-; CHECK-NEXT: 35: {{.*}} nop
-; CHECK: 3b: {{.*}} call
-
-; Bundle lock align_to_end with two bunches of padding.
-define internal void @bundle_lock_align_to_end_padding_2(i32 %target) {
-entry:
- call void @call_target()
- ; bundle boundary
- %addr_byte = bitcast [1 x i8]* @global_byte to i8*
- %addr_short = bitcast [2 x i8]* @global_short to i16*
- %__1 = inttoptr i32 %target to void ()*
- store i8 0, i8* %addr_byte, align 1 ; 7-byte instruction
- store i16 0, i16* %addr_short, align 1 ; 9-byte instruction
- store i16 0, i16* %addr_short, align 1 ; 9-byte instruction
- call void %__1()
- ; 4 bytes to load %target into a register
- ; bundle_lock align_to_end
- ; 3 bytes to mask the register
- ; This is now 32 bytes from the beginning of the bundle, so
- ; a 3-byte nop will need to be emitted before the bundle_lock,
- ; followed by a 27-byte nop before the mask/jump.
- ; 2 bytes to jump to the register
- ; bundle_unlock
- ret void
-}
-; CHECK-LABEL: bundle_lock_align_to_end_padding_2
-; CHECK: call
-; CHECK-NEXT: 20: {{.*}} mov BYTE PTR
-; CHECK-NEXT: 27: {{.*}} mov WORD PTR
-; CHECK-NEXT: 30: {{.*}} mov WORD PTR
-; CHECK-NEXT: 39: {{.*}} mov [[REG:.*]],DWORD PTR [esp
-; CHECK-NEXT: 3d: {{.*}} nop
-; CHECK: 40: {{.*}} nop
-; CHECK: 5b: {{.*}} and [[REG]],0xffffffe0
-; CHECK-NEXT: 5e: {{.*}} call [[REG]]
-
-; Tests the pad_to_end bundle alignment with no padding bytes needed.
-define internal void @bundle_lock_pad_to_end_padding_0(i32 %arg0, i32 %arg1,
- i32 %arg3, i32 %arg4,
- i32 %arg5, i32 %arg6) {
- call void @call_target()
- ; bundle boundary
- %x = add i32 %arg5, %arg6 ; 12 bytes
- %y = trunc i32 %x to i16 ; 10 bytes
- call void @call_target() ; 10 bytes
- ; bundle boundary
- ret void
-}
-; X8664: 56: {{.*}} push {{.*}} R_X86_64_32S bundle_lock_pad_to_end_padding_0+{{.*}}60
-; X8664: 5b: {{.*}} jmp {{.*}} call_target
-; X8664: 60: {{.*}} add
-
-; Tests the pad_to_end bundle alignment with 11 padding bytes needed, and some
-; instructions before the call.
-define internal void @bundle_lock_pad_to_end_padding_11(i32 %arg0, i32 %arg1,
- i32 %arg3, i32 %arg4,
- i32 %arg5, i32 %arg6) {
- call void @call_target()
- ; bundle boundary
- %x = add i32 %arg5, %arg6 ; 11 bytes
- call void @call_target() ; 10 bytes
- ; 11 bytes of nop
- ; bundle boundary
- ret void
-}
-; X8664: 4b: {{.*}} push {{.*}} R_X86_64_32S bundle_lock_pad_to_end_padding_11+{{.*}}60
-; X8664: 50: {{.*}} jmp {{.*}} call_target
-; X8664: 55: {{.*}} nop
-; X8664: 5d: {{.*}} nop
-; X8664: 60: {{.*}} add
-
-; Tests the pad_to_end bundle alignment with 22 padding bytes needed, and no
-; instructions before the call.
-define internal void @bundle_lock_pad_to_end_padding_22(i32 %arg0, i32 %arg1,
- i32 %arg3, i32 %arg4,
- i32 %arg5, i32 %arg6) {
- call void @call_target()
- ; bundle boundary
- call void @call_target() ; 10 bytes
- ; 22 bytes of nop
- ; bundle boundary
- ret void
-}
-; X8664: 40: {{.*}} push {{.*}} R_X86_64_32S bundle_lock_pad_to_end_padding_22+{{.*}}60
-; X8664: 45: {{.*}} jmp {{.*}} call_target
-; X8664: 4a: {{.*}} nop
-; X8664: 52: {{.*}} nop
-; X8664: 5a: {{.*}} nop
-; X8664: 60: {{.*}} add
-
-; Stack adjustment state during an argument push sequence gets
-; properly checkpointed and restored during the two passes, as
-; observed by the stack adjustment for accessing stack-allocated
-; variables.
-define internal void @checkpoint_restore_stack_adjustment(i32 %arg) {
-entry:
- call void @call_target()
- ; bundle boundary
- call void @checkpoint_restore_stack_adjustment(i32 %arg)
- ret void
-}
-; CHECK-LABEL: checkpoint_restore_stack_adjustment
-; CHECK: sub esp,0x1c
-; CHECK: call
-; The address of %arg should be [esp+0x20], not [esp+0x30].
-; CHECK-NEXT: mov [[REG:.*]],DWORD PTR [esp+0x20]
-; CHECK-NEXT: mov DWORD PTR [esp],[[REG]]
-; CHECK: call
-; CHECK: add esp,0x1c
diff --git a/third_party/subzero/tests_lit/lit.cfg b/third_party/subzero/tests_lit/lit.cfg
deleted file mode 100644
index 1b94bd3..0000000
--- a/third_party/subzero/tests_lit/lit.cfg
+++ /dev/null
@@ -1,143 +0,0 @@
-# -*- Python -*-
-# Taken from utils/lit/tests in the LLVM tree and hacked together to support
-# our tests.
-#
-# Note: This configuration has simple commands to run Subzero's translator.
-# They have the form %X2i (i.e. %p2i, %l2i, and %lc2i) where X is defined
-# as follows:
-#
-# p : Run Subzero's translator, building ICE from PNaCl bitcode directly.
-# l : Run Subzero's translator, converting the .ll file to a PNaCl bitcode
-# file, reading in the bitcode file and generating LLVM IR, and
-# then convert LLVM IR to ICE IR.
-# lc : Run Subzero's translator, directly parsing the .ll file into LLVM IR,
-# and then convert it to ICE IR.
-#
-# These commands can be used in RUN lines by FileCheck. If the Subzero
-# build being tested lacks any required attributes (e.g., the ability
-# to parse .ll files), the command will simply return successfully,
-# generating no output. This allows translation tests to be able to
-# conditionally test the translator, based on the translator built.
-#
-# This conditional handling of translation introduces potential problems
-# when the output is piped to another command on a RUN line. Executables
-# like FileCheck expect non-empty input.
-#
-# To handle the problem that the pipe is conditional, any command that
-# doesn't accept empty input should be prefixed by a corresponding
-# %ifX (i.e. %p2i, %ifl, or %ifpc). Note: %p2i should always work, and
-# hence %ifp is not necessary (i.e. it is a nop).
-#
-# If you need to check other build attributes (other than the
-# existence of %l2i and %lc2i), you can use the %if command (which is
-# a short hand for using pydir/ifatts.py).
-
-import os
-import re
-import sys
-
-import lit.formats
-
-sys.path.insert(0, 'pydir')
-from utils import FindBaseNaCl, shellcmd
-
-# name: The name of this test suite.
-config.name = 'subzero'
-
-# testFormat: The test format to use to interpret tests.
-config.test_format = lit.formats.ShTest()
-
-# suffixes: A list of file extensions to treat as test files.
-config.suffixes = ['.ll', '.test']
-
-# test_source_root: The root path where tests are located.
-config.test_source_root = os.path.dirname(__file__)
-config.test_exec_root = config.test_source_root
-config.target_triple = '(unused)'
-
-src_root = os.path.join(FindBaseNaCl(), 'toolchain_build/src/subzero')
-bin_root = src_root
-config.substitutions.append(('%{src_root}', src_root))
-config.substitutions.append(('%{python}', sys.executable))
-
-pydir = os.path.join(bin_root, 'pydir')
-
-# Finding PNaCl binary tools. Tools used in the tests must be listed in the
-# pnaclbintools list.
-pnaclbinpath = os.path.abspath(os.environ.get('PNACL_BIN_PATH'))
-
-# Define the location of the pnacl-sz tool.
-pnacl_sz_tool = os.path.join(bin_root, 'pnacl-sz')
-pnacl_sz_atts = shellcmd(' '.join([pnacl_sz_tool, '--build-atts']),
- echo=False).split()
-
-# Add build attributes of pnacl-sz tool to the set of available features.
-config.available_features.update(pnacl_sz_atts)
-
-def if_cond_flag(Value):
- return '--cond=true' if Value else '--cond=false'
-
-# shell conditional commands.
-if_atts = [os.path.join(pydir, 'if.py')]
-if_atts_cmd = if_atts + ['--have=' + att for att in pnacl_sz_atts]
-ifl2i_atts_cmd = if_atts + [if_cond_flag('allow_llvm_ir' in pnacl_sz_atts),
- '--command']
-iflc2i_atts_cmd = if_atts + [if_cond_flag('allow_llvm_ir_as_input'
- in pnacl_sz_atts), '--command']
-
-# Base command for running pnacl-sz
-pnacl_sz_cmd = [os.path.join(pydir, 'run-pnacl-sz.py'),
- '--echo-cmd',
- '--pnacl-sz', pnacl_sz_tool,
- '--pnacl-bin-path', pnaclbinpath]
-if 'FORCEASM' in lit_config.params:
- pnacl_sz_cmd += ['--forceasm']
-
-# Run commands only if corresponding build attributes apply, including
-# for each compiler setup.
-config.substitutions.append(('%ifp', ' '))
-config.substitutions.append(('%iflc', ' '.join(iflc2i_atts_cmd)))
-config.substitutions.append(('%ifl', ' '.join(ifl2i_atts_cmd)))
-config.substitutions.append(('%if', ' '.join(if_atts_cmd)))
-
-# Translate LLVM source for each compiler setup.
-config.substitutions.append(('%p2i', ' '.join(pnacl_sz_cmd)))
-config.substitutions.append(('%l2i', ' '.join(ifl2i_atts_cmd + pnacl_sz_cmd
- + ['--llvm'])))
-config.substitutions.append(('%lc2i', ' '.join(iflc2i_atts_cmd + pnacl_sz_cmd
- + ['--llvm-source'])))
-
-config.substitutions.append(('%pnacl_sz', pnacl_sz_tool))
-
-pnaclbintools = [r'\b' + x + r'\b' for x in
- ['FileCheck',
- 'llvm-as',
- 'llvm-mc',
- 'llvm-readobj',
- 'not',
- 'pnacl-bcdis',
- 'pnacl-bcfuzz',
- 'pnacl-freeze']]
-
-for tool in pnaclbintools:
- # The re.sub() line is adapted from one of LLVM's lit.cfg files.
- # Extract the tool name from the pattern. This relies on the tool
- # name being surrounded by \b word match operators. If the
- # pattern starts with "| ", include it in the string to be
- # substituted.
- substitution = re.sub(r"^(\\)?((\| )?)\W+b([0-9A-Za-z-_]+)\\b\W*$",
- r"\2" + pnaclbinpath + "/" + r"\4",
- tool)
- config.substitutions.append((tool, substitution))
-
-# Add a feature to detect the Python version.
-config.available_features.add("python%d.%d" % (sys.version_info[0],
- sys.version_info[1]))
-
-# Debugging output
-def dbg(s):
- print '[DBG] %s' % s
-
-dbg('bin_root = %s' % bin_root)
-dbg('pnaclbinpath = %s' % pnaclbinpath)
-dbg("Build attributes = %s" % pnacl_sz_atts)
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/64bit.pnacl.ll b/third_party/subzero/tests_lit/llvm2ice_tests/64bit.pnacl.ll
deleted file mode 100644
index 55f6832..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/64bit.pnacl.ll
+++ /dev/null
@@ -1,2544 +0,0 @@
-; This tries to be a comprehensive test of i64 operations, in
-; particular the patterns for lowering i64 operations into constituent
-; i32 operations on x86-32.
-
-; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
-; RUN: --target x8632 -i %s --args -O2 -allow-externally-defined-symbols \
-; RUN: | %if --need=target_X8632 --command FileCheck %s
-
-; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
-; RUN: --target x8632 -i %s --args -Om1 -allow-externally-defined-symbols \
-; RUN: | %if --need=target_X8632 --command FileCheck --check-prefix=OPTM1 %s
-
-; RUN: %if --need=target_ARM32 \
-; RUN: --command %p2i --filetype=obj \
-; RUN: --disassemble --target arm32 -i %s --args -O2 \
-; RUN: -allow-externally-defined-symbols \
-; RUN: | %if --need=target_ARM32 \
-; RUN: --command FileCheck --check-prefix ARM32 --check-prefix ARM32-O2 %s
-; RUN: %if --need=target_ARM32 \
-; RUN: --command %p2i --filetype=obj --disassemble --target arm32 \
-; RUN: -i %s --args -Om1 \
-; RUN: -allow-externally-defined-symbols \
-; RUN: | %if --need=target_ARM32 \
-; RUN: --command FileCheck --check-prefix ARM32 --check-prefix ARM32-OM1 %s
-
-; TODO: Switch to --filetype=obj when possible.
-; RUN: %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command %p2i --filetype=asm --assemble \
-; RUN: --disassemble --target mips32 -i %s --args -O2 \
-; RUN: -allow-externally-defined-symbols \
-; RUN: | %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command FileCheck --check-prefix MIPS32 --check-prefix MIPS32-O2 %s
-
-; RUN: %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command %p2i --filetype=asm --assemble \
-; RUN: --disassemble --target mips32 -i %s --args -Om1 \
-; RUN: -allow-externally-defined-symbols \
-; RUN: | %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command FileCheck --check-prefix MIPS32 --check-prefix MIPS32-OM1 %s
-
-@__init_array_start = internal constant [0 x i8] zeroinitializer, align 4
-@__fini_array_start = internal constant [0 x i8] zeroinitializer, align 4
-@__tls_template_start = internal constant [0 x i8] zeroinitializer, align 8
-@__tls_template_alignment = internal constant [4 x i8] c"\01\00\00\00", align 4
-
-define internal i32 @ignore64BitArg(i64 %a, i32 %b, i64 %c) {
-entry:
- ret i32 %b
-}
-
-; MIPS32-LABEL: ignore64BitArg
-; MIPS32-O2: move v0,a2
-; MIPS32-OM1: sw a2,[[MEM:.*]]
-; MIPS32-OM1: lw v0,[[MEM]]
-
-define internal i32 @pass64BitArg(i64 %a, i64 %b, i64 %c, i64 %d, i64 %e, i64 %f) {
-entry:
- %call = call i32 @ignore64BitArgNoInline(i64 %a, i32 123, i64 %b)
- %call1 = call i32 @ignore64BitArgNoInline(i64 %c, i32 123, i64 %d)
- %call2 = call i32 @ignore64BitArgNoInline(i64 %e, i32 123, i64 %f)
- %add = add i32 %call1, %call
- %add3 = add i32 %add, %call2
- ret i32 %add3
-}
-; CHECK-LABEL: pass64BitArg
-; CHECK: sub esp
-; CHECK: mov DWORD PTR [esp+0x4]
-; CHECK: mov DWORD PTR [esp]
-; CHECK: mov DWORD PTR [esp+0x8],0x7b
-; CHECK: mov DWORD PTR [esp+0x10]
-; CHECK: mov DWORD PTR [esp+0xc]
-; CHECK: call {{.*}} R_{{.*}} ignore64BitArgNoInline
-; CHECK: mov DWORD PTR [esp+0x4]
-; CHECK: mov DWORD PTR [esp]
-; CHECK: mov DWORD PTR [esp+0x8],0x7b
-; CHECK: mov DWORD PTR [esp+0x10]
-; CHECK: mov DWORD PTR [esp+0xc]
-; CHECK: call {{.*}} R_{{.*}} ignore64BitArgNoInline
-; CHECK: mov DWORD PTR [esp+0x4]
-; CHECK: mov DWORD PTR [esp]
-; CHECK: mov DWORD PTR [esp+0x8],0x7b
-; CHECK: mov DWORD PTR [esp+0x10]
-; CHECK: mov DWORD PTR [esp+0xc]
-; CHECK: call {{.*}} R_{{.*}} ignore64BitArgNoInline
-;
-; OPTM1-LABEL: pass64BitArg
-; OPTM1: sub esp
-; OPTM1: mov DWORD PTR [esp+0x4]
-; OPTM1: mov DWORD PTR [esp]
-; OPTM1: mov DWORD PTR [esp+0x8],0x7b
-; OPTM1: mov DWORD PTR [esp+0x10]
-; OPTM1: mov DWORD PTR [esp+0xc]
-; OPTM1: call {{.*}} R_{{.*}} ignore64BitArgNoInline
-; OPTM1: mov DWORD PTR [esp+0x4]
-; OPTM1: mov DWORD PTR [esp]
-; OPTM1: mov DWORD PTR [esp+0x8],0x7b
-; OPTM1: mov DWORD PTR [esp+0x10]
-; OPTM1: mov DWORD PTR [esp+0xc]
-; OPTM1: call {{.*}} R_{{.*}} ignore64BitArgNoInline
-; OPTM1: mov DWORD PTR [esp+0x4]
-; OPTM1: mov DWORD PTR [esp]
-; OPTM1: mov DWORD PTR [esp+0x8],0x7b
-; OPTM1: mov DWORD PTR [esp+0x10]
-; OPTM1: mov DWORD PTR [esp+0xc]
-; OPTM1: call {{.*}} R_{{.*}} ignore64BitArgNoInline
-
-; ARM32-LABEL: pass64BitArg
-; ARM32: str {{.*}}, [sp]
-; ARM32: mov r2, #123
-; ARM32: bl {{.*}} ignore64BitArgNoInline
-; ARM32: str {{.*}}, [sp]
-; ARM32: {{mov|ldr}} r0
-; ARM32: {{mov|ldr}} r1
-; ARM32: mov r2, #123
-; ARM32: bl {{.*}} ignore64BitArgNoInline
-; ARM32: str {{.*}}, [sp]
-; ARM32: {{mov|ldr}} r0
-; ARM32: {{mov|ldr}} r1
-; ARM32: mov r2, #123
-; ARM32: bl {{.*}} ignore64BitArgNoInline
-
-; MIPS32-LABEL: pass64BitArg
-; MIPS32-O2: sw a3,{{.*}}(sp)
-; MIPS32-O2: sw a2,{{.*}}(sp)
-; MIPS32-O2: li a2,123
-; MIPS32-O2: jal {{.*}} ignore64BitArgNoInline
-; MIPS32-O2: nop
-; MIPS32-O2: move s0,v0
-; MIPS32-O2: sw s3,{{.*}}(sp)
-; MIPS32-O2: sw s2,{{.*}}(sp)
-; MIPS32-O2: lw a0,{{.*}}(sp)
-; MIPS32-O2: move a1,s1
-; MIPS32-O2: li a2,123
-; MIPS32-O2: jal {{.*}} ignore64BitArgNoInline
-; MIPS32-O2: nop
-; MIPS32-O2: move s1,v0
-; MIPS32-O2: sw s7,{{.*}}(sp)
-; MIPS32-O2: sw s6,{{.*}}(sp)
-; MIPS32-O2: move a0,s4
-; MIPS32-O2: move a1,s5
-; MIPS32-O2: li a2,123
-; MIPS32-O2: jal {{.*}} ignore64BitArgNoInline
-; MIPS32-O2: nop
-
-
-declare i32 @ignore64BitArgNoInline(i64, i32, i64)
-
-define internal i32 @pass64BitConstArg(i64 %a, i64 %b) {
-entry:
- %call = call i32 @ignore64BitArgNoInline(i64 %b, i32 123, i64 -2401053092306725256)
- ret i32 %call
-}
-; CHECK-LABEL: pass64BitConstArg
-; CHECK: sub esp
-; CHECK: mov DWORD PTR [esp+0x4]
-; CHECK-NEXT: mov DWORD PTR [esp]
-; CHECK-NEXT: mov DWORD PTR [esp+0x8],0x7b
-; Bundle padding might be added (so not using -NEXT).
-; CHECK: mov DWORD PTR [esp+0x10],0xdeadbeef
-; CHECK-NEXT: mov DWORD PTR [esp+0xc],0x12345678
-; Bundle padding will push the call down.
-; CHECK-NOT: mov
-; CHECK: call {{.*}} R_{{.*}} ignore64BitArgNoInline
-;
-; OPTM1-LABEL: pass64BitConstArg
-; OPTM1: sub esp
-; OPTM1: mov DWORD PTR [esp+0x4]
-; OPTM1: mov DWORD PTR [esp]
-; OPTM1-NEXT: mov DWORD PTR [esp+0x8],0x7b
-; Bundle padding might be added (so not using -NEXT).
-; OPTM1: mov DWORD PTR [esp+0x10],0xdeadbeef
-; OPTM1-NEXT: mov DWORD PTR [esp+0xc],0x12345678
-; OPTM1-NOT: mov
-; OPTM1: call {{.*}} R_{{.*}} ignore64BitArgNoInline
-
-; ARM32-LABEL: pass64BitConstArg
-; ARM32: movw [[REG1:r.*]], {{.*}} ; 0xbeef
-; ARM32: movt [[REG1]], {{.*}} ; 0xdead
-; ARM32: movw [[REG2:r.*]], {{.*}} ; 0x5678
-; ARM32: movt [[REG2]], {{.*}} ; 0x1234
-; ARM32: str [[REG1]], [sp, #4]
-; ARM32: str [[REG2]], [sp]
-; ARM32: {{mov|ldr}} r0
-; ARM32: {{mov|ldr}} r1
-; ARM32: mov r2, #123
-; ARM32: bl {{.*}} ignore64BitArgNoInline
-
-; MIPS32-LABEL: pass64BitConstArg
-; MIPS32-O2: lui [[REG:.*]],0xdead
-; MIPS32-O2: ori [[REG1:.*]],[[REG]],0xbeef
-; MIPS32-O2: lui [[REG:.*]],0x1234
-; MIPS32-O2: ori [[REG2:.*]],[[REG]],0x5678
-; MIPS32-O2: sw [[REG1]],{{.*}}(sp)
-; MIPS32-O2: sw [[REG2]],{{.*}}(sp)
-; MIPS32-O2: move a0,a2
-; MIPS32-O2: move a1,a3
-; MIPS32-O2: li a2,123
-; MIPS32-O2: jal {{.*}} ignore64BitArgNoInline
-
-define internal i32 @pass64BitUndefArg() {
-entry:
- %call = call i32 @ignore64BitArgNoInline(i64 0, i32 123, i64 undef)
- ret i32 %call
-}
-; CHECK-LABEL: pass64BitUndefArg
-; CHECK: sub esp
-; CHECK: mov DWORD PTR{{.*}},0x7b
-; CHECK: mov DWORD PTR{{.*}},0x0
-; CHECK: call {{.*}} R_{{.*}} ignore64BitArgNoInline
-; OPTM1-LABEL: pass64BitUndefArg
-; OPTM1: sub esp
-; OPTM1: mov DWORD PTR{{.*}},0x7b
-; OPTM1: mov DWORD PTR{{.*}},0x0
-; OPTM1: call {{.*}} R_{{.*}} ignore64BitArgNoInline
-; ARM32-LABEL: pass64BitUndefArg
-; ARM32: sub sp
-; ARM32: mov {{.*}}, #0
-; ARM32: str
-; ARM32: mov {{.*}}, #123
-; ARM32: bl {{.*}} ignore64BitArgNoInline
-
-; MIPS32-LABEL: pass64BitUndefArg
-; MIPS32: jr ra
-
-define internal i64 @return64BitArg(i64 %padding, i64 %a) {
-entry:
- ret i64 %a
-}
-; CHECK-LABEL: return64BitArg
-; CHECK: mov {{.*}},DWORD PTR [esp+0xc]
-; CHECK: mov {{.*}},DWORD PTR [esp+0x10]
-;
-; OPTM1-LABEL: return64BitArg
-; OPTM1: mov {{.*}},DWORD PTR [esp+0xc]
-; OPTM1: mov {{.*}},DWORD PTR [esp+0x10]
-
-; ARM32-LABEL: return64BitArg
-; ARM32: mov {{.*}}, r2
-; ARM32: mov {{.*}}, r3
-; ARM32: bx lr
-
-; MIPS32-LABEL; return64BitArg
-; MIPS32-O2: move v0,a2
-; MIPS32-O2: move v1,a3
-; MIPS32-OM1: move [[T1:.*]],a2
-; MIPS32-OM1: sw [[T1]],[[MEM1:.*]]
-; MIPS32-OM1: move [[T2:.*]],a3
-; MIPS32-OM1: sw [[T2]],[[MEM2:.*]]
-; MIPS32-OM1: lw v0,[[MEM1]]
-; MIPS32-OM1: lw v1,[[MEM2]]
-; MIPS32: jr ra
-
-define internal i64 @return64BitConst() {
-entry:
- ret i64 -2401053092306725256
-}
-; CHECK-LABEL: return64BitConst
-; CHECK: mov eax,0x12345678
-; CHECK: mov edx,0xdeadbeef
-;
-; OPTM1-LABEL: return64BitConst
-; OPTM1: mov eax,0x12345678
-; OPTM1: mov edx,0xdeadbeef
-
-; ARM32-LABEL: return64BitConst
-; ARM32: movw r0, #22136 ; 0x5678
-; ARM32: movt r0, #4660 ; 0x1234
-; ARM32: movw r1, #48879 ; 0xbeef
-; ARM32: movt r1, #57005 ; 0xdead
-
-; MIPS32-LABEL: return64BitConst
-; MIPS32: lui v0,0x1234
-; MIPS32: ori v0,v0,0x5678
-; MIPS32: lui v1,0xdead
-; MIPS32: ori v1,v1,0xbeef
-; MIPS32: jr ra
-
-define internal i64 @add64BitSigned(i64 %a, i64 %b) {
-entry:
- %add = add i64 %b, %a
- ret i64 %add
-}
-; CHECK-LABEL: add64BitSigned
-; CHECK: add
-; CHECK: adc
-;
-; OPTM1-LABEL: add64BitSigned
-; OPTM1: add
-; OPTM1: adc
-
-; ARM32-LABEL: add64BitSigned
-; ARM32: adds
-; ARM32: adc
-
-; MIPS32-LABEL: add64BitSigned
-; MIPS32: addu
-; MIPS32: sltu
-; MIPS32: addu
-; MIPS32: addu
-
-define internal i64 @add64BitUnsigned(i64 %a, i64 %b) {
-entry:
- %add = add i64 %b, %a
- ret i64 %add
-}
-; CHECK-LABEL: add64BitUnsigned
-; CHECK: add
-; CHECK: adc
-;
-; OPTM1-LABEL: add64BitUnsigned
-; OPTM1: add
-; OPTM1: adc
-
-; ARM32-LABEL: add64BitUnsigned
-; ARM32: adds
-; ARM32: adc
-
-; MIPS32-LABEL: add64BitUnsigned
-; MIPS32: addu
-; MIPS32: sltu
-; MIPS32: addu
-; MIPS32: addu
-
-define internal i64 @sub64BitSigned(i64 %a, i64 %b) {
-entry:
- %sub = sub i64 %a, %b
- ret i64 %sub
-}
-; CHECK-LABEL: sub64BitSigned
-; CHECK: sub
-; CHECK: sbb
-;
-; OPTM1-LABEL: sub64BitSigned
-; OPTM1: sub
-; OPTM1: sbb
-
-; ARM32-LABEL: sub64BitSigned
-; ARM32: subs
-; ARM32: sbc
-
-; MIPS32-LABEL: sub64BitSigned
-; MIPS32: subu
-; MIPS32: sltu
-; MIPS32: addu
-; MIPS32: subu
-
-define internal i64 @sub64BitUnsigned(i64 %a, i64 %b) {
-entry:
- %sub = sub i64 %a, %b
- ret i64 %sub
-}
-; CHECK-LABEL: sub64BitUnsigned
-; CHECK: sub
-; CHECK: sbb
-;
-; OPTM1-LABEL: sub64BitUnsigned
-; OPTM1: sub
-; OPTM1: sbb
-
-; ARM32-LABEL: sub64BitUnsigned
-; ARM32: subs
-; ARM32: sbc
-
-; MIPS32-LABEL: sub64BitUnsigned
-; MIPS32: subu
-; MIPS32: sltu
-; MIPS32: addu
-; MIPS32: subu
-
-define internal i64 @mul64BitSigned(i64 %a, i64 %b) {
-entry:
- %mul = mul i64 %b, %a
- ret i64 %mul
-}
-; CHECK-LABEL: mul64BitSigned
-; CHECK: imul
-; CHECK: mul
-; CHECK: add
-; CHECK: imul
-; CHECK: add
-;
-; OPTM1-LABEL: mul64BitSigned
-; OPTM1: imul
-; OPTM1: mul
-; OPTM1: add
-; OPTM1: imul
-; OPTM1: add
-
-; ARM32-LABEL: mul64BitSigned
-; ARM32: mul
-; ARM32: mla
-; ARM32: umull
-; ARM32: add
-
-; MIPS32-LABEL: mul64BitSigned
-; MIPS32: multu
-; MIPS32: mflo
-; MIPS32: mfhi
-; MIPS32: mul
-; MIPS32: mul
-; MIPS32: addu
-; MIPS32: addu
-
-define internal i64 @mul64BitUnsigned(i64 %a, i64 %b) {
-entry:
- %mul = mul i64 %b, %a
- ret i64 %mul
-}
-; CHECK-LABEL: mul64BitUnsigned
-; CHECK: imul
-; CHECK: mul
-; CHECK: add
-; CHECK: imul
-; CHECK: add
-;
-; OPTM1-LABEL: mul64BitUnsigned
-; OPTM1: imul
-; OPTM1: mul
-; OPTM1: add
-; OPTM1: imul
-; OPTM1: add
-
-; ARM32-LABEL: mul64BitUnsigned
-; ARM32: mul
-; ARM32: mla
-; ARM32: umull
-; ARM32: add
-
-; MIPS32-LABEL: mul64BitUnsigned
-; MIPS32: multu
-; MIPS32: mflo
-; MIPS32: mfhi
-; MIPS32: mul
-; MIPS32: mul
-; MIPS32: addu
-; MIPS32: addu
-
-define internal i64 @div64BitSigned(i64 %a, i64 %b) {
-entry:
- %div = sdiv i64 %a, %b
- ret i64 %div
-}
-; CHECK-LABEL: div64BitSigned
-; CHECK: call {{.*}} R_{{.*}} __divdi3
-
-; OPTM1-LABEL: div64BitSigned
-; OPTM1: call {{.*}} R_{{.*}} __divdi3
-;
-; ARM32-LABEL: div64BitSigned
-; ARM32: orrs {{r.*}}, {{r.*}}
-; ARM32: bne
-; ARM32: bl {{.*}} __divdi3
-
-; MIPS32-LABEL: div64BitSigned
-; MIPS32: jal {{.*}} __divdi3
-
-define internal i64 @div64BitSignedConst(i64 %a) {
-entry:
- %div = sdiv i64 %a, 12345678901234
- ret i64 %div
-}
-; CHECK-LABEL: div64BitSignedConst
-; CHECK: mov DWORD PTR [esp+0xc],0xb3a
-; CHECK: mov DWORD PTR [esp+0x8],0x73ce2ff2
-; CHECK: call {{.*}} R_{{.*}} __divdi3
-;
-; OPTM1-LABEL: div64BitSignedConst
-; OPTM1: mov DWORD PTR [esp+0xc],0xb3a
-; OPTM1: mov DWORD PTR [esp+0x8],0x73ce2ff2
-; OPTM1: call {{.*}} R_{{.*}} __divdi3
-;
-; ARM32-LABEL: div64BitSignedConst
-; For a constant, we should be able to optimize-out the divide by zero check.
-; ARM32-NOT: orrs
-; ARM32: movw {{.*}} ; 0x2ff2
-; ARM32: movt {{.*}} ; 0x73ce
-; ARM32: movw {{.*}} ; 0xb3a
-; ARM32: bl {{.*}} __divdi3
-
-; MIPS32-LABEL: div64BitSignedConst
-; MIPS32: jal {{.*}} __divdi3
-
-define internal i64 @div64BitUnsigned(i64 %a, i64 %b) {
-entry:
- %div = udiv i64 %a, %b
- ret i64 %div
-}
-; CHECK-LABEL: div64BitUnsigned
-; CHECK: call {{.*}} R_{{.*}} __udivdi3
-;
-; OPTM1-LABEL: div64BitUnsigned
-; OPTM1: call {{.*}} R_{{.*}} __udivdi3
-;
-; ARM32-LABEL: div64BitUnsigned
-; ARM32: orrs {{r.*}}, {{r.*}}
-; ARM32: bne
-; ARM32: bl {{.*}} __udivdi3
-
-; MIPS32-LABEL: div64BitUnsigned
-; MIPS32: jal {{.*}} __udivdi3
-
-define internal i64 @rem64BitSigned(i64 %a, i64 %b) {
-entry:
- %rem = srem i64 %a, %b
- ret i64 %rem
-}
-; CHECK-LABEL: rem64BitSigned
-; CHECK: call {{.*}} R_{{.*}} __moddi3
-;
-; OPTM1-LABEL: rem64BitSigned
-; OPTM1: call {{.*}} R_{{.*}} __moddi3
-;
-; ARM32-LABEL: rem64BitSigned
-; ARM32: orrs {{r.*}}, {{r.*}}
-; ARM32: bne
-; ARM32: bl {{.*}} __moddi3
-
-; MIPS32-LABEL: rem64BitSigned
-; MIPS32: jal {{.*}} __moddi3
-
-define internal i64 @rem64BitUnsigned(i64 %a, i64 %b) {
-entry:
- %rem = urem i64 %a, %b
- ret i64 %rem
-}
-; CHECK-LABEL: rem64BitUnsigned
-; CHECK: call {{.*}} R_{{.*}} __umoddi3
-;
-; OPTM1-LABEL: rem64BitUnsigned
-; OPTM1: call {{.*}} R_{{.*}} __umoddi3
-;
-; ARM32-LABEL: rem64BitUnsigned
-; ARM32: orrs {{r.*}}, {{r.*}}
-; ARM32: bne
-; ARM32: bl {{.*}} __umoddi3
-
-; MIPS32-LABEL: rem64BitUnsigned
-; MIPS32: jal {{.*}} __umoddi3
-
-define internal i64 @shl64BitSigned(i64 %a, i64 %b) {
-entry:
- %shl = shl i64 %a, %b
- ret i64 %shl
-}
-; CHECK-LABEL: shl64BitSigned
-; CHECK: shld
-; CHECK: shl e
-; CHECK: test {{.*}},0x20
-; CHECK: je
-;
-; OPTM1-LABEL: shl64BitSigned
-; OPTM1: shld
-; OPTM1: shl e
-; OPTM1: test {{.*}},0x20
-; OPTM1: je
-
-; ARM32-LABEL: shl64BitSigned
-; ARM32: rsb [[T0:r[0-9]+]], r2, #32
-; ARM32: lsr [[T1:r[0-9]+]], r0, [[T0]]
-; ARM32: orr [[T2:r[0-9]+]], [[T1]], r1, lsl r2
-; ARM32: sub [[T3:r[0-9]+]], r2, #32
-; ARM32: cmp [[T3]], #0
-; ARM32: lslge [[T2]], r0, [[T3]]
-; ARM32: lsl r{{[0-9]+}}, r0, r2
-
-; MIPS32-LABEL: shl64BitSigned
-; MIPS32: sllv [[T1:.*]],[[A_HI:.*]],[[B_LO:.*]]
-; MIPS32: nor [[T2:.*]],[[B_LO]],zero
-; MIPS32: srl [[T3:.*]],[[A_LO:.*]],0x1
-; MIPS32: srlv [[T4:.*]],[[T3]],[[T2]]
-; MIPS32: or [[T_HI:.*]],[[T1]],[[T4]]
-; MIPS32: sllv [[T_LO:.*]],[[A_LO]],[[B_LO]]
-; MIPS32: move [[T1_LO:.*]],[[T_LO]]
-; MIPS32: andi [[T5:.*]],[[B_LO]],0x20
-; MIPS32: movn [[T_HI]],[[T_LO]],[[T5]]
-; MIPS32: movn [[T1_LO]],zero,[[T5]]
-; MIPS32-O2: move v1,[[T_HI]]
-; MIPS32-OM1: sw [[T_HI]],[[MEM:.*]]
-; MIPS32-OM1: lw v1,[[MEM]]
-
-define internal i32 @shl64BitSignedTrunc(i64 %a, i64 %b) {
-entry:
- %shl = shl i64 %a, %b
- %result = trunc i64 %shl to i32
- ret i32 %result
-}
-; CHECK-LABEL: shl64BitSignedTrunc
-; CHECK: mov
-; CHECK: shl e
-; CHECK: test {{.*}},0x20
-; CHECK: je
-;
-; OPTM1-LABEL: shl64BitSignedTrunc
-; OPTM1: shld
-; OPTM1: shl e
-; OPTM1: test {{.*}},0x20
-; OPTM1: je
-
-; ARM32-LABEL: shl64BitSignedTrunc
-; ARM32: lsl r
-
-; MIPS32-LABEL: shl64BitSignedTrunc
-; MIPS32-O2: sllv
-; MIPS32-O2: andi {{.*}},0x20
-; MIPS32-O2: movn
-
-define internal i64 @shl64BitUnsigned(i64 %a, i64 %b) {
-entry:
- %shl = shl i64 %a, %b
- ret i64 %shl
-}
-; CHECK-LABEL: shl64BitUnsigned
-; CHECK: shld
-; CHECK: shl e
-; CHECK: test {{.*}},0x20
-; CHECK: je
-;
-; OPTM1-LABEL: shl64BitUnsigned
-; OPTM1: shld
-; OPTM1: shl e
-; OPTM1: test {{.*}},0x20
-; OPTM1: je
-
-; ARM32-LABEL: shl64BitUnsigned
-; ARM32: rsb
-; ARM32: lsr
-; ARM32: orr
-; ARM32: sub
-; ARM32: cmp
-; ARM32: lslge
-; ARM32: lsl
-
-; MIPS32-LABEL: shl64BitUnsigned
-; MIPS32: sllv [[T1:.*]],[[A_HI:.*]],[[B_LO:.*]]
-; MIPS32: nor [[T2:.*]],[[B_LO]],zero
-; MIPS32: srl [[T3:.*]],[[A_LO:.*]],0x1
-; MIPS32: srlv [[T4:.*]],[[T3]],[[T2]]
-; MIPS32: or [[T_HI:.*]],[[T1]],[[T4]]
-; MIPS32: sllv [[T_LO:.*]],[[A_LO]],[[B_LO]]
-; MIPS32: move [[T1_LO:.*]],[[T_LO]]
-; MIPS32: andi [[T5:.*]],[[B_LO]],0x20
-; MIPS32: movn [[T_HI]],[[T_LO]],[[T5]]
-; MIPS32: movn [[T1_LO]],zero,[[T5]]
-; MIPS32-O2: move v1,[[T_HI]]
-; MIPS32-OM1: sw [[T_HI]],[[MEM:.*]]
-; MIPS32-OM1: lw v1,[[MEM]]
-
-define internal i64 @shr64BitSigned(i64 %a, i64 %b) {
-entry:
- %shr = ashr i64 %a, %b
- ret i64 %shr
-}
-; CHECK-LABEL: shr64BitSigned
-; CHECK: shrd
-; CHECK: sar
-; CHECK: test {{.*}},0x20
-; CHECK: je
-; CHECK: sar {{.*}},0x1f
-;
-; OPTM1-LABEL: shr64BitSigned
-; OPTM1: shrd
-; OPTM1: sar
-; OPTM1: test {{.*}},0x20
-; OPTM1: je
-; OPTM1: sar {{.*}},0x1f
-
-; ARM32-LABEL: shr64BitSigned
-; ARM32: lsr [[T0:r[0-9]+]], r{{[0-9]+}}, r{{[0-9]+}}
-; ARM32: rsb [[T1:r[0-9]+]], r{{[0-9]+}}, #32
-; ARM32: orr r{{[0-9]+}}, [[T0]], r{{[0-9]+}}, lsl [[T1]]
-; ARM32: sub [[T2:r[0-9]+]], r{{[0-9]+}}, #32
-; ARM32: cmp [[T2]], #0
-; ARM32: asrge r{{[0-9]+}}, r{{[0-9]+}}, [[T2]]
-; ARM32: asr r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}
-
-; MIPS32-LABEL: shr64BitSigned
-; MIPS32: srlv [[T1:.*]],[[A_LO:.*]],[[B_LO:.*]]
-; MIPS32: nor [[T2:.*]],[[B_LO]],zero
-; MIPS32: sll [[T3:.*]],[[A_HI:.*]],0x1
-; MIPS32: sllv [[T4:.*]],[[T3]],[[T2]]
-; MIPS32: or [[T_LO:.*]],[[T1]],[[T4]]
-; MIPS32: srav [[T_HI:.*]],[[A_HI]],[[B_LO]]
-; MIPS32: move [[T_HI1:.*]],[[T_HI]]
-; MIPS32: andi [[T5:.*]],[[B_LO]],0x20
-; MIPS32: movn [[T_LO1:.*]],[[T_HI]],[[T5]]
-; MIPS32: sra [[T6:.*]],[[A_HI]],0x1f
-; MIPS32: movn [[T_HI1]],[[T6]],[[T5]]
-
-define internal i32 @shr64BitSignedTrunc(i64 %a, i64 %b) {
-entry:
- %shr = ashr i64 %a, %b
- %result = trunc i64 %shr to i32
- ret i32 %result
-}
-; CHECK-LABEL: shr64BitSignedTrunc
-; CHECK: shrd
-; CHECK: sar
-; CHECK: test {{.*}},0x20
-; CHECK: je
-;
-; OPTM1-LABEL: shr64BitSignedTrunc
-; OPTM1: shrd
-; OPTM1: sar
-; OPTM1: test {{.*}},0x20
-; OPTM1: je
-; OPTM1: sar {{.*}},0x1f
-
-; ARM32-LABEL: shr64BitSignedTrunc
-; ARM32: lsr
-; ARM32: rsb
-; ARM32: orr
-; ARM32: sub
-; ARM32: cmp
-; ARM32: asrge
-
-; MIPS32-LABEL: shr64BitSignedTrunc
-; MIPS32-O2: srlv
-; MIPS32-O2: nor
-; MIPS32-O2: sll
-; MIPS32-O2: sllv
-; MIPS32-O2: or
-; MIPS32-O2: srav
-; MIPS32-O2: andi {{.*}},0x20
-; MIPS32-O2: movn
-
-define internal i64 @shr64BitUnsigned(i64 %a, i64 %b) {
-entry:
- %shr = lshr i64 %a, %b
- ret i64 %shr
-}
-; CHECK-LABEL: shr64BitUnsigned
-; CHECK: shrd
-; CHECK: shr
-; CHECK: test {{.*}},0x20
-; CHECK: je
-;
-; OPTM1-LABEL: shr64BitUnsigned
-; OPTM1: shrd
-; OPTM1: shr
-; OPTM1: test {{.*}},0x20
-; OPTM1: je
-
-; ARM32-LABEL: shr64BitUnsigned
-; ARM32: lsr
-; ARM32: rsb
-; ARM32: orr
-; ARM32: sub
-; ARM32: cmp
-; ARM32: lsrge
-; ARM32: lsr
-
-; MIPS32-LABEL: shr64BitUnsigned
-; MIPS32: srlv [[T1:.*]],[[A_LO:.*]],[[B_LO:.*]]
-; MIPS32: nor [[T2:.*]],[[B_LO]],zero
-; MIPS32: sll [[T3:.*]],[[A_HI:.*]],0x1
-; MIPS32: sllv [[T4:.*]],[[T3]],[[T2]]
-; MIPS32: or [[T_LO:.*]],[[T1]],[[T4]]
-; MIPS32: srlv [[T_HI:.*]],[[A_HI]],[[B_LO]]
-; MIPS32: move [[T_HI1:.*]],[[T_HI]]
-; MIPS32: andi [[T5:.*]],[[B_LO]],0x20
-; MIPS32: movn [[T_LO1:.*]],[[T_HI]],[[T5]]
-; MIPS32: movn [[T_HI1]],zero,[[T5]]
-
-define internal i32 @shr64BitUnsignedTrunc(i64 %a, i64 %b) {
-entry:
- %shr = lshr i64 %a, %b
- %result = trunc i64 %shr to i32
- ret i32 %result
-}
-; CHECK-LABEL: shr64BitUnsignedTrunc
-; CHECK: shrd
-; CHECK: shr
-; CHECK: test {{.*}},0x20
-; CHECK: je
-;
-; OPTM1-LABEL: shr64BitUnsignedTrunc
-; OPTM1: shrd
-; OPTM1: shr
-; OPTM1: test {{.*}},0x20
-; OPTM1: je
-
-; ARM32-LABEL: shr64BitUnsignedTrunc
-; ARM32: lsr
-; ARM32: rsb
-; ARM32: orr
-; ARM32: sub
-; ARM32: cmp
-; ARM32: lsrge
-
-; MIPS32-LABEL: shr64BitUnsignedTrunc
-; MIPS32-O2: srlv
-; MIPS32-O2: nor
-; MIPS32-O2: sll
-; MIPS32-O2: sllv
-; MIPS32-O2: or
-; MIPS32-O2: srlv
-; MIPS32-O2: andi
-; MIPS32-O2: movn
-
-define internal i64 @and64BitSigned(i64 %a, i64 %b) {
-entry:
- %and = and i64 %b, %a
- ret i64 %and
-}
-; CHECK-LABEL: and64BitSigned
-; CHECK: and
-; CHECK: and
-;
-; OPTM1-LABEL: and64BitSigned
-; OPTM1: and
-; OPTM1: and
-
-; ARM32-LABEL: and64BitSigned
-; ARM32: and
-; ARM32: and
-
-; MIPS32-LABEL: and64BitSigned
-; MIPS32: and
-; MIPS32: and
-
-define internal i64 @and64BitUnsigned(i64 %a, i64 %b) {
-entry:
- %and = and i64 %b, %a
- ret i64 %and
-}
-; CHECK-LABEL: and64BitUnsigned
-; CHECK: and
-; CHECK: and
-;
-; OPTM1-LABEL: and64BitUnsigned
-; OPTM1: and
-; OPTM1: and
-
-; ARM32-LABEL: and64BitUnsigned
-; ARM32: and
-; ARM32: and
-
-; MIPS32-LABEL: and64BitUnsigned
-; MIPS32: and
-; MIPS32: and
-
-define internal i64 @or64BitSigned(i64 %a, i64 %b) {
-entry:
- %or = or i64 %b, %a
- ret i64 %or
-}
-; CHECK-LABEL: or64BitSigned
-; CHECK: or
-; CHECK: or
-;
-; OPTM1-LABEL: or64BitSigned
-; OPTM1: or
-; OPTM1: or
-
-; ARM32-LABEL: or64BitSigned
-; ARM32: orr
-; ARM32: orr
-
-; MIPS32-LABEL: or64BitSigned
-; MIPS32: or
-; MIPS32: or
-
-define internal i64 @or64BitUnsigned(i64 %a, i64 %b) {
-entry:
- %or = or i64 %b, %a
- ret i64 %or
-}
-; CHECK-LABEL: or64BitUnsigned
-; CHECK: or
-; CHECK: or
-;
-; OPTM1-LABEL: or64BitUnsigned
-; OPTM1: or
-; OPTM1: or
-
-; ARM32-LABEL: or64BitUnsigned
-; ARM32: orr
-; ARM32: orr
-
-; MIPS32-LABEL: or64BitUnsigned
-; MIPS32: or
-; MIPS32: or
-
-define internal i64 @xor64BitSigned(i64 %a, i64 %b) {
-entry:
- %xor = xor i64 %b, %a
- ret i64 %xor
-}
-; CHECK-LABEL: xor64BitSigned
-; CHECK: xor
-; CHECK: xor
-;
-; OPTM1-LABEL: xor64BitSigned
-; OPTM1: xor
-; OPTM1: xor
-
-; ARM32-LABEL: xor64BitSigned
-; ARM32: eor
-; ARM32: eor
-
-; MIPS32-LABEL: xor64BitSigned
-; MIPS32: xor
-; MIPS32: xor
-
-define internal i64 @xor64BitUnsigned(i64 %a, i64 %b) {
-entry:
- %xor = xor i64 %b, %a
- ret i64 %xor
-}
-; CHECK-LABEL: xor64BitUnsigned
-; CHECK: xor
-; CHECK: xor
-;
-; OPTM1-LABEL: xor64BitUnsigned
-; OPTM1: xor
-; OPTM1: xor
-
-; ARM32-LABEL: xor64BitUnsigned
-; ARM32: eor
-; ARM32: eor
-
-; MIPS32-LABEL: xor64BitUnsigned
-; MIPS32: xor
-; MIPS32: xor
-
-define internal i32 @trunc64To32Signed(i64 %padding, i64 %a) {
-entry:
- %conv = trunc i64 %a to i32
- ret i32 %conv
-}
-; CHECK-LABEL: trunc64To32Signed
-; CHECK: mov eax,DWORD PTR [esp+0xc]
-;
-; OPTM1-LABEL: trunc64To32Signed
-; OPTM1: mov eax,DWORD PTR [esp+
-
-; ARM32-LABEL: trunc64To32Signed
-; ARM32: mov r0, r2
-
-; MIPS32-LABEL: trunc64To32Signed
-; MIPS32: move v0,a2
-
-define internal i32 @trunc64To16Signed(i64 %a) {
-entry:
- %conv = trunc i64 %a to i16
- %conv.ret_ext = sext i16 %conv to i32
- ret i32 %conv.ret_ext
-}
-; CHECK-LABEL: trunc64To16Signed
-; CHECK: mov eax,DWORD PTR [esp+0x4]
-; CHECK-NEXT: movsx eax,ax
-;
-; OPTM1-LABEL: trunc64To16Signed
-; OPTM1: mov ax,WORD PTR [esp+
-; OPTM1: movsx eax,
-
-; ARM32-LABEL: trunc64To16Signed
-; ARM32: sxth r0, r0
-
-; MIPS32-LABEL: trunc64To16Signed
-; MIPS32-O2: sll [[T1:.*]],a0,0x10
-; MIPS32-O2: sra [[T2:.*]],[[T1]],0x10
-; MIPS32-O2: move v0,[[T2]]
-; MIPS32-OM1: sll [[T1:.*]],{{.*}},0x10
-; MIPS32-OM1: sra [[T2:.*]],[[T1]],0x10
-; MIPS32-OM1: sw [[T2]],[[MEM:.*]]
-; MIPS32-OM1: lw v0,[[MEM]]
-
-define internal i32 @trunc64To8Signed(i64 %a) {
-entry:
- %conv = trunc i64 %a to i8
- %conv.ret_ext = sext i8 %conv to i32
- ret i32 %conv.ret_ext
-}
-; CHECK-LABEL: trunc64To8Signed
-; CHECK: mov eax,DWORD PTR [esp+0x4]
-; CHECK-NEXT: movsx eax,al
-;
-; OPTM1-LABEL: trunc64To8Signed
-; OPTM1: mov eax,DWORD PTR [esp+
-; OPTM1: movsx eax,
-
-; ARM32-LABEL: trunc64To8Signed
-; ARM32: sxtb r0, r0
-
-; MIPS32-LABEL: trunc64To8Signed
-; MIPS32-O2: sll [[T1:.*]],a0,0x18
-; MIPS32-O2: sra [[T2:.*]],[[T1]],0x18
-; MIPS32-O2: move v0,[[T2]]
-; MIPS32-OM1: sll [[T1:.*]],{{.*}},0x18
-; MIPS32-OM1: sra [[T2:.*]],[[T1]],0x18
-; MIPS32-OM1: sw [[T2]],[[MEM:.*]]
-; MIPS32-OM1: lw v0,[[MEM]]
-
-define internal i32 @trunc64To32SignedConst() {
-entry:
- %conv = trunc i64 12345678901234 to i32
- ret i32 %conv
-}
-; CHECK-LABEL: trunc64To32SignedConst
-; CHECK: mov eax,0x73ce2ff2
-;
-; OPTM1-LABEL: trunc64To32SignedConst
-; OPTM1: mov eax,0x73ce2ff2
-
-; ARM32-LABEL: trunc64To32SignedConst
-; ARM32: movw r0, #12274 ; 0x2ff2
-; ARM32: movt r0, #29646 ; 0x73ce
-
-; MIPS32-LABEL: trunc64To32SignedConst
-; MIPS32: lui v0,0x73ce
-; MIPS32: ori v0,v0,0x2ff2
-
-define internal i32 @trunc64To16SignedConst() {
-entry:
- %conv = trunc i64 12345678901234 to i16
- %conv.ret_ext = sext i16 %conv to i32
- ret i32 %conv.ret_ext
-}
-; CHECK-LABEL: trunc64To16SignedConst
-; CHECK: mov eax,0x73ce2ff2
-; CHECK: movsx eax,ax
-;
-; OPTM1-LABEL: trunc64To16SignedConst
-; OPTM1: mov eax,0x73ce2ff2
-; OPTM1: movsx eax,
-
-; ARM32-LABEL: trunc64To16SignedConst
-; ARM32: movw r0, #12274 ; 0x2ff2
-; ARM32: movt r0, #29646 ; 0x73ce
-; ARM32: sxth r0, r0
-
-; MIPS32-LABEL: trunc64To16SignedConst
-; MIPS32: lui v0,0x73ce
-; MIPS32: ori v0,v0,0x2ff2
-; MIPS32: sll v0,v0,0x10
-; MIPS32: sra v0,v0,0x10
-
-define internal i32 @trunc64To32Unsigned(i64 %padding, i64 %a) {
-entry:
- %conv = trunc i64 %a to i32
- ret i32 %conv
-}
-; CHECK-LABEL: trunc64To32Unsigned
-; CHECK: mov eax,DWORD PTR [esp+0xc]
-;
-; OPTM1-LABEL: trunc64To32Unsigned
-; OPTM1: mov eax,DWORD PTR [esp+
-
-; ARM32-LABEL: trunc64To32Unsigned
-; ARM32: mov r0, r2
-
-; MIPS32-LABEL: trunc64To32Unsigned
-; MIPS32: move v0,a2
-
-define internal i32 @trunc64To16Unsigned(i64 %a) {
-entry:
- %conv = trunc i64 %a to i16
- %conv.ret_ext = zext i16 %conv to i32
- ret i32 %conv.ret_ext
-}
-; CHECK-LABEL: trunc64To16Unsigned
-; CHECK: mov eax,DWORD PTR [esp+0x4]
-; CHECK-NEXT: movzx eax,ax
-;
-; OPTM1-LABEL: trunc64To16Unsigned
-; OPTM1: mov ax,WORD PTR [esp+
-; OPTM1: movzx eax,
-
-; ARM32-LABEL: trunc64To16Unsigned
-; ARM32: uxth
-
-; MIPS32-LABEL: trunc64To16Unsigned
-; MIPS32-O2: andi [[T1:.*]],a0,0xffff
-; MIPS32-O2: move v0,[[T1]]
-; MIPS32-OM1: andi [[T1:.*]],{{.*}},0xffff
-; MIPS32-OM1: sw [[T1]],[[MEM:.*]]
-; MIPS32-OM1: lw v0,[[MEM]]
-
-define internal i32 @trunc64To8Unsigned(i64 %a) {
-entry:
- %conv = trunc i64 %a to i8
- %conv.ret_ext = zext i8 %conv to i32
- ret i32 %conv.ret_ext
-}
-; CHECK-LABEL: trunc64To8Unsigned
-; CHECK: mov eax,DWORD PTR [esp+0x4]
-; CHECK-NEXT: movzx eax,al
-;
-; OPTM1-LABEL: trunc64To8Unsigned
-; OPTM1: mov eax,DWORD PTR [esp+
-; OPTM1: movzx eax,
-
-; ARM32-LABEL: trunc64To8Unsigned
-; ARM32: uxtb
-
-; MIPS32-LABEL: trunc64To8Unsigned
-; MIPS32-O2: andi [[T1:.*]],a0,0xff
-; MIPS32-O2: move v0,[[T1]]
-; MIPS32-OM1: andi [[T1:.*]],{{.*}},0xff
-; MIPS32-OM1: sw [[T1]],[[MEM:.*]]
-; MIPS32-OM1: lw v0,[[MEM]]
-
-define internal i32 @trunc64To1(i64 %a) {
-entry:
-; %tobool = icmp ne i64 %a, 0
- %tobool = trunc i64 %a to i1
- %tobool.ret_ext = zext i1 %tobool to i32
- ret i32 %tobool.ret_ext
-}
-; CHECK-LABEL: trunc64To1
-; CHECK: mov eax,DWORD PTR [esp+0x4]
-; CHECK: and al,0x1
-; CHECK-NOT: and eax,0x1
-;
-; OPTM1-LABEL: trunc64To1
-; OPTM1: mov eax,DWORD PTR [esp+
-; OPTM1: and al,0x1
-; OPTM1-NOT: and eax,0x1
-
-; ARM32-LABEL: trunc64To1
-; ARM32-OM1: and r0, r0, #1
-; ARM32-O2: and r0, r0, #1
-
-; MIPS32-LABEL: trunc64To1
-; MIPS32-O2: andi [[T1:.*]],a0,0x1
-; MIPS32-O2: move v0,[[T1]]
-; MIPS32-OM1: andi [[T1:.*]],{{.*}},0x1
-; MIPS32-OM1: sw [[T1]],[[MEM:.*]]
-; MIPS32-OM1: lw v0,[[MEM]]
-
-define internal i64 @sext32To64(i32 %a) {
-entry:
- %conv = sext i32 %a to i64
- ret i64 %conv
-}
-; CHECK-LABEL: sext32To64
-; CHECK: mov
-; CHECK: sar {{.*}},0x1f
-;
-; OPTM1-LABEL: sext32To64
-; OPTM1: mov
-; OPTM1: sar {{.*}},0x1f
-
-; ARM32-LABEL: sext32To64
-; ARM32: asr {{.*}}, #31
-
-; MIPS32-LABEL: sext32To64
-; MIPS32: sra [[T_HI:.*]],[[T_LO:.*]],0x1f
-; MIPS32-O2: move v1,[[T_HI]]
-; MIPS32-O2: move v0,[[T_LO]]
-; MIPS32-OM1: sw [[T_HI]],[[MEM_HI:.*]]
-; MIPS32-OM1: sw [[T_LO]],[[MEM_LO:.*]]
-; MIPS32-OM1: lw v0,[[MEM_LO]]
-; MIPS32-OM1: lw v1,[[MEM_HI]]
-
-define internal i64 @sext16To64(i32 %a) {
-entry:
- %a.arg_trunc = trunc i32 %a to i16
- %conv = sext i16 %a.arg_trunc to i64
- ret i64 %conv
-}
-; CHECK-LABEL: sext16To64
-; CHECK: movsx
-; CHECK: sar {{.*}},0x1f
-;
-; OPTM1-LABEL: sext16To64
-; OPTM1: movsx
-; OPTM1: sar {{.*}},0x1f
-
-; ARM32-LABEL: sext16To64
-; ARM32: sxth
-; ARM32: asr {{.*}}, #31
-
-; MIPS32-LABEL: sext16To64
-; MIPS32: sll [[T1_LO:.*]],{{.*}},0x10
-; MIPS32: sra [[T2_LO:.*]],[[T1_LO]],0x10
-; MIPS32: sra [[T_HI:.*]],[[T2_LO]],0x1f
-; MIPS32-O2: move v1,[[T_HI]]
-; MIPS32-O2: move v0,[[T2_LO]]
-; MIPS32-OM1: sw [[T_HI]],[[MEM_HI:.*]]
-; MIPS32-OM1: sw [[T2_LO]],[[MEM_LO:.*]]
-; MIPS32-OM1: lw v0,[[MEM_LO]]
-; MIPS32-OM1: lw v1,[[MEM_HI]]
-
-
-define internal i64 @sext8To64(i32 %a) {
-entry:
- %a.arg_trunc = trunc i32 %a to i8
- %conv = sext i8 %a.arg_trunc to i64
- ret i64 %conv
-}
-; CHECK-LABEL: sext8To64
-; CHECK: movsx
-; CHECK: sar {{.*}},0x1f
-;
-; OPTM1-LABEL: sext8To64
-; OPTM1: movsx
-; OPTM1: sar {{.*}},0x1f
-
-; ARM32-LABEL: sext8To64
-; ARM32: sxtb
-; ARM32: asr {{.*}}, #31
-
-; MIPS32-LABEL: sext8To64
-; MIPS32: sll [[T1_LO:.*]],{{.*}},0x18
-; MIPS32: sra [[T2_LO:.*]],[[T1_LO]],0x18
-; MIPS32: sra [[T_HI:.*]],[[T2_LO]],0x1f
-; MIPS32-O2: move v1,[[T_HI]]
-; MIPS32-O2: move v0,[[T2_LO]]
-; MIPS32-OM1: sw [[T_HI]],[[MEM_HI:.*]]
-; MIPS32-OM1: sw [[T2_LO]],[[MEM_LO:.*]]
-; MIPS32-OM1: lw v0,[[MEM_LO]]
-; MIPS32-OM1: lw v1,[[MEM_HI]]
-
-define internal i64 @sext1To64(i32 %a) {
-entry:
- %a.arg_trunc = trunc i32 %a to i1
- %conv = sext i1 %a.arg_trunc to i64
- ret i64 %conv
-}
-; CHECK-LABEL: sext1To64
-; CHECK: mov
-; CHECK: shl {{.*}},0x1f
-; CHECK: sar {{.*}},0x1f
-;
-; OPTM1-LABEL: sext1To64
-; OPTM1: mov
-; OPTM1: shl {{.*}},0x1f
-; OPTM1: sar {{.*}},0x1f
-
-; ARM32-LABEL: sext1To64
-; ARM32: mov {{.*}}, #0
-; ARM32: tst {{.*}}, #1
-; ARM32: mvn {{.*}}, #0
-; ARM32: movne
-
-; MIPS32-LABEL: sext1To64
-; MIPS32: sll [[T1:.*]],{{.*}},0x1f
-; MIPS32: sra [[T2:.*]],[[T1]],0x1f
-; MIPS32-O2: move v1,[[T2]]
-; MIPS32-O2: move v0,[[T2]]
-; MIPS32-OM1: sw [[T2]],[[MEM_HI:.*]]
-; MIPS32-OM1: sw [[T2]],[[MEM_LO:.*]]
-; MIPS32-OM1: lw v0,[[MEM_LO]]
-; MIPS32-OM1: lw v1,[[MEM_HI]]
-
-define internal i64 @zext32To64(i32 %a) {
-entry:
- %conv = zext i32 %a to i64
- ret i64 %conv
-}
-; CHECK-LABEL: zext32To64
-; CHECK: mov
-; CHECK: mov {{.*}},0x0
-;
-; OPTM1-LABEL: zext32To64
-; OPTM1: mov
-; OPTM1: mov {{.*}},0x0
-
-; ARM32-LABEL: zext32To64
-; ARM32: mov {{.*}}, #0
-
-; MIPS32-LABEL: zext32To64
-; MIPS32: li [[T1:.*]],0
-; MIPS32-O2: move v1,[[T1]]
-; MIPS32-O2: move v0,a0
-; MIPS32-OM1: sw [[T1]],[[MEM_HI:.*]]
-; MIPS32-OM1: lw v1,[[MEM_HI]]
-
-define internal i64 @zext16To64(i32 %a) {
-entry:
- %a.arg_trunc = trunc i32 %a to i16
- %conv = zext i16 %a.arg_trunc to i64
- ret i64 %conv
-}
-; CHECK-LABEL: zext16To64
-; CHECK: movzx
-; CHECK: mov {{.*}},0x0
-;
-; OPTM1-LABEL: zext16To64
-; OPTM1: movzx
-; OPTM1: mov {{.*}},0x0
-
-; ARM32-LABEL: zext16To64
-; ARM32: uxth
-; ARM32: mov {{.*}}, #0
-
-; MIPS32-LABEL: zext16To64
-; MIPS32: andi [[T_LO:.*]],{{.*}},0xffff
-; MIPS32: li [[T_HI:.*]],0
-; MIPS32-O2: move v1,[[T_HI]]
-; MIPS32-O2: move v0,[[T_LO]]
-; MIPS32-OM1: sw [[T_HI]],[[MEM_HI:.*]]
-; MIPS32-OM1: lw v1,[[MEM_HI]]
-
-define internal i64 @zext8To64(i32 %a) {
-entry:
- %a.arg_trunc = trunc i32 %a to i8
- %conv = zext i8 %a.arg_trunc to i64
- ret i64 %conv
-}
-; CHECK-LABEL: zext8To64
-; CHECK: movzx
-; CHECK: mov {{.*}},0x0
-;
-; OPTM1-LABEL: zext8To64
-; OPTM1: movzx
-; OPTM1: mov {{.*}},0x0
-
-; ARM32-LABEL: zext8To64
-; ARM32: uxtb
-; ARM32: mov {{.*}}, #0
-
-; MIPS32-LABEL: zext8To64
-; MIPS32: andi [[T_LO:.*]],{{.*}},0xff
-; MIPS32: li [[T_HI:.*]],0
-; MIPS32-O2: move v1,[[T_HI]]
-; MIPS32-O2: move v0,[[T_LO]]
-; MIPS32-OM1: sw [[T_HI]],[[MEM_HI:.*]]
-; MIPS32-OM1: lw v1,[[MEM_HI]]
-
-define internal i64 @zext1To64(i32 %a) {
-entry:
- %a.arg_trunc = trunc i32 %a to i1
- %conv = zext i1 %a.arg_trunc to i64
- ret i64 %conv
-}
-; CHECK-LABEL: zext1To64
-; CHECK: and {{.*}},0x1
-; CHECK: mov {{.*}},0x0
-;
-; OPTM1-LABEL: zext1To64
-; OPTM1: and {{.*}},0x1
-; OPTM1: mov {{.*}},0x0
-
-; ARM32-LABEL: zext1To64
-; ARM32: and {{.*}}, #1
-; ARM32: mov {{.*}}, #0
-; ARM32: bx
-
-; MIPS32-LABEL: zext1To64
-; MIPS32: andi [[T_LO:.*]],{{.*}},0x1
-; MIPS32: li [[T_HI:.*]],0
-; MIPS32-O2: move v1,[[T_HI]]
-; MIPS32-O2: move v0,[[T_LO]]
-; MIPS32-OM1: sw [[T_HI]],[[MEM_HI:.*]]
-; MIPS32-OM1: lw v1,[[MEM_HI]]
-
-define internal void @icmpEq64(i64 %a, i64 %b, i64 %c, i64 %d) {
-entry:
- %cmp = icmp eq i64 %a, %b
- br i1 %cmp, label %if.then, label %if.end
-
-if.then: ; preds = %entry
- call void @func()
- br label %if.end
-
-if.end: ; preds = %if.then, %entry
- %cmp1 = icmp eq i64 %c, %d
- br i1 %cmp1, label %if.then2, label %if.end3
-
-if.then2: ; preds = %if.end
- call void @func()
- br label %if.end3
-
-if.end3: ; preds = %if.then2, %if.end
- ret void
-}
-; CHECK-LABEL: icmpEq64
-; CHECK: cmp {{.*}}
-; CHECK-NEXT: jne {{.*}}
-; CHECK-NEXT: cmp {{.*}}
-; CHECK-NEXT: jne {{.*}}
-; CHECK-NEXT: call {{.*}}
-; CHECK: cmp {{.*}}
-; CHECK-NEXT: jne {{.*}}
-; CHECK-NEXT: cmp {{.*}}
-; CHECK-NEXT: jne {{.*}}
-; CHECK-NEXT: call {{.*}}
-;
-; OPTM1-LABEL: icmpEq64
-; OPTM1: mov [[RESULT:.*]],0x1
-; OPTM1-NEXT: cmp {{.*}}
-; OPTM1-NEXT: jne {{.*}}
-; OPTM1-NEXT: cmp {{.*}}
-; OPTM1-NEXT: je {{.*}}
-; OPTM1-NEXT: mov [[RESULT]],0x0
-; OPTM1-NEXT: cmp [[RESULT]],0x0
-; OPTM1-NEXT: jne
-; OPTM1-NEXT: jmp
-; OPTM1-NEXT: call
-; OPTM1: mov [[RESULT:.*]],0x1
-; OPTM1-NEXT: cmp {{.*}}
-; OPTM1-NEXT: jne {{.*}}
-; OPTM1-NEXT: cmp {{.*}}
-; OPTM1-NEXT: je {{.*}}
-; OPTM1-NEXT: mov [[RESULT]],0x0
-; OPTM1-NEXT: cmp [[RESULT]],0x0
-; OPTM1-NEXT: jne
-; OPTM1-NEXT: jmp
-; OPTM1-NEXT: call
-
-; ARM32-LABEL: icmpEq64
-; ARM32: cmp
-; ARM32: cmpeq
-; ARM32-OM1: tst
-; ARM32: bne
-; ARM32: bl {{.*}} <func>
-; ARM32: cmp
-; ARM32: cmpeq
-; ARM32-OM1: tst
-; ARM32: bne
-; ARM32: bl {{.*}} <func>
-; ARM32: bx
-
-; MIPS32-LABEL: icmpEq64
-; MIPS32: xor [[T1:.*]],{{.*}},{{.*}}
-; MIPS32: xor [[T2:.*]],{{.*}},{{.*}}
-; MIPS32: or [[T3:.*]],[[T1]],[[T2]]
-; MIPS32-O2: bnez [[T3]],{{.*}}
-; MIPS32-OM1: sltiu [[T4:.*]],[[T3]],1
-; MIPS32-OM1: sw [[T4]],[[MEM:.*]]
-; MIPS32-OM1: lb [[T5:.*]],[[MEM]]
-; MIPS32-OM1: beqz [[T5]],{{.*}}
-; MIPS32-OM1: b {{.*}}
-; MIPS32: jal {{.*}}
-; MIPS32-OM1: b {{.*}}
-; MIPS32: xor [[T1:.*]],{{.*}},{{.*}}
-; MIPS32: xor [[T2:.*]],{{.*}},{{.*}}
-; MIPS32: or [[T3:.*]],[[T1]],[[T2]]
-; MIPS32-O2: bnez [[T3]],{{.*}}
-; MIPS32-OM1: sltiu [[T4:.*]],[[T3]],1
-; MIPS32-OM1: sw [[T4]],[[MEM:.*]]
-; MIPS32-OM1: lb [[T5:.*]],[[MEM]]
-; MIPS32-OM1: beqz [[T5]],{{.*}}
-; MIPS32-OM1: b {{.*}}
-; MIPS32: jal {{.*}}
-; MIPS32-OM1: b {{.*}}
-
-declare void @func()
-
-define internal void @icmpNe64(i64 %a, i64 %b, i64 %c, i64 %d) {
-entry:
- %cmp = icmp ne i64 %a, %b
- br i1 %cmp, label %if.then, label %if.end
-
-if.then: ; preds = %entry
- call void @func()
- br label %if.end
-
-if.end: ; preds = %if.then, %entry
- %cmp1 = icmp ne i64 %c, %d
- br i1 %cmp1, label %if.then2, label %if.end3
-
-if.then2: ; preds = %if.end
- call void @func()
- br label %if.end3
-
-if.end3: ; preds = %if.end, %if.then2
- ret void
-}
-; CHECK-LABEL: icmpNe64
-; CHECK: cmp {{.*}}
-; CHECK-NEXT: jne {{.*}}
-; CHECK-NEXT: cmp {{.*}}
-; CHECK-NEXT: je {{.*}}
-; CHECK-NEXT: call {{.*}}
-; CHECK: cmp {{.*}}
-; CHECK-NEXT: jne {{.*}}
-; CHECK-NEXT: cmp {{.*}}
-; CHECK-NEXT: je {{.*}}
-; CHECK-NEXT: call {{.*}}
-;
-; OPTM1-LABEL: icmpNe64
-; OPTM1: mov [[RESULT:.*]],0x1
-; OPTM1-NEXT: cmp {{.*}}
-; OPTM1-NEXT: jne {{.*}}
-; OPTM1-NEXT: cmp {{.*}}
-; OPTM1-NEXT: jne {{.*}}
-; OPTM1-NEXT: mov [[RESULT:.*]],0x0
-; OPTM1-NEXT: cmp [[RESULT]],0x0
-; OPTM1-NEXT: jne {{.*}}
-; OPTM1-NEXT: jmp {{.*}}
-; OPTM1-NEXT: call
-; OPTM1: mov [[RESULT:.*]],0x1
-; OPTM1-NEXT: cmp {{.*}}
-; OPTM1-NEXT: jne {{.*}}
-; OPTM1-NEXT: cmp {{.*}}
-; OPTM1-NEXT: jne {{.*}}
-; OPTM1-NEXT: mov [[RESULT:.*]],0x0
-; OPTM1-NEXT: cmp [[RESULT]],0x0
-; OPTM1-NEXT: jne {{.*}}
-; OPTM1-NEXT: jmp {{.*}}
-; OPTM1-NEXT: call
-
-; ARM32-LABEL: icmpNe64
-; ARM32: cmp
-; ARM32: cmpeq
-; ARM32-OM1: tst
-; ARM32-OM1: bne
-; ARM32-O2: beq
-; ARM32: bl {{.*}} <func>
-; ARM32: cmp
-; ARM32: cmpeq
-; ARM32-OM1: tst
-; ARM32-OM1: bne
-; ARM32-O2: beq
-; ARM32: bl
-
-; MIPS32-LABEL: icmpNe64
-; MIPS32: xor [[T1:.*]],{{.*}},{{.*}}
-; MIPS32: xor [[T2:.*]],{{.*}},{{.*}}
-; MIPS32: or [[T3:.*]],[[T1]],[[T2]]
-; MIPS32-O2: beqz [[T3]],{{.*}}
-; MIPS32-OM1: sltu [[T4:.*]],zero,[[T3]]
-; MIPS32-OM1: sw [[T4]],[[MEM:.*]]
-; MIPS32-OM1: lb [[T5:.*]],[[MEM]]
-; MIPS32-OM1: beqz [[T5]],{{.*}}
-; MIPS32-OM1: b {{.*}}
-; MIPS32: jal {{.*}}
-; MIPS32-OM1: b {{.*}}
-; MIPS32: xor [[T1:.*]],{{.*}},{{.*}}
-; MIPS32: xor [[T2:.*]],{{.*}},{{.*}}
-; MIPS32: or [[T3:.*]],[[T1]],[[T2]]
-; MIPS32-O2: beqz [[T3]],{{.*}}
-; MIPS32-OM1: sltu [[T4:.*]],zero,[[T3]]
-; MIPS32-OM1: sw [[T4]],[[MEM:.*]]
-; MIPS32-OM1: lb [[T5:.*]],[[MEM]]
-; MIPS32-OM1: beqz [[T5]],{{.*}}
-; MIPS32-OM1: b {{.*}}
-; MIPS32: jal {{.*}}
-; MIPS32-OM1: b {{.*}}
-
-define internal void @icmpGt64(i64 %a, i64 %b, i64 %c, i64 %d) {
-entry:
- %cmp = icmp ugt i64 %a, %b
- br i1 %cmp, label %if.then, label %if.end
-
-if.then: ; preds = %entry
- call void @func()
- br label %if.end
-
-if.end: ; preds = %if.then, %entry
- %cmp1 = icmp sgt i64 %c, %d
- br i1 %cmp1, label %if.then2, label %if.end3
-
-if.then2: ; preds = %if.end
- call void @func()
- br label %if.end3
-
-if.end3: ; preds = %if.then2, %if.end
- ret void
-}
-; CHECK-LABEL: icmpGt64
-; CHECK: ja
-; CHECK: jb
-; CHECK: jbe
-; CHECK: call
-; CHECK: jg
-; CHECK: jl
-; CHECK: jbe
-; CHECK: call
-;
-; OPTM1-LABEL: icmpGt64
-; OPTM1: ja
-; OPTM1: jb
-; OPTM1: ja
-; OPTM1: call
-; OPTM1: jg
-; OPTM1: jl
-; OPTM1: ja
-; OPTM1: call
-
-; ARM32-LABEL: icmpGt64
-; ARM32: cmp
-; ARM32: cmpeq
-; ARM32-OM1: tst
-; ARM32-OM1: bne
-; ARM32-O2: bls
-; ARM32: bl
-; ARM32: cmp
-; ARM32: sbcs
-; ARM32-OM1: tst
-; ARM32-OM1: bne
-; ARM32-O2: bge
-; ARM32: bl
-
-; MIPS32-LABEL: icmpGt64
-; MIPS32: xor [[T1:.*]],[[A_HI:.*]],[[B_HI:.*]]
-; MIPS32-O2: sltu [[T2:.*]],[[B_HI]],[[A_HI]]
-; MIPS32-O2: xori [[T3:.*]],[[T2]],0x1
-; MIPS32-O2: sltu [[T4:.*]],{{.*}},{{.*}}
-; MIPS32-O2: xori [[T5:.*]],[[T4]],0x1
-; MIPS32-OM1: sltu [[T3:.*]],[[B_HI]],[[A_HI]]
-; MIPS32-OM1: sltu [[T5:.*]],{{.*}},{{.*}}
-; MIPS32: movz [[T3]],[[T5]],[[T1]]
-; MIPS32-O2: bnez [[T3]],{{.*}}
-; MIPS32-OM1: sw [[T3]],[[MEM:.*]]
-; MIPS32-OM1: lb [[T6:.*]],[[MEM]]
-; MIPS32-OM1: beqz [[T6]],{{.*}}
-; MIPS32-OM1: b {{.*}}
-; MIPS32: jal {{.*}}
-; MIPS32-OM1: b {{.*}}
-; MIPS32: xor [[T1:.*]],[[A_HI:.*]],[[B_HI:.*]]
-; MIPS32-O2: slt [[T2:.*]],[[B_HI]],[[A_HI]]
-; MIPS32-O2: xori [[T3:.*]],[[T2]],0x1
-; MIPS32-O2: sltu [[T4:.*]],{{.*}},{{.*}}
-; MIPS32-O2: xori [[T5:.*]],[[T4]],0x1
-; MIPS32-OM1: slt [[T3:.*]],[[B_HI]],[[A_HI]]
-; MIPS32-OM1: sltu [[T5:.*]],{{.*}},{{.*}}
-; MIPS32: movz [[T3]],[[T5]],[[T1]]
-; MIPS32-O2: bnez [[T3]],{{.*}}
-; MIPS32-OM1: sw [[T3]],[[MEM:.*]]
-; MIPS32-OM1: lb [[T6:.*]],[[MEM]]
-; MIPS32-OM1: beqz [[T6]],{{.*}}
-; MIPS32-OM1: b {{.*}}
-; MIPS32: jal {{.*}}
-; MIPS32-OM1: b {{.*}}
-
-define internal void @icmpGe64(i64 %a, i64 %b, i64 %c, i64 %d) {
-entry:
- %cmp = icmp uge i64 %a, %b
- br i1 %cmp, label %if.then, label %if.end
-
-if.then: ; preds = %entry
- call void @func()
- br label %if.end
-
-if.end: ; preds = %if.then, %entry
- %cmp1 = icmp sge i64 %c, %d
- br i1 %cmp1, label %if.then2, label %if.end3
-
-if.then2: ; preds = %if.end
- call void @func()
- br label %if.end3
-
-if.end3: ; preds = %if.end, %if.then2
- ret void
-}
-; CHECK-LABEL: icmpGe64
-; CHECK: ja
-; CHECK: jb
-; CHECK: jb
-; CHECK: call
-; CHECK: jg
-; CHECK: jl
-; CHECK: jb
-; CHECK: call
-;
-; OPTM1-LABEL: icmpGe64
-; OPTM1: ja
-; OPTM1: jb
-; OPTM1: jae
-; OPTM1: call
-; OPTM1: jg
-; OPTM1: jl
-; OPTM1: jae
-; OPTM1: call
-
-; ARM32-LABEL: icmpGe64
-; ARM32: cmp
-; ARM32: cmpeq
-; ARM32-OM1: tst
-; ARM32-OM1: bne
-; ARM32-O2: bcc
-; ARM32: bl
-; ARM32: cmp
-; ARM32: sbcs
-; ARM32-OM1: tst
-; ARM32-OM1: bne
-; ARM32-O2: blt
-; ARM32: bl
-
-; MIPS32-LABEL: icmpGe64
-; MIPS32: xor [[T1:.*]],[[A_HI:.*]],[[B_HI:.*]]
-; MIPS32-OM1: sltu [[T2:.*]],[[A_HI]],[[B_HI]]
-; MIPS32-OM1: xori [[T3:.*]],[[T2]],0x1
-; MIPS32-OM1: sltu [[T4:.*]],{{.*}},{{.*}}
-; MIPS32-OM1: xori [[T5:.*]],[[T4]],0x1
-; MIPS32-O2: sltu [[T3:.*]],[[A_HI]],[[B_HI]]
-; MIPS32-O2: sltu [[T5:.*]],{{.*}},{{.*}}
-; MIPS32: movz [[T3]],[[T5]],[[T1]]
-; MIPS32-O2: bnez [[T3]],{{.*}}
-; MIPS32-OM1: sw [[T3]],[[MEM:.*]]
-; MIPS32-OM1: lb [[T6:.*]],[[MEM]]
-; MIPS32-OM1: beqz [[T6]],{{.*}}
-; MIPS32-OM1: b {{.*}}
-; MIPS32: jal {{.*}}
-; MIPS32-OM1: b {{.*}}
-; MIPS32: xor [[T1:.*]],[[A_HI:.*]],[[B_HI:.*]]
-; MIPS32-OM1: slt [[T2:.*]],[[A_HI]],[[B_HI]]
-; MIPS32-OM1: xori [[T3:.*]],[[T2]],0x1
-; MIPS32-OM1: sltu [[T4:.*]],{{.*}},{{.*}}
-; MIPS32-OM1: xori [[T5:.*]],[[T4]],0x1
-; MIPS32-O2: slt [[T3:.*]],[[A_HI]],[[B_HI]]
-; MIPS32-O2: sltu [[T5:.*]],{{.*}},{{.*}}
-; MIPS32: movz [[T3]],[[T5]],[[T1]]
-; MIPS32-O2: bnez [[T3]],{{.*}}
-; MIPS32-OM1: sw [[T3]],[[MEM:.*]]
-; MIPS32-OM1: lb [[T6:.*]],[[MEM]]
-; MIPS32-OM1: beqz [[T6]],{{.*}}
-; MIPS32-OM1: b {{.*}}
-; MIPS32: jal {{.*}}
-; MIPS32-OM1: b {{.*}}
-
-define internal void @icmpLt64(i64 %a, i64 %b, i64 %c, i64 %d) {
-entry:
- %cmp = icmp ult i64 %a, %b
- br i1 %cmp, label %if.then, label %if.end
-
-if.then: ; preds = %entry
- call void @func()
- br label %if.end
-
-if.end: ; preds = %if.then, %entry
- %cmp1 = icmp slt i64 %c, %d
- br i1 %cmp1, label %if.then2, label %if.end3
-
-if.then2: ; preds = %if.end
- call void @func()
- br label %if.end3
-
-if.end3: ; preds = %if.then2, %if.end
- ret void
-}
-; CHECK-LABEL: icmpLt64
-; CHECK: jb
-; CHECK: ja
-; CHECK: jae
-; CHECK: call
-; CHECK: jl
-; CHECK: jg
-; CHECK: jae
-; CHECK: call
-;
-; OPTM1-LABEL: icmpLt64
-; OPTM1: jb
-; OPTM1: ja
-; OPTM1: jb
-; OPTM1: call
-; OPTM1: jl
-; OPTM1: jg
-; OPTM1: jb
-; OPTM1: call
-
-; ARM32-LABEL: icmpLt64
-; ARM32: cmp
-; ARM32: cmpeq
-; ARM32-OM1: tst
-; ARM32-OM1: bne
-; ARM32-O2: bcs
-; ARM32: bl
-; ARM32: cmp
-; ARM32: sbcs
-; ARM32-OM1: tst
-; ARM32-OM1: bne
-; ARM32-O2: bge
-; ARM32: bl
-
-; MIPS32-LABEL: icmpLt64
-; MIPS32: xor [[T1:.*]],[[A_HI:.*]],[[B_HI:.*]]
-; MIPS32-O2: sltu [[T2:.*]],[[A_HI]],[[B_HI]]
-; MIPS32-O2: xori [[T3:.*]],[[T2]],0x1
-; MIPS32-O2: sltu [[T4:.*]],{{.*}},{{.*}}
-; MIPS32-O2: xori [[T5:.*]],[[T4]],0x1
-; MIPS32-OM1: sltu [[T3:.*]],[[A_HI]],[[B_HI]]
-; MIPS32-OM1: sltu [[T5:.*]],{{.*}},{{.*}}
-; MIPS32: movz [[T3]],[[T5]],[[T1]]
-; MIPS32-O2: bnez [[T3]],{{.*}}
-; MIPS32-OM1: sw [[T3]],[[MEM:.*]]
-; MIPS32-OM1: lb [[T6:.*]],[[MEM]]
-; MIPS32-OM1: beqz [[T6]],{{.*}}
-; MIPS32-OM1: b {{.*}}
-; MIPS32: jal {{.*}}
-; MIPS32-OM1: b {{.*}}
-; MIPS32: xor [[T1:.*]],[[A_HI:.*]],[[B_HI:.*]]
-; MIPS32-O2: slt [[T2:.*]],[[A_HI]],[[B_HI]]
-; MIPS32-O2: xori [[T3:.*]],[[T2]],0x1
-; MIPS32-O2: sltu [[T4:.*]],{{.*}},{{.*}}
-; MIPS32-O2: xori [[T5:.*]],[[T4]],0x1
-; MIPS32-OM1: slt [[T3:.*]],[[A_HI]],[[B_HI]]
-; MIPS32-OM1: sltu [[T5:.*]],{{.*}},{{.*}}
-; MIPS32: movz [[T3]],[[T5]],[[T1]]
-; MIPS32-O2: bnez [[T3]],{{.*}}
-; MIPS32-OM1: sw [[T3]],[[MEM:.*]]
-; MIPS32-OM1: lb [[T6:.*]],[[MEM]]
-; MIPS32-OM1: beqz [[T6]],{{.*}}
-; MIPS32-OM1: b {{.*}}
-; MIPS32: jal {{.*}}
-; MIPS32-OM1: b {{.*}}
-
-define internal void @icmpLe64(i64 %a, i64 %b, i64 %c, i64 %d) {
-entry:
- %cmp = icmp ule i64 %a, %b
- br i1 %cmp, label %if.then, label %if.end
-
-if.then: ; preds = %entry
- call void @func()
- br label %if.end
-
-if.end: ; preds = %if.then, %entry
- %cmp1 = icmp sle i64 %c, %d
- br i1 %cmp1, label %if.then2, label %if.end3
-
-if.then2: ; preds = %if.end
- call void @func()
- br label %if.end3
-
-if.end3: ; preds = %if.end, %if.then2
- ret void
-}
-; CHECK-LABEL: icmpLe64
-; CHECK: jb
-; CHECK: ja
-; CHECK: ja
-; CHECK: call
-; CHECK: jl
-; CHECK: jg
-; CHECK: ja
-; CHECK: call
-;
-; OPTM1-LABEL: icmpLe64
-; OPTM1: jb
-; OPTM1: ja
-; OPTM1: jbe
-; OPTM1: call
-; OPTM1: jl
-; OPTM1: jg
-; OPTM1: jbe
-; OPTM1: call
-
-; ARM32-LABEL: icmpLe64
-; ARM32: cmp
-; ARM32: cmpeq
-; ARM32-OM1: tst
-; ARM32-OM1: bne
-; ARM32-O2: bhi
-; ARM32: bl
-; ARM32: cmp
-; ARM32: sbcs
-; ARM32-OM1: tst
-; ARM32-OM1: bne
-; ARM32-O2: blt
-; ARM32: bl
-
-; MIPS32-LABEL: icmpLe64
-; MIPS32: xor [[T1:.*]],[[A_HI:.*]],[[B_HI:.*]]
-; MIPS32-OM1: sltu [[T2:.*]],[[B_HI]],[[A_HI]]
-; MIPS32-OM1: xori [[T3:.*]],[[T2]],0x1
-; MIPS32-OM1: sltu [[T4:.*]],{{.*}},{{.*}}
-; MIPS32-OM1: xori [[T5:.*]],[[T4]],0x1
-; MIPS32-O2: sltu [[T3:.*]],[[B_HI]],[[A_HI]]
-; MIPS32-O2: sltu [[T5:.*]],{{.*}},{{.*}}
-; MIPS32: movz [[T3]],[[T5]],[[T1]]
-; MIPS32-O2: bnez [[T3]],{{.*}}
-; MIPS32-OM1: sw [[T3]],[[MEM:.*]]
-; MIPS32-OM1: lb [[T6:.*]],[[MEM]]
-; MIPS32-OM1: beqz [[T6]],{{.*}}
-; MIPS32-OM1: b {{.*}}
-; MIPS32: jal {{.*}}
-; MIPS32-OM1: b {{.*}}
-; MIPS32: xor [[T1:.*]],[[A_HI:.*]],[[B_HI:.*]]
-; MIPS32-OM1: slt [[T2:.*]],[[B_HI]],[[A_HI]]
-; MIPS32-OM1: xori [[T3:.*]],[[T2]],0x1
-; MIPS32-OM1: sltu [[T4:.*]],{{.*}},{{.*}}
-; MIPS32-OM1: xori [[T5:.*]],[[T4]],0x1
-; MIPS32-O2: slt [[T3:.*]],[[B_HI]],[[A_HI]]
-; MIPS32-O2: sltu [[T5:.*]],{{.*}},{{.*}}
-; MIPS32: movz [[T3]],[[T5]],[[T1]]
-; MIPS32-O2: bnez [[T3]],{{.*}}
-; MIPS32-OM1: sw [[T3]],[[MEM:.*]]
-; MIPS32-OM1: lb [[T6:.*]],[[MEM]]
-; MIPS32-OM1: beqz [[T6]],{{.*}}
-; MIPS32-OM1: b {{.*}}
-; MIPS32: jal {{.*}}
-; MIPS32-OM1: b {{.*}}
-
-define internal i32 @icmpEq64Bool(i64 %a, i64 %b) {
-entry:
- %cmp = icmp eq i64 %a, %b
- %cmp.ret_ext = zext i1 %cmp to i32
- ret i32 %cmp.ret_ext
-}
-; CHECK-LABEL: icmpEq64Bool
-; CHECK: jne
-; CHECK: je
-;
-; OPTM1-LABEL: icmpEq64Bool
-; OPTM1: jne
-; OPTM1: je
-
-; ARM32-LABEL: icmpEq64Bool
-; ARM32: mov
-; ARM32: moveq
-
-; MIPS32-LABEL: icmpEq64Bool
-; MIPS32: xor [[T1:.*]],{{.*}},{{.*}}
-; MIPS32: xor [[T2:.*]],{{.*}},{{.*}}
-; MIPS32: or [[T3:.*]],[[T1]],[[T2]]
-; MIPS32: sltiu {{.*}},[[T3]],1
-
-define internal i32 @icmpNe64Bool(i64 %a, i64 %b) {
-entry:
- %cmp = icmp ne i64 %a, %b
- %cmp.ret_ext = zext i1 %cmp to i32
- ret i32 %cmp.ret_ext
-}
-; CHECK-LABEL: icmpNe64Bool
-; CHECK: jne
-; CHECK: jne
-;
-; OPTM1-LABEL: icmpNe64Bool
-; OPTM1: jne
-; OPTM1: jne
-
-; ARM32-LABEL: icmpNe64Bool
-; ARM32: mov
-; ARM32: movne
-
-; MIPS32-LABEL: icmpNe64Bool
-; MIPS32: xor [[T1:.*]],{{.*}},{{.*}}
-; MIPS32: xor [[T2:.*]],{{.*}},{{.*}}
-; MIPS32: or [[T3:.*]],[[T1]],[[T2]]
-; MIPS32: sltu {{.*}},zero,[[T3]]
-
-define internal i32 @icmpSgt64Bool(i64 %a, i64 %b) {
-entry:
- %cmp = icmp sgt i64 %a, %b
- %cmp.ret_ext = zext i1 %cmp to i32
- ret i32 %cmp.ret_ext
-}
-; CHECK-LABEL: icmpSgt64Bool
-; CHECK: cmp
-; CHECK: jg
-; CHECK: jl
-; CHECK: cmp
-; CHECK: ja
-;
-; OPTM1-LABEL: icmpSgt64Bool
-; OPTM1: cmp
-; OPTM1: jg
-; OPTM1: jl
-; OPTM1: cmp
-; OPTM1: ja
-
-; ARM32-LABEL: icmpSgt64Bool
-; ARM32: mov
-; ARM32: cmp
-; ARM32: sbcs
-; ARM32: movlt
-
-; MIPS32-LABEL: icmpSgt64Bool
-; MIPS32: xor [[T1:.*]],[[A_HI:.*]],[[B_HI:.*]]
-; MIPS32: slt [[T2:.*]],{{.*}},{{.*}}
-; MIPS32: sltu [[T3:.*]],{{.*}},{{.*}}
-; MIPS32: movz [[T2]],[[T3]],[[T1]]
-; MIPS32-O2: move {{.*}},[[T2]]
-; MIPS32-OM1: sw [[T2]],[[MEM:.*]]
-; MIPS32-OM1: lb {{.*}},[[MEM]]
-
-define internal i32 @icmpUgt64Bool(i64 %a, i64 %b) {
-entry:
- %cmp = icmp ugt i64 %a, %b
- %cmp.ret_ext = zext i1 %cmp to i32
- ret i32 %cmp.ret_ext
-}
-; CHECK-LABEL: icmpUgt64Bool
-; CHECK: cmp
-; CHECK: ja
-; CHECK: jb
-; CHECK: cmp
-; CHECK: ja
-;
-; OPTM1-LABEL: icmpUgt64Bool
-; OPTM1: cmp
-; OPTM1: ja
-; OPTM1: jb
-; OPTM1: cmp
-; OPTM1: ja
-
-; ARM32-LABEL: icmpUgt64Bool
-; ARM32: mov
-; ARM32: cmp
-; ARM32: cmpeq
-; ARM32: movhi
-
-; MIPS32-LABEL: icmpUgt64Bool
-; MIPS32: xor [[T1:.*]],[[A_HI:.*]],[[B_HI:.*]]
-; MIPS32: sltu [[T2:.*]],[[B_HI]],[[A_HI]]
-; MIPS32: sltu [[T3:.*]],{{.*}},{{.*}}
-; MIPS32: movz [[T2]],[[T3]],[[T1]]
-; MIPS32-O2: move {{.*}},[[T2]]
-; MIPS32-OM1: sw [[T2]],[[MEM:.*]]
-; MIPS32-OM1: lb {{.*}},[[MEM]]
-
-define internal i32 @icmpSge64Bool(i64 %a, i64 %b) {
-entry:
- %cmp = icmp sge i64 %a, %b
- %cmp.ret_ext = zext i1 %cmp to i32
- ret i32 %cmp.ret_ext
-}
-; CHECK-LABEL: icmpSge64Bool
-; CHECK: cmp
-; CHECK: jg
-; CHECK: jl
-; CHECK: cmp
-; CHECK: jae
-;
-; OPTM1-LABEL: icmpSge64Bool
-; OPTM1: cmp
-; OPTM1: jg
-; OPTM1: jl
-; OPTM1: cmp
-; OPTM1: jae
-
-; ARM32-LABEL: icmpSge64Bool
-; ARM32: mov
-; ARM32: cmp
-; ARM32: sbcs
-; ARM32: movge
-
-; MIPS32-LABEL: icmpSge64Bool
-; MIPS32: xor [[T1:.*]],[[A_HI:.*]],[[B_HI:.*]]
-; MIPS32: slt [[T2:.*]],[[A_HI]],[[B_HI]]
-; MIPS32: xori [[T3:.*]],[[T2]],0x1
-; MIPS32: sltu [[T4:.*]],{{.*}},{{.*}}
-; MIPS32: xori [[T5:.*]],[[T4]],0x1
-; MIPS32: movz [[T6:.*]],[[T5]],[[T1]]
-; MIPS32-O2: move {{.*}},[[T3]]
-; MIPS32-OM1: sw [[T3]],[[MEM:.*]]
-; MIPS32-OM1: lb {{.*}},[[MEM]]
-
-define internal i32 @icmpUge64Bool(i64 %a, i64 %b) {
-entry:
- %cmp = icmp uge i64 %a, %b
- %cmp.ret_ext = zext i1 %cmp to i32
- ret i32 %cmp.ret_ext
-}
-; CHECK-LABEL: icmpUge64Bool
-; CHECK: cmp
-; CHECK: ja
-; CHECK: jb
-; CHECK: cmp
-; CHECK: jae
-;
-; OPTM1-LABEL: icmpUge64Bool
-; OPTM1: cmp
-; OPTM1: ja
-; OPTM1: jb
-; OPTM1: cmp
-; OPTM1: jae
-
-; ARM32-LABEL: icmpUge64Bool
-; ARM32: mov
-; ARM32: cmp
-; ARM32: cmpeq
-; ARM32: movcs
-
-; MIPS32-LABEL: icmpUge64Bool
-; MIPS32: xor [[T1:.*]],[[A_HI:.*]],[[B_HI:.*]]
-; MIPS32: sltu [[T2:.*]],[[A_HI]],[[B_HI]]
-; MIPS32: xori [[T3:.*]],[[T2]],0x1
-; MIPS32: sltu [[T4:.*]],{{.*}},{{.*}}
-; MIPS32: xori [[T5:.*]],[[T4]],0x1
-; MIPS32: movz [[T6:.*]],[[T5]],[[T1]]
-; MIPS32-O2: move {{.*}},[[T3]]
-; MIPS32-OM1: sw [[T3]],[[MEM:.*]]
-; MIPS32-OM1: lb {{.*}},[[MEM]]
-
-define internal i32 @icmpSlt64Bool(i64 %a, i64 %b) {
-entry:
- %cmp = icmp slt i64 %a, %b
- %cmp.ret_ext = zext i1 %cmp to i32
- ret i32 %cmp.ret_ext
-}
-; CHECK-LABEL: icmpSlt64Bool
-; CHECK: cmp
-; CHECK: jl
-; CHECK: jg
-; CHECK: cmp
-; CHECK: jb
-;
-; OPTM1-LABEL: icmpSlt64Bool
-; OPTM1: cmp
-; OPTM1: jl
-; OPTM1: jg
-; OPTM1: cmp
-; OPTM1: jb
-
-; ARM32-LABEL: icmpSlt64Bool
-; ARM32: mov
-; ARM32: cmp
-; ARM32: sbcs
-; ARM32: movlt
-
-; MIPS32-LABEL: icmpSlt64Bool
-; MIPS32: xor [[T1:.*]],[[A_HI:.*]],[[B_HI:.*]]
-; MIPS32: slt [[T2:.*]],[[A_HI]],[[B_HI]]
-; MIPS32: sltu [[T3:.*]],{{.*}},{{.*}}
-; MIPS32: movz [[T2:.*]],[[T3]],[[T1]]
-; MIPS32-O2: move {{.*}},[[T2]]
-; MIPS32-OM1: sw [[T2]],[[MEM:.*]]
-; MIPS32-OM1: lb {{.*}},[[MEM]]
-
-define internal i32 @icmpUlt64Bool(i64 %a, i64 %b) {
-entry:
- %cmp = icmp ult i64 %a, %b
- %cmp.ret_ext = zext i1 %cmp to i32
- ret i32 %cmp.ret_ext
-}
-; CHECK-LABEL: icmpUlt64Bool
-; CHECK: cmp
-; CHECK: jb
-; CHECK: ja
-; CHECK: cmp
-; CHECK: jb
-;
-; OPTM1-LABEL: icmpUlt64Bool
-; OPTM1: cmp
-; OPTM1: jb
-; OPTM1: ja
-; OPTM1: cmp
-; OPTM1: jb
-
-; ARM32-LABEL: icmpUlt64Bool
-; ARM32: mov
-; ARM32: cmp
-; ARM32: cmpeq
-; ARM32: movcc
-
-; MIPS32-LABEL: icmpUlt64Bool
-; MIPS32: xor [[T1:.*]],[[A_HI:.*]],[[B_HI:.*]]
-; MIPS32: sltu [[T2:.*]],[[A_HI]],[[B_HI]]
-; MIPS32: sltu [[T3:.*]],{{.*}},{{.*}}
-; MIPS32: movz [[T2:.*]],[[T3]],[[T1]]
-; MIPS32-O2: move {{.*}},[[T2]]
-; MIPS32-OM1: sw [[T2]],[[MEM:.*]]
-; MIPS32-OM1: lb {{.*}},[[MEM]]
-
-define internal i32 @icmpSle64Bool(i64 %a, i64 %b) {
-entry:
- %cmp = icmp sle i64 %a, %b
- %cmp.ret_ext = zext i1 %cmp to i32
- ret i32 %cmp.ret_ext
-}
-; CHECK-LABEL: icmpSle64Bool
-; CHECK: cmp
-; CHECK: jl
-; CHECK: jg
-; CHECK: cmp
-; CHECK: jbe
-;
-; OPTM1-LABEL: icmpSle64Bool
-; OPTM1: cmp
-; OPTM1: jl
-; OPTM1: jg
-; OPTM1: cmp
-; OPTM1: jbe
-
-; ARM32-LABEL: icmpSle64Bool
-; ARM32: mov
-; ARM32: cmp
-; ARM32: sbcs
-; ARM32: movge
-
-; MIPS32-LABEL: icmpSle64Bool
-; MIPS32: xor [[T1:.*]],[[A_HI:.*]],[[B_HI:.*]]
-; MIPS32: slt [[T2:.*]],[[B_HI]],[[A_HI]]
-; MIPS32: xori [[T3:.*]],[[T2]],0x1
-; MIPS32: sltu [[T4:.*]],{{.*}},{{.*}}
-; MIPS32: xori [[T5:.*]],[[T4]],0x1
-; MIPS32: movz [[T6:.*]],[[T5]],[[T1]]
-; MIPS32-O2: move {{.*}},[[T3]]
-; MIPS32-OM1: sw [[T3]],[[MEM:.*]]
-; MIPS32-OM1: lb {{.*}},[[MEM]]
-
-define internal i32 @icmpUle64Bool(i64 %a, i64 %b) {
-entry:
- %cmp = icmp ule i64 %a, %b
- %cmp.ret_ext = zext i1 %cmp to i32
- ret i32 %cmp.ret_ext
-}
-; CHECK-LABEL: icmpUle64Bool
-; CHECK: cmp
-; CHECK: jb
-; CHECK: ja
-; CHECK: cmp
-; CHECK: jbe
-;
-; OPTM1-LABEL: icmpUle64Bool
-; OPTM1: cmp
-; OPTM1: jb
-; OPTM1: ja
-; OPTM1: cmp
-; OPTM1: jbe
-
-; ARM32-LABEL: icmpUle64Bool
-; ARM32: mov
-; ARM32: cmp
-; ARM32: cmpeq
-; ARM32: movls
-
-; MIPS32-LABEL: icmpUle64Bool
-; MIPS32: xor [[T1:.*]],[[A_HI:.*]],[[B_HI:.*]]
-; MIPS32: sltu [[T2:.*]],[[B_HI]],[[A_HI]]
-; MIPS32: xori [[T3:.*]],[[T2]],0x1
-; MIPS32: sltu [[T4:.*]],{{.*}},{{.*}}
-; MIPS32: xori [[T5:.*]],[[T4]],0x1
-; MIPS32: movz [[T6:.*]],[[T5]],[[T1]]
-; MIPS32-O2: move {{.*}},[[T3]]
-; MIPS32-OM1: sw [[T3]],[[MEM:.*]]
-; MIPS32-OM1: lb {{.*}},[[MEM]]
-
-define internal i64 @load64(i32 %a) {
-entry:
- %__1 = inttoptr i32 %a to i64*
- %v0 = load i64, i64* %__1, align 1
- ret i64 %v0
-}
-; CHECK-LABEL: load64
-; CHECK: mov e[[REGISTER:[a-z]+]],DWORD PTR [esp+0x4]
-; CHECK-NEXT: mov {{.*}},DWORD PTR [e[[REGISTER]]]
-; CHECK-NEXT: mov {{.*}},DWORD PTR [e[[REGISTER]]+0x4]
-;
-; OPTM1-LABEL: load64
-; OPTM1: mov e{{..}},DWORD PTR [e{{..}}]
-; OPTM1: mov e{{..}},DWORD PTR [e{{..}}+0x4]
-
-; ARM32-LABEL: load64
-; ARM32: ldr r{{.*}}, [r[[REG:.*]]]
-; ARM32: ldr r{{.*}}, [r[[REG]], #4]
-
-; MIPS32-LABEL: load64
-; MIPS32-O2: lw {{.*}},0([[REG:.*]])
-; MIPS32-O2: lw [[REG]],4([[REG]])
-
-define internal void @store64(i32 %a, i64 %value) {
-entry:
- %__2 = inttoptr i32 %a to i64*
- store i64 %value, i64* %__2, align 1
- ret void
-}
-; CHECK-LABEL: store64
-; CHECK: mov e[[REGISTER:[a-z]+]],DWORD PTR [esp+0x4]
-; CHECK: mov DWORD PTR [e[[REGISTER]]+0x4],
-; CHECK: mov DWORD PTR [e[[REGISTER]]],
-;
-; OPTM1-LABEL: store64
-; OPTM1: mov DWORD PTR [e[[REGISTER:[a-z]+]]+0x4],
-; OPTM1: mov DWORD PTR [e[[REGISTER]]],
-
-; ARM32-LABEL: store64
-; ARM32: str r{{.*}}, [r[[REG:.*]], #4]
-; ARM32: str r{{.*}}, [r[[REG]]]
-
-; MIPS32-LABEL: store64
-; MIPS32-O2: sw {{.*}},4([[REG:.*]])
-; MIPS32-O2: sw {{.*}},0([[REG]])
-
-define internal void @store64Const(i32 %a) {
-entry:
- %__1 = inttoptr i32 %a to i64*
- store i64 -2401053092306725256, i64* %__1, align 1
- ret void
-}
-; CHECK-LABEL: store64Const
-; CHECK: mov e[[REGISTER:[a-z]+]],DWORD PTR [esp+0x4]
-; CHECK: mov DWORD PTR [e[[REGISTER]]+0x4],0xdeadbeef
-; CHECK: mov DWORD PTR [e[[REGISTER]]],0x12345678
-;
-; OPTM1-LABEL: store64Const
-; OPTM1: mov DWORD PTR [e[[REGISTER:[a-z]+]]+0x4],0xdeadbeef
-; OPTM1: mov DWORD PTR [e[[REGISTER]]],0x12345678
-
-; ARM32-LABEL: store64Const
-; ARM32: movw [[REG1:.*]], #48879 ; 0xbeef
-; ARM32: movt [[REG1:.*]], #57005 ; 0xdead
-; ARM32: movw [[REG2:.*]], #22136 ; 0x5678
-; ARM32: movt [[REG2:.*]], #4660 ; 0x1234
-; ARM32: str [[REG1]], [r[[REG:.*]], #4]
-; ARM32: str [[REG2]], [r[[REG]]]
-
-; MIPS32-LABEL: store64Const
-; MIPS32-O2: lui [[REG1:.*]],0xdead
-; MIPS32-O2: ori [[REG1:.*]],[[REG1]],0xbeef
-; MIPS32-O2: lui [[REG2:.*]],0x1234
-; MIPS32-O2: ori [[REG2:.*]],[[REG2]],0x5678
-; MIPS32-O2: sw [[REG1]],4([[REG:.*]])
-; MIPS32-O2: sw [[REG2]],0([[REG]])
-
-define internal i64 @select64VarVar(i64 %a, i64 %b) {
-entry:
- %cmp = icmp ult i64 %a, %b
- %cond = select i1 %cmp, i64 %a, i64 %b
- ret i64 %cond
-}
-; CHECK-LABEL: select64VarVar
-; CHECK: mov
-; CHECK: mov
-; CHECK: cmp
-; CHECK: jb
-; CHECK: ja
-; CHECK: cmp
-; CHECK: jb
-; CHECK: mov
-; CHECK: mov
-;
-; OPTM1-LABEL: select64VarVar
-; OPTM1: cmp
-; OPTM1: jb
-; OPTM1: ja
-; OPTM1: cmp
-; OPTM1: jb
-; OPTM1: cmp
-; OPTM1: cmovne
-
-; ARM32-LABEL: select64VarVar
-; ARM32: cmp
-; ARM32: cmpeq
-; ARM32-OM1: tst
-; ARM32-OM1: movne
-; ARM32-O2: movcc
-; ARM32-OM1: movne
-; ARM32-O2: movcc
-
-; MIPS32-LABEL: select64VarVar
-; MIPS32: movn
-; MIPS32: movn
-
-define internal i64 @select64VarConst(i64 %a, i64 %b) {
-entry:
- %cmp = icmp ult i64 %a, %b
- %cond = select i1 %cmp, i64 %a, i64 -2401053092306725256
- ret i64 %cond
-}
-; CHECK-LABEL: select64VarConst
-; CHECK: mov
-; CHECK: mov
-; CHECK: cmp
-; CHECK: jb
-; CHECK: ja
-; CHECK: cmp
-; CHECK: jb
-; CHECK: mov
-; CHECK: mov
-;
-; OPTM1-LABEL: select64VarConst
-; OPTM1: cmp
-; OPTM1: jb
-; OPTM1: ja
-; OPTM1: cmp
-; OPTM1: jb
-; OPTM1: cmp
-; OPTM1: cmovne
-
-; ARM32-LABEL: select64VarConst
-; ARM32: mov
-; ARM32: mov
-; ARM32: cmp
-; ARM32: cmpeq
-; ARM32-OM1: tst
-; ARM32-OM1: movne
-; ARM32-O2: movcc
-; ARM32-OM1: movne
-; ARM32-O2: movcc
-; ARM32-O2: mov
-; ARM32-O2: mov
-
-; MIPS32-LABEL: select64VarConst
-; MIPS32: movn
-; MIPS32: movn
-
-define internal i64 @select64ConstVar(i64 %a, i64 %b) {
-entry:
- %cmp = icmp ult i64 %a, %b
- %cond = select i1 %cmp, i64 -2401053092306725256, i64 %b
- ret i64 %cond
-}
-; CHECK-LABEL: select64ConstVar
-; CHECK: mov
-; CHECK: mov
-; CHECK: cmp
-; CHECK: jb
-; CHECK: ja
-; CHECK: cmp
-; CHECK: jb
-; CHECK: mov
-; CHECK: mov
-;
-; OPTM1-LABEL: select64ConstVar
-; OPTM1: cmp
-; OPTM1: jb
-; OPTM1: ja
-; OPTM1: cmp
-; OPTM1: jb
-; OPTM1: cmp
-; OPTM1: cmove
-
-; ARM32-LABEL: select64ConstVar
-; ARM32: cmp
-; ARM32: cmpeq
-; ARM32-OM1: tst
-; ARM32: movw
-; ARM32: movt
-; ARM32-OM1: movne
-; ARM32-O2: movcc
-; ARM32: movw
-; ARM32: movt
-; ARM32-OM1: movne
-; ARM32-O2: movcc
-
-; MIPS32-LABEL: select64ConstVar
-; MIPS32: movn
-; MIPS32: movn
-
-define internal void @icmpEq64Imm() {
-entry:
- %cmp = icmp eq i64 123, 234
- br i1 %cmp, label %if.then, label %if.end
-
-if.then: ; preds = %entry
- call void @func()
- br label %if.end
-
-if.end: ; preds = %if.then, %entry
- %cmp1 = icmp eq i64 345, 456
- br i1 %cmp1, label %if.then2, label %if.end3
-
-if.then2: ; preds = %if.end
- call void @func()
- br label %if.end3
-
-if.end3: ; preds = %if.then2, %if.end
- ret void
-}
-; The following checks are not strictly necessary since one of the RUN
-; lines actually runs the output through the assembler.
-; CHECK-LABEL: icmpEq64Imm
-; CHECK-NOT: cmp 0x{{[0-9a-f]+}},
-; OPTM1-LABEL: icmpEq64Imm
-; OPTM1-LABEL-NOT: cmp 0x{{[0-9a-f]+}},
-; ARM32-LABEL: icmpEq64Imm
-; ARM32-NOT: cmp #{{[0-9a-f]+}},
-
-define internal void @icmpLt64Imm() {
-entry:
- %cmp = icmp ult i64 123, 234
- br i1 %cmp, label %if.then, label %if.end
-
-if.then: ; preds = %entry
- call void @func()
- br label %if.end
-
-if.end: ; preds = %if.then, %entry
- %cmp1 = icmp slt i64 345, 456
- br i1 %cmp1, label %if.then2, label %if.end3
-
-if.then2: ; preds = %if.end
- call void @func()
- br label %if.end3
-
-if.end3: ; preds = %if.then2, %if.end
- ret void
-}
-; The following checks are not strictly necessary since one of the RUN
-; lines actually runs the output through the assembler.
-; CHECK-LABEL: icmpLt64Imm
-; CHECK-NOT: cmp 0x{{[0-9a-f]+}},
-; OPTM1-LABEL: icmpLt64Imm
-; OPTM1-NOT: cmp 0x{{[0-9a-f]+}},
-; ARM32-LABEL: icmpLt64Imm
-; ARM32-NOT: cmp #{{[0-9a-f]+}},
-
-define internal i64 @phi64Imm(i32 %x, i64 %y, i64 %z) {
-entry:
- %cond = icmp eq i32 %x, 88
- br i1 %cond, label %branch1, label %branch2
-branch1:
- %tmp = add i64 %y, %z
- br label %branch2
-
-branch2:
- %merge = phi i64 [ %tmp, %branch1 ], [ 20014547621496, %entry ]
- ret i64 %merge
-}
-; CHECK-LABEL: phi64Imm
-; CHECK: mov {{.*}},0x5678
-; CHECK: mov {{.*}},0x1234
-; OPTM1-LABEL: phi64Imm
-; OPTM1: mov {{.*}},0x5678
-; OPTM1: mov {{.*}},0x1234
-; ARM32-LABEL: phi64Imm
-; ARM32: movw {{.*}}, #22136 ; 0x5678
-; ARM32: movw {{.*}}, #4660 ; 0x1234
-
-define internal i64 @phi64Undef(i32 %x, i64 %y, i64 %z) {
-entry:
- %cond = icmp eq i32 %x, 88
- br i1 %cond, label %branch1, label %branch2
-branch1:
- %tmp = add i64 %y, %z
- br label %branch2
-
-branch2:
- %merge = phi i64 [ %tmp, %branch1 ], [ undef, %entry ]
- ret i64 %merge
-}
-
-; CHECK-LABEL: phi64Undef
-; CHECK: mov {{.*}},0x0
-; CHECK: mov {{.*}},0x0
-; OPTM1-LABEL: phi64Undef
-; OPTM1: mov {{.*}},0x0
-; OPTM1: mov {{.*}},0x0
-; ARM32-LABEL: phi64Undef
-; ARM32: mov {{.*}} #0
-; ARM32: mov {{.*}} #0
-
-define internal i32 @addOneToUpperAfterShift(i64 %value) {
- %a = add i64 %value, 1
- %s = lshr i64 %a, 40
- %t = trunc i64 %s to i32
- %r = add i32 %t, 1
- ret i32 %r
-; ARM32-LABEL: addOneToUpperAfterShift
-; ARM32: adds
-; ARM32: adc
-; ARM32: lsr
-; ARM32: add
-}
-
-define internal i32 @subOneToUpperAfterShift(i64 %value) {
- %a = sub i64 %value, 1
- %s = lshr i64 %a, 40
- %t = trunc i64 %s to i32
- %r = sub i32 %t, 1
- ret i32 %r
-; ARM32-LABEL: subOneToUpperAfterShift
-; ARM32: subs
-; ARM32: sbc
-; ARM32: lsr
-; ARM32: sub
-}
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/8bit.pnacl.ll b/third_party/subzero/tests_lit/llvm2ice_tests/8bit.pnacl.ll
deleted file mode 100644
index fcc939f..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/8bit.pnacl.ll
+++ /dev/null
@@ -1,626 +0,0 @@
-; This tries to be a comprehensive test of i8 operations.
-
-; RUN: %p2i --filetype=obj --disassemble -i %s --args -O2 \
-; RUN: -allow-externally-defined-symbols | FileCheck %s
-; RUN: %p2i --filetype=obj --disassemble -i %s --args -Om1 \
-; RUN: -allow-externally-defined-symbols | FileCheck %s
-
-; The following tests i8 srem/urem lowering on x86-64, specifically that the %ah
-; result gets copied into %al/%bl/%cl/%dl before moved into its final register.
-; This extra copy is forced by excluding al/bl/cl/dl by default (-reg-exclude),
-; but allowing them to be used if absolutely necessary (-reg-reserve).
-
-; RUN: %p2i --target=x8664 --filetype=obj --disassemble -i %s --args -O2 \
-; RUN: -reg-exclude=al,bl,cl,dl -reg-reserve \
-; RUN: -allow-externally-defined-symbols | FileCheck %s --check-prefix=REM
-
-; RUN: %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command %p2i --filetype=asm --assemble --disassemble --target \
-; RUN: mips32 -i %s --args -O2 -allow-externally-defined-symbols \
-; RUN: | %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command FileCheck --check-prefix MIPS32 %s
-
-declare void @useInt(i32 %x)
-
-define internal i32 @add8Bit(i32 %a, i32 %b) {
-entry:
- %a_8 = trunc i32 %a to i8
- %b_8 = trunc i32 %b to i8
- %add = add i8 %b_8, %a_8
- %ret = zext i8 %add to i32
- ret i32 %ret
-}
-; CHECK-LABEL: add8Bit
-; CHECK: add {{[abcd]l}}
-; MIPS32-LABEL: add8Bit
-; MIPS32: addu
-; MIPS32: andi {{.*}},0xff
-; MIPS32: move
-; MIPS32: jr
-; MIPS32: nop
-
-define internal i32 @add8BitConst(i32 %a) {
-entry:
- %a_8 = trunc i32 %a to i8
- %add = add i8 %a_8, 123
- %ret = zext i8 %add to i32
- ret i32 %ret
-}
-; CHECK-LABEL: add8BitConst
-; CHECK: add {{[abcd]l}}
-; MIPS32-LABEL: add8BitConst
-; MIPS32: addiu
-; MIPS32: andi {{.*}},0xff
-; MIPS32: move
-; MIPS32: jr
-; MIPS32: nop
-
-define internal i32 @sub8Bit(i32 %a, i32 %b) {
-entry:
- %a_8 = trunc i32 %a to i8
- %b_8 = trunc i32 %b to i8
- %sub = sub i8 %b_8, %a_8
- %ret = zext i8 %sub to i32
- ret i32 %ret
-}
-; CHECK-LABEL: sub8Bit
-; CHECK: sub {{[abcd]l}}
-; MIPS32-LABEL: sub8Bit
-; MIPS32: subu
-; MIPS32: andi {{.*}},0xff
-; MIPS32: move
-; MIPS32: jr
-; MIPS32: nop
-
-define internal i32 @sub8BitConst(i32 %a) {
-entry:
- %a_8 = trunc i32 %a to i8
- %sub = sub i8 %a_8, 123
- %ret = zext i8 %sub to i32
- ret i32 %ret
-}
-; CHECK-LABEL: sub8BitConst
-; CHECK: sub {{[abcd]l}}
-; MIPS32-LABEL: sub8BitConst
-; MIPS32: addiu {{.*}},-123
-; MIPS32: andi {{.*}},0xff
-; MIPS32: move
-; MIPS32: jr
-; MIPS32: nop
-
-define internal i32 @mul8Bit(i32 %a, i32 %b) {
-entry:
- %a_8 = trunc i32 %a to i8
- %b_8 = trunc i32 %b to i8
- %mul = mul i8 %b_8, %a_8
- %ret = zext i8 %mul to i32
- ret i32 %ret
-}
-; CHECK-LABEL: mul8Bit
-; CHECK: mul {{[abcd]l|BYTE PTR}}
-; MIPS32-LABEL: mul8Bit
-; MIPS32: mul
-; MIPS32: andi {{.*}},0xff
-; MIPS32: move
-; MIPS32: jr
-; MIPS32: nop
-
-define internal i32 @mul8BitConst(i32 %a) {
-entry:
- %a_8 = trunc i32 %a to i8
- %mul = mul i8 %a_8, 56
- %ret = zext i8 %mul to i32
- ret i32 %ret
-}
-; CHECK-LABEL: mul8BitConst
-; 8-bit imul only accepts r/m, not imm
-; CHECK: mov {{.*}},0x38
-; CHECK: mul {{[abcd]l|BYTE PTR}}
-; MIPS32-LABEL: mul8BitConst
-; MIPS32: li
-; MIPS32: mul
-; MIPS32: andi {{.*}},0xff
-; MIPS32: move
-; MIPS32: jr
-; MIPS32: nop
-
-define internal i32 @udiv8Bit(i32 %a, i32 %b) {
-entry:
- %a_8 = trunc i32 %a to i8
- %b_8 = trunc i32 %b to i8
- %udiv = udiv i8 %b_8, %a_8
- %ret = zext i8 %udiv to i32
- ret i32 %ret
-}
-; CHECK-LABEL: udiv8Bit
-; CHECK: div {{[abcd]l|BYTE PTR}}
-; MIPS32-LABEL: udiv8Bit
-; MIPS32: divu
-; MIPS32: teq
-; MIPS32: mflo
-; MIPS32: andi {{.*}},0xff
-; MIPS32: jr
-; MIPS32: nop
-
-define internal i32 @udiv8BitConst(i32 %a) {
-entry:
- %a_8 = trunc i32 %a to i8
- %udiv = udiv i8 %a_8, 123
- %ret = zext i8 %udiv to i32
- ret i32 %ret
-}
-; CHECK-LABEL: udiv8BitConst
-; CHECK: div {{[abcd]l|BYTE PTR}}
-; MIPS32-LABEL: udiv8BitConst
-; MIPS32: li
-; MIPS32: divu
-; MIPS32: teq
-; MIPS32: mflo
-; MIPS32: andi {{.*}},0xff
-; MIPS32: jr
-; MIPS32: nop
-
-define internal i32 @urem8Bit(i32 %a, i32 %b) {
-entry:
- %a_8 = trunc i32 %a to i8
- %b_8 = trunc i32 %b to i8
- %urem = urem i8 %b_8, %a_8
- %ret = zext i8 %urem to i32
- ret i32 %ret
-}
-; CHECK-LABEL: urem8Bit
-; CHECK: div {{[abcd]l|BYTE PTR}}
-; REM-LABEL: urem8Bit
-; REM: div
-; REM-NEXT: mov {{[abcd]}}l,ah
-; MIPS32-LABEL: urem8Bit
-; MIPS32: divu
-; MIPS32: teq
-; MIPS32: mfhi
-; MIPS32: andi {{.*}},0xff
-; MIPS32: jr
-; MIPS32: nop
-
-define internal i32 @urem8BitConst(i32 %a) {
-entry:
- %a_8 = trunc i32 %a to i8
- %urem = urem i8 %a_8, 123
- %ret = zext i8 %urem to i32
- ret i32 %ret
-}
-; CHECK-LABEL: urem8BitConst
-; CHECK: div {{[abcd]l|BYTE PTR}}
-; REM-LABEL: urem8BitConst
-; MIPS32-LABEL: urem8BitConst
-; MIPS32: li
-; MIPS32: divu
-; MIPS32: teq
-; MIPS32: mfhi
-; MIPS32: andi {{.*}},0xff
-; MIPS32: jr
-; MIPS32: nop
-
-
-define internal i32 @sdiv8Bit(i32 %a, i32 %b) {
-entry:
- %a_8 = trunc i32 %a to i8
- %b_8 = trunc i32 %b to i8
- %sdiv = sdiv i8 %b_8, %a_8
- %ret = zext i8 %sdiv to i32
- ret i32 %ret
-}
-; CHECK-LABEL: sdiv8Bit
-; CHECK: idiv {{[abcd]l|BYTE PTR}}
-; MIPS32-LABEL: sdiv8Bit
-; MIPS32: div
-; MIPS32: teq
-; MIPS32: mflo
-; MIPS32: andi {{.*}},0xff
-; MIPS32: jr
-; MIPS32: nop
-
-define internal i32 @sdiv8BitConst(i32 %a) {
-entry:
- %a_8 = trunc i32 %a to i8
- %sdiv = sdiv i8 %a_8, 123
- %ret = zext i8 %sdiv to i32
- ret i32 %ret
-}
-; CHECK-LABEL: sdiv8BitConst
-; CHECK: idiv {{[abcd]l|BYTE PTR}}
-; MIPS32-LABEL: sdiv8BitConst
-; MIPS32: li
-; MIPS32: div
-; MIPS32: teq
-; MIPS32: mflo
-; MIPS32: andi {{.*}},0xff
-; MIPS32: jr
-; MIPS32: nop
-
-define internal i32 @srem8Bit(i32 %a, i32 %b) {
-entry:
- %a_8 = trunc i32 %a to i8
- %b_8 = trunc i32 %b to i8
- %srem = srem i8 %b_8, %a_8
- %ret = zext i8 %srem to i32
- ret i32 %ret
-}
-; CHECK-LABEL: srem8Bit
-; CHECK: idiv {{[abcd]l|BYTE PTR}}
-; REM-LABEL: srem8Bit
-; REM: idiv
-; REM-NEXT: mov {{[abcd]}}l,ah
-; MIPS32-LABEL: srem8Bit
-; MIPS32: div
-; MIPS32: teq
-; MIPS32: mfhi
-; MIPS32: andi {{.*}},0xff
-; MIPS32: jr
-; MIPS32: nop
-
-define internal i32 @srem8BitConst(i32 %a) {
-entry:
- %a_8 = trunc i32 %a to i8
- %srem = srem i8 %a_8, 123
- %ret = zext i8 %srem to i32
- ret i32 %ret
-}
-; CHECK-LABEL: srem8BitConst
-; CHECK: idiv {{[abcd]l|BYTE PTR}}
-; REM-LABEL: srem8BitConst
-; MIPS32-LABEL: srem8BitConst
-; MIPS32: li
-; MIPS32: div
-; MIPS32: teq
-; MIPS32: mfhi
-; MIPS32: andi {{.*}},0xff
-; MIPS32: jr
-; MIPS32: nop
-
-define internal i32 @shl8Bit(i32 %a, i32 %b) {
-entry:
- %a_8 = trunc i32 %a to i8
- %b_8 = trunc i32 %b to i8
- %shl = shl i8 %b_8, %a_8
- %ret = zext i8 %shl to i32
- ret i32 %ret
-}
-; CHECK-LABEL: shl8Bit
-; CHECK: shl {{[abd]l|BYTE PTR}},cl
-; MIPS32-LABEL: shl8Bit
-; MIPS32: sllv
-; MIPS32: andi {{.*}},0xff
-; MIPS32: move
-; MIPS32: jr
-; MIPS32: nop
-
-define internal i32 @shl8BitConst(i32 %a, i32 %b) {
-entry:
- %a_8 = trunc i32 %a to i8
- %shl = shl i8 %a_8, 6
- %ret = zext i8 %shl to i32
- ret i32 %ret
-}
-; CHECK-LABEL: shl8BitConst
-; CHECK: shl {{[abcd]l|BYTE PTR}},0x6
-; MIPS32-LABEL: shl8BitConst
-; MIPS32: sll
-; MIPS32: andi {{.*}},0xff
-; MIPS32: move
-; MIPS32: jr
-; MIPS32: nop
-
-define internal i32 @lshr8Bit(i32 %a, i32 %b) {
-entry:
- %a_8 = trunc i32 %a to i8
- %b_8 = trunc i32 %b to i8
- %lshr = lshr i8 %b_8, %a_8
- %ret = zext i8 %lshr to i32
- ret i32 %ret
-}
-; CHECK-LABEL: lshr8Bit
-; CHECK: shr {{[abd]l|BYTE PTR}},cl
-; MIPS32-LABEL: lshr8Bit
-; MIPS32: srlv
-; MIPS32: andi {{.*}},0xff
-; MIPS32: move
-; MIPS32: jr
-; MIPS32: nop
-
-define internal i32 @lshr8BitConst(i32 %a, i32 %b) {
-entry:
- %a_8 = trunc i32 %a to i8
- %lshr = lshr i8 %a_8, 6
- %ret = zext i8 %lshr to i32
- ret i32 %ret
-}
-; CHECK-LABEL: lshr8BitConst
-; CHECK: shr {{[abcd]l|BYTE PTR}},0x6
-; MIPS32-LABEL: lshr8BitConst
-; MIPS32: srl
-; MIPS32: andi {{.*}},0xff
-; MIPS32: move
-; MIPS32: jr
-; MIPS32: nop
-
-define internal i32 @ashr8Bit(i32 %a, i32 %b) {
-entry:
- %a_8 = trunc i32 %a to i8
- %b_8 = trunc i32 %b to i8
- %ashr = ashr i8 %b_8, %a_8
- %ret = zext i8 %ashr to i32
- ret i32 %ret
-}
-; CHECK-LABEL: ashr8Bit
-; CHECK: sar {{[abd]l|BYTE PTR}},cl
-; MIPS32-LABEL: ashr8Bit
-; MIPS32: sra
-; MIPS32: andi {{.*}},0xff
-; MIPS32: move
-; MIPS32: jr
-; MIPS32: nop
-
-define internal i32 @ashr8BitConst(i32 %a, i32 %b) {
-entry:
- %a_8 = trunc i32 %a to i8
- %ashr = ashr i8 %a_8, 6
- %ret = zext i8 %ashr to i32
- ret i32 %ret
-}
-; CHECK-LABEL: ashr8BitConst
-; CHECK: sar {{[abcd]l|BYTE PTR}},0x6
-; MIPS32-LABEL: ashr8BitConst
-; MIPS32: sra
-; MIPS32: andi {{.*}},0xff
-; MIPS32: move
-; MIPS32: jr
-; MIPS32: nop
-
-define internal i32 @icmp8Bit(i32 %a, i32 %b) {
-entry:
- %a_8 = trunc i32 %a to i8
- %b_8 = trunc i32 %b to i8
- %icmp = icmp ne i8 %b_8, %a_8
- %ret = zext i1 %icmp to i32
- ret i32 %ret
-}
-; CHECK-LABEL: icmp8Bit
-; CHECK: cmp {{[abcd]l|BYTE PTR}}
-; MIPS32-LABEL: icmp8Bit
-; MIPS32: sll {{.*}},0x18
-; MIPS32: sll {{.*}},0x18
-; MIPS32: xor
-; MIPS32: sltu
-; MIPS32: andi {{.*}},0x1
-; MIPS32: move
-; MIPS32: jr
-; MIPS32: nop
-
-define internal i32 @icmp8BitConst(i32 %a) {
-entry:
- %a_8 = trunc i32 %a to i8
- %icmp = icmp ne i8 %a_8, 123
- %ret = zext i1 %icmp to i32
- ret i32 %ret
-}
-; CHECK-LABEL: icmp8BitConst
-; CHECK: cmp {{[abcd]l|BYTE PTR}}
-; MIPS32-LABEL: icmp8BitConst
-; MIPS32: li
-; MIPS32: sll {{.*}},0x18
-; MIPS32: sll {{.*}},0x18
-; MIPS32: xor
-; MIPS32: sltu
-; MIPS32: andi {{.*}},0x1
-; MIPS32: move
-; MIPS32: jr
-; MIPS32: nop
-
-define internal i32 @icmp8BitConstSwapped(i32 %a) {
-entry:
- %a_8 = trunc i32 %a to i8
- %icmp = icmp ne i8 123, %a_8
- %ret = zext i1 %icmp to i32
- ret i32 %ret
-}
-; CHECK-LABEL: icmp8BitConstSwapped
-; CHECK: cmp {{[abcd]l|BYTE PTR}}
-; MIPS32-LABEL: icmp8BitConstSwapped
-; MIPS32: li
-; MIPS32: sll {{.*}},0x18
-; MIPS32: sll {{.*}},0x18
-; MIPS32: xor v0,v0,a0
-; MIPS32: sltu
-; MIPS32: andi {{.*}},0x1
-; MIPS32: jr
-; MIPS32: nop
-
-define internal i32 @icmp8BitMem(i32 %a, i32 %b_iptr) {
-entry:
- %a_8 = trunc i32 %a to i8
- %bptr = inttoptr i32 %b_iptr to i8*
- %b_8 = load i8, i8* %bptr, align 1
- %icmp = icmp ne i8 %b_8, %a_8
- %ret = zext i1 %icmp to i32
- ret i32 %ret
-}
-; CHECK-LABEL: icmp8BitMem
-; CHECK: cmp {{[abcd]l|BYTE PTR}}
-; MIPS32-LABEL: icmp8BitMem
-; MIPS32: lb
-; MIPS32: sll {{.*}},0x18
-; MIPS32: sll {{.*}},0x18
-; MIPS32: xor
-; MIPS32: sltu
-; MIPS32: andi {{.*}},0x1
-; MIPS32: move
-; MIPS32: jr
-; MIPS32: nop
-
-define internal i32 @icmp8BitMemSwapped(i32 %a, i32 %b_iptr) {
-entry:
- %a_8 = trunc i32 %a to i8
- %bptr = inttoptr i32 %b_iptr to i8*
- %b_8 = load i8, i8* %bptr, align 1
- %icmp = icmp ne i8 %a_8, %b_8
- %ret = zext i1 %icmp to i32
- ret i32 %ret
-}
-; CHECK-LABEL: icmp8BitMemSwapped
-; CHECK: cmp {{[abcd]l|BYTE PTR}}
-; MIPS32-LABEL: icmp8BitMemSwapped
-; MIPS32: lb
-; MIPS32: sll {{.*}},0x18
-; MIPS32: sll {{.*}},0x18
-; MIPS32: xor
-; MIPS32: sltu
-; MIPS32: andi {{.*}},0x1
-; MIPS32: move
-; MIPS32: jr
-; MIPS32: nop
-
-define internal i32 @selectI8Var(i32 %a, i32 %b) {
-entry:
- %a_8 = trunc i32 %a to i8
- %b_8 = trunc i32 %b to i8
- %cmp = icmp slt i8 %a_8, %b_8
- %ret = select i1 %cmp, i8 %a_8, i8 %b_8
- %ret_ext = zext i8 %ret to i32
- ; Create a "fake" use of %cmp to prevent O2 bool folding.
- %d1 = zext i1 %cmp to i32
- call void @useInt(i32 %d1)
- ret i32 %ret_ext
-}
-; CHECK-LABEL: selectI8Var
-; CHECK: cmp
-; CHECK: setl
-; CHECK: mov {{[a-d]l}}
-; MIPS32-LABEL: selectI8Var
-; MIPS32: addiu
-; MIPS32: sw
-; MIPS32: sw
-; MIPS32: move
-; MIPS32: move
-; MIPS32: sll {{.*}},0x18
-; MIPS32: sll {{.*}},0x18
-; MIPS32: slt
-; MIPS32: move
-; MIPS32: movn
-; MIPS32: andi {{.*}},0xff
-; MIPS32: move
-; MIPS32: andi {{.*}},0x1
-; MIPS32: move
-; MIPS32: jal
-; MIPS32: nop
-; MIPS32: move
-; MIPS32: lw
-; MIPS32: lw
-; MIPS32: addiu
-; MIPS32: jr
-; MIPS32: nop
-
-define internal i32 @testPhi8(i32 %arg, i32 %arg2, i32 %arg3, i32 %arg4, i32 %arg5, i32 %arg6, i32 %arg7, i32 %arg8, i32 %arg9, i32 %arg10) {
-entry:
- %trunc = trunc i32 %arg to i8
- %trunc2 = trunc i32 %arg2 to i8
- %trunc3 = trunc i32 %arg3 to i8
- %trunc4 = trunc i32 %arg4 to i8
- %trunc5 = trunc i32 %arg5 to i8
- %cmp1 = icmp sgt i32 %arg, 0
- br i1 %cmp1, label %next, label %target
-next:
- %trunc6_16 = trunc i32 %arg6 to i16
- %trunc7_16 = trunc i32 %arg7 to i16
- %trunc8_16 = trunc i32 %arg8 to i16
- %trunc9 = trunc i32 %arg9 to i8
- %trunc10 = trunc i32 %arg10 to i8
- %trunc7_8 = trunc i16 %trunc7_16 to i8
- %trunc6_8 = trunc i16 %trunc6_16 to i8
- %trunc8_8 = trunc i16 %trunc8_16 to i8
- br label %target
-target:
- %merge1 = phi i1 [ %cmp1, %entry ], [ false, %next ]
- %merge2 = phi i8 [ %trunc, %entry ], [ %trunc6_8, %next ]
- %merge3 = phi i8 [ %trunc2, %entry ], [ %trunc7_8, %next ]
- %merge5 = phi i8 [ %trunc4, %entry ], [ %trunc9, %next ]
- %merge6 = phi i8 [ %trunc5, %entry ], [ %trunc10, %next ]
- %merge4 = phi i8 [ %trunc3, %entry ], [ %trunc8_8, %next ]
- %res1 = select i1 %merge1, i8 %merge2, i8 %merge3
- %res2 = select i1 %merge1, i8 %merge4, i8 %merge5
- %res1_2 = select i1 %merge1, i8 %res1, i8 %res2
- %res123 = select i1 %merge1, i8 %merge6, i8 %res1_2
- %result = zext i8 %res123 to i32
- ret i32 %result
-}
-; CHECK-LABEL: testPhi8
-; This assumes there will be some copy from an 8-bit register / stack slot.
-; CHECK-DAG: mov {{.*}},{{[a-d]}}l
-; CHECK-DAG: mov {{.*}},BYTE PTR
-; CHECK-DAG: mov BYTE PTR {{.*}}
-
-@global8 = internal global [1 x i8] c"\01", align 4
-
-define i32 @load_i8(i32 %addr_arg) {
-entry:
- %addr = inttoptr i32 %addr_arg to i8*
- %ret = load i8, i8* %addr, align 1
- %ret2 = sub i8 %ret, 0
- %ret_ext = zext i8 %ret2 to i32
- ret i32 %ret_ext
-}
-; CHECK-LABEL: load_i8
-; CHECK: mov {{[a-d]l}},BYTE PTR
-; MIPS32-LABEL: load_i8
-; MIPS32: lb
-; MIPS32: addiu {{.*}},0
-; MIPS32: andi {{.*}},0xff
-; MIPS32: move
-; MIPS32: jr
-; MIPS32: nop
-
-define i32 @load_i8_global(i32 %addr_arg) {
-entry:
- %addr = bitcast [1 x i8]* @global8 to i8*
- %ret = load i8, i8* %addr, align 1
- %ret2 = sub i8 %ret, 0
- %ret_ext = zext i8 %ret2 to i32
- ret i32 %ret_ext
-}
-; CHECK-LABEL: load_i8_global
-; CHECK: mov {{[a-d]l}},{{(BYTE PTR)?}}
-; MIPS32-LABEL: load_i8_global
-; MIPS32: lui
-; MIPS32: addiu
-; MIPS32: lb
-; MIPS32: addiu {{.*}},0
-; MIPS32: andi {{.*}},0xff
-; MIPS32: jr
-; MIPS32: nop
-
-define void @store_i8(i32 %addr_arg, i32 %val) {
-entry:
- %val_trunc = trunc i32 %val to i8
- %addr = inttoptr i32 %addr_arg to i8*
- store i8 %val_trunc, i8* %addr, align 1
- ret void
-}
-; CHECK-LABEL: store_i8
-; CHECK: mov BYTE PTR {{.*}},{{[a-d]l}}
-; MIPS32-LABEL: store_i8
-; MIPS32: sb
-; MIPS32: jr
-; MIPS32: nop
-
-define void @store_i8_const(i32 %addr_arg) {
-entry:
- %addr = inttoptr i32 %addr_arg to i8*
- store i8 123, i8* %addr, align 1
- ret void
-}
-; CHECK-LABEL: store_i8_const
-; CHECK: mov BYTE PTR {{.*}},0x7b
-; MIPS32-LABEL: store_i8_const
-; MIPS32: li
-; MIPS32: sb
-; MIPS32: jr
-; MIPS32: nop
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/Input/no-terminator-inst.tbc b/third_party/subzero/tests_lit/llvm2ice_tests/Input/no-terminator-inst.tbc
deleted file mode 100644
index 112c372..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/Input/no-terminator-inst.tbc
+++ /dev/null
@@ -1,31 +0,0 @@
-65535,8,2;
-1,1;
-65535,17,2;
-1,4;
-7,32;
-2;
-21,0,0,0;
-7,1;
-65534;
-8,2,0,0,0;
-65535,19,2;
-5,0;
-65534;
-65535,14,2;
-1,0,102,105,98;
-65534;
-65535,12,2;
-1,3;
-65535,11,2;
-1,0;
-4,2;
-65534;
-28,2,1,36;
-11,1,2,1;
-10,2;
-2,3,2,1;
-34,0,5,1;
-2,1,5,0;
-65534;
-5534;
-65534;
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/Input/phi-invalid.tbc b/third_party/subzero/tests_lit/llvm2ice_tests/Input/phi-invalid.tbc
deleted file mode 100644
index bb9d59e..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/Input/phi-invalid.tbc
+++ /dev/null
@@ -1,55 +0,0 @@
-65535,8,2;
-1,1;
-65535,17,2;
-1,5;
-7,32;
-2;
-7,1;
-21,0,1;
-21,0,1,0;
-65534;
-8,3,0,0,0;
-8,4,0,0,0;
-65535,19,2;
-5,0;
-65534;
-65535,14,2;
-1,0,76,111,111,112,67,97,114,114,105,101,100,68,101,112;
-1,1,66,97,99,107,66,114,97,110,99,104;
-65534;
-65535,12,2;
-1,2;
-65535,11,2;
-1,0;
-4,2;
-4,4;
-65534;
-2,2,1,0;
-11,1;
-43,6,0;
-16,0,2,0,3,0;
-2,1,4,0;
-11,1;
-65534;
-65535,12,2;
-1,7;
-65535,11,2;
-1,2;
-4,3;
-65534;
-11,4;
-43,7,0;
-2,2,4294967293,0;
-11,6;
-43,8,0;
-2,3,4294967293,0;
-11,6;
-2,4,4294967295,0;
-11,6;
-2,5,5,0;
-11,1,5,5;
-2,1,6,0;
-11,2,3,6;
-10;
-65534;
-65534;
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/abi-atomics.ll b/third_party/subzero/tests_lit/llvm2ice_tests/abi-atomics.ll
deleted file mode 100644
index 1ab1397..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/abi-atomics.ll
+++ /dev/null
@@ -1,536 +0,0 @@
-; This file is copied/adapted from llvm/test/NaCl/PNaClABI/abi-atomics.ll .
-; TODO(stichnot): Find a way to share the file to avoid divergence.
-
-; REQUIRES: allow_dump
-
-; RUN: %p2i -i %s --args --verbose none --exit-success -threads=0 2>&1 \
-; RUN: | FileCheck %s
-
-declare i8 @llvm.nacl.atomic.load.i8(i8*, i32)
-declare i16 @llvm.nacl.atomic.load.i16(i16*, i32)
-declare i32 @llvm.nacl.atomic.load.i32(i32*, i32)
-declare i64 @llvm.nacl.atomic.load.i64(i64*, i32)
-declare void @llvm.nacl.atomic.store.i8(i8, i8*, i32)
-declare void @llvm.nacl.atomic.store.i16(i16, i16*, i32)
-declare void @llvm.nacl.atomic.store.i32(i32, i32*, i32)
-declare void @llvm.nacl.atomic.store.i64(i64, i64*, i32)
-declare i8 @llvm.nacl.atomic.rmw.i8(i32, i8*, i8, i32)
-declare i16 @llvm.nacl.atomic.rmw.i16(i32, i16*, i16, i32)
-declare i32 @llvm.nacl.atomic.rmw.i32(i32, i32*, i32, i32)
-declare i64 @llvm.nacl.atomic.rmw.i64(i32, i64*, i64, i32)
-declare i8 @llvm.nacl.atomic.cmpxchg.i8(i8*, i8, i8, i32, i32)
-declare i16 @llvm.nacl.atomic.cmpxchg.i16(i16*, i16, i16, i32, i32)
-declare i32 @llvm.nacl.atomic.cmpxchg.i32(i32*, i32, i32, i32, i32)
-declare i64 @llvm.nacl.atomic.cmpxchg.i64(i64*, i64, i64, i32, i32)
-declare void @llvm.nacl.atomic.fence(i32)
-declare void @llvm.nacl.atomic.fence.all()
-declare i1 @llvm.nacl.atomic.is.lock.free(i32, i8*)
-
-
-; Load
-
-define internal i32 @test_load_invalid_7() {
- %ptr = inttoptr i32 undef to i32*
- %1 = call i32 @llvm.nacl.atomic.load.i32(i32* %ptr, i32 7)
- ret i32 %1
-}
-; CHECK: test_load_invalid_7: Unexpected memory ordering for AtomicLoad
-
-define internal i32 @test_load_invalid_0() {
- %ptr = inttoptr i32 undef to i32*
- %1 = call i32 @llvm.nacl.atomic.load.i32(i32* %ptr, i32 0)
- ret i32 %1
-}
-; CHECK: test_load_invalid_0: Unexpected memory ordering for AtomicLoad
-
-define internal i32 @test_load_seqcst() {
- %ptr = inttoptr i32 undef to i32*
- %1 = call i32 @llvm.nacl.atomic.load.i32(i32* %ptr, i32 6)
- ret i32 %1
-}
-; CHECK-LABEL: test_load_seqcst
-
-define internal i32 @test_load_acqrel() {
- %ptr = inttoptr i32 undef to i32*
- %1 = call i32 @llvm.nacl.atomic.load.i32(i32* %ptr, i32 5)
- ret i32 %1
-}
-; CHECK: test_load_acqrel: Unexpected memory ordering for AtomicLoad
-
-define internal i32 @test_load_release() {
- %ptr = inttoptr i32 undef to i32*
- %1 = call i32 @llvm.nacl.atomic.load.i32(i32* %ptr, i32 4)
- ret i32 %1
-}
-; CHECK: test_load_release: Unexpected memory ordering for AtomicLoad
-
-define internal i32 @test_load_acquire() {
- %ptr = inttoptr i32 undef to i32*
- %1 = call i32 @llvm.nacl.atomic.load.i32(i32* %ptr, i32 3)
- ret i32 %1
-}
-; CHECK-LABEL: test_load_acquire
-
-define internal i32 @test_load_consume() {
- %ptr = inttoptr i32 undef to i32*
- %1 = call i32 @llvm.nacl.atomic.load.i32(i32* %ptr, i32 2)
- ret i32 %1
-}
-; CHECK: test_load_consume: Unexpected memory ordering for AtomicLoad
-
-define internal i32 @test_load_relaxed() {
- %ptr = inttoptr i32 undef to i32*
- %1 = call i32 @llvm.nacl.atomic.load.i32(i32* %ptr, i32 1)
- ret i32 %1
-}
-; CHECK: test_load_relaxed: Unexpected memory ordering for AtomicLoad
-
-
-; Store
-
-define internal void @test_store_invalid_7() {
- %ptr = inttoptr i32 undef to i32*
- call void @llvm.nacl.atomic.store.i32(i32 undef, i32* %ptr, i32 7)
- ret void
-}
-; CHECK: test_store_invalid_7: Unexpected memory ordering for AtomicStore
-
-define internal void @test_store_invalid_0() {
- %ptr = inttoptr i32 undef to i32*
- call void @llvm.nacl.atomic.store.i32(i32 undef, i32* %ptr, i32 0)
- ret void
-}
-; CHECK: test_store_invalid_0: Unexpected memory ordering for AtomicStore
-
-define internal void @test_store_seqcst() {
- %ptr = inttoptr i32 undef to i32*
- call void @llvm.nacl.atomic.store.i32(i32 undef, i32* %ptr, i32 6)
- ret void
-}
-; CHECK-LABEL: test_store_seqcst
-
-define internal void @test_store_acqrel() {
- %ptr = inttoptr i32 undef to i32*
- call void @llvm.nacl.atomic.store.i32(i32 undef, i32* %ptr, i32 5)
- ret void
-}
-; CHECK: test_store_acqrel: Unexpected memory ordering for AtomicStore
-
-define internal void @test_store_release() {
- %ptr = inttoptr i32 undef to i32*
- call void @llvm.nacl.atomic.store.i32(i32 undef, i32* %ptr, i32 4)
- ret void
-}
-; CHECK-LABEL: test_store_release
-
-define internal void @test_store_acquire() {
- %ptr = inttoptr i32 undef to i32*
- call void @llvm.nacl.atomic.store.i32(i32 undef, i32* %ptr, i32 3)
- ret void
-}
-; CHECK: test_store_acquire: Unexpected memory ordering for AtomicStore
-
-define internal void @test_store_consume() {
- %ptr = inttoptr i32 undef to i32*
- call void @llvm.nacl.atomic.store.i32(i32 undef, i32* %ptr, i32 2)
- ret void
-}
-; CHECK: test_store_consume: Unexpected memory ordering for AtomicStore
-
-define internal void @test_store_relaxed() {
- %ptr = inttoptr i32 undef to i32*
- call void @llvm.nacl.atomic.store.i32(i32 undef, i32* %ptr, i32 1)
- ret void
-}
-; CHECK: test_store_relaxed: Unexpected memory ordering for AtomicStore
-
-
-; rmw
-
-define internal i32 @test_rmw_invalid_7() {
- %ptr = inttoptr i32 undef to i32*
- %1 = call i32 @llvm.nacl.atomic.rmw.i32(i32 1, i32* %ptr, i32 0, i32 7)
- ret i32 %1
-}
-; CHECK: test_rmw_invalid_7: Unexpected memory ordering for AtomicRMW
-
-define internal i32 @test_rmw_invalid_0() {
- %ptr = inttoptr i32 undef to i32*
- %1 = call i32 @llvm.nacl.atomic.rmw.i32(i32 1, i32* %ptr, i32 0, i32 0)
- ret i32 %1
-}
-; CHECK: test_rmw_invalid_0: Unexpected memory ordering for AtomicRMW
-
-define internal i32 @test_rmw_seqcst() {
- %ptr = inttoptr i32 undef to i32*
- %1 = call i32 @llvm.nacl.atomic.rmw.i32(i32 1, i32* %ptr, i32 0, i32 6)
- ret i32 %1
-}
-; CHECK-LABEL: test_rmw_seqcst
-
-define internal i32 @test_rmw_acqrel() {
- %ptr = inttoptr i32 undef to i32*
- %1 = call i32 @llvm.nacl.atomic.rmw.i32(i32 1, i32* %ptr, i32 0, i32 5)
- ret i32 %1
-}
-; CHECK-LABEL: test_rmw_acqrel
-
-define internal i32 @test_rmw_release() {
- %ptr = inttoptr i32 undef to i32*
- %1 = call i32 @llvm.nacl.atomic.rmw.i32(i32 1, i32* %ptr, i32 0, i32 4)
- ret i32 %1
-}
-; CHECK-LABEL: test_rmw_release
-
-define internal i32 @test_rmw_acquire() {
- %ptr = inttoptr i32 undef to i32*
- %1 = call i32 @llvm.nacl.atomic.rmw.i32(i32 1, i32* %ptr, i32 0, i32 3)
- ret i32 %1
-}
-; CHECK-LABEL: test_rmw_acquire
-
-define internal i32 @test_rmw_consume() {
- %ptr = inttoptr i32 undef to i32*
- %1 = call i32 @llvm.nacl.atomic.rmw.i32(i32 1, i32* %ptr, i32 0, i32 2)
- ret i32 %1
-}
-; CHECK: test_rmw_consume: Unexpected memory ordering for AtomicRMW
-
-define internal i32 @test_rmw_relaxed() {
- %ptr = inttoptr i32 undef to i32*
- %1 = call i32 @llvm.nacl.atomic.rmw.i32(i32 1, i32* %ptr, i32 0, i32 1)
- ret i32 %1
-}
-; CHECK: test_rmw_relaxed: Unexpected memory ordering for AtomicRMW
-
-
-; cmpxchg
-
-define internal i32 @test_cmpxchg_invalid_7(i32 %oldval, i32 %newval) {
- %ptr = inttoptr i32 undef to i32*
- %1 = call i32 @llvm.nacl.atomic.cmpxchg.i32(i32* %ptr, i32 %oldval, i32 %newval, i32 7, i32 7)
- ret i32 %1
-}
-; CHECK: test_cmpxchg_invalid_7: Unexpected memory ordering for AtomicCmpxchg
-
-define internal i32 @test_cmpxchg_invalid_0(i32 %oldval, i32 %newval) {
- %ptr = inttoptr i32 undef to i32*
- %1 = call i32 @llvm.nacl.atomic.cmpxchg.i32(i32* %ptr, i32 %oldval, i32 %newval, i32 0, i32 0)
- ret i32 %1
-}
-; CHECK: test_cmpxchg_invalid_0: Unexpected memory ordering for AtomicCmpxchg
-
-; seq_cst
-
-define internal i32 @test_cmpxchg_seqcst_seqcst(i32 %oldval, i32 %newval) {
- %ptr = inttoptr i32 undef to i32*
- %1 = call i32 @llvm.nacl.atomic.cmpxchg.i32(i32* %ptr, i32 %oldval, i32 %newval, i32 6, i32 6)
- ret i32 %1
-}
-; CHECK-LABEL: test_cmpxchg_seqcst_seqcst
-
-define internal i32 @test_cmpxchg_seqcst_acqrel(i32 %oldval, i32 %newval) {
- %ptr = inttoptr i32 undef to i32*
- %1 = call i32 @llvm.nacl.atomic.cmpxchg.i32(i32* %ptr, i32 %oldval, i32 %newval, i32 6, i32 5)
- ret i32 %1
-}
-; CHECK: test_cmpxchg_seqcst_acqrel: Unexpected memory ordering for AtomicCmpxchg
-
-define internal i32 @test_cmpxchg_seqcst_release(i32 %oldval, i32 %newval) {
- %ptr = inttoptr i32 undef to i32*
- %1 = call i32 @llvm.nacl.atomic.cmpxchg.i32(i32* %ptr, i32 %oldval, i32 %newval, i32 6, i32 4)
- ret i32 %1
-}
-; CHECK: test_cmpxchg_seqcst_release: Unexpected memory ordering for AtomicCmpxchg
-
-define internal i32 @test_cmpxchg_seqcst_acquire(i32 %oldval, i32 %newval) {
- %ptr = inttoptr i32 undef to i32*
- %1 = call i32 @llvm.nacl.atomic.cmpxchg.i32(i32* %ptr, i32 %oldval, i32 %newval, i32 6, i32 3)
- ret i32 %1
-}
-; CHECK-LABEL: test_cmpxchg_seqcst_acquire
-
-define internal i32 @test_cmpxchg_seqcst_consume(i32 %oldval, i32 %newval) {
- %ptr = inttoptr i32 undef to i32*
- %1 = call i32 @llvm.nacl.atomic.cmpxchg.i32(i32* %ptr, i32 %oldval, i32 %newval, i32 6, i32 2)
- ret i32 %1
-}
-; CHECK: test_cmpxchg_seqcst_consume: Unexpected memory ordering for AtomicCmpxchg
-
-define internal i32 @test_cmpxchg_seqcst_relaxed(i32 %oldval, i32 %newval) {
- %ptr = inttoptr i32 undef to i32*
- %1 = call i32 @llvm.nacl.atomic.cmpxchg.i32(i32* %ptr, i32 %oldval, i32 %newval, i32 6, i32 1)
- ret i32 %1
-}
-; CHECK: test_cmpxchg_seqcst_relaxed: Unexpected memory ordering for AtomicCmpxchg
-
-; acq_rel
-
-define internal i32 @test_cmpxchg_acqrel_seqcst(i32 %oldval, i32 %newval) {
- %ptr = inttoptr i32 undef to i32*
- %1 = call i32 @llvm.nacl.atomic.cmpxchg.i32(i32* %ptr, i32 %oldval, i32 %newval, i32 5, i32 6)
- ret i32 %1
-}
-; CHECK: test_cmpxchg_acqrel_seqcst: Unexpected memory ordering for AtomicCmpxchg
-
-define internal i32 @test_cmpxchg_acqrel_acqrel(i32 %oldval, i32 %newval) {
- %ptr = inttoptr i32 undef to i32*
- %1 = call i32 @llvm.nacl.atomic.cmpxchg.i32(i32* %ptr, i32 %oldval, i32 %newval, i32 5, i32 5)
- ret i32 %1
-}
-; CHECK: test_cmpxchg_acqrel_acqrel: Unexpected memory ordering for AtomicCmpxchg
-
-define internal i32 @test_cmpxchg_acqrel_release(i32 %oldval, i32 %newval) {
- %ptr = inttoptr i32 undef to i32*
- %1 = call i32 @llvm.nacl.atomic.cmpxchg.i32(i32* %ptr, i32 %oldval, i32 %newval, i32 5, i32 4)
- ret i32 %1
-}
-; CHECK: test_cmpxchg_acqrel_release: Unexpected memory ordering for AtomicCmpxchg
-
-define internal i32 @test_cmpxchg_acqrel_acquire(i32 %oldval, i32 %newval) {
- %ptr = inttoptr i32 undef to i32*
- %1 = call i32 @llvm.nacl.atomic.cmpxchg.i32(i32* %ptr, i32 %oldval, i32 %newval, i32 5, i32 3)
- ret i32 %1
-}
-; CHECK-LABEL: test_cmpxchg_acqrel_acquire
-
-define internal i32 @test_cmpxchg_acqrel_consume(i32 %oldval, i32 %newval) {
- %ptr = inttoptr i32 undef to i32*
- %1 = call i32 @llvm.nacl.atomic.cmpxchg.i32(i32* %ptr, i32 %oldval, i32 %newval, i32 5, i32 2)
- ret i32 %1
-}
-; CHECK: test_cmpxchg_acqrel_consume: Unexpected memory ordering for AtomicCmpxchg
-
-define internal i32 @test_cmpxchg_acqrel_relaxed(i32 %oldval, i32 %newval) {
- %ptr = inttoptr i32 undef to i32*
- %1 = call i32 @llvm.nacl.atomic.cmpxchg.i32(i32* %ptr, i32 %oldval, i32 %newval, i32 5, i32 1)
- ret i32 %1
-}
-; CHECK: test_cmpxchg_acqrel_relaxed: Unexpected memory ordering for AtomicCmpxchg
-
-; release
-
-define internal i32 @test_cmpxchg_release_seqcst(i32 %oldval, i32 %newval) {
- %ptr = inttoptr i32 undef to i32*
- %1 = call i32 @llvm.nacl.atomic.cmpxchg.i32(i32* %ptr, i32 %oldval, i32 %newval, i32 4, i32 6)
- ret i32 %1
-}
-; CHECK: test_cmpxchg_release_seqcst: Unexpected memory ordering for AtomicCmpxchg
-
-define internal i32 @test_cmpxchg_release_acqrel(i32 %oldval, i32 %newval) {
- %ptr = inttoptr i32 undef to i32*
- %1 = call i32 @llvm.nacl.atomic.cmpxchg.i32(i32* %ptr, i32 %oldval, i32 %newval, i32 4, i32 5)
- ret i32 %1
-}
-; CHECK: test_cmpxchg_release_acqrel: Unexpected memory ordering for AtomicCmpxchg
-
-define internal i32 @test_cmpxchg_release_release(i32 %oldval, i32 %newval) {
- %ptr = inttoptr i32 undef to i32*
- %1 = call i32 @llvm.nacl.atomic.cmpxchg.i32(i32* %ptr, i32 %oldval, i32 %newval, i32 4, i32 4)
- ret i32 %1
-}
-; CHECK: test_cmpxchg_release_release: Unexpected memory ordering for AtomicCmpxchg
-
-define internal i32 @test_cmpxchg_release_acquire(i32 %oldval, i32 %newval) {
- %ptr = inttoptr i32 undef to i32*
- %1 = call i32 @llvm.nacl.atomic.cmpxchg.i32(i32* %ptr, i32 %oldval, i32 %newval, i32 4, i32 3)
- ret i32 %1
-}
-; CHECK: test_cmpxchg_release_acquire: Unexpected memory ordering for AtomicCmpxchg
-
-define internal i32 @test_cmpxchg_release_consume(i32 %oldval, i32 %newval) {
- %ptr = inttoptr i32 undef to i32*
- %1 = call i32 @llvm.nacl.atomic.cmpxchg.i32(i32* %ptr, i32 %oldval, i32 %newval, i32 4, i32 2)
- ret i32 %1
-}
-; CHECK: test_cmpxchg_release_consume: Unexpected memory ordering for AtomicCmpxchg
-
-define internal i32 @test_cmpxchg_release_relaxed(i32 %oldval, i32 %newval) {
- %ptr = inttoptr i32 undef to i32*
- %1 = call i32 @llvm.nacl.atomic.cmpxchg.i32(i32* %ptr, i32 %oldval, i32 %newval, i32 4, i32 1)
- ret i32 %1
-}
-; CHECK: test_cmpxchg_release_relaxed: Unexpected memory ordering for AtomicCmpxchg
-
-; acquire
-
-define internal i32 @test_cmpxchg_acquire_seqcst(i32 %oldval, i32 %newval) {
- %ptr = inttoptr i32 undef to i32*
- %1 = call i32 @llvm.nacl.atomic.cmpxchg.i32(i32* %ptr, i32 %oldval, i32 %newval, i32 3, i32 6)
- ret i32 %1
-}
-; CHECK: test_cmpxchg_acquire_seqcst: Unexpected memory ordering for AtomicCmpxchg
-
-define internal i32 @test_cmpxchg_acquire_acqrel(i32 %oldval, i32 %newval) {
- %ptr = inttoptr i32 undef to i32*
- %1 = call i32 @llvm.nacl.atomic.cmpxchg.i32(i32* %ptr, i32 %oldval, i32 %newval, i32 3, i32 5)
- ret i32 %1
-}
-; CHECK: test_cmpxchg_acquire_acqrel: Unexpected memory ordering for AtomicCmpxchg
-
-define internal i32 @test_cmpxchg_acquire_release(i32 %oldval, i32 %newval) {
- %ptr = inttoptr i32 undef to i32*
- %1 = call i32 @llvm.nacl.atomic.cmpxchg.i32(i32* %ptr, i32 %oldval, i32 %newval, i32 3, i32 4)
- ret i32 %1
-}
-; CHECK: test_cmpxchg_acquire_release: Unexpected memory ordering for AtomicCmpxchg
-
-define internal i32 @test_cmpxchg_acquire_acquire(i32 %oldval, i32 %newval) {
- %ptr = inttoptr i32 undef to i32*
- %1 = call i32 @llvm.nacl.atomic.cmpxchg.i32(i32* %ptr, i32 %oldval, i32 %newval, i32 3, i32 3)
- ret i32 %1
-}
-; CHECK-LABEL: test_cmpxchg_acquire_acquire
-
-define internal i32 @test_cmpxchg_acquire_consume(i32 %oldval, i32 %newval) {
- %ptr = inttoptr i32 undef to i32*
- %1 = call i32 @llvm.nacl.atomic.cmpxchg.i32(i32* %ptr, i32 %oldval, i32 %newval, i32 3, i32 2)
- ret i32 %1
-}
-; CHECK: test_cmpxchg_acquire_consume: Unexpected memory ordering for AtomicCmpxchg
-
-define internal i32 @test_cmpxchg_acquire_relaxed(i32 %oldval, i32 %newval) {
- %ptr = inttoptr i32 undef to i32*
- %1 = call i32 @llvm.nacl.atomic.cmpxchg.i32(i32* %ptr, i32 %oldval, i32 %newval, i32 3, i32 1)
- ret i32 %1
-}
-; CHECK: test_cmpxchg_acquire_relaxed: Unexpected memory ordering for AtomicCmpxchg
-
-; consume
-
-define internal i32 @test_cmpxchg_consume_seqcst(i32 %oldval, i32 %newval) {
- %ptr = inttoptr i32 undef to i32*
- %1 = call i32 @llvm.nacl.atomic.cmpxchg.i32(i32* %ptr, i32 %oldval, i32 %newval, i32 2, i32 6)
- ret i32 %1
-}
-; CHECK: test_cmpxchg_consume_seqcst: Unexpected memory ordering for AtomicCmpxchg
-
-define internal i32 @test_cmpxchg_consume_acqrel(i32 %oldval, i32 %newval) {
- %ptr = inttoptr i32 undef to i32*
- %1 = call i32 @llvm.nacl.atomic.cmpxchg.i32(i32* %ptr, i32 %oldval, i32 %newval, i32 2, i32 5)
- ret i32 %1
-}
-; CHECK: test_cmpxchg_consume_acqrel: Unexpected memory ordering for AtomicCmpxchg
-
-define internal i32 @test_cmpxchg_consume_release(i32 %oldval, i32 %newval) {
- %ptr = inttoptr i32 undef to i32*
- %1 = call i32 @llvm.nacl.atomic.cmpxchg.i32(i32* %ptr, i32 %oldval, i32 %newval, i32 2, i32 4)
- ret i32 %1
-}
-; CHECK: test_cmpxchg_consume_release: Unexpected memory ordering for AtomicCmpxchg
-
-define internal i32 @test_cmpxchg_consume_acquire(i32 %oldval, i32 %newval) {
- %ptr = inttoptr i32 undef to i32*
- %1 = call i32 @llvm.nacl.atomic.cmpxchg.i32(i32* %ptr, i32 %oldval, i32 %newval, i32 2, i32 3)
- ret i32 %1
-}
-; CHECK: test_cmpxchg_consume_acquire: Unexpected memory ordering for AtomicCmpxchg
-
-define internal i32 @test_cmpxchg_consume_consume(i32 %oldval, i32 %newval) {
- %ptr = inttoptr i32 undef to i32*
- %1 = call i32 @llvm.nacl.atomic.cmpxchg.i32(i32* %ptr, i32 %oldval, i32 %newval, i32 2, i32 2)
- ret i32 %1
-}
-; CHECK: test_cmpxchg_consume_consume: Unexpected memory ordering for AtomicCmpxchg
-
-define internal i32 @test_cmpxchg_consume_relaxed(i32 %oldval, i32 %newval) {
- %ptr = inttoptr i32 undef to i32*
- %1 = call i32 @llvm.nacl.atomic.cmpxchg.i32(i32* %ptr, i32 %oldval, i32 %newval, i32 2, i32 1)
- ret i32 %1
-}
-; CHECK: test_cmpxchg_consume_relaxed: Unexpected memory ordering for AtomicCmpxchg
-
-; relaxed
-
-define internal i32 @test_cmpxchg_relaxed_seqcst(i32 %oldval, i32 %newval) {
- %ptr = inttoptr i32 undef to i32*
- %1 = call i32 @llvm.nacl.atomic.cmpxchg.i32(i32* %ptr, i32 %oldval, i32 %newval, i32 1, i32 6)
- ret i32 %1
-}
-; CHECK: test_cmpxchg_relaxed_seqcst: Unexpected memory ordering for AtomicCmpxchg
-
-define internal i32 @test_cmpxchg_relaxed_acqrel(i32 %oldval, i32 %newval) {
- %ptr = inttoptr i32 undef to i32*
- %1 = call i32 @llvm.nacl.atomic.cmpxchg.i32(i32* %ptr, i32 %oldval, i32 %newval, i32 1, i32 5)
- ret i32 %1
-}
-; CHECK: test_cmpxchg_relaxed_acqrel: Unexpected memory ordering for AtomicCmpxchg
-
-define internal i32 @test_cmpxchg_relaxed_release(i32 %oldval, i32 %newval) {
- %ptr = inttoptr i32 undef to i32*
- %1 = call i32 @llvm.nacl.atomic.cmpxchg.i32(i32* %ptr, i32 %oldval, i32 %newval, i32 1, i32 4)
- ret i32 %1
-}
-; CHECK: test_cmpxchg_relaxed_release: Unexpected memory ordering for AtomicCmpxchg
-
-define internal i32 @test_cmpxchg_relaxed_acquire(i32 %oldval, i32 %newval) {
- %ptr = inttoptr i32 undef to i32*
- %1 = call i32 @llvm.nacl.atomic.cmpxchg.i32(i32* %ptr, i32 %oldval, i32 %newval, i32 1, i32 3)
- ret i32 %1
-}
-; CHECK: test_cmpxchg_relaxed_acquire: Unexpected memory ordering for AtomicCmpxchg
-
-define internal i32 @test_cmpxchg_relaxed_consume(i32 %oldval, i32 %newval) {
- %ptr = inttoptr i32 undef to i32*
- %1 = call i32 @llvm.nacl.atomic.cmpxchg.i32(i32* %ptr, i32 %oldval, i32 %newval, i32 1, i32 2)
- ret i32 %1
-}
-; CHECK: test_cmpxchg_relaxed_consume: Unexpected memory ordering for AtomicCmpxchg
-
-define internal i32 @test_cmpxchg_relaxed_relaxed(i32 %oldval, i32 %newval) {
- %ptr = inttoptr i32 undef to i32*
- %1 = call i32 @llvm.nacl.atomic.cmpxchg.i32(i32* %ptr, i32 %oldval, i32 %newval, i32 1, i32 1)
- ret i32 %1
-}
-; CHECK: test_cmpxchg_relaxed_relaxed: Unexpected memory ordering for AtomicCmpxchg
-
-
-; fence
-
-define internal void @test_fence_invalid_7() {
- call void @llvm.nacl.atomic.fence(i32 7)
- ret void
-}
-; CHECK: test_fence_invalid_7: Unexpected memory ordering for AtomicFence
-
-define internal void @test_fence_invalid_0() {
- call void @llvm.nacl.atomic.fence(i32 0)
- ret void
-}
-; CHECK: test_fence_invalid_0: Unexpected memory ordering for AtomicFence
-
-define internal void @test_fence_seqcst() {
- call void @llvm.nacl.atomic.fence(i32 6)
- ret void
-}
-; CHECK-LABEL: test_fence_seqcst
-
-define internal void @test_fence_acqrel() {
- call void @llvm.nacl.atomic.fence(i32 5)
- ret void
-}
-; CHECK-LABEL: test_fence_acqrel
-
-define internal void @test_fence_acquire() {
- call void @llvm.nacl.atomic.fence(i32 4)
- ret void
-}
-; CHECK-LABEL: test_fence_acquire
-
-define internal void @test_fence_release() {
- call void @llvm.nacl.atomic.fence(i32 3)
- ret void
-}
-; CHECK-LABEL: test_fence_release
-
-define internal void @test_fence_consume() {
- call void @llvm.nacl.atomic.fence(i32 2)
- ret void
-}
-; CHECK: test_fence_consume: Unexpected memory ordering for AtomicFence
-
-define internal void @test_fence_relaxed() {
- call void @llvm.nacl.atomic.fence(i32 1)
- ret void
-}
-; CHECK: test_fence_relaxed: Unexpected memory ordering for AtomicFence
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/addr-opt-multi-def-var.ll b/third_party/subzero/tests_lit/llvm2ice_tests/addr-opt-multi-def-var.ll
deleted file mode 100644
index 401359a..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/addr-opt-multi-def-var.ll
+++ /dev/null
@@ -1,69 +0,0 @@
-; This is distilled from a real function that led to a bug in the
-; address mode optimization code. It followed assignment chains
-; through non-SSA temporaries created from Phi instruction lowering.
-;
-; This test depends to some degree on the stability of "--verbose
-; addropt" output format.
-
-; REQUIRES: target_X8632
-; REQUIRES: allow_dump
-; RUN: %p2i -i %s --args -O2 --verbose addropt \
-; RUN: -allow-externally-defined-symbols | FileCheck %s
-
-declare i32 @_calloc_r(i32, i32, i32)
-
-define internal i32 @_Balloc(i32 %ptr, i32 %k) {
-entry:
- %gep = add i32 %ptr, 76
- %gep.asptr = inttoptr i32 %gep to i32*
- %0 = load i32, i32* %gep.asptr, align 1
- %cmp = icmp eq i32 %0, 0
- br i1 %cmp, label %if.then, label %if.end5
-
-if.then: ; preds = %entry
- %call = tail call i32 @_calloc_r(i32 %ptr, i32 4, i32 33)
- %gep.asptr2 = inttoptr i32 %gep to i32*
- store i32 %call, i32* %gep.asptr2, align 1
- %cmp3 = icmp eq i32 %call, 0
- br i1 %cmp3, label %return, label %if.end5
-
-if.end5: ; preds = %if.then, %entry
- %1 = phi i32 [ %call, %if.then ], [ %0, %entry ]
- %gep_array = mul i32 %k, 4
- %gep2 = add i32 %1, %gep_array
- %gep2.asptr = inttoptr i32 %gep2 to i32*
- %2 = load i32, i32* %gep2.asptr, align 1
-; The above load instruction is a good target for address mode
-; optimization. Correct analysis would lead to dump output like:
-; Starting computeAddressOpt for instruction:
-; [ 15] %__13 = load i32, i32* %gep2.asptr, align 1
-; Instruction: [ 14] %gep2.asptr = i32 %gep2
-; results in Base=%gep2, Index=<null>, Shift=0, Offset=0
-; Instruction: [ 13] %gep2 = add i32 %__9, %gep_array
-; results in Base=%__9, Index=%gep_array, Shift=0, Offset=0
-; Instruction: [ 18] %__9 = i32 %__9_phi
-; results in Base=%__9_phi, Index=%gep_array, Shift=0, Offset=0
-; Instruction: [ 12] %gep_array = mul i32 %k, 4
-; results in Base=%__9_phi, Index=%k, Shift=2, Offset=0
-;
-; Incorrect, overly-aggressive analysis would lead to output like:
-; Starting computeAddressOpt for instruction:
-; [ 15] %__13 = load i32, i32* %gep2.asptr, align 1
-; Instruction: [ 14] %gep2.asptr = i32 %gep2
-; results in Base=%gep2, Index=<null>, Shift=0, Offset=0
-; Instruction: [ 13] %gep2 = add i32 %__9, %gep_array
-; results in Base=%__9, Index=%gep_array, Shift=0, Offset=0
-; Instruction: [ 18] %__9 = i32 %__9_phi
-; results in Base=%__9_phi, Index=%gep_array, Shift=0, Offset=0
-; Instruction: [ 19] %__9_phi = i32 %__4
-; results in Base=%__4, Index=%gep_array, Shift=0, Offset=0
-; Instruction: [ 12] %gep_array = mul i32 %k, 4
-; results in Base=%__4, Index=%k, Shift=2, Offset=0
-;
-; CHECK-NOT: results in Base=%__4,
-;
- ret i32 %2
-
-return: ; preds = %if.then
- ret i32 0
-}
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/address-mode-global.ll b/third_party/subzero/tests_lit/llvm2ice_tests/address-mode-global.ll
deleted file mode 100644
index a592648..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/address-mode-global.ll
+++ /dev/null
@@ -1,35 +0,0 @@
-; This file checks support for address mode optimization.
-
-; RUN: %p2i --filetype=obj --disassemble -i %s --args -O2 \
-; RUN: -allow-externally-defined-symbols | FileCheck %s
-
-@bytes = internal global [1024 x i8] zeroinitializer
-
-define internal i32 @load_global_direct() {
-entry:
- %base = ptrtoint [1024 x i8]* @bytes to i32
- %addr_lo.int = add i32 0, %base
- %addr_hi.int = add i32 4, %base
- %addr_lo.ptr = inttoptr i32 %addr_lo.int to i32*
- %addr_hi.ptr = inttoptr i32 %addr_hi.int to i32*
- %addr_lo.load = load i32, i32* %addr_lo.ptr, align 1
- %addr_hi.load = load i32, i32* %addr_hi.ptr, align 1
- %result = add i32 %addr_lo.load, %addr_hi.load
- ret i32 %result
-; CHECK-LABEL: load_global_direct
-; CHECK-NEXT: mov eax,{{(DWORD PTR )?}}ds:0x0{{.*}}{{bytes|.bss}}
-; CHECK-NEXT: add eax,DWORD PTR ds:0x4{{.*}}{{bytes|.bss}}
-}
-
-define internal i32 @load_global_indexed(i32 %arg) {
-entry:
- %offset = shl i32 %arg, 3
- %base = ptrtoint [1024 x i8]* @bytes to i32
- %addr.int = add i32 %offset, %base
- %addr.ptr = inttoptr i32 %addr.int to i32*
- %addr.load = load i32, i32* %addr.ptr, align 1
- ret i32 %addr.load
-; CHECK-LABEL: load_global_indexed
-; CHECK-NEXT: mov eax,DWORD PTR [esp+0x4]
-; CHECK-NEXT: mov eax,DWORD PTR [eax*8+0x0]
-}
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/address-mode-opt.ll b/third_party/subzero/tests_lit/llvm2ice_tests/address-mode-opt.ll
deleted file mode 100644
index fd15998..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/address-mode-opt.ll
+++ /dev/null
@@ -1,206 +0,0 @@
-; This file checks support for address mode optimization.
-
-; RUN: %p2i --filetype=obj --disassemble -i %s --args -O2 \
-; RUN: -allow-externally-defined-symbols | FileCheck %s
-; RUN: %p2i --filetype=obj --disassemble -i %s --args -O2 -mattr=sse4.1 \
-; RUN: -allow-externally-defined-symbols | FileCheck --check-prefix=SSE41 %s
-
-define internal float @load_arg_plus_200000(float* %arg) {
-entry:
- %arg.int = ptrtoint float* %arg to i32
- %addr.int = add i32 %arg.int, 200000
- %addr.ptr = inttoptr i32 %addr.int to float*
- %addr.load = load float, float* %addr.ptr, align 4
- ret float %addr.load
-; CHECK-LABEL: load_arg_plus_200000
-; CHECK: movss xmm0,DWORD PTR [eax+0x30d40]
-}
-
-define internal float @load_200000_plus_arg(float* %arg) {
-entry:
- %arg.int = ptrtoint float* %arg to i32
- %addr.int = add i32 200000, %arg.int
- %addr.ptr = inttoptr i32 %addr.int to float*
- %addr.load = load float, float* %addr.ptr, align 4
- ret float %addr.load
-; CHECK-LABEL: load_200000_plus_arg
-; CHECK: movss xmm0,DWORD PTR [eax+0x30d40]
-}
-
-define internal float @load_arg_minus_200000(float* %arg) {
-entry:
- %arg.int = ptrtoint float* %arg to i32
- %addr.int = sub i32 %arg.int, 200000
- %addr.ptr = inttoptr i32 %addr.int to float*
- %addr.load = load float, float* %addr.ptr, align 4
- ret float %addr.load
-; CHECK-LABEL: load_arg_minus_200000
-; CHECK: movss xmm0,DWORD PTR [eax-0x30d40]
-}
-
-define internal float @load_200000_minus_arg(float* %arg) {
-entry:
- %arg.int = ptrtoint float* %arg to i32
- %addr.int = sub i32 200000, %arg.int
- %addr.ptr = inttoptr i32 %addr.int to float*
- %addr.load = load float, float* %addr.ptr, align 4
- ret float %addr.load
-; CHECK-LABEL: load_200000_minus_arg
-; CHECK: movss xmm0,DWORD PTR [e{{..}}]
-}
-
-define internal <8 x i16> @load_mul_v8i16_mem(<8 x i16> %arg0, i32 %arg1_iptr) {
-entry:
- %addr_sub = sub i32 %arg1_iptr, 200000
- %addr_ptr = inttoptr i32 %addr_sub to <8 x i16>*
- %arg1 = load <8 x i16>, <8 x i16>* %addr_ptr, align 2
- %res_vec = mul <8 x i16> %arg0, %arg1
- ret <8 x i16> %res_vec
-; Address mode optimization is generally unsafe for SSE vector instructions.
-; CHECK-LABEL: load_mul_v8i16_mem
-; CHECK-NOT: pmullw xmm{{.*}},XMMWORD PTR [e{{..}}-0x30d40]
-}
-
-define internal <4 x i32> @load_mul_v4i32_mem(<4 x i32> %arg0, i32 %arg1_iptr) {
-entry:
- %addr_sub = sub i32 %arg1_iptr, 200000
- %addr_ptr = inttoptr i32 %addr_sub to <4 x i32>*
- %arg1 = load <4 x i32>, <4 x i32>* %addr_ptr, align 4
- %res = mul <4 x i32> %arg0, %arg1
- ret <4 x i32> %res
-; Address mode optimization is generally unsafe for SSE vector instructions.
-; CHECK-LABEL: load_mul_v4i32_mem
-; CHECK-NOT: pmuludq xmm{{.*}},XMMWORD PTR [e{{..}}-0x30d40]
-; CHECK: pmuludq
-;
-; SSE41-LABEL: load_mul_v4i32_mem
-; SSE41-NOT: pmulld xmm{{.*}},XMMWORD PTR [e{{..}}-0x30d40]
-}
-
-define internal float @address_mode_opt_chaining(float* %arg) {
-entry:
- %arg.int = ptrtoint float* %arg to i32
- %addr1.int = add i32 12, %arg.int
- %addr2.int = sub i32 %addr1.int, 4
- %addr2.ptr = inttoptr i32 %addr2.int to float*
- %addr2.load = load float, float* %addr2.ptr, align 4
- ret float %addr2.load
-; CHECK-LABEL: address_mode_opt_chaining
-; CHECK: movss xmm0,DWORD PTR [eax+0x8]
-}
-
-define internal float @address_mode_opt_chaining_overflow(float* %arg) {
-entry:
- %arg.int = ptrtoint float* %arg to i32
- %addr1.int = add i32 2147483640, %arg.int
- %addr2.int = add i32 %addr1.int, 2147483643
- %addr2.ptr = inttoptr i32 %addr2.int to float*
- %addr2.load = load float, float* %addr2.ptr, align 4
- ret float %addr2.load
-; CHECK-LABEL: address_mode_opt_chaining_overflow
-; CHECK: 0x7ffffff8
-; CHECK: movss xmm0,DWORD PTR [{{.*}}+0x7ffffffb]
-}
-
-define internal float @address_mode_opt_chaining_overflow_sub(float* %arg) {
-entry:
- %arg.int = ptrtoint float* %arg to i32
- %addr1.int = sub i32 %arg.int, 2147483640
- %addr2.int = sub i32 %addr1.int, 2147483643
- %addr2.ptr = inttoptr i32 %addr2.int to float*
- %addr2.load = load float, float* %addr2.ptr, align 4
- ret float %addr2.load
-; CHECK-LABEL: address_mode_opt_chaining_overflow_sub
-; CHECK: 0x7ffffff8
-; CHECK: movss xmm0,DWORD PTR [{{.*}}-0x7ffffffb]
-}
-
-define internal float @address_mode_opt_chaining_no_overflow(float* %arg) {
-entry:
- %arg.int = ptrtoint float* %arg to i32
- %addr1.int = sub i32 %arg.int, 2147483640
- %addr2.int = add i32 %addr1.int, 2147483643
- %addr2.ptr = inttoptr i32 %addr2.int to float*
- %addr2.load = load float, float* %addr2.ptr, align 4
- ret float %addr2.load
-; CHECK-LABEL: address_mode_opt_chaining_no_overflow
-; CHECK: movss xmm0,DWORD PTR [{{.*}}+0x3]
-}
-
-define internal float @address_mode_opt_add_pos_min_int(float* %arg) {
-entry:
- %arg.int = ptrtoint float* %arg to i32
- %addr1.int = add i32 %arg.int, 2147483648
- %addr1.ptr = inttoptr i32 %addr1.int to float*
- %addr1.load = load float, float* %addr1.ptr, align 4
- ret float %addr1.load
-; CHECK-LABEL: address_mode_opt_add_pos_min_int
-; CHECK: movss xmm0,DWORD PTR [{{.*}}-0x80000000]
-}
-
-define internal float @address_mode_opt_sub_min_int(float* %arg) {
-entry:
- %arg.int = ptrtoint float* %arg to i32
- %addr1.int = sub i32 %arg.int, 2147483648
- %addr1.ptr = inttoptr i32 %addr1.int to float*
- %addr1.load = load float, float* %addr1.ptr, align 4
- ret float %addr1.load
-; CHECK-LABEL: address_mode_opt_sub_min_int
-; CHECK: movss xmm0,DWORD PTR [{{.*}}-0x80000000]
-}
-
-define internal float @load_1_or__2_shl_arg(float* %arg) {
-entry:
- %arg.int = ptrtoint float* %arg to i32
- %shl1 = shl i32 %arg.int, 2
- %addr.int = or i32 1, %shl1
- %addr.ptr = inttoptr i32 %addr.int to float*
- %addr.load = load float, float* %addr.ptr, align 4
- ret float %addr.load
-; CHECK-LABEL: load_1_or__2_shl_arg
-; CHECK-NOT: or
-; CHECK: movss xmm{{[0-9]+}},DWORD PTR [{{e..}}*4+0x1]
-}
-
-define internal float @or_add_boundary_check_1(float* %arg) {
-entry:
- %arg.int = ptrtoint float* %arg to i32
- %shl1 = shl i32 %arg.int, 2
- %addr.int = or i32 5, %shl1
- %addr.ptr = inttoptr i32 %addr.int to float*
- %addr.load = load float, float* %addr.ptr, align 4
- ret float %addr.load
-; CHECK-LABEL: or_add_boundary_check_1
-; CHECK: or
-; CHECK-NOT: movss xmm{{[0-9]+}},DWORD PTR [{{e..}}*4+0x5]
-}
-
-define internal float @or_add_boundary_check_2(float* %arg) {
-entry:
- %arg.int = ptrtoint float* %arg to i32
- %shl1 = shl i32 %arg.int, 2
- %addr.int = or i32 -1, %shl1
- %addr.ptr = inttoptr i32 %addr.int to float*
- %addr.load = load float, float* %addr.ptr, align 4
- ret float %addr.load
-; CHECK-LABEL: or_add_boundary_check_2
-; CHECK: or
-; CHECK-NOT: movss xmm{{[0-9]+}},DWORD PTR [{{e..}}*4+0xFFFF]
-}
-
-define internal void @invert_icmp(i32* %arg1, i32* %arg2) {
-entry:
- %addr.other = load i32, i32* %arg2, align 1
- br label %next
-next:
- %addr.load = load i32, i32* %arg1, align 1
- %cond = icmp slt i32 %addr.load, %addr.other
- br i1 %cond, label %if.then, label %if.else
-if.then:
- ret void
-if.else:
- ret void
-; CHECK-LABEL: invert_icmp
-; CHECK: cmp {{e..}},DWORD PTR [{{e..}}]
-; CHECK: jle
-}
\ No newline at end of file
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/adv-switch-opt.ll b/third_party/subzero/tests_lit/llvm2ice_tests/adv-switch-opt.ll
deleted file mode 100644
index 60aa1ab..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/adv-switch-opt.ll
+++ /dev/null
@@ -1,321 +0,0 @@
-; This tests the advanced lowering of switch statements. The advanced lowering
-; uses jump tables, range tests and binary search.
-
-; RUN: %p2i -i %s --target=x8632 --filetype=obj --disassemble --args -O2 \
-; RUN: | FileCheck %s --check-prefix=CHECK --check-prefix=X8632
-; RUN: %p2i -i %s --target=x8664 --filetype=obj --disassemble --args -O2 \
-; RUN: | FileCheck %s --check-prefix=CHECK --check-prefix=X8664
-
-; RUN: %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command %p2i --filetype=asm --assemble --disassemble --target \
-; RUN: mips32 -i %s --args -O2 -allow-externally-defined-symbols \
-; RUN: | %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command FileCheck --check-prefix MIPS32 %s
-
-; Dense but non-continuous ranges should be converted into a jump table.
-define internal i32 @testJumpTable(i32 %a) {
-entry:
- switch i32 %a, label %sw.default [
- i32 91, label %sw.default
- i32 92, label %sw.bb1
- i32 93, label %sw.default
- i32 99, label %sw.bb1
- i32 98, label %sw.default
- i32 96, label %sw.bb1
- i32 97, label %sw.epilog
- ]
-
-sw.default:
- %add = add i32 %a, 27
- br label %sw.epilog
-
-sw.bb1:
- %tmp = add i32 %a, 16
- br label %sw.epilog
-
-sw.epilog:
- %result.1 = phi i32 [ %add, %sw.default ], [ %tmp, %sw.bb1 ], [ 17, %entry ]
- ret i32 %result.1
-}
-; CHECK-LABEL: testJumpTable
-; CHECK: sub [[IND:[^,]+]],0x5b
-; CHECK-NEXT: cmp [[IND]],0x8
-; CHECK-NEXT: ja
-; X8632-NEXT: mov [[TARGET:.*]],DWORD PTR {{\[}}[[IND]]*4+0x0] {{[0-9a-f]+}}: R_386_32 .{{.*}}testJumpTable$jumptable
-; X8632-NEXT: jmp [[TARGET]]
-; X8664-NEXT: mov {{.}}[[TARGET:.*]],DWORD PTR {{\[}}[[IND]]*4+0x0] {{[0-9a-f]+}}: R_X86_64_32S .{{.*}}testJumpTable$jumptable
-; X8664-NEXT: jmp {{.}}[[TARGET]]
-; Note: x86-32 may do "mov eax, [...]; jmp eax", whereas x86-64 may do
-; "mov eax, [...]; jmp rax", so we assume the all characters except the first
-; one in the register name will match.
-
-; MIPS32-LABEL: testJumpTable
-; MIPS32: move [[REG1:.*]],{{.*}}
-; MIPS32: li [[REG2:.*]],91
-; MIPS32: beq [[REG1]],[[REG2]],6c <.LtestJumpTable$sw.default>
-; MIPS32: nop
-; MIPS32: li [[REG2:.*]],92
-; MIPS32: beq [[REG1]],[[REG2]],78 <.LtestJumpTable$sw.bb1>
-; MIPS32: nop
-; MIPS32: li [[REG2:.*]],93
-; MIPS32: beq [[REG1]],[[REG2]],6c <.LtestJumpTable$sw.default>
-; MIPS32: nop
-; MIPS32: li [[REG2:.*]],99
-; MIPS32: beq [[REG1]],[[REG2]],78 <.LtestJumpTable$sw.bb1>
-; MIPS32: nop
-; MIPS32: li [[REG2:.*]],98
-; MIPS32: beq [[REG1]],[[REG2]],6c <.LtestJumpTable$sw.default>
-; MIPS32: nop
-; MIPS32: li [[REG2:.*]],96
-; MIPS32: beq [[REG1]],[[REG2]],78 <.LtestJumpTable$sw.bb1>
-; MIPS32: nop
-; MIPS32: li [[REG2:.*]],97
-; MIPS32: beq [[REG1]],[[REG2]],60 <.LtestJumpTable$split_entry_sw.epilog_0>
-; MIPS32: nop
-; MIPS32: b 6c <.LtestJumpTable$sw.default>
-; MIPS32: nop
-
-; Continuous ranges which map to the same target should be grouped and
-; efficiently tested.
-define internal i32 @testRangeTest() {
-entry:
- switch i32 10, label %sw.default [
- i32 0, label %sw.epilog
- i32 1, label %sw.epilog
- i32 2, label %sw.epilog
- i32 3, label %sw.epilog
- i32 10, label %sw.bb1
- i32 11, label %sw.bb1
- i32 12, label %sw.bb1
- i32 13, label %sw.bb1
- ]
-
-sw.default:
- br label %sw.epilog
-
-sw.bb1:
- br label %sw.epilog
-
-sw.epilog:
- %result.1 = phi i32 [ 23, %sw.default ], [ 42, %sw.bb1 ], [ 17, %entry ], [ 17, %entry ], [ 17, %entry ], [ 17, %entry ]
- ret i32 %result.1
-}
-; CHECK-LABEL: testRangeTest
-; CHECK: cmp {{.*}},0x3
-; CHECK-NEXT: jbe
-; CHECK: sub [[REG:[^,]*]],0xa
-; CHECK-NEXT: cmp [[REG]],0x3
-; CHECK-NEXT: jbe
-; CHECK-NEXT: jmp
-
-; MIPS32-LABEL: testRangeTest
-; MIPS32: li [[REG1:.*]],10
-; MIPS32: li [[REG2:.*]],0
-; MIPS32: beq [[REG1]],[[REG2]],114 <.LtestRangeTest$split_entry_sw.epilog_0>
-; MIPS32: nop
-; MIPS32: li [[REG2:.*]],1
-; MIPS32: beq [[REG1]],[[REG2]],114 <.LtestRangeTest$split_entry_sw.epilog_0>
-; MIPS32: nop
-; MIPS32: li [[REG2:.*]],2
-; MIPS32: beq [[REG1]],[[REG2]],114 <.LtestRangeTest$split_entry_sw.epilog_0>
-; MIPS32: nop
-; MIPS32: li [[REG2:.*]],3
-; MIPS32: beq [[REG1]],[[REG2]],114 <.LtestRangeTest$split_entry_sw.epilog_0>
-; MIPS32: nop
-; MIPS32: li [[REG2:.*]],10
-; MIPS32: beq [[REG1]],[[REG2]],fc <.LtestRangeTest$split_sw.bb1_sw.epilog_2>
-; MIPS32: nop
-; MIPS32: li [[REG2:.*]],11
-; MIPS32: beq [[REG1]],[[REG2]],fc <.LtestRangeTest$split_sw.bb1_sw.epilog_2>
-; MIPS32: nop
-; MIPS32: li [[REG2:.*]],12
-; MIPS32: beq [[REG1]],[[REG2]],fc <.LtestRangeTest$split_sw.bb1_sw.epilog_2>
-; MIPS32: nop
-; MIPS32: li [[REG2:.*]],13
-; MIPS32: beq [[REG1]],[[REG2]],fc <.LtestRangeTest$split_sw.bb1_sw.epilog_2>
-; MIPS32: nop
-; MIPS32: b 108 <.LtestRangeTest$split_sw.default_sw.epilog_1>
-; MIPS32: nop
-
-; Sparse cases should be searched with a binary search.
-define internal i32 @testBinarySearch() {
-entry:
- switch i32 10, label %sw.default [
- i32 0, label %sw.epilog
- i32 10, label %sw.epilog
- i32 20, label %sw.bb1
- i32 30, label %sw.bb1
- ]
-
-sw.default:
- br label %sw.epilog
-
-sw.bb1:
- br label %sw.epilog
-
-sw.epilog:
- %result.1 = phi i32 [ 23, %sw.default ], [ 42, %sw.bb1 ], [ 17, %entry ], [ 17, %entry ]
- ret i32 %result.1
-}
-; CHECK-LABEL: testBinarySearch
-; CHECK: cmp {{.*}},0x14
-; CHECK-NEXT: jb
-; CHECK-NEXT: je
-; CHECK-NEXT: cmp {{.*}},0x1e
-; CHECK-NEXT: je
-; CHECK-NEXT: jmp
-; CHECK-NEXT: cmp {{.*}},0x0
-; CHECK-NEXT: je
-; CHECK-NEXT: cmp {{.*}},0xa
-; CHECK-NEXT: je
-; CHECK-NEXT: jmp
-
-; MIPS32-LABEL: testBinarySearch
-; MIPS32: li [[REG1:.*]],10
-; MIPS32: li [[REG2:.*]],0
-; MIPS32: beq [[REG1]],[[REG2]],174 <.LtestBinarySearch$split_entry_sw.epilog_0>
-; MIPS32: nop
-; MIPS32: li [[REG2:.*]],10
-; MIPS32: beq [[REG1]],[[REG2]],174 <.LtestBinarySearch$split_entry_sw.epilog_0>
-; MIPS32: nop
-; MIPS32: li [[REG2:.*]],20
-; MIPS32: beq [[REG1]],[[REG2]],15c <.LtestBinarySearch$split_sw.bb1_sw.epilog_2>
-; MIPS32: nop
-; MIPS32: li [[REG2:.*]],30
-; MIPS32: beq [[REG1]],[[REG2]],15c <.LtestBinarySearch$split_sw.bb1_sw.epilog_2>
-; MIPS32: nop
-; MIPS32: b 168 <.LtestBinarySearch$split_sw.default_sw.epilog_1>
-; MIPS32: nop
-
-; 64-bit switches where the cases are all 32-bit values should be reduced to a
-; 32-bit switch after checking the top byte is 0.
-define internal i32 @testSwitchSmall64(i64 %a) {
-entry:
- switch i64 %a, label %sw.default [
- i64 123, label %return
- i64 234, label %sw.bb1
- i64 345, label %sw.bb2
- i64 456, label %sw.bb3
- ]
-
-sw.bb1:
- br label %return
-
-sw.bb2:
- br label %return
-
-sw.bb3:
- br label %return
-
-sw.default:
- br label %return
-
-return:
- %retval.0 = phi i32 [ 5, %sw.default ], [ 4, %sw.bb3 ], [ 3, %sw.bb2 ], [ 2, %sw.bb1 ], [ 1, %entry ]
- ret i32 %retval.0
-}
-; CHECK-LABEL: testSwitchSmall64
-; X8632: cmp {{.*}},0x0
-; X8632-NEXT: jne
-; X8632-NEXT: cmp {{.*}},0x159
-; X8632-NEXT: jb
-; X8632-NEXT: je
-; X8632-NEXT: cmp {{.*}},0x1c8
-; X8632-NEXT: je
-; X8632-NEXT: jmp
-; X8632-NEXT: cmp {{.*}},0x7b
-; X8632-NEXT: je
-; X8632-NEXT: cmp {{.*}},0xea
-; X8632-NEXT: je
-
-; MIPS32-LABEL: testSwitchSmall64
-; MIPS32: li [[REG:.*]],0
-; MIPS32: bne {{.*}},[[REG]],198 <.LtestSwitchSmall64$local$__0>
-; MIPS32: nop
-; MIPS32: li [[REG:.*]],123
-; MIPS32: beq {{.*}},[[REG]],210 <.LtestSwitchSmall64$split_entry_return_0>
-; MIPS32: nop
-
-; Test for correct 64-bit lowering.
-; TODO(ascull): this should generate better code like the 32-bit version
-define internal i32 @testSwitch64(i64 %a) {
-entry:
- switch i64 %a, label %sw.default [
- i64 123, label %return
- i64 234, label %sw.bb1
- i64 345, label %sw.bb2
- i64 78187493520, label %sw.bb3
- ]
-
-sw.bb1:
- br label %return
-
-sw.bb2:
- br label %return
-
-sw.bb3:
- br label %return
-
-sw.default:
- br label %return
-
-return:
- %retval.0 = phi i32 [ 5, %sw.default ], [ 4, %sw.bb3 ], [ 3, %sw.bb2 ], [ 2, %sw.bb1 ], [ 1, %entry ]
- ret i32 %retval.0
-}
-; CHECK-LABEL: testSwitch64
-; X8632: cmp {{.*}},0x7b
-; X8632-NEXT: jne
-; X8632-NEXT: cmp {{.*}},0x0
-; X8632-NEXT: je
-; X8632: cmp {{.*}},0xea
-; X8632-NEXT: jne
-; X8632-NEXT: cmp {{.*}},0x0
-; X8632-NEXT: je
-; X8632: cmp {{.*}},0x159
-; X8632-NEXT: jne
-; X8632-NEXT: cmp {{.*}},0x0
-; X8632-NEXT: je
-; X8632: cmp {{.*}},0x34567890
-; X8632-NEXT: jne
-; X8632-NEXT: cmp {{.*}},0x12
-; X8632-NEXT: je
-
-; MIPS32-LABEL: testSwitch64
-; MIPS32: li [[REG:.*]],0
-; MIPS32: bne {{.*}},[[REG]],238 <.LtestSwitch64$local$__0>
-; MIPS32: nop
-; MIPS32: li [[REG:.*]],123
-; MIPS32: beq {{.*}},[[REG]],2b4 <.LtestSwitch64$split_entry_return_0>
-; MIPS32: nop
-
-; Test for correct 64-bit jump table with UINT64_MAX as one of the values.
-define internal i32 @testJumpTable64(i64 %a) {
-entry:
- switch i64 %a, label %sw.default [
- i64 -6, label %return
- i64 -4, label %sw.bb1
- i64 -3, label %sw.bb2
- i64 -1, label %sw.bb3
- ]
-
-sw.bb1:
- br label %return
-
-sw.bb2:
- br label %return
-
-sw.bb3:
- br label %return
-
-sw.default:
- br label %return
-
-return:
- %retval.0 = phi i32 [ 5, %sw.default ], [ 4, %sw.bb3 ], [ 3, %sw.bb2 ], [ 2, %sw.bb1 ], [ 1, %entry ]
- ret i32 %retval.0
-}
-
-; TODO(ascull): this should generate a jump table. For now, just make sure it
-; doesn't crash the compiler.
-; CHECK-LABEL: testJumpTable64
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/align-spill-locations.ll b/third_party/subzero/tests_lit/llvm2ice_tests/align-spill-locations.ll
deleted file mode 100644
index 8649973..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/align-spill-locations.ll
+++ /dev/null
@@ -1,93 +0,0 @@
-; This checks to ensure that Subzero aligns spill slots.
-
-; RUN: %p2i --filetype=obj --disassemble -i %s --args -Om1 \
-; RUN: -allow-externally-defined-symbols | FileCheck %s
-; RUN: %p2i --filetype=obj --disassemble -i %s --args -O2 \
-; RUN: -allow-externally-defined-symbols | FileCheck %s
-
-; The location of the stack slot for a variable is inferred from the
-; return sequence.
-
-; In this file, "global" refers to a variable with a live range across
-; multiple basic blocks (not an LLVM global variable) and "local"
-; refers to a variable that is live in only a single basic block.
-
-define internal <4 x i32> @align_global_vector(i32 %arg) {
-entry:
- %vec.global = insertelement <4 x i32> undef, i32 %arg, i32 0
- br label %block
-block:
- call void @ForceXmmSpills()
- ret <4 x i32> %vec.global
-; CHECK-LABEL: align_global_vector
-; CHECK: movups xmm0,XMMWORD PTR [esp]
-; CHECK-NEXT: add esp,0x1c
-; CHECK-NEXT: ret
-}
-
-define internal <4 x i32> @align_local_vector(i32 %arg) {
-entry:
- br label %block
-block:
- %vec.local = insertelement <4 x i32> undef, i32 %arg, i32 0
- call void @ForceXmmSpills()
- ret <4 x i32> %vec.local
-; CHECK-LABEL: align_local_vector
-; CHECK: movups xmm0,XMMWORD PTR [esp]
-; CHECK-NEXT: add esp,0x1c
-; CHECK-NEXT: ret
-}
-
-declare void @ForceXmmSpills()
-
-define internal <4 x i32> @align_global_vector_ebp_based(i32 %arg) {
-entry:
- br label %eblock ; Disable alloca optimization
-eblock:
- %alloc = alloca i8, i32 1, align 1
- %vec.global = insertelement <4 x i32> undef, i32 %arg, i32 0
- br label %block
-block:
- call void @ForceXmmSpillsAndUseAlloca(i8* %alloc)
- ret <4 x i32> %vec.global
-; CHECK-LABEL: align_global_vector_ebp_based
-; CHECK: movups xmm0,XMMWORD PTR [ebp-0x18]
-; CHECK-NEXT: mov esp,ebp
-; CHECK-NEXT: pop ebp
-; CHECK: ret
-}
-
-define internal <4 x i32> @align_local_vector_ebp_based(i32 %arg) {
-entry:
- br label %eblock ; Disable alloca optimization
-eblock:
- %alloc = alloca i8, i32 1, align 1
- %vec.local = insertelement <4 x i32> undef, i32 %arg, i32 0
- call void @ForceXmmSpillsAndUseAlloca(i8* %alloc)
- ret <4 x i32> %vec.local
-; CHECK-LABEL: align_local_vector_ebp_based
-; CHECK: movups xmm0,XMMWORD PTR [ebp-0x18]
-; CHECK-NEXT: mov esp,ebp
-; CHECK-NEXT: pop ebp
-; CHECK: ret
-}
-
-define internal <4 x i32> @align_local_vector_and_global_float(i32 %arg) {
-entry:
- %float.global = sitofp i32 %arg to float
- call void @ForceXmmSpillsAndUseFloat(float %float.global)
- br label %block
-block:
- %vec.local = insertelement <4 x i32> undef, i32 undef, i32 0
- call void @ForceXmmSpillsAndUseFloat(float %float.global)
- ret <4 x i32> %vec.local
-; CHECK-LABEL: align_local_vector_and_global_float
-; CHECK: cvtsi2ss xmm0,eax
-; CHECK-NEXT: movss DWORD PTR [esp+{{0x1c|0x2c}}],xmm0
-; CHECK: movups xmm0,XMMWORD PTR [{{esp\+0x10|esp\+0x20}}]
-; CHECK-NEXT: add esp,0x3c
-; CHECK-NEXT: ret
-}
-
-declare void @ForceXmmSpillsAndUseAlloca(i8*)
-declare void @ForceXmmSpillsAndUseFloat(float)
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/alloc.ll b/third_party/subzero/tests_lit/llvm2ice_tests/alloc.ll
deleted file mode 100644
index 64b3513..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/alloc.ll
+++ /dev/null
@@ -1,404 +0,0 @@
-; This is a basic test of the alloca instruction.
-
-; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
-; RUN: --target x8632 -i %s --args -O2 -allow-externally-defined-symbols \
-; RUN: | %if --need=target_X8632 --command FileCheck %s
-
-; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
-; RUN: --target x8632 -i %s --args -Om1 -allow-externally-defined-symbols \
-; RUN: | %if --need=target_X8632 --command FileCheck \
-; RUN: --check-prefix CHECK-OPTM1 %s
-
-; RUN: %if --need=target_ARM32 \
-; RUN: --command %p2i --filetype=obj \
-; RUN: --disassemble --target arm32 -i %s --args -O2 \
-; RUN: -allow-externally-defined-symbols \
-; RUN: | %if --need=target_ARM32 \
-; RUN: --command FileCheck --check-prefix ARM32 --check-prefix=ARM-OPT2 %s
-
-; RUN: %if --need=target_ARM32 \
-; RUN: --command %p2i --filetype=obj \
-; RUN: --disassemble --target arm32 -i %s --args -Om1 \
-; RUN: -allow-externally-defined-symbols \
-; RUN: | %if --need=target_ARM32 \
-; RUN: --command FileCheck --check-prefix ARM32 --check-prefix=ARM-OPTM1 %s
-
-; RUN: %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command %p2i --filetype=asm --assemble \
-; RUN: --disassemble --target mips32 -i %s --args -O2 \
-; RUN: -allow-externally-defined-symbols \
-; RUN: | %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command FileCheck --check-prefix MIPS32 --check-prefix=MIPS32-OPT2 %s
-
-; RUN: %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command %p2i --filetype=asm --assemble \
-; RUN: --disassemble --target mips32 -i %s --args -Om1 \
-; RUN: -allow-externally-defined-symbols \
-; RUN: | %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command FileCheck --check-prefix MIPS32 --check-prefix=MIPS32-OPTM1 %s
-
-define internal void @fixed_416_align_16(i32 %n) {
-entry:
- %array = alloca i8, i32 416, align 16
- %__2 = ptrtoint i8* %array to i32
- call void @f1(i32 %__2)
- ret void
-}
-; CHECK-LABEL: fixed_416_align_16
-; CHECK: sub esp,0x1bc
-; CHECK: lea eax,[esp+0x10]
-; CHECK: mov DWORD PTR [esp],eax
-; CHECK: call {{.*}} R_{{.*}} f1
-
-; CHECK-OPTM1-LABEL: fixed_416_align_16
-; CHECK-OPTM1: sub esp,0x18
-; CHECK-OPTM1: sub esp,0x1a0
-; CHECK-OPTM1: mov DWORD PTR [esp],eax
-; CHECK-OPTM1: call {{.*}} R_{{.*}} f1
-
-; ARM32-LABEL: fixed_416_align_16
-; ARM32-OPT2: sub sp, sp, #428
-; ARM32-OPTM1: sub sp, sp, #416
-; ARM32: bl {{.*}} R_{{.*}} f1
-
-; MIPS32-LABEL: fixed_416_align_16
-; MIPS32-OPT2: addiu sp,sp,-448
-; MIPS32-OPT2: addiu a0,sp,16
-; MIPS32-OPTM1: addiu sp,sp,-464
-; MIPS32-OPTM1: addiu [[REG:.*]],sp,16
-; MIPS32-OPTM1: sw [[REG]],{{.*}}
-; MIPS32-OPTM1: lw a0,{{.*}}
-; MIPS32: jal {{.*}} R_{{.*}} f1
-
-define internal void @fixed_416_align_32(i32 %n) {
-entry:
- %array = alloca i8, i32 400, align 32
- %__2 = ptrtoint i8* %array to i32
- call void @f1(i32 %__2)
- ret void
-}
-; CHECK-LABEL: fixed_416_align_32
-; CHECK: push ebp
-; CHECK-NEXT: mov ebp,esp
-; CHECK: sub esp,0x1d8
-; CHECK: and esp,0xffffffe0
-; CHECK: lea eax,[esp+0x10]
-; CHECK: mov DWORD PTR [esp],eax
-; CHECK: call {{.*}} R_{{.*}} f1
-
-; ARM32-LABEL: fixed_416_align_32
-; ARM32-OPT2: sub sp, sp, #424
-; ARM32-OPTM1: sub sp, sp, #416
-; ARM32: bic sp, sp, #31
-; ARM32: bl {{.*}} R_{{.*}} f1
-
-; MIPS32-LABEL: fixed_416_align_32
-; MIPS32-OPT2: addiu sp,sp,-448
-; MIPS32-OPT2: addiu a0,sp,16
-; MIPS32-OPTM1: addiu sp,sp,-464
-; MIPS32-OPTM1: addiu [[REG:.*]],sp,32
-; MIPS32-OPTM1: sw [[REG]],{{.*}}
-; MIPS32-OPTM1: lw a0,{{.*}}
-; MIPS32: jal {{.*}} R_{{.*}} f1
-
-; Show that the amount to allocate will be rounded up.
-define internal void @fixed_351_align_16(i32 %n) {
-entry:
- %array = alloca i8, i32 351, align 16
- %__2 = ptrtoint i8* %array to i32
- call void @f1(i32 %__2)
- ret void
-}
-; CHECK-LABEL: fixed_351_align_16
-; CHECK: sub esp,0x17c
-; CHECK: lea eax,[esp+0x10]
-; CHECK: mov DWORD PTR [esp],eax
-; CHECK: call {{.*}} R_{{.*}} f1
-
-; CHECK-OPTM1-LABEL: fixed_351_align_16
-; CHECK-OPTM1: sub esp,0x18
-; CHECK-OPTM1: sub esp,0x160
-; CHECK-OPTM1: mov DWORD PTR [esp],eax
-; CHECK-OPTM1: call {{.*}} R_{{.*}} f1
-
-; ARM32-LABEL: fixed_351_align_16
-; ARM32-OPT2: sub sp, sp, #364
-; ARM32-OPTM1: sub sp, sp, #352
-; ARM32: bl {{.*}} R_{{.*}} f1
-
-; MIPS32-LABEL: fixed_351_align_16
-; MIPS32-OPT2: addiu sp,sp,-384
-; MIPS32-OPT2: addiu a0,sp,16
-; MIPS32-OPTM1: addiu sp,sp,-400
-; MIPS32-OPTM1: addiu [[REG:.*]],sp,16
-; MIPS32-OPTM1: sw [[REG]],{{.*}}
-; MIPS32-OPTM1: lw a0,{{.*}}
-; MIPS32: jal {{.*}} R_{{.*}} f1
-
-define internal void @fixed_351_align_32(i32 %n) {
-entry:
- %array = alloca i8, i32 351, align 32
- %__2 = ptrtoint i8* %array to i32
- call void @f1(i32 %__2)
- ret void
-}
-; CHECK-LABEL: fixed_351_align_32
-; CHECK: push ebp
-; CHECK-NEXT: mov ebp,esp
-; CHECK: sub esp,0x198
-; CHECK: and esp,0xffffffe0
-; CHECK: lea eax,[esp+0x10]
-; CHECK: mov DWORD PTR [esp],eax
-; CHECK: call {{.*}} R_{{.*}} f1
-
-; ARM32-LABEL: fixed_351_align_32
-; ARM32-OPT2: sub sp, sp, #360
-; ARM32-OPTM1: sub sp, sp, #352
-; ARM32: bic sp, sp, #31
-; ARM32: bl {{.*}} R_{{.*}} f1
-
-; MIPS32-LABEL: fixed_351_align_32
-; MIPS32-OPT2: addiu sp,sp,-384
-; MIPS32-OPT2: addiu a0,sp,16
-; MIPS32-OPTM1: addiu sp,sp,-400
-; MIPS32-OPTM1: addiu [[REG:.*]],sp,32
-; MIPS32-OPTM1: sw [[REG]],{{.*}}
-; MIPS32-OPTM1: lw a0,{{.*}}
-; MIPS32: jal {{.*}} R_{{.*}} f1
-
-declare void @f1(i32 %ignored)
-
-declare void @f2(i32 %ignored)
-
-define internal void @variable_n_align_16(i32 %n) {
-entry:
- %array = alloca i8, i32 %n, align 16
- %__2 = ptrtoint i8* %array to i32
- call void @f2(i32 %__2)
- ret void
-}
-; CHECK-LABEL: variable_n_align_16
-; CHECK: sub esp,0x18
-; CHECK: mov eax,DWORD PTR [ebp+0x8]
-; CHECK: add eax,0xf
-; CHECK: and eax,0xfffffff0
-; CHECK: sub esp,eax
-; CHECK: lea eax,[esp+0x10]
-; CHECK: mov DWORD PTR [esp],eax
-; CHECK: call {{.*}} R_{{.*}} f2
-
-; ARM32-LABEL: variable_n_align_16
-; ARM32: add r0, r0, #15
-; ARM32: bic r0, r0, #15
-; ARM32: sub sp, sp, r0
-; ARM32: bl {{.*}} R_{{.*}} f2
-
-; MIPS32-LABEL: variable_n_align_16
-; MIPS32: addiu [[REG:.*]],{{.*}},15
-; MIPS32: li [[REG1:.*]],-16
-; MIPS32: and [[REG2:.*]],[[REG]],[[REG1]]
-; MIPS32: subu [[REG3:.*]],sp,[[REG2:.*]]
-; MIPS32: li [[REG4:.*]],-16
-; MIPS32: and {{.*}},[[REG3]],[[REG4]]
-; MIPS32: addiu sp,sp,-16
-; MIPS32: jal {{.*}} R_{{.*}} f2
-; MIPS32: addiu sp,sp,16
-
-define internal void @variable_n_align_32(i32 %n) {
-entry:
- %array = alloca i8, i32 %n, align 32
- %__2 = ptrtoint i8* %array to i32
- call void @f2(i32 %__2)
- ret void
-}
-; In -O2, the order of the CHECK-DAG lines in the output is switched.
-; CHECK-LABEL: variable_n_align_32
-; CHECK: push ebp
-; CHECK: mov ebp,esp
-; CHECK: sub esp,0x18
-; CHECK-DAG: and esp,0xffffffe0
-; CHECK-DAG: mov eax,DWORD PTR [ebp+0x8]
-; CHECK: add eax,0x1f
-; CHECK: and eax,0xffffffe0
-; CHECK: sub esp,eax
-; CHECK: lea eax,[esp+0x10]
-; CHECK: mov DWORD PTR [esp],eax
-; CHECK: call {{.*}} R_{{.*}} f2
-; CHECK: mov esp,ebp
-; CHECK: pop ebp
-
-; ARM32-LABEL: variable_n_align_32
-; ARM32: push {fp, lr}
-; ARM32: mov fp, sp
-; ARM32: bic sp, sp, #31
-; ARM32: add r0, r0, #31
-; ARM32: bic r0, r0, #31
-; ARM32: sub sp, sp, r0
-; ARM32: bl {{.*}} R_{{.*}} f2
-; ARM32: mov sp, fp
-; ARM32: pop {fp, lr}
-
-; MIPS32-LABEL: variable_n_align_32
-; MIPS32: addiu [[REG:.*]],{{.*}},15
-; MIPS32: li [[REG1:.*]],-16
-; MIPS32: and [[REG2:.*]],[[REG]],[[REG1]]
-; MIPS32: subu [[REG3:.*]],sp,[[REG2]]
-; MIPS32: li [[REG4:.*]],-32
-; MIPS32: and {{.*}},[[REG3]],[[REG4]]
-; MIPS32: addiu sp,sp,-16
-; MIPS32: jal {{.*}} R_{{.*}} f2
-; MIPS32: addiu sp,sp,16
-
-; Test alloca with default (0) alignment.
-define internal void @align0(i32 %n) {
-entry:
- %array = alloca i8, i32 %n
- %__2 = ptrtoint i8* %array to i32
- call void @f2(i32 %__2)
- ret void
-}
-; CHECK-LABEL: align0
-; CHECK: add [[REG:.*]],0xf
-; CHECK: and [[REG]],0xfffffff0
-; CHECK: sub esp,[[REG]]
-
-; ARM32-LABEL: align0
-; ARM32: add r0, r0, #15
-; ARM32: bic r0, r0, #15
-; ARM32: sub sp, sp, r0
-
-; MIPS32-LABEL: align0
-; MIPS32: addiu [[REG:.*]],{{.*}},15
-; MIPS32: li [[REG1:.*]],-16
-; MIPS32: and [[REG2:.*]],[[REG]],[[REG1]]
-; MIPS32: subu {{.*}},sp,[[REG2]]
-; MIPS32: addiu sp,sp,-16
-; MIPS32: jal {{.*}} R_{{.*}} f2
-; MIPS32: addiu sp,sp,16
-
-; Test a large alignment where a mask might not fit in an immediate
-; field of an instruction for some architectures.
-define internal void @align1MB(i32 %n) {
-entry:
- %array = alloca i8, i32 %n, align 1048576
- %__2 = ptrtoint i8* %array to i32
- call void @f2(i32 %__2)
- ret void
-}
-; CHECK-LABEL: align1MB
-; CHECK: push ebp
-; CHECK-NEXT: mov ebp,esp
-; CHECK: and esp,0xfff00000
-; CHECK: add [[REG:.*]],0xfffff
-; CHECK: and [[REG]],0xfff00000
-; CHECK: sub esp,[[REG]]
-
-; ARM32-LABEL: align1MB
-; ARM32: movw [[REG:.*]], #0
-; ARM32: movt [[REG]], #65520 ; 0xfff0
-; ARM32: and sp, sp, [[REG]]
-; ARM32: movw [[REG2:.*]], #65535 ; 0xffff
-; ARM32: movt [[REG2]], #15
-; ARM32: add r0, r0, [[REG2]]
-; ARM32: movw [[REG3:.*]], #0
-; ARM32: movt [[REG3]], #65520 ; 0xfff0
-; ARM32: and r0, r0, [[REG3]]
-; ARM32: sub sp, sp, r0
-
-; MIPS32-LABEL: align1MB
-; MIPS32: addiu [[REG:.*]],{{.*}},15
-; MIPS32: li [[REG1:.*]],-16
-; MIPS32: and [[REG2:.*]],[[REG]],[[REG1]]
-; MIPS32: subu [[REG3:.*]],sp,[[REG2]]
-; MIPS32: lui [[REG4:.*]],0xfff0
-; MIPS32: and {{.*}},[[REG3]],[[REG4]]
-; MIPS32: addiu sp,sp,-16
-; MIPS32: jal {{.*}} R_{{.*}} f2
-; MIPS32: addiu sp,sp,16
-
-; Test a large alignment where a mask might still fit in an immediate
-; field of an instruction for some architectures.
-define internal void @align512MB(i32 %n) {
-entry:
- %array = alloca i8, i32 %n, align 536870912
- %__2 = ptrtoint i8* %array to i32
- call void @f2(i32 %__2)
- ret void
-}
-; CHECK-LABEL: align512MB
-; CHECK: push ebp
-; CHECK-NEXT: mov ebp,esp
-; CHECK: and esp,0xe0000000
-; CHECK: add [[REG:.*]],0x1fffffff
-; CHECK: and [[REG]],0xe0000000
-; CHECK: sub esp,[[REG]]
-
-; ARM32-LABEL: align512MB
-; ARM32: and sp, sp, #-536870912 ; 0xe0000000
-; ARM32: mvn [[REG:.*]], #-536870912 ; 0xe0000000
-; ARM32: add r0, r0, [[REG]]
-; ARM32: and r0, r0, #-536870912 ; 0xe0000000
-; ARM32: sub sp, sp, r0
-
-; MIPS32-LABEL: align512MB
-; MIPS32: addiu [[REG:.*]],{{.*}},15
-; MIPS32: li [[REG2:.*]],-16
-; MIPS32: and [[REG3:.*]],[[REG]],[[REG2]]
-; MIPS32: subu [[REG4:.*]],sp,[[REG3]]
-; MIPS32: lui [[REG5:.*]],0xe000
-; MIPS32: and {{.*}},[[REG4]],[[REG5]]
-; MIPS32: addiu sp,sp,-16
-; MIPS32: jal {{.*}} R_{{.*}} f2
-; MIPS32: addiu sp,sp,16
-
-; Test that a simple alloca sequence doesn't trigger a frame pointer.
-define internal void @fixed_no_frameptr(i32 %arg) {
-entry:
- %a1 = alloca i8, i32 8, align 4
- %a2 = alloca i8, i32 12, align 4
- %a3 = alloca i8, i32 16, align 4
- %p1 = bitcast i8* %a1 to i32*
- %p2 = bitcast i8* %a2 to i32*
- %p3 = bitcast i8* %a3 to i32*
- store i32 %arg, i32* %p1, align 1
- store i32 %arg, i32* %p2, align 1
- store i32 %arg, i32* %p3, align 1
- ret void
-}
-; CHECK-LABEL: fixed_no_frameptr
-; CHECK-NOT: mov ebp,esp
-
-; Test that a simple alloca sequence with at least one large alignment does
-; trigger a frame pointer.
-define internal void @fixed_bigalign_with_frameptr(i32 %arg) {
-entry:
- %a1 = alloca i8, i32 8, align 4
- %a2 = alloca i8, i32 12, align 4
- %a3 = alloca i8, i32 16, align 64
- %p1 = bitcast i8* %a1 to i32*
- %p2 = bitcast i8* %a2 to i32*
- %p3 = bitcast i8* %a3 to i32*
- store i32 %arg, i32* %p1, align 1
- store i32 %arg, i32* %p2, align 1
- store i32 %arg, i32* %p3, align 1
- ret void
-}
-; CHECK-LABEL: fixed_bigalign_with_frameptr
-; CHECK: mov ebp,esp
-
-; Test that a more complex alloca sequence does trigger a frame pointer.
-define internal void @var_with_frameptr(i32 %arg) {
-entry:
- %a1 = alloca i8, i32 8, align 4
- %a2 = alloca i8, i32 12, align 4
- %a3 = alloca i8, i32 %arg, align 4
- %p1 = bitcast i8* %a1 to i32*
- %p2 = bitcast i8* %a2 to i32*
- %p3 = bitcast i8* %a3 to i32*
- store i32 %arg, i32* %p1, align 1
- store i32 %arg, i32* %p2, align 1
- store i32 %arg, i32* %p3, align 1
- ret void
-}
-; CHECK-LABEL: var_with_frameptr
-; CHECK: mov ebp,esp
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/arith-opt.ll b/third_party/subzero/tests_lit/llvm2ice_tests/arith-opt.ll
deleted file mode 100644
index e0cb0db..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/arith-opt.ll
+++ /dev/null
@@ -1,121 +0,0 @@
-; This is a very early test that just checks the representation of i32
-; arithmetic instructions. No assembly tests are done.
-
-; REQUIRES: allow_dump
-
-; RUN: %p2i -i %s --filetype=asm --args --verbose inst -threads=0 \
-; RUN: -allow-externally-defined-symbols | FileCheck %s
-
-define internal i32 @Add(i32 %a, i32 %b) {
-; CHECK: define internal i32 @Add
-entry:
- %add = add i32 %b, %a
-; CHECK: add
- tail call void @Use(i32 %add)
-; CHECK: call Use
- ret i32 %add
-}
-
-declare void @Use(i32)
-
-define internal i32 @And(i32 %a, i32 %b) {
-; CHECK: define internal i32 @And
-entry:
- %and = and i32 %b, %a
-; CHECK: and
- tail call void @Use(i32 %and)
-; CHECK: call Use
- ret i32 %and
-}
-
-define internal i32 @Or(i32 %a, i32 %b) {
-; CHECK: define internal i32 @Or
-entry:
- %or = or i32 %b, %a
-; CHECK: or
- tail call void @Use(i32 %or)
-; CHECK: call Use
- ret i32 %or
-}
-
-define internal i32 @Xor(i32 %a, i32 %b) {
-; CHECK: define internal i32 @Xor
-entry:
- %xor = xor i32 %b, %a
-; CHECK: xor
- tail call void @Use(i32 %xor)
-; CHECK: call Use
- ret i32 %xor
-}
-
-define internal i32 @Sub(i32 %a, i32 %b) {
-; CHECK: define internal i32 @Sub
-entry:
- %sub = sub i32 %a, %b
-; CHECK: sub
- tail call void @Use(i32 %sub)
-; CHECK: call Use
- ret i32 %sub
-}
-
-define internal i32 @Mul(i32 %a, i32 %b) {
-; CHECK: define internal i32 @Mul
-entry:
- %mul = mul i32 %b, %a
-; CHECK: imul
- tail call void @Use(i32 %mul)
-; CHECK: call Use
- ret i32 %mul
-}
-
-define internal i32 @Sdiv(i32 %a, i32 %b) {
-; CHECK: define internal i32 @Sdiv
-entry:
- %div = sdiv i32 %a, %b
-; CHECK: cdq
-; CHECK: idiv
- tail call void @Use(i32 %div)
-; CHECK: call Use
- ret i32 %div
-}
-
-define internal i32 @Srem(i32 %a, i32 %b) {
-; CHECK: define internal i32 @Srem
-entry:
- %rem = srem i32 %a, %b
-; CHECK: cdq
-; CHECK: idiv
- tail call void @Use(i32 %rem)
-; CHECK: call Use
- ret i32 %rem
-}
-
-define internal i32 @Udiv(i32 %a, i32 %b) {
-; CHECK: define internal i32 @Udiv
-entry:
- %div = udiv i32 %a, %b
-; CHECK: div
- tail call void @Use(i32 %div)
-; CHECK: call Use
- ret i32 %div
-}
-
-define internal i32 @Urem(i32 %a, i32 %b) {
-; CHECK: define internal i32 @Urem
-entry:
- %rem = urem i32 %a, %b
-; CHECK: div
- tail call void @Use(i32 %rem)
-; CHECK: call Use
- ret i32 %rem
-}
-
-; Check for a valid addressing mode in the x86-32 mul instruction when
-; the second source operand is an immediate.
-define internal i64 @MulImm() {
-entry:
- %mul = mul i64 3, 4
- ret i64 %mul
-}
-; CHECK-LABEL: MulImm
-; CHECK-NOT: mul {{[0-9]+}}
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/arith.ll b/third_party/subzero/tests_lit/llvm2ice_tests/arith.ll
deleted file mode 100644
index 72c459d..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/arith.ll
+++ /dev/null
@@ -1,310 +0,0 @@
-; Assembly test for simple arithmetic operations.
-
-; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
-; RUN: --target x8632 -i %s --args -O2 \
-; RUN: | %if --need=target_X8632 --command FileCheck %s
-
-; RUN: %if --need=target_ARM32 \
-; RUN: --command %p2i --filetype=obj --disassemble --target arm32 \
-; RUN: -i %s --args -O2 \
-; RUN: | %if --need=target_ARM32 \
-; RUN: --command FileCheck --check-prefix ARM32 --check-prefix ARM-OPT2 %s
-; RUN: %if --need=target_ARM32 \
-; RUN: --command %p2i --filetype=obj --disassemble --target arm32 \
-; RUN: -i %s --args -O2 --mattr=hwdiv-arm \
-; RUN: | %if --need=target_ARM32 \
-; RUN: --command FileCheck --check-prefix ARM32HWDIV %s
-; RUN: %if --need=target_ARM32 \
-; RUN: --command %p2i --filetype=obj --disassemble --target arm32 \
-; RUN: -i %s --args -Om1 \
-; RUN: | %if --need=target_ARM32 \
-; RUN: --command FileCheck --check-prefix ARM32 --check-prefix ARM32-OPTM1 %s
-;
-; RUN: %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command %p2i --filetype=asm --assemble --disassemble --target mips32\
-; RUN: -i %s --args -O2 \
-; RUN: | %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command FileCheck --check-prefix MIPS32 %s
-
-; RUN: %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command %p2i --filetype=asm --assemble --disassemble --target mips32\
-; RUN: -i %s --args -Om1 \
-; RUN: | %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command FileCheck --check-prefix MIPS32 %s
-
-define internal i32 @Add(i32 %a, i32 %b) {
-entry:
- %add = add i32 %b, %a
- ret i32 %add
-}
-; CHECK-LABEL: Add
-; CHECK: add e
-; ARM32-LABEL: Add
-; ARM32: add r
-; MIPS32-LABEL: Add
-; MIPS32: add
-
-define internal i32 @And(i32 %a, i32 %b) {
-entry:
- %and = and i32 %b, %a
- ret i32 %and
-}
-; CHECK-LABEL: And
-; CHECK: and e
-; ARM32-LABEL: And
-; ARM32: and r
-; MIPS32-LABEL: And
-; MIPS32: and
-
-define internal i32 @Or(i32 %a, i32 %b) {
-entry:
- %or = or i32 %b, %a
- ret i32 %or
-}
-; CHECK-LABEL: Or
-; CHECK: or e
-; ARM32-LABEL: Or
-; ARM32: orr r
-; MIPS32-LABEL: Or
-; MIPS32: or
-
-define internal i32 @Xor(i32 %a, i32 %b) {
-entry:
- %xor = xor i32 %b, %a
- ret i32 %xor
-}
-; CHECK-LABEL: Xor
-; CHECK: xor e
-; ARM32-LABEL: Xor
-; ARM32: eor r
-; MIPS32-LABEL: Xor
-; MIPS32: xor
-
-define internal i32 @Sub(i32 %a, i32 %b) {
-entry:
- %sub = sub i32 %a, %b
- ret i32 %sub
-}
-; CHECK-LABEL: Sub
-; CHECK: sub e
-; ARM32-LABEL: Sub
-; ARM32: sub r
-; MIPS32-LABEL: Sub
-; MIPS32: sub
-
-define internal i32 @Mul(i32 %a, i32 %b) {
-entry:
- %mul = mul i32 %b, %a
- ret i32 %mul
-}
-; CHECK-LABEL: Mul
-; CHECK: imul e
-; ARM32-LABEL: Mul
-; ARM32: mul r
-; MIPS32-LABEL: Mul
-; MIPS32: mul
-
-; Check for a valid ARM mul instruction where operands have to be registers.
-; On the other hand x86-32 does allow an immediate.
-define internal i32 @MulImm(i32 %a, i32 %b) {
-entry:
- %mul = mul i32 %a, 99
- ret i32 %mul
-}
-; CHECK-LABEL: MulImm
-; CHECK: imul e{{.*}},e{{.*}},0x63
-; ARM32-LABEL: MulImm
-; ARM32-OPTM1: mov {{.*}}, #99
-; ARM32-OPTM1: mul r{{.*}}, r{{.*}}, r{{.*}}
-; ARM32-OPT2: rsb [[T:r[0-9]+]], [[S:r[0-9]+]], [[S]], lsl #2
-; ARM32-OPT2-DAG: add [[T]], [[T]], [[S]], lsl #7
-; ARM32-OPT2-DAG: sub [[T]], [[T]], [[S]], lsl #5
-; MIPS32-LABEL: MulImm
-; MIPS32: mul
-
-; Check for a valid addressing mode in the x86-32 mul instruction when
-; the second source operand is an immediate.
-define internal i64 @MulImm64(i64 %a) {
-entry:
- %mul = mul i64 %a, 99
- ret i64 %mul
-}
-; NOTE: the lowering is currently a bit inefficient for small 64-bit constants.
-; The top bits of the immediate are 0, but the instructions modeling that
-; multiply by 0 are not eliminated (see expanded 64-bit ARM lowering).
-; CHECK-LABEL: MulImm64
-; CHECK: mov {{.*}},0x63
-; CHECK: mov {{.*}},0x0
-; CHECK-NOT: mul {{[0-9]+}}
-;
-; ARM32-LABEL: MulImm64
-; ARM32: mov {{.*}}, #99
-; ARM32: mov {{.*}}, #0
-; ARM32: mul r
-; ARM32: mla r
-; ARM32: umull r
-; ARM32: add r
-
-; MIPS32-LABEL: MulImm64
-
-define internal i32 @Sdiv(i32 %a, i32 %b) {
-entry:
- %div = sdiv i32 %a, %b
- ret i32 %div
-}
-; CHECK-LABEL: Sdiv
-; CHECK: cdq
-; CHECK: idiv e
-;
-; ARM32-LABEL: Sdiv
-; ARM32: tst [[DENOM:r.*]], [[DENOM]]
-; ARM32: bne
-; The following instruction is ".word 0xe7fedef0 = udf #60896 ; 0xede0".
-; ARM32: e7fedef0
-; ARM32: bl {{.*}} __divsi3
-; ARM32HWDIV-LABEL: Sdiv
-; ARM32HWDIV: tst
-; ARM32HWDIV: bne
-; ARM32HWDIV: sdiv
-
-; MIPS32-LABEL: Sdiv
-; MIPS32: div zero,{{.*}},[[REG:.*]]
-; MIPS32: teq [[REG]],zero,0x7
-; MIPS32: mflo
-
-define internal i32 @SdivConst(i32 %a) {
-entry:
- %div = sdiv i32 %a, 219
- ret i32 %div
-}
-; CHECK-LABEL: SdivConst
-; CHECK: cdq
-; CHECK: idiv e
-;
-; ARM32-LABEL: SdivConst
-; ARM32-NOT: tst
-; ARM32: bl {{.*}} __divsi3
-; ARM32HWDIV-LABEL: SdivConst
-; ARM32HWDIV-NOT: tst
-; ARM32HWDIV: sdiv
-
-; MIPS32-LABEL: SdivConst
-; MIPS32: div zero,{{.*}},[[REG:.*]]
-; MIPS32: teq [[REG]],zero,0x7
-; MIPS32: mflo
-
-define internal i32 @Srem(i32 %a, i32 %b) {
-entry:
- %rem = srem i32 %a, %b
- ret i32 %rem
-}
-; CHECK-LABEL: Srem
-; CHECK: cdq
-; CHECK: idiv e
-;
-; ARM32-LABEL: Srem
-; ARM32: tst [[DENOM:r.*]], [[DENOM]]
-; ARM32: bne
-; ARM32: bl {{.*}} __modsi3
-; ARM32HWDIV-LABEL: Srem
-; ARM32HWDIV: tst
-; ARM32HWDIV: bne
-; ARM32HWDIV: sdiv
-; ARM32HWDIV: mls
-
-; MIPS32-LABEL: Srem
-; MIPS32: div zero,{{.*}},[[REG:.*]]
-; MIPS32: teq [[REG]],zero,0x7
-; MIPS32: mfhi
-
-define internal i32 @Udiv(i32 %a, i32 %b) {
-entry:
- %div = udiv i32 %a, %b
- ret i32 %div
-}
-; CHECK-LABEL: Udiv
-; CHECK: div e
-;
-; ARM32-LABEL: Udiv
-; ARM32: tst [[DENOM:r.*]], [[DENOM]]
-; ARM32: bne
-; ARM32: bl {{.*}} __udivsi3
-; ARM32HWDIV-LABEL: Udiv
-; ARM32HWDIV: tst
-; ARM32HWDIV: bne
-; ARM32HWDIV: udiv
-
-; MIPS32-LABEL: Udiv
-; MIPS32: divu zero,{{.*}},[[REG:.*]]
-; MIPS32: teq [[REG]],zero,0x7
-; MIPS32: mflo
-
-define internal i32 @Urem(i32 %a, i32 %b) {
-entry:
- %rem = urem i32 %a, %b
- ret i32 %rem
-}
-; CHECK-LABEL: Urem
-; CHECK: div e
-;
-; ARM32-LABEL: Urem
-; ARM32: tst [[DENOM:r.*]], [[DENOM]]
-; ARM32: bne
-; ARM32: bl {{.*}} __umodsi3
-; ARM32HWDIV-LABEL: Urem
-; ARM32HWDIV: tst
-; ARM32HWDIV: bne
-; ARM32HWDIV: udiv
-; ARM32HWDIV: mls
-
-; MIPS32-LABEL: Urem
-; MIPS32: divu zero,{{.*}},[[REG:.*]]
-; MIPS32: teq [[REG]],zero,0x7
-; MIPS32: mfhi
-
-; The following tests check that shift instructions don't try to use a
-; ConstantRelocatable as an immediate operand.
-
-@G = internal global [4 x i8] zeroinitializer, align 4
-
-define internal i32 @ShlReloc(i32 %a) {
-entry:
- %opnd = ptrtoint [4 x i8]* @G to i32
- %result = shl i32 %a, %opnd
- ret i32 %result
-}
-; CHECK-LABEL: ShlReloc
-; CHECK: shl {{.*}},cl
-
-; MIPS32-LABEL: ShlReloc
-; MIPS32: lui [[REG:.*]],{{.*}} R_MIPS_HI16 G
-; MIPS32: addiu [[REG]],[[REG]],{{.*}} R_MIPS_LO16 G
-; MIPS32: sllv {{.*}},{{.*}},[[REG]]
-
-define internal i32 @LshrReloc(i32 %a) {
-entry:
- %opnd = ptrtoint [4 x i8]* @G to i32
- %result = lshr i32 %a, %opnd
- ret i32 %result
-}
-; CHECK-LABEL: LshrReloc
-; CHECK: shr {{.*}},cl
-
-; MIPS32-LABEL: LshrReloc
-; MIPS32: lui [[REG:.*]],{{.*}} R_MIPS_HI16 G
-; MIPS32: addiu [[REG]],[[REG]],{{.*}} R_MIPS_LO16 G
-; MIPS32: srlv {{.*}},{{.*}},[[REG]]
-
-define internal i32 @AshrReloc(i32 %a) {
-entry:
- %opnd = ptrtoint [4 x i8]* @G to i32
- %result = ashr i32 %a, %opnd
- ret i32 %result
-}
-; CHECK-LABEL: AshrReloc
-; CHECK: sar {{.*}},cl
-
-; MIPS32-LABEL: AshrReloc
-; MIPS32: lui [[REG:.*]],{{.*}} R_MIPS_HI16 G
-; MIPS32: addiu [[REG]],[[REG]],{{.*}} R_MIPS_LO16 G
-; MIPS32: srav {{.*}},{{.*}},[[REG]]
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/asm-verbose.ll b/third_party/subzero/tests_lit/llvm2ice_tests/asm-verbose.ll
deleted file mode 100644
index 65b8970..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/asm-verbose.ll
+++ /dev/null
@@ -1,26 +0,0 @@
-; Tests that -asm-verbose doesn't fail liveness validation because of
-; callee-save pushes/pops in a single-basic-block function.
-
-; REQUIRES: allow_dump
-; RUN: %p2i --target x8632 -i %s --filetype=asm --args -O2 -asm-verbose \
-; RUN: | FileCheck %s
-; TODO(stichnot,jpp): Enable for x8664.
-; RUIN: %p2i --target x8664 -i %s --filetype=asm --args -O2 -asm-verbose \
-; RUIN: | FileCheck %s
-; RUN: %p2i --target arm32 -i %s --filetype=asm --args -O2 -asm-verbose \
-; RUN: | FileCheck %s
-
-define internal i32 @single_bb(i32 %arg0, i32 %arg1, i32 %arg2, i32 %arg3,
- i32 %arg4, i32 %arg5, i32 %arg6, i32 %arg7) {
-b1:
- %t1 = add i32 %arg0, %arg1
- %t2 = add i32 %t1, %arg2
- %t3 = add i32 %t2, %arg3
- %t4 = add i32 %t3, %arg4
- %t5 = add i32 %t4, %arg5
- %t6 = add i32 %t5, %arg6
- %t7 = add i32 %t6, %arg7
- ret i32 %t7
-}
-
-; CHECK-LABEL: single_bb
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/bitcast.ll b/third_party/subzero/tests_lit/llvm2ice_tests/bitcast.ll
deleted file mode 100644
index 1a38a76..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/bitcast.ll
+++ /dev/null
@@ -1,135 +0,0 @@
-; Trivial smoke test of bitcast between integer and FP types.
-
-; RUN: %p2i --filetype=obj --disassemble -i %s --args -O2 | FileCheck %s
-; RUN: %p2i --filetype=obj --disassemble -i %s --args -Om1 | FileCheck %s
-
-; RUN: %if --need=target_ARM32 --command %p2i --filetype=obj --disassemble \
-; RUN: --target arm32 -i %s --args -O2 \
-; RUN: | %if --need=target_ARM32 --command FileCheck %s \
-; RUN: --check-prefix=ARM32
-
-; RUN: %if --need=target_ARM32 --command %p2i --filetype=obj --disassemble \
-; RUN: --target arm32 -i %s --args -Om1 \
-; RUN: | %if --need=target_ARM32 --command FileCheck %s \
-; RUN: --check-prefix=ARM32
-
-; RUN: %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command %p2i --filetype=asm \
-; RUN: --target mips32 -i %s --args -O2 \
-; RUN: | %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command FileCheck %s \
-; RUN: --check-prefix=MIPS32 --check-prefix=MIPS32-O2
-
-; RUN: %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command %p2i --filetype=asm \
-; RUN: --target mips32 -i %s --args -Om1 \
-; RUN: | %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command FileCheck %s \
-; RUN: --check-prefix=MIPS32 --check-prefix=MIPS32-OM1
-
-define internal i32 @cast_f2i(float %f) {
-entry:
- %v0 = bitcast float %f to i32
- ret i32 %v0
-}
-; CHECK-LABEL: cast_f2i
-; CHECK: movd eax
-; ARM32-LABEL: cast_f2i
-; ARM32: vmov r{{[0-9]+}}, s{{[0-9]+}}
-; MIPS32-LABEL: cast_f2i
-; MIPS32-O2: mfc1 $v0, $f{{[0-9]+}}
-; MIPS32-OM1: swc1
-; MIPS32-OM1: lw
-
-define internal float @cast_i2f(i32 %i) {
-entry:
- %v0 = bitcast i32 %i to float
- ret float %v0
-}
-; CHECK-LABEL: cast_i2f
-; CHECK: fld DWORD PTR
-; ARM32-LABEL: cast_i2f
-; ARM32: vmov s{{[0-9]+}}, r{{[0-9]+}}
-; MIPS32-LABEL: cast_i2f
-; MIPS32-O2: mtc1 $a0, $f{{[0-9]+}}
-; MIPS32-OM1: sw
-; MIPS32-OM1: lwc1
-
-define internal i64 @cast_d2ll(double %d) {
-entry:
- %v0 = bitcast double %d to i64
- ret i64 %v0
-}
-; CHECK-LABEL: cast_d2ll
-; CHECK: mov edx
-; ARM32-LABEL: cast_d2ll
-; ARM32: vmov r{{[0-9]+}}, r{{[0-9]+}}, d{{[0-9]+}}
-; MIPS32-LABEL: cast_d2ll
-; MIPS32-O2: swc1 $f13, {{.*}}
-; MIPS32-O2: swc1 $f12, {{.*}}
-; MIPS32-O2: lw $v0, {{.*}}
-; MIPS32-O2: lw $v1, {{.*}}
-; MIPS32-OM1: sdc1
-; MIPS32-OM1: lw
-; MIPS32-OM1: lw
-
-define internal i64 @cast_d2ll_const() {
-entry:
- %v0 = bitcast double 0x12345678901234 to i64
- ret i64 %v0
-}
-; CHECK-LABEL: cast_d2ll_const
-; CHECK: mov e{{..}},{{(DWORD PTR )?}}ds:0x0 {{.*}} {{.*}}0012345678901234
-; CHECK: mov e{{..}},{{(DWORD PTR )?}}ds:0x4 {{.*}} {{.*}}0012345678901234
-; ARM32-LABEL: cast_d2ll_const
-; ARM32-DAG: movw [[ADDR:r[0-9]+]], #{{.*_MOVW_}}
-; ARM32-DAG: movt [[ADDR]], #{{.*_MOVT_}}
-; ARM32-DAG: vldr [[DREG:d[0-9]+]], {{\[}}[[ADDR]]{{\]}}
-; ARM32: vmov r{{[0-9]+}}, r{{[0-9]+}}, [[DREG]]
-; MIPS32-LABEL: cast_d2ll_const
-; MIPS32: lui {{.*}}, %hi(.L$double$0012345678901234)
-; MIPS32: ldc1 {{.*}}, %lo(.L$double$0012345678901234)({{.*}})
-; MIPS32: swc1 $f{{[0-9]+}}, {{.*}}
-; MIPS32: swc1 $f{{[0-9]+}}, {{.*}}
-; MIPS32: lw $v0, {{.*}}
-; MIPS32: lw $v1, {{.*}}
-
-define internal double @cast_ll2d(i64 %ll) {
-entry:
- %v0 = bitcast i64 %ll to double
- ret double %v0
-}
-; CHECK-LABEL: cast_ll2d
-; CHECK: fld QWORD PTR
-; ARM32-LABEL: cast_ll2d
-; ARM32: vmov d{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}
-; MIPS32-LABEL: cast_ll2d
-; MIPS32-O2: mtc1 $a0, $f{{[0-9]+}}
-; MIPS32-O2: mtc1 $a1, $f{{[0-9]+}}
-; MIPS32-OM1: sw
-; MIPS32-OM1: sw
-; MIPS32-OM1: ldc1
-
-define internal double @cast_ll2d_const() {
-entry:
- %v0 = bitcast i64 12345678901234 to double
- ret double %v0
-}
-; CHECK-LABEL: cast_ll2d_const
-; CHECK: mov {{.*}},0x73ce2ff2
-; CHECK: mov {{.*}},0xb3a
-; CHECK: fld QWORD PTR
-; ARM32-LABEL: cast_ll2d_const
-; ARM32-DAG: movw [[REG0:r[0-9]+]], #12274
-; ARM32-DAG: movt [[REG0:r[0-9]+]], #29646
-; ARM32-DAG: movw [[REG1:r[0-9]+]], #2874
-; ARM32: vmov d{{[0-9]+}}, [[REG0]], [[REG1]]
-; MIPS32-LABEL: cast_ll2d_const
-; MIPS32: lui {{.*}}, 29646
-; MIPS32: ori {{.*}}, {{.*}}, 12274
-; MIPS32: addiu {{.*}}, $zero, 2874
-; MIPS32-O2: mtc1 {{.*}}, $f{{[0-9]+}}
-; MIPS32-O2: mtc1 {{.*}}, $f{{[0-9]+}}
-; MIPS32-OM1: sw
-; MIPS32-OM1: sw
-; MIPS32-OM1: ldc1
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/bool-folding.ll b/third_party/subzero/tests_lit/llvm2ice_tests/bool-folding.ll
deleted file mode 100644
index 1ce0121..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/bool-folding.ll
+++ /dev/null
@@ -1,481 +0,0 @@
-; This tests the optimization where producers and consumers of i1 (bool)
-; variables are combined to implicitly use flags instead of explicitly using
-; stack or register variables.
-
-; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 \
-; RUN: -allow-externally-defined-symbols | FileCheck %s
-
-; RUN: %if --need=target_ARM32 --command %p2i --filetype=obj \
-; RUN: --target arm32 -i %s --disassemble --args -O2 \
-; RUN: -allow-externally-defined-symbols \
-; RUN: | %if --need=target_ARM32 --command FileCheck %s \
-; RUN: --check-prefix=ARM32
-
-declare void @use_value(i32)
-
-; Basic cmp/branch folding.
-define internal i32 @fold_cmp_br(i32 %arg1, i32 %arg2) {
-entry:
- %cmp1 = icmp slt i32 %arg1, %arg2
- br i1 %cmp1, label %branch1, label %branch2
-branch1:
- ret i32 1
-branch2:
- ret i32 2
-}
-
-; CHECK-LABEL: fold_cmp_br
-; CHECK: cmp
-; CHECK: jge
-; ARM32-LABEL: fold_cmp_br
-; ARM32: cmp r0, r1
-; ARM32: bge
-; ARM32: mov r0, #1
-; ARM32: bx lr
-; ARM32: mov r0, #2
-; ARM32: bx lr
-
-
-; Cmp/branch folding with intervening instructions.
-define internal i32 @fold_cmp_br_intervening_insts(i32 %arg1, i32 %arg2) {
-entry:
- %cmp1 = icmp slt i32 %arg1, %arg2
- call void @use_value(i32 %arg1)
- br i1 %cmp1, label %branch1, label %branch2
-branch1:
- ret i32 1
-branch2:
- ret i32 2
-}
-
-; CHECK-LABEL: fold_cmp_br_intervening_insts
-; CHECK-NOT: cmp
-; CHECK: call
-; CHECK: cmp
-; CHECK: jge
-; ARM32-LABEL: fold_cmp_br_intervening_insts
-; ARM32: push {{[{].*[}]}}
-; ARM32: bl{{.*}}use_value
-; ARM32: cmp {{r[0-9]+}}, {{r[0-9]+}}
-; ARM32: bge
-; ARM32: mov r0, #1
-; ARM32: bx lr
-; ARM32: mov r0, #2
-; ARM32: bx lr
-
-
-; Cmp/branch non-folding because of live-out.
-define internal i32 @no_fold_cmp_br_liveout(i32 %arg1, i32 %arg2) {
-entry:
- %cmp1 = icmp slt i32 %arg1, %arg2
- br label %next
-next:
- br i1 %cmp1, label %branch1, label %branch2
-branch1:
- ret i32 1
-branch2:
- ret i32 2
-}
-
-; CHECK-LABEL: no_fold_cmp_br_liveout
-; CHECK: cmp
-; CHECK: set
-; CHECK: cmp
-; CHECK: je
-; ARM32-LABEL: no_fold_cmp_br_liveout
-; ARM32: cmp
-; ARM32: movlt [[REG:r[0-9]+]]
-; ARM32: tst [[REG]], #1
-; ARM32: beq
-
-
-; Cmp/branch non-folding because of extra non-whitelisted uses.
-define internal i32 @no_fold_cmp_br_non_whitelist(i32 %arg1, i32 %arg2) {
-entry:
- %cmp1 = icmp slt i32 %arg1, %arg2
- %result = zext i1 %cmp1 to i32
- br i1 %cmp1, label %branch1, label %branch2
-branch1:
- ret i32 %result
-branch2:
- ret i32 2
-}
-
-; CHECK-LABEL: no_fold_cmp_br_non_whitelist
-; CHECK: cmp
-; CHECK: set
-; CHECK: movzx
-; CHECK: cmp
-; CHECK: je
-; ARM32-LABEL: no_fold_cmp_br_non_whitelist
-; ARM32: mov [[R:r[0-9]+]], #0
-; ARM32: cmp r0, r1
-; ARM32: movlt [[R]], #1
-; ARM32: tst [[R]], #1
-; ARM32: beq
-; ARM32: bx lr
-; ARM32: mov r0, #2
-; ARM32: bx lr
-
-
-; Basic cmp/select folding.
-define internal i32 @fold_cmp_select(i32 %arg1, i32 %arg2) {
-entry:
- %cmp1 = icmp slt i32 %arg1, %arg2
- %result = select i1 %cmp1, i32 %arg1, i32 %arg2
- ret i32 %result
-}
-
-; CHECK-LABEL: fold_cmp_select
-; CHECK: cmp
-; CHECK: cmovl
-; ARM32-LABEL: fold_cmp_select
-; ARM32: cmp r0, r1
-; ARM32: movlt {{r[0-9]+}}, r0
-
-; 64-bit cmp/select folding.
-define internal i64 @fold_cmp_select_64(i64 %arg1, i64 %arg2) {
-entry:
- %arg1_trunc = trunc i64 %arg1 to i32
- %arg2_trunc = trunc i64 %arg2 to i32
- %cmp1 = icmp slt i32 %arg1_trunc, %arg2_trunc
- %result = select i1 %cmp1, i64 %arg1, i64 %arg2
- ret i64 %result
-}
-
-; CHECK-LABEL: fold_cmp_select_64
-; CHECK: cmp
-; CHECK: cmovl
-; CHECK: cmovl
-; ARM32-LABEL: fold_cmp_select_64
-; ARM32: cmp r0, r2
-; ARM32: movlt [[LOW:r[0-9]+]], r0
-; ARM32: movlt [[HIGH:r[0-9]+]], r1
-; ARM32: mov r0, [[LOW]]
-; ARM32: mov r1, [[HIGH]]
-; ARM32: bx lr
-
-
-define internal i64 @fold_cmp_select_64_undef(i64 %arg1) {
-entry:
- %arg1_trunc = trunc i64 %arg1 to i32
- %cmp1 = icmp slt i32 undef, %arg1_trunc
- %result = select i1 %cmp1, i64 %arg1, i64 undef
- ret i64 %result
-}
-; CHECK-LABEL: fold_cmp_select_64_undef
-; CHECK: cmp
-; CHECK: cmovl
-; CHECK: cmovl
-; ARM32-LABEL: fold_cmp_select_64_undef
-; ARM32: mov
-; ARM32: rsbs r{{[0-9]+}}, r{{[0-9]+}}, #0
-; ARM32: movlt
-; ARM32: movlt
-; ARM32: bx lr
-
-
-; Cmp/select folding with intervening instructions.
-define internal i32 @fold_cmp_select_intervening_insts(i32 %arg1, i32 %arg2) {
-entry:
- %cmp1 = icmp slt i32 %arg1, %arg2
- call void @use_value(i32 %arg1)
- %result = select i1 %cmp1, i32 %arg1, i32 %arg2
- ret i32 %result
-}
-
-; CHECK-LABEL: fold_cmp_select_intervening_insts
-; CHECK-NOT: cmp
-; CHECK: call
-; CHECK: cmp
-; CHECK: cmovl
-; ARM32-LABEL: fold_cmp_select_intervening_insts
-; ARM32: bl{{.*}}use_value
-; ARM32: cmp r{{[0-9]+}}, r{{[0-9]+}}
-; ARM32: movlt
-; ARM32: bx lr
-
-; Cmp/multi-select folding.
-define internal i32 @fold_cmp_select_multi(i32 %arg1, i32 %arg2) {
-entry:
- %cmp1 = icmp slt i32 %arg1, %arg2
- %a = select i1 %cmp1, i32 %arg1, i32 %arg2
- %b = select i1 %cmp1, i32 %arg2, i32 %arg1
- %c = select i1 %cmp1, i32 123, i32 %arg1
- %partial = add i32 %a, %b
- %result = add i32 %partial, %c
- ret i32 %result
-}
-
-; CHECK-LABEL: fold_cmp_select_multi
-; CHECK: cmp
-; CHECK: cmovl
-; CHECK: cmp
-; CHECK: cmovl
-; CHECK: cmp
-; CHECK: cmovge
-; CHECK: add
-; CHECK: add
-; ARM32-LABEL: fold_cmp_select_multi
-; ARM32: mov
-; ARM32: cmp
-; ARM32: movlt {{.*}}, #1
-; ARM32: mov
-; ARM32: tst {{.*}}, #1
-; ARM32: movne
-; ARM32: mov
-; ARM32: tst {{.*}}, #1
-; ARM32: movne
-; ARM32: tst {{.*}}, #1
-; ARM32: movne {{.*}}, #123
-; ARM32: bx lr
-
-
-; Cmp/multi-select non-folding because of live-out.
-define internal i32 @no_fold_cmp_select_multi_liveout(i32 %arg1, i32 %arg2) {
-entry:
- %cmp1 = icmp slt i32 %arg1, %arg2
- %a = select i1 %cmp1, i32 %arg1, i32 %arg2
- %b = select i1 %cmp1, i32 %arg2, i32 %arg1
- br label %next
-next:
- %c = select i1 %cmp1, i32 123, i32 %arg1
- %partial = add i32 %a, %b
- %result = add i32 %partial, %c
- ret i32 %result
-}
-
-; CHECK-LABEL: no_fold_cmp_select_multi_liveout
-; CHECK: set
-; CHECK: cmp
-; CHECK: cmovne
-; CHECK: cmp
-; CHECK: cmovne
-; CHECK: cmp
-; CHECK: cmove
-; CHECK: add
-; CHECK: add
-; ARM32-LABEL: no_fold_cmp_select_multi_liveout
-; ARM32: mov
-; ARM32: cmp r0, r1
-; ARM32: movlt
-; ARM32: mov
-; ARM32: tst
-; ARM32: movne
-; ARM32: mov
-; ARM32: tst
-; ARM32: movne
-; ARM32: tst
-; ARM32: movne
-; ARM32: bx lr
-
-; Cmp/branch non-folding due to load folding and intervening store.
-define internal i32 @no_fold_cmp_br_store(i32 %arg2, i32 %argaddr) {
-entry:
- %addr = inttoptr i32 %argaddr to i32*
- %arg1 = load i32, i32* %addr, align 1
- %cmp1 = icmp slt i32 %arg1, %arg2
- store i32 1, i32* %addr, align 1
- br i1 %cmp1, label %branch1, label %branch2
-branch1:
- ret i32 1
-branch2:
- ret i32 2
-}
-
-; CHECK-LABEL: no_fold_cmp_br_store
-; CHECK: cmp
-; CHECK: set
-; CHECK: cmp
-
-; Cmp/select non-folding due to load folding and intervening store.
-define internal i32 @no_fold_cmp_select_store(i32 %arg1, i32 %argaddr) {
-entry:
- %addr = inttoptr i32 %argaddr to i32*
- %arg2 = load i32, i32* %addr, align 1
- %cmp1 = icmp slt i32 %arg1, %arg2
- store i32 1, i32* %addr, align 1
- %result = select i1 %cmp1, i32 %arg1, i32 %argaddr
- ret i32 %result
-}
-
-; CHECK-LABEL: no_fold_cmp_select_store
-; CHECK: cmp
-; CHECK: setl
-; CHECK: mov DWORD PTR
-; CHECK: cmp
-; CHECK: cmovne
-
-; Cmp/select folding due to load folding and non-intervening store.
-define internal i32 @fold_cmp_select_store(i32 %arg1, i32 %argaddr) {
-entry:
- %addr = inttoptr i32 %argaddr to i32*
- %arg2 = load i32, i32* %addr, align 1
- %cmp1 = icmp slt i32 %arg1, %arg2
- %result = select i1 %cmp1, i32 %arg1, i32 %argaddr
- store i32 1, i32* %addr, align 1
- ret i32 %result
-}
-
-; CHECK-LABEL: fold_cmp_select_store
-; CHECK: cmp {{.*}},DWORD PTR
-; CHECK: cmovl
-
-; Cmp/multi-select non-folding because of extra non-whitelisted uses.
-define internal i32 @no_fold_cmp_select_multi_non_whitelist(i32 %arg1,
- i32 %arg2) {
-entry:
- %cmp1 = icmp slt i32 %arg1, %arg2
- %a = select i1 %cmp1, i32 %arg1, i32 %arg2
- %b = select i1 %cmp1, i32 %arg2, i32 %arg1
- %c = select i1 %cmp1, i32 123, i32 %arg1
- %ext = zext i1 %cmp1 to i32
- %partial1 = add i32 %a, %b
- %partial2 = add i32 %partial1, %c
- %result = add i32 %partial2, %ext
- ret i32 %result
-}
-
-; CHECK-LABEL: no_fold_cmp_select_multi_non_whitelist
-; CHECK: set
-; CHECK: cmp
-; CHECK: cmovne
-; CHECK: cmp
-; CHECK: cmovne
-; CHECK: cmp
-; CHECK: cmove
-; CHECK: movzx
-; CHECK: add
-; CHECK: add
-; CHECK: add
-; ARM32-LABEL: no_fold_cmp_select_multi_non_whitelist
-; ARM32: mov
-; ARM32: cmp r0, r1
-; ARM32: movlt
-; ARM32: mov
-; ARM32: tst
-; ARM32: movne
-; ARM32: mov
-; ARM32: tst
-; ARM32: movne
-; ARM32: tst
-; ARM32: movne
-; ARM32: bx lr
-
-define internal i32 @br_i1_folding2_and(i32 %arg1, i32 %arg2) {
- %t0 = trunc i32 %arg1 to i1
- %t1 = trunc i32 %arg2 to i1
-
- %t2 = and i1 %t0, %t1
- br i1 %t2, label %target_true, label %target_false
-
-target_true:
- ret i32 1
-
-target_false:
- ret i32 0
-}
-; ARM32-LABEL: br_i1_folding2_and
-; ARM32: tst r0, #1
-; ARM32: beq
-; ARM32: tst r1, #1
-; ARM32: beq
-
-define internal i32 @br_i1_folding2_or(i32 %arg1, i32 %arg2) {
- %t0 = trunc i32 %arg1 to i1
- %t1 = trunc i32 %arg2 to i1
-
- %t2 = or i1 %t0, %t1
- br i1 %t2, label %target_true, label %target_false
-
-target_true:
- ret i32 1
-
-target_false:
- ret i32 0
-}
-; ARM32-LABEL: br_i1_folding2_or
-; ARM32: tst r0, #1
-; ARM32: bne
-; ARM32: tst r1, #1
-; ARM32: beq
-
-define internal i32 @br_i1_folding3_and_or(i32 %arg1, i32 %arg2, i32 %arg3) {
- %t0 = trunc i32 %arg1 to i1
- %t1 = trunc i32 %arg2 to i1
- %t2 = trunc i32 %arg3 to i1
-
- %t3 = and i1 %t0, %t1
- %t4 = or i1 %t3, %t2
-
- br i1 %t4, label %target_true, label %target_false
-
-target_true:
- ret i32 1
-
-target_false:
- ret i32 0
-}
-; ARM32-LABEL: br_i1_folding3_and_or
-; ARM32: tst r0, #1
-; ARM32: beq
-; ARM32: tst r1, #1
-; ARM32: bne
-; ARM32: tst r2, #1
-; ARM32: beq
-
-define internal i32 @br_i1_folding3_or_and(i32 %arg1, i32 %arg2, i32 %arg3) {
- %t0 = trunc i32 %arg1 to i1
- %t1 = trunc i32 %arg2 to i1
- %t2 = trunc i32 %arg3 to i1
-
- %t3 = or i1 %t0, %t1
- %t4 = and i1 %t3, %t2
-
- br i1 %t4, label %target_true, label %target_false
-
-target_true:
- ret i32 1
-
-target_false:
- ret i32 0
-}
-; ARM32-LABEL: br_i1_folding3_or_and
-; ARM32: tst r0, #1
-; ARM32: bne
-; ARM32: tst r1, #1
-; ARM32: beq
-; ARM32: tst r2, #1
-; ARM32: beq
-
-define internal i32 @br_i1_folding4(i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4,
- i32 %arg5) {
- %t0 = trunc i32 %arg1 to i1
- %t1 = trunc i32 %arg2 to i1
- %t2 = trunc i32 %arg3 to i1
- %t3 = trunc i32 %arg4 to i1
- %t4 = trunc i32 %arg5 to i1
-
- %t5 = or i1 %t0, %t1
- %t6 = and i1 %t5, %t2
- %t7 = and i1 %t3, %t4
- %t8 = or i1 %t6, %t7
- br i1 %t8, label %target_true, label %target_false
-
-target_true:
- ret i32 1
-
-target_false:
- ret i32 0
-}
-; ARM32-LABEL: br_i1_folding4
-; ARM32: tst r0, #1
-; ARM32: bne
-; ARM32: tst r1, #1
-; ARM32: beq
-; ARM32: tst r2, #1
-; ARM32: bne
-; ARM32: tst r3, #1
-; ARM32: beq [[TARGET:.*]]
-; ARM32: tst r4, #1
-; ARM32: beq [[TARGET]]
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/bool-opt.ll b/third_party/subzero/tests_lit/llvm2ice_tests/bool-opt.ll
deleted file mode 100644
index c7a31e0..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/bool-opt.ll
+++ /dev/null
@@ -1,18 +0,0 @@
-; Trivial smoke test of icmp without fused branch opportunity.
-
-; RUN: %p2i -i %s --filetype=obj --disassemble --args \
-; RUN: -allow-externally-defined-symbols | FileCheck %s
-
-; Check that correct addressing modes are used for comparing two
-; immediates.
-define internal void @testIcmpImm() {
-entry:
- %cmp = icmp eq i32 1, 2
- %cmp_ext = zext i1 %cmp to i32
- tail call void @use(i32 %cmp_ext)
- ret void
-}
-; CHECK-LABEL: testIcmpImm
-; CHECK-NOT: cmp {{[0-9]+}},
-
-declare void @use(i32)
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/branch-opt.ll b/third_party/subzero/tests_lit/llvm2ice_tests/branch-opt.ll
deleted file mode 100644
index f5827df..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/branch-opt.ll
+++ /dev/null
@@ -1,310 +0,0 @@
-; Tests the branch optimizations under O2 (against a lack of
-; optimizations under Om1).
-
-; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
-; RUN: --target x8632 -i %s --args -O2 -allow-externally-defined-symbols \
-; RUN: | %if --need=target_X8632 --command FileCheck --check-prefix=O2 %s
-
-; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
-; RUN: --target x8632 -i %s --args -Om1 -allow-externally-defined-symbols \
-; RUN: | %if --need=target_X8632 --command FileCheck --check-prefix=OM1 %s
-
-; RUN: %if --need=target_ARM32_dump \
-; RUN: --command %p2i --filetype=obj \
-; RUN: --disassemble --target arm32 -i %s --args -O2 \
-; RUN: -allow-externally-defined-symbols \
-; RUN: | %if --need=target_ARM32_dump \
-; RUN: --command FileCheck --check-prefix ARM32O2 %s
-
-; RUN: %if --need=target_ARM32 \
-; RUN: --command %p2i --filetype=obj \
-; RUN: --disassemble --target arm32 -i %s --args -Om1 \
-; RUN: -allow-externally-defined-symbols \
-; RUN: | %if --need=target_ARM32 \
-; RUN: --command FileCheck \
-; RUN: --check-prefix ARM32OM1 %s
-
-; RUN: %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command %p2i --filetype=asm --assemble \
-; RUN: --disassemble --target mips32 -i %s --args -O2 \
-; RUN: -allow-externally-defined-symbols \
-; RUN: | %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command FileCheck --check-prefix MIPS32O2 %s
-
-; RUN: %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command %p2i --filetype=asm --assemble \
-; RUN: --disassemble --target mips32 -i %s --args -Om1 \
-; RUN: -allow-externally-defined-symbols \
-; RUN: | %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command FileCheck \
-; RUN: --check-prefix MIPS32OM1 %s
-
-declare void @dummy()
-
-; An unconditional branch to the next block should be removed.
-define internal void @testUncondToNextBlock() {
-entry:
- call void @dummy()
- br label %next
-next:
- call void @dummy()
- ret void
-}
-; O2-LABEL: testUncondToNextBlock
-; O2: call
-; There will be nops for bundle align to end (for NaCl), but there should
-; not be a branch.
-; O2-NOT: j
-; O2: call
-
-; OM1-LABEL: testUncondToNextBlock
-; OM1: call
-; OM1-NEXT: jmp
-; OM1: call
-
-; ARM32O2-LABEL: testUncondToNextBlock
-; ARM32O2: bl {{.*}} dummy
-; ARM32O2-NEXT: bl {{.*}} dummy
-
-; ARM32OM1-LABEL: testUncondToNextBlock
-; ARM32OM1: bl {{.*}} dummy
-; ARM32OM1-NEXT: b
-; ARM32OM1-NEXT: bl {{.*}} dummy
-
-; MIPS32O2-LABEL: testUncondToNextBlock
-; MIPS32O2: jal {{.*}} dummy
-; MIPS32O2-NEXT: nop
-; MIPS32O2-LABEL: <.LtestUncondToNextBlock$next>:
-; MIPS32O2-NEXT: jal {{.*}} dummy
-; MIPS32O2-NEXT: nop
-
-; MIPS32OM1-LABEL: testUncondToNextBlock
-; MIPS32OM1: jal {{.*}} dummy
-; MIPS32OM1-NEXT: nop
-; MIPS32OM1-NEXT: b {{.*}} <.LtestUncondToNextBlock$next>
-; MIPS32OM1-NEXT: nop
-; MIPS32OM1-LABEL: <.LtestUncondToNextBlock$next>:
-; MIPS32OM1-NEXT: jal {{.*}} dummy
-; MIPS32OM1-NEXT: nop
-
-; For a conditional branch with a fallthrough to the next block, the
-; fallthrough branch should be removed.
-define internal void @testCondFallthroughToNextBlock(i32 %arg) {
-entry:
- %cmp = icmp sge i32 %arg, 123
- br i1 %cmp, label %target, label %fallthrough
-fallthrough:
- call void @dummy()
- ret void
-target:
- call void @dummy()
- ret void
-}
-; O2-LABEL: testCondFallthroughToNextBlock
-; O2: cmp {{.*}},0x7b
-; O2-NEXT: jge
-; O2-NOT: j
-; O2: call
-; O2: ret
-; O2: call
-; O2: ret
-
-; OM1-LABEL: testCondFallthroughToNextBlock
-; OM1: cmp {{.*}},0x7b
-; OM1: setge
-; OM1: cmp
-; OM1: jne
-; OM1: jmp
-; OM1: call
-; OM1: ret
-; OM1: call
-; OM1: ret
-
-; ARM32O2-LABEL: testCondFallthroughToNextBlock
-; ARM32O2: cmp {{.*}}, #123
-; ARM32O2-NEXT: bge
-; ARM32O2-NEXT: bl
-; ARM32O2: bx lr
-; ARM32O2: bl
-; ARM32O2: bx lr
-
-; ARM32OM1-LABEL: testCondFallthroughToNextBlock
-; ARM32OM1: mov {{.*}}, #0
-; ARM32OM1: cmp {{.*}}, #123
-; ARM32OM1: movge {{.*}}, #1
-; ARM32OM1: tst {{.*}}, #1
-; ARM32OM1: bne
-; ARM32OM1: b
-; ARM32OM1: bl
-; ARM32OM1: bx lr
-; ARM32OM1: bl
-; ARM32OM1: bx lr
-
-; MIPS32O2-LABEL: testCondFallthroughToNextBlock
-; MIPS32O2: li {{.*}},123
-; MIPS32O2: slt {{.*}},{{.*}},{{.*}}
-; MIPS32O2: beqz
-; MIPS32O2: nop
-; MIPS32O2: .LtestCondFallthroughToNextBlock$fallthrough
-; MIPS32O2: jal {{.*}} dummy
-; MIPS32O2: nop
-; MIPS32O2: jr
-; MIPS32O2: nop
-; MIPS32O2: .LtestCondFallthroughToNextBlock$target
-; MIPS32O2: jal {{.*}} dummy
-; MIPS32O2: nop
-; MIPS32O2: jr
-; MIPS32O2: nop
-
-; MIPS32OM1-LABEL: testCondFallthroughToNextBlock
-; MIPS32OM1: li {{.*}},123
-; MIPS32OM1: slt {{.*}},{{.*}},{{.*}}
-; MIPS32OM1: xori {{.*}},{{.*}},{{.*}}
-; MIPS32OM1: beqz
-; MIPS32OM1: nop
-; MIPS32OM1: b
-; MIPS32OM1: nop
-; MIPS32OM1: .LtestCondFallthroughToNextBlock$fallthrough
-; MIPS32OM1: jal {{.*}} dummy
-; MIPS32OM1: nop
-; MIPS32OM1: jr
-; MIPS32OM1: nop
-; MIPS32OM1: .LtestCondFallthroughToNextBlock$target
-; MIPS32OM1: jal {{.*}} dummy
-; MIPS32OM1: nop
-; MIPS32OM1: jr
-; MIPS32OM1: nop
-
-; For a conditional branch with the next block as the target and a
-; different block as the fallthrough, the branch condition should be
-; inverted, the fallthrough block changed to the target, and the
-; branch to the next block removed.
-define internal void @testCondTargetNextBlock(i32 %arg) {
-entry:
- %cmp = icmp sge i32 %arg, 123
- br i1 %cmp, label %fallthrough, label %target
-fallthrough:
- call void @dummy()
- ret void
-target:
- call void @dummy()
- ret void
-}
-; O2-LABEL: testCondTargetNextBlock
-; O2: cmp {{.*}},0x7b
-; O2-NEXT: jl
-; O2-NOT: j
-; O2: call
-; O2: ret
-; O2: call
-; O2: ret
-
-; OM1-LABEL: testCondTargetNextBlock
-; OM1: cmp {{.*}},0x7b
-; OM1: setge
-; OM1: cmp
-; OM1: jne
-; OM1: jmp
-; OM1: call
-; OM1: ret
-; OM1: call
-; OM1: ret
-
-; Note that compare and branch folding isn't implemented yet
-; (compared to x86-32).
-; ARM32O2-LABEL: testCondTargetNextBlock
-; ARM32O2: cmp {{.*}}, #123
-; ARM32O2-NEXT: blt
-; ARM32O2-NEXT: bl
-; ARM32O2: bx lr
-; ARM32O2: bl
-; ARM32O2: bx lr
-
-; ARM32OM1-LABEL: testCondTargetNextBlock
-; ARM32OM1: cmp {{.*}}, #123
-; ARM32OM1: movge {{.*}}, #1
-; ARM32OM1: tst {{.*}}, #1
-; ARM32OM1: bne
-; ARM32OM1: b
-; ARM32OM1: bl
-; ARM32OM1: bx lr
-; ARM32OM1: bl
-; ARM32OM1: bx lr
-
-; MIPS32O2-LABEL: testCondTargetNextBlock
-; MIPS32O2: li {{.*}},123
-; MIPS32O2: slt {{.*}},{{.*}},{{.*}}
-; MIPS32O2: bnez
-; MIPS32O2: nop
-; MIPS32O2: .LtestCondTargetNextBlock$fallthrough
-; MIPS32O2: jal {{.*}} dummy
-; MIPS32O2: nop
-; MIPS32O2: jr
-; MIPS32O2: nop
-; MIPS32O2: .LtestCondTargetNextBlock$target
-; MIPS32O2: jal {{.*}} dummy
-; MIPS32O2: nop
-; MIPS32O2: jr
-; MIPS32O2: nop
-
-; MIPS32OM1-LABEL: testCondTargetNextBlock
-; MIPS32OM1: li {{.*}},123
-; MIPS32OM1: slt {{.*}},{{.*}},{{.*}}
-; MIPS32OM1: xori {{.*}},{{.*}},{{.*}}
-; MIPS32OM1: beqz
-; MIPS32OM1: nop
-; MIPS32OM1: b
-; MIPS32OM1: nop
-; MIPS32OM1: .LtestCondTargetNextBlock$fallthrough
-; MIPS32OM1: jal {{.*}} dummy
-; MIPS32OM1: nop
-; MIPS32OM1: jr
-; MIPS32OM1: nop
-; MIPS32OM1: .LtestCondTargetNextBlock$target
-; MIPS32OM1: jal {{.*}} dummy
-; MIPS32OM1: nop
-; MIPS32OM1: jr
-; MIPS32OM1: nop
-
-; Unconditional branches to the block after a contracted block should be
-; removed.
-define internal void @testUncondToBlockAfterContract() {
-entry:
- call void @dummy()
- br label %target
-contract:
- br label %target
-target:
- call void @dummy()
- ret void
-}
-
-; O2-LABEL: testUncondToBlockAfterContract
-; O2: call
-; There will be nops for bundle align to end (for NaCl), but there should
-; not be a branch.
-; O2-NOT: j
-; O2: call
-
-; OM1-LABEL: testUncondToBlockAfterContract
-; OM1: call
-; OM1-NEXT: jmp
-; OM1: call
-
-; ARM32O2-LABEL: testUncondToBlockAfterContract
-; ARM32O2: bl {{.*}} dummy
-; ARM32O2-NEXT: bl {{.*}} dummy
-
-; ARM32OM1-LABEL: testUncondToBlockAfterContract
-; ARM32OM1: bl {{.*}} dummy
-; ARM32OM1-NEXT: b
-; ARM32OM1-NEXT: bl {{.*}} dummy
-
-; MIPS32O2-LABEL: testUncondToBlockAfterContract
-; MIPS32O2: jal {{.*}} dummy
-; MIPS32O2: .LtestUncondToBlockAfterContract$target
-
-; MIPS32OM1-LABEL: testUncondToBlockAfterContract
-; MIPS32OM1: jal {{.*}} dummy
-; MIPS32OM1: b
-; MIPS32OM1: .LtestUncondToBlockAfterContract$target
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/branch-simple.ll b/third_party/subzero/tests_lit/llvm2ice_tests/branch-simple.ll
deleted file mode 100644
index cbe495d..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/branch-simple.ll
+++ /dev/null
@@ -1,37 +0,0 @@
-; 1. Trivial smoke test of compare and branch, with multiple basic
-; blocks.
-; 2. For a conditional branch on a constant boolean value, make sure
-; we don't lower to a cmp instructions with an immediate as the first
-; source operand.
-
-; REQUIRES: allow_dump
-
-; RUN: %p2i -i %s --args -O2 --verbose inst -threads=0 | FileCheck %s
-; RUN: %p2i -i %s --args -Om1 --verbose inst -threads=0 | FileCheck %s
-
-define internal i32 @simple_cond_branch(i32 %foo, i32 %bar) {
-entry:
- %r1 = icmp eq i32 %foo, %bar
- br i1 %r1, label %Equal, label %Unequal
-Equal:
- ret i32 %foo
-Unequal:
- ret i32 %bar
-; CHECK-LABEL: simple_cond_branch
-; CHECK: br i1 %r1, label %Equal, label %Unequal
-; CHECK: Equal:
-; CHECK: ret i32 %foo
-; CHECK: Unequal:
-; CHECK: ret i32 %bar
-}
-
-define internal i32 @test_br_const() {
-__0:
- br i1 true, label %__1, label %__2
-__1:
- ret i32 21
-__2:
- ret i32 43
-}
-; CHECK-LABEL: test_br_const
-; CHECK-NOT: cmp {{[0-9]*}},
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/callArgs.ll b/third_party/subzero/tests_lit/llvm2ice_tests/callArgs.ll
deleted file mode 100644
index 3aa402d..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/callArgs.ll
+++ /dev/null
@@ -1,54 +0,0 @@
-; RUN: %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command %p2i --filetype=asm --assemble \
-; RUN: --disassemble --target mips32 -i %s --args -O2 \
-; RUN: -allow-externally-defined-symbols \
-; RUN: | %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command FileCheck --check-prefix MIPS32 %s
-
-
-
-declare void @voidCall5i32(i32 %a1, i32 %a2, i32 %a3, i32 %a4, i32 %a5)
-declare void @voidCall5i64(i64 %a1, i64 %a2, i64 %a3, i64 %a4, i64 %a5)
-declare void @voidCalli32i64i32(i32 %a1, i64 %a2, i32 %a3)
-
-;TODO(mohit.bhakkad): Add tests for f32/f64 once legalize() or lowerArgument is
-;available for f32/f64
-
-define internal void @Call() {
- call void @voidCall5i32(i32 1, i32 2, i32 3, i32 4, i32 5)
- call void @voidCall5i64(i64 1, i64 2, i64 3, i64 4, i64 5)
- call void @voidCalli32i64i32(i32 1, i64 2, i32 3)
- ret void
-}
-; MIPS32: li {{.*}},5
-; MIPS32: sw {{.*}},16(sp)
-; MIPS32: li a0,1
-; MIPS32: li a1,2
-; MIPS32: li a2,3
-; MIPS32: li a3,4
-; MIPS32: jal
-
-; MIPS32: li {{.*}},0
-; MIPS32: li {{.*}},3
-; MIPS32: sw {{.*}},20(sp)
-; MIPS32: sw {{.*}},16(sp)
-; MIPS32: li {{.*}},0
-; MIPS32: li {{.*}},4
-; MIPS32: sw {{.*}},28(sp)
-; MIPS32: sw {{.*}},24(sp)
-; MIPS32: li {{.*}},0
-; MIPS32: li {{.*}},5
-; MIPS32: sw {{.*}},36(sp)
-; MIPS32: sw {{.*}},32(sp)
-; MIPS32: li a0,1
-; MIPS32: li a1,0
-; MIPS32: li a2,2
-; MIPS32: li a3,0
-; MIPS32: jal
-
-; MIPS32: li {{.*}},3
-; MIPS32: sw {{.*}},16(sp)
-; MIPS32: li a0,1
-; MIPS32: li a2,2
-; MIPS32: li a3,0
-; MIPS32: jal
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/callindirect.pnacl.ll b/third_party/subzero/tests_lit/llvm2ice_tests/callindirect.pnacl.ll
deleted file mode 100644
index fded7f4..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/callindirect.pnacl.ll
+++ /dev/null
@@ -1,209 +0,0 @@
-; Test of multiple indirect calls to the same target. Each call
-; should be to the same operand, whether it's in a register or on the
-; stack.
-
-; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
-; RUN: --target x8632 -i %s --args -O2 \
-; RUN: | %if --need=target_X8632 --command FileCheck %s
-; RUN: %if --need=allow_dump --need=target_X8632 --command %p2i --filetype=asm \
-; RUN: --assemble --disassemble -i %s --args -O2 \
-; RUN: | %if --need=allow_dump --need=target_X8632 --command FileCheck %s
-; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
-; RUN: --target x8632 -i %s --args -Om1 \
-; RUN: | %if --need=target_X8632 --command FileCheck --check-prefix=OPTM1 %s
-
-; RUN: %if --need=target_X8664 --command %p2i --filetype=obj --disassemble \
-; RUN: --target x8664 -i %s --args -O2 \
-; RUN: | %if --need=target_X8664 --command FileCheck --check-prefix X8664 %s
-; RUN: %if --need=allow_dump --need=target_X8664 --command %p2i --filetype=asm \
-; RUN: --assemble --disassemble --target x8664 -i %s --args -O2 \
-; RUN: | %if --need=allow_dump --need=target_X8664 \
-; RUN: --command FileCheck --check-prefix=X8664 %s
-; RUN: %if --need=target_X8664 --command %p2i --filetype=obj --disassemble \
-; RUN: --target x8664 -i %s --args -Om1 \
-; RUN: | %if --need=target_X8664 \
-; RUN: --command FileCheck --check-prefix=X8664-OPTM1 %s
-
-; RUN: %if --need=target_ARM32 \
-; RUN: --command %p2i --filetype=obj \
-; RUN: --disassemble --target arm32 -i %s --args -O2 \
-; RUN: | %if --need=target_ARM32 \
-; RUN: --command FileCheck --check-prefix ARM32 %s
-; RUN: %if --need=target_ARM32 \
-; RUN: --command %p2i --filetype=obj \
-; RUN: --disassemble --target arm32 -i %s --args -Om1 \
-; RUN: | %if --need=target_ARM32_dump \
-; RUN: --command FileCheck --check-prefix ARM32 %s
-
-; RUN: %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command %p2i --filetype=asm --assemble --disassemble --target \
-; RUN: mips32 -i %s --args -O2 -allow-externally-defined-symbols \
-; RUN: | %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command FileCheck --check-prefix MIPS32 %s
-
-@__init_array_start = internal constant [0 x i8] zeroinitializer, align 4
-@__fini_array_start = internal constant [0 x i8] zeroinitializer, align 4
-@__tls_template_start = internal constant [0 x i8] zeroinitializer, align 8
-@__tls_template_alignment = internal constant [4 x i8] c"\01\00\00\00", align 4
-
-define internal void @CallIndirect(i32 %f) {
-entry:
- %__1 = inttoptr i32 %f to void ()*
- call void %__1()
- call void %__1()
- call void %__1()
- call void %__1()
- call void %__1()
- call void %__1()
- ret void
-}
-; CHECK-LABEL: CallIndirect
-; Use the first call as a barrier in case the register allocator decides to use
-; a scratch register for it but a common preserved register for the rest.
-; CHECK: call
-; CHECK: call [[REGISTER:[a-z]+]]
-; CHECK: call [[REGISTER]]
-; CHECK: call [[REGISTER]]
-; CHECK: call [[REGISTER]]
-; CHECK: call [[REGISTER]]
-;
-; OPTM1-LABEL: CallIndirect
-; OPTM1: call [[TARGET:.+]]
-; OPTM1: call [[TARGET]]
-; OPTM1: call [[TARGET]]
-; OPTM1: call [[TARGET]]
-; OPTM1: call [[TARGET]]
-;
-; X8664-LABEL: CallIndirect
-; Use the first call as a barrier so we skip the movs in the function prolog.
-; X8664: call r{{..}}
-; X8664: mov e[[REG:..]],
-; X8664-NEXT: call r[[REG]]
-; X8664: mov e[[REG:..]],
-; X8664-NEXT: call r[[REG]]
-; X8664: mov e[[REG:..]],
-; X8664-NEXT: call r[[REG]]
-; X8664: call r{{..}}
-;
-; X8664-OPTM1-LABEL: CallIndirect
-; X8664-OPTM1: mov e[[REG:..]],DWORD PTR
-; X8664-OPTM1: call r[[REG]]
-; X8664-OPTM1: mov e[[REG:..]],DWORD PTR
-; X8664-OPTM1: call r[[REG]]
-; X8664-OPTM1: mov e[[REG:..]],DWORD PTR
-; X8664-OPTM1: call r[[REG]]
-; X8664-OPTM1: mov e[[REG:..]],DWORD PTR
-; X8664-OPTM1: call r[[REG]]
-; X8664-OPTM1: mov e[[REG:..]],DWORD PTR
-; X8664-OPTM1: call r[[REG]]
-;
-; ARM32-LABEL: CallIndirect
-; ARM32: blx [[REGISTER:r.*]]
-; ARM32: blx [[REGISTER]]
-; ARM32: blx [[REGISTER]]
-; ARM32: blx [[REGISTER]]
-; ARM32: blx [[REGISTER]]
-
-; MIPS32-LABEL: CallIndirect
-; MIPS32: jalr [[REGISTER:.*]]
-; MIPS32: jalr [[REGISTER]]
-; MIPS32: jalr [[REGISTER]]
-; MIPS32: jalr [[REGISTER]]
-
-@fp_v = internal global [4 x i8] zeroinitializer, align 4
-
-define internal void @CallIndirectGlobal() {
-entry:
- %fp_ptr_i32 = bitcast [4 x i8]* @fp_v to i32*
- %fp_ptr = load i32, i32* %fp_ptr_i32, align 1
- %fp = inttoptr i32 %fp_ptr to void ()*
- call void %fp()
- call void %fp()
- call void %fp()
- call void %fp()
- ret void
-}
-; CHECK-LABEL: CallIndirectGlobal
-; Allow the first call to be to a different register because of simple
-; availability optimization.
-; CHECK: call
-; CHECK: call [[REGISTER:[a-z]+]]
-; CHECK: call [[REGISTER]]
-; CHECK: call [[REGISTER]]
-;
-; OPTM1-LABEL: CallIndirectGlobal
-; OPTM1: call [[TARGET:.+]]
-; OPTM1: call [[TARGET]]
-; OPTM1: call [[TARGET]]
-; OPTM1: call [[TARGET]]
-;
-; X8664-LABEL: CallIndirectGlobal
-; X8664: call r[[REG]]
-; X8664: mov e[[REG:..]]
-; X8664-NEXT: call r[[REG]]
-; X8664: mov e[[REG:..]]
-; X8664-NEXT: call r[[REG]]
-; X8664: call r{{..}}
-;
-; X8664-OPTM1-LABEL: CallIndirectGlobal
-; X8664-OPTM1: mov e[[REG:..]],DWORD PTR
-; X8664-OPTM1: call r[[REG]]
-; X8664-OPTM1: mov e[[REG:..]],DWORD PTR
-; X8664-OPTM1: call r[[REG]]
-; X8664-OPTM1: mov e[[REG:..]],DWORD PTR
-; X8664-OPTM1: call r[[REG]]
-; X8664-OPTM1: mov e[[REG:..]],DWORD PTR
-; X8664-OPTM1: call r[[REG]]
-;
-; ARM32-LABEL: CallIndirectGlobal
-; ARM32: blx {{r.*}}
-; ARM32: blx [[REGISTER:r[0-9]*]]
-; ARM32: blx [[REGISTER]]
-; ARM32: blx [[REGISTER]]
-
-; MIPS32-LABEL: CallIndirectGlobal
-; MIPS32: jalr [[REGISTER:.*]]
-; MIPS32: jalr [[REGISTER]]
-; MIPS32: jalr [[REGISTER]]
-; MIPS32: jalr [[REGISTER]]
-
-; Calling an absolute address is used for non-IRT PNaCl pexes to directly
-; access syscall trampolines. This is not really an indirect call, but
-; there is a cast from int to pointer first.
-define internal void @CallConst() {
-entry:
- %__1 = inttoptr i32 66496 to void ()*
- call void %__1()
- call void %__1()
- call void %__1()
- ret void
-}
-
-; CHECK-LABEL: CallConst
-; CHECK: e8 bc 03 01 00 call {{[0-9a-f]+}} {{.*}} R_386_PC32 *ABS*
-; CHECK: e8 bc 03 01 00 call {{[0-9a-f]+}} {{.*}} R_386_PC32 *ABS*
-; CHECK: e8 bc 03 01 00 call {{[0-9a-f]+}} {{.*}} R_386_PC32 *ABS*
-;
-; OPTM1-LABEL: CallConst
-; OPTM1: e8 bc 03 01 00 call {{[0-9a-f]+}} {{.*}} R_386_PC32 *ABS*
-; OPTM1: e8 bc 03 01 00 call {{[0-9a-f]+}} {{.*}} R_386_PC32 *ABS*
-; OPTM1: e8 bc 03 01 00 call {{[0-9a-f]+}} {{.*}} R_386_PC32 *ABS*
-;
-; X8664-LABEL: CallConst
-; TODO(jpp): fix absolute call emission.
-; These are broken: the emitted code should be
-; e8 00 00 00 00 call {{.*}} *ABS*+0x103bc
-;
-; X8664-OPTM1-LABEL: CallConst
-; TODO(jpp): fix absolute call emission.
-; These are broken: the emitted code should be
-; e8 00 00 00 00 call {{.*}} *ABS*+0x103bc
-;
-; ARM32-LABEL: CallConst
-; ARM32: movw [[REGISTER:r.*]], #960
-; ARM32: movt [[REGISTER]], #1
-; ARM32: blx [[REGISTER]]
-; The legalization of the constant could be shared, but it isn't.
-; ARM32: movw [[REGISTER:r.*]], #960
-; ARM32: blx [[REGISTER]]
-; ARM32: blx [[REGISTER]]
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/cmp-opt.ll b/third_party/subzero/tests_lit/llvm2ice_tests/cmp-opt.ll
deleted file mode 100644
index fefd226..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/cmp-opt.ll
+++ /dev/null
@@ -1,55 +0,0 @@
-; Simple test of non-fused compare/branch.
-
-; RUN: %p2i --filetype=obj --disassemble -i %s --args -O2 \
-; RUN: -allow-externally-defined-symbols | FileCheck %s
-; RUN: %p2i --filetype=obj --disassemble -i %s --args -Om1 \
-; RUN: -allow-externally-defined-symbols | FileCheck --check-prefix=OPTM1 %s
-
-define internal void @testBool(i32 %a, i32 %b) {
-entry:
- %cmp = icmp slt i32 %a, %b
- %cmp1 = icmp sgt i32 %a, %b
- br i1 %cmp, label %if.then, label %if.end
-
-if.then: ; preds = %entry
- %cmp_ext = zext i1 %cmp to i32
- tail call void @use(i32 %cmp_ext)
- br label %if.end
-
-if.end: ; preds = %if.then, %entry
- br i1 %cmp1, label %if.then5, label %if.end7
-
-if.then5: ; preds = %if.end
- %cmp1_ext = zext i1 %cmp1 to i32
- tail call void @use(i32 %cmp1_ext)
- br label %if.end7
-
-if.end7: ; preds = %if.then5, %if.end
- ret void
-}
-
-declare void @use(i32)
-
-; CHECK-LABEL: testBool
-; Two bool computations
-; CHECK: cmp
-; CHECK: cmp
-; Test first bool
-; CHECK: cmp
-; CHECK: call
-; Test second bool
-; CHECK: cmp
-; CHECK: call
-; CHECK: ret
-;
-; OPTM1-LABEL: testBool
-; Two bool computations
-; OPTM1: cmp
-; OPTM1: cmp
-; Test first bool
-; OPTM1: cmp
-; OPTM1: call
-; Test second bool
-; OPTM1: cmp
-; OPTM1: call
-; OPTM1: ret
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/commutativity.ll b/third_party/subzero/tests_lit/llvm2ice_tests/commutativity.ll
deleted file mode 100644
index ca5f6c7..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/commutativity.ll
+++ /dev/null
@@ -1,145 +0,0 @@
-; Test the lowering sequence for commutative operations. If there is a source
-; operand whose lifetime ends in an operation, it should be the first operand,
-; eliminating the need for a move to start the new lifetime.
-
-; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
-; RUN: --target x8632 -i %s --args -O2 \
-; RUN: | %if --need=target_X8632 --command FileCheck %s
-
-; RUN: %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command %p2i --filetype=asm --assemble --disassemble --target \
-; RUN: mips32 -i %s --args -O2 -allow-externally-defined-symbols \
-; RUN: | %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command FileCheck --check-prefix MIPS32 %s
-
-define internal i32 @integerAddLeft(i32 %a, i32 %b) {
-entry:
- %tmp = add i32 %a, %b
- %result = add i32 %a, %tmp
- ret i32 %result
-}
-; CHECK-LABEL: integerAddLeft
-; CHECK-NEXT: mov {{e..}},DWORD PTR
-; CHECK-NEXT: mov {{e..}},DWORD PTR
-; CHECK-NEXT: add {{e..}},{{e..}}
-; CHECK-NEXT: add {{e..}},{{e..}}
-; MIPS32-LABEL: integerAddLeft
-; MIPS32: move v0,a0
-; MIPS32: addu v0,v0,a1
-; MIPS32: addu a0,a0,v0
-
-define internal i32 @integerAddRight(i32 %a, i32 %b) {
-entry:
- %tmp = add i32 %a, %b
- %result = add i32 %b, %tmp
- ret i32 %result
-}
-; CHECK-LABEL: integerAddRight
-; CHECK-NEXT: mov {{e..}},DWORD PTR
-; CHECK-NEXT: mov {{e..}},DWORD PTR
-; CHECK-NEXT: add {{e..}},{{e..}}
-; CHECK-NEXT: add {{e..}},{{e..}}
-; MIPS32-LABEL: integerAddRight
-; MIPS32: move v0,a1
-; MIPS32: addu a0,a0,v0
-; MIPS32: addu a1,a1,a0
-
-define internal i32 @integerMultiplyLeft(i32 %a, i32 %b) {
-entry:
- %tmp = mul i32 %a, %b
- %result = mul i32 %a, %tmp
- ret i32 %result
-}
-; CHECK-LABEL: integerMultiplyLeft
-; CHECK-NEXT: mov {{e..}},DWORD PTR
-; CHECK-NEXT: mov {{e..}},DWORD PTR
-; CHECK-NEXT: imul {{e..}},{{e..}}
-; CHECK-NEXT: imul {{e..}},{{e..}}
-; MIPS32-LABEL: integerMultiplyLeft
-; MIPS32: move v0,a0
-; MIPS32: mul v0,v0,a1
-; MIPS32: mul a0,a0,v0
-
-define internal i32 @integerMultiplyRight(i32 %a, i32 %b) {
-entry:
- %tmp = mul i32 %a, %b
- %result = mul i32 %b, %tmp
- ret i32 %result
-}
-; CHECK-LABEL: integerMultiplyRight
-; CHECK-NEXT: mov {{e..}},DWORD PTR
-; CHECK-NEXT: mov {{e..}},DWORD PTR
-; CHECK-NEXT: imul {{e..}},{{e..}}
-; CHECK-NEXT: imul {{e..}},{{e..}}
-; MIPS32-LABEL: integerMultiplyRight
-; MIPS32: move v0,a1
-; MIPS32: mul a0,a0,v0
-; MIPS32: mul a1,a1,a0
-
-define internal float @floatAddLeft(float %a, float %b) {
-entry:
- %tmp = fadd float %a, %b
- %result = fadd float %a, %tmp
- ret float %result
-}
-; CHECK-LABEL: floatAddLeft
-; CHECK-NEXT: sub esp,0x1c
-; CHECK-NEXT: movss xmm0,DWORD PTR
-; CHECK-NEXT: movss xmm1,DWORD PTR
-; CHECK-NEXT: addss xmm1,xmm0
-; CHECK-NEXT: addss xmm0,xmm1
-; MIPS32-LABEL: floatAddLeft
-; MIPS32: mov.s $f0,$f12
-; MIPS32: add.s $f0,$f0,$f14
-; MIPS32: add.s $f12,$f12,$f0
-
-define internal float @floatAddRight(float %a, float %b) {
-entry:
- %tmp = fadd float %a, %b
- %result = fadd float %b, %tmp
- ret float %result
-}
-; CHECK-LABEL: floatAddRight
-; CHECK-NEXT: sub esp,0x1c
-; CHECK-NEXT: movss xmm0,DWORD PTR
-; CHECK-NEXT: movss xmm1,DWORD PTR
-; CHECK-NEXT: addss xmm0,xmm1
-; CHECK-NEXT: addss xmm1,xmm0
-; MIPS32-LABEL: floatAddRight
-; MIPS32: mov.s $f0,$f14
-; MIPS32: add.s $f12,$f12,$f0
-; MIPS32: add.s $f14,$f14,$f12
-
-define internal float @floatMultiplyLeft(float %a, float %b) {
-entry:
- %tmp = fmul float %a, %b
- %result = fmul float %a, %tmp
- ret float %result
-}
-; CHECK-LABEL: floatMultiplyLeft
-; CHECK-NEXT: sub esp,0x1c
-; CHECK-NEXT: movss xmm0,DWORD PTR
-; CHECK-NEXT: movss xmm1,DWORD PTR
-; CHECK-NEXT: mulss xmm1,xmm0
-; CHECK-NEXT: mulss xmm0,xmm1
-; MIPS32-LABEL: floatMultiplyLeft
-; MIPS32: mov.s $f0,$f12
-; MIPS32: mul.s $f0,$f0,$f14
-; MIPS32: mul.s $f12,$f12,$f0
-
-define internal float @floatMultiplyRight(float %a, float %b) {
-entry:
- %tmp = fmul float %a, %b
- %result = fmul float %b, %tmp
- ret float %result
-}
-; CHECK-LABEL: floatMultiplyRight
-; CHECK-NEXT: sub esp,0x1c
-; CHECK-NEXT: movss xmm0,DWORD PTR
-; CHECK-NEXT: movss xmm1,DWORD PTR
-; CHECK-NEXT: mulss xmm0,xmm1
-; CHECK-NEXT: mulss xmm1,xmm0
-; MIPS32-LABEL: floatMultiplyRight
-; MIPS32: mov.s $f0,$f14
-; MIPS32: mul.s $f12,$f12,$f0
-; MIPS32: mul.s $f14,$f14,$f12
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/cond-br-same-target.ll b/third_party/subzero/tests_lit/llvm2ice_tests/cond-br-same-target.ll
deleted file mode 100644
index f4a3876..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/cond-br-same-target.ll
+++ /dev/null
@@ -1,23 +0,0 @@
-; Test conditional branch where targets are the same.
-; Tests issue: https://code.google.com/p/nativeclient/issues/detail?id=4212
-; REQUIRES: allow_dump
-
-; RUN: %p2i -i %s --insts | FileCheck %s
-
-define internal void @f(i32 %foo, i32 %bar) {
-entry:
- %c = icmp ult i32 %foo, %bar
- br i1 %c, label %block, label %block
-block:
- ret void
-}
-
-; Note that the branch is converted to an unconditional branch.
-
-; CHECK: define internal void @f(i32 %foo, i32 %bar) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %c = icmp ult i32 %foo, %bar
-; CHECK-NEXT: br label %block
-; CHECK-NEXT: block:
-; CHECK-NEXT: ret void
-; CHECK-NEXT: }
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/cond-branch.ll b/third_party/subzero/tests_lit/llvm2ice_tests/cond-branch.ll
deleted file mode 100644
index d601056..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/cond-branch.ll
+++ /dev/null
@@ -1,187 +0,0 @@
-; Tests for conditional branch instructions
-
-; RUN: %if --need=allow_dump --need=target_MIPS32 --command %p2i \
-; RUN: --filetype=asm --target mips32 -i %s --args -O2 \
-; RUN: -allow-externally-defined-symbols \
-; RUN: | %if --need=allow_dump --need=target_MIPS32 --command FileCheck %s \
-; RUN: --check-prefix=COMMON --check-prefix=MIPS32
-
-; RUN: %if --need=allow_dump --need=target_MIPS32 --command %p2i \
-; RUN: --filetype=asm --target mips32 -i %s --args -Om1 \
-; RUN: -allow-externally-defined-symbols \
-; RUN: | %if --need=allow_dump --need=target_MIPS32 --command FileCheck %s \
-; RUN: --check-prefix=COMMON --check-prefix=MIPS32-OM1
-
-define internal i32 @cond_br_eq(i32 %arg1, i32 %arg2) {
-entry:
- %cmp1 = icmp eq i32 %arg1, %arg2
- br i1 %cmp1, label %branch1, label %branch2
-branch1:
- ret i32 1
-branch2:
- ret i32 2
-}
-; COMMON-LABEL: cond_br_eq
-; MIPS32: bne {{.*}} .Lcond_br_eq$branch2
-; MIPS32-NEXT: .Lcond_br_eq$branch1
-; MIPS32-OM1: xor
-; MIPS32-OM1: sltiu {{.*}}, {{.*}}, 1
-; MIPS32-OM1: beqz {{.*}} .Lcond_br_eq$branch2
-; MIPS32-OM1-NEXT: b .Lcond_br_eq$branch1
-
-define internal i32 @cond_br_ne(i32 %arg1, i32 %arg2) {
-entry:
- %cmp1 = icmp ne i32 %arg1, %arg2
- br i1 %cmp1, label %branch1, label %branch2
-branch1:
- ret i32 1
-branch2:
- ret i32 2
-}
-; COMMON-LABEL: cond_br_ne
-; MIPS32: beq {{.*}} .Lcond_br_ne$branch2
-; MIPS32-NEXT: .Lcond_br_ne$branch1
-; MIPS32-OM1: xor
-; MIPS32-OM1: sltu {{.*}}, $zero, {{.*}}
-; MIPS32-OM1: beqz {{.*}} .Lcond_br_ne$branch2
-; MIPS32-OM1-NEXT: b .Lcond_br_ne$branch1
-
-define internal i32 @cond_br_slt(i32 %arg1, i32 %arg2) {
-entry:
- %cmp1 = icmp slt i32 %arg1, %arg2
- br i1 %cmp1, label %branch1, label %branch2
-branch1:
- ret i32 1
-branch2:
- ret i32 2
-}
-; COMMON-LABEL: cond_br_slt
-; MIPS32: slt
-; MIPS32: beqz {{.*}} .Lcond_br_slt$branch2
-; MIPS32-NEXT: .Lcond_br_slt$branch1
-; MIPS32-OM1: slt
-; MIPS32-OM1: beqz {{.*}} .Lcond_br_slt$branch2
-; MIPS32-OM1-NEXT: b .Lcond_br_slt$branch1
-
-define internal i32 @cond_br_sle(i32 %arg1, i32 %arg2) {
-entry:
- %cmp1 = icmp sle i32 %arg1, %arg2
- br i1 %cmp1, label %branch1, label %branch2
-branch1:
- ret i32 1
-branch2:
- ret i32 2
-}
-; COMMON-LABEL: cond_br_sle
-; MIPS32: slt
-; MIPS32: bnez {{.*}} .Lcond_br_sle$branch2
-; MIPS32-NEXT: .Lcond_br_sle$branch1
-; MIPS32-OM1: slt
-; MIPS32-OM1: xori {{.*}}, {{.*}}, 1
-; MIPS32-OM1: beqz {{.*}} .Lcond_br_sle$branch2
-; MIPS32-OM1-NEXT: b .Lcond_br_sle$branch1
-
-define internal i32 @cond_br_sgt(i32 %arg1, i32 %arg2) {
-entry:
- %cmp1 = icmp sgt i32 %arg1, %arg2
- br i1 %cmp1, label %branch1, label %branch2
-branch1:
- ret i32 1
-branch2:
- ret i32 2
-}
-; COMMON-LABEL: cond_br_sgt
-; MIPS32: slt
-; MIPS32-NEXT: beqz {{.*}} .Lcond_br_sgt$branch2
-; MIPS32-NEXT: .Lcond_br_sgt$branch1
-; MIPS32-OM1: slt
-; MIPS32-OM1: beqz {{.*}} .Lcond_br_sgt$branch2
-; MIPS32-OM1-NEXT: b .Lcond_br_sgt$branch1
-
-define internal i32 @cond_br_sge(i32 %arg1, i32 %arg2) {
-entry:
- %cmp1 = icmp sge i32 %arg1, %arg2
- br i1 %cmp1, label %branch1, label %branch2
-branch1:
- ret i32 1
-branch2:
- ret i32 2
-}
-; COMMON-LABEL: cond_br_sge
-; MIPS32: slt
-; MIPS32: bnez {{.*}} .Lcond_br_sge$branch2
-; MIPS32-NEXT: .Lcond_br_sge$branch1
-; MIPS32-OM1: slt
-; MIPS32-OM1: xori {{.*}}, {{.*}}, 1
-; MIPS32-OM1: beqz {{.*}} .Lcond_br_sge$branch2
-; MIPS32-OM1-NEXT: b .Lcond_br_sge$branch1
-
-define internal i32 @cond_br_ugt(i32 %arg1, i32 %arg2) {
-entry:
- %cmp1 = icmp ugt i32 %arg1, %arg2
- br i1 %cmp1, label %branch1, label %branch2
-branch1:
- ret i32 1
-branch2:
- ret i32 2
-}
-; COMMON-LABEL: cond_br_ugt
-; MIPS32: sltu
-; MIPS32: beqz {{.*}} .Lcond_br_ugt$branch2
-; MIPS32-NEXT: .Lcond_br_ugt$branch1
-; MIPS32-OM1: sltu
-; MIPS32-OM1: beqz {{.*}} .Lcond_br_ugt$branch2
-; MIPS32-OM1-NEXT: b .Lcond_br_ugt$branch1
-
-define internal i32 @cond_br_uge(i32 %arg1, i32 %arg2) {
-entry:
- %cmp1 = icmp uge i32 %arg1, %arg2
- br i1 %cmp1, label %branch1, label %branch2
-branch1:
- ret i32 1
-branch2:
- ret i32 2
-}
-; COMMON-LABEL: cond_br_uge
-; MIPS32: sltu
-; MIPS32: bnez {{.*}} .Lcond_br_uge$branch2
-; MIPS32-NEXT: .Lcond_br_uge$branch1
-; MIPS32-OM1: sltu
-; MIPS32-OM1: xori {{.*}}, {{.*}}, 1
-; MIPS32-OM1: beqz {{.*}} .Lcond_br_uge$branch2
-; MIPS32-OM1-NEXT: b .Lcond_br_uge$branch1
-
-define internal i32 @cond_br_ult(i32 %arg1, i32 %arg2) {
-entry:
- %cmp1 = icmp ult i32 %arg1, %arg2
- br i1 %cmp1, label %branch1, label %branch2
-branch1:
- ret i32 1
-branch2:
- ret i32 2
-}
-; COMMON-LABEL: cond_br_ult
-; MIPS32: sltu
-; MIPS32: beqz {{.*}} .Lcond_br_ult$branch2
-; MIPS32-NEXT: .Lcond_br_ult$branch1
-; MIPS32-OM1: sltu
-; MIPS32-OM1: beqz {{.*}} .Lcond_br_ult$branch2
-; MIPS32-OM1-NEXT: b .Lcond_br_ult$branch1
-
-define internal i32 @cond_br_ule(i32 %arg1, i32 %arg2) {
-entry:
- %cmp1 = icmp ule i32 %arg1, %arg2
- br i1 %cmp1, label %branch1, label %branch2
-branch1:
- ret i32 1
-branch2:
- ret i32 2
-}
-; COMMON-LABEL: cond_br_ule
-; MIPS32: sltu
-; MIPS32: bnez {{.*}} .Lcond_br_ule$branch2
-; MIPS32-NEXT: .Lcond_br_ule$branch1
-; MIPS32-OM1: sltu
-; MIPS32-OM1: xori {{.*}}, {{.*}}, 1
-; MIPS32-OM1: beqz {{.*}} .Lcond_br_ule$branch2
-; MIPS32-OM1-NEXT: b .Lcond_br_ule$branch1
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/contract.ll b/third_party/subzero/tests_lit/llvm2ice_tests/contract.ll
deleted file mode 100644
index 499ab69..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/contract.ll
+++ /dev/null
@@ -1,17 +0,0 @@
-; This tests that an empty node pointing to itself is not contracted.
-; https://code.google.com/p/nativeclient/issues/detail?id=4307
-;
-; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 \
-; RUN: | FileCheck %s
-
-define internal void @SimpleBranch() {
-label0:
- br label %label2
-label1:
- br label %label1
-label2:
- br label %label1
-}
-
-; CHECK-LABEL: SimpleBranch
-; CHECK-NEXT: jmp 0 <SimpleBranch>
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/convert.ll b/third_party/subzero/tests_lit/llvm2ice_tests/convert.ll
deleted file mode 100644
index 743cdad..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/convert.ll
+++ /dev/null
@@ -1,459 +0,0 @@
-; Simple test of signed and unsigned integer conversions.
-
-; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
-; RUN: --target x8632 -i %s --args -O2 \
-; RUN: | %if --need=target_X8632 --command FileCheck %s
-
-; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
-; RUN: --target x8632 -i %s --args -Om1 \
-; RUN: | %if --need=target_X8632 --command FileCheck %s
-
-; RUN: %if --need=target_ARM32 \
-; RUN: --command %p2i --filetype=obj \
-; RUN: --disassemble --target arm32 -i %s --args -O2 \
-; RUN: | %if --need=target_ARM32 \
-; RUN: --command FileCheck --check-prefix ARM32 %s
-
-; RUN: %if --need=target_ARM32 \
-; RUN: --command %p2i --filetype=obj \
-; RUN: --disassemble --target arm32 -i %s --args -Om1 \
-; RUN: | %if --need=target_ARM32 \
-; RUN: --command FileCheck --check-prefix ARM32 %s
-
-; RUN: %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command %p2i --filetype=asm --assemble --disassemble --target \
-; RUN: mips32 -i %s --args -O2 -allow-externally-defined-symbols \
-; RUN: | %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command FileCheck --check-prefix MIPS32 %s
-
-@i8v = internal global [1 x i8] zeroinitializer, align 1
-@i16v = internal global [2 x i8] zeroinitializer, align 2
-@i32v = internal global [4 x i8] zeroinitializer, align 4
-@i64v = internal global [8 x i8] zeroinitializer, align 8
-@u8v = internal global [1 x i8] zeroinitializer, align 1
-@u16v = internal global [2 x i8] zeroinitializer, align 2
-@u32v = internal global [4 x i8] zeroinitializer, align 4
-@u64v = internal global [8 x i8] zeroinitializer, align 8
-
-define internal void @from_int8() {
-entry:
- %__0 = bitcast [1 x i8]* @i8v to i8*
- %v0 = load i8, i8* %__0, align 1
- %v1 = sext i8 %v0 to i16
- %__3 = bitcast [2 x i8]* @i16v to i16*
- store i16 %v1, i16* %__3, align 1
- %v2 = sext i8 %v0 to i32
- %__5 = bitcast [4 x i8]* @i32v to i32*
- store i32 %v2, i32* %__5, align 1
- %v3 = sext i8 %v0 to i64
- %__7 = bitcast [8 x i8]* @i64v to i64*
- store i64 %v3, i64* %__7, align 1
- ret void
-}
-; CHECK-LABEL: from_int8
-; CHECK: mov {{.*}},{{(BYTE PTR)?}}
-; CHECK: movsx {{.*}},{{[a-d]l|BYTE PTR}}
-; CHECK: mov {{(WORD PTR)?}}
-; CHECK: movsx
-; CHECK: mov {{(DWORD PTR)?}}
-; CHECK: movsx
-; CHECK: sar {{.*}},0x1f
-; CHECK-DAG: ds:0x{{.}},{{.*}}{{i64v|.bss}}
-; CHECK-DAG: ds:0x{{.}},{{.*}}{{i64v|.bss}}
-
-; ARM32-LABEL: from_int8
-; ARM32: movw {{.*}}i8v
-; ARM32: ldrb
-; ARM32: sxtb
-; ARM32: movw {{.*}}i16v
-; ARM32: strh
-; ARM32: sxtb
-; ARM32: movw {{.*}}i32v
-; ARM32: str r
-; ARM32: sxtb
-; ARM32: asr
-; ARM32: movw {{.*}}i64v
-; ARM32-DAG: str r{{.*}}, [r{{[0-9]+}}]
-; ARM32-DAG: str r{{.*}}, [{{.*}}, #4]
-
-; MIPS32-LABEL: from_int8
-; MIPS32: lui {{.*}} i8v
-; MIPS32: addiu {{.*}} i8v
-; MIPS32: lb
-; MIPS32: move
-; MIPS32: sll {{.*}},0x18
-; MIPS32: sra {{.*}},0x18
-; MIPS32: lui {{.*}} i16v
-; MIPS32: addiu {{.*}} i16v
-; MIPS32: sh
-; MIPS32: move
-; MIPS32: sll {{.*}},0x18
-; MIPS32: sra {{.*}},0x18
-; MIPS32: lui {{.*}} i32v
-; MIPS32: addiu {{.*}} i32v
-; MIPS32: sw
-; MIPS32: sll {{.*}},0x18
-; MIPS32: sra {{.*}},0x18
-; MIPS32: sra {{.*}},0x1f
-; MIPS32: lui {{.*}} i64v
-; MIPS32: addiu {{.*}} i64v
-
-define internal void @from_int16() {
-entry:
- %__0 = bitcast [2 x i8]* @i16v to i16*
- %v0 = load i16, i16* %__0, align 1
- %v1 = trunc i16 %v0 to i8
- %__3 = bitcast [1 x i8]* @i8v to i8*
- store i8 %v1, i8* %__3, align 1
- %v2 = sext i16 %v0 to i32
- %__5 = bitcast [4 x i8]* @i32v to i32*
- store i32 %v2, i32* %__5, align 1
- %v3 = sext i16 %v0 to i64
- %__7 = bitcast [8 x i8]* @i64v to i64*
- store i64 %v3, i64* %__7, align 1
- ret void
-}
-; CHECK-LABEL: from_int16
-; CHECK: mov {{.*}},{{(WORD PTR)?}}
-; CHECK: 0x{{.}} {{.*}}{{i16v|.bss}}
-; CHECK: movsx e{{.*}},{{.*x|[ds]i|bp|WORD PTR}}
-; CHECK: 0x{{.}},{{.*}}{{i32v|.bss}}
-; CHECK: movsx e{{.*}},{{.*x|[ds]i|bp|WORD PTR}}
-; CHECK: sar {{.*}},0x1f
-; CHECK: 0x{{.}},{{.*}}{{i64v|.bss}}
-
-; ARM32-LABEL: from_int16
-; ARM32: movw {{.*}}i16v
-; ARM32: ldrh
-; ARM32: movw {{.*}}i8v
-; ARM32: strb
-; ARM32: sxth
-; ARM32: movw {{.*}}i32v
-; ARM32: str r
-; ARM32: sxth
-; ARM32: asr
-; ARM32: movw {{.*}}i64v
-; ARM32: str r
-
-; MIPS32-LABEL: from_int16
-; MIPS32: lui {{.*}} i16v
-; MIPS32: addiu {{.*}} i16v
-; MIPS32: lh
-; MIPS32: move
-; MIPS32: lui {{.*}} i8v
-; MIPS32: addiu {{.*}} i8v
-; MIPS32: sb
-; MIPS32: move
-; MIPS32: sll {{.*}},0x10
-; MIPS32: sra {{.*}},0x10
-; MIPS32: lui {{.*}} i32v
-; MIPS32: addiu {{.*}} i32v
-; MIPS32: sw
-; MIPS32: sll {{.*}},0x10
-; MIPS32: sra {{.*}},0x10
-; MIPS32: sra {{.*}},0x1f
-; MIPS32: lui {{.*}} i64v
-; MIPS32: addiu {{.*}} i64v
-
-define internal void @from_int32() {
-entry:
- %__0 = bitcast [4 x i8]* @i32v to i32*
- %v0 = load i32, i32* %__0, align 1
- %v1 = trunc i32 %v0 to i8
- %__3 = bitcast [1 x i8]* @i8v to i8*
- store i8 %v1, i8* %__3, align 1
- %v2 = trunc i32 %v0 to i16
- %__5 = bitcast [2 x i8]* @i16v to i16*
- store i16 %v2, i16* %__5, align 1
- %v3 = sext i32 %v0 to i64
- %__7 = bitcast [8 x i8]* @i64v to i64*
- store i64 %v3, i64* %__7, align 1
- ret void
-}
-; CHECK-LABEL: from_int32
-; CHECK: 0x{{.}} {{.*}} {{i32v|.bss}}
-; CHECK: 0x{{.}},{{.*}} {{i8v|.bss}}
-; CHECK: 0x{{.}},{{.*}} {{i16v|.bss}}
-; CHECK: sar {{.*}},0x1f
-; CHECK: 0x{{.}},{{.*}} {{i64v|.bss}}
-
-; ARM32-LABEL: from_int32
-; ARM32: movw {{.*}}i32v
-; ARM32: ldr r
-; ARM32: movw {{.*}}i8v
-; ARM32: strb
-; ARM32: movw {{.*}}i16v
-; ARM32: strh
-; ARM32: asr
-; ARM32: movw {{.*}}i64v
-; ARM32: str r
-
-; MIPS32-LABEL: from_int32
-; MIPS32: lui {{.*}} i32v
-; MIPS32: addiu {{.*}} i32v
-; MIPS32: lw
-; MIPS32: move
-; MIPS32: lui {{.*}} i8v
-; MIPS32: addiu {{.*}} i8v
-; MIPS32: sb
-; MIPS32: move
-; MIPS32: lui {{.*}} i16v
-; MIPS32: addiu {{.*}} i16v
-; MIPS32: sh
-; MIPS32: sra {{.*}},0x1f
-; MIPS32: lui {{.*}} i64v
-; MIPS32: addiu {{.*}} i64v
-
-define internal void @from_int64() {
-entry:
- %__0 = bitcast [8 x i8]* @i64v to i64*
- %v0 = load i64, i64* %__0, align 1
- %v1 = trunc i64 %v0 to i8
- %__3 = bitcast [1 x i8]* @i8v to i8*
- store i8 %v1, i8* %__3, align 1
- %v2 = trunc i64 %v0 to i16
- %__5 = bitcast [2 x i8]* @i16v to i16*
- store i16 %v2, i16* %__5, align 1
- %v3 = trunc i64 %v0 to i32
- %__7 = bitcast [4 x i8]* @i32v to i32*
- store i32 %v3, i32* %__7, align 1
- ret void
-}
-; CHECK-LABEL: from_int64
-; CHECK: 0x{{.}} {{.*}} {{i64v|.bss}}
-; CHECK: 0x{{.}},{{.*}} {{i8v|.bss}}
-; CHECK: 0x{{.}},{{.*}} {{i16v|.bss}}
-; CHECK: 0x{{.}},{{.*}} {{i32v|.bss}}
-
-; ARM32-LABEL: from_int64
-; ARM32: movw {{.*}}i64v
-; ARM32: ldr r
-; ARM32: movw {{.*}}i8v
-; ARM32: strb
-; ARM32: movw {{.*}}i16v
-; ARM32: strh
-; ARM32: movw {{.*}}i32v
-; ARM32: str r
-
-; MIPS32-LABEL: from_int64
-; MIPS32: lui {{.*}} i64v
-; MIPS32: addiu {{.*}} i64v
-; MIPS32: lw
-; MIPS32: move
-; MIPS32: lui {{.*}} i8v
-; MIPS32: addiu {{.*}} i8v
-; MIPS32: sb
-; MIPS32: move
-; MIPS32: lui {{.*}} i16v
-; MIPS32: addiu {{.*}} i16v
-; MIPS32: sh
-; MIPS32: lui {{.*}} i32v
-; MIPS32: addiu {{.*}} i32v
-
-define internal void @from_uint8() {
-entry:
- %__0 = bitcast [1 x i8]* @u8v to i8*
- %v0 = load i8, i8* %__0, align 1
- %v1 = zext i8 %v0 to i16
- %__3 = bitcast [2 x i8]* @i16v to i16*
- store i16 %v1, i16* %__3, align 1
- %v2 = zext i8 %v0 to i32
- %__5 = bitcast [4 x i8]* @i32v to i32*
- store i32 %v2, i32* %__5, align 1
- %v3 = zext i8 %v0 to i64
- %__7 = bitcast [8 x i8]* @i64v to i64*
- store i64 %v3, i64* %__7, align 1
- ret void
-}
-; CHECK-LABEL: from_uint8
-; CHECK: 0x{{.*}} {{.*}} {{u8v|.bss}}
-; CHECK: movzx {{.*}},{{[a-d]l|BYTE PTR}}
-; CHECK: 0x{{.}},{{.*}} {{i16v|.bss}}
-; CHECK: movzx
-; CHECK: 0x{{.}},{{.*}} {{i32v|.bss}}
-; CHECK: movzx
-; CHECK: mov {{.*}},0x0
-; CHECK: 0x{{.}},{{.*}} {{i64v|.bss}}
-
-; ARM32-LABEL: from_uint8
-; ARM32: movw {{.*}}u8v
-; ARM32: ldrb
-; ARM32: uxtb
-; ARM32: movw {{.*}}i16v
-; ARM32: strh
-; ARM32: uxtb
-; ARM32: movw {{.*}}i32v
-; ARM32: str r
-; ARM32: uxtb
-; ARM32: mov {{.*}}, #0
-; ARM32: movw {{.*}}i64v
-; ARM32: str r
-
-; MIPS32-LABEL: from_uint8
-; MIPS32: lui {{.*}} u8v
-; MIPS32: addiu {{.*}} u8v
-; MIPS32: lb
-; MIPS32: move
-; MIPS32: andi {{.*}},0xff
-; MIPS32: lui {{.*}} i16v
-; MIPS32: addiu {{.*}} i16v
-; MIPS32: sh
-; MIPS32: move
-; MIPS32: andi {{.*}},0xff
-; MIPS32: lui {{.*}} i32v
-; MIPS32: addiu {{.*}} i32v
-; MIPS32: sw
-; MIPS32: andi {{.*}},0xff
-; MIPS32: li {{.*}},0
-; MIPS32: lui {{.*}} i64v
-; MIPS32: addiu {{.*}} i64v
-
-define internal void @from_uint16() {
-entry:
- %__0 = bitcast [2 x i8]* @u16v to i16*
- %v0 = load i16, i16* %__0, align 1
- %v1 = trunc i16 %v0 to i8
- %__3 = bitcast [1 x i8]* @i8v to i8*
- store i8 %v1, i8* %__3, align 1
- %v2 = zext i16 %v0 to i32
- %__5 = bitcast [4 x i8]* @i32v to i32*
- store i32 %v2, i32* %__5, align 1
- %v3 = zext i16 %v0 to i64
- %__7 = bitcast [8 x i8]* @i64v to i64*
- store i64 %v3, i64* %__7, align 1
- ret void
-}
-; CHECK-LABEL: from_uint16
-; CHECK: 0x{{.*}} {{.*}} {{u16v|.bss}}
-; CHECK: 0x{{.}},{{.*}} {{i8v|.bss}}
-; CHECK: movzx e{{.*}},{{.*x|[ds]i|bp|WORD PTR}}
-; CHECK: 0x{{.}},{{.*}} {{i32v|.bss}}
-; CHECK: movzx e{{.*}},{{.*x|[ds]i|bp|WORD PTR}}
-; CHECK: mov {{.*}},0x0
-; CHECK: 0x{{.}},{{.*}} {{i64v|.bss}}
-
-; ARM32-LABEL: from_uint16
-; ARM32: movw {{.*}}u16v
-; ARM32: ldrh
-; ARM32: movw {{.*}}i8v
-; ARM32: strb
-; ARM32: uxth
-; ARM32: movw {{.*}}i32v
-; ARM32: str r
-; ARM32: uxth
-; ARM32: mov {{.*}}, #0
-; ARM32: movw {{.*}}i64v
-; ARM32: str r
-
-; MIPS32-LABEL: from_uint16
-; MIPS32: lui {{.*}} u16v
-; MIPS32: addiu {{.*}} u16v
-; MIPS32: lh
-; MIPS32: move
-; MIPS32: lui {{.*}} i8v
-; MIPS32: addiu {{.*}} i8v
-; MIPS32: sb
-; MIPS32: move
-; MIPS32: andi {{.*}},0xffff
-; MIPS32: lui {{.*}} i32v
-; MIPS32: addiu {{.*}} i32v
-; MIPS32: sw
-; MIPS32: andi {{.*}},0xffff
-; MIPS32: li {{.*}},0
-; MIPS32: lui {{.*}} i64v
-; MIPS32: addiu {{.*}} i64v
-
-define internal void @from_uint32() {
-entry:
- %__0 = bitcast [4 x i8]* @u32v to i32*
- %v0 = load i32, i32* %__0, align 1
- %v1 = trunc i32 %v0 to i8
- %__3 = bitcast [1 x i8]* @i8v to i8*
- store i8 %v1, i8* %__3, align 1
- %v2 = trunc i32 %v0 to i16
- %__5 = bitcast [2 x i8]* @i16v to i16*
- store i16 %v2, i16* %__5, align 1
- %v3 = zext i32 %v0 to i64
- %__7 = bitcast [8 x i8]* @i64v to i64*
- store i64 %v3, i64* %__7, align 1
- ret void
-}
-; CHECK-LABEL: from_uint32
-; CHECK: 0x{{.*}} {{.*}} {{u32v|.bss}}
-; CHECK: 0x{{.}},{{.*}} {{i8v|.bss}}
-; CHECK: 0x{{.}},{{.*}} {{i16v|.bss}}
-; CHECK: mov {{.*}},0x0
-; CHECK: 0x{{.}},{{.*}} {{i64v|.bss}}
-
-; ARM32-LABEL: from_uint32
-; ARM32: movw {{.*}}u32v
-; ARM32: ldr r
-; ARM32: movw {{.*}}i8v
-; ARM32: strb
-; ARM32: movw {{.*}}i16v
-; ARM32: strh
-; ARM32: mov {{.*}}, #0
-; ARM32: movw {{.*}}i64v
-; ARM32: str r
-
-; MIPS32-LABEL: from_uint32
-; MIPS32: lui {{.*}} u32v
-; MIPS32: addiu {{.*}} u32v
-; MIPS32: lw
-; MIPS32: move
-; MIPS32: lui {{.*}} i8v
-; MIPS32: addiu {{.*}} i8v
-; MIPS32: sb
-; MIPS32: move
-; MIPS32: lui {{.*}} i16v
-; MIPS32: addiu {{.*}} i16v
-; MIPS32: sh
-; MIPS32: li {{.*}},0
-; MIPS32: lui {{.*}} i64v
-; MIPS32: addiu {{.*}} i64v
-
-define internal void @from_uint64() {
-entry:
- %__0 = bitcast [8 x i8]* @u64v to i64*
- %v0 = load i64, i64* %__0, align 1
- %v1 = trunc i64 %v0 to i8
- %__3 = bitcast [1 x i8]* @i8v to i8*
- store i8 %v1, i8* %__3, align 1
- %v2 = trunc i64 %v0 to i16
- %__5 = bitcast [2 x i8]* @i16v to i16*
- store i16 %v2, i16* %__5, align 1
- %v3 = trunc i64 %v0 to i32
- %__7 = bitcast [4 x i8]* @i32v to i32*
- store i32 %v3, i32* %__7, align 1
- ret void
-}
-; CHECK-LABEL: from_uint64
-; CHECK: 0x{{.*}} {{.*}} {{u64v|.bss}}
-; CHECK: 0x{{.}},{{.*}} {{i8v|.bss}}
-; CHECK: 0x{{.}},{{.*}} {{i16v|.bss}}
-; CHECK: 0x{{.}},{{.*}} {{i32v|.bss}}
-
-; ARM32-LABEL: from_uint64
-; ARM32: movw {{.*}}u64v
-; ARM32: ldr r
-; ARM32: movw {{.*}}i8v
-; ARM32: strb
-; ARM32: movw {{.*}}i16v
-; ARM32: strh
-; ARM32: movw {{.*}}i32v
-; ARM32: str r
-
-; MIPS32-LABEL: from_uint64
-; MIPS32: lui {{.*}} u64v
-; MIPS32: addiu {{.*}} u64v
-; MIPS32: lw
-; MIPS32: move
-; MIPS32: lui {{.*}} i8v
-; MIPS32: addiu {{.*}} i8v
-; MIPS32: sb
-; MIPS32: move
-; MIPS32: lui {{.*}} i16v
-; MIPS32: addiu {{.*}} i16v
-; MIPS32: sh
-; MIPS32: lui {{.*}} i32v
-; MIPS32: addiu {{.*}} i32v
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/div_legalization.ll b/third_party/subzero/tests_lit/llvm2ice_tests/div_legalization.ll
deleted file mode 100644
index 4624dcf..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/div_legalization.ll
+++ /dev/null
@@ -1,63 +0,0 @@
-; This is a regression test that idiv and div operands are legalized
-; (they cannot be constants and can only be reg/mem for x86).
-
-; RUN: %p2i --filetype=obj --disassemble -i %s --args -O2 | FileCheck %s
-; RUN: %p2i --filetype=obj --disassemble -i %s --args -Om1 | FileCheck %s
-
-define internal i32 @Sdiv_const8_b(i32 %a32) {
-; CHECK-LABEL: Sdiv_const8_b
-entry:
- %a = trunc i32 %a32 to i8
- %div = sdiv i8 %a, 12
-; CHECK: mov {{.*}},0xc
-; CHECK-NOT: idiv 0xc
- %div_ext = sext i8 %div to i32
- ret i32 %div_ext
-}
-
-define internal i32 @Sdiv_const16_b(i32 %a32) {
-; CHECK-LABEL: Sdiv_const16_b
-entry:
- %a = trunc i32 %a32 to i16
- %div = sdiv i16 %a, 1234
-; CHECK: mov {{.*}},0x4d2
-; CHECK-NOT: idiv 0x4d2
- %div_ext = sext i16 %div to i32
- ret i32 %div_ext
-}
-
-define internal i32 @Sdiv_const32_b(i32 %a) {
-; CHECK-LABEL: Sdiv_const32_b
-entry:
- %div = sdiv i32 %a, 1234
-; CHECK: mov {{.*}},0x4d2
-; CHECK-NOT: idiv 0x4d2
- ret i32 %div
-}
-
-define internal i32 @Srem_const_b(i32 %a) {
-; CHECK-LABEL: Srem_const_b
-entry:
- %rem = srem i32 %a, 2345
-; CHECK: mov {{.*}},0x929
-; CHECK-NOT: idiv 0x929
- ret i32 %rem
-}
-
-define internal i32 @Udiv_const_b(i32 %a) {
-; CHECK-LABEL: Udiv_const_b
-entry:
- %div = udiv i32 %a, 3456
-; CHECK: mov {{.*}},0xd80
-; CHECK-NOT: div 0xd80
- ret i32 %div
-}
-
-define internal i32 @Urem_const_b(i32 %a) {
-; CHECK-LABEL: Urem_const_b
-entry:
- %rem = urem i32 %a, 4567
-; CHECK: mov {{.*}},0x11d7
-; CHECK-NOT: div 0x11d7
- ret i32 %rem
-}
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/ebp_args.ll b/third_party/subzero/tests_lit/llvm2ice_tests/ebp_args.ll
deleted file mode 100644
index e87e9d3..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/ebp_args.ll
+++ /dev/null
@@ -1,44 +0,0 @@
-; This test originally exhibited a bug in ebp-based stack slots. The
-; problem was that during a function call push sequence, the esp
-; adjustment was incorrectly added to the stack/frame offset for
-; ebp-based frames.
-
-; RUN: %p2i --filetype=obj --disassemble -i %s --args -Om1 \
-; RUN: -allow-externally-defined-symbols | FileCheck %s
-
-declare i32 @memcpy_helper2(i32 %buf, i32 %buf2, i32 %n)
-
-define internal i32 @memcpy_helper(i32 %buf, i32 %n) {
-entry:
- br label %eblock ; Disable alloca optimization
-eblock:
- %buf2 = alloca i8, i32 128, align 4
- %n.arg_trunc = trunc i32 %n to i8
- %arg.ext = zext i8 %n.arg_trunc to i32
- %buf2.asint = ptrtoint i8* %buf2 to i32
- %call = call i32 @memcpy_helper2(i32 %buf, i32 %buf2.asint, i32 %arg.ext)
- ret i32 %call
-}
-
-; This check sequence is highly specific to the current Om1 lowering
-; and stack slot assignment code, and may need to be relaxed if the
-; lowering code changes.
-
-; CHECK-LABEL: memcpy_helper
-; CHECK: push ebp
-; CHECK: mov ebp,esp
-; CHECK: sub esp,0x28
-; CHECK: sub esp,0x80
-; CHECK: lea eax,[esp+0x10]
-; CHECK: mov DWORD PTR [ebp-0x4],eax
-; CHECK: mov eax,DWORD PTR [ebp+0xc]
-; CHECK: mov BYTE PTR [ebp-0x8],al
-; CHECK: movzx eax,BYTE PTR [ebp-0x8]
-; CHECK: mov DWORD PTR [ebp-0xc],eax
-; CHECK: mov eax,DWORD PTR [ebp+0x8]
-; CHECK: mov DWORD PTR [esp],eax
-; CHECK: mov eax,DWORD PTR [ebp-0x4]
-; CHECK: mov DWORD PTR [esp+0x4],eax
-; CHECK: mov eax,DWORD PTR [ebp-0xc]
-; CHECK: mov DWORD PTR [esp+0x8],eax
-; CHECK: call {{.*}} R_{{.*}} memcpy_helper2
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/elf_container.ll b/third_party/subzero/tests_lit/llvm2ice_tests/elf_container.ll
deleted file mode 100644
index bee9002..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/elf_container.ll
+++ /dev/null
@@ -1,649 +0,0 @@
-; Tests that we generate an ELF container with fields that make sense,
-; cross-validating against llvm-mc.
-
-; For the integrated ELF writer, we can't pipe the output because we need
-; to seek backward and patch up the file headers. So, use a temporary file.
-; RUN: %p2i -i %s --filetype=obj --output %t --args -O2 --verbose none \
-; RUN: -allow-externally-defined-symbols \
-; RUN: && llvm-readobj -file-headers -sections -section-data \
-; RUN: -relocations -symbols %t | FileCheck %s
-
-; RUN: %if --need=allow_dump --command %p2i -i %s --args -O2 --verbose none \
-; RUN: -allow-externally-defined-symbols \
-; RUN: | %if --need=allow_dump --command llvm-mc -triple=i686-nacl \
-; RUN: -filetype=obj -o - \
-; RUN: | %if --need=allow_dump --command llvm-readobj -file-headers \
-; RUN: -sections -section-data -relocations -symbols - \
-; RUN: | %if --need=allow_dump --command FileCheck %s
-
-; Add a run that shows relocations in code inline.
-; RUN: %p2i -i %s --filetype=obj --output %t --disassemble --args -O2 \
-; RUN: -allow-externally-defined-symbols \
-; RUN: | FileCheck --check-prefix=TEXT-RELOCS %s
-
-; Use intrinsics to test external calls.
-declare void @llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1)
-declare void @llvm.memset.p0i8.i32(i8*, i8, i32, i32, i1)
-
-; Try other external functions (for cross tests).
-; Not testing external global variables since the NaCl bitcode writer
-; refuses to freeze such IR.
-declare void @external_foo(i32)
-
-; Test some global data relocs (data, rodata, bss).
-@bytes = internal global [7 x i8] c"ab\03\FF\F6fg", align 1
-@bytes_const = internal constant [7 x i8] c"ab\03\FF\F6fg", align 1
-
-@ptr = internal global i32 ptrtoint ([7 x i8]* @bytes to i32), align 16
-@ptr_const = internal constant i32 ptrtoint ([7 x i8]* @bytes to i32), align 16
-
-@ptr_to_func = internal global i32 ptrtoint (double ()* @returnDoubleConst to i32), align 4
-@ptr_to_func_const = internal constant i32 ptrtoint (double ()* @returnDoubleConst to i32), align 4
-
-@addend_ptr = internal global i32 add (i32 ptrtoint (i32* @ptr to i32), i32 128), align 4
-@addend_ptr_const = internal constant i32 add (i32 ptrtoint (i32* @ptr to i32), i32 64), align 4
-
-@short_zero = internal global [2 x i8] zeroinitializer, align 2
-@double_zero = internal global [8 x i8] zeroinitializer, align 32
-@double_zero2 = internal global [8 x i8] zeroinitializer, align 8
-@short_zero_const = internal constant [2 x i8] zeroinitializer, align 2
-@double_zero_const = internal constant [8 x i8] zeroinitializer, align 32
-@double_zero_const2 = internal constant [8 x i8] zeroinitializer, align 8
-
-; Use float/double constants to test constant pools.
-define internal float @returnFloatConst() {
-entry:
- %f = fadd float -0.0, 0x3FF3AE1400000000
- ret float %f
-}
-; TEXT-RELOCS-LABEL: returnFloatConst
-; TEXT-RELOCS: movss {{.*}} R_386_32 {{.*}}80000000
-; TEXT-RELOCS: addss {{.*}} R_386_32 {{.*}}3f9d70a0
-
-define internal double @returnDoubleConst() {
-entry:
- %d = fadd double 0x7FFFFFFFFFFFFFFFF, 0xFFF7FFFFFFFFFFFF
- %d2 = fadd double %d, 0xFFF8000000000003
- ret double %d2
-}
-; TEXT-RELOCS-LABEL: returnDoubleConst
-; TEXT-RELOCS: movsd {{.*}} R_386_32 {{.*}}ffffffffffffffff
-; TEXT-RELOCS: addsd {{.*}} R_386_32 {{.*}}fff7ffffffffffff
-; TEXT-RELOCS: addsd {{.*}} R_386_32 {{.*}}fff8000000000003
-
-; Test intrinsics that call out to external functions.
-define internal void @test_memcpy(i32 %iptr_dst, i32 %len) {
-entry:
- %dst = inttoptr i32 %iptr_dst to i8*
- %src = bitcast [7 x i8]* @bytes to i8*
- call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dst, i8* %src,
- i32 %len, i32 1, i1 false)
- ret void
-}
-; TEXT-RELOCS-LABEL: test_memcpy
-; TEXT-RELOCS: mov {{.*}} R_386_32 {{bytes|.data}}
-
-define internal void @test_memset(i32 %iptr_dst, i32 %wide_val, i32 %len) {
-entry:
- %val = trunc i32 %wide_val to i8
- %dst = inttoptr i32 %iptr_dst to i8*
- call void @llvm.memset.p0i8.i32(i8* %dst, i8 %val,
- i32 %len, i32 1, i1 false)
- ret void
-}
-; TEXT-RELOCS-LABEL: test_memset
-
-; Test calling internal functions (may be able to do the fixup,
-; without emitting a relocation).
-define internal float @test_call_internal() {
- %f = call float @returnFloatConst()
- ret float %f
-}
-
-; Test calling an external function.
-define internal void @test_call_external() {
- call void @external_foo(i32 42)
- ret void
-}
-
-; Test copying a function pointer, or a global data pointer.
-define internal i32 @test_ret_fp() {
- %r = ptrtoint float ()* @returnFloatConst to i32
- ret i32 %r
-}
-; TEXT-RELOCS-LABEL: test_ret_fp
-; TEXT-RELOCS-NEXT: mov {{.*}} R_386_32 {{returnFloatConst|.text}}
-
-define internal i32 @test_ret_global_pointer() {
- %r = ptrtoint [7 x i8]* @bytes to i32
- ret i32 %r
-}
-; TEXT-RELOCS-LABEL: test_ret_global_pointer
-; TEXT-RELOCS-NEXT: mov {{.*}} R_386_32 {{bytes|.data}}
-
-; Test defining a non-internal function.
-define void @_start(i32) {
- %f = call float @returnFloatConst()
- %d = call double @returnDoubleConst()
- call void @test_memcpy(i32 0, i32 99)
- call void @test_memset(i32 0, i32 0, i32 99)
- %f2 = call float @test_call_internal()
- %p1 = call i32 @test_ret_fp()
- %p2 = call i32 @test_ret_global_pointer()
- ret void
-}
-
-; CHECK: ElfHeader {
-; CHECK: Ident {
-; CHECK: Magic: (7F 45 4C 46)
-; CHECK: Class: 32-bit
-; CHECK: DataEncoding: LittleEndian
-; CHECK: OS/ABI: SystemV (0x0)
-; CHECK: ABIVersion: 0
-; CHECK: Unused: (00 00 00 00 00 00 00)
-; CHECK: }
-; CHECK: Type: Relocatable (0x1)
-; CHECK: Machine: EM_386 (0x3)
-; CHECK: Version: 1
-; CHECK: Entry: 0x0
-; CHECK: ProgramHeaderOffset: 0x0
-; CHECK: SectionHeaderOffset: 0x{{[1-9A-F][0-9A-F]*}}
-; CHECK: Flags [ (0x0)
-; CHECK: ]
-; CHECK: HeaderSize: 52
-; CHECK: ProgramHeaderEntrySize: 0
-; CHECK: ProgramHeaderCount: 0
-; CHECK: SectionHeaderEntrySize: 40
-; CHECK: SectionHeaderCount: {{[1-9][0-9]*}}
-; CHECK: StringTableSectionIndex: {{[1-9][0-9]*}}
-; CHECK: }
-
-
-; CHECK: Sections [
-; CHECK: Section {
-; CHECK: Index: 0
-; CHECK: Name: (0)
-; CHECK: Type: SHT_NULL
-; CHECK: Flags [ (0x0)
-; CHECK: ]
-; CHECK: Address: 0x0
-; CHECK: Offset: 0x0
-; CHECK: Size: 0
-; CHECK: Link: 0
-; CHECK: Info: 0
-; CHECK: AddressAlignment: 0
-; CHECK: EntrySize: 0
-; CHECK: SectionData (
-; CHECK: )
-; CHECK: }
-; CHECK: Section {
-; CHECK: Index: {{[1-9][0-9]*}}
-; CHECK: Name: .text
-; CHECK: Type: SHT_PROGBITS
-; CHECK: Flags [ (0x6)
-; CHECK: SHF_ALLOC
-; CHECK: SHF_EXECINSTR
-; CHECK: ]
-; CHECK: Address: 0x0
-; CHECK: Offset: 0x{{[1-9A-F][0-9A-F]*}}
-; CHECK: Size: {{[1-9][0-9]*}}
-; CHECK: Link: 0
-; CHECK: Info: 0
-; CHECK: AddressAlignment: 32
-; CHECK: EntrySize: 0
-; CHECK: SectionData (
-; There's probably halt padding (0xF4) in there somewhere.
-; CHECK: {{.*}}F4
-; CHECK: )
-; CHECK: }
-; CHECK: Section {
-; CHECK: Index: {{[1-9][0-9]*}}
-; CHECK: Name: .rel.text
-; CHECK: Type: SHT_REL
-; CHECK: Flags [ (0x0)
-; CHECK: ]
-; CHECK: Address: 0x0
-; CHECK: Offset: 0x{{[1-9A-F][0-9A-F]*}}
-; CHECK: Size: {{[1-9][0-9]*}}
-; CHECK: Link: [[SYMTAB_INDEX:[1-9][0-9]*]]
-; CHECK: Info: {{[1-9][0-9]*}}
-; CHECK: AddressAlignment: 4
-; CHECK: EntrySize: 8
-; CHECK: SectionData (
-; CHECK: )
-; CHECK: }
-; CHECK: Section {
-; CHECK: Index: [[DATA_INDEX:[1-9][0-9]*]]
-; CHECK: Name: .data
-; CHECK: Type: SHT_PROGBITS
-; CHECK: Flags [ (0x3)
-; CHECK: SHF_ALLOC
-; CHECK: SHF_WRITE
-; CHECK: ]
-; CHECK: Address: 0x0
-; CHECK: Offset: 0x{{[1-9A-F][0-9A-F]*}}
-; CHECK: Size: 28
-; CHECK: Link: 0
-; CHECK: Info: 0
-; CHECK: AddressAlignment: 16
-; CHECK: EntrySize: 0
-; CHECK: SectionData (
-; CHECK: 0000: 616203FF F66667{{.*}} |ab...fg
-; CHECK: )
-; CHECK: }
-; CHECK: Section {
-; CHECK: Index: {{[1-9][0-9]*}}
-; CHECK: Name: .rel.data
-; CHECK: Type: SHT_REL
-; CHECK: Flags [ (0x0)
-; CHECK: ]
-; CHECK: Address: 0x0
-; CHECK: Offset: 0x{{[1-9A-F][0-9A-F]*}}
-; CHECK: Size: 24
-; CHECK: Link: [[SYMTAB_INDEX]]
-; CHECK: Info: [[DATA_INDEX]]
-; CHECK: AddressAlignment: 4
-; CHECK: EntrySize: 8
-; CHECK: SectionData (
-; CHECK: )
-; CHECK: }
-; CHECK: Section {
-; CHECK: Index: {{[1-9][0-9]*}}
-; CHECK: Name: .bss
-; CHECK: Type: SHT_NOBITS
-; CHECK: Flags [ (0x3)
-; CHECK: SHF_ALLOC
-; CHECK: SHF_WRITE
-; CHECK: ]
-; CHECK: Address: 0x0
-; CHECK: Offset: 0x{{[1-9A-F][0-9A-F]*}}
-; CHECK: Size: 48
-; CHECK: Link: 0
-; CHECK: Info: 0
-; CHECK: AddressAlignment: 32
-; CHECK: EntrySize: 0
-; CHECK: }
-; CHECK: Section {
-; CHECK: Index: {{[1-9][0-9]*}}
-; CHECK: Name: .rodata
-; CHECK: Type: SHT_PROGBITS
-; CHECK: Flags [ (0x2)
-; CHECK: SHF_ALLOC
-; CHECK: ]
-; CHECK: Address: 0x0
-; CHECK: Offset: 0x{{[1-9A-F][0-9A-F]*}}
-; CHECK: Size: 48
-; CHECK: Link: 0
-; CHECK: Info: 0
-; CHECK: AddressAlignment: 32
-; CHECK: EntrySize: 0
-; CHECK: SectionData (
-; CHECK: 0000: 616203FF F66667{{.*}} |ab...fg
-; CHECK: )
-; CHECK: }
-; CHECK: Section {
-; CHECK: Index: {{[1-9][0-9]*}}
-; CHECK: Name: .rel.rodata
-; CHECK: Type: SHT_REL
-; CHECK: Flags [ (0x0)
-; CHECK: ]
-; CHECK: Address: 0x0
-; CHECK: Offset: 0x{{[1-9A-F][0-9A-F]*}}
-; CHECK: Size: {{[1-9][0-9]*}}
-; CHECK: Link: [[SYMTAB_INDEX]]
-; CHECK: Info: {{[1-9][0-9]*}}
-; CHECK: AddressAlignment: 4
-; CHECK: EntrySize: 8
-; CHECK: SectionData (
-; CHECK: )
-; CHECK: }
-; CHECK: Section {
-; CHECK: Index: {{[1-9][0-9]*}}
-; CHECK: Name: .rodata.cst4
-; CHECK: Type: SHT_PROGBITS
-; CHECK: Flags [ (0x12)
-; CHECK: SHF_ALLOC
-; CHECK: SHF_MERGE
-; CHECK: ]
-; CHECK: Address: 0x0
-; CHECK: Offset: 0x{{[1-9A-F][0-9A-F]*}}
-; CHECK: Size: 8
-; CHECK: Link: 0
-; CHECK: Info: 0
-; CHECK: AddressAlignment: 4
-; CHECK: EntrySize: 4
-; CHECK: SectionData (
-; CHECK: 0000: A0709D3F 00000080
-; CHECK: )
-; CHECK: }
-; CHECK: Section {
-; CHECK: Index: {{[1-9][0-9]*}}
-; CHECK: Name: .rodata.cst8
-; CHECK: Type: SHT_PROGBITS
-; CHECK: Flags [ (0x12)
-; CHECK: SHF_ALLOC
-; CHECK: SHF_MERGE
-; CHECK: ]
-; CHECK: Address: 0x0
-; CHECK: Offset: 0x{{[1-9A-F][0-9A-F]*}}
-; CHECK: Size: 24
-; CHECK: Link: 0
-; CHECK: Info: 0
-; CHECK: AddressAlignment: 8
-; CHECK: EntrySize: 8
-; CHECK: SectionData (
-; CHECK: 0000: FFFFFFFF FFFFF7FF 03000000 0000F8FF
-; CHECK: 0010: FFFFFFFF FFFFFFFF
-; CHECK: )
-; CHECK: }
-; CHECK: Section {
-; CHECK: Index: {{[1-9][0-9]*}}
-; CHECK: Name: .shstrtab
-; CHECK: Type: SHT_STRTAB
-; CHECK: Flags [ (0x0)
-; CHECK: ]
-; CHECK: Address: 0x0
-; CHECK: Offset: 0x{{[1-9A-F][0-9A-F]*}}
-; CHECK: Size: {{[1-9][0-9]*}}
-; CHECK: Link: 0
-; CHECK: Info: 0
-; CHECK: AddressAlignment: 1
-; CHECK: EntrySize: 0
-; CHECK: SectionData (
-; CHECK: {{.*}}.text{{.*}}
-; CHECK: )
-; CHECK: }
-; CHECK: Section {
-; CHECK: Index: [[SYMTAB_INDEX]]
-; CHECK-NEXT: Name: .symtab
-; CHECK: Type: SHT_SYMTAB
-; CHECK: Flags [ (0x0)
-; CHECK: ]
-; CHECK: Address: 0x0
-; CHECK: Offset: 0x{{[1-9A-F][0-9A-F]*}}
-; CHECK: Size: {{[1-9][0-9]*}}
-; CHECK: Link: [[STRTAB_INDEX:[1-9][0-9]*]]
-; CHECK: Info: [[GLOBAL_START_INDEX:[1-9][0-9]*]]
-; CHECK: AddressAlignment: 4
-; CHECK: EntrySize: 16
-; CHECK: }
-; CHECK: Section {
-; CHECK: Index: [[STRTAB_INDEX]]
-; CHECK-NEXT: Name: .strtab
-; CHECK: Type: SHT_STRTAB
-; CHECK: Flags [ (0x0)
-; CHECK: ]
-; CHECK: Address: 0x0
-; CHECK: Offset: 0x{{[1-9A-F][0-9A-F]*}}
-; CHECK: Size: {{[1-9][0-9]*}}
-; CHECK: Link: 0
-; CHECK: Info: 0
-; CHECK: AddressAlignment: 1
-; CHECK: EntrySize: 0
-; CHECK: }
-
-
-; CHECK: Relocations [
-; CHECK: Section ({{[0-9]+}}) .rel.text {
-; CHECK: 0x7 R_386_32 {{.*}}80000000 0x0
-; CHECK: 0xF R_386_32 {{.*}}3f9d70a0 0x0
-; CHECK: 0x27 R_386_32 {{.*}}ffffffffffffffff 0x0
-; CHECK: 0x2F R_386_32 {{.*}}fff7ffffffffffff 0x0
-; CHECK: 0x37 R_386_32 {{.*}}fff8000000000003 0x0
-; CHECK: 0x{{.*}} R_386_PC32 memcpy
-; CHECK: 0x{{.*}} R_386_PC32 memset
-; CHECK: 0x{{.*}} R_386_PC32 external_foo
-; CHECK: }
-; CHECK: Section ({{[0-9]+}}) .rel.data {
-; The set of relocations between llvm-mc and the integrated elf-writer
-; are different. For local symbols, llvm-mc uses the section + offset within
-; the section, while the integrated elf-writer refers the symbol itself.
-; CHECK: 0x10 R_386_32 {{.*}} 0x0
-; CHECK: 0x14 R_386_32 {{.*}} 0x0
-; CHECK: 0x18 R_386_32 {{.*}} 0x0
-; CHECK: }
-; CHECK: Section ({{[0-9]+}}) .rel.rodata {
-; CHECK: 0x10 R_386_32 {{.*}} 0x0
-; CHECK: 0x14 R_386_32 {{.*}} 0x0
-; CHECK: 0x18 R_386_32 {{.*}} 0x0
-; CHECK: }
-; CHECK: ]
-
-
-; CHECK: Symbols [
-; CHECK-NEXT: Symbol {
-; CHECK-NEXT: Name: (0)
-; CHECK-NEXT: Value: 0x0
-; CHECK-NEXT: Size: 0
-; CHECK-NEXT: Binding: Local
-; CHECK-NEXT: Type: None
-; CHECK-NEXT: Other: 0
-; CHECK-NEXT: Section: Undefined (0x0)
-; CHECK-NEXT: }
-; CHECK: Symbol {
-; CHECK: Name: {{.*}}fff8000000000003
-; CHECK-NEXT: Value: 0x8
-; CHECK-NEXT: Size: 0
-; CHECK-NEXT: Binding: Local (0x0)
-; CHECK-NEXT: Type: None (0x0)
-; CHECK-NEXT: Other: 0
-; CHECK-NEXT: Section: .rodata.cst8
-; CHECK-NEXT: }
-; CHECK: Symbol {
-; CHECK: Name: {{.*}}ffffffffffffffff
-; CHECK-NEXT: Value: 0x10
-; CHECK-NEXT: Size: 0
-; CHECK-NEXT: Binding: Local (0x0)
-; CHECK-NEXT: Type: None (0x0)
-; CHECK-NEXT: Other: 0
-; CHECK-NEXT: Section: .rodata.cst8
-; CHECK-NEXT: }
-; CHECK: Symbol {
-; CHECK: Name: {{.*}}3f9d70a0
-; CHECK-NEXT: Value: 0x0
-; CHECK-NEXT: Size: 0
-; CHECK-NEXT: Binding: Local (0x0)
-; CHECK-NEXT: Type: None (0x0)
-; CHECK-NEXT: Other: 0
-; CHECK-NEXT: Section: .rodata.cst4
-; CHECK-NEXT: }
-; CHECK: Symbol {
-; CHECK: Name: {{.*}}80000000
-; CHECK-NEXT: Value: 0x4
-; CHECK-NEXT: Size: 0
-; CHECK-NEXT: Binding: Local (0x0)
-; CHECK-NEXT: Type: None (0x0)
-; CHECK-NEXT: Other: 0
-; CHECK-NEXT: Section: .rodata.cst4
-; CHECK-NEXT: }
-; CHECK: Symbol {
-; CHECK: Name: addend_ptr
-; CHECK-NEXT: Value: 0x18
-; CHECK-NEXT: Size: 4
-; CHECK-NEXT: Binding: Local (0x0)
-; CHECK-NEXT: Type: Object (0x1)
-; CHECK-NEXT: Other: 0
-; CHECK-NEXT: Section: .data
-; CHECK-NEXT: }
-; CHECK: Symbol {
-; CHECK: Name: addend_ptr_const
-; CHECK-NEXT: Value: 0x18
-; CHECK-NEXT: Size: 4
-; CHECK-NEXT: Binding: Local (0x0)
-; CHECK-NEXT: Type: Object (0x1)
-; CHECK-NEXT: Other: 0
-; CHECK-NEXT: Section: .rodata
-; CHECK-NEXT: }
-; CHECK: Symbol {
-; CHECK: Name: bytes
-; CHECK-NEXT: Value: 0x0
-; CHECK-NEXT: Size: 7
-; CHECK-NEXT: Binding: Local (0x0)
-; CHECK-NEXT: Type: Object (0x1)
-; CHECK-NEXT: Other: 0
-; CHECK-NEXT: Section: .data
-; CHECK-NEXT: }
-; CHECK: Symbol {
-; CHECK: Name: bytes_const
-; CHECK-NEXT: Value: 0x0
-; CHECK-NEXT: Size: 7
-; CHECK-NEXT: Binding: Local (0x0)
-; CHECK-NEXT: Type: Object (0x1)
-; CHECK-NEXT: Other: 0
-; CHECK-NEXT: Section: .rodata
-; CHECK-NEXT: }
-; CHECK: Symbol {
-; CHECK: Name: double_zero
-; CHECK-NEXT: Value: 0x20
-; CHECK-NEXT: Size: 8
-; CHECK-NEXT: Binding: Local
-; CHECK-NEXT: Type: Object
-; CHECK-NEXT: Other: 0
-; CHECK-NEXT: Section: .bss
-; CHECK-NEXT: }
-; CHECK: Symbol {
-; CHECK: Name: double_zero2
-; CHECK-NEXT: Value: 0x28
-; CHECK-NEXT: Size: 8
-; CHECK-NEXT: Binding: Local
-; CHECK-NEXT: Type: Object
-; CHECK-NEXT: Other: 0
-; CHECK-NEXT: Section: .bss
-; CHECK-NEXT: }
-; CHECK: Symbol {
-; CHECK: Name: double_zero_const
-; CHECK-NEXT: Value: 0x20
-; CHECK-NEXT: Size: 8
-; CHECK-NEXT: Binding: Local
-; CHECK-NEXT: Type: Object
-; CHECK-NEXT: Other: 0
-; CHECK-NEXT: Section: .rodata
-; CHECK-NEXT: }
-; CHECK: Symbol {
-; CHECK: Name: double_zero_const2
-; CHECK-NEXT: Value: 0x28
-; CHECK-NEXT: Size: 8
-; CHECK-NEXT: Binding: Local
-; CHECK-NEXT: Type: Object
-; CHECK-NEXT: Other: 0
-; CHECK-NEXT: Section: .rodata
-; CHECK-NEXT: }
-; CHECK: Symbol {
-; CHECK: Name: ptr
-; CHECK-NEXT: Value: 0x10
-; CHECK-NEXT: Size: 4
-; CHECK-NEXT: Binding: Local
-; CHECK-NEXT: Type: Object
-; CHECK-NEXT: Other: 0
-; CHECK-NEXT: Section: .data
-; CHECK-NEXT: }
-; CHECK: Symbol {
-; CHECK: Name: ptr_const
-; CHECK-NEXT: Value: 0x10
-; CHECK-NEXT: Size: 4
-; CHECK-NEXT: Binding: Local
-; CHECK-NEXT: Type: Object
-; CHECK-NEXT: Other: 0
-; CHECK-NEXT: Section: .rodata
-; CHECK-NEXT: }
-; CHECK: Symbol {
-; CHECK: Name: ptr_to_func
-; CHECK-NEXT: Value: 0x14
-; CHECK-NEXT: Size: 4
-; CHECK-NEXT: Binding: Local
-; CHECK-NEXT: Type: Object
-; CHECK-NEXT: Other: 0
-; CHECK-NEXT: Section: .data
-; CHECK-NEXT: }
-; CHECK: Symbol {
-; CHECK: Name: ptr_to_func_const
-; CHECK-NEXT: Value: 0x14
-; CHECK-NEXT: Size: 4
-; CHECK-NEXT: Binding: Local
-; CHECK-NEXT: Type: Object
-; CHECK-NEXT: Other: 0
-; CHECK-NEXT: Section: .rodata
-; CHECK-NEXT: }
-; CHECK: Symbol {
-; CHECK: Name: returnDoubleConst
-; CHECK-NEXT: Value: 0x{{[1-9A-F][0-9A-F]*}}
-; CHECK-NEXT: Size: 0
-; CHECK-NEXT: Binding: Local
-; CHECK-NEXT: Type: None
-; CHECK-NEXT: Other: 0
-; CHECK-NEXT: Section: .text
-; CHECK-NEXT: }
-; CHECK: Symbol {
-; CHECK: Name: returnFloatConst
-; This happens to be the first function, so its offset is 0 within the text.
-; CHECK-NEXT: Value: 0x0
-; CHECK-NEXT: Size: 0
-; CHECK-NEXT: Binding: Local
-; CHECK-NEXT: Type: None
-; CHECK-NEXT: Other: 0
-; CHECK-NEXT: Section: .text
-; CHECK-NEXT: }
-; CHECK: Symbol {
-; CHECK: Name: short_zero
-; CHECK-NEXT: Value: 0x0
-; CHECK-NEXT: Size: 2
-; CHECK-NEXT: Binding: Local
-; CHECK-NEXT: Type: Object
-; CHECK-NEXT: Other: 0
-; CHECK-NEXT: Section: .bss
-; CHECK-NEXT: }
-; CHECK: Symbol {
-; CHECK: Name: short_zero_const
-; CHECK-NEXT: Value: 0x1C
-; CHECK-NEXT: Size: 2
-; CHECK-NEXT: Binding: Local
-; CHECK-NEXT: Type: Object
-; CHECK-NEXT: Other: 0
-; CHECK-NEXT: Section: .rodata
-; CHECK-NEXT: }
-; CHECK: Symbol {
-; CHECK: Name: test_memcpy
-; CHECK-NEXT: Value: 0x{{[1-9A-F][0-9A-F]*}}
-; CHECK-NEXT: Size: 0
-; CHECK-NEXT: Binding: Local
-; CHECK-NEXT: Type: None
-; CHECK-NEXT: Other: 0
-; CHECK-NEXT: Section: .text
-; CHECK-NEXT: }
-; CHECK: Symbol {
-; CHECK: Name: _start
-; CHECK-NEXT: Value: 0x{{[1-9A-F][0-9A-F]*}}
-; CHECK-NEXT: Size: 0
-; CHECK-NEXT: Binding: Global
-; CHECK-NEXT: Type: Function
-; CHECK-NEXT: Other: 0
-; CHECK-NEXT: Section: .text
-; CHECK-NEXT: }
-; CHECK: Symbol {
-; CHECK: Name: external_foo
-; CHECK-NEXT: Value: 0x0
-; CHECK-NEXT: Size: 0
-; CHECK-NEXT: Binding: Global
-; CHECK-NEXT: Type: None
-; CHECK-NEXT: Other: 0
-; CHECK-NEXT: Section: Undefined
-; CHECK-NEXT: }
-; CHECK: Symbol {
-; CHECK: Name: memcpy
-; CHECK-NEXT: Value: 0x0
-; CHECK-NEXT: Size: 0
-; CHECK-NEXT: Binding: Global
-; CHECK-NEXT: Type: None
-; CHECK-NEXT: Other: 0
-; CHECK-NEXT: Section: Undefined
-; CHECK-NEXT: }
-; CHECK: Symbol {
-; CHECK: Name: memset
-; CHECK-NEXT: Value: 0x0
-; CHECK-NEXT: Size: 0
-; CHECK-NEXT: Binding: Global
-; CHECK-NEXT: Type: None
-; CHECK-NEXT: Other: 0
-; CHECK-NEXT: Section: Undefined
-; CHECK-NEXT: }
-; CHECK: ]
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/elf_function_sections.ll b/third_party/subzero/tests_lit/llvm2ice_tests/elf_function_sections.ll
deleted file mode 100644
index 804ba1d..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/elf_function_sections.ll
+++ /dev/null
@@ -1,95 +0,0 @@
-; Tests filetype=obj with -ffunction-sections.
-
-; RUN: %p2i -i %s --filetype=obj --output %t --args -O2 -ffunction-sections && \
-; RUN: llvm-readobj -file-headers -sections -section-data \
-; RUN: -relocations -symbols %t | FileCheck %s
-
-; RUN: %if --need=allow_dump --command \
-; RUN: %p2i -i %s --args -O2 -ffunction-sections \
-; RUN: | %if --need=allow_dump --command \
-; RUN: llvm-mc -triple=i686-nacl -filetype=obj -o - \
-; RUN: | %if --need=allow_dump --command \
-; RUN: llvm-readobj -file-headers -sections -section-data \
-; RUN: -relocations -symbols - \
-; RUN: | %if --need=allow_dump --command FileCheck %s
-
-declare void @llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1)
-
-define internal i32 @foo(i32 %x, i32 %len) {
- %y = add i32 %x, %x
- %dst = inttoptr i32 %y to i8*
- %src = inttoptr i32 %x to i8*
- call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dst, i8* %src,
- i32 %len, i32 1, i1 false)
-
- ret i32 %y
-}
-
-define internal i32 @bar(i32 %x) {
- ret i32 %x
-}
-
-define void @_start(i32 %x) {
- %y = call i32 @bar(i32 4)
- %ignored = call i32 @foo(i32 %x, i32 %y)
- ret void
-}
-
-; CHECK: Section {
-; CHECK: Name: .text.foo
-; CHECK: Type: SHT_PROGBITS
-; CHECK: Flags [ (0x6)
-; CHECK: SHF_ALLOC
-; CHECK: SHF_EXECINSTR
-; CHECK: ]
-; CHECK: }
-; CHECK: Section {
-; CHECK: Name: .rel.text.foo
-; CHECK: Type: SHT_REL
-; CHECK: Flags [ (0x0)
-; CHECK: ]
-; CHECK: }
-
-; CHECK: Section {
-; CHECK: Name: .text.bar
-; CHECK: Type: SHT_PROGBITS
-; CHECK: Flags [ (0x6)
-; CHECK: SHF_ALLOC
-; CHECK: SHF_EXECINSTR
-; CHECK: ]
-; CHECK: }
-
-; CHECK: Section {
-; CHECK: Name: .text._start
-; CHECK: Type: SHT_PROGBITS
-; CHECK: Flags [ (0x6)
-; CHECK: SHF_ALLOC
-; CHECK: SHF_EXECINSTR
-; CHECK: ]
-; CHECK: }
-; CHECK: Section {
-; CHECK: Name: .rel.text._start
-; CHECK: Type: SHT_REL
-; CHECK: Flags [ (0x0)
-; CHECK: ]
-; CHECK: )
-; CHECK: }
-
-; CHECK: Relocations [
-; CHECK: Section ({{[0-9]+}}) .rel.text.foo {
-; CHECK: 0x1E R_386_PC32 memcpy 0x0
-; CHECK: }
-; Relocation can be against the start of the section or
-; the function's symbol itself.
-; CHECK: Section ({{[0-9]+}}) .rel.text._start {
-; CHECK: 0x10 R_386_PC32 {{.*}}bar 0x0
-; CHECK: 0x1C R_386_PC32 {{.*}}foo 0x0
-; CHECK: }
-; CHECK: ]
-
-; CHECK: Symbols [
-; CHECK: Name: bar
-; CHECK: Name: foo
-; CHECK: Name: _start
-; CHECK: Name: memcpy
-; CHECK: ]
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/elf_nodata.ll b/third_party/subzero/tests_lit/llvm2ice_tests/elf_nodata.ll
deleted file mode 100644
index f286044..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/elf_nodata.ll
+++ /dev/null
@@ -1,128 +0,0 @@
-; Tests that we generate an ELF container correctly when there
-; is no data section.
-
-; RUN: %p2i -i %s --filetype=obj --output %t --args -O2 \
-; RUN: && llvm-readobj -file-headers -sections -section-data \
-; RUN: -relocations -symbols %t | FileCheck %s
-
-; RUN: %if --need=allow_dump --command %p2i -i %s --args -O2 \
-; RUN: | %if --need=allow_dump --command \
-; RUN: llvm-mc -triple=i686-nacl -filetype=obj -o - \
-; RUN: | %if --need=allow_dump --command \
-; RUN: llvm-readobj -file-headers -sections -section-data \
-; RUN: -relocations -symbols - \
-; RUN: | %if --need=allow_dump --command FileCheck %s
-
-declare void @llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1)
-
-define internal i32 @foo(i32 %x, i32 %len) {
- %y = add i32 %x, %x
- %dst = inttoptr i32 %y to i8*
- %src = inttoptr i32 %x to i8*
- call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dst, i8* %src,
- i32 %len, i32 1, i1 false)
-
- ret i32 %y
-}
-
-; Test defining a non-internal function.
-define void @_start(i32 %x) {
- %ignored = call i32 @foo(i32 %x, i32 4)
- ret void
-}
-
-; CHECK: Section {
-; CHECK: Index: {{[1-9][0-9]*}}
-; CHECK: Name: .text
-; CHECK: Type: SHT_PROGBITS
-; CHECK: Flags [ (0x6)
-; CHECK: SHF_ALLOC
-; CHECK: SHF_EXECINSTR
-; CHECK: ]
-; CHECK: Address: 0x0
-; CHECK: Offset: 0x{{[1-9A-F][0-9A-F]*}}
-; CHECK: Size: {{[1-9][0-9]*}}
-; CHECK: Link: 0
-; CHECK: Info: 0
-; CHECK: AddressAlignment: 32
-; CHECK: EntrySize: 0
-; CHECK: SectionData (
-; CHECK: )
-; CHECK: }
-; CHECK: Section {
-; CHECK: Index: {{[1-9][0-9]*}}
-; CHECK: Name: .rel.text
-; CHECK: Type: SHT_REL
-; CHECK: Flags [ (0x0)
-; CHECK: ]
-; CHECK: Address: 0x0
-; CHECK: Offset: 0x{{[1-9A-F][0-9A-F]*}}
-; CHECK: Size: {{[1-9][0-9]*}}
-; CHECK: Link: [[SYMTAB_INDEX:[1-9][0-9]*]]
-; CHECK: Info: {{[1-9][0-9]*}}
-; CHECK: AddressAlignment: 4
-; CHECK: EntrySize: 8
-; CHECK: SectionData (
-; CHECK: )
-; CHECK: }
-; CHECK: Section {
-; CHECK: Index: [[SYMTAB_INDEX]]
-; CHECK-NEXT: Name: .symtab
-; CHECK: Type: SHT_SYMTAB
-; CHECK: Flags [ (0x0)
-; CHECK: ]
-; CHECK: Address: 0x0
-; CHECK: Offset: 0x{{[1-9A-F][0-9A-F]*}}
-; CHECK: Size: {{[1-9][0-9]*}}
-; CHECK: Link: {{[1-9][0-9]*}}
-; CHECK: Info: {{[1-9][0-9]*}}
-; CHECK: AddressAlignment: 4
-; CHECK: EntrySize: 16
-; CHECK: }
-
-
-; CHECK: Relocations [
-; CHECK: Section ({{[0-9]+}}) .rel.text {
-; CHECK: 0x1E R_386_PC32 memcpy 0x0
-; CHECK: }
-; CHECK: ]
-
-
-; CHECK: Symbols [
-; CHECK-NEXT: Symbol {
-; CHECK-NEXT: Name: (0)
-; CHECK-NEXT: Value: 0x0
-; CHECK-NEXT: Size: 0
-; CHECK-NEXT: Binding: Local
-; CHECK-NEXT: Type: None
-; CHECK-NEXT: Other: 0
-; CHECK-NEXT: Section: Undefined (0x0)
-; CHECK-NEXT: }
-; CHECK: Symbol {
-; CHECK: Name: foo
-; CHECK-NEXT: Value: 0x0
-; CHECK-NEXT: Size: 0
-; CHECK-NEXT: Binding: Local
-; CHECK-NEXT: Type: None
-; CHECK-NEXT: Other: 0
-; CHECK-NEXT: Section: .text
-; CHECK-NEXT: }
-; CHECK: Symbol {
-; CHECK: Name: _start
-; CHECK-NEXT: Value: 0x{{[1-9A-F][0-9A-F]*}}
-; CHECK-NEXT: Size: 0
-; CHECK-NEXT: Binding: Global
-; CHECK-NEXT: Type: Function
-; CHECK-NEXT: Other: 0
-; CHECK-NEXT: Section: .text
-; CHECK-NEXT: }
-; CHECK: Symbol {
-; CHECK: Name: memcpy
-; CHECK-NEXT: Value: 0x0
-; CHECK-NEXT: Size: 0
-; CHECK-NEXT: Binding: Global
-; CHECK-NEXT: Type: None
-; CHECK-NEXT: Other: 0
-; CHECK-NEXT: Section: Undefined
-; CHECK-NEXT: }
-; CHECK: ]
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/external_declaration.ll b/third_party/subzero/tests_lit/llvm2ice_tests/external_declaration.ll
deleted file mode 100644
index cf8a8bc..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/external_declaration.ll
+++ /dev/null
@@ -1,13 +0,0 @@
-; Tests that any symbols with special names have specially treated linkage.
-
-; RUN: %if --need=allow_dump --command %p2i -i %s --filetype=asm \
-; RUN: --args -nonsfi=0 \
-; RUN: | %if --need=allow_dump --command FileCheck %s
-
-; Verify that "__pnacl_pso_root", a specially named symbol, is made global, but
-; other global variables are not.
-@__pnacl_pso_root = constant [4 x i8] c"abcd";
-@__pnacl_pso_not_root = constant [4 x i8] c"efgh";
-
-; CHECK: .globl __pnacl_pso_root
-; CHECK-NOT: .globl __pnacl_pso_not_root
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/fp.arith.ll b/third_party/subzero/tests_lit/llvm2ice_tests/fp.arith.ll
deleted file mode 100644
index da1c035..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/fp.arith.ll
+++ /dev/null
@@ -1,161 +0,0 @@
-; This tries to be a comprehensive test of f32 and f64 arith operations.
-; The CHECK lines are only checking for basic instruction patterns
-; that should be present regardless of the optimization level, so
-; there are no special OPTM1 match lines.
-
-; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
-; RUN: --target x8632 -i %s --args -O2 \
-; RUN: | %if --need=target_X8632 --command FileCheck %s
-; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
-; RUN: --target x8632 -i %s --args -Om1 \
-; RUN: | %if --need=target_X8632 --command FileCheck %s
-
-; RUN: %if --need=target_ARM32 \
-; RUN: --command %p2i --filetype=obj --disassemble --target arm32 \
-; RUN: -i %s --args -O2 \
-; RUN: | %if --need=target_ARM32 \
-; RUN: --command FileCheck --check-prefix ARM32 %s
-; RUN: %if --need=target_ARM32 \
-; RUN: --command %p2i --filetype=obj --disassemble --target arm32 \
-; RUN: -i %s --args -Om1 \
-; RUN: | %if --need=target_ARM32 \
-; RUN: --command FileCheck --check-prefix ARM32 %s
-
-; RUN: %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command %p2i --filetype=asm --assemble --disassemble --target \
-; RUN: mips32 -i %s --args -O2 \
-; RUN: | %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command FileCheck --check-prefix MIPS32 %s
-; RUN: %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command %p2i --filetype=asm --assemble --disassemble --target \
-; RUN: mips32 -i %s --args -Om1 \
-; RUN: | %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command FileCheck --check-prefix MIPS32 %s
-
-define internal float @addFloat(float %a, float %b) {
-entry:
- %add = fadd float %a, %b
- ret float %add
-}
-; CHECK-LABEL: addFloat
-; CHECK: addss
-; CHECK: fld
-; ARM32-LABEL: addFloat
-; ARM32: vadd.f32 s{{[0-9]+}}, s
-; MIPS32-LABEL: addFloat
-; MIPS32: add.s
-
-define internal double @addDouble(double %a, double %b) {
-entry:
- %add = fadd double %a, %b
- ret double %add
-}
-; CHECK-LABEL: addDouble
-; CHECK: addsd
-; CHECK: fld
-; ARM32-LABEL: addDouble
-; ARM32: vadd.f64 d{{[0-9]+}}, d
-; MIPS32-LABEL: addDouble
-; MIPS32: add.d
-
-define internal float @subFloat(float %a, float %b) {
-entry:
- %sub = fsub float %a, %b
- ret float %sub
-}
-; CHECK-LABEL: subFloat
-; CHECK: subss
-; CHECK: fld
-; ARM32-LABEL: subFloat
-; ARM32: vsub.f32 s{{[0-9]+}}, s
-; MIPS32-LABEL: subFloat
-; MIPS32: sub.s
-
-define internal double @subDouble(double %a, double %b) {
-entry:
- %sub = fsub double %a, %b
- ret double %sub
-}
-; CHECK-LABEL: subDouble
-; CHECK: subsd
-; CHECK: fld
-; ARM32-LABEL: subDouble
-; ARM32: vsub.f64 d{{[0-9]+}}, d
-; MIPS32-LABEL: subDouble
-; MIPS32: sub.d
-
-define internal float @mulFloat(float %a, float %b) {
-entry:
- %mul = fmul float %a, %b
- ret float %mul
-}
-; CHECK-LABEL: mulFloat
-; CHECK: mulss
-; CHECK: fld
-; ARM32-LABEL: mulFloat
-; ARM32: vmul.f32 s{{[0-9]+}}, s
-; MIPS32-LABEL: mulFloat
-; MIPS32: mul.s
-
-define internal double @mulDouble(double %a, double %b) {
-entry:
- %mul = fmul double %a, %b
- ret double %mul
-}
-; CHECK-LABEL: mulDouble
-; CHECK: mulsd
-; CHECK: fld
-; ARM32-LABEL: mulDouble
-; ARM32: vmul.f64 d{{[0-9]+}}, d
-; MIPS32-LABEL: mulDouble
-; MIPS32: mul.d
-
-define internal float @divFloat(float %a, float %b) {
-entry:
- %div = fdiv float %a, %b
- ret float %div
-}
-; CHECK-LABEL: divFloat
-; CHECK: divss
-; CHECK: fld
-; ARM32-LABEL: divFloat
-; ARM32: vdiv.f32 s{{[0-9]+}}, s
-; MIPS32-LABEL: divFloat
-; MIPS32: div.s
-
-define internal double @divDouble(double %a, double %b) {
-entry:
- %div = fdiv double %a, %b
- ret double %div
-}
-; CHECK-LABEL: divDouble
-; CHECK: divsd
-; CHECK: fld
-; ARM32-LABEL: divDouble
-; ARM32: vdiv.f64 d{{[0-9]+}}, d
-; MIPS32-LABEL: divDouble
-; MIPS32: div.d
-
-define internal float @remFloat(float %a, float %b) {
-entry:
- %div = frem float %a, %b
- ret float %div
-}
-; CHECK-LABEL: remFloat
-; CHECK: call {{.*}} R_{{.*}} fmodf
-; ARM32-LABEL: remFloat
-; ARM32: bl {{.*}} fmodf
-; MIPS32-LABEL: remFloat
-; MIPS32: jal {{.*}} fmodf
-
-define internal double @remDouble(double %a, double %b) {
-entry:
- %div = frem double %a, %b
- ret double %div
-}
-; CHECK-LABEL: remDouble
-; CHECK: call {{.*}} R_{{.*}} fmod
-; ARM32-LABEL: remDouble
-; ARM32: bl {{.*}} fmod
-; MIPS32-LABEL: remDouble
-; MIPS32: jal {{.*}} fmod
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/fp.arm.call.ll b/third_party/subzero/tests_lit/llvm2ice_tests/fp.arm.call.ll
deleted file mode 100644
index d45957a..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/fp.arm.call.ll
+++ /dev/null
@@ -1,576 +0,0 @@
-; Tests validating the vfp calling convention for ARM32.
-;
-; RUN: %if --need=target_ARM32 \
-; RUN: --command %p2i --filetype=obj \
-; RUN: --disassemble --target arm32 -i %s --args -O2 \
-; RUN: -allow-externally-defined-symbols \
-; RUN: | %if --need=target_ARM32 \
-; RUN: --command FileCheck %s
-; RUN: %if --need=target_ARM32 \
-; RUN: --command %p2i --filetype=obj --disassemble --target arm32 \
-; RUN: -i %s --args -Om1 \
-; RUN: -allow-externally-defined-symbols \
-; RUN: | %if --need=target_ARM32 \
-; RUN: --command FileCheck %s
-
-; Boring tests ensuring float arguments are allocated "correctly." Unfortunately
-; this test cannot verify whether the right arguments are being allocated to the
-; right register.
-declare void @float1(float %p0)
-declare void @float2(float %p0, float %p1)
-declare void @float3(float %p0, float %p1, float %p2)
-declare void @float4(float %p0, float %p1, float %p2, float %p3)
-declare void @float5(float %p0, float %p1, float %p2, float %p3, float %p4)
-declare void @float6(float %p0, float %p1, float %p2, float %p3, float %p4,
- float %p5)
-declare void @float7(float %p0, float %p1, float %p2, float %p3, float %p4,
- float %p5, float %p6)
-declare void @float8(float %p0, float %p1, float %p2, float %p3, float %p4,
- float %p5, float %p6, float %p7)
-declare void @float9(float %p0, float %p1, float %p2, float %p3, float %p4,
- float %p5, float %p6, float %p7, float %p8)
-declare void @float10(float %p0, float %p1, float %p2, float %p3, float %p4,
- float %p5, float %p6, float %p7, float %p8, float %p9)
-declare void @float11(float %p0, float %p1, float %p2, float %p3, float %p4,
- float %p5, float %p6, float %p7, float %p8, float %p9,
- float %p10)
-declare void @float12(float %p0, float %p1, float %p2, float %p3, float %p4,
- float %p5, float %p6, float %p7, float %p8, float %p9,
- float %p10, float %p11)
-declare void @float13(float %p0, float %p1, float %p2, float %p3, float %p4,
- float %p5, float %p6, float %p7, float %p8, float %p9,
- float %p10, float %p11, float %p12)
-declare void @float14(float %p0, float %p1, float %p2, float %p3, float %p4,
- float %p5, float %p6, float %p7, float %p8, float %p9,
- float %p10, float %p11, float %p12, float %p13)
-declare void @float15(float %p0, float %p1, float %p2, float %p3, float %p4,
- float %p5, float %p6, float %p7, float %p8, float %p9,
- float %p10, float %p11, float %p12, float %p13,
- float %p14)
-declare void @float16(float %p0, float %p1, float %p2, float %p3, float %p4,
- float %p5, float %p6, float %p7, float %p8, float %p9,
- float %p10, float %p11, float %p12, float %p13,
- float %p14, float %p15)
-declare void @float17(float %p0, float %p1, float %p2, float %p3, float %p4,
- float %p5, float %p6, float %p7, float %p8, float %p9,
- float %p10, float %p11, float %p12, float %p13,
- float %p14, float %p15, float %p16)
-declare void @float18(float %p0, float %p1, float %p2, float %p3, float %p4,
- float %p5, float %p6, float %p7, float %p8, float %p9,
- float %p10, float %p11, float %p12, float %p13,
- float %p14, float %p15, float %p16, float %p17)
-define internal void @floatHarness() nounwind {
-; CHECK-LABEL: floatHarness
- call void @float1(float 1.0)
-; CHECK-DAG: vmov.f32 s0
-; CHECK: bl {{.*}} float1
- call void @float2(float 1.0, float 2.0)
-; CHECK-DAG: vmov.f32 s0
-; CHECK-DAG: vmov.f32 s1
-; CHECK: bl {{.*}} float2
- call void @float3(float 1.0, float 2.0, float 3.0)
-; CHECK-DAG: vmov.f32 s0
-; CHECK-DAG: vmov.f32 s1
-; CHECK-DAG: vmov.f32 s2
-; CHECK: bl {{.*}} float3
- call void @float4(float 1.0, float 2.0, float 3.0, float 4.0)
-; CHECK-DAG: vmov.f32 s0
-; CHECK-DAG: vmov.f32 s1
-; CHECK-DAG: vmov.f32 s2
-; CHECK-DAG: vmov.f32 s3
-; CHECK: bl {{.*}} float4
- call void @float5(float 1.0, float 2.0, float 3.0, float 4.0, float 5.0)
-; CHECK-DAG: vmov.f32 s0
-; CHECK-DAG: vmov.f32 s1
-; CHECK-DAG: vmov.f32 s2
-; CHECK-DAG: vmov.f32 s3
-; CHECK-DAG: vmov.f32 s4
-; CHECK: bl {{.*}} float5
- call void @float6(float 1.0, float 2.0, float 3.0, float 4.0, float 5.0,
- float 6.0)
-; CHECK-DAG: vmov.f32 s0
-; CHECK-DAG: vmov.f32 s1
-; CHECK-DAG: vmov.f32 s2
-; CHECK-DAG: vmov.f32 s3
-; CHECK-DAG: vmov.f32 s4
-; CHECK-DAG: vmov.f32 s5
-; CHECK: bl {{.*}} float6
- call void @float7(float 1.0, float 2.0, float 3.0, float 4.0, float 5.0,
- float 6.0, float 7.0)
-; CHECK-DAG: vmov.f32 s0
-; CHECK-DAG: vmov.f32 s1
-; CHECK-DAG: vmov.f32 s2
-; CHECK-DAG: vmov.f32 s3
-; CHECK-DAG: vmov.f32 s4
-; CHECK-DAG: vmov.f32 s5
-; CHECK-DAG: vmov.f32 s6
-; CHECK: bl {{.*}} float7
- call void @float8(float 1.0, float 2.0, float 3.0, float 4.0, float 5.0,
- float 6.0, float 7.0, float 8.0)
-; CHECK-DAG: vmov.f32 s0
-; CHECK-DAG: vmov.f32 s1
-; CHECK-DAG: vmov.f32 s2
-; CHECK-DAG: vmov.f32 s3
-; CHECK-DAG: vmov.f32 s4
-; CHECK-DAG: vmov.f32 s5
-; CHECK-DAG: vmov.f32 s6
-; CHECK-DAG: vmov.f32 s7
-; CHECK: bl {{.*}} float8
- call void @float9(float 1.0, float 2.0, float 3.0, float 4.0, float 5.0,
- float 6.0, float 7.0, float 8.0, float 9.0)
-; CHECK-DAG: vmov.f32 s0
-; CHECK-DAG: vmov.f32 s1
-; CHECK-DAG: vmov.f32 s2
-; CHECK-DAG: vmov.f32 s3
-; CHECK-DAG: vmov.f32 s4
-; CHECK-DAG: vmov.f32 s5
-; CHECK-DAG: vmov.f32 s6
-; CHECK-DAG: vmov.f32 s7
-; CHECK-DAG: vmov.f32 s8
-; CHECK: bl {{.*}} float9
- call void @float10(float 1.0, float 2.0, float 3.0, float 4.0, float 5.0,
- float 6.0, float 7.0, float 8.0, float 9.0, float 10.0)
-; CHECK-DAG: vmov.f32 s0
-; CHECK-DAG: vmov.f32 s1
-; CHECK-DAG: vmov.f32 s2
-; CHECK-DAG: vmov.f32 s3
-; CHECK-DAG: vmov.f32 s4
-; CHECK-DAG: vmov.f32 s5
-; CHECK-DAG: vmov.f32 s6
-; CHECK-DAG: vmov.f32 s7
-; CHECK-DAG: vmov.f32 s8
-; CHECK-DAG: vmov.f32 s9
-; CHECK: bl {{.*}} float10
- call void @float11(float 1.0, float 2.0, float 3.0, float 4.0, float 5.0,
- float 6.0, float 7.0, float 8.0, float 9.0, float 10.0,
- float 11.0)
-; CHECK-DAG: vmov.f32 s0
-; CHECK-DAG: vmov.f32 s1
-; CHECK-DAG: vmov.f32 s2
-; CHECK-DAG: vmov.f32 s3
-; CHECK-DAG: vmov.f32 s4
-; CHECK-DAG: vmov.f32 s5
-; CHECK-DAG: vmov.f32 s6
-; CHECK-DAG: vmov.f32 s7
-; CHECK-DAG: vmov.f32 s8
-; CHECK-DAG: vmov.f32 s9
-; CHECK-DAG: vmov.f32 s10
-; CHECK: bl {{.*}} float11
- call void @float12(float 1.0, float 2.0, float 3.0, float 4.0, float 5.0,
- float 6.0, float 7.0, float 8.0, float 9.0, float 10.0,
- float 11.0, float 12.0)
-; CHECK-DAG: vmov.f32 s0
-; CHECK-DAG: vmov.f32 s1
-; CHECK-DAG: vmov.f32 s2
-; CHECK-DAG: vmov.f32 s3
-; CHECK-DAG: vmov.f32 s4
-; CHECK-DAG: vmov.f32 s5
-; CHECK-DAG: vmov.f32 s6
-; CHECK-DAG: vmov.f32 s7
-; CHECK-DAG: vmov.f32 s8
-; CHECK-DAG: vmov.f32 s9
-; CHECK-DAG: vmov.f32 s10
-; CHECK-DAG: vmov.f32 s11
-; CHECK: bl {{.*}} float12
- call void @float13(float 1.0, float 2.0, float 3.0, float 4.0, float 5.0,
- float 6.0, float 7.0, float 8.0, float 9.0, float 10.0,
- float 11.0, float 12.0, float 13.0)
-; CHECK-DAG: vmov.f32 s0
-; CHECK-DAG: vmov.f32 s1
-; CHECK-DAG: vmov.f32 s2
-; CHECK-DAG: vmov.f32 s3
-; CHECK-DAG: vmov.f32 s4
-; CHECK-DAG: vmov.f32 s5
-; CHECK-DAG: vmov.f32 s6
-; CHECK-DAG: vmov.f32 s7
-; CHECK-DAG: vmov.f32 s8
-; CHECK-DAG: vmov.f32 s9
-; CHECK-DAG: vmov.f32 s10
-; CHECK-DAG: vmov.f32 s11
-; CHECK-DAG: vmov.f32 s12
-; CHECK: bl {{.*}} float13
- call void @float14(float 1.0, float 2.0, float 3.0, float 4.0, float 5.0,
- float 6.0, float 7.0, float 8.0, float 9.0, float 10.0,
- float 11.0, float 12.0, float 13.0, float 14.0)
-; CHECK-DAG: vmov.f32 s0
-; CHECK-DAG: vmov.f32 s1
-; CHECK-DAG: vmov.f32 s2
-; CHECK-DAG: vmov.f32 s3
-; CHECK-DAG: vmov.f32 s4
-; CHECK-DAG: vmov.f32 s5
-; CHECK-DAG: vmov.f32 s6
-; CHECK-DAG: vmov.f32 s7
-; CHECK-DAG: vmov.f32 s8
-; CHECK-DAG: vmov.f32 s9
-; CHECK-DAG: vmov.f32 s10
-; CHECK-DAG: vmov.f32 s11
-; CHECK-DAG: vmov.f32 s12
-; CHECK-DAG: vmov.f32 s13
-; CHECK: bl {{.*}} float14
- call void @float15(float 1.0, float 2.0, float 3.0, float 4.0, float 5.0,
- float 6.0, float 7.0, float 8.0, float 9.0, float 10.0,
- float 11.0, float 12.0, float 13.0, float 14.0,
- float 15.0)
-; CHECK-DAG: vmov.f32 s0
-; CHECK-DAG: vmov.f32 s1
-; CHECK-DAG: vmov.f32 s2
-; CHECK-DAG: vmov.f32 s3
-; CHECK-DAG: vmov.f32 s4
-; CHECK-DAG: vmov.f32 s5
-; CHECK-DAG: vmov.f32 s6
-; CHECK-DAG: vmov.f32 s7
-; CHECK-DAG: vmov.f32 s8
-; CHECK-DAG: vmov.f32 s9
-; CHECK-DAG: vmov.f32 s10
-; CHECK-DAG: vmov.f32 s11
-; CHECK-DAG: vmov.f32 s12
-; CHECK-DAG: vmov.f32 s13
-; CHECK-DAG: vmov.f32 s14
-; CHECK: bl {{.*}} float15
- call void @float16(float 1.0, float 2.0, float 3.0, float 4.0, float 5.0,
- float 6.0, float 7.0, float 8.0, float 9.0, float 10.0,
- float 11.0, float 12.0, float 13.0, float 14.0,
- float 15.0, float 16.0)
-; CHECK-DAG: vmov.f32 s0
-; CHECK-DAG: vmov.f32 s1
-; CHECK-DAG: vmov.f32 s2
-; CHECK-DAG: vmov.f32 s3
-; CHECK-DAG: vmov.f32 s4
-; CHECK-DAG: vmov.f32 s5
-; CHECK-DAG: vmov.f32 s6
-; CHECK-DAG: vmov.f32 s7
-; CHECK-DAG: vmov.f32 s8
-; CHECK-DAG: vmov.f32 s9
-; CHECK-DAG: vmov.f32 s10
-; CHECK-DAG: vmov.f32 s11
-; CHECK-DAG: vmov.f32 s12
-; CHECK-DAG: vmov.f32 s13
-; CHECK-DAG: vmov.f32 s14
-; CHECK-DAG: vmov.f32 s15
-; CHECK: bl {{.*}} float16
- call void @float17(float 1.0, float 2.0, float 3.0, float 4.0, float 5.0,
- float 6.0, float 7.0, float 8.0, float 9.0, float 10.0,
- float 11.0, float 12.0, float 13.0, float 14.0,
- float 15.0, float 16.0, float 17.0)
-; CHECK-DAG: vmov.f32 s0
-; CHECK-DAG: vmov.f32 s1
-; CHECK-DAG: vmov.f32 s2
-; CHECK-DAG: vmov.f32 s3
-; CHECK-DAG: vmov.f32 s4
-; CHECK-DAG: vmov.f32 s5
-; CHECK-DAG: vmov.f32 s6
-; CHECK-DAG: vmov.f32 s7
-; CHECK-DAG: vmov.f32 s8
-; CHECK-DAG: vmov.f32 s9
-; CHECK-DAG: vmov.f32 s10
-; CHECK-DAG: vmov.f32 s11
-; CHECK-DAG: vmov.f32 s12
-; CHECK-DAG: vmov.f32 s13
-; CHECK-DAG: vmov.f32 s14
-; CHECK-DAG: vmov.f32 s15
-; CHECK-DAG: vstr s{{.*}}, [sp]
-; CHECK: bl {{.*}} float17
- call void @float18(float 1.0, float 2.0, float 3.0, float 4.0, float 5.0,
- float 6.0, float 7.0, float 8.0, float 9.0, float 10.0,
- float 11.0, float 12.0, float 13.0, float 14.0,
- float 15.0, float 16.0, float 17.0, float 18.0)
-; CHECK-DAG: vmov.f32 s0
-; CHECK-DAG: vmov.f32 s1
-; CHECK-DAG: vmov.f32 s2
-; CHECK-DAG: vmov.f32 s3
-; CHECK-DAG: vmov.f32 s4
-; CHECK-DAG: vmov.f32 s5
-; CHECK-DAG: vmov.f32 s6
-; CHECK-DAG: vmov.f32 s7
-; CHECK-DAG: vmov.f32 s8
-; CHECK-DAG: vmov.f32 s9
-; CHECK-DAG: vmov.f32 s10
-; CHECK-DAG: vmov.f32 s11
-; CHECK-DAG: vmov.f32 s12
-; CHECK-DAG: vmov.f32 s13
-; CHECK-DAG: vmov.f32 s14
-; CHECK-DAG: vmov.f32 s15
-; CHECK-DAG: vstr s{{.*}}, [sp]
-; CHECK-DAG: vstr s{{.*}}, [sp, #4]
-; CHECK: bl {{.*}} float18
- ret void
-}
-
-declare void @double1(double %p0)
-declare void @double2(double %p0, double %p1)
-declare void @double3(double %p0, double %p1, double %p2)
-declare void @double4(double %p0, double %p1, double %p2, double %p3)
-declare void @double5(double %p0, double %p1, double %p2, double %p3,
- double %p4)
-declare void @double6(double %p0, double %p1, double %p2, double %p3,
- double %p4, double %p5)
-declare void @double7(double %p0, double %p1, double %p2, double %p3,
- double %p4, double %p5, double %p6)
-declare void @double8(double %p0, double %p1, double %p2, double %p3,
- double %p4, double %p5, double %p6, double %p7)
-declare void @double9(double %p0, double %p1, double %p2, double %p3,
- double %p4, double %p5, double %p6, double %p7,
- double %p8)
-declare void @double10(double %p0, double %p1, double %p2, double %p3,
- double %p4, double %p5, double %p6, double %p7,
- double %p8, double %p9)
-define internal void @doubleHarness() nounwind {
-; CHECK-LABEL: doubleHarness
- call void @double1(double 1.0)
-; CHECK-DAG: vmov.f64 d0
-; CHECK: bl {{.*}} double1
- call void @double2(double 1.0, double 2.0)
-; CHECK-DAG: vmov.f64 d0
-; CHECK-DAG: vmov.f64 d1
-; CHECK: bl {{.*}} double2
- call void @double3(double 1.0, double 2.0, double 3.0)
-; CHECK-DAG: vmov.f64 d0
-; CHECK-DAG: vmov.f64 d1
-; CHECK-DAG: vmov.f64 d2
-; CHECK: bl {{.*}} double3
- call void @double4(double 1.0, double 2.0, double 3.0, double 4.0)
-; CHECK-DAG: vmov.f64 d0
-; CHECK-DAG: vmov.f64 d1
-; CHECK-DAG: vmov.f64 d2
-; CHECK-DAG: vmov.f64 d3
-; CHECK: bl {{.*}} double4
- call void @double5(double 1.0, double 2.0, double 3.0, double 4.0,
- double 5.0)
-; CHECK-DAG: vmov.f64 d0
-; CHECK-DAG: vmov.f64 d1
-; CHECK-DAG: vmov.f64 d2
-; CHECK-DAG: vmov.f64 d3
-; CHECK-DAG: vmov.f64 d4
-; CHECK: bl {{.*}} double5
- call void @double6(double 1.0, double 2.0, double 3.0, double 4.0,
- double 5.0, double 6.0)
-; CHECK-DAG: vmov.f64 d0
-; CHECK-DAG: vmov.f64 d1
-; CHECK-DAG: vmov.f64 d2
-; CHECK-DAG: vmov.f64 d3
-; CHECK-DAG: vmov.f64 d4
-; CHECK-DAG: vmov.f64 d5
-; CHECK: bl {{.*}} double6
- call void @double7(double 1.0, double 2.0, double 3.0, double 4.0,
- double 5.0, double 6.0, double 7.0)
-; CHECK-DAG: vmov.f64 d0
-; CHECK-DAG: vmov.f64 d1
-; CHECK-DAG: vmov.f64 d2
-; CHECK-DAG: vmov.f64 d3
-; CHECK-DAG: vmov.f64 d4
-; CHECK-DAG: vmov.f64 d5
-; CHECK-DAG: vmov.f64 d6
-; CHECK: bl {{.*}} double7
- call void @double8(double 1.0, double 2.0, double 3.0, double 4.0,
- double 5.0, double 6.0, double 7.0, double 8.0)
-; CHECK-DAG: vmov.f64 d0
-; CHECK-DAG: vmov.f64 d1
-; CHECK-DAG: vmov.f64 d2
-; CHECK-DAG: vmov.f64 d3
-; CHECK-DAG: vmov.f64 d4
-; CHECK-DAG: vmov.f64 d5
-; CHECK-DAG: vmov.f64 d6
-; CHECK-DAG: vmov.f64 d7
-; CHECK: bl {{.*}} double8
- call void @double9(double 1.0, double 2.0, double 3.0, double 4.0,
- double 5.0, double 6.0, double 7.0, double 8.0,
- double 9.0)
-; CHECK-DAG: vmov.f64 d0
-; CHECK-DAG: vmov.f64 d1
-; CHECK-DAG: vmov.f64 d2
-; CHECK-DAG: vmov.f64 d3
-; CHECK-DAG: vmov.f64 d4
-; CHECK-DAG: vmov.f64 d5
-; CHECK-DAG: vmov.f64 d6
-; CHECK-DAG: vmov.f64 d7
-; CHECK-DAG: vstr d{{.*}}, [sp]
-; CHECK: bl {{.*}} double9
- call void @double10(double 1.0, double 2.0, double 3.0, double 4.0,
- double 5.0, double 6.0, double 7.0, double 8.0,
- double 9.0, double 10.0)
-; CHECK-DAG: vmov.f64 d0
-; CHECK-DAG: vmov.f64 d1
-; CHECK-DAG: vmov.f64 d2
-; CHECK-DAG: vmov.f64 d3
-; CHECK-DAG: vmov.f64 d4
-; CHECK-DAG: vmov.f64 d5
-; CHECK-DAG: vmov.f64 d6
-; CHECK-DAG: vmov.f64 d7
-; CHECK-DAG: vstr d{{.*}}, [sp]
-; CHECK-DAG: vstr d{{.*}}, [sp, #8]
-; CHECK: bl {{.*}} double10
-
- ret void
-}
-
-declare void @testFDF(float %p0, double %p1, float %p2)
-declare void @testFDDF(float %p0, double %p1, double %p2, float %p3)
-declare void @testFDDDF(float %p0, double %p1, double %p2, double %p3,
- float %p4)
-declare void @testFDDDDF(float %p0, double %p1, double %p2, double %p3,
- double %p4, float %p5)
-declare void @testFDDDDDF(float %p0, double %p1, double %p2, double %p3,
- double %p4, double %p5, float %p6)
-declare void @testFDDDDDDF(float %p0, double %p1, double %p2, double %p3,
- double %p4, double %p5, double %p6, float %p7)
-declare void @testFDDDDDDDF(float %p0, double %p1, double %p2, double %p3,
- double %p4, double %p5, double %p6, double %p7,
- float %p8)
-declare void @testFDDDDDDDFD(float %p0, double %p1, double %p2, double %p3,
- double %p4, double %p5, double %p6, double %p7,
- float %p8, double %p9)
-declare void @testFDDDDDDDDF(float %p0, double %p1, double %p2, double %p3,
- double %p4, double %p5, double %p6, double %p7,
- double %p8, float %p9)
-declare void @testFDDDDDDDDDF(float %p0, double %p1, double %p2, double %p3,
- double %p4, double %p5, double %p6, double %p7,
- double %p8, double %p9, float %p10)
-declare void @testFDDDDDDDDFD(float %p0, double %p1, double %p2, double %p3,
- double %p4, double %p5, double %p6, double %p7,
- double %p8, float %p9, double %p10)
-declare void @testFDDDDDDDDFDF(float %p0, double %p1, double %p2, double %p3,
- double %p4, double %p5, double %p6, double %p7,
- double %p8, float %p9, double %p10, float %p11)
-define internal void @packsFloats() nounwind {
-; CHECK-LABEL: packsFloats
- call void @testFDF(float 1.0, double 2.0, float 3.0)
-; CHECK-DAG: vmov.f32 s0
-; CHECK-DAG: vmov.f64 d1
-; CHECK-DAG: vmov.f32 s1
-; CHECK: bl {{.*}} testFDF
- call void @testFDDF(float 1.0, double 2.0, double 3.0, float 4.0)
-; CHECK-DAG: vmov.f32 s0
-; CHECK-DAG: vmov.f64 d1
-; CHECK-DAG: vmov.f64 d2
-; CHECK-DAG: vmov.f32 s1
-; CHECK: bl {{.*}} testFDDF
- call void @testFDDDF(float 1.0, double 2.0, double 3.0, double 4.0,
- float 5.0)
-; CHECK-DAG: vmov.f32 s0
-; CHECK-DAG: vmov.f64 d1
-; CHECK-DAG: vmov.f64 d2
-; CHECK-DAG: vmov.f64 d3
-; CHECK-DAG: vmov.f32 s1
-; CHECK: bl {{.*}} testFDDDF
- call void @testFDDDDF(float 1.0, double 2.0, double 3.0, double 4.0,
- double 5.0, float 6.0)
-; CHECK-DAG: vmov.f32 s0
-; CHECK-DAG: vmov.f64 d1
-; CHECK-DAG: vmov.f64 d2
-; CHECK-DAG: vmov.f64 d3
-; CHECK-DAG: vmov.f64 d4
-; CHECK-DAG: vmov.f32 s1
-; CHECK: bl {{.*}} testFDDDDF
- call void @testFDDDDDF(float 1.0, double 2.0, double 3.0, double 4.0,
- double 5.0, double 6.0, float 7.0)
-; CHECK-DAG: vmov.f32 s0
-; CHECK-DAG: vmov.f64 d1
-; CHECK-DAG: vmov.f64 d2
-; CHECK-DAG: vmov.f64 d3
-; CHECK-DAG: vmov.f64 d4
-; CHECK-DAG: vmov.f64 d5
-; CHECK-DAG: vmov.f32 s1
-; CHECK: bl {{.*}} testFDDDDDF
- call void @testFDDDDDDF(float 1.0, double 2.0, double 3.0, double 4.0,
- double 5.0, double 6.0, double 7.0, float 8.0)
-; CHECK-DAG: vmov.f32 s0
-; CHECK-DAG: vmov.f64 d1
-; CHECK-DAG: vmov.f64 d2
-; CHECK-DAG: vmov.f64 d3
-; CHECK-DAG: vmov.f64 d4
-; CHECK-DAG: vmov.f64 d5
-; CHECK-DAG: vmov.f64 d6
-; CHECK-DAG: vmov.f32 s1
-; CHECK: bl {{.*}} testFDDDDDDF
- call void @testFDDDDDDDF(float 1.0, double 2.0, double 3.0, double 4.0,
- double 5.0, double 6.0, double 7.0, double 8.0,
- float 9.0)
-; CHECK-DAG: vmov.f32 s0
-; CHECK-DAG: vmov.f64 d1
-; CHECK-DAG: vmov.f64 d2
-; CHECK-DAG: vmov.f64 d3
-; CHECK-DAG: vmov.f64 d4
-; CHECK-DAG: vmov.f64 d5
-; CHECK-DAG: vmov.f64 d6
-; CHECK-DAG: vmov.f64 d7
-; CHECK-DAG: vmov.f32 s1
-; CHECK: bl {{.*}} testFDDDDDDDF
- call void @testFDDDDDDDFD(float 1.0, double 2.0, double 3.0, double 4.0,
- double 5.0, double 6.0, double 7.0, double 8.0,
- float 9.0, double 10.0)
-; CHECK-DAG: vmov.f32 s0
-; CHECK-DAG: vmov.f64 d1
-; CHECK-DAG: vmov.f64 d2
-; CHECK-DAG: vmov.f64 d3
-; CHECK-DAG: vmov.f64 d4
-; CHECK-DAG: vmov.f64 d5
-; CHECK-DAG: vmov.f64 d6
-; CHECK-DAG: vmov.f64 d7
-; CHECK-DAG: vstr d{{.*}}, [sp]
-; CHECK-DAG: vmov.f32 s1
-; CHECK: bl {{.*}} testFDDDDDDDFD
- call void @testFDDDDDDDDF(float 1.0, double 2.0, double 3.0, double 4.0,
- double 5.0, double 6.0, double 7.0, double 8.0,
- double 9.0, float 10.0)
-; CHECK-DAG: vmov.f32 s0
-; CHECK-DAG: vmov.f64 d1
-; CHECK-DAG: vmov.f64 d2
-; CHECK-DAG: vmov.f64 d3
-; CHECK-DAG: vmov.f64 d4
-; CHECK-DAG: vmov.f64 d5
-; CHECK-DAG: vmov.f64 d6
-; CHECK-DAG: vmov.f64 d7
-; CHECK-DAG: vstr d{{.*}}, [sp]
-; CHECK-DAG: vstr s{{.*}}, [sp, #8]
-; CHECK: bl {{.*}} testFDDDDDDDDF
- call void @testFDDDDDDDDDF(float 1.0, double 2.0, double 3.0, double 4.0,
- double 5.0, double 6.0, double 7.0, double 8.0,
- double 9.0, double 10.0, float 11.0)
-; CHECK-DAG: vmov.f32 s0
-; CHECK-DAG: vmov.f64 d1
-; CHECK-DAG: vmov.f64 d2
-; CHECK-DAG: vmov.f64 d3
-; CHECK-DAG: vmov.f64 d4
-; CHECK-DAG: vmov.f64 d5
-; CHECK-DAG: vmov.f64 d6
-; CHECK-DAG: vmov.f64 d7
-; CHECK-DAG: vstr d{{.*}}, [sp]
-; CHECK-DAG: vstr d{{.*}}, [sp, #8]
-; CHECK-DAG: vstr s{{.*}}, [sp, #16]
-; CHECK: bl {{.*}} testFDDDDDDDDDF
- call void @testFDDDDDDDDFD(float 1.0, double 2.0, double 3.0, double 4.0,
- double 5.0, double 6.0, double 7.0, double 8.0,
- double 9.0, float 10.0, double 11.0)
-; CHECK-DAG: vmov.f32 s0
-; CHECK-DAG: vmov.f64 d1
-; CHECK-DAG: vmov.f64 d2
-; CHECK-DAG: vmov.f64 d3
-; CHECK-DAG: vmov.f64 d4
-; CHECK-DAG: vmov.f64 d5
-; CHECK-DAG: vmov.f64 d6
-; CHECK-DAG: vmov.f64 d7
-; CHECK-DAG: vstr d{{.*}}, [sp]
-; CHECK-DAG: vstr s{{.*}}, [sp, #8]
-; CHECK-DAG: vstr d{{.*}}, [sp, #16]
-; CHECK: bl {{.*}} testFDDDDDDDDFD
- call void @testFDDDDDDDDFDF(float 1.0, double 2.0, double 3.0, double 4.0,
- double 5.0, double 6.0, double 7.0, double 8.0,
- double 9.0, float 10.0, double 11.0, float 12.0)
-; CHECK-DAG: vmov.f32 s0
-; CHECK-DAG: vmov.f64 d1
-; CHECK-DAG: vmov.f64 d2
-; CHECK-DAG: vmov.f64 d3
-; CHECK-DAG: vmov.f64 d4
-; CHECK-DAG: vmov.f64 d5
-; CHECK-DAG: vmov.f64 d6
-; CHECK-DAG: vmov.f64 d7
-; CHECK-DAG: vstr d{{.*}}, [sp]
-; CHECK-DAG: vstr s{{.*}}, [sp, #8]
-; CHECK-DAG: vstr d{{.*}}, [sp, #16]
-; CHECK-DAG: vstr s{{.*}}, [sp, #24]
-; CHECK: bl {{.*}} testFDDDDDDDDFD
-
- ret void
-}
-
-; TODO(jpp): add tests for stack alignment.
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/fp.call_ret.ll b/third_party/subzero/tests_lit/llvm2ice_tests/fp.call_ret.ll
deleted file mode 100644
index 460d70c..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/fp.call_ret.ll
+++ /dev/null
@@ -1,147 +0,0 @@
-; This tries to be a comprehensive test of f32 and f64 call/return ops.
-; The CHECK lines are only checking for basic instruction patterns
-; that should be present regardless of the optimization level, so
-; there are no special OPTM1 match lines.
-
-; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
-; RUN: --target x8632 -i %s --args -O2 -allow-externally-defined-symbols \
-; RUN: | %if --need=target_X8632 --command FileCheck %s
-; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
-; RUN: --target x8632 -i %s --args -Om1 -allow-externally-defined-symbols \
-; RUN: | %if --need=target_X8632 --command FileCheck %s
-
-; RUN: %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command %p2i --filetype=asm --assemble --disassemble --target \
-; RUN: mips32 -i %s --args -O2 -allow-externally-defined-symbols \
-; RUN: | %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command FileCheck --check-prefix MIPS32 %s
-
-; Can't test on ARM yet. Need to use several vpush {contiguous FP regs},
-; instead of push {any GPR list}.
-
-define internal i32 @doubleArgs(double %a, i32 %b, double %c) {
-entry:
- ret i32 %b
-}
-; CHECK-LABEL: doubleArgs
-; CHECK: mov eax,DWORD PTR [esp+0xc]
-; CHECK-NEXT: ret
-; ARM32-LABEL: doubleArgs
-; MIPS32-LABEL: doubleArgs
-; MIPS32: move v0,a2
-; MIPS32: jr ra
-
-define internal i32 @floatArgs(float %a, i32 %b, float %c) {
-entry:
- ret i32 %b
-}
-; CHECK-LABEL: floatArgs
-; CHECK: mov eax,DWORD PTR [esp+0x8]
-; CHECK-NEXT: ret
-; MIPS32-LABEL: floatArgs
-; MIPS32: move v0,a1
-; MIPS32: jr ra
-
-define internal i32 @passFpArgs(float %a, double %b, float %c, double %d, float %e, double %f) {
-entry:
- %call = call i32 @ignoreFpArgsNoInline(float %a, i32 123, double %b)
- %call1 = call i32 @ignoreFpArgsNoInline(float %c, i32 123, double %d)
- %call2 = call i32 @ignoreFpArgsNoInline(float %e, i32 123, double %f)
- %add = add i32 %call1, %call
- %add3 = add i32 %add, %call2
- ret i32 %add3
-}
-; CHECK-LABEL: passFpArgs
-; CHECK: mov DWORD PTR [esp+0x4],0x7b
-; CHECK: call {{.*}} R_{{.*}} ignoreFpArgsNoInline
-; CHECK: mov DWORD PTR [esp+0x4],0x7b
-; CHECK: call {{.*}} R_{{.*}} ignoreFpArgsNoInline
-; CHECK: mov DWORD PTR [esp+0x4],0x7b
-; CHECK: call {{.*}} R_{{.*}} ignoreFpArgsNoInline
-; MIPS32-LABEL: passFpArgs
-; MIPS32: mfc1 a2,$f{{[0-9]+}}
-; MIPS32: mfc1 a3,$f{{[0-9]+}}
-; MIPS32: li a1,123
-; MIPS32: jal {{.*}} ignoreFpArgsNoInline
-; MIPS32: mfc1 a2,$f{{[0-9]+}}
-; MIPS32: mfc1 a3,$f{{[0-9]+}}
-; MIPS32: li a1,123
-; MIPS32: jal {{.*}} ignoreFpArgsNoInline
-; MIPS32: mfc1 a2,$f{{[0-9]+}}
-; MIPS32: mfc1 a3,$f{{[0-9]+}}
-; MIPS32: li a1,123
-; MIPS32: jal {{.*}} ignoreFpArgsNoInline
-
-declare i32 @ignoreFpArgsNoInline(float %x, i32 %y, double %z)
-
-define internal i32 @passFpConstArg(float %a, double %b) {
-entry:
- %call = call i32 @ignoreFpArgsNoInline(float %a, i32 123, double 2.340000e+00)
- ret i32 %call
-}
-; CHECK-LABEL: passFpConstArg
-; CHECK: mov DWORD PTR [esp+0x4],0x7b
-; CHECK: call {{.*}} R_{{.*}} ignoreFpArgsNoInline
-; MIPS32-LABEL: passFpConstArg
-; MIPS32: mfc1 a2,$f{{[0-9]+}}
-; MIPS32: mfc1 a3,$f{{[0-9]+}}
-; MIPS32: li a1,123
-; MIPS32: jal {{.*}} ignoreFpArgsNoInline
-
-define internal i32 @passFp32ConstArg(float %a) {
-entry:
- %call = call i32 @ignoreFp32ArgsNoInline(float %a, i32 123, float 2.0)
- ret i32 %call
-}
-; CHECK-LABEL: passFp32ConstArg
-; CHECK: mov DWORD PTR [esp+0x4],0x7b
-; CHECK: movss DWORD PTR [esp+0x8]
-; CHECK: call {{.*}} R_{{.*}} ignoreFp32ArgsNoInline
-; MIPS32-LABEL: passFp32ConstArg
-; MIPS32: mfc1 a2,$f0
-; MIPS32: li a1,123
-; MIPS32: jal {{.*}} ignoreFp32ArgsNoInline
-
-declare i32 @ignoreFp32ArgsNoInline(float %x, i32 %y, float %z)
-
-define internal float @returnFloatArg(float %a) {
-entry:
- ret float %a
-}
-; CHECK-LABEL: returnFloatArg
-; CHECK: fld DWORD PTR [esp
-; MIPS32-LABEL: returnFloatArg
-; MIPS32: mov.s $f0,$f12
-; MIPS32: jr ra
-
-define internal double @returnDoubleArg(double %a) {
-entry:
- ret double %a
-}
-; CHECK-LABEL: returnDoubleArg
-; CHECK: fld QWORD PTR [esp
-; MIPS32-LABEL: returnDoubleArg
-; MIPS32: mov.d $f0,$f12
-; MIPS32: jr ra
-
-define internal float @returnFloatConst() {
-entry:
- ret float 0x3FF3AE1480000000
-}
-; CHECK-LABEL: returnFloatConst
-; CHECK: fld
-; MIPS32-LABEL: returnFloatConst
-; MIPS32: lui v0,0x0 {{.*}} .L$float$3f9d70a4
-; MIPS32: lwc1 $f0,0(v0) {{.*}} .L$float$3f9d70a4
-; MIPS32: jr ra
-
-define internal double @returnDoubleConst() {
-entry:
- ret double 1.230000e+00
-}
-; CHECK-LABEL: returnDoubleConst
-; CHECK: fld
-; MIPS32-LABEL: returnDoubleConst
-; MIPS32: lui v0,0x0 {{.*}} .L$double$3ff3ae147ae147ae
-; MIPS32: ldc1 $f0,0(v0) {{.*}} .L$double$3ff3ae147ae147ae
-; MIPS32: jr ra
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/fp.cmp.ll b/third_party/subzero/tests_lit/llvm2ice_tests/fp.cmp.ll
deleted file mode 100644
index ce646f2..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/fp.cmp.ll
+++ /dev/null
@@ -1,1027 +0,0 @@
-; This tries to be a comprehensive test of f32 and f64 compare operations.
-
-; RUN: %p2i --filetype=obj --disassemble -i %s --args -O2 \
-; RUN: -allow-externally-defined-symbols | FileCheck %s
-; RUN: %p2i --filetype=obj --disassemble -i %s --args -Om1 \
-; RUN: -allow-externally-defined-symbols | FileCheck %s \
-; RUN: --check-prefix=CHECK-OM1
-
-; RUN: %if --need=target_ARM32 --command %p2i --filetype=obj --disassemble \
-; RUN: --target arm32 -i %s --args -O2 \
-; RUN: -allow-externally-defined-symbols \
-; RUN: | %if --need=target_ARM32 --command FileCheck %s \
-; RUN: --check-prefix=ARM32 --check-prefix=ARM32-O2
-
-; RUN: %if --need=target_ARM32 --command %p2i --filetype=obj --disassemble \
-; RUN: --target arm32 -i %s --args -Om1 \
-; RUN: -allow-externally-defined-symbols \
-; RUN: | %if --need=target_ARM32 --command FileCheck %s \
-; RUN: --check-prefix=ARM32 --check-prefix=ARM32-OM1
-
-; RUN: %if --need=allow_dump --need=target_MIPS32 --command %p2i \
-; RUN: --filetype=asm --target mips32 -i %s --args -Om1 \
-; RUN: -allow-externally-defined-symbols \
-; RUN: | %if --need=allow_dump --need=target_MIPS32 --command FileCheck %s \
-; RUN: --check-prefix=MIPS32
-
-define internal void @fcmpEq(float %a, float %b, double %c, double %d) {
-entry:
- %cmp = fcmp oeq float %a, %b
- br i1 %cmp, label %if.then, label %if.end
-
-if.then: ; preds = %entry
- call void @func()
- br label %if.end
-
-if.end: ; preds = %if.then, %entry
- %cmp1 = fcmp oeq double %c, %d
- br i1 %cmp1, label %if.then2, label %if.end3
-
-if.then2: ; preds = %if.end
- call void @func()
- br label %if.end3
-
-if.end3: ; preds = %if.then2, %if.end
- ret void
-}
-; CHECK-LABEL: fcmpEq
-; CHECK: ucomiss
-; CHECK-NEXT: jne
-; CHECK-NEXT: jp
-; CHECK-NEXT: call {{.*}} R_{{.*}} func
-; CHECK: ucomisd
-; CHECK-NEXT: jne
-; CHECK-NEXT: jp
-; CHECK: call {{.*}} R_{{.*}} func
-; CHECK-OM1-LABEL: fcmpEq
-; CHECK-OM1: ucomiss
-; CHECK-OM1: jne
-; CHECK-OM1-NEXT: jp
-; CHECK-OM1: call {{.*}} R_{{.*}} func
-; CHECK-OM1: ucomisd
-; CHECK-OM1: jne
-; CHECK-NEXT-OM1: jp
-; ARM32-LABEL: fcmpEq
-; ARM32: vcmp.f32
-; ARM32: vmrs
-; ARM32-OM1: mov [[R0:r[0-9]+]], #0
-; ARM32-OM1: moveq [[R0]], #1
-; ARM32-O2: bne
-; ARM32: bl{{.*}}func
-; ARM32: vcmp.f64
-; ARM32: vmrs
-; ARM32-OM1: mov [[R1:r[0-9]+]], #0
-; ARM32-OM1: moveq [[R1]], #1
-; ARM32-O2: bne
-; MIPS32-LABEL: fcmpEq
-; MIPS32-LABEL: .LfcmpEq$entry
-; MIPS32: c.eq.s
-; MIPS32: addiu [[REG:.*]], $zero, 1
-; MIPS32: movf [[REG]], $zero, {{.*}}
-; MIPS32-LABEL: .LfcmpEq$if.end
-; MIPS32: c.eq.d
-; MIPS32: addiu [[REG:.*]], $zero, 1
-; MIPS32: movf [[REG]], $zero, {{.*}}
-
-declare void @func()
-
-define internal void @fcmpNe(float %a, float %b, double %c, double %d) {
-entry:
- %cmp = fcmp une float %a, %b
- br i1 %cmp, label %if.then, label %if.end
-
-if.then: ; preds = %entry
- call void @func()
- br label %if.end
-
-if.end: ; preds = %if.then, %entry
- %cmp1 = fcmp une double %c, %d
- br i1 %cmp1, label %if.then2, label %if.end3
-
-if.then2: ; preds = %if.end
- call void @func()
- br label %if.end3
-
-if.end3: ; preds = %if.then2, %if.end
- ret void
-}
-; CHECK-LABEL: fcmpNe
-; CHECK: ucomiss
-; CHECK-NEXT: jne
-; CHECK-NEXT: jp
-; CHECK-NEXT: jmp
-; CHECK-NEXT: call {{.*}} R_{{.*}} func
-; CHECK: ucomisd
-; CHECK-NEXT: jne
-; CHECK-NEXT: jp
-; CHECK-NEXT: jmp
-; CHECK-NEXT: call {{.*}} R_{{.*}} func
-; CHECK-OM1-LABEL: fcmpNe
-; CHECK-OM1: ucomiss
-; CHECK-OM1: jne
-; CHECK-OM1: jp
-; CHECK-OM1: jmp
-; CHECK-OM1: call {{.*}} R_{{.*}} func
-; CHECK-OM1: ucomisd
-; CHECK-OM1: jne
-; CHECK-OM1: jp
-; CHECK-OM1: jmp
-; CHECK-OM1: call {{.*}} R_{{.*}} func
-; ARM32-LABEL: fcmpNe
-; ARM32: vcmp.f32
-; ARM32: vmrs
-; ARM32-OM1: mov [[R0:r[0-9]+]], #0
-; ARM32-OM1: movne [[R0]], #1
-; ARM32-O2: beq
-; ARM32: vcmp.f64
-; ARM32: vmrs
-; ARM32-OM1: mov [[R1:r[0-9]+]], #0
-; ARM32-OM1: movne [[R1]], #1
-; ARM32-O2: beq
-; MIPS32-LABEL: fcmpNe
-; MIPS32-LABEL: .LfcmpNe$entry
-; MIPS32: c.eq.s
-; MIPS32: addiu [[REG:.*]], $zero, 1
-; MIPS32: movt [[REG]], $zero, {{.*}}
-; MIPS32-LABEL: .LfcmpNe$if.end
-; MIPS32: c.eq.d
-; MIPS32: addiu [[REG:.*]], $zero, 1
-; MIPS32: movt [[REG]], $zero, {{.*}}
-
-define internal void @fcmpGt(float %a, float %b, double %c, double %d) {
-entry:
- %cmp = fcmp ogt float %a, %b
- br i1 %cmp, label %if.then, label %if.end
-
-if.then: ; preds = %entry
- call void @func()
- br label %if.end
-
-if.end: ; preds = %if.then, %entry
- %cmp1 = fcmp ogt double %c, %d
- br i1 %cmp1, label %if.then2, label %if.end3
-
-if.then2: ; preds = %if.end
- call void @func()
- br label %if.end3
-
-if.end3: ; preds = %if.then2, %if.end
- ret void
-}
-; CHECK-LABEL: fcmpGt
-; CHECK: ucomiss
-; CHECK-NEXT: jbe
-; CHECK-NEXT: call {{.*}} R_{{.*}} func
-; CHECK: ucomisd
-; CHECK-NEXT: jbe
-; CHECK-NEXT: call {{.*}} R_{{.*}} func
-; CHECK-OM1-LABEL: fcmpGt
-; CHECK-OM1: ucomiss
-; CHECK-OM1: seta
-; CHECK-OM1: call {{.*}} R_{{.*}} func
-; CHECK-OM1: ucomisd
-; CHECK-OM1: seta
-; CHECK-OM1: call {{.*}} R_{{.*}} func
-; ARM32-LABEL: fcmpGt
-; ARM32: vcmp.f32
-; ARM32: vmrs
-; ARM32-OM1: mov [[R0:r[0-9]+]], #0
-; ARM32-OM1: movgt [[R0]], #1
-; ARM32-O2: ble
-; ARM32: vcmp.f64
-; ARM32: vmrs
-; ARM32-OM1: mov [[R1:r[0-9]+]], #0
-; ARM32-OM1: movgt [[R1]], #1
-; ARM32-O2: ble
-; MIPS32-LABEL: fcmpGt
-; MIPS32-LABEL: .LfcmpGt$entry
-; MIPS32: c.ule.s
-; MIPS32: addiu [[REG:.*]], $zero, 1
-; MIPS32: movt [[REG]], $zero, {{.*}}
-; MIPS32-LABEL: .LfcmpGt$if.end
-; MIPS32: c.ule.d
-; MIPS32: addiu [[REG:.*]], $zero, 1
-; MIPS32: movt [[REG]], $zero, {{.*}}
-
-define internal void @fcmpGe(float %a, float %b, double %c, double %d) {
-entry:
- %cmp = fcmp ult float %a, %b
- br i1 %cmp, label %if.end, label %if.then
-
-if.then: ; preds = %entry
- call void @func()
- br label %if.end
-
-if.end: ; preds = %entry, %if.then
- %cmp1 = fcmp ult double %c, %d
- br i1 %cmp1, label %if.end3, label %if.then2
-
-if.then2: ; preds = %if.end
- call void @func()
- br label %if.end3
-
-if.end3: ; preds = %if.end, %if.then2
- ret void
-}
-; CHECK-LABEL: fcmpGe
-; CHECK: ucomiss
-; CHECK-NEXT: jb
-; CHECK-NEXT: call {{.*}} R_{{.*}} func
-; CHECK: ucomisd
-; CHECK-NEXT: jb
-; CHECK-NEXT: call {{.*}} R_{{.*}} func
-; CHECK-OM1-LABEL: fcmpGe
-; CHECK-OM1: ucomiss
-; CHECK-OM1-NEXT: setb
-; CHECK-OM1: call {{.*}} R_{{.*}} func
-; CHECK-OM1: ucomisd
-; CHECK-OM1-NEXT: setb
-; CHECK-OM1: call {{.*}} R_{{.*}} func
-; ARM32-LABEL: fcmpGe
-; ARM32: vcmp.f32
-; ARM32: vmrs
-; ARM32-OM1: mov [[R0:r[0-9]+]], #0
-; ARM32-OM1: movlt [[R0]], #1
-; ARM32-O2: blt
-; ARM32: vcmp.f64
-; ARM32: vmrs
-; ARM32-OM1: mov [[R1:r[0-9]+]], #0
-; ARM32-OM1: movlt [[R1]], #1
-; ARM32-O2: blt
-; MIPS32-LABEL: fcmpGe
-; MIPS32-LABEL: .LfcmpGe$entry
-; MIPS32: c.ult.s
-; MIPS32: addiu [[REG:.*]], $zero, 1
-; MIPS32: movf [[REG]], $zero, {{.*}}
-; MIPS32-LABEL: .LfcmpGe$if.end
-; MIPS32: c.ult.d
-; MIPS32: addiu [[REG:.*]], $zero, 1
-; MIPS32: movf [[REG]], $zero, {{.*}}
-
-define internal void @fcmpLt(float %a, float %b, double %c, double %d) {
-entry:
- %cmp = fcmp olt float %a, %b
- br i1 %cmp, label %if.then, label %if.end
-
-if.then: ; preds = %entry
- call void @func()
- br label %if.end
-
-if.end: ; preds = %if.then, %entry
- %cmp1 = fcmp olt double %c, %d
- br i1 %cmp1, label %if.then2, label %if.end3
-
-if.then2: ; preds = %if.end
- call void @func()
- br label %if.end3
-
-if.end3: ; preds = %if.then2, %if.end
- ret void
-}
-; CHECK-LABEL: fcmpLt
-; CHECK: ucomiss
-; CHECK-NEXT: jbe
-; CHECK-NEXT: call {{.*}} R_{{.*}} func
-; CHECK: ucomisd
-; CHECK-NEXT: jbe
-; CHECK-NEXT: call {{.*}} R_{{.*}} func
-; CHECK-OM1-LABEL: fcmpLt
-; CHECK-OM1: ucomiss
-; CHECK-OM1-NEXT: seta
-; CHECK-OM1: call {{.*}} R_{{.*}} func
-; CHECK-OM1: ucomisd
-; CHECK-OM1-NEXT: seta
-; CHECK-OM1: call {{.*}} R_{{.*}} func
-; ARM32-LABEL: fcmpLt
-; ARM32: vcmp.f32
-; ARM32: vmrs
-; ARM32-OM1: mov [[R0:r[0-9]+]], #0
-; ARM32-OM1: movmi [[R0]], #1
-; ARM32-O2: bpl
-; ARM32: vcmp.f64
-; ARM32: vmrs
-; ARM32-OM1: mov [[R1:r[0-9]+]], #0
-; ARM32-OM1: movmi [[R1]], #1
-; ARM32-O2: bpl
-; MIPS32-LABEL: fcmpLt
-; MIPS32-LABEL: .LfcmpLt$entry
-; MIPS32: c.olt.s
-; MIPS32: addiu [[REG:.*]], $zero, 1
-; MIPS32: movf [[REG]], $zero, {{.*}}
-; MIPS32-LABEL: .LfcmpLt$if.end
-; MIPS32: c.olt.d
-; MIPS32: addiu [[REG:.*]], $zero, 1
-; MIPS32: movf [[REG]], $zero, {{.*}}
-
-define internal void @fcmpLe(float %a, float %b, double %c, double %d) {
-entry:
- %cmp = fcmp ugt float %a, %b
- br i1 %cmp, label %if.end, label %if.then
-
-if.then: ; preds = %entry
- call void @func()
- br label %if.end
-
-if.end: ; preds = %entry, %if.then
- %cmp1 = fcmp ugt double %c, %d
- br i1 %cmp1, label %if.end3, label %if.then2
-
-if.then2: ; preds = %if.end
- call void @func()
- br label %if.end3
-
-if.end3: ; preds = %if.end, %if.then2
- ret void
-}
-; CHECK-LABEL: fcmpLe
-; CHECK: ucomiss
-; CHECK-NEXT: jb
-; CHECK-NEXT: call {{.*}} R_{{.*}} func
-; CHECK: ucomisd
-; CHECK-NEXT: jb
-; CHECK-NEXT: call {{.*}} R_{{.*}} func
-; CHECK-OM1-LABEL: fcmpLe
-; CHECK-OM1: ucomiss
-; CHECK-OM1-NEXT: setb
-; CHECK-OM1: call {{.*}} R_{{.*}} func
-; CHECK-OM1: ucomisd
-; CHECK-OM1-NEXT: setb
-; CHECK-OM1: call {{.*}} R_{{.*}} func
-; ARM32-LABEL: fcmpLe
-; ARM32: vcmp.f32
-; ARM32: vmrs
-; ARM32-OM1: mov [[R0:r[0-9]+]], #0
-; ARM32-OM1: movhi [[R0]], #1
-; ARM32-O2: bhi
-; ARM32: vcmp.f64
-; ARM32: vmrs
-; ARM32-OM1: mov [[R1:r[0-9]+]], #0
-; ARM32-OM1: movhi [[R1]], #1
-; ARM32-O2: bhi
-; MIPS32-LABEL: fcmpLe
-; MIPS32-LABEL: .LfcmpLe$entry
-; MIPS32: c.ole.s
-; MIPS32: addiu [[REG:.*]], $zero, 1
-; MIPS32: movt [[REG]], $zero, {{.*}}
-; MIPS32-LABEL: .LfcmpLe$if.end
-; MIPS32: c.ole.d
-; MIPS32: addiu [[REG:.*]], $zero, 1
-; MIPS32: movt [[REG]], $zero, {{.*}}
-
-define internal i32 @fcmpFalseFloat(float %a, float %b) {
-entry:
- %cmp = fcmp false float %a, %b
- %cmp.ret_ext = zext i1 %cmp to i32
- ret i32 %cmp.ret_ext
-}
-; CHECK-LABEL: fcmpFalseFloat
-; CHECK: mov {{.*}},0x0
-; ARM32-LABEL: fcmpFalseFloat
-; ARM32: mov [[R:r[0-9]+]], #0
-; MIPS32-LABEL: fcmpFalseFloat
-; MIPS32: addiu [[R:.*]], $zero, 0
-; MIPS32: andi [[R]], [[R]], 1
-
-define internal i32 @fcmpFalseDouble(double %a, double %b) {
-entry:
- %cmp = fcmp false double %a, %b
- %cmp.ret_ext = zext i1 %cmp to i32
- ret i32 %cmp.ret_ext
-}
-; CHECK-LABEL: fcmpFalseDouble
-; CHECK: mov {{.*}},0x0
-; ARM32-LABEL: fcmpFalseDouble
-; ARM32: mov [[R:r[0-9]+]], #0
-; MIPS32-LABEL: fcmpFalseDouble
-; MIPS32: addiu [[R:.*]], $zero, 0
-; MIPS32: andi [[R]], [[R]], 1
-
-define internal i32 @fcmpOeqFloat(float %a, float %b) {
-entry:
- %cmp = fcmp oeq float %a, %b
- %cmp.ret_ext = zext i1 %cmp to i32
- ret i32 %cmp.ret_ext
-}
-; CHECK-LABEL: fcmpOeqFloat
-; CHECK: ucomiss
-; CHECK: jne
-; CHECK: jp
-; ARM32-LABEL: fcmpOeqFloat
-; ARM32-O2: mov [[R:r[0-9]+]], #0
-; ARM32: vcmp.f32
-; ARM32: vmrs
-; ARM32-OM1: mov [[R:r[0-9]+]], #0
-; ARM32: moveq [[R]], #1
-; MIPS32-LABEL: fcmpOeqFloat
-; MIPS32: c.eq.s
-; MIPS32: addiu [[REG:.*]], $zero, 1
-; MIPS32: movf [[REG]], $zero, {{.*}}
-
-define internal i32 @fcmpOeqDouble(double %a, double %b) {
-entry:
- %cmp = fcmp oeq double %a, %b
- %cmp.ret_ext = zext i1 %cmp to i32
- ret i32 %cmp.ret_ext
-}
-; CHECK-LABEL: fcmpOeqDouble
-; CHECK: ucomisd
-; CHECK: jne
-; CHECK: jp
-; ARM32-LABEL: fcmpOeqDouble
-; ARM32-O2: mov [[R:r[0-9]+]], #0
-; ARM32: vcmp.f64
-; ARM32: vmrs
-; ARM32-OM1: mov [[R:r[0-9]+]], #0
-; ARM32: moveq [[R]], #1
-; MIPS32-LABEL: fcmpOeqDouble
-; MIPS32: c.eq.d
-; MIPS32: addiu [[REG:.*]], $zero, 1
-; MIPS32: movf [[REG]], $zero, {{.*}}
-
-define internal i32 @fcmpOgtFloat(float %a, float %b) {
-entry:
- %cmp = fcmp ogt float %a, %b
- %cmp.ret_ext = zext i1 %cmp to i32
- ret i32 %cmp.ret_ext
-}
-; CHECK-LABEL: fcmpOgtFloat
-; CHECK: ucomiss
-; CHECK: seta
-; ARM32-LABEL: fcmpOgtFloat
-; ARM32-O2: mov [[R:r[0-9]+]], #0
-; ARM32: vcmp.f32
-; ARM32: vmrs
-; ARM32-OM1: mov [[R:r[0-9]+]], #0
-; ARM32: movgt [[R]], #1
-; MIPS32-LABEL: fcmpOgtFloat
-; MIPS32: c.ule.s
-; MIPS32: addiu [[REG:.*]], $zero, 1
-; MIPS32: movt [[REG]], $zero, {{.*}}
-
-define internal i32 @fcmpOgtDouble(double %a, double %b) {
-entry:
- %cmp = fcmp ogt double %a, %b
- %cmp.ret_ext = zext i1 %cmp to i32
- ret i32 %cmp.ret_ext
-}
-; CHECK-LABEL: fcmpOgtDouble
-; CHECK: ucomisd
-; CHECK: seta
-; ARM32-LABEL: fcmpOgtDouble
-; ARM32-O2: mov [[R:r[0-9]+]], #0
-; ARM32: vcmp.f64
-; ARM32: vmrs
-; ARM32-OM1: mov [[R:r[0-9]+]], #0
-; ARM32: movgt [[R]], #1
-; MIPS32-LABEL: fcmpOgtDouble
-; MIPS32: c.ule.d
-; MIPS32: addiu [[REG:.*]], $zero, 1
-; MIPS32: movt [[REG]], $zero, {{.*}}
-
-define internal i32 @fcmpOgeFloat(float %a, float %b) {
-entry:
- %cmp = fcmp oge float %a, %b
- %cmp.ret_ext = zext i1 %cmp to i32
- ret i32 %cmp.ret_ext
-}
-; CHECK-LABEL: fcmpOgeFloat
-; CHECK: ucomiss
-; CHECK: setae
-; ARM32-LABEL: fcmpOgeFloat
-; ARM32-O2: mov [[R:r[0-9]+]], #0
-; ARM32: vcmp.f32
-; ARM32: vmrs
-; ARM32-OM1: mov [[R:r[0-9]+]], #0
-; ARM32: movge [[R]], #1
-; MIPS32-LABEL: fcmpOgeFloat
-; MIPS32: c.ult.s
-; MIPS32: addiu [[REG:.*]], $zero, 1
-; MIPS32: movt [[REG]], $zero, {{.*}}
-
-define internal i32 @fcmpOgeDouble(double %a, double %b) {
-entry:
- %cmp = fcmp oge double %a, %b
- %cmp.ret_ext = zext i1 %cmp to i32
- ret i32 %cmp.ret_ext
-}
-; CHECK-LABEL: fcmpOgeDouble
-; CHECK: ucomisd
-; CHECK: setae
-; ARM32-LABEL: fcmpOgeDouble
-; ARM32-O2: mov [[R:r[0-9]+]], #0
-; ARM32: vcmp.f64
-; ARM32: vmrs
-; ARM32-OM1: mov [[R:r[0-9]+]], #0
-; ARM32: movge [[R]], #1
-; MIPS32-LABEL: fcmpOgeDouble
-; MIPS32: c.ult.d
-; MIPS32: addiu [[REG:.*]], $zero, 1
-; MIPS32: movt [[REG]], $zero, {{.*}}
-
-define internal i32 @fcmpOltFloat(float %a, float %b) {
-entry:
- %cmp = fcmp olt float %a, %b
- %cmp.ret_ext = zext i1 %cmp to i32
- ret i32 %cmp.ret_ext
-}
-; CHECK-LABEL: fcmpOltFloat
-; CHECK: ucomiss
-; CHECK: seta
-; ARM32-LABEL: fcmpOltFloat
-; ARM32-O2: mov [[R:r[0-9]+]], #0
-; ARM32: vcmp.f32
-; ARM32: vmrs
-; ARM32-OM1: mov [[R:r[0-9]+]], #0
-; ARM32: movmi [[R]], #1
-; MIPS32-LABEL: fcmpOltFloat
-; MIPS32: c.olt.s
-; MIPS32: addiu [[REG:.*]], $zero, 1
-; MIPS32: movf [[REG]], $zero, {{.*}}
-
-define internal i32 @fcmpOltDouble(double %a, double %b) {
-entry:
- %cmp = fcmp olt double %a, %b
- %cmp.ret_ext = zext i1 %cmp to i32
- ret i32 %cmp.ret_ext
-}
-; CHECK-LABEL: fcmpOltDouble
-; CHECK: ucomisd
-; CHECK: seta
-; ARM32-LABEL: fcmpOltDouble
-; ARM32-O2: mov [[R:r[0-9]+]], #0
-; ARM32: vcmp.f64
-; ARM32: vmrs
-; ARM32-OM1: mov [[R:r[0-9]+]], #0
-; ARM32: movmi [[R]], #1
-; MIPS32-LABEL: fcmpOltDouble
-; MIPS32: c.olt.d
-; MIPS32: addiu [[REG:.*]], $zero, 1
-; MIPS32: movf [[REG]], $zero, {{.*}}
-
-define internal i32 @fcmpOleFloat(float %a, float %b) {
-entry:
- %cmp = fcmp ole float %a, %b
- %cmp.ret_ext = zext i1 %cmp to i32
- ret i32 %cmp.ret_ext
-}
-; CHECK-LABEL: fcmpOleFloat
-; CHECK: ucomiss
-; CHECK: setae
-; ARM32-LABEL: fcmpOleFloat
-; ARM32-O2: mov [[R:r[0-9]+]], #0
-; ARM32: vcmp.f32
-; ARM32: vmrs
-; ARM32-OM1: mov [[R:r[0-9]+]], #0
-; ARM32: movls [[R]], #1
-; MIPS32-LABEL: fcmpOleFloat
-; MIPS32: c.ole.s
-; MIPS32: addiu [[REG:.*]], $zero, 1
-; MIPS32: movf [[REG]], $zero, {{.*}}
-
-define internal i32 @fcmpOleDouble(double %a, double %b) {
-entry:
- %cmp = fcmp ole double %a, %b
- %cmp.ret_ext = zext i1 %cmp to i32
- ret i32 %cmp.ret_ext
-}
-; CHECK-LABEL: fcmpOleDouble
-; CHECK: ucomisd
-; CHECK: setae
-; ARM32-LABEL: fcmpOleDouble
-; ARM32-O2: mov [[R:r[0-9]+]], #0
-; ARM32: vcmp.f64
-; ARM32: vmrs
-; ARM32-OM1: mov [[R:r[0-9]+]], #0
-; ARM32: movls [[R]], #1
-; MIPS32-LABEL: fcmpOleDouble
-; MIPS32: c.ole.d
-; MIPS32: addiu [[REG:.*]], $zero, 1
-; MIPS32: movf [[REG]], $zero, {{.*}}
-
-define internal i32 @fcmpOneFloat(float %a, float %b) {
-entry:
- %cmp = fcmp one float %a, %b
- %cmp.ret_ext = zext i1 %cmp to i32
- ret i32 %cmp.ret_ext
-}
-; CHECK-LABEL: fcmpOneFloat
-; CHECK: ucomiss
-; CHECK: setne
-; ARM32-LABEL: fcmpOneFloat
-; ARM32-O2: mov [[R:r[0-9]+]], #0
-; ARM32: vcmp.f32
-; ARM32: vmrs
-; ARM32-OM1: mov [[R:r[0-9]+]], #0
-; ARM32: movmi [[R]], #1
-; ARM32: movgt [[R]], #1
-; MIPS32-LABEL: fcmpOneFloat
-; MIPS32: c.ueq.s
-; MIPS32: addiu [[REG:.*]], $zero, 1
-; MIPS32: movt [[REG]], $zero, {{.*}}
-
-define internal i32 @fcmpOneDouble(double %a, double %b) {
-entry:
- %cmp = fcmp one double %a, %b
- %cmp.ret_ext = zext i1 %cmp to i32
- ret i32 %cmp.ret_ext
-}
-; CHECK-LABEL: fcmpOneDouble
-; CHECK: ucomisd
-; CHECK: setne
-; ARM32-LABEL: fcmpOneDouble
-; ARM32-O2: mov [[R:r[0-9]+]], #0
-; ARM32: vcmp.f64
-; ARM32: vmrs
-; ARM32-OM1: mov [[R:r[0-9]+]], #0
-; ARM32: movmi [[R]], #1
-; ARM32: movgt [[R]], #1
-; MIPS32-LABEL: fcmpOneDouble
-; MIPS32: c.ueq.d
-; MIPS32: addiu [[REG:.*]], $zero, 1
-; MIPS32: movt [[REG]], $zero, {{.*}}
-
-define internal i32 @fcmpOrdFloat(float %a, float %b) {
-entry:
- %cmp = fcmp ord float %a, %b
- %cmp.ret_ext = zext i1 %cmp to i32
- ret i32 %cmp.ret_ext
-}
-; CHECK-LABEL: fcmpOrdFloat
-; CHECK: ucomiss
-; CHECK: setnp
-; ARM32-LABEL: fcmpOrdFloat
-; ARM32-O2: mov [[R:r[0-9]+]], #0
-; ARM32: vcmp.f32
-; ARM32: vmrs
-; ARM32-OM1: mov [[R:r[0-9]+]], #0
-; ARM32: movvc [[R]], #1
-; MIPS32-LABEL: fcmpOrdFloat
-; MIPS32: c.un.s
-; MIPS32: addiu [[REG:.*]], $zero, 1
-; MIPS32: movt [[REG]], $zero, {{.*}}
-
-define internal i32 @fcmpOrdDouble(double %a, double %b) {
-entry:
- %cmp = fcmp ord double %a, %b
- %cmp.ret_ext = zext i1 %cmp to i32
- ret i32 %cmp.ret_ext
-}
-; CHECK-LABEL: fcmpOrdDouble
-; CHECK: ucomisd
-; CHECK: setnp
-; ARM32-LABEL: fcmpOrdDouble
-; ARM32-O2: mov [[R:r[0-9]+]], #0
-; ARM32: vcmp.f64
-; ARM32: vmrs
-; ARM32-OM1: mov [[R:r[0-9]+]], #0
-; ARM32: movvc [[R]], #1
-; MIPS32-LABEL: fcmpOrdDouble
-; MIPS32: c.un.d
-; MIPS32: addiu [[REG:.*]], $zero, 1
-; MIPS32: movt [[REG]], $zero, {{.*}}
-
-define internal i32 @fcmpUeqFloat(float %a, float %b) {
-entry:
- %cmp = fcmp ueq float %a, %b
- %cmp.ret_ext = zext i1 %cmp to i32
- ret i32 %cmp.ret_ext
-}
-; CHECK-LABEL: fcmpUeqFloat
-; CHECK: ucomiss
-; CHECK: sete
-; ARM32-LABEL: fcmpUeqFloat
-; ARM32-O2: mov [[R:r[0-9]+]], #0
-; ARM32: vcmp.f32
-; ARM32: vmrs
-; ARM32-OM1: mov [[R:r[0-9]+]], #0
-; ARM32: moveq [[R]], #1
-; ARM32: movvs [[R]], #1
-; MIPS32-LABEL: fcmpUeqFloat
-; MIPS32: c.ueq.s
-; MIPS32: addiu [[REG:.*]], $zero, 1
-; MIPS32: movf [[REG]], $zero, {{.*}}
-
-define internal i32 @fcmpUeqDouble(double %a, double %b) {
-entry:
- %cmp = fcmp ueq double %a, %b
- %cmp.ret_ext = zext i1 %cmp to i32
- ret i32 %cmp.ret_ext
-}
-; CHECK-LABEL: fcmpUeqDouble
-; CHECK: ucomisd
-; CHECK: sete
-; ARM32-LABEL: fcmpUeqDouble
-; ARM32-O2: mov [[R:r[0-9]+]], #0
-; ARM32: vcmp.f64
-; ARM32: vmrs
-; ARM32-OM1: mov [[R:r[0-9]+]], #0
-; ARM32: moveq [[R]], #1
-; ARM32: movvs [[R]], #1
-; MIPS32-LABEL: fcmpUeqDouble
-; MIPS32: c.ueq.d
-; MIPS32: addiu [[REG:.*]], $zero, 1
-; MIPS32: movf [[REG]], $zero, {{.*}}
-
-define internal i32 @fcmpUgtFloat(float %a, float %b) {
-entry:
- %cmp = fcmp ugt float %a, %b
- %cmp.ret_ext = zext i1 %cmp to i32
- ret i32 %cmp.ret_ext
-}
-; CHECK-LABEL: fcmpUgtFloat
-; CHECK: ucomiss
-; CHECK: setb
-; ARM32-LABEL: fcmpUgtFloat
-; ARM32-O2: mov [[R:r[0-9]+]], #0
-; ARM32: vcmp.f32
-; ARM32: vmrs
-; ARM32-OM1: mov [[R:r[0-9]+]], #0
-; ARM32: movhi [[R]], #1
-; MIPS32-LABEL: fcmpUgtFloat
-; MIPS32: c.ole.s
-; MIPS32: addiu [[REG:.*]], $zero, 1
-; MIPS32: movt [[REG]], $zero, {{.*}}
-
-define internal i32 @fcmpUgtDouble(double %a, double %b) {
-entry:
- %cmp = fcmp ugt double %a, %b
- %cmp.ret_ext = zext i1 %cmp to i32
- ret i32 %cmp.ret_ext
-}
-; CHECK-LABEL: fcmpUgtDouble
-; CHECK: ucomisd
-; CHECK: setb
-; ARM32-LABEL: fcmpUgtDouble
-; ARM32-O2: mov [[R:r[0-9]+]], #0
-; ARM32: vcmp.f64
-; ARM32: vmrs
-; ARM32-OM1: mov [[R:r[0-9]+]], #0
-; ARM32: movhi [[R]], #1
-; MIPS32-LABEL: fcmpUgtDouble
-; MIPS32: c.ole.d
-; MIPS32: addiu [[REG:.*]], $zero, 1
-; MIPS32: movt [[REG]], $zero, {{.*}}
-
-define internal i32 @fcmpUgeFloat(float %a, float %b) {
-entry:
- %cmp = fcmp uge float %a, %b
- %cmp.ret_ext = zext i1 %cmp to i32
- ret i32 %cmp.ret_ext
-}
-; CHECK-LABEL: fcmpUgeFloat
-; CHECK: ucomiss
-; CHECK: setbe
-; ARM32-LABEL: fcmpUgeFloat
-; ARM32-O2: mov [[R:r[0-9]+]], #0
-; ARM32: vcmp.f32
-; ARM32: vmrs
-; ARM32-OM1: mov [[R:r[0-9]+]], #0
-; ARM32: movpl [[R]], #1
-; MIPS32-LABEL: fcmpUgeFloat
-; MIPS32: c.olt.s
-; MIPS32: addiu [[REG:.*]], $zero, 1
-; MIPS32: movt [[REG]], $zero, {{.*}}
-
-define internal i32 @fcmpUgeDouble(double %a, double %b) {
-entry:
- %cmp = fcmp uge double %a, %b
- %cmp.ret_ext = zext i1 %cmp to i32
- ret i32 %cmp.ret_ext
-}
-; CHECK-LABEL: fcmpUgeDouble
-; CHECK: ucomisd
-; CHECK: setbe
-; ARM32-LABEL: fcmpUgeDouble
-; ARM32-O2: mov [[R:r[0-9]+]], #0
-; ARM32: vcmp.f64
-; ARM32: vmrs
-; ARM32-OM1: mov [[R:r[0-9]+]], #0
-; ARM32: movpl [[R]], #1
-; MIPS32-LABEL: fcmpUgeDouble
-; MIPS32: c.olt.d
-; MIPS32: addiu [[REG:.*]], $zero, 1
-; MIPS32: movt [[REG]], $zero, {{.*}}
-
-define internal i32 @fcmpUltFloat(float %a, float %b) {
-entry:
- %cmp = fcmp ult float %a, %b
- %cmp.ret_ext = zext i1 %cmp to i32
- ret i32 %cmp.ret_ext
-}
-; CHECK-LABEL: fcmpUltFloat
-; CHECK: ucomiss
-; CHECK: setb
-; ARM32-LABEL: fcmpUltFloat
-; ARM32-O2: mov [[R:r[0-9]+]], #0
-; ARM32: vcmp.f32
-; ARM32: vmrs
-; ARM32-OM1: mov [[R:r[0-9]+]], #0
-; ARM32: movlt [[R]], #1
-; MIPS32-LABEL: fcmpUltFloat
-; MIPS32: c.ult.s
-; MIPS32: addiu [[REG:.*]], $zero, 1
-; MIPS32: movf [[REG]], $zero, {{.*}}
-
-define internal i32 @fcmpUltDouble(double %a, double %b) {
-entry:
- %cmp = fcmp ult double %a, %b
- %cmp.ret_ext = zext i1 %cmp to i32
- ret i32 %cmp.ret_ext
-}
-; CHECK-LABEL: fcmpUltDouble
-; CHECK: ucomisd
-; CHECK: setb
-; ARM32-LABEL: fcmpUltDouble
-; ARM32-O2: mov [[R:r[0-9]+]], #0
-; ARM32: vcmp.f64
-; ARM32: vmrs
-; ARM32-OM1: mov [[R:r[0-9]+]], #0
-; ARM32: movlt [[R]], #1
-; MIPS32-LABEL: fcmpUltDouble
-; MIPS32: c.ult.d
-; MIPS32: addiu [[REG:.*]], $zero, 1
-; MIPS32: movf [[REG]], $zero, {{.*}}
-
-define internal i32 @fcmpUleFloat(float %a, float %b) {
-entry:
- %cmp = fcmp ule float %a, %b
- %cmp.ret_ext = zext i1 %cmp to i32
- ret i32 %cmp.ret_ext
-}
-; CHECK-LABEL: fcmpUleFloat
-; CHECK: ucomiss
-; CHECK: setbe
-; ARM32-LABEL: fcmpUleFloat
-; ARM32-O2: mov [[R:r[0-9]+]], #0
-; ARM32: vcmp.f32
-; ARM32: vmrs
-; ARM32-OM1: mov [[R:r[0-9]+]], #0
-; ARM32: movle [[R]], #1
-; MIPS32-LABEL: fcmpUleFloat
-; MIPS32: c.ule.s
-; MIPS32: addiu [[REG:.*]], $zero, 1
-; MIPS32: movf [[REG]], $zero, {{.*}}
-
-define internal i32 @fcmpUleDouble(double %a, double %b) {
-entry:
- %cmp = fcmp ule double %a, %b
- %cmp.ret_ext = zext i1 %cmp to i32
- ret i32 %cmp.ret_ext
-}
-; CHECK-LABEL: fcmpUleDouble
-; CHECK: ucomisd
-; CHECK: setbe
-; ARM32-LABEL: fcmpUleDouble
-; ARM32-O2: mov [[R:r[0-9]+]], #0
-; ARM32: vcmp.f64
-; ARM32: vmrs
-; ARM32-OM1: mov [[R:r[0-9]+]], #0
-; ARM32: movle [[R]], #1
-; MIPS32-LABEL: fcmpUleDouble
-; MIPS32: c.ule.d
-; MIPS32: addiu [[REG:.*]], $zero, 1
-; MIPS32: movf [[REG]], $zero, {{.*}}
-
-define internal i32 @fcmpUneFloat(float %a, float %b) {
-entry:
- %cmp = fcmp une float %a, %b
- %cmp.ret_ext = zext i1 %cmp to i32
- ret i32 %cmp.ret_ext
-}
-; CHECK-LABEL: fcmpUneFloat
-; CHECK: ucomiss
-; CHECK: jne
-; CHECK: jp
-; ARM32-LABEL: fcmpUneFloat
-; ARM32-O2: mov [[R:r[0-9]+]], #0
-; ARM32: vcmp.f32
-; ARM32: vmrs
-; ARM32-OM1: mov [[R:r[0-9]+]], #0
-; ARM32: movne [[R]], #1
-; MIPS32-LABEL: fcmpUneFloat
-; MIPS32: c.eq.s
-; MIPS32: addiu [[REG:.*]], $zero, 1
-; MIPS32: movt [[REG]], $zero, {{.*}}
-
-define internal i32 @fcmpUneDouble(double %a, double %b) {
-entry:
- %cmp = fcmp une double %a, %b
- %cmp.ret_ext = zext i1 %cmp to i32
- ret i32 %cmp.ret_ext
-}
-; CHECK-LABEL: fcmpUneDouble
-; CHECK: ucomisd
-; CHECK: jne
-; CHECK: jp
-; ARM32-LABEL: fcmpUneDouble
-; ARM32-O2: mov [[R:r[0-9]+]], #0
-; ARM32: vcmp.f64
-; ARM32: vmrs
-; ARM32-OM1: mov [[R:r[0-9]+]], #0
-; ARM32: movne [[R]], #1
-; MIPS32-LABEL: fcmpUneDouble
-; MIPS32: c.eq.d
-; MIPS32: addiu [[REG:.*]], $zero, 1
-; MIPS32: movt [[REG]], $zero, {{.*}}
-
-define internal i32 @fcmpUnoFloat(float %a, float %b) {
-entry:
- %cmp = fcmp uno float %a, %b
- %cmp.ret_ext = zext i1 %cmp to i32
- ret i32 %cmp.ret_ext
-}
-; CHECK-LABEL: fcmpUnoFloat
-; CHECK: ucomiss
-; CHECK: setp
-; ARM32-LABEL: fcmpUnoFloat
-; ARM32-O2: mov [[R:r[0-9]+]], #0
-; ARM32: vcmp.f32
-; ARM32: vmrs
-; ARM32-OM1: mov [[R:r[0-9]+]], #0
-; ARM32: movvs [[R]], #1
-; MIPS32-LABEL: fcmpUnoFloat
-; MIPS32: c.un.s
-; MIPS32: addiu [[REG:.*]], $zero, 1
-; MIPS32: movf [[REG]], $zero, {{.*}}
-
-define internal i32 @fcmpUnoDouble(double %a, double %b) {
-entry:
- %cmp = fcmp uno double %a, %b
- %cmp.ret_ext = zext i1 %cmp to i32
- ret i32 %cmp.ret_ext
-}
-; CHECK-LABEL: fcmpUnoDouble
-; CHECK: ucomisd
-; CHECK: setp
-; ARM32-LABEL: fcmpUnoDouble
-; ARM32-O2: mov [[R:r[0-9]+]], #0
-; ARM32: vcmp.f64
-; ARM32: vmrs
-; ARM32-OM1: mov [[R:r[0-9]+]], #0
-; ARM32: movvs [[R]], #1
-; MIPS32-LABEL: fcmpUnoDouble
-; MIPS32: c.un.d
-; MIPS32: addiu [[REG:.*]], $zero, 1
-; MIPS32: movf [[REG]], $zero, {{.*}}
-
-define internal i32 @fcmpTrueFloat(float %a, float %b) {
-entry:
- %cmp = fcmp true float %a, %b
- %cmp.ret_ext = zext i1 %cmp to i32
- ret i32 %cmp.ret_ext
-}
-; CHECK-LABEL: fcmpTrueFloat
-; CHECK: mov {{.*}},0x1
-; ARM32-LABEL: fcmpTrueFloat
-; ARM32: mov {{r[0-9]+}}, #1
-; MIPS32-LABEL: fcmpTrueFloat
-; MIPS32: addiu [[R:.*]], $zero, 1
-; MIPS32: andi [[R]], [[R]], 1
-
-define internal i32 @fcmpTrueDouble(double %a, double %b) {
-entry:
- %cmp = fcmp true double %a, %b
- %cmp.ret_ext = zext i1 %cmp to i32
- ret i32 %cmp.ret_ext
-}
-; CHECK-LABEL: fcmpTrueDouble
-; CHECK: mov {{.*}},0x1
-; ARM32-LABEL: fcmpTrueDouble
-; ARM32: mov {{r[0-9]+}}, #1
-; MIPS32-LABEL: fcmpTrueDouble
-; MIPS32: addiu [[R:.*]], $zero, 1
-; MIPS32: andi [[R]], [[R]], 1
-
-define internal float @selectFloatVarVar(float %a, float %b) {
-entry:
- %cmp = fcmp olt float %a, %b
- %cond = select i1 %cmp, float %a, float %b
- ret float %cond
-}
-; CHECK-LABEL: selectFloatVarVar
-; CHECK: movss
-; CHECK: minss
-; ARM32-LABEL: selectFloatVarVar
-; ARM32: vcmp.f32
-; ARM32-OM1: vmovne.f32 s{{[0-9]+}}
-; ARM32-O2: vmovmi.f32 s{{[0-9]+}}
-; ARM32: bx
-; MIPS32-LABEL: selectFloatVarVar
-; MIPS32: movn.s {{.*}}
-
-define internal double @selectDoubleVarVar(double %a, double %b) {
-entry:
- %cmp = fcmp olt double %a, %b
- %cond = select i1 %cmp, double %a, double %b
- ret double %cond
-}
-; CHECK-LABEL: selectDoubleVarVar
-; CHECK: movsd
-; CHECK: minsd
-; ARM32-LABEL: selectDoubleVarVar
-; ARM32: vcmp.f64
-; ARM32-OM1: vmovne.f64 d{{[0-9]+}}
-; ARM32-O2: vmovmi.f64 d{{[0-9]+}}
-; ARM32: bx
-; MIPS32-LABEL: selectDoubleVarVar
-; MIPS32: movn.d {{.*}}
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/fp.convert.ll b/third_party/subzero/tests_lit/llvm2ice_tests/fp.convert.ll
deleted file mode 100644
index 5c416a7..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/fp.convert.ll
+++ /dev/null
@@ -1,797 +0,0 @@
-; This tries to be a comprehensive test of f32 and f64 convert operations.
-; The CHECK lines are only checking for basic instruction patterns
-; that should be present regardless of the optimization level, so
-; there are no special OPTM1 match lines.
-
-; RUN: %p2i --filetype=obj --disassemble -i %s --args -O2 | FileCheck %s
-; RUN: %p2i --filetype=obj --disassemble -i %s --args -Om1 | FileCheck %s
-
-; RUN: %if --need=target_ARM32 --command %p2i --filetype=obj --disassemble \
-; RUN: --target arm32 -i %s --args -O2 \
-; RUN: | %if --need=target_ARM32 --command FileCheck %s \
-; RUN: --check-prefix=ARM32
-
-; RUN: %if --need=target_ARM32 --command %p2i --filetype=obj --disassemble \
-; RUN: --target arm32 -i %s --args -Om1 \
-; RUN: | %if --need=target_ARM32 --command FileCheck %s \
-; RUN: --check-prefix=ARM32
-
-; RUN: %if --need=allow_dump --need=target_MIPS32 --command %p2i \
-; RUN: --filetype=asm --target mips32 -i %s --args -Om1 \
-; RUN: | %if --need=allow_dump --need=target_MIPS32 --command FileCheck %s \
-; RUN: --check-prefix=MIPS32
-
-; RUN: %if --need=allow_dump --need=target_MIPS32 --command %p2i \
-; RUN: --filetype=asm --target mips32 -i %s --args -O2 \
-; RUN: | %if --need=allow_dump --need=target_MIPS32 --command FileCheck %s \
-; RUN: --check-prefix=MIPS32O2
-
-define internal float @fptrunc(double %a) {
-entry:
- %conv = fptrunc double %a to float
- ret float %conv
-}
-; CHECK-LABEL: fptrunc
-; CHECK: cvtsd2ss
-; CHECK: fld
-; ARM32-LABEL: fptrunc
-; ARM32: vcvt.f32.f64 {{s[0-9]+}}, {{d[0-9]+}}
-; MIPS32-LABEL: fptrunc
-; MIPS32: cvt.s.d
-; MIPS32O2-LABEL: fptrunc
-; MIPS32O2: cvt.s.d
-
-define internal double @fpext(float %a) {
-entry:
- %conv = fpext float %a to double
- ret double %conv
-}
-; CHECK-LABEL: fpext
-; CHECK: cvtss2sd
-; CHECK: fld
-; ARM32-LABEL: fpext
-; ARM32: vcvt.f64.f32 {{d[0-9]+}}, {{s[0-9]+}}
-; MIPS32-LABEL: fpext
-; MIPS32: cvt.d.s
-; MIPS32O2-LABEL: fpext
-; MIPS32O2: cvt.d.s
-
-define internal i64 @doubleToSigned64(double %a) {
-entry:
- %conv = fptosi double %a to i64
- ret i64 %conv
-}
-; CHECK-LABEL: doubleToSigned64
-; CHECK: call {{.*}} R_{{.*}} __Sz_fptosi_f64_i64
-; ARM32-LABEL: doubleToSigned64
-; TODO(jpp): implement this test.
-; MIPS32-LABEL: doubleToSigned64
-; MIPS32: jal __Sz_fptosi_f64_i64
-; MIPS32O2-LABEL: doubleToSigned64
-; MIPS32O2: jal __Sz_fptosi_f64_i64
-
-define internal i64 @floatToSigned64(float %a) {
-entry:
- %conv = fptosi float %a to i64
- ret i64 %conv
-}
-; CHECK-LABEL: floatToSigned64
-; CHECK: call {{.*}} R_{{.*}} __Sz_fptosi_f32_i64
-; ARM32-LABEL: floatToSigned64
-; TODO(jpp): implement this test.
-; MIPS32-LABEL: floatToSigned64
-; MIPS32: jal __Sz_fptosi_f32_i64
-; MIPS32O2-LABEL: floatToSigned64
-; MIPS32O2: jal __Sz_fptosi_f32_i64
-
-define internal i64 @doubleToUnsigned64(double %a) {
-entry:
- %conv = fptoui double %a to i64
- ret i64 %conv
-}
-; CHECK-LABEL: doubleToUnsigned64
-; CHECK: call {{.*}} R_{{.*}} __Sz_fptoui_f64_i64
-; ARM32-LABEL: doubleToUnsigned64
-; TODO(jpp): implement this test.
-; MIPS32-LABEL: doubleToUnsigned64
-; MIPS32: jal __Sz_fptoui_f64_i64
-; MIPS32O2-LABEL: doubleToUnsigned64
-; MIPS32O2: jal __Sz_fptoui_f64_i64
-
-define internal i64 @floatToUnsigned64(float %a) {
-entry:
- %conv = fptoui float %a to i64
- ret i64 %conv
-}
-; CHECK-LABEL: floatToUnsigned64
-; CHECK: call {{.*}} R_{{.*}} __Sz_fptoui_f32_i64
-; ARM32-LABEL: floatToUnsigned64
-; TODO(jpp): implement this test.
-; MIPS32-LABEL: floatToUnsigned64
-; MIPS32: jal __Sz_fptoui_f32_i64
-; MIPS32O2-LABEL: floatToUnsigned64
-; MIPS32O2: jal __Sz_fptoui_f32_i64
-
-define internal i32 @doubleToSigned32(double %a) {
-entry:
- %conv = fptosi double %a to i32
- ret i32 %conv
-}
-; CHECK-LABEL: doubleToSigned32
-; CHECK: cvttsd2si
-; ARM32-LABEL: doubleToSigned32
-; ARM32-DAG: vcvt.s32.f64 [[REG:s[0-9]*]], {{d[0-9]*}}
-; ARM32-DAG: vmov {{r[0-9]+}}, [[REG]]
-; MIPS32-LABEL: doubleToSigned32
-; MIPS32: trunc.w.d
-; MIPS32O2-LABEL: doubleToSigned32
-; MIPS32O2: trunc.w.d
-
-define internal i32 @doubleToSigned32Const() {
-entry:
- %conv = fptosi double 867.5309 to i32
- ret i32 %conv
-}
-; CHECK-LABEL: doubleToSigned32Const
-; CHECK: cvttsd2si
-; ARM32-LABEL: doubleToSigned32Const
-; ARM32-DAG: movw [[ADDR:r[0-9]+]], #{{.*_MOVW_}}
-; ARM32-DAG: movt [[ADDR]], #{{.*_MOVT_}}
-; ARM32-DAG: vldr [[DREG:d[0-9]+]], {{\[}}[[ADDR]]{{\]}}
-; ARM32-DAG: vcvt.s32.f64 [[REG:s[0-9]+]], [[DREG]]
-; ARM32-DAF: vmov {{r[0-9]+}}, [[REG]]
-; MIPS32-LABEL: doubleToSigned32Const
-; MIPS32: lui
-; MIPS32: ldc1
-; MIPS32: trunc.w.d
-; MIPS32O2-LABEL: doubleToSigned32Const
-; MIPS32O2: lui
-; MIPS32O2: ldc1
-; MIPS32O2: trunc.w.d
-
-define internal i32 @floatToSigned32(float %a) {
-entry:
- %conv = fptosi float %a to i32
- ret i32 %conv
-}
-; CHECK-LABEL: floatToSigned32
-; CHECK: cvttss2si
-; ARM32-LABEL: floatToSigned32
-; ARM32-DAG: vcvt.s32.f32 [[REG:s[0-9]+]], {{s[0-9]+}}
-; ARM32-DAG: vmov {{r[0-9]+}}, [[REG]]
-; MIPS32-LABEL: floatToSigned32
-; MIPS32: trunc.w.s $f{{.*}}, $f{{.*}}
-; MIPS32O2-LABEL: floatToSigned32
-; MIPS32O2: trunc.w.s $[[REG:f[0-9]+]], $f{{.*}}
-; MIPS32O2: mfc1 $v0, $[[REG]]
-
-define internal i32 @doubleToUnsigned32(double %a) {
-entry:
- %conv = fptoui double %a to i32
- ret i32 %conv
-}
-; CHECK-LABEL: doubleToUnsigned32
-; CHECK: call {{.*}} R_{{.*}} __Sz_fptoui_f64_i32
-; ARM32-LABEL: doubleToUnsigned32
-; ARM32-DAG: vcvt.u32.f64 [[REG:s[0-9]+]], {{d[0-9]+}}
-; ARM32-DAG: vmov {{r[0-9]+}}, [[REG]]
-; MIPS32-LABEL: doubleToUnsigned32
-; MIPS32: jal __Sz_fptoui_f64_i32
-; MIPS32O2-LABEL: doubleToUnsigned32
-; MIPS32O2: jal __Sz_fptoui_f64_i32
-
-define internal i32 @floatToUnsigned32(float %a) {
-entry:
- %conv = fptoui float %a to i32
- ret i32 %conv
-}
-; CHECK-LABEL: floatToUnsigned32
-; CHECK: call {{.*}} R_{{.*}} __Sz_fptoui_f32_i32
-; ARM32-LABEL: floatToUnsigned32
-; ARM32-DAG: vcvt.u32.f32 [[REG:s[0-9]+]], {{s[0-9]+}}
-; ARM32-DAG: vmov {{r[0-9]+}}, [[REG]]
-; MIPS32-LABEL: floatToUnsigned32
-; MIPS32: jal __Sz_fptoui_f32_i32
-; MIPS32O2-LABEL: floatToUnsigned32
-; MIPS32O2: jal __Sz_fptoui_f32_i32
-
-define internal i32 @doubleToSigned16(double %a) {
-entry:
- %conv = fptosi double %a to i16
- %conv.ret_ext = sext i16 %conv to i32
- ret i32 %conv.ret_ext
-}
-; CHECK-LABEL: doubleToSigned16
-; CHECK: cvttsd2si
-; CHECK: movsx
-; ARM32-LABEL: doubleToSigned16
-; ARM32-DAG: vcvt.s32.f64 [[REG:s[0-9]*]], {{d[0-9]*}}
-; ARM32-DAG: vmov {{r[0-9]+}}, [[REG]]
-; ARM32: sxth
-; MIPS32-LABEL: doubleToSigned16
-; MIPS32: trunc.w.d
-; MIPS32O2-LABEL: doubleToSigned16
-; MIPS32O2: trunc.w.d
-
-define internal i32 @floatToSigned16(float %a) {
-entry:
- %conv = fptosi float %a to i16
- %conv.ret_ext = sext i16 %conv to i32
- ret i32 %conv.ret_ext
-}
-; CHECK-LABEL: floatToSigned16
-; CHECK: cvttss2si
-; CHECK: movsx
-; ARM32-LABEL: floatToSigned16
-; ARM32-DAG: vcvt.s32.f32 [[REG:s[0-9]*]], {{s[0-9]*}}
-; ARM32-DAG: vmov {{r[0-9]+}}, [[REG]]
-; ARM32: sxth
-; MIPS32-LABEL: floatToSigned16
-; MIPS32: trunc.w.s
-; MIPS32O2-LABEL: floatToSigned16
-; MIPS32O2: trunc.w.s
-
-define internal i32 @doubleToUnsigned16(double %a) {
-entry:
- %conv = fptoui double %a to i16
- %conv.ret_ext = zext i16 %conv to i32
- ret i32 %conv.ret_ext
-}
-; CHECK-LABEL: doubleToUnsigned16
-; CHECK: cvttsd2si
-; CHECK: movzx
-; ARM32-LABEL: doubleToUnsigned16
-; ARM32-DAG: vcvt.u32.f64 [[REG:s[0-9]*]], {{d[0-9]*}}
-; ARM32-DAG: vmov {{r[0-9]+}}, [[REG]]
-; ARM32: uxth
-; MIPS32-LABEL: doubleToUnsigned16
-; MIPS32: trunc.w.d
-; MIPS32O2-LABEL: doubleToUnsigned16
-; MIPS32O2: trunc.w.d
-
-define internal i32 @floatToUnsigned16(float %a) {
-entry:
- %conv = fptoui float %a to i16
- %conv.ret_ext = zext i16 %conv to i32
- ret i32 %conv.ret_ext
-}
-; CHECK-LABEL: floatToUnsigned16
-; CHECK: cvttss2si
-; CHECK: movzx
-; ARM32-LABEL: floatToUnsigned16
-; ARM32-DAG: vcvt.u32.f32 [[REG:s[0-9]*]], {{s[0-9]*}}
-; ARM32-DAG: vmov {{r[0-9]+}}, [[REG]]
-; ARM32: uxth
-; MIPS32-LABEL: floatToUnsigned16
-; MIPS32: trunc.w.s
-; MIPS32O2-LABEL: floatToUnsigned16
-; MIPS32O2: trunc.w.s
-
-define internal i32 @doubleToSigned8(double %a) {
-entry:
- %conv = fptosi double %a to i8
- %conv.ret_ext = sext i8 %conv to i32
- ret i32 %conv.ret_ext
-}
-; CHECK-LABEL: doubleToSigned8
-; CHECK: cvttsd2si
-; CHECK: movsx
-; ARM32-LABEL: doubleToSigned8
-; ARM32-DAG: vcvt.s32.f64 [[REG:s[0-9]*]], {{d[0-9]*}}
-; ARM32-DAG: vmov {{r[0-9]+}}, [[REG]]
-; ARM32: sxtb
-; MIPS32-LABEL: doubleToSigned8
-; MIPS32: trunc.w.d
-; MIPS32O2-LABEL: doubleToSigned8
-; MIPS32O2: trunc.w.d
-
-define internal i32 @floatToSigned8(float %a) {
-entry:
- %conv = fptosi float %a to i8
- %conv.ret_ext = sext i8 %conv to i32
- ret i32 %conv.ret_ext
-}
-; CHECK-LABEL: floatToSigned8
-; CHECK: cvttss2si
-; CHECK: movsx
-; ARM32-LABEL: floatToSigned8
-; ARM32-DAG: vcvt.s32.f32 [[REG:s[0-9]*]], {{s[0-9]*}}
-; ARM32-DAG: vmov {{r[0-9]+}}, [[REG]]
-; ARM32: sxtb
-; MIPS32-LABEL: floatToSigned8
-; MIPS32: trunc.w.s
-; MIPS32O2-LABEL: floatToSigned8
-; MIPS32O2: trunc.w.s
-
-define internal i32 @doubleToUnsigned8(double %a) {
-entry:
- %conv = fptoui double %a to i8
- %conv.ret_ext = zext i8 %conv to i32
- ret i32 %conv.ret_ext
-}
-; CHECK-LABEL: doubleToUnsigned8
-; CHECK: cvttsd2si
-; CHECK: movzx
-; ARM32-LABEL: doubleToUnsigned8
-; ARM32-DAG: vcvt.u32.f64 [[REG:s[0-9]*]], {{d[0-9]*}}
-; ARM32-DAG: vmov {{r[0-9]+}}, [[REG]]
-; ARM32: uxtb
-; MIPS32-LABEL: doubleToUnsigned8
-; MIPS32: trunc.w.d
-; MIPS32O2-LABEL: doubleToUnsigned8
-; MIPS32O2: trunc.w.d
-
-define internal i32 @floatToUnsigned8(float %a) {
-entry:
- %conv = fptoui float %a to i8
- %conv.ret_ext = zext i8 %conv to i32
- ret i32 %conv.ret_ext
-}
-; CHECK-LABEL: floatToUnsigned8
-; CHECK: cvttss2si
-; CHECK: movzx
-; ARM32-LABEL: floatToUnsigned8
-; ARM32-DAG: vcvt.u32.f32 [[REG:s[0-9]*]], {{s[0-9]*}}
-; ARM32-DAG: vmov {{r[0-9]+}}, [[REG]]
-; ARM32: uxtb
-; MIPS32-LABEL: floatToUnsigned8
-; MIPS32: trunc.w.s
-; MIPS32O2-LABEL: floatToUnsigned8
-; MIPS32O2: trunc.w.s
-
-define internal i32 @doubleToUnsigned1(double %a) {
-entry:
- %tobool = fptoui double %a to i1
- %tobool.ret_ext = zext i1 %tobool to i32
- ret i32 %tobool.ret_ext
-}
-; CHECK-LABEL: doubleToUnsigned1
-; CHECK: cvttsd2si
-; CHECK-NOT: and eax,0x1
-; ARM32-LABEL: doubleToUnsigned1
-; ARM32-DAG: vcvt.u32.f64 [[REG:s[0-9]*]], {{d[0-9]*}}
-; ARM32-DAG: vmov [[RES:r[0-9]+]], [[REG]]
-; ARM32-DAG: and {{r[0-9]+}}, [[RES]], #1
-; ARM32-NOT: uxth
-; ARM32-NOT: uxtb
-; MIPS32-LABEL: doubleToUnsigned1
-; MIPS32: trunc.w.d
-; MIPS32O2-LABEL: doubleToUnsigned1
-; MIPS32O2: trunc.w.d
-
-define internal i32 @floatToUnsigned1(float %a) {
-entry:
- %tobool = fptoui float %a to i1
- %tobool.ret_ext = zext i1 %tobool to i32
- ret i32 %tobool.ret_ext
-}
-; CHECK-LABEL: floatToUnsigned1
-; CHECK: cvttss2si
-; CHECK-NOT: and eax,0x1
-; ARM32-LABEL: floatToUnsigned1
-; ARM32-DAG: vcvt.u32.f32 [[REG:s[0-9]*]], {{s[0-9]*}}
-; ARM32-DAG: vmov [[RES:r[0-9]+]], [[REG]]
-; ARM32-DAG: and {{r[0-9]+}}, [[RES]], #1
-; ARM32-NOT: uxth
-; ARM32-NOT: uxtb
-; MIPS32-LABEL: floatToUnsigned1
-; MIPS32: trunc.w.s
-; MIPS32O2-LABEL: floatToUnsigned1
-; MIPS32O2: trunc.w.s
-
-define internal double @signed64ToDouble(i64 %a) {
-entry:
- %conv = sitofp i64 %a to double
- ret double %conv
-}
-; CHECK-LABEL: signed64ToDouble
-; CHECK: call {{.*}} R_{{.*}} __Sz_sitofp_i64_f64
-; CHECK: fstp QWORD
-; ARM32-LABEL: signed64ToDouble
-; TODO(jpp): implement this test.
-; MIPS32-LABEL: signed64ToDouble
-; MIPS32: jal __Sz_sitofp_i64_f64
-; MIPS32O2-LABEL: signed64ToDouble
-; MIPS32O2: jal __Sz_sitofp_i64_f64
-
-define internal float @signed64ToFloat(i64 %a) {
-entry:
- %conv = sitofp i64 %a to float
- ret float %conv
-}
-; CHECK-LABEL: signed64ToFloat
-; CHECK: call {{.*}} R_{{.*}} __Sz_sitofp_i64_f32
-; CHECK: fstp DWORD
-; ARM32-LABEL: signed64ToFloat
-; TODO(jpp): implement this test.
-; MIPS32-LABEL: signed64ToFloat
-; MIPS32: jal __Sz_sitofp_i64_f32
-; MIPS32O2-LABEL: signed64ToFloat
-; MIPS32O2: jal __Sz_sitofp_i64_f32
-
-define internal double @unsigned64ToDouble(i64 %a) {
-entry:
- %conv = uitofp i64 %a to double
- ret double %conv
-}
-; CHECK-LABEL: unsigned64ToDouble
-; CHECK: call {{.*}} R_{{.*}} __Sz_uitofp_i64_f64
-; CHECK: fstp
-; ARM32-LABEL: unsigned64ToDouble
-; TODO(jpp): implement this test.
-; MIPS32-LABEL: unsigned64ToDouble
-; MIPS32: jal __Sz_uitofp_i64_f64
-; MIPS32O2-LABEL: unsigned64ToDouble
-; MIPS32O2: jal __Sz_uitofp_i64_f64
-
-define internal float @unsigned64ToFloat(i64 %a) {
-entry:
- %conv = uitofp i64 %a to float
- ret float %conv
-}
-; CHECK-LABEL: unsigned64ToFloat
-; CHECK: call {{.*}} R_{{.*}} __Sz_uitofp_i64_f32
-; CHECK: fstp
-; ARM32-LABEL: unsigned64ToFloat
-; TODO(jpp): implement this test.
-; MIPS32-LABEL: unsigned64ToFloat
-; MIPS32: jal __Sz_uitofp_i64_f32
-; MIPS32O2-LABEL: unsigned64ToFloat
-; MIPS32O2: jal __Sz_uitofp_i64_f32
-
-define internal double @unsigned64ToDoubleConst() {
-entry:
- %conv = uitofp i64 12345678901234 to double
- ret double %conv
-}
-; CHECK-LABEL: unsigned64ToDoubleConst
-; CHECK: mov DWORD PTR [esp+0x4],0xb3a
-; CHECK: mov DWORD PTR [esp],0x73ce2ff2
-; CHECK: call {{.*}} R_{{.*}} __Sz_uitofp_i64_f64
-; CHECK: fstp
-; ARM32-LABEL: unsigned64ToDoubleConst
-; TODO(jpp): implement this test.
-; MIPS32-LABEL: unsigned64ToDoubleConst
-; MIPS32: jal __Sz_uitofp_i64_f64
-; MIPS32O2-LABEL: unsigned64ToDoubleConst
-; MIPS32O2: jal __Sz_uitofp_i64_f64
-
-define internal double @signed32ToDouble(i32 %a) {
-entry:
- %conv = sitofp i32 %a to double
- ret double %conv
-}
-; CHECK-LABEL: signed32ToDouble
-; CHECK: cvtsi2sd
-; CHECK: fld
-; ARM32-LABEL: signed32ToDouble
-; ARM32-DAG: vmov [[SRC:s[0-9]+]], {{r[0-9]+}}
-; ARM32-DAG: vcvt.f64.s32 {{d[0-9]+}}, [[SRC]]
-; MIPS32-LABEL: signed32ToDouble
-; MIPS32: cvt.d.w
-; MIPS32O2-LABEL: signed32ToDouble
-; MIPS32O2: cvt.d.w
-
-define internal double @signed32ToDoubleConst() {
-entry:
- %conv = sitofp i32 123 to double
- ret double %conv
-}
-; CHECK-LABEL: signed32ToDoubleConst
-; CHECK: cvtsi2sd {{.*[^1]}}
-; CHECK: fld
-; ARM32-LABEL: signed32ToDoubleConst
-; ARM32-DAG: mov [[CONST:r[0-9]+]], #123
-; ARM32-DAG: vmov [[SRC:s[0-9]+]], [[CONST]]
-; ARM32-DAG: vcvt.f64.s32 {{d[0-9]+}}, [[SRC]]
-; MIPS32-LABEL: signed32ToDoubleConst
-; MIPS32: cvt.d.w
-; MIPS32O2-LABEL: signed32ToDoubleConst
-; MIPS32O2: cvt.d.w
-
-define internal float @signed32ToFloat(i32 %a) {
-entry:
- %conv = sitofp i32 %a to float
- ret float %conv
-}
-; CHECK-LABEL: signed32ToFloat
-; CHECK: cvtsi2ss
-; CHECK: fld
-; ARM32-LABEL: signed32ToFloat
-; ARM32-DAG: vmov [[SRC:s[0-9]+]], {{r[0-9]+}}
-; ARM32-DAG: vcvt.f32.s32 {{s[0-9]+}}, [[SRC]]
-; MIPS32-LABEL: signed32ToFloat
-; MIPS32: cvt.s.w $f{{.*}}, $f{{.*}}
-; MIPS32O2-LABEL: signed32ToFloat
-; MIPS32O2: mtc1 $a0, $[[REG:f[0-9]+]]
-; MIPS32O2: cvt.s.w $f{{.*}}, $[[REG]]
-
-define internal double @unsigned32ToDouble(i32 %a) {
-entry:
- %conv = uitofp i32 %a to double
- ret double %conv
-}
-; CHECK-LABEL: unsigned32ToDouble
-; CHECK: call {{.*}} R_{{.*}} __Sz_uitofp_i32_f64
-; CHECK: fstp QWORD
-; ARM32-LABEL: unsigned32ToDouble
-; ARM32-DAG: vmov [[SRC:s[0-9]+]], {{r[0-9]+}}
-; ARM32-DAG: vcvt.f64.u32 {{d[0-9]+}}, [[SRC]]
-; MIPS32-LABEL: unsigned32ToDouble
-; MIPS32: jal __Sz_uitofp_i32_f64
-; MIPS32O2-LABEL: unsigned32ToDouble
-; MIPS32O2: jal __Sz_uitofp_i32_f64
-
-define internal float @unsigned32ToFloat(i32 %a) {
-entry:
- %conv = uitofp i32 %a to float
- ret float %conv
-}
-; CHECK-LABEL: unsigned32ToFloat
-; CHECK: call {{.*}} R_{{.*}} __Sz_uitofp_i32_f32
-; CHECK: fstp DWORD
-; ARM32-LABEL: unsigned32ToFloat
-; ARM32-DAG: vmov [[SRC:s[0-9]+]], {{r[0-9]+}}
-; ARM32-DAG: vcvt.f32.u32 {{s[0-9]+}}, [[SRC]]
-; MIPS32-LABEL: unsigned32ToFloat
-; MIPS32: jal __Sz_uitofp_i32_f32
-; MIPS32O2-LABEL: unsigned32ToFloat
-; MIPS32O2: jal __Sz_uitofp_i32_f32
-
-define internal double @signed16ToDouble(i32 %a) {
-entry:
- %a.arg_trunc = trunc i32 %a to i16
- %conv = sitofp i16 %a.arg_trunc to double
- ret double %conv
-}
-; CHECK-LABEL: signed16ToDouble
-; CHECK: cvtsi2sd
-; CHECK: fld QWORD
-; ARM32-LABEL: signed16ToDouble
-; ARM32-DAG: sxth [[INT:r[0-9]+]]
-; ARM32-DAG: vmov [[SRC:s[0-9]+]], [[INT]]
-; ARM32-DAG: vcvt.f64.s32 {{d[0-9]+}}, [[SRC]]
-; MIPS32-LABEL: signed16ToDouble
-; MIPS32: cvt.d.w
-; MIPS32O2-LABEL: signed16ToDouble
-; MIPS32O2: cvt.d.w
-
-define internal float @signed16ToFloat(i32 %a) {
-entry:
- %a.arg_trunc = trunc i32 %a to i16
- %conv = sitofp i16 %a.arg_trunc to float
- ret float %conv
-}
-; CHECK-LABEL: signed16ToFloat
-; CHECK: cvtsi2ss
-; CHECK: fld DWORD
-; ARM32-LABEL: signed16ToFloat
-; ARM32-DAG: sxth [[INT:r[0-9]+]]
-; ARM32-DAG: vmov [[SRC:s[0-9]+]], [[INT]]
-; ARM32-DAG: vcvt.f32.s32 {{s[0-9]+}}, [[SRC]]
-; MIPS32-LABEL: signed16ToFloat
-; MIPS32: cvt.s.w
-; MIPS32O2-LABEL: signed16ToFloat
-; MIPS32O2: cvt.s.w
-
-define internal double @unsigned16ToDouble(i32 %a) {
-entry:
- %a.arg_trunc = trunc i32 %a to i16
- %conv = uitofp i16 %a.arg_trunc to double
- ret double %conv
-}
-; CHECK-LABEL: unsigned16ToDouble
-; CHECK: cvtsi2sd
-; CHECK: fld
-; ARM32-LABEL: unsigned16ToDouble
-; ARM32-DAG: uxth [[INT:r[0-9]+]]
-; ARM32-DAG: vmov [[SRC:s[0-9]+]], [[INT]]
-; ARM32-DAG: vcvt.f64.u32 {{d[0-9]+}}, [[SRC]]
-; MIPS32-LABEL: unsigned16ToDouble
-; MIPS32: cvt.d.w
-; MIPS32O2-LABEL: unsigned16ToDouble
-; MIPS32O2: cvt.d.w
-
-define internal double @unsigned16ToDoubleConst() {
-entry:
- %conv = uitofp i16 12345 to double
- ret double %conv
-}
-; CHECK-LABEL: unsigned16ToDoubleConst
-; CHECK: cvtsi2sd
-; CHECK: fld
-; ARM32-LABEL: unsigned16ToDoubleConst
-; ARM32-DAG: movw [[INT:r[0-9]+]], #12345
-; ARM32-DAG: uxth [[INT]]
-; ARM32-DAG: vmov [[SRC:s[0-9]+]], [[INT]]
-; ARM32-DAG: vcvt.f64.u32 {{d[0-9]+}}, [[SRC]]
-; MIPS32-LABEL: unsigned16ToDoubleConst
-; MIPS32: cvt.d.w
-; MIPS32O2-LABEL: unsigned16ToDoubleConst
-; MIPS32O2: cvt.d.w
-
-define internal float @unsigned16ToFloat(i32 %a) {
-entry:
- %a.arg_trunc = trunc i32 %a to i16
- %conv = uitofp i16 %a.arg_trunc to float
- ret float %conv
-}
-; CHECK-LABEL: unsigned16ToFloat
-; CHECK: cvtsi2ss
-; CHECK: fld
-; ARM32-LABEL: unsigned16ToFloat
-; ARM32-DAG: uxth [[INT:r[0-9]+]]
-; ARM32-DAG: vmov [[SRC:s[0-9]+]], [[INT]]
-; ARM32-DAG: vcvt.f32.u32 {{s[0-9]+}}, [[SRC]]
-; MIPS32-LABEL: unsigned16ToFloat
-; MIPS32: cvt.s.w
-; MIPS32O2-LABEL: unsigned16ToFloat
-; MIPS32O2: cvt.s.w
-
-define internal double @signed8ToDouble(i32 %a) {
-entry:
- %a.arg_trunc = trunc i32 %a to i8
- %conv = sitofp i8 %a.arg_trunc to double
- ret double %conv
-}
-; CHECK-LABEL: signed8ToDouble
-; CHECK: cvtsi2sd
-; CHECK: fld
-; ARM32-LABEL: signed8ToDouble
-; ARM32-DAG: sxtb [[INT:r[0-9]+]]
-; ARM32-DAG: vmov [[SRC:s[0-9]+]], [[INT]]
-; ARM32-DAG: vcvt.f64.s32 {{d[0-9]+}}, [[SRC]]
-; MIPS32-LABEL: signed8ToDouble
-; MIPS32: cvt.d.w
-; MIPS32O2-LABEL: signed8ToDouble
-; MIPS32O2: cvt.d.w
-
-define internal float @signed8ToFloat(i32 %a) {
-entry:
- %a.arg_trunc = trunc i32 %a to i8
- %conv = sitofp i8 %a.arg_trunc to float
- ret float %conv
-}
-; CHECK-LABEL: signed8ToFloat
-; CHECK: cvtsi2ss
-; CHECK: fld
-; ARM32-LABEL: signed8ToFloat
-; ARM32-DAG: sxtb [[INT:r[0-9]+]]
-; ARM32-DAG: vmov [[SRC:s[0-9]+]], [[INT]]
-; ARM32-DAG: vcvt.f32.s32 {{s[0-9]+}}, [[SRC]]
-; MIPS32-LABEL: signed8ToFloat
-; MIPS32: cvt.s.w
-; MIPS32O2-LABEL: signed8ToFloat
-; MIPS32O2: cvt.s.w
-
-define internal double @unsigned8ToDouble(i32 %a) {
-entry:
- %a.arg_trunc = trunc i32 %a to i8
- %conv = uitofp i8 %a.arg_trunc to double
- ret double %conv
-}
-; CHECK-LABEL: unsigned8ToDouble
-; CHECK: cvtsi2sd
-; CHECK: fld
-; ARM32-LABEL: unsigned8ToDouble
-; ARM32-DAG: uxtb [[INT:r[0-9]+]]
-; ARM32-DAG: vmov [[SRC:s[0-9]+]], [[INT]]
-; ARM32-DAG: vcvt.f64.u32 {{d[0-9]+}}, [[SRC]]
-; MIPS32-LABEL: unsigned8ToDouble
-; MIPS32: cvt.d.w
-; MIPS32O2-LABEL: unsigned8ToDouble
-; MIPS32O2: cvt.d.w
-
-define internal float @unsigned8ToFloat(i32 %a) {
-entry:
- %a.arg_trunc = trunc i32 %a to i8
- %conv = uitofp i8 %a.arg_trunc to float
- ret float %conv
-}
-; CHECK-LABEL: unsigned8ToFloat
-; CHECK: cvtsi2ss
-; CHECK: fld
-; ARM32-LABEL: unsigned8ToFloat
-; ARM32-DAG: uxtb [[INT:r[0-9]+]]
-; ARM32-DAG: vmov [[SRC:s[0-9]+]], [[INT]]
-; ARM32-DAG: vcvt.f32.u32 {{s[0-9]+}}, [[SRC]]
-; MIPS32-LABEL: unsigned8ToFloat
-; MIPS32: cvt.s.w
-; MIPS32O2-LABEL: unsigned8ToFloat
-; MIPS32O2: cvt.s.w
-
-define internal double @unsigned1ToDouble(i32 %a) {
-entry:
- %a.arg_trunc = trunc i32 %a to i1
- %conv = uitofp i1 %a.arg_trunc to double
- ret double %conv
-}
-; CHECK-LABEL: unsigned1ToDouble
-; CHECK: cvtsi2sd
-; CHECK: fld
-; ARM32-LABEL: unsigned1ToDouble
-; ARM32-DAG: and [[INT:r[0-9]+]], {{r[0-9]+}}, #1
-; ARM32-DAG: vmov [[SRC:s[0-9]+]], [[INT]]
-; ARM32-DAG: vcvt.f64.u32 {{d[0-9]+}}, [[SRC]]
-; MIPS32-LABEL: unsigned1ToDouble
-; MIPS32: cvt.d.w
-; MIPS32O2-LABEL: unsigned1ToDouble
-; MIPS32O2: cvt.d.w
-
-define internal float @unsigned1ToFloat(i32 %a) {
-entry:
- %a.arg_trunc = trunc i32 %a to i1
- %conv = uitofp i1 %a.arg_trunc to float
- ret float %conv
-}
-; CHECK-LABEL: unsigned1ToFloat
-; CHECK: cvtsi2ss
-; CHECK: fld
-; ARM32-LABEL: unsigned1ToFloat
-; ARM32-DAG: and [[INT:r[0-9]+]], {{r[0-9]+}}, #1
-; ARM32-DAG: vmov [[SRC:s[0-9]+]], [[INT]]
-; ARM32-DAG: vcvt.f32.u32 {{s[0-9]+}}, [[SRC]]
-; MIPS32-LABEL: unsigned1ToFloat
-; MIPS32: cvt.s.w
-; MIPS32O2-LABEL: unsigned1ToFloat
-; MIPS32O2: cvt.s.w
-
-define internal float @int32BitcastToFloat(i32 %a) {
-entry:
- %conv = bitcast i32 %a to float
- ret float %conv
-}
-; CHECK-LABEL: int32BitcastToFloat
-; CHECK: mov
-; ARM32-LABEL: int32BitcastToFloat
-; ARM32: vmov s{{[0-9]+}}, r{{[0-9]+}}
-; MIPS32-LABEL: int32BitcastToFloat
-; MIPS32: sw
-; MIPS32: lwc1
-; MIPS32O2-LABEL: int32BitcastToFloat
-
-define internal float @int32BitcastToFloatConst() {
-entry:
- %conv = bitcast i32 8675309 to float
- ret float %conv
-}
-; CHECK-LABEL: int32BitcastToFloatConst
-; CHECK: mov
-; ARM32-LABEL: int32BitcastToFloatConst
-; ARM32-DAG: movw [[REG:r[0-9]+]], #24557
-; ARM32-DAG: movt [[REG]], #132
-; ARM32: vmov s{{[0-9]+}}, [[REG]]
-; MIPS32-LABEL: int32BitcastToFloatConst
-; MIPS32: lwc1
-; MIPS32O2-LABEL: int32BitcastToFloatConst
-
-define internal double @int64BitcastToDouble(i64 %a) {
-entry:
- %conv = bitcast i64 %a to double
- ret double %conv
-}
-; CHECK-LABEL: int64BitcastToDouble
-; CHECK: mov
-; ARM32-LABEL: int64BitcastToDouble
-; ARM32: vmov d{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}
-; MIPS32-LABEL: int64BitcastToDouble
-; MIPS32: sw
-; MIPS32: sw
-; MIPS32: ldc1
-; MIPS32O2-LABEL: int64BitcastToDouble
-
-define internal double @int64BitcastToDoubleConst() {
-entry:
- %conv = bitcast i64 9035768 to double
- ret double %conv
-}
-; CHECK-LABEL: int64BitcastToDoubleConst
-; CHECK: mov
-; ARM32-LABEL: int64BitcastToDoubleConst
-; ARM32-DAG: movw [[REG0:r[0-9]+]], #57336
-; ARM32-DAG: movt [[REG0]], #137
-; ARM32-DAG: mov [[REG1:r[0-9]+]], #0
-; ARM32-DAG: vmov d{{[0-9]+}}, [[REG0]], [[REG1]]
-; MIPS32-LABEL: int64BitcastToDoubleConst
-; MIPS32: ldc1
-; MIPS32O2-LABEL: int64BitcastToDoubleConst
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/fp.load_store.ll b/third_party/subzero/tests_lit/llvm2ice_tests/fp.load_store.ll
deleted file mode 100644
index a0089a1..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/fp.load_store.ll
+++ /dev/null
@@ -1,122 +0,0 @@
-; This tries to be a comprehensive test of f32 and f64 compare operations.
-; The CHECK lines are only checking for basic instruction patterns
-; that should be present regardless of the optimization level, so
-; there are no special OPTM1 match lines.
-
-; RUN: %p2i --filetype=obj --disassemble -i %s --args -O2 | FileCheck %s
-; RUN: %p2i --filetype=obj --disassemble -i %s --args -Om1 | FileCheck %s
-
-; RUN: %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command %p2i --filetype=asm --assemble \
-; RUN: --disassemble --target mips32 -i %s --args -Om1 \
-; RUN: -allow-externally-defined-symbols \
-; RUN: | %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command FileCheck --check-prefix MIPS32 %s
-
-; RUN: %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command %p2i --filetype=asm --assemble \
-; RUN: --disassemble --target mips32 -i %s --args -O2 \
-; RUN: -allow-externally-defined-symbols \
-; RUN: | %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command FileCheck --check-prefix MIPS32O2 %s
-
-define internal float @loadFloat(i32 %a) {
-entry:
- %__1 = inttoptr i32 %a to float*
- %v0 = load float, float* %__1, align 4
- ret float %v0
-}
-; CHECK-LABEL: loadFloat
-; CHECK: movss
-; CHECK: fld
-
-; MIPS32-LABEL: loadFloat
-; MIPS32: lwc1 $f{{.*}},0{{.*}}
-; MIPS32O2-LABEL: loadFloat
-; MIPS32O2: lwc1 $f{{.*}},0{{.*}}
-
-define internal double @loadDouble(i32 %a) {
-entry:
- %__1 = inttoptr i32 %a to double*
- %v0 = load double, double* %__1, align 8
- ret double %v0
-}
-; CHECK-LABEL: loadDouble
-; CHECK: movsd
-; CHECK: fld
-
-; MIPS32-LABEL: loadDouble
-; MIPS32: ldc1 $f{{.*}},0{{.*}}
-; MIPS32O2-LABEL: loadDouble
-; MIPS32O2: ldc1 $f{{.*}},0{{.*}}
-
-define internal void @storeFloat(i32 %a, float %value) {
-entry:
- %__2 = inttoptr i32 %a to float*
- store float %value, float* %__2, align 4
- ret void
-}
-; CHECK-LABEL: storeFloat
-; CHECK: movss
-; CHECK: movss
-
-; MIPS32-LABEL: storeFloat
-; MIPS32: swc1 $f{{.*}},0{{.*}}
-; MIPS32O2-LABEL: storeFloat
-; MIPS32O2: mtc1 a1,$f{{.*}}
-; MIPS32O2: swc1 $f{{.*}},0(a0)
-
-define internal void @storeDouble(i32 %a, double %value) {
-entry:
- %__2 = inttoptr i32 %a to double*
- store double %value, double* %__2, align 8
- ret void
-}
-; CHECK-LABEL: storeDouble
-; CHECK: movsd
-; CHECK: movsd
-
-; MIPS32-LABEL: storeDouble
-; MIPS32: sdc1 $f{{.*}},0{{.*}}
-; MIPS32O2-LABEL: storeDouble
-; MIPS32O2: mtc1 a2,$f{{.*}}
-; MIPS32O2: mtc1 a3,$f{{.*}}
-; MIPS32O2: sdc1 $f{{.*}},0(a0)
-
-define internal void @storeFloatConst(i32 %a) {
-entry:
- %a.asptr = inttoptr i32 %a to float*
- store float 0x3FF3AE1480000000, float* %a.asptr, align 4
- ret void
-}
-; CHECK-LABEL: storeFloatConst
-; CHECK: movss
-; CHECK: movss
-
-; MIPS32-LABEL: storeFloatConst
-; MIPS32: lui {{.*}},{{.*}}
-; MIPS32: lwc1 $f{{.*}},{{.*}}
-; MIPS32: swc1 $f{{.*}},0{{.*}}
-; MIPS32O2-LABEL: storeFloatConst
-; MIPS32O2: lui {{.*}},{{.*}}
-; MIPS32O2: lwc1 $f{{.*}},{{.*}}
-; MIPS32O2: swc1 $f{{.*}},0{{.*}}
-
-define internal void @storeDoubleConst(i32 %a) {
-entry:
- %a.asptr = inttoptr i32 %a to double*
- store double 1.230000e+00, double* %a.asptr, align 8
- ret void
-}
-; CHECK-LABEL: storeDoubleConst
-; CHECK: movsd
-; CHECK: movsd
-
-; MIPS32-LABEL: storeDoubleConst
-; MIPS32: lui {{.*}},{{.*}}
-; MIPS32: ldc1 $f{{.*}},{{.*}}
-; MIPS32: sdc1 $f{{.*}},0{{.*}}
-; MIPS32O2-LABEL: storeDoubleConst
-; MIPS32O2: lui {{.*}},{{.*}}
-; MIPS32O2: ldc1 $f{{.*}},{{.*}}
-; MIPS32O2: sdc1 $f{{.*}},0{{.*}}
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/fp_const_pool.ll b/third_party/subzero/tests_lit/llvm2ice_tests/fp_const_pool.ll
deleted file mode 100644
index 7ab7c43..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/fp_const_pool.ll
+++ /dev/null
@@ -1,128 +0,0 @@
-; This tests that different floating point constants (such as 0.0 and -0.0)
-; remain distinct even when they sort of look equal, and also that different
-; instances of the same floating point constant (such as NaN and NaN) get the
-; same constant pool entry even when "a==a" would suggest they are different.
-
-; REQUIRES: allow_dump
-
-; RUN: %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command %p2i --filetype=asm --assemble --disassemble \
-; RUN: --target mips32 -i %s --args -O2 \
-; RUN: | %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command FileCheck --check-prefix MIPS32 %s
-
-define internal void @consume_float(float %f) {
- ret void
-}
-
-define internal void @consume_double(double %d) {
- ret void
-}
-
-define internal void @test_zeros() {
-entry:
- call void @consume_float(float 0.0)
- call void @consume_float(float -0.0)
- call void @consume_double(double 0.0)
- call void @consume_double(double -0.0)
- ret void
-}
-
-; MIPS32-LABEL: test_zeros
-; MIPS32: mtc1 zero,[[REG:.*]]
-; MIPS32: mov.s {{.*}},[[REG]]
-; MIPS32: lui [[REG:.*]],{{.*}}: R_MIPS_HI16 .L$float$80000000
-; MIPS32: lwc1 {{.*}},0([[REG]]) {{.*}}: R_MIPS_LO16 .L$float$80000000
-; MIPS32: mtc1 zero,[[REGLo:.*]]
-; MIPS32: mtc1 zero,[[REGHi:.*]]
-; MIPS32: mov.d {{.*}},[[REGLo]]
-; MIPS32: lui [[REG:.*]],{{.*}}: R_MIPS_HI16 .L$double$8000000000000000
-; MIPS32: ldc1 {{.*}},0([[REG]]) {{.*}}: R_MIPS_LO16 .L$double$8000000000000000
-
-; Parse the function, dump the bitcode back out, and stop without translating.
-; This tests that +0.0 and -0.0 aren't accidentally merged into a single
-; zero-valued constant pool entry.
-;
-; RUN: %p2i -i %s --insts | FileCheck --check-prefix=ZERO %s
-; ZERO: test_zeros
-; ZERO-NEXT: entry:
-; ZERO-NEXT: call void @consume_float(float 0.0
-; ZERO-NEXT: call void @consume_float(float -0.0
-; ZERO-NEXT: call void @consume_double(double 0.0
-; ZERO-NEXT: call void @consume_double(double -0.0
-
-
-define internal void @test_nans() {
-entry:
- call void @consume_float(float 0x7FF8000000000000)
- call void @consume_float(float 0x7FF8000000000000)
- call void @consume_float(float 0xFFF8000000000000)
- call void @consume_float(float 0xFFF8000000000000)
- call void @consume_double(double 0x7FF8000000000000)
- call void @consume_double(double 0x7FF8000000000000)
- call void @consume_double(double 0xFFF8000000000000)
- call void @consume_double(double 0xFFF8000000000000)
- ret void
-}
-
-; MIPS32-LABEL: test_nans
-; MIPS32: lui [[REG:.*]],{{.*}}: R_MIPS_HI16 .L$float$7fc00000
-; MIPS32: lwc1 {{.*}},0([[REG]]) {{.*}}: R_MIPS_LO16 .L$float$7fc00000
-; MIPS32: lui [[REG:.*]],{{.*}}: R_MIPS_HI16 .L$float$7fc00000
-; MIPS32: lwc1 {{.*}},0([[REG]]) {{.*}}: R_MIPS_LO16 .L$float$7fc00000
-; MIPS32: lui [[REG:.*]],{{.*}}: R_MIPS_HI16 .L$float$ffc00000
-; MIPS32: lwc1 {{.*}},0([[REG]]) {{.*}}: R_MIPS_LO16 .L$float$ffc00000
-; MIPS32: lui [[REG:.*]],{{.*}}: R_MIPS_HI16 .L$float$ffc00000
-; MIPS32: lwc1 {{.*}},0([[REG]]) {{.*}}: R_MIPS_LO16 .L$float$ffc00000
-; MIPS32: lui [[REG:.*]],{{.*}}: R_MIPS_HI16 .L$double$7ff8000000000000
-; MIPS32: ldc1 {{.*}},0([[REG]]) {{.*}}: R_MIPS_LO16 .L$double$7ff8000000000000
-; MIPS32: lui [[REG:.*]],{{.*}}: R_MIPS_HI16 .L$double$7ff8000000000000
-; MIPS32: ldc1 {{.*}},0([[REG]]) {{.*}}: R_MIPS_LO16 .L$double$7ff8000000000000
-; MIPS32: lui [[REG:.*]],{{.*}}: R_MIPS_HI16 .L$double$fff8000000000000
-; MIPS32: ldc1 {{.*}},0([[REG]]) {{.*}}: R_MIPS_LO16 .L$double$fff8000000000000
-; MIPS32: lui [[REG:.*]],{{.*}}: R_MIPS_HI16 .L$double$fff8000000000000
-; MIPS32: ldc1 {{.*}},0([[REG]]) {{.*}}: R_MIPS_LO16 .L$double$fff8000000000000
-; MIPS32: jr ra
-
-; The following tests check the emitted constant pool entries and make sure
-; there is at most one entry for each NaN value. We have to run a separate test
-; for each NaN because the constant pool entries may be emitted in any order.
-;
-; RUN: %p2i -i %s --filetype=asm --llvm-source \
-; RUN: | FileCheck --check-prefix=NANS1 %s
-; NANS1: float nan
-; NANS1-NOT: float nan
-;
-; RUN: %p2i -i %s --filetype=asm --llvm-source \
-; RUN: | FileCheck --check-prefix=NANS2 %s
-; NANS2: float -nan
-; NANS2-NOT: float -nan
-;
-; RUN: %p2i -i %s --filetype=asm --llvm-source \
-; RUN: | FileCheck --check-prefix=NANS3 %s
-; NANS3: double nan
-; NANS3-NOT: double nan
-;
-; RUN: %p2i -i %s --filetype=asm --llvm-source \
-; RUN: | FileCheck --check-prefix=NANS4 %s
-; NANS4: double -nan
-; NANS4-NOT: double -nan
-
-; MIPS32 constant pool
-; RUN: %if --need=target_MIPS32 --command %p2i \
-; RUN: --target mips32 -i %s --filetype=asm --llvm-source \
-; RUN: --args -O2 \
-; RUN: | %if --need=target_MIPS32 --command FileCheck \
-; RUN: --check-prefix=MIPS32CP %s
-; MIPS32CP-LABEL: .L$float$7fc00000:
-; MIPS32CP: .word 0x7fc00000 /* f32 nan */
-; MIPS32CP-LABEL: .L$float$80000000
-; MIPS32CP: .word 0x80000000 /* f32 -0.000000e+00 */
-; MIPS32CP-LABEL: .L$float$ffc00000
-; MIPS32CP: .word 0xffc00000 /* f32 -nan */
-; MIPS32CP-LABEL: .L$double$7ff8000000000000
-; MIPS32CP: .quad 0x7ff8000000000000 /* f64 nan */
-; MIPS32CP-LABEL: .L$double$8000000000000000
-; MIPS32CP: .quad 0x8000000000000000 /* f64 -0.000000e+00 */
-; MIPS32CP-LABEL: .L$double$fff8000000000000
-; MIPS32CP: .quad 0xfff8000000000000 /* f64 -nan */
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/fpcall.ll b/third_party/subzero/tests_lit/llvm2ice_tests/fpcall.ll
deleted file mode 100644
index 07d1830..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/fpcall.ll
+++ /dev/null
@@ -1,47 +0,0 @@
-; Test that for calls returning a floating-point value, the calling
-; ABI with respect to the x87 floating point stack is honored. In
-; particular, the top-of-stack must be popped regardless of whether
-; its value is used.
-
-; RUN: %p2i --filetype=obj --disassemble -i %s --args -O2 \
-; RUN: -allow-externally-defined-symbols | FileCheck %s
-; RUN: %p2i --filetype=obj --disassemble -i %s --args -Om1 \
-; RUN: -allow-externally-defined-symbols | FileCheck %s
-
-declare float @dummy()
-
-; The call is ignored, but the top of the FP stack still needs to be
-; popped.
-define i32 @ignored_fp_call() {
-entry:
- %ignored = call float @dummy()
- ret i32 0
-}
-; CHECK-LABEL: ignored_fp_call
-; CHECK: call {{.*}} R_{{.*}} dummy
-; CHECK: fstp
-
-; The top of the FP stack is popped and subsequently used.
-define i32 @converted_fp_call() {
-entry:
- %fp = call float @dummy()
- %ret = fptosi float %fp to i32
- ret i32 %ret
-}
-; CHECK-LABEL: converted_fp_call
-; CHECK: call {{.*}} R_{{.*}} dummy
-; CHECK: fstp
-; CHECK: cvttss2si
-
-; The top of the FP stack is ultimately passed through as the return
-; value. Note: the translator could optimized by not popping and
-; re-pushing, in which case the test would need to be changed.
-define float @returned_fp_call() {
-entry:
- %fp = call float @dummy()
- ret float %fp
-}
-; CHECK-LABEL: returned_fp_call
-; CHECK: call {{.*}} R_{{.*}} dummy
-; CHECK: fstp
-; CHECK: fld
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/fpconst.pnacl.ll b/third_party/subzero/tests_lit/llvm2ice_tests/fpconst.pnacl.ll
deleted file mode 100644
index d8048d7..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/fpconst.pnacl.ll
+++ /dev/null
@@ -1,561 +0,0 @@
-; This is a smoke test for floating-point constant pooling. It tests
-; pooling of various float and double constants (including positive
-; and negative NaN) within functions and across functions. Note that
-; in LLVM bitcode, hex constants are used for an FP constant whenever
-; the constant "cannot be represented as a decimal floating point
-; number in a reasonable number of digits". See
-; http://llvm.org/docs/LangRef.html#simple-constants .
-
-; RUN: %p2i --assemble --disassemble --filetype=obj --dis-flags=-s \
-; RUN: -i %s --args -O2 --verbose none -allow-externally-defined-symbols \
-; RUN: | FileCheck %s
-; RUN: %p2i --assemble --disassemble --filetype=obj --dis-flags=-s \
-; RUN: -i %s --args -Om1 --verbose none -allow-externally-defined-symbols \
-; RUN: | FileCheck %s
-
-; RUN: %if --need allow_dump --command %p2i --assemble --disassemble \
-; RUN: --dis-flags=-s -i %s --args -O2 --verbose none \
-; RUN: -allow-externally-defined-symbols \
-; RUN: | %if --need allow_dump --command FileCheck %s
-; RUN: %if --need allow_dump --command %p2i --assemble --disassemble \
-; RUN: --dis-flags=-s -i %s --args -Om1 --verbose none \
-; RUN: -allow-externally-defined-symbols \
-; RUN: | %if --need allow_dump --command FileCheck %s
-
-@__init_array_start = internal constant [0 x i8] zeroinitializer, align 4
-@__fini_array_start = internal constant [0 x i8] zeroinitializer, align 4
-@__tls_template_start = internal constant [0 x i8] zeroinitializer, align 8
-@__tls_template_alignment = internal constant [4 x i8] c"\01\00\00\00", align 4
-
-define internal float @FpLookup1(i32 %Arg) {
-entry:
- switch i32 %Arg, label %return [
- i32 0, label %sw.bb
- i32 1, label %sw.bb1
- i32 2, label %sw.bb4
- i32 3, label %sw.bb7
- i32 -1, label %sw.bb10
- i32 -2, label %sw.bb14
- i32 -3, label %sw.bb19
- i32 10, label %sw.bb24
- i32 -10, label %sw.bb27
- i32 100, label %sw.bb30
- i32 101, label %sw.bb33
- i32 102, label %sw.bb36
- i32 103, label %sw.bb39
- i32 -101, label %sw.bb42
- i32 -102, label %sw.bb47
- i32 -103, label %sw.bb52
- i32 110, label %sw.bb57
- i32 -110, label %sw.bb60
- ]
-
-sw.bb: ; preds = %entry
- %call = call float @Dummy(i32 0)
- %add = fadd float %call, 1.000000e+00
- br label %return
-
-sw.bb1: ; preds = %entry
- %call2 = call float @Dummy(i32 1)
- %add3 = fadd float %call2, 2.000000e+00
- br label %return
-
-sw.bb4: ; preds = %entry
- %call5 = call float @Dummy(i32 2)
- %add6 = fadd float %call5, 4.000000e+00
- br label %return
-
-sw.bb7: ; preds = %entry
- %call8 = call float @Dummy(i32 3)
- %add9 = fadd float %call8, 8.000000e+00
- br label %return
-
-sw.bb10: ; preds = %entry
- %call11 = call float @Dummy(i32 -1)
- %conv13 = fadd float %call11, 5.000000e-01
- br label %return
-
-sw.bb14: ; preds = %entry
- %call15 = call float @Dummy(i32 -2)
- %conv16 = fpext float %call15 to double
- %add17 = fadd double %conv16, 0x3FD5555555555555
- %conv18 = fptrunc double %add17 to float
- br label %return
-
-sw.bb19: ; preds = %entry
- %call20 = call float @Dummy(i32 -3)
- %conv23 = fadd float %call20, 2.500000e-01
- br label %return
-
-sw.bb24: ; preds = %entry
- %call25 = call float @Dummy(i32 10)
- %add26 = fadd float %call25, 0x7FF8000000000000
- br label %return
-
-sw.bb27: ; preds = %entry
- %call28 = call float @Dummy(i32 -10)
- %add29 = fadd float %call28, 0xFFF8000000000000
- br label %return
-
-sw.bb30: ; preds = %entry
- %call31 = call float @Dummy(i32 100)
- %add32 = fadd float %call31, 1.000000e+00
- br label %return
-
-sw.bb33: ; preds = %entry
- %call34 = call float @Dummy(i32 101)
- %add35 = fadd float %call34, 2.000000e+00
- br label %return
-
-sw.bb36: ; preds = %entry
- %call37 = call float @Dummy(i32 102)
- %add38 = fadd float %call37, 4.000000e+00
- br label %return
-
-sw.bb39: ; preds = %entry
- %call40 = call float @Dummy(i32 103)
- %add41 = fadd float %call40, 8.000000e+00
- br label %return
-
-sw.bb42: ; preds = %entry
- %call43 = call float @Dummy(i32 -101)
- %conv46 = fadd float %call43, 5.000000e-01
- br label %return
-
-sw.bb47: ; preds = %entry
- %call48 = call float @Dummy(i32 -102)
- %conv49 = fpext float %call48 to double
- %add50 = fadd double %conv49, 0x3FD5555555555555
- %conv51 = fptrunc double %add50 to float
- br label %return
-
-sw.bb52: ; preds = %entry
- %call53 = call float @Dummy(i32 -103)
- %conv56 = fadd float %call53, 2.500000e-01
- br label %return
-
-sw.bb57: ; preds = %entry
- %call58 = call float @Dummy(i32 110)
- %add59 = fadd float %call58, 0x7FF8000000000000
- br label %return
-
-sw.bb60: ; preds = %entry
- %call61 = call float @Dummy(i32 -110)
- %add62 = fadd float %call61, 0xFFF8000000000000
- br label %return
-
-return: ; preds = %entry, %sw.bb60, %sw.bb57, %sw.bb52, %sw.bb47, %sw.bb42, %sw.bb39, %sw.bb36, %sw.bb33, %sw.bb30, %sw.bb27, %sw.bb24, %sw.bb19, %sw.bb14, %sw.bb10, %sw.bb7, %sw.bb4, %sw.bb1, %sw.bb
- %retval.0 = phi float [ %add62, %sw.bb60 ], [ %add59, %sw.bb57 ], [ %conv56, %sw.bb52 ], [ %conv51, %sw.bb47 ], [ %conv46, %sw.bb42 ], [ %add41, %sw.bb39 ], [ %add38, %sw.bb36 ], [ %add35, %sw.bb33 ], [ %add32, %sw.bb30 ], [ %add29, %sw.bb27 ], [ %add26, %sw.bb24 ], [ %conv23, %sw.bb19 ], [ %conv18, %sw.bb14 ], [ %conv13, %sw.bb10 ], [ %add9, %sw.bb7 ], [ %add6, %sw.bb4 ], [ %add3, %sw.bb1 ], [ %add, %sw.bb ], [ 0.000000e+00, %entry ]
- ret float %retval.0
-}
-
-declare float @Dummy(i32)
-
-define internal float @FpLookup2(i32 %Arg) {
-entry:
- switch i32 %Arg, label %return [
- i32 0, label %sw.bb
- i32 1, label %sw.bb1
- i32 2, label %sw.bb4
- i32 3, label %sw.bb7
- i32 -1, label %sw.bb10
- i32 -2, label %sw.bb14
- i32 -3, label %sw.bb19
- i32 10, label %sw.bb24
- i32 -10, label %sw.bb27
- i32 100, label %sw.bb30
- i32 101, label %sw.bb33
- i32 102, label %sw.bb36
- i32 103, label %sw.bb39
- i32 -101, label %sw.bb42
- i32 -102, label %sw.bb47
- i32 -103, label %sw.bb52
- i32 110, label %sw.bb57
- i32 -110, label %sw.bb60
- ]
-
-sw.bb: ; preds = %entry
- %call = call float @Dummy(i32 0)
- %add = fadd float %call, 1.000000e+00
- br label %return
-
-sw.bb1: ; preds = %entry
- %call2 = call float @Dummy(i32 1)
- %add3 = fadd float %call2, 2.000000e+00
- br label %return
-
-sw.bb4: ; preds = %entry
- %call5 = call float @Dummy(i32 2)
- %add6 = fadd float %call5, 4.000000e+00
- br label %return
-
-sw.bb7: ; preds = %entry
- %call8 = call float @Dummy(i32 3)
- %add9 = fadd float %call8, 8.000000e+00
- br label %return
-
-sw.bb10: ; preds = %entry
- %call11 = call float @Dummy(i32 -1)
- %conv13 = fadd float %call11, 5.000000e-01
- br label %return
-
-sw.bb14: ; preds = %entry
- %call15 = call float @Dummy(i32 -2)
- %conv16 = fpext float %call15 to double
- %add17 = fadd double %conv16, 0x3FD5555555555555
- %conv18 = fptrunc double %add17 to float
- br label %return
-
-sw.bb19: ; preds = %entry
- %call20 = call float @Dummy(i32 -3)
- %conv23 = fadd float %call20, 2.500000e-01
- br label %return
-
-sw.bb24: ; preds = %entry
- %call25 = call float @Dummy(i32 10)
- %add26 = fadd float %call25, 0x7FF8000000000000
- br label %return
-
-sw.bb27: ; preds = %entry
- %call28 = call float @Dummy(i32 -10)
- %add29 = fadd float %call28, 0xFFF8000000000000
- br label %return
-
-sw.bb30: ; preds = %entry
- %call31 = call float @Dummy(i32 100)
- %add32 = fadd float %call31, 1.000000e+00
- br label %return
-
-sw.bb33: ; preds = %entry
- %call34 = call float @Dummy(i32 101)
- %add35 = fadd float %call34, 2.000000e+00
- br label %return
-
-sw.bb36: ; preds = %entry
- %call37 = call float @Dummy(i32 102)
- %add38 = fadd float %call37, 4.000000e+00
- br label %return
-
-sw.bb39: ; preds = %entry
- %call40 = call float @Dummy(i32 103)
- %add41 = fadd float %call40, 8.000000e+00
- br label %return
-
-sw.bb42: ; preds = %entry
- %call43 = call float @Dummy(i32 -101)
- %conv46 = fadd float %call43, 5.000000e-01
- br label %return
-
-sw.bb47: ; preds = %entry
- %call48 = call float @Dummy(i32 -102)
- %conv49 = fpext float %call48 to double
- %add50 = fadd double %conv49, 0x3FD5555555555555
- %conv51 = fptrunc double %add50 to float
- br label %return
-
-sw.bb52: ; preds = %entry
- %call53 = call float @Dummy(i32 -103)
- %conv56 = fadd float %call53, 2.500000e-01
- br label %return
-
-sw.bb57: ; preds = %entry
- %call58 = call float @Dummy(i32 110)
- %add59 = fadd float %call58, 0x7FF8000000000000
- br label %return
-
-sw.bb60: ; preds = %entry
- %call61 = call float @Dummy(i32 -110)
- %add62 = fadd float %call61, 0xFFF8000000000000
- br label %return
-
-return: ; preds = %entry, %sw.bb60, %sw.bb57, %sw.bb52, %sw.bb47, %sw.bb42, %sw.bb39, %sw.bb36, %sw.bb33, %sw.bb30, %sw.bb27, %sw.bb24, %sw.bb19, %sw.bb14, %sw.bb10, %sw.bb7, %sw.bb4, %sw.bb1, %sw.bb
- %retval.0 = phi float [ %add62, %sw.bb60 ], [ %add59, %sw.bb57 ], [ %conv56, %sw.bb52 ], [ %conv51, %sw.bb47 ], [ %conv46, %sw.bb42 ], [ %add41, %sw.bb39 ], [ %add38, %sw.bb36 ], [ %add35, %sw.bb33 ], [ %add32, %sw.bb30 ], [ %add29, %sw.bb27 ], [ %add26, %sw.bb24 ], [ %conv23, %sw.bb19 ], [ %conv18, %sw.bb14 ], [ %conv13, %sw.bb10 ], [ %add9, %sw.bb7 ], [ %add6, %sw.bb4 ], [ %add3, %sw.bb1 ], [ %add, %sw.bb ], [ 0.000000e+00, %entry ]
- ret float %retval.0
-}
-
-define internal double @FpLookup3(i32 %Arg) {
-entry:
- switch i32 %Arg, label %return [
- i32 0, label %sw.bb
- i32 1, label %sw.bb1
- i32 2, label %sw.bb5
- i32 3, label %sw.bb9
- i32 -1, label %sw.bb13
- i32 -2, label %sw.bb17
- i32 -3, label %sw.bb21
- i32 10, label %sw.bb25
- i32 -10, label %sw.bb29
- i32 100, label %sw.bb33
- i32 101, label %sw.bb37
- i32 102, label %sw.bb41
- i32 103, label %sw.bb45
- i32 -101, label %sw.bb49
- i32 -102, label %sw.bb53
- i32 -103, label %sw.bb57
- i32 110, label %sw.bb61
- i32 -110, label %sw.bb65
- ]
-
-sw.bb: ; preds = %entry
- %call = call float @Dummy(i32 0)
- %add = fadd float %call, 1.000000e+00
- %conv = fpext float %add to double
- br label %return
-
-sw.bb1: ; preds = %entry
- %call2 = call float @Dummy(i32 1)
- %add3 = fadd float %call2, 2.000000e+00
- %conv4 = fpext float %add3 to double
- br label %return
-
-sw.bb5: ; preds = %entry
- %call6 = call float @Dummy(i32 2)
- %add7 = fadd float %call6, 4.000000e+00
- %conv8 = fpext float %add7 to double
- br label %return
-
-sw.bb9: ; preds = %entry
- %call10 = call float @Dummy(i32 3)
- %add11 = fadd float %call10, 8.000000e+00
- %conv12 = fpext float %add11 to double
- br label %return
-
-sw.bb13: ; preds = %entry
- %call14 = call float @Dummy(i32 -1)
- %conv15 = fpext float %call14 to double
- %add16 = fadd double %conv15, 5.000000e-01
- br label %return
-
-sw.bb17: ; preds = %entry
- %call18 = call float @Dummy(i32 -2)
- %conv19 = fpext float %call18 to double
- %add20 = fadd double %conv19, 0x3FD5555555555555
- br label %return
-
-sw.bb21: ; preds = %entry
- %call22 = call float @Dummy(i32 -3)
- %conv23 = fpext float %call22 to double
- %add24 = fadd double %conv23, 2.500000e-01
- br label %return
-
-sw.bb25: ; preds = %entry
- %call26 = call float @Dummy(i32 10)
- %conv27 = fpext float %call26 to double
- %add28 = fadd double %conv27, 0x7FF8000000000000
- br label %return
-
-sw.bb29: ; preds = %entry
- %call30 = call float @Dummy(i32 -10)
- %conv31 = fpext float %call30 to double
- %add32 = fadd double %conv31, 0xFFF8000000000000
- br label %return
-
-sw.bb33: ; preds = %entry
- %call34 = call float @Dummy(i32 100)
- %add35 = fadd float %call34, 1.000000e+00
- %conv36 = fpext float %add35 to double
- br label %return
-
-sw.bb37: ; preds = %entry
- %call38 = call float @Dummy(i32 101)
- %add39 = fadd float %call38, 2.000000e+00
- %conv40 = fpext float %add39 to double
- br label %return
-
-sw.bb41: ; preds = %entry
- %call42 = call float @Dummy(i32 102)
- %add43 = fadd float %call42, 4.000000e+00
- %conv44 = fpext float %add43 to double
- br label %return
-
-sw.bb45: ; preds = %entry
- %call46 = call float @Dummy(i32 103)
- %add47 = fadd float %call46, 8.000000e+00
- %conv48 = fpext float %add47 to double
- br label %return
-
-sw.bb49: ; preds = %entry
- %call50 = call float @Dummy(i32 -101)
- %conv51 = fpext float %call50 to double
- %add52 = fadd double %conv51, 5.000000e-01
- br label %return
-
-sw.bb53: ; preds = %entry
- %call54 = call float @Dummy(i32 -102)
- %conv55 = fpext float %call54 to double
- %add56 = fadd double %conv55, 0x3FD5555555555555
- br label %return
-
-sw.bb57: ; preds = %entry
- %call58 = call float @Dummy(i32 -103)
- %conv59 = fpext float %call58 to double
- %add60 = fadd double %conv59, 2.500000e-01
- br label %return
-
-sw.bb61: ; preds = %entry
- %call62 = call float @Dummy(i32 110)
- %conv63 = fpext float %call62 to double
- %add64 = fadd double %conv63, 0x7FF8000000000000
- br label %return
-
-sw.bb65: ; preds = %entry
- %call66 = call float @Dummy(i32 -110)
- %conv67 = fpext float %call66 to double
- %add68 = fadd double %conv67, 0xFFF8000000000000
- br label %return
-
-return: ; preds = %entry, %sw.bb65, %sw.bb61, %sw.bb57, %sw.bb53, %sw.bb49, %sw.bb45, %sw.bb41, %sw.bb37, %sw.bb33, %sw.bb29, %sw.bb25, %sw.bb21, %sw.bb17, %sw.bb13, %sw.bb9, %sw.bb5, %sw.bb1, %sw.bb
- %retval.0 = phi double [ %add68, %sw.bb65 ], [ %add64, %sw.bb61 ], [ %add60, %sw.bb57 ], [ %add56, %sw.bb53 ], [ %add52, %sw.bb49 ], [ %conv48, %sw.bb45 ], [ %conv44, %sw.bb41 ], [ %conv40, %sw.bb37 ], [ %conv36, %sw.bb33 ], [ %add32, %sw.bb29 ], [ %add28, %sw.bb25 ], [ %add24, %sw.bb21 ], [ %add20, %sw.bb17 ], [ %add16, %sw.bb13 ], [ %conv12, %sw.bb9 ], [ %conv8, %sw.bb5 ], [ %conv4, %sw.bb1 ], [ %conv, %sw.bb ], [ 0.000000e+00, %entry ]
- ret double %retval.0
-}
-
-define internal double @FpLookup4(i32 %Arg) {
-entry:
- switch i32 %Arg, label %return [
- i32 0, label %sw.bb
- i32 1, label %sw.bb1
- i32 2, label %sw.bb5
- i32 3, label %sw.bb9
- i32 -1, label %sw.bb13
- i32 -2, label %sw.bb17
- i32 -3, label %sw.bb21
- i32 10, label %sw.bb25
- i32 -10, label %sw.bb29
- i32 100, label %sw.bb33
- i32 101, label %sw.bb37
- i32 102, label %sw.bb41
- i32 103, label %sw.bb45
- i32 -101, label %sw.bb49
- i32 -102, label %sw.bb53
- i32 -103, label %sw.bb57
- i32 110, label %sw.bb61
- i32 -110, label %sw.bb65
- ]
-
-sw.bb: ; preds = %entry
- %call = call float @Dummy(i32 0)
- %add = fadd float %call, 1.000000e+00
- %conv = fpext float %add to double
- br label %return
-
-sw.bb1: ; preds = %entry
- %call2 = call float @Dummy(i32 1)
- %add3 = fadd float %call2, 2.000000e+00
- %conv4 = fpext float %add3 to double
- br label %return
-
-sw.bb5: ; preds = %entry
- %call6 = call float @Dummy(i32 2)
- %add7 = fadd float %call6, 4.000000e+00
- %conv8 = fpext float %add7 to double
- br label %return
-
-sw.bb9: ; preds = %entry
- %call10 = call float @Dummy(i32 3)
- %add11 = fadd float %call10, 8.000000e+00
- %conv12 = fpext float %add11 to double
- br label %return
-
-sw.bb13: ; preds = %entry
- %call14 = call float @Dummy(i32 -1)
- %conv15 = fpext float %call14 to double
- %add16 = fadd double %conv15, 5.000000e-01
- br label %return
-
-sw.bb17: ; preds = %entry
- %call18 = call float @Dummy(i32 -2)
- %conv19 = fpext float %call18 to double
- %add20 = fadd double %conv19, 0x3FD5555555555555
- br label %return
-
-sw.bb21: ; preds = %entry
- %call22 = call float @Dummy(i32 -3)
- %conv23 = fpext float %call22 to double
- %add24 = fadd double %conv23, 2.500000e-01
- br label %return
-
-sw.bb25: ; preds = %entry
- %call26 = call float @Dummy(i32 10)
- %conv27 = fpext float %call26 to double
- %add28 = fadd double %conv27, 0x7FF8000000000000
- br label %return
-
-sw.bb29: ; preds = %entry
- %call30 = call float @Dummy(i32 -10)
- %conv31 = fpext float %call30 to double
- %add32 = fadd double %conv31, 0xFFF8000000000000
- br label %return
-
-sw.bb33: ; preds = %entry
- %call34 = call float @Dummy(i32 100)
- %add35 = fadd float %call34, 1.000000e+00
- %conv36 = fpext float %add35 to double
- br label %return
-
-sw.bb37: ; preds = %entry
- %call38 = call float @Dummy(i32 101)
- %add39 = fadd float %call38, 2.000000e+00
- %conv40 = fpext float %add39 to double
- br label %return
-
-sw.bb41: ; preds = %entry
- %call42 = call float @Dummy(i32 102)
- %add43 = fadd float %call42, 4.000000e+00
- %conv44 = fpext float %add43 to double
- br label %return
-
-sw.bb45: ; preds = %entry
- %call46 = call float @Dummy(i32 103)
- %add47 = fadd float %call46, 8.000000e+00
- %conv48 = fpext float %add47 to double
- br label %return
-
-sw.bb49: ; preds = %entry
- %call50 = call float @Dummy(i32 -101)
- %conv51 = fpext float %call50 to double
- %add52 = fadd double %conv51, 5.000000e-01
- br label %return
-
-sw.bb53: ; preds = %entry
- %call54 = call float @Dummy(i32 -102)
- %conv55 = fpext float %call54 to double
- %add56 = fadd double %conv55, 0x3FD5555555555555
- br label %return
-
-sw.bb57: ; preds = %entry
- %call58 = call float @Dummy(i32 -103)
- %conv59 = fpext float %call58 to double
- %add60 = fadd double %conv59, 2.500000e-01
- br label %return
-
-sw.bb61: ; preds = %entry
- %call62 = call float @Dummy(i32 110)
- %conv63 = fpext float %call62 to double
- %add64 = fadd double %conv63, 0x7FF8000000000000
- br label %return
-
-sw.bb65: ; preds = %entry
- %call66 = call float @Dummy(i32 -110)
- %conv67 = fpext float %call66 to double
- %add68 = fadd double %conv67, 0xFFF8000000000000
- br label %return
-
-return: ; preds = %entry, %sw.bb65, %sw.bb61, %sw.bb57, %sw.bb53, %sw.bb49, %sw.bb45, %sw.bb41, %sw.bb37, %sw.bb33, %sw.bb29, %sw.bb25, %sw.bb21, %sw.bb17, %sw.bb13, %sw.bb9, %sw.bb5, %sw.bb1, %sw.bb
- %retval.0 = phi double [ %add68, %sw.bb65 ], [ %add64, %sw.bb61 ], [ %add60, %sw.bb57 ], [ %add56, %sw.bb53 ], [ %add52, %sw.bb49 ], [ %conv48, %sw.bb45 ], [ %conv44, %sw.bb41 ], [ %conv40, %sw.bb37 ], [ %conv36, %sw.bb33 ], [ %add32, %sw.bb29 ], [ %add28, %sw.bb25 ], [ %add24, %sw.bb21 ], [ %add20, %sw.bb17 ], [ %add16, %sw.bb13 ], [ %conv12, %sw.bb9 ], [ %conv8, %sw.bb5 ], [ %conv4, %sw.bb1 ], [ %conv, %sw.bb ], [ 0.000000e+00, %entry ]
- ret double %retval.0
-}
-
-; The FP constant pool entries for each type are dumped in some
-; implementation-dependent order. So for the purposes of lit, we just
-; pick one value for each type, and make sure it appears exactly once.
-
-; Check for float 0.5
-; CHECK-LABEL: .rodata.cst4
-; CHECK: 0000003f
-; CHECK-NOT: 0000003f
-
-; Check for double 0.5
-; CHECK-LABEL: .rodata.cst8
-; CHECK: 00000000 0000e03f
-; CHECK-NOT: 00000000 0000e03f
-; CHECK-LABEL: .text
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/function_aligned.ll b/third_party/subzero/tests_lit/llvm2ice_tests/function_aligned.ll
deleted file mode 100644
index b38ea19..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/function_aligned.ll
+++ /dev/null
@@ -1,43 +0,0 @@
-; Test that functions are aligned to the NaCl bundle alignment.
-; We could be smarter and only do this for indirect call targets
-; but typically you want to align functions anyway.
-; Also, we are currently using hlts for non-executable padding.
-
-; RUN: %p2i --filetype=obj --disassemble -i %s --args -O2 | FileCheck %s
-
-; RUN: %if --need=target_ARM32 \
-; RUN: --command %p2i --filetype=obj \
-; RUN: --disassemble --target arm32 -i %s --args -O2 \
-; RUN: | %if --need=target_ARM32 \
-; RUN: --command FileCheck --check-prefix ARM32 %s
-; RUN: %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command %p2i --filetype=asm --assemble \
-; RUN: --disassemble --target mips32 -i %s --args -O2 \
-; RUN: | %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command FileCheck --check-prefix MIPS32 %s
-
-define internal void @foo() {
- ret void
-}
-; CHECK-LABEL: foo
-; CHECK-NEXT: 0: {{.*}} ret
-; CHECK-NEXT: 1: {{.*}} hlt
-; ARM32-LABEL: foo
-; ARM32-NEXT: 0: {{.*}} bx lr
-; ARM32-NEXT: 4: e7fedef0 udf
-; ARM32-NEXT: 8: e7fedef0 udf
-; ARM32-NEXT: c: e7fedef0 udf
-; MIPS32-LABEL: foo
-; MIPS32: 0: {{.*}} jr ra
-; MIPS32-NEXT: 4: {{.*}} nop
-
-define internal void @bar() {
- ret void
-}
-; CHECK-LABEL: bar
-; CHECK-NEXT: 20: {{.*}} ret
-; ARM32-LABEL: bar
-; ARM32-NEXT: 10: {{.*}} bx lr
-; MIPS32-LABEL: bar
-; MIPS32: 10: {{.*}} jr ra
-; MIPS32-NEXT: 14: {{.*}} nop
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/fused-alloca-arg.ll b/third_party/subzero/tests_lit/llvm2ice_tests/fused-alloca-arg.ll
deleted file mode 100644
index b51a2cf..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/fused-alloca-arg.ll
+++ /dev/null
@@ -1,103 +0,0 @@
-; This is a basic test of the alloca instruction and a call.
-
-; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
-; RUN: --target x8632 -i %s --args -O2 -allow-externally-defined-symbols \
-; RUN: | %if --need=target_X8632 --command FileCheck %s
-
-; RUN: %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command %p2i --filetype=asm --assemble --disassemble --target \
-; RUN: mips32 -i %s --args -O2 -allow-externally-defined-symbols \
-; RUN: | %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command FileCheck --check-prefix MIPS32 %s
-
-declare void @copy(i32 %arg1, i8* %arr1, i8* %arr2, i8* %arr3, i8* %arr4);
-
-; Test that alloca base addresses get passed correctly to functions.
-define internal void @caller1(i32 %arg) {
-entry:
- %a1 = alloca i8, i32 32, align 4
- %p1 = bitcast i8* %a1 to i32*
- store i32 %arg, i32* %p1, align 1
- call void @copy(i32 %arg, i8* %a1, i8* %a1, i8* %a1, i8* %a1)
- ret void
-}
-
-; CHECK-LABEL: caller1
-; CHECK-NEXT: sub esp,0x4c
-; CHECK-NEXT: mov eax,DWORD PTR [esp+0x50]
-; CHECK-NEXT: mov DWORD PTR [esp+0x20],eax
-; CHECK-NEXT: mov DWORD PTR [esp],eax
-; CHECK-NEXT: lea eax,[esp+0x20]
-; CHECK-NEXT: mov DWORD PTR [esp+0x4],eax
-; CHECK-NEXT: lea eax,[esp+0x20]
-; CHECK-NEXT: mov DWORD PTR [esp+0x8],eax
-; CHECK-NEXT: lea eax,[esp+0x20]
-; CHECK-NEXT: mov DWORD PTR [esp+0xc],eax
-; CHECK-NEXT: lea eax,[esp+0x20]
-; CHECK-NEXT: mov DWORD PTR [esp+0x10],eax
-; CHECK-NEXT: call
-; CHECK-NEXT: add esp,0x4c
-; CHECK-NEXT: ret
-; MIPS32-LABEL: caller1
-; MIPS32: addiu sp,sp,{{.*}}
-; MIPS32: sw ra,{{.*}}(sp)
-; MIPS32: move v0,a0
-; MIPS32: sw v0,{{.*}}(sp)
-; MIPS32: addiu v0,sp,32
-; MIPS32: sw v0,{{.*}}(sp)
-; MIPS32: addiu a1,sp,32
-; MIPS32: addiu a2,sp,32
-; MIPS32: addiu a3,sp,32
-; MIPS32: jal
-; MIPS32: nop
-; MIPS32: lw ra,{{.*}}(sp)
-; MIPS32: addiu sp,sp,{{.*}}
-; MIPS32: jr ra
-
-; Test that alloca base addresses get passed correctly to functions.
-define internal void @caller2(i32 %arg) {
-entry:
- %a1 = alloca i8, i32 32, align 4
- %a2 = alloca i8, i32 32, align 4
- %p1 = bitcast i8* %a1 to i32*
- %p2 = bitcast i8* %a2 to i32*
- store i32 %arg, i32* %p1, align 1
- store i32 %arg, i32* %p2, align 1
- call void @copy(i32 %arg, i8* %a1, i8* %a2, i8* %a1, i8* %a2)
- ret void
-}
-
-; CHECK-LABEL: caller2
-; CHECK-NEXT: sub esp,0x6c
-; CHECK-NEXT: mov eax,DWORD PTR [esp+0x70]
-; CHECK-NEXT: mov DWORD PTR [esp+0x20],eax
-; CHECK-NEXT: mov DWORD PTR [esp+0x40],eax
-; CHECK-NEXT: mov DWORD PTR [esp],eax
-; CHECK-NEXT: lea eax,[esp+0x20]
-; CHECK-NEXT: mov DWORD PTR [esp+0x4],eax
-; CHECK-NEXT: lea eax,[esp+0x40]
-; CHECK-NEXT: mov DWORD PTR [esp+0x8],eax
-; CHECK-NEXT: lea eax,[esp+0x20]
-; CHECK-NEXT: mov DWORD PTR [esp+0xc],eax
-; CHECK-NEXT: lea eax,[esp+0x40]
-; CHECK-NEXT: mov DWORD PTR [esp+0x10],eax
-; CHECK-NEXT: call
-; CHECK-NEXT: add esp,0x6c
-; CHECK-NEXT: ret
-; MIPS32-LABEL: caller2
-; MIPS32: addiu sp,sp,{{.*}}
-; MIPS32: sw ra,{{.*}}(sp)
-; MIPS32: move v0,a0
-; MIPS32: sw v0,{{.*}}(sp)
-; MIPS32: move v0,a0
-; MIPS32: sw v0,{{.*}}(sp)
-; MIPS32: addiu v0,sp,64
-; MIPS32: sw v0,{{.*}}(sp)
-; MIPS32: addiu a1,sp,32
-; MIPS32: addiu a2,sp,64
-; MIPS32: addiu a3,sp,32
-; MIPS32: jal
-; MIPS32: nop
-; MIPS32: lw ra,{{.*}}(sp)
-; MIPS32: addiu sp,sp,{{.*}}
-; MIPS32: jr ra
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/fused-alloca.ll b/third_party/subzero/tests_lit/llvm2ice_tests/fused-alloca.ll
deleted file mode 100644
index 2c6992a..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/fused-alloca.ll
+++ /dev/null
@@ -1,230 +0,0 @@
-; This is a basic test of the alloca instruction.
-
-; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
-; RUN: --target x8632 -i %s --args -O2 -allow-externally-defined-symbols \
-; RUN: | %if --need=target_X8632 --command FileCheck %s
-
-; RUN: %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command %p2i --filetype=asm --assemble --disassemble --target \
-; RUN: mips32 -i %s --args -O2 -allow-externally-defined-symbols \
-; RUN: | %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command FileCheck --check-prefix MIPS32 %s
-
-; Test that a sequence of allocas with less than stack alignment get fused.
-define internal void @fused_small_align(i32 %arg) {
-entry:
- %a1 = alloca i8, i32 8, align 4
- %a2 = alloca i8, i32 12, align 4
- %a3 = alloca i8, i32 16, align 8
- %p1 = bitcast i8* %a1 to i32*
- %p2 = bitcast i8* %a2 to i32*
- %p3 = bitcast i8* %a3 to i32*
- store i32 %arg, i32* %p1, align 1
- store i32 %arg, i32* %p2, align 1
- store i32 %arg, i32* %p3, align 1
- ret void
-}
-; CHECK-LABEL: fused_small_align
-; CHECK-NEXT: sub esp,0x3c
-; CHECK-NEXT: mov eax,DWORD PTR [esp+0x40]
-; CHECK-NEXT: mov DWORD PTR [esp+0x10],eax
-; CHECK-NEXT: mov DWORD PTR [esp+0x18],eax
-; CHECK-NEXT: mov DWORD PTR [esp],eax
-; CHECK-NEXT: add esp,0x3c
-; MIPS32-LABEL: fused_small_align
-; MIPS32: addiu sp,sp,{{.*}}
-; MIPS32: move v0,a0
-; MIPS32: sw v0,{{.*}}(sp)
-; MIPS32: move v0,a0
-; MIPS32: sw v0,{{.*}}(sp)
-; MIPS32: sw a0,{{.*}}(sp)
-; MIPS32: addiu sp,sp,{{.*}}
-
-; Test that a sequence of allocas with greater than stack alignment get fused.
-define internal void @fused_large_align(i32 %arg) {
-entry:
- %a1 = alloca i8, i32 8, align 32
- %a2 = alloca i8, i32 12, align 64
- %a3 = alloca i8, i32 16, align 32
- %p1 = bitcast i8* %a1 to i32*
- %p2 = bitcast i8* %a2 to i32*
- %p3 = bitcast i8* %a3 to i32*
- store i32 %arg, i32* %p1, align 1
- store i32 %arg, i32* %p2, align 1
- store i32 %arg, i32* %p3, align 1
- ret void
-}
-; CHECK-LABEL: fused_large_align
-; CHECK-NEXT: push ebp
-; CHECK-NEXT: mov ebp,esp
-; CHECK-NEXT: sub esp,0xb8
-; CHECK-NEXT: and esp,0xffffffc0
-; CHECK-NEXT: mov eax,DWORD PTR [ebp+0x8]
-; CHECK-NEXT: mov DWORD PTR [esp+0x40],eax
-; CHECK-NEXT: mov DWORD PTR [esp],eax
-; CHECK-NEXT: mov DWORD PTR [esp+0x60],eax
-; CHECK-NEXT: mov esp,ebp
-; CHECK-NEXT: pop ebp
-; MIPS32-LABEL: fused_large_align
-; MIPS32: addiu sp,sp,{{.*}}
-; MIPS32: sw s8,{{.*}}(sp)
-; MIPS32: move s8,sp
-; MIPS32: move v0,a0
-; MIPS32: sw v0,{{.*}}(sp)
-; MIPS32: move v0,a0
-; MIPS32: sw v0,{{.*}}(sp)
-; MIPS32: sw a0,{{.*}}(sp)
-; MIPS32: move sp,s8
-; MIPS32: lw s8,{{.*}}(sp)
-; MIPS32: addiu sp,sp,{{.*}}
-
-; Test that an interior pointer into a rematerializable variable is also
-; rematerializable, and test that it is detected even when the use appears
-; syntactically before the definition. Test that it is folded into mem
-; operands, and also rematerializable through an lea instruction for direct use.
-define internal i32 @fused_derived(i32 %arg) {
-entry:
- %a1 = alloca i8, i32 128, align 4
- %a2 = alloca i8, i32 128, align 4
- %a3 = alloca i8, i32 128, align 4
- br label %block2
-block1:
- %a2_i32 = bitcast i8* %a2 to i32*
- store i32 %arg, i32* %a2_i32, align 1
- store i32 %arg, i32* %derived, align 1
- ret i32 %retval
-block2:
-; The following are all rematerializable variables deriving from %a2.
- %p2 = ptrtoint i8* %a2 to i32
- %d = add i32 %p2, 12
- %retval = add i32 %p2, 1
- %derived = inttoptr i32 %d to i32*
- br label %block1
-}
-; CHECK-LABEL: fused_derived
-; CHECK-NEXT: sub esp,0x18c
-; CHECK-NEXT: mov [[ARG:e..]],DWORD PTR [esp+0x190]
-; CHECK-NEXT: jmp
-; CHECK-NEXT: mov DWORD PTR [esp+0x80],[[ARG]]
-; CHECK-NEXT: mov DWORD PTR [esp+0x8c],[[ARG]]
-; CHECK-NEXT: lea eax,[esp+0x81]
-; CHECK-NEXT: add esp,0x18c
-; CHECK-NEXT: ret
-; MIPS32-LABEL: fused_derived
-; MIPS32: addiu sp,sp,{{.*}}
-; MIPS32: b
-; MIPS32: move v0,a0
-; MIPS32: sw v0,{{.*}}(sp)
-; MIPS32: sw a0,{{.*}}(sp)
-; MIPS32: addiu v0,sp,129
-; MIPS32: addiu sp,sp,{{.*}}
-
-; Test that a fixed alloca gets referenced by the frame pointer.
-define internal void @fused_small_align_with_dynamic(i32 %arg) {
-entry:
- %a1 = alloca i8, i32 8, align 16
- br label %next
-next:
- %a2 = alloca i8, i32 12, align 1
- %a3 = alloca i8, i32 16, align 1
- %p1 = bitcast i8* %a1 to i32*
- %p2 = bitcast i8* %a2 to i32*
- %p3 = bitcast i8* %a3 to i32*
- store i32 %arg, i32* %p1, align 1
- store i32 %arg, i32* %p2, align 1
- store i32 %arg, i32* %p3, align 1
- ret void
-}
-; CHECK-LABEL: fused_small_align_with_dynamic
-; CHECK-NEXT: push ebp
-; CHECK-NEXT: mov ebp,esp
-; CHECK-NEXT: sub esp,0x18
-; CHECK-NEXT: mov eax,DWORD PTR [ebp+0x8]
-; CHECK-NEXT: sub esp,0x10
-; CHECK-NEXT: mov ecx,esp
-; CHECK-NEXT: sub esp,0x10
-; CHECK-NEXT: mov edx,esp
-; CHECK-NEXT: mov DWORD PTR [ebp-0x18],eax
-; CHECK-NEXT: mov DWORD PTR [ecx],eax
-; CHECK-NEXT: mov DWORD PTR [edx],eax
-; CHECK-NEXT: mov esp,ebp
-; CHECK-NEXT: pop ebp
-; MIPS32-LABEL: fused_small_align_with_dynamic
-; MIPS32: addiu sp,sp,{{.*}}
-; MIPS32: sw s8,{{.*}}(sp)
-; MIPS32: move s8,sp
-; MIPS32: addiu v0,sp,0
-; MIPS32: addiu v1,sp,16
-; MIPS32: move a1,a0
-; MIPS32: sw a1,32(s8)
-; MIPS32: move a1,a0
-; MIPS32: sw a1,0(v0)
-; MIPS32: sw a0,0(v1)
-; MIPS32: move sp,s8
-; MIPS32: lw s8,{{.*}}(sp)
-; MIPS32: addiu sp,sp,{{.*}}
-
-; Test that a sequence with greater than stack alignment and dynamic size
-; get folded and referenced correctly;
-
-define internal void @fused_large_align_with_dynamic(i32 %arg) {
-entry:
- %a1 = alloca i8, i32 8, align 32
- %a2 = alloca i8, i32 12, align 32
- %a3 = alloca i8, i32 16, align 1
- %a4 = alloca i8, i32 16, align 1
- br label %next
-next:
- %a5 = alloca i8, i32 16, align 1
- %p1 = bitcast i8* %a1 to i32*
- %p2 = bitcast i8* %a2 to i32*
- %p3 = bitcast i8* %a3 to i32*
- %p4 = bitcast i8* %a4 to i32*
- %p5 = bitcast i8* %a5 to i32*
- store i32 %arg, i32* %p1, align 1
- store i32 %arg, i32* %p2, align 1
- store i32 %arg, i32* %p3, align 1
- store i32 %arg, i32* %p4, align 1
- store i32 %arg, i32* %p5, align 1
- ret void
-}
-; CHECK-LABEL: fused_large_align_with_dynamic
-; CHECK-NEXT: push ebx
-; CHECK-NEXT: push ebp
-; CHECK-NEXT: mov ebp,esp
-; CHECK-NEXT: sub esp,0x24
-; CHECK-NEXT: mov eax,DWORD PTR [ebp+0xc]
-; CHECK-NEXT: and esp,0xffffffe0
-; CHECK-NEXT: sub esp,0x40
-; CHECK-NEXT: mov ecx,esp
-; CHECK-NEXT: mov edx,ecx
-; CHECK-NEXT: add ecx,0x20
-; CHECK-NEXT: add edx,0x0
-; CHECK-NEXT: sub esp,0x10
-; CHECK-NEXT: mov ebx,esp
-; CHECK-NEXT: mov DWORD PTR [edx],eax
-; CHECK-NEXT: mov DWORD PTR [ecx],eax
-; CHECK-NEXT: mov DWORD PTR [ebp-0x14],eax
-; CHECK-NEXT: mov DWORD PTR [ebp-0x24],eax
-; CHECK-NEXT: mov DWORD PTR [ebx],eax
-; CHECK-NEXT: mov esp,ebp
-; CHECK-NEXT: pop ebp
-; MIPS32-LABEL: fused_large_align_with_dynamic
-; MIPS32: addiu sp,sp,{{.*}}
-; MIPS32: sw s8,{{.*}}(sp)
-; MIPS32: move s8,sp
-; MIPS32: addiu v0,sp,0
-; MIPS32: addiu v1,sp,64
-; MIPS32: move a1,v0
-; MIPS32: move a2,a0
-; MIPS32: sw a2,0(a1)
-; MIPS32: move a1,a0
-; MIPS32: sw a1,32(v0)
-; MIPS32: move v0,a0
-; MIPS32: sw v0,80(s8)
-; MIPS32: move v0,a0
-; MIPS32: sw v0,96(s8)
-; MIPS32: sw a0,0(v1)
-; MIPS32: move sp,s8
-; MIPS32: lw s8,{{.*}}(sp)
-; MIPS32: addiu sp,sp,{{.*}}
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/globalinit.pnacl.ll b/third_party/subzero/tests_lit/llvm2ice_tests/globalinit.pnacl.ll
deleted file mode 100644
index 4495eaa..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/globalinit.pnacl.ll
+++ /dev/null
@@ -1,253 +0,0 @@
-; Test of global initializers.
-
-; REQUIRES: allow_dump
-
-; Test initializers with -filetype=asm.
-; RUN: %if --need=target_X8632 --command %p2i --filetype=asm --target x8632 \
-; RUN: -i %s --args -O2 -allow-externally-defined-symbols \
-; RUN: | %if --need=target_X8632 --command FileCheck %s
-
-; RUN: %if --need=target_ARM32 --command %p2i --filetype=asm --target arm32 \
-; RUN: -i %s --args -O2 \
-; RUN: -allow-externally-defined-symbols \
-; RUN: | %if --need=target_ARM32 --command FileCheck %s
-
-; Test instructions for materializing addresses.
-; RUN: %if --need=target_X8632 --command %p2i --filetype=asm --target x8632 \
-; RUN: -i %s --args -O2 -allow-externally-defined-symbols \
-; RUN: | %if --need=target_X8632 --command FileCheck %s --check-prefix=X8632
-
-; Test instructions with -filetype=obj and try to cross reference instructions
-; w/ the symbol table.
-; RUN: %if --need=target_X8632 --command %p2i --assemble --disassemble \
-; RUN: --target x8632 -i %s --args --verbose none \
-; RUN: -allow-externally-defined-symbols \
-; RUN: | %if --need=target_X8632 --command FileCheck --check-prefix=IAS %s
-
-; RUN: %if --need=target_X8632 --command %p2i --assemble --disassemble \
-; RUN: --dis-flags=-t --target x8632 -i %s --args --verbose none \
-; RUN: -allow-externally-defined-symbols \
-; RUN: | %if --need=target_X8632 --command FileCheck --check-prefix=SYMTAB %s
-
-; This is not really IAS, but we can switch when that is implemented.
-; For now we can at least see the instructions / relocations.
-; RUN: %if --need=target_ARM32 --command %p2i --filetype=asm --assemble \
-; RUN: --disassemble --target arm32 -i %s \
-; RUN: --args --verbose none \
-; RUN: -allow-externally-defined-symbols \
-; RUN: | %if --need=target_ARM32 --command FileCheck \
-; RUN: --check-prefix=IASARM32 %s
-
-; RUN: %if --need=target_ARM32 --command %p2i --filetype=asm --assemble \
-; RUN: --disassemble --dis-flags=-t --target arm32 -i %s \
-; RUN: --args --verbose none \
-; RUN: -allow-externally-defined-symbols \
-; RUN: | %if --need=target_ARM32 --command FileCheck --check-prefix=SYMTAB %s
-
-; RUN: %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command %p2i --filetype=asm --assemble --disassemble --target \
-; RUN: mips32 -i %s --args -O2 -allow-externally-defined-symbols \
-; RUN: | %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command FileCheck --check-prefix=IASMIPS32 %s
-
-; RUN: %if --need=target_MIPS32 --need=allow_dump --command %p2i \
-; RUN: --filetype=asm --assemble --disassemble --dis-flags=-t \
-; RUN: --target mips32 -i %s --args --verbose none \
-; RUN: -allow-externally-defined-symbols \
-; RUN: | %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command FileCheck --check-prefix=SYMTAB %s
-
-define internal i32 @main(i32 %argc, i32 %argv) {
-entry:
- %expanded1 = ptrtoint [4 x i8]* @PrimitiveInit to i32
- call void @use(i32 %expanded1)
- %expanded3 = ptrtoint [4 x i8]* @PrimitiveInitConst to i32
- call void @use(i32 %expanded3)
- %expanded5 = ptrtoint [4 x i8]* @PrimitiveInitStatic to i32
- call void @use(i32 %expanded5)
- %expanded7 = ptrtoint [4 x i8]* @PrimitiveUninit to i32
- call void @use(i32 %expanded7)
- %expanded9 = ptrtoint [20 x i8]* @ArrayInit to i32
- call void @use(i32 %expanded9)
- %expanded11 = ptrtoint [40 x i8]* @ArrayInitPartial to i32
- call void @use(i32 %expanded11)
- %expanded13 = ptrtoint [20 x i8]* @ArrayUninit to i32
- call void @use(i32 %expanded13)
- ret i32 0
-}
-; X8632-LABEL: main
-; X8632: movl $PrimitiveInit,
-; X8632: movl $PrimitiveInitConst,
-; X8632: movl $PrimitiveInitStatic,
-; X8632: movl $PrimitiveUninit,
-; X8632: movl $ArrayInit,
-; X8632: movl $ArrayInitPartial,
-; X8632: movl $ArrayUninit,
-
-; objdump does not indicate what symbol the mov/relocation applies to
-; so we grep for "mov {{.*}}, OFFSET, sec", along with
-; "OFFSET {{.*}} sec {{.*}} symbol" in the symbol table as a sanity check.
-; NOTE: The symbol table sorting has no relation to the code's references.
-; IAS-LABEL: main
-; SYMTAB-LABEL: SYMBOL TABLE
-
-; SYMTAB-DAG: 00000000 {{.*}} .data {{.*}} PrimitiveInit
-; IAS: mov {{.*}},0x0 {{.*}} .data
-; IAS: call
-; IASARM32: movw {{.*}} PrimitiveInit
-; IASARM32: movt {{.*}} PrimitiveInit
-; IASARM32: bl
-; IASMIPS32: lui {{.*}} PrimitiveInit
-; IASMIPS32: addiu {{.*}} PrimitiveInit
-; IASMIPS32: jal
-
-; SYMTAB-DAG: 00000000 {{.*}} .rodata {{.*}} PrimitiveInitConst
-; IAS: mov {{.*}},0x0 {{.*}} .rodata
-; IAS: call
-; IASARM32: movw {{.*}} PrimitiveInitConst
-; IASARM32: movt {{.*}} PrimitiveInitConst
-; IASARM32: bl
-; IASMIPS32: lui {{.*}} PrimitiveInitConst
-; IASMIPS32: addiu {{.*}} PrimitiveInitConst
-; IASMIPS32: jal
-
-; SYMTAB-DAG: 00000000 {{.*}} .bss {{.*}} PrimitiveInitStatic
-; IAS: mov {{.*}},0x0 {{.*}} .bss
-; IAS: call
-; IASARM32: movw {{.*}} PrimitiveInitStatic
-; IASARM32: movt {{.*}} PrimitiveInitStatic
-; IASARM32: bl
-; IASMIPS32: lui {{.*}} PrimitiveInitStatic
-; IASMIPS32: addiu {{.*}} PrimitiveInitStatic
-; IASMIPS32: jal
-
-; SYMTAB-DAG: 00000004 {{.*}} .bss {{.*}} PrimitiveUninit
-; IAS: mov {{.*}},0x4 {{.*}} .bss
-; IAS: call
-; IASARM32: movw {{.*}} PrimitiveUninit
-; IASARM32: movt {{.*}} PrimitiveUninit
-; IASARM32: bl
-; IASMIPS32: lui {{.*}} PrimitiveUninit
-; IASMIPS32: addiu {{.*}} PrimitiveUninit
-; IASMIPS32: jal
-
-; SYMTAB-DAG: 00000004{{.*}}.data{{.*}}ArrayInit
-; IAS: mov {{.*}},0x4 {{.*}} .data
-; IAS: call
-; IASARM32: movw {{.*}} ArrayInit
-; IASARM32: movt {{.*}} ArrayInit
-; IASARM32: bl
-; IASMIPS32: lui {{.*}} ArrayInit
-; IASMIPS32: addiu {{.*}} ArrayInit
-; IASMIPS32: jal
-
-; SYMTAB-DAG: 00000018 {{.*}} .data {{.*}} ArrayInitPartial
-; IAS: mov {{.*}},0x18 {{.*}} .data
-; IAS: call
-; IASARM32: movw {{.*}} ArrayInitPartial
-; IASARM32: movt {{.*}} ArrayInitPartial
-; IASARM32: bl
-; IASMIPS32: lui {{.*}} ArrayInitPartial
-; IASMIPS32: addiu {{.*}} ArrayInitPartial
-; IASMIPS32: jal
-
-; SYMTAB-DAG: 00000008 {{.*}} .bss {{.*}} ArrayUninit
-; IAS: mov {{.*}},0x8 {{.*}} .bss
-; IAS: call
-; IASARM32: movw {{.*}} ArrayUninit
-; IASARM32: movt {{.*}} ArrayUninit
-; IASARM32: bl
-; IASMIPS32: lui {{.*}} ArrayUninit
-; IASMIPS32: addiu {{.*}} ArrayUninit
-; IASMIPS32: jal
-
-declare void @use(i32)
-
-define internal i32 @nacl_tp_tdb_offset(i32 %__0) {
-entry:
- ret i32 0
-}
-
-define internal i32 @nacl_tp_tls_offset(i32 %size) {
-entry:
- %result = sub i32 0, %size
- ret i32 %result
-}
-
-
-@PrimitiveInit = internal global [4 x i8] c"\1B\00\00\00", align 4
-; CHECK: .type PrimitiveInit,%object
-; CHECK-NEXT: .section .data,"aw",%progbits
-; CHECK-NEXT: .p2align 2
-; CHECK-NEXT: PrimitiveInit:
-; CHECK-NEXT: .byte
-; CHECK: .size PrimitiveInit, 4
-
-@PrimitiveInitConst = internal constant [4 x i8] c"\0D\00\00\00", align 4
-; CHECK: .type PrimitiveInitConst,%object
-; CHECK-NEXT: .section .rodata,"a",%progbits
-; CHECK-NEXT: .p2align 2
-; CHECK-NEXT: PrimitiveInitConst:
-; CHECK-NEXT: .byte
-; CHECK: .size PrimitiveInitConst, 4
-
-@ArrayInit = internal global [20 x i8] c"\0A\00\00\00\14\00\00\00\1E\00\00\00(\00\00\002\00\00\00", align 4
-; CHECK: .type ArrayInit,%object
-; CHECK-NEXT: .section .data,"aw",%progbits
-; CHECK-NEXT: .p2align 2
-; CHECK-NEXT: ArrayInit:
-; CHECK-NEXT: .byte
-; CHECK: .size ArrayInit, 20
-
-@ArrayInitPartial = internal global [40 x i8] c"<\00\00\00F\00\00\00P\00\00\00Z\00\00\00d\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00", align 4
-; CHECK: .type ArrayInitPartial,%object
-; CHECK-NEXT: .section .data,"aw",%progbits
-; CHECK-NEXT: .p2align 2
-; CHECK-NEXT: ArrayInitPartial:
-; CHECK-NEXT: .byte
-; CHECK: .size ArrayInitPartial, 40
-
-@PrimitiveInitStatic = internal global [4 x i8] zeroinitializer, align 4
-; CHECK: .type PrimitiveInitStatic,%object
-; CHECK-NEXT: .section .bss,"aw",%nobits
-; CHECK-NEXT: .p2align 2
-; CHECK-NEXT: PrimitiveInitStatic:
-; CHECK-NEXT: .zero 4
-; CHECK-NEXT: .size PrimitiveInitStatic, 4
-
-@PrimitiveUninit = internal global [4 x i8] zeroinitializer, align 4
-; CHECK: .type PrimitiveUninit,%object
-; CHECK-NEXT: .section .bss,"aw",%nobits
-; CHECK-NEXT: .p2align 2
-; CHECK-NEXT: PrimitiveUninit:
-; CHECK-NEXT: .zero 4
-; CHECK-NEXT: .size PrimitiveUninit, 4
-
-@ArrayUninit = internal global [20 x i8] zeroinitializer, align 4
-; CHECK: .type ArrayUninit,%object
-; CHECK-NEXT: .section .bss,"aw",%nobits
-; CHECK-NEXT: .p2align 2
-; CHECK-NEXT: ArrayUninit:
-; CHECK-NEXT: .zero 20
-; CHECK-NEXT: .size ArrayUninit, 20
-
-@ArrayUninitConstDouble = internal constant [200 x i8] zeroinitializer, align 8
-; CHECK: .type ArrayUninitConstDouble,%object
-; CHECK-NEXT: .section .rodata,"a",%progbits
-; CHECK-NEXT: .p2align 3
-; CHECK-NEXT: ArrayUninitConstDouble:
-; CHECK-NEXT: .zero 200
-; CHECK-NEXT: .size ArrayUninitConstDouble, 200
-
-@ArrayUninitConstInt = internal constant [20 x i8] zeroinitializer, align 4
-; CHECK: .type ArrayUninitConstInt,%object
-; CHECK: .section .rodata,"a",%progbits
-; CHECK-NEXT: .p2align 2
-; CHECK-NEXT: ArrayUninitConstInt:
-; CHECK-NEXT: .zero 20
-; CHECK-NEXT: .size ArrayUninitConstInt, 20
-
-@__init_array_start = internal constant [0 x i8] zeroinitializer, align 4
-@__fini_array_start = internal constant [0 x i8] zeroinitializer, align 4
-@__tls_template_start = internal constant [0 x i8] zeroinitializer, align 8
-@__tls_template_alignment = internal constant [4 x i8] c"\01\00\00\00", align 4
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/globalrelocs.ll b/third_party/subzero/tests_lit/llvm2ice_tests/globalrelocs.ll
deleted file mode 100644
index 0a528dc..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/globalrelocs.ll
+++ /dev/null
@@ -1,265 +0,0 @@
-; Tests if we handle global variables with relocation initializers.
-
-; REQUIRES: allow_dump
-
-; Test that we handle it in the ICE converter.
-; RUN: %lc2i -i %s --args -verbose inst -threads=0 \
-; RUN: | %iflc FileCheck %s
-; RUN: %lc2i -i %s --args -verbose inst,global_init -threads=0 \
-; RUN: | %iflc FileCheck --check-prefix=DUMP %s
-
-; Test that we handle it using Subzero's bitcode reader.
-; RUN: %p2i -i %s --args -verbose inst -threads=0 \
-; RUN: | FileCheck %s
-; RUN: %p2i -i %s --args -verbose inst,global_init -threads=0 \
-; RUN: | FileCheck --check-prefix=DUMP %s
-
-@bytes = internal global [7 x i8] c"abcdefg"
-; DUMP: @bytes = internal global [7 x i8] c"abcdefg"
-; CHECK: .type bytes,%object
-; CHECK: .section .data,"aw",%progbits
-; CHECK:bytes:
-; CHECK: .byte 97
-; CHECK: .byte 98
-; CHECK: .byte 99
-; CHECK: .byte 100
-; CHECK: .byte 101
-; CHECK: .byte 102
-; CHECK: .byte 103
-; CHECK: .size bytes, 7
-
-@const_bytes = internal constant [7 x i8] c"abcdefg"
-; DUMP: @const_bytes = internal constant [7 x i8] c"abcdefg"
-; CHECK: .type const_bytes,%object
-; CHECK: .section .rodata,"a",%progbits
-; CHECK:const_bytes:
-; CHECK: .byte 97
-; CHECK: .byte 98
-; CHECK: .byte 99
-; CHECK: .byte 100
-; CHECK: .byte 101
-; CHECK: .byte 102
-; CHECK: .byte 103
-; CHECK: .size const_bytes, 7
-
-@ptr_to_ptr = internal global i32 ptrtoint (i32* @ptr to i32)
-; DUMP: @ptr_to_ptr = internal global i32 ptrtoint (i32* @ptr to i32)
-; CHECK: .type ptr_to_ptr,%object
-; CHECK: .section .data,"aw",%progbits
-; CHECK:ptr_to_ptr:
-; CHECK: .long ptr
-; CHECK: .size ptr_to_ptr, 4
-
-@const_ptr_to_ptr = internal constant i32 ptrtoint (i32* @ptr to i32)
-; DUMP: @const_ptr_to_ptr = internal constant i32 ptrtoint (i32* @ptr to i32)
-; CHECK: .type const_ptr_to_ptr,%object
-; CHECK: .section .rodata,"a",%progbits
-; CHECK:const_ptr_to_ptr:
-; CHECK: .long ptr
-; CHECK: .size const_ptr_to_ptr, 4
-
-@ptr_to_func = internal global i32 ptrtoint (void ()* @func to i32)
-; DUMP: @ptr_to_func = internal global i32 ptrtoint (void ()* @func to i32)
-; CHECK: .type ptr_to_func,%object
-; CHECK: .section .data,"aw",%progbits
-; CHECK:ptr_to_func:
-; CHECK: .long func
-; CHECK: .size ptr_to_func, 4
-
-@const_ptr_to_func = internal constant i32 ptrtoint (void ()* @func to i32)
-; DUMP: @const_ptr_to_func = internal constant i32 ptrtoint (void ()* @func to i32)
-; CHECK: .type const_ptr_to_func,%object
-; CHECK: .section .rodata,"a",%progbits
-; CHECK:const_ptr_to_func:
-; CHECK: .long func
-; CHECK: .size const_ptr_to_func, 4
-
-@compound = internal global <{ [3 x i8], i32 }> <{ [3 x i8] c"foo", i32 ptrtoint (void ()* @func to i32) }>
-; DUMP: @compound = internal global <{ [3 x i8], i32 }> <{ [3 x i8] c"foo", i32 ptrtoint (void ()* @func to i32) }>
-; CHECK: .type compound,%object
-; CHECK: .section .data,"aw",%progbits
-; CHECK:compound:
-; CHECK: .byte 102
-; CHECK: .byte 111
-; CHECK: .byte 111
-; CHECK: .long func
-; CHECK: .size compound, 7
-
-@const_compound = internal constant <{ [3 x i8], i32 }> <{ [3 x i8] c"foo", i32 ptrtoint (void ()* @func to i32) }>
-; DUMP: @const_compound = internal constant <{ [3 x i8], i32 }> <{ [3 x i8] c"foo", i32 ptrtoint (void ()* @func to i32) }>
-; CHECK: .type const_compound,%object
-; CHECK: .section .rodata,"a",%progbits
-; CHECK:const_compound:
-; CHECK: .byte 102
-; CHECK: .byte 111
-; CHECK: .byte 111
-; CHECK: .long func
-; CHECK: .size const_compound, 7
-
-@ptr = internal global i32 ptrtoint ([7 x i8]* @bytes to i32)
-; DUMP: @ptr = internal global i32 ptrtoint ([7 x i8]* @bytes to i32)
-; CHECK: .type ptr,%object
-; CHECK: .section .data,"aw",%progbits
-; CHECK:ptr:
-; CHECK: .long bytes
-; CHECK: .size ptr, 4
-
-@const_ptr = internal constant i32 ptrtoint ([7 x i8]* @bytes to i32)
-; DUMP: @const_ptr = internal constant i32 ptrtoint ([7 x i8]* @bytes to i32)
-; CHECK: .type const_ptr,%object
-; CHECK: .section .rodata,"a",%progbits
-; CHECK:const_ptr:
-; CHECK: .long bytes
-; CHECK: .size const_ptr, 4
-
-@addend_ptr = internal global i32 add (i32 ptrtoint (i32* @ptr to i32), i32 1)
-; DUMP: @addend_ptr = internal global i32 add (i32 ptrtoint (i32* @ptr to i32), i32 1)
-; CHECK: .type addend_ptr,%object
-; CHECK: .section .data,"aw",%progbits
-; CHECK:addend_ptr:
-; CHECK: .long ptr + 1
-; CHECK: .size addend_ptr, 4
-
-@const_addend_ptr = internal constant i32 add (i32 ptrtoint (i32* @ptr to i32), i32 1)
-; DUMP: @const_addend_ptr = internal constant i32 add (i32 ptrtoint (i32* @ptr to i32), i32 1)
-; CHECK: .type const_addend_ptr,%object
-; CHECK: .section .rodata,"a",%progbits
-; CHECK:const_addend_ptr:
-; CHECK: .long ptr + 1
-; CHECK: .size const_addend_ptr, 4
-
-@addend_negative = internal global i32 add (i32 ptrtoint (i32* @ptr to i32), i32 -1)
-; DUMP: @addend_negative = internal global i32 add (i32 ptrtoint (i32* @ptr to i32), i32 -1)
-; CHECK: .type addend_negative,%object
-; CHECK: .section .data,"aw",%progbits
-; CHECK:addend_negative:
-; CHECK: .long ptr - 1
-; CHECK: .size addend_negative, 4
-
-@const_addend_negative = internal constant i32 add (i32 ptrtoint (i32* @ptr to i32), i32 -1)
-; DUMP: @const_addend_negative = internal constant i32 add (i32 ptrtoint (i32* @ptr to i32), i32 -1)
-; CHECK: .type const_addend_negative,%object
-; CHECK: .section .rodata,"a",%progbits
-; CHECK:const_addend_negative:
-; CHECK: .long ptr - 1
-; CHECK: .size const_addend_negative, 4
-
-@addend_array1 = internal global i32 add (i32 ptrtoint ([7 x i8]* @bytes to i32), i32 1)
-; DUMP: @addend_array1 = internal global i32 add (i32 ptrtoint ([7 x i8]* @bytes to i32), i32 1)
-; CHECK: .type addend_array1,%object
-; CHECK: .section .data,"aw",%progbits
-; CHECK:addend_array1:
-; CHECK: .long bytes + 1
-; CHECK: .size addend_array1, 4
-
-@const_addend_array1 = internal constant i32 add (i32 ptrtoint ([7 x i8]* @bytes to i32), i32 1)
-; DUMP: @const_addend_array1 = internal constant i32 add (i32 ptrtoint ([7 x i8]* @bytes to i32), i32 1)
-; CHECK: .type const_addend_array1,%object
-; CHECK: .section .rodata,"a",%progbits
-; CHECK:const_addend_array1:
-; CHECK: .long bytes + 1
-; CHECK: .size const_addend_array1, 4
-
-@addend_array2 = internal global i32 add (i32 ptrtoint ([7 x i8]* @bytes to i32), i32 7)
-; DUMP: @addend_array2 = internal global i32 add (i32 ptrtoint ([7 x i8]* @bytes to i32), i32 7)
-; CHECK: .type addend_array2,%object
-; CHECK: .section .data,"aw",%progbits
-; CHECK:addend_array2:
-; CHECK: .long bytes + 7
-; CHECK: .size addend_array2, 4
-
-@const_addend_array2 = internal constant i32 add (i32 ptrtoint ([7 x i8]* @bytes to i32), i32 7)
-; DUMP: @const_addend_array2 = internal constant i32 add (i32 ptrtoint ([7 x i8]* @bytes to i32), i32 7)
-; CHECK: .type const_addend_array2,%object
-; CHECK: .section .rodata,"a",%progbits
-; CHECK:const_addend_array2:
-; CHECK: .long bytes + 7
-; CHECK: .size const_addend_array2, 4
-
-@addend_array3 = internal global i32 add (i32 ptrtoint ([7 x i8]* @bytes to i32), i32 9)
-; DUMP: @addend_array3 = internal global i32 add (i32 ptrtoint ([7 x i8]* @bytes to i32), i32 9)
-; CHECK: .type addend_array3,%object
-; CHECK: .section .data,"aw",%progbits
-; CHECK:addend_array3:
-; CHECK: .long bytes + 9
-; CHECK: .size addend_array3, 4
-
-@const_addend_array3 = internal constant i32 add (i32 ptrtoint ([7 x i8]* @bytes to i32), i32 9)
-; DUMP: @const_addend_array3 = internal constant i32 add (i32 ptrtoint ([7 x i8]* @bytes to i32), i32 9)
-; CHECK: .type const_addend_array3,%object
-; CHECK: .section .rodata,"a",%progbits
-; CHECK:const_addend_array3:
-; CHECK: .long bytes + 9
-; CHECK: .size const_addend_array3, 4
-
-@addend_struct1 = internal global i32 add (i32 ptrtoint (<{ [3 x i8], i32 }>* @compound to i32), i32 1)
-; DUMP: @addend_struct1 = internal global i32 add (i32 ptrtoint (<{ [3 x i8], i32 }>* @compound to i32), i32 1)
-; CHECK: .type addend_struct1,%object
-; CHECK: .section .data,"aw",%progbits
-; CHECK:addend_struct1:
-; CHECK: .long compound + 1
-; CHECK: .size addend_struct1, 4
-
-@const_addend_struct1 = internal constant i32 add (i32 ptrtoint (<{ [3 x i8], i32 }>* @compound to i32), i32 1)
-; DUMP: @const_addend_struct1 = internal constant i32 add (i32 ptrtoint (<{ [3 x i8], i32 }>* @compound to i32), i32 1)
-; CHECK: .type const_addend_struct1,%object
-; CHECK: .section .rodata,"a",%progbits
-; CHECK:const_addend_struct1:
-; CHECK: .long compound + 1
-; CHECK: .size const_addend_struct1, 4
-
-@addend_struct2 = internal global i32 add (i32 ptrtoint (<{ [3 x i8], i32 }>* @compound to i32), i32 4)
-; DUMP: @addend_struct2 = internal global i32 add (i32 ptrtoint (<{ [3 x i8], i32 }>* @compound to i32), i32 4)
-; CHECK: .type addend_struct2,%object
-; CHECK: .section .data,"aw",%progbits
-; CHECK:addend_struct2:
-; CHECK: .long compound + 4
-; CHECK: .size addend_struct2, 4
-
-@const_addend_struct2 = internal constant i32 add (i32 ptrtoint (<{ [3 x i8], i32 }>* @compound to i32), i32 4)
-; DUMP: @const_addend_struct2 = internal constant i32 add (i32 ptrtoint (<{ [3 x i8], i32 }>* @compound to i32), i32 4)
-; CHECK: .type const_addend_struct2,%object
-; CHECK: .section .rodata,"a",%progbits
-; CHECK:const_addend_struct2:
-; CHECK: .long compound + 4
-; CHECK: .size const_addend_struct2, 4
-
-@ptr_to_func_align = internal global i32 ptrtoint (void ()* @func to i32), align 8
-; DUMP: @ptr_to_func_align = internal global i32 ptrtoint (void ()* @func to i32), align 8
-; CHECK: .type ptr_to_func_align,%object
-; CHECK: .section .data,"aw",%progbits
-; CHECK: .p2align 3
-; CHECK:ptr_to_func_align:
-; CHECK: .long func
-; CHECK: .size ptr_to_func_align, 4
-
-@const_ptr_to_func_align = internal constant i32 ptrtoint (void ()* @func to i32), align 8
-; DUMP: @const_ptr_to_func_align = internal constant i32 ptrtoint (void ()* @func to i32), align 8
-; CHECK: .type const_ptr_to_func_align,%object
-; CHECK: .section .rodata,"a",%progbits
-; CHECK: .p2align 3
-; CHECK:const_ptr_to_func_align:
-; CHECK: .long func
-; CHECK: .size const_ptr_to_func_align, 4
-
-@char = internal constant [1 x i8] c"0"
-; DUMP: @char = internal constant [1 x i8] c"0"
-; CHECK: .type char,%object
-; CHECK: .section .rodata,"a",%progbits
-; CHECK:char:
-; CHECK: .byte 48
-; CHECK: .size char, 1
-
-@short = internal constant [2 x i8] zeroinitializer
-; DUMP: @short = internal constant [2 x i8] zeroinitializer
-; CHECK: .type short,%object
-; CHECK: .section .rodata,"a",%progbits
-; CHECK:short:
-; CHECK: .zero 2
-; CHECK: .size short, 2
-
-define internal void @func() {
- ret void
-}
-
-; DUMP: define internal void @func() {
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/ias-data-reloc.ll b/third_party/subzero/tests_lit/llvm2ice_tests/ias-data-reloc.ll
deleted file mode 100644
index d265d40..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/ias-data-reloc.ll
+++ /dev/null
@@ -1,18 +0,0 @@
-; Tests the integrated assembler for instructions with a reloc + offset.
-
-; RUN: %if --need=target_X8632 --need=allow_dump \
-; RUN: --command %p2i --target x8632 -i %s --args -O2 \
-; RUN: | %if --need=target_X8632 --need=allow_dump --command FileCheck %s
-
-@p_global_char = internal global [8 x i8] zeroinitializer, align 8
-
-define internal void @reloc_in_global(i64 %x) {
-entry:
- %p_global_char.bc = bitcast [8 x i8]* @p_global_char to i64*
- ; This 64-bit load is split into an i32 store to [p_global_char]
- ; and an i32 store to [p_global_char + 4] on 32-bit architectures.
- store i64 %x, i64* %p_global_char.bc, align 1
- ret void
-}
-; CHECK-LABEL: reloc_in_global
-; CHECK: .long p_global_char + 4
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/ias-multi-reloc.ll b/third_party/subzero/tests_lit/llvm2ice_tests/ias-multi-reloc.ll
deleted file mode 100644
index 0fedb1e..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/ias-multi-reloc.ll
+++ /dev/null
@@ -1,63 +0,0 @@
-; Tests the integrated assembler for instructions with multiple
-; relocations.
-
-; RUN: %if --need=allow_dump --command %p2i -i %s --args -O2 \
-; RUN: -allow-externally-defined-symbols \
-; RUN: | %if --need=allow_dump --command FileCheck %s
-
-; char global_char;
-; char *p_global_char;
-; void dummy();
-; void store_immediate_to_global() { p_global_char = &global_char; }
-; void add_in_place() { p_global_char += (int)&global_char; }
-; void cmp_global_immediate() { if (p_global_char == &global_char) dummy(); }
-
-@global_char = internal global [1 x i8] zeroinitializer, align 1
-@p_global_char = internal global [4 x i8] zeroinitializer, align 4
-declare void @dummy()
-
-define internal void @store_immediate_to_global() {
-entry:
- %p_global_char.bc = bitcast [4 x i8]* @p_global_char to i32*
- %expanded1 = ptrtoint [1 x i8]* @global_char to i32
- store i32 %expanded1, i32* %p_global_char.bc, align 1
- ret void
-}
-; CHECK-LABEL: store_immediate_to_global
-; CHECK: .long p_global_char
-; CHECK: .long global_char
-
-; Also exercises the RMW add operation.
-define internal void @add_in_place() {
-entry:
- %p_global_char.bc = bitcast [4 x i8]* @p_global_char to i32*
- %0 = load i32, i32* %p_global_char.bc, align 1
- %expanded1 = ptrtoint [1 x i8]* @global_char to i32
- %gep = add i32 %0, %expanded1
- %p_global_char.bc3 = bitcast [4 x i8]* @p_global_char to i32*
- store i32 %gep, i32* %p_global_char.bc3, align 1
- ret void
-}
-; CHECK-LABEL: add_in_place
-; CHECK: .long p_global_char
-; CHECK-NEXT: .long global_char
-
-define internal void @cmp_global_immediate() {
-entry:
- %p_global_char.bc = bitcast [4 x i8]* @p_global_char to i32*
- %0 = load i32, i32* %p_global_char.bc, align 1
- %expanded1 = ptrtoint [1 x i8]* @global_char to i32
- %cmp = icmp eq i32 %0, %expanded1
- br i1 %cmp, label %if.then, label %if.end
-
-if.then: ; preds = %entry
- tail call void @dummy()
- br label %if.end
-
-if.end: ; preds = %if.then, %entry
- ret void
-}
-; CHECK-LABEL: cmp_global_immediate
-; CHECK: .long p_global_char
-; CHECK: .long global_char
-; CHECK: .long dummy
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/icmp-with-zero.ll b/third_party/subzero/tests_lit/llvm2ice_tests/icmp-with-zero.ll
deleted file mode 100644
index aaa9f0d..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/icmp-with-zero.ll
+++ /dev/null
@@ -1,267 +0,0 @@
-; Simple test of non-fused compare/branch.
-
-; RUN: %p2i --filetype=obj --disassemble -i %s --args -O2 \
-; RUN: -allow-externally-defined-symbols | FileCheck %s
-; RUN: %p2i --filetype=obj --disassemble -i %s --args -Om1 \
-; RUN: -allow-externally-defined-symbols | FileCheck --check-prefix=OPTM1 %s
-
-define internal void @icmpEqZero64() {
-entry:
- %cmp = icmp eq i64 123, 0
- br i1 %cmp, label %if.then, label %if.end
-
-if.then: ; preds = %entry
- call void @func()
- br label %if.end
-
-if.end: ; preds = %if.then, %if.end
- ret void
-}
-; The following checks are not strictly necessary since one of the RUN
-; lines actually runs the output through the assembler.
-; CHECK-LABEL: icmpEqZero64
-; CHECK: or
-; CHECK-NOT: set
-; OPTM1-LABEL: icmpEqZero64
-; OPTM1: or
-; OPTM1-NEXT: sete
-
-define internal void @icmpNeZero64() {
-entry:
- %cmp = icmp ne i64 123, 0
- br i1 %cmp, label %if.then, label %if.end
-
-if.then: ; preds = %entry
- call void @func()
- br label %if.end
-
-if.end: ; preds = %if.then, %if.end
- ret void
-}
-; The following checks are not strictly necessary since one of the RUN
-; lines actually runs the output through the assembler.
-; CHECK-LABEL: icmpNeZero64
-; CHECK: or
-; CHECK-NOT: set
-; OPTM1-LABEL: icmpNeZero64
-; OPTM1: or
-; OPTM1-NEXT: setne
-
-define internal void @icmpSgeZero64() {
-entry:
- %cmp = icmp sge i64 123, 0
- br i1 %cmp, label %if.then, label %if.end
-
-if.then: ; preds = %entry
- call void @func()
- br label %if.end
-
-if.end: ; preds = %if.then, %if.end
- ret void
-}
-; The following checks are not strictly necessary since one of the RUN
-; lines actually runs the output through the assembler.
-; CHECK-LABEL: icmpSgeZero64
-; CHECK: test eax,0x80000000
-; CHECK-NOT: sete
-; OPTM1-LABEL: icmpSgeZero64
-; OPTM1: test eax,0x80000000
-; OPTM1-NEXT: sete
-
-define internal void @icmpSltZero64() {
-entry:
- %cmp = icmp slt i64 123, 0
- br i1 %cmp, label %if.then, label %if.end
-
-if.then: ; preds = %entry
- call void @func()
- br label %if.end
-
-if.end: ; preds = %if.then, %if.end
- ret void
-}
-; The following checks are not strictly necessary since one of the RUN
-; lines actually runs the output through the assembler.
-; CHECK-LABEL: icmpSltZero64
-; CHECK: test eax,0x80000000
-; CHECK-NOT: setne
-; OPTM1-LABEL: icmpSltZero64
-; OPTM1: test eax,0x80000000
-; OPTM1-NEXT: setne
-
-define internal void @icmpUltZero64() {
-entry:
- %cmp = icmp ult i64 123, 0
- br i1 %cmp, label %if.then, label %if.end
-
-if.then: ; preds = %entry
- call void @func()
- br label %if.end
-
-if.end: ; preds = %if.then, %if.end
- ret void
-}
-; The following checks are not strictly necessary since one of the RUN
-; lines actually runs the output through the assembler.
-; CHECK-LABEL: icmpUltZero64
-; CHECK: mov [[RESULT:.*]],0x0
-; CHECK-NEXT: cmp [[RESULT]],0x0
-; OPTM1-LABEL: icmpUltZero64
-; OPTM1: mov [[RESULT:.*]],0x0
-; OPTM1-NEXT: cmp [[RESULT]],0x0
-
-define internal void @icmpUgeZero64() {
-entry:
- %cmp = icmp uge i64 123, 0
- br i1 %cmp, label %if.then, label %if.end
-
-if.then: ; preds = %entry
- call void @func()
- br label %if.end
-
-if.end: ; preds = %if.then, %if.end
- ret void
-}
-; The following checks are not strictly necessary since one of the RUN
-; lines actually runs the output through the assembler.
-; CHECK-LABEL: icmpUgeZero64
-; CHECK: mov [[RESULT:.*]],0x1
-; CHECK-NEXT: cmp [[RESULT]],0x0
-; OPTM1-LABEL: icmpUgeZero64
-; OPTM1: mov [[RESULT:.*]],0x1
-; OPTM1-NEXT: cmp [[RESULT]],0x0
-
-define internal void @icmpUltZero32() {
-entry:
- %cmp = icmp ult i32 123, 0
- br i1 %cmp, label %if.then, label %if.end
-
-if.then: ; preds = %entry
- %cmp_ext = zext i1 %cmp to i32
- call void @use(i32 %cmp_ext)
- br label %if.end
-
-if.end: ; preds = %if.then, %if.end
- ret void
-}
-; The following checks are not strictly necessary since one of the RUN
-; lines actually runs the output through the assembler.
-; CHECK-LABEL: icmpUltZero32
-; CHECK: mov [[RESULT:.*]],0x0
-; CHECK-NEXT: cmp [[RESULT]],0x0
-; OPTM1-LABEL: icmpUltZero32
-; OPTM1: mov [[RESULT:.*]],0x0
-; OPTM1: cmp [[RESULT]],0x0
-
-define internal void @icmpUgeZero32() {
-entry:
- %cmp = icmp uge i32 123, 0
- br i1 %cmp, label %if.then, label %if.end
-
-if.then: ; preds = %entry
- %cmp_ext = zext i1 %cmp to i32
- call void @use(i32 %cmp_ext)
- br label %if.end
-
-if.end: ; preds = %if.then, %if.end
- ret void
-}
-; The following checks are not strictly necessary since one of the RUN
-; lines actually runs the output through the assembler.
-; CHECK-LABEL: icmpUgeZero32
-; CHECK: mov [[RESULT:.*]],0x1
-; CHECK-NEXT: cmp [[RESULT]],0x0
-; OPTM1-LABEL: icmpUgeZero32
-; OPTM1: mov [[RESULT:.*]],0x1
-; OPTM1-NEXT: cmp [[RESULT]],0x0
-
-define internal void @icmpUltZero16() {
-entry:
- %cmp = icmp ult i16 123, 0
- br i1 %cmp, label %if.then, label %if.end
-
-if.then: ; preds = %entry
- %cmp_ext = zext i1 %cmp to i32
- call void @use(i32 %cmp_ext)
- br label %if.end
-
-if.end: ; preds = %if.then, %if.end
- ret void
-}
-; The following checks are not strictly necessary since one of the RUN
-; lines actually runs the output through the assembler.
-; CHECK-LABEL: icmpUltZero16
-; CHECK: mov [[RESULT:.*]],0x0
-; CHECK-NEXT: cmp [[RESULT]],0x0
-; OPTM1-LABEL: icmpUltZero16
-; OPTM1: mov [[RESULT:.*]],0x0
-; OPTM1-NEXT: cmp [[RESULT]],0x0
-
-define internal void @icmpUgeZero16() {
-entry:
- %cmp = icmp uge i16 123, 0
- br i1 %cmp, label %if.then, label %if.end
-
-if.then: ; preds = %entry
- %cmp_ext = zext i1 %cmp to i32
- call void @use(i32 %cmp_ext)
- br label %if.end
-
-if.end: ; preds = %if.then, %if.end
- ret void
-}
-; The following checks are not strictly necessary since one of the RUN
-; lines actually runs the output through the assembler.
-; CHECK-LABEL: icmpUgeZero16
-; CHECK: mov [[RESULT:.*]],0x1
-; CHECK-NEXT: cmp [[RESULT]],0x0
-; OPTM1-LABEL: icmpUgeZero16
-; OPTM1: mov [[RESULT:.*]],0x1
-; OPTM1-NEXT: cmp [[RESULT]],0x0
-
-define internal void @icmpUltZero8() {
-entry:
- %cmp = icmp ult i8 123, 0
- br i1 %cmp, label %if.then, label %if.end
-
-if.then: ; preds = %entry
- %cmp_ext = zext i1 %cmp to i32
- call void @use(i32 %cmp_ext)
- br label %if.end
-
-if.end: ; preds = %if.then, %if.end
- ret void
-}
-; The following checks are not strictly necessary since one of the RUN
-; lines actually runs the output through the assembler.
-; CHECK-LABEL: icmpUltZero8
-; CHECK: mov [[RESULT:.*]],0x0
-; CHECK-NEXT: cmp [[RESULT]],0x0
-; OPTM1-LABEL: icmpUltZero8
-; OPTM1: mov [[RESULT:.*]],0x0
-; OPTM1-NEXT: cmp [[RESULT]],0x0
-
-define internal void @icmpUgeZero8() {
-entry:
- %cmp = icmp uge i8 123, 0
- br i1 %cmp, label %if.then, label %if.end
-
-if.then: ; preds = %entry
- %cmp_ext = zext i1 %cmp to i32
- call void @use(i32 %cmp_ext)
- br label %if.end
-
-if.end: ; preds = %if.then, %if.end
- ret void
-}
-; The following checks are not strictly necessary since one of the RUN
-; lines actually runs the output through the assembler.
-; CHECK-LABEL: icmpUgeZero8
-; CHECK: mov [[RESULT:.*]],0x1
-; CHECK-NEXT: cmp [[RESULT]],0x0
-; OPTM1-LABEL: icmpUgeZero8
-; OPTM1: mov [[RESULT:.*]],0x1
-; OPTM1-NEXT: cmp [[RESULT]],0x0
-
-declare void @func()
-declare void @use(i32)
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/icmp.ll b/third_party/subzero/tests_lit/llvm2ice_tests/icmp.ll
deleted file mode 100644
index 6c73ff6..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/icmp.ll
+++ /dev/null
@@ -1,174 +0,0 @@
-; Simple tests for icmp with i8, i16, i32 operands.
-
-; RUN: %if --need=allow_dump --need=target_MIPS32 --command %p2i \
-; RUN: --filetype=asm --target mips32 -i %s --args -O2 \
-; RUN: -allow-externally-defined-symbols \
-; RUN: | %if --need=allow_dump --need=target_MIPS32 --command FileCheck %s \
-; RUN: --check-prefix=COMMON --check-prefix=MIPS32
-; RUN: %if --need=allow_dump --need=target_MIPS32 --command %p2i \
-; RUN: --filetype=asm --target mips32 -i %s --args -Om1 \
-; RUN: -allow-externally-defined-symbols \
-; RUN: | %if --need=allow_dump --need=target_MIPS32 --command FileCheck %s \
-; RUN: --check-prefix=COMMON --check-prefix=MIPS32
-
-define internal i32 @icmpEq32(i32 %a, i32 %b) {
-entry:
- %cmp = icmp eq i32 %a, %b
- %cmp.ret_ext = zext i1 %cmp to i32
- ret i32 %cmp.ret_ext
-}
-; MIPS32-LABEL: icmpEq32
-; MIPS32: xor
-; MIPS32: sltiu {{.*}}, {{.*}}, 1
-
-define internal i32 @icmpNe32(i32 %a, i32 %b) {
-entry:
- %cmp = icmp ne i32 %a, %b
- %cmp.ret_ext = zext i1 %cmp to i32
- ret i32 %cmp.ret_ext
-}
-; MIPS32-LABEL: icmpNe32
-; MIPS32: xor
-; MIPS32: sltu {{.*}}, $zero, {{.*}}
-
-define internal i32 @icmpSgt32(i32 %a, i32 %b) {
-entry:
- %cmp = icmp sgt i32 %a, %b
- %cmp.ret_ext = zext i1 %cmp to i32
- ret i32 %cmp.ret_ext
-}
-; MIPS32-LABEL: icmpSgt32
-; MIPS32: slt
-
-define internal i32 @icmpUgt32(i32 %a, i32 %b) {
-entry:
- %cmp = icmp ugt i32 %a, %b
- %cmp.ret_ext = zext i1 %cmp to i32
- ret i32 %cmp.ret_ext
-}
-; MIPS32-LABEL: icmpUgt32
-; MIPS32: sltu
-
-define internal i32 @icmpSge32(i32 %a, i32 %b) {
-entry:
- %cmp = icmp sge i32 %a, %b
- %cmp.ret_ext = zext i1 %cmp to i32
- ret i32 %cmp.ret_ext
-}
-; MIPS32-LABEL: icmpSge32
-; MIPS32: slt
-; MIPS32: xori {{.*}}, {{.*}}, 1
-
-define internal i32 @icmpUge32(i32 %a, i32 %b) {
-entry:
- %cmp = icmp uge i32 %a, %b
- %cmp.ret_ext = zext i1 %cmp to i32
- ret i32 %cmp.ret_ext
-}
-; MIPS32-LABEL: icmpUge32
-; MIPS32: sltu
-; MIPS32: xori {{.*}}, {{.*}}, 1
-
-define internal i32 @icmpSlt32(i32 %a, i32 %b) {
-entry:
- %cmp = icmp slt i32 %a, %b
- %cmp.ret_ext = zext i1 %cmp to i32
- ret i32 %cmp.ret_ext
-}
-; MIPS32-LABEL: icmpSlt32
-; MIPS32: slt
-
-define internal i32 @icmpUlt32(i32 %a, i32 %b) {
-entry:
- %cmp = icmp ult i32 %a, %b
- %cmp.ret_ext = zext i1 %cmp to i32
- ret i32 %cmp.ret_ext
-}
-; MIPS32-LABEL: icmpUlt32
-; MIPS32: sltu
-
-define internal i32 @icmpSle32(i32 %a, i32 %b) {
-entry:
- %cmp = icmp sle i32 %a, %b
- %cmp.ret_ext = zext i1 %cmp to i32
- ret i32 %cmp.ret_ext
-}
-; MIPS32-LABEL: icmpSle32
-; MIPS32: slt
-; MIPS32: xori {{.*}}, {{.*}}, 1
-
-define internal i32 @icmpUle32(i32 %a, i32 %b) {
-entry:
- %cmp = icmp ule i32 %a, %b
- %cmp.ret_ext = zext i1 %cmp to i32
- ret i32 %cmp.ret_ext
-}
-; MIPS32-LABEL: icmpUle32
-; MIPS32: sltu
-; MIPS32: xori {{.*}}, {{.*}}, 1
-
-define internal i32 @icmpEq8(i32 %a, i32 %b) {
-entry:
- %a_8 = trunc i32 %a to i8
- %b_8 = trunc i32 %b to i8
- %icmp = icmp eq i8 %b_8, %a_8
- %ret = zext i1 %icmp to i32
- ret i32 %ret
-}
-; MIPS32-LABEL: icmpEq8
-; MIPS32: sll {{.*}}, {{.*}}, 24
-; MIPS32: sll {{.*}}, {{.*}}, 24
-; MIPS32: xor
-; MIPS32: sltiu {{.*}}, {{.*}}, 1
-
-define internal i32 @icmpSgt8(i32 %a, i32 %b) {
-entry:
- %a_8 = trunc i32 %a to i8
- %b_8 = trunc i32 %b to i8
- %icmp = icmp sgt i8 %b_8, %a_8
- %ret = zext i1 %icmp to i32
- ret i32 %ret
-}
-; MIPS32-LABEL: icmpSgt8
-; MIPS32: sll {{.*}}, {{.*}}, 24
-; MIPS32: sll {{.*}}, {{.*}}, 24
-; MIPS32: slt
-
-define internal i32 @icmpUgt8(i32 %a, i32 %b) {
-entry:
- %a_8 = trunc i32 %a to i8
- %b_8 = trunc i32 %b to i8
- %icmp = icmp ugt i8 %b_8, %a_8
- %ret = zext i1 %icmp to i32
- ret i32 %ret
-}
-; MIPS32-LABEL: icmpUgt8
-; MIPS32: sll {{.*}}, {{.*}}, 24
-; MIPS32: sll {{.*}}, {{.*}}, 24
-; MIPS32: sltu
-
-define internal i32 @icmpSgt16(i32 %a, i32 %b) {
-entry:
- %a_16 = trunc i32 %a to i16
- %b_16 = trunc i32 %b to i16
- %icmp = icmp sgt i16 %b_16, %a_16
- %ret = zext i1 %icmp to i32
- ret i32 %ret
-}
-; MIPS32-LABEL: icmpSgt16
-; MIPS32: sll {{.*}}, {{.*}}, 16
-; MIPS32: sll {{.*}}, {{.*}}, 16
-; MIPS32: slt
-
-define internal i32 @icmpUgt16(i32 %a, i32 %b) {
-entry:
- %a_16 = trunc i32 %a to i16
- %b_16 = trunc i32 %b to i16
- %icmp = icmp ugt i16 %b_16, %a_16
- %ret = zext i1 %icmp to i32
- ret i32 %ret
-}
-; MIPS32-LABEL: icmpUgt16
-; MIPS32: sll {{.*}}, {{.*}}, 16
-; MIPS32: sll {{.*}}, {{.*}}, 16
-; MIPS32: sltu
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/int-arg.ll b/third_party/subzero/tests_lit/llvm2ice_tests/int-arg.ll
deleted file mode 100644
index e1965b1..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/int-arg.ll
+++ /dev/null
@@ -1,297 +0,0 @@
-; This file checks that Subzero generates code in accordance with the
-; calling convention for integers.
-
-; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
-; RUN: --target x8632 -i %s --args -O2 -allow-externally-defined-symbols \
-; RUN: | %if --need=target_X8632 --command FileCheck %s
-
-; RUN: %if --need=target_ARM32 \
-; RUN: --command %p2i --filetype=obj \
-; RUN: --disassemble --target arm32 -i %s --args -O2 \
-; RUN: -allow-externally-defined-symbols \
-; RUN: | %if --need=target_ARM32 \
-; RUN: --command FileCheck --check-prefix ARM32 %s
-
-; TODO: Switch to --filetype=obj when possible.
-; RUN: %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command %p2i --filetype=asm --assemble \
-; RUN: --disassemble --target mips32 -i %s --args -O2 \
-; RUN: -allow-externally-defined-symbols \
-; RUN: | %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command FileCheck --check-prefix MIPS32 %s
-
-; For x86-32, integer arguments use the stack.
-; For ARM32, integer arguments can be r0-r3. i64 arguments occupy two
-; adjacent 32-bit registers, and require the first to be an even register.
-
-
-; i32
-
-define internal i32 @test_returning32_arg0(i32 %arg0, i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %arg5, i32 %arg6, i32 %arg7) {
-entry:
- ret i32 %arg0
-}
-; CHECK-LABEL: test_returning32_arg0
-; CHECK-NEXT: mov eax,{{.*}} [esp+0x4]
-; CHECK-NEXT: ret
-; ARM32-LABEL: test_returning32_arg0
-; ARM32-NEXT: bx lr
-; MIPS32-LABEL: test_returning32_arg0
-; MIPS32: move v0,a0
-; MIPS32-NEXT: jr ra
-
-define internal i32 @test_returning32_arg1(i32 %arg0, i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %arg5, i32 %arg6, i32 %arg7) {
-entry:
- ret i32 %arg1
-}
-; CHECK-LABEL: test_returning32_arg1
-; CHECK-NEXT: mov eax,{{.*}} [esp+0x8]
-; CHECK-NEXT: ret
-; ARM32-LABEL: test_returning32_arg1
-; ARM32-NEXT: mov r0, r1
-; ARM32-NEXT: bx lr
-; MIPS32-LABEL: test_returning32_arg1
-; MIPS32: move v0,a1
-; MIPS32-NEXT: jr ra
-
-define internal i32 @test_returning32_arg2(i32 %arg0, i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %arg5, i32 %arg6, i32 %arg7) {
-entry:
- ret i32 %arg2
-}
-; CHECK-LABEL: test_returning32_arg2
-; CHECK-NEXT: mov eax,{{.*}} [esp+0xc]
-; CHECK-NEXT: ret
-; ARM32-LABEL: test_returning32_arg2
-; ARM32-NEXT: mov r0, r2
-; ARM32-NEXT: bx lr
-; MIPS32-LABEL: test_returning32_arg2
-; MIPS32: move v0,a2
-; MIPS32-NEXT: jr ra
-
-
-define internal i32 @test_returning32_arg3(i32 %arg0, i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %arg5, i32 %arg6, i32 %arg7) {
-entry:
- ret i32 %arg3
-}
-; CHECK-LABEL: test_returning32_arg3
-; CHECK-NEXT: mov eax,{{.*}} [esp+0x10]
-; CHECK-NEXT: ret
-; ARM32-LABEL: test_returning32_arg3
-; ARM32-NEXT: mov r0, r3
-; ARM32-NEXT: bx lr
-
-
-define internal i32 @test_returning32_arg4(i32 %arg0, i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %arg5, i32 %arg6, i32 %arg7) {
-entry:
- ret i32 %arg4
-}
-; CHECK-LABEL: test_returning32_arg4
-; CHECK-NEXT: mov eax,{{.*}} [esp+0x14]
-; CHECK-NEXT: ret
-; ARM32-LABEL: test_returning32_arg4
-; ARM32-NEXT: ldr r0, [sp]
-; ARM32-NEXT: bx lr
-
-
-define internal i32 @test_returning32_arg5(i32 %arg0, i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %arg5, i32 %arg6, i32 %arg7) {
-entry:
- ret i32 %arg5
-}
-; CHECK-LABEL: test_returning32_arg5
-; CHECK-NEXT: mov eax,{{.*}} [esp+0x18]
-; CHECK-NEXT: ret
-; ARM32-LABEL: test_returning32_arg5
-; ARM32-NEXT: ldr r0, [sp, #4]
-; ARM32-NEXT: bx lr
-
-; i64
-
-define internal i64 @test_returning64_arg0(i64 %arg0, i64 %arg1, i64 %arg2, i64 %arg3) {
-entry:
- ret i64 %arg0
-}
-; CHECK-LABEL: test_returning64_arg0
-; CHECK-NEXT: mov {{.*}} [esp+0x4]
-; CHECK-NEXT: mov {{.*}} [esp+0x8]
-; CHECK: ret
-; ARM32-LABEL: test_returning64_arg0
-; ARM32-NEXT: bx lr
-; MIPS32-LABEL: test_returning64_arg0
-; MIPS32-NEXT: move v0,a0
-; MIPS32-NEXT: move v1,a1
-
-
-define internal i64 @test_returning64_arg1(i64 %arg0, i64 %arg1, i64 %arg2, i64 %arg3) {
-entry:
- ret i64 %arg1
-}
-; CHECK-LABEL: test_returning64_arg1
-; CHECK-NEXT: mov {{.*}} [esp+0xc]
-; CHECK-NEXT: mov {{.*}} [esp+0x10]
-; CHECK: ret
-; ARM32-LABEL: test_returning64_arg1
-; ARM32-NEXT: mov r0, r2
-; ARM32-NEXT: mov r1, r3
-; ARM32-NEXT: bx lr
-; MIPS32-LABEL: test_returning64_arg1
-; MIPS32-NEXT: move v0,a2
-; MIPS32-NEXT: move v1,a3
-
-define internal i64 @test_returning64_arg2(i64 %arg0, i64 %arg1, i64 %arg2, i64 %arg3) {
-entry:
- ret i64 %arg2
-}
-; CHECK-LABEL: test_returning64_arg2
-; CHECK-NEXT: mov {{.*}} [esp+0x14]
-; CHECK-NEXT: mov {{.*}} [esp+0x18]
-; CHECK: ret
-; ARM32-LABEL: test_returning64_arg2
-; This could have been a ldm sp, {r0, r1}, but we don't do the ldm optimization.
-; ARM32-NEXT: ldr r0, [sp]
-; ARM32-NEXT: ldr r1, [sp, #4]
-; ARM32-NEXT: bx lr
-
-define internal i64 @test_returning64_arg3(i64 %arg0, i64 %arg1, i64 %arg2, i64 %arg3) {
-entry:
- ret i64 %arg3
-}
-; CHECK-LABEL: test_returning64_arg3
-; CHECK-NEXT: mov {{.*}} [esp+0x1c]
-; CHECK-NEXT: mov {{.*}} [esp+0x20]
-; CHECK: ret
-; ARM32-LABEL: test_returning64_arg3
-; ARM32-NEXT: ldr r0, [sp, #8]
-; ARM32-NEXT: ldr r1, [sp, #12]
-; ARM32-NEXT: bx lr
-
-
-; Test that on ARM, the i64 arguments start with an even register.
-
-define internal i64 @test_returning64_even_arg1(i32 %arg0, i64 %arg1, i64 %arg2) {
-entry:
- ret i64 %arg1
-}
-; Not padded out x86-32.
-; CHECK-LABEL: test_returning64_even_arg1
-; CHECK-NEXT: mov {{.*}} [esp+0x8]
-; CHECK-NEXT: mov {{.*}} [esp+0xc]
-; CHECK: ret
-; ARM32-LABEL: test_returning64_even_arg1
-; ARM32-NEXT: mov r0, r2
-; ARM32-NEXT: mov r1, r3
-; ARM32-NEXT: bx lr
-
-define internal i64 @test_returning64_even_arg1b(i32 %arg0, i32 %arg0b, i64 %arg1, i64 %arg2) {
-entry:
- ret i64 %arg1
-}
-; CHECK-LABEL: test_returning64_even_arg1b
-; CHECK-NEXT: mov {{.*}} [esp+0xc]
-; CHECK-NEXT: mov {{.*}} [esp+0x10]
-; CHECK: ret
-; ARM32-LABEL: test_returning64_even_arg1b
-; ARM32-NEXT: mov r0, r2
-; ARM32-NEXT: mov r1, r3
-; ARM32-NEXT: bx lr
-
-define internal i64 @test_returning64_even_arg2(i64 %arg0, i32 %arg1, i64 %arg2) {
-entry:
- ret i64 %arg2
-}
-; Not padded out on x86-32.
-; CHECK-LABEL: test_returning64_even_arg2
-; CHECK-NEXT: mov {{.*}} [esp+0x10]
-; CHECK-NEXT: mov {{.*}} [esp+0x14]
-; CHECK: ret
-; ARM32-LABEL: test_returning64_even_arg2
-; ARM32-DAG: ldr r0, [sp]
-; ARM32-DAG: ldr r1, [sp, #4]
-; ARM32-NEXT: bx lr
-
-define internal i64 @test_returning64_even_arg2b(i64 %arg0, i32 %arg1, i32 %arg1b, i64 %arg2) {
-entry:
- ret i64 %arg2
-}
-; CHECK-LABEL: test_returning64_even_arg2b
-; CHECK-NEXT: mov {{.*}} [esp+0x14]
-; CHECK-NEXT: mov {{.*}} [esp+0x18]
-; CHECK: ret
-; ARM32-LABEL: test_returning64_even_arg2b
-; ARM32-NEXT: ldr r0, [sp]
-; ARM32-NEXT: ldr r1, [sp, #4]
-; ARM32-NEXT: bx lr
-
-define internal i32 @test_returning32_even_arg2(i64 %arg0, i32 %arg1, i32 %arg2) {
-entry:
- ret i32 %arg2
-}
-; CHECK-LABEL: test_returning32_even_arg2
-; CHECK-NEXT: mov {{.*}} [esp+0x10]
-; CHECK-NEXT: ret
-; ARM32-LABEL: test_returning32_even_arg2
-; ARM32-NEXT: mov r0, r3
-; ARM32-NEXT: bx lr
-
-define internal i32 @test_returning32_even_arg2b(i32 %arg0, i32 %arg1, i32 %arg2, i64 %arg3) {
-entry:
- ret i32 %arg2
-}
-; CHECK-LABEL: test_returning32_even_arg2b
-; CHECK-NEXT: mov {{.*}} [esp+0xc]
-; CHECK-NEXT: ret
-; ARM32-LABEL: test_returning32_even_arg2b
-; ARM32-NEXT: mov r0, r2
-; ARM32-NEXT: bx lr
-
-; The i64 won't fit in a pair of register, and consumes the last register so a
-; following i32 can't use that free register.
-define internal i32 @test_returning32_even_arg4(i32 %arg0, i32 %arg1, i32 %arg2, i64 %arg3, i32 %arg4) {
-entry:
- ret i32 %arg4
-}
-; CHECK-LABEL: test_returning32_even_arg4
-; CHECK-NEXT: mov {{.*}} [esp+0x18]
-; CHECK-NEXT: ret
-; ARM32-LABEL: test_returning32_even_arg4
-; ARM32-NEXT: ldr r0, [sp, #8]
-; ARM32-NEXT: bx lr
-
-; Test interleaving float/double and integer (different register streams on ARM).
-; TODO(jvoung): Test once the S/D/Q regs are modeled.
-
-; Test that integers are passed correctly as arguments to a function.
-
-declare void @IntArgs(i32, i32, i32, i32, i32, i32)
-
-declare void @killRegisters()
-
-define internal void @test_passing_integers(i32 %arg0, i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %arg5, i32 %arg6) {
- call void @killRegisters()
- call void @IntArgs(i32 %arg6, i32 %arg5, i32 %arg4, i32 %arg3, i32 %arg2, i32 %arg1)
- ret void
-}
-
-; CHECK-LABEL: test_passing_integers
-; CHECK-DAG: mov [[REG1:e.*]],DWORD PTR [esp+0x44]
-; CHECK-DAG: mov [[REG2:e.*]],DWORD PTR [esp+0x48]
-; CHECK-DAG: mov [[REG3:e.*]],DWORD PTR [esp+0x4c]
-; CHECK-DAG: mov [[REG4:e.*]],DWORD PTR [esp+0x50]
-; CHECK: mov DWORD PTR [esp]
-; CHECK: mov DWORD PTR [esp+0x4]
-; CHECK-DAG: mov DWORD PTR [esp+0x8],[[REG4]]
-; CHECK-DAG: mov DWORD PTR [esp+0xc],[[REG3]]
-; CHECK-DAG: mov DWORD PTR [esp+0x10],[[REG2]]
-; CHECK-DAG: mov DWORD PTR [esp+0x14],[[REG1]]
-; CHECK: call
-
-; ARM32-LABEL: test_passing_integers
-; ARM32-DAG: mov [[REG1:.*]], r1
-; ARM32-DAG: mov [[REG2:.*]], r2
-; ARM32-DAG: mov [[REG3:.*]], r3
-; ARM32: str [[REG2]], [sp]
-; ARM32: str [[REG1]], [sp, #4]
-; ARM32-DAG: mov r0
-; ARM32-DAG: mov r1
-; ARM32-DAG: mov r2
-; ARM32-DAG: mov r3, [[REG3]]
-; ARM32: bl
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/invalid.test b/third_party/subzero/tests_lit/llvm2ice_tests/invalid.test
deleted file mode 100644
index 14413b7..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/invalid.test
+++ /dev/null
@@ -1,13 +0,0 @@
-; Test that we handle functions that don't end with a terminator instruction.
-; See issue: https://code.google.com/p/nativeclient/issues/detail?id=4214
-
-; Don't run in minimal build, since error messages are in generic form
- when minimal.
-
-; REQUIRES: no_minimal_build
-
-RUN: %p2i --expect-fail --tbc -i %p/Input/no-terminator-inst.tbc --insts \
-RUN: --args -allow-externally-defined-symbols \
-RUN: | FileCheck --check-prefix=NO-TERM-INST %s
-
-; NO-TERM-INST: Last instruction in function not terminator
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/large_stack_offs.ll b/third_party/subzero/tests_lit/llvm2ice_tests/large_stack_offs.ll
deleted file mode 100644
index 9490c68..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/large_stack_offs.ll
+++ /dev/null
@@ -1,126 +0,0 @@
-; This tries to create variables with very large stack offsets.
-; This requires a lot of variables/register pressure. To simplify this
-; we assume poor register allocation from Om1, and a flag that forces
-; the frame to add K amount of unused stack for testing.
-; We only need to test ARM and other architectures which have limited space
-; for specifying an offset within an instruction.
-
-; RUN: %if --need=target_ARM32 \
-; RUN: --command %p2i --filetype=obj --disassemble --target arm32 \
-; RUN: -i %s --args -Om1 --test-stack-extra 4096 \
-; RUN: -allow-externally-defined-symbols \
-; RUN: | %if --need=target_ARM32 \
-; RUN: --command FileCheck --check-prefix ARM32 %s
-
-declare i64 @dummy(i32 %t1, i32 %t2, i32 %t3, i64 %t4, i64 %t5)
-
-; Test a function that requires lots of stack (due to test flag), and uses
-; SP as the base register (originally).
-define internal i64 @lotsOfStack(i32 %a, i32 %b, i32 %c, i32 %d) {
-entry:
- %t1 = xor i32 %a, %b
- %t2 = or i32 %c, %d
- %cmp = icmp eq i32 %t1, %t2
- br i1 %cmp, label %br_1, label %br_2
-
-br_1:
- %x1 = zext i32 %t1 to i64
- %y1 = ashr i64 %x1, 17
- ; Use some stack during the call, so that references to %t1 and %t2's
- ; stack slots require stack adjustment.
- %r1 = call i64 @dummy(i32 123, i32 321, i32 %t2, i64 %x1, i64 %y1)
- %z1 = sub i64 %r1, %y1
- br label %end
-
-br_2:
- %x2 = zext i32 %t2 to i64
- %y2 = and i64 %x2, 123
- %r2 = call i64 @dummy(i32 123, i32 321, i32 %t2, i64 %x2, i64 %y2)
- %z2 = and i64 %r2, %y2
- br label %end
-
-end:
- %x3 = phi i64 [ %x1, %br_1 ], [ %x2, %br_2 ]
- %z3 = phi i64 [ %z1, %br_1 ], [ %z2, %br_2 ]
- %r3 = and i64 %x3, %z3
- ret i64 %r3
-}
-; ARM32-LABEL: lotsOfStack
-; ARM32-NOT: mov fp, sp
-; ARM32: movw ip, #4{{.*}}
-; ARM32-NEXT: sub sp, sp, ip
-; ARM32: movw ip, #4248
-; ARM32-NEXT: add ip, sp, ip
-; ARM32-NOT: movw ip
-; %t2 is the result of the "or", and %t2 will be passed via r1 to the call.
-; Use that to check the stack offset of %t2. The first offset and the
-; later offset right before the call should be 16 bytes apart,
-; because of the sub sp, sp, #16.
-; ARM32: orr [[REG:r.*]], {{.*}},
-; I.e., the slot for t2 is (sp0 + 4232 - 20) == sp0 + 4212.
-; ARM32: str [[REG]], [ip, #-20]
-; ARM32: b {{[a-f0-9]+}}
-; Now skip ahead to where the call in br_1 begins, to check how %t2 is used.
-; ARM32: movw ip, #4232
-; ARM32-NEXT: add ip, sp, ip
-; ARM32: ldr r2, [ip, #-4]
-; ARM32: bl {{.*}} dummy
-; The call clobbers ip, so we need to re-create the base register.
-; ARM32: movw ip, #4{{.*}}
-; ARM32: b {{[a-f0-9]+}}
-; ARM32: bl {{.*}} dummy
-
-; Similar, but test a function that uses FP as the base register (originally).
-define internal i64 @usesFrameReg(i32 %a, i32 %b, i32 %c, i32 %d) {
-entry:
- %p = alloca i8, i32 %d, align 4
- %t1 = xor i32 %a, %b
- %t2 = or i32 %c, %d
- %cmp = icmp eq i32 %t1, %t2
- br i1 %cmp, label %br_1, label %br_2
-
-br_1:
- %x1 = zext i32 %t1 to i64
- %y1 = ashr i64 %x1, 17
- %p32 = ptrtoint i8* %p to i32
- %r1 = call i64 @dummy(i32 %p32, i32 321, i32 %t2, i64 %x1, i64 %y1)
- %z1 = sub i64 %r1, %y1
- br label %end
-
-br_2:
- %x2 = zext i32 %t2 to i64
- %y2 = and i64 %x2, 123
- %r2 = call i64 @dummy(i32 123, i32 321, i32 %d, i64 %x2, i64 %y2)
- %z2 = and i64 %r2, %y2
- br label %end
-
-end:
- %x3 = phi i64 [ %x1, %br_1 ], [ %x2, %br_2 ]
- %z3 = phi i64 [ %z1, %br_1 ], [ %z2, %br_2 ]
- %r3 = and i64 %x3, %z3
- ret i64 %r3
-}
-; ARM32-LABEL: usesFrameReg
-; ARM32: mov fp, sp
-; ARM32: movw ip, #4{{.*}}
-; ARM32-NEXT: sub sp, sp, ip
-; ARM32: movw ip, #4100
-; ARM32-NEXT: sub ip, fp, ip
-; ARM32-NOT: movw ip
-; %t2 is the result of the "or", and %t2 will be passed via r1 to the call.
-; Use that to check the stack offset of %t2. It should be the same offset
-; even after sub sp, sp, #16, because the base register was originally
-; the FP and not the SP.
-; ARM32: orr [[REG:r.*]], {{.*}},
-; I.e., the slot for t2 is (fp0 - 4100 -24) == fp0 - 4124
-; ARM32: str [[REG]], [ip, #-24]
-; ARM32: b {{[a-f0-9]+}}
-; Now skip ahead to where the call in br_1 begins, to check how %t2 is used.
-; ARM32: movw ip, #4120
-; ARM32-NEXT: sub ip, fp, ip
-; ARM32: ldr r2, [ip, #-4]
-; ARM32: bl {{.*}} dummy
-; The call clobbers ip, so we need to re-create the base register.
-; ARM32: movw ip, #4{{.*}}
-; ARM32: b {{[a-f0-9]+}}
-; ARM32: bl {{.*}} dummy
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/licm.ll b/third_party/subzero/tests_lit/llvm2ice_tests/licm.ll
deleted file mode 100644
index 53761bb..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/licm.ll
+++ /dev/null
@@ -1,36 +0,0 @@
-; Tests if the licm flag successfully hoists the add from loop0 to entry
-
-; RUN: %p2i -i %s --filetype=obj --disassemble --target x8664 --args \
-; RUN: -O2 -licm | FileCheck --check-prefix ENABLE %s
-
-; RUN: %p2i -i %s --filetype=obj --disassemble --target x8664 --args \
-; RUN: -O2 | FileCheck --check-prefix NOENABLE %s
-
-define internal void @dummy() {
-entry:
- ret void
-}
-define internal i32 @test_licm(i32 %a32, i32 %b, i32 %c) {
-entry:
- %a = trunc i32 %a32 to i1
- br label %loop0
-loop0: ; <-+
- call void @dummy() ; |
- %add1 = add i32 %b, %c ; |
- br label %loop1 ; |
-loop1: ; |
- br i1 %a, label %loop0, label %out ; --+
-out:
- ret i32 %add1
-}
-
-; CHECK-LABEL: test_licm
-
-; ENABLE: add
-; ENABLE: call
-
-; NOENABLE: call
-; NOENABLE-NEXT: mov
-; NOENABLE-NEXT: add
-
-; CHECK: ret
\ No newline at end of file
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/load.ll b/third_party/subzero/tests_lit/llvm2ice_tests/load.ll
deleted file mode 100644
index 5dd0039..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/load.ll
+++ /dev/null
@@ -1,74 +0,0 @@
-; Simple test of the load instruction.
-
-; REQUIRES: allow_dump
-
-; RUN: %p2i -i %s --args --verbose inst -threads=0 | FileCheck %s
-
-; RUN: %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command %p2i --filetype=asm --assemble \
-; RUN: --disassemble --target mips32 -i %s --args -Om1 \
-; RUN: -allow-externally-defined-symbols \
-; RUN: | %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command FileCheck --check-prefix MIPS32 %s
-
-define internal void @load_i64(i32 %addr_arg) {
-entry:
- %__1 = inttoptr i32 %addr_arg to i64*
- %iv = load i64, i64* %__1, align 1
- ret void
-
-; CHECK: Initial CFG
-; CHECK: entry:
-; CHECK-NEXT: %iv = load i64, i64* %addr_arg, align 1
-; CHECK-NEXT: ret void
-}
-
-; MIPS32-LABEL: load_i64
-; MIPS32: lw [[BASE:.*]],
-; MIPS32-NEXT: lw {{.*}},0([[BASE]])
-; MIPS32-NEXT: lw {{.*}},4([[BASE]])
-
-define internal void @load_i32(i32 %addr_arg) {
-entry:
- %__1 = inttoptr i32 %addr_arg to i32*
- %iv = load i32, i32* %__1, align 1
- ret void
-
-; CHECK: Initial CFG
-; CHECK: entry:
-; CHECK-NEXT: %iv = load i32, i32* %addr_arg, align 1
-; CHECK-NEXT: ret void
-}
-
-; MIPS32-LABEL: load_i32
-; MIPS32: lw {{.*}},0({{.*}})
-
-define internal void @load_i16(i32 %addr_arg) {
-entry:
- %__1 = inttoptr i32 %addr_arg to i16*
- %iv = load i16, i16* %__1, align 1
- ret void
-
-; CHECK: Initial CFG
-; CHECK: entry:
-; CHECK-NEXT: %iv = load i16, i16* %addr_arg, align 1
-; CHECK-NEXT: ret void
-}
-
-; MIPS32-LABEL: load_i16
-; MIPS32: lh {{.*}},0({{.*}})
-
-define internal void @load_i8(i32 %addr_arg) {
-entry:
- %__1 = inttoptr i32 %addr_arg to i8*
- %iv = load i8, i8* %__1, align 1
- ret void
-
-; CHECK: Initial CFG
-; CHECK: entry:
-; CHECK-NEXT: %iv = load i8, i8* %addr_arg, align 1
-; CHECK-NEXT: ret void
-}
-
-; MIPS32-LABEL: load_i8
-; MIPS32: lb {{.*}},0({{.*}})
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/load_cast.ll b/third_party/subzero/tests_lit/llvm2ice_tests/load_cast.ll
deleted file mode 100644
index 07e7173..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/load_cast.ll
+++ /dev/null
@@ -1,266 +0,0 @@
-; Tests desired and undesired folding of load instructions into cast
-; instructions. The folding is only done when liveness analysis is performed,
-; so only O2 is tested.
-
-; RUN: %p2i --filetype=obj --disassemble -i %s --args -O2 | FileCheck %s
-
-; Not testing trunc, or 32-bit bitcast, because the lowered code uses pretty
-; much the same mov instructions regardless of whether folding is done.
-
-define internal i32 @zext_fold(i32 %arg) {
-entry:
- %ptr = add i32 %arg, 200
- %addr = inttoptr i32 %ptr to i8*
- %load = load i8, i8* %addr, align 1
- %result = zext i8 %load to i32
- ret i32 %result
-}
-; CHECK-LABEL: zext_fold
-; CHECK: movzx {{.*}},BYTE PTR [{{.*}}+0xc8]
-
-define internal i32 @zext_nofold(i32 %arg) {
-entry:
- %ptr = add i32 %arg, 200
- %addr = inttoptr i32 %ptr to i8*
- %load = load i8, i8* %addr, align 1
- %tmp1 = zext i8 %load to i32
- %tmp2 = zext i8 %load to i32
- %result = add i32 %tmp1, %tmp2
- ret i32 %result
-}
-; Test that load folding does not happen.
-; CHECK-LABEL: zext_nofold
-; CHECK-NOT: movzx {{.*}},BYTE PTR [{{.*}}+0xc8]
-
-define internal i32 @sext_fold(i32 %arg) {
-entry:
- %ptr = add i32 %arg, 200
- %addr = inttoptr i32 %ptr to i8*
- %load = load i8, i8* %addr, align 1
- %result = sext i8 %load to i32
- ret i32 %result
-}
-; CHECK-LABEL: sext_fold
-; CHECK: movsx {{.*}},BYTE PTR [{{.*}}+0xc8]
-
-define internal i32 @sext_nofold(i32 %arg) {
-entry:
- %ptr = add i32 %arg, 200
- %addr = inttoptr i32 %ptr to i8*
- %load = load i8, i8* %addr, align 1
- %tmp1 = sext i8 %load to i32
- %tmp2 = sext i8 %load to i32
- %result = add i32 %tmp1, %tmp2
- ret i32 %result
-}
-; Test that load folding does not happen.
-; CHECK-LABEL: sext_nofold
-; CHECK-NOT: movsx {{.*}},BYTE PTR [{{.*}}+0xc8]
-
-define internal float @fptrunc_fold(i32 %arg) {
-entry:
- %ptr = add i32 %arg, 200
- %addr = inttoptr i32 %ptr to double*
- %load = load double, double* %addr, align 8
- %result = fptrunc double %load to float
- ret float %result
-}
-; CHECK-LABEL: fptrunc_fold
-; CHECK: cvtsd2ss {{.*}},QWORD PTR [{{.*}}+0xc8]
-
-define internal float @fptrunc_nofold(i32 %arg) {
-entry:
- %ptr = add i32 %arg, 200
- %addr = inttoptr i32 %ptr to double*
- %load = load double, double* %addr, align 8
- %tmp1 = fptrunc double %load to float
- %tmp2 = fptrunc double %load to float
- %result = fadd float %tmp1, %tmp2
- ret float %result
-}
-; Test that load folding does not happen.
-; CHECK-LABEL: fptrunc_nofold
-; CHECK-NOT: cvtsd2ss {{.*}},QWORD PTR [{{.*}}+0xc8]
-
-define internal double @fpext_fold(i32 %arg) {
-entry:
- %ptr = add i32 %arg, 200
- %addr = inttoptr i32 %ptr to float*
- %load = load float, float* %addr, align 4
- %result = fpext float %load to double
- ret double %result
-}
-; CHECK-LABEL: fpext_fold
-; CHECK: cvtss2sd {{.*}},DWORD PTR [{{.*}}+0xc8]
-
-define internal double @fpext_nofold(i32 %arg) {
-entry:
- %ptr = add i32 %arg, 200
- %addr = inttoptr i32 %ptr to float*
- %load = load float, float* %addr, align 4
- %tmp1 = fpext float %load to double
- %tmp2 = fpext float %load to double
- %result = fadd double %tmp1, %tmp2
- ret double %result
-}
-; Test that load folding does not happen.
-; CHECK-LABEL: fpext_nofold
-; CHECK-NOT: cvtss2sd {{.*}},DWORD PTR [{{.*}}+0xc8]
-
-define internal i32 @fptoui_fold(i32 %arg) {
-entry:
- %ptr = add i32 %arg, 200
- %addr = inttoptr i32 %ptr to double*
- %load = load double, double* %addr, align 8
- %result = fptoui double %load to i16
- %result2 = zext i16 %result to i32
- ret i32 %result2
-}
-; CHECK-LABEL: fptoui_fold
-; CHECK: cvttsd2si {{.*}},QWORD PTR [{{.*}}+0xc8]
-
-define internal i32 @fptoui_nofold(i32 %arg) {
-entry:
- %ptr = add i32 %arg, 200
- %addr = inttoptr i32 %ptr to double*
- %load = load double, double* %addr, align 8
- %tmp1 = fptoui double %load to i16
- %tmp2 = fptoui double %load to i16
- %result = add i16 %tmp1, %tmp2
- %result2 = zext i16 %result to i32
- ret i32 %result2
-}
-; Test that load folding does not happen.
-; CHECK-LABEL: fptoui_nofold
-; CHECK-NOT: cvttsd2si {{.*}},QWORD PTR [{{.*}}+0xc8]
-
-define internal i32 @fptosi_fold(i32 %arg) {
-entry:
- %ptr = add i32 %arg, 200
- %addr = inttoptr i32 %ptr to double*
- %load = load double, double* %addr, align 8
- %result = fptosi double %load to i16
- %result2 = zext i16 %result to i32
- ret i32 %result2
-}
-; CHECK-LABEL: fptosi_fold
-; CHECK: cvttsd2si {{.*}},QWORD PTR [{{.*}}+0xc8]
-
-define internal i32 @fptosi_nofold(i32 %arg) {
-entry:
- %ptr = add i32 %arg, 200
- %addr = inttoptr i32 %ptr to double*
- %load = load double, double* %addr, align 8
- %tmp1 = fptosi double %load to i16
- %tmp2 = fptosi double %load to i16
- %result = add i16 %tmp1, %tmp2
- %result2 = zext i16 %result to i32
- ret i32 %result2
-}
-; Test that load folding does not happen.
-; CHECK-LABEL: fptosi_nofold
-; CHECK-NOT: cvttsd2si {{.*}},QWORD PTR [{{.*}}+0xc8]
-
-define internal double @uitofp_fold(i32 %arg) {
-entry:
- %ptr = add i32 %arg, 200
- %addr = inttoptr i32 %ptr to i16*
- %load = load i16, i16* %addr, align 1
- %result = uitofp i16 %load to double
- ret double %result
-}
-; CHECK-LABEL: uitofp_fold
-; CHECK: movzx {{.*}},WORD PTR [{{.*}}+0xc8]
-
-define internal double @uitofp_nofold(i32 %arg) {
-entry:
- %ptr = add i32 %arg, 200
- %addr = inttoptr i32 %ptr to i16*
- %load = load i16, i16* %addr, align 1
- %tmp1 = uitofp i16 %load to double
- %tmp2 = uitofp i16 %load to double
- %result = fadd double %tmp1, %tmp2
- ret double %result
-}
-; Test that load folding does not happen.
-; CHECK-LABEL: uitofp_nofold
-; CHECK-NOT: movzx {{.*}},WORD PTR [{{.*}}+0xc8]
-
-define internal double @sitofp_fold(i32 %arg) {
-entry:
- %ptr = add i32 %arg, 200
- %addr = inttoptr i32 %ptr to i16*
- %load = load i16, i16* %addr, align 1
- %result = sitofp i16 %load to double
- ret double %result
-}
-; CHECK-LABEL: sitofp_fold
-; CHECK: movsx {{.*}},WORD PTR [{{.*}}+0xc8]
-
-define internal double @sitofp_nofold(i32 %arg) {
-entry:
- %ptr = add i32 %arg, 200
- %addr = inttoptr i32 %ptr to i16*
- %load = load i16, i16* %addr, align 1
- %tmp1 = sitofp i16 %load to double
- %tmp2 = sitofp i16 %load to double
- %result = fadd double %tmp1, %tmp2
- ret double %result
-}
-; Test that load folding does not happen.
-; CHECK-LABEL: sitofp_nofold
-; CHECK-NOT: movsx {{.*}},WORD PTR [{{.*}}+0xc8]
-
-define internal double @bitcast_i64_fold(i32 %arg) {
-entry:
- %ptr = add i32 %arg, 200
- %addr = inttoptr i32 %ptr to i64*
- %load = load i64, i64* %addr, align 1
- %result = bitcast i64 %load to double
- ret double %result
-}
-; CHECK-LABEL: bitcast_i64_fold
-; CHECK: movq {{.*}},QWORD PTR [{{.*}}+0xc8]
-
-define internal double @bitcast_i64_nofold(i32 %arg) {
-entry:
- %ptr = add i32 %arg, 200
- %addr = inttoptr i32 %ptr to i64*
- %load = load i64, i64* %addr, align 1
- %tmp1 = bitcast i64 %load to double
- %tmp2 = bitcast i64 %load to double
- %result = fadd double %tmp1, %tmp2
- ret double %result
-}
-; Test that load folding does not happen.
-; CHECK-LABEL: bitcast_i64_nofold
-; CHECK-NOT: movq {{.*}},QWORD PTR [{{.*}}+0xc8]
-
-define internal i64 @bitcast_double_fold(i32 %arg) {
-entry:
- %ptr = add i32 %arg, 200
- %addr = inttoptr i32 %ptr to double*
- %load = load double, double* %addr, align 8
- %result = bitcast double %load to i64
- ret i64 %result
-}
-; CHECK-LABEL: bitcast_double_fold
-; CHECK-NOT: QWORD PTR
-; CHECK: mov {{.*}},DWORD PTR [{{.*}}+0xc8]
-; CHECK: mov {{.*}},DWORD PTR [{{.*}}+0xcc]
-; CHECK-NOT: QWORD PTR
-
-define internal i64 @bitcast_double_nofold(i32 %arg) {
-entry:
- %ptr = add i32 %arg, 200
- %addr = inttoptr i32 %ptr to double*
- %load = load double, double* %addr, align 8
- %tmp1 = bitcast double %load to i64
- %tmp2 = bitcast double %load to i64
- %result = add i64 %tmp1, %tmp2
- ret i64 %result
-}
-; Test that load folding does not happen.
-; CHECK-LABEL: bitcast_double_nofold
-; CHECK: QWORD PTR
-; CHECK: QWORD PTR
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/local-cse.ll b/third_party/subzero/tests_lit/llvm2ice_tests/local-cse.ll
deleted file mode 100644
index b99c8f4..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/local-cse.ll
+++ /dev/null
@@ -1,36 +0,0 @@
-; Tests local-cse on x8632 and x8664
-
-; RUN: %p2i -i %s --filetype=obj --disassemble --target x8632 --args \
-; RUN: -O2 | FileCheck --check-prefix=X8632 \
-; RUN: --check-prefix=X8632EXP %s
-
-; RUN: %p2i -i %s --filetype=obj --disassemble --target x8632 --args \
-; RUN: -O2 -lcse=0| FileCheck --check-prefix=X8632 --check-prefix X8632NOEXP %s
-
-; RUN: %p2i -i %s --filetype=obj --disassemble --target x8664 --args \
-; RUN: -O2 | FileCheck --check-prefix=X8664 \
-; RUN: --check-prefix=X8664EXP %s
-
-; RUN: %p2i -i %s --filetype=obj --disassemble --target x8664 --args \
-; RUN: -O2 -lcse=0| FileCheck --check-prefix=X8664 --check-prefix X8664NOEXP %s
-
-
-define internal i32 @local_cse_test(i32 %a, i32 %b) {
-entry:
- %add1 = add i32 %b, %a
- %add2 = add i32 %b, %a
- %add3 = add i32 %add1, %add2
- ret i32 %add3
-}
-
-; X8632: add
-; X8632: add
-; X8632NOEXP: add
-; X8632EXP-NOT: add
-; X8632: ret
-
-; X8664: add
-; X8664: add
-; X8664NOEXP: add
-; X8664EXP-NOT: add
-; X8664: ret
\ No newline at end of file
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/loop-nest-depth.ll b/third_party/subzero/tests_lit/llvm2ice_tests/loop-nest-depth.ll
deleted file mode 100644
index e43abb9..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/loop-nest-depth.ll
+++ /dev/null
@@ -1,306 +0,0 @@
-; Test the the loop nest depth is correctly calculated for basic blocks.
-
-; REQUIRES: allow_dump
-
-; Single threaded so that the dumps used for checking happen in order.
-; RUN: %p2i --filetype=obj --disassemble -i %s --args -O2 --verbose=loop \
-; RUN: -log=%t --threads=0 && FileCheck %s < %t
-
-define internal void @test_single_loop(i32 %a32) {
-entry:
- %a = trunc i32 %a32 to i1
- br label %loop0
-
-loop0: ; <-+
- br label %loop1 ; |
-loop1: ; |
- br i1 %a, label %loop0, label %out ; --+
-
-out:
- ret void
-}
-
-; CHECK-LABEL: After loop analysis
-; CHECK-NEXT: entry:
-; CHECK-NEXT: LoopNestDepth = 0
-; CHECK-NEXT: loop0:
-; CHECK-NEXT: LoopNestDepth = 1
-; CHECK-NEXT: loop1:
-; CHECK-NEXT: LoopNestDepth = 1
-; CHECK-NEXT: out:
-; CHECK-NEXT: LoopNestDepth = 0
-; CHECK-LABEL: Before RMW
-
-define internal void @test_single_loop_with_continue(i32 %a32, i32 %b32) {
-entry:
- %a = trunc i32 %a32 to i1
- %b = trunc i32 %b32 to i1
- br label %loop0
-
-loop0: ; <-+
- br label %loop1 ; |
-loop1: ; |
- br i1 %a, label %loop0, label %loop2 ; --+
-loop2: ; |
- br i1 %b, label %loop0, label %out ; --+
-
-out:
- ret void
-}
-
-; CHECK-LABEL: After loop analysis
-; CHECK-NEXT: entry:
-; CHECK-NEXT: LoopNestDepth = 0
-; CHECK-NEXT: loop0:
-; CHECK-NEXT: LoopNestDepth = 1
-; CHECK-NEXT: loop1:
-; CHECK-NEXT: LoopNestDepth = 1
-; CHECK-NEXT: loop2:
-; CHECK-NEXT: LoopNestDepth = 1
-; CHECK-NEXT: out:
-; CHECK-NEXT: LoopNestDepth = 0
-; CHECK-LABEL: Before RMW
-
-define internal void @test_multiple_exits(i32 %a32, i32 %b32) {
-entry:
- %a = trunc i32 %a32 to i1
- %b = trunc i32 %b32 to i1
- br label %loop0
-
-loop0: ; <-+
- br label %loop1 ; |
-loop1: ; |
- br i1 %a, label %loop2, label %out ; --+-+
-loop2: ; | |
- br i1 %b, label %loop0, label %out ; --+ |
- ; |
-out: ; <---+
- ret void
-}
-
-; CHECK-LABEL: After loop analysis
-; CHECK-NEXT: entry:
-; CHECK-NEXT: LoopNestDepth = 0
-; CHECK-NEXT: loop0:
-; CHECK-NEXT: LoopNestDepth = 1
-; CHECK-NEXT: loop1:
-; CHECK-NEXT: LoopNestDepth = 1
-; CHECK-NEXT: loop2:
-; CHECK-NEXT: LoopNestDepth = 1
-; CHECK-NEXT: out:
-; CHECK-NEXT: LoopNestDepth = 0
-; CHECK-LABEL: Before RMW
-
-define internal void @test_two_nested_loops(i32 %a32, i32 %b32) {
-entry:
- %a = trunc i32 %a32 to i1
- %b = trunc i32 %b32 to i1
- br label %loop0_0
-
-loop0_0: ; <---+
- br label %loop1_0 ; |
-loop1_0: ; <-+ |
- br label %loop1_1 ; | |
-loop1_1: ; | |
- br i1 %a, label %loop1_0, label %loop0_1 ; --+ |
-loop0_1: ; |
- br i1 %b, label %loop0_0, label %out ; ----+
-
-out:
- ret void
-}
-
-; CHECK-LABEL: After loop analysis
-; CHECK-NEXT: entry:
-; CHECK-NEXT: LoopNestDepth = 0
-; CHECK-NEXT: loop0_0:
-; CHECK-NEXT: LoopNestDepth = 1
-; CHECK-NEXT: loop1_0:
-; CHECK-NEXT: LoopNestDepth = 2
-; CHECK-NEXT: loop1_1:
-; CHECK-NEXT: LoopNestDepth = 2
-; CHECK-NEXT: loop0_1:
-; CHECK-NEXT: LoopNestDepth = 1
-; CHECK-NEXT: out:
-; CHECK-NEXT: LoopNestDepth = 0
-; CHECK-LABEL: Before RMW
-
-define internal void @test_two_nested_loops_with_continue(i32 %a32, i32 %b32,
- i32 %c32) {
-entry:
- %a = trunc i32 %a32 to i1
- %b = trunc i32 %b32 to i1
- %c = trunc i32 %c32 to i1
- br label %loop0_0
-
-loop0_0: ; <---+
- br label %loop1_0 ; |
-loop1_0: ; <-+ |
- br label %loop1_1 ; | |
-loop1_1: ; | |
- br i1 %a, label %loop1_0, label %loop1_2 ; --+ |
-loop1_2: ; | |
- br i1 %a, label %loop1_0, label %loop0_1 ; --+ |
-loop0_1: ; |
- br i1 %b, label %loop0_0, label %out ; ----+
-
-out:
- ret void
-}
-
-; CHECK-LABEL: After loop analysis
-; CHECK-NEXT: entry:
-; CHECK-NEXT: LoopNestDepth = 0
-; CHECK-NEXT: loop0_0:
-; CHECK-NEXT: LoopNestDepth = 1
-; CHECK-NEXT: loop1_0:
-; CHECK-NEXT: LoopNestDepth = 2
-; CHECK-NEXT: loop1_1:
-; CHECK-NEXT: LoopNestDepth = 2
-; CHECK-NEXT: loop1_2:
-; CHECK-NEXT: LoopNestDepth = 2
-; CHECK-NEXT: loop0_1:
-; CHECK-NEXT: LoopNestDepth = 1
-; CHECK-NEXT: out:
-; CHECK-NEXT: LoopNestDepth = 0
-; CHECK-LABEL: Before RMW
-
-define internal void @test_multiple_nested_loops(i32 %a32, i32 %b32) {
-entry:
- %a = trunc i32 %a32 to i1
- %b = trunc i32 %b32 to i1
- br label %loop0_0
-
-loop0_0: ; <---+
- br label %loop1_0 ; |
-loop1_0: ; <-+ |
- br label %loop1_1 ; | |
-loop1_1: ; | |
- br i1 %a, label %loop1_0, label %loop0_1 ; --+ |
-loop0_1: ; |
- br label %loop2_0 ; |
-loop2_0: ; <-+ |
- br label %loop2_1 ; | |
-loop2_1: ; | |
- br i1 %a, label %loop2_0, label %loop0_2 ; --+ |
-loop0_2: ; |
- br i1 %b, label %loop0_0, label %out ; ----+
-
-out:
- ret void
-}
-
-; CHECK-LABEL: After loop analysis
-; CHECK-NEXT: entry:
-; CHECK-NEXT: LoopNestDepth = 0
-; CHECK-NEXT: loop0_0:
-; CHECK-NEXT: LoopNestDepth = 1
-; CHECK-NEXT: loop1_0:
-; CHECK-NEXT: LoopNestDepth = 2
-; CHECK-NEXT: loop1_1:
-; CHECK-NEXT: LoopNestDepth = 2
-; CHECK-NEXT: loop0_1:
-; CHECK-NEXT: LoopNestDepth = 1
-; CHECK-NEXT: loop2_0:
-; CHECK-NEXT: LoopNestDepth = 2
-; CHECK-NEXT: loop2_1:
-; CHECK-NEXT: LoopNestDepth = 2
-; CHECK-NEXT: loop0_2:
-; CHECK-NEXT: LoopNestDepth = 1
-; CHECK-NEXT: out:
-; CHECK-NEXT: LoopNestDepth = 0
-; CHECK-LABEL: Before RMW
-
-define internal void @test_three_nested_loops(i32 %a32, i32 %b32, i32 %c32) {
-entry:
- %a = trunc i32 %a32 to i1
- %b = trunc i32 %b32 to i1
- %c = trunc i32 %c32 to i1
- br label %loop0_0
-
-loop0_0: ; <-----+
- br label %loop1_0 ; |
-loop1_0: ; <---+ |
- br label %loop2_0 ; | |
-loop2_0: ; <-+ | |
- br label %loop2_1 ; | | |
-loop2_1: ; | | |
- br i1 %a, label %loop2_0, label %loop1_1 ; --+ | |
-loop1_1: ; | |
- br i1 %b, label %loop1_0, label %loop0_1 ; ----+ |
-loop0_1: ; |
- br i1 %c, label %loop0_0, label %out ; ------+
-
-out:
- ret void
-}
-
-; CHECK-LABEL: After loop analysis
-; CHECK-NEXT: entry:
-; CHECK-NEXT: LoopNestDepth = 0
-; CHECK-NEXT: loop0_0:
-; CHECK-NEXT: LoopNestDepth = 1
-; CHECK-NEXT: loop1_0:
-; CHECK-NEXT: LoopNestDepth = 2
-; CHECK-NEXT: loop2_0:
-; CHECK-NEXT: LoopNestDepth = 3
-; CHECK-NEXT: loop2_1:
-; CHECK-NEXT: LoopNestDepth = 3
-; CHECK-NEXT: loop1_1:
-; CHECK-NEXT: LoopNestDepth = 2
-; CHECK-NEXT: loop0_1:
-; CHECK-NEXT: LoopNestDepth = 1
-; CHECK-NEXT: out:
-; CHECK-NEXT: LoopNestDepth = 0
-; CHECK-LABEL: Before RMW
-
-define internal void @test_diamond(i32 %a32) {
-entry:
- %a = trunc i32 %a32 to i1
- br i1 %a, label %left, label %right
-
-left:
- br label %out
-
-right:
- br label %out
-
-out:
- ret void
-}
-
-; CHECK-LABEL: After loop analysis
-; CHECK-NEXT: entry:
-; CHECK-NEXT: LoopNestDepth = 0
-; CHECK-NEXT: left:
-; CHECK-NEXT: LoopNestDepth = 0
-; CHECK-NEXT: right:
-; CHECK-NEXT: LoopNestDepth = 0
-; CHECK-NEXT: out:
-; CHECK-NEXT: LoopNestDepth = 0
-; CHECK-LABEL: Before RMW
-
-define internal void @test_single_block_loop(i32 %count) {
-entry:
- br label %body
-body:
-; %i = phi i32 [ 0, %entry ], [ %inc, %body ]
-; A normal loop would have a phi instruction like above for the induction
-; variable, but that may introduce new basic blocks due to phi edge splitting,
-; so we use an alternative definition for %i to make the test more clear.
- %i = add i32 %count, 1
- %inc = add i32 %i, 1
- %cmp = icmp slt i32 %inc, %count
- br i1 %cmp, label %body, label %exit
-exit:
- ret void
-}
-
-; CHECK-LABEL: After loop analysis
-; CHECK-NEXT: entry:
-; CHECK-NEXT: LoopNestDepth = 0
-; CHECK-NEXT: body:
-; CHECK-NEXT: LoopNestDepth = 1
-; CHECK-NEXT: exit:
-; CHECK-NEXT: LoopNestDepth = 0
-; CHECK-LABEL: Before RMW
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/mangle.ll b/third_party/subzero/tests_lit/llvm2ice_tests/mangle.ll
deleted file mode 100644
index 1ba73f7..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/mangle.ll
+++ /dev/null
@@ -1,145 +0,0 @@
-; Tests the Subzero "name mangling" when using the "pnacl-sz --prefix"
-; option. Also does a quick smoke test of -ffunction-sections.
-
-; REQUIRES: allow_dump
-; RUN: %p2i -i %s --args --verbose none -ffunction-sections | FileCheck %s
-; TODO(stichnot): The following line causes this test to fail.
-; RUIN: %p2i --assemble --disassemble -i %s --args --verbose none \
-; RUIN: | FileCheck %s
-; RUN: %p2i -i %s --args --verbose none --prefix Subzero -ffunction-sections \
-; RUN: | FileCheck --check-prefix=MANGLE %s
-
-define internal void @FuncC(i32 %i) {
-entry:
- ret void
-}
-; FuncC is a C symbol that isn't recognized as a C++ mangled symbol.
-; CHECK-LABEL: .text.FuncC
-; CHECK: FuncC:
-; MANGLE-LABEL: .text.SubzeroFuncC
-; MANGLE: SubzeroFuncC:
-
-define internal void @_ZN13TestNamespace4FuncEi(i32 %i) {
-entry:
- ret void
-}
-; This is Func(int) nested inside namespace TestNamespace.
-; CHECK-LABEL: .text._ZN13TestNamespace4FuncEi
-; CHECK: _ZN13TestNamespace4FuncEi:
-; MANGLE-LABEL: .text._ZN7Subzero13TestNamespace4FuncEi
-; MANGLE: _ZN7Subzero13TestNamespace4FuncEi:
-
-define internal void @_ZN13TestNamespace15NestedNamespace4FuncEi(i32 %i) {
-entry:
- ret void
-}
-; This is Func(int) nested inside two namespaces.
-; CHECK-LABEL: .text._ZN13TestNamespace15NestedNamespace4FuncEi
-; CHECK: _ZN13TestNamespace15NestedNamespace4FuncEi:
-; MANGLE-LABEL: .text._ZN7Subzero13TestNamespace15NestedNamespace4FuncEi
-; MANGLE: _ZN7Subzero13TestNamespace15NestedNamespace4FuncEi:
-
-define internal void @_Z13FuncCPlusPlusi(i32 %i) {
-entry:
- ret void
-}
-; This is a non-nested, mangled C++ symbol.
-; CHECK-LABEL: .text._Z13FuncCPlusPlusi
-; CHECK: _Z13FuncCPlusPlusi:
-; MANGLE-LABEL: .text._ZN7Subzero13FuncCPlusPlusEi
-; MANGLE: _ZN7Subzero13FuncCPlusPlusEi:
-
-define internal void @_ZN12_GLOBAL__N_18FuncAnonEi(i32 %i) {
-entry:
- ret void
-}
-; This is FuncAnon(int) nested inside an anonymous namespace.
-; CHECK-LABEL: .text._ZN12_GLOBAL__N_18FuncAnonEi
-; CHECK: _ZN12_GLOBAL__N_18FuncAnonEi:
-; MANGLE-LABEL: .text._ZN7Subzero12_GLOBAL__N_18FuncAnonEi
-; MANGLE: _ZN7Subzero12_GLOBAL__N_18FuncAnonEi:
-
-; Now for the illegitimate examples.
-
-; Test for _ZN with no suffix. Don't crash, prepend Subzero.
-define internal void @_ZN(i32 %i) {
-entry:
- ret void
-}
-; MANGLE-LABEL: .text.Subzero_ZN
-; MANGLE: Subzero_ZN:
-
-; Test for _Z<len><str> where <len> is smaller than it should be.
-define internal void @_Z12FuncCPlusPlusi(i32 %i) {
-entry:
- ret void
-}
-; MANGLE-LABEL: .text._ZN7Subzero12FuncCPlusPluEsi
-; MANGLE: _ZN7Subzero12FuncCPlusPluEsi:
-
-; Test for _Z<len><str> where <len> is slightly larger than it should be.
-define internal void @_Z14FuncCPlusPlusi(i32 %i) {
-entry:
- ret void
-}
-; MANGLE-LABEL: .text._ZN7Subzero14FuncCPlusPlusiE
-; MANGLE: _ZN7Subzero14FuncCPlusPlusiE:
-
-; Test for _Z<len><str> where <len> is much larger than it should be.
-define internal void @_Z114FuncCPlusPlusi(i32 %i) {
-entry:
- ret void
-}
-; MANGLE-LABEL: .text.Subzero_Z114FuncCPlusPlusi
-; MANGLE: Subzero_Z114FuncCPlusPlusi:
-
-; Test for _Z<len><str> where we try to overflow the uint32_t holding <len>.
-define internal void @_Z4294967296FuncCPlusPlusi(i32 %i) {
-entry:
- ret void
-}
-; MANGLE-LABEL: .text.Subzero_Z4294967296FuncCPlusPlusi
-; MANGLE: Subzero_Z4294967296FuncCPlusPlusi:
-
-; Test for _Z<len><str> where <len> is 0.
-define internal void @_Z0FuncCPlusPlusi(i32 %i) {
-entry:
- ret void
-}
-; MANGLE-LABEL: .text._ZN7Subzero0EFuncCPlusPlusi
-; MANGLE: _ZN7Subzero0EFuncCPlusPlusi:
-
-; Test for _Z<len><str> where <len> is -1. LLVM explicitly allows the
-; '-' character in identifiers.
-
-define internal void @_Z-1FuncCPlusPlusi(i32 %i) {
-entry:
- ret void
-}
-; MANGLE-LABEL: .text.Subzero_Z-1FuncCPlusPlusi
-; MANGLE: Subzero_Z-1FuncCPlusPlusi:
-
-
-; Test for substitution incrementing. This single test captures:
-; S<num>_ ==> S<num+1>_ for single-digit <num>
-; S_ ==> S0_
-; String length increase, e.g. SZZZ_ ==> S1000_
-; At least one digit wrapping without length increase, e.g. SZ9ZZ_ ==> SZA00_
-; Unrelated identifiers containing S[0-9A-Z]* , e.g. MyClassS1x
-; A proper substring of S<num>_ at the end of the string
-; (to test parser edge cases)
-
-define internal void @_Z3fooP10MyClassS1xP10MyClassS2xRS_RS1_S_S1_SZZZ_SZ9ZZ_S12345() {
-; MANGLE-LABEL: .text._ZN7Subzero3fooEP10MyClassS1xP10MyClassS2xRS0_RS2_S0_S2_S1000_SZA00_S12345
-; MANGLE: _ZN7Subzero3fooEP10MyClassS1xP10MyClassS2xRS0_RS2_S0_S2_S1000_SZA00_S12345:
-entry:
- ret void
-}
-
-; Test that unmangled (non-C++) strings don't have substitutions updated.
-define internal void @foo_S_S0_SZ_S() {
-; MANGLE-LABEL: .text.Subzerofoo_S_S0_SZ_S
-; MANGLE: Subzerofoo_S_S0_SZ_S:
-entry:
- ret void
-}
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/mips-address-mode-opt.ll b/third_party/subzero/tests_lit/llvm2ice_tests/mips-address-mode-opt.ll
deleted file mode 100644
index 2563c74..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/mips-address-mode-opt.ll
+++ /dev/null
@@ -1,44 +0,0 @@
-; This file checks support for address mode optimization.
-; This test file is same as address-mode-opt.ll however the functions in this
-; file are relevant to MIPS only.
-
-; RUN: %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command %p2i --filetype=asm --assemble --disassemble \
-; RUN: --target mips32 -i %s --args -O2 \
-; RUN: -allow-externally-defined-symbols \
-; RUN: | %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command FileCheck --check-prefix MIPS32 %s
-
-define internal float @load_arg_plus_offset(float* %arg) {
-entry:
- %arg.int = ptrtoint float* %arg to i32
- %addr.int = add i32 %arg.int, 16
- %addr.ptr = inttoptr i32 %addr.int to float*
- %addr.load = load float, float* %addr.ptr, align 4
- ret float %addr.load
-}
-; MIPS32-LABEL: load_arg_plus_offset
-; MIPS32: lwc1 $f0,16(a0)
-
-define internal float @load_arg_minus_offset(float* %arg) {
-entry:
- %arg.int = ptrtoint float* %arg to i32
- %addr.int = sub i32 %arg.int, 16
- %addr.ptr = inttoptr i32 %addr.int to float*
- %addr.load = load float, float* %addr.ptr, align 4
- ret float %addr.load
-}
-; MIPS32-LABEL: load_arg_minus_offset
-; MIPS32 lwc1 $f0,-16(a0)
-
-define internal float @address_mode_opt_chaining(float* %arg) {
-entry:
- %arg.int = ptrtoint float* %arg to i32
- %addr1.int = add i32 12, %arg.int
- %addr2.int = sub i32 %addr1.int, 4
- %addr2.ptr = inttoptr i32 %addr2.int to float*
- %addr2.load = load float, float* %addr2.ptr, align 4
- ret float %addr2.load
-}
-; MIPS32-LABEL: address_mode_opt_chaining
-; MIPS32 lwc1 $f0,8(a0)
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/mips-legalization.ll b/third_party/subzero/tests_lit/llvm2ice_tests/mips-legalization.ll
deleted file mode 100644
index cc9414d..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/mips-legalization.ll
+++ /dev/null
@@ -1,84 +0,0 @@
-; This file checks support for legalization in MIPS.
-
-; REQUIRES: allow_dump
-
-; RUN: %if --need=target_MIPS32 \
-; RUN: --command %p2i --filetype=asm --assemble --disassemble \
-; RUN: --target mips32 -i %s --args -O2 \
-; RUN: | %if --need=target_MIPS32 \
-; RUN: --command FileCheck --check-prefix MIPS32 %s
-
-define internal i32 @legalization(i32 %a, i32 %b, i32 %c, i32 %d,
- i32 %e, i32 %f) {
-entry:
- %a.addr = alloca i8, i32 4, align 4
- %b.addr = alloca i8, i32 4, align 4
- %c.addr = alloca i8, i32 4, align 4
- %d.addr = alloca i8, i32 4, align 4
- %e.addr = alloca i8, i32 4, align 4
- %f.addr = alloca i8, i32 4, align 4
- %r1 = alloca i8, i32 4, align 4
- %r2 = alloca i8, i32 4, align 4
- %r3 = alloca i8, i32 4, align 4
- %a.addr.bc = bitcast i8* %a.addr to i32*
- store i32 %a, i32* %a.addr.bc, align 1
- %b.addr.bc = bitcast i8* %b.addr to i32*
- store i32 %b, i32* %b.addr.bc, align 1
- %c.addr.bc = bitcast i8* %c.addr to i32*
- store i32 %c, i32* %c.addr.bc, align 1
- %d.addr.bc = bitcast i8* %d.addr to i32*
- store i32 %d, i32* %d.addr.bc, align 1
- %e.addr.bc = bitcast i8* %e.addr to i32*
- store i32 %e, i32* %e.addr.bc, align 1
- %f.addr.bc = bitcast i8* %f.addr to i32*
- store i32 %f, i32* %f.addr.bc, align 1
- %a.addr.bc1 = bitcast i8* %a.addr to i32*
- %0 = load i32, i32* %a.addr.bc1, align 1
- %f.addr.bc2 = bitcast i8* %f.addr to i32*
- %1 = load i32, i32* %f.addr.bc2, align 1
- %add = add i32 %0, %1
- %r1.bc = bitcast i8* %r1 to i32*
- store i32 %add, i32* %r1.bc, align 1
- %b.addr.bc3 = bitcast i8* %b.addr to i32*
- %2 = load i32, i32* %b.addr.bc3, align 1
- %e.addr.bc4 = bitcast i8* %e.addr to i32*
- %3 = load i32, i32* %e.addr.bc4, align 1
- %add1 = add i32 %2, %3
- %r2.bc = bitcast i8* %r2 to i32*
- store i32 %add1, i32* %r2.bc, align 1
- %r1.bc5 = bitcast i8* %r1 to i32*
- %4 = load i32, i32* %r1.bc5, align 1
- %r2.bc6 = bitcast i8* %r2 to i32*
- %5 = load i32, i32* %r2.bc6, align 1
- %add2 = add i32 %4, %5
- %r3.bc = bitcast i8* %r3 to i32*
- store i32 %add2, i32* %r3.bc, align 1
- %r3.bc7 = bitcast i8* %r3 to i32*
- %6 = load i32, i32* %r3.bc7, align 1
- ret i32 %6
-}
-; MIPS32-LABEL: legalization
-; MIPS32: addiu sp,sp,-48
-; MIPS32: lw [[ARG_E:.*]],64(sp)
-; MIPS32: lw [[ARG_F:.*]],68(sp)
-; MIPS32: sw a0,0(sp)
-; MIPS32: sw a1,4(sp)
-; MIPS32: sw a2,8(sp)
-; MIPS32: sw a3,12(sp)
-; MIPS32: sw [[ARG_E]],16(sp)
-; MIPS32: sw [[ARG_F]],20(sp)
-; MIPS32: lw [[TMP_A:.*]],0(sp)
-; MIPS32: lw [[TMP_F:.*]],20(sp)
-; MIPS32: addu [[ADD1:.*]],[[TMP_A]],[[TMP_F]]
-; MIPS32: sw [[ADD1]],24(sp)
-; MIPS32: lw [[TMP_B:.*]],4(sp)
-; MIPS32: lw [[TMP_E:.*]],16(sp)
-; MIPS32: addu [[ADD2:.*]],[[TMP_B]],[[TMP_E]]
-; MIPS32: sw [[ADD2]],28(sp)
-; MIPS32: lw [[TMP_ADD1:.*]],24(sp)
-; MIPS32: lw [[TMP_ADD2:.*]],28(sp)
-; MIPS32: addu [[ADD3:.*]],[[TMP_ADD1]],[[TMP_ADD2]]
-; MIPS32: sw [[ADD3]],32(sp)
-; MIPS32: lw v0,32(sp)
-; MIPS32: addiu sp,sp,48
-; MIPS32: jr ra
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/multidef_kill.ll b/third_party/subzero/tests_lit/llvm2ice_tests/multidef_kill.ll
deleted file mode 100644
index bfc907e..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/multidef_kill.ll
+++ /dev/null
@@ -1,42 +0,0 @@
-; This tests against a lowering error in a multiply instruction that produces
-; results in a low and high register. This is usually lowered as a mul
-; instruction whose dest contains the low portion, and a FakeDef of the high
-; portion. The problem is that if the high portion is unused (e.g. the multiply
-; is followed by a truncation), the FakeDef may be eliminated, and the register
-; allocator may assign the high register to a variable that is live across the
-; mul instruction. This is incorrect because the mul instruction smashes the
-; register.
-
-; REQUIRES: allow_dump
-
-; RUN: %p2i --target x8632 -i %s --filetype=asm --args -O2 -asm-verbose \
-; RUN: --split-local-vars=0 \
-; RUN: --reg-use=eax,edx -reg-reserve | FileCheck --check-prefix=X8632 %s
-; RUN: %p2i --target arm32 -i %s --filetype=asm --args -O2 -asm-verbose \
-; RUN: | FileCheck --check-prefix=ARM32 %s
-
-define internal i32 @mul(i64 %a, i64 %b, i32 %c) {
- ; Force an early use of %c.
- store i32 %c, i32* undef, align 1
- %m = mul i64 %a, %b
- %t = trunc i64 %m to i32
- ; Make many uses of %c to give it high weight.
- %t1 = add i32 %t, %c
- %t2 = add i32 %t1, %c
- %t3 = add i32 %t2, %c
- ret i32 %t3
-}
-
-; For x8632, we want asm-verbose to print the stack offset assignment for lv$c
-; ("local variable 'c'") in the prolog, and then have at least one use of lv$c
-; in the body, i.e. don't register-allocate edx to %c.
-
-; X8632-LABEL: mul
-; X8632: lv$c =
-; X8632: lv$c
-
-; For arm32, the failure would manifest as a translation error - no register
-; being allocated to the high operand, so we just check for successful
-; translation.
-
-; ARM32-LABEL: mul
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/nacl-atomic-cmpxchg-optimization.ll b/third_party/subzero/tests_lit/llvm2ice_tests/nacl-atomic-cmpxchg-optimization.ll
deleted file mode 100644
index 3e2e743..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/nacl-atomic-cmpxchg-optimization.ll
+++ /dev/null
@@ -1,136 +0,0 @@
-; This tests the optimization of atomic cmpxchg w/ following cmp + branches.
-
-; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 \
-; RUN: -allow-externally-defined-symbols | FileCheck --check-prefix=O2 %s
-; RUN: %p2i -i %s --filetype=obj --disassemble --args -Om1 \
-; RUN: -allow-externally-defined-symbols | FileCheck --check-prefix=OM1 %s
-
-declare i32 @llvm.nacl.atomic.cmpxchg.i32(i32*, i32, i32, i32, i32)
-
-
-; Test that a cmpxchg followed by icmp eq and branch can be optimized to
-; reuse the flags set by the cmpxchg instruction itself.
-; This is only expected to work w/ O2, based on lightweight liveness.
-; (Or if we had other means to detect the only use).
-declare void @use_value(i32)
-
-define internal i32 @test_atomic_cmpxchg_loop(i32 %iptr, i32 %expected,
- i32 %desired) {
-entry:
- br label %loop
-
-loop:
- %expected_loop = phi i32 [ %expected, %entry ], [ %old, %loop ]
- %succeeded_first_try = phi i32 [ 1, %entry ], [ 2, %loop ]
- %ptr = inttoptr i32 %iptr to i32*
- %old = call i32 @llvm.nacl.atomic.cmpxchg.i32(i32* %ptr, i32 %expected_loop,
- i32 %desired, i32 6, i32 6)
- %success = icmp eq i32 %expected_loop, %old
- br i1 %success, label %done, label %loop
-
-done:
- call void @use_value(i32 %old)
- ret i32 %succeeded_first_try
-}
-; O2-LABEL: test_atomic_cmpxchg_loop
-; O2: lock cmpxchg DWORD PTR [e{{[^a].}}],e{{[^a]}}
-; O2-NEXT: j{{e|ne}}
-; Make sure the call isn't accidentally deleted.
-; O2: call
-;
-; Check that the unopt version does have a cmp
-; OM1-LABEL: test_atomic_cmpxchg_loop
-; OM1: lock cmpxchg DWORD PTR [e{{[^a].}}],e{{[^a]}}
-; OM1: cmp
-; OM1: sete
-; OM1: call
-
-; Still works if the compare operands are flipped.
-define internal i32 @test_atomic_cmpxchg_loop2(i32 %iptr, i32 %expected,
- i32 %desired) {
-entry:
- br label %loop
-
-loop:
- %expected_loop = phi i32 [ %expected, %entry ], [ %old, %loop ]
- %ptr = inttoptr i32 %iptr to i32*
- %old = call i32 @llvm.nacl.atomic.cmpxchg.i32(i32* %ptr, i32 %expected_loop,
- i32 %desired, i32 6, i32 6)
- %success = icmp eq i32 %old, %expected_loop
- br i1 %success, label %done, label %loop
-
-done:
- ret i32 %old
-}
-; O2-LABEL: test_atomic_cmpxchg_loop2
-; O2: lock cmpxchg DWORD PTR [e{{[^a].}}],e{{[^a]}}
-; O2-NOT: cmp
-; O2: jne
-
-
-; Still works if the compare operands are constants.
-define internal i32 @test_atomic_cmpxchg_loop_const(i32 %iptr, i32 %desired) {
-entry:
- br label %loop
-
-loop:
- %succeeded_first_try = phi i32 [ 1, %entry ], [ 0, %loop ]
- %ptr = inttoptr i32 %iptr to i32*
- %old = call i32 @llvm.nacl.atomic.cmpxchg.i32(i32* %ptr, i32 0,
- i32 %desired, i32 6, i32 6)
- %success = icmp eq i32 %old, 0
- br i1 %success, label %done, label %loop
-
-done:
- ret i32 %succeeded_first_try
-}
-; O2-LABEL: test_atomic_cmpxchg_loop_const
-; O2: lock cmpxchg DWORD PTR [e{{[^a].}}],e{{[^a]}}
-; O2-NEXT: j{{e|ne}}
-
-; This is a case where the flags cannot be reused (compare is for some
-; other condition).
-define internal i32 @test_atomic_cmpxchg_no_opt(i32 %iptr, i32 %expected,
- i32 %desired) {
-entry:
- br label %loop
-
-loop:
- %expected_loop = phi i32 [ %expected, %entry ], [ %old, %loop ]
- %ptr = inttoptr i32 %iptr to i32*
- %old = call i32 @llvm.nacl.atomic.cmpxchg.i32(i32* %ptr, i32 %expected_loop,
- i32 %desired, i32 6, i32 6)
- %success = icmp sgt i32 %old, %expected
- br i1 %success, label %done, label %loop
-
-done:
- ret i32 %old
-}
-; O2-LABEL: test_atomic_cmpxchg_no_opt
-; O2: lock cmpxchg DWORD PTR [e{{[^a].}}],e{{[^a]}}
-; O2: cmp
-; O2: jle
-
-; Another case where the flags cannot be reused (the comparison result
-; is used somewhere else).
-define internal i32 @test_atomic_cmpxchg_no_opt2(i32 %iptr, i32 %expected,
- i32 %desired) {
-entry:
- br label %loop
-
-loop:
- %expected_loop = phi i32 [ %expected, %entry ], [ %old, %loop ]
- %ptr = inttoptr i32 %iptr to i32*
- %old = call i32 @llvm.nacl.atomic.cmpxchg.i32(i32* %ptr, i32 %expected_loop,
- i32 %desired, i32 6, i32 6)
- %success = icmp eq i32 %old, %expected
- br i1 %success, label %done, label %loop
-
-done:
- %r = zext i1 %success to i32
- ret i32 %r
-}
-; O2-LABEL: test_atomic_cmpxchg_no_opt2
-; O2: lock cmpxchg DWORD PTR [e{{[^a].}}],e{{[^a]}}
-; O2: cmp
-; O2: sete
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/nacl-atomic-errors.ll b/third_party/subzero/tests_lit/llvm2ice_tests/nacl-atomic-errors.ll
deleted file mode 100644
index 5d0a9bb..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/nacl-atomic-errors.ll
+++ /dev/null
@@ -1,233 +0,0 @@
-; Test that some errors trigger when the usage of NaCl atomic
-; intrinsics does not match the required ABI.
-; REQUIRES: allow_dump
-
-; RUN: %p2i -i %s --args --verbose none --exit-success -threads=0 2>&1 \
-; RUN: | FileCheck %s
-
-declare i8 @llvm.nacl.atomic.load.i8(i8*, i32)
-declare i16 @llvm.nacl.atomic.load.i16(i16*, i32)
-declare i64 @llvm.nacl.atomic.load.i64(i64*, i32)
-declare void @llvm.nacl.atomic.store.i32(i32, i32*, i32)
-declare void @llvm.nacl.atomic.store.i64(i64, i64*, i32)
-declare i8 @llvm.nacl.atomic.rmw.i8(i32, i8*, i8, i32)
-declare i16 @llvm.nacl.atomic.rmw.i16(i32, i16*, i16, i32)
-declare i32 @llvm.nacl.atomic.rmw.i32(i32, i32*, i32, i32)
-declare i64 @llvm.nacl.atomic.rmw.i64(i32, i64*, i64, i32)
-declare i32 @llvm.nacl.atomic.cmpxchg.i32(i32*, i32, i32, i32, i32)
-declare i64 @llvm.nacl.atomic.cmpxchg.i64(i64*, i64, i64, i32, i32)
-declare void @llvm.nacl.atomic.fence(i32)
-declare i1 @llvm.nacl.atomic.is.lock.free(i32, i8*)
-
-;;; Load
-;;; Check unexpected memory order parameter (release=4 and acq_rel=5
-;;; are disallowed).
-
-define internal i32 @error_atomic_load_8(i32 %iptr) {
-entry:
- %ptr = inttoptr i32 %iptr to i8*
- %i = call i8 @llvm.nacl.atomic.load.i8(i8* %ptr, i32 0)
- %r = zext i8 %i to i32
- ret i32 %r
-}
-; CHECK: Unexpected memory ordering for AtomicLoad
-
-define internal i32 @error_atomic_load_16(i32 %iptr) {
-entry:
- %ptr = inttoptr i32 %iptr to i16*
- %i = call i16 @llvm.nacl.atomic.load.i16(i16* %ptr, i32 4)
- %r = zext i16 %i to i32
- ret i32 %r
-}
-; CHECK: Unexpected memory ordering for AtomicLoad
-
-define internal i64 @error_atomic_load_64(i32 %iptr) {
-entry:
- %ptr = inttoptr i32 %iptr to i64*
- %r = call i64 @llvm.nacl.atomic.load.i64(i64* %ptr, i32 5)
- ret i64 %r
-}
-; CHECK: Unexpected memory ordering for AtomicLoad
-
-
-;;; Store
-;;; consume=2, acquire=3, acq_rel=5 are disallowed
-
-define internal void @error_atomic_store_32(i32 %iptr, i32 %v) {
-entry:
- %ptr = inttoptr i32 %iptr to i32*
- call void @llvm.nacl.atomic.store.i32(i32 %v, i32* %ptr, i32 2)
- ret void
-}
-; CHECK: Unexpected memory ordering for AtomicStore
-
-define internal void @error_atomic_store_64(i32 %iptr, i64 %v) {
-entry:
- %ptr = inttoptr i32 %iptr to i64*
- call void @llvm.nacl.atomic.store.i64(i64 %v, i64* %ptr, i32 3)
- ret void
-}
-; CHECK: Unexpected memory ordering for AtomicStore
-
-define internal void @error_atomic_store_64_const(i32 %iptr) {
-entry:
- %ptr = inttoptr i32 %iptr to i64*
- call void @llvm.nacl.atomic.store.i64(i64 12345678901234, i64* %ptr, i32 5)
- ret void
-}
-; CHECK: Unexpected memory ordering for AtomicStore
-
-;;; RMW
-;;; Test atomic memory order and operation.
-;;; Modes 3:6 allowed.
-
-define internal i32 @error_atomic_rmw_add_8(i32 %iptr, i32 %v) {
-entry:
- %trunc = trunc i32 %v to i8
- %ptr = inttoptr i32 %iptr to i8*
- %a = call i8 @llvm.nacl.atomic.rmw.i8(i32 1, i8* %ptr, i8 %trunc, i32 1)
- %a_ext = zext i8 %a to i32
- ret i32 %a_ext
-}
-; CHECK: Unexpected memory ordering for AtomicRMW
-
-define internal i64 @error_atomic_rmw_add_64(i32 %iptr, i64 %v) {
-entry:
- %ptr = inttoptr i32 %iptr to i64*
- %a = call i64 @llvm.nacl.atomic.rmw.i64(i32 1, i64* %ptr, i64 %v, i32 7)
- ret i64 %a
-}
-; CHECK: Unexpected memory ordering for AtomicRMW
-
-define internal i32 @error_atomic_rmw_add_16(i32 %iptr, i32 %v) {
-entry:
- %trunc = trunc i32 %v to i16
- %ptr = inttoptr i32 %iptr to i16*
- %a = call i16 @llvm.nacl.atomic.rmw.i16(i32 0, i16* %ptr, i16 %trunc, i32 6)
- %a_ext = zext i16 %a to i32
- ret i32 %a_ext
-}
-; CHECK: Unknown AtomicRMW operation
-
-define internal i32 @error_atomic_rmw_add_32(i32 %iptr, i32 %v) {
-entry:
- %ptr = inttoptr i32 %iptr to i32*
- %a = call i32 @llvm.nacl.atomic.rmw.i32(i32 7, i32* %ptr, i32 %v, i32 6)
- ret i32 %a
-}
-; CHECK: Unknown AtomicRMW operation
-
-define internal i32 @error_atomic_rmw_add_32_max(i32 %iptr, i32 %v) {
-entry:
- %ptr = inttoptr i32 %iptr to i32*
- %a = call i32 @llvm.nacl.atomic.rmw.i32(i32 4294967295, i32* %ptr, i32 %v, i32 6)
- ret i32 %a
-}
-; CHECK: Unknown AtomicRMW operation
-
-;;; Cmpxchg
-
-define internal i32 @error_atomic_cmpxchg_32_success(i32 %iptr, i32 %expected,
- i32 %desired) {
-entry:
- %ptr = inttoptr i32 %iptr to i32*
- %old = call i32 @llvm.nacl.atomic.cmpxchg.i32(i32* %ptr, i32 %expected,
- i32 %desired, i32 0, i32 6)
- ret i32 %old
-}
-; CHECK: Unexpected memory ordering for AtomicCmpxchg
-
-define internal i32 @error_atomic_cmpxchg_32_failure(i32 %iptr, i32 %expected,
- i32 %desired) {
-entry:
- %ptr = inttoptr i32 %iptr to i32*
- %old = call i32 @llvm.nacl.atomic.cmpxchg.i32(i32* %ptr, i32 %expected,
- i32 %desired, i32 6, i32 0)
- ret i32 %old
-}
-; CHECK: Unexpected memory ordering for AtomicCmpxchg
-
-define internal i64 @error_atomic_cmpxchg_64_failure(i32 %iptr, i64 %expected,
- i64 %desired) {
-entry:
- %ptr = inttoptr i32 %iptr to i64*
- %old = call i64 @llvm.nacl.atomic.cmpxchg.i64(i64* %ptr, i64 %expected,
- i64 %desired, i32 4, i32 1)
- ret i64 %old
-}
-; CHECK: Unexpected memory ordering for AtomicCmpxchg
-
-;;; Fence and is-lock-free.
-
-define internal void @error_atomic_fence() {
-entry:
- call void @llvm.nacl.atomic.fence(i32 0)
- ret void
-}
-; CHECK: Unexpected memory ordering for AtomicFence
-
-define internal i32 @error_atomic_is_lock_free_var(i32 %iptr, i32 %bs) {
-entry:
- %ptr = inttoptr i32 %iptr to i8*
- %i = call i1 @llvm.nacl.atomic.is.lock.free(i32 %bs, i8* %ptr)
- %r = zext i1 %i to i32
- ret i32 %r
-}
-; CHECK: AtomicIsLockFree byte size should be compile-time const
-
-
-;;; Test bad non-constant memory ordering values.
-
-define internal i32 @error_atomic_load_8_nonconst(i32 %iptr) {
-entry:
- %ptr = inttoptr i32 %iptr to i8*
- %i = call i8 @llvm.nacl.atomic.load.i8(i8* %ptr, i32 %iptr)
- %r = zext i8 %i to i32
- ret i32 %r
-}
-; CHECK: Unexpected memory ordering for AtomicLoad
-
-define internal void @error_atomic_store_32_nonconst(i32 %iptr, i32 %v) {
-entry:
- %ptr = inttoptr i32 %iptr to i32*
- call void @llvm.nacl.atomic.store.i32(i32 %v, i32* %ptr, i32 %v)
- ret void
-}
-; CHECK: Unexpected memory ordering for AtomicStore
-
-define internal i32 @error_atomic_rmw_add_8_nonconst(i32 %iptr, i32 %v) {
-entry:
- %trunc = trunc i32 %v to i8
- %ptr = inttoptr i32 %iptr to i8*
- %a = call i8 @llvm.nacl.atomic.rmw.i8(i32 1, i8* %ptr, i8 %trunc, i32 %iptr)
- %a_ext = zext i8 %a to i32
- ret i32 %a_ext
-}
-; CHECK: Unexpected memory ordering for AtomicRMW
-
-define internal i32 @error_atomic_cmpxchg_32_success_nonconst_1(i32 %iptr, i32 %expected,
- i32 %desired) {
-entry:
- %ptr = inttoptr i32 %iptr to i32*
- %old = call i32 @llvm.nacl.atomic.cmpxchg.i32(i32* %ptr, i32 %expected,
- i32 %desired, i32 %iptr, i32 6)
- ret i32 %old
-}
-; CHECK: Unexpected memory ordering for AtomicCmpxchg
-
-define internal i32 @error_atomic_cmpxchg_32_success_nonconst_2(i32 %iptr, i32 %expected,
- i32 %desired) {
-entry:
- %ptr = inttoptr i32 %iptr to i32*
- %old = call i32 @llvm.nacl.atomic.cmpxchg.i32(i32* %ptr, i32 %expected,
- i32 %desired, i32 6, i32 %iptr)
- ret i32 %old
-}
-; CHECK: Unexpected memory ordering for AtomicCmpxchg
-
-define internal void @error_atomic_fence_nonconst(i32 %v) {
-entry:
- call void @llvm.nacl.atomic.fence(i32 %v)
- ret void
-}
-; CHECK: Unexpected memory ordering for AtomicFence
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/nacl-atomic-fence-all.ll b/third_party/subzero/tests_lit/llvm2ice_tests/nacl-atomic-fence-all.ll
deleted file mode 100644
index cf37696..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/nacl-atomic-fence-all.ll
+++ /dev/null
@@ -1,202 +0,0 @@
-; Test that loads/stores don't move across a nacl.atomic.fence.all.
-; This should apply to both atomic and non-atomic loads/stores
-; (unlike the non-"all" variety of nacl.atomic.fence, which only
-; applies to atomic load/stores).
-;
-; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 | FileCheck %s
-
-declare void @llvm.nacl.atomic.fence.all()
-declare i32 @llvm.nacl.atomic.load.i32(i32*, i32)
-declare void @llvm.nacl.atomic.store.i32(i32, i32*, i32)
-
-@g32_a = internal global [4 x i8] zeroinitializer, align 4
-@g32_b = internal global [4 x i8] zeroinitializer, align 4
-@g32_c = internal global [4 x i8] zeroinitializer, align 4
-@g32_d = internal global [4 x i8] zeroinitializer, align 4
-
-define internal i32 @test_fused_load_sub_a() {
-entry:
- %p_alloca = alloca i8, i32 4, align 4
- %p_alloca_bc = bitcast i8* %p_alloca to i32*
- store i32 999, i32* %p_alloca_bc, align 1
-
- %p_a = bitcast [4 x i8]* @g32_a to i32*
- %l_a = call i32 @llvm.nacl.atomic.load.i32(i32* %p_a, i32 6)
- %l_a2 = sub i32 1, %l_a
- call void @llvm.nacl.atomic.store.i32(i32 %l_a2, i32* %p_a, i32 6)
-
- %p_b = bitcast [4 x i8]* @g32_b to i32*
- %l_b = load i32, i32* %p_b, align 1
- %l_b2 = sub i32 1, %l_b
- store i32 %l_b2, i32* %p_b, align 1
-
- %p_c = bitcast [4 x i8]* @g32_c to i32*
- %l_c = load i32, i32* %p_c, align 1
- %l_c2 = sub i32 1, %l_c
- call void @llvm.nacl.atomic.fence.all()
- store i32 %l_c2, i32* %p_c, align 1
-
- ret i32 %l_c2
-}
-; CHECK-LABEL: test_fused_load_sub_a
-; alloca store
-; CHECK: mov DWORD PTR {{.*}},0x3e7
-; atomic store (w/ its own mfence)
-; The load + sub are optimized into one everywhere.
-; CHECK: sub {{.*}},DWORD PTR {{.*}}{{(g32_a)|(.bss)}}
-; CHECK: mov {{(DWORD PTR)?}}
-; CHECK: mfence
-; CHECK: sub {{.*}},DWORD PTR {{.*}}{{(g32_b)|(.bss)}}
-; CHECK: mov {{(DWORD PTR)?}}
-; CHECK: sub {{.*}},DWORD PTR {{.*}}{{(g32_c)|(.bss)}}
-; CHECK: mfence
-; CHECK: mov {{(DWORD PTR)?}}
-
-; Test with the fence moved up a bit.
-define internal i32 @test_fused_load_sub_b() {
-entry:
- %p_alloca = alloca i8, i32 4, align 4
- %p_alloca_bc = bitcast i8* %p_alloca to i32*
- store i32 999, i32* %p_alloca_bc, align 1
-
- %p_a = bitcast [4 x i8]* @g32_a to i32*
- %l_a = call i32 @llvm.nacl.atomic.load.i32(i32* %p_a, i32 6)
- %l_a2 = sub i32 1, %l_a
- call void @llvm.nacl.atomic.store.i32(i32 %l_a2, i32* %p_a, i32 6)
-
- %p_b = bitcast [4 x i8]* @g32_b to i32*
- %l_b = load i32, i32* %p_b, align 1
- %l_b2 = sub i32 1, %l_b
- store i32 %l_b2, i32* %p_b, align 1
-
- %p_c = bitcast [4 x i8]* @g32_c to i32*
- call void @llvm.nacl.atomic.fence.all()
- %l_c = load i32, i32* %p_c, align 1
- %l_c2 = sub i32 1, %l_c
- store i32 %l_c2, i32* %p_c, align 1
-
- ret i32 %l_c2
-}
-; CHECK-LABEL: test_fused_load_sub_b
-; alloca store
-; CHECK: mov DWORD PTR {{.*}},0x3e7
-; atomic store (w/ its own mfence)
-; CHECK: sub {{.*}},DWORD PTR {{.*}}{{(g32_a)|(.bss)}}
-; CHECK: mov {{(DWORD PTR)?}}
-; CHECK: mfence
-; CHECK: sub {{.*}},DWORD PTR {{.*}}{{(g32_b)|(.bss)}}
-; CHECK: mov {{(DWORD PTR)?}}
-; CHECK: mfence
-; Load + sub can still be optimized into one instruction
-; because it is not separated by a fence.
-; CHECK: sub {{.*}},DWORD PTR {{.*}}{{(g32_c)|(.bss)}}
-; CHECK: mov {{(DWORD PTR)?}}
-
-; Test with the fence splitting a load/sub.
-define internal i32 @test_fused_load_sub_c() {
-entry:
- %p_alloca = alloca i8, i32 4, align 4
- %p_alloca_bc = bitcast i8* %p_alloca to i32*
- store i32 999, i32* %p_alloca_bc, align 1
-
- %p_a = bitcast [4 x i8]* @g32_a to i32*
- %l_a = call i32 @llvm.nacl.atomic.load.i32(i32* %p_a, i32 6)
- %l_a2 = sub i32 1, %l_a
- call void @llvm.nacl.atomic.store.i32(i32 %l_a2, i32* %p_a, i32 6)
-
- %p_b = bitcast [4 x i8]* @g32_b to i32*
- %l_b = load i32, i32* %p_b, align 1
- call void @llvm.nacl.atomic.fence.all()
- %l_b2 = sub i32 1, %l_b
- store i32 %l_b2, i32* %p_b, align 1
-
- %p_c = bitcast [4 x i8]* @g32_c to i32*
- %l_c = load i32, i32* %p_c, align 1
- %l_c2 = sub i32 1, %l_c
- store i32 %l_c2, i32* %p_c, align 1
-
- ret i32 %l_c2
-}
-; CHECK-LABEL: test_fused_load_sub_c
-; alloca store
-; CHECK: mov DWORD PTR {{.*}},0x3e7
-; atomic store (w/ its own mfence)
-; CHECK: sub {{.*}},DWORD PTR {{.*}}{{(g32_a)|(.bss)}}
-; CHECK: mov {{(DWORD PTR)?}}
-; CHECK: mfence
-; This load + sub are no longer optimized into one,
-; though perhaps it should be legal as long as
-; the load stays on the same side of the fence.
-; CHECK: mov {{.*}},{{(DWORD PTR )?}}{{.*}}{{(g32_b)|(.bss)}}
-; CHECK: mfence
-; CHECK: mov {{.*}},0x1
-; CHECK: sub
-; CHECK: mov {{(DWORD PTR)?}}
-; CHECK: sub {{.*}},DWORD PTR {{.*}}{{(g32_c)|(.bss)}}
-; CHECK: mov {{(DWORD PTR)?}}
-
-
-; Test where a bunch of i8 loads could have been fused into one
-; i32 load, but a fence blocks that.
-define internal i32 @could_have_fused_loads() {
-entry:
- %ptr1 = bitcast [4 x i8]* @g32_d to i8*
- %b1 = load i8, i8* %ptr1, align 1
-
- %int_ptr2 = ptrtoint [4 x i8]* @g32_d to i32
- %int_ptr_bump2 = add i32 %int_ptr2, 1
- %ptr2 = inttoptr i32 %int_ptr_bump2 to i8*
- %b2 = load i8, i8* %ptr2, align 1
-
- %int_ptr_bump3 = add i32 %int_ptr2, 2
- %ptr3 = inttoptr i32 %int_ptr_bump3 to i8*
- %b3 = load i8, i8* %ptr3, align 1
-
- call void @llvm.nacl.atomic.fence.all()
-
- %int_ptr_bump4 = add i32 %int_ptr2, 3
- %ptr4 = inttoptr i32 %int_ptr_bump4 to i8*
- %b4 = load i8, i8* %ptr4, align 1
-
- %b1.ext = zext i8 %b1 to i32
- %b2.ext = zext i8 %b2 to i32
- %b2.shift = shl i32 %b2.ext, 8
- %b12 = or i32 %b1.ext, %b2.shift
- %b3.ext = zext i8 %b3 to i32
- %b3.shift = shl i32 %b3.ext, 16
- %b123 = or i32 %b12, %b3.shift
- %b4.ext = zext i8 %b4 to i32
- %b4.shift = shl i32 %b4.ext, 24
- %b1234 = or i32 %b123, %b4.shift
- ret i32 %b1234
-}
-; CHECK-LABEL: could_have_fused_loads
-; CHECK: mov {{.*}},{{(BYTE PTR)?}}
-; CHECK: mov {{.*}},BYTE PTR
-; CHECK: mov {{.*}},BYTE PTR
-; CHECK: mfence
-; CHECK: mov {{.*}},BYTE PTR
-
-
-; Test where an identical load from two branches could have been hoisted
-; up, and then the code merged, but a fence prevents it.
-define internal i32 @could_have_hoisted_loads(i32 %x) {
-entry:
- %ptr = bitcast [4 x i8]* @g32_d to i32*
- %cmp = icmp eq i32 %x, 1
- br i1 %cmp, label %branch1, label %branch2
-branch1:
- %y = load i32, i32* %ptr, align 1
- ret i32 %y
-branch2:
- call void @llvm.nacl.atomic.fence.all()
- %z = load i32, i32* %ptr, align 1
- ret i32 %z
-}
-; CHECK-LABEL: could_have_hoisted_loads
-; CHECK: jne {{.*}}
-; CHECK: mov {{.*}},{{(DWORD PTR )?}}{{.*}}{{(g32_d)|(.bss)}}
-; CHECK: ret
-; CHECK: mfence
-; CHECK: mov {{.*}},{{(DWORD PTR )?}}{{.*}}{{(g32_d)|(.bss)}}
-; CHECK: ret
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/nacl-atomic-intrinsics.ll b/third_party/subzero/tests_lit/llvm2ice_tests/nacl-atomic-intrinsics.ll
deleted file mode 100644
index abb8e34..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/nacl-atomic-intrinsics.ll
+++ /dev/null
@@ -1,2066 +0,0 @@
-; This tests each of the supported NaCl atomic instructions for every
-; size allowed.
-
-; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 \
-; RUN: -allow-externally-defined-symbols | FileCheck %s
-; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 \
-; RUN: -allow-externally-defined-symbols | FileCheck --check-prefix=O2 %s
-; RUN: %p2i -i %s --filetype=obj --disassemble --args -Om1 \
-; RUN: -allow-externally-defined-symbols | FileCheck %s
-
-; RUN: %if --need=allow_dump --need=target_ARM32 --command %p2i --filetype=asm \
-; RUN: --target arm32 -i %s --args -O2 \
-; RUN: -allow-externally-defined-symbols \
-; RUN: | %if --need=allow_dump --need=target_ARM32 --command FileCheck %s \
-; RUN: --check-prefix=ARM32
-
-; RUN: %if --need=allow_dump --need=target_ARM32 --command %p2i --filetype=asm \
-; RUN: --target arm32 -i %s --args -O2 \
-; RUN: -allow-externally-defined-symbols \
-; RUN: | %if --need=allow_dump --need=target_ARM32 --command FileCheck %s \
-; RUN: --check-prefix=ARM32O2
-
-; RUN: %if --need=allow_dump --need=target_ARM32 --command %p2i --filetype=asm \
-; RUN: --target arm32 -i %s --args -Om1 \
-; RUN: -allow-externally-defined-symbols \
-; RUN: | %if --need=allow_dump --need=target_ARM32 --command FileCheck %s \
-; RUN: --check-prefix=ARM32
-
-; RUN: %if --need=allow_dump --need=target_MIPS32 --command %p2i --filetype=asm\
-; RUN: --target mips32 -i %s --args -O2 \
-; RUN: -allow-externally-defined-symbols \
-; RUN: | %if --need=allow_dump --need=target_MIPS32 --command FileCheck %s \
-; RUN: --check-prefix=MIPS32O2 --check-prefix=MIPS32
-
-; RUN: %if --need=allow_dump --need=target_MIPS32 --command %p2i --filetype=asm\
-; RUN: --target mips32 -i %s --args -Om1 \
-; RUN: -allow-externally-defined-symbols \
-; RUN: | %if --need=allow_dump --need=target_MIPS32 --command FileCheck %s \
-; RUN: --check-prefix=MIPS32OM1 --check-prefix=MIPS32
-
-declare i8 @llvm.nacl.atomic.load.i8(i8*, i32)
-declare i16 @llvm.nacl.atomic.load.i16(i16*, i32)
-declare i32 @llvm.nacl.atomic.load.i32(i32*, i32)
-declare i64 @llvm.nacl.atomic.load.i64(i64*, i32)
-declare void @llvm.nacl.atomic.store.i8(i8, i8*, i32)
-declare void @llvm.nacl.atomic.store.i16(i16, i16*, i32)
-declare void @llvm.nacl.atomic.store.i32(i32, i32*, i32)
-declare void @llvm.nacl.atomic.store.i64(i64, i64*, i32)
-declare i8 @llvm.nacl.atomic.rmw.i8(i32, i8*, i8, i32)
-declare i16 @llvm.nacl.atomic.rmw.i16(i32, i16*, i16, i32)
-declare i32 @llvm.nacl.atomic.rmw.i32(i32, i32*, i32, i32)
-declare i64 @llvm.nacl.atomic.rmw.i64(i32, i64*, i64, i32)
-declare i8 @llvm.nacl.atomic.cmpxchg.i8(i8*, i8, i8, i32, i32)
-declare i16 @llvm.nacl.atomic.cmpxchg.i16(i16*, i16, i16, i32, i32)
-declare i32 @llvm.nacl.atomic.cmpxchg.i32(i32*, i32, i32, i32, i32)
-declare i64 @llvm.nacl.atomic.cmpxchg.i64(i64*, i64, i64, i32, i32)
-declare void @llvm.nacl.atomic.fence(i32)
-declare void @llvm.nacl.atomic.fence.all()
-declare i1 @llvm.nacl.atomic.is.lock.free(i32, i8*)
-
-@SzGlobal8 = internal global [1 x i8] zeroinitializer, align 1
-@SzGlobal16 = internal global [2 x i8] zeroinitializer, align 2
-@SzGlobal32 = internal global [4 x i8] zeroinitializer, align 4
-@SzGlobal64 = internal global [8 x i8] zeroinitializer, align 8
-
-; NOTE: The LLC equivalent for 16-bit atomic operations are expanded
-; as 32-bit operations. For Subzero, assume that real 16-bit operations
-; will be usable (the validator will be fixed):
-; https://code.google.com/p/nativeclient/issues/detail?id=2981
-
-;;; Load
-
-; x86 guarantees load/store to be atomic if naturally aligned.
-; The PNaCl IR requires all atomic accesses to be naturally aligned.
-
-define internal i32 @test_atomic_load_8(i32 %iptr) {
-entry:
- %ptr = inttoptr i32 %iptr to i8*
- ; parameter value "6" is for the sequential consistency memory order.
- %i = call i8 @llvm.nacl.atomic.load.i8(i8* %ptr, i32 6)
- %i2 = sub i8 %i, 0
- %r = zext i8 %i2 to i32
- ret i32 %r
-}
-; CHECK-LABEL: test_atomic_load_8
-; CHECK: mov {{.*}},DWORD
-; CHECK: mov {{.*}},BYTE
-; ARM32-LABEL: test_atomic_load_8
-; ARM32: ldrb r{{[0-9]+}}, [r{{[0-9]+}}
-; ARM32: dmb
-; MIPS32-LABEL: test_atomic_load_8
-; MIPS32: sync
-; MIPS32: ll
-; MIPS32: sc
-; MIPS32: sync
-
-define internal i32 @test_atomic_load_16(i32 %iptr) {
-entry:
- %ptr = inttoptr i32 %iptr to i16*
- %i = call i16 @llvm.nacl.atomic.load.i16(i16* %ptr, i32 6)
- %i2 = sub i16 %i, 0
- %r = zext i16 %i2 to i32
- ret i32 %r
-}
-; CHECK-LABEL: test_atomic_load_16
-; CHECK: mov {{.*}},DWORD
-; CHECK: mov {{.*}},WORD
-; ARM32-LABEL: test_atomic_load_16
-; ARM32: ldrh r{{[0-9]+}}, [r{{[0-9]+}}
-; ARM32: dmb
-; MIPS32-LABEL: test_atomic_load_16
-; MIPS32: sync
-; MIPS32: ll
-; MIPS32: sc
-; MIPS32: sync
-
-define internal i32 @test_atomic_load_32(i32 %iptr) {
-entry:
- %ptr = inttoptr i32 %iptr to i32*
- %r = call i32 @llvm.nacl.atomic.load.i32(i32* %ptr, i32 6)
- ret i32 %r
-}
-; CHECK-LABEL: test_atomic_load_32
-; CHECK: mov {{.*}},DWORD
-; CHECK: mov {{.*}},DWORD
-; ARM32-LABEL: test_atomic_load_32
-; ARM32: ldr r{{[0-9]+}}, [r{{[0-9]+}}
-; ARM32: dmb
-; MIPS32-LABEL: test_atomic_load_32
-; MIPS32: sync
-; MIPS32: ll
-; MIPS32: sc
-; MIPS32: sync
-
-define internal i64 @test_atomic_load_64(i32 %iptr) {
-entry:
- %ptr = inttoptr i32 %iptr to i64*
- %r = call i64 @llvm.nacl.atomic.load.i64(i64* %ptr, i32 6)
- ret i64 %r
-}
-; CHECK-LABEL: test_atomic_load_64
-; CHECK: movq x{{.*}},QWORD
-; CHECK: movq QWORD {{.*}},x{{.*}}
-; ARM32-LABEL: test_atomic_load_64
-; ARM32: ldrexd r{{[0-9]+}}, r{{[0-9]+}}, [r{{[0-9]+}}
-; ARM32: dmb
-; MIPS32-LABEL: test_atomic_load_64
-; MIPS32: jal __sync_val_compare_and_swap_8
-; MIPS32: sync
-
-define internal i32 @test_atomic_load_32_with_arith(i32 %iptr) {
-entry:
- br label %next
-
-next:
- %ptr = inttoptr i32 %iptr to i32*
- %r = call i32 @llvm.nacl.atomic.load.i32(i32* %ptr, i32 6)
- %r2 = sub i32 32, %r
- ret i32 %r2
-}
-; CHECK-LABEL: test_atomic_load_32_with_arith
-; CHECK: mov {{.*}},DWORD
-; The next instruction may be a separate load or folded into an add.
-;
-; In O2 mode, we know that the load and sub are going to be fused.
-; O2-LABEL: test_atomic_load_32_with_arith
-; O2: mov {{.*}},DWORD
-; O2: sub {{.*}},DWORD
-; ARM32-LABEL: test_atomic_load_32_with_arith
-; ARM32: ldr r{{[0-9]+}}, [r{{[0-9]+}}
-; ARM32: dmb
-; MIPS32-LABEL: test_atomic_load_32_with_arith
-; MIPS32: sync
-; MIPS32: ll
-; MIPS32: sc
-; MIPS32: sync
-; MIPS32: subu
-
-define internal i32 @test_atomic_load_32_ignored(i32 %iptr) {
-entry:
- %ptr = inttoptr i32 %iptr to i32*
- %ignored = call i32 @llvm.nacl.atomic.load.i32(i32* %ptr, i32 6)
- ret i32 0
-}
-; CHECK-LABEL: test_atomic_load_32_ignored
-; CHECK: mov {{.*}},DWORD
-; CHECK: mov {{.*}},DWORD
-; O2-LABEL: test_atomic_load_32_ignored
-; O2: mov {{.*}},DWORD
-; O2: mov {{.*}},DWORD
-; ARM32-LABEL: test_atomic_load_32_ignored
-; ARM32: ldr r{{[0-9]+}}, [r{{[0-9]+}}
-; ARM32: dmb
-; MIPS32-LABEL: test_atomic_load_32_ignored
-; MIPS32: sync
-; MIPS32: ll
-; MIPS32: sc
-; MIPS32: sync
-
-define internal i64 @test_atomic_load_64_ignored(i32 %iptr) {
-entry:
- %ptr = inttoptr i32 %iptr to i64*
- %ignored = call i64 @llvm.nacl.atomic.load.i64(i64* %ptr, i32 6)
- ret i64 0
-}
-; CHECK-LABEL: test_atomic_load_64_ignored
-; CHECK: movq x{{.*}},QWORD
-; CHECK: movq QWORD {{.*}},x{{.*}}
-; ARM32-LABEL: test_atomic_load_64_ignored
-; ARM32: ldrexd r{{[0-9]+}}, r{{[0-9]+}}, [r{{[0-9]+}}
-; ARM32: dmb
-; MIPS32-LABEL: test_atomic_load_64_ignored
-; MIPS32: jal __sync_val_compare_and_swap_8
-; MIPS32: sync
-
-;;; Store
-
-define internal void @test_atomic_store_8(i32 %iptr, i32 %v) {
-entry:
- %truncv = trunc i32 %v to i8
- %ptr = inttoptr i32 %iptr to i8*
- call void @llvm.nacl.atomic.store.i8(i8 %truncv, i8* %ptr, i32 6)
- ret void
-}
-; CHECK-LABEL: test_atomic_store_8
-; CHECK: mov BYTE
-; CHECK: mfence
-; ARM32-LABEL: test_atomic_store_8
-; ARM32: dmb
-; ARM32: strb r{{[0-9]+}}, [r{{[0-9]+}}
-; ARM32: dmb
-; MIPS32-LABEL: test_atomic_store_8
-; MIPS32: sync
-; MIPS32: ll
-; MIPS32: sc
-; MIPS32: sync
-
-define internal void @test_atomic_store_16(i32 %iptr, i32 %v) {
-entry:
- %truncv = trunc i32 %v to i16
- %ptr = inttoptr i32 %iptr to i16*
- call void @llvm.nacl.atomic.store.i16(i16 %truncv, i16* %ptr, i32 6)
- ret void
-}
-; CHECK-LABEL: test_atomic_store_16
-; CHECK: mov WORD
-; CHECK: mfence
-; ARM32-LABEL: test_atomic_store_16
-; ARM32: dmb
-; ARM32: strh r{{[0-9]+}}, [r{{[0-9]+}}
-; ARM32: dmb
-; MIPS32-LABEL: test_atomic_store_16
-; MIPS32: sync
-; MIPS32: ll
-; MIPS32: sc
-; MIPS32: sync
-
-define internal void @test_atomic_store_32(i32 %iptr, i32 %v) {
-entry:
- %ptr = inttoptr i32 %iptr to i32*
- call void @llvm.nacl.atomic.store.i32(i32 %v, i32* %ptr, i32 6)
- ret void
-}
-; CHECK-LABEL: test_atomic_store_32
-; CHECK: mov DWORD
-; CHECK: mfence
-; ARM32-LABEL: test_atomic_store_32
-; ARM32: dmb
-; ARM32: str r{{[0-9]+}}, [r{{[0-9]+}}
-; ARM32: dmb
-; MIPS32-LABEL: test_atomic_store_32
-; MIPS32: sync
-; MIPS32: ll
-; MIPS32: sc
-; MIPS32: sync
-
-define internal void @test_atomic_store_64(i32 %iptr, i64 %v) {
-entry:
- %ptr = inttoptr i32 %iptr to i64*
- call void @llvm.nacl.atomic.store.i64(i64 %v, i64* %ptr, i32 6)
- ret void
-}
-; CHECK-LABEL: test_atomic_store_64
-; CHECK: movq x{{.*}},QWORD
-; CHECK: movq QWORD {{.*}},x{{.*}}
-; CHECK: mfence
-; ARM32-LABEL: test_atomic_store_64
-; ARM32: dmb
-; ARM32: ldrexd r{{[0-9]+}}, r{{[0-9]+}}, [[MEM:.*]]
-; ARM32: strexd [[S:r[0-9]+]], r{{[0-9]+}}, r{{[0-9]+}}, [[MEM]]
-; ARM32: cmp [[S]], #0
-; ARM32: bne
-; ARM32: dmb
-; MIPS32-LABEL: test_atomic_store_64
-; MIPS32: sync
-; MIPS32: jal __sync_lock_test_and_set_8
-; MIPS32: sync
-
-define internal void @test_atomic_store_64_const(i32 %iptr) {
-entry:
- %ptr = inttoptr i32 %iptr to i64*
- call void @llvm.nacl.atomic.store.i64(i64 12345678901234, i64* %ptr, i32 6)
- ret void
-}
-; CHECK-LABEL: test_atomic_store_64_const
-; CHECK: mov {{.*}},0x73ce2ff2
-; CHECK: mov {{.*}},0xb3a
-; CHECK: movq x{{.*}},QWORD
-; CHECK: movq QWORD {{.*}},x{{.*}}
-; CHECK: mfence
-; ARM32-LABEL: test_atomic_store_64_const
-; ARM32: movw [[T0:r[0-9]+]], #12274
-; ARM32: movt [[T0]], #29646
-; ARM32: movw r{{[0-9]+}}, #2874
-; ARM32: dmb
-; ARM32: .L[[RETRY:.*]]:
-; ARM32: ldrexd r{{[0-9]+}}, r{{[0-9]+}}, [[MEM:.*]]
-; ARM32: strexd [[S:r[0-9]+]], r{{[0-9]+}}, r{{[0-9]+}}, [[MEM]]
-; ARM32: cmp [[S]], #0
-; ARM32: bne .L[[RETRY]]
-; ARM32: dmb
-; MIPS32-LABEL: test_atomic_store_64_const
-; MIPS32: sync
-; MIPS32: lui {{.*}}, 29646
-; MIPS32: ori {{.*}},{{.*}}, 12274
-; MIPS32: addiu {{.*}}, $zero, 2874
-; MIPS32: jal __sync_lock_test_and_set_8
-; MIPS32: sync
-
-;;; RMW
-
-;; add
-
-define internal i32 @test_atomic_rmw_add_8(i32 %iptr, i32 %v) {
-entry:
- %trunc = trunc i32 %v to i8
- %ptr = inttoptr i32 %iptr to i8*
- ; "1" is an atomic add, and "6" is sequential consistency.
- %a = call i8 @llvm.nacl.atomic.rmw.i8(i32 1, i8* %ptr, i8 %trunc, i32 6)
- %a_ext = zext i8 %a to i32
- ret i32 %a_ext
-}
-; CHECK-LABEL: test_atomic_rmw_add_8
-; CHECK: lock xadd BYTE {{.*}},[[REG:.*]]
-; CHECK: {{mov|movzx}} {{.*}},[[REG]]
-; ARM32-LABEL: test_atomic_rmw_add_8
-; ARM32: dmb
-; ARM32: ldrexb
-; ARM32: add
-; ARM32: strexb
-; ARM32: bne
-; ARM32: dmb
-; MIPS32-LABEL: test_atomic_rmw_add_8
-; MIPS32: sync
-; MIPS32: addiu {{.*}}, $zero, -4
-; MIPS32: and
-; MIPS32: andi {{.*}}, {{.*}}, 3
-; MIPS32: sll {{.*}}, {{.*}}, 3
-; MIPS32: ori {{.*}}, $zero, 255
-; MIPS32: sllv
-; MIPS32: nor
-; MIPS32: sllv
-; MIPS32: ll
-; MIPS32: addu
-; MIPS32: and
-; MIPS32: and
-; MIPS32: or
-; MIPS32: sc
-; MIPS32: beq {{.*}}, $zero, {{.*}}
-; MIPS32: and
-; MIPS32: srlv
-; MIPS32: sll {{.*}}, {{.*}}, 24
-; MIPS32: sra {{.*}}, {{.*}}, 24
-; MIPS32: sync
-
-define internal i32 @test_atomic_rmw_add_16(i32 %iptr, i32 %v) {
-entry:
- %trunc = trunc i32 %v to i16
- %ptr = inttoptr i32 %iptr to i16*
- %a = call i16 @llvm.nacl.atomic.rmw.i16(i32 1, i16* %ptr, i16 %trunc, i32 6)
- %a_ext = zext i16 %a to i32
- ret i32 %a_ext
-}
-; CHECK-LABEL: test_atomic_rmw_add_16
-; CHECK: lock xadd WORD {{.*}},[[REG:.*]]
-; CHECK: {{mov|movzx}} {{.*}},[[REG]]
-; ARM32-LABEL: test_atomic_rmw_add_16
-; ARM32: dmb
-; ARM32: ldrexh
-; ARM32: add
-; ARM32: strexh
-; ARM32: bne
-; ARM32: dmb
-; MIPS32-LABEL: test_atomic_rmw_add_16
-; MIPS32: sync
-; MIPS32: addiu {{.*}}, $zero, -4
-; MIPS32: and
-; MIPS32: andi {{.*}}, {{.*}}, 3
-; MIPS32: sll {{.*}}, {{.*}}, 3
-; MIPS32: ori {{.*}}, {{.*}}, 65535
-; MIPS32: sllv
-; MIPS32: nor
-; MIPS32: sllv
-; MIPS32: ll
-; MIPS32: addu
-; MIPS32: and
-; MIPS32: and
-; MIPS32: or
-; MIPS32: sc
-; MIPS32: beq {{.*}}, $zero, {{.*}}
-; MIPS32: and
-; MIPS32: srlv
-; MIPS32: sll {{.*}}, {{.*}}, 16
-; MIPS32: sra {{.*}}, {{.*}}, 16
-; MIPS32: sync
-
-define internal i32 @test_atomic_rmw_add_32(i32 %iptr, i32 %v) {
-entry:
- %ptr = inttoptr i32 %iptr to i32*
- %a = call i32 @llvm.nacl.atomic.rmw.i32(i32 1, i32* %ptr, i32 %v, i32 6)
- ret i32 %a
-}
-; CHECK-LABEL: test_atomic_rmw_add_32
-; CHECK: lock xadd DWORD {{.*}},[[REG:.*]]
-; CHECK: mov {{.*}},[[REG]]
-; ARM32-LABEL: test_atomic_rmw_add_32
-; ARM32: dmb
-; ARM32: ldrex
-; ARM32: add
-; ARM32: strex
-; ARM32: bne
-; ARM32: dmb
-; MIPS32-LABEL: test_atomic_rmw_add_32
-; MIPS32: sync
-; MIPS32: ll
-; MIPS32: addu
-; MIPS32: sc
-; MIPS32: beq {{.*}}, $zero, {{.*}}
-; MIPS32: sync
-
-define internal i64 @test_atomic_rmw_add_64(i32 %iptr, i64 %v) {
-entry:
- %ptr = inttoptr i32 %iptr to i64*
- %a = call i64 @llvm.nacl.atomic.rmw.i64(i32 1, i64* %ptr, i64 %v, i32 6)
- ret i64 %a
-}
-; CHECK-LABEL: test_atomic_rmw_add_64
-; CHECK: push ebx
-; CHECK: mov eax,DWORD PTR [{{.*}}]
-; CHECK: mov edx,DWORD PTR [{{.*}}+0x4]
-; CHECK: [[LABEL:[^ ]*]]: {{.*}} mov ebx,eax
-; RHS of add cannot be any of the e[abcd]x regs because they are
-; clobbered in the loop, and the RHS needs to be remain live.
-; CHECK: add ebx,{{.*e.[^x]}}
-; CHECK: mov ecx,edx
-; CHECK: adc ecx,{{.*e.[^x]}}
-; Ptr cannot be eax, ebx, ecx, or edx (used up for the expected and desired).
-; It can be esi, edi, or ebp though, for example (so we need to be careful
-; about rejecting eb* and ed*.)
-; CHECK: lock cmpxchg8b QWORD PTR [e{{.[^x]}}
-; CHECK: jne [[LABEL]]
-; ARM32-LABEL: test_atomic_rmw_add_64
-; ARM32: dmb
-; ARM32: ldrexd r{{[0-9]+}}, r{{[0-9]+}}, [r{{[0-9]+}}]
-; ARM32: adds
-; ARM32: adc
-; ARM32: strexd r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}, [r{{[0-9]+}}]
-; ARM32: bne
-; ARM32: dmb
-; MIPS32-LABEL: test_atomic_rmw_add_64
-; MIPS32: sync
-; MIPS32: jal __sync_fetch_and_add_8
-; MIPS32: sync
-
-; Same test as above, but with a global address to test FakeUse issues.
-define internal i64 @test_atomic_rmw_add_64_global(i64 %v) {
-entry:
- %ptr = bitcast [8 x i8]* @SzGlobal64 to i64*
- %a = call i64 @llvm.nacl.atomic.rmw.i64(i32 1, i64* %ptr, i64 %v, i32 6)
- ret i64 %a
-}
-; CHECK-LABEL: test_atomic_rmw_add_64_global
-; ARM32-LABEL: test_atomic_rmw_add_64_global
-; ARM32: dmb
-; ARM32: ldrexd r{{[0-9]+}}, r{{[0-9]+}}, [r{{[0-9]+}}]
-; ARM32: adds
-; ARM32: adc
-; ARM32: strexd r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}, [r{{[0-9]+}}]
-; ARM32: bne
-; ARM32: dmb
-; MIPS32-LABEL: test_atomic_rmw_add_64_global
-; MIPS32: sync
-; MIPS32: jal __sync_fetch_and_add_8
-; MIPS32: sync
-
-; Test with some more register pressure. When we have an alloca, ebp is
-; used to manage the stack frame, so it cannot be used as a register either.
-declare void @use_ptr(i32 %iptr)
-
-define internal i64 @test_atomic_rmw_add_64_alloca(i32 %iptr, i64 %v) {
-entry:
- br label %eblock ; Disable alloca optimization
-eblock:
- %alloca_ptr = alloca i8, i32 16, align 16
- %ptr = inttoptr i32 %iptr to i64*
- %old = call i64 @llvm.nacl.atomic.rmw.i64(i32 1, i64* %ptr, i64 %v, i32 6)
- store i8 0, i8* %alloca_ptr, align 1
- store i8 1, i8* %alloca_ptr, align 1
- store i8 2, i8* %alloca_ptr, align 1
- store i8 3, i8* %alloca_ptr, align 1
- %__5 = ptrtoint i8* %alloca_ptr to i32
- call void @use_ptr(i32 %__5)
- ret i64 %old
-}
-; CHECK-LABEL: test_atomic_rmw_add_64_alloca
-; CHECK: push ebx
-; CHECK-DAG: mov edx
-; CHECK-DAG: mov eax
-; CHECK-DAG: mov ecx
-; CHECK-DAG: mov ebx
-; Ptr cannot be eax, ebx, ecx, or edx (used up for the expected and desired).
-; It also cannot be ebp since we use that for alloca. Also make sure it's
-; not esp, since that's the stack pointer and mucking with it will break
-; the later use_ptr function call.
-; That pretty much leaves esi, or edi as the only viable registers.
-; CHECK: lock cmpxchg8b QWORD PTR [e{{[ds]}}i]
-; CHECK: call {{.*}} R_{{.*}} use_ptr
-; ARM32-LABEL: test_atomic_rmw_add_64_alloca
-; ARM32: dmb
-; ARM32: ldrexd r{{[0-9]+}}, r{{[0-9]+}}, [r{{[0-9]+}}]
-; ARM32: adds
-; ARM32: adc
-; ARM32: strexd r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}, [r{{[0-9]+}}]
-; ARM32: bne
-; ARM32: dmb
-; MIPS32-LABEL: test_atomic_rmw_add_64_alloca
-; MIPS32: sync
-; MIPS32: jal __sync_fetch_and_add_8
-; MIPS32: sync
-
-define internal i32 @test_atomic_rmw_add_32_ignored(i32 %iptr, i32 %v) {
-entry:
- %ptr = inttoptr i32 %iptr to i32*
- %ignored = call i32 @llvm.nacl.atomic.rmw.i32(i32 1, i32* %ptr, i32 %v, i32 6)
- ret i32 %v
-}
-; Technically this could use "lock add" instead of "lock xadd", if liveness
-; tells us that the destination variable is dead.
-; CHECK-LABEL: test_atomic_rmw_add_32_ignored
-; CHECK: lock xadd DWORD {{.*}},[[REG:.*]]
-; ARM32-LABEL: test_atomic_rmw_add_32_ignored
-; ARM32: dmb
-; ARM32: ldrex
-; ARM32: add
-; ARM32: strex
-; ARM32: bne
-; ARM32: dmb
-; MIPS32-LABEL: test_atomic_rmw_add_32_ignored
-; MIPS32: sync
-; MIPS32: ll
-; MIPS32: addu
-; MIPS32: sc
-; MIPS32: beq {{.*}}, $zero, {{.*}}
-; MIPS32: sync
-
-; Atomic RMW 64 needs to be expanded into its own loop.
-; Make sure that works w/ non-trivial function bodies.
-define internal i64 @test_atomic_rmw_add_64_loop(i32 %iptr, i64 %v) {
-entry:
- %x = icmp ult i64 %v, 100
- br i1 %x, label %err, label %loop
-
-loop:
- %v_next = phi i64 [ %v, %entry ], [ %next, %loop ]
- %ptr = inttoptr i32 %iptr to i64*
- %next = call i64 @llvm.nacl.atomic.rmw.i64(i32 1, i64* %ptr, i64 %v_next, i32 6)
- %success = icmp eq i64 %next, 100
- br i1 %success, label %done, label %loop
-
-done:
- ret i64 %next
-
-err:
- ret i64 0
-}
-; CHECK-LABEL: test_atomic_rmw_add_64_loop
-; CHECK: push ebx
-; CHECK: mov eax,DWORD PTR [{{.*}}]
-; CHECK: mov edx,DWORD PTR [{{.*}}+0x4]
-; CHECK: [[LABEL:[^ ]*]]: {{.*}} mov ebx,eax
-; CHECK: add ebx,{{.*e.[^x]}}
-; CHECK: mov ecx,edx
-; CHECK: adc ecx,{{.*e.[^x]}}
-; CHECK: lock cmpxchg8b QWORD PTR [e{{.[^x]}}+0x0]
-; CHECK: jne [[LABEL]]
-; ARM32-LABEL: test_atomic_rmw_add_64_loop
-; ARM32: dmb
-; ARM32: ldrexd r{{[0-9]+}}, r{{[0-9]+}}, [r{{[0-9]+}}]
-; ARM32: adds
-; ARM32: adc
-; ARM32: strexd r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}, [r{{[0-9]+}}]
-; ARM32: bne
-; ARM32: dmb
-; ARM32: b
-; MIPS32-LABEL: test_atomic_rmw_add_64_loop
-; MIPS32: sync
-; MIPS32: jal __sync_fetch_and_add_8
-; MIPS32: sync
-
-;; sub
-
-define internal i32 @test_atomic_rmw_sub_8(i32 %iptr, i32 %v) {
-entry:
- %trunc = trunc i32 %v to i8
- %ptr = inttoptr i32 %iptr to i8*
- %a = call i8 @llvm.nacl.atomic.rmw.i8(i32 2, i8* %ptr, i8 %trunc, i32 6)
- %a_ext = zext i8 %a to i32
- ret i32 %a_ext
-}
-; CHECK-LABEL: test_atomic_rmw_sub_8
-; CHECK: neg [[REG:.*]]
-; CHECK: lock xadd BYTE {{.*}},[[REG]]
-; CHECK: {{mov|movzx}} {{.*}},[[REG]]
-; ARM32-LABEL: test_atomic_rmw_sub_8
-; ARM32: dmb
-; ARM32: ldrexb
-; ARM32: sub
-; ARM32: strexb
-; ARM32: bne
-; ARM32: dmb
-; MIPS32-LABEL: test_atomic_rmw_sub_8
-; MIPS32: sync
-; MIPS32: addiu {{.*}}, $zero, -4
-; MIPS32: and
-; MIPS32: andi {{.*}}, {{.*}}, 3
-; MIPS32: sll {{.*}}, {{.*}}, 3
-; MIPS32: ori {{.*}}, $zero, 255
-; MIPS32: sllv
-; MIPS32: nor
-; MIPS32: sllv
-; MIPS32: ll
-; MIPS32: subu
-; MIPS32: and
-; MIPS32: and
-; MIPS32: or
-; MIPS32: sc
-; MIPS32: beq {{.*}}, $zero, {{.*}}
-; MIPS32: and
-; MIPS32: srlv
-; MIPS32: sll {{.*}}, {{.*}}, 24
-; MIPS32: sra {{.*}}, {{.*}}, 24
-; MIPS32: sync
-
-define internal i32 @test_atomic_rmw_sub_16(i32 %iptr, i32 %v) {
-entry:
- %trunc = trunc i32 %v to i16
- %ptr = inttoptr i32 %iptr to i16*
- %a = call i16 @llvm.nacl.atomic.rmw.i16(i32 2, i16* %ptr, i16 %trunc, i32 6)
- %a_ext = zext i16 %a to i32
- ret i32 %a_ext
-}
-; CHECK-LABEL: test_atomic_rmw_sub_16
-; CHECK: neg [[REG:.*]]
-; CHECK: lock xadd WORD {{.*}},[[REG]]
-; CHECK: {{mov|movzx}} {{.*}},[[REG]]
-; ARM32-LABEL: test_atomic_rmw_sub_16
-; ARM32: dmb
-; ARM32: ldrexh
-; ARM32: sub
-; ARM32: strexh
-; ARM32: bne
-; ARM32: dmb
-; MIPS32-LABEL: test_atomic_rmw_sub_16
-; MIPS32: sync
-; MIPS32: addiu {{.*}}, $zero, -4
-; MIPS32: and
-; MIPS32: andi {{.*}}, {{.*}}, 3
-; MIPS32: sll {{.*}}, {{.*}}, 3
-; MIPS32: ori {{.*}}, {{.*}}, 65535
-; MIPS32: sllv
-; MIPS32: nor
-; MIPS32: sllv
-; MIPS32: ll
-; MIPS32: subu
-; MIPS32: and
-; MIPS32: and
-; MIPS32: or
-; MIPS32: sc
-; MIPS32: beq {{.*}}, $zero, {{.*}}
-; MIPS32: and
-; MIPS32: srlv
-; MIPS32: sll {{.*}}, {{.*}}, 16
-; MIPS32: sra {{.*}}, {{.*}}, 16
-; MIPS32: sync
-
-define internal i32 @test_atomic_rmw_sub_32(i32 %iptr, i32 %v) {
-entry:
- %ptr = inttoptr i32 %iptr to i32*
- %a = call i32 @llvm.nacl.atomic.rmw.i32(i32 2, i32* %ptr, i32 %v, i32 6)
- ret i32 %a
-}
-; CHECK-LABEL: test_atomic_rmw_sub_32
-; CHECK: neg [[REG:.*]]
-; CHECK: lock xadd DWORD {{.*}},[[REG]]
-; CHECK: mov {{.*}},[[REG]]
-; ARM32-LABEL: test_atomic_rmw_sub_32
-; ARM32: dmb
-; ARM32: ldrex
-; ARM32: sub
-; ARM32: strex
-; ARM32: bne
-; ARM32: dmb
-; MIPS32-LABEL: test_atomic_rmw_sub_32
-; MIPS32: sync
-; MIPS32: ll
-; MIPS32: subu
-; MIPS32: sc
-; MIPS32: beq {{.*}}, $zero, {{.*}}
-; MIPS32: sync
-
-define internal i64 @test_atomic_rmw_sub_64(i32 %iptr, i64 %v) {
-entry:
- %ptr = inttoptr i32 %iptr to i64*
- %a = call i64 @llvm.nacl.atomic.rmw.i64(i32 2, i64* %ptr, i64 %v, i32 6)
- ret i64 %a
-}
-; CHECK-LABEL: test_atomic_rmw_sub_64
-; CHECK: push ebx
-; CHECK: mov eax,DWORD PTR [{{.*}}]
-; CHECK: mov edx,DWORD PTR [{{.*}}+0x4]
-; CHECK: [[LABEL:[^ ]*]]: {{.*}} mov ebx,eax
-; CHECK: sub ebx,{{.*e.[^x]}}
-; CHECK: mov ecx,edx
-; CHECK: sbb ecx,{{.*e.[^x]}}
-; CHECK: lock cmpxchg8b QWORD PTR [e{{.[^x]}}
-; CHECK: jne [[LABEL]]
-; ARM32-LABEL: test_atomic_rmw_sub_64
-; ARM32: dmb
-; ARM32: ldrexd r{{[0-9]+}}, r{{[0-9]+}}, [r{{[0-9]+}}]
-; ARM32: subs
-; ARM32: sbc
-; ARM32: strexd r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}, [r{{[0-9]+}}]
-; ARM32: bne
-; ARM32: dmb
-; MIPS32-LABEL: test_atomic_rmw_sub_64
-; MIPS32: sync
-; MIPS32: jal __sync_fetch_and_sub_8
-; MIPS32: sync
-
-define internal i32 @test_atomic_rmw_sub_32_ignored(i32 %iptr, i32 %v) {
-entry:
- %ptr = inttoptr i32 %iptr to i32*
- %ignored = call i32 @llvm.nacl.atomic.rmw.i32(i32 2, i32* %ptr, i32 %v, i32 6)
- ret i32 %v
-}
-; Could use "lock sub" instead of "neg; lock xadd"
-; CHECK-LABEL: test_atomic_rmw_sub_32_ignored
-; CHECK: neg [[REG:.*]]
-; CHECK: lock xadd DWORD {{.*}},[[REG]]
-; ARM32-LABEL: test_atomic_rmw_sub_32_ignored
-; ARM32: dmb
-; ARM32: ldrex
-; ARM32: sub
-; ARM32: strex
-; ARM32: bne
-; ARM32: dmb
-; MIPS32-LABEL: test_atomic_rmw_sub_32_ignored
-; MIPS32: sync
-; MIPS32: ll
-; MIPS32: subu
-; MIPS32: sc
-; MIPS32: beq {{.*}}, $zero, {{.*}}
-; MIPS32: sync
-
-;; or
-
-define internal i32 @test_atomic_rmw_or_8(i32 %iptr, i32 %v) {
-entry:
- %trunc = trunc i32 %v to i8
- %ptr = inttoptr i32 %iptr to i8*
- %a = call i8 @llvm.nacl.atomic.rmw.i8(i32 3, i8* %ptr, i8 %trunc, i32 6)
- %a_ext = zext i8 %a to i32
- ret i32 %a_ext
-}
-; CHECK-LABEL: test_atomic_rmw_or_8
-; CHECK: mov al,BYTE PTR
-; Dest cannot be eax here, because eax is used for the old value. Also want
-; to make sure that cmpxchg's source is the same register.
-; CHECK: or [[REG:[^a].]]
-; CHECK: lock cmpxchg BYTE PTR [e{{[^a].}}],[[REG]]
-; CHECK: jne
-; ARM32-LABEL: test_atomic_rmw_or_8
-; ARM32: dmb
-; ARM32: ldrexb
-; ARM32: orr
-; ARM32: strexb
-; ARM32: bne
-; ARM32: dmb
-; MIPS32-LABEL: test_atomic_rmw_or_8
-; MIPS32: sync
-; MIPS32: addiu {{.*}}, $zero, -4
-; MIPS32: and
-; MIPS32: andi {{.*}}, {{.*}}, 3
-; MIPS32: sll {{.*}}, {{.*}}, 3
-; MIPS32: ori {{.*}}, $zero, 255
-; MIPS32: sllv
-; MIPS32: nor
-; MIPS32: sllv
-; MIPS32: ll
-; MIPS32: or
-; MIPS32: and
-; MIPS32: and
-; MIPS32: or
-; MIPS32: sc
-; MIPS32: beq {{.*}}, $zero, {{.*}}
-; MIPS32: and
-; MIPS32: srlv
-; MIPS32: sll {{.*}}, {{.*}}, 24
-; MIPS32: sra {{.*}}, {{.*}}, 24
-; MIPS32: sync
-
-; Same test as above, but with a global address to test FakeUse issues.
-define internal i32 @test_atomic_rmw_or_8_global(i32 %v) {
-entry:
- %trunc = trunc i32 %v to i8
- %ptr = bitcast [1 x i8]* @SzGlobal8 to i8*
- %a = call i8 @llvm.nacl.atomic.rmw.i8(i32 3, i8* %ptr, i8 %trunc, i32 6)
- %a_ext = zext i8 %a to i32
- ret i32 %a_ext
-}
-; CHECK-LABEL: test_atomic_rmw_or_8_global
-; ARM32-LABEL: test_atomic_rmw_or_8_global
-; ARM32: dmb
-; ARM32: movw [[PTR:r[0-9]+]], #:lower16:SzGlobal8
-; ARM32: movt [[PTR]], #:upper16:SzGlobal8
-; ARM32: ldrexb r{{[0-9]+}}, {{[[]}}[[PTR]]{{[]]}}
-; ARM32: orr
-; ARM32: strexb
-; ARM32: bne
-; ARM32: dmb
-; MIPS32-LABEL: test_atomic_rmw_or_8_global
-; MIPS32: sync
-; MIPS32: addiu {{.*}}, $zero, -4
-; MIPS32: and
-; MIPS32: andi {{.*}}, {{.*}}, 3
-; MIPS32: sll {{.*}}, {{.*}}, 3
-; MIPS32: ori {{.*}}, $zero, 255
-; MIPS32: sllv
-; MIPS32: nor
-; MIPS32: sllv
-; MIPS32: ll
-; MIPS32: or
-; MIPS32: and
-; MIPS32: and
-; MIPS32: or
-; MIPS32: sc
-; MIPS32: beq {{.*}}, $zero, {{.*}}
-; MIPS32: and
-; MIPS32: srlv
-; MIPS32: sll {{.*}}, {{.*}}, 24
-; MIPS32: sra {{.*}}, {{.*}}, 24
-; MIPS32: sync
-
-define internal i32 @test_atomic_rmw_or_16(i32 %iptr, i32 %v) {
-entry:
- %trunc = trunc i32 %v to i16
- %ptr = inttoptr i32 %iptr to i16*
- %a = call i16 @llvm.nacl.atomic.rmw.i16(i32 3, i16* %ptr, i16 %trunc, i32 6)
- %a_ext = zext i16 %a to i32
- ret i32 %a_ext
-}
-; CHECK-LABEL: test_atomic_rmw_or_16
-; CHECK: mov ax,WORD PTR
-; CHECK: or [[REG:[^a].]]
-; CHECK: lock cmpxchg WORD PTR [e{{[^a].}}],[[REG]]
-; CHECK: jne
-; ARM32-LABEL: test_atomic_rmw_or_16
-; ARM32: dmb
-; ARM32: ldrexh
-; ARM32: orr
-; ARM32: strexh
-; ARM32: bne
-; ARM32: dmb
-; MIPS32-LABEL: test_atomic_rmw_or_16
-; MIPS32: sync
-; MIPS32: addiu {{.*}}, $zero, -4
-; MIPS32: and
-; MIPS32: andi {{.*}}, {{.*}}, 3
-; MIPS32: sll {{.*}}, {{.*}}, 3
-; MIPS32: ori {{.*}}, {{.*}}, 65535
-; MIPS32: sllv
-; MIPS32: nor
-; MIPS32: sllv
-; MIPS32: ll
-; MIPS32: or
-; MIPS32: and
-; MIPS32: and
-; MIPS32: or
-; MIPS32: sc
-; MIPS32: beq {{.*}}, $zero, {{.*}}
-; MIPS32: and
-; MIPS32: srlv
-; MIPS32: sll {{.*}}, {{.*}}, 16
-; MIPS32: sra {{.*}}, {{.*}}, 16
-; MIPS32: sync
-
-; Same test as above, but with a global address to test FakeUse issues.
-define internal i32 @test_atomic_rmw_or_16_global(i32 %v) {
-entry:
- %trunc = trunc i32 %v to i16
- %ptr = bitcast [2 x i8]* @SzGlobal16 to i16*
- %a = call i16 @llvm.nacl.atomic.rmw.i16(i32 3, i16* %ptr, i16 %trunc, i32 6)
- %a_ext = zext i16 %a to i32
- ret i32 %a_ext
-}
-; CHECK-LABEL: test_atomic_rmw_or_16_global
-; ARM32-LABEL: test_atomic_rmw_or_16_global
-; ARM32: dmb
-; ARM32: movw [[PTR:r[0-9]+]], #:lower16:SzGlobal16
-; ARM32: movt [[PTR]], #:upper16:SzGlobal16
-; ARM32: ldrexh r{{[0-9]+}}, {{[[]}}[[PTR]]{{[]]}}
-; ARM32: orr
-; ARM32: strexh
-; ARM32: bne
-; ARM32: dmb
-; MIPS32-LABEL: test_atomic_rmw_or_16_global
-; MIPS32: sync
-; MIPS32: addiu {{.*}}, $zero, -4
-; MIPS32: and
-; MIPS32: andi {{.*}}, {{.*}}, 3
-; MIPS32: sll {{.*}}, {{.*}}, 3
-; MIPS32: ori {{.*}}, {{.*}}, 65535
-; MIPS32: sllv
-; MIPS32: nor
-; MIPS32: sllv
-; MIPS32: ll
-; MIPS32: or
-; MIPS32: and
-; MIPS32: and
-; MIPS32: or
-; MIPS32: sc
-; MIPS32: beq {{.*}}, $zero, {{.*}}
-; MIPS32: and
-; MIPS32: srlv
-; MIPS32: sll {{.*}}, {{.*}}, 16
-; MIPS32: sra {{.*}}, {{.*}}, 16
-; MIPS32: sync
-
-define internal i32 @test_atomic_rmw_or_32(i32 %iptr, i32 %v) {
-entry:
- %ptr = inttoptr i32 %iptr to i32*
- %a = call i32 @llvm.nacl.atomic.rmw.i32(i32 3, i32* %ptr, i32 %v, i32 6)
- ret i32 %a
-}
-; CHECK-LABEL: test_atomic_rmw_or_32
-; CHECK: mov eax,DWORD PTR
-; CHECK: or [[REG:e[^a].]]
-; CHECK: lock cmpxchg DWORD PTR [e{{[^a].}}],[[REG]]
-; CHECK: jne
-; ARM32-LABEL: test_atomic_rmw_or_32
-; ARM32: dmb
-; ARM32: ldrex
-; ARM32: orr
-; ARM32: strex
-; ARM32: bne
-; ARM32: dmb
-; MIPS32-LABEL: test_atomic_rmw_or_32
-; MIPS32: sync
-; MIPS32: ll
-; MIPS32: or
-; MIPS32: sc
-; MIPS32: beq {{.*}}, $zero, {{.*}}
-; MIPS32: sync
-
-; Same test as above, but with a global address to test FakeUse issues.
-define internal i32 @test_atomic_rmw_or_32_global(i32 %v) {
-entry:
- %ptr = bitcast [4 x i8]* @SzGlobal32 to i32*
- %a = call i32 @llvm.nacl.atomic.rmw.i32(i32 3, i32* %ptr, i32 %v, i32 6)
- ret i32 %a
-}
-; CHECK-LABEL: test_atomic_rmw_or_32_global
-; ARM32-LABEL: test_atomic_rmw_or_32_global
-; ARM32: dmb
-; ARM32: movw [[PTR:r[0-9]+]], #:lower16:SzGlobal32
-; ARM32: movt [[PTR]], #:upper16:SzGlobal32
-; ARM32: ldrex r{{[0-9]+}}, {{[[]}}[[PTR]]{{[]]}}
-; ARM32: orr
-; ARM32: strex
-; ARM32: bne
-; ARM32: dmb
-; MIPS32-LABEL: test_atomic_rmw_or_32_global
-; MIPS32: sync
-; MIPS32: ll
-; MIPS32: or
-; MIPS32: sc
-; MIPS32: beq {{.*}}, $zero, {{.*}}
-; MIPS32: sync
-
-define internal i64 @test_atomic_rmw_or_64(i32 %iptr, i64 %v) {
-entry:
- %ptr = inttoptr i32 %iptr to i64*
- %a = call i64 @llvm.nacl.atomic.rmw.i64(i32 3, i64* %ptr, i64 %v, i32 6)
- ret i64 %a
-}
-; CHECK-LABEL: test_atomic_rmw_or_64
-; CHECK: push ebx
-; CHECK: mov eax,DWORD PTR [{{.*}}]
-; CHECK: mov edx,DWORD PTR [{{.*}}+0x4]
-; CHECK: [[LABEL:[^ ]*]]: {{.*}} mov ebx,eax
-; CHECK: or ebx,{{.*e.[^x]}}
-; CHECK: mov ecx,edx
-; CHECK: or ecx,{{.*e.[^x]}}
-; CHECK: lock cmpxchg8b QWORD PTR [e{{.[^x]}}
-; CHECK: jne [[LABEL]]
-; ARM32-LABEL: test_atomic_rmw_or_64
-; ARM32: dmb
-; ARM32: ldrexd r{{[0-9]+}}, r{{[0-9]+}}, [r{{[0-9]+}}]
-; ARM32: orr
-; ARM32: orr
-; ARM32: strexd r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}, [r{{[0-9]+}}]
-; ARM32: bne
-; ARM32: dmb
-; MIPS32-LABEL: test_atomic_rmw_or_64
-; MIPS32: sync
-; MIPS32: jal __sync_fetch_and_or_8
-; MIPS32: sync
-
-define internal i32 @test_atomic_rmw_or_32_ignored(i32 %iptr, i32 %v) {
-entry:
- %ptr = inttoptr i32 %iptr to i32*
- %ignored = call i32 @llvm.nacl.atomic.rmw.i32(i32 3, i32* %ptr, i32 %v, i32 6)
- ret i32 %v
-}
-; CHECK-LABEL: test_atomic_rmw_or_32_ignored
-; Could just "lock or", if we inspect the liveness information first.
-; Would also need a way to introduce "lock"'edness to binary
-; operators without introducing overhead on the more common binary ops.
-; CHECK: mov eax,DWORD PTR
-; CHECK: or [[REG:e[^a].]]
-; CHECK: lock cmpxchg DWORD PTR [e{{[^a].}}],[[REG]]
-; CHECK: jne
-; ARM32-LABEL: test_atomic_rmw_or_32_ignored
-; ARM32: dmb
-; ARM32: ldrex
-; ARM32: orr
-; ARM32: strex
-; ARM32: bne
-; ARM32: dmb
-; MIPS32-LABEL: test_atomic_rmw_or_32_ignored
-; MIPS32: sync
-; MIPS32: ll
-; MIPS32: or
-; MIPS32: sc
-; MIPS32: beq {{.*}}, $zero, {{.*}}
-; MIPS32: sync
-
-;; and
-
-define internal i32 @test_atomic_rmw_and_8(i32 %iptr, i32 %v) {
-entry:
- %trunc = trunc i32 %v to i8
- %ptr = inttoptr i32 %iptr to i8*
- %a = call i8 @llvm.nacl.atomic.rmw.i8(i32 4, i8* %ptr, i8 %trunc, i32 6)
- %a_ext = zext i8 %a to i32
- ret i32 %a_ext
-}
-; CHECK-LABEL: test_atomic_rmw_and_8
-; CHECK: mov al,BYTE PTR
-; CHECK: and [[REG:[^a].]]
-; CHECK: lock cmpxchg BYTE PTR [e{{[^a].}}],[[REG]]
-; CHECK: jne
-; ARM32-LABEL: test_atomic_rmw_and_8
-; ARM32: dmb
-; ARM32: ldrexb
-; ARM32: and
-; ARM32: strexb
-; ARM32: bne
-; ARM32: dmb
-; MIPS32-LABEL: test_atomic_rmw_and_8
-; MIPS32: sync
-; MIPS32: addiu {{.*}}, $zero, -4
-; MIPS32: and
-; MIPS32: andi {{.*}}, {{.*}}, 3
-; MIPS32: sll {{.*}}, {{.*}}, 3
-; MIPS32: ori {{.*}}, $zero, 255
-; MIPS32: sllv
-; MIPS32: nor
-; MIPS32: sllv
-; MIPS32: ll
-; MIPS32: and
-; MIPS32: and
-; MIPS32: and
-; MIPS32: or
-; MIPS32: sc
-; MIPS32: beq {{.*}}, $zero, {{.*}}
-; MIPS32: and
-; MIPS32: srlv
-; MIPS32: sll {{.*}}, {{.*}}, 24
-; MIPS32: sra {{.*}}, {{.*}}, 24
-; MIPS32: sync
-
-define internal i32 @test_atomic_rmw_and_16(i32 %iptr, i32 %v) {
-entry:
- %trunc = trunc i32 %v to i16
- %ptr = inttoptr i32 %iptr to i16*
- %a = call i16 @llvm.nacl.atomic.rmw.i16(i32 4, i16* %ptr, i16 %trunc, i32 6)
- %a_ext = zext i16 %a to i32
- ret i32 %a_ext
-}
-; CHECK-LABEL: test_atomic_rmw_and_16
-; CHECK: mov ax,WORD PTR
-; CHECK: and
-; CHECK: lock cmpxchg WORD PTR [e{{[^a].}}]
-; CHECK: jne
-; ARM32-LABEL: test_atomic_rmw_and_16
-; ARM32: dmb
-; ARM32: ldrexh
-; ARM32: and
-; ARM32: strexh
-; ARM32: bne
-; ARM32: dmb
-; MIPS32-LABEL: test_atomic_rmw_and_16
-; MIPS32: sync
-; MIPS32: addiu {{.*}}, $zero, -4
-; MIPS32: and
-; MIPS32: andi {{.*}}, {{.*}}, 3
-; MIPS32: sll {{.*}}, {{.*}}, 3
-; MIPS32: ori {{.*}}, {{.*}}, 65535
-; MIPS32: sllv
-; MIPS32: nor
-; MIPS32: sllv
-; MIPS32: ll
-; MIPS32: and
-; MIPS32: and
-; MIPS32: and
-; MIPS32: or
-; MIPS32: sc
-; MIPS32: beq {{.*}}, $zero, {{.*}}
-; MIPS32: and
-; MIPS32: srlv
-; MIPS32: sll {{.*}}, {{.*}}, 16
-; MIPS32: sra {{.*}}, {{.*}}, 16
-; MIPS32: sync
-
-define internal i32 @test_atomic_rmw_and_32(i32 %iptr, i32 %v) {
-entry:
- %ptr = inttoptr i32 %iptr to i32*
- %a = call i32 @llvm.nacl.atomic.rmw.i32(i32 4, i32* %ptr, i32 %v, i32 6)
- ret i32 %a
-}
-; CHECK-LABEL: test_atomic_rmw_and_32
-; CHECK: mov eax,DWORD PTR
-; CHECK: and
-; CHECK: lock cmpxchg DWORD PTR [e{{[^a].}}]
-; CHECK: jne
-; ARM32-LABEL: test_atomic_rmw_and_32
-; ARM32: dmb
-; ARM32: ldrex
-; ARM32: and
-; ARM32: strex
-; ARM32: bne
-; ARM32: dmb
-; MIPS32-LABEL: test_atomic_rmw_and_32
-; MIPS32: sync
-; MIPS32: ll
-; MIPS32: and
-; MIPS32: sc
-; MIPS32: beq {{.*}}, $zero, {{.*}}
-; MIPS32: sync
-
-define internal i64 @test_atomic_rmw_and_64(i32 %iptr, i64 %v) {
-entry:
- %ptr = inttoptr i32 %iptr to i64*
- %a = call i64 @llvm.nacl.atomic.rmw.i64(i32 4, i64* %ptr, i64 %v, i32 6)
- ret i64 %a
-}
-; CHECK-LABEL: test_atomic_rmw_and_64
-; CHECK: push ebx
-; CHECK: mov eax,DWORD PTR [{{.*}}]
-; CHECK: mov edx,DWORD PTR [{{.*}}+0x4]
-; CHECK: [[LABEL:[^ ]*]]: {{.*}} mov ebx,eax
-; CHECK: and ebx,{{.*e.[^x]}}
-; CHECK: mov ecx,edx
-; CHECK: and ecx,{{.*e.[^x]}}
-; CHECK: lock cmpxchg8b QWORD PTR [e{{.[^x]}}
-; CHECK: jne [[LABEL]]
-; ARM32-LABEL: test_atomic_rmw_and_64
-; ARM32: dmb
-; ARM32: ldrexd r{{[0-9]+}}, r{{[0-9]+}}, [r{{[0-9]+}}]
-; ARM32: and
-; ARM32: and
-; ARM32: strexd r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}, [r{{[0-9]+}}]
-; ARM32: bne
-; ARM32: dmb
-; MIPS32-LABEL: test_atomic_rmw_and_64
-; MIPS32: sync
-; MIPS32: jal __sync_fetch_and_and_8
-; MIPS32: sync
-
-define internal i32 @test_atomic_rmw_and_32_ignored(i32 %iptr, i32 %v) {
-entry:
- %ptr = inttoptr i32 %iptr to i32*
- %ignored = call i32 @llvm.nacl.atomic.rmw.i32(i32 4, i32* %ptr, i32 %v, i32 6)
- ret i32 %v
-}
-; CHECK-LABEL: test_atomic_rmw_and_32_ignored
-; Could just "lock and"
-; CHECK: mov eax,DWORD PTR
-; CHECK: and
-; CHECK: lock cmpxchg DWORD PTR [e{{[^a].}}]
-; CHECK: jne
-; ARM32-LABEL: test_atomic_rmw_and_32_ignored
-; ARM32: dmb
-; ARM32: ldrex
-; ARM32: and
-; ARM32: strex
-; ARM32: bne
-; ARM32: dmb
-; MIPS32-LABEL: test_atomic_rmw_and_32_ignored
-; MIPS32: sync
-; MIPS32: ll
-; MIPS32: and
-; MIPS32: sc
-; MIPS32: beq {{.*}}, $zero, {{.*}}
-; MIPS32: sync
-
-;; xor
-
-define internal i32 @test_atomic_rmw_xor_8(i32 %iptr, i32 %v) {
-entry:
- %trunc = trunc i32 %v to i8
- %ptr = inttoptr i32 %iptr to i8*
- %a = call i8 @llvm.nacl.atomic.rmw.i8(i32 5, i8* %ptr, i8 %trunc, i32 6)
- %a_ext = zext i8 %a to i32
- ret i32 %a_ext
-}
-; CHECK-LABEL: test_atomic_rmw_xor_8
-; CHECK: mov al,BYTE PTR
-; CHECK: xor [[REG:[^a].]]
-; CHECK: lock cmpxchg BYTE PTR [e{{[^a].}}],[[REG]]
-; CHECK: jne
-; ARM32-LABEL: test_atomic_rmw_xor_8
-; ARM32: dmb
-; ARM32: ldrexb
-; ARM32: eor
-; ARM32: strexb
-; ARM32: bne
-; ARM32: dmb
-; MIPS32-LABEL: test_atomic_rmw_xor_8
-; MIPS32: sync
-; MIPS32: addiu {{.*}}, $zero, -4
-; MIPS32: and
-; MIPS32: andi {{.*}}, {{.*}}, 3
-; MIPS32: sll {{.*}}, {{.*}}, 3
-; MIPS32: ori {{.*}}, $zero, 255
-; MIPS32: sllv
-; MIPS32: nor
-; MIPS32: sllv
-; MIPS32: ll
-; MIPS32: xor
-; MIPS32: and
-; MIPS32: and
-; MIPS32: or
-; MIPS32: sc
-; MIPS32: beq {{.*}}, $zero, {{.*}}
-; MIPS32: and
-; MIPS32: srlv
-; MIPS32: sll {{.*}}, {{.*}}, 24
-; MIPS32: sra {{.*}}, {{.*}}, 24
-; MIPS32: sync
-
-define internal i32 @test_atomic_rmw_xor_16(i32 %iptr, i32 %v) {
-entry:
- %trunc = trunc i32 %v to i16
- %ptr = inttoptr i32 %iptr to i16*
- %a = call i16 @llvm.nacl.atomic.rmw.i16(i32 5, i16* %ptr, i16 %trunc, i32 6)
- %a_ext = zext i16 %a to i32
- ret i32 %a_ext
-}
-; CHECK-LABEL: test_atomic_rmw_xor_16
-; CHECK: mov ax,WORD PTR
-; CHECK: xor
-; CHECK: lock cmpxchg WORD PTR [e{{[^a].}}]
-; CHECK: jne
-; ARM32-LABEL: test_atomic_rmw_xor_16
-; ARM32: dmb
-; ARM32: ldrexh
-; ARM32: eor
-; ARM32: strexh
-; ARM32: bne
-; ARM32: dmb
-; MIPS32-LABEL: test_atomic_rmw_xor_16
-; MIPS32: sync
-; MIPS32: addiu {{.*}}, $zero, -4
-; MIPS32: and
-; MIPS32: andi {{.*}}, {{.*}}, 3
-; MIPS32: sll {{.*}}, {{.*}}, 3
-; MIPS32: ori {{.*}}, {{.*}}, 65535
-; MIPS32: sllv
-; MIPS32: nor
-; MIPS32: sllv
-; MIPS32: ll
-; MIPS32: xor
-; MIPS32: and
-; MIPS32: and
-; MIPS32: or
-; MIPS32: sc
-; MIPS32: beq {{.*}}, $zero, {{.*}}
-; MIPS32: and
-; MIPS32: srlv
-; MIPS32: sll {{.*}}, {{.*}}, 16
-; MIPS32: sra {{.*}}, {{.*}}, 16
-; MIPS32: sync
-
-define internal i32 @test_atomic_rmw_xor_32(i32 %iptr, i32 %v) {
-entry:
- %ptr = inttoptr i32 %iptr to i32*
- %a = call i32 @llvm.nacl.atomic.rmw.i32(i32 5, i32* %ptr, i32 %v, i32 6)
- ret i32 %a
-}
-; CHECK-LABEL: test_atomic_rmw_xor_32
-; CHECK: mov eax,DWORD PTR
-; CHECK: xor
-; CHECK: lock cmpxchg DWORD PTR [e{{[^a].}}]
-; CHECK: jne
-; ARM32-LABEL: test_atomic_rmw_xor_32
-; ARM32: dmb
-; ARM32: ldrex
-; ARM32: eor
-; ARM32: strex
-; ARM32: bne
-; ARM32: dmb
-; MIPS32-LABEL: test_atomic_rmw_xor_32
-; MIPS32: sync
-; MIPS32: ll
-; MIPS32: xor
-; MIPS32: sc
-; MIPS32: beq {{.*}}, $zero, {{.*}}
-; MIPS32: sync
-
-define internal i64 @test_atomic_rmw_xor_64(i32 %iptr, i64 %v) {
-entry:
- %ptr = inttoptr i32 %iptr to i64*
- %a = call i64 @llvm.nacl.atomic.rmw.i64(i32 5, i64* %ptr, i64 %v, i32 6)
- ret i64 %a
-}
-; CHECK-LABEL: test_atomic_rmw_xor_64
-; CHECK: push ebx
-; CHECK: mov eax,DWORD PTR [{{.*}}]
-; CHECK: mov edx,DWORD PTR [{{.*}}+0x4]
-; CHECK: mov ebx,eax
-; CHECK: or ebx,{{.*e.[^x]}}
-; CHECK: mov ecx,edx
-; CHECK: or ecx,{{.*e.[^x]}}
-; CHECK: lock cmpxchg8b QWORD PTR [e{{.[^x]}}
-; CHECK: jne
-; ARM32-LABEL: test_atomic_rmw_xor_64
-; ARM32: dmb
-; ARM32: ldrexd r{{[0-9]+}}, r{{[0-9]+}}, [r{{[0-9]+}}]
-; ARM32: eor
-; ARM32: eor
-; ARM32: strexd r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}, [r{{[0-9]+}}]
-; ARM32: bne
-; ARM32: dmb
-; MIPS32-LABEL: test_atomic_rmw_xor_64
-; MIPS32: sync
-; MIPS32: jal __sync_fetch_and_xor_8
-; MIPS32: sync
-
-define internal i32 @test_atomic_rmw_xor_32_ignored(i32 %iptr, i32 %v) {
-entry:
- %ptr = inttoptr i32 %iptr to i32*
- %ignored = call i32 @llvm.nacl.atomic.rmw.i32(i32 5, i32* %ptr, i32 %v, i32 6)
- ret i32 %v
-}
-; CHECK-LABEL: test_atomic_rmw_xor_32_ignored
-; CHECK: mov eax,DWORD PTR
-; CHECK: xor
-; CHECK: lock cmpxchg DWORD PTR [e{{[^a].}}]
-; CHECK: jne
-; ARM32-LABEL: test_atomic_rmw_xor_32_ignored
-; ARM32: dmb
-; ARM32: ldrex
-; ARM32: eor
-; ARM32: strex
-; ARM32: bne
-; ARM32: dmb
-; MIPS32-LABEL: test_atomic_rmw_xor_32_ignored
-; MIPS32: sync
-; MIPS32: ll
-; MIPS32: xor
-; MIPS32: sc
-; MIPS32: beq {{.*}}, $zero, {{.*}}
-; MIPS32: sync
-
-;; exchange
-
-define internal i32 @test_atomic_rmw_xchg_8(i32 %iptr, i32 %v) {
-entry:
- %trunc = trunc i32 %v to i8
- %ptr = inttoptr i32 %iptr to i8*
- %a = call i8 @llvm.nacl.atomic.rmw.i8(i32 6, i8* %ptr, i8 %trunc, i32 6)
- %a_ext = zext i8 %a to i32
- ret i32 %a_ext
-}
-; CHECK-LABEL: test_atomic_rmw_xchg_8
-; CHECK: xchg BYTE PTR {{.*}},[[REG:.*]]
-; ARM32-LABEL: test_atomic_rmw_xchg_8
-; ARM32: dmb
-; ARM32: ldrexb
-; ARM32: strexb
-; ARM32: cmp
-; ARM32: bne
-; ARM32: dmb
-; MIPS32-LABEL: test_atomic_rmw_xchg_8
-; MIPS32: sync
-; MIPS32: addiu {{.*}}, $zero, -4
-; MIPS32: and
-; MIPS32: andi {{.*}}, {{.*}}, 3
-; MIPS32: sll {{.*}}, {{.*}}, 3
-; MIPS32: ori {{.*}}, $zero, 255
-; MIPS32: sllv
-; MIPS32: nor
-; MIPS32: sllv
-; MIPS32: ll
-; MIPS32: and
-; MIPS32: or
-; MIPS32: sc
-; MIPS32: beq {{.*}}, $zero, {{.*}}
-; MIPS32: and
-; MIPS32: srlv
-; MIPS32: sll {{.*}}, {{.*}}, 24
-; MIPS32: sra {{.*}}, {{.*}}, 24
-; MIPS32: sync
-
-define internal i32 @test_atomic_rmw_xchg_16(i32 %iptr, i32 %v) {
-entry:
- %trunc = trunc i32 %v to i16
- %ptr = inttoptr i32 %iptr to i16*
- %a = call i16 @llvm.nacl.atomic.rmw.i16(i32 6, i16* %ptr, i16 %trunc, i32 6)
- %a_ext = zext i16 %a to i32
- ret i32 %a_ext
-}
-; CHECK-LABEL: test_atomic_rmw_xchg_16
-; CHECK: xchg WORD PTR {{.*}},[[REG:.*]]
-; ARM32-LABEL: test_atomic_rmw_xchg_16
-; ARM32: dmb
-; ARM32: ldrexh
-; ARM32: strexh
-; ARM32: cmp
-; ARM32: bne
-; ARM32: dmb
-; MIPS32-LABEL: test_atomic_rmw_xchg_16
-; MIPS32: sync
-; MIPS32: addiu {{.*}}, $zero, -4
-; MIPS32: and
-; MIPS32: andi {{.*}}, {{.*}}, 3
-; MIPS32: sll {{.*}}, {{.*}}, 3
-; MIPS32: ori {{.*}}, {{.*}}, 65535
-; MIPS32: sllv
-; MIPS32: nor
-; MIPS32: sllv
-; MIPS32: ll
-; MIPS32: and
-; MIPS32: or
-; MIPS32: sc
-; MIPS32: beq {{.*}}, $zero, {{.*}}
-; MIPS32: and
-; MIPS32: srlv
-; MIPS32: sll {{.*}}, {{.*}}, 16
-; MIPS32: sra {{.*}}, {{.*}}, 16
-; MIPS32: sync
-
-define internal i32 @test_atomic_rmw_xchg_32(i32 %iptr, i32 %v) {
-entry:
- %ptr = inttoptr i32 %iptr to i32*
- %a = call i32 @llvm.nacl.atomic.rmw.i32(i32 6, i32* %ptr, i32 %v, i32 6)
- ret i32 %a
-}
-; CHECK-LABEL: test_atomic_rmw_xchg_32
-; CHECK: xchg DWORD PTR {{.*}},[[REG:.*]]
-; ARM32-LABEL: test_atomic_rmw_xchg_32
-; ARM32: dmb
-; ARM32: ldrex
-; ARM32: strex
-; ARM32: cmp
-; ARM32: bne
-; ARM32: dmb
-; MIPS32-LABEL: test_atomic_rmw_xchg_32
-; MIPS32: sync
-; MIPS32: ll
-; MIPS32: move
-; MIPS32: sc
-; MIPS32: beq {{.*}}, $zero, {{.*}}
-; MIPS32: sync
-
-define internal i64 @test_atomic_rmw_xchg_64(i32 %iptr, i64 %v) {
-entry:
- %ptr = inttoptr i32 %iptr to i64*
- %a = call i64 @llvm.nacl.atomic.rmw.i64(i32 6, i64* %ptr, i64 %v, i32 6)
- ret i64 %a
-}
-; CHECK-LABEL: test_atomic_rmw_xchg_64
-; CHECK: push ebx
-; CHECK-DAG: mov edx
-; CHECK-DAG: mov eax
-; CHECK-DAG: mov ecx
-; CHECK-DAG: mov ebx
-; CHECK: lock cmpxchg8b QWORD PTR [{{e.[^x]}}
-; CHECK: jne
-; ARM32-LABEL: test_atomic_rmw_xchg_64
-; ARM32: dmb
-; ARM32: ldrexd r{{[0-9]+}}, r{{[0-9]+}}, {{[[]}}[[PTR:r[0-9]+]]{{[]]}}
-; ARM32: strexd r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}, {{[[]}}[[PTR]]{{[]]}}
-; ARM32: cmp
-; ARM32: bne
-; ARM32: dmb
-; MIPS32-LABEL: test_atomic_rmw_xchg_64
-; MIPS32: sync
-; MIPS32: jal __sync_lock_test_and_set_8
-; MIPS32: sync
-
-define internal i32 @test_atomic_rmw_xchg_32_ignored(i32 %iptr, i32 %v) {
-entry:
- %ptr = inttoptr i32 %iptr to i32*
- %ignored = call i32 @llvm.nacl.atomic.rmw.i32(i32 6, i32* %ptr, i32 %v, i32 6)
- ret i32 %v
-}
-; In this case, ignoring the return value doesn't help. The xchg is
-; used to do an atomic store.
-; CHECK-LABEL: test_atomic_rmw_xchg_32_ignored
-; CHECK: xchg DWORD PTR {{.*}},[[REG:.*]]
-; ARM32-LABEL: test_atomic_rmw_xchg_32_ignored
-; ARM32: dmb
-; ARM32: ldrex
-; ARM32: strex
-; ARM32: cmp
-; ARM32: bne
-; ARM32: dmb
-; MIPS32-LABEL: test_atomic_rmw_xchg_32_ignored
-; MIPS32: sync
-; MIPS32: ll
-; MIPS32: move
-; MIPS32: sc
-; MIPS32: beq {{.*}}, $zero, {{.*}}
-; MIPS32: sync
-
-;;;; Cmpxchg
-
-define internal i32 @test_atomic_cmpxchg_8(i32 %iptr, i32 %expected,
- i32 %desired) {
-entry:
- %trunc_exp = trunc i32 %expected to i8
- %trunc_des = trunc i32 %desired to i8
- %ptr = inttoptr i32 %iptr to i8*
- %old = call i8 @llvm.nacl.atomic.cmpxchg.i8(i8* %ptr, i8 %trunc_exp,
- i8 %trunc_des, i32 6, i32 6)
- %old_ext = zext i8 %old to i32
- ret i32 %old_ext
-}
-; CHECK-LABEL: test_atomic_cmpxchg_8
-; CHECK: mov eax,{{.*}}
-; Need to check that eax isn't used as the address register or the desired.
-; since it is already used as the *expected* register.
-; CHECK: lock cmpxchg BYTE PTR [e{{[^a].}}],{{[^a]}}l
-; ARM32-LABEL: test_atomic_cmpxchg_8
-; ARM32: dmb
-; ARM32: ldrexb [[V:r[0-9]+]], {{[[]}}[[A:r[0-9]+]]{{[]]}}
-; ARM32: lsl [[VV:r[0-9]+]], [[V]], #24
-; ARM32: cmp [[VV]], {{r[0-9]+}}, lsl #24
-; ARM32: movne [[SUCCESS:r[0-9]+]],
-; ARM32: strexbeq [[SUCCESS]], {{r[0-9]+}}, {{[[]}}[[A]]{{[]]}}
-; ARM32: cmp [[SUCCESS]], #0
-; ARM32: bne
-; ARM32: dmb
-; MIPS32-LABEL: test_atomic_cmpxchg_8
-; MIPS32: addiu {{.*}}, $zero, -4
-; MIPS32: and
-; MIPS32: andi {{.*}}, {{.*}}, 3
-; MIPS32: sll {{.*}}, {{.*}}, 3
-; MIPS32: ori {{.*}}, $zero, 255
-; MIPS32: sllv
-; MIPS32: nor
-; MIPS32: andi {{.*}}, {{.*}}, 255
-; MIPS32: sllv
-; MIPS32: andi {{.*}}, {{.*}}, 255
-; MIPS32: sllv
-; MIPS32: sync
-; MIPS32: ll
-; MIPS32: and
-; MIPS32: bne
-; MIPS32: and
-; MIPS32: or
-; MIPS32: sc
-; MIPS32: beq $zero, {{.*}}, {{.*}}
-; MIPS32: srlv
-; MIPS32: sll {{.*}}, {{.*}}, 24
-; MIPS32: sra {{.*}}, {{.*}}, 24
-; MIPS32: sync
-
-define internal i32 @test_atomic_cmpxchg_16(i32 %iptr, i32 %expected,
- i32 %desired) {
-entry:
- %trunc_exp = trunc i32 %expected to i16
- %trunc_des = trunc i32 %desired to i16
- %ptr = inttoptr i32 %iptr to i16*
- %old = call i16 @llvm.nacl.atomic.cmpxchg.i16(i16* %ptr, i16 %trunc_exp,
- i16 %trunc_des, i32 6, i32 6)
- %old_ext = zext i16 %old to i32
- ret i32 %old_ext
-}
-; CHECK-LABEL: test_atomic_cmpxchg_16
-; CHECK: mov {{ax|eax}},{{.*}}
-; CHECK: lock cmpxchg WORD PTR [e{{[^a].}}],{{[^a]}}x
-; ARM32-LABEL: test_atomic_cmpxchg_16
-; ARM32: dmb
-; ARM32: ldrexh [[V:r[0-9]+]], {{[[]}}[[A:r[0-9]+]]{{[]]}}
-; ARM32: lsl [[VV:r[0-9]+]], [[V]], #16
-; ARM32: cmp [[VV]], {{r[0-9]+}}, lsl #16
-; ARM32: movne [[SUCCESS:r[0-9]+]],
-; ARM32: strexheq [[SUCCESS]], {{r[0-9]+}}, {{[[]}}[[A]]{{[]]}}
-; ARM32: cmp [[SUCCESS]], #0
-; ARM32: bne
-; ARM32: dmb
-; MIPS32-LABEL: test_atomic_cmpxchg_16
-; MIPS32: addiu {{.*}}, $zero, -4
-; MIPS32: and
-; MIPS32: andi {{.*}}, {{.*}}, 3
-; MIPS32: sll {{.*}}, {{.*}}, 3
-; MIPS32: ori {{.*}}, {{.*}}, 65535
-; MIPS32: sllv
-; MIPS32: nor
-; MIPS32: andi {{.*}}, {{.*}}, 65535
-; MIPS32: sllv
-; MIPS32: andi {{.*}}, {{.*}}, 65535
-; MIPS32: sllv
-; MIPS32: sync
-; MIPS32: ll
-; MIPS32: and
-; MIPS32: bne
-; MIPS32: and
-; MIPS32: or
-; MIPS32: sc
-; MIPS32: beq $zero, {{.*}}, {{.*}}
-; MIPS32: srlv
-; MIPS32: sll {{.*}}, {{.*}}, 16
-; MIPS32: sra {{.*}}, {{.*}}, 16
-; MIPS32: sync
-
-define internal i32 @test_atomic_cmpxchg_32(i32 %iptr, i32 %expected,
- i32 %desired) {
-entry:
- %ptr = inttoptr i32 %iptr to i32*
- %old = call i32 @llvm.nacl.atomic.cmpxchg.i32(i32* %ptr, i32 %expected,
- i32 %desired, i32 6, i32 6)
- ret i32 %old
-}
-; CHECK-LABEL: test_atomic_cmpxchg_32
-; CHECK: mov eax,{{.*}}
-; CHECK: lock cmpxchg DWORD PTR [e{{[^a].}}],e{{[^a]}}
-; ARM32-LABEL: test_atomic_cmpxchg_32
-; ARM32: dmb
-; ARM32: ldrex [[V:r[0-9]+]], {{[[]}}[[A:r[0-9]+]]{{[]]}}
-; ARM32: cmp [[V]], {{r[0-9]+}}
-; ARM32: movne [[SUCCESS:r[0-9]+]],
-; ARM32: strexeq [[SUCCESS]], {{r[0-9]+}}, {{[[]}}[[A]]{{[]]}}
-; ARM32: cmp [[SUCCESS]], #0
-; ARM32: bne
-; ARM32: dmb
-; MIPS32-LABEL: test_atomic_cmpxchg_32
-; MIPS32: sync
-; MIPS32: ll
-; MIPS32: bne
-; MIPS32: sc
-; MIPS32: beq {{.*}}, $zero, {{.*}}
-; MIPS32: sync
-
-define internal i64 @test_atomic_cmpxchg_64(i32 %iptr, i64 %expected,
- i64 %desired) {
-entry:
- %ptr = inttoptr i32 %iptr to i64*
- %old = call i64 @llvm.nacl.atomic.cmpxchg.i64(i64* %ptr, i64 %expected,
- i64 %desired, i32 6, i32 6)
- ret i64 %old
-}
-; CHECK-LABEL: test_atomic_cmpxchg_64
-; CHECK: push ebx
-; CHECK-DAG: mov edx
-; CHECK-DAG: mov eax
-; CHECK-DAG: mov ecx
-; CHECK-DAG: mov ebx
-; CHECK: lock cmpxchg8b QWORD PTR [e{{.[^x]}}+0x0]
-; edx and eax are already the return registers, so they don't actually
-; need to be reshuffled via movs. The next test stores the result
-; somewhere, so in that case they do need to be mov'ed.
-; ARM32-LABEL: test_atomic_cmpxchg_64
-; ARM32: dmb
-; ARM32: ldrexd [[V0:r[0-9]+]], [[V1:r[0-9]+]], {{[[]}}[[A:r[0-9]+]]{{[]]}}
-; ARM32: cmp [[V0]], {{r[0-9]+}}
-; ARM32: cmpeq [[V1]], {{r[0-9]+}}
-; ARM32: movne [[SUCCESS:r[0-9]+]],
-; ARM32: strexdeq [[SUCCESS]], r{{[0-9]+}}, r{{[0-9]+}}, {{[[]}}[[A]]{{[]]}}
-; ARM32: cmp [[SUCCESS]], #0
-; ARM32: bne
-; ARM32: dmb
-; MIPS32-LABEL: test_atomic_cmpxchg_64
-; MIPS32: sync
-; MIPS32: jal __sync_val_compare_and_swap_8
-; MIPS32: sync
-
-
-define internal i64 @test_atomic_cmpxchg_64_undef(i32 %iptr, i64 %desired) {
-entry:
- %ptr = inttoptr i32 %iptr to i64*
- %old = call i64 @llvm.nacl.atomic.cmpxchg.i64(i64* %ptr, i64 undef,
- i64 %desired, i32 6, i32 6)
- ret i64 %old
-}
-; CHECK-LABEL: test_atomic_cmpxchg_64_undef
-; CHECK: lock cmpxchg8b QWORD PTR [e{{.[^x]}}+0x0]
-; ARM32-LABEL: test_atomic_cmpxchg_64_undef
-; ARM32: mov r{{[0-9]+}}, #0
-; ARM32: mov r{{[0-9]+}}, #0
-; ARM32: dmb
-; ARM32: ldrexd [[V0:r[0-9]+]], [[V1:r[0-9]+]], {{[[]}}[[A:r[0-9]+]]{{[]]}}
-; ARM32: cmp [[V0]], {{r[0-9]+}}
-; ARM32: cmpeq [[V1]], {{r[0-9]+}}
-; ARM32: movne [[SUCCESS:r[0-9]+]],
-; ARM32: strexdeq [[SUCCESS]], r{{[0-9]+}}, r{{[0-9]+}}, {{[[]}}[[A]]{{[]]}}
-; ARM32: cmp [[SUCCESS]], #0
-; ARM32: bne
-; ARM32: dmb
-; MIPS32-LABEL: test_atomic_cmpxchg_64_undef
-; MIPS32: sync
-; MIPS32: jal __sync_val_compare_and_swap_8
-; MIPS32: sync
-
-; Test a case where %old really does need to be copied out of edx:eax.
-define internal void @test_atomic_cmpxchg_64_store(
- i32 %ret_iptr, i32 %iptr, i64 %expected, i64 %desired) {
-entry:
- %ptr = inttoptr i32 %iptr to i64*
- %old = call i64 @llvm.nacl.atomic.cmpxchg.i64(i64* %ptr, i64 %expected,
- i64 %desired, i32 6, i32 6)
- %__6 = inttoptr i32 %ret_iptr to i64*
- store i64 %old, i64* %__6, align 1
- ret void
-}
-; CHECK-LABEL: test_atomic_cmpxchg_64_store
-; CHECK: push ebx
-; CHECK-DAG: mov edx
-; CHECK-DAG: mov eax
-; CHECK-DAG: mov ecx
-; CHECK-DAG: mov ebx
-; CHECK: lock cmpxchg8b QWORD PTR [e{{.[^x]}}
-; CHECK-DAG: mov {{.*}},edx
-; CHECK-DAG: mov {{.*}},eax
-; ARM32-LABEL: test_atomic_cmpxchg_64_store
-; ARM32: dmb
-; ARM32: ldrexd [[V0:r[0-9]+]], [[V1:r[0-9]+]], {{[[]}}[[A:r[0-9]+]]{{[]]}}
-; ARM32: cmp [[V0]], {{r[0-9]+}}
-; ARM32: cmpeq [[V1]], {{r[0-9]+}}
-; ARM32: movne [[SUCCESS:r[0-9]+]],
-; ARM32: strexdeq [[SUCCESS]], r{{[0-9]+}}, r{{[0-9]+}}, {{[[]}}[[A]]{{[]]}}
-; ARM32: cmp [[SUCCESS]], #0
-; ARM32: bne
-; ARM32: dmb
-; ARM32: str
-; ARM32: str
-; MIPS32-LABEL: test_atomic_cmpxchg_64_store
-; MIPS32: sync
-; MIPS32: jal __sync_val_compare_and_swap_8
-; MIPS32: sync
-
-
-; Test with some more register pressure. When we have an alloca, ebp is
-; used to manage the stack frame, so it cannot be used as a register either.
-define internal i64 @test_atomic_cmpxchg_64_alloca(i32 %iptr, i64 %expected,
- i64 %desired) {
-entry:
- br label %eblock ; Disable alloca optimization
-eblock:
- %alloca_ptr = alloca i8, i32 16, align 16
- %ptr = inttoptr i32 %iptr to i64*
- %old = call i64 @llvm.nacl.atomic.cmpxchg.i64(i64* %ptr, i64 %expected,
- i64 %desired, i32 6, i32 6)
- store i8 0, i8* %alloca_ptr, align 1
- store i8 1, i8* %alloca_ptr, align 1
- store i8 2, i8* %alloca_ptr, align 1
- store i8 3, i8* %alloca_ptr, align 1
- %__6 = ptrtoint i8* %alloca_ptr to i32
- call void @use_ptr(i32 %__6)
- ret i64 %old
-}
-; CHECK-LABEL: test_atomic_cmpxchg_64_alloca
-; CHECK: push ebx
-; CHECK-DAG: mov edx
-; CHECK-DAG: mov eax
-; CHECK-DAG: mov ecx
-; CHECK-DAG: mov ebx
-; Ptr cannot be eax, ebx, ecx, or edx (used up for the expected and desired).
-; It also cannot be ebp since we use that for alloca. Also make sure it's
-; not esp, since that's the stack pointer and mucking with it will break
-; the later use_ptr function call.
-; That pretty much leaves esi, or edi as the only viable registers.
-; CHECK: lock cmpxchg8b QWORD PTR [e{{[ds]}}i]
-; CHECK: call {{.*}} R_{{.*}} use_ptr
-; ARM32-LABEL: test_atomic_cmpxchg_64_alloca
-; ARM32: dmb
-; ARM32: ldrexd [[V0:r[0-9]+]], [[V1:r[0-9]+]], {{[[]}}[[A:r[0-9]+]]{{[]]}}
-; ARM32: cmp [[V0]], {{r[0-9]+}}
-; ARM32: cmpeq [[V1]], {{r[0-9]+}}
-; ARM32: movne [[SUCCESS:r[0-9]+]],
-; ARM32: strexdeq [[SUCCESS]], r{{[0-9]+}}, r{{[0-9]+}}, {{[[]}}[[A]]{{[]]}}
-; ARM32: cmp [[SUCCESS]], #0
-; ARM32: bne
-; ARM32: dmb
-; MIPS32-LABEL: test_atomic_cmpxchg_64_alloca
-; MIPS32: sync
-; MIPS32: jal __sync_val_compare_and_swap_8
-; MIPS32: sync
-
-define internal i32 @test_atomic_cmpxchg_32_ignored(i32 %iptr, i32 %expected,
- i32 %desired) {
-entry:
- %ptr = inttoptr i32 %iptr to i32*
- %ignored = call i32 @llvm.nacl.atomic.cmpxchg.i32(i32* %ptr, i32 %expected,
- i32 %desired, i32 6, i32 6)
- ret i32 0
-}
-; CHECK-LABEL: test_atomic_cmpxchg_32_ignored
-; CHECK: mov eax,{{.*}}
-; CHECK: lock cmpxchg DWORD PTR [e{{[^a].}}]
-; ARM32-LABEL: test_atomic_cmpxchg_32_ignored
-; ARM32: dmb
-; ARM32: ldrex [[V:r[0-9]+]], {{[[]}}[[A:r[0-9]+]]{{[]]}}
-; ARM32: cmp [[V]], {{r[0-9]+}}
-; ARM32: movne [[SUCCESS:r[0-9]+]],
-; ARM32: strexeq [[SUCCESS]]
-; ARM32: cmp [[SUCCESS]], #0
-; ARM32: bne
-; ARM32: dmb
-; MIPS32-LABEL: test_atomic_cmpxchg_32_ignored
-; MIPS32: sync
-; MIPS32: ll
-; MIPS32: bne
-; MIPS32: sc
-; MIPS32: beq {{.*}}, $zero, {{.*}}
-; MIPS32: sync
-
-define internal i64 @test_atomic_cmpxchg_64_ignored(i32 %iptr, i64 %expected,
- i64 %desired) {
-entry:
- %ptr = inttoptr i32 %iptr to i64*
- %ignored = call i64 @llvm.nacl.atomic.cmpxchg.i64(i64* %ptr, i64 %expected,
- i64 %desired, i32 6, i32 6)
- ret i64 0
-}
-; CHECK-LABEL: test_atomic_cmpxchg_64_ignored
-; CHECK: push ebx
-; CHECK-DAG: mov edx
-; CHECK-DAG: mov eax
-; CHECK-DAG: mov ecx
-; CHECK-DAG: mov ebx
-; CHECK: lock cmpxchg8b QWORD PTR [e{{.[^x]}}+0x0]
-; ARM32-LABEL: test_atomic_cmpxchg_64_ignored
-; ARM32: dmb
-; ARM32: ldrexd [[V0:r[0-9]+]], [[V1:r[0-9]+]], {{[[]}}[[A:r[0-9]+]]{{[]]}}
-; ARM32: cmp [[V0]], {{r[0-9]+}}
-; ARM32: cmpeq [[V1]], {{r[0-9]+}}
-; ARM32: movne [[SUCCESS:r[0-9]+]],
-; ARM32: strexdeq [[SUCCESS]], r{{[0-9]+}}, r{{[0-9]+}}, {{[[]}}[[PTR]]{{[]]}}
-; ARM32: cmp [[SUCCESS]], #0
-; ARM32: bne
-; ARM32: dmb
-; MIPS32-LABEL: test_atomic_cmpxchg_64_ignored
-; MIPS32: sync
-; MIPS32: jal __sync_val_compare_and_swap_8
-; MIPS32: sync
-
-;;;; Fence and is-lock-free.
-
-define internal void @test_atomic_fence() {
-entry:
- call void @llvm.nacl.atomic.fence(i32 6)
- ret void
-}
-; CHECK-LABEL: test_atomic_fence
-; CHECK: mfence
-; ARM32-LABEL: test_atomic_fence
-; ARM32: dmb sy
-; MIPS32-LABEL: test_atomic_fence
-; MIPS32: sync
-
-define internal void @test_atomic_fence_all() {
-entry:
- call void @llvm.nacl.atomic.fence.all()
- ret void
-}
-; CHECK-LABEL: test_atomic_fence_all
-; CHECK: mfence
-; ARM32-LABEL: test_atomic_fence_all
-; ARM32: dmb sy
-; MIPS32-LABEL: test_atomic_fence_all
-; MIPS32: sync
-
-define internal i32 @test_atomic_is_lock_free(i32 %iptr) {
-entry:
- %ptr = inttoptr i32 %iptr to i8*
- %i = call i1 @llvm.nacl.atomic.is.lock.free(i32 4, i8* %ptr)
- %r = zext i1 %i to i32
- ret i32 %r
-}
-; CHECK-LABEL: test_atomic_is_lock_free
-; CHECK: mov {{.*}},0x1
-; ARM32-LABEL: test_atomic_is_lock_free
-; ARM32: mov {{.*}}, #1
-; MIPS32-LABEL: test_atomic_is_lock_free
-; MIPS32: addiu {{.*}}, $zero, 1
-
-define internal i32 @test_not_lock_free(i32 %iptr) {
-entry:
- %ptr = inttoptr i32 %iptr to i8*
- %i = call i1 @llvm.nacl.atomic.is.lock.free(i32 7, i8* %ptr)
- %r = zext i1 %i to i32
- ret i32 %r
-}
-; CHECK-LABEL: test_not_lock_free
-; CHECK: mov {{.*}},0x0
-; ARM32-LABEL: test_not_lock_free
-; ARM32: mov {{.*}}, #0
-; MIPS32-LABEL: test_not_lock_free
-; MIPS32: addiu {{.*}}, $zero, 0
-
-define internal i32 @test_atomic_is_lock_free_ignored(i32 %iptr) {
-entry:
- %ptr = inttoptr i32 %iptr to i8*
- %ignored = call i1 @llvm.nacl.atomic.is.lock.free(i32 4, i8* %ptr)
- ret i32 0
-}
-; CHECK-LABEL: test_atomic_is_lock_free_ignored
-; CHECK: mov {{.*}},0x0
-; This can get optimized out, because it's side-effect-free.
-; O2-LABEL: test_atomic_is_lock_free_ignored
-; O2-NOT: mov {{.*}}, 1
-; O2: mov {{.*}},0x0
-; ARM32O2-LABEL: test_atomic_is_lock_free_ignored
-; ARM32O2-NOT: mov {{.*}}, #1
-; ARM32O2: mov {{.*}}, #0
-; MIPS32O2-LABEL: test_atomic_is_lock_free
-; MIPS32O2-NOT: addiu {{.*}}, $zero, 1
-; MIPS32O2: addiu {{.*}}, $zero, 0
-
-; TODO(jvoung): at some point we can take advantage of the
-; fact that nacl.atomic.is.lock.free will resolve to a constant
-; (which adds DCE opportunities). Once we optimize, the test expectations
-; for this case should change.
-define internal i32 @test_atomic_is_lock_free_can_dce(i32 %iptr, i32 %x,
- i32 %y) {
-entry:
- %ptr = inttoptr i32 %iptr to i8*
- %i = call i1 @llvm.nacl.atomic.is.lock.free(i32 4, i8* %ptr)
- %i_ext = zext i1 %i to i32
- %cmp = icmp eq i32 %i_ext, 1
- br i1 %cmp, label %lock_free, label %not_lock_free
-lock_free:
- ret i32 %i_ext
-
-not_lock_free:
- %z = add i32 %x, %y
- ret i32 %z
-}
-; CHECK-LABEL: test_atomic_is_lock_free_can_dce
-; CHECK: mov {{.*}},0x1
-; CHECK: ret
-; CHECK: add
-; CHECK: ret
-
-; Test the liveness / register allocation properties of the xadd instruction.
-; Make sure we model that the Src register is modified and therefore it can't
-; share a register with an overlapping live range, even if the result of the
-; xadd instruction is unused.
-define internal void @test_xadd_regalloc() {
-entry:
- br label %body
-body:
- %i = phi i32 [ 1, %entry ], [ %i_plus_1, %body ]
- %g = bitcast [4 x i8]* @SzGlobal32 to i32*
- %unused = call i32 @llvm.nacl.atomic.rmw.i32(i32 1, i32* %g, i32 %i, i32 6)
- %i_plus_1 = add i32 %i, 1
- %cmp = icmp eq i32 %i_plus_1, 1001
- br i1 %cmp, label %done, label %body
-done:
- ret void
-}
-; O2-LABEL: test_xadd_regalloc
-;;; Some register will be used in the xadd instruction.
-; O2: lock xadd DWORD PTR {{.*}},[[REG:e..]]
-;;; Make sure that register isn't used again, e.g. as the induction variable.
-; O2-NOT: ,[[REG]]
-; O2: ret
-
-; Do the same test for the xchg instruction instead of xadd.
-define internal void @test_xchg_regalloc() {
-entry:
- br label %body
-body:
- %i = phi i32 [ 1, %entry ], [ %i_plus_1, %body ]
- %g = bitcast [4 x i8]* @SzGlobal32 to i32*
- %unused = call i32 @llvm.nacl.atomic.rmw.i32(i32 6, i32* %g, i32 %i, i32 6)
- %i_plus_1 = add i32 %i, 1
- %cmp = icmp eq i32 %i_plus_1, 1001
- br i1 %cmp, label %done, label %body
-done:
- ret void
-}
-; O2-LABEL: test_xchg_regalloc
-;;; Some register will be used in the xchg instruction.
-; O2: xchg DWORD PTR {{.*}},[[REG:e..]]
-;;; Make sure that register isn't used again, e.g. as the induction variable.
-; O2-NOT: ,[[REG]]
-; O2: ret
-
-; Same test for cmpxchg.
-define internal void @test_cmpxchg_regalloc() {
-entry:
- br label %body
-body:
- %i = phi i32 [ 1, %entry ], [ %i_plus_1, %body ]
- %g = bitcast [4 x i8]* @SzGlobal32 to i32*
- %unused = call i32 @llvm.nacl.atomic.cmpxchg.i32(i32* %g, i32 %i, i32 %i, i32 6, i32 6)
- %i_plus_1 = add i32 %i, 1
- %cmp = icmp eq i32 %i_plus_1, 1001
- br i1 %cmp, label %done, label %body
-done:
- ret void
-}
-; O2-LABEL: test_cmpxchg_regalloc
-;;; eax and some other register will be used in the cmpxchg instruction.
-; O2: lock cmpxchg DWORD PTR {{.*}},[[REG:e..]]
-;;; Make sure eax isn't used again, e.g. as the induction variable.
-; O2-NOT: ,eax
-; O2: ret
-
-; Same test for cmpxchg8b.
-define internal void @test_cmpxchg8b_regalloc() {
-entry:
- br label %body
-body:
- %i = phi i32 [ 1, %entry ], [ %i_plus_1, %body ]
- %g = bitcast [8 x i8]* @SzGlobal64 to i64*
- %i_64 = zext i32 %i to i64
- %unused = call i64 @llvm.nacl.atomic.cmpxchg.i64(i64* %g, i64 %i_64, i64 %i_64, i32 6, i32 6)
- %i_plus_1 = add i32 %i, 1
- %cmp = icmp eq i32 %i_plus_1, 1001
- br i1 %cmp, label %done, label %body
-done:
- ret void
-}
-; O2-LABEL: test_cmpxchg8b_regalloc
-;;; eax and some other register will be used in the cmpxchg instruction.
-; O2: lock cmpxchg8b QWORD PTR
-;;; Make sure eax/ecx/edx/ebx aren't used again, e.g. as the induction variable.
-; O2-NOT: ,{{eax|ecx|edx|ebx}}
-; O2: pop ebx
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/nacl-mem-intrinsics.ll b/third_party/subzero/tests_lit/llvm2ice_tests/nacl-mem-intrinsics.ll
deleted file mode 100644
index 570edda..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/nacl-mem-intrinsics.ll
+++ /dev/null
@@ -1,583 +0,0 @@
-; This tests the NaCl intrinsics memset, memcpy and memmove.
-
-; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
-; RUN: --target x8632 --sandbox -i %s --args -O2 \
-; RUN: | %if --need=target_X8632 --command FileCheck %s
-; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
-; RUN: --target x8632 --sandbox -i %s --args -Om1 --fmem-intrin-opt \
-; RUN: | %if --need=target_X8632 --command FileCheck %s
-; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
-; RUN: --target x8632 --sandbox -i %s --args -Om1 \
-; RUN: | %if --need=target_X8632 --command FileCheck --check-prefix OM1 %s
-
-; RUN: %if --need=target_ARM32 \
-; RUN: --command %p2i --filetype=obj --disassemble --target arm32 \
-; RUN: -i %s --args -O2 \
-; RUN: | %if --need=target_ARM32 \
-; RUN: --command FileCheck --check-prefix ARM32 %s
-
-; RUN: %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command %p2i --filetype=asm --assemble --disassemble --target mips32\
-; RUN: -i %s --args -Om1 \
-; RUN: | %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command FileCheck --check-prefix MIPS32 %s
-
-declare void @llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1)
-declare void @llvm.memmove.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1)
-declare void @llvm.memset.p0i8.i32(i8*, i8, i32, i32, i1)
-
-define internal void @test_memcpy(i32 %iptr_dst, i32 %iptr_src, i32 %len) {
-entry:
- %dst = inttoptr i32 %iptr_dst to i8*
- %src = inttoptr i32 %iptr_src to i8*
- call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dst, i8* %src,
- i32 %len, i32 1, i1 false)
- ret void
-}
-; CHECK-LABEL: test_memcpy
-; CHECK: call {{.*}} R_{{.*}} memcpy
-; OM1-LABEL: test_memcpy
-; OM1: call {{.*}} memcpy
-; ARM32-LABEL: test_memcpy
-; ARM32: bl {{.*}} memcpy
-; MIPS32-LABEL: test_memcpy
-; MIPS32: jal {{.*}} memcpy
-
-define internal void @test_memcpy_long_const_len(i32 %iptr_dst, i32 %iptr_src) {
-entry:
- %dst = inttoptr i32 %iptr_dst to i8*
- %src = inttoptr i32 %iptr_src to i8*
- call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dst, i8* %src,
- i32 4876, i32 1, i1 false)
- ret void
-}
-; CHECK-LABEL: test_memcpy_long_const_len
-; CHECK: call {{.*}} R_{{.*}} memcpy
-; OM1-LABEL: test_memcpy_long_const_len
-; OM1: call {{.*}} memcpy
-; ARM32-LABEL: test_memcpy_long_const_len
-; ARM32: bl {{.*}} memcpy
-; MIPS32-LABEL: test_memcpy_long_const_len
-; MIPS32: jal {{.*}} memcpy
-
-define internal void @test_memcpy_very_small_const_len(i32 %iptr_dst,
- i32 %iptr_src) {
-entry:
- %dst = inttoptr i32 %iptr_dst to i8*
- %src = inttoptr i32 %iptr_src to i8*
- call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dst, i8* %src,
- i32 2, i32 1, i1 false)
- ret void
-}
-; CHECK-LABEL: test_memcpy_very_small_const_len
-; CHECK: mov [[REG:[^,]*]],WORD PTR [{{.*}}]
-; CHECK-NEXT: mov WORD PTR [{{.*}}],[[REG]]
-; CHECK-NOT: mov
-; OM1-LABEL: test_memcpy_very_small_const_len
-; OM1: call {{.*}} memcpy
-; ARM32-LABEL: test_memcpy_very_small_const_len
-; ARM32: bl {{.*}} memcpy
-; MIPS32-LABEL: test_memcpy_very_small_const_len
-; MIPS32: jal {{.*}} memcpy
-
-define internal void @test_memcpy_const_len_3(i32 %iptr_dst, i32 %iptr_src) {
-entry:
- %dst = inttoptr i32 %iptr_dst to i8*
- %src = inttoptr i32 %iptr_src to i8*
- call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dst, i8* %src,
- i32 3, i32 1, i1 false)
- ret void
-}
-; CHECK-LABEL: test_memcpy_const_len_3
-; CHECK: mov [[REG:[^,]*]],WORD PTR [{{.*}}]
-; CHECK-NEXT: mov WORD PTR [{{.*}}],[[REG]]
-; CHECK-NEXT: mov [[REG:[^,]*]],BYTE PTR [{{.*}}+0x2]
-; CHECK-NEXT: mov BYTE PTR [{{.*}}+0x2],[[REG]]
-; CHECK-NOT: mov
-; OM1-LABEL: test_memcpy_const_len_3
-; OM1: call {{.*}} memcpy
-; ARM32-LABEL: test_memcpy_const_len_3
-; ARM32: bl {{.*}} memcpy
-; MIPS32-LABEL: test_memcpy_const_len_3
-; MIPS32: jal {{.*}} memcpy
-
-define internal void @test_memcpy_mid_const_len(i32 %iptr_dst, i32 %iptr_src) {
-entry:
- %dst = inttoptr i32 %iptr_dst to i8*
- %src = inttoptr i32 %iptr_src to i8*
- call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dst, i8* %src,
- i32 9, i32 1, i1 false)
- ret void
-}
-; CHECK-LABEL: test_memcpy_mid_const_len
-; CHECK: movq [[REG:xmm[0-9]+]],QWORD PTR [{{.*}}]
-; CHECK-NEXT: movq QWORD PTR [{{.*}}],[[REG]]
-; CHECK-NEXT: mov [[REG:[^,]*]],BYTE PTR [{{.*}}+0x8]
-; CHECK-NEXT: mov BYTE PTR [{{.*}}+0x8],[[REG]]
-; CHECK-NOT: mov
-; OM1-LABEL: test_memcpy_mid_const_len
-; OM1: call {{.*}} memcpy
-; ARM32-LABEL: test_memcpy_mid_const_len
-; ARM32: bl {{.*}} memcpy
-; MIPS32-LABEL: test_memcpy_mid_const_len
-; MIPS32: jal {{.*}} memcpy
-
-define internal void @test_memcpy_mid_const_len_overlap(i32 %iptr_dst,
- i32 %iptr_src) {
-entry:
- %dst = inttoptr i32 %iptr_dst to i8*
- %src = inttoptr i32 %iptr_src to i8*
- call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dst, i8* %src,
- i32 15, i32 1, i1 false)
- ret void
-}
-; CHECK-LABEL: test_memcpy_mid_const_len_overlap
-; CHECK: movq [[REG:xmm[0-9]+]],QWORD PTR [{{.*}}]
-; CHECK-NEXT: movq QWORD PTR [{{.*}}],[[REG]]
-; CHECK-NEXT: movq [[REG:xmm[0-9]+]],QWORD PTR [{{.*}}+0x7]
-; CHECK-NEXT: movq QWORD PTR [{{.*}}+0x7],[[REG]]
-; CHECK-NOT: mov
-; OM1-LABEL: test_memcpy_mid_const_len_overlap
-; OM1: call {{.*}} memcpy
-; ARM32-LABEL: test_memcpy_mid_const_len_overlap
-; ARM32: bl {{.*}} memcpy
-; MIPS32-LABEL: test_memcpy_mid_const_len_overlap
-; MIPS32: jal {{.*}} memcpy
-
-define internal void @test_memcpy_big_const_len_overlap(i32 %iptr_dst,
- i32 %iptr_src) {
-entry:
- %dst = inttoptr i32 %iptr_dst to i8*
- %src = inttoptr i32 %iptr_src to i8*
- call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dst, i8* %src,
- i32 30, i32 1, i1 false)
- ret void
-}
-; CHECK-LABEL: test_memcpy_big_const_len_overlap
-; CHECK: movups [[REG:xmm[0-9]+]],XMMWORD PTR [{{.*}}]
-; CHECK-NEXT: movups XMMWORD PTR [{{.*}}],[[REG]]
-; CHECK-NEXT: movups [[REG:xmm[0-9]+]],XMMWORD PTR [{{.*}}+0xe]
-; CHECK-NEXT: movups XMMWORD PTR [{{.*}}+0xe],[[REG]]
-; CHECK-NOT: mov
-; OM1-LABEL: test_memcpy_big_const_len_overlap
-; OM1: call {{.*}} memcpy
-; ARM32-LABEL: test_memcpy_big_const_len_overlap
-; ARM32: bl {{.*}} memcpy
-; MIPS32-LABEL: test_memcpy_big_const_len_overlap
-; MIPS32: jal {{.*}} memcpy
-
-define internal void @test_memcpy_large_const_len(i32 %iptr_dst,
- i32 %iptr_src) {
-entry:
- %dst = inttoptr i32 %iptr_dst to i8*
- %src = inttoptr i32 %iptr_src to i8*
- call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dst, i8* %src,
- i32 33, i32 1, i1 false)
- ret void
-}
-; CHECK-LABEL: test_memcpy_large_const_len
-; CHECK: movups [[REG:xmm[0-9]+]],XMMWORD PTR [{{.*}}+0x10]
-; CHECK-NEXT: movups XMMWORD PTR [{{.*}}+0x10],[[REG]]
-; CHECK-NEXT: movups [[REG:xmm[0-9]+]],XMMWORD PTR [{{.*}}]
-; CHECK-NEXT: movups XMMWORD PTR [{{.*}}],[[REG]]
-; CHECK-NEXT: mov [[REG:[^,]*]],BYTE PTR [{{.*}}+0x20]
-; CHECK-NEXT: mov BYTE PTR [{{.*}}+0x20],[[REG]]
-; CHECK-NOT: mov
-; OM1-LABEL: test_memcpy_large_const_len
-; OM1: call {{.*}} memcpy
-; ARM32-LABEL: test_memcpy_large_const_len
-; ARM32: bl {{.*}} memcpy
-; MIPS32-LABEL: test_memcpy_large_const_len
-; MIPS32: jal {{.*}} memcpy
-
-define internal void @test_memmove(i32 %iptr_dst, i32 %iptr_src, i32 %len) {
-entry:
- %dst = inttoptr i32 %iptr_dst to i8*
- %src = inttoptr i32 %iptr_src to i8*
- call void @llvm.memmove.p0i8.p0i8.i32(i8* %dst, i8* %src,
- i32 %len, i32 1, i1 false)
- ret void
-}
-; CHECK-LABEL: test_memmove
-; CHECK: call {{.*}} R_{{.*}} memmove
-; OM1-LABEL: test_memmove
-; OM1: call {{.*}} memmove
-; ARM32-LABEL: test_memmove
-; ARM32: bl {{.*}} memmove
-; MIPS32-LABEL: test_memmove
-; MIPS32: jal {{.*}} memmove
-
-define internal void @test_memmove_long_const_len(i32 %iptr_dst,
- i32 %iptr_src) {
-entry:
- %dst = inttoptr i32 %iptr_dst to i8*
- %src = inttoptr i32 %iptr_src to i8*
- call void @llvm.memmove.p0i8.p0i8.i32(i8* %dst, i8* %src,
- i32 4876, i32 1, i1 false)
- ret void
-}
-; CHECK-LABEL: test_memmove_long_const_len
-; CHECK: call {{.*}} R_{{.*}} memmove
-; OM1-LABEL: test_memmove_long_const_len
-; OM1: call {{.*}} memmove
-; ARM32-LABEL: test_memmove_long_const_len
-; ARM32: bl {{.*}} memmove
-; MIPS32-LABEL: test_memmove_long_const_len
-; MIPS32: jal {{.*}} memmove
-
-define internal void @test_memmove_very_small_const_len(i32 %iptr_dst,
- i32 %iptr_src) {
-entry:
- %dst = inttoptr i32 %iptr_dst to i8*
- %src = inttoptr i32 %iptr_src to i8*
- call void @llvm.memmove.p0i8.p0i8.i32(i8* %dst, i8* %src,
- i32 2, i32 1, i1 false)
- ret void
-}
-; CHECK-LABEL: test_memmove_very_small_const_len
-; CHECK: mov [[REG:[^,]*]],WORD PTR [{{.*}}]
-; CHECK-NEXT: mov WORD PTR [{{.*}}],[[REG]]
-; CHECK-NOT: mov
-; OM1-LABEL: test_memmove_very_small_const_len
-; OM1: call {{.*}} memmove
-; ARM32-LABEL: test_memmove_very_small_const_len
-; ARM32: bl {{.*}} memmove
-; MIPS32-LABEL: test_memmove_very_small_const_len
-; MIPS32: jal {{.*}} memmove
-
-define internal void @test_memmove_const_len_3(i32 %iptr_dst, i32 %iptr_src) {
-entry:
- %dst = inttoptr i32 %iptr_dst to i8*
- %src = inttoptr i32 %iptr_src to i8*
- call void @llvm.memmove.p0i8.p0i8.i32(i8* %dst, i8* %src,
- i32 3, i32 1, i1 false)
- ret void
-}
-; CHECK-LABEL: test_memmove_const_len_3
-; CHECK: mov [[REG0:[^,]*]],WORD PTR [{{.*}}]
-; CHECK-NEXT: mov [[REG1:[^,]*]],BYTE PTR [{{.*}}+0x2]
-; CHECK-NEXT: mov WORD PTR [{{.*}}],[[REG0]]
-; CHECK-NEXT: mov BYTE PTR [{{.*}}+0x2],[[REG1]]
-; CHECK-NOT: mov
-; OM1-LABEL: test_memmove_const_len_3
-; OM1: call {{.*}} memmove
-; ARM32-LABEL: test_memmove_const_len_3
-; ARM32: bl {{.*}} memmove
-; MIPS32-LABEL: test_memmove_const_len_3
-; MIPS32: jal {{.*}} memmove
-
-define internal void @test_memmove_mid_const_len(i32 %iptr_dst, i32 %iptr_src) {
-entry:
- %dst = inttoptr i32 %iptr_dst to i8*
- %src = inttoptr i32 %iptr_src to i8*
- call void @llvm.memmove.p0i8.p0i8.i32(i8* %dst, i8* %src,
- i32 9, i32 1, i1 false)
- ret void
-}
-; CHECK-LABEL: test_memmove_mid_const_len
-; CHECK: movq [[REG0:xmm[0-9]+]],QWORD PTR [{{.*}}]
-; CHECK-NEXT: mov [[REG1:[^,]*]],BYTE PTR [{{.*}}+0x8]
-; CHECK-NEXT: movq QWORD PTR [{{.*}}],[[REG0]]
-; CHECK-NEXT: mov BYTE PTR [{{.*}}+0x8],[[REG1]]
-; CHECK-NOT: mov
-; OM1-LABEL: test_memmove_mid_const_len
-; OM1: call {{.*}} memmove
-; ARM32-LABEL: test_memmove_mid_const_len
-; ARM32: bl {{.*}} memmove
-; MIPS32-LABEL: test_memmove_mid_const_len
-; MIPS32: jal {{.*}} memmove
-
-define internal void @test_memmove_mid_const_len_overlap(i32 %iptr_dst,
- i32 %iptr_src) {
-entry:
- %dst = inttoptr i32 %iptr_dst to i8*
- %src = inttoptr i32 %iptr_src to i8*
- call void @llvm.memmove.p0i8.p0i8.i32(i8* %dst, i8* %src,
- i32 15, i32 1, i1 false)
- ret void
-}
-; CHECK-LABEL: test_memmove_mid_const_len_overlap
-; CHECK: movq [[REG0:xmm[0-9]+]],QWORD PTR [{{.*}}]
-; CHECK-NEXT: movq [[REG1:xmm[0-9]+]],QWORD PTR [{{.*}}+0x7]
-; CHECK-NEXT: movq QWORD PTR [{{.*}}],[[REG0]]
-; CHECK-NEXT: movq QWORD PTR [{{.*}}+0x7],[[REG1]]
-; CHECK-NOT: mov
-; OM1-LABEL: test_memmove_mid_const_len_overlap
-; OM1: call {{.*}} memmove
-; ARM32-LABEL: test_memmove_mid_const_len_overlap
-; ARM32: bl {{.*}} memmove
-; MIPS32-LABEL: test_memmove_mid_const_len_overlap
-; MIPS32: jal {{.*}} memmove
-
-define internal void @test_memmove_big_const_len_overlap(i32 %iptr_dst,
- i32 %iptr_src) {
-entry:
- %dst = inttoptr i32 %iptr_dst to i8*
- %src = inttoptr i32 %iptr_src to i8*
- call void @llvm.memmove.p0i8.p0i8.i32(i8* %dst, i8* %src,
- i32 30, i32 1, i1 false)
- ret void
-}
-; CHECK-LABEL: test_memmove_big_const_len_overlap
-; CHECK: movups [[REG0:xmm[0-9]+]],XMMWORD PTR [{{.*}}]
-; CHECK-NEXT: movups [[REG1:xmm[0-9]+]],XMMWORD PTR [{{.*}}+0xe]
-; CHECK-NEXT: movups XMMWORD PTR [{{.*}}],[[REG0]]
-; CHECK-NEXT: movups XMMWORD PTR [{{.*}}+0xe],[[REG1]]
-; CHECK-NOT: mov
-; OM1-LABEL: test_memmove_big_const_len_overlap
-; OM1: call {{.*}} memmove
-; ARM32-LABEL: test_memmove_big_const_len_overlap
-; ARM32: bl {{.*}} memmove
-; MIPS32-LABEL: test_memmove_big_const_len_overlap
-; MIPS32: jal {{.*}} memmove
-
-define internal void @test_memmove_large_const_len(i32 %iptr_dst,
- i32 %iptr_src) {
-entry:
- %dst = inttoptr i32 %iptr_dst to i8*
- %src = inttoptr i32 %iptr_src to i8*
- call void @llvm.memmove.p0i8.p0i8.i32(i8* %dst, i8* %src,
- i32 33, i32 1, i1 false)
- ret void
-}
-; CHECK-LABEL: test_memmove_large_const_len
-; CHECK: movups [[REG0:xmm[0-9]+]],XMMWORD PTR [{{.*}}+0x10]
-; CHECK-NEXT: movups [[REG1:xmm[0-9]+]],XMMWORD PTR [{{.*}}]
-; CHECK-NEXT: mov [[REG2:[^,]*]],BYTE PTR [{{.*}}+0x20]
-; CHECK-NEXT: movups XMMWORD PTR [{{.*}}+0x10],[[REG0]]
-; CHECK-NEXT: movups XMMWORD PTR [{{.*}}],[[REG1]]
-; CHECK-NEXT: mov BYTE PTR [{{.*}}+0x20],[[REG2]]
-; CHECK-NOT: mov
-; OM1-LABEL: test_memmove_large_const_len
-; OM1: call {{.*}} memmove
-; ARM32-LABEL: test_memmove_large_const_len
-; ARM32: bl {{.*}} memmove
-; MIPS32-LABEL: test_memmove_large_const_len
-; MIPS32: jal {{.*}} memmove
-
-define internal void @test_memset(i32 %iptr_dst, i32 %wide_val, i32 %len) {
-entry:
- %val = trunc i32 %wide_val to i8
- %dst = inttoptr i32 %iptr_dst to i8*
- call void @llvm.memset.p0i8.i32(i8* %dst, i8 %val,
- i32 %len, i32 1, i1 false)
- ret void
-}
-; CHECK-LABEL: test_memset
-; CHECK: movzx
-; CHECK: call {{.*}} R_{{.*}} memset
-; OM1-LABEL: test_memset
-; OM1: movzx
-; OM1: call {{.*}} R_{{.*}} memset
-; ARM32-LABEL: test_memset
-; ARM32: uxtb
-; ARM32: bl {{.*}} memset
-; MIPS32-LABEL: test_memset
-; MIPS32: jal {{.*}} memset
-
-define internal void @test_memset_const_len_align(i32 %iptr_dst,
- i32 %wide_val) {
-entry:
- %val = trunc i32 %wide_val to i8
- %dst = inttoptr i32 %iptr_dst to i8*
- call void @llvm.memset.p0i8.i32(i8* %dst, i8 %val,
- i32 32, i32 1, i1 false)
- ret void
-}
-; CHECK-LABEL: test_memset_const_len_align
-; CHECK: movzx
-; CHECK: call {{.*}} R_{{.*}} memset
-; OM1-LABEL: test_memset_const_len_align
-; OM1: movzx
-; OM1: call {{.*}} R_{{.*}} memset
-; ARM32-LABEL: test_memset_const_len_align
-; ARM32: uxtb
-; ARM32: bl {{.*}} memset
-; MIPS32-LABEL: test_memset_const_len_align
-; MIPS32: jal {{.*}} memset
-
-define internal void @test_memset_long_const_len_zero_val_align(
- i32 %iptr_dst) {
-entry:
- %dst = inttoptr i32 %iptr_dst to i8*
- call void @llvm.memset.p0i8.i32(i8* %dst, i8 0,
- i32 4876, i32 1, i1 false)
- ret void
-}
-; CHECK-LABEL: test_memset_long_const_len_zero_val_align
-; CHECK: call {{.*}} R_{{.*}} memset
-; OM1-LABEL: test_memset_long_const_len_zero_val_align
-; OM1: call {{.*}} R_{{.*}} memset
-; ARM32-LABEL: test_memset_long_const_len_zero_val_align
-; ARM32: uxtb
-; ARM32: bl {{.*}} memset
-; MIPS32-LABEL: test_memset_long_const_len_zero_val_align
-; MIPS32: jal {{.*}} memset
-
-define internal void @test_memset_const_val(i32 %iptr_dst, i32 %len) {
-entry:
- %dst = inttoptr i32 %iptr_dst to i8*
- call void @llvm.memset.p0i8.i32(i8* %dst, i8 0, i32 %len, i32 1, i1 false)
- ret void
-}
-; CHECK-LABEL: test_memset_const_val
-; CHECK-NOT: movzx
-; CHECK: call {{.*}} R_{{.*}} memset
-; OM1-LABEL: test_memset_const_val
-; OM1: call {{.*}} R_{{.*}} memset
-; ARM32-LABEL: test_memset_const_val
-; ARM32: uxtb
-; ARM32: bl {{.*}} memset
-; MIPS32-LABEL: test_memset_const_val
-; MIPS32: jal {{.*}} memset
-
-define internal void @test_memset_const_val_len_very_small(i32 %iptr_dst) {
-entry:
- %dst = inttoptr i32 %iptr_dst to i8*
- call void @llvm.memset.p0i8.i32(i8* %dst, i8 10, i32 2, i32 1, i1 false)
- ret void
-}
-; CHECK-LABEL: test_memset_const_val_len_very_small
-; CHECK: mov WORD PTR [{{.*}}],0xa0a
-; CHECK-NOT: mov
-; OM1-LABEL: test_memset_const_val_len_very_small
-; OM1: call {{.*}} R_{{.*}} memset
-; ARM32-LABEL: test_memset_const_val_len_very_small
-; ARM32: uxtb
-; ARM32: bl {{.*}} memset
-; MIPS32-LABEL: test_memset_const_val_len_very_small
-; MIPS32: jal {{.*}} memset
-
-define internal void @test_memset_const_val_len_3(i32 %iptr_dst) {
-entry:
- %dst = inttoptr i32 %iptr_dst to i8*
- call void @llvm.memset.p0i8.i32(i8* %dst, i8 16, i32 3, i32 1, i1 false)
- ret void
-}
-; CHECK-LABEL: test_memset_const_val_len_3
-; CHECK: mov WORD PTR [{{.*}}],0x1010
-; CHECK-NEXT: mov BYTE PTR [{{.*}}+0x2],0x10
-; CHECK-NOT: mov
-; OM1-LABEL: test_memset_const_val_len_3
-; OM1: call {{.*}} R_{{.*}} memset
-; ARM32-LABEL: test_memset_const_val_len_3
-; ARM32: uxtb
-; ARM32: bl {{.*}} memset
-; MIPS32-LABEL: test_memset_const_val_len_3
-; MIPS32: jal {{.*}} memset
-
-define internal void @test_memset_const_val_len_mid(i32 %iptr_dst) {
-entry:
- %dst = inttoptr i32 %iptr_dst to i8*
- call void @llvm.memset.p0i8.i32(i8* %dst, i8 32, i32 9, i32 1, i1 false)
- ret void
-}
-; CHECK-LABEL: test_memset_const_val_len_mid
-; CHECK: mov DWORD PTR [{{.*}}+0x4],0x20202020
-; CHECK: mov DWORD PTR [{{.*}}],0x20202020
-; CHECK-NEXT: mov BYTE PTR [{{.*}}+0x8],0x20
-; CHECK-NOT: mov
-; OM1-LABEL: test_memset_const_val_len_mid
-; OM1: call {{.*}} R_{{.*}} memset
-; ARM32-LABEL: test_memset_const_val_len_mid
-; ARM32: uxtb
-; ARM32: bl {{.*}} memset
-; MIPS32-LABEL: test_memset_const_val_len_mid
-; MIPS32: jal {{.*}} memset
-
-; Same as above, but with a negative value.
-define internal void @test_memset_const_neg_val_len_mid(i32 %iptr_dst) {
-entry:
- %dst = inttoptr i32 %iptr_dst to i8*
- call void @llvm.memset.p0i8.i32(i8* %dst, i8 -128, i32 9, i32 1, i1 false)
- ret void
-}
-; CHECK-LABEL: test_memset_const_neg_val_len_mid
-; CHECK: mov DWORD PTR [{{.*}}+0x4],0x80808080
-; CHECK: mov DWORD PTR [{{.*}}],0x80808080
-; CHECK-NEXT: mov BYTE PTR [{{.*}}+0x8],0x80
-; CHECK-NOT: mov
-; OM1-LABEL: test_memset_const_neg_val_len_mid
-; OM1: call {{.*}} R_{{.*}} memset
-; ARM32-LABEL: test_memset_const_neg_val_len_mid
-; ARM32: uxtb
-; ARM32: bl {{.*}} memset
-; MIPS32-LABEL: test_memset_const_neg_val_len_mid
-; MIPS32: jal {{.*}} memset
-
-define internal void @test_memset_zero_const_len_small(i32 %iptr_dst) {
-entry:
- %dst = inttoptr i32 %iptr_dst to i8*
- call void @llvm.memset.p0i8.i32(i8* %dst, i8 0, i32 12, i32 1, i1 false)
- ret void
-}
-; CHECK-LABEL: test_memset_zero_const_len_small
-; CHECK: pxor [[ZERO:xmm[0-9]+]],[[ZERO]]
-; CHECK-NEXT: movq QWORD PTR [{{.*}}],[[ZERO]]
-; CHECK-NEXT: mov DWORD PTR [{{.*}}+0x8],0x0
-; CHECK-NOT: mov
-; OM1-LABEL: test_memset_zero_const_len_small
-; OM1: call {{.*}} R_{{.*}} memset
-; ARM32-LABEL: test_memset_zero_const_len_small
-; ARM32: uxtb
-; ARM32: bl {{.*}} memset
-; MIPS32-LABEL: test_memset_zero_const_len_small
-; MIPS32: jal {{.*}} memset
-
-define internal void @test_memset_zero_const_len_small_overlap(i32 %iptr_dst) {
-entry:
- %dst = inttoptr i32 %iptr_dst to i8*
- call void @llvm.memset.p0i8.i32(i8* %dst, i8 0, i32 15, i32 1, i1 false)
- ret void
-}
-; CHECK-LABEL: test_memset_zero_const_len_small_overlap
-; CHECK: pxor [[ZERO:xmm[0-9]+]],[[ZERO]]
-; CHECK-NEXT: movq QWORD PTR [{{.*}}],[[ZERO]]
-; CHECK-NEXT: movq QWORD PTR [{{.*}}+0x7],[[ZERO]]
-; CHECK-NOT: mov
-; OM1-LABEL: test_memset_zero_const_len_small_overlap
-; OM1: call {{.*}} R_{{.*}} memset
-; ARM32-LABEL: test_memset_zero_const_len_small_overlap
-; ARM32: uxtb
-; ARM32: bl {{.*}} memset
-; MIPS32-LABEL: test_memset_zero_const_len_small_overlap
-; MIPS32: jal {{.*}} memset
-
-define internal void @test_memset_zero_const_len_big_overlap(i32 %iptr_dst) {
-entry:
- %dst = inttoptr i32 %iptr_dst to i8*
- call void @llvm.memset.p0i8.i32(i8* %dst, i8 0, i32 30, i32 1, i1 false)
- ret void
-}
-; CHECK-LABEL: test_memset_zero_const_len_big_overlap
-; CHECK: pxor [[ZERO:xmm[0-9]+]],[[ZERO]]
-; CHECK-NEXT: movups XMMWORD PTR [{{.*}}],[[ZERO]]
-; CHECK-NEXT: movups XMMWORD PTR [{{.*}}+0xe],[[ZERO]]
-; CHECK-NOT: mov
-; OM1-LABEL: test_memset_zero_const_len_big_overlap
-; OM1: call {{.*}} R_{{.*}} memset
-; ARM32-LABEL: test_memset_zero_const_len_big_overlap
-; ARM32: uxtb
-; ARM32: bl {{.*}} memset
-; MIPS32-LABEL: test_memset_zero_const_len_big_overlap
-; MIPS32: jal {{.*}} memset
-
-define internal void @test_memset_zero_const_len_large(i32 %iptr_dst) {
-entry:
- %dst = inttoptr i32 %iptr_dst to i8*
- call void @llvm.memset.p0i8.i32(i8* %dst, i8 0, i32 33, i32 1, i1 false)
- ret void
-}
-; CHECK-LABEL: test_memset_zero_const_len_large
-; CHECK: pxor [[ZERO:xmm[0-9]+]],[[ZERO]]
-; CHECK-NEXT: movups XMMWORD PTR [{{.*}}+0x10],[[ZERO]]
-; CHECK-NEXT: movups XMMWORD PTR [{{.*}}],[[ZERO]]
-; CHECK-NEXT: mov BYTE PTR [{{.*}}+0x20],0x0
-; CHECK-NOT: mov
-; OM1-LABEL: test_memset_zero_const_len_large
-; OM1: call {{.*}} R_{{.*}} memset
-; ARM32-LABEL: test_memset_zero_const_len_large
-; ARM32: uxtb
-; ARM32: bl {{.*}} memset
-; MIPS32-LABEL: test_memset_zero_const_len_large
-; MIPS32: jal {{.*}} memset
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/nacl-other-intrinsics.ll b/third_party/subzero/tests_lit/llvm2ice_tests/nacl-other-intrinsics.ll
deleted file mode 100644
index 003fe38..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/nacl-other-intrinsics.ll
+++ /dev/null
@@ -1,714 +0,0 @@
-; This tests the NaCl intrinsics not related to atomic operations.
-
-; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
-; RUN: --target x8632 --sandbox -i %s --args -O2 \
-; RUN: -allow-externally-defined-symbols \
-; RUN: | %if --need=target_X8632 --command FileCheck %s
-; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
-; RUN: --target x8632 --sandbox -i %s --args -Om1 \
-; RUN: -allow-externally-defined-symbols \
-; RUN: | %if --need=target_X8632 --command FileCheck %s
-
-; Do another run w/ O2 and a different check-prefix (otherwise O2 and Om1
-; share the same "CHECK" prefix). This separate run helps check that
-; some code is optimized out.
-; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
-; RUN: --target x8632 --sandbox -i %s --args -O2 \
-; RUN: -allow-externally-defined-symbols \
-; RUN: | %if --need=target_X8632 \
-; RUN: --command FileCheck --check-prefix=CHECKO2REM %s
-
-; Do O2 runs without -sandbox to make sure llvm.nacl.read.tp gets
-; lowered to __nacl_read_tp instead of gs:0x0.
-; We also know that because it's O2, it'll have the O2REM optimizations.
-; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
-; RUN: --target x8632 -i %s --args -O2 \
-; RUN: -allow-externally-defined-symbols \
-; RUN: | %if --need=target_X8632 \
-; RUN: --command FileCheck --check-prefix=CHECKO2UNSANDBOXEDREM %s
-
-; RUN: %if --need=target_ARM32 \
-; RUN: --command %p2i --filetype=obj --disassemble --target arm32 \
-; RUN: -i %s --args -O2 \
-; RUN: -allow-externally-defined-symbols \
-; RUN: | %if --need=target_ARM32 \
-; RUN: --command FileCheck --check-prefix ARM32 %s
-
-; RUN: %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command %p2i --filetype=asm --assemble --disassemble --target mips32\
-; RUN: -i %s --args -Om1 --skip-unimplemented \
-; RUN: -allow-externally-defined-symbols \
-; RUN: | %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command FileCheck --check-prefix MIPS32 %s
-
-declare i8* @llvm.nacl.read.tp()
-declare void @llvm.nacl.longjmp(i8*, i32)
-declare i32 @llvm.nacl.setjmp(i8*)
-declare float @llvm.sqrt.f32(float)
-declare double @llvm.sqrt.f64(double)
-declare float @llvm.fabs.f32(float)
-declare double @llvm.fabs.f64(double)
-declare <4 x float> @llvm.fabs.v4f32(<4 x float>)
-declare void @llvm.trap()
-declare i16 @llvm.bswap.i16(i16)
-declare i32 @llvm.bswap.i32(i32)
-declare i64 @llvm.bswap.i64(i64)
-declare i32 @llvm.ctlz.i32(i32, i1)
-declare i64 @llvm.ctlz.i64(i64, i1)
-declare i32 @llvm.cttz.i32(i32, i1)
-declare i64 @llvm.cttz.i64(i64, i1)
-declare i32 @llvm.ctpop.i32(i32)
-declare i64 @llvm.ctpop.i64(i64)
-declare i8* @llvm.stacksave()
-declare void @llvm.stackrestore(i8*)
-
-define internal i32 @test_nacl_read_tp() {
-entry:
- %ptr = call i8* @llvm.nacl.read.tp()
- %__1 = ptrtoint i8* %ptr to i32
- ret i32 %__1
-}
-; CHECK-LABEL: test_nacl_read_tp
-; CHECK: mov e{{.*}},{{(DWORD PTR )?}}gs:0x0
-; CHECKO2REM-LABEL: test_nacl_read_tp
-; CHECKO2REM: mov e{{.*}},{{(DWORD PTR )?}}gs:0x0
-; CHECKO2UNSANDBOXEDREM-LABEL: test_nacl_read_tp
-; CHECKO2UNSANDBOXEDREM: call {{.*}} R_{{.*}} __nacl_read_tp
-; MIPS32-LABEL: test_nacl_read_tp
-; MIPS32: jal {{.*}} __nacl_read_tp
-
-define internal i32 @test_nacl_read_tp_more_addressing() {
-entry:
- %ptr = call i8* @llvm.nacl.read.tp()
- %__1 = ptrtoint i8* %ptr to i32
- %x = add i32 %__1, %__1
- %__3 = inttoptr i32 %x to i32*
- %v = load i32, i32* %__3, align 1
- %v_add = add i32 %v, 1
-
- %ptr2 = call i8* @llvm.nacl.read.tp()
- %__6 = ptrtoint i8* %ptr2 to i32
- %y = add i32 %__6, 4
- %__8 = inttoptr i32 %y to i32*
- %v_add2 = add i32 %v, 4
- store i32 %v_add2, i32* %__8, align 1
- ret i32 %v
-}
-; CHECK-LABEL: test_nacl_read_tp_more_addressing
-; CHECK: mov e{{.*}},{{(DWORD PTR )?}}gs:0x0
-; CHECK: mov e{{.*}},{{(DWORD PTR )?}}gs:0x0
-; CHECKO2REM-LABEL: test_nacl_read_tp_more_addressing
-; CHECKO2REM: mov e{{.*}},{{(DWORD PTR )?}}gs:0x0
-; CHECKO2REM: mov e{{.*}},{{(DWORD PTR )?}}gs:0x0
-; CHECKO2UNSANDBOXEDREM-LABEL: test_nacl_read_tp_more_addressing
-; CHECKO2UNSANDBOXEDREM: call {{.*}} R_{{.*}} __nacl_read_tp
-; CHECKO2UNSANDBOXEDREM: call {{.*}} R_{{.*}} __nacl_read_tp
-; MIPS32-LABEL: test_nacl_read_tp_more_addressing
-; MIPS32: jal {{.*}} __nacl_read_tp
-
-define internal i32 @test_nacl_read_tp_dead(i32 %a) {
-entry:
- %ptr = call i8* @llvm.nacl.read.tp()
- ; Not actually using the result of nacl read tp call.
- ; In O2 mode this should be DCE'ed.
- ret i32 %a
-}
-; Consider nacl.read.tp side-effect free, so it can be eliminated.
-; CHECKO2REM-LABEL: test_nacl_read_tp_dead
-; CHECKO2REM-NOT: mov e{{.*}}, DWORD PTR gs:0x0
-; CHECKO2UNSANDBOXEDREM-LABEL: test_nacl_read_tp_dead
-; CHECKO2UNSANDBOXEDREM-NOT: call {{.*}} R_{{.*}} __nacl_read_tp
-; MIPS32-LABEL: test_nacl_read_tp_dead
-; MIPS32: jal {{.*}} __nacl_read_tp
-
-define internal i32 @test_setjmplongjmp(i32 %iptr_env) {
-entry:
- %env = inttoptr i32 %iptr_env to i8*
- %i = call i32 @llvm.nacl.setjmp(i8* %env)
- %r1 = icmp eq i32 %i, 0
- br i1 %r1, label %Zero, label %NonZero
-Zero:
- ; Redundant inttoptr, to make --pnacl cast-eliding/re-insertion happy.
- %env2 = inttoptr i32 %iptr_env to i8*
- call void @llvm.nacl.longjmp(i8* %env2, i32 1)
- ret i32 0
-NonZero:
- ret i32 1
-}
-; CHECK-LABEL: test_setjmplongjmp
-; CHECK: call {{.*}} R_{{.*}} setjmp
-; CHECK: call {{.*}} R_{{.*}} longjmp
-; CHECKO2REM-LABEL: test_setjmplongjmp
-; CHECKO2REM: call {{.*}} R_{{.*}} setjmp
-; CHECKO2REM: call {{.*}} R_{{.*}} longjmp
-; ARM32-LABEL: test_setjmplongjmp
-; ARM32: bl {{.*}} setjmp
-; ARM32: bl {{.*}} longjmp
-; MIPS32-LABEL: test_setjmplongjmp
-; MIPS32: jal {{.*}} setjmp
-; MIPS32: jal {{.*}} longjmp
-
-define internal i32 @test_setjmp_unused(i32 %iptr_env, i32 %i_other) {
-entry:
- %env = inttoptr i32 %iptr_env to i8*
- %i = call i32 @llvm.nacl.setjmp(i8* %env)
- ret i32 %i_other
-}
-; Don't consider setjmp side-effect free, so it's not eliminated if
-; result unused.
-; CHECKO2REM-LABEL: test_setjmp_unused
-; CHECKO2REM: call {{.*}} R_{{.*}} setjmp
-; MIPS32-LABEL: test_setjmp_unused
-; MIPS32: jal {{.*}} setjmp
-
-define internal float @test_sqrt_float(float %x, i32 %iptr) {
-entry:
- %r = call float @llvm.sqrt.f32(float %x)
- %r2 = call float @llvm.sqrt.f32(float %r)
- %r3 = call float @llvm.sqrt.f32(float -0.0)
- %r4 = fadd float %r2, %r3
- ret float %r4
-}
-; CHECK-LABEL: test_sqrt_float
-; CHECK: sqrtss xmm{{.*}}
-; CHECK: sqrtss xmm{{.*}}
-; CHECK: sqrtss xmm{{.*}},DWORD PTR
-; ARM32-LABEL: test_sqrt_float
-; ARM32: vsqrt.f32
-; ARM32: vsqrt.f32
-; ARM32: vsqrt.f32
-; ARM32: vadd.f32
-; MIPS32-LABEL: test_sqrt_float
-; MIPS32: sqrt.s
-; MIPS32: sqrt.s
-; MIPS32: sqrt.s
-; MIPS32: add.s
-
-define internal float @test_sqrt_float_mergeable_load(float %x, i32 %iptr) {
-entry:
- %__2 = inttoptr i32 %iptr to float*
- %y = load float, float* %__2, align 4
- %r5 = call float @llvm.sqrt.f32(float %y)
- %r6 = fadd float %x, %r5
- ret float %r6
-}
-; CHECK-LABEL: test_sqrt_float_mergeable_load
-; We could fold the load and the sqrt into one operation, but the
-; current folding only handles load + arithmetic op. The sqrt inst
-; is considered an intrinsic call and not an arithmetic op.
-; CHECK: sqrtss xmm{{.*}}
-; ARM32-LABEL: test_sqrt_float_mergeable_load
-; ARM32: vldr s{{.*}}
-; ARM32: vsqrt.f32
-
-define internal double @test_sqrt_double(double %x, i32 %iptr) {
-entry:
- %r = call double @llvm.sqrt.f64(double %x)
- %r2 = call double @llvm.sqrt.f64(double %r)
- %r3 = call double @llvm.sqrt.f64(double -0.0)
- %r4 = fadd double %r2, %r3
- ret double %r4
-}
-; CHECK-LABEL: test_sqrt_double
-; CHECK: sqrtsd xmm{{.*}}
-; CHECK: sqrtsd xmm{{.*}}
-; CHECK: sqrtsd xmm{{.*}},QWORD PTR
-; ARM32-LABEL: test_sqrt_double
-; ARM32: vsqrt.f64
-; ARM32: vsqrt.f64
-; ARM32: vsqrt.f64
-; ARM32: vadd.f64
-; MIPS32-LABEL: test_sqrt_double
-; MIPS32: sqrt.d
-; MIPS32: sqrt.d
-; MIPS32: sqrt.d
-; MIPS32: add.d
-
-define internal double @test_sqrt_double_mergeable_load(double %x, i32 %iptr) {
-entry:
- %__2 = inttoptr i32 %iptr to double*
- %y = load double, double* %__2, align 8
- %r5 = call double @llvm.sqrt.f64(double %y)
- %r6 = fadd double %x, %r5
- ret double %r6
-}
-; CHECK-LABEL: test_sqrt_double_mergeable_load
-; CHECK: sqrtsd xmm{{.*}}
-; ARM32-LABEL: test_sqrt_double_mergeable_load
-; ARM32: vldr d{{.*}}
-; ARM32: vsqrt.f64
-
-define internal float @test_sqrt_ignored(float %x, double %y) {
-entry:
- %ignored1 = call float @llvm.sqrt.f32(float %x)
- %ignored2 = call double @llvm.sqrt.f64(double %y)
- ret float 0.0
-}
-; CHECKO2REM-LABEL: test_sqrt_ignored
-; CHECKO2REM-NOT: sqrtss
-; CHECKO2REM-NOT: sqrtsd
-; MIPS32-LABEL: test_sqrt_ignored
-; MIPS32: sqrt.s
-; MIPS32: sqrt.d
-
-define internal float @test_fabs_float(float %x) {
-entry:
- %r = call float @llvm.fabs.f32(float %x)
- %r2 = call float @llvm.fabs.f32(float %r)
- %r3 = call float @llvm.fabs.f32(float -0.0)
- %r4 = fadd float %r2, %r3
- ret float %r4
-}
-;;; Specially check that the pand instruction doesn't try to operate on a 32-bit
-;;; (f32) memory operand, and instead uses two xmm registers.
-; CHECK-LABEL: test_fabs_float
-; CHECK: pcmpeqd
-; CHECK: psrld
-; CHECK: pand {{.*}}xmm{{.*}}xmm
-; CHECK: pcmpeqd
-; CHECK: psrld
-; CHECK: pand {{.*}}xmm{{.*}}xmm
-; CHECK: pcmpeqd
-; CHECK: psrld
-; CHECK: pand {{.*}}xmm{{.*}}xmm
-; MIPS32-LABEL: test_fabs_float
-; MIPS32: abs.s
-; MIPS32: abs.s
-; MIPS32: abs.s
-; MIPS32: add.s
-
-define internal double @test_fabs_double(double %x) {
-entry:
- %r = call double @llvm.fabs.f64(double %x)
- %r2 = call double @llvm.fabs.f64(double %r)
- %r3 = call double @llvm.fabs.f64(double -0.0)
- %r4 = fadd double %r2, %r3
- ret double %r4
-}
-;;; Specially check that the pand instruction doesn't try to operate on a 64-bit
-;;; (f64) memory operand, and instead uses two xmm registers.
-; CHECK-LABEL: test_fabs_double
-; CHECK: pcmpeqd
-; CHECK: psrlq
-; CHECK: pand {{.*}}xmm{{.*}}xmm
-; CHECK: pcmpeqd
-; CHECK: psrlq
-; CHECK: pand {{.*}}xmm{{.*}}xmm
-; CHECK: pcmpeqd
-; CHECK: psrlq
-; CHECK: pand {{.*}}xmm{{.*}}xmm
-; MIPS32-LABEL: test_fabs_double
-; MIPS32: abs.d
-; MIPS32: abs.d
-; MIPS32: abs.d
-; MIPS32: add.d
-
-define internal <4 x float> @test_fabs_v4f32(<4 x float> %x) {
-entry:
- %r = call <4 x float> @llvm.fabs.v4f32(<4 x float> %x)
- %r2 = call <4 x float> @llvm.fabs.v4f32(<4 x float> %r)
- %r3 = call <4 x float> @llvm.fabs.v4f32(<4 x float> undef)
- %r4 = fadd <4 x float> %r2, %r3
- ret <4 x float> %r4
-}
-; CHECK-LABEL: test_fabs_v4f32
-; CHECK: pcmpeqd
-; CHECK: psrld
-; CHECK: pand
-; CHECK: pcmpeqd
-; CHECK: psrld
-; CHECK: pand
-; CHECK: pcmpeqd
-; CHECK: psrld
-; CHECK: pand
-
-define internal i32 @test_trap(i32 %br) {
-entry:
- %r1 = icmp eq i32 %br, 0
- br i1 %r1, label %Zero, label %NonZero
-Zero:
- call void @llvm.trap()
- unreachable
-NonZero:
- ret i32 1
-}
-; CHECK-LABEL: test_trap
-; CHECK: ud2
-; ARM32-LABEL: test_trap
-; ARM32: udf
-; MIPS32-LABEL: test_trap
-; MIPS32: teq zero,zero
-
-define internal i32 @test_bswap_16(i32 %x) {
-entry:
- %x_trunc = trunc i32 %x to i16
- %r = call i16 @llvm.bswap.i16(i16 %x_trunc)
- %r_zext = zext i16 %r to i32
- ret i32 %r_zext
-}
-; CHECK-LABEL: test_bswap_16
-; Make sure this is the right operand size so that the most significant bit
-; to least significant bit rotation happens at the right boundary.
-; CHECK: rol {{[abcd]x|si|di|bp|word ptr}},0x8
-; ARM32-LABEL: test_bswap_16
-; ARM32: rev
-; ARM32: lsr {{.*}} #16
-; MIPS32-LABEL: test_bswap_16
-; MIPS32: sll {{.*}},0x8
-; MIPS32: lui {{.*}},0xff
-; MIPS32: and
-; MIPS32: sll {{.*}},0x18
-; MIPS32: or
-; MIPS32: srl {{.*}},0x10
-; MIPS32: andi {{.*}},0xffff
-
-define internal i32 @test_bswap_32(i32 %x) {
-entry:
- %r = call i32 @llvm.bswap.i32(i32 %x)
- ret i32 %r
-}
-; CHECK-LABEL: test_bswap_32
-; CHECK: bswap e{{.*}}
-; ARM32-LABEL: test_bswap_32
-; ARM32: rev
-; MIPS32-LABEL: test_bswap_32
-; MIPS32: srl {{.*}},0x18
-; MIPS32: srl {{.*}},0x8
-; MIPS32: andi {{.*}},0xff00
-; MIPS32: or
-; MIPS32: sll {{.*}},0x8
-; MIPS32: lui {{.*}},0xff
-; MIPS32: and
-; MIPS32: sll {{.*}},0x18
-; MIPS32: or
-; MIPS32: or
-
-define internal i64 @test_bswap_64(i64 %x) {
-entry:
- %r = call i64 @llvm.bswap.i64(i64 %x)
- ret i64 %r
-}
-; CHECK-LABEL: test_bswap_64
-; CHECK: bswap e{{.*}}
-; CHECK: bswap e{{.*}}
-; ARM32-LABEL: test_bswap_64
-; ARM32: rev
-; ARM32: rev
-; MIPS32-LABEL: test_bswap_64
-; MIPS32: sll {{.*}},0x8
-; MIPS32: srl {{.*}},0x18
-; MIPS32: srl {{.*}},0x8
-; MIPS32: andi {{.*}},0xff00
-; MIPS32: lui {{.*}},0xff
-; MIPS32: or
-; MIPS32: and
-; MIPS32: sll {{.*}},0x18
-; MIPS32: or
-; MIPS32: srl {{.*}},0x18
-; MIPS32: srl {{.*}},0x8
-; MIPS32: andi {{.*}},0xff00
-; MIPS32: or
-; MIPS32: or
-; MIPS32: sll {{.*}},0x8
-; MIPS32: and
-; MIPS32: sll {{.*}},0x18
-; MIPS32: or
-; MIPS32: or
-
-define internal i64 @test_bswap_64_undef() {
-entry:
- %r = call i64 @llvm.bswap.i64(i64 undef)
- ret i64 %r
-}
-; CHECK-LABEL: test_bswap_64_undef
-; CHECK: bswap e{{.*}}
-; CHECK: bswap e{{.*}}
-; ARM32-LABEL: test_bswap_64
-; ARM32: rev
-; ARM32: rev
-; MIPS32-LABEL: test_bswap_64_undef
-; MIPS32: sll {{.*}},0x8
-; MIPS32: srl {{.*}},0x18
-; MIPS32: srl {{.*}},0x8
-; MIPS32: andi {{.*}},0xff00
-; MIPS32: lui {{.*}},0xff
-; MIPS32: or
-; MIPS32: and
-; MIPS32: sll {{.*}},0x18
-; MIPS32: or
-; MIPS32: srl {{.*}},0x18
-; MIPS32: srl {{.*}},0x8
-; MIPS32: andi {{.*}},0xff00
-; MIPS32: or
-; MIPS32: or
-; MIPS32: sll {{.*}},0x8
-; MIPS32: and
-; MIPS32: sll {{.*}},0x18
-; MIPS32: or
-; MIPS32: or
-
-define internal i32 @test_ctlz_32(i32 %x) {
-entry:
- %r = call i32 @llvm.ctlz.i32(i32 %x, i1 false)
- ret i32 %r
-}
-; CHECK-LABEL: test_ctlz_32
-; TODO(jvoung): If we detect that LZCNT is supported, then use that
-; and avoid the need to do the cmovne and xor stuff to guarantee that
-; the result is well-defined w/ input == 0.
-; CHECK: bsr [[REG_TMP:e.*]],{{.*}}
-; CHECK: mov [[REG_RES:e.*]],0x3f
-; CHECK: cmovne [[REG_RES]],[[REG_TMP]]
-; CHECK: xor [[REG_RES]],0x1f
-; ARM32-LABEL: test_ctlz_32
-; ARM32: clz
-; MIPS32-LABEL: test_ctlz_32
-; MIPS32: clz
-
-define internal i32 @test_ctlz_32_const() {
-entry:
- %r = call i32 @llvm.ctlz.i32(i32 123456, i1 false)
- ret i32 %r
-}
-; Could potentially constant fold this, but the front-end should have done that.
-; The dest operand must be a register and the source operand must be a register
-; or memory.
-; CHECK-LABEL: test_ctlz_32_const
-; CHECK: bsr e{{.*}},{{.*}}e{{.*}}
-; ARM32-LABEL: test_ctlz_32_const
-; ARM32: clz
-; MIPS32-LABEL: test_ctlz_32_const
-; MIPS32: clz
-
-define internal i32 @test_ctlz_32_ignored(i32 %x) {
-entry:
- %ignored = call i32 @llvm.ctlz.i32(i32 %x, i1 false)
- ret i32 1
-}
-; CHECKO2REM-LABEL: test_ctlz_32_ignored
-; CHECKO2REM-NOT: bsr
-
-define internal i64 @test_ctlz_64(i64 %x) {
-entry:
- %r = call i64 @llvm.ctlz.i64(i64 %x, i1 false)
- ret i64 %r
-}
-; CHECKO2REM-LABEL: test_ctlz_64
-; CHECK-LABEL: test_ctlz_64
-; CHECK: bsr [[REG_TMP1:e.*]],{{.*}}
-; CHECK: mov [[REG_RES1:e.*]],0x3f
-; CHECK: cmovne [[REG_RES1]],[[REG_TMP1]]
-; CHECK: xor [[REG_RES1]],0x1f
-; CHECK: add [[REG_RES1]],0x20
-; CHECK: bsr [[REG_RES2:e.*]],{{.*}}
-; CHECK: xor [[REG_RES2]],0x1f
-; CHECK: test [[REG_UPPER:.*]],[[REG_UPPER]]
-; CHECK: cmove [[REG_RES2]],[[REG_RES1]]
-; CHECK: mov {{.*}},0x0
-; ARM32-LABEL: test_ctlz_64
-; ARM32: clz
-; ARM32: cmp {{.*}}, #0
-; ARM32: add {{.*}}, #32
-; ARM32: clzne
-; ARM32: mov {{.*}}, #0
-; MIPS32-LABEL: test_ctlz_64
-; MIPS32: clz
-; MIPS32: clz
-; MIPS32: addiu
-; MIPS32: movn
-; MIPS32: addiu
-
-define internal i32 @test_ctlz_64_const(i64 %x) {
-entry:
- %r = call i64 @llvm.ctlz.i64(i64 123456789012, i1 false)
- %r2 = trunc i64 %r to i32
- ret i32 %r2
-}
-; CHECK-LABEL: test_ctlz_64_const
-; CHECK: bsr e{{.*}},{{.*}}e{{.*}}
-; CHECK: bsr e{{.*}},{{.*}}e{{.*}}
-; ARM32-LABEL: test_ctlz_64
-; ARM32: clz
-; ARM32: clzne
-; MIPS32-LABEL: test_ctlz_64_const
-; MIPS32: clz
-; MIPS32: clz
-; MIPS32: addiu
-; MIPS32: movn
-; MIPS32: addiu
-
-define internal i32 @test_ctlz_64_ignored(i64 %x) {
-entry:
- %ignored = call i64 @llvm.ctlz.i64(i64 1234567890, i1 false)
- ret i32 2
-}
-; CHECKO2REM-LABEL: test_ctlz_64_ignored
-; CHECKO2REM-NOT: bsr
-
-define internal i32 @test_cttz_32(i32 %x) {
-entry:
- %r = call i32 @llvm.cttz.i32(i32 %x, i1 false)
- ret i32 %r
-}
-; CHECK-LABEL: test_cttz_32
-; CHECK: bsf [[REG_IF_NOTZERO:e.*]],{{.*}}
-; CHECK: mov [[REG_IF_ZERO:e.*]],0x20
-; CHECK: cmovne [[REG_IF_ZERO]],[[REG_IF_NOTZERO]]
-; ARM32-LABEL: test_cttz_32
-; ARM32: rbit
-; ARM32: clz
-; MIPS32-LABEL: test_cttz_32
-; MIPS32: addiu
-; MIPS32: nor
-; MIPS32: and
-; MIPS32: clz
-; MIPS32: li
-; MIPS32: subu
-
-define internal i64 @test_cttz_64(i64 %x) {
-entry:
- %r = call i64 @llvm.cttz.i64(i64 %x, i1 false)
- ret i64 %r
-}
-; CHECK-LABEL: test_cttz_64
-; CHECK: bsf [[REG_IF_NOTZERO:e.*]],{{.*}}
-; CHECK: mov [[REG_RES1:e.*]],0x20
-; CHECK: cmovne [[REG_RES1]],[[REG_IF_NOTZERO]]
-; CHECK: add [[REG_RES1]],0x20
-; CHECK: bsf [[REG_RES2:e.*]],[[REG_LOWER:.*]]
-; CHECK: test [[REG_LOWER]],[[REG_LOWER]]
-; CHECK: cmove [[REG_RES2]],[[REG_RES1]]
-; CHECK: mov {{.*}},0x0
-; ARM32-LABEL: test_cttz_64
-; ARM32: rbit
-; ARM32: rbit
-; ARM32: clz
-; ARM32: cmp {{.*}}, #0
-; ARM32: add {{.*}}, #32
-; ARM32: clzne
-; ARM32: mov {{.*}}, #0
-; MIPS32-LABEL: test_cttz_64
-; MIPS32: addiu
-; MIPS32: nor
-; MIPS32: and
-; MIPS32: clz
-; MIPS32: li
-; MIPS32: subu
-; MIPS32: addiu
-; MIPS32: nor
-; MIPS32: and
-; MIPS32: clz
-; MIPS32: li
-; MIPS32: subu
-
-define internal i32 @test_popcount_32(i32 %x) {
-entry:
- %r = call i32 @llvm.ctpop.i32(i32 %x)
- ret i32 %r
-}
-; CHECK-LABEL: test_popcount_32
-; CHECK: call {{.*}} R_{{.*}} __popcountsi2
-; ARM32-LABEL: test_popcount_32
-; ARM32: bl {{.*}} __popcountsi2
-; MIPS32-LABEL: test_popcount_32
-; MIPS32: jal {{.*}} __popcountsi2
-
-define internal i64 @test_popcount_64(i64 %x) {
-entry:
- %r = call i64 @llvm.ctpop.i64(i64 %x)
- ret i64 %r
-}
-; CHECK-LABEL: test_popcount_64
-; CHECK: call {{.*}} R_{{.*}} __popcountdi2
-; __popcountdi2 only returns a 32-bit result, so clear the upper bits of
-; the return value just in case.
-; CHECK: mov {{.*}},0x0
-; ARM32-LABEL: test_popcount_64
-; ARM32: bl {{.*}} __popcountdi2
-; ARM32: mov {{.*}}, #0
-; MIPS32-LABEL: test_popcount_64
-; MIPS32: jal {{.*}} __popcountdi2
-
-define internal i32 @test_popcount_64_ret_i32(i64 %x) {
-entry:
- %r_i64 = call i64 @llvm.ctpop.i64(i64 %x)
- %r = trunc i64 %r_i64 to i32
- ret i32 %r
-}
-; If there is a trunc, then the mov {{.*}}, 0 is dead and gets optimized out.
-; CHECKO2REM-LABEL: test_popcount_64_ret_i32
-; CHECKO2REM: call {{.*}} R_{{.*}} __popcountdi2
-; CHECKO2REM-NOT: mov {{.*}}, 0
-; MIPS32-LABEL: test_popcount_64_ret_i32
-; MIPS32: jal {{.*}} __popcountdi2
-; MIPS32: sw v0,{{.*}}
-; MIPS32: sw v1,{{.*}}
-; MIPS32: lw v0,{{.*}}
-; MIPS32: lw ra,{{.*}}
-
-define internal void @test_stacksave_noalloca() {
-entry:
- %sp = call i8* @llvm.stacksave()
- call void @llvm.stackrestore(i8* %sp)
- ret void
-}
-; CHECK-LABEL: test_stacksave_noalloca
-; CHECK: mov {{.*}},esp
-; CHECK: mov esp,{{.*}}
-; ARM32-LABEL: test_stacksave_noalloca
-; ARM32: mov {{.*}}, sp
-; ARM32: mov sp, {{.*}}
-; MIPS32-LABEL: test_stacksave_noalloca
-; MIPS32: sw sp,{{.*}}
-; MIPS32: lw [[REG:.*]],0(sp)
-; MIPS32: move sp,[[REG]]
-
-declare i32 @foo(i32 %x)
-
-define internal void @test_stacksave_multiple(i32 %x) {
-entry:
- %x_4 = mul i32 %x, 4
- %sp1 = call i8* @llvm.stacksave()
- %tmp1 = alloca i8, i32 %x_4, align 4
-
- %sp2 = call i8* @llvm.stacksave()
- %tmp2 = alloca i8, i32 %x_4, align 4
-
- %y = call i32 @foo(i32 %x)
-
- %sp3 = call i8* @llvm.stacksave()
- %tmp3 = alloca i8, i32 %x_4, align 4
-
- %__9 = bitcast i8* %tmp1 to i32*
- store i32 %y, i32* %__9, align 1
-
- %__10 = bitcast i8* %tmp2 to i32*
- store i32 %x, i32* %__10, align 1
-
- %__11 = bitcast i8* %tmp3 to i32*
- store i32 %x, i32* %__11, align 1
-
- call void @llvm.stackrestore(i8* %sp1)
- ret void
-}
-; CHECK-LABEL: test_stacksave_multiple
-; lea is used to copy from esp for the allocas.
-; Otherwise, only one stacksave is live.
-; CHECK: mov ebp,esp
-; CHECK: mov {{.*}},esp
-; CHECK: lea {{.*}},[esp+0x10]
-; CHECK: lea {{.*}},[esp+0x10]
-; CHECK: call
-; CHECK: mov esp,{{.*}}
-; CHECK: mov esp,ebp
-; ARM32-LABEL: test_stacksave_multiple
-; ARM32: mov {{.*}}, sp
-; ARM32: mov {{.*}}, sp
-; ARM32: mov {{.*}}, sp
-; ARM32: mov sp, {{.*}}
-; MIPS32-LABEL: test_stacksave_multiple
-; MIPS32: sw sp,[[MEMLOC:.*]]
-; MIPS32: sw sp,{{.*}}
-; MIPS32: sw sp,{{.*}}
-; MIPS32: lw [[REG:.*]],[[MEMLOC]]
-; MIPS32: move sp,[[REG]]
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/nonsfi.ll b/third_party/subzero/tests_lit/llvm2ice_tests/nonsfi.ll
deleted file mode 100644
index 7da6cd4..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/nonsfi.ll
+++ /dev/null
@@ -1,155 +0,0 @@
-; RUN: %p2i -i %s --target=x8632 --filetype=obj --assemble --disassemble \
-; RUN: --args -O2 -nonsfi=1 --ffunction-sections \
-; RUN: | FileCheck --check-prefix=NONSFI %s
-; RUN: %p2i -i %s --target=x8632 --filetype=obj --assemble --disassemble \
-; RUN: --args -O2 -nonsfi=0 --ffunction-sections \
-; RUN: | FileCheck --check-prefix=DEFAULT %s
-
-; RUN: %p2i -i %s --target=arm32 --filetype=obj --assemble --disassemble \
-; RUN: --args -O2 -nonsfi=1 --ffunction-sections \
-; RUN: | FileCheck --check-prefix=ARM32-NONSFI %s
-
-@G1 = internal global [4 x i8] zeroinitializer, align 4
-@G2 = internal global [4 x i8] zeroinitializer, align 4
-
-define internal void @testCallRegular() {
-entry:
- ; Make a call to a *different* function, plus use -ffunction-sections, to
- ; force an appropriately-named relocation.
- call i32 @testLoadBasic()
- ret void
-}
-; Expect a simple direct call to testCallRegular.
-; NONSFI-LABEL: testCallRegular
-; NONSFI: call {{.*}} R_386_PC32 {{.*}}testLoadBasic
-; DEFAULT-LABEL: testCallRegular
-
-; ARM32-NONSFI-LABEL: testCallRegular
-; ARM32-NONSFI: bl {{.*}} R_ARM_CALL {{.*}}testLoadBasic
-
-define internal double @testCallBuiltin(double %val) {
-entry:
- %result = frem double %val, %val
- ret double %result
-}
-; Expect a simple direct call to fmod.
-; NONSFI-LABEL: testCallBuiltin
-; NONSFI: call {{.*}} R_386_PC32 fmod
-; DEFAULT-LABEL: testCallBuiltin
-
-; ARM32-NONSFI-LABEL: testCallBuiltin
-; ARM32-NONSFI: bl {{.*}} R_ARM_CALL {{.*}}fmod
-
-define internal i32 @testLoadBasic() {
-entry:
- %a = bitcast [4 x i8]* @G1 to i32*
- %b = load i32, i32* %a, align 1
- ret i32 %b
-}
-; Expect a load with a R_386_GOTOFF relocation.
-; NONSFI-LABEL: testLoadBasic
-; NONSFI: mov {{.*}} R_386_GOTOFF {{G1|.bss}}
-; DEFAULT-LABEL: testLoadBasic
-
-; ARM32 PIC load.
-; ARM32-NONSFI-LABEL: testLoadBasic
-; ARM32-NONSFI: movw {{.*}} R_ARM_MOVW_PREL_NC _GLOBAL_OFFSET_TABLE_
-; ARM32-NONSFI-NEXT: movt {{.*}} R_ARM_MOVT_PREL _GLOBAL_OFFSET_TABLE_
-; ARM32-NONSFI: movw [[REG:r[0-9]+]], {{.*}} R_ARM_MOVW_PREL_NC {{.*}}G1
-; ARM32-NONSFI-NEXT: movt [[REG]], {{.*}} R_ARM_MOVT_PREL {{.*}}G1
-; ARM32-NONSFI-NEXT: ldr r{{[0-9]+}}, [pc, [[REG]]]
-
-define internal i32 @testLoadFixedOffset() {
-entry:
- %a = ptrtoint [4 x i8]* @G1 to i32
- %a1 = add i32 %a, 4
- %a2 = inttoptr i32 %a1 to i32*
- %b = load i32, i32* %a2, align 1
- ret i32 %b
-}
-; Expect a load with a R_386_GOTOFF relocation plus an immediate offset.
-; NONSFI-LABEL: testLoadFixedOffset
-; NONSFI: mov {{.*}}+0x4] {{.*}} R_386_GOTOFF {{G1|.bss}}
-; DEFAULT-LABEL: testLoadFixedOffset
-
-; ARM32-NONSFI-LABEL: testLoadFixedOffset
-; ARM32-NONSFI: movw [[GOT:r[0-9]+]], {{.*}} R_ARM_MOVW_PREL_NC _GLOBAL_OFFSET_TABLE_
-; ARM32-NONSFI-NEXT: movt [[GOT]], {{.*}} R_ARM_MOVT_PREL _GLOBAL_OFFSET_TABLE_
-; ARM32-NONSFI: movw [[REG:r[0-9]+]], {{.*}} R_ARM_MOVW_PREL_NC {{.*}}G1
-; ARM32-NONSFI-NEXT: movt [[REG]], {{.*}} R_ARM_MOVT_PREL {{.*}}G1
-; ARM32-NONSFI-NEXT: ldr [[ADDR:r[0-9]+]], [pc, [[REG]]]
-; ARM32-NONSFI-NEXT: add [[G1BASE:r[0-9]+]], [[GOT]], [[ADDR]]
-; ARM32-NONSFI-NEXT: add {{.*}}, [[G1BASE]], #4
-
-define internal i32 @testLoadIndexed(i32 %idx) {
-entry:
- %a = ptrtoint [4 x i8]* @G1 to i32
- %a0 = mul i32 %idx, 4
- %a1 = add i32 %a0, 12
- %a2 = add i32 %a1, %a
- %a3 = inttoptr i32 %a2 to i32*
- %b = load i32, i32* %a3, align 1
- ret i32 %b
-}
-; Expect a load with a R_386_GOTOFF relocation plus an immediate offset, plus a
-; scaled index register.
-; NONSFI-LABEL: testLoadIndexed
-; NONSFI: mov {{.*}}*4+0xc] {{.*}} R_386_GOTOFF {{G1|.bss}}
-; DEFAULT-LABEL: testLoadIndexed
-
-; ARM32-NONSFI-LABEL: testLoadIndexed
-; ARM32-NONSFI: movw [[GOT:r[0-9]+]], {{.*}} R_ARM_MOVW_PREL_NC _GLOBAL_OFFSET_TABLE_
-; ARM32-NONSFI-NEXT: movt [[GOT]], {{.*}} R_ARM_MOVT_PREL _GLOBAL_OFFSET_TABLE_
-; ARM32-NONSFI: movw [[REG:r[0-9]+]], {{.*}} R_ARM_MOVW_PREL_NC {{.*}}G1
-; ARM32-NONSFI-NEXT: movt [[REG]], {{.*}} R_ARM_MOVT_PREL {{.*}}G1
-; ARM32-NONSFI-NEXT: ldr [[ADDR:r[0-9]+]], [pc, [[REG]]]
-; ARM32-NONSFI-NEXT: add [[G1BASE:r[0-9]+]], [[GOT]], [[ADDR]]
-; ARaM32-NONSFI-NEXT: add {{.*}}, [[G1BASE]]
-
-define internal i32 @testLoadIndexedBase(i32 %base, i32 %idx) {
-entry:
- %a = ptrtoint [4 x i8]* @G1 to i32
- %a0 = mul i32 %idx, 4
- %a1 = add i32 %a0, %base
- %a2 = add i32 %a1, %a
- %a3 = add i32 %a2, 12
- %a4 = inttoptr i32 %a3 to i32*
- %b = load i32, i32* %a4, align 1
- ret i32 %b
-}
-; Expect a load with a R_386_GOTOFF relocation plus an immediate offset, but
-; without the scaled index.
-; NONSFI-LABEL: testLoadIndexedBase
-; NONSFI: mov {{.*}}*1+0xc] {{.*}} R_386_GOTOFF {{G1|.bss}}
-; By contrast, without -nonsfi, expect a load with a *R_386_32* relocation plus
-; an immediate offset, and *with* the scaled index.
-; DEFAULT-LABEL: testLoadIndexedBase
-; DEFAULT: mov {{.*}},DWORD PTR [{{.*}}+{{.*}}*4+0xc] {{.*}} R_386_32 {{G1|.bss}}
-
-define internal i32 @testLoadOpt() {
-entry:
- %a = bitcast [4 x i8]* @G1 to i32*
- %b = load i32, i32* %a, align 1
- %c = bitcast [4 x i8]* @G2 to i32*
- %d = load i32, i32* %c, align 1
- %e = add i32 %b, %d
- ret i32 %e
-}
-; Expect a load-folding optimization with a R_386_GOTOFF relocation.
-; NONSFI-LABEL: testLoadOpt
-; NONSFI: mov [[REG:e..]],{{.*}}+0x0] {{.*}} R_386_GOTOFF {{G1|.bss}}
-; NONSFI-NEXT: add [[REG]],{{.*}}+0x{{0|4}}] {{.*}} R_386_GOTOFF {{G2|.bss}}
-; DEFAULT-LABEL: testLoadOpt
-
-define internal void @testRMW() {
-entry:
- %a = bitcast [4 x i8]* @G1 to i32*
- %b = load i32, i32* %a, align 1
- %c = add i32 %b, 1234
- store i32 %c, i32* %a, align 1
- ret void
-}
-; Expect an RMW optimization with a R_386_GOTOFF relocation.
-; NONSFI-LABEL: testRMW
-; NONSFI: add DWORD PTR {{.*}}+0x0],0x4d2 {{.*}} R_386_GOTOFF {{G1|.bss}}
-; DEFAULT-LABEL: testRMW
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/nop-insertion-no-vectors.ll b/third_party/subzero/tests_lit/llvm2ice_tests/nop-insertion-no-vectors.ll
deleted file mode 100644
index 3a25270..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/nop-insertion-no-vectors.ll
+++ /dev/null
@@ -1,181 +0,0 @@
-; REQUIRES: allow_dump
-
-; RUN: %p2i -i %s --filetype=asm --assemble --disassemble --target=mips32 \
-; RUN: -a -sz-seed=1 -nop-insertion \
-; RUN: -nop-insertion-percentage=50 -max-nops-per-instruction=1 \
-; RUN: | FileCheck %s --check-prefix=MIPS32P50N1
-; RUN: %p2i -i %s --filetype=asm --assemble --disassemble --target=mips32 \
-; RUN: -a -sz-seed=1 -nop-insertion \
-; RUN: -nop-insertion-percentage=110 -max-nops-per-instruction=2 \
-; RUN: | FileCheck %s --check-prefix=MIPS32P110N2
-
-
-define internal i32 @nopInsertion(i32 %a, i32 %b, i32 %c) {
-entry:
- %a1 = add i32 %a, 1
- %b1 = add i32 %b, 2
- %c1 = add i32 %c, 3
- %a2 = sub i32 %a1, 1
- %b2 = sub i32 %b1, 2
- %c2 = sub i32 %c1, 3
- %a3 = mul i32 %a2, %b2
- %b3 = mul i32 %a3, %c2
- ret i32 %b3
-}
-
-; MIPS32P50N1-LABEL: nopInsertion
-; MIPS32P50N1: nop
-; MIPS32P50N1: addiu {{.*}}
-; MIPS32P50N1: sw {{.*}}
-; MIPS32P50N1: nop
-; MIPS32P50N1: sw {{.*}}
-; MIPS32P50N1: nop
-; MIPS32P50N1: sw {{.*}}
-; MIPS32P50N1: lw {{.*}}
-; MIPS32P50N1: addiu {{.*}},1
-; MIPS32P50N1: nop
-; MIPS32P50N1: sw {{.*}}
-; MIPS32P50N1: lw {{.*}}
-; MIPS32P50N1: nop
-; MIPS32P50N1: addiu {{.*}},2
-; MIPS32P50N1: nop
-; MIPS32P50N1: sw {{.*}}
-; MIPS32P50N1: nop
-; MIPS32P50N1: lw {{.*}}
-; MIPS32P50N1: nop
-; MIPS32P50N1: addiu {{.*}},3
-; MIPS32P50N1: sw {{.*}}
-; MIPS32P50N1: nop
-; MIPS32P50N1: lw {{.*}}
-; MIPS32P50N1: addiu {{.*}},-1
-; MIPS32P50N1: nop
-; MIPS32P50N1: sw {{.*}}
-; MIPS32P50N1: lw {{.*}}
-; MIPS32P50N1: nop
-; MIPS32P50N1: addiu {{.*}},-2
-; MIPS32P50N1: nop
-; MIPS32P50N1: sw {{.*}}
-; MIPS32P50N1: lw {{.*}}
-; MIPS32P50N1: addiu {{.*}},-3
-; MIPS32P50N1: sw {{.*}}
-; MIPS32P50N1: lw {{.*}}
-; MIPS32P50N1: lw {{.*}}
-; MIPS32P50N1: nop
-; MIPS32P50N1: mul {{.*}}
-; MIPS32P50N1: sw {{.*}}
-; MIPS32P50N1: lw {{.*}}
-; MIPS32P50N1: nop
-; MIPS32P50N1: lw {{.*}}
-; MIPS32P50N1: nop
-; MIPS32P50N1: mul {{.*}}
-; MIPS32P50N1: nop
-; MIPS32P50N1: sw {{.*}}
-; MIPS32P50N1: nop
-; MIPS32P50N1: lw {{.*}}
-; MIPS32P50N1: nop
-; MIPS32P50N1: addiu {{.*}}
-; MIPS32P50N1: jr ra
-; MIPS32P50N1: nop
-
-; MIPS32P110N2-LABEL: nopInsertion
-; MIPS32P110N2: nop
-; MIPS32P110N2: nop
-; MIPS32P110N2: addiu {{.*}}
-; MIPS32P110N2: nop
-; MIPS32P110N2: nop
-; MIPS32P110N2: sw {{.*}}
-; MIPS32P110N2: nop
-; MIPS32P110N2: nop
-; MIPS32P110N2: sw {{.*}}
-; MIPS32P110N2: nop
-; MIPS32P110N2: nop
-; MIPS32P110N2: sw {{.*}}
-; MIPS32P110N2: nop
-; MIPS32P110N2: nop
-; MIPS32P110N2: lw {{.*}}
-; MIPS32P110N2: nop
-; MIPS32P110N2: nop
-; MIPS32P110N2: addiu {{.*}},1
-; MIPS32P110N2: nop
-; MIPS32P110N2: nop
-; MIPS32P110N2: sw {{.*}}
-; MIPS32P110N2: nop
-; MIPS32P110N2: nop
-; MIPS32P110N2: lw {{.*}}
-; MIPS32P110N2: nop
-; MIPS32P110N2: nop
-; MIPS32P110N2: addiu {{.*}},2
-; MIPS32P110N2: nop
-; MIPS32P110N2: nop
-; MIPS32P110N2: sw {{.*}}
-; MIPS32P110N2: nop
-; MIPS32P110N2: nop
-; MIPS32P110N2: lw {{.*}}
-; MIPS32P110N2: nop
-; MIPS32P110N2: nop
-; MIPS32P110N2: addiu {{.*}},3
-; MIPS32P110N2: nop
-; MIPS32P110N2: nop
-; MIPS32P110N2: sw {{.*}}
-; MIPS32P110N2: nop
-; MIPS32P110N2: nop
-; MIPS32P110N2: lw {{.*}}
-; MIPS32P110N2: nop
-; MIPS32P110N2: nop
-; MIPS32P110N2: addiu {{.*}},-1
-; MIPS32P110N2: nop
-; MIPS32P110N2: nop
-; MIPS32P110N2: sw {{.*}}
-; MIPS32P110N2: nop
-; MIPS32P110N2: nop
-; MIPS32P110N2: lw {{.*}}
-; MIPS32P110N2: nop
-; MIPS32P110N2: nop
-; MIPS32P110N2: addiu {{.*}},-2
-; MIPS32P110N2: nop
-; MIPS32P110N2: nop
-; MIPS32P110N2: sw {{.*}}
-; MIPS32P110N2: nop
-; MIPS32P110N2: nop
-; MIPS32P110N2: lw {{.*}}
-; MIPS32P110N2: nop
-; MIPS32P110N2: nop
-; MIPS32P110N2: addiu {{.*}},-3
-; MIPS32P110N2: nop
-; MIPS32P110N2: nop
-; MIPS32P110N2: sw {{.*}}
-; MIPS32P110N2: nop
-; MIPS32P110N2: nop
-; MIPS32P110N2: lw {{.*}}
-; MIPS32P110N2: nop
-; MIPS32P110N2: nop
-; MIPS32P110N2: lw {{.*}}
-; MIPS32P110N2: nop
-; MIPS32P110N2: nop
-; MIPS32P110N2: mul {{.*}}
-; MIPS32P110N2: nop
-; MIPS32P110N2: nop
-; MIPS32P110N2: sw {{.*}}
-; MIPS32P110N2: nop
-; MIPS32P110N2: nop
-; MIPS32P110N2: lw {{.*}}
-; MIPS32P110N2: nop
-; MIPS32P110N2: nop
-; MIPS32P110N2: lw {{.*}}
-; MIPS32P110N2: nop
-; MIPS32P110N2: nop
-; MIPS32P110N2: mul {{.*}}
-; MIPS32P110N2: nop
-; MIPS32P110N2: nop
-; MIPS32P110N2: sw {{.*}}
-; MIPS32P110N2: nop
-; MIPS32P110N2: nop
-; MIPS32P110N2: lw {{.*}}
-; MIPS32P110N2: nop
-; MIPS32P110N2: nop
-; MIPS32P110N2: addiu {{.*}}
-; MIPS32P110N2: nop
-; MIPS32P110N2: nop
-; MIPS32P110N2: jr ra
-; MIPS32P110N2: nop
-; MIPS32P110N2: nop
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/nop-insertion.ll b/third_party/subzero/tests_lit/llvm2ice_tests/nop-insertion.ll
deleted file mode 100644
index 59ff760..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/nop-insertion.ll
+++ /dev/null
@@ -1,213 +0,0 @@
-; This is a smoke test of nop insertion.
-
-; REQUIRES: allow_dump
-
-; Use filetype=asm because this currently depends on the /* variant */
-; assembler comment.
-
-; RUN: %p2i -i %s --filetype=asm -a -sz-seed=1 -nop-insertion \
-; RUN: -nop-insertion-percentage=50 -max-nops-per-instruction=1 \
-; RUN: | FileCheck %s --check-prefix=PROB50
-; RUN: %p2i -i %s --filetype=asm -a -sz-seed=1 -nop-insertion \
-; RUN: -nop-insertion-percentage=90 -max-nops-per-instruction=1 \
-; RUN: | FileCheck %s --check-prefix=PROB90
-; RUN: %p2i -i %s --filetype=asm -a -sz-seed=1 -nop-insertion \
-; RUN: -nop-insertion-percentage=50 -max-nops-per-instruction=2 \
-; RUN: | FileCheck %s --check-prefix=MAXNOPS2
-; RUN: %p2i -i %s --filetype=asm --sandbox -a -sz-seed=1 -nop-insertion \
-; RUN: -nop-insertion-percentage=50 -max-nops-per-instruction=1 \
-; RUN: | FileCheck %s --check-prefix=SANDBOX50
-; RUN: %p2i -i %s --filetype=asm --sandbox --target=arm32 -a -sz-seed=1 \
-; RUN: -nop-insertion -nop-insertion-percentage=110 \
-; RUN: -max-nops-per-instruction=2 \
-; RUN: | FileCheck %s --check-prefix=ARM110P2
-
-
-define internal <4 x i32> @mul_v4i32(<4 x i32> %a, <4 x i32> %b) {
-entry:
- %res = mul <4 x i32> %a, %b
- ret <4 x i32> %res
-
-; PROB50-LABEL: mul_v4i32
-; PROB50: nop /* variant = 1 */
-; PROB50: subl $60, %esp
-; PROB50: nop /* variant = 3 */
-; PROB50: movups %xmm0, 32(%esp)
-; PROB50: movups %xmm1, 16(%esp)
-; PROB50: movups 32(%esp), %xmm0
-; PROB50: nop /* variant = 1 */
-; PROB50: pshufd $49, 32(%esp), %xmm1
-; PROB50: nop /* variant = 4 */
-; PROB50: pshufd $49, 16(%esp), %xmm2
-; PROB50: nop /* variant = 1 */
-; PROB50: pmuludq 16(%esp), %xmm0
-; PROB50: pmuludq %xmm2, %xmm1
-; PROB50: nop /* variant = 0 */
-; PROB50: shufps $136, %xmm1, %xmm0
-; PROB50: nop /* variant = 3 */
-; PROB50: pshufd $216, %xmm0, %xmm0
-; PROB50: nop /* variant = 1 */
-; PROB50: movups %xmm0, (%esp)
-; PROB50: movups (%esp), %xmm0
-; PROB50: addl $60, %esp
-; PROB50: ret
-
-; PROB90-LABEL: mul_v4i32
-; PROB90: nop /* variant = 1 */
-; PROB90: subl $60, %esp
-; PROB90: nop /* variant = 3 */
-; PROB90: movups %xmm0, 32(%esp)
-; PROB90: nop /* variant = 4 */
-; PROB90: movups %xmm1, 16(%esp)
-; PROB90: nop /* variant = 1 */
-; PROB90: movups 32(%esp), %xmm0
-; PROB90: nop /* variant = 4 */
-; PROB90: pshufd $49, 32(%esp), %xmm1
-; PROB90: nop /* variant = 1 */
-; PROB90: pshufd $49, 16(%esp), %xmm2
-; PROB90: nop /* variant = 4 */
-; PROB90: pmuludq 16(%esp), %xmm0
-; PROB90: nop /* variant = 2 */
-; PROB90: pmuludq %xmm2, %xmm1
-; PROB90: shufps $136, %xmm1, %xmm0
-; PROB90: nop /* variant = 1 */
-; PROB90: pshufd $216, %xmm0, %xmm0
-; PROB90: movups %xmm0, (%esp)
-; PROB90: nop /* variant = 1 */
-; PROB90: movups (%esp), %xmm0
-; PROB90: nop /* variant = 0 */
-; PROB90: addl $60, %esp
-; PROB90: nop /* variant = 0 */
-; PROB90: ret
-; PROB90: nop /* variant = 4 */
-
-; MAXNOPS2-LABEL: mul_v4i32
-; MAXNOPS2: nop /* variant = 1 */
-; MAXNOPS2: nop /* variant = 3 */
-; MAXNOPS2: subl $60, %esp
-; MAXNOPS2: movups %xmm0, 32(%esp)
-; MAXNOPS2: nop /* variant = 1 */
-; MAXNOPS2: nop /* variant = 4 */
-; MAXNOPS2: movups %xmm1, 16(%esp)
-; MAXNOPS2: nop /* variant = 1 */
-; MAXNOPS2: movups 32(%esp), %xmm0
-; MAXNOPS2: nop /* variant = 0 */
-; MAXNOPS2: nop /* variant = 3 */
-; MAXNOPS2: pshufd $49, 32(%esp), %xmm1
-; MAXNOPS2: nop /* variant = 1 */
-; MAXNOPS2: pshufd $49, 16(%esp), %xmm2
-; MAXNOPS2: pmuludq 16(%esp), %xmm0
-; MAXNOPS2: pmuludq %xmm2, %xmm1
-; MAXNOPS2: nop /* variant = 0 */
-; MAXNOPS2: shufps $136, %xmm1, %xmm0
-; MAXNOPS2: nop /* variant = 0 */
-; MAXNOPS2: nop /* variant = 0 */
-; MAXNOPS2: pshufd $216, %xmm0, %xmm0
-; MAXNOPS2: nop /* variant = 1 */
-; MAXNOPS2: nop /* variant = 3 */
-; MAXNOPS2: movups %xmm0, (%esp)
-; MAXNOPS2: nop /* variant = 3 */
-; MAXNOPS2: movups (%esp), %xmm0
-; MAXNOPS2: addl $60, %esp
-; MAXNOPS2: nop /* variant = 3 */
-; MAXNOPS2: ret
-
-
-; SANDBOX50-LABEL: mul_v4i32
-; SANDBOX50: nop /* variant = 1 */
-; SANDBOX50: subl $60, %esp
-; SANDBOX50: nop /* variant = 3 */
-; SANDBOX50: movups %xmm0, 32(%esp)
-; SANDBOX50: movups %xmm1, 16(%esp)
-; SANDBOX50: movups 32(%esp), %xmm0
-; SANDBOX50: nop /* variant = 1 */
-; SANDBOX50: pshufd $49, 32(%esp), %xmm1
-; SANDBOX50: nop /* variant = 4 */
-; SANDBOX50: pshufd $49, 16(%esp), %xmm2
-; SANDBOX50: nop /* variant = 1 */
-; SANDBOX50: pmuludq 16(%esp), %xmm0
-; SANDBOX50: pmuludq %xmm2, %xmm1
-; SANDBOX50: nop /* variant = 0 */
-; SANDBOX50: shufps $136, %xmm1, %xmm0
-; SANDBOX50: nop /* variant = 3 */
-; SANDBOX50: pshufd $216, %xmm0, %xmm0
-; SANDBOX50: nop /* variant = 1 */
-; SANDBOX50: movups %xmm0, (%esp)
-; SANDBOX50: movups (%esp), %xmm0
-; SANDBOX50: addl $60, %esp
-; SANDBOX50: pop %ecx
-; SANDBOX50: .bundle_lock
-; SANDBOX50: andl $-32, %ecx
-; SANDBOX50: jmp *%ecx
-; SANDBOX50: .bundle_unlock
-
-; ARM110P2: mul_v4i32:
-; ARM110P2-NEXT: .Lmul_v4i32$entry:
-; ARM110P2-NEXT: .bundle_lock
-; ARM110P2-NEXT: sub sp, sp, #48
-; ARM110P2-NEXT: bic sp, sp, #3221225472
-; ARM110P2-NEXT: .bundle_unlock
-; ARM110P2-NEXT: nop
-; ARM110P2-NEXT: nop
-; ARM110P2-NEXT: add ip, sp, #32
-; ARM110P2-NEXT: nop
-; ARM110P2-NEXT: nop
-; ARM110P2-NEXT: .bundle_lock
-; ARM110P2-NEXT: bic ip, ip, #3221225472
-; ARM110P2-NEXT: vst1.32 q0, [ip]
-; ARM110P2-NEXT: .bundle_unlock
-; ARM110P2-NEXT: nop
-; ARM110P2-NEXT: nop
-; ARM110P2-NEXT: # [sp, #32] = def.pseudo
-; ARM110P2-NEXT: add ip, sp, #16
-; ARM110P2-NEXT: nop
-; ARM110P2-NEXT: nop
-; ARM110P2-NEXT: .bundle_lock
-; ARM110P2-NEXT: bic ip, ip, #3221225472
-; ARM110P2-NEXT: vst1.32 q1, [ip]
-; ARM110P2-NEXT: .bundle_unlock
-; ARM110P2-NEXT: nop
-; ARM110P2-NEXT: nop
-; ARM110P2-NEXT: # [sp, #16] = def.pseudo
-; ARM110P2-NEXT: add ip, sp, #32
-; ARM110P2-NEXT: nop
-; ARM110P2-NEXT: nop
-; ARM110P2-NEXT: .bundle_lock
-; ARM110P2-NEXT: bic ip, ip, #3221225472
-; ARM110P2-NEXT: vld1.32 q0, [ip]
-; ARM110P2-NEXT: .bundle_unlock
-; ARM110P2-NEXT: nop
-; ARM110P2-NEXT: nop
-; ARM110P2-NEXT: add ip, sp, #16
-; ARM110P2-NEXT: nop
-; ARM110P2-NEXT: nop
-; ARM110P2-NEXT: .bundle_lock
-; ARM110P2-NEXT: bic ip, ip, #3221225472
-; ARM110P2-NEXT: vld1.32 q1, [ip]
-; ARM110P2-NEXT: .bundle_unlock
-; ARM110P2-NEXT: nop
-; ARM110P2-NEXT: nop
-; ARM110P2-NEXT: vmul.i32 q0, q0, q1
-; ARM110P2-NEXT: nop
-; ARM110P2-NEXT: nop
-; ARM110P2-NEXT: vst1.32 q0, [sp]
-; ARM110P2-NEXT: nop
-; ARM110P2-NEXT: nop
-; ARM110P2-NEXT: # [sp] = def.pseudo
-; ARM110P2-NEXT: vld1.32 q0, [sp]
-; ARM110P2-NEXT: nop
-; ARM110P2-NEXT: nop
-; ARM110P2-NEXT: .bundle_lock
-; ARM110P2-NEXT: add sp, sp, #48
-; ARM110P2-NEXT: bic sp, sp, #3221225472
-; ARM110P2-NEXT: .bundle_unlock
-; ARM110P2-NEXT: nop
-; ARM110P2-NEXT: nop
-; ARM110P2-NEXT: .bundle_lock
-; ARM110P2-NEXT: bic lr, lr, #3221225487
-; ARM110P2-NEXT: bx lr
-; ARM110P2-NEXT: .bundle_unlock
-; ARM110P2-NEXT: nop
-; ARM110P2-NEXT: nop
-
-}
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/phi.ll b/third_party/subzero/tests_lit/llvm2ice_tests/phi.ll
deleted file mode 100644
index d5ca2b1..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/phi.ll
+++ /dev/null
@@ -1,160 +0,0 @@
-; This tests some of the subtleties of Phi lowering. In particular,
-; it tests that it does the right thing when it tries to enable
-; compare/branch fusing.
-
-; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 --phi-edge-split=0 \
-; RUN: | FileCheck %s
-; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 --phi-edge-split=1 \
-; RUN: | FileCheck --check-prefix=SPLIT %s
-
-define internal i32 @testPhi1(i32 %arg) {
-entry:
- %cmp1 = icmp sgt i32 %arg, 0
- br i1 %cmp1, label %next, label %target
-next:
- br label %target
-target:
- %merge = phi i1 [ %cmp1, %entry ], [ false, %next ]
- %result = zext i1 %merge to i32
- ret i32 %result
-}
-; Test that compare/branch fusing does not happen, and Phi lowering is
-; put in the right place.
-; CHECK-LABEL: testPhi1
-; CHECK: cmp {{.*}},0x0
-; CHECK: setg
-; CHECK: mov [[PHI:.*]],
-; CHECK: cmp {{.*}},0x0
-; CHECK: je
-; CHECK: mov [[PHI]],0x0
-; CHECK: movzx {{.*}},[[PHI]]
-
-define internal i32 @testPhi2(i32 %arg) {
-entry:
- %cmp1 = icmp sgt i32 %arg, 0
- br i1 %cmp1, label %next, label %target
-next:
- br label %target
-target:
- %merge = phi i32 [ 12345, %entry ], [ 54321, %next ]
- ret i32 %merge
-}
-; Test that compare/branch fusing and Phi lowering happens as expected.
-; CHECK-LABEL: testPhi2
-; CHECK: mov {{.*}},0x3039
-; CHECK: cmp {{.*}},0x0
-; CHECK-NEXT: jle
-; CHECK: mov [[PHI:.*]],0xd431
-; CHECK: mov {{.*}},[[PHI]]
-
-; Test that address mode inference doesn't extend past
-; multi-definition, non-SSA Phi temporaries.
-define internal i32 @testPhi3(i32 %arg) {
-entry:
- br label %body
-body:
- %merge = phi i32 [ %arg, %entry ], [ %elt, %body ]
- %interior = add i32 %merge, 1000
- ; Trick to make a basic block local copy of interior for
- ; addressing mode optimization.
- %interior__4 = add i32 %interior, 0
- %__4 = inttoptr i32 %interior__4 to i32*
- %elt = load i32, i32* %__4, align 1
- %cmp = icmp eq i32 %elt, 0
- br i1 %cmp, label %exit, label %body
-exit:
- ; Same trick (making a basic block local copy).
- %interior__6 = add i32 %interior, 0
- %__6 = inttoptr i32 %interior__6 to i32*
- store i32 %arg, i32* %__6, align 1
- ret i32 %arg
-}
-; I can't figure out how to reliably test this for correctness, so I
-; will just include patterns for the entire current O2 sequence. This
-; may need to be changed when meaningful optimizations are added.
-; The key is to avoid the "bad" pattern like this:
-;
-; testPhi3:
-; .LtestPhi3$entry:
-; mov eax, DWORD PTR [esp+4]
-; mov ecx, eax
-; .LtestPhi3$body:
-; mov ecx, DWORD PTR [ecx+1000]
-; cmp ecx, 0
-; jne .LtestPhi3$body
-; .LtestPhi3$exit:
-; mov DWORD PTR [ecx+1000], eax
-; ret
-;
-; This is bad because the final store address is supposed to be the
-; same as the load address in the loop, but it has clearly been
-; over-optimized into a null pointer dereference.
-
-; CHECK-LABEL: testPhi3
-; CHECK: push [[EBX:.*]]
-; CHECK: mov [[EAX:.*]],DWORD PTR [esp
-; CHECK: mov [[ECX:.*]],[[EAX]]
-;;; start of loop body
-; CHECK: mov [[EDX:.*]],[[ECX]]
-; CHECK: mov {{.*}},DWORD PTR [{{.*}}+0x3e8]
-; CHECK: cmp {{.*}},0x0
-; CHECK: jne
-;;; start of epilog
-; CHECK: mov DWORD PTR {{.}}[[EDX]]+0x3e8],
-; CHECK: pop [[EBX]]
-
-; Test of "advanced phi lowering" with undef phi arg (integer vector).
-define internal <4 x i32> @test_split_undef_int_vec(<4 x i32> %arg, i32 %cond) {
-entry:
- %cmp = icmp eq i32 %cond, 0
- br i1 %cmp, label %eq, label %exit
-eq:
- br label %exit
-exit:
- %merge = phi <4 x i32> [ %arg, %entry ], [ undef, %eq ]
- ret <4 x i32> %merge
-}
-; SPLIT-LABEL: test_split_undef_int_vec
-; SPLIT: pxor
-
-; Test of "advanced phi lowering" with undef phi arg (float vector).
-define internal <4 x float> @test_split_undef_float_vec(<4 x float> %arg, i32 %cond) {
-entry:
- %cmp = icmp eq i32 %cond, 0
- br i1 %cmp, label %eq, label %exit
-eq:
- br label %exit
-exit:
- %merge = phi <4 x float> [ %arg, %entry ], [ undef, %eq ]
- ret <4 x float> %merge
-}
-; SPLIT-LABEL: test_split_undef_float_vec
-; SPLIT: pxor
-
-; Test of "advanced phi lowering" with undef phi arg (integer scalar).
-define internal i32 @test_split_undef_int_scalar(i32 %arg, i32 %cond) {
-entry:
- %cmp = icmp eq i32 %cond, 0
- br i1 %cmp, label %eq, label %exit
-eq:
- br label %exit
-exit:
- %merge = phi i32 [ %arg, %entry ], [ undef, %eq ]
- ret i32 %merge
-}
-; SPLIT-LABEL: test_split_undef_int_scalar
-; SPLIT: mov {{.*}},0x0
-
-; Test of "advanced phi lowering" with undef phi arg (float scalar).
-define internal float @test_split_undef_float_scalar(float %arg, i32 %cond) {
-entry:
- %cmp = icmp eq i32 %cond, 0
- br i1 %cmp, label %eq, label %exit
-eq:
- br label %exit
-exit:
- %merge = phi float [ %arg, %entry ], [ undef, %eq ]
- ret float %merge
-}
-; SPLIT-LABEL: test_split_undef_float_scalar
-; SPLIT: movss {{.*}},DWORD PTR
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/phi_invalid.test b/third_party/subzero/tests_lit/llvm2ice_tests/phi_invalid.test
deleted file mode 100644
index 665f09c..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/phi_invalid.test
+++ /dev/null
@@ -1,9 +0,0 @@
-; Test that a bad phi instruction is caught.
-; https://code.google.com/p/nativeclient/issues/detail?id=4304
-
-RUN: %p2i --expect-fail --tbc -i %p/Input/phi-invalid.tbc --insts 2>&1 \
-RUN: --filetype=obj --output /dev/null \
-RUN: --args -allow-externally-defined-symbols \
-RUN: | FileCheck --check-prefix=BADPHI %s
-
-; BADPHI: Phi error:
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/prune_unreachable.ll b/third_party/subzero/tests_lit/llvm2ice_tests/prune_unreachable.ll
deleted file mode 100644
index 7ce93e9..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/prune_unreachable.ll
+++ /dev/null
@@ -1,24 +0,0 @@
-; This tests that unreachable basic blocks are pruned from the CFG, so that
-; liveness analysis doesn't detect inconsistencies.
-
-; RUN: %p2i -i %s --filetype=obj --disassemble --args -Om1 \
-; RUN: -allow-externally-defined-symbols | FileCheck %s
-; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 \
-; RUN: -allow-externally-defined-symbols | FileCheck %s
-
-declare void @abort()
-
-define internal i32 @unreachable_block() {
-entry:
- ; ret_val has no reaching uses and so its assignment may be
- ; dead-code eliminated.
- %ret_val = add i32 undef, undef
- call void @abort()
- unreachable
-label:
- ; ret_val has no reaching definitions, causing an inconsistency in
- ; liveness analysis.
- ret i32 %ret_val
-}
-
-; CHECK-LABEL: unreachable_block
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/randomize-pool-immediate-basic.ll b/third_party/subzero/tests_lit/llvm2ice_tests/randomize-pool-immediate-basic.ll
deleted file mode 100644
index d8ebefe..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/randomize-pool-immediate-basic.ll
+++ /dev/null
@@ -1,133 +0,0 @@
-; This is a smoke test of constant blinding and constant pooling.
-
-; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 \
-; RUN: -sz-seed=1 -randomize-pool-immediates=randomize \
-; RUN: -randomize-pool-threshold=0x1 \
-; RUN: | FileCheck %s --check-prefix=BLINDINGO2
-; RUN: %p2i -i %s --filetype=obj --disassemble --args -Om1 \
-; RUN: -sz-seed=1 -randomize-pool-immediates=randomize \
-; RUN: -randomize-pool-threshold=0x1 \
-; RUN: | FileCheck %s --check-prefix=BLINDINGOM1
-
-; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 \
-; RUN: -sz-seed=1 -randomize-pool-immediates=pool \
-; RUN: -randomize-pool-threshold=0x1 \
-; RUN: | FileCheck %s --check-prefix=POOLING
-; RUN: %p2i -i %s --filetype=obj --disassemble --args -Om1 \
-; RUN: -sz-seed=1 -randomize-pool-immediates=pool \
-; RUN: -randomize-pool-threshold=0x1 \
-; RUN: | FileCheck %s --check-prefix=POOLING
-
-
-define internal i32 @add_arg_plus_200000(i32 %arg) {
-entry:
- %res = add i32 200000, %arg
- ret i32 %res
-
-; BLINDINGO2-LABEL: add_arg_plus_200000
-; BLINDINGO2: mov [[REG:e[a-z]*]],0x669f4eea
-; BLINDINGO2-NEXT: lea [[REG]],{{[[]}}[[REG]]-0x669c41aa{{[]]}}
-
-; BLINDINGOM1-LABEL: add_arg_plus_200000
-; BLINDINGOM1: mov [[REG:e[a-z]*]],0x669f4eea
-; BLINDINGOM1-NEXT: lea [[REG]],{{[[]}}[[REG]]-0x669c41aa{{[]]}}
-
-; POOLING-LABEL: add_arg_plus_200000
-; POOLING: mov e{{[a-z]*}},{{(DWORD PTR )?}}ds:0x0 {{[0-9a-f]*}}: R_386_32 .L$i32$00030d40
-}
-
-define internal float @load_arg_plus_200000(float* %arg) {
-entry:
- %arg.int = ptrtoint float* %arg to i32
- %addr.int = add i32 %arg.int, 200000
- %addr.ptr = inttoptr i32 %addr.int to float*
- %addr.load = load float, float* %addr.ptr, align 4
- ret float %addr.load
-; BLINDINGO2-LABEL: load_arg_plus_200000
-; BLINDINGO2: lea [[REG:e[a-z]*]],{{[[]}}{{e[a-z]*}}+0x69ed4ee7{{[]]}}
-
-; BLINDINGOM1-LABEL: load_arg_plus_200000
-; BLINDINGOM1: lea [[REG:e[a-z]*]],{{[[]}}{{e[a-z]*}}-0x69ea41a7{{[]]}}
-
-; POOLING-LABEL: load_arg_plus_200000
-; POOLING: mov e{{[a-z]*}},{{(DWORD PTR )?}}ds:0x0 {{[0-9a-f]*}}: R_386_32 .L$i32$00030d40
-}
-
-define internal i64 @add_arg_plus_64bits(i32 %arg) {
-entry:
- %0 = sext i32 %arg to i64
- %res = add i64 90000000000, %0
- ret i64 %res
-
-; BLINDINGO2-LABEL: add_arg_plus_64bits
-; BLINDINGO2: sar [[RHI:e[a-z]*]],0x1f
-; BLINDINGO2: mov [[RLO:e[a-z]*]],0x61a345a8
-; BLINDINGO2-NEXT: lea [[RLO]],{{[[]}}[[RLO]]-0x6d3841a8{{[]]}}
-
-; BLINDINGOM1-LABEL: add_arg_plus_64bits
-; BLINDINGOM1: sar [[RHI:e[a-z]*]],0x1f
-; BLINDINGOM1: mov [[RLO:e[a-z]*]],0x61a345a8
-; BLINDINGOM1-NEXT: lea [[RLO]],{{[[]}}[[RLO]]-0x6d3841a8{{[]]}}
-
-; POOLING-LABEL: add_arg_plus_64bits
-; POOLING: mov e{{[a-z]*}},{{(DWORD PTR )?}}ds:0x0 {{[0-9a-f]*}}: R_386_32 .L$i32$f46b0400
-}
-
-define internal i64 @load_arg_plus_64bits(i64* %arg) {
-entry:
- %arg.int = ptrtoint i64* %arg to i32
- %arg.new = add i32 %arg.int, 90000
- %arg.ptr = inttoptr i32 %arg.new to i64*
- %arg.load = load i64, i64* %arg.ptr, align 1
- ret i64 %arg.load
-
-; BLINDINGO2-LABEL: load_arg_plus_64bits
-; BLINDINGO2: lea e{{[a-z]*}},{{[[]}}e{{[a-z]*}}+0x7087a139{{[]]}}
-; BLINDINGO2: mov e{{[a-z]*}},DWORD PTR {{[[]}}e{{[a-z]*}}-0x708641a9{{[]]}}
-
-; BLINDINGOM1-LABEL: load_arg_plus_64bits
-; BLINDINGOM1: mov e{{[a-z]*}},0x7087a139
-; BLINDINGOM1-NEXT: lea e{{[a-z]*}},{{[[]}}e{{[a-z]*}}-0x708641a9{{[]]}}
-
-; POOLING-LABEL: load_arg_plus_64bits
-; POOLING: mov e{{[a-z]x}},{{(DWORD PTR )?}}ds:0x0 {{[0-9a-f]*}}: R_386_32 .L$i32$00000004
-}
-
-define internal i32 @add_const_8bits(i32 %a) {
-entry:
- %a_8 = trunc i32 %a to i8
- %add = add i8 %a_8, 123
- %ret = zext i8 %add to i32
- ret i32 %ret
-
-; BLINDINGO2-LABEL: add_const_8bits
-; BLINDINGO2: mov e{{[a-z]*}},0x73d44225
-; BLINDINGO2-NEXT: e{{[a-z]*}},{{[[]}}e{{[a-z]*}}-0x73d441aa{{[]]}}
-
-; BLINDINGOM1-LABEL: add_const_8bits
-; BLINDINGOM1: mov e{{[a-z]*}},0x73d44225
-; BLINDINGOM1-NEXT: e{{[a-z]*}},{{[[]}}e{{[a-z]*}}-0x73d441aa{{[]]}}
-
-; POOLING-LABEL: add_const_8bits
-; POOLING: mov {{[a-z]l}},{{(BYTE PTR )?}}ds:0x0 {{[0-9a-f]*}}: R_386_32 .L$i8$0000007b
-}
-
-define internal i32 @add_const_16bits(i32 %a) {
-entry:
- %a_16 = trunc i32 %a to i16
- %add = add i16 %a_16, 32766
- %ret = zext i16 %add to i32
- ret i32 %ret
-
-; BLINDINGO2-LABEL: add_const_16bits
-; BLINDINGO2: mov e{{[a-z]*}},0x7722c1a5
-; BLINDINGO2-NEXT: e{{[a-z]*}},{{[[]}}e{{[a-z]*}}-0x772241a7{{[]]}}
-
-; BLINDINGOM1-LABEL: add_const_16bits
-; BLINDINGOM1: mov e{{[a-z]*}},0x7722c1a5
-; BLINDINGOM1-NEXT: e{{[a-z]*}},{{[[]}}e{{[a-z]*}}-0x772241a7{{[]]}}
-
-; POOLING-LABEL: add_const_16bits
-; POOLING: mov {{[a-z]x}},{{(WORD PTR )?}}ds:0x0 {{[0-9a-f]*}}: R_386_32 .L$i16$00007ffe
-
-}
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/randomize-regalloc.ll b/third_party/subzero/tests_lit/llvm2ice_tests/randomize-regalloc.ll
deleted file mode 100644
index e13410a..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/randomize-regalloc.ll
+++ /dev/null
@@ -1,80 +0,0 @@
-; This is a smoke test of randomized register allocation. The output
-; of this test will change with changes to the random number generator
-; implementation.
-
-; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 -sz-seed=1 \
-; RUN: -randomize-regalloc -split-local-vars=0 \
-; RUN: | FileCheck %s --check-prefix=CHECK_1
-; RUN: %p2i -i %s --filetype=obj --disassemble --args -Om1 -sz-seed=1 \
-; RUN: -randomize-regalloc \
-; RUN: | FileCheck %s --check-prefix=OPTM1_1
-
-; Same tests but with a different seed, just to verify randomness.
-; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 -sz-seed=123 \
-; RUN: -randomize-regalloc -split-local-vars=0 \
-; RUN: | FileCheck %s --check-prefix=CHECK_123
-; RUN: %p2i -i %s --filetype=obj --disassemble --args -Om1 -sz-seed=123 \
-; RUN: -randomize-regalloc \
-; RUN: | FileCheck %s --check-prefix=OPTM1_123
-
-define internal <4 x i32> @mul_v4i32(<4 x i32> %a, <4 x i32> %b) {
-entry:
- %res = mul <4 x i32> %a, %b
- ret <4 x i32> %res
-; OPTM1_1-LABEL: mul_v4i32
-; OPTM1_1: sub esp,0x3c
-; OPTM1_1-NEXT: movups XMMWORD PTR [esp+0x20],xmm0
-; OPTM1_1-NEXT: movups XMMWORD PTR [esp+0x10],xmm1
-; OPTM1_1-NEXT: movups xmm0,XMMWORD PTR [esp+0x20]
-; OPTM1_1-NEXT: pshufd xmm6,XMMWORD PTR [esp+0x20],0x31
-; OPTM1_1-NEXT: pshufd xmm2,XMMWORD PTR [esp+0x10],0x31
-; OPTM1_1-NEXT: pmuludq xmm0,XMMWORD PTR [esp+0x10]
-; OPTM1_1-NEXT: pmuludq xmm6,xmm2
-; OPTM1_1-NEXT: shufps xmm0,xmm6,0x88
-; OPTM1_1-NEXT: pshufd xmm0,xmm0,0xd8
-; OPTM1_1-NEXT: movups XMMWORD PTR [esp],xmm0
-; OPTM1_1-NEXT: movups xmm0,XMMWORD PTR [esp]
-; OPTM1_1-NEXT: add esp,0x3c
-; OPTM1_1-NEXT: ret
-
-; CHECK_1-LABEL: mul_v4i32
-; CHECK_1: movups xmm7,xmm0
-; CHECK_1-NEXT: pshufd xmm0,xmm0,0x31
-; CHECK_1-NEXT: pshufd xmm5,xmm1,0x31
-; CHECK_1-NEXT: pmuludq xmm7,xmm1
-; CHECK_1-NEXT: pmuludq xmm0,xmm5
-; CHECK_1-NEXT: shufps xmm7,xmm0,0x88
-; CHECK_1-NEXT: pshufd xmm7,xmm7,0xd8
-; CHECK_1-NEXT: movups xmm0,xmm7
-; CHECK_1-NEXT: ret
-
-; OPTM1_123-LABEL: mul_v4i32
-; OPTM1_123: sub esp,0x3c
-; OPTM1_123-NEXT: movups XMMWORD PTR [esp+0x20],xmm0
-; OPTM1_123-NEXT: movups XMMWORD PTR [esp+0x10],xmm1
-; OPTM1_123-NEXT: movups xmm0,XMMWORD PTR [esp+0x20]
-; OPTM1_123-NEXT: pshufd xmm6,XMMWORD PTR [esp+0x20],0x31
-; OPTM1_123-NEXT: pshufd xmm2,XMMWORD PTR [esp+0x10],0x31
-; OPTM1_123-NEXT: pmuludq xmm0,XMMWORD PTR [esp+0x10]
-; OPTM1_123-NEXT: pmuludq xmm6,xmm2
-; OPTM1_123-NEXT: shufps xmm0,xmm6,0x88
-; OPTM1_123-NEXT: pshufd xmm0,xmm0,0xd8
-; OPTM1_123-NEXT: movups XMMWORD PTR [esp],xmm0
-; OPTM1_123-NEXT: movups xmm0,XMMWORD PTR [esp]
-; OPTM1_123-NEXT: add esp,0x3c
-; OPTM1_123-NEXT: ret
-
-; CHECK_123-LABEL: mul_v4i32
-; CHECK_123: movups xmm5,xmm0
-; CHECK_123-NEXT: pshufd xmm0,xmm0,0x31
-; CHECK_123-NEXT: pshufd xmm7,xmm1,0x31
-; CHECK_123-NEXT: pmuludq xmm5,xmm1
-; CHECK_123-NEXT: pmuludq xmm0,xmm7
-; CHECK_123-NEXT: shufps xmm5,xmm0,0x88
-; CHECK_123-NEXT: pshufd xmm5,xmm5,0xd8
-; CHECK_123-NEXT: movups xmm0,xmm5
-; CHECK_123-NEXT: ret
-}
-
-; ERRORS-NOT: ICE translation error
-; DUMP-NOT: SZ
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/rangespec.ll b/third_party/subzero/tests_lit/llvm2ice_tests/rangespec.ll
deleted file mode 100644
index aeadbf8..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/rangespec.ll
+++ /dev/null
@@ -1,68 +0,0 @@
-; Tests basic functionality of RangeSpec matching. Makes use of the fact that
-; "-verbose=status" prints the sequence number, and "-test-status" can suppress
-; this output. Note that seq=2 is the first sequence number for functions.
-
-; REQUIRES: allow_dump
-
-define internal void @Func2() { ret void }
-define internal void @Func3() { ret void }
-define internal void @Func4() { ret void }
-define internal void @Func5() { ret void }
-define internal void @Func6() { ret void }
-define internal void @Func7() { ret void }
-define internal void @Func8() { ret void }
-define internal void @Func9() { ret void }
-define internal void @Func10() { ret void }
-define internal void @Func11() { ret void }
-
-; A few tests that include everything.
-; RUN: %p2i -i %s -o /dev/null --args -verbose status -threads=0 \
-; RUN: -test-status=: \
-; RUN: | FileCheck %s --check-prefix=TEST1
-; RUN: %p2i -i %s -o /dev/null --args -verbose status -threads=0 \
-; RUN: -test-status=2: \
-; RUN: | FileCheck %s --check-prefix=TEST1
-; RUN: %p2i -i %s -o /dev/null --args -verbose status -threads=0 \
-; RUN: -test-status=:20 \
-; RUN: | FileCheck %s --check-prefix=TEST1
-; RUN: %p2i -i %s -o /dev/null --args -verbose status -threads=0 \
-; RUN: -test-status=-xxx \
-; RUN: | FileCheck %s --check-prefix=TEST1
-; TEST1: seq=2
-; TEST1: seq=3
-; TEST1: seq=4
-; TEST1: seq=5
-; TEST1: seq=6
-; TEST1: seq=7
-; TEST1: seq=8
-; TEST1: seq=9
-; TEST1: seq=10
-; TEST1: seq=11
-
-; Several ways of expressing 3+4+5+6
-; RUN: %p2i -i %s -o /dev/null --args -verbose status -threads=0 \
-; RUN: -test-status=3:7 \
-; RUN: | FileCheck %s --check-prefix=TEST2
-; RUN: %p2i -i %s -o /dev/null --args -verbose status -threads=0 \
-; RUN: -test-status=3:6,6 \
-; RUN: | FileCheck %s --check-prefix=TEST2
-; RUN: %p2i -i %s -o /dev/null --args -verbose status -threads=0 \
-; RUN: -test-status=5,3:5,6 \
-; RUN: | FileCheck %s --check-prefix=TEST2
-; RUN: %p2i -i %s -o /dev/null --args -verbose status -threads=0 \
-; RUN: -test-status=3:9,-7: \
-; RUN: | FileCheck %s --check-prefix=TEST2
-; RUN: %p2i -i %s -o /dev/null --args -verbose status -threads=0 \
-; RUN: -test-status=3:9,-Func7,-Func8 \
-; RUN: | FileCheck %s --check-prefix=TEST2
-; TEST2-NOT: seq=2
-; TEST2: seq=3
-; TEST2: seq=4
-; TEST2: seq=5
-; TEST2: seq=6
-; TEST2-NOT: seq=7
-; TEST2-NOT: seq=8
-; TEST2-NOT: seq=9
-; TEST2-NOT: seq=10
-; TEST2-NOT: seq=11
-; TEST2-NOT: seq=12
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/regalloc_evict_non_overlap.ll b/third_party/subzero/tests_lit/llvm2ice_tests/regalloc_evict_non_overlap.ll
deleted file mode 100644
index 0833a5c..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/regalloc_evict_non_overlap.ll
+++ /dev/null
@@ -1,78 +0,0 @@
-; Bugpoint-reduced example that demonstrated a bug (assertion failure)
-; in register allocation. See
-; https://code.google.com/p/nativeclient/issues/detail?id=3903 .
-;
-; TODO(kschimpf) Find out why lc2i is needed.
-; RUN: %lc2i -i %s --args -O2 --verbose regalloc
-
-define internal void @foo() {
-bb:
- br i1 undef, label %bb13, label %bb14
-
-bb13:
- unreachable
-
-bb14:
- br i1 undef, label %bb50, label %bb16
-
-bb15: ; preds = %bb42, %bb35
- br i1 undef, label %bb50, label %bb16
-
-bb16: ; preds = %bb49, %bb15, %bb14
- %tmp = phi i32 [ undef, %bb14 ], [ %tmp18, %bb49 ], [ undef, %bb15 ]
- br label %bb17
-
-bb17: ; preds = %bb48, %bb16
- %tmp18 = phi i32 [ undef, %bb16 ], [ undef, %bb48 ]
- %tmp19 = add i32 %tmp18, 4
- br i1 undef, label %bb21, label %bb46
-
-bb21: ; preds = %bb27, %bb17
- %tmp22 = phi i32 [ undef, %bb17 ], [ %tmp30, %bb27 ]
- %tmp23 = add i32 undef, -1
- %tmp24 = add i32 undef, undef
- %undef.ptr = inttoptr i32 undef to i32*
- %tmp25 = load i32, i32* %undef.ptr, align 1
- %tmp26 = icmp eq i32 undef, %tmp22
- br i1 %tmp26, label %bb34, label %bb32
-
-bb27: ; preds = %bb42, %bb34
- %tmp28 = icmp sgt i32 %tmp23, 0
- %tmp29 = inttoptr i32 %tmp19 to i32*
- %tmp30 = load i32, i32* %tmp29, align 1
- br i1 %tmp28, label %bb21, label %bb46
-
-bb32: ; preds = %bb21
- %tmp33 = inttoptr i32 %tmp24 to i32*
- store i32 0, i32* %tmp33, align 1
- br label %bb34
-
-bb34: ; preds = %bb32, %bb31
- br i1 undef, label %bb27, label %bb35
-
-bb35: ; preds = %bb34
- %tmp40 = inttoptr i32 %tmp25 to void (i32)*
- call void %tmp40(i32 undef)
- br i1 undef, label %bb42, label %bb15
-
-bb42: ; preds = %bb35
- %tmp43 = inttoptr i32 %tmp to i32*
- %tmp44 = load i32, i32* %tmp43, align 1
- %tmp45 = icmp eq i32 %tmp44, %tmp18
- br i1 %tmp45, label %bb27, label %bb15
-
-bb46: ; preds = %bb27, %bb17
- br i1 undef, label %bb47, label %bb49
-
-bb47: ; preds = %bb46
- br i1 undef, label %bb50, label %bb48
-
-bb48: ; preds = %bb47
- br i1 undef, label %bb50, label %bb17
-
-bb49: ; preds = %bb46
- br i1 undef, label %bb50, label %bb16
-
-bb50: ; preds = %bb49, %bb48, %bb47, %bb15, %bb14
- unreachable
-}
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/reorder-basic-blocks.ll b/third_party/subzero/tests_lit/llvm2ice_tests/reorder-basic-blocks.ll
deleted file mode 100644
index 440b08d..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/reorder-basic-blocks.ll
+++ /dev/null
@@ -1,41 +0,0 @@
-; Trivial smoke test of basic block reordering. Different random seeds should
-; generate different basic block layout.
-; REQUIRES: allow_dump
-
-; RUN: %p2i -i %s --filetype=asm --args -O2 -sz-seed=1 \
-; RUN: -reorder-basic-blocks -threads=0 \
-; RUN: | FileCheck %s --check-prefix=SEED1
-; RUN: %p2i -i %s --filetype=asm --args -O2 -sz-seed=2 \
-; RUN: -reorder-basic-blocks -threads=0 \
-; RUN: | FileCheck %s --check-prefix=SEED2
-
-define internal void @basic_block_reordering(i32 %foo, i32 %bar) {
-entry:
- %r1 = icmp eq i32 %foo, %bar
- br i1 %r1, label %BB1, label %BB2
-BB1:
- %r2 = icmp sgt i32 %foo, %bar
- br i1 %r2, label %BB3, label %BB4
-BB2:
- %r3 = icmp slt i32 %foo, %bar
- br i1 %r3, label %BB3, label %BB4
-BB3:
- ret void
-BB4:
- ret void
-
-
-; SEED1-LABEL: basic_block_reordering:
-; SEED1: .Lbasic_block_reordering$entry:
-; SEED1: .Lbasic_block_reordering$BB1:
-; SEED1: .Lbasic_block_reordering$BB2:
-; SEED1: .Lbasic_block_reordering$BB4:
-; SEED1: .Lbasic_block_reordering$BB3:
-
-; SEED2-LABEL: basic_block_reordering:
-; SEED2: .Lbasic_block_reordering$entry:
-; SEED2: .Lbasic_block_reordering$BB2:
-; SEED2: .Lbasic_block_reordering$BB1:
-; SEED2: .Lbasic_block_reordering$BB4:
-; SEED2: .Lbasic_block_reordering$BB3
-}
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/reorder-functions.ll b/third_party/subzero/tests_lit/llvm2ice_tests/reorder-functions.ll
deleted file mode 100644
index 5351e43..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/reorder-functions.ll
+++ /dev/null
@@ -1,90 +0,0 @@
-; This is a smoke test of function reordering.
-
-; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 \
-; RUN: -sz-seed=1 -reorder-functions \
-; RUN: | FileCheck %s --check-prefix=DEFAULTWINDOWSIZE
-; RUN: %p2i -i %s --filetype=obj --disassemble --args -Om1 \
-; RUN: -sz-seed=1 -reorder-functions \
-; RUN: | FileCheck %s --check-prefix=DEFAULTWINDOWSIZE
-
-
-; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 \
-; RUN: -sz-seed=1 -reorder-functions \
-; RUN: -reorder-functions-window-size=1 \
-; RUN: | FileCheck %s --check-prefix=WINDOWSIZE1
-; RUN: %p2i -i %s --filetype=obj --disassemble --args -Om1 \
-; RUN: -sz-seed=1 -reorder-functions \
-; RUN: -reorder-functions-window-size=1 \
-; RUN: | FileCheck %s --check-prefix=WINDOWSIZE1
-
-
-; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 \
-; RUN: -sz-seed=1 -reorder-functions \
-; RUN: -threads=0 \
-; RUN: | FileCheck %s --check-prefix=SEQUENTIAL
-; RUN: %p2i -i %s --filetype=obj --disassemble --args -Om1 \
-; RUN: -sz-seed=1 -reorder-functions \
-; RUN: -threads=0 \
-; RUN: | FileCheck %s --check-prefix=SEQUENTIAL
-
-
-; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 \
-; RUN: -sz-seed=1 -reorder-functions \
-; RUN: -reorder-functions-window-size=0xffffffff \
-; RUN: | FileCheck %s --check-prefix=WINDOWSIZEMAX
-; RUN: %p2i -i %s --filetype=obj --disassemble --args -Om1 \
-; RUN: -sz-seed=1 -reorder-functions \
-; RUN: -reorder-functions-window-size=0xffffffff \
-; RUN: | FileCheck %s --check-prefix=WINDOWSIZEMAX
-
-define internal void @func1() {
- ret void
-}
-
-define internal void @func2() {
- ret void
-}
-
-define internal void @func3() {
- ret void
-}
-
-define internal void @func4() {
- ret void
-}
-
-define internal void @func5() {
- ret void
-}
-
-define internal void @func6() {
- ret void
-}
-
-; DEFAULTWINDOWSIZE-LABEL: func1
-; DEFAULTWINDOWSIZE-LABEL: func4
-; DEFAULTWINDOWSIZE-LABEL: func5
-; DEFAULTWINDOWSIZE-LABEL: func2
-; DEFAULTWINDOWSIZE-LABEL: func6
-; DEFAULTWINDOWSIZE-LABEL: func3
-
-; WINDOWSIZE1-LABEL: func1
-; WINDOWSIZE1-LABEL: func2
-; WINDOWSIZE1-LABEL: func3
-; WINDOWSIZE1-LABEL: func4
-; WINDOWSIZE1-LABEL: func5
-; WINDOWSIZE1-LABEL: func6
-
-; SEQUENTIAL-LABEL: func1
-; SEQUENTIAL-LABEL: func2
-; SEQUENTIAL-LABEL: func3
-; SEQUENTIAL-LABEL: func4
-; SEQUENTIAL-LABEL: func5
-; SEQUENTIAL-LABEL: func6
-
-; WINDOWSIZEMAX-LABEL: func1
-; WINDOWSIZEMAX-LABEL: func4
-; WINDOWSIZEMAX-LABEL: func5
-; WINDOWSIZEMAX-LABEL: func2
-; WINDOWSIZEMAX-LABEL: func6
-; WINDOWSIZEMAX-LABEL: func3
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/reorder-global-variables.ll b/third_party/subzero/tests_lit/llvm2ice_tests/reorder-global-variables.ll
deleted file mode 100644
index a1239b6..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/reorder-global-variables.ll
+++ /dev/null
@@ -1,71 +0,0 @@
-; Test of global variable reordering.
-
-; REQUIRES: allow_dump
-
-; Test x8632 asm output
-; RUN: %if --need=target_X8632 --command %p2i --filetype=asm --target x8632 \
-; RUN: -i %s --assemble --disassemble --dis-flags=-rD \
-; RUN: --args -sz-seed=1 -reorder-global-variables -O2 \
-; RUN: | %if --need=target_X8632 --command FileCheck %s
-; RUN: %if --need=target_X8632 --command %p2i --filetype=asm --target x8632 \
-; RUN: -i %s --assemble --disassemble --dis-flags=-rD \
-; RUN: --args -sz-seed=1 -reorder-global-variables -Om1 \
-; RUN: | %if --need=target_X8632 --command FileCheck %s
-
-; Test x8632 elf output
-; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --target x8632 \
-; RUN: -i %s --disassemble --dis-flags=-rD \
-; RUN: --args -sz-seed=1 -reorder-global-variables -O2 \
-; RUN: | %if --need=target_X8632 --command FileCheck %s
-; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --target x8632 \
-; RUN: -i %s --disassemble --dis-flags=-rD \
-; RUN: --args -sz-seed=1 -reorder-global-variables -Om1 \
-; RUN: | %if --need=target_X8632 --command FileCheck %s
-
-; Test arm output
-; RUN: %if --need=target_ARM32 --command %p2i --filetype=obj --target arm32 \
-; RUN: -i %s --disassemble --dis-flags=-rD \
-; RUN: --args -sz-seed=1 -reorder-global-variables \
-; RUN: -O2 \
-; RUN: | %if --need=target_ARM32 --command FileCheck %s
-; RUN: %if --need=target_ARM32 --command %p2i --filetype=obj --target arm32 \
-; RUN: -i %s --disassemble --dis-flags=-rD \
-; RUN: --args -sz-seed=1 -reorder-global-variables \
-; RUN: -Om1 \
-; RUN: | %if --need=target_ARM32 --command FileCheck %s
-
-; RUN: %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command %p2i --filetype=asm --assemble --disassemble --target \
-; RUN: mips32 -i %s --dis-flags=-rD --args -O2 -sz-seed=1 \
-; RUN: -reorder-global-variables \
-; RUN: | %if --need=target_MIPS32 --need=allow_dump --command FileCheck %s
-
-@PrimitiveInit = internal global [4 x i8] c"\1B\00\00\00", align 4
-
-@PrimitiveInitConst = internal constant [4 x i8] c"\0D\00\00\00", align 4
-
-@ArrayInit = internal global [20 x i8] c"\0A\00\00\00\14\00\00\00\1E\00\00\00(\00\00\002\00\00\00", align 4
-
-@ArrayInitPartial = internal global [40 x i8] c"<\00\00\00F\00\00\00P\00\00\00Z\00\00\00d\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00", align 4
-
-@PrimitiveInitStatic = internal global [4 x i8] zeroinitializer, align 4
-
-@PrimitiveUninit = internal global [4 x i8] zeroinitializer, align 4
-
-@ArrayUninit = internal global [20 x i8] zeroinitializer, align 4
-
-@ArrayUninitConstDouble = internal constant [200 x i8] zeroinitializer, align 8
-
-@ArrayUninitConstInt = internal constant [20 x i8] zeroinitializer, align 4
-
-; Make sure the shuffled order is correct.
-
-; CHECK-LABEL: ArrayInit
-; CHECK-LABEL: PrimitiveInit
-; CHECK-LABEL: ArrayInitPartial
-; CHECK-LABEL: PrimitiveUninit
-; CHECK-LABEL: ArrayUninit
-; CHECK-LABEL: PrimitiveInitStatic
-; CHECK-LABEL: ArrayUninitConstDouble
-; CHECK-LABEL: ArrayUninitConstInt
-; CHECK-LABEL: PrimitiveInitConst
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/reorder-pooled-constants.ll b/third_party/subzero/tests_lit/llvm2ice_tests/reorder-pooled-constants.ll
deleted file mode 100644
index 76bfc0f..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/reorder-pooled-constants.ll
+++ /dev/null
@@ -1,548 +0,0 @@
-; This is a smoke test for reordering pooled constants.
-; This option is only implemented for target X8632 for now.
-
-; RUN: %p2i --assemble --disassemble --filetype=obj --dis-flags=-s \
-; RUN: --target x8632 -i %s --args -sz-seed=1 -O2 -reorder-pooled-constants \
-; RUN: -allow-externally-defined-symbols | FileCheck %s --check-prefix=X86
-
-; RUN: %p2i --assemble --disassemble --filetype=obj --dis-flags=-s \
-; RUN: --target x8632 -i %s --args -sz-seed=1 -Om1 -reorder-pooled-constants \
-; RUN: -allow-externally-defined-symbols | FileCheck %s --check-prefix=X86
-
-@__init_array_start = internal constant [0 x i8] zeroinitializer, align 4
-@__fini_array_start = internal constant [0 x i8] zeroinitializer, align 4
-@__tls_template_start = internal constant [0 x i8] zeroinitializer, align 8
-@__tls_template_alignment = internal constant [4 x i8] c"\01\00\00\00", align 4
-
-define internal float @FpLookup1(i32 %Arg) {
-entry:
- switch i32 %Arg, label %return [
- i32 0, label %sw.bb
- i32 1, label %sw.bb1
- i32 2, label %sw.bb4
- i32 3, label %sw.bb7
- i32 -1, label %sw.bb10
- i32 -2, label %sw.bb14
- i32 -3, label %sw.bb19
- i32 10, label %sw.bb24
- i32 -10, label %sw.bb27
- i32 100, label %sw.bb30
- i32 101, label %sw.bb33
- i32 102, label %sw.bb36
- i32 103, label %sw.bb39
- i32 -101, label %sw.bb42
- i32 -102, label %sw.bb47
- i32 -103, label %sw.bb52
- i32 110, label %sw.bb57
- i32 -110, label %sw.bb60
- ]
-
-sw.bb: ; preds = %entry
- %call = call float @Dummy(i32 0)
- %add = fadd float %call, 1.000000e+00
- br label %return
-
-sw.bb1: ; preds = %entry
- %call2 = call float @Dummy(i32 1)
- %add3 = fadd float %call2, 2.000000e+00
- br label %return
-
-sw.bb4: ; preds = %entry
- %call5 = call float @Dummy(i32 2)
- %add6 = fadd float %call5, 4.000000e+00
- br label %return
-
-sw.bb7: ; preds = %entry
- %call8 = call float @Dummy(i32 3)
- %add9 = fadd float %call8, 8.000000e+00
- br label %return
-
-sw.bb10: ; preds = %entry
- %call11 = call float @Dummy(i32 -1)
- %conv13 = fadd float %call11, 5.000000e-01
- br label %return
-
-sw.bb14: ; preds = %entry
- %call15 = call float @Dummy(i32 -2)
- %conv16 = fpext float %call15 to double
- %add17 = fadd double %conv16, 0x3FD5555555555555
- %conv18 = fptrunc double %add17 to float
- br label %return
-
-sw.bb19: ; preds = %entry
- %call20 = call float @Dummy(i32 -3)
- %conv23 = fadd float %call20, 2.500000e-01
- br label %return
-
-sw.bb24: ; preds = %entry
- %call25 = call float @Dummy(i32 10)
- %add26 = fadd float %call25, 0x7FF8000000000000
- br label %return
-
-sw.bb27: ; preds = %entry
- %call28 = call float @Dummy(i32 -10)
- %add29 = fadd float %call28, 0xFFF8000000000000
- br label %return
-
-sw.bb30: ; preds = %entry
- %call31 = call float @Dummy(i32 100)
- %add32 = fadd float %call31, 1.000000e+00
- br label %return
-
-sw.bb33: ; preds = %entry
- %call34 = call float @Dummy(i32 101)
- %add35 = fadd float %call34, 2.000000e+00
- br label %return
-
-sw.bb36: ; preds = %entry
- %call37 = call float @Dummy(i32 102)
- %add38 = fadd float %call37, 4.000000e+00
- br label %return
-
-sw.bb39: ; preds = %entry
- %call40 = call float @Dummy(i32 103)
- %add41 = fadd float %call40, 8.000000e+00
- br label %return
-
-sw.bb42: ; preds = %entry
- %call43 = call float @Dummy(i32 -101)
- %conv46 = fadd float %call43, 5.000000e-01
- br label %return
-
-sw.bb47: ; preds = %entry
- %call48 = call float @Dummy(i32 -102)
- %conv49 = fpext float %call48 to double
- %add50 = fadd double %conv49, 0x3FD5555555555555
- %conv51 = fptrunc double %add50 to float
- br label %return
-
-sw.bb52: ; preds = %entry
- %call53 = call float @Dummy(i32 -103)
- %conv56 = fadd float %call53, 2.500000e-01
- br label %return
-
-sw.bb57: ; preds = %entry
- %call58 = call float @Dummy(i32 110)
- %add59 = fadd float %call58, 0x7FF8000000000000
- br label %return
-
-sw.bb60: ; preds = %entry
- %call61 = call float @Dummy(i32 -110)
- %add62 = fadd float %call61, 0xFFF8000000000000
- br label %return
-
-return: ; preds = %entry, %sw.bb60, %sw.bb57, %sw.bb52, %sw.bb47, %sw.bb42, %sw.bb39, %sw.bb36, %sw.bb33, %sw.bb30, %sw.bb27, %sw.bb24, %sw.bb19, %sw.bb14, %sw.bb10, %sw.bb7, %sw.bb4, %sw.bb1, %sw.bb
- %retval.0 = phi float [ %add62, %sw.bb60 ], [ %add59, %sw.bb57 ], [ %conv56, %sw.bb52 ], [ %conv51, %sw.bb47 ], [ %conv46, %sw.bb42 ], [ %add41, %sw.bb39 ], [ %add38, %sw.bb36 ], [ %add35, %sw.bb33 ], [ %add32, %sw.bb30 ], [ %add29, %sw.bb27 ], [ %add26, %sw.bb24 ], [ %conv23, %sw.bb19 ], [ %conv18, %sw.bb14 ], [ %conv13, %sw.bb10 ], [ %add9, %sw.bb7 ], [ %add6, %sw.bb4 ], [ %add3, %sw.bb1 ], [ %add, %sw.bb ], [ 0.000000e+00, %entry ]
- ret float %retval.0
-}
-
-declare float @Dummy(i32)
-
-define internal float @FpLookup2(i32 %Arg) {
-entry:
- switch i32 %Arg, label %return [
- i32 0, label %sw.bb
- i32 1, label %sw.bb1
- i32 2, label %sw.bb4
- i32 3, label %sw.bb7
- i32 -1, label %sw.bb10
- i32 -2, label %sw.bb14
- i32 -3, label %sw.bb19
- i32 10, label %sw.bb24
- i32 -10, label %sw.bb27
- i32 100, label %sw.bb30
- i32 101, label %sw.bb33
- i32 102, label %sw.bb36
- i32 103, label %sw.bb39
- i32 -101, label %sw.bb42
- i32 -102, label %sw.bb47
- i32 -103, label %sw.bb52
- i32 110, label %sw.bb57
- i32 -110, label %sw.bb60
- ]
-
-sw.bb: ; preds = %entry
- %call = call float @Dummy(i32 0)
- %add = fadd float %call, 1.000000e+00
- br label %return
-
-sw.bb1: ; preds = %entry
- %call2 = call float @Dummy(i32 1)
- %add3 = fadd float %call2, 2.000000e+00
- br label %return
-
-sw.bb4: ; preds = %entry
- %call5 = call float @Dummy(i32 2)
- %add6 = fadd float %call5, 4.000000e+00
- br label %return
-
-sw.bb7: ; preds = %entry
- %call8 = call float @Dummy(i32 3)
- %add9 = fadd float %call8, 8.000000e+00
- br label %return
-
-sw.bb10: ; preds = %entry
- %call11 = call float @Dummy(i32 -1)
- %conv13 = fadd float %call11, 5.000000e-01
- br label %return
-
-sw.bb14: ; preds = %entry
- %call15 = call float @Dummy(i32 -2)
- %conv16 = fpext float %call15 to double
- %add17 = fadd double %conv16, 0x3FD5555555555555
- %conv18 = fptrunc double %add17 to float
- br label %return
-
-sw.bb19: ; preds = %entry
- %call20 = call float @Dummy(i32 -3)
- %conv23 = fadd float %call20, 2.500000e-01
- br label %return
-
-sw.bb24: ; preds = %entry
- %call25 = call float @Dummy(i32 10)
- %add26 = fadd float %call25, 0x7FF8000000000000
- br label %return
-
-sw.bb27: ; preds = %entry
- %call28 = call float @Dummy(i32 -10)
- %add29 = fadd float %call28, 0xFFF8000000000000
- br label %return
-
-sw.bb30: ; preds = %entry
- %call31 = call float @Dummy(i32 100)
- %add32 = fadd float %call31, 1.000000e+00
- br label %return
-
-sw.bb33: ; preds = %entry
- %call34 = call float @Dummy(i32 101)
- %add35 = fadd float %call34, 2.000000e+00
- br label %return
-
-sw.bb36: ; preds = %entry
- %call37 = call float @Dummy(i32 102)
- %add38 = fadd float %call37, 4.000000e+00
- br label %return
-
-sw.bb39: ; preds = %entry
- %call40 = call float @Dummy(i32 103)
- %add41 = fadd float %call40, 8.000000e+00
- br label %return
-
-sw.bb42: ; preds = %entry
- %call43 = call float @Dummy(i32 -101)
- %conv46 = fadd float %call43, 5.000000e-01
- br label %return
-
-sw.bb47: ; preds = %entry
- %call48 = call float @Dummy(i32 -102)
- %conv49 = fpext float %call48 to double
- %add50 = fadd double %conv49, 0x3FD5555555555555
- %conv51 = fptrunc double %add50 to float
- br label %return
-
-sw.bb52: ; preds = %entry
- %call53 = call float @Dummy(i32 -103)
- %conv56 = fadd float %call53, 2.500000e-01
- br label %return
-
-sw.bb57: ; preds = %entry
- %call58 = call float @Dummy(i32 110)
- %add59 = fadd float %call58, 0x7FF8000000000000
- br label %return
-
-sw.bb60: ; preds = %entry
- %call61 = call float @Dummy(i32 -110)
- %add62 = fadd float %call61, 0xFFF8000000000000
- br label %return
-
-return: ; preds = %entry, %sw.bb60, %sw.bb57, %sw.bb52, %sw.bb47, %sw.bb42, %sw.bb39, %sw.bb36, %sw.bb33, %sw.bb30, %sw.bb27, %sw.bb24, %sw.bb19, %sw.bb14, %sw.bb10, %sw.bb7, %sw.bb4, %sw.bb1, %sw.bb
- %retval.0 = phi float [ %add62, %sw.bb60 ], [ %add59, %sw.bb57 ], [ %conv56, %sw.bb52 ], [ %conv51, %sw.bb47 ], [ %conv46, %sw.bb42 ], [ %add41, %sw.bb39 ], [ %add38, %sw.bb36 ], [ %add35, %sw.bb33 ], [ %add32, %sw.bb30 ], [ %add29, %sw.bb27 ], [ %add26, %sw.bb24 ], [ %conv23, %sw.bb19 ], [ %conv18, %sw.bb14 ], [ %conv13, %sw.bb10 ], [ %add9, %sw.bb7 ], [ %add6, %sw.bb4 ], [ %add3, %sw.bb1 ], [ %add, %sw.bb ], [ 0.000000e+00, %entry ]
- ret float %retval.0
-}
-
-define internal double @FpLookup3(i32 %Arg) {
-entry:
- switch i32 %Arg, label %return [
- i32 0, label %sw.bb
- i32 1, label %sw.bb1
- i32 2, label %sw.bb5
- i32 3, label %sw.bb9
- i32 -1, label %sw.bb13
- i32 -2, label %sw.bb17
- i32 -3, label %sw.bb21
- i32 10, label %sw.bb25
- i32 -10, label %sw.bb29
- i32 100, label %sw.bb33
- i32 101, label %sw.bb37
- i32 102, label %sw.bb41
- i32 103, label %sw.bb45
- i32 -101, label %sw.bb49
- i32 -102, label %sw.bb53
- i32 -103, label %sw.bb57
- i32 110, label %sw.bb61
- i32 -110, label %sw.bb65
- ]
-
-sw.bb: ; preds = %entry
- %call = call float @Dummy(i32 0)
- %add = fadd float %call, 1.000000e+00
- %conv = fpext float %add to double
- br label %return
-
-sw.bb1: ; preds = %entry
- %call2 = call float @Dummy(i32 1)
- %add3 = fadd float %call2, 2.000000e+00
- %conv4 = fpext float %add3 to double
- br label %return
-
-sw.bb5: ; preds = %entry
- %call6 = call float @Dummy(i32 2)
- %add7 = fadd float %call6, 4.000000e+00
- %conv8 = fpext float %add7 to double
- br label %return
-
-sw.bb9: ; preds = %entry
- %call10 = call float @Dummy(i32 3)
- %add11 = fadd float %call10, 8.000000e+00
- %conv12 = fpext float %add11 to double
- br label %return
-
-sw.bb13: ; preds = %entry
- %call14 = call float @Dummy(i32 -1)
- %conv15 = fpext float %call14 to double
- %add16 = fadd double %conv15, 5.000000e-01
- br label %return
-
-sw.bb17: ; preds = %entry
- %call18 = call float @Dummy(i32 -2)
- %conv19 = fpext float %call18 to double
- %add20 = fadd double %conv19, 0x3FD5555555555555
- br label %return
-
-sw.bb21: ; preds = %entry
- %call22 = call float @Dummy(i32 -3)
- %conv23 = fpext float %call22 to double
- %add24 = fadd double %conv23, 2.500000e-01
- br label %return
-
-sw.bb25: ; preds = %entry
- %call26 = call float @Dummy(i32 10)
- %conv27 = fpext float %call26 to double
- %add28 = fadd double %conv27, 0x7FF8000000000000
- br label %return
-
-sw.bb29: ; preds = %entry
- %call30 = call float @Dummy(i32 -10)
- %conv31 = fpext float %call30 to double
- %add32 = fadd double %conv31, 0xFFF8000000000000
- br label %return
-
-sw.bb33: ; preds = %entry
- %call34 = call float @Dummy(i32 100)
- %add35 = fadd float %call34, 1.000000e+00
- %conv36 = fpext float %add35 to double
- br label %return
-
-sw.bb37: ; preds = %entry
- %call38 = call float @Dummy(i32 101)
- %add39 = fadd float %call38, 2.000000e+00
- %conv40 = fpext float %add39 to double
- br label %return
-
-sw.bb41: ; preds = %entry
- %call42 = call float @Dummy(i32 102)
- %add43 = fadd float %call42, 4.000000e+00
- %conv44 = fpext float %add43 to double
- br label %return
-
-sw.bb45: ; preds = %entry
- %call46 = call float @Dummy(i32 103)
- %add47 = fadd float %call46, 8.000000e+00
- %conv48 = fpext float %add47 to double
- br label %return
-
-sw.bb49: ; preds = %entry
- %call50 = call float @Dummy(i32 -101)
- %conv51 = fpext float %call50 to double
- %add52 = fadd double %conv51, 5.000000e-01
- br label %return
-
-sw.bb53: ; preds = %entry
- %call54 = call float @Dummy(i32 -102)
- %conv55 = fpext float %call54 to double
- %add56 = fadd double %conv55, 0x3FD5555555555555
- br label %return
-
-sw.bb57: ; preds = %entry
- %call58 = call float @Dummy(i32 -103)
- %conv59 = fpext float %call58 to double
- %add60 = fadd double %conv59, 2.500000e-01
- br label %return
-
-sw.bb61: ; preds = %entry
- %call62 = call float @Dummy(i32 110)
- %conv63 = fpext float %call62 to double
- %add64 = fadd double %conv63, 0x7FF8000000000000
- br label %return
-
-sw.bb65: ; preds = %entry
- %call66 = call float @Dummy(i32 -110)
- %conv67 = fpext float %call66 to double
- %add68 = fadd double %conv67, 0xFFF8000000000000
- br label %return
-
-return: ; preds = %entry, %sw.bb65, %sw.bb61, %sw.bb57, %sw.bb53, %sw.bb49, %sw.bb45, %sw.bb41, %sw.bb37, %sw.bb33, %sw.bb29, %sw.bb25, %sw.bb21, %sw.bb17, %sw.bb13, %sw.bb9, %sw.bb5, %sw.bb1, %sw.bb
- %retval.0 = phi double [ %add68, %sw.bb65 ], [ %add64, %sw.bb61 ], [ %add60, %sw.bb57 ], [ %add56, %sw.bb53 ], [ %add52, %sw.bb49 ], [ %conv48, %sw.bb45 ], [ %conv44, %sw.bb41 ], [ %conv40, %sw.bb37 ], [ %conv36, %sw.bb33 ], [ %add32, %sw.bb29 ], [ %add28, %sw.bb25 ], [ %add24, %sw.bb21 ], [ %add20, %sw.bb17 ], [ %add16, %sw.bb13 ], [ %conv12, %sw.bb9 ], [ %conv8, %sw.bb5 ], [ %conv4, %sw.bb1 ], [ %conv, %sw.bb ], [ 0.000000e+00, %entry ]
- ret double %retval.0
-}
-
-define internal double @FpLookup4(i32 %Arg) {
-entry:
- switch i32 %Arg, label %return [
- i32 0, label %sw.bb
- i32 1, label %sw.bb1
- i32 2, label %sw.bb5
- i32 3, label %sw.bb9
- i32 -1, label %sw.bb13
- i32 -2, label %sw.bb17
- i32 -3, label %sw.bb21
- i32 10, label %sw.bb25
- i32 -10, label %sw.bb29
- i32 100, label %sw.bb33
- i32 101, label %sw.bb37
- i32 102, label %sw.bb41
- i32 103, label %sw.bb45
- i32 -101, label %sw.bb49
- i32 -102, label %sw.bb53
- i32 -103, label %sw.bb57
- i32 110, label %sw.bb61
- i32 -110, label %sw.bb65
- ]
-
-sw.bb: ; preds = %entry
- %call = call float @Dummy(i32 0)
- %add = fadd float %call, 1.000000e+00
- %conv = fpext float %add to double
- br label %return
-
-sw.bb1: ; preds = %entry
- %call2 = call float @Dummy(i32 1)
- %add3 = fadd float %call2, 2.000000e+00
- %conv4 = fpext float %add3 to double
- br label %return
-
-sw.bb5: ; preds = %entry
- %call6 = call float @Dummy(i32 2)
- %add7 = fadd float %call6, 4.000000e+00
- %conv8 = fpext float %add7 to double
- br label %return
-
-sw.bb9: ; preds = %entry
- %call10 = call float @Dummy(i32 3)
- %add11 = fadd float %call10, 8.000000e+00
- %conv12 = fpext float %add11 to double
- br label %return
-
-sw.bb13: ; preds = %entry
- %call14 = call float @Dummy(i32 -1)
- %conv15 = fpext float %call14 to double
- %add16 = fadd double %conv15, 5.000000e-01
- br label %return
-
-sw.bb17: ; preds = %entry
- %call18 = call float @Dummy(i32 -2)
- %conv19 = fpext float %call18 to double
- %add20 = fadd double %conv19, 0x3FD5555555555555
- br label %return
-
-sw.bb21: ; preds = %entry
- %call22 = call float @Dummy(i32 -3)
- %conv23 = fpext float %call22 to double
- %add24 = fadd double %conv23, 2.500000e-01
- br label %return
-
-sw.bb25: ; preds = %entry
- %call26 = call float @Dummy(i32 10)
- %conv27 = fpext float %call26 to double
- %add28 = fadd double %conv27, 0x7FF8000000000000
- br label %return
-
-sw.bb29: ; preds = %entry
- %call30 = call float @Dummy(i32 -10)
- %conv31 = fpext float %call30 to double
- %add32 = fadd double %conv31, 0xFFF8000000000000
- br label %return
-
-sw.bb33: ; preds = %entry
- %call34 = call float @Dummy(i32 100)
- %add35 = fadd float %call34, 1.000000e+00
- %conv36 = fpext float %add35 to double
- br label %return
-
-sw.bb37: ; preds = %entry
- %call38 = call float @Dummy(i32 101)
- %add39 = fadd float %call38, 2.000000e+00
- %conv40 = fpext float %add39 to double
- br label %return
-
-sw.bb41: ; preds = %entry
- %call42 = call float @Dummy(i32 102)
- %add43 = fadd float %call42, 4.000000e+00
- %conv44 = fpext float %add43 to double
- br label %return
-
-sw.bb45: ; preds = %entry
- %call46 = call float @Dummy(i32 103)
- %add47 = fadd float %call46, 8.000000e+00
- %conv48 = fpext float %add47 to double
- br label %return
-
-sw.bb49: ; preds = %entry
- %call50 = call float @Dummy(i32 -101)
- %conv51 = fpext float %call50 to double
- %add52 = fadd double %conv51, 5.000000e-01
- br label %return
-
-sw.bb53: ; preds = %entry
- %call54 = call float @Dummy(i32 -102)
- %conv55 = fpext float %call54 to double
- %add56 = fadd double %conv55, 0x3FD5555555555555
- br label %return
-
-sw.bb57: ; preds = %entry
- %call58 = call float @Dummy(i32 -103)
- %conv59 = fpext float %call58 to double
- %add60 = fadd double %conv59, 2.500000e-01
- br label %return
-
-sw.bb61: ; preds = %entry
- %call62 = call float @Dummy(i32 110)
- %conv63 = fpext float %call62 to double
- %add64 = fadd double %conv63, 0x7FF8000000000000
- br label %return
-
-sw.bb65: ; preds = %entry
- %call66 = call float @Dummy(i32 -110)
- %conv67 = fpext float %call66 to double
- %add68 = fadd double %conv67, 0xFFF8000000000000
- br label %return
-
-return: ; preds = %entry, %sw.bb65, %sw.bb61, %sw.bb57, %sw.bb53, %sw.bb49, %sw.bb45, %sw.bb41, %sw.bb37, %sw.bb33, %sw.bb29, %sw.bb25, %sw.bb21, %sw.bb17, %sw.bb13, %sw.bb9, %sw.bb5, %sw.bb1, %sw.bb
- %retval.0 = phi double [ %add68, %sw.bb65 ], [ %add64, %sw.bb61 ], [ %add60, %sw.bb57 ], [ %add56, %sw.bb53 ], [ %add52, %sw.bb49 ], [ %conv48, %sw.bb45 ], [ %conv44, %sw.bb41 ], [ %conv40, %sw.bb37 ], [ %conv36, %sw.bb33 ], [ %add32, %sw.bb29 ], [ %add28, %sw.bb25 ], [ %add24, %sw.bb21 ], [ %add20, %sw.bb17 ], [ %add16, %sw.bb13 ], [ %conv12, %sw.bb9 ], [ %conv8, %sw.bb5 ], [ %conv4, %sw.bb1 ], [ %conv, %sw.bb ], [ 0.000000e+00, %entry ]
- ret double %retval.0
-}
-
-; Make sure the constants in pools are shuffled.
-
-; Check for float pool
-; X86-LABEL: .rodata.cst4
-; X86: 00000041 0000c0ff 0000803f 00008040
-; X86: 0000c07f 0000003f 0000803e 00000040
-
-; Check for double pool
-; X86-LABEL: .rodata.cst8
-; X86: 00000000 0000f8ff 00000000 0000f87f
-; X86: 00000000 0000e03f 55555555 5555d53f
-; X86: 00000000 0000d03f
-
-; X86-LABEL: .text
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/return_immediates.ll b/third_party/subzero/tests_lit/llvm2ice_tests/return_immediates.ll
deleted file mode 100644
index f551506..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/return_immediates.ll
+++ /dev/null
@@ -1,324 +0,0 @@
-; Simple test that returns various immediates. For fixed-width instruction
-; sets, some immediates are more complicated than others.
-; For x86-32, it shouldn't be a problem.
-
-; RUN: %p2i --filetype=obj --disassemble -i %s --args -O2 \
-; RUN: -allow-externally-defined-symbols | FileCheck %s
-
-; RUN: %if --need=target_ARM32 \
-; RUN: --command %p2i --filetype=obj \
-; RUN: --disassemble --target arm32 -i %s --args -O2 \
-; RUN: | %if --need=target_ARM32 \
-; RUN: --command FileCheck --check-prefix ARM32 %s
-
-; TODO: Switch to --filetype=obj when possible.
-; RUN: %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command %p2i --filetype=asm --assemble \
-; RUN: --disassemble --target mips32 -i %s --args -O2 \
-; RUN: | %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command FileCheck --check-prefix MIPS32 %s
-
-; Test 8-bits of all ones rotated right by various amounts (even vs odd).
-; ARM has a shifter that allows encoding 8-bits rotated right by even amounts.
-; The first few "rotate right" test cases are expressed as shift-left.
-
-define internal i32 @ret_8bits_shift_left0() {
- ret i32 255
-}
-; CHECK-LABEL: ret_8bits_shift_left0
-; CHECK-NEXT: mov eax,0xff
-; ARM32-LABEL: ret_8bits_shift_left0
-; ARM32-NEXT: mov r0, #255
-; MIPS32-LABEL: ret_8bits_shift_left0
-; MIPS32-NEXT: li v0,255
-
-define internal i32 @ret_8bits_shift_left1() {
- ret i32 510
-}
-; CHECK-LABEL: ret_8bits_shift_left1
-; CHECK-NEXT: mov eax,0x1fe
-; ARM32-LABEL: ret_8bits_shift_left1
-; ARM32-NEXT: movw r0, #510
-; MIPS32-LABEL: ret_8bits_shift_left1
-; MIPS32-NEXT: li v0,510
-
-define internal i32 @ret_8bits_shift_left2() {
- ret i32 1020
-}
-; CHECK-LABEL: ret_8bits_shift_left2
-; CHECK-NEXT: mov eax,0x3fc
-; ARM32-LABEL: ret_8bits_shift_left2
-; ARM32-NEXT: mov r0, #1020
-; MIPS32-LABEL: ret_8bits_shift_left2
-; MIPS32-NEXT: li v0,1020
-
-define internal i32 @ret_8bits_shift_left4() {
- ret i32 4080
-}
-; CHECK-LABEL: ret_8bits_shift_left4
-; CHECK-NEXT: mov eax,0xff0
-; ARM32-LABEL: ret_8bits_shift_left4
-; ARM32-NEXT: mov r0, #4080
-; MIPS32-LABEL: ret_8bits_shift_left4
-; MIPS32-NEXT: li v0,4080
-
-define internal i32 @ret_8bits_shift_left14() {
- ret i32 4177920
-}
-; CHECK-LABEL: ret_8bits_shift_left14
-; CHECK-NEXT: mov eax,0x3fc000
-; ARM32-LABEL: ret_8bits_shift_left14
-; ARM32-NEXT: mov r0, #4177920
-; MIPS32-LABEL: ret_8bits_shift_left14
-; MIPS32-NEXT: lui v0,0x3f
-; MIPS32-NEXT: ori v0,v0,0xc000
-
-define internal i32 @ret_8bits_shift_left15() {
- ret i32 8355840
-}
-; CHECK-LABEL: ret_8bits_shift_left15
-; CHECK-NEXT: mov eax,0x7f8000
-; ARM32-LABEL: ret_8bits_shift_left15
-; ARM32-NEXT: movw r0, #32768
-; ARM32-NEXT: movt r0, #127
-; MIPS32-LABEL: ret_8bits_shift_left15
-; MIPS32-NEXT: lui v0,0x7f
-; MIPS32-NEXT: ori v0,v0,0x8000
-
-; Shift 8 bits left by 24 to the i32 limit. This is also ror by 8 bits.
-
-define internal i32 @ret_8bits_shift_left24() {
- ret i32 4278190080
-}
-; CHECK-LABEL: ret_8bits_shift_left24
-; CHECK-NEXT: mov eax,0xff000000
-; ARM32-LABEL: ret_8bits_shift_left24
-; ARM32-NEXT: mov r0, #-16777216
-; ARM32-NEXT: bx lr
-; MIPS32-LABEL: ret_8bits_shift_left24
-; MIPS32-NEXT: lui v0,0xff00
-
-; The next few cases wrap around and actually demonstrate the rotation.
-
-define internal i32 @ret_8bits_ror7() {
- ret i32 4261412865
-}
-; CHECK-LABEL: ret_8bits_ror7
-; CHECK-NEXT: mov eax,0xfe000001
-; ARM32-LABEL: ret_8bits_ror7
-; ARM32-NEXT: movw r0, #1
-; ARM32-NEXT: movt r0, #65024
-; MIPS32-LABEL: ret_8bits_ror7
-; MIPS32-NEXT: lui v0,0xfe00
-; MIPS32-NEXT: ori v0,v0,0x1
-
-define internal i32 @ret_8bits_ror6() {
- ret i32 4227858435
-}
-; CHECK-LABEL: ret_8bits_ror6
-; CHECK-NEXT: mov eax,0xfc000003
-; ARM32-LABEL: ret_8bits_ror6
-; ARM32-NEXT: mov r0, #-67108861
-; ARM32-NEXT: bx lr
-; MIPS32-LABEL: ret_8bits_ror6
-; MIPS32-NEXT: lui v0,0xfc00
-; MIPS32-NEXT: ori v0,v0,0x3
-
-define internal i32 @ret_8bits_ror5() {
- ret i32 4160749575
-}
-; CHECK-LABEL: ret_8bits_ror5
-; CHECK-NEXT: mov eax,0xf8000007
-; ARM32-LABEL: ret_8bits_ror5
-; ARM32-NEXT: movw r0, #7
-; ARM32-NEXT: movt r0, #63488
-; MIPS32-LABEL: ret_8bits_ror5
-; MIPS32-NEXT: lui v0,0xf800
-; MIPS32-NEXT: ori v0,v0,0x7
-
-define internal i32 @ret_8bits_ror4() {
- ret i32 4026531855
-}
-; CHECK-LABEL: ret_8bits_ror4
-; CHECK-NEXT: mov eax,0xf000000f
-; ARM32-LABEL: ret_8bits_ror4
-; ARM32-NEXT: mov r0, #-268435441
-; ARM32-NEXT: bx lr
-; MIPS32-LABEL: ret_8bits_ror4
-; MIPS32-NEXT: lui v0,0xf000
-; MIPS32-NEXT: ori v0,v0,0xf
-
-define internal i32 @ret_8bits_ror3() {
- ret i32 3758096415
-}
-; CHECK-LABEL: ret_8bits_ror3
-; CHECK-NEXT: mov eax,0xe000001f
-; ARM32-LABEL: ret_8bits_ror3
-; ARM32-NEXT: movw r0, #31
-; ARM32-NEXT: movt r0, #57344
-; MIPS32-LABEL: ret_8bits_ror3
-; MIPS32-NEXT: lui v0,0xe000
-; MIPS32-NEXT: ori v0,v0,0x1f
-
-
-define internal i32 @ret_8bits_ror2() {
- ret i32 3221225535
-}
-; CHECK-LABEL: ret_8bits_ror2
-; CHECK-NEXT: mov eax,0xc000003f
-; ARM32-LABEL: ret_8bits_ror2
-; ARM32-NEXT: mov r0, #-1073741761
-; ARM32-NEXT: bx lr
-; MIPS32-LABEL: ret_8bits_ror2
-; MIPS32-NEXT: lui v0,0xc000
-; MIPS32-NEXT: ori v0,v0,0x3f
-
-define internal i32 @ret_8bits_ror1() {
- ret i32 2147483775
-}
-; CHECK-LABEL: ret_8bits_ror1
-; CHECK-NEXT: mov eax,0x8000007f
-; ARM32-LABEL: ret_8bits_ror1
-; ARM32-NEXT: movw r0, #127
-; ARM32-NEXT: movt r0, #32768
-; MIPS32-LABEL: ret_8bits_ror1
-; MIPS32-NEXT: lui v0,0x8000
-; MIPS32-NEXT: ori v0,v0,0x7f
-
-; Some architectures can handle 16-bits at a time efficiently,
-; so also test those.
-
-define internal i32 @ret_16bits_lower() {
- ret i32 65535
-}
-; CHECK-LABEL: ret_16bits_lower
-; CHECK-NEXT: mov eax,0xffff
-; ARM32-LABEL: ret_16bits_lower
-; ARM32-NEXT: movw r0, #65535
-; ARM32-NEXT: bx lr
-; MIPS32-LABEL: ret_16bits_lower
-; MIPS32-NEXT: lui v0,0x0
-; MIPS32-NEXT: ori v0,v0,0xffff
-
-define internal i32 @ret_17bits_lower() {
- ret i32 131071
-}
-; CHECK-LABEL: ret_17bits_lower
-; CHECK-NEXT: mov eax,0x1ffff
-; ARM32-LABEL: ret_17bits_lower
-; ARM32-NEXT: movw r0, #65535
-; ARM32-NEXT: movt r0, #1
-; MIPS32-LABEL: ret_17bits_lower
-; MIPS32-NEXT: lui v0,0x1
-; MIPS32-NEXT: ori v0,v0,0xffff
-
-
-define internal i32 @ret_16bits_upper() {
- ret i32 4294901760
-}
-; CHECK-LABEL: ret_16bits_upper
-; CHECK-NEXT: mov eax,0xffff0000
-; ARM32-LABEL: ret_16bits_upper
-; ARM32-NEXT: movw r0, #0
-; ARM32-NEXT: movt r0, #65535
-; MIPS32-LABEL: ret_16bits_upper
-; MIPS32-NEXT: lui v0,0xffff
-
-
-; Some 32-bit immediates can be inverted, and moved in a single instruction.
-
-define internal i32 @ret_8bits_inverted_shift_left0() {
- ret i32 4294967040
-}
-; CHECK-LABEL: ret_8bits_inverted_shift_left0
-; CHECK-NEXT: mov eax,0xffffff00
-; ARM32-LABEL: ret_8bits_inverted_shift_left0
-; ARM32-NEXT: mvn r0, #255
-; ARM32-NEXT: bx lr
-; MIPS32-LABEL: ret_8bits_inverted_shift_left0
-; MIPS32-NEXT: li v0,-256
-
-define internal i32 @ret_8bits_inverted_shift_left24() {
- ret i32 16777215
-}
-; CHECK-LABEL: ret_8bits_inverted_shift_left24
-; CHECK-NEXT: mov eax,0xffffff
-; ARM32-LABEL: ret_8bits_inverted_shift_left24
-; ARM32-NEXT: mvn r0, #-16777216
-; ARM32-NEXT: bx lr
-; MIPS32-LABEL: ret_8bits_inverted_shift_left24
-; MIPS32-NEXT: lui v0,0xff
-; MIPS32-NEXT: ori v0,v0,0xffff
-
-define internal i32 @ret_8bits_inverted_ror2() {
- ret i32 1073741760
-}
-; CHECK-LABEL: ret_8bits_inverted_ror2
-; CHECK-NEXT: mov eax,0x3fffffc0
-; ARM32-LABEL: ret_8bits_inverted_ror2
-; ARM32-NEXT: mvn r0, #-1073741761
-; ARM32-NEXT: bx lr
-; MIPS32-LABEL: ret_8bits_inverted_ror2
-; MIPS32-NEXT: lui v0,0x3fff
-; MIPS32-NEXT: ori v0,v0,0xffc0
-
-define internal i32 @ret_8bits_inverted_ror6() {
- ret i32 67108860
-}
-; CHECK-LABEL: ret_8bits_inverted_ror6
-; CHECK-NEXT: mov eax,0x3fffffc
-; ARM32-LABEL: ret_8bits_inverted_ror6
-; ARM32-NEXT: mvn r0, #-67108861
-; ARM32-NEXT: bx lr
-; MIPS32-LABEL: ret_8bits_inverted_ror6
-; MIPS32-NEXT: lui v0,0x3ff
-; MIPS32-NEXT: ori v0,v0,0xfffc
-
-
-define internal i32 @ret_8bits_inverted_ror7() {
- ret i32 33554430
-}
-; CHECK-LABEL: ret_8bits_inverted_ror7
-; CHECK-NEXT: mov eax,0x1fffffe
-; ARM32-LABEL: ret_8bits_inverted_ror7
-; ARM32-NEXT: movw r0, #65534
-; ARM32-NEXT: movt r0, #511
-; MIPS32-LABEL: ret_8bits_inverted_ror7
-; MIPS32-NEXT: lui v0,0x1ff
-; MIPS32-NEXT: ori v0,v0,0xfffe
-
-; 64-bit immediates.
-
-define internal i64 @ret_64bits_shift_left0() {
- ret i64 1095216660735
-}
-; CHECK-LABEL: ret_64bits_shift_left0
-; CHECK-NEXT: mov eax,0xff
-; CHECK-NEXT: mov edx,0xff
-; ARM32-LABEL: ret_64bits_shift_left0
-; ARM32-NEXT: mov r0, #255
-; ARM32-NEXT: mov r1, #255
-; MIPS32-LABEL: ret_64bits_shift_left0
-; MIPS32-NEXT: li v0,255
-; MIPS32-NEXT: li v1,255
-
-
-; A relocatable constant is assumed to require 32-bits along with
-; relocation directives.
-
-declare void @_start()
-
-define internal i32 @ret_addr() {
- %ptr = ptrtoint void ()* @_start to i32
- ret i32 %ptr
-}
-; CHECK-LABEL: ret_addr
-; CHECK-NEXT: mov eax,0x0 {{.*}} R_386_32 _start
-; ARM32-LABEL: ret_addr
-; ARM32-NEXT: movw r0, #0 {{.*}} R_ARM_MOVW_ABS_NC _start
-; ARM32-NEXT: movt r0, #0 {{.*}} R_ARM_MOVT_ABS _start
-; TODO(RKotler) emitting proper li but in disassembly
-; it shows up only in the relocation records. Should emit
-; without the macro but we still need to add GOT implementation
-; to finish this case
-;
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/returns_twice_no_coalesce.ll b/third_party/subzero/tests_lit/llvm2ice_tests/returns_twice_no_coalesce.ll
deleted file mode 100644
index c9da9cb..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/returns_twice_no_coalesce.ll
+++ /dev/null
@@ -1,59 +0,0 @@
-; This file checks that SimpleCoalescing of local stack slots is not done
-; when calling a function with the "returns twice" attribute.
-
-; RUN: %p2i -i %s --filetype=obj --disassemble --args -Om1 \
-; RUN: -allow-externally-defined-symbols | FileCheck %s
-
-; Setjmp is a function with the "returns twice" attribute.
-declare i32 @llvm.nacl.setjmp(i8*)
-
-declare i32 @other(i32)
-declare void @user(i32)
-
-define internal i32 @call_returns_twice(i32 %iptr_jmpbuf, i32 %x) {
-entry:
- %local = add i32 %x, 12345
- %jmpbuf = inttoptr i32 %iptr_jmpbuf to i8*
- %y = call i32 @llvm.nacl.setjmp(i8* %jmpbuf)
- call void @user(i32 %local)
- %cmp = icmp eq i32 %y, 0
- br i1 %cmp, label %Zero, label %NonZero
-Zero:
- %other_local = add i32 %x, 54321
- call void @user(i32 %other_local)
- ret i32 %other_local
-NonZero:
- ret i32 1
-}
-
-; CHECK-LABEL: call_returns_twice
-; CHECK: add [[REG1:.*]],0x3039
-; CHECK: mov DWORD PTR [esp+[[OFF:.*]]],[[REG1]]
-; CHECK: add [[REG2:.*]],0xd431
-; There should not be sharing of the stack slot.
-; CHECK-NOT: mov DWORD PTR [esp + [[OFF]]], [[REG2]]
-
-define internal i32 @no_call_returns_twice(i32 %iptr_jmpbuf, i32 %x) {
-entry:
- %local = add i32 %x, 12345
- %y = call i32 @other(i32 %x)
- call void @user(i32 %local)
- %cmp = icmp eq i32 %y, 0
- br i1 %cmp, label %Zero, label %NonZero
-Zero:
- %other_local = add i32 %x, 54321
- call void @user(i32 %other_local)
- ret i32 %other_local
-NonZero:
- ret i32 1
-}
-
-; CHECK-LABEL: no_call_returns_twice
-; CHECK: add [[REG1:.*]],0x3039
-; CHECK: mov DWORD PTR [esp+[[OFF:.*]]],[[REG1]]
-; CHECK: add [[REG2:.*]],0xd431
-; Now there should be sharing of the stack slot (OFF is the same).
-; Commenting out after disabling simple coalescing for -Om1.
-; TODO(stichnot): Add it back if/when we add a flag to enable simple
-; coalescing.
-; xCHECK: mov DWORD PTR [esp + [[OFF]]], [[REG2]]
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/rmw.ll b/third_party/subzero/tests_lit/llvm2ice_tests/rmw.ll
deleted file mode 100644
index 39f5a32..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/rmw.ll
+++ /dev/null
@@ -1,146 +0,0 @@
-; This tests Read-Modify-Write (RMW) detection and lowering at the O2
-; optimization level.
-
-; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
-; RUN: --target x8632 -i %s --args -O2 \
-; RUN: | %if --need=target_X8632 --command FileCheck %s
-
-define internal void @rmw_add_i32_var(i32 %addr_arg, i32 %var) {
-entry:
- %addr = inttoptr i32 %addr_arg to i32*
- %val = load i32, i32* %addr, align 1
- %rmw = add i32 %val, %var
- store i32 %rmw, i32* %addr, align 1
- ret void
-}
-; Look for something like: add DWORD PTR [eax],ecx
-; CHECK-LABEL: rmw_add_i32_var
-; CHECK: add DWORD PTR [e{{ax|bx|cx|dx|bp|di|si}}],e{{ax|bx|cx|dx|bp|di|si}}
-
-define internal void @rmw_add_i32_imm(i32 %addr_arg) {
-entry:
- %addr = inttoptr i32 %addr_arg to i32*
- %val = load i32, i32* %addr, align 1
- %rmw = add i32 %val, 19
- store i32 %rmw, i32* %addr, align 1
- ret void
-}
-; Look for something like: add DWORD PTR [eax],0x13
-; CHECK-LABEL: rmw_add_i32_imm
-; CHECK: add DWORD PTR [e{{ax|bx|cx|dx|bp|di|si}}],0x13
-
-define internal i32 @no_rmw_add_i32_var(i32 %addr_arg, i32 %var) {
-entry:
- %addr = inttoptr i32 %addr_arg to i32*
- %val = load i32, i32* %addr, align 1
- %rmw = add i32 %val, %var
- store i32 %rmw, i32* %addr, align 1
- ret i32 %rmw
-}
-; CHECK-LABEL: no_rmw_add_i32_var
-; CHECK: add e{{ax|bx|cx|dx|bp|di|si}},DWORD PTR [e{{ax|bx|cx|dx|bp|di|si}}]
-
-define internal void @rmw_add_i16_var(i32 %addr_arg, i32 %var32) {
-entry:
- %var = trunc i32 %var32 to i16
- %addr = inttoptr i32 %addr_arg to i16*
- %val = load i16, i16* %addr, align 1
- %rmw = add i16 %val, %var
- store i16 %rmw, i16* %addr, align 1
- ret void
-}
-; Look for something like: add WORD PTR [eax],cx
-; CHECK-LABEL: rmw_add_i16_var
-; CHECK: add WORD PTR [e{{ax|bx|cx|dx|bp|di|si}}],{{ax|bx|cx|dx|bp|di|si}}
-
-define internal void @rmw_add_i16_imm(i32 %addr_arg) {
-entry:
- %addr = inttoptr i32 %addr_arg to i16*
- %val = load i16, i16* %addr, align 1
- %rmw = add i16 %val, 19
- store i16 %rmw, i16* %addr, align 1
- ret void
-}
-; Look for something like: add WORD PTR [eax],0x13
-; CHECK-LABEL: rmw_add_i16_imm
-; CHECK: add WORD PTR [e{{ax|bx|cx|dx|bp|di|si}}],0x13
-
-define internal void @rmw_add_i8_var(i32 %addr_arg, i32 %var32) {
-entry:
- %var = trunc i32 %var32 to i8
- %addr = inttoptr i32 %addr_arg to i8*
- %val = load i8, i8* %addr, align 1
- %rmw = add i8 %val, %var
- store i8 %rmw, i8* %addr, align 1
- ret void
-}
-; Look for something like: add BYTE PTR [eax],cl
-; CHECK-LABEL: rmw_add_i8_var
-; CHECK: add BYTE PTR [e{{ax|bx|cx|dx|bp|di|si}}],{{al|bl|cl|dl}}
-
-define internal void @rmw_add_i8_imm(i32 %addr_arg) {
-entry:
- %addr = inttoptr i32 %addr_arg to i8*
- %val = load i8, i8* %addr, align 1
- %rmw = add i8 %val, 19
- store i8 %rmw, i8* %addr, align 1
- ret void
-}
-; Look for something like: add BYTE PTR [eax],0x13
-; CHECK-LABEL: rmw_add_i8_imm
-; CHECK: add BYTE PTR [e{{ax|bx|cx|dx|bp|di|si}}],0x13
-
-define internal void @rmw_add_i32_var_addropt(i32 %addr_arg, i32 %var) {
-entry:
- %addr_arg_plus_12 = add i32 %addr_arg, 12
- %var_times_4 = mul i32 %var, 4
- %addr_base = add i32 %addr_arg_plus_12 , %var_times_4
- %addr = inttoptr i32 %addr_base to i32*
- %val = load i32, i32* %addr, align 1
- %rmw = add i32 %val, %var
- store i32 %rmw, i32* %addr, align 1
- ret void
-}
-; Look for something like: add DWORD PTR [eax+ecx*4+12],ecx
-; CHECK-LABEL: rmw_add_i32_var_addropt
-; CHECK: add DWORD PTR [e{{..}}+e{{..}}*4+0xc],e{{ax|bx|cx|dx|bp|di|si}}
-
-; Test for commutativity opportunities. This is the same as rmw_add_i32_var
-; except with the "add" operands reversed.
-define internal void @rmw_add_i32_var_comm(i32 %addr_arg, i32 %var) {
-entry:
- %addr = inttoptr i32 %addr_arg to i32*
- %val = load i32, i32* %addr, align 1
- %rmw = add i32 %var, %val
- store i32 %rmw, i32* %addr, align 1
- ret void
-}
-; Look for something like: add DWORD PTR [eax],ecx
-; CHECK-LABEL: rmw_add_i32_var_comm
-; CHECK: add DWORD PTR [e{{ax|bx|cx|dx|bp|di|si}}],e{{ax|bx|cx|dx|bp|di|si}}
-
-; Test that commutativity isn't triggered for a non-commutative arithmetic
-; operator (sub). This is the same as rmw_add_i32_var_comm except with a
-; "sub" operation.
-define internal i32 @no_rmw_sub_i32_var(i32 %addr_arg, i32 %var) {
-entry:
- %addr = inttoptr i32 %addr_arg to i32*
- %val = load i32, i32* %addr, align 1
- %rmw = sub i32 %var, %val
- store i32 %rmw, i32* %addr, align 1
- ret i32 %rmw
-}
-; CHECK-LABEL: no_rmw_sub_i32_var
-; CHECK: sub e{{ax|bx|cx|dx|bp|di|si}},DWORD PTR [e{{ax|bx|cx|dx|bp|di|si}}]
-
-define internal void @rmw_add_i64_undef(i32 %addr_arg) {
-entry:
- %addr = inttoptr i32 %addr_arg to i64*
- %val = load i64, i64* %addr, align 1
- %rmw = add i64 %val, undef
- store i64 %rmw, i64* %addr, align 1
- ret void
-}
-; CHECK-LABEL: rmw_add_i64_undef
-; CHECK: add DWORD PTR [e{{ax|bx|cx|dx|bp|di|si}}],0x0
-; CHECK: adc DWORD PTR [e{{ax|bx|cx|dx|bp|di|si}}+0x4],0x0
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/rng.ll b/third_party/subzero/tests_lit/llvm2ice_tests/rng.ll
deleted file mode 100644
index 24140ea..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/rng.ll
+++ /dev/null
@@ -1,259 +0,0 @@
-; This is a smoke test of random number generator.
-; The random number generators for different randomization passes should be
-; decoupled. The random number used in one randomization pass should not be
-; influenced by the existence of other randomization passes.
-
-; REQUIRES: allow_dump, target_X8632
-
-; Command for checking constant blinding (Need to turn off nop-insertion)
-; RUN: %p2i --target x8632 -i %s --filetype=obj --disassemble --args -O2 \
-; RUN: -sz-seed=1 -randomize-pool-immediates=randomize \
-; RUN: -randomize-pool-threshold=0x1 \
-; RUN: -reorder-global-variables \
-; RUN: -reorder-basic-blocks \
-; RUN: -reorder-functions \
-; RUN: -randomize-regalloc \
-; RUN: -nop-insertion=0 \
-; RUN: -reorder-pooled-constants \
-; RUN: | FileCheck %s --check-prefix=BLINDINGO2
-
-; Command for checking global variable reordering
-; RUN: %p2i --target x8632 -i %s \
-; RUN: --filetype=obj --disassemble --dis-flags=-rD \
-; RUN: --args -O2 -sz-seed=1 \
-; RUN: -randomize-pool-immediates=randomize \
-; RUN: -randomize-pool-threshold=0x1 \
-; RUN: -reorder-global-variables \
-; RUN: -reorder-basic-blocks \
-; RUN: -reorder-functions \
-; RUN: -randomize-regalloc \
-; RUN: -nop-insertion \
-; RUN: -reorder-pooled-constants \
-; RUN: | FileCheck %s --check-prefix=GLOBALVARS
-
-; Command for checking basic block reordering
-; RUN: %p2i --target x8632 -i %s --filetype=asm --args -O2 -sz-seed=1\
-; RUN: -randomize-pool-immediates=randomize \
-; RUN: -randomize-pool-threshold=0x1 \
-; RUN: -reorder-global-variables \
-; RUN: -reorder-basic-blocks \
-; RUN: -reorder-functions \
-; RUN: -randomize-regalloc \
-; RUN: -nop-insertion \
-; RUN: -reorder-pooled-constants \
-; RUN: | FileCheck %s --check-prefix=BBREORDERING
-
-; Command for checking function reordering
-; RUN: %p2i --target x8632 -i %s --filetype=obj --disassemble --args -O2 \
-; RUN: -sz-seed=1 -randomize-pool-immediates=randomize \
-; RUN: -randomize-pool-threshold=0x1 \
-; RUN: -reorder-global-variables \
-; RUN: -reorder-basic-blocks \
-; RUN: -reorder-functions \
-; RUN: -randomize-regalloc \
-; RUN: -nop-insertion \
-; RUN: -reorder-pooled-constants \
-; RUN: | FileCheck %s --check-prefix=FUNCREORDERING
-
-; Command for checking regalloc randomization
-; RUN: %p2i --target x8632 -i %s --filetype=obj --disassemble --args -O2 \
-; RUN: -sz-seed=1 -randomize-pool-immediates=randomize \
-; RUN: -randomize-pool-threshold=0x1 \
-; RUN: -reorder-global-variables \
-; RUN: -reorder-basic-blocks \
-; RUN: -reorder-functions \
-; RUN: -randomize-regalloc \
-; RUN: -nop-insertion \
-; RUN: -reorder-pooled-constants \
-; RUN: -split-local-vars=0 \
-; RUN: | FileCheck %s --check-prefix=REGALLOC
-
-; Command for checking nop insertion (Need to turn off randomize-regalloc)
-; RUN: %p2i --target x8632 -i %s --filetype=asm --args \
-; RUN: -sz-seed=1 -randomize-pool-immediates=randomize \
-; RUN: -reorder-global-variables \
-; RUN: -reorder-basic-blocks \
-; RUN: -reorder-functions \
-; RUN: -randomize-regalloc=0 \
-; RUN: -nop-insertion -nop-insertion-percentage=50\
-; RUN: -reorder-pooled-constants \
-; RUN: | FileCheck %s --check-prefix=NOPINSERTION
-
-; Command for checking pooled constants reordering
-; RUN: %p2i --target x8632 -i %s --filetype=obj --disassemble --dis-flags=-s \
-; RUN: --args -O2 -sz-seed=1 \
-; RUN: -randomize-pool-immediates=randomize \
-; RUN: -randomize-pool-threshold=0x1 \
-; RUN: -reorder-global-variables \
-; RUN: -reorder-basic-blocks \
-; RUN: -reorder-functions \
-; RUN: -randomize-regalloc \
-; RUN: -nop-insertion \
-; RUN: -reorder-pooled-constants \
-; RUN: | FileCheck %s --check-prefix=POOLEDCONSTANTS
-
-
-; Global variables copied from reorder-global-variables.ll
-@PrimitiveInit = internal global [4 x i8] c"\1B\00\00\00", align 4
-@PrimitiveInitConst = internal constant [4 x i8] c"\0D\00\00\00", align 4
-@ArrayInit = internal global [20 x i8] c"\0A\00\00\00\14\00\00\00\1E\00\00\00(\00\00\002\00\00\00", align 4
-@ArrayInitPartial = internal global [40 x i8] c"<\00\00\00F\00\00\00P\00\00\00Z\00\00\00d\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00", align 4
-@PrimitiveInitStatic = internal global [4 x i8] zeroinitializer, align 4
-@PrimitiveUninit = internal global [4 x i8] zeroinitializer, align 4
-@ArrayUninit = internal global [20 x i8] zeroinitializer, align 4
-@ArrayUninitConstDouble = internal constant [200 x i8] zeroinitializer, align 8
-@ArrayUninitConstInt = internal constant [20 x i8] zeroinitializer, align 4
-
-
-define internal <4 x i32> @func1(<4 x i32> %a, <4 x i32> %b) {
-entry:
- %res = mul <4 x i32> %a, %b
- ret <4 x i32> %res
-
-; NOPINSERTION-LABEL: func1
-; NOPINSERTION: nop /* variant = 1 */
-; NOPINSERTION: subl $60, %esp
-; NOPINSERTION: nop /* variant = 3 */
-; NOPINSERTION: movups %xmm0, 32(%esp)
-; NOPINSERTION: movups %xmm1, 16(%esp)
-; NOPINSERTION: movups 32(%esp), %xmm0
-; NOPINSERTION: nop /* variant = 1 */
-; NOPINSERTION: pshufd $49, 32(%esp), %xmm1
-; NOPINSERTION: nop /* variant = 4 */
-; NOPINSERTION: pshufd $49, 16(%esp), %xmm2
-; NOPINSERTION: nop /* variant = 1 */
-; NOPINSERTION: pmuludq 16(%esp), %xmm0
-; NOPINSERTION: pmuludq %xmm2, %xmm1
-; NOPINSERTION: nop /* variant = 0 */
-; NOPINSERTION: shufps $136, %xmm1, %xmm0
-; NOPINSERTION: nop /* variant = 3 */
-; NOPINSERTION: pshufd $216, %xmm0, %xmm0
-; NOPINSERTION: nop /* variant = 1 */
-; NOPINSERTION: movups %xmm0, (%esp)
-; NOPINSERTION: movups (%esp), %xmm0
-; NOPINSERTION: addl $60, %esp
-; NOPINSERTION: ret
-}
-
-
-
-define internal float @func2(float* %arg) {
-entry:
- %arg.int = ptrtoint float* %arg to i32
- %addr.int = add i32 %arg.int, 200000
- %addr.ptr = inttoptr i32 %addr.int to float*
- %addr.load = load float, float* %addr.ptr, align 4
- ret float %addr.load
-
-; BLINDINGO2-LABEL: func2
-; BLINDINGO2: lea [[REG:e[a-z]*]],{{[[]}}{{e[a-z]*}}+0x69ed4ee7{{[]]}}
-}
-
-define internal float @func3(i32 %arg, float %input) {
-entry:
- switch i32 %arg, label %return [
- i32 0, label %sw.bb
- i32 1, label %sw.bb1
- i32 2, label %sw.bb2
- i32 3, label %sw.bb3
- i32 4, label %sw.bb4
- ]
-
-sw.bb:
- %rbb = fadd float %input, 1.000000e+00
- br label %return
-
-sw.bb1:
- %rbb1 = fadd float %input, 2.000000e+00
- br label %return
-
-sw.bb2:
- %rbb2 = fadd float %input, 4.000000e+00
- br label %return
-
-sw.bb3:
- %rbb3 = fadd float %input, 5.000000e-01
- br label %return
-
-sw.bb4:
- %rbb4 = fadd float %input, 2.500000e-01
- br label %return
-
-return:
- %retval.0 = phi float [ %rbb, %sw.bb ], [ %rbb1, %sw.bb1 ], [ %rbb2, %sw.bb2 ], [ %rbb3, %sw.bb3 ], [ %rbb4, %sw.bb4], [ 0.000000e+00, %entry ]
- ret float %retval.0
-}
-
-define internal <4 x i32> @func4(<4 x i32> %a, <4 x i32> %b) {
-entry:
- %res = mul <4 x i32> %a, %b
- ret <4 x i32> %res
-
-; REGALLOC-LABEL: func4
-; REGALLOC: movups xmm3,xmm0
-; REGALLOC-NEXT: pshufd xmm0,xmm0,0x31
-; REGALLOC-NEXT: pshufd xmm4,xmm1,0x31
-; REGALLOC-NEXT: pmuludq xmm3,xmm1
-; REGALLOC-NEXT: pmuludq xmm0,xmm4
-; REGALLOC-NEXT: shufps xmm3,xmm0,0x88
-; REGALLOC-NEXT: pshufd xmm3,xmm3,0xd8
-; REGALLOC-NEXT: movups xmm0,xmm3
-; REGALLOC-NEXT: ret
-}
-
-define internal void @func5(i32 %foo, i32 %bar) {
-entry:
- %r1 = icmp eq i32 %foo, %bar
- br i1 %r1, label %BB1, label %BB2
-BB1:
- %r2 = icmp sgt i32 %foo, %bar
- br i1 %r2, label %BB3, label %BB4
-BB2:
- %r3 = icmp slt i32 %foo, %bar
- br i1 %r3, label %BB3, label %BB4
-BB3:
- ret void
-BB4:
- ret void
-
-; BBREORDERING-LABEL: func5:
-; BBREORDERING: .Lfunc5$entry:
-; BBREORDERING: .Lfunc5$BB1:
-; BBREORDERING: .Lfunc5$BB2:
-; BBREORDERING: .Lfunc5$BB4:
-; BBREORDERING: .Lfunc5$BB3
-}
-
-define internal i32 @func6(i32 %arg) {
-entry:
- %res = add i32 200000, %arg
- ret i32 %res
-
-; BLINDINGO2-LABEL: func6
-; BLINDINGO2: mov [[REG:e[a-z]*]],0x77254ee7
-; BLINDINGO2-NEXT: lea [[REG]],{{[[]}}[[REG]]-0x772241a7{{[]]}}
-}
-
-; Check for function reordering
-; FUNCREORDERING-LABEL: func1
-; FUNCREORDERING-LABEL: func4
-; FUNCREORDERING-LABEL: func5
-; FUNCREORDERING-LABEL: func2
-; FUNCREORDERING-LABEL: func6
-; FUNCREORDERING-LABEL: func3
-
-; Check for global variable reordering
-; GLOBALVARS-LABEL: ArrayInit
-; GLOBALVARS-LABEL: PrimitiveInit
-; GLOBALVARS-LABEL: ArrayInitPartial
-; GLOBALVARS-LABEL: PrimitiveUninit
-; GLOBALVARS-LABEL: ArrayUninit
-; GLOBALVARS-LABEL: PrimitiveInitStatic
-; GLOBALVARS-LABEL: ArrayUninitConstDouble
-; GLOBALVARS-LABEL: ArrayUninitConstInt
-; GLOBALVARS-LABEL: PrimitiveInitConst
-
-; Check for pooled constant reordering
-; POOLEDCONSTANTS-LABEL: .rodata.cst4
-; POOLEDCONSTANTS: 0000803e 0000803f 0000003f 00008040
-; POOLEDCONSTANTS: 00000040
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/sdiv.ll b/third_party/subzero/tests_lit/llvm2ice_tests/sdiv.ll
deleted file mode 100644
index 4097a55..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/sdiv.ll
+++ /dev/null
@@ -1,105 +0,0 @@
-; This checks the correctness of the lowering code for the small
-; integer variants of sdiv and srem.
-
-; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 | FileCheck %s
-; RUN: %p2i -i %s --filetype=obj --disassemble --args -Om1 | FileCheck %s
-
-; RUN: %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command %p2i --filetype=asm --assemble --disassemble --target \
-; RUN: mips32 -i %s --args -O2 -allow-externally-defined-symbols \
-; RUN: | %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command FileCheck --check-prefix MIPS32 %s
-
-define internal i32 @sdiv_i8(i32 %a.i32, i32 %b.i32) {
-entry:
- %a = trunc i32 %a.i32 to i8
- %b = trunc i32 %b.i32 to i8
- %res = sdiv i8 %a, %b
- %res.i32 = zext i8 %res to i32
- ret i32 %res.i32
-; CHECK-LABEL: sdiv_i8
-; CHECK: cbw
-; CHECK: idiv
-; MIPS32-LABEL: sdiv_i8
-; MIPS32: div
-; MIPS32: teq
-; MIPS32: mflo
-; MIPS32: andi {{.*}},0xff
-}
-
-define internal i32 @sdiv_i16(i32 %a.i32, i32 %b.i32) {
-entry:
- %a = trunc i32 %a.i32 to i16
- %b = trunc i32 %b.i32 to i16
- %res = sdiv i16 %a, %b
- %res.i32 = zext i16 %res to i32
- ret i32 %res.i32
-; CHECK-LABEL: sdiv_i16
-; CHECK: cwd
-; CHECK: idiv
-; MIPS32-LABEL: sdiv_i16
-; MIPS32: div
-; MIPS32: teq
-; MIPS32: mflo
-; MIPS32: andi {{.*}},0xffff
-}
-
-define internal i32 @sdiv_i32(i32 %a, i32 %b) {
-entry:
- %res = sdiv i32 %a, %b
- ret i32 %res
-; CHECK-LABEL: sdiv_i32
-; CHECK: cdq
-; CHECK: idiv
-; MIPS32-LABEL: sdiv_i32
-; MIPS32: div
-; MIPS32: teq
-; MIPS32: mflo
-}
-
-define internal i32 @srem_i8(i32 %a.i32, i32 %b.i32) {
-entry:
- %a = trunc i32 %a.i32 to i8
- %b = trunc i32 %b.i32 to i8
- %res = srem i8 %a, %b
- %res.i32 = zext i8 %res to i32
- ret i32 %res.i32
-; CHECK-LABEL: srem_i8
-; CHECK: cbw
-; CHECK: idiv
-; MIPS32-LABEL: srem_i8
-; MIPS32: div
-; MIPS32: teq
-; MIPS32: mfhi
-; MIPS32: andi {{.*}},0xff
-}
-
-define internal i32 @srem_i16(i32 %a.i32, i32 %b.i32) {
-entry:
- %a = trunc i32 %a.i32 to i16
- %b = trunc i32 %b.i32 to i16
- %res = srem i16 %a, %b
- %res.i32 = zext i16 %res to i32
- ret i32 %res.i32
-; CHECK-LABEL: srem_i16
-; CHECK: cwd
-; CHECK: idiv
-; MIPS32-LABEL: srem_i16
-; MIPS32: div
-; MIPS32: teq
-; MIPS32: mfhi
-; MIPS32: andi {{.*}},0xffff
-}
-
-define internal i32 @srem_i32(i32 %a, i32 %b) {
-entry:
- %res = srem i32 %a, %b
- ret i32 %res
-; CHECK-LABEL: srem_i32
-; CHECK: cdq
-; CHECK: idiv
-; MIPS32-LABEL: srem_i32
-; MIPS32: div
-; MIPS32: teq
-; MIPS32: mfhi
-}
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/select-opt.ll b/third_party/subzero/tests_lit/llvm2ice_tests/select-opt.ll
deleted file mode 100644
index 2383f8b..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/select-opt.ll
+++ /dev/null
@@ -1,110 +0,0 @@
-; Simple test of the select instruction. The CHECK lines are only
-; checking for basic instruction patterns that should be present
-; regardless of the optimization level, so there are no special OPTM1
-; match lines.
-
-; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
-; RUN: --target x8632 -i %s --args -O2 -allow-externally-defined-symbols \
-; RUN: | %if --need=target_X8632 --command FileCheck %s
-; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
-; RUN: --target x8632 -i %s --args -Om1 -allow-externally-defined-symbols \
-; RUN: | %if --need=target_X8632 --command FileCheck %s
-
-; RUN: %if --need=target_ARM32 \
-; RUN: --command %p2i --filetype=obj \
-; RUN: --disassemble --target arm32 -i %s --args -O2 \
-; RUN: -allow-externally-defined-symbols \
-; RUN: | %if --need=target_ARM32 \
-; RUN: --command FileCheck --check-prefix ARM32 --check-prefix ARM32-O2 %s
-; RUN: %if --need=target_ARM32 \
-; RUN: --command %p2i --filetype=obj \
-; RUN: --disassemble --target arm32 -i %s --args -Om1 \
-; RUN: -allow-externally-defined-symbols \
-; RUN: | %if --need=target_ARM32 \
-; RUN: --command FileCheck --check-prefix ARM32 --check-prefix ARM32-OM1 %s
-
-; RUN: %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command %p2i --filetype=asm --assemble \
-; RUN: --disassemble --target mips32 -i %s --args -Om1 \
-; RUN: -allow-externally-defined-symbols \
-; RUN: | %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command FileCheck --check-prefix MIPS32 %s
-
-; RUN: %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command %p2i --filetype=asm --assemble \
-; RUN: --disassemble --target mips32 -i %s --args -O2 \
-; RUN: -allow-externally-defined-symbols \
-; RUN: | %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command FileCheck --check-prefix MIPS32 %s
-
-define internal void @testSelect(i32 %a, i32 %b) {
-entry:
- %cmp = icmp slt i32 %a, %b
- %cond = select i1 %cmp, i32 %a, i32 %b
- tail call void @useInt(i32 %cond)
- %cmp1 = icmp sgt i32 %a, %b
- %cond2 = select i1 %cmp1, i32 10, i32 20
- tail call void @useInt(i32 %cond2)
- ; Create "fake" uses of %cmp and %cmp1 to prevent O2 bool folding.
- %d1 = zext i1 %cmp to i32
- call void @useInt(i32 %d1)
- %d2 = zext i1 %cmp1 to i32
- call void @useInt(i32 %d2)
- ret void
-}
-
-declare void @useInt(i32 %x)
-
-; CHECK-LABEL: testSelect
-; CHECK: cmp
-; CHECK: cmp
-; CHECK: call {{.*}} R_{{.*}} useInt
-; CHECK: cmp
-; CHECK: cmp
-; CHECK: call {{.*}} R_{{.*}} useInt
-; CHECK: ret
-; ARM32-LABEL: testSelect
-; ARM32: cmp
-; ARM32: bl {{.*}} useInt
-; ARM32-Om1: mov {{.*}}, #20
-; ARM32-O2: mov [[REG:r[0-9]+]], #20
-; ARM32: tst
-; ARM32-Om1: movne {{.*}}, #10
-; ARM32-O2: movne [[REG]], #10
-; ARM32: bl {{.*}} useInt
-; ARM32: bl {{.*}} useInt
-; ARM32: bl {{.*}} useInt
-; ARM32: bx lr
-; MIPS32-LABEL: testSelect
-; MIPS32: slt {{.*}}
-; MIPS32: movn {{.*}}
-
-; Check for valid addressing mode in the cmp instruction when the
-; operand is an immediate.
-define internal i32 @testSelectImm32(i32 %a, i32 %b) {
-entry:
- %cond = select i1 false, i32 %a, i32 %b
- ret i32 %cond
-}
-; CHECK-LABEL: testSelectImm32
-; CHECK-NOT: cmp 0x{{[0-9a-f]+}},
-; ARM32-LABEL: testSelectImm32
-; ARM32-NOT: cmp #{{.*}},
-; MIPS32-LABEL: testSelectImm32
-; MIPS32: movn {{.*}}
-
-; Check for valid addressing mode in the cmp instruction when the
-; operand is an immediate. There is a different x86-32 lowering
-; sequence for 64-bit operands.
-define internal i64 @testSelectImm64(i64 %a, i64 %b) {
-entry:
- %cond = select i1 true, i64 %a, i64 %b
- ret i64 %cond
-}
-; CHECK-LABEL: testSelectImm64
-; CHECK-NOT: cmp 0x{{[0-9a-f]+}},
-; ARM32-LABEL: testSelectImm64
-; ARM32-NOT: cmp #{{.*}},
-; MIPS32-LABEL: testSelectImm64
-; MIPS32: movn
-; MIPS32: movn
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/shift.ll b/third_party/subzero/tests_lit/llvm2ice_tests/shift.ll
deleted file mode 100644
index cb9aa92..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/shift.ll
+++ /dev/null
@@ -1,296 +0,0 @@
-; This is a test of C-level conversion operations that clang lowers
-; into pairs of shifts.
-
-; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
-; RUN: --target x8632 -i %s --args -O2 \
-; RUN: | %if --need=target_X8632 --command FileCheck %s
-
-; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
-; RUN: --target x8632 -i %s --args -Om1 \
-; RUN: | %if --need=target_X8632 --command FileCheck %s
-
-; RUN: %if --need=target_ARM32 \
-; RUN: --command %p2i --filetype=obj \
-; RUN: --disassemble --target arm32 -i %s --args -O2 \
-; RUN: | %if --need=target_ARM32 \
-; RUN: --command FileCheck --check-prefix ARM32 %s
-
-; RUN: %if --need=target_ARM32 \
-; RUN: --command %p2i --filetype=obj \
-; RUN: --disassemble --target arm32 -i %s --args -Om1 \
-; RUN: | %if --need=target_ARM32 \
-; RUN: --command FileCheck --check-prefix ARM32 %s
-
-; RUN: %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command %p2i --filetype=asm --assemble \
-; RUN: --disassemble --target mips32 -i %s --args -O2 \
-; RUN: | %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command FileCheck --check-prefix MIPS32-O2 --check-prefix MIPS32 %s
-
-; RUN: %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command %p2i --filetype=asm --assemble \
-; RUN: --disassemble --target mips32 -i %s --args -Om1 \
-; RUN: | %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command FileCheck --check-prefix MIPS32-OM1 --check-prefix MIPS32 %s
-
-@i1 = internal global [4 x i8] zeroinitializer, align 4
-@i2 = internal global [4 x i8] zeroinitializer, align 4
-@u1 = internal global [4 x i8] zeroinitializer, align 4
-
-define internal void @conv1() {
-entry:
- %__0 = bitcast [4 x i8]* @u1 to i32*
- %v0 = load i32, i32* %__0, align 1
- %sext = shl i32 %v0, 24
- %v1 = ashr i32 %sext, 24
- %__4 = bitcast [4 x i8]* @i1 to i32*
- store i32 %v1, i32* %__4, align 1
- ret void
-}
-; CHECK-LABEL: conv1
-; CHECK: shl {{.*}},0x18
-; CHECK: sar {{.*}},0x18
-
-; ARM32-LABEL: conv1
-; ARM32: lsl {{.*}}, #24
-; ARM32: asr {{.*}}, #24
-
-define internal void @conv2() {
-entry:
- %__0 = bitcast [4 x i8]* @u1 to i32*
- %v0 = load i32, i32* %__0, align 1
- %sext1 = shl i32 %v0, 16
- %v1 = lshr i32 %sext1, 16
- %__4 = bitcast [4 x i8]* @i2 to i32*
- store i32 %v1, i32* %__4, align 1
- ret void
-}
-; CHECK-LABEL: conv2
-; CHECK: shl {{.*}},0x10
-; CHECK: shr {{.*}},0x10
-
-; ARM32-LABEL: conv2
-; ARM32: lsl {{.*}}, #16
-; ARM32: lsr {{.*}}, #16
-
-define internal i32 @shlImmLarge(i32 %val) {
-entry:
- %result = shl i32 %val, 257
- ret i32 %result
-}
-; CHECK-LABEL: shlImmLarge
-; CHECK: shl {{.*}},0x1
-
-; MIPS32-LABEL: shlImmLarge
-; MIPS32: sll
-
-define internal i32 @shlImmNeg(i32 %val) {
-entry:
- %result = shl i32 %val, -1
- ret i32 %result
-}
-; CHECK-LABEL: shlImmNeg
-; CHECK: shl {{.*}},0xff
-
-; MIPS32-LABEL: shlImmNeg
-; MIPS32: sll
-
-define internal i32 @lshrImmLarge(i32 %val) {
-entry:
- %result = lshr i32 %val, 257
- ret i32 %result
-}
-; CHECK-LABEL: lshrImmLarge
-; CHECK: shr {{.*}},0x1
-
-; MIPS32-LABEL: lshrImmLarge
-; MIPS32: srl
-
-define internal i32 @lshrImmNeg(i32 %val) {
-entry:
- %result = lshr i32 %val, -1
- ret i32 %result
-}
-; CHECK-LABEL: lshrImmNeg
-; CHECK: shr {{.*}},0xff
-
-; MIPS32-LABEL: lshrImmNeg
-; MIPS32: srl
-
-define internal i32 @ashrImmLarge(i32 %val) {
-entry:
- %result = ashr i32 %val, 257
- ret i32 %result
-}
-; CHECK-LABEL: ashrImmLarge
-; CHECK: sar {{.*}},0x1
-
-; MIPS32-LABEL: ashrImmLarge
-; MIPS32: sra
-
-define internal i32 @ashrImmNeg(i32 %val) {
-entry:
- %result = ashr i32 %val, -1
- ret i32 %result
-}
-; CHECK-LABEL: ashrImmNeg
-; CHECK: sar {{.*}},0xff
-
-; MIPS32-LABEL: ashrImmNeg
-; MIPS32: sra
-
-define internal i64 @shlImm64One(i64 %val) {
-entry:
- %result = shl i64 %val, 1
- ret i64 %result
-}
-; CHECK-LABEL: shlImm64One
-; CHECK: shl {{.*}},1
-; MIPS32-LABEL: shlImm64One
-; MIPS32: addu [[T_LO:.*]],[[VAL_LO:.*]],[[VAL_LO]]
-; MIPS32: sltu [[T1:.*]],[[T_LO]],[[VAL_LO]]
-; MIPS32: addu [[T2:.*]],[[T1]],[[VAL_HI:.*]]
-; MIPS32: addu {{.*}},[[VAL_HI]],[[T2]]
-
-define internal i64 @shlImm64LessThan32(i64 %val) {
-entry:
- %result = shl i64 %val, 4
- ret i64 %result
-}
-; CHECK-LABEL: shlImm64LessThan32
-; CHECK: shl {{.*}},0x4
-; MIPS32-LABEL: shlImm64LessThan32
-; MIPS32: srl [[T1:.*]],[[VAL_LO:.*]],0x1c
-; MIPS32: sll [[T2:.*]],{{.*}},0x4
-; MIPS32: or {{.*}},[[T1]],[[T2]]
-; MIPS32: sll {{.*}},[[VAL_LO]],0x4
-
-define internal i64 @shlImm64Equal32(i64 %val) {
-entry:
- %result = shl i64 %val, 32
- ret i64 %result
-}
-; CHECK-LABEL: shlImm64Equal32
-; CHECK-NOT: shl
-; MIPS32-LABEL: shlImm64Equal32
-; MIPS32: li {{.*}},0
-; MIPS32-O2: move
-; MIPS32-OM1: sw
-; MIPS32-OM1: lw
-
-define internal i64 @shlImm64GreaterThan32(i64 %val) {
-entry:
- %result = shl i64 %val, 40
- ret i64 %result
-}
-; CHECK-LABEL: shlImm64GreaterThan32
-; CHECK: shl {{.*}},0x8
-; MIPS32-LABEL: shlImm64GreaterThan32
-; MIPS32: sll {{.*}},{{.*}},0x8
-; MIPS32: li {{.*}},0
-
-define internal i64 @lshrImm64One(i64 %val) {
-entry:
- %result = lshr i64 %val, 1
- ret i64 %result
-}
-; CHECK-LABEL: lshrImm64One
-; CHECK: shr {{.*}},1
-; MIPS32-LABEL: lshrImm64One
-; MIPS32: sll [[T1:.*]],[[VAL_HI:.*]],0x1f
-; MIPS32: srl [[T2:.*]],{{.*}},0x1
-; MIPS32: or {{.*}},[[T1]],[[T2]]
-; MIPS32: srl {{.*}},[[VAL_HI]],0x1
-
-define internal i64 @lshrImm64LessThan32(i64 %val) {
-entry:
- %result = lshr i64 %val, 4
- ret i64 %result
-}
-; CHECK-LABEL: lshrImm64LessThan32
-; CHECK: shrd {{.*}},0x4
-; CHECK: shr {{.*}},0x4
-; MIPS32-LABEL: lshrImm64LessThan32
-; MIPS32: sll [[T1:.*]],[[VAL_HI:.*]],0x1c
-; MIPS32: srl [[T2:.*]],{{.*}},0x4
-; MIPS32: or {{.*}},[[T1]],[[T2]]
-; MIPS32: srl {{.*}},[[VAL_HI]],0x4
-
-define internal i64 @lshrImm64Equal32(i64 %val) {
-entry:
- %result = lshr i64 %val, 32
- ret i64 %result
-}
-; CHECK-LABEL: lshrImm64Equal32
-; CHECK-NOT: shr
-; MIPS32-LABEL: lshrImm64Equal32
-; MIPS32: li {{.*}},0
-; MIPS32-O2: move
-; MIPS32-OM1: sw
-; MIPS32-OM1: lw
-
-define internal i64 @lshrImm64GreaterThan32(i64 %val) {
-entry:
- %result = lshr i64 %val, 40
- ret i64 %result
-}
-; CHECK-LABEL: lshrImm64GreaterThan32
-; CHECK-NOT: shrd
-; CHECK: shr {{.*}},0x8
-; MIPS32-LABEL: lshrImm64GreaterThan32
-; MIPS32: srl {{.*}},{{.*}},0x8
-; MIPS32: li {{.*}},0
-
-define internal i64 @ashrImm64One(i64 %val) {
-entry:
- %result = ashr i64 %val, 1
- ret i64 %result
-}
-; CHECK-LABEL: ashrImm64One
-; CHECK: shrd {{.*}},0x1
-; CHECK: sar {{.*}},1
-; MIPS32-LABEL: ashrImm64One
-; MIPS32: sll [[T1:.*]],[[VAL_HI:.*]],0x1f
-; MIPS32: srl [[T2:.*]],{{.*}},0x1
-; MIPS32: or {{.*}},[[T1]],[[T2]]
-; MIPS32: sra {{.*}},[[VAL_HI]],0x1
-
-define internal i64 @ashrImm64LessThan32(i64 %val) {
-entry:
- %result = ashr i64 %val, 4
- ret i64 %result
-}
-; CHECK-LABEL: ashrImm64LessThan32
-; CHECK: shrd {{.*}},0x4
-; CHECK: sar {{.*}},0x4
-; MIPS32-LABEL: ashrImm64LessThan32
-; MIPS32: sll [[T1:.*]],[[VAL_HI:.*]],0x1c
-; MIPS32: srl [[T2:.*]],{{.*}},0x4
-; MIPS32: or {{.*}},[[T1]],[[T2]]
-; MIPS32: sra {{.*}},[[VAL_HI]],0x4
-
-define internal i64 @ashrImm64Equal32(i64 %val) {
-entry:
- %result = ashr i64 %val, 32
- ret i64 %result
-}
-; CHECK-LABEL: ashrImm64Equal32
-; CHECK: sar {{.*}},0x1f
-; CHECK-NOT: shrd
-; MIPS32-LABEL: ashrImm64Equal32
-; MIPS32: sra {{.*}},[[VAL_HI:.*]],0x1f
-; MIPS32-O2: move {{.*}},[[VAL_HI]]
-; MIPS32-OM1: sw [[VAL_HI]],{{.*}}
-; MIPS32-OM1: lw {{.*}},{{.*}}
-
-define internal i64 @ashrImm64GreaterThan32(i64 %val) {
-entry:
- %result = ashr i64 %val, 40
- ret i64 %result
-}
-; CHECK-LABEL: ashrImm64GreaterThan32
-; CHECK: sar {{.*}},0x1f
-; CHECK: shrd {{.*}},0x8
-; MIPS32-LABEL: ashrImm64GreaterThan32
-; MIPS32: sra {{.*}},[[VAL_HI:.*]],0x8
-; MIPS32: sra {{.*}},[[VAL_HI]],0x1f
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/short-circuit.ll b/third_party/subzero/tests_lit/llvm2ice_tests/short-circuit.ll
deleted file mode 100644
index df0e1a9..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/short-circuit.ll
+++ /dev/null
@@ -1,42 +0,0 @@
-; Test on -enable-sc if basic blocks are split when short circuit evaluation
-; is possible for boolean expressions
-
-; REQUIRES: allow_dump
-
-; RUN: %p2i -i %s --filetype=asm --target x8632 --args \
-; RUN: -O2 -enable-sc | FileCheck %s --check-prefix=ENABLE \
-; RUN: --check-prefix=CHECK
-
-; RUN: %p2i -i %s --filetype=asm --target x8632 --args \
-; RUN: -O2 | FileCheck %s --check-prefix=NOENABLE \
-; RUN: --check-prefix=CHECK
-
-define internal i32 @short_circuit(i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4,
- i32 %arg5) {
- %t0 = trunc i32 %arg1 to i1
- %t1 = trunc i32 %arg2 to i1
- %t2 = trunc i32 %arg3 to i1
- %t3 = trunc i32 %arg4 to i1
- %t4 = trunc i32 %arg5 to i1
-
- %t5 = or i1 %t0, %t1
- %t6 = and i1 %t5, %t2
- %t7 = and i1 %t3, %t4
- %t8 = or i1 %t6, %t7
-
- br i1 %t8, label %target_true, label %target_false
-
-target_true:
- ret i32 1
-
-target_false:
- ret i32 0
-}
-
-; CHECK-LABEL: short_circuit
-; NOENABLE: .Lshort_circuit$__0:
-; ENABLE: .Lshort_circuit$__0_1_1:
-; ENABLE: .Lshort_circuit$__0_1_2:
-; ENABLE: .Lshort_circuit$__0_2:
-; CHECK: .Lshort_circuit$target_true:
-; CHECK: .Lshort_circuit$target_false:
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/simple-loop.ll b/third_party/subzero/tests_lit/llvm2ice_tests/simple-loop.ll
deleted file mode 100644
index 95cb9b8..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/simple-loop.ll
+++ /dev/null
@@ -1,50 +0,0 @@
-; This tests a simple loop that sums the elements of an input array.
-; The O2 check patterns represent the best code currently achieved.
-
-; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 \
-; RUN: | FileCheck %s
-; RUN: %p2i -i %s --filetype=obj --disassemble --args -Om1 \
-; RUN: | FileCheck --check-prefix=OPTM1 %s
-
-define internal i32 @simple_loop(i32 %a, i32 %n) {
-entry:
- %cmp4 = icmp sgt i32 %n, 0
- br i1 %cmp4, label %for.body, label %for.end
-
-for.body:
- %i.06 = phi i32 [ %inc, %for.body ], [ 0, %entry ]
- %sum.05 = phi i32 [ %add, %for.body ], [ 0, %entry ]
- %gep_array = mul i32 %i.06, 4
- %gep = add i32 %a, %gep_array
- %__9 = inttoptr i32 %gep to i32*
- %v0 = load i32, i32* %__9, align 1
- %add = add i32 %v0, %sum.05
- %inc = add i32 %i.06, 1
- %cmp = icmp slt i32 %inc, %n
- br i1 %cmp, label %for.body, label %for.end
-
-for.end:
- %sum.0.lcssa = phi i32 [ 0, %entry ], [ %add, %for.body ]
- ret i32 %sum.0.lcssa
-}
-
-; CHECK-LABEL: simple_loop
-; CHECK: mov ecx,DWORD PTR [esp{{.*}}+0x{{[0-9a-f]+}}]
-; CHECK: cmp ecx,0x0
-; CHECK-NEXT: j{{le|g}} {{[0-9]}}
-
-; Check for the combination of address mode inference, register
-; allocation, and load/arithmetic fusing.
-; CHECK: [[L:[0-9a-f]+]]{{.*}} add e{{..}},DWORD PTR [e{{..}}+[[IREG:e..]]*4]
-; Check for incrementing of the register-allocated induction variable.
-; CHECK-NEXT: add [[IREG]],0x1
-; Check for comparing the induction variable against the loop size.
-; CHECK-NEXT: cmp [[IREG]],
-; CHECK-NEXT: jl [[L]]
-;
-; There's nothing remarkable under Om1 to test for, since Om1 generates
-; such atrocious code (by design).
-; OPTM1-LABEL: simple_loop
-; OPTM1: cmp {{.*}},0x0
-; OPTM1: setl
-; OPTM1: ret
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/square.ll b/third_party/subzero/tests_lit/llvm2ice_tests/square.ll
deleted file mode 100644
index 08e7d67..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/square.ll
+++ /dev/null
@@ -1,111 +0,0 @@
-; Test the a=b*b lowering sequence which can use a single temporary register
-; instead of two registers.
-
-; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
-; RUN: --target x8632 -i %s --args -O2 -mattr=sse4.1 \
-; RUN: | %if --need=target_X8632 --command FileCheck %s
-
-; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
-; RUN: --target x8632 -i %s --args -Om1 -mattr=sse4.1 \
-; RUN: | %if --need=target_X8632 --command FileCheck %s
-
-; RUN: %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command %p2i --filetype=asm --assemble --disassemble --target \
-; RUN: mips32 -i %s --args -O2 -allow-externally-defined-symbols \
-; RUN: | %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command FileCheck --check-prefix MIPS32 %s
-
-define internal float @Square_float(float %a) {
-entry:
- %result = fmul float %a, %a
- ret float %result
-}
-; CHECK-LABEL: Square_float
-; CHECK: mulss [[REG:xmm.]],[[REG]]
-; MIPS32-LABEL: Square_float
-; MIPS32: mov.s
-; MIPS32: mul.s
-
-define internal double @Square_double(double %a) {
-entry:
- %result = fmul double %a, %a
- ret double %result
-}
-; CHECK-LABEL: Square_double
-; CHECK: mulsd [[REG:xmm.]],[[REG]]
-; MIPS32-LABEL: Square_double
-; MIPS32: mov.d
-; MIPS32: mul.d
-
-define internal i32 @Square_i32(i32 %a) {
-entry:
- %result = mul i32 %a, %a
- ret i32 %result
-}
-; CHECK-LABEL: Square_i32
-; CHECK: imul [[REG:e..]],[[REG]]
-; MIPS32-LABEL: Square_i32
-; MIPS32: move
-; MIPS32: mul
-
-define internal i32 @Square_i16(i32 %a) {
-entry:
- %a.16 = trunc i32 %a to i16
- %result = mul i16 %a.16, %a.16
- %result.i32 = sext i16 %result to i32
- ret i32 %result.i32
-}
-; CHECK-LABEL: Square_i16
-; CHECK: imul [[REG:..]],[[REG]]
-; MIPS32-LABEL: Square_i16
-; MIPS32: move
-; MIPS32: mul
-; MIPS32: sll
-; MIPS32: sra
-
-define internal i32 @Square_i8(i32 %a) {
-entry:
- %a.8 = trunc i32 %a to i8
- %result = mul i8 %a.8, %a.8
- %result.i32 = sext i8 %result to i32
- ret i32 %result.i32
-}
-; CHECK-LABEL: Square_i8
-; CHECK: imul al
-; MIPS32-LABEL: Square_i8
-; MIPS32: move
-; MIPS32: mul
-; MIPS32: sll
-; MIPS32: sra
-
-define internal <4 x float> @Square_v4f32(<4 x float> %a) {
-entry:
- %result = fmul <4 x float> %a, %a
- ret <4 x float> %result
-}
-; CHECK-LABEL: Square_v4f32
-; CHECK: mulps [[REG:xmm.]],[[REG]]
-
-define internal <4 x i32> @Square_v4i32(<4 x i32> %a) {
-entry:
- %result = mul <4 x i32> %a, %a
- ret <4 x i32> %result
-}
-; CHECK-LABEL: Square_v4i32
-; CHECK: pmulld [[REG:xmm.]],[[REG]]
-
-define internal <8 x i16> @Square_v8i16(<8 x i16> %a) {
-entry:
- %result = mul <8 x i16> %a, %a
- ret <8 x i16> %result
-}
-; CHECK-LABEL: Square_v8i16
-; CHECK: pmullw [[REG:xmm.]],[[REG]]
-
-define internal <16 x i8> @Square_v16i8(<16 x i8> %a) {
-entry:
- %result = mul <16 x i8> %a, %a
- ret <16 x i8> %result
-}
-; CHECK-LABEL: Square_v16i8
-; CHECK-NOT: pmul
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/store.ll b/third_party/subzero/tests_lit/llvm2ice_tests/store.ll
deleted file mode 100644
index c0550cc..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/store.ll
+++ /dev/null
@@ -1,104 +0,0 @@
-; Simple test of the store instruction.
-
-; REQUIRES: allow_dump
-
-; RUN: %p2i -i %s --args --verbose inst -threads=0 | FileCheck %s
-
-; RUN: %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command %p2i --filetype=asm --assemble \
-; RUN: --disassemble --target mips32 -i %s --args -O2 \
-; RUN: -allow-externally-defined-symbols \
-; RUN: | %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command FileCheck --check-prefix MIPS32 %s
-
-define internal void @store_i64(i32 %addr_arg) {
-entry:
- %__1 = inttoptr i32 %addr_arg to i64*
- store i64 1, i64* %__1, align 1
- ret void
-
-; CHECK: Initial CFG
-; CHECK: entry:
-; CHECK-NEXT: store i64 1, i64* %addr_arg, align 1
-; CHECK-NEXT: ret void
-}
-; MIPS32-LABEL: store_i64
-; MIPS32: li
-; MIPS32: li
-; MIPS32: sw
-; MIPS32: sw
-
-define internal void @store_i32(i32 %addr_arg) {
-entry:
- %__1 = inttoptr i32 %addr_arg to i32*
- store i32 1, i32* %__1, align 1
- ret void
-
-; CHECK: Initial CFG
-; CHECK: entry:
-; CHECK-NEXT: store i32 1, i32* %addr_arg, align 1
-; CHECK-NEXT: ret void
-}
-; MIPS32-LABEL: store_i32
-; MIPS32: li
-; MIPS32: sw
-
-define internal void @store_i16(i32 %addr_arg) {
-entry:
- %__1 = inttoptr i32 %addr_arg to i16*
- store i16 1, i16* %__1, align 1
- ret void
-
-; CHECK: Initial CFG
-; CHECK: entry:
-; CHECK-NEXT: store i16 1, i16* %addr_arg, align 1
-; CHECK-NEXT: ret void
-}
-; MIPS32-LABEL: store_i16
-; MIPS32: li
-; MIPS32: sh
-
-define internal void @store_i8(i32 %addr_arg) {
-entry:
- %__1 = inttoptr i32 %addr_arg to i8*
- store i8 1, i8* %__1, align 1
- ret void
-
-; CHECK: Initial CFG
-; CHECK: entry:
-; CHECK-NEXT: store i8 1, i8* %addr_arg, align 1
-; CHECK-NEXT: ret void
-}
-; MIPS32-LABEL: store_i8
-; MIPS32: li
-; MIPS32: sb
-
-define internal void @store_f32(float* %faddr_arg) {
-entry:
- store float 1.000000e+00, float* %faddr_arg, align 4
- ret void
-
-; CHECK: Initial CFG
-; CHECK: entry:
-; CHECK-NEXT: store float 1.000000e+00, float* %faddr_arg, align 4
-; CHECK-NEXT: ret void
-}
-; MIPS32-LABEL: store_f32
-; MIPS32: lui
-; MIPS32: lwc1
-; MIPS32: swc1
-
-define internal void @store_f64(double* %daddr_arg) {
-entry:
- store double 1.000000e+00, double* %daddr_arg, align 8
- ret void
-
-; CHECK: Initial CFG
-; CHECK: entry:
-; CHECK-NEXT: store double 1.000000e+00, double* %daddr_arg, align 8
-; CHECK-NEXT: ret void
-}
-; MIPS32-LABEL: store_f64
-; MIPS32: lui
-; MIPS32: ldc1
-; MIPS32: sdc1
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/strength-reduce.ll b/third_party/subzero/tests_lit/llvm2ice_tests/strength-reduce.ll
deleted file mode 100644
index 09188f7..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/strength-reduce.ll
+++ /dev/null
@@ -1,71 +0,0 @@
-; This tests various strength reduction operations.
-
-; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
-; RUN: --target x8632 -i %s --args -O2 \
-; RUN: | %if --need=target_X8632 --command FileCheck %s
-
-define internal i32 @mul_i32_arg_5(i32 %arg) {
- %result = mul i32 %arg, 5
- ret i32 %result
-}
-; CHECK-LABEL: mul_i32_arg_5
-; CHECK: lea [[REG:e..]],{{\[}}[[REG]]+[[REG]]*4]
-
-define internal i32 @mul_i32_5_arg(i32 %arg) {
- %result = mul i32 5, %arg
- ret i32 %result
-}
-; CHECK-LABEL: mul_i32_5_arg
-; CHECK: lea [[REG:e..]],{{\[}}[[REG]]+[[REG]]*4]
-
-define internal i32 @mul_i32_arg_18(i32 %arg) {
- %result = mul i32 %arg, 18
- ret i32 %result
-}
-; CHECK-LABEL: mul_i32_arg_18
-; CHECK-DAG: lea [[REG:e..]],{{\[}}[[REG]]+[[REG]]*8]
-; CHECK-DAG: shl [[REG]],1
-
-define internal i32 @mul_i32_arg_27(i32 %arg) {
- %result = mul i32 %arg, 27
- ret i32 %result
-}
-; CHECK-LABEL: mul_i32_arg_27
-; CHECK-DAG: lea [[REG:e..]],{{\[}}[[REG]]+[[REG]]*2]
-; CHECK-DAG: lea [[REG]],{{\[}}[[REG]]+[[REG]]*8]
-
-define internal i32 @mul_i32_arg_m45(i32 %arg) {
- %result = mul i32 %arg, -45
- ret i32 %result
-}
-; CHECK-LABEL: mul_i32_arg_m45
-; CHECK-DAG: lea [[REG:e..]],{{\[}}[[REG]]+[[REG]]*8]
-; CHECK-DAG: lea [[REG]],{{\[}}[[REG]]+[[REG]]*4]
-; CHECK: neg [[REG]]
-
-define internal i32 @mul_i16_arg_18(i32 %arg) {
- %arg.16 = trunc i32 %arg to i16
- %result = mul i16 %arg.16, 18
- %result.i32 = zext i16 %result to i32
- ret i32 %result.i32
-}
-; CHECK-LABEL: mul_i16_arg_18
-; CHECK: imul
-
-define internal i32 @mul_i8_arg_16(i32 %arg) {
- %arg.8 = trunc i32 %arg to i8
- %result = mul i8 %arg.8, 16
- %result.i32 = zext i8 %result to i32
- ret i32 %result.i32
-}
-; CHECK-LABEL: mul_i8_arg_16
-; CHECK: shl {{.*}},0x4
-
-define internal i32 @mul_i8_arg_18(i32 %arg) {
- %arg.8 = trunc i32 %arg to i8
- %result = mul i8 %arg.8, 18
- %result.i32 = zext i8 %result to i32
- ret i32 %result.i32
-}
-; CHECK-LABEL: mul_i8_arg_18
-; CHECK: imul
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/struct-arith.pnacl.ll b/third_party/subzero/tests_lit/llvm2ice_tests/struct-arith.pnacl.ll
deleted file mode 100644
index acab66b..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/struct-arith.pnacl.ll
+++ /dev/null
@@ -1,48 +0,0 @@
-; This test is lowered from C code that does some simple aritmetic
-; with struct members.
-
-; REQUIRES: allow_dump
-; RUN: %p2i -i %s --args --verbose inst -threads=0 | FileCheck %s
-
-define internal i32 @compute_important_function(i32 %v1, i32 %v2) {
-entry:
- %__2 = inttoptr i32 %v1 to i32*
- %_v0 = load i32, i32* %__2, align 1
-
-; CHECK: entry:
-; CHECK-NEXT: %_v0 = load i32, i32* {{.*}}, align 1
-
- %__4 = inttoptr i32 %v2 to i32*
- %_v1 = load i32, i32* %__4, align 1
- %gep = add i32 %v2, 12
- %__7 = inttoptr i32 %gep to i32*
- %_v2 = load i32, i32* %__7, align 1
- %mul = mul i32 %_v2, %_v1
- %gep6 = add i32 %v1, 4
- %__11 = inttoptr i32 %gep6 to i32*
- %_v3 = load i32, i32* %__11, align 1
- %gep8 = add i32 %v2, 8
- %__14 = inttoptr i32 %gep8 to i32*
- %_v4 = load i32, i32* %__14, align 1
- %gep10 = add i32 %v2, 4
- %__17 = inttoptr i32 %gep10 to i32*
- %_v5 = load i32, i32* %__17, align 1
- %mul3 = mul i32 %_v5, %_v4
- %gep12 = add i32 %v1, 8
- %__21 = inttoptr i32 %gep12 to i32*
- %_v6 = load i32, i32* %__21, align 1
- %mul7 = mul i32 %_v6, %_v3
- %mul9 = mul i32 %mul7, %_v6
- %gep14 = add i32 %v1, 12
- %__26 = inttoptr i32 %gep14 to i32*
- %_v7 = load i32, i32* %__26, align 1
- %mul11 = mul i32 %mul9, %_v7
- %add4.neg = add i32 %mul, %_v0
- %add = sub i32 %add4.neg, %_v3
- %sub = sub i32 %add, %mul3
- %sub12 = sub i32 %sub, %mul11
- ret i32 %sub12
-
-; CHECK: %sub12 = sub i32 %sub, %mul11
-; CHECK-NEXT: ret i32 %sub12
-}
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/switch-opt.ll b/third_party/subzero/tests_lit/llvm2ice_tests/switch-opt.ll
deleted file mode 100644
index 255bfe66..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/switch-opt.ll
+++ /dev/null
@@ -1,241 +0,0 @@
-; This tests a switch statement, including multiple branches to the
-; same label which also results in phi instructions with multiple
-; entries for the same incoming edge.
-
-; For x86 see adv-switch-opt.ll
-
-; TODO(jvoung): Update to -02 once the phi assignments is done for ARM
-; RUN: %if --need=target_ARM32 \
-; RUN: --command %p2i --filetype=obj --disassemble \
-; RUN: --target arm32 -i %s --args -Om1 \
-; RUN: | %if --need=target_ARM32 \
-; RUN: --command FileCheck --check-prefix ARM32 %s
-
-; RUN: %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command %p2i --filetype=asm --assemble --disassemble \
-; RUN: --target mips32 -i %s --args -Om1 \
-; RUN: -allow-externally-defined-symbols \
-; RUN: | %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command FileCheck --check-prefix MIPS32 %s
-
-define internal i32 @testSwitch(i32 %a) {
-entry:
- switch i32 %a, label %sw.default [
- i32 1, label %sw.epilog
- i32 2, label %sw.epilog
- i32 3, label %sw.epilog
- i32 7, label %sw.bb1
- i32 8, label %sw.bb1
- i32 15, label %sw.bb2
- i32 14, label %sw.bb2
- ]
-
-sw.default: ; preds = %entry
- %add = add i32 %a, 27
- br label %sw.epilog
-
-sw.bb1: ; preds = %entry, %entry
- %phitmp = sub i32 21, %a
- br label %sw.bb2
-
-sw.bb2: ; preds = %sw.bb1, %entry, %entry
- %result.0 = phi i32 [ 1, %entry ], [ 1, %entry ], [ %phitmp, %sw.bb1 ]
- br label %sw.epilog
-
-sw.epilog: ; preds = %sw.bb2, %sw.default, %entry, %entry, %entry
- %result.1 = phi i32 [ %add, %sw.default ], [ %result.0, %sw.bb2 ], [ 17, %entry ], [ 17, %entry ], [ 17, %entry ]
- ret i32 %result.1
-}
-
-; MIPS32-LABEL: testSwitch
-; MIPS32: li {{.*}},1
-; MIPS32: li {{.*}},17
-; MIPS32: li {{.*}},1
-; MIPS32: beq {{.*}},{{.*}},{{.*}} <[[SW_EPILOG:.*]]>
-; MIPS32: li {{.*}},2
-; MIPS32: beq {{.*}},{{.*}},{{.*}} <[[SW_EPILOG]]>
-; MIPS32: li {{.*}},3
-; MIPS32: beq {{.*}},{{.*}},{{.*}} <[[SW_EPILOG]]>
-; MIPS32: li {{.*}},7
-; MIPS32: beq {{.*}},{{.*}},{{.*}} <[[SW_BB1:.*]]>
-; MIPS32: li {{.*}},8
-; MIPS32: beq {{.*}},{{.*}},{{.*}} <[[SW_BB1]]>
-; MIPS32: li {{.*}},15
-; MIPS32: beq {{.*}},{{.*}},{{.*}} <[[SW_BB2:.*]]>
-; MIPS32: li {{.*}},14
-; MIPS32: beq {{.*}},{{.*}},{{.*}} <[[SW_BB2]]>
-; MIPS32: b {{.*}} <[[SW_DEFAULT:.*]]>
-; MIPS32: <[[SW_DEFAULT]]>
-; MIPS32: addiu {{.*}},27
-; MIPS32: b {{.*}} <[[SW_EPILOG]]>
-; MIPS32: <[[SW_BB1]]>
-; MIPS32: li {{.*}},21
-; MIPS32: b {{.*}} <[[SW_BB2]]>
-; MIPS32: <[[SW_BB2]]>
-; MIPS32: b {{.*}} <[[SW_EPILOG]]>
-; MIPS32: <[[SW_EPILOG]]>
-; MIPS32: jr ra
-
-; Check for a valid addressing mode when the switch operand is an
-; immediate. It's important that there is exactly one case, because
-; for two or more cases the source operand is legalized into a
-; register.
-define internal i32 @testSwitchImm() {
-entry:
- switch i32 10, label %sw.default [
- i32 1, label %sw.default
- ]
-
-sw.default:
- ret i32 20
-}
-; ARM32-LABEL: testSwitchImm
-; ARM32: cmp {{r[0-9]+}}, #1
-; ARM32-NEXT: beq
-; ARM32-NEXT: b
-
-; MIPS32-LABEL: testSwitchImm
-; MIPS32: li {{.*}},10
-; MIPS32: li {{.*}},1
-; MIPS32: beq {{.*}},{{.*}},{{.*}} <.LtestSwitchImm$sw.default>
-; MIPS32: .LtestSwitchImm$sw.default
-; MIPS32: li v0,20
-; MIPS32: jr ra
-
-; Test for correct 64-bit lowering.
-define internal i32 @testSwitch64(i64 %a) {
-entry:
- switch i64 %a, label %sw.default [
- i64 123, label %return
- i64 234, label %sw.bb1
- i64 345, label %sw.bb2
- i64 78187493520, label %sw.bb3
- ]
-
-sw.bb1: ; preds = %entry
- br label %return
-
-sw.bb2: ; preds = %entry
- br label %return
-
-sw.bb3: ; preds = %entry
- br label %return
-
-sw.default: ; preds = %entry
- br label %return
-
-return: ; preds = %sw.default, %sw.bb3, %sw.bb2, %sw.bb1, %entry
- %retval.0 = phi i32 [ 5, %sw.default ], [ 4, %sw.bb3 ], [ 3, %sw.bb2 ], [ 2, %sw.bb1 ], [ 1, %entry ]
- ret i32 %retval.0
-}
-; ARM32-LABEL: testSwitch64
-; ARM32: cmp {{r[0-9]+}}, #123
-; ARM32-NEXT: cmpeq {{r[0-9]+}}, #0
-; ARM32-NEXT: beq
-; ARM32: cmp {{r[0-9]+}}, #234
-; ARM32-NEXT: cmpeq {{r[0-9]+}}, #0
-; ARM32-NEXT: beq
-; ARM32: movw [[REG:r[0-9]+]], #345
-; ARM32-NEXT: cmp {{r[0-9]+}}, [[REG]]
-; ARM32-NEXT: cmpeq {{r[0-9]+}}, #0
-; ARM32-NEXT: beq
-; ARM32: movw [[REG:r[0-9]+]], #30864
-; ARM32-NEXT: movt [[REG]], #13398
-; ARM32-NEXT: cmp {{r[0-9]+}}, [[REG]]
-; ARM32-NEXT: cmpeq {{r[0-9]+}}, #18
-; ARM32-NEXT: beq
-; ARM32-NEXT: b
-
-; MIPS32-LABEL: testSwitch64
-; MIPS32: bne {{.*}},{{.*}},{{.*}} <.LtestSwitch64$local$__0>
-; MIPS32: li {{.*}},123
-; MIPS32: beq {{.*}},{{.*}},{{.*}} <.LtestSwitch64$return>
-; MIPS32: .LtestSwitch64$local$__0
-; MIPS32: li {{.*}},0
-; MIPS32: bne {{.*}},{{.*}},{{.*}} <.LtestSwitch64$local$__1>
-; MIPS32: li {{.*}},234
-; MIPS32: beq {{.*}},{{.*}},{{.*}} <.LtestSwitch64$sw.bb1>
-; MIPS32: .LtestSwitch64$local$__1
-; MIPS32: li {{.*}},0
-; MIPS32: bne {{.*}},{{.*}},{{.*}} <.LtestSwitch64$local$__2>
-; MIPS32: li {{.*}},345
-; MIPS32: beq {{.*}},{{.*}},{{.*}} <.LtestSwitch64$sw.bb2>
-; MIPS32: .LtestSwitch64$local$__2
-; MIPS32: li {{.*}},18
-; MIPS32: bne {{.*}},{{.*}},{{.*}} <.LtestSwitch64$local$__3>
-; MIPS32: lui {{.*}},0x3456
-; MIPS32: ori {{.*}},{{.*}},0x7890
-; MIPS32: beq {{.*}},{{.*}},{{.*}} <.LtestSwitch64$sw.bb3>
-; MIPS32: .LtestSwitch64$local$__3
-; MIPS32: b {{.*}} <.LtestSwitch64$sw.default>
-; MIPS32: .LtestSwitch64$sw.bb1
-; MIPS32: li {{.*}},2
-; MIPS32: b {{.*}} <.LtestSwitch64$return>
-; MIPS32: .LtestSwitch64$sw.bb2
-; MIPS32: li {{.*}},3
-; MIPS32: b {{.*}} <.LtestSwitch64$return>
-; MIPS32: .LtestSwitch64$sw.bb3
-; MIPS32: li {{.*}},4
-; MIPS32: b {{.*}} <.LtestSwitch64$return>
-; MIPS32: .LtestSwitch64$sw.default
-; MIPS32: li {{.*}},5
-; MIPS32: b {{.*}} <.LtestSwitch64$return>
-; MIPS32: .LtestSwitch64$return
-; MIPS32: jr ra
-
-; Similar to testSwitchImm, make sure proper addressing modes are
-; used. In reality, this is tested by running the output through the
-; assembler.
-define internal i32 @testSwitchImm64() {
-entry:
- switch i64 10, label %sw.default [
- i64 1, label %sw.default
- ]
-
-sw.default:
- ret i32 20
-}
-; ARM32-LABEL: testSwitchImm64
-; ARM32: cmp {{r[0-9]+}}, #1
-; ARM32-NEXT: cmpeq {{r[0-9]+}}, #0
-; ARM32-NEXT: beq [[ADDR:[0-9a-f]+]]
-; ARM32-NEXT: b [[ADDR]]
-
-; MIPS32-LABEL: testSwitchImm64
-; MIPS32: li {{.*}},10
-; MIPS32: li {{.*}},0
-; MIPS32: li {{.*}},0
-; MIPS32: bne {{.*}},{{.*}},{{.*}} <.LtestSwitchImm64$local$__0>
-; MIPS32: li {{.*}},1
-; MIPS32: beq {{.*}},{{.*}},{{.*}} <.LtestSwitchImm64$sw.default>
-; MIPS32: .LtestSwitchImm64$local$__0
-; MIPS32: b {{.*}} <.LtestSwitchImm64$sw.default>
-; MIPS32: .LtestSwitchImm64$sw.default
-; MIPS32: li {{.*}},20
-; MIPS32: jr ra
-
-define internal i32 @testSwitchUndef64() {
-entry:
- switch i64 undef, label %sw.default [
- i64 1, label %sw.default
- ]
-
-sw.default:
- ret i32 20
-}
-; ARM32-LABEL: testSwitchUndef64
-; ARM32: mov {{.*}}, #0
-; ARM32: mov {{.*}}, #0
-
-; MIPS32-LABEL: testSwitchUndef64
-; MIPS32: li {{.*}},0
-; MIPS32: li {{.*}},0
-; MIPS32: li {{.*}},0
-; MIPS32: bne {{.*}},{{.*}},{{.*}} <.LtestSwitchUndef64$local$__0>
-; MIPS32: li {{.*}},1
-; MIPS32: beq {{.*}},{{.*}},{{.*}} <.LtestSwitchUndef64$sw.default>
-; MIPS32: .LtestSwitchUndef64$local$__0
-; MIPS32: b {{.*}} <.LtestSwitchUndef64$sw.default>
-; MIPS32: .LtestSwitchUndef64$sw.default
-; MIPS32: li {{.*}},20
-; MIPS32: jr ra
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/test_i1.ll b/third_party/subzero/tests_lit/llvm2ice_tests/test_i1.ll
deleted file mode 100644
index 13d6b51..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/test_i1.ll
+++ /dev/null
@@ -1,348 +0,0 @@
-; Tests various aspects of i1 related lowering.
-
-; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
-; RUN: --target x8632 -i %s --args -O2 \
-; RUN: | %if --need=target_X8632 --command FileCheck %s
-
-; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
-; RUN: --target x8632 -i %s --args -Om1 \
-; RUN: | %if --need=target_X8632 --command FileCheck %s
-
-; TODO(jpp): Switch to --filetype=obj when possible.
-; RUN: %if --need=target_ARM32 --need=allow_dump \
-; RUN: --command %p2i --filetype=asm --assemble \
-; RUN: --disassemble --target arm32 -i %s --args -O2 \
-; RUN: | %if --need=target_ARM32 --need=allow_dump \
-; RUN: --command FileCheck --check-prefix ARM32 %s
-
-; RUN: %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command %p2i --filetype=asm --assemble --disassemble --target \
-; RUN: mips32 -i %s --args -O2 -allow-externally-defined-symbols \
-; RUN: | %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command FileCheck --check-prefix MIPS32 %s
-
-; Test that and with true uses immediate 1, not -1.
-define internal i32 @testAndTrue(i32 %arg) {
-entry:
- %arg_i1 = trunc i32 %arg to i1
- %result_i1 = and i1 %arg_i1, true
- %result = zext i1 %result_i1 to i32
- ret i32 %result
-}
-; CHECK-LABEL: testAndTrue
-; CHECK: and {{.*}},0x1
-; ARM32-LABEL: testAndTrue
-; ARM32: and {{.*}}, #1
-; MIPS32-LABEL: testAndTrue
-; MIPS32: andi {{.*}},0x1
-
-; Test that or with true uses immediate 1, not -1.
-define internal i32 @testOrTrue(i32 %arg) {
-entry:
- %arg_i1 = trunc i32 %arg to i1
- %result_i1 = or i1 %arg_i1, true
- %result = zext i1 %result_i1 to i32
- ret i32 %result
-}
-; CHECK-LABEL: testOrTrue
-; CHECK: or {{.*}},0x1
-; ARM32-LABEL: testOrTrue
-; ARM32: orr {{.*}}, #1
-; MIPS32-LABEL: testOrTrue
-; MIPS32: ori {{.*}},0x1
-
-; Test that xor with true uses immediate 1, not -1.
-define internal i32 @testXorTrue(i32 %arg) {
-entry:
- %arg_i1 = trunc i32 %arg to i1
- %result_i1 = xor i1 %arg_i1, true
- %result = zext i1 %result_i1 to i32
- ret i32 %result
-}
-; CHECK-LABEL: testXorTrue
-; CHECK: xor {{.*}},0x1
-; ARM32-LABEL: testXorTrue
-; ARM32: eor {{.*}}, #1
-; MIPS32-LABEL: testXorTrue
-; MIPS32: xori {{.*}},0x1
-
-; Test that trunc to i1 masks correctly.
-define internal i32 @testTrunc(i32 %arg) {
-entry:
- %arg_i1 = trunc i32 %arg to i1
- %result = zext i1 %arg_i1 to i32
- ret i32 %result
-}
-; CHECK-LABEL: testTrunc
-; CHECK: and {{.*}},0x1
-; ARM32-LABEL: testTrunc
-; ARM32: and {{.*}}, #1
-; MIPS32-LABEL: testTrunc
-; MIPS32: andi {{.*}},0x1
-
-; Test zext to i8.
-define internal i32 @testZextI8(i32 %arg) {
-entry:
- %arg_i1 = trunc i32 %arg to i1
- %result_i8 = zext i1 %arg_i1 to i8
- %result = zext i8 %result_i8 to i32
- ret i32 %result
-}
-; CHECK-LABEL: testZextI8
-; match the trunc instruction
-; CHECK: and {{.*}},0x1
-; match the zext i1 instruction (NOTE: no mov need between i1 and i8).
-; CHECK-NOT: and {{.*}},0x1
-; ARM32-LABEL: testZextI8
-; ARM32: {{.*}}, #1
-; ARM32: uxtb
-; MIPS32-LABEL: testZextI8
-; MIPS32: andi {{.*}},0x1
-; MIPS32: andi {{.*}},0xff
-
-; Test zext to i16.
-define internal i32 @testZextI16(i32 %arg) {
-entry:
- %arg_i1 = trunc i32 %arg to i1
- %result_i16 = zext i1 %arg_i1 to i16
- %result = zext i16 %result_i16 to i32
- ret i32 %result
-}
-; CHECK-LABEL: testZextI16
-; match the trunc instruction
-; CHECK: and {{.*}},0x1
-; match the zext i1 instruction (note 32-bit reg is used because it's shorter).
-; CHECK: movzx [[REG:e.*]],{{[a-d]l|BYTE PTR}}
-; CHECK-NOT: and [[REG]],0x1
-
-; ARM32-LABEL: testZextI16
-; ARM32: and {{.*}}, #1
-; ARM32: uxth
-
-; MIPS32-LABEL: testZextI16
-; MIPS32: andi {{.*}},0x1
-; MIPS32: andi {{.*}},0xffff
-
-; Test zext to i32.
-define internal i32 @testZextI32(i32 %arg) {
-entry:
- %arg_i1 = trunc i32 %arg to i1
- %result_i32 = zext i1 %arg_i1 to i32
- ret i32 %result_i32
-}
-; CHECK-LABEL: testZextI32
-; match the trunc instruction
-; CHECK: and {{.*}},0x1
-; match the zext i1 instruction
-; CHECK: movzx
-; CHECK-NOT: and {{.*}},0x1
-; ARM32-LABEL: testZextI32
-; ARM32: and {{.*}}, #1
-; MIPS32-LABEL: testZextI32
-; MIPS32: andi {{.*}},0x1
-
-; Test zext to i64.
-define internal i64 @testZextI64(i32 %arg) {
-entry:
- %arg_i1 = trunc i32 %arg to i1
- %result_i64 = zext i1 %arg_i1 to i64
- ret i64 %result_i64
-}
-; CHECK-LABEL: testZextI64
-; match the trunc instruction
-; CHECK: and {{.*}},0x1
-; match the zext i1 instruction
-; CHECK: movzx
-; CHECK: mov {{.*}},0x0
-; ARM32-LABEL: testZextI64
-; ARM32: and {{.*}}, #1
-; ARM32: mov {{.*}}, #0
-; MIPS32-LABEL: testZextI64
-; MIPS32: andi {{.*}},0x1
-; MIPS32: li {{.*}},0
-; MIPS32: move
-; MIPS32: move
-
-; Test sext to i8.
-define internal i32 @testSextI8(i32 %arg) {
-entry:
- %arg_i1 = trunc i32 %arg to i1
- %result_i8 = sext i1 %arg_i1 to i8
- %result = sext i8 %result_i8 to i32
- ret i32 %result
-}
-; CHECK-LABEL: testSextI8
-; match the trunc instruction
-; CHECK: and {{.*}},0x1
-; match the sext i1 instruction
-; CHECK: shl [[REG:.*]],0x7
-; CHECK-NEXT: sar [[REG]],0x7
-;
-; ARM32-LABEL: testSextI8
-; ARM32: mov {{.*}}, #0
-; ARM32: tst {{.*}}, #1
-; ARM32: mvn {{.*}}, #0
-; ARM32: movne
-; ARM32: sxtb
-;
-; MIPS32-LABEL: testSextI8
-; MIPS32: sll {{.*}},0x1f
-; MIPS32: sra {{.*}},0x1f
-; MIPS32: sll {{.*}},0x18
-; MIPS32: sra {{.*}},0x18
-
-; Test sext to i16.
-define internal i32 @testSextI16(i32 %arg) {
-entry:
- %arg_i1 = trunc i32 %arg to i1
- %result_i16 = sext i1 %arg_i1 to i16
- %result = sext i16 %result_i16 to i32
- ret i32 %result
-}
-; CHECK-LABEL: testSextI16
-; match the trunc instruction
-; CHECK: and {{.*}},0x1
-; match the sext i1 instruction
-; CHECK: movzx {{e*}}[[REG:.*]],{{[a-d]l|BYTE PTR}}
-; CHECK-NEXT: shl [[REG]],0xf
-; CHECK-NEXT: sar [[REG]],0xf
-
-; ARM32-LABEL: testSextI16
-; ARM32: mov {{.*}}, #0
-; ARM32: tst {{.*}}, #1
-; ARM32: mvn {{.*}}, #0
-; ARM32: movne
-; ARM32: sxth
-
-; MIPS32-LABEL: testSextI16
-; MIPS32: sll {{.*}},0x1f
-; MIPS32: sra {{.*}},0x1f
-; MIPS32: sll {{.*}},0x10
-; MIPS32: sra {{.*}},0x10
-
-; Test sext to i32.
-define internal i32 @testSextI32(i32 %arg) {
-entry:
- %arg_i1 = trunc i32 %arg to i1
- %result_i32 = sext i1 %arg_i1 to i32
- ret i32 %result_i32
-}
-; CHECK-LABEL: testSextI32
-; match the trunc instruction
-; CHECK: and {{.*}},0x1
-; match the sext i1 instruction
-; CHECK: movzx [[REG:.*]],
-; CHECK-NEXT: shl [[REG]],0x1f
-; CHECK-NEXT: sar [[REG]],0x1f
-
-; ARM32-LABEL: testSextI32
-; ARM32: mov {{.*}}, #0
-; ARM32: tst {{.*}}, #1
-; ARM32: mvn {{.*}}, #0
-; ARM32: movne
-
-; MIPS32-LABEL: testSextI32
-; MIPS32: sll {{.*}},0x1f
-; MIPS32: sra {{.*}},0x1f
-
-; Test sext to i64.
-define internal i64 @testSextI64(i32 %arg) {
-entry:
- %arg_i1 = trunc i32 %arg to i1
- %result_i64 = sext i1 %arg_i1 to i64
- ret i64 %result_i64
-}
-; CHECK-LABEL: testSextI64
-; match the trunc instruction
-; CHECK: and {{.*}},0x1
-; match the sext i1 instruction
-; CHECK: movzx [[REG:.*]],
-; CHECK-NEXT: shl [[REG]],0x1f
-; CHECK-NEXT: sar [[REG]],0x1f
-
-; ARM32-LABEL: testSextI64
-; ARM32: mov {{.*}}, #0
-; ARM32: tst {{.*}}, #1
-; ARM32: mvn {{.*}}, #0
-; ARM32: movne [[REG:r[0-9]+]]
-; ARM32: mov {{.*}}, [[REG]]
-
-; MIPS32-LABEL: testSextI64
-; MIPS32: sll {{.*}},0x1f
-; MIPS32: sra {{.*}},0x1f
-; MIPS32: move
-; MIPS32: move
-
-; Kind of like sext i1 to i32, but with an immediate source. On ARM,
-; sxtb cannot take an immediate operand, so make sure it's using a reg.
-; If we had optimized constants, this could just be mov dst, 0xffffffff
-; or mvn dst, #0.
-define internal i32 @testSextTrue() {
- %result = sext i1 true to i32
- ret i32 %result
-}
-; CHECK-LABEL: testSextTrue
-; CHECK: movzx
-; CHECK-NEXT: shl
-; CHECK-NEXT: sar
-; ARM32-LABEL: testSextTrue
-; ARM32: mov {{.*}}, #0
-; ARM32: tst {{.*}}, #1
-; ARM32: mvn {{.*}}, #0
-; ARM32: movne
-; MIPS32-LABEL: testSextTrue
-; MIPS32: li {{.*}},1
-; MIPS32: sll {{.*}},0x1f
-; MIPS32: sra {{.*}},0x1f
-
-define internal i32 @testZextTrue() {
- %result = zext i1 true to i32
- ret i32 %result
-}
-; CHECK-LABEL: testZextTrue
-; CHECK: movzx
-; CHECK-NOT: and {{.*}},0x1
-; ARM32-LABEL: testZextTrue
-; ARM32: mov{{.*}}, #1
-; ARM32: and {{.*}}, #1
-; MIPS32-LABEL: testZextTrue
-; MIPS32: li {{.*}},1
-; MIPS32: andi {{.*}},0x1
-
-; Test fptosi float to i1.
-define internal i32 @testFptosiFloat(float %arg) {
-entry:
- %arg_i1 = fptosi float %arg to i1
- %result = sext i1 %arg_i1 to i32
- ret i32 %result
-}
-; CHECK-LABEL: testFptosiFloat
-; CHECK: cvttss2si
-; CHECK: and {{.*}},0x1
-; CHECK: movzx [[REG:.*]],
-; CHECK-NEXT: shl [[REG]],0x1f
-; CHECK-NEXT: sar [[REG]],0x1f
-; MIPS32-LABEL: testFptosiFloat
-; MIPS32: trunc.w.s
-; MIPS32: mfc1
-; MIPS32: sll {{.*}},0x1f
-; MIPS32: sra {{.*}},0x1f
-
-; Test fptosi double to i1.
-define internal i32 @testFptosiDouble(double %arg) {
-entry:
- %arg_i1 = fptosi double %arg to i1
- %result = sext i1 %arg_i1 to i32
- ret i32 %result
-}
-; CHECK-LABEL: testFptosiDouble
-; CHECK: cvttsd2si
-; CHECK: and {{.*}},0x1
-; CHECK: movzx [[REG:.*]],
-; CHECK-NEXT: shl [[REG]],0x1f
-; CHECK-NEXT: sar [[REG]],0x1f
-; MIPS32-LABEL: testFptosiDouble
-; MIPS32: trunc.w.d
-; MIPS32: mfc1
-; MIPS32: sll {{.*}},0x1f
-; MIPS32: sra {{.*}},0x1f
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/uncond_br.ll b/third_party/subzero/tests_lit/llvm2ice_tests/uncond_br.ll
deleted file mode 100644
index 4b1e091..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/uncond_br.ll
+++ /dev/null
@@ -1,26 +0,0 @@
-; TODO: Switch to --filetype=obj when possible.
-; RUN: %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command %p2i --filetype=asm --assemble \
-; RUN: --disassemble --target mips32 -i %s --args -O2 \
-; RUN: -allow-externally-defined-symbols \
-; RUN: | %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command FileCheck --check-prefix MIPS32 %s
-
-define internal void @uncond1(i32 %i) {
- %1 = alloca i8, i32 4, align 4
- %.bc = bitcast i8* %1 to i32*
- store i32 %i, i32* %.bc, align 1
- br label %target
-target:
- %.bc1 = bitcast i8* %1 to i32*
- %2 = load i32, i32* %.bc1, align 1
- %3 = add i32 %2, 1
- %.bc2 = bitcast i8* %1 to i32*
- store i32 %3, i32* %.bc2, align 1
- br label %target
-}
-
-; MIPS32-LABEL: uncond1
-; MIPS32: <.Luncond1$target>:
-; MIPS32: addiu {{.*}},1
-; MIPS32: b {{[0-9a-f]+}} <.Luncond1$target>
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/undef.ll b/third_party/subzero/tests_lit/llvm2ice_tests/undef.ll
deleted file mode 100644
index ba86d03..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/undef.ll
+++ /dev/null
@@ -1,311 +0,0 @@
-; This test checks that undef values are represented as zero.
-
-; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 \
-; RUN: | FileCheck %s
-; RUN: %p2i -i %s --filetype=obj --disassemble --args -Om1 \
-; RUN: | FileCheck %s
-; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 -mattr=sse4.1 \
-; RUN: | FileCheck %s
-; RUN: %p2i -i %s --filetype=obj --disassemble --args -Om1 -mattr=sse4.1 \
-; RUN: | FileCheck %s
-
-define internal i32 @undef_i32() {
-entry:
- ret i32 undef
-; CHECK-LABEL: undef_i32
-; CHECK: mov eax,0x0
-}
-
-define internal i64 @undef_i64() {
-entry:
- ret i64 undef
-; CHECK-LABEL: undef_i64
-; CHECK-DAG: mov eax,0x0
-; CHECK-DAG: mov edx,0x0
-; CHECK: ret
-}
-
-define internal i32 @trunc_undef_i64() {
-entry:
- %ret = trunc i64 undef to i32
- ret i32 %ret
-; CHECK-LABEL: trunc_undef_i64
-; CHECK: mov eax,0x0
-; CHECK: ret
-}
-
-define internal float @undef_float() {
-entry:
- ret float undef
-; CHECK-LABEL: undef_float
-; CHECK: xorps [[REG:xmm.]],[[REG]]
-; CHECK: fld
-}
-
-define internal double @undef_double() {
-entry:
- ret double undef
-; CHECK-LABEL: undef_double
-; CHECK: xorpd [[REG:xmm.]],[[REG]]
-; CHECK: fld
-}
-
-define internal <4 x i1> @undef_v4i1() {
-entry:
- ret <4 x i1> undef
-; CHECK-LABEL: undef_v4i1
-; CHECK: pxor
-}
-
-define internal <8 x i1> @undef_v8i1() {
-entry:
- ret <8 x i1> undef
-; CHECK-LABEL: undef_v8i1
-; CHECK: pxor
-}
-
-define internal <16 x i1> @undef_v16i1() {
-entry:
- ret <16 x i1> undef
-; CHECK-LABEL: undef_v16i1
-; CHECK: pxor
-}
-
-define internal <16 x i8> @undef_v16i8() {
-entry:
- ret <16 x i8> undef
-; CHECK-LABEL: undef_v16i8
-; CHECK: pxor
-}
-
-define internal <8 x i16> @undef_v8i16() {
-entry:
- ret <8 x i16> undef
-; CHECK-LABEL: undef_v8i16
-; CHECK: pxor
-}
-
-define internal <4 x i32> @undef_v4i32() {
-entry:
- ret <4 x i32> undef
-; CHECK-LABEL: undef_v4i32
-; CHECK: pxor
-}
-
-define internal <4 x float> @undef_v4f32() {
-entry:
- ret <4 x float> undef
-; CHECK-LABEL: undef_v4f32
-; CHECK: pxor
-}
-
-define internal <4 x i32> @vector_arith(<4 x i32> %arg) {
-entry:
- %val = add <4 x i32> undef, %arg
- ret <4 x i32> %val
-; CHECK-LABEL: vector_arith
-; CHECK: pxor
-}
-
-define internal <4 x float> @vector_bitcast() {
-entry:
- %val = bitcast <4 x i32> undef to <4 x float>
- ret <4 x float> %val
-; CHECK-LABEL: vector_bitcast
-; CHECK: pxor
-}
-
-define internal <4 x i32> @vector_sext() {
-entry:
- %val = sext <4 x i1> undef to <4 x i32>
- ret <4 x i32> %val
-; CHECK-LABEL: vector_sext
-; CHECK: pxor
-}
-
-define internal <4 x i32> @vector_zext() {
-entry:
- %val = zext <4 x i1> undef to <4 x i32>
- ret <4 x i32> %val
-; CHECK-LABEL: vector_zext
-; CHECK: pxor
-}
-
-define internal <4 x i1> @vector_trunc() {
-entry:
- %val = trunc <4 x i32> undef to <4 x i1>
- ret <4 x i1> %val
-; CHECK-LABEL: vector_trunc
-; CHECK: pxor
-}
-
-define internal <4 x i1> @vector_icmp(<4 x i32> %arg) {
-entry:
- %val = icmp eq <4 x i32> undef, %arg
- ret <4 x i1> %val
-; CHECK-LABEL: vector_icmp
-; CHECK: pxor
-}
-
-define internal <4 x i1> @vector_fcmp(<4 x float> %arg) {
-entry:
- %val = fcmp ueq <4 x float> undef, %arg
- ret <4 x i1> %val
-; CHECK-LABEL: vector_fcmp
-; CHECK: pxor
-}
-
-define internal <4 x i32> @vector_fptosi() {
-entry:
- %val = fptosi <4 x float> undef to <4 x i32>
- ret <4 x i32> %val
-; CHECK-LABEL: vector_fptosi
-; CHECK: pxor
-}
-
-define internal <4 x i32> @vector_fptoui() {
-entry:
- %val = fptoui <4 x float> undef to <4 x i32>
- ret <4 x i32> %val
-; CHECK-LABEL: vector_fptoui
-; CHECK: pxor
-}
-
-define internal <4 x float> @vector_sitofp() {
-entry:
- %val = sitofp <4 x i32> undef to <4 x float>
- ret <4 x float> %val
-; CHECK-LABEL: vector_sitofp
-; CHECK: pxor
-}
-
-define internal <4 x float> @vector_uitofp() {
-entry:
- %val = uitofp <4 x i32> undef to <4 x float>
- ret <4 x float> %val
-; CHECK-LABEL: vector_uitofp
-; CHECK: pxor
-}
-
-define internal <4 x float> @vector_insertelement_arg1() {
-entry:
- %val = insertelement <4 x float> undef, float 1.0, i32 0
- ret <4 x float> %val
-; CHECK-LABEL: vector_insertelement_arg1
-; CHECK: pxor
-}
-
-define internal <4 x float> @vector_insertelement_arg2(<4 x float> %arg) {
-entry:
- %val = insertelement <4 x float> %arg, float undef, i32 0
- ret <4 x float> %val
-; CHECK-LABEL: vector_insertelement_arg2
-; CHECK: xorps [[REG:xmm.]],[[REG]]
-; CHECK: {{movss|insertps}} {{.*}},[[REG]]
-}
-
-define internal float @vector_extractelement_v4f32_index_0() {
-entry:
- %val = extractelement <4 x float> undef, i32 0
- ret float %val
-; CHECK-LABEL: vector_extractelement_v4f32_index_0
-; CHECK: pxor
-}
-
-define internal float @vector_extractelement_v4f32_index_1() {
-entry:
- %val = extractelement <4 x float> undef, i32 1
- ret float %val
-; CHECK-LABEL: vector_extractelement_v4f32_index_1
-; CHECK: pxor
-}
-
-define internal i32 @vector_extractelement_v16i1_index_7() {
-entry:
- %val.trunc = extractelement <16 x i1> undef, i32 7
- %val = sext i1 %val.trunc to i32
- ret i32 %val
-; CHECK-LABEL: vector_extractelement_v16i1_index_7
-; CHECK: pxor
-}
-
-define internal <4 x i32> @vector_select_v4i32_cond(<4 x i32> %a,
- <4 x i32> %b) {
-entry:
- %val = select <4 x i1> undef, <4 x i32> %a, <4 x i32> %b
- ret <4 x i32> %val
-; CHECK-LABEL: vector_select_v4i32_cond
-; CHECK: pxor
-}
-
-define internal <4 x i32> @vector_select_v4i32_arg1(<4 x i1> %cond,
- <4 x i32> %b) {
-entry:
- %val = select <4 x i1> %cond, <4 x i32> undef, <4 x i32> %b
- ret <4 x i32> %val
-; CHECK-LABEL: vector_select_v4i32_arg1
-; CHECK: pxor
-}
-
-define internal <4 x i32> @vector_select_v4i32_arg2(<4 x i1> %cond,
- <4 x i32> %a) {
-entry:
- %val = select <4 x i1> %cond, <4 x i32> %a, <4 x i32> undef
- ret <4 x i32> %val
-; CHECK-LABEL: vector_select_v4i32_arg2
-; CHECK: pxor
-}
-
-define internal <4 x i1> @vector_select_v4i1_cond(<4 x i1> %a,
- <4 x i1> %b) {
-entry:
- %val = select <4 x i1> undef, <4 x i1> %a, <4 x i1> %b
- ret <4 x i1> %val
-; CHECK-LABEL: vector_select_v4i1_cond
-; CHECK: pxor
-}
-
-define internal <4 x i1> @vector_select_v4i1_arg1(<4 x i1> %cond,
- <4 x i1> %b) {
-entry:
- %val = select <4 x i1> %cond, <4 x i1> undef, <4 x i1> %b
- ret <4 x i1> %val
-; CHECK-LABEL: vector_select_v4i1_arg1
-; CHECK: pxor
-}
-
-define internal <4 x i1> @vector_select_v4i1_arg2(<4 x i1> %cond,
- <4 x i1> %a) {
-entry:
- %val = select <4 x i1> %cond, <4 x i1> %a, <4 x i1> undef
- ret <4 x i1> %val
-; CHECK-LABEL: vector_select_v4i1_arg2
-; CHECK: pxor
-}
-
-define internal <4 x float> @vector_select_v4f32_cond(<4 x float> %a,
- <4 x float> %b) {
-entry:
- %val = select <4 x i1> undef, <4 x float> %a, <4 x float> %b
- ret <4 x float> %val
-; CHECK-LABEL: vector_select_v4f32_cond
-; CHECK: pxor
-}
-
-define internal <4 x float> @vector_select_v4f32_arg1(<4 x i1> %cond,
- <4 x float> %b) {
-entry:
- %val = select <4 x i1> %cond, <4 x float> undef, <4 x float> %b
- ret <4 x float> %val
-; CHECK-LABEL: vector_select_v4f32_arg1
-; CHECK: pxor
-}
-
-define internal <4 x float> @vector_select_v4f32_arg2(<4 x i1> %cond,
- <4 x float> %a) {
-entry:
- %val = select <4 x i1> %cond, <4 x float> %a, <4 x float> undef
- ret <4 x float> %val
-; CHECK-LABEL: vector_select_v4f32_arg2
-; CHECK: pxor
-}
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/unknown-arm-reg.ll b/third_party/subzero/tests_lit/llvm2ice_tests/unknown-arm-reg.ll
deleted file mode 100644
index e25ea13..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/unknown-arm-reg.ll
+++ /dev/null
@@ -1,12 +0,0 @@
-; Show that we complain if an unknown register is specified on the command line.
-
-; Compile using standalone assembler.
-; RUN: %p2i --expect-fail --filetype=asm -i %s --target=arm32 --args -Om1 \
-; RUN: -reg-use r2,xx9x,r5,yy28 -reg-exclude s1,sq5 2>&1 \
-; RUN: | FileCheck %s
-
-define void @foo() {
- ret void
-}
-
-; CHECK: LLVM ERROR: Unrecognized use/exclude registers: xx9x yy28 sq5
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/unreachable.ll b/third_party/subzero/tests_lit/llvm2ice_tests/unreachable.ll
deleted file mode 100644
index b80b249..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/unreachable.ll
+++ /dev/null
@@ -1,69 +0,0 @@
-; This tests the basic structure of the Unreachable instruction.
-
-; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
-; RUN: --target x8632 -i %s --args -O2 \
-; RUN: | %if --need=target_X8632 --command FileCheck %s
-; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
-; RUN: --target x8632 -i %s --args -Om1 \
-; RUN: | %if --need=target_X8632 --command FileCheck %s
-
-; RUN: %if --need=target_ARM32 \
-; RUN: --command %p2i --filetype=obj \
-; RUN: --disassemble --target arm32 -i %s --args -O2 \
-; RUN: | %if --need=target_ARM32 \
-; RUN: --command FileCheck --check-prefix ARM32 %s
-; RUN: %if --need=target_ARM32 \
-; RUN: --command %p2i --filetype=obj \
-; RUN: --disassemble --target arm32 -i %s --args -Om1 \
-; RUN: | %if --need=target_ARM32 \
-; RUN: --command FileCheck --check-prefix ARM32 %s
-
-; RUN: %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command %p2i --filetype=asm --assemble \
-; RUN: --disassemble --target mips32 -i %s --args -Om1 \
-; RUN: | %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command FileCheck --check-prefix MIPS32 %s
-
-; RUN: %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command %p2i --filetype=asm --assemble \
-; RUN: --disassemble --target mips32 -i %s --args -O2 \
-; RUN: | %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command FileCheck --check-prefix MIPS32-O2 %s
-
-define internal i32 @divide(i32 %num, i32 %den) {
-entry:
- %cmp = icmp ne i32 %den, 0
- br i1 %cmp, label %return, label %abort
-
-abort: ; preds = %entry
- unreachable
-
-return: ; preds = %entry
- %div = sdiv i32 %num, %den
- ret i32 %div
-}
-
-; CHECK-LABEL: divide
-; CHECK: cmp
-; CHECK: ud2
-; CHECK: cdq
-; CHECK: idiv
-; CHECK: ret
-
-; ARM32-LABEL: divide
-; ARM32: tst
-; ARM32: e7fedef0
-; ARM32: bl {{.*}} __divsi3
-; ARM32: bx lr
-
-; MIPS32-LABEL: divide
-; MIPS32: beqz
-; MIPS32: nop
-; MIPS32: teq zero,zero
-; MIPS32: div
-
-; MIPS32-O2-LABEL: divide
-; MIPS32-O2: bne
-; MIPS32-O2: nop
-; MIPS32-O2: teq zero,zero
-; MIPS32-O2: div
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/vector-align.ll b/third_party/subzero/tests_lit/llvm2ice_tests/vector-align.ll
deleted file mode 100644
index e578725..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/vector-align.ll
+++ /dev/null
@@ -1,133 +0,0 @@
-; This test checks that when SSE instructions access memory and require full
-; alignment, memory operands are limited to properly aligned stack operands.
-; This would only happen when we fuse a load instruction with another
-; instruction, which currently only happens with non-scalarized Arithmetic
-; instructions.
-
-; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 | FileCheck %s
-; RUN: %p2i -i %s --filetype=obj --disassemble --args -Om1 | FileCheck %s
-
-; RUN: %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command %p2i --filetype=asm --assemble --disassemble --target mips32\
-; RUN: -i %s --args -O2 \
-; RUN: | %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command FileCheck --check-prefix MIPS32 %s
-
-define internal <4 x i32> @test_add(i32 %addr_i, <4 x i32> %addend) {
-entry:
- %addr = inttoptr i32 %addr_i to <4 x i32>*
- %loaded = load <4 x i32>, <4 x i32>* %addr, align 4
- %result = add <4 x i32> %addend, %loaded
- ret <4 x i32> %result
-}
-; CHECK-LABEL: test_add
-; CHECK-NOT: paddd xmm{{.}},XMMWORD PTR [e{{ax|cx|dx|di|si|bx|bp}}
-; CHECK: paddd xmm{{.}},
-
-; MIPS32-LABEL: test_add
-; MIPS32: addu
-; MIPS32: addu
-; MIPS32: addu
-; MIPS32: addu
-
-define internal <4 x i32> @test_and(i32 %addr_i, <4 x i32> %addend) {
-entry:
- %addr = inttoptr i32 %addr_i to <4 x i32>*
- %loaded = load <4 x i32>, <4 x i32>* %addr, align 4
- %result = and <4 x i32> %addend, %loaded
- ret <4 x i32> %result
-}
-; CHECK-LABEL: test_and
-; CHECK-NOT: pand xmm{{.}},XMMWORD PTR [e{{ax|cx|dx|di|si|bx|bp}}
-; CHECK: pand xmm{{.}},
-
-; MIPS32-LABEL: test_and
-; MIPS32: and
-; MIPS32: and
-; MIPS32: and
-; MIPS32: and
-
-define internal <4 x i32> @test_or(i32 %addr_i, <4 x i32> %addend) {
-entry:
- %addr = inttoptr i32 %addr_i to <4 x i32>*
- %loaded = load <4 x i32>, <4 x i32>* %addr, align 4
- %result = or <4 x i32> %addend, %loaded
- ret <4 x i32> %result
-}
-; CHECK-LABEL: test_or
-; CHECK-NOT: por xmm{{.}},XMMWORD PTR [e{{ax|cx|dx|di|si|bx|bp}}
-; CHECK: por xmm{{.}},
-
-; MIPS32-LABEL: test_or
-; MIPS32: or
-; MIPS32: or
-; MIPS32: or
-; MIPS32: or
-
-define internal <4 x i32> @test_xor(i32 %addr_i, <4 x i32> %addend) {
-entry:
- %addr = inttoptr i32 %addr_i to <4 x i32>*
- %loaded = load <4 x i32>, <4 x i32>* %addr, align 4
- %result = xor <4 x i32> %addend, %loaded
- ret <4 x i32> %result
-}
-; CHECK-LABEL: test_xor
-; CHECK-NOT: pxor xmm{{.}},XMMWORD PTR [e{{ax|cx|dx|di|si|bx|bp}}
-; CHECK: pxor xmm{{.}},
-
-; MIPS32-LABEL: test_xor
-; MIPS32: xor
-; MIPS32: xor
-; MIPS32: xor
-; MIPS32: xor
-
-define internal <4 x i32> @test_sub(i32 %addr_i, <4 x i32> %addend) {
-entry:
- %addr = inttoptr i32 %addr_i to <4 x i32>*
- %loaded = load <4 x i32>, <4 x i32>* %addr, align 4
- %result = sub <4 x i32> %addend, %loaded
- ret <4 x i32> %result
-}
-; CHECK-LABEL: test_sub
-; CHECK-NOT: psubd xmm{{.}},XMMWORD PTR [e{{ax|cx|dx|di|si|bx|bp}}
-; CHECK: psubd xmm{{.}},
-
-; MIPS32-LABEL: test_sub
-; MIPS32: subu
-; MIPS32: subu
-; MIPS32: subu
-; MIPS32: subu
-
-define internal <4 x float> @test_fadd(i32 %addr_i, <4 x float> %addend) {
-entry:
- %addr = inttoptr i32 %addr_i to <4 x float>*
- %loaded = load <4 x float>, <4 x float>* %addr, align 4
- %result = fadd <4 x float> %addend, %loaded
- ret <4 x float> %result
-}
-; CHECK-LABEL: test_fadd
-; CHECK-NOT: addps xmm{{.}},XMMWORD PTR [e{{ax|cx|dx|di|si|bx|bp}}
-; CHECK: addps xmm{{.}},
-
-; MIPS32-LABEL: test_fadd
-; MIPS32: add.s
-; MIPS32: add.s
-; MIPS32: add.s
-; MIPS32: add.s
-
-define internal <4 x float> @test_fsub(i32 %addr_i, <4 x float> %addend) {
-entry:
- %addr = inttoptr i32 %addr_i to <4 x float>*
- %loaded = load <4 x float>, <4 x float>* %addr, align 4
- %result = fsub <4 x float> %addend, %loaded
- ret <4 x float> %result
-}
-; CHECK-LABEL: test_fsub
-; CHECK-NOT: subps xmm{{.}},XMMWORD PTR [e{{ax|cx|dx|di|si|bx|bp}}
-; CHECK: subps xmm{{.}},
-
-; MIPS32-LABEL: test_fsub
-; MIPS32: sub.s
-; MIPS32: sub.s
-; MIPS32: sub.s
-; MIPS32: sub.s
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/vector-arg.ll b/third_party/subzero/tests_lit/llvm2ice_tests/vector-arg.ll
deleted file mode 100644
index df97e65..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/vector-arg.ll
+++ /dev/null
@@ -1,581 +0,0 @@
-; This file checks that Subzero generates code in accordance with the
-; calling convention for vectors.
-
-; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 \
-; RUN: -allow-externally-defined-symbols | FileCheck %s
-; RUN: %p2i -i %s --filetype=obj --disassemble --args -Om1 \
-; RUN: -allow-externally-defined-symbols | FileCheck --check-prefix=OPTM1 %s
-
-; RUN: %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command %p2i --filetype=asm --assemble --disassemble --target \
-; RUN: mips32 -i %s --args -O2 -allow-externally-defined-symbols \
-; RUN: | %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command FileCheck --check-prefix MIPS32 %s
-
-; The first five functions test that vectors are moved from their
-; correct argument location to xmm0.
-
-define internal <4 x float> @test_returning_arg0(
- <4 x float> %arg0, <4 x float> %arg1, <4 x float> %arg2, <4 x float> %arg3,
- <4 x float> %arg4, <4 x float> %arg5) {
-entry:
- ret <4 x float> %arg0
-; CHECK-LABEL: test_returning_arg0
-; CHECK-NOT: mov
-; CHECK: ret
-
-; OPTM1-LABEL: test_returning_arg0
-; OPTM1: movups XMMWORD PTR [[LOC:.*]],xmm0
-; OPTM1: movups xmm0,XMMWORD PTR [[LOC]]
-; OPTM1: ret
-; MIPS32-LABEL: test_returning_arg0
-; MIPS32: lw v0,{{.*}}(sp)
-; MIPS32: lw v1,{{.*}}(sp)
-; MIPS32: move a1,a0
-; MIPS32: sw a2,0(a1)
-; MIPS32: sw a3,4(a1)
-; MIPS32: sw v0,8(a1)
-; MIPS32: sw v1,12(a1)
-; MIPS32: move v0,a0
-}
-
-define internal <4 x float> @test_returning_arg1(
- <4 x float> %arg0, <4 x float> %arg1, <4 x float> %arg2, <4 x float> %arg3,
- <4 x float> %arg4, <4 x float> %arg5) {
-entry:
- ret <4 x float> %arg1
-; CHECK-LABEL: test_returning_arg1
-; CHECK: movups xmm0,xmm1
-; CHECK: ret
-
-; OPTM1-LABEL: test_returning_arg1
-; OPTM1: movups XMMWORD PTR [[LOC:.*]],xmm1
-; OPTM1: movups xmm0,XMMWORD PTR [[LOC]]
-; OPTM1: ret
-; MIPS32-LABEL: test_returning_arg1
-; MIPS32: lw v0,{{.*}}(sp)
-; MIPS32: lw v1,{{.*}}(sp)
-; MIPS32: lw a1,{{.*}}(sp)
-; MIPS32: lw a2,{{.*}}(sp)
-; MIPS32: move a3,a0
-; MIPS32: sw v0,0(a3)
-; MIPS32: sw v1,4(a3)
-; MIPS32: sw a1,8(a3)
-; MIPS32: sw a2,12(a3)
-; MIPS32: move v0,a0
-}
-
-define internal <4 x float> @test_returning_arg2(
- <4 x float> %arg0, <4 x float> %arg1, <4 x float> %arg2, <4 x float> %arg3,
- <4 x float> %arg4, <4 x float> %arg5) {
-entry:
- ret <4 x float> %arg2
-; CHECK-LABEL: test_returning_arg2
-; CHECK: movups xmm0,xmm2
-; CHECK: ret
-
-; OPTM1-LABEL: test_returning_arg2
-; OPTM1: movups XMMWORD PTR [[LOC:.*]],xmm2
-; OPTM1: movups xmm0,XMMWORD PTR [[LOC]]
-; OPTM1: ret
-; MIPS32-LABEL: test_returning_arg2
-; MIPS32: lw v0,{{.*}}(sp)
-; MIPS32: lw v1,{{.*}}(sp)
-; MIPS32: lw a1,{{.*}}(sp)
-; MIPS32: lw a2,{{.*}}(sp)
-; MIPS32: move a3,a0
-; MIPS32: sw v0,0(a3)
-; MIPS32: sw v1,4(a3)
-; MIPS32: sw a1,8(a3)
-; MIPS32: sw a2,12(a3)
-; MIPS32: move v0,a0
-}
-
-define internal <4 x float> @test_returning_arg3(
- <4 x float> %arg0, <4 x float> %arg1, <4 x float> %arg2, <4 x float> %arg3,
- <4 x float> %arg4, <4 x float> %arg5) {
-entry:
- ret <4 x float> %arg3
-; CHECK-LABEL: test_returning_arg3
-; CHECK: movups xmm0,xmm3
-; CHECK: ret
-
-; OPTM1-LABEL: test_returning_arg3
-; OPTM1: movups XMMWORD PTR [[LOC:.*]],xmm3
-; OPTM1: movups xmm0,XMMWORD PTR [[LOC]]
-; OPTM1: ret
-; MIPS32-LABEL: test_returning_arg3
-; MIPS32: lw v0,{{.*}}(sp)
-; MIPS32: lw v1,{{.*}}(sp)
-; MIPS32: lw a1,{{.*}}(sp)
-; MIPS32: lw a2,{{.*}}(sp)
-; MIPS32: move a3,a0
-; MIPS32: sw v0,0(a3)
-; MIPS32: sw v1,4(a3)
-; MIPS32: sw a1,8(a3)
-; MIPS32: sw a2,12(a3)
-; MIPS32: move v0,a0
-}
-
-define internal <4 x float> @test_returning_arg4(
- <4 x float> %arg0, <4 x float> %arg1, <4 x float> %arg2, <4 x float> %arg3,
- <4 x float> %arg4, <4 x float> %arg5) {
-entry:
- ret <4 x float> %arg4
-; CHECK-LABEL: test_returning_arg4
-; CHECK: movups xmm0,XMMWORD PTR [esp+0x4]
-; CHECK: ret
-
-; OPTM1-LABEL: test_returning_arg4
-; OPTM1: movups xmm0,XMMWORD PTR {{.*}}
-; OPTM1: ret
-; MIPS32-LABEL: test_returning_arg4
-; MIPS32: lw v0,{{.*}}(sp)
-; MIPS32: lw v1,{{.*}}(sp)
-; MIPS32: lw a1,{{.*}}(sp)
-; MIPS32: lw a2,{{.*}}(sp)
-; MIPS32: move a3,a0
-; MIPS32: sw v0,0(a3)
-; MIPS32: sw v1,4(a3)
-; MIPS32: sw a1,8(a3)
-; MIPS32: sw a2,12(a3)
-; MIPS32: move v0,a0
-}
-
-; The next five functions check that xmm arguments are handled
-; correctly when interspersed with stack arguments in the argument
-; list.
-
-define internal <4 x float> @test_returning_interspersed_arg0(
- i32 %i32arg0, double %doublearg0, <4 x float> %arg0, <4 x float> %arg1,
- i32 %i32arg1, <4 x float> %arg2, double %doublearg1, <4 x float> %arg3,
- i32 %i32arg2, double %doublearg2, float %floatarg0, <4 x float> %arg4,
- <4 x float> %arg5, float %floatarg1) {
-entry:
- ret <4 x float> %arg0
-; CHECK-LABEL: test_returning_interspersed_arg0
-; CHECK-NOT: mov
-; CHECK: ret
-
-; OPTM1-LABEL: test_returning_interspersed_arg0
-; OPTM1: movups XMMWORD PTR [[LOC:.*]],xmm0
-; OPTM1: movups xmm0,XMMWORD PTR [[LOC]]
-; OPTM1: ret
-; MIPS32-LABEL: test_returning_interspersed_arg0
-; MIPS32: lw v0,{{.*}}(sp)
-; MIPS32: lw v1,{{.*}}(sp)
-; MIPS32: lw a1,{{.*}}(sp)
-; MIPS32: lw a2,{{.*}}(sp)
-; MIPS32: move a3,a0
-; MIPS32: sw v0,0(a3)
-; MIPS32: sw v1,4(a3)
-; MIPS32: sw a1,8(a3)
-; MIPS32: sw a2,12(a3)
-; MIPS32: move v0,a0
-}
-
-define internal <4 x float> @test_returning_interspersed_arg1(
- i32 %i32arg0, double %doublearg0, <4 x float> %arg0, <4 x float> %arg1,
- i32 %i32arg1, <4 x float> %arg2, double %doublearg1, <4 x float> %arg3,
- i32 %i32arg2, double %doublearg2, float %floatarg0, <4 x float> %arg4,
- <4 x float> %arg5, float %floatarg1) {
-entry:
- ret <4 x float> %arg1
-; CHECK-LABEL: test_returning_interspersed_arg1
-; CHECK: movups xmm0,xmm1
-; CHECK: ret
-
-; OPTM1-LABEL: test_returning_interspersed_arg1
-; OPTM1: movups XMMWORD PTR [[LOC:.*]],xmm1
-; OPTM1: movups xmm0,XMMWORD PTR [[LOC]]
-; OPTM1: ret
-; MIPS32-LABEL: test_returning_interspersed_arg1
-; MIPS32: lw v0,{{.*}}(sp)
-; MIPS32: lw v1,{{.*}}(sp)
-; MIPS32: lw a1,{{.*}}(sp)
-; MIPS32: lw a2,{{.*}}(sp)
-; MIPS32: move a3,a0
-; MIPS32: sw v0,0(a3)
-; MIPS32: sw v1,4(a3)
-; MIPS32: sw a1,8(a3)
-; MIPS32: sw a2,12(a3)
-; MIPS32: move v0,a0
-}
-
-define internal <4 x float> @test_returning_interspersed_arg2(
- i32 %i32arg0, double %doublearg0, <4 x float> %arg0, <4 x float> %arg1,
- i32 %i32arg1, <4 x float> %arg2, double %doublearg1, <4 x float> %arg3,
- i32 %i32arg2, double %doublearg2, float %floatarg0, <4 x float> %arg4,
- <4 x float> %arg5, float %floatarg1) {
-entry:
- ret <4 x float> %arg2
-; CHECK-LABEL: test_returning_interspersed_arg2
-; CHECK: movups xmm0,xmm2
-; CHECK: ret
-
-; OPTM1-LABEL: test_returning_interspersed_arg2
-; OPTM1: movups XMMWORD PTR [[LOC:.*]],xmm2
-; OPTM1: movups xmm0,XMMWORD PTR [[LOC]]
-; OPTM1: ret
-; MIPS32-LABEL: test_returning_interspersed_arg2
-; MIPS32: lw v0,{{.*}}(sp)
-; MIPS32: lw v1,{{.*}}(sp)
-; MIPS32: lw a1,{{.*}}(sp)
-; MIPS32: lw a2,{{.*}}(sp)
-; MIPS32: move a3,a0
-; MIPS32: sw v0,0(a3)
-; MIPS32: sw v1,4(a3)
-; MIPS32: sw a1,8(a3)
-; MIPS32: sw a2,12(a3)
-; MIPS32: move v0,a0
-}
-
-define internal <4 x float> @test_returning_interspersed_arg3(
- i32 %i32arg0, double %doublearg0, <4 x float> %arg0, <4 x float> %arg1,
- i32 %i32arg1, <4 x float> %arg2, double %doublearg1, <4 x float> %arg3,
- i32 %i32arg2, double %doublearg2, float %floatarg0, <4 x float> %arg4,
- <4 x float> %arg5, float %floatarg1) {
-entry:
- ret <4 x float> %arg3
-; CHECK-LABEL: test_returning_interspersed_arg3
-; CHECK: movups xmm0,xmm3
-; CHECK: ret
-
-; OPTM1-LABEL: test_returning_interspersed_arg3
-; OPTM1: movups XMMWORD PTR [[LOC:.*]],xmm3
-; OPTM1: movups xmm0,XMMWORD PTR [[LOC]]
-; OPTM1: ret
-; MIPS32-LABEL: test_returning_interspersed_arg3
-; MIPS32: lw v0,{{.*}}(sp)
-; MIPS32: lw v1,{{.*}}(sp)
-; MIPS32: lw a1,{{.*}}(sp)
-; MIPS32: lw a2,{{.*}}(sp)
-; MIPS32: move a3,a0
-; MIPS32: sw v0,0(a3)
-; MIPS32: sw v1,4(a3)
-; MIPS32: sw a1,8(a3)
-; MIPS32: sw a2,12(a3)
-; MIPS32: move v0,a0
-
-}
-
-define internal <4 x float> @test_returning_interspersed_arg4(
- i32 %i32arg0, double %doublearg0, <4 x float> %arg0, <4 x float> %arg1,
- i32 %i32arg1, <4 x float> %arg2, double %doublearg1, <4 x float> %arg3,
- i32 %i32arg2, double %doublearg2, float %floatarg0, <4 x float> %arg4,
- <4 x float> %arg5, float %floatarg1) {
-entry:
- ret <4 x float> %arg4
-; CHECK-LABEL: test_returning_interspersed_arg4
-; CHECK: movups xmm0,XMMWORD PTR [esp+0x34]
-; CHECK: ret
-
-; OPTM1-LABEL: test_returning_interspersed_arg4
-; OPTM1: movups xmm0,XMMWORD PTR {{.*}}
-; OPTM1: ret
-; MIPS32-LABEL: test_returning_interspersed_arg4
-; MIPS32: lw v0,1{{.*}}(sp)
-; MIPS32: lw v1,1{{.*}}(sp)
-; MIPS32: lw a1,1{{.*}}(sp)
-; MIPS32: lw a2,1{{.*}}(sp)
-; MIPS32: move a3,a0
-; MIPS32: sw v0,0(a3)
-; MIPS32: sw v1,4(a3)
-; MIPS32: sw a1,8(a3)
-; MIPS32: sw a2,12(a3)
-; MIPS32: move v0,a0
-}
-
-; Test that vectors are passed correctly as arguments to a function.
-
-declare void @VectorArgs(<4 x float>, <4 x float>, <4 x float>, <4 x float>,
- <4 x float>, <4 x float>)
-
-declare void @killXmmRegisters()
-
-define internal void @test_passing_vectors(
- <4 x float> %arg0, <4 x float> %arg1, <4 x float> %arg2, <4 x float> %arg3,
- <4 x float> %arg4, <4 x float> %arg5, <4 x float> %arg6, <4 x float> %arg7,
- <4 x float> %arg8, <4 x float> %arg9) {
-entry:
- ; Kills XMM registers so that no in-arg lowering code interferes
- ; with the test.
- call void @killXmmRegisters()
- call void @VectorArgs(<4 x float> %arg9, <4 x float> %arg8, <4 x float> %arg7,
- <4 x float> %arg6, <4 x float> %arg5, <4 x float> %arg4)
- ret void
-; CHECK-LABEL: test_passing_vectors
-; CHECK-NEXT: sub esp,0x2c
-; CHECK: movups [[ARG5:.*]],XMMWORD PTR [esp+0x40]
-; CHECK: movups XMMWORD PTR [esp],[[ARG5]]
-; CHECK: movups [[ARG6:.*]],XMMWORD PTR [esp+0x30]
-; CHECK: movups XMMWORD PTR [esp+0x10],[[ARG6]]
-; CHECK: movups xmm0,XMMWORD PTR [esp+0x80]
-; CHECK: movups xmm1,XMMWORD PTR [esp+0x70]
-; CHECK: movups xmm2,XMMWORD PTR [esp+0x60]
-; CHECK: movups xmm3,XMMWORD PTR [esp+0x50]
-; CHECK: call {{.*}} R_{{.*}} VectorArgs
-; CHECK-NEXT: add esp,0x2c
-
-; OPTM1-LABEL: test_passing_vectors
-; OPTM1: sub esp,0x6c
-; OPTM1: movups [[ARG5:.*]],XMMWORD PTR {{.*}}
-; OPTM1: movups XMMWORD PTR [esp],[[ARG5]]
-; OPTM1: movups [[ARG6:.*]],XMMWORD PTR {{.*}}
-; OPTM1: movups XMMWORD PTR [esp+0x10],[[ARG6]]
-; OPTM1: movups xmm0,XMMWORD PTR {{.*}}
-; OPTM1: movups xmm1,XMMWORD PTR {{.*}}
-; OPTM1: movups xmm2,XMMWORD PTR {{.*}}
-; OPTM1: movups xmm3,XMMWORD PTR {{.*}}
-; OPTM1: call {{.*}} R_{{.*}} VectorArgs
-; OPTM1-NEXT: add esp,0x6c
-; MIPS32-LABEL: test_passing_vectors
-; MIPS32: sw s7,{{.*}}(sp)
-; MIPS32: sw s6,{{.*}}(sp)
-; MIPS32: sw s5,{{.*}}(sp)
-; MIPS32: sw s4,{{.*}}(sp)
-; MIPS32: sw s3,{{.*}}(sp)
-; MIPS32: sw s2,{{.*}}(sp)
-; MIPS32: sw s1,{{.*}}(sp)
-; MIPS32: sw s0,{{.*}}(sp)
-; MIPS32: lw s0,{{.*}}(sp)
-; MIPS32: lw s1,{{.*}}(sp)
-; MIPS32: lw s2,{{.*}}(sp)
-; MIPS32: lw s3,{{.*}}(sp)
-; MIPS32: lw s4,{{.*}}(sp)
-; MIPS32: lw s5,{{.*}}(sp)
-; MIPS32: lw s6,{{.*}}(sp)
-; MIPS32: lw s7,{{.*}}(sp)
-; MIPS32: jal 0 <test_returning_arg0> 228: R_MIPS_26 killXmmRegisters
-; MIPS32: nop
-; MIPS32: lw v0,{{.*}}(sp)
-; MIPS32: sw v0,{{.*}}(sp)
-; MIPS32: lw v0,{{.*}}(sp)
-; MIPS32: sw v0,{{.*}}(sp)
-; MIPS32: lw v0,{{.*}}(sp)
-; MIPS32: sw v0,{{.*}}(sp)
-; MIPS32: lw v0,{{.*}}(sp)
-; MIPS32: sw v0,{{.*}}(sp)
-; MIPS32: lw v0,{{.*}}(sp)
-; MIPS32: sw v0,{{.*}}(sp)
-; MIPS32: lw v0,{{.*}}(sp)
-; MIPS32: sw v0,{{.*}}(sp)
-; MIPS32: lw v0,{{.*}}(sp)
-; MIPS32: sw v0,{{.*}}(sp)
-; MIPS32: lw v0,{{.*}}(sp)
-; MIPS32: sw v0,{{.*}}(sp)
-; MIPS32: lw v0,{{.*}}(sp)
-; MIPS32: sw v0,{{.*}}(sp)
-; MIPS32: lw v0,{{.*}}(sp)
-; MIPS32: sw v0,{{.*}}(sp)
-; MIPS32: lw v0,{{.*}}(sp)
-; MIPS32: sw v0,{{.*}}(sp)
-; MIPS32: lw v0,{{.*}}(sp)
-; MIPS32: sw v0,{{.*}}(sp)
-; MIPS32: sw s4,{{.*}}(sp)
-; MIPS32: sw s5,{{.*}}(sp)
-; MIPS32: sw s6,{{.*}}(sp)
-; MIPS32: sw s7,{{.*}}(sp)
-; MIPS32: sw s0,{{.*}}(sp)
-; MIPS32: sw s1,{{.*}}(sp)
-; MIPS32: sw s2,{{.*}}(sp)
-; MIPS32: sw s3,{{.*}}(sp)
-; MIPS32: lw a0,{{.*}}(sp)
-; MIPS32: lw a1,{{.*}}(sp)
-; MIPS32: lw a2,{{.*}}(sp)
-; MIPS32: lw a3,{{.*}}(sp)
-; MIPS32: jal 0 <test_returning_arg0> 2c0: R_MIPS_26 VectorArgs
-; MIPS32: nop
-; MIPS32: lw s0,{{.*}}(sp)
-; MIPS32: lw s1,{{.*}}(sp)
-; MIPS32: lw s2,{{.*}}(sp)
-; MIPS32: lw s3,{{.*}}(sp)
-; MIPS32: lw s4,{{.*}}(sp)
-; MIPS32: lw s5,{{.*}}(sp)
-; MIPS32: lw s6,{{.*}}(sp)
-; MIPS32: lw s7,{{.*}}(sp)
-; MIPS32: lw ra,{{.*}}(sp)
-
-}
-
-declare void @InterspersedVectorArgs(
- <4 x float>, i64, <4 x float>, i64, <4 x float>, float, <4 x float>,
- double, <4 x float>, i32, <4 x float>)
-
-define internal void @test_passing_vectors_interspersed(
- <4 x float> %arg0, <4 x float> %arg1, <4 x float> %arg2, <4 x float> %arg3,
- <4 x float> %arg4, <4 x float> %arg5, <4 x float> %arg6, <4 x float> %arg7,
- <4 x float> %arg8, <4 x float> %arg9) {
-entry:
- ; Kills XMM registers so that no in-arg lowering code interferes
- ; with the test.
- call void @killXmmRegisters()
- call void @InterspersedVectorArgs(<4 x float> %arg9, i64 0, <4 x float> %arg8,
- i64 1, <4 x float> %arg7, float 2.000000e+00,
- <4 x float> %arg6, double 3.000000e+00,
- <4 x float> %arg5, i32 4, <4 x float> %arg4)
- ret void
-; CHECK-LABEL: test_passing_vectors_interspersed
-; CHECK: sub esp,0x5c
-; CHECK: movups [[ARG9:.*]],XMMWORD PTR [esp+0x70]
-; CHECK: movups XMMWORD PTR [esp+0x20],[[ARG9]]
-; CHECK: movups [[ARG11:.*]],XMMWORD PTR [esp+0x60]
-; CHECK: movups XMMWORD PTR [esp+0x40],[[ARG11]]
-; CHECK: movups xmm0,XMMWORD PTR [esp+0xb0]
-; CHECK: movups xmm1,XMMWORD PTR [esp+0xa0]
-; CHECK: movups xmm2,XMMWORD PTR [esp+0x90]
-; CHECK: movups xmm3,XMMWORD PTR [esp+0x80]
-; CHECK: call {{.*}} R_{{.*}} InterspersedVectorArgs
-; CHECK-NEXT: add esp,0x5c
-; CHECK: ret
-
-; OPTM1-LABEL: test_passing_vectors_interspersed
-; OPTM1: sub esp,0x9c
-; OPTM1: movups [[ARG9:.*]],XMMWORD PTR {{.*}}
-; OPTM1: movups XMMWORD PTR [esp+0x20],[[ARG9]]
-; OPTM1: movups [[ARG11:.*]],XMMWORD PTR {{.*}}
-; OPTM1: movups XMMWORD PTR [esp+0x40],[[ARG11]]
-; OPTM1: movups xmm0,XMMWORD PTR {{.*}}
-; OPTM1: movups xmm1,XMMWORD PTR {{.*}}
-; OPTM1: movups xmm2,XMMWORD PTR {{.*}}
-; OPTM1: movups xmm3,XMMWORD PTR {{.*}}
-; OPTM1: call {{.*}} R_{{.*}} InterspersedVectorArgs
-; OPTM1-NEXT: add esp,0x9c
-; OPTM1: ret
-; MIPS32-LABEL: test_passing_vectors_interspersed
-; MIPS32: sw s7,{{.*}}(sp)
-; MIPS32: sw s6,{{.*}}(sp)
-; MIPS32: sw s5,{{.*}}(sp)
-; MIPS32: sw s4,{{.*}}(sp)
-; MIPS32: sw s3,{{.*}}(sp)
-; MIPS32: sw s2,{{.*}}(sp)
-; MIPS32: sw s1,{{.*}}(sp)
-; MIPS32: sw s0,{{.*}}(sp)
-; MIPS32: lw s0,{{.*}}(sp)
-; MIPS32: lw s1,{{.*}}(sp)
-; MIPS32: lw s2,{{.*}}(sp)
-; MIPS32: lw s3,{{.*}}(sp)
-; MIPS32: lw s4,{{.*}}(sp)
-; MIPS32: lw s5,{{.*}}(sp)
-; MIPS32: lw s6,{{.*}}(sp)
-; MIPS32: lw s7,{{.*}}(sp)
-; MIPS32: jal 0 <test_returning_arg0> 348: R_MIPS_26 killXmmRegisters
-; MIPS32: nop
-; MIPS32: li v0,0
-; MIPS32: li v1,0
-; MIPS32: sw v0,{{.*}}(sp)
-; MIPS32: sw v1,{{.*}}(sp)
-; MIPS32: lw v0,{{.*}}(sp)
-; MIPS32: sw v0,{{.*}}(sp)
-; MIPS32: lw v0,{{.*}}(sp)
-; MIPS32: sw v0,{{.*}}(sp)
-; MIPS32: lw v0,{{.*}}(sp)
-; MIPS32: sw v0,{{.*}}(sp)
-; MIPS32: lw v0,{{.*}}(sp)
-; MIPS32: sw v0,{{.*}}(sp)
-; MIPS32: li v0,0
-; MIPS32: li v1,1
-; MIPS32: sw v0,{{.*}}(sp)
-; MIPS32: sw v1,{{.*}}(sp)
-; MIPS32: lw v0,{{.*}}(sp)
-; MIPS32: sw v0,{{.*}}(sp)
-; MIPS32: lw v0,{{.*}}(sp)
-; MIPS32: sw v0,{{.*}}(sp)
-; MIPS32: lw v0,{{.*}}(sp)
-; MIPS32: sw v0,{{.*}}(sp)
-; MIPS32: lw v0,{{.*}}(sp)
-; MIPS32: sw v0,{{.*}}(sp)
-; MIPS32: lui v0,0x0 3b0: R_MIPS_HI16 .L$float$40000000
-; MIPS32: lwc1 $f0,0(v0) 3b4: R_MIPS_LO16 .L$float$40000000
-; MIPS32: swc1 $f0,{{.*}}(sp)
-; MIPS32: lw v0,{{.*}}(sp)
-; MIPS32: sw v0,{{.*}}(sp)
-; MIPS32: lw v0,{{.*}}(sp)
-; MIPS32: sw v0,{{.*}}(sp)
-; MIPS32: lw v0,{{.*}}(sp)
-; MIPS32: sw v0,{{.*}}(sp)
-; MIPS32: lw v0,{{.*}}(sp)
-; MIPS32: sw v0,{{.*}}(sp)
-; MIPS32: lui v0,0x0 3dc: R_MIPS_HI16 .L$double$4008000000000000
-; MIPS32: ldc1 $f0,0(v0) 3e0: R_MIPS_LO16 .L$double$4008000000000000
-; MIPS32: sdc1 $f0,{{.*}}(sp)
-; MIPS32: sw s4,{{.*}}(sp)
-; MIPS32: sw s5,{{.*}}(sp)
-; MIPS32: sw s6,{{.*}}(sp)
-; MIPS32: sw s7,{{.*}}(sp)
-; MIPS32: li v0,4
-; MIPS32: sw v0,{{.*}}(sp)
-; MIPS32: sw s0,{{.*}}(sp)
-; MIPS32: sw s1,{{.*}}(sp)
-; MIPS32: sw s2,{{.*}}(sp)
-; MIPS32: sw s3,{{.*}}(sp)
-; MIPS32: lw a0,{{.*}}(sp)
-; MIPS32: lw a1,{{.*}}(sp)
-; MIPS32: lw a2,{{.*}}(sp)
-; MIPS32: lw a3,{{.*}}(sp)
-; MIPS32: jal 0 <test_returning_arg0> 420: R_MIPS_26 InterspersedVectorArgs
-; MIPS32: nop
-; MIPS32: lw s0,{{.*}}(sp)
-; MIPS32: lw s1,{{.*}}(sp)
-; MIPS32: lw s2,{{.*}}(sp)
-; MIPS32: lw s3,{{.*}}(sp)
-; MIPS32: lw s4,{{.*}}(sp)
-; MIPS32: lw s5,{{.*}}(sp)
-; MIPS32: lw s6,{{.*}}(sp)
-; MIPS32: lw s7,{{.*}}(sp)
-; MIPS32: lw ra,{{.*}}(sp)
-}
-
-; Test that a vector returned from a function is recognized to be in
-; xmm0.
-
-declare <4 x float> @VectorReturn(<4 x float> %arg0)
-
-define internal void @test_receiving_vectors(<4 x float> %arg0) {
-entry:
- %result = call <4 x float> @VectorReturn(<4 x float> %arg0)
- %result2 = call <4 x float> @VectorReturn(<4 x float> %result)
- ret void
-; CHECK-LABEL: test_receiving_vectors
-; CHECK: call {{.*}} R_{{.*}} VectorReturn
-; CHECK-NOT: movups xmm0
-; CHECK: call {{.*}} R_{{.*}} VectorReturn
-; CHECK: ret
-
-; OPTM1-LABEL: test_receiving_vectors
-; OPTM1: call {{.*}} R_{{.*}} VectorReturn
-; OPTM1: movups {{.*}},xmm0
-; OPTM1: movups xmm0,{{.*}}
-; OPTM1: call {{.*}} R_{{.*}} VectorReturn
-; OPTM1: ret
-; MIPS32-LABEL: test_receiving_vectors
-; MIPS32: sw s8,{{.*}}(sp)
-; MIPS32: sw s0,{{.*}}(sp)
-; MIPS32: move s8,sp
-; MIPS32: move v0,a0
-; MIPS32: addiu v1,sp,32
-; MIPS32: move s0,v1
-; MIPS32: move a0,s0
-; MIPS32: sw a2,{{.*}}(sp)
-; MIPS32: sw a3,{{.*}}(sp)
-; MIPS32: move a2,v0
-; MIPS32: move a3,a1
-; MIPS32: jal 0 <test_returning_arg0> {{.*}} R_MIPS_26 VectorReturn
-; MIPS32: nop
-; MIPS32: lw v0,0(s0)
-; MIPS32: lw v1,4(s0)
-; MIPS32: lw a0,8(s0)
-; MIPS32: move a1,a0
-; MIPS32: lw s0,12(s0)
-; MIPS32: addiu a0,sp,48
-; MIPS32: sw a1,{{.*}}(sp)
-; MIPS32: sw s0,{{.*}}(sp)
-; MIPS32: move a2,v0
-; MIPS32: move a3,v1
-; MIPS32: jal 0 <test_returning_arg0> {{.*}} R_MIPS_26 VectorReturn
-; MIPS32: nop
-; MIPS32: move sp,s8
-; MIPS32: lw s0,{{.*}}(sp)
-; MIPS32: lw s8,{{.*}}(sp)
-; MIPS32: lw ra,{{.*}}(sp)
-}
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/vector-arith.ll b/third_party/subzero/tests_lit/llvm2ice_tests/vector-arith.ll
deleted file mode 100644
index a1b3126..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/vector-arith.ll
+++ /dev/null
@@ -1,991 +0,0 @@
-; This test checks support for vector arithmetic.
-
-; RUN: %p2i -i %s --filetype=obj --disassemble -a -O2 \
-; RUN: | FileCheck %s
-; RUN: %p2i -i %s --filetype=obj --disassemble -a -Om1 \
-; RUN: | FileCheck %s
-; RUN: %p2i -i %s --filetype=obj --disassemble -a -O2 -mattr=sse4.1 \
-; RUN: | FileCheck --check-prefix=SSE41 %s
-; RUN: %p2i -i %s --filetype=obj --disassemble -a -Om1 -mattr=sse4.1 \
-; RUN: | FileCheck --check-prefix=SSE41 %s
-
-; RUN: %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command %p2i --filetype=asm --assemble --disassemble --target \
-; RUN: mips32 -i %s --args -O2 -allow-externally-defined-symbols \
-; RUN: | %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command FileCheck --check-prefix MIPS32 %s
-
-define internal <4 x float> @test_fadd(<4 x float> %arg0, <4 x float> %arg1) {
-entry:
- %res = fadd <4 x float> %arg0, %arg1
- ret <4 x float> %res
-; CHECK-LABEL: test_fadd
-; CHECK: addps
-; MIPS32-LABEL: test_fadd
-; MIPS32: add.s
-; MIPS32: add.s
-; MIPS32: add.s
-; MIPS32: add.s
-}
-
-define internal <4 x float> @test_fsub(<4 x float> %arg0, <4 x float> %arg1) {
-entry:
- %res = fsub <4 x float> %arg0, %arg1
- ret <4 x float> %res
-; CHECK-LABEL: test_fsub
-; CHECK: subps
-; MIPS32-LABEL: test_fsub
-; MIPS32: sub.s
-; MIPS32: sub.s
-; MIPS32: sub.s
-; MIPS32: sub.s
-}
-
-define internal <4 x float> @test_fmul(<4 x float> %arg0, <4 x float> %arg1) {
-entry:
- %res = fmul <4 x float> %arg0, %arg1
- ret <4 x float> %res
-; CHECK-LABEL: test_fmul
-; CHECK: mulps
-; MIPS32-LABEL: test_fmul
-; MIPS32: mul.s
-; MIPS32: mul.s
-; MIPS32: mul.s
-; MIPS32: mul.s
-}
-
-define internal <4 x float> @test_fdiv(<4 x float> %arg0, <4 x float> %arg1) {
-entry:
- %res = fdiv <4 x float> %arg0, %arg1
- ret <4 x float> %res
-; CHECK-LABEL: test_fdiv
-; CHECK: divps
-; MIPS32-LABEL: test_fdiv
-; MIPS32: div.s
-; MIPS32: div.s
-; MIPS32: div.s
-; MIPS32: div.s
-}
-
-define internal <4 x float> @test_frem(<4 x float> %arg0, <4 x float> %arg1) {
-entry:
- %res = frem <4 x float> %arg0, %arg1
- ret <4 x float> %res
-; CHECK-LABEL: test_frem
-; CHECK: fmodf
-; CHECK: fmodf
-; CHECK: fmodf
-; CHECK: fmodf
-}
-
-define internal <16 x i8> @test_add_v16i8(<16 x i8> %arg0, <16 x i8> %arg1) {
-entry:
- %res = add <16 x i8> %arg0, %arg1
- ret <16 x i8> %res
-; CHECK-LABEL: test_add_v16i8
-; CHECK: paddb
-; MIPS32-LABEL: test_add_v16i8
-; MIPS32: addu
-; MIPS32: addu
-; MIPS32: addu
-; MIPS32: addu
-; MIPS32: addu
-; MIPS32: addu
-; MIPS32: addu
-; MIPS32: addu
-; MIPS32: addu
-; MIPS32: addu
-; MIPS32: addu
-; MIPS32: addu
-; MIPS32: addu
-; MIPS32: addu
-; MIPS32: addu
-; MIPS32: addu
-}
-
-define internal <16 x i8> @test_and_v16i8(<16 x i8> %arg0, <16 x i8> %arg1) {
-entry:
- %res = and <16 x i8> %arg0, %arg1
- ret <16 x i8> %res
-; CHECK-LABEL: test_and_v16i8
-; CHECK: pand
-; MIPS32-LABEL: test_and_v16i8
-; MIPS32: and
-; MIPS32: and
-; MIPS32: and
-; MIPS32: and
-; MIPS32: and
-; MIPS32: and
-; MIPS32: and
-; MIPS32: and
-; MIPS32: and
-; MIPS32: and
-; MIPS32: and
-; MIPS32: and
-; MIPS32: and
-; MIPS32: and
-; MIPS32: and
-; MIPS32: and
-}
-
-define internal <16 x i8> @test_or_v16i8(<16 x i8> %arg0, <16 x i8> %arg1) {
-entry:
- %res = or <16 x i8> %arg0, %arg1
- ret <16 x i8> %res
-; CHECK-LABEL: test_or_v16i8
-; CHECK: por
-; MIPS32-LABEL: test_or_v16i8
-; MIPS32: or
-; MIPS32: or
-; MIPS32: or
-; MIPS32: or
-; MIPS32: or
-; MIPS32: or
-; MIPS32: or
-; MIPS32: or
-; MIPS32: or
-; MIPS32: or
-; MIPS32: or
-; MIPS32: or
-; MIPS32: or
-; MIPS32: or
-; MIPS32: or
-; MIPS32: or
-}
-
-define internal <16 x i8> @test_xor_v16i8(<16 x i8> %arg0, <16 x i8> %arg1) {
-entry:
- %res = xor <16 x i8> %arg0, %arg1
- ret <16 x i8> %res
-; CHECK-LABEL: test_xor_v16i8
-; CHECK: pxor
-; MIPS32-LABEL: test_xor_v16i8
-; MIPS32: xor
-; MIPS32: xor
-; MIPS32: xor
-; MIPS32: xor
-; MIPS32: xor
-; MIPS32: xor
-; MIPS32: xor
-; MIPS32: xor
-; MIPS32: xor
-; MIPS32: xor
-; MIPS32: xor
-; MIPS32: xor
-; MIPS32: xor
-; MIPS32: xor
-; MIPS32: xor
-; MIPS32: xor
-}
-
-define internal <16 x i8> @test_sub_v16i8(<16 x i8> %arg0, <16 x i8> %arg1) {
-entry:
- %res = sub <16 x i8> %arg0, %arg1
- ret <16 x i8> %res
-; CHECK-LABEL: test_sub_v16i8
-; CHECK: psubb
-; MIPS32-LABEL: test_sub_v16i8
-; MIPS32: subu
-; MIPS32: subu
-; MIPS32: subu
-; MIPS32: subu
-; MIPS32: subu
-; MIPS32: subu
-; MIPS32: subu
-; MIPS32: subu
-; MIPS32: subu
-; MIPS32: subu
-; MIPS32: subu
-; MIPS32: subu
-; MIPS32: subu
-; MIPS32: subu
-; MIPS32: subu
-; MIPS32: subu
-}
-
-define internal <16 x i8> @test_mul_v16i8(<16 x i8> %arg0, <16 x i8> %arg1) {
-entry:
- %res = mul <16 x i8> %arg0, %arg1
- ret <16 x i8> %res
-; CHECK-LABEL: test_mul_v16i8
-; CHECK: imul
-; CHECK: imul
-; CHECK: imul
-; CHECK: imul
-; CHECK: imul
-; CHECK: imul
-; CHECK: imul
-; CHECK: imul
-; CHECK: imul
-; CHECK: imul
-; CHECK: imul
-; CHECK: imul
-; CHECK: imul
-; CHECK: imul
-; CHECK: imul
-; CHECK: imul
-; MIPS32-LABEL: test_mul_v16i8
-; MIPS32: mul
-; MIPS32: mul
-; MIPS32: mul
-; MIPS32: mul
-; MIPS32: mul
-; MIPS32: mul
-; MIPS32: mul
-; MIPS32: mul
-; MIPS32: mul
-; MIPS32: mul
-; MIPS32: mul
-; MIPS32: mul
-; MIPS32: mul
-; MIPS32: mul
-; MIPS32: mul
-; MIPS32: mul
-}
-
-define internal <16 x i8> @test_shl_v16i8(<16 x i8> %arg0, <16 x i8> %arg1) {
-entry:
- %res = shl <16 x i8> %arg0, %arg1
- ret <16 x i8> %res
-; CHECK-LABEL: test_shl_v16i8
-; CHECK: shl
-; CHECK: shl
-; CHECK: shl
-; CHECK: shl
-; CHECK: shl
-; CHECK: shl
-; CHECK: shl
-; CHECK: shl
-; CHECK: shl
-; CHECK: shl
-; CHECK: shl
-; CHECK: shl
-; CHECK: shl
-; CHECK: shl
-; CHECK: shl
-; CHECK: shl
-; MIPS32-LABEL: test_shl_v16i8
-; MIPS32: sllv
-; MIPS32: sllv
-; MIPS32: sllv
-; MIPS32: sllv
-; MIPS32: sllv
-; MIPS32: sllv
-; MIPS32: sllv
-; MIPS32: sllv
-; MIPS32: sllv
-; MIPS32: sllv
-; MIPS32: sllv
-; MIPS32: sllv
-; MIPS32: sllv
-; MIPS32: sllv
-; MIPS32: sllv
-; MIPS32: sllv
-}
-
-define internal <16 x i8> @test_lshr_v16i8(<16 x i8> %arg0, <16 x i8> %arg1) {
-entry:
- %res = lshr <16 x i8> %arg0, %arg1
- ret <16 x i8> %res
-; CHECK-LABEL: test_lshr_v16i8
-; CHECK: shr
-; CHECK: shr
-; CHECK: shr
-; CHECK: shr
-; CHECK: shr
-; CHECK: shr
-; CHECK: shr
-; CHECK: shr
-; CHECK: shr
-; CHECK: shr
-; CHECK: shr
-; CHECK: shr
-; CHECK: shr
-; CHECK: shr
-; CHECK: shr
-; CHECK: shr
-; MIPS32-LABEL: test_lshr_v16i8
-; MIPS32: srlv
-; MIPS32: srlv
-; MIPS32: srlv
-; MIPS32: srlv
-; MIPS32: srlv
-; MIPS32: srlv
-; MIPS32: srlv
-; MIPS32: srlv
-; MIPS32: srlv
-; MIPS32: srlv
-; MIPS32: srlv
-; MIPS32: srlv
-; MIPS32: srlv
-; MIPS32: srlv
-; MIPS32: srlv
-; MIPS32: srlv
-}
-
-define internal <16 x i8> @test_ashr_v16i8(<16 x i8> %arg0, <16 x i8> %arg1) {
-entry:
- %res = ashr <16 x i8> %arg0, %arg1
- ret <16 x i8> %res
-; CHECK-LABEL: test_ashr_v16i8
-; CHECK: sar
-; CHECK: sar
-; CHECK: sar
-; CHECK: sar
-; CHECK: sar
-; CHECK: sar
-; CHECK: sar
-; CHECK: sar
-; CHECK: sar
-; CHECK: sar
-; CHECK: sar
-; CHECK: sar
-; CHECK: sar
-; CHECK: sar
-; CHECK: sar
-; CHECK: sar
-; MIPS32-LABEL: test_ashr_v16i8
-; MIPS32: srav
-; MIPS32: srav
-; MIPS32: srav
-; MIPS32: srav
-; MIPS32: srav
-; MIPS32: srav
-; MIPS32: srav
-; MIPS32: srav
-; MIPS32: srav
-; MIPS32: srav
-; MIPS32: srav
-; MIPS32: srav
-; MIPS32: srav
-; MIPS32: srav
-; MIPS32: srav
-; MIPS32: srav
-}
-
-define internal <16 x i8> @test_udiv_v16i8(<16 x i8> %arg0, <16 x i8> %arg1) {
-entry:
- %res = udiv <16 x i8> %arg0, %arg1
- ret <16 x i8> %res
-; CHECK-LABEL: test_udiv_v16i8
-; CHECK: div
-; CHECK: div
-; CHECK: div
-; CHECK: div
-; CHECK: div
-; CHECK: div
-; CHECK: div
-; CHECK: div
-; CHECK: div
-; CHECK: div
-; CHECK: div
-; CHECK: div
-; CHECK: div
-; CHECK: div
-; CHECK: div
-; CHECK: div
-; MIPS32-LABEL: test_udiv_v16i8
-; MIPS32: divu
-; MIPS32: divu
-; MIPS32: divu
-; MIPS32: divu
-; MIPS32: divu
-; MIPS32: divu
-; MIPS32: divu
-; MIPS32: divu
-; MIPS32: divu
-; MIPS32: divu
-; MIPS32: divu
-; MIPS32: divu
-; MIPS32: divu
-; MIPS32: divu
-; MIPS32: divu
-; MIPS32: divu
-}
-
-define internal <16 x i8> @test_sdiv_v16i8(<16 x i8> %arg0, <16 x i8> %arg1) {
-entry:
- %res = sdiv <16 x i8> %arg0, %arg1
- ret <16 x i8> %res
-; CHECK-LABEL: test_sdiv_v16i8
-; CHECK: idiv
-; CHECK: idiv
-; CHECK: idiv
-; CHECK: idiv
-; CHECK: idiv
-; CHECK: idiv
-; CHECK: idiv
-; CHECK: idiv
-; CHECK: idiv
-; CHECK: idiv
-; CHECK: idiv
-; CHECK: idiv
-; CHECK: idiv
-; CHECK: idiv
-; CHECK: idiv
-; CHECK: idiv
-; MIPS32-LABEL: test_sdiv_v16i8
-; MIPS32: div
-; MIPS32: div
-; MIPS32: div
-; MIPS32: div
-; MIPS32: div
-; MIPS32: div
-; MIPS32: div
-; MIPS32: div
-; MIPS32: div
-; MIPS32: div
-; MIPS32: div
-; MIPS32: div
-; MIPS32: div
-; MIPS32: div
-; MIPS32: div
-; MIPS32: div
-}
-
-define internal <16 x i8> @test_urem_v16i8(<16 x i8> %arg0, <16 x i8> %arg1) {
-entry:
- %res = urem <16 x i8> %arg0, %arg1
- ret <16 x i8> %res
-; CHECK-LABEL: test_urem_v16i8
-; CHECK: div
-; CHECK: div
-; CHECK: div
-; CHECK: div
-; CHECK: div
-; CHECK: div
-; CHECK: div
-; CHECK: div
-; CHECK: div
-; CHECK: div
-; CHECK: div
-; CHECK: div
-; CHECK: div
-; CHECK: div
-; CHECK: div
-; CHECK: div
-; MIPS32-LABEL: test_urem_v16i8
-; MIPS32: divu
-; MIPS32: divu
-; MIPS32: divu
-; MIPS32: divu
-; MIPS32: divu
-; MIPS32: divu
-; MIPS32: divu
-; MIPS32: divu
-; MIPS32: divu
-; MIPS32: divu
-; MIPS32: divu
-; MIPS32: divu
-; MIPS32: divu
-; MIPS32: divu
-; MIPS32: divu
-; MIPS32: divu
-}
-
-define internal <16 x i8> @test_srem_v16i8(<16 x i8> %arg0, <16 x i8> %arg1) {
-entry:
- %res = srem <16 x i8> %arg0, %arg1
- ret <16 x i8> %res
-; CHECK-LABEL: test_srem_v16i8
-; CHECK: idiv
-; CHECK: idiv
-; CHECK: idiv
-; CHECK: idiv
-; CHECK: idiv
-; CHECK: idiv
-; CHECK: idiv
-; CHECK: idiv
-; CHECK: idiv
-; CHECK: idiv
-; CHECK: idiv
-; CHECK: idiv
-; CHECK: idiv
-; CHECK: idiv
-; CHECK: idiv
-; CHECK: idiv
-; MIPS32-LABEL: test_srem_v16i8
-; MIPS32: div
-; MIPS32: div
-; MIPS32: div
-; MIPS32: div
-; MIPS32: div
-; MIPS32: div
-; MIPS32: div
-; MIPS32: div
-; MIPS32: div
-; MIPS32: div
-; MIPS32: div
-; MIPS32: div
-; MIPS32: div
-; MIPS32: div
-; MIPS32: div
-; MIPS32: div
-}
-
-define internal <8 x i16> @test_add_v8i16(<8 x i16> %arg0, <8 x i16> %arg1) {
-entry:
- %res = add <8 x i16> %arg0, %arg1
- ret <8 x i16> %res
-; CHECK-LABEL: test_add_v8i16
-; CHECK: paddw
-; MIPS32-LABEL: test_add_v8i16
-; MIPS32: addu
-; MIPS32: addu
-; MIPS32: addu
-; MIPS32: addu
-; MIPS32: addu
-; MIPS32: addu
-; MIPS32: addu
-; MIPS32: addu
-}
-
-define internal <8 x i16> @test_and_v8i16(<8 x i16> %arg0, <8 x i16> %arg1) {
-entry:
- %res = and <8 x i16> %arg0, %arg1
- ret <8 x i16> %res
-; CHECK-LABEL: test_and_v8i16
-; CHECK: pand
-; MIPS32-LABEL: test_and_v8i16
-; MIPS32: andi
-; MIPS32: andi
-; MIPS32: andi
-; MIPS32: andi
-; MIPS32: andi
-; MIPS32: andi
-; MIPS32: andi
-; MIPS32: andi
-}
-
-define internal <8 x i16> @test_or_v8i16(<8 x i16> %arg0, <8 x i16> %arg1) {
-entry:
- %res = or <8 x i16> %arg0, %arg1
- ret <8 x i16> %res
-; CHECK-LABEL: test_or_v8i16
-; CHECK: por
-; MIPS32-LABEL: test_or_v8i16
-; MIPS32: or
-; MIPS32: or
-; MIPS32: or
-; MIPS32: or
-; MIPS32: or
-; MIPS32: or
-; MIPS32: or
-; MIPS32: or
-}
-
-define internal <8 x i16> @test_xor_v8i16(<8 x i16> %arg0, <8 x i16> %arg1) {
-entry:
- %res = xor <8 x i16> %arg0, %arg1
- ret <8 x i16> %res
-; CHECK-LABEL: test_xor_v8i16
-; CHECK: pxor
-; MIPS32-LABEL: test_xor_v8i16
-; MIPS32: xor
-; MIPS32: xor
-; MIPS32: xor
-; MIPS32: xor
-; MIPS32: xor
-; MIPS32: xor
-; MIPS32: xor
-; MIPS32: xor
-}
-
-define internal <8 x i16> @test_sub_v8i16(<8 x i16> %arg0, <8 x i16> %arg1) {
-entry:
- %res = sub <8 x i16> %arg0, %arg1
- ret <8 x i16> %res
-; CHECK-LABEL: test_sub_v8i16
-; CHECK: psubw
-; MIPS32-LABEL: test_sub_v8i16
-; MIPS32: subu
-; MIPS32: subu
-; MIPS32: subu
-; MIPS32: subu
-; MIPS32: subu
-; MIPS32: subu
-; MIPS32: subu
-; MIPS32: subu
-}
-
-define internal <8 x i16> @test_mul_v8i16(<8 x i16> %arg0, <8 x i16> %arg1) {
-entry:
- %res = mul <8 x i16> %arg0, %arg1
- ret <8 x i16> %res
-; CHECK-LABEL: test_mul_v8i16
-; CHECK: pmullw
-; MIPS32-LABEL: test_mul_v8i16
-; MIPS32: mul
-; MIPS32: mul
-; MIPS32: mul
-; MIPS32: mul
-; MIPS32: mul
-; MIPS32: mul
-; MIPS32: mul
-; MIPS32: mul
-}
-
-define internal <8 x i16> @test_shl_v8i16(<8 x i16> %arg0, <8 x i16> %arg1) {
-entry:
- %res = shl <8 x i16> %arg0, %arg1
- ret <8 x i16> %res
-; CHECK-LABEL: test_shl_v8i16
-; CHECK: shl
-; CHECK: shl
-; CHECK: shl
-; CHECK: shl
-; CHECK: shl
-; CHECK: shl
-; CHECK: shl
-; CHECK: shl
-; MIPS32-LABEL: test_shl_v8i16
-; MIPS32: sllv
-; MIPS32: sllv
-; MIPS32: sllv
-; MIPS32: sllv
-; MIPS32: sllv
-; MIPS32: sllv
-; MIPS32: sllv
-; MIPS32: sllv
-}
-
-define internal <8 x i16> @test_lshr_v8i16(<8 x i16> %arg0, <8 x i16> %arg1) {
-entry:
- %res = lshr <8 x i16> %arg0, %arg1
- ret <8 x i16> %res
-; CHECK-LABEL: test_lshr_v8i16
-; CHECK: shr
-; CHECK: shr
-; CHECK: shr
-; CHECK: shr
-; CHECK: shr
-; CHECK: shr
-; CHECK: shr
-; CHECK: shr
-; MIPS32-LABEL: test_lshr_v8i16
-; MIPS32: srlv
-; MIPS32: srlv
-; MIPS32: srlv
-; MIPS32: srlv
-; MIPS32: srlv
-; MIPS32: srlv
-; MIPS32: srlv
-; MIPS32: srlv
-}
-
-define internal <8 x i16> @test_ashr_v8i16(<8 x i16> %arg0, <8 x i16> %arg1) {
-entry:
- %res = ashr <8 x i16> %arg0, %arg1
- ret <8 x i16> %res
-; CHECK-LABEL: test_ashr_v8i16
-; CHECK: sar
-; CHECK: sar
-; CHECK: sar
-; CHECK: sar
-; CHECK: sar
-; CHECK: sar
-; CHECK: sar
-; CHECK: sar
-; MIPS32-LABEL: test_ashr_v8i16
-; MIPS32: srav
-; MIPS32: srav
-; MIPS32: srav
-; MIPS32: srav
-; MIPS32: srav
-; MIPS32: srav
-; MIPS32: srav
-; MIPS32: srav
-}
-
-define internal <8 x i16> @test_udiv_v8i16(<8 x i16> %arg0, <8 x i16> %arg1) {
-entry:
- %res = udiv <8 x i16> %arg0, %arg1
- ret <8 x i16> %res
-; CHECK-LABEL: test_udiv_v8i16
-; CHECK: div
-; CHECK: div
-; CHECK: div
-; CHECK: div
-; CHECK: div
-; CHECK: div
-; CHECK: div
-; CHECK: div
-; MIPS32-LABEL: test_udiv_v8i16
-; MIPS32: divu
-; MIPS32: divu
-; MIPS32: divu
-; MIPS32: divu
-; MIPS32: divu
-; MIPS32: divu
-; MIPS32: divu
-; MIPS32: divu
-}
-
-define internal <8 x i16> @test_sdiv_v8i16(<8 x i16> %arg0, <8 x i16> %arg1) {
-entry:
- %res = sdiv <8 x i16> %arg0, %arg1
- ret <8 x i16> %res
-; CHECK-LABEL: test_sdiv_v8i16
-; CHECK: idiv
-; CHECK: idiv
-; CHECK: idiv
-; CHECK: idiv
-; CHECK: idiv
-; CHECK: idiv
-; CHECK: idiv
-; CHECK: idiv
-; MIPS32-LABEL: test_sdiv_v8i16
-; MIPS32: div
-; MIPS32: div
-; MIPS32: div
-; MIPS32: div
-; MIPS32: div
-; MIPS32: div
-; MIPS32: div
-; MIPS32: div
-}
-
-define internal <8 x i16> @test_urem_v8i16(<8 x i16> %arg0, <8 x i16> %arg1) {
-entry:
- %res = urem <8 x i16> %arg0, %arg1
- ret <8 x i16> %res
-; CHECK-LABEL: test_urem_v8i16
-; CHECK: div
-; CHECK: div
-; CHECK: div
-; CHECK: div
-; CHECK: div
-; CHECK: div
-; CHECK: div
-; CHECK: div
-; MIPS32-LABEL: test_urem_v8i16
-; MIPS32: divu
-; MIPS32: divu
-; MIPS32: divu
-; MIPS32: divu
-; MIPS32: divu
-; MIPS32: divu
-; MIPS32: divu
-; MIPS32: divu
-}
-
-define internal <8 x i16> @test_srem_v8i16(<8 x i16> %arg0, <8 x i16> %arg1) {
-entry:
- %res = srem <8 x i16> %arg0, %arg1
- ret <8 x i16> %res
-; CHECK-LABEL: test_srem_v8i16
-; CHECK: idiv
-; CHECK: idiv
-; CHECK: idiv
-; CHECK: idiv
-; CHECK: idiv
-; CHECK: idiv
-; CHECK: idiv
-; CHECK: idiv
-; MIPS32-LABEL: test_srem_v8i16
-; MIPS32: div
-; MIPS32: div
-; MIPS32: div
-; MIPS32: div
-; MIPS32: div
-; MIPS32: div
-; MIPS32: div
-; MIPS32: div
-}
-
-define internal <4 x i32> @test_add_v4i32(<4 x i32> %arg0, <4 x i32> %arg1) {
-entry:
- %res = add <4 x i32> %arg0, %arg1
- ret <4 x i32> %res
-; CHECK-LABEL: test_add_v4i32
-; CHECK: paddd
-; MIPS32-LABEL: test_add_v4i32
-; MIPS32: addu
-; MIPS32: addu
-; MIPS32: addu
-; MIPS32: addu
-}
-
-define internal <4 x i32> @test_and_v4i32(<4 x i32> %arg0, <4 x i32> %arg1) {
-entry:
- %res = and <4 x i32> %arg0, %arg1
- ret <4 x i32> %res
-; CHECK-LABEL: test_and_v4i32
-; CHECK: pand
-; MIPS32-LABEL: test_and_v4i32
-; MIPS32: and
-; MIPS32: and
-; MIPS32: and
-; MIPS32: and
-}
-
-define internal <4 x i32> @test_or_v4i32(<4 x i32> %arg0, <4 x i32> %arg1) {
-entry:
- %res = or <4 x i32> %arg0, %arg1
- ret <4 x i32> %res
-; CHECK-LABEL: test_or_v4i32
-; CHECK: por
-; MIPS32-LABEL: test_or_v4i32
-; MIPS32: or
-; MIPS32: or
-; MIPS32: or
-; MIPS32: or
-}
-
-define internal <4 x i32> @test_xor_v4i32(<4 x i32> %arg0, <4 x i32> %arg1) {
-entry:
- %res = xor <4 x i32> %arg0, %arg1
- ret <4 x i32> %res
-; CHECK-LABEL: test_xor_v4i32
-; CHECK: pxor
-; MIPS32-LABEL: test_xor_v4i32
-; MIPS32: xor
-; MIPS32: xor
-; MIPS32: xor
-; MIPS32: xor
-}
-
-define internal <4 x i32> @test_sub_v4i32(<4 x i32> %arg0, <4 x i32> %arg1) {
-entry:
- %res = sub <4 x i32> %arg0, %arg1
- ret <4 x i32> %res
-; CHECK-LABEL: test_sub_v4i32
-; CHECK: psubd
-; MIPS32-LABEL: test_sub_v4i32
-; MIPS32: subu
-; MIPS32: subu
-; MIPS32: subu
-; MIPS32: subu
-}
-
-define internal <4 x i32> @test_mul_v4i32(<4 x i32> %arg0, <4 x i32> %arg1) {
-entry:
- %res = mul <4 x i32> %arg0, %arg1
- ret <4 x i32> %res
-; CHECK-LABEL: test_mul_v4i32
-; CHECK: pmuludq
-; CHECK: pmuludq
-;
-; SSE41-LABEL: test_mul_v4i32
-; SSE41: pmulld
-; MIPS32-LABEL: test_mul_v4i32
-; MIPS32: mul
-; MIPS32: mul
-; MIPS32: mul
-; MIPS32: mul
-}
-
-define internal <4 x i32> @test_shl_v4i32(<4 x i32> %arg0, <4 x i32> %arg1) {
-entry:
- %res = shl <4 x i32> %arg0, %arg1
- ret <4 x i32> %res
-; CHECK-LABEL: test_shl_v4i32
-; CHECK: shl
-; CHECK: shl
-; CHECK: shl
-; CHECK: shl
-
-; This line is to ensure that pmulld is generated in test_mul_v4i32 above.
-; SSE41-LABEL: test_shl_v4i32
-; MIPS32-LABEL: test_shl_v4i32
-; MIPS32: sllv
-; MIPS32: sllv
-; MIPS32: sllv
-; MIPS32: sllv
-}
-
-define internal <4 x i32> @test_lshr_v4i32(<4 x i32> %arg0, <4 x i32> %arg1) {
-entry:
- %res = lshr <4 x i32> %arg0, %arg1
- ret <4 x i32> %res
-; CHECK-LABEL: test_lshr_v4i32
-; CHECK: shr
-; CHECK: shr
-; CHECK: shr
-; CHECK: shr
-; MIPS32-LABEL: test_lshr_v4i32
-; MIPS32: srlv
-; MIPS32: srlv
-; MIPS32: srlv
-; MIPS32: srlv
-}
-
-define internal <4 x i32> @test_ashr_v4i32(<4 x i32> %arg0, <4 x i32> %arg1) {
-entry:
- %res = ashr <4 x i32> %arg0, %arg1
- ret <4 x i32> %res
-; CHECK-LABEL: test_ashr_v4i32
-; CHECK: sar
-; CHECK: sar
-; CHECK: sar
-; CHECK: sar
-; MIPS32-LABEL: test_ashr_v4i32
-; MIPS32: srav
-; MIPS32: srav
-; MIPS32: srav
-; MIPS32: srav
-}
-
-define internal <4 x i32> @test_udiv_v4i32(<4 x i32> %arg0, <4 x i32> %arg1) {
-entry:
- %res = udiv <4 x i32> %arg0, %arg1
- ret <4 x i32> %res
-; CHECK-LABEL: test_udiv_v4i32
-; CHECK: div
-; CHECK: div
-; CHECK: div
-; CHECK: div
-; MIPS32-LABEL: test_udiv_v4i32
-; MIPS32: divu
-; MIPS32: divu
-; MIPS32: divu
-; MIPS32: divu
-}
-
-define internal <4 x i32> @test_sdiv_v4i32(<4 x i32> %arg0, <4 x i32> %arg1) {
-entry:
- %res = sdiv <4 x i32> %arg0, %arg1
- ret <4 x i32> %res
-; CHECK-LABEL: test_sdiv_v4i32
-; CHECK: idiv
-; CHECK: idiv
-; CHECK: idiv
-; CHECK: idiv
-; MIPS32-LABEL: test_sdiv_v4i32
-; MIPS32: div
-; MIPS32: div
-; MIPS32: div
-; MIPS32: div
-}
-
-define internal <4 x i32> @test_urem_v4i32(<4 x i32> %arg0, <4 x i32> %arg1) {
-entry:
- %res = urem <4 x i32> %arg0, %arg1
- ret <4 x i32> %res
-; CHECK-LABEL: test_urem_v4i32
-; CHECK: div
-; CHECK: div
-; CHECK: div
-; CHECK: div
-; MIPS32-LABEL: test_urem_v4i32
-; MIPS32: divu
-; MIPS32: divu
-; MIPS32: divu
-; MIPS32: divu
-}
-
-define internal <4 x i32> @test_srem_v4i32(<4 x i32> %arg0, <4 x i32> %arg1) {
-entry:
- %res = srem <4 x i32> %arg0, %arg1
- ret <4 x i32> %res
-; CHECK-LABEL: test_srem_v4i32
-; CHECK: idiv
-; CHECK: idiv
-; CHECK: idiv
-; CHECK: idiv
-; MIPS32-LABEL: test_srem_v4i32
-; MIPS32: div
-; MIPS32: div
-; MIPS32: div
-; MIPS32: div
-}
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/vector-bitcast.ll b/third_party/subzero/tests_lit/llvm2ice_tests/vector-bitcast.ll
deleted file mode 100644
index e7ac594..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/vector-bitcast.ll
+++ /dev/null
@@ -1,261 +0,0 @@
-; This file tests bitcasts of vector type. For most operations, these
-; should be lowered to a no-op on -O2.
-
-; RUN: %p2i -i %s --filetype=obj --disassemble --target=x8632 --args -O2 \
-; RUN: | FileCheck --check-prefix=X86-O2 --check-prefix=X86 %s
-; RUN: %p2i -i %s --filetype=obj --disassemble --target=x8632 --args -Om1 \
-; RUN: | FileCheck --check-prefix=X86 %s
-
-; RUN: %p2i -i %s --filetype=obj --disassemble --target=x8664 --args -O2 \
-; RUN: | FileCheck --check-prefix=X86-O2 --check-prefix=X86 %s
-; RUN: %p2i -i %s --filetype=obj --disassemble --target=x8664 --args -Om1 \
-; RUN: | FileCheck --check-prefix=X86 %s
-
-; RUN: %p2i -i %s --filetype=obj --disassemble --target=arm32 --args -O2 \
-; RUN: | FileCheck --check-prefix=ARM32-O2-O2 --check-prefix=ARM32 %s
-; RUN: %p2i -i %s --filetype=obj --disassemble --target=arm32 --args -Om1 \
-; RUN: | FileCheck --check-prefix=ARM32 %s
-
-define internal <16 x i8> @test_bitcast_v16i8_to_v16i8(<16 x i8> %arg) {
-entry:
- %res = bitcast <16 x i8> %arg to <16 x i8>
- ret <16 x i8> %res
-
-; X86-O2-LABEL: test_bitcast_v16i8_to_v16i8
-; X86-O2-NEXT: ret
-
-; ARM32-O2-LABEL: test_bitcast_v16i8_to_v16i8
-; ARM32-O2-NEXT: bx
-}
-
-define internal <8 x i16> @test_bitcast_v16i8_to_v8i16(<16 x i8> %arg) {
-entry:
- %res = bitcast <16 x i8> %arg to <8 x i16>
- ret <8 x i16> %res
-
-; X86-O2-LABEL: test_bitcast_v16i8_to_v8i16
-; X86-O2-NEXT: ret
-
-; ARM32-O2-LABEL: test_bitcast_v16i8_to_v8i16
-; ARM32-O2-NEXT: bx
-}
-
-define internal <4 x i32> @test_bitcast_v16i8_to_v4i32(<16 x i8> %arg) {
-entry:
- %res = bitcast <16 x i8> %arg to <4 x i32>
- ret <4 x i32> %res
-
-; X86-O2-LABEL: test_bitcast_v16i8_to_v4i32
-; X86-O2-NEXT: ret
-
-; ARM32-O2-LABEL: test_bitcast_v16i8_to_v4i32
-; ARM32-O2-NEXT: bx
-}
-
-define internal <4 x float> @test_bitcast_v16i8_to_v4f32(<16 x i8> %arg) {
-entry:
- %res = bitcast <16 x i8> %arg to <4 x float>
- ret <4 x float> %res
-
-; X86-O2-LABEL: test_bitcast_v16i8_to_v4f32
-; X86-O2-NEXT: ret
-
-; ARM32-O2-LABEL: test_bitcast_v16i8_to_v4f32
-; ARM32-O2-NEXT: bx
-}
-
-define internal <16 x i8> @test_bitcast_v8i16_to_v16i8(<8 x i16> %arg) {
-entry:
- %res = bitcast <8 x i16> %arg to <16 x i8>
- ret <16 x i8> %res
-
-; X86-O2-LABEL: test_bitcast_v8i16_to_v16i8
-; X86-O2-NEXT: ret
-
-; ARM32-O2-LABEL: test_bitcast_v8i16_to_v16i8
-; ARM32-O2-NEXT: bx
-}
-
-define internal <8 x i16> @test_bitcast_v8i16_to_v8i16(<8 x i16> %arg) {
-entry:
- %res = bitcast <8 x i16> %arg to <8 x i16>
- ret <8 x i16> %res
-
-; X86-O2-LABEL: test_bitcast_v8i16_to_v8i16
-; X86-O2-NEXT: ret
-
-; ARM32-O2-LABEL: test_bitcast_v8i16_to_v8i16
-; ARM32-O2-NEXT: bx
-}
-
-define internal <4 x i32> @test_bitcast_v8i16_to_v4i32(<8 x i16> %arg) {
-entry:
- %res = bitcast <8 x i16> %arg to <4 x i32>
- ret <4 x i32> %res
-
-; X86-O2-LABEL: test_bitcast_v8i16_to_v4i32
-; X86-O2-NEXT: ret
-
-; ARM32-O2-LABEL: test_bitcast_v8i16_to_v4i32
-; ARM32-O2-NEXT: bx
-}
-
-define internal <4 x float> @test_bitcast_v8i16_to_v4f32(<8 x i16> %arg) {
-entry:
- %res = bitcast <8 x i16> %arg to <4 x float>
- ret <4 x float> %res
-
-; X86-O2-LABEL: test_bitcast_v8i16_to_v4f32
-; X86-O2-NEXT: ret
-
-; ARM32-O2-LABEL: test_bitcast_v8i16_to_v4f32
-; ARM32-O2-NEXT: bx
-}
-
-define internal <16 x i8> @test_bitcast_v4i32_to_v16i8(<4 x i32> %arg) {
-entry:
- %res = bitcast <4 x i32> %arg to <16 x i8>
- ret <16 x i8> %res
-
-; X86-O2-LABEL: test_bitcast_v4i32_to_v16i8
-; X86-O2-NEXT: ret
-
-; ARM32-O2-LABEL: test_bitcast_v4i32_to_v16i8
-; ARM32-O2-NEXT: bx
-}
-
-define internal <8 x i16> @test_bitcast_v4i32_to_v8i16(<4 x i32> %arg) {
-entry:
- %res = bitcast <4 x i32> %arg to <8 x i16>
- ret <8 x i16> %res
-
-; X86-O2-LABEL: test_bitcast_v4i32_to_v8i16
-; X86-O2-NEXT: ret
-
-; ARM32-O2-LABEL: test_bitcast_v4i32_to_v8i16
-; ARM32-O2-NEXT: bx
-}
-
-define internal <4 x i32> @test_bitcast_v4i32_to_v4i32(<4 x i32> %arg) {
-entry:
- %res = bitcast <4 x i32> %arg to <4 x i32>
- ret <4 x i32> %res
-
-; X86-O2-LABEL: test_bitcast_v4i32_to_v4i32
-; X86-O2-NEXT: ret
-
-; ARM32-O2-LABEL: test_bitcast_v4i32_to_v4i32
-; ARM32-O2-NEXT: bx
-}
-
-define internal <4 x float> @test_bitcast_v4i32_to_v4f32(<4 x i32> %arg) {
-entry:
- %res = bitcast <4 x i32> %arg to <4 x float>
- ret <4 x float> %res
-
-; X86-O2-LABEL: test_bitcast_v4i32_to_v4f32
-; X86-O2-NEXT: ret
-
-; ARM32-O2-LABEL: test_bitcast_v4i32_to_v4f32
-; ARM32-O2-NEXT: bx
-}
-
-define internal <16 x i8> @test_bitcast_v4f32_to_v16i8(<4 x float> %arg) {
-entry:
- %res = bitcast <4 x float> %arg to <16 x i8>
- ret <16 x i8> %res
-
-; X86-O2-LABEL: test_bitcast_v4f32_to_v16i8
-; X86-O2-NEXT: ret
-
-; ARM32-O2-LABEL: test_bitcast_v4f32_to_v16i8
-; ARM32-O2-NEXT: bx
-}
-
-define internal <8 x i16> @test_bitcast_v4f32_to_v8i16(<4 x float> %arg) {
-entry:
- %res = bitcast <4 x float> %arg to <8 x i16>
- ret <8 x i16> %res
-
-; X86-O2-LABEL: test_bitcast_v4f32_to_v8i16
-; X86-O2-NEXT: ret
-
-; ARM32-O2-LABEL: test_bitcast_v4f32_to_v8i16
-; ARM32-O2-NEXT: bx
-}
-
-define internal <4 x i32> @test_bitcast_v4f32_to_v4i32(<4 x float> %arg) {
-entry:
- %res = bitcast <4 x float> %arg to <4 x i32>
- ret <4 x i32> %res
-
-; X86-O2-LABEL: test_bitcast_v4f32_to_v4i32
-; X86-O2-NEXT: ret
-
-; ARM32-O2-LABEL: test_bitcast_v4f32_to_v4i32
-; ARM32-O2-NEXT: bx
-}
-
-define internal <4 x float> @test_bitcast_v4f32_to_v4f32(<4 x float> %arg) {
-entry:
- %res = bitcast <4 x float> %arg to <4 x float>
- ret <4 x float> %res
-
-; X86-O2-LABEL: test_bitcast_v4f32_to_v4f32
-; X86-O2-NEXT: ret
-
-; ARM32-O2-LABEL: test_bitcast_v4f32_to_v4f32
-; ARM32-O2-NEXT: bx
-}
-
-define internal i32 @test_bitcast_v8i1_to_i8(<8 x i1> %arg) {
-entry:
- %res = bitcast <8 x i1> %arg to i8
- %res.i32 = zext i8 %res to i32
- ret i32 %res.i32
-
-; X86-LABEL: test_bitcast_v8i1_to_i8
-; X86: call {{.*}} R_{{.*}} __Sz_bitcast_8xi1_i8
-
-; ARM32-LABEL: test_bitcast_v8i1_to_i8
-; ARM32: bl {{.*}} __Sz_bitcast_8xi1_i8
-}
-
-define internal i32 @test_bitcast_v16i1_to_i16(<16 x i1> %arg) {
-entry:
- %res = bitcast <16 x i1> %arg to i16
- %res.i32 = zext i16 %res to i32
- ret i32 %res.i32
-
-; X86-LABEL: test_bitcast_v16i1_to_i16
-; X86: call {{.*}} __Sz_bitcast_16xi1_i16
-
-; ARM32-LABEL: test_bitcast_v16i1_to_i16
-; ARM32: bl {{.*}} __Sz_bitcast_16xi1_i16
-}
-
-define internal <8 x i1> @test_bitcast_i8_to_v8i1(i32 %arg) {
-entry:
- %arg.trunc = trunc i32 %arg to i8
- %res = bitcast i8 %arg.trunc to <8 x i1>
- ret <8 x i1> %res
-
-; X86-LABEL: test_bitcast_i8_to_v8i1
-; X86: call {{.*}} R_{{.*}} __Sz_bitcast_i8_8xi1
-
-; ARM32-LABEL: test_bitcast_i8_to_v8i1
-; ARM32: bl {{.*}} __Sz_bitcast_i8_8xi1
-}
-
-define internal <16 x i1> @test_bitcast_i16_to_v16i1(i32 %arg) {
-entry:
- %arg.trunc = trunc i32 %arg to i16
- %res = bitcast i16 %arg.trunc to <16 x i1>
- ret <16 x i1> %res
-
-; X86-LABEL: test_bitcast_i16_to_v16i1
-; X86: call {{.*}} R_{{.*}} __Sz_bitcast_i16_16xi1
-
-; ARM32-LABEL: test_bitcast_i16_to_v16i1
-; ARM32: bl {{.*}} __Sz_bitcast_i16_16xi1
-}
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/vector-cast.ll b/third_party/subzero/tests_lit/llvm2ice_tests/vector-cast.ll
deleted file mode 100644
index 13c2acd..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/vector-cast.ll
+++ /dev/null
@@ -1,847 +0,0 @@
-; This file tests casting / conversion operations that apply to vector types.
-; bitcast operations are in vector-bitcast.ll.
-
-; RUN: %p2i -i %s --target=x8632 --filetype=obj --disassemble --args -O2 \
-; RUN: | FileCheck %s --check-prefix=X8632 --check-prefix=CHECK
-; RUN: %p2i -i %s --target=x8632 --filetype=obj --disassemble --args -Om1 \
-; RUN: | FileCheck %s --check-prefix=X8632 --check-prefix=CHECK
-
-; RUN: %p2i -i %s --target=arm32 --filetype=obj --disassemble --args -O2 \
-; RUN: | FileCheck %s --check-prefix=ARM32 --check-prefix=CHECK
-; RUN: %p2i -i %s --target=arm32 --filetype=obj --disassemble --args -Om1 \
-; RUN: | FileCheck %s --check-prefix=ARM32 --check-prefix=CHECK
-
-; RUN: %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command %p2i --filetype=asm --assemble --disassemble --target \
-; RUN: mips32 -i %s --args -O2 -allow-externally-defined-symbols \
-; RUN: | %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command FileCheck --check-prefix MIPS32 %s
-
-; sext operations
-
-define internal <16 x i8> @test_sext_v16i1_to_v16i8(<16 x i1> %arg) {
-entry:
- %res = sext <16 x i1> %arg to <16 x i8>
- ret <16 x i8> %res
-
-; CHECK-LABEL: test_sext_v16i1_to_v16i8
-; X8632: pxor
-; X8632: pcmpeqb
-; X8632: psubb
-; X8632: pand
-; X8632: pxor
-; X8632: pcmpgtb
-; ARM32: vshl.s8
-; ARM32-NEXT: vshr.s8
-; MIPS32: move t2,a0
-; MIPS32: andi t2,t2,0xff
-; MIPS32: andi t2,t2,0x1
-; MIPS32: sll t2,t2,0x1f
-; MIPS32: sra t2,t2,0x1f
-; MIPS32: andi t2,t2,0xff
-; MIPS32: srl v0,v0,0x8
-; MIPS32: sll v0,v0,0x8
-; MIPS32: or t2,t2,v0
-; MIPS32: move v0,a0
-; MIPS32: srl v0,v0,0x8
-; MIPS32: andi v0,v0,0xff
-; MIPS32: andi v0,v0,0x1
-; MIPS32: sll v0,v0,0x1f
-; MIPS32: sra v0,v0,0x1f
-; MIPS32: andi v0,v0,0xff
-; MIPS32: sll v0,v0,0x8
-; MIPS32: lui t3,0xffff
-; MIPS32: ori t3,t3,0xff
-; MIPS32: and t2,t2,t3
-; MIPS32: or v0,v0,t2
-; MIPS32: move t2,a0
-; MIPS32: srl t2,t2,0x10
-; MIPS32: andi t2,t2,0xff
-; MIPS32: andi t2,t2,0x1
-; MIPS32: sll t2,t2,0x1f
-; MIPS32: sra t2,t2,0x1f
-; MIPS32: andi t2,t2,0xff
-; MIPS32: sll t2,t2,0x10
-; MIPS32: lui t3,0xff00
-; MIPS32: ori t3,t3,0xffff
-; MIPS32: and v0,v0,t3
-; MIPS32: or t2,t2,v0
-; MIPS32: srl a0,a0,0x18
-; MIPS32: andi a0,a0,0x1
-; MIPS32: sll a0,a0,0x1f
-; MIPS32: sra a0,a0,0x1f
-; MIPS32: sll a0,a0,0x18
-; MIPS32: sll t2,t2,0x8
-; MIPS32: srl t2,t2,0x8
-; MIPS32: or a0,a0,t2
-; MIPS32: move v0,a1
-; MIPS32: andi v0,v0,0xff
-; MIPS32: andi v0,v0,0x1
-; MIPS32: sll v0,v0,0x1f
-; MIPS32: sra v0,v0,0x1f
-; MIPS32: andi v0,v0,0xff
-; MIPS32: srl v1,v1,0x8
-; MIPS32: sll v1,v1,0x8
-; MIPS32: or v0,v0,v1
-; MIPS32: move v1,a1
-; MIPS32: srl v1,v1,0x8
-; MIPS32: andi v1,v1,0xff
-; MIPS32: andi v1,v1,0x1
-; MIPS32: sll v1,v1,0x1f
-; MIPS32: sra v1,v1,0x1f
-; MIPS32: andi v1,v1,0xff
-; MIPS32: sll v1,v1,0x8
-; MIPS32: lui t2,0xffff
-; MIPS32: ori t2,t2,0xff
-; MIPS32: and v0,v0,t2
-; MIPS32: or v1,v1,v0
-; MIPS32: move v0,a1
-; MIPS32: srl v0,v0,0x10
-; MIPS32: andi v0,v0,0xff
-; MIPS32: andi v0,v0,0x1
-; MIPS32: sll v0,v0,0x1f
-; MIPS32: sra v0,v0,0x1f
-; MIPS32: andi v0,v0,0xff
-; MIPS32: sll v0,v0,0x10
-; MIPS32: lui t2,0xff00
-; MIPS32: ori t2,t2,0xffff
-; MIPS32: and v1,v1,t2
-; MIPS32: or v0,v0,v1
-; MIPS32: srl a1,a1,0x18
-; MIPS32: andi a1,a1,0x1
-; MIPS32: sll a1,a1,0x1f
-; MIPS32: sra a1,a1,0x1f
-; MIPS32: sll a1,a1,0x18
-; MIPS32: sll v0,v0,0x8
-; MIPS32: srl v0,v0,0x8
-; MIPS32: or a1,a1,v0
-; MIPS32: move v0,a2
-; MIPS32: andi v0,v0,0xff
-; MIPS32: andi v0,v0,0x1
-; MIPS32: sll v0,v0,0x1f
-; MIPS32: sra v0,v0,0x1f
-; MIPS32: andi v0,v0,0xff
-; MIPS32: srl t0,t0,0x8
-; MIPS32: sll t0,t0,0x8
-; MIPS32: or v0,v0,t0
-; MIPS32: move v1,a2
-; MIPS32: srl v1,v1,0x8
-; MIPS32: andi v1,v1,0xff
-; MIPS32: andi v1,v1,0x1
-; MIPS32: sll v1,v1,0x1f
-; MIPS32: sra v1,v1,0x1f
-; MIPS32: andi v1,v1,0xff
-; MIPS32: sll v1,v1,0x8
-; MIPS32: lui t0,0xffff
-; MIPS32: ori t0,t0,0xff
-; MIPS32: and v0,v0,t0
-; MIPS32: or v1,v1,v0
-; MIPS32: move v0,a2
-; MIPS32: srl v0,v0,0x10
-; MIPS32: andi v0,v0,0xff
-; MIPS32: andi v0,v0,0x1
-; MIPS32: sll v0,v0,0x1f
-; MIPS32: sra v0,v0,0x1f
-; MIPS32: andi v0,v0,0xff
-; MIPS32: sll v0,v0,0x10
-; MIPS32: lui t0,0xff00
-; MIPS32: ori t0,t0,0xffff
-; MIPS32: and v1,v1,t0
-; MIPS32: or v0,v0,v1
-; MIPS32: srl a2,a2,0x18
-; MIPS32: andi a2,a2,0x1
-; MIPS32: sll a2,a2,0x1f
-; MIPS32: sra a2,a2,0x1f
-; MIPS32: sll a2,a2,0x18
-; MIPS32: sll v0,v0,0x8
-; MIPS32: srl v0,v0,0x8
-; MIPS32: or a2,a2,v0
-; MIPS32: move v0,a3
-; MIPS32: andi v0,v0,0xff
-; MIPS32: andi v0,v0,0x1
-; MIPS32: sll v0,v0,0x1f
-; MIPS32: sra v0,v0,0x1f
-; MIPS32: andi v0,v0,0xff
-; MIPS32: srl t1,t1,0x8
-; MIPS32: sll t1,t1,0x8
-; MIPS32: or v0,v0,t1
-; MIPS32: move v1,a3
-; MIPS32: srl v1,v1,0x8
-; MIPS32: andi v1,v1,0xff
-; MIPS32: andi v1,v1,0x1
-; MIPS32: sll v1,v1,0x1f
-; MIPS32: sra v1,v1,0x1f
-; MIPS32: andi v1,v1,0xff
-; MIPS32: sll v1,v1,0x8
-; MIPS32: lui t0,0xffff
-; MIPS32: ori t0,t0,0xff
-; MIPS32: and v0,v0,t0
-; MIPS32: or v1,v1,v0
-; MIPS32: move v0,a3
-; MIPS32: srl v0,v0,0x10
-; MIPS32: andi v0,v0,0xff
-; MIPS32: andi v0,v0,0x1
-; MIPS32: sll v0,v0,0x1f
-; MIPS32: sra v0,v0,0x1f
-; MIPS32: andi v0,v0,0xff
-; MIPS32: sll v0,v0,0x10
-; MIPS32: lui t0,0xff00
-; MIPS32: ori t0,t0,0xffff
-; MIPS32: and v1,v1,t0
-; MIPS32: or v0,v0,v1
-; MIPS32: srl a3,a3,0x18
-; MIPS32: andi a3,a3,0x1
-; MIPS32: sll a3,a3,0x1f
-; MIPS32: sra a3,a3,0x1f
-; MIPS32: sll a3,a3,0x18
-; MIPS32: sll v0,v0,0x8
-; MIPS32: srl v0,v0,0x8
-; MIPS32: or a3,a3,v0
-}
-
-define internal <8 x i16> @test_sext_v8i1_to_v8i16(<8 x i1> %arg) {
-entry:
- %res = sext <8 x i1> %arg to <8 x i16>
- ret <8 x i16> %res
-
-; CHECK-LABEL: test_sext_v8i1_to_v8i16
-; X8632: psllw {{.*}},0xf
-; X8632: psraw {{.*}},0xf
-; ARM32: vshl.s16
-; ARM32-NEXT: vshr.s16
-; MIPS32: move v0,zero
-; MIPS32: move v1,zero
-; MIPS32: move t0,zero
-; MIPS32: move t1,zero
-; MIPS32: move t2,a0
-; MIPS32: andi t2,t2,0xffff
-; MIPS32: andi t2,t2,0x1
-; MIPS32: sll t2,t2,0x1f
-; MIPS32: sra t2,t2,0x1f
-; MIPS32: andi t2,t2,0xffff
-; MIPS32: srl v0,v0,0x10
-; MIPS32: sll v0,v0,0x10
-; MIPS32: or t2,t2,v0
-; MIPS32: srl a0,a0,0x10
-; MIPS32: andi a0,a0,0x1
-; MIPS32: sll a0,a0,0x1f
-; MIPS32: sra a0,a0,0x1f
-; MIPS32: sll a0,a0,0x10
-; MIPS32: sll t2,t2,0x10
-; MIPS32: srl t2,t2,0x10
-; MIPS32: or a0,a0,t2
-; MIPS32: move v0,a1
-; MIPS32: andi v0,v0,0xffff
-; MIPS32: andi v0,v0,0x1
-; MIPS32: sll v0,v0,0x1f
-; MIPS32: sra v0,v0,0x1f
-; MIPS32: andi v0,v0,0xffff
-; MIPS32: srl v1,v1,0x10
-; MIPS32: sll v1,v1,0x10
-; MIPS32: or v0,v0,v1
-; MIPS32: srl a1,a1,0x10
-; MIPS32: andi a1,a1,0x1
-; MIPS32: sll a1,a1,0x1f
-; MIPS32: sra a1,a1,0x1f
-; MIPS32: sll a1,a1,0x10
-; MIPS32: sll v0,v0,0x10
-; MIPS32: srl v0,v0,0x10
-; MIPS32: or a1,a1,v0
-; MIPS32: move v0,a2
-; MIPS32: andi v0,v0,0xffff
-; MIPS32: andi v0,v0,0x1
-; MIPS32: sll v0,v0,0x1f
-; MIPS32: sra v0,v0,0x1f
-; MIPS32: andi v0,v0,0xffff
-; MIPS32: srl t0,t0,0x10
-; MIPS32: sll t0,t0,0x10
-; MIPS32: or v0,v0,t0
-; MIPS32: srl a2,a2,0x10
-; MIPS32: andi a2,a2,0x1
-; MIPS32: sll a2,a2,0x1f
-; MIPS32: sra a2,a2,0x1f
-; MIPS32: sll a2,a2,0x10
-; MIPS32: sll v0,v0,0x10
-; MIPS32: srl v0,v0,0x10
-; MIPS32: or a2,a2,v0
-; MIPS32: move v0,a3
-; MIPS32: andi v0,v0,0xffff
-; MIPS32: andi v0,v0,0x1
-; MIPS32: sll v0,v0,0x1f
-; MIPS32: sra v0,v0,0x1f
-; MIPS32: andi v0,v0,0xffff
-; MIPS32: srl t1,t1,0x10
-; MIPS32: sll t1,t1,0x10
-; MIPS32: or v0,v0,t1
-; MIPS32: srl a3,a3,0x10
-; MIPS32: andi a3,a3,0x1
-; MIPS32: sll a3,a3,0x1f
-; MIPS32: sra a3,a3,0x1f
-; MIPS32: sll a3,a3,0x10
-; MIPS32: sll v0,v0,0x10
-; MIPS32: srl v0,v0,0x10
-; MIPS32: or a3,a3,v0
-}
-
-define internal <4 x i32> @test_sext_v4i1_to_v4i32(<4 x i1> %arg) {
-entry:
- %res = sext <4 x i1> %arg to <4 x i32>
- ret <4 x i32> %res
-
-; CHECK-LABEL: test_sext_v4i1_to_v4i32
-; X8632: pslld {{.*}},0x1f
-; X8632: psrad {{.*}},0x1f
-; ARM32: vshl.s32
-; ARM32-NEXT: vshr.s32
-; MIPS32: andi a0,a0,0x1
-; MIPS32: sll a0,a0,0x1f
-; MIPS32: sra a0,a0,0x1f
-; MIPS32: andi a1,a1,0x1
-; MIPS32: sll a1,a1,0x1f
-; MIPS32: sra a1,a1,0x1f
-; MIPS32: andi a2,a2,0x1
-; MIPS32: sll a2,a2,0x1f
-; MIPS32: sra a2,a2,0x1f
-; MIPS32: andi a3,a3,0x1
-; MIPS32: sll a3,a3,0x1f
-; MIPS32: sra a3,a3,0x1f
-}
-
-; zext operations
-
-define internal <16 x i8> @test_zext_v16i1_to_v16i8(<16 x i1> %arg) {
-entry:
- %res = zext <16 x i1> %arg to <16 x i8>
- ret <16 x i8> %res
-
-; CHECK-LABEL: test_zext_v16i1_to_v16i8
-; X8632: pxor
-; X8632: pcmpeqb
-; X8632: psubb
-; X8632: pand
-; ARM32: vmov.i8 [[S:.*]], #1
-; ARM32-NEXT: vand {{.*}}, [[S]]
-; MIPS32: move t2,a0
-; MIPS32: andi t2,t2,0xff
-; MIPS32: andi t2,t2,0x1
-; MIPS32: andi t2,t2,0x1
-; MIPS32: andi t2,t2,0xff
-; MIPS32: srl v0,v0,0x8
-; MIPS32: sll v0,v0,0x8
-; MIPS32: or t2,t2,v0
-; MIPS32: move v0,a0
-; MIPS32: srl v0,v0,0x8
-; MIPS32: andi v0,v0,0xff
-; MIPS32: andi v0,v0,0x1
-; MIPS32: andi v0,v0,0x1
-; MIPS32: andi v0,v0,0xff
-; MIPS32: sll v0,v0,0x8
-; MIPS32: lui t3,0xffff
-; MIPS32: ori t3,t3,0xff
-; MIPS32: and t2,t2,t3
-; MIPS32: or v0,v0,t2
-; MIPS32: move t2,a0
-; MIPS32: srl t2,t2,0x10
-; MIPS32: andi t2,t2,0xff
-; MIPS32: andi t2,t2,0x1
-; MIPS32: andi t2,t2,0x1
-; MIPS32: andi t2,t2,0xff
-; MIPS32: sll t2,t2,0x10
-; MIPS32: lui t3,0xff00
-; MIPS32: ori t3,t3,0xffff
-; MIPS32: and v0,v0,t3
-; MIPS32: or t2,t2,v0
-; MIPS32: srl a0,a0,0x18
-; MIPS32: andi a0,a0,0x1
-; MIPS32: andi a0,a0,0x1
-; MIPS32: sll a0,a0,0x18
-; MIPS32: sll t2,t2,0x8
-; MIPS32: srl t2,t2,0x8
-; MIPS32: or a0,a0,t2
-; MIPS32: move v0,a1
-; MIPS32: andi v0,v0,0xff
-; MIPS32: andi v0,v0,0x1
-; MIPS32: andi v0,v0,0x1
-; MIPS32: andi v0,v0,0xff
-; MIPS32: srl v1,v1,0x8
-; MIPS32: sll v1,v1,0x8
-; MIPS32: or v0,v0,v1
-; MIPS32: move v1,a1
-; MIPS32: srl v1,v1,0x8
-; MIPS32: andi v1,v1,0xff
-; MIPS32: andi v1,v1,0x1
-; MIPS32: andi v1,v1,0x1
-; MIPS32: andi v1,v1,0xff
-; MIPS32: sll v1,v1,0x8
-; MIPS32: lui t2,0xffff
-; MIPS32: ori t2,t2,0xff
-; MIPS32: and v0,v0,t2
-; MIPS32: or v1,v1,v0
-; MIPS32: move v0,a1
-; MIPS32: srl v0,v0,0x10
-; MIPS32: andi v0,v0,0xff
-; MIPS32: andi v0,v0,0x1
-; MIPS32: andi v0,v0,0x1
-; MIPS32: andi v0,v0,0xff
-; MIPS32: sll v0,v0,0x10
-; MIPS32: lui t2,0xff00
-; MIPS32: ori t2,t2,0xffff
-; MIPS32: and v1,v1,t2
-; MIPS32: or v0,v0,v1
-; MIPS32: srl a1,a1,0x18
-; MIPS32: andi a1,a1,0x1
-; MIPS32: andi a1,a1,0x1
-; MIPS32: sll a1,a1,0x18
-; MIPS32: sll v0,v0,0x8
-; MIPS32: srl v0,v0,0x8
-; MIPS32: or a1,a1,v0
-; MIPS32: move v0,a2
-; MIPS32: andi v0,v0,0xff
-; MIPS32: andi v0,v0,0x1
-; MIPS32: andi v0,v0,0x1
-; MIPS32: andi v0,v0,0xff
-; MIPS32: srl t0,t0,0x8
-; MIPS32: sll t0,t0,0x8
-; MIPS32: or v0,v0,t0
-; MIPS32: move v1,a2
-; MIPS32: srl v1,v1,0x8
-; MIPS32: andi v1,v1,0xff
-; MIPS32: andi v1,v1,0x1
-; MIPS32: andi v1,v1,0x1
-; MIPS32: andi v1,v1,0xff
-; MIPS32: sll v1,v1,0x8
-; MIPS32: lui t0,0xffff
-; MIPS32: ori t0,t0,0xff
-; MIPS32: and v0,v0,t0
-; MIPS32: or v1,v1,v0
-; MIPS32: move v0,a2
-; MIPS32: srl v0,v0,0x10
-; MIPS32: andi v0,v0,0xff
-; MIPS32: andi v0,v0,0x1
-; MIPS32: andi v0,v0,0x1
-; MIPS32: andi v0,v0,0xff
-; MIPS32: sll v0,v0,0x10
-; MIPS32: lui t0,0xff00
-; MIPS32: ori t0,t0,0xffff
-; MIPS32: and v1,v1,t0
-; MIPS32: or v0,v0,v1
-; MIPS32: srl a2,a2,0x18
-; MIPS32: andi a2,a2,0x1
-; MIPS32: andi a2,a2,0x1
-; MIPS32: sll a2,a2,0x18
-; MIPS32: sll v0,v0,0x8
-; MIPS32: srl v0,v0,0x8
-; MIPS32: or a2,a2,v0
-; MIPS32: move v0,a3
-; MIPS32: andi v0,v0,0xff
-; MIPS32: andi v0,v0,0x1
-; MIPS32: andi v0,v0,0x1
-; MIPS32: andi v0,v0,0xff
-; MIPS32: srl t1,t1,0x8
-; MIPS32: sll t1,t1,0x8
-; MIPS32: or v0,v0,t1
-; MIPS32: move v1,a3
-; MIPS32: srl v1,v1,0x8
-; MIPS32: andi v1,v1,0xff
-; MIPS32: andi v1,v1,0x1
-; MIPS32: andi v1,v1,0x1
-; MIPS32: andi v1,v1,0xff
-; MIPS32: sll v1,v1,0x8
-; MIPS32: lui t0,0xffff
-; MIPS32: ori t0,t0,0xff
-; MIPS32: and v0,v0,t0
-; MIPS32: or v1,v1,v0
-; MIPS32: move v0,a3
-; MIPS32: srl v0,v0,0x10
-; MIPS32: andi v0,v0,0xff
-; MIPS32: andi v0,v0,0x1
-; MIPS32: andi v0,v0,0x1
-; MIPS32: andi v0,v0,0xff
-; MIPS32: sll v0,v0,0x10
-; MIPS32: lui t0,0xff00
-; MIPS32: ori t0,t0,0xffff
-; MIPS32: and v1,v1,t0
-; MIPS32: or v0,v0,v1
-; MIPS32: srl a3,a3,0x18
-; MIPS32: andi a3,a3,0x1
-; MIPS32: andi a3,a3,0x1
-; MIPS32: sll a3,a3,0x18
-; MIPS32: sll v0,v0,0x8
-; MIPS32: srl v0,v0,0x8
-; MIPS32: or a3,a3,v0
-}
-
-define internal <8 x i16> @test_zext_v8i1_to_v8i16(<8 x i1> %arg) {
-entry:
- %res = zext <8 x i1> %arg to <8 x i16>
- ret <8 x i16> %res
-
-; CHECK-LABEL: test_zext_v8i1_to_v8i16
-; X8632: pxor
-; X8632: pcmpeqw
-; X8632: psubw
-; X8632: pand
-; ARM32: vmov.i16 [[S:.*]], #1
-; ARM32-NEXT: vand {{.*}}, [[S]]
-; MIPS32: move t2,a0
-; MIPS32: andi t2,t2,0xffff
-; MIPS32: andi t2,t2,0x1
-; MIPS32: andi t2,t2,0x1
-; MIPS32: andi t2,t2,0xffff
-; MIPS32: srl v0,v0,0x10
-; MIPS32: sll v0,v0,0x10
-; MIPS32: or t2,t2,v0
-; MIPS32: srl a0,a0,0x10
-; MIPS32: andi a0,a0,0x1
-; MIPS32: andi a0,a0,0x1
-; MIPS32: sll a0,a0,0x10
-; MIPS32: sll t2,t2,0x10
-; MIPS32: srl t2,t2,0x10
-; MIPS32: or a0,a0,t2
-; MIPS32: move v0,a1
-; MIPS32: andi v0,v0,0xffff
-; MIPS32: andi v0,v0,0x1
-; MIPS32: andi v0,v0,0x1
-; MIPS32: andi v0,v0,0xffff
-; MIPS32: srl v1,v1,0x10
-; MIPS32: sll v1,v1,0x10
-; MIPS32: or v0,v0,v1
-; MIPS32: srl a1,a1,0x10
-; MIPS32: andi a1,a1,0x1
-; MIPS32: andi a1,a1,0x1
-; MIPS32: sll a1,a1,0x10
-; MIPS32: sll v0,v0,0x10
-; MIPS32: srl v0,v0,0x10
-; MIPS32: or a1,a1,v0
-; MIPS32: move v0,a2
-; MIPS32: andi v0,v0,0xffff
-; MIPS32: andi v0,v0,0x1
-; MIPS32: andi v0,v0,0x1
-; MIPS32: andi v0,v0,0xffff
-; MIPS32: srl t0,t0,0x10
-; MIPS32: sll t0,t0,0x10
-; MIPS32: or v0,v0,t0
-; MIPS32: srl a2,a2,0x10
-; MIPS32: andi a2,a2,0x1
-; MIPS32: andi a2,a2,0x1
-; MIPS32: sll a2,a2,0x10
-; MIPS32: sll v0,v0,0x10
-; MIPS32: srl v0,v0,0x10
-; MIPS32: or a2,a2,v0
-; MIPS32: move v0,a3
-; MIPS32: andi v0,v0,0xffff
-; MIPS32: andi v0,v0,0x1
-; MIPS32: andi v0,v0,0x1
-; MIPS32: andi v0,v0,0xffff
-; MIPS32: srl t1,t1,0x10
-; MIPS32: sll t1,t1,0x10
-; MIPS32: or v0,v0,t1
-; MIPS32: srl a3,a3,0x10
-; MIPS32: andi a3,a3,0x1
-; MIPS32: andi a3,a3,0x1
-; MIPS32: sll a3,a3,0x10
-; MIPS32: sll v0,v0,0x10
-; MIPS32: srl v0,v0,0x10
-; MIPS32: or a3,a3,v0
-}
-
-define internal <4 x i32> @test_zext_v4i1_to_v4i32(<4 x i1> %arg) {
-entry:
- %res = zext <4 x i1> %arg to <4 x i32>
- ret <4 x i32> %res
-
-; CHECK-LABEL: test_zext_v4i1_to_v4i32
-; X8632: pxor
-; X8632: pcmpeqd
-; X8632: psubd
-; X8632: pand
-; ARM32: vmov.i32 [[S:.*]], #1
-; ARM32-NEXT: vand {{.*}}, [[S]]
-; MIPS32: andi a0,a0,0x1
-; MIPS32: andi a0,a0,0x1
-; MIPS32: andi a1,a1,0x1
-; MIPS32: andi a1,a1,0x1
-; MIPS32: andi a2,a2,0x1
-; MIPS32: andi a2,a2,0x1
-; MIPS32: andi a3,a3,0x1
-; MIPS32: andi a3,a3,0x1
-}
-
-; trunc operations
-
-define internal <16 x i1> @test_trunc_v16i8_to_v16i1(<16 x i8> %arg) {
-entry:
- %res = trunc <16 x i8> %arg to <16 x i1>
- ret <16 x i1> %res
-
-; CHECK-LABEL: test_trunc_v16i8_to_v16i1
-; X8632: pxor
-; X8632: pcmpeqb
-; X8632: psubb
-; X8632: pand
-; MIPS32: move t2,a0
-; MIPS32: andi t2,t2,0xff
-; MIPS32: andi t2,t2,0x1
-; MIPS32: andi t2,t2,0xff
-; MIPS32: srl v0,v0,0x8
-; MIPS32: sll v0,v0,0x8
-; MIPS32: or t2,t2,v0
-; MIPS32: move v0,a0
-; MIPS32: srl v0,v0,0x8
-; MIPS32: andi v0,v0,0xff
-; MIPS32: andi v0,v0,0x1
-; MIPS32: andi v0,v0,0xff
-; MIPS32: sll v0,v0,0x8
-; MIPS32: lui t3,0xffff
-; MIPS32: ori t3,t3,0xff
-; MIPS32: and t2,t2,t3
-; MIPS32: or v0,v0,t2
-; MIPS32: move t2,a0
-; MIPS32: srl t2,t2,0x10
-; MIPS32: andi t2,t2,0xff
-; MIPS32: andi t2,t2,0x1
-; MIPS32: andi t2,t2,0xff
-; MIPS32: sll t2,t2,0x10
-; MIPS32: lui t3,0xff00
-; MIPS32: ori t3,t3,0xffff
-; MIPS32: and v0,v0,t3
-; MIPS32: or t2,t2,v0
-; MIPS32: srl a0,a0,0x18
-; MIPS32: andi a0,a0,0x1
-; MIPS32: sll a0,a0,0x18
-; MIPS32: sll t2,t2,0x8
-; MIPS32: srl t2,t2,0x8
-; MIPS32: or a0,a0,t2
-; MIPS32: move v0,a1
-; MIPS32: andi v0,v0,0xff
-; MIPS32: andi v0,v0,0x1
-; MIPS32: andi v0,v0,0xff
-; MIPS32: srl v1,v1,0x8
-; MIPS32: sll v1,v1,0x8
-; MIPS32: or v0,v0,v1
-; MIPS32: move v1,a1
-; MIPS32: srl v1,v1,0x8
-; MIPS32: andi v1,v1,0xff
-; MIPS32: andi v1,v1,0x1
-; MIPS32: andi v1,v1,0xff
-; MIPS32: sll v1,v1,0x8
-; MIPS32: lui t2,0xffff
-; MIPS32: ori t2,t2,0xff
-; MIPS32: and v0,v0,t2
-; MIPS32: or v1,v1,v0
-; MIPS32: move v0,a1
-; MIPS32: srl v0,v0,0x10
-; MIPS32: andi v0,v0,0xff
-; MIPS32: andi v0,v0,0x1
-; MIPS32: andi v0,v0,0xff
-; MIPS32: sll v0,v0,0x10
-; MIPS32: lui t2,0xff00
-; MIPS32: ori t2,t2,0xffff
-; MIPS32: and v1,v1,t2
-; MIPS32: or v0,v0,v1
-; MIPS32: srl a1,a1,0x18
-; MIPS32: andi a1,a1,0x1
-; MIPS32: sll a1,a1,0x18
-; MIPS32: sll v0,v0,0x8
-; MIPS32: srl v0,v0,0x8
-; MIPS32: or a1,a1,v0
-; MIPS32: move v0,a2
-; MIPS32: andi v0,v0,0xff
-; MIPS32: andi v0,v0,0x1
-; MIPS32: andi v0,v0,0xff
-; MIPS32: srl t0,t0,0x8
-; MIPS32: sll t0,t0,0x8
-; MIPS32: or v0,v0,t0
-; MIPS32: move v1,a2
-; MIPS32: srl v1,v1,0x8
-; MIPS32: andi v1,v1,0xff
-; MIPS32: andi v1,v1,0x1
-; MIPS32: andi v1,v1,0xff
-; MIPS32: sll v1,v1,0x8
-; MIPS32: lui t0,0xffff
-; MIPS32: ori t0,t0,0xff
-; MIPS32: and v0,v0,t0
-; MIPS32: or v1,v1,v0
-; MIPS32: move v0,a2
-; MIPS32: srl v0,v0,0x10
-; MIPS32: andi v0,v0,0xff
-; MIPS32: andi v0,v0,0x1
-; MIPS32: andi v0,v0,0xff
-; MIPS32: sll v0,v0,0x10
-; MIPS32: lui t0,0xff00
-; MIPS32: ori t0,t0,0xffff
-; MIPS32: and v1,v1,t0
-; MIPS32: or v0,v0,v1
-; MIPS32: srl a2,a2,0x18
-; MIPS32: andi a2,a2,0x1
-; MIPS32: sll a2,a2,0x18
-; MIPS32: sll v0,v0,0x8
-; MIPS32: srl v0,v0,0x8
-; MIPS32: or a2,a2,v0
-; MIPS32: move v0,a3
-; MIPS32: andi v0,v0,0xff
-; MIPS32: andi v0,v0,0x1
-; MIPS32: andi v0,v0,0xff
-; MIPS32: srl t1,t1,0x8
-; MIPS32: sll t1,t1,0x8
-; MIPS32: or v0,v0,t1
-; MIPS32: move v1,a3
-; MIPS32: srl v1,v1,0x8
-; MIPS32: andi v1,v1,0xff
-; MIPS32: andi v1,v1,0x1
-; MIPS32: andi v1,v1,0xff
-; MIPS32: sll v1,v1,0x8
-; MIPS32: lui t0,0xffff
-; MIPS32: ori t0,t0,0xff
-; MIPS32: and v0,v0,t0
-; MIPS32: or v1,v1,v0
-; MIPS32: move v0,a3
-; MIPS32: srl v0,v0,0x10
-; MIPS32: andi v0,v0,0xff
-; MIPS32: andi v0,v0,0x1
-; MIPS32: andi v0,v0,0xff
-; MIPS32: sll v0,v0,0x10
-; MIPS32: lui t0,0xff00
-; MIPS32: ori t0,t0,0xffff
-; MIPS32: and v1,v1,t0
-; MIPS32: or v0,v0,v1
-; MIPS32: srl a3,a3,0x18
-; MIPS32: andi a3,a3,0x1
-; MIPS32: sll a3,a3,0x18
-; MIPS32: sll v0,v0,0x8
-; MIPS32: srl v0,v0,0x8
-; MIPS32: or a3,a3,v0
-}
-
-define internal <8 x i1> @test_trunc_v8i16_to_v8i1(<8 x i16> %arg) {
-entry:
- %res = trunc <8 x i16> %arg to <8 x i1>
- ret <8 x i1> %res
-
-; CHECK-LABEL: test_trunc_v8i16_to_v8i1
-; X8632: pxor
-; X8632: pcmpeqw
-; X8632: psubw
-; X8632: pand
-; MIPS32: move t2,a0
-; MIPS32: andi t2,t2,0xffff
-; MIPS32: andi t2,t2,0xffff
-; MIPS32: srl v0,v0,0x10
-; MIPS32: sll v0,v0,0x10
-; MIPS32: or t2,t2,v0
-; MIPS32: srl a0,a0,0x10
-; MIPS32: sll a0,a0,0x10
-; MIPS32: sll t2,t2,0x10
-; MIPS32: srl t2,t2,0x10
-; MIPS32: or a0,a0,t2
-; MIPS32: move v0,a1
-; MIPS32: andi v0,v0,0xffff
-; MIPS32: andi v0,v0,0xffff
-; MIPS32: srl v1,v1,0x10
-; MIPS32: sll v1,v1,0x10
-; MIPS32: or v0,v0,v1
-; MIPS32: srl a1,a1,0x10
-; MIPS32: sll a1,a1,0x10
-; MIPS32: sll v0,v0,0x10
-; MIPS32: srl v0,v0,0x10
-; MIPS32: or a1,a1,v0
-; MIPS32: move v0,a2
-; MIPS32: andi v0,v0,0xffff
-; MIPS32: andi v0,v0,0xffff
-; MIPS32: srl t0,t0,0x10
-; MIPS32: sll t0,t0,0x10
-; MIPS32: or v0,v0,t0
-; MIPS32: srl a2,a2,0x10
-; MIPS32: sll a2,a2,0x10
-; MIPS32: sll v0,v0,0x10
-; MIPS32: srl v0,v0,0x10
-; MIPS32: or a2,a2,v0
-; MIPS32: move v0,a3
-; MIPS32: andi v0,v0,0xffff
-; MIPS32: andi v0,v0,0xffff
-; MIPS32: srl t1,t1,0x10
-; MIPS32: sll t1,t1,0x10
-; MIPS32: or v0,v0,t1
-; MIPS32: srl a3,a3,0x10
-; MIPS32: sll a3,a3,0x10
-; MIPS32: sll v0,v0,0x10
-; MIPS32: srl v0,v0,0x10
-; MIPS32: or a3,a3,v0
-}
-
-define internal <4 x i1> @test_trunc_v4i32_to_v4i1(<4 x i32> %arg) {
-entry:
- %res = trunc <4 x i32> %arg to <4 x i1>
- ret <4 x i1> %res
-
-; CHECK-LABEL: test_trunc_v4i32_to_v4i1
-; X8632: pxor
-; X8632: pcmpeqd
-; X8632: psubd
-; X8632: pand
-; MIPS32: move v0,a0
-; MIPS32: move v1,a1
-; MIPS32: move a0,a2
-; MIPS32: move a1,a3
-}
-
-; fpto[us]i operations
-
-define internal <4 x i32> @test_fptosi_v4f32_to_v4i32(<4 x float> %arg) {
-entry:
- %res = fptosi <4 x float> %arg to <4 x i32>
- ret <4 x i32> %res
-
-; CHECK-LABEL: test_fptosi_v4f32_to_v4i32
-; X8632: cvttps2dq
-; ARM32: vcvt.s32.f32
-; MIPS32: trunc.w.s $f0,$f0
-; MIPS32: trunc.w.s $f0,$f0
-; MIPS32: trunc.w.s $f0,$f0
-; MIPS32: trunc.w.s $f0,$f0
-}
-
-define internal <4 x i32> @test_fptoui_v4f32_to_v4i32(<4 x float> %arg) {
-entry:
- %res = fptoui <4 x float> %arg to <4 x i32>
- ret <4 x i32> %res
-
-; CHECK-LABEL: test_fptoui_v4f32_to_v4i32
-; X8632: call {{.*}} R_{{.*}} __Sz_fptoui_4xi32_f32
-; ARM32: vcvt.u32.f32
-; MIPS32: trunc.w.s $f0,$f0
-; MIPS32: trunc.w.s $f0,$f0
-; MIPS32: trunc.w.s $f0,$f0
-; MIPS32: trunc.w.s $f0,$f0
-}
-
-; [su]itofp operations
-
-define internal <4 x float> @test_sitofp_v4i32_to_v4f32(<4 x i32> %arg) {
-entry:
- %res = sitofp <4 x i32> %arg to <4 x float>
- ret <4 x float> %res
-
-; CHECK-LABEL: test_sitofp_v4i32_to_v4f32
-; X8632: cvtdq2ps
-; ARM32: vcvt.f32.s32
-; MIPS32: cvt.s.w $f0,$f0
-; MIPS32: cvt.s.w $f0,$f0
-; MIPS32: cvt.s.w $f0,$f0
-; MIPS32: cvt.s.w $f0,$f0
-
-}
-
-define internal <4 x float> @test_uitofp_v4i32_to_v4f32(<4 x i32> %arg) {
-entry:
- %res = uitofp <4 x i32> %arg to <4 x float>
- ret <4 x float> %res
-
-; CHECK-LABEL: test_uitofp_v4i32_to_v4f32
-; X8632: call {{.*}} R_{{.*}} __Sz_uitofp_4xi32_4xf32
-; ARM32: vcvt.f32.u32
-; MIPS32: cvt.s.w $f0,$f0
-; MIPS32: cvt.s.w $f0,$f0
-; MIPS32: cvt.s.w $f0,$f0
-; MIPS32: cvt.s.w $f0,$f0
-}
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/vector-fcmp.ll b/third_party/subzero/tests_lit/llvm2ice_tests/vector-fcmp.ll
deleted file mode 100644
index d092fbc..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/vector-fcmp.ll
+++ /dev/null
@@ -1,377 +0,0 @@
-; This file checks support for comparing vector values with the fcmp
-; instruction.
-
-; RUN: %p2i -i %s --filetype=obj --disassemble -a -O2 | FileCheck %s
-; RUN: %p2i -i %s --filetype=obj --disassemble -a -Om1 | FileCheck %s
-
-; RUN: %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command %p2i --filetype=asm --assemble --disassemble --target mips32\
-; RUN: -i %s --args -O2 \
-; RUN: | %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command FileCheck --check-prefix MIPS32 %s
-
-; Check that sext elimination occurs when the result of the comparison
-; instruction is alrady sign extended. Sign extension to 4 x i32 uses
-; the pslld instruction.
-define internal <4 x i32> @sextElimination(<4 x float> %a, <4 x float> %b) {
-entry:
- %res.trunc = fcmp oeq <4 x float> %a, %b
- %res = sext <4 x i1> %res.trunc to <4 x i32>
- ret <4 x i32> %res
-; CHECK-LABEL: sextElimination
-; CHECK: cmpeqps
-; CHECK-NOT: pslld
-}
-; MIPS32-LABEL: sextElimination
-; MIPS32: c.eq.s
-; MIPS32: li [[R:.*]],1
-; MIPS32: movf [[R]],zero,$fcc0
-; MIPS32: c.eq.s
-; MIPS32: li [[R:.*]],1
-; MIPS32: movf [[R]],zero,$fcc0
-; MIPS32: c.eq.s
-; MIPS32: li [[R:.*]],1
-; MIPS32: movf [[R]],zero,$fcc0
-; MIPS32: c.eq.s
-; MIPS32: li [[R:.*]],1
-; MIPS32: movf [[R]],zero,$fcc0
-
-define internal <4 x i32> @fcmpFalseVector(<4 x float> %a, <4 x float> %b) {
-entry:
- %res.trunc = fcmp false <4 x float> %a, %b
- %res = sext <4 x i1> %res.trunc to <4 x i32>
- ret <4 x i32> %res
-; CHECK-LABEL: fcmpFalseVector
-; CHECK: pxor
-}
-; MIPS32-LABEL: fcmpFalseVector
-; MIPS32: li v0,0
-; MIPS32: li v1,0
-; MIPS32: li a0,0
-; MIPS32: li a1,0
-
-define internal <4 x i32> @fcmpOeqVector(<4 x float> %a, <4 x float> %b) {
-entry:
- %res.trunc = fcmp oeq <4 x float> %a, %b
- %res = sext <4 x i1> %res.trunc to <4 x i32>
- ret <4 x i32> %res
-; CHECK-LABEL: fcmpOeqVector
-; CHECK: cmpeqps
-}
-; MIPS32-LABEL: fcmpOeqVector
-; MIPS32: c.eq.s
-; MIPS32: li [[R:.*]],1
-; MIPS32: movf [[R]],zero,$fcc0
-; MIPS32: c.eq.s
-; MIPS32: li [[R:.*]],1
-; MIPS32: movf [[R]],zero,$fcc0
-; MIPS32: c.eq.s
-; MIPS32: li [[R:.*]],1
-; MIPS32: movf [[R]],zero,$fcc0
-; MIPS32: c.eq.s
-; MIPS32: li [[R:.*]],1
-; MIPS32: movf [[R]],zero,$fcc0
-
-define internal <4 x i32> @fcmpOgeVector(<4 x float> %a, <4 x float> %b) {
-entry:
- %res.trunc = fcmp oge <4 x float> %a, %b
- %res = sext <4 x i1> %res.trunc to <4 x i32>
- ret <4 x i32> %res
-; CHECK-LABEL: fcmpOgeVector
-; CHECK: cmpleps
-}
-; MIPS32-LABEL: fcmpOgeVector
-; MIPS32: c.ult.s
-; MIPS32: li [[R:.*]],1
-; MIPS32: movt [[R]],zero,$fcc0
-; MIPS32: c.ult.s
-; MIPS32: li [[R:.*]],1
-; MIPS32: movt [[R]],zero,$fcc0
-; MIPS32: c.ult.s
-; MIPS32: li [[R:.*]],1
-; MIPS32: movt [[R]],zero,$fcc0
-; MIPS32: c.ult.s
-; MIPS32: li [[R:.*]],1
-; MIPS32: movt [[R]],zero,$fcc0
-
-define internal <4 x i32> @fcmpOgtVector(<4 x float> %a, <4 x float> %b) {
-entry:
- %res.trunc = fcmp ogt <4 x float> %a, %b
- %res = sext <4 x i1> %res.trunc to <4 x i32>
- ret <4 x i32> %res
-; CHECK-LABEL: fcmpOgtVector
-; CHECK: cmpltps
-}
-; MIPS32-LABEL: fcmpOgtVector
-; MIPS32: c.ule.s
-; MIPS32: li [[R:.*]],1
-; MIPS32: movt [[R]],zero,$fcc0
-; MIPS32: c.ule.s
-; MIPS32: li [[R:.*]],1
-; MIPS32: movt [[R]],zero,$fcc0
-; MIPS32: c.ule.s
-; MIPS32: li [[R:.*]],1
-; MIPS32: movt [[R]],zero,$fcc0
-; MIPS32: c.ule.s
-; MIPS32: li [[R:.*]],1
-; MIPS32: movt [[R]],zero,$fcc0
-
-define internal <4 x i32> @fcmpOleVector(<4 x float> %a, <4 x float> %b) {
-entry:
- %res.trunc = fcmp ole <4 x float> %a, %b
- %res = sext <4 x i1> %res.trunc to <4 x i32>
- ret <4 x i32> %res
-; CHECK-LABEL: fcmpOleVector
-; CHECK: cmpleps
-}
-; MIPS32-LABEL: fcmpOleVector
-; MIPS32: c.ole.s
-; MIPS32: li [[R:.*]],1
-; MIPS32: movf [[R]],zero,$fcc0
-; MIPS32: c.ole.s
-; MIPS32: li [[R:.*]],1
-; MIPS32: movf [[R]],zero,$fcc0
-; MIPS32: c.ole.s
-; MIPS32: li [[R:.*]],1
-; MIPS32: movf [[R]],zero,$fcc0
-; MIPS32: c.ole.s
-; MIPS32: li [[R:.*]],1
-; MIPS32: movf [[R]],zero,$fcc0
-
-define internal <4 x i32> @fcmpOltVector(<4 x float> %a, <4 x float> %b) {
-entry:
- %res.trunc = fcmp olt <4 x float> %a, %b
- %res = sext <4 x i1> %res.trunc to <4 x i32>
- ret <4 x i32> %res
-; CHECK-LABEL: fcmpOltVector
-; CHECK: cmpltps
-}
-; MIPS32-LABEL: fcmpOltVector
-; MIPS32: c.olt.s
-; MIPS32: li [[R:.*]],1
-; MIPS32: movf [[R]],zero,$fcc0
-; MIPS32: c.olt.s
-; MIPS32: li [[R:.*]],1
-; MIPS32: movf [[R]],zero,$fcc0
-; MIPS32: c.olt.s
-; MIPS32: li [[R:.*]],1
-; MIPS32: movf [[R]],zero,$fcc0
-; MIPS32: c.olt.s
-; MIPS32: li [[R:.*]],1
-; MIPS32: movf [[R]],zero,$fcc0
-
-define internal <4 x i32> @fcmpOneVector(<4 x float> %a, <4 x float> %b) {
-entry:
- %res.trunc = fcmp one <4 x float> %a, %b
- %res = sext <4 x i1> %res.trunc to <4 x i32>
- ret <4 x i32> %res
-; CHECK-LABEL: fcmpOneVector
-; CHECK: cmpneqps
-; CHECK: cmpordps
-; CHECK: pand
-}
-; MIPS32-LABEL: fcmpOneVector
-; MIPS32: c.ueq.s
-; MIPS32: li [[R:.*]],1
-; MIPS32: movt [[R]],zero,$fcc0
-; MIPS32: c.ueq.s
-; MIPS32: li [[R:.*]],1
-; MIPS32: movt [[R]],zero,$fcc0
-; MIPS32: c.ueq.s
-; MIPS32: li [[R:.*]],1
-; MIPS32: movt [[R]],zero,$fcc0
-; MIPS32: c.ueq.s
-; MIPS32: li [[R:.*]],1
-; MIPS32: movt [[R]],zero,$fcc0
-
-define internal <4 x i32> @fcmpOrdVector(<4 x float> %a, <4 x float> %b) {
-entry:
- %res.trunc = fcmp ord <4 x float> %a, %b
- %res = sext <4 x i1> %res.trunc to <4 x i32>
- ret <4 x i32> %res
-; CHECK-LABEL: fcmpOrdVector
-; CHECK: cmpordps
-}
-; MIPS32-LABEL: fcmpOrdVector
-; MIPS32: c.un.s
-; MIPS32: li [[R:.*]],1
-; MIPS32: movt [[R]],zero,$fcc0
-; MIPS32: c.un.s
-; MIPS32: li [[R:.*]],1
-; MIPS32: movt [[R]],zero,$fcc0
-; MIPS32: c.un.s
-; MIPS32: li [[R:.*]],1
-; MIPS32: movt [[R]],zero,$fcc0
-; MIPS32: c.un.s
-; MIPS32: li [[R:.*]],1
-; MIPS32: movt [[R]],zero,$fcc0
-
-define internal <4 x i32> @fcmpTrueVector(<4 x float> %a, <4 x float> %b) {
-entry:
- %res.trunc = fcmp true <4 x float> %a, %b
- %res = sext <4 x i1> %res.trunc to <4 x i32>
- ret <4 x i32> %res
-; CHECK-LABEL: fcmpTrueVector
-; CHECK: pcmpeqd
-}
-; MIPS32-LABEL: fcmpTrueVector
-; MIPS32: li v0,1
-; MIPS32: li v1,1
-; MIPS32: li a0,1
-; MIPS32: li a1,1
-
-define internal <4 x i32> @fcmpUeqVector(<4 x float> %a, <4 x float> %b) {
-entry:
- %res.trunc = fcmp ueq <4 x float> %a, %b
- %res = sext <4 x i1> %res.trunc to <4 x i32>
- ret <4 x i32> %res
-; CHECK-LABEL: fcmpUeqVector
-; CHECK: cmpeqps
-; CHECK: cmpunordps
-; CHECK: por
-}
-; MIPS32-LABEL: fcmpUeqVector
-; MIPS32: c.ueq.s
-; MIPS32: li [[R:.*]],1
-; MIPS32: movf [[R]],zero,$fcc0
-; MIPS32: c.ueq.s
-; MIPS32: li [[R:.*]],1
-; MIPS32: movf [[R]],zero,$fcc0
-; MIPS32: c.ueq.s
-; MIPS32: li [[R:.*]],1
-; MIPS32: movf [[R]],zero,$fcc0
-; MIPS32: c.ueq.s
-; MIPS32: li [[R:.*]],1
-; MIPS32: movf [[R]],zero,$fcc0
-
-define internal <4 x i32> @fcmpUgeVector(<4 x float> %a, <4 x float> %b) {
-entry:
- %res.trunc = fcmp uge <4 x float> %a, %b
- %res = sext <4 x i1> %res.trunc to <4 x i32>
- ret <4 x i32> %res
-; CHECK-LABEL: fcmpUgeVector
-; CHECK: cmpnltps
-}
-; MIPS32-LABEL: fcmpUgeVector
-; MIPS32: c.olt.s
-; MIPS32: li [[R:.*]],1
-; MIPS32: movt [[R]],zero,$fcc0
-; MIPS32: c.olt.s
-; MIPS32: li [[R:.*]],1
-; MIPS32: movt [[R]],zero,$fcc0
-; MIPS32: c.olt.s
-; MIPS32: li [[R:.*]],1
-; MIPS32: movt [[R]],zero,$fcc0
-; MIPS32: c.olt.s
-; MIPS32: li [[R:.*]],1
-; MIPS32: movt [[R]],zero,$fcc0
-
-define internal <4 x i32> @fcmpUgtVector(<4 x float> %a, <4 x float> %b) {
-entry:
- %res.trunc = fcmp ugt <4 x float> %a, %b
- %res = sext <4 x i1> %res.trunc to <4 x i32>
- ret <4 x i32> %res
-; CHECK-LABEL: fcmpUgtVector
-; CHECK: cmpnleps
-}
-; MIPS32-LABEL: fcmpUgtVector
-; MIPS32: c.ole.s
-; MIPS32: li [[R:.*]],1
-; MIPS32: movt [[R]],zero,$fcc0
-; MIPS32: c.ole.s
-; MIPS32: li [[R:.*]],1
-; MIPS32: movt [[R]],zero,$fcc0
-; MIPS32: c.ole.s
-; MIPS32: li [[R:.*]],1
-; MIPS32: movt [[R]],zero,$fcc0
-; MIPS32: c.ole.s
-; MIPS32: li [[R:.*]],1
-; MIPS32: movt [[R]],zero,$fcc0
-
-define internal <4 x i32> @fcmpUleVector(<4 x float> %a, <4 x float> %b) {
-entry:
- %res.trunc = fcmp ule <4 x float> %a, %b
- %res = sext <4 x i1> %res.trunc to <4 x i32>
- ret <4 x i32> %res
-; CHECK-LABEL: fcmpUleVector
-; CHECK: cmpnltps
-}
-; MIPS32-LABEL: fcmpUleVector
-; MIPS32: c.ule.s
-; MIPS32: li [[R:.*]],1
-; MIPS32: movf [[R]],zero,$fcc0
-; MIPS32: c.ule.s
-; MIPS32: li [[R:.*]],1
-; MIPS32: movf [[R]],zero,$fcc0
-; MIPS32: c.ule.s
-; MIPS32: li [[R:.*]],1
-; MIPS32: movf [[R]],zero,$fcc0
-; MIPS32: c.ule.s
-; MIPS32: li [[R:.*]],1
-; MIPS32: movf [[R]],zero,$fcc0
-
-define internal <4 x i32> @fcmpUltVector(<4 x float> %a, <4 x float> %b) {
-entry:
- %res.trunc = fcmp ult <4 x float> %a, %b
- %res = sext <4 x i1> %res.trunc to <4 x i32>
- ret <4 x i32> %res
-; CHECK-LABEL: fcmpUltVector
-; CHECK: cmpnleps
-}
-; MIPS32-LABEL: fcmpUltVector
-; MIPS32: c.ult.s
-; MIPS32: li [[R:.*]],1
-; MIPS32: movf [[R]],zero,$fcc0
-; MIPS32: c.ult.s
-; MIPS32: li [[R:.*]],1
-; MIPS32: movf [[R]],zero,$fcc0
-; MIPS32: c.ult.s
-; MIPS32: li [[R:.*]],1
-; MIPS32: movf [[R]],zero,$fcc0
-; MIPS32: c.ult.s
-; MIPS32: li [[R:.*]],1
-; MIPS32: movf [[R]],zero,$fcc0
-
-define internal <4 x i32> @fcmpUneVector(<4 x float> %a, <4 x float> %b) {
-entry:
- %res.trunc = fcmp une <4 x float> %a, %b
- %res = sext <4 x i1> %res.trunc to <4 x i32>
- ret <4 x i32> %res
-; CHECK-LABEL: fcmpUneVector
-; CHECK: cmpneqps
-}
-; MIPS32-LABEL: fcmpUneVector
-; MIPS32: c.eq.s
-; MIPS32: li [[R:.*]],1
-; MIPS32: movt [[R]],zero,$fcc0
-; MIPS32: c.eq.s
-; MIPS32: li [[R:.*]],1
-; MIPS32: movt [[R]],zero,$fcc0
-; MIPS32: c.eq.s
-; MIPS32: li [[R:.*]],1
-; MIPS32: movt [[R]],zero,$fcc0
-; MIPS32: c.eq.s
-; MIPS32: li [[R:.*]],1
-; MIPS32: movt [[R]],zero,$fcc0
-
-define internal <4 x i32> @fcmpUnoVector(<4 x float> %a, <4 x float> %b) {
-entry:
- %res.trunc = fcmp uno <4 x float> %a, %b
- %res = sext <4 x i1> %res.trunc to <4 x i32>
- ret <4 x i32> %res
-; CHECK-LABEL: fcmpUnoVector
-; CHECK: cmpunordps
-}
-; MIPS32-LABEL: fcmpUnoVector
-; MIPS32: c.un.s
-; MIPS32: li [[R:.*]],1
-; MIPS32: movf [[R]],zero,$fcc0
-; MIPS32: c.un.s
-; MIPS32: li [[R:.*]],1
-; MIPS32: movf [[R]],zero,$fcc0
-; MIPS32: c.un.s
-; MIPS32: li [[R:.*]],1
-; MIPS32: movf [[R]],zero,$fcc0
-; MIPS32: c.un.s
-; MIPS32: li [[R:.*]],1
-; MIPS32: movf [[R]],zero,$fcc0
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/vector-icmp.ll b/third_party/subzero/tests_lit/llvm2ice_tests/vector-icmp.ll
deleted file mode 100644
index 54fba56..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/vector-icmp.ll
+++ /dev/null
@@ -1,7137 +0,0 @@
-; This file checks support for comparing vector values with the icmp
-; instruction.
-
-; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 | FileCheck %s
-; RUN: %p2i -i %s --filetype=obj --disassemble --args -Om1 | FileCheck %s
-
-; RUN: %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command %p2i --filetype=asm --assemble --disassemble --target mips32\
-; RUN: -i %s --args -O2 \
-; RUN: | %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command FileCheck --check-prefix MIPS32 %s
-
-; Check that sext elimination occurs when the result of the comparison
-; instruction is already sign extended. Sign extension to 4 x i32 uses
-; the pslld instruction on x86.
-define internal <4 x i32> @test_sext_elimination(<4 x i32> %a, <4 x i32> %b) {
-entry:
- %res.trunc = icmp eq <4 x i32> %a, %b
- %res = sext <4 x i1> %res.trunc to <4 x i32>
- ret <4 x i32> %res
-; CHECK-LABEL: test_sext_elimination
-; CHECK: pcmpeqd
-; CHECK-NOT: pslld
-
-; MIPS32-LABEL: test_sext_elimination
-; MIPS32: lw [[T0:.*]],
-; MIPS32: lw [[T1:.*]],
-; MIPS32: lw [[T2:.*]],
-; MIPS32: lw [[T3:.*]],
-; MIPS32: xor [[T4:.*]],a0,[[T0]]
-; MIPS32: sltiu [[T4]],[[T4]],1
-; MIPS32: xor [[T5:.*]],a1,[[T1]]
-; MIPS32: sltiu [[T5]],[[T5]],1
-; MIPS32: xor [[T6:.*]],a2,[[T2]]
-; MIPS32: sltiu [[T6]],[[T6]],1
-; MIPS32: xor [[T7:.*]],a3,[[T3]]
-; MIPS32: sltiu [[T7]],[[T7]],1
-; MIPS32: andi [[T4]],[[T4]],0x1
-; MIPS32: sll [[T4]],[[T4]],0x1f
-; MIPS32: sra [[T4]],[[T4]],0x1f
-; MIPS32: andi [[T5]],[[T5]],0x1
-; MIPS32: sll [[T5]],[[T5]],0x1f
-; MIPS32: sra [[T5]],[[T5]],0x1f
-; MIPS32: andi [[T6]],[[T6]],0x1
-; MIPS32: sll [[T6]],[[T6]],0x1f
-; MIPS32: sra [[T6]],[[T6]],0x1f
-; MIPS32: andi [[T7]],[[T7]],0x1
-; MIPS32: sll [[T7]],[[T7]],0x1f
-; MIPS32: sra [[T7]],[[T7]],0x1f
-; MIPS32: move v0,[[T4]]
-; MIPS32: move v1,[[T5]]
-; MIPS32: move a0,[[T6]]
-; MIPS32: move a1,[[T7]]
-}
-
-define internal <4 x i1> @test_icmp_v4i32_eq(<4 x i32> %a, <4 x i32> %b) {
-entry:
- %res = icmp eq <4 x i32> %a, %b
- ret <4 x i1> %res
-; CHECK-LABEL: test_icmp_v4i32_eq
-; CHECK: pcmpeqd
-
-; MIPS32-LABEL: test_icmp_v4i32_eq
-; MIPS32: lw [[T0:.*]],
-; MIPS32: lw [[T1:.*]],
-; MIPS32: lw [[T2:.*]],
-; MIPS32: lw [[T3:.*]],
-; MIPS32: xor [[T4:.*]],a0,[[T0]]
-; MIPS32: sltiu [[T4]],[[T4]],1
-; MIPS32: xor [[T5:.*]],a1,[[T1]]
-; MIPS32: sltiu [[T5]],[[T5]],1
-; MIPS32: xor [[T6:.*]],a2,[[T2]]
-; MIPS32: sltiu [[T6]],[[T6]],1
-; MIPS32: xor [[T7:.*]],a3,[[T3]]
-; MIPS32: sltiu [[T7]],[[T7]],1
-; MIPS32: move v0,[[T4]]
-; MIPS32: move v1,[[T5]]
-; MIPS32: move a0,[[T6]]
-; MIPS32: move a1,[[T7]]
-}
-
-define internal <4 x i1> @test_icmp_v4i32_ne(<4 x i32> %a, <4 x i32> %b) {
-entry:
- %res = icmp ne <4 x i32> %a, %b
- ret <4 x i1> %res
-; CHECK-LABEL: test_icmp_v4i32_ne
-; CHECK: pcmpeqd
-; CHECK: pxor
-
-; MIPS32-LABEL: test_icmp_v4i32_ne
-; MIPS32: lw [[T0:.*]],
-; MIPS32: lw [[T1:.*]],
-; MIPS32: lw [[T2:.*]],
-; MIPS32: lw [[T3:.*]],
-; MIPS32: xor [[T4:.*]],a0,[[T0]]
-; MIPS32: sltu [[T4]],zero,[[T4]]
-; MIPS32: xor [[T5:.*]],a1,[[T1]]
-; MIPS32: sltu [[T5]],zero,[[T5]]
-; MIPS32: xor [[T6:.*]],a2,[[T2]]
-; MIPS32: sltu [[T6]],zero,[[T6]]
-; MIPS32: xor [[T7:.*]],a3,[[T3]]
-; MIPS32: sltu [[T7]],zero,[[T7]]
-; MIPS32: move v0,[[T4]]
-; MIPS32: move v1,[[T5]]
-; MIPS32: move a0,[[T6]]
-; MIPS32: move a1,[[T7]]
-}
-
-define internal <4 x i1> @test_icmp_v4i32_sgt(<4 x i32> %a, <4 x i32> %b) {
-entry:
- %res = icmp sgt <4 x i32> %a, %b
- ret <4 x i1> %res
-; CHECK: pcmpgtd
-
-; MIPS32-LABEL: test_icmp_v4i32_sgt
-; MIPS32: lw [[T0:.*]],
-; MIPS32: lw [[T1:.*]],
-; MIPS32: lw [[T2:.*]],
-; MIPS32: lw [[T3:.*]],
-; MIPS32: slt v0,[[T0]],[[T4:.*]]
-; MIPS32: slt v1,[[T1]],[[T5:.*]]
-; MIPS32: slt [[T2]],[[T2]],[[T6:.*]]
-; MIPS32: slt [[T3]],[[T3]],[[T7:.*]]
-; MIPS32: move a0,[[T2]]
-; MIPS32: move a1,[[T3]]
-}
-
-define internal <4 x i1> @test_icmp_v4i32_sle(<4 x i32> %a, <4 x i32> %b) {
-entry:
- %res = icmp sle <4 x i32> %a, %b
- ret <4 x i1> %res
-; CHECK-LABEL: test_icmp_v4i32_sle
-; CHECK: pcmpgtd
-; CHECK: pxor
-
-; MIPS32-LABEL: test_icmp_v4i32_sle
-; MIPS32: lw [[T0:.*]],
-; MIPS32: lw [[T1:.*]],
-; MIPS32: lw [[T2:.*]],
-; MIPS32: lw [[T3:.*]],
-; MIPS32: slt [[T0]],[[T0]],[[T4:.*]]
-; MIPS32: xori v0,[[T0]],0x1
-; MIPS32: slt [[T1]],[[T1]],[[T5:.*]]
-; MIPS32: xori v1,[[T1]],0x1
-; MIPS32: slt [[T2]],[[T2]],[[T6:.*]]
-; MIPS32: xori [[T2]],[[T2]],0x1
-; MIPS32: slt [[T3]],[[T3]],[[T7:.*]]
-; MIPS32: xori [[T3]],[[T3]],0x1
-; MIPS32: move a0,[[T2]]
-; MIPS32: move a1,[[T3]]
-}
-
-define internal <4 x i1> @test_icmp_v4i32_slt(<4 x i32> %a, <4 x i32> %b) {
-entry:
- %res = icmp slt <4 x i32> %a, %b
- ret <4 x i1> %res
-; CHECK-LABEL: test_icmp_v4i32_slt
-; CHECK: pcmpgtd
-
-; MIPS32-LABEL: test_icmp_v4i32_slt
-; MIPS32: lw [[T0:.*]],
-; MIPS32: lw [[T1:.*]],
-; MIPS32: lw [[T2:.*]],
-; MIPS32: lw [[T3:.*]],
-; MIPS32: slt [[T4:.*]],a0,[[T0]]
-; MIPS32: slt [[T5:.*]],a1,[[T1]]
-; MIPS32: slt [[T6:.*]],a2,[[T2]]
-; MIPS32: slt [[T7:.*]],a3,[[T3]]
-; MIPS32: move v0,[[T4]]
-; MIPS32: move v1,[[T5]]
-; MIPS32: move a0,[[T6]]
-; MIPS32: move a1,[[T7]]
-}
-
-define internal <4 x i1> @test_icmp_v4i32_uge(<4 x i32> %a, <4 x i32> %b) {
-entry:
- %res = icmp uge <4 x i32> %a, %b
- ret <4 x i1> %res
-; CHECK-LABEL: test_icmp_v4i32_uge
-; CHECK: pxor
-; CHECK: pcmpgtd
-; CHECK: pxor
-
-; MIPS32-LABEL: test_icmp_v4i32_uge
-; MIPS32: lw [[T0:.*]],
-; MIPS32: lw [[T1:.*]],
-; MIPS32: lw [[T2:.*]],
-; MIPS32: lw [[T3:.*]],
-; MIPS32: sltu [[T4:.*]],a0,[[T0]]
-; MIPS32: xori [[T4]],[[T4]],0x1
-; MIPS32: sltu [[T5:.*]],a1,[[T1]]
-; MIPS32: xori [[T5]],[[T5]],0x1
-; MIPS32: sltu [[T6:.*]],a2,[[T2]]
-; MIPS32: xori [[T6]],[[T6]],0x1
-; MIPS32: sltu [[T7:.*]],a3,[[T3]]
-; MIPS32: xori [[T7]],[[T7]],0x1
-; MIPS32: move v0,[[T4]]
-; MIPS32: move v1,[[T5]]
-; MIPS32: move a0,[[T6]]
-; MIPS32: move a1,[[T7]]
-}
-
-define internal <4 x i1> @test_icmp_v4i32_ugt(<4 x i32> %a, <4 x i32> %b) {
-entry:
- %res = icmp ugt <4 x i32> %a, %b
- ret <4 x i1> %res
-; CHECK-LABEL: test_icmp_v4i32_ugt
-; CHECK: pxor
-; CHECK: pcmpgtd
-
-; MIPS32-LABEL: test_icmp_v4i32_ugt
-; MIPS32: lw [[T0:.*]],
-; MIPS32: lw [[T1:.*]],
-; MIPS32: lw [[T2:.*]],
-; MIPS32: lw [[T3:.*]],
-; MIPS32: sltu v0,[[T0]],[[T4:.*]]
-; MIPS32: sltu v1,[[T1]],[[T5:.*]]
-; MIPS32: sltu [[T2]],[[T2]],[[T6:.*]]
-; MIPS32: sltu [[T3]],[[T3]],[[T7:.*]]
-; MIPS32: move a0,[[T2]]
-; MIPS32: move a1,[[T3]]
-}
-
-define internal <4 x i1> @test_icmp_v4i32_ule(<4 x i32> %a, <4 x i32> %b) {
-entry:
- %res = icmp ule <4 x i32> %a, %b
- ret <4 x i1> %res
-; CHECK-LABEL: test_icmp_v4i32_ule
-; CHECK: pxor
-; CHECK: pcmpgtd
-; CHECK: pxor
-
-; MIPS32-LABEL: test_icmp_v4i32_ule
-; MIPS32: lw [[T0:.*]],
-; MIPS32: lw [[T1:.*]],
-; MIPS32: lw [[T2:.*]],
-; MIPS32: lw [[T3:.*]],
-; MIPS32: sltu [[T0]],[[T0]],[[T4:.*]]
-; MIPS32: xori v0,[[T0]],0x1
-; MIPS32: sltu [[T1]],[[T1]],[[T5:.*]]
-; MIPS32: xori v1,[[T1]],0x1
-; MIPS32: sltu [[T2]],[[T2]],[[T6:.*]]
-; MIPS32: xori [[T2]],[[T2]],0x1
-; MIPS32: sltu [[T3]],[[T3]],[[T7:.*]]
-; MIPS32: xori [[T3]],[[T3]],0x1
-; MIPS32: move a0,[[T2]]
-; MIPS32: move a1,[[T3]]
-}
-
-define internal <4 x i1> @test_icmp_v4i32_ult(<4 x i32> %a, <4 x i32> %b) {
-entry:
- %res = icmp ult <4 x i32> %a, %b
- ret <4 x i1> %res
-; CHECK-LABEL: test_icmp_v4i32_ult
-; CHECK: pxor
-; CHECK: pcmpgtd
-
-; MIPS32-LABEL: test_icmp_v4i32_ult
-; MIPS32: lw [[T0:.*]],
-; MIPS32: lw [[T1:.*]],
-; MIPS32: lw [[T2:.*]],
-; MIPS32: lw [[T3:.*]],
-; MIPS32: sltu [[T4:.*]],a0,[[T0]]
-; MIPS32: sltu [[T5:.*]],a1,[[T1]]
-; MIPS32: sltu [[T6:.*]],a2,[[T2]]
-; MIPS32: sltu [[T7:.*]],a3,[[T3]]
-; MIPS32: move v0,[[T4]]
-; MIPS32: move v1,[[T5]]
-; MIPS32: move a0,[[T6]]
-; MIPS32: move a1,[[T7]]
-}
-
-define internal <4 x i1> @test_icmp_v4i1_eq(<4 x i1> %a, <4 x i1> %b) {
-entry:
- %res = icmp eq <4 x i1> %a, %b
- ret <4 x i1> %res
-; CHECK-LABEL: test_icmp_v4i1_eq
-; CHECK: pcmpeqd
-
-; MIPS32-LABEL: test_icmp_v4i1_eq
-; MIPS32: lw [[T0:.*]],
-; MIPS32: lw [[T1:.*]],
-; MIPS32: lw [[T2:.*]],
-; MIPS32: lw [[T3:.*]],
-; MIPS32: andi [[T4:.*]],a0,0x1
-; MIPS32: andi [[T0]],[[T0]],0x1
-; MIPS32: sll [[T4]],[[T4]],0x1f
-; MIPS32: sll [[T0]],[[T0]],0x1f
-; MIPS32: xor [[T4]],[[T4]],[[T0]]
-; MIPS32: sltiu [[T4]],[[T4]],1
-; MIPS32: andi [[T5:.*]],a1,0x1
-; MIPS32: andi [[T1]],[[T1]],0x1
-; MIPS32: sll [[T5]],[[T5]],0x1f
-; MIPS32: sll [[T1]],[[T1]],0x1f
-; MIPS32: xor [[T5]],[[T5]],[[T1]]
-; MIPS32: sltiu [[T5]],[[T5]],1
-; MIPS32: andi [[T6:.*]],a2,0x1
-; MIPS32: andi [[T2]],[[T2]],0x1
-; MIPS32: sll [[T6]],[[T6]],0x1f
-; MIPS32: sll [[T2]],[[T2]],0x1f
-; MIPS32: xor [[T6]],[[T6]],[[T2]]
-; MIPS32: sltiu [[T6]],[[T6]],1
-; MIPS32: andi [[T7:.*]],a3,0x1
-; MIPS32: andi [[T3]],[[T3]],0x1
-; MIPS32: sll [[T7]],[[T7]],0x1f
-; MIPS32: sll [[T3]],[[T3]],0x1f
-; MIPS32: xor [[T7]],[[T7]],[[T3]]
-; MIPS32: sltiu [[T7]],[[T7]],1
-; MIPS32: move v0,[[T4]]
-; MIPS32: move v1,[[T5]]
-; MIPS32: move a0,[[T6]]
-; MIPS32: move a1,[[T7]]
-}
-
-define internal <4 x i1> @test_icmp_v4i1_ne(<4 x i1> %a, <4 x i1> %b) {
-entry:
- %res = icmp ne <4 x i1> %a, %b
- ret <4 x i1> %res
-; CHECK-LABEL: test_icmp_v4i1_ne
-; CHECK: pcmpeqd
-; CHECK: pxor
-
-; MIPS32-LABEL: test_icmp_v4i1_ne
-; MIPS32: lw [[T0:.*]],
-; MIPS32: lw [[T1:.*]],
-; MIPS32: lw [[T2:.*]],
-; MIPS32: lw [[T3:.*]],
-; MIPS32: andi [[T4:.*]],a0,0x1
-; MIPS32: andi [[T0]],[[T0]],0x1
-; MIPS32: sll [[T4]],[[T4]],0x1f
-; MIPS32: sll [[T0]],[[T0]],0x1f
-; MIPS32: xor [[T4]],[[T4]],[[T0]]
-; MIPS32: sltu [[T4]],zero,[[T4]]
-; MIPS32: andi [[T5:.*]],a1,0x1
-; MIPS32: andi [[T1]],[[T1]],0x1
-; MIPS32: sll [[T5]],[[T5]],0x1f
-; MIPS32: sll [[T1]],[[T1]],0x1f
-; MIPS32: xor [[T5]],[[T5]],[[T1]]
-; MIPS32: sltu [[T5]],zero,[[T5]]
-; MIPS32: andi [[T6:.*]],a2,0x1
-; MIPS32: andi [[T2]],[[T2]],0x1
-; MIPS32: sll [[T6]],[[T6]],0x1f
-; MIPS32: sll [[T2]],[[T2]],0x1f
-; MIPS32: xor [[T6]],[[T6]],[[T2]]
-; MIPS32: sltu [[T6]],zero,[[T6]]
-; MIPS32: andi [[T7:.*]],a3,0x1
-; MIPS32: andi [[T3]],[[T3]],0x1
-; MIPS32: sll [[T7]],[[T7]],0x1f
-; MIPS32: sll [[T3]],[[T3]],0x1f
-; MIPS32: xor [[T7]],[[T7]],[[T3]]
-; MIPS32: sltu [[T7]],zero,[[T7]]
-; MIPS32: move v0,[[T4]]
-; MIPS32: move v1,[[T5]]
-; MIPS32: move a0,[[T6]]
-; MIPS32: move a1,[[T7]]
-}
-
-define internal <4 x i1> @test_icmp_v4i1_sgt(<4 x i1> %a, <4 x i1> %b) {
-entry:
- %res = icmp sgt <4 x i1> %a, %b
- ret <4 x i1> %res
-; CHECK-LABEL: test_icmp_v4i1_sgt
-; CHECK: pcmpgtd
-
-; MIPS32-LABEL: test_icmp_v4i1_sgt
-; MIPS32: lw [[T0:.*]],
-; MIPS32: lw [[T1:.*]],
-; MIPS32: lw [[T2:.*]],
-; MIPS32: lw [[T3:.*]],
-; MIPS32: andi [[T4:.*]],a0,0x1
-; MIPS32: andi [[T0]],[[T0]],0x1
-; MIPS32: sll [[T4]],[[T4]],0x1f
-; MIPS32: sll [[T0]],[[T0]],0x1f
-; MIPS32: slt v0,[[T0]],[[T4]]
-; MIPS32: andi [[T5:.*]],a1,0x1
-; MIPS32: andi [[T1]],[[T1]],0x1
-; MIPS32: sll [[T5]],[[T5]],0x1f
-; MIPS32: sll [[T1]],[[T1]],0x1f
-; MIPS32: slt v1,[[T1]],[[T5]]
-; MIPS32: andi [[T6:.*]],a2,0x1
-; MIPS32: andi [[T2]],[[T2]],0x1
-; MIPS32: sll [[T6]],[[T6]],0x1f
-; MIPS32: sll [[T2]],[[T2]],0x1f
-; MIPS32: slt [[T2]],[[T2]],[[T6]]
-; MIPS32: andi [[T7:.*]],a3,0x1
-; MIPS32: andi [[T3]],[[T3]],0x1
-; MIPS32: sll [[T7]],[[T7]],0x1f
-; MIPS32: sll [[T3]],[[T3]],0x1f
-; MIPS32: slt [[T3]],[[T3]],[[T7]]
-; MIPS32: move a0,[[T2]]
-; MIPS32: move a1,[[T3]]
-}
-
-define internal <4 x i1> @test_icmp_v4i1_sle(<4 x i1> %a, <4 x i1> %b) {
-entry:
- %res = icmp sle <4 x i1> %a, %b
- ret <4 x i1> %res
-; CHECK-LABEL: test_icmp_v4i1_sle
-; CHECK: pcmpgtd
-; CHECK: pxor
-
-; MIPS32-LABEL: test_icmp_v4i1_sle
-; MIPS32: lw [[T0:.*]],
-; MIPS32: lw [[T1:.*]],
-; MIPS32: lw [[T2:.*]],
-; MIPS32: lw [[T3:.*]],
-; MIPS32: andi [[T4:.*]],a0,0x1
-; MIPS32: andi [[T0]],[[T0]],0x1
-; MIPS32: sll [[T4]],[[T4]],0x1f
-; MIPS32: sll [[T0]],[[T0]],0x1f
-; MIPS32: slt [[T0]],[[T0]],[[T4]]
-; MIPS32: xori v0,[[T0]],0x1
-; MIPS32: andi [[T5:.*]],a1,0x1
-; MIPS32: andi [[T1]],[[T1]],0x1
-; MIPS32: sll [[T5]],[[T5]],0x1f
-; MIPS32: sll [[T1]],[[T1]],0x1f
-; MIPS32: slt [[T1]],[[T1]],[[T5]]
-; MIPS32: xori v1,[[T1]],0x1
-; MIPS32: andi [[T6:.*]],a2,0x1
-; MIPS32: andi [[T2]],[[T2]],0x1
-; MIPS32: sll [[T6]],[[T6]],0x1f
-; MIPS32: sll [[T2]],[[T2]],0x1f
-; MIPS32: slt [[T2]],[[T2]],[[T6]]
-; MIPS32: xori [[T2]],[[T2]],0x1
-; MIPS32: andi [[T7:.*]],a3,0x1
-; MIPS32: andi [[T3]],[[T3]],0x1
-; MIPS32: sll [[T7]],[[T7]],0x1f
-; MIPS32: sll [[T3]],[[T3]],0x1f
-; MIPS32: slt [[T3]],[[T3]],[[T7]]
-; MIPS32: xori [[T3]],[[T3]],0x1
-; MIPS32: move a0,[[T2]]
-; MIPS32: move a1,[[T3]]
-}
-
-define internal <4 x i1> @test_icmp_v4i1_slt(<4 x i1> %a, <4 x i1> %b) {
-entry:
- %res = icmp slt <4 x i1> %a, %b
- ret <4 x i1> %res
-; CHECK-LABEL: test_icmp_v4i1_slt
-; CHECK: pcmpgtd
-
-; MIPS32-LABEL: test_icmp_v4i1_slt
-; MIPS32: lw [[T0:.*]],
-; MIPS32: lw [[T1:.*]],
-; MIPS32: lw [[T2:.*]],
-; MIPS32: lw [[T3:.*]],
-; MIPS32: andi [[T4:.*]],a0,0x1
-; MIPS32: andi [[T0]],[[T0]],0x1
-; MIPS32: sll [[T4]],[[T4]],0x1f
-; MIPS32: sll [[T0]],[[T0]],0x1f
-; MIPS32: slt [[T4]],[[T4]],[[T0]]
-; MIPS32: andi [[T5:.*]],a1,0x1
-; MIPS32: andi [[T1]],[[T1]],0x1
-; MIPS32: sll [[T5]],[[T5]],0x1f
-; MIPS32: sll [[T1]],[[T1]],0x1f
-; MIPS32: slt [[T5]],[[T5]],[[T1]]
-; MIPS32: andi [[T6:.*]],a2,0x1
-; MIPS32: andi [[T2]],[[T2]],0x1
-; MIPS32: sll [[T6]],[[T6]],0x1f
-; MIPS32: sll [[T2]],[[T2]],0x1f
-; MIPS32: slt [[T6]],[[T6]],[[T2]]
-; MIPS32: andi [[T7:.*]],a3,0x1
-; MIPS32: andi [[T3]],[[T3]],0x1
-; MIPS32: sll [[T7]],[[T7]],0x1f
-; MIPS32: sll [[T3]],[[T3]],0x1f
-; MIPS32: slt [[T7]],[[T7]],[[T3]]
-; MIPS32: move v0,[[T4]]
-; MIPS32: move v1,[[T5]]
-; MIPS32: move a0,[[T6]]
-; MIPS32: move a1,[[T7]]
-}
-
-define internal <4 x i1> @test_icmp_v4i1_uge(<4 x i1> %a, <4 x i1> %b) {
-entry:
- %res = icmp uge <4 x i1> %a, %b
- ret <4 x i1> %res
-; CHECK-LABEL: test_icmp_v4i1_uge
-; CHECK: pxor
-; CHECK: pcmpgtd
-; CHECK: pxor
-
-; MIPS32-LABEL: test_icmp_v4i1_uge
-; MIPS32: lw [[T0:.*]],
-; MIPS32: lw [[T1:.*]],
-; MIPS32: lw [[T2:.*]],
-; MIPS32: lw [[T3:.*]],
-; MIPS32: andi [[T4:.*]],a0,0x1
-; MIPS32: andi [[T0]],[[T0]],0x1
-; MIPS32: sll [[T4]],[[T4]],0x1f
-; MIPS32: sll [[T0]],[[T0]],0x1f
-; MIPS32: sltu [[T4]],[[T4]],[[T0]]
-; MIPS32: xori [[T4]],[[T4]],0x1
-; MIPS32: andi [[T5:.*]],a1,0x1
-; MIPS32: andi [[T1]],[[T1]],0x1
-; MIPS32: sll [[T5]],[[T5]],0x1f
-; MIPS32: sll [[T1]],[[T1]],0x1f
-; MIPS32: sltu [[T5]],[[T5]],[[T1]]
-; MIPS32: xori [[T5]],[[T5]],0x1
-; MIPS32: andi [[T6:.*]],a2,0x1
-; MIPS32: andi [[T2]],[[T2]],0x1
-; MIPS32: sll [[T6]],[[T6]],0x1f
-; MIPS32: sll [[T2]],[[T2]],0x1f
-; MIPS32: sltu [[T6]],[[T6]],[[T2]]
-; MIPS32: xori [[T6]],[[T6]],0x1
-; MIPS32: andi [[T7:.*]],a3,0x1
-; MIPS32: andi [[T3]],[[T3]],0x1
-; MIPS32: sll [[T7]],[[T7]],0x1f
-; MIPS32: sll [[T3]],[[T3]],0x1f
-; MIPS32: sltu [[T7]],[[T7]],[[T3]]
-; MIPS32: xori [[T7]],[[T7]],0x1
-; MIPS32: move v0,[[T4]]
-; MIPS32: move v1,[[T5]]
-; MIPS32: move a0,[[T6]]
-; MIPS32: move a1,[[T7]]
-}
-
-define internal <4 x i1> @test_icmp_v4i1_ugt(<4 x i1> %a, <4 x i1> %b) {
-entry:
- %res = icmp ugt <4 x i1> %a, %b
- ret <4 x i1> %res
-; CHECK-LABEL: test_icmp_v4i1_ugt
-; CHECK: pxor
-; CHECK: pcmpgtd
-
-; MIPS32-LABEL: test_icmp_v4i1_ugt
-; MIPS32: lw [[T0:.*]],
-; MIPS32: lw [[T1:.*]],
-; MIPS32: lw [[T2:.*]],
-; MIPS32: lw [[T3:.*]],
-; MIPS32: andi [[T4:.*]],a0,0x1
-; MIPS32: andi [[T0]],[[T0]],0x1
-; MIPS32: sll [[T4]],[[T4]],0x1f
-; MIPS32: sll [[T0]],[[T0]],0x1f
-; MIPS32: sltu v0,[[T0]],[[T4]]
-; MIPS32: andi [[T5:.*]],a1,0x1
-; MIPS32: andi [[T1]],[[T1]],0x1
-; MIPS32: sll [[T5]],[[T5]],0x1f
-; MIPS32: sll [[T1]],[[T1]],0x1f
-; MIPS32: sltu v1,[[T1]],[[T5]]
-; MIPS32: andi [[T6:.*]],a2,0x1
-; MIPS32: andi [[T2]],[[T2]],0x1
-; MIPS32: sll [[T6]],[[T6]],0x1f
-; MIPS32: sll [[T2]],[[T2]],0x1f
-; MIPS32: sltu [[T2]],[[T2]],[[T6]]
-; MIPS32: andi [[T7:.*]],a3,0x1
-; MIPS32: andi [[T3]],[[T3]],0x1
-; MIPS32: sll [[T7]],[[T7]],0x1f
-; MIPS32: sll [[T3]],[[T3]],0x1f
-; MIPS32: sltu [[T3]],[[T3]],[[T7]]
-; MIPS32: move a0,[[T2]]
-; MIPS32: move a1,[[T3]]
-}
-
-define internal <4 x i1> @test_icmp_v4i1_ule(<4 x i1> %a, <4 x i1> %b) {
-entry:
- %res = icmp ule <4 x i1> %a, %b
- ret <4 x i1> %res
-; CHECK-LABEL: test_icmp_v4i1_ule
-; CHECK: pxor
-; CHECK: pcmpgtd
-; CHECK: pxor
-
-; MIPS32-LABEL: test_icmp_v4i1_ule
-; MIPS32: lw [[T0:.*]],
-; MIPS32: lw [[T1:.*]],
-; MIPS32: lw [[T2:.*]],
-; MIPS32: lw [[T3:.*]],
-; MIPS32: andi [[T4:.*]],a0,0x1
-; MIPS32: andi [[T0]],[[T0]],0x1
-; MIPS32: sll [[T4]],[[T4]],0x1f
-; MIPS32: sll [[T0]],[[T0]],0x1f
-; MIPS32: sltu [[T0]],[[T0]],[[T4]]
-; MIPS32: xori v0,[[T0]],0x1
-; MIPS32: andi [[T5:.*]],a1,0x1
-; MIPS32: andi [[T1]],[[T1]],0x1
-; MIPS32: sll [[T5]],[[T5]],0x1f
-; MIPS32: sll [[T1]],[[T1]],0x1f
-; MIPS32: sltu [[T1]],[[T1]],[[T5]]
-; MIPS32: xori v1,[[T1]],0x1
-; MIPS32: andi [[T6:.*]],a2,0x1
-; MIPS32: andi [[T2]],[[T2]],0x1
-; MIPS32: sll [[T6]],[[T6]],0x1f
-; MIPS32: sll [[T2]],[[T2]],0x1f
-; MIPS32: sltu [[T2]],[[T2]],[[T6]]
-; MIPS32: xori [[T2]],[[T2]],0x1
-; MIPS32: andi [[T7:.*]],a3,0x1
-; MIPS32: andi [[T3]],[[T3]],0x1
-; MIPS32: sll [[T7]],[[T7]],0x1f
-; MIPS32: sll [[T3]],[[T3]],0x1f
-; MIPS32: sltu [[T3]],[[T3]],[[T7]]
-; MIPS32: xori [[T3]],[[T3]],0x1
-; MIPS32: move a0,[[T2]]
-; MIPS32: move a1,[[T3]]
-}
-
-define internal <4 x i1> @test_icmp_v4i1_ult(<4 x i1> %a, <4 x i1> %b) {
-entry:
- %res = icmp ult <4 x i1> %a, %b
- ret <4 x i1> %res
-; CHECK-LABEL: test_icmp_v4i1_ult
-; CHECK: pxor
-; CHECK: pcmpgtd
-
-; MIPS32-LABEL: test_icmp_v4i1_ult
-; MIPS32: lw [[T0:.*]],
-; MIPS32: lw [[T1:.*]],
-; MIPS32: lw [[T2:.*]],
-; MIPS32: lw [[T3:.*]],
-; MIPS32: andi [[T4:.*]],a0,0x1
-; MIPS32: andi [[T0]],[[T0]],0x1
-; MIPS32: sll [[T4]],[[T4]],0x1f
-; MIPS32: sll [[T0]],[[T0]],0x1f
-; MIPS32: sltu [[T4]],[[T4]],[[T0]]
-; MIPS32: andi [[T5:.*]],a1,0x1
-; MIPS32: andi [[T1]],[[T1]],0x1
-; MIPS32: sll [[T5]],[[T5]],0x1f
-; MIPS32: sll [[T1]],[[T1]],0x1f
-; MIPS32: sltu [[T5]],[[T5]],[[T1]]
-; MIPS32: andi [[T6:.*]],a2,0x1
-; MIPS32: andi [[T2]],[[T2]],0x1
-; MIPS32: sll [[T6]],[[T6]],0x1f
-; MIPS32: sll [[T2]],[[T2]],0x1f
-; MIPS32: sltu [[T6]],[[T6]],[[T2]]
-; MIPS32: andi [[T7:.*]],a3,0x1
-; MIPS32: andi [[T3]],[[T3]],0x1
-; MIPS32: sll [[T7]],[[T7]],0x1f
-; MIPS32: sll [[T3]],[[T3]],0x1f
-; MIPS32: sltu [[T7]],[[T7]],[[T3]]
-; MIPS32: move v0,[[T4]]
-; MIPS32: move v1,[[T5]]
-; MIPS32: move a0,[[T6]]
-; MIPS32: move a1,[[T7]]
-}
-
-define internal <8 x i1> @test_icmp_v8i16_eq(<8 x i16> %a, <8 x i16> %b) {
-entry:
- %res = icmp eq <8 x i16> %a, %b
- ret <8 x i1> %res
-; CHECK-LABEL: test_icmp_v8i16_eq
-; CHECK: pcmpeqw
-
-; MIPS32-LABEL: test_icmp_v8i16_eq
-; MIPS32: lw [[T0:.*]],
-; MIPS32: lw [[T1:.*]],
-; MIPS32: lw [[T2:.*]],
-; MIPS32: lw [[T3:.*]],
-; MIPS32: move [[T4:.*]],zero
-; MIPS32: move [[T5:.*]],zero
-; MIPS32: move [[T6:.*]],zero
-; MIPS32: move [[T7:.*]],zero
-; MIPS32: move [[T8:.*]],a0
-; MIPS32: andi [[T8]],[[T8]],0xffff
-; MIPS32: move [[T9:.*]],[[T0]]
-; MIPS32: andi [[T9]],[[T9]],0xffff
-; MIPS32: sll [[T8]],[[T8]],0x10
-; MIPS32: sll [[T9]],[[T9]],0x10
-; MIPS32: xor [[T8]],[[T8]],[[T9]]
-; MIPS32: sltiu [[T8]],[[T8]],1
-; MIPS32: andi [[T8]],[[T8]],0xffff
-; MIPS32: srl [[T4]],[[T4]],0x10
-; MIPS32: sll [[T4]],[[T4]],0x10
-; MIPS32: or [[T8]],[[T8]],[[T4]]
-; MIPS32: srl [[T10:.*]],a0,0x10
-; MIPS32: srl [[T0]],[[T0]],0x10
-; MIPS32: sll [[T10]],[[T10]],0x10
-; MIPS32: sll [[T0]],[[T0]],0x10
-; MIPS32: xor [[T10]],[[T10]],[[T0]]
-; MIPS32: sltiu [[T10]],[[T10]],1
-; MIPS32: sll [[T10]],[[T10]],0x10
-; MIPS32: sll [[T8]],[[T8]],0x10
-; MIPS32: srl [[T8]],[[T8]],0x10
-; MIPS32: or [[T10]],[[T10]],[[T8]]
-; MIPS32: move [[T0]],a1
-; MIPS32: andi [[T0]],[[T0]],0xffff
-; MIPS32: move [[T4]],[[T1]]
-; MIPS32: andi [[T4]],[[T4]],0xffff
-; MIPS32: sll [[T0]],[[T0]],0x10
-; MIPS32: sll [[T4]],[[T4]],0x10
-; MIPS32: xor [[T0]],[[T0]],[[T4]]
-; MIPS32: sltiu [[T0]],[[T0]],1
-; MIPS32: andi [[T0]],[[T0]],0xffff
-; MIPS32: srl [[T5]],[[T5]],0x10
-; MIPS32: sll [[T5]],[[T5]],0x10
-; MIPS32: or [[T0]],[[T0]],[[T5]]
-; MIPS32: srl [[T11:.*]],a1,0x10
-; MIPS32: srl [[T1]],[[T1]],0x10
-; MIPS32: sll [[T11]],[[T11]],0x10
-; MIPS32: sll [[T1]],[[T1]],0x10
-; MIPS32: xor [[T11]],[[T11]],[[T1]]
-; MIPS32: sltiu [[T11]],[[T11]],1
-; MIPS32: sll [[T11]],[[T11]],0x10
-; MIPS32: sll [[T0]],[[T0]],0x10
-; MIPS32: srl [[T0]],[[T0]],0x10
-; MIPS32: or [[T11]],[[T11]],[[T0]]
-; MIPS32: move [[T0]],a2
-; MIPS32: andi [[T0]],[[T0]],0xffff
-; MIPS32: move [[T1]],[[T2]]
-; MIPS32: andi [[T1]],[[T1]],0xffff
-; MIPS32: sll [[T0]],[[T0]],0x10
-; MIPS32: sll [[T1]],[[T1]],0x10
-; MIPS32: xor [[T0]],[[T0]],[[T1]]
-; MIPS32: sltiu [[T0]],[[T0]],1
-; MIPS32: andi [[T0]],[[T0]],0xffff
-; MIPS32: srl [[T6]],[[T6]],0x10
-; MIPS32: sll [[T6]],[[T6]],0x10
-; MIPS32: or [[T0]],[[T0]],[[T6]]
-; MIPS32: srl [[T12:.*]],a2,0x10
-; MIPS32: srl [[T2]],[[T2]],0x10
-; MIPS32: sll [[T12]],[[T12]],0x10
-; MIPS32: sll [[T2]],[[T2]],0x10
-; MIPS32: xor [[T12]],[[T12]],[[T2]]
-; MIPS32: sltiu [[T12]],[[T12]],1
-; MIPS32: sll [[T12]],[[T12]],0x10
-; MIPS32: sll [[T0]],[[T0]],0x10
-; MIPS32: srl [[T0]],[[T0]],0x10
-; MIPS32: or [[T12]],[[T12]],[[T0]]
-; MIPS32: move [[T0]],a3
-; MIPS32: andi [[T0]],[[T0]],0xffff
-; MIPS32: move [[T1]],[[T3]]
-; MIPS32: andi [[T1]],[[T1]],0xffff
-; MIPS32: sll [[T0]],[[T0]],0x10
-; MIPS32: sll [[T1]],[[T1]],0x10
-; MIPS32: xor [[T0]],[[T0]],[[T1]]
-; MIPS32: sltiu [[T0]],[[T0]],1
-; MIPS32: andi [[T0]],[[T0]],0xffff
-; MIPS32: srl [[T7]],[[T7]],0x10
-; MIPS32: sll [[T7]],[[T7]],0x10
-; MIPS32: or [[T0]],[[T0]],[[T7]]
-; MIPS32: srl [[T13:.*]],a3,0x10
-; MIPS32: srl [[T3]],[[T3]],0x10
-; MIPS32: sll [[T13]],[[T13]],0x10
-; MIPS32: sll [[T3]],[[T3]],0x10
-; MIPS32: xor [[T13]],[[T13]],[[T3]]
-; MIPS32: sltiu [[T13]],[[T13]],1
-; MIPS32: sll [[T13]],[[T13]],0x10
-; MIPS32: sll [[T0]],[[T0]],0x10
-; MIPS32: srl [[T0]],[[T0]],0x10
-; MIPS32: or [[T13]],[[T13]],[[T0]]
-; MIPS32: move v0,[[T10]]
-; MIPS32: move v1,[[T11]]
-; MIPS32: move a0,[[T12]]
-; MIPS32: move a1,[[T13]]
-}
-
-define internal <8 x i1> @test_icmp_v8i16_ne(<8 x i16> %a, <8 x i16> %b) {
-entry:
- %res = icmp ne <8 x i16> %a, %b
- ret <8 x i1> %res
-; CHECK-LABEL: test_icmp_v8i16_ne
-; CHECK: pcmpeqw
-; CHECK: pxor
-
-; MIPS32-LABEL: test_icmp_v8i16_ne
-; MIPS32: lw [[T0:.*]],
-; MIPS32: lw [[T1:.*]],
-; MIPS32: lw [[T2:.*]],
-; MIPS32: lw [[T3:.*]],
-; MIPS32: move [[T4:.*]],zero
-; MIPS32: move [[T5:.*]],zero
-; MIPS32: move [[T6:.*]],zero
-; MIPS32: move [[T7:.*]],zero
-; MIPS32: move [[T8:.*]],a0
-; MIPS32: andi [[T8]],[[T8]],0xffff
-; MIPS32: move [[T9:.*]],[[T0]]
-; MIPS32: andi [[T9]],[[T9]],0xffff
-; MIPS32: sll [[T8]],[[T8]],0x10
-; MIPS32: sll [[T9]],[[T9]],0x10
-; MIPS32: xor [[T8]],[[T8]],[[T9]]
-; MIPS32: sltu [[T8]],zero,[[T8]]
-; MIPS32: andi [[T8]],[[T8]],0xffff
-; MIPS32: srl [[T4]],[[T4]],0x10
-; MIPS32: sll [[T4]],[[T4]],0x10
-; MIPS32: or [[T8]],[[T8]],[[T4]]
-; MIPS32: srl [[T10:.*]],a0,0x10
-; MIPS32: srl [[T0]],[[T0]],0x10
-; MIPS32: sll [[T10]],[[T10]],0x10
-; MIPS32: sll [[T0]],[[T0]],0x10
-; MIPS32: xor [[T10]],[[T10]],[[T0]]
-; MIPS32: sltu [[T10]],zero,[[T10]]
-; MIPS32: sll [[T10]],[[T10]],0x10
-; MIPS32: sll [[T8]],[[T8]],0x10
-; MIPS32: srl [[T8]],[[T8]],0x10
-; MIPS32: or [[T10]],[[T10]],[[T8]]
-; MIPS32: move [[T0]],a1
-; MIPS32: andi [[T0]],[[T0]],0xffff
-; MIPS32: move [[T4]],[[T1]]
-; MIPS32: andi [[T4]],[[T4]],0xffff
-; MIPS32: sll [[T0]],[[T0]],0x10
-; MIPS32: sll [[T4]],[[T4]],0x10
-; MIPS32: xor [[T0]],[[T0]],[[T4]]
-; MIPS32: sltu [[T0]],zero,[[T0]]
-; MIPS32: andi [[T0]],[[T0]],0xffff
-; MIPS32: srl [[T5]],[[T5]],0x10
-; MIPS32: sll [[T5]],[[T5]],0x10
-; MIPS32: or [[T0]],[[T0]],[[T5]]
-; MIPS32: srl [[T11:.*]],a1,0x10
-; MIPS32: srl [[T1]],[[T1]],0x10
-; MIPS32: sll [[T11]],[[T11]],0x10
-; MIPS32: sll [[T1]],[[T1]],0x10
-; MIPS32: xor [[T11]],[[T11]],[[T1]]
-; MIPS32: sltu [[T11]],zero,[[T11]]
-; MIPS32: sll [[T11]],[[T11]],0x10
-; MIPS32: sll [[T0]],[[T0]],0x10
-; MIPS32: srl [[T0]],[[T0]],0x10
-; MIPS32: or [[T11]],[[T11]],[[T0]]
-; MIPS32: move [[T0]],a2
-; MIPS32: andi [[T0]],[[T0]],0xffff
-; MIPS32: move [[T1]],[[T2]]
-; MIPS32: andi [[T1]],[[T1]],0xffff
-; MIPS32: sll [[T0]],[[T0]],0x10
-; MIPS32: sll [[T1]],[[T1]],0x10
-; MIPS32: xor [[T0]],[[T0]],[[T1]]
-; MIPS32: sltu [[T0]],zero,[[T0]]
-; MIPS32: andi [[T0]],[[T0]],0xffff
-; MIPS32: srl [[T6]],[[T6]],0x10
-; MIPS32: sll [[T6]],[[T6]],0x10
-; MIPS32: or [[T0]],[[T0]],[[T6]]
-; MIPS32: srl [[T12:.*]],a2,0x10
-; MIPS32: srl [[T2]],[[T2]],0x10
-; MIPS32: sll [[T12]],[[T12]],0x10
-; MIPS32: sll [[T2]],[[T2]],0x10
-; MIPS32: xor [[T12]],[[T12]],[[T2]]
-; MIPS32: sltu [[T12]],zero,[[T12]]
-; MIPS32: sll [[T12]],[[T12]],0x10
-; MIPS32: sll [[T0]],[[T0]],0x10
-; MIPS32: srl [[T0]],[[T0]],0x10
-; MIPS32: or [[T12]],[[T12]],[[T0]]
-; MIPS32: move [[T0]],a3
-; MIPS32: andi [[T0]],[[T0]],0xffff
-; MIPS32: move [[T1]],[[T3]]
-; MIPS32: andi [[T1]],[[T1]],0xffff
-; MIPS32: sll [[T0]],[[T0]],0x10
-; MIPS32: sll [[T1]],[[T1]],0x10
-; MIPS32: xor [[T0]],[[T0]],[[T1]]
-; MIPS32: sltu [[T0]],zero,[[T0]]
-; MIPS32: andi [[T0]],[[T0]],0xffff
-; MIPS32: srl [[T7]],[[T7]],0x10
-; MIPS32: sll [[T7]],[[T7]],0x10
-; MIPS32: or [[T0]],[[T0]],[[T7]]
-; MIPS32: srl [[T13:.*]],a3,0x10
-; MIPS32: srl [[T3]],[[T3]],0x10
-; MIPS32: sll [[T13]],[[T13]],0x10
-; MIPS32: sll [[T3]],[[T3]],0x10
-; MIPS32: xor [[T13]],[[T13]],[[T3]]
-; MIPS32: sltu [[T13]],zero,[[T13]]
-; MIPS32: sll [[T13]],[[T13]],0x10
-; MIPS32: sll [[T0]],[[T0]],0x10
-; MIPS32: srl [[T0]],[[T0]],0x10
-; MIPS32: or [[T13]],[[T13]],[[T0]]
-; MIPS32: move v0,[[T10]]
-; MIPS32: move v1,[[T11]]
-; MIPS32: move a0,[[T12]]
-; MIPS32: move a1,[[T13]]
-}
-
-define internal <8 x i1> @test_icmp_v8i16_sgt(<8 x i16> %a, <8 x i16> %b) {
-entry:
- %res = icmp sgt <8 x i16> %a, %b
- ret <8 x i1> %res
-; CHECK-LABEL: test_icmp_v8i16_sgt
-; CHECK: pcmpgtw
-
-; MIPS32-LABEL: test_icmp_v8i16_sgt
-; MIPS32: lw [[T0:.*]],
-; MIPS32: lw [[T1:.*]],
-; MIPS32: lw [[T2:.*]],
-; MIPS32: lw [[T3:.*]],
-; MIPS32: move [[T4:.*]],zero
-; MIPS32: move [[T5:.*]],zero
-; MIPS32: move [[T6:.*]],zero
-; MIPS32: move [[T7:.*]],zero
-; MIPS32: move [[T8:.*]],a0
-; MIPS32: andi [[T8]],[[T8]],0xffff
-; MIPS32: move [[T9:.*]],[[T0]]
-; MIPS32: andi [[T9]],[[T9]],0xffff
-; MIPS32: sll [[T8]],[[T8]],0x10
-; MIPS32: sll [[T9]],[[T9]],0x10
-; MIPS32: slt [[T9]],[[T9]],[[T8]]
-; MIPS32: andi [[T9]],[[T9]],0xffff
-; MIPS32: srl [[T4]],[[T4]],0x10
-; MIPS32: sll [[T4]],[[T4]],0x10
-; MIPS32: or [[T9]],[[T9]],[[T4]]
-; MIPS32: srl [[T10:.*]],a0,0x10
-; MIPS32: srl [[T0]],[[T0]],0x10
-; MIPS32: sll [[T10]],[[T10]],0x10
-; MIPS32: sll [[T0]],[[T0]],0x10
-; MIPS32: slt [[T0]],[[T0]],[[T10]]
-; MIPS32: sll [[T0]],[[T0]],0x10
-; MIPS32: sll [[T9]],[[T9]],0x10
-; MIPS32: srl [[T9]],[[T9]],0x10
-; MIPS32: or v0,[[T0]],[[T9]]
-; MIPS32: move [[T10]],a1
-; MIPS32: andi [[T10]],[[T10]],0xffff
-; MIPS32: move [[T4]],[[T1]]
-; MIPS32: andi [[T4]],[[T4]],0xffff
-; MIPS32: sll [[T10]],[[T10]],0x10
-; MIPS32: sll [[T4]],[[T4]],0x10
-; MIPS32: slt [[T4]],[[T4]],[[T10]]
-; MIPS32: andi [[T4]],[[T4]],0xffff
-; MIPS32: srl [[T5]],[[T5]],0x10
-; MIPS32: sll [[T5]],[[T5]],0x10
-; MIPS32: or [[T4]],[[T4]],[[T5]]
-; MIPS32: srl [[T11:.*]],a1,0x10
-; MIPS32: srl [[T1]],[[T1]],0x10
-; MIPS32: sll [[T11]],[[T11]],0x10
-; MIPS32: sll [[T1]],[[T1]],0x10
-; MIPS32: slt [[T1]],[[T1]],[[T11]]
-; MIPS32: sll [[T1]],[[T1]],0x10
-; MIPS32: sll [[T4]],[[T4]],0x10
-; MIPS32: srl [[T4]],[[T4]],0x10
-; MIPS32: or v1,[[T1]],[[T4]]
-; MIPS32: move [[T10]],a2
-; MIPS32: andi [[T10]],[[T10]],0xffff
-; MIPS32: move [[T11]],[[T2]]
-; MIPS32: andi [[T11]],[[T11]],0xffff
-; MIPS32: sll [[T10]],[[T10]],0x10
-; MIPS32: sll [[T11]],[[T11]],0x10
-; MIPS32: slt [[T11]],[[T11]],[[T10]]
-; MIPS32: andi [[T11]],[[T11]],0xffff
-; MIPS32: srl [[T6]],[[T6]],0x10
-; MIPS32: sll [[T6]],[[T6]],0x10
-; MIPS32: or [[T11]],[[T11]],[[T6]]
-; MIPS32: srl [[T12:.*]],a2,0x10
-; MIPS32: srl [[T2]],[[T2]],0x10
-; MIPS32: sll [[T12]],[[T12]],0x10
-; MIPS32: sll [[T2]],[[T2]],0x10
-; MIPS32: slt [[T2]],[[T2]],[[T12]]
-; MIPS32: sll [[T2]],[[T2]],0x10
-; MIPS32: sll [[T11]],[[T11]],0x10
-; MIPS32: srl [[T11]],[[T11]],0x10
-; MIPS32: or [[T2]],[[T2]],[[T11]]
-; MIPS32: move [[T10]],a3
-; MIPS32: andi [[T10]],[[T10]],0xffff
-; MIPS32: move [[T11]],[[T3]]
-; MIPS32: andi [[T11]],[[T11]],0xffff
-; MIPS32: sll [[T10]],[[T10]],0x10
-; MIPS32: sll [[T11]],[[T11]],0x10
-; MIPS32: slt [[T11]],[[T11]],[[T10]]
-; MIPS32: andi [[T11]],[[T11]],0xffff
-; MIPS32: srl [[T7]],[[T7]],0x10
-; MIPS32: sll [[T7]],[[T7]],0x10
-; MIPS32: or [[T11]],[[T11]],[[T7]]
-; MIPS32: srl [[T13:.*]],a3,0x10
-; MIPS32: srl [[T3]],[[T3]],0x10
-; MIPS32: sll [[T13]],[[T13]],0x10
-; MIPS32: sll [[T3]],[[T3]],0x10
-; MIPS32: slt [[T3]],[[T3]],[[T13]]
-; MIPS32: sll [[T3]],[[T3]],0x10
-; MIPS32: sll [[T11]],[[T11]],0x10
-; MIPS32: srl [[T11]],[[T11]],0x10
-; MIPS32: or [[T3]],[[T3]],[[T11]]
-; MIPS32: move a0,[[T2]]
-; MIPS32: move a1,[[T3]]
-}
-
-define internal <8 x i1> @test_icmp_v8i16_sle(<8 x i16> %a, <8 x i16> %b) {
-entry:
- %res = icmp sle <8 x i16> %a, %b
- ret <8 x i1> %res
-; CHECK-LABEL: test_icmp_v8i16_sle
-; CHECK: pcmpgtw
-; CHECK: pxor
-
-; MIPS32-LABEL: test_icmp_v8i16_sle
-; MIPS32: lw [[T0:.*]],
-; MIPS32: lw [[T1:.*]],
-; MIPS32: lw [[T2:.*]],
-; MIPS32: lw [[T3:.*]],
-; MIPS32: move [[T4:.*]],zero
-; MIPS32: move [[T5:.*]],zero
-; MIPS32: move [[T6:.*]],zero
-; MIPS32: move [[T7:.*]],zero
-; MIPS32: move [[T8:.*]],a0
-; MIPS32: andi [[T8]],[[T8]],0xffff
-; MIPS32: move [[T9:.*]],[[T0]]
-; MIPS32: andi [[T9]],[[T9]],0xffff
-; MIPS32: sll [[T8]],[[T8]],0x10
-; MIPS32: sll [[T9]],[[T9]],0x10
-; MIPS32: slt [[T9]],[[T9]],[[T8]]
-; MIPS32: xori [[T9]],[[T9]],0x1
-; MIPS32: andi [[T9]],[[T9]],0xffff
-; MIPS32: srl [[T4]],[[T4]],0x10
-; MIPS32: sll [[T4]],[[T4]],0x10
-; MIPS32: or [[T9]],[[T9]],[[T4]]
-; MIPS32: srl [[T10:.*]],a0,0x10
-; MIPS32: srl [[T0]],[[T0]],0x10
-; MIPS32: sll [[T10]],[[T10]],0x10
-; MIPS32: sll [[T0]],[[T0]],0x10
-; MIPS32: slt [[T0]],[[T0]],[[T10]]
-; MIPS32: xori [[T0]],[[T0]],0x1
-; MIPS32: sll [[T0]],[[T0]],0x10
-; MIPS32: sll [[T9]],[[T9]],0x10
-; MIPS32: srl [[T9]],[[T9]],0x10
-; MIPS32: or v0,[[T0]],[[T9]]
-; MIPS32: move [[T10]],a1
-; MIPS32: andi [[T10]],[[T10]],0xffff
-; MIPS32: move [[T4]],[[T1]]
-; MIPS32: andi [[T4]],[[T4]],0xffff
-; MIPS32: sll [[T10]],[[T10]],0x10
-; MIPS32: sll [[T4]],[[T4]],0x10
-; MIPS32: slt [[T4]],[[T4]],[[T10]]
-; MIPS32: xori [[T4]],[[T4]],0x1
-; MIPS32: andi [[T4]],[[T4]],0xffff
-; MIPS32: srl [[T5]],[[T5]],0x10
-; MIPS32: sll [[T5]],[[T5]],0x10
-; MIPS32: or [[T4]],[[T4]],[[T5]]
-; MIPS32: srl [[T11:.*]],a1,0x10
-; MIPS32: srl [[T1]],[[T1]],0x10
-; MIPS32: sll [[T11]],[[T11]],0x10
-; MIPS32: sll [[T1]],[[T1]],0x10
-; MIPS32: slt [[T1]],[[T1]],[[T11]]
-; MIPS32: xori [[T1]],[[T1]],0x1
-; MIPS32: sll [[T1]],[[T1]],0x10
-; MIPS32: sll [[T4]],[[T4]],0x10
-; MIPS32: srl [[T4]],[[T4]],0x10
-; MIPS32: or v1,[[T1]],[[T4]]
-; MIPS32: move [[T10]],a2
-; MIPS32: andi [[T10]],[[T10]],0xffff
-; MIPS32: move [[T11]],[[T2]]
-; MIPS32: andi [[T11]],[[T11]],0xffff
-; MIPS32: sll [[T10]],[[T10]],0x10
-; MIPS32: sll [[T11]],[[T11]],0x10
-; MIPS32: slt [[T11]],[[T11]],[[T10]]
-; MIPS32: xori [[T11]],[[T11]],0x1
-; MIPS32: andi [[T11]],[[T11]],0xffff
-; MIPS32: srl [[T6]],[[T6]],0x10
-; MIPS32: sll [[T6]],[[T6]],0x10
-; MIPS32: or [[T11]],[[T11]],[[T6]]
-; MIPS32: srl [[T12:.*]],a2,0x10
-; MIPS32: srl [[T2]],[[T2]],0x10
-; MIPS32: sll [[T12]],[[T12]],0x10
-; MIPS32: sll [[T2]],[[T2]],0x10
-; MIPS32: slt [[T2]],[[T2]],[[T12]]
-; MIPS32: xori [[T2]],[[T2]],0x1
-; MIPS32: sll [[T2]],[[T2]],0x10
-; MIPS32: sll [[T11]],[[T11]],0x10
-; MIPS32: srl [[T11]],[[T11]],0x10
-; MIPS32: or [[T2]],[[T2]],[[T11]]
-; MIPS32: move [[T10]],a3
-; MIPS32: andi [[T10]],[[T10]],0xffff
-; MIPS32: move [[T11]],[[T3]]
-; MIPS32: andi [[T11]],[[T11]],0xffff
-; MIPS32: sll [[T10]],[[T10]],0x10
-; MIPS32: sll [[T11]],[[T11]],0x10
-; MIPS32: slt [[T11]],[[T11]],[[T10]]
-; MIPS32: xori [[T11]],[[T11]],0x1
-; MIPS32: andi [[T11]],[[T11]],0xffff
-; MIPS32: srl [[T7]],[[T7]],0x10
-; MIPS32: sll [[T7]],[[T7]],0x10
-; MIPS32: or [[T11]],[[T11]],[[T7]]
-; MIPS32: srl [[T13:.*]],a3,0x10
-; MIPS32: srl [[T3]],[[T3]],0x10
-; MIPS32: sll [[T13]],[[T13]],0x10
-; MIPS32: sll [[T3]],[[T3]],0x10
-; MIPS32: slt [[T3]],[[T3]],[[T13]]
-; MIPS32: xori [[T3]],[[T3]],0x1
-; MIPS32: sll [[T3]],[[T3]],0x10
-; MIPS32: sll [[T11]],[[T11]],0x10
-; MIPS32: srl [[T11]],[[T11]],0x10
-; MIPS32: or [[T3]],[[T3]],[[T11]]
-; MIPS32: move a0,[[T2]]
-; MIPS32: move a1,[[T3]]
-}
-
-define internal <8 x i1> @test_icmp_v8i16_slt(<8 x i16> %a, <8 x i16> %b) {
-entry:
- %res = icmp slt <8 x i16> %a, %b
- ret <8 x i1> %res
-; CHECK-LABEL: test_icmp_v8i16_slt
-; CHECK: pcmpgtw
-
-; MIPS32-LABEL: test_icmp_v8i16_slt
-; MIPS32: lw [[T0:.*]],
-; MIPS32: lw [[T1:.*]],
-; MIPS32: lw [[T2:.*]],
-; MIPS32: lw [[T3:.*]],
-; MIPS32: move [[T4:.*]],zero
-; MIPS32: move [[T5:.*]],zero
-; MIPS32: move [[T6:.*]],zero
-; MIPS32: move [[T7:.*]],zero
-; MIPS32: move [[T8:.*]],a0
-; MIPS32: andi [[T8]],[[T8]],0xffff
-; MIPS32: move [[T9:.*]],[[T0]]
-; MIPS32: andi [[T9]],[[T9]],0xffff
-; MIPS32: sll [[T8]],[[T8]],0x10
-; MIPS32: sll [[T9]],[[T9]],0x10
-; MIPS32: slt [[T8]],[[T8]],[[T9]]
-; MIPS32: andi [[T8]],[[T8]],0xffff
-; MIPS32: srl [[T4]],[[T4]],0x10
-; MIPS32: sll [[T4]],[[T4]],0x10
-; MIPS32: or [[T8]],[[T8]],[[T4]]
-; MIPS32: srl [[T10:.*]],a0,0x10
-; MIPS32: srl [[T0]],[[T0]],0x10
-; MIPS32: sll [[T10]],[[T10]],0x10
-; MIPS32: sll [[T0]],[[T0]],0x10
-; MIPS32: slt [[T10]],[[T10]],[[T0]]
-; MIPS32: sll [[T10]],[[T10]],0x10
-; MIPS32: sll [[T8]],[[T8]],0x10
-; MIPS32: srl [[T8]],[[T8]],0x10
-; MIPS32: or [[T10]],[[T10]],[[T8]]
-; MIPS32: move [[T0]],a1
-; MIPS32: andi [[T0]],[[T0]],0xffff
-; MIPS32: move [[T4]],[[T1]]
-; MIPS32: andi [[T4]],[[T4]],0xffff
-; MIPS32: sll [[T0]],[[T0]],0x10
-; MIPS32: sll [[T4]],[[T4]],0x10
-; MIPS32: slt [[T0]],[[T0]],[[T4]]
-; MIPS32: andi [[T0]],[[T0]],0xffff
-; MIPS32: srl [[T5]],[[T5]],0x10
-; MIPS32: sll [[T5]],[[T5]],0x10
-; MIPS32: or [[T0]],[[T0]],[[T5]]
-; MIPS32: srl [[T11:.*]],a1,0x10
-; MIPS32: srl [[T1]],[[T1]],0x10
-; MIPS32: sll [[T11]],[[T11]],0x10
-; MIPS32: sll [[T1]],[[T1]],0x10
-; MIPS32: slt [[T11]],[[T11]],[[T1]]
-; MIPS32: sll [[T11]],[[T11]],0x10
-; MIPS32: sll [[T0]],[[T0]],0x10
-; MIPS32: srl [[T0]],[[T0]],0x10
-; MIPS32: or [[T11]],[[T11]],[[T0]]
-; MIPS32: move [[T0]],a2
-; MIPS32: andi [[T0]],[[T0]],0xffff
-; MIPS32: move [[T1]],[[T2]]
-; MIPS32: andi [[T1]],[[T1]],0xffff
-; MIPS32: sll [[T0]],[[T0]],0x10
-; MIPS32: sll [[T1]],[[T1]],0x10
-; MIPS32: slt [[T0]],[[T0]],[[T1]]
-; MIPS32: andi [[T0]],[[T0]],0xffff
-; MIPS32: srl [[T6]],[[T6]],0x10
-; MIPS32: sll [[T6]],[[T6]],0x10
-; MIPS32: or [[T0]],[[T0]],[[T6]]
-; MIPS32: srl [[T12:.*]],a2,0x10
-; MIPS32: srl [[T2]],[[T2]],0x10
-; MIPS32: sll [[T12]],[[T12]],0x10
-; MIPS32: sll [[T2]],[[T2]],0x10
-; MIPS32: slt [[T12]],[[T12]],[[T2]]
-; MIPS32: sll [[T12]],[[T12]],0x10
-; MIPS32: sll [[T0]],[[T0]],0x10
-; MIPS32: srl [[T0]],[[T0]],0x10
-; MIPS32: or [[T12]],[[T12]],[[T0]]
-; MIPS32: move [[T0]],a3
-; MIPS32: andi [[T0]],[[T0]],0xffff
-; MIPS32: move [[T1]],[[T3]]
-; MIPS32: andi [[T1]],[[T1]],0xffff
-; MIPS32: sll [[T0]],[[T0]],0x10
-; MIPS32: sll [[T1]],[[T1]],0x10
-; MIPS32: slt [[T0]],[[T0]],[[T1]]
-; MIPS32: andi [[T0]],[[T0]],0xffff
-; MIPS32: srl [[T7]],[[T7]],0x10
-; MIPS32: sll [[T7]],[[T7]],0x10
-; MIPS32: or [[T0]],[[T0]],[[T7]]
-; MIPS32: srl [[T13:.*]],a3,0x10
-; MIPS32: srl [[T3]],[[T3]],0x10
-; MIPS32: sll [[T13]],[[T13]],0x10
-; MIPS32: sll [[T3]],[[T3]],0x10
-; MIPS32: slt [[T13]],[[T13]],[[T3]]
-; MIPS32: sll [[T13]],[[T13]],0x10
-; MIPS32: sll [[T0]],[[T0]],0x10
-; MIPS32: srl [[T0]],[[T0]],0x10
-; MIPS32: or [[T13]],[[T13]],[[T0]]
-; MIPS32: move v0,[[T10]]
-; MIPS32: move v1,[[T11]]
-; MIPS32: move a0,[[T12]]
-; MIPS32: move a1,[[T13]]
-}
-
-define internal <8 x i1> @test_icmp_v8i16_uge(<8 x i16> %a, <8 x i16> %b) {
-entry:
- %res = icmp uge <8 x i16> %a, %b
- ret <8 x i1> %res
-; CHECK-LABEL: test_icmp_v8i16_uge
-; CHECK: pxor
-; CHECK: pcmpgtw
-; CHECK: pxor
-
-; MIPS32-LABEL: test_icmp_v8i16_uge
-; MIPS32: lw [[T0:.*]],
-; MIPS32: lw [[T1:.*]],
-; MIPS32: lw [[T2:.*]],
-; MIPS32: lw [[T3:.*]],
-; MIPS32: move [[T4:.*]],zero
-; MIPS32: move [[T5:.*]],zero
-; MIPS32: move [[T6:.*]],zero
-; MIPS32: move [[T7:.*]],zero
-; MIPS32: move [[T8:.*]],a0
-; MIPS32: andi [[T8]],[[T8]],0xffff
-; MIPS32: move [[T9:.*]],[[T0]]
-; MIPS32: andi [[T9]],[[T9]],0xffff
-; MIPS32: sll [[T8]],[[T8]],0x10
-; MIPS32: sll [[T9]],[[T9]],0x10
-; MIPS32: sltu [[T8]],[[T8]],[[T9]]
-; MIPS32: xori [[T8]],[[T8]],0x1
-; MIPS32: andi [[T8]],[[T8]],0xffff
-; MIPS32: srl [[T4]],[[T4]],0x10
-; MIPS32: sll [[T4]],[[T4]],0x10
-; MIPS32: or [[T8]],[[T8]],[[T4]]
-; MIPS32: srl [[T10:.*]],a0,0x10
-; MIPS32: srl [[T0]],[[T0]],0x10
-; MIPS32: sll [[T10]],[[T10]],0x10
-; MIPS32: sll [[T0]],[[T0]],0x10
-; MIPS32: sltu [[T10]],[[T10]],[[T0]]
-; MIPS32: xori [[T10]],[[T10]],0x1
-; MIPS32: sll [[T10]],[[T10]],0x10
-; MIPS32: sll [[T8]],[[T8]],0x10
-; MIPS32: srl [[T8]],[[T8]],0x10
-; MIPS32: or [[T10]],[[T10]],[[T8]]
-; MIPS32: move [[T0]],a1
-; MIPS32: andi [[T0]],[[T0]],0xffff
-; MIPS32: move [[T4]],[[T1]]
-; MIPS32: andi [[T4]],[[T4]],0xffff
-; MIPS32: sll [[T0]],[[T0]],0x10
-; MIPS32: sll [[T4]],[[T4]],0x10
-; MIPS32: sltu [[T0]],[[T0]],[[T4]]
-; MIPS32: xori [[T0]],[[T0]],0x1
-; MIPS32: andi [[T0]],[[T0]],0xffff
-; MIPS32: srl [[T5]],[[T5]],0x10
-; MIPS32: sll [[T5]],[[T5]],0x10
-; MIPS32: or [[T0]],[[T0]],[[T5]]
-; MIPS32: srl [[T11:.*]],a1,0x10
-; MIPS32: srl [[T1]],[[T1]],0x10
-; MIPS32: sll [[T11]],[[T11]],0x10
-; MIPS32: sll [[T1]],[[T1]],0x10
-; MIPS32: sltu [[T11]],[[T11]],[[T1]]
-; MIPS32: xori [[T11]],[[T11]],0x1
-; MIPS32: sll [[T11]],[[T11]],0x10
-; MIPS32: sll [[T0]],[[T0]],0x10
-; MIPS32: srl [[T0]],[[T0]],0x10
-; MIPS32: or [[T11]],[[T11]],[[T0]]
-; MIPS32: move [[T0]],a2
-; MIPS32: andi [[T0]],[[T0]],0xffff
-; MIPS32: move [[T1]],[[T2]]
-; MIPS32: andi [[T1]],[[T1]],0xffff
-; MIPS32: sll [[T0]],[[T0]],0x10
-; MIPS32: sll [[T1]],[[T1]],0x10
-; MIPS32: sltu [[T0]],[[T0]],[[T1]]
-; MIPS32: xori [[T0]],[[T0]],0x1
-; MIPS32: andi [[T0]],[[T0]],0xffff
-; MIPS32: srl [[T6]],[[T6]],0x10
-; MIPS32: sll [[T6]],[[T6]],0x10
-; MIPS32: or [[T0]],[[T0]],[[T6]]
-; MIPS32: srl [[T12:.*]],a2,0x10
-; MIPS32: srl [[T2]],[[T2]],0x10
-; MIPS32: sll [[T12]],[[T12]],0x10
-; MIPS32: sll [[T2]],[[T2]],0x10
-; MIPS32: sltu [[T12]],[[T12]],[[T2]]
-; MIPS32: xori [[T12]],[[T12]],0x1
-; MIPS32: sll [[T12]],[[T12]],0x10
-; MIPS32: sll [[T0]],[[T0]],0x10
-; MIPS32: srl [[T0]],[[T0]],0x10
-; MIPS32: or [[T12]],[[T12]],[[T0]]
-; MIPS32: move [[T0]],a3
-; MIPS32: andi [[T0]],[[T0]],0xffff
-; MIPS32: move [[T1]],[[T3]]
-; MIPS32: andi [[T1]],[[T1]],0xffff
-; MIPS32: sll [[T0]],[[T0]],0x10
-; MIPS32: sll [[T1]],[[T1]],0x10
-; MIPS32: sltu [[T0]],[[T0]],[[T1]]
-; MIPS32: xori [[T0]],[[T0]],0x1
-; MIPS32: andi [[T0]],[[T0]],0xffff
-; MIPS32: srl [[T7]],[[T7]],0x10
-; MIPS32: sll [[T7]],[[T7]],0x10
-; MIPS32: or [[T0]],[[T0]],[[T7]]
-; MIPS32: srl [[T13:.*]],a3,0x10
-; MIPS32: srl [[T3]],[[T3]],0x10
-; MIPS32: sll [[T13]],[[T13]],0x10
-; MIPS32: sll [[T3]],[[T3]],0x10
-; MIPS32: sltu [[T13]],[[T13]],[[T3]]
-; MIPS32: xori [[T13]],[[T13]],0x1
-; MIPS32: sll [[T13]],[[T13]],0x10
-; MIPS32: sll [[T0]],[[T0]],0x10
-; MIPS32: srl [[T0]],[[T0]],0x10
-; MIPS32: or [[T13]],[[T13]],[[T0]]
-; MIPS32: move v0,[[T10]]
-; MIPS32: move v1,[[T11]]
-; MIPS32: move a0,[[T12]]
-; MIPS32: move a1,[[T13]]
-}
-
-define internal <8 x i1> @test_icmp_v8i16_ugt(<8 x i16> %a, <8 x i16> %b) {
-entry:
- %res = icmp ugt <8 x i16> %a, %b
- ret <8 x i1> %res
-; CHECK-LABEL: test_icmp_v8i16_ugt
-; CHECK: pxor
-; CHECK: pcmpgtw
-
-; MIPS32-LABEL: test_icmp_v8i16_ugt
-; MIPS32: lw [[T0:.*]],
-; MIPS32: lw [[T1:.*]],
-; MIPS32: lw [[T2:.*]],
-; MIPS32: lw [[T3:.*]],
-; MIPS32: move [[T4:.*]],zero
-; MIPS32: move [[T5:.*]],zero
-; MIPS32: move [[T6:.*]],zero
-; MIPS32: move [[T7:.*]],zero
-; MIPS32: move [[T8:.*]],a0
-; MIPS32: andi [[T8]],[[T8]],0xffff
-; MIPS32: move [[T9:.*]],[[T0]]
-; MIPS32: andi [[T9]],[[T9]],0xffff
-; MIPS32: sll [[T8]],[[T8]],0x10
-; MIPS32: sll [[T9]],[[T9]],0x10
-; MIPS32: sltu [[T9]],[[T9]],[[T8]]
-; MIPS32: andi [[T9]],[[T9]],0xffff
-; MIPS32: srl [[T4]],[[T4]],0x10
-; MIPS32: sll [[T4]],[[T4]],0x10
-; MIPS32: or [[T9]],[[T9]],[[T4]]
-; MIPS32: srl [[T10:.*]],a0,0x10
-; MIPS32: srl [[T0]],[[T0]],0x10
-; MIPS32: sll [[T10]],[[T10]],0x10
-; MIPS32: sll [[T0]],[[T0]],0x10
-; MIPS32: sltu [[T0]],[[T0]],[[T10]]
-; MIPS32: sll [[T0]],[[T0]],0x10
-; MIPS32: sll [[T9]],[[T9]],0x10
-; MIPS32: srl [[T9]],[[T9]],0x10
-; MIPS32: or v0,[[T0]],[[T9]]
-; MIPS32: move [[T10]],a1
-; MIPS32: andi [[T10]],[[T10]],0xffff
-; MIPS32: move [[T4]],[[T1]]
-; MIPS32: andi [[T4]],[[T4]],0xffff
-; MIPS32: sll [[T10]],[[T10]],0x10
-; MIPS32: sll [[T4]],[[T4]],0x10
-; MIPS32: sltu [[T4]],[[T4]],[[T10]]
-; MIPS32: andi [[T4]],[[T4]],0xffff
-; MIPS32: srl [[T5]],[[T5]],0x10
-; MIPS32: sll [[T5]],[[T5]],0x10
-; MIPS32: or [[T4]],[[T4]],[[T5]]
-; MIPS32: srl [[T11:.*]],a1,0x10
-; MIPS32: srl [[T1]],[[T1]],0x10
-; MIPS32: sll [[T11]],[[T11]],0x10
-; MIPS32: sll [[T1]],[[T1]],0x10
-; MIPS32: sltu [[T1]],[[T1]],[[T11]]
-; MIPS32: sll [[T1]],[[T1]],0x10
-; MIPS32: sll [[T4]],[[T4]],0x10
-; MIPS32: srl [[T4]],[[T4]],0x10
-; MIPS32: or v1,[[T1]],[[T4]]
-; MIPS32: move [[T10]],a2
-; MIPS32: andi [[T10]],[[T10]],0xffff
-; MIPS32: move [[T11]],[[T2]]
-; MIPS32: andi [[T11]],[[T11]],0xffff
-; MIPS32: sll [[T10]],[[T10]],0x10
-; MIPS32: sll [[T11]],[[T11]],0x10
-; MIPS32: sltu [[T11]],[[T11]],[[T10]]
-; MIPS32: andi [[T11]],[[T11]],0xffff
-; MIPS32: srl [[T6]],[[T6]],0x10
-; MIPS32: sll [[T6]],[[T6]],0x10
-; MIPS32: or [[T11]],[[T11]],[[T6]]
-; MIPS32: srl [[T12:.*]],a2,0x10
-; MIPS32: srl [[T2]],[[T2]],0x10
-; MIPS32: sll [[T12]],[[T12]],0x10
-; MIPS32: sll [[T2]],[[T2]],0x10
-; MIPS32: sltu [[T2]],[[T2]],[[T12]]
-; MIPS32: sll [[T2]],[[T2]],0x10
-; MIPS32: sll [[T11]],[[T11]],0x10
-; MIPS32: srl [[T11]],[[T11]],0x10
-; MIPS32: or [[T2]],[[T2]],[[T11]]
-; MIPS32: move [[T10]],a3
-; MIPS32: andi [[T10]],[[T10]],0xffff
-; MIPS32: move [[T11]],[[T3]]
-; MIPS32: andi [[T11]],[[T11]],0xffff
-; MIPS32: sll [[T10]],[[T10]],0x10
-; MIPS32: sll [[T11]],[[T11]],0x10
-; MIPS32: sltu [[T11]],[[T11]],[[T10]]
-; MIPS32: andi [[T11]],[[T11]],0xffff
-; MIPS32: srl [[T7]],[[T7]],0x10
-; MIPS32: sll [[T7]],[[T7]],0x10
-; MIPS32: or [[T11]],[[T11]],[[T7]]
-; MIPS32: srl [[T13:.*]],a3,0x10
-; MIPS32: srl [[T3]],[[T3]],0x10
-; MIPS32: sll [[T13]],[[T13]],0x10
-; MIPS32: sll [[T3]],[[T3]],0x10
-; MIPS32: sltu [[T3]],[[T3]],[[T13]]
-; MIPS32: sll [[T3]],[[T3]],0x10
-; MIPS32: sll [[T11]],[[T11]],0x10
-; MIPS32: srl [[T11]],[[T11]],0x10
-; MIPS32: or [[T3]],[[T3]],[[T11]]
-; MIPS32: move a0,[[T2]]
-; MIPS32: move a1,[[T3]]
-}
-
-define internal <8 x i1> @test_icmp_v8i16_ule(<8 x i16> %a, <8 x i16> %b) {
-entry:
- %res = icmp ule <8 x i16> %a, %b
- ret <8 x i1> %res
-; CHECK-LABEL: test_icmp_v8i16_ule
-; CHECK: pxor
-; CHECK: pcmpgtw
-; CHECK: pxor
-
-; MIPS32-LABEL: test_icmp_v8i16_ule
-; MIPS32: lw [[T0:.*]],
-; MIPS32: lw [[T1:.*]],
-; MIPS32: lw [[T2:.*]],
-; MIPS32: lw [[T3:.*]],
-; MIPS32: move [[T4:.*]],zero
-; MIPS32: move [[T5:.*]],zero
-; MIPS32: move [[T6:.*]],zero
-; MIPS32: move [[T7:.*]],zero
-; MIPS32: move [[T8:.*]],a0
-; MIPS32: andi [[T8]],[[T8]],0xffff
-; MIPS32: move [[T9:.*]],[[T0]]
-; MIPS32: andi [[T9]],[[T9]],0xffff
-; MIPS32: sll [[T8]],[[T8]],0x10
-; MIPS32: sll [[T9]],[[T9]],0x10
-; MIPS32: sltu [[T9]],[[T9]],[[T8]]
-; MIPS32: xori [[T9]],[[T9]],0x1
-; MIPS32: andi [[T9]],[[T9]],0xffff
-; MIPS32: srl [[T4]],[[T4]],0x10
-; MIPS32: sll [[T4]],[[T4]],0x10
-; MIPS32: or [[T9]],[[T9]],[[T4]]
-; MIPS32: srl [[T10:.*]],a0,0x10
-; MIPS32: srl [[T0]],[[T0]],0x10
-; MIPS32: sll [[T10]],[[T10]],0x10
-; MIPS32: sll [[T0]],[[T0]],0x10
-; MIPS32: sltu [[T0]],[[T0]],[[T10]]
-; MIPS32: xori [[T0]],[[T0]],0x1
-; MIPS32: sll [[T0]],[[T0]],0x10
-; MIPS32: sll [[T9]],[[T9]],0x10
-; MIPS32: srl [[T9]],[[T9]],0x10
-; MIPS32: or v0,[[T0]],[[T9]]
-; MIPS32: move [[T10]],a1
-; MIPS32: andi [[T10]],[[T10]],0xffff
-; MIPS32: move [[T4]],[[T1]]
-; MIPS32: andi [[T4]],[[T4]],0xffff
-; MIPS32: sll [[T10]],[[T10]],0x10
-; MIPS32: sll [[T4]],[[T4]],0x10
-; MIPS32: sltu [[T4]],[[T4]],[[T10]]
-; MIPS32: xori [[T4]],[[T4]],0x1
-; MIPS32: andi [[T4]],[[T4]],0xffff
-; MIPS32: srl [[T5]],[[T5]],0x10
-; MIPS32: sll [[T5]],[[T5]],0x10
-; MIPS32: or [[T4]],[[T4]],[[T5]]
-; MIPS32: srl [[T11:.*]],a1,0x10
-; MIPS32: srl [[T1]],[[T1]],0x10
-; MIPS32: sll [[T11]],[[T11]],0x10
-; MIPS32: sll [[T1]],[[T1]],0x10
-; MIPS32: sltu [[T1]],[[T1]],[[T11]]
-; MIPS32: xori [[T1]],[[T1]],0x1
-; MIPS32: sll [[T1]],[[T1]],0x10
-; MIPS32: sll [[T4]],[[T4]],0x10
-; MIPS32: srl [[T4]],[[T4]],0x10
-; MIPS32: or v1,[[T1]],[[T4]]
-; MIPS32: move [[T10]],a2
-; MIPS32: andi [[T10]],[[T10]],0xffff
-; MIPS32: move [[T11]],[[T2]]
-; MIPS32: andi [[T11]],[[T11]],0xffff
-; MIPS32: sll [[T10]],[[T10]],0x10
-; MIPS32: sll [[T11]],[[T11]],0x10
-; MIPS32: sltu [[T11]],[[T11]],[[T10]]
-; MIPS32: xori [[T11]],[[T11]],0x1
-; MIPS32: andi [[T11]],[[T11]],0xffff
-; MIPS32: srl [[T6]],[[T6]],0x10
-; MIPS32: sll [[T6]],[[T6]],0x10
-; MIPS32: or [[T11]],[[T11]],[[T6]]
-; MIPS32: srl [[T12:.*]],a2,0x10
-; MIPS32: srl [[T2]],[[T2]],0x10
-; MIPS32: sll [[T12]],[[T12]],0x10
-; MIPS32: sll [[T2]],[[T2]],0x10
-; MIPS32: sltu [[T2]],[[T2]],[[T12]]
-; MIPS32: xori [[T2]],[[T2]],0x1
-; MIPS32: sll [[T2]],[[T2]],0x10
-; MIPS32: sll [[T11]],[[T11]],0x10
-; MIPS32: srl [[T11]],[[T11]],0x10
-; MIPS32: or [[T2]],[[T2]],[[T11]]
-; MIPS32: move [[T10]],a3
-; MIPS32: andi [[T10]],[[T10]],0xffff
-; MIPS32: move [[T11]],[[T3]]
-; MIPS32: andi [[T11]],[[T11]],0xffff
-; MIPS32: sll [[T10]],[[T10]],0x10
-; MIPS32: sll [[T11]],[[T11]],0x10
-; MIPS32: sltu [[T11]],[[T11]],[[T10]]
-; MIPS32: xori [[T11]],[[T11]],0x1
-; MIPS32: andi [[T11]],[[T11]],0xffff
-; MIPS32: srl [[T7]],[[T7]],0x10
-; MIPS32: sll [[T7]],[[T7]],0x10
-; MIPS32: or [[T11]],[[T11]],[[T7]]
-; MIPS32: srl [[T13:.*]],a3,0x10
-; MIPS32: srl [[T3]],[[T3]],0x10
-; MIPS32: sll [[T13]],[[T13]],0x10
-; MIPS32: sll [[T3]],[[T3]],0x10
-; MIPS32: sltu [[T3]],[[T3]],[[T13]]
-; MIPS32: xori [[T3]],[[T3]],0x1
-; MIPS32: sll [[T3]],[[T3]],0x10
-; MIPS32: sll [[T11]],[[T11]],0x10
-; MIPS32: srl [[T11]],[[T11]],0x10
-; MIPS32: or [[T3]],[[T3]],[[T11]]
-; MIPS32: move a0,[[T2]]
-; MIPS32: move a1,[[T3]]
-}
-
-define internal <8 x i1> @test_icmp_v8i16_ult(<8 x i16> %a, <8 x i16> %b) {
-entry:
- %res = icmp ult <8 x i16> %a, %b
- ret <8 x i1> %res
-; CHECK-LABEL: test_icmp_v8i16_ult
-; CHECK: pxor
-; CHECK: pcmpgtw
-
-; MIPS32-LABEL: test_icmp_v8i16_ult
-; MIPS32: lw [[T0:.*]],
-; MIPS32: lw [[T1:.*]],
-; MIPS32: lw [[T2:.*]],
-; MIPS32: lw [[T3:.*]],
-; MIPS32: move [[T4:.*]],zero
-; MIPS32: move [[T5:.*]],zero
-; MIPS32: move [[T6:.*]],zero
-; MIPS32: move [[T7:.*]],zero
-; MIPS32: move [[T8:.*]],a0
-; MIPS32: andi [[T8]],[[T8]],0xffff
-; MIPS32: move [[T9:.*]],[[T0]]
-; MIPS32: andi [[T9]],[[T9]],0xffff
-; MIPS32: sll [[T8]],[[T8]],0x10
-; MIPS32: sll [[T9]],[[T9]],0x10
-; MIPS32: sltu [[T8]],[[T8]],[[T9]]
-; MIPS32: andi [[T8]],[[T8]],0xffff
-; MIPS32: srl [[T4]],[[T4]],0x10
-; MIPS32: sll [[T4]],[[T4]],0x10
-; MIPS32: or [[T8]],[[T8]],[[T4]]
-; MIPS32: srl [[T10:.*]],a0,0x10
-; MIPS32: srl [[T0]],[[T0]],0x10
-; MIPS32: sll [[T10]],[[T10]],0x10
-; MIPS32: sll [[T0]],[[T0]],0x10
-; MIPS32: sltu [[T10]],[[T10]],[[T0]]
-; MIPS32: sll [[T10]],[[T10]],0x10
-; MIPS32: sll [[T8]],[[T8]],0x10
-; MIPS32: srl [[T8]],[[T8]],0x10
-; MIPS32: or [[T10]],[[T10]],[[T8]]
-; MIPS32: move [[T0]],a1
-; MIPS32: andi [[T0]],[[T0]],0xffff
-; MIPS32: move [[T4]],[[T1]]
-; MIPS32: andi [[T4]],[[T4]],0xffff
-; MIPS32: sll [[T0]],[[T0]],0x10
-; MIPS32: sll [[T4]],[[T4]],0x10
-; MIPS32: sltu [[T0]],[[T0]],[[T4]]
-; MIPS32: andi [[T0]],[[T0]],0xffff
-; MIPS32: srl [[T5]],[[T5]],0x10
-; MIPS32: sll [[T5]],[[T5]],0x10
-; MIPS32: or [[T0]],[[T0]],[[T5]]
-; MIPS32: srl [[T11:.*]],a1,0x10
-; MIPS32: srl [[T1]],[[T1]],0x10
-; MIPS32: sll [[T11]],[[T11]],0x10
-; MIPS32: sll [[T1]],[[T1]],0x10
-; MIPS32: sltu [[T11]],[[T11]],[[T1]]
-; MIPS32: sll [[T11]],[[T11]],0x10
-; MIPS32: sll [[T0]],[[T0]],0x10
-; MIPS32: srl [[T0]],[[T0]],0x10
-; MIPS32: or [[T11]],[[T11]],[[T0]]
-; MIPS32: move [[T0]],a2
-; MIPS32: andi [[T0]],[[T0]],0xffff
-; MIPS32: move [[T1]],[[T2]]
-; MIPS32: andi [[T1]],[[T1]],0xffff
-; MIPS32: sll [[T0]],[[T0]],0x10
-; MIPS32: sll [[T1]],[[T1]],0x10
-; MIPS32: sltu [[T0]],[[T0]],[[T1]]
-; MIPS32: andi [[T0]],[[T0]],0xffff
-; MIPS32: srl [[T6]],[[T6]],0x10
-; MIPS32: sll [[T6]],[[T6]],0x10
-; MIPS32: or [[T0]],[[T0]],[[T6]]
-; MIPS32: srl [[T12:.*]],a2,0x10
-; MIPS32: srl [[T2]],[[T2]],0x10
-; MIPS32: sll [[T12]],[[T12]],0x10
-; MIPS32: sll [[T2]],[[T2]],0x10
-; MIPS32: sltu [[T12]],[[T12]],[[T2]]
-; MIPS32: sll [[T12]],[[T12]],0x10
-; MIPS32: sll [[T0]],[[T0]],0x10
-; MIPS32: srl [[T0]],[[T0]],0x10
-; MIPS32: or [[T12]],[[T12]],[[T0]]
-; MIPS32: move [[T0]],a3
-; MIPS32: andi [[T0]],[[T0]],0xffff
-; MIPS32: move [[T1]],[[T3]]
-; MIPS32: andi [[T1]],[[T1]],0xffff
-; MIPS32: sll [[T0]],[[T0]],0x10
-; MIPS32: sll [[T1]],[[T1]],0x10
-; MIPS32: sltu [[T0]],[[T0]],[[T1]]
-; MIPS32: andi [[T0]],[[T0]],0xffff
-; MIPS32: srl [[T7]],[[T7]],0x10
-; MIPS32: sll [[T7]],[[T7]],0x10
-; MIPS32: or [[T0]],[[T0]],[[T7]]
-; MIPS32: srl [[T13:.*]],a3,0x10
-; MIPS32: srl [[T3]],[[T3]],0x10
-; MIPS32: sll [[T13]],[[T13]],0x10
-; MIPS32: sll [[T3]],[[T3]],0x10
-; MIPS32: sltu [[T13]],[[T13]],[[T3]]
-; MIPS32: sll [[T13]],[[T13]],0x10
-; MIPS32: sll [[T0]],[[T0]],0x10
-; MIPS32: srl [[T0]],[[T0]],0x10
-; MIPS32: or [[T13]],[[T13]],[[T0]]
-; MIPS32: move v0,[[T10]]
-; MIPS32: move v1,[[T11]]
-; MIPS32: move a0,[[T12]]
-; MIPS32: move a1,[[T13]]
-}
-
-define internal <8 x i1> @test_icmp_v8i1_eq(<8 x i1> %a, <8 x i1> %b) {
-entry:
- %res = icmp eq <8 x i1> %a, %b
- ret <8 x i1> %res
-; CHECK-LABEL: test_icmp_v8i1_eq
-; CHECK: pcmpeqw
-
-; MIPS32-LABEL: test_icmp_v8i1_eq
-; MIPS32: lw [[T0:.*]],
-; MIPS32: lw [[T1:.*]],
-; MIPS32: lw [[T2:.*]],
-; MIPS32: lw [[T3:.*]],
-; MIPS32: move [[T4:.*]],zero
-; MIPS32: move [[T5:.*]],zero
-; MIPS32: move [[T6:.*]],zero
-; MIPS32: move [[T7:.*]],zero
-; MIPS32: move [[T8:.*]],a0
-; MIPS32: andi [[T8]],[[T8]],0xffff
-; MIPS32: andi [[T8]],[[T8]],0x1
-; MIPS32: move [[T9:.*]],[[T0]]
-; MIPS32: andi [[T9]],[[T9]],0xffff
-; MIPS32: andi [[T9]],[[T9]],0x1
-; MIPS32: sll [[T8]],[[T8]],0x1f
-; MIPS32: sll [[T9]],[[T9]],0x1f
-; MIPS32: xor [[T8]],[[T8]],[[T9]]
-; MIPS32: sltiu [[T8]],[[T8]],1
-; MIPS32: andi [[T8]],[[T8]],0xffff
-; MIPS32: srl [[T4]],[[T4]],0x10
-; MIPS32: sll [[T4]],[[T4]],0x10
-; MIPS32: or [[T8]],[[T8]],[[T4]]
-; MIPS32: srl [[T10:.*]],a0,0x10
-; MIPS32: andi [[T10]],[[T10]],0x1
-; MIPS32: srl [[T0]],[[T0]],0x10
-; MIPS32: andi [[T0]],[[T0]],0x1
-; MIPS32: sll [[T10]],[[T10]],0x1f
-; MIPS32: sll [[T0]],[[T0]],0x1f
-; MIPS32: xor [[T10]],[[T10]],[[T0]]
-; MIPS32: sltiu [[T10]],[[T10]],1
-; MIPS32: sll [[T10]],[[T10]],0x10
-; MIPS32: sll [[T8]],[[T8]],0x10
-; MIPS32: srl [[T8]],[[T8]],0x10
-; MIPS32: or [[T10]],[[T10]],[[T8]]
-; MIPS32: move [[T0]],a1
-; MIPS32: andi [[T0]],[[T0]],0xffff
-; MIPS32: andi [[T0]],[[T0]],0x1
-; MIPS32: move [[T4]],[[T1]]
-; MIPS32: andi [[T4]],[[T4]],0xffff
-; MIPS32: andi [[T4]],[[T4]],0x1
-; MIPS32: sll [[T0]],[[T0]],0x1f
-; MIPS32: sll [[T4]],[[T4]],0x1f
-; MIPS32: xor [[T0]],[[T0]],[[T4]]
-; MIPS32: sltiu [[T0]],[[T0]],1
-; MIPS32: andi [[T0]],[[T0]],0xffff
-; MIPS32: srl [[T5]],[[T5]],0x10
-; MIPS32: sll [[T5]],[[T5]],0x10
-; MIPS32: or [[T0]],[[T0]],[[T5]]
-; MIPS32: srl [[T11:.*]],a1,0x10
-; MIPS32: andi [[T11]],[[T11]],0x1
-; MIPS32: srl [[T1]],[[T1]],0x10
-; MIPS32: andi [[T1]],[[T1]],0x1
-; MIPS32: sll [[T11]],[[T11]],0x1f
-; MIPS32: sll [[T1]],[[T1]],0x1f
-; MIPS32: xor [[T11]],[[T11]],[[T1]]
-; MIPS32: sltiu [[T11]],[[T11]],1
-; MIPS32: sll [[T11]],[[T11]],0x10
-; MIPS32: sll [[T0]],[[T0]],0x10
-; MIPS32: srl [[T0]],[[T0]],0x10
-; MIPS32: or [[T11]],[[T11]],[[T0]]
-; MIPS32: move [[T0]],a2
-; MIPS32: andi [[T0]],[[T0]],0xffff
-; MIPS32: andi [[T0]],[[T0]],0x1
-; MIPS32: move [[T1]],[[T2]]
-; MIPS32: andi [[T1]],[[T1]],0xffff
-; MIPS32: andi [[T1]],[[T1]],0x1
-; MIPS32: sll [[T0]],[[T0]],0x1f
-; MIPS32: sll [[T1]],[[T1]],0x1f
-; MIPS32: xor [[T0]],[[T0]],[[T1]]
-; MIPS32: sltiu [[T0]],[[T0]],1
-; MIPS32: andi [[T0]],[[T0]],0xffff
-; MIPS32: srl [[T6]],[[T6]],0x10
-; MIPS32: sll [[T6]],[[T6]],0x10
-; MIPS32: or [[T0]],[[T0]],[[T6]]
-; MIPS32: srl [[T12:.*]],a2,0x10
-; MIPS32: andi [[T12]],[[T12]],0x1
-; MIPS32: srl [[T2]],[[T2]],0x10
-; MIPS32: andi [[T2]],[[T2]],0x1
-; MIPS32: sll [[T12]],[[T12]],0x1f
-; MIPS32: sll [[T2]],[[T2]],0x1f
-; MIPS32: xor [[T12]],[[T12]],[[T2]]
-; MIPS32: sltiu [[T12]],[[T12]],1
-; MIPS32: sll [[T12]],[[T12]],0x10
-; MIPS32: sll [[T0]],[[T0]],0x10
-; MIPS32: srl [[T0]],[[T0]],0x10
-; MIPS32: or [[T12]],[[T12]],[[T0]]
-; MIPS32: move [[T0]],a3
-; MIPS32: andi [[T0]],[[T0]],0xffff
-; MIPS32: andi [[T0]],[[T0]],0x1
-; MIPS32: move [[T1]],[[T3]]
-; MIPS32: andi [[T1]],[[T1]],0xffff
-; MIPS32: andi [[T1]],[[T1]],0x1
-; MIPS32: sll [[T0]],[[T0]],0x1f
-; MIPS32: sll [[T1]],[[T1]],0x1f
-; MIPS32: xor [[T0]],[[T0]],[[T1]]
-; MIPS32: sltiu [[T0]],[[T0]],1
-; MIPS32: andi [[T0]],[[T0]],0xffff
-; MIPS32: srl [[T7]],[[T7]],0x10
-; MIPS32: sll [[T7]],[[T7]],0x10
-; MIPS32: or [[T0]],[[T0]],[[T7]]
-; MIPS32: srl [[T13:.*]],a3,0x10
-; MIPS32: andi [[T13]],[[T13]],0x1
-; MIPS32: srl [[T3]],[[T3]],0x10
-; MIPS32: andi [[T3]],[[T3]],0x1
-; MIPS32: sll [[T13]],[[T13]],0x1f
-; MIPS32: sll [[T3]],[[T3]],0x1f
-; MIPS32: xor [[T13]],[[T13]],[[T3]]
-; MIPS32: sltiu [[T13]],[[T13]],1
-; MIPS32: sll [[T13]],[[T13]],0x10
-; MIPS32: sll [[T0]],[[T0]],0x10
-; MIPS32: srl [[T0]],[[T0]],0x10
-; MIPS32: or [[T13]],[[T13]],[[T0]]
-; MIPS32: move v0,[[T10]]
-; MIPS32: move v1,[[T11]]
-; MIPS32: move a0,[[T12]]
-; MIPS32: move a1,[[T13]]
-}
-
-define internal <8 x i1> @test_icmp_v8i1_ne(<8 x i1> %a, <8 x i1> %b) {
-entry:
- %res = icmp ne <8 x i1> %a, %b
- ret <8 x i1> %res
-; CHECK-LABEL: test_icmp_v8i1_ne
-; CHECK: pcmpeqw
-; CHECK: pxor
-
-; MIPS32-LABEL: test_icmp_v8i1_ne
-; MIPS32: lw [[T0:.*]],
-; MIPS32: lw [[T1:.*]],
-; MIPS32: lw [[T2:.*]],
-; MIPS32: lw [[T3:.*]],
-; MIPS32: move [[T4:.*]],zero
-; MIPS32: move [[T5:.*]],zero
-; MIPS32: move [[T6:.*]],zero
-; MIPS32: move [[T7:.*]],zero
-; MIPS32: move [[T8:.*]],a0
-; MIPS32: andi [[T8]],[[T8]],0xffff
-; MIPS32: andi [[T8]],[[T8]],0x1
-; MIPS32: move [[T9:.*]],[[T0]]
-; MIPS32: andi [[T9]],[[T9]],0xffff
-; MIPS32: andi [[T9]],[[T9]],0x1
-; MIPS32: sll [[T8]],[[T8]],0x1f
-; MIPS32: sll [[T9]],[[T9]],0x1f
-; MIPS32: xor [[T8]],[[T8]],[[T9]]
-; MIPS32: sltu [[T8]],zero,[[T8]]
-; MIPS32: andi [[T8]],[[T8]],0xffff
-; MIPS32: srl [[T4]],[[T4]],0x10
-; MIPS32: sll [[T4]],[[T4]],0x10
-; MIPS32: or [[T8]],[[T8]],[[T4]]
-; MIPS32: srl [[T10:.*]],a0,0x10
-; MIPS32: andi [[T10]],[[T10]],0x1
-; MIPS32: srl [[T0]],[[T0]],0x10
-; MIPS32: andi [[T0]],[[T0]],0x1
-; MIPS32: sll [[T10]],[[T10]],0x1f
-; MIPS32: sll [[T0]],[[T0]],0x1f
-; MIPS32: xor [[T10]],[[T10]],[[T0]]
-; MIPS32: sltu [[T10]],zero,[[T10]]
-; MIPS32: sll [[T10]],[[T10]],0x10
-; MIPS32: sll [[T8]],[[T8]],0x10
-; MIPS32: srl [[T8]],[[T8]],0x10
-; MIPS32: or [[T10]],[[T10]],[[T8]]
-; MIPS32: move [[T0]],a1
-; MIPS32: andi [[T0]],[[T0]],0xffff
-; MIPS32: andi [[T0]],[[T0]],0x1
-; MIPS32: move [[T4]],[[T1]]
-; MIPS32: andi [[T4]],[[T4]],0xffff
-; MIPS32: andi [[T4]],[[T4]],0x1
-; MIPS32: sll [[T0]],[[T0]],0x1f
-; MIPS32: sll [[T4]],[[T4]],0x1f
-; MIPS32: xor [[T0]],[[T0]],[[T4]]
-; MIPS32: sltu [[T0]],zero,[[T0]]
-; MIPS32: andi [[T0]],[[T0]],0xffff
-; MIPS32: srl [[T5]],[[T5]],0x10
-; MIPS32: sll [[T5]],[[T5]],0x10
-; MIPS32: or [[T0]],[[T0]],[[T5]]
-; MIPS32: srl [[T11:.*]],a1,0x10
-; MIPS32: andi [[T11]],[[T11]],0x1
-; MIPS32: srl [[T1]],[[T1]],0x10
-; MIPS32: andi [[T1]],[[T1]],0x1
-; MIPS32: sll [[T11]],[[T11]],0x1f
-; MIPS32: sll [[T1]],[[T1]],0x1f
-; MIPS32: xor [[T11]],[[T11]],[[T1]]
-; MIPS32: sltu [[T11]],zero,[[T11]]
-; MIPS32: sll [[T11]],[[T11]],0x10
-; MIPS32: sll [[T0]],[[T0]],0x10
-; MIPS32: srl [[T0]],[[T0]],0x10
-; MIPS32: or [[T11]],[[T11]],[[T0]]
-; MIPS32: move [[T0]],a2
-; MIPS32: andi [[T0]],[[T0]],0xffff
-; MIPS32: andi [[T0]],[[T0]],0x1
-; MIPS32: move [[T1]],[[T2]]
-; MIPS32: andi [[T1]],[[T1]],0xffff
-; MIPS32: andi [[T1]],[[T1]],0x1
-; MIPS32: sll [[T0]],[[T0]],0x1f
-; MIPS32: sll [[T1]],[[T1]],0x1f
-; MIPS32: xor [[T0]],[[T0]],[[T1]]
-; MIPS32: sltu [[T0]],zero,[[T0]]
-; MIPS32: andi [[T0]],[[T0]],0xffff
-; MIPS32: srl [[T6]],[[T6]],0x10
-; MIPS32: sll [[T6]],[[T6]],0x10
-; MIPS32: or [[T0]],[[T0]],[[T6]]
-; MIPS32: srl [[T12:.*]],a2,0x10
-; MIPS32: andi [[T12]],[[T12]],0x1
-; MIPS32: srl [[T2]],[[T2]],0x10
-; MIPS32: andi [[T2]],[[T2]],0x1
-; MIPS32: sll [[T12]],[[T12]],0x1f
-; MIPS32: sll [[T2]],[[T2]],0x1f
-; MIPS32: xor [[T12]],[[T12]],[[T2]]
-; MIPS32: sltu [[T12]],zero,[[T12]]
-; MIPS32: sll [[T12]],[[T12]],0x10
-; MIPS32: sll [[T0]],[[T0]],0x10
-; MIPS32: srl [[T0]],[[T0]],0x10
-; MIPS32: or [[T12]],[[T12]],[[T0]]
-; MIPS32: move [[T0]],a3
-; MIPS32: andi [[T0]],[[T0]],0xffff
-; MIPS32: andi [[T0]],[[T0]],0x1
-; MIPS32: move [[T1]],[[T3]]
-; MIPS32: andi [[T1]],[[T1]],0xffff
-; MIPS32: andi [[T1]],[[T1]],0x1
-; MIPS32: sll [[T0]],[[T0]],0x1f
-; MIPS32: sll [[T1]],[[T1]],0x1f
-; MIPS32: xor [[T0]],[[T0]],[[T1]]
-; MIPS32: sltu [[T0]],zero,[[T0]]
-; MIPS32: andi [[T0]],[[T0]],0xffff
-; MIPS32: srl [[T7]],[[T7]],0x10
-; MIPS32: sll [[T7]],[[T7]],0x10
-; MIPS32: or [[T0]],[[T0]],[[T7]]
-; MIPS32: srl [[T13:.*]],a3,0x10
-; MIPS32: andi [[T13]],[[T13]],0x1
-; MIPS32: srl [[T3]],[[T3]],0x10
-; MIPS32: andi [[T3]],[[T3]],0x1
-; MIPS32: sll [[T13]],[[T13]],0x1f
-; MIPS32: sll [[T3]],[[T3]],0x1f
-; MIPS32: xor [[T13]],[[T13]],[[T3]]
-; MIPS32: sltu [[T13]],zero,[[T13]]
-; MIPS32: sll [[T13]],[[T13]],0x10
-; MIPS32: sll [[T0]],[[T0]],0x10
-; MIPS32: srl [[T0]],[[T0]],0x10
-; MIPS32: or [[T13]],[[T13]],[[T0]]
-; MIPS32: move v0,[[T10]]
-; MIPS32: move v1,[[T11]]
-; MIPS32: move a0,[[T12]]
-; MIPS32: move a1,[[T13]]
-}
-
-define internal <8 x i1> @test_icmp_v8i1_sgt(<8 x i1> %a, <8 x i1> %b) {
-entry:
- %res = icmp sgt <8 x i1> %a, %b
- ret <8 x i1> %res
-; CHECK-LABEL: test_icmp_v8i1_sgt
-; CHECK: pcmpgtw
-
-; MIPS32-LABEL: test_icmp_v8i1_sgt
-; MIPS32: lw [[T0:.*]],
-; MIPS32: lw [[T1:.*]],
-; MIPS32: lw [[T2:.*]],
-; MIPS32: lw [[T3:.*]],
-; MIPS32: move [[T4:.*]],zero
-; MIPS32: move [[T5:.*]],zero
-; MIPS32: move [[T6:.*]],zero
-; MIPS32: move [[T7:.*]],zero
-; MIPS32: move [[T8:.*]],a0
-; MIPS32: andi [[T8]],[[T8]],0xffff
-; MIPS32: andi [[T8]],[[T8]],0x1
-; MIPS32: move [[T9:.*]],[[T0]]
-; MIPS32: andi [[T9]],[[T9]],0xffff
-; MIPS32: andi [[T9]],[[T9]],0x1
-; MIPS32: sll [[T8]],[[T8]],0x1f
-; MIPS32: sll [[T9]],[[T9]],0x1f
-; MIPS32: slt [[T9]],[[T9]],[[T8]]
-; MIPS32: andi [[T9]],[[T9]],0xffff
-; MIPS32: srl [[T4]],[[T4]],0x10
-; MIPS32: sll [[T4]],[[T4]],0x10
-; MIPS32: or [[T9]],[[T9]],[[T4]]
-; MIPS32: srl [[T10:.*]],a0,0x10
-; MIPS32: andi [[T10]],[[T10]],0x1
-; MIPS32: srl [[T0]],[[T0]],0x10
-; MIPS32: andi [[T0]],[[T0]],0x1
-; MIPS32: sll [[T10]],[[T10]],0x1f
-; MIPS32: sll [[T0]],[[T0]],0x1f
-; MIPS32: slt [[T0]],[[T0]],[[T10]]
-; MIPS32: sll [[T0]],[[T0]],0x10
-; MIPS32: sll [[T9]],[[T9]],0x10
-; MIPS32: srl [[T9]],[[T9]],0x10
-; MIPS32: or v0,[[T0]],[[T9]]
-; MIPS32: move [[T10]],a1
-; MIPS32: andi [[T10]],[[T10]],0xffff
-; MIPS32: andi [[T10]],[[T10]],0x1
-; MIPS32: move [[T4]],[[T1]]
-; MIPS32: andi [[T4]],[[T4]],0xffff
-; MIPS32: andi [[T4]],[[T4]],0x1
-; MIPS32: sll [[T10]],[[T10]],0x1f
-; MIPS32: sll [[T4]],[[T4]],0x1f
-; MIPS32: slt [[T4]],[[T4]],[[T10]]
-; MIPS32: andi [[T4]],[[T4]],0xffff
-; MIPS32: srl [[T5]],[[T5]],0x10
-; MIPS32: sll [[T5]],[[T5]],0x10
-; MIPS32: or [[T4]],[[T4]],[[T5]]
-; MIPS32: srl [[T11:.*]],a1,0x10
-; MIPS32: andi [[T11]],[[T11]],0x1
-; MIPS32: srl [[T1]],[[T1]],0x10
-; MIPS32: andi [[T1]],[[T1]],0x1
-; MIPS32: sll [[T11]],[[T11]],0x1f
-; MIPS32: sll [[T1]],[[T1]],0x1f
-; MIPS32: slt [[T1]],[[T1]],[[T11]]
-; MIPS32: sll [[T1]],[[T1]],0x10
-; MIPS32: sll [[T4]],[[T4]],0x10
-; MIPS32: srl [[T4]],[[T4]],0x10
-; MIPS32: or v1,[[T1]],[[T4]]
-; MIPS32: move [[T10]],a2
-; MIPS32: andi [[T10]],[[T10]],0xffff
-; MIPS32: andi [[T10]],[[T10]],0x1
-; MIPS32: move [[T11]],[[T2]]
-; MIPS32: andi [[T11]],[[T11]],0xffff
-; MIPS32: andi [[T11]],[[T11]],0x1
-; MIPS32: sll [[T10]],[[T10]],0x1f
-; MIPS32: sll [[T11]],[[T11]],0x1f
-; MIPS32: slt [[T11]],[[T11]],[[T10]]
-; MIPS32: andi [[T11]],[[T11]],0xffff
-; MIPS32: srl [[T6]],[[T6]],0x10
-; MIPS32: sll [[T6]],[[T6]],0x10
-; MIPS32: or [[T11]],[[T11]],[[T6]]
-; MIPS32: srl [[T12:.*]],a2,0x10
-; MIPS32: andi [[T12]],[[T12]],0x1
-; MIPS32: srl [[T2]],[[T2]],0x10
-; MIPS32: andi [[T2]],[[T2]],0x1
-; MIPS32: sll [[T12]],[[T12]],0x1f
-; MIPS32: sll [[T2]],[[T2]],0x1f
-; MIPS32: slt [[T2]],[[T2]],[[T12]]
-; MIPS32: sll [[T2]],[[T2]],0x10
-; MIPS32: sll [[T11]],[[T11]],0x10
-; MIPS32: srl [[T11]],[[T11]],0x10
-; MIPS32: or [[T2]],[[T2]],[[T11]]
-; MIPS32: move [[T10]],a3
-; MIPS32: andi [[T10]],[[T10]],0xffff
-; MIPS32: andi [[T10]],[[T10]],0x1
-; MIPS32: move [[T11]],[[T3]]
-; MIPS32: andi [[T11]],[[T11]],0xffff
-; MIPS32: andi [[T11]],[[T11]],0x1
-; MIPS32: sll [[T10]],[[T10]],0x1f
-; MIPS32: sll [[T11]],[[T11]],0x1f
-; MIPS32: slt [[T11]],[[T11]],[[T10]]
-; MIPS32: andi [[T11]],[[T11]],0xffff
-; MIPS32: srl [[T7]],[[T7]],0x10
-; MIPS32: sll [[T7]],[[T7]],0x10
-; MIPS32: or [[T11]],[[T11]],[[T7]]
-; MIPS32: srl [[T13:.*]],a3,0x10
-; MIPS32: andi [[T13]],[[T13]],0x1
-; MIPS32: srl [[T3]],[[T3]],0x10
-; MIPS32: andi [[T3]],[[T3]],0x1
-; MIPS32: sll [[T13]],[[T13]],0x1f
-; MIPS32: sll [[T3]],[[T3]],0x1f
-; MIPS32: slt [[T3]],[[T3]],[[T13]]
-; MIPS32: sll [[T3]],[[T3]],0x10
-; MIPS32: sll [[T11]],[[T11]],0x10
-; MIPS32: srl [[T11]],[[T11]],0x10
-; MIPS32: or [[T3]],[[T3]],[[T11]]
-; MIPS32: move a0,[[T2]]
-; MIPS32: move a1,[[T3]]
-}
-
-define internal <8 x i1> @test_icmp_v8i1_sle(<8 x i1> %a, <8 x i1> %b) {
-entry:
- %res = icmp sle <8 x i1> %a, %b
- ret <8 x i1> %res
-; CHECK-LABEL: test_icmp_v8i1_sle
-; CHECK: pcmpgtw
-; CHECK: pxor
-
-; MIPS32-LABEL: test_icmp_v8i1_sle
-; MIPS32: lw [[T0:.*]],
-; MIPS32: lw [[T1:.*]],
-; MIPS32: lw [[T2:.*]],
-; MIPS32: lw [[T3:.*]],
-; MIPS32: move [[T4:.*]],zero
-; MIPS32: move [[T5:.*]],zero
-; MIPS32: move [[T6:.*]],zero
-; MIPS32: move [[T7:.*]],zero
-; MIPS32: move [[T8:.*]],a0
-; MIPS32: andi [[T8]],[[T8]],0xffff
-; MIPS32: andi [[T8]],[[T8]],0x1
-; MIPS32: move [[T9:.*]],[[T0]]
-; MIPS32: andi [[T9]],[[T9]],0xffff
-; MIPS32: andi [[T9]],[[T9]],0x1
-; MIPS32: sll [[T8]],[[T8]],0x1f
-; MIPS32: sll [[T9]],[[T9]],0x1f
-; MIPS32: slt [[T9]],[[T9]],[[T8]]
-; MIPS32: xori [[T9]],[[T9]],0x1
-; MIPS32: andi [[T9]],[[T9]],0xffff
-; MIPS32: srl [[T4]],[[T4]],0x10
-; MIPS32: sll [[T4]],[[T4]],0x10
-; MIPS32: or [[T9]],[[T9]],[[T4]]
-; MIPS32: srl [[T10:.*]],a0,0x10
-; MIPS32: andi [[T10]],[[T10]],0x1
-; MIPS32: srl [[T0]],[[T0]],0x10
-; MIPS32: andi [[T0]],[[T0]],0x1
-; MIPS32: sll [[T10]],[[T10]],0x1f
-; MIPS32: sll [[T0]],[[T0]],0x1f
-; MIPS32: slt [[T0]],[[T0]],[[T10]]
-; MIPS32: xori [[T0]],[[T0]],0x1
-; MIPS32: sll [[T0]],[[T0]],0x10
-; MIPS32: sll [[T9]],[[T9]],0x10
-; MIPS32: srl [[T9]],[[T9]],0x10
-; MIPS32: or v0,[[T0]],[[T9]]
-; MIPS32: move [[T10]],a1
-; MIPS32: andi [[T10]],[[T10]],0xffff
-; MIPS32: andi [[T10]],[[T10]],0x1
-; MIPS32: move [[T4]],[[T1]]
-; MIPS32: andi [[T4]],[[T4]],0xffff
-; MIPS32: andi [[T4]],[[T4]],0x1
-; MIPS32: sll [[T10]],[[T10]],0x1f
-; MIPS32: sll [[T4]],[[T4]],0x1f
-; MIPS32: slt [[T4]],[[T4]],[[T10]]
-; MIPS32: xori [[T4]],[[T4]],0x1
-; MIPS32: andi [[T4]],[[T4]],0xffff
-; MIPS32: srl [[T5]],[[T5]],0x10
-; MIPS32: sll [[T5]],[[T5]],0x10
-; MIPS32: or [[T4]],[[T4]],[[T5]]
-; MIPS32: srl [[T11:.*]],a1,0x10
-; MIPS32: andi [[T11]],[[T11]],0x1
-; MIPS32: srl [[T1]],[[T1]],0x10
-; MIPS32: andi [[T1]],[[T1]],0x1
-; MIPS32: sll [[T11]],[[T11]],0x1f
-; MIPS32: sll [[T1]],[[T1]],0x1f
-; MIPS32: slt [[T1]],[[T1]],[[T11]]
-; MIPS32: xori [[T1]],[[T1]],0x1
-; MIPS32: sll [[T1]],[[T1]],0x10
-; MIPS32: sll [[T4]],[[T4]],0x10
-; MIPS32: srl [[T4]],[[T4]],0x10
-; MIPS32: or v1,[[T1]],[[T4]]
-; MIPS32: move [[T10]],a2
-; MIPS32: andi [[T10]],[[T10]],0xffff
-; MIPS32: andi [[T10]],[[T10]],0x1
-; MIPS32: move [[T11]],[[T2]]
-; MIPS32: andi [[T11]],[[T11]],0xffff
-; MIPS32: andi [[T11]],[[T11]],0x1
-; MIPS32: sll [[T10]],[[T10]],0x1f
-; MIPS32: sll [[T11]],[[T11]],0x1f
-; MIPS32: slt [[T11]],[[T11]],[[T10]]
-; MIPS32: xori [[T11]],[[T11]],0x1
-; MIPS32: andi [[T11]],[[T11]],0xffff
-; MIPS32: srl [[T6]],[[T6]],0x10
-; MIPS32: sll [[T6]],[[T6]],0x10
-; MIPS32: or [[T11]],[[T11]],[[T6]]
-; MIPS32: srl [[T12:.*]],a2,0x10
-; MIPS32: andi [[T12]],[[T12]],0x1
-; MIPS32: srl [[T2]],[[T2]],0x10
-; MIPS32: andi [[T2]],[[T2]],0x1
-; MIPS32: sll [[T12]],[[T12]],0x1f
-; MIPS32: sll [[T2]],[[T2]],0x1f
-; MIPS32: slt [[T2]],[[T2]],[[T12]]
-; MIPS32: xori [[T2]],[[T2]],0x1
-; MIPS32: sll [[T2]],[[T2]],0x10
-; MIPS32: sll [[T11]],[[T11]],0x10
-; MIPS32: srl [[T11]],[[T11]],0x10
-; MIPS32: or [[T2]],[[T2]],[[T11]]
-; MIPS32: move [[T10]],a3
-; MIPS32: andi [[T10]],[[T10]],0xffff
-; MIPS32: andi [[T10]],[[T10]],0x1
-; MIPS32: move [[T11]],[[T3]]
-; MIPS32: andi [[T11]],[[T11]],0xffff
-; MIPS32: andi [[T11]],[[T11]],0x1
-; MIPS32: sll [[T10]],[[T10]],0x1f
-; MIPS32: sll [[T11]],[[T11]],0x1f
-; MIPS32: slt [[T11]],[[T11]],[[T10]]
-; MIPS32: xori [[T11]],[[T11]],0x1
-; MIPS32: andi [[T11]],[[T11]],0xffff
-; MIPS32: srl [[T7]],[[T7]],0x10
-; MIPS32: sll [[T7]],[[T7]],0x10
-; MIPS32: or [[T11]],[[T11]],[[T7]]
-; MIPS32: srl [[T13:.*]],a3,0x10
-; MIPS32: andi [[T13]],[[T13]],0x1
-; MIPS32: srl [[T3]],[[T3]],0x10
-; MIPS32: andi [[T3]],[[T3]],0x1
-; MIPS32: sll [[T13]],[[T13]],0x1f
-; MIPS32: sll [[T3]],[[T3]],0x1f
-; MIPS32: slt [[T3]],[[T3]],[[T13]]
-; MIPS32: xori [[T3]],[[T3]],0x1
-; MIPS32: sll [[T3]],[[T3]],0x10
-; MIPS32: sll [[T11]],[[T11]],0x10
-; MIPS32: srl [[T11]],[[T11]],0x10
-; MIPS32: or [[T3]],[[T3]],[[T11]]
-; MIPS32: move a0,[[T2]]
-; MIPS32: move a1,[[T3]]
-}
-
-define internal <8 x i1> @test_icmp_v8i1_slt(<8 x i1> %a, <8 x i1> %b) {
-entry:
- %res = icmp slt <8 x i1> %a, %b
- ret <8 x i1> %res
-; CHECK-LABEL: test_icmp_v8i1_slt
-; CHECK: pcmpgtw
-
-; MIPS32-LABEL: test_icmp_v8i1_slt
-; MIPS32: lw [[T0:.*]],
-; MIPS32: lw [[T1:.*]],
-; MIPS32: lw [[T2:.*]],
-; MIPS32: lw [[T3:.*]],
-; MIPS32: move [[T4:.*]],zero
-; MIPS32: move [[T5:.*]],zero
-; MIPS32: move [[T6:.*]],zero
-; MIPS32: move [[T7:.*]],zero
-; MIPS32: move [[T8:.*]],a0
-; MIPS32: andi [[T8]],[[T8]],0xffff
-; MIPS32: andi [[T8]],[[T8]],0x1
-; MIPS32: move [[T9:.*]],[[T0]]
-; MIPS32: andi [[T9]],[[T9]],0xffff
-; MIPS32: andi [[T9]],[[T9]],0x1
-; MIPS32: sll [[T8]],[[T8]],0x1f
-; MIPS32: sll [[T9]],[[T9]],0x1f
-; MIPS32: slt [[T8]],[[T8]],[[T9]]
-; MIPS32: andi [[T8]],[[T8]],0xffff
-; MIPS32: srl [[T4]],[[T4]],0x10
-; MIPS32: sll [[T4]],[[T4]],0x10
-; MIPS32: or [[T8]],[[T8]],[[T4]]
-; MIPS32: srl [[T10:.*]],a0,0x10
-; MIPS32: andi [[T10]],[[T10]],0x1
-; MIPS32: srl [[T0]],[[T0]],0x10
-; MIPS32: andi [[T0]],[[T0]],0x1
-; MIPS32: sll [[T10]],[[T10]],0x1f
-; MIPS32: sll [[T0]],[[T0]],0x1f
-; MIPS32: slt [[T10]],[[T10]],[[T0]]
-; MIPS32: sll [[T10]],[[T10]],0x10
-; MIPS32: sll [[T8]],[[T8]],0x10
-; MIPS32: srl [[T8]],[[T8]],0x10
-; MIPS32: or [[T10]],[[T10]],[[T8]]
-; MIPS32: move [[T0]],a1
-; MIPS32: andi [[T0]],[[T0]],0xffff
-; MIPS32: andi [[T0]],[[T0]],0x1
-; MIPS32: move [[T4]],[[T1]]
-; MIPS32: andi [[T4]],[[T4]],0xffff
-; MIPS32: andi [[T4]],[[T4]],0x1
-; MIPS32: sll [[T0]],[[T0]],0x1f
-; MIPS32: sll [[T4]],[[T4]],0x1f
-; MIPS32: slt [[T0]],[[T0]],[[T4]]
-; MIPS32: andi [[T0]],[[T0]],0xffff
-; MIPS32: srl [[T5]],[[T5]],0x10
-; MIPS32: sll [[T5]],[[T5]],0x10
-; MIPS32: or [[T0]],[[T0]],[[T5]]
-; MIPS32: srl [[T11:.*]],a1,0x10
-; MIPS32: andi [[T11]],[[T11]],0x1
-; MIPS32: srl [[T1]],[[T1]],0x10
-; MIPS32: andi [[T1]],[[T1]],0x1
-; MIPS32: sll [[T11]],[[T11]],0x1f
-; MIPS32: sll [[T1]],[[T1]],0x1f
-; MIPS32: slt [[T11]],[[T11]],[[T1]]
-; MIPS32: sll [[T11]],[[T11]],0x10
-; MIPS32: sll [[T0]],[[T0]],0x10
-; MIPS32: srl [[T0]],[[T0]],0x10
-; MIPS32: or [[T11]],[[T11]],[[T0]]
-; MIPS32: move [[T0]],a2
-; MIPS32: andi [[T0]],[[T0]],0xffff
-; MIPS32: andi [[T0]],[[T0]],0x1
-; MIPS32: move [[T1]],[[T2]]
-; MIPS32: andi [[T1]],[[T1]],0xffff
-; MIPS32: andi [[T1]],[[T1]],0x1
-; MIPS32: sll [[T0]],[[T0]],0x1f
-; MIPS32: sll [[T1]],[[T1]],0x1f
-; MIPS32: slt [[T0]],[[T0]],[[T1]]
-; MIPS32: andi [[T0]],[[T0]],0xffff
-; MIPS32: srl [[T6]],[[T6]],0x10
-; MIPS32: sll [[T6]],[[T6]],0x10
-; MIPS32: or [[T0]],[[T0]],[[T6]]
-; MIPS32: srl [[T12:.*]],a2,0x10
-; MIPS32: andi [[T12]],[[T12]],0x1
-; MIPS32: srl [[T2]],[[T2]],0x10
-; MIPS32: andi [[T2]],[[T2]],0x1
-; MIPS32: sll [[T12]],[[T12]],0x1f
-; MIPS32: sll [[T2]],[[T2]],0x1f
-; MIPS32: slt [[T12]],[[T12]],[[T2]]
-; MIPS32: sll [[T12]],[[T12]],0x10
-; MIPS32: sll [[T0]],[[T0]],0x10
-; MIPS32: srl [[T0]],[[T0]],0x10
-; MIPS32: or [[T12]],[[T12]],[[T0]]
-; MIPS32: move [[T0]],a3
-; MIPS32: andi [[T0]],[[T0]],0xffff
-; MIPS32: andi [[T0]],[[T0]],0x1
-; MIPS32: move [[T1]],[[T3]]
-; MIPS32: andi [[T1]],[[T1]],0xffff
-; MIPS32: andi [[T1]],[[T1]],0x1
-; MIPS32: sll [[T0]],[[T0]],0x1f
-; MIPS32: sll [[T1]],[[T1]],0x1f
-; MIPS32: slt [[T0]],[[T0]],[[T1]]
-; MIPS32: andi [[T0]],[[T0]],0xffff
-; MIPS32: srl [[T7]],[[T7]],0x10
-; MIPS32: sll [[T7]],[[T7]],0x10
-; MIPS32: or [[T0]],[[T0]],[[T7]]
-; MIPS32: srl [[T13:.*]],a3,0x10
-; MIPS32: andi [[T13]],[[T13]],0x1
-; MIPS32: srl [[T3]],[[T3]],0x10
-; MIPS32: andi [[T3]],[[T3]],0x1
-; MIPS32: sll [[T13]],[[T13]],0x1f
-; MIPS32: sll [[T3]],[[T3]],0x1f
-; MIPS32: slt [[T13]],[[T13]],[[T3]]
-; MIPS32: sll [[T13]],[[T13]],0x10
-; MIPS32: sll [[T0]],[[T0]],0x10
-; MIPS32: srl [[T0]],[[T0]],0x10
-; MIPS32: or [[T13]],[[T13]],[[T0]]
-; MIPS32: move v0,[[T10]]
-; MIPS32: move v1,[[T11]]
-; MIPS32: move a0,[[T12]]
-; MIPS32: move a1,[[T13]]
-}
-
-define internal <8 x i1> @test_icmp_v8i1_uge(<8 x i1> %a, <8 x i1> %b) {
-entry:
- %res = icmp uge <8 x i1> %a, %b
- ret <8 x i1> %res
-; CHECK-LABEL: test_icmp_v8i1_uge
-; CHECK: pxor
-; CHECK: pcmpgtw
-; CHECK: pxor
-
-; MIPS32-LABEL: test_icmp_v8i1_uge
-; MIPS32: lw [[T0:.*]],
-; MIPS32: lw [[T1:.*]],
-; MIPS32: lw [[T2:.*]],
-; MIPS32: lw [[T3:.*]],
-; MIPS32: move [[T4:.*]],zero
-; MIPS32: move [[T5:.*]],zero
-; MIPS32: move [[T6:.*]],zero
-; MIPS32: move [[T7:.*]],zero
-; MIPS32: move [[T8:.*]],a0
-; MIPS32: andi [[T8]],[[T8]],0xffff
-; MIPS32: andi [[T8]],[[T8]],0x1
-; MIPS32: move [[T9:.*]],[[T0]]
-; MIPS32: andi [[T9]],[[T9]],0xffff
-; MIPS32: andi [[T9]],[[T9]],0x1
-; MIPS32: sll [[T8]],[[T8]],0x1f
-; MIPS32: sll [[T9]],[[T9]],0x1f
-; MIPS32: sltu [[T8]],[[T8]],[[T9]]
-; MIPS32: xori [[T8]],[[T8]],0x1
-; MIPS32: andi [[T8]],[[T8]],0xffff
-; MIPS32: srl [[T4]],[[T4]],0x10
-; MIPS32: sll [[T4]],[[T4]],0x10
-; MIPS32: or [[T8]],[[T8]],[[T4]]
-; MIPS32: srl [[T10:.*]],a0,0x10
-; MIPS32: andi [[T10]],[[T10]],0x1
-; MIPS32: srl [[T0]],[[T0]],0x10
-; MIPS32: andi [[T0]],[[T0]],0x1
-; MIPS32: sll [[T10]],[[T10]],0x1f
-; MIPS32: sll [[T0]],[[T0]],0x1f
-; MIPS32: sltu [[T10]],[[T10]],[[T0]]
-; MIPS32: xori [[T10]],[[T10]],0x1
-; MIPS32: sll [[T10]],[[T10]],0x10
-; MIPS32: sll [[T8]],[[T8]],0x10
-; MIPS32: srl [[T8]],[[T8]],0x10
-; MIPS32: or [[T10]],[[T10]],[[T8]]
-; MIPS32: move [[T0]],a1
-; MIPS32: andi [[T0]],[[T0]],0xffff
-; MIPS32: andi [[T0]],[[T0]],0x1
-; MIPS32: move [[T4]],[[T1]]
-; MIPS32: andi [[T4]],[[T4]],0xffff
-; MIPS32: andi [[T4]],[[T4]],0x1
-; MIPS32: sll [[T0]],[[T0]],0x1f
-; MIPS32: sll [[T4]],[[T4]],0x1f
-; MIPS32: sltu [[T0]],[[T0]],[[T4]]
-; MIPS32: xori [[T0]],[[T0]],0x1
-; MIPS32: andi [[T0]],[[T0]],0xffff
-; MIPS32: srl [[T5]],[[T5]],0x10
-; MIPS32: sll [[T5]],[[T5]],0x10
-; MIPS32: or [[T0]],[[T0]],[[T5]]
-; MIPS32: srl [[T11:.*]],a1,0x10
-; MIPS32: andi [[T11]],[[T11]],0x1
-; MIPS32: srl [[T1]],[[T1]],0x10
-; MIPS32: andi [[T1]],[[T1]],0x1
-; MIPS32: sll [[T11]],[[T11]],0x1f
-; MIPS32: sll [[T1]],[[T1]],0x1f
-; MIPS32: sltu [[T11]],[[T11]],[[T1]]
-; MIPS32: xori [[T11]],[[T11]],0x1
-; MIPS32: sll [[T11]],[[T11]],0x10
-; MIPS32: sll [[T0]],[[T0]],0x10
-; MIPS32: srl [[T0]],[[T0]],0x10
-; MIPS32: or [[T11]],[[T11]],[[T0]]
-; MIPS32: move [[T0]],a2
-; MIPS32: andi [[T0]],[[T0]],0xffff
-; MIPS32: andi [[T0]],[[T0]],0x1
-; MIPS32: move [[T1]],[[T2]]
-; MIPS32: andi [[T1]],[[T1]],0xffff
-; MIPS32: andi [[T1]],[[T1]],0x1
-; MIPS32: sll [[T0]],[[T0]],0x1f
-; MIPS32: sll [[T1]],[[T1]],0x1f
-; MIPS32: sltu [[T0]],[[T0]],[[T1]]
-; MIPS32: xori [[T0]],[[T0]],0x1
-; MIPS32: andi [[T0]],[[T0]],0xffff
-; MIPS32: srl [[T6]],[[T6]],0x10
-; MIPS32: sll [[T6]],[[T6]],0x10
-; MIPS32: or [[T0]],[[T0]],[[T6]]
-; MIPS32: srl [[T12:.*]],a2,0x10
-; MIPS32: andi [[T12]],[[T12]],0x1
-; MIPS32: srl [[T2]],[[T2]],0x10
-; MIPS32: andi [[T2]],[[T2]],0x1
-; MIPS32: sll [[T12]],[[T12]],0x1f
-; MIPS32: sll [[T2]],[[T2]],0x1f
-; MIPS32: sltu [[T12]],[[T12]],[[T2]]
-; MIPS32: xori [[T12]],[[T12]],0x1
-; MIPS32: sll [[T12]],[[T12]],0x10
-; MIPS32: sll [[T0]],[[T0]],0x10
-; MIPS32: srl [[T0]],[[T0]],0x10
-; MIPS32: or [[T12]],[[T12]],[[T0]]
-; MIPS32: move [[T0]],a3
-; MIPS32: andi [[T0]],[[T0]],0xffff
-; MIPS32: andi [[T0]],[[T0]],0x1
-; MIPS32: move [[T1]],[[T3]]
-; MIPS32: andi [[T1]],[[T1]],0xffff
-; MIPS32: andi [[T1]],[[T1]],0x1
-; MIPS32: sll [[T0]],[[T0]],0x1f
-; MIPS32: sll [[T1]],[[T1]],0x1f
-; MIPS32: sltu [[T0]],[[T0]],[[T1]]
-; MIPS32: xori [[T0]],[[T0]],0x1
-; MIPS32: andi [[T0]],[[T0]],0xffff
-; MIPS32: srl [[T7]],[[T7]],0x10
-; MIPS32: sll [[T7]],[[T7]],0x10
-; MIPS32: or [[T0]],[[T0]],[[T7]]
-; MIPS32: srl [[T13:.*]],a3,0x10
-; MIPS32: andi [[T13]],[[T13]],0x1
-; MIPS32: srl [[T3]],[[T3]],0x10
-; MIPS32: andi [[T3]],[[T3]],0x1
-; MIPS32: sll [[T13]],[[T13]],0x1f
-; MIPS32: sll [[T3]],[[T3]],0x1f
-; MIPS32: sltu [[T13]],[[T13]],[[T3]]
-; MIPS32: xori [[T13]],[[T13]],0x1
-; MIPS32: sll [[T13]],[[T13]],0x10
-; MIPS32: sll [[T0]],[[T0]],0x10
-; MIPS32: srl [[T0]],[[T0]],0x10
-; MIPS32: or [[T13]],[[T13]],[[T0]]
-; MIPS32: move v0,[[T10]]
-; MIPS32: move v1,[[T11]]
-; MIPS32: move a0,[[T12]]
-; MIPS32: move a1,[[T13]]
-}
-
-define internal <8 x i1> @test_icmp_v8i1_ugt(<8 x i1> %a, <8 x i1> %b) {
-entry:
- %res = icmp ugt <8 x i1> %a, %b
- ret <8 x i1> %res
-; CHECK-LABEL: test_icmp_v8i1_ugt
-; CHECK: pxor
-; CHECK: pcmpgtw
-
-; MIPS32-LABEL: test_icmp_v8i1_ugt
-; MIPS32: lw [[T0:.*]],
-; MIPS32: lw [[T1:.*]],
-; MIPS32: lw [[T2:.*]],
-; MIPS32: lw [[T3:.*]],
-; MIPS32: move [[T4:.*]],zero
-; MIPS32: move [[T5:.*]],zero
-; MIPS32: move [[T6:.*]],zero
-; MIPS32: move [[T7:.*]],zero
-; MIPS32: move [[T8:.*]],a0
-; MIPS32: andi [[T8]],[[T8]],0xffff
-; MIPS32: andi [[T8]],[[T8]],0x1
-; MIPS32: move [[T9:.*]],[[T0]]
-; MIPS32: andi [[T9]],[[T9]],0xffff
-; MIPS32: andi [[T9]],[[T9]],0x1
-; MIPS32: sll [[T8]],[[T8]],0x1f
-; MIPS32: sll [[T9]],[[T9]],0x1f
-; MIPS32: sltu [[T9]],[[T9]],[[T8]]
-; MIPS32: andi [[T9]],[[T9]],0xffff
-; MIPS32: srl [[T4]],[[T4]],0x10
-; MIPS32: sll [[T4]],[[T4]],0x10
-; MIPS32: or [[T9]],[[T9]],[[T4]]
-; MIPS32: srl [[T10:.*]],a0,0x10
-; MIPS32: andi [[T10]],[[T10]],0x1
-; MIPS32: srl [[T0]],[[T0]],0x10
-; MIPS32: andi [[T0]],[[T0]],0x1
-; MIPS32: sll [[T10]],[[T10]],0x1f
-; MIPS32: sll [[T0]],[[T0]],0x1f
-; MIPS32: sltu [[T0]],[[T0]],[[T10]]
-; MIPS32: sll [[T0]],[[T0]],0x10
-; MIPS32: sll [[T9]],[[T9]],0x10
-; MIPS32: srl [[T9]],[[T9]],0x10
-; MIPS32: or v0,[[T0]],[[T9]]
-; MIPS32: move [[T10]],a1
-; MIPS32: andi [[T10]],[[T10]],0xffff
-; MIPS32: andi [[T10]],[[T10]],0x1
-; MIPS32: move [[T4]],[[T1]]
-; MIPS32: andi [[T4]],[[T4]],0xffff
-; MIPS32: andi [[T4]],[[T4]],0x1
-; MIPS32: sll [[T10]],[[T10]],0x1f
-; MIPS32: sll [[T4]],[[T4]],0x1f
-; MIPS32: sltu [[T4]],[[T4]],[[T10]]
-; MIPS32: andi [[T4]],[[T4]],0xffff
-; MIPS32: srl [[T5]],[[T5]],0x10
-; MIPS32: sll [[T5]],[[T5]],0x10
-; MIPS32: or [[T4]],[[T4]],[[T5]]
-; MIPS32: srl [[T11:.*]],a1,0x10
-; MIPS32: andi [[T11]],[[T11]],0x1
-; MIPS32: srl [[T1]],[[T1]],0x10
-; MIPS32: andi [[T1]],[[T1]],0x1
-; MIPS32: sll [[T11]],[[T11]],0x1f
-; MIPS32: sll [[T1]],[[T1]],0x1f
-; MIPS32: sltu [[T1]],[[T1]],[[T11]]
-; MIPS32: sll [[T1]],[[T1]],0x10
-; MIPS32: sll [[T4]],[[T4]],0x10
-; MIPS32: srl [[T4]],[[T4]],0x10
-; MIPS32: or v1,[[T1]],[[T4]]
-; MIPS32: move [[T10]],a2
-; MIPS32: andi [[T10]],[[T10]],0xffff
-; MIPS32: andi [[T10]],[[T10]],0x1
-; MIPS32: move [[T11]],[[T2]]
-; MIPS32: andi [[T11]],[[T11]],0xffff
-; MIPS32: andi [[T11]],[[T11]],0x1
-; MIPS32: sll [[T10]],[[T10]],0x1f
-; MIPS32: sll [[T11]],[[T11]],0x1f
-; MIPS32: sltu [[T11]],[[T11]],[[T10]]
-; MIPS32: andi [[T11]],[[T11]],0xffff
-; MIPS32: srl [[T6]],[[T6]],0x10
-; MIPS32: sll [[T6]],[[T6]],0x10
-; MIPS32: or [[T11]],[[T11]],[[T6]]
-; MIPS32: srl [[T12:.*]],a2,0x10
-; MIPS32: andi [[T12]],[[T12]],0x1
-; MIPS32: srl [[T2]],[[T2]],0x10
-; MIPS32: andi [[T2]],[[T2]],0x1
-; MIPS32: sll [[T12]],[[T12]],0x1f
-; MIPS32: sll [[T2]],[[T2]],0x1f
-; MIPS32: sltu [[T2]],[[T2]],[[T12]]
-; MIPS32: sll [[T2]],[[T2]],0x10
-; MIPS32: sll [[T11]],[[T11]],0x10
-; MIPS32: srl [[T11]],[[T11]],0x10
-; MIPS32: or [[T2]],[[T2]],[[T11]]
-; MIPS32: move [[T10]],a3
-; MIPS32: andi [[T10]],[[T10]],0xffff
-; MIPS32: andi [[T10]],[[T10]],0x1
-; MIPS32: move [[T11]],[[T3]]
-; MIPS32: andi [[T11]],[[T11]],0xffff
-; MIPS32: andi [[T11]],[[T11]],0x1
-; MIPS32: sll [[T10]],[[T10]],0x1f
-; MIPS32: sll [[T11]],[[T11]],0x1f
-; MIPS32: sltu [[T11]],[[T11]],[[T10]]
-; MIPS32: andi [[T11]],[[T11]],0xffff
-; MIPS32: srl [[T7]],[[T7]],0x10
-; MIPS32: sll [[T7]],[[T7]],0x10
-; MIPS32: or [[T11]],[[T11]],[[T7]]
-; MIPS32: srl [[T13:.*]],a3,0x10
-; MIPS32: andi [[T13]],[[T13]],0x1
-; MIPS32: srl [[T3]],[[T3]],0x10
-; MIPS32: andi [[T3]],[[T3]],0x1
-; MIPS32: sll [[T13]],[[T13]],0x1f
-; MIPS32: sll [[T3]],[[T3]],0x1f
-; MIPS32: sltu [[T3]],[[T3]],[[T13]]
-; MIPS32: sll [[T3]],[[T3]],0x10
-; MIPS32: sll [[T11]],[[T11]],0x10
-; MIPS32: srl [[T11]],[[T11]],0x10
-; MIPS32: or [[T3]],[[T3]],[[T11]]
-; MIPS32: move a0,[[T2]]
-; MIPS32: move a1,[[T3]]
-}
-
-define internal <8 x i1> @test_icmp_v8i1_ule(<8 x i1> %a, <8 x i1> %b) {
-entry:
- %res = icmp ule <8 x i1> %a, %b
- ret <8 x i1> %res
-; CHECK-LABEL: test_icmp_v8i1_ule
-; CHECK: pxor
-; CHECK: pcmpgtw
-; CHECK: pxor
-
-; MIPS32-LABEL: test_icmp_v8i1_ule
-; MIPS32: lw [[T0:.*]],
-; MIPS32: lw [[T1:.*]],
-; MIPS32: lw [[T2:.*]],
-; MIPS32: lw [[T3:.*]],
-; MIPS32: move [[T4:.*]],zero
-; MIPS32: move [[T5:.*]],zero
-; MIPS32: move [[T6:.*]],zero
-; MIPS32: move [[T7:.*]],zero
-; MIPS32: move [[T8:.*]],a0
-; MIPS32: andi [[T8]],[[T8]],0xffff
-; MIPS32: andi [[T8]],[[T8]],0x1
-; MIPS32: move [[T9:.*]],[[T0]]
-; MIPS32: andi [[T9]],[[T9]],0xffff
-; MIPS32: andi [[T9]],[[T9]],0x1
-; MIPS32: sll [[T8]],[[T8]],0x1f
-; MIPS32: sll [[T9]],[[T9]],0x1f
-; MIPS32: sltu [[T9]],[[T9]],[[T8]]
-; MIPS32: xori [[T9]],[[T9]],0x1
-; MIPS32: andi [[T9]],[[T9]],0xffff
-; MIPS32: srl [[T4]],[[T4]],0x10
-; MIPS32: sll [[T4]],[[T4]],0x10
-; MIPS32: or [[T9]],[[T9]],[[T4]]
-; MIPS32: srl [[T10:.*]],a0,0x10
-; MIPS32: andi [[T10]],[[T10]],0x1
-; MIPS32: srl [[T0]],[[T0]],0x10
-; MIPS32: andi [[T0]],[[T0]],0x1
-; MIPS32: sll [[T10]],[[T10]],0x1f
-; MIPS32: sll [[T0]],[[T0]],0x1f
-; MIPS32: sltu [[T0]],[[T0]],[[T10]]
-; MIPS32: xori [[T0]],[[T0]],0x1
-; MIPS32: sll [[T0]],[[T0]],0x10
-; MIPS32: sll [[T9]],[[T9]],0x10
-; MIPS32: srl [[T9]],[[T9]],0x10
-; MIPS32: or v0,[[T0]],[[T9]]
-; MIPS32: move [[T10]],a1
-; MIPS32: andi [[T10]],[[T10]],0xffff
-; MIPS32: andi [[T10]],[[T10]],0x1
-; MIPS32: move [[T4]],[[T1]]
-; MIPS32: andi [[T4]],[[T4]],0xffff
-; MIPS32: andi [[T4]],[[T4]],0x1
-; MIPS32: sll [[T10]],[[T10]],0x1f
-; MIPS32: sll [[T4]],[[T4]],0x1f
-; MIPS32: sltu [[T4]],[[T4]],[[T10]]
-; MIPS32: xori [[T4]],[[T4]],0x1
-; MIPS32: andi [[T4]],[[T4]],0xffff
-; MIPS32: srl [[T5]],[[T5]],0x10
-; MIPS32: sll [[T5]],[[T5]],0x10
-; MIPS32: or [[T4]],[[T4]],[[T5]]
-; MIPS32: srl [[T11:.*]],a1,0x10
-; MIPS32: andi [[T11]],[[T11]],0x1
-; MIPS32: srl [[T1]],[[T1]],0x10
-; MIPS32: andi [[T1]],[[T1]],0x1
-; MIPS32: sll [[T11]],[[T11]],0x1f
-; MIPS32: sll [[T1]],[[T1]],0x1f
-; MIPS32: sltu [[T1]],[[T1]],[[T11]]
-; MIPS32: xori [[T1]],[[T1]],0x1
-; MIPS32: sll [[T1]],[[T1]],0x10
-; MIPS32: sll [[T4]],[[T4]],0x10
-; MIPS32: srl [[T4]],[[T4]],0x10
-; MIPS32: or v1,[[T1]],[[T4]]
-; MIPS32: move [[T10]],a2
-; MIPS32: andi [[T10]],[[T10]],0xffff
-; MIPS32: andi [[T10]],[[T10]],0x1
-; MIPS32: move [[T11]],[[T2]]
-; MIPS32: andi [[T11]],[[T11]],0xffff
-; MIPS32: andi [[T11]],[[T11]],0x1
-; MIPS32: sll [[T10]],[[T10]],0x1f
-; MIPS32: sll [[T11]],[[T11]],0x1f
-; MIPS32: sltu [[T11]],[[T11]],[[T10]]
-; MIPS32: xori [[T11]],[[T11]],0x1
-; MIPS32: andi [[T11]],[[T11]],0xffff
-; MIPS32: srl [[T6]],[[T6]],0x10
-; MIPS32: sll [[T6]],[[T6]],0x10
-; MIPS32: or [[T11]],[[T11]],[[T6]]
-; MIPS32: srl [[T12:.*]],a2,0x10
-; MIPS32: andi [[T12]],[[T12]],0x1
-; MIPS32: srl [[T2]],[[T2]],0x10
-; MIPS32: andi [[T2]],[[T2]],0x1
-; MIPS32: sll [[T12]],[[T12]],0x1f
-; MIPS32: sll [[T2]],[[T2]],0x1f
-; MIPS32: sltu [[T2]],[[T2]],[[T12]]
-; MIPS32: xori [[T2]],[[T2]],0x1
-; MIPS32: sll [[T2]],[[T2]],0x10
-; MIPS32: sll [[T11]],[[T11]],0x10
-; MIPS32: srl [[T11]],[[T11]],0x10
-; MIPS32: or [[T2]],[[T2]],[[T11]]
-; MIPS32: move [[T10]],a3
-; MIPS32: andi [[T10]],[[T10]],0xffff
-; MIPS32: andi [[T10]],[[T10]],0x1
-; MIPS32: move [[T11]],[[T3]]
-; MIPS32: andi [[T11]],[[T11]],0xffff
-; MIPS32: andi [[T11]],[[T11]],0x1
-; MIPS32: sll [[T10]],[[T10]],0x1f
-; MIPS32: sll [[T11]],[[T11]],0x1f
-; MIPS32: sltu [[T11]],[[T11]],[[T10]]
-; MIPS32: xori [[T11]],[[T11]],0x1
-; MIPS32: andi [[T11]],[[T11]],0xffff
-; MIPS32: srl [[T7]],[[T7]],0x10
-; MIPS32: sll [[T7]],[[T7]],0x10
-; MIPS32: or [[T11]],[[T11]],[[T7]]
-; MIPS32: srl [[T13:.*]],a3,0x10
-; MIPS32: andi [[T13]],[[T13]],0x1
-; MIPS32: srl [[T3]],[[T3]],0x10
-; MIPS32: andi [[T3]],[[T3]],0x1
-; MIPS32: sll [[T13]],[[T13]],0x1f
-; MIPS32: sll [[T3]],[[T3]],0x1f
-; MIPS32: sltu [[T3]],[[T3]],[[T13]]
-; MIPS32: xori [[T3]],[[T3]],0x1
-; MIPS32: sll [[T3]],[[T3]],0x10
-; MIPS32: sll [[T11]],[[T11]],0x10
-; MIPS32: srl [[T11]],[[T11]],0x10
-; MIPS32: or [[T3]],[[T3]],[[T11]]
-; MIPS32: move a0,[[T2]]
-; MIPS32: move a1,[[T3]]
-}
-
-define internal <8 x i1> @test_icmp_v8i1_ult(<8 x i1> %a, <8 x i1> %b) {
-entry:
- %res = icmp ult <8 x i1> %a, %b
- ret <8 x i1> %res
-; CHECK-LABEL: test_icmp_v8i1_ult
-; CHECK: pxor
-; CHECK: pcmpgtw
-
-; MIPS32-LABEL: test_icmp_v8i1_ult
-; MIPS32: lw [[T0:.*]],
-; MIPS32: lw [[T1:.*]],
-; MIPS32: lw [[T2:.*]],
-; MIPS32: lw [[T3:.*]],
-; MIPS32: move [[T4:.*]],zero
-; MIPS32: move [[T5:.*]],zero
-; MIPS32: move [[T6:.*]],zero
-; MIPS32: move [[T7:.*]],zero
-; MIPS32: move [[T8:.*]],a0
-; MIPS32: andi [[T8]],[[T8]],0xffff
-; MIPS32: andi [[T8]],[[T8]],0x1
-; MIPS32: move [[T9:.*]],[[T0]]
-; MIPS32: andi [[T9]],[[T9]],0xffff
-; MIPS32: andi [[T9]],[[T9]],0x1
-; MIPS32: sll [[T8]],[[T8]],0x1f
-; MIPS32: sll [[T9]],[[T9]],0x1f
-; MIPS32: sltu [[T8]],[[T8]],[[T9]]
-; MIPS32: andi [[T8]],[[T8]],0xffff
-; MIPS32: srl [[T4]],[[T4]],0x10
-; MIPS32: sll [[T4]],[[T4]],0x10
-; MIPS32: or [[T8]],[[T8]],[[T4]]
-; MIPS32: srl [[T10:.*]],a0,0x10
-; MIPS32: andi [[T10]],[[T10]],0x1
-; MIPS32: srl [[T0]],[[T0]],0x10
-; MIPS32: andi [[T0]],[[T0]],0x1
-; MIPS32: sll [[T10]],[[T10]],0x1f
-; MIPS32: sll [[T0]],[[T0]],0x1f
-; MIPS32: sltu [[T10]],[[T10]],[[T0]]
-; MIPS32: sll [[T10]],[[T10]],0x10
-; MIPS32: sll [[T8]],[[T8]],0x10
-; MIPS32: srl [[T8]],[[T8]],0x10
-; MIPS32: or [[T10]],[[T10]],[[T8]]
-; MIPS32: move [[T0]],a1
-; MIPS32: andi [[T0]],[[T0]],0xffff
-; MIPS32: andi [[T0]],[[T0]],0x1
-; MIPS32: move [[T4]],[[T1]]
-; MIPS32: andi [[T4]],[[T4]],0xffff
-; MIPS32: andi [[T4]],[[T4]],0x1
-; MIPS32: sll [[T0]],[[T0]],0x1f
-; MIPS32: sll [[T4]],[[T4]],0x1f
-; MIPS32: sltu [[T0]],[[T0]],[[T4]]
-; MIPS32: andi [[T0]],[[T0]],0xffff
-; MIPS32: srl [[T5]],[[T5]],0x10
-; MIPS32: sll [[T5]],[[T5]],0x10
-; MIPS32: or [[T0]],[[T0]],[[T5]]
-; MIPS32: srl [[T11:.*]],a1,0x10
-; MIPS32: andi [[T11]],[[T11]],0x1
-; MIPS32: srl [[T1]],[[T1]],0x10
-; MIPS32: andi [[T1]],[[T1]],0x1
-; MIPS32: sll [[T11]],[[T11]],0x1f
-; MIPS32: sll [[T1]],[[T1]],0x1f
-; MIPS32: sltu [[T11]],[[T11]],[[T1]]
-; MIPS32: sll [[T11]],[[T11]],0x10
-; MIPS32: sll [[T0]],[[T0]],0x10
-; MIPS32: srl [[T0]],[[T0]],0x10
-; MIPS32: or [[T11]],[[T11]],[[T0]]
-; MIPS32: move [[T0]],a2
-; MIPS32: andi [[T0]],[[T0]],0xffff
-; MIPS32: andi [[T0]],[[T0]],0x1
-; MIPS32: move [[T1]],[[T2]]
-; MIPS32: andi [[T1]],[[T1]],0xffff
-; MIPS32: andi [[T1]],[[T1]],0x1
-; MIPS32: sll [[T0]],[[T0]],0x1f
-; MIPS32: sll [[T1]],[[T1]],0x1f
-; MIPS32: sltu [[T0]],[[T0]],[[T1]]
-; MIPS32: andi [[T0]],[[T0]],0xffff
-; MIPS32: srl [[T6]],[[T6]],0x10
-; MIPS32: sll [[T6]],[[T6]],0x10
-; MIPS32: or [[T0]],[[T0]],[[T6]]
-; MIPS32: srl [[T12:.*]],a2,0x10
-; MIPS32: andi [[T12]],[[T12]],0x1
-; MIPS32: srl [[T2]],[[T2]],0x10
-; MIPS32: andi [[T2]],[[T2]],0x1
-; MIPS32: sll [[T12]],[[T12]],0x1f
-; MIPS32: sll [[T2]],[[T2]],0x1f
-; MIPS32: sltu [[T12]],[[T12]],[[T2]]
-; MIPS32: sll [[T12]],[[T12]],0x10
-; MIPS32: sll [[T0]],[[T0]],0x10
-; MIPS32: srl [[T0]],[[T0]],0x10
-; MIPS32: or [[T12]],[[T12]],[[T0]]
-; MIPS32: move [[T0]],a3
-; MIPS32: andi [[T0]],[[T0]],0xffff
-; MIPS32: andi [[T0]],[[T0]],0x1
-; MIPS32: move [[T1]],[[T3]]
-; MIPS32: andi [[T1]],[[T1]],0xffff
-; MIPS32: andi [[T1]],[[T1]],0x1
-; MIPS32: sll [[T0]],[[T0]],0x1f
-; MIPS32: sll [[T1]],[[T1]],0x1f
-; MIPS32: sltu [[T0]],[[T0]],[[T1]]
-; MIPS32: andi [[T0]],[[T0]],0xffff
-; MIPS32: srl [[T7]],[[T7]],0x10
-; MIPS32: sll [[T7]],[[T7]],0x10
-; MIPS32: or [[T0]],[[T0]],[[T7]]
-; MIPS32: srl [[T13:.*]],a3,0x10
-; MIPS32: andi [[T13]],[[T13]],0x1
-; MIPS32: srl [[T3]],[[T3]],0x10
-; MIPS32: andi [[T3]],[[T3]],0x1
-; MIPS32: sll [[T13]],[[T13]],0x1f
-; MIPS32: sll [[T3]],[[T3]],0x1f
-; MIPS32: sltu [[T13]],[[T13]],[[T3]]
-; MIPS32: sll [[T13]],[[T13]],0x10
-; MIPS32: sll [[T0]],[[T0]],0x10
-; MIPS32: srl [[T0]],[[T0]],0x10
-; MIPS32: or [[T13]],[[T13]],[[T0]]
-; MIPS32: move v0,[[T10]]
-; MIPS32: move v1,[[T11]]
-; MIPS32: move a0,[[T12]]
-; MIPS32: move a1,[[T13]]
-}
-
-define internal <16 x i1> @test_icmp_v16i8_eq(<16 x i8> %a, <16 x i8> %b) {
-entry:
- %res = icmp eq <16 x i8> %a, %b
- ret <16 x i1> %res
-; CHECK-LABEL: test_icmp_v16i8_eq
-; CHECK: pcmpeqb
-
-; MIPS32-LABEL: test_icmp_v16i8_eq
-; MIPS32: lw [[T0:.*]],
-; MIPS32: lw [[T1:.*]],
-; MIPS32: lw [[T2:.*]],
-; MIPS32: lw [[T3:.*]],
-; MIPS32: move [[T4:.*]],zero
-; MIPS32: move [[T5:.*]],zero
-; MIPS32: move [[T6:.*]],zero
-; MIPS32: move [[T7:.*]],zero
-; MIPS32: move [[T8:.*]],a0
-; MIPS32: andi [[T8]],[[T8]],0xff
-; MIPS32: move [[T9:.*]],[[T0]]
-; MIPS32: andi [[T9]],[[T9]],0xff
-; MIPS32: sll [[T8]],[[T8]],0x18
-; MIPS32: sll [[T9]],[[T9]],0x18
-; MIPS32: xor [[T8]],[[T8]],[[T9]]
-; MIPS32: sltiu [[T8]],[[T8]],1
-; MIPS32: andi [[T8]],[[T8]],0xff
-; MIPS32: srl [[T4]],[[T4]],0x8
-; MIPS32: sll [[T4]],[[T4]],0x8
-; MIPS32: or [[T8]],[[T8]],[[T4]]
-; MIPS32: move [[T4]],a0
-; MIPS32: srl [[T4]],[[T4]],0x8
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: move [[T9]],[[T0]]
-; MIPS32: srl [[T9]],[[T9]],0x8
-; MIPS32: andi [[T9]],[[T9]],0xff
-; MIPS32: sll [[T4]],[[T4]],0x18
-; MIPS32: sll [[T9]],[[T9]],0x18
-; MIPS32: xor [[T4]],[[T4]],[[T9]]
-; MIPS32: sltiu [[T4]],[[T4]],1
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: sll [[T4]],[[T4]],0x8
-; MIPS32: lui [[T9]],0xffff
-; MIPS32: ori [[T9]],[[T9]],0xff
-; MIPS32: and [[T8]],[[T8]],[[T9]]
-; MIPS32: or [[T4]],[[T4]],[[T8]]
-; MIPS32: move [[T8]],a0
-; MIPS32: srl [[T8]],[[T8]],0x10
-; MIPS32: andi [[T8]],[[T8]],0xff
-; MIPS32: move [[T9]],[[T0]]
-; MIPS32: srl [[T9]],[[T9]],0x10
-; MIPS32: andi [[T9]],[[T9]],0xff
-; MIPS32: sll [[T8]],[[T8]],0x18
-; MIPS32: sll [[T9]],[[T9]],0x18
-; MIPS32: xor [[T8]],[[T8]],[[T9]]
-; MIPS32: sltiu [[T8]],[[T8]],1
-; MIPS32: andi [[T8]],[[T8]],0xff
-; MIPS32: sll [[T8]],[[T8]],0x10
-; MIPS32: lui [[T9]],0xff00
-; MIPS32: ori [[T9]],[[T9]],0xffff
-; MIPS32: and [[T4]],[[T4]],[[T9]]
-; MIPS32: or [[T8]],[[T8]],[[T4]]
-; MIPS32: srl [[T10:.*]],a0,0x18
-; MIPS32: srl [[T0]],[[T0]],0x18
-; MIPS32: sll [[T10]],[[T10]],0x18
-; MIPS32: sll [[T0]],[[T0]],0x18
-; MIPS32: xor [[T10]],[[T10]],[[T0]]
-; MIPS32: sltiu [[T10]],[[T10]],1
-; MIPS32: sll [[T10]],[[T10]],0x18
-; MIPS32: sll [[T8]],[[T8]],0x8
-; MIPS32: srl [[T8]],[[T8]],0x8
-; MIPS32: or [[T10]],[[T10]],[[T8]]
-; MIPS32: move [[T0]],a1
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: move [[T4]],[[T1]]
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: sll [[T0]],[[T0]],0x18
-; MIPS32: sll [[T4]],[[T4]],0x18
-; MIPS32: xor [[T0]],[[T0]],[[T4]]
-; MIPS32: sltiu [[T0]],[[T0]],1
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: srl [[T5]],[[T5]],0x8
-; MIPS32: sll [[T5]],[[T5]],0x8
-; MIPS32: or [[T0]],[[T0]],[[T5]]
-; MIPS32: move [[T4]],a1
-; MIPS32: srl [[T4]],[[T4]],0x8
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: move [[T5]],[[T1]]
-; MIPS32: srl [[T5]],[[T5]],0x8
-; MIPS32: andi [[T5]],[[T5]],0xff
-; MIPS32: sll [[T4]],[[T4]],0x18
-; MIPS32: sll [[T5]],[[T5]],0x18
-; MIPS32: xor [[T4]],[[T4]],[[T5]]
-; MIPS32: sltiu [[T4]],[[T4]],1
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: sll [[T4]],[[T4]],0x8
-; MIPS32: lui [[T5]],0xffff
-; MIPS32: ori [[T5]],[[T5]],0xff
-; MIPS32: and [[T0]],[[T0]],[[T5]]
-; MIPS32: or [[T4]],[[T4]],[[T0]]
-; MIPS32: move [[T0]],a1
-; MIPS32: srl [[T0]],[[T0]],0x10
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: move [[T5]],[[T1]]
-; MIPS32: srl [[T5]],[[T5]],0x10
-; MIPS32: andi [[T5]],[[T5]],0xff
-; MIPS32: sll [[T0]],[[T0]],0x18
-; MIPS32: sll [[T5]],[[T5]],0x18
-; MIPS32: xor [[T0]],[[T0]],[[T5]]
-; MIPS32: sltiu [[T0]],[[T0]],1
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: sll [[T0]],[[T0]],0x10
-; MIPS32: lui [[T5]],0xff00
-; MIPS32: ori [[T5]],[[T5]],0xffff
-; MIPS32: and [[T4]],[[T4]],[[T5]]
-; MIPS32: or [[T0]],[[T0]],[[T4]]
-; MIPS32: srl [[T11:.*]],a1,0x18
-; MIPS32: srl [[T1]],[[T1]],0x18
-; MIPS32: sll [[T11]],[[T11]],0x18
-; MIPS32: sll [[T1]],[[T1]],0x18
-; MIPS32: xor [[T11]],[[T11]],[[T1]]
-; MIPS32: sltiu [[T11]],[[T11]],1
-; MIPS32: sll [[T11]],[[T11]],0x18
-; MIPS32: sll [[T0]],[[T0]],0x8
-; MIPS32: srl [[T0]],[[T0]],0x8
-; MIPS32: or [[T11]],[[T11]],[[T0]]
-; MIPS32: move [[T0]],a2
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: move [[T1]],[[T2]]
-; MIPS32: andi [[T1]],[[T1]],0xff
-; MIPS32: sll [[T0]],[[T0]],0x18
-; MIPS32: sll [[T1]],[[T1]],0x18
-; MIPS32: xor [[T0]],[[T0]],[[T1]]
-; MIPS32: sltiu [[T0]],[[T0]],1
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: srl [[T6]],[[T6]],0x8
-; MIPS32: sll [[T6]],[[T6]],0x8
-; MIPS32: or [[T0]],[[T0]],[[T6]]
-; MIPS32: move [[T1]],a2
-; MIPS32: srl [[T1]],[[T1]],0x8
-; MIPS32: andi [[T1]],[[T1]],0xff
-; MIPS32: move [[T4]],[[T2]]
-; MIPS32: srl [[T4]],[[T4]],0x8
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: sll [[T1]],[[T1]],0x18
-; MIPS32: sll [[T4]],[[T4]],0x18
-; MIPS32: xor [[T1]],[[T1]],[[T4]]
-; MIPS32: sltiu [[T1]],[[T1]],1
-; MIPS32: andi [[T1]],[[T1]],0xff
-; MIPS32: sll [[T1]],[[T1]],0x8
-; MIPS32: lui [[T4]],0xffff
-; MIPS32: ori [[T4]],[[T4]],0xff
-; MIPS32: and [[T0]],[[T0]],[[T4]]
-; MIPS32: or [[T1]],[[T1]],[[T0]]
-; MIPS32: move [[T0]],a2
-; MIPS32: srl [[T0]],[[T0]],0x10
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: move [[T4]],[[T2]]
-; MIPS32: srl [[T4]],[[T4]],0x10
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: sll [[T0]],[[T0]],0x18
-; MIPS32: sll [[T4]],[[T4]],0x18
-; MIPS32: xor [[T0]],[[T0]],[[T4]]
-; MIPS32: sltiu [[T0]],[[T0]],1
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: sll [[T0]],[[T0]],0x10
-; MIPS32: lui [[T4]],0xff00
-; MIPS32: ori [[T4]],[[T4]],0xffff
-; MIPS32: and [[T1]],[[T1]],[[T4]]
-; MIPS32: or [[T0]],[[T0]],[[T1]]
-; MIPS32: srl [[T12:.*]],a2,0x18
-; MIPS32: srl [[T2]],[[T2]],0x18
-; MIPS32: sll [[T12]],[[T12]],0x18
-; MIPS32: sll [[T2]],[[T2]],0x18
-; MIPS32: xor [[T12]],[[T12]],[[T2]]
-; MIPS32: sltiu [[T12]],[[T12]],1
-; MIPS32: sll [[T12]],[[T12]],0x18
-; MIPS32: sll [[T0]],[[T0]],0x8
-; MIPS32: srl [[T0]],[[T0]],0x8
-; MIPS32: or [[T12]],[[T12]],[[T0]]
-; MIPS32: move [[T0]],a3
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: move [[T1]],[[T3]]
-; MIPS32: andi [[T1]],[[T1]],0xff
-; MIPS32: sll [[T0]],[[T0]],0x18
-; MIPS32: sll [[T1]],[[T1]],0x18
-; MIPS32: xor [[T0]],[[T0]],[[T1]]
-; MIPS32: sltiu [[T0]],[[T0]],1
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: srl [[T7]],[[T7]],0x8
-; MIPS32: sll [[T7]],[[T7]],0x8
-; MIPS32: or [[T0]],[[T0]],[[T7]]
-; MIPS32: move [[T1]],a3
-; MIPS32: srl [[T1]],[[T1]],0x8
-; MIPS32: andi [[T1]],[[T1]],0xff
-; MIPS32: move [[T2]],[[T3]]
-; MIPS32: srl [[T2]],[[T2]],0x8
-; MIPS32: andi [[T2]],[[T2]],0xff
-; MIPS32: sll [[T1]],[[T1]],0x18
-; MIPS32: sll [[T2]],[[T2]],0x18
-; MIPS32: xor [[T1]],[[T1]],[[T2]]
-; MIPS32: sltiu [[T1]],[[T1]],1
-; MIPS32: andi [[T1]],[[T1]],0xff
-; MIPS32: sll [[T1]],[[T1]],0x8
-; MIPS32: lui [[T2]],0xffff
-; MIPS32: ori [[T2]],[[T2]],0xff
-; MIPS32: and [[T0]],[[T0]],[[T2]]
-; MIPS32: or [[T1]],[[T1]],[[T0]]
-; MIPS32: move [[T0]],a3
-; MIPS32: srl [[T0]],[[T0]],0x10
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: move [[T2]],[[T3]]
-; MIPS32: srl [[T2]],[[T2]],0x10
-; MIPS32: andi [[T2]],[[T2]],0xff
-; MIPS32: sll [[T0]],[[T0]],0x18
-; MIPS32: sll [[T2]],[[T2]],0x18
-; MIPS32: xor [[T0]],[[T0]],[[T2]]
-; MIPS32: sltiu [[T0]],[[T0]],1
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: sll [[T0]],[[T0]],0x10
-; MIPS32: lui [[T2]],0xff00
-; MIPS32: ori [[T2]],[[T2]],0xffff
-; MIPS32: and [[T1]],[[T1]],[[T2]]
-; MIPS32: or [[T0]],[[T0]],[[T1]]
-; MIPS32: srl [[T13:.*]],a3,0x18
-; MIPS32: srl [[T3]],[[T3]],0x18
-; MIPS32: sll [[T13]],[[T13]],0x18
-; MIPS32: sll [[T3]],[[T3]],0x18
-; MIPS32: xor [[T13]],[[T13]],[[T3]]
-; MIPS32: sltiu [[T13]],[[T13]],1
-; MIPS32: sll [[T13]],[[T13]],0x18
-; MIPS32: sll [[T0]],[[T0]],0x8
-; MIPS32: srl [[T0]],[[T0]],0x8
-; MIPS32: or [[T13]],[[T13]],[[T0]]
-; MIPS32: move v0,[[T10]]
-; MIPS32: move v1,[[T11]]
-; MIPS32: move a0,[[T12]]
-; MIPS32: move a1,[[T13]]
-}
-
-define internal <16 x i1> @test_icmp_v16i8_ne(<16 x i8> %a, <16 x i8> %b) {
-entry:
- %res = icmp ne <16 x i8> %a, %b
- ret <16 x i1> %res
-; CHECK-LABEL: test_icmp_v16i8_ne
-; CHECK: pcmpeqb
-; CHECK: pxor
-
-; MIPS32-LABEL: test_icmp_v16i8_ne
-; MIPS32: lw [[T0:.*]],
-; MIPS32: lw [[T1:.*]],
-; MIPS32: lw [[T2:.*]],
-; MIPS32: lw [[T3:.*]],
-; MIPS32: move [[T4:.*]],zero
-; MIPS32: move [[T5:.*]],zero
-; MIPS32: move [[T6:.*]],zero
-; MIPS32: move [[T7:.*]],zero
-; MIPS32: move [[T8:.*]],a0
-; MIPS32: andi [[T8]],[[T8]],0xff
-; MIPS32: move [[T9:.*]],[[T0]]
-; MIPS32: andi [[T9]],[[T9]],0xff
-; MIPS32: sll [[T8]],[[T8]],0x18
-; MIPS32: sll [[T9]],[[T9]],0x18
-; MIPS32: xor [[T8]],[[T8]],[[T9]]
-; MIPS32: sltu [[T8]],zero,[[T8]]
-; MIPS32: andi [[T8]],[[T8]],0xff
-; MIPS32: srl [[T4]],[[T4]],0x8
-; MIPS32: sll [[T4]],[[T4]],0x8
-; MIPS32: or [[T8]],[[T8]],[[T4]]
-; MIPS32: move [[T4]],a0
-; MIPS32: srl [[T4]],[[T4]],0x8
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: move [[T9]],[[T0]]
-; MIPS32: srl [[T9]],[[T9]],0x8
-; MIPS32: andi [[T9]],[[T9]],0xff
-; MIPS32: sll [[T4]],[[T4]],0x18
-; MIPS32: sll [[T9]],[[T9]],0x18
-; MIPS32: xor [[T4]],[[T4]],[[T9]]
-; MIPS32: sltu [[T4]],zero,[[T4]]
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: sll [[T4]],[[T4]],0x8
-; MIPS32: lui [[T9]],0xffff
-; MIPS32: ori [[T9]],[[T9]],0xff
-; MIPS32: and [[T8]],[[T8]],[[T9]]
-; MIPS32: or [[T4]],[[T4]],[[T8]]
-; MIPS32: move [[T8]],a0
-; MIPS32: srl [[T8]],[[T8]],0x10
-; MIPS32: andi [[T8]],[[T8]],0xff
-; MIPS32: move [[T9]],[[T0]]
-; MIPS32: srl [[T9]],[[T9]],0x10
-; MIPS32: andi [[T9]],[[T9]],0xff
-; MIPS32: sll [[T8]],[[T8]],0x18
-; MIPS32: sll [[T9]],[[T9]],0x18
-; MIPS32: xor [[T8]],[[T8]],[[T9]]
-; MIPS32: sltu [[T8]],zero,[[T8]]
-; MIPS32: andi [[T8]],[[T8]],0xff
-; MIPS32: sll [[T8]],[[T8]],0x10
-; MIPS32: lui [[T9]],0xff00
-; MIPS32: ori [[T9]],[[T9]],0xffff
-; MIPS32: and [[T4]],[[T4]],[[T9]]
-; MIPS32: or [[T8]],[[T8]],[[T4]]
-; MIPS32: srl [[T10:.*]],a0,0x18
-; MIPS32: srl [[T0]],[[T0]],0x18
-; MIPS32: sll [[T10]],[[T10]],0x18
-; MIPS32: sll [[T0]],[[T0]],0x18
-; MIPS32: xor [[T10]],[[T10]],[[T0]]
-; MIPS32: sltu [[T10]],zero,[[T10]]
-; MIPS32: sll [[T10]],[[T10]],0x18
-; MIPS32: sll [[T8]],[[T8]],0x8
-; MIPS32: srl [[T8]],[[T8]],0x8
-; MIPS32: or [[T10]],[[T10]],[[T8]]
-; MIPS32: move [[T0]],a1
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: move [[T4]],[[T1]]
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: sll [[T0]],[[T0]],0x18
-; MIPS32: sll [[T4]],[[T4]],0x18
-; MIPS32: xor [[T0]],[[T0]],[[T4]]
-; MIPS32: sltu [[T0]],zero,[[T0]]
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: srl [[T5]],[[T5]],0x8
-; MIPS32: sll [[T5]],[[T5]],0x8
-; MIPS32: or [[T0]],[[T0]],[[T5]]
-; MIPS32: move [[T4]],a1
-; MIPS32: srl [[T4]],[[T4]],0x8
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: move [[T5]],[[T1]]
-; MIPS32: srl [[T5]],[[T5]],0x8
-; MIPS32: andi [[T5]],[[T5]],0xff
-; MIPS32: sll [[T4]],[[T4]],0x18
-; MIPS32: sll [[T5]],[[T5]],0x18
-; MIPS32: xor [[T4]],[[T4]],[[T5]]
-; MIPS32: sltu [[T4]],zero,[[T4]]
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: sll [[T4]],[[T4]],0x8
-; MIPS32: lui [[T5]],0xffff
-; MIPS32: ori [[T5]],[[T5]],0xff
-; MIPS32: and [[T0]],[[T0]],[[T5]]
-; MIPS32: or [[T4]],[[T4]],[[T0]]
-; MIPS32: move [[T0]],a1
-; MIPS32: srl [[T0]],[[T0]],0x10
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: move [[T5]],[[T1]]
-; MIPS32: srl [[T5]],[[T5]],0x10
-; MIPS32: andi [[T5]],[[T5]],0xff
-; MIPS32: sll [[T0]],[[T0]],0x18
-; MIPS32: sll [[T5]],[[T5]],0x18
-; MIPS32: xor [[T0]],[[T0]],[[T5]]
-; MIPS32: sltu [[T0]],zero,[[T0]]
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: sll [[T0]],[[T0]],0x10
-; MIPS32: lui [[T5]],0xff00
-; MIPS32: ori [[T5]],[[T5]],0xffff
-; MIPS32: and [[T4]],[[T4]],[[T5]]
-; MIPS32: or [[T0]],[[T0]],[[T4]]
-; MIPS32: srl [[T11:.*]],a1,0x18
-; MIPS32: srl [[T1]],[[T1]],0x18
-; MIPS32: sll [[T11]],[[T11]],0x18
-; MIPS32: sll [[T1]],[[T1]],0x18
-; MIPS32: xor [[T11]],[[T11]],[[T1]]
-; MIPS32: sltu [[T11]],zero,[[T11]]
-; MIPS32: sll [[T11]],[[T11]],0x18
-; MIPS32: sll [[T0]],[[T0]],0x8
-; MIPS32: srl [[T0]],[[T0]],0x8
-; MIPS32: or [[T11]],[[T11]],[[T0]]
-; MIPS32: move [[T0]],a2
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: move [[T1]],[[T2]]
-; MIPS32: andi [[T1]],[[T1]],0xff
-; MIPS32: sll [[T0]],[[T0]],0x18
-; MIPS32: sll [[T1]],[[T1]],0x18
-; MIPS32: xor [[T0]],[[T0]],[[T1]]
-; MIPS32: sltu [[T0]],zero,[[T0]]
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: srl [[T6]],[[T6]],0x8
-; MIPS32: sll [[T6]],[[T6]],0x8
-; MIPS32: or [[T0]],[[T0]],[[T6]]
-; MIPS32: move [[T1]],a2
-; MIPS32: srl [[T1]],[[T1]],0x8
-; MIPS32: andi [[T1]],[[T1]],0xff
-; MIPS32: move [[T4]],[[T2]]
-; MIPS32: srl [[T4]],[[T4]],0x8
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: sll [[T1]],[[T1]],0x18
-; MIPS32: sll [[T4]],[[T4]],0x18
-; MIPS32: xor [[T1]],[[T1]],[[T4]]
-; MIPS32: sltu [[T1]],zero,[[T1]]
-; MIPS32: andi [[T1]],[[T1]],0xff
-; MIPS32: sll [[T1]],[[T1]],0x8
-; MIPS32: lui [[T4]],0xffff
-; MIPS32: ori [[T4]],[[T4]],0xff
-; MIPS32: and [[T0]],[[T0]],[[T4]]
-; MIPS32: or [[T1]],[[T1]],[[T0]]
-; MIPS32: move [[T0]],a2
-; MIPS32: srl [[T0]],[[T0]],0x10
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: move [[T4]],[[T2]]
-; MIPS32: srl [[T4]],[[T4]],0x10
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: sll [[T0]],[[T0]],0x18
-; MIPS32: sll [[T4]],[[T4]],0x18
-; MIPS32: xor [[T0]],[[T0]],[[T4]]
-; MIPS32: sltu [[T0]],zero,[[T0]]
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: sll [[T0]],[[T0]],0x10
-; MIPS32: lui [[T4]],0xff00
-; MIPS32: ori [[T4]],[[T4]],0xffff
-; MIPS32: and [[T1]],[[T1]],[[T4]]
-; MIPS32: or [[T0]],[[T0]],[[T1]]
-; MIPS32: srl [[T12:.*]],a2,0x18
-; MIPS32: srl [[T2]],[[T2]],0x18
-; MIPS32: sll [[T12]],[[T12]],0x18
-; MIPS32: sll [[T2]],[[T2]],0x18
-; MIPS32: xor [[T12]],[[T12]],[[T2]]
-; MIPS32: sltu [[T12]],zero,[[T12]]
-; MIPS32: sll [[T12]],[[T12]],0x18
-; MIPS32: sll [[T0]],[[T0]],0x8
-; MIPS32: srl [[T0]],[[T0]],0x8
-; MIPS32: or [[T12]],[[T12]],[[T0]]
-; MIPS32: move [[T0]],a3
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: move [[T1]],[[T3]]
-; MIPS32: andi [[T1]],[[T1]],0xff
-; MIPS32: sll [[T0]],[[T0]],0x18
-; MIPS32: sll [[T1]],[[T1]],0x18
-; MIPS32: xor [[T0]],[[T0]],[[T1]]
-; MIPS32: sltu [[T0]],zero,[[T0]]
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: srl [[T7]],[[T7]],0x8
-; MIPS32: sll [[T7]],[[T7]],0x8
-; MIPS32: or [[T0]],[[T0]],[[T7]]
-; MIPS32: move [[T1]],a3
-; MIPS32: srl [[T1]],[[T1]],0x8
-; MIPS32: andi [[T1]],[[T1]],0xff
-; MIPS32: move [[T2]],[[T3]]
-; MIPS32: srl [[T2]],[[T2]],0x8
-; MIPS32: andi [[T2]],[[T2]],0xff
-; MIPS32: sll [[T1]],[[T1]],0x18
-; MIPS32: sll [[T2]],[[T2]],0x18
-; MIPS32: xor [[T1]],[[T1]],[[T2]]
-; MIPS32: sltu [[T1]],zero,[[T1]]
-; MIPS32: andi [[T1]],[[T1]],0xff
-; MIPS32: sll [[T1]],[[T1]],0x8
-; MIPS32: lui [[T2]],0xffff
-; MIPS32: ori [[T2]],[[T2]],0xff
-; MIPS32: and [[T0]],[[T0]],[[T2]]
-; MIPS32: or [[T1]],[[T1]],[[T0]]
-; MIPS32: move [[T0]],a3
-; MIPS32: srl [[T0]],[[T0]],0x10
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: move [[T2]],[[T3]]
-; MIPS32: srl [[T2]],[[T2]],0x10
-; MIPS32: andi [[T2]],[[T2]],0xff
-; MIPS32: sll [[T0]],[[T0]],0x18
-; MIPS32: sll [[T2]],[[T2]],0x18
-; MIPS32: xor [[T0]],[[T0]],[[T2]]
-; MIPS32: sltu [[T0]],zero,[[T0]]
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: sll [[T0]],[[T0]],0x10
-; MIPS32: lui [[T2]],0xff00
-; MIPS32: ori [[T2]],[[T2]],0xffff
-; MIPS32: and [[T1]],[[T1]],[[T2]]
-; MIPS32: or [[T0]],[[T0]],[[T1]]
-; MIPS32: srl [[T13:.*]],a3,0x18
-; MIPS32: srl [[T3]],[[T3]],0x18
-; MIPS32: sll [[T13]],[[T13]],0x18
-; MIPS32: sll [[T3]],[[T3]],0x18
-; MIPS32: xor [[T13]],[[T13]],[[T3]]
-; MIPS32: sltu [[T13]],zero,[[T13]]
-; MIPS32: sll [[T13]],[[T13]],0x18
-; MIPS32: sll [[T0]],[[T0]],0x8
-; MIPS32: srl [[T0]],[[T0]],0x8
-; MIPS32: or [[T13]],[[T13]],[[T0]]
-; MIPS32: move v0,[[T10]]
-; MIPS32: move v1,[[T11]]
-; MIPS32: move a0,[[T12]]
-; MIPS32: move a1,[[T13]]
-}
-
-define internal <16 x i1> @test_icmp_v16i8_sgt(<16 x i8> %a, <16 x i8> %b) {
-entry:
- %res = icmp sgt <16 x i8> %a, %b
- ret <16 x i1> %res
-; CHECK-LABEL: test_icmp_v16i8_sgt
-; CHECK: pcmpgtb
-
-; MIPS32-LABEL: test_icmp_v16i8_sgt
-; MIPS32: lw [[T0:.*]],
-; MIPS32: lw [[T1:.*]],
-; MIPS32: lw [[T2:.*]],
-; MIPS32: lw [[T3:.*]],
-; MIPS32: move [[T4:.*]],zero
-; MIPS32: move [[T5:.*]],zero
-; MIPS32: move [[T6:.*]],zero
-; MIPS32: move [[T7:.*]],zero
-; MIPS32: move [[T8:.*]],a0
-; MIPS32: andi [[T8]],[[T8]],0xff
-; MIPS32: move [[T9:.*]],[[T0]]
-; MIPS32: andi [[T9]],[[T9]],0xff
-; MIPS32: sll [[T8]],[[T8]],0x18
-; MIPS32: sll [[T9]],[[T9]],0x18
-; MIPS32: slt [[T9]],[[T9]],[[T8]]
-; MIPS32: andi [[T9]],[[T9]],0xff
-; MIPS32: srl [[T4]],[[T4]],0x8
-; MIPS32: sll [[T4]],[[T4]],0x8
-; MIPS32: or [[T9]],[[T9]],[[T4]]
-; MIPS32: move [[T4]],a0
-; MIPS32: srl [[T4]],[[T4]],0x8
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: move [[T8]],[[T0]]
-; MIPS32: srl [[T8]],[[T8]],0x8
-; MIPS32: andi [[T8]],[[T8]],0xff
-; MIPS32: sll [[T4]],[[T4]],0x18
-; MIPS32: sll [[T8]],[[T8]],0x18
-; MIPS32: slt [[T8]],[[T8]],[[T4]]
-; MIPS32: andi [[T8]],[[T8]],0xff
-; MIPS32: sll [[T8]],[[T8]],0x8
-; MIPS32: lui [[T4]],0xffff
-; MIPS32: ori [[T4]],[[T4]],0xff
-; MIPS32: and [[T9]],[[T9]],[[T4]]
-; MIPS32: or [[T8]],[[T8]],[[T9]]
-; MIPS32: move [[T4]],a0
-; MIPS32: srl [[T4]],[[T4]],0x10
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: move [[T9]],[[T0]]
-; MIPS32: srl [[T9]],[[T9]],0x10
-; MIPS32: andi [[T9]],[[T9]],0xff
-; MIPS32: sll [[T4]],[[T4]],0x18
-; MIPS32: sll [[T9]],[[T9]],0x18
-; MIPS32: slt [[T9]],[[T9]],[[T4]]
-; MIPS32: andi [[T9]],[[T9]],0xff
-; MIPS32: sll [[T9]],[[T9]],0x10
-; MIPS32: lui [[T4]],0xff00
-; MIPS32: ori [[T4]],[[T4]],0xffff
-; MIPS32: and [[T8]],[[T8]],[[T4]]
-; MIPS32: or [[T9]],[[T9]],[[T8]]
-; MIPS32: srl [[T10:.*]],a0,0x18
-; MIPS32: srl [[T0]],[[T0]],0x18
-; MIPS32: sll [[T10]],[[T10]],0x18
-; MIPS32: sll [[T0]],[[T0]],0x18
-; MIPS32: slt [[T0]],[[T0]],[[T10]]
-; MIPS32: sll [[T0]],[[T0]],0x18
-; MIPS32: sll [[T9]],[[T9]],0x8
-; MIPS32: srl [[T9]],[[T9]],0x8
-; MIPS32: or v0,[[T0]],[[T9]]
-; MIPS32: move [[T10]],a1
-; MIPS32: andi [[T10]],[[T10]],0xff
-; MIPS32: move [[T4]],[[T1]]
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: sll [[T10]],[[T10]],0x18
-; MIPS32: sll [[T4]],[[T4]],0x18
-; MIPS32: slt [[T4]],[[T4]],[[T10]]
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: srl [[T5]],[[T5]],0x8
-; MIPS32: sll [[T5]],[[T5]],0x8
-; MIPS32: or [[T4]],[[T4]],[[T5]]
-; MIPS32: move [[T10]],a1
-; MIPS32: srl [[T10]],[[T10]],0x8
-; MIPS32: andi [[T10]],[[T10]],0xff
-; MIPS32: move [[T5]],[[T1]]
-; MIPS32: srl [[T5]],[[T5]],0x8
-; MIPS32: andi [[T5]],[[T5]],0xff
-; MIPS32: sll [[T10]],[[T10]],0x18
-; MIPS32: sll [[T5]],[[T5]],0x18
-; MIPS32: slt [[T5]],[[T5]],[[T10]]
-; MIPS32: andi [[T5]],[[T5]],0xff
-; MIPS32: sll [[T5]],[[T5]],0x8
-; MIPS32: lui [[T10]],0xffff
-; MIPS32: ori [[T10]],[[T10]],0xff
-; MIPS32: and [[T4]],[[T4]],[[T10]]
-; MIPS32: or [[T5]],[[T5]],[[T4]]
-; MIPS32: move [[T10]],a1
-; MIPS32: srl [[T10]],[[T10]],0x10
-; MIPS32: andi [[T10]],[[T10]],0xff
-; MIPS32: move [[T4]],[[T1]]
-; MIPS32: srl [[T4]],[[T4]],0x10
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: sll [[T10]],[[T10]],0x18
-; MIPS32: sll [[T4]],[[T4]],0x18
-; MIPS32: slt [[T4]],[[T4]],[[T10]]
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: sll [[T4]],[[T4]],0x10
-; MIPS32: lui [[T10]],0xff00
-; MIPS32: ori [[T10]],[[T10]],0xffff
-; MIPS32: and [[T5]],[[T5]],[[T10]]
-; MIPS32: or [[T4]],[[T4]],[[T5]]
-; MIPS32: srl [[T11:.*]],a1,0x18
-; MIPS32: srl [[T1]],[[T1]],0x18
-; MIPS32: sll [[T11]],[[T11]],0x18
-; MIPS32: sll [[T1]],[[T1]],0x18
-; MIPS32: slt [[T1]],[[T1]],[[T11]]
-; MIPS32: sll [[T1]],[[T1]],0x18
-; MIPS32: sll [[T4]],[[T4]],0x8
-; MIPS32: srl [[T4]],[[T4]],0x8
-; MIPS32: or v1,[[T1]],[[T4]]
-; MIPS32: move [[T10]],a2
-; MIPS32: andi [[T10]],[[T10]],0xff
-; MIPS32: move [[T11]],[[T2]]
-; MIPS32: andi [[T11]],[[T11]],0xff
-; MIPS32: sll [[T10]],[[T10]],0x18
-; MIPS32: sll [[T11]],[[T11]],0x18
-; MIPS32: slt [[T11]],[[T11]],[[T10]]
-; MIPS32: andi [[T11]],[[T11]],0xff
-; MIPS32: srl [[T6]],[[T6]],0x8
-; MIPS32: sll [[T6]],[[T6]],0x8
-; MIPS32: or [[T11]],[[T11]],[[T6]]
-; MIPS32: move [[T10]],a2
-; MIPS32: srl [[T10]],[[T10]],0x8
-; MIPS32: andi [[T10]],[[T10]],0xff
-; MIPS32: move [[T4]],[[T2]]
-; MIPS32: srl [[T4]],[[T4]],0x8
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: sll [[T10]],[[T10]],0x18
-; MIPS32: sll [[T4]],[[T4]],0x18
-; MIPS32: slt [[T4]],[[T4]],[[T10]]
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: sll [[T4]],[[T4]],0x8
-; MIPS32: lui [[T10]],0xffff
-; MIPS32: ori [[T10]],[[T10]],0xff
-; MIPS32: and [[T11]],[[T11]],[[T10]]
-; MIPS32: or [[T4]],[[T4]],[[T11]]
-; MIPS32: move [[T10]],a2
-; MIPS32: srl [[T10]],[[T10]],0x10
-; MIPS32: andi [[T10]],[[T10]],0xff
-; MIPS32: move [[T11]],[[T2]]
-; MIPS32: srl [[T11]],[[T11]],0x10
-; MIPS32: andi [[T11]],[[T11]],0xff
-; MIPS32: sll [[T10]],[[T10]],0x18
-; MIPS32: sll [[T11]],[[T11]],0x18
-; MIPS32: slt [[T11]],[[T11]],[[T10]]
-; MIPS32: andi [[T11]],[[T11]],0xff
-; MIPS32: sll [[T11]],[[T11]],0x10
-; MIPS32: lui [[T10]],0xff00
-; MIPS32: ori [[T10]],[[T10]],0xffff
-; MIPS32: and [[T4]],[[T4]],[[T10]]
-; MIPS32: or [[T11]],[[T11]],[[T4]]
-; MIPS32: srl [[T12:.*]],a2,0x18
-; MIPS32: srl [[T2]],[[T2]],0x18
-; MIPS32: sll [[T12]],[[T12]],0x18
-; MIPS32: sll [[T2]],[[T2]],0x18
-; MIPS32: slt [[T2]],[[T2]],[[T12]]
-; MIPS32: sll [[T2]],[[T2]],0x18
-; MIPS32: sll [[T11]],[[T11]],0x8
-; MIPS32: srl [[T11]],[[T11]],0x8
-; MIPS32: or [[T2]],[[T2]],[[T11]]
-; MIPS32: move [[T10]],a3
-; MIPS32: andi [[T10]],[[T10]],0xff
-; MIPS32: move [[T11]],[[T3]]
-; MIPS32: andi [[T11]],[[T11]],0xff
-; MIPS32: sll [[T10]],[[T10]],0x18
-; MIPS32: sll [[T11]],[[T11]],0x18
-; MIPS32: slt [[T11]],[[T11]],[[T10]]
-; MIPS32: andi [[T11]],[[T11]],0xff
-; MIPS32: srl [[T7]],[[T7]],0x8
-; MIPS32: sll [[T7]],[[T7]],0x8
-; MIPS32: or [[T11]],[[T11]],[[T7]]
-; MIPS32: move [[T10]],a3
-; MIPS32: srl [[T10]],[[T10]],0x8
-; MIPS32: andi [[T10]],[[T10]],0xff
-; MIPS32: move [[T12]],[[T3]]
-; MIPS32: srl [[T12]],[[T12]],0x8
-; MIPS32: andi [[T12]],[[T12]],0xff
-; MIPS32: sll [[T10]],[[T10]],0x18
-; MIPS32: sll [[T12]],[[T12]],0x18
-; MIPS32: slt [[T12]],[[T12]],[[T10]]
-; MIPS32: andi [[T12]],[[T12]],0xff
-; MIPS32: sll [[T12]],[[T12]],0x8
-; MIPS32: lui [[T10]],0xffff
-; MIPS32: ori [[T10]],[[T10]],0xff
-; MIPS32: and [[T11]],[[T11]],[[T10]]
-; MIPS32: or [[T12]],[[T12]],[[T11]]
-; MIPS32: move [[T10]],a3
-; MIPS32: srl [[T10]],[[T10]],0x10
-; MIPS32: andi [[T10]],[[T10]],0xff
-; MIPS32: move [[T11]],[[T3]]
-; MIPS32: srl [[T11]],[[T11]],0x10
-; MIPS32: andi [[T11]],[[T11]],0xff
-; MIPS32: sll [[T10]],[[T10]],0x18
-; MIPS32: sll [[T11]],[[T11]],0x18
-; MIPS32: slt [[T11]],[[T11]],[[T10]]
-; MIPS32: andi [[T11]],[[T11]],0xff
-; MIPS32: sll [[T11]],[[T11]],0x10
-; MIPS32: lui [[T10]],0xff00
-; MIPS32: ori [[T10]],[[T10]],0xffff
-; MIPS32: and [[T12]],[[T12]],[[T10]]
-; MIPS32: or [[T11]],[[T11]],[[T12]]
-; MIPS32: srl [[T13:.*]],a3,0x18
-; MIPS32: srl [[T3]],[[T3]],0x18
-; MIPS32: sll [[T13]],[[T13]],0x18
-; MIPS32: sll [[T3]],[[T3]],0x18
-; MIPS32: slt [[T3]],[[T3]],[[T13]]
-; MIPS32: sll [[T3]],[[T3]],0x18
-; MIPS32: sll [[T11]],[[T11]],0x8
-; MIPS32: srl [[T11]],[[T11]],0x8
-; MIPS32: or [[T3]],[[T3]],[[T11]]
-; MIPS32: move a0,[[T2]]
-; MIPS32: move a1,[[T3]]
-}
-
-define internal <16 x i1> @test_icmp_v16i8_sle(<16 x i8> %a, <16 x i8> %b) {
-entry:
- %res = icmp sle <16 x i8> %a, %b
- ret <16 x i1> %res
-; CHECK-LABEL: test_icmp_v16i8_sle
-; CHECK: pcmpgtb
-; CHECK: pxor
-
-; MIPS32-LABEL: test_icmp_v16i8_sle
-; MIPS32: lw [[T0:.*]],
-; MIPS32: lw [[T1:.*]],
-; MIPS32: lw [[T2:.*]],
-; MIPS32: lw [[T3:.*]],
-; MIPS32: move [[T4:.*]],zero
-; MIPS32: move [[T5:.*]],zero
-; MIPS32: move [[T6:.*]],zero
-; MIPS32: move [[T7:.*]],zero
-; MIPS32: move [[T8:.*]],a0
-; MIPS32: andi [[T8]],[[T8]],0xff
-; MIPS32: move [[T9:.*]],[[T0]]
-; MIPS32: andi [[T9]],[[T9]],0xff
-; MIPS32: sll [[T8]],[[T8]],0x18
-; MIPS32: sll [[T9]],[[T9]],0x18
-; MIPS32: slt [[T9]],[[T9]],[[T8]]
-; MIPS32: xori [[T9]],[[T9]],0x1
-; MIPS32: andi [[T9]],[[T9]],0xff
-; MIPS32: srl [[T4]],[[T4]],0x8
-; MIPS32: sll [[T4]],[[T4]],0x8
-; MIPS32: or [[T9]],[[T9]],[[T4]]
-; MIPS32: move [[T4]],a0
-; MIPS32: srl [[T4]],[[T4]],0x8
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: move [[T8]],[[T0]]
-; MIPS32: srl [[T8]],[[T8]],0x8
-; MIPS32: andi [[T8]],[[T8]],0xff
-; MIPS32: sll [[T4]],[[T4]],0x18
-; MIPS32: sll [[T8]],[[T8]],0x18
-; MIPS32: slt [[T8]],[[T8]],[[T4]]
-; MIPS32: xori [[T8]],[[T8]],0x1
-; MIPS32: andi [[T8]],[[T8]],0xff
-; MIPS32: sll [[T8]],[[T8]],0x8
-; MIPS32: lui [[T4]],0xffff
-; MIPS32: ori [[T4]],[[T4]],0xff
-; MIPS32: and [[T9]],[[T9]],[[T4]]
-; MIPS32: or [[T8]],[[T8]],[[T9]]
-; MIPS32: move [[T4]],a0
-; MIPS32: srl [[T4]],[[T4]],0x10
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: move [[T9]],[[T0]]
-; MIPS32: srl [[T9]],[[T9]],0x10
-; MIPS32: andi [[T9]],[[T9]],0xff
-; MIPS32: sll [[T4]],[[T4]],0x18
-; MIPS32: sll [[T9]],[[T9]],0x18
-; MIPS32: slt [[T9]],[[T9]],[[T4]]
-; MIPS32: xori [[T9]],[[T9]],0x1
-; MIPS32: andi [[T9]],[[T9]],0xff
-; MIPS32: sll [[T9]],[[T9]],0x10
-; MIPS32: lui [[T4]],0xff00
-; MIPS32: ori [[T4]],[[T4]],0xffff
-; MIPS32: and [[T8]],[[T8]],[[T4]]
-; MIPS32: or [[T9]],[[T9]],[[T8]]
-; MIPS32: srl [[T10:.*]],a0,0x18
-; MIPS32: srl [[T0]],[[T0]],0x18
-; MIPS32: sll [[T10]],[[T10]],0x18
-; MIPS32: sll [[T0]],[[T0]],0x18
-; MIPS32: slt [[T0]],[[T0]],[[T10]]
-; MIPS32: xori [[T0]],[[T0]],0x1
-; MIPS32: sll [[T0]],[[T0]],0x18
-; MIPS32: sll [[T9]],[[T9]],0x8
-; MIPS32: srl [[T9]],[[T9]],0x8
-; MIPS32: or v0,[[T0]],[[T9]]
-; MIPS32: move [[T10]],a1
-; MIPS32: andi [[T10]],[[T10]],0xff
-; MIPS32: move [[T4]],[[T1]]
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: sll [[T10]],[[T10]],0x18
-; MIPS32: sll [[T4]],[[T4]],0x18
-; MIPS32: slt [[T4]],[[T4]],[[T10]]
-; MIPS32: xori [[T4]],[[T4]],0x1
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: srl [[T5]],[[T5]],0x8
-; MIPS32: sll [[T5]],[[T5]],0x8
-; MIPS32: or [[T4]],[[T4]],[[T5]]
-; MIPS32: move [[T10]],a1
-; MIPS32: srl [[T10]],[[T10]],0x8
-; MIPS32: andi [[T10]],[[T10]],0xff
-; MIPS32: move [[T5]],[[T1]]
-; MIPS32: srl [[T5]],[[T5]],0x8
-; MIPS32: andi [[T5]],[[T5]],0xff
-; MIPS32: sll [[T10]],[[T10]],0x18
-; MIPS32: sll [[T5]],[[T5]],0x18
-; MIPS32: slt [[T5]],[[T5]],[[T10]]
-; MIPS32: xori [[T5]],[[T5]],0x1
-; MIPS32: andi [[T5]],[[T5]],0xff
-; MIPS32: sll [[T5]],[[T5]],0x8
-; MIPS32: lui [[T10]],0xffff
-; MIPS32: ori [[T10]],[[T10]],0xff
-; MIPS32: and [[T4]],[[T4]],[[T10]]
-; MIPS32: or [[T5]],[[T5]],[[T4]]
-; MIPS32: move [[T10]],a1
-; MIPS32: srl [[T10]],[[T10]],0x10
-; MIPS32: andi [[T10]],[[T10]],0xff
-; MIPS32: move [[T4]],[[T1]]
-; MIPS32: srl [[T4]],[[T4]],0x10
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: sll [[T10]],[[T10]],0x18
-; MIPS32: sll [[T4]],[[T4]],0x18
-; MIPS32: slt [[T4]],[[T4]],[[T10]]
-; MIPS32: xori [[T4]],[[T4]],0x1
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: sll [[T4]],[[T4]],0x10
-; MIPS32: lui [[T10]],0xff00
-; MIPS32: ori [[T10]],[[T10]],0xffff
-; MIPS32: and [[T5]],[[T5]],[[T10]]
-; MIPS32: or [[T4]],[[T4]],[[T5]]
-; MIPS32: srl [[T11:.*]],a1,0x18
-; MIPS32: srl [[T1]],[[T1]],0x18
-; MIPS32: sll [[T11]],[[T11]],0x18
-; MIPS32: sll [[T1]],[[T1]],0x18
-; MIPS32: slt [[T1]],[[T1]],[[T11]]
-; MIPS32: xori [[T1]],[[T1]],0x1
-; MIPS32: sll [[T1]],[[T1]],0x18
-; MIPS32: sll [[T4]],[[T4]],0x8
-; MIPS32: srl [[T4]],[[T4]],0x8
-; MIPS32: or v1,[[T1]],[[T4]]
-; MIPS32: move [[T10]],a2
-; MIPS32: andi [[T10]],[[T10]],0xff
-; MIPS32: move [[T11]],[[T2]]
-; MIPS32: andi [[T11]],[[T11]],0xff
-; MIPS32: sll [[T10]],[[T10]],0x18
-; MIPS32: sll [[T11]],[[T11]],0x18
-; MIPS32: slt [[T11]],[[T11]],[[T10]]
-; MIPS32: xori [[T11]],[[T11]],0x1
-; MIPS32: andi [[T11]],[[T11]],0xff
-; MIPS32: srl [[T6]],[[T6]],0x8
-; MIPS32: sll [[T6]],[[T6]],0x8
-; MIPS32: or [[T11]],[[T11]],[[T6]]
-; MIPS32: move [[T10]],a2
-; MIPS32: srl [[T10]],[[T10]],0x8
-; MIPS32: andi [[T10]],[[T10]],0xff
-; MIPS32: move [[T4]],[[T2]]
-; MIPS32: srl [[T4]],[[T4]],0x8
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: sll [[T10]],[[T10]],0x18
-; MIPS32: sll [[T4]],[[T4]],0x18
-; MIPS32: slt [[T4]],[[T4]],[[T10]]
-; MIPS32: xori [[T4]],[[T4]],0x1
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: sll [[T4]],[[T4]],0x8
-; MIPS32: lui [[T10]],0xffff
-; MIPS32: ori [[T10]],[[T10]],0xff
-; MIPS32: and [[T11]],[[T11]],[[T10]]
-; MIPS32: or [[T4]],[[T4]],[[T11]]
-; MIPS32: move [[T10]],a2
-; MIPS32: srl [[T10]],[[T10]],0x10
-; MIPS32: andi [[T10]],[[T10]],0xff
-; MIPS32: move [[T11]],[[T2]]
-; MIPS32: srl [[T11]],[[T11]],0x10
-; MIPS32: andi [[T11]],[[T11]],0xff
-; MIPS32: sll [[T10]],[[T10]],0x18
-; MIPS32: sll [[T11]],[[T11]],0x18
-; MIPS32: slt [[T11]],[[T11]],[[T10]]
-; MIPS32: xori [[T11]],[[T11]],0x1
-; MIPS32: andi [[T11]],[[T11]],0xff
-; MIPS32: sll [[T11]],[[T11]],0x10
-; MIPS32: lui [[T10]],0xff00
-; MIPS32: ori [[T10]],[[T10]],0xffff
-; MIPS32: and [[T4]],[[T4]],[[T10]]
-; MIPS32: or [[T11]],[[T11]],[[T4]]
-; MIPS32: srl [[T12:.*]],a2,0x18
-; MIPS32: srl [[T2]],[[T2]],0x18
-; MIPS32: sll [[T12]],[[T12]],0x18
-; MIPS32: sll [[T2]],[[T2]],0x18
-; MIPS32: slt [[T2]],[[T2]],[[T12]]
-; MIPS32: xori [[T2]],[[T2]],0x1
-; MIPS32: sll [[T2]],[[T2]],0x18
-; MIPS32: sll [[T11]],[[T11]],0x8
-; MIPS32: srl [[T11]],[[T11]],0x8
-; MIPS32: or [[T2]],[[T2]],[[T11]]
-; MIPS32: move [[T10]],a3
-; MIPS32: andi [[T10]],[[T10]],0xff
-; MIPS32: move [[T11]],[[T3]]
-; MIPS32: andi [[T11]],[[T11]],0xff
-; MIPS32: sll [[T10]],[[T10]],0x18
-; MIPS32: sll [[T11]],[[T11]],0x18
-; MIPS32: slt [[T11]],[[T11]],[[T10]]
-; MIPS32: xori [[T11]],[[T11]],0x1
-; MIPS32: andi [[T11]],[[T11]],0xff
-; MIPS32: srl [[T7]],[[T7]],0x8
-; MIPS32: sll [[T7]],[[T7]],0x8
-; MIPS32: or [[T11]],[[T11]],[[T7]]
-; MIPS32: move [[T10]],a3
-; MIPS32: srl [[T10]],[[T10]],0x8
-; MIPS32: andi [[T10]],[[T10]],0xff
-; MIPS32: move [[T12]],[[T3]]
-; MIPS32: srl [[T12]],[[T12]],0x8
-; MIPS32: andi [[T12]],[[T12]],0xff
-; MIPS32: sll [[T10]],[[T10]],0x18
-; MIPS32: sll [[T12]],[[T12]],0x18
-; MIPS32: slt [[T12]],[[T12]],[[T10]]
-; MIPS32: xori [[T12]],[[T12]],0x1
-; MIPS32: andi [[T12]],[[T12]],0xff
-; MIPS32: sll [[T12]],[[T12]],0x8
-; MIPS32: lui [[T10]],0xffff
-; MIPS32: ori [[T10]],[[T10]],0xff
-; MIPS32: and [[T11]],[[T11]],[[T10]]
-; MIPS32: or [[T12]],[[T12]],[[T11]]
-; MIPS32: move [[T10]],a3
-; MIPS32: srl [[T10]],[[T10]],0x10
-; MIPS32: andi [[T10]],[[T10]],0xff
-; MIPS32: move [[T11]],[[T3]]
-; MIPS32: srl [[T11]],[[T11]],0x10
-; MIPS32: andi [[T11]],[[T11]],0xff
-; MIPS32: sll [[T10]],[[T10]],0x18
-; MIPS32: sll [[T11]],[[T11]],0x18
-; MIPS32: slt [[T11]],[[T11]],[[T10]]
-; MIPS32: xori [[T11]],[[T11]],0x1
-; MIPS32: andi [[T11]],[[T11]],0xff
-; MIPS32: sll [[T11]],[[T11]],0x10
-; MIPS32: lui [[T10]],0xff00
-; MIPS32: ori [[T10]],[[T10]],0xffff
-; MIPS32: and [[T12]],[[T12]],[[T10]]
-; MIPS32: or [[T11]],[[T11]],[[T12]]
-; MIPS32: srl [[T13:.*]],a3,0x18
-; MIPS32: srl [[T3]],[[T3]],0x18
-; MIPS32: sll [[T13]],[[T13]],0x18
-; MIPS32: sll [[T3]],[[T3]],0x18
-; MIPS32: slt [[T3]],[[T3]],[[T13]]
-; MIPS32: xori [[T3]],[[T3]],0x1
-; MIPS32: sll [[T3]],[[T3]],0x18
-; MIPS32: sll [[T11]],[[T11]],0x8
-; MIPS32: srl [[T11]],[[T11]],0x8
-; MIPS32: or [[T3]],[[T3]],[[T11]]
-; MIPS32: move a0,[[T2]]
-; MIPS32: move a1,[[T3]]
-}
-
-define internal <16 x i1> @test_icmp_v16i8_slt(<16 x i8> %a, <16 x i8> %b) {
-entry:
- %res = icmp slt <16 x i8> %a, %b
- ret <16 x i1> %res
-; CHECK-LABEL: test_icmp_v16i8_slt
-; CHECK: pcmpgtb
-
-; MIPS32-LABEL: test_icmp_v16i8_slt
-; MIPS32: lw [[T0:.*]],
-; MIPS32: lw [[T1:.*]],
-; MIPS32: lw [[T2:.*]],
-; MIPS32: lw [[T3:.*]],
-; MIPS32: move [[T4:.*]],zero
-; MIPS32: move [[T5:.*]],zero
-; MIPS32: move [[T6:.*]],zero
-; MIPS32: move [[T7:.*]],zero
-; MIPS32: move [[T8:.*]],a0
-; MIPS32: andi [[T8]],[[T8]],0xff
-; MIPS32: move [[T9:.*]],[[T0]]
-; MIPS32: andi [[T9]],[[T9]],0xff
-; MIPS32: sll [[T8]],[[T8]],0x18
-; MIPS32: sll [[T9]],[[T9]],0x18
-; MIPS32: slt [[T8]],[[T8]],[[T9]]
-; MIPS32: andi [[T8]],[[T8]],0xff
-; MIPS32: srl [[T4]],[[T4]],0x8
-; MIPS32: sll [[T4]],[[T4]],0x8
-; MIPS32: or [[T8]],[[T8]],[[T4]]
-; MIPS32: move [[T4]],a0
-; MIPS32: srl [[T4]],[[T4]],0x8
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: move [[T9]],[[T0]]
-; MIPS32: srl [[T9]],[[T9]],0x8
-; MIPS32: andi [[T9]],[[T9]],0xff
-; MIPS32: sll [[T4]],[[T4]],0x18
-; MIPS32: sll [[T9]],[[T9]],0x18
-; MIPS32: slt [[T4]],[[T4]],[[T9]]
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: sll [[T4]],[[T4]],0x8
-; MIPS32: lui [[T9]],0xffff
-; MIPS32: ori [[T9]],[[T9]],0xff
-; MIPS32: and [[T8]],[[T8]],[[T9]]
-; MIPS32: or [[T4]],[[T4]],[[T8]]
-; MIPS32: move [[T8]],a0
-; MIPS32: srl [[T8]],[[T8]],0x10
-; MIPS32: andi [[T8]],[[T8]],0xff
-; MIPS32: move [[T9]],[[T0]]
-; MIPS32: srl [[T9]],[[T9]],0x10
-; MIPS32: andi [[T9]],[[T9]],0xff
-; MIPS32: sll [[T8]],[[T8]],0x18
-; MIPS32: sll [[T9]],[[T9]],0x18
-; MIPS32: slt [[T8]],[[T8]],[[T9]]
-; MIPS32: andi [[T8]],[[T8]],0xff
-; MIPS32: sll [[T8]],[[T8]],0x10
-; MIPS32: lui [[T9]],0xff00
-; MIPS32: ori [[T9]],[[T9]],0xffff
-; MIPS32: and [[T4]],[[T4]],[[T9]]
-; MIPS32: or [[T8]],[[T8]],[[T4]]
-; MIPS32: srl [[T10:.*]],a0,0x18
-; MIPS32: srl [[T0]],[[T0]],0x18
-; MIPS32: sll [[T10]],[[T10]],0x18
-; MIPS32: sll [[T0]],[[T0]],0x18
-; MIPS32: slt [[T10]],[[T10]],[[T0]]
-; MIPS32: sll [[T10]],[[T10]],0x18
-; MIPS32: sll [[T8]],[[T8]],0x8
-; MIPS32: srl [[T8]],[[T8]],0x8
-; MIPS32: or [[T10]],[[T10]],[[T8]]
-; MIPS32: move [[T0]],a1
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: move [[T4]],[[T1]]
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: sll [[T0]],[[T0]],0x18
-; MIPS32: sll [[T4]],[[T4]],0x18
-; MIPS32: slt [[T0]],[[T0]],[[T4]]
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: srl [[T5]],[[T5]],0x8
-; MIPS32: sll [[T5]],[[T5]],0x8
-; MIPS32: or [[T0]],[[T0]],[[T5]]
-; MIPS32: move [[T4]],a1
-; MIPS32: srl [[T4]],[[T4]],0x8
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: move [[T5]],[[T1]]
-; MIPS32: srl [[T5]],[[T5]],0x8
-; MIPS32: andi [[T5]],[[T5]],0xff
-; MIPS32: sll [[T4]],[[T4]],0x18
-; MIPS32: sll [[T5]],[[T5]],0x18
-; MIPS32: slt [[T4]],[[T4]],[[T5]]
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: sll [[T4]],[[T4]],0x8
-; MIPS32: lui [[T5]],0xffff
-; MIPS32: ori [[T5]],[[T5]],0xff
-; MIPS32: and [[T0]],[[T0]],[[T5]]
-; MIPS32: or [[T4]],[[T4]],[[T0]]
-; MIPS32: move [[T0]],a1
-; MIPS32: srl [[T0]],[[T0]],0x10
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: move [[T5]],[[T1]]
-; MIPS32: srl [[T5]],[[T5]],0x10
-; MIPS32: andi [[T5]],[[T5]],0xff
-; MIPS32: sll [[T0]],[[T0]],0x18
-; MIPS32: sll [[T5]],[[T5]],0x18
-; MIPS32: slt [[T0]],[[T0]],[[T5]]
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: sll [[T0]],[[T0]],0x10
-; MIPS32: lui [[T5]],0xff00
-; MIPS32: ori [[T5]],[[T5]],0xffff
-; MIPS32: and [[T4]],[[T4]],[[T5]]
-; MIPS32: or [[T0]],[[T0]],[[T4]]
-; MIPS32: srl [[T11:.*]],a1,0x18
-; MIPS32: srl [[T1]],[[T1]],0x18
-; MIPS32: sll [[T11]],[[T11]],0x18
-; MIPS32: sll [[T1]],[[T1]],0x18
-; MIPS32: slt [[T11]],[[T11]],[[T1]]
-; MIPS32: sll [[T11]],[[T11]],0x18
-; MIPS32: sll [[T0]],[[T0]],0x8
-; MIPS32: srl [[T0]],[[T0]],0x8
-; MIPS32: or [[T11]],[[T11]],[[T0]]
-; MIPS32: move [[T0]],a2
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: move [[T1]],[[T2]]
-; MIPS32: andi [[T1]],[[T1]],0xff
-; MIPS32: sll [[T0]],[[T0]],0x18
-; MIPS32: sll [[T1]],[[T1]],0x18
-; MIPS32: slt [[T0]],[[T0]],[[T1]]
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: srl [[T6]],[[T6]],0x8
-; MIPS32: sll [[T6]],[[T6]],0x8
-; MIPS32: or [[T0]],[[T0]],[[T6]]
-; MIPS32: move [[T1]],a2
-; MIPS32: srl [[T1]],[[T1]],0x8
-; MIPS32: andi [[T1]],[[T1]],0xff
-; MIPS32: move [[T4]],[[T2]]
-; MIPS32: srl [[T4]],[[T4]],0x8
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: sll [[T1]],[[T1]],0x18
-; MIPS32: sll [[T4]],[[T4]],0x18
-; MIPS32: slt [[T1]],[[T1]],[[T4]]
-; MIPS32: andi [[T1]],[[T1]],0xff
-; MIPS32: sll [[T1]],[[T1]],0x8
-; MIPS32: lui [[T4]],0xffff
-; MIPS32: ori [[T4]],[[T4]],0xff
-; MIPS32: and [[T0]],[[T0]],[[T4]]
-; MIPS32: or [[T1]],[[T1]],[[T0]]
-; MIPS32: move [[T0]],a2
-; MIPS32: srl [[T0]],[[T0]],0x10
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: move [[T4]],[[T2]]
-; MIPS32: srl [[T4]],[[T4]],0x10
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: sll [[T0]],[[T0]],0x18
-; MIPS32: sll [[T4]],[[T4]],0x18
-; MIPS32: slt [[T0]],[[T0]],[[T4]]
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: sll [[T0]],[[T0]],0x10
-; MIPS32: lui [[T4]],0xff00
-; MIPS32: ori [[T4]],[[T4]],0xffff
-; MIPS32: and [[T1]],[[T1]],[[T4]]
-; MIPS32: or [[T0]],[[T0]],[[T1]]
-; MIPS32: srl [[T12:.*]],a2,0x18
-; MIPS32: srl [[T2]],[[T2]],0x18
-; MIPS32: sll [[T12]],[[T12]],0x18
-; MIPS32: sll [[T2]],[[T2]],0x18
-; MIPS32: slt [[T12]],[[T12]],[[T2]]
-; MIPS32: sll [[T12]],[[T12]],0x18
-; MIPS32: sll [[T0]],[[T0]],0x8
-; MIPS32: srl [[T0]],[[T0]],0x8
-; MIPS32: or [[T12]],[[T12]],[[T0]]
-; MIPS32: move [[T0]],a3
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: move [[T1]],[[T3]]
-; MIPS32: andi [[T1]],[[T1]],0xff
-; MIPS32: sll [[T0]],[[T0]],0x18
-; MIPS32: sll [[T1]],[[T1]],0x18
-; MIPS32: slt [[T0]],[[T0]],[[T1]]
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: srl [[T7]],[[T7]],0x8
-; MIPS32: sll [[T7]],[[T7]],0x8
-; MIPS32: or [[T0]],[[T0]],[[T7]]
-; MIPS32: move [[T1]],a3
-; MIPS32: srl [[T1]],[[T1]],0x8
-; MIPS32: andi [[T1]],[[T1]],0xff
-; MIPS32: move [[T2]],[[T3]]
-; MIPS32: srl [[T2]],[[T2]],0x8
-; MIPS32: andi [[T2]],[[T2]],0xff
-; MIPS32: sll [[T1]],[[T1]],0x18
-; MIPS32: sll [[T2]],[[T2]],0x18
-; MIPS32: slt [[T1]],[[T1]],[[T2]]
-; MIPS32: andi [[T1]],[[T1]],0xff
-; MIPS32: sll [[T1]],[[T1]],0x8
-; MIPS32: lui [[T2]],0xffff
-; MIPS32: ori [[T2]],[[T2]],0xff
-; MIPS32: and [[T0]],[[T0]],[[T2]]
-; MIPS32: or [[T1]],[[T1]],[[T0]]
-; MIPS32: move [[T0]],a3
-; MIPS32: srl [[T0]],[[T0]],0x10
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: move [[T2]],[[T3]]
-; MIPS32: srl [[T2]],[[T2]],0x10
-; MIPS32: andi [[T2]],[[T2]],0xff
-; MIPS32: sll [[T0]],[[T0]],0x18
-; MIPS32: sll [[T2]],[[T2]],0x18
-; MIPS32: slt [[T0]],[[T0]],[[T2]]
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: sll [[T0]],[[T0]],0x10
-; MIPS32: lui [[T2]],0xff00
-; MIPS32: ori [[T2]],[[T2]],0xffff
-; MIPS32: and [[T1]],[[T1]],[[T2]]
-; MIPS32: or [[T0]],[[T0]],[[T1]]
-; MIPS32: srl [[T13:.*]],a3,0x18
-; MIPS32: srl [[T3]],[[T3]],0x18
-; MIPS32: sll [[T13]],[[T13]],0x18
-; MIPS32: sll [[T3]],[[T3]],0x18
-; MIPS32: slt [[T13]],[[T13]],[[T3]]
-; MIPS32: sll [[T13]],[[T13]],0x18
-; MIPS32: sll [[T0]],[[T0]],0x8
-; MIPS32: srl [[T0]],[[T0]],0x8
-; MIPS32: or [[T13]],[[T13]],[[T0]]
-; MIPS32: move v0,[[T10]]
-; MIPS32: move v1,[[T11]]
-; MIPS32: move a0,[[T12]]
-; MIPS32: move a1,[[T13]]
-}
-
-define internal <16 x i1> @test_icmp_v16i8_uge(<16 x i8> %a, <16 x i8> %b) {
-entry:
- %res = icmp uge <16 x i8> %a, %b
- ret <16 x i1> %res
-; CHECK-LABEL: test_icmp_v16i8_uge
-; CHECK: pxor
-; CHECK: pcmpgtb
-; CHECK: pxor
-
-; MIPS32-LABEL: test_icmp_v16i8_uge
-; MIPS32: lw [[T0:.*]],
-; MIPS32: lw [[T1:.*]],
-; MIPS32: lw [[T2:.*]],
-; MIPS32: lw [[T3:.*]],
-; MIPS32: move [[T4:.*]],zero
-; MIPS32: move [[T5:.*]],zero
-; MIPS32: move [[T6:.*]],zero
-; MIPS32: move [[T7:.*]],zero
-; MIPS32: move [[T8:.*]],a0
-; MIPS32: andi [[T8]],[[T8]],0xff
-; MIPS32: move [[T9:.*]],[[T0]]
-; MIPS32: andi [[T9]],[[T9]],0xff
-; MIPS32: sll [[T8]],[[T8]],0x18
-; MIPS32: sll [[T9]],[[T9]],0x18
-; MIPS32: sltu [[T8]],[[T8]],[[T9]]
-; MIPS32: xori [[T8]],[[T8]],0x1
-; MIPS32: andi [[T8]],[[T8]],0xff
-; MIPS32: srl [[T4]],[[T4]],0x8
-; MIPS32: sll [[T4]],[[T4]],0x8
-; MIPS32: or [[T8]],[[T8]],[[T4]]
-; MIPS32: move [[T4]],a0
-; MIPS32: srl [[T4]],[[T4]],0x8
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: move [[T9]],[[T0]]
-; MIPS32: srl [[T9]],[[T9]],0x8
-; MIPS32: andi [[T9]],[[T9]],0xff
-; MIPS32: sll [[T4]],[[T4]],0x18
-; MIPS32: sll [[T9]],[[T9]],0x18
-; MIPS32: sltu [[T4]],[[T4]],[[T9]]
-; MIPS32: xori [[T4]],[[T4]],0x1
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: sll [[T4]],[[T4]],0x8
-; MIPS32: lui [[T9]],0xffff
-; MIPS32: ori [[T9]],[[T9]],0xff
-; MIPS32: and [[T8]],[[T8]],[[T9]]
-; MIPS32: or [[T4]],[[T4]],[[T8]]
-; MIPS32: move [[T8]],a0
-; MIPS32: srl [[T8]],[[T8]],0x10
-; MIPS32: andi [[T8]],[[T8]],0xff
-; MIPS32: move [[T9]],[[T0]]
-; MIPS32: srl [[T9]],[[T9]],0x10
-; MIPS32: andi [[T9]],[[T9]],0xff
-; MIPS32: sll [[T8]],[[T8]],0x18
-; MIPS32: sll [[T9]],[[T9]],0x18
-; MIPS32: sltu [[T8]],[[T8]],[[T9]]
-; MIPS32: xori [[T8]],[[T8]],0x1
-; MIPS32: andi [[T8]],[[T8]],0xff
-; MIPS32: sll [[T8]],[[T8]],0x10
-; MIPS32: lui [[T9]],0xff00
-; MIPS32: ori [[T9]],[[T9]],0xffff
-; MIPS32: and [[T4]],[[T4]],[[T9]]
-; MIPS32: or [[T8]],[[T8]],[[T4]]
-; MIPS32: srl [[T10:.*]],a0,0x18
-; MIPS32: srl [[T0]],[[T0]],0x18
-; MIPS32: sll [[T10]],[[T10]],0x18
-; MIPS32: sll [[T0]],[[T0]],0x18
-; MIPS32: sltu [[T10]],[[T10]],[[T0]]
-; MIPS32: xori [[T10]],[[T10]],0x1
-; MIPS32: sll [[T10]],[[T10]],0x18
-; MIPS32: sll [[T8]],[[T8]],0x8
-; MIPS32: srl [[T8]],[[T8]],0x8
-; MIPS32: or [[T10]],[[T10]],[[T8]]
-; MIPS32: move [[T0]],a1
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: move [[T4]],[[T1]]
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: sll [[T0]],[[T0]],0x18
-; MIPS32: sll [[T4]],[[T4]],0x18
-; MIPS32: sltu [[T0]],[[T0]],[[T4]]
-; MIPS32: xori [[T0]],[[T0]],0x1
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: srl [[T5]],[[T5]],0x8
-; MIPS32: sll [[T5]],[[T5]],0x8
-; MIPS32: or [[T0]],[[T0]],[[T5]]
-; MIPS32: move [[T4]],a1
-; MIPS32: srl [[T4]],[[T4]],0x8
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: move [[T5]],[[T1]]
-; MIPS32: srl [[T5]],[[T5]],0x8
-; MIPS32: andi [[T5]],[[T5]],0xff
-; MIPS32: sll [[T4]],[[T4]],0x18
-; MIPS32: sll [[T5]],[[T5]],0x18
-; MIPS32: sltu [[T4]],[[T4]],[[T5]]
-; MIPS32: xori [[T4]],[[T4]],0x1
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: sll [[T4]],[[T4]],0x8
-; MIPS32: lui [[T5]],0xffff
-; MIPS32: ori [[T5]],[[T5]],0xff
-; MIPS32: and [[T0]],[[T0]],[[T5]]
-; MIPS32: or [[T4]],[[T4]],[[T0]]
-; MIPS32: move [[T0]],a1
-; MIPS32: srl [[T0]],[[T0]],0x10
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: move [[T5]],[[T1]]
-; MIPS32: srl [[T5]],[[T5]],0x10
-; MIPS32: andi [[T5]],[[T5]],0xff
-; MIPS32: sll [[T0]],[[T0]],0x18
-; MIPS32: sll [[T5]],[[T5]],0x18
-; MIPS32: sltu [[T0]],[[T0]],[[T5]]
-; MIPS32: xori [[T0]],[[T0]],0x1
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: sll [[T0]],[[T0]],0x10
-; MIPS32: lui [[T5]],0xff00
-; MIPS32: ori [[T5]],[[T5]],0xffff
-; MIPS32: and [[T4]],[[T4]],[[T5]]
-; MIPS32: or [[T0]],[[T0]],[[T4]]
-; MIPS32: srl [[T11:.*]],a1,0x18
-; MIPS32: srl [[T1]],[[T1]],0x18
-; MIPS32: sll [[T11]],[[T11]],0x18
-; MIPS32: sll [[T1]],[[T1]],0x18
-; MIPS32: sltu [[T11]],[[T11]],[[T1]]
-; MIPS32: xori [[T11]],[[T11]],0x1
-; MIPS32: sll [[T11]],[[T11]],0x18
-; MIPS32: sll [[T0]],[[T0]],0x8
-; MIPS32: srl [[T0]],[[T0]],0x8
-; MIPS32: or [[T11]],[[T11]],[[T0]]
-; MIPS32: move [[T0]],a2
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: move [[T1]],[[T2]]
-; MIPS32: andi [[T1]],[[T1]],0xff
-; MIPS32: sll [[T0]],[[T0]],0x18
-; MIPS32: sll [[T1]],[[T1]],0x18
-; MIPS32: sltu [[T0]],[[T0]],[[T1]]
-; MIPS32: xori [[T0]],[[T0]],0x1
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: srl [[T6]],[[T6]],0x8
-; MIPS32: sll [[T6]],[[T6]],0x8
-; MIPS32: or [[T0]],[[T0]],[[T6]]
-; MIPS32: move [[T1]],a2
-; MIPS32: srl [[T1]],[[T1]],0x8
-; MIPS32: andi [[T1]],[[T1]],0xff
-; MIPS32: move [[T4]],[[T2]]
-; MIPS32: srl [[T4]],[[T4]],0x8
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: sll [[T1]],[[T1]],0x18
-; MIPS32: sll [[T4]],[[T4]],0x18
-; MIPS32: sltu [[T1]],[[T1]],[[T4]]
-; MIPS32: xori [[T1]],[[T1]],0x1
-; MIPS32: andi [[T1]],[[T1]],0xff
-; MIPS32: sll [[T1]],[[T1]],0x8
-; MIPS32: lui [[T4]],0xffff
-; MIPS32: ori [[T4]],[[T4]],0xff
-; MIPS32: and [[T0]],[[T0]],[[T4]]
-; MIPS32: or [[T1]],[[T1]],[[T0]]
-; MIPS32: move [[T0]],a2
-; MIPS32: srl [[T0]],[[T0]],0x10
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: move [[T4]],[[T2]]
-; MIPS32: srl [[T4]],[[T4]],0x10
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: sll [[T0]],[[T0]],0x18
-; MIPS32: sll [[T4]],[[T4]],0x18
-; MIPS32: sltu [[T0]],[[T0]],[[T4]]
-; MIPS32: xori [[T0]],[[T0]],0x1
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: sll [[T0]],[[T0]],0x10
-; MIPS32: lui [[T4]],0xff00
-; MIPS32: ori [[T4]],[[T4]],0xffff
-; MIPS32: and [[T1]],[[T1]],[[T4]]
-; MIPS32: or [[T0]],[[T0]],[[T1]]
-; MIPS32: srl [[T12:.*]],a2,0x18
-; MIPS32: srl [[T2]],[[T2]],0x18
-; MIPS32: sll [[T12]],[[T12]],0x18
-; MIPS32: sll [[T2]],[[T2]],0x18
-; MIPS32: sltu [[T12]],[[T12]],[[T2]]
-; MIPS32: xori [[T12]],[[T12]],0x1
-; MIPS32: sll [[T12]],[[T12]],0x18
-; MIPS32: sll [[T0]],[[T0]],0x8
-; MIPS32: srl [[T0]],[[T0]],0x8
-; MIPS32: or [[T12]],[[T12]],[[T0]]
-; MIPS32: move [[T0]],a3
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: move [[T1]],[[T3]]
-; MIPS32: andi [[T1]],[[T1]],0xff
-; MIPS32: sll [[T0]],[[T0]],0x18
-; MIPS32: sll [[T1]],[[T1]],0x18
-; MIPS32: sltu [[T0]],[[T0]],[[T1]]
-; MIPS32: xori [[T0]],[[T0]],0x1
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: srl [[T7]],[[T7]],0x8
-; MIPS32: sll [[T7]],[[T7]],0x8
-; MIPS32: or [[T0]],[[T0]],[[T7]]
-; MIPS32: move [[T1]],a3
-; MIPS32: srl [[T1]],[[T1]],0x8
-; MIPS32: andi [[T1]],[[T1]],0xff
-; MIPS32: move [[T2]],[[T3]]
-; MIPS32: srl [[T2]],[[T2]],0x8
-; MIPS32: andi [[T2]],[[T2]],0xff
-; MIPS32: sll [[T1]],[[T1]],0x18
-; MIPS32: sll [[T2]],[[T2]],0x18
-; MIPS32: sltu [[T1]],[[T1]],[[T2]]
-; MIPS32: xori [[T1]],[[T1]],0x1
-; MIPS32: andi [[T1]],[[T1]],0xff
-; MIPS32: sll [[T1]],[[T1]],0x8
-; MIPS32: lui [[T2]],0xffff
-; MIPS32: ori [[T2]],[[T2]],0xff
-; MIPS32: and [[T0]],[[T0]],[[T2]]
-; MIPS32: or [[T1]],[[T1]],[[T0]]
-; MIPS32: move [[T0]],a3
-; MIPS32: srl [[T0]],[[T0]],0x10
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: move [[T2]],[[T3]]
-; MIPS32: srl [[T2]],[[T2]],0x10
-; MIPS32: andi [[T2]],[[T2]],0xff
-; MIPS32: sll [[T0]],[[T0]],0x18
-; MIPS32: sll [[T2]],[[T2]],0x18
-; MIPS32: sltu [[T0]],[[T0]],[[T2]]
-; MIPS32: xori [[T0]],[[T0]],0x1
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: sll [[T0]],[[T0]],0x10
-; MIPS32: lui [[T2]],0xff00
-; MIPS32: ori [[T2]],[[T2]],0xffff
-; MIPS32: and [[T1]],[[T1]],[[T2]]
-; MIPS32: or [[T0]],[[T0]],[[T1]]
-; MIPS32: srl [[T13:.*]],a3,0x18
-; MIPS32: srl [[T3]],[[T3]],0x18
-; MIPS32: sll [[T13]],[[T13]],0x18
-; MIPS32: sll [[T3]],[[T3]],0x18
-; MIPS32: sltu [[T13]],[[T13]],[[T3]]
-; MIPS32: xori [[T13]],[[T13]],0x1
-; MIPS32: sll [[T13]],[[T13]],0x18
-; MIPS32: sll [[T0]],[[T0]],0x8
-; MIPS32: srl [[T0]],[[T0]],0x8
-; MIPS32: or [[T13]],[[T13]],[[T0]]
-; MIPS32: move v0,[[T10]]
-; MIPS32: move v1,[[T11]]
-; MIPS32: move a0,[[T12]]
-; MIPS32: move a1,[[T13]]
-}
-
-define internal <16 x i1> @test_icmp_v16i8_ugt(<16 x i8> %a, <16 x i8> %b) {
-entry:
- %res = icmp ugt <16 x i8> %a, %b
- ret <16 x i1> %res
-; CHECK-LABEL: test_icmp_v16i8_ugt
-; CHECK: pxor
-; CHECK: pcmpgtb
-
-; MIPS32-LABEL: test_icmp_v16i8_ugt
-; MIPS32: lw [[T0:.*]],
-; MIPS32: lw [[T1:.*]],
-; MIPS32: lw [[T2:.*]],
-; MIPS32: lw [[T3:.*]],
-; MIPS32: move [[T4:.*]],zero
-; MIPS32: move [[T5:.*]],zero
-; MIPS32: move [[T6:.*]],zero
-; MIPS32: move [[T7:.*]],zero
-; MIPS32: move [[T8:.*]],a0
-; MIPS32: andi [[T8]],[[T8]],0xff
-; MIPS32: move [[T9:.*]],[[T0]]
-; MIPS32: andi [[T9]],[[T9]],0xff
-; MIPS32: sll [[T8]],[[T8]],0x18
-; MIPS32: sll [[T9]],[[T9]],0x18
-; MIPS32: sltu [[T9]],[[T9]],[[T8]]
-; MIPS32: andi [[T9]],[[T9]],0xff
-; MIPS32: srl [[T4]],[[T4]],0x8
-; MIPS32: sll [[T4]],[[T4]],0x8
-; MIPS32: or [[T9]],[[T9]],[[T4]]
-; MIPS32: move [[T4]],a0
-; MIPS32: srl [[T4]],[[T4]],0x8
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: move [[T8]],[[T0]]
-; MIPS32: srl [[T8]],[[T8]],0x8
-; MIPS32: andi [[T8]],[[T8]],0xff
-; MIPS32: sll [[T4]],[[T4]],0x18
-; MIPS32: sll [[T8]],[[T8]],0x18
-; MIPS32: sltu [[T8]],[[T8]],[[T4]]
-; MIPS32: andi [[T8]],[[T8]],0xff
-; MIPS32: sll [[T8]],[[T8]],0x8
-; MIPS32: lui [[T4]],0xffff
-; MIPS32: ori [[T4]],[[T4]],0xff
-; MIPS32: and [[T9]],[[T9]],[[T4]]
-; MIPS32: or [[T8]],[[T8]],[[T9]]
-; MIPS32: move [[T4]],a0
-; MIPS32: srl [[T4]],[[T4]],0x10
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: move [[T9]],[[T0]]
-; MIPS32: srl [[T9]],[[T9]],0x10
-; MIPS32: andi [[T9]],[[T9]],0xff
-; MIPS32: sll [[T4]],[[T4]],0x18
-; MIPS32: sll [[T9]],[[T9]],0x18
-; MIPS32: sltu [[T9]],[[T9]],[[T4]]
-; MIPS32: andi [[T9]],[[T9]],0xff
-; MIPS32: sll [[T9]],[[T9]],0x10
-; MIPS32: lui [[T4]],0xff00
-; MIPS32: ori [[T4]],[[T4]],0xffff
-; MIPS32: and [[T8]],[[T8]],[[T4]]
-; MIPS32: or [[T9]],[[T9]],[[T8]]
-; MIPS32: srl [[T10:.*]],a0,0x18
-; MIPS32: srl [[T0]],[[T0]],0x18
-; MIPS32: sll [[T10]],[[T10]],0x18
-; MIPS32: sll [[T0]],[[T0]],0x18
-; MIPS32: sltu [[T0]],[[T0]],[[T10]]
-; MIPS32: sll [[T0]],[[T0]],0x18
-; MIPS32: sll [[T9]],[[T9]],0x8
-; MIPS32: srl [[T9]],[[T9]],0x8
-; MIPS32: or v0,[[T0]],[[T9]]
-; MIPS32: move [[T10]],a1
-; MIPS32: andi [[T10]],[[T10]],0xff
-; MIPS32: move [[T4]],[[T1]]
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: sll [[T10]],[[T10]],0x18
-; MIPS32: sll [[T4]],[[T4]],0x18
-; MIPS32: sltu [[T4]],[[T4]],[[T10]]
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: srl [[T5]],[[T5]],0x8
-; MIPS32: sll [[T5]],[[T5]],0x8
-; MIPS32: or [[T4]],[[T4]],[[T5]]
-; MIPS32: move [[T10]],a1
-; MIPS32: srl [[T10]],[[T10]],0x8
-; MIPS32: andi [[T10]],[[T10]],0xff
-; MIPS32: move [[T5]],[[T1]]
-; MIPS32: srl [[T5]],[[T5]],0x8
-; MIPS32: andi [[T5]],[[T5]],0xff
-; MIPS32: sll [[T10]],[[T10]],0x18
-; MIPS32: sll [[T5]],[[T5]],0x18
-; MIPS32: sltu [[T5]],[[T5]],[[T10]]
-; MIPS32: andi [[T5]],[[T5]],0xff
-; MIPS32: sll [[T5]],[[T5]],0x8
-; MIPS32: lui [[T10]],0xffff
-; MIPS32: ori [[T10]],[[T10]],0xff
-; MIPS32: and [[T4]],[[T4]],[[T10]]
-; MIPS32: or [[T5]],[[T5]],[[T4]]
-; MIPS32: move [[T10]],a1
-; MIPS32: srl [[T10]],[[T10]],0x10
-; MIPS32: andi [[T10]],[[T10]],0xff
-; MIPS32: move [[T4]],[[T1]]
-; MIPS32: srl [[T4]],[[T4]],0x10
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: sll [[T10]],[[T10]],0x18
-; MIPS32: sll [[T4]],[[T4]],0x18
-; MIPS32: sltu [[T4]],[[T4]],[[T10]]
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: sll [[T4]],[[T4]],0x10
-; MIPS32: lui [[T10]],0xff00
-; MIPS32: ori [[T10]],[[T10]],0xffff
-; MIPS32: and [[T5]],[[T5]],[[T10]]
-; MIPS32: or [[T4]],[[T4]],[[T5]]
-; MIPS32: srl [[T11:.*]],a1,0x18
-; MIPS32: srl [[T1]],[[T1]],0x18
-; MIPS32: sll [[T11]],[[T11]],0x18
-; MIPS32: sll [[T1]],[[T1]],0x18
-; MIPS32: sltu [[T1]],[[T1]],[[T11]]
-; MIPS32: sll [[T1]],[[T1]],0x18
-; MIPS32: sll [[T4]],[[T4]],0x8
-; MIPS32: srl [[T4]],[[T4]],0x8
-; MIPS32: or v1,[[T1]],[[T4]]
-; MIPS32: move [[T10]],a2
-; MIPS32: andi [[T10]],[[T10]],0xff
-; MIPS32: move [[T11]],[[T2]]
-; MIPS32: andi [[T11]],[[T11]],0xff
-; MIPS32: sll [[T10]],[[T10]],0x18
-; MIPS32: sll [[T11]],[[T11]],0x18
-; MIPS32: sltu [[T11]],[[T11]],[[T10]]
-; MIPS32: andi [[T11]],[[T11]],0xff
-; MIPS32: srl [[T6]],[[T6]],0x8
-; MIPS32: sll [[T6]],[[T6]],0x8
-; MIPS32: or [[T11]],[[T11]],[[T6]]
-; MIPS32: move [[T10]],a2
-; MIPS32: srl [[T10]],[[T10]],0x8
-; MIPS32: andi [[T10]],[[T10]],0xff
-; MIPS32: move [[T4]],[[T2]]
-; MIPS32: srl [[T4]],[[T4]],0x8
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: sll [[T10]],[[T10]],0x18
-; MIPS32: sll [[T4]],[[T4]],0x18
-; MIPS32: sltu [[T4]],[[T4]],[[T10]]
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: sll [[T4]],[[T4]],0x8
-; MIPS32: lui [[T10]],0xffff
-; MIPS32: ori [[T10]],[[T10]],0xff
-; MIPS32: and [[T11]],[[T11]],[[T10]]
-; MIPS32: or [[T4]],[[T4]],[[T11]]
-; MIPS32: move [[T10]],a2
-; MIPS32: srl [[T10]],[[T10]],0x10
-; MIPS32: andi [[T10]],[[T10]],0xff
-; MIPS32: move [[T11]],[[T2]]
-; MIPS32: srl [[T11]],[[T11]],0x10
-; MIPS32: andi [[T11]],[[T11]],0xff
-; MIPS32: sll [[T10]],[[T10]],0x18
-; MIPS32: sll [[T11]],[[T11]],0x18
-; MIPS32: sltu [[T11]],[[T11]],[[T10]]
-; MIPS32: andi [[T11]],[[T11]],0xff
-; MIPS32: sll [[T11]],[[T11]],0x10
-; MIPS32: lui [[T10]],0xff00
-; MIPS32: ori [[T10]],[[T10]],0xffff
-; MIPS32: and [[T4]],[[T4]],[[T10]]
-; MIPS32: or [[T11]],[[T11]],[[T4]]
-; MIPS32: srl [[T12:.*]],a2,0x18
-; MIPS32: srl [[T2]],[[T2]],0x18
-; MIPS32: sll [[T12]],[[T12]],0x18
-; MIPS32: sll [[T2]],[[T2]],0x18
-; MIPS32: sltu [[T2]],[[T2]],[[T12]]
-; MIPS32: sll [[T2]],[[T2]],0x18
-; MIPS32: sll [[T11]],[[T11]],0x8
-; MIPS32: srl [[T11]],[[T11]],0x8
-; MIPS32: or [[T2]],[[T2]],[[T11]]
-; MIPS32: move [[T10]],a3
-; MIPS32: andi [[T10]],[[T10]],0xff
-; MIPS32: move [[T11]],[[T3]]
-; MIPS32: andi [[T11]],[[T11]],0xff
-; MIPS32: sll [[T10]],[[T10]],0x18
-; MIPS32: sll [[T11]],[[T11]],0x18
-; MIPS32: sltu [[T11]],[[T11]],[[T10]]
-; MIPS32: andi [[T11]],[[T11]],0xff
-; MIPS32: srl [[T7]],[[T7]],0x8
-; MIPS32: sll [[T7]],[[T7]],0x8
-; MIPS32: or [[T11]],[[T11]],[[T7]]
-; MIPS32: move [[T10]],a3
-; MIPS32: srl [[T10]],[[T10]],0x8
-; MIPS32: andi [[T10]],[[T10]],0xff
-; MIPS32: move [[T12]],[[T3]]
-; MIPS32: srl [[T12]],[[T12]],0x8
-; MIPS32: andi [[T12]],[[T12]],0xff
-; MIPS32: sll [[T10]],[[T10]],0x18
-; MIPS32: sll [[T12]],[[T12]],0x18
-; MIPS32: sltu [[T12]],[[T12]],[[T10]]
-; MIPS32: andi [[T12]],[[T12]],0xff
-; MIPS32: sll [[T12]],[[T12]],0x8
-; MIPS32: lui [[T10]],0xffff
-; MIPS32: ori [[T10]],[[T10]],0xff
-; MIPS32: and [[T11]],[[T11]],[[T10]]
-; MIPS32: or [[T12]],[[T12]],[[T11]]
-; MIPS32: move [[T10]],a3
-; MIPS32: srl [[T10]],[[T10]],0x10
-; MIPS32: andi [[T10]],[[T10]],0xff
-; MIPS32: move [[T11]],[[T3]]
-; MIPS32: srl [[T11]],[[T11]],0x10
-; MIPS32: andi [[T11]],[[T11]],0xff
-; MIPS32: sll [[T10]],[[T10]],0x18
-; MIPS32: sll [[T11]],[[T11]],0x18
-; MIPS32: sltu [[T11]],[[T11]],[[T10]]
-; MIPS32: andi [[T11]],[[T11]],0xff
-; MIPS32: sll [[T11]],[[T11]],0x10
-; MIPS32: lui [[T10]],0xff00
-; MIPS32: ori [[T10]],[[T10]],0xffff
-; MIPS32: and [[T12]],[[T12]],[[T10]]
-; MIPS32: or [[T11]],[[T11]],[[T12]]
-; MIPS32: srl [[T13:.*]],a3,0x18
-; MIPS32: srl [[T3]],[[T3]],0x18
-; MIPS32: sll [[T13]],[[T13]],0x18
-; MIPS32: sll [[T3]],[[T3]],0x18
-; MIPS32: sltu [[T3]],[[T3]],[[T13]]
-; MIPS32: sll [[T3]],[[T3]],0x18
-; MIPS32: sll [[T11]],[[T11]],0x8
-; MIPS32: srl [[T11]],[[T11]],0x8
-; MIPS32: or [[T3]],[[T3]],[[T11]]
-; MIPS32: move a0,[[T2]]
-; MIPS32: move a1,[[T3]]
-}
-
-define internal <16 x i1> @test_icmp_v16i8_ule(<16 x i8> %a, <16 x i8> %b) {
-entry:
- %res = icmp ule <16 x i8> %a, %b
- ret <16 x i1> %res
-; CHECK-LABEL: test_icmp_v16i8_ule
-; CHECK: pxor
-; CHECK: pcmpgtb
-; CHECK: pxor
-
-; MIPS32-LABEL: test_icmp_v16i8_ule
-; MIPS32: lw [[T0:.*]],
-; MIPS32: lw [[T1:.*]],
-; MIPS32: lw [[T2:.*]],
-; MIPS32: lw [[T3:.*]],
-; MIPS32: move [[T4:.*]],zero
-; MIPS32: move [[T5:.*]],zero
-; MIPS32: move [[T6:.*]],zero
-; MIPS32: move [[T7:.*]],zero
-; MIPS32: move [[T8:.*]],a0
-; MIPS32: andi [[T8]],[[T8]],0xff
-; MIPS32: move [[T9:.*]],[[T0]]
-; MIPS32: andi [[T9]],[[T9]],0xff
-; MIPS32: sll [[T8]],[[T8]],0x18
-; MIPS32: sll [[T9]],[[T9]],0x18
-; MIPS32: sltu [[T9]],[[T9]],[[T8]]
-; MIPS32: xori [[T9]],[[T9]],0x1
-; MIPS32: andi [[T9]],[[T9]],0xff
-; MIPS32: srl [[T4]],[[T4]],0x8
-; MIPS32: sll [[T4]],[[T4]],0x8
-; MIPS32: or [[T9]],[[T9]],[[T4]]
-; MIPS32: move [[T4]],a0
-; MIPS32: srl [[T4]],[[T4]],0x8
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: move [[T8]],[[T0]]
-; MIPS32: srl [[T8]],[[T8]],0x8
-; MIPS32: andi [[T8]],[[T8]],0xff
-; MIPS32: sll [[T4]],[[T4]],0x18
-; MIPS32: sll [[T8]],[[T8]],0x18
-; MIPS32: sltu [[T8]],[[T8]],[[T4]]
-; MIPS32: xori [[T8]],[[T8]],0x1
-; MIPS32: andi [[T8]],[[T8]],0xff
-; MIPS32: sll [[T8]],[[T8]],0x8
-; MIPS32: lui [[T4]],0xffff
-; MIPS32: ori [[T4]],[[T4]],0xff
-; MIPS32: and [[T9]],[[T9]],[[T4]]
-; MIPS32: or [[T8]],[[T8]],[[T9]]
-; MIPS32: move [[T4]],a0
-; MIPS32: srl [[T4]],[[T4]],0x10
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: move [[T9]],[[T0]]
-; MIPS32: srl [[T9]],[[T9]],0x10
-; MIPS32: andi [[T9]],[[T9]],0xff
-; MIPS32: sll [[T4]],[[T4]],0x18
-; MIPS32: sll [[T9]],[[T9]],0x18
-; MIPS32: sltu [[T9]],[[T9]],[[T4]]
-; MIPS32: xori [[T9]],[[T9]],0x1
-; MIPS32: andi [[T9]],[[T9]],0xff
-; MIPS32: sll [[T9]],[[T9]],0x10
-; MIPS32: lui [[T4]],0xff00
-; MIPS32: ori [[T4]],[[T4]],0xffff
-; MIPS32: and [[T8]],[[T8]],[[T4]]
-; MIPS32: or [[T9]],[[T9]],[[T8]]
-; MIPS32: srl [[T10:.*]],a0,0x18
-; MIPS32: srl [[T0]],[[T0]],0x18
-; MIPS32: sll [[T10]],[[T10]],0x18
-; MIPS32: sll [[T0]],[[T0]],0x18
-; MIPS32: sltu [[T0]],[[T0]],[[T10]]
-; MIPS32: xori [[T0]],[[T0]],0x1
-; MIPS32: sll [[T0]],[[T0]],0x18
-; MIPS32: sll [[T9]],[[T9]],0x8
-; MIPS32: srl [[T9]],[[T9]],0x8
-; MIPS32: or v0,[[T0]],[[T9]]
-; MIPS32: move [[T10]],a1
-; MIPS32: andi [[T10]],[[T10]],0xff
-; MIPS32: move [[T4]],[[T1]]
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: sll [[T10]],[[T10]],0x18
-; MIPS32: sll [[T4]],[[T4]],0x18
-; MIPS32: sltu [[T4]],[[T4]],[[T10]]
-; MIPS32: xori [[T4]],[[T4]],0x1
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: srl [[T5]],[[T5]],0x8
-; MIPS32: sll [[T5]],[[T5]],0x8
-; MIPS32: or [[T4]],[[T4]],[[T5]]
-; MIPS32: move [[T10]],a1
-; MIPS32: srl [[T10]],[[T10]],0x8
-; MIPS32: andi [[T10]],[[T10]],0xff
-; MIPS32: move [[T5]],[[T1]]
-; MIPS32: srl [[T5]],[[T5]],0x8
-; MIPS32: andi [[T5]],[[T5]],0xff
-; MIPS32: sll [[T10]],[[T10]],0x18
-; MIPS32: sll [[T5]],[[T5]],0x18
-; MIPS32: sltu [[T5]],[[T5]],[[T10]]
-; MIPS32: xori [[T5]],[[T5]],0x1
-; MIPS32: andi [[T5]],[[T5]],0xff
-; MIPS32: sll [[T5]],[[T5]],0x8
-; MIPS32: lui [[T10]],0xffff
-; MIPS32: ori [[T10]],[[T10]],0xff
-; MIPS32: and [[T4]],[[T4]],[[T10]]
-; MIPS32: or [[T5]],[[T5]],[[T4]]
-; MIPS32: move [[T10]],a1
-; MIPS32: srl [[T10]],[[T10]],0x10
-; MIPS32: andi [[T10]],[[T10]],0xff
-; MIPS32: move [[T4]],[[T1]]
-; MIPS32: srl [[T4]],[[T4]],0x10
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: sll [[T10]],[[T10]],0x18
-; MIPS32: sll [[T4]],[[T4]],0x18
-; MIPS32: sltu [[T4]],[[T4]],[[T10]]
-; MIPS32: xori [[T4]],[[T4]],0x1
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: sll [[T4]],[[T4]],0x10
-; MIPS32: lui [[T10]],0xff00
-; MIPS32: ori [[T10]],[[T10]],0xffff
-; MIPS32: and [[T5]],[[T5]],[[T10]]
-; MIPS32: or [[T4]],[[T4]],[[T5]]
-; MIPS32: srl [[T11:.*]],a1,0x18
-; MIPS32: srl [[T1]],[[T1]],0x18
-; MIPS32: sll [[T11]],[[T11]],0x18
-; MIPS32: sll [[T1]],[[T1]],0x18
-; MIPS32: sltu [[T1]],[[T1]],[[T11]]
-; MIPS32: xori [[T1]],[[T1]],0x1
-; MIPS32: sll [[T1]],[[T1]],0x18
-; MIPS32: sll [[T4]],[[T4]],0x8
-; MIPS32: srl [[T4]],[[T4]],0x8
-; MIPS32: or v1,[[T1]],[[T4]]
-; MIPS32: move [[T10]],a2
-; MIPS32: andi [[T10]],[[T10]],0xff
-; MIPS32: move [[T11]],[[T2]]
-; MIPS32: andi [[T11]],[[T11]],0xff
-; MIPS32: sll [[T10]],[[T10]],0x18
-; MIPS32: sll [[T11]],[[T11]],0x18
-; MIPS32: sltu [[T11]],[[T11]],[[T10]]
-; MIPS32: xori [[T11]],[[T11]],0x1
-; MIPS32: andi [[T11]],[[T11]],0xff
-; MIPS32: srl [[T6]],[[T6]],0x8
-; MIPS32: sll [[T6]],[[T6]],0x8
-; MIPS32: or [[T11]],[[T11]],[[T6]]
-; MIPS32: move [[T10]],a2
-; MIPS32: srl [[T10]],[[T10]],0x8
-; MIPS32: andi [[T10]],[[T10]],0xff
-; MIPS32: move [[T4]],[[T2]]
-; MIPS32: srl [[T4]],[[T4]],0x8
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: sll [[T10]],[[T10]],0x18
-; MIPS32: sll [[T4]],[[T4]],0x18
-; MIPS32: sltu [[T4]],[[T4]],[[T10]]
-; MIPS32: xori [[T4]],[[T4]],0x1
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: sll [[T4]],[[T4]],0x8
-; MIPS32: lui [[T10]],0xffff
-; MIPS32: ori [[T10]],[[T10]],0xff
-; MIPS32: and [[T11]],[[T11]],[[T10]]
-; MIPS32: or [[T4]],[[T4]],[[T11]]
-; MIPS32: move [[T10]],a2
-; MIPS32: srl [[T10]],[[T10]],0x10
-; MIPS32: andi [[T10]],[[T10]],0xff
-; MIPS32: move [[T11]],[[T2]]
-; MIPS32: srl [[T11]],[[T11]],0x10
-; MIPS32: andi [[T11]],[[T11]],0xff
-; MIPS32: sll [[T10]],[[T10]],0x18
-; MIPS32: sll [[T11]],[[T11]],0x18
-; MIPS32: sltu [[T11]],[[T11]],[[T10]]
-; MIPS32: xori [[T11]],[[T11]],0x1
-; MIPS32: andi [[T11]],[[T11]],0xff
-; MIPS32: sll [[T11]],[[T11]],0x10
-; MIPS32: lui [[T10]],0xff00
-; MIPS32: ori [[T10]],[[T10]],0xffff
-; MIPS32: and [[T4]],[[T4]],[[T10]]
-; MIPS32: or [[T11]],[[T11]],[[T4]]
-; MIPS32: srl [[T12:.*]],a2,0x18
-; MIPS32: srl [[T2]],[[T2]],0x18
-; MIPS32: sll [[T12]],[[T12]],0x18
-; MIPS32: sll [[T2]],[[T2]],0x18
-; MIPS32: sltu [[T2]],[[T2]],[[T12]]
-; MIPS32: xori [[T2]],[[T2]],0x1
-; MIPS32: sll [[T2]],[[T2]],0x18
-; MIPS32: sll [[T11]],[[T11]],0x8
-; MIPS32: srl [[T11]],[[T11]],0x8
-; MIPS32: or [[T2]],[[T2]],[[T11]]
-; MIPS32: move [[T10]],a3
-; MIPS32: andi [[T10]],[[T10]],0xff
-; MIPS32: move [[T11]],[[T3]]
-; MIPS32: andi [[T11]],[[T11]],0xff
-; MIPS32: sll [[T10]],[[T10]],0x18
-; MIPS32: sll [[T11]],[[T11]],0x18
-; MIPS32: sltu [[T11]],[[T11]],[[T10]]
-; MIPS32: xori [[T11]],[[T11]],0x1
-; MIPS32: andi [[T11]],[[T11]],0xff
-; MIPS32: srl [[T7]],[[T7]],0x8
-; MIPS32: sll [[T7]],[[T7]],0x8
-; MIPS32: or [[T11]],[[T11]],[[T7]]
-; MIPS32: move [[T10]],a3
-; MIPS32: srl [[T10]],[[T10]],0x8
-; MIPS32: andi [[T10]],[[T10]],0xff
-; MIPS32: move [[T12]],[[T3]]
-; MIPS32: srl [[T12]],[[T12]],0x8
-; MIPS32: andi [[T12]],[[T12]],0xff
-; MIPS32: sll [[T10]],[[T10]],0x18
-; MIPS32: sll [[T12]],[[T12]],0x18
-; MIPS32: sltu [[T12]],[[T12]],[[T10]]
-; MIPS32: xori [[T12]],[[T12]],0x1
-; MIPS32: andi [[T12]],[[T12]],0xff
-; MIPS32: sll [[T12]],[[T12]],0x8
-; MIPS32: lui [[T10]],0xffff
-; MIPS32: ori [[T10]],[[T10]],0xff
-; MIPS32: and [[T11]],[[T11]],[[T10]]
-; MIPS32: or [[T12]],[[T12]],[[T11]]
-; MIPS32: move [[T10]],a3
-; MIPS32: srl [[T10]],[[T10]],0x10
-; MIPS32: andi [[T10]],[[T10]],0xff
-; MIPS32: move [[T11]],[[T3]]
-; MIPS32: srl [[T11]],[[T11]],0x10
-; MIPS32: andi [[T11]],[[T11]],0xff
-; MIPS32: sll [[T10]],[[T10]],0x18
-; MIPS32: sll [[T11]],[[T11]],0x18
-; MIPS32: sltu [[T11]],[[T11]],[[T10]]
-; MIPS32: xori [[T11]],[[T11]],0x1
-; MIPS32: andi [[T11]],[[T11]],0xff
-; MIPS32: sll [[T11]],[[T11]],0x10
-; MIPS32: lui [[T10]],0xff00
-; MIPS32: ori [[T10]],[[T10]],0xffff
-; MIPS32: and [[T12]],[[T12]],[[T10]]
-; MIPS32: or [[T11]],[[T11]],[[T12]]
-; MIPS32: srl [[T13:.*]],a3,0x18
-; MIPS32: srl [[T3]],[[T3]],0x18
-; MIPS32: sll [[T13]],[[T13]],0x18
-; MIPS32: sll [[T3]],[[T3]],0x18
-; MIPS32: sltu [[T3]],[[T3]],[[T13]]
-; MIPS32: xori [[T3]],[[T3]],0x1
-; MIPS32: sll [[T3]],[[T3]],0x18
-; MIPS32: sll [[T11]],[[T11]],0x8
-; MIPS32: srl [[T11]],[[T11]],0x8
-; MIPS32: or [[T3]],[[T3]],[[T11]]
-; MIPS32: move a0,[[T2]]
-; MIPS32: move a1,[[T3]]
-}
-
-define internal <16 x i1> @test_icmp_v16i8_ult(<16 x i8> %a, <16 x i8> %b) {
-entry:
- %res = icmp ult <16 x i8> %a, %b
- ret <16 x i1> %res
-; CHECK-LABEL: test_icmp_v16i8_ult
-; CHECK: pxor
-; CHECK: pcmpgtb
-
-; MIPS32-LABEL: test_icmp_v16i8_ult
-; MIPS32: lw [[T0:.*]],
-; MIPS32: lw [[T1:.*]],
-; MIPS32: lw [[T2:.*]],
-; MIPS32: lw [[T3:.*]],
-; MIPS32: move [[T4:.*]],zero
-; MIPS32: move [[T5:.*]],zero
-; MIPS32: move [[T6:.*]],zero
-; MIPS32: move [[T7:.*]],zero
-; MIPS32: move [[T8:.*]],a0
-; MIPS32: andi [[T8]],[[T8]],0xff
-; MIPS32: move [[T9:.*]],[[T0]]
-; MIPS32: andi [[T9]],[[T9]],0xff
-; MIPS32: sll [[T8]],[[T8]],0x18
-; MIPS32: sll [[T9]],[[T9]],0x18
-; MIPS32: sltu [[T8]],[[T8]],[[T9]]
-; MIPS32: andi [[T8]],[[T8]],0xff
-; MIPS32: srl [[T4]],[[T4]],0x8
-; MIPS32: sll [[T4]],[[T4]],0x8
-; MIPS32: or [[T8]],[[T8]],[[T4]]
-; MIPS32: move [[T4]],a0
-; MIPS32: srl [[T4]],[[T4]],0x8
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: move [[T9]],[[T0]]
-; MIPS32: srl [[T9]],[[T9]],0x8
-; MIPS32: andi [[T9]],[[T9]],0xff
-; MIPS32: sll [[T4]],[[T4]],0x18
-; MIPS32: sll [[T9]],[[T9]],0x18
-; MIPS32: sltu [[T4]],[[T4]],[[T9]]
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: sll [[T4]],[[T4]],0x8
-; MIPS32: lui [[T9]],0xffff
-; MIPS32: ori [[T9]],[[T9]],0xff
-; MIPS32: and [[T8]],[[T8]],[[T9]]
-; MIPS32: or [[T4]],[[T4]],[[T8]]
-; MIPS32: move [[T8]],a0
-; MIPS32: srl [[T8]],[[T8]],0x10
-; MIPS32: andi [[T8]],[[T8]],0xff
-; MIPS32: move [[T9]],[[T0]]
-; MIPS32: srl [[T9]],[[T9]],0x10
-; MIPS32: andi [[T9]],[[T9]],0xff
-; MIPS32: sll [[T8]],[[T8]],0x18
-; MIPS32: sll [[T9]],[[T9]],0x18
-; MIPS32: sltu [[T8]],[[T8]],[[T9]]
-; MIPS32: andi [[T8]],[[T8]],0xff
-; MIPS32: sll [[T8]],[[T8]],0x10
-; MIPS32: lui [[T9]],0xff00
-; MIPS32: ori [[T9]],[[T9]],0xffff
-; MIPS32: and [[T4]],[[T4]],[[T9]]
-; MIPS32: or [[T8]],[[T8]],[[T4]]
-; MIPS32: srl [[T10:.*]],a0,0x18
-; MIPS32: srl [[T0]],[[T0]],0x18
-; MIPS32: sll [[T10]],[[T10]],0x18
-; MIPS32: sll [[T0]],[[T0]],0x18
-; MIPS32: sltu [[T10]],[[T10]],[[T0]]
-; MIPS32: sll [[T10]],[[T10]],0x18
-; MIPS32: sll [[T8]],[[T8]],0x8
-; MIPS32: srl [[T8]],[[T8]],0x8
-; MIPS32: or [[T10]],[[T10]],[[T8]]
-; MIPS32: move [[T0]],a1
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: move [[T4]],[[T1]]
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: sll [[T0]],[[T0]],0x18
-; MIPS32: sll [[T4]],[[T4]],0x18
-; MIPS32: sltu [[T0]],[[T0]],[[T4]]
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: srl [[T5]],[[T5]],0x8
-; MIPS32: sll [[T5]],[[T5]],0x8
-; MIPS32: or [[T0]],[[T0]],[[T5]]
-; MIPS32: move [[T4]],a1
-; MIPS32: srl [[T4]],[[T4]],0x8
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: move [[T5]],[[T1]]
-; MIPS32: srl [[T5]],[[T5]],0x8
-; MIPS32: andi [[T5]],[[T5]],0xff
-; MIPS32: sll [[T4]],[[T4]],0x18
-; MIPS32: sll [[T5]],[[T5]],0x18
-; MIPS32: sltu [[T4]],[[T4]],[[T5]]
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: sll [[T4]],[[T4]],0x8
-; MIPS32: lui [[T5]],0xffff
-; MIPS32: ori [[T5]],[[T5]],0xff
-; MIPS32: and [[T0]],[[T0]],[[T5]]
-; MIPS32: or [[T4]],[[T4]],[[T0]]
-; MIPS32: move [[T0]],a1
-; MIPS32: srl [[T0]],[[T0]],0x10
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: move [[T5]],[[T1]]
-; MIPS32: srl [[T5]],[[T5]],0x10
-; MIPS32: andi [[T5]],[[T5]],0xff
-; MIPS32: sll [[T0]],[[T0]],0x18
-; MIPS32: sll [[T5]],[[T5]],0x18
-; MIPS32: sltu [[T0]],[[T0]],[[T5]]
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: sll [[T0]],[[T0]],0x10
-; MIPS32: lui [[T5]],0xff00
-; MIPS32: ori [[T5]],[[T5]],0xffff
-; MIPS32: and [[T4]],[[T4]],[[T5]]
-; MIPS32: or [[T0]],[[T0]],[[T4]]
-; MIPS32: srl [[T11:.*]],a1,0x18
-; MIPS32: srl [[T1]],[[T1]],0x18
-; MIPS32: sll [[T11]],[[T11]],0x18
-; MIPS32: sll [[T1]],[[T1]],0x18
-; MIPS32: sltu [[T11]],[[T11]],[[T1]]
-; MIPS32: sll [[T11]],[[T11]],0x18
-; MIPS32: sll [[T0]],[[T0]],0x8
-; MIPS32: srl [[T0]],[[T0]],0x8
-; MIPS32: or [[T11]],[[T11]],[[T0]]
-; MIPS32: move [[T0]],a2
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: move [[T1]],[[T2]]
-; MIPS32: andi [[T1]],[[T1]],0xff
-; MIPS32: sll [[T0]],[[T0]],0x18
-; MIPS32: sll [[T1]],[[T1]],0x18
-; MIPS32: sltu [[T0]],[[T0]],[[T1]]
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: srl [[T6]],[[T6]],0x8
-; MIPS32: sll [[T6]],[[T6]],0x8
-; MIPS32: or [[T0]],[[T0]],[[T6]]
-; MIPS32: move [[T1]],a2
-; MIPS32: srl [[T1]],[[T1]],0x8
-; MIPS32: andi [[T1]],[[T1]],0xff
-; MIPS32: move [[T4]],[[T2]]
-; MIPS32: srl [[T4]],[[T4]],0x8
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: sll [[T1]],[[T1]],0x18
-; MIPS32: sll [[T4]],[[T4]],0x18
-; MIPS32: sltu [[T1]],[[T1]],[[T4]]
-; MIPS32: andi [[T1]],[[T1]],0xff
-; MIPS32: sll [[T1]],[[T1]],0x8
-; MIPS32: lui [[T4]],0xffff
-; MIPS32: ori [[T4]],[[T4]],0xff
-; MIPS32: and [[T0]],[[T0]],[[T4]]
-; MIPS32: or [[T1]],[[T1]],[[T0]]
-; MIPS32: move [[T0]],a2
-; MIPS32: srl [[T0]],[[T0]],0x10
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: move [[T4]],[[T2]]
-; MIPS32: srl [[T4]],[[T4]],0x10
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: sll [[T0]],[[T0]],0x18
-; MIPS32: sll [[T4]],[[T4]],0x18
-; MIPS32: sltu [[T0]],[[T0]],[[T4]]
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: sll [[T0]],[[T0]],0x10
-; MIPS32: lui [[T4]],0xff00
-; MIPS32: ori [[T4]],[[T4]],0xffff
-; MIPS32: and [[T1]],[[T1]],[[T4]]
-; MIPS32: or [[T0]],[[T0]],[[T1]]
-; MIPS32: srl [[T12:.*]],a2,0x18
-; MIPS32: srl [[T2]],[[T2]],0x18
-; MIPS32: sll [[T12]],[[T12]],0x18
-; MIPS32: sll [[T2]],[[T2]],0x18
-; MIPS32: sltu [[T12]],[[T12]],[[T2]]
-; MIPS32: sll [[T12]],[[T12]],0x18
-; MIPS32: sll [[T0]],[[T0]],0x8
-; MIPS32: srl [[T0]],[[T0]],0x8
-; MIPS32: or [[T12]],[[T12]],[[T0]]
-; MIPS32: move [[T0]],a3
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: move [[T1]],[[T3]]
-; MIPS32: andi [[T1]],[[T1]],0xff
-; MIPS32: sll [[T0]],[[T0]],0x18
-; MIPS32: sll [[T1]],[[T1]],0x18
-; MIPS32: sltu [[T0]],[[T0]],[[T1]]
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: srl [[T7]],[[T7]],0x8
-; MIPS32: sll [[T7]],[[T7]],0x8
-; MIPS32: or [[T0]],[[T0]],[[T7]]
-; MIPS32: move [[T1]],a3
-; MIPS32: srl [[T1]],[[T1]],0x8
-; MIPS32: andi [[T1]],[[T1]],0xff
-; MIPS32: move [[T2]],[[T3]]
-; MIPS32: srl [[T2]],[[T2]],0x8
-; MIPS32: andi [[T2]],[[T2]],0xff
-; MIPS32: sll [[T1]],[[T1]],0x18
-; MIPS32: sll [[T2]],[[T2]],0x18
-; MIPS32: sltu [[T1]],[[T1]],[[T2]]
-; MIPS32: andi [[T1]],[[T1]],0xff
-; MIPS32: sll [[T1]],[[T1]],0x8
-; MIPS32: lui [[T2]],0xffff
-; MIPS32: ori [[T2]],[[T2]],0xff
-; MIPS32: and [[T0]],[[T0]],[[T2]]
-; MIPS32: or [[T1]],[[T1]],[[T0]]
-; MIPS32: move [[T0]],a3
-; MIPS32: srl [[T0]],[[T0]],0x10
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: move [[T2]],[[T3]]
-; MIPS32: srl [[T2]],[[T2]],0x10
-; MIPS32: andi [[T2]],[[T2]],0xff
-; MIPS32: sll [[T0]],[[T0]],0x18
-; MIPS32: sll [[T2]],[[T2]],0x18
-; MIPS32: sltu [[T0]],[[T0]],[[T2]]
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: sll [[T0]],[[T0]],0x10
-; MIPS32: lui [[T2]],0xff00
-; MIPS32: ori [[T2]],[[T2]],0xffff
-; MIPS32: and [[T1]],[[T1]],[[T2]]
-; MIPS32: or [[T0]],[[T0]],[[T1]]
-; MIPS32: srl [[T13:.*]],a3,0x18
-; MIPS32: srl [[T3]],[[T3]],0x18
-; MIPS32: sll [[T13]],[[T13]],0x18
-; MIPS32: sll [[T3]],[[T3]],0x18
-; MIPS32: sltu [[T13]],[[T13]],[[T3]]
-; MIPS32: sll [[T13]],[[T13]],0x18
-; MIPS32: sll [[T0]],[[T0]],0x8
-; MIPS32: srl [[T0]],[[T0]],0x8
-; MIPS32: or [[T13]],[[T13]],[[T0]]
-; MIPS32: move v0,[[T10]]
-; MIPS32: move v1,[[T11]]
-; MIPS32: move a0,[[T12]]
-; MIPS32: move a1,[[T13]]
-}
-
-define internal <16 x i1> @test_icmp_v16i1_eq(<16 x i1> %a, <16 x i1> %b) {
-entry:
- %res = icmp eq <16 x i1> %a, %b
- ret <16 x i1> %res
-; CHECK-LABEL: test_icmp_v16i1_eq
-; CHECK: pcmpeqb
-
-; MIPS32-LABEL: test_icmp_v16i1_eq
-; MIPS32: lw [[T0:.*]],
-; MIPS32: lw [[T1:.*]],
-; MIPS32: lw [[T2:.*]],
-; MIPS32: lw [[T3:.*]],
-; MIPS32: move [[T4:.*]],zero
-; MIPS32: move [[T5:.*]],zero
-; MIPS32: move [[T6:.*]],zero
-; MIPS32: move [[T7:.*]],zero
-; MIPS32: move [[T8:.*]],a0
-; MIPS32: andi [[T8]],[[T8]],0xff
-; MIPS32: andi [[T8]],[[T8]],0x1
-; MIPS32: move [[T9:.*]],[[T0]]
-; MIPS32: andi [[T9]],[[T9]],0xff
-; MIPS32: andi [[T9]],[[T9]],0x1
-; MIPS32: sll [[T8]],[[T8]],0x1f
-; MIPS32: sll [[T9]],[[T9]],0x1f
-; MIPS32: xor [[T8]],[[T8]],[[T9]]
-; MIPS32: sltiu [[T8]],[[T8]],1
-; MIPS32: andi [[T8]],[[T8]],0xff
-; MIPS32: srl [[T4]],[[T4]],0x8
-; MIPS32: sll [[T4]],[[T4]],0x8
-; MIPS32: or [[T8]],[[T8]],[[T4]]
-; MIPS32: move [[T4]],a0
-; MIPS32: srl [[T4]],[[T4]],0x8
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: andi [[T4]],[[T4]],0x1
-; MIPS32: move [[T9]],[[T0]]
-; MIPS32: srl [[T9]],[[T9]],0x8
-; MIPS32: andi [[T9]],[[T9]],0xff
-; MIPS32: andi [[T9]],[[T9]],0x1
-; MIPS32: sll [[T4]],[[T4]],0x1f
-; MIPS32: sll [[T9]],[[T9]],0x1f
-; MIPS32: xor [[T4]],[[T4]],[[T9]]
-; MIPS32: sltiu [[T4]],[[T4]],1
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: sll [[T4]],[[T4]],0x8
-; MIPS32: lui [[T9]],0xffff
-; MIPS32: ori [[T9]],[[T9]],0xff
-; MIPS32: and [[T8]],[[T8]],[[T9]]
-; MIPS32: or [[T4]],[[T4]],[[T8]]
-; MIPS32: move [[T8]],a0
-; MIPS32: srl [[T8]],[[T8]],0x10
-; MIPS32: andi [[T8]],[[T8]],0xff
-; MIPS32: andi [[T8]],[[T8]],0x1
-; MIPS32: move [[T9]],[[T0]]
-; MIPS32: srl [[T9]],[[T9]],0x10
-; MIPS32: andi [[T9]],[[T9]],0xff
-; MIPS32: andi [[T9]],[[T9]],0x1
-; MIPS32: sll [[T8]],[[T8]],0x1f
-; MIPS32: sll [[T9]],[[T9]],0x1f
-; MIPS32: xor [[T8]],[[T8]],[[T9]]
-; MIPS32: sltiu [[T8]],[[T8]],1
-; MIPS32: andi [[T8]],[[T8]],0xff
-; MIPS32: sll [[T8]],[[T8]],0x10
-; MIPS32: lui [[T9]],0xff00
-; MIPS32: ori [[T9]],[[T9]],0xffff
-; MIPS32: and [[T4]],[[T4]],[[T9]]
-; MIPS32: or [[T8]],[[T8]],[[T4]]
-; MIPS32: srl [[T10:.*]],a0,0x18
-; MIPS32: andi [[T10]],[[T10]],0x1
-; MIPS32: srl [[T0]],[[T0]],0x18
-; MIPS32: andi [[T0]],[[T0]],0x1
-; MIPS32: sll [[T10]],[[T10]],0x1f
-; MIPS32: sll [[T0]],[[T0]],0x1f
-; MIPS32: xor [[T10]],[[T10]],[[T0]]
-; MIPS32: sltiu [[T10]],[[T10]],1
-; MIPS32: sll [[T10]],[[T10]],0x18
-; MIPS32: sll [[T8]],[[T8]],0x8
-; MIPS32: srl [[T8]],[[T8]],0x8
-; MIPS32: or [[T10]],[[T10]],[[T8]]
-; MIPS32: move [[T0]],a1
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: andi [[T0]],[[T0]],0x1
-; MIPS32: move [[T4]],[[T1]]
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: andi [[T4]],[[T4]],0x1
-; MIPS32: sll [[T0]],[[T0]],0x1f
-; MIPS32: sll [[T4]],[[T4]],0x1f
-; MIPS32: xor [[T0]],[[T0]],[[T4]]
-; MIPS32: sltiu [[T0]],[[T0]],1
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: srl [[T5]],[[T5]],0x8
-; MIPS32: sll [[T5]],[[T5]],0x8
-; MIPS32: or [[T0]],[[T0]],[[T5]]
-; MIPS32: move [[T4]],a1
-; MIPS32: srl [[T4]],[[T4]],0x8
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: andi [[T4]],[[T4]],0x1
-; MIPS32: move [[T5]],[[T1]]
-; MIPS32: srl [[T5]],[[T5]],0x8
-; MIPS32: andi [[T5]],[[T5]],0xff
-; MIPS32: andi [[T5]],[[T5]],0x1
-; MIPS32: sll [[T4]],[[T4]],0x1f
-; MIPS32: sll [[T5]],[[T5]],0x1f
-; MIPS32: xor [[T4]],[[T4]],[[T5]]
-; MIPS32: sltiu [[T4]],[[T4]],1
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: sll [[T4]],[[T4]],0x8
-; MIPS32: lui [[T5]],0xffff
-; MIPS32: ori [[T5]],[[T5]],0xff
-; MIPS32: and [[T0]],[[T0]],[[T5]]
-; MIPS32: or [[T4]],[[T4]],[[T0]]
-; MIPS32: move [[T0]],a1
-; MIPS32: srl [[T0]],[[T0]],0x10
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: andi [[T0]],[[T0]],0x1
-; MIPS32: move [[T5]],[[T1]]
-; MIPS32: srl [[T5]],[[T5]],0x10
-; MIPS32: andi [[T5]],[[T5]],0xff
-; MIPS32: andi [[T5]],[[T5]],0x1
-; MIPS32: sll [[T0]],[[T0]],0x1f
-; MIPS32: sll [[T5]],[[T5]],0x1f
-; MIPS32: xor [[T0]],[[T0]],[[T5]]
-; MIPS32: sltiu [[T0]],[[T0]],1
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: sll [[T0]],[[T0]],0x10
-; MIPS32: lui [[T5]],0xff00
-; MIPS32: ori [[T5]],[[T5]],0xffff
-; MIPS32: and [[T4]],[[T4]],[[T5]]
-; MIPS32: or [[T0]],[[T0]],[[T4]]
-; MIPS32: srl [[T11:.*]],a1,0x18
-; MIPS32: andi [[T11]],[[T11]],0x1
-; MIPS32: srl [[T1]],[[T1]],0x18
-; MIPS32: andi [[T1]],[[T1]],0x1
-; MIPS32: sll [[T11]],[[T11]],0x1f
-; MIPS32: sll [[T1]],[[T1]],0x1f
-; MIPS32: xor [[T11]],[[T11]],[[T1]]
-; MIPS32: sltiu [[T11]],[[T11]],1
-; MIPS32: sll [[T11]],[[T11]],0x18
-; MIPS32: sll [[T0]],[[T0]],0x8
-; MIPS32: srl [[T0]],[[T0]],0x8
-; MIPS32: or [[T11]],[[T11]],[[T0]]
-; MIPS32: move [[T0]],a2
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: andi [[T0]],[[T0]],0x1
-; MIPS32: move [[T1]],[[T2]]
-; MIPS32: andi [[T1]],[[T1]],0xff
-; MIPS32: andi [[T1]],[[T1]],0x1
-; MIPS32: sll [[T0]],[[T0]],0x1f
-; MIPS32: sll [[T1]],[[T1]],0x1f
-; MIPS32: xor [[T0]],[[T0]],[[T1]]
-; MIPS32: sltiu [[T0]],[[T0]],1
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: srl [[T6]],[[T6]],0x8
-; MIPS32: sll [[T6]],[[T6]],0x8
-; MIPS32: or [[T0]],[[T0]],[[T6]]
-; MIPS32: move [[T1]],a2
-; MIPS32: srl [[T1]],[[T1]],0x8
-; MIPS32: andi [[T1]],[[T1]],0xff
-; MIPS32: andi [[T1]],[[T1]],0x1
-; MIPS32: move [[T4]],[[T2]]
-; MIPS32: srl [[T4]],[[T4]],0x8
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: andi [[T4]],[[T4]],0x1
-; MIPS32: sll [[T1]],[[T1]],0x1f
-; MIPS32: sll [[T4]],[[T4]],0x1f
-; MIPS32: xor [[T1]],[[T1]],[[T4]]
-; MIPS32: sltiu [[T1]],[[T1]],1
-; MIPS32: andi [[T1]],[[T1]],0xff
-; MIPS32: sll [[T1]],[[T1]],0x8
-; MIPS32: lui [[T4]],0xffff
-; MIPS32: ori [[T4]],[[T4]],0xff
-; MIPS32: and [[T0]],[[T0]],[[T4]]
-; MIPS32: or [[T1]],[[T1]],[[T0]]
-; MIPS32: move [[T0]],a2
-; MIPS32: srl [[T0]],[[T0]],0x10
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: andi [[T0]],[[T0]],0x1
-; MIPS32: move [[T4]],[[T2]]
-; MIPS32: srl [[T4]],[[T4]],0x10
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: andi [[T4]],[[T4]],0x1
-; MIPS32: sll [[T0]],[[T0]],0x1f
-; MIPS32: sll [[T4]],[[T4]],0x1f
-; MIPS32: xor [[T0]],[[T0]],[[T4]]
-; MIPS32: sltiu [[T0]],[[T0]],1
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: sll [[T0]],[[T0]],0x10
-; MIPS32: lui [[T4]],0xff00
-; MIPS32: ori [[T4]],[[T4]],0xffff
-; MIPS32: and [[T1]],[[T1]],[[T4]]
-; MIPS32: or [[T0]],[[T0]],[[T1]]
-; MIPS32: srl [[T12:.*]],a2,0x18
-; MIPS32: andi [[T12]],[[T12]],0x1
-; MIPS32: srl [[T2]],[[T2]],0x18
-; MIPS32: andi [[T2]],[[T2]],0x1
-; MIPS32: sll [[T12]],[[T12]],0x1f
-; MIPS32: sll [[T2]],[[T2]],0x1f
-; MIPS32: xor [[T12]],[[T12]],[[T2]]
-; MIPS32: sltiu [[T12]],[[T12]],1
-; MIPS32: sll [[T12]],[[T12]],0x18
-; MIPS32: sll [[T0]],[[T0]],0x8
-; MIPS32: srl [[T0]],[[T0]],0x8
-; MIPS32: or [[T12]],[[T12]],[[T0]]
-; MIPS32: move [[T0]],a3
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: andi [[T0]],[[T0]],0x1
-; MIPS32: move [[T1]],[[T3]]
-; MIPS32: andi [[T1]],[[T1]],0xff
-; MIPS32: andi [[T1]],[[T1]],0x1
-; MIPS32: sll [[T0]],[[T0]],0x1f
-; MIPS32: sll [[T1]],[[T1]],0x1f
-; MIPS32: xor [[T0]],[[T0]],[[T1]]
-; MIPS32: sltiu [[T0]],[[T0]],1
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: srl [[T7]],[[T7]],0x8
-; MIPS32: sll [[T7]],[[T7]],0x8
-; MIPS32: or [[T0]],[[T0]],[[T7]]
-; MIPS32: move [[T1]],a3
-; MIPS32: srl [[T1]],[[T1]],0x8
-; MIPS32: andi [[T1]],[[T1]],0xff
-; MIPS32: andi [[T1]],[[T1]],0x1
-; MIPS32: move [[T2]],[[T3]]
-; MIPS32: srl [[T2]],[[T2]],0x8
-; MIPS32: andi [[T2]],[[T2]],0xff
-; MIPS32: andi [[T2]],[[T2]],0x1
-; MIPS32: sll [[T1]],[[T1]],0x1f
-; MIPS32: sll [[T2]],[[T2]],0x1f
-; MIPS32: xor [[T1]],[[T1]],[[T2]]
-; MIPS32: sltiu [[T1]],[[T1]],1
-; MIPS32: andi [[T1]],[[T1]],0xff
-; MIPS32: sll [[T1]],[[T1]],0x8
-; MIPS32: lui [[T2]],0xffff
-; MIPS32: ori [[T2]],[[T2]],0xff
-; MIPS32: and [[T0]],[[T0]],[[T2]]
-; MIPS32: or [[T1]],[[T1]],[[T0]]
-; MIPS32: move [[T0]],a3
-; MIPS32: srl [[T0]],[[T0]],0x10
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: andi [[T0]],[[T0]],0x1
-; MIPS32: move [[T2]],[[T3]]
-; MIPS32: srl [[T2]],[[T2]],0x10
-; MIPS32: andi [[T2]],[[T2]],0xff
-; MIPS32: andi [[T2]],[[T2]],0x1
-; MIPS32: sll [[T0]],[[T0]],0x1f
-; MIPS32: sll [[T2]],[[T2]],0x1f
-; MIPS32: xor [[T0]],[[T0]],[[T2]]
-; MIPS32: sltiu [[T0]],[[T0]],1
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: sll [[T0]],[[T0]],0x10
-; MIPS32: lui [[T2]],0xff00
-; MIPS32: ori [[T2]],[[T2]],0xffff
-; MIPS32: and [[T1]],[[T1]],[[T2]]
-; MIPS32: or [[T0]],[[T0]],[[T1]]
-; MIPS32: srl [[T13:.*]],a3,0x18
-; MIPS32: andi [[T13]],[[T13]],0x1
-; MIPS32: srl [[T3]],[[T3]],0x18
-; MIPS32: andi [[T3]],[[T3]],0x1
-; MIPS32: sll [[T13]],[[T13]],0x1f
-; MIPS32: sll [[T3]],[[T3]],0x1f
-; MIPS32: xor [[T13]],[[T13]],[[T3]]
-; MIPS32: sltiu [[T13]],[[T13]],1
-; MIPS32: sll [[T13]],[[T13]],0x18
-; MIPS32: sll [[T0]],[[T0]],0x8
-; MIPS32: srl [[T0]],[[T0]],0x8
-; MIPS32: or [[T13]],[[T13]],[[T0]]
-; MIPS32: move v0,[[T10]]
-; MIPS32: move v1,[[T11]]
-; MIPS32: move a0,[[T12]]
-; MIPS32: move a1,[[T13]]
-}
-
-define internal <16 x i1> @test_icmp_v16i1_ne(<16 x i1> %a, <16 x i1> %b) {
-entry:
- %res = icmp ne <16 x i1> %a, %b
- ret <16 x i1> %res
-; CHECK-LABEL: test_icmp_v16i1_ne
-; CHECK: pcmpeqb
-; CHECK: pxor
-
-; MIPS32-LABEL: test_icmp_v16i1_ne
-; MIPS32: lw [[T0:.*]],
-; MIPS32: lw [[T1:.*]],
-; MIPS32: lw [[T2:.*]],
-; MIPS32: lw [[T3:.*]],
-; MIPS32: move [[T4:.*]],zero
-; MIPS32: move [[T5:.*]],zero
-; MIPS32: move [[T6:.*]],zero
-; MIPS32: move [[T7:.*]],zero
-; MIPS32: move [[T8:.*]],a0
-; MIPS32: andi [[T8]],[[T8]],0xff
-; MIPS32: andi [[T8]],[[T8]],0x1
-; MIPS32: move [[T9:.*]],[[T0]]
-; MIPS32: andi [[T9]],[[T9]],0xff
-; MIPS32: andi [[T9]],[[T9]],0x1
-; MIPS32: sll [[T8]],[[T8]],0x1f
-; MIPS32: sll [[T9]],[[T9]],0x1f
-; MIPS32: xor [[T8]],[[T8]],[[T9]]
-; MIPS32: sltu [[T8]],zero,[[T8]]
-; MIPS32: andi [[T8]],[[T8]],0xff
-; MIPS32: srl [[T4]],[[T4]],0x8
-; MIPS32: sll [[T4]],[[T4]],0x8
-; MIPS32: or [[T8]],[[T8]],[[T4]]
-; MIPS32: move [[T4]],a0
-; MIPS32: srl [[T4]],[[T4]],0x8
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: andi [[T4]],[[T4]],0x1
-; MIPS32: move [[T9]],[[T0]]
-; MIPS32: srl [[T9]],[[T9]],0x8
-; MIPS32: andi [[T9]],[[T9]],0xff
-; MIPS32: andi [[T9]],[[T9]],0x1
-; MIPS32: sll [[T4]],[[T4]],0x1f
-; MIPS32: sll [[T9]],[[T9]],0x1f
-; MIPS32: xor [[T4]],[[T4]],[[T9]]
-; MIPS32: sltu [[T4]],zero,[[T4]]
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: sll [[T4]],[[T4]],0x8
-; MIPS32: lui [[T9]],0xffff
-; MIPS32: ori [[T9]],[[T9]],0xff
-; MIPS32: and [[T8]],[[T8]],[[T9]]
-; MIPS32: or [[T4]],[[T4]],[[T8]]
-; MIPS32: move [[T8]],a0
-; MIPS32: srl [[T8]],[[T8]],0x10
-; MIPS32: andi [[T8]],[[T8]],0xff
-; MIPS32: andi [[T8]],[[T8]],0x1
-; MIPS32: move [[T9]],[[T0]]
-; MIPS32: srl [[T9]],[[T9]],0x10
-; MIPS32: andi [[T9]],[[T9]],0xff
-; MIPS32: andi [[T9]],[[T9]],0x1
-; MIPS32: sll [[T8]],[[T8]],0x1f
-; MIPS32: sll [[T9]],[[T9]],0x1f
-; MIPS32: xor [[T8]],[[T8]],[[T9]]
-; MIPS32: sltu [[T8]],zero,[[T8]]
-; MIPS32: andi [[T8]],[[T8]],0xff
-; MIPS32: sll [[T8]],[[T8]],0x10
-; MIPS32: lui [[T9]],0xff00
-; MIPS32: ori [[T9]],[[T9]],0xffff
-; MIPS32: and [[T4]],[[T4]],[[T9]]
-; MIPS32: or [[T8]],[[T8]],[[T4]]
-; MIPS32: srl [[T10:.*]],a0,0x18
-; MIPS32: andi [[T10]],[[T10]],0x1
-; MIPS32: srl [[T0]],[[T0]],0x18
-; MIPS32: andi [[T0]],[[T0]],0x1
-; MIPS32: sll [[T10]],[[T10]],0x1f
-; MIPS32: sll [[T0]],[[T0]],0x1f
-; MIPS32: xor [[T10]],[[T10]],[[T0]]
-; MIPS32: sltu [[T10]],zero,[[T10]]
-; MIPS32: sll [[T10]],[[T10]],0x18
-; MIPS32: sll [[T8]],[[T8]],0x8
-; MIPS32: srl [[T8]],[[T8]],0x8
-; MIPS32: or [[T10]],[[T10]],[[T8]]
-; MIPS32: move [[T0]],a1
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: andi [[T0]],[[T0]],0x1
-; MIPS32: move [[T4]],[[T1]]
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: andi [[T4]],[[T4]],0x1
-; MIPS32: sll [[T0]],[[T0]],0x1f
-; MIPS32: sll [[T4]],[[T4]],0x1f
-; MIPS32: xor [[T0]],[[T0]],[[T4]]
-; MIPS32: sltu [[T0]],zero,[[T0]]
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: srl [[T5]],[[T5]],0x8
-; MIPS32: sll [[T5]],[[T5]],0x8
-; MIPS32: or [[T0]],[[T0]],[[T5]]
-; MIPS32: move [[T4]],a1
-; MIPS32: srl [[T4]],[[T4]],0x8
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: andi [[T4]],[[T4]],0x1
-; MIPS32: move [[T5]],[[T1]]
-; MIPS32: srl [[T5]],[[T5]],0x8
-; MIPS32: andi [[T5]],[[T5]],0xff
-; MIPS32: andi [[T5]],[[T5]],0x1
-; MIPS32: sll [[T4]],[[T4]],0x1f
-; MIPS32: sll [[T5]],[[T5]],0x1f
-; MIPS32: xor [[T4]],[[T4]],[[T5]]
-; MIPS32: sltu [[T4]],zero,[[T4]]
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: sll [[T4]],[[T4]],0x8
-; MIPS32: lui [[T5]],0xffff
-; MIPS32: ori [[T5]],[[T5]],0xff
-; MIPS32: and [[T0]],[[T0]],[[T5]]
-; MIPS32: or [[T4]],[[T4]],[[T0]]
-; MIPS32: move [[T0]],a1
-; MIPS32: srl [[T0]],[[T0]],0x10
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: andi [[T0]],[[T0]],0x1
-; MIPS32: move [[T5]],[[T1]]
-; MIPS32: srl [[T5]],[[T5]],0x10
-; MIPS32: andi [[T5]],[[T5]],0xff
-; MIPS32: andi [[T5]],[[T5]],0x1
-; MIPS32: sll [[T0]],[[T0]],0x1f
-; MIPS32: sll [[T5]],[[T5]],0x1f
-; MIPS32: xor [[T0]],[[T0]],[[T5]]
-; MIPS32: sltu [[T0]],zero,[[T0]]
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: sll [[T0]],[[T0]],0x10
-; MIPS32: lui [[T5]],0xff00
-; MIPS32: ori [[T5]],[[T5]],0xffff
-; MIPS32: and [[T4]],[[T4]],[[T5]]
-; MIPS32: or [[T0]],[[T0]],[[T4]]
-; MIPS32: srl [[T11:.*]],a1,0x18
-; MIPS32: andi [[T11]],[[T11]],0x1
-; MIPS32: srl [[T1]],[[T1]],0x18
-; MIPS32: andi [[T1]],[[T1]],0x1
-; MIPS32: sll [[T11]],[[T11]],0x1f
-; MIPS32: sll [[T1]],[[T1]],0x1f
-; MIPS32: xor [[T11]],[[T11]],[[T1]]
-; MIPS32: sltu [[T11]],zero,[[T11]]
-; MIPS32: sll [[T11]],[[T11]],0x18
-; MIPS32: sll [[T0]],[[T0]],0x8
-; MIPS32: srl [[T0]],[[T0]],0x8
-; MIPS32: or [[T11]],[[T11]],[[T0]]
-; MIPS32: move [[T0]],a2
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: andi [[T0]],[[T0]],0x1
-; MIPS32: move [[T1]],[[T2]]
-; MIPS32: andi [[T1]],[[T1]],0xff
-; MIPS32: andi [[T1]],[[T1]],0x1
-; MIPS32: sll [[T0]],[[T0]],0x1f
-; MIPS32: sll [[T1]],[[T1]],0x1f
-; MIPS32: xor [[T0]],[[T0]],[[T1]]
-; MIPS32: sltu [[T0]],zero,[[T0]]
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: srl [[T6]],[[T6]],0x8
-; MIPS32: sll [[T6]],[[T6]],0x8
-; MIPS32: or [[T0]],[[T0]],[[T6]]
-; MIPS32: move [[T1]],a2
-; MIPS32: srl [[T1]],[[T1]],0x8
-; MIPS32: andi [[T1]],[[T1]],0xff
-; MIPS32: andi [[T1]],[[T1]],0x1
-; MIPS32: move [[T4]],[[T2]]
-; MIPS32: srl [[T4]],[[T4]],0x8
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: andi [[T4]],[[T4]],0x1
-; MIPS32: sll [[T1]],[[T1]],0x1f
-; MIPS32: sll [[T4]],[[T4]],0x1f
-; MIPS32: xor [[T1]],[[T1]],[[T4]]
-; MIPS32: sltu [[T1]],zero,[[T1]]
-; MIPS32: andi [[T1]],[[T1]],0xff
-; MIPS32: sll [[T1]],[[T1]],0x8
-; MIPS32: lui [[T4]],0xffff
-; MIPS32: ori [[T4]],[[T4]],0xff
-; MIPS32: and [[T0]],[[T0]],[[T4]]
-; MIPS32: or [[T1]],[[T1]],[[T0]]
-; MIPS32: move [[T0]],a2
-; MIPS32: srl [[T0]],[[T0]],0x10
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: andi [[T0]],[[T0]],0x1
-; MIPS32: move [[T4]],[[T2]]
-; MIPS32: srl [[T4]],[[T4]],0x10
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: andi [[T4]],[[T4]],0x1
-; MIPS32: sll [[T0]],[[T0]],0x1f
-; MIPS32: sll [[T4]],[[T4]],0x1f
-; MIPS32: xor [[T0]],[[T0]],[[T4]]
-; MIPS32: sltu [[T0]],zero,[[T0]]
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: sll [[T0]],[[T0]],0x10
-; MIPS32: lui [[T4]],0xff00
-; MIPS32: ori [[T4]],[[T4]],0xffff
-; MIPS32: and [[T1]],[[T1]],[[T4]]
-; MIPS32: or [[T0]],[[T0]],[[T1]]
-; MIPS32: srl [[T12:.*]],a2,0x18
-; MIPS32: andi [[T12]],[[T12]],0x1
-; MIPS32: srl [[T2]],[[T2]],0x18
-; MIPS32: andi [[T2]],[[T2]],0x1
-; MIPS32: sll [[T12]],[[T12]],0x1f
-; MIPS32: sll [[T2]],[[T2]],0x1f
-; MIPS32: xor [[T12]],[[T12]],[[T2]]
-; MIPS32: sltu [[T12]],zero,[[T12]]
-; MIPS32: sll [[T12]],[[T12]],0x18
-; MIPS32: sll [[T0]],[[T0]],0x8
-; MIPS32: srl [[T0]],[[T0]],0x8
-; MIPS32: or [[T12]],[[T12]],[[T0]]
-; MIPS32: move [[T0]],a3
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: andi [[T0]],[[T0]],0x1
-; MIPS32: move [[T1]],[[T3]]
-; MIPS32: andi [[T1]],[[T1]],0xff
-; MIPS32: andi [[T1]],[[T1]],0x1
-; MIPS32: sll [[T0]],[[T0]],0x1f
-; MIPS32: sll [[T1]],[[T1]],0x1f
-; MIPS32: xor [[T0]],[[T0]],[[T1]]
-; MIPS32: sltu [[T0]],zero,[[T0]]
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: srl [[T7]],[[T7]],0x8
-; MIPS32: sll [[T7]],[[T7]],0x8
-; MIPS32: or [[T0]],[[T0]],[[T7]]
-; MIPS32: move [[T1]],a3
-; MIPS32: srl [[T1]],[[T1]],0x8
-; MIPS32: andi [[T1]],[[T1]],0xff
-; MIPS32: andi [[T1]],[[T1]],0x1
-; MIPS32: move [[T2]],[[T3]]
-; MIPS32: srl [[T2]],[[T2]],0x8
-; MIPS32: andi [[T2]],[[T2]],0xff
-; MIPS32: andi [[T2]],[[T2]],0x1
-; MIPS32: sll [[T1]],[[T1]],0x1f
-; MIPS32: sll [[T2]],[[T2]],0x1f
-; MIPS32: xor [[T1]],[[T1]],[[T2]]
-; MIPS32: sltu [[T1]],zero,[[T1]]
-; MIPS32: andi [[T1]],[[T1]],0xff
-; MIPS32: sll [[T1]],[[T1]],0x8
-; MIPS32: lui [[T2]],0xffff
-; MIPS32: ori [[T2]],[[T2]],0xff
-; MIPS32: and [[T0]],[[T0]],[[T2]]
-; MIPS32: or [[T1]],[[T1]],[[T0]]
-; MIPS32: move [[T0]],a3
-; MIPS32: srl [[T0]],[[T0]],0x10
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: andi [[T0]],[[T0]],0x1
-; MIPS32: move [[T2]],[[T3]]
-; MIPS32: srl [[T2]],[[T2]],0x10
-; MIPS32: andi [[T2]],[[T2]],0xff
-; MIPS32: andi [[T2]],[[T2]],0x1
-; MIPS32: sll [[T0]],[[T0]],0x1f
-; MIPS32: sll [[T2]],[[T2]],0x1f
-; MIPS32: xor [[T0]],[[T0]],[[T2]]
-; MIPS32: sltu [[T0]],zero,[[T0]]
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: sll [[T0]],[[T0]],0x10
-; MIPS32: lui [[T2]],0xff00
-; MIPS32: ori [[T2]],[[T2]],0xffff
-; MIPS32: and [[T1]],[[T1]],[[T2]]
-; MIPS32: or [[T0]],[[T0]],[[T1]]
-; MIPS32: srl [[T13:.*]],a3,0x18
-; MIPS32: andi [[T13]],[[T13]],0x1
-; MIPS32: srl [[T3]],[[T3]],0x18
-; MIPS32: andi [[T3]],[[T3]],0x1
-; MIPS32: sll [[T13]],[[T13]],0x1f
-; MIPS32: sll [[T3]],[[T3]],0x1f
-; MIPS32: xor [[T13]],[[T13]],[[T3]]
-; MIPS32: sltu [[T13]],zero,[[T13]]
-; MIPS32: sll [[T13]],[[T13]],0x18
-; MIPS32: sll [[T0]],[[T0]],0x8
-; MIPS32: srl [[T0]],[[T0]],0x8
-; MIPS32: or [[T13]],[[T13]],[[T0]]
-; MIPS32: move v0,[[T10]]
-; MIPS32: move v1,[[T11]]
-; MIPS32: move a0,[[T12]]
-; MIPS32: move a1,[[T13]]
-}
-
-define internal <16 x i1> @test_icmp_v16i1_sgt(<16 x i1> %a, <16 x i1> %b) {
-entry:
- %res = icmp sgt <16 x i1> %a, %b
- ret <16 x i1> %res
-; CHECK-LABEL: test_icmp_v16i1_sgt
-; CHECK: pcmpgtb
-
-; MIPS32-LABEL: test_icmp_v16i1_sgt
-; MIPS32: lw [[T0:.*]],
-; MIPS32: lw [[T1:.*]],
-; MIPS32: lw [[T2:.*]],
-; MIPS32: lw [[T3:.*]],
-; MIPS32: move [[T4:.*]],zero
-; MIPS32: move [[T5:.*]],zero
-; MIPS32: move [[T6:.*]],zero
-; MIPS32: move [[T7:.*]],zero
-; MIPS32: move [[T8:.*]],a0
-; MIPS32: andi [[T8]],[[T8]],0xff
-; MIPS32: andi [[T8]],[[T8]],0x1
-; MIPS32: move [[T9:.*]],[[T0]]
-; MIPS32: andi [[T9]],[[T9]],0xff
-; MIPS32: andi [[T9]],[[T9]],0x1
-; MIPS32: sll [[T8]],[[T8]],0x1f
-; MIPS32: sll [[T9]],[[T9]],0x1f
-; MIPS32: slt [[T9]],[[T9]],[[T8]]
-; MIPS32: andi [[T9]],[[T9]],0xff
-; MIPS32: srl [[T4]],[[T4]],0x8
-; MIPS32: sll [[T4]],[[T4]],0x8
-; MIPS32: or [[T9]],[[T9]],[[T4]]
-; MIPS32: move [[T4]],a0
-; MIPS32: srl [[T4]],[[T4]],0x8
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: andi [[T4]],[[T4]],0x1
-; MIPS32: move [[T8]],[[T0]]
-; MIPS32: srl [[T8]],[[T8]],0x8
-; MIPS32: andi [[T8]],[[T8]],0xff
-; MIPS32: andi [[T8]],[[T8]],0x1
-; MIPS32: sll [[T4]],[[T4]],0x1f
-; MIPS32: sll [[T8]],[[T8]],0x1f
-; MIPS32: slt [[T8]],[[T8]],[[T4]]
-; MIPS32: andi [[T8]],[[T8]],0xff
-; MIPS32: sll [[T8]],[[T8]],0x8
-; MIPS32: lui [[T4]],0xffff
-; MIPS32: ori [[T4]],[[T4]],0xff
-; MIPS32: and [[T9]],[[T9]],[[T4]]
-; MIPS32: or [[T8]],[[T8]],[[T9]]
-; MIPS32: move [[T4]],a0
-; MIPS32: srl [[T4]],[[T4]],0x10
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: andi [[T4]],[[T4]],0x1
-; MIPS32: move [[T9]],[[T0]]
-; MIPS32: srl [[T9]],[[T9]],0x10
-; MIPS32: andi [[T9]],[[T9]],0xff
-; MIPS32: andi [[T9]],[[T9]],0x1
-; MIPS32: sll [[T4]],[[T4]],0x1f
-; MIPS32: sll [[T9]],[[T9]],0x1f
-; MIPS32: slt [[T9]],[[T9]],[[T4]]
-; MIPS32: andi [[T9]],[[T9]],0xff
-; MIPS32: sll [[T9]],[[T9]],0x10
-; MIPS32: lui [[T4]],0xff00
-; MIPS32: ori [[T4]],[[T4]],0xffff
-; MIPS32: and [[T8]],[[T8]],[[T4]]
-; MIPS32: or [[T9]],[[T9]],[[T8]]
-; MIPS32: srl [[T10:.*]],a0,0x18
-; MIPS32: andi [[T10]],[[T10]],0x1
-; MIPS32: srl [[T0]],[[T0]],0x18
-; MIPS32: andi [[T0]],[[T0]],0x1
-; MIPS32: sll [[T10]],[[T10]],0x1f
-; MIPS32: sll [[T0]],[[T0]],0x1f
-; MIPS32: slt [[T0]],[[T0]],[[T10]]
-; MIPS32: sll [[T0]],[[T0]],0x18
-; MIPS32: sll [[T9]],[[T9]],0x8
-; MIPS32: srl [[T9]],[[T9]],0x8
-; MIPS32: or v0,[[T0]],[[T9]]
-; MIPS32: move [[T10]],a1
-; MIPS32: andi [[T10]],[[T10]],0xff
-; MIPS32: andi [[T10]],[[T10]],0x1
-; MIPS32: move [[T4]],[[T1]]
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: andi [[T4]],[[T4]],0x1
-; MIPS32: sll [[T10]],[[T10]],0x1f
-; MIPS32: sll [[T4]],[[T4]],0x1f
-; MIPS32: slt [[T4]],[[T4]],[[T10]]
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: srl [[T5]],[[T5]],0x8
-; MIPS32: sll [[T5]],[[T5]],0x8
-; MIPS32: or [[T4]],[[T4]],[[T5]]
-; MIPS32: move [[T10]],a1
-; MIPS32: srl [[T10]],[[T10]],0x8
-; MIPS32: andi [[T10]],[[T10]],0xff
-; MIPS32: andi [[T10]],[[T10]],0x1
-; MIPS32: move [[T5]],[[T1]]
-; MIPS32: srl [[T5]],[[T5]],0x8
-; MIPS32: andi [[T5]],[[T5]],0xff
-; MIPS32: andi [[T5]],[[T5]],0x1
-; MIPS32: sll [[T10]],[[T10]],0x1f
-; MIPS32: sll [[T5]],[[T5]],0x1f
-; MIPS32: slt [[T5]],[[T5]],[[T10]]
-; MIPS32: andi [[T5]],[[T5]],0xff
-; MIPS32: sll [[T5]],[[T5]],0x8
-; MIPS32: lui [[T10]],0xffff
-; MIPS32: ori [[T10]],[[T10]],0xff
-; MIPS32: and [[T4]],[[T4]],[[T10]]
-; MIPS32: or [[T5]],[[T5]],[[T4]]
-; MIPS32: move [[T10]],a1
-; MIPS32: srl [[T10]],[[T10]],0x10
-; MIPS32: andi [[T10]],[[T10]],0xff
-; MIPS32: andi [[T10]],[[T10]],0x1
-; MIPS32: move [[T4]],[[T1]]
-; MIPS32: srl [[T4]],[[T4]],0x10
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: andi [[T4]],[[T4]],0x1
-; MIPS32: sll [[T10]],[[T10]],0x1f
-; MIPS32: sll [[T4]],[[T4]],0x1f
-; MIPS32: slt [[T4]],[[T4]],[[T10]]
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: sll [[T4]],[[T4]],0x10
-; MIPS32: lui [[T10]],0xff00
-; MIPS32: ori [[T10]],[[T10]],0xffff
-; MIPS32: and [[T5]],[[T5]],[[T10]]
-; MIPS32: or [[T4]],[[T4]],[[T5]]
-; MIPS32: srl [[T11:.*]],a1,0x18
-; MIPS32: andi [[T11]],[[T11]],0x1
-; MIPS32: srl [[T1]],[[T1]],0x18
-; MIPS32: andi [[T1]],[[T1]],0x1
-; MIPS32: sll [[T11]],[[T11]],0x1f
-; MIPS32: sll [[T1]],[[T1]],0x1f
-; MIPS32: slt [[T1]],[[T1]],[[T11]]
-; MIPS32: sll [[T1]],[[T1]],0x18
-; MIPS32: sll [[T4]],[[T4]],0x8
-; MIPS32: srl [[T4]],[[T4]],0x8
-; MIPS32: or v1,[[T1]],[[T4]]
-; MIPS32: move [[T10]],a2
-; MIPS32: andi [[T10]],[[T10]],0xff
-; MIPS32: andi [[T10]],[[T10]],0x1
-; MIPS32: move [[T11]],[[T2]]
-; MIPS32: andi [[T11]],[[T11]],0xff
-; MIPS32: andi [[T11]],[[T11]],0x1
-; MIPS32: sll [[T10]],[[T10]],0x1f
-; MIPS32: sll [[T11]],[[T11]],0x1f
-; MIPS32: slt [[T11]],[[T11]],[[T10]]
-; MIPS32: andi [[T11]],[[T11]],0xff
-; MIPS32: srl [[T6]],[[T6]],0x8
-; MIPS32: sll [[T6]],[[T6]],0x8
-; MIPS32: or [[T11]],[[T11]],[[T6]]
-; MIPS32: move [[T10]],a2
-; MIPS32: srl [[T10]],[[T10]],0x8
-; MIPS32: andi [[T10]],[[T10]],0xff
-; MIPS32: andi [[T10]],[[T10]],0x1
-; MIPS32: move [[T4]],[[T2]]
-; MIPS32: srl [[T4]],[[T4]],0x8
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: andi [[T4]],[[T4]],0x1
-; MIPS32: sll [[T10]],[[T10]],0x1f
-; MIPS32: sll [[T4]],[[T4]],0x1f
-; MIPS32: slt [[T4]],[[T4]],[[T10]]
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: sll [[T4]],[[T4]],0x8
-; MIPS32: lui [[T10]],0xffff
-; MIPS32: ori [[T10]],[[T10]],0xff
-; MIPS32: and [[T11]],[[T11]],[[T10]]
-; MIPS32: or [[T4]],[[T4]],[[T11]]
-; MIPS32: move [[T10]],a2
-; MIPS32: srl [[T10]],[[T10]],0x10
-; MIPS32: andi [[T10]],[[T10]],0xff
-; MIPS32: andi [[T10]],[[T10]],0x1
-; MIPS32: move [[T11]],[[T2]]
-; MIPS32: srl [[T11]],[[T11]],0x10
-; MIPS32: andi [[T11]],[[T11]],0xff
-; MIPS32: andi [[T11]],[[T11]],0x1
-; MIPS32: sll [[T10]],[[T10]],0x1f
-; MIPS32: sll [[T11]],[[T11]],0x1f
-; MIPS32: slt [[T11]],[[T11]],[[T10]]
-; MIPS32: andi [[T11]],[[T11]],0xff
-; MIPS32: sll [[T11]],[[T11]],0x10
-; MIPS32: lui [[T10]],0xff00
-; MIPS32: ori [[T10]],[[T10]],0xffff
-; MIPS32: and [[T4]],[[T4]],[[T10]]
-; MIPS32: or [[T11]],[[T11]],[[T4]]
-; MIPS32: srl [[T12:.*]],a2,0x18
-; MIPS32: andi [[T12]],[[T12]],0x1
-; MIPS32: srl [[T2]],[[T2]],0x18
-; MIPS32: andi [[T2]],[[T2]],0x1
-; MIPS32: sll [[T12]],[[T12]],0x1f
-; MIPS32: sll [[T2]],[[T2]],0x1f
-; MIPS32: slt [[T2]],[[T2]],[[T12]]
-; MIPS32: sll [[T2]],[[T2]],0x18
-; MIPS32: sll [[T11]],[[T11]],0x8
-; MIPS32: srl [[T11]],[[T11]],0x8
-; MIPS32: or [[T2]],[[T2]],[[T11]]
-; MIPS32: move [[T10]],a3
-; MIPS32: andi [[T10]],[[T10]],0xff
-; MIPS32: andi [[T10]],[[T10]],0x1
-; MIPS32: move [[T11]],[[T3]]
-; MIPS32: andi [[T11]],[[T11]],0xff
-; MIPS32: andi [[T11]],[[T11]],0x1
-; MIPS32: sll [[T10]],[[T10]],0x1f
-; MIPS32: sll [[T11]],[[T11]],0x1f
-; MIPS32: slt [[T11]],[[T11]],[[T10]]
-; MIPS32: andi [[T11]],[[T11]],0xff
-; MIPS32: srl [[T7]],[[T7]],0x8
-; MIPS32: sll [[T7]],[[T7]],0x8
-; MIPS32: or [[T11]],[[T11]],[[T7]]
-; MIPS32: move [[T10]],a3
-; MIPS32: srl [[T10]],[[T10]],0x8
-; MIPS32: andi [[T10]],[[T10]],0xff
-; MIPS32: andi [[T10]],[[T10]],0x1
-; MIPS32: move [[T12]],[[T3]]
-; MIPS32: srl [[T12]],[[T12]],0x8
-; MIPS32: andi [[T12]],[[T12]],0xff
-; MIPS32: andi [[T12]],[[T12]],0x1
-; MIPS32: sll [[T10]],[[T10]],0x1f
-; MIPS32: sll [[T12]],[[T12]],0x1f
-; MIPS32: slt [[T12]],[[T12]],[[T10]]
-; MIPS32: andi [[T12]],[[T12]],0xff
-; MIPS32: sll [[T12]],[[T12]],0x8
-; MIPS32: lui [[T10]],0xffff
-; MIPS32: ori [[T10]],[[T10]],0xff
-; MIPS32: and [[T11]],[[T11]],[[T10]]
-; MIPS32: or [[T12]],[[T12]],[[T11]]
-; MIPS32: move [[T10]],a3
-; MIPS32: srl [[T10]],[[T10]],0x10
-; MIPS32: andi [[T10]],[[T10]],0xff
-; MIPS32: andi [[T10]],[[T10]],0x1
-; MIPS32: move [[T11]],[[T3]]
-; MIPS32: srl [[T11]],[[T11]],0x10
-; MIPS32: andi [[T11]],[[T11]],0xff
-; MIPS32: andi [[T11]],[[T11]],0x1
-; MIPS32: sll [[T10]],[[T10]],0x1f
-; MIPS32: sll [[T11]],[[T11]],0x1f
-; MIPS32: slt [[T11]],[[T11]],[[T10]]
-; MIPS32: andi [[T11]],[[T11]],0xff
-; MIPS32: sll [[T11]],[[T11]],0x10
-; MIPS32: lui [[T10]],0xff00
-; MIPS32: ori [[T10]],[[T10]],0xffff
-; MIPS32: and [[T12]],[[T12]],[[T10]]
-; MIPS32: or [[T11]],[[T11]],[[T12]]
-; MIPS32: srl [[T13:.*]],a3,0x18
-; MIPS32: andi [[T13]],[[T13]],0x1
-; MIPS32: srl [[T3]],[[T3]],0x18
-; MIPS32: andi [[T3]],[[T3]],0x1
-; MIPS32: sll [[T13]],[[T13]],0x1f
-; MIPS32: sll [[T3]],[[T3]],0x1f
-; MIPS32: slt [[T3]],[[T3]],[[T13]]
-; MIPS32: sll [[T3]],[[T3]],0x18
-; MIPS32: sll [[T11]],[[T11]],0x8
-; MIPS32: srl [[T11]],[[T11]],0x8
-; MIPS32: or [[T3]],[[T3]],[[T11]]
-; MIPS32: move a0,[[T2]]
-; MIPS32: move a1,[[T3]]
-}
-
-define internal <16 x i1> @test_icmp_v16i1_sle(<16 x i1> %a, <16 x i1> %b) {
-entry:
- %res = icmp sle <16 x i1> %a, %b
- ret <16 x i1> %res
-; CHECK-LABEL: test_icmp_v16i1_sle
-; CHECK: pcmpgtb
-; CHECK: pxor
-
-; MIPS32-LABEL: test_icmp_v16i1_sle
-; MIPS32: lw [[T0:.*]],
-; MIPS32: lw [[T1:.*]],
-; MIPS32: lw [[T2:.*]],
-; MIPS32: lw [[T3:.*]],
-; MIPS32: move [[T4:.*]],zero
-; MIPS32: move [[T5:.*]],zero
-; MIPS32: move [[T6:.*]],zero
-; MIPS32: move [[T7:.*]],zero
-; MIPS32: move [[T8:.*]],a0
-; MIPS32: andi [[T8]],[[T8]],0xff
-; MIPS32: andi [[T8]],[[T8]],0x1
-; MIPS32: move [[T9:.*]],[[T0]]
-; MIPS32: andi [[T9]],[[T9]],0xff
-; MIPS32: andi [[T9]],[[T9]],0x1
-; MIPS32: sll [[T8]],[[T8]],0x1f
-; MIPS32: sll [[T9]],[[T9]],0x1f
-; MIPS32: slt [[T9]],[[T9]],[[T8]]
-; MIPS32: xori [[T9]],[[T9]],0x1
-; MIPS32: andi [[T9]],[[T9]],0xff
-; MIPS32: srl [[T4]],[[T4]],0x8
-; MIPS32: sll [[T4]],[[T4]],0x8
-; MIPS32: or [[T9]],[[T9]],[[T4]]
-; MIPS32: move [[T4]],a0
-; MIPS32: srl [[T4]],[[T4]],0x8
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: andi [[T4]],[[T4]],0x1
-; MIPS32: move [[T8]],[[T0]]
-; MIPS32: srl [[T8]],[[T8]],0x8
-; MIPS32: andi [[T8]],[[T8]],0xff
-; MIPS32: andi [[T8]],[[T8]],0x1
-; MIPS32: sll [[T4]],[[T4]],0x1f
-; MIPS32: sll [[T8]],[[T8]],0x1f
-; MIPS32: slt [[T8]],[[T8]],[[T4]]
-; MIPS32: xori [[T8]],[[T8]],0x1
-; MIPS32: andi [[T8]],[[T8]],0xff
-; MIPS32: sll [[T8]],[[T8]],0x8
-; MIPS32: lui [[T4]],0xffff
-; MIPS32: ori [[T4]],[[T4]],0xff
-; MIPS32: and [[T9]],[[T9]],[[T4]]
-; MIPS32: or [[T8]],[[T8]],[[T9]]
-; MIPS32: move [[T4]],a0
-; MIPS32: srl [[T4]],[[T4]],0x10
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: andi [[T4]],[[T4]],0x1
-; MIPS32: move [[T9]],[[T0]]
-; MIPS32: srl [[T9]],[[T9]],0x10
-; MIPS32: andi [[T9]],[[T9]],0xff
-; MIPS32: andi [[T9]],[[T9]],0x1
-; MIPS32: sll [[T4]],[[T4]],0x1f
-; MIPS32: sll [[T9]],[[T9]],0x1f
-; MIPS32: slt [[T9]],[[T9]],[[T4]]
-; MIPS32: xori [[T9]],[[T9]],0x1
-; MIPS32: andi [[T9]],[[T9]],0xff
-; MIPS32: sll [[T9]],[[T9]],0x10
-; MIPS32: lui [[T4]],0xff00
-; MIPS32: ori [[T4]],[[T4]],0xffff
-; MIPS32: and [[T8]],[[T8]],[[T4]]
-; MIPS32: or [[T9]],[[T9]],[[T8]]
-; MIPS32: srl [[T10:.*]],a0,0x18
-; MIPS32: andi [[T10]],[[T10]],0x1
-; MIPS32: srl [[T0]],[[T0]],0x18
-; MIPS32: andi [[T0]],[[T0]],0x1
-; MIPS32: sll [[T10]],[[T10]],0x1f
-; MIPS32: sll [[T0]],[[T0]],0x1f
-; MIPS32: slt [[T0]],[[T0]],[[T10]]
-; MIPS32: xori [[T0]],[[T0]],0x1
-; MIPS32: sll [[T0]],[[T0]],0x18
-; MIPS32: sll [[T9]],[[T9]],0x8
-; MIPS32: srl [[T9]],[[T9]],0x8
-; MIPS32: or v0,[[T0]],[[T9]]
-; MIPS32: move [[T10]],a1
-; MIPS32: andi [[T10]],[[T10]],0xff
-; MIPS32: andi [[T10]],[[T10]],0x1
-; MIPS32: move [[T4]],[[T1]]
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: andi [[T4]],[[T4]],0x1
-; MIPS32: sll [[T10]],[[T10]],0x1f
-; MIPS32: sll [[T4]],[[T4]],0x1f
-; MIPS32: slt [[T4]],[[T4]],[[T10]]
-; MIPS32: xori [[T4]],[[T4]],0x1
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: srl [[T5]],[[T5]],0x8
-; MIPS32: sll [[T5]],[[T5]],0x8
-; MIPS32: or [[T4]],[[T4]],[[T5]]
-; MIPS32: move [[T10]],a1
-; MIPS32: srl [[T10]],[[T10]],0x8
-; MIPS32: andi [[T10]],[[T10]],0xff
-; MIPS32: andi [[T10]],[[T10]],0x1
-; MIPS32: move [[T5]],[[T1]]
-; MIPS32: srl [[T5]],[[T5]],0x8
-; MIPS32: andi [[T5]],[[T5]],0xff
-; MIPS32: andi [[T5]],[[T5]],0x1
-; MIPS32: sll [[T10]],[[T10]],0x1f
-; MIPS32: sll [[T5]],[[T5]],0x1f
-; MIPS32: slt [[T5]],[[T5]],[[T10]]
-; MIPS32: xori [[T5]],[[T5]],0x1
-; MIPS32: andi [[T5]],[[T5]],0xff
-; MIPS32: sll [[T5]],[[T5]],0x8
-; MIPS32: lui [[T10]],0xffff
-; MIPS32: ori [[T10]],[[T10]],0xff
-; MIPS32: and [[T4]],[[T4]],[[T10]]
-; MIPS32: or [[T5]],[[T5]],[[T4]]
-; MIPS32: move [[T10]],a1
-; MIPS32: srl [[T10]],[[T10]],0x10
-; MIPS32: andi [[T10]],[[T10]],0xff
-; MIPS32: andi [[T10]],[[T10]],0x1
-; MIPS32: move [[T4]],[[T1]]
-; MIPS32: srl [[T4]],[[T4]],0x10
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: andi [[T4]],[[T4]],0x1
-; MIPS32: sll [[T10]],[[T10]],0x1f
-; MIPS32: sll [[T4]],[[T4]],0x1f
-; MIPS32: slt [[T4]],[[T4]],[[T10]]
-; MIPS32: xori [[T4]],[[T4]],0x1
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: sll [[T4]],[[T4]],0x10
-; MIPS32: lui [[T10]],0xff00
-; MIPS32: ori [[T10]],[[T10]],0xffff
-; MIPS32: and [[T5]],[[T5]],[[T10]]
-; MIPS32: or [[T4]],[[T4]],[[T5]]
-; MIPS32: srl [[T11:.*]],a1,0x18
-; MIPS32: andi [[T11]],[[T11]],0x1
-; MIPS32: srl [[T1]],[[T1]],0x18
-; MIPS32: andi [[T1]],[[T1]],0x1
-; MIPS32: sll [[T11]],[[T11]],0x1f
-; MIPS32: sll [[T1]],[[T1]],0x1f
-; MIPS32: slt [[T1]],[[T1]],[[T11]]
-; MIPS32: xori [[T1]],[[T1]],0x1
-; MIPS32: sll [[T1]],[[T1]],0x18
-; MIPS32: sll [[T4]],[[T4]],0x8
-; MIPS32: srl [[T4]],[[T4]],0x8
-; MIPS32: or v1,[[T1]],[[T4]]
-; MIPS32: move [[T10]],a2
-; MIPS32: andi [[T10]],[[T10]],0xff
-; MIPS32: andi [[T10]],[[T10]],0x1
-; MIPS32: move [[T11]],[[T2]]
-; MIPS32: andi [[T11]],[[T11]],0xff
-; MIPS32: andi [[T11]],[[T11]],0x1
-; MIPS32: sll [[T10]],[[T10]],0x1f
-; MIPS32: sll [[T11]],[[T11]],0x1f
-; MIPS32: slt [[T11]],[[T11]],[[T10]]
-; MIPS32: xori [[T11]],[[T11]],0x1
-; MIPS32: andi [[T11]],[[T11]],0xff
-; MIPS32: srl [[T6]],[[T6]],0x8
-; MIPS32: sll [[T6]],[[T6]],0x8
-; MIPS32: or [[T11]],[[T11]],[[T6]]
-; MIPS32: move [[T10]],a2
-; MIPS32: srl [[T10]],[[T10]],0x8
-; MIPS32: andi [[T10]],[[T10]],0xff
-; MIPS32: andi [[T10]],[[T10]],0x1
-; MIPS32: move [[T4]],[[T2]]
-; MIPS32: srl [[T4]],[[T4]],0x8
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: andi [[T4]],[[T4]],0x1
-; MIPS32: sll [[T10]],[[T10]],0x1f
-; MIPS32: sll [[T4]],[[T4]],0x1f
-; MIPS32: slt [[T4]],[[T4]],[[T10]]
-; MIPS32: xori [[T4]],[[T4]],0x1
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: sll [[T4]],[[T4]],0x8
-; MIPS32: lui [[T10]],0xffff
-; MIPS32: ori [[T10]],[[T10]],0xff
-; MIPS32: and [[T11]],[[T11]],[[T10]]
-; MIPS32: or [[T4]],[[T4]],[[T11]]
-; MIPS32: move [[T10]],a2
-; MIPS32: srl [[T10]],[[T10]],0x10
-; MIPS32: andi [[T10]],[[T10]],0xff
-; MIPS32: andi [[T10]],[[T10]],0x1
-; MIPS32: move [[T11]],[[T2]]
-; MIPS32: srl [[T11]],[[T11]],0x10
-; MIPS32: andi [[T11]],[[T11]],0xff
-; MIPS32: andi [[T11]],[[T11]],0x1
-; MIPS32: sll [[T10]],[[T10]],0x1f
-; MIPS32: sll [[T11]],[[T11]],0x1f
-; MIPS32: slt [[T11]],[[T11]],[[T10]]
-; MIPS32: xori [[T11]],[[T11]],0x1
-; MIPS32: andi [[T11]],[[T11]],0xff
-; MIPS32: sll [[T11]],[[T11]],0x10
-; MIPS32: lui [[T10]],0xff00
-; MIPS32: ori [[T10]],[[T10]],0xffff
-; MIPS32: and [[T4]],[[T4]],[[T10]]
-; MIPS32: or [[T11]],[[T11]],[[T4]]
-; MIPS32: srl [[T12:.*]],a2,0x18
-; MIPS32: andi [[T12]],[[T12]],0x1
-; MIPS32: srl [[T2]],[[T2]],0x18
-; MIPS32: andi [[T2]],[[T2]],0x1
-; MIPS32: sll [[T12]],[[T12]],0x1f
-; MIPS32: sll [[T2]],[[T2]],0x1f
-; MIPS32: slt [[T2]],[[T2]],[[T12]]
-; MIPS32: xori [[T2]],[[T2]],0x1
-; MIPS32: sll [[T2]],[[T2]],0x18
-; MIPS32: sll [[T11]],[[T11]],0x8
-; MIPS32: srl [[T11]],[[T11]],0x8
-; MIPS32: or [[T2]],[[T2]],[[T11]]
-; MIPS32: move [[T10]],a3
-; MIPS32: andi [[T10]],[[T10]],0xff
-; MIPS32: andi [[T10]],[[T10]],0x1
-; MIPS32: move [[T11]],[[T3]]
-; MIPS32: andi [[T11]],[[T11]],0xff
-; MIPS32: andi [[T11]],[[T11]],0x1
-; MIPS32: sll [[T10]],[[T10]],0x1f
-; MIPS32: sll [[T11]],[[T11]],0x1f
-; MIPS32: slt [[T11]],[[T11]],[[T10]]
-; MIPS32: xori [[T11]],[[T11]],0x1
-; MIPS32: andi [[T11]],[[T11]],0xff
-; MIPS32: srl [[T7]],[[T7]],0x8
-; MIPS32: sll [[T7]],[[T7]],0x8
-; MIPS32: or [[T11]],[[T11]],[[T7]]
-; MIPS32: move [[T10]],a3
-; MIPS32: srl [[T10]],[[T10]],0x8
-; MIPS32: andi [[T10]],[[T10]],0xff
-; MIPS32: andi [[T10]],[[T10]],0x1
-; MIPS32: move [[T12]],[[T3]]
-; MIPS32: srl [[T12]],[[T12]],0x8
-; MIPS32: andi [[T12]],[[T12]],0xff
-; MIPS32: andi [[T12]],[[T12]],0x1
-; MIPS32: sll [[T10]],[[T10]],0x1f
-; MIPS32: sll [[T12]],[[T12]],0x1f
-; MIPS32: slt [[T12]],[[T12]],[[T10]]
-; MIPS32: xori [[T12]],[[T12]],0x1
-; MIPS32: andi [[T12]],[[T12]],0xff
-; MIPS32: sll [[T12]],[[T12]],0x8
-; MIPS32: lui [[T10]],0xffff
-; MIPS32: ori [[T10]],[[T10]],0xff
-; MIPS32: and [[T11]],[[T11]],[[T10]]
-; MIPS32: or [[T12]],[[T12]],[[T11]]
-; MIPS32: move [[T10]],a3
-; MIPS32: srl [[T10]],[[T10]],0x10
-; MIPS32: andi [[T10]],[[T10]],0xff
-; MIPS32: andi [[T10]],[[T10]],0x1
-; MIPS32: move [[T11]],[[T3]]
-; MIPS32: srl [[T11]],[[T11]],0x10
-; MIPS32: andi [[T11]],[[T11]],0xff
-; MIPS32: andi [[T11]],[[T11]],0x1
-; MIPS32: sll [[T10]],[[T10]],0x1f
-; MIPS32: sll [[T11]],[[T11]],0x1f
-; MIPS32: slt [[T11]],[[T11]],[[T10]]
-; MIPS32: xori [[T11]],[[T11]],0x1
-; MIPS32: andi [[T11]],[[T11]],0xff
-; MIPS32: sll [[T11]],[[T11]],0x10
-; MIPS32: lui [[T10]],0xff00
-; MIPS32: ori [[T10]],[[T10]],0xffff
-; MIPS32: and [[T12]],[[T12]],[[T10]]
-; MIPS32: or [[T11]],[[T11]],[[T12]]
-; MIPS32: srl [[T13:.*]],a3,0x18
-; MIPS32: andi [[T13]],[[T13]],0x1
-; MIPS32: srl [[T3]],[[T3]],0x18
-; MIPS32: andi [[T3]],[[T3]],0x1
-; MIPS32: sll [[T13]],[[T13]],0x1f
-; MIPS32: sll [[T3]],[[T3]],0x1f
-; MIPS32: slt [[T3]],[[T3]],[[T13]]
-; MIPS32: xori [[T3]],[[T3]],0x1
-; MIPS32: sll [[T3]],[[T3]],0x18
-; MIPS32: sll [[T11]],[[T11]],0x8
-; MIPS32: srl [[T11]],[[T11]],0x8
-; MIPS32: or [[T3]],[[T3]],[[T11]]
-; MIPS32: move a0,[[T2]]
-; MIPS32: move a1,[[T3]]
-}
-
-define internal <16 x i1> @test_icmp_v16i1_slt(<16 x i1> %a, <16 x i1> %b) {
-entry:
- %res = icmp slt <16 x i1> %a, %b
- ret <16 x i1> %res
-; CHECK-LABEL: test_icmp_v16i1_slt
-; CHECK: pcmpgtb
-
-; MIPS32-LABEL: test_icmp_v16i1_slt
-; MIPS32: lw [[T0:.*]],
-; MIPS32: lw [[T1:.*]],
-; MIPS32: lw [[T2:.*]],
-; MIPS32: lw [[T3:.*]],
-; MIPS32: move [[T4:.*]],zero
-; MIPS32: move [[T5:.*]],zero
-; MIPS32: move [[T6:.*]],zero
-; MIPS32: move [[T7:.*]],zero
-; MIPS32: move [[T8:.*]],a0
-; MIPS32: andi [[T8]],[[T8]],0xff
-; MIPS32: andi [[T8]],[[T8]],0x1
-; MIPS32: move [[T9:.*]],[[T0]]
-; MIPS32: andi [[T9]],[[T9]],0xff
-; MIPS32: andi [[T9]],[[T9]],0x1
-; MIPS32: sll [[T8]],[[T8]],0x1f
-; MIPS32: sll [[T9]],[[T9]],0x1f
-; MIPS32: slt [[T8]],[[T8]],[[T9]]
-; MIPS32: andi [[T8]],[[T8]],0xff
-; MIPS32: srl [[T4]],[[T4]],0x8
-; MIPS32: sll [[T4]],[[T4]],0x8
-; MIPS32: or [[T8]],[[T8]],[[T4]]
-; MIPS32: move [[T4]],a0
-; MIPS32: srl [[T4]],[[T4]],0x8
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: andi [[T4]],[[T4]],0x1
-; MIPS32: move [[T9]],[[T0]]
-; MIPS32: srl [[T9]],[[T9]],0x8
-; MIPS32: andi [[T9]],[[T9]],0xff
-; MIPS32: andi [[T9]],[[T9]],0x1
-; MIPS32: sll [[T4]],[[T4]],0x1f
-; MIPS32: sll [[T9]],[[T9]],0x1f
-; MIPS32: slt [[T4]],[[T4]],[[T9]]
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: sll [[T4]],[[T4]],0x8
-; MIPS32: lui [[T9]],0xffff
-; MIPS32: ori [[T9]],[[T9]],0xff
-; MIPS32: and [[T8]],[[T8]],[[T9]]
-; MIPS32: or [[T4]],[[T4]],[[T8]]
-; MIPS32: move [[T8]],a0
-; MIPS32: srl [[T8]],[[T8]],0x10
-; MIPS32: andi [[T8]],[[T8]],0xff
-; MIPS32: andi [[T8]],[[T8]],0x1
-; MIPS32: move [[T9]],[[T0]]
-; MIPS32: srl [[T9]],[[T9]],0x10
-; MIPS32: andi [[T9]],[[T9]],0xff
-; MIPS32: andi [[T9]],[[T9]],0x1
-; MIPS32: sll [[T8]],[[T8]],0x1f
-; MIPS32: sll [[T9]],[[T9]],0x1f
-; MIPS32: slt [[T8]],[[T8]],[[T9]]
-; MIPS32: andi [[T8]],[[T8]],0xff
-; MIPS32: sll [[T8]],[[T8]],0x10
-; MIPS32: lui [[T9]],0xff00
-; MIPS32: ori [[T9]],[[T9]],0xffff
-; MIPS32: and [[T4]],[[T4]],[[T9]]
-; MIPS32: or [[T8]],[[T8]],[[T4]]
-; MIPS32: srl [[T10:.*]],a0,0x18
-; MIPS32: andi [[T10]],[[T10]],0x1
-; MIPS32: srl [[T0]],[[T0]],0x18
-; MIPS32: andi [[T0]],[[T0]],0x1
-; MIPS32: sll [[T10]],[[T10]],0x1f
-; MIPS32: sll [[T0]],[[T0]],0x1f
-; MIPS32: slt [[T10]],[[T10]],[[T0]]
-; MIPS32: sll [[T10]],[[T10]],0x18
-; MIPS32: sll [[T8]],[[T8]],0x8
-; MIPS32: srl [[T8]],[[T8]],0x8
-; MIPS32: or [[T10]],[[T10]],[[T8]]
-; MIPS32: move [[T0]],a1
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: andi [[T0]],[[T0]],0x1
-; MIPS32: move [[T4]],[[T1]]
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: andi [[T4]],[[T4]],0x1
-; MIPS32: sll [[T0]],[[T0]],0x1f
-; MIPS32: sll [[T4]],[[T4]],0x1f
-; MIPS32: slt [[T0]],[[T0]],[[T4]]
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: srl [[T5]],[[T5]],0x8
-; MIPS32: sll [[T5]],[[T5]],0x8
-; MIPS32: or [[T0]],[[T0]],[[T5]]
-; MIPS32: move [[T4]],a1
-; MIPS32: srl [[T4]],[[T4]],0x8
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: andi [[T4]],[[T4]],0x1
-; MIPS32: move [[T5]],[[T1]]
-; MIPS32: srl [[T5]],[[T5]],0x8
-; MIPS32: andi [[T5]],[[T5]],0xff
-; MIPS32: andi [[T5]],[[T5]],0x1
-; MIPS32: sll [[T4]],[[T4]],0x1f
-; MIPS32: sll [[T5]],[[T5]],0x1f
-; MIPS32: slt [[T4]],[[T4]],[[T5]]
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: sll [[T4]],[[T4]],0x8
-; MIPS32: lui [[T5]],0xffff
-; MIPS32: ori [[T5]],[[T5]],0xff
-; MIPS32: and [[T0]],[[T0]],[[T5]]
-; MIPS32: or [[T4]],[[T4]],[[T0]]
-; MIPS32: move [[T0]],a1
-; MIPS32: srl [[T0]],[[T0]],0x10
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: andi [[T0]],[[T0]],0x1
-; MIPS32: move [[T5]],[[T1]]
-; MIPS32: srl [[T5]],[[T5]],0x10
-; MIPS32: andi [[T5]],[[T5]],0xff
-; MIPS32: andi [[T5]],[[T5]],0x1
-; MIPS32: sll [[T0]],[[T0]],0x1f
-; MIPS32: sll [[T5]],[[T5]],0x1f
-; MIPS32: slt [[T0]],[[T0]],[[T5]]
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: sll [[T0]],[[T0]],0x10
-; MIPS32: lui [[T5]],0xff00
-; MIPS32: ori [[T5]],[[T5]],0xffff
-; MIPS32: and [[T4]],[[T4]],[[T5]]
-; MIPS32: or [[T0]],[[T0]],[[T4]]
-; MIPS32: srl [[T11:.*]],a1,0x18
-; MIPS32: andi [[T11]],[[T11]],0x1
-; MIPS32: srl [[T1]],[[T1]],0x18
-; MIPS32: andi [[T1]],[[T1]],0x1
-; MIPS32: sll [[T11]],[[T11]],0x1f
-; MIPS32: sll [[T1]],[[T1]],0x1f
-; MIPS32: slt [[T11]],[[T11]],[[T1]]
-; MIPS32: sll [[T11]],[[T11]],0x18
-; MIPS32: sll [[T0]],[[T0]],0x8
-; MIPS32: srl [[T0]],[[T0]],0x8
-; MIPS32: or [[T11]],[[T11]],[[T0]]
-; MIPS32: move [[T0]],a2
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: andi [[T0]],[[T0]],0x1
-; MIPS32: move [[T1]],[[T2]]
-; MIPS32: andi [[T1]],[[T1]],0xff
-; MIPS32: andi [[T1]],[[T1]],0x1
-; MIPS32: sll [[T0]],[[T0]],0x1f
-; MIPS32: sll [[T1]],[[T1]],0x1f
-; MIPS32: slt [[T0]],[[T0]],[[T1]]
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: srl [[T6]],[[T6]],0x8
-; MIPS32: sll [[T6]],[[T6]],0x8
-; MIPS32: or [[T0]],[[T0]],[[T6]]
-; MIPS32: move [[T1]],a2
-; MIPS32: srl [[T1]],[[T1]],0x8
-; MIPS32: andi [[T1]],[[T1]],0xff
-; MIPS32: andi [[T1]],[[T1]],0x1
-; MIPS32: move [[T4]],[[T2]]
-; MIPS32: srl [[T4]],[[T4]],0x8
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: andi [[T4]],[[T4]],0x1
-; MIPS32: sll [[T1]],[[T1]],0x1f
-; MIPS32: sll [[T4]],[[T4]],0x1f
-; MIPS32: slt [[T1]],[[T1]],[[T4]]
-; MIPS32: andi [[T1]],[[T1]],0xff
-; MIPS32: sll [[T1]],[[T1]],0x8
-; MIPS32: lui [[T4]],0xffff
-; MIPS32: ori [[T4]],[[T4]],0xff
-; MIPS32: and [[T0]],[[T0]],[[T4]]
-; MIPS32: or [[T1]],[[T1]],[[T0]]
-; MIPS32: move [[T0]],a2
-; MIPS32: srl [[T0]],[[T0]],0x10
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: andi [[T0]],[[T0]],0x1
-; MIPS32: move [[T4]],[[T2]]
-; MIPS32: srl [[T4]],[[T4]],0x10
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: andi [[T4]],[[T4]],0x1
-; MIPS32: sll [[T0]],[[T0]],0x1f
-; MIPS32: sll [[T4]],[[T4]],0x1f
-; MIPS32: slt [[T0]],[[T0]],[[T4]]
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: sll [[T0]],[[T0]],0x10
-; MIPS32: lui [[T4]],0xff00
-; MIPS32: ori [[T4]],[[T4]],0xffff
-; MIPS32: and [[T1]],[[T1]],[[T4]]
-; MIPS32: or [[T0]],[[T0]],[[T1]]
-; MIPS32: srl [[T12:.*]],a2,0x18
-; MIPS32: andi [[T12]],[[T12]],0x1
-; MIPS32: srl [[T2]],[[T2]],0x18
-; MIPS32: andi [[T2]],[[T2]],0x1
-; MIPS32: sll [[T12]],[[T12]],0x1f
-; MIPS32: sll [[T2]],[[T2]],0x1f
-; MIPS32: slt [[T12]],[[T12]],[[T2]]
-; MIPS32: sll [[T12]],[[T12]],0x18
-; MIPS32: sll [[T0]],[[T0]],0x8
-; MIPS32: srl [[T0]],[[T0]],0x8
-; MIPS32: or [[T12]],[[T12]],[[T0]]
-; MIPS32: move [[T0]],a3
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: andi [[T0]],[[T0]],0x1
-; MIPS32: move [[T1]],[[T3]]
-; MIPS32: andi [[T1]],[[T1]],0xff
-; MIPS32: andi [[T1]],[[T1]],0x1
-; MIPS32: sll [[T0]],[[T0]],0x1f
-; MIPS32: sll [[T1]],[[T1]],0x1f
-; MIPS32: slt [[T0]],[[T0]],[[T1]]
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: srl [[T7]],[[T7]],0x8
-; MIPS32: sll [[T7]],[[T7]],0x8
-; MIPS32: or [[T0]],[[T0]],[[T7]]
-; MIPS32: move [[T1]],a3
-; MIPS32: srl [[T1]],[[T1]],0x8
-; MIPS32: andi [[T1]],[[T1]],0xff
-; MIPS32: andi [[T1]],[[T1]],0x1
-; MIPS32: move [[T2]],[[T3]]
-; MIPS32: srl [[T2]],[[T2]],0x8
-; MIPS32: andi [[T2]],[[T2]],0xff
-; MIPS32: andi [[T2]],[[T2]],0x1
-; MIPS32: sll [[T1]],[[T1]],0x1f
-; MIPS32: sll [[T2]],[[T2]],0x1f
-; MIPS32: slt [[T1]],[[T1]],[[T2]]
-; MIPS32: andi [[T1]],[[T1]],0xff
-; MIPS32: sll [[T1]],[[T1]],0x8
-; MIPS32: lui [[T2]],0xffff
-; MIPS32: ori [[T2]],[[T2]],0xff
-; MIPS32: and [[T0]],[[T0]],[[T2]]
-; MIPS32: or [[T1]],[[T1]],[[T0]]
-; MIPS32: move [[T0]],a3
-; MIPS32: srl [[T0]],[[T0]],0x10
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: andi [[T0]],[[T0]],0x1
-; MIPS32: move [[T2]],[[T3]]
-; MIPS32: srl [[T2]],[[T2]],0x10
-; MIPS32: andi [[T2]],[[T2]],0xff
-; MIPS32: andi [[T2]],[[T2]],0x1
-; MIPS32: sll [[T0]],[[T0]],0x1f
-; MIPS32: sll [[T2]],[[T2]],0x1f
-; MIPS32: slt [[T0]],[[T0]],[[T2]]
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: sll [[T0]],[[T0]],0x10
-; MIPS32: lui [[T2]],0xff00
-; MIPS32: ori [[T2]],[[T2]],0xffff
-; MIPS32: and [[T1]],[[T1]],[[T2]]
-; MIPS32: or [[T0]],[[T0]],[[T1]]
-; MIPS32: srl [[T13:.*]],a3,0x18
-; MIPS32: andi [[T13]],[[T13]],0x1
-; MIPS32: srl [[T3]],[[T3]],0x18
-; MIPS32: andi [[T3]],[[T3]],0x1
-; MIPS32: sll [[T13]],[[T13]],0x1f
-; MIPS32: sll [[T3]],[[T3]],0x1f
-; MIPS32: slt [[T13]],[[T13]],[[T3]]
-; MIPS32: sll [[T13]],[[T13]],0x18
-; MIPS32: sll [[T0]],[[T0]],0x8
-; MIPS32: srl [[T0]],[[T0]],0x8
-; MIPS32: or [[T13]],[[T13]],[[T0]]
-; MIPS32: move v0,[[T10]]
-; MIPS32: move v1,[[T11]]
-; MIPS32: move a0,[[T12]]
-; MIPS32: move a1,[[T13]]
-}
-
-define internal <16 x i1> @test_icmp_v16i1_uge(<16 x i1> %a, <16 x i1> %b) {
-entry:
- %res = icmp uge <16 x i1> %a, %b
- ret <16 x i1> %res
-; CHECK-LABEL: test_icmp_v16i1_uge
-; CHECK: pxor
-; CHECK: pcmpgtb
-; CHECK: pxor
-
-; MIPS32-LABEL: test_icmp_v16i1_uge
-; MIPS32: lw [[T0:.*]],
-; MIPS32: lw [[T1:.*]],
-; MIPS32: lw [[T2:.*]],
-; MIPS32: lw [[T3:.*]],
-; MIPS32: move [[T4:.*]],zero
-; MIPS32: move [[T5:.*]],zero
-; MIPS32: move [[T6:.*]],zero
-; MIPS32: move [[T7:.*]],zero
-; MIPS32: move [[T8:.*]],a0
-; MIPS32: andi [[T8]],[[T8]],0xff
-; MIPS32: andi [[T8]],[[T8]],0x1
-; MIPS32: move [[T9:.*]],[[T0]]
-; MIPS32: andi [[T9]],[[T9]],0xff
-; MIPS32: andi [[T9]],[[T9]],0x1
-; MIPS32: sll [[T8]],[[T8]],0x1f
-; MIPS32: sll [[T9]],[[T9]],0x1f
-; MIPS32: sltu [[T8]],[[T8]],[[T9]]
-; MIPS32: xori [[T8]],[[T8]],0x1
-; MIPS32: andi [[T8]],[[T8]],0xff
-; MIPS32: srl [[T4]],[[T4]],0x8
-; MIPS32: sll [[T4]],[[T4]],0x8
-; MIPS32: or [[T8]],[[T8]],[[T4]]
-; MIPS32: move [[T4]],a0
-; MIPS32: srl [[T4]],[[T4]],0x8
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: andi [[T4]],[[T4]],0x1
-; MIPS32: move [[T9]],[[T0]]
-; MIPS32: srl [[T9]],[[T9]],0x8
-; MIPS32: andi [[T9]],[[T9]],0xff
-; MIPS32: andi [[T9]],[[T9]],0x1
-; MIPS32: sll [[T4]],[[T4]],0x1f
-; MIPS32: sll [[T9]],[[T9]],0x1f
-; MIPS32: sltu [[T4]],[[T4]],[[T9]]
-; MIPS32: xori [[T4]],[[T4]],0x1
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: sll [[T4]],[[T4]],0x8
-; MIPS32: lui [[T9]],0xffff
-; MIPS32: ori [[T9]],[[T9]],0xff
-; MIPS32: and [[T8]],[[T8]],[[T9]]
-; MIPS32: or [[T4]],[[T4]],[[T8]]
-; MIPS32: move [[T8]],a0
-; MIPS32: srl [[T8]],[[T8]],0x10
-; MIPS32: andi [[T8]],[[T8]],0xff
-; MIPS32: andi [[T8]],[[T8]],0x1
-; MIPS32: move [[T9]],[[T0]]
-; MIPS32: srl [[T9]],[[T9]],0x10
-; MIPS32: andi [[T9]],[[T9]],0xff
-; MIPS32: andi [[T9]],[[T9]],0x1
-; MIPS32: sll [[T8]],[[T8]],0x1f
-; MIPS32: sll [[T9]],[[T9]],0x1f
-; MIPS32: sltu [[T8]],[[T8]],[[T9]]
-; MIPS32: xori [[T8]],[[T8]],0x1
-; MIPS32: andi [[T8]],[[T8]],0xff
-; MIPS32: sll [[T8]],[[T8]],0x10
-; MIPS32: lui [[T9]],0xff00
-; MIPS32: ori [[T9]],[[T9]],0xffff
-; MIPS32: and [[T4]],[[T4]],[[T9]]
-; MIPS32: or [[T8]],[[T8]],[[T4]]
-; MIPS32: srl [[T10:.*]],a0,0x18
-; MIPS32: andi [[T10]],[[T10]],0x1
-; MIPS32: srl [[T0]],[[T0]],0x18
-; MIPS32: andi [[T0]],[[T0]],0x1
-; MIPS32: sll [[T10]],[[T10]],0x1f
-; MIPS32: sll [[T0]],[[T0]],0x1f
-; MIPS32: sltu [[T10]],[[T10]],[[T0]]
-; MIPS32: xori [[T10]],[[T10]],0x1
-; MIPS32: sll [[T10]],[[T10]],0x18
-; MIPS32: sll [[T8]],[[T8]],0x8
-; MIPS32: srl [[T8]],[[T8]],0x8
-; MIPS32: or [[T10]],[[T10]],[[T8]]
-; MIPS32: move [[T0]],a1
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: andi [[T0]],[[T0]],0x1
-; MIPS32: move [[T4]],[[T1]]
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: andi [[T4]],[[T4]],0x1
-; MIPS32: sll [[T0]],[[T0]],0x1f
-; MIPS32: sll [[T4]],[[T4]],0x1f
-; MIPS32: sltu [[T0]],[[T0]],[[T4]]
-; MIPS32: xori [[T0]],[[T0]],0x1
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: srl [[T5]],[[T5]],0x8
-; MIPS32: sll [[T5]],[[T5]],0x8
-; MIPS32: or [[T0]],[[T0]],[[T5]]
-; MIPS32: move [[T4]],a1
-; MIPS32: srl [[T4]],[[T4]],0x8
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: andi [[T4]],[[T4]],0x1
-; MIPS32: move [[T5]],[[T1]]
-; MIPS32: srl [[T5]],[[T5]],0x8
-; MIPS32: andi [[T5]],[[T5]],0xff
-; MIPS32: andi [[T5]],[[T5]],0x1
-; MIPS32: sll [[T4]],[[T4]],0x1f
-; MIPS32: sll [[T5]],[[T5]],0x1f
-; MIPS32: sltu [[T4]],[[T4]],[[T5]]
-; MIPS32: xori [[T4]],[[T4]],0x1
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: sll [[T4]],[[T4]],0x8
-; MIPS32: lui [[T5]],0xffff
-; MIPS32: ori [[T5]],[[T5]],0xff
-; MIPS32: and [[T0]],[[T0]],[[T5]]
-; MIPS32: or [[T4]],[[T4]],[[T0]]
-; MIPS32: move [[T0]],a1
-; MIPS32: srl [[T0]],[[T0]],0x10
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: andi [[T0]],[[T0]],0x1
-; MIPS32: move [[T5]],[[T1]]
-; MIPS32: srl [[T5]],[[T5]],0x10
-; MIPS32: andi [[T5]],[[T5]],0xff
-; MIPS32: andi [[T5]],[[T5]],0x1
-; MIPS32: sll [[T0]],[[T0]],0x1f
-; MIPS32: sll [[T5]],[[T5]],0x1f
-; MIPS32: sltu [[T0]],[[T0]],[[T5]]
-; MIPS32: xori [[T0]],[[T0]],0x1
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: sll [[T0]],[[T0]],0x10
-; MIPS32: lui [[T5]],0xff00
-; MIPS32: ori [[T5]],[[T5]],0xffff
-; MIPS32: and [[T4]],[[T4]],[[T5]]
-; MIPS32: or [[T0]],[[T0]],[[T4]]
-; MIPS32: srl [[T11:.*]],a1,0x18
-; MIPS32: andi [[T11]],[[T11]],0x1
-; MIPS32: srl [[T1]],[[T1]],0x18
-; MIPS32: andi [[T1]],[[T1]],0x1
-; MIPS32: sll [[T11]],[[T11]],0x1f
-; MIPS32: sll [[T1]],[[T1]],0x1f
-; MIPS32: sltu [[T11]],[[T11]],[[T1]]
-; MIPS32: xori [[T11]],[[T11]],0x1
-; MIPS32: sll [[T11]],[[T11]],0x18
-; MIPS32: sll [[T0]],[[T0]],0x8
-; MIPS32: srl [[T0]],[[T0]],0x8
-; MIPS32: or [[T11]],[[T11]],[[T0]]
-; MIPS32: move [[T0]],a2
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: andi [[T0]],[[T0]],0x1
-; MIPS32: move [[T1]],[[T2]]
-; MIPS32: andi [[T1]],[[T1]],0xff
-; MIPS32: andi [[T1]],[[T1]],0x1
-; MIPS32: sll [[T0]],[[T0]],0x1f
-; MIPS32: sll [[T1]],[[T1]],0x1f
-; MIPS32: sltu [[T0]],[[T0]],[[T1]]
-; MIPS32: xori [[T0]],[[T0]],0x1
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: srl [[T6]],[[T6]],0x8
-; MIPS32: sll [[T6]],[[T6]],0x8
-; MIPS32: or [[T0]],[[T0]],[[T6]]
-; MIPS32: move [[T1]],a2
-; MIPS32: srl [[T1]],[[T1]],0x8
-; MIPS32: andi [[T1]],[[T1]],0xff
-; MIPS32: andi [[T1]],[[T1]],0x1
-; MIPS32: move [[T4]],[[T2]]
-; MIPS32: srl [[T4]],[[T4]],0x8
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: andi [[T4]],[[T4]],0x1
-; MIPS32: sll [[T1]],[[T1]],0x1f
-; MIPS32: sll [[T4]],[[T4]],0x1f
-; MIPS32: sltu [[T1]],[[T1]],[[T4]]
-; MIPS32: xori [[T1]],[[T1]],0x1
-; MIPS32: andi [[T1]],[[T1]],0xff
-; MIPS32: sll [[T1]],[[T1]],0x8
-; MIPS32: lui [[T4]],0xffff
-; MIPS32: ori [[T4]],[[T4]],0xff
-; MIPS32: and [[T0]],[[T0]],[[T4]]
-; MIPS32: or [[T1]],[[T1]],[[T0]]
-; MIPS32: move [[T0]],a2
-; MIPS32: srl [[T0]],[[T0]],0x10
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: andi [[T0]],[[T0]],0x1
-; MIPS32: move [[T4]],[[T2]]
-; MIPS32: srl [[T4]],[[T4]],0x10
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: andi [[T4]],[[T4]],0x1
-; MIPS32: sll [[T0]],[[T0]],0x1f
-; MIPS32: sll [[T4]],[[T4]],0x1f
-; MIPS32: sltu [[T0]],[[T0]],[[T4]]
-; MIPS32: xori [[T0]],[[T0]],0x1
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: sll [[T0]],[[T0]],0x10
-; MIPS32: lui [[T4]],0xff00
-; MIPS32: ori [[T4]],[[T4]],0xffff
-; MIPS32: and [[T1]],[[T1]],[[T4]]
-; MIPS32: or [[T0]],[[T0]],[[T1]]
-; MIPS32: srl [[T12:.*]],a2,0x18
-; MIPS32: andi [[T12]],[[T12]],0x1
-; MIPS32: srl [[T2]],[[T2]],0x18
-; MIPS32: andi [[T2]],[[T2]],0x1
-; MIPS32: sll [[T12]],[[T12]],0x1f
-; MIPS32: sll [[T2]],[[T2]],0x1f
-; MIPS32: sltu [[T12]],[[T12]],[[T2]]
-; MIPS32: xori [[T12]],[[T12]],0x1
-; MIPS32: sll [[T12]],[[T12]],0x18
-; MIPS32: sll [[T0]],[[T0]],0x8
-; MIPS32: srl [[T0]],[[T0]],0x8
-; MIPS32: or [[T12]],[[T12]],[[T0]]
-; MIPS32: move [[T0]],a3
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: andi [[T0]],[[T0]],0x1
-; MIPS32: move [[T1]],[[T3]]
-; MIPS32: andi [[T1]],[[T1]],0xff
-; MIPS32: andi [[T1]],[[T1]],0x1
-; MIPS32: sll [[T0]],[[T0]],0x1f
-; MIPS32: sll [[T1]],[[T1]],0x1f
-; MIPS32: sltu [[T0]],[[T0]],[[T1]]
-; MIPS32: xori [[T0]],[[T0]],0x1
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: srl [[T7]],[[T7]],0x8
-; MIPS32: sll [[T7]],[[T7]],0x8
-; MIPS32: or [[T0]],[[T0]],[[T7]]
-; MIPS32: move [[T1]],a3
-; MIPS32: srl [[T1]],[[T1]],0x8
-; MIPS32: andi [[T1]],[[T1]],0xff
-; MIPS32: andi [[T1]],[[T1]],0x1
-; MIPS32: move [[T2]],[[T3]]
-; MIPS32: srl [[T2]],[[T2]],0x8
-; MIPS32: andi [[T2]],[[T2]],0xff
-; MIPS32: andi [[T2]],[[T2]],0x1
-; MIPS32: sll [[T1]],[[T1]],0x1f
-; MIPS32: sll [[T2]],[[T2]],0x1f
-; MIPS32: sltu [[T1]],[[T1]],[[T2]]
-; MIPS32: xori [[T1]],[[T1]],0x1
-; MIPS32: andi [[T1]],[[T1]],0xff
-; MIPS32: sll [[T1]],[[T1]],0x8
-; MIPS32: lui [[T2]],0xffff
-; MIPS32: ori [[T2]],[[T2]],0xff
-; MIPS32: and [[T0]],[[T0]],[[T2]]
-; MIPS32: or [[T1]],[[T1]],[[T0]]
-; MIPS32: move [[T0]],a3
-; MIPS32: srl [[T0]],[[T0]],0x10
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: andi [[T0]],[[T0]],0x1
-; MIPS32: move [[T2]],[[T3]]
-; MIPS32: srl [[T2]],[[T2]],0x10
-; MIPS32: andi [[T2]],[[T2]],0xff
-; MIPS32: andi [[T2]],[[T2]],0x1
-; MIPS32: sll [[T0]],[[T0]],0x1f
-; MIPS32: sll [[T2]],[[T2]],0x1f
-; MIPS32: sltu [[T0]],[[T0]],[[T2]]
-; MIPS32: xori [[T0]],[[T0]],0x1
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: sll [[T0]],[[T0]],0x10
-; MIPS32: lui [[T2]],0xff00
-; MIPS32: ori [[T2]],[[T2]],0xffff
-; MIPS32: and [[T1]],[[T1]],[[T2]]
-; MIPS32: or [[T0]],[[T0]],[[T1]]
-; MIPS32: srl [[T13:.*]],a3,0x18
-; MIPS32: andi [[T13]],[[T13]],0x1
-; MIPS32: srl [[T3]],[[T3]],0x18
-; MIPS32: andi [[T3]],[[T3]],0x1
-; MIPS32: sll [[T13]],[[T13]],0x1f
-; MIPS32: sll [[T3]],[[T3]],0x1f
-; MIPS32: sltu [[T13]],[[T13]],[[T3]]
-; MIPS32: xori [[T13]],[[T13]],0x1
-; MIPS32: sll [[T13]],[[T13]],0x18
-; MIPS32: sll [[T0]],[[T0]],0x8
-; MIPS32: srl [[T0]],[[T0]],0x8
-; MIPS32: or [[T13]],[[T13]],[[T0]]
-; MIPS32: move v0,[[T10]]
-; MIPS32: move v1,[[T11]]
-; MIPS32: move a0,[[T12]]
-; MIPS32: move a1,[[T13]]
-}
-
-define internal <16 x i1> @test_icmp_v16i1_ugt(<16 x i1> %a, <16 x i1> %b) {
-entry:
- %res = icmp ugt <16 x i1> %a, %b
- ret <16 x i1> %res
-; CHECK-LABEL: test_icmp_v16i1_ugt
-; CHECK: pxor
-; CHECK: pcmpgtb
-
-; MIPS32-LABEL: test_icmp_v16i1_ugt
-; MIPS32: lw [[T0:.*]],
-; MIPS32: lw [[T1:.*]],
-; MIPS32: lw [[T2:.*]],
-; MIPS32: lw [[T3:.*]],
-; MIPS32: move [[T4:.*]],zero
-; MIPS32: move [[T5:.*]],zero
-; MIPS32: move [[T6:.*]],zero
-; MIPS32: move [[T7:.*]],zero
-; MIPS32: move [[T8:.*]],a0
-; MIPS32: andi [[T8]],[[T8]],0xff
-; MIPS32: andi [[T8]],[[T8]],0x1
-; MIPS32: move [[T9:.*]],[[T0]]
-; MIPS32: andi [[T9]],[[T9]],0xff
-; MIPS32: andi [[T9]],[[T9]],0x1
-; MIPS32: sll [[T8]],[[T8]],0x1f
-; MIPS32: sll [[T9]],[[T9]],0x1f
-; MIPS32: sltu [[T9]],[[T9]],[[T8]]
-; MIPS32: andi [[T9]],[[T9]],0xff
-; MIPS32: srl [[T4]],[[T4]],0x8
-; MIPS32: sll [[T4]],[[T4]],0x8
-; MIPS32: or [[T9]],[[T9]],[[T4]]
-; MIPS32: move [[T4]],a0
-; MIPS32: srl [[T4]],[[T4]],0x8
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: andi [[T4]],[[T4]],0x1
-; MIPS32: move [[T8]],[[T0]]
-; MIPS32: srl [[T8]],[[T8]],0x8
-; MIPS32: andi [[T8]],[[T8]],0xff
-; MIPS32: andi [[T8]],[[T8]],0x1
-; MIPS32: sll [[T4]],[[T4]],0x1f
-; MIPS32: sll [[T8]],[[T8]],0x1f
-; MIPS32: sltu [[T8]],[[T8]],[[T4]]
-; MIPS32: andi [[T8]],[[T8]],0xff
-; MIPS32: sll [[T8]],[[T8]],0x8
-; MIPS32: lui [[T4]],0xffff
-; MIPS32: ori [[T4]],[[T4]],0xff
-; MIPS32: and [[T9]],[[T9]],[[T4]]
-; MIPS32: or [[T8]],[[T8]],[[T9]]
-; MIPS32: move [[T4]],a0
-; MIPS32: srl [[T4]],[[T4]],0x10
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: andi [[T4]],[[T4]],0x1
-; MIPS32: move [[T9]],[[T0]]
-; MIPS32: srl [[T9]],[[T9]],0x10
-; MIPS32: andi [[T9]],[[T9]],0xff
-; MIPS32: andi [[T9]],[[T9]],0x1
-; MIPS32: sll [[T4]],[[T4]],0x1f
-; MIPS32: sll [[T9]],[[T9]],0x1f
-; MIPS32: sltu [[T9]],[[T9]],[[T4]]
-; MIPS32: andi [[T9]],[[T9]],0xff
-; MIPS32: sll [[T9]],[[T9]],0x10
-; MIPS32: lui [[T4]],0xff00
-; MIPS32: ori [[T4]],[[T4]],0xffff
-; MIPS32: and [[T8]],[[T8]],[[T4]]
-; MIPS32: or [[T9]],[[T9]],[[T8]]
-; MIPS32: srl [[T10:.*]],a0,0x18
-; MIPS32: andi [[T10]],[[T10]],0x1
-; MIPS32: srl [[T0]],[[T0]],0x18
-; MIPS32: andi [[T0]],[[T0]],0x1
-; MIPS32: sll [[T10]],[[T10]],0x1f
-; MIPS32: sll [[T0]],[[T0]],0x1f
-; MIPS32: sltu [[T0]],[[T0]],[[T10]]
-; MIPS32: sll [[T0]],[[T0]],0x18
-; MIPS32: sll [[T9]],[[T9]],0x8
-; MIPS32: srl [[T9]],[[T9]],0x8
-; MIPS32: or v0,[[T0]],[[T9]]
-; MIPS32: move [[T10]],a1
-; MIPS32: andi [[T10]],[[T10]],0xff
-; MIPS32: andi [[T10]],[[T10]],0x1
-; MIPS32: move [[T4]],[[T1]]
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: andi [[T4]],[[T4]],0x1
-; MIPS32: sll [[T10]],[[T10]],0x1f
-; MIPS32: sll [[T4]],[[T4]],0x1f
-; MIPS32: sltu [[T4]],[[T4]],[[T10]]
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: srl [[T5]],[[T5]],0x8
-; MIPS32: sll [[T5]],[[T5]],0x8
-; MIPS32: or [[T4]],[[T4]],[[T5]]
-; MIPS32: move [[T10]],a1
-; MIPS32: srl [[T10]],[[T10]],0x8
-; MIPS32: andi [[T10]],[[T10]],0xff
-; MIPS32: andi [[T10]],[[T10]],0x1
-; MIPS32: move [[T5]],[[T1]]
-; MIPS32: srl [[T5]],[[T5]],0x8
-; MIPS32: andi [[T5]],[[T5]],0xff
-; MIPS32: andi [[T5]],[[T5]],0x1
-; MIPS32: sll [[T10]],[[T10]],0x1f
-; MIPS32: sll [[T5]],[[T5]],0x1f
-; MIPS32: sltu [[T5]],[[T5]],[[T10]]
-; MIPS32: andi [[T5]],[[T5]],0xff
-; MIPS32: sll [[T5]],[[T5]],0x8
-; MIPS32: lui [[T10]],0xffff
-; MIPS32: ori [[T10]],[[T10]],0xff
-; MIPS32: and [[T4]],[[T4]],[[T10]]
-; MIPS32: or [[T5]],[[T5]],[[T4]]
-; MIPS32: move [[T10]],a1
-; MIPS32: srl [[T10]],[[T10]],0x10
-; MIPS32: andi [[T10]],[[T10]],0xff
-; MIPS32: andi [[T10]],[[T10]],0x1
-; MIPS32: move [[T4]],[[T1]]
-; MIPS32: srl [[T4]],[[T4]],0x10
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: andi [[T4]],[[T4]],0x1
-; MIPS32: sll [[T10]],[[T10]],0x1f
-; MIPS32: sll [[T4]],[[T4]],0x1f
-; MIPS32: sltu [[T4]],[[T4]],[[T10]]
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: sll [[T4]],[[T4]],0x10
-; MIPS32: lui [[T10]],0xff00
-; MIPS32: ori [[T10]],[[T10]],0xffff
-; MIPS32: and [[T5]],[[T5]],[[T10]]
-; MIPS32: or [[T4]],[[T4]],[[T5]]
-; MIPS32: srl [[T11:.*]],a1,0x18
-; MIPS32: andi [[T11]],[[T11]],0x1
-; MIPS32: srl [[T1]],[[T1]],0x18
-; MIPS32: andi [[T1]],[[T1]],0x1
-; MIPS32: sll [[T11]],[[T11]],0x1f
-; MIPS32: sll [[T1]],[[T1]],0x1f
-; MIPS32: sltu [[T1]],[[T1]],[[T11]]
-; MIPS32: sll [[T1]],[[T1]],0x18
-; MIPS32: sll [[T4]],[[T4]],0x8
-; MIPS32: srl [[T4]],[[T4]],0x8
-; MIPS32: or v1,[[T1]],[[T4]]
-; MIPS32: move [[T10]],a2
-; MIPS32: andi [[T10]],[[T10]],0xff
-; MIPS32: andi [[T10]],[[T10]],0x1
-; MIPS32: move [[T11]],[[T2]]
-; MIPS32: andi [[T11]],[[T11]],0xff
-; MIPS32: andi [[T11]],[[T11]],0x1
-; MIPS32: sll [[T10]],[[T10]],0x1f
-; MIPS32: sll [[T11]],[[T11]],0x1f
-; MIPS32: sltu [[T11]],[[T11]],[[T10]]
-; MIPS32: andi [[T11]],[[T11]],0xff
-; MIPS32: srl [[T6]],[[T6]],0x8
-; MIPS32: sll [[T6]],[[T6]],0x8
-; MIPS32: or [[T11]],[[T11]],[[T6]]
-; MIPS32: move [[T10]],a2
-; MIPS32: srl [[T10]],[[T10]],0x8
-; MIPS32: andi [[T10]],[[T10]],0xff
-; MIPS32: andi [[T10]],[[T10]],0x1
-; MIPS32: move [[T4]],[[T2]]
-; MIPS32: srl [[T4]],[[T4]],0x8
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: andi [[T4]],[[T4]],0x1
-; MIPS32: sll [[T10]],[[T10]],0x1f
-; MIPS32: sll [[T4]],[[T4]],0x1f
-; MIPS32: sltu [[T4]],[[T4]],[[T10]]
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: sll [[T4]],[[T4]],0x8
-; MIPS32: lui [[T10]],0xffff
-; MIPS32: ori [[T10]],[[T10]],0xff
-; MIPS32: and [[T11]],[[T11]],[[T10]]
-; MIPS32: or [[T4]],[[T4]],[[T11]]
-; MIPS32: move [[T10]],a2
-; MIPS32: srl [[T10]],[[T10]],0x10
-; MIPS32: andi [[T10]],[[T10]],0xff
-; MIPS32: andi [[T10]],[[T10]],0x1
-; MIPS32: move [[T11]],[[T2]]
-; MIPS32: srl [[T11]],[[T11]],0x10
-; MIPS32: andi [[T11]],[[T11]],0xff
-; MIPS32: andi [[T11]],[[T11]],0x1
-; MIPS32: sll [[T10]],[[T10]],0x1f
-; MIPS32: sll [[T11]],[[T11]],0x1f
-; MIPS32: sltu [[T11]],[[T11]],[[T10]]
-; MIPS32: andi [[T11]],[[T11]],0xff
-; MIPS32: sll [[T11]],[[T11]],0x10
-; MIPS32: lui [[T10]],0xff00
-; MIPS32: ori [[T10]],[[T10]],0xffff
-; MIPS32: and [[T4]],[[T4]],[[T10]]
-; MIPS32: or [[T11]],[[T11]],[[T4]]
-; MIPS32: srl [[T12:.*]],a2,0x18
-; MIPS32: andi [[T12]],[[T12]],0x1
-; MIPS32: srl [[T2]],[[T2]],0x18
-; MIPS32: andi [[T2]],[[T2]],0x1
-; MIPS32: sll [[T12]],[[T12]],0x1f
-; MIPS32: sll [[T2]],[[T2]],0x1f
-; MIPS32: sltu [[T2]],[[T2]],[[T12]]
-; MIPS32: sll [[T2]],[[T2]],0x18
-; MIPS32: sll [[T11]],[[T11]],0x8
-; MIPS32: srl [[T11]],[[T11]],0x8
-; MIPS32: or [[T2]],[[T2]],[[T11]]
-; MIPS32: move [[T10]],a3
-; MIPS32: andi [[T10]],[[T10]],0xff
-; MIPS32: andi [[T10]],[[T10]],0x1
-; MIPS32: move [[T11]],[[T3]]
-; MIPS32: andi [[T11]],[[T11]],0xff
-; MIPS32: andi [[T11]],[[T11]],0x1
-; MIPS32: sll [[T10]],[[T10]],0x1f
-; MIPS32: sll [[T11]],[[T11]],0x1f
-; MIPS32: sltu [[T11]],[[T11]],[[T10]]
-; MIPS32: andi [[T11]],[[T11]],0xff
-; MIPS32: srl [[T7]],[[T7]],0x8
-; MIPS32: sll [[T7]],[[T7]],0x8
-; MIPS32: or [[T11]],[[T11]],[[T7]]
-; MIPS32: move [[T10]],a3
-; MIPS32: srl [[T10]],[[T10]],0x8
-; MIPS32: andi [[T10]],[[T10]],0xff
-; MIPS32: andi [[T10]],[[T10]],0x1
-; MIPS32: move [[T12]],[[T3]]
-; MIPS32: srl [[T12]],[[T12]],0x8
-; MIPS32: andi [[T12]],[[T12]],0xff
-; MIPS32: andi [[T12]],[[T12]],0x1
-; MIPS32: sll [[T10]],[[T10]],0x1f
-; MIPS32: sll [[T12]],[[T12]],0x1f
-; MIPS32: sltu [[T12]],[[T12]],[[T10]]
-; MIPS32: andi [[T12]],[[T12]],0xff
-; MIPS32: sll [[T12]],[[T12]],0x8
-; MIPS32: lui [[T10]],0xffff
-; MIPS32: ori [[T10]],[[T10]],0xff
-; MIPS32: and [[T11]],[[T11]],[[T10]]
-; MIPS32: or [[T12]],[[T12]],[[T11]]
-; MIPS32: move [[T10]],a3
-; MIPS32: srl [[T10]],[[T10]],0x10
-; MIPS32: andi [[T10]],[[T10]],0xff
-; MIPS32: andi [[T10]],[[T10]],0x1
-; MIPS32: move [[T11]],[[T3]]
-; MIPS32: srl [[T11]],[[T11]],0x10
-; MIPS32: andi [[T11]],[[T11]],0xff
-; MIPS32: andi [[T11]],[[T11]],0x1
-; MIPS32: sll [[T10]],[[T10]],0x1f
-; MIPS32: sll [[T11]],[[T11]],0x1f
-; MIPS32: sltu [[T11]],[[T11]],[[T10]]
-; MIPS32: andi [[T11]],[[T11]],0xff
-; MIPS32: sll [[T11]],[[T11]],0x10
-; MIPS32: lui [[T10]],0xff00
-; MIPS32: ori [[T10]],[[T10]],0xffff
-; MIPS32: and [[T12]],[[T12]],[[T10]]
-; MIPS32: or [[T11]],[[T11]],[[T12]]
-; MIPS32: srl [[T13:.*]],a3,0x18
-; MIPS32: andi [[T13]],[[T13]],0x1
-; MIPS32: srl [[T3]],[[T3]],0x18
-; MIPS32: andi [[T3]],[[T3]],0x1
-; MIPS32: sll [[T13]],[[T13]],0x1f
-; MIPS32: sll [[T3]],[[T3]],0x1f
-; MIPS32: sltu [[T3]],[[T3]],[[T13]]
-; MIPS32: sll [[T3]],[[T3]],0x18
-; MIPS32: sll [[T11]],[[T11]],0x8
-; MIPS32: srl [[T11]],[[T11]],0x8
-; MIPS32: or [[T3]],[[T3]],[[T11]]
-; MIPS32: move a0,[[T2]]
-; MIPS32: move a1,[[T3]]
-}
-
-define internal <16 x i1> @test_icmp_v16i1_ule(<16 x i1> %a, <16 x i1> %b) {
-entry:
- %res = icmp ule <16 x i1> %a, %b
- ret <16 x i1> %res
-; CHECK-LABEL: test_icmp_v16i1_ule
-; CHECK: pxor
-; CHECK: pcmpgtb
-; CHECK: pxor
-
-; MIPS32-LABEL: test_icmp_v16i1_ule
-; MIPS32: lw [[T0:.*]],
-; MIPS32: lw [[T1:.*]],
-; MIPS32: lw [[T2:.*]],
-; MIPS32: lw [[T3:.*]],
-; MIPS32: move [[T4:.*]],zero
-; MIPS32: move [[T5:.*]],zero
-; MIPS32: move [[T6:.*]],zero
-; MIPS32: move [[T7:.*]],zero
-; MIPS32: move [[T8:.*]],a0
-; MIPS32: andi [[T8]],[[T8]],0xff
-; MIPS32: andi [[T8]],[[T8]],0x1
-; MIPS32: move [[T9:.*]],[[T0]]
-; MIPS32: andi [[T9]],[[T9]],0xff
-; MIPS32: andi [[T9]],[[T9]],0x1
-; MIPS32: sll [[T8]],[[T8]],0x1f
-; MIPS32: sll [[T9]],[[T9]],0x1f
-; MIPS32: sltu [[T9]],[[T9]],[[T8]]
-; MIPS32: xori [[T9]],[[T9]],0x1
-; MIPS32: andi [[T9]],[[T9]],0xff
-; MIPS32: srl [[T4]],[[T4]],0x8
-; MIPS32: sll [[T4]],[[T4]],0x8
-; MIPS32: or [[T9]],[[T9]],[[T4]]
-; MIPS32: move [[T4]],a0
-; MIPS32: srl [[T4]],[[T4]],0x8
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: andi [[T4]],[[T4]],0x1
-; MIPS32: move [[T8]],[[T0]]
-; MIPS32: srl [[T8]],[[T8]],0x8
-; MIPS32: andi [[T8]],[[T8]],0xff
-; MIPS32: andi [[T8]],[[T8]],0x1
-; MIPS32: sll [[T4]],[[T4]],0x1f
-; MIPS32: sll [[T8]],[[T8]],0x1f
-; MIPS32: sltu [[T8]],[[T8]],[[T4]]
-; MIPS32: xori [[T8]],[[T8]],0x1
-; MIPS32: andi [[T8]],[[T8]],0xff
-; MIPS32: sll [[T8]],[[T8]],0x8
-; MIPS32: lui [[T4]],0xffff
-; MIPS32: ori [[T4]],[[T4]],0xff
-; MIPS32: and [[T9]],[[T9]],[[T4]]
-; MIPS32: or [[T8]],[[T8]],[[T9]]
-; MIPS32: move [[T4]],a0
-; MIPS32: srl [[T4]],[[T4]],0x10
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: andi [[T4]],[[T4]],0x1
-; MIPS32: move [[T9]],[[T0]]
-; MIPS32: srl [[T9]],[[T9]],0x10
-; MIPS32: andi [[T9]],[[T9]],0xff
-; MIPS32: andi [[T9]],[[T9]],0x1
-; MIPS32: sll [[T4]],[[T4]],0x1f
-; MIPS32: sll [[T9]],[[T9]],0x1f
-; MIPS32: sltu [[T9]],[[T9]],[[T4]]
-; MIPS32: xori [[T9]],[[T9]],0x1
-; MIPS32: andi [[T9]],[[T9]],0xff
-; MIPS32: sll [[T9]],[[T9]],0x10
-; MIPS32: lui [[T4]],0xff00
-; MIPS32: ori [[T4]],[[T4]],0xffff
-; MIPS32: and [[T8]],[[T8]],[[T4]]
-; MIPS32: or [[T9]],[[T9]],[[T8]]
-; MIPS32: srl [[T10:.*]],a0,0x18
-; MIPS32: andi [[T10]],[[T10]],0x1
-; MIPS32: srl [[T0]],[[T0]],0x18
-; MIPS32: andi [[T0]],[[T0]],0x1
-; MIPS32: sll [[T10]],[[T10]],0x1f
-; MIPS32: sll [[T0]],[[T0]],0x1f
-; MIPS32: sltu [[T0]],[[T0]],[[T10]]
-; MIPS32: xori [[T0]],[[T0]],0x1
-; MIPS32: sll [[T0]],[[T0]],0x18
-; MIPS32: sll [[T9]],[[T9]],0x8
-; MIPS32: srl [[T9]],[[T9]],0x8
-; MIPS32: or v0,[[T0]],[[T9]]
-; MIPS32: move [[T10]],a1
-; MIPS32: andi [[T10]],[[T10]],0xff
-; MIPS32: andi [[T10]],[[T10]],0x1
-; MIPS32: move [[T4]],[[T1]]
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: andi [[T4]],[[T4]],0x1
-; MIPS32: sll [[T10]],[[T10]],0x1f
-; MIPS32: sll [[T4]],[[T4]],0x1f
-; MIPS32: sltu [[T4]],[[T4]],[[T10]]
-; MIPS32: xori [[T4]],[[T4]],0x1
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: srl [[T5]],[[T5]],0x8
-; MIPS32: sll [[T5]],[[T5]],0x8
-; MIPS32: or [[T4]],[[T4]],[[T5]]
-; MIPS32: move [[T10]],a1
-; MIPS32: srl [[T10]],[[T10]],0x8
-; MIPS32: andi [[T10]],[[T10]],0xff
-; MIPS32: andi [[T10]],[[T10]],0x1
-; MIPS32: move [[T5]],[[T1]]
-; MIPS32: srl [[T5]],[[T5]],0x8
-; MIPS32: andi [[T5]],[[T5]],0xff
-; MIPS32: andi [[T5]],[[T5]],0x1
-; MIPS32: sll [[T10]],[[T10]],0x1f
-; MIPS32: sll [[T5]],[[T5]],0x1f
-; MIPS32: sltu [[T5]],[[T5]],[[T10]]
-; MIPS32: xori [[T5]],[[T5]],0x1
-; MIPS32: andi [[T5]],[[T5]],0xff
-; MIPS32: sll [[T5]],[[T5]],0x8
-; MIPS32: lui [[T10]],0xffff
-; MIPS32: ori [[T10]],[[T10]],0xff
-; MIPS32: and [[T4]],[[T4]],[[T10]]
-; MIPS32: or [[T5]],[[T5]],[[T4]]
-; MIPS32: move [[T10]],a1
-; MIPS32: srl [[T10]],[[T10]],0x10
-; MIPS32: andi [[T10]],[[T10]],0xff
-; MIPS32: andi [[T10]],[[T10]],0x1
-; MIPS32: move [[T4]],[[T1]]
-; MIPS32: srl [[T4]],[[T4]],0x10
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: andi [[T4]],[[T4]],0x1
-; MIPS32: sll [[T10]],[[T10]],0x1f
-; MIPS32: sll [[T4]],[[T4]],0x1f
-; MIPS32: sltu [[T4]],[[T4]],[[T10]]
-; MIPS32: xori [[T4]],[[T4]],0x1
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: sll [[T4]],[[T4]],0x10
-; MIPS32: lui [[T10]],0xff00
-; MIPS32: ori [[T10]],[[T10]],0xffff
-; MIPS32: and [[T5]],[[T5]],[[T10]]
-; MIPS32: or [[T4]],[[T4]],[[T5]]
-; MIPS32: srl [[T11:.*]],a1,0x18
-; MIPS32: andi [[T11]],[[T11]],0x1
-; MIPS32: srl [[T1]],[[T1]],0x18
-; MIPS32: andi [[T1]],[[T1]],0x1
-; MIPS32: sll [[T11]],[[T11]],0x1f
-; MIPS32: sll [[T1]],[[T1]],0x1f
-; MIPS32: sltu [[T1]],[[T1]],[[T11]]
-; MIPS32: xori [[T1]],[[T1]],0x1
-; MIPS32: sll [[T1]],[[T1]],0x18
-; MIPS32: sll [[T4]],[[T4]],0x8
-; MIPS32: srl [[T4]],[[T4]],0x8
-; MIPS32: or v1,[[T1]],[[T4]]
-; MIPS32: move [[T10]],a2
-; MIPS32: andi [[T10]],[[T10]],0xff
-; MIPS32: andi [[T10]],[[T10]],0x1
-; MIPS32: move [[T11]],[[T2]]
-; MIPS32: andi [[T11]],[[T11]],0xff
-; MIPS32: andi [[T11]],[[T11]],0x1
-; MIPS32: sll [[T10]],[[T10]],0x1f
-; MIPS32: sll [[T11]],[[T11]],0x1f
-; MIPS32: sltu [[T11]],[[T11]],[[T10]]
-; MIPS32: xori [[T11]],[[T11]],0x1
-; MIPS32: andi [[T11]],[[T11]],0xff
-; MIPS32: srl [[T6]],[[T6]],0x8
-; MIPS32: sll [[T6]],[[T6]],0x8
-; MIPS32: or [[T11]],[[T11]],[[T6]]
-; MIPS32: move [[T10]],a2
-; MIPS32: srl [[T10]],[[T10]],0x8
-; MIPS32: andi [[T10]],[[T10]],0xff
-; MIPS32: andi [[T10]],[[T10]],0x1
-; MIPS32: move [[T4]],[[T2]]
-; MIPS32: srl [[T4]],[[T4]],0x8
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: andi [[T4]],[[T4]],0x1
-; MIPS32: sll [[T10]],[[T10]],0x1f
-; MIPS32: sll [[T4]],[[T4]],0x1f
-; MIPS32: sltu [[T4]],[[T4]],[[T10]]
-; MIPS32: xori [[T4]],[[T4]],0x1
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: sll [[T4]],[[T4]],0x8
-; MIPS32: lui [[T10]],0xffff
-; MIPS32: ori [[T10]],[[T10]],0xff
-; MIPS32: and [[T11]],[[T11]],[[T10]]
-; MIPS32: or [[T4]],[[T4]],[[T11]]
-; MIPS32: move [[T10]],a2
-; MIPS32: srl [[T10]],[[T10]],0x10
-; MIPS32: andi [[T10]],[[T10]],0xff
-; MIPS32: andi [[T10]],[[T10]],0x1
-; MIPS32: move [[T11]],[[T2]]
-; MIPS32: srl [[T11]],[[T11]],0x10
-; MIPS32: andi [[T11]],[[T11]],0xff
-; MIPS32: andi [[T11]],[[T11]],0x1
-; MIPS32: sll [[T10]],[[T10]],0x1f
-; MIPS32: sll [[T11]],[[T11]],0x1f
-; MIPS32: sltu [[T11]],[[T11]],[[T10]]
-; MIPS32: xori [[T11]],[[T11]],0x1
-; MIPS32: andi [[T11]],[[T11]],0xff
-; MIPS32: sll [[T11]],[[T11]],0x10
-; MIPS32: lui [[T10]],0xff00
-; MIPS32: ori [[T10]],[[T10]],0xffff
-; MIPS32: and [[T4]],[[T4]],[[T10]]
-; MIPS32: or [[T11]],[[T11]],[[T4]]
-; MIPS32: srl [[T12:.*]],a2,0x18
-; MIPS32: andi [[T12]],[[T12]],0x1
-; MIPS32: srl [[T2]],[[T2]],0x18
-; MIPS32: andi [[T2]],[[T2]],0x1
-; MIPS32: sll [[T12]],[[T12]],0x1f
-; MIPS32: sll [[T2]],[[T2]],0x1f
-; MIPS32: sltu [[T2]],[[T2]],[[T12]]
-; MIPS32: xori [[T2]],[[T2]],0x1
-; MIPS32: sll [[T2]],[[T2]],0x18
-; MIPS32: sll [[T11]],[[T11]],0x8
-; MIPS32: srl [[T11]],[[T11]],0x8
-; MIPS32: or [[T2]],[[T2]],[[T11]]
-; MIPS32: move [[T10]],a3
-; MIPS32: andi [[T10]],[[T10]],0xff
-; MIPS32: andi [[T10]],[[T10]],0x1
-; MIPS32: move [[T11]],[[T3]]
-; MIPS32: andi [[T11]],[[T11]],0xff
-; MIPS32: andi [[T11]],[[T11]],0x1
-; MIPS32: sll [[T10]],[[T10]],0x1f
-; MIPS32: sll [[T11]],[[T11]],0x1f
-; MIPS32: sltu [[T11]],[[T11]],[[T10]]
-; MIPS32: xori [[T11]],[[T11]],0x1
-; MIPS32: andi [[T11]],[[T11]],0xff
-; MIPS32: srl [[T7]],[[T7]],0x8
-; MIPS32: sll [[T7]],[[T7]],0x8
-; MIPS32: or [[T11]],[[T11]],[[T7]]
-; MIPS32: move [[T10]],a3
-; MIPS32: srl [[T10]],[[T10]],0x8
-; MIPS32: andi [[T10]],[[T10]],0xff
-; MIPS32: andi [[T10]],[[T10]],0x1
-; MIPS32: move [[T12]],[[T3]]
-; MIPS32: srl [[T12]],[[T12]],0x8
-; MIPS32: andi [[T12]],[[T12]],0xff
-; MIPS32: andi [[T12]],[[T12]],0x1
-; MIPS32: sll [[T10]],[[T10]],0x1f
-; MIPS32: sll [[T12]],[[T12]],0x1f
-; MIPS32: sltu [[T12]],[[T12]],[[T10]]
-; MIPS32: xori [[T12]],[[T12]],0x1
-; MIPS32: andi [[T12]],[[T12]],0xff
-; MIPS32: sll [[T12]],[[T12]],0x8
-; MIPS32: lui [[T10]],0xffff
-; MIPS32: ori [[T10]],[[T10]],0xff
-; MIPS32: and [[T11]],[[T11]],[[T10]]
-; MIPS32: or [[T12]],[[T12]],[[T11]]
-; MIPS32: move [[T10]],a3
-; MIPS32: srl [[T10]],[[T10]],0x10
-; MIPS32: andi [[T10]],[[T10]],0xff
-; MIPS32: andi [[T10]],[[T10]],0x1
-; MIPS32: move [[T11]],[[T3]]
-; MIPS32: srl [[T11]],[[T11]],0x10
-; MIPS32: andi [[T11]],[[T11]],0xff
-; MIPS32: andi [[T11]],[[T11]],0x1
-; MIPS32: sll [[T10]],[[T10]],0x1f
-; MIPS32: sll [[T11]],[[T11]],0x1f
-; MIPS32: sltu [[T11]],[[T11]],[[T10]]
-; MIPS32: xori [[T11]],[[T11]],0x1
-; MIPS32: andi [[T11]],[[T11]],0xff
-; MIPS32: sll [[T11]],[[T11]],0x10
-; MIPS32: lui [[T10]],0xff00
-; MIPS32: ori [[T10]],[[T10]],0xffff
-; MIPS32: and [[T12]],[[T12]],[[T10]]
-; MIPS32: or [[T11]],[[T11]],[[T12]]
-; MIPS32: srl [[T13:.*]],a3,0x18
-; MIPS32: andi [[T13]],[[T13]],0x1
-; MIPS32: srl [[T3]],[[T3]],0x18
-; MIPS32: andi [[T3]],[[T3]],0x1
-; MIPS32: sll [[T13]],[[T13]],0x1f
-; MIPS32: sll [[T3]],[[T3]],0x1f
-; MIPS32: sltu [[T3]],[[T3]],[[T13]]
-; MIPS32: xori [[T3]],[[T3]],0x1
-; MIPS32: sll [[T3]],[[T3]],0x18
-; MIPS32: sll [[T11]],[[T11]],0x8
-; MIPS32: srl [[T11]],[[T11]],0x8
-; MIPS32: or [[T3]],[[T3]],[[T11]]
-; MIPS32: move a0,[[T2]]
-; MIPS32: move a1,[[T3]]
-}
-
-define internal <16 x i1> @test_icmp_v16i1_ult(<16 x i1> %a, <16 x i1> %b) {
-entry:
- %res = icmp ult <16 x i1> %a, %b
- ret <16 x i1> %res
-; CHECK-LABEL: test_icmp_v16i1_ult
-; CHECK: pxor
-; CHECK: pcmpgtb
-
-; MIPS32-LABEL: test_icmp_v16i1_ult
-; MIPS32: lw [[T0:.*]],
-; MIPS32: lw [[T1:.*]],
-; MIPS32: lw [[T2:.*]],
-; MIPS32: lw [[T3:.*]],
-; MIPS32: move [[T4:.*]],zero
-; MIPS32: move [[T5:.*]],zero
-; MIPS32: move [[T6:.*]],zero
-; MIPS32: move [[T7:.*]],zero
-; MIPS32: move [[T8:.*]],a0
-; MIPS32: andi [[T8]],[[T8]],0xff
-; MIPS32: andi [[T8]],[[T8]],0x1
-; MIPS32: move [[T9:.*]],[[T0]]
-; MIPS32: andi [[T9]],[[T9]],0xff
-; MIPS32: andi [[T9]],[[T9]],0x1
-; MIPS32: sll [[T8]],[[T8]],0x1f
-; MIPS32: sll [[T9]],[[T9]],0x1f
-; MIPS32: sltu [[T8]],[[T8]],[[T9]]
-; MIPS32: andi [[T8]],[[T8]],0xff
-; MIPS32: srl [[T4]],[[T4]],0x8
-; MIPS32: sll [[T4]],[[T4]],0x8
-; MIPS32: or [[T8]],[[T8]],[[T4]]
-; MIPS32: move [[T4]],a0
-; MIPS32: srl [[T4]],[[T4]],0x8
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: andi [[T4]],[[T4]],0x1
-; MIPS32: move [[T9]],[[T0]]
-; MIPS32: srl [[T9]],[[T9]],0x8
-; MIPS32: andi [[T9]],[[T9]],0xff
-; MIPS32: andi [[T9]],[[T9]],0x1
-; MIPS32: sll [[T4]],[[T4]],0x1f
-; MIPS32: sll [[T9]],[[T9]],0x1f
-; MIPS32: sltu [[T4]],[[T4]],[[T9]]
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: sll [[T4]],[[T4]],0x8
-; MIPS32: lui [[T9]],0xffff
-; MIPS32: ori [[T9]],[[T9]],0xff
-; MIPS32: and [[T8]],[[T8]],[[T9]]
-; MIPS32: or [[T4]],[[T4]],[[T8]]
-; MIPS32: move [[T8]],a0
-; MIPS32: srl [[T8]],[[T8]],0x10
-; MIPS32: andi [[T8]],[[T8]],0xff
-; MIPS32: andi [[T8]],[[T8]],0x1
-; MIPS32: move [[T9]],[[T0]]
-; MIPS32: srl [[T9]],[[T9]],0x10
-; MIPS32: andi [[T9]],[[T9]],0xff
-; MIPS32: andi [[T9]],[[T9]],0x1
-; MIPS32: sll [[T8]],[[T8]],0x1f
-; MIPS32: sll [[T9]],[[T9]],0x1f
-; MIPS32: sltu [[T8]],[[T8]],[[T9]]
-; MIPS32: andi [[T8]],[[T8]],0xff
-; MIPS32: sll [[T8]],[[T8]],0x10
-; MIPS32: lui [[T9]],0xff00
-; MIPS32: ori [[T9]],[[T9]],0xffff
-; MIPS32: and [[T4]],[[T4]],[[T9]]
-; MIPS32: or [[T8]],[[T8]],[[T4]]
-; MIPS32: srl [[T10:.*]],a0,0x18
-; MIPS32: andi [[T10]],[[T10]],0x1
-; MIPS32: srl [[T0]],[[T0]],0x18
-; MIPS32: andi [[T0]],[[T0]],0x1
-; MIPS32: sll [[T10]],[[T10]],0x1f
-; MIPS32: sll [[T0]],[[T0]],0x1f
-; MIPS32: sltu [[T10]],[[T10]],[[T0]]
-; MIPS32: sll [[T10]],[[T10]],0x18
-; MIPS32: sll [[T8]],[[T8]],0x8
-; MIPS32: srl [[T8]],[[T8]],0x8
-; MIPS32: or [[T10]],[[T10]],[[T8]]
-; MIPS32: move [[T0]],a1
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: andi [[T0]],[[T0]],0x1
-; MIPS32: move [[T4]],[[T1]]
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: andi [[T4]],[[T4]],0x1
-; MIPS32: sll [[T0]],[[T0]],0x1f
-; MIPS32: sll [[T4]],[[T4]],0x1f
-; MIPS32: sltu [[T0]],[[T0]],[[T4]]
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: srl [[T5]],[[T5]],0x8
-; MIPS32: sll [[T5]],[[T5]],0x8
-; MIPS32: or [[T0]],[[T0]],[[T5]]
-; MIPS32: move [[T4]],a1
-; MIPS32: srl [[T4]],[[T4]],0x8
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: andi [[T4]],[[T4]],0x1
-; MIPS32: move [[T5]],[[T1]]
-; MIPS32: srl [[T5]],[[T5]],0x8
-; MIPS32: andi [[T5]],[[T5]],0xff
-; MIPS32: andi [[T5]],[[T5]],0x1
-; MIPS32: sll [[T4]],[[T4]],0x1f
-; MIPS32: sll [[T5]],[[T5]],0x1f
-; MIPS32: sltu [[T4]],[[T4]],[[T5]]
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: sll [[T4]],[[T4]],0x8
-; MIPS32: lui [[T5]],0xffff
-; MIPS32: ori [[T5]],[[T5]],0xff
-; MIPS32: and [[T0]],[[T0]],[[T5]]
-; MIPS32: or [[T4]],[[T4]],[[T0]]
-; MIPS32: move [[T0]],a1
-; MIPS32: srl [[T0]],[[T0]],0x10
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: andi [[T0]],[[T0]],0x1
-; MIPS32: move [[T5]],[[T1]]
-; MIPS32: srl [[T5]],[[T5]],0x10
-; MIPS32: andi [[T5]],[[T5]],0xff
-; MIPS32: andi [[T5]],[[T5]],0x1
-; MIPS32: sll [[T0]],[[T0]],0x1f
-; MIPS32: sll [[T5]],[[T5]],0x1f
-; MIPS32: sltu [[T0]],[[T0]],[[T5]]
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: sll [[T0]],[[T0]],0x10
-; MIPS32: lui [[T5]],0xff00
-; MIPS32: ori [[T5]],[[T5]],0xffff
-; MIPS32: and [[T4]],[[T4]],[[T5]]
-; MIPS32: or [[T0]],[[T0]],[[T4]]
-; MIPS32: srl [[T11:.*]],a1,0x18
-; MIPS32: andi [[T11]],[[T11]],0x1
-; MIPS32: srl [[T1]],[[T1]],0x18
-; MIPS32: andi [[T1]],[[T1]],0x1
-; MIPS32: sll [[T11]],[[T11]],0x1f
-; MIPS32: sll [[T1]],[[T1]],0x1f
-; MIPS32: sltu [[T11]],[[T11]],[[T1]]
-; MIPS32: sll [[T11]],[[T11]],0x18
-; MIPS32: sll [[T0]],[[T0]],0x8
-; MIPS32: srl [[T0]],[[T0]],0x8
-; MIPS32: or [[T11]],[[T11]],[[T0]]
-; MIPS32: move [[T0]],a2
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: andi [[T0]],[[T0]],0x1
-; MIPS32: move [[T1]],[[T2]]
-; MIPS32: andi [[T1]],[[T1]],0xff
-; MIPS32: andi [[T1]],[[T1]],0x1
-; MIPS32: sll [[T0]],[[T0]],0x1f
-; MIPS32: sll [[T1]],[[T1]],0x1f
-; MIPS32: sltu [[T0]],[[T0]],[[T1]]
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: srl [[T6]],[[T6]],0x8
-; MIPS32: sll [[T6]],[[T6]],0x8
-; MIPS32: or [[T0]],[[T0]],[[T6]]
-; MIPS32: move [[T1]],a2
-; MIPS32: srl [[T1]],[[T1]],0x8
-; MIPS32: andi [[T1]],[[T1]],0xff
-; MIPS32: andi [[T1]],[[T1]],0x1
-; MIPS32: move [[T4]],[[T2]]
-; MIPS32: srl [[T4]],[[T4]],0x8
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: andi [[T4]],[[T4]],0x1
-; MIPS32: sll [[T1]],[[T1]],0x1f
-; MIPS32: sll [[T4]],[[T4]],0x1f
-; MIPS32: sltu [[T1]],[[T1]],[[T4]]
-; MIPS32: andi [[T1]],[[T1]],0xff
-; MIPS32: sll [[T1]],[[T1]],0x8
-; MIPS32: lui [[T4]],0xffff
-; MIPS32: ori [[T4]],[[T4]],0xff
-; MIPS32: and [[T0]],[[T0]],[[T4]]
-; MIPS32: or [[T1]],[[T1]],[[T0]]
-; MIPS32: move [[T0]],a2
-; MIPS32: srl [[T0]],[[T0]],0x10
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: andi [[T0]],[[T0]],0x1
-; MIPS32: move [[T4]],[[T2]]
-; MIPS32: srl [[T4]],[[T4]],0x10
-; MIPS32: andi [[T4]],[[T4]],0xff
-; MIPS32: andi [[T4]],[[T4]],0x1
-; MIPS32: sll [[T0]],[[T0]],0x1f
-; MIPS32: sll [[T4]],[[T4]],0x1f
-; MIPS32: sltu [[T0]],[[T0]],[[T4]]
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: sll [[T0]],[[T0]],0x10
-; MIPS32: lui [[T4]],0xff00
-; MIPS32: ori [[T4]],[[T4]],0xffff
-; MIPS32: and [[T1]],[[T1]],[[T4]]
-; MIPS32: or [[T0]],[[T0]],[[T1]]
-; MIPS32: srl [[T12:.*]],a2,0x18
-; MIPS32: andi [[T12]],[[T12]],0x1
-; MIPS32: srl [[T2]],[[T2]],0x18
-; MIPS32: andi [[T2]],[[T2]],0x1
-; MIPS32: sll [[T12]],[[T12]],0x1f
-; MIPS32: sll [[T2]],[[T2]],0x1f
-; MIPS32: sltu [[T12]],[[T12]],[[T2]]
-; MIPS32: sll [[T12]],[[T12]],0x18
-; MIPS32: sll [[T0]],[[T0]],0x8
-; MIPS32: srl [[T0]],[[T0]],0x8
-; MIPS32: or [[T12]],[[T12]],[[T0]]
-; MIPS32: move [[T0]],a3
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: andi [[T0]],[[T0]],0x1
-; MIPS32: move [[T1]],[[T3]]
-; MIPS32: andi [[T1]],[[T1]],0xff
-; MIPS32: andi [[T1]],[[T1]],0x1
-; MIPS32: sll [[T0]],[[T0]],0x1f
-; MIPS32: sll [[T1]],[[T1]],0x1f
-; MIPS32: sltu [[T0]],[[T0]],[[T1]]
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: srl [[T7]],[[T7]],0x8
-; MIPS32: sll [[T7]],[[T7]],0x8
-; MIPS32: or [[T0]],[[T0]],[[T7]]
-; MIPS32: move [[T1]],a3
-; MIPS32: srl [[T1]],[[T1]],0x8
-; MIPS32: andi [[T1]],[[T1]],0xff
-; MIPS32: andi [[T1]],[[T1]],0x1
-; MIPS32: move [[T2]],[[T3]]
-; MIPS32: srl [[T2]],[[T2]],0x8
-; MIPS32: andi [[T2]],[[T2]],0xff
-; MIPS32: andi [[T2]],[[T2]],0x1
-; MIPS32: sll [[T1]],[[T1]],0x1f
-; MIPS32: sll [[T2]],[[T2]],0x1f
-; MIPS32: sltu [[T1]],[[T1]],[[T2]]
-; MIPS32: andi [[T1]],[[T1]],0xff
-; MIPS32: sll [[T1]],[[T1]],0x8
-; MIPS32: lui [[T2]],0xffff
-; MIPS32: ori [[T2]],[[T2]],0xff
-; MIPS32: and [[T0]],[[T0]],[[T2]]
-; MIPS32: or [[T1]],[[T1]],[[T0]]
-; MIPS32: move [[T0]],a3
-; MIPS32: srl [[T0]],[[T0]],0x10
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: andi [[T0]],[[T0]],0x1
-; MIPS32: move [[T2]],[[T3]]
-; MIPS32: srl [[T2]],[[T2]],0x10
-; MIPS32: andi [[T2]],[[T2]],0xff
-; MIPS32: andi [[T2]],[[T2]],0x1
-; MIPS32: sll [[T0]],[[T0]],0x1f
-; MIPS32: sll [[T2]],[[T2]],0x1f
-; MIPS32: sltu [[T0]],[[T0]],[[T2]]
-; MIPS32: andi [[T0]],[[T0]],0xff
-; MIPS32: sll [[T0]],[[T0]],0x10
-; MIPS32: lui [[T2]],0xff00
-; MIPS32: ori [[T2]],[[T2]],0xffff
-; MIPS32: and [[T1]],[[T1]],[[T2]]
-; MIPS32: or [[T0]],[[T0]],[[T1]]
-; MIPS32: srl [[T13:.*]],a3,0x18
-; MIPS32: andi [[T13]],[[T13]],0x1
-; MIPS32: srl [[T3]],[[T3]],0x18
-; MIPS32: andi [[T3]],[[T3]],0x1
-; MIPS32: sll [[T13]],[[T13]],0x1f
-; MIPS32: sll [[T3]],[[T3]],0x1f
-; MIPS32: sltu [[T13]],[[T13]],[[T3]]
-; MIPS32: sll [[T13]],[[T13]],0x18
-; MIPS32: sll [[T0]],[[T0]],0x8
-; MIPS32: srl [[T0]],[[T0]],0x8
-; MIPS32: or [[T13]],[[T13]],[[T0]]
-; MIPS32: move v0,[[T10]]
-; MIPS32: move v1,[[T11]]
-; MIPS32: move a0,[[T12]]
-; MIPS32: move a1,[[T13]]
-}
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/vector-mips.ll b/third_party/subzero/tests_lit/llvm2ice_tests/vector-mips.ll
deleted file mode 100644
index f937b0c..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/vector-mips.ll
+++ /dev/null
@@ -1,246 +0,0 @@
-; This test checks support for vector type in MIPS.
-
-; RUN: %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command %p2i --filetype=asm --assemble --disassemble --target mips32\
-; RUN: -i %s --args -O2 \
-; RUN: | %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command FileCheck --check-prefix MIPS32 %s
-
-define internal i32 @test_0(<4 x i32> %a) #0 {
-entry:
- %vecext = extractelement <4 x i32> %a, i32 0
- ret i32 %vecext
-}
-; MIPS32-LABEL: test_0
-; MIPS32: move v0,a0
-
-define internal i32 @test_1(<4 x i32> %a) #0 {
-entry:
- %vecext = extractelement <4 x i32> %a, i32 1
- ret i32 %vecext
-}
-; MIPS32-LABEL: test_1
-; MIPS32: move v0,a1
-
-define internal i32 @test_2(<4 x i32> %a) #0 {
-entry:
- %vecext = extractelement <4 x i32> %a, i32 2
- ret i32 %vecext
-}
-; MIPS32-LABEL: test_2
-; MIPS32: move v0,a2
-
-define internal i32 @test_3(<4 x i32> %a) #0 {
-entry:
- %vecext = extractelement <4 x i32> %a, i32 3
- ret i32 %vecext
-}
-; MIPS32-LABEL: test_3
-; MIPS32: move v0,a3
-
-define internal float @test_4(<4 x float> %a) #0 {
-entry:
- %vecext = extractelement <4 x float> %a, i32 1
- ret float %vecext
-}
-; MIPS32-LABEL: test_4
-; MIPS32: mtc1 a1,$f0
-
-define internal float @test_5(<4 x float> %a) #0 {
-entry:
- %vecext = extractelement <4 x float> %a, i32 2
- ret float %vecext
-}
-; MIPS32-LABEL: test_5
-; MIPS32: mtc1 a2,$f0
-
-define internal i32 @test_6(<16 x i8> %a) #0 {
-entry:
- %vecext = extractelement <16 x i8> %a, i32 0
- %conv = sext i8 %vecext to i32
- ret i32 %conv
-}
-; MIPS32-LABEL: test_6
-; MIPS32: andi a0,a0,0xff
-; MIPS32: sll a0,a0,0x18
-; MIPS32: sra a0,a0,0x18
-; MIPS32: move v0,a0
-
-define internal i32 @test_7(<16 x i8> %a) #0 {
-entry:
- %vecext = extractelement <16 x i8> %a, i32 15
- %conv = sext i8 %vecext to i32
- ret i32 %conv
-}
-; MIPS32-LABEL: test_7
-; MIPS32: srl a3,a3,0x18
-; MIPS32: sll a3,a3,0x18
-; MIPS32: sra a3,a3,0x18
-; MIPS32: move v0,a3
-
-define internal i32 @test_8(<8 x i16> %a) #0 {
-entry:
- %vecext = extractelement <8 x i16> %a, i32 0
- %conv = sext i16 %vecext to i32
- ret i32 %conv
-}
-; MIPS32-LABEL: test_8
-; MIPS32: andi a0,a0,0xffff
-; MIPS32: sll a0,a0,0x10
-; MIPS32: sra a0,a0,0x10
-; MIPS32: move v0,a0
-
-define internal i32 @test_9(<8 x i16> %a) #0 {
-entry:
- %vecext = extractelement <8 x i16> %a, i32 7
- %conv = sext i16 %vecext to i32
- ret i32 %conv
-}
-; MIPS32-LABEL: test_9
-; MIPS32: srl a3,a3,0x10
-; MIPS32: sll a3,a3,0x10
-; MIPS32: sra a3,a3,0x10
-; MIPS32: move v0,a3
-
-define internal i32 @test_10(<4 x i1> %a) #0 {
-entry:
- %vecext = extractelement <4 x i1> %a, i32 0
- %conv = sext i1 %vecext to i32
- ret i32 %conv
-}
-; MIPS32-LABEL: test_10
-; MIPS32: andi a0,a0,0x1
-; MIPS32: sll a0,a0,0x1f
-; MIPS32: sra a0,a0,0x1f
-; MIPS32: move v0,a0
-
-define internal i32 @test_11(<4 x i1> %a) #0 {
-entry:
- %vecext = extractelement <4 x i1> %a, i32 2
- %conv = sext i1 %vecext to i32
- ret i32 %conv
-}
-; MIPS32-LABEL: test_11
-; MIPS32: andi a2,a2,0x1
-; MIPS32: sll a2,a2,0x1f
-; MIPS32: sra a2,a2,0x1f
-; MIPS32: move v0,a2
-
-define internal i32 @test_12(<8 x i1> %a) #0 {
-entry:
- %vecext = extractelement <8 x i1> %a, i32 0
- %conv = sext i1 %vecext to i32
- ret i32 %conv
-}
-; MIPS32-LABEL: test_12
-; MIPS32: andi a0,a0,0xffff
-; MIPS32: andi a0,a0,0x1
-; MIPS32: sll a0,a0,0x1f
-; MIPS32: sra a0,a0,0x1f
-; MIPS32: move v0,a0
-
-define internal i32 @test_13(<8 x i1> %a) #0 {
-entry:
- %vecext = extractelement <8 x i1> %a, i32 7
- %conv = sext i1 %vecext to i32
- ret i32 %conv
-}
-; MIPS32-LABEL: test_13
-; MIPS32: srl a3,a3,0x10
-; MIPS32: andi a3,a3,0x1
-; MIPS32: sll a3,a3,0x1f
-; MIPS32: sra a3,a3,0x1f
-; MIPS32: move v0,a3
-
-define internal i32 @test_14(<16 x i1> %a) #0 {
-entry:
- %vecext = extractelement <16 x i1> %a, i32 0
- %conv = sext i1 %vecext to i32
- ret i32 %conv
-}
-; MIPS32-LABEL: test_14
-; MIPS32: andi a0,a0,0xff
-; MIPS32: andi a0,a0,0x1
-; MIPS32: sll a0,a0,0x1f
-; MIPS32: sra a0,a0,0x1f
-; MIPS32: move v0,a0
-
-define internal i32 @test_15(<16 x i1> %a) #0 {
-entry:
- %vecext = extractelement <16 x i1> %a, i32 15
- %conv = sext i1 %vecext to i32
- ret i32 %conv
-}
-; MIPS32-LABEL: test_15
-; MIPS32: srl a3,a3,0x18
-; MIPS32: andi a3,a3,0x1
-; MIPS32: sll a3,a3,0x1f
-; MIPS32: sra a3,a3,0x1f
-; MIPS32: move v0,a3
-
-define internal i32 @test_16(i32 %i, <4 x i32> %a) #0 {
-entry:
- %vecext = extractelement <4 x i32> %a, i32 0
- %add = add nsw i32 %vecext, %i
- ret i32 %add
-}
-; MIPS32-LABEL: test_16
-; MIPS32: addu a2,a2,a0
-; MIPS32: move v0,a2
-
-define internal i32 @test_17(i32 %i, <4 x i32> %a) #0 {
-entry:
- %vecext = extractelement <4 x i32> %a, i32 3
- %add = add nsw i32 %vecext, %i
- ret i32 %add
-}
-; MIPS32-LABEL: test_17
-; MIPS32: lw v0,{{.*}}(sp)
-; MIPS32: addu v0,v0,a0
-
-define internal float @test_18(float %f, <4 x float> %a) #0 {
-entry:
- %vecext = extractelement <4 x float> %a, i32 0
- %add = fadd float %vecext, %f
- ret float %add
-}
-; MIPS32-LABEL: test_18
-; MIPS32: mtc1 a2,$f0
-; MIPS32: add.s $f0,$f0,$f12
-
-define internal float @test_19(float %f, <4 x float> %a) #0 {
-entry:
- %vecext = extractelement <4 x float> %a, i32 3
- %add = fadd float %vecext, %f
- ret float %add
-}
-; MIPS32-LABEL: test_19
-; MIPS32: lw v0,{{.*}}(sp)
-; MIPS32: mtc1 v0,$f0
-; MIPS32: add.s $f0,$f0,$f12
-
-define internal <4 x float> @test_20(i32 %addr_i, <4 x float> %addend) {
-entry:
- %addr = inttoptr i32 %addr_i to <4 x float>*
- %loaded = load <4 x float>, <4 x float>* %addr, align 4
- %result = fadd <4 x float> %addend, %loaded
- ret <4 x float> %result
-}
-; MIPS32-LABEL: test_20
-; MIPS32: add.s
-; MIPS32: add.s
-; MIPS32: add.s
-; MIPS32: add.s
-
-define internal <4 x i32> @test_21(i32 %addr_i, <4 x i32> %addend) {
-entry:
- %addr = inttoptr i32 %addr_i to <4 x i32>*
- %loaded = load <4 x i32>, <4 x i32>* %addr, align 4
- %result = add <4 x i32> %addend, %loaded
- ret <4 x i32> %result
-}
-; MIPS32-LABEL: test_21
-; MIPS32: add
-; MIPS32: add
-; MIPS32: add
-; MIPS32: add
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/vector-ops.ll b/third_party/subzero/tests_lit/llvm2ice_tests/vector-ops.ll
deleted file mode 100644
index 5145ad3..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/vector-ops.ll
+++ /dev/null
@@ -1,371 +0,0 @@
-; This checks support for insertelement and extractelement.
-
-; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 \
-; RUN: | FileCheck %s
-; RUN: %p2i -i %s --filetype=obj --disassemble --args -Om1 \
-; RUN: | FileCheck %s
-; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 -mattr=sse4.1 \
-; RUN: | FileCheck --check-prefix=SSE41 %s
-; RUN: %p2i -i %s --filetype=obj --disassemble --args -Om1 -mattr=sse4.1 \
-; RUN: | FileCheck --check-prefix=SSE41 %s
-
-; RUN: %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command %p2i --filetype=asm --assemble --disassemble --target mips32\
-; RUN: -i %s --args -O2 \
-; RUN: | %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command FileCheck --check-prefix MIPS32 %s
-
-; insertelement operations
-
-define internal <4 x float> @insertelement_v4f32_0(<4 x float> %vec,
- float %elt) {
-entry:
- %res = insertelement <4 x float> %vec, float %elt, i32 0
- ret <4 x float> %res
-; CHECK-LABEL: insertelement_v4f32_0
-; CHECK: movss
-
-; SSE41-LABEL: insertelement_v4f32_0
-; SSE41: insertps {{.*}},{{.*}},0x0
-
-; *** a0 - implicit return <4 x float>
-; *** a1 - unused due to alignment of %vec
-; *** a2:a3:sp[16]:s[20] - %vec
-; *** sp[24] - %elt
-; MIPS32-LABEL: insertelement_v4f32_0
-; *** Load element 2 and 3 of %vec
-; MIPS32: lw [[BV_E2:.*]],
-; MIPS32: lw [[BV_E3:.*]],
-; *** Load %elt
-; MIPS32: lwc1 [[ELT:.*]],
-; *** Insert %elt at %vec[0]
-; MIPS32: mfc1 [[RV_E0:.*]],[[ELT]]
-; MIPS32: move [[RET_PTR:.*]],a0
-; MIPS32: sw [[RV_E0]],0([[RET_PTR]])
-; MIPS32: sw a3,4([[RET_PTR]])
-; MIPS32: sw [[BV_E2]],8([[RET_PTR]])
-; MIPS32: sw [[BV_E3]],12([[RET_PTR]])
-}
-
-define internal <4 x i32> @insertelement_v4i32_0(<4 x i32> %vec, i32 %elt) {
-entry:
- %res = insertelement <4 x i32> %vec, i32 %elt, i32 0
- ret <4 x i32> %res
-; CHECK-LABEL: insertelement_v4i32_0
-; CHECK: movd xmm{{.*}},
-; CHECK: movss
-
-; SSE41-LABEL: insertelement_v4i32_0
-; SSE41: pinsrd {{.*}},{{.*}},0x0
-
-; *** a0:a1:a2:a3 - %vec
-; *** sp[16] - %elt
-; MIPS32-LABEL: insertelement_v4i32_0
-; *** Load %elt
-; MIPS32: lw v0,16(sp)
-; MIPS32: move v1,a1
-; MIPS32: move a0,a2
-; MIPS32: move a1,a3
-}
-
-
-define internal <4 x float> @insertelement_v4f32_1(<4 x float> %vec,
- float %elt) {
-entry:
- %res = insertelement <4 x float> %vec, float %elt, i32 1
- ret <4 x float> %res
-; CHECK-LABEL: insertelement_v4f32_1
-; CHECK: shufps
-; CHECK: shufps
-
-; SSE41-LABEL: insertelement_v4f32_1
-; SSE41: insertps {{.*}},{{.*}},0x10
-
-; MIPS32-LABEL: insertelement_v4f32_1
-; MIPS32: lw [[VEC_E2:.*]],16(sp)
-; MIPS32: lw [[VEC_E3:.*]],20(sp)
-; MIPS32: lwc1 [[ELT:.*]],24(sp)
-; MIPS32: mfc1 [[R_E1:.*]],[[ELT]]
-; MIPS32: move [[PTR:.*]],a0
-; MIPS32: sw a2,0([[PTR]])
-; MIPS32: sw [[R_E1]],4([[PTR]])
-; MIPS32: sw [[VEC_E2]],8([[PTR]])
-; MIPS32: sw [[VEC_E3]],12([[PTR]])
-}
-
-define internal <4 x i32> @insertelement_v4i32_1(<4 x i32> %vec, i32 %elt) {
-entry:
- %res = insertelement <4 x i32> %vec, i32 %elt, i32 1
- ret <4 x i32> %res
-; CHECK-LABEL: insertelement_v4i32_1
-; CHECK: shufps
-; CHECK: shufps
-
-; SSE41-LABEL: insertelement_v4i32_1
-; SSE41: pinsrd {{.*}},{{.*}},0x1
-
-; MIPS32-LABEL: insertelement_v4i32_1
-; MIPS32: lw [[ELT:.*]],16(sp)
-; MIPS32: move v1,[[ELT]]
-; MIPS32: move v0,a0
-; MIPS32: move a0,a2
-; MIPS32: move a1,a3
-}
-
-define internal <8 x i16> @insertelement_v8i16(<8 x i16> %vec, i32 %elt.arg) {
-entry:
- %elt = trunc i32 %elt.arg to i16
- %res = insertelement <8 x i16> %vec, i16 %elt, i32 1
- ret <8 x i16> %res
-; CHECK-LABEL: insertelement_v8i16
-; CHECK: pinsrw
-
-; SSE41-LABEL: insertelement_v8i16
-; SSE41: pinsrw
-
-; MIPS32-LABEL: insertelement_v8i16
-; MIPS32: lw [[ELT:.*]],16(sp)
-; MIPS32: sll [[ELT]],[[ELT]],0x10
-; MIPS32: sll a0,a0,0x10
-; MIPS32: srl a0,a0,0x10
-; MIPS32: or v0,[[ELT]],a0
-; MIPS32: move v1,a1
-; MIPS32: move a0,a2
-; MIPS32: move a1,a3
-}
-
-define internal <16 x i8> @insertelement_v16i8(<16 x i8> %vec, i32 %elt.arg) {
-entry:
- %elt = trunc i32 %elt.arg to i8
- %res = insertelement <16 x i8> %vec, i8 %elt, i32 1
- ret <16 x i8> %res
-; CHECK-LABEL: insertelement_v16i8
-; CHECK: movups
-; CHECK: lea
-; CHECK: mov
-
-; SSE41-LABEL: insertelement_v16i8
-; SSE41: pinsrb
-
-; MIPS32-LABEL: insertelement_v16i8
-; MIPS32: lw [[ELT:.*]],16(sp)
-; MIPS32: andi [[ELT]],[[ELT]],0xff
-; MIPS32: sll [[ELT]],[[ELT]],0x8
-; MIPS32: lui [[T:.*]],0xffff
-; MIPS32: ori [[T]],[[T]],0xff
-; MIPS32: and a0,a0,[[T]]
-; MIPS32: or v0,v0,a0
-; MIPS32: move v1,a1
-; MIPS32: move a0,a2
-; MIPS32: move a1,a3
-}
-
-define internal <4 x i1> @insertelement_v4i1_0(<4 x i1> %vec, i32 %elt.arg) {
-entry:
- %elt = trunc i32 %elt.arg to i1
- %res = insertelement <4 x i1> %vec, i1 %elt, i32 0
- ret <4 x i1> %res
-; CHECK-LABEL: insertelement_v4i1_0
-; CHECK: movss
-
-; SSE41-LABEL: insertelement_v4i1_0
-; SSE41: pinsrd {{.*}},{{.*}},0x0
-
-; MIPS32-LABEL: insertelement_v4i1_0
-; MIPS32: lw v0,16(sp)
-; MIPS32: move v1,a1
-; MIPS32: move a0,a2
-; MIPS32: move a1,a3
-}
-
-define internal <4 x i1> @insertelement_v4i1_1(<4 x i1> %vec, i32 %elt.arg) {
-entry:
- %elt = trunc i32 %elt.arg to i1
- %res = insertelement <4 x i1> %vec, i1 %elt, i32 1
- ret <4 x i1> %res
-; CHECK-LABEL: insertelement_v4i1_1
-; CHECK: shufps
-; CHECK: shufps
-
-; SSE41-LABEL: insertelement_v4i1_1
-; SSE41: pinsrd {{.*}},{{.*}},0x1
-
-; MIPS32-LABEL: insertelement_v4i1_1
-; MIPS32: lw [[ELT:.*]],16(sp)
-; MIPS32: move v1,[[ELT]]
-; MIPS32: move v0,a0
-; MIPS32: move a0,a2
-; MIPS32: move a1,a3
-}
-
-define internal <8 x i1> @insertelement_v8i1(<8 x i1> %vec, i32 %elt.arg) {
-entry:
- %elt = trunc i32 %elt.arg to i1
- %res = insertelement <8 x i1> %vec, i1 %elt, i32 1
- ret <8 x i1> %res
-; CHECK-LABEL: insertelement_v8i1
-; CHECK: pinsrw
-
-; SSE41-LABEL: insertelement_v8i1
-; SSE41: pinsrw
-
-; MIPS32-LABEL: insertelement_v8i1
-; MIPS32: lw [[ELT:.*]],16(sp)
-; MIPS32: sll [[ELT]],[[ELT]],0x10
-; MIPS32: sll a0,a0,0x10
-; MIPS32: srl a0,a0,0x10
-; MIPS32: or v0,[[ELT]],a0
-; MIPS32: move v1,a1
-; MIPS32: move a0,a2
-; MIPS32: move a1,a3
-}
-
-define internal <16 x i1> @insertelement_v16i1(<16 x i1> %vec, i32 %elt.arg) {
-entry:
- %elt = trunc i32 %elt.arg to i1
- %res = insertelement <16 x i1> %vec, i1 %elt, i32 1
- ret <16 x i1> %res
-; CHECK-LABEL: insertelement_v16i1
-; CHECK: movups
-; CHECK: lea
-; CHECK: mov
-
-; SSE41-LABEL: insertelement_v16i1
-; SSE41: pinsrb
-
-; MIPS32-LABEL: insertelement_v16i1
-; MIPS32: lw [[ELT:.*]],16(sp)
-; MIPS32: andi [[ELT]],[[ELT]],0xff
-; MIPS32: sll [[ELT]],[[ELT]],0x8
-; MIPS32: lui [[T:.*]],0xffff
-; MIPS32: ori [[T]],[[T]],0xff
-; MIPS32: and a0,a0,[[T]]
-; MIPS32: or v0,[[ELT]],a0
-; MIPS32: move v1,a1
-; MIPS32: move a0,a2
-; MIPS32: move a1,a3
-}
-
-; extractelement operations
-
-define internal float @extractelement_v4f32(<4 x float> %vec) {
-entry:
- %res = extractelement <4 x float> %vec, i32 1
- ret float %res
-; CHECK-LABEL: extractelement_v4f32
-; CHECK: pshufd
-
-; SSE41-LABEL: extractelement_v4f32
-; SSE41: pshufd
-
-; MIPS32-LABEL: extractelement_v4f32
-; MIPS32: mtc1 a1,$f0
-}
-
-define internal i32 @extractelement_v4i32(<4 x i32> %vec) {
-entry:
- %res = extractelement <4 x i32> %vec, i32 1
- ret i32 %res
-; CHECK-LABEL: extractelement_v4i32
-; CHECK: pshufd
-; CHECK: movd {{.*}},xmm
-
-; SSE41-LABEL: extractelement_v4i32
-; SSE41: pextrd
-
-; MIPS32-LABEL: extractelement_v4i32
-; MIPS32L move v0,a1
-}
-
-define internal i32 @extractelement_v8i16(<8 x i16> %vec) {
-entry:
- %res = extractelement <8 x i16> %vec, i32 1
- %res.ext = zext i16 %res to i32
- ret i32 %res.ext
-; CHECK-LABEL: extractelement_v8i16
-; CHECK: pextrw
-
-; SSE41-LABEL: extractelement_v8i16
-; SSE41: pextrw
-
-; MIPS32-LABEL: extractelement_v8i16
-; MIPS32: srl a0,a0,0x10
-; MIPS32: andi a0,a0,0xffff
-; MIPS32: move v0,a0
-}
-
-define internal i32 @extractelement_v16i8(<16 x i8> %vec) {
-entry:
- %res = extractelement <16 x i8> %vec, i32 1
- %res.ext = zext i8 %res to i32
- ret i32 %res.ext
-; CHECK-LABEL: extractelement_v16i8
-; CHECK: movups
-; CHECK: lea
-; CHECK: mov
-
-; SSE41-LABEL: extractelement_v16i8
-; SSE41: pextrb
-
-; MIPS32-LABEL: extractelement_v16i8
-; MIPS32: srl a0,a0,0x8
-; MIPS32: andi a0,a0,0xff
-; MIPS32: andi a0,a0,0xff
-; MIPS32: move v0,a0
-}
-
-define internal i32 @extractelement_v4i1(<4 x i1> %vec) {
-entry:
- %res = extractelement <4 x i1> %vec, i32 1
- %res.ext = zext i1 %res to i32
- ret i32 %res.ext
-; CHECK-LABEL: extractelement_v4i1
-; CHECK: pshufd
-
-; SSE41-LABEL: extractelement_v4i1
-; SSE41: pextrd
-
-; MIPS32-LABEL: extractelement_v4i1
-; MIPS32: andi a1,a1,0x1
-; MIPS32: andi a1,a1,0x1
-; MIPS32: move v0,a1
-}
-
-define internal i32 @extractelement_v8i1(<8 x i1> %vec) {
-entry:
- %res = extractelement <8 x i1> %vec, i32 1
- %res.ext = zext i1 %res to i32
- ret i32 %res.ext
-; CHECK-LABEL: extractelement_v8i1
-; CHECK: pextrw
-
-; SSE41-LABEL: extractelement_v8i1
-; SSE41: pextrw
-
-; MIPS32-LABEL: extractelement_v8i1
-; MIPS32: srl a0,a0,0x10
-; MIPS32: andi a0,a0,0x1
-; MIPS32: andi a0,a0,0x1
-; MIPS32: move v0,a0
-}
-
-define internal i32 @extractelement_v16i1(<16 x i1> %vec) {
-entry:
- %res = extractelement <16 x i1> %vec, i32 1
- %res.ext = zext i1 %res to i32
- ret i32 %res.ext
-; CHECK-LABEL: extractelement_v16i1
-; CHECK: movups
-; CHECK: lea
-; CHECK: mov
-
-; SSE41-LABEL: extractelement_v16i1
-; SSE41: pextrb
-
-; MIPS32-LABEL: extractelement_v16i1
-; MIPS32: srl a0,a0,0x8
-; MIPS32: andi a0,a0,0xff
-; MIPS32: andi a0,a0,0x1
-; MIPS32: andi a0,a0,0x1
-; MIPS32: move v0,a0
-}
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/vector-select.ll b/third_party/subzero/tests_lit/llvm2ice_tests/vector-select.ll
deleted file mode 100644
index 0d1fa92..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/vector-select.ll
+++ /dev/null
@@ -1,983 +0,0 @@
-; This file tests support for the select instruction with vector valued inputs.
-
-; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 \
-; RUN: | FileCheck %s
-; RUN: %p2i -i %s --filetype=obj --disassemble --args -Om1 \
-; RUN: | FileCheck %s
-; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 -mattr=sse4.1 \
-; RUN: | FileCheck --check-prefix=SSE41 %s
-; RUN: %p2i -i %s --filetype=obj --disassemble --args -Om1 -mattr=sse4.1 \
-; RUN: | FileCheck --check-prefix=SSE41 %s
-
-; RUN: %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command %p2i --filetype=asm --assemble --disassemble --target mips32\
-; RUN: -i %s --args -O2 \
-; RUN: | %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command FileCheck --check-prefix MIPS32 %s
-
-define internal <16 x i8> @test_select_v16i8(<16 x i1> %cond, <16 x i8> %arg1,
- <16 x i8> %arg2) {
-entry:
- %res = select <16 x i1> %cond, <16 x i8> %arg1, <16 x i8> %arg2
- ret <16 x i8> %res
-; CHECK-LABEL: test_select_v16i8
-; CHECK: pand
-; CHECK: pandn
-; CHECK: por
-
-; SSE41-LABEL: test_select_v16i8
-; SSE41: pblendvb xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}}
-
-; MIPS32-LABEL: test_select_v16i8
-; MIPS32: addiu [[T0:.*]],sp,-32
-; MIPS32: sw [[T1:.*]],
-; MIPS32: sw [[T2:.*]],
-; MIPS32: sw [[T3:.*]],
-; MIPS32: sw [[T4:.*]],
-; MIPS32: sw [[T5:.*]],
-; MIPS32: lw [[T6:.*]],
-; MIPS32: lw [[T7:.*]],
-; MIPS32: lw [[T8:.*]],
-; MIPS32: lw [[T9:.*]],
-; MIPS32: lw [[T10:.*]],
-; MIPS32: lw [[T11:.*]],
-; MIPS32: lw [[T12:.*]],
-; MIPS32: lw [[T13:.*]],
-; MIPS32: move [[T14:.*]],zero
-; MIPS32: move [[T15:.*]],zero
-; MIPS32: move [[T5]],zero
-; MIPS32: move [[T4]],zero
-; MIPS32: move [[T3]],a0
-; MIPS32: andi [[T3]],[[T3]],0xff
-; MIPS32: andi [[T3]],[[T3]],0x1
-; MIPS32: move [[T2]],[[T6]]
-; MIPS32: andi [[T2]],[[T2]],0xff
-; MIPS32: move [[T1]],[[T10]]
-; MIPS32: andi [[T1]],[[T1]],0xff
-; MIPS32: movn [[T1]],[[T2]],[[T3]]
-; MIPS32: andi [[T1]],[[T1]],0xff
-; MIPS32: srl [[T14]],[[T14]],0x8
-; MIPS32: sll [[T14]],[[T14]],0x8
-; MIPS32: or [[T1]],[[T1]],[[T14]]
-; MIPS32: move [[T14]],a0
-; MIPS32: srl [[T14]],[[T14]],0x8
-; MIPS32: andi [[T14]],[[T14]],0xff
-; MIPS32: andi [[T14]],[[T14]],0x1
-; MIPS32: move [[T3]],[[T6]]
-; MIPS32: srl [[T3]],[[T3]],0x8
-; MIPS32: andi [[T3]],[[T3]],0xff
-; MIPS32: move [[T2]],[[T10]]
-; MIPS32: srl [[T2]],[[T2]],0x8
-; MIPS32: andi [[T2]],[[T2]],0xff
-; MIPS32: movn [[T2]],[[T3]],[[T14]]
-; MIPS32: andi [[T2]],[[T2]],0xff
-; MIPS32: sll [[T2]],[[T2]],0x8
-; MIPS32: lui [[T14]],0xffff
-; MIPS32: ori [[T14]],[[T14]],0xff
-; MIPS32: and [[T1]],[[T1]],[[T14]]
-; MIPS32: or [[T2]],[[T2]],[[T1]]
-; MIPS32: move [[T14]],a0
-; MIPS32: srl [[T14]],[[T14]],0x10
-; MIPS32: andi [[T14]],[[T14]],0xff
-; MIPS32: andi [[T14]],[[T14]],0x1
-; MIPS32: move [[T3]],[[T6]]
-; MIPS32: srl [[T3]],[[T3]],0x10
-; MIPS32: andi [[T3]],[[T3]],0xff
-; MIPS32: move [[T1]],[[T10]]
-; MIPS32: srl [[T1]],[[T1]],0x10
-; MIPS32: andi [[T1]],[[T1]],0xff
-; MIPS32: movn [[T1]],[[T3]],[[T14]]
-; MIPS32: andi [[T1]],[[T1]],0xff
-; MIPS32: sll [[T1]],[[T1]],0x10
-; MIPS32: lui [[T14]],0xff00
-; MIPS32: ori [[T14]],[[T14]],0xffff
-; MIPS32: and [[T2]],[[T2]],[[T14]]
-; MIPS32: or [[T1]],[[T1]],[[T2]]
-; MIPS32: srl [[T16:.*]],a0,0x18
-; MIPS32: andi [[T16]],[[T16]],0x1
-; MIPS32: srl [[T6]],[[T6]],0x18
-; MIPS32: srl [[T10]],[[T10]],0x18
-; MIPS32: movn [[T10]],[[T6]],[[T16]]
-; MIPS32: sll [[T10]],[[T10]],0x18
-; MIPS32: sll [[T1]],[[T1]],0x8
-; MIPS32: srl [[T1]],[[T1]],0x8
-; MIPS32: or [[T10]],[[T10]],[[T1]]
-; MIPS32: move [[T6]],a1
-; MIPS32: andi [[T6]],[[T6]],0xff
-; MIPS32: andi [[T6]],[[T6]],0x1
-; MIPS32: move [[T16]],[[T7]]
-; MIPS32: andi [[T16]],[[T16]],0xff
-; MIPS32: move [[T14]],[[T11]]
-; MIPS32: andi [[T14]],[[T14]],0xff
-; MIPS32: movn [[T14]],[[T16]],[[T6]]
-; MIPS32: andi [[T14]],[[T14]],0xff
-; MIPS32: srl [[T15]],[[T15]],0x8
-; MIPS32: sll [[T15]],[[T15]],0x8
-; MIPS32: or [[T14]],[[T14]],[[T15]]
-; MIPS32: move [[T6]],a1
-; MIPS32: srl [[T6]],[[T6]],0x8
-; MIPS32: andi [[T6]],[[T6]],0xff
-; MIPS32: andi [[T6]],[[T6]],0x1
-; MIPS32: move [[T16]],[[T7]]
-; MIPS32: srl [[T16]],[[T16]],0x8
-; MIPS32: andi [[T16]],[[T16]],0xff
-; MIPS32: move [[T15]],[[T11]]
-; MIPS32: srl [[T15]],[[T15]],0x8
-; MIPS32: andi [[T15]],[[T15]],0xff
-; MIPS32: movn [[T15]],[[T16]],[[T6]]
-; MIPS32: andi [[T15]],[[T15]],0xff
-; MIPS32: sll [[T15]],[[T15]],0x8
-; MIPS32: lui [[T6]],0xffff
-; MIPS32: ori [[T6]],[[T6]],0xff
-; MIPS32: and [[T14]],[[T14]],[[T6]]
-; MIPS32: or [[T15]],[[T15]],[[T14]]
-; MIPS32: move [[T6]],a1
-; MIPS32: srl [[T6]],[[T6]],0x10
-; MIPS32: andi [[T6]],[[T6]],0xff
-; MIPS32: andi [[T6]],[[T6]],0x1
-; MIPS32: move [[T16]],[[T7]]
-; MIPS32: srl [[T16]],[[T16]],0x10
-; MIPS32: andi [[T16]],[[T16]],0xff
-; MIPS32: move [[T14]],[[T11]]
-; MIPS32: srl [[T14]],[[T14]],0x10
-; MIPS32: andi [[T14]],[[T14]],0xff
-; MIPS32: movn [[T14]],[[T16]],[[T6]]
-; MIPS32: andi [[T14]],[[T14]],0xff
-; MIPS32: sll [[T14]],[[T14]],0x10
-; MIPS32: lui [[T6]],0xff00
-; MIPS32: ori [[T6]],[[T6]],0xffff
-; MIPS32: and [[T15]],[[T15]],[[T6]]
-; MIPS32: or [[T14]],[[T14]],[[T15]]
-; MIPS32: srl [[T17:.*]],a1,0x18
-; MIPS32: andi [[T17]],[[T17]],0x1
-; MIPS32: srl [[T7]],[[T7]],0x18
-; MIPS32: srl [[T11]],[[T11]],0x18
-; MIPS32: movn [[T11]],[[T7]],[[T17]]
-; MIPS32: sll [[T11]],[[T11]],0x18
-; MIPS32: sll [[T14]],[[T14]],0x8
-; MIPS32: srl [[T14]],[[T14]],0x8
-; MIPS32: or [[T11]],[[T11]],[[T14]]
-; MIPS32: move [[T6]],a2
-; MIPS32: andi [[T6]],[[T6]],0xff
-; MIPS32: andi [[T6]],[[T6]],0x1
-; MIPS32: move [[T7]],[[T8]]
-; MIPS32: andi [[T7]],[[T7]],0xff
-; MIPS32: move [[T16]],[[T12]]
-; MIPS32: andi [[T16]],[[T16]],0xff
-; MIPS32: movn [[T16]],[[T7]],[[T6]]
-; MIPS32: andi [[T16]],[[T16]],0xff
-; MIPS32: srl [[T5]],[[T5]],0x8
-; MIPS32: sll [[T5]],[[T5]],0x8
-; MIPS32: or [[T16]],[[T16]],[[T5]]
-; MIPS32: move [[T6]],a2
-; MIPS32: srl [[T6]],[[T6]],0x8
-; MIPS32: andi [[T6]],[[T6]],0xff
-; MIPS32: andi [[T6]],[[T6]],0x1
-; MIPS32: move [[T7]],[[T8]]
-; MIPS32: srl [[T7]],[[T7]],0x8
-; MIPS32: andi [[T7]],[[T7]],0xff
-; MIPS32: move [[T17]],[[T12]]
-; MIPS32: srl [[T17]],[[T17]],0x8
-; MIPS32: andi [[T17]],[[T17]],0xff
-; MIPS32: movn [[T17]],[[T7]],[[T6]]
-; MIPS32: andi [[T17]],[[T17]],0xff
-; MIPS32: sll [[T17]],[[T17]],0x8
-; MIPS32: lui [[T6]],0xffff
-; MIPS32: ori [[T6]],[[T6]],0xff
-; MIPS32: and [[T16]],[[T16]],[[T6]]
-; MIPS32: or [[T17]],[[T17]],[[T16]]
-; MIPS32: move [[T6]],a2
-; MIPS32: srl [[T6]],[[T6]],0x10
-; MIPS32: andi [[T6]],[[T6]],0xff
-; MIPS32: andi [[T6]],[[T6]],0x1
-; MIPS32: move [[T7]],[[T8]]
-; MIPS32: srl [[T7]],[[T7]],0x10
-; MIPS32: andi [[T7]],[[T7]],0xff
-; MIPS32: move [[T16]],[[T12]]
-; MIPS32: srl [[T16]],[[T16]],0x10
-; MIPS32: andi [[T16]],[[T16]],0xff
-; MIPS32: movn [[T16]],[[T7]],[[T6]]
-; MIPS32: andi [[T16]],[[T16]],0xff
-; MIPS32: sll [[T16]],[[T16]],0x10
-; MIPS32: lui [[T6]],0xff00
-; MIPS32: ori [[T6]],[[T6]],0xffff
-; MIPS32: and [[T17]],[[T17]],[[T6]]
-; MIPS32: or [[T16]],[[T16]],[[T17]]
-; MIPS32: srl [[T18:.*]],a2,0x18
-; MIPS32: andi [[T18]],[[T18]],0x1
-; MIPS32: srl [[T8]],[[T8]],0x18
-; MIPS32: srl [[T12]],[[T12]],0x18
-; MIPS32: movn [[T12]],[[T8]],[[T18]]
-; MIPS32: sll [[T12]],[[T12]],0x18
-; MIPS32: sll [[T16]],[[T16]],0x8
-; MIPS32: srl [[T16]],[[T16]],0x8
-; MIPS32: or [[T12]],[[T12]],[[T16]]
-; MIPS32: move [[T6]],a3
-; MIPS32: andi [[T6]],[[T6]],0xff
-; MIPS32: andi [[T6]],[[T6]],0x1
-; MIPS32: move [[T7]],[[T9]]
-; MIPS32: andi [[T7]],[[T7]],0xff
-; MIPS32: move [[T16]],[[T13]]
-; MIPS32: andi [[T16]],[[T16]],0xff
-; MIPS32: movn [[T16]],[[T7]],[[T6]]
-; MIPS32: andi [[T16]],[[T16]],0xff
-; MIPS32: srl [[T4]],[[T4]],0x8
-; MIPS32: sll [[T4]],[[T4]],0x8
-; MIPS32: or [[T16]],[[T16]],[[T4]]
-; MIPS32: move [[T6]],a3
-; MIPS32: srl [[T6]],[[T6]],0x8
-; MIPS32: andi [[T6]],[[T6]],0xff
-; MIPS32: andi [[T6]],[[T6]],0x1
-; MIPS32: move [[T7]],[[T9]]
-; MIPS32: srl [[T7]],[[T7]],0x8
-; MIPS32: andi [[T7]],[[T7]],0xff
-; MIPS32: move [[T17]],[[T13]]
-; MIPS32: srl [[T17]],[[T17]],0x8
-; MIPS32: andi [[T17]],[[T17]],0xff
-; MIPS32: movn [[T17]],[[T7]],[[T6]]
-; MIPS32: andi [[T17]],[[T17]],0xff
-; MIPS32: sll [[T17]],[[T17]],0x8
-; MIPS32: lui [[T6]],0xffff
-; MIPS32: ori [[T6]],[[T6]],0xff
-; MIPS32: and [[T16]],[[T16]],[[T6]]
-; MIPS32: or [[T17]],[[T17]],[[T16]]
-; MIPS32: move [[T6]],a3
-; MIPS32: srl [[T6]],[[T6]],0x10
-; MIPS32: andi [[T6]],[[T6]],0xff
-; MIPS32: andi [[T6]],[[T6]],0x1
-; MIPS32: move [[T7]],[[T9]]
-; MIPS32: srl [[T7]],[[T7]],0x10
-; MIPS32: andi [[T7]],[[T7]],0xff
-; MIPS32: move [[T16]],[[T13]]
-; MIPS32: srl [[T16]],[[T16]],0x10
-; MIPS32: andi [[T16]],[[T16]],0xff
-; MIPS32: movn [[T16]],[[T7]],[[T6]]
-; MIPS32: andi [[T16]],[[T16]],0xff
-; MIPS32: sll [[T16]],[[T16]],0x10
-; MIPS32: lui [[T6]],0xff00
-; MIPS32: ori [[T6]],[[T6]],0xffff
-; MIPS32: and [[T17]],[[T17]],[[T6]]
-; MIPS32: or [[T16]],[[T16]],[[T17]]
-; MIPS32: srl [[T19:.*]],a3,0x18
-; MIPS32: andi [[T19]],[[T19]],0x1
-; MIPS32: srl [[T9]],[[T9]],0x18
-; MIPS32: srl [[T13]],[[T13]],0x18
-; MIPS32: movn [[T13]],[[T9]],[[T19]]
-; MIPS32: sll [[T13]],[[T13]],0x18
-; MIPS32: sll [[T16]],[[T16]],0x8
-; MIPS32: srl [[T16]],[[T16]],0x8
-; MIPS32: or [[T13]],[[T13]],[[T16]]
-; MIPS32: move v0,[[T10]]
-; MIPS32: move v1,[[T11]]
-; MIPS32: move a0,[[T12]]
-; MIPS32: move a1,[[T13]]
-; MIPS32: lw [[T5]],
-; MIPS32: lw [[T4]],
-; MIPS32: lw [[T3]],
-; MIPS32: lw [[T2]],
-; MIPS32: lw [[T1]],
-; MIPS32: addiu [[T0]],sp,32
-}
-
-define internal <16 x i1> @test_select_v16i1(<16 x i1> %cond, <16 x i1> %arg1,
- <16 x i1> %arg2) {
-entry:
- %res = select <16 x i1> %cond, <16 x i1> %arg1, <16 x i1> %arg2
- ret <16 x i1> %res
-; CHECK-LABEL: test_select_v16i1
-; CHECK: pand
-; CHECK: pandn
-; CHECK: por
-
-; SSE41-LABEL: test_select_v16i1
-; SSE41: pblendvb xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}}
-
-; MIPS32-LABEL: test_select_v16i1
-; MIPS32: addiu [[T0:.*]],sp,-32
-; MIPS32: sw [[T1:.*]],
-; MIPS32: sw [[T2:.*]],
-; MIPS32: sw [[T3:.*]],
-; MIPS32: sw [[T4:.*]],
-; MIPS32: sw [[T5:.*]],
-; MIPS32: lw [[T6:.*]],
-; MIPS32: lw [[T7:.*]],
-; MIPS32: lw [[T8:.*]],
-; MIPS32: lw [[T9:.*]],
-; MIPS32: lw [[T10:.*]],
-; MIPS32: lw [[T11:.*]],
-; MIPS32: lw [[T12:.*]],
-; MIPS32: lw [[T13:.*]],
-; MIPS32: move [[T14:.*]],zero
-; MIPS32: move [[T15:.*]],zero
-; MIPS32: move [[T5]],zero
-; MIPS32: move [[T4]],zero
-; MIPS32: move [[T3]],a0
-; MIPS32: andi [[T3]],[[T3]],0xff
-; MIPS32: andi [[T3]],[[T3]],0x1
-; MIPS32: move [[T2]],[[T6]]
-; MIPS32: andi [[T2]],[[T2]],0xff
-; MIPS32: andi [[T2]],[[T2]],0x1
-; MIPS32: move [[T1]],[[T10]]
-; MIPS32: andi [[T1]],[[T1]],0xff
-; MIPS32: andi [[T1]],[[T1]],0x1
-; MIPS32: movn [[T1]],[[T2]],[[T3]]
-; MIPS32: andi [[T1]],[[T1]],0xff
-; MIPS32: srl [[T14]],[[T14]],0x8
-; MIPS32: sll [[T14]],[[T14]],0x8
-; MIPS32: or [[T1]],[[T1]],[[T14]]
-; MIPS32: move [[T14]],a0
-; MIPS32: srl [[T14]],[[T14]],0x8
-; MIPS32: andi [[T14]],[[T14]],0xff
-; MIPS32: andi [[T14]],[[T14]],0x1
-; MIPS32: move [[T3]],[[T6]]
-; MIPS32: srl [[T3]],[[T3]],0x8
-; MIPS32: andi [[T3]],[[T3]],0xff
-; MIPS32: andi [[T3]],[[T3]],0x1
-; MIPS32: move [[T2]],[[T10]]
-; MIPS32: srl [[T2]],[[T2]],0x8
-; MIPS32: andi [[T2]],[[T2]],0xff
-; MIPS32: andi [[T2]],[[T2]],0x1
-; MIPS32: movn [[T2]],[[T3]],[[T14]]
-; MIPS32: andi [[T2]],[[T2]],0xff
-; MIPS32: sll [[T2]],[[T2]],0x8
-; MIPS32: lui [[T14]],0xffff
-; MIPS32: ori [[T14]],[[T14]],0xff
-; MIPS32: and [[T1]],[[T1]],[[T14]]
-; MIPS32: or [[T2]],[[T2]],[[T1]]
-; MIPS32: move [[T14]],a0
-; MIPS32: srl [[T14]],[[T14]],0x10
-; MIPS32: andi [[T14]],[[T14]],0xff
-; MIPS32: andi [[T14]],[[T14]],0x1
-; MIPS32: move [[T3]],[[T6]]
-; MIPS32: srl [[T3]],[[T3]],0x10
-; MIPS32: andi [[T3]],[[T3]],0xff
-; MIPS32: andi [[T3]],[[T3]],0x1
-; MIPS32: move [[T1]],[[T10]]
-; MIPS32: srl [[T1]],[[T1]],0x10
-; MIPS32: andi [[T1]],[[T1]],0xff
-; MIPS32: andi [[T1]],[[T1]],0x1
-; MIPS32: movn [[T1]],[[T3]],[[T14]]
-; MIPS32: andi [[T1]],[[T1]],0xff
-; MIPS32: sll [[T1]],[[T1]],0x10
-; MIPS32: lui [[T14]],0xff00
-; MIPS32: ori [[T14]],[[T14]],0xffff
-; MIPS32: and [[T2]],[[T2]],[[T14]]
-; MIPS32: or [[T1]],[[T1]],[[T2]]
-; MIPS32: srl [[T16:.*]],a0,0x18
-; MIPS32: andi [[T16]],[[T16]],0x1
-; MIPS32: srl [[T6]],[[T6]],0x18
-; MIPS32: andi [[T6]],[[T6]],0x1
-; MIPS32: srl [[T10]],[[T10]],0x18
-; MIPS32: andi [[T10]],[[T10]],0x1
-; MIPS32: movn [[T10]],[[T6]],[[T16]]
-; MIPS32: sll [[T10]],[[T10]],0x18
-; MIPS32: sll [[T1]],[[T1]],0x8
-; MIPS32: srl [[T1]],[[T1]],0x8
-; MIPS32: or [[T10]],[[T10]],[[T1]]
-; MIPS32: move [[T6]],a1
-; MIPS32: andi [[T6]],[[T6]],0xff
-; MIPS32: andi [[T6]],[[T6]],0x1
-; MIPS32: move [[T16]],[[T7]]
-; MIPS32: andi [[T16]],[[T16]],0xff
-; MIPS32: andi [[T16]],[[T16]],0x1
-; MIPS32: move [[T14]],[[T11]]
-; MIPS32: andi [[T14]],[[T14]],0xff
-; MIPS32: andi [[T14]],[[T14]],0x1
-; MIPS32: movn [[T14]],[[T16]],[[T6]]
-; MIPS32: andi [[T14]],[[T14]],0xff
-; MIPS32: srl [[T15]],[[T15]],0x8
-; MIPS32: sll [[T15]],[[T15]],0x8
-; MIPS32: or [[T14]],[[T14]],[[T15]]
-; MIPS32: move [[T6]],a1
-; MIPS32: srl [[T6]],[[T6]],0x8
-; MIPS32: andi [[T6]],[[T6]],0xff
-; MIPS32: andi [[T6]],[[T6]],0x1
-; MIPS32: move [[T16]],[[T7]]
-; MIPS32: srl [[T16]],[[T16]],0x8
-; MIPS32: andi [[T16]],[[T16]],0xff
-; MIPS32: andi [[T16]],[[T16]],0x1
-; MIPS32: move [[T15]],[[T11]]
-; MIPS32: srl [[T15]],[[T15]],0x8
-; MIPS32: andi [[T15]],[[T15]],0xff
-; MIPS32: andi [[T15]],[[T15]],0x1
-; MIPS32: movn [[T15]],[[T16]],[[T6]]
-; MIPS32: andi [[T15]],[[T15]],0xff
-; MIPS32: sll [[T15]],[[T15]],0x8
-; MIPS32: lui [[T6]],0xffff
-; MIPS32: ori [[T6]],[[T6]],0xff
-; MIPS32: and [[T14]],[[T14]],[[T6]]
-; MIPS32: or [[T15]],[[T15]],[[T14]]
-; MIPS32: move [[T6]],a1
-; MIPS32: srl [[T6]],[[T6]],0x10
-; MIPS32: andi [[T6]],[[T6]],0xff
-; MIPS32: andi [[T6]],[[T6]],0x1
-; MIPS32: move [[T16]],[[T7]]
-; MIPS32: srl [[T16]],[[T16]],0x10
-; MIPS32: andi [[T16]],[[T16]],0xff
-; MIPS32: andi [[T16]],[[T16]],0x1
-; MIPS32: move [[T14]],[[T11]]
-; MIPS32: srl [[T14]],[[T14]],0x10
-; MIPS32: andi [[T14]],[[T14]],0xff
-; MIPS32: andi [[T14]],[[T14]],0x1
-; MIPS32: movn [[T14]],[[T16]],[[T6]]
-; MIPS32: andi [[T14]],[[T14]],0xff
-; MIPS32: sll [[T14]],[[T14]],0x10
-; MIPS32: lui [[T6]],0xff00
-; MIPS32: ori [[T6]],[[T6]],0xffff
-; MIPS32: and [[T15]],[[T15]],[[T6]]
-; MIPS32: or [[T14]],[[T14]],[[T15]]
-; MIPS32: srl [[T17:.*]],a1,0x18
-; MIPS32: andi [[T17]],[[T17]],0x1
-; MIPS32: srl [[T7]],[[T7]],0x18
-; MIPS32: andi [[T7]],[[T7]],0x1
-; MIPS32: srl [[T11]],[[T11]],0x18
-; MIPS32: andi [[T11]],[[T11]],0x1
-; MIPS32: movn [[T11]],[[T7]],[[T17]]
-; MIPS32: sll [[T11]],[[T11]],0x18
-; MIPS32: sll [[T14]],[[T14]],0x8
-; MIPS32: srl [[T14]],[[T14]],0x8
-; MIPS32: or [[T11]],[[T11]],[[T14]]
-; MIPS32: move [[T6]],a2
-; MIPS32: andi [[T6]],[[T6]],0xff
-; MIPS32: andi [[T6]],[[T6]],0x1
-; MIPS32: move [[T7]],[[T8]]
-; MIPS32: andi [[T7]],[[T7]],0xff
-; MIPS32: andi [[T7]],[[T7]],0x1
-; MIPS32: move [[T16]],[[T12]]
-; MIPS32: andi [[T16]],[[T16]],0xff
-; MIPS32: andi [[T16]],[[T16]],0x1
-; MIPS32: movn [[T16]],[[T7]],[[T6]]
-; MIPS32: andi [[T16]],[[T16]],0xff
-; MIPS32: srl [[T5]],[[T5]],0x8
-; MIPS32: sll [[T5]],[[T5]],0x8
-; MIPS32: or [[T16]],[[T16]],[[T5]]
-; MIPS32: move [[T6]],a2
-; MIPS32: srl [[T6]],[[T6]],0x8
-; MIPS32: andi [[T6]],[[T6]],0xff
-; MIPS32: andi [[T6]],[[T6]],0x1
-; MIPS32: move [[T7]],[[T8]]
-; MIPS32: srl [[T7]],[[T7]],0x8
-; MIPS32: andi [[T7]],[[T7]],0xff
-; MIPS32: andi [[T7]],[[T7]],0x1
-; MIPS32: move [[T17]],[[T12]]
-; MIPS32: srl [[T17]],[[T17]],0x8
-; MIPS32: andi [[T17]],[[T17]],0xff
-; MIPS32: andi [[T17]],[[T17]],0x1
-; MIPS32: movn [[T17]],[[T7]],[[T6]]
-; MIPS32: andi [[T17]],[[T17]],0xff
-; MIPS32: sll [[T17]],[[T17]],0x8
-; MIPS32: lui [[T6]],0xffff
-; MIPS32: ori [[T6]],[[T6]],0xff
-; MIPS32: and [[T16]],[[T16]],[[T6]]
-; MIPS32: or [[T17]],[[T17]],[[T16]]
-; MIPS32: move [[T6]],a2
-; MIPS32: srl [[T6]],[[T6]],0x10
-; MIPS32: andi [[T6]],[[T6]],0xff
-; MIPS32: andi [[T6]],[[T6]],0x1
-; MIPS32: move [[T7]],[[T8]]
-; MIPS32: srl [[T7]],[[T7]],0x10
-; MIPS32: andi [[T7]],[[T7]],0xff
-; MIPS32: andi [[T7]],[[T7]],0x1
-; MIPS32: move [[T16]],[[T12]]
-; MIPS32: srl [[T16]],[[T16]],0x10
-; MIPS32: andi [[T16]],[[T16]],0xff
-; MIPS32: andi [[T16]],[[T16]],0x1
-; MIPS32: movn [[T16]],[[T7]],[[T6]]
-; MIPS32: andi [[T16]],[[T16]],0xff
-; MIPS32: sll [[T16]],[[T16]],0x10
-; MIPS32: lui [[T6]],0xff00
-; MIPS32: ori [[T6]],[[T6]],0xffff
-; MIPS32: and [[T17]],[[T17]],[[T6]]
-; MIPS32: or [[T16]],[[T16]],[[T17]]
-; MIPS32: srl [[T18:.*]],a2,0x18
-; MIPS32: andi [[T18]],[[T18]],0x1
-; MIPS32: srl [[T8]],[[T8]],0x18
-; MIPS32: andi [[T8]],[[T8]],0x1
-; MIPS32: srl [[T12]],[[T12]],0x18
-; MIPS32: andi [[T12]],[[T12]],0x1
-; MIPS32: movn [[T12]],[[T8]],[[T18]]
-; MIPS32: sll [[T12]],[[T12]],0x18
-; MIPS32: sll [[T16]],[[T16]],0x8
-; MIPS32: srl [[T16]],[[T16]],0x8
-; MIPS32: or [[T12]],[[T12]],[[T16]]
-; MIPS32: move [[T6]],a3
-; MIPS32: andi [[T6]],[[T6]],0xff
-; MIPS32: andi [[T6]],[[T6]],0x1
-; MIPS32: move [[T7]],[[T9]]
-; MIPS32: andi [[T7]],[[T7]],0xff
-; MIPS32: andi [[T7]],[[T7]],0x1
-; MIPS32: move [[T16]],[[T13]]
-; MIPS32: andi [[T16]],[[T16]],0xff
-; MIPS32: andi [[T16]],[[T16]],0x1
-; MIPS32: movn [[T16]],[[T7]],[[T6]]
-; MIPS32: andi [[T16]],[[T16]],0xff
-; MIPS32: srl [[T4]],[[T4]],0x8
-; MIPS32: sll [[T4]],[[T4]],0x8
-; MIPS32: or [[T16]],[[T16]],[[T4]]
-; MIPS32: move [[T6]],a3
-; MIPS32: srl [[T6]],[[T6]],0x8
-; MIPS32: andi [[T6]],[[T6]],0xff
-; MIPS32: andi [[T6]],[[T6]],0x1
-; MIPS32: move [[T7]],[[T9]]
-; MIPS32: srl [[T7]],[[T7]],0x8
-; MIPS32: andi [[T7]],[[T7]],0xff
-; MIPS32: andi [[T7]],[[T7]],0x1
-; MIPS32: move [[T17]],[[T13]]
-; MIPS32: srl [[T17]],[[T17]],0x8
-; MIPS32: andi [[T17]],[[T17]],0xff
-; MIPS32: andi [[T17]],[[T17]],0x1
-; MIPS32: movn [[T17]],[[T7]],[[T6]]
-; MIPS32: andi [[T17]],[[T17]],0xff
-; MIPS32: sll [[T17]],[[T17]],0x8
-; MIPS32: lui [[T6]],0xffff
-; MIPS32: ori [[T6]],[[T6]],0xff
-; MIPS32: and [[T16]],[[T16]],[[T6]]
-; MIPS32: or [[T17]],[[T17]],[[T16]]
-; MIPS32: move [[T6]],a3
-; MIPS32: srl [[T6]],[[T6]],0x10
-; MIPS32: andi [[T6]],[[T6]],0xff
-; MIPS32: andi [[T6]],[[T6]],0x1
-; MIPS32: move [[T7]],[[T9]]
-; MIPS32: srl [[T7]],[[T7]],0x10
-; MIPS32: andi [[T7]],[[T7]],0xff
-; MIPS32: andi [[T7]],[[T7]],0x1
-; MIPS32: move [[T16]],[[T13]]
-; MIPS32: srl [[T16]],[[T16]],0x10
-; MIPS32: andi [[T16]],[[T16]],0xff
-; MIPS32: andi [[T16]],[[T16]],0x1
-; MIPS32: movn [[T16]],[[T7]],[[T6]]
-; MIPS32: andi [[T16]],[[T16]],0xff
-; MIPS32: sll [[T16]],[[T16]],0x10
-; MIPS32: lui [[T6]],0xff00
-; MIPS32: ori [[T6]],[[T6]],0xffff
-; MIPS32: and [[T17]],[[T17]],[[T6]]
-; MIPS32: or [[T16]],[[T16]],[[T17]]
-; MIPS32: srl [[T19:.*]],a3,0x18
-; MIPS32: andi [[T19]],[[T19]],0x1
-; MIPS32: srl [[T9]],[[T9]],0x18
-; MIPS32: andi [[T9]],[[T9]],0x1
-; MIPS32: srl [[T13]],[[T13]],0x18
-; MIPS32: andi [[T13]],[[T13]],0x1
-; MIPS32: movn [[T13]],[[T9]],[[T19]]
-; MIPS32: sll [[T13]],[[T13]],0x18
-; MIPS32: sll [[T16]],[[T16]],0x8
-; MIPS32: srl [[T16]],[[T16]],0x8
-; MIPS32: or [[T13]],[[T13]],[[T16]]
-; MIPS32: move v0,[[T10]]
-; MIPS32: move v1,[[T11]]
-; MIPS32: move a0,[[T12]]
-; MIPS32: move a1,[[T13]]
-; MIPS32: lw [[T5]],
-; MIPS32: lw [[T4]],
-; MIPS32: lw [[T3]],
-; MIPS32: lw [[T2]],
-; MIPS32: lw [[T1]],
-; MIPS32: addiu [[T0]],sp,32
-}
-
-define internal <8 x i16> @test_select_v8i16(<8 x i1> %cond, <8 x i16> %arg1,
- <8 x i16> %arg2) {
-entry:
- %res = select <8 x i1> %cond, <8 x i16> %arg1, <8 x i16> %arg2
- ret <8 x i16> %res
-; CHECK-LABEL: test_select_v8i16
-; CHECK: pand
-; CHECK: pandn
-; CHECK: por
-
-; SSE41-LABEL: test_select_v8i16
-; SSE41: pblendvb xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}}
-
-; MIPS32-LABEL: test_select_v8i16
-; MIPS32: addiu [[T0:.*]],sp,-32
-; MIPS32: sw [[T1:.*]],
-; MIPS32: sw [[T2:.*]],
-; MIPS32: sw [[T3:.*]],
-; MIPS32: sw [[T4:.*]],
-; MIPS32: sw [[T5:.*]],
-; MIPS32: lw [[T6:.*]],
-; MIPS32: lw [[T7:.*]],
-; MIPS32: lw [[T8:.*]],
-; MIPS32: lw [[T9:.*]],
-; MIPS32: lw [[T10:.*]],
-; MIPS32: lw [[T11:.*]],
-; MIPS32: lw [[T12:.*]],
-; MIPS32: lw [[T13:.*]],
-; MIPS32: move [[T14:.*]],zero
-; MIPS32: move [[T15:.*]],zero
-; MIPS32: move [[T5]],zero
-; MIPS32: move [[T4]],zero
-; MIPS32: move [[T3]],a0
-; MIPS32: andi [[T3]],[[T3]],0xffff
-; MIPS32: andi [[T3]],[[T3]],0x1
-; MIPS32: move [[T2]],[[T6]]
-; MIPS32: andi [[T2]],[[T2]],0xffff
-; MIPS32: move [[T1]],[[T10]]
-; MIPS32: andi [[T1]],[[T1]],0xffff
-; MIPS32: movn [[T1]],[[T2]],[[T3]]
-; MIPS32: andi [[T1]],[[T1]],0xffff
-; MIPS32: srl [[T14]],[[T14]],0x10
-; MIPS32: sll [[T14]],[[T14]],0x10
-; MIPS32: or [[T1]],[[T1]],[[T14]]
-; MIPS32: srl [[T16:.*]],a0,0x10
-; MIPS32: andi [[T16]],[[T16]],0x1
-; MIPS32: srl [[T6]],[[T6]],0x10
-; MIPS32: srl [[T10]],[[T10]],0x10
-; MIPS32: movn [[T10]],[[T6]],[[T16]]
-; MIPS32: sll [[T10]],[[T10]],0x10
-; MIPS32: sll [[T1]],[[T1]],0x10
-; MIPS32: srl [[T1]],[[T1]],0x10
-; MIPS32: or [[T10]],[[T10]],[[T1]]
-; MIPS32: move [[T6]],a1
-; MIPS32: andi [[T6]],[[T6]],0xffff
-; MIPS32: andi [[T6]],[[T6]],0x1
-; MIPS32: move [[T16]],[[T7]]
-; MIPS32: andi [[T16]],[[T16]],0xffff
-; MIPS32: move [[T14]],[[T11]]
-; MIPS32: andi [[T14]],[[T14]],0xffff
-; MIPS32: movn [[T14]],[[T16]],[[T6]]
-; MIPS32: andi [[T14]],[[T14]],0xffff
-; MIPS32: srl [[T15]],[[T15]],0x10
-; MIPS32: sll [[T15]],[[T15]],0x10
-; MIPS32: or [[T14]],[[T14]],[[T15]]
-; MIPS32: srl [[T17:.*]],a1,0x10
-; MIPS32: andi [[T17]],[[T17]],0x1
-; MIPS32: srl [[T7]],[[T7]],0x10
-; MIPS32: srl [[T11]],[[T11]],0x10
-; MIPS32: movn [[T11]],[[T7]],[[T17]]
-; MIPS32: sll [[T11]],[[T11]],0x10
-; MIPS32: sll [[T14]],[[T14]],0x10
-; MIPS32: srl [[T14]],[[T14]],0x10
-; MIPS32: or [[T11]],[[T11]],[[T14]]
-; MIPS32: move [[T6]],a2
-; MIPS32: andi [[T6]],[[T6]],0xffff
-; MIPS32: andi [[T6]],[[T6]],0x1
-; MIPS32: move [[T7]],[[T8]]
-; MIPS32: andi [[T7]],[[T7]],0xffff
-; MIPS32: move [[T16]],[[T12]]
-; MIPS32: andi [[T16]],[[T16]],0xffff
-; MIPS32: movn [[T16]],[[T7]],[[T6]]
-; MIPS32: andi [[T16]],[[T16]],0xffff
-; MIPS32: srl [[T5]],[[T5]],0x10
-; MIPS32: sll [[T5]],[[T5]],0x10
-; MIPS32: or [[T16]],[[T16]],[[T5]]
-; MIPS32: srl [[T18:.*]],a2,0x10
-; MIPS32: andi [[T18]],[[T18]],0x1
-; MIPS32: srl [[T8]],[[T8]],0x10
-; MIPS32: srl [[T12]],[[T12]],0x10
-; MIPS32: movn [[T12]],[[T8]],[[T18]]
-; MIPS32: sll [[T12]],[[T12]],0x10
-; MIPS32: sll [[T16]],[[T16]],0x10
-; MIPS32: srl [[T16]],[[T16]],0x10
-; MIPS32: or [[T12]],[[T12]],[[T16]]
-; MIPS32: move [[T6]],a3
-; MIPS32: andi [[T6]],[[T6]],0xffff
-; MIPS32: andi [[T6]],[[T6]],0x1
-; MIPS32: move [[T7]],[[T9]]
-; MIPS32: andi [[T7]],[[T7]],0xffff
-; MIPS32: move [[T16]],[[T13]]
-; MIPS32: andi [[T16]],[[T16]],0xffff
-; MIPS32: movn [[T16]],[[T7]],[[T6]]
-; MIPS32: andi [[T16]],[[T16]],0xffff
-; MIPS32: srl [[T4]],[[T4]],0x10
-; MIPS32: sll [[T4]],[[T4]],0x10
-; MIPS32: or [[T16]],[[T16]],[[T4]]
-; MIPS32: srl [[T19:.*]],a3,0x10
-; MIPS32: andi [[T19]],[[T19]],0x1
-; MIPS32: srl [[T9]],[[T9]],0x10
-; MIPS32: srl [[T13]],[[T13]],0x10
-; MIPS32: movn [[T13]],[[T9]],[[T19]]
-; MIPS32: sll [[T13]],[[T13]],0x10
-; MIPS32: sll [[T16]],[[T16]],0x10
-; MIPS32: srl [[T16]],[[T16]],0x10
-; MIPS32: or [[T13]],[[T13]],[[T16]]
-; MIPS32: move v0,[[T10]]
-; MIPS32: move v1,[[T11]]
-; MIPS32: move a0,[[T12]]
-; MIPS32: move a1,[[T13]]
-; MIPS32: lw [[T5]],
-; MIPS32: lw [[T4]],
-; MIPS32: lw [[T3]],
-; MIPS32: lw [[T2]],
-; MIPS32: lw [[T1]],
-; MIPS32: addiu [[T0]],sp,32
-}
-
-define internal <8 x i1> @test_select_v8i1(<8 x i1> %cond, <8 x i1> %arg1,
- <8 x i1> %arg2) {
-entry:
- %res = select <8 x i1> %cond, <8 x i1> %arg1, <8 x i1> %arg2
- ret <8 x i1> %res
-; CHECK-LABEL: test_select_v8i1
-; CHECK: pand
-; CHECK: pandn
-; CHECK: por
-
-; SSE41-LABEL: test_select_v8i1
-; SSE41: pblendvb xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}}
-
-; MIPS32-LABEL: test_select_v8i1
-; MIPS32: addiu [[T0:.*]],sp,-32
-; MIPS32: sw [[T1:.*]],
-; MIPS32: sw [[T2:.*]],
-; MIPS32: sw [[T3:.*]],
-; MIPS32: sw [[T4:.*]],
-; MIPS32: sw [[T5:.*]],
-; MIPS32: lw [[T6:.*]],
-; MIPS32: lw [[T7:.*]],
-; MIPS32: lw [[T8:.*]],
-; MIPS32: lw [[T9:.*]],
-; MIPS32: lw [[T10:.*]],
-; MIPS32: lw [[T11:.*]],
-; MIPS32: lw [[T12:.*]],
-; MIPS32: lw [[T13:.*]],
-; MIPS32: move [[T14:.*]],zero
-; MIPS32: move [[T15:.*]],zero
-; MIPS32: move [[T5]],zero
-; MIPS32: move [[T4]],zero
-; MIPS32: move [[T3]],a0
-; MIPS32: andi [[T3]],[[T3]],0xffff
-; MIPS32: andi [[T3]],[[T3]],0x1
-; MIPS32: move [[T2]],[[T6]]
-; MIPS32: andi [[T2]],[[T2]],0xffff
-; MIPS32: andi [[T2]],[[T2]],0x1
-; MIPS32: move [[T1]],[[T10]]
-; MIPS32: andi [[T1]],[[T1]],0xffff
-; MIPS32: andi [[T1]],[[T1]],0x1
-; MIPS32: movn [[T1]],[[T2]],[[T3]]
-; MIPS32: andi [[T1]],[[T1]],0xffff
-; MIPS32: srl [[T14]],[[T14]],0x10
-; MIPS32: sll [[T14]],[[T14]],0x10
-; MIPS32: or [[T1]],[[T1]],[[T14]]
-; MIPS32: srl [[T16:.*]],a0,0x10
-; MIPS32: andi [[T16]],[[T16]],0x1
-; MIPS32: srl [[T6]],[[T6]],0x10
-; MIPS32: andi [[T6]],[[T6]],0x1
-; MIPS32: srl [[T10]],[[T10]],0x10
-; MIPS32: andi [[T10]],[[T10]],0x1
-; MIPS32: movn [[T10]],[[T6]],[[T16]]
-; MIPS32: sll [[T10]],[[T10]],0x10
-; MIPS32: sll [[T1]],[[T1]],0x10
-; MIPS32: srl [[T1]],[[T1]],0x10
-; MIPS32: or [[T10]],[[T10]],[[T1]]
-; MIPS32: move [[T6]],a1
-; MIPS32: andi [[T6]],[[T6]],0xffff
-; MIPS32: andi [[T6]],[[T6]],0x1
-; MIPS32: move [[T16]],[[T7]]
-; MIPS32: andi [[T16]],[[T16]],0xffff
-; MIPS32: andi [[T16]],[[T16]],0x1
-; MIPS32: move [[T14]],[[T11]]
-; MIPS32: andi [[T14]],[[T14]],0xffff
-; MIPS32: andi [[T14]],[[T14]],0x1
-; MIPS32: movn [[T14]],[[T16]],[[T6]]
-; MIPS32: andi [[T14]],[[T14]],0xffff
-; MIPS32: srl [[T15]],[[T15]],0x10
-; MIPS32: sll [[T15]],[[T15]],0x10
-; MIPS32: or [[T14]],[[T14]],[[T15]]
-; MIPS32: srl [[T17:.*]],a1,0x10
-; MIPS32: andi [[T17]],[[T17]],0x1
-; MIPS32: srl [[T7]],[[T7]],0x10
-; MIPS32: andi [[T7]],[[T7]],0x1
-; MIPS32: srl [[T11]],[[T11]],0x10
-; MIPS32: andi [[T11]],[[T11]],0x1
-; MIPS32: movn [[T11]],[[T7]],[[T17]]
-; MIPS32: sll [[T11]],[[T11]],0x10
-; MIPS32: sll [[T14]],[[T14]],0x10
-; MIPS32: srl [[T14]],[[T14]],0x10
-; MIPS32: or [[T11]],[[T11]],[[T14]]
-; MIPS32: move [[T6]],a2
-; MIPS32: andi [[T6]],[[T6]],0xffff
-; MIPS32: andi [[T6]],[[T6]],0x1
-; MIPS32: move [[T7]],[[T8]]
-; MIPS32: andi [[T7]],[[T7]],0xffff
-; MIPS32: andi [[T7]],[[T7]],0x1
-; MIPS32: move [[T16]],[[T12]]
-; MIPS32: andi [[T16]],[[T16]],0xffff
-; MIPS32: andi [[T16]],[[T16]],0x1
-; MIPS32: movn [[T16]],[[T7]],[[T6]]
-; MIPS32: andi [[T16]],[[T16]],0xffff
-; MIPS32: srl [[T5]],[[T5]],0x10
-; MIPS32: sll [[T5]],[[T5]],0x10
-; MIPS32: or [[T16]],[[T16]],[[T5]]
-; MIPS32: srl [[T18:.*]],a2,0x10
-; MIPS32: andi [[T18]],[[T18]],0x1
-; MIPS32: srl [[T8]],[[T8]],0x10
-; MIPS32: andi [[T8]],[[T8]],0x1
-; MIPS32: srl [[T12]],[[T12]],0x10
-; MIPS32: andi [[T12]],[[T12]],0x1
-; MIPS32: movn [[T12]],[[T8]],[[T18]]
-; MIPS32: sll [[T12]],[[T12]],0x10
-; MIPS32: sll [[T16]],[[T16]],0x10
-; MIPS32: srl [[T16]],[[T16]],0x10
-; MIPS32: or [[T12]],[[T12]],[[T16]]
-; MIPS32: move [[T6]],a3
-; MIPS32: andi [[T6]],[[T6]],0xffff
-; MIPS32: andi [[T6]],[[T6]],0x1
-; MIPS32: move [[T7]],[[T9]]
-; MIPS32: andi [[T7]],[[T7]],0xffff
-; MIPS32: andi [[T7]],[[T7]],0x1
-; MIPS32: move [[T16]],[[T13]]
-; MIPS32: andi [[T16]],[[T16]],0xffff
-; MIPS32: andi [[T16]],[[T16]],0x1
-; MIPS32: movn [[T16]],[[T7]],[[T6]]
-; MIPS32: andi [[T16]],[[T16]],0xffff
-; MIPS32: srl [[T4]],[[T4]],0x10
-; MIPS32: sll [[T4]],[[T4]],0x10
-; MIPS32: or [[T16]],[[T16]],[[T4]]
-; MIPS32: srl [[T19:.*]],a3,0x10
-; MIPS32: andi [[T19]],[[T19]],0x1
-; MIPS32: srl [[T9]],[[T9]],0x10
-; MIPS32: andi [[T9]],[[T9]],0x1
-; MIPS32: srl [[T13]],[[T13]],0x10
-; MIPS32: andi [[T13]],[[T13]],0x1
-; MIPS32: movn [[T13]],[[T9]],[[T19]]
-; MIPS32: sll [[T13]],[[T13]],0x10
-; MIPS32: sll [[T16]],[[T16]],0x10
-; MIPS32: srl [[T16]],[[T16]],0x10
-; MIPS32: or [[T13]],[[T13]],[[T16]]
-; MIPS32: move v0,[[T10]]
-; MIPS32: move v1,[[T11]]
-; MIPS32: move a0,[[T12]]
-; MIPS32: move a1,[[T13]]
-; MIPS32: lw [[T5]],
-; MIPS32: lw [[T4]],
-; MIPS32: lw [[T3]],
-; MIPS32: lw [[T2]],
-; MIPS32: lw [[T1]],
-; MIPS32: addiu [[T0]],sp,32
-}
-
-define internal <4 x i32> @test_select_v4i32(<4 x i1> %cond, <4 x i32> %arg1,
- <4 x i32> %arg2) {
-entry:
- %res = select <4 x i1> %cond, <4 x i32> %arg1, <4 x i32> %arg2
- ret <4 x i32> %res
-; CHECK-LABEL: test_select_v4i32
-; CHECK: pand
-; CHECK: pandn
-; CHECK: por
-
-; SSE41-LABEL: test_select_v4i32
-; SSE41: pslld xmm0,0x1f
-; SSE41: blendvps xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}}
-
-; MIPS32-LABEL: test_select_v4i32
-; MIPS32: lw [[T0:.*]],
-; MIPS32: lw [[T1:.*]],
-; MIPS32: lw [[T2:.*]],
-; MIPS32: lw [[T3:.*]],
-; MIPS32: lw [[T4:.*]],
-; MIPS32: lw [[T5:.*]],
-; MIPS32: lw [[T6:.*]],
-; MIPS32: lw [[T7:.*]],
-; MIPS32: andi [[T8:.*]],a0,0x1
-; MIPS32: movn [[T4]],[[T0]],[[T8]]
-; MIPS32: andi [[T9:.*]],a1,0x1
-; MIPS32: movn [[T5]],[[T1]],[[T9]]
-; MIPS32: andi [[T10:.*]],a2,0x1
-; MIPS32: movn [[T6]],[[T2]],[[T10]]
-; MIPS32: andi [[T11:.*]],a3,0x1
-; MIPS32: movn [[T7]],[[T3]],[[T11]]
-; MIPS32: move v0,[[T4]]
-; MIPS32: move v1,[[T5]]
-; MIPS32: move a0,[[T6]]
-; MIPS32: move a1,[[T7]]
-}
-
-define internal <4 x float> @test_select_v4f32(
- <4 x i1> %cond, <4 x float> %arg1, <4 x float> %arg2) {
-entry:
- %res = select <4 x i1> %cond, <4 x float> %arg1, <4 x float> %arg2
- ret <4 x float> %res
-; CHECK-LABEL: test_select_v4f32
-; CHECK: pand
-; CHECK: pandn
-; CHECK: por
-
-; SSE41-LABEL: test_select_v4f32
-; SSE41: pslld xmm0,0x1f
-; SSE41: blendvps xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}}
-
-; MIPS32-LABEL: test_select_v4f32
-; MIPS32: lw [[T0:.*]],
-; MIPS32: lw [[T1:.*]],
-; MIPS32: lw [[T2:.*]],
-; MIPS32: lw [[T3:.*]],
-; MIPS32: lw [[T4:.*]],
-; MIPS32: lw [[T5:.*]],
-; MIPS32: lw [[T6:.*]],
-; MIPS32: lw [[T7:.*]],
-; MIPS32: lw [[T8:.*]],
-; MIPS32: lw [[T9:.*]],
-; MIPS32: andi [[T10:.*]],a2,0x1
-; MIPS32: mtc1 [[T2]],$f0
-; MIPS32: mtc1 [[T6]],$f1
-; MIPS32: movn.s [[T11:.*]],$f0,[[T10]]
-; MIPS32: mfc1 [[T2]],[[T11]]
-; MIPS32: andi [[T12:.*]],a3,0x1
-; MIPS32: mtc1 [[T3]],$f0
-; MIPS32: mtc1 [[T7]],[[T11]]
-; MIPS32: movn.s [[T11]],$f0,[[T12]]
-; MIPS32: mfc1 [[T3]],[[T11]]
-; MIPS32: andi [[T0]],[[T0]],0x1
-; MIPS32: mtc1 [[T4]],$f0
-; MIPS32: mtc1 [[T8]],[[T11]]
-; MIPS32: movn.s [[T11]],$f0,[[T0]]
-; MIPS32: mfc1 [[T4]],[[T11]]
-; MIPS32: andi [[T1]],[[T1]],0x1
-; MIPS32: mtc1 [[T5]],$f0
-; MIPS32: mtc1 [[T9]],[[T11]]
-; MIPS32: movn.s [[T11]],$f0,[[T1]]
-; MIPS32: mfc1 [[T10]],[[T11]]
-; MIPS32: move [[T12]],a0
-; MIPS32: sw [[T2]],0(a3)
-; MIPS32: sw v1,4(a3)
-; MIPS32: sw a1,8(a3)
-; MIPS32: sw [[T10]],12(a3)
-; MIPS32: move v0,a0
-}
-
-define internal <4 x i1> @test_select_v4i1(<4 x i1> %cond, <4 x i1> %arg1,
- <4 x i1> %arg2) {
-entry:
- %res = select <4 x i1> %cond, <4 x i1> %arg1, <4 x i1> %arg2
- ret <4 x i1> %res
-; CHECK-LABEL: test_select_v4i1
-; CHECK: pand
-; CHECK: pandn
-; CHECK: por
-
-; SSE41-LABEL: test_select_v4i1
-; SSE41: pslld xmm0,0x1f
-; SSE41: blendvps xmm{{[0-7]}},{{xmm[0-7]|XMMWORD}}
-
-; MIPS32-LABEL: test_select_v4i1
-; MIPS32: lw [[T0:.*]],
-; MIPS32: lw [[T1:.*]],
-; MIPS32: lw [[T2:.*]],
-; MIPS32: lw [[T3:.*]],
-; MIPS32: lw [[T4:.*]],
-; MIPS32: lw [[T5:.*]],
-; MIPS32: lw [[T6:.*]],
-; MIPS32: lw [[T7:.*]],
-; MIPS32: andi [[T8:.*]],a0,0x1
-; MIPS32: andi [[T0]],[[T0]],0x1
-; MIPS32: andi [[T4]],[[T4]],0x1
-; MIPS32: movn [[T4]],[[T0]],[[T8]]
-; MIPS32: andi [[T9:.*]],a1,0x1
-; MIPS32: andi [[T1]],[[T1]],0x1
-; MIPS32: andi [[T5]],[[T5]],0x1
-; MIPS32: movn [[T5]],[[T1]],[[T9]]
-; MIPS32: andi [[T10:.*]],a2,0x1
-; MIPS32: andi [[T2]],[[T2]],0x1
-; MIPS32: andi [[T6]],[[T6]],0x1
-; MIPS32: movn [[T6]],[[T2]],[[T10]]
-; MIPS32: andi [[T11:.*]],a3,0x1
-; MIPS32: andi [[T3]],[[T3]],0x1
-; MIPS32: andi [[T7]],[[T7]],0x1
-; MIPS32: movn [[T7]],[[T3]],[[T11]]
-; MIPS32: move v0,[[T4]]
-; MIPS32: move v1,[[T5]]
-; MIPS32: move a0,[[T6]]
-; MIPS32: move a1,[[T7]]
-}
diff --git a/third_party/subzero/tests_lit/llvm2ice_tests/vector-shuffle.ll b/third_party/subzero/tests_lit/llvm2ice_tests/vector-shuffle.ll
deleted file mode 100644
index e0fa157..0000000
--- a/third_party/subzero/tests_lit/llvm2ice_tests/vector-shuffle.ll
+++ /dev/null
@@ -1,75 +0,0 @@
-; Some shufflevector optimized lowering. This list is by no means exhaustive. It
-; is only a **basic** smoke test. the vector_ops crosstest has a broader range
-; of test cases.
-
-; RUN: %p2i -i %s --target=x8632 --filetype=obj --disassemble -a -O2 \
-; RUN: --allow-externally-defined-symbols | FileCheck %s --check-prefix=X86
-
-; RUN: %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command %p2i --filetype=asm --assemble --disassemble --target \
-; RUN: mips32 -i %s --args -O2 -allow-externally-defined-symbols \
-; RUN: | %if --need=target_MIPS32 --need=allow_dump \
-; RUN: --command FileCheck --check-prefix MIPS32 %s
-
-declare void @useV4I32(<4 x i32> %t);
-
-define internal void @shuffleV4I32(<4 x i32> %a, <4 x i32> %b) {
-; X86-LABEL: shuffleV4I32
- %a_0 = extractelement <4 x i32> %a, i32 0
- %a_1 = extractelement <4 x i32> %a, i32 1
- %a_2 = extractelement <4 x i32> %a, i32 2
- %a_3 = extractelement <4 x i32> %a, i32 3
-
- %b_0 = extractelement <4 x i32> %b, i32 0
- %b_1 = extractelement <4 x i32> %b, i32 1
- %b_2 = extractelement <4 x i32> %b, i32 2
- %b_3 = extractelement <4 x i32> %b, i32 3
-
- %t0_0 = insertelement <4 x i32> undef, i32 %a_0, i32 0
- %t0_1 = insertelement <4 x i32> %t0_0, i32 %b_0, i32 1
- %t0_2 = insertelement <4 x i32> %t0_1, i32 %a_1, i32 2
- %t0 = insertelement <4 x i32> %t0_2, i32 %b_1, i32 3
-; X86: punpckldq {{.*}}
-
- call void @useV4I32(<4 x i32> %t0)
-; X86: call
-
- %t1_0 = insertelement <4 x i32> undef, i32 %a_0, i32 0
- %t1_1 = insertelement <4 x i32> %t1_0, i32 %b_1, i32 1
- %t1_2 = insertelement <4 x i32> %t1_1, i32 %b_1, i32 2
- %t1 = insertelement <4 x i32> %t1_2, i32 %a_0, i32 3
-; X86: shufps [[T:xmm[0-9]+]],{{.*}},0x10
-; X86: pshufd {{.*}},[[T]],0x28
-
- call void @useV4I32(<4 x i32> %t1)
-; X86: call
-
- %t2_0 = insertelement <4 x i32> undef, i32 %a_0, i32 0
- %t2_1 = insertelement <4 x i32> %t2_0, i32 %b_3, i32 1
- %t2_2 = insertelement <4 x i32> %t2_1, i32 %a_2, i32 2
- %t2 = insertelement <4 x i32> %t2_2, i32 %b_2, i32 3
-; X86: shufps {{.*}},0x30
-; X86: shufps {{.*}},0x22
-; X86: shufps {{.*}},0x88
-
- call void @useV4I32(<4 x i32> %t2)
-; X86: call
-
- ret void
-}
-; MIPS32-LABEL: shuffleV4I32
-; MIPS32: move
-; MIPS32: move
-; MIPS32: move
-; MIPS32: move
-; MIPS32: jal
-; MIPS32: move
-; MIPS32: move
-; MIPS32: move
-; MIPS32: move
-; MIPS32: jal
-; MIPS32: move
-; MIPS32: move
-; MIPS32: move
-; MIPS32: move
-; MIPS32: jal
diff --git a/third_party/subzero/tests_lit/parse_errs/Inputs/bad-bb-size.tbc b/third_party/subzero/tests_lit/parse_errs/Inputs/bad-bb-size.tbc
deleted file mode 100644
index fcdd1a3..0000000
--- a/third_party/subzero/tests_lit/parse_errs/Inputs/bad-bb-size.tbc
+++ /dev/null
@@ -1,27 +0,0 @@
-65535,8,2;
-1,1;
-65535,17,2;
-1,4;
-7,32;
-2;
-21,0,0,0;
-7,1;
-65534;
-8,2,0,0,0;
-65535,19,2;
-5,0;
-65534;
-65535,14,2;
-1,0,102,105,98;
-65534;
-65535,12,2;
-1,3105555534;
-28,2,1,36;
-11,1,2,1;
-11,2;
-2,3,2,1;
-43,0,5,1;
-2,1,5,0;
-10,1;
-65534;
-65534;
diff --git a/third_party/subzero/tests_lit/parse_errs/Inputs/bad-global-alignment.tbc b/third_party/subzero/tests_lit/parse_errs/Inputs/bad-global-alignment.tbc
deleted file mode 100644
index aa4bfe6..0000000
--- a/third_party/subzero/tests_lit/parse_errs/Inputs/bad-global-alignment.tbc
+++ /dev/null
@@ -1,8 +0,0 @@
-65535,8,2;
-1,1;
-65535,19,2;
-5,1;
-0,31,0;
-2,4;
-65534;
-65534;
diff --git a/third_party/subzero/tests_lit/parse_errs/Inputs/bad-intrinsic-arg.tbc b/third_party/subzero/tests_lit/parse_errs/Inputs/bad-intrinsic-arg.tbc
deleted file mode 100644
index b99309d..0000000
--- a/third_party/subzero/tests_lit/parse_errs/Inputs/bad-intrinsic-arg.tbc
+++ /dev/null
@@ -1,30 +0,0 @@
-65535,8,2;
-1,1;
-65535,17,2;
-1,6;
-7,32;
-4;
-21,0,0,0;
-2;
-21,0,0,1;
-21,0,3,0,1;
-65534;
-8,4,0,1,0;
-8,2,0,1,0;
-8,4,0,1,0;
-8,5,0,0,0;
-65535,19,2;
-5,0;
-65534;
-65535,14,2;
-1,1,102,111,111;
-1,2,98,97,114;
-1,3,102;
-1,0,108,108,118,109,46,110,97,99,108,46,115,101,116,106,109,112;
-65534;
-65535,12,2;
-1,1;
-34,0,6,1;
-10;
-65534;
-65534;
diff --git a/third_party/subzero/tests_lit/parse_errs/Inputs/bad-switch-case.tbc b/third_party/subzero/tests_lit/parse_errs/Inputs/bad-switch-case.tbc
deleted file mode 100644
index 27b9dd5..0000000
--- a/third_party/subzero/tests_lit/parse_errs/Inputs/bad-switch-case.tbc
+++ /dev/null
@@ -1,25 +0,0 @@
-65535,8,2;
-1,1;
-65535,17,2;
-1,3;
-2;
-7,32;
-21,0,0,1;
-65534;
-8,2,0,0,0;
-65535,19,2;
-5,0;
-65534;
-65535,14,2;
-1,0,83,119,105,116,99,104,86,97,114,105,97,98,108,101;
-65534;
-65535,12,2;
-1,6;
-12,1,1,2,2,1,1,2,3105555534,1,1,8,4;
-11,5;
-11,5;
-11,5;
-11,5;
-10;
-65534;
-65534;
diff --git a/third_party/subzero/tests_lit/parse_errs/Inputs/bad-var-fwdref.tbc b/third_party/subzero/tests_lit/parse_errs/Inputs/bad-var-fwdref.tbc
deleted file mode 100644
index 690a5a9..0000000
--- a/third_party/subzero/tests_lit/parse_errs/Inputs/bad-var-fwdref.tbc
+++ /dev/null
@@ -1,21 +0,0 @@
-65535,8,2;
-1,1;
-65535,17,2;
-1,3;
-2;
-7,32;
-21,0,0,1;
-65534;
-8,2,0,0,0;
-65535,19,2;
-5,0;
-65534;
-65535,14,2;
-1,0,102;
-65534;
-65535,12,2;
-1,1;
-43,3105555534,1;
-10;
-65534;
-65534;
diff --git a/third_party/subzero/tests_lit/parse_errs/Inputs/call-fcn-bad-param-type.tbc b/third_party/subzero/tests_lit/parse_errs/Inputs/call-fcn-bad-param-type.tbc
deleted file mode 100644
index 92b647f..0000000
--- a/third_party/subzero/tests_lit/parse_errs/Inputs/call-fcn-bad-param-type.tbc
+++ /dev/null
@@ -1,32 +0,0 @@
-65535,8,2;
-1,1;
-65535,17,2;
-1,5;
-2;
-7,32;
-7,8;
-21,0,0,1;
-21,0,0;
-65534;
-8,3,0,1,0;
-8,4,0,0,0;
-65535,19,2;
-5,0;
-65534;
-65535,14,2;
-1,1,84,101,115,116;
-1,0,102;
-65534;
-65535,12,2;
-1,1;
-65535,11,2;
-1,1;
-4,2;
-1,2;
-4,2;
-65534;
-2,1,1,0;
-34,0,5,2;
-10;
-65534;
-65534;
diff --git a/third_party/subzero/tests_lit/parse_errs/Inputs/dup-module-vst.tbc b/third_party/subzero/tests_lit/parse_errs/Inputs/dup-module-vst.tbc
deleted file mode 100644
index 50edd56..0000000
--- a/third_party/subzero/tests_lit/parse_errs/Inputs/dup-module-vst.tbc
+++ /dev/null
@@ -1,22 +0,0 @@
-65535,8,2;
-1,1;
-65535,17,2;
-1,2;
-2;
-21,0,0;
-65534;
-8,1,0,0,0;
-65535,19,2;
-5,0;
-65534;
-65535,14,2;
-1,0,102;
-65534;
-65535,14,2;
-1,0,102;
-65534;
-65535,12,2;
-1,1;
-10;
-65534;
-65534;
diff --git a/third_party/subzero/tests_lit/parse_errs/Inputs/duplicate-fcn-name.tbc b/third_party/subzero/tests_lit/parse_errs/Inputs/duplicate-fcn-name.tbc
deleted file mode 100644
index 1e363ea..0000000
--- a/third_party/subzero/tests_lit/parse_errs/Inputs/duplicate-fcn-name.tbc
+++ /dev/null
@@ -1,25 +0,0 @@
-65535,8,2;
-1,1;
-65535,17,2;
-1,2;
-2;
-21,0,0;
-65534;
-8,1,0,0,0;
-8,1,0,0,0;
-65535,19,2;
-5,0;
-65534;
-65535,14,2;
-1,0,102;
-1,1,102;
-65534;
-65535,12,2;
-1,1;
-10;
-65534;
-65535,12,2;
-1,1;
-10;
-65534;
-65534;
diff --git a/third_party/subzero/tests_lit/parse_errs/Inputs/fcn-value-index-isnt-defined.tbc b/third_party/subzero/tests_lit/parse_errs/Inputs/fcn-value-index-isnt-defined.tbc
deleted file mode 100644
index 887341f..0000000
--- a/third_party/subzero/tests_lit/parse_errs/Inputs/fcn-value-index-isnt-defined.tbc
+++ /dev/null
@@ -1,26 +0,0 @@
-65535,8,2;
-1,1;
-65535,17,2;
-1,4;
-7,32;
-21,0,0;
-7,8;
-2;
-65534;
-8,1,0,0,0;
-65535,19,2;
-5,0;
-65534;
-65535,14,2;
-1,0,102;
-65534;
-65535,12,2;
-1,1;
-65535,11,2;
-1,0;
-4,2;
-65534;
-19,1,3;
-10,0;
-65534;
-65534;
diff --git a/third_party/subzero/tests_lit/parse_errs/Inputs/indirect-call-on-float.tbc b/third_party/subzero/tests_lit/parse_errs/Inputs/indirect-call-on-float.tbc
deleted file mode 100644
index 2dac5d4..0000000
--- a/third_party/subzero/tests_lit/parse_errs/Inputs/indirect-call-on-float.tbc
+++ /dev/null
@@ -1,25 +0,0 @@
-65535,8,2;
-1,1;
-65535,17,2;
-1,5;
-2;
-21,0,0;
-7,32;
-3;
-21,0,0,2,3;
-65534;
-8,1,0,1,0;
-8,4,0,0,0;
-65535,19,2;
-5,0;
-65534;
-65535,14,2;
-1,1,102;
-1,0,103;
-65534;
-65535,12,2;
-1,1;
-44,0,1,0;
-10;
-65534;
-65534;
diff --git a/third_party/subzero/tests_lit/parse_errs/Inputs/insertelt-wrong-type.tbc b/third_party/subzero/tests_lit/parse_errs/Inputs/insertelt-wrong-type.tbc
deleted file mode 100644
index 8eb6f65..0000000
--- a/third_party/subzero/tests_lit/parse_errs/Inputs/insertelt-wrong-type.tbc
+++ /dev/null
@@ -1,33 +0,0 @@
-65535,8,2;
-1,1;
-65535,17,2;
-1,6;
-7,1;
-12,16,0;
-7,8;
-2;
-21,0,3,1;
-7,32;
-65534;
-8,4,0,0,0;
-65535,19,2;
-5,0;
-65534;
-65535,14,2;
-1,0,102;
-65534;
-65535,12,2;
-1,1;
-65535,11,2;
-1,0;
-4,3;
-1,2;
-4,2;
-1,5;
-4,0;
-65534;
-2,2,2,0;
-7,5,3,2;
-10;
-65534;
-65534;
diff --git a/third_party/subzero/tests_lit/parse_errs/Inputs/multiple-modules.tbc b/third_party/subzero/tests_lit/parse_errs/Inputs/multiple-modules.tbc
deleted file mode 100644
index 4f6ae2e..0000000
--- a/third_party/subzero/tests_lit/parse_errs/Inputs/multiple-modules.tbc
+++ /dev/null
@@ -1,6 +0,0 @@
-65535,8,2;
-1,1;
-65534;
-65535,8,2;
-1,1;
-65534;
diff --git a/third_party/subzero/tests_lit/parse_errs/Inputs/symtab-after-fcn.tbc b/third_party/subzero/tests_lit/parse_errs/Inputs/symtab-after-fcn.tbc
deleted file mode 100644
index 4132a5c..0000000
--- a/third_party/subzero/tests_lit/parse_errs/Inputs/symtab-after-fcn.tbc
+++ /dev/null
@@ -1,19 +0,0 @@
-65535,8,2;
-1,1;
-65535,17,2;
-1,2;
-2;
-21,0,0;
-65534;
-8,1,0,0,0;
-65535,19,2;
-5,0;
-65534;
-65535,12,2;
-1,1;
-10;
-65534;
-65535,14,2;
-1,0,102;
-65534;
-65534;
diff --git a/third_party/subzero/tests_lit/parse_errs/bad-bb-size.test b/third_party/subzero/tests_lit/parse_errs/bad-bb-size.test
deleted file mode 100644
index 6176dfe..0000000
--- a/third_party/subzero/tests_lit/parse_errs/bad-bb-size.test
+++ /dev/null
@@ -1,10 +0,0 @@
-; Test if we recognize a bad basic block count in a function block.
-
-; REQUIRES: no_minimal_build
-
-; RUN: not %pnacl_sz -bitcode-as-text %p/Inputs/bad-bb-size.tbc \
-; RUN: -bitcode-format=pnacl -notranslate -build-on-read \
-; RUN: -allow-externally-defined-symbols 2>&1 \
-; RUN: | FileCheck %s
-
-; CHECK: Function defines 3105555534 basic blocks, which is too big for a function containing 36 bytes
diff --git a/third_party/subzero/tests_lit/parse_errs/bad-global-alignment.test b/third_party/subzero/tests_lit/parse_errs/bad-global-alignment.test
deleted file mode 100644
index f35c5b2..0000000
--- a/third_party/subzero/tests_lit/parse_errs/bad-global-alignment.test
+++ /dev/null
@@ -1,11 +0,0 @@
-; Test that we check that alignment on global variables can't be greater
-; than 2**29.
-
-
-; REQUIRES: no_minimal_build
-
-; RUN: not %pnacl_sz -bitcode-as-text %p/Inputs/bad-global-alignment.tbc \
-; RUN: -bitcode-format=pnacl -notranslate -build-on-read 2>&1 \
-; RUN: | FileCheck %s
-
-; CHECK: Global variable alignment greater than 2**29. Found: 2**30
diff --git a/third_party/subzero/tests_lit/parse_errs/bad-intrinsic-arg.test b/third_party/subzero/tests_lit/parse_errs/bad-intrinsic-arg.test
deleted file mode 100644
index ffbb894..0000000
--- a/third_party/subzero/tests_lit/parse_errs/bad-intrinsic-arg.test
+++ /dev/null
@@ -1,29 +0,0 @@
-; Tests that we correctly check parameter types for intrinsics.
-
-; REQUIRES: no_minimal_build
-
-; RUN: not %pnacl_sz -bitcode-as-text \
-; RUN: %p/Inputs/bad-intrinsic-arg.tbc \
-; RUN: -bitcode-format=pnacl -notranslate -build-on-read \
-; RUN: -allow-externally-defined-symbols 2>&1 \
-; RUN: | FileCheck %s
-
-; CHECK: Invalid type signature for intrinsic llvm.nacl.setjmp: i32 (double)
-
-; RUN: pnacl-bcfuzz -bitcode-as-text \
-; RUN: %p/Inputs/bad-intrinsic-arg.tbc -output - \
-; RUN: | not pnacl-bcdis -no-records | FileCheck -check-prefix=ASM %s
-
-; ASM: module { // BlockID = 8
-; ASM: declare external i32 @f0(double);
-; ASM: valuesymtab { // BlockID = 14
-; ASM: @f0 : "llvm.nacl.setjmp";
-; ASM: Error(118:0): Intrinsic llvm.nacl.setjmp expects i8* for argument 1. Found: double
-; ASM: }
-; ASM: function void @f3(i32 %p0, double %p1) { // BlockID = 12
-; ASM: blocks 1;
-; ASM: %b0:
-; ASM: %v0 = call i32 @f0(double %p1);
-; ASM: ret void;
-; ASM: }
-; ASM: }
diff --git a/third_party/subzero/tests_lit/parse_errs/bad-switch-case.test b/third_party/subzero/tests_lit/parse_errs/bad-switch-case.test
deleted file mode 100644
index 41e9e09..0000000
--- a/third_party/subzero/tests_lit/parse_errs/bad-switch-case.test
+++ /dev/null
@@ -1,7 +0,0 @@
-; REQUIRES: no_minimal_build
-; RUN: not %pnacl_sz -bitcode-as-text %p/Inputs/bad-switch-case.tbc \
-; RUN: -bitcode-format=pnacl -notranslate -build-on-read \
-; RUN: -allow-externally-defined-symbols 2>&1 \
-; RUN: | FileCheck -check-prefix=BAD-SWITCH-CASE %s
-
-; BAD-SWITCH-CASE: Reference to basic block 3105555534 not found. Must be less than 6
diff --git a/third_party/subzero/tests_lit/parse_errs/bad-var-fwdref.test b/third_party/subzero/tests_lit/parse_errs/bad-var-fwdref.test
deleted file mode 100644
index 4d8f003..0000000
--- a/third_party/subzero/tests_lit/parse_errs/bad-var-fwdref.test
+++ /dev/null
@@ -1,10 +0,0 @@
-; Test if we recognize a forward reference that can't be in function block.
-
-; REQUIRES: no_minimal_build
-
-; RUN: not %pnacl_sz -bitcode-as-text %p/Inputs/bad-var-fwdref.tbc \
-; RUN: -bitcode-format=pnacl -notranslate -build-on-read \
-; RUN: -allow-externally-defined-symbols 2>&1 \
-; RUN: | FileCheck %s
-
-; CHECK: Forward reference @3105555534 too big. Have 1 globals and function contains 16 bytes
diff --git a/third_party/subzero/tests_lit/parse_errs/call-fcn-bad-param-type.ll b/third_party/subzero/tests_lit/parse_errs/call-fcn-bad-param-type.ll
deleted file mode 100644
index 093807f..0000000
--- a/third_party/subzero/tests_lit/parse_errs/call-fcn-bad-param-type.ll
+++ /dev/null
@@ -1,16 +0,0 @@
-; Test that a function parameter must be a legal parameter type (unless
-; declaration is intrinsic).
-
-; REQUIRES: no_minimal_build
-
-; RUN: %p2i --expect-fail -i %s --insts --args \
-; RUN: -allow-externally-defined-symbols | FileCheck %s
-
-declare void @f(i8);
-; CHECK: Invalid type signature for f: void (i8)
-
-define void @Test() {
-entry:
- call void @f(i8 1)
- ret void
-}
diff --git a/third_party/subzero/tests_lit/parse_errs/call-fcn-bad-param-type.test b/third_party/subzero/tests_lit/parse_errs/call-fcn-bad-param-type.test
deleted file mode 100644
index 32b9c6b..0000000
--- a/third_party/subzero/tests_lit/parse_errs/call-fcn-bad-param-type.test
+++ /dev/null
@@ -1,49 +0,0 @@
-; Show that we check parameter types of a function call against paramter types
-; of called function.
-
-; REQUIRES: no_minimal_build
-
-; RUN: not %pnacl_sz -bitcode-as-text %p/Inputs/call-fcn-bad-param-type.tbc \
-; RUN: -bitcode-format=pnacl -notranslate -build-on-read \
-; RUN: -allow-externally-defined-symbols 2>&1 \
-; RUN: | FileCheck %s
-
-; RUN: pnacl-bcfuzz -bitcode-as-text -output - \
-; RUN: %p/Inputs/call-fcn-bad-param-type.tbc \
-; RUN: | not pnacl-bcdis -no-records | FileCheck %s --check-prefix=DIS
-
-; DIS: module { // BlockID = 8
-; DIS-NEXT: version 1;
-; DIS-NEXT: types { // BlockID = 17
-; DIS-NEXT: count 5;
-; DIS-NEXT: @t0 = void;
-; DIS-NEXT: @t1 = i32;
-; DIS-NEXT: @t2 = i8;
-; DIS-NEXT: @t3 = void (i32);
-; DIS-NEXT: @t4 = void ();
-; DIS-NEXT: }
-; DIS-NEXT: declare external void @f0(i32);
-; DIS-NEXT: define external void @f1();
-; DIS-NEXT: globals { // BlockID = 19
-; DIS-NEXT: count 0;
-; DIS-NEXT: }
-; DIS-NEXT: valuesymtab { // BlockID = 14
-; DIS-NEXT: @f1 : "Test";
-; DIS-NEXT: @f0 : "f";
-; DIS-NEXT: }
-; DIS-NEXT: function void @f1() { // BlockID = 12
-; DIS-NEXT: blocks 1;
-; DIS-NEXT: constants { // BlockID = 11
-; DIS-NEXT: i32:
-; DIS-NEXT: %c0 = i32 1;
-; DIS-NEXT: i8:
-; DIS-NEXT: %c1 = i8 1;
-; DIS-NEXT: }
-; DIS-NEXT: %b0:
-; DIS-NEXT: %v0 = add i8 %c1, %c1;
-; DIS-NEXT: call void @f0(i8 %c1);
-; DIS-NEXT: Error({{.*}}): Parameter 1 mismatch: i8 and i32
-; CHECK: Argument 1 of f expects i32. Found: i8
-; DIS-NEXT: ret void;
-; DIS-NEXT: }
-; DIS-NEXT: }
diff --git a/third_party/subzero/tests_lit/parse_errs/call-fcn-bad-return-type.ll b/third_party/subzero/tests_lit/parse_errs/call-fcn-bad-return-type.ll
deleted file mode 100644
index 0a9ce58..0000000
--- a/third_party/subzero/tests_lit/parse_errs/call-fcn-bad-return-type.ll
+++ /dev/null
@@ -1,19 +0,0 @@
-; Test that even if a call return type matches its declaration, it must still be
-; a legal call return type (unless declaration is intrinsic).
-
-; REQUIRES: no_minimal_build
-
-; RUN: %p2i --expect-fail -i %s --insts --args \
-; RUN: -allow-externally-defined-symbols | FileCheck %s
-
-declare i32 @f();
-
-declare i64 @g();
-
-define void @Test(i32 %ifcn) {
-entry:
- %fcn = inttoptr i32 %ifcn to i1()*
- %v = call i1 %fcn()
-; CHECK: Return type of function is invalid: i1
- ret void
-}
diff --git a/third_party/subzero/tests_lit/parse_errs/call-indirect-i8.ll b/third_party/subzero/tests_lit/parse_errs/call-indirect-i8.ll
deleted file mode 100644
index c1a8947..0000000
--- a/third_party/subzero/tests_lit/parse_errs/call-indirect-i8.ll
+++ /dev/null
@@ -1,13 +0,0 @@
-; Tests that we don't allow illegal sized parameters on indirect calls.
-
-; REQUIRES: no_minimal_build
-
-; RUN: %p2i --expect-fail -i %s --insts | FileCheck %s
-
-define internal void @CallIndirectI32(i32 %f_addr) {
-entry:
- %f = inttoptr i32 %f_addr to i32(i8)*
- %r = call i32 %f(i8 1)
-; CHECK: Argument 1 of function has invalid type: i8
- ret void
-}
diff --git a/third_party/subzero/tests_lit/parse_errs/dup-module-vst.test b/third_party/subzero/tests_lit/parse_errs/dup-module-vst.test
deleted file mode 100644
index c526bd9..0000000
--- a/third_party/subzero/tests_lit/parse_errs/dup-module-vst.test
+++ /dev/null
@@ -1,21 +0,0 @@
-; Test if we detect multiple module-level symbol tables in bitcode.
-
-; REQUIRES: no_minimal_build
-
-; RUN: not %pnacl_sz -bitcode-as-text %p/Inputs/dup-module-vst.tbc \
-; RUN: -bitcode-format=pnacl -notranslate -build-on-read 2>&1 \
-; RUN: | FileCheck %s
-
-; CHECK: Duplicate valuesymtab in module
-
-; RUN: pnacl-bcfuzz -bitcode-as-text %p/Inputs/dup-module-vst.tbc \
-; RUN: -output - | pnacl-bcdis -no-records | FileCheck -check-prefix=ASM %s
-
-; ASM: module { // BlockID = 8
-; ASM: valuesymtab { // BlockID = 14
-; ASM: @f0 : "f";
-; ASM: }
-; ASM: valuesymtab { // BlockID = 14
-; ASM: @f0 : "f";
-; ASM: }
-; ASM: }
diff --git a/third_party/subzero/tests_lit/parse_errs/duplicate-fcn-name.test b/third_party/subzero/tests_lit/parse_errs/duplicate-fcn-name.test
deleted file mode 100644
index 5d72d36..0000000
--- a/third_party/subzero/tests_lit/parse_errs/duplicate-fcn-name.test
+++ /dev/null
@@ -1,40 +0,0 @@
-; Test if we detect duplicate names in a symbol table.
-
-; REQUIRES: no_minimal_build
-
-; RUN: not %pnacl_sz -bitcode-as-text %p/Inputs/duplicate-fcn-name.tbc \
-; RUN: -bitcode-format=pnacl -notranslate -build-on-read 2>&1 \
-; RUN: | FileCheck %s
-
-; CHECK: Module valuesymtab defines duplicate value name: 'f'
-
-; RUN: pnacl-bcfuzz -bitcode-as-text %p/Inputs/duplicate-fcn-name.tbc -output - \
-; RUN: | pnacl-bcdis -no-records | FileCheck -check-prefix=ASM %s
-
-; ASM: module { // BlockID = 8
-; ASM: version 1;
-; ASM: types { // BlockID = 17
-; ASM: count 2;
-; ASM: @t0 = void;
-; ASM: @t1 = void ();
-; ASM: }
-; ASM: define external void @f0();
-; ASM: define external void @f1();
-; ASM: globals { // BlockID = 19
-; ASM: count 0;
-; ASM: }
-; ASM: valuesymtab { // BlockID = 14
-; ASM: @f0 : "f";
-; ASM: @f1 : "f";
-; ASM: }
-; ASM: function void @f0() { // BlockID = 12
-; ASM: blocks 1;
-; ASM: %b0:
-; ASM: ret void;
-; ASM: }
-; ASM: function void @f1() { // BlockID = 12
-; ASM: blocks 1;
-; ASM: %b0:
-; ASM: ret void;
-; ASM: }
-; ASM: }
diff --git a/third_party/subzero/tests_lit/parse_errs/fcn-bad-param-type.ll b/third_party/subzero/tests_lit/parse_errs/fcn-bad-param-type.ll
deleted file mode 100644
index a4faab2..0000000
--- a/third_party/subzero/tests_lit/parse_errs/fcn-bad-param-type.ll
+++ /dev/null
@@ -1,16 +0,0 @@
-; Test that even if a call parameter matches its declaration, it must still
-; be a legal call parameter type (unless declaration is intrinsic).
-
-; REQUIRES: no_minimal_build
-
-; RUN: %p2i --expect-fail -i %s --insts --args \
-; RUN: -allow-externally-defined-symbols | FileCheck %s
-
-declare void @f(i8);
-; CHECK: Invalid type signature for f: void (i8)
-
-define void @Test() {
-entry:
- call void @f(i8 1)
- ret void
-}
diff --git a/third_party/subzero/tests_lit/parse_errs/fcn-value-index-isnt-defined.test b/third_party/subzero/tests_lit/parse_errs/fcn-value-index-isnt-defined.test
deleted file mode 100644
index 9390e95..0000000
--- a/third_party/subzero/tests_lit/parse_errs/fcn-value-index-isnt-defined.test
+++ /dev/null
@@ -1,43 +0,0 @@
-; Test if we detect duplicate names in a symbol table.
-
-; REQUIRES: no_minimal_build
-
-; RUN: not %pnacl_sz -bitcode-as-text -allow-externally-defined-symbols \
-; RUN: %p/Inputs/fcn-value-index-isnt-defined.tbc \
-; RUN: -bitcode-format=pnacl -notranslate -build-on-read 2>&1 \
-; RUN: | FileCheck %s
-
-; CHECK: Value index {{.*}} not defined!
-
-; RUN: pnacl-bcfuzz -bitcode-as-text \
-; RUN: %p/Inputs/fcn-value-index-isnt-defined.tbc -output - \
-; RUN: | not pnacl-bcdis -no-records | FileCheck -check-prefix=ASM %s
-
-; ASM: module { // BlockID = 8
-; ASM: version 1;
-; ASM: types { // BlockID = 17
-; ASM: count 4;
-; ASM: @t0 = i32;
-; ASM: @t1 = i32 ();
-; ASM: @t2 = i8;
-; ASM: @t3 = void;
-; ASM: }
-; ASM: define external i32 @f0();
-; ASM: globals { // BlockID = 19
-; ASM: count 0;
-; ASM: }
-; ASM: valuesymtab { // BlockID = 14
-; ASM: @f0 : "f";
-; ASM: }
-; ASM: function i32 @f0() { // BlockID = 12
-; ASM: blocks 1;
-; ASM: constants { // BlockID = 11
-; ASM: i32:
-; ASM: %c0 = i32 1;
-; ASM: }
-; ASM: %b0:
-; ASM: %v0 = alloca i8, i32 %c0, align 4;
-; ASM: ret void %v1;
-; ASM: Error({{.*}}): Can't find type for %v1
-; ASM: }
-; ASM: }
diff --git a/third_party/subzero/tests_lit/parse_errs/indirect-call-on-float.test b/third_party/subzero/tests_lit/parse_errs/indirect-call-on-float.test
deleted file mode 100644
index fc68512..0000000
--- a/third_party/subzero/tests_lit/parse_errs/indirect-call-on-float.test
+++ /dev/null
@@ -1,21 +0,0 @@
-; Tests that we check the call address is a pointer on an indirect call.
-
-; REQUIRES: no_minimal_build
-
-; RUN: not %pnacl_sz -bitcode-as-text -allow-externally-defined-symbols \
-; RUN: %p/Inputs/indirect-call-on-float.tbc \
-; RUN: -bitcode-format=pnacl -notranslate -build-on-read 2>&1 \
-; RUN: | FileCheck %s
-
-; CHECK: Call indirect address not i32. Found: float
-
-; RUN: pnacl-bcfuzz -bitcode-as-text \
-; RUN: %p/Inputs/indirect-call-on-float.tbc -output - \
-; RUN: | not pnacl-bcdis -no-records | FileCheck -check-prefix=ASM %s
-
-; ASM: function void @f1(i32 %p0, float %p1) { // BlockID = 12
-; ASM: blocks 1;
-; ASM: %b0:
-; ASM: call void %p1();
-; ASM: ret void;
-; ASM: }
diff --git a/third_party/subzero/tests_lit/parse_errs/insertelt-wrong-type.test b/third_party/subzero/tests_lit/parse_errs/insertelt-wrong-type.test
deleted file mode 100644
index 3e38a97..0000000
--- a/third_party/subzero/tests_lit/parse_errs/insertelt-wrong-type.test
+++ /dev/null
@@ -1,32 +0,0 @@
-; Tests that we check if the element being inserted into a vector is of the
-; right type.
-
-; REQUIRES: no_minimal_build
-
-; RUN: not %pnacl_sz -bitcode-as-text -allow-externally-defined-symbols \
-; RUN: %p/Inputs/insertelt-wrong-type.tbc \
-; RUN: -bitcode-format=pnacl -notranslate -build-on-read 2>&1 \
-; RUN: | FileCheck %s
-
-; CHECK: Insertelement: Element type i8 doesn't match vector type <16 x i1>
-
-; RUN: pnacl-bcfuzz -bitcode-as-text \
-; RUN: %p/Inputs/insertelt-wrong-type.tbc -output - \
-; RUN: | not pnacl-bcdis -no-records | FileCheck -check-prefix=ASM %s
-
-; ASM: function void @f0(<16 x i1> %p0) { // BlockID = 12
-; ASM: blocks 1;
-; ASM: constants { // BlockID = 11
-; ASM: i1:
-; ASM: %c0 = i1 1;
-; ASM: i8:
-; ASM: %c1 = i8 1;
-; ASM: i32:
-; ASM: %c2 = i32 0;
-; ASM: }
-; ASM: %b0:
-; ASM: %v0 = add i8 %c1, %c1;
-; ASM: %v1 = insertelement <16 x i1> %p0, i8 %c1, i32 %c2;
-; ASM: Error(128:0): insertelement: Illegal element type i8. Expected: i1
-; ASM: ret void;
-; ASM: }
diff --git a/third_party/subzero/tests_lit/parse_errs/insertextract-err.ll b/third_party/subzero/tests_lit/parse_errs/insertextract-err.ll
deleted file mode 100644
index 9898924..0000000
--- a/third_party/subzero/tests_lit/parse_errs/insertextract-err.ll
+++ /dev/null
@@ -1,194 +0,0 @@
-; Tests malformed insertelement and extractelement vector instructions.
-
-; RUN: %if --need=allow_dump --command \
-; RUN: %p2i --expect-fail -i %s --allow-pnacl-reader-error-recovery \
-; RUN: --filetype=obj -o /dev/null --args -notranslate \
-; RUN: | %if --need=allow_dump --command FileCheck %s
-
-; RUN: %if --need=no_dump --command \
-; RUN: %p2i --expect-fail -i %s --allow-pnacl-reader-error-recovery \
-; RUN: --filetype=obj -o /dev/null --args -notranslate \
-; RUN: | %if --need=no_dump --command FileCheck %s --check-prefix=MIN
-
-define void @ExtractV4xi1(<4 x i1> %v, i32 %i) {
- %e0 = extractelement <4 x i1> %v, i32 %i
-; CHECK: Error{{.*}} not {{.*}} constant
-; MIN: Error{{.*}} Invalid function record: <6 4 3>
- %e1 = extractelement <4 x i1> %v, i32 4
-; CHECK: Error{{.*}} not in range
-; MIN: Error{{.*}} Invalid function record: <6 5 3>
- %e2 = extractelement <4 x i1> %v, i32 9
-; CHECK: Error{{.*}} not in range
-; MIN: Error{{.*}} Invalid function record: <6 6 3>
- ret void
-}
-
-define void @ExtractV8xi1(<8 x i1> %v, i32 %i) {
- %e0 = extractelement <8 x i1> %v, i32 %i
-; CHECK: Error{{.*}} not {{.*}} constant
-; MIN: Error{{.*}} Invalid function record: <6 4 3>
- %e1 = extractelement <8 x i1> %v, i32 8;
-; CHECK: Error{{.*}} not in range
-; MIN: Error{{.*}} Invalid function record: <6 5 3>
- %e2 = extractelement <8 x i1> %v, i32 9;
-; CHECK: Error{{.*}} not in range
-; MIN: Error{{.*}} Invalid function record: <6 6 3>
- ret void
-}
-
-define void @ExtractV16xi1(<16 x i1> %v, i32 %i) {
- %e0 = extractelement <16 x i1> %v, i32 %i
-; CHECK: Error{{.*}} not {{.*}} constant
-; MIN: Error{{.*}} Invalid function record: <6 4 3>
- %e1 = extractelement <16 x i1> %v, i32 16
-; CHECK: Error{{.*}} not in range
-; MIN: Error{{.*}} Invalid function record: <6 5 3>
- %e2 = extractelement <16 x i1> %v, i32 24
-; CHECK: Error{{.*}} not in range
-; MIN: Error{{.*}} Invalid function record: <6 6 3>
- ret void
-}
-
-define void @ExtractV16xi8(<16 x i8> %v, i32 %i) {
- %e0 = extractelement <16 x i8> %v, i32 %i
-; CHECK: Error{{.*}} not {{.*}} constant
-; MIN: Error{{.*}} Invalid function record: <6 4 3>
- %e1 = extractelement <16 x i8> %v, i32 16
-; CHECK: Error{{.*}} not in range
-; MIN: Error{{.*}} Invalid function record: <6 5 3>
- %e2 = extractelement <16 x i8> %v, i32 71
-; CHECK: Error{{.*}} not in range
-; MIN: Error{{.*}} Invalid function record: <6 6 3>
- ret void
-}
-
-define void @ExtractV8xi16(<8 x i16> %v, i32 %i) {
- %e0 = extractelement <8 x i16> %v, i32 %i
-; CHECK: Error{{.*}} not {{.*}} constant
-; MIN: Error{{.*}} Invalid function record: <6 4 3>
- %e1 = extractelement <8 x i16> %v, i32 8
-; CHECK: Error{{.*}} not in range
-; MIN: Error{{.*}} Invalid function record: <6 5 3>
- %e2 = extractelement <8 x i16> %v, i32 15
-; CHECK: Error{{.*}} not in range
-; MIN: Error{{.*}} Invalid function record: <6 6 3>
- ret void
-}
-
-define i32 @ExtractV4xi32(<4 x i32> %v, i32 %i) {
- %e0 = extractelement <4 x i32> %v, i32 %i
-; CHECK: Error{{.*}} not {{.*}} constant
-; MIN: Error{{.*}} Invalid function record: <6 4 3>
- %e1 = extractelement <4 x i32> %v, i32 4
-; CHECK: Error{{.*}} not in range
-; MIN: Error{{.*}} Invalid function record: <6 5 3>
- %e2 = extractelement <4 x i32> %v, i32 17
-; CHECK: Error{{.*}} not in range
-; MIN: Error{{.*}} Invalid function record: <6 6 3>
- ret i32 %e0
-}
-
-define float @ExtractV4xfloat(<4 x float> %v, i32 %i) {
- %e0 = extractelement <4 x float> %v, i32 %i
-; CHECK: Error{{.*}} not {{.*}} constant
-; MIN: Error{{.*}} Invalid function record: <6 3 2>
- %e1 = extractelement <4 x float> %v, i32 4
-; CHECK: Error{{.*}} not in range
-; MIN: Error{{.*}} Invalid function record: <6 4 2>
- %e2 = extractelement <4 x float> %v, i32 4
-; CHECK: Error{{.*}} not in range
-; MIN: Error{{.*}} Invalid function record: <6 5 3>
- ret float %e2
-}
-
-define <4 x i1> @InsertV4xi1(<4 x i1> %v, i32 %i) {
- %r0 = insertelement <4 x i1> %v, i1 1, i32 %i
-; CHECK: Error{{.*}} not {{.*}} constant
-; MIN: Error{{.*}} Invalid function record: <7 5 1 4>
- %r1 = insertelement <4 x i1> %v, i1 1, i32 4
-; CHECK: Error{{.*}} not in range
-; MIN: Error{{.*}} Invalid function record: <7 6 2 4>
- %r2 = insertelement <4 x i1> %v, i1 1, i32 7
-; CHECK: Error{{.*}} not in range
-; MIN: Error{{.*}} Invalid function record: <7 7 3 4>
- ret <4 x i1> %r2
-}
-
-define <8 x i1> @InsertV8xi1(<8 x i1> %v, i32 %i) {
- %r0 = insertelement <8 x i1> %v, i1 0, i32 %i
-; CHECK: Error{{.*}} not {{.*}} constant
-; MIN: Error{{.*}} Invalid function record: <7 5 1 4>
- %r1 = insertelement <8 x i1> %v, i1 0, i32 8
-; CHECK: Error{{.*}} not in range
-; MIN: Error{{.*}} Invalid function record: <7 6 2 4>
- %r2 = insertelement <8 x i1> %v, i1 0, i32 88
-; CHECK: Error{{.*}} not in range
-; MIN: Error{{.*}} Invalid function record: <7 7 3 4>
- ret <8 x i1> %r2
-}
-
-define <16 x i1> @InsertV16xi1(<16 x i1> %v, i32 %i) {
- %r = insertelement <16 x i1> %v, i1 1, i32 %i
-; CHECK: Error{{.*}} not {{.*}} constant
-; MIN: Error{{.*}} Invalid function record: <7 5 1 4>
- ret <16 x i1> %r
- %r1 = insertelement <16 x i1> %v, i1 1, i32 16
-; CHECK: Error{{.*}} not in range
-; MIN: Error{{.*}} Invalid function record: <7 6 2 4>
- %r2 = insertelement <16 x i1> %v, i1 1, i32 31
-; CHECK: Error{{.*}} not in range
-; MIN: Error{{.*}} Invalid function record: <7 7 3 4>
- ret <16 x i1> %r2
-}
-
-define <16 x i8> @InsertV16xi8(<16 x i8> %v, i32 %i) {
- %r0 = insertelement <16 x i8> %v, i8 34, i32 %i
-; CHECK: Error{{.*}} not {{.*}} constant
-; MIN: Error{{.*}} Invalid function record: <7 5 1 4>
- %r1 = insertelement <16 x i8> %v, i8 34, i32 16
-; CHECK: Error{{.*}} not in range
-; MIN: Error{{.*}} Invalid function record: <7 6 2 4>
- %r2 = insertelement <16 x i8> %v, i8 34, i32 19
-; CHECK: Error{{.*}} not in range
-; MIN: Error{{.*}} Invalid function record: <7 7 3 4>
- ret <16 x i8> %r0
-}
-
-define <8 x i16> @InsertV8xi16(<8 x i16> %v, i32 %i) {
- %r0 = insertelement <8 x i16> %v, i16 289, i32 %i
-; CHECK: Error{{.*}} not {{.*}} constant
-; MIN: Error{{.*}} Invalid function record: <7 5 1 4>
- %r1 = insertelement <8 x i16> %v, i16 289, i32 8
-; CHECK: Error{{.*}} not in range
-; MIN: Error{{.*}} Invalid function record: <7 6 2 4>
- %r2 = insertelement <8 x i16> %v, i16 289, i32 19
-; CHECK: Error{{.*}} not in range
-; MIN: Error{{.*}} Invalid function record: <7 7 3 4>
- ret <8 x i16> %r1
-}
-
-define <4 x i32> @InsertV4xi32(<4 x i32> %v, i32 %i) {
- %r0 = insertelement <4 x i32> %v, i32 54545454, i32 %i
-; CHECK: Error{{.*}} not {{.*}} constant
-; MIN: Error{{.*}} Invalid function record: <7 5 3 4>
- %r1 = insertelement <4 x i32> %v, i32 54545454, i32 4
-; CHECK: Error{{.*}} not in range
-; MIN: Error{{.*}} Invalid function record: <7 6 4 3>
- %r2 = insertelement <4 x i32> %v, i32 54545454, i32 9
-; CHECK: Error{{.*}} not in range
-; MIN: Error{{.*}} Invalid function record: <7 7 5 3>
- ret <4 x i32> %r2
-}
-
-define <4 x float> @InsertV4xfloat(<4 x float> %v, i32 %i) {
- %r0 = insertelement <4 x float> %v, float 3.0, i32 %i
-; CHECK: Error{{.*}} not {{.*}} constant
-; MIN: Error{{.*}} Invalid function record: <7 5 1 4>
- %r1 = insertelement <4 x float> %v, float 3.0, i32 4
-; CHECK: Error{{.*}} not in range
-; MIN: Error{{.*}} Invalid function record: <7 6 2 4>
- %r2 = insertelement <4 x float> %v, float 3.0, i32 44
-; CHECK: Error{{.*}} not in range
-; MIN: Error{{.*}} Invalid function record: <7 7 3 4>
- ret <4 x float> %r2
-}
diff --git a/third_party/subzero/tests_lit/parse_errs/lit.local.cfg b/third_party/subzero/tests_lit/parse_errs/lit.local.cfg
deleted file mode 100644
index e531cac..0000000
--- a/third_party/subzero/tests_lit/parse_errs/lit.local.cfg
+++ /dev/null
@@ -1 +0,0 @@
-config.suffixes = ['.ll', '.test']
diff --git a/third_party/subzero/tests_lit/parse_errs/multiple-modules.test b/third_party/subzero/tests_lit/parse_errs/multiple-modules.test
deleted file mode 100644
index 62ff6aa..0000000
--- a/third_party/subzero/tests_lit/parse_errs/multiple-modules.test
+++ /dev/null
@@ -1,22 +0,0 @@
-; Tests that we check for multiple modules in the bitcode file.
-
-; REQUIRES: no_minimal_build
-
-; RUN: not %pnacl_sz -bitcode-as-text \
-; RUN: %p/Inputs/multiple-modules.tbc \
-; RUN: -bitcode-format=pnacl -notranslate -build-on-read 2>&1 \
-; RUN: | FileCheck %s
-
-; CHECK: Input can't contain more than one module
-
-; RUN: pnacl-bcfuzz -bitcode-as-text \
-; RUN: %p/Inputs/multiple-modules.tbc -output - \
-; RUN: | not pnacl-bcdis -no-records | FileCheck -check-prefix=ASM %s
-
-; ASM: module { // BlockID = 8
-; ASM: version 1;
-; ASM: }
-; ASM: module { // BlockID = 8
-; ASM: version 1;
-; ASM: }
-; ASM: Error(38:4): Expected 1 top level block in bitcode: Found:2
diff --git a/third_party/subzero/tests_lit/parse_errs/nacl-fake-intrinsic.ll b/third_party/subzero/tests_lit/parse_errs/nacl-fake-intrinsic.ll
deleted file mode 100644
index f1e066c..0000000
--- a/third_party/subzero/tests_lit/parse_errs/nacl-fake-intrinsic.ll
+++ /dev/null
@@ -1,11 +0,0 @@
-; Tests that we don't get fooled by a fake NaCl intrinsic.
-
-; REQUIRES: allow_dump
-
-; RUN: %p2i --expect-fail -i %s --insts --args \
-; RUN: -verbose=inst -allow-externally-defined-symbols \
-; RUN: | FileCheck %s
-
-declare i32 @llvm.fake.i32(i32)
-
-; CHECK: Error({{.*}}): Invalid intrinsic name: llvm.fake.i32
diff --git a/third_party/subzero/tests_lit/parse_errs/parallel.ll b/third_party/subzero/tests_lit/parse_errs/parallel.ll
deleted file mode 100644
index 6b1ba99..0000000
--- a/third_party/subzero/tests_lit/parse_errs/parallel.ll
+++ /dev/null
@@ -1,23 +0,0 @@
-; Test that we report a bug at the same place, independent of a parallel parse.
-
-; REQUIRES: no_minimal_build
-
-; RUN: %p2i --expect-fail -i %s --args -threads=0 -parse-parallel=0 \
-; RUN: -allow-externally-defined-symbols | FileCheck %s
-
-; RUN: %p2i --expect-fail -i %s --args -threads=1 -parse-parallel=1 \
-; RUN: -allow-externally-defined-symbols | FileCheck %s
-
-declare i32 @f();
-
-declare i64 @g();
-
-define void @Test(i32 %ifcn) {
-entry:
- %fcn = inttoptr i32 %ifcn to i1()*
- %v = call i1 %fcn()
-
-; CHECK: Error(222:6): Return type of function is invalid: i1
-
- ret void
-}
diff --git a/third_party/subzero/tests_lit/parse_errs/symtab-after-fcn.test b/third_party/subzero/tests_lit/parse_errs/symtab-after-fcn.test
deleted file mode 100644
index a74bbd2..0000000
--- a/third_party/subzero/tests_lit/parse_errs/symtab-after-fcn.test
+++ /dev/null
@@ -1,22 +0,0 @@
-; Test if we detect if the value symbol table appears after a function block.
-
-; REQUIRES: no_minimal_build
-
-; RUN: not %pnacl_sz -bitcode-as-text %p/Inputs/symtab-after-fcn.tbc \
-; RUN: -bitcode-format=pnacl -notranslate -build-on-read \
-; RUN: -allow-externally-defined-symbols 2>&1 \
-; RUN: | FileCheck %s
-
-; CHECK: Module valuesymtab not allowed after function blocks
-
-; RUN: pnacl-bcfuzz -bitcode-as-text %p/Inputs/symtab-after-fcn.tbc \
-; RUN: -output - | not pnacl-bcdis -no-records \
-; RUN: | FileCheck -check-prefix=ASM %s
-
-; ASM: module { // BlockID = 8
-; ASM: function void @f0() { // BlockID = 12
-; ASM: }
-; ASM: valuesymtab { // BlockID = 14
-; ASM: Error({{.*}}): Module symbol table must appear before function blocks
-; ASM: }
-; ASM: }
diff --git a/third_party/subzero/tests_lit/reader_tests/Inputs/binop-newform.tbc b/third_party/subzero/tests_lit/reader_tests/Inputs/binop-newform.tbc
deleted file mode 100644
index 65f7b81..0000000
--- a/third_party/subzero/tests_lit/reader_tests/Inputs/binop-newform.tbc
+++ /dev/null
@@ -1,18 +0,0 @@
-65535,8,2;
-1,1;
-65535,17,2;
-1,3;
-7,32;
-21,0,0,0,0;
-2;
-65534;
-8,1,0,0,3;
-65535,19,2;
-5,0;
-65534;
-65535,12,4;
-1,1;
-2,2,1,0;
-10,1;
-65534;
-65534;
diff --git a/third_party/subzero/tests_lit/reader_tests/Inputs/binop-oldform.tbc b/third_party/subzero/tests_lit/reader_tests/Inputs/binop-oldform.tbc
deleted file mode 100644
index 81e2c0e..0000000
--- a/third_party/subzero/tests_lit/reader_tests/Inputs/binop-oldform.tbc
+++ /dev/null
@@ -1,18 +0,0 @@
-65535,8,2;
-1,1;
-65535,17,2;
-1,3;
-7,32;
-21,0,0,0,0;
-2;
-65534;
-8,1,0,0,3;
-65535,19,2;
-5,0;
-65534;
-65535,12,4;
-1,1;
-2,2,1,0,5169;
-10,1;
-65534;
-65534;
diff --git a/third_party/subzero/tests_lit/reader_tests/alloca.ll b/third_party/subzero/tests_lit/reader_tests/alloca.ll
deleted file mode 100644
index bb18e74..0000000
--- a/third_party/subzero/tests_lit/reader_tests/alloca.ll
+++ /dev/null
@@ -1,165 +0,0 @@
-; Test if we can read alloca instructions.
-
-; RUN: %p2i -i %s --insts | FileCheck %s
-; RUN: %p2i -i %s --args -notranslate -timing | \
-; RUN: FileCheck --check-prefix=NOIR %s
-
-; Show examples where size is defined by a constant.
-
-define internal i32 @AllocaA0Size1() {
-entry:
- %array = alloca i8, i32 1
- %addr = ptrtoint i8* %array to i32
- ret i32 %addr
-
-; CHECK: entry:
-; CHECK-NEXT: %array = alloca i8, i32 1
-; CHECK-NEXT: ret i32 %array
-}
-
-define internal i32 @AllocaA0Size2() {
-entry:
- %array = alloca i8, i32 2
- %addr = ptrtoint i8* %array to i32
- ret i32 %addr
-
-; CHECK: entry:
-; CHECK-NEXT: %array = alloca i8, i32 2
-; CHECK-NEXT: ret i32 %array
-}
-
-define internal i32 @AllocaA0Size3() {
-entry:
- %array = alloca i8, i32 3
- %addr = ptrtoint i8* %array to i32
- ret i32 %addr
-
-; CHECK: entry:
-; CHECK-NEXT: %array = alloca i8, i32 3
-; CHECK-NEXT: ret i32 %array
-}
-
-define internal i32 @AllocaA0Size4() {
-entry:
- %array = alloca i8, i32 4
- %addr = ptrtoint i8* %array to i32
- ret i32 %addr
-
-; CHECK: entry:
-; CHECK-NEXT: %array = alloca i8, i32 4
-; CHECK-NEXT: ret i32 %array
-}
-
-define internal i32 @AllocaA1Size4(i32 %n) {
-entry:
- %array = alloca i8, i32 4, align 1
- %addr = ptrtoint i8* %array to i32
- ret i32 %addr
-
-; CHECK: entry:
-; CHECK-NEXT: %array = alloca i8, i32 4, align 1
-; CHECK-NEXT: ret i32 %array
-}
-
-define internal i32 @AllocaA2Size4(i32 %n) {
-entry:
- %array = alloca i8, i32 4, align 2
- %addr = ptrtoint i8* %array to i32
- ret i32 %addr
-
-; CHECK: entry:
-; CHECK-NEXT: %array = alloca i8, i32 4, align 2
-; CHECK-NEXT: ret i32 %array
-}
-
-define internal i32 @AllocaA8Size4(i32 %n) {
-entry:
- %array = alloca i8, i32 4, align 8
- %addr = ptrtoint i8* %array to i32
- ret i32 %addr
-
-; CHECK: entry:
-; CHECK-NEXT: %array = alloca i8, i32 4, align 8
-; CHECK-NEXT: ret i32 %array
-}
-
-define internal i32 @Alloca16Size4(i32 %n) {
-entry:
- %array = alloca i8, i32 4, align 16
- %addr = ptrtoint i8* %array to i32
- ret i32 %addr
-
-; CHECK: entry:
-; CHECK-NEXT: %array = alloca i8, i32 4, align 16
-; CHECK-NEXT: ret i32 %array
-}
-
-; Show examples where size is not known at compile time.
-
-define internal i32 @AllocaVarsizeA0(i32 %n) {
-entry:
- %array = alloca i8, i32 %n
- %addr = ptrtoint i8* %array to i32
- ret i32 %addr
-
-; CHECK: entry:
-; CHECK-NEXT: %array = alloca i8, i32 %n
-; CHECK-NEXT: ret i32 %array
-}
-
-define internal i32 @AllocaVarsizeA1(i32 %n) {
-entry:
- %array = alloca i8, i32 %n, align 1
- %addr = ptrtoint i8* %array to i32
- ret i32 %addr
-
-; CHECK: entry:
-; CHECK-NEXT: %array = alloca i8, i32 %n, align 1
-; CHECK-NEXT: ret i32 %array
-}
-
-define internal i32 @AllocaVarsizeA2(i32 %n) {
-entry:
- %array = alloca i8, i32 %n, align 2
- %addr = ptrtoint i8* %array to i32
- ret i32 %addr
-
-; CHECK: entry:
-; CHECK-NEXT: %array = alloca i8, i32 %n, align 2
-; CHECK-NEXT: ret i32 %array
-}
-
-define internal i32 @AllocaVarsizeA4(i32 %n) {
-entry:
- %array = alloca i8, i32 %n, align 4
- %addr = ptrtoint i8* %array to i32
- ret i32 %addr
-
-; CHECK: entry:
-; CHECK-NEXT: %array = alloca i8, i32 %n, align 4
-; CHECK-NEXT: ret i32 %array
-}
-
-define internal i32 @AllocaVarsizeA8(i32 %n) {
-entry:
- %array = alloca i8, i32 %n, align 8
- %addr = ptrtoint i8* %array to i32
- ret i32 %addr
-
-; CHECK: entry:
-; CHECK-NEXT: %array = alloca i8, i32 %n, align 8
-; CHECK-NEXT: ret i32 %array
-}
-
-define internal i32 @AllocaVarsizeA16(i32 %n) {
-entry:
- %array = alloca i8, i32 %n, align 16
- %addr = ptrtoint i8* %array to i32
- ret i32 %addr
-
-; CHECK: entry:
-; CHECK-NEXT: %array = alloca i8, i32 %n, align 16
-; CHECK-NEXT: ret i32 %array
-}
-
-; NOIR: Total across all functions
diff --git a/third_party/subzero/tests_lit/reader_tests/binop-forms.test b/third_party/subzero/tests_lit/reader_tests/binop-forms.test
deleted file mode 100644
index 086f0f0..0000000
--- a/third_party/subzero/tests_lit/reader_tests/binop-forms.test
+++ /dev/null
@@ -1,19 +0,0 @@
-; Test if we recognize both the old and the new forms of a binary instruction.
-
-; REQUIRES: no_minimal_build
-
-; Checks that the new form of binary add (without flags argument) works.
-; RUN: %pnacl_sz -verbose inst,global_init -notranslate \
-; RUN: -threads=0 -bitcode-as-text %p/Inputs/binop-newform.tbc \
-; RUN: | FileCheck %s
-
-; Checks that the old form of binary add (with flags argument) works.
-; RUN: %pnacl_sz -verbose inst,global_init -notranslate \
-; RUN: -threads=0 -bitcode-as-text %p/Inputs/binop-oldform.tbc \
-; RUN: | FileCheck %s
-
-; CHECK: define internal i32 @Function(i32 %__0, i32 %__1) {
-; CHECK: __0:
-; CHECK: %__2 = add i32 %__0, %__1
-; CHECK: ret i32 %__2
-; CHECK: }
diff --git a/third_party/subzero/tests_lit/reader_tests/binops.ll b/third_party/subzero/tests_lit/reader_tests/binops.ll
deleted file mode 100644
index c4533ac..0000000
--- a/third_party/subzero/tests_lit/reader_tests/binops.ll
+++ /dev/null
@@ -1,971 +0,0 @@
-; Tests if we can read binary operators.
-
-; RUN: %p2i -i %s --insts | FileCheck %s
-; RUN: %l2i -i %s --insts | %ifl FileCheck %s
-; RUN: %lc2i -i %s --insts | %iflc FileCheck %s
-; RUN: %p2i -i %s --args -notranslate -timing | \
-; RUN: FileCheck --check-prefix=NOIR %s
-
-; TODO(kschimpf): add i8/i16. Needs bitcasts.
-
-define internal i32 @AddI32(i32 %a, i32 %b) {
-entry:
- %add = add i32 %b, %a
- ret i32 %add
-}
-
-; CHECK: define internal i32 @AddI32(i32 %a, i32 %b) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %add = add i32 %b, %a
-; CHECK-NEXT: ret i32 %add
-; CHECK-NEXT: }
-
-define internal i64 @AddI64(i64 %a, i64 %b) {
-entry:
- %add = add i64 %b, %a
- ret i64 %add
-}
-
-; CHECK-NEXT: define internal i64 @AddI64(i64 %a, i64 %b) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %add = add i64 %b, %a
-; CHECK-NEXT: ret i64 %add
-; CHECK-NEXT: }
-
-define internal <16 x i8> @AddV16I8(<16 x i8> %a, <16 x i8> %b) {
-entry:
- %add = add <16 x i8> %b, %a
- ret <16 x i8> %add
-}
-
-; CHECK-NEXT: define internal <16 x i8> @AddV16I8(<16 x i8> %a, <16 x i8> %b) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %add = add <16 x i8> %b, %a
-; CHECK-NEXT: ret <16 x i8> %add
-; CHECK-NEXT: }
-
-define internal <8 x i16> @AddV8I16(<8 x i16> %a, <8 x i16> %b) {
-entry:
- %add = add <8 x i16> %b, %a
- ret <8 x i16> %add
-}
-
-; CHECK-NEXT: define internal <8 x i16> @AddV8I16(<8 x i16> %a, <8 x i16> %b) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %add = add <8 x i16> %b, %a
-; CHECK-NEXT: ret <8 x i16> %add
-; CHECK-NEXT: }
-
-define internal <4 x i32> @AddV4I32(<4 x i32> %a, <4 x i32> %b) {
-entry:
- %add = add <4 x i32> %b, %a
- ret <4 x i32> %add
-}
-
-; CHECK-NEXT: define internal <4 x i32> @AddV4I32(<4 x i32> %a, <4 x i32> %b) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %add = add <4 x i32> %b, %a
-; CHECK-NEXT: ret <4 x i32> %add
-; CHECK-NEXT: }
-
-define internal float @AddFloat(float %a, float %b) {
-entry:
- %add = fadd float %b, %a
- ret float %add
-}
-
-; CHECK-NEXT: define internal float @AddFloat(float %a, float %b) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %add = fadd float %b, %a
-; CHECK-NEXT: ret float %add
-; CHECK-NEXT: }
-
-define internal double @AddDouble(double %a, double %b) {
-entry:
- %add = fadd double %b, %a
- ret double %add
-}
-
-; CHECK-NEXT: define internal double @AddDouble(double %a, double %b) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %add = fadd double %b, %a
-; CHECK-NEXT: ret double %add
-; CHECK-NEXT: }
-
-define internal <4 x float> @AddV4Float(<4 x float> %a, <4 x float> %b) {
-entry:
- %add = fadd <4 x float> %b, %a
- ret <4 x float> %add
-}
-
-; CHECK-NEXT: define internal <4 x float> @AddV4Float(<4 x float> %a, <4 x float> %b) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %add = fadd <4 x float> %b, %a
-; CHECK-NEXT: ret <4 x float> %add
-; CHECK-NEXT: }
-
-; TODO(kschimpf): sub i8/i16. Needs bitcasts.
-
-define internal i32 @SubI32(i32 %a, i32 %b) {
-entry:
- %sub = sub i32 %a, %b
- ret i32 %sub
-}
-
-; CHECK-NEXT: define internal i32 @SubI32(i32 %a, i32 %b) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %sub = sub i32 %a, %b
-; CHECK-NEXT: ret i32 %sub
-; CHECK-NEXT: }
-
-define internal i64 @SubI64(i64 %a, i64 %b) {
-entry:
- %sub = sub i64 %a, %b
- ret i64 %sub
-}
-
-; CHECK-NEXT: define internal i64 @SubI64(i64 %a, i64 %b) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %sub = sub i64 %a, %b
-; CHECK-NEXT: ret i64 %sub
-; CHECK-NEXT: }
-
-define internal <16 x i8> @SubV16I8(<16 x i8> %a, <16 x i8> %b) {
-entry:
- %sub = sub <16 x i8> %a, %b
- ret <16 x i8> %sub
-}
-
-; CHECK-NEXT: define internal <16 x i8> @SubV16I8(<16 x i8> %a, <16 x i8> %b) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %sub = sub <16 x i8> %a, %b
-; CHECK-NEXT: ret <16 x i8> %sub
-; CHECK-NEXT: }
-
-define internal <8 x i16> @SubV8I16(<8 x i16> %a, <8 x i16> %b) {
-entry:
- %sub = sub <8 x i16> %a, %b
- ret <8 x i16> %sub
-}
-
-; CHECK-NEXT: define internal <8 x i16> @SubV8I16(<8 x i16> %a, <8 x i16> %b) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %sub = sub <8 x i16> %a, %b
-; CHECK-NEXT: ret <8 x i16> %sub
-; CHECK-NEXT: }
-
-define internal <4 x i32> @SubV4I32(<4 x i32> %a, <4 x i32> %b) {
-entry:
- %sub = sub <4 x i32> %a, %b
- ret <4 x i32> %sub
-}
-
-; CHECK-NEXT: define internal <4 x i32> @SubV4I32(<4 x i32> %a, <4 x i32> %b) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %sub = sub <4 x i32> %a, %b
-; CHECK-NEXT: ret <4 x i32> %sub
-; CHECK-NEXT: }
-
-define internal float @SubFloat(float %a, float %b) {
-entry:
- %sub = fsub float %a, %b
- ret float %sub
-}
-
-; CHECK-NEXT: define internal float @SubFloat(float %a, float %b) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %sub = fsub float %a, %b
-; CHECK-NEXT: ret float %sub
-; CHECK-NEXT: }
-
-define internal double @SubDouble(double %a, double %b) {
-entry:
- %sub = fsub double %a, %b
- ret double %sub
-}
-
-; CHECK-NEXT: define internal double @SubDouble(double %a, double %b) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %sub = fsub double %a, %b
-; CHECK-NEXT: ret double %sub
-; CHECK-NEXT: }
-
-define internal <4 x float> @SubV4Float(<4 x float> %a, <4 x float> %b) {
-entry:
- %sub = fsub <4 x float> %a, %b
- ret <4 x float> %sub
-}
-
-; CHECK-NEXT: define internal <4 x float> @SubV4Float(<4 x float> %a, <4 x float> %b) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %sub = fsub <4 x float> %a, %b
-; CHECK-NEXT: ret <4 x float> %sub
-; CHECK-NEXT: }
-
-; TODO(kschimpf): mul i8/i16. Needs bitcasts.
-
-define internal i32 @MulI32(i32 %a, i32 %b) {
-entry:
- %mul = mul i32 %b, %a
- ret i32 %mul
-}
-
-; CHECK-NEXT: define internal i32 @MulI32(i32 %a, i32 %b) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %mul = mul i32 %b, %a
-; CHECK-NEXT: ret i32 %mul
-; CHECK-NEXT: }
-
-define internal i64 @MulI64(i64 %a, i64 %b) {
-entry:
- %mul = mul i64 %b, %a
- ret i64 %mul
-}
-
-; CHECK-NEXT: define internal i64 @MulI64(i64 %a, i64 %b) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %mul = mul i64 %b, %a
-; CHECK-NEXT: ret i64 %mul
-; CHECK-NEXT: }
-
-define internal <16 x i8> @MulV16I8(<16 x i8> %a, <16 x i8> %b) {
-entry:
- %mul = mul <16 x i8> %b, %a
- ret <16 x i8> %mul
-}
-
-; CHECK-NEXT: define internal <16 x i8> @MulV16I8(<16 x i8> %a, <16 x i8> %b) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %mul = mul <16 x i8> %b, %a
-; CHECK-NEXT: ret <16 x i8> %mul
-; CHECK-NEXT: }
-
-define internal float @MulFloat(float %a, float %b) {
-entry:
- %mul = fmul float %b, %a
- ret float %mul
-}
-
-; CHECK-NEXT: define internal float @MulFloat(float %a, float %b) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %mul = fmul float %b, %a
-; CHECK-NEXT: ret float %mul
-; CHECK-NEXT: }
-
-define internal double @MulDouble(double %a, double %b) {
-entry:
- %mul = fmul double %b, %a
- ret double %mul
-}
-
-; CHECK-NEXT: define internal double @MulDouble(double %a, double %b) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %mul = fmul double %b, %a
-; CHECK-NEXT: ret double %mul
-; CHECK-NEXT: }
-
-define internal <4 x float> @MulV4Float(<4 x float> %a, <4 x float> %b) {
-entry:
- %mul = fmul <4 x float> %b, %a
- ret <4 x float> %mul
-}
-
-; CHECK-NEXT: define internal <4 x float> @MulV4Float(<4 x float> %a, <4 x float> %b) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %mul = fmul <4 x float> %b, %a
-; CHECK-NEXT: ret <4 x float> %mul
-; CHECK-NEXT: }
-
-; TODO(kschimpf): sdiv i8/i16. Needs bitcasts.
-
-define internal i32 @SdivI32(i32 %a, i32 %b) {
-entry:
- %div = sdiv i32 %a, %b
- ret i32 %div
-}
-
-; CHECK-NEXT: define internal i32 @SdivI32(i32 %a, i32 %b) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %div = sdiv i32 %a, %b
-; CHECK-NEXT: ret i32 %div
-; CHECK-NEXT: }
-
-define internal i64 @SdivI64(i64 %a, i64 %b) {
-entry:
- %div = sdiv i64 %a, %b
- ret i64 %div
-}
-
-; CHECK-NEXT: define internal i64 @SdivI64(i64 %a, i64 %b) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %div = sdiv i64 %a, %b
-; CHECK-NEXT: ret i64 %div
-; CHECK-NEXT: }
-
-define internal <16 x i8> @SdivV16I8(<16 x i8> %a, <16 x i8> %b) {
-entry:
- %div = sdiv <16 x i8> %a, %b
- ret <16 x i8> %div
-}
-
-; CHECK-NEXT: define internal <16 x i8> @SdivV16I8(<16 x i8> %a, <16 x i8> %b) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %div = sdiv <16 x i8> %a, %b
-; CHECK-NEXT: ret <16 x i8> %div
-; CHECK-NEXT: }
-
-define internal <8 x i16> @SdivV8I16(<8 x i16> %a, <8 x i16> %b) {
-entry:
- %div = sdiv <8 x i16> %a, %b
- ret <8 x i16> %div
-}
-
-; CHECK-NEXT: define internal <8 x i16> @SdivV8I16(<8 x i16> %a, <8 x i16> %b) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %div = sdiv <8 x i16> %a, %b
-; CHECK-NEXT: ret <8 x i16> %div
-; CHECK-NEXT: }
-
-define internal <4 x i32> @SdivV4I32(<4 x i32> %a, <4 x i32> %b) {
-entry:
- %div = sdiv <4 x i32> %a, %b
- ret <4 x i32> %div
-}
-
-; CHECK-NEXT: define internal <4 x i32> @SdivV4I32(<4 x i32> %a, <4 x i32> %b) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %div = sdiv <4 x i32> %a, %b
-; CHECK-NEXT: ret <4 x i32> %div
-; CHECK-NEXT: }
-
-; TODO(kschimpf): srem i8/i16. Needs bitcasts.
-
-define internal i32 @SremI32(i32 %a, i32 %b) {
-entry:
- %rem = srem i32 %a, %b
- ret i32 %rem
-}
-
-; CHECK-NEXT: define internal i32 @SremI32(i32 %a, i32 %b) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %rem = srem i32 %a, %b
-; CHECK-NEXT: ret i32 %rem
-; CHECK-NEXT: }
-
-define internal i64 @SremI64(i64 %a, i64 %b) {
-entry:
- %rem = srem i64 %a, %b
- ret i64 %rem
-}
-
-; CHECK-NEXT: define internal i64 @SremI64(i64 %a, i64 %b) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %rem = srem i64 %a, %b
-; CHECK-NEXT: ret i64 %rem
-; CHECK-NEXT: }
-
-define internal <16 x i8> @SremV16I8(<16 x i8> %a, <16 x i8> %b) {
-entry:
- %rem = srem <16 x i8> %a, %b
- ret <16 x i8> %rem
-}
-
-; CHECK-NEXT: define internal <16 x i8> @SremV16I8(<16 x i8> %a, <16 x i8> %b) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %rem = srem <16 x i8> %a, %b
-; CHECK-NEXT: ret <16 x i8> %rem
-; CHECK-NEXT: }
-
-define internal <8 x i16> @SremV8I16(<8 x i16> %a, <8 x i16> %b) {
-entry:
- %rem = srem <8 x i16> %a, %b
- ret <8 x i16> %rem
-}
-
-; CHECK-NEXT: define internal <8 x i16> @SremV8I16(<8 x i16> %a, <8 x i16> %b) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %rem = srem <8 x i16> %a, %b
-; CHECK-NEXT: ret <8 x i16> %rem
-; CHECK-NEXT: }
-
-define internal <4 x i32> @SremV4I32(<4 x i32> %a, <4 x i32> %b) {
-entry:
- %rem = srem <4 x i32> %a, %b
- ret <4 x i32> %rem
-}
-
-; CHECK-NEXT: define internal <4 x i32> @SremV4I32(<4 x i32> %a, <4 x i32> %b) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %rem = srem <4 x i32> %a, %b
-; CHECK-NEXT: ret <4 x i32> %rem
-; CHECK-NEXT: }
-
-; TODO(kschimpf): udiv i8/i16. Needs bitcasts.
-
-define internal i32 @UdivI32(i32 %a, i32 %b) {
-entry:
- %div = udiv i32 %a, %b
- ret i32 %div
-}
-
-; CHECK-NEXT: define internal i32 @UdivI32(i32 %a, i32 %b) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %div = udiv i32 %a, %b
-; CHECK-NEXT: ret i32 %div
-; CHECK-NEXT: }
-
-define internal i64 @UdivI64(i64 %a, i64 %b) {
-entry:
- %div = udiv i64 %a, %b
- ret i64 %div
-}
-
-; CHECK-NEXT: define internal i64 @UdivI64(i64 %a, i64 %b) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %div = udiv i64 %a, %b
-; CHECK-NEXT: ret i64 %div
-; CHECK-NEXT: }
-
-define internal <16 x i8> @UdivV16I8(<16 x i8> %a, <16 x i8> %b) {
-entry:
- %div = udiv <16 x i8> %a, %b
- ret <16 x i8> %div
-}
-
-; CHECK-NEXT: define internal <16 x i8> @UdivV16I8(<16 x i8> %a, <16 x i8> %b) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %div = udiv <16 x i8> %a, %b
-; CHECK-NEXT: ret <16 x i8> %div
-; CHECK-NEXT: }
-
-define internal <8 x i16> @UdivV8I16(<8 x i16> %a, <8 x i16> %b) {
-entry:
- %div = udiv <8 x i16> %a, %b
- ret <8 x i16> %div
-}
-
-; CHECK-NEXT: define internal <8 x i16> @UdivV8I16(<8 x i16> %a, <8 x i16> %b) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %div = udiv <8 x i16> %a, %b
-; CHECK-NEXT: ret <8 x i16> %div
-; CHECK-NEXT: }
-
-define internal <4 x i32> @UdivV4I32(<4 x i32> %a, <4 x i32> %b) {
-entry:
- %div = udiv <4 x i32> %a, %b
- ret <4 x i32> %div
-}
-
-; CHECK-NEXT: define internal <4 x i32> @UdivV4I32(<4 x i32> %a, <4 x i32> %b) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %div = udiv <4 x i32> %a, %b
-; CHECK-NEXT: ret <4 x i32> %div
-; CHECK-NEXT: }
-
-; TODO(kschimpf): urem i8/i16. Needs bitcasts.
-
-define internal i32 @UremI32(i32 %a, i32 %b) {
-entry:
- %rem = urem i32 %a, %b
- ret i32 %rem
-}
-
-; CHECK-NEXT: define internal i32 @UremI32(i32 %a, i32 %b) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %rem = urem i32 %a, %b
-; CHECK-NEXT: ret i32 %rem
-; CHECK-NEXT: }
-
-define internal i64 @UremI64(i64 %a, i64 %b) {
-entry:
- %rem = urem i64 %a, %b
- ret i64 %rem
-}
-
-; CHECK-NEXT: define internal i64 @UremI64(i64 %a, i64 %b) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %rem = urem i64 %a, %b
-; CHECK-NEXT: ret i64 %rem
-; CHECK-NEXT: }
-
-define internal <16 x i8> @UremV16I8(<16 x i8> %a, <16 x i8> %b) {
-entry:
- %rem = urem <16 x i8> %a, %b
- ret <16 x i8> %rem
-}
-
-; CHECK-NEXT: define internal <16 x i8> @UremV16I8(<16 x i8> %a, <16 x i8> %b) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %rem = urem <16 x i8> %a, %b
-; CHECK-NEXT: ret <16 x i8> %rem
-; CHECK-NEXT: }
-
-define internal <8 x i16> @UremV8I16(<8 x i16> %a, <8 x i16> %b) {
-entry:
- %rem = urem <8 x i16> %a, %b
- ret <8 x i16> %rem
-}
-
-; CHECK-NEXT: define internal <8 x i16> @UremV8I16(<8 x i16> %a, <8 x i16> %b) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %rem = urem <8 x i16> %a, %b
-; CHECK-NEXT: ret <8 x i16> %rem
-; CHECK-NEXT: }
-
-define internal <4 x i32> @UremV4I32(<4 x i32> %a, <4 x i32> %b) {
-entry:
- %rem = urem <4 x i32> %a, %b
- ret <4 x i32> %rem
-}
-
-; CHECK-NEXT: define internal <4 x i32> @UremV4I32(<4 x i32> %a, <4 x i32> %b) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %rem = urem <4 x i32> %a, %b
-; CHECK-NEXT: ret <4 x i32> %rem
-; CHECK-NEXT: }
-
-define internal float @fdivFloat(float %a, float %b) {
-entry:
- %div = fdiv float %a, %b
- ret float %div
-}
-
-; CHECK-NEXT: define internal float @fdivFloat(float %a, float %b) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %div = fdiv float %a, %b
-; CHECK-NEXT: ret float %div
-; CHECK-NEXT: }
-
-define internal double @fdivDouble(double %a, double %b) {
-entry:
- %div = fdiv double %a, %b
- ret double %div
-}
-
-; CHECK-NEXT: define internal double @fdivDouble(double %a, double %b) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %div = fdiv double %a, %b
-; CHECK-NEXT: ret double %div
-; CHECK-NEXT: }
-
-define internal <4 x float> @fdivV4Float(<4 x float> %a, <4 x float> %b) {
-entry:
- %div = fdiv <4 x float> %a, %b
- ret <4 x float> %div
-}
-
-; CHECK-NEXT: define internal <4 x float> @fdivV4Float(<4 x float> %a, <4 x float> %b) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %div = fdiv <4 x float> %a, %b
-; CHECK-NEXT: ret <4 x float> %div
-; CHECK-NEXT: }
-
-define internal float @fremFloat(float %a, float %b) {
-entry:
- %rem = frem float %a, %b
- ret float %rem
-}
-
-; CHECK-NEXT: define internal float @fremFloat(float %a, float %b) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %rem = frem float %a, %b
-; CHECK-NEXT: ret float %rem
-; CHECK-NEXT: }
-
-define internal double @fremDouble(double %a, double %b) {
-entry:
- %rem = frem double %a, %b
- ret double %rem
-}
-
-; CHECK-NEXT: define internal double @fremDouble(double %a, double %b) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %rem = frem double %a, %b
-; CHECK-NEXT: ret double %rem
-; CHECK-NEXT: }
-
-define internal <4 x float> @fremV4Float(<4 x float> %a, <4 x float> %b) {
-entry:
- %rem = frem <4 x float> %a, %b
- ret <4 x float> %rem
-}
-
-; CHECK-NEXT: define internal <4 x float> @fremV4Float(<4 x float> %a, <4 x float> %b) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %rem = frem <4 x float> %a, %b
-; CHECK-NEXT: ret <4 x float> %rem
-; CHECK-NEXT: }
-
-; TODO(kschimpf): and i1/i8/i16. Needs bitcasts.
-
-define internal i32 @AndI32(i32 %a, i32 %b) {
-entry:
- %and = and i32 %b, %a
- ret i32 %and
-}
-
-; CHECK-NEXT: define internal i32 @AndI32(i32 %a, i32 %b) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %and = and i32 %b, %a
-; CHECK-NEXT: ret i32 %and
-; CHECK-NEXT: }
-
-define internal i64 @AndI64(i64 %a, i64 %b) {
-entry:
- %and = and i64 %b, %a
- ret i64 %and
-}
-
-; CHECK-NEXT: define internal i64 @AndI64(i64 %a, i64 %b) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %and = and i64 %b, %a
-; CHECK-NEXT: ret i64 %and
-; CHECK-NEXT: }
-
-define internal <16 x i8> @AndV16I8(<16 x i8> %a, <16 x i8> %b) {
-entry:
- %and = and <16 x i8> %b, %a
- ret <16 x i8> %and
-}
-
-; CHECK-NEXT: define internal <16 x i8> @AndV16I8(<16 x i8> %a, <16 x i8> %b) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %and = and <16 x i8> %b, %a
-; CHECK-NEXT: ret <16 x i8> %and
-; CHECK-NEXT: }
-
-define internal <8 x i16> @AndV8I16(<8 x i16> %a, <8 x i16> %b) {
-entry:
- %and = and <8 x i16> %b, %a
- ret <8 x i16> %and
-}
-
-; CHECK-NEXT: define internal <8 x i16> @AndV8I16(<8 x i16> %a, <8 x i16> %b) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %and = and <8 x i16> %b, %a
-; CHECK-NEXT: ret <8 x i16> %and
-; CHECK-NEXT: }
-
-define internal <4 x i32> @AndV4I32(<4 x i32> %a, <4 x i32> %b) {
-entry:
- %and = and <4 x i32> %b, %a
- ret <4 x i32> %and
-}
-
-; CHECK-NEXT: define internal <4 x i32> @AndV4I32(<4 x i32> %a, <4 x i32> %b) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %and = and <4 x i32> %b, %a
-; CHECK-NEXT: ret <4 x i32> %and
-; CHECK-NEXT: }
-
-; TODO(kschimpf): or i1/i8/i16. Needs bitcasts.
-
-define internal i32 @OrI32(i32 %a, i32 %b) {
-entry:
- %or = or i32 %b, %a
- ret i32 %or
-}
-
-; CHECK-NEXT: define internal i32 @OrI32(i32 %a, i32 %b) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %or = or i32 %b, %a
-; CHECK-NEXT: ret i32 %or
-; CHECK-NEXT: }
-
-define internal i64 @OrI64(i64 %a, i64 %b) {
-entry:
- %or = or i64 %b, %a
- ret i64 %or
-}
-
-; CHECK-NEXT: define internal i64 @OrI64(i64 %a, i64 %b) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %or = or i64 %b, %a
-; CHECK-NEXT: ret i64 %or
-; CHECK-NEXT: }
-
-define internal <16 x i8> @OrV16I8(<16 x i8> %a, <16 x i8> %b) {
-entry:
- %or = or <16 x i8> %b, %a
- ret <16 x i8> %or
-}
-
-; CHECK-NEXT: define internal <16 x i8> @OrV16I8(<16 x i8> %a, <16 x i8> %b) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %or = or <16 x i8> %b, %a
-; CHECK-NEXT: ret <16 x i8> %or
-; CHECK-NEXT: }
-
-define internal <8 x i16> @OrV8I16(<8 x i16> %a, <8 x i16> %b) {
-entry:
- %or = or <8 x i16> %b, %a
- ret <8 x i16> %or
-}
-
-; CHECK-NEXT: define internal <8 x i16> @OrV8I16(<8 x i16> %a, <8 x i16> %b) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %or = or <8 x i16> %b, %a
-; CHECK-NEXT: ret <8 x i16> %or
-; CHECK-NEXT: }
-
-define internal <4 x i32> @OrV4I32(<4 x i32> %a, <4 x i32> %b) {
-entry:
- %or = or <4 x i32> %b, %a
- ret <4 x i32> %or
-}
-
-; CHECK-NEXT: define internal <4 x i32> @OrV4I32(<4 x i32> %a, <4 x i32> %b) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %or = or <4 x i32> %b, %a
-; CHECK-NEXT: ret <4 x i32> %or
-; CHECK-NEXT: }
-
-; TODO(kschimpf): xor i1/i8/i16. Needs bitcasts.
-
-define internal i32 @XorI32(i32 %a, i32 %b) {
-entry:
- %xor = xor i32 %b, %a
- ret i32 %xor
-}
-
-; CHECK-NEXT: define internal i32 @XorI32(i32 %a, i32 %b) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %xor = xor i32 %b, %a
-; CHECK-NEXT: ret i32 %xor
-; CHECK-NEXT: }
-
-define internal i64 @XorI64(i64 %a, i64 %b) {
-entry:
- %xor = xor i64 %b, %a
- ret i64 %xor
-}
-
-; CHECK-NEXT: define internal i64 @XorI64(i64 %a, i64 %b) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %xor = xor i64 %b, %a
-; CHECK-NEXT: ret i64 %xor
-; CHECK-NEXT: }
-
-define internal <16 x i8> @XorV16I8(<16 x i8> %a, <16 x i8> %b) {
-entry:
- %xor = xor <16 x i8> %b, %a
- ret <16 x i8> %xor
-}
-
-; CHECK-NEXT: define internal <16 x i8> @XorV16I8(<16 x i8> %a, <16 x i8> %b) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %xor = xor <16 x i8> %b, %a
-; CHECK-NEXT: ret <16 x i8> %xor
-; CHECK-NEXT: }
-
-define internal <8 x i16> @XorV8I16(<8 x i16> %a, <8 x i16> %b) {
-entry:
- %xor = xor <8 x i16> %b, %a
- ret <8 x i16> %xor
-}
-
-; CHECK-NEXT: define internal <8 x i16> @XorV8I16(<8 x i16> %a, <8 x i16> %b) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %xor = xor <8 x i16> %b, %a
-; CHECK-NEXT: ret <8 x i16> %xor
-; CHECK-NEXT: }
-
-define internal <4 x i32> @XorV4I32(<4 x i32> %a, <4 x i32> %b) {
-entry:
- %xor = xor <4 x i32> %b, %a
- ret <4 x i32> %xor
-}
-
-; CHECK-NEXT: define internal <4 x i32> @XorV4I32(<4 x i32> %a, <4 x i32> %b) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %xor = xor <4 x i32> %b, %a
-; CHECK-NEXT: ret <4 x i32> %xor
-; CHECK-NEXT: }
-
-; TODO(kschimpf): shl i8/i16. Needs bitcasts.
-
-define internal i32 @ShlI32(i32 %a, i32 %b) {
-entry:
- %shl = shl i32 %b, %a
- ret i32 %shl
-}
-
-; CHECK-NEXT: define internal i32 @ShlI32(i32 %a, i32 %b) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %shl = shl i32 %b, %a
-; CHECK-NEXT: ret i32 %shl
-; CHECK-NEXT: }
-
-define internal i64 @ShlI64(i64 %a, i64 %b) {
-entry:
- %shl = shl i64 %b, %a
- ret i64 %shl
-}
-
-; CHECK-NEXT: define internal i64 @ShlI64(i64 %a, i64 %b) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %shl = shl i64 %b, %a
-; CHECK-NEXT: ret i64 %shl
-; CHECK-NEXT: }
-
-define internal <16 x i8> @ShlV16I8(<16 x i8> %a, <16 x i8> %b) {
-entry:
- %shl = shl <16 x i8> %b, %a
- ret <16 x i8> %shl
-}
-
-; CHECK-NEXT: define internal <16 x i8> @ShlV16I8(<16 x i8> %a, <16 x i8> %b) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %shl = shl <16 x i8> %b, %a
-; CHECK-NEXT: ret <16 x i8> %shl
-; CHECK-NEXT: }
-
-define internal <8 x i16> @ShlV8I16(<8 x i16> %a, <8 x i16> %b) {
-entry:
- %shl = shl <8 x i16> %b, %a
- ret <8 x i16> %shl
-}
-
-; CHECK-NEXT: define internal <8 x i16> @ShlV8I16(<8 x i16> %a, <8 x i16> %b) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %shl = shl <8 x i16> %b, %a
-; CHECK-NEXT: ret <8 x i16> %shl
-; CHECK-NEXT: }
-
-define internal <4 x i32> @ShlV4I32(<4 x i32> %a, <4 x i32> %b) {
-entry:
- %shl = shl <4 x i32> %b, %a
- ret <4 x i32> %shl
-}
-
-; CHECK-NEXT: define internal <4 x i32> @ShlV4I32(<4 x i32> %a, <4 x i32> %b) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %shl = shl <4 x i32> %b, %a
-; CHECK-NEXT: ret <4 x i32> %shl
-; CHECK-NEXT: }
-
-; TODO(kschimpf): ashr i8/i16. Needs bitcasts.
-
-define internal i32 @ashrI32(i32 %a, i32 %b) {
-entry:
- %ashr = ashr i32 %b, %a
- ret i32 %ashr
-}
-
-; CHECK-NEXT: define internal i32 @ashrI32(i32 %a, i32 %b) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %ashr = ashr i32 %b, %a
-; CHECK-NEXT: ret i32 %ashr
-; CHECK-NEXT: }
-
-define internal i64 @AshrI64(i64 %a, i64 %b) {
-entry:
- %ashr = ashr i64 %b, %a
- ret i64 %ashr
-}
-
-; CHECK-NEXT: define internal i64 @AshrI64(i64 %a, i64 %b) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %ashr = ashr i64 %b, %a
-; CHECK-NEXT: ret i64 %ashr
-; CHECK-NEXT: }
-
-define internal <16 x i8> @AshrV16I8(<16 x i8> %a, <16 x i8> %b) {
-entry:
- %ashr = ashr <16 x i8> %b, %a
- ret <16 x i8> %ashr
-}
-
-; CHECK-NEXT: define internal <16 x i8> @AshrV16I8(<16 x i8> %a, <16 x i8> %b) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %ashr = ashr <16 x i8> %b, %a
-; CHECK-NEXT: ret <16 x i8> %ashr
-; CHECK-NEXT: }
-
-define internal <8 x i16> @AshrV8I16(<8 x i16> %a, <8 x i16> %b) {
-entry:
- %ashr = ashr <8 x i16> %b, %a
- ret <8 x i16> %ashr
-}
-
-; CHECK-NEXT: define internal <8 x i16> @AshrV8I16(<8 x i16> %a, <8 x i16> %b) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %ashr = ashr <8 x i16> %b, %a
-; CHECK-NEXT: ret <8 x i16> %ashr
-; CHECK-NEXT: }
-
-define internal <4 x i32> @AshrV4I32(<4 x i32> %a, <4 x i32> %b) {
-entry:
- %ashr = ashr <4 x i32> %b, %a
- ret <4 x i32> %ashr
-}
-
-; CHECK-NEXT: define internal <4 x i32> @AshrV4I32(<4 x i32> %a, <4 x i32> %b) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %ashr = ashr <4 x i32> %b, %a
-; CHECK-NEXT: ret <4 x i32> %ashr
-; CHECK-NEXT: }
-
-; TODO(kschimpf): lshr i8/i16. Needs bitcasts.
-
-define internal i32 @lshrI32(i32 %a, i32 %b) {
-entry:
- %lshr = lshr i32 %b, %a
- ret i32 %lshr
-}
-
-; CHECK-NEXT: define internal i32 @lshrI32(i32 %a, i32 %b) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %lshr = lshr i32 %b, %a
-; CHECK-NEXT: ret i32 %lshr
-; CHECK-NEXT: }
-
-define internal i64 @LshrI64(i64 %a, i64 %b) {
-entry:
- %lshr = lshr i64 %b, %a
- ret i64 %lshr
-}
-
-; CHECK-NEXT: define internal i64 @LshrI64(i64 %a, i64 %b) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %lshr = lshr i64 %b, %a
-; CHECK-NEXT: ret i64 %lshr
-; CHECK-NEXT: }
-
-define internal <16 x i8> @LshrV16I8(<16 x i8> %a, <16 x i8> %b) {
-entry:
- %lshr = lshr <16 x i8> %b, %a
- ret <16 x i8> %lshr
-}
-
-; CHECK-NEXT: define internal <16 x i8> @LshrV16I8(<16 x i8> %a, <16 x i8> %b) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %lshr = lshr <16 x i8> %b, %a
-; CHECK-NEXT: ret <16 x i8> %lshr
-; CHECK-NEXT: }
-
-define internal <8 x i16> @LshrV8I16(<8 x i16> %a, <8 x i16> %b) {
-entry:
- %lshr = lshr <8 x i16> %b, %a
- ret <8 x i16> %lshr
-}
-
-; CHECK-NEXT: define internal <8 x i16> @LshrV8I16(<8 x i16> %a, <8 x i16> %b) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %lshr = lshr <8 x i16> %b, %a
-; CHECK-NEXT: ret <8 x i16> %lshr
-; CHECK-NEXT: }
-
-define internal <4 x i32> @LshrV4I32(<4 x i32> %a, <4 x i32> %b) {
-entry:
- %lshr = lshr <4 x i32> %b, %a
- ret <4 x i32> %lshr
-}
-
-; CHECK-NEXT: define internal <4 x i32> @LshrV4I32(<4 x i32> %a, <4 x i32> %b) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %lshr = lshr <4 x i32> %b, %a
-; CHECK-NEXT: ret <4 x i32> %lshr
-; CHECK-NEXT: }
-
-; NOIR: Total across all functions
diff --git a/third_party/subzero/tests_lit/reader_tests/branch.ll b/third_party/subzero/tests_lit/reader_tests/branch.ll
deleted file mode 100644
index 5613fdb..0000000
--- a/third_party/subzero/tests_lit/reader_tests/branch.ll
+++ /dev/null
@@ -1,49 +0,0 @@
-; Tests if we handle a branch instructions.
-
-; RUN: %p2i -i %s --insts | FileCheck %s
-; RUN: %p2i -i %s --args -notranslate -timing | \
-; RUN: FileCheck --check-prefix=NOIR %s
-
-define internal void @SimpleBranch() {
-entry:
- br label %b3
-b1:
- br label %b2
-b2:
- ret void
-b3:
- br label %b1
-}
-
-; CHECK: define internal void @SimpleBranch() {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: br label %b3
-; CHECK-NEXT: b1:
-; CHECK-NEXT: br label %b2
-; CHECK-NEXT: b2:
-; CHECK-NEXT: ret void
-; CHECK-NEXT: b3:
-; CHECK-NEXT: br label %b1
-; CHECK-NEXT: }
-
-define internal void @CondBranch(i32 %p) {
-entry:
- %test = trunc i32 %p to i1
- br i1 %test, label %b1, label %b2
-b1:
- ret void
-b2:
- br i1 %test, label %b2, label %b1
-}
-
-; CHECK-NEXT: define internal void @CondBranch(i32 %p) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %test = trunc i32 %p to i1
-; CHECK-NEXT: br i1 %test, label %b1, label %b2
-; CHECK-NEXT: b1:
-; CHECK-NEXT: ret void
-; CHECK-NEXT: b2:
-; CHECK-NEXT: br i1 %test, label %b2, label %b1
-; CHECK-NEXT: }
-
-; NOIR: Total across all functions
diff --git a/third_party/subzero/tests_lit/reader_tests/call-indirect.ll b/third_party/subzero/tests_lit/reader_tests/call-indirect.ll
deleted file mode 100644
index d3d7e1d..0000000
--- a/third_party/subzero/tests_lit/reader_tests/call-indirect.ll
+++ /dev/null
@@ -1,32 +0,0 @@
-; Test parsing indirect calls in Subzero.
-
-; RUN: %p2i -i %s --insts | FileCheck %s
-; RUN: %p2i -i %s --args -notranslate -timing | FileCheck --check-prefix=NOIR %s
-
-define internal void @CallIndirectVoid(i32 %f_addr) {
-entry:
- %f = inttoptr i32 %f_addr to void ()*
- call void %f()
- ret void
-}
-
-; CHECK: define internal void @CallIndirectVoid(i32 %f_addr) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: call void %f_addr()
-; CHECK-NEXT: ret void
-; CHECK-NEXT: }
-
-define internal i32 @CallIndirectI32(i32 %f_addr) {
-entry:
- %f = inttoptr i32 %f_addr to i32(i64, i32)*
- %r = call i32 %f(i64 1, i32 %f_addr)
- ret i32 %r
-}
-
-; CHECK-NEXT: define internal i32 @CallIndirectI32(i32 %f_addr) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %r = call i32 %f_addr(i64 1, i32 %f_addr)
-; CHECK-NEXT: ret i32 %r
-; CHECK-NEXT: }
-
-; NOIR: Total across all functions
diff --git a/third_party/subzero/tests_lit/reader_tests/call.ll b/third_party/subzero/tests_lit/reader_tests/call.ll
deleted file mode 100644
index 59af96c..0000000
--- a/third_party/subzero/tests_lit/reader_tests/call.ll
+++ /dev/null
@@ -1,113 +0,0 @@
-; Test handling of call instructions.
-
-; RUN: %p2i -i %s --insts --args -allow-externally-defined-symbols \
-; RUN: | FileCheck %s
-; RUN: %p2i -i %s --args -notranslate -timing \
-; RUN: -allow-externally-defined-symbols | \
-; RUN: FileCheck --check-prefix=NOIR %s
-
-define internal i32 @fib(i32 %n) {
-entry:
- %cmp = icmp slt i32 %n, 2
- br i1 %cmp, label %return, label %if.end
-
-if.end: ; preds = %entry
- %sub = add i32 %n, -1
- %call = tail call i32 @fib(i32 %sub)
- %sub1 = add i32 %n, -2
- %call2 = tail call i32 @fib(i32 %sub1)
- %add = add i32 %call2, %call
- ret i32 %add
-
-return: ; preds = %entry
- ret i32 %n
-}
-
-; CHECK: define internal i32 @fib(i32 %n) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %cmp = icmp slt i32 %n, 2
-; CHECK-NEXT: br i1 %cmp, label %return, label %if.end
-; CHECK-NEXT: if.end:
-; CHECK-NEXT: %sub = add i32 %n, -1
-; CHECK-NEXT: %call = call i32 @fib(i32 %sub)
-; CHECK-NEXT: %sub1 = add i32 %n, -2
-; CHECK-NEXT: %call2 = call i32 @fib(i32 %sub1)
-; CHECK-NEXT: %add = add i32 %call2, %call
-; CHECK-NEXT: ret i32 %add
-; CHECK-NEXT: return:
-; CHECK-NEXT: ret i32 %n
-; CHECK-NEXT: }
-
-define internal i32 @fact(i32 %n) {
-entry:
- %cmp = icmp slt i32 %n, 2
- br i1 %cmp, label %return, label %if.end
-
-if.end: ; preds = %entry
- %sub = add i32 %n, -1
- %call = tail call i32 @fact(i32 %sub)
- %mul = mul i32 %call, %n
- ret i32 %mul
-
-return: ; preds = %entry
- ret i32 %n
-}
-
-; CHECK-NEXT: define internal i32 @fact(i32 %n) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %cmp = icmp slt i32 %n, 2
-; CHECK-NEXT: br i1 %cmp, label %return, label %if.end
-; CHECK-NEXT: if.end:
-; CHECK-NEXT: %sub = add i32 %n, -1
-; CHECK-NEXT: %call = call i32 @fact(i32 %sub)
-; CHECK-NEXT: %mul = mul i32 %call, %n
-; CHECK-NEXT: ret i32 %mul
-; CHECK-NEXT: return:
-; CHECK-NEXT: ret i32 %n
-; CHECK-NEXT: }
-
-define internal i32 @redirect(i32 %n) {
-entry:
- %call = tail call i32 @redirect_target(i32 %n)
- ret i32 %call
-}
-
-; CHECK-NEXT: define internal i32 @redirect(i32 %n) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %call = call i32 @redirect_target(i32 %n)
-; CHECK-NEXT: ret i32 %call
-; CHECK-NEXT: }
-
-declare i32 @redirect_target(i32)
-
-define internal void @call_void(i32 %n) {
-entry:
- %cmp2 = icmp sgt i32 %n, 0
- br i1 %cmp2, label %if.then, label %if.end
-
-if.then: ; preds = %entry, %if.then
- %n.tr3 = phi i32 [ %call.i, %if.then ], [ %n, %entry ]
- %sub = add i32 %n.tr3, -1
- %call.i = tail call i32 @redirect_target(i32 %sub)
- %cmp = icmp sgt i32 %call.i, 0
- br i1 %cmp, label %if.then, label %if.end
-
-if.end: ; preds = %if.then, %entry
- ret void
-}
-
-; CHECK-NEXT: define internal void @call_void(i32 %n) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %cmp2 = icmp sgt i32 %n, 0
-; CHECK-NEXT: br i1 %cmp2, label %if.then, label %if.end
-; CHECK-NEXT: if.then:
-; CHECK-NEXT: %n.tr3 = phi i32 [ %call.i, %if.then ], [ %n, %entry ]
-; CHECK-NEXT: %sub = add i32 %n.tr3, -1
-; CHECK-NEXT: %call.i = call i32 @redirect_target(i32 %sub)
-; CHECK-NEXT: %cmp = icmp sgt i32 %call.i, 0
-; CHECK-NEXT: br i1 %cmp, label %if.then, label %if.end
-; CHECK-NEXT: if.end:
-; CHECK-NEXT: ret void
-; CHECK-NEXT: }
-
-; NOIR: Total across all functions
diff --git a/third_party/subzero/tests_lit/reader_tests/casts.ll b/third_party/subzero/tests_lit/reader_tests/casts.ll
deleted file mode 100644
index 901fa9a..0000000
--- a/third_party/subzero/tests_lit/reader_tests/casts.ll
+++ /dev/null
@@ -1,538 +0,0 @@
-; Tests if we can read cast operations.
-
-; RUN: %p2i -i %s --insts --no-local-syms | FileCheck %s
-; RUN: %p2i -i %s --args -notranslate -timing | \
-; RUN: FileCheck --check-prefix=NOIR %s
-
-; TODO(kschimpf) Find way to test pointer conversions (since they in general
-; get removed by pnacl-freeze).
-
-define internal i32 @TruncI64(i64 %v) {
- %v1 = trunc i64 %v to i1
- %v8 = trunc i64 %v to i8
- %v16 = trunc i64 %v to i16
- %v32 = trunc i64 %v to i32
- ret i32 %v32
-}
-
-; CHECK: define internal i32 @TruncI64(i64 %__0) {
-; CHECK-NEXT: __0:
-; CHECK-NEXT: %__1 = trunc i64 %__0 to i1
-; CHECK-NEXT: %__2 = trunc i64 %__0 to i8
-; CHECK-NEXT: %__3 = trunc i64 %__0 to i16
-; CHECK-NEXT: %__4 = trunc i64 %__0 to i32
-; CHECK-NEXT: ret i32 %__4
-; CHECK-NEXT: }
-
-define internal void @TruncI32(i32 %v) {
- %v1 = trunc i32 %v to i1
- %v8 = trunc i32 %v to i8
- %v16 = trunc i32 %v to i16
- ret void
-}
-
-; CHECK-NEXT: define internal void @TruncI32(i32 %__0) {
-; CHECK-NEXT: __0:
-; CHECK-NEXT: %__1 = trunc i32 %__0 to i1
-; CHECK-NEXT: %__2 = trunc i32 %__0 to i8
-; CHECK-NEXT: %__3 = trunc i32 %__0 to i16
-; CHECK-NEXT: ret void
-; CHECK-NEXT: }
-
-define internal void @TruncI16(i32 %p) {
- %v = trunc i32 %p to i16
- %v1 = trunc i16 %v to i1
- %v8 = trunc i16 %v to i8
- ret void
-}
-
-; CHECK-NEXT: define internal void @TruncI16(i32 %__0) {
-; CHECK-NEXT: __0:
-; CHECK-NEXT: %__1 = trunc i32 %__0 to i16
-; CHECK-NEXT: %__2 = trunc i16 %__1 to i1
-; CHECK-NEXT: %__3 = trunc i16 %__1 to i8
-; CHECK-NEXT: ret void
-; CHECK-NEXT: }
-
-define internal void @TruncI8(i32 %p) {
- %v = trunc i32 %p to i8
- %v1 = trunc i8 %v to i1
- ret void
-}
-
-; CHECK-NEXT: define internal void @TruncI8(i32 %__0) {
-; CHECK-NEXT: __0:
-; CHECK-NEXT: %__1 = trunc i32 %__0 to i8
-; CHECK-NEXT: %__2 = trunc i8 %__1 to i1
-; CHECK-NEXT: ret void
-; CHECK-NEXT: }
-
-define internal i64 @ZextI1(i32 %p) {
- %v = trunc i32 %p to i1
- %v8 = zext i1 %v to i8
- %v16 = zext i1 %v to i16
- %v32 = zext i1 %v to i32
- %v64 = zext i1 %v to i64
- ret i64 %v64
-}
-
-; CHECK-NEXT: define internal i64 @ZextI1(i32 %__0) {
-; CHECK-NEXT: __0:
-; CHECK-NEXT: %__1 = trunc i32 %__0 to i1
-; CHECK-NEXT: %__2 = zext i1 %__1 to i8
-; CHECK-NEXT: %__3 = zext i1 %__1 to i16
-; CHECK-NEXT: %__4 = zext i1 %__1 to i32
-; CHECK-NEXT: %__5 = zext i1 %__1 to i64
-; CHECK-NEXT: ret i64 %__5
-; CHECK-NEXT: }
-
-define internal i32 @ZextI8(i32 %p) {
- %v = trunc i32 %p to i8
- %v16 = zext i8 %v to i16
- %v32 = zext i8 %v to i32
- %v64 = zext i8 %v to i64
- ret i32 %v32
-}
-
-; CHECK-NEXT: define internal i32 @ZextI8(i32 %__0) {
-; CHECK-NEXT: __0:
-; CHECK-NEXT: %__1 = trunc i32 %__0 to i8
-; CHECK-NEXT: %__2 = zext i8 %__1 to i16
-; CHECK-NEXT: %__3 = zext i8 %__1 to i32
-; CHECK-NEXT: %__4 = zext i8 %__1 to i64
-; CHECK-NEXT: ret i32 %__3
-; CHECK-NEXT: }
-
-define internal i64 @ZextI16(i32 %p) {
- %v = trunc i32 %p to i16
- %v32 = zext i16 %v to i32
- %v64 = zext i16 %v to i64
- ret i64 %v64
-}
-
-; CHECK-NEXT: define internal i64 @ZextI16(i32 %__0) {
-; CHECK-NEXT: __0:
-; CHECK-NEXT: %__1 = trunc i32 %__0 to i16
-; CHECK-NEXT: %__2 = zext i16 %__1 to i32
-; CHECK-NEXT: %__3 = zext i16 %__1 to i64
-; CHECK-NEXT: ret i64 %__3
-; CHECK-NEXT: }
-
-define internal i64 @Zexti32(i32 %v) {
- %v64 = zext i32 %v to i64
- ret i64 %v64
-}
-
-; CHECK-NEXT: define internal i64 @Zexti32(i32 %__0) {
-; CHECK-NEXT: __0:
-; CHECK-NEXT: %__1 = zext i32 %__0 to i64
-; CHECK-NEXT: ret i64 %__1
-; CHECK-NEXT: }
-
-define internal i32 @SextI1(i32 %p) {
- %v = trunc i32 %p to i1
- %v8 = sext i1 %v to i8
- %v16 = sext i1 %v to i16
- %v32 = sext i1 %v to i32
- %v64 = sext i1 %v to i64
- ret i32 %v32
-}
-
-; CHECK-NEXT: define internal i32 @SextI1(i32 %__0) {
-; CHECK-NEXT: __0:
-; CHECK-NEXT: %__1 = trunc i32 %__0 to i1
-; CHECK-NEXT: %__2 = sext i1 %__1 to i8
-; CHECK-NEXT: %__3 = sext i1 %__1 to i16
-; CHECK-NEXT: %__4 = sext i1 %__1 to i32
-; CHECK-NEXT: %__5 = sext i1 %__1 to i64
-; CHECK-NEXT: ret i32 %__4
-; CHECK-NEXT: }
-
-define internal i64 @SextI8(i32 %p) {
- %v = trunc i32 %p to i8
- %v16 = sext i8 %v to i16
- %v32 = sext i8 %v to i32
- %v64 = sext i8 %v to i64
- ret i64 %v64
-}
-
-; CHECK-NEXT: define internal i64 @SextI8(i32 %__0) {
-; CHECK-NEXT: __0:
-; CHECK-NEXT: %__1 = trunc i32 %__0 to i8
-; CHECK-NEXT: %__2 = sext i8 %__1 to i16
-; CHECK-NEXT: %__3 = sext i8 %__1 to i32
-; CHECK-NEXT: %__4 = sext i8 %__1 to i64
-; CHECK-NEXT: ret i64 %__4
-; CHECK-NEXT: }
-
-define internal i32 @SextI16(i32 %p) {
- %v = trunc i32 %p to i16
- %v32 = sext i16 %v to i32
- %v64 = sext i16 %v to i64
- ret i32 %v32
-}
-
-; CHECK-NEXT: define internal i32 @SextI16(i32 %__0) {
-; CHECK-NEXT: __0:
-; CHECK-NEXT: %__1 = trunc i32 %__0 to i16
-; CHECK-NEXT: %__2 = sext i16 %__1 to i32
-; CHECK-NEXT: %__3 = sext i16 %__1 to i64
-; CHECK-NEXT: ret i32 %__2
-; CHECK-NEXT: }
-
-define internal i64 @Sexti32(i32 %v) {
- %v64 = sext i32 %v to i64
- ret i64 %v64
-}
-
-; CHECK-NEXT: define internal i64 @Sexti32(i32 %__0) {
-; CHECK-NEXT: __0:
-; CHECK-NEXT: %__1 = sext i32 %__0 to i64
-; CHECK-NEXT: ret i64 %__1
-; CHECK-NEXT: }
-
-define internal float @Fptrunc(double %v) {
- %vfloat = fptrunc double %v to float
- ret float %vfloat
-}
-
-; CHECK-NEXT: define internal float @Fptrunc(double %__0) {
-; CHECK-NEXT: __0:
-; CHECK-NEXT: %__1 = fptrunc double %__0 to float
-; CHECK-NEXT: ret float %__1
-; CHECK-NEXT: }
-
-define internal double @Fpext(float %v) {
- %vdouble = fpext float %v to double
- ret double %vdouble
-}
-
-; CHECK-NEXT: define internal double @Fpext(float %__0) {
-; CHECK-NEXT: __0:
-; CHECK-NEXT: %__1 = fpext float %__0 to double
-; CHECK-NEXT: ret double %__1
-; CHECK-NEXT: }
-
-define internal i32 @FptouiFloat(float %v) {
- %v1 = fptoui float %v to i1
- %v8 = fptoui float %v to i8
- %v16 = fptoui float %v to i16
- %v32 = fptoui float %v to i32
- %v64 = fptoui float %v to i64
- ret i32 %v32
-}
-
-; CHECK-NEXT: define internal i32 @FptouiFloat(float %__0) {
-; CHECK-NEXT: __0:
-; CHECK-NEXT: %__1 = fptoui float %__0 to i1
-; CHECK-NEXT: %__2 = fptoui float %__0 to i8
-; CHECK-NEXT: %__3 = fptoui float %__0 to i16
-; CHECK-NEXT: %__4 = fptoui float %__0 to i32
-; CHECK-NEXT: %__5 = fptoui float %__0 to i64
-; CHECK-NEXT: ret i32 %__4
-; CHECK-NEXT: }
-
-define internal i32 @FptouiDouble(double %v) {
- %v1 = fptoui double %v to i1
- %v8 = fptoui double %v to i8
- %v16 = fptoui double %v to i16
- %v32 = fptoui double %v to i32
- %v64 = fptoui double %v to i64
- ret i32 %v32
-}
-
-; CHECK-NEXT: define internal i32 @FptouiDouble(double %__0) {
-; CHECK-NEXT: __0:
-; CHECK-NEXT: %__1 = fptoui double %__0 to i1
-; CHECK-NEXT: %__2 = fptoui double %__0 to i8
-; CHECK-NEXT: %__3 = fptoui double %__0 to i16
-; CHECK-NEXT: %__4 = fptoui double %__0 to i32
-; CHECK-NEXT: %__5 = fptoui double %__0 to i64
-; CHECK-NEXT: ret i32 %__4
-; CHECK-NEXT: }
-
-define internal i32 @FptosiFloat(float %v) {
- %v1 = fptosi float %v to i1
- %v8 = fptosi float %v to i8
- %v16 = fptosi float %v to i16
- %v32 = fptosi float %v to i32
- %v64 = fptosi float %v to i64
- ret i32 %v32
-}
-
-; CHECK-NEXT: define internal i32 @FptosiFloat(float %__0) {
-; CHECK-NEXT: __0:
-; CHECK-NEXT: %__1 = fptosi float %__0 to i1
-; CHECK-NEXT: %__2 = fptosi float %__0 to i8
-; CHECK-NEXT: %__3 = fptosi float %__0 to i16
-; CHECK-NEXT: %__4 = fptosi float %__0 to i32
-; CHECK-NEXT: %__5 = fptosi float %__0 to i64
-; CHECK-NEXT: ret i32 %__4
-; CHECK-NEXT: }
-
-define internal i32 @FptosiDouble(double %v) {
- %v1 = fptosi double %v to i1
- %v8 = fptosi double %v to i8
- %v16 = fptosi double %v to i16
- %v32 = fptosi double %v to i32
- %v64 = fptosi double %v to i64
- ret i32 %v32
-}
-
-; CHECK-NEXT: define internal i32 @FptosiDouble(double %__0) {
-; CHECK-NEXT: __0:
-; CHECK-NEXT: %__1 = fptosi double %__0 to i1
-; CHECK-NEXT: %__2 = fptosi double %__0 to i8
-; CHECK-NEXT: %__3 = fptosi double %__0 to i16
-; CHECK-NEXT: %__4 = fptosi double %__0 to i32
-; CHECK-NEXT: %__5 = fptosi double %__0 to i64
-; CHECK-NEXT: ret i32 %__4
-; CHECK-NEXT: }
-
-define internal float @UitofpI1(i32 %p) {
- %v = trunc i32 %p to i1
- %vfloat = uitofp i1 %v to float
- %vdouble = uitofp i1 %v to double
- ret float %vfloat
-}
-
-; CHECK-NEXT: define internal float @UitofpI1(i32 %__0) {
-; CHECK-NEXT: __0:
-; CHECK-NEXT: %__1 = trunc i32 %__0 to i1
-; CHECK-NEXT: %__2 = uitofp i1 %__1 to float
-; CHECK-NEXT: %__3 = uitofp i1 %__1 to double
-; CHECK-NEXT: ret float %__2
-; CHECK-NEXT: }
-
-define internal float @UitofpI8(i32 %p) {
- %v = trunc i32 %p to i8
- %vfloat = uitofp i8 %v to float
- %vdouble = uitofp i8 %v to double
- ret float %vfloat
-}
-
-; CHECK-NEXT: define internal float @UitofpI8(i32 %__0) {
-; CHECK-NEXT: __0:
-; CHECK-NEXT: %__1 = trunc i32 %__0 to i8
-; CHECK-NEXT: %__2 = uitofp i8 %__1 to float
-; CHECK-NEXT: %__3 = uitofp i8 %__1 to double
-; CHECK-NEXT: ret float %__2
-; CHECK-NEXT: }
-
-define internal float @UitofpI16(i32 %p) {
- %v = trunc i32 %p to i16
- %vfloat = uitofp i16 %v to float
- %vdouble = uitofp i16 %v to double
- ret float %vfloat
-}
-
-; CHECK-NEXT: define internal float @UitofpI16(i32 %__0) {
-; CHECK-NEXT: __0:
-; CHECK-NEXT: %__1 = trunc i32 %__0 to i16
-; CHECK-NEXT: %__2 = uitofp i16 %__1 to float
-; CHECK-NEXT: %__3 = uitofp i16 %__1 to double
-; CHECK-NEXT: ret float %__2
-; CHECK-NEXT: }
-
-define internal float @UitofpI32(i32 %v) {
- %vfloat = uitofp i32 %v to float
- %vdouble = uitofp i32 %v to double
- ret float %vfloat
-}
-
-; CHECK-NEXT: define internal float @UitofpI32(i32 %__0) {
-; CHECK-NEXT: __0:
-; CHECK-NEXT: %__1 = uitofp i32 %__0 to float
-; CHECK-NEXT: %__2 = uitofp i32 %__0 to double
-; CHECK-NEXT: ret float %__1
-; CHECK-NEXT: }
-
-define internal float @UitofpI64(i64 %v) {
- %vfloat = uitofp i64 %v to float
- %vdouble = uitofp i64 %v to double
- ret float %vfloat
-}
-
-; CHECK-NEXT: define internal float @UitofpI64(i64 %__0) {
-; CHECK-NEXT: __0:
-; CHECK-NEXT: %__1 = uitofp i64 %__0 to float
-; CHECK-NEXT: %__2 = uitofp i64 %__0 to double
-; CHECK-NEXT: ret float %__1
-; CHECK-NEXT: }
-
-define internal float @SitofpI1(i32 %p) {
- %v = trunc i32 %p to i1
- %vfloat = sitofp i1 %v to float
- %vdouble = sitofp i1 %v to double
- ret float %vfloat
-}
-
-; CHECK-NEXT: define internal float @SitofpI1(i32 %__0) {
-; CHECK-NEXT: __0:
-; CHECK-NEXT: %__1 = trunc i32 %__0 to i1
-; CHECK-NEXT: %__2 = sitofp i1 %__1 to float
-; CHECK-NEXT: %__3 = sitofp i1 %__1 to double
-; CHECK-NEXT: ret float %__2
-; CHECK-NEXT: }
-
-define internal float @SitofpI8(i32 %p) {
- %v = trunc i32 %p to i8
- %vfloat = sitofp i8 %v to float
- %vdouble = sitofp i8 %v to double
- ret float %vfloat
-}
-
-; CHECK-NEXT: define internal float @SitofpI8(i32 %__0) {
-; CHECK-NEXT: __0:
-; CHECK-NEXT: %__1 = trunc i32 %__0 to i8
-; CHECK-NEXT: %__2 = sitofp i8 %__1 to float
-; CHECK-NEXT: %__3 = sitofp i8 %__1 to double
-; CHECK-NEXT: ret float %__2
-; CHECK-NEXT: }
-
-define internal float @SitofpI16(i32 %p) {
- %v = trunc i32 %p to i16
- %vfloat = sitofp i16 %v to float
- %vdouble = sitofp i16 %v to double
- ret float %vfloat
-}
-
-; CHECK-NEXT: define internal float @SitofpI16(i32 %__0) {
-; CHECK-NEXT: __0:
-; CHECK-NEXT: %__1 = trunc i32 %__0 to i16
-; CHECK-NEXT: %__2 = sitofp i16 %__1 to float
-; CHECK-NEXT: %__3 = sitofp i16 %__1 to double
-; CHECK-NEXT: ret float %__2
-; CHECK-NEXT: }
-
-define internal float @SitofpI32(i32 %v) {
- %vfloat = sitofp i32 %v to float
- %vdouble = sitofp i32 %v to double
- ret float %vfloat
-}
-
-; CHECK-NEXT: define internal float @SitofpI32(i32 %__0) {
-; CHECK-NEXT: __0:
-; CHECK-NEXT: %__1 = sitofp i32 %__0 to float
-; CHECK-NEXT: %__2 = sitofp i32 %__0 to double
-; CHECK-NEXT: ret float %__1
-; CHECK-NEXT: }
-
-define internal float @SitofpI64(i64 %v) {
- %vfloat = sitofp i64 %v to float
- %vdouble = sitofp i64 %v to double
- ret float %vfloat
-}
-
-; CHECK-NEXT: define internal float @SitofpI64(i64 %__0) {
-; CHECK-NEXT: __0:
-; CHECK-NEXT: %__1 = sitofp i64 %__0 to float
-; CHECK-NEXT: %__2 = sitofp i64 %__0 to double
-; CHECK-NEXT: ret float %__1
-; CHECK-NEXT: }
-
-define internal float @BitcastI32(i32 %v) {
- %vfloat = bitcast i32 %v to float
- ret float %vfloat
-}
-
-; CHECK-NEXT: define internal float @BitcastI32(i32 %__0) {
-; CHECK-NEXT: __0:
-; CHECK-NEXT: %__1 = bitcast i32 %__0 to float
-; CHECK-NEXT: ret float %__1
-; CHECK-NEXT: }
-
-define internal double @BitcastI64(i64 %v) {
- %vdouble = bitcast i64 %v to double
- ret double %vdouble
-}
-
-; CHECK-NEXT: define internal double @BitcastI64(i64 %__0) {
-; CHECK-NEXT: __0:
-; CHECK-NEXT: %__1 = bitcast i64 %__0 to double
-; CHECK-NEXT: ret double %__1
-; CHECK-NEXT: }
-
-define internal i32 @BitcastFloat(float %v) {
- %vi32 = bitcast float %v to i32
- ret i32 %vi32
-}
-
-; CHECK-NEXT: define internal i32 @BitcastFloat(float %__0) {
-; CHECK-NEXT: __0:
-; CHECK-NEXT: %__1 = bitcast float %__0 to i32
-; CHECK-NEXT: ret i32 %__1
-; CHECK-NEXT: }
-
-define internal i64 @BitcastDouble(double %v) {
- %vi64 = bitcast double %v to i64
- ret i64 %vi64
-}
-
-; CHECK-NEXT: define internal i64 @BitcastDouble(double %__0) {
-; CHECK-NEXT: __0:
-; CHECK-NEXT: %__1 = bitcast double %__0 to i64
-; CHECK-NEXT: ret i64 %__1
-; CHECK-NEXT: }
-
-define internal void @BitcastV4xFloat(<4 x float> %v) {
- %v4xi32 = bitcast <4 x float> %v to <4 x i32>
- %v8xi16 = bitcast <4 x float> %v to <8 x i16>
- %v16xi8 = bitcast <4 x float> %v to <16 x i8>
- ret void
-}
-
-; CHECK-NEXT: define internal void @BitcastV4xFloat(<4 x float> %__0) {
-; CHECK-NEXT: __0:
-; CHECK-NEXT: %__1 = bitcast <4 x float> %__0 to <4 x i32>
-; CHECK-NEXT: %__2 = bitcast <4 x float> %__0 to <8 x i16>
-; CHECK-NEXT: %__3 = bitcast <4 x float> %__0 to <16 x i8>
-; CHECK-NEXT: ret void
-; CHECK-NEXT: }
-
-define internal void @BitcastV4xi32(<4 x i32> %v) {
- %v4xfloat = bitcast <4 x i32> %v to <4 x float>
- %v8xi16 = bitcast <4 x i32> %v to <8 x i16>
- %v16xi8 = bitcast <4 x i32> %v to <16 x i8>
- ret void
-}
-
-; CHECK-NEXT: define internal void @BitcastV4xi32(<4 x i32> %__0) {
-; CHECK-NEXT: __0:
-; CHECK-NEXT: %__1 = bitcast <4 x i32> %__0 to <4 x float>
-; CHECK-NEXT: %__2 = bitcast <4 x i32> %__0 to <8 x i16>
-; CHECK-NEXT: %__3 = bitcast <4 x i32> %__0 to <16 x i8>
-; CHECK-NEXT: ret void
-; CHECK-NEXT: }
-
-define internal void @BitcastV8xi16(<8 x i16> %v) {
- %v4xfloat = bitcast <8 x i16> %v to <4 x float>
- %v4xi32 = bitcast <8 x i16> %v to <4 x i32>
- %v16xi8 = bitcast <8 x i16> %v to <16 x i8>
- ret void
-}
-
-; CHECK-NEXT: define internal void @BitcastV8xi16(<8 x i16> %__0) {
-; CHECK-NEXT: __0:
-; CHECK-NEXT: %__1 = bitcast <8 x i16> %__0 to <4 x float>
-; CHECK-NEXT: %__2 = bitcast <8 x i16> %__0 to <4 x i32>
-; CHECK-NEXT: %__3 = bitcast <8 x i16> %__0 to <16 x i8>
-; CHECK-NEXT: ret void
-; CHECK-NEXT: }
-
-define internal void @BitcastV16xi8(<16 x i8> %v) {
- %v4xfloat = bitcast <16 x i8> %v to <4 x float>
- %v4xi32 = bitcast <16 x i8> %v to <4 x i32>
- %v8xi16 = bitcast <16 x i8> %v to <8 x i16>
- ret void
-}
-
-; CHECK-NEXT: define internal void @BitcastV16xi8(<16 x i8> %__0) {
-; CHECK-NEXT: __0:
-; CHECK-NEXT: %__1 = bitcast <16 x i8> %__0 to <4 x float>
-; CHECK-NEXT: %__2 = bitcast <16 x i8> %__0 to <4 x i32>
-; CHECK-NEXT: %__3 = bitcast <16 x i8> %__0 to <8 x i16>
-; CHECK-NEXT: ret void
-; CHECK-NEXT: }
-
-; NOIR: Total across all functions
diff --git a/third_party/subzero/tests_lit/reader_tests/compare.ll b/third_party/subzero/tests_lit/reader_tests/compare.ll
deleted file mode 100644
index bb2229b..0000000
--- a/third_party/subzero/tests_lit/reader_tests/compare.ll
+++ /dev/null
@@ -1,475 +0,0 @@
-; Test if we can read compare instructions.
-
-; RUN: %p2i -i %s --insts | FileCheck %s
-; RUN: %p2i -i %s --args -notranslate -timing | \
-; RUN: FileCheck --check-prefix=NOIR %s
-
-define internal void @IcmpI1(i32 %p1, i32 %p2) {
-entry:
- %a1 = trunc i32 %p1 to i1
- %a2 = trunc i32 %p2 to i1
- %veq = icmp eq i1 %a1, %a2
- %vne = icmp ne i1 %a1, %a2
- %vugt = icmp ugt i1 %a1, %a2
- %vuge = icmp uge i1 %a1, %a2
- %vult = icmp ult i1 %a1, %a2
- %vule = icmp ule i1 %a1, %a2
- %vsgt = icmp sgt i1 %a1, %a2
- %vsge = icmp sge i1 %a1, %a2
- %vslt = icmp slt i1 %a1, %a2
- %vsle = icmp sle i1 %a1, %a2
- ret void
-}
-
-; CHECK: define internal void @IcmpI1(i32 %p1, i32 %p2) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %a1 = trunc i32 %p1 to i1
-; CHECK-NEXT: %a2 = trunc i32 %p2 to i1
-; CHECK-NEXT: %veq = icmp eq i1 %a1, %a2
-; CHECK-NEXT: %vne = icmp ne i1 %a1, %a2
-; CHECK-NEXT: %vugt = icmp ugt i1 %a1, %a2
-; CHECK-NEXT: %vuge = icmp uge i1 %a1, %a2
-; CHECK-NEXT: %vult = icmp ult i1 %a1, %a2
-; CHECK-NEXT: %vule = icmp ule i1 %a1, %a2
-; CHECK-NEXT: %vsgt = icmp sgt i1 %a1, %a2
-; CHECK-NEXT: %vsge = icmp sge i1 %a1, %a2
-; CHECK-NEXT: %vslt = icmp slt i1 %a1, %a2
-; CHECK-NEXT: %vsle = icmp sle i1 %a1, %a2
-; CHECK-NEXT: ret void
-; CHECK-NEXT: }
-
-define internal void @IcmpI8(i32 %p1, i32 %p2) {
-entry:
- %a1 = trunc i32 %p1 to i8
- %a2 = trunc i32 %p2 to i8
- %veq = icmp eq i8 %a1, %a2
- %vne = icmp ne i8 %a1, %a2
- %vugt = icmp ugt i8 %a1, %a2
- %vuge = icmp uge i8 %a1, %a2
- %vult = icmp ult i8 %a1, %a2
- %vule = icmp ule i8 %a1, %a2
- %vsgt = icmp sgt i8 %a1, %a2
- %vsge = icmp sge i8 %a1, %a2
- %vslt = icmp slt i8 %a1, %a2
- %vsle = icmp sle i8 %a1, %a2
- ret void
-}
-
-; CHECK-NEXT: define internal void @IcmpI8(i32 %p1, i32 %p2) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %a1 = trunc i32 %p1 to i8
-; CHECK-NEXT: %a2 = trunc i32 %p2 to i8
-; CHECK-NEXT: %veq = icmp eq i8 %a1, %a2
-; CHECK-NEXT: %vne = icmp ne i8 %a1, %a2
-; CHECK-NEXT: %vugt = icmp ugt i8 %a1, %a2
-; CHECK-NEXT: %vuge = icmp uge i8 %a1, %a2
-; CHECK-NEXT: %vult = icmp ult i8 %a1, %a2
-; CHECK-NEXT: %vule = icmp ule i8 %a1, %a2
-; CHECK-NEXT: %vsgt = icmp sgt i8 %a1, %a2
-; CHECK-NEXT: %vsge = icmp sge i8 %a1, %a2
-; CHECK-NEXT: %vslt = icmp slt i8 %a1, %a2
-; CHECK-NEXT: %vsle = icmp sle i8 %a1, %a2
-; CHECK-NEXT: ret void
-; CHECK-NEXT: }
-
-define internal void @IcmpI16(i32 %p1, i32 %p2) {
-entry:
- %a1 = trunc i32 %p1 to i16
- %a2 = trunc i32 %p2 to i16
- %veq = icmp eq i16 %a1, %a2
- %vne = icmp ne i16 %a1, %a2
- %vugt = icmp ugt i16 %a1, %a2
- %vuge = icmp uge i16 %a1, %a2
- %vult = icmp ult i16 %a1, %a2
- %vule = icmp ule i16 %a1, %a2
- %vsgt = icmp sgt i16 %a1, %a2
- %vsge = icmp sge i16 %a1, %a2
- %vslt = icmp slt i16 %a1, %a2
- %vsle = icmp sle i16 %a1, %a2
- ret void
-}
-
-; CHECK-NEXT: define internal void @IcmpI16(i32 %p1, i32 %p2) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %a1 = trunc i32 %p1 to i16
-; CHECK-NEXT: %a2 = trunc i32 %p2 to i16
-; CHECK-NEXT: %veq = icmp eq i16 %a1, %a2
-; CHECK-NEXT: %vne = icmp ne i16 %a1, %a2
-; CHECK-NEXT: %vugt = icmp ugt i16 %a1, %a2
-; CHECK-NEXT: %vuge = icmp uge i16 %a1, %a2
-; CHECK-NEXT: %vult = icmp ult i16 %a1, %a2
-; CHECK-NEXT: %vule = icmp ule i16 %a1, %a2
-; CHECK-NEXT: %vsgt = icmp sgt i16 %a1, %a2
-; CHECK-NEXT: %vsge = icmp sge i16 %a1, %a2
-; CHECK-NEXT: %vslt = icmp slt i16 %a1, %a2
-; CHECK-NEXT: %vsle = icmp sle i16 %a1, %a2
-; CHECK-NEXT: ret void
-; CHECK-NEXT: }
-
-define internal void @IcmpI32(i32 %a1, i32 %a2) {
-entry:
- %veq = icmp eq i32 %a1, %a2
- %vne = icmp ne i32 %a1, %a2
- %vugt = icmp ugt i32 %a1, %a2
- %vuge = icmp uge i32 %a1, %a2
- %vult = icmp ult i32 %a1, %a2
- %vule = icmp ule i32 %a1, %a2
- %vsgt = icmp sgt i32 %a1, %a2
- %vsge = icmp sge i32 %a1, %a2
- %vslt = icmp slt i32 %a1, %a2
- %vsle = icmp sle i32 %a1, %a2
- ret void
-}
-
-; CHECK-NEXT: define internal void @IcmpI32(i32 %a1, i32 %a2) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %veq = icmp eq i32 %a1, %a2
-; CHECK-NEXT: %vne = icmp ne i32 %a1, %a2
-; CHECK-NEXT: %vugt = icmp ugt i32 %a1, %a2
-; CHECK-NEXT: %vuge = icmp uge i32 %a1, %a2
-; CHECK-NEXT: %vult = icmp ult i32 %a1, %a2
-; CHECK-NEXT: %vule = icmp ule i32 %a1, %a2
-; CHECK-NEXT: %vsgt = icmp sgt i32 %a1, %a2
-; CHECK-NEXT: %vsge = icmp sge i32 %a1, %a2
-; CHECK-NEXT: %vslt = icmp slt i32 %a1, %a2
-; CHECK-NEXT: %vsle = icmp sle i32 %a1, %a2
-; CHECK-NEXT: ret void
-; CHECK-NEXT: }
-
-define internal void @IcmpI64(i64 %a1, i64 %a2) {
-entry:
- %veq = icmp eq i64 %a1, %a2
- %vne = icmp ne i64 %a1, %a2
- %vugt = icmp ugt i64 %a1, %a2
- %vuge = icmp uge i64 %a1, %a2
- %vult = icmp ult i64 %a1, %a2
- %vule = icmp ule i64 %a1, %a2
- %vsgt = icmp sgt i64 %a1, %a2
- %vsge = icmp sge i64 %a1, %a2
- %vslt = icmp slt i64 %a1, %a2
- %vsle = icmp sle i64 %a1, %a2
- ret void
-}
-
-; CHECK-NEXT: define internal void @IcmpI64(i64 %a1, i64 %a2) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %veq = icmp eq i64 %a1, %a2
-; CHECK-NEXT: %vne = icmp ne i64 %a1, %a2
-; CHECK-NEXT: %vugt = icmp ugt i64 %a1, %a2
-; CHECK-NEXT: %vuge = icmp uge i64 %a1, %a2
-; CHECK-NEXT: %vult = icmp ult i64 %a1, %a2
-; CHECK-NEXT: %vule = icmp ule i64 %a1, %a2
-; CHECK-NEXT: %vsgt = icmp sgt i64 %a1, %a2
-; CHECK-NEXT: %vsge = icmp sge i64 %a1, %a2
-; CHECK-NEXT: %vslt = icmp slt i64 %a1, %a2
-; CHECK-NEXT: %vsle = icmp sle i64 %a1, %a2
-; CHECK-NEXT: ret void
-; CHECK-NEXT: }
-
-define internal <4 x i1> @IcmpV4xI1(<4 x i1> %a1, <4 x i1> %a2) {
-entry:
- %veq = icmp eq <4 x i1> %a1, %a2
- %vne = icmp ne <4 x i1> %a1, %a2
- %vugt = icmp ugt <4 x i1> %a1, %a2
- %vuge = icmp uge <4 x i1> %a1, %a2
- %vult = icmp ult <4 x i1> %a1, %a2
- %vule = icmp ule <4 x i1> %a1, %a2
- %vsgt = icmp sgt <4 x i1> %a1, %a2
- %vsge = icmp sge <4 x i1> %a1, %a2
- %vslt = icmp slt <4 x i1> %a1, %a2
- %vsle = icmp sle <4 x i1> %a1, %a2
- ret <4 x i1> %veq
-}
-
-; CHECK-NEXT: define internal <4 x i1> @IcmpV4xI1(<4 x i1> %a1, <4 x i1> %a2) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %veq = icmp eq <4 x i1> %a1, %a2
-; CHECK-NEXT: %vne = icmp ne <4 x i1> %a1, %a2
-; CHECK-NEXT: %vugt = icmp ugt <4 x i1> %a1, %a2
-; CHECK-NEXT: %vuge = icmp uge <4 x i1> %a1, %a2
-; CHECK-NEXT: %vult = icmp ult <4 x i1> %a1, %a2
-; CHECK-NEXT: %vule = icmp ule <4 x i1> %a1, %a2
-; CHECK-NEXT: %vsgt = icmp sgt <4 x i1> %a1, %a2
-; CHECK-NEXT: %vsge = icmp sge <4 x i1> %a1, %a2
-; CHECK-NEXT: %vslt = icmp slt <4 x i1> %a1, %a2
-; CHECK-NEXT: %vsle = icmp sle <4 x i1> %a1, %a2
-; CHECK-NEXT: ret <4 x i1> %veq
-; CHECK-NEXT: }
-
-define internal <8 x i1> @IcmpV8xI1(<8 x i1> %a1, <8 x i1> %a2) {
-entry:
- %veq = icmp eq <8 x i1> %a1, %a2
- %vne = icmp ne <8 x i1> %a1, %a2
- %vugt = icmp ugt <8 x i1> %a1, %a2
- %vuge = icmp uge <8 x i1> %a1, %a2
- %vult = icmp ult <8 x i1> %a1, %a2
- %vule = icmp ule <8 x i1> %a1, %a2
- %vsgt = icmp sgt <8 x i1> %a1, %a2
- %vsge = icmp sge <8 x i1> %a1, %a2
- %vslt = icmp slt <8 x i1> %a1, %a2
- %vsle = icmp sle <8 x i1> %a1, %a2
- ret <8 x i1> %veq
-}
-
-; CHECK-NEXT: define internal <8 x i1> @IcmpV8xI1(<8 x i1> %a1, <8 x i1> %a2) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %veq = icmp eq <8 x i1> %a1, %a2
-; CHECK-NEXT: %vne = icmp ne <8 x i1> %a1, %a2
-; CHECK-NEXT: %vugt = icmp ugt <8 x i1> %a1, %a2
-; CHECK-NEXT: %vuge = icmp uge <8 x i1> %a1, %a2
-; CHECK-NEXT: %vult = icmp ult <8 x i1> %a1, %a2
-; CHECK-NEXT: %vule = icmp ule <8 x i1> %a1, %a2
-; CHECK-NEXT: %vsgt = icmp sgt <8 x i1> %a1, %a2
-; CHECK-NEXT: %vsge = icmp sge <8 x i1> %a1, %a2
-; CHECK-NEXT: %vslt = icmp slt <8 x i1> %a1, %a2
-; CHECK-NEXT: %vsle = icmp sle <8 x i1> %a1, %a2
-; CHECK-NEXT: ret <8 x i1> %veq
-; CHECK-NEXT: }
-
-define internal <16 x i1> @IcmpV16xI1(<16 x i1> %a1, <16 x i1> %a2) {
-entry:
- %veq = icmp eq <16 x i1> %a1, %a2
- %vne = icmp ne <16 x i1> %a1, %a2
- %vugt = icmp ugt <16 x i1> %a1, %a2
- %vuge = icmp uge <16 x i1> %a1, %a2
- %vult = icmp ult <16 x i1> %a1, %a2
- %vule = icmp ule <16 x i1> %a1, %a2
- %vsgt = icmp sgt <16 x i1> %a1, %a2
- %vsge = icmp sge <16 x i1> %a1, %a2
- %vslt = icmp slt <16 x i1> %a1, %a2
- %vsle = icmp sle <16 x i1> %a1, %a2
- ret <16 x i1> %veq
-}
-
-; CHECK-NEXT: define internal <16 x i1> @IcmpV16xI1(<16 x i1> %a1, <16 x i1> %a2) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %veq = icmp eq <16 x i1> %a1, %a2
-; CHECK-NEXT: %vne = icmp ne <16 x i1> %a1, %a2
-; CHECK-NEXT: %vugt = icmp ugt <16 x i1> %a1, %a2
-; CHECK-NEXT: %vuge = icmp uge <16 x i1> %a1, %a2
-; CHECK-NEXT: %vult = icmp ult <16 x i1> %a1, %a2
-; CHECK-NEXT: %vule = icmp ule <16 x i1> %a1, %a2
-; CHECK-NEXT: %vsgt = icmp sgt <16 x i1> %a1, %a2
-; CHECK-NEXT: %vsge = icmp sge <16 x i1> %a1, %a2
-; CHECK-NEXT: %vslt = icmp slt <16 x i1> %a1, %a2
-; CHECK-NEXT: %vsle = icmp sle <16 x i1> %a1, %a2
-; CHECK-NEXT: ret <16 x i1> %veq
-; CHECK-NEXT: }
-
-define internal <16 x i1> @IcmpV16xI8(<16 x i8> %a1, <16 x i8> %a2) {
-entry:
- %veq = icmp eq <16 x i8> %a1, %a2
- %vne = icmp ne <16 x i8> %a1, %a2
- %vugt = icmp ugt <16 x i8> %a1, %a2
- %vuge = icmp uge <16 x i8> %a1, %a2
- %vult = icmp ult <16 x i8> %a1, %a2
- %vule = icmp ule <16 x i8> %a1, %a2
- %vsgt = icmp sgt <16 x i8> %a1, %a2
- %vsge = icmp sge <16 x i8> %a1, %a2
- %vslt = icmp slt <16 x i8> %a1, %a2
- %vsle = icmp sle <16 x i8> %a1, %a2
- ret <16 x i1> %veq
-}
-
-; CHECK-NEXT: define internal <16 x i1> @IcmpV16xI8(<16 x i8> %a1, <16 x i8> %a2) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %veq = icmp eq <16 x i8> %a1, %a2
-; CHECK-NEXT: %vne = icmp ne <16 x i8> %a1, %a2
-; CHECK-NEXT: %vugt = icmp ugt <16 x i8> %a1, %a2
-; CHECK-NEXT: %vuge = icmp uge <16 x i8> %a1, %a2
-; CHECK-NEXT: %vult = icmp ult <16 x i8> %a1, %a2
-; CHECK-NEXT: %vule = icmp ule <16 x i8> %a1, %a2
-; CHECK-NEXT: %vsgt = icmp sgt <16 x i8> %a1, %a2
-; CHECK-NEXT: %vsge = icmp sge <16 x i8> %a1, %a2
-; CHECK-NEXT: %vslt = icmp slt <16 x i8> %a1, %a2
-; CHECK-NEXT: %vsle = icmp sle <16 x i8> %a1, %a2
-; CHECK-NEXT: ret <16 x i1> %veq
-; CHECK-NEXT: }
-
-define internal <8 x i1> @IcmpV8xI16(<8 x i16> %a1, <8 x i16> %a2) {
-entry:
- %veq = icmp eq <8 x i16> %a1, %a2
- %vne = icmp ne <8 x i16> %a1, %a2
- %vugt = icmp ugt <8 x i16> %a1, %a2
- %vuge = icmp uge <8 x i16> %a1, %a2
- %vult = icmp ult <8 x i16> %a1, %a2
- %vule = icmp ule <8 x i16> %a1, %a2
- %vsgt = icmp sgt <8 x i16> %a1, %a2
- %vsge = icmp sge <8 x i16> %a1, %a2
- %vslt = icmp slt <8 x i16> %a1, %a2
- %vsle = icmp sle <8 x i16> %a1, %a2
- ret <8 x i1> %veq
-}
-
-; CHECK-NEXT: define internal <8 x i1> @IcmpV8xI16(<8 x i16> %a1, <8 x i16> %a2) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %veq = icmp eq <8 x i16> %a1, %a2
-; CHECK-NEXT: %vne = icmp ne <8 x i16> %a1, %a2
-; CHECK-NEXT: %vugt = icmp ugt <8 x i16> %a1, %a2
-; CHECK-NEXT: %vuge = icmp uge <8 x i16> %a1, %a2
-; CHECK-NEXT: %vult = icmp ult <8 x i16> %a1, %a2
-; CHECK-NEXT: %vule = icmp ule <8 x i16> %a1, %a2
-; CHECK-NEXT: %vsgt = icmp sgt <8 x i16> %a1, %a2
-; CHECK-NEXT: %vsge = icmp sge <8 x i16> %a1, %a2
-; CHECK-NEXT: %vslt = icmp slt <8 x i16> %a1, %a2
-; CHECK-NEXT: %vsle = icmp sle <8 x i16> %a1, %a2
-; CHECK-NEXT: ret <8 x i1> %veq
-; CHECK-NEXT: }
-
-define internal <4 x i1> @IcmpV4xI32(<4 x i32> %a1, <4 x i32> %a2) {
-entry:
- %veq = icmp eq <4 x i32> %a1, %a2
- %vne = icmp ne <4 x i32> %a1, %a2
- %vugt = icmp ugt <4 x i32> %a1, %a2
- %vuge = icmp uge <4 x i32> %a1, %a2
- %vult = icmp ult <4 x i32> %a1, %a2
- %vule = icmp ule <4 x i32> %a1, %a2
- %vsgt = icmp sgt <4 x i32> %a1, %a2
- %vsge = icmp sge <4 x i32> %a1, %a2
- %vslt = icmp slt <4 x i32> %a1, %a2
- %vsle = icmp sle <4 x i32> %a1, %a2
- ret <4 x i1> %veq
-}
-
-; CHECK-NEXT: define internal <4 x i1> @IcmpV4xI32(<4 x i32> %a1, <4 x i32> %a2) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %veq = icmp eq <4 x i32> %a1, %a2
-; CHECK-NEXT: %vne = icmp ne <4 x i32> %a1, %a2
-; CHECK-NEXT: %vugt = icmp ugt <4 x i32> %a1, %a2
-; CHECK-NEXT: %vuge = icmp uge <4 x i32> %a1, %a2
-; CHECK-NEXT: %vult = icmp ult <4 x i32> %a1, %a2
-; CHECK-NEXT: %vule = icmp ule <4 x i32> %a1, %a2
-; CHECK-NEXT: %vsgt = icmp sgt <4 x i32> %a1, %a2
-; CHECK-NEXT: %vsge = icmp sge <4 x i32> %a1, %a2
-; CHECK-NEXT: %vslt = icmp slt <4 x i32> %a1, %a2
-; CHECK-NEXT: %vsle = icmp sle <4 x i32> %a1, %a2
-; CHECK-NEXT: ret <4 x i1> %veq
-; CHECK-NEXT: }
-
-define internal void @FcmpFloat(float %a1, float %a2) {
-entry:
- %vfalse = fcmp false float %a1, %a2
- %voeq = fcmp oeq float %a1, %a2
- %vogt = fcmp ogt float %a1, %a2
- %voge = fcmp oge float %a1, %a2
- %volt = fcmp olt float %a1, %a2
- %vole = fcmp ole float %a1, %a2
- %vone = fcmp one float %a1, %a2
- %ord = fcmp ord float %a1, %a2
- %vueq = fcmp ueq float %a1, %a2
- %vugt = fcmp ugt float %a1, %a2
- %vuge = fcmp uge float %a1, %a2
- %vult = fcmp ult float %a1, %a2
- %vule = fcmp ule float %a1, %a2
- %vune = fcmp une float %a1, %a2
- %vuno = fcmp uno float %a1, %a2
- %vtrue = fcmp true float %a1, %a2
- ret void
-}
-
-; CHECK-NEXT: define internal void @FcmpFloat(float %a1, float %a2) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %vfalse = fcmp false float %a1, %a2
-; CHECK-NEXT: %voeq = fcmp oeq float %a1, %a2
-; CHECK-NEXT: %vogt = fcmp ogt float %a1, %a2
-; CHECK-NEXT: %voge = fcmp oge float %a1, %a2
-; CHECK-NEXT: %volt = fcmp olt float %a1, %a2
-; CHECK-NEXT: %vole = fcmp ole float %a1, %a2
-; CHECK-NEXT: %vone = fcmp one float %a1, %a2
-; CHECK-NEXT: %ord = fcmp ord float %a1, %a2
-; CHECK-NEXT: %vueq = fcmp ueq float %a1, %a2
-; CHECK-NEXT: %vugt = fcmp ugt float %a1, %a2
-; CHECK-NEXT: %vuge = fcmp uge float %a1, %a2
-; CHECK-NEXT: %vult = fcmp ult float %a1, %a2
-; CHECK-NEXT: %vule = fcmp ule float %a1, %a2
-; CHECK-NEXT: %vune = fcmp une float %a1, %a2
-; CHECK-NEXT: %vuno = fcmp uno float %a1, %a2
-; CHECK-NEXT: %vtrue = fcmp true float %a1, %a2
-; CHECK-NEXT: ret void
-; CHECK-NEXT: }
-
-define internal void @FcmpDouble(double %a1, double %a2) {
-entry:
- %vfalse = fcmp false double %a1, %a2
- %voeq = fcmp oeq double %a1, %a2
- %vogt = fcmp ogt double %a1, %a2
- %voge = fcmp oge double %a1, %a2
- %volt = fcmp olt double %a1, %a2
- %vole = fcmp ole double %a1, %a2
- %vone = fcmp one double %a1, %a2
- %ord = fcmp ord double %a1, %a2
- %vueq = fcmp ueq double %a1, %a2
- %vugt = fcmp ugt double %a1, %a2
- %vuge = fcmp uge double %a1, %a2
- %vult = fcmp ult double %a1, %a2
- %vule = fcmp ule double %a1, %a2
- %vune = fcmp une double %a1, %a2
- %vuno = fcmp uno double %a1, %a2
- %vtrue = fcmp true double %a1, %a2
- ret void
-}
-
-; CHECK-NEXT: define internal void @FcmpDouble(double %a1, double %a2) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %vfalse = fcmp false double %a1, %a2
-; CHECK-NEXT: %voeq = fcmp oeq double %a1, %a2
-; CHECK-NEXT: %vogt = fcmp ogt double %a1, %a2
-; CHECK-NEXT: %voge = fcmp oge double %a1, %a2
-; CHECK-NEXT: %volt = fcmp olt double %a1, %a2
-; CHECK-NEXT: %vole = fcmp ole double %a1, %a2
-; CHECK-NEXT: %vone = fcmp one double %a1, %a2
-; CHECK-NEXT: %ord = fcmp ord double %a1, %a2
-; CHECK-NEXT: %vueq = fcmp ueq double %a1, %a2
-; CHECK-NEXT: %vugt = fcmp ugt double %a1, %a2
-; CHECK-NEXT: %vuge = fcmp uge double %a1, %a2
-; CHECK-NEXT: %vult = fcmp ult double %a1, %a2
-; CHECK-NEXT: %vule = fcmp ule double %a1, %a2
-; CHECK-NEXT: %vune = fcmp une double %a1, %a2
-; CHECK-NEXT: %vuno = fcmp uno double %a1, %a2
-; CHECK-NEXT: %vtrue = fcmp true double %a1, %a2
-; CHECK-NEXT: ret void
-; CHECK-NEXT: }
-
-define internal <4 x i1> @FcmpV4xFloat(<4 x float> %a1, <4 x float> %a2) {
-entry:
- %vfalse = fcmp false <4 x float> %a1, %a2
- %voeq = fcmp oeq <4 x float> %a1, %a2
- %vogt = fcmp ogt <4 x float> %a1, %a2
- %voge = fcmp oge <4 x float> %a1, %a2
- %volt = fcmp olt <4 x float> %a1, %a2
- %vole = fcmp ole <4 x float> %a1, %a2
- %vone = fcmp one <4 x float> %a1, %a2
- %ord = fcmp ord <4 x float> %a1, %a2
- %vueq = fcmp ueq <4 x float> %a1, %a2
- %vugt = fcmp ugt <4 x float> %a1, %a2
- %vuge = fcmp uge <4 x float> %a1, %a2
- %vult = fcmp ult <4 x float> %a1, %a2
- %vule = fcmp ule <4 x float> %a1, %a2
- %vune = fcmp une <4 x float> %a1, %a2
- %vuno = fcmp uno <4 x float> %a1, %a2
- %vtrue = fcmp true <4 x float> %a1, %a2
- ret <4 x i1> %voeq
-}
-
-; CHECK-NEXT: define internal <4 x i1> @FcmpV4xFloat(<4 x float> %a1, <4 x float> %a2) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %vfalse = fcmp false <4 x float> %a1, %a2
-; CHECK-NEXT: %voeq = fcmp oeq <4 x float> %a1, %a2
-; CHECK-NEXT: %vogt = fcmp ogt <4 x float> %a1, %a2
-; CHECK-NEXT: %voge = fcmp oge <4 x float> %a1, %a2
-; CHECK-NEXT: %volt = fcmp olt <4 x float> %a1, %a2
-; CHECK-NEXT: %vole = fcmp ole <4 x float> %a1, %a2
-; CHECK-NEXT: %vone = fcmp one <4 x float> %a1, %a2
-; CHECK-NEXT: %ord = fcmp ord <4 x float> %a1, %a2
-; CHECK-NEXT: %vueq = fcmp ueq <4 x float> %a1, %a2
-; CHECK-NEXT: %vugt = fcmp ugt <4 x float> %a1, %a2
-; CHECK-NEXT: %vuge = fcmp uge <4 x float> %a1, %a2
-; CHECK-NEXT: %vult = fcmp ult <4 x float> %a1, %a2
-; CHECK-NEXT: %vule = fcmp ule <4 x float> %a1, %a2
-; CHECK-NEXT: %vune = fcmp une <4 x float> %a1, %a2
-; CHECK-NEXT: %vuno = fcmp uno <4 x float> %a1, %a2
-; CHECK-NEXT: %vtrue = fcmp true <4 x float> %a1, %a2
-; CHECK-NEXT: ret <4 x i1> %voeq
-; CHECK-NEXT: }
-
-; NOIR: Total across all functions
diff --git a/third_party/subzero/tests_lit/reader_tests/constants.ll b/third_party/subzero/tests_lit/reader_tests/constants.ll
deleted file mode 100644
index e63112e..0000000
--- a/third_party/subzero/tests_lit/reader_tests/constants.ll
+++ /dev/null
@@ -1,158 +0,0 @@
-; Test handling of constants in function blocks.
-
-; RUN: %p2i -i %s --insts | FileCheck %s
-; RUN: %p2i -i %s --args -notranslate -timing | \
-; RUN: FileCheck --check-prefix=NOIR %s
-
-define internal void @TestIntegers() {
-entry:
-; CHECK: entry:
-
- ; Test various sized integers
- %v0 = or i1 true, false
-; CHECK-NEXT: %v0 = or i1 true, false
-
- %v1 = add i8 0, 0
-; CHECK-NEXT: %v1 = add i8 0, 0
-
- %v2 = add i8 5, 0
-; CHECK-NEXT: %v2 = add i8 5, 0
-
- %v3 = add i8 -5, 0
-; CHECK-NEXT: %v3 = add i8 -5, 0
-
- %v4 = and i16 10, 0
-; CHECK-NEXT: %v4 = and i16 10, 0
-
- %v5 = add i16 -10, 0
-; CHECK-NEXT: %v5 = add i16 -10, 0
-
- %v6 = add i32 20, 0
-; CHECK-NEXT: %v6 = add i32 20, 0
-
- %v7 = add i32 -20, 0
-; CHECK-NEXT: %v7 = add i32 -20, 0
-
- %v8 = add i64 30, 0
-; CHECK-NEXT: %v8 = add i64 30, 0
-
- %v9 = add i64 -30, 0
-; CHECK-NEXT: %v9 = add i64 -30, 0
-
- ; Test undefined integer values.
- %v10 = xor i1 undef, false
-; CHECK-NEXT: %v10 = xor i1 undef, false
-
- %v11 = add i8 undef, 0
-; CHECK-NEXT: %v11 = add i8 undef, 0
-
- %v12 = add i16 undef, 0
-; CHECK-NEXT: %v12 = add i16 undef, 0
-
- %v13 = add i32 undef, 0
-; CHECK-NEXT: %v13 = add i32 undef, 0
-
- %v14 = add i64 undef, 0
-; CHECK-NEXT: %v14 = add i64 undef, 0
-
- ret void
-; CHECK-NEXT: ret void
-
-}
-
-define internal void @TestFloats() {
-entry:
-; CHECK: entry:
-
- ; Test float and double constants
- %v0 = fadd float 1.0, 0.0
-; CHECK-NEXT: %v0 = fadd float 1.000000e+00, 0.000000e+00
-
- %v1 = fadd double 1.0, 0.0
-; CHECK-NEXT: %v1 = fadd double 1.000000e+00, 0.000000e+00
-
- %v2 = fsub float 7.000000e+00, 8.000000e+00
-; CHECK-NEXT: %v2 = fsub float 7.000000e+00, 8.000000e+00
-
- %v3 = fsub double 5.000000e+00, 6.000000e+00
-; CHECK-NEXT: %v3 = fsub double 5.000000e+00, 6.000000e+00
-
- ; Test undefined float and double.
- %v4 = fadd float undef, 0.0
-; CHECK-NEXT: %v4 = fadd float undef, 0.000000e+00
-
- %v5 = fsub double undef, 6.000000e+00
-; CHECK-NEXT: %v5 = fsub double undef, 6.000000e+00
-
- ; Test special floating point constants. Note: LLVM assembly appears
- ; to use 64-bit integer constants for both float and double.
-
- ; Generated from NAN in <math.h>
- %v6 = fadd float 0x7FF8000000000000, 0.0
-; CHECK-NEXT: %v6 = fadd float nan, 0.000000e+00
-
- ; Generated from -NAN in <math.h>
- %v7 = fadd float 0xFFF8000000000000, 0.0
-; CHECK-NEXT: %v7 = fadd float -nan, 0.000000e+00
-
- ; Generated from INFINITY in <math.h>
- %v8 = fadd float 0x7FF0000000000000, 0.0
-; CHECK-NEXT: %v8 = fadd float inf, 0.000000e+00
-
- ; Generated from -INFINITY in <math.h>
- %v9 = fadd float 0xFFF0000000000000, 0.0
-; CHECK-NEXT: %v9 = fadd float -inf, 0.000000e+00
-
- ; Generated from FLT_MIN in <float.h>
- %v10 = fadd float 0x381000000000000000, 0.0
-; CHECK-NEXT: %v10 = fadd float 0.000000e+00, 0.000000e+00
-
- ; Generated from -FLT_MIN in <float.h>
- %v11 = fadd float 0xb81000000000000000, 0.0
-; CHECK-NEXT: %v11 = fadd float 0.000000e+00, 0.000000e+00
-
- ; Generated from FLT_MAX in <float.h>
- %v12 = fadd float 340282346638528859811704183484516925440.000000, 0.0
-; CHECK-NEXT: %v12 = fadd float 3.402823e+38, 0.000000e+00
-
- ; Generated from -FLT_MAX in <float.h>
- %v13 = fadd float -340282346638528859811704183484516925440.000000, 0.0
-; CHECK-NEXT: %v13 = fadd float -3.402823e+38, 0.000000e+00
-
- ; Generated from NAN in <math.h>
- %v14 = fadd double 0x7FF8000000000000, 0.0
-; CHECK-NEXT: %v14 = fadd double nan, 0.000000e+00
-
- ; Generated from -NAN in <math.h>
- %v15 = fadd double 0xFFF8000000000000, 0.0
-; CHECK-NEXT: %v15 = fadd double -nan, 0.000000e+00
-
- ; Generated from INFINITY in <math.h>
- %v16 = fadd double 0x7FF0000000000000, 0.0
-; CHECK-NEXT: %v16 = fadd double inf, 0.000000e+00
-
- ; Generated from -INFINITY in <math.h>
- %v17 = fadd double 0xFFF0000000000000, 0.0
-; CHECK-NEXT: %v17 = fadd double -inf, 0.000000e+00
-
- ; Generated from DBL_MIN in <float.h>
- %v18 = fadd double 0x0010000000000000, 0.0
-; CHECK-NEXT: %v18 = fadd double 2.225074e-308, 0.000000e+00
-
- ; Generated from -DBL_MIN in <float.h>
- %v19 = fadd double 0x8010000000000000, 0.0
-; CHECK-NEXT: %v19 = fadd double -2.225074e-308, 0.000000e+00
-
- ; Generated from DBL_MAX in <float.h>
- %v20 = fadd double 179769313486231570814527423731704356798070567525844996598917476803157260780028538760589558632766878171540458953514382464234321326889464182768467546703537516986049910576551282076245490090389328944075868508455133942304583236903222948165808559332123348274797826204144723168738177180919299881250404026184124858368.000000, 0.0
-; CHECK-NEXT: %v20 = fadd double 1.797693e+308, 0.000000e+00
-
- ; Generated from -DBL_MAX in <float.h>
- %v21 = fadd double -179769313486231570814527423731704356798070567525844996598917476803157260780028538760589558632766878171540458953514382464234321326889464182768467546703537516986049910576551282076245490090389328944075868508455133942304583236903222948165808559332123348274797826204144723168738177180919299881250404026184124858368.000000, 0.0
-; CHECK-NEXT: %v21 = fadd double -1.797693e+308, 0.000000e+00
-
- ret void
-; CHECK-NEXT: ret void
-}
-
-; NOIR: Total across all functions
diff --git a/third_party/subzero/tests_lit/reader_tests/extern_globals.ll b/third_party/subzero/tests_lit/reader_tests/extern_globals.ll
deleted file mode 100644
index ddc870e..0000000
--- a/third_party/subzero/tests_lit/reader_tests/extern_globals.ll
+++ /dev/null
@@ -1,270 +0,0 @@
-; Test whether we don't mangle external, undefined, global names. This
-; feature is needed for cross tests on global initializer relocations.
-;
-; Note: This code was generated by compiling subzero/crosstest/test_global.cpp
-
-; We use lc2i (rather than p2i) because PNaCl bitcode files do not
-; allow externally defined global variables. Hence, this test can only
-; work if we read LLVM IR source, and convert to to ICE.
-
-; REQUIRES: allow_llvm_ir_as_input
-; RUN: %lc2i -i %s --insts --args --allow-uninitialized-globals \
-; RUN: -allow-externally-defined-symbols | FileCheck %s
-; RUN: %lc2i -i %s --insts --args --allow-uninitialized-globals \
-; RUN: -allow-externally-defined-symbols \
-; RUN: -prefix Subzero_ | FileCheck --check-prefix=CROSS %s
-
-@ArrayInitPartial = internal global [40 x i8] c"<\00\00\00F\00\00\00P\00\00\00Z\00\00\00d\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00", align 4
-
-; CHECK: @ArrayInitPartial = internal global [40 x i8] c"<\00\00\00F\00\00\00P\00\00\00Z\00\00\00d\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00", align 4
-; CROSS: @Subzero_ArrayInitPartial = internal global [40 x i8] c"<\00\00\00F\00\00\00P\00\00\00Z\00\00\00d\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00", align 4
-
-@ArrayInitFull = internal global [20 x i8] c"\0A\00\00\00\14\00\00\00\1E\00\00\00(\00\00\002\00\00\00", align 4
-
-; CHECK: @ArrayInitFull = internal global [20 x i8] c"\0A\00\00\00\14\00\00\00\1E\00\00\00(\00\00\002\00\00\00", align 4
-; CROSS: @Subzero_ArrayInitFull = internal global [20 x i8] c"\0A\00\00\00\14\00\00\00\1E\00\00\00(\00\00\002\00\00\00", align 4
-
-@NumArraysElements = internal global [4 x i8] c"\06\00\00\00", align 4
-
-; CHECK: @NumArraysElements = internal global [4 x i8] c"\06\00\00\00", align 4
-; CROSS: @Subzero_NumArraysElements = internal global [4 x i8] c"\06\00\00\00", align 4
-
-@Arrays = internal constant <{ i32, [4 x i8], i32, [4 x i8], i32, [4 x i8], i32, [4 x i8], i32, [4 x i8], i32, [4 x i8] }> <{ i32 ptrtoint ([40 x i8]* @ArrayInitPartial to i32), [4 x i8] c"(\00\00\00", i32 ptrtoint ([20 x i8]* @ArrayInitFull to i32), [4 x i8] c"\14\00\00\00", i32 ptrtoint ([12 x i8]* @_ZL10ArrayConst to i32), [4 x i8] c"\0C\00\00\00", i32 ptrtoint ([80 x i8]* @_ZL11ArrayDouble to i32), [4 x i8] c"P\00\00\00", i32 add (i32 ptrtoint ([40 x i8]* @ArrayInitPartial to i32), i32 8), [4 x i8] c" \00\00\00", i32 ptrtoint ([80 x i8]* @_ZL8StructEx to i32), [4 x i8] c"P\00\00\00" }>, align 4
-
-; CHECK: @Arrays = internal constant <{ i32, [4 x i8], i32, [4 x i8], i32, [4 x i8], i32, [4 x i8], i32, [4 x i8], i32, [4 x i8] }> <{ i32 ptrtoint ([40 x i8]* @ArrayInitPartial to i32), [4 x i8] c"(\00\00\00", i32 ptrtoint ([20 x i8]* @ArrayInitFull to i32), [4 x i8] c"\14\00\00\00", i32 ptrtoint ([12 x i8]* @_ZL10ArrayConst to i32), [4 x i8] c"\0C\00\00\00", i32 ptrtoint ([80 x i8]* @_ZL11ArrayDouble to i32), [4 x i8] c"P\00\00\00", i32 add (i32 ptrtoint ([40 x i8]* @ArrayInitPartial to i32), i32 8), [4 x i8] c" \00\00\00", i32 ptrtoint ([80 x i8]* @_ZL8StructEx to i32), [4 x i8] c"P\00\00\00" }>, align 4
-; CROSS: @Subzero_Arrays = internal constant <{ i32, [4 x i8], i32, [4 x i8], i32, [4 x i8], i32, [4 x i8], i32, [4 x i8], i32, [4 x i8] }> <{ i32 ptrtoint ([40 x i8]* @Subzero_ArrayInitPartial to i32), [4 x i8] c"(\00\00\00", i32 ptrtoint ([20 x i8]* @Subzero_ArrayInitFull to i32), [4 x i8] c"\14\00\00\00", i32 ptrtoint ([12 x i8]* @Subzero__ZL10ArrayConst to i32), [4 x i8] c"\0C\00\00\00", i32 ptrtoint ([80 x i8]* @Subzero__ZL11ArrayDouble to i32), [4 x i8] c"P\00\00\00", i32 add (i32 ptrtoint ([40 x i8]* @Subzero_ArrayInitPartial to i32), i32 8), [4 x i8] c" \00\00\00", i32 ptrtoint ([80 x i8]* @Subzero__ZL8StructEx to i32), [4 x i8] c"P\00\00\00" }>, align 4
-
-
-@_ZL10ArrayConst = internal constant [12 x i8] c"\F6\FF\FF\FF\EC\FF\FF\FF\E2\FF\FF\FF", align 4
-
-; CHECK: @_ZL10ArrayConst = internal constant [12 x i8] c"\F6\FF\FF\FF\EC\FF\FF\FF\E2\FF\FF\FF", align 4
-; CROSS: @Subzero__ZL10ArrayConst = internal constant [12 x i8] c"\F6\FF\FF\FF\EC\FF\FF\FF\E2\FF\FF\FF", align 4
-
-@_ZL11ArrayDouble = internal global [80 x i8] c"\00\00\00\00\00\00\E0?\00\00\00\00\00\00\F8?\00\00\00\00\00\00\04@\00\00\00\00\00\00\0C@\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00", align 8
-
-; CHECK: @_ZL11ArrayDouble = internal global [80 x i8] c"\00\00\00\00\00\00\E0?\00\00\00\00\00\00\F8?\00\00\00\00\00\00\04@\00\00\00\00\00\00\0C@\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00", align 8
-; CROSS: @Subzero__ZL11ArrayDouble = internal global [80 x i8] c"\00\00\00\00\00\00\E0?\00\00\00\00\00\00\F8?\00\00\00\00\00\00\04@\00\00\00\00\00\00\0C@\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00", align 8
-
-@_ZL8StructEx = internal global [80 x i8] zeroinitializer, align 8
-
-; CHECK: @_ZL8StructEx = internal global [80 x i8] zeroinitializer, align 8
-; CROSS: @Subzero__ZL8StructEx = internal global [80 x i8] zeroinitializer, align 8
-
-@ExternName1 = external global [4 x i8], align 4
-
-; CHECK: @ExternName1 = external global <{ }> <{ }>, align 4
-; CROSS: @ExternName1 = external global <{ }> <{ }>, align 4
-
-@ExternName4 = external global [4 x i8], align 4
-
-; CHECK: @ExternName4 = external global <{ }> <{ }>, align 4
-; CROSS: @ExternName4 = external global <{ }> <{ }>, align 4
-
-@ExternName3 = external global [4 x i8], align 4
-
-; CHECK: @ExternName3 = external global <{ }> <{ }>, align 4
-; CROSS: @ExternName3 = external global <{ }> <{ }>, align 4
-
-@ExternName2 = external global [4 x i8], align 4
-
-; CHECK: @ExternName2 = external global <{ }> <{ }>, align 4
-; CROSS: @ExternName2 = external global <{ }> <{ }>, align 4
-
-@ExternName5 = external global [4 x i8], align 4
-
-; CHECK: @ExternName5 = external global <{ }> <{ }>, align 4
-; CROSS: @ExternName5 = external global <{ }> <{ }>, align 4
-
-define i32 @_Z12getNumArraysv() {
-; CHECK: define i32 @_Z12getNumArraysv() {
-; CROSS: define i32 @_ZN8Subzero_12getNumArraysEv() {
-entry:
- %NumArraysElements.bc = bitcast [4 x i8]* @NumArraysElements to i32*
-; CHECK: %NumArraysElements.bc = bitcast i32 @NumArraysElements to i32
-; CROSS: %NumArraysElements.bc = bitcast i32 @Subzero_NumArraysElements to i32
- %0 = load i32, i32* %NumArraysElements.bc, align 1
- ret i32 %0
-}
-
-define i32 @_Z8getArrayjRj(i32 %WhichArray, i32 %Len) {
-; CHECK: define i32 @_Z8getArrayjRj(i32 %WhichArray, i32 %Len) {
-; CROSS: define i32 @_ZN8Subzero_8getArrayEjRj(i32 %WhichArray, i32 %Len) {
-entry:
- %NumArraysElements.bc = bitcast [4 x i8]* @NumArraysElements to i32*
-; CHECK: %NumArraysElements.bc = bitcast i32 @NumArraysElements to i32
-; CROSS: %NumArraysElements.bc = bitcast i32 @Subzero_NumArraysElements to i32
- %0 = load i32, i32* %NumArraysElements.bc, align 1
- %cmp = icmp ugt i32 %0, %WhichArray
-; CHECK: %cmp = icmp ugt i32 %__3, %WhichArray
-; CROSS: %cmp = icmp ugt i32 %__3, %WhichArray
- br i1 %cmp, label %if.end, label %if.then
-
-if.then: ; preds = %entry
- %Len.asptr = inttoptr i32 %Len to i32*
-; CHECK: %Len.asptr = i32 %Len
-; CROSS: %Len.asptr = i32 %Len
- store i32 -1, i32* %Len.asptr, align 1
- br label %return
-
-if.end: ; preds = %entry
- %gep_array = mul i32 %WhichArray, 8
-; CHECK: %gep_array = mul i32 %WhichArray, 8
-; CROSS: %gep_array = mul i32 %WhichArray, 8
- %expanded1 = ptrtoint <{ i32, [4 x i8], i32, [4 x i8], i32, [4 x i8], i32, [4 x i8], i32, [4 x i8], i32, [4 x i8] }>* @Arrays to i32
-; CHECK: %expanded1 = i32 @Arrays
-; CROSS: %expanded1 = i32 @Subzero_Arrays
- %gep = add i32 %expanded1, %gep_array
- %gep1 = add i32 %gep, 4
- %gep1.asptr = inttoptr i32 %gep1 to i32*
- %1 = load i32, i32* %gep1.asptr, align 1
- %Len.asptr3 = inttoptr i32 %Len to i32*
-; CHECK: %Len.asptr3 = i32 %Len
-; CROSS: %Len.asptr3 = i32 %Len
- store i32 %1, i32* %Len.asptr3, align 1
- %gep_array3 = mul i32 %WhichArray, 8
-; CHECK: %gep_array3 = mul i32 %WhichArray, 8
-; CROSS: %gep_array3 = mul i32 %WhichArray, 8
- %expanded2 = ptrtoint <{ i32, [4 x i8], i32, [4 x i8], i32, [4 x i8], i32, [4 x i8], i32, [4 x i8], i32, [4 x i8] }>* @Arrays to i32
-; CHECK: %expanded2 = i32 @Arrays
-; CROSS: %expanded2 = i32 @Subzero_Arrays
- %gep4 = add i32 %expanded2, %gep_array3
- %gep4.asptr = inttoptr i32 %gep4 to i32*
- %2 = load i32, i32* %gep4.asptr, align 1
- br label %return
-
-return: ; preds = %if.end, %if.then
- %retval.0 = phi i32 [ 0, %if.then ], [ %2, %if.end ]
- ret i32 %retval.0
-}
-
-define void @_GLOBAL__I_a() {
-; CHECK: define void @_GLOBAL__I_a() {
-; CROSS: define void @Subzero__GLOBAL__I_a() {
-entry:
- %_ZL8StructEx.bc = bitcast [80 x i8]* @_ZL8StructEx to i32*
-; CHECK: %_ZL8StructEx.bc = bitcast i32 @_ZL8StructEx to i32
-; CROSS: %_ZL8StructEx.bc = bitcast i32 @Subzero__ZL8StructEx to i32
- store i32 10, i32* %_ZL8StructEx.bc, align 1
- %expanded1 = ptrtoint [80 x i8]* @_ZL8StructEx to i32
-; CHECK: %expanded1 = i32 @_ZL8StructEx
-; CROSS: %expanded1 = i32 @Subzero__ZL8StructEx
- %gep = add i32 %expanded1, 4
- %gep.asptr = inttoptr i32 %gep to i32*
- store i32 20, i32* %gep.asptr, align 1
- %expanded2 = ptrtoint [80 x i8]* @_ZL8StructEx to i32
-; CHECK: %expanded2 = i32 @_ZL8StructEx
-; CROSS: %expanded2 = i32 @Subzero__ZL8StructEx
- %gep18 = add i32 %expanded2, 8
- %gep18.asptr = inttoptr i32 %gep18 to i32*
- store i32 30, i32* %gep18.asptr, align 1
- %expanded3 = ptrtoint [80 x i8]* @_ZL8StructEx to i32
-; CHECK: %expanded3 = i32 @_ZL8StructEx
-; CROSS: %expanded3 = i32 @Subzero__ZL8StructEx
- %gep20 = add i32 %expanded3, 12
- %gep20.asptr = inttoptr i32 %gep20 to i32*
- store i32 40, i32* %gep20.asptr, align 1
- %expanded4 = ptrtoint [80 x i8]* @_ZL8StructEx to i32
-; CHECK: %expanded4 = i32 @_ZL8StructEx
-; CROSS: %expanded4 = i32 @Subzero__ZL8StructEx
- %gep22 = add i32 %expanded4, 16
- %gep22.asptr = inttoptr i32 %gep22 to i32*
- store i32 50, i32* %gep22.asptr, align 1
- %ExternName1.bc = bitcast [4 x i8]* @ExternName1 to i32*
-; CHECK: %ExternName1.bc = bitcast i32 @ExternName1 to i32
-; CROSS: %ExternName1.bc = bitcast i32 @ExternName1 to i32
- %0 = load i32, i32* %ExternName1.bc, align 1
- %expanded6 = ptrtoint [80 x i8]* @_ZL8StructEx to i32
-; CHECK: %expanded6 = i32 @_ZL8StructEx
-; CROSS: %expanded6 = i32 @Subzero__ZL8StructEx
- %gep24 = add i32 %expanded6, 20
- %gep24.asptr = inttoptr i32 %gep24 to i32*
- store i32 %0, i32* %gep24.asptr, align 1
- %expanded7 = ptrtoint [80 x i8]* @_ZL8StructEx to i32
-; CHECK: %expanded7 = i32 @_ZL8StructEx
-; CROSS: %expanded7 = i32 @Subzero__ZL8StructEx
- %gep26 = add i32 %expanded7, 24
- %gep26.asptr = inttoptr i32 %gep26 to double*
- store double 5.000000e-01, double* %gep26.asptr, align 8
- %expanded8 = ptrtoint [80 x i8]* @_ZL8StructEx to i32
-; CHECK: %expanded8 = i32 @_ZL8StructEx
-; CROSS: %expanded8 = i32 @Subzero__ZL8StructEx
- %gep28 = add i32 %expanded8, 32
- %gep28.asptr = inttoptr i32 %gep28 to double*
- store double 1.500000e+00, double* %gep28.asptr, align 8
- %expanded9 = ptrtoint [80 x i8]* @_ZL8StructEx to i32
-; CHECK: %expanded9 = i32 @_ZL8StructEx
-; CROSS: %expanded9 = i32 @Subzero__ZL8StructEx
- %gep30 = add i32 %expanded9, 40
- %gep30.asptr = inttoptr i32 %gep30 to double*
- store double 2.500000e+00, double* %gep30.asptr, align 8
- %ExternName4.bc = bitcast [4 x i8]* @ExternName4 to i32*
-; CHECK: %ExternName4.bc = bitcast i32 @ExternName4 to i32
-; CROSS: %ExternName4.bc = bitcast i32 @ExternName4 to i32
- %1 = load i32, i32* %ExternName4.bc, align 1
- %expanded11 = ptrtoint [80 x i8]* @_ZL8StructEx to i32
-; CHECK: %expanded11 = i32 @_ZL8StructEx
-; CROSS: %expanded11 = i32 @Subzero__ZL8StructEx
- %gep32 = add i32 %expanded11, 48
- %gep32.asptr = inttoptr i32 %gep32 to i32*
- store i32 %1, i32* %gep32.asptr, align 1
- %ExternName3.bc = bitcast [4 x i8]* @ExternName3 to i32*
-; CHECK: %ExternName3.bc = bitcast i32 @ExternName3 to i32
-; CROSS: %ExternName3.bc = bitcast i32 @ExternName3 to i32
- %2 = load i32, i32* %ExternName3.bc, align 1
- %expanded13 = ptrtoint [80 x i8]* @_ZL8StructEx to i32
-; CHECK: %expanded13 = i32 @_ZL8StructEx
-; CROSS: %expanded13 = i32 @Subzero__ZL8StructEx
- %gep34 = add i32 %expanded13, 52
- %gep34.asptr = inttoptr i32 %gep34 to i32*
- store i32 %2, i32* %gep34.asptr, align 1
- %expanded14 = ptrtoint [80 x i8]* @_ZL8StructEx to i32
-; CHECK: %expanded14 = i32 @_ZL8StructEx
-; CROSS: %expanded14 = i32 @Subzero__ZL8StructEx
- %gep36 = add i32 %expanded14, 56
- %gep36.asptr = inttoptr i32 %gep36 to i32*
- store i32 1000, i32* %gep36.asptr, align 1
- %expanded15 = ptrtoint [80 x i8]* @_ZL8StructEx to i32
-; CHECK: %expanded15 = i32 @_ZL8StructEx
-; CROSS: %expanded15 = i32 @Subzero__ZL8StructEx
- %gep38 = add i32 %expanded15, 60
- %gep38.asptr = inttoptr i32 %gep38 to i32*
- store i32 1010, i32* %gep38.asptr, align 1
- %expanded16 = ptrtoint [80 x i8]* @_ZL8StructEx to i32
-; CHECK: %expanded16 = i32 @_ZL8StructEx
-; CROSS: %expanded16 = i32 @Subzero__ZL8StructEx
- %gep40 = add i32 %expanded16, 64
- %gep40.asptr = inttoptr i32 %gep40 to i32*
- store i32 1020, i32* %gep40.asptr, align 1
- %ExternName2.bc = bitcast [4 x i8]* @ExternName2 to i32*
-; CHECK: %ExternName2.bc = bitcast i32 @ExternName2 to i32
-; CROSS: %ExternName2.bc = bitcast i32 @ExternName2 to i32
- %3 = load i32, i32* %ExternName2.bc, align 1
- %expanded18 = ptrtoint [80 x i8]* @_ZL8StructEx to i32
-; CHECK: %expanded18 = i32 @_ZL8StructEx
-; CROSS: %expanded18 = i32 @Subzero__ZL8StructEx
- %gep42 = add i32 %expanded18, 68
- %gep42.asptr = inttoptr i32 %gep42 to i32*
- store i32 %3, i32* %gep42.asptr, align 1
- %ExternName5.bc = bitcast [4 x i8]* @ExternName5 to i32*
-; CHECK: %ExternName5.bc = bitcast i32 @ExternName5 to i32
-; CROSS: %ExternName5.bc = bitcast i32 @ExternName5 to i32
- %4 = load i32, i32* %ExternName5.bc, align 1
- %expanded20 = ptrtoint [80 x i8]* @_ZL8StructEx to i32
-; CHECK: %expanded20 = i32 @_ZL8StructEx
-; CROSS: %expanded20 = i32 @Subzero__ZL8StructEx
- %gep44 = add i32 %expanded20, 72
- %gep44.asptr = inttoptr i32 %gep44 to i32*
- store i32 %4, i32* %gep44.asptr, align 1
- ret void
-}
-
-define i32 @nacl_tp_tdb_offset(i32) {
-entry:
- ret i32 0
-}
-
-define i32 @nacl_tp_tls_offset(i32 %size) {
-entry:
- %result = sub i32 0, %size
- ret i32 %result
-}
diff --git a/third_party/subzero/tests_lit/reader_tests/forwardref.ll b/third_party/subzero/tests_lit/reader_tests/forwardref.ll
deleted file mode 100644
index adc0dee..0000000
--- a/third_party/subzero/tests_lit/reader_tests/forwardref.ll
+++ /dev/null
@@ -1,112 +0,0 @@
-; Test use forward type references in function blocks.
-
-; RUN: %p2i -i %s --insts | FileCheck %s
-; RUN: llvm-as < %s | pnacl-freeze | pnacl-bcdis -no-records \
-; RUN: | FileCheck --check-prefix=DUMP %s
-; RUN: %p2i -i %s --args -notranslate -timing | \
-; RUN: FileCheck --check-prefix=NOIR %s
-
-define internal void @LoopCarriedDep() {
-b0:
- %v0 = add i32 1, 2
- br label %b1
-b1:
- %v1 = phi i32 [%v0, %b0], [%v2, %b1]
- %v2 = add i32 %v1, 1
- br label %b1
-}
-
-; CHECK: define internal void @LoopCarriedDep() {
-; CHECK-NEXT: b0:
-; CHECK-NEXT: %v0 = add i32 1, 2
-; CHECK-NEXT: br label %b1
-; CHECK-NEXT: b1:
-; CHECK-NEXT: %v1 = phi i32 [ %v0, %b0 ], [ %v2, %b1 ]
-; CHECK-NEXT: %v2 = add i32 %v1, 1
-; CHECK-NEXT: br label %b1
-; CHECK-NEXT: }
-
-; Snippet of bitcode objdump with forward type reference (see "declare").
-; DUMP: function void @f0() { // BlockID = 12
-; DUMP-NEXT: blocks 2;
-; DUMP-NEXT: constants { // BlockID = 11
-; DUMP-NEXT: i32: <@a0>
-; DUMP-NEXT: %c0 = i32 1; <@a1>
-; DUMP-NEXT: %c1 = i32 2; <@a1>
-; DUMP-NEXT: }
-; DUMP-NEXT: %b0:
-; DUMP-NEXT: %v0 = add i32 %c0, %c1; <@a1>
-; DUMP-NEXT: br label %b1;
-; DUMP-NEXT: %b1:
-; DUMP-NEXT: declare i32 %v2; <@a6>
-; DUMP-NEXT: %v1 = phi i32 [%v0, %b0], [%v2, %b1];
-; DUMP-NEXT: %v2 = add i32 %v1, %c0; <@a1>
-; DUMP-NEXT: br label %b1;
-; DUMP-NEXT: }
-
-define internal void @BackBranch(i32 %p0) {
-b0:
- br label %b4
-b1:
- %v0 = add i32 %p0, %v3
- br label %b6
-b2:
- %v1 = add i32 %p0, %v4
- br label %b6
-b3:
- %v2 = add i32 %p0, %v3 ; No forward declare, already done!
- br label %b6
-b4:
- %v3 = add i32 %p0, %p0
- br i1 1, label %b1, label %b5
-b5:
- %v4 = add i32 %v3, %p0
- br i1 1, label %b2, label %b3
-b6:
- ret void
-}
-
-; CHECK: define internal void @BackBranch(i32 %p0) {
-; CHECK-NEXT: b0:
-; CHECK-NEXT: br label %b4
-; CHECK-NEXT: b1:
-; CHECK-NEXT: %v0 = add i32 %p0, %v3
-; CHECK-NEXT: br label %b6
-; CHECK-NEXT: b4:
-; CHECK-NEXT: %v3 = add i32 %p0, %p0
-; CHECK-NEXT: br label %b1
-; CHECK-NEXT: b6:
-; CHECK-NEXT: ret void
-; CHECK-NEXT: }
-
-; Snippet of bitcode objdump with forward type references (see "declare").
-; DUMP: function void @f1(i32 %p0) { // BlockID = 12
-; DUMP-NEXT: blocks 7;
-; DUMP-NEXT: constants { // BlockID = 11
-; DUMP-NEXT: i1: <@a0>
-; DUMP-NEXT: %c0 = i1 1; <@a1>
-; DUMP-NEXT: }
-; DUMP-NEXT: %b0:
-; DUMP-NEXT: br label %b4;
-; DUMP-NEXT: %b1:
-; DUMP-NEXT: declare i32 %v3; <@a6>
-; DUMP-NEXT: %v0 = add i32 %p0, %v3; <@a1>
-; DUMP-NEXT: br label %b6;
-; DUMP-NEXT: %b2:
-; DUMP-NEXT: declare i32 %v4; <@a6>
-; DUMP-NEXT: %v1 = add i32 %p0, %v4; <@a1>
-; DUMP-NEXT: br label %b6;
-; DUMP-NEXT: %b3:
-; DUMP-NEXT: %v2 = add i32 %p0, %v3; <@a1>
-; DUMP-NEXT: br label %b6;
-; DUMP-NEXT: %b4:
-; DUMP-NEXT: %v3 = add i32 %p0, %p0; <@a1>
-; DUMP-NEXT: br i1 %c0, label %b1, label %b5;
-; DUMP-NEXT: %b5:
-; DUMP-NEXT: %v4 = add i32 %v3, %p0; <@a1>
-; DUMP-NEXT: br i1 %c0, label %b2, label %b3;
-; DUMP-NEXT: %b6:
-; DUMP-NEXT: ret void; <@a3>
-; DUMP-NEXT: }
-
-; NOIR: Total across all functions
diff --git a/third_party/subzero/tests_lit/reader_tests/globalinit.pnacl.ll b/third_party/subzero/tests_lit/reader_tests/globalinit.pnacl.ll
deleted file mode 100644
index 9d020f3..0000000
--- a/third_party/subzero/tests_lit/reader_tests/globalinit.pnacl.ll
+++ /dev/null
@@ -1,84 +0,0 @@
-; Test of global initializers.
-
-; RUN: %p2i -i %s --insts --args -allow-externally-defined-symbols \
-; RUN: | FileCheck %s
-; RUN: %l2i -i %s --insts --args -allow-externally-defined-symbols \
-; RUN: | %ifl FileCheck %s
-; RUN: %lc2i -i %s --insts --args -allow-externally-defined-symbols \
-; RUN: | %iflc FileCheck %s
-; RUN: %p2i -i %s --args -notranslate -timing \
-; RUN: -allow-externally-defined-symbols | \
-; RUN: FileCheck --check-prefix=NOIR %s
-
-@PrimitiveInit = internal global [4 x i8] c"\1B\00\00\00", align 4
-; CHECK: @PrimitiveInit = internal global [4 x i8] c"\1B\00\00\00", align 4
-
-@PrimitiveInitConst = internal constant [4 x i8] c"\0D\00\00\00", align 4
-; CHECK-NEXT: @PrimitiveInitConst = internal constant [4 x i8] c"\0D\00\00\00", align 4
-
-@ArrayInit = internal global [20 x i8] c"\0A\00\00\00\14\00\00\00\1E\00\00\00(\00\00\002\00\00\00", align 4
-; CHECK-NEXT: @ArrayInit = internal global [20 x i8] c"\0A\00\00\00\14\00\00\00\1E\00\00\00(\00\00\002\00\00\00", align 4
-
-@ArrayInitPartial = internal global [40 x i8] c"<\00\00\00F\00\00\00P\00\00\00Z\00\00\00d\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00", align 4
-; CHECK-NEXT: @ArrayInitPartial = internal global [40 x i8] c"<\00\00\00F\00\00\00P\00\00\00Z\00\00\00d\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00", align 4
-
-@PrimitiveInitStatic = internal global [4 x i8] zeroinitializer, align 4
-; CHECK-NEXT: @PrimitiveInitStatic = internal global [4 x i8] zeroinitializer, align 4
-
-@PrimitiveUninit = internal global [4 x i8] zeroinitializer, align 4
-; CHECK-NEXT: @PrimitiveUninit = internal global [4 x i8] zeroinitializer, align 4
-
-@ArrayUninit = internal global [20 x i8] zeroinitializer, align 4
-; CHECK-NEXT: @ArrayUninit = internal global [20 x i8] zeroinitializer, align 4
-
-@ArrayUninitConstDouble = internal constant [200 x i8] zeroinitializer, align 8
-; CHECK-NEXT: @ArrayUninitConstDouble = internal constant [200 x i8] zeroinitializer, align 8
-
-@ArrayUninitConstInt = internal constant [20 x i8] zeroinitializer, align 4
-; CHECK-NEXT: @ArrayUninitConstInt = internal constant [20 x i8] zeroinitializer, align 4
-
-@__init_array_start = internal constant [0 x i8] zeroinitializer, align 4
-; CHECK-NEXT: @__init_array_start = internal constant [0 x i8] zeroinitializer, align 4
-
-@__fini_array_start = internal constant [0 x i8] zeroinitializer, align 4
-; CHECK: @__fini_array_start = internal constant [0 x i8] zeroinitializer, align 4
-
-@__tls_template_start = internal constant [0 x i8] zeroinitializer, align 8
-; CHECK: @__tls_template_start = internal constant [0 x i8] zeroinitializer, align 8
-
-@__tls_template_alignment = internal constant [4 x i8] c"\01\00\00\00", align 4
-; CHECK: @__tls_template_alignment = internal constant [4 x i8] c"\01\00\00\00", align 4
-
-define internal i32 @main(i32 %argc, i32 %argv) {
-entry:
- %expanded1 = ptrtoint [4 x i8]* @PrimitiveInit to i32
- call void @use(i32 %expanded1)
- %expanded3 = ptrtoint [4 x i8]* @PrimitiveInitConst to i32
- call void @use(i32 %expanded3)
- %expanded5 = ptrtoint [4 x i8]* @PrimitiveInitStatic to i32
- call void @use(i32 %expanded5)
- %expanded7 = ptrtoint [4 x i8]* @PrimitiveUninit to i32
- call void @use(i32 %expanded7)
- %expanded9 = ptrtoint [20 x i8]* @ArrayInit to i32
- call void @use(i32 %expanded9)
- %expanded11 = ptrtoint [40 x i8]* @ArrayInitPartial to i32
- call void @use(i32 %expanded11)
- %expanded13 = ptrtoint [20 x i8]* @ArrayUninit to i32
- call void @use(i32 %expanded13)
- ret i32 0
-}
-
-declare void @use(i32)
-
-define internal i32 @nacl_tp_tdb_offset(i32 %__0) {
-entry:
- ret i32 0
-}
-
-define internal i32 @nacl_tp_tls_offset(i32 %size) {
-entry:
- %result = sub i32 0, %size
- ret i32 %result
-}
-
-; NOIR: Total across all functions
diff --git a/third_party/subzero/tests_lit/reader_tests/globalrelocs.ll b/third_party/subzero/tests_lit/reader_tests/globalrelocs.ll
deleted file mode 100644
index b6869d1..0000000
--- a/third_party/subzero/tests_lit/reader_tests/globalrelocs.ll
+++ /dev/null
@@ -1,100 +0,0 @@
-; Tests if we handle global variables with relocation initializers.
-
-; RUN: %p2i -i %s --insts | FileCheck %s
-; RUN: %l2i -i %s --insts | %ifl FileCheck %s
-; RUN: %lc2i -i %s --insts | %iflc FileCheck %s
-; RUN: %p2i -i %s --args -notranslate -timing | \
-; RUN: FileCheck --check-prefix=NOIR %s
-
-@bytes = internal global [7 x i8] c"abcdefg"
-; CHECK: @bytes = internal global [7 x i8] c"abcdefg"
-
-@const_bytes = internal constant [7 x i8] c"abcdefg"
-; CHECK-NEXT: @const_bytes = internal constant [7 x i8] c"abcdefg"
-
-@ptr_to_ptr = internal global i32 ptrtoint (i32* @ptr to i32)
-; CHECK-NEXT: @ptr_to_ptr = internal global i32 ptrtoint (i32* @ptr to i32)
-
-@const_ptr_to_ptr = internal constant i32 ptrtoint (i32* @ptr to i32)
-; CHECK-NEXT: @const_ptr_to_ptr = internal constant i32 ptrtoint (i32* @ptr to i32)
-
-@ptr_to_func = internal global i32 ptrtoint (void ()* @func to i32)
-; CHECK-NEXT: @ptr_to_func = internal global i32 ptrtoint (void ()* @func to i32)
-
-@const_ptr_to_func = internal constant i32 ptrtoint (void ()* @func to i32)
-; CHECK-NEXT: @const_ptr_to_func = internal constant i32 ptrtoint (void ()* @func to i32)
-
-@compound = internal global <{ [3 x i8], i32 }> <{ [3 x i8] c"foo", i32 ptrtoint (void ()* @func to i32) }>
-; CHECK-NEXT: @compound = internal global <{ [3 x i8], i32 }> <{ [3 x i8] c"foo", i32 ptrtoint (void ()* @func to i32) }>
-
-@const_compound = internal constant <{ [3 x i8], i32 }> <{ [3 x i8] c"foo", i32 ptrtoint (void ()* @func to i32) }>
-
-; CHECK-NEXT: @const_compound = internal constant <{ [3 x i8], i32 }> <{ [3 x i8] c"foo", i32 ptrtoint (void ()* @func to i32) }>
-
-@ptr = internal global i32 ptrtoint ([7 x i8]* @bytes to i32)
-; CHECK-NEXT: @ptr = internal global i32 ptrtoint ([7 x i8]* @bytes to i32)
-
-@const_ptr = internal constant i32 ptrtoint ([7 x i8]* @bytes to i32)
-; CHECK-NEXT: @const_ptr = internal constant i32 ptrtoint ([7 x i8]* @bytes to i32)
-
-@addend_ptr = internal global i32 add (i32 ptrtoint (i32* @ptr to i32), i32 1)
-; CHECK-NEXT: @addend_ptr = internal global i32 add (i32 ptrtoint (i32* @ptr to i32), i32 1)
-
-@const_addend_ptr = internal constant i32 add (i32 ptrtoint (i32* @ptr to i32), i32 1)
-; CHECK-NEXT: @const_addend_ptr = internal constant i32 add (i32 ptrtoint (i32* @ptr to i32), i32 1)
-
-@addend_negative = internal global i32 add (i32 ptrtoint (i32* @ptr to i32), i32 -1)
-; CHECK-NEXT: @addend_negative = internal global i32 add (i32 ptrtoint (i32* @ptr to i32), i32 -1)
-
-@const_addend_negative = internal constant i32 add (i32 ptrtoint (i32* @ptr to i32), i32 -1)
-; CHECK-NEXT: @const_addend_negative = internal constant i32 add (i32 ptrtoint (i32* @ptr to i32), i32 -1)
-
-@addend_array1 = internal global i32 add (i32 ptrtoint ([7 x i8]* @bytes to i32), i32 1)
-; CHECK-NEXT: @addend_array1 = internal global i32 add (i32 ptrtoint ([7 x i8]* @bytes to i32), i32 1)
-
-@const_addend_array1 = internal constant i32 add (i32 ptrtoint ([7 x i8]* @bytes to i32), i32 1)
-; CHECK-NEXT: @const_addend_array1 = internal constant i32 add (i32 ptrtoint ([7 x i8]* @bytes to i32), i32 1)
-
-@addend_array2 = internal global i32 add (i32 ptrtoint ([7 x i8]* @bytes to i32), i32 7)
-; CHECK-NEXT: @addend_array2 = internal global i32 add (i32 ptrtoint ([7 x i8]* @bytes to i32), i32 7)
-
-@const_addend_array2 = internal constant i32 add (i32 ptrtoint ([7 x i8]* @bytes to i32), i32 7)
-; CHECK-NEXT: @const_addend_array2 = internal constant i32 add (i32 ptrtoint ([7 x i8]* @bytes to i32), i32 7)
-
-@addend_array3 = internal global i32 add (i32 ptrtoint ([7 x i8]* @bytes to i32), i32 9)
-; CHECK-NEXT: @addend_array3 = internal global i32 add (i32 ptrtoint ([7 x i8]* @bytes to i32), i32 9)
-
-@const_addend_array3 = internal constant i32 add (i32 ptrtoint ([7 x i8]* @bytes to i32), i32 9)
-; CHECK-NEXT: @const_addend_array3 = internal constant i32 add (i32 ptrtoint ([7 x i8]* @bytes to i32), i32 9)
-
-@addend_struct1 = internal global i32 add (i32 ptrtoint (<{ [3 x i8], i32 }>* @compound to i32), i32 1)
-; CHECK-NEXT: @addend_struct1 = internal global i32 add (i32 ptrtoint (<{ [3 x i8], i32 }>* @compound to i32), i32 1)
-
-@const_addend_struct1 = internal constant i32 add (i32 ptrtoint (<{ [3 x i8], i32 }>* @compound to i32), i32 1)
-; CHECK-NEXT: @const_addend_struct1 = internal constant i32 add (i32 ptrtoint (<{ [3 x i8], i32 }>* @compound to i32), i32 1)
-
-@addend_struct2 = internal global i32 add (i32 ptrtoint (<{ [3 x i8], i32 }>* @compound to i32), i32 4)
-; CHECK-NEXT: @addend_struct2 = internal global i32 add (i32 ptrtoint (<{ [3 x i8], i32 }>* @compound to i32), i32 4)
-
-@const_addend_struct2 = internal constant i32 add (i32 ptrtoint (<{ [3 x i8], i32 }>* @compound to i32), i32 4)
-; CHECK-NEXT: @const_addend_struct2 = internal constant i32 add (i32 ptrtoint (<{ [3 x i8], i32 }>* @compound to i32), i32 4)
-
-@ptr_to_func_align = internal global i32 ptrtoint (void ()* @func to i32), align 8
-; CHECK-NEXT: @ptr_to_func_align = internal global i32 ptrtoint (void ()* @func to i32), align 8
-
-@const_ptr_to_func_align = internal constant i32 ptrtoint (void ()* @func to i32), align 8
-; CHECK-NEXT: @const_ptr_to_func_align = internal constant i32 ptrtoint (void ()* @func to i32), align 8
-
-@char = internal constant [1 x i8] c"0"
-; CHECK-NEXT: @char = internal constant [1 x i8] c"0"
-
-@short = internal constant [2 x i8] zeroinitializer
-; CHECK-NEXT: @short = internal constant [2 x i8] zeroinitializer
-
-define internal void @func() {
- ret void
-}
-
-; CHECK-NEXT: define internal void @func() {
-
-; NOIR: Total across all functions
diff --git a/third_party/subzero/tests_lit/reader_tests/insertextract.ll b/third_party/subzero/tests_lit/reader_tests/insertextract.ll
deleted file mode 100644
index ffdda6c..0000000
--- a/third_party/subzero/tests_lit/reader_tests/insertextract.ll
+++ /dev/null
@@ -1,383 +0,0 @@
-; Tests insertelement and extractelement vector instructions.
-
-; RUN: %p2i -i %s --insts | FileCheck %s
-; RUN: %l2i -i %s --insts | %ifl FileCheck %s
-; RUN: %lc2i -i %s --insts | %iflc FileCheck %s
-; RUN: %p2i -i %s --args -notranslate -timing | \
-; RUN: FileCheck --check-prefix=NOIR %s
-
-define internal void @ExtractV4xi1(<4 x i1> %v) {
-entry:
- %e0 = extractelement <4 x i1> %v, i32 0
- %e1 = extractelement <4 x i1> %v, i32 1
- %e2 = extractelement <4 x i1> %v, i32 2
- %e3 = extractelement <4 x i1> %v, i32 3
- ret void
-}
-
-; CHECK: define internal void @ExtractV4xi1(<4 x i1> %v) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %e0 = extractelement <4 x i1> %v, i32 0
-; CHECK-NEXT: %e1 = extractelement <4 x i1> %v, i32 1
-; CHECK-NEXT: %e2 = extractelement <4 x i1> %v, i32 2
-; CHECK-NEXT: %e3 = extractelement <4 x i1> %v, i32 3
-; CHECK-NEXT: ret void
-; CHECK-NEXT: }
-
-define internal void @ExtractV8xi1(<8 x i1> %v) {
-entry:
- %e0 = extractelement <8 x i1> %v, i32 0
- %e1 = extractelement <8 x i1> %v, i32 1
- %e2 = extractelement <8 x i1> %v, i32 2
- %e3 = extractelement <8 x i1> %v, i32 3
- %e4 = extractelement <8 x i1> %v, i32 4
- %e5 = extractelement <8 x i1> %v, i32 5
- %e6 = extractelement <8 x i1> %v, i32 6
- %e7 = extractelement <8 x i1> %v, i32 7
- ret void
-}
-
-; CHECK-NEXT: define internal void @ExtractV8xi1(<8 x i1> %v) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %e0 = extractelement <8 x i1> %v, i32 0
-; CHECK-NEXT: %e1 = extractelement <8 x i1> %v, i32 1
-; CHECK-NEXT: %e2 = extractelement <8 x i1> %v, i32 2
-; CHECK-NEXT: %e3 = extractelement <8 x i1> %v, i32 3
-; CHECK-NEXT: %e4 = extractelement <8 x i1> %v, i32 4
-; CHECK-NEXT: %e5 = extractelement <8 x i1> %v, i32 5
-; CHECK-NEXT: %e6 = extractelement <8 x i1> %v, i32 6
-; CHECK-NEXT: %e7 = extractelement <8 x i1> %v, i32 7
-; CHECK-NEXT: ret void
-; CHECK-NEXT: }
-
-define internal void @ExtractV16xi1(<16 x i1> %v) {
-entry:
- %e0 = extractelement <16 x i1> %v, i32 0
- %e1 = extractelement <16 x i1> %v, i32 1
- %e2 = extractelement <16 x i1> %v, i32 2
- %e3 = extractelement <16 x i1> %v, i32 3
- %e4 = extractelement <16 x i1> %v, i32 4
- %e5 = extractelement <16 x i1> %v, i32 5
- %e6 = extractelement <16 x i1> %v, i32 6
- %e7 = extractelement <16 x i1> %v, i32 7
- %e8 = extractelement <16 x i1> %v, i32 8
- %e9 = extractelement <16 x i1> %v, i32 9
- %e10 = extractelement <16 x i1> %v, i32 10
- %e11 = extractelement <16 x i1> %v, i32 11
- %e12 = extractelement <16 x i1> %v, i32 12
- %e13 = extractelement <16 x i1> %v, i32 13
- %e14 = extractelement <16 x i1> %v, i32 14
- %e15 = extractelement <16 x i1> %v, i32 15
- ret void
-}
-
-; CHECK-NEXT: define internal void @ExtractV16xi1(<16 x i1> %v) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %e0 = extractelement <16 x i1> %v, i32 0
-; CHECK-NEXT: %e1 = extractelement <16 x i1> %v, i32 1
-; CHECK-NEXT: %e2 = extractelement <16 x i1> %v, i32 2
-; CHECK-NEXT: %e3 = extractelement <16 x i1> %v, i32 3
-; CHECK-NEXT: %e4 = extractelement <16 x i1> %v, i32 4
-; CHECK-NEXT: %e5 = extractelement <16 x i1> %v, i32 5
-; CHECK-NEXT: %e6 = extractelement <16 x i1> %v, i32 6
-; CHECK-NEXT: %e7 = extractelement <16 x i1> %v, i32 7
-; CHECK-NEXT: %e8 = extractelement <16 x i1> %v, i32 8
-; CHECK-NEXT: %e9 = extractelement <16 x i1> %v, i32 9
-; CHECK-NEXT: %e10 = extractelement <16 x i1> %v, i32 10
-; CHECK-NEXT: %e11 = extractelement <16 x i1> %v, i32 11
-; CHECK-NEXT: %e12 = extractelement <16 x i1> %v, i32 12
-; CHECK-NEXT: %e13 = extractelement <16 x i1> %v, i32 13
-; CHECK-NEXT: %e14 = extractelement <16 x i1> %v, i32 14
-; CHECK-NEXT: %e15 = extractelement <16 x i1> %v, i32 15
-; CHECK-NEXT: ret void
-; CHECK-NEXT: }
-
-define internal void @ExtractV16xi8(<16 x i8> %v, i32 %i) {
-entry:
- %e0 = extractelement <16 x i8> %v, i32 0
- %e1 = extractelement <16 x i8> %v, i32 1
- %e2 = extractelement <16 x i8> %v, i32 2
- %e3 = extractelement <16 x i8> %v, i32 3
- %e4 = extractelement <16 x i8> %v, i32 4
- %e5 = extractelement <16 x i8> %v, i32 5
- %e6 = extractelement <16 x i8> %v, i32 6
- %e7 = extractelement <16 x i8> %v, i32 7
- %e8 = extractelement <16 x i8> %v, i32 8
- %e9 = extractelement <16 x i8> %v, i32 9
- %e10 = extractelement <16 x i8> %v, i32 10
- %e11 = extractelement <16 x i8> %v, i32 11
- %e12 = extractelement <16 x i8> %v, i32 12
- %e13 = extractelement <16 x i8> %v, i32 13
- %e14 = extractelement <16 x i8> %v, i32 14
- %e15 = extractelement <16 x i8> %v, i32 15
- ret void
-}
-
-; CHECK-NEXT: define internal void @ExtractV16xi8(<16 x i8> %v, i32 %i) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %e0 = extractelement <16 x i8> %v, i32 0
-; CHECK-NEXT: %e1 = extractelement <16 x i8> %v, i32 1
-; CHECK-NEXT: %e2 = extractelement <16 x i8> %v, i32 2
-; CHECK-NEXT: %e3 = extractelement <16 x i8> %v, i32 3
-; CHECK-NEXT: %e4 = extractelement <16 x i8> %v, i32 4
-; CHECK-NEXT: %e5 = extractelement <16 x i8> %v, i32 5
-; CHECK-NEXT: %e6 = extractelement <16 x i8> %v, i32 6
-; CHECK-NEXT: %e7 = extractelement <16 x i8> %v, i32 7
-; CHECK-NEXT: %e8 = extractelement <16 x i8> %v, i32 8
-; CHECK-NEXT: %e9 = extractelement <16 x i8> %v, i32 9
-; CHECK-NEXT: %e10 = extractelement <16 x i8> %v, i32 10
-; CHECK-NEXT: %e11 = extractelement <16 x i8> %v, i32 11
-; CHECK-NEXT: %e12 = extractelement <16 x i8> %v, i32 12
-; CHECK-NEXT: %e13 = extractelement <16 x i8> %v, i32 13
-; CHECK-NEXT: %e14 = extractelement <16 x i8> %v, i32 14
-; CHECK-NEXT: %e15 = extractelement <16 x i8> %v, i32 15
-; CHECK-NEXT: ret void
-; CHECK-NEXT: }
-
-define internal void @ExtractV8xi16(<8 x i16> %v) {
-entry:
- %e0 = extractelement <8 x i16> %v, i32 0
- %e1 = extractelement <8 x i16> %v, i32 1
- %e2 = extractelement <8 x i16> %v, i32 2
- %e3 = extractelement <8 x i16> %v, i32 3
- %e4 = extractelement <8 x i16> %v, i32 4
- %e5 = extractelement <8 x i16> %v, i32 5
- %e6 = extractelement <8 x i16> %v, i32 6
- %e7 = extractelement <8 x i16> %v, i32 7
- ret void
-}
-
-; CHECK-NEXT: define internal void @ExtractV8xi16(<8 x i16> %v) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %e0 = extractelement <8 x i16> %v, i32 0
-; CHECK-NEXT: %e1 = extractelement <8 x i16> %v, i32 1
-; CHECK-NEXT: %e2 = extractelement <8 x i16> %v, i32 2
-; CHECK-NEXT: %e3 = extractelement <8 x i16> %v, i32 3
-; CHECK-NEXT: %e4 = extractelement <8 x i16> %v, i32 4
-; CHECK-NEXT: %e5 = extractelement <8 x i16> %v, i32 5
-; CHECK-NEXT: %e6 = extractelement <8 x i16> %v, i32 6
-; CHECK-NEXT: %e7 = extractelement <8 x i16> %v, i32 7
-; CHECK-NEXT: ret void
-; CHECK-NEXT: }
-
-define internal i32 @ExtractV4xi32(<4 x i32> %v) {
-entry:
- %e0 = extractelement <4 x i32> %v, i32 0
- %e1 = extractelement <4 x i32> %v, i32 1
- %e2 = extractelement <4 x i32> %v, i32 2
- %e3 = extractelement <4 x i32> %v, i32 3
- ret i32 %e0
-}
-
-; CHECK-NEXT: define internal i32 @ExtractV4xi32(<4 x i32> %v) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %e0 = extractelement <4 x i32> %v, i32 0
-; CHECK-NEXT: %e1 = extractelement <4 x i32> %v, i32 1
-; CHECK-NEXT: %e2 = extractelement <4 x i32> %v, i32 2
-; CHECK-NEXT: %e3 = extractelement <4 x i32> %v, i32 3
-; CHECK-NEXT: ret i32 %e0
-; CHECK-NEXT: }
-
-define internal float @ExtractV4xfloat(<4 x float> %v) {
-entry:
- %e0 = extractelement <4 x float> %v, i32 0
- %e1 = extractelement <4 x float> %v, i32 1
- %e2 = extractelement <4 x float> %v, i32 2
- %e3 = extractelement <4 x float> %v, i32 3
- ret float %e0
-}
-
-; CHECK-NEXT: define internal float @ExtractV4xfloat(<4 x float> %v) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %e0 = extractelement <4 x float> %v, i32 0
-; CHECK-NEXT: %e1 = extractelement <4 x float> %v, i32 1
-; CHECK-NEXT: %e2 = extractelement <4 x float> %v, i32 2
-; CHECK-NEXT: %e3 = extractelement <4 x float> %v, i32 3
-; CHECK-NEXT: ret float %e0
-; CHECK-NEXT: }
-
-define internal <4 x i1> @InsertV4xi1(<4 x i1> %v, i32 %pe) {
-entry:
- %e = trunc i32 %pe to i1
- %r0 = insertelement <4 x i1> %v, i1 %e, i32 0
- %r1 = insertelement <4 x i1> %v, i1 %e, i32 1
- %r2 = insertelement <4 x i1> %v, i1 %e, i32 2
- %r3 = insertelement <4 x i1> %v, i1 %e, i32 3
- ret <4 x i1> %r3
-}
-
-; CHECK-NEXT: define internal <4 x i1> @InsertV4xi1(<4 x i1> %v, i32 %pe) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %e = trunc i32 %pe to i1
-; CHECK-NEXT: %r0 = insertelement <4 x i1> %v, i1 %e, i32 0
-; CHECK-NEXT: %r1 = insertelement <4 x i1> %v, i1 %e, i32 1
-; CHECK-NEXT: %r2 = insertelement <4 x i1> %v, i1 %e, i32 2
-; CHECK-NEXT: %r3 = insertelement <4 x i1> %v, i1 %e, i32 3
-; CHECK-NEXT: ret <4 x i1> %r3
-; CHECK-NEXT: }
-
-define internal <8 x i1> @InsertV8xi1(<8 x i1> %v, i32 %pe) {
-entry:
- %e = trunc i32 %pe to i1
- %r0 = insertelement <8 x i1> %v, i1 %e, i32 0
- %r1 = insertelement <8 x i1> %v, i1 %e, i32 1
- %r2 = insertelement <8 x i1> %v, i1 %e, i32 2
- %r3 = insertelement <8 x i1> %v, i1 %e, i32 3
- %r4 = insertelement <8 x i1> %v, i1 %e, i32 4
- %r5 = insertelement <8 x i1> %v, i1 %e, i32 5
- %r6 = insertelement <8 x i1> %v, i1 %e, i32 6
- %r7 = insertelement <8 x i1> %v, i1 %e, i32 7
- ret <8 x i1> %r7
-}
-
-; CHECK-NEXT: define internal <8 x i1> @InsertV8xi1(<8 x i1> %v, i32 %pe) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %e = trunc i32 %pe to i1
-; CHECK-NEXT: %r0 = insertelement <8 x i1> %v, i1 %e, i32 0
-; CHECK-NEXT: %r1 = insertelement <8 x i1> %v, i1 %e, i32 1
-; CHECK-NEXT: %r2 = insertelement <8 x i1> %v, i1 %e, i32 2
-; CHECK-NEXT: %r3 = insertelement <8 x i1> %v, i1 %e, i32 3
-; CHECK-NEXT: %r4 = insertelement <8 x i1> %v, i1 %e, i32 4
-; CHECK-NEXT: %r5 = insertelement <8 x i1> %v, i1 %e, i32 5
-; CHECK-NEXT: %r6 = insertelement <8 x i1> %v, i1 %e, i32 6
-; CHECK-NEXT: %r7 = insertelement <8 x i1> %v, i1 %e, i32 7
-; CHECK-NEXT: ret <8 x i1> %r7
-; CHECK-NEXT: }
-
-define internal <16 x i1> @InsertV16xi1(<16 x i1> %v, i32 %pe) {
-entry:
- %e = trunc i32 %pe to i1
- %r0 = insertelement <16 x i1> %v, i1 %e, i32 0
- %r1 = insertelement <16 x i1> %v, i1 %e, i32 1
- %r2 = insertelement <16 x i1> %v, i1 %e, i32 2
- %r3 = insertelement <16 x i1> %v, i1 %e, i32 3
- %r4 = insertelement <16 x i1> %v, i1 %e, i32 4
- %r5 = insertelement <16 x i1> %v, i1 %e, i32 5
- %r6 = insertelement <16 x i1> %v, i1 %e, i32 6
- %r7 = insertelement <16 x i1> %v, i1 %e, i32 7
- %r8 = insertelement <16 x i1> %v, i1 %e, i32 8
- %r9 = insertelement <16 x i1> %v, i1 %e, i32 9
- %r10 = insertelement <16 x i1> %v, i1 %e, i32 10
- %r11 = insertelement <16 x i1> %v, i1 %e, i32 11
- %r12 = insertelement <16 x i1> %v, i1 %e, i32 12
- %r13 = insertelement <16 x i1> %v, i1 %e, i32 13
- %r14 = insertelement <16 x i1> %v, i1 %e, i32 14
- %r15 = insertelement <16 x i1> %v, i1 %e, i32 15
- ret <16 x i1> %r15
-}
-
-; CHECK-NEXT: define internal <16 x i1> @InsertV16xi1(<16 x i1> %v, i32 %pe) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %e = trunc i32 %pe to i1
-; CHECK-NEXT: %r0 = insertelement <16 x i1> %v, i1 %e, i32 0
-; CHECK-NEXT: %r1 = insertelement <16 x i1> %v, i1 %e, i32 1
-; CHECK-NEXT: %r2 = insertelement <16 x i1> %v, i1 %e, i32 2
-; CHECK-NEXT: %r3 = insertelement <16 x i1> %v, i1 %e, i32 3
-; CHECK-NEXT: %r4 = insertelement <16 x i1> %v, i1 %e, i32 4
-; CHECK-NEXT: %r5 = insertelement <16 x i1> %v, i1 %e, i32 5
-; CHECK-NEXT: %r6 = insertelement <16 x i1> %v, i1 %e, i32 6
-; CHECK-NEXT: %r7 = insertelement <16 x i1> %v, i1 %e, i32 7
-; CHECK-NEXT: %r8 = insertelement <16 x i1> %v, i1 %e, i32 8
-; CHECK-NEXT: %r9 = insertelement <16 x i1> %v, i1 %e, i32 9
-; CHECK-NEXT: %r10 = insertelement <16 x i1> %v, i1 %e, i32 10
-; CHECK-NEXT: %r11 = insertelement <16 x i1> %v, i1 %e, i32 11
-; CHECK-NEXT: %r12 = insertelement <16 x i1> %v, i1 %e, i32 12
-; CHECK-NEXT: %r13 = insertelement <16 x i1> %v, i1 %e, i32 13
-; CHECK-NEXT: %r14 = insertelement <16 x i1> %v, i1 %e, i32 14
-; CHECK-NEXT: %r15 = insertelement <16 x i1> %v, i1 %e, i32 15
-; CHECK-NEXT: ret <16 x i1> %r15
-; CHECK-NEXT: }
-
-define internal <16 x i8> @InsertV16xi8(<16 x i8> %v, i32 %pe) {
-entry:
- %e = trunc i32 %pe to i8
- %r0 = insertelement <16 x i8> %v, i8 %e, i32 0
- %r1 = insertelement <16 x i8> %v, i8 %e, i32 1
- %r2 = insertelement <16 x i8> %v, i8 %e, i32 2
- %r3 = insertelement <16 x i8> %v, i8 %e, i32 3
- %r4 = insertelement <16 x i8> %v, i8 %e, i32 4
- %r5 = insertelement <16 x i8> %v, i8 %e, i32 5
- %r6 = insertelement <16 x i8> %v, i8 %e, i32 6
- %r7 = insertelement <16 x i8> %v, i8 %e, i32 7
- ret <16 x i8> %r7
-}
-
-; CHECK-NEXT: define internal <16 x i8> @InsertV16xi8(<16 x i8> %v, i32 %pe) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %e = trunc i32 %pe to i8
-; CHECK-NEXT: %r0 = insertelement <16 x i8> %v, i8 %e, i32 0
-; CHECK-NEXT: %r1 = insertelement <16 x i8> %v, i8 %e, i32 1
-; CHECK-NEXT: %r2 = insertelement <16 x i8> %v, i8 %e, i32 2
-; CHECK-NEXT: %r3 = insertelement <16 x i8> %v, i8 %e, i32 3
-; CHECK-NEXT: %r4 = insertelement <16 x i8> %v, i8 %e, i32 4
-; CHECK-NEXT: %r5 = insertelement <16 x i8> %v, i8 %e, i32 5
-; CHECK-NEXT: %r6 = insertelement <16 x i8> %v, i8 %e, i32 6
-; CHECK-NEXT: %r7 = insertelement <16 x i8> %v, i8 %e, i32 7
-; CHECK-NEXT: ret <16 x i8> %r7
-; CHECK-NEXT: }
-
-define internal <8 x i16> @InsertV8xi16(<8 x i16> %v, i32 %pe) {
-entry:
- %e = trunc i32 %pe to i16
- %r0 = insertelement <8 x i16> %v, i16 %e, i32 0
- %r1 = insertelement <8 x i16> %v, i16 %e, i32 1
- %r2 = insertelement <8 x i16> %v, i16 %e, i32 2
- %r3 = insertelement <8 x i16> %v, i16 %e, i32 3
- %r4 = insertelement <8 x i16> %v, i16 %e, i32 4
- %r5 = insertelement <8 x i16> %v, i16 %e, i32 5
- %r6 = insertelement <8 x i16> %v, i16 %e, i32 6
- %r7 = insertelement <8 x i16> %v, i16 %e, i32 7
- ret <8 x i16> %r7
-}
-
-; CHECK-NEXT: define internal <8 x i16> @InsertV8xi16(<8 x i16> %v, i32 %pe) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %e = trunc i32 %pe to i16
-; CHECK-NEXT: %r0 = insertelement <8 x i16> %v, i16 %e, i32 0
-; CHECK-NEXT: %r1 = insertelement <8 x i16> %v, i16 %e, i32 1
-; CHECK-NEXT: %r2 = insertelement <8 x i16> %v, i16 %e, i32 2
-; CHECK-NEXT: %r3 = insertelement <8 x i16> %v, i16 %e, i32 3
-; CHECK-NEXT: %r4 = insertelement <8 x i16> %v, i16 %e, i32 4
-; CHECK-NEXT: %r5 = insertelement <8 x i16> %v, i16 %e, i32 5
-; CHECK-NEXT: %r6 = insertelement <8 x i16> %v, i16 %e, i32 6
-; CHECK-NEXT: %r7 = insertelement <8 x i16> %v, i16 %e, i32 7
-; CHECK-NEXT: ret <8 x i16> %r7
-; CHECK-NEXT: }
-
-define internal <4 x i32> @InsertV4xi32(<4 x i32> %v, i32 %e) {
-entry:
- %r0 = insertelement <4 x i32> %v, i32 %e, i32 0
- %r1 = insertelement <4 x i32> %v, i32 %e, i32 1
- %r2 = insertelement <4 x i32> %v, i32 %e, i32 2
- %r3 = insertelement <4 x i32> %v, i32 %e, i32 3
- ret <4 x i32> %r3
-}
-
-; CHECK-NEXT: define internal <4 x i32> @InsertV4xi32(<4 x i32> %v, i32 %e) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %r0 = insertelement <4 x i32> %v, i32 %e, i32 0
-; CHECK-NEXT: %r1 = insertelement <4 x i32> %v, i32 %e, i32 1
-; CHECK-NEXT: %r2 = insertelement <4 x i32> %v, i32 %e, i32 2
-; CHECK-NEXT: %r3 = insertelement <4 x i32> %v, i32 %e, i32 3
-; CHECK-NEXT: ret <4 x i32> %r3
-; CHECK-NEXT: }
-
-define internal <4 x float> @InsertV4xfloat(<4 x float> %v, float %e) {
-entry:
- %r0 = insertelement <4 x float> %v, float %e, i32 0
- %r1 = insertelement <4 x float> %v, float %e, i32 1
- %r2 = insertelement <4 x float> %v, float %e, i32 2
- %r3 = insertelement <4 x float> %v, float %e, i32 3
- ret <4 x float> %r3
-}
-
-; CHECK-NEXT: define internal <4 x float> @InsertV4xfloat(<4 x float> %v, float %e) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %r0 = insertelement <4 x float> %v, float %e, i32 0
-; CHECK-NEXT: %r1 = insertelement <4 x float> %v, float %e, i32 1
-; CHECK-NEXT: %r2 = insertelement <4 x float> %v, float %e, i32 2
-; CHECK-NEXT: %r3 = insertelement <4 x float> %v, float %e, i32 3
-; CHECK-NEXT: ret <4 x float> %r3
-; CHECK-NEXT: }
-
-; NOIR: Total across all functions
diff --git a/third_party/subzero/tests_lit/reader_tests/lit.local.cfg b/third_party/subzero/tests_lit/reader_tests/lit.local.cfg
deleted file mode 100644
index 7781f86..0000000
--- a/third_party/subzero/tests_lit/reader_tests/lit.local.cfg
+++ /dev/null
@@ -1,7 +0,0 @@
-# -*- Python -*-
-#
-# This directory contains reader tests that require the ability to dump parsed
-# IR.
-
-if not 'allow_dump' in config.root.available_features:
- config.unsupported = True
diff --git a/third_party/subzero/tests_lit/reader_tests/load.ll b/third_party/subzero/tests_lit/reader_tests/load.ll
deleted file mode 100644
index 0d15992..0000000
--- a/third_party/subzero/tests_lit/reader_tests/load.ll
+++ /dev/null
@@ -1,149 +0,0 @@
-; Test if we can read load instructions.
-
-; RUN: %p2i --no-local-syms -i %s --insts | FileCheck %s
-; RUN: %p2i -i %s --args -notranslate -timing | \
-; RUN: FileCheck --check-prefix=NOIR %s
-
-define internal i32 @load_i8(i32 %addr) {
-entry:
- %addr_i8 = inttoptr i32 %addr to i8*
- %v = load i8, i8* %addr_i8, align 1
- %r = sext i8 %v to i32
- ret i32 %r
-
-; CHECK: __0:
-; CHECK-NEXT: %__1 = load i8, i8* %__0, align 1
-; CHECK-NEXT: %__2 = sext i8 %__1 to i32
-; CHECK-NEXT: ret i32 %__2
-}
-
-define internal i32 @load_i16(i32 %addr) {
-entry:
- %addr_i16 = inttoptr i32 %addr to i16*
- %v = load i16, i16* %addr_i16, align 1
- %r = sext i16 %v to i32
- ret i32 %r
-
-; CHECK: __0:
-; CHECK-NEXT: %__1 = load i16, i16* %__0, align 1
-; CHECK-NEXT: %__2 = sext i16 %__1 to i32
-; CHECK-NEXT: ret i32 %__2
-}
-
-define internal i32 @load_i32(i32 %addr) {
-entry:
- %addr_i32 = inttoptr i32 %addr to i32*
- %v = load i32, i32* %addr_i32, align 1
- ret i32 %v
-
-; CHECK: __0:
-; CHECK-NEXT: %__1 = load i32, i32* %__0, align 1
-; CHECK-NEXT: ret i32 %__1
-}
-
-define internal i64 @load_i64(i32 %addr) {
-entry:
- %addr_i64 = inttoptr i32 %addr to i64*
- %v = load i64, i64* %addr_i64, align 1
- ret i64 %v
-
-; CHECK: __0:
-; CHECK-NEXT: %__1 = load i64, i64* %__0, align 1
-; CHECK-NEXT: ret i64 %__1
-}
-
-define internal float @load_float_a1(i32 %addr) {
-entry:
- %addr_float = inttoptr i32 %addr to float*
- %v = load float, float* %addr_float, align 1
- ret float %v
-
-; TODO(kschimpf) Fix load alignment in ICE to allow non-default.
-
-; CHECK: __0:
-; CHECK-NEXT: %__1 = load float, float* %__0, align 4
-; CHECK-NEXT: ret float %__1
-}
-
-
-define internal float @load_float_a4(i32 %addr) {
-entry:
- %addr_float = inttoptr i32 %addr to float*
- %v = load float, float* %addr_float, align 4
- ret float %v
-
-; CHECK: __0:
-; CHECK-NEXT: %__1 = load float, float* %__0, align 4
-; CHECK-NEXT: ret float %__1
-}
-
-define internal double @load_double_a1(i32 %addr) {
-entry:
- %addr_double = inttoptr i32 %addr to double*
- %v = load double, double* %addr_double, align 1
- ret double %v
-
-; TODO(kschimpf) Fix load alignment in ICE to allow non-default.
-
-; CHECK: __0:
-; CHECK-NEXT: %__1 = load double, double* %__0, align 8
-; CHECK-NEXT: ret double %__1
-}
-
-
-define internal double @load_double_a8(i32 %addr) {
-entry:
- %addr_double = inttoptr i32 %addr to double*
- %v = load double, double* %addr_double, align 8
- ret double %v
-
-; CHECK: __0:
-; CHECK-NEXT: %__1 = load double, double* %__0, align 8
-; CHECK-NEXT: ret double %__1
-}
-
-define internal <16 x i8> @load_v16xI8(i32 %addr) {
-entry:
- %addr_v16xI8 = inttoptr i32 %addr to <16 x i8>*
- %v = load <16 x i8>, <16 x i8>* %addr_v16xI8, align 1
- ret <16 x i8> %v
-
-; CHECK: __0:
-; CHECK-NEXT: %__1 = load <16 x i8>, <16 x i8>* %__0, align 1
-; CHECK-NEXT: ret <16 x i8> %__1
-}
-
-define internal <8 x i16> @load_v8xI16(i32 %addr) {
-entry:
- %addr_v8xI16 = inttoptr i32 %addr to <8 x i16>*
- %v = load <8 x i16>, <8 x i16>* %addr_v8xI16, align 2
- ret <8 x i16> %v
-
-; CHECK: __0:
-; CHECK-NEXT: %__1 = load <8 x i16>, <8 x i16>* %__0, align 2
-; CHECK-NEXT: ret <8 x i16> %__1
-}
-
-define internal <4 x i32> @load_v4xI32(i32 %addr) {
-entry:
- %addr_v4xI32 = inttoptr i32 %addr to <4 x i32>*
- %v = load <4 x i32>, <4 x i32>* %addr_v4xI32, align 4
- ret <4 x i32> %v
-
-; CHECK: __0:
-; CHECK-NEXT: %__1 = load <4 x i32>, <4 x i32>* %__0, align 4
-; CHECK-NEXT: ret <4 x i32> %__1
-}
-
-define internal <4 x float> @load_v4xFloat(i32 %addr) {
-entry:
- %addr_v4xFloat = inttoptr i32 %addr to <4 x float>*
- %v = load <4 x float>, <4 x float>* %addr_v4xFloat, align 4
- ret <4 x float> %v
-
-; CHECK: __0:
-; CHECK-NEXT: %__1 = load <4 x float>, <4 x float>* %__0, align 4
-; CHECK-NEXT: ret <4 x float> %__1
-}
-
-; NOIR: Total across all functions
diff --git a/third_party/subzero/tests_lit/reader_tests/nacl-atomic-intrinsics.ll b/third_party/subzero/tests_lit/reader_tests/nacl-atomic-intrinsics.ll
deleted file mode 100644
index e0db3a2..0000000
--- a/third_party/subzero/tests_lit/reader_tests/nacl-atomic-intrinsics.ll
+++ /dev/null
@@ -1,643 +0,0 @@
-; Test parsing NaCl atomic instructions.
-
-; RUN: %p2i -i %s --insts | FileCheck %s
-; RUN: %p2i -i %s --args -notranslate -timing | \
-; RUN: FileCheck --check-prefix=NOIR %s
-
-declare i8 @llvm.nacl.atomic.load.i8(i8*, i32)
-declare i16 @llvm.nacl.atomic.load.i16(i16*, i32)
-declare i32 @llvm.nacl.atomic.load.i32(i32*, i32)
-declare i64 @llvm.nacl.atomic.load.i64(i64*, i32)
-declare void @llvm.nacl.atomic.store.i8(i8, i8*, i32)
-declare void @llvm.nacl.atomic.store.i16(i16, i16*, i32)
-declare void @llvm.nacl.atomic.store.i32(i32, i32*, i32)
-declare void @llvm.nacl.atomic.store.i64(i64, i64*, i32)
-declare i8 @llvm.nacl.atomic.rmw.i8(i32, i8*, i8, i32)
-declare i16 @llvm.nacl.atomic.rmw.i16(i32, i16*, i16, i32)
-declare i32 @llvm.nacl.atomic.rmw.i32(i32, i32*, i32, i32)
-declare i64 @llvm.nacl.atomic.rmw.i64(i32, i64*, i64, i32)
-declare i8 @llvm.nacl.atomic.cmpxchg.i8(i8*, i8, i8, i32, i32)
-declare i16 @llvm.nacl.atomic.cmpxchg.i16(i16*, i16, i16, i32, i32)
-declare i32 @llvm.nacl.atomic.cmpxchg.i32(i32*, i32, i32, i32, i32)
-declare i64 @llvm.nacl.atomic.cmpxchg.i64(i64*, i64, i64, i32, i32)
-declare void @llvm.nacl.atomic.fence(i32)
-declare void @llvm.nacl.atomic.fence.all()
-declare i1 @llvm.nacl.atomic.is.lock.free(i32, i8*)
-
-;;; Load
-
-define internal i32 @test_atomic_load_8(i32 %iptr) {
-entry:
- %ptr = inttoptr i32 %iptr to i8*
- ; parameter value "6" is for the sequential consistency memory order.
- %i = call i8 @llvm.nacl.atomic.load.i8(i8* %ptr, i32 6)
- %r = zext i8 %i to i32
- ret i32 %r
-}
-
-; CHECK: define internal i32 @test_atomic_load_8(i32 %iptr) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %i = call i8 @llvm.nacl.atomic.load.i8(i32 %iptr, i32 6)
-; CHECK-NEXT: %r = zext i8 %i to i32
-; CHECK-NEXT: ret i32 %r
-; CHECK-NEXT: }
-
-define internal i32 @test_atomic_load_16(i32 %iptr) {
-entry:
- %ptr = inttoptr i32 %iptr to i16*
- %i = call i16 @llvm.nacl.atomic.load.i16(i16* %ptr, i32 6)
- %r = zext i16 %i to i32
- ret i32 %r
-}
-
-; CHECK-NEXT: define internal i32 @test_atomic_load_16(i32 %iptr) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %i = call i16 @llvm.nacl.atomic.load.i16(i32 %iptr, i32 6)
-; CHECK-NEXT: %r = zext i16 %i to i32
-; CHECK-NEXT: ret i32 %r
-; CHECK-NEXT: }
-
-define internal i32 @test_atomic_load_32(i32 %iptr) {
-entry:
- %ptr = inttoptr i32 %iptr to i32*
- %r = call i32 @llvm.nacl.atomic.load.i32(i32* %ptr, i32 6)
- ret i32 %r
-}
-
-; CHECK-NEXT: define internal i32 @test_atomic_load_32(i32 %iptr) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %r = call i32 @llvm.nacl.atomic.load.i32(i32 %iptr, i32 6)
-; CHECK-NEXT: ret i32 %r
-; CHECK-NEXT: }
-
-define internal i64 @test_atomic_load_64(i32 %iptr) {
-entry:
- %ptr = inttoptr i32 %iptr to i64*
- %r = call i64 @llvm.nacl.atomic.load.i64(i64* %ptr, i32 6)
- ret i64 %r
-}
-
-; CHECK-NEXT: define internal i64 @test_atomic_load_64(i32 %iptr) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %r = call i64 @llvm.nacl.atomic.load.i64(i32 %iptr, i32 6)
-; CHECK-NEXT: ret i64 %r
-; CHECK-NEXT: }
-
-;;; Store
-
-define internal void @test_atomic_store_8(i32 %iptr, i32 %v) {
-entry:
- %truncv = trunc i32 %v to i8
- %ptr = inttoptr i32 %iptr to i8*
- call void @llvm.nacl.atomic.store.i8(i8 %truncv, i8* %ptr, i32 6)
- ret void
-}
-
-; CHECK-NEXT: define internal void @test_atomic_store_8(i32 %iptr, i32 %v) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %truncv = trunc i32 %v to i8
-; CHECK-NEXT: call void @llvm.nacl.atomic.store.i8(i8 %truncv, i32 %iptr, i32 6)
-; CHECK-NEXT: ret void
-; CHECK-NEXT: }
-
-define internal void @test_atomic_store_16(i32 %iptr, i32 %v) {
-entry:
- %truncv = trunc i32 %v to i16
- %ptr = inttoptr i32 %iptr to i16*
- call void @llvm.nacl.atomic.store.i16(i16 %truncv, i16* %ptr, i32 6)
- ret void
-}
-
-; CHECK-NEXT: define internal void @test_atomic_store_16(i32 %iptr, i32 %v) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %truncv = trunc i32 %v to i16
-; CHECK-NEXT: call void @llvm.nacl.atomic.store.i16(i16 %truncv, i32 %iptr, i32 6)
-; CHECK-NEXT: ret void
-; CHECK-NEXT: }
-
-define internal void @test_atomic_store_32(i32 %iptr, i32 %v) {
-entry:
- %ptr = inttoptr i32 %iptr to i32*
- call void @llvm.nacl.atomic.store.i32(i32 %v, i32* %ptr, i32 6)
- ret void
-}
-
-; CHECK-NEXT: define internal void @test_atomic_store_32(i32 %iptr, i32 %v) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: call void @llvm.nacl.atomic.store.i32(i32 %v, i32 %iptr, i32 6)
-; CHECK-NEXT: ret void
-; CHECK-NEXT: }
-
-define internal void @test_atomic_store_64(i32 %iptr, i64 %v) {
-entry:
- %ptr = inttoptr i32 %iptr to i64*
- call void @llvm.nacl.atomic.store.i64(i64 %v, i64* %ptr, i32 6)
- ret void
-}
-
-; CHECK-NEXT: define internal void @test_atomic_store_64(i32 %iptr, i64 %v) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: call void @llvm.nacl.atomic.store.i64(i64 %v, i32 %iptr, i32 6)
-; CHECK-NEXT: ret void
-; CHECK-NEXT: }
-
-define internal void @test_atomic_store_64_const(i32 %iptr) {
-entry:
- %ptr = inttoptr i32 %iptr to i64*
- call void @llvm.nacl.atomic.store.i64(i64 12345678901234, i64* %ptr, i32 6)
- ret void
-}
-
-; CHECK-NEXT: define internal void @test_atomic_store_64_const(i32 %iptr) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: call void @llvm.nacl.atomic.store.i64(i64 12345678901234, i32 %iptr, i32 6)
-; CHECK-NEXT: ret void
-; CHECK-NEXT: }
-
-;;; RMW
-
-;; add
-
-define internal i32 @test_atomic_rmw_add_8(i32 %iptr, i32 %v) {
-entry:
- %trunc = trunc i32 %v to i8
- %ptr = inttoptr i32 %iptr to i8*
- ; "1" is an atomic add, and "6" is sequential consistency.
- %a = call i8 @llvm.nacl.atomic.rmw.i8(i32 1, i8* %ptr, i8 %trunc, i32 6)
- %a_ext = zext i8 %a to i32
- ret i32 %a_ext
-}
-
-; CHECK-NEXT: define internal i32 @test_atomic_rmw_add_8(i32 %iptr, i32 %v) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %trunc = trunc i32 %v to i8
-; CHECK-NEXT: %a = call i8 @llvm.nacl.atomic.rmw.i8(i32 1, i32 %iptr, i8 %trunc, i32 6)
-; CHECK-NEXT: %a_ext = zext i8 %a to i32
-; CHECK-NEXT: ret i32 %a_ext
-; CHECK-NEXT: }
-
-define internal i32 @test_atomic_rmw_add_16(i32 %iptr, i32 %v) {
-entry:
- %trunc = trunc i32 %v to i16
- %ptr = inttoptr i32 %iptr to i16*
- %a = call i16 @llvm.nacl.atomic.rmw.i16(i32 1, i16* %ptr, i16 %trunc, i32 6)
- %a_ext = zext i16 %a to i32
- ret i32 %a_ext
-}
-
-; CHECK-NEXT: define internal i32 @test_atomic_rmw_add_16(i32 %iptr, i32 %v) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %trunc = trunc i32 %v to i16
-; CHECK-NEXT: %a = call i16 @llvm.nacl.atomic.rmw.i16(i32 1, i32 %iptr, i16 %trunc, i32 6)
-; CHECK-NEXT: %a_ext = zext i16 %a to i32
-; CHECK-NEXT: ret i32 %a_ext
-; CHECK-NEXT: }
-
-define internal i32 @test_atomic_rmw_add_32(i32 %iptr, i32 %v) {
-entry:
- %ptr = inttoptr i32 %iptr to i32*
- %a = call i32 @llvm.nacl.atomic.rmw.i32(i32 1, i32* %ptr, i32 %v, i32 6)
- ret i32 %a
-}
-
-; CHECK-NEXT: define internal i32 @test_atomic_rmw_add_32(i32 %iptr, i32 %v) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %a = call i32 @llvm.nacl.atomic.rmw.i32(i32 1, i32 %iptr, i32 %v, i32 6)
-; CHECK-NEXT: ret i32 %a
-; CHECK-NEXT: }
-
-define internal i64 @test_atomic_rmw_add_64(i32 %iptr, i64 %v) {
-entry:
- %ptr = inttoptr i32 %iptr to i64*
- %a = call i64 @llvm.nacl.atomic.rmw.i64(i32 1, i64* %ptr, i64 %v, i32 6)
- ret i64 %a
-}
-
-; CHECK-NEXT: define internal i64 @test_atomic_rmw_add_64(i32 %iptr, i64 %v) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %a = call i64 @llvm.nacl.atomic.rmw.i64(i32 1, i32 %iptr, i64 %v, i32 6)
-; CHECK-NEXT: ret i64 %a
-; CHECK-NEXT: }
-
-;; sub
-
-define internal i32 @test_atomic_rmw_sub_8(i32 %iptr, i32 %v) {
-entry:
- %trunc = trunc i32 %v to i8
- %ptr = inttoptr i32 %iptr to i8*
- %a = call i8 @llvm.nacl.atomic.rmw.i8(i32 2, i8* %ptr, i8 %trunc, i32 6)
- %a_ext = zext i8 %a to i32
- ret i32 %a_ext
-}
-
-; CHECK-NEXT: define internal i32 @test_atomic_rmw_sub_8(i32 %iptr, i32 %v) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %trunc = trunc i32 %v to i8
-; CHECK-NEXT: %a = call i8 @llvm.nacl.atomic.rmw.i8(i32 2, i32 %iptr, i8 %trunc, i32 6)
-; CHECK-NEXT: %a_ext = zext i8 %a to i32
-; CHECK-NEXT: ret i32 %a_ext
-; CHECK-NEXT: }
-
-define internal i32 @test_atomic_rmw_sub_16(i32 %iptr, i32 %v) {
-entry:
- %trunc = trunc i32 %v to i16
- %ptr = inttoptr i32 %iptr to i16*
- %a = call i16 @llvm.nacl.atomic.rmw.i16(i32 2, i16* %ptr, i16 %trunc, i32 6)
- %a_ext = zext i16 %a to i32
- ret i32 %a_ext
-}
-
-; CHECK-NEXT: define internal i32 @test_atomic_rmw_sub_16(i32 %iptr, i32 %v) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %trunc = trunc i32 %v to i16
-; CHECK-NEXT: %a = call i16 @llvm.nacl.atomic.rmw.i16(i32 2, i32 %iptr, i16 %trunc, i32 6)
-; CHECK-NEXT: %a_ext = zext i16 %a to i32
-; CHECK-NEXT: ret i32 %a_ext
-; CHECK-NEXT: }
-
-define internal i32 @test_atomic_rmw_sub_32(i32 %iptr, i32 %v) {
-entry:
- %ptr = inttoptr i32 %iptr to i32*
- %a = call i32 @llvm.nacl.atomic.rmw.i32(i32 2, i32* %ptr, i32 %v, i32 6)
- ret i32 %a
-}
-
-; CHECK-NEXT: define internal i32 @test_atomic_rmw_sub_32(i32 %iptr, i32 %v) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %a = call i32 @llvm.nacl.atomic.rmw.i32(i32 2, i32 %iptr, i32 %v, i32 6)
-; CHECK-NEXT: ret i32 %a
-; CHECK-NEXT: }
-
-define internal i64 @test_atomic_rmw_sub_64(i32 %iptr, i64 %v) {
-entry:
- %ptr = inttoptr i32 %iptr to i64*
- %a = call i64 @llvm.nacl.atomic.rmw.i64(i32 2, i64* %ptr, i64 %v, i32 6)
- ret i64 %a
-}
-
-; CHECK-NEXT: define internal i64 @test_atomic_rmw_sub_64(i32 %iptr, i64 %v) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %a = call i64 @llvm.nacl.atomic.rmw.i64(i32 2, i32 %iptr, i64 %v, i32 6)
-; CHECK-NEXT: ret i64 %a
-; CHECK-NEXT: }
-
-;; or
-
-define internal i32 @test_atomic_rmw_or_8(i32 %iptr, i32 %v) {
-entry:
- %trunc = trunc i32 %v to i8
- %ptr = inttoptr i32 %iptr to i8*
- %a = call i8 @llvm.nacl.atomic.rmw.i8(i32 3, i8* %ptr, i8 %trunc, i32 6)
- %a_ext = zext i8 %a to i32
- ret i32 %a_ext
-}
-
-; CHECK-NEXT: define internal i32 @test_atomic_rmw_or_8(i32 %iptr, i32 %v) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %trunc = trunc i32 %v to i8
-; CHECK-NEXT: %a = call i8 @llvm.nacl.atomic.rmw.i8(i32 3, i32 %iptr, i8 %trunc, i32 6)
-; CHECK-NEXT: %a_ext = zext i8 %a to i32
-; CHECK-NEXT: ret i32 %a_ext
-; CHECK-NEXT: }
-
-define internal i32 @test_atomic_rmw_or_16(i32 %iptr, i32 %v) {
-entry:
- %trunc = trunc i32 %v to i16
- %ptr = inttoptr i32 %iptr to i16*
- %a = call i16 @llvm.nacl.atomic.rmw.i16(i32 3, i16* %ptr, i16 %trunc, i32 6)
- %a_ext = zext i16 %a to i32
- ret i32 %a_ext
-}
-
-; CHECK-NEXT: define internal i32 @test_atomic_rmw_or_16(i32 %iptr, i32 %v) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %trunc = trunc i32 %v to i16
-; CHECK-NEXT: %a = call i16 @llvm.nacl.atomic.rmw.i16(i32 3, i32 %iptr, i16 %trunc, i32 6)
-; CHECK-NEXT: %a_ext = zext i16 %a to i32
-; CHECK-NEXT: ret i32 %a_ext
-; CHECK-NEXT: }
-
-define internal i32 @test_atomic_rmw_or_32(i32 %iptr, i32 %v) {
-entry:
- %ptr = inttoptr i32 %iptr to i32*
- %a = call i32 @llvm.nacl.atomic.rmw.i32(i32 3, i32* %ptr, i32 %v, i32 6)
- ret i32 %a
-}
-
-; CHECK-NEXT: define internal i32 @test_atomic_rmw_or_32(i32 %iptr, i32 %v) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %a = call i32 @llvm.nacl.atomic.rmw.i32(i32 3, i32 %iptr, i32 %v, i32 6)
-; CHECK-NEXT: ret i32 %a
-; CHECK-NEXT: }
-
-define internal i64 @test_atomic_rmw_or_64(i32 %iptr, i64 %v) {
-entry:
- %ptr = inttoptr i32 %iptr to i64*
- %a = call i64 @llvm.nacl.atomic.rmw.i64(i32 3, i64* %ptr, i64 %v, i32 6)
- ret i64 %a
-}
-
-; CHECK-NEXT: define internal i64 @test_atomic_rmw_or_64(i32 %iptr, i64 %v) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %a = call i64 @llvm.nacl.atomic.rmw.i64(i32 3, i32 %iptr, i64 %v, i32 6)
-; CHECK-NEXT: ret i64 %a
-; CHECK-NEXT: }
-
-;; and
-
-define internal i32 @test_atomic_rmw_and_8(i32 %iptr, i32 %v) {
-entry:
- %trunc = trunc i32 %v to i8
- %ptr = inttoptr i32 %iptr to i8*
- %a = call i8 @llvm.nacl.atomic.rmw.i8(i32 4, i8* %ptr, i8 %trunc, i32 6)
- %a_ext = zext i8 %a to i32
- ret i32 %a_ext
-}
-
-; CHECK-NEXT: define internal i32 @test_atomic_rmw_and_8(i32 %iptr, i32 %v) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %trunc = trunc i32 %v to i8
-; CHECK-NEXT: %a = call i8 @llvm.nacl.atomic.rmw.i8(i32 4, i32 %iptr, i8 %trunc, i32 6)
-; CHECK-NEXT: %a_ext = zext i8 %a to i32
-; CHECK-NEXT: ret i32 %a_ext
-; CHECK-NEXT: }
-
-define internal i32 @test_atomic_rmw_and_16(i32 %iptr, i32 %v) {
-entry:
- %trunc = trunc i32 %v to i16
- %ptr = inttoptr i32 %iptr to i16*
- %a = call i16 @llvm.nacl.atomic.rmw.i16(i32 4, i16* %ptr, i16 %trunc, i32 6)
- %a_ext = zext i16 %a to i32
- ret i32 %a_ext
-}
-
-; CHECK-NEXT: define internal i32 @test_atomic_rmw_and_16(i32 %iptr, i32 %v) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %trunc = trunc i32 %v to i16
-; CHECK-NEXT: %a = call i16 @llvm.nacl.atomic.rmw.i16(i32 4, i32 %iptr, i16 %trunc, i32 6)
-; CHECK-NEXT: %a_ext = zext i16 %a to i32
-; CHECK-NEXT: ret i32 %a_ext
-; CHECK-NEXT: }
-
-define internal i32 @test_atomic_rmw_and_32(i32 %iptr, i32 %v) {
-entry:
- %ptr = inttoptr i32 %iptr to i32*
- %a = call i32 @llvm.nacl.atomic.rmw.i32(i32 4, i32* %ptr, i32 %v, i32 6)
- ret i32 %a
-}
-
-; CHECK-NEXT: define internal i32 @test_atomic_rmw_and_32(i32 %iptr, i32 %v) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %a = call i32 @llvm.nacl.atomic.rmw.i32(i32 4, i32 %iptr, i32 %v, i32 6)
-; CHECK-NEXT: ret i32 %a
-; CHECK-NEXT: }
-
-define internal i64 @test_atomic_rmw_and_64(i32 %iptr, i64 %v) {
-entry:
- %ptr = inttoptr i32 %iptr to i64*
- %a = call i64 @llvm.nacl.atomic.rmw.i64(i32 4, i64* %ptr, i64 %v, i32 6)
- ret i64 %a
-}
-
-; CHECK-NEXT: define internal i64 @test_atomic_rmw_and_64(i32 %iptr, i64 %v) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %a = call i64 @llvm.nacl.atomic.rmw.i64(i32 4, i32 %iptr, i64 %v, i32 6)
-; CHECK-NEXT: ret i64 %a
-; CHECK-NEXT: }
-
-;; xor
-
-define internal i32 @test_atomic_rmw_xor_8(i32 %iptr, i32 %v) {
-entry:
- %trunc = trunc i32 %v to i8
- %ptr = inttoptr i32 %iptr to i8*
- %a = call i8 @llvm.nacl.atomic.rmw.i8(i32 5, i8* %ptr, i8 %trunc, i32 6)
- %a_ext = zext i8 %a to i32
- ret i32 %a_ext
-}
-
-; CHECK-NEXT: define internal i32 @test_atomic_rmw_xor_8(i32 %iptr, i32 %v) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %trunc = trunc i32 %v to i8
-; CHECK-NEXT: %a = call i8 @llvm.nacl.atomic.rmw.i8(i32 5, i32 %iptr, i8 %trunc, i32 6)
-; CHECK-NEXT: %a_ext = zext i8 %a to i32
-; CHECK-NEXT: ret i32 %a_ext
-; CHECK-NEXT: }
-
-define internal i32 @test_atomic_rmw_xor_16(i32 %iptr, i32 %v) {
-entry:
- %trunc = trunc i32 %v to i16
- %ptr = inttoptr i32 %iptr to i16*
- %a = call i16 @llvm.nacl.atomic.rmw.i16(i32 5, i16* %ptr, i16 %trunc, i32 6)
- %a_ext = zext i16 %a to i32
- ret i32 %a_ext
-}
-
-; CHECK-NEXT: define internal i32 @test_atomic_rmw_xor_16(i32 %iptr, i32 %v) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %trunc = trunc i32 %v to i16
-; CHECK-NEXT: %a = call i16 @llvm.nacl.atomic.rmw.i16(i32 5, i32 %iptr, i16 %trunc, i32 6)
-; CHECK-NEXT: %a_ext = zext i16 %a to i32
-; CHECK-NEXT: ret i32 %a_ext
-; CHECK-NEXT: }
-
-define internal i32 @test_atomic_rmw_xor_32(i32 %iptr, i32 %v) {
-entry:
- %ptr = inttoptr i32 %iptr to i32*
- %a = call i32 @llvm.nacl.atomic.rmw.i32(i32 5, i32* %ptr, i32 %v, i32 6)
- ret i32 %a
-}
-
-; CHECK-NEXT: define internal i32 @test_atomic_rmw_xor_32(i32 %iptr, i32 %v) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %a = call i32 @llvm.nacl.atomic.rmw.i32(i32 5, i32 %iptr, i32 %v, i32 6)
-; CHECK-NEXT: ret i32 %a
-; CHECK-NEXT: }
-
-define internal i64 @test_atomic_rmw_xor_64(i32 %iptr, i64 %v) {
-entry:
- %ptr = inttoptr i32 %iptr to i64*
- %a = call i64 @llvm.nacl.atomic.rmw.i64(i32 5, i64* %ptr, i64 %v, i32 6)
- ret i64 %a
-}
-
-; CHECK-NEXT: define internal i64 @test_atomic_rmw_xor_64(i32 %iptr, i64 %v) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %a = call i64 @llvm.nacl.atomic.rmw.i64(i32 5, i32 %iptr, i64 %v, i32 6)
-; CHECK-NEXT: ret i64 %a
-; CHECK-NEXT: }
-
-;; exchange
-
-define internal i32 @test_atomic_rmw_xchg_8(i32 %iptr, i32 %v) {
-entry:
- %trunc = trunc i32 %v to i8
- %ptr = inttoptr i32 %iptr to i8*
- %a = call i8 @llvm.nacl.atomic.rmw.i8(i32 6, i8* %ptr, i8 %trunc, i32 6)
- %a_ext = zext i8 %a to i32
- ret i32 %a_ext
-}
-
-; CHECK-NEXT: define internal i32 @test_atomic_rmw_xchg_8(i32 %iptr, i32 %v) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %trunc = trunc i32 %v to i8
-; CHECK-NEXT: %a = call i8 @llvm.nacl.atomic.rmw.i8(i32 6, i32 %iptr, i8 %trunc, i32 6)
-; CHECK-NEXT: %a_ext = zext i8 %a to i32
-; CHECK-NEXT: ret i32 %a_ext
-; CHECK-NEXT: }
-
-define internal i32 @test_atomic_rmw_xchg_16(i32 %iptr, i32 %v) {
-entry:
- %trunc = trunc i32 %v to i16
- %ptr = inttoptr i32 %iptr to i16*
- %a = call i16 @llvm.nacl.atomic.rmw.i16(i32 6, i16* %ptr, i16 %trunc, i32 6)
- %a_ext = zext i16 %a to i32
- ret i32 %a_ext
-}
-
-; CHECK-NEXT: define internal i32 @test_atomic_rmw_xchg_16(i32 %iptr, i32 %v) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %trunc = trunc i32 %v to i16
-; CHECK-NEXT: %a = call i16 @llvm.nacl.atomic.rmw.i16(i32 6, i32 %iptr, i16 %trunc, i32 6)
-; CHECK-NEXT: %a_ext = zext i16 %a to i32
-; CHECK-NEXT: ret i32 %a_ext
-; CHECK-NEXT: }
-
-define internal i32 @test_atomic_rmw_xchg_32(i32 %iptr, i32 %v) {
-entry:
- %ptr = inttoptr i32 %iptr to i32*
- %a = call i32 @llvm.nacl.atomic.rmw.i32(i32 6, i32* %ptr, i32 %v, i32 6)
- ret i32 %a
-}
-
-; CHECK-NEXT: define internal i32 @test_atomic_rmw_xchg_32(i32 %iptr, i32 %v) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %a = call i32 @llvm.nacl.atomic.rmw.i32(i32 6, i32 %iptr, i32 %v, i32 6)
-; CHECK-NEXT: ret i32 %a
-; CHECK-NEXT: }
-
-define internal i64 @test_atomic_rmw_xchg_64(i32 %iptr, i64 %v) {
-entry:
- %ptr = inttoptr i32 %iptr to i64*
- %a = call i64 @llvm.nacl.atomic.rmw.i64(i32 6, i64* %ptr, i64 %v, i32 6)
- ret i64 %a
-}
-
-; CHECK-NEXT: define internal i64 @test_atomic_rmw_xchg_64(i32 %iptr, i64 %v) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %a = call i64 @llvm.nacl.atomic.rmw.i64(i32 6, i32 %iptr, i64 %v, i32 6)
-; CHECK-NEXT: ret i64 %a
-; CHECK-NEXT: }
-
-;;;; Cmpxchg
-
-define internal i32 @test_atomic_cmpxchg_8(i32 %iptr, i32 %expected, i32 %desired) {
-entry:
- %trunc_exp = trunc i32 %expected to i8
- %trunc_des = trunc i32 %desired to i8
- %ptr = inttoptr i32 %iptr to i8*
- %old = call i8 @llvm.nacl.atomic.cmpxchg.i8(i8* %ptr, i8 %trunc_exp,
- i8 %trunc_des, i32 6, i32 6)
- %old_ext = zext i8 %old to i32
- ret i32 %old_ext
-}
-
-; CHECK-NEXT: define internal i32 @test_atomic_cmpxchg_8(i32 %iptr, i32 %expected, i32 %desired) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %trunc_exp = trunc i32 %expected to i8
-; CHECK-NEXT: %trunc_des = trunc i32 %desired to i8
-; CHECK-NEXT: %old = call i8 @llvm.nacl.atomic.cmpxchg.i8(i32 %iptr, i8 %trunc_exp, i8 %trunc_des, i32 6, i32 6)
-; CHECK-NEXT: %old_ext = zext i8 %old to i32
-; CHECK-NEXT: ret i32 %old_ext
-; CHECK-NEXT: }
-
-define internal i32 @test_atomic_cmpxchg_16(i32 %iptr, i32 %expected, i32 %desired) {
-entry:
- %trunc_exp = trunc i32 %expected to i16
- %trunc_des = trunc i32 %desired to i16
- %ptr = inttoptr i32 %iptr to i16*
- %old = call i16 @llvm.nacl.atomic.cmpxchg.i16(i16* %ptr, i16 %trunc_exp,
- i16 %trunc_des, i32 6, i32 6)
- %old_ext = zext i16 %old to i32
- ret i32 %old_ext
-}
-
-; CHECK-NEXT: define internal i32 @test_atomic_cmpxchg_16(i32 %iptr, i32 %expected, i32 %desired) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %trunc_exp = trunc i32 %expected to i16
-; CHECK-NEXT: %trunc_des = trunc i32 %desired to i16
-; CHECK-NEXT: %old = call i16 @llvm.nacl.atomic.cmpxchg.i16(i32 %iptr, i16 %trunc_exp, i16 %trunc_des, i32 6, i32 6)
-; CHECK-NEXT: %old_ext = zext i16 %old to i32
-; CHECK-NEXT: ret i32 %old_ext
-; CHECK-NEXT: }
-
-define internal i32 @test_atomic_cmpxchg_32(i32 %iptr, i32 %expected, i32 %desired) {
-entry:
- %ptr = inttoptr i32 %iptr to i32*
- %old = call i32 @llvm.nacl.atomic.cmpxchg.i32(i32* %ptr, i32 %expected,
- i32 %desired, i32 6, i32 6)
- ret i32 %old
-}
-
-; CHECK-NEXT: define internal i32 @test_atomic_cmpxchg_32(i32 %iptr, i32 %expected, i32 %desired) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %old = call i32 @llvm.nacl.atomic.cmpxchg.i32(i32 %iptr, i32 %expected, i32 %desired, i32 6, i32 6)
-; CHECK-NEXT: ret i32 %old
-; CHECK-NEXT: }
-
-define internal i64 @test_atomic_cmpxchg_64(i32 %iptr, i64 %expected, i64 %desired) {
-entry:
- %ptr = inttoptr i32 %iptr to i64*
- %old = call i64 @llvm.nacl.atomic.cmpxchg.i64(i64* %ptr, i64 %expected,
- i64 %desired, i32 6, i32 6)
- ret i64 %old
-}
-
-; CHECK-NEXT: define internal i64 @test_atomic_cmpxchg_64(i32 %iptr, i64 %expected, i64 %desired) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %old = call i64 @llvm.nacl.atomic.cmpxchg.i64(i32 %iptr, i64 %expected, i64 %desired, i32 6, i32 6)
-; CHECK-NEXT: ret i64 %old
-; CHECK-NEXT: }
-
-;;;; Fence and is-lock-free.
-
-define internal void @test_atomic_fence() {
-entry:
- call void @llvm.nacl.atomic.fence(i32 6)
- ret void
-}
-
-; CHECK-NEXT: define internal void @test_atomic_fence() {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: call void @llvm.nacl.atomic.fence(i32 6)
-; CHECK-NEXT: ret void
-; CHECK-NEXT: }
-
-define internal void @test_atomic_fence_all() {
-entry:
- call void @llvm.nacl.atomic.fence.all()
- ret void
-}
-
-; CHECK-NEXT: define internal void @test_atomic_fence_all() {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: call void @llvm.nacl.atomic.fence.all()
-; CHECK-NEXT: ret void
-; CHECK-NEXT: }
-
-define internal i32 @test_atomic_is_lock_free(i32 %iptr) {
-entry:
- %ptr = inttoptr i32 %iptr to i8*
- %i = call i1 @llvm.nacl.atomic.is.lock.free(i32 4, i8* %ptr)
- %r = zext i1 %i to i32
- ret i32 %r
-}
-
-; CHECK-NEXT: define internal i32 @test_atomic_is_lock_free(i32 %iptr) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %i = call i1 @llvm.nacl.atomic.is.lock.free(i32 4, i32 %iptr)
-; CHECK-NEXT: %r = zext i1 %i to i32
-; CHECK-NEXT: ret i32 %r
-; CHECK-NEXT: }
-
-; NOIR: Total across all functions
diff --git a/third_party/subzero/tests_lit/reader_tests/nacl-other-intrinsics.ll b/third_party/subzero/tests_lit/reader_tests/nacl-other-intrinsics.ll
deleted file mode 100644
index f1ef663..0000000
--- a/third_party/subzero/tests_lit/reader_tests/nacl-other-intrinsics.ll
+++ /dev/null
@@ -1,403 +0,0 @@
-; This tests parsing NaCl intrinsics not related to atomic operations.
-
-; RUN: %p2i -i %s --insts --args -allow-externally-defined-symbols \
-; RUN: | FileCheck %s
-; RUN: %p2i -i %s --args -notranslate -timing \
-; RUN: -allow-externally-defined-symbols | \
-; RUN: FileCheck --check-prefix=NOIR %s
-
-declare i8* @llvm.nacl.read.tp()
-declare void @llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1)
-declare void @llvm.memmove.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1)
-declare void @llvm.memset.p0i8.i32(i8*, i8, i32, i32, i1)
-declare void @llvm.nacl.longjmp(i8*, i32)
-declare i32 @llvm.nacl.setjmp(i8*)
-declare float @llvm.sqrt.f32(float)
-declare double @llvm.sqrt.f64(double)
-declare float @llvm.fabs.f32(float)
-declare double @llvm.fabs.f64(double)
-declare <4 x float> @llvm.fabs.v4f32(<4 x float>)
-declare void @llvm.trap()
-declare i16 @llvm.bswap.i16(i16)
-declare i32 @llvm.bswap.i32(i32)
-declare i64 @llvm.bswap.i64(i64)
-declare i32 @llvm.ctlz.i32(i32, i1)
-declare i64 @llvm.ctlz.i64(i64, i1)
-declare i32 @llvm.cttz.i32(i32, i1)
-declare i64 @llvm.cttz.i64(i64, i1)
-declare i32 @llvm.ctpop.i32(i32)
-declare i64 @llvm.ctpop.i64(i64)
-declare i8* @llvm.stacksave()
-declare void @llvm.stackrestore(i8*)
-
-define internal i32 @test_nacl_read_tp() {
-entry:
- %ptr = call i8* @llvm.nacl.read.tp()
- %__1 = ptrtoint i8* %ptr to i32
- ret i32 %__1
-}
-
-; CHECK: define internal i32 @test_nacl_read_tp() {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %ptr = call i32 @llvm.nacl.read.tp()
-; CHECK-NEXT: ret i32 %ptr
-; CHECK-NEXT: }
-
-define internal void @test_memcpy(i32 %iptr_dst, i32 %iptr_src, i32 %len) {
-entry:
- %dst = inttoptr i32 %iptr_dst to i8*
- %src = inttoptr i32 %iptr_src to i8*
- call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dst, i8* %src,
- i32 %len, i32 1, i1 false)
- ret void
-}
-
-; CHECK-NEXT: define internal void @test_memcpy(i32 %iptr_dst, i32 %iptr_src, i32 %len) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i32 %iptr_dst, i32 %iptr_src, i32 %len, i32 1, i1 false)
-; CHECK-NEXT: ret void
-; CHECK-NEXT: }
-
-define internal void @test_memmove(i32 %iptr_dst, i32 %iptr_src, i32 %len) {
-entry:
- %dst = inttoptr i32 %iptr_dst to i8*
- %src = inttoptr i32 %iptr_src to i8*
- call void @llvm.memmove.p0i8.p0i8.i32(i8* %dst, i8* %src,
- i32 %len, i32 1, i1 false)
- ret void
-}
-
-; CHECK-NEXT: define internal void @test_memmove(i32 %iptr_dst, i32 %iptr_src, i32 %len) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: call void @llvm.memmove.p0i8.p0i8.i32(i32 %iptr_dst, i32 %iptr_src, i32 %len, i32 1, i1 false)
-; CHECK-NEXT: ret void
-; CHECK-NEXT: }
-
-define internal void @test_memset(i32 %iptr_dst, i32 %wide_val, i32 %len) {
-entry:
- %val = trunc i32 %wide_val to i8
- %dst = inttoptr i32 %iptr_dst to i8*
- call void @llvm.memset.p0i8.i32(i8* %dst, i8 %val,
- i32 %len, i32 1, i1 false)
- ret void
-}
-
-; CHECK-NEXT: define internal void @test_memset(i32 %iptr_dst, i32 %wide_val, i32 %len) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %val = trunc i32 %wide_val to i8
-; CHECK-NEXT: call void @llvm.memset.p0i8.i32(i32 %iptr_dst, i8 %val, i32 %len, i32 1, i1 false)
-; CHECK-NEXT: ret void
-; CHECK-NEXT: }
-
-define internal i32 @test_setjmplongjmp(i32 %iptr_env) {
-entry:
- %env = inttoptr i32 %iptr_env to i8*
- %i = call i32 @llvm.nacl.setjmp(i8* %env)
- %r1 = icmp eq i32 %i, 0
- br i1 %r1, label %Zero, label %NonZero
-Zero:
- ; Redundant inttoptr, to make --pnacl cast-eliding/re-insertion happy.
- %env2 = inttoptr i32 %iptr_env to i8*
- call void @llvm.nacl.longjmp(i8* %env2, i32 1)
- ret i32 0
-NonZero:
- ret i32 1
-}
-
-; CHECK-NEXT: define internal i32 @test_setjmplongjmp(i32 %iptr_env) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %i = call i32 @llvm.nacl.setjmp(i32 %iptr_env)
-; CHECK-NEXT: %r1 = icmp eq i32 %i, 0
-; CHECK-NEXT: br i1 %r1, label %Zero, label %NonZero
-; CHECK-NEXT: Zero:
-; CHECK-NEXT: call void @llvm.nacl.longjmp(i32 %iptr_env, i32 1)
-; CHECK-NEXT: ret i32 0
-; CHECK-NEXT: NonZero:
-; CHECK-NEXT: ret i32 1
-; CHECK-NEXT: }
-
-define internal float @test_sqrt_float(float %x, i32 %iptr) {
-entry:
- %r = call float @llvm.sqrt.f32(float %x)
- %r2 = call float @llvm.sqrt.f32(float %r)
- %r3 = call float @llvm.sqrt.f32(float -0.0)
- %r4 = fadd float %r2, %r3
- ret float %r4
-}
-
-; CHECK-NEXT: define internal float @test_sqrt_float(float %x, i32 %iptr) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %r = call float @llvm.sqrt.f32(float %x)
-; CHECK-NEXT: %r2 = call float @llvm.sqrt.f32(float %r)
-; CHECK-NEXT: %r3 = call float @llvm.sqrt.f32(float -0.000000e+00)
-; CHECK-NEXT: %r4 = fadd float %r2, %r3
-; CHECK-NEXT: ret float %r4
-; CHECK-NEXT: }
-
-define internal double @test_sqrt_double(double %x, i32 %iptr) {
-entry:
- %r = call double @llvm.sqrt.f64(double %x)
- %r2 = call double @llvm.sqrt.f64(double %r)
- %r3 = call double @llvm.sqrt.f64(double -0.0)
- %r4 = fadd double %r2, %r3
- ret double %r4
-}
-
-; CHECK-NEXT: define internal double @test_sqrt_double(double %x, i32 %iptr) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %r = call double @llvm.sqrt.f64(double %x)
-; CHECK-NEXT: %r2 = call double @llvm.sqrt.f64(double %r)
-; CHECK-NEXT: %r3 = call double @llvm.sqrt.f64(double -0.000000e+00)
-; CHECK-NEXT: %r4 = fadd double %r2, %r3
-; CHECK-NEXT: ret double %r4
-; CHECK-NEXT: }
-
-define internal float @test_fabs_float(float %x) {
-entry:
- %r = call float @llvm.fabs.f32(float %x)
- %r2 = call float @llvm.fabs.f32(float %r)
- %r3 = call float @llvm.fabs.f32(float -0.0)
- %r4 = fadd float %r2, %r3
- ret float %r4
-}
-
-; CHECK-NEXT: define internal float @test_fabs_float(float %x) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %r = call float @llvm.fabs.f32(float %x)
-; CHECK-NEXT: %r2 = call float @llvm.fabs.f32(float %r)
-; CHECK-NEXT: %r3 = call float @llvm.fabs.f32(float -0.000000e+00)
-; CHECK-NEXT: %r4 = fadd float %r2, %r3
-; CHECK-NEXT: ret float %r4
-; CHECK-NEXT: }
-
-define internal double @test_fabs_double(double %x) {
-entry:
- %r = call double @llvm.fabs.f64(double %x)
- %r2 = call double @llvm.fabs.f64(double %r)
- %r3 = call double @llvm.fabs.f64(double -0.0)
- %r4 = fadd double %r2, %r3
- ret double %r4
-}
-
-; CHECK-NEXT: define internal double @test_fabs_double(double %x) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %r = call double @llvm.fabs.f64(double %x)
-; CHECK-NEXT: %r2 = call double @llvm.fabs.f64(double %r)
-; CHECK-NEXT: %r3 = call double @llvm.fabs.f64(double -0.000000e+00)
-; CHECK-NEXT: %r4 = fadd double %r2, %r3
-; CHECK-NEXT: ret double %r4
-; CHECK-NEXT: }
-
-define internal <4 x float> @test_fabs_v4f32(<4 x float> %x) {
-entry:
- %r = call <4 x float> @llvm.fabs.v4f32(<4 x float> %x)
- %r2 = call <4 x float> @llvm.fabs.v4f32(<4 x float> %r)
- %r3 = call <4 x float> @llvm.fabs.v4f32(<4 x float> undef)
- %r4 = fadd <4 x float> %r2, %r3
- ret <4 x float> %r4
-}
-
-; CHECK-NEXT: define internal <4 x float> @test_fabs_v4f32(<4 x float> %x) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %r = call <4 x float> @llvm.fabs.v4f32(<4 x float> %x)
-; CHECK-NEXT: %r2 = call <4 x float> @llvm.fabs.v4f32(<4 x float> %r)
-; CHECK-NEXT: %r3 = call <4 x float> @llvm.fabs.v4f32(<4 x float> undef)
-; CHECK-NEXT: %r4 = fadd <4 x float> %r2, %r3
-; CHECK-NEXT: ret <4 x float> %r4
-; CHECK-NEXT: }
-
-define internal i32 @test_trap(i32 %br) {
-entry:
- %r1 = icmp eq i32 %br, 0
- br i1 %r1, label %Zero, label %NonZero
-Zero:
- call void @llvm.trap()
- unreachable
-NonZero:
- ret i32 1
-}
-
-; CHECK-NEXT: define internal i32 @test_trap(i32 %br) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %r1 = icmp eq i32 %br, 0
-; CHECK-NEXT: br i1 %r1, label %Zero, label %NonZero
-; CHECK-NEXT: Zero:
-; CHECK-NEXT: call void @llvm.trap()
-; CHECK-NEXT: unreachable
-; CHECK-NEXT: NonZero:
-; CHECK-NEXT: ret i32 1
-; CHECK-NEXT: }
-
-define internal i32 @test_bswap_16(i32 %x) {
-entry:
- %x_trunc = trunc i32 %x to i16
- %r = call i16 @llvm.bswap.i16(i16 %x_trunc)
- %r_zext = zext i16 %r to i32
- ret i32 %r_zext
-}
-
-; CHECK-NEXT: define internal i32 @test_bswap_16(i32 %x) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %x_trunc = trunc i32 %x to i16
-; CHECK-NEXT: %r = call i16 @llvm.bswap.i16(i16 %x_trunc)
-; CHECK-NEXT: %r_zext = zext i16 %r to i32
-; CHECK-NEXT: ret i32 %r_zext
-; CHECK-NEXT: }
-
-define internal i32 @test_bswap_32(i32 %x) {
-entry:
- %r = call i32 @llvm.bswap.i32(i32 %x)
- ret i32 %r
-}
-
-; CHECK-NEXT: define internal i32 @test_bswap_32(i32 %x) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %r = call i32 @llvm.bswap.i32(i32 %x)
-; CHECK-NEXT: ret i32 %r
-; CHECK-NEXT: }
-
-define internal i64 @test_bswap_64(i64 %x) {
-entry:
- %r = call i64 @llvm.bswap.i64(i64 %x)
- ret i64 %r
-}
-
-; CHECK-NEXT: define internal i64 @test_bswap_64(i64 %x) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %r = call i64 @llvm.bswap.i64(i64 %x)
-; CHECK-NEXT: ret i64 %r
-; CHECK-NEXT: }
-
-define internal i32 @test_ctlz_32(i32 %x) {
-entry:
- %r = call i32 @llvm.ctlz.i32(i32 %x, i1 false)
- ret i32 %r
-}
-
-; CHECK-NEXT: define internal i32 @test_ctlz_32(i32 %x) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %r = call i32 @llvm.ctlz.i32(i32 %x, i1 false)
-; CHECK-NEXT: ret i32 %r
-; CHECK-NEXT: }
-
-define internal i64 @test_ctlz_64(i64 %x) {
-entry:
- %r = call i64 @llvm.ctlz.i64(i64 %x, i1 false)
- ret i64 %r
-}
-
-; CHECK-NEXT: define internal i64 @test_ctlz_64(i64 %x) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %r = call i64 @llvm.ctlz.i64(i64 %x, i1 false)
-; CHECK-NEXT: ret i64 %r
-; CHECK-NEXT: }
-
-define internal i32 @test_cttz_32(i32 %x) {
-entry:
- %r = call i32 @llvm.cttz.i32(i32 %x, i1 false)
- ret i32 %r
-}
-
-; CHECK-NEXT: define internal i32 @test_cttz_32(i32 %x) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %r = call i32 @llvm.cttz.i32(i32 %x, i1 false)
-; CHECK-NEXT: ret i32 %r
-; CHECK-NEXT: }
-
-define internal i64 @test_cttz_64(i64 %x) {
-entry:
- %r = call i64 @llvm.cttz.i64(i64 %x, i1 false)
- ret i64 %r
-}
-
-; CHECK-NEXT: define internal i64 @test_cttz_64(i64 %x) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %r = call i64 @llvm.cttz.i64(i64 %x, i1 false)
-; CHECK-NEXT: ret i64 %r
-; CHECK-NEXT: }
-
-define internal i32 @test_popcount_32(i32 %x) {
-entry:
- %r = call i32 @llvm.ctpop.i32(i32 %x)
- ret i32 %r
-}
-
-; CHECK-NEXT: define internal i32 @test_popcount_32(i32 %x) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %r = call i32 @llvm.ctpop.i32(i32 %x)
-; CHECK-NEXT: ret i32 %r
-; CHECK-NEXT: }
-
-define internal i64 @test_popcount_64(i64 %x) {
-entry:
- %r = call i64 @llvm.ctpop.i64(i64 %x)
- ret i64 %r
-}
-
-; CHECK-NEXT: define internal i64 @test_popcount_64(i64 %x) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %r = call i64 @llvm.ctpop.i64(i64 %x)
-; CHECK-NEXT: ret i64 %r
-; CHECK-NEXT: }
-
-define internal void @test_stacksave_noalloca() {
-entry:
- %sp = call i8* @llvm.stacksave()
- call void @llvm.stackrestore(i8* %sp)
- ret void
-}
-
-; CHECK-NEXT: define internal void @test_stacksave_noalloca() {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %sp = call i32 @llvm.stacksave()
-; CHECK-NEXT: call void @llvm.stackrestore(i32 %sp)
-; CHECK-NEXT: ret void
-; CHECK-NEXT: }
-
-declare i32 @foo(i32 %x)
-
-define internal void @test_stacksave_multiple(i32 %x) {
-entry:
- %x_4 = mul i32 %x, 4
- %sp1 = call i8* @llvm.stacksave()
- %tmp1 = alloca i8, i32 %x_4, align 4
-
- %sp2 = call i8* @llvm.stacksave()
- %tmp2 = alloca i8, i32 %x_4, align 4
-
- %y = call i32 @foo(i32 %x)
-
- %sp3 = call i8* @llvm.stacksave()
- %tmp3 = alloca i8, i32 %x_4, align 4
-
- %__9 = bitcast i8* %tmp1 to i32*
- store i32 %y, i32* %__9, align 1
-
- %__10 = bitcast i8* %tmp2 to i32*
- store i32 %x, i32* %__10, align 1
-
- %__11 = bitcast i8* %tmp3 to i32*
- store i32 %x, i32* %__11, align 1
-
- call void @llvm.stackrestore(i8* %sp1)
- ret void
-}
-
-; CHECK-NEXT: define internal void @test_stacksave_multiple(i32 %x) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %x_4 = mul i32 %x, 4
-; CHECK-NEXT: %sp1 = call i32 @llvm.stacksave()
-; CHECK-NEXT: %tmp1 = alloca i8, i32 %x_4, align 4
-; CHECK-NEXT: %sp2 = call i32 @llvm.stacksave()
-; CHECK-NEXT: %tmp2 = alloca i8, i32 %x_4, align 4
-; CHECK-NEXT: %y = call i32 @foo(i32 %x)
-; CHECK-NEXT: %sp3 = call i32 @llvm.stacksave()
-; CHECK-NEXT: %tmp3 = alloca i8, i32 %x_4, align 4
-; CHECK-NEXT: store i32 %y, i32* %tmp1, align 1
-; CHECK-NEXT: store i32 %x, i32* %tmp2, align 1
-; CHECK-NEXT: store i32 %x, i32* %tmp3, align 1
-; CHECK-NEXT: call void @llvm.stackrestore(i32 %sp1)
-; CHECK-NEXT: ret void
-; CHECK-NEXT: }
-
-; NOIR: Total across all functions
diff --git a/third_party/subzero/tests_lit/reader_tests/phi.ll b/third_party/subzero/tests_lit/reader_tests/phi.ll
deleted file mode 100644
index de35635..0000000
--- a/third_party/subzero/tests_lit/reader_tests/phi.ll
+++ /dev/null
@@ -1,33 +0,0 @@
-; Test reading phi instructions.
-
-; RUN: %p2i -i %s --insts | FileCheck %s
-; RUN: %p2i -i %s --args -notranslate -timing | \
-; RUN: FileCheck --check-prefix=NOIR %s
-
-; TODO(kschimpf) Add forward reference examples.
-
-define internal i32 @testPhi1(i32 %arg) {
-entry:
- %cmp1 = icmp sgt i32 %arg, 0
- br i1 %cmp1, label %next, label %target
-next:
- br label %target
-target:
- %merge = phi i1 [ %cmp1, %entry ], [ false, %next ]
- %result = zext i1 %merge to i32
- ret i32 %result
-}
-
-; CHECK: define internal i32 @testPhi1(i32 %arg) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %cmp1 = icmp sgt i32 %arg, 0
-; CHECK-NEXT: br i1 %cmp1, label %next, label %target
-; CHECK-NEXT: next:
-; CHECK-NEXT: br label %target
-; CHECK-NEXT: target:
-; CHECK-NEXT: %merge = phi i1 [ %cmp1, %entry ], [ false, %next ]
-; CHECK-NEXT: %result = zext i1 %merge to i32
-; CHECK-NEXT: ret i32 %result
-; CHECK-NEXT: }
-
-; NOIR: Total across all functions
diff --git a/third_party/subzero/tests_lit/reader_tests/select.ll b/third_party/subzero/tests_lit/reader_tests/select.ll
deleted file mode 100644
index a99c36d..0000000
--- a/third_party/subzero/tests_lit/reader_tests/select.ll
+++ /dev/null
@@ -1,299 +0,0 @@
-; Tests if we can read select instructions.
-
-; RUN: %p2i -i %s --insts | FileCheck %s
-; RUN: %p2i -i %s --args -notranslate -timing | \
-; RUN: FileCheck --check-prefix=NOIR %s
-
-define internal void @Seli1(i32 %p) {
-entry:
- %vc = trunc i32 %p to i1
- %vt = trunc i32 %p to i1
- %ve = trunc i32 %p to i1
- %r = select i1 %vc, i1 %vt, i1 %ve
- ret void
-}
-
-; CHECK: define internal void @Seli1(i32 %p) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %vc = trunc i32 %p to i1
-; CHECK-NEXT: %vt = trunc i32 %p to i1
-; CHECK-NEXT: %ve = trunc i32 %p to i1
-; CHECK-NEXT: %r = select i1 %vc, i1 %vt, i1 %ve
-; CHECK-NEXT: ret void
-; CHECK-NEXT: }
-
-define internal void @Seli8(i32 %p) {
-entry:
- %vc = trunc i32 %p to i1
- %vt = trunc i32 %p to i8
- %ve = trunc i32 %p to i8
- %r = select i1 %vc, i8 %vt, i8 %ve
- ret void
-}
-
-; CHECK-NEXT: define internal void @Seli8(i32 %p) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %vc = trunc i32 %p to i1
-; CHECK-NEXT: %vt = trunc i32 %p to i8
-; CHECK-NEXT: %ve = trunc i32 %p to i8
-; CHECK-NEXT: %r = select i1 %vc, i8 %vt, i8 %ve
-; CHECK-NEXT: ret void
-; CHECK-NEXT: }
-
-define internal void @Seli16(i32 %p) {
-entry:
- %vc = trunc i32 %p to i1
- %vt = trunc i32 %p to i16
- %ve = trunc i32 %p to i16
- %r = select i1 %vc, i16 %vt, i16 %ve
- ret void
-}
-
-; CHECK-NEXT: define internal void @Seli16(i32 %p) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %vc = trunc i32 %p to i1
-; CHECK-NEXT: %vt = trunc i32 %p to i16
-; CHECK-NEXT: %ve = trunc i32 %p to i16
-; CHECK-NEXT: %r = select i1 %vc, i16 %vt, i16 %ve
-; CHECK-NEXT: ret void
-; CHECK-NEXT: }
-
-define internal i32 @Seli32(i32 %pc, i32 %pt, i32 %pe) {
-entry:
- %vc = trunc i32 %pc to i1
- %r = select i1 %vc, i32 %pt, i32 %pe
- ret i32 %r
-}
-
-; CHECK-NEXT: define internal i32 @Seli32(i32 %pc, i32 %pt, i32 %pe) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %vc = trunc i32 %pc to i1
-; CHECK-NEXT: %r = select i1 %vc, i32 %pt, i32 %pe
-; CHECK-NEXT: ret i32 %r
-; CHECK-NEXT: }
-
-define internal i64 @Seli64(i64 %pc, i64 %pt, i64 %pe) {
-entry:
- %vc = trunc i64 %pc to i1
- %r = select i1 %vc, i64 %pt, i64 %pe
- ret i64 %r
-}
-
-; CHECK-NEXT: define internal i64 @Seli64(i64 %pc, i64 %pt, i64 %pe) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %vc = trunc i64 %pc to i1
-; CHECK-NEXT: %r = select i1 %vc, i64 %pt, i64 %pe
-; CHECK-NEXT: ret i64 %r
-; CHECK-NEXT: }
-
-define internal float @SelFloat(i32 %pc, float %pt, float %pe) {
-entry:
- %vc = trunc i32 %pc to i1
- %r = select i1 %vc, float %pt, float %pe
- ret float %r
-}
-
-; CHECK-NEXT: define internal float @SelFloat(i32 %pc, float %pt, float %pe) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %vc = trunc i32 %pc to i1
-; CHECK-NEXT: %r = select i1 %vc, float %pt, float %pe
-; CHECK-NEXT: ret float %r
-; CHECK-NEXT: }
-
-define internal double @SelDouble(i32 %pc, double %pt, double %pe) {
-entry:
- %vc = trunc i32 %pc to i1
- %r = select i1 %vc, double %pt, double %pe
- ret double %r
-}
-
-; CHECK-NEXT: define internal double @SelDouble(i32 %pc, double %pt, double %pe) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %vc = trunc i32 %pc to i1
-; CHECK-NEXT: %r = select i1 %vc, double %pt, double %pe
-; CHECK-NEXT: ret double %r
-; CHECK-NEXT: }
-
-define internal <16 x i1> @SelV16x1(i32 %pc, <16 x i1> %pt, <16 x i1> %pe) {
-entry:
- %vc = trunc i32 %pc to i1
- %r = select i1 %vc, <16 x i1> %pt, <16 x i1> %pe
- ret <16 x i1> %r
-}
-
-; CHECK-NEXT: define internal <16 x i1> @SelV16x1(i32 %pc, <16 x i1> %pt, <16 x i1> %pe) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %vc = trunc i32 %pc to i1
-; CHECK-NEXT: %r = select i1 %vc, <16 x i1> %pt, <16 x i1> %pe
-; CHECK-NEXT: ret <16 x i1> %r
-; CHECK-NEXT: }
-
-define internal <8 x i1> @SelV8x1(i32 %pc, <8 x i1> %pt, <8 x i1> %pe) {
-entry:
- %vc = trunc i32 %pc to i1
- %r = select i1 %vc, <8 x i1> %pt, <8 x i1> %pe
- ret <8 x i1> %r
-}
-
-; CHECK-NEXT: define internal <8 x i1> @SelV8x1(i32 %pc, <8 x i1> %pt, <8 x i1> %pe) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %vc = trunc i32 %pc to i1
-; CHECK-NEXT: %r = select i1 %vc, <8 x i1> %pt, <8 x i1> %pe
-; CHECK-NEXT: ret <8 x i1> %r
-; CHECK-NEXT: }
-
-define internal <4 x i1> @SelV4x1(i32 %pc, <4 x i1> %pt, <4 x i1> %pe) {
-entry:
- %vc = trunc i32 %pc to i1
- %r = select i1 %vc, <4 x i1> %pt, <4 x i1> %pe
- ret <4 x i1> %r
-}
-
-; CHECK-NEXT: define internal <4 x i1> @SelV4x1(i32 %pc, <4 x i1> %pt, <4 x i1> %pe) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %vc = trunc i32 %pc to i1
-; CHECK-NEXT: %r = select i1 %vc, <4 x i1> %pt, <4 x i1> %pe
-; CHECK-NEXT: ret <4 x i1> %r
-; CHECK-NEXT: }
-
-define internal <16 x i8> @SelV16x8(i32 %pc, <16 x i8> %pt, <16 x i8> %pe) {
-entry:
- %vc = trunc i32 %pc to i1
- %r = select i1 %vc, <16 x i8> %pt, <16 x i8> %pe
- ret <16 x i8> %r
-}
-
-; CHECK-NEXT: define internal <16 x i8> @SelV16x8(i32 %pc, <16 x i8> %pt, <16 x i8> %pe) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %vc = trunc i32 %pc to i1
-; CHECK-NEXT: %r = select i1 %vc, <16 x i8> %pt, <16 x i8> %pe
-; CHECK-NEXT: ret <16 x i8> %r
-; CHECK-NEXT: }
-
-define internal <8 x i16> @SelV8x16(i32 %pc, <8 x i16> %pt, <8 x i16> %pe) {
-entry:
- %vc = trunc i32 %pc to i1
- %r = select i1 %vc, <8 x i16> %pt, <8 x i16> %pe
- ret <8 x i16> %r
-}
-
-; CHECK-NEXT: define internal <8 x i16> @SelV8x16(i32 %pc, <8 x i16> %pt, <8 x i16> %pe) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %vc = trunc i32 %pc to i1
-; CHECK-NEXT: %r = select i1 %vc, <8 x i16> %pt, <8 x i16> %pe
-; CHECK-NEXT: ret <8 x i16> %r
-; CHECK-NEXT: }
-
-define internal <4 x i32> @SelV4x32(i32 %pc, <4 x i32> %pt, <4 x i32> %pe) {
-entry:
- %vc = trunc i32 %pc to i1
- %r = select i1 %vc, <4 x i32> %pt, <4 x i32> %pe
- ret <4 x i32> %r
-}
-
-; CHECK-NEXT: define internal <4 x i32> @SelV4x32(i32 %pc, <4 x i32> %pt, <4 x i32> %pe) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %vc = trunc i32 %pc to i1
-; CHECK-NEXT: %r = select i1 %vc, <4 x i32> %pt, <4 x i32> %pe
-; CHECK-NEXT: ret <4 x i32> %r
-; CHECK-NEXT: }
-
-define internal <4 x float> @SelV4xfloat(i32 %pc, <4 x float> %pt, <4 x float> %pe) {
-entry:
- %vc = trunc i32 %pc to i1
- %r = select i1 %vc, <4 x float> %pt, <4 x float> %pe
- ret <4 x float> %r
-}
-
-; CHECK-NEXT: define internal <4 x float> @SelV4xfloat(i32 %pc, <4 x float> %pt, <4 x float> %pe) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %vc = trunc i32 %pc to i1
-; CHECK-NEXT: %r = select i1 %vc, <4 x float> %pt, <4 x float> %pe
-; CHECK-NEXT: ret <4 x float> %r
-; CHECK-NEXT: }
-
-define internal <16 x i1> @SelV16x1Vcond(<16 x i1> %pc, <16 x i1> %pt, <16 x i1> %pe) {
-entry:
- %r = select <16 x i1> %pc, <16 x i1> %pt, <16 x i1> %pe
- ret <16 x i1> %r
-}
-
-; CHECK-NEXT: define internal <16 x i1> @SelV16x1Vcond(<16 x i1> %pc, <16 x i1> %pt, <16 x i1> %pe) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %r = select <16 x i1> %pc, <16 x i1> %pt, <16 x i1> %pe
-; CHECK-NEXT: ret <16 x i1> %r
-; CHECK-NEXT: }
-
-define internal <8 x i1> @SelV8x1Vcond(<8 x i1> %pc, <8 x i1> %pt, <8 x i1> %pe) {
-entry:
- %r = select <8 x i1> %pc, <8 x i1> %pt, <8 x i1> %pe
- ret <8 x i1> %r
-}
-
-; CHECK-NEXT: define internal <8 x i1> @SelV8x1Vcond(<8 x i1> %pc, <8 x i1> %pt, <8 x i1> %pe) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %r = select <8 x i1> %pc, <8 x i1> %pt, <8 x i1> %pe
-; CHECK-NEXT: ret <8 x i1> %r
-; CHECK-NEXT: }
-
-define internal <4 x i1> @SelV4x1Vcond(<4 x i1> %pc, <4 x i1> %pt, <4 x i1> %pe) {
-entry:
- %r = select <4 x i1> %pc, <4 x i1> %pt, <4 x i1> %pe
- ret <4 x i1> %r
-}
-
-; CHECK-NEXT: define internal <4 x i1> @SelV4x1Vcond(<4 x i1> %pc, <4 x i1> %pt, <4 x i1> %pe) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %r = select <4 x i1> %pc, <4 x i1> %pt, <4 x i1> %pe
-; CHECK-NEXT: ret <4 x i1> %r
-; CHECK-NEXT: }
-
-define internal <16 x i8> @SelV16x8Vcond(<16 x i1> %pc, <16 x i8> %pt, <16 x i8> %pe) {
-entry:
- %r = select <16 x i1> %pc, <16 x i8> %pt, <16 x i8> %pe
- ret <16 x i8> %r
-}
-
-; CHECK-NEXT: define internal <16 x i8> @SelV16x8Vcond(<16 x i1> %pc, <16 x i8> %pt, <16 x i8> %pe) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %r = select <16 x i1> %pc, <16 x i8> %pt, <16 x i8> %pe
-; CHECK-NEXT: ret <16 x i8> %r
-; CHECK-NEXT: }
-
-define internal <8 x i16> @SelV8x16Vcond(<8 x i1> %pc, <8 x i16> %pt, <8 x i16> %pe) {
-entry:
- %r = select <8 x i1> %pc, <8 x i16> %pt, <8 x i16> %pe
- ret <8 x i16> %r
-}
-
-; CHECK-NEXT: define internal <8 x i16> @SelV8x16Vcond(<8 x i1> %pc, <8 x i16> %pt, <8 x i16> %pe) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %r = select <8 x i1> %pc, <8 x i16> %pt, <8 x i16> %pe
-; CHECK-NEXT: ret <8 x i16> %r
-; CHECK-NEXT: }
-
-define internal <4 x i32> @SelV4x32Vcond(<4 x i1> %pc, <4 x i32> %pt, <4 x i32> %pe) {
-entry:
- %r = select <4 x i1> %pc, <4 x i32> %pt, <4 x i32> %pe
- ret <4 x i32> %r
-}
-
-; CHECK-NEXT: define internal <4 x i32> @SelV4x32Vcond(<4 x i1> %pc, <4 x i32> %pt, <4 x i32> %pe) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %r = select <4 x i1> %pc, <4 x i32> %pt, <4 x i32> %pe
-; CHECK-NEXT: ret <4 x i32> %r
-; CHECK-NEXT: }
-
-define internal <4 x float> @SelV4xfloatVcond(<4 x i1> %pc, <4 x float> %pt, <4 x float> %pe) {
-entry:
- %r = select <4 x i1> %pc, <4 x float> %pt, <4 x float> %pe
- ret <4 x float> %r
-}
-
-; CHECK-NEXT: define internal <4 x float> @SelV4xfloatVcond(<4 x i1> %pc, <4 x float> %pt, <4 x float> %pe) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %r = select <4 x i1> %pc, <4 x float> %pt, <4 x float> %pe
-; CHECK-NEXT: ret <4 x float> %r
-; CHECK-NEXT: }
-
-; NOIR: Total across all functions
diff --git a/third_party/subzero/tests_lit/reader_tests/store.ll b/third_party/subzero/tests_lit/reader_tests/store.ll
deleted file mode 100644
index de4dd77..0000000
--- a/third_party/subzero/tests_lit/reader_tests/store.ll
+++ /dev/null
@@ -1,139 +0,0 @@
-; Test if we can read store instructions.
-
-; RUN: %p2i -i %s --insts --no-local-syms | FileCheck %s
-; RUN: %p2i -i %s --args -notranslate -timing | \
-; RUN: FileCheck --check-prefix=NOIR %s
-
-define internal void @store_i8(i32 %addr) {
-entry:
- %addr_i8 = inttoptr i32 %addr to i8*
- store i8 3, i8* %addr_i8, align 1
- ret void
-
-; CHECK: __0:
-; CHECK-NEXT: store i8 3, i8* %__0, align 1
-; CHECK-NEXT: ret void
-}
-
-define internal void @store_i16(i32 %addr) {
-entry:
- %addr_i16 = inttoptr i32 %addr to i16*
- store i16 5, i16* %addr_i16, align 1
- ret void
-
-; CHECK: __0:
-; CHECK-NEXT: store i16 5, i16* %__0, align 1
-; CHECK-NEXT: ret void
-}
-
-define internal void @store_i32(i32 %addr, i32 %v) {
-entry:
- %addr_i32 = inttoptr i32 %addr to i32*
- store i32 %v, i32* %addr_i32, align 1
- ret void
-
-; CHECK: __0:
-; CHECK-NEXT: store i32 %__1, i32* %__0, align 1
-; CHECK-NEXT: ret void
-}
-
-define internal void @store_i64(i32 %addr, i64 %v) {
-entry:
- %addr_i64 = inttoptr i32 %addr to i64*
- store i64 %v, i64* %addr_i64, align 1
- ret void
-
-; CHECK: __0:
-; CHECK-NEXT: store i64 %__1, i64* %__0, align 1
-; CHECK-NEXT: ret void
-}
-
-define internal void @store_float_a1(i32 %addr, float %v) {
-entry:
- %addr_float = inttoptr i32 %addr to float*
- store float %v, float* %addr_float, align 1
- ret void
-
-; TODO(kschimpf) Fix store alignment in ICE to allow non-default.
-
-; CHECK: __0:
-; CHECK-NEXT: store float %__1, float* %__0, align 4
-; CHECK-NEXT: ret void
-}
-
-define internal void @store_float_a4(i32 %addr, float %v) {
-entry:
- %addr_float = inttoptr i32 %addr to float*
- store float %v, float* %addr_float, align 4
- ret void
-
-; CHECK: __0:
-; CHECK-NEXT: store float %__1, float* %__0, align 4
-; CHECK-NEXT: ret void
-}
-
-define internal void @store_double_a1(i32 %addr, double %v) {
-entry:
- %addr_double = inttoptr i32 %addr to double*
- store double %v, double* %addr_double, align 1
- ret void
-
-; TODO(kschimpf) Fix store alignment in ICE to allow non-default.
-
-; CHECK: __0:
-; CHECK-NEXT: store double %__1, double* %__0, align 8
-; CHECK-NEXT: ret void
-}
-
-define internal void @store_double_a8(i32 %addr, double %v) {
-entry:
- %addr_double = inttoptr i32 %addr to double*
- store double %v, double* %addr_double, align 8
- ret void
-
-; CHECK: __0:
-; CHECK-NEXT: store double %__1, double* %__0, align 8
-; CHECK-NEXT: ret void
-}
-
-define internal void @store_v16xI8(i32 %addr, <16 x i8> %v) {
- %addr_v16xI8 = inttoptr i32 %addr to <16 x i8>*
- store <16 x i8> %v, <16 x i8>* %addr_v16xI8, align 1
- ret void
-
-; CHECK: __0:
-; CHECK-NEXT: store <16 x i8> %__1, <16 x i8>* %__0, align 1
-; CHECK-NEXT: ret void
-}
-
-define internal void @store_v8xI16(i32 %addr, <8 x i16> %v) {
- %addr_v8xI16 = inttoptr i32 %addr to <8 x i16>*
- store <8 x i16> %v, <8 x i16>* %addr_v8xI16, align 2
- ret void
-
-; CHECK: __0:
-; CHECK-NEXT: store <8 x i16> %__1, <8 x i16>* %__0, align 2
-; CHECK-NEXT: ret void
-}
-
-define internal void @store_v4xI32(i32 %addr, <4 x i32> %v) {
- %addr_v4xI32 = inttoptr i32 %addr to <4 x i32>*
- store <4 x i32> %v, <4 x i32>* %addr_v4xI32, align 4
- ret void
-
-; CHECK: __0:
-; CHECK-NEXT: store <4 x i32> %__1, <4 x i32>* %__0, align 4
-; CHECK-NEXT: ret void
-}
-
-define internal void @store_v4xFloat(i32 %addr, <4 x float> %v) {
- %addr_v4xFloat = inttoptr i32 %addr to <4 x float>*
- store <4 x float> %v, <4 x float>* %addr_v4xFloat, align 4
- ret void
-
-; CHECK: __0:
-; CHECK-NEXT: store <4 x float> %__1, <4 x float>* %__0, align 4
-; CHECK-NEXT: ret void
-}
-
-; NOIR: Total across all functions
diff --git a/third_party/subzero/tests_lit/reader_tests/switch.ll b/third_party/subzero/tests_lit/reader_tests/switch.ll
deleted file mode 100644
index 27f7598..0000000
--- a/third_party/subzero/tests_lit/reader_tests/switch.ll
+++ /dev/null
@@ -1,495 +0,0 @@
-; Test switch instructions.
-
-; RUN: %p2i -i %s --insts | FileCheck %s
-; RUN: %p2i -i %s --args -notranslate -timing | \
-; RUN: FileCheck --check-prefix=NOIR %s
-
-define internal void @testDefaultSwitch(i32 %a) {
-entry:
- switch i32 %a, label %exit [
- ]
-exit:
- ret void
-}
-
-; CHECK: define internal void @testDefaultSwitch(i32 %a) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: switch i32 %a, label %exit [
-; CHECK-NEXT: ]
-; CHECK-NEXT: exit:
-; CHECK-NEXT: ret void
-; CHECK-NEXT: }
-
-define internal i32 @testSwitch(i32 %a) {
-entry:
- switch i32 %a, label %sw.default [
- i32 1, label %sw.epilog
- i32 2, label %sw.epilog
- i32 3, label %sw.epilog
- i32 7, label %sw.bb1
- i32 8, label %sw.bb1
- i32 15, label %sw.bb2
- i32 14, label %sw.bb2
- ]
-
-sw.default: ; preds = %entry
- %add = add i32 %a, 27
- br label %sw.epilog
-
-sw.bb1: ; preds = %entry, %entry
- %phitmp = sub i32 21, %a
- br label %sw.bb2
-
-sw.bb2: ; preds = %sw.bb1, %entry, %entry
- %result.0 = phi i32 [ 1, %entry ], [ 1, %entry ], [ %phitmp, %sw.bb1 ]
- br label %sw.epilog
-
-sw.epilog: ; preds = %sw.bb2, %sw.default, %entry, %entry, %entry
- %result.1 = phi i32 [ %add, %sw.default ], [ %result.0, %sw.bb2 ], [ 17, %entry ], [ 17, %entry ], [ 17, %entry ]
- ret i32 %result.1
-}
-
-; CHECK-NEXT: define internal i32 @testSwitch(i32 %a) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: switch i32 %a, label %sw.default [
-; CHECK-NEXT: i32 1, label %sw.epilog
-; CHECK-NEXT: i32 2, label %sw.epilog
-; CHECK-NEXT: i32 3, label %sw.epilog
-; CHECK-NEXT: i32 7, label %sw.bb1
-; CHECK-NEXT: i32 8, label %sw.bb1
-; CHECK-NEXT: i32 15, label %sw.bb2
-; CHECK-NEXT: i32 14, label %sw.bb2
-; CHECK-NEXT: ]
-; CHECK-NEXT: sw.default:
-; CHECK-NEXT: %add = add i32 %a, 27
-; CHECK-NEXT: br label %sw.epilog
-; CHECK-NEXT: sw.bb1:
-; CHECK-NEXT: %phitmp = sub i32 21, %a
-; CHECK-NEXT: br label %sw.bb2
-; CHECK-NEXT: sw.bb2:
-; CHECK-NEXT: %result.0 = phi i32 [ 1, %entry ], [ 1, %entry ], [ %phitmp, %sw.bb1 ]
-; CHECK-NEXT: br label %sw.epilog
-; CHECK-NEXT: sw.epilog:
-; CHECK-NEXT: %result.1 = phi i32 [ %add, %sw.default ], [ %result.0, %sw.bb2 ], [ 17, %entry ], [ 17, %entry ], [ 17, %entry ]
-; CHECK-NEXT: ret i32 %result.1
-; CHECK-NEXT: }
-
-define internal void @testSignedI32Values(i32 %a) {
-entry:
- switch i32 %a, label %labelDefault [
- i32 0, label %label0
- i32 -1, label %labelM1
- i32 3, label %labelOther
- i32 -3, label %labelOther
- i32 -2147483648, label %labelMin ; min signed i32
- i32 2147483647, label %labelMax ; max signed i32
- ]
-labelDefault:
- ret void
-label0:
- ret void
-labelM1:
- ret void
-labelMin:
- ret void
-labelMax:
- ret void
-labelOther:
- ret void
-}
-
-; CHECK-NEXT: define internal void @testSignedI32Values(i32 %a) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: switch i32 %a, label %labelDefault [
-; CHECK-NEXT: i32 0, label %label0
-; CHECK-NEXT: i32 -1, label %labelM1
-; CHECK-NEXT: i32 3, label %labelOther
-; CHECK-NEXT: i32 -3, label %labelOther
-; CHECK-NEXT: i32 -2147483648, label %labelMin
-; CHECK-NEXT: i32 2147483647, label %labelMax
-; CHECK-NEXT: ]
-; CHECK-NEXT: labelDefault:
-; CHECK-NEXT: ret void
-; CHECK-NEXT: label0:
-; CHECK-NEXT: ret void
-; CHECK-NEXT: labelM1:
-; CHECK-NEXT: ret void
-; CHECK-NEXT: labelMin:
-; CHECK-NEXT: ret void
-; CHECK-NEXT: labelMax:
-; CHECK-NEXT: ret void
-; CHECK-NEXT: labelOther:
-; CHECK-NEXT: ret void
-; CHECK-NEXT: }
-
-; Test values that cross signed i32 size boundaries.
-define internal void @testSignedI32Boundary(i32 %a) {
-entry:
- switch i32 %a, label %exit [
- i32 -2147483649, label %exit ; min signed i32 - 1
- i32 2147483648, label %exit ; max signed i32 + 1
- ]
-exit:
- ret void
-}
-
-; CHECK-NEXT: define internal void @testSignedI32Boundary(i32 %a) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: switch i32 %a, label %exit [
-; CHECK-NEXT: i32 2147483647, label %exit
-; CHECK-NEXT: i32 -2147483648, label %exit
-; CHECK-NEXT: ]
-; CHECK-NEXT: exit:
-; CHECK-NEXT: ret void
-; CHECK-NEXT: }
-
-define internal void @testUnsignedI32Values(i32 %a) {
-entry:
- switch i32 %a, label %exit [
- i32 0, label %exit
- i32 2147483647, label %exit ; max signed i32
- i32 4294967295, label %exit ; max unsigned i32
- ]
-exit:
- ret void
-}
-
-; CHECK-NEXT: define internal void @testUnsignedI32Values(i32 %a) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: switch i32 %a, label %exit [
-; CHECK-NEXT: i32 0, label %exit
-; CHECK-NEXT: i32 2147483647, label %exit
-; ; Note that -1 is signed version of 4294967295
-; CHECK-NEXT: i32 -1, label %exit
-; CHECK-NEXT: ]
-; CHECK-NEXT: exit:
-; CHECK-NEXT: ret void
-; CHECK-NEXT: }
-
-; Test values that cross unsigned i32 boundaries.
-define internal void @testUnsignedI32Boundary(i32 %a) {
-entry:
- switch i32 %a, label %exit [
- i32 4294967296, label %exit ; max unsigned i32 + 1
- ]
-exit:
- ret void
-}
-
-; CHECK-NEXT: define internal void @testUnsignedI32Boundary(i32 %a) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: switch i32 %a, label %exit [
-; CHECK-NEXT: i32 0, label %exit
-; CHECK-NEXT: ]
-; CHECK-NEXT: exit:
-; CHECK-NEXT: ret void
-; CHECK-NEXT: }
-
-define internal void @testSignedI64Values(i64 %a) {
-entry:
- switch i64 %a, label %exit [
- i64 0, label %exit
- i64 -9223372036854775808, label %exit ; min signed i64
- i64 9223372036854775807, label %exit ; max signed i64
- ]
-exit:
- ret void
-}
-
-; CHECK-NEXT: define internal void @testSignedI64Values(i64 %a) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: switch i64 %a, label %exit [
-; CHECK-NEXT: i64 0, label %exit
-; CHECK-NEXT: i64 -9223372036854775808, label %exit
-; CHECK-NEXT: i64 9223372036854775807, label %exit
-; CHECK-NEXT: ]
-; CHECK-NEXT: exit:
-; CHECK-NEXT: ret void
-; CHECK-NEXT: }
-
-; Test values that cross signed i64 size boundaries.
-define internal void @testSignedI64Boundary(i64 %a) {
-entry:
- switch i64 %a, label %exit [
- i64 0, label %exit
- i64 -9223372036854775809, label %exit ; min signed i64 - 1
- i64 9223372036854775808, label %exit ; max signed i64 + 1
- ]
-exit:
- ret void
-}
-
-; CHECK-NEXT: define internal void @testSignedI64Boundary(i64 %a) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: switch i64 %a, label %exit [
-; CHECK-NEXT: i64 0, label %exit
-; CHECK-NEXT: i64 9223372036854775807, label %exit
-; CHECK-NEXT: i64 -9223372036854775808, label %exit
-; CHECK-NEXT: ]
-; CHECK-NEXT: exit:
-; CHECK-NEXT: ret void
-; CHECK-NEXT: }
-
-define internal void @testUnsignedI64Values(i64 %a) {
-entry:
- switch i64 %a, label %exit [
- i64 0, label %exit
- i64 9223372036854775807, label %exit ; max signed i64
- i64 18446744073709551615, label %exit ; max unsigned i64
- ]
-exit:
- ret void
-}
-
-; CHECK-NEXT: define internal void @testUnsignedI64Values(i64 %a) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: switch i64 %a, label %exit [
-; CHECK-NEXT: i64 0, label %exit
-; CHECK-NEXT: i64 9223372036854775807, label %exit
-; CHECK-NEXT: i64 -1, label %exit
-; CHECK-NEXT: ]
-; CHECK-NEXT: exit:
-; CHECK-NEXT: ret void
-; CHECK-NEXT: }
-
-; Test values that cross unsigned i64 size boundaries.
-define internal void @testUnsignedI64Boundary(i64 %a) {
-entry:
- switch i64 %a, label %exit [
- i64 18446744073709551616, label %exit ; max unsigned i64 + 1
- ]
-exit:
- ret void
-}
-
-; CHECK-NEXT: define internal void @testUnsignedI64Boundary(i64 %a) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: switch i64 %a, label %exit [
-; CHECK-NEXT: i64 0, label %exit
-; CHECK-NEXT: ]
-; CHECK-NEXT: exit:
-; CHECK-NEXT: ret void
-; CHECK-NEXT: }
-
-define internal void @testSignedI16Values(i32 %p) {
-entry:
- %a = trunc i32 %p to i16
- switch i16 %a, label %exit [
- i16 0, label %exit
- i16 -1, label %exit
- i16 3, label %exit
- i16 -3, label %exit
- i16 -32768, label %exit ; min signed i16
- i16 32767, label %exit ; max unsigned i16
- ]
-exit:
- ret void
-}
-
-; CHECK-NEXT: define internal void @testSignedI16Values(i32 %p) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %a = trunc i32 %p to i16
-; CHECK-NEXT: switch i16 %a, label %exit [
-; CHECK-NEXT: i16 0, label %exit
-; CHECK-NEXT: i16 -1, label %exit
-; CHECK-NEXT: i16 3, label %exit
-; CHECK-NEXT: i16 -3, label %exit
-; CHECK-NEXT: i16 -32768, label %exit
-; CHECK-NEXT: i16 32767, label %exit
-; CHECK-NEXT: ]
-; CHECK-NEXT: exit:
-; CHECK-NEXT: ret void
-; CHECK-NEXT: }
-
-; Test values that cross signed i16 size boundaries.
-define internal void @testSignedI16Boundary(i32 %p) {
-entry:
- %a = trunc i32 %p to i16
- switch i16 %a, label %exit [
- i16 -32769, label %exit ; min signed i16 - 1
- i16 32768, label %exit ; max unsigned i16 + 1
- ]
-exit:
- ret void
-}
-
-; CHECK-NEXT: define internal void @testSignedI16Boundary(i32 %p) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %a = trunc i32 %p to i16
-; CHECK-NEXT: switch i16 %a, label %exit [
-; CHECK-NEXT: i16 32767, label %exit
-; CHECK-NEXT: i16 -32768, label %exit
-; CHECK-NEXT: ]
-; CHECK-NEXT: exit:
-; CHECK-NEXT: ret void
-; CHECK-NEXT: }
-
-define internal void @testUnsignedI16Values(i32 %p) {
-entry:
- %a = trunc i32 %p to i16
- switch i16 %a, label %exit [
- i16 0, label %exit
- i16 32767, label %exit ; max signed i16
- i16 65535, label %exit ; max unsigned i16
- ]
-exit:
- ret void
-}
-
-; CHECK-NEXT: define internal void @testUnsignedI16Values(i32 %p) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %a = trunc i32 %p to i16
-; CHECK-NEXT: switch i16 %a, label %exit [
-; CHECK-NEXT: i16 0, label %exit
-; CHECK-NEXT: i16 32767, label %exit
-; ; Note that -1 is signed version of 65535
-; CHECK-NEXT: i16 -1, label %exit
-; CHECK-NEXT: ]
-; CHECK-NEXT: exit:
-; CHECK-NEXT: ret void
-; CHECK-NEXT: }
-
-; Test values that cross unsigned i16 size boundaries.
-define internal void @testUnsignedI16Boundary(i32 %p) {
-entry:
- %a = trunc i32 %p to i16
- switch i16 %a, label %exit [
- i16 65536, label %exit ; max unsigned i16 + 1
- ]
-exit:
- ret void
-}
-
-; CHECK-NEXT: define internal void @testUnsignedI16Boundary(i32 %p) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %a = trunc i32 %p to i16
-; CHECK-NEXT: switch i16 %a, label %exit [
-; CHECK-NEXT: i16 0, label %exit
-; CHECK-NEXT: ]
-; CHECK-NEXT: exit:
-; CHECK-NEXT: ret void
-; CHECK-NEXT: }
-
-define internal void @testSignedI8Values(i32 %p) {
-entry:
- %a = trunc i32 %p to i8
- switch i8 %a, label %exit [
- i8 0, label %exit
- i8 -1, label %exit
- i8 3, label %exit
- i8 -3, label %exit
- i8 -128, label %exit ; min signed i8
- i8 127, label %exit ; max unsigned i8
- ]
-exit:
- ret void
-}
-
-; CHECK-NEXT: define internal void @testSignedI8Values(i32 %p) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %a = trunc i32 %p to i8
-; CHECK-NEXT: switch i8 %a, label %exit [
-; CHECK-NEXT: i8 0, label %exit
-; CHECK-NEXT: i8 -1, label %exit
-; CHECK-NEXT: i8 3, label %exit
-; CHECK-NEXT: i8 -3, label %exit
-; CHECK-NEXT: i8 -128, label %exit
-; CHECK-NEXT: i8 127, label %exit
-; CHECK-NEXT: ]
-; CHECK-NEXT: exit:
-; CHECK-NEXT: ret void
-; CHECK-NEXT: }
-
-; Test values that cross signed i8 size boundaries.
-define internal void @testSignedI8Boundary(i32 %p) {
-entry:
- %a = trunc i32 %p to i8
- switch i8 %a, label %exit [
- i8 -129, label %exit ; min signed i8 - 1
- i8 128, label %exit ; max unsigned i8 + 1
- ]
-exit:
- ret void
-}
-
-; CHECK-NEXT: define internal void @testSignedI8Boundary(i32 %p) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %a = trunc i32 %p to i8
-; CHECK-NEXT: switch i8 %a, label %exit [
-; CHECK-NEXT: i8 127, label %exit
-; CHECK-NEXT: i8 -128, label %exit
-; CHECK-NEXT: ]
-; CHECK-NEXT: exit:
-; CHECK-NEXT: ret void
-; CHECK-NEXT: }
-
-
-define internal void @testUnsignedI8Values(i32 %p) {
-entry:
- %a = trunc i32 %p to i8
- switch i8 %a, label %exit [
- i8 0, label %exit
- i8 127, label %exit ; max signed i8
- i8 255, label %exit ; max unsigned i8
- ]
-exit:
- ret void
-}
-
-; CHECK-NEXT: define internal void @testUnsignedI8Values(i32 %p) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %a = trunc i32 %p to i8
-; CHECK-NEXT: switch i8 %a, label %exit [
-; CHECK-NEXT: i8 0, label %exit
-; CHECK-NEXT: i8 127, label %exit
-; ; Note that -1 is signed version of 255
-; CHECK-NEXT: i8 -1, label %exit
-; CHECK-NEXT: ]
-; CHECK-NEXT: exit:
-; CHECK-NEXT: ret void
-; CHECK-NEXT: }
-
-; Test values that cross unsigned i8 size boundaries.
-define internal void @testUnsignedI8Boundary(i32 %p) {
-entry:
- %a = trunc i32 %p to i8
- switch i8 %a, label %exit [
- i8 256, label %exit ; max unsigned i8
- ]
-exit:
- ret void
-}
-
-; CHECK-NEXT: define internal void @testUnsignedI8Boundary(i32 %p) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %a = trunc i32 %p to i8
-; CHECK-NEXT: switch i8 %a, label %exit [
-; CHECK-NEXT: i8 0, label %exit
-; CHECK-NEXT: ]
-; CHECK-NEXT: exit:
-; CHECK-NEXT: ret void
-; CHECK-NEXT: }
-
-define internal void @testI1Values(i32 %p) {
-entry:
- %a = trunc i32 %p to i1
- switch i1 %a, label %exit [
- i1 true, label %exit
- i1 false, label %exit
- ]
-exit:
- ret void
-}
-
-; CHECK-NEXT: define internal void @testI1Values(i32 %p) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %a = trunc i32 %p to i1
-; CHECK-NEXT: switch i1 %a, label %exit [
-; CHECK-NEXT: i1 -1, label %exit
-; CHECK-NEXT: i1 0, label %exit
-; CHECK-NEXT: ]
-; CHECK-NEXT: exit:
-; CHECK-NEXT: ret void
-; CHECK-NEXT: }
-
-; NOIR: Total across all functions
diff --git a/third_party/subzero/tests_lit/reader_tests/unnamed.ll b/third_party/subzero/tests_lit/reader_tests/unnamed.ll
deleted file mode 100644
index 3f4e1fd..0000000
--- a/third_party/subzero/tests_lit/reader_tests/unnamed.ll
+++ /dev/null
@@ -1,64 +0,0 @@
-; Tests that we name unnamed global addresses.
-
-; Check that Subzero's bitcode reader handles renaming correctly.
-; RUN: %p2i --no-local-syms -i %s --insts | FileCheck %s
-; RUN: %l2i --no-local-syms -i %s --insts | %ifl FileCheck %s
-
-; RUN: %l2i --no-local-syms -i %s --insts --args --exit-success \
-; RUN: -default-function-prefix=h -default-global-prefix=g \
-; RUN: | %ifl FileCheck --check-prefix=BAD %s
-
-; RUN: %p2i --no-local-syms -i %s --insts --args --exit-success \
-; RUN: -default-function-prefix=h -default-global-prefix=g \
-; RUN: | FileCheck --check-prefix=BAD %s
-
-; RUN: %p2i -i %s --args -notranslate -timing | \
-; RUN: FileCheck --check-prefix=NOIR %s
-
-; TODO(kschimpf) Check global variable declarations, once generated.
-
-@0 = internal global [4 x i8] zeroinitializer, align 4
-@1 = internal constant [10 x i8] c"Some stuff", align 1
-@g = internal global [4 x i8] zeroinitializer, align 4
-
-define internal i32 @2(i32 %v) {
- ret i32 %v
-}
-
-; CHECK: define internal i32 @Function(i32 %__0) {
-; CHECK-NEXT: __0:
-; CHECK-NEXT: ret i32 %__0
-; CHECK-NEXT: }
-
-define internal void @hg() {
- ret void
-}
-
-
-; CHECK-NEXT: define internal void @hg() {
-; CHECK-NEXT: __0:
-; CHECK-NEXT: ret void
-; CHECK-NEXT: }
-
-define internal void @3() {
- ret void
-}
-
-; CHECK-NEXT: define internal void @Function1() {
-; CHECK-NEXT: __0:
-; CHECK-NEXT: ret void
-; CHECK-NEXT: }
-
-define internal void @h5() {
- ret void
-}
-
-; CHECK-NEXT: define internal void @h5() {
-; CHECK-NEXT: __0:
-; CHECK-NEXT: ret void
-; CHECK-NEXT: }
-
-; BAD: Warning : Default global prefix 'g' potentially conflicts with name 'g'.
-; BAD: Warning : Default function prefix 'h' potentially conflicts with name 'h5'.
-
-; NOIR: Total across all functions
diff --git a/third_party/subzero/tests_lit/reader_tests/unreachable.ll b/third_party/subzero/tests_lit/reader_tests/unreachable.ll
deleted file mode 100644
index b9950bf..0000000
--- a/third_party/subzero/tests_lit/reader_tests/unreachable.ll
+++ /dev/null
@@ -1,31 +0,0 @@
-; Test parsing unreachable instruction.
-
-; RUN: %p2i -i %s --insts | FileCheck %s
-; RUN: %p2i -i %s --args -notranslate -timing | \
-; RUN: FileCheck --check-prefix=NOIR %s
-
-define internal i32 @divide(i32 %num, i32 %den) {
-entry:
- %cmp = icmp ne i32 %den, 0
- br i1 %cmp, label %return, label %abort
-
-abort: ; preds = %entry
- unreachable
-
-return: ; preds = %entry
- %div = sdiv i32 %num, %den
- ret i32 %div
-}
-
-; CHECK: define internal i32 @divide(i32 %num, i32 %den) {
-; CHECK-NEXT: entry:
-; CHECK-NEXT: %cmp = icmp ne i32 %den, 0
-; CHECK-NEXT: br i1 %cmp, label %return, label %abort
-; CHECK-NEXT: abort:
-; CHECK-NEXT: unreachable
-; CHECK-NEXT: return:
-; CHECK-NEXT: %div = sdiv i32 %num, %den
-; CHECK-NEXT: ret i32 %div
-; CHECK-NEXT: }
-
-; NOIR: Total across all functions
diff --git a/third_party/subzero/wasm-tests/hello-printf.c b/third_party/subzero/wasm-tests/hello-printf.c
deleted file mode 100644
index d0c89ee..0000000
--- a/third_party/subzero/wasm-tests/hello-printf.c
+++ /dev/null
@@ -1,6 +0,0 @@
-#include <stdio.h>
-
-int main(int argc, const char **argv) {
- printf("Hello, World!\n");
- return 0;
-}
diff --git a/third_party/subzero/wasm-tests/hello-putchar.c b/third_party/subzero/wasm-tests/hello-putchar.c
deleted file mode 100644
index fdeaa3b..0000000
--- a/third_party/subzero/wasm-tests/hello-putchar.c
+++ /dev/null
@@ -1,39 +0,0 @@
-#include <stdio.h>
-#include <string.h>
-#include <unistd.h>
-
-void write_int_(int fd, int n) {
- if (n > 0) {
- write_int_(fd, n / 10);
-
- int rem = n % 10;
- char c = '0' + rem;
- write(fd, &c, 1);
- }
-}
-
-void write_int(int fd, int n) {
- if (n == 0) {
- write(fd, "0", 1);
- } else {
- if (n < 0) {
- write(fd, "-", 1);
- write_int_(fd, -n);
- } else {
- write_int_(fd, n);
- }
- }
-}
-
-void stderr_int(int n) {
- write_int(2, n);
- write(2, "\n", 1);
-}
-
-int main(int argc, const char **argv) {
- char *str = "Hello, World!\n";
- for (int i = 0; str[i]; ++i) {
- putchar(str[i]);
- }
- return 0;
-}
diff --git a/third_party/subzero/wasm-tests/hello-puts.c b/third_party/subzero/wasm-tests/hello-puts.c
deleted file mode 100644
index fa5dc6a..0000000
--- a/third_party/subzero/wasm-tests/hello-puts.c
+++ /dev/null
@@ -1,10 +0,0 @@
-#include <stdio.h>
-#include <string.h>
-#include <unistd.h>
-
-int main(int argc, const char **argv) {
- fputs("Hello,", stdout);
- fputs(" ", stdout);
- fputs("world\n", stdout);
- return 0;
-}
diff --git a/third_party/subzero/wasm-tests/hello-write.c b/third_party/subzero/wasm-tests/hello-write.c
deleted file mode 100644
index ecbf75d..0000000
--- a/third_party/subzero/wasm-tests/hello-write.c
+++ /dev/null
@@ -1,10 +0,0 @@
-#include <stdio.h>
-#include <string.h>
-#include <unistd.h>
-
-int main(int argc, const char **argv) {
- char *str = "Hello, World!\n";
- const int len = strlen(str);
- write(1, str, len);
- return 0;
-}
diff --git a/third_party/subzero/wasm-tests/indirect.c b/third_party/subzero/wasm-tests/indirect.c
deleted file mode 100644
index 2b8753d..0000000
--- a/third_party/subzero/wasm-tests/indirect.c
+++ /dev/null
@@ -1,13 +0,0 @@
-int foo() { return 5; }
-
-int bar() { return 6; }
-
-int baz() { return 7; }
-
-int (*TABLE[])() = {foo, baz, bar, baz};
-
-int main(int argc, const char **argv) {
- int (*f)() = TABLE[argc - 1];
-
- return f();
-}
diff --git a/third_party/subzero/wasm-tests/write_loop.c b/third_party/subzero/wasm-tests/write_loop.c
deleted file mode 100644
index d398d6b..0000000
--- a/third_party/subzero/wasm-tests/write_loop.c
+++ /dev/null
@@ -1,14 +0,0 @@
-// This is derived from the loop in musl's __fwritex that looks for newlines.
-
-int puts(const char *s);
-
-int main(int argc, const char **argv) {
- const char *p = (const char *)argv;
- char *s = "Hello\nWorld";
- unsigned i = 0;
- // Depend on argc to avoid having this whole thing get dead-code-eliminated.
- for (i = 14 - argc; i && p[i - 1] != '\n'; i--)
- ;
- puts(s);
- return i;
-}
