Subzero: fix warnings for VS 2019 x86 build
Bug: b/142132927
Change-Id: If3d63a8327ef8940dbeee7b49c1099adda7feab2
Reviewed-on: https://swiftshader-review.googlesource.com/c/SwiftShader/+/37275
Tested-by: Antonio Maiorano <amaiorano@google.com>
Kokoro-Presubmit: kokoro <noreply+kokoro@google.com>
Reviewed-by: Alexis Hétu <sugoi@google.com>
diff --git a/third_party/subzero/src/IceGlobalContext.h b/third_party/subzero/src/IceGlobalContext.h
index 55b37d8..1843fd9 100644
--- a/third_party/subzero/src/IceGlobalContext.h
+++ b/third_party/subzero/src/IceGlobalContext.h
@@ -100,7 +100,7 @@
CodeStats() { reset(); }
void reset() { Stats.fill(0); }
void update(CSTag Tag, uint32_t Count = 1) {
- assert(Tag < Stats.size());
+ assert(static_cast<SizeT>(Tag) < Stats.size());
Stats[Tag] += Count;
}
void add(const CodeStats &Other) {
diff --git a/third_party/subzero/src/IceTargetLoweringX8632Traits.h b/third_party/subzero/src/IceTargetLoweringX8632Traits.h
index 092457d..8924692 100644
--- a/third_party/subzero/src/IceTargetLoweringX8632Traits.h
+++ b/third_party/subzero/src/IceTargetLoweringX8632Traits.h
@@ -509,7 +509,7 @@
(Trunc8RcvrRegisters)[Entry.Val] = Entry.IsTrunc8Rcvr;
(AhRcvrRegisters)[Entry.Val] = Entry.IsAhRcvr;
(*RegisterAliases)[Entry.Val].resize(RegisterSet::Reg_NUM);
- for (int J = 0; J < Entry.NumAliases; J++) {
+ for (SizeT J = 0; J < Entry.NumAliases; J++) {
SizeT Alias = Entry.Aliases[J];
assert(!(*RegisterAliases)[Entry.Val][Alias] && "Duplicate alias");
(*RegisterAliases)[Entry.Val].set(Alias);
@@ -730,7 +730,7 @@
/// representation of the vector.
static Type getInVectorElementType(Type Ty) {
assert(isVectorType(Ty));
- assert(Ty < TableTypeX8632AttributesSize);
+ assert(static_cast<size_t>(Ty) < TableTypeX8632AttributesSize);
return TableTypeX8632Attributes[Ty].InVectorElementType;
}
@@ -785,7 +785,7 @@
/// @}
static Cond::BrCond getIcmp32Mapping(InstIcmp::ICond Cond) {
- assert(Cond < TableIcmp32Size);
+ assert(static_cast<size_t>(Cond) < TableIcmp32Size);
return TableIcmp32[Cond].Mapping;
}
diff --git a/third_party/subzero/src/IceTargetLoweringX86BaseImpl.h b/third_party/subzero/src/IceTargetLoweringX86BaseImpl.h
index 523f80c..10ffe98 100644
--- a/third_party/subzero/src/IceTargetLoweringX86BaseImpl.h
+++ b/third_party/subzero/src/IceTargetLoweringX86BaseImpl.h
@@ -3414,7 +3414,7 @@
// ucomiss b, c /* but swap b,c order if SwapOperands==true */
// setcc a, C1
InstFcmp::FCond Condition = Fcmp->getCondition();
- assert(Condition < Traits::TableFcmpSize);
+ assert(static_cast<size_t>(Condition) < Traits::TableFcmpSize);
if (Traits::TableFcmp[Condition].SwapScalarOperands)
std::swap(Src0, Src1);
const bool HasC1 = (Traits::TableFcmp[Condition].C1 != Traits::Cond::Br_None);
@@ -3495,7 +3495,7 @@
llvm::report_fatal_error("Expected vector compare");
InstFcmp::FCond Condition = Fcmp->getCondition();
- assert(Condition < Traits::TableFcmpSize);
+ assert(static_cast<size_t>(Condition) < Traits::TableFcmpSize);
if (Traits::TableFcmp[Condition].SwapVectorOperands)
std::swap(Src0, Src1);
@@ -3721,7 +3721,7 @@
Operand *Src1 = legalize(Icmp->getSrc(1));
Variable *Dest = Icmp->getDest();
InstIcmp::ICond Condition = Icmp->getCondition();
- assert(Condition < Traits::TableIcmp64Size);
+ assert(static_cast<size_t>(Condition) < Traits::TableIcmp64Size);
Operand *Src0LoRM = nullptr;
Operand *Src0HiRM = nullptr;
// Legalize the portions of Src0 that are going to be needed.