Subzero: Transform suitable Load/Arith/Store sequences into RMW ops.
Search for sequences of Load/Arith/Store instructions that can be transformed into single non-atomic Read-Modify-Write instructions. Corresponding operands must match up, and it is limited to the operator/type combinations that have simple lowerings.
For suitable sequences, an RMW pseudo-instruction is added. Extra variables are attached to the RMW instruction and the original Store instruction, to make it easy to figure out whether to retain the original Store instruction or the new RMW instruction (but never both).
The RMW instructions are similar to their non-RMW counterparts, except that the RMW instruction has no Dest variable - the Src[0] operand doubles as the memory-operand dest.
The x86-32 integrated assembler has some new forms of existing instructions added.
Note: this CL puts the machinery in place to identify, lower, and emit RMW operations only for the "add" instruction operating on i32/i16/i8 operands. The next CL will fill in the rest of the options.
BUG= https://code.google.com/p/nativeclient/issues/detail?id=4095
R=jvoung@chromium.org
Review URL: https://codereview.chromium.org/1182603004
diff --git a/src/IceInst.h b/src/IceInst.h
index 948c5db..99a8653 100644
--- a/src/IceInst.h
+++ b/src/IceInst.h
@@ -691,13 +691,15 @@
public:
static InstStore *create(Cfg *Func, Operand *Data, Operand *Addr,
- uint32_t align = 1) {
+ uint32_t Align = 1) {
// TODO(kschimpf) Stop ignoring alignment specification.
- (void)align;
+ (void)Align;
return new (Func->allocate<InstStore>()) InstStore(Func, Data, Addr);
}
Operand *getAddr() const { return getSrc(1); }
Operand *getData() const { return getSrc(0); }
+ Variable *getRmwBeacon() const { return llvm::dyn_cast<Variable>(getSrc(2)); }
+ void setRmwBeacon(Variable *Beacon);
void dump(const Cfg *Func) const override;
static bool classof(const Inst *Inst) { return Inst->getKind() == Store; }
