third_party/llvm-7.0/llvm/test/CodeGen/ARM/fp16-litpool-thumb.mir

# RUN: llc -mtriple=thumbv7-none-eabi -run-pass=arm-cp-islands %s -o - | FileCheck %s
#
# This checks alignment of a new block when a big basic block is split up.
#
--- |
  ; ModuleID = '<stdin>'
  source_filename = "<stdin>"
  target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
  target triple = "thumbv7-arm--eabi"

  declare i32 @llvm.arm.space(i32, i32) #0

  define dso_local i32 @THUMB(i32 %A.coerce) local_unnamed_addr #1 {
  entry:
    %F = alloca float, align 4
    %S = alloca half, align 2
    %tmp.0.extract.trunc = trunc i32 %A.coerce to i16
    %0 = bitcast i16 %tmp.0.extract.trunc to half
    store volatile float 4.200000e+01, float* %F, align 4
    store volatile half 0xH3C00, half* %S, align 2
    %S.0.S.0.142 = load volatile half, half* %S, align 2
    %1 = call i32 @llvm.arm.space(i32 1230, i32 undef)
    %add42 = fadd half %S.0.S.0.142, 0xH2E66
    store volatile half %add42, half* %S, align 2
    %2 = call i32 @llvm.arm.space(i32 1330, i32 undef)
    %S.0.S.0.119 = load volatile half, half* %S, align 2
    %3 = bitcast half %add42 to i16
    %tmp87.0.insert.ext = zext i16 %3 to i32
    ret i32 %tmp87.0.insert.ext
  }

  attributes #0 = { nounwind }
  attributes #1 = { minsize nounwind optsize "target-features"="+crc,+crypto,+dsp,+fp-armv8,+fullfp16,+hwdiv,+hwdiv-arm,+neon,+ras,+strict-align,+thumb-mode" }

...
---
name:            THUMB
alignment:       1
tracksRegLiveness: true
frameInfo:
  stackSize:       8
  maxAlignment:    4
  maxCallFrameSize: 0
stack:
  - { id: 0, name: F, offset: -4, size: 4, alignment: 4, stack-id: 0, local-offset: -4 }
  - { id: 1, name: S, offset: -6, size: 2, alignment: 2, stack-id: 0, local-offset: -6 }
constants:
  - id:              0
    value:           i32 1109917696
    alignment:       4
  - id:              1
    value:           half 0xH2E66
    alignment:       2

#CHECK:  t2B %[[BB3:bb.[0-9]]]
#CHECK:  bb.{{.}} (align 2):
#CHECK:    successors:
#CHECK:    CONSTPOOL_ENTRY 2, %const.{{.}}, 4
#CHECK:  bb.{{.}} (align 1):
#CHECK:    successors:
#CHECK:    CONSTPOOL_ENTRY 3, %const.{{.}}, 2
#CHECK:  [[BB3]].entry (align 1):

body:             |
  bb.0.entry:
    $sp = frame-setup tSUBspi $sp, 2, 14, $noreg
    frame-setup CFI_INSTRUCTION def_cfa_offset 8
    renamable $r0 = tLDRpci %const.0, 14, $noreg :: (load 4 from constant-pool)
    renamable $s0 = FCONSTH 112, 14, $noreg
    tSTRspi killed renamable $r0, $sp, 1, 14, $noreg :: (volatile store 4 into %ir.F)
    VSTRH killed renamable $s0, $sp, 1, 14, $noreg :: (volatile store 2 into %ir.S)
    renamable $s2 = VLDRH $sp, 1, 14, $noreg :: (volatile dereferenceable load 2 from %ir.S)
    renamable $s0 = VLDRH %const.1, 0, 14, $noreg :: (load 2 from constant-pool)
    dead renamable $r0 = SPACE 1230, undef renamable $r0
    renamable $s0 = VADDH killed renamable $s2, killed renamable $s0, 14, $noreg
    VSTRH renamable $s0, $sp, 1, 14, $noreg :: (volatile store 2 into %ir.S)
    renamable $r0 = VMOVRH killed renamable $s0, 14, $noreg
    dead renamable $r1 = SPACE 1330, undef renamable $r0
    dead renamable $s0 = VLDRH $sp, 1, 14, $noreg :: (volatile dereferenceable load 2 from %ir.S)
    $sp = tADDspi $sp, 2, 14, $noreg
    tBX_RET 14, $noreg, implicit killed $r0

...