Subzero: clang-format src
Formatted using:
find ${DIR} -iname "*.cc" -o -iname "*.h" -o -iname "*.hpp" -o -iname "*.cpp" -o -iname "*.inl" | xargs ${CLANG_FORMAT} -i -style=file
Bug: b/144825072
Change-Id: Icda5e53cbbe0c95a24ca4e16750f2368f7daa0e1
Reviewed-on: https://swiftshader-review.googlesource.com/c/SwiftShader/+/50168
Reviewed-by: Nicolas Capens <nicolascapens@google.com>
Tested-by: Antonio Maiorano <amaiorano@google.com>
Kokoro-Result: kokoro <noreply+kokoro@google.com>
diff --git a/third_party/subzero/src/DartARM32/assembler_arm.cc b/third_party/subzero/src/DartARM32/assembler_arm.cc
index 961299e..70e301e 100644
--- a/third_party/subzero/src/DartARM32/assembler_arm.cc
+++ b/third_party/subzero/src/DartARM32/assembler_arm.cc
@@ -6,7 +6,7 @@
// Please update the (git) revision if we merge changes from Dart.
// https://code.google.com/p/dart/wiki/GettingTheSource
-#include "vm/globals.h" // NOLINT
+#include "vm/globals.h" // NOLINT
#if defined(TARGET_ARCH_ARM)
#include "vm/assembler.h"
@@ -45,9 +45,9 @@
uint32_t Address::vencoding() const {
ASSERT(kind_ == Immediate);
uint32_t offset = encoding_ & kOffset12Mask;
- ASSERT(offset < (1 << 10)); // In the range 0 to +1020.
- ASSERT(Utils::IsAligned(offset, 4)); // Multiple of 4.
- int mode = encoding_ & ((8|4|1) << 21);
+ ASSERT(offset < (1 << 10)); // In the range 0 to +1020.
+ ASSERT(Utils::IsAligned(offset, 4)); // Multiple of 4.
+ int mode = encoding_ & ((8 | 4 | 1) << 21);
ASSERT((mode == Offset) || (mode == NegOffset));
uint32_t vencoding = (encoding_ & (0xf << kRnShift)) | (offset >> 2);
if (mode == Offset) {
@@ -56,18 +56,16 @@
return vencoding;
}
-
void Assembler::InitializeMemoryWithBreakpoints(uword data, intptr_t length) {
ASSERT(Utils::IsAligned(data, 4));
ASSERT(Utils::IsAligned(length, 4));
const uword end = data + length;
while (data < end) {
- *reinterpret_cast<int32_t*>(data) = Instr::kBreakPointInstruction;
+ *reinterpret_cast<int32_t *>(data) = Instr::kBreakPointInstruction;
data += 4;
}
}
-
void Assembler::Emit(int32_t value) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
buffer_.Emit<int32_t>(value);
@@ -152,41 +150,31 @@
}
#endif
-void Assembler::EmitShiftImmediate(Condition cond,
- Shift opcode,
- Register rd,
- Register rm,
- Operand o) {
+void Assembler::EmitShiftImmediate(Condition cond, Shift opcode, Register rd,
+ Register rm, Operand o) {
ASSERT(cond != kNoCondition);
ASSERT(o.type() == 1);
- int32_t encoding = static_cast<int32_t>(cond) << kConditionShift |
- static_cast<int32_t>(MOV) << kOpcodeShift |
- static_cast<int32_t>(rd) << kRdShift |
- o.encoding() << kShiftImmShift |
- static_cast<int32_t>(opcode) << kShiftShift |
- static_cast<int32_t>(rm);
+ int32_t encoding =
+ static_cast<int32_t>(cond) << kConditionShift |
+ static_cast<int32_t>(MOV) << kOpcodeShift |
+ static_cast<int32_t>(rd) << kRdShift | o.encoding() << kShiftImmShift |
+ static_cast<int32_t>(opcode) << kShiftShift | static_cast<int32_t>(rm);
Emit(encoding);
}
-
-void Assembler::EmitShiftRegister(Condition cond,
- Shift opcode,
- Register rd,
- Register rm,
- Operand o) {
+void Assembler::EmitShiftRegister(Condition cond, Shift opcode, Register rd,
+ Register rm, Operand o) {
ASSERT(cond != kNoCondition);
ASSERT(o.type() == 0);
int32_t encoding = static_cast<int32_t>(cond) << kConditionShift |
static_cast<int32_t>(MOV) << kOpcodeShift |
static_cast<int32_t>(rd) << kRdShift |
o.encoding() << kShiftRegisterShift |
- static_cast<int32_t>(opcode) << kShiftShift |
- B4 |
+ static_cast<int32_t>(opcode) << kShiftShift | B4 |
static_cast<int32_t>(rm);
Emit(encoding);
}
-
#if 0
// Moved to ARM32::AssemblerARM32::and_()
void Assembler::and_(Register rd, Register rn, Operand o, Condition cond) {
@@ -243,7 +231,6 @@
EmitType01(cond, o.type(), SBC, 0, rn, rd, o);
}
-
void Assembler::sbcs(Register rd, Register rn, Operand o, Condition cond) {
EmitType01(cond, o.type(), SBC, 1, rn, rd, o);
}
@@ -296,7 +283,6 @@
EmitType01(cond, o.type(), MOV, 1, R0, rd, o);
}
-
#if 0
// Moved to ARM32::AssemblerARM32::bic()
void Assembler::bic(Register rd, Register rn, Operand o, Condition cond) {
@@ -405,8 +391,8 @@
}
#endif
-void Assembler::smull(Register rd_lo, Register rd_hi,
- Register rn, Register rm, Condition cond) {
+void Assembler::smull(Register rd_lo, Register rd_hi, Register rn, Register rm,
+ Condition cond) {
// Assembler registers rd_lo, rd_hi, rn, rm are encoded as rd, rn, rm, rs.
EmitMulOp(cond, B23 | B22, rd_lo, rd_hi, rn, rm);
}
@@ -420,15 +406,14 @@
}
#endif
-void Assembler::umlal(Register rd_lo, Register rd_hi,
- Register rn, Register rm, Condition cond) {
+void Assembler::umlal(Register rd_lo, Register rd_hi, Register rn, Register rm,
+ Condition cond) {
// Assembler registers rd_lo, rd_hi, rn, rm are encoded as rd, rn, rm, rs.
EmitMulOp(cond, B23 | B21, rd_lo, rd_hi, rn, rm);
}
-
-void Assembler::umaal(Register rd_lo, Register rd_hi,
- Register rn, Register rm) {
+void Assembler::umaal(Register rd_lo, Register rd_hi, Register rn,
+ Register rm) {
ASSERT(rd_lo != IP);
ASSERT(rd_hi != IP);
ASSERT(rn != IP);
@@ -444,7 +429,6 @@
}
}
-
#if 0
// Moved to ARM32::AssemblerARM32::emitDivOp()
void Assembler::EmitDivOp(Condition cond, int32_t opcode,
@@ -499,22 +483,18 @@
EmitMemOpAddressMode3(cond, L | B7 | H | B4, rd, ad);
}
-
void Assembler::strh(Register rd, Address ad, Condition cond) {
EmitMemOpAddressMode3(cond, B7 | H | B4, rd, ad);
}
-
void Assembler::ldrsb(Register rd, Address ad, Condition cond) {
EmitMemOpAddressMode3(cond, L | B7 | B6 | B4, rd, ad);
}
-
void Assembler::ldrsh(Register rd, Address ad, Condition cond) {
EmitMemOpAddressMode3(cond, L | B7 | B6 | H | B4, rd, ad);
}
-
void Assembler::ldrd(Register rd, Register rn, int32_t offset, Condition cond) {
ASSERT((rd % 2) == 0);
if (TargetCPUFeatures::arm_version() == ARMv5TE) {
@@ -526,7 +506,6 @@
}
}
-
void Assembler::strd(Register rd, Register rn, int32_t offset, Condition cond) {
ASSERT((rd % 2) == 0);
if (TargetCPUFeatures::arm_version() == ARMv5TE) {
@@ -591,8 +570,8 @@
void Assembler::clrex() {
ASSERT(TargetCPUFeatures::arm_version() != ARMv5TE);
- int32_t encoding = (kSpecialCondition << kConditionShift) |
- B26 | B24 | B22 | B21 | B20 | (0xff << 12) | B4 | 0xf;
+ int32_t encoding = (kSpecialCondition << kConditionShift) | B26 | B24 | B22 |
+ B21 | B20 | (0xff << 12) | B4 | 0xf;
Emit(encoding);
}
@@ -638,7 +617,6 @@
}
#endif
-
void Assembler::vmovsrr(SRegister sm, Register rt, Register rt2,
Condition cond) {
ASSERT(TargetCPUFeatures::vfp_supported());
@@ -651,16 +629,14 @@
ASSERT(rt2 != SP);
ASSERT(rt2 != PC);
ASSERT(cond != kNoCondition);
- int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
- B27 | B26 | B22 |
- (static_cast<int32_t>(rt2)*B16) |
- (static_cast<int32_t>(rt)*B12) | B11 | B9 |
- ((static_cast<int32_t>(sm) & 1)*B5) | B4 |
+ int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | B27 |
+ B26 | B22 | (static_cast<int32_t>(rt2) * B16) |
+ (static_cast<int32_t>(rt) * B12) | B11 | B9 |
+ ((static_cast<int32_t>(sm) & 1) * B5) | B4 |
(static_cast<int32_t>(sm) >> 1);
Emit(encoding);
}
-
void Assembler::vmovrrs(Register rt, Register rt2, SRegister sm,
Condition cond) {
ASSERT(TargetCPUFeatures::vfp_supported());
@@ -674,11 +650,10 @@
ASSERT(rt2 != PC);
ASSERT(rt != rt2);
ASSERT(cond != kNoCondition);
- int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
- B27 | B26 | B22 | B20 |
- (static_cast<int32_t>(rt2)*B16) |
- (static_cast<int32_t>(rt)*B12) | B11 | B9 |
- ((static_cast<int32_t>(sm) & 1)*B5) | B4 |
+ int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | B27 |
+ B26 | B22 | B20 | (static_cast<int32_t>(rt2) * B16) |
+ (static_cast<int32_t>(rt) * B12) | B11 | B9 |
+ ((static_cast<int32_t>(sm) & 1) * B5) | B4 |
(static_cast<int32_t>(sm) >> 1);
Emit(encoding);
}
@@ -790,44 +765,33 @@
ASSERT(static_cast<Register>(ad.encoding_ & (0xf << kRnShift)) != PC);
ASSERT(dd != kNoDRegister);
ASSERT(cond != kNoCondition);
- int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
- B27 | B26 | B24 |
- ((static_cast<int32_t>(dd) >> 4)*B22) |
- ((static_cast<int32_t>(dd) & 0xf)*B12) |
- B11 | B9 | B8 | ad.vencoding();
+ int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | B27 |
+ B26 | B24 | ((static_cast<int32_t>(dd) >> 4) * B22) |
+ ((static_cast<int32_t>(dd) & 0xf) * B12) | B11 | B9 | B8 |
+ ad.vencoding();
Emit(encoding);
}
-void Assembler::EmitMultiVSMemOp(Condition cond,
- BlockAddressMode am,
- bool load,
- Register base,
- SRegister start,
- uint32_t count) {
+void Assembler::EmitMultiVSMemOp(Condition cond, BlockAddressMode am, bool load,
+ Register base, SRegister start,
+ uint32_t count) {
ASSERT(TargetCPUFeatures::vfp_supported());
ASSERT(base != kNoRegister);
ASSERT(cond != kNoCondition);
ASSERT(start != kNoSRegister);
ASSERT(static_cast<int32_t>(start) + count <= kNumberOfSRegisters);
- int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
- B27 | B26 | B11 | B9 |
- am |
- (load ? L : 0) |
+ int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | B27 |
+ B26 | B11 | B9 | am | (load ? L : 0) |
(static_cast<int32_t>(base) << kRnShift) |
((static_cast<int32_t>(start) & 0x1) ? D : 0) |
- ((static_cast<int32_t>(start) >> 1) << 12) |
- count;
+ ((static_cast<int32_t>(start) >> 1) << 12) | count;
Emit(encoding);
}
-
-void Assembler::EmitMultiVDMemOp(Condition cond,
- BlockAddressMode am,
- bool load,
- Register base,
- DRegister start,
- int32_t count) {
+void Assembler::EmitMultiVDMemOp(Condition cond, BlockAddressMode am, bool load,
+ Register base, DRegister start,
+ int32_t count) {
ASSERT(TargetCPUFeatures::vfp_supported());
ASSERT(base != kNoRegister);
ASSERT(cond != kNoCondition);
@@ -835,45 +799,38 @@
ASSERT(static_cast<int32_t>(start) + count <= kNumberOfDRegisters);
const int armv5te = TargetCPUFeatures::arm_version() == ARMv5TE ? 1 : 0;
- int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) |
- B27 | B26 | B11 | B9 | B8 |
- am |
- (load ? L : 0) |
- (static_cast<int32_t>(base) << kRnShift) |
- ((static_cast<int32_t>(start) & 0x10) ? D : 0) |
- ((static_cast<int32_t>(start) & 0xf) << 12) |
- (count << 1) | armv5te;
+ int32_t encoding =
+ (static_cast<int32_t>(cond) << kConditionShift) | B27 | B26 | B11 | B9 |
+ B8 | am | (load ? L : 0) | (static_cast<int32_t>(base) << kRnShift) |
+ ((static_cast<int32_t>(start) & 0x10) ? D : 0) |
+ ((static_cast<int32_t>(start) & 0xf) << 12) | (count << 1) | armv5te;
Emit(encoding);
}
-
-void Assembler::vldms(BlockAddressMode am, Register base,
- SRegister first, SRegister last, Condition cond) {
+void Assembler::vldms(BlockAddressMode am, Register base, SRegister first,
+ SRegister last, Condition cond) {
ASSERT((am == IA) || (am == IA_W) || (am == DB_W));
ASSERT(last > first);
EmitMultiVSMemOp(cond, am, true, base, first, last - first + 1);
}
-
-void Assembler::vstms(BlockAddressMode am, Register base,
- SRegister first, SRegister last, Condition cond) {
+void Assembler::vstms(BlockAddressMode am, Register base, SRegister first,
+ SRegister last, Condition cond) {
ASSERT((am == IA) || (am == IA_W) || (am == DB_W));
ASSERT(last > first);
EmitMultiVSMemOp(cond, am, false, base, first, last - first + 1);
}
-
-void Assembler::vldmd(BlockAddressMode am, Register base,
- DRegister first, intptr_t count, Condition cond) {
+void Assembler::vldmd(BlockAddressMode am, Register base, DRegister first,
+ intptr_t count, Condition cond) {
ASSERT((am == IA) || (am == IA_W) || (am == DB_W));
ASSERT(count <= 16);
ASSERT(first + count <= kNumberOfDRegisters);
EmitMultiVDMemOp(cond, am, true, base, first, count);
}
-
-void Assembler::vstmd(BlockAddressMode am, Register base,
- DRegister first, intptr_t count, Condition cond) {
+void Assembler::vstmd(BlockAddressMode am, Register base, DRegister first,
+ intptr_t count, Condition cond) {
ASSERT((am == IA) || (am == IA_W) || (am == DB_W));
ASSERT(count <= 16);
ASSERT(first + count <= kNumberOfDRegisters);
@@ -1052,7 +1009,6 @@
EmitVFPsss(cond, B23 | B21 | B20 | B16 | B6, sd, S0, sm);
}
-
void Assembler::vnegd(DRegister dd, DRegister dm, Condition cond) {
EmitVFPddd(cond, B23 | B21 | B20 | B16 | B6, dd, D0, dm);
}
@@ -1183,30 +1139,27 @@
}
#endif
-void Assembler::vmstat(Condition cond) {
- vmrs(APSR, cond);
-}
-
+void Assembler::vmstat(Condition cond) { vmrs(APSR, cond); }
static inline int ShiftOfOperandSize(OperandSize size) {
switch (size) {
- case kByte:
- case kUnsignedByte:
- return 0;
- case kHalfword:
- case kUnsignedHalfword:
- return 1;
- case kWord:
- case kUnsignedWord:
- return 2;
- case kWordPair:
- return 3;
- case kSWord:
- case kDWord:
- return 0;
- default:
- UNREACHABLE();
- break;
+ case kByte:
+ case kUnsignedByte:
+ return 0;
+ case kHalfword:
+ case kUnsignedHalfword:
+ return 1;
+ case kWord:
+ case kUnsignedWord:
+ return 2;
+ case kWordPair:
+ return 3;
+ case kSWord:
+ case kDWord:
+ return 0;
+ default:
+ UNREACHABLE();
+ break;
}
UNREACHABLE();
@@ -1233,24 +1186,20 @@
}
#endif
-void Assembler::EmitSIMDddd(int32_t opcode, OperandSize size,
- DRegister dd, DRegister dn, DRegister dm) {
+void Assembler::EmitSIMDddd(int32_t opcode, OperandSize size, DRegister dd,
+ DRegister dn, DRegister dm) {
ASSERT(TargetCPUFeatures::neon_supported());
int sz = ShiftOfOperandSize(size);
int32_t encoding =
- (static_cast<int32_t>(kSpecialCondition) << kConditionShift) |
- B25 |
- opcode | ((sz & 0x3) * B20) |
- ((static_cast<int32_t>(dd) >> 4)*B22) |
- ((static_cast<int32_t>(dn) & 0xf)*B16) |
- ((static_cast<int32_t>(dd) & 0xf)*B12) |
- ((static_cast<int32_t>(dn) >> 4)*B7) |
- ((static_cast<int32_t>(dm) >> 4)*B5) |
- (static_cast<int32_t>(dm) & 0xf);
+ (static_cast<int32_t>(kSpecialCondition) << kConditionShift) | B25 |
+ opcode | ((sz & 0x3) * B20) | ((static_cast<int32_t>(dd) >> 4) * B22) |
+ ((static_cast<int32_t>(dn) & 0xf) * B16) |
+ ((static_cast<int32_t>(dd) & 0xf) * B12) |
+ ((static_cast<int32_t>(dn) >> 4) * B7) |
+ ((static_cast<int32_t>(dm) >> 4) * B5) | (static_cast<int32_t>(dm) & 0xf);
Emit(encoding);
}
-
void Assembler::vmovq(QRegister qd, QRegister qm) {
EmitSIMDqqq(B21 | B8 | B4, kByte, qd, qm, qm);
}
@@ -1268,12 +1217,11 @@
}
#endif
-void Assembler::vsubqi(OperandSize sz,
- QRegister qd, QRegister qn, QRegister qm) {
+void Assembler::vsubqi(OperandSize sz, QRegister qd, QRegister qn,
+ QRegister qm) {
EmitSIMDqqq(B24 | B11, sz, qd, qn, qm);
}
-
void Assembler::vsubqs(QRegister qd, QRegister qn, QRegister qm) {
EmitSIMDqqq(B21 | B11 | B10 | B8, kSWord, qd, qn, qm);
}
@@ -1329,12 +1277,10 @@
}
#endif
-
void Assembler::vminqs(QRegister qd, QRegister qn, QRegister qm) {
EmitSIMDqqq(B21 | B11 | B10 | B9 | B8, kSWord, qd, qn, qm);
}
-
void Assembler::vmaxqs(QRegister qd, QRegister qn, QRegister qm) {
EmitSIMDqqq(B11 | B10 | B9 | B8, kSWord, qd, qn, qm);
}
@@ -1353,75 +1299,66 @@
}
#endif
-
void Assembler::vrecpeqs(QRegister qd, QRegister qm) {
- EmitSIMDqqq(B24 | B23 | B21 | B20 | B19 | B17 | B16 | B10 | B8, kSWord,
- qd, Q0, qm);
+ EmitSIMDqqq(B24 | B23 | B21 | B20 | B19 | B17 | B16 | B10 | B8, kSWord, qd,
+ Q0, qm);
}
-
void Assembler::vrecpsqs(QRegister qd, QRegister qn, QRegister qm) {
EmitSIMDqqq(B11 | B10 | B9 | B8 | B4, kSWord, qd, qn, qm);
}
-
void Assembler::vrsqrteqs(QRegister qd, QRegister qm) {
- EmitSIMDqqq(B24 | B23 | B21 | B20 | B19 | B17 | B16 | B10 | B8 | B7,
- kSWord, qd, Q0, qm);
+ EmitSIMDqqq(B24 | B23 | B21 | B20 | B19 | B17 | B16 | B10 | B8 | B7, kSWord,
+ qd, Q0, qm);
}
-
void Assembler::vrsqrtsqs(QRegister qd, QRegister qn, QRegister qm) {
EmitSIMDqqq(B21 | B11 | B10 | B9 | B8 | B4, kSWord, qd, qn, qm);
}
-
void Assembler::vdup(OperandSize sz, QRegister qd, DRegister dm, int idx) {
ASSERT((sz != kDWord) && (sz != kSWord) && (sz != kWordPair));
int code = 0;
switch (sz) {
- case kByte:
- case kUnsignedByte: {
- ASSERT((idx >= 0) && (idx < 8));
- code = 1 | (idx << 1);
- break;
- }
- case kHalfword:
- case kUnsignedHalfword: {
- ASSERT((idx >= 0) && (idx < 4));
- code = 2 | (idx << 2);
- break;
- }
- case kWord:
- case kUnsignedWord: {
- ASSERT((idx >= 0) && (idx < 2));
- code = 4 | (idx << 3);
- break;
- }
- default: {
- break;
- }
+ case kByte:
+ case kUnsignedByte: {
+ ASSERT((idx >= 0) && (idx < 8));
+ code = 1 | (idx << 1);
+ break;
+ }
+ case kHalfword:
+ case kUnsignedHalfword: {
+ ASSERT((idx >= 0) && (idx < 4));
+ code = 2 | (idx << 2);
+ break;
+ }
+ case kWord:
+ case kUnsignedWord: {
+ ASSERT((idx >= 0) && (idx < 2));
+ code = 4 | (idx << 3);
+ break;
+ }
+ default: {
+ break;
+ }
}
EmitSIMDddd(B24 | B23 | B11 | B10 | B6, kWordPair,
static_cast<DRegister>(qd * 2),
- static_cast<DRegister>(code & 0xf),
- dm);
+ static_cast<DRegister>(code & 0xf), dm);
}
-
void Assembler::vtbl(DRegister dd, DRegister dn, int len, DRegister dm) {
ASSERT((len >= 1) && (len <= 4));
EmitSIMDddd(B24 | B23 | B11 | ((len - 1) * B8), kWordPair, dd, dn, dm);
}
-
void Assembler::vzipqw(QRegister qd, QRegister qm) {
EmitSIMDqqq(B24 | B23 | B21 | B20 | B19 | B17 | B8 | B7, kByte, qd, Q0, qm);
}
-
#if 0
// Moved to Arm32::AssemblerARM32::vceqqi().
void Assembler::vceqqi(OperandSize sz,
@@ -1474,12 +1411,10 @@
}
#endif
-
-void Assembler::b(Label* label, Condition cond) {
+void Assembler::b(Label *label, Condition cond) {
EmitBranch(cond, label, false);
}
-
#if 0
// Moved to ARM32::AssemblerARM32::bl()
void Assembler::bl(Label* label, Condition cond) {
@@ -1507,8 +1442,7 @@
}
#endif
-
-void Assembler::MarkExceptionHandler(Label* label) {
+void Assembler::MarkExceptionHandler(Label *label) {
EmitType01(AL, 1, TST, 1, PC, R0, Operand(0));
Label l;
b(&l);
@@ -1516,7 +1450,6 @@
Bind(&l);
}
-
void Assembler::Drop(intptr_t stack_elements) {
ASSERT(stack_elements >= 0);
if (stack_elements > 0) {
@@ -1524,16 +1457,12 @@
}
}
-
intptr_t Assembler::FindImmediate(int32_t imm) {
return object_pool_wrapper_.FindImmediate(imm);
}
-
// Uses a code sequence that can easily be decoded.
-void Assembler::LoadWordFromPoolOffset(Register rd,
- int32_t offset,
- Register pp,
+void Assembler::LoadWordFromPoolOffset(Register rd, int32_t offset, Register pp,
Condition cond) {
ASSERT((pp != PP) || constant_pool_allowed());
ASSERT(rd != pp);
@@ -1541,8 +1470,8 @@
if (Address::CanHoldLoadOffset(kWord, offset, &offset_mask)) {
ldr(rd, Address(pp, offset), cond);
} else {
- int32_t offset_hi = offset & ~offset_mask; // signed
- uint32_t offset_lo = offset & offset_mask; // unsigned
+ int32_t offset_hi = offset & ~offset_mask; // signed
+ uint32_t offset_lo = offset & offset_mask; // unsigned
// Inline a simplified version of AddImmediate(rd, pp, offset_hi).
Operand o;
if (Operand::CanHold(offset_hi, &o)) {
@@ -1566,7 +1495,7 @@
Bind(&cid_ok);
const intptr_t offset = CodeSize() + Instr::kPCReadOffset +
- Instructions::HeaderSize() - kHeapObjectTag;
+ Instructions::HeaderSize() - kHeapObjectTag;
mov(R0, Operand(PC));
AddImmediate(R0, R0, -offset);
ldr(IP, FieldAddress(CODE_REG, Code::saved_instructions_offset()));
@@ -1579,13 +1508,11 @@
#endif
}
-
void Assembler::RestoreCodePointer() {
ldr(CODE_REG, Address(FP, kPcMarkerSlotFromFp * kWordSize));
CheckCodePointer();
}
-
void Assembler::LoadPoolPointer(Register reg) {
// Load new pool pointer.
CheckCodePointer();
@@ -1593,13 +1520,11 @@
set_constant_pool_allowed(reg == PP);
}
-
void Assembler::LoadIsolate(Register rd) {
ldr(rd, Address(THR, Thread::isolate_offset()));
}
-
-bool Assembler::CanLoadFromObjectPool(const Object& object) const {
+bool Assembler::CanLoadFromObjectPool(const Object &object) const {
ASSERT(!Thread::CanLoadFromThread(object));
if (!constant_pool_allowed()) {
return false;
@@ -1610,12 +1535,8 @@
return true;
}
-
-void Assembler::LoadObjectHelper(Register rd,
- const Object& object,
- Condition cond,
- bool is_unique,
- Register pp) {
+void Assembler::LoadObjectHelper(Register rd, const Object &object,
+ Condition cond, bool is_unique, Register pp) {
// Load common VM constants from the thread. This works also in places where
// no constant pool is set up (e.g. intrinsic code).
if (Thread::CanLoadFromThread(object)) {
@@ -1629,8 +1550,8 @@
// Make sure that class CallPattern is able to decode this load from the
// object pool.
const int32_t offset = ObjectPool::element_offset(
- is_unique ? object_pool_wrapper_.AddObject(object)
- : object_pool_wrapper_.FindObject(object));
+ is_unique ? object_pool_wrapper_.AddObject(object)
+ : object_pool_wrapper_.FindObject(object));
LoadWordFromPoolOffset(rd, offset - kHeapObjectTag, pp, cond);
} else {
ASSERT(FLAG_allow_absolute_addresses);
@@ -1641,45 +1562,36 @@
}
}
-
-void Assembler::LoadObject(Register rd, const Object& object, Condition cond) {
+void Assembler::LoadObject(Register rd, const Object &object, Condition cond) {
LoadObjectHelper(rd, object, cond, /* is_unique = */ false, PP);
}
-
-void Assembler::LoadUniqueObject(Register rd,
- const Object& object,
+void Assembler::LoadUniqueObject(Register rd, const Object &object,
Condition cond) {
LoadObjectHelper(rd, object, cond, /* is_unique = */ true, PP);
}
-
void Assembler::LoadFunctionFromCalleePool(Register dst,
- const Function& function,
+ const Function &function,
Register new_pp) {
const int32_t offset =
ObjectPool::element_offset(object_pool_wrapper_.FindObject(function));
LoadWordFromPoolOffset(dst, offset - kHeapObjectTag, new_pp, AL);
}
-
-void Assembler::LoadNativeEntry(Register rd,
- const ExternalLabel* label,
- Patchability patchable,
- Condition cond) {
+void Assembler::LoadNativeEntry(Register rd, const ExternalLabel *label,
+ Patchability patchable, Condition cond) {
const int32_t offset = ObjectPool::element_offset(
object_pool_wrapper_.FindNativeEntry(label, patchable));
LoadWordFromPoolOffset(rd, offset - kHeapObjectTag, PP, cond);
}
-
-void Assembler::PushObject(const Object& object) {
+void Assembler::PushObject(const Object &object) {
LoadObject(IP, object);
Push(IP);
}
-
-void Assembler::CompareObject(Register rn, const Object& object) {
+void Assembler::CompareObject(Register rn, const Object &object) {
ASSERT(rn != IP);
if (object.IsSmi()) {
CompareImmediate(rn, reinterpret_cast<int32_t>(object.raw()));
@@ -1689,11 +1601,9 @@
}
}
-
// Preserves object and value registers.
-void Assembler::StoreIntoObjectFilterNoSmi(Register object,
- Register value,
- Label* no_update) {
+void Assembler::StoreIntoObjectFilterNoSmi(Register object, Register value,
+ Label *no_update) {
COMPILE_ASSERT((kNewObjectAlignmentOffset == kWordSize) &&
(kOldObjectAlignmentOffset == 0));
@@ -1706,11 +1616,9 @@
b(no_update, EQ);
}
-
// Preserves object and value registers.
-void Assembler::StoreIntoObjectFilter(Register object,
- Register value,
- Label* no_update) {
+void Assembler::StoreIntoObjectFilter(Register object, Register value,
+ Label *no_update) {
// For the value we are only interested in the new/old bit and the tag bit.
// And the new bit with the tag bit. The resulting bit will be 0 for a Smi.
and_(IP, value, Operand(value, LSL, kObjectAlignmentLog2 - 1));
@@ -1720,7 +1628,6 @@
b(no_update, EQ);
}
-
Operand Assembler::GetVerifiedMemoryShadow() {
Operand offset;
if (!Operand::CanHold(VerifiedMemory::offset(), &offset)) {
@@ -1729,11 +1636,8 @@
return offset;
}
-
-void Assembler::WriteShadowedField(Register base,
- intptr_t offset,
- Register value,
- Condition cond) {
+void Assembler::WriteShadowedField(Register base, intptr_t offset,
+ Register value, Condition cond) {
if (VerifiedMemory::enabled()) {
ASSERT(base != value);
Operand shadow(GetVerifiedMemoryShadow());
@@ -1744,11 +1648,8 @@
str(value, Address(base, offset), cond);
}
-
-void Assembler::WriteShadowedFieldPair(Register base,
- intptr_t offset,
- Register value_even,
- Register value_odd,
+void Assembler::WriteShadowedFieldPair(Register base, intptr_t offset,
+ Register value_even, Register value_odd,
Condition cond) {
ASSERT(value_odd == value_even + 1);
if (VerifiedMemory::enabled()) {
@@ -1762,8 +1663,7 @@
strd(value_even, base, offset, cond);
}
-
-Register UseRegister(Register reg, RegList* used) {
+Register UseRegister(Register reg, RegList *used) {
ASSERT(reg != SP);
ASSERT(reg != PC);
ASSERT((*used & (1 << reg)) == 0);
@@ -1771,17 +1671,15 @@
return reg;
}
-
-Register AllocateRegister(RegList* used) {
+Register AllocateRegister(RegList *used) {
const RegList free = ~*used;
- return (free == 0) ?
- kNoRegister :
- UseRegister(static_cast<Register>(Utils::CountTrailingZeros(free)), used);
+ return (free == 0) ? kNoRegister
+ : UseRegister(static_cast<Register>(
+ Utils::CountTrailingZeros(free)),
+ used);
}
-
-void Assembler::VerifiedWrite(const Address& address,
- Register new_value,
+void Assembler::VerifiedWrite(const Address &address, Register new_value,
FieldContent old_content) {
#if defined(DEBUG)
ASSERT(address.mode() == Address::Offset ||
@@ -1802,32 +1700,32 @@
tst(old_value, Operand(kHeapObjectTag));
Label ok;
switch (old_content) {
- case kOnlySmi:
- b(&ok, EQ); // Smi is OK.
- Stop("Expected smi.");
- break;
- case kHeapObjectOrSmi:
- b(&ok, EQ); // Smi is OK.
- // Non-smi case: Verify object pointer is word-aligned when untagged.
- COMPILE_ASSERT(kHeapObjectTag == 1);
- tst(old_value, Operand((kWordSize - 1) - kHeapObjectTag));
- b(&ok, EQ);
- Stop("Expected heap object or Smi");
- break;
- case kEmptyOrSmiOrNull:
- b(&ok, EQ); // Smi is OK.
- // Non-smi case: Check for the special zap word or null.
- // Note: Cannot use CompareImmediate, since IP may be in use.
- LoadImmediate(temp, Heap::kZap32Bits);
- cmp(old_value, Operand(temp));
- b(&ok, EQ);
- LoadObject(temp, Object::null_object());
- cmp(old_value, Operand(temp));
- b(&ok, EQ);
- Stop("Expected zapped, Smi or null");
- break;
- default:
- UNREACHABLE();
+ case kOnlySmi:
+ b(&ok, EQ); // Smi is OK.
+ Stop("Expected smi.");
+ break;
+ case kHeapObjectOrSmi:
+ b(&ok, EQ); // Smi is OK.
+ // Non-smi case: Verify object pointer is word-aligned when untagged.
+ COMPILE_ASSERT(kHeapObjectTag == 1);
+ tst(old_value, Operand((kWordSize - 1) - kHeapObjectTag));
+ b(&ok, EQ);
+ Stop("Expected heap object or Smi");
+ break;
+ case kEmptyOrSmiOrNull:
+ b(&ok, EQ); // Smi is OK.
+ // Non-smi case: Check for the special zap word or null.
+ // Note: Cannot use CompareImmediate, since IP may be in use.
+ LoadImmediate(temp, Heap::kZap32Bits);
+ cmp(old_value, Operand(temp));
+ b(&ok, EQ);
+ LoadObject(temp, Object::null_object());
+ cmp(old_value, Operand(temp));
+ b(&ok, EQ);
+ Stop("Expected zapped, Smi or null");
+ break;
+ default:
+ UNREACHABLE();
}
Bind(&ok);
if (VerifiedMemory::enabled()) {
@@ -1849,14 +1747,11 @@
PopList(used);
#else
str(new_value, address);
-#endif // DEBUG
+#endif // DEBUG
}
-
-void Assembler::StoreIntoObject(Register object,
- const Address& dest,
- Register value,
- bool can_value_be_smi) {
+void Assembler::StoreIntoObject(Register object, const Address &dest,
+ Register value, bool can_value_be_smi) {
ASSERT(object != value);
VerifiedWrite(dest, value, kHeapObjectOrSmi);
Label done;
@@ -1868,7 +1763,7 @@
// A store buffer update is required.
RegList regs = (1 << CODE_REG) | (1 << LR);
if (value != R0) {
- regs |= (1 << R0); // Preserve R0.
+ regs |= (1 << R0); // Preserve R0.
}
PushList(regs);
if (object != R0) {
@@ -1881,24 +1776,19 @@
Bind(&done);
}
-
-void Assembler::StoreIntoObjectOffset(Register object,
- int32_t offset,
- Register value,
- bool can_value_be_smi) {
+void Assembler::StoreIntoObjectOffset(Register object, int32_t offset,
+ Register value, bool can_value_be_smi) {
int32_t ignored = 0;
if (Address::CanHoldStoreOffset(kWord, offset - kHeapObjectTag, &ignored)) {
- StoreIntoObject(
- object, FieldAddress(object, offset), value, can_value_be_smi);
+ StoreIntoObject(object, FieldAddress(object, offset), value,
+ can_value_be_smi);
} else {
AddImmediate(IP, object, offset - kHeapObjectTag);
StoreIntoObject(object, Address(IP), value, can_value_be_smi);
}
}
-
-void Assembler::StoreIntoObjectNoBarrier(Register object,
- const Address& dest,
+void Assembler::StoreIntoObjectNoBarrier(Register object, const Address &dest,
Register value,
FieldContent old_content) {
VerifiedWrite(dest, value, old_content);
@@ -1907,13 +1797,11 @@
StoreIntoObjectFilter(object, value, &done);
Stop("Store buffer update is required");
Bind(&done);
-#endif // defined(DEBUG)
+#endif // defined(DEBUG)
// No store buffer update.
}
-
-void Assembler::StoreIntoObjectNoBarrierOffset(Register object,
- int32_t offset,
+void Assembler::StoreIntoObjectNoBarrierOffset(Register object, int32_t offset,
Register value,
FieldContent old_content) {
int32_t ignored = 0;
@@ -1926,10 +1814,8 @@
}
}
-
-void Assembler::StoreIntoObjectNoBarrier(Register object,
- const Address& dest,
- const Object& value,
+void Assembler::StoreIntoObjectNoBarrier(Register object, const Address &dest,
+ const Object &value,
FieldContent old_content) {
ASSERT(value.IsSmi() || value.InVMHeap() ||
(value.IsOld() && value.IsNotTemporaryScopedHandle()));
@@ -1938,10 +1824,8 @@
VerifiedWrite(dest, IP, old_content);
}
-
-void Assembler::StoreIntoObjectNoBarrierOffset(Register object,
- int32_t offset,
- const Object& value,
+void Assembler::StoreIntoObjectNoBarrierOffset(Register object, int32_t offset,
+ const Object &value,
FieldContent old_content) {
int32_t ignored = 0;
if (Address::CanHoldStoreOffset(kWord, offset - kHeapObjectTag, &ignored)) {
@@ -1953,11 +1837,8 @@
}
}
-
-void Assembler::InitializeFieldsNoBarrier(Register object,
- Register begin,
- Register end,
- Register value_even,
+void Assembler::InitializeFieldsNoBarrier(Register object, Register begin,
+ Register end, Register value_even,
Register value_odd) {
ASSERT(value_odd == value_even + 1);
Label init_loop;
@@ -1973,22 +1854,18 @@
StoreIntoObjectFilter(object, value_odd, &done);
Stop("Store buffer update is required");
Bind(&done);
-#endif // defined(DEBUG)
+#endif // defined(DEBUG)
// No store buffer update.
}
-
-void Assembler::InitializeFieldsNoBarrierUnrolled(Register object,
- Register base,
- intptr_t begin_offset,
- intptr_t end_offset,
- Register value_even,
- Register value_odd) {
+void Assembler::InitializeFieldsNoBarrierUnrolled(
+ Register object, Register base, intptr_t begin_offset, intptr_t end_offset,
+ Register value_even, Register value_odd) {
ASSERT(value_odd == value_even + 1);
intptr_t current_offset = begin_offset;
while (current_offset + kWordSize < end_offset) {
WriteShadowedFieldPair(base, current_offset, value_even, value_odd);
- current_offset += 2*kWordSize;
+ current_offset += 2 * kWordSize;
}
while (current_offset < end_offset) {
WriteShadowedField(base, current_offset, value_even);
@@ -2000,32 +1877,29 @@
StoreIntoObjectFilter(object, value_odd, &done);
Stop("Store buffer update is required");
Bind(&done);
-#endif // defined(DEBUG)
+#endif // defined(DEBUG)
// No store buffer update.
}
-
-void Assembler::StoreIntoSmiField(const Address& dest, Register value) {
+void Assembler::StoreIntoSmiField(const Address &dest, Register value) {
#if defined(DEBUG)
Label done;
tst(value, Operand(kHeapObjectTag));
b(&done, EQ);
Stop("New value must be Smi.");
Bind(&done);
-#endif // defined(DEBUG)
+#endif // defined(DEBUG)
VerifiedWrite(dest, value, kOnlySmi);
}
-
void Assembler::LoadClassId(Register result, Register object, Condition cond) {
ASSERT(RawObject::kClassIdTagPos == 16);
ASSERT(RawObject::kClassIdTagSize == 16);
- const intptr_t class_id_offset = Object::tags_offset() +
- RawObject::kClassIdTagPos / kBitsPerByte;
+ const intptr_t class_id_offset =
+ Object::tags_offset() + RawObject::kClassIdTagPos / kBitsPerByte;
ldrh(result, FieldAddress(object, class_id_offset), cond);
}
-
void Assembler::LoadClassById(Register result, Register class_id) {
ASSERT(result != class_id);
LoadIsolate(result);
@@ -2035,39 +1909,31 @@
ldr(result, Address(result, class_id, LSL, 2));
}
-
void Assembler::LoadClass(Register result, Register object, Register scratch) {
ASSERT(scratch != result);
LoadClassId(scratch, object);
LoadClassById(result, scratch);
}
-
-void Assembler::CompareClassId(Register object,
- intptr_t class_id,
+void Assembler::CompareClassId(Register object, intptr_t class_id,
Register scratch) {
LoadClassId(scratch, object);
CompareImmediate(scratch, class_id);
}
-
void Assembler::LoadClassIdMayBeSmi(Register result, Register object) {
tst(object, Operand(kSmiTagMask));
LoadClassId(result, object, NE);
LoadImmediate(result, kSmiCid, EQ);
}
-
void Assembler::LoadTaggedClassIdMayBeSmi(Register result, Register object) {
LoadClassIdMayBeSmi(result, object);
SmiTag(result);
}
-
-void Assembler::ComputeRange(Register result,
- Register value,
- Register scratch,
- Label* not_mint) {
+void Assembler::ComputeRange(Register result, Register value, Register scratch,
+ Label *not_mint) {
const Register hi = TMP;
const Register lo = scratch;
@@ -2082,24 +1948,19 @@
rsb(result, hi, Operand(ICData::kInt32RangeBit));
cmp(hi, Operand(lo, ASR, kBitsPerWord - 1));
b(&done, EQ);
- LoadImmediate(result, ICData::kUint32RangeBit); // Uint32
+ LoadImmediate(result, ICData::kUint32RangeBit); // Uint32
tst(hi, Operand(hi));
- LoadImmediate(result, ICData::kInt64RangeBit, NE); // Int64
+ LoadImmediate(result, ICData::kInt64RangeBit, NE); // Int64
Bind(&done);
}
-
-void Assembler::UpdateRangeFeedback(Register value,
- intptr_t index,
- Register ic_data,
- Register scratch1,
- Register scratch2,
- Label* miss) {
+void Assembler::UpdateRangeFeedback(Register value, intptr_t index,
+ Register ic_data, Register scratch1,
+ Register scratch2, Label *miss) {
ASSERT(ICData::IsValidRangeFeedbackIndex(index));
ComputeRange(scratch1, value, scratch2, miss);
ldr(scratch2, FieldAddress(ic_data, ICData::state_bits_offset()));
- orr(scratch2,
- scratch2,
+ orr(scratch2, scratch2,
Operand(scratch1, LSL, ICData::RangeFeedbackShift(index)));
str(scratch2, FieldAddress(ic_data, ICData::state_bits_offset()));
}
@@ -2146,9 +2007,8 @@
return offset;
}
-
-static int32_t DecodeARMv6LoadImmediate(int32_t mov, int32_t or1,
- int32_t or2, int32_t or3) {
+static int32_t DecodeARMv6LoadImmediate(int32_t mov, int32_t or1, int32_t or2,
+ int32_t or3) {
int32_t offset = 0;
offset |= (mov & 0xff) << 24;
offset |= (or1 & 0xff) << 16;
@@ -2157,12 +2017,11 @@
return offset;
}
-
class PatchFarBranch : public AssemblerFixup {
- public:
+public:
PatchFarBranch() {}
- void Process(const MemoryRegion& region, intptr_t position) {
+ void Process(const MemoryRegion ®ion, intptr_t position) {
const ARMVersion version = TargetCPUFeatures::arm_version();
if ((version == ARMv5TE) || (version == ARMv6)) {
ProcessARMv6(region, position);
@@ -2172,18 +2031,18 @@
}
}
- private:
- void ProcessARMv6(const MemoryRegion& region, intptr_t position) {
+private:
+ void ProcessARMv6(const MemoryRegion ®ion, intptr_t position) {
const int32_t mov = region.Load<int32_t>(position);
- const int32_t or1 = region.Load<int32_t>(position + 1*Instr::kInstrSize);
- const int32_t or2 = region.Load<int32_t>(position + 2*Instr::kInstrSize);
- const int32_t or3 = region.Load<int32_t>(position + 3*Instr::kInstrSize);
- const int32_t bx = region.Load<int32_t>(position + 4*Instr::kInstrSize);
+ const int32_t or1 = region.Load<int32_t>(position + 1 * Instr::kInstrSize);
+ const int32_t or2 = region.Load<int32_t>(position + 2 * Instr::kInstrSize);
+ const int32_t or3 = region.Load<int32_t>(position + 3 * Instr::kInstrSize);
+ const int32_t bx = region.Load<int32_t>(position + 4 * Instr::kInstrSize);
- if (((mov & 0xffffff00) == 0xe3a0c400) && // mov IP, (byte3 rot 4)
- ((or1 & 0xffffff00) == 0xe38cc800) && // orr IP, IP, (byte2 rot 8)
- ((or2 & 0xffffff00) == 0xe38ccc00) && // orr IP, IP, (byte1 rot 12)
- ((or3 & 0xffffff00) == 0xe38cc000)) { // orr IP, IP, byte0
+ if (((mov & 0xffffff00) == 0xe3a0c400) && // mov IP, (byte3 rot 4)
+ ((or1 & 0xffffff00) == 0xe38cc800) && // orr IP, IP, (byte2 rot 8)
+ ((or2 & 0xffffff00) == 0xe38ccc00) && // orr IP, IP, (byte1 rot 12)
+ ((or3 & 0xffffff00) == 0xe38cc000)) { // orr IP, IP, byte0
const int32_t offset = DecodeARMv6LoadImmediate(mov, or1, or2, or3);
const int32_t dest = region.start() + offset;
const int32_t dest0 = (dest & 0x000000ff);
@@ -2205,20 +2064,17 @@
// If the offset loading instructions aren't there, we must have replaced
// the far branch with a near one, and so these instructions
// should be NOPs.
- ASSERT((or1 == Instr::kNopInstruction) &&
- (or2 == Instr::kNopInstruction) &&
- (or3 == Instr::kNopInstruction) &&
- (bx == Instr::kNopInstruction));
+ ASSERT((or1 == Instr::kNopInstruction) && (or2 == Instr::kNopInstruction) &&
+ (or3 == Instr::kNopInstruction) && (bx == Instr::kNopInstruction));
}
-
- void ProcessARMv7(const MemoryRegion& region, intptr_t position) {
+ void ProcessARMv7(const MemoryRegion ®ion, intptr_t position) {
const int32_t movw = region.Load<int32_t>(position);
const int32_t movt = region.Load<int32_t>(position + Instr::kInstrSize);
const int32_t bx = region.Load<int32_t>(position + 2 * Instr::kInstrSize);
- if (((movt & 0xfff0f000) == 0xe340c000) && // movt IP, high
- ((movw & 0xfff0f000) == 0xe300c000)) { // movw IP, low
+ if (((movt & 0xfff0f000) == 0xe340c000) && // movt IP, high
+ ((movw & 0xfff0f000) == 0xe300c000)) { // movw IP, low
const int32_t offset = DecodeARMv7LoadImmediate(movt, movw);
const int32_t dest = region.start() + offset;
const uint16_t dest_high = Utils::High16Bits(dest);
@@ -2236,14 +2092,12 @@
// If the offset loading instructions aren't there, we must have replaced
// the far branch with a near one, and so these instructions
// should be NOPs.
- ASSERT((movt == Instr::kNopInstruction) &&
- (bx == Instr::kNopInstruction));
+ ASSERT((movt == Instr::kNopInstruction) && (bx == Instr::kNopInstruction));
}
virtual bool IsPointerOffset() const { return false; }
};
-
void Assembler::EmitFarBranch(Condition cond, int32_t offset, bool link) {
buffer_.EmitFixup(new PatchFarBranch());
LoadPatchableImmediate(IP, offset);
@@ -2254,8 +2108,7 @@
}
}
-
-void Assembler::EmitBranch(Condition cond, Label* label, bool link) {
+void Assembler::EmitBranch(Condition cond, Label *label, bool link) {
if (label->IsBound()) {
const int32_t dest = label->Position() - buffer_.Size();
if (use_far_branches() && !CanEncodeBranchOffset(dest)) {
@@ -2276,8 +2129,7 @@
}
}
-
-void Assembler::BindARMv6(Label* label) {
+void Assembler::BindARMv6(Label *label) {
ASSERT(!label->IsBound());
intptr_t bound_pc = buffer_.Size();
while (label->IsLinked()) {
@@ -2287,8 +2139,7 @@
// Far branches are enabled and we can't encode the branch offset.
// Grab instructions that load the offset.
- const int32_t mov =
- buffer_.Load<int32_t>(position);
+ const int32_t mov = buffer_.Load<int32_t>(position);
const int32_t or1 =
buffer_.Load<int32_t>(position + 1 * Instr::kInstrSize);
const int32_t or2 =
@@ -2316,8 +2167,7 @@
label->position_ = DecodeARMv6LoadImmediate(mov, or1, or2, or3);
} else if (use_far_branches() && CanEncodeBranchOffset(dest)) {
// Grab instructions that load the offset, and the branch.
- const int32_t mov =
- buffer_.Load<int32_t>(position);
+ const int32_t mov = buffer_.Load<int32_t>(position);
const int32_t or1 =
buffer_.Load<int32_t>(position + 1 * Instr::kInstrSize);
const int32_t or2 =
@@ -2338,13 +2188,13 @@
// Write the encoded branch instruction followed by two nops.
buffer_.Store<int32_t>(position, encoded);
buffer_.Store<int32_t>(position + 1 * Instr::kInstrSize,
- Instr::kNopInstruction);
+ Instr::kNopInstruction);
buffer_.Store<int32_t>(position + 2 * Instr::kInstrSize,
- Instr::kNopInstruction);
+ Instr::kNopInstruction);
buffer_.Store<int32_t>(position + 3 * Instr::kInstrSize,
- Instr::kNopInstruction);
+ Instr::kNopInstruction);
buffer_.Store<int32_t>(position + 4 * Instr::kInstrSize,
- Instr::kNopInstruction);
+ Instr::kNopInstruction);
label->position_ = DecodeARMv6LoadImmediate(mov, or1, or2, or3);
} else {
@@ -2429,8 +2279,7 @@
}
#endif
-
-void Assembler::Bind(Label* label) {
+void Assembler::Bind(Label *label) {
const ARMVersion version = TargetCPUFeatures::arm_version();
if ((version == ARMv5TE) || (version == ARMv6)) {
BindARMv6(label);
@@ -2440,127 +2289,121 @@
}
}
-
OperandSize Address::OperandSizeFor(intptr_t cid) {
switch (cid) {
- case kArrayCid:
- case kImmutableArrayCid:
- return kWord;
- case kOneByteStringCid:
- case kExternalOneByteStringCid:
- return kByte;
- case kTwoByteStringCid:
- case kExternalTwoByteStringCid:
- return kHalfword;
- case kTypedDataInt8ArrayCid:
- return kByte;
- case kTypedDataUint8ArrayCid:
- case kTypedDataUint8ClampedArrayCid:
- case kExternalTypedDataUint8ArrayCid:
- case kExternalTypedDataUint8ClampedArrayCid:
- return kUnsignedByte;
- case kTypedDataInt16ArrayCid:
- return kHalfword;
- case kTypedDataUint16ArrayCid:
- return kUnsignedHalfword;
- case kTypedDataInt32ArrayCid:
- return kWord;
- case kTypedDataUint32ArrayCid:
- return kUnsignedWord;
- case kTypedDataInt64ArrayCid:
- case kTypedDataUint64ArrayCid:
- UNREACHABLE();
- return kByte;
- case kTypedDataFloat32ArrayCid:
- return kSWord;
- case kTypedDataFloat64ArrayCid:
- return kDWord;
- case kTypedDataFloat32x4ArrayCid:
- case kTypedDataInt32x4ArrayCid:
- case kTypedDataFloat64x2ArrayCid:
- return kRegList;
- case kTypedDataInt8ArrayViewCid:
- UNREACHABLE();
- return kByte;
- default:
- UNREACHABLE();
- return kByte;
+ case kArrayCid:
+ case kImmutableArrayCid:
+ return kWord;
+ case kOneByteStringCid:
+ case kExternalOneByteStringCid:
+ return kByte;
+ case kTwoByteStringCid:
+ case kExternalTwoByteStringCid:
+ return kHalfword;
+ case kTypedDataInt8ArrayCid:
+ return kByte;
+ case kTypedDataUint8ArrayCid:
+ case kTypedDataUint8ClampedArrayCid:
+ case kExternalTypedDataUint8ArrayCid:
+ case kExternalTypedDataUint8ClampedArrayCid:
+ return kUnsignedByte;
+ case kTypedDataInt16ArrayCid:
+ return kHalfword;
+ case kTypedDataUint16ArrayCid:
+ return kUnsignedHalfword;
+ case kTypedDataInt32ArrayCid:
+ return kWord;
+ case kTypedDataUint32ArrayCid:
+ return kUnsignedWord;
+ case kTypedDataInt64ArrayCid:
+ case kTypedDataUint64ArrayCid:
+ UNREACHABLE();
+ return kByte;
+ case kTypedDataFloat32ArrayCid:
+ return kSWord;
+ case kTypedDataFloat64ArrayCid:
+ return kDWord;
+ case kTypedDataFloat32x4ArrayCid:
+ case kTypedDataInt32x4ArrayCid:
+ case kTypedDataFloat64x2ArrayCid:
+ return kRegList;
+ case kTypedDataInt8ArrayViewCid:
+ UNREACHABLE();
+ return kByte;
+ default:
+ UNREACHABLE();
+ return kByte;
}
}
-
-bool Address::CanHoldLoadOffset(OperandSize size,
- int32_t offset,
- int32_t* offset_mask) {
+bool Address::CanHoldLoadOffset(OperandSize size, int32_t offset,
+ int32_t *offset_mask) {
switch (size) {
- case kByte:
- case kHalfword:
- case kUnsignedHalfword:
- case kWordPair: {
- *offset_mask = 0xff;
- return Utils::IsAbsoluteUint(8, offset); // Addressing mode 3.
- }
- case kUnsignedByte:
- case kWord:
- case kUnsignedWord: {
- *offset_mask = 0xfff;
- return Utils::IsAbsoluteUint(12, offset); // Addressing mode 2.
- }
- case kSWord:
- case kDWord: {
- *offset_mask = 0x3fc; // Multiple of 4.
- // VFP addressing mode.
- return (Utils::IsAbsoluteUint(10, offset) && Utils::IsAligned(offset, 4));
- }
- case kRegList: {
- *offset_mask = 0x0;
- return offset == 0;
- }
- default: {
- UNREACHABLE();
- return false;
- }
+ case kByte:
+ case kHalfword:
+ case kUnsignedHalfword:
+ case kWordPair: {
+ *offset_mask = 0xff;
+ return Utils::IsAbsoluteUint(8, offset); // Addressing mode 3.
+ }
+ case kUnsignedByte:
+ case kWord:
+ case kUnsignedWord: {
+ *offset_mask = 0xfff;
+ return Utils::IsAbsoluteUint(12, offset); // Addressing mode 2.
+ }
+ case kSWord:
+ case kDWord: {
+ *offset_mask = 0x3fc; // Multiple of 4.
+ // VFP addressing mode.
+ return (Utils::IsAbsoluteUint(10, offset) && Utils::IsAligned(offset, 4));
+ }
+ case kRegList: {
+ *offset_mask = 0x0;
+ return offset == 0;
+ }
+ default: {
+ UNREACHABLE();
+ return false;
+ }
}
}
-
-bool Address::CanHoldStoreOffset(OperandSize size,
- int32_t offset,
- int32_t* offset_mask) {
+bool Address::CanHoldStoreOffset(OperandSize size, int32_t offset,
+ int32_t *offset_mask) {
switch (size) {
- case kHalfword:
- case kUnsignedHalfword:
- case kWordPair: {
- *offset_mask = 0xff;
- return Utils::IsAbsoluteUint(8, offset); // Addressing mode 3.
- }
- case kByte:
- case kUnsignedByte:
- case kWord:
- case kUnsignedWord: {
- *offset_mask = 0xfff;
- return Utils::IsAbsoluteUint(12, offset); // Addressing mode 2.
- }
- case kSWord:
- case kDWord: {
- *offset_mask = 0x3fc; // Multiple of 4.
- // VFP addressing mode.
- return (Utils::IsAbsoluteUint(10, offset) && Utils::IsAligned(offset, 4));
- }
- case kRegList: {
- *offset_mask = 0x0;
- return offset == 0;
- }
- default: {
- UNREACHABLE();
- return false;
- }
+ case kHalfword:
+ case kUnsignedHalfword:
+ case kWordPair: {
+ *offset_mask = 0xff;
+ return Utils::IsAbsoluteUint(8, offset); // Addressing mode 3.
+ }
+ case kByte:
+ case kUnsignedByte:
+ case kWord:
+ case kUnsignedWord: {
+ *offset_mask = 0xfff;
+ return Utils::IsAbsoluteUint(12, offset); // Addressing mode 2.
+ }
+ case kSWord:
+ case kDWord: {
+ *offset_mask = 0x3fc; // Multiple of 4.
+ // VFP addressing mode.
+ return (Utils::IsAbsoluteUint(10, offset) && Utils::IsAligned(offset, 4));
+ }
+ case kRegList: {
+ *offset_mask = 0x0;
+ return offset == 0;
+ }
+ default: {
+ UNREACHABLE();
+ return false;
+ }
}
}
-
-bool Address::CanHoldImmediateOffset(
- bool is_load, intptr_t cid, int64_t offset) {
+bool Address::CanHoldImmediateOffset(bool is_load, intptr_t cid,
+ int64_t offset) {
int32_t offset_mask = 0;
if (is_load) {
return CanHoldLoadOffset(OperandSizeFor(cid), offset, &offset_mask);
@@ -2641,13 +2484,13 @@
}
#endif
-void Assembler::Asrs(Register rd, Register rm, const Operand& shift_imm,
+void Assembler::Asrs(Register rd, Register rm, const Operand &shift_imm,
Condition cond) {
ASSERT(shift_imm.type() == 1);
uint32_t shift = shift_imm.encoding();
- ASSERT(shift != 0); // Do not use Asr if no shift is wanted.
+ ASSERT(shift != 0); // Do not use Asr if no shift is wanted.
if (shift == 32) {
- shift = 0; // Comply to UAL syntax.
+ shift = 0; // Comply to UAL syntax.
}
movs(rd, Operand(rm, ASR, shift), cond);
}
@@ -2659,29 +2502,25 @@
}
#endif
-void Assembler::Ror(Register rd, Register rm, const Operand& shift_imm,
+void Assembler::Ror(Register rd, Register rm, const Operand &shift_imm,
Condition cond) {
ASSERT(shift_imm.type() == 1);
- ASSERT(shift_imm.encoding() != 0); // Use Rrx instruction.
+ ASSERT(shift_imm.encoding() != 0); // Use Rrx instruction.
mov(rd, Operand(rm, ROR, shift_imm.encoding()), cond);
}
-
void Assembler::Ror(Register rd, Register rm, Register rs, Condition cond) {
mov(rd, Operand(rm, ROR, rs), cond);
}
-
void Assembler::Rrx(Register rd, Register rm, Condition cond) {
mov(rd, Operand(rm, ROR, 0), cond);
}
-
void Assembler::SignFill(Register rd, Register rm, Condition cond) {
Asr(rd, rm, Operand(31), cond);
}
-
void Assembler::Vreciprocalqs(QRegister qd, QRegister qm) {
ASSERT(qm != QTMP);
ASSERT(qd != QTMP);
@@ -2695,7 +2534,6 @@
vmulqs(qd, qd, QTMP);
}
-
void Assembler::VreciprocalSqrtqs(QRegister qd, QRegister qm) {
ASSERT(qm != QTMP);
ASSERT(qd != QTMP);
@@ -2704,16 +2542,15 @@
vrsqrteqs(qd, qm);
// 2 Newton-Raphson steps. xn+1 = xn * (3 - Q1*xn^2) / 2.
// First step.
- vmulqs(QTMP, qd, qd); // QTMP <- xn^2
- vrsqrtsqs(QTMP, qm, QTMP); // QTMP <- (3 - Q1*QTMP) / 2.
- vmulqs(qd, qd, QTMP); // xn+1 <- xn * QTMP
+ vmulqs(QTMP, qd, qd); // QTMP <- xn^2
+ vrsqrtsqs(QTMP, qm, QTMP); // QTMP <- (3 - Q1*QTMP) / 2.
+ vmulqs(qd, qd, QTMP); // xn+1 <- xn * QTMP
// Second step.
vmulqs(QTMP, qd, qd);
vrsqrtsqs(QTMP, qm, QTMP);
vmulqs(qd, qd, QTMP);
}
-
void Assembler::Vsqrtqs(QRegister qd, QRegister qm, QRegister temp) {
ASSERT(temp != QTMP);
ASSERT(qm != QTMP);
@@ -2729,7 +2566,6 @@
Vreciprocalqs(qd, qm);
}
-
void Assembler::Vdivqs(QRegister qd, QRegister qn, QRegister qm) {
ASSERT(qd != QTMP);
ASSERT(qn != QTMP);
@@ -2739,12 +2575,9 @@
vmulqs(qd, qn, qd);
}
-
-void Assembler::Branch(const StubEntry& stub_entry,
- Patchability patchable,
- Register pp,
- Condition cond) {
- const Code& target_code = Code::Handle(stub_entry.code());
+void Assembler::Branch(const StubEntry &stub_entry, Patchability patchable,
+ Register pp, Condition cond) {
+ const Code &target_code = Code::Handle(stub_entry.code());
const int32_t offset = ObjectPool::element_offset(
object_pool_wrapper_.FindObject(target_code, patchable));
LoadWordFromPoolOffset(CODE_REG, offset - kHeapObjectTag, pp, cond);
@@ -2752,8 +2585,7 @@
bx(IP, cond);
}
-
-void Assembler::BranchLink(const Code& target, Patchability patchable) {
+void Assembler::BranchLink(const Code &target, Patchability patchable) {
// Make sure that class CallPattern is able to patch the label referred
// to by this code sequence.
// For added code robustness, use 'blx lr' in a patchable sequence and
@@ -2762,43 +2594,37 @@
object_pool_wrapper_.FindObject(target, patchable));
LoadWordFromPoolOffset(CODE_REG, offset - kHeapObjectTag, PP, AL);
ldr(LR, FieldAddress(CODE_REG, Code::entry_point_offset()));
- blx(LR); // Use blx instruction so that the return branch prediction works.
+ blx(LR); // Use blx instruction so that the return branch prediction works.
}
-
-void Assembler::BranchLink(const StubEntry& stub_entry,
+void Assembler::BranchLink(const StubEntry &stub_entry,
Patchability patchable) {
- const Code& code = Code::Handle(stub_entry.code());
+ const Code &code = Code::Handle(stub_entry.code());
BranchLink(code, patchable);
}
-
-void Assembler::BranchLinkPatchable(const Code& target) {
+void Assembler::BranchLinkPatchable(const Code &target) {
BranchLink(target, kPatchable);
}
-
-void Assembler::BranchLink(const ExternalLabel* label) {
- LoadImmediate(LR, label->address()); // Target address is never patched.
- blx(LR); // Use blx instruction so that the return branch prediction works.
+void Assembler::BranchLink(const ExternalLabel *label) {
+ LoadImmediate(LR, label->address()); // Target address is never patched.
+ blx(LR); // Use blx instruction so that the return branch prediction works.
}
-
-void Assembler::BranchLinkPatchable(const StubEntry& stub_entry) {
+void Assembler::BranchLinkPatchable(const StubEntry &stub_entry) {
BranchLinkPatchable(Code::Handle(stub_entry.code()));
}
-
void Assembler::BranchLinkOffset(Register base, int32_t offset) {
ASSERT(base != PC);
ASSERT(base != IP);
LoadFromOffset(kWord, IP, base, offset);
- blx(IP); // Use blx instruction so that the return branch prediction works.
+ blx(IP); // Use blx instruction so that the return branch prediction works.
}
-
-void Assembler::LoadPatchableImmediate(
- Register rd, int32_t value, Condition cond) {
+void Assembler::LoadPatchableImmediate(Register rd, int32_t value,
+ Condition cond) {
const ARMVersion version = TargetCPUFeatures::arm_version();
if ((version == ARMv5TE) || (version == ARMv6)) {
// This sequence is patched in a few places, and should remain fixed.
@@ -2819,9 +2645,8 @@
}
}
-
-void Assembler::LoadDecodableImmediate(
- Register rd, int32_t value, Condition cond) {
+void Assembler::LoadDecodableImmediate(Register rd, int32_t value,
+ Condition cond) {
const ARMVersion version = TargetCPUFeatures::arm_version();
if ((version == ARMv5TE) || (version == ARMv6)) {
if (constant_pool_allowed()) {
@@ -2840,7 +2665,6 @@
}
}
-
void Assembler::LoadImmediate(Register rd, int32_t value, Condition cond) {
Operand o;
if (Operand::CanHold(value, &o)) {
@@ -2852,7 +2676,6 @@
}
}
-
void Assembler::LoadSImmediate(SRegister sd, float value, Condition cond) {
if (!vmovs(sd, value, cond)) {
const DRegister dd = static_cast<DRegister>(sd >> 1);
@@ -2862,10 +2685,7 @@
}
}
-
-void Assembler::LoadDImmediate(DRegister dd,
- double value,
- Register scratch,
+void Assembler::LoadDImmediate(DRegister dd, double value, Register scratch,
Condition cond) {
ASSERT(scratch != PC);
ASSERT(scratch != IP);
@@ -2879,12 +2699,8 @@
}
}
-
-void Assembler::LoadFromOffset(OperandSize size,
- Register reg,
- Register base,
- int32_t offset,
- Condition cond) {
+void Assembler::LoadFromOffset(OperandSize size, Register reg, Register base,
+ int32_t offset, Condition cond) {
int32_t offset_mask = 0;
if (!Address::CanHoldLoadOffset(size, offset, &offset_mask)) {
ASSERT(base != IP);
@@ -2893,35 +2709,31 @@
offset = offset & offset_mask;
}
switch (size) {
- case kByte:
- ldrsb(reg, Address(base, offset), cond);
- break;
- case kUnsignedByte:
- ldrb(reg, Address(base, offset), cond);
- break;
- case kHalfword:
- ldrsh(reg, Address(base, offset), cond);
- break;
- case kUnsignedHalfword:
- ldrh(reg, Address(base, offset), cond);
- break;
- case kWord:
- ldr(reg, Address(base, offset), cond);
- break;
- case kWordPair:
- ldrd(reg, base, offset, cond);
- break;
- default:
- UNREACHABLE();
+ case kByte:
+ ldrsb(reg, Address(base, offset), cond);
+ break;
+ case kUnsignedByte:
+ ldrb(reg, Address(base, offset), cond);
+ break;
+ case kHalfword:
+ ldrsh(reg, Address(base, offset), cond);
+ break;
+ case kUnsignedHalfword:
+ ldrh(reg, Address(base, offset), cond);
+ break;
+ case kWord:
+ ldr(reg, Address(base, offset), cond);
+ break;
+ case kWordPair:
+ ldrd(reg, base, offset, cond);
+ break;
+ default:
+ UNREACHABLE();
}
}
-
-void Assembler::StoreToOffset(OperandSize size,
- Register reg,
- Register base,
- int32_t offset,
- Condition cond) {
+void Assembler::StoreToOffset(OperandSize size, Register reg, Register base,
+ int32_t offset, Condition cond) {
int32_t offset_mask = 0;
if (!Address::CanHoldStoreOffset(size, offset, &offset_mask)) {
ASSERT(reg != IP);
@@ -2931,27 +2743,24 @@
offset = offset & offset_mask;
}
switch (size) {
- case kByte:
- strb(reg, Address(base, offset), cond);
- break;
- case kHalfword:
- strh(reg, Address(base, offset), cond);
- break;
- case kWord:
- str(reg, Address(base, offset), cond);
- break;
- case kWordPair:
- strd(reg, base, offset, cond);
- break;
- default:
- UNREACHABLE();
+ case kByte:
+ strb(reg, Address(base, offset), cond);
+ break;
+ case kHalfword:
+ strh(reg, Address(base, offset), cond);
+ break;
+ case kWord:
+ str(reg, Address(base, offset), cond);
+ break;
+ case kWordPair:
+ strd(reg, base, offset, cond);
+ break;
+ default:
+ UNREACHABLE();
}
}
-
-void Assembler::LoadSFromOffset(SRegister reg,
- Register base,
- int32_t offset,
+void Assembler::LoadSFromOffset(SRegister reg, Register base, int32_t offset,
Condition cond) {
int32_t offset_mask = 0;
if (!Address::CanHoldLoadOffset(kSWord, offset, &offset_mask)) {
@@ -2963,10 +2772,7 @@
vldrs(reg, Address(base, offset), cond);
}
-
-void Assembler::StoreSToOffset(SRegister reg,
- Register base,
- int32_t offset,
+void Assembler::StoreSToOffset(SRegister reg, Register base, int32_t offset,
Condition cond) {
int32_t offset_mask = 0;
if (!Address::CanHoldStoreOffset(kSWord, offset, &offset_mask)) {
@@ -2978,10 +2784,7 @@
vstrs(reg, Address(base, offset), cond);
}
-
-void Assembler::LoadDFromOffset(DRegister reg,
- Register base,
- int32_t offset,
+void Assembler::LoadDFromOffset(DRegister reg, Register base, int32_t offset,
Condition cond) {
int32_t offset_mask = 0;
if (!Address::CanHoldLoadOffset(kDWord, offset, &offset_mask)) {
@@ -2993,10 +2796,7 @@
vldrd(reg, Address(base, offset), cond);
}
-
-void Assembler::StoreDToOffset(DRegister reg,
- Register base,
- int32_t offset,
+void Assembler::StoreDToOffset(DRegister reg, Register base, int32_t offset,
Condition cond) {
int32_t offset_mask = 0;
if (!Address::CanHoldStoreOffset(kDWord, offset, &offset_mask)) {
@@ -3008,107 +2808,103 @@
vstrd(reg, Address(base, offset), cond);
}
-
-void Assembler::LoadMultipleDFromOffset(DRegister first,
- intptr_t count,
- Register base,
- int32_t offset) {
+void Assembler::LoadMultipleDFromOffset(DRegister first, intptr_t count,
+ Register base, int32_t offset) {
ASSERT(base != IP);
AddImmediate(IP, base, offset);
vldmd(IA, IP, first, count);
}
-void Assembler::StoreMultipleDToOffset(DRegister first,
- intptr_t count,
- Register base,
- int32_t offset) {
+void Assembler::StoreMultipleDToOffset(DRegister first, intptr_t count,
+ Register base, int32_t offset) {
ASSERT(base != IP);
AddImmediate(IP, base, offset);
vstmd(IA, IP, first, count);
}
-
-void Assembler::CopyDoubleField(
- Register dst, Register src, Register tmp1, Register tmp2, DRegister dtmp) {
+void Assembler::CopyDoubleField(Register dst, Register src, Register tmp1,
+ Register tmp2, DRegister dtmp) {
if (TargetCPUFeatures::vfp_supported()) {
LoadDFromOffset(dtmp, src, Double::value_offset() - kHeapObjectTag);
StoreDToOffset(dtmp, dst, Double::value_offset() - kHeapObjectTag);
} else {
- LoadFromOffset(kWord, tmp1, src,
- Double::value_offset() - kHeapObjectTag);
+ LoadFromOffset(kWord, tmp1, src, Double::value_offset() - kHeapObjectTag);
LoadFromOffset(kWord, tmp2, src,
- Double::value_offset() + kWordSize - kHeapObjectTag);
- StoreToOffset(kWord, tmp1, dst,
- Double::value_offset() - kHeapObjectTag);
+ Double::value_offset() + kWordSize - kHeapObjectTag);
+ StoreToOffset(kWord, tmp1, dst, Double::value_offset() - kHeapObjectTag);
StoreToOffset(kWord, tmp2, dst,
- Double::value_offset() + kWordSize - kHeapObjectTag);
+ Double::value_offset() + kWordSize - kHeapObjectTag);
}
}
-
-void Assembler::CopyFloat32x4Field(
- Register dst, Register src, Register tmp1, Register tmp2, DRegister dtmp) {
+void Assembler::CopyFloat32x4Field(Register dst, Register src, Register tmp1,
+ Register tmp2, DRegister dtmp) {
if (TargetCPUFeatures::neon_supported()) {
LoadMultipleDFromOffset(dtmp, 2, src,
- Float32x4::value_offset() - kHeapObjectTag);
+ Float32x4::value_offset() - kHeapObjectTag);
StoreMultipleDToOffset(dtmp, 2, dst,
- Float32x4::value_offset() - kHeapObjectTag);
+ Float32x4::value_offset() - kHeapObjectTag);
} else {
LoadFromOffset(kWord, tmp1, src,
- (Float32x4::value_offset() + 0 * kWordSize) - kHeapObjectTag);
+ (Float32x4::value_offset() + 0 * kWordSize) -
+ kHeapObjectTag);
LoadFromOffset(kWord, tmp2, src,
- (Float32x4::value_offset() + 1 * kWordSize) - kHeapObjectTag);
+ (Float32x4::value_offset() + 1 * kWordSize) -
+ kHeapObjectTag);
StoreToOffset(kWord, tmp1, dst,
- (Float32x4::value_offset() + 0 * kWordSize) - kHeapObjectTag);
+ (Float32x4::value_offset() + 0 * kWordSize) - kHeapObjectTag);
StoreToOffset(kWord, tmp2, dst,
- (Float32x4::value_offset() + 1 * kWordSize) - kHeapObjectTag);
+ (Float32x4::value_offset() + 1 * kWordSize) - kHeapObjectTag);
LoadFromOffset(kWord, tmp1, src,
- (Float32x4::value_offset() + 2 * kWordSize) - kHeapObjectTag);
+ (Float32x4::value_offset() + 2 * kWordSize) -
+ kHeapObjectTag);
LoadFromOffset(kWord, tmp2, src,
- (Float32x4::value_offset() + 3 * kWordSize) - kHeapObjectTag);
+ (Float32x4::value_offset() + 3 * kWordSize) -
+ kHeapObjectTag);
StoreToOffset(kWord, tmp1, dst,
- (Float32x4::value_offset() + 2 * kWordSize) - kHeapObjectTag);
+ (Float32x4::value_offset() + 2 * kWordSize) - kHeapObjectTag);
StoreToOffset(kWord, tmp2, dst,
- (Float32x4::value_offset() + 3 * kWordSize) - kHeapObjectTag);
+ (Float32x4::value_offset() + 3 * kWordSize) - kHeapObjectTag);
}
}
-
-void Assembler::CopyFloat64x2Field(
- Register dst, Register src, Register tmp1, Register tmp2, DRegister dtmp) {
+void Assembler::CopyFloat64x2Field(Register dst, Register src, Register tmp1,
+ Register tmp2, DRegister dtmp) {
if (TargetCPUFeatures::neon_supported()) {
LoadMultipleDFromOffset(dtmp, 2, src,
- Float64x2::value_offset() - kHeapObjectTag);
+ Float64x2::value_offset() - kHeapObjectTag);
StoreMultipleDToOffset(dtmp, 2, dst,
- Float64x2::value_offset() - kHeapObjectTag);
+ Float64x2::value_offset() - kHeapObjectTag);
} else {
LoadFromOffset(kWord, tmp1, src,
- (Float64x2::value_offset() + 0 * kWordSize) - kHeapObjectTag);
+ (Float64x2::value_offset() + 0 * kWordSize) -
+ kHeapObjectTag);
LoadFromOffset(kWord, tmp2, src,
- (Float64x2::value_offset() + 1 * kWordSize) - kHeapObjectTag);
+ (Float64x2::value_offset() + 1 * kWordSize) -
+ kHeapObjectTag);
StoreToOffset(kWord, tmp1, dst,
- (Float64x2::value_offset() + 0 * kWordSize) - kHeapObjectTag);
+ (Float64x2::value_offset() + 0 * kWordSize) - kHeapObjectTag);
StoreToOffset(kWord, tmp2, dst,
- (Float64x2::value_offset() + 1 * kWordSize) - kHeapObjectTag);
+ (Float64x2::value_offset() + 1 * kWordSize) - kHeapObjectTag);
LoadFromOffset(kWord, tmp1, src,
- (Float64x2::value_offset() + 2 * kWordSize) - kHeapObjectTag);
+ (Float64x2::value_offset() + 2 * kWordSize) -
+ kHeapObjectTag);
LoadFromOffset(kWord, tmp2, src,
- (Float64x2::value_offset() + 3 * kWordSize) - kHeapObjectTag);
+ (Float64x2::value_offset() + 3 * kWordSize) -
+ kHeapObjectTag);
StoreToOffset(kWord, tmp1, dst,
- (Float64x2::value_offset() + 2 * kWordSize) - kHeapObjectTag);
+ (Float64x2::value_offset() + 2 * kWordSize) - kHeapObjectTag);
StoreToOffset(kWord, tmp2, dst,
- (Float64x2::value_offset() + 3 * kWordSize) - kHeapObjectTag);
+ (Float64x2::value_offset() + 3 * kWordSize) - kHeapObjectTag);
}
}
-
void Assembler::AddImmediate(Register rd, int32_t value, Condition cond) {
AddImmediate(rd, rd, value, cond);
}
-
void Assembler::AddImmediate(Register rd, Register rn, int32_t value,
Condition cond) {
if (value == 0) {
@@ -3140,7 +2936,6 @@
}
}
-
void Assembler::AddImmediateSetFlags(Register rd, Register rn, int32_t value,
Condition cond) {
Operand o;
@@ -3148,7 +2943,7 @@
// Handles value == kMinInt32.
adds(rd, rn, o, cond);
} else if (Operand::CanHold(-value, &o)) {
- ASSERT(value != kMinInt32); // Would cause erroneous overflow detection.
+ ASSERT(value != kMinInt32); // Would cause erroneous overflow detection.
subs(rd, rn, o, cond);
} else {
ASSERT(rn != IP);
@@ -3156,7 +2951,7 @@
mvn(IP, o, cond);
adds(rd, rn, Operand(IP), cond);
} else if (Operand::CanHold(~(-value), &o)) {
- ASSERT(value != kMinInt32); // Would cause erroneous overflow detection.
+ ASSERT(value != kMinInt32); // Would cause erroneous overflow detection.
mvn(IP, o, cond);
subs(rd, rn, Operand(IP), cond);
} else {
@@ -3166,15 +2961,14 @@
}
}
-
void Assembler::SubImmediateSetFlags(Register rd, Register rn, int32_t value,
- Condition cond) {
+ Condition cond) {
Operand o;
if (Operand::CanHold(value, &o)) {
// Handles value == kMinInt32.
subs(rd, rn, o, cond);
} else if (Operand::CanHold(-value, &o)) {
- ASSERT(value != kMinInt32); // Would cause erroneous overflow detection.
+ ASSERT(value != kMinInt32); // Would cause erroneous overflow detection.
adds(rd, rn, o, cond);
} else {
ASSERT(rn != IP);
@@ -3182,7 +2976,7 @@
mvn(IP, o, cond);
subs(rd, rn, Operand(IP), cond);
} else if (Operand::CanHold(~(-value), &o)) {
- ASSERT(value != kMinInt32); // Would cause erroneous overflow detection.
+ ASSERT(value != kMinInt32); // Would cause erroneous overflow detection.
mvn(IP, o, cond);
adds(rd, rn, Operand(IP), cond);
} else {
@@ -3192,7 +2986,6 @@
}
}
-
void Assembler::AndImmediate(Register rd, Register rs, int32_t imm,
Condition cond) {
Operand o;
@@ -3204,7 +2997,6 @@
}
}
-
void Assembler::CompareImmediate(Register rn, int32_t value, Condition cond) {
Operand o;
if (Operand::CanHold(value, &o)) {
@@ -3216,7 +3008,6 @@
}
}
-
void Assembler::TestImmediate(Register rn, int32_t imm, Condition cond) {
Operand o;
if (Operand::CanHold(imm, &o)) {
@@ -3237,16 +3028,15 @@
SRegister stmpl = static_cast<SRegister>(2 * tmpl);
SRegister stmpr = static_cast<SRegister>(2 * tmpr);
vmovsr(stmpl, left);
- vcvtdi(tmpl, stmpl); // left is in tmpl.
+ vcvtdi(tmpl, stmpl); // left is in tmpl.
vmovsr(stmpr, right);
- vcvtdi(tmpr, stmpr); // right is in tmpr.
+ vcvtdi(tmpr, stmpr); // right is in tmpr.
vdivd(tmpr, tmpl, tmpr);
vcvtid(stmpr, tmpr);
vmovrs(result, stmpr);
}
}
-
static int NumRegsBelowFP(RegList regs) {
int count = 0;
for (int i = 0; i < FP; i++) {
@@ -3257,7 +3047,6 @@
return count;
}
-
void Assembler::EnterFrame(RegList regs, intptr_t frame_size) {
if (prologue_offset_ == -1) {
prologue_offset_ = CodeSize();
@@ -3270,9 +3059,8 @@
AddImmediate(SP, -frame_size);
}
-
void Assembler::LeaveFrame(RegList regs) {
- ASSERT((regs & (1 << PC)) == 0); // Must not pop PC.
+ ASSERT((regs & (1 << PC)) == 0); // Must not pop PC.
if ((regs & (1 << FP)) != 0) {
// Use FP to set SP.
sub(SP, FP, Operand(4 * NumRegsBelowFP(regs)));
@@ -3280,11 +3068,7 @@
PopList(regs);
}
-
-void Assembler::Ret() {
- bx(LR);
-}
-
+void Assembler::Ret() { bx(LR); }
void Assembler::ReserveAlignedFrameSpace(intptr_t frame_space) {
// Reserve space for arguments and align frame before entering
@@ -3295,7 +3079,6 @@
}
}
-
void Assembler::EnterCallRuntimeFrame(intptr_t frame_space) {
// Preserve volatile CPU registers and PP.
EnterFrame(kDartVolatileCpuRegs | (1 << PP) | (1 << FP), 0);
@@ -3319,14 +3102,14 @@
ReserveAlignedFrameSpace(frame_space);
}
-
void Assembler::LeaveCallRuntimeFrame() {
// SP might have been modified to reserve space for arguments
// and ensure proper alignment of the stack frame.
// We need to restore it before restoring registers.
const intptr_t kPushedFpuRegisterSize =
- TargetCPUFeatures::vfp_supported() ?
- kDartVolatileFpuRegCount * kFpuRegisterSize : 0;
+ TargetCPUFeatures::vfp_supported()
+ ? kDartVolatileFpuRegCount * kFpuRegisterSize
+ : 0;
COMPILE_ASSERT(PP < FP);
COMPILE_ASSERT((kDartVolatileCpuRegs & (1 << PP)) == 0);
@@ -3353,13 +3136,11 @@
LeaveFrame(kDartVolatileCpuRegs | (1 << PP) | (1 << FP));
}
-
-void Assembler::CallRuntime(const RuntimeEntry& entry,
+void Assembler::CallRuntime(const RuntimeEntry &entry,
intptr_t argument_count) {
entry.Call(this, argument_count);
}
-
void Assembler::EnterDartFrame(intptr_t frame_size) {
ASSERT(!constant_pool_allowed());
@@ -3373,7 +3154,6 @@
AddImmediate(SP, -frame_size);
}
-
// On entry to a function compiled for OSR, the caller's frame pointer, the
// stack locals, and any copied parameters are already in place. The frame
// pointer is already set up. The PC marker is not correct for the
@@ -3388,29 +3168,20 @@
AddImmediate(SP, -extra_size);
}
-
void Assembler::LeaveDartFrame(RestorePP restore_pp) {
if (restore_pp == kRestoreCallerPP) {
ldr(PP, Address(FP, kSavedCallerPpSlotFromFp * kWordSize));
set_constant_pool_allowed(false);
}
- Drop(2); // Drop saved PP, PC marker.
+ Drop(2); // Drop saved PP, PC marker.
LeaveFrame((1 << FP) | (1 << LR));
}
+void Assembler::EnterStubFrame() { EnterDartFrame(0); }
-void Assembler::EnterStubFrame() {
- EnterDartFrame(0);
-}
+void Assembler::LeaveStubFrame() { LeaveDartFrame(); }
-
-void Assembler::LeaveStubFrame() {
- LeaveDartFrame();
-}
-
-
-void Assembler::LoadAllocationStatsAddress(Register dest,
- intptr_t cid,
+void Assembler::LoadAllocationStatsAddress(Register dest, intptr_t cid,
bool inline_isolate) {
ASSERT(dest != kNoRegister);
ASSERT(dest != TMP);
@@ -3418,8 +3189,8 @@
const intptr_t class_offset = ClassTable::ClassOffsetFor(cid);
if (inline_isolate) {
ASSERT(FLAG_allow_absolute_addresses);
- ClassTable* class_table = Isolate::Current()->class_table();
- ClassHeapStats** table_ptr = class_table->TableAddressFor(cid);
+ ClassTable *class_table = Isolate::Current()->class_table();
+ ClassHeapStats **table_ptr = class_table->TableAddressFor(cid);
if (cid < kNumPredefinedCids) {
LoadImmediate(dest, reinterpret_cast<uword>(*table_ptr) + class_offset);
} else {
@@ -3436,11 +3207,8 @@
}
}
-
-void Assembler::MaybeTraceAllocation(intptr_t cid,
- Register temp_reg,
- Label* trace,
- bool inline_isolate) {
+void Assembler::MaybeTraceAllocation(intptr_t cid, Register temp_reg,
+ Label *trace, bool inline_isolate) {
LoadAllocationStatsAddress(temp_reg, cid, inline_isolate);
const uword state_offset = ClassHeapStats::state_offset();
ldr(temp_reg, Address(temp_reg, state_offset));
@@ -3448,36 +3216,36 @@
b(trace, NE);
}
-
-void Assembler::IncrementAllocationStats(Register stats_addr_reg,
- intptr_t cid,
+void Assembler::IncrementAllocationStats(Register stats_addr_reg, intptr_t cid,
Heap::Space space) {
ASSERT(stats_addr_reg != kNoRegister);
ASSERT(stats_addr_reg != TMP);
ASSERT(cid > 0);
- const uword count_field_offset = (space == Heap::kNew) ?
- ClassHeapStats::allocated_since_gc_new_space_offset() :
- ClassHeapStats::allocated_since_gc_old_space_offset();
- const Address& count_address = Address(stats_addr_reg, count_field_offset);
+ const uword count_field_offset =
+ (space == Heap::kNew)
+ ? ClassHeapStats::allocated_since_gc_new_space_offset()
+ : ClassHeapStats::allocated_since_gc_old_space_offset();
+ const Address &count_address = Address(stats_addr_reg, count_field_offset);
ldr(TMP, count_address);
AddImmediate(TMP, 1);
str(TMP, count_address);
}
-
void Assembler::IncrementAllocationStatsWithSize(Register stats_addr_reg,
Register size_reg,
Heap::Space space) {
ASSERT(stats_addr_reg != kNoRegister);
ASSERT(stats_addr_reg != TMP);
- const uword count_field_offset = (space == Heap::kNew) ?
- ClassHeapStats::allocated_since_gc_new_space_offset() :
- ClassHeapStats::allocated_since_gc_old_space_offset();
- const uword size_field_offset = (space == Heap::kNew) ?
- ClassHeapStats::allocated_size_since_gc_new_space_offset() :
- ClassHeapStats::allocated_size_since_gc_old_space_offset();
- const Address& count_address = Address(stats_addr_reg, count_field_offset);
- const Address& size_address = Address(stats_addr_reg, size_field_offset);
+ const uword count_field_offset =
+ (space == Heap::kNew)
+ ? ClassHeapStats::allocated_since_gc_new_space_offset()
+ : ClassHeapStats::allocated_since_gc_old_space_offset();
+ const uword size_field_offset =
+ (space == Heap::kNew)
+ ? ClassHeapStats::allocated_size_since_gc_new_space_offset()
+ : ClassHeapStats::allocated_size_since_gc_old_space_offset();
+ const Address &count_address = Address(stats_addr_reg, count_field_offset);
+ const Address &size_address = Address(stats_addr_reg, size_field_offset);
ldr(TMP, count_address);
AddImmediate(TMP, 1);
str(TMP, count_address);
@@ -3486,11 +3254,8 @@
str(TMP, size_address);
}
-
-void Assembler::TryAllocate(const Class& cls,
- Label* failure,
- Register instance_reg,
- Register temp_reg) {
+void Assembler::TryAllocate(const Class &cls, Label *failure,
+ Register instance_reg, Register temp_reg) {
ASSERT(failure != NULL);
if (FLAG_inline_alloc) {
ASSERT(instance_reg != temp_reg);
@@ -3537,13 +3302,9 @@
}
}
-
-void Assembler::TryAllocateArray(intptr_t cid,
- intptr_t instance_size,
- Label* failure,
- Register instance,
- Register end_address,
- Register temp1,
+void Assembler::TryAllocateArray(intptr_t cid, intptr_t instance_size,
+ Label *failure, Register instance,
+ Register end_address, Register temp1,
Register temp2) {
if (FLAG_inline_alloc) {
// If this allocation is traced, program will jump to failure path
@@ -3555,7 +3316,7 @@
// Potential new object start.
ldr(instance, Address(temp1, Heap::TopOffset(space)));
AddImmediateSetFlags(end_address, instance, instance_size);
- b(failure, CS); // Branch if unsigned overflow.
+ b(failure, CS); // Branch if unsigned overflow.
// Check if the allocation fits into the remaining space.
// instance: potential new object start.
@@ -3577,7 +3338,7 @@
tags = RawObject::ClassIdTag::update(cid, tags);
tags = RawObject::SizeTag::update(instance_size, tags);
LoadImmediate(temp1, tags);
- str(temp1, FieldAddress(instance, Array::tags_offset())); // Store tags.
+ str(temp1, FieldAddress(instance, Array::tags_offset())); // Store tags.
LoadImmediate(temp1, instance_size);
IncrementAllocationStatsWithSize(temp2, temp1, space);
@@ -3586,14 +3347,13 @@
}
}
-
-void Assembler::Stop(const char* message) {
+void Assembler::Stop(const char *message) {
if (FLAG_print_stop_message) {
- PushList((1 << R0) | (1 << IP) | (1 << LR)); // Preserve R0, IP, LR.
+ PushList((1 << R0) | (1 << IP) | (1 << LR)); // Preserve R0, IP, LR.
LoadImmediate(R0, reinterpret_cast<int32_t>(message));
// PrintStopMessage() preserves all registers.
BranchLink(&StubCode::PrintStopMessage_entry()->label());
- PopList((1 << R0) | (1 << IP) | (1 << LR)); // Restore R0, IP, LR.
+ PopList((1 << R0) | (1 << IP) | (1 << LR)); // Restore R0, IP, LR.
}
// Emit the message address before the svc instruction, so that we can
// 'unstop' and continue execution in the simulator or jump to the next
@@ -3605,18 +3365,14 @@
bkpt(Instr::kStopMessageCode);
}
-
-Address Assembler::ElementAddressForIntIndex(bool is_load,
- bool is_external,
- intptr_t cid,
- intptr_t index_scale,
- Register array,
- intptr_t index,
+Address Assembler::ElementAddressForIntIndex(bool is_load, bool is_external,
+ intptr_t cid, intptr_t index_scale,
+ Register array, intptr_t index,
Register temp) {
const int64_t offset_base =
(is_external ? 0 : (Instance::DataOffsetFor(cid) - kHeapObjectTag));
- const int64_t offset = offset_base +
- static_cast<int64_t>(index) * index_scale;
+ const int64_t offset =
+ offset_base + static_cast<int64_t>(index) * index_scale;
ASSERT(Utils::IsInt(32, offset));
if (Address::CanHoldImmediateOffset(is_load, cid, offset)) {
@@ -3628,13 +3384,9 @@
}
}
-
-Address Assembler::ElementAddressForRegIndex(bool is_load,
- bool is_external,
- intptr_t cid,
- intptr_t index_scale,
- Register array,
- Register index) {
+Address Assembler::ElementAddressForRegIndex(bool is_load, bool is_external,
+ intptr_t cid, intptr_t index_scale,
+ Register array, Register index) {
// Note that index is expected smi-tagged, (i.e, LSL 1) for all arrays.
const intptr_t shift = Utils::ShiftForPowerOfTwo(index_scale) - kSmiTagShift;
int32_t offset =
@@ -3643,8 +3395,8 @@
ASSERT(array != IP);
ASSERT(index != IP);
const Register base = is_load ? IP : index;
- if ((offset != 0) ||
- (size == kSWord) || (size == kDWord) || (size == kRegList)) {
+ if ((offset != 0) || (size == kSWord) || (size == kDWord) ||
+ (size == kRegList)) {
if (shift < 0) {
ASSERT(shift == -1);
add(base, array, Operand(index, ASR, 1));
@@ -3660,44 +3412,36 @@
}
}
int32_t offset_mask = 0;
- if ((is_load && !Address::CanHoldLoadOffset(size,
- offset,
- &offset_mask)) ||
- (!is_load && !Address::CanHoldStoreOffset(size,
- offset,
- &offset_mask))) {
+ if ((is_load && !Address::CanHoldLoadOffset(size, offset, &offset_mask)) ||
+ (!is_load && !Address::CanHoldStoreOffset(size, offset, &offset_mask))) {
AddImmediate(base, offset & ~offset_mask);
offset = offset & offset_mask;
}
return Address(base, offset);
}
-
-static const char* cpu_reg_names[kNumberOfCpuRegisters] = {
- "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
- "r8", "ctx", "pp", "fp", "ip", "sp", "lr", "pc",
+static const char *cpu_reg_names[kNumberOfCpuRegisters] = {
+ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
+ "r8", "ctx", "pp", "fp", "ip", "sp", "lr", "pc",
};
-
-const char* Assembler::RegisterName(Register reg) {
+const char *Assembler::RegisterName(Register reg) {
ASSERT((0 <= reg) && (reg < kNumberOfCpuRegisters));
return cpu_reg_names[reg];
}
-
-static const char* fpu_reg_names[kNumberOfFpuRegisters] = {
- "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
+static const char *fpu_reg_names[kNumberOfFpuRegisters] = {
+ "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
#if defined(VFPv3_D32)
- "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15",
+ "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15",
#endif
};
-
-const char* Assembler::FpuRegisterName(FpuRegister reg) {
+const char *Assembler::FpuRegisterName(FpuRegister reg) {
ASSERT((0 <= reg) && (reg < kNumberOfFpuRegisters));
return fpu_reg_names[reg];
}
-} // namespace dart
+} // namespace dart
-#endif // defined TARGET_ARCH_ARM
+#endif // defined TARGET_ARCH_ARM
diff --git a/third_party/subzero/src/DartARM32/assembler_arm.h b/third_party/subzero/src/DartARM32/assembler_arm.h
index 93de45f..daa6ea0 100644
--- a/third_party/subzero/src/DartARM32/assembler_arm.h
+++ b/third_party/subzero/src/DartARM32/assembler_arm.h
@@ -72,8 +72,8 @@
#endif
class Label : public ValueObject {
- public:
- Label() : position_(0) { }
+public:
+ Label() : position_(0) {}
~Label() {
// Assert if label is being destroyed with unresolved branches pending.
@@ -91,12 +91,10 @@
bool IsUnused() const { return position_ == 0; }
bool IsLinked() const { return position_ > 0; }
- private:
+private:
intptr_t position_;
- void Reinitialize() {
- position_ = 0;
- }
+ void Reinitialize() { position_ = 0; }
void BindTo(intptr_t position) {
ASSERT(!IsBound());
@@ -114,19 +112,18 @@
DISALLOW_COPY_AND_ASSIGN(Label);
};
-
// Encodes Addressing Mode 1 - Data-processing operands.
class Operand : public ValueObject {
- public:
+public:
// Data-processing operands - Uninitialized.
- Operand() : type_(-1), encoding_(-1) { }
+ Operand() : type_(-1), encoding_(-1) {}
// Data-processing operands - Copy constructor.
- Operand(const Operand& other)
- : ValueObject(), type_(other.type_), encoding_(other.encoding_) { }
+ Operand(const Operand &other)
+ : ValueObject(), type_(other.type_), encoding_(other.encoding_) {}
// Data-processing operands - Assignment operator.
- Operand& operator=(const Operand& other) {
+ Operand &operator=(const Operand &other) {
type_ = other.type_;
encoding_ = other.encoding_;
return *this;
@@ -196,7 +193,7 @@
}
#endif
- private:
+private:
bool is_valid() const { return (type_ == 0) || (type_ == 1); }
uint32_t type() const {
@@ -209,14 +206,13 @@
return encoding_;
}
- uint32_t type_; // Encodes the type field (bits 27-25) in the instruction.
+ uint32_t type_; // Encodes the type field (bits 27-25) in the instruction.
uint32_t encoding_;
friend class Assembler;
friend class Address;
};
-
enum OperandSize {
kByte,
kUnsignedByte,
@@ -230,9 +226,9 @@
kRegList,
};
-
// Load/store multiple addressing mode.
enum BlockAddressMode {
+ // clang-format off
// bit encoding P U W
DA = (0|0|0) << 21, // decrement after
IA = (0|4|0) << 21, // increment after
@@ -242,11 +238,11 @@
IA_W = (0|4|1) << 21, // increment after with writeback to base
DB_W = (8|0|1) << 21, // decrement before with writeback to base
IB_W = (8|4|1) << 21 // increment before with writeback to base
+ // clang-format on
};
-
class Address : public ValueObject {
- public:
+public:
enum OffsetKind {
Immediate,
IndexRegister,
@@ -255,6 +251,7 @@
// Memory operand addressing mode
enum Mode {
+ // clang-format off
kModeMask = (8|4|1) << 21,
// bit encoding P U W
Offset = (8|4|0) << 21, // offset (w/o writeback to base)
@@ -263,19 +260,19 @@
NegOffset = (8|0|0) << 21, // negative offset (w/o writeback to base)
NegPreIndex = (8|0|1) << 21, // negative pre-indexed with writeback
NegPostIndex = (0|0|0) << 21 // negative post-indexed with writeback
+ // clang-format on
};
- Address(const Address& other)
- : ValueObject(), encoding_(other.encoding_), kind_(other.kind_) {
- }
+ Address(const Address &other)
+ : ValueObject(), encoding_(other.encoding_), kind_(other.kind_) {}
- Address& operator=(const Address& other) {
+ Address &operator=(const Address &other) {
encoding_ = other.encoding_;
kind_ = other.kind_;
return *this;
}
- bool Equals(const Address& other) const {
+ bool Equals(const Address &other) const {
return (encoding_ == other.encoding_) && (kind_ == other.kind_);
}
@@ -298,8 +295,8 @@
// shifted register case below should be used.
Address(Register rn, Register r, Mode am);
- Address(Register rn, Register rm,
- Shift shift = LSL, uint32_t shift_imm = 0, Mode am = Offset) {
+ Address(Register rn, Register rm, Shift shift = LSL, uint32_t shift_imm = 0,
+ Mode am = Offset) {
Operand o(rm, shift, shift_imm);
if ((shift == LSL) && (shift_imm == 0)) {
@@ -315,25 +312,22 @@
static OperandSize OperandSizeFor(intptr_t cid);
- static bool CanHoldLoadOffset(OperandSize size,
- int32_t offset,
- int32_t* offset_mask);
- static bool CanHoldStoreOffset(OperandSize size,
- int32_t offset,
- int32_t* offset_mask);
- static bool CanHoldImmediateOffset(bool is_load,
- intptr_t cid,
+ static bool CanHoldLoadOffset(OperandSize size, int32_t offset,
+ int32_t *offset_mask);
+ static bool CanHoldStoreOffset(OperandSize size, int32_t offset,
+ int32_t *offset_mask);
+ static bool CanHoldImmediateOffset(bool is_load, intptr_t cid,
int64_t offset);
- private:
+private:
Register rn() const {
return Instr::At(reinterpret_cast<uword>(&encoding_))->RnField();
}
Register rm() const {
- return ((kind() == IndexRegister) || (kind() == ScaledIndexRegister)) ?
- Instr::At(reinterpret_cast<uword>(&encoding_))->RmField() :
- kNoRegister;
+ return ((kind() == IndexRegister) || (kind() == ScaledIndexRegister))
+ ? Instr::At(reinterpret_cast<uword>(&encoding_))->RmField()
+ : kNoRegister;
}
Mode mode() const { return static_cast<Mode>(encoding() & kModeMask); }
@@ -358,39 +352,34 @@
friend class Assembler;
};
-
class FieldAddress : public Address {
- public:
+public:
FieldAddress(Register base, int32_t disp)
- : Address(base, disp - kHeapObjectTag) { }
+ : Address(base, disp - kHeapObjectTag) {}
// This addressing mode does not exist.
FieldAddress(Register base, Register r);
- FieldAddress(const FieldAddress& other) : Address(other) { }
+ FieldAddress(const FieldAddress &other) : Address(other) {}
- FieldAddress& operator=(const FieldAddress& other) {
+ FieldAddress &operator=(const FieldAddress &other) {
Address::operator=(other);
return *this;
}
};
-
class Assembler : public ValueObject {
- public:
+public:
explicit Assembler(bool use_far_branches = false)
- : buffer_(),
- prologue_offset_(-1),
- use_far_branches_(use_far_branches),
- comments_(),
- constant_pool_allowed_(false) { }
+ : buffer_(), prologue_offset_(-1), use_far_branches_(use_far_branches),
+ comments_(), constant_pool_allowed_(false) {}
- ~Assembler() { }
+ ~Assembler() {}
void PopRegister(Register r) { Pop(r); }
- void Bind(Label* label);
- void Jump(Label* label) { b(label); }
+ void Bind(Label *label);
+ void Jump(Label *label) { b(label); }
// Misc. functionality
intptr_t CodeSize() const { return buffer_.Size(); }
@@ -400,14 +389,14 @@
// the fixups. On ARM there are no pointers in code.
intptr_t CountPointerOffsets() const { return 0; }
- const ZoneGrowableArray<intptr_t>& GetPointerOffsets() const {
- ASSERT(buffer_.pointer_offsets().length() == 0); // No pointers in code.
+ const ZoneGrowableArray<intptr_t> &GetPointerOffsets() const {
+ ASSERT(buffer_.pointer_offsets().length() == 0); // No pointers in code.
return buffer_.pointer_offsets();
}
- ObjectPoolWrapper& object_pool_wrapper() { return object_pool_wrapper_; }
+ ObjectPoolWrapper &object_pool_wrapper() { return object_pool_wrapper_; }
- RawObjectPool* MakeObjectPool() {
+ RawObjectPool *MakeObjectPool() {
return object_pool_wrapper_.MakeObjectPool();
}
@@ -418,31 +407,29 @@
#if defined(TESTING) || defined(DEBUG)
// Used in unit tests and to ensure predictable verification code size in
// FlowGraphCompiler::EmitEdgeCounter.
- void set_use_far_branches(bool b) {
- use_far_branches_ = b;
- }
-#endif // TESTING || DEBUG
+ void set_use_far_branches(bool b) { use_far_branches_ = b; }
+#endif // TESTING || DEBUG
- void FinalizeInstructions(const MemoryRegion& region) {
+ void FinalizeInstructions(const MemoryRegion ®ion) {
buffer_.FinalizeInstructions(region);
}
// Debugging and bringup support.
- void Stop(const char* message);
- void Unimplemented(const char* message);
- void Untested(const char* message);
- void Unreachable(const char* message);
+ void Stop(const char *message);
+ void Unimplemented(const char *message);
+ void Untested(const char *message);
+ void Unreachable(const char *message);
static void InitializeMemoryWithBreakpoints(uword data, intptr_t length);
- void Comment(const char* format, ...) PRINTF_ATTRIBUTE(2, 3);
+ void Comment(const char *format, ...) PRINTF_ATTRIBUTE(2, 3);
static bool EmittingComments();
- const Code::Comments& GetCodeComments() const;
+ const Code::Comments &GetCodeComments() const;
- static const char* RegisterName(Register reg);
+ static const char *RegisterName(Register reg);
- static const char* FpuRegisterName(FpuRegister reg);
+ static const char *FpuRegisterName(FpuRegister reg);
#if 0
// Moved to ARM32::AssemblerARM32::and_()
@@ -658,15 +645,15 @@
void vstrd(DRegister dd, Address ad, Condition cond = AL);
#endif
- void vldms(BlockAddressMode am, Register base,
- SRegister first, SRegister last, Condition cond = AL);
- void vstms(BlockAddressMode am, Register base,
- SRegister first, SRegister last, Condition cond = AL);
+ void vldms(BlockAddressMode am, Register base, SRegister first,
+ SRegister last, Condition cond = AL);
+ void vstms(BlockAddressMode am, Register base, SRegister first,
+ SRegister last, Condition cond = AL);
- void vldmd(BlockAddressMode am, Register base,
- DRegister first, intptr_t count, Condition cond = AL);
- void vstmd(BlockAddressMode am, Register base,
- DRegister first, intptr_t count, Condition cond = AL);
+ void vldmd(BlockAddressMode am, Register base, DRegister first,
+ intptr_t count, Condition cond = AL);
+ void vstmd(BlockAddressMode am, Register base, DRegister first,
+ intptr_t count, Condition cond = AL);
#if 0
// Moved to Arm32::AssemblerARM32::vadds()
@@ -823,18 +810,17 @@
void blx(Register rm, Condition cond = AL);
#endif
- void Branch(const StubEntry& stub_entry,
- Patchability patchable = kNotPatchable,
- Register pp = PP,
+ void Branch(const StubEntry &stub_entry,
+ Patchability patchable = kNotPatchable, Register pp = PP,
Condition cond = AL);
- void BranchLink(const StubEntry& stub_entry,
+ void BranchLink(const StubEntry &stub_entry,
Patchability patchable = kNotPatchable);
- void BranchLink(const Code& code, Patchability patchable);
+ void BranchLink(const Code &code, Patchability patchable);
// Branch and link to an entry address. Call sequence can be patched.
- void BranchLinkPatchable(const StubEntry& stub_entry);
- void BranchLinkPatchable(const Code& code);
+ void BranchLinkPatchable(const StubEntry &stub_entry);
+ void BranchLinkPatchable(const Code &code);
// Branch and link to [base + offset]. Call sequence is never patched.
void BranchLinkOffset(Register base, int32_t offset);
@@ -855,7 +841,6 @@
// Compare rn with signed immediate value. May clobber IP.
void CompareImmediate(Register rn, int32_t value, Condition cond = AL);
-
// Signed integer division of left by right. Checks to see if integer
// division is supported. If not, uses the FPU for division with
// temporary registers tmpl and tmpr. tmpl and tmpr must be different
@@ -870,10 +855,10 @@
void LoadImmediate(Register rd, int32_t value, Condition cond = AL);
// These two may clobber IP.
void LoadSImmediate(SRegister sd, float value, Condition cond = AL);
- void LoadDImmediate(DRegister dd, double value,
- Register scratch, Condition cond = AL);
+ void LoadDImmediate(DRegister dd, double value, Register scratch,
+ Condition cond = AL);
- void MarkExceptionHandler(Label* label);
+ void MarkExceptionHandler(Label *label);
void Drop(intptr_t stack_elements);
@@ -882,79 +867,65 @@
void LoadIsolate(Register rd);
- void LoadObject(Register rd, const Object& object, Condition cond = AL);
- void LoadUniqueObject(Register rd, const Object& object, Condition cond = AL);
- void LoadFunctionFromCalleePool(Register dst,
- const Function& function,
+ void LoadObject(Register rd, const Object &object, Condition cond = AL);
+ void LoadUniqueObject(Register rd, const Object &object, Condition cond = AL);
+ void LoadFunctionFromCalleePool(Register dst, const Function &function,
Register new_pp);
- void LoadNativeEntry(Register dst,
- const ExternalLabel* label,
- Patchability patchable,
- Condition cond = AL);
- void PushObject(const Object& object);
- void CompareObject(Register rn, const Object& object);
+ void LoadNativeEntry(Register dst, const ExternalLabel *label,
+ Patchability patchable, Condition cond = AL);
+ void PushObject(const Object &object);
+ void CompareObject(Register rn, const Object &object);
// When storing into a heap object field, knowledge of the previous content
// is expressed through these constants.
enum FieldContent {
- kEmptyOrSmiOrNull, // Empty = garbage/zapped in release/debug mode.
+ kEmptyOrSmiOrNull, // Empty = garbage/zapped in release/debug mode.
kHeapObjectOrSmi,
kOnlySmi,
};
- void StoreIntoObject(Register object, // Object we are storing into.
- const Address& dest, // Where we are storing into.
- Register value, // Value we are storing.
+ void StoreIntoObject(Register object, // Object we are storing into.
+ const Address &dest, // Where we are storing into.
+ Register value, // Value we are storing.
bool can_value_be_smi = true);
- void StoreIntoObjectOffset(Register object,
- int32_t offset,
- Register value,
+ void StoreIntoObjectOffset(Register object, int32_t offset, Register value,
bool can_value_be_smi = true);
- void StoreIntoObjectNoBarrier(Register object,
- const Address& dest,
+ void StoreIntoObjectNoBarrier(Register object, const Address &dest,
Register value,
FieldContent old_content = kHeapObjectOrSmi);
- void InitializeFieldNoBarrier(Register object,
- const Address& dest,
+ void InitializeFieldNoBarrier(Register object, const Address &dest,
Register value) {
StoreIntoObjectNoBarrier(object, dest, value, kEmptyOrSmiOrNull);
}
- void StoreIntoObjectNoBarrierOffset(
- Register object,
- int32_t offset,
- Register value,
- FieldContent old_content = kHeapObjectOrSmi);
- void StoreIntoObjectNoBarrier(Register object,
- const Address& dest,
- const Object& value,
+ void
+ StoreIntoObjectNoBarrierOffset(Register object, int32_t offset,
+ Register value,
+ FieldContent old_content = kHeapObjectOrSmi);
+ void StoreIntoObjectNoBarrier(Register object, const Address &dest,
+ const Object &value,
FieldContent old_content = kHeapObjectOrSmi);
- void StoreIntoObjectNoBarrierOffset(
- Register object,
- int32_t offset,
- const Object& value,
- FieldContent old_content = kHeapObjectOrSmi);
+ void
+ StoreIntoObjectNoBarrierOffset(Register object, int32_t offset,
+ const Object &value,
+ FieldContent old_content = kHeapObjectOrSmi);
// Store value_even, value_odd, value_even, ... into the words in the address
// range [begin, end), assumed to be uninitialized fields in object (tagged).
// The stores must not need a generational store barrier (e.g., smi/null),
// and (value_even, value_odd) must be a valid register pair.
// Destroys register 'begin'.
- void InitializeFieldsNoBarrier(Register object,
- Register begin,
- Register end,
- Register value_even,
- Register value_odd);
+ void InitializeFieldsNoBarrier(Register object, Register begin, Register end,
+ Register value_even, Register value_odd);
// Like above, for the range [base+begin_offset, base+end_offset), unrolled.
- void InitializeFieldsNoBarrierUnrolled(Register object,
- Register base,
+ void InitializeFieldsNoBarrierUnrolled(Register object, Register base,
intptr_t begin_offset,
intptr_t end_offset,
Register value_even,
Register value_odd);
// Stores a Smi value into a heap object field that always contains a Smi.
- void StoreIntoSmiField(const Address& dest, Register value);
+ void StoreIntoSmiField(const Address &dest, Register value);
void LoadClassId(Register result, Register object, Condition cond = AL);
void LoadClassById(Register result, Register class_id);
@@ -963,69 +934,42 @@
void LoadClassIdMayBeSmi(Register result, Register object);
void LoadTaggedClassIdMayBeSmi(Register result, Register object);
- void ComputeRange(Register result,
- Register value,
- Register scratch,
- Label* miss);
+ void ComputeRange(Register result, Register value, Register scratch,
+ Label *miss);
- void UpdateRangeFeedback(Register value,
- intptr_t idx,
- Register ic_data,
- Register scratch1,
- Register scratch2,
- Label* miss);
+ void UpdateRangeFeedback(Register value, intptr_t idx, Register ic_data,
+ Register scratch1, Register scratch2, Label *miss);
intptr_t FindImmediate(int32_t imm);
- bool CanLoadFromObjectPool(const Object& object) const;
- void LoadFromOffset(OperandSize type,
- Register reg,
- Register base,
- int32_t offset,
- Condition cond = AL);
- void LoadFieldFromOffset(OperandSize type,
- Register reg,
- Register base,
- int32_t offset,
- Condition cond = AL) {
+ bool CanLoadFromObjectPool(const Object &object) const;
+ void LoadFromOffset(OperandSize type, Register reg, Register base,
+ int32_t offset, Condition cond = AL);
+ void LoadFieldFromOffset(OperandSize type, Register reg, Register base,
+ int32_t offset, Condition cond = AL) {
LoadFromOffset(type, reg, base, offset - kHeapObjectTag, cond);
}
- void StoreToOffset(OperandSize type,
- Register reg,
- Register base,
- int32_t offset,
- Condition cond = AL);
- void LoadSFromOffset(SRegister reg,
- Register base,
- int32_t offset,
+ void StoreToOffset(OperandSize type, Register reg, Register base,
+ int32_t offset, Condition cond = AL);
+ void LoadSFromOffset(SRegister reg, Register base, int32_t offset,
Condition cond = AL);
- void StoreSToOffset(SRegister reg,
- Register base,
- int32_t offset,
+ void StoreSToOffset(SRegister reg, Register base, int32_t offset,
Condition cond = AL);
- void LoadDFromOffset(DRegister reg,
- Register base,
- int32_t offset,
+ void LoadDFromOffset(DRegister reg, Register base, int32_t offset,
Condition cond = AL);
- void StoreDToOffset(DRegister reg,
- Register base,
- int32_t offset,
+ void StoreDToOffset(DRegister reg, Register base, int32_t offset,
Condition cond = AL);
- void LoadMultipleDFromOffset(DRegister first,
- intptr_t count,
- Register base,
+ void LoadMultipleDFromOffset(DRegister first, intptr_t count, Register base,
int32_t offset);
- void StoreMultipleDToOffset(DRegister first,
- intptr_t count,
- Register base,
+ void StoreMultipleDToOffset(DRegister first, intptr_t count, Register base,
int32_t offset);
- void CopyDoubleField(Register dst, Register src,
- Register tmp1, Register tmp2, DRegister dtmp);
- void CopyFloat32x4Field(Register dst, Register src,
- Register tmp1, Register tmp2, DRegister dtmp);
- void CopyFloat64x2Field(Register dst, Register src,
- Register tmp1, Register tmp2, DRegister dtmp);
+ void CopyDoubleField(Register dst, Register src, Register tmp1, Register tmp2,
+ DRegister dtmp);
+ void CopyFloat32x4Field(Register dst, Register src, Register tmp1,
+ Register tmp2, DRegister dtmp);
+ void CopyFloat64x2Field(Register dst, Register src, Register tmp1,
+ Register tmp2, DRegister dtmp);
#if 0
// Moved to ARM32::AssemblerARM32::push().
@@ -1061,9 +1005,9 @@
// Moved to ARM32::AssemblerARM32::asr()
void Asr(Register rd, Register rm, Register rs, Condition cond = AL);
#endif
- void Asrs(Register rd, Register rm, const Operand& shift_imm,
+ void Asrs(Register rd, Register rm, const Operand &shift_imm,
Condition cond = AL);
- void Ror(Register rd, Register rm, const Operand& shift_imm,
+ void Ror(Register rd, Register rm, const Operand &shift_imm,
Condition cond = AL);
void Ror(Register rd, Register rm, Register rs, Condition cond = AL);
void Rrx(Register rd, Register rm, Condition cond = AL);
@@ -1097,7 +1041,7 @@
// Untagging shifts tag bit into the carry flag - if carry is clear
// assumption was correct. In this case jump to the is_smi label.
// Otherwise fall-through.
- void SmiUntag(Register dst, Register src, Label* is_smi) {
+ void SmiUntag(Register dst, Register src, Label *is_smi) {
ASSERT(kSmiTagSize == 1);
Asrs(dst, src, Operand(kSmiTagSize));
b(is_smi, CC);
@@ -1117,7 +1061,7 @@
void EnterCallRuntimeFrame(intptr_t frame_space);
void LeaveCallRuntimeFrame();
- void CallRuntime(const RuntimeEntry& entry, intptr_t argument_count);
+ void CallRuntime(const RuntimeEntry &entry, intptr_t argument_count);
// Set up a Dart frame on entry with a frame pointer and PC information to
// enable easy access to the RawInstruction object of code corresponding
@@ -1140,53 +1084,36 @@
// IncrementAllocationStats(WithSize) as stats_addr_reg to update the
// allocation stats. These are separate assembler macros so we can
// avoid a dependent load too nearby the load of the table address.
- void LoadAllocationStatsAddress(Register dest,
- intptr_t cid,
+ void LoadAllocationStatsAddress(Register dest, intptr_t cid,
bool inline_isolate = true);
- void IncrementAllocationStats(Register stats_addr,
- intptr_t cid,
+ void IncrementAllocationStats(Register stats_addr, intptr_t cid,
Heap::Space space);
void IncrementAllocationStatsWithSize(Register stats_addr_reg,
- Register size_reg,
- Heap::Space space);
+ Register size_reg, Heap::Space space);
- Address ElementAddressForIntIndex(bool is_load,
- bool is_external,
- intptr_t cid,
- intptr_t index_scale,
- Register array,
- intptr_t index,
+ Address ElementAddressForIntIndex(bool is_load, bool is_external,
+ intptr_t cid, intptr_t index_scale,
+ Register array, intptr_t index,
Register temp);
- Address ElementAddressForRegIndex(bool is_load,
- bool is_external,
- intptr_t cid,
- intptr_t index_scale,
- Register array,
- Register index);
+ Address ElementAddressForRegIndex(bool is_load, bool is_external,
+ intptr_t cid, intptr_t index_scale,
+ Register array, Register index);
// If allocation tracing for |cid| is enabled, will jump to |trace| label,
// which will allocate in the runtime where tracing occurs.
- void MaybeTraceAllocation(intptr_t cid,
- Register temp_reg,
- Label* trace,
+ void MaybeTraceAllocation(intptr_t cid, Register temp_reg, Label *trace,
bool inline_isolate = true);
// Inlined allocation of an instance of class 'cls', code has no runtime
// calls. Jump to 'failure' if the instance cannot be allocated here.
// Allocated instance is returned in 'instance_reg'.
// Only the tags field of the object is initialized.
- void TryAllocate(const Class& cls,
- Label* failure,
- Register instance_reg,
+ void TryAllocate(const Class &cls, Label *failure, Register instance_reg,
Register temp_reg);
- void TryAllocateArray(intptr_t cid,
- intptr_t instance_size,
- Label* failure,
- Register instance,
- Register end_address,
- Register temp1,
+ void TryAllocateArray(intptr_t cid, intptr_t instance_size, Label *failure,
+ Register instance, Register end_address, Register temp1,
Register temp2);
// Emit data (e.g encoded instruction or immediate) in instruction stream.
@@ -1194,18 +1121,14 @@
// On some other platforms, we draw a distinction between safe and unsafe
// smis.
- static bool IsSafe(const Object& object) { return true; }
- static bool IsSafeSmi(const Object& object) { return object.IsSmi(); }
+ static bool IsSafe(const Object &object) { return true; }
+ static bool IsSafeSmi(const Object &object) { return object.IsSmi(); }
- bool constant_pool_allowed() const {
- return constant_pool_allowed_;
- }
- void set_constant_pool_allowed(bool b) {
- constant_pool_allowed_ = b;
- }
+ bool constant_pool_allowed() const { return constant_pool_allowed_; }
+ void set_constant_pool_allowed(bool b) { constant_pool_allowed_ = b; }
- private:
- AssemblerBuffer buffer_; // Contains position independent code.
+private:
+ AssemblerBuffer buffer_; // Contains position independent code.
ObjectPoolWrapper object_pool_wrapper_;
int32_t prologue_offset_;
@@ -1221,40 +1144,35 @@
void movt(Register rd, uint16_t imm16, Condition cond = AL);
#endif
- void BindARMv6(Label* label);
- void BindARMv7(Label* label);
+ void BindARMv6(Label *label);
+ void BindARMv7(Label *label);
- void LoadWordFromPoolOffset(Register rd,
- int32_t offset,
- Register pp,
+ void LoadWordFromPoolOffset(Register rd, int32_t offset, Register pp,
Condition cond);
- void BranchLink(const ExternalLabel* label);
+ void BranchLink(const ExternalLabel *label);
class CodeComment : public ZoneAllocated {
- public:
- CodeComment(intptr_t pc_offset, const String& comment)
- : pc_offset_(pc_offset), comment_(comment) { }
+ public:
+ CodeComment(intptr_t pc_offset, const String &comment)
+ : pc_offset_(pc_offset), comment_(comment) {}
intptr_t pc_offset() const { return pc_offset_; }
- const String& comment() const { return comment_; }
+ const String &comment() const { return comment_; }
- private:
+ private:
intptr_t pc_offset_;
- const String& comment_;
+ const String &comment_;
DISALLOW_COPY_AND_ASSIGN(CodeComment);
};
- GrowableArray<CodeComment*> comments_;
+ GrowableArray<CodeComment *> comments_;
bool constant_pool_allowed_;
- void LoadObjectHelper(Register rd,
- const Object& object,
- Condition cond,
- bool is_unique,
- Register pp);
+ void LoadObjectHelper(Register rd, const Object &object, Condition cond,
+ bool is_unique, Register pp);
#if 0
// Moved to ARM32::AssemblerARM32::emitType01()
@@ -1290,16 +1208,10 @@
RegList regs);
#endif
- void EmitShiftImmediate(Condition cond,
- Shift opcode,
- Register rd,
- Register rm,
- Operand o);
+ void EmitShiftImmediate(Condition cond, Shift opcode, Register rd,
+ Register rm, Operand o);
- void EmitShiftRegister(Condition cond,
- Shift opcode,
- Register rd,
- Register rm,
+ void EmitShiftRegister(Condition cond, Shift opcode, Register rd, Register rm,
Operand o);
#if 0
@@ -1319,19 +1231,11 @@
Register rm);
#endif
- void EmitMultiVSMemOp(Condition cond,
- BlockAddressMode am,
- bool load,
- Register base,
- SRegister start,
- uint32_t count);
+ void EmitMultiVSMemOp(Condition cond, BlockAddressMode am, bool load,
+ Register base, SRegister start, uint32_t count);
- void EmitMultiVDMemOp(Condition cond,
- BlockAddressMode am,
- bool load,
- Register base,
- DRegister start,
- int32_t count);
+ void EmitMultiVDMemOp(Condition cond, BlockAddressMode am, bool load,
+ Register base, DRegister start, int32_t count);
#if 0
// Moved to ARM32::AssemblerARM32::emitVFPsss
@@ -1365,8 +1269,8 @@
QRegister qd, QRegister qn, QRegister qm);
#endif
- void EmitSIMDddd(int32_t opcode, OperandSize sz,
- DRegister dd, DRegister dn, DRegister dm);
+ void EmitSIMDddd(int32_t opcode, OperandSize sz, DRegister dd, DRegister dn,
+ DRegister dm);
void EmitFarBranch(Condition cond, int32_t offset, bool link);
#if 0
@@ -1380,31 +1284,25 @@
int32_t EncodeTstOffset(int32_t offset, int32_t inst);
int32_t DecodeTstOffset(int32_t inst);
- void StoreIntoObjectFilter(Register object, Register value, Label* no_update);
+ void StoreIntoObjectFilter(Register object, Register value, Label *no_update);
// Shorter filtering sequence that assumes that value is not a smi.
- void StoreIntoObjectFilterNoSmi(Register object,
- Register value,
- Label* no_update);
+ void StoreIntoObjectFilterNoSmi(Register object, Register value,
+ Label *no_update);
// Helpers for write-barrier verification.
// Returns VerifiedMemory::offset() as an Operand.
Operand GetVerifiedMemoryShadow();
// Writes value to [base + offset] and also its shadow location, if enabled.
- void WriteShadowedField(Register base,
- intptr_t offset,
- Register value,
+ void WriteShadowedField(Register base, intptr_t offset, Register value,
Condition cond = AL);
- void WriteShadowedFieldPair(Register base,
- intptr_t offset,
- Register value_even,
- Register value_odd,
+ void WriteShadowedFieldPair(Register base, intptr_t offset,
+ Register value_even, Register value_odd,
Condition cond = AL);
// Writes new_value to address and its shadow location, if enabled, after
// verifying that its old value matches its shadow.
- void VerifiedWrite(const Address& address,
- Register new_value,
+ void VerifiedWrite(const Address &address, Register new_value,
FieldContent old_content);
#if 0
@@ -1429,6 +1327,6 @@
DISALLOW_COPY_AND_ASSIGN(Assembler);
};
-} // namespace dart
+} // namespace dart
-#endif // VM_ASSEMBLER_ARM_H_
+#endif // VM_ASSEMBLER_ARM_H_
diff --git a/third_party/subzero/src/IceAssemblerARM32.cpp b/third_party/subzero/src/IceAssemblerARM32.cpp
index 4b1fcb9..0557e21 100644
--- a/third_party/subzero/src/IceAssemblerARM32.cpp
+++ b/third_party/subzero/src/IceAssemblerARM32.cpp
@@ -642,10 +642,12 @@
const bool NeedsPCRelSuffix =
(Asm.fixupIsPCRel(kind()) || Symbol == GlobalOffsetTable);
Str << "\t"
- "mov" << (IsMovw ? "w" : "t") << "\t"
+ "mov"
+ << (IsMovw ? "w" : "t") << "\t"
<< RegARM32::getRegName(RegNumT::fixme((Inst >> kRdShift) & 0xF))
<< ", #:" << (IsMovw ? "lower" : "upper") << "16:" << Symbol
- << (NeedsPCRelSuffix ? " - ." : "") << "\t@ .word "
+ << (NeedsPCRelSuffix ? " - ." : "")
+ << "\t@ .word "
// TODO(jpp): This is broken, it also needs to add a magic constant.
<< llvm::format_hex_no_prefix(Inst, 8) << "\n";
return InstARM32::InstSize;
@@ -700,8 +702,9 @@
Ostream &Str = Ctx->getStrEmit();
IValueT Inst = Asm.load<IValueT>(position());
Str << "\t"
- "bl\t" << symbol() << "\t@ .word "
- << llvm::format_hex_no_prefix(Inst, 8) << "\n";
+ "bl\t"
+ << symbol() << "\t@ .word " << llvm::format_hex_no_prefix(Inst, 8)
+ << "\n";
return InstARM32::InstSize;
}
diff --git a/third_party/subzero/src/IceAssemblerMIPS32.cpp b/third_party/subzero/src/IceAssemblerMIPS32.cpp
index f1a656d..1e58503 100644
--- a/third_party/subzero/src/IceAssemblerMIPS32.cpp
+++ b/third_party/subzero/src/IceAssemblerMIPS32.cpp
@@ -737,7 +737,9 @@
emitFtRsImm16(Opcode, OpRt, OpBase, Offset, "ldc1");
break;
}
- default: { UnimplementedError(getFlags()); }
+ default: {
+ UnimplementedError(getFlags());
+ }
}
}
@@ -825,7 +827,9 @@
emitInst(Opcode);
break;
}
- default: { UnimplementedError(getFlags()); }
+ default: {
+ UnimplementedError(getFlags());
+ }
}
}
}
@@ -1115,7 +1119,9 @@
emitFtRsImm16(Opcode, OpRt, OpBase, Offset, "sdc1");
break;
}
- default: { UnimplementedError(getFlags()); }
+ default: {
+ UnimplementedError(getFlags());
+ }
}
}
diff --git a/third_party/subzero/src/IceBitVector.h b/third_party/subzero/src/IceBitVector.h
index 742d2b4..70fccdb 100644
--- a/third_party/subzero/src/IceBitVector.h
+++ b/third_party/subzero/src/IceBitVector.h
@@ -825,6 +825,6 @@
inline void swap(Ice::BitVectorTmpl<AT> &LHS, Ice::BitVectorTmpl<AT> &RHS) {
LHS.swap(RHS);
}
-}
+} // namespace std
#endif // SUBZERO_SRC_ICEBITVECTOR_H
diff --git a/third_party/subzero/src/IceCfg.cpp b/third_party/subzero/src/IceCfg.cpp
index f75ca29..ce09d5c 100644
--- a/third_party/subzero/src/IceCfg.cpp
+++ b/third_party/subzero/src/IceCfg.cpp
@@ -94,8 +94,8 @@
++InstCount;
}
}
- return getFunctionName() + "(i=" + std::to_string(InstCount) + ":b=" +
- std::to_string(NodeCount) + ")";
+ return getFunctionName() + "(i=" + std::to_string(InstCount) +
+ ":b=" + std::to_string(NodeCount) + ")";
}
void Cfg::setError(const std::string &Message) {
@@ -228,9 +228,9 @@
if (BuildDefs::dump()) {
if (isVerbose(IceV_Status) &&
getFlags().matchTestStatus(getFunctionName(), getSequenceNumber())) {
- getContext()->getStrDump() << ">>>Translating "
- << getFunctionNameAndSize()
- << " seq=" << getSequenceNumber() << "\n";
+ getContext()->getStrDump()
+ << ">>>Translating " << getFunctionNameAndSize()
+ << " seq=" << getSequenceNumber() << "\n";
}
}
TimerMarker T_func(getContext(), getFunctionName().toStringOrEmpty());
diff --git a/third_party/subzero/src/IceCfgNode.cpp b/third_party/subzero/src/IceCfgNode.cpp
index d8e95af..7170bef 100644
--- a/third_party/subzero/src/IceCfgNode.cpp
+++ b/third_party/subzero/src/IceCfgNode.cpp
@@ -776,10 +776,10 @@
return true;
// Verify there are no duplicates.
- auto ComparePair =
- [](const LiveBeginEndMapEntry &A, const LiveBeginEndMapEntry &B) {
- return A.first == B.first;
- };
+ auto ComparePair = [](const LiveBeginEndMapEntry &A,
+ const LiveBeginEndMapEntry &B) {
+ return A.first == B.first;
+ };
LiveBeginEndMap &MapBegin = *Liveness->getLiveBegin(this);
LiveBeginEndMap &MapEnd = *Liveness->getLiveEnd(this);
if (std::adjacent_find(MapBegin.begin(), MapBegin.end(), ComparePair) ==
diff --git a/third_party/subzero/src/IceCfgNode.h b/third_party/subzero/src/IceCfgNode.h
index b2d2de8..3406bd8 100644
--- a/third_party/subzero/src/IceCfgNode.h
+++ b/third_party/subzero/src/IceCfgNode.h
@@ -127,8 +127,8 @@
}
CfgNode *shortCircuit();
- inline void* getExternalData() const { return externalData; }
- inline void setExternalData(void* data) { externalData = data; }
+ inline void *getExternalData() const { return externalData; }
+ inline void setExternalData(void *data) { externalData = data; }
private:
CfgNode(Cfg *Func, SizeT Number)
@@ -152,7 +152,7 @@
/// External data can be set by an optimizer to compute and retain any
/// information related to the current node. All the memory used to
/// store this information must be managed by the optimizer.
- void* externalData = nullptr;
+ void *externalData = nullptr;
};
} // end of namespace Ice
diff --git a/third_party/subzero/src/IceClFlags.h b/third_party/subzero/src/IceClFlags.h
index 27ca582..925731e 100644
--- a/third_party/subzero/src/IceClFlags.h
+++ b/third_party/subzero/src/IceClFlags.h
@@ -15,9 +15,9 @@
#ifndef SUBZERO_SRC_ICECLFLAGS_H
#define SUBZERO_SRC_ICECLFLAGS_H
-#include "IceDefs.h"
#include "IceBuildDefs.h"
#include "IceClFlags.def"
+#include "IceDefs.h"
#include "IceRangeSpec.h"
#include "IceTypes.h"
diff --git a/third_party/subzero/src/IceCompileServer.cpp b/third_party/subzero/src/IceCompileServer.cpp
index 570ccfa..3e97a40 100644
--- a/third_party/subzero/src/IceCompileServer.cpp
+++ b/third_party/subzero/src/IceCompileServer.cpp
@@ -30,10 +30,10 @@
#include "llvm/Bitcode/NaCl/NaClBitcodeMungeUtils.h"
#endif // PNACL_LLVM
#include "llvm/Support/FileSystem.h"
-#include "llvm/Support/raw_os_ostream.h"
#include "llvm/Support/Signals.h"
#include "llvm/Support/SourceMgr.h"
#include "llvm/Support/StreamingMemoryObject.h"
+#include "llvm/Support/raw_os_ostream.h"
#ifdef __clang__
#pragma clang diagnostic pop
@@ -205,7 +205,8 @@
Flags.getOutputFilename(), EC, llvm::sys::fs::F_None));
if (EC) {
*Ls << "Failed to open output file: " << Flags.getOutputFilename()
- << ":\n" << EC.message() << "\n";
+ << ":\n"
+ << EC.message() << "\n";
return transferErrorCode(getReturnValue(Ice::EC_Args));
}
ELFStr.reset(new ELFFileStreamer(*FdOs.get()));
@@ -219,7 +220,8 @@
Os = makeStream(Flags.getOutputFilename(), EC);
if (EC) {
*Ls << "Failed to open output file: " << Flags.getOutputFilename()
- << ":\n" << EC.message() << "\n";
+ << ":\n"
+ << EC.message() << "\n";
return transferErrorCode(getReturnValue(Ice::EC_Args));
}
Os->SetUnbuffered();
diff --git a/third_party/subzero/src/IceCompileServer.h b/third_party/subzero/src/IceCompileServer.h
index ca02577..3b4726d 100644
--- a/third_party/subzero/src/IceCompileServer.h
+++ b/third_party/subzero/src/IceCompileServer.h
@@ -25,7 +25,7 @@
namespace llvm {
class DataStreamer;
class raw_fd_ostream;
-}
+} // namespace llvm
namespace Ice {
diff --git a/third_party/subzero/src/IceConverter.cpp b/third_party/subzero/src/IceConverter.cpp
index 7d192e6..bb113c8 100644
--- a/third_party/subzero/src/IceConverter.cpp
+++ b/third_party/subzero/src/IceConverter.cpp
@@ -24,8 +24,8 @@
#include "IceMangling.h"
#include "IceOperand.h"
#include "IceTargetLowering.h"
-#include "IceTypes.h"
#include "IceTypeConverter.h"
+#include "IceTypes.h"
#ifdef __clang__
#pragma clang diagnostic push
diff --git a/third_party/subzero/src/IceConverter.h b/third_party/subzero/src/IceConverter.h
index c670b50..bb904db 100644
--- a/third_party/subzero/src/IceConverter.h
+++ b/third_party/subzero/src/IceConverter.h
@@ -21,7 +21,7 @@
namespace llvm {
class GlobalValue;
class Module;
-}
+} // namespace llvm
namespace Ice {
@@ -73,6 +73,6 @@
void installGlobalDeclarations(llvm::Module *Mod);
};
-} // end of namespace ICE.
+} // namespace Ice
#endif // SUBZERO_SRC_ICECONVERTER_H
diff --git a/third_party/subzero/src/IceDefs.h b/third_party/subzero/src/IceDefs.h
index 3e6519a..c5f7f5d 100644
--- a/third_party/subzero/src/IceDefs.h
+++ b/third_party/subzero/src/IceDefs.h
@@ -21,11 +21,11 @@
#include "IceTLS.h"
#include "llvm/ADT/ArrayRef.h"
+#include "llvm/ADT/STLExtras.h"
+#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/ilist.h"
#include "llvm/ADT/ilist_node.h"
#include "llvm/ADT/iterator_range.h"
-#include "llvm/ADT/SmallVector.h"
-#include "llvm/ADT/STLExtras.h"
#include "llvm/Support/Casting.h"
#include "llvm/Support/ELF.h"
#include "llvm/Support/raw_ostream.h"
diff --git a/third_party/subzero/src/IceELFObjectWriter.cpp b/third_party/subzero/src/IceELFObjectWriter.cpp
index 4663b71..6517f39 100644
--- a/third_party/subzero/src/IceELFObjectWriter.cpp
+++ b/third_party/subzero/src/IceELFObjectWriter.cpp
@@ -36,8 +36,7 @@
uint32_t ELFFlags;
} ELFTargetInfo[TargetArch_NUM] = {
#define X(tag, str, is_elf64, e_machine, e_flags) \
- { is_elf64, e_machine, e_flags } \
- ,
+ {is_elf64, e_machine, e_flags},
TARGETARCH_TABLE
#undef X
};
diff --git a/third_party/subzero/src/IceELFSection.cpp b/third_party/subzero/src/IceELFSection.cpp
index cc8e1e5..89d58d0 100644
--- a/third_party/subzero/src/IceELFSection.cpp
+++ b/third_party/subzero/src/IceELFSection.cpp
@@ -202,8 +202,8 @@
return It->second;
}
-bool ELFStringTableSection::SuffixComparator::
-operator()(const std::string &StrA, const std::string &StrB) const {
+bool ELFStringTableSection::SuffixComparator::operator()(
+ const std::string &StrA, const std::string &StrB) const {
size_t LenA = StrA.size();
size_t LenB = StrB.size();
size_t CommonLen = std::min(LenA, LenB);
diff --git a/third_party/subzero/src/IceGlobalContext.h b/third_party/subzero/src/IceGlobalContext.h
index 1843fd9..ba0bc09 100644
--- a/third_party/subzero/src/IceGlobalContext.h
+++ b/third_party/subzero/src/IceGlobalContext.h
@@ -16,8 +16,8 @@
#ifndef SUBZERO_SRC_ICEGLOBALCONTEXT_H
#define SUBZERO_SRC_ICEGLOBALCONTEXT_H
-#include "IceDefs.h"
#include "IceClFlags.h"
+#include "IceDefs.h"
#include "IceInstrumentation.h"
#include "IceIntrinsics.h"
#include "IceRNG.h"
diff --git a/third_party/subzero/src/IceInst.cpp b/third_party/subzero/src/IceInst.cpp
index a40d234..7cf0a34 100644
--- a/third_party/subzero/src/IceInst.cpp
+++ b/third_party/subzero/src/IceInst.cpp
@@ -33,9 +33,7 @@
const char *DisplayString;
bool IsCommutative;
} InstArithmeticAttributes[] = {
-#define X(tag, str, commutative) \
- { str, commutative } \
- ,
+#define X(tag, str, commutative) {str, commutative},
ICEINSTARITHMETIC_TABLE
#undef X
};
@@ -44,9 +42,7 @@
const struct InstCastAttributes_ {
const char *DisplayString;
} InstCastAttributes[] = {
-#define X(tag, str) \
- { str } \
- ,
+#define X(tag, str) {str},
ICEINSTCAST_TABLE
#undef X
};
@@ -55,9 +51,7 @@
const struct InstFcmpAttributes_ {
const char *DisplayString;
} InstFcmpAttributes[] = {
-#define X(tag, str) \
- { str } \
- ,
+#define X(tag, str) {str},
ICEINSTFCMP_TABLE
#undef X
};
@@ -67,9 +61,7 @@
const char *DisplayString;
InstIcmp::ICond Reverse;
} InstIcmpAttributes[] = {
-#define X(tag, reverse, str) \
- { str, InstIcmp::ICond::reverse } \
- ,
+#define X(tag, reverse, str) {str, InstIcmp::ICond::reverse},
ICEINSTICMP_TABLE
#undef X
};
diff --git a/third_party/subzero/src/IceInst.h b/third_party/subzero/src/IceInst.h
index f1caeb4..502d29f 100644
--- a/third_party/subzero/src/IceInst.h
+++ b/third_party/subzero/src/IceInst.h
@@ -199,8 +199,8 @@
llvm::report_fatal_error("Inst unexpectedly deleted");
}
- inline void* getExternalData() const { return externalData; }
- inline void setExternalData(void* data) { externalData = data; }
+ inline void *getExternalData() const { return externalData; }
+ inline void setExternalData(void *data) { externalData = data; }
protected:
Inst(Cfg *Func, InstKind Kind, SizeT MaxSrcs, Variable *Dest);
@@ -242,7 +242,7 @@
/// External data can be set by an optimizer to compute and retain any
/// information related to the current instruction. All the memory used to
/// store this information must be managed by the optimizer.
- void* externalData = nullptr;
+ void *externalData = nullptr;
Variable *Dest;
const SizeT MaxSrcs; // only used for assert
diff --git a/third_party/subzero/src/IceInstARM32.cpp b/third_party/subzero/src/IceInstARM32.cpp
index 646730f..d015b55 100644
--- a/third_party/subzero/src/IceInstARM32.cpp
+++ b/third_party/subzero/src/IceInstARM32.cpp
@@ -42,8 +42,7 @@
} TypeARM32Attributes[] = {
#define X(tag, elementty, int_width, fp_width, uvec_width, svec_width, sbits, \
ubits, rraddr, shaddr) \
- { int_width, fp_width, svec_width, uvec_width, sbits, ubits } \
- ,
+ {int_width, fp_width, svec_width, uvec_width, sbits, ubits},
ICETYPEARM32_TABLE
#undef X
};
@@ -51,9 +50,7 @@
const struct InstARM32ShiftAttributes_ {
const char *EmitString;
} InstARM32ShiftAttributes[] = {
-#define X(tag, emit) \
- { emit } \
- ,
+#define X(tag, emit) {emit},
ICEINSTARM32SHIFT_TABLE
#undef X
};
@@ -62,9 +59,7 @@
CondARM32::Cond Opposite;
const char *EmitString;
} InstARM32CondAttributes[] = {
-#define X(tag, encode, opp, emit) \
- { CondARM32::opp, emit } \
- ,
+#define X(tag, encode, opp, emit) {CondARM32::opp, emit},
ICEINSTARM32COND_TABLE
#undef X
};
@@ -1915,7 +1910,8 @@
assert(Src->hasReg());
Str << "\t"
- "vmov" << getPredicate() << "\t";
+ "vmov"
+ << getPredicate() << "\t";
DestLo->emit(Func);
Str << ", ";
DestHi->emit(Func);
@@ -1937,7 +1933,8 @@
assert(getSrcSize() == 2);
Str << "\t"
- "vmov" << getPredicate() << "\t";
+ "vmov"
+ << getPredicate() << "\t";
Dest->emit(Func);
Str << ", ";
SrcLo->emit(Func);
@@ -2170,7 +2167,8 @@
return;
Ostream &Str = Func->getContext()->getStrEmit();
Str << "\t"
- "b" << getPredicate() << "\t";
+ "b"
+ << getPredicate() << "\t";
if (Label) {
Str << Label->getLabelName();
} else {
@@ -2972,7 +2970,8 @@
assert(getSrcSize() == 2);
assert(getDest()->hasReg());
Str << "\t"
- "umull" << getPredicate() << "\t";
+ "umull"
+ << getPredicate() << "\t";
getDest()->emit(Func);
Str << ", ";
DestHi->emit(Func);
@@ -3044,7 +3043,8 @@
assert(getSrcSize() == 1);
assert(getDest()->hasReg());
Str << "\t"
- "vcvt" << getPredicate() << vcvtVariantSuffix(Variant) << "\t";
+ "vcvt"
+ << getPredicate() << vcvtVariantSuffix(Variant) << "\t";
getDest()->emit(Func);
Str << ", ";
getSrc(0)->emit(Func);
@@ -3115,8 +3115,8 @@
Ostream &Str = Func->getContext()->getStrEmit();
assert(getSrcSize() == 2);
Str << "\t"
- "vcmp" << getPredicate() << getFpWidthString(getSrc(0)->getType())
- << "\t";
+ "vcmp"
+ << getPredicate() << getFpWidthString(getSrc(0)->getType()) << "\t";
getSrc(0)->emit(Func);
Str << ", ";
getSrc(1)->emit(Func);
@@ -3169,10 +3169,12 @@
Ostream &Str = Func->getContext()->getStrEmit();
assert(getSrcSize() == 0);
Str << "\t"
- "vmrs" << getPredicate() << "\t"
- "APSR_nzcv"
- ", "
- "FPSCR";
+ "vmrs"
+ << getPredicate()
+ << "\t"
+ "APSR_nzcv"
+ ", "
+ "FPSCR";
}
void InstARM32Vmrs::emitIAS(const Cfg *Func) const {
@@ -3185,8 +3187,9 @@
if (!BuildDefs::dump())
return;
Ostream &Str = Func->getContext()->getStrDump();
- Str << "APSR{n,z,v,c} = vmrs" << getPredicate() << "\t"
- "FPSCR{n,z,c,v}";
+ Str << "APSR{n,z,v,c} = vmrs" << getPredicate()
+ << "\t"
+ "FPSCR{n,z,c,v}";
}
void InstARM32Vabs::emit(const Cfg *Func) const {
@@ -3195,8 +3198,8 @@
Ostream &Str = Func->getContext()->getStrEmit();
assert(getSrcSize() == 1);
Str << "\t"
- "vabs" << getPredicate() << getFpWidthString(getSrc(0)->getType())
- << "\t";
+ "vabs"
+ << getPredicate() << getFpWidthString(getSrc(0)->getType()) << "\t";
getDest()->emit(Func);
Str << ", ";
getSrc(0)->emit(Func);
diff --git a/third_party/subzero/src/IceInstMIPS32.cpp b/third_party/subzero/src/IceInstMIPS32.cpp
index 1506e02..e1b8cb9 100644
--- a/third_party/subzero/src/IceInstMIPS32.cpp
+++ b/third_party/subzero/src/IceInstMIPS32.cpp
@@ -12,11 +12,11 @@
/// constructors and the dump()/emit() methods.
///
//===----------------------------------------------------------------------===//
+#include "IceInstMIPS32.h"
#include "IceAssemblerMIPS32.h"
#include "IceCfg.h"
#include "IceCfgNode.h"
#include "IceInst.h"
-#include "IceInstMIPS32.h"
#include "IceOperand.h"
#include "IceRegistersMIPS32.h"
#include "IceTargetLoweringMIPS32.h"
@@ -29,9 +29,7 @@
CondMIPS32::Cond Opposite;
const char *EmitString;
} InstMIPS32CondAttributes[] = {
-#define X(tag, opp, emit) \
- { CondMIPS32::opp, emit } \
- ,
+#define X(tag, opp, emit) {CondMIPS32::opp, emit},
ICEINSTMIPS32COND_TABLE
#undef X
};
@@ -477,7 +475,8 @@
return;
Ostream &Str = Func->getContext()->getStrEmit();
Str << "\t"
- "b" << InstMIPS32CondAttributes[Predicate].EmitString << "\t";
+ "b"
+ << InstMIPS32CondAttributes[Predicate].EmitString << "\t";
if (Label != nullptr) {
if (isUnconditionalBranch()) {
Str << Label->getLabelName();
@@ -528,7 +527,8 @@
return;
Ostream &Str = Func->getContext()->getStrDump();
Str << "\t"
- "b" << InstMIPS32CondAttributes[Predicate].EmitString << "\t";
+ "b"
+ << InstMIPS32CondAttributes[Predicate].EmitString << "\t";
if (Label != nullptr) {
if (isUnconditionalBranch()) {
diff --git a/third_party/subzero/src/IceInstX8632.cpp b/third_party/subzero/src/IceInstX8632.cpp
index 00a455c..136858c 100644
--- a/third_party/subzero/src/IceInstX8632.cpp
+++ b/third_party/subzero/src/IceInstX8632.cpp
@@ -22,9 +22,9 @@
#include "IceCfgNode.h"
#include "IceConditionCodesX8632.h"
#include "IceInst.h"
+#include "IceOperand.h"
#include "IceRegistersX8632.h"
#include "IceTargetLoweringX8632.h"
-#include "IceOperand.h"
namespace Ice {
@@ -32,18 +32,14 @@
const TargetX8632Traits::InstBrAttributesType
TargetX8632Traits::InstBrAttributes[] = {
-#define X(val, encode, opp, dump, emit) \
- { X8632::Traits::Cond::opp, dump, emit } \
- ,
+#define X(val, encode, opp, dump, emit) {X8632::Traits::Cond::opp, dump, emit},
ICEINSTX8632BR_TABLE
#undef X
};
const TargetX8632Traits::InstCmppsAttributesType
TargetX8632Traits::InstCmppsAttributes[] = {
-#define X(val, emit) \
- { emit } \
- ,
+#define X(val, emit) {emit},
ICEINSTX8632CMPPS_TABLE
#undef X
};
@@ -51,8 +47,7 @@
const TargetX8632Traits::TypeAttributesType
TargetX8632Traits::TypeAttributes[] = {
#define X(tag, elty, cvt, sdss, pdps, spsd, int_, unpack, pack, width, fld) \
- { cvt, sdss, pdps, spsd, int_, unpack, pack, width, fld } \
- ,
+ {cvt, sdss, pdps, spsd, int_, unpack, pack, width, fld},
ICETYPEX8632_TABLE
#undef X
};
diff --git a/third_party/subzero/src/IceInstX8664.cpp b/third_party/subzero/src/IceInstX8664.cpp
index 7f1fa52..1377ae8 100644
--- a/third_party/subzero/src/IceInstX8664.cpp
+++ b/third_party/subzero/src/IceInstX8664.cpp
@@ -23,9 +23,9 @@
#include "IceCfgNode.h"
#include "IceConditionCodesX8664.h"
#include "IceInst.h"
+#include "IceOperand.h"
#include "IceRegistersX8664.h"
#include "IceTargetLoweringX8664.h"
-#include "IceOperand.h"
namespace Ice {
@@ -33,18 +33,14 @@
const TargetX8664Traits::InstBrAttributesType
TargetX8664Traits::InstBrAttributes[] = {
-#define X(val, encode, opp, dump, emit) \
- { X8664::Traits::Cond::opp, dump, emit } \
- ,
+#define X(val, encode, opp, dump, emit) {X8664::Traits::Cond::opp, dump, emit},
ICEINSTX8664BR_TABLE
#undef X
};
const TargetX8664Traits::InstCmppsAttributesType
TargetX8664Traits::InstCmppsAttributes[] = {
-#define X(val, emit) \
- { emit } \
- ,
+#define X(val, emit) {emit},
ICEINSTX8664CMPPS_TABLE
#undef X
};
@@ -52,8 +48,7 @@
const TargetX8664Traits::TypeAttributesType
TargetX8664Traits::TypeAttributes[] = {
#define X(tag, elty, cvt, sdss, pdps, spsd, int_, unpack, pack, width, fld) \
- { cvt, sdss, pdps, spsd, int_, unpack, pack, width, fld } \
- ,
+ {cvt, sdss, pdps, spsd, int_, unpack, pack, width, fld},
ICETYPEX8664_TABLE
#undef X
};
@@ -159,15 +154,17 @@
if (!NeedSandboxing) {
// TODO(jpp): stop abusing the operand's type to identify LEAs.
const Type MemType = getType();
- if (Base->getType() != IceType_i32 && MemType != IceType_void && !isVectorType(MemType)) {
+ if (Base->getType() != IceType_i32 && MemType != IceType_void &&
+ !isVectorType(MemType)) {
// X86-64 is ILP32, but %rsp and %rbp are accessed as 64-bit registers.
// For filetype=asm, they need to be emitted as their 32-bit siblings.
assert(Base->getType() == IceType_i64);
assert(getEncodedGPR(Base->getRegNum()) == RegX8664::Encoded_Reg_rsp ||
getEncodedGPR(Base->getRegNum()) == RegX8664::Encoded_Reg_rbp ||
getType() == IceType_void);
- B = B->asType(Func, IceType_i32, X8664::Traits::getGprForType(
- IceType_i32, Base->getRegNum()));
+ B = B->asType(
+ Func, IceType_i32,
+ X8664::Traits::getGprForType(IceType_i32, Base->getRegNum()));
}
}
diff --git a/third_party/subzero/src/IceInstX86BaseImpl.h b/third_party/subzero/src/IceInstX86BaseImpl.h
index cf976ac..20636ea 100644
--- a/third_party/subzero/src/IceInstX86BaseImpl.h
+++ b/third_party/subzero/src/IceInstX86BaseImpl.h
@@ -499,7 +499,8 @@
Str << "\t" << getTargetTrue()->getAsmName();
if (getTargetFalse()) {
Str << "\n\t"
- "jmp\t" << getTargetFalse()->getAsmName();
+ "jmp\t"
+ << getTargetFalse()->getAsmName();
}
}
}
@@ -571,7 +572,8 @@
if (const auto *CR = llvm::dyn_cast<ConstantRelocatable>(Src)) {
Str << "\t"
"jmp"
- "\t" << CR->getName();
+ "\t"
+ << CR->getName();
return;
}
}
@@ -1082,7 +1084,8 @@
Type Ty = this->getSrc(0)->getType();
assert(isScalarFloatingType(Ty));
Str << "\t"
- "sqrt" << Traits::TypeAttributes[Ty].SpSdString << "\t";
+ "sqrt"
+ << Traits::TypeAttributes[Ty].SpSdString << "\t";
this->getSrc(0)->emit(Func);
Str << ", ";
this->getDest()->emit(Func);
@@ -1201,7 +1204,8 @@
this->getSrc(1)->emit(Func);
} else if (llvm::isa<Constant>(this->getSrc(1))) {
Str << "\t"
- "imul" << this->getWidthString(Dest->getType()) << "\t";
+ "imul"
+ << this->getWidthString(Dest->getType()) << "\t";
this->getSrc(1)->emit(Func);
Str << ", ";
this->getSrc(0)->emit(Func);
@@ -1246,7 +1250,8 @@
assert(Dest->getType() == IceType_i16 || Dest->getType() == IceType_i32);
assert(llvm::isa<Constant>(this->getSrc(1)));
Str << "\t"
- "imul" << this->getWidthString(Dest->getType()) << "\t";
+ "imul"
+ << this->getWidthString(Dest->getType()) << "\t";
this->getSrc(1)->emit(Func);
Str << ", ";
this->getSrc(0)->emit(Func);
@@ -1374,7 +1379,8 @@
// allow
// edx?
Str << "\t"
- "mul" << this->getWidthString(this->getDest()->getType()) << "\t";
+ "mul"
+ << this->getWidthString(this->getDest()->getType()) << "\t";
this->getSrc(1)->emit(Func);
}
@@ -1412,7 +1418,8 @@
assert(this->getSrcSize() == 3);
assert(Dest == this->getSrc(0));
Str << "\t"
- "shld" << this->getWidthString(Dest->getType()) << "\t";
+ "shld"
+ << this->getWidthString(Dest->getType()) << "\t";
this->getSrc(2)->emit(Func);
Str << ", ";
this->getSrc(1)->emit(Func);
@@ -1450,7 +1457,8 @@
assert(this->getSrcSize() == 3);
assert(Dest == this->getSrc(0));
Str << "\t"
- "shrd" << this->getWidthString(Dest->getType()) << "\t";
+ "shrd"
+ << this->getWidthString(Dest->getType()) << "\t";
this->getSrc(2)->emit(Func);
Str << ", ";
this->getSrc(1)->emit(Func);
@@ -1546,7 +1554,8 @@
assert(Condition < Cond::Cmpps_Invalid);
Type DestTy = this->Dest->getType();
Str << "\t"
- "cmp" << Traits::InstCmppsAttributes[Condition].EmitString
+ "cmp"
+ << Traits::InstCmppsAttributes[Condition].EmitString
<< Traits::TypeAttributes[DestTy].PdPsString << "\t";
this->getSrc(1)->emit(Func);
Str << ", ";
@@ -1582,8 +1591,9 @@
Ostream &Str = Func->getContext()->getStrDump();
assert(Condition < Cond::Cmpps_Invalid);
this->dumpDest(Func);
- Str << " = cmp" << Traits::InstCmppsAttributes[Condition].EmitString << "ps"
- "\t";
+ Str << " = cmp" << Traits::InstCmppsAttributes[Condition].EmitString
+ << "ps"
+ "\t";
this->dumpSources(Func);
}
@@ -1598,7 +1608,8 @@
"lock";
}
Str << "\t"
- "cmpxchg" << this->getWidthString(this->getSrc(0)->getType()) << "\t";
+ "cmpxchg"
+ << this->getWidthString(this->getSrc(0)->getType()) << "\t";
this->getSrc(2)->emit(Func);
Str << ", ";
this->getSrc(0)->emit(Func);
@@ -1824,7 +1835,8 @@
Ostream &Str = Func->getContext()->getStrEmit();
assert(this->getSrcSize() == 2);
Str << "\t"
- "cmp" << this->getWidthString(this->getSrc(0)->getType()) << "\t";
+ "cmp"
+ << this->getWidthString(this->getSrc(0)->getType()) << "\t";
this->getSrc(1)->emit(Func);
Str << ", ";
this->getSrc(0)->emit(Func);
@@ -1950,7 +1962,8 @@
Ostream &Str = Func->getContext()->getStrEmit();
assert(this->getSrcSize() == 2);
Str << "\t"
- "test" << this->getWidthString(this->getSrc(0)->getType()) << "\t";
+ "test"
+ << this->getWidthString(this->getSrc(0)->getType()) << "\t";
this->getSrc(1)->emit(Func);
Str << ", ";
this->getSrc(0)->emit(Func);
@@ -2018,8 +2031,9 @@
assert(this->getSrcSize() == 2);
Type Ty = this->getSrc(0)->getType();
Str << "\t"
- "mov" << this->getWidthString(Ty)
- << Traits::TypeAttributes[Ty].SdSsString << "\t";
+ "mov"
+ << this->getWidthString(Ty) << Traits::TypeAttributes[Ty].SdSsString
+ << "\t";
this->getSrc(0)->emit(Func);
Str << ", ";
this->getSrc(1)->emit(Func);
@@ -2198,7 +2212,8 @@
assert(this->getSrcSize() == 1);
assert(this->getDest()->hasReg());
Str << "\t"
- "lea" << this->getWidthString(this->getDest()->getType()) << "\t";
+ "lea"
+ << this->getWidthString(this->getDest()->getType()) << "\t";
Operand *Src0 = this->getSrc(0);
if (const auto *Src0Var = llvm::dyn_cast<Variable>(Src0)) {
Type Ty = Src0Var->getType();
@@ -2230,9 +2245,11 @@
"\t";
} else {
Str << "\t"
- "mov" << (!isScalarFloatingType(DestTy)
- ? this->getWidthString(DestTy)
- : Traits::TypeAttributes[DestTy].SdSsString) << "\t";
+ "mov"
+ << (!isScalarFloatingType(DestTy)
+ ? this->getWidthString(DestTy)
+ : Traits::TypeAttributes[DestTy].SdSsString)
+ << "\t";
}
// For an integer truncation operation, src is wider than dest. In this case,
// we use a mov instruction whose data width matches the narrower dest.
@@ -2568,7 +2585,8 @@
Ostream &Str = Func->getContext()->getStrEmit();
// TODO: Emit the right code for each variant.
Str << "\t"
- "nop\t/* variant = " << Variant << " */";
+ "nop\t/* variant = "
+ << Variant << " */";
}
template <typename TraitsType>
@@ -2599,16 +2617,20 @@
// stack slot. Function prolog emission guarantees that there is sufficient
// space to do this.
Str << "\t"
- "mov" << Traits::TypeAttributes[Ty].SdSsString << "\t";
+ "mov"
+ << Traits::TypeAttributes[Ty].SdSsString << "\t";
Var->emit(Func);
Str << ", (%esp)\n"
"\t"
- "fld" << this->getFldString(Ty) << "\t"
- "(%esp)";
+ "fld"
+ << this->getFldString(Ty)
+ << "\t"
+ "(%esp)";
return;
}
Str << "\t"
- "fld" << this->getFldString(Ty) << "\t";
+ "fld"
+ << this->getFldString(Ty) << "\t";
this->getSrc(0)->emit(Func);
}
@@ -2669,7 +2691,8 @@
Type Ty = this->getDest()->getType();
if (!this->getDest()->hasReg()) {
Str << "\t"
- "fstp" << this->getFldString(Ty) << "\t";
+ "fstp"
+ << this->getFldString(Ty) << "\t";
this->getDest()->emit(Func);
return;
}
@@ -2677,11 +2700,15 @@
// Hack this by using caller-reserved memory at the top of stack, spilling
// st(0) there, and loading it into the xmm register.
Str << "\t"
- "fstp" << this->getFldString(Ty) << "\t"
- "(%esp)\n";
+ "fstp"
+ << this->getFldString(Ty)
+ << "\t"
+ "(%esp)\n";
Str << "\t"
- "mov" << Traits::TypeAttributes[Ty].SdSsString << "\t"
- "(%esp), ";
+ "mov"
+ << Traits::TypeAttributes[Ty].SdSsString
+ << "\t"
+ "(%esp), ";
this->getDest()->emit(Func);
}
@@ -2949,7 +2976,8 @@
return;
Ostream &Str = Func->getContext()->getStrEmit();
Str << "\t"
- "set" << Traits::InstBrAttributes[Condition].DisplayString << "\t";
+ "set"
+ << Traits::InstBrAttributes[Condition].DisplayString << "\t";
this->Dest->emit(Func);
}
@@ -2987,7 +3015,8 @@
"lock";
}
Str << "\t"
- "xadd" << this->getWidthString(this->getSrc(0)->getType()) << "\t";
+ "xadd"
+ << this->getWidthString(this->getSrc(0)->getType()) << "\t";
this->getSrc(1)->emit(Func);
Str << ", ";
this->getSrc(0)->emit(Func);
@@ -3027,7 +3056,8 @@
return;
Ostream &Str = Func->getContext()->getStrEmit();
Str << "\t"
- "xchg" << this->getWidthString(this->getSrc(0)->getType()) << "\t";
+ "xchg"
+ << this->getWidthString(this->getSrc(0)->getType()) << "\t";
this->getSrc(1)->emit(Func);
Str << ", ";
this->getSrc(0)->emit(Func);
diff --git a/third_party/subzero/src/IceIntrinsics.cpp b/third_party/subzero/src/IceIntrinsics.cpp
index 7f8af30..cbf0726 100644
--- a/third_party/subzero/src/IceIntrinsics.cpp
+++ b/third_party/subzero/src/IceIntrinsics.cpp
@@ -41,14 +41,12 @@
const char *IntrinsicName;
} IceIntrinsicsTable[] = {
-#define AtomicCmpxchgInit(Overload, NameSuffix) \
- { \
- { \
- INTRIN(AtomicCmpxchg, SideEffects_T, ReturnsTwice_F, MemoryWrite_T), \
- {Overload, IceType_i32, Overload, Overload, IceType_i32, IceType_i32}, \
- 6 \
- } \
- , "llvm.nacl.atomic.cmpxchg." NameSuffix \
+#define AtomicCmpxchgInit(Overload, NameSuffix) \
+ { \
+ {INTRIN(AtomicCmpxchg, SideEffects_T, ReturnsTwice_F, MemoryWrite_T), \
+ {Overload, IceType_i32, Overload, Overload, IceType_i32, IceType_i32}, \
+ 6}, \
+ "llvm.nacl.atomic.cmpxchg." NameSuffix \
}
AtomicCmpxchgInit(IceType_i8, "i8"),
AtomicCmpxchgInit(IceType_i16, "i16"),
@@ -71,11 +69,10 @@
#define AtomicLoadInit(Overload, NameSuffix) \
{ \
- { \
- INTRIN(AtomicLoad, SideEffects_T, ReturnsTwice_F, MemoryWrite_T), \
- {Overload, IceType_i32, IceType_i32}, 3 \
- } \
- , "llvm.nacl.atomic.load." NameSuffix \
+ {INTRIN(AtomicLoad, SideEffects_T, ReturnsTwice_F, MemoryWrite_T), \
+ {Overload, IceType_i32, IceType_i32}, \
+ 3}, \
+ "llvm.nacl.atomic.load." NameSuffix \
}
AtomicLoadInit(IceType_i8, "i8"),
AtomicLoadInit(IceType_i16, "i16"),
@@ -85,11 +82,10 @@
#define AtomicRMWInit(Overload, NameSuffix) \
{ \
- { \
- INTRIN(AtomicRMW, SideEffects_T, ReturnsTwice_F, MemoryWrite_T) \
- , {Overload, IceType_i32, IceType_i32, Overload, IceType_i32}, 5 \
- } \
- , "llvm.nacl.atomic.rmw." NameSuffix \
+ {INTRIN(AtomicRMW, SideEffects_T, ReturnsTwice_F, MemoryWrite_T), \
+ {Overload, IceType_i32, IceType_i32, Overload, IceType_i32}, \
+ 5}, \
+ "llvm.nacl.atomic.rmw." NameSuffix \
}
AtomicRMWInit(IceType_i8, "i8"),
AtomicRMWInit(IceType_i16, "i16"),
@@ -99,11 +95,10 @@
#define AtomicStoreInit(Overload, NameSuffix) \
{ \
- { \
- INTRIN(AtomicStore, SideEffects_T, ReturnsTwice_F, MemoryWrite_T) \
- , {IceType_void, Overload, IceType_i32, IceType_i32}, 4 \
- } \
- , "llvm.nacl.atomic.store." NameSuffix \
+ {INTRIN(AtomicStore, SideEffects_T, ReturnsTwice_F, MemoryWrite_T), \
+ {IceType_void, Overload, IceType_i32, IceType_i32}, \
+ 4}, \
+ "llvm.nacl.atomic.store." NameSuffix \
}
AtomicStoreInit(IceType_i8, "i8"),
AtomicStoreInit(IceType_i16, "i16"),
@@ -113,11 +108,10 @@
#define BswapInit(Overload, NameSuffix) \
{ \
- { \
- INTRIN(Bswap, SideEffects_F, ReturnsTwice_F, MemoryWrite_F) \
- , {Overload, Overload}, 2 \
- } \
- , "llvm.bswap." NameSuffix \
+ {INTRIN(Bswap, SideEffects_F, ReturnsTwice_F, MemoryWrite_F), \
+ {Overload, Overload}, \
+ 2}, \
+ "llvm.bswap." NameSuffix \
}
BswapInit(IceType_i16, "i16"),
BswapInit(IceType_i32, "i32"),
@@ -126,11 +120,10 @@
#define CtlzInit(Overload, NameSuffix) \
{ \
- { \
- INTRIN(Ctlz, SideEffects_F, ReturnsTwice_F, MemoryWrite_F) \
- , {Overload, Overload, IceType_i1}, 3 \
- } \
- , "llvm.ctlz." NameSuffix \
+ {INTRIN(Ctlz, SideEffects_F, ReturnsTwice_F, MemoryWrite_F), \
+ {Overload, Overload, IceType_i1}, \
+ 3}, \
+ "llvm.ctlz." NameSuffix \
}
CtlzInit(IceType_i32, "i32"),
CtlzInit(IceType_i64, "i64"),
@@ -138,11 +131,10 @@
#define CtpopInit(Overload, NameSuffix) \
{ \
- { \
- INTRIN(Ctpop, SideEffects_F, ReturnsTwice_F, MemoryWrite_F) \
- , {Overload, Overload}, 2 \
- } \
- , "llvm.ctpop." NameSuffix \
+ {INTRIN(Ctpop, SideEffects_F, ReturnsTwice_F, MemoryWrite_F), \
+ {Overload, Overload}, \
+ 2}, \
+ "llvm.ctpop." NameSuffix \
}
CtpopInit(IceType_i32, "i32"),
CtpopInit(IceType_i64, "i64"),
@@ -150,11 +142,10 @@
#define CttzInit(Overload, NameSuffix) \
{ \
- { \
- INTRIN(Cttz, SideEffects_F, ReturnsTwice_F, MemoryWrite_F) \
- , {Overload, Overload, IceType_i1}, 3 \
- } \
- , "llvm.cttz." NameSuffix \
+ {INTRIN(Cttz, SideEffects_F, ReturnsTwice_F, MemoryWrite_F), \
+ {Overload, Overload, IceType_i1}, \
+ 3}, \
+ "llvm.cttz." NameSuffix \
}
CttzInit(IceType_i32, "i32"),
CttzInit(IceType_i64, "i64"),
@@ -162,11 +153,10 @@
#define FabsInit(Overload, NameSuffix) \
{ \
- { \
- INTRIN(Fabs, SideEffects_F, ReturnsTwice_F, MemoryWrite_F), \
- {Overload, Overload}, 2 \
- } \
- , "llvm.fabs." NameSuffix \
+ {INTRIN(Fabs, SideEffects_F, ReturnsTwice_F, MemoryWrite_F), \
+ {Overload, Overload}, \
+ 2}, \
+ "llvm.fabs." NameSuffix \
}
FabsInit(IceType_f32, "f32"),
FabsInit(IceType_f64, "f64"),
@@ -203,11 +193,10 @@
#define SqrtInit(Overload, NameSuffix) \
{ \
- { \
- INTRIN(Sqrt, SideEffects_F, ReturnsTwice_F, MemoryWrite_F), \
- {Overload, Overload}, 2 \
- } \
- , "llvm.sqrt." NameSuffix \
+ {INTRIN(Sqrt, SideEffects_F, ReturnsTwice_F, MemoryWrite_F), \
+ {Overload, Overload}, \
+ 2}, \
+ "llvm.sqrt." NameSuffix \
}
SqrtInit(IceType_f32, "f32"),
SqrtInit(IceType_f64, "f64"),
diff --git a/third_party/subzero/src/IceLiveness.h b/third_party/subzero/src/IceLiveness.h
index 634bc35..8f1ba78 100644
--- a/third_party/subzero/src/IceLiveness.h
+++ b/third_party/subzero/src/IceLiveness.h
@@ -21,9 +21,9 @@
#ifndef SUBZERO_SRC_ICELIVENESS_H
#define SUBZERO_SRC_ICELIVENESS_H
-#include "IceDefs.h"
#include "IceBitVector.h"
#include "IceCfgNode.h"
+#include "IceDefs.h"
#include "IceTLS.h"
#include "IceTypes.h"
@@ -114,8 +114,9 @@
static void TlsInit() { LivenessAllocatorTraits::init(); }
std::string dumpStr() const {
- return "MaxLocals(" + std::to_string(MaxLocals) + "), "
- "NumGlobals(" +
+ return "MaxLocals(" + std::to_string(MaxLocals) +
+ "), "
+ "NumGlobals(" +
std::to_string(NumGlobals) + ")";
}
diff --git a/third_party/subzero/src/IceMangling.cpp b/third_party/subzero/src/IceMangling.cpp
index fe46bb1..7068fc3 100644
--- a/third_party/subzero/src/IceMangling.cpp
+++ b/third_party/subzero/src/IceMangling.cpp
@@ -12,9 +12,9 @@
///
//===----------------------------------------------------------------------===//
+#include "IceMangling.h"
#include "IceDefs.h"
#include "IceGlobalContext.h"
-#include "IceMangling.h"
#include <cctype> // isdigit(), isupper()
#include <locale> // locale
diff --git a/third_party/subzero/src/IceMemory.h b/third_party/subzero/src/IceMemory.h
index fc19d7a..6fea9dd 100644
--- a/third_party/subzero/src/IceMemory.h
+++ b/third_party/subzero/src/IceMemory.h
@@ -64,8 +64,7 @@
sz_allocator() : Current() {}
template <class U>
- sz_allocator(const sz_allocator<U, Traits> &)
- : Current() {}
+ sz_allocator(const sz_allocator<U, Traits> &) : Current() {}
pointer address(reference x) const {
return reinterpret_cast<pointer>(&reinterpret_cast<char &>(x));
diff --git a/third_party/subzero/src/IceOperand.cpp b/third_party/subzero/src/IceOperand.cpp
index d5ec6dd..1e98324 100644
--- a/third_party/subzero/src/IceOperand.cpp
+++ b/third_party/subzero/src/IceOperand.cpp
@@ -617,7 +617,7 @@
Str << EmitString;
return;
}
- Str << "@" << (Name.hasStdString() ? Name.toString() : "<Unnamed>") ;
+ Str << "@" << (Name.hasStdString() ? Name.toString() : "<Unnamed>");
const RelocOffsetT Offset = getOffset();
if (Offset) {
if (Offset >= 0) {
diff --git a/third_party/subzero/src/IceOperand.h b/third_party/subzero/src/IceOperand.h
index 5501f47..ae65523 100644
--- a/third_party/subzero/src/IceOperand.h
+++ b/third_party/subzero/src/IceOperand.h
@@ -19,8 +19,8 @@
#ifndef SUBZERO_SRC_ICEOPERAND_H
#define SUBZERO_SRC_ICEOPERAND_H
-#include "IceDefs.h"
#include "IceCfg.h"
+#include "IceDefs.h"
#include "IceGlobalContext.h"
#include "IceStringPool.h"
#include "IceTypes.h"
@@ -106,8 +106,8 @@
return 0;
}
- inline void* getExternalData() const { return externalData; }
- inline void setExternalData(void* data) { externalData = data; }
+ inline void *getExternalData() const { return externalData; }
+ inline void setExternalData(void *data) { externalData = data; }
protected:
Operand(OperandKind Kind, Type Ty) : Ty(Ty), Kind(Kind) {
@@ -124,7 +124,7 @@
/// External data can be set by an optimizer to compute and retain any
/// information related to the current operand. All the memory used to
/// store this information must be managed by the optimizer.
- void* externalData = nullptr;
+ void *externalData = nullptr;
};
template <class StreamType>
@@ -862,8 +862,8 @@
SizeT hashValue() const override { return std::hash<SizeT>()(getIndex()); }
- inline void* getExternalData() const { return externalData; }
- inline void setExternalData(void* data) { externalData = data; }
+ inline void *getExternalData() const { return externalData; }
+ inline void setExternalData(void *data) { externalData = data; }
protected:
Variable(const Cfg *Func, OperandKind K, Type Ty, SizeT Index)
@@ -909,7 +909,7 @@
/// External data can be set by an optimizer to compute and retain any
/// information related to the current variable. All the memory used to
/// store this information must be managed by the optimizer.
- void* externalData = nullptr;
+ void *externalData = nullptr;
};
// Variable64On32 represents a 64-bit variable on a 32-bit architecture. In
diff --git a/third_party/subzero/src/IceRNG.cpp b/third_party/subzero/src/IceRNG.cpp
index 3744a53..a623f0a 100644
--- a/third_party/subzero/src/IceRNG.cpp
+++ b/third_party/subzero/src/IceRNG.cpp
@@ -38,9 +38,10 @@
constexpr unsigned NumBitsPassID = 4;
constexpr unsigned NumBitsSalt = 12;
static_assert(RPE_num < (1 << NumBitsPassID), "NumBitsPassID too small");
- State = Seed ^ ((uint64_t)RandomizationPassID
- << (NumBitsGlobalSeed - NumBitsPassID)) ^
- (Salt << (NumBitsGlobalSeed - NumBitsPassID - NumBitsSalt));
+ State =
+ Seed ^
+ ((uint64_t)RandomizationPassID << (NumBitsGlobalSeed - NumBitsPassID)) ^
+ (Salt << (NumBitsGlobalSeed - NumBitsPassID - NumBitsSalt));
}
uint64_t RandomNumberGenerator::next(uint64_t Max) {
// Lewis, Goodman, and Miller (1969)
diff --git a/third_party/subzero/src/IceRNG.h b/third_party/subzero/src/IceRNG.h
index 15a3dee..354337c 100644
--- a/third_party/subzero/src/IceRNG.h
+++ b/third_party/subzero/src/IceRNG.h
@@ -15,9 +15,9 @@
#ifndef SUBZERO_SRC_ICERNG_H
#define SUBZERO_SRC_ICERNG_H
+#include "IceDefs.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/Support/Compiler.h"
-#include "IceDefs.h"
#include <cstdint>
diff --git a/third_party/subzero/src/IceRegAlloc.h b/third_party/subzero/src/IceRegAlloc.h
index 0fd523a..896e178 100644
--- a/third_party/subzero/src/IceRegAlloc.h
+++ b/third_party/subzero/src/IceRegAlloc.h
@@ -18,8 +18,8 @@
#ifndef SUBZERO_SRC_ICEREGALLOC_H
#define SUBZERO_SRC_ICEREGALLOC_H
-#include "IceDefs.h"
#include "IceBitVector.h"
+#include "IceDefs.h"
#include "IceOperand.h"
#include "IceTypes.h"
diff --git a/third_party/subzero/src/IceTargetLowering.cpp b/third_party/subzero/src/IceTargetLowering.cpp
index 3d8537d..7cb476b 100644
--- a/third_party/subzero/src/IceTargetLowering.cpp
+++ b/third_party/subzero/src/IceTargetLowering.cpp
@@ -567,7 +567,7 @@
// instructions.
return Result;
}
-}
+} // namespace
void TargetLowering::postRegallocSplitting(const SmallBitVector &RegMask) {
// Splits the live ranges of global(/multi block) variables and runs the
@@ -955,9 +955,11 @@
Variable *Dest, Operand *Src0,
Operand *Src1) {
scalarizeInstruction(
- Dest, [this, Kind](Variable *Dest, Operand *Src0, Operand *Src1) {
+ Dest,
+ [this, Kind](Variable *Dest, Operand *Src0, Operand *Src1) {
return Context.insert<InstArithmetic>(Kind, Dest, Src0, Src1);
- }, Src0, Src1);
+ },
+ Src0, Src1);
}
void TargetLowering::emitWithoutPrefix(const ConstantRelocatable *C,
diff --git a/third_party/subzero/src/IceTargetLoweringARM32.cpp b/third_party/subzero/src/IceTargetLoweringARM32.cpp
index bf0a5ce..d290e15 100644
--- a/third_party/subzero/src/IceTargetLoweringARM32.cpp
+++ b/third_party/subzero/src/IceTargetLoweringARM32.cpp
@@ -87,8 +87,7 @@
public:
constexpr SizeOf() : Size(0) {}
template <typename... T>
- explicit constexpr SizeOf(T...)
- : Size(__length<T...>::value) {}
+ explicit constexpr SizeOf(T...) : Size(__length<T...>::value) {}
constexpr SizeT size() const { return Size; }
private:
@@ -109,12 +108,14 @@
RegARM32::RegTableType RegARM32::RegTable[RegARM32::Reg_NUM] = {
#define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr, \
isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init) \
- { \
- name, encode, cc_arg, scratch, preserved, stackptr, frameptr, isGPR, \
- isInt, isI64Pair, isFP32, isFP64, isVec128, \
- (SizeOf alias_init).size(), alias_init \
- } \
- ,
+ {name, encode, \
+ cc_arg, scratch, \
+ preserved, stackptr, \
+ frameptr, isGPR, \
+ isInt, isI64Pair, \
+ isFP32, isFP64, \
+ isVec128, (SizeOf alias_init).size(), \
+ alias_init},
REGARM32_TABLE
#undef X
};
@@ -129,8 +130,7 @@
CondARM32::Cond Mapping;
} TableIcmp32[] = {
#define X(val, is_signed, swapped64, C_32, C1_64, C2_64, C_V, INV_V, NEG_V) \
- { CondARM32::C_32 } \
- ,
+ {CondARM32::C_32},
ICMPARM32_TABLE
#undef X
};
@@ -145,8 +145,7 @@
CondARM32::Cond C1, C2;
} TableIcmp64[] = {
#define X(val, is_signed, swapped64, C_32, C1_64, C2_64, C_V, INV_V, NEG_V) \
- { is_signed, swapped64, CondARM32::C1_64, CondARM32::C2_64 } \
- ,
+ {is_signed, swapped64, CondARM32::C1_64, CondARM32::C2_64},
ICMPARM32_TABLE
#undef X
};
@@ -371,23 +370,23 @@
for (size_t i = 0; i < llvm::array_lengthof(TypeToRegisterSet); ++i)
TypeToRegisterSetUnfiltered[i] = TypeToRegisterSet[i];
- filterTypeToRegisterSet(Ctx, RegARM32::Reg_NUM, TypeToRegisterSet,
- llvm::array_lengthof(TypeToRegisterSet),
- [](RegNumT RegNum) -> std::string {
- // This function simply removes ", " from the
- // register name.
- std::string Name = RegARM32::getRegName(RegNum);
- constexpr const char RegSeparator[] = ", ";
- constexpr size_t RegSeparatorWidth =
- llvm::array_lengthof(RegSeparator) - 1;
- for (size_t Pos = Name.find(RegSeparator);
- Pos != std::string::npos;
- Pos = Name.find(RegSeparator)) {
- Name.replace(Pos, RegSeparatorWidth, "");
- }
- return Name;
- },
- getRegClassName);
+ filterTypeToRegisterSet(
+ Ctx, RegARM32::Reg_NUM, TypeToRegisterSet,
+ llvm::array_lengthof(TypeToRegisterSet),
+ [](RegNumT RegNum) -> std::string {
+ // This function simply removes ", " from the
+ // register name.
+ std::string Name = RegARM32::getRegName(RegNum);
+ constexpr const char RegSeparator[] = ", ";
+ constexpr size_t RegSeparatorWidth =
+ llvm::array_lengthof(RegSeparator) - 1;
+ for (size_t Pos = Name.find(RegSeparator); Pos != std::string::npos;
+ Pos = Name.find(RegSeparator)) {
+ Name.replace(Pos, RegSeparatorWidth, "");
+ }
+ return Name;
+ },
+ getRegClassName);
}
namespace {
@@ -1376,7 +1375,9 @@
Arg->setIsArg(false);
Args[I] = RegisterArg;
switch (Ty) {
- default: { RegisterArg->setRegNum(RegNum); } break;
+ default: {
+ RegisterArg->setRegNum(RegNum);
+ } break;
case IceType_i64: {
auto *RegisterArg64 = llvm::cast<Variable64On32>(RegisterArg);
RegisterArg64->initHiLo(Func);
@@ -1878,9 +1879,9 @@
assert(!SrcR->isRematerializable());
const int32_t Offset = Dest->getStackOffset();
// This is a _mov(Mem(), Variable), i.e., a store.
- TargetARM32::Sandboxer(Target)
- .str(SrcR, createMemOperand(DestTy, StackOrFrameReg, Offset),
- MovInstr->getPredicate());
+ TargetARM32::Sandboxer(Target).str(
+ SrcR, createMemOperand(DestTy, StackOrFrameReg, Offset),
+ MovInstr->getPredicate());
// _str() does not have a Dest, so we add a fake-def(Dest).
Target->Context.insert<InstFakeDef>(Dest);
Legalized = true;
@@ -1903,9 +1904,9 @@
if (!Var->hasReg()) {
// This is a _mov(Variable, Mem()), i.e., a load.
const int32_t Offset = Var->getStackOffset();
- TargetARM32::Sandboxer(Target)
- .ldr(Dest, createMemOperand(DestTy, StackOrFrameReg, Offset),
- MovInstr->getPredicate());
+ TargetARM32::Sandboxer(Target).ldr(
+ Dest, createMemOperand(DestTy, StackOrFrameReg, Offset),
+ MovInstr->getPredicate());
Legalized = true;
}
}
@@ -1942,8 +1943,12 @@
} MemTraits[] = {
#define X(tag, elementty, int_width, fp_width, uvec_width, svec_width, sbits, \
ubits, rraddr, shaddr) \
- { (1 << ubits) - 1, (ubits) > 0, rraddr, shaddr, } \
- ,
+ { \
+ (1 << ubits) - 1, \
+ (ubits) > 0, \
+ rraddr, \
+ shaddr, \
+ },
ICETYPEARM32_TABLE
#undef X
};
@@ -1954,9 +1959,8 @@
TargetARM32::PostLoweringLegalizer::legalizeMemOperand(OperandARM32Mem *Mem,
bool AllowOffsets) {
assert(!Mem->isRegReg() || !Mem->getIndex()->isRematerializable());
- assert(
- Mem->isRegReg() ||
- Target->isLegalMemOffset(Mem->getType(), Mem->getOffset()->getValue()));
+ assert(Mem->isRegReg() || Target->isLegalMemOffset(
+ Mem->getType(), Mem->getOffset()->getValue()));
bool Legalized = false;
Variable *Base = Mem->getBase();
@@ -2054,8 +2058,8 @@
} else if (auto *LdrInstr = llvm::dyn_cast<InstARM32Ldr>(CurInstr)) {
if (OperandARM32Mem *LegalMem = Legalizer.legalizeMemOperand(
llvm::cast<OperandARM32Mem>(LdrInstr->getSrc(0)))) {
- Sandboxer(this)
- .ldr(CurInstr->getDest(), LegalMem, LdrInstr->getPredicate());
+ Sandboxer(this).ldr(CurInstr->getDest(), LegalMem,
+ LdrInstr->getPredicate());
CurInstr->setDeleted();
}
} else if (auto *LdrexInstr = llvm::dyn_cast<InstARM32Ldrex>(CurInstr)) {
@@ -2063,8 +2067,8 @@
if (OperandARM32Mem *LegalMem = Legalizer.legalizeMemOperand(
llvm::cast<OperandARM32Mem>(LdrexInstr->getSrc(0)),
DisallowOffsetsBecauseLdrex)) {
- Sandboxer(this)
- .ldrex(CurInstr->getDest(), LegalMem, LdrexInstr->getPredicate());
+ Sandboxer(this).ldrex(CurInstr->getDest(), LegalMem,
+ LdrexInstr->getPredicate());
CurInstr->setDeleted();
}
} else if (auto *StrInstr = llvm::dyn_cast<InstARM32Str>(CurInstr)) {
@@ -2783,8 +2787,9 @@
Variable *Src1RLo = SrcsLo.unswappedSrc1R(this);
_rsb(T0, Src1RLo, _32);
_lsr(T1, Src0RLo, T0);
- _orr(TA_Hi, T1, OperandARM32FlexReg::create(Func, IceType_i32, Src0RHi,
- OperandARM32::LSL, Src1RLo));
+ _orr(TA_Hi, T1,
+ OperandARM32FlexReg::create(Func, IceType_i32, Src0RHi,
+ OperandARM32::LSL, Src1RLo));
_sub(T2, Src1RLo, _32);
_cmp(T2, _0);
_lsl(TA_Hi, Src0RLo, T2, CondARM32::GE);
@@ -2889,8 +2894,9 @@
Variable *Src1RLo = SrcsLo.unswappedSrc1R(this);
_lsr(T0, Src0RLo, Src1RLo);
_rsb(T1, Src1RLo, _32);
- _orr(TA_Lo, T0, OperandARM32FlexReg::create(Func, IceType_i32, Src0RHi,
- OperandARM32::LSL, T1));
+ _orr(TA_Lo, T0,
+ OperandARM32FlexReg::create(Func, IceType_i32, Src0RHi,
+ OperandARM32::LSL, T1));
_sub(T2, Src1RLo, _32);
_cmp(T2, _0);
if (ASR) {
@@ -3058,8 +3064,9 @@
const uint32_t NegSrcLastBitSet = llvm::findLastSet(NegSrc);
assert(NegSrcLastBitSet < SrcLastBitSet);
const uint32_t SrcClearMask =
- (NegSrcLastBitSet == 0) ? 0 : (0xFFFFFFFFu) >>
- (SrcSizeBits - NegSrcLastBitSet);
+ (NegSrcLastBitSet == 0)
+ ? 0
+ : (0xFFFFFFFFu) >> (SrcSizeBits - NegSrcLastBitSet);
Src &= SrcClearMask;
if (!addOperations(SrcLastBitSet, NegSrcLastBitSet + 1, NumOperations,
Operations)) {
@@ -4125,9 +4132,9 @@
// t3.fp = vcvt.{fp}.s32 @ fp is either f32 or f64
if (Src0->getType() != IceType_i32) {
Variable *Src0R_32 = makeReg(IceType_i32);
- lowerCast(InstCast::create(Func, SourceIsSigned ? InstCast::Sext
- : InstCast::Zext,
- Src0R_32, Src0));
+ lowerCast(InstCast::create(
+ Func, SourceIsSigned ? InstCast::Sext : InstCast::Zext, Src0R_32,
+ Src0));
Src0 = Src0R_32;
}
Variable *Src0R = legalizeToReg(Src0);
@@ -4289,8 +4296,7 @@
CondARM32::Cond CC1;
} TableFcmp[] = {
#define X(val, CC0, CC1, CC0_V, CC1_V, INV_V, NEG_V) \
- { CondARM32::CC0, CondARM32::CC1 } \
- ,
+ {CondARM32::CC0, CondARM32::CC1},
FCMPARM32_TABLE
#undef X
};
@@ -4755,11 +4761,11 @@
llvm::report_fatal_error("Unhandled integer comparison.");
#define _Vceq(T, S0, S1, Signed) _vceq(T, S0, S1)
#define _Vcge(T, S0, S1, Signed) \
- _vcge(T, S0, S1) \
- ->setSignType(Signed ? InstARM32::FS_Signed : InstARM32::FS_Unsigned)
+ _vcge(T, S0, S1)->setSignType(Signed ? InstARM32::FS_Signed \
+ : InstARM32::FS_Unsigned)
#define _Vcgt(T, S0, S1, Signed) \
- _vcgt(T, S0, S1) \
- ->setSignType(Signed ? InstARM32::FS_Signed : InstARM32::FS_Unsigned)
+ _vcgt(T, S0, S1)->setSignType(Signed ? InstARM32::FS_Signed \
+ : InstARM32::FS_Unsigned)
#define X(val, is_signed, swapped64, C_32, C1_64, C2_64, C_V, INV_V, NEG_V) \
case InstIcmp::val: { \
_Vc##C_V(T, (INV_V) ? Src1 : Src0, (INV_V) ? Src0 : Src1, is_signed); \
@@ -5191,8 +5197,9 @@
return;
}
lowerAtomicRMW(
- Dest, static_cast<uint32_t>(
- llvm::cast<ConstantInteger32>(Instr->getArg(0))->getValue()),
+ Dest,
+ static_cast<uint32_t>(
+ llvm::cast<ConstantInteger32>(Instr->getArg(0))->getValue()),
Instr->getArg(1), Instr->getArg(2));
return;
}
@@ -6996,7 +7003,7 @@
}
}
}
-} // end of namespace FpFolding
+} // namespace IntFolding
} // end of anonymous namespace
void TargetARM32::ComputationTracker::recordProducers(CfgNode *Node) {
diff --git a/third_party/subzero/src/IceTargetLoweringMIPS32.cpp b/third_party/subzero/src/IceTargetLoweringMIPS32.cpp
index ccf5659..cd082cd 100644
--- a/third_party/subzero/src/IceTargetLoweringMIPS32.cpp
+++ b/third_party/subzero/src/IceTargetLoweringMIPS32.cpp
@@ -260,7 +260,7 @@
return Integer->getValue();
return Intrinsics::MemoryOrderInvalid;
}
-}
+} // namespace
void TargetMIPS32::genTargetHelperCallFor(Inst *Instr) {
constexpr bool NoTailCall = false;
@@ -1398,7 +1398,9 @@
}
} else {
switch (Ty) {
- default: { RegisterArg->setRegNum(RegNum); } break;
+ default: {
+ RegisterArg->setRegNum(RegNum);
+ } break;
case IceType_i64: {
auto *RegisterArg64 = llvm::cast<Variable64On32>(RegisterArg);
RegisterArg64->initHiLo(Func);
diff --git a/third_party/subzero/src/IceTargetLoweringX8632.cpp b/third_party/subzero/src/IceTargetLoweringX8632.cpp
index 4a14825..904d1ce 100644
--- a/third_party/subzero/src/IceTargetLoweringX8632.cpp
+++ b/third_party/subzero/src/IceTargetLoweringX8632.cpp
@@ -72,11 +72,12 @@
//------------------------------------------------------------------------------
const TargetX8632Traits::TableFcmpType TargetX8632Traits::TableFcmp[] = {
#define X(val, dflt, swapS, C1, C2, swapV, pred) \
- { \
- dflt, swapS, X8632::Traits::Cond::C1, X8632::Traits::Cond::C2, swapV, \
- X8632::Traits::Cond::pred \
- } \
- ,
+ {dflt, \
+ swapS, \
+ X8632::Traits::Cond::C1, \
+ X8632::Traits::Cond::C2, \
+ swapV, \
+ X8632::Traits::Cond::pred},
FCMPX8632_TABLE
#undef X
};
@@ -84,9 +85,7 @@
const size_t TargetX8632Traits::TableFcmpSize = llvm::array_lengthof(TableFcmp);
const TargetX8632Traits::TableIcmp32Type TargetX8632Traits::TableIcmp32[] = {
-#define X(val, C_32, C1_64, C2_64, C3_64) \
- { X8632::Traits::Cond::C_32 } \
- ,
+#define X(val, C_32, C1_64, C2_64, C3_64) {X8632::Traits::Cond::C_32},
ICMPX8632_TABLE
#undef X
};
@@ -96,11 +95,8 @@
const TargetX8632Traits::TableIcmp64Type TargetX8632Traits::TableIcmp64[] = {
#define X(val, C_32, C1_64, C2_64, C3_64) \
- { \
- X8632::Traits::Cond::C1_64, X8632::Traits::Cond::C2_64, \
- X8632::Traits::Cond::C3_64 \
- } \
- ,
+ {X8632::Traits::Cond::C1_64, X8632::Traits::Cond::C2_64, \
+ X8632::Traits::Cond::C3_64},
ICMPX8632_TABLE
#undef X
};
@@ -111,8 +107,7 @@
const TargetX8632Traits::TableTypeX8632AttributesType
TargetX8632Traits::TableTypeX8632Attributes[] = {
#define X(tag, elty, cvt, sdss, pdps, spsd, int_, unpack, pack, width, fld) \
- { IceType_##elty } \
- ,
+ {IceType_##elty},
ICETYPEX8632_TABLE
#undef X
};
diff --git a/third_party/subzero/src/IceTargetLoweringX8632.h b/third_party/subzero/src/IceTargetLoweringX8632.h
index d712d6b..4234384 100644
--- a/third_party/subzero/src/IceTargetLoweringX8632.h
+++ b/third_party/subzero/src/IceTargetLoweringX8632.h
@@ -18,9 +18,9 @@
#include "IceAssemblerX8632.h"
#include "IceDefs.h"
+#include "IceInstX8632.h"
#include "IceRegistersX8632.h"
#include "IceTargetLowering.h"
-#include "IceInstX8632.h"
#define X86NAMESPACE X8632
#include "IceTargetLoweringX86Base.h"
#undef X86NAMESPACE
diff --git a/third_party/subzero/src/IceTargetLoweringX8632Traits.h b/third_party/subzero/src/IceTargetLoweringX8632Traits.h
index 09e449c..2f7de46 100644
--- a/third_party/subzero/src/IceTargetLoweringX8632Traits.h
+++ b/third_party/subzero/src/IceTargetLoweringX8632Traits.h
@@ -173,8 +173,7 @@
bool IsRegister(GPRRegister reg) const {
return ((encoding_[0] & 0xF8) ==
0xC0) // Addressing mode is register only.
- &&
- ((encoding_[0] & 0x07) == reg); // Register codes match.
+ && ((encoding_[0] & 0x07) == reg); // Register codes match.
}
friend class AssemblerX86Base<TargetX8632Traits>;
@@ -323,7 +322,7 @@
isGPR, is64, is32, is16, is8, isXmm, is64To8, is32To8, is16To8, \
isTrunc8Rcvr, isAhRcvr, aliases) \
isXmm,
- REGX8632_TABLE
+ REGX8632_TABLE
#undef X
};
return IsXmm[RegNum];
@@ -446,8 +445,7 @@
public:
constexpr SizeOf() : Size(0) {}
template <typename... T>
- explicit constexpr SizeOf(T...)
- : Size(__length<T...>::value) {}
+ explicit constexpr SizeOf(T...) : Size(__length<T...>::value) {}
constexpr SizeT size() const { return Size; }
private:
@@ -500,10 +498,20 @@
isGPR, is64, is32, is16, is8, isXmm, is64To8, is32To8, is16To8, \
isTrunc8Rcvr, isAhRcvr, aliases) \
{ \
- RegisterSet::val, is64, is32, is16, is8, isXmm, is64To8, is32To8, is16To8, \
- isTrunc8Rcvr, isAhRcvr, (SizeOf aliases).size(), aliases, \
- } \
- ,
+ RegisterSet::val, \
+ is64, \
+ is32, \
+ is16, \
+ is8, \
+ isXmm, \
+ is64To8, \
+ is32To8, \
+ is16To8, \
+ isTrunc8Rcvr, \
+ isAhRcvr, \
+ (SizeOf aliases).size(), \
+ aliases, \
+ },
REGX8632_TABLE
#undef X
};
diff --git a/third_party/subzero/src/IceTargetLoweringX8664.cpp b/third_party/subzero/src/IceTargetLoweringX8664.cpp
index a4cf854..e7407b1 100644
--- a/third_party/subzero/src/IceTargetLoweringX8664.cpp
+++ b/third_party/subzero/src/IceTargetLoweringX8664.cpp
@@ -64,11 +64,12 @@
//------------------------------------------------------------------------------
const TargetX8664Traits::TableFcmpType TargetX8664Traits::TableFcmp[] = {
#define X(val, dflt, swapS, C1, C2, swapV, pred) \
- { \
- dflt, swapS, X8664::Traits::Cond::C1, X8664::Traits::Cond::C2, swapV, \
- X8664::Traits::Cond::pred \
- } \
- ,
+ {dflt, \
+ swapS, \
+ X8664::Traits::Cond::C1, \
+ X8664::Traits::Cond::C2, \
+ swapV, \
+ X8664::Traits::Cond::pred},
FCMPX8664_TABLE
#undef X
};
@@ -76,9 +77,7 @@
const size_t TargetX8664Traits::TableFcmpSize = llvm::array_lengthof(TableFcmp);
const TargetX8664Traits::TableIcmp32Type TargetX8664Traits::TableIcmp32[] = {
-#define X(val, C_32, C1_64, C2_64, C3_64) \
- { X8664::Traits::Cond::C_32 } \
- ,
+#define X(val, C_32, C1_64, C2_64, C3_64) {X8664::Traits::Cond::C_32},
ICMPX8664_TABLE
#undef X
};
@@ -88,11 +87,8 @@
const TargetX8664Traits::TableIcmp64Type TargetX8664Traits::TableIcmp64[] = {
#define X(val, C_32, C1_64, C2_64, C3_64) \
- { \
- X8664::Traits::Cond::C1_64, X8664::Traits::Cond::C2_64, \
- X8664::Traits::Cond::C3_64 \
- } \
- ,
+ {X8664::Traits::Cond::C1_64, X8664::Traits::Cond::C2_64, \
+ X8664::Traits::Cond::C3_64},
ICMPX8664_TABLE
#undef X
};
@@ -103,8 +99,7 @@
const TargetX8664Traits::TableTypeX8664AttributesType
TargetX8664Traits::TableTypeX8664Attributes[] = {
#define X(tag, elty, cvt, sdss, pdps, spsd, int_, unpack, pack, width, fld) \
- { IceType_##elty } \
- ,
+ {IceType_##elty},
ICETYPEX8664_TABLE
#undef X
};
@@ -298,12 +293,14 @@
void TargetX8664::_push_reg(RegNumT RegNum) {
if (Traits::isXmm(RegNum)) {
- Variable *reg =
- getPhysicalRegister(RegNum, IceType_v4f32);
+ Variable *reg = getPhysicalRegister(RegNum, IceType_v4f32);
Variable *rsp =
getPhysicalRegister(Traits::RegisterSet::Reg_rsp, Traits::WordType);
- auto* address = Traits::X86OperandMem::create(Func, reg->getType(), rsp, nullptr);
- _sub_sp(Ctx->getConstantInt32(16)); // TODO(capn): accumulate all the offsets and adjust the stack pointer once.
+ auto *address =
+ Traits::X86OperandMem::create(Func, reg->getType(), rsp, nullptr);
+ _sub_sp(
+ Ctx->getConstantInt32(16)); // TODO(capn): accumulate all the offsets
+ // and adjust the stack pointer once.
_storep(reg, address);
} else if (RegNum != Traits::RegisterSet::Reg_rbp || !NeedSandboxing) {
_push(getPhysicalRegister(RegNum, Traits::WordType));
@@ -314,13 +311,15 @@
void TargetX8664::_pop_reg(RegNumT RegNum) {
if (Traits::isXmm(RegNum)) {
- Variable *reg =
- getPhysicalRegister(RegNum, IceType_v4f32);
+ Variable *reg = getPhysicalRegister(RegNum, IceType_v4f32);
Variable *rsp =
getPhysicalRegister(Traits::RegisterSet::Reg_rsp, Traits::WordType);
- auto* address = Traits::X86OperandMem::create(Func, reg->getType(), rsp, nullptr);
+ auto *address =
+ Traits::X86OperandMem::create(Func, reg->getType(), rsp, nullptr);
_movp(reg, address);
- _add_sp(Ctx->getConstantInt32(16)); // TODO(capn): accumulate all the offsets and adjust the stack pointer once.
+ _add_sp(
+ Ctx->getConstantInt32(16)); // TODO(capn): accumulate all the offsets
+ // and adjust the stack pointer once.
} else {
_pop(getPhysicalRegister(RegNum, Traits::WordType));
}
diff --git a/third_party/subzero/src/IceTargetLoweringX8664Traits.h b/third_party/subzero/src/IceTargetLoweringX8664Traits.h
index 7eea684..b8278f6 100644
--- a/third_party/subzero/src/IceTargetLoweringX8664Traits.h
+++ b/third_party/subzero/src/IceTargetLoweringX8664Traits.h
@@ -179,9 +179,8 @@
/// disguise. Used from the assembler to generate better encodings.
bool IsRegister(GPRRegister reg) const {
return ((encoding_[0] & 0xF8) ==
- 0xC0) // Addressing mode is register only.
- &&
- (rm() == reg); // Register codes match.
+ 0xC0) // Addressing mode is register only.
+ && (rm() == reg); // Register codes match.
}
friend class AssemblerX86Base<TargetX8664Traits>;
@@ -343,11 +342,11 @@
}
static bool isXmm(RegNumT RegNum) {
- static const bool IsXmm [RegisterSet::Reg_NUM] = {
+ static const bool IsXmm[RegisterSet::Reg_NUM] = {
#define X(val, encode, name, base, scratch, preserved, stackptr, frameptr, \
sboxres, isGPR, is64, is32, is16, is8, isXmm, is64To8, is32To8, \
is16To8, isTrunc8Rcvr, isAhRcvr, aliases) \
- isXmm,
+ isXmm,
REGX8664_TABLE
#undef X
};
@@ -474,8 +473,7 @@
public:
constexpr SizeOf() : Size(0) {}
template <typename... T>
- explicit constexpr SizeOf(T...)
- : Size(length<T...>::value) {}
+ explicit constexpr SizeOf(T...) : Size(length<T...>::value) {}
constexpr SizeT size() const { return Size; }
private:
@@ -530,10 +528,21 @@
sboxres, isGPR, is64, is32, is16, is8, isXmm, is64To8, is32To8, \
is16To8, isTrunc8Rcvr, isAhRcvr, aliases) \
{ \
- RegisterSet::val, sboxres, is64, is32, is16, is8, isXmm, is64To8, is32To8, \
- is16To8, isTrunc8Rcvr, isAhRcvr, (SizeOf aliases).size(), aliases, \
- } \
- ,
+ RegisterSet::val, \
+ sboxres, \
+ is64, \
+ is32, \
+ is16, \
+ is8, \
+ isXmm, \
+ is64To8, \
+ is32To8, \
+ is16To8, \
+ isTrunc8Rcvr, \
+ isAhRcvr, \
+ (SizeOf aliases).size(), \
+ aliases, \
+ },
REGX8664_TABLE
#undef X
};
@@ -734,7 +743,9 @@
return RegNumT();
}
static const RegisterSet::AllRegisters GprForArgNum[] = {
- RegisterSet::Reg_rcx, RegisterSet::Reg_rdx, RegisterSet::Reg_r8,
+ RegisterSet::Reg_rcx,
+ RegisterSet::Reg_rdx,
+ RegisterSet::Reg_r8,
RegisterSet::Reg_r9,
};
static_assert(llvm::array_lengthof(GprForArgNum) == X86_MAX_GPR_ARGS,
diff --git a/third_party/subzero/src/IceTargetLoweringX86Base.h b/third_party/subzero/src/IceTargetLoweringX86Base.h
index f4019c6..376d7b2 100644
--- a/third_party/subzero/src/IceTargetLoweringX86Base.h
+++ b/third_party/subzero/src/IceTargetLoweringX86Base.h
@@ -1244,7 +1244,7 @@
private:
ENABLE_MAKE_UNIQUE;
- explicit TargetDataX86(GlobalContext *Ctx) : TargetDataLowering(Ctx){}
+ explicit TargetDataX86(GlobalContext *Ctx) : TargetDataLowering(Ctx) {}
template <typename T> static void emitConstantPool(GlobalContext *Ctx);
};
diff --git a/third_party/subzero/src/IceTargetLoweringX86BaseImpl.h b/third_party/subzero/src/IceTargetLoweringX86BaseImpl.h
index 935a3d8..2b40b66 100644
--- a/third_party/subzero/src/IceTargetLoweringX86BaseImpl.h
+++ b/third_party/subzero/src/IceTargetLoweringX86BaseImpl.h
@@ -615,7 +615,8 @@
// Do not merge Alloca instructions, and lay out the stack.
// static constexpr bool SortAndCombineAllocas = false;
- static constexpr bool SortAndCombineAllocas = true; // TODO(b/171222930): Fix Win32 bug when this is false
+ static constexpr bool SortAndCombineAllocas =
+ true; // TODO(b/171222930): Fix Win32 bug when this is false
Func->processAllocas(SortAndCombineAllocas);
Func->dump("After Alloca processing");
@@ -1134,8 +1135,9 @@
// Generate "push frameptr; mov frameptr, stackptr"
if (IsEbpBasedFrame) {
- assert((RegsUsed & getRegisterSet(RegSet_FramePointer, RegSet_None))
- .count() == 0);
+ assert(
+ (RegsUsed & getRegisterSet(RegSet_FramePointer, RegSet_None)).count() ==
+ 0);
PreservedRegsSizeBytes += typeWidthInBytes(Traits::WordType);
_link_bp();
}
@@ -5881,7 +5883,7 @@
AddressWasOptimized = true;
Reason = nullptr;
SkipLastFolding = nullptr;
- memset(reinterpret_cast<void*>(&Skip), 0, sizeof(Skip));
+ memset(reinterpret_cast<void *>(&Skip), 0, sizeof(Skip));
}
NewAddrCheckpoint = NewAddr;
@@ -7723,7 +7725,8 @@
Variable *Dest = Instr->getDest();
if (Dest != nullptr)
ReturnType = Dest->getType();
- return getShadowStoreSize<Traits>() + getCallStackArgumentsSizeBytes(ArgTypes, ReturnType);
+ return getShadowStoreSize<Traits>() +
+ getCallStackArgumentsSizeBytes(ArgTypes, ReturnType);
}
template <typename TraitsType>
@@ -8495,7 +8498,8 @@
const char *Prefix = UseNonsfi ? ".data.rel.ro." : ".rodata.";
Str << "\t.section\t" << Prefix << JumpTable->getSectionName()
<< ",\"a\",@progbits\n"
- "\t.align\t" << typeWidthInBytes(getPointerType()) << "\n"
+ "\t.align\t"
+ << typeWidthInBytes(getPointerType()) << "\n"
<< JumpTable->getName() << ":";
// On X86 ILP32 pointers are 32-bit hence the use of .long
@@ -8603,7 +8607,8 @@
for (const JumpTableData &JT : Ctx->getJumpTables()) {
Str << "\t.section\t" << Prefix << JT.getSectionName()
<< ",\"a\",@progbits\n"
- "\t.align\t" << typeWidthInBytes(getPointerType()) << "\n"
+ "\t.align\t"
+ << typeWidthInBytes(getPointerType()) << "\n"
<< JT.getName().toString() << ":";
// On X8664 ILP32 pointers are 32-bit hence the use of .long
diff --git a/third_party/subzero/src/IceTimerTree.cpp b/third_party/subzero/src/IceTimerTree.cpp
index 35295ae..d031146 100644
--- a/third_party/subzero/src/IceTimerTree.cpp
+++ b/third_party/subzero/src/IceTimerTree.cpp
@@ -253,7 +253,8 @@
<< I.second << "\n";
} else {
Str << llvm::format(" %10.6f %4.1f%% ", I.first,
- I.first * 100 / TotalTime) << I.second << "\n";
+ I.first * 100 / TotalTime)
+ << I.second << "\n";
}
}
}
@@ -269,8 +270,9 @@
assert(TotalTime);
char PrefixStr[30];
if (DumpCumulative) {
- Str << Name << " - Cumulative times:\n"
- " Seconds Pct EventCnt TimerPath\n";
+ Str << Name
+ << " - Cumulative times:\n"
+ " Seconds Pct EventCnt TimerPath\n";
DumpMapType CumulativeMap;
for (TTindex i = 1; i < Nodes.size(); ++i) {
TTindex Prefix = i;
@@ -290,8 +292,9 @@
constexpr bool NoAddPercents = false;
dumpHelper(Str, CumulativeMap, TotalTime, NoAddPercents);
}
- Str << Name << " - Flat times:\n"
- " Seconds Pct CumPct EventCnt TimerName\n";
+ Str << Name
+ << " - Flat times:\n"
+ " Seconds Pct CumPct EventCnt TimerName\n";
DumpMapType FlatMap;
for (TimerIdT i = 0; i < LeafTimes.size(); ++i) {
if (LeafCounts[i]) {
diff --git a/third_party/subzero/src/IceTranslator.cpp b/third_party/subzero/src/IceTranslator.cpp
index 1211510..e288d29 100644
--- a/third_party/subzero/src/IceTranslator.cpp
+++ b/third_party/subzero/src/IceTranslator.cpp
@@ -14,9 +14,9 @@
#include "IceTranslator.h"
-#include "IceDefs.h"
#include "IceCfg.h"
#include "IceClFlags.h"
+#include "IceDefs.h"
#include "IceGlobalInits.h"
#include "IceTargetLowering.h"
diff --git a/third_party/subzero/src/IceTypeConverter.cpp b/third_party/subzero/src/IceTypeConverter.cpp
index e0c631c..af2e5c3 100644
--- a/third_party/subzero/src/IceTypeConverter.cpp
+++ b/third_party/subzero/src/IceTypeConverter.cpp
@@ -57,4 +57,4 @@
}
}
-} // end of Ice namespace.
+} // namespace Ice
diff --git a/third_party/subzero/src/IceTypes.cpp b/third_party/subzero/src/IceTypes.cpp
index cfa8e50..7c98fdd 100644
--- a/third_party/subzero/src/IceTypes.cpp
+++ b/third_party/subzero/src/IceTypes.cpp
@@ -102,8 +102,7 @@
const struct TypeAttributeFields TypeAttributes[] = {
#define X(tag, sizeLog2, align, elts, elty, str, rcstr) \
- { sizeLog2, align, elts, IceType_##elty, str, rcstr } \
- ,
+ {sizeLog2, align, elts, IceType_##elty, str, rcstr},
ICETYPE_TABLE
#undef X
};
@@ -125,12 +124,9 @@
const TypePropertyFields TypePropertiesTable[] = {
#define X(tag, IsVec, IsInt, IsFloat, IsIntArith, IsBoolean, IsParam, \
CompareResult) \
- { \
- IsVec, IsInt, IsInt & !IsVec, IsInt & IsVec, IsIntArith, IsFloat, \
- IsFloat & !IsVec, IsFloat & IsVec, IsBoolean, IsParam, \
- IceType_##CompareResult \
- } \
- ,
+ {IsVec, IsInt, IsInt & !IsVec, IsInt & IsVec, \
+ IsIntArith, IsFloat, IsFloat & !IsVec, IsFloat & IsVec, \
+ IsBoolean, IsParam, IceType_##CompareResult},
ICETYPE_PROPS_TABLE
#undef X
};
diff --git a/third_party/subzero/src/WasmTranslator.cpp b/third_party/subzero/src/WasmTranslator.cpp
index cb6da00..960a940 100644
--- a/third_party/subzero/src/WasmTranslator.cpp
+++ b/third_party/subzero/src/WasmTranslator.cpp
@@ -54,7 +54,7 @@
using v8::internal::wasm::DecodeWasmModule;
#undef LOG
-#define LOG(Expr) log([&](Ostream & out) { Expr; })
+#define LOG(Expr) log([&](Ostream &out) { Expr; })
namespace {
// 64KB
@@ -1594,8 +1594,9 @@
// Add the data
WasmMemory->addInitializer(VariableDeclaration::DataInitializer::create(
- Globals.get(), reinterpret_cast<const char *>(Module->module_start) +
- Seg.source_offset,
+ Globals.get(),
+ reinterpret_cast<const char *>(Module->module_start) +
+ Seg.source_offset,
Seg.source_size));
WritePtr += Seg.source_size;
diff --git a/third_party/subzero/src/WasmTranslator.h b/third_party/subzero/src/WasmTranslator.h
index dbc594a..8c58ba6 100644
--- a/third_party/subzero/src/WasmTranslator.h
+++ b/third_party/subzero/src/WasmTranslator.h
@@ -72,7 +72,7 @@
private:
std::vector<uint8_t> Buffer;
};
-}
+} // namespace Ice
#endif // ALLOW_WASM
