| /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
| |* *| |
| |* Intrinsic Function Source Fragment *| |
| |* *| |
| |* Automatically generated file, do not edit! *| |
| |* *| |
| \*===----------------------------------------------------------------------===*/ |
| |
| #ifndef LLVM_IR_INTRINSIC_RISCV_ENUMS_H |
| #define LLVM_IR_INTRINSIC_RISCV_ENUMS_H |
| |
| namespace llvm { |
| namespace Intrinsic { |
| enum RISCVIntrinsics : unsigned { |
| // Enum values for intrinsics |
| riscv_masked_atomicrmw_add_i32 = 6039, // llvm.riscv.masked.atomicrmw.add.i32 |
| riscv_masked_atomicrmw_add_i64, // llvm.riscv.masked.atomicrmw.add.i64 |
| riscv_masked_atomicrmw_max_i32, // llvm.riscv.masked.atomicrmw.max.i32 |
| riscv_masked_atomicrmw_max_i64, // llvm.riscv.masked.atomicrmw.max.i64 |
| riscv_masked_atomicrmw_min_i32, // llvm.riscv.masked.atomicrmw.min.i32 |
| riscv_masked_atomicrmw_min_i64, // llvm.riscv.masked.atomicrmw.min.i64 |
| riscv_masked_atomicrmw_nand_i32, // llvm.riscv.masked.atomicrmw.nand.i32 |
| riscv_masked_atomicrmw_nand_i64, // llvm.riscv.masked.atomicrmw.nand.i64 |
| riscv_masked_atomicrmw_sub_i32, // llvm.riscv.masked.atomicrmw.sub.i32 |
| riscv_masked_atomicrmw_sub_i64, // llvm.riscv.masked.atomicrmw.sub.i64 |
| riscv_masked_atomicrmw_umax_i32, // llvm.riscv.masked.atomicrmw.umax.i32 |
| riscv_masked_atomicrmw_umax_i64, // llvm.riscv.masked.atomicrmw.umax.i64 |
| riscv_masked_atomicrmw_umin_i32, // llvm.riscv.masked.atomicrmw.umin.i32 |
| riscv_masked_atomicrmw_umin_i64, // llvm.riscv.masked.atomicrmw.umin.i64 |
| riscv_masked_atomicrmw_xchg_i32, // llvm.riscv.masked.atomicrmw.xchg.i32 |
| riscv_masked_atomicrmw_xchg_i64, // llvm.riscv.masked.atomicrmw.xchg.i64 |
| riscv_masked_cmpxchg_i32, // llvm.riscv.masked.cmpxchg.i32 |
| riscv_masked_cmpxchg_i64, // llvm.riscv.masked.cmpxchg.i64 |
| }; // enum |
| } // namespace Intrinsic |
| } // namespace llvm |
| |
| #endif |
