| /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
| |* *| |
| |* Target Instruction Enum Values and Descriptors *| |
| |* *| |
| |* Automatically generated file, do not edit! *| |
| |* *| |
| \*===----------------------------------------------------------------------===*/ |
| |
| #ifdef GET_INSTRINFO_ENUM |
| #undef GET_INSTRINFO_ENUM |
| namespace llvm { |
| |
| namespace Mips { |
| enum { |
| PHI = 0, |
| INLINEASM = 1, |
| INLINEASM_BR = 2, |
| CFI_INSTRUCTION = 3, |
| EH_LABEL = 4, |
| GC_LABEL = 5, |
| ANNOTATION_LABEL = 6, |
| KILL = 7, |
| EXTRACT_SUBREG = 8, |
| INSERT_SUBREG = 9, |
| IMPLICIT_DEF = 10, |
| SUBREG_TO_REG = 11, |
| COPY_TO_REGCLASS = 12, |
| DBG_VALUE = 13, |
| DBG_VALUE_LIST = 14, |
| DBG_INSTR_REF = 15, |
| DBG_PHI = 16, |
| DBG_LABEL = 17, |
| REG_SEQUENCE = 18, |
| COPY = 19, |
| BUNDLE = 20, |
| LIFETIME_START = 21, |
| LIFETIME_END = 22, |
| PSEUDO_PROBE = 23, |
| ARITH_FENCE = 24, |
| STACKMAP = 25, |
| FENTRY_CALL = 26, |
| PATCHPOINT = 27, |
| LOAD_STACK_GUARD = 28, |
| PREALLOCATED_SETUP = 29, |
| PREALLOCATED_ARG = 30, |
| STATEPOINT = 31, |
| LOCAL_ESCAPE = 32, |
| FAULTING_OP = 33, |
| PATCHABLE_OP = 34, |
| PATCHABLE_FUNCTION_ENTER = 35, |
| PATCHABLE_RET = 36, |
| PATCHABLE_FUNCTION_EXIT = 37, |
| PATCHABLE_TAIL_CALL = 38, |
| PATCHABLE_EVENT_CALL = 39, |
| PATCHABLE_TYPED_EVENT_CALL = 40, |
| ICALL_BRANCH_FUNNEL = 41, |
| MEMBARRIER = 42, |
| G_ASSERT_SEXT = 43, |
| G_ASSERT_ZEXT = 44, |
| G_ASSERT_ALIGN = 45, |
| G_ADD = 46, |
| G_SUB = 47, |
| G_MUL = 48, |
| G_SDIV = 49, |
| G_UDIV = 50, |
| G_SREM = 51, |
| G_UREM = 52, |
| G_SDIVREM = 53, |
| G_UDIVREM = 54, |
| G_AND = 55, |
| G_OR = 56, |
| G_XOR = 57, |
| G_IMPLICIT_DEF = 58, |
| G_PHI = 59, |
| G_FRAME_INDEX = 60, |
| G_GLOBAL_VALUE = 61, |
| G_EXTRACT = 62, |
| G_UNMERGE_VALUES = 63, |
| G_INSERT = 64, |
| G_MERGE_VALUES = 65, |
| G_BUILD_VECTOR = 66, |
| G_BUILD_VECTOR_TRUNC = 67, |
| G_CONCAT_VECTORS = 68, |
| G_PTRTOINT = 69, |
| G_INTTOPTR = 70, |
| G_BITCAST = 71, |
| G_FREEZE = 72, |
| G_INTRINSIC_FPTRUNC_ROUND = 73, |
| G_INTRINSIC_TRUNC = 74, |
| G_INTRINSIC_ROUND = 75, |
| G_INTRINSIC_LRINT = 76, |
| G_INTRINSIC_ROUNDEVEN = 77, |
| G_READCYCLECOUNTER = 78, |
| G_LOAD = 79, |
| G_SEXTLOAD = 80, |
| G_ZEXTLOAD = 81, |
| G_INDEXED_LOAD = 82, |
| G_INDEXED_SEXTLOAD = 83, |
| G_INDEXED_ZEXTLOAD = 84, |
| G_STORE = 85, |
| G_INDEXED_STORE = 86, |
| G_ATOMIC_CMPXCHG_WITH_SUCCESS = 87, |
| G_ATOMIC_CMPXCHG = 88, |
| G_ATOMICRMW_XCHG = 89, |
| G_ATOMICRMW_ADD = 90, |
| G_ATOMICRMW_SUB = 91, |
| G_ATOMICRMW_AND = 92, |
| G_ATOMICRMW_NAND = 93, |
| G_ATOMICRMW_OR = 94, |
| G_ATOMICRMW_XOR = 95, |
| G_ATOMICRMW_MAX = 96, |
| G_ATOMICRMW_MIN = 97, |
| G_ATOMICRMW_UMAX = 98, |
| G_ATOMICRMW_UMIN = 99, |
| G_ATOMICRMW_FADD = 100, |
| G_ATOMICRMW_FSUB = 101, |
| G_ATOMICRMW_FMAX = 102, |
| G_ATOMICRMW_FMIN = 103, |
| G_ATOMICRMW_UINC_WRAP = 104, |
| G_ATOMICRMW_UDEC_WRAP = 105, |
| G_FENCE = 106, |
| G_BRCOND = 107, |
| G_BRINDIRECT = 108, |
| G_INVOKE_REGION_START = 109, |
| G_INTRINSIC = 110, |
| G_INTRINSIC_W_SIDE_EFFECTS = 111, |
| G_ANYEXT = 112, |
| G_TRUNC = 113, |
| G_CONSTANT = 114, |
| G_FCONSTANT = 115, |
| G_VASTART = 116, |
| G_VAARG = 117, |
| G_SEXT = 118, |
| G_SEXT_INREG = 119, |
| G_ZEXT = 120, |
| G_SHL = 121, |
| G_LSHR = 122, |
| G_ASHR = 123, |
| G_FSHL = 124, |
| G_FSHR = 125, |
| G_ROTR = 126, |
| G_ROTL = 127, |
| G_ICMP = 128, |
| G_FCMP = 129, |
| G_SELECT = 130, |
| G_UADDO = 131, |
| G_UADDE = 132, |
| G_USUBO = 133, |
| G_USUBE = 134, |
| G_SADDO = 135, |
| G_SADDE = 136, |
| G_SSUBO = 137, |
| G_SSUBE = 138, |
| G_UMULO = 139, |
| G_SMULO = 140, |
| G_UMULH = 141, |
| G_SMULH = 142, |
| G_UADDSAT = 143, |
| G_SADDSAT = 144, |
| G_USUBSAT = 145, |
| G_SSUBSAT = 146, |
| G_USHLSAT = 147, |
| G_SSHLSAT = 148, |
| G_SMULFIX = 149, |
| G_UMULFIX = 150, |
| G_SMULFIXSAT = 151, |
| G_UMULFIXSAT = 152, |
| G_SDIVFIX = 153, |
| G_UDIVFIX = 154, |
| G_SDIVFIXSAT = 155, |
| G_UDIVFIXSAT = 156, |
| G_FADD = 157, |
| G_FSUB = 158, |
| G_FMUL = 159, |
| G_FMA = 160, |
| G_FMAD = 161, |
| G_FDIV = 162, |
| G_FREM = 163, |
| G_FPOW = 164, |
| G_FPOWI = 165, |
| G_FEXP = 166, |
| G_FEXP2 = 167, |
| G_FLOG = 168, |
| G_FLOG2 = 169, |
| G_FLOG10 = 170, |
| G_FNEG = 171, |
| G_FPEXT = 172, |
| G_FPTRUNC = 173, |
| G_FPTOSI = 174, |
| G_FPTOUI = 175, |
| G_SITOFP = 176, |
| G_UITOFP = 177, |
| G_FABS = 178, |
| G_FCOPYSIGN = 179, |
| G_IS_FPCLASS = 180, |
| G_FCANONICALIZE = 181, |
| G_FMINNUM = 182, |
| G_FMAXNUM = 183, |
| G_FMINNUM_IEEE = 184, |
| G_FMAXNUM_IEEE = 185, |
| G_FMINIMUM = 186, |
| G_FMAXIMUM = 187, |
| G_PTR_ADD = 188, |
| G_PTRMASK = 189, |
| G_SMIN = 190, |
| G_SMAX = 191, |
| G_UMIN = 192, |
| G_UMAX = 193, |
| G_ABS = 194, |
| G_LROUND = 195, |
| G_LLROUND = 196, |
| G_BR = 197, |
| G_BRJT = 198, |
| G_INSERT_VECTOR_ELT = 199, |
| G_EXTRACT_VECTOR_ELT = 200, |
| G_SHUFFLE_VECTOR = 201, |
| G_CTTZ = 202, |
| G_CTTZ_ZERO_UNDEF = 203, |
| G_CTLZ = 204, |
| G_CTLZ_ZERO_UNDEF = 205, |
| G_CTPOP = 206, |
| G_BSWAP = 207, |
| G_BITREVERSE = 208, |
| G_FCEIL = 209, |
| G_FCOS = 210, |
| G_FSIN = 211, |
| G_FSQRT = 212, |
| G_FFLOOR = 213, |
| G_FRINT = 214, |
| G_FNEARBYINT = 215, |
| G_ADDRSPACE_CAST = 216, |
| G_BLOCK_ADDR = 217, |
| G_JUMP_TABLE = 218, |
| G_DYN_STACKALLOC = 219, |
| G_STRICT_FADD = 220, |
| G_STRICT_FSUB = 221, |
| G_STRICT_FMUL = 222, |
| G_STRICT_FDIV = 223, |
| G_STRICT_FREM = 224, |
| G_STRICT_FMA = 225, |
| G_STRICT_FSQRT = 226, |
| G_READ_REGISTER = 227, |
| G_WRITE_REGISTER = 228, |
| G_MEMCPY = 229, |
| G_MEMCPY_INLINE = 230, |
| G_MEMMOVE = 231, |
| G_MEMSET = 232, |
| G_BZERO = 233, |
| G_VECREDUCE_SEQ_FADD = 234, |
| G_VECREDUCE_SEQ_FMUL = 235, |
| G_VECREDUCE_FADD = 236, |
| G_VECREDUCE_FMUL = 237, |
| G_VECREDUCE_FMAX = 238, |
| G_VECREDUCE_FMIN = 239, |
| G_VECREDUCE_ADD = 240, |
| G_VECREDUCE_MUL = 241, |
| G_VECREDUCE_AND = 242, |
| G_VECREDUCE_OR = 243, |
| G_VECREDUCE_XOR = 244, |
| G_VECREDUCE_SMAX = 245, |
| G_VECREDUCE_SMIN = 246, |
| G_VECREDUCE_UMAX = 247, |
| G_VECREDUCE_UMIN = 248, |
| G_SBFX = 249, |
| G_UBFX = 250, |
| ABSMacro = 251, |
| ADJCALLSTACKDOWN = 252, |
| ADJCALLSTACKUP = 253, |
| AND_V_D_PSEUDO = 254, |
| AND_V_H_PSEUDO = 255, |
| AND_V_W_PSEUDO = 256, |
| ATOMIC_CMP_SWAP_I16 = 257, |
| ATOMIC_CMP_SWAP_I16_POSTRA = 258, |
| ATOMIC_CMP_SWAP_I32 = 259, |
| ATOMIC_CMP_SWAP_I32_POSTRA = 260, |
| ATOMIC_CMP_SWAP_I64 = 261, |
| ATOMIC_CMP_SWAP_I64_POSTRA = 262, |
| ATOMIC_CMP_SWAP_I8 = 263, |
| ATOMIC_CMP_SWAP_I8_POSTRA = 264, |
| ATOMIC_LOAD_ADD_I16 = 265, |
| ATOMIC_LOAD_ADD_I16_POSTRA = 266, |
| ATOMIC_LOAD_ADD_I32 = 267, |
| ATOMIC_LOAD_ADD_I32_POSTRA = 268, |
| ATOMIC_LOAD_ADD_I64 = 269, |
| ATOMIC_LOAD_ADD_I64_POSTRA = 270, |
| ATOMIC_LOAD_ADD_I8 = 271, |
| ATOMIC_LOAD_ADD_I8_POSTRA = 272, |
| ATOMIC_LOAD_AND_I16 = 273, |
| ATOMIC_LOAD_AND_I16_POSTRA = 274, |
| ATOMIC_LOAD_AND_I32 = 275, |
| ATOMIC_LOAD_AND_I32_POSTRA = 276, |
| ATOMIC_LOAD_AND_I64 = 277, |
| ATOMIC_LOAD_AND_I64_POSTRA = 278, |
| ATOMIC_LOAD_AND_I8 = 279, |
| ATOMIC_LOAD_AND_I8_POSTRA = 280, |
| ATOMIC_LOAD_MAX_I16 = 281, |
| ATOMIC_LOAD_MAX_I16_POSTRA = 282, |
| ATOMIC_LOAD_MAX_I32 = 283, |
| ATOMIC_LOAD_MAX_I32_POSTRA = 284, |
| ATOMIC_LOAD_MAX_I64 = 285, |
| ATOMIC_LOAD_MAX_I64_POSTRA = 286, |
| ATOMIC_LOAD_MAX_I8 = 287, |
| ATOMIC_LOAD_MAX_I8_POSTRA = 288, |
| ATOMIC_LOAD_MIN_I16 = 289, |
| ATOMIC_LOAD_MIN_I16_POSTRA = 290, |
| ATOMIC_LOAD_MIN_I32 = 291, |
| ATOMIC_LOAD_MIN_I32_POSTRA = 292, |
| ATOMIC_LOAD_MIN_I64 = 293, |
| ATOMIC_LOAD_MIN_I64_POSTRA = 294, |
| ATOMIC_LOAD_MIN_I8 = 295, |
| ATOMIC_LOAD_MIN_I8_POSTRA = 296, |
| ATOMIC_LOAD_NAND_I16 = 297, |
| ATOMIC_LOAD_NAND_I16_POSTRA = 298, |
| ATOMIC_LOAD_NAND_I32 = 299, |
| ATOMIC_LOAD_NAND_I32_POSTRA = 300, |
| ATOMIC_LOAD_NAND_I64 = 301, |
| ATOMIC_LOAD_NAND_I64_POSTRA = 302, |
| ATOMIC_LOAD_NAND_I8 = 303, |
| ATOMIC_LOAD_NAND_I8_POSTRA = 304, |
| ATOMIC_LOAD_OR_I16 = 305, |
| ATOMIC_LOAD_OR_I16_POSTRA = 306, |
| ATOMIC_LOAD_OR_I32 = 307, |
| ATOMIC_LOAD_OR_I32_POSTRA = 308, |
| ATOMIC_LOAD_OR_I64 = 309, |
| ATOMIC_LOAD_OR_I64_POSTRA = 310, |
| ATOMIC_LOAD_OR_I8 = 311, |
| ATOMIC_LOAD_OR_I8_POSTRA = 312, |
| ATOMIC_LOAD_SUB_I16 = 313, |
| ATOMIC_LOAD_SUB_I16_POSTRA = 314, |
| ATOMIC_LOAD_SUB_I32 = 315, |
| ATOMIC_LOAD_SUB_I32_POSTRA = 316, |
| ATOMIC_LOAD_SUB_I64 = 317, |
| ATOMIC_LOAD_SUB_I64_POSTRA = 318, |
| ATOMIC_LOAD_SUB_I8 = 319, |
| ATOMIC_LOAD_SUB_I8_POSTRA = 320, |
| ATOMIC_LOAD_UMAX_I16 = 321, |
| ATOMIC_LOAD_UMAX_I16_POSTRA = 322, |
| ATOMIC_LOAD_UMAX_I32 = 323, |
| ATOMIC_LOAD_UMAX_I32_POSTRA = 324, |
| ATOMIC_LOAD_UMAX_I64 = 325, |
| ATOMIC_LOAD_UMAX_I64_POSTRA = 326, |
| ATOMIC_LOAD_UMAX_I8 = 327, |
| ATOMIC_LOAD_UMAX_I8_POSTRA = 328, |
| ATOMIC_LOAD_UMIN_I16 = 329, |
| ATOMIC_LOAD_UMIN_I16_POSTRA = 330, |
| ATOMIC_LOAD_UMIN_I32 = 331, |
| ATOMIC_LOAD_UMIN_I32_POSTRA = 332, |
| ATOMIC_LOAD_UMIN_I64 = 333, |
| ATOMIC_LOAD_UMIN_I64_POSTRA = 334, |
| ATOMIC_LOAD_UMIN_I8 = 335, |
| ATOMIC_LOAD_UMIN_I8_POSTRA = 336, |
| ATOMIC_LOAD_XOR_I16 = 337, |
| ATOMIC_LOAD_XOR_I16_POSTRA = 338, |
| ATOMIC_LOAD_XOR_I32 = 339, |
| ATOMIC_LOAD_XOR_I32_POSTRA = 340, |
| ATOMIC_LOAD_XOR_I64 = 341, |
| ATOMIC_LOAD_XOR_I64_POSTRA = 342, |
| ATOMIC_LOAD_XOR_I8 = 343, |
| ATOMIC_LOAD_XOR_I8_POSTRA = 344, |
| ATOMIC_SWAP_I16 = 345, |
| ATOMIC_SWAP_I16_POSTRA = 346, |
| ATOMIC_SWAP_I32 = 347, |
| ATOMIC_SWAP_I32_POSTRA = 348, |
| ATOMIC_SWAP_I64 = 349, |
| ATOMIC_SWAP_I64_POSTRA = 350, |
| ATOMIC_SWAP_I8 = 351, |
| ATOMIC_SWAP_I8_POSTRA = 352, |
| B = 353, |
| BAL_BR = 354, |
| BAL_BR_MM = 355, |
| BEQLImmMacro = 356, |
| BGE = 357, |
| BGEImmMacro = 358, |
| BGEL = 359, |
| BGELImmMacro = 360, |
| BGEU = 361, |
| BGEUImmMacro = 362, |
| BGEUL = 363, |
| BGEULImmMacro = 364, |
| BGT = 365, |
| BGTImmMacro = 366, |
| BGTL = 367, |
| BGTLImmMacro = 368, |
| BGTU = 369, |
| BGTUImmMacro = 370, |
| BGTUL = 371, |
| BGTULImmMacro = 372, |
| BLE = 373, |
| BLEImmMacro = 374, |
| BLEL = 375, |
| BLELImmMacro = 376, |
| BLEU = 377, |
| BLEUImmMacro = 378, |
| BLEUL = 379, |
| BLEULImmMacro = 380, |
| BLT = 381, |
| BLTImmMacro = 382, |
| BLTL = 383, |
| BLTLImmMacro = 384, |
| BLTU = 385, |
| BLTUImmMacro = 386, |
| BLTUL = 387, |
| BLTULImmMacro = 388, |
| BNELImmMacro = 389, |
| BPOSGE32_PSEUDO = 390, |
| BSEL_D_PSEUDO = 391, |
| BSEL_FD_PSEUDO = 392, |
| BSEL_FW_PSEUDO = 393, |
| BSEL_H_PSEUDO = 394, |
| BSEL_W_PSEUDO = 395, |
| B_MM = 396, |
| B_MMR6_Pseudo = 397, |
| B_MM_Pseudo = 398, |
| BeqImm = 399, |
| BneImm = 400, |
| BteqzT8CmpX16 = 401, |
| BteqzT8CmpiX16 = 402, |
| BteqzT8SltX16 = 403, |
| BteqzT8SltiX16 = 404, |
| BteqzT8SltiuX16 = 405, |
| BteqzT8SltuX16 = 406, |
| BtnezT8CmpX16 = 407, |
| BtnezT8CmpiX16 = 408, |
| BtnezT8SltX16 = 409, |
| BtnezT8SltiX16 = 410, |
| BtnezT8SltiuX16 = 411, |
| BtnezT8SltuX16 = 412, |
| BuildPairF64 = 413, |
| BuildPairF64_64 = 414, |
| CFTC1 = 415, |
| CONSTPOOL_ENTRY = 416, |
| COPY_FD_PSEUDO = 417, |
| COPY_FW_PSEUDO = 418, |
| CTTC1 = 419, |
| Constant32 = 420, |
| DMULImmMacro = 421, |
| DMULMacro = 422, |
| DMULOMacro = 423, |
| DMULOUMacro = 424, |
| DROL = 425, |
| DROLImm = 426, |
| DROR = 427, |
| DRORImm = 428, |
| DSDivIMacro = 429, |
| DSDivMacro = 430, |
| DSRemIMacro = 431, |
| DSRemMacro = 432, |
| DUDivIMacro = 433, |
| DUDivMacro = 434, |
| DURemIMacro = 435, |
| DURemMacro = 436, |
| ERet = 437, |
| ExtractElementF64 = 438, |
| ExtractElementF64_64 = 439, |
| FABS_D = 440, |
| FABS_W = 441, |
| FEXP2_D_1_PSEUDO = 442, |
| FEXP2_W_1_PSEUDO = 443, |
| FILL_FD_PSEUDO = 444, |
| FILL_FW_PSEUDO = 445, |
| GotPrologue16 = 446, |
| INSERT_B_VIDX64_PSEUDO = 447, |
| INSERT_B_VIDX_PSEUDO = 448, |
| INSERT_D_VIDX64_PSEUDO = 449, |
| INSERT_D_VIDX_PSEUDO = 450, |
| INSERT_FD_PSEUDO = 451, |
| INSERT_FD_VIDX64_PSEUDO = 452, |
| INSERT_FD_VIDX_PSEUDO = 453, |
| INSERT_FW_PSEUDO = 454, |
| INSERT_FW_VIDX64_PSEUDO = 455, |
| INSERT_FW_VIDX_PSEUDO = 456, |
| INSERT_H_VIDX64_PSEUDO = 457, |
| INSERT_H_VIDX_PSEUDO = 458, |
| INSERT_W_VIDX64_PSEUDO = 459, |
| INSERT_W_VIDX_PSEUDO = 460, |
| JALR64Pseudo = 461, |
| JALRHB64Pseudo = 462, |
| JALRHBPseudo = 463, |
| JALRPseudo = 464, |
| JAL_MMR6 = 465, |
| JalOneReg = 466, |
| JalTwoReg = 467, |
| LDMacro = 468, |
| LDR_D = 469, |
| LDR_W = 470, |
| LD_F16 = 471, |
| LOAD_ACC128 = 472, |
| LOAD_ACC64 = 473, |
| LOAD_ACC64DSP = 474, |
| LOAD_CCOND_DSP = 475, |
| LONG_BRANCH_ADDiu = 476, |
| LONG_BRANCH_ADDiu2Op = 477, |
| LONG_BRANCH_DADDiu = 478, |
| LONG_BRANCH_DADDiu2Op = 479, |
| LONG_BRANCH_LUi = 480, |
| LONG_BRANCH_LUi2Op = 481, |
| LONG_BRANCH_LUi2Op_64 = 482, |
| LWM_MM = 483, |
| LoadAddrImm32 = 484, |
| LoadAddrImm64 = 485, |
| LoadAddrReg32 = 486, |
| LoadAddrReg64 = 487, |
| LoadImm32 = 488, |
| LoadImm64 = 489, |
| LoadImmDoubleFGR = 490, |
| LoadImmDoubleFGR_32 = 491, |
| LoadImmDoubleGPR = 492, |
| LoadImmSingleFGR = 493, |
| LoadImmSingleGPR = 494, |
| LwConstant32 = 495, |
| MFTACX = 496, |
| MFTC0 = 497, |
| MFTC1 = 498, |
| MFTDSP = 499, |
| MFTGPR = 500, |
| MFTHC1 = 501, |
| MFTHI = 502, |
| MFTLO = 503, |
| MIPSeh_return32 = 504, |
| MIPSeh_return64 = 505, |
| MSA_FP_EXTEND_D_PSEUDO = 506, |
| MSA_FP_EXTEND_W_PSEUDO = 507, |
| MSA_FP_ROUND_D_PSEUDO = 508, |
| MSA_FP_ROUND_W_PSEUDO = 509, |
| MTTACX = 510, |
| MTTC0 = 511, |
| MTTC1 = 512, |
| MTTDSP = 513, |
| MTTGPR = 514, |
| MTTHC1 = 515, |
| MTTHI = 516, |
| MTTLO = 517, |
| MULImmMacro = 518, |
| MULOMacro = 519, |
| MULOUMacro = 520, |
| MultRxRy16 = 521, |
| MultRxRyRz16 = 522, |
| MultuRxRy16 = 523, |
| MultuRxRyRz16 = 524, |
| NOP = 525, |
| NORImm = 526, |
| NORImm64 = 527, |
| NOR_V_D_PSEUDO = 528, |
| NOR_V_H_PSEUDO = 529, |
| NOR_V_W_PSEUDO = 530, |
| OR_V_D_PSEUDO = 531, |
| OR_V_H_PSEUDO = 532, |
| OR_V_W_PSEUDO = 533, |
| PseudoCMPU_EQ_QB = 534, |
| PseudoCMPU_LE_QB = 535, |
| PseudoCMPU_LT_QB = 536, |
| PseudoCMP_EQ_PH = 537, |
| PseudoCMP_LE_PH = 538, |
| PseudoCMP_LT_PH = 539, |
| PseudoCVT_D32_W = 540, |
| PseudoCVT_D64_L = 541, |
| PseudoCVT_D64_W = 542, |
| PseudoCVT_S_L = 543, |
| PseudoCVT_S_W = 544, |
| PseudoDMULT = 545, |
| PseudoDMULTu = 546, |
| PseudoDSDIV = 547, |
| PseudoDUDIV = 548, |
| PseudoD_SELECT_I = 549, |
| PseudoD_SELECT_I64 = 550, |
| PseudoIndirectBranch = 551, |
| PseudoIndirectBranch64 = 552, |
| PseudoIndirectBranch64R6 = 553, |
| PseudoIndirectBranchR6 = 554, |
| PseudoIndirectBranch_MM = 555, |
| PseudoIndirectBranch_MMR6 = 556, |
| PseudoIndirectHazardBranch = 557, |
| PseudoIndirectHazardBranch64 = 558, |
| PseudoIndrectHazardBranch64R6 = 559, |
| PseudoIndrectHazardBranchR6 = 560, |
| PseudoMADD = 561, |
| PseudoMADDU = 562, |
| PseudoMADDU_MM = 563, |
| PseudoMADD_MM = 564, |
| PseudoMFHI = 565, |
| PseudoMFHI64 = 566, |
| PseudoMFHI_MM = 567, |
| PseudoMFLO = 568, |
| PseudoMFLO64 = 569, |
| PseudoMFLO_MM = 570, |
| PseudoMSUB = 571, |
| PseudoMSUBU = 572, |
| PseudoMSUBU_MM = 573, |
| PseudoMSUB_MM = 574, |
| PseudoMTLOHI = 575, |
| PseudoMTLOHI64 = 576, |
| PseudoMTLOHI_DSP = 577, |
| PseudoMTLOHI_MM = 578, |
| PseudoMULT = 579, |
| PseudoMULT_MM = 580, |
| PseudoMULTu = 581, |
| PseudoMULTu_MM = 582, |
| PseudoPICK_PH = 583, |
| PseudoPICK_QB = 584, |
| PseudoReturn = 585, |
| PseudoReturn64 = 586, |
| PseudoSDIV = 587, |
| PseudoSELECTFP_F_D32 = 588, |
| PseudoSELECTFP_F_D64 = 589, |
| PseudoSELECTFP_F_I = 590, |
| PseudoSELECTFP_F_I64 = 591, |
| PseudoSELECTFP_F_S = 592, |
| PseudoSELECTFP_T_D32 = 593, |
| PseudoSELECTFP_T_D64 = 594, |
| PseudoSELECTFP_T_I = 595, |
| PseudoSELECTFP_T_I64 = 596, |
| PseudoSELECTFP_T_S = 597, |
| PseudoSELECT_D32 = 598, |
| PseudoSELECT_D64 = 599, |
| PseudoSELECT_I = 600, |
| PseudoSELECT_I64 = 601, |
| PseudoSELECT_S = 602, |
| PseudoTRUNC_W_D = 603, |
| PseudoTRUNC_W_D32 = 604, |
| PseudoTRUNC_W_S = 605, |
| PseudoUDIV = 606, |
| ROL = 607, |
| ROLImm = 608, |
| ROR = 609, |
| RORImm = 610, |
| RetRA = 611, |
| RetRA16 = 612, |
| SDC1_M1 = 613, |
| SDIV_MM_Pseudo = 614, |
| SDMacro = 615, |
| SDivIMacro = 616, |
| SDivMacro = 617, |
| SEQIMacro = 618, |
| SEQMacro = 619, |
| SGE = 620, |
| SGEImm = 621, |
| SGEImm64 = 622, |
| SGEU = 623, |
| SGEUImm = 624, |
| SGEUImm64 = 625, |
| SGTImm = 626, |
| SGTImm64 = 627, |
| SGTUImm = 628, |
| SGTUImm64 = 629, |
| SLE = 630, |
| SLEImm = 631, |
| SLEImm64 = 632, |
| SLEU = 633, |
| SLEUImm = 634, |
| SLEUImm64 = 635, |
| SLTImm64 = 636, |
| SLTUImm64 = 637, |
| SNEIMacro = 638, |
| SNEMacro = 639, |
| SNZ_B_PSEUDO = 640, |
| SNZ_D_PSEUDO = 641, |
| SNZ_H_PSEUDO = 642, |
| SNZ_V_PSEUDO = 643, |
| SNZ_W_PSEUDO = 644, |
| SRemIMacro = 645, |
| SRemMacro = 646, |
| STORE_ACC128 = 647, |
| STORE_ACC64 = 648, |
| STORE_ACC64DSP = 649, |
| STORE_CCOND_DSP = 650, |
| STR_D = 651, |
| STR_W = 652, |
| ST_F16 = 653, |
| SWM_MM = 654, |
| SZ_B_PSEUDO = 655, |
| SZ_D_PSEUDO = 656, |
| SZ_H_PSEUDO = 657, |
| SZ_V_PSEUDO = 658, |
| SZ_W_PSEUDO = 659, |
| SaaAddr = 660, |
| SaadAddr = 661, |
| SelBeqZ = 662, |
| SelBneZ = 663, |
| SelTBteqZCmp = 664, |
| SelTBteqZCmpi = 665, |
| SelTBteqZSlt = 666, |
| SelTBteqZSlti = 667, |
| SelTBteqZSltiu = 668, |
| SelTBteqZSltu = 669, |
| SelTBtneZCmp = 670, |
| SelTBtneZCmpi = 671, |
| SelTBtneZSlt = 672, |
| SelTBtneZSlti = 673, |
| SelTBtneZSltiu = 674, |
| SelTBtneZSltu = 675, |
| SltCCRxRy16 = 676, |
| SltiCCRxImmX16 = 677, |
| SltiuCCRxImmX16 = 678, |
| SltuCCRxRy16 = 679, |
| SltuRxRyRz16 = 680, |
| TAILCALL = 681, |
| TAILCALL64R6REG = 682, |
| TAILCALLHB64R6REG = 683, |
| TAILCALLHBR6REG = 684, |
| TAILCALLR6REG = 685, |
| TAILCALLREG = 686, |
| TAILCALLREG64 = 687, |
| TAILCALLREGHB = 688, |
| TAILCALLREGHB64 = 689, |
| TAILCALLREG_MM = 690, |
| TAILCALLREG_MMR6 = 691, |
| TAILCALL_MM = 692, |
| TAILCALL_MMR6 = 693, |
| TRAP = 694, |
| TRAP_MM = 695, |
| UDIV_MM_Pseudo = 696, |
| UDivIMacro = 697, |
| UDivMacro = 698, |
| URemIMacro = 699, |
| URemMacro = 700, |
| Ulh = 701, |
| Ulhu = 702, |
| Ulw = 703, |
| Ush = 704, |
| Usw = 705, |
| XOR_V_D_PSEUDO = 706, |
| XOR_V_H_PSEUDO = 707, |
| XOR_V_W_PSEUDO = 708, |
| ABSQ_S_PH = 709, |
| ABSQ_S_PH_MM = 710, |
| ABSQ_S_QB = 711, |
| ABSQ_S_QB_MMR2 = 712, |
| ABSQ_S_W = 713, |
| ABSQ_S_W_MM = 714, |
| ADD = 715, |
| ADDIUPC = 716, |
| ADDIUPC_MM = 717, |
| ADDIUPC_MMR6 = 718, |
| ADDIUR1SP_MM = 719, |
| ADDIUR2_MM = 720, |
| ADDIUS5_MM = 721, |
| ADDIUSP_MM = 722, |
| ADDIU_MMR6 = 723, |
| ADDQH_PH = 724, |
| ADDQH_PH_MMR2 = 725, |
| ADDQH_R_PH = 726, |
| ADDQH_R_PH_MMR2 = 727, |
| ADDQH_R_W = 728, |
| ADDQH_R_W_MMR2 = 729, |
| ADDQH_W = 730, |
| ADDQH_W_MMR2 = 731, |
| ADDQ_PH = 732, |
| ADDQ_PH_MM = 733, |
| ADDQ_S_PH = 734, |
| ADDQ_S_PH_MM = 735, |
| ADDQ_S_W = 736, |
| ADDQ_S_W_MM = 737, |
| ADDR_PS64 = 738, |
| ADDSC = 739, |
| ADDSC_MM = 740, |
| ADDS_A_B = 741, |
| ADDS_A_D = 742, |
| ADDS_A_H = 743, |
| ADDS_A_W = 744, |
| ADDS_S_B = 745, |
| ADDS_S_D = 746, |
| ADDS_S_H = 747, |
| ADDS_S_W = 748, |
| ADDS_U_B = 749, |
| ADDS_U_D = 750, |
| ADDS_U_H = 751, |
| ADDS_U_W = 752, |
| ADDU16_MM = 753, |
| ADDU16_MMR6 = 754, |
| ADDUH_QB = 755, |
| ADDUH_QB_MMR2 = 756, |
| ADDUH_R_QB = 757, |
| ADDUH_R_QB_MMR2 = 758, |
| ADDU_MMR6 = 759, |
| ADDU_PH = 760, |
| ADDU_PH_MMR2 = 761, |
| ADDU_QB = 762, |
| ADDU_QB_MM = 763, |
| ADDU_S_PH = 764, |
| ADDU_S_PH_MMR2 = 765, |
| ADDU_S_QB = 766, |
| ADDU_S_QB_MM = 767, |
| ADDVI_B = 768, |
| ADDVI_D = 769, |
| ADDVI_H = 770, |
| ADDVI_W = 771, |
| ADDV_B = 772, |
| ADDV_D = 773, |
| ADDV_H = 774, |
| ADDV_W = 775, |
| ADDWC = 776, |
| ADDWC_MM = 777, |
| ADD_A_B = 778, |
| ADD_A_D = 779, |
| ADD_A_H = 780, |
| ADD_A_W = 781, |
| ADD_MM = 782, |
| ADD_MMR6 = 783, |
| ADDi = 784, |
| ADDi_MM = 785, |
| ADDiu = 786, |
| ADDiu_MM = 787, |
| ADDu = 788, |
| ADDu_MM = 789, |
| ALIGN = 790, |
| ALIGN_MMR6 = 791, |
| ALUIPC = 792, |
| ALUIPC_MMR6 = 793, |
| AND = 794, |
| AND16_MM = 795, |
| AND16_MMR6 = 796, |
| AND64 = 797, |
| ANDI16_MM = 798, |
| ANDI16_MMR6 = 799, |
| ANDI_B = 800, |
| ANDI_MMR6 = 801, |
| AND_MM = 802, |
| AND_MMR6 = 803, |
| AND_V = 804, |
| ANDi = 805, |
| ANDi64 = 806, |
| ANDi_MM = 807, |
| APPEND = 808, |
| APPEND_MMR2 = 809, |
| ASUB_S_B = 810, |
| ASUB_S_D = 811, |
| ASUB_S_H = 812, |
| ASUB_S_W = 813, |
| ASUB_U_B = 814, |
| ASUB_U_D = 815, |
| ASUB_U_H = 816, |
| ASUB_U_W = 817, |
| AUI = 818, |
| AUIPC = 819, |
| AUIPC_MMR6 = 820, |
| AUI_MMR6 = 821, |
| AVER_S_B = 822, |
| AVER_S_D = 823, |
| AVER_S_H = 824, |
| AVER_S_W = 825, |
| AVER_U_B = 826, |
| AVER_U_D = 827, |
| AVER_U_H = 828, |
| AVER_U_W = 829, |
| AVE_S_B = 830, |
| AVE_S_D = 831, |
| AVE_S_H = 832, |
| AVE_S_W = 833, |
| AVE_U_B = 834, |
| AVE_U_D = 835, |
| AVE_U_H = 836, |
| AVE_U_W = 837, |
| AddiuRxImmX16 = 838, |
| AddiuRxPcImmX16 = 839, |
| AddiuRxRxImm16 = 840, |
| AddiuRxRxImmX16 = 841, |
| AddiuRxRyOffMemX16 = 842, |
| AddiuSpImm16 = 843, |
| AddiuSpImmX16 = 844, |
| AdduRxRyRz16 = 845, |
| AndRxRxRy16 = 846, |
| B16_MM = 847, |
| BADDu = 848, |
| BAL = 849, |
| BALC = 850, |
| BALC_MMR6 = 851, |
| BALIGN = 852, |
| BALIGN_MMR2 = 853, |
| BBIT0 = 854, |
| BBIT032 = 855, |
| BBIT1 = 856, |
| BBIT132 = 857, |
| BC = 858, |
| BC16_MMR6 = 859, |
| BC1EQZ = 860, |
| BC1EQZC_MMR6 = 861, |
| BC1F = 862, |
| BC1FL = 863, |
| BC1F_MM = 864, |
| BC1NEZ = 865, |
| BC1NEZC_MMR6 = 866, |
| BC1T = 867, |
| BC1TL = 868, |
| BC1T_MM = 869, |
| BC2EQZ = 870, |
| BC2EQZC_MMR6 = 871, |
| BC2NEZ = 872, |
| BC2NEZC_MMR6 = 873, |
| BCLRI_B = 874, |
| BCLRI_D = 875, |
| BCLRI_H = 876, |
| BCLRI_W = 877, |
| BCLR_B = 878, |
| BCLR_D = 879, |
| BCLR_H = 880, |
| BCLR_W = 881, |
| BC_MMR6 = 882, |
| BEQ = 883, |
| BEQ64 = 884, |
| BEQC = 885, |
| BEQC64 = 886, |
| BEQC_MMR6 = 887, |
| BEQL = 888, |
| BEQZ16_MM = 889, |
| BEQZALC = 890, |
| BEQZALC_MMR6 = 891, |
| BEQZC = 892, |
| BEQZC16_MMR6 = 893, |
| BEQZC64 = 894, |
| BEQZC_MM = 895, |
| BEQZC_MMR6 = 896, |
| BEQ_MM = 897, |
| BGEC = 898, |
| BGEC64 = 899, |
| BGEC_MMR6 = 900, |
| BGEUC = 901, |
| BGEUC64 = 902, |
| BGEUC_MMR6 = 903, |
| BGEZ = 904, |
| BGEZ64 = 905, |
| BGEZAL = 906, |
| BGEZALC = 907, |
| BGEZALC_MMR6 = 908, |
| BGEZALL = 909, |
| BGEZALS_MM = 910, |
| BGEZAL_MM = 911, |
| BGEZC = 912, |
| BGEZC64 = 913, |
| BGEZC_MMR6 = 914, |
| BGEZL = 915, |
| BGEZ_MM = 916, |
| BGTZ = 917, |
| BGTZ64 = 918, |
| BGTZALC = 919, |
| BGTZALC_MMR6 = 920, |
| BGTZC = 921, |
| BGTZC64 = 922, |
| BGTZC_MMR6 = 923, |
| BGTZL = 924, |
| BGTZ_MM = 925, |
| BINSLI_B = 926, |
| BINSLI_D = 927, |
| BINSLI_H = 928, |
| BINSLI_W = 929, |
| BINSL_B = 930, |
| BINSL_D = 931, |
| BINSL_H = 932, |
| BINSL_W = 933, |
| BINSRI_B = 934, |
| BINSRI_D = 935, |
| BINSRI_H = 936, |
| BINSRI_W = 937, |
| BINSR_B = 938, |
| BINSR_D = 939, |
| BINSR_H = 940, |
| BINSR_W = 941, |
| BITREV = 942, |
| BITREV_MM = 943, |
| BITSWAP = 944, |
| BITSWAP_MMR6 = 945, |
| BLEZ = 946, |
| BLEZ64 = 947, |
| BLEZALC = 948, |
| BLEZALC_MMR6 = 949, |
| BLEZC = 950, |
| BLEZC64 = 951, |
| BLEZC_MMR6 = 952, |
| BLEZL = 953, |
| BLEZ_MM = 954, |
| BLTC = 955, |
| BLTC64 = 956, |
| BLTC_MMR6 = 957, |
| BLTUC = 958, |
| BLTUC64 = 959, |
| BLTUC_MMR6 = 960, |
| BLTZ = 961, |
| BLTZ64 = 962, |
| BLTZAL = 963, |
| BLTZALC = 964, |
| BLTZALC_MMR6 = 965, |
| BLTZALL = 966, |
| BLTZALS_MM = 967, |
| BLTZAL_MM = 968, |
| BLTZC = 969, |
| BLTZC64 = 970, |
| BLTZC_MMR6 = 971, |
| BLTZL = 972, |
| BLTZ_MM = 973, |
| BMNZI_B = 974, |
| BMNZ_V = 975, |
| BMZI_B = 976, |
| BMZ_V = 977, |
| BNE = 978, |
| BNE64 = 979, |
| BNEC = 980, |
| BNEC64 = 981, |
| BNEC_MMR6 = 982, |
| BNEGI_B = 983, |
| BNEGI_D = 984, |
| BNEGI_H = 985, |
| BNEGI_W = 986, |
| BNEG_B = 987, |
| BNEG_D = 988, |
| BNEG_H = 989, |
| BNEG_W = 990, |
| BNEL = 991, |
| BNEZ16_MM = 992, |
| BNEZALC = 993, |
| BNEZALC_MMR6 = 994, |
| BNEZC = 995, |
| BNEZC16_MMR6 = 996, |
| BNEZC64 = 997, |
| BNEZC_MM = 998, |
| BNEZC_MMR6 = 999, |
| BNE_MM = 1000, |
| BNVC = 1001, |
| BNVC_MMR6 = 1002, |
| BNZ_B = 1003, |
| BNZ_D = 1004, |
| BNZ_H = 1005, |
| BNZ_V = 1006, |
| BNZ_W = 1007, |
| BOVC = 1008, |
| BOVC_MMR6 = 1009, |
| BPOSGE32 = 1010, |
| BPOSGE32C_MMR3 = 1011, |
| BPOSGE32_MM = 1012, |
| BREAK = 1013, |
| BREAK16_MM = 1014, |
| BREAK16_MMR6 = 1015, |
| BREAK_MM = 1016, |
| BREAK_MMR6 = 1017, |
| BSELI_B = 1018, |
| BSEL_V = 1019, |
| BSETI_B = 1020, |
| BSETI_D = 1021, |
| BSETI_H = 1022, |
| BSETI_W = 1023, |
| BSET_B = 1024, |
| BSET_D = 1025, |
| BSET_H = 1026, |
| BSET_W = 1027, |
| BZ_B = 1028, |
| BZ_D = 1029, |
| BZ_H = 1030, |
| BZ_V = 1031, |
| BZ_W = 1032, |
| BeqzRxImm16 = 1033, |
| BeqzRxImmX16 = 1034, |
| Bimm16 = 1035, |
| BimmX16 = 1036, |
| BnezRxImm16 = 1037, |
| BnezRxImmX16 = 1038, |
| Break16 = 1039, |
| Bteqz16 = 1040, |
| BteqzX16 = 1041, |
| Btnez16 = 1042, |
| BtnezX16 = 1043, |
| CACHE = 1044, |
| CACHEE = 1045, |
| CACHEE_MM = 1046, |
| CACHE_MM = 1047, |
| CACHE_MMR6 = 1048, |
| CACHE_R6 = 1049, |
| CEIL_L_D64 = 1050, |
| CEIL_L_D_MMR6 = 1051, |
| CEIL_L_S = 1052, |
| CEIL_L_S_MMR6 = 1053, |
| CEIL_W_D32 = 1054, |
| CEIL_W_D64 = 1055, |
| CEIL_W_D_MMR6 = 1056, |
| CEIL_W_MM = 1057, |
| CEIL_W_S = 1058, |
| CEIL_W_S_MM = 1059, |
| CEIL_W_S_MMR6 = 1060, |
| CEQI_B = 1061, |
| CEQI_D = 1062, |
| CEQI_H = 1063, |
| CEQI_W = 1064, |
| CEQ_B = 1065, |
| CEQ_D = 1066, |
| CEQ_H = 1067, |
| CEQ_W = 1068, |
| CFC1 = 1069, |
| CFC1_MM = 1070, |
| CFC2_MM = 1071, |
| CFCMSA = 1072, |
| CINS = 1073, |
| CINS32 = 1074, |
| CINS64_32 = 1075, |
| CINS_i32 = 1076, |
| CLASS_D = 1077, |
| CLASS_D_MMR6 = 1078, |
| CLASS_S = 1079, |
| CLASS_S_MMR6 = 1080, |
| CLEI_S_B = 1081, |
| CLEI_S_D = 1082, |
| CLEI_S_H = 1083, |
| CLEI_S_W = 1084, |
| CLEI_U_B = 1085, |
| CLEI_U_D = 1086, |
| CLEI_U_H = 1087, |
| CLEI_U_W = 1088, |
| CLE_S_B = 1089, |
| CLE_S_D = 1090, |
| CLE_S_H = 1091, |
| CLE_S_W = 1092, |
| CLE_U_B = 1093, |
| CLE_U_D = 1094, |
| CLE_U_H = 1095, |
| CLE_U_W = 1096, |
| CLO = 1097, |
| CLO_MM = 1098, |
| CLO_MMR6 = 1099, |
| CLO_R6 = 1100, |
| CLTI_S_B = 1101, |
| CLTI_S_D = 1102, |
| CLTI_S_H = 1103, |
| CLTI_S_W = 1104, |
| CLTI_U_B = 1105, |
| CLTI_U_D = 1106, |
| CLTI_U_H = 1107, |
| CLTI_U_W = 1108, |
| CLT_S_B = 1109, |
| CLT_S_D = 1110, |
| CLT_S_H = 1111, |
| CLT_S_W = 1112, |
| CLT_U_B = 1113, |
| CLT_U_D = 1114, |
| CLT_U_H = 1115, |
| CLT_U_W = 1116, |
| CLZ = 1117, |
| CLZ_MM = 1118, |
| CLZ_MMR6 = 1119, |
| CLZ_R6 = 1120, |
| CMPGDU_EQ_QB = 1121, |
| CMPGDU_EQ_QB_MMR2 = 1122, |
| CMPGDU_LE_QB = 1123, |
| CMPGDU_LE_QB_MMR2 = 1124, |
| CMPGDU_LT_QB = 1125, |
| CMPGDU_LT_QB_MMR2 = 1126, |
| CMPGU_EQ_QB = 1127, |
| CMPGU_EQ_QB_MM = 1128, |
| CMPGU_LE_QB = 1129, |
| CMPGU_LE_QB_MM = 1130, |
| CMPGU_LT_QB = 1131, |
| CMPGU_LT_QB_MM = 1132, |
| CMPU_EQ_QB = 1133, |
| CMPU_EQ_QB_MM = 1134, |
| CMPU_LE_QB = 1135, |
| CMPU_LE_QB_MM = 1136, |
| CMPU_LT_QB = 1137, |
| CMPU_LT_QB_MM = 1138, |
| CMP_AF_D_MMR6 = 1139, |
| CMP_AF_S_MMR6 = 1140, |
| CMP_EQ_D = 1141, |
| CMP_EQ_D_MMR6 = 1142, |
| CMP_EQ_PH = 1143, |
| CMP_EQ_PH_MM = 1144, |
| CMP_EQ_S = 1145, |
| CMP_EQ_S_MMR6 = 1146, |
| CMP_F_D = 1147, |
| CMP_F_S = 1148, |
| CMP_LE_D = 1149, |
| CMP_LE_D_MMR6 = 1150, |
| CMP_LE_PH = 1151, |
| CMP_LE_PH_MM = 1152, |
| CMP_LE_S = 1153, |
| CMP_LE_S_MMR6 = 1154, |
| CMP_LT_D = 1155, |
| CMP_LT_D_MMR6 = 1156, |
| CMP_LT_PH = 1157, |
| CMP_LT_PH_MM = 1158, |
| CMP_LT_S = 1159, |
| CMP_LT_S_MMR6 = 1160, |
| CMP_SAF_D = 1161, |
| CMP_SAF_D_MMR6 = 1162, |
| CMP_SAF_S = 1163, |
| CMP_SAF_S_MMR6 = 1164, |
| CMP_SEQ_D = 1165, |
| CMP_SEQ_D_MMR6 = 1166, |
| CMP_SEQ_S = 1167, |
| CMP_SEQ_S_MMR6 = 1168, |
| CMP_SLE_D = 1169, |
| CMP_SLE_D_MMR6 = 1170, |
| CMP_SLE_S = 1171, |
| CMP_SLE_S_MMR6 = 1172, |
| CMP_SLT_D = 1173, |
| CMP_SLT_D_MMR6 = 1174, |
| CMP_SLT_S = 1175, |
| CMP_SLT_S_MMR6 = 1176, |
| CMP_SUEQ_D = 1177, |
| CMP_SUEQ_D_MMR6 = 1178, |
| CMP_SUEQ_S = 1179, |
| CMP_SUEQ_S_MMR6 = 1180, |
| CMP_SULE_D = 1181, |
| CMP_SULE_D_MMR6 = 1182, |
| CMP_SULE_S = 1183, |
| CMP_SULE_S_MMR6 = 1184, |
| CMP_SULT_D = 1185, |
| CMP_SULT_D_MMR6 = 1186, |
| CMP_SULT_S = 1187, |
| CMP_SULT_S_MMR6 = 1188, |
| CMP_SUN_D = 1189, |
| CMP_SUN_D_MMR6 = 1190, |
| CMP_SUN_S = 1191, |
| CMP_SUN_S_MMR6 = 1192, |
| CMP_UEQ_D = 1193, |
| CMP_UEQ_D_MMR6 = 1194, |
| CMP_UEQ_S = 1195, |
| CMP_UEQ_S_MMR6 = 1196, |
| CMP_ULE_D = 1197, |
| CMP_ULE_D_MMR6 = 1198, |
| CMP_ULE_S = 1199, |
| CMP_ULE_S_MMR6 = 1200, |
| CMP_ULT_D = 1201, |
| CMP_ULT_D_MMR6 = 1202, |
| CMP_ULT_S = 1203, |
| CMP_ULT_S_MMR6 = 1204, |
| CMP_UN_D = 1205, |
| CMP_UN_D_MMR6 = 1206, |
| CMP_UN_S = 1207, |
| CMP_UN_S_MMR6 = 1208, |
| COPY_S_B = 1209, |
| COPY_S_D = 1210, |
| COPY_S_H = 1211, |
| COPY_S_W = 1212, |
| COPY_U_B = 1213, |
| COPY_U_H = 1214, |
| COPY_U_W = 1215, |
| CRC32B = 1216, |
| CRC32CB = 1217, |
| CRC32CD = 1218, |
| CRC32CH = 1219, |
| CRC32CW = 1220, |
| CRC32D = 1221, |
| CRC32H = 1222, |
| CRC32W = 1223, |
| CTC1 = 1224, |
| CTC1_MM = 1225, |
| CTC2_MM = 1226, |
| CTCMSA = 1227, |
| CVT_D32_S = 1228, |
| CVT_D32_S_MM = 1229, |
| CVT_D32_W = 1230, |
| CVT_D32_W_MM = 1231, |
| CVT_D64_L = 1232, |
| CVT_D64_S = 1233, |
| CVT_D64_S_MM = 1234, |
| CVT_D64_W = 1235, |
| CVT_D64_W_MM = 1236, |
| CVT_D_L_MMR6 = 1237, |
| CVT_L_D64 = 1238, |
| CVT_L_D64_MM = 1239, |
| CVT_L_D_MMR6 = 1240, |
| CVT_L_S = 1241, |
| CVT_L_S_MM = 1242, |
| CVT_L_S_MMR6 = 1243, |
| CVT_PS_PW64 = 1244, |
| CVT_PS_S64 = 1245, |
| CVT_PW_PS64 = 1246, |
| CVT_S_D32 = 1247, |
| CVT_S_D32_MM = 1248, |
| CVT_S_D64 = 1249, |
| CVT_S_D64_MM = 1250, |
| CVT_S_L = 1251, |
| CVT_S_L_MMR6 = 1252, |
| CVT_S_PL64 = 1253, |
| CVT_S_PU64 = 1254, |
| CVT_S_W = 1255, |
| CVT_S_W_MM = 1256, |
| CVT_S_W_MMR6 = 1257, |
| CVT_W_D32 = 1258, |
| CVT_W_D32_MM = 1259, |
| CVT_W_D64 = 1260, |
| CVT_W_D64_MM = 1261, |
| CVT_W_S = 1262, |
| CVT_W_S_MM = 1263, |
| CVT_W_S_MMR6 = 1264, |
| C_EQ_D32 = 1265, |
| C_EQ_D32_MM = 1266, |
| C_EQ_D64 = 1267, |
| C_EQ_D64_MM = 1268, |
| C_EQ_S = 1269, |
| C_EQ_S_MM = 1270, |
| C_F_D32 = 1271, |
| C_F_D32_MM = 1272, |
| C_F_D64 = 1273, |
| C_F_D64_MM = 1274, |
| C_F_S = 1275, |
| C_F_S_MM = 1276, |
| C_LE_D32 = 1277, |
| C_LE_D32_MM = 1278, |
| C_LE_D64 = 1279, |
| C_LE_D64_MM = 1280, |
| C_LE_S = 1281, |
| C_LE_S_MM = 1282, |
| C_LT_D32 = 1283, |
| C_LT_D32_MM = 1284, |
| C_LT_D64 = 1285, |
| C_LT_D64_MM = 1286, |
| C_LT_S = 1287, |
| C_LT_S_MM = 1288, |
| C_NGE_D32 = 1289, |
| C_NGE_D32_MM = 1290, |
| C_NGE_D64 = 1291, |
| C_NGE_D64_MM = 1292, |
| C_NGE_S = 1293, |
| C_NGE_S_MM = 1294, |
| C_NGLE_D32 = 1295, |
| C_NGLE_D32_MM = 1296, |
| C_NGLE_D64 = 1297, |
| C_NGLE_D64_MM = 1298, |
| C_NGLE_S = 1299, |
| C_NGLE_S_MM = 1300, |
| C_NGL_D32 = 1301, |
| C_NGL_D32_MM = 1302, |
| C_NGL_D64 = 1303, |
| C_NGL_D64_MM = 1304, |
| C_NGL_S = 1305, |
| C_NGL_S_MM = 1306, |
| C_NGT_D32 = 1307, |
| C_NGT_D32_MM = 1308, |
| C_NGT_D64 = 1309, |
| C_NGT_D64_MM = 1310, |
| C_NGT_S = 1311, |
| C_NGT_S_MM = 1312, |
| C_OLE_D32 = 1313, |
| C_OLE_D32_MM = 1314, |
| C_OLE_D64 = 1315, |
| C_OLE_D64_MM = 1316, |
| C_OLE_S = 1317, |
| C_OLE_S_MM = 1318, |
| C_OLT_D32 = 1319, |
| C_OLT_D32_MM = 1320, |
| C_OLT_D64 = 1321, |
| C_OLT_D64_MM = 1322, |
| C_OLT_S = 1323, |
| C_OLT_S_MM = 1324, |
| C_SEQ_D32 = 1325, |
| C_SEQ_D32_MM = 1326, |
| C_SEQ_D64 = 1327, |
| C_SEQ_D64_MM = 1328, |
| C_SEQ_S = 1329, |
| C_SEQ_S_MM = 1330, |
| C_SF_D32 = 1331, |
| C_SF_D32_MM = 1332, |
| C_SF_D64 = 1333, |
| C_SF_D64_MM = 1334, |
| C_SF_S = 1335, |
| C_SF_S_MM = 1336, |
| C_UEQ_D32 = 1337, |
| C_UEQ_D32_MM = 1338, |
| C_UEQ_D64 = 1339, |
| C_UEQ_D64_MM = 1340, |
| C_UEQ_S = 1341, |
| C_UEQ_S_MM = 1342, |
| C_ULE_D32 = 1343, |
| C_ULE_D32_MM = 1344, |
| C_ULE_D64 = 1345, |
| C_ULE_D64_MM = 1346, |
| C_ULE_S = 1347, |
| C_ULE_S_MM = 1348, |
| C_ULT_D32 = 1349, |
| C_ULT_D32_MM = 1350, |
| C_ULT_D64 = 1351, |
| C_ULT_D64_MM = 1352, |
| C_ULT_S = 1353, |
| C_ULT_S_MM = 1354, |
| C_UN_D32 = 1355, |
| C_UN_D32_MM = 1356, |
| C_UN_D64 = 1357, |
| C_UN_D64_MM = 1358, |
| C_UN_S = 1359, |
| C_UN_S_MM = 1360, |
| CmpRxRy16 = 1361, |
| CmpiRxImm16 = 1362, |
| CmpiRxImmX16 = 1363, |
| DADD = 1364, |
| DADDi = 1365, |
| DADDiu = 1366, |
| DADDu = 1367, |
| DAHI = 1368, |
| DALIGN = 1369, |
| DATI = 1370, |
| DAUI = 1371, |
| DBITSWAP = 1372, |
| DCLO = 1373, |
| DCLO_R6 = 1374, |
| DCLZ = 1375, |
| DCLZ_R6 = 1376, |
| DDIV = 1377, |
| DDIVU = 1378, |
| DERET = 1379, |
| DERET_MM = 1380, |
| DERET_MMR6 = 1381, |
| DEXT = 1382, |
| DEXT64_32 = 1383, |
| DEXTM = 1384, |
| DEXTU = 1385, |
| DI = 1386, |
| DINS = 1387, |
| DINSM = 1388, |
| DINSU = 1389, |
| DIV = 1390, |
| DIVU = 1391, |
| DIVU_MMR6 = 1392, |
| DIV_MMR6 = 1393, |
| DIV_S_B = 1394, |
| DIV_S_D = 1395, |
| DIV_S_H = 1396, |
| DIV_S_W = 1397, |
| DIV_U_B = 1398, |
| DIV_U_D = 1399, |
| DIV_U_H = 1400, |
| DIV_U_W = 1401, |
| DI_MM = 1402, |
| DI_MMR6 = 1403, |
| DLSA = 1404, |
| DLSA_R6 = 1405, |
| DMFC0 = 1406, |
| DMFC1 = 1407, |
| DMFC2 = 1408, |
| DMFC2_OCTEON = 1409, |
| DMFGC0 = 1410, |
| DMOD = 1411, |
| DMODU = 1412, |
| DMT = 1413, |
| DMTC0 = 1414, |
| DMTC1 = 1415, |
| DMTC2 = 1416, |
| DMTC2_OCTEON = 1417, |
| DMTGC0 = 1418, |
| DMUH = 1419, |
| DMUHU = 1420, |
| DMUL = 1421, |
| DMULT = 1422, |
| DMULTu = 1423, |
| DMULU = 1424, |
| DMUL_R6 = 1425, |
| DOTP_S_D = 1426, |
| DOTP_S_H = 1427, |
| DOTP_S_W = 1428, |
| DOTP_U_D = 1429, |
| DOTP_U_H = 1430, |
| DOTP_U_W = 1431, |
| DPADD_S_D = 1432, |
| DPADD_S_H = 1433, |
| DPADD_S_W = 1434, |
| DPADD_U_D = 1435, |
| DPADD_U_H = 1436, |
| DPADD_U_W = 1437, |
| DPAQX_SA_W_PH = 1438, |
| DPAQX_SA_W_PH_MMR2 = 1439, |
| DPAQX_S_W_PH = 1440, |
| DPAQX_S_W_PH_MMR2 = 1441, |
| DPAQ_SA_L_W = 1442, |
| DPAQ_SA_L_W_MM = 1443, |
| DPAQ_S_W_PH = 1444, |
| DPAQ_S_W_PH_MM = 1445, |
| DPAU_H_QBL = 1446, |
| DPAU_H_QBL_MM = 1447, |
| DPAU_H_QBR = 1448, |
| DPAU_H_QBR_MM = 1449, |
| DPAX_W_PH = 1450, |
| DPAX_W_PH_MMR2 = 1451, |
| DPA_W_PH = 1452, |
| DPA_W_PH_MMR2 = 1453, |
| DPOP = 1454, |
| DPSQX_SA_W_PH = 1455, |
| DPSQX_SA_W_PH_MMR2 = 1456, |
| DPSQX_S_W_PH = 1457, |
| DPSQX_S_W_PH_MMR2 = 1458, |
| DPSQ_SA_L_W = 1459, |
| DPSQ_SA_L_W_MM = 1460, |
| DPSQ_S_W_PH = 1461, |
| DPSQ_S_W_PH_MM = 1462, |
| DPSUB_S_D = 1463, |
| DPSUB_S_H = 1464, |
| DPSUB_S_W = 1465, |
| DPSUB_U_D = 1466, |
| DPSUB_U_H = 1467, |
| DPSUB_U_W = 1468, |
| DPSU_H_QBL = 1469, |
| DPSU_H_QBL_MM = 1470, |
| DPSU_H_QBR = 1471, |
| DPSU_H_QBR_MM = 1472, |
| DPSX_W_PH = 1473, |
| DPSX_W_PH_MMR2 = 1474, |
| DPS_W_PH = 1475, |
| DPS_W_PH_MMR2 = 1476, |
| DROTR = 1477, |
| DROTR32 = 1478, |
| DROTRV = 1479, |
| DSBH = 1480, |
| DSDIV = 1481, |
| DSHD = 1482, |
| DSLL = 1483, |
| DSLL32 = 1484, |
| DSLL64_32 = 1485, |
| DSLLV = 1486, |
| DSRA = 1487, |
| DSRA32 = 1488, |
| DSRAV = 1489, |
| DSRL = 1490, |
| DSRL32 = 1491, |
| DSRLV = 1492, |
| DSUB = 1493, |
| DSUBu = 1494, |
| DUDIV = 1495, |
| DVP = 1496, |
| DVPE = 1497, |
| DVP_MMR6 = 1498, |
| DivRxRy16 = 1499, |
| DivuRxRy16 = 1500, |
| EHB = 1501, |
| EHB_MM = 1502, |
| EHB_MMR6 = 1503, |
| EI = 1504, |
| EI_MM = 1505, |
| EI_MMR6 = 1506, |
| EMT = 1507, |
| ERET = 1508, |
| ERETNC = 1509, |
| ERETNC_MMR6 = 1510, |
| ERET_MM = 1511, |
| ERET_MMR6 = 1512, |
| EVP = 1513, |
| EVPE = 1514, |
| EVP_MMR6 = 1515, |
| EXT = 1516, |
| EXTP = 1517, |
| EXTPDP = 1518, |
| EXTPDPV = 1519, |
| EXTPDPV_MM = 1520, |
| EXTPDP_MM = 1521, |
| EXTPV = 1522, |
| EXTPV_MM = 1523, |
| EXTP_MM = 1524, |
| EXTRV_RS_W = 1525, |
| EXTRV_RS_W_MM = 1526, |
| EXTRV_R_W = 1527, |
| EXTRV_R_W_MM = 1528, |
| EXTRV_S_H = 1529, |
| EXTRV_S_H_MM = 1530, |
| EXTRV_W = 1531, |
| EXTRV_W_MM = 1532, |
| EXTR_RS_W = 1533, |
| EXTR_RS_W_MM = 1534, |
| EXTR_R_W = 1535, |
| EXTR_R_W_MM = 1536, |
| EXTR_S_H = 1537, |
| EXTR_S_H_MM = 1538, |
| EXTR_W = 1539, |
| EXTR_W_MM = 1540, |
| EXTS = 1541, |
| EXTS32 = 1542, |
| EXT_MM = 1543, |
| EXT_MMR6 = 1544, |
| FABS_D32 = 1545, |
| FABS_D32_MM = 1546, |
| FABS_D64 = 1547, |
| FABS_D64_MM = 1548, |
| FABS_S = 1549, |
| FABS_S_MM = 1550, |
| FADD_D = 1551, |
| FADD_D32 = 1552, |
| FADD_D32_MM = 1553, |
| FADD_D64 = 1554, |
| FADD_D64_MM = 1555, |
| FADD_PS64 = 1556, |
| FADD_S = 1557, |
| FADD_S_MM = 1558, |
| FADD_S_MMR6 = 1559, |
| FADD_W = 1560, |
| FCAF_D = 1561, |
| FCAF_W = 1562, |
| FCEQ_D = 1563, |
| FCEQ_W = 1564, |
| FCLASS_D = 1565, |
| FCLASS_W = 1566, |
| FCLE_D = 1567, |
| FCLE_W = 1568, |
| FCLT_D = 1569, |
| FCLT_W = 1570, |
| FCMP_D32 = 1571, |
| FCMP_D32_MM = 1572, |
| FCMP_D64 = 1573, |
| FCMP_S32 = 1574, |
| FCMP_S32_MM = 1575, |
| FCNE_D = 1576, |
| FCNE_W = 1577, |
| FCOR_D = 1578, |
| FCOR_W = 1579, |
| FCUEQ_D = 1580, |
| FCUEQ_W = 1581, |
| FCULE_D = 1582, |
| FCULE_W = 1583, |
| FCULT_D = 1584, |
| FCULT_W = 1585, |
| FCUNE_D = 1586, |
| FCUNE_W = 1587, |
| FCUN_D = 1588, |
| FCUN_W = 1589, |
| FDIV_D = 1590, |
| FDIV_D32 = 1591, |
| FDIV_D32_MM = 1592, |
| FDIV_D64 = 1593, |
| FDIV_D64_MM = 1594, |
| FDIV_S = 1595, |
| FDIV_S_MM = 1596, |
| FDIV_S_MMR6 = 1597, |
| FDIV_W = 1598, |
| FEXDO_H = 1599, |
| FEXDO_W = 1600, |
| FEXP2_D = 1601, |
| FEXP2_W = 1602, |
| FEXUPL_D = 1603, |
| FEXUPL_W = 1604, |
| FEXUPR_D = 1605, |
| FEXUPR_W = 1606, |
| FFINT_S_D = 1607, |
| FFINT_S_W = 1608, |
| FFINT_U_D = 1609, |
| FFINT_U_W = 1610, |
| FFQL_D = 1611, |
| FFQL_W = 1612, |
| FFQR_D = 1613, |
| FFQR_W = 1614, |
| FILL_B = 1615, |
| FILL_D = 1616, |
| FILL_H = 1617, |
| FILL_W = 1618, |
| FLOG2_D = 1619, |
| FLOG2_W = 1620, |
| FLOOR_L_D64 = 1621, |
| FLOOR_L_D_MMR6 = 1622, |
| FLOOR_L_S = 1623, |
| FLOOR_L_S_MMR6 = 1624, |
| FLOOR_W_D32 = 1625, |
| FLOOR_W_D64 = 1626, |
| FLOOR_W_D_MMR6 = 1627, |
| FLOOR_W_MM = 1628, |
| FLOOR_W_S = 1629, |
| FLOOR_W_S_MM = 1630, |
| FLOOR_W_S_MMR6 = 1631, |
| FMADD_D = 1632, |
| FMADD_W = 1633, |
| FMAX_A_D = 1634, |
| FMAX_A_W = 1635, |
| FMAX_D = 1636, |
| FMAX_W = 1637, |
| FMIN_A_D = 1638, |
| FMIN_A_W = 1639, |
| FMIN_D = 1640, |
| FMIN_W = 1641, |
| FMOV_D32 = 1642, |
| FMOV_D32_MM = 1643, |
| FMOV_D64 = 1644, |
| FMOV_D64_MM = 1645, |
| FMOV_D_MMR6 = 1646, |
| FMOV_S = 1647, |
| FMOV_S_MM = 1648, |
| FMOV_S_MMR6 = 1649, |
| FMSUB_D = 1650, |
| FMSUB_W = 1651, |
| FMUL_D = 1652, |
| FMUL_D32 = 1653, |
| FMUL_D32_MM = 1654, |
| FMUL_D64 = 1655, |
| FMUL_D64_MM = 1656, |
| FMUL_PS64 = 1657, |
| FMUL_S = 1658, |
| FMUL_S_MM = 1659, |
| FMUL_S_MMR6 = 1660, |
| FMUL_W = 1661, |
| FNEG_D32 = 1662, |
| FNEG_D32_MM = 1663, |
| FNEG_D64 = 1664, |
| FNEG_D64_MM = 1665, |
| FNEG_S = 1666, |
| FNEG_S_MM = 1667, |
| FNEG_S_MMR6 = 1668, |
| FORK = 1669, |
| FRCP_D = 1670, |
| FRCP_W = 1671, |
| FRINT_D = 1672, |
| FRINT_W = 1673, |
| FRSQRT_D = 1674, |
| FRSQRT_W = 1675, |
| FSAF_D = 1676, |
| FSAF_W = 1677, |
| FSEQ_D = 1678, |
| FSEQ_W = 1679, |
| FSLE_D = 1680, |
| FSLE_W = 1681, |
| FSLT_D = 1682, |
| FSLT_W = 1683, |
| FSNE_D = 1684, |
| FSNE_W = 1685, |
| FSOR_D = 1686, |
| FSOR_W = 1687, |
| FSQRT_D = 1688, |
| FSQRT_D32 = 1689, |
| FSQRT_D32_MM = 1690, |
| FSQRT_D64 = 1691, |
| FSQRT_D64_MM = 1692, |
| FSQRT_S = 1693, |
| FSQRT_S_MM = 1694, |
| FSQRT_W = 1695, |
| FSUB_D = 1696, |
| FSUB_D32 = 1697, |
| FSUB_D32_MM = 1698, |
| FSUB_D64 = 1699, |
| FSUB_D64_MM = 1700, |
| FSUB_PS64 = 1701, |
| FSUB_S = 1702, |
| FSUB_S_MM = 1703, |
| FSUB_S_MMR6 = 1704, |
| FSUB_W = 1705, |
| FSUEQ_D = 1706, |
| FSUEQ_W = 1707, |
| FSULE_D = 1708, |
| FSULE_W = 1709, |
| FSULT_D = 1710, |
| FSULT_W = 1711, |
| FSUNE_D = 1712, |
| FSUNE_W = 1713, |
| FSUN_D = 1714, |
| FSUN_W = 1715, |
| FTINT_S_D = 1716, |
| FTINT_S_W = 1717, |
| FTINT_U_D = 1718, |
| FTINT_U_W = 1719, |
| FTQ_H = 1720, |
| FTQ_W = 1721, |
| FTRUNC_S_D = 1722, |
| FTRUNC_S_W = 1723, |
| FTRUNC_U_D = 1724, |
| FTRUNC_U_W = 1725, |
| GINVI = 1726, |
| GINVI_MMR6 = 1727, |
| GINVT = 1728, |
| GINVT_MMR6 = 1729, |
| HADD_S_D = 1730, |
| HADD_S_H = 1731, |
| HADD_S_W = 1732, |
| HADD_U_D = 1733, |
| HADD_U_H = 1734, |
| HADD_U_W = 1735, |
| HSUB_S_D = 1736, |
| HSUB_S_H = 1737, |
| HSUB_S_W = 1738, |
| HSUB_U_D = 1739, |
| HSUB_U_H = 1740, |
| HSUB_U_W = 1741, |
| HYPCALL = 1742, |
| HYPCALL_MM = 1743, |
| ILVEV_B = 1744, |
| ILVEV_D = 1745, |
| ILVEV_H = 1746, |
| ILVEV_W = 1747, |
| ILVL_B = 1748, |
| ILVL_D = 1749, |
| ILVL_H = 1750, |
| ILVL_W = 1751, |
| ILVOD_B = 1752, |
| ILVOD_D = 1753, |
| ILVOD_H = 1754, |
| ILVOD_W = 1755, |
| ILVR_B = 1756, |
| ILVR_D = 1757, |
| ILVR_H = 1758, |
| ILVR_W = 1759, |
| INS = 1760, |
| INSERT_B = 1761, |
| INSERT_D = 1762, |
| INSERT_H = 1763, |
| INSERT_W = 1764, |
| INSV = 1765, |
| INSVE_B = 1766, |
| INSVE_D = 1767, |
| INSVE_H = 1768, |
| INSVE_W = 1769, |
| INSV_MM = 1770, |
| INS_MM = 1771, |
| INS_MMR6 = 1772, |
| J = 1773, |
| JAL = 1774, |
| JALR = 1775, |
| JALR16_MM = 1776, |
| JALR64 = 1777, |
| JALRC16_MMR6 = 1778, |
| JALRC_HB_MMR6 = 1779, |
| JALRC_MMR6 = 1780, |
| JALRS16_MM = 1781, |
| JALRS_MM = 1782, |
| JALR_HB = 1783, |
| JALR_HB64 = 1784, |
| JALR_MM = 1785, |
| JALS_MM = 1786, |
| JALX = 1787, |
| JALX_MM = 1788, |
| JAL_MM = 1789, |
| JIALC = 1790, |
| JIALC64 = 1791, |
| JIALC_MMR6 = 1792, |
| JIC = 1793, |
| JIC64 = 1794, |
| JIC_MMR6 = 1795, |
| JR = 1796, |
| JR16_MM = 1797, |
| JR64 = 1798, |
| JRADDIUSP = 1799, |
| JRC16_MM = 1800, |
| JRC16_MMR6 = 1801, |
| JRCADDIUSP_MMR6 = 1802, |
| JR_HB = 1803, |
| JR_HB64 = 1804, |
| JR_HB64_R6 = 1805, |
| JR_HB_R6 = 1806, |
| JR_MM = 1807, |
| J_MM = 1808, |
| Jal16 = 1809, |
| JalB16 = 1810, |
| JrRa16 = 1811, |
| JrcRa16 = 1812, |
| JrcRx16 = 1813, |
| JumpLinkReg16 = 1814, |
| LB = 1815, |
| LB64 = 1816, |
| LBE = 1817, |
| LBE_MM = 1818, |
| LBU16_MM = 1819, |
| LBUX = 1820, |
| LBUX_MM = 1821, |
| LBU_MMR6 = 1822, |
| LB_MM = 1823, |
| LB_MMR6 = 1824, |
| LBu = 1825, |
| LBu64 = 1826, |
| LBuE = 1827, |
| LBuE_MM = 1828, |
| LBu_MM = 1829, |
| LD = 1830, |
| LDC1 = 1831, |
| LDC164 = 1832, |
| LDC1_D64_MMR6 = 1833, |
| LDC1_MM_D32 = 1834, |
| LDC1_MM_D64 = 1835, |
| LDC2 = 1836, |
| LDC2_MMR6 = 1837, |
| LDC2_R6 = 1838, |
| LDC3 = 1839, |
| LDI_B = 1840, |
| LDI_D = 1841, |
| LDI_H = 1842, |
| LDI_W = 1843, |
| LDL = 1844, |
| LDPC = 1845, |
| LDR = 1846, |
| LDXC1 = 1847, |
| LDXC164 = 1848, |
| LD_B = 1849, |
| LD_D = 1850, |
| LD_H = 1851, |
| LD_W = 1852, |
| LEA_ADDiu = 1853, |
| LEA_ADDiu64 = 1854, |
| LEA_ADDiu_MM = 1855, |
| LH = 1856, |
| LH64 = 1857, |
| LHE = 1858, |
| LHE_MM = 1859, |
| LHU16_MM = 1860, |
| LHX = 1861, |
| LHX_MM = 1862, |
| LH_MM = 1863, |
| LHu = 1864, |
| LHu64 = 1865, |
| LHuE = 1866, |
| LHuE_MM = 1867, |
| LHu_MM = 1868, |
| LI16_MM = 1869, |
| LI16_MMR6 = 1870, |
| LL = 1871, |
| LL64 = 1872, |
| LL64_R6 = 1873, |
| LLD = 1874, |
| LLD_R6 = 1875, |
| LLE = 1876, |
| LLE_MM = 1877, |
| LL_MM = 1878, |
| LL_MMR6 = 1879, |
| LL_R6 = 1880, |
| LSA = 1881, |
| LSA_MMR6 = 1882, |
| LSA_R6 = 1883, |
| LUI_MMR6 = 1884, |
| LUXC1 = 1885, |
| LUXC164 = 1886, |
| LUXC1_MM = 1887, |
| LUi = 1888, |
| LUi64 = 1889, |
| LUi_MM = 1890, |
| LW = 1891, |
| LW16_MM = 1892, |
| LW64 = 1893, |
| LWC1 = 1894, |
| LWC1_MM = 1895, |
| LWC2 = 1896, |
| LWC2_MMR6 = 1897, |
| LWC2_R6 = 1898, |
| LWC3 = 1899, |
| LWDSP = 1900, |
| LWDSP_MM = 1901, |
| LWE = 1902, |
| LWE_MM = 1903, |
| LWGP_MM = 1904, |
| LWL = 1905, |
| LWL64 = 1906, |
| LWLE = 1907, |
| LWLE_MM = 1908, |
| LWL_MM = 1909, |
| LWM16_MM = 1910, |
| LWM16_MMR6 = 1911, |
| LWM32_MM = 1912, |
| LWPC = 1913, |
| LWPC_MMR6 = 1914, |
| LWP_MM = 1915, |
| LWR = 1916, |
| LWR64 = 1917, |
| LWRE = 1918, |
| LWRE_MM = 1919, |
| LWR_MM = 1920, |
| LWSP_MM = 1921, |
| LWUPC = 1922, |
| LWU_MM = 1923, |
| LWX = 1924, |
| LWXC1 = 1925, |
| LWXC1_MM = 1926, |
| LWXS_MM = 1927, |
| LWX_MM = 1928, |
| LW_MM = 1929, |
| LW_MMR6 = 1930, |
| LWu = 1931, |
| LbRxRyOffMemX16 = 1932, |
| LbuRxRyOffMemX16 = 1933, |
| LhRxRyOffMemX16 = 1934, |
| LhuRxRyOffMemX16 = 1935, |
| LiRxImm16 = 1936, |
| LiRxImmAlignX16 = 1937, |
| LiRxImmX16 = 1938, |
| LwRxPcTcp16 = 1939, |
| LwRxPcTcpX16 = 1940, |
| LwRxRyOffMemX16 = 1941, |
| LwRxSpImmX16 = 1942, |
| MADD = 1943, |
| MADDF_D = 1944, |
| MADDF_D_MMR6 = 1945, |
| MADDF_S = 1946, |
| MADDF_S_MMR6 = 1947, |
| MADDR_Q_H = 1948, |
| MADDR_Q_W = 1949, |
| MADDU = 1950, |
| MADDU_DSP = 1951, |
| MADDU_DSP_MM = 1952, |
| MADDU_MM = 1953, |
| MADDV_B = 1954, |
| MADDV_D = 1955, |
| MADDV_H = 1956, |
| MADDV_W = 1957, |
| MADD_D32 = 1958, |
| MADD_D32_MM = 1959, |
| MADD_D64 = 1960, |
| MADD_DSP = 1961, |
| MADD_DSP_MM = 1962, |
| MADD_MM = 1963, |
| MADD_Q_H = 1964, |
| MADD_Q_W = 1965, |
| MADD_S = 1966, |
| MADD_S_MM = 1967, |
| MAQ_SA_W_PHL = 1968, |
| MAQ_SA_W_PHL_MM = 1969, |
| MAQ_SA_W_PHR = 1970, |
| MAQ_SA_W_PHR_MM = 1971, |
| MAQ_S_W_PHL = 1972, |
| MAQ_S_W_PHL_MM = 1973, |
| MAQ_S_W_PHR = 1974, |
| MAQ_S_W_PHR_MM = 1975, |
| MAXA_D = 1976, |
| MAXA_D_MMR6 = 1977, |
| MAXA_S = 1978, |
| MAXA_S_MMR6 = 1979, |
| MAXI_S_B = 1980, |
| MAXI_S_D = 1981, |
| MAXI_S_H = 1982, |
| MAXI_S_W = 1983, |
| MAXI_U_B = 1984, |
| MAXI_U_D = 1985, |
| MAXI_U_H = 1986, |
| MAXI_U_W = 1987, |
| MAX_A_B = 1988, |
| MAX_A_D = 1989, |
| MAX_A_H = 1990, |
| MAX_A_W = 1991, |
| MAX_D = 1992, |
| MAX_D_MMR6 = 1993, |
| MAX_S = 1994, |
| MAX_S_B = 1995, |
| MAX_S_D = 1996, |
| MAX_S_H = 1997, |
| MAX_S_MMR6 = 1998, |
| MAX_S_W = 1999, |
| MAX_U_B = 2000, |
| MAX_U_D = 2001, |
| MAX_U_H = 2002, |
| MAX_U_W = 2003, |
| MFC0 = 2004, |
| MFC0_MMR6 = 2005, |
| MFC1 = 2006, |
| MFC1_D64 = 2007, |
| MFC1_MM = 2008, |
| MFC1_MMR6 = 2009, |
| MFC2 = 2010, |
| MFC2_MMR6 = 2011, |
| MFGC0 = 2012, |
| MFGC0_MM = 2013, |
| MFHC0_MMR6 = 2014, |
| MFHC1_D32 = 2015, |
| MFHC1_D32_MM = 2016, |
| MFHC1_D64 = 2017, |
| MFHC1_D64_MM = 2018, |
| MFHC2_MMR6 = 2019, |
| MFHGC0 = 2020, |
| MFHGC0_MM = 2021, |
| MFHI = 2022, |
| MFHI16_MM = 2023, |
| MFHI64 = 2024, |
| MFHI_DSP = 2025, |
| MFHI_DSP_MM = 2026, |
| MFHI_MM = 2027, |
| MFLO = 2028, |
| MFLO16_MM = 2029, |
| MFLO64 = 2030, |
| MFLO_DSP = 2031, |
| MFLO_DSP_MM = 2032, |
| MFLO_MM = 2033, |
| MFTR = 2034, |
| MINA_D = 2035, |
| MINA_D_MMR6 = 2036, |
| MINA_S = 2037, |
| MINA_S_MMR6 = 2038, |
| MINI_S_B = 2039, |
| MINI_S_D = 2040, |
| MINI_S_H = 2041, |
| MINI_S_W = 2042, |
| MINI_U_B = 2043, |
| MINI_U_D = 2044, |
| MINI_U_H = 2045, |
| MINI_U_W = 2046, |
| MIN_A_B = 2047, |
| MIN_A_D = 2048, |
| MIN_A_H = 2049, |
| MIN_A_W = 2050, |
| MIN_D = 2051, |
| MIN_D_MMR6 = 2052, |
| MIN_S = 2053, |
| MIN_S_B = 2054, |
| MIN_S_D = 2055, |
| MIN_S_H = 2056, |
| MIN_S_MMR6 = 2057, |
| MIN_S_W = 2058, |
| MIN_U_B = 2059, |
| MIN_U_D = 2060, |
| MIN_U_H = 2061, |
| MIN_U_W = 2062, |
| MOD = 2063, |
| MODSUB = 2064, |
| MODSUB_MM = 2065, |
| MODU = 2066, |
| MODU_MMR6 = 2067, |
| MOD_MMR6 = 2068, |
| MOD_S_B = 2069, |
| MOD_S_D = 2070, |
| MOD_S_H = 2071, |
| MOD_S_W = 2072, |
| MOD_U_B = 2073, |
| MOD_U_D = 2074, |
| MOD_U_H = 2075, |
| MOD_U_W = 2076, |
| MOVE16_MM = 2077, |
| MOVE16_MMR6 = 2078, |
| MOVEP_MM = 2079, |
| MOVEP_MMR6 = 2080, |
| MOVE_V = 2081, |
| MOVF_D32 = 2082, |
| MOVF_D32_MM = 2083, |
| MOVF_D64 = 2084, |
| MOVF_I = 2085, |
| MOVF_I64 = 2086, |
| MOVF_I_MM = 2087, |
| MOVF_S = 2088, |
| MOVF_S_MM = 2089, |
| MOVN_I64_D64 = 2090, |
| MOVN_I64_I = 2091, |
| MOVN_I64_I64 = 2092, |
| MOVN_I64_S = 2093, |
| MOVN_I_D32 = 2094, |
| MOVN_I_D32_MM = 2095, |
| MOVN_I_D64 = 2096, |
| MOVN_I_I = 2097, |
| MOVN_I_I64 = 2098, |
| MOVN_I_MM = 2099, |
| MOVN_I_S = 2100, |
| MOVN_I_S_MM = 2101, |
| MOVT_D32 = 2102, |
| MOVT_D32_MM = 2103, |
| MOVT_D64 = 2104, |
| MOVT_I = 2105, |
| MOVT_I64 = 2106, |
| MOVT_I_MM = 2107, |
| MOVT_S = 2108, |
| MOVT_S_MM = 2109, |
| MOVZ_I64_D64 = 2110, |
| MOVZ_I64_I = 2111, |
| MOVZ_I64_I64 = 2112, |
| MOVZ_I64_S = 2113, |
| MOVZ_I_D32 = 2114, |
| MOVZ_I_D32_MM = 2115, |
| MOVZ_I_D64 = 2116, |
| MOVZ_I_I = 2117, |
| MOVZ_I_I64 = 2118, |
| MOVZ_I_MM = 2119, |
| MOVZ_I_S = 2120, |
| MOVZ_I_S_MM = 2121, |
| MSUB = 2122, |
| MSUBF_D = 2123, |
| MSUBF_D_MMR6 = 2124, |
| MSUBF_S = 2125, |
| MSUBF_S_MMR6 = 2126, |
| MSUBR_Q_H = 2127, |
| MSUBR_Q_W = 2128, |
| MSUBU = 2129, |
| MSUBU_DSP = 2130, |
| MSUBU_DSP_MM = 2131, |
| MSUBU_MM = 2132, |
| MSUBV_B = 2133, |
| MSUBV_D = 2134, |
| MSUBV_H = 2135, |
| MSUBV_W = 2136, |
| MSUB_D32 = 2137, |
| MSUB_D32_MM = 2138, |
| MSUB_D64 = 2139, |
| MSUB_DSP = 2140, |
| MSUB_DSP_MM = 2141, |
| MSUB_MM = 2142, |
| MSUB_Q_H = 2143, |
| MSUB_Q_W = 2144, |
| MSUB_S = 2145, |
| MSUB_S_MM = 2146, |
| MTC0 = 2147, |
| MTC0_MMR6 = 2148, |
| MTC1 = 2149, |
| MTC1_D64 = 2150, |
| MTC1_D64_MM = 2151, |
| MTC1_MM = 2152, |
| MTC1_MMR6 = 2153, |
| MTC2 = 2154, |
| MTC2_MMR6 = 2155, |
| MTGC0 = 2156, |
| MTGC0_MM = 2157, |
| MTHC0_MMR6 = 2158, |
| MTHC1_D32 = 2159, |
| MTHC1_D32_MM = 2160, |
| MTHC1_D64 = 2161, |
| MTHC1_D64_MM = 2162, |
| MTHC2_MMR6 = 2163, |
| MTHGC0 = 2164, |
| MTHGC0_MM = 2165, |
| MTHI = 2166, |
| MTHI64 = 2167, |
| MTHI_DSP = 2168, |
| MTHI_DSP_MM = 2169, |
| MTHI_MM = 2170, |
| MTHLIP = 2171, |
| MTHLIP_MM = 2172, |
| MTLO = 2173, |
| MTLO64 = 2174, |
| MTLO_DSP = 2175, |
| MTLO_DSP_MM = 2176, |
| MTLO_MM = 2177, |
| MTM0 = 2178, |
| MTM1 = 2179, |
| MTM2 = 2180, |
| MTP0 = 2181, |
| MTP1 = 2182, |
| MTP2 = 2183, |
| MTTR = 2184, |
| MUH = 2185, |
| MUHU = 2186, |
| MUHU_MMR6 = 2187, |
| MUH_MMR6 = 2188, |
| MUL = 2189, |
| MULEQ_S_W_PHL = 2190, |
| MULEQ_S_W_PHL_MM = 2191, |
| MULEQ_S_W_PHR = 2192, |
| MULEQ_S_W_PHR_MM = 2193, |
| MULEU_S_PH_QBL = 2194, |
| MULEU_S_PH_QBL_MM = 2195, |
| MULEU_S_PH_QBR = 2196, |
| MULEU_S_PH_QBR_MM = 2197, |
| MULQ_RS_PH = 2198, |
| MULQ_RS_PH_MM = 2199, |
| MULQ_RS_W = 2200, |
| MULQ_RS_W_MMR2 = 2201, |
| MULQ_S_PH = 2202, |
| MULQ_S_PH_MMR2 = 2203, |
| MULQ_S_W = 2204, |
| MULQ_S_W_MMR2 = 2205, |
| MULR_PS64 = 2206, |
| MULR_Q_H = 2207, |
| MULR_Q_W = 2208, |
| MULSAQ_S_W_PH = 2209, |
| MULSAQ_S_W_PH_MM = 2210, |
| MULSA_W_PH = 2211, |
| MULSA_W_PH_MMR2 = 2212, |
| MULT = 2213, |
| MULTU_DSP = 2214, |
| MULTU_DSP_MM = 2215, |
| MULT_DSP = 2216, |
| MULT_DSP_MM = 2217, |
| MULT_MM = 2218, |
| MULTu = 2219, |
| MULTu_MM = 2220, |
| MULU = 2221, |
| MULU_MMR6 = 2222, |
| MULV_B = 2223, |
| MULV_D = 2224, |
| MULV_H = 2225, |
| MULV_W = 2226, |
| MUL_MM = 2227, |
| MUL_MMR6 = 2228, |
| MUL_PH = 2229, |
| MUL_PH_MMR2 = 2230, |
| MUL_Q_H = 2231, |
| MUL_Q_W = 2232, |
| MUL_R6 = 2233, |
| MUL_S_PH = 2234, |
| MUL_S_PH_MMR2 = 2235, |
| Mfhi16 = 2236, |
| Mflo16 = 2237, |
| Move32R16 = 2238, |
| MoveR3216 = 2239, |
| NLOC_B = 2240, |
| NLOC_D = 2241, |
| NLOC_H = 2242, |
| NLOC_W = 2243, |
| NLZC_B = 2244, |
| NLZC_D = 2245, |
| NLZC_H = 2246, |
| NLZC_W = 2247, |
| NMADD_D32 = 2248, |
| NMADD_D32_MM = 2249, |
| NMADD_D64 = 2250, |
| NMADD_S = 2251, |
| NMADD_S_MM = 2252, |
| NMSUB_D32 = 2253, |
| NMSUB_D32_MM = 2254, |
| NMSUB_D64 = 2255, |
| NMSUB_S = 2256, |
| NMSUB_S_MM = 2257, |
| NOR = 2258, |
| NOR64 = 2259, |
| NORI_B = 2260, |
| NOR_MM = 2261, |
| NOR_MMR6 = 2262, |
| NOR_V = 2263, |
| NOT16_MM = 2264, |
| NOT16_MMR6 = 2265, |
| NegRxRy16 = 2266, |
| NotRxRy16 = 2267, |
| OR = 2268, |
| OR16_MM = 2269, |
| OR16_MMR6 = 2270, |
| OR64 = 2271, |
| ORI_B = 2272, |
| ORI_MMR6 = 2273, |
| OR_MM = 2274, |
| OR_MMR6 = 2275, |
| OR_V = 2276, |
| ORi = 2277, |
| ORi64 = 2278, |
| ORi_MM = 2279, |
| OrRxRxRy16 = 2280, |
| PACKRL_PH = 2281, |
| PACKRL_PH_MM = 2282, |
| PAUSE = 2283, |
| PAUSE_MM = 2284, |
| PAUSE_MMR6 = 2285, |
| PCKEV_B = 2286, |
| PCKEV_D = 2287, |
| PCKEV_H = 2288, |
| PCKEV_W = 2289, |
| PCKOD_B = 2290, |
| PCKOD_D = 2291, |
| PCKOD_H = 2292, |
| PCKOD_W = 2293, |
| PCNT_B = 2294, |
| PCNT_D = 2295, |
| PCNT_H = 2296, |
| PCNT_W = 2297, |
| PICK_PH = 2298, |
| PICK_PH_MM = 2299, |
| PICK_QB = 2300, |
| PICK_QB_MM = 2301, |
| PLL_PS64 = 2302, |
| PLU_PS64 = 2303, |
| POP = 2304, |
| PRECEQU_PH_QBL = 2305, |
| PRECEQU_PH_QBLA = 2306, |
| PRECEQU_PH_QBLA_MM = 2307, |
| PRECEQU_PH_QBL_MM = 2308, |
| PRECEQU_PH_QBR = 2309, |
| PRECEQU_PH_QBRA = 2310, |
| PRECEQU_PH_QBRA_MM = 2311, |
| PRECEQU_PH_QBR_MM = 2312, |
| PRECEQ_W_PHL = 2313, |
| PRECEQ_W_PHL_MM = 2314, |
| PRECEQ_W_PHR = 2315, |
| PRECEQ_W_PHR_MM = 2316, |
| PRECEU_PH_QBL = 2317, |
| PRECEU_PH_QBLA = 2318, |
| PRECEU_PH_QBLA_MM = 2319, |
| PRECEU_PH_QBL_MM = 2320, |
| PRECEU_PH_QBR = 2321, |
| PRECEU_PH_QBRA = 2322, |
| PRECEU_PH_QBRA_MM = 2323, |
| PRECEU_PH_QBR_MM = 2324, |
| PRECRQU_S_QB_PH = 2325, |
| PRECRQU_S_QB_PH_MM = 2326, |
| PRECRQ_PH_W = 2327, |
| PRECRQ_PH_W_MM = 2328, |
| PRECRQ_QB_PH = 2329, |
| PRECRQ_QB_PH_MM = 2330, |
| PRECRQ_RS_PH_W = 2331, |
| PRECRQ_RS_PH_W_MM = 2332, |
| PRECR_QB_PH = 2333, |
| PRECR_QB_PH_MMR2 = 2334, |
| PRECR_SRA_PH_W = 2335, |
| PRECR_SRA_PH_W_MMR2 = 2336, |
| PRECR_SRA_R_PH_W = 2337, |
| PRECR_SRA_R_PH_W_MMR2 = 2338, |
| PREF = 2339, |
| PREFE = 2340, |
| PREFE_MM = 2341, |
| PREFX_MM = 2342, |
| PREF_MM = 2343, |
| PREF_MMR6 = 2344, |
| PREF_R6 = 2345, |
| PREPEND = 2346, |
| PREPEND_MMR2 = 2347, |
| PUL_PS64 = 2348, |
| PUU_PS64 = 2349, |
| RADDU_W_QB = 2350, |
| RADDU_W_QB_MM = 2351, |
| RDDSP = 2352, |
| RDDSP_MM = 2353, |
| RDHWR = 2354, |
| RDHWR64 = 2355, |
| RDHWR_MM = 2356, |
| RDHWR_MMR6 = 2357, |
| RDPGPR_MMR6 = 2358, |
| RECIP_D32 = 2359, |
| RECIP_D32_MM = 2360, |
| RECIP_D64 = 2361, |
| RECIP_D64_MM = 2362, |
| RECIP_S = 2363, |
| RECIP_S_MM = 2364, |
| REPLV_PH = 2365, |
| REPLV_PH_MM = 2366, |
| REPLV_QB = 2367, |
| REPLV_QB_MM = 2368, |
| REPL_PH = 2369, |
| REPL_PH_MM = 2370, |
| REPL_QB = 2371, |
| REPL_QB_MM = 2372, |
| RINT_D = 2373, |
| RINT_D_MMR6 = 2374, |
| RINT_S = 2375, |
| RINT_S_MMR6 = 2376, |
| ROTR = 2377, |
| ROTRV = 2378, |
| ROTRV_MM = 2379, |
| ROTR_MM = 2380, |
| ROUND_L_D64 = 2381, |
| ROUND_L_D_MMR6 = 2382, |
| ROUND_L_S = 2383, |
| ROUND_L_S_MMR6 = 2384, |
| ROUND_W_D32 = 2385, |
| ROUND_W_D64 = 2386, |
| ROUND_W_D_MMR6 = 2387, |
| ROUND_W_MM = 2388, |
| ROUND_W_S = 2389, |
| ROUND_W_S_MM = 2390, |
| ROUND_W_S_MMR6 = 2391, |
| RSQRT_D32 = 2392, |
| RSQRT_D32_MM = 2393, |
| RSQRT_D64 = 2394, |
| RSQRT_D64_MM = 2395, |
| RSQRT_S = 2396, |
| RSQRT_S_MM = 2397, |
| Restore16 = 2398, |
| RestoreX16 = 2399, |
| SAA = 2400, |
| SAAD = 2401, |
| SAT_S_B = 2402, |
| SAT_S_D = 2403, |
| SAT_S_H = 2404, |
| SAT_S_W = 2405, |
| SAT_U_B = 2406, |
| SAT_U_D = 2407, |
| SAT_U_H = 2408, |
| SAT_U_W = 2409, |
| SB = 2410, |
| SB16_MM = 2411, |
| SB16_MMR6 = 2412, |
| SB64 = 2413, |
| SBE = 2414, |
| SBE_MM = 2415, |
| SB_MM = 2416, |
| SB_MMR6 = 2417, |
| SC = 2418, |
| SC64 = 2419, |
| SC64_R6 = 2420, |
| SCD = 2421, |
| SCD_R6 = 2422, |
| SCE = 2423, |
| SCE_MM = 2424, |
| SC_MM = 2425, |
| SC_MMR6 = 2426, |
| SC_R6 = 2427, |
| SD = 2428, |
| SDBBP = 2429, |
| SDBBP16_MM = 2430, |
| SDBBP16_MMR6 = 2431, |
| SDBBP_MM = 2432, |
| SDBBP_MMR6 = 2433, |
| SDBBP_R6 = 2434, |
| SDC1 = 2435, |
| SDC164 = 2436, |
| SDC1_D64_MMR6 = 2437, |
| SDC1_MM_D32 = 2438, |
| SDC1_MM_D64 = 2439, |
| SDC2 = 2440, |
| SDC2_MMR6 = 2441, |
| SDC2_R6 = 2442, |
| SDC3 = 2443, |
| SDIV = 2444, |
| SDIV_MM = 2445, |
| SDL = 2446, |
| SDR = 2447, |
| SDXC1 = 2448, |
| SDXC164 = 2449, |
| SEB = 2450, |
| SEB64 = 2451, |
| SEB_MM = 2452, |
| SEH = 2453, |
| SEH64 = 2454, |
| SEH_MM = 2455, |
| SELEQZ = 2456, |
| SELEQZ64 = 2457, |
| SELEQZ_D = 2458, |
| SELEQZ_D_MMR6 = 2459, |
| SELEQZ_MMR6 = 2460, |
| SELEQZ_S = 2461, |
| SELEQZ_S_MMR6 = 2462, |
| SELNEZ = 2463, |
| SELNEZ64 = 2464, |
| SELNEZ_D = 2465, |
| SELNEZ_D_MMR6 = 2466, |
| SELNEZ_MMR6 = 2467, |
| SELNEZ_S = 2468, |
| SELNEZ_S_MMR6 = 2469, |
| SEL_D = 2470, |
| SEL_D_MMR6 = 2471, |
| SEL_S = 2472, |
| SEL_S_MMR6 = 2473, |
| SEQ = 2474, |
| SEQi = 2475, |
| SH = 2476, |
| SH16_MM = 2477, |
| SH16_MMR6 = 2478, |
| SH64 = 2479, |
| SHE = 2480, |
| SHE_MM = 2481, |
| SHF_B = 2482, |
| SHF_H = 2483, |
| SHF_W = 2484, |
| SHILO = 2485, |
| SHILOV = 2486, |
| SHILOV_MM = 2487, |
| SHILO_MM = 2488, |
| SHLLV_PH = 2489, |
| SHLLV_PH_MM = 2490, |
| SHLLV_QB = 2491, |
| SHLLV_QB_MM = 2492, |
| SHLLV_S_PH = 2493, |
| SHLLV_S_PH_MM = 2494, |
| SHLLV_S_W = 2495, |
| SHLLV_S_W_MM = 2496, |
| SHLL_PH = 2497, |
| SHLL_PH_MM = 2498, |
| SHLL_QB = 2499, |
| SHLL_QB_MM = 2500, |
| SHLL_S_PH = 2501, |
| SHLL_S_PH_MM = 2502, |
| SHLL_S_W = 2503, |
| SHLL_S_W_MM = 2504, |
| SHRAV_PH = 2505, |
| SHRAV_PH_MM = 2506, |
| SHRAV_QB = 2507, |
| SHRAV_QB_MMR2 = 2508, |
| SHRAV_R_PH = 2509, |
| SHRAV_R_PH_MM = 2510, |
| SHRAV_R_QB = 2511, |
| SHRAV_R_QB_MMR2 = 2512, |
| SHRAV_R_W = 2513, |
| SHRAV_R_W_MM = 2514, |
| SHRA_PH = 2515, |
| SHRA_PH_MM = 2516, |
| SHRA_QB = 2517, |
| SHRA_QB_MMR2 = 2518, |
| SHRA_R_PH = 2519, |
| SHRA_R_PH_MM = 2520, |
| SHRA_R_QB = 2521, |
| SHRA_R_QB_MMR2 = 2522, |
| SHRA_R_W = 2523, |
| SHRA_R_W_MM = 2524, |
| SHRLV_PH = 2525, |
| SHRLV_PH_MMR2 = 2526, |
| SHRLV_QB = 2527, |
| SHRLV_QB_MM = 2528, |
| SHRL_PH = 2529, |
| SHRL_PH_MMR2 = 2530, |
| SHRL_QB = 2531, |
| SHRL_QB_MM = 2532, |
| SH_MM = 2533, |
| SH_MMR6 = 2534, |
| SIGRIE = 2535, |
| SIGRIE_MMR6 = 2536, |
| SLDI_B = 2537, |
| SLDI_D = 2538, |
| SLDI_H = 2539, |
| SLDI_W = 2540, |
| SLD_B = 2541, |
| SLD_D = 2542, |
| SLD_H = 2543, |
| SLD_W = 2544, |
| SLL = 2545, |
| SLL16_MM = 2546, |
| SLL16_MMR6 = 2547, |
| SLL64_32 = 2548, |
| SLL64_64 = 2549, |
| SLLI_B = 2550, |
| SLLI_D = 2551, |
| SLLI_H = 2552, |
| SLLI_W = 2553, |
| SLLV = 2554, |
| SLLV_MM = 2555, |
| SLL_B = 2556, |
| SLL_D = 2557, |
| SLL_H = 2558, |
| SLL_MM = 2559, |
| SLL_MMR6 = 2560, |
| SLL_W = 2561, |
| SLT = 2562, |
| SLT64 = 2563, |
| SLT_MM = 2564, |
| SLTi = 2565, |
| SLTi64 = 2566, |
| SLTi_MM = 2567, |
| SLTiu = 2568, |
| SLTiu64 = 2569, |
| SLTiu_MM = 2570, |
| SLTu = 2571, |
| SLTu64 = 2572, |
| SLTu_MM = 2573, |
| SNE = 2574, |
| SNEi = 2575, |
| SPLATI_B = 2576, |
| SPLATI_D = 2577, |
| SPLATI_H = 2578, |
| SPLATI_W = 2579, |
| SPLAT_B = 2580, |
| SPLAT_D = 2581, |
| SPLAT_H = 2582, |
| SPLAT_W = 2583, |
| SRA = 2584, |
| SRAI_B = 2585, |
| SRAI_D = 2586, |
| SRAI_H = 2587, |
| SRAI_W = 2588, |
| SRARI_B = 2589, |
| SRARI_D = 2590, |
| SRARI_H = 2591, |
| SRARI_W = 2592, |
| SRAR_B = 2593, |
| SRAR_D = 2594, |
| SRAR_H = 2595, |
| SRAR_W = 2596, |
| SRAV = 2597, |
| SRAV_MM = 2598, |
| SRA_B = 2599, |
| SRA_D = 2600, |
| SRA_H = 2601, |
| SRA_MM = 2602, |
| SRA_W = 2603, |
| SRL = 2604, |
| SRL16_MM = 2605, |
| SRL16_MMR6 = 2606, |
| SRLI_B = 2607, |
| SRLI_D = 2608, |
| SRLI_H = 2609, |
| SRLI_W = 2610, |
| SRLRI_B = 2611, |
| SRLRI_D = 2612, |
| SRLRI_H = 2613, |
| SRLRI_W = 2614, |
| SRLR_B = 2615, |
| SRLR_D = 2616, |
| SRLR_H = 2617, |
| SRLR_W = 2618, |
| SRLV = 2619, |
| SRLV_MM = 2620, |
| SRL_B = 2621, |
| SRL_D = 2622, |
| SRL_H = 2623, |
| SRL_MM = 2624, |
| SRL_W = 2625, |
| SSNOP = 2626, |
| SSNOP_MM = 2627, |
| SSNOP_MMR6 = 2628, |
| ST_B = 2629, |
| ST_D = 2630, |
| ST_H = 2631, |
| ST_W = 2632, |
| SUB = 2633, |
| SUBQH_PH = 2634, |
| SUBQH_PH_MMR2 = 2635, |
| SUBQH_R_PH = 2636, |
| SUBQH_R_PH_MMR2 = 2637, |
| SUBQH_R_W = 2638, |
| SUBQH_R_W_MMR2 = 2639, |
| SUBQH_W = 2640, |
| SUBQH_W_MMR2 = 2641, |
| SUBQ_PH = 2642, |
| SUBQ_PH_MM = 2643, |
| SUBQ_S_PH = 2644, |
| SUBQ_S_PH_MM = 2645, |
| SUBQ_S_W = 2646, |
| SUBQ_S_W_MM = 2647, |
| SUBSUS_U_B = 2648, |
| SUBSUS_U_D = 2649, |
| SUBSUS_U_H = 2650, |
| SUBSUS_U_W = 2651, |
| SUBSUU_S_B = 2652, |
| SUBSUU_S_D = 2653, |
| SUBSUU_S_H = 2654, |
| SUBSUU_S_W = 2655, |
| SUBS_S_B = 2656, |
| SUBS_S_D = 2657, |
| SUBS_S_H = 2658, |
| SUBS_S_W = 2659, |
| SUBS_U_B = 2660, |
| SUBS_U_D = 2661, |
| SUBS_U_H = 2662, |
| SUBS_U_W = 2663, |
| SUBU16_MM = 2664, |
| SUBU16_MMR6 = 2665, |
| SUBUH_QB = 2666, |
| SUBUH_QB_MMR2 = 2667, |
| SUBUH_R_QB = 2668, |
| SUBUH_R_QB_MMR2 = 2669, |
| SUBU_MMR6 = 2670, |
| SUBU_PH = 2671, |
| SUBU_PH_MMR2 = 2672, |
| SUBU_QB = 2673, |
| SUBU_QB_MM = 2674, |
| SUBU_S_PH = 2675, |
| SUBU_S_PH_MMR2 = 2676, |
| SUBU_S_QB = 2677, |
| SUBU_S_QB_MM = 2678, |
| SUBVI_B = 2679, |
| SUBVI_D = 2680, |
| SUBVI_H = 2681, |
| SUBVI_W = 2682, |
| SUBV_B = 2683, |
| SUBV_D = 2684, |
| SUBV_H = 2685, |
| SUBV_W = 2686, |
| SUB_MM = 2687, |
| SUB_MMR6 = 2688, |
| SUBu = 2689, |
| SUBu_MM = 2690, |
| SUXC1 = 2691, |
| SUXC164 = 2692, |
| SUXC1_MM = 2693, |
| SW = 2694, |
| SW16_MM = 2695, |
| SW16_MMR6 = 2696, |
| SW64 = 2697, |
| SWC1 = 2698, |
| SWC1_MM = 2699, |
| SWC2 = 2700, |
| SWC2_MMR6 = 2701, |
| SWC2_R6 = 2702, |
| SWC3 = 2703, |
| SWDSP = 2704, |
| SWDSP_MM = 2705, |
| SWE = 2706, |
| SWE_MM = 2707, |
| SWL = 2708, |
| SWL64 = 2709, |
| SWLE = 2710, |
| SWLE_MM = 2711, |
| SWL_MM = 2712, |
| SWM16_MM = 2713, |
| SWM16_MMR6 = 2714, |
| SWM32_MM = 2715, |
| SWP_MM = 2716, |
| SWR = 2717, |
| SWR64 = 2718, |
| SWRE = 2719, |
| SWRE_MM = 2720, |
| SWR_MM = 2721, |
| SWSP_MM = 2722, |
| SWSP_MMR6 = 2723, |
| SWXC1 = 2724, |
| SWXC1_MM = 2725, |
| SW_MM = 2726, |
| SW_MMR6 = 2727, |
| SYNC = 2728, |
| SYNCI = 2729, |
| SYNCI_MM = 2730, |
| SYNCI_MMR6 = 2731, |
| SYNC_MM = 2732, |
| SYNC_MMR6 = 2733, |
| SYSCALL = 2734, |
| SYSCALL_MM = 2735, |
| Save16 = 2736, |
| SaveX16 = 2737, |
| SbRxRyOffMemX16 = 2738, |
| SebRx16 = 2739, |
| SehRx16 = 2740, |
| ShRxRyOffMemX16 = 2741, |
| SllX16 = 2742, |
| SllvRxRy16 = 2743, |
| SltRxRy16 = 2744, |
| SltiRxImm16 = 2745, |
| SltiRxImmX16 = 2746, |
| SltiuRxImm16 = 2747, |
| SltiuRxImmX16 = 2748, |
| SltuRxRy16 = 2749, |
| SraX16 = 2750, |
| SravRxRy16 = 2751, |
| SrlX16 = 2752, |
| SrlvRxRy16 = 2753, |
| SubuRxRyRz16 = 2754, |
| SwRxRyOffMemX16 = 2755, |
| SwRxSpImmX16 = 2756, |
| TEQ = 2757, |
| TEQI = 2758, |
| TEQI_MM = 2759, |
| TEQ_MM = 2760, |
| TGE = 2761, |
| TGEI = 2762, |
| TGEIU = 2763, |
| TGEIU_MM = 2764, |
| TGEI_MM = 2765, |
| TGEU = 2766, |
| TGEU_MM = 2767, |
| TGE_MM = 2768, |
| TLBGINV = 2769, |
| TLBGINVF = 2770, |
| TLBGINVF_MM = 2771, |
| TLBGINV_MM = 2772, |
| TLBGP = 2773, |
| TLBGP_MM = 2774, |
| TLBGR = 2775, |
| TLBGR_MM = 2776, |
| TLBGWI = 2777, |
| TLBGWI_MM = 2778, |
| TLBGWR = 2779, |
| TLBGWR_MM = 2780, |
| TLBINV = 2781, |
| TLBINVF = 2782, |
| TLBINVF_MMR6 = 2783, |
| TLBINV_MMR6 = 2784, |
| TLBP = 2785, |
| TLBP_MM = 2786, |
| TLBR = 2787, |
| TLBR_MM = 2788, |
| TLBWI = 2789, |
| TLBWI_MM = 2790, |
| TLBWR = 2791, |
| TLBWR_MM = 2792, |
| TLT = 2793, |
| TLTI = 2794, |
| TLTIU_MM = 2795, |
| TLTI_MM = 2796, |
| TLTU = 2797, |
| TLTU_MM = 2798, |
| TLT_MM = 2799, |
| TNE = 2800, |
| TNEI = 2801, |
| TNEI_MM = 2802, |
| TNE_MM = 2803, |
| TRUNC_L_D64 = 2804, |
| TRUNC_L_D_MMR6 = 2805, |
| TRUNC_L_S = 2806, |
| TRUNC_L_S_MMR6 = 2807, |
| TRUNC_W_D32 = 2808, |
| TRUNC_W_D64 = 2809, |
| TRUNC_W_D_MMR6 = 2810, |
| TRUNC_W_MM = 2811, |
| TRUNC_W_S = 2812, |
| TRUNC_W_S_MM = 2813, |
| TRUNC_W_S_MMR6 = 2814, |
| TTLTIU = 2815, |
| UDIV = 2816, |
| UDIV_MM = 2817, |
| V3MULU = 2818, |
| VMM0 = 2819, |
| VMULU = 2820, |
| VSHF_B = 2821, |
| VSHF_D = 2822, |
| VSHF_H = 2823, |
| VSHF_W = 2824, |
| WAIT = 2825, |
| WAIT_MM = 2826, |
| WAIT_MMR6 = 2827, |
| WRDSP = 2828, |
| WRDSP_MM = 2829, |
| WRPGPR_MMR6 = 2830, |
| WSBH = 2831, |
| WSBH_MM = 2832, |
| WSBH_MMR6 = 2833, |
| XOR = 2834, |
| XOR16_MM = 2835, |
| XOR16_MMR6 = 2836, |
| XOR64 = 2837, |
| XORI_B = 2838, |
| XORI_MMR6 = 2839, |
| XOR_MM = 2840, |
| XOR_MMR6 = 2841, |
| XOR_V = 2842, |
| XORi = 2843, |
| XORi64 = 2844, |
| XORi_MM = 2845, |
| XorRxRxRy16 = 2846, |
| YIELD = 2847, |
| INSTRUCTION_LIST_END = 2848 |
| }; |
| |
| } // end namespace Mips |
| } // end namespace llvm |
| #endif // GET_INSTRINFO_ENUM |
| |
| #ifdef GET_INSTRINFO_SCHED_ENUM |
| #undef GET_INSTRINFO_SCHED_ENUM |
| namespace llvm { |
| |
| namespace Mips { |
| namespace Sched { |
| enum { |
| NoInstrModel = 0, |
| IIPseudo = 1, |
| II_B = 2, |
| II_BCCZAL = 3, |
| II_MTC1 = 4, |
| II_MFC1 = 5, |
| II_JALR = 6, |
| II_JAL = 7, |
| II_CVT = 8, |
| II_DMULT = 9, |
| II_DMULTU = 10, |
| II_DDIV = 11, |
| II_DDIVU = 12, |
| II_IndirectBranchPseudo = 13, |
| II_MADD = 14, |
| II_MADDU = 15, |
| II_MFHI_MFLO = 16, |
| II_MSUB = 17, |
| II_MSUBU = 18, |
| II_MTHI_MTLO = 19, |
| II_MULT = 20, |
| II_MULTU = 21, |
| II_ReturnPseudo = 22, |
| II_DIV = 23, |
| II_DIVU = 24, |
| II_J = 25, |
| II_JR = 26, |
| II_TRAP = 27, |
| II_ADD = 28, |
| II_ADDIUPC = 29, |
| II_ADDIU = 30, |
| II_ADDR_PS = 31, |
| II_ADDU = 32, |
| II_ADDI = 33, |
| II_ALIGN = 34, |
| II_ALUIPC = 35, |
| II_AND = 36, |
| II_ANDI = 37, |
| II_AUI = 38, |
| II_AUIPC = 39, |
| IIM16Alu = 40, |
| II_BADDU = 41, |
| II_BC = 42, |
| II_BALC = 43, |
| II_BBIT = 44, |
| II_BC1CCZ = 45, |
| II_BC1F = 46, |
| II_BC1FL = 47, |
| II_BC1T = 48, |
| II_BC1TL = 49, |
| II_BC2CCZ = 50, |
| II_BCC = 51, |
| II_BCCC = 52, |
| II_BCCZ = 53, |
| II_BCCZC = 54, |
| II_BCCZALS = 55, |
| II_BITSWAP = 56, |
| II_BREAK = 57, |
| II_CACHE = 58, |
| II_CACHEE = 59, |
| II_CEIL = 60, |
| II_CFC1 = 61, |
| II_CFC2 = 62, |
| II_INS = 63, |
| II_CLASS_D = 64, |
| II_CLASS_S = 65, |
| II_CLO = 66, |
| II_CLZ = 67, |
| II_CMP_CC_D = 68, |
| II_CMP_CC_S = 69, |
| II_CRC32B = 70, |
| II_CRC32CB = 71, |
| II_CRC32CD = 72, |
| II_CRC32CH = 73, |
| II_CRC32CW = 74, |
| II_CRC32D = 75, |
| II_CRC32H = 76, |
| II_CRC32W = 77, |
| II_CTC1 = 78, |
| II_CTC2 = 79, |
| II_C_CC_D = 80, |
| II_C_CC_S = 81, |
| II_DADD = 82, |
| II_DADDI = 83, |
| II_DADDIU = 84, |
| II_DADDU = 85, |
| II_DAHI = 86, |
| II_DALIGN = 87, |
| II_DATI = 88, |
| II_DAUI = 89, |
| II_DBITSWAP = 90, |
| II_DCLO = 91, |
| II_DCLZ = 92, |
| II_DERET = 93, |
| II_EXT = 94, |
| II_DI = 95, |
| II_DLSA = 96, |
| II_DMFC0 = 97, |
| II_DMFC1 = 98, |
| II_DMFC2 = 99, |
| II_DMFGC0 = 100, |
| II_DMOD = 101, |
| II_DMODU = 102, |
| II_DMT = 103, |
| II_DMTC0 = 104, |
| II_DMTC1 = 105, |
| II_DMTC2 = 106, |
| II_DMTGC0 = 107, |
| II_DMUH = 108, |
| II_DMUHU = 109, |
| II_DMUL = 110, |
| II_POP = 111, |
| II_DROTR = 112, |
| II_DROTR32 = 113, |
| II_DROTRV = 114, |
| II_DSBH = 115, |
| II_DSHD = 116, |
| II_DSLL = 117, |
| II_DSLL32 = 118, |
| II_DSLLV = 119, |
| II_DSRA = 120, |
| II_DSRA32 = 121, |
| II_DSRAV = 122, |
| II_DSRL = 123, |
| II_DSRL32 = 124, |
| II_DSRLV = 125, |
| II_DSUB = 126, |
| II_DSUBU = 127, |
| II_DVP = 128, |
| II_DVPE = 129, |
| II_EHB = 130, |
| II_EI = 131, |
| II_EMT = 132, |
| II_ERET = 133, |
| II_ERETNC = 134, |
| II_EVP = 135, |
| II_EVPE = 136, |
| II_ABS = 137, |
| II_SQRT_D = 138, |
| II_ADD_D = 139, |
| II_ADD_PS = 140, |
| II_ADD_S = 141, |
| II_DIV_D = 142, |
| II_DIV_S = 143, |
| II_FLOOR = 144, |
| II_MOV_D = 145, |
| II_MOV_S = 146, |
| II_MUL_D = 147, |
| II_MUL_PS = 148, |
| II_MUL_S = 149, |
| II_NEG = 150, |
| II_FORK = 151, |
| II_SQRT_S = 152, |
| II_SUB_D = 153, |
| II_SUB_PS = 154, |
| II_SUB_S = 155, |
| II_GINVI = 156, |
| II_GINVT = 157, |
| II_HYPCALL = 158, |
| II_JALR_HB = 159, |
| II_JALRC = 160, |
| II_JALRS = 161, |
| II_JALS = 162, |
| II_JIALC = 163, |
| II_JIC = 164, |
| II_JRADDIUSP = 165, |
| II_JRC = 166, |
| II_JR_HB = 167, |
| II_LB = 168, |
| II_LBE = 169, |
| II_LBU = 170, |
| II_LBUE = 171, |
| II_LD = 172, |
| II_LDC1 = 173, |
| II_LDC2 = 174, |
| II_LDC3 = 175, |
| II_LDL = 176, |
| II_LDPC = 177, |
| II_LDR = 178, |
| II_LDXC1 = 179, |
| II_LH = 180, |
| II_LHE = 181, |
| II_LHU = 182, |
| II_LHUE = 183, |
| II_LI = 184, |
| II_LL = 185, |
| II_LLD = 186, |
| II_LLE = 187, |
| II_LSA = 188, |
| II_LUI = 189, |
| II_LUXC1 = 190, |
| II_LW = 191, |
| II_LWC1 = 192, |
| II_LWC2 = 193, |
| II_LWC3 = 194, |
| II_LWE = 195, |
| II_LWL = 196, |
| II_LWLE = 197, |
| II_LWM = 198, |
| II_LWPC = 199, |
| II_LWP = 200, |
| II_LWR = 201, |
| II_LWRE = 202, |
| II_LWUPC = 203, |
| II_LWU = 204, |
| II_LWXC1 = 205, |
| II_LWXS = 206, |
| II_MADDF_D = 207, |
| II_MADDF_S = 208, |
| II_MADD_D = 209, |
| II_MADD_S = 210, |
| II_MAX_D = 211, |
| II_MAXA_D = 212, |
| II_MAX_S = 213, |
| II_MAXA_S = 214, |
| II_MFC0 = 215, |
| II_MFC2 = 216, |
| II_MFGC0 = 217, |
| II_MFHC0 = 218, |
| II_MFHC1 = 219, |
| II_MFHGC0 = 220, |
| II_MFTR = 221, |
| II_MIN_S = 222, |
| II_MINA_D = 223, |
| II_MIN_D = 224, |
| II_MINA_S = 225, |
| II_MOD = 226, |
| II_MODU = 227, |
| II_MOVE = 228, |
| II_MOVF_D = 229, |
| II_MOVF = 230, |
| II_MOVF_S = 231, |
| II_MOVN_D = 232, |
| II_MOVN = 233, |
| II_MOVN_S = 234, |
| II_MOVT_D = 235, |
| II_MOVT = 236, |
| II_MOVT_S = 237, |
| II_MOVZ_D = 238, |
| II_MOVZ = 239, |
| II_MOVZ_S = 240, |
| II_MSUBF_D = 241, |
| II_MSUBF_S = 242, |
| II_MSUB_D = 243, |
| II_MSUB_S = 244, |
| II_MTC0 = 245, |
| II_MTC2 = 246, |
| II_MTGC0 = 247, |
| II_MTHC0 = 248, |
| II_MTHC1 = 249, |
| II_MTHGC0 = 250, |
| II_MTTR = 251, |
| II_MUH = 252, |
| II_MUHU = 253, |
| II_MUL = 254, |
| II_MULR_PS = 255, |
| II_MULU = 256, |
| II_NMADD_D = 257, |
| II_NMADD_S = 258, |
| II_NMSUB_D = 259, |
| II_NMSUB_S = 260, |
| II_NOR = 261, |
| II_NOT = 262, |
| II_OR = 263, |
| II_ORI = 264, |
| II_PAUSE = 265, |
| II_PREF = 266, |
| II_PREFE = 267, |
| II_RDHWR = 268, |
| II_RDPGPR = 269, |
| II_RECIP_D = 270, |
| II_RECIP_S = 271, |
| II_RINT_D = 272, |
| II_RINT_S = 273, |
| II_ROTR = 274, |
| II_ROTRV = 275, |
| II_ROUND = 276, |
| II_RSQRT_D = 277, |
| II_RSQRT_S = 278, |
| II_RESTORE = 279, |
| II_SB = 280, |
| II_SBE = 281, |
| II_SC = 282, |
| II_SCD = 283, |
| II_SCE = 284, |
| II_SD = 285, |
| II_SDBBP = 286, |
| II_SDC1 = 287, |
| II_SDC2 = 288, |
| II_SDC3 = 289, |
| II_SDL = 290, |
| II_SDR = 291, |
| II_SDXC1 = 292, |
| II_SEB = 293, |
| II_SEH = 294, |
| II_SELCCZ = 295, |
| II_SELCCZ_D = 296, |
| II_SELCCZ_S = 297, |
| II_SEL_D = 298, |
| II_SEL_S = 299, |
| II_SEQ_SNE = 300, |
| II_SEQI_SNEI = 301, |
| II_SH = 302, |
| II_SHE = 303, |
| II_SIGRIE = 304, |
| II_SLL = 305, |
| II_SLLV = 306, |
| II_SLT_SLTU = 307, |
| II_SLTI_SLTIU = 308, |
| II_SRA = 309, |
| II_SRAV = 310, |
| II_SRL = 311, |
| II_SRLV = 312, |
| II_SSNOP = 313, |
| II_SUB = 314, |
| II_SUBU = 315, |
| II_SUXC1 = 316, |
| II_SW = 317, |
| II_SWC1 = 318, |
| II_SWC2 = 319, |
| II_SWC3 = 320, |
| II_SWE = 321, |
| II_SWL = 322, |
| II_SWLE = 323, |
| II_SWM = 324, |
| II_SWP = 325, |
| II_SWR = 326, |
| II_SWRE = 327, |
| II_SWXC1 = 328, |
| II_SYNC = 329, |
| II_SYNCI = 330, |
| II_SYSCALL = 331, |
| II_SAVE = 332, |
| II_TEQ = 333, |
| II_TEQI = 334, |
| II_TGE = 335, |
| II_TGEI = 336, |
| II_TGEIU = 337, |
| II_TGEU = 338, |
| II_TLBGINV = 339, |
| II_TLBGINVF = 340, |
| II_TLBGP = 341, |
| II_TLBGR = 342, |
| II_TLBGWI = 343, |
| II_TLBGWR = 344, |
| II_TLBINV = 345, |
| II_TLBINVF = 346, |
| II_TLBP = 347, |
| II_TLBR = 348, |
| II_TLBWI = 349, |
| II_TLBWR = 350, |
| II_TLT = 351, |
| II_TLTI = 352, |
| II_TTLTIU = 353, |
| II_TLTU = 354, |
| II_TNE = 355, |
| II_TNEI = 356, |
| II_TRUNC = 357, |
| II_WAIT = 358, |
| II_WRPGPR = 359, |
| II_WSBH = 360, |
| II_XOR = 361, |
| II_XORI = 362, |
| II_YIELD = 363, |
| AND = 364, |
| LUi = 365, |
| NOR = 366, |
| OR = 367, |
| SLTi_SLTiu = 368, |
| SUB = 369, |
| SUBu = 370, |
| XOR = 371, |
| SSNOP = 372, |
| NOP = 373, |
| B = 374, |
| BAL = 375, |
| BAL_BR_BGEZAL_BGEZALL_BLTZAL_BLTZALL = 376, |
| BEQ_BEQL_BNE_BNEL = 377, |
| BGEZ_BGEZL_BGTZ_BGTZL_BLEZ_BLEZL_BLTZ_BLTZL = 378, |
| BREAK = 379, |
| DERET = 380, |
| ERET = 381, |
| ERet_RetRA = 382, |
| ERETNC = 383, |
| J_TAILCALL = 384, |
| JR_TAILCALLREG_TAILCALLREGHB = 385, |
| JR_HB = 386, |
| PseudoIndirectBranch_PseudoIndirectHazardBranch = 387, |
| PseudoReturn = 388, |
| SDBBP = 389, |
| SYSCALL = 390, |
| TEQ = 391, |
| TEQI = 392, |
| TGE = 393, |
| TGEI = 394, |
| TGEIU = 395, |
| TGEU = 396, |
| TLT = 397, |
| TLTI = 398, |
| TLTU = 399, |
| TNE = 400, |
| TNEI = 401, |
| TRAP = 402, |
| TTLTIU = 403, |
| WAIT = 404, |
| PAUSE = 405, |
| JAL = 406, |
| JALR_JALRHBPseudo_JALRPseudo = 407, |
| JALR_HB = 408, |
| JALX = 409, |
| TLBINV = 410, |
| TLBINVF = 411, |
| TLBP = 412, |
| TLBR = 413, |
| TLBWI = 414, |
| TLBWR = 415, |
| MFC0 = 416, |
| MTC0 = 417, |
| MFC2 = 418, |
| MTC2 = 419, |
| HYPCALL = 420, |
| MFGC0 = 421, |
| MFHGC0 = 422, |
| MTGC0 = 423, |
| MTHGC0 = 424, |
| TLBGINV = 425, |
| TLBGINVF = 426, |
| TLBGP = 427, |
| TLBGR = 428, |
| TLBGWI = 429, |
| TLBGWR = 430, |
| LB = 431, |
| LBu = 432, |
| LH = 433, |
| LHu = 434, |
| LW = 435, |
| LL = 436, |
| LWC2 = 437, |
| LWC3 = 438, |
| LDC2 = 439, |
| LDC3 = 440, |
| LBE = 441, |
| LBuE = 442, |
| LHE = 443, |
| LHuE = 444, |
| LWE = 445, |
| LLE = 446, |
| LWPC = 447, |
| LWL = 448, |
| LWR = 449, |
| LWLE = 450, |
| LWRE = 451, |
| SB = 452, |
| SH = 453, |
| SW = 454, |
| SWC2 = 455, |
| SWC3 = 456, |
| SDC2 = 457, |
| SDC3 = 458, |
| SC = 459, |
| SBE = 460, |
| SHE = 461, |
| SWE = 462, |
| SCE = 463, |
| SWL = 464, |
| SWR = 465, |
| SWLE = 466, |
| SWRE = 467, |
| PREF = 468, |
| PREFE = 469, |
| CACHE = 470, |
| CACHEE = 471, |
| SYNC = 472, |
| SYNCI = 473, |
| CLO = 474, |
| CLZ = 475, |
| DI = 476, |
| EI = 477, |
| MFHI_MFLO_PseudoMFHI_PseudoMFLO = 478, |
| EHB = 479, |
| RDHWR = 480, |
| WSBH = 481, |
| MOVN_I_I = 482, |
| MOVZ_I_I = 483, |
| DIV_PseudoSDIV_SDIV = 484, |
| DIVU_PseudoUDIV_UDIV = 485, |
| MUL = 486, |
| MULT_PseudoMULT = 487, |
| MULTu_PseudoMULTu = 488, |
| MADD_PseudoMADD = 489, |
| MADDU_PseudoMADDU = 490, |
| MSUB_PseudoMSUB = 491, |
| MSUBU_PseudoMSUBU = 492, |
| MTHI_MTLO_PseudoMTLOHI = 493, |
| EXT = 494, |
| INS = 495, |
| ADD = 496, |
| ADDi = 497, |
| ADDiu = 498, |
| ANDi = 499, |
| ORi = 500, |
| ROTR = 501, |
| SEB = 502, |
| SEH = 503, |
| SLT_SLTu = 504, |
| SLL = 505, |
| SRA = 506, |
| SRL = 507, |
| XORi = 508, |
| ADDu = 509, |
| SLLV = 510, |
| SRAV = 511, |
| SRLV = 512, |
| LSA = 513, |
| COPY = 514, |
| VSHF_B_VSHF_D_VSHF_H_VSHF_W = 515, |
| BINSLI_B_BINSLI_D_BINSLI_H_BINSLI_W_BINSL_B_BINSL_D_BINSL_H_BINSL_W = 516, |
| BINSRI_B_BINSRI_D_BINSRI_H_BINSRI_W_BINSR_B_BINSR_D_BINSR_H_BINSR_W = 517, |
| INSERT_B_INSERT_D_INSERT_H_INSERT_W = 518, |
| SLDI_B_SLDI_D_SLDI_H_SLDI_W_SLD_B_SLD_D_SLD_H_SLD_W = 519, |
| BSETI_B_BSETI_D_BSETI_H_BSETI_W_BSET_B_BSET_D_BSET_H_BSET_W = 520, |
| BCLRI_B_BCLRI_D_BCLRI_H_BCLRI_W_BCLR_B_BCLR_D_BCLR_H_BCLR_W = 521, |
| BNEGI_B_BNEGI_D_BNEGI_H_BNEGI_W_BNEG_B_BNEG_D_BNEG_H_BNEG_W = 522, |
| BSELI_B_BSEL_V = 523, |
| BMNZI_B_BMNZ_V_BMZI_B_BMZ_V = 524, |
| BSEL_D_PSEUDO_BSEL_FD_PSEUDO_BSEL_FW_PSEUDO_BSEL_H_PSEUDO_BSEL_W_PSEUDO = 525, |
| PCNT_B_PCNT_D_PCNT_H_PCNT_W = 526, |
| SAT_S_B_SAT_S_D_SAT_S_H_SAT_S_W_SAT_U_B_SAT_U_D_SAT_U_H_SAT_U_W = 527, |
| BNZ_B_BNZ_D_BNZ_H_BNZ_V_BNZ_W_BZ_B_BZ_D_BZ_H_BZ_V_BZ_W = 528, |
| CFCMSA_CTCMSA = 529, |
| FABS_S_FABS_D32_FABS_D64 = 530, |
| MOVF_D32_MOVF_D64 = 531, |
| MOVF_S = 532, |
| MOVT_D32_MOVT_D64 = 533, |
| MOVT_S = 534, |
| FMOV_D32_FMOV_D64 = 535, |
| FMOV_S = 536, |
| FNEG_S_FNEG_D32_FNEG_D64 = 537, |
| ADD_A_B_ADD_A_D_ADD_A_H_ADD_A_W = 538, |
| ADDS_A_B_ADDS_A_D_ADDS_A_H_ADDS_A_W_ADDS_S_B_ADDS_S_D_ADDS_S_H_ADDS_S_W_ADDS_U_B_ADDS_U_D_ADDS_U_H_ADDS_U_W = 539, |
| ADDVI_B_ADDVI_D_ADDVI_H_ADDVI_W_ADDV_B_ADDV_D_ADDV_H_ADDV_W = 540, |
| ASUB_S_B_ASUB_S_D_ASUB_S_H_ASUB_S_W_ASUB_U_B_ASUB_U_D_ASUB_U_H_ASUB_U_W = 541, |
| AVER_S_B_AVER_S_D_AVER_S_H_AVER_S_W_AVER_U_B_AVER_U_D_AVER_U_H_AVER_U_W_AVE_S_B_AVE_S_D_AVE_S_H_AVE_S_W_AVE_U_B_AVE_U_D_AVE_U_H_AVE_U_W = 542, |
| SHF_B_SHF_H_SHF_W = 543, |
| FILL_B_FILL_D_FILL_H_FILL_W = 544, |
| SPLATI_B_SPLATI_D_SPLATI_H_SPLATI_W_SPLAT_B_SPLAT_D_SPLAT_H_SPLAT_W = 545, |
| MOVE_V = 546, |
| LDI_B_LDI_D_LDI_H_LDI_W = 547, |
| AND_V_NOR_V_OR_V_XOR_V = 548, |
| ANDI_B_NORI_B_ORI_B_XORI_B = 549, |
| AND_V_D_PSEUDO_AND_V_H_PSEUDO_AND_V_W_PSEUDO_NOR_V_D_PSEUDO_NOR_V_H_PSEUDO_NOR_V_W_PSEUDO_OR_V_D_PSEUDO_OR_V_H_PSEUDO_OR_V_W_PSEUDO_XOR_V_D_PSEUDO_XOR_V_H_PSEUDO_XOR_V_W_PSEUDO = 550, |
| FILL_FD_PSEUDO_FILL_FW_PSEUDO = 551, |
| INSERT_FD_PSEUDO_INSERT_FW_PSEUDO = 552, |
| FEXP2_D_FEXP2_W = 553, |
| CLTI_S_B_CLTI_S_D_CLTI_S_H_CLTI_S_W_CLTI_U_B_CLTI_U_D_CLTI_U_H_CLTI_U_W_CLT_S_B_CLT_S_D_CLT_S_H_CLT_S_W_CLT_U_B_CLT_U_D_CLT_U_H_CLT_U_W = 554, |
| CLEI_S_B_CLEI_S_D_CLEI_S_H_CLEI_S_W_CLEI_U_B_CLEI_U_D_CLEI_U_H_CLEI_U_W_CLE_S_B_CLE_S_D_CLE_S_H_CLE_S_W_CLE_U_B_CLE_U_D_CLE_U_H_CLE_U_W = 555, |
| CEQI_B_CEQI_D_CEQI_H_CEQI_W_CEQ_B_CEQ_D_CEQ_H_CEQ_W = 556, |
| CMP_UN_D = 557, |
| CMP_UN_S = 558, |
| CMP_UEQ_D = 559, |
| CMP_UEQ_S = 560, |
| CMP_EQ_D = 561, |
| CMP_EQ_S = 562, |
| CMP_LT_D = 563, |
| CMP_LT_S = 564, |
| CMP_ULT_D = 565, |
| CMP_ULT_S = 566, |
| CMP_LE_D = 567, |
| CMP_LE_S = 568, |
| CMP_ULE_D = 569, |
| CMP_ULE_S = 570, |
| FSAF_D_FSAF_W_FSEQ_D_FSEQ_W_FSLE_D_FSLE_W_FSLT_D_FSLT_W_FSNE_D_FSNE_W_FSOR_D_FSOR_W = 571, |
| FSUEQ_D_FSUEQ_W = 572, |
| FSULE_D_FSULE_W = 573, |
| FSULT_D_FSULT_W = 574, |
| FSUNE_D_FSUNE_W = 575, |
| FSUN_D_FSUN_W = 576, |
| FCAF_D_FCAF_W = 577, |
| FCEQ_D_FCEQ_W = 578, |
| FCLE_D_FCLE_W = 579, |
| FCLT_D_FCLT_W = 580, |
| FCNE_D_FCNE_W = 581, |
| FCOR_D_FCOR_W = 582, |
| FCUEQ_D_FCUEQ_W = 583, |
| FCULE_D_FCULE_W = 584, |
| FCULT_D_FCULT_W = 585, |
| FCUNE_D_FCUNE_W = 586, |
| FCUN_D_FCUN_W = 587, |
| FABS_D_FABS_W = 588, |
| FFINT_S_D_FFINT_S_W_FFINT_U_D_FFINT_U_W = 589, |
| FFQL_D_FFQL_W = 590, |
| FFQR_D_FFQR_W = 591, |
| FTINT_S_D_FTINT_S_W_FTINT_U_D_FTINT_U_W = 592, |
| FRINT_D_FRINT_W = 593, |
| FTQ_H_FTQ_W = 594, |
| FTRUNC_S_D_FTRUNC_S_W_FTRUNC_U_D_FTRUNC_U_W = 595, |
| FEXDO_H_FEXDO_W = 596, |
| FEXUPL_D_FEXUPL_W = 597, |
| FEXUPR_D_FEXUPR_W = 598, |
| FCLASS_D_FCLASS_W = 599, |
| FMAX_A_D_FMAX_A_W = 600, |
| FMAX_D_FMAX_W = 601, |
| FMIN_A_D_FMIN_A_W = 602, |
| FMIN_D_FMIN_W = 603, |
| FLOG2_D_FLOG2_W = 604, |
| ILVL_B_ILVL_D_ILVL_H_ILVL_W_ILVR_B_ILVR_D_ILVR_H_ILVR_W = 605, |
| ILVEV_B_ILVEV_D_ILVEV_H_ILVEV_W_ILVOD_B_ILVOD_D_ILVOD_H_ILVOD_W = 606, |
| INSVE_B_INSVE_D_INSVE_H_INSVE_W = 607, |
| SUBS_S_B_SUBS_S_D_SUBS_S_H_SUBS_S_W_SUBS_U_B_SUBS_U_D_SUBS_U_H_SUBS_U_W = 608, |
| SUBSUS_U_B_SUBSUS_U_D_SUBSUS_U_H_SUBSUS_U_W = 609, |
| SUBSUU_S_B_SUBSUU_S_D_SUBSUU_S_H_SUBSUU_S_W = 610, |
| SUBVI_B_SUBVI_D_SUBVI_H_SUBVI_W = 611, |
| SUBV_B_SUBV_D_SUBV_H_SUBV_W = 612, |
| MOD_S_B_MOD_S_D_MOD_S_H_MOD_S_W_MOD_U_B_MOD_U_D_MOD_U_H_MOD_U_W = 613, |
| DIV_S_B_DIV_S_D_DIV_S_H_DIV_S_W_DIV_U_B_DIV_U_D_DIV_U_H_DIV_U_W = 614, |
| HADD_S_D_HADD_S_H_HADD_S_W_HADD_U_D_HADD_U_H_HADD_U_W = 615, |
| HSUB_S_D_HSUB_S_H_HSUB_S_W_HSUB_U_D_HSUB_U_H_HSUB_U_W = 616, |
| MAX_S_B_MAX_S_D_MAX_S_H_MAX_S_W_MIN_S_B_MIN_S_D_MIN_S_H_MIN_S_W = 617, |
| MAX_U_B_MAX_U_D_MAX_U_H_MAX_U_W_MIN_U_B_MIN_U_D_MIN_U_H_MIN_U_W = 618, |
| MAX_A_B_MAX_A_D_MAX_A_H_MAX_A_W_MIN_A_B_MIN_A_D_MIN_A_H_MIN_A_W = 619, |
| MAXI_S_B_MAXI_S_D_MAXI_S_H_MAXI_S_W_MAXI_U_B_MAXI_U_D_MAXI_U_H_MAXI_U_W_MINI_S_B_MINI_S_D_MINI_S_H_MINI_S_W_MINI_U_B_MINI_U_D_MINI_U_H_MINI_U_W = 620, |
| SRAI_B_SRAI_D_SRAI_H_SRAI_W_SRA_B_SRA_D_SRA_H_SRA_W = 621, |
| SRLI_B_SRLI_D_SRLI_H_SRLI_W_SRL_B_SRL_D_SRL_H_SRL_W = 622, |
| SRARI_B_SRARI_D_SRARI_H_SRARI_W_SRAR_B_SRAR_D_SRAR_H_SRAR_W = 623, |
| SRLRI_B_SRLRI_D_SRLRI_H_SRLRI_W_SRLR_B_SRLR_D_SRLR_H_SRLR_W = 624, |
| SLLI_B_SLLI_D_SLLI_H_SLLI_W_SLL_B_SLL_D_SLL_H_SLL_W = 625, |
| PCKEV_B_PCKEV_D_PCKEV_H_PCKEV_W_PCKOD_B_PCKOD_D_PCKOD_H_PCKOD_W = 626, |
| NLOC_B_NLOC_D_NLOC_H_NLOC_W_NLZC_B_NLZC_D_NLZC_H_NLZC_W = 627, |
| FADD_D32_FADD_D64 = 628, |
| FADD_PS64 = 629, |
| FADD_S = 630, |
| FMUL_D32_FMUL_D64 = 631, |
| FMUL_PS64 = 632, |
| FMUL_S = 633, |
| FSUB_D32_FSUB_D64 = 634, |
| FSUB_PS64 = 635, |
| FSUB_S = 636, |
| TRUNC_L_D64_TRUNC_L_S_TRUNC_W_D32_TRUNC_W_D64_TRUNC_W_S = 637, |
| CVT_D32_S_CVT_D32_W_CVT_D64_L_CVT_D64_S_CVT_D64_W_CVT_L_D64_CVT_L_S_CVT_S_D32_CVT_S_D64_CVT_S_L_CVT_S_W_CVT_W_D32_CVT_W_D64_CVT_W_S = 638, |
| CVT_PS_S64_CVT_S_PL64_CVT_S_PU64 = 639, |
| C_EQ_D32_C_EQ_D64_C_F_D32_C_F_D64_C_LE_D32_C_LE_D64_C_LT_D32_C_LT_D64_C_NGE_D32_C_NGE_D64_C_NGLE_D32_C_NGLE_D64_C_NGL_D32_C_NGL_D64_C_NGT_D32_C_NGT_D64_C_OLE_D32_C_OLE_D64_C_OLT_D32_C_OLT_D64_C_SEQ_D32_C_SEQ_D64_C_SF_D32_C_SF_D64_C_UEQ_D32_C_UEQ_D64_C_ULE_D32_C_ULE_D64_C_ULT_D32_C_ULT_D64_C_UN_D32_C_UN_D64 = 640, |
| C_EQ_S_C_F_S_C_LE_S_C_LT_S_C_NGE_S_C_NGLE_S_C_NGL_S_C_NGT_S_C_OLE_S_C_OLT_S_C_SEQ_S_C_SF_S_C_UEQ_S_C_ULE_S_C_ULT_S_C_UN_S = 641, |
| FCMP_D32_FCMP_D64 = 642, |
| FCMP_S32 = 643, |
| PseudoCVT_D32_W_PseudoCVT_D64_L_PseudoCVT_D64_W_PseudoCVT_S_L_PseudoCVT_S_W = 644, |
| PLL_PS64_PLU_PS64_PUL_PS64_PUU_PS64 = 645, |
| FDIV_S = 646, |
| FDIV_D32_FDIV_D64 = 647, |
| FSQRT_S = 648, |
| FSQRT_D32_FSQRT_D64 = 649, |
| FRCP_D_FRCP_W = 650, |
| FRSQRT_D_FRSQRT_W = 651, |
| RECIP_D32_RECIP_D64 = 652, |
| RSQRT_D32_RSQRT_D64 = 653, |
| RECIP_S = 654, |
| RSQRT_S = 655, |
| FMADD_D_FMADD_W = 656, |
| FMSUB_D_FMSUB_W = 657, |
| FDIV_W = 658, |
| FDIV_D = 659, |
| FSQRT_W = 660, |
| FSQRT_D = 661, |
| FMUL_D_FMUL_W = 662, |
| FADD_D_FADD_W = 663, |
| FSUB_D_FSUB_W = 664, |
| DPADD_S_D_DPADD_S_H_DPADD_S_W_DPADD_U_D_DPADD_U_H_DPADD_U_W = 665, |
| DPSUB_S_D_DPSUB_S_H_DPSUB_S_W_DPSUB_U_D_DPSUB_U_H_DPSUB_U_W = 666, |
| DOTP_S_D_DOTP_S_H_DOTP_S_W_DOTP_U_D_DOTP_U_H_DOTP_U_W = 667, |
| MSUBV_B_MSUBV_D_MSUBV_H_MSUBV_W = 668, |
| MADDV_B_MADDV_D_MADDV_H_MADDV_W = 669, |
| MULV_B_MULV_D_MULV_H_MULV_W = 670, |
| MADDR_Q_H_MADDR_Q_W = 671, |
| MADD_Q_H_MADD_Q_W = 672, |
| MSUBR_Q_H_MSUBR_Q_W = 673, |
| MSUB_Q_H_MSUB_Q_W = 674, |
| MULR_Q_H_MULR_Q_W = 675, |
| MUL_Q_H_MUL_Q_W = 676, |
| MADD_D32_MADD_D64 = 677, |
| MADD_S = 678, |
| MSUB_D32_MSUB_D64 = 679, |
| MSUB_S = 680, |
| NMADD_D32_NMADD_D64 = 681, |
| NMADD_S = 682, |
| NMSUB_D32_NMSUB_D64 = 683, |
| NMSUB_S = 684, |
| CTC1 = 685, |
| MTC1_MTC1_D64_BuildPairF64_BuildPairF64_64 = 686, |
| MTHC1_D32_MTHC1_D64 = 687, |
| COPY_U_B_COPY_U_H_COPY_U_W = 688, |
| COPY_S_B_COPY_S_D_COPY_S_H_COPY_S_W = 689, |
| BC1F = 690, |
| BC1FL = 691, |
| BC1T = 692, |
| BC1TL = 693, |
| CFC1 = 694, |
| MFC1_MFC1_D64_ExtractElementF64_ExtractElementF64_64 = 695, |
| MFHC1_D32_MFHC1_D64 = 696, |
| MOVF_I = 697, |
| MOVT_I = 698, |
| SDC1_SDC164 = 699, |
| SDXC1_SDXC164 = 700, |
| SWC1 = 701, |
| SWXC1 = 702, |
| SUXC1_SUXC164 = 703, |
| ST_B_ST_D_ST_H_ST_W = 704, |
| ST_F16 = 705, |
| MOVN_I_D32_MOVN_I_D64 = 706, |
| MOVN_I_S = 707, |
| MOVZ_I_D32_MOVZ_I_D64 = 708, |
| MOVZ_I_S = 709, |
| LDC1_LDC164 = 710, |
| LDXC1_LDXC164 = 711, |
| LWC1 = 712, |
| LWXC1 = 713, |
| LUXC1_LUXC164 = 714, |
| LD_B_LD_D_LD_H_LD_W = 715, |
| LD_F16 = 716, |
| CEIL_L_D64_CEIL_L_S_CEIL_W_D32_CEIL_W_D64_CEIL_W_S = 717, |
| FLOOR_L_D64_FLOOR_L_S_FLOOR_W_D32_FLOOR_W_D64_FLOOR_W_S = 718, |
| ROUND_L_D64_ROUND_L_S_ROUND_W_D32_ROUND_W_D64_ROUND_W_S = 719, |
| ROTRV = 720, |
| ATOMIC_SWAP_I16_POSTRA_ATOMIC_SWAP_I32_POSTRA_ATOMIC_SWAP_I64_POSTRA_ATOMIC_SWAP_I8_POSTRA = 721, |
| ATOMIC_CMP_SWAP_I16_POSTRA_ATOMIC_CMP_SWAP_I32_POSTRA_ATOMIC_CMP_SWAP_I64_POSTRA_ATOMIC_CMP_SWAP_I8_POSTRA = 722, |
| ATOMIC_LOAD_ADD_I16_POSTRA_ATOMIC_LOAD_ADD_I32_POSTRA_ATOMIC_LOAD_ADD_I64_POSTRA_ATOMIC_LOAD_ADD_I8_POSTRA_ATOMIC_LOAD_AND_I16_POSTRA_ATOMIC_LOAD_AND_I32_POSTRA_ATOMIC_LOAD_AND_I64_POSTRA_ATOMIC_LOAD_AND_I8_POSTRA_ATOMIC_LOAD_MAX_I16_POSTRA_ATOMIC_LOAD_MAX_I32_POSTRA_ATOMIC_LOAD_MAX_I64_POSTRA_ATOMIC_LOAD_MAX_I8_POSTRA_ATOMIC_LOAD_MIN_I16_POSTRA_ATOMIC_LOAD_MIN_I32_POSTRA_ATOMIC_LOAD_MIN_I64_POSTRA_ATOMIC_LOAD_MIN_I8_POSTRA_ATOMIC_LOAD_NAND_I16_POSTRA_ATOMIC_LOAD_NAND_I32_POSTRA_ATOMIC_LOAD_NAND_I64_POSTRA_ATOMIC_LOAD_NAND_I8_POSTRA_ATOMIC_LOAD_OR_I16_POSTRA_ATOMIC_LOAD_OR_I32_POSTRA_ATOMIC_LOAD_OR_I64_POSTRA_ATOMIC_LOAD_OR_I8_POSTRA_ATOMIC_LOAD_SUB_I16_POSTRA_ATOMIC_LOAD_SUB_I32_POSTRA_ATOMIC_LOAD_SUB_I64_POSTRA_ATOMIC_LOAD_SUB_I8_POSTRA_ATOMIC_LOAD_UMAX_I16_POSTRA_ATOMIC_LOAD_UMAX_I32_POSTRA_ATOMIC_LOAD_UMAX_I64_POSTRA_ATOMIC_LOAD_UMAX_I8_POSTRA_ATOMIC_LOAD_UMIN_I16_POSTRA_ATOMIC_LOAD_UMIN_I32_POSTRA_ATOMIC_LOAD_UMIN_I64_POSTRA_ATOMIC_LOAD_UMIN_I8_POSTRA_ATOMIC_LOAD_XOR_I16_POSTRA_ATOMIC_LOAD_XOR_I32_POSTRA_ATOMIC_LOAD_XOR_I64_POSTRA_ATOMIC_LOAD_XOR_I8_POSTRA = 723, |
| LEA_ADDiu = 724, |
| ADDIUPC = 725, |
| ALIGN = 726, |
| ALUIPC = 727, |
| AUI = 728, |
| AUIPC = 729, |
| BITSWAP = 730, |
| CLO_R6 = 731, |
| CLZ_R6 = 732, |
| LSA_R6 = 733, |
| SELEQZ_SELNEZ = 734, |
| AddiuRxImmX16_AddiuRxRxImm16_AddiuRxRxImmX16_AddiuRxRyOffMemX16_AddiuRxPcImmX16_AddiuSpImm16_AddiuSpImmX16_AdduRxRyRz16_AndRxRxRy16_CmpRxRy16_CmpiRxImm16_CmpiRxImmX16_LiRxImm16_LiRxImmX16_LiRxImmAlignX16_Move32R16_MoveR3216_Mfhi16_Mflo16_NegRxRy16_NotRxRy16_OrRxRxRy16_SebRx16_SehRx16_SllX16_SllvRxRy16_SltiRxImm16_SltiRxImmX16_SltiuRxImm16_SltiuRxImmX16_SltRxRy16_SltuRxRy16_SravRxRy16_SraX16_SrlvRxRy16_SrlX16_SubuRxRyRz16_XorRxRxRy16 = 735, |
| SltiCCRxImmX16_SltiuCCRxImmX16_SltCCRxRy16_SltuRxRyRz16_SltuCCRxRy16 = 736, |
| Constant32_LwConstant32_GotPrologue16_CONSTPOOL_ENTRY = 737, |
| ADDIUPC_MM_ADDIUR1SP_MM_ADDIUR2_MM_ADDIUS5_MM_ADDIUSP_MM_ADDiu_MM_LEA_ADDiu_MM = 738, |
| ADDU16_MM_ADDu_MM = 739, |
| ADD_MM = 740, |
| ADDi_MM = 741, |
| AND16_MM_ANDI16_MM_AND_MM = 742, |
| ANDi_MM = 743, |
| CLO_MM = 744, |
| CLZ_MM = 745, |
| EXT_MM = 746, |
| INS_MM = 747, |
| LI16_MM = 748, |
| LUi_MM = 749, |
| MOVE16_MM = 750, |
| MOVEP_MM = 751, |
| NOR_MM = 752, |
| NOT16_MM = 753, |
| OR16_MM_OR_MM = 754, |
| ORi_MM = 755, |
| ROTRV_MM = 756, |
| ROTR_MM = 757, |
| SEB_MM = 758, |
| SEH_MM = 759, |
| SLL16_MM_SLL_MM = 760, |
| SLLV_MM = 761, |
| SLT_MM_SLTu_MM = 762, |
| SLTi_MM_SLTiu_MM = 763, |
| SRAV_MM = 764, |
| SRA_MM = 765, |
| SRL16_MM_SRL_MM = 766, |
| SRLV_MM = 767, |
| SSNOP_MM = 768, |
| SUBU16_MM_SUBu_MM = 769, |
| SUB_MM = 770, |
| WSBH_MM = 771, |
| XOR16_MM_XOR_MM = 772, |
| XORi_MM = 773, |
| ADDIUPC_MMR6 = 774, |
| ADDIU_MMR6 = 775, |
| ADDU16_MMR6_ADDU_MMR6 = 776, |
| ADD_MMR6 = 777, |
| ALIGN_MMR6 = 778, |
| ALUIPC_MMR6 = 779, |
| AND16_MMR6_ANDI16_MMR6_AND_MMR6 = 780, |
| ANDI_MMR6 = 781, |
| AUIPC_MMR6 = 782, |
| AUI_MMR6 = 783, |
| BITSWAP_MMR6 = 784, |
| CLO_MMR6 = 785, |
| CLZ_MMR6 = 786, |
| EXT_MMR6 = 787, |
| INS_MMR6 = 788, |
| LI16_MMR6 = 789, |
| LSA_MMR6 = 790, |
| LUI_MMR6 = 791, |
| MOVE16_MMR6 = 792, |
| NOR_MMR6 = 793, |
| NOT16_MMR6 = 794, |
| OR16_MMR6_OR_MMR6 = 795, |
| ORI_MMR6 = 796, |
| SELEQZ_MMR6_SELNEZ_MMR6 = 797, |
| SLL16_MMR6_SLL_MMR6 = 798, |
| SRL16_MMR6 = 799, |
| SSNOP_MMR6 = 800, |
| SUBU16_MMR6_SUBU_MMR6 = 801, |
| SUB_MMR6 = 802, |
| WSBH_MMR6 = 803, |
| XOR16_MMR6_XOR_MMR6 = 804, |
| XORI_MMR6 = 805, |
| AND64_ANDi64 = 806, |
| DEXT64_32 = 807, |
| DSLL64_32 = 808, |
| ORi64 = 809, |
| SEB64 = 810, |
| SEH64 = 811, |
| SLL64_32_SLL64_64 = 812, |
| SLT64_SLTu64 = 813, |
| SLTi64_SLTiu64 = 814, |
| XOR64_XORi64 = 815, |
| DADD = 816, |
| DADDi = 817, |
| DADDiu = 818, |
| DADDu = 819, |
| DCLO = 820, |
| DCLZ = 821, |
| DEXT_DEXTM_DEXTU = 822, |
| DINS_DINSM_DINSU = 823, |
| DROTR = 824, |
| DROTR32 = 825, |
| DROTRV = 826, |
| DSBH = 827, |
| DSHD = 828, |
| DSLL = 829, |
| DSLL32 = 830, |
| DSLLV = 831, |
| DSRA = 832, |
| DSRA32 = 833, |
| DSRAV = 834, |
| DSRL = 835, |
| DSRL32 = 836, |
| DSRLV = 837, |
| DSUB = 838, |
| DSUBu = 839, |
| LEA_ADDiu64 = 840, |
| LUi64 = 841, |
| NOR64 = 842, |
| OR64 = 843, |
| DALIGN = 844, |
| DAHI = 845, |
| DATI = 846, |
| DAUI = 847, |
| DCLO_R6 = 848, |
| DCLZ_R6 = 849, |
| DBITSWAP = 850, |
| DLSA_DLSA_R6 = 851, |
| SELEQZ64_SELNEZ64 = 852, |
| MADD = 853, |
| MADDU = 854, |
| MSUB = 855, |
| MSUBU = 856, |
| PseudoMADD_MM = 857, |
| PseudoMADDU_MM = 858, |
| PseudoMSUB_MM = 859, |
| PseudoMSUBU_MM = 860, |
| PseudoMULT_MM = 861, |
| PseudoMULTu_MM = 862, |
| PseudoMULT = 863, |
| PseudoMULTu = 864, |
| PseudoSDIV_SDIV = 865, |
| PseudoUDIV_UDIV = 866, |
| PseudoMFHI_MM_PseudoMFLO_MM = 867, |
| PseudoMTLOHI_MM = 868, |
| MUH = 869, |
| MUHU = 870, |
| MULU = 871, |
| MUL_R6 = 872, |
| MOD = 873, |
| MODU = 874, |
| MultRxRy16_MultuRxRy16_MultRxRyRz16_MultuRxRyRz16 = 875, |
| DivRxRy16 = 876, |
| DivuRxRy16 = 877, |
| MULT_MM = 878, |
| MULTu_MM = 879, |
| MADD_MM = 880, |
| MADDU_MM = 881, |
| MSUB_MM = 882, |
| MSUBU_MM = 883, |
| MUL_MM = 884, |
| SDIV_MM_SDIV_MM_Pseudo = 885, |
| UDIV_MM_UDIV_MM_Pseudo = 886, |
| MFHI16_MM_MFLO16_MM_MFHI_MM_MFLO_MM = 887, |
| MOVF_I_MM = 888, |
| MOVT_I_MM = 889, |
| MTHI_MM_MTLO_MM = 890, |
| RDHWR_MM = 891, |
| MUHU_MMR6 = 892, |
| MUH_MMR6 = 893, |
| MULU_MMR6 = 894, |
| MUL_MMR6 = 895, |
| MODU_MMR6 = 896, |
| MOD_MMR6 = 897, |
| DIVU_MMR6 = 898, |
| DIV_MMR6 = 899, |
| RDHWR_MMR6 = 900, |
| DMULU = 901, |
| DMULT_PseudoDMULT = 902, |
| DMULTu_PseudoDMULTu = 903, |
| DSDIV_PseudoDSDIV = 904, |
| DUDIV_PseudoDUDIV = 905, |
| MFHI64_MFLO64_PseudoMFHI64_PseudoMFLO64 = 906, |
| PseudoMTLOHI64 = 907, |
| MTHI64_MTLO64 = 908, |
| RDHWR64 = 909, |
| MOVN_I_I64_MOVN_I64_I_MOVN_I64_I64 = 910, |
| MOVZ_I_I64_MOVZ_I64_I_MOVZ_I64_I64 = 911, |
| DMUH = 912, |
| DMUHU = 913, |
| DMUL_R6 = 914, |
| DDIV = 915, |
| DMOD = 916, |
| DDIVU = 917, |
| DMODU = 918, |
| BAL_BR_BLTZAL = 919, |
| BEQ_BNE = 920, |
| BGTZ_BGEZ_BLEZ_BLTZ = 921, |
| J = 922, |
| JR = 923, |
| ERet = 924, |
| BGEZAL = 925, |
| BALC = 926, |
| BEQZALC_BGEZALC_BGTZALC_BLEZALC_BLTZALC_BNEZALC = 927, |
| JIALC = 928, |
| BC = 929, |
| BC2EQZ_BC2NEZ = 930, |
| BEQC_BGEC_BGEUC_BLTC_BLTUC_BNEC_BNVC_BOVC = 931, |
| BEQZC_BGEZC_BGTZC_BLEZC_BLTZC_BNEZC = 932, |
| JIC = 933, |
| JR_HB_R6 = 934, |
| SIGRIE = 935, |
| PseudoIndirectBranchR6_PseudoIndrectHazardBranchR6 = 936, |
| TAILCALLR6REG_TAILCALLHBR6REG = 937, |
| SDBBP_R6 = 938, |
| Bimm16_BimmX16_BeqzRxImm16_BeqzRxImmX16_BnezRxImm16_BnezRxImmX16_Bteqz16_BteqzX16_Btnez16_BtnezX16_JrRa16_JrcRa16_JrcRx16 = 939, |
| BteqzT8CmpX16_BteqzT8CmpiX16_BteqzT8SltX16_BteqzT8SltuX16_BteqzT8SltiX16_BteqzT8SltiuX16_BtnezT8CmpX16_BtnezT8CmpiX16_BtnezT8SltX16_BtnezT8SltuX16_BtnezT8SltiX16_BtnezT8SltiuX16_RetRA16 = 940, |
| Jal16_JalB16 = 941, |
| JumpLinkReg16 = 942, |
| Break16 = 943, |
| SelBeqZ_SelTBteqZCmp_SelTBteqZCmpi_SelTBteqZSlt_SelTBteqZSlti_SelTBteqZSltu_SelTBteqZSltiu_SelBneZ_SelTBtneZCmp_SelTBtneZCmpi_SelTBtneZSlt_SelTBtneZSlti_SelTBtneZSltu_SelTBtneZSltiu = 944, |
| B16_MM_B_MM = 945, |
| BAL_BR_MM = 946, |
| BC1F_MM = 947, |
| BC1T_MM = 948, |
| BEQZ16_MM_BGEZ_MM_BGTZ_MM_BLEZ_MM_BLTZ_MM_BNEZ16_MM = 949, |
| BEQZC_MM_BNEZC_MM = 950, |
| BEQ_MM_BNE_MM = 951, |
| DERET_MM = 952, |
| ERET_MM = 953, |
| JR16_MM_JR_MM = 954, |
| J_MM = 955, |
| B_MM_Pseudo = 956, |
| BGEZALS_MM_BLTZALS_MM = 957, |
| BGEZAL_MM_BLTZAL_MM = 958, |
| JALR16_MM_JALR_MM = 959, |
| JALRS16_MM_JALRS_MM = 960, |
| JALS_MM = 961, |
| JALX_MM_JAL_MM = 962, |
| TAILCALLREG_MM = 963, |
| TAILCALL_MM = 964, |
| PseudoIndirectBranch_MM = 965, |
| BREAK16_MM_BREAK_MM = 966, |
| SDBBP16_MM_SDBBP_MM = 967, |
| SYSCALL_MM = 968, |
| TEQI_MM = 969, |
| TEQ_MM = 970, |
| TGEIU_MM = 971, |
| TGEI_MM = 972, |
| TGEU_MM = 973, |
| TGE_MM = 974, |
| TLTIU_MM = 975, |
| TLTI_MM = 976, |
| TLTU_MM = 977, |
| TLT_MM = 978, |
| TNEI_MM = 979, |
| TNE_MM = 980, |
| TRAP_MM = 981, |
| BC16_MMR6_BC_MMR6 = 982, |
| BC1EQZC_MMR6_BC1NEZC_MMR6 = 983, |
| BC2EQZC_MMR6_BC2NEZC_MMR6 = 984, |
| BEQC_MMR6_BGEC_MMR6_BGEUC_MMR6_BLTC_MMR6_BLTUC_MMR6_BNEC_MMR6_BNVC_MMR6_BOVC_MMR6 = 985, |
| BEQZC16_MMR6_BNEZC16_MMR6 = 986, |
| BEQZC_MMR6_BGEZC_MMR6_BGTZC_MMR6_BLEZC_MMR6_BLTZC_MMR6_BNEZC_MMR6 = 987, |
| DERET_MMR6 = 988, |
| ERETNC_MMR6 = 989, |
| JAL_MMR6 = 990, |
| ERET_MMR6 = 991, |
| JIC_MMR6 = 992, |
| JRADDIUSP_JRCADDIUSP_MMR6 = 993, |
| JRC16_MM = 994, |
| JRC16_MMR6 = 995, |
| SIGRIE_MMR6 = 996, |
| B_MMR6_Pseudo = 997, |
| PseudoIndirectBranch_MMR6 = 998, |
| BALC_MMR6 = 999, |
| BEQZALC_MMR6_BGEZALC_MMR6_BGTZALC_MMR6_BLEZALC_MMR6_BLTZALC_MMR6_BNEZALC_MMR6 = 1000, |
| JALRC16_MMR6 = 1001, |
| JALRC_HB_MMR6 = 1002, |
| JALRC_MMR6 = 1003, |
| JIALC_MMR6 = 1004, |
| TAILCALLREG_MMR6 = 1005, |
| TAILCALL_MMR6 = 1006, |
| BREAK16_MMR6_BREAK_MMR6 = 1007, |
| SDBBP_MMR6_SDBBP16_MMR6 = 1008, |
| BEQ64_BNE64 = 1009, |
| BGEZ64_BGTZ64_BLEZ64_BLTZ64 = 1010, |
| JR64 = 1011, |
| JALR64_JALR64Pseudo_JALRHB64Pseudo = 1012, |
| JALR_HB64 = 1013, |
| JR_HB64 = 1014, |
| TAILCALLREG64_TAILCALLREGHB64 = 1015, |
| PseudoReturn64 = 1016, |
| BEQC64_BGEC64_BGEUC64_BLTC64_BLTUC64_BNEC64 = 1017, |
| BEQZC64_BGEZC64_BGTZC64_BLEZC64_BLTZC64_BNEZC64 = 1018, |
| JIC64 = 1019, |
| PseudoIndirectBranch64_PseudoIndirectHazardBranch64 = 1020, |
| JIALC64 = 1021, |
| JR_HB64_R6 = 1022, |
| TAILCALL64R6REG_TAILCALLHB64R6REG = 1023, |
| PseudoIndirectBranch64R6_PseudoIndrectHazardBranch64R6 = 1024, |
| EVP = 1025, |
| DVP = 1026, |
| TLBP_MM = 1027, |
| TLBR_MM = 1028, |
| TLBWI_MM = 1029, |
| TLBWR_MM = 1030, |
| DI_MM = 1031, |
| EI_MM = 1032, |
| EHB_MM = 1033, |
| PAUSE_MM = 1034, |
| WAIT_MM = 1035, |
| RDPGPR_MMR6 = 1036, |
| WRPGPR_MMR6 = 1037, |
| TLBINV_MMR6 = 1038, |
| TLBINVF_MMR6 = 1039, |
| MFHC0_MMR6 = 1040, |
| MFC0_MMR6 = 1041, |
| MFHC2_MMR6_MFC2_MMR6 = 1042, |
| MTHC0_MMR6 = 1043, |
| MTC0_MMR6 = 1044, |
| MTHC2_MMR6_MTC2_MMR6 = 1045, |
| EVP_MMR6 = 1046, |
| DVP_MMR6 = 1047, |
| DI_MMR6 = 1048, |
| EI_MMR6 = 1049, |
| EHB_MMR6 = 1050, |
| PAUSE_MMR6 = 1051, |
| WAIT_MMR6 = 1052, |
| DMFC0 = 1053, |
| DMTC0 = 1054, |
| DMFC2 = 1055, |
| DMTC2 = 1056, |
| CFC2_MM = 1057, |
| CTC2_MM = 1058, |
| DMT = 1059, |
| DVPE = 1060, |
| EMT = 1061, |
| EVPE = 1062, |
| MFTR = 1063, |
| MTTR = 1064, |
| YIELD = 1065, |
| FORK = 1066, |
| DMFGC0 = 1067, |
| DMTGC0 = 1068, |
| HYPCALL_MM = 1069, |
| TLBGINVF_MM = 1070, |
| TLBGINV_MM = 1071, |
| TLBGP_MM = 1072, |
| TLBGR_MM = 1073, |
| TLBGWI_MM = 1074, |
| TLBGWR_MM = 1075, |
| MFGC0_MM = 1076, |
| MFHGC0_MM = 1077, |
| MTGC0_MM = 1078, |
| MTHGC0_MM = 1079, |
| SC_MMR6 = 1080, |
| LDC2_R6 = 1081, |
| LL_R6 = 1082, |
| LWC2_R6 = 1083, |
| SWC2_R6 = 1084, |
| SDC2_R6 = 1085, |
| SC_R6 = 1086, |
| PREF_R6 = 1087, |
| CACHE_R6 = 1088, |
| GINVI = 1089, |
| GINVT = 1090, |
| LBE_MM = 1091, |
| LBuE_MM = 1092, |
| LHE_MM = 1093, |
| LHuE_MM = 1094, |
| LWE_MM = 1095, |
| LWLE_MM = 1096, |
| LWRE_MM = 1097, |
| LLE_MM = 1098, |
| SBE_MM = 1099, |
| SB_MM = 1100, |
| SHE_MM = 1101, |
| SWE_MM = 1102, |
| SWLE_MM = 1103, |
| SWRE_MM = 1104, |
| SCE_MM = 1105, |
| PREFE_MM = 1106, |
| CACHEE_MM = 1107, |
| Restore16_RestoreX16 = 1108, |
| LbRxRyOffMemX16 = 1109, |
| LbuRxRyOffMemX16 = 1110, |
| LhRxRyOffMemX16 = 1111, |
| LhuRxRyOffMemX16 = 1112, |
| LwRxRyOffMemX16_LwRxSpImmX16_LwRxPcTcp16_LwRxPcTcpX16 = 1113, |
| Save16_SaveX16 = 1114, |
| SbRxRyOffMemX16 = 1115, |
| ShRxRyOffMemX16 = 1116, |
| SwRxRyOffMemX16_SwRxSpImmX16 = 1117, |
| LBU16_MM_LBu_MM = 1118, |
| LB_MM = 1119, |
| LHU16_MM_LHu_MM = 1120, |
| LH_MM = 1121, |
| LL_MM = 1122, |
| LW16_MM_LWGP_MM_LWSP_MM_LW_MM = 1123, |
| LWL_MM = 1124, |
| LWM16_MM_LWM32_MM = 1125, |
| LWP_MM = 1126, |
| LWR_MM = 1127, |
| LWU_MM = 1128, |
| LWXS_MM = 1129, |
| SB16_MM = 1130, |
| SC_MM = 1131, |
| SH16_MM_SH_MM = 1132, |
| SW16_MM_SWSP_MM_SW_MM = 1133, |
| SWL_MM = 1134, |
| SWM16_MM_SWM32_MM = 1135, |
| SWM_MM = 1136, |
| SWP_MM = 1137, |
| SWR_MM = 1138, |
| PREF_MM_PREFX_MM = 1139, |
| CACHE_MM = 1140, |
| SYNC_MM = 1141, |
| SYNCI_MM = 1142, |
| GINVI_MMR6 = 1143, |
| GINVT_MMR6 = 1144, |
| LBU_MMR6 = 1145, |
| LB_MMR6 = 1146, |
| LDC2_MMR6 = 1147, |
| LL_MMR6 = 1148, |
| LWM16_MMR6 = 1149, |
| LWC2_MMR6 = 1150, |
| LWPC_MMR6 = 1151, |
| LW_MMR6 = 1152, |
| SB16_MMR6_SB_MMR6 = 1153, |
| SDC2_MMR6 = 1154, |
| SH16_MMR6_SH_MMR6 = 1155, |
| SW16_MMR6_SWSP_MMR6_SW_MMR6 = 1156, |
| SWC2_MMR6 = 1157, |
| SWM16_MMR6 = 1158, |
| SYNC_MMR6 = 1159, |
| SYNCI_MMR6 = 1160, |
| PREF_MMR6 = 1161, |
| CACHE_MMR6 = 1162, |
| LD = 1163, |
| LL64_LLD = 1164, |
| LWu = 1165, |
| LB64 = 1166, |
| LBu64 = 1167, |
| LH64 = 1168, |
| LHu64 = 1169, |
| LW64 = 1170, |
| LWL64 = 1171, |
| LWR64 = 1172, |
| LDL = 1173, |
| LDR = 1174, |
| SD = 1175, |
| SC64_SCD = 1176, |
| SB64 = 1177, |
| SH64 = 1178, |
| SW64 = 1179, |
| SWL64 = 1180, |
| SWR64 = 1181, |
| SDL = 1182, |
| SDR = 1183, |
| LWUPC = 1184, |
| LDPC = 1185, |
| LLD_R6 = 1186, |
| LL64_R6 = 1187, |
| SC64_R6 = 1188, |
| SCD_R6 = 1189, |
| CRC32B = 1190, |
| CRC32H = 1191, |
| CRC32W = 1192, |
| CRC32CB = 1193, |
| CRC32CH = 1194, |
| CRC32CW = 1195, |
| CRC32D = 1196, |
| CRC32CD = 1197, |
| BADDu = 1198, |
| BBIT0_BBIT032_BBIT1_BBIT132 = 1199, |
| CINS_CINS32_CINS64_32_CINS_i32 = 1200, |
| DMFC2_OCTEON = 1201, |
| DMTC2_OCTEON = 1202, |
| DPOP_POP = 1203, |
| EXTS_EXTS32 = 1204, |
| MTM0_MTM1_MTM2_MTP0_MTP1_MTP2 = 1205, |
| SEQ_SNE = 1206, |
| SEQi_SNEi = 1207, |
| V3MULU_VMM0_VMULU = 1208, |
| DMUL = 1209, |
| SAA_SAAD = 1210, |
| ADDR_PS64 = 1211, |
| CVT_PS_PW64_CVT_PW_PS64 = 1212, |
| MULR_PS64 = 1213, |
| PseudoTRUNC_W_D_PseudoTRUNC_W_D32_PseudoTRUNC_W_S = 1214, |
| MOVT_I64 = 1215, |
| MOVF_I64 = 1216, |
| MOVZ_I64_S = 1217, |
| MOVN_I64_D64 = 1218, |
| MOVN_I64_S = 1219, |
| MOVZ_I64_D64 = 1220, |
| SELEQZ_S_SELNEZ_S = 1221, |
| SELEQZ_D_SELNEZ_D = 1222, |
| MAX_S_MAXA_S = 1223, |
| MAX_D_MAXA_D = 1224, |
| MIN_S_MINA_D = 1225, |
| MIN_D_MINA_S = 1226, |
| CLASS_S = 1227, |
| CLASS_D = 1228, |
| RINT_S = 1229, |
| RINT_D = 1230, |
| BC1EQZ_BC1NEZ = 1231, |
| SEL_D = 1232, |
| SEL_S = 1233, |
| MADDF_S = 1234, |
| MSUBF_S = 1235, |
| MADDF_D = 1236, |
| MSUBF_D = 1237, |
| MOVF_D32_MM = 1238, |
| MOVF_S_MM = 1239, |
| MOVN_I_D32_MM = 1240, |
| MOVN_I_S_MM = 1241, |
| MOVT_D32_MM = 1242, |
| MOVT_S_MM = 1243, |
| MOVZ_I_D32_MM = 1244, |
| MOVZ_I_S_MM = 1245, |
| CVT_D32_S_MM_CVT_D32_W_MM_CVT_D64_S_MM_CVT_D64_W_MM_CVT_L_D64_MM_CVT_L_S_MM_CVT_S_D32_MM_CVT_S_D64_MM_CVT_S_W_MM_CVT_W_D32_MM_CVT_W_D64_MM_CVT_W_S_MM = 1246, |
| CEIL_W_MM_CEIL_W_S_MM = 1247, |
| FLOOR_W_MM_FLOOR_W_S_MM = 1248, |
| NMADD_S_MM = 1249, |
| NMADD_D32_MM = 1250, |
| NMSUB_S_MM = 1251, |
| NMSUB_D32_MM = 1252, |
| MADD_S_MM = 1253, |
| MADD_D32_MM = 1254, |
| ROUND_W_MM_ROUND_W_S_MM = 1255, |
| TRUNC_W_MM_TRUNC_W_S_MM = 1256, |
| C_F_D32_MM_C_F_D64_MM = 1257, |
| C_F_S_MM = 1258, |
| C_EQ_D32_MM_C_EQ_D64_MM_C_LE_D32_MM_C_LE_D64_MM_C_LT_D32_MM_C_LT_D64_MM_C_SF_D32_MM_C_SF_D64_MM_C_UN_D32_MM_C_UN_D64_MM = 1259, |
| C_EQ_S_MM_C_LE_S_MM_C_LT_S_MM_C_SF_S_MM_C_UN_S_MM = 1260, |
| C_NGE_D32_MM_C_NGE_D64_MM_C_NGL_D32_MM_C_NGL_D64_MM_C_NGT_D32_MM_C_NGT_D64_MM_C_OLE_D32_MM_C_OLE_D64_MM_C_OLT_D32_MM_C_OLT_D64_MM_C_SEQ_D32_MM_C_SEQ_D64_MM_C_UEQ_D32_MM_C_UEQ_D64_MM_C_ULE_D32_MM_C_ULE_D64_MM_C_ULT_D32_MM_C_ULT_D64_MM = 1261, |
| C_NGE_S_MM_C_NGL_S_MM_C_NGT_S_MM_C_OLE_S_MM_C_OLT_S_MM_C_SEQ_S_MM_C_UEQ_S_MM_C_ULE_S_MM_C_ULT_S_MM = 1262, |
| C_NGLE_D32_MM_C_NGLE_D64_MM = 1263, |
| C_NGLE_S_MM = 1264, |
| FCMP_S32_MM = 1265, |
| FCMP_D32_MM = 1266, |
| MFC1_MM = 1267, |
| MFHC1_D32_MM_MFHC1_D64_MM = 1268, |
| MTC1_MM_MTC1_D64_MM = 1269, |
| MTHC1_D32_MM_MTHC1_D64_MM = 1270, |
| FABS_D32_MM_FABS_D64_MM = 1271, |
| FABS_S_MM = 1272, |
| FNEG_D32_MM_FNEG_D64_MM_FNEG_S_MM = 1273, |
| FADD_D32_MM_FADD_D64_MM = 1274, |
| FADD_S_MM = 1275, |
| FMOV_D32_MM_FMOV_D64_MM = 1276, |
| FMOV_S_MM = 1277, |
| FMUL_D32_MM_FMUL_D64_MM = 1278, |
| FMUL_S_MM = 1279, |
| FSUB_D32_MM_FSUB_D64_MM = 1280, |
| FSUB_S_MM = 1281, |
| MSUB_S_MM = 1282, |
| MSUB_D32_MM = 1283, |
| FDIV_S_MM = 1284, |
| FDIV_D32_MM_FDIV_D64_MM = 1285, |
| FSQRT_S_MM = 1286, |
| FSQRT_D32_MM_FSQRT_D64_MM = 1287, |
| RECIP_S_MM_RSQRT_S_MM = 1288, |
| RECIP_D32_MM_RECIP_D64_MM_RSQRT_D32_MM_RSQRT_D64_MM = 1289, |
| SDC1_MM_D32_SDC1_MM_D64 = 1290, |
| SWC1_MM = 1291, |
| SUXC1_MM = 1292, |
| SWXC1_MM = 1293, |
| CFC1_MM = 1294, |
| CTC1_MM = 1295, |
| LDC1_MM_D32_LDC1_MM_D64 = 1296, |
| LUXC1_MM = 1297, |
| LWC1_MM = 1298, |
| LWXC1_MM = 1299, |
| FNEG_S_MMR6 = 1300, |
| CMP_AF_D_MMR6_CMP_EQ_D_MMR6_CMP_LE_D_MMR6_CMP_LT_D_MMR6_CMP_UN_D_MMR6 = 1301, |
| CMP_AF_S_MMR6_CMP_EQ_S_MMR6_CMP_LE_S_MMR6_CMP_LT_S_MMR6_CMP_UN_S_MMR6 = 1302, |
| CMP_SAF_D_MMR6_CMP_SEQ_D_MMR6_CMP_SLE_D_MMR6_CMP_SLT_D_MMR6_CMP_SUN_D_MMR6_CMP_UEQ_D_MMR6_CMP_ULE_D_MMR6_CMP_ULT_D_MMR6 = 1303, |
| CMP_SAF_S_MMR6_CMP_SEQ_S_MMR6_CMP_SLE_S_MMR6_CMP_SLT_S_MMR6_CMP_SUN_S_MMR6_CMP_UEQ_S_MMR6_CMP_ULE_S_MMR6_CMP_ULT_S_MMR6 = 1304, |
| CMP_SUEQ_D_MMR6_CMP_SULE_D_MMR6_CMP_SULT_D_MMR6 = 1305, |
| CMP_SUEQ_S_MMR6_CMP_SULE_S_MMR6_CMP_SULT_S_MMR6 = 1306, |
| CVT_D_L_MMR6_CVT_L_D_MMR6_CVT_L_S_MMR6_CVT_S_L_MMR6_CVT_S_W_MMR6_CVT_W_S_MMR6 = 1307, |
| TRUNC_L_D_MMR6_TRUNC_L_S_MMR6_TRUNC_W_D_MMR6_TRUNC_W_S_MMR6 = 1308, |
| ROUND_L_D_MMR6_ROUND_L_S_MMR6_ROUND_W_D_MMR6_ROUND_W_S_MMR6 = 1309, |
| FLOOR_L_D_MMR6_FLOOR_L_S_MMR6_FLOOR_W_D_MMR6_FLOOR_W_S_MMR6 = 1310, |
| CEIL_L_D_MMR6_CEIL_L_S_MMR6_CEIL_W_D_MMR6_CEIL_W_S_MMR6 = 1311, |
| MFC1_MMR6 = 1312, |
| MTC1_MMR6 = 1313, |
| CLASS_S_MMR6_CLASS_D_MMR6 = 1314, |
| FADD_S_MMR6 = 1315, |
| MAX_D_MMR6 = 1316, |
| MAX_S_MMR6 = 1317, |
| MIN_D_MMR6 = 1318, |
| MIN_S_MMR6 = 1319, |
| MAXA_D_MMR6 = 1320, |
| MAXA_S_MMR6 = 1321, |
| MINA_D_MMR6 = 1322, |
| MINA_S_MMR6 = 1323, |
| SELEQZ_D_MMR6_SELNEZ_D_MMR6 = 1324, |
| SELEQZ_S_MMR6_SELNEZ_S_MMR6 = 1325, |
| SEL_D_MMR6 = 1326, |
| SEL_S_MMR6 = 1327, |
| RINT_S_MMR6_RINT_D_MMR6 = 1328, |
| MADDF_D_MMR6 = 1329, |
| MADDF_S_MMR6 = 1330, |
| MSUBF_D_MMR6 = 1331, |
| MSUBF_S_MMR6 = 1332, |
| FMOV_S_MMR6 = 1333, |
| FMUL_S_MMR6 = 1334, |
| FSUB_S_MMR6 = 1335, |
| FMOV_D_MMR6 = 1336, |
| FDIV_S_MMR6 = 1337, |
| SDC1_D64_MMR6 = 1338, |
| LDC1_D64_MMR6 = 1339, |
| DMFC1 = 1340, |
| DMTC1 = 1341, |
| SWDSP = 1342, |
| LWDSP = 1343, |
| PseudoMTLOHI_DSP = 1344, |
| EXTRV_RS_W = 1345, |
| EXTRV_R_W = 1346, |
| EXTRV_S_H = 1347, |
| EXTRV_W = 1348, |
| EXTR_RS_W = 1349, |
| EXTR_R_W = 1350, |
| EXTR_S_H = 1351, |
| EXTR_W = 1352, |
| INSV = 1353, |
| MTHLIP = 1354, |
| MTHI_DSP = 1355, |
| MTLO_DSP = 1356, |
| ABSQ_S_PH = 1357, |
| ABSQ_S_W = 1358, |
| ADDQ_PH = 1359, |
| ADDQ_S_PH = 1360, |
| ADDQ_S_W = 1361, |
| ADDSC = 1362, |
| ADDU_QB = 1363, |
| ADDU_S_QB = 1364, |
| ADDWC = 1365, |
| BITREV = 1366, |
| BPOSGE32 = 1367, |
| CMPGU_EQ_QB = 1368, |
| CMPGU_LE_QB = 1369, |
| CMPGU_LT_QB = 1370, |
| CMPU_EQ_QB = 1371, |
| CMPU_LE_QB = 1372, |
| CMPU_LT_QB = 1373, |
| CMP_EQ_PH = 1374, |
| CMP_LE_PH = 1375, |
| CMP_LT_PH = 1376, |
| DPAQ_SA_L_W = 1377, |
| DPAQ_S_W_PH = 1378, |
| DPAU_H_QBL = 1379, |
| DPAU_H_QBR = 1380, |
| DPSQ_SA_L_W = 1381, |
| DPSQ_S_W_PH = 1382, |
| DPSU_H_QBL = 1383, |
| DPSU_H_QBR = 1384, |
| EXTPDPV = 1385, |
| EXTPDP = 1386, |
| EXTPV = 1387, |
| EXTP = 1388, |
| LBUX = 1389, |
| LHX = 1390, |
| LWX = 1391, |
| MADDU_DSP = 1392, |
| MADD_DSP = 1393, |
| MAQ_SA_W_PHL = 1394, |
| MAQ_SA_W_PHR = 1395, |
| MAQ_S_W_PHL = 1396, |
| MAQ_S_W_PHR = 1397, |
| MFHI_DSP = 1398, |
| MFLO_DSP = 1399, |
| MODSUB = 1400, |
| MSUBU_DSP = 1401, |
| MSUB_DSP = 1402, |
| MULEQ_S_W_PHL = 1403, |
| MULEQ_S_W_PHR = 1404, |
| MULEU_S_PH_QBL = 1405, |
| MULEU_S_PH_QBR = 1406, |
| MULQ_RS_PH = 1407, |
| MULSAQ_S_W_PH = 1408, |
| MULTU_DSP = 1409, |
| MULT_DSP = 1410, |
| PACKRL_PH = 1411, |
| PICK_PH = 1412, |
| PICK_QB = 1413, |
| PRECEQU_PH_QBLA = 1414, |
| PRECEQU_PH_QBL = 1415, |
| PRECEQU_PH_QBRA = 1416, |
| PRECEQU_PH_QBR = 1417, |
| PRECEQ_W_PHL = 1418, |
| PRECEQ_W_PHR = 1419, |
| PRECEU_PH_QBLA = 1420, |
| PRECEU_PH_QBL = 1421, |
| PRECEU_PH_QBRA = 1422, |
| PRECEU_PH_QBR = 1423, |
| PRECRQU_S_QB_PH = 1424, |
| PRECRQ_PH_W = 1425, |
| PRECRQ_QB_PH = 1426, |
| PRECRQ_RS_PH_W = 1427, |
| RADDU_W_QB = 1428, |
| RDDSP = 1429, |
| REPLV_PH = 1430, |
| REPLV_QB = 1431, |
| REPL_PH = 1432, |
| REPL_QB = 1433, |
| SHILOV = 1434, |
| SHILO = 1435, |
| SHLLV_PH = 1436, |
| SHLLV_QB = 1437, |
| SHLLV_S_PH = 1438, |
| SHLLV_S_W = 1439, |
| SHLL_PH = 1440, |
| SHLL_QB = 1441, |
| SHLL_S_PH = 1442, |
| SHLL_S_W = 1443, |
| SHRAV_PH = 1444, |
| SHRAV_R_PH = 1445, |
| SHRAV_R_W = 1446, |
| SHRA_PH = 1447, |
| SHRA_R_PH = 1448, |
| SHRA_R_W = 1449, |
| SHRLV_QB = 1450, |
| SHRL_QB = 1451, |
| SUBQ_PH = 1452, |
| SUBQ_S_PH = 1453, |
| SUBQ_S_W = 1454, |
| SUBU_QB = 1455, |
| SUBU_S_QB = 1456, |
| WRDSP = 1457, |
| PseudoCMPU_EQ_QB_PseudoCMPU_LE_QB_PseudoCMPU_LT_QB_PseudoCMP_EQ_PH_PseudoCMP_LE_PH_PseudoCMP_LT_PH = 1458, |
| PseudoPICK_PH_PseudoPICK_QB = 1459, |
| ABSQ_S_QB = 1460, |
| ADDQH_PH = 1461, |
| ADDQH_R_PH = 1462, |
| ADDQH_R_W = 1463, |
| ADDQH_W = 1464, |
| ADDUH_QB = 1465, |
| ADDUH_R_QB = 1466, |
| ADDU_PH = 1467, |
| ADDU_S_PH = 1468, |
| APPEND = 1469, |
| BALIGN = 1470, |
| CMPGDU_EQ_QB = 1471, |
| CMPGDU_LE_QB = 1472, |
| CMPGDU_LT_QB = 1473, |
| DPA_W_PH = 1474, |
| DPAQX_SA_W_PH = 1475, |
| DPAQX_S_W_PH = 1476, |
| DPAX_W_PH = 1477, |
| DPS_W_PH = 1478, |
| DPSQX_S_W_PH = 1479, |
| DPSQX_SA_W_PH = 1480, |
| DPSX_W_PH = 1481, |
| MUL_PH = 1482, |
| MUL_S_PH = 1483, |
| MULQ_RS_W = 1484, |
| MULQ_S_PH = 1485, |
| MULQ_S_W = 1486, |
| MULSA_W_PH = 1487, |
| PRECR_QB_PH = 1488, |
| PRECR_SRA_PH_W = 1489, |
| PRECR_SRA_R_PH_W = 1490, |
| PREPEND = 1491, |
| SHRA_QB = 1492, |
| SHRA_R_QB = 1493, |
| SHRAV_QB = 1494, |
| SHRAV_R_QB = 1495, |
| SHRL_PH = 1496, |
| SHRLV_PH = 1497, |
| SUBQH_PH = 1498, |
| SUBQH_R_PH = 1499, |
| SUBQH_W = 1500, |
| SUBQH_R_W = 1501, |
| SUBU_PH = 1502, |
| SUBU_S_PH = 1503, |
| SUBUH_QB = 1504, |
| SUBUH_R_QB = 1505, |
| LWDSP_MM = 1506, |
| SWDSP_MM = 1507, |
| ABSQ_S_PH_MM = 1508, |
| ABSQ_S_W_MM = 1509, |
| ADDQ_PH_MM = 1510, |
| ADDQ_S_PH_MM = 1511, |
| ADDQ_S_W_MM = 1512, |
| ADDSC_MM = 1513, |
| ADDU_QB_MM = 1514, |
| ADDU_S_QB_MM = 1515, |
| ADDWC_MM = 1516, |
| BITREV_MM = 1517, |
| BPOSGE32_MM = 1518, |
| CMPGU_EQ_QB_MM = 1519, |
| CMPGU_LE_QB_MM = 1520, |
| CMPGU_LT_QB_MM = 1521, |
| CMPU_EQ_QB_MM = 1522, |
| CMPU_LE_QB_MM = 1523, |
| CMPU_LT_QB_MM = 1524, |
| CMP_EQ_PH_MM = 1525, |
| CMP_LE_PH_MM = 1526, |
| CMP_LT_PH_MM = 1527, |
| DPAQ_SA_L_W_MM = 1528, |
| DPAQ_S_W_PH_MM = 1529, |
| DPAU_H_QBL_MM = 1530, |
| DPAU_H_QBR_MM = 1531, |
| DPSQ_SA_L_W_MM = 1532, |
| DPSQ_S_W_PH_MM = 1533, |
| DPSU_H_QBL_MM = 1534, |
| DPSU_H_QBR_MM = 1535, |
| EXTPDPV_MM = 1536, |
| EXTPDP_MM = 1537, |
| EXTPV_MM = 1538, |
| EXTP_MM = 1539, |
| EXTRV_RS_W_MM = 1540, |
| EXTRV_R_W_MM = 1541, |
| EXTRV_S_H_MM = 1542, |
| EXTRV_W_MM = 1543, |
| EXTR_RS_W_MM = 1544, |
| EXTR_R_W_MM = 1545, |
| EXTR_S_H_MM = 1546, |
| EXTR_W_MM = 1547, |
| INSV_MM = 1548, |
| LBUX_MM = 1549, |
| LHX_MM = 1550, |
| LWX_MM = 1551, |
| MADDU_DSP_MM = 1552, |
| MADD_DSP_MM = 1553, |
| MAQ_SA_W_PHL_MM = 1554, |
| MAQ_SA_W_PHR_MM = 1555, |
| MAQ_S_W_PHL_MM = 1556, |
| MAQ_S_W_PHR_MM = 1557, |
| MFHI_DSP_MM = 1558, |
| MFLO_DSP_MM = 1559, |
| MODSUB_MM = 1560, |
| MOVEP_MMR6 = 1561, |
| MOVN_I_MM = 1562, |
| MOVZ_I_MM = 1563, |
| MSUBU_DSP_MM = 1564, |
| MSUB_DSP_MM = 1565, |
| MTHI_DSP_MM = 1566, |
| MTHLIP_MM = 1567, |
| MTLO_DSP_MM = 1568, |
| MULEQ_S_W_PHL_MM = 1569, |
| MULEQ_S_W_PHR_MM = 1570, |
| MULEU_S_PH_QBL_MM = 1571, |
| MULEU_S_PH_QBR_MM = 1572, |
| MULQ_RS_PH_MM = 1573, |
| MULSAQ_S_W_PH_MM = 1574, |
| MULTU_DSP_MM = 1575, |
| MULT_DSP_MM = 1576, |
| PACKRL_PH_MM = 1577, |
| PICK_PH_MM = 1578, |
| PICK_QB_MM = 1579, |
| PRECEQU_PH_QBLA_MM = 1580, |
| PRECEQU_PH_QBL_MM = 1581, |
| PRECEQU_PH_QBRA_MM = 1582, |
| PRECEQU_PH_QBR_MM = 1583, |
| PRECEQ_W_PHL_MM = 1584, |
| PRECEQ_W_PHR_MM = 1585, |
| PRECEU_PH_QBLA_MM = 1586, |
| PRECEU_PH_QBL_MM = 1587, |
| PRECEU_PH_QBRA_MM = 1588, |
| PRECEU_PH_QBR_MM = 1589, |
| PRECRQU_S_QB_PH_MM = 1590, |
| PRECRQ_PH_W_MM = 1591, |
| PRECRQ_QB_PH_MM = 1592, |
| PRECRQ_RS_PH_W_MM = 1593, |
| RADDU_W_QB_MM = 1594, |
| RDDSP_MM = 1595, |
| REPLV_PH_MM = 1596, |
| REPLV_QB_MM = 1597, |
| REPL_PH_MM = 1598, |
| REPL_QB_MM = 1599, |
| SHILOV_MM = 1600, |
| SHILO_MM = 1601, |
| SHLLV_PH_MM = 1602, |
| SHLLV_QB_MM = 1603, |
| SHLLV_S_PH_MM = 1604, |
| SHLLV_S_W_MM = 1605, |
| SHLL_PH_MM = 1606, |
| SHLL_QB_MM = 1607, |
| SHLL_S_PH_MM = 1608, |
| SHLL_S_W_MM = 1609, |
| SHRAV_PH_MM = 1610, |
| SHRAV_R_PH_MM = 1611, |
| SHRAV_R_W_MM = 1612, |
| SHRA_PH_MM = 1613, |
| SHRA_R_PH_MM = 1614, |
| SHRA_R_W_MM = 1615, |
| SHRLV_QB_MM = 1616, |
| SHRL_QB_MM = 1617, |
| SUBQ_PH_MM = 1618, |
| SUBQ_S_PH_MM = 1619, |
| SUBQ_S_W_MM = 1620, |
| SUBU_QB_MM = 1621, |
| SUBU_S_QB_MM = 1622, |
| WRDSP_MM = 1623, |
| ABSQ_S_QB_MMR2 = 1624, |
| ADDQH_PH_MMR2 = 1625, |
| ADDQH_R_PH_MMR2 = 1626, |
| ADDQH_R_W_MMR2 = 1627, |
| ADDQH_W_MMR2 = 1628, |
| ADDUH_QB_MMR2 = 1629, |
| ADDUH_R_QB_MMR2 = 1630, |
| ADDU_PH_MMR2 = 1631, |
| ADDU_S_PH_MMR2 = 1632, |
| APPEND_MMR2 = 1633, |
| BALIGN_MMR2 = 1634, |
| CMPGDU_EQ_QB_MMR2 = 1635, |
| CMPGDU_LE_QB_MMR2 = 1636, |
| CMPGDU_LT_QB_MMR2 = 1637, |
| DPA_W_PH_MMR2 = 1638, |
| DPAQX_SA_W_PH_MMR2 = 1639, |
| DPAQX_S_W_PH_MMR2 = 1640, |
| DPAX_W_PH_MMR2 = 1641, |
| DPS_W_PH_MMR2 = 1642, |
| DPSQX_S_W_PH_MMR2 = 1643, |
| DPSQX_SA_W_PH_MMR2 = 1644, |
| DPSX_W_PH_MMR2 = 1645, |
| MUL_PH_MMR2 = 1646, |
| MUL_S_PH_MMR2 = 1647, |
| MULQ_RS_W_MMR2 = 1648, |
| MULQ_S_PH_MMR2 = 1649, |
| MULQ_S_W_MMR2 = 1650, |
| MULSA_W_PH_MMR2 = 1651, |
| PRECR_QB_PH_MMR2 = 1652, |
| PRECR_SRA_PH_W_MMR2 = 1653, |
| PRECR_SRA_R_PH_W_MMR2 = 1654, |
| PREPEND_MMR2 = 1655, |
| SHRA_QB_MMR2 = 1656, |
| SHRA_R_QB_MMR2 = 1657, |
| SHRAV_QB_MMR2 = 1658, |
| SHRAV_R_QB_MMR2 = 1659, |
| SHRL_PH_MMR2 = 1660, |
| SHRLV_PH_MMR2 = 1661, |
| SUBQH_PH_MMR2 = 1662, |
| SUBQH_R_PH_MMR2 = 1663, |
| SUBQH_W_MMR2 = 1664, |
| SUBQH_R_W_MMR2 = 1665, |
| SUBU_PH_MMR2 = 1666, |
| SUBU_S_PH_MMR2 = 1667, |
| SUBUH_QB_MMR2 = 1668, |
| SUBUH_R_QB_MMR2 = 1669, |
| BPOSGE32C_MMR3 = 1670, |
| CMP_F_D = 1671, |
| CMP_F_S = 1672, |
| CMP_SAF_D = 1673, |
| CMP_SAF_S = 1674, |
| CMP_SEQ_D = 1675, |
| CMP_SEQ_S = 1676, |
| CMP_SLE_D = 1677, |
| CMP_SLE_S = 1678, |
| CMP_SLT_D = 1679, |
| CMP_SLT_S = 1680, |
| CMP_SUEQ_D = 1681, |
| CMP_SUEQ_S = 1682, |
| CMP_SULE_D = 1683, |
| CMP_SULE_S = 1684, |
| CMP_SULT_D = 1685, |
| CMP_SULT_S = 1686, |
| CMP_SUN_D = 1687, |
| CMP_SUN_S = 1688, |
| SCHED_LIST_END = 1689 |
| }; |
| } // end namespace Sched |
| } // end namespace Mips |
| } // end namespace llvm |
| #endif // GET_INSTRINFO_SCHED_ENUM |
| |
| #ifdef GET_INSTRINFO_MC_DESC |
| #undef GET_INSTRINFO_MC_DESC |
| namespace llvm { |
| |
| static const MCPhysReg ImplicitList1[] = { Mips::SP, Mips::SP }; |
| static const MCPhysReg ImplicitList2[] = { Mips::AT }; |
| static const MCPhysReg ImplicitList3[] = { Mips::RA }; |
| static const MCPhysReg ImplicitList4[] = { Mips::DSPPos }; |
| static const MCPhysReg ImplicitList5[] = { Mips::V0, Mips::V1 }; |
| static const MCPhysReg ImplicitList6[] = { Mips::HI0, Mips::LO0 }; |
| static const MCPhysReg ImplicitList7[] = { Mips::T8 }; |
| static const MCPhysReg ImplicitList8[] = { Mips::DSPOutFlag20 }; |
| static const MCPhysReg ImplicitList9[] = { Mips::DSPCarry }; |
| static const MCPhysReg ImplicitList10[] = { Mips::DSPCarry, Mips::DSPOutFlag20 }; |
| static const MCPhysReg ImplicitList11[] = { Mips::DSPCCond }; |
| static const MCPhysReg ImplicitList12[] = { Mips::HI0, Mips::LO0, Mips::P0, Mips::P1, Mips::P2 }; |
| static const MCPhysReg ImplicitList13[] = { Mips::HI0_64, Mips::LO0_64 }; |
| static const MCPhysReg ImplicitList14[] = { Mips::DSPOutFlag16_19 }; |
| static const MCPhysReg ImplicitList15[] = { Mips::DSPPos, Mips::DSPEFI }; |
| static const MCPhysReg ImplicitList16[] = { Mips::DSPPos, Mips::DSPPos, Mips::DSPEFI }; |
| static const MCPhysReg ImplicitList17[] = { Mips::DSPOutFlag23 }; |
| static const MCPhysReg ImplicitList18[] = { Mips::FCC0 }; |
| static const MCPhysReg ImplicitList19[] = { Mips::DSPPos, Mips::DSPSCount }; |
| static const MCPhysReg ImplicitList20[] = { Mips::HI0, Mips::LO0, Mips::HI0, Mips::LO0 }; |
| static const MCPhysReg ImplicitList21[] = { Mips::AC0 }; |
| static const MCPhysReg ImplicitList22[] = { Mips::AC0_64 }; |
| static const MCPhysReg ImplicitList23[] = { Mips::HI0 }; |
| static const MCPhysReg ImplicitList24[] = { Mips::HI0_64 }; |
| static const MCPhysReg ImplicitList25[] = { Mips::LO0 }; |
| static const MCPhysReg ImplicitList26[] = { Mips::LO0_64 }; |
| static const MCPhysReg ImplicitList27[] = { Mips::MPL0, Mips::P0, Mips::P1, Mips::P2 }; |
| static const MCPhysReg ImplicitList28[] = { Mips::MPL1, Mips::P0, Mips::P1, Mips::P2 }; |
| static const MCPhysReg ImplicitList29[] = { Mips::MPL2, Mips::P0, Mips::P1, Mips::P2 }; |
| static const MCPhysReg ImplicitList30[] = { Mips::P0 }; |
| static const MCPhysReg ImplicitList31[] = { Mips::P1 }; |
| static const MCPhysReg ImplicitList32[] = { Mips::P2 }; |
| static const MCPhysReg ImplicitList33[] = { Mips::DSPOutFlag21 }; |
| static const MCPhysReg ImplicitList34[] = { Mips::DSPOutFlag22 }; |
| static const MCPhysReg ImplicitList35[] = { Mips::P0, Mips::P1, Mips::P2 }; |
| static const MCPhysReg ImplicitList36[] = { Mips::MPL1, Mips::MPL2, Mips::P0, Mips::P1, Mips::P2 }; |
| |
| static const MCOperandInfo OperandInfo2[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo3[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; |
| static const MCOperandInfo OperandInfo4[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; |
| static const MCOperandInfo OperandInfo5[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; |
| static const MCOperandInfo OperandInfo6[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; |
| static const MCOperandInfo OperandInfo7[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo8[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; |
| static const MCOperandInfo OperandInfo9[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, }; |
| static const MCOperandInfo OperandInfo10[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; |
| static const MCOperandInfo OperandInfo11[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; |
| static const MCOperandInfo OperandInfo12[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo13[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; |
| static const MCOperandInfo OperandInfo14[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; |
| static const MCOperandInfo OperandInfo15[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo16[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo17[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, }; |
| static const MCOperandInfo OperandInfo18[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, }; |
| static const MCOperandInfo OperandInfo19[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, }; |
| static const MCOperandInfo OperandInfo20[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, }; |
| static const MCOperandInfo OperandInfo21[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo22[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, }; |
| static const MCOperandInfo OperandInfo23[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, }; |
| static const MCOperandInfo OperandInfo24[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, }; |
| static const MCOperandInfo OperandInfo25[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, }; |
| static const MCOperandInfo OperandInfo26[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; |
| static const MCOperandInfo OperandInfo27[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo28[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo29[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, }; |
| static const MCOperandInfo OperandInfo30[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, }; |
| static const MCOperandInfo OperandInfo31[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, }; |
| static const MCOperandInfo OperandInfo32[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo33[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, }; |
| static const MCOperandInfo OperandInfo34[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, }; |
| static const MCOperandInfo OperandInfo35[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, }; |
| static const MCOperandInfo OperandInfo36[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, }; |
| static const MCOperandInfo OperandInfo37[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, }; |
| static const MCOperandInfo OperandInfo38[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, }; |
| static const MCOperandInfo OperandInfo39[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, }; |
| static const MCOperandInfo OperandInfo40[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, }; |
| static const MCOperandInfo OperandInfo41[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo42[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, }; |
| static const MCOperandInfo OperandInfo43[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, }; |
| static const MCOperandInfo OperandInfo44[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, }; |
| static const MCOperandInfo OperandInfo45[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo46[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo47[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo48[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo49[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo50[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo51[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo52[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo53[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo54[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo55[] = { { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; |
| static const MCOperandInfo OperandInfo56[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; |
| static const MCOperandInfo OperandInfo57[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; |
| static const MCOperandInfo OperandInfo58[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo59[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo60[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo61[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo62[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; |
| static const MCOperandInfo OperandInfo63[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; |
| static const MCOperandInfo OperandInfo64[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo65[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo66[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGRCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo67[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo68[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo69[] = { { Mips::FGRCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo70[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo71[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo72[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo73[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo74[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; |
| static const MCOperandInfo OperandInfo75[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; |
| static const MCOperandInfo OperandInfo76[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo77[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo78[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo79[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo80[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo81[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo82[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo83[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo84[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo85[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo86[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo87[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo88[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo89[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo90[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo91[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo92[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo93[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo94[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo95[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo96[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; |
| static const MCOperandInfo OperandInfo97[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo98[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo99[] = { { Mips::MSA128F16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; |
| static const MCOperandInfo OperandInfo100[] = { { Mips::ACC128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; |
| static const MCOperandInfo OperandInfo101[] = { { Mips::ACC64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; |
| static const MCOperandInfo OperandInfo102[] = { { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; |
| static const MCOperandInfo OperandInfo103[] = { { Mips::DSPCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; |
| static const MCOperandInfo OperandInfo104[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; |
| static const MCOperandInfo OperandInfo105[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; |
| static const MCOperandInfo OperandInfo106[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; |
| static const MCOperandInfo OperandInfo107[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; |
| static const MCOperandInfo OperandInfo108[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; |
| static const MCOperandInfo OperandInfo109[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; |
| static const MCOperandInfo OperandInfo110[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; |
| static const MCOperandInfo OperandInfo111[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; |
| static const MCOperandInfo OperandInfo112[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo113[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; |
| static const MCOperandInfo OperandInfo114[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo115[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo116[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo117[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo118[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo119[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo120[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::COP0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo121[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo122[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo123[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128F16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo124[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128F16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo125[] = { { Mips::MSA128F16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo126[] = { { Mips::MSA128F16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo127[] = { { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo128[] = { { Mips::COP0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo129[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo130[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo131[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo132[] = { { Mips::DSPCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo133[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo134[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo135[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo136[] = { { Mips::ACC128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo137[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo138[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo139[] = { { Mips::ACC64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, }; |
| static const MCOperandInfo OperandInfo140[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo141[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo142[] = { { Mips::ACC64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo143[] = { { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo144[] = { { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo145[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo146[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo147[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo148[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo149[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo150[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo151[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo152[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo153[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo154[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo155[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo156[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo157[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo158[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; |
| static const MCOperandInfo OperandInfo159[] = { { Mips::GPR32NONZERORegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo160[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo161[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo162[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo163[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo164[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo165[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo166[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo167[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo168[] = { { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo169[] = { { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo170[] = { { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo171[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo172[] = { { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo173[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo174[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo175[] = { { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo176[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo177[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo178[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo179[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo180[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo181[] = { { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, }; |
| static const MCOperandInfo OperandInfo182[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, }; |
| static const MCOperandInfo OperandInfo183[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo184[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo185[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsPlusSPRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo186[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo187[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; |
| static const MCOperandInfo OperandInfo188[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; |
| static const MCOperandInfo OperandInfo189[] = { { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; |
| static const MCOperandInfo OperandInfo190[] = { { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; |
| static const MCOperandInfo OperandInfo191[] = { { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; |
| static const MCOperandInfo OperandInfo192[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo193[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo194[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo195[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo196[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo197[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; |
| static const MCOperandInfo OperandInfo198[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; |
| static const MCOperandInfo OperandInfo199[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; |
| static const MCOperandInfo OperandInfo200[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; |
| static const MCOperandInfo OperandInfo201[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; |
| static const MCOperandInfo OperandInfo202[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo203[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo204[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo205[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo206[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo207[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo208[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CCRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo209[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo210[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSACtrlRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo211[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo212[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo213[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo214[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo215[] = { { Mips::FGRCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo216[] = { { Mips::FGRCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo217[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo218[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo219[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo220[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo221[] = { { Mips::CCRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo222[] = { { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo223[] = { { Mips::MSACtrlRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo224[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo225[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo226[] = { { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo227[] = { { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo228[] = { { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo229[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo230[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo231[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, }; |
| static const MCOperandInfo OperandInfo232[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::COP0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo233[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo234[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo235[] = { { Mips::COP0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo236[] = { { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo237[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo238[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo239[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo240[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo241[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo242[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo243[] = { { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, }; |
| static const MCOperandInfo OperandInfo244[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo245[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo246[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo247[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo248[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo249[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo250[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo251[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo252[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo253[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo254[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo255[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo256[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo257[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo258[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo259[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo260[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo261[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo262[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, }; |
| static const MCOperandInfo OperandInfo263[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo264[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo265[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo266[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo267[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo268[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo269[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo270[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo271[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo272[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo273[] = { { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; |
| static const MCOperandInfo OperandInfo274[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo275[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; |
| static const MCOperandInfo OperandInfo276[] = { { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; |
| static const MCOperandInfo OperandInfo277[] = { { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; |
| static const MCOperandInfo OperandInfo278[] = { { Mips::COP3RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; |
| static const MCOperandInfo OperandInfo279[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo280[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo281[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo282[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo283[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, }; |
| static const MCOperandInfo OperandInfo284[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo285[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo286[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; |
| static const MCOperandInfo OperandInfo287[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; |
| static const MCOperandInfo OperandInfo288[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; |
| static const MCOperandInfo OperandInfo289[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; |
| static const MCOperandInfo OperandInfo290[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MipsII::OPERAND_MEM_SIMM9, 0 }, { -1, 0, MipsII::OPERAND_MEM_SIMM9, 0 }, }; |
| static const MCOperandInfo OperandInfo291[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MipsII::OPERAND_MEM_SIMM9, 0 }, { -1, 0, MipsII::OPERAND_MEM_SIMM9, 0 }, }; |
| static const MCOperandInfo OperandInfo292[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; |
| static const MCOperandInfo OperandInfo293[] = { { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; |
| static const MCOperandInfo OperandInfo294[] = { { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 3, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; |
| static const MCOperandInfo OperandInfo295[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, }; |
| static const MCOperandInfo OperandInfo296[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 2, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; |
| static const MCOperandInfo OperandInfo297[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; |
| static const MCOperandInfo OperandInfo298[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 2, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; |
| static const MCOperandInfo OperandInfo299[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo300[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo301[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; |
| static const MCOperandInfo OperandInfo302[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo303[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo304[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo305[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo306[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo307[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo308[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo309[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo310[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo311[] = { { Mips::GPRMM16MovePPairFirstRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16MovePPairSecondRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16MovePRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16MovePRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo312[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo313[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, }; |
| static const MCOperandInfo OperandInfo314[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, }; |
| static const MCOperandInfo OperandInfo315[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, }; |
| static const MCOperandInfo OperandInfo316[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, }; |
| static const MCOperandInfo OperandInfo317[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, }; |
| static const MCOperandInfo OperandInfo318[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, }; |
| static const MCOperandInfo OperandInfo319[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, }; |
| static const MCOperandInfo OperandInfo320[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, }; |
| static const MCOperandInfo OperandInfo321[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, }; |
| static const MCOperandInfo OperandInfo322[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, }; |
| static const MCOperandInfo OperandInfo323[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, }; |
| static const MCOperandInfo OperandInfo324[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, }; |
| static const MCOperandInfo OperandInfo325[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, }; |
| static const MCOperandInfo OperandInfo326[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, }; |
| static const MCOperandInfo OperandInfo327[] = { { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo328[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo329[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo330[] = { { Mips::HI32DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo331[] = { { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, }; |
| static const MCOperandInfo OperandInfo332[] = { { Mips::LO32DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo333[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo334[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo335[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo336[] = { { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo337[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo338[] = { { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo339[] = { { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, }; |
| static const MCOperandInfo OperandInfo340[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo341[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::HWRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo342[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::HWRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo343[] = { { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo344[] = { { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo345[] = { { Mips::GPRMM16ZeroRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; |
| static const MCOperandInfo OperandInfo346[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; |
| static const MCOperandInfo OperandInfo347[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MipsII::OPERAND_MEM_SIMM9, 0 }, { -1, 0, MipsII::OPERAND_MEM_SIMM9, 0 }, }; |
| static const MCOperandInfo OperandInfo348[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; |
| static const MCOperandInfo OperandInfo349[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MipsII::OPERAND_MEM_SIMM9, 0 }, { -1, 0, MipsII::OPERAND_MEM_SIMM9, 0 }, }; |
| static const MCOperandInfo OperandInfo350[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGRCCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo351[] = { { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, }; |
| static const MCOperandInfo OperandInfo352[] = { { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo353[] = { { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo354[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo355[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo356[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo357[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo358[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo359[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo360[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo361[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo362[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo363[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo364[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; |
| static const MCOperandInfo OperandInfo365[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, }; |
| |
| extern const MCInstrDesc MipsInsts[] = { |
| { 2847, 2, 1, 4, 1065, 0, 0, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo45 }, // Inst #2847 = YIELD |
| { 2846, 3, 1, 2, 735, 0, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, OperandInfo186 }, // Inst #2846 = XorRxRxRy16 |
| { 2845, 3, 1, 4, 773, 0, 0, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, OperandInfo73 }, // Inst #2845 = XORi_MM |
| { 2844, 3, 1, 4, 815, 0, 0, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, OperandInfo70 }, // Inst #2844 = XORi64 |
| { 2843, 3, 1, 4, 508, 0, 0, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, OperandInfo73 }, // Inst #2843 = XORi |
| { 2842, 3, 1, 4, 548, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #2842 = XOR_V |
| { 2841, 3, 1, 4, 804, 0, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, OperandInfo72 }, // Inst #2841 = XOR_MMR6 |
| { 2840, 3, 1, 4, 772, 0, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, OperandInfo72 }, // Inst #2840 = XOR_MM |
| { 2839, 3, 1, 4, 805, 0, 0, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, OperandInfo73 }, // Inst #2839 = XORI_MMR6 |
| { 2838, 3, 1, 4, 549, 0, 0, 0, 0x6ULL, nullptr, OperandInfo176 }, // Inst #2838 = XORI_B |
| { 2837, 3, 1, 4, 815, 0, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, OperandInfo71 }, // Inst #2837 = XOR64 |
| { 2836, 3, 1, 2, 804, 0, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo181 }, // Inst #2836 = XOR16_MMR6 |
| { 2835, 3, 1, 2, 772, 0, 0, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo181 }, // Inst #2835 = XOR16_MM |
| { 2834, 3, 1, 4, 371, 0, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, OperandInfo72 }, // Inst #2834 = XOR |
| { 2833, 2, 1, 4, 803, 0, 0, 0, 0x6ULL, nullptr, OperandInfo45 }, // Inst #2833 = WSBH_MMR6 |
| { 2832, 2, 1, 4, 771, 0, 0, 0, 0x1ULL, nullptr, OperandInfo45 }, // Inst #2832 = WSBH_MM |
| { 2831, 2, 1, 4, 481, 0, 0, 0, 0x1ULL, nullptr, OperandInfo45 }, // Inst #2831 = WSBH |
| { 2830, 2, 1, 4, 1037, 0, 0, 0, 0x6ULL, nullptr, OperandInfo45 }, // Inst #2830 = WRPGPR_MMR6 |
| { 2829, 2, 0, 4, 1623, 0, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo114 }, // Inst #2829 = WRDSP_MM |
| { 2828, 2, 0, 4, 1457, 0, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo114 }, // Inst #2828 = WRDSP |
| { 2827, 1, 0, 4, 1052, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo2 }, // Inst #2827 = WAIT_MMR6 |
| { 2826, 1, 0, 4, 1035, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo2 }, // Inst #2826 = WAIT_MM |
| { 2825, 0, 0, 4, 404, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr }, // Inst #2825 = WAIT |
| { 2824, 4, 1, 4, 515, 0, 0, 0, 0x6ULL, nullptr, OperandInfo60 }, // Inst #2824 = VSHF_W |
| { 2823, 4, 1, 4, 515, 0, 0, 0, 0x6ULL, nullptr, OperandInfo61 }, // Inst #2823 = VSHF_H |
| { 2822, 4, 1, 4, 515, 0, 0, 0, 0x6ULL, nullptr, OperandInfo59 }, // Inst #2822 = VSHF_D |
| { 2821, 4, 1, 4, 515, 0, 0, 0, 0x6ULL, nullptr, OperandInfo196 }, // Inst #2821 = VSHF_B |
| { 2820, 3, 1, 4, 1208, 0, 5, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList36, OperandInfo71 }, // Inst #2820 = VMULU |
| { 2819, 3, 1, 4, 1208, 0, 4, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList27, OperandInfo71 }, // Inst #2819 = VMM0 |
| { 2818, 3, 1, 4, 1208, 0, 3, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList35, OperandInfo71 }, // Inst #2818 = V3MULU |
| { 2817, 2, 0, 4, 886, 0, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList6, OperandInfo45 }, // Inst #2817 = UDIV_MM |
| { 2816, 2, 0, 4, 866, 0, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList6, OperandInfo45 }, // Inst #2816 = UDIV |
| { 2815, 2, 0, 4, 403, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo114 }, // Inst #2815 = TTLTIU |
| { 2814, 2, 1, 4, 1308, 0, 0, 0, 0x4ULL, nullptr, OperandInfo207 }, // Inst #2814 = TRUNC_W_S_MMR6 |
| { 2813, 2, 1, 4, 1256, 0, 0, 0, 0x4ULL, nullptr, OperandInfo207 }, // Inst #2813 = TRUNC_W_S_MM |
| { 2812, 2, 1, 4, 637, 0, 0, 0, 0x4ULL, nullptr, OperandInfo207 }, // Inst #2812 = TRUNC_W_S |
| { 2811, 2, 1, 4, 1256, 0, 0, 0, 0x4ULL, nullptr, OperandInfo205 }, // Inst #2811 = TRUNC_W_MM |
| { 2810, 2, 1, 4, 1308, 0, 0, 0, 0x4ULL, nullptr, OperandInfo206 }, // Inst #2810 = TRUNC_W_D_MMR6 |
| { 2809, 2, 1, 4, 637, 0, 0, 0, 0x4ULL, nullptr, OperandInfo206 }, // Inst #2809 = TRUNC_W_D64 |
| { 2808, 2, 1, 4, 637, 0, 0, 0, 0x4ULL, nullptr, OperandInfo205 }, // Inst #2808 = TRUNC_W_D32 |
| { 2807, 2, 1, 4, 1308, 0, 0, 0, 0x4ULL, nullptr, OperandInfo204 }, // Inst #2807 = TRUNC_L_S_MMR6 |
| { 2806, 2, 1, 4, 637, 0, 0, 0, 0x4ULL, nullptr, OperandInfo204 }, // Inst #2806 = TRUNC_L_S |
| { 2805, 2, 1, 4, 1308, 0, 0, 0, 0x4ULL, nullptr, OperandInfo203 }, // Inst #2805 = TRUNC_L_D_MMR6 |
| { 2804, 2, 1, 4, 637, 0, 0, 0, 0x4ULL, nullptr, OperandInfo203 }, // Inst #2804 = TRUNC_L_D64 |
| { 2803, 3, 0, 4, 980, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, OperandInfo73 }, // Inst #2803 = TNE_MM |
| { 2802, 2, 0, 4, 979, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo114 }, // Inst #2802 = TNEI_MM |
| { 2801, 2, 0, 4, 401, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo114 }, // Inst #2801 = TNEI |
| { 2800, 3, 0, 4, 400, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, OperandInfo73 }, // Inst #2800 = TNE |
| { 2799, 3, 0, 4, 978, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, OperandInfo73 }, // Inst #2799 = TLT_MM |
| { 2798, 3, 0, 4, 977, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, OperandInfo73 }, // Inst #2798 = TLTU_MM |
| { 2797, 3, 0, 4, 399, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, OperandInfo73 }, // Inst #2797 = TLTU |
| { 2796, 2, 0, 4, 976, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo114 }, // Inst #2796 = TLTI_MM |
| { 2795, 2, 0, 4, 975, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo114 }, // Inst #2795 = TLTIU_MM |
| { 2794, 2, 0, 4, 398, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo114 }, // Inst #2794 = TLTI |
| { 2793, 3, 0, 4, 397, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, OperandInfo73 }, // Inst #2793 = TLT |
| { 2792, 0, 0, 4, 1030, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr }, // Inst #2792 = TLBWR_MM |
| { 2791, 0, 0, 4, 415, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr }, // Inst #2791 = TLBWR |
| { 2790, 0, 0, 4, 1029, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr }, // Inst #2790 = TLBWI_MM |
| { 2789, 0, 0, 4, 414, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr }, // Inst #2789 = TLBWI |
| { 2788, 0, 0, 4, 1028, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr }, // Inst #2788 = TLBR_MM |
| { 2787, 0, 0, 4, 413, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr }, // Inst #2787 = TLBR |
| { 2786, 0, 0, 4, 1027, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr }, // Inst #2786 = TLBP_MM |
| { 2785, 0, 0, 4, 412, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr }, // Inst #2785 = TLBP |
| { 2784, 0, 0, 4, 1038, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr }, // Inst #2784 = TLBINV_MMR6 |
| { 2783, 0, 0, 4, 1039, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr }, // Inst #2783 = TLBINVF_MMR6 |
| { 2782, 0, 0, 4, 411, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr }, // Inst #2782 = TLBINVF |
| { 2781, 0, 0, 4, 410, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr }, // Inst #2781 = TLBINV |
| { 2780, 0, 0, 4, 1075, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr }, // Inst #2780 = TLBGWR_MM |
| { 2779, 0, 0, 4, 430, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr }, // Inst #2779 = TLBGWR |
| { 2778, 0, 0, 4, 1074, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr }, // Inst #2778 = TLBGWI_MM |
| { 2777, 0, 0, 4, 429, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr }, // Inst #2777 = TLBGWI |
| { 2776, 0, 0, 4, 1073, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr }, // Inst #2776 = TLBGR_MM |
| { 2775, 0, 0, 4, 428, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr }, // Inst #2775 = TLBGR |
| { 2774, 0, 0, 4, 1072, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr }, // Inst #2774 = TLBGP_MM |
| { 2773, 0, 0, 4, 427, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr }, // Inst #2773 = TLBGP |
| { 2772, 0, 0, 4, 1071, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr }, // Inst #2772 = TLBGINV_MM |
| { 2771, 0, 0, 4, 1070, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr }, // Inst #2771 = TLBGINVF_MM |
| { 2770, 0, 0, 4, 426, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr }, // Inst #2770 = TLBGINVF |
| { 2769, 0, 0, 4, 425, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr }, // Inst #2769 = TLBGINV |
| { 2768, 3, 0, 4, 974, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, OperandInfo73 }, // Inst #2768 = TGE_MM |
| { 2767, 3, 0, 4, 973, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, OperandInfo73 }, // Inst #2767 = TGEU_MM |
| { 2766, 3, 0, 4, 396, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, OperandInfo73 }, // Inst #2766 = TGEU |
| { 2765, 2, 0, 4, 972, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo114 }, // Inst #2765 = TGEI_MM |
| { 2764, 2, 0, 4, 971, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo114 }, // Inst #2764 = TGEIU_MM |
| { 2763, 2, 0, 4, 395, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo114 }, // Inst #2763 = TGEIU |
| { 2762, 2, 0, 4, 394, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo114 }, // Inst #2762 = TGEI |
| { 2761, 3, 0, 4, 393, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, OperandInfo73 }, // Inst #2761 = TGE |
| { 2760, 3, 0, 4, 970, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, OperandInfo73 }, // Inst #2760 = TEQ_MM |
| { 2759, 2, 0, 4, 969, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo114 }, // Inst #2759 = TEQI_MM |
| { 2758, 2, 0, 4, 392, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo114 }, // Inst #2758 = TEQI |
| { 2757, 3, 0, 4, 391, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, OperandInfo73 }, // Inst #2757 = TEQ |
| { 2756, 3, 0, 4, 1117, 0, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo185 }, // Inst #2756 = SwRxSpImmX16 |
| { 2755, 3, 0, 4, 1117, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo300 }, // Inst #2755 = SwRxRyOffMemX16 |
| { 2754, 3, 1, 2, 735, 0, 0, 0|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, OperandInfo131 }, // Inst #2754 = SubuRxRyRz16 |
| { 2753, 3, 1, 2, 735, 0, 0, 0, 0x0ULL, nullptr, OperandInfo186 }, // Inst #2753 = SrlvRxRy16 |
| { 2752, 3, 1, 4, 735, 0, 0, 0, 0x0ULL, nullptr, OperandInfo167 }, // Inst #2752 = SrlX16 |
| { 2751, 3, 1, 2, 735, 0, 0, 0, 0x0ULL, nullptr, OperandInfo186 }, // Inst #2751 = SravRxRy16 |
| { 2750, 3, 1, 4, 735, 0, 0, 0, 0x0ULL, nullptr, OperandInfo167 }, // Inst #2750 = SraX16 |
| { 2749, 2, 0, 2, 735, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList7, OperandInfo130 }, // Inst #2749 = SltuRxRy16 |
| { 2748, 2, 0, 4, 735, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList7, OperandInfo183 }, // Inst #2748 = SltiuRxImmX16 |
| { 2747, 2, 0, 2, 735, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList7, OperandInfo183 }, // Inst #2747 = SltiuRxImm16 |
| { 2746, 2, 0, 4, 735, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList7, OperandInfo183 }, // Inst #2746 = SltiRxImmX16 |
| { 2745, 2, 0, 2, 735, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList7, OperandInfo183 }, // Inst #2745 = SltiRxImm16 |
| { 2744, 2, 0, 2, 735, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList7, OperandInfo130 }, // Inst #2744 = SltRxRy16 |
| { 2743, 3, 1, 2, 735, 0, 0, 0, 0x0ULL, nullptr, OperandInfo186 }, // Inst #2743 = SllvRxRy16 |
| { 2742, 3, 1, 4, 735, 0, 0, 0, 0x0ULL, nullptr, OperandInfo167 }, // Inst #2742 = SllX16 |
| { 2741, 3, 0, 4, 1116, 0, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo300 }, // Inst #2741 = ShRxRyOffMemX16 |
| { 2740, 2, 1, 2, 735, 0, 0, 0, 0x0ULL, nullptr, OperandInfo365 }, // Inst #2740 = SehRx16 |
| { 2739, 2, 1, 2, 735, 0, 0, 0, 0x0ULL, nullptr, OperandInfo365 }, // Inst #2739 = SebRx16 |
| { 2738, 3, 0, 4, 1115, 0, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo300 }, // Inst #2738 = SbRxRyOffMemX16 |
| { 2737, 0, 0, 2, 1114, 1, 1, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, nullptr }, // Inst #2737 = SaveX16 |
| { 2736, 0, 0, 2, 1114, 1, 1, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, nullptr }, // Inst #2736 = Save16 |
| { 2735, 1, 0, 4, 968, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, OperandInfo2 }, // Inst #2735 = SYSCALL_MM |
| { 2734, 1, 0, 4, 390, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, OperandInfo2 }, // Inst #2734 = SYSCALL |
| { 2733, 1, 0, 4, 1159, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo2 }, // Inst #2733 = SYNC_MMR6 |
| { 2732, 1, 0, 4, 1141, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo2 }, // Inst #2732 = SYNC_MM |
| { 2731, 2, 0, 4, 1160, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo364 }, // Inst #2731 = SYNCI_MMR6 |
| { 2730, 2, 0, 4, 1142, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo364 }, // Inst #2730 = SYNCI_MM |
| { 2729, 2, 0, 4, 473, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo364 }, // Inst #2729 = SYNCI |
| { 2728, 1, 0, 4, 472, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo2 }, // Inst #2728 = SYNC |
| { 2727, 3, 0, 4, 1156, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo96 }, // Inst #2727 = SW_MMR6 |
| { 2726, 3, 0, 4, 1133, 0, 0, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, OperandInfo96 }, // Inst #2726 = SW_MM |
| { 2725, 3, 0, 4, 1293, 0, 0, 0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, OperandInfo299 }, // Inst #2725 = SWXC1_MM |
| { 2724, 3, 0, 4, 702, 0, 0, 0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, OperandInfo299 }, // Inst #2724 = SWXC1 |
| { 2723, 3, 0, 2, 1156, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo298 }, // Inst #2723 = SWSP_MMR6 |
| { 2722, 3, 0, 2, 1133, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo298 }, // Inst #2722 = SWSP_MM |
| { 2721, 3, 0, 4, 1138, 0, 0, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, OperandInfo96 }, // Inst #2721 = SWR_MM |
| { 2720, 3, 0, 4, 1104, 0, 0, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, OperandInfo96 }, // Inst #2720 = SWRE_MM |
| { 2719, 3, 0, 4, 467, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo96 }, // Inst #2719 = SWRE |
| { 2718, 3, 0, 4, 1181, 0, 0, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, OperandInfo113 }, // Inst #2718 = SWR64 |
| { 2717, 3, 0, 4, 465, 0, 0, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, OperandInfo96 }, // Inst #2717 = SWR |
| { 2716, 4, 0, 4, 1137, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo297 }, // Inst #2716 = SWP_MM |
| { 2715, 3, 0, 4, 1135, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo110 }, // Inst #2715 = SWM32_MM |
| { 2714, 3, 0, 2, 1158, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo296 }, // Inst #2714 = SWM16_MMR6 |
| { 2713, 3, 0, 2, 1135, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo296 }, // Inst #2713 = SWM16_MM |
| { 2712, 3, 0, 4, 1134, 0, 0, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, OperandInfo96 }, // Inst #2712 = SWL_MM |
| { 2711, 3, 0, 4, 1103, 0, 0, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, OperandInfo96 }, // Inst #2711 = SWLE_MM |
| { 2710, 3, 0, 4, 466, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo96 }, // Inst #2710 = SWLE |
| { 2709, 3, 0, 4, 1180, 0, 0, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, OperandInfo113 }, // Inst #2709 = SWL64 |
| { 2708, 3, 0, 4, 464, 0, 0, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, OperandInfo96 }, // Inst #2708 = SWL |
| { 2707, 3, 0, 4, 1102, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo96 }, // Inst #2707 = SWE_MM |
| { 2706, 3, 0, 4, 462, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo96 }, // Inst #2706 = SWE |
| { 2705, 3, 0, 4, 1507, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo293 }, // Inst #2705 = SWDSP_MM |
| { 2704, 3, 0, 4, 1342, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo293 }, // Inst #2704 = SWDSP |
| { 2703, 3, 0, 4, 456, 0, 0, 0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, OperandInfo278 }, // Inst #2703 = SWC3 |
| { 2702, 3, 0, 4, 1084, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo276 }, // Inst #2702 = SWC2_R6 |
| { 2701, 3, 0, 4, 1157, 0, 0, 0|(1ULL<<MCID::MayStore), 0x6ULL, nullptr, OperandInfo277 }, // Inst #2701 = SWC2_MMR6 |
| { 2700, 3, 0, 4, 455, 0, 0, 0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, OperandInfo276 }, // Inst #2700 = SWC2 |
| { 2699, 3, 0, 4, 1291, 0, 0, 0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, OperandInfo292 }, // Inst #2699 = SWC1_MM |
| { 2698, 3, 0, 4, 701, 0, 0, 0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, OperandInfo292 }, // Inst #2698 = SWC1 |
| { 2697, 3, 0, 4, 1179, 0, 0, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, OperandInfo113 }, // Inst #2697 = SW64 |
| { 2696, 3, 0, 2, 1156, 0, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo345 }, // Inst #2696 = SW16_MMR6 |
| { 2695, 3, 0, 2, 1133, 0, 0, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, OperandInfo345 }, // Inst #2695 = SW16_MM |
| { 2694, 3, 0, 4, 454, 0, 0, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, OperandInfo96 }, // Inst #2694 = SW |
| { 2693, 3, 0, 4, 1292, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, nullptr, OperandInfo285 }, // Inst #2693 = SUXC1_MM |
| { 2692, 3, 0, 4, 703, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, nullptr, OperandInfo285 }, // Inst #2692 = SUXC164 |
| { 2691, 3, 0, 4, 703, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, nullptr, OperandInfo284 }, // Inst #2691 = SUXC1 |
| { 2690, 3, 1, 4, 769, 0, 0, 0|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, OperandInfo72 }, // Inst #2690 = SUBu_MM |
| { 2689, 3, 1, 4, 370, 0, 0, 0|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, OperandInfo72 }, // Inst #2689 = SUBu |
| { 2688, 3, 1, 4, 802, 0, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, OperandInfo72 }, // Inst #2688 = SUB_MMR6 |
| { 2687, 3, 1, 4, 770, 0, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, OperandInfo72 }, // Inst #2687 = SUB_MM |
| { 2686, 3, 1, 4, 612, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #2686 = SUBV_W |
| { 2685, 3, 1, 4, 612, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #2685 = SUBV_H |
| { 2684, 3, 1, 4, 612, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #2684 = SUBV_D |
| { 2683, 3, 1, 4, 612, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #2683 = SUBV_B |
| { 2682, 3, 1, 4, 611, 0, 0, 0, 0x6ULL, nullptr, OperandInfo179 }, // Inst #2682 = SUBVI_W |
| { 2681, 3, 1, 4, 611, 0, 0, 0, 0x6ULL, nullptr, OperandInfo178 }, // Inst #2681 = SUBVI_H |
| { 2680, 3, 1, 4, 611, 0, 0, 0, 0x6ULL, nullptr, OperandInfo177 }, // Inst #2680 = SUBVI_D |
| { 2679, 3, 1, 4, 611, 0, 0, 0, 0x6ULL, nullptr, OperandInfo176 }, // Inst #2679 = SUBVI_B |
| { 2678, 3, 1, 4, 1622, 0, 1, 0, 0x6ULL, ImplicitList8, OperandInfo172 }, // Inst #2678 = SUBU_S_QB_MM |
| { 2677, 3, 1, 4, 1456, 0, 1, 0, 0x6ULL, ImplicitList8, OperandInfo172 }, // Inst #2677 = SUBU_S_QB |
| { 2676, 3, 1, 4, 1667, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList8, OperandInfo172 }, // Inst #2676 = SUBU_S_PH_MMR2 |
| { 2675, 3, 1, 4, 1503, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList8, OperandInfo172 }, // Inst #2675 = SUBU_S_PH |
| { 2674, 3, 1, 4, 1621, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList8, OperandInfo172 }, // Inst #2674 = SUBU_QB_MM |
| { 2673, 3, 1, 4, 1455, 0, 1, 0, 0x6ULL, ImplicitList8, OperandInfo172 }, // Inst #2673 = SUBU_QB |
| { 2672, 3, 1, 4, 1666, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList8, OperandInfo172 }, // Inst #2672 = SUBU_PH_MMR2 |
| { 2671, 3, 1, 4, 1502, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList8, OperandInfo172 }, // Inst #2671 = SUBU_PH |
| { 2670, 3, 1, 4, 801, 0, 0, 0|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, OperandInfo72 }, // Inst #2670 = SUBU_MMR6 |
| { 2669, 3, 1, 4, 1669, 0, 0, 0, 0x6ULL, nullptr, OperandInfo172 }, // Inst #2669 = SUBUH_R_QB_MMR2 |
| { 2668, 3, 1, 4, 1505, 0, 0, 0, 0x6ULL, nullptr, OperandInfo172 }, // Inst #2668 = SUBUH_R_QB |
| { 2667, 3, 1, 4, 1668, 0, 0, 0, 0x6ULL, nullptr, OperandInfo172 }, // Inst #2667 = SUBUH_QB_MMR2 |
| { 2666, 3, 1, 4, 1504, 0, 0, 0, 0x6ULL, nullptr, OperandInfo172 }, // Inst #2666 = SUBUH_QB |
| { 2665, 3, 1, 2, 801, 0, 0, 0, 0x0ULL, nullptr, OperandInfo175 }, // Inst #2665 = SUBU16_MMR6 |
| { 2664, 3, 1, 2, 769, 0, 0, 0, 0x0ULL, nullptr, OperandInfo175 }, // Inst #2664 = SUBU16_MM |
| { 2663, 3, 1, 4, 608, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #2663 = SUBS_U_W |
| { 2662, 3, 1, 4, 608, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #2662 = SUBS_U_H |
| { 2661, 3, 1, 4, 608, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #2661 = SUBS_U_D |
| { 2660, 3, 1, 4, 608, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #2660 = SUBS_U_B |
| { 2659, 3, 1, 4, 608, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #2659 = SUBS_S_W |
| { 2658, 3, 1, 4, 608, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #2658 = SUBS_S_H |
| { 2657, 3, 1, 4, 608, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #2657 = SUBS_S_D |
| { 2656, 3, 1, 4, 608, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #2656 = SUBS_S_B |
| { 2655, 3, 1, 4, 610, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #2655 = SUBSUU_S_W |
| { 2654, 3, 1, 4, 610, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #2654 = SUBSUU_S_H |
| { 2653, 3, 1, 4, 610, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #2653 = SUBSUU_S_D |
| { 2652, 3, 1, 4, 610, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #2652 = SUBSUU_S_B |
| { 2651, 3, 1, 4, 609, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #2651 = SUBSUS_U_W |
| { 2650, 3, 1, 4, 609, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #2650 = SUBSUS_U_H |
| { 2649, 3, 1, 4, 609, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #2649 = SUBSUS_U_D |
| { 2648, 3, 1, 4, 609, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #2648 = SUBSUS_U_B |
| { 2647, 3, 1, 4, 1620, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList8, OperandInfo72 }, // Inst #2647 = SUBQ_S_W_MM |
| { 2646, 3, 1, 4, 1454, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList8, OperandInfo72 }, // Inst #2646 = SUBQ_S_W |
| { 2645, 3, 1, 4, 1619, 0, 1, 0, 0x6ULL, ImplicitList8, OperandInfo172 }, // Inst #2645 = SUBQ_S_PH_MM |
| { 2644, 3, 1, 4, 1453, 0, 1, 0, 0x6ULL, ImplicitList8, OperandInfo172 }, // Inst #2644 = SUBQ_S_PH |
| { 2643, 3, 1, 4, 1618, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList8, OperandInfo172 }, // Inst #2643 = SUBQ_PH_MM |
| { 2642, 3, 1, 4, 1452, 0, 1, 0, 0x6ULL, ImplicitList8, OperandInfo172 }, // Inst #2642 = SUBQ_PH |
| { 2641, 3, 1, 4, 1664, 0, 0, 0, 0x6ULL, nullptr, OperandInfo72 }, // Inst #2641 = SUBQH_W_MMR2 |
| { 2640, 3, 1, 4, 1500, 0, 0, 0, 0x6ULL, nullptr, OperandInfo72 }, // Inst #2640 = SUBQH_W |
| { 2639, 3, 1, 4, 1665, 0, 0, 0, 0x6ULL, nullptr, OperandInfo72 }, // Inst #2639 = SUBQH_R_W_MMR2 |
| { 2638, 3, 1, 4, 1501, 0, 0, 0, 0x6ULL, nullptr, OperandInfo72 }, // Inst #2638 = SUBQH_R_W |
| { 2637, 3, 1, 4, 1663, 0, 0, 0, 0x6ULL, nullptr, OperandInfo172 }, // Inst #2637 = SUBQH_R_PH_MMR2 |
| { 2636, 3, 1, 4, 1499, 0, 0, 0, 0x6ULL, nullptr, OperandInfo172 }, // Inst #2636 = SUBQH_R_PH |
| { 2635, 3, 1, 4, 1662, 0, 0, 0, 0x6ULL, nullptr, OperandInfo172 }, // Inst #2635 = SUBQH_PH_MMR2 |
| { 2634, 3, 1, 4, 1498, 0, 0, 0, 0x6ULL, nullptr, OperandInfo172 }, // Inst #2634 = SUBQH_PH |
| { 2633, 3, 1, 4, 369, 0, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, OperandInfo72 }, // Inst #2633 = SUB |
| { 2632, 3, 0, 4, 704, 0, 0, 0|(1ULL<<MCID::MayStore), 0x6ULL, nullptr, OperandInfo289 }, // Inst #2632 = ST_W |
| { 2631, 3, 0, 4, 704, 0, 0, 0|(1ULL<<MCID::MayStore), 0x6ULL, nullptr, OperandInfo288 }, // Inst #2631 = ST_H |
| { 2630, 3, 0, 4, 704, 0, 0, 0|(1ULL<<MCID::MayStore), 0x6ULL, nullptr, OperandInfo287 }, // Inst #2630 = ST_D |
| { 2629, 3, 0, 4, 704, 0, 0, 0|(1ULL<<MCID::MayStore), 0x6ULL, nullptr, OperandInfo286 }, // Inst #2629 = ST_B |
| { 2628, 0, 0, 4, 800, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr }, // Inst #2628 = SSNOP_MMR6 |
| { 2627, 0, 0, 4, 768, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr }, // Inst #2627 = SSNOP_MM |
| { 2626, 0, 0, 4, 372, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr }, // Inst #2626 = SSNOP |
| { 2625, 3, 1, 4, 622, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #2625 = SRL_W |
| { 2624, 3, 1, 4, 766, 0, 0, 0, 0x1ULL, nullptr, OperandInfo73 }, // Inst #2624 = SRL_MM |
| { 2623, 3, 1, 4, 622, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #2623 = SRL_H |
| { 2622, 3, 1, 4, 622, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #2622 = SRL_D |
| { 2621, 3, 1, 4, 622, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #2621 = SRL_B |
| { 2620, 3, 1, 4, 767, 0, 0, 0, 0x1ULL, nullptr, OperandInfo72 }, // Inst #2620 = SRLV_MM |
| { 2619, 3, 1, 4, 512, 0, 0, 0, 0x1ULL, nullptr, OperandInfo72 }, // Inst #2619 = SRLV |
| { 2618, 3, 1, 4, 624, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #2618 = SRLR_W |
| { 2617, 3, 1, 4, 624, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #2617 = SRLR_H |
| { 2616, 3, 1, 4, 624, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #2616 = SRLR_D |
| { 2615, 3, 1, 4, 624, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #2615 = SRLR_B |
| { 2614, 3, 1, 4, 624, 0, 0, 0, 0x6ULL, nullptr, OperandInfo179 }, // Inst #2614 = SRLRI_W |
| { 2613, 3, 1, 4, 624, 0, 0, 0, 0x6ULL, nullptr, OperandInfo178 }, // Inst #2613 = SRLRI_H |
| { 2612, 3, 1, 4, 624, 0, 0, 0, 0x6ULL, nullptr, OperandInfo177 }, // Inst #2612 = SRLRI_D |
| { 2611, 3, 1, 4, 624, 0, 0, 0, 0x6ULL, nullptr, OperandInfo176 }, // Inst #2611 = SRLRI_B |
| { 2610, 3, 1, 4, 622, 0, 0, 0, 0x6ULL, nullptr, OperandInfo179 }, // Inst #2610 = SRLI_W |
| { 2609, 3, 1, 4, 622, 0, 0, 0, 0x6ULL, nullptr, OperandInfo178 }, // Inst #2609 = SRLI_H |
| { 2608, 3, 1, 4, 622, 0, 0, 0, 0x6ULL, nullptr, OperandInfo177 }, // Inst #2608 = SRLI_D |
| { 2607, 3, 1, 4, 622, 0, 0, 0, 0x6ULL, nullptr, OperandInfo176 }, // Inst #2607 = SRLI_B |
| { 2606, 3, 1, 2, 799, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo170 }, // Inst #2606 = SRL16_MMR6 |
| { 2605, 3, 1, 2, 766, 0, 0, 0, 0x0ULL, nullptr, OperandInfo170 }, // Inst #2605 = SRL16_MM |
| { 2604, 3, 1, 4, 507, 0, 0, 0, 0x1ULL, nullptr, OperandInfo73 }, // Inst #2604 = SRL |
| { 2603, 3, 1, 4, 621, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #2603 = SRA_W |
| { 2602, 3, 1, 4, 765, 0, 0, 0, 0x1ULL, nullptr, OperandInfo73 }, // Inst #2602 = SRA_MM |
| { 2601, 3, 1, 4, 621, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #2601 = SRA_H |
| { 2600, 3, 1, 4, 621, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #2600 = SRA_D |
| { 2599, 3, 1, 4, 621, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #2599 = SRA_B |
| { 2598, 3, 1, 4, 764, 0, 0, 0, 0x1ULL, nullptr, OperandInfo72 }, // Inst #2598 = SRAV_MM |
| { 2597, 3, 1, 4, 511, 0, 0, 0, 0x1ULL, nullptr, OperandInfo72 }, // Inst #2597 = SRAV |
| { 2596, 3, 1, 4, 623, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #2596 = SRAR_W |
| { 2595, 3, 1, 4, 623, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #2595 = SRAR_H |
| { 2594, 3, 1, 4, 623, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #2594 = SRAR_D |
| { 2593, 3, 1, 4, 623, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #2593 = SRAR_B |
| { 2592, 3, 1, 4, 623, 0, 0, 0, 0x6ULL, nullptr, OperandInfo179 }, // Inst #2592 = SRARI_W |
| { 2591, 3, 1, 4, 623, 0, 0, 0, 0x6ULL, nullptr, OperandInfo178 }, // Inst #2591 = SRARI_H |
| { 2590, 3, 1, 4, 623, 0, 0, 0, 0x6ULL, nullptr, OperandInfo177 }, // Inst #2590 = SRARI_D |
| { 2589, 3, 1, 4, 623, 0, 0, 0, 0x6ULL, nullptr, OperandInfo176 }, // Inst #2589 = SRARI_B |
| { 2588, 3, 1, 4, 621, 0, 0, 0, 0x6ULL, nullptr, OperandInfo179 }, // Inst #2588 = SRAI_W |
| { 2587, 3, 1, 4, 621, 0, 0, 0, 0x6ULL, nullptr, OperandInfo178 }, // Inst #2587 = SRAI_H |
| { 2586, 3, 1, 4, 621, 0, 0, 0, 0x6ULL, nullptr, OperandInfo177 }, // Inst #2586 = SRAI_D |
| { 2585, 3, 1, 4, 621, 0, 0, 0, 0x6ULL, nullptr, OperandInfo176 }, // Inst #2585 = SRAI_B |
| { 2584, 3, 1, 4, 506, 0, 0, 0, 0x1ULL, nullptr, OperandInfo73 }, // Inst #2584 = SRA |
| { 2583, 3, 1, 4, 545, 0, 0, 0, 0x6ULL, nullptr, OperandInfo363 }, // Inst #2583 = SPLAT_W |
| { 2582, 3, 1, 4, 545, 0, 0, 0, 0x6ULL, nullptr, OperandInfo362 }, // Inst #2582 = SPLAT_H |
| { 2581, 3, 1, 4, 545, 0, 0, 0, 0x6ULL, nullptr, OperandInfo361 }, // Inst #2581 = SPLAT_D |
| { 2580, 3, 1, 4, 545, 0, 0, 0, 0x6ULL, nullptr, OperandInfo360 }, // Inst #2580 = SPLAT_B |
| { 2579, 3, 1, 4, 545, 0, 0, 0, 0x6ULL, nullptr, OperandInfo179 }, // Inst #2579 = SPLATI_W |
| { 2578, 3, 1, 4, 545, 0, 0, 0, 0x6ULL, nullptr, OperandInfo178 }, // Inst #2578 = SPLATI_H |
| { 2577, 3, 1, 4, 545, 0, 0, 0, 0x6ULL, nullptr, OperandInfo177 }, // Inst #2577 = SPLATI_D |
| { 2576, 3, 1, 4, 545, 0, 0, 0, 0x6ULL, nullptr, OperandInfo176 }, // Inst #2576 = SPLATI_B |
| { 2575, 3, 1, 4, 1207, 0, 0, 0, 0x2ULL, nullptr, OperandInfo70 }, // Inst #2575 = SNEi |
| { 2574, 3, 1, 4, 1206, 0, 0, 0, 0x1ULL, nullptr, OperandInfo71 }, // Inst #2574 = SNE |
| { 2573, 3, 1, 4, 762, 0, 0, 0, 0x1ULL, nullptr, OperandInfo72 }, // Inst #2573 = SLTu_MM |
| { 2572, 3, 1, 4, 813, 0, 0, 0, 0x1ULL, nullptr, OperandInfo358 }, // Inst #2572 = SLTu64 |
| { 2571, 3, 1, 4, 504, 0, 0, 0, 0x1ULL, nullptr, OperandInfo72 }, // Inst #2571 = SLTu |
| { 2570, 3, 1, 4, 763, 0, 0, 0, 0x2ULL, nullptr, OperandInfo73 }, // Inst #2570 = SLTiu_MM |
| { 2569, 3, 1, 4, 814, 0, 0, 0, 0x2ULL, nullptr, OperandInfo359 }, // Inst #2569 = SLTiu64 |
| { 2568, 3, 1, 4, 368, 0, 0, 0, 0x2ULL, nullptr, OperandInfo73 }, // Inst #2568 = SLTiu |
| { 2567, 3, 1, 4, 763, 0, 0, 0, 0x2ULL, nullptr, OperandInfo73 }, // Inst #2567 = SLTi_MM |
| { 2566, 3, 1, 4, 814, 0, 0, 0, 0x2ULL, nullptr, OperandInfo359 }, // Inst #2566 = SLTi64 |
| { 2565, 3, 1, 4, 368, 0, 0, 0, 0x2ULL, nullptr, OperandInfo73 }, // Inst #2565 = SLTi |
| { 2564, 3, 1, 4, 762, 0, 0, 0, 0x1ULL, nullptr, OperandInfo72 }, // Inst #2564 = SLT_MM |
| { 2563, 3, 1, 4, 813, 0, 0, 0, 0x1ULL, nullptr, OperandInfo358 }, // Inst #2563 = SLT64 |
| { 2562, 3, 1, 4, 504, 0, 0, 0, 0x1ULL, nullptr, OperandInfo72 }, // Inst #2562 = SLT |
| { 2561, 3, 1, 4, 625, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #2561 = SLL_W |
| { 2560, 3, 1, 4, 798, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, OperandInfo73 }, // Inst #2560 = SLL_MMR6 |
| { 2559, 3, 1, 4, 760, 0, 0, 0, 0x1ULL, nullptr, OperandInfo73 }, // Inst #2559 = SLL_MM |
| { 2558, 3, 1, 4, 625, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #2558 = SLL_H |
| { 2557, 3, 1, 4, 625, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #2557 = SLL_D |
| { 2556, 3, 1, 4, 625, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #2556 = SLL_B |
| { 2555, 3, 1, 4, 761, 0, 0, 0, 0x1ULL, nullptr, OperandInfo72 }, // Inst #2555 = SLLV_MM |
| { 2554, 3, 1, 4, 510, 0, 0, 0, 0x1ULL, nullptr, OperandInfo72 }, // Inst #2554 = SLLV |
| { 2553, 3, 1, 4, 625, 0, 0, 0, 0x6ULL, nullptr, OperandInfo179 }, // Inst #2553 = SLLI_W |
| { 2552, 3, 1, 4, 625, 0, 0, 0, 0x6ULL, nullptr, OperandInfo178 }, // Inst #2552 = SLLI_H |
| { 2551, 3, 1, 4, 625, 0, 0, 0, 0x6ULL, nullptr, OperandInfo177 }, // Inst #2551 = SLLI_D |
| { 2550, 3, 1, 4, 625, 0, 0, 0, 0x6ULL, nullptr, OperandInfo176 }, // Inst #2550 = SLLI_B |
| { 2549, 2, 1, 4, 812, 0, 0, 0|(1ULL<<MCID::MoveReg), 0x1ULL, nullptr, OperandInfo122 }, // Inst #2549 = SLL64_64 |
| { 2548, 2, 1, 4, 812, 0, 0, 0|(1ULL<<MCID::MoveReg), 0x1ULL, nullptr, OperandInfo245 }, // Inst #2548 = SLL64_32 |
| { 2547, 3, 1, 2, 798, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo170 }, // Inst #2547 = SLL16_MMR6 |
| { 2546, 3, 1, 2, 760, 0, 0, 0, 0x0ULL, nullptr, OperandInfo170 }, // Inst #2546 = SLL16_MM |
| { 2545, 3, 1, 4, 505, 0, 0, 0, 0x1ULL, nullptr, OperandInfo73 }, // Inst #2545 = SLL |
| { 2544, 4, 1, 4, 519, 0, 0, 0, 0x6ULL, nullptr, OperandInfo357 }, // Inst #2544 = SLD_W |
| { 2543, 4, 1, 4, 519, 0, 0, 0, 0x6ULL, nullptr, OperandInfo356 }, // Inst #2543 = SLD_H |
| { 2542, 4, 1, 4, 519, 0, 0, 0, 0x6ULL, nullptr, OperandInfo355 }, // Inst #2542 = SLD_D |
| { 2541, 4, 1, 4, 519, 0, 0, 0, 0x6ULL, nullptr, OperandInfo354 }, // Inst #2541 = SLD_B |
| { 2540, 4, 1, 4, 519, 0, 0, 0, 0x6ULL, nullptr, OperandInfo195 }, // Inst #2540 = SLDI_W |
| { 2539, 4, 1, 4, 519, 0, 0, 0, 0x6ULL, nullptr, OperandInfo194 }, // Inst #2539 = SLDI_H |
| { 2538, 4, 1, 4, 519, 0, 0, 0, 0x6ULL, nullptr, OperandInfo193 }, // Inst #2538 = SLDI_D |
| { 2537, 4, 1, 4, 519, 0, 0, 0, 0x6ULL, nullptr, OperandInfo192 }, // Inst #2537 = SLDI_B |
| { 2536, 1, 0, 4, 996, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo2 }, // Inst #2536 = SIGRIE_MMR6 |
| { 2535, 1, 0, 4, 935, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo2 }, // Inst #2535 = SIGRIE |
| { 2534, 3, 0, 4, 1155, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo96 }, // Inst #2534 = SH_MMR6 |
| { 2533, 3, 0, 4, 1132, 0, 0, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, OperandInfo96 }, // Inst #2533 = SH_MM |
| { 2532, 3, 1, 4, 1617, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo353 }, // Inst #2532 = SHRL_QB_MM |
| { 2531, 3, 1, 4, 1451, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo353 }, // Inst #2531 = SHRL_QB |
| { 2530, 3, 1, 4, 1660, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo353 }, // Inst #2530 = SHRL_PH_MMR2 |
| { 2529, 3, 1, 4, 1496, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo353 }, // Inst #2529 = SHRL_PH |
| { 2528, 3, 1, 4, 1616, 0, 0, 0, 0x6ULL, nullptr, OperandInfo352 }, // Inst #2528 = SHRLV_QB_MM |
| { 2527, 3, 1, 4, 1450, 0, 0, 0, 0x6ULL, nullptr, OperandInfo352 }, // Inst #2527 = SHRLV_QB |
| { 2526, 3, 1, 4, 1661, 0, 0, 0, 0x6ULL, nullptr, OperandInfo352 }, // Inst #2526 = SHRLV_PH_MMR2 |
| { 2525, 3, 1, 4, 1497, 0, 0, 0, 0x6ULL, nullptr, OperandInfo352 }, // Inst #2525 = SHRLV_PH |
| { 2524, 3, 1, 4, 1615, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo73 }, // Inst #2524 = SHRA_R_W_MM |
| { 2523, 3, 1, 4, 1449, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo73 }, // Inst #2523 = SHRA_R_W |
| { 2522, 3, 1, 4, 1657, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo353 }, // Inst #2522 = SHRA_R_QB_MMR2 |
| { 2521, 3, 1, 4, 1493, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo353 }, // Inst #2521 = SHRA_R_QB |
| { 2520, 3, 1, 4, 1614, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo353 }, // Inst #2520 = SHRA_R_PH_MM |
| { 2519, 3, 1, 4, 1448, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo353 }, // Inst #2519 = SHRA_R_PH |
| { 2518, 3, 1, 4, 1656, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo353 }, // Inst #2518 = SHRA_QB_MMR2 |
| { 2517, 3, 1, 4, 1492, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo353 }, // Inst #2517 = SHRA_QB |
| { 2516, 3, 1, 4, 1613, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo353 }, // Inst #2516 = SHRA_PH_MM |
| { 2515, 3, 1, 4, 1447, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo353 }, // Inst #2515 = SHRA_PH |
| { 2514, 3, 1, 4, 1612, 0, 0, 0, 0x6ULL, nullptr, OperandInfo72 }, // Inst #2514 = SHRAV_R_W_MM |
| { 2513, 3, 1, 4, 1446, 0, 0, 0, 0x6ULL, nullptr, OperandInfo72 }, // Inst #2513 = SHRAV_R_W |
| { 2512, 3, 1, 4, 1659, 0, 0, 0, 0x6ULL, nullptr, OperandInfo352 }, // Inst #2512 = SHRAV_R_QB_MMR2 |
| { 2511, 3, 1, 4, 1495, 0, 0, 0, 0x6ULL, nullptr, OperandInfo352 }, // Inst #2511 = SHRAV_R_QB |
| { 2510, 3, 1, 4, 1611, 0, 0, 0, 0x6ULL, nullptr, OperandInfo352 }, // Inst #2510 = SHRAV_R_PH_MM |
| { 2509, 3, 1, 4, 1445, 0, 0, 0, 0x6ULL, nullptr, OperandInfo352 }, // Inst #2509 = SHRAV_R_PH |
| { 2508, 3, 1, 4, 1658, 0, 0, 0, 0x6ULL, nullptr, OperandInfo352 }, // Inst #2508 = SHRAV_QB_MMR2 |
| { 2507, 3, 1, 4, 1494, 0, 0, 0, 0x6ULL, nullptr, OperandInfo352 }, // Inst #2507 = SHRAV_QB |
| { 2506, 3, 1, 4, 1610, 0, 0, 0, 0x6ULL, nullptr, OperandInfo352 }, // Inst #2506 = SHRAV_PH_MM |
| { 2505, 3, 1, 4, 1444, 0, 0, 0, 0x6ULL, nullptr, OperandInfo352 }, // Inst #2505 = SHRAV_PH |
| { 2504, 3, 1, 4, 1609, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList34, OperandInfo73 }, // Inst #2504 = SHLL_S_W_MM |
| { 2503, 3, 1, 4, 1443, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList34, OperandInfo73 }, // Inst #2503 = SHLL_S_W |
| { 2502, 3, 1, 4, 1608, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList34, OperandInfo353 }, // Inst #2502 = SHLL_S_PH_MM |
| { 2501, 3, 1, 4, 1442, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList34, OperandInfo353 }, // Inst #2501 = SHLL_S_PH |
| { 2500, 3, 1, 4, 1607, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList34, OperandInfo353 }, // Inst #2500 = SHLL_QB_MM |
| { 2499, 3, 1, 4, 1441, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList34, OperandInfo353 }, // Inst #2499 = SHLL_QB |
| { 2498, 3, 1, 4, 1606, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList34, OperandInfo353 }, // Inst #2498 = SHLL_PH_MM |
| { 2497, 3, 1, 4, 1440, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList34, OperandInfo353 }, // Inst #2497 = SHLL_PH |
| { 2496, 3, 1, 4, 1605, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList34, OperandInfo72 }, // Inst #2496 = SHLLV_S_W_MM |
| { 2495, 3, 1, 4, 1439, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList34, OperandInfo72 }, // Inst #2495 = SHLLV_S_W |
| { 2494, 3, 1, 4, 1604, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList34, OperandInfo352 }, // Inst #2494 = SHLLV_S_PH_MM |
| { 2493, 3, 1, 4, 1438, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList34, OperandInfo352 }, // Inst #2493 = SHLLV_S_PH |
| { 2492, 3, 1, 4, 1603, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList34, OperandInfo352 }, // Inst #2492 = SHLLV_QB_MM |
| { 2491, 3, 1, 4, 1437, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList34, OperandInfo352 }, // Inst #2491 = SHLLV_QB |
| { 2490, 3, 1, 4, 1602, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList34, OperandInfo352 }, // Inst #2490 = SHLLV_PH_MM |
| { 2489, 3, 1, 4, 1436, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList34, OperandInfo352 }, // Inst #2489 = SHLLV_PH |
| { 2488, 3, 1, 4, 1601, 0, 0, 0, 0x6ULL, nullptr, OperandInfo351 }, // Inst #2488 = SHILO_MM |
| { 2487, 3, 1, 4, 1600, 0, 0, 0, 0x6ULL, nullptr, OperandInfo331 }, // Inst #2487 = SHILOV_MM |
| { 2486, 3, 1, 4, 1434, 0, 0, 0, 0x6ULL, nullptr, OperandInfo331 }, // Inst #2486 = SHILOV |
| { 2485, 3, 1, 4, 1435, 0, 0, 0, 0x6ULL, nullptr, OperandInfo351 }, // Inst #2485 = SHILO |
| { 2484, 3, 1, 4, 543, 0, 0, 0, 0x6ULL, nullptr, OperandInfo179 }, // Inst #2484 = SHF_W |
| { 2483, 3, 1, 4, 543, 0, 0, 0, 0x6ULL, nullptr, OperandInfo178 }, // Inst #2483 = SHF_H |
| { 2482, 3, 1, 4, 543, 0, 0, 0, 0x6ULL, nullptr, OperandInfo176 }, // Inst #2482 = SHF_B |
| { 2481, 3, 0, 4, 1101, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo96 }, // Inst #2481 = SHE_MM |
| { 2480, 3, 0, 4, 461, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo96 }, // Inst #2480 = SHE |
| { 2479, 3, 0, 4, 1178, 0, 0, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, OperandInfo113 }, // Inst #2479 = SH64 |
| { 2478, 3, 0, 2, 1155, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo345 }, // Inst #2478 = SH16_MMR6 |
| { 2477, 3, 0, 2, 1132, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo345 }, // Inst #2477 = SH16_MM |
| { 2476, 3, 0, 4, 453, 0, 0, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, OperandInfo96 }, // Inst #2476 = SH |
| { 2475, 3, 1, 4, 1207, 0, 0, 0, 0x2ULL, nullptr, OperandInfo70 }, // Inst #2475 = SEQi |
| { 2474, 3, 1, 4, 1206, 0, 0, 0, 0x1ULL, nullptr, OperandInfo71 }, // Inst #2474 = SEQ |
| { 2473, 4, 1, 4, 1327, 0, 0, 0, 0x6ULL, nullptr, OperandInfo350 }, // Inst #2473 = SEL_S_MMR6 |
| { 2472, 4, 1, 4, 1233, 0, 0, 0, 0x6ULL, nullptr, OperandInfo350 }, // Inst #2472 = SEL_S |
| { 2471, 4, 1, 4, 1326, 0, 0, 0, 0x6ULL, nullptr, OperandInfo302 }, // Inst #2471 = SEL_D_MMR6 |
| { 2470, 4, 1, 4, 1232, 0, 0, 0, 0x6ULL, nullptr, OperandInfo302 }, // Inst #2470 = SEL_D |
| { 2469, 3, 1, 4, 1325, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo250 }, // Inst #2469 = SELNEZ_S_MMR6 |
| { 2468, 3, 1, 4, 1221, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo250 }, // Inst #2468 = SELNEZ_S |
| { 2467, 3, 1, 4, 797, 0, 0, 0, 0x6ULL, nullptr, OperandInfo72 }, // Inst #2467 = SELNEZ_MMR6 |
| { 2466, 3, 1, 4, 1324, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo173 }, // Inst #2466 = SELNEZ_D_MMR6 |
| { 2465, 3, 1, 4, 1222, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo173 }, // Inst #2465 = SELNEZ_D |
| { 2464, 3, 1, 4, 852, 0, 0, 0, 0x6ULL, nullptr, OperandInfo71 }, // Inst #2464 = SELNEZ64 |
| { 2463, 3, 1, 4, 734, 0, 0, 0, 0x6ULL, nullptr, OperandInfo72 }, // Inst #2463 = SELNEZ |
| { 2462, 3, 1, 4, 1325, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo250 }, // Inst #2462 = SELEQZ_S_MMR6 |
| { 2461, 3, 1, 4, 1221, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo250 }, // Inst #2461 = SELEQZ_S |
| { 2460, 3, 1, 4, 797, 0, 0, 0, 0x6ULL, nullptr, OperandInfo72 }, // Inst #2460 = SELEQZ_MMR6 |
| { 2459, 3, 1, 4, 1324, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo173 }, // Inst #2459 = SELEQZ_D_MMR6 |
| { 2458, 3, 1, 4, 1222, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo173 }, // Inst #2458 = SELEQZ_D |
| { 2457, 3, 1, 4, 852, 0, 0, 0, 0x6ULL, nullptr, OperandInfo71 }, // Inst #2457 = SELEQZ64 |
| { 2456, 3, 1, 4, 734, 0, 0, 0, 0x6ULL, nullptr, OperandInfo72 }, // Inst #2456 = SELEQZ |
| { 2455, 2, 1, 4, 759, 0, 0, 0, 0x1ULL, nullptr, OperandInfo45 }, // Inst #2455 = SEH_MM |
| { 2454, 2, 1, 4, 811, 0, 0, 0, 0x1ULL, nullptr, OperandInfo122 }, // Inst #2454 = SEH64 |
| { 2453, 2, 1, 4, 503, 0, 0, 0, 0x1ULL, nullptr, OperandInfo45 }, // Inst #2453 = SEH |
| { 2452, 2, 1, 4, 758, 0, 0, 0, 0x1ULL, nullptr, OperandInfo45 }, // Inst #2452 = SEB_MM |
| { 2451, 2, 1, 4, 810, 0, 0, 0, 0x1ULL, nullptr, OperandInfo122 }, // Inst #2451 = SEB64 |
| { 2450, 2, 1, 4, 502, 0, 0, 0, 0x1ULL, nullptr, OperandInfo45 }, // Inst #2450 = SEB |
| { 2449, 3, 0, 4, 700, 0, 0, 0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, OperandInfo285 }, // Inst #2449 = SDXC164 |
| { 2448, 3, 0, 4, 700, 0, 0, 0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, OperandInfo284 }, // Inst #2448 = SDXC1 |
| { 2447, 3, 0, 4, 1183, 0, 0, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, OperandInfo113 }, // Inst #2447 = SDR |
| { 2446, 3, 0, 4, 1182, 0, 0, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, OperandInfo113 }, // Inst #2446 = SDL |
| { 2445, 2, 0, 4, 885, 0, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList6, OperandInfo45 }, // Inst #2445 = SDIV_MM |
| { 2444, 2, 0, 4, 865, 0, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList6, OperandInfo45 }, // Inst #2444 = SDIV |
| { 2443, 3, 0, 4, 458, 0, 0, 0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, OperandInfo278 }, // Inst #2443 = SDC3 |
| { 2442, 3, 0, 4, 1085, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo276 }, // Inst #2442 = SDC2_R6 |
| { 2441, 3, 0, 4, 1154, 0, 0, 0|(1ULL<<MCID::MayStore), 0x6ULL, nullptr, OperandInfo277 }, // Inst #2441 = SDC2_MMR6 |
| { 2440, 3, 0, 4, 457, 0, 0, 0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, OperandInfo276 }, // Inst #2440 = SDC2 |
| { 2439, 3, 0, 4, 1290, 0, 0, 0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, OperandInfo275 }, // Inst #2439 = SDC1_MM_D64 |
| { 2438, 3, 0, 4, 1290, 0, 0, 0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, OperandInfo158 }, // Inst #2438 = SDC1_MM_D32 |
| { 2437, 3, 0, 4, 1338, 0, 0, 0|(1ULL<<MCID::MayStore), 0x6ULL, nullptr, OperandInfo275 }, // Inst #2437 = SDC1_D64_MMR6 |
| { 2436, 3, 0, 4, 699, 0, 0, 0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, OperandInfo275 }, // Inst #2436 = SDC164 |
| { 2435, 3, 0, 4, 699, 0, 0, 0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, OperandInfo158 }, // Inst #2435 = SDC1 |
| { 2434, 1, 0, 4, 938, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo2 }, // Inst #2434 = SDBBP_R6 |
| { 2433, 1, 0, 4, 1008, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo2 }, // Inst #2433 = SDBBP_MMR6 |
| { 2432, 1, 0, 4, 967, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, OperandInfo2 }, // Inst #2432 = SDBBP_MM |
| { 2431, 1, 0, 2, 1008, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo2 }, // Inst #2431 = SDBBP16_MMR6 |
| { 2430, 1, 0, 2, 967, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo2 }, // Inst #2430 = SDBBP16_MM |
| { 2429, 1, 0, 4, 389, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, OperandInfo2 }, // Inst #2429 = SDBBP |
| { 2428, 3, 0, 4, 1175, 0, 0, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, OperandInfo113 }, // Inst #2428 = SD |
| { 2427, 4, 1, 4, 1086, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo347 }, // Inst #2427 = SC_R6 |
| { 2426, 4, 1, 4, 1080, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo346 }, // Inst #2426 = SC_MMR6 |
| { 2425, 4, 1, 4, 1131, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo346 }, // Inst #2425 = SC_MM |
| { 2424, 4, 1, 4, 1105, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo346 }, // Inst #2424 = SCE_MM |
| { 2423, 4, 1, 4, 463, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo346 }, // Inst #2423 = SCE |
| { 2422, 4, 1, 4, 1189, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo349 }, // Inst #2422 = SCD_R6 |
| { 2421, 4, 1, 4, 1176, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo348 }, // Inst #2421 = SCD |
| { 2420, 4, 1, 4, 1188, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo347 }, // Inst #2420 = SC64_R6 |
| { 2419, 4, 1, 4, 1176, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo346 }, // Inst #2419 = SC64 |
| { 2418, 4, 1, 4, 459, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo346 }, // Inst #2418 = SC |
| { 2417, 3, 0, 4, 1153, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo96 }, // Inst #2417 = SB_MMR6 |
| { 2416, 3, 0, 4, 1100, 0, 0, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, OperandInfo96 }, // Inst #2416 = SB_MM |
| { 2415, 3, 0, 4, 1099, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo96 }, // Inst #2415 = SBE_MM |
| { 2414, 3, 0, 4, 460, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo96 }, // Inst #2414 = SBE |
| { 2413, 3, 0, 4, 1177, 0, 0, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, OperandInfo113 }, // Inst #2413 = SB64 |
| { 2412, 3, 0, 2, 1153, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo345 }, // Inst #2412 = SB16_MMR6 |
| { 2411, 3, 0, 2, 1130, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo345 }, // Inst #2411 = SB16_MM |
| { 2410, 3, 0, 4, 452, 0, 0, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, OperandInfo96 }, // Inst #2410 = SB |
| { 2409, 3, 1, 4, 527, 0, 0, 0, 0x6ULL, nullptr, OperandInfo179 }, // Inst #2409 = SAT_U_W |
| { 2408, 3, 1, 4, 527, 0, 0, 0, 0x6ULL, nullptr, OperandInfo178 }, // Inst #2408 = SAT_U_H |
| { 2407, 3, 1, 4, 527, 0, 0, 0, 0x6ULL, nullptr, OperandInfo177 }, // Inst #2407 = SAT_U_D |
| { 2406, 3, 1, 4, 527, 0, 0, 0, 0x6ULL, nullptr, OperandInfo176 }, // Inst #2406 = SAT_U_B |
| { 2405, 3, 1, 4, 527, 0, 0, 0, 0x6ULL, nullptr, OperandInfo179 }, // Inst #2405 = SAT_S_W |
| { 2404, 3, 1, 4, 527, 0, 0, 0, 0x6ULL, nullptr, OperandInfo178 }, // Inst #2404 = SAT_S_H |
| { 2403, 3, 1, 4, 527, 0, 0, 0, 0x6ULL, nullptr, OperandInfo177 }, // Inst #2403 = SAT_S_D |
| { 2402, 3, 1, 4, 527, 0, 0, 0, 0x6ULL, nullptr, OperandInfo176 }, // Inst #2402 = SAT_S_B |
| { 2401, 2, 0, 4, 1210, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, OperandInfo122 }, // Inst #2401 = SAAD |
| { 2400, 2, 0, 4, 1210, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, OperandInfo122 }, // Inst #2400 = SAA |
| { 2399, 0, 0, 2, 1108, 1, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, nullptr }, // Inst #2399 = RestoreX16 |
| { 2398, 0, 0, 2, 1108, 1, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, nullptr }, // Inst #2398 = Restore16 |
| { 2397, 2, 1, 4, 1288, 0, 0, 0, 0x4ULL, nullptr, OperandInfo207 }, // Inst #2397 = RSQRT_S_MM |
| { 2396, 2, 1, 4, 655, 0, 0, 0, 0x4ULL, nullptr, OperandInfo207 }, // Inst #2396 = RSQRT_S |
| { 2395, 2, 1, 4, 1289, 0, 0, 0, 0x4ULL, nullptr, OperandInfo203 }, // Inst #2395 = RSQRT_D64_MM |
| { 2394, 2, 1, 4, 653, 0, 0, 0, 0x4ULL, nullptr, OperandInfo203 }, // Inst #2394 = RSQRT_D64 |
| { 2393, 2, 1, 4, 1289, 0, 0, 0, 0x4ULL, nullptr, OperandInfo248 }, // Inst #2393 = RSQRT_D32_MM |
| { 2392, 2, 1, 4, 653, 0, 0, 0, 0x4ULL, nullptr, OperandInfo248 }, // Inst #2392 = RSQRT_D32 |
| { 2391, 2, 1, 4, 1309, 0, 0, 0, 0x4ULL, nullptr, OperandInfo207 }, // Inst #2391 = ROUND_W_S_MMR6 |
| { 2390, 2, 1, 4, 1255, 0, 0, 0, 0x4ULL, nullptr, OperandInfo207 }, // Inst #2390 = ROUND_W_S_MM |
| { 2389, 2, 1, 4, 719, 0, 0, 0, 0x4ULL, nullptr, OperandInfo207 }, // Inst #2389 = ROUND_W_S |
| { 2388, 2, 1, 4, 1255, 0, 0, 0, 0x4ULL, nullptr, OperandInfo205 }, // Inst #2388 = ROUND_W_MM |
| { 2387, 2, 1, 4, 1309, 0, 0, 0, 0x4ULL, nullptr, OperandInfo203 }, // Inst #2387 = ROUND_W_D_MMR6 |
| { 2386, 2, 1, 4, 719, 0, 0, 0, 0x4ULL, nullptr, OperandInfo206 }, // Inst #2386 = ROUND_W_D64 |
| { 2385, 2, 1, 4, 719, 0, 0, 0, 0x4ULL, nullptr, OperandInfo205 }, // Inst #2385 = ROUND_W_D32 |
| { 2384, 2, 1, 4, 1309, 0, 0, 0, 0x4ULL, nullptr, OperandInfo204 }, // Inst #2384 = ROUND_L_S_MMR6 |
| { 2383, 2, 1, 4, 719, 0, 0, 0, 0x4ULL, nullptr, OperandInfo204 }, // Inst #2383 = ROUND_L_S |
| { 2382, 2, 1, 4, 1309, 0, 0, 0, 0x4ULL, nullptr, OperandInfo203 }, // Inst #2382 = ROUND_L_D_MMR6 |
| { 2381, 2, 1, 4, 719, 0, 0, 0, 0x4ULL, nullptr, OperandInfo203 }, // Inst #2381 = ROUND_L_D64 |
| { 2380, 3, 1, 4, 757, 0, 0, 0, 0x1ULL, nullptr, OperandInfo73 }, // Inst #2380 = ROTR_MM |
| { 2379, 3, 1, 4, 756, 0, 0, 0, 0x1ULL, nullptr, OperandInfo72 }, // Inst #2379 = ROTRV_MM |
| { 2378, 3, 1, 4, 720, 0, 0, 0, 0x1ULL, nullptr, OperandInfo72 }, // Inst #2378 = ROTRV |
| { 2377, 3, 1, 4, 501, 0, 0, 0, 0x1ULL, nullptr, OperandInfo73 }, // Inst #2377 = ROTR |
| { 2376, 2, 1, 4, 1328, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo207 }, // Inst #2376 = RINT_S_MMR6 |
| { 2375, 2, 1, 4, 1229, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo207 }, // Inst #2375 = RINT_S |
| { 2374, 2, 1, 4, 1328, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo203 }, // Inst #2374 = RINT_D_MMR6 |
| { 2373, 2, 1, 4, 1230, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo203 }, // Inst #2373 = RINT_D |
| { 2372, 2, 1, 4, 1599, 0, 0, 0, 0x6ULL, nullptr, OperandInfo344 }, // Inst #2372 = REPL_QB_MM |
| { 2371, 2, 1, 4, 1433, 0, 0, 0, 0x6ULL, nullptr, OperandInfo344 }, // Inst #2371 = REPL_QB |
| { 2370, 2, 1, 4, 1598, 0, 0, 0, 0x6ULL, nullptr, OperandInfo344 }, // Inst #2370 = REPL_PH_MM |
| { 2369, 2, 1, 4, 1432, 0, 0, 0, 0x6ULL, nullptr, OperandInfo344 }, // Inst #2369 = REPL_PH |
| { 2368, 2, 1, 4, 1597, 0, 0, 0, 0x6ULL, nullptr, OperandInfo343 }, // Inst #2368 = REPLV_QB_MM |
| { 2367, 2, 1, 4, 1431, 0, 0, 0, 0x6ULL, nullptr, OperandInfo343 }, // Inst #2367 = REPLV_QB |
| { 2366, 2, 1, 4, 1596, 0, 0, 0, 0x6ULL, nullptr, OperandInfo343 }, // Inst #2366 = REPLV_PH_MM |
| { 2365, 2, 1, 4, 1430, 0, 0, 0, 0x6ULL, nullptr, OperandInfo343 }, // Inst #2365 = REPLV_PH |
| { 2364, 2, 1, 4, 1288, 0, 0, 0, 0x4ULL, nullptr, OperandInfo207 }, // Inst #2364 = RECIP_S_MM |
| { 2363, 2, 1, 4, 654, 0, 0, 0, 0x4ULL, nullptr, OperandInfo207 }, // Inst #2363 = RECIP_S |
| { 2362, 2, 1, 4, 1289, 0, 0, 0, 0x4ULL, nullptr, OperandInfo203 }, // Inst #2362 = RECIP_D64_MM |
| { 2361, 2, 1, 4, 652, 0, 0, 0, 0x4ULL, nullptr, OperandInfo203 }, // Inst #2361 = RECIP_D64 |
| { 2360, 2, 1, 4, 1289, 0, 0, 0, 0x4ULL, nullptr, OperandInfo248 }, // Inst #2360 = RECIP_D32_MM |
| { 2359, 2, 1, 4, 652, 0, 0, 0, 0x4ULL, nullptr, OperandInfo248 }, // Inst #2359 = RECIP_D32 |
| { 2358, 2, 1, 4, 1036, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo45 }, // Inst #2358 = RDPGPR_MMR6 |
| { 2357, 3, 1, 4, 900, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, OperandInfo341 }, // Inst #2357 = RDHWR_MMR6 |
| { 2356, 3, 1, 4, 891, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, OperandInfo341 }, // Inst #2356 = RDHWR_MM |
| { 2355, 3, 1, 4, 909, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, OperandInfo342 }, // Inst #2355 = RDHWR64 |
| { 2354, 3, 1, 4, 480, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, OperandInfo341 }, // Inst #2354 = RDHWR |
| { 2353, 2, 1, 4, 1595, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, OperandInfo114 }, // Inst #2353 = RDDSP_MM |
| { 2352, 2, 1, 4, 1429, 0, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, OperandInfo114 }, // Inst #2352 = RDDSP |
| { 2351, 2, 1, 4, 1594, 0, 0, 0, 0x6ULL, nullptr, OperandInfo337 }, // Inst #2351 = RADDU_W_QB_MM |
| { 2350, 2, 1, 4, 1428, 0, 0, 0, 0x6ULL, nullptr, OperandInfo337 }, // Inst #2350 = RADDU_W_QB |
| { 2349, 3, 1, 4, 645, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo173 }, // Inst #2349 = PUU_PS64 |
| { 2348, 3, 1, 4, 645, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo173 }, // Inst #2348 = PUL_PS64 |
| { 2347, 4, 1, 4, 1655, 0, 0, 0, 0x6ULL, nullptr, OperandInfo182 }, // Inst #2347 = PREPEND_MMR2 |
| { 2346, 4, 1, 4, 1491, 0, 0, 0, 0x6ULL, nullptr, OperandInfo182 }, // Inst #2346 = PREPEND |
| { 2345, 3, 0, 4, 1087, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo202 }, // Inst #2345 = PREF_R6 |
| { 2344, 3, 0, 4, 1161, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo202 }, // Inst #2344 = PREF_MMR6 |
| { 2343, 3, 0, 4, 1139, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo202 }, // Inst #2343 = PREF_MM |
| { 2342, 3, 0, 4, 1139, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo340 }, // Inst #2342 = PREFX_MM |
| { 2341, 3, 0, 4, 1106, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo202 }, // Inst #2341 = PREFE_MM |
| { 2340, 3, 0, 4, 469, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo202 }, // Inst #2340 = PREFE |
| { 2339, 3, 0, 4, 468, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo202 }, // Inst #2339 = PREF |
| { 2338, 4, 1, 4, 1654, 0, 0, 0, 0x6ULL, nullptr, OperandInfo339 }, // Inst #2338 = PRECR_SRA_R_PH_W_MMR2 |
| { 2337, 4, 1, 4, 1490, 0, 0, 0, 0x6ULL, nullptr, OperandInfo339 }, // Inst #2337 = PRECR_SRA_R_PH_W |
| { 2336, 4, 1, 4, 1653, 0, 0, 0, 0x6ULL, nullptr, OperandInfo339 }, // Inst #2336 = PRECR_SRA_PH_W_MMR2 |
| { 2335, 4, 1, 4, 1489, 0, 0, 0, 0x6ULL, nullptr, OperandInfo339 }, // Inst #2335 = PRECR_SRA_PH_W |
| { 2334, 3, 1, 4, 1652, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo172 }, // Inst #2334 = PRECR_QB_PH_MMR2 |
| { 2333, 3, 1, 4, 1488, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo172 }, // Inst #2333 = PRECR_QB_PH |
| { 2332, 3, 1, 4, 1593, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList34, OperandInfo338 }, // Inst #2332 = PRECRQ_RS_PH_W_MM |
| { 2331, 3, 1, 4, 1427, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList34, OperandInfo338 }, // Inst #2331 = PRECRQ_RS_PH_W |
| { 2330, 3, 1, 4, 1592, 0, 0, 0, 0x6ULL, nullptr, OperandInfo172 }, // Inst #2330 = PRECRQ_QB_PH_MM |
| { 2329, 3, 1, 4, 1426, 0, 0, 0, 0x6ULL, nullptr, OperandInfo172 }, // Inst #2329 = PRECRQ_QB_PH |
| { 2328, 3, 1, 4, 1591, 0, 0, 0, 0x6ULL, nullptr, OperandInfo338 }, // Inst #2328 = PRECRQ_PH_W_MM |
| { 2327, 3, 1, 4, 1425, 0, 0, 0, 0x6ULL, nullptr, OperandInfo338 }, // Inst #2327 = PRECRQ_PH_W |
| { 2326, 3, 1, 4, 1590, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList34, OperandInfo172 }, // Inst #2326 = PRECRQU_S_QB_PH_MM |
| { 2325, 3, 1, 4, 1424, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList34, OperandInfo172 }, // Inst #2325 = PRECRQU_S_QB_PH |
| { 2324, 2, 1, 4, 1589, 0, 0, 0, 0x6ULL, nullptr, OperandInfo168 }, // Inst #2324 = PRECEU_PH_QBR_MM |
| { 2323, 2, 1, 4, 1588, 0, 0, 0, 0x6ULL, nullptr, OperandInfo168 }, // Inst #2323 = PRECEU_PH_QBRA_MM |
| { 2322, 2, 1, 4, 1422, 0, 0, 0, 0x6ULL, nullptr, OperandInfo168 }, // Inst #2322 = PRECEU_PH_QBRA |
| { 2321, 2, 1, 4, 1423, 0, 0, 0, 0x6ULL, nullptr, OperandInfo168 }, // Inst #2321 = PRECEU_PH_QBR |
| { 2320, 2, 1, 4, 1587, 0, 0, 0, 0x6ULL, nullptr, OperandInfo168 }, // Inst #2320 = PRECEU_PH_QBL_MM |
| { 2319, 2, 1, 4, 1586, 0, 0, 0, 0x6ULL, nullptr, OperandInfo168 }, // Inst #2319 = PRECEU_PH_QBLA_MM |
| { 2318, 2, 1, 4, 1420, 0, 0, 0, 0x6ULL, nullptr, OperandInfo168 }, // Inst #2318 = PRECEU_PH_QBLA |
| { 2317, 2, 1, 4, 1421, 0, 0, 0, 0x6ULL, nullptr, OperandInfo168 }, // Inst #2317 = PRECEU_PH_QBL |
| { 2316, 2, 1, 4, 1585, 0, 0, 0, 0x6ULL, nullptr, OperandInfo337 }, // Inst #2316 = PRECEQ_W_PHR_MM |
| { 2315, 2, 1, 4, 1419, 0, 0, 0, 0x6ULL, nullptr, OperandInfo337 }, // Inst #2315 = PRECEQ_W_PHR |
| { 2314, 2, 1, 4, 1584, 0, 0, 0, 0x6ULL, nullptr, OperandInfo337 }, // Inst #2314 = PRECEQ_W_PHL_MM |
| { 2313, 2, 1, 4, 1418, 0, 0, 0, 0x6ULL, nullptr, OperandInfo337 }, // Inst #2313 = PRECEQ_W_PHL |
| { 2312, 2, 1, 4, 1583, 0, 0, 0, 0x6ULL, nullptr, OperandInfo168 }, // Inst #2312 = PRECEQU_PH_QBR_MM |
| { 2311, 2, 1, 4, 1582, 0, 0, 0, 0x6ULL, nullptr, OperandInfo168 }, // Inst #2311 = PRECEQU_PH_QBRA_MM |
| { 2310, 2, 1, 4, 1416, 0, 0, 0, 0x6ULL, nullptr, OperandInfo168 }, // Inst #2310 = PRECEQU_PH_QBRA |
| { 2309, 2, 1, 4, 1417, 0, 0, 0, 0x6ULL, nullptr, OperandInfo168 }, // Inst #2309 = PRECEQU_PH_QBR |
| { 2308, 2, 1, 4, 1581, 0, 0, 0, 0x6ULL, nullptr, OperandInfo168 }, // Inst #2308 = PRECEQU_PH_QBL_MM |
| { 2307, 2, 1, 4, 1580, 0, 0, 0, 0x6ULL, nullptr, OperandInfo168 }, // Inst #2307 = PRECEQU_PH_QBLA_MM |
| { 2306, 2, 1, 4, 1414, 0, 0, 0, 0x6ULL, nullptr, OperandInfo168 }, // Inst #2306 = PRECEQU_PH_QBLA |
| { 2305, 2, 1, 4, 1415, 0, 0, 0, 0x6ULL, nullptr, OperandInfo168 }, // Inst #2305 = PRECEQU_PH_QBL |
| { 2304, 2, 1, 4, 1203, 0, 0, 0, 0x1ULL, nullptr, OperandInfo45 }, // Inst #2304 = POP |
| { 2303, 3, 1, 4, 645, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo173 }, // Inst #2303 = PLU_PS64 |
| { 2302, 3, 1, 4, 645, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo173 }, // Inst #2302 = PLL_PS64 |
| { 2301, 3, 1, 4, 1579, 1, 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL, ImplicitList11, OperandInfo172 }, // Inst #2301 = PICK_QB_MM |
| { 2300, 3, 1, 4, 1413, 1, 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL, ImplicitList11, OperandInfo172 }, // Inst #2300 = PICK_QB |
| { 2299, 3, 1, 4, 1578, 1, 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL, ImplicitList11, OperandInfo172 }, // Inst #2299 = PICK_PH_MM |
| { 2298, 3, 1, 4, 1412, 1, 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL, ImplicitList11, OperandInfo172 }, // Inst #2298 = PICK_PH |
| { 2297, 2, 1, 4, 526, 0, 0, 0, 0x6ULL, nullptr, OperandInfo77 }, // Inst #2297 = PCNT_W |
| { 2296, 2, 1, 4, 526, 0, 0, 0, 0x6ULL, nullptr, OperandInfo335 }, // Inst #2296 = PCNT_H |
| { 2295, 2, 1, 4, 526, 0, 0, 0, 0x6ULL, nullptr, OperandInfo76 }, // Inst #2295 = PCNT_D |
| { 2294, 2, 1, 4, 526, 0, 0, 0, 0x6ULL, nullptr, OperandInfo312 }, // Inst #2294 = PCNT_B |
| { 2293, 3, 1, 4, 626, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #2293 = PCKOD_W |
| { 2292, 3, 1, 4, 626, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #2292 = PCKOD_H |
| { 2291, 3, 1, 4, 626, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #2291 = PCKOD_D |
| { 2290, 3, 1, 4, 626, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #2290 = PCKOD_B |
| { 2289, 3, 1, 4, 626, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #2289 = PCKEV_W |
| { 2288, 3, 1, 4, 626, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #2288 = PCKEV_H |
| { 2287, 3, 1, 4, 626, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #2287 = PCKEV_D |
| { 2286, 3, 1, 4, 626, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #2286 = PCKEV_B |
| { 2285, 0, 0, 4, 1051, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr }, // Inst #2285 = PAUSE_MMR6 |
| { 2284, 0, 0, 4, 1034, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr }, // Inst #2284 = PAUSE_MM |
| { 2283, 0, 0, 4, 405, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr }, // Inst #2283 = PAUSE |
| { 2282, 3, 1, 4, 1577, 0, 0, 0, 0x6ULL, nullptr, OperandInfo172 }, // Inst #2282 = PACKRL_PH_MM |
| { 2281, 3, 1, 4, 1411, 0, 0, 0, 0x6ULL, nullptr, OperandInfo172 }, // Inst #2281 = PACKRL_PH |
| { 2280, 3, 1, 2, 735, 0, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, OperandInfo186 }, // Inst #2280 = OrRxRxRy16 |
| { 2279, 3, 1, 4, 755, 0, 0, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, OperandInfo73 }, // Inst #2279 = ORi_MM |
| { 2278, 3, 1, 4, 809, 0, 0, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, OperandInfo70 }, // Inst #2278 = ORi64 |
| { 2277, 3, 1, 4, 500, 0, 0, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, OperandInfo73 }, // Inst #2277 = ORi |
| { 2276, 3, 1, 4, 548, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #2276 = OR_V |
| { 2275, 3, 1, 4, 795, 0, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, OperandInfo72 }, // Inst #2275 = OR_MMR6 |
| { 2274, 3, 1, 4, 754, 0, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, OperandInfo72 }, // Inst #2274 = OR_MM |
| { 2273, 3, 1, 4, 796, 0, 0, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, OperandInfo73 }, // Inst #2273 = ORI_MMR6 |
| { 2272, 3, 1, 4, 549, 0, 0, 0, 0x6ULL, nullptr, OperandInfo176 }, // Inst #2272 = ORI_B |
| { 2271, 3, 1, 4, 843, 0, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, OperandInfo71 }, // Inst #2271 = OR64 |
| { 2270, 3, 1, 2, 795, 0, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo181 }, // Inst #2270 = OR16_MMR6 |
| { 2269, 3, 1, 2, 754, 0, 0, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, OperandInfo181 }, // Inst #2269 = OR16_MM |
| { 2268, 3, 1, 4, 367, 0, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, OperandInfo72 }, // Inst #2268 = OR |
| { 2267, 2, 1, 2, 735, 0, 0, 0, 0x0ULL, nullptr, OperandInfo130 }, // Inst #2267 = NotRxRy16 |
| { 2266, 2, 1, 2, 735, 0, 0, 0, 0x0ULL, nullptr, OperandInfo130 }, // Inst #2266 = NegRxRy16 |
| { 2265, 2, 1, 2, 794, 0, 0, 0, 0x0ULL, nullptr, OperandInfo336 }, // Inst #2265 = NOT16_MMR6 |
| { 2264, 2, 1, 2, 753, 0, 0, 0, 0x0ULL, nullptr, OperandInfo336 }, // Inst #2264 = NOT16_MM |
| { 2263, 3, 1, 4, 548, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #2263 = NOR_V |
| { 2262, 3, 1, 4, 793, 0, 0, 0|(1ULL<<MCID::Commutable), 0x1ULL, nullptr, OperandInfo72 }, // Inst #2262 = NOR_MMR6 |
| { 2261, 3, 1, 4, 752, 0, 0, 0|(1ULL<<MCID::Commutable), 0x1ULL, nullptr, OperandInfo72 }, // Inst #2261 = NOR_MM |
| { 2260, 3, 1, 4, 549, 0, 0, 0, 0x6ULL, nullptr, OperandInfo176 }, // Inst #2260 = NORI_B |
| { 2259, 3, 1, 4, 842, 0, 0, 0|(1ULL<<MCID::Commutable), 0x1ULL, nullptr, OperandInfo71 }, // Inst #2259 = NOR64 |
| { 2258, 3, 1, 4, 366, 0, 0, 0|(1ULL<<MCID::Commutable), 0x1ULL, nullptr, OperandInfo72 }, // Inst #2258 = NOR |
| { 2257, 4, 1, 4, 1251, 0, 0, 0, 0x4ULL, nullptr, OperandInfo306 }, // Inst #2257 = NMSUB_S_MM |
| { 2256, 4, 1, 4, 684, 0, 0, 0, 0x4ULL, nullptr, OperandInfo306 }, // Inst #2256 = NMSUB_S |
| { 2255, 4, 1, 4, 683, 0, 0, 0, 0x4ULL, nullptr, OperandInfo305 }, // Inst #2255 = NMSUB_D64 |
| { 2254, 4, 1, 4, 1252, 0, 0, 0, 0x4ULL, nullptr, OperandInfo304 }, // Inst #2254 = NMSUB_D32_MM |
| { 2253, 4, 1, 4, 683, 0, 0, 0, 0x4ULL, nullptr, OperandInfo304 }, // Inst #2253 = NMSUB_D32 |
| { 2252, 4, 1, 4, 1249, 0, 0, 0, 0x4ULL, nullptr, OperandInfo306 }, // Inst #2252 = NMADD_S_MM |
| { 2251, 4, 1, 4, 682, 0, 0, 0, 0x4ULL, nullptr, OperandInfo306 }, // Inst #2251 = NMADD_S |
| { 2250, 4, 1, 4, 681, 0, 0, 0, 0x4ULL, nullptr, OperandInfo305 }, // Inst #2250 = NMADD_D64 |
| { 2249, 4, 1, 4, 1250, 0, 0, 0, 0x4ULL, nullptr, OperandInfo304 }, // Inst #2249 = NMADD_D32_MM |
| { 2248, 4, 1, 4, 681, 0, 0, 0, 0x4ULL, nullptr, OperandInfo304 }, // Inst #2248 = NMADD_D32 |
| { 2247, 2, 1, 4, 627, 0, 0, 0, 0x6ULL, nullptr, OperandInfo77 }, // Inst #2247 = NLZC_W |
| { 2246, 2, 1, 4, 627, 0, 0, 0, 0x6ULL, nullptr, OperandInfo335 }, // Inst #2246 = NLZC_H |
| { 2245, 2, 1, 4, 627, 0, 0, 0, 0x6ULL, nullptr, OperandInfo76 }, // Inst #2245 = NLZC_D |
| { 2244, 2, 1, 4, 627, 0, 0, 0, 0x6ULL, nullptr, OperandInfo312 }, // Inst #2244 = NLZC_B |
| { 2243, 2, 1, 4, 627, 0, 0, 0, 0x6ULL, nullptr, OperandInfo77 }, // Inst #2243 = NLOC_W |
| { 2242, 2, 1, 4, 627, 0, 0, 0, 0x6ULL, nullptr, OperandInfo335 }, // Inst #2242 = NLOC_H |
| { 2241, 2, 1, 4, 627, 0, 0, 0, 0x6ULL, nullptr, OperandInfo76 }, // Inst #2241 = NLOC_D |
| { 2240, 2, 1, 4, 627, 0, 0, 0, 0x6ULL, nullptr, OperandInfo312 }, // Inst #2240 = NLOC_B |
| { 2239, 2, 1, 2, 735, 0, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo334 }, // Inst #2239 = MoveR3216 |
| { 2238, 2, 1, 2, 735, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo333 }, // Inst #2238 = Move32R16 |
| { 2237, 1, 1, 2, 735, 1, 0, 0, 0x0ULL, ImplicitList25, OperandInfo272 }, // Inst #2237 = Mflo16 |
| { 2236, 1, 1, 2, 735, 1, 0, 0|(1ULL<<MCID::MoveReg), 0x0ULL, ImplicitList23, OperandInfo272 }, // Inst #2236 = Mfhi16 |
| { 2235, 3, 1, 4, 1647, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList33, OperandInfo172 }, // Inst #2235 = MUL_S_PH_MMR2 |
| { 2234, 3, 1, 4, 1483, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList33, OperandInfo172 }, // Inst #2234 = MUL_S_PH |
| { 2233, 3, 1, 4, 872, 0, 0, 0, 0x6ULL, nullptr, OperandInfo72 }, // Inst #2233 = MUL_R6 |
| { 2232, 3, 1, 4, 676, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #2232 = MUL_Q_W |
| { 2231, 3, 1, 4, 676, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #2231 = MUL_Q_H |
| { 2230, 3, 1, 4, 1646, 0, 1, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList33, OperandInfo172 }, // Inst #2230 = MUL_PH_MMR2 |
| { 2229, 3, 1, 4, 1482, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList33, OperandInfo172 }, // Inst #2229 = MUL_PH |
| { 2228, 3, 1, 4, 895, 0, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, OperandInfo72 }, // Inst #2228 = MUL_MMR6 |
| { 2227, 3, 1, 4, 884, 0, 2, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, ImplicitList6, OperandInfo72 }, // Inst #2227 = MUL_MM |
| { 2226, 3, 1, 4, 670, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #2226 = MULV_W |
| { 2225, 3, 1, 4, 670, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #2225 = MULV_H |
| { 2224, 3, 1, 4, 670, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #2224 = MULV_D |
| { 2223, 3, 1, 4, 670, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #2223 = MULV_B |
| { 2222, 3, 1, 4, 894, 0, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, OperandInfo72 }, // Inst #2222 = MULU_MMR6 |
| { 2221, 3, 1, 4, 871, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo72 }, // Inst #2221 = MULU |
| { 2220, 2, 0, 4, 879, 0, 2, 0|(1ULL<<MCID::Commutable), 0x1ULL, ImplicitList6, OperandInfo45 }, // Inst #2220 = MULTu_MM |
| { 2219, 2, 0, 4, 488, 0, 2, 0|(1ULL<<MCID::Commutable), 0x1ULL, ImplicitList6, OperandInfo45 }, // Inst #2219 = MULTu |
| { 2218, 2, 0, 4, 878, 0, 2, 0|(1ULL<<MCID::Commutable), 0x1ULL, ImplicitList6, OperandInfo45 }, // Inst #2218 = MULT_MM |
| { 2217, 3, 1, 4, 1576, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo143 }, // Inst #2217 = MULT_DSP_MM |
| { 2216, 3, 1, 4, 1410, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo143 }, // Inst #2216 = MULT_DSP |
| { 2215, 3, 1, 4, 1575, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo143 }, // Inst #2215 = MULTU_DSP_MM |
| { 2214, 3, 1, 4, 1409, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo143 }, // Inst #2214 = MULTU_DSP |
| { 2213, 2, 0, 4, 487, 0, 2, 0|(1ULL<<MCID::Commutable), 0x1ULL, ImplicitList6, OperandInfo45 }, // Inst #2213 = MULT |
| { 2212, 4, 1, 4, 1651, 0, 0, 0, 0x6ULL, nullptr, OperandInfo243 }, // Inst #2212 = MULSA_W_PH_MMR2 |
| { 2211, 4, 1, 4, 1487, 0, 0, 0, 0x6ULL, nullptr, OperandInfo243 }, // Inst #2211 = MULSA_W_PH |
| { 2210, 4, 1, 4, 1574, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList14, OperandInfo243 }, // Inst #2210 = MULSAQ_S_W_PH_MM |
| { 2209, 4, 1, 4, 1408, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList14, OperandInfo243 }, // Inst #2209 = MULSAQ_S_W_PH |
| { 2208, 3, 1, 4, 675, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #2208 = MULR_Q_W |
| { 2207, 3, 1, 4, 675, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #2207 = MULR_Q_H |
| { 2206, 3, 1, 4, 1213, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo173 }, // Inst #2206 = MULR_PS64 |
| { 2205, 3, 1, 4, 1650, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList33, OperandInfo72 }, // Inst #2205 = MULQ_S_W_MMR2 |
| { 2204, 3, 1, 4, 1486, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList33, OperandInfo72 }, // Inst #2204 = MULQ_S_W |
| { 2203, 3, 1, 4, 1649, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList33, OperandInfo172 }, // Inst #2203 = MULQ_S_PH_MMR2 |
| { 2202, 3, 1, 4, 1485, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList33, OperandInfo172 }, // Inst #2202 = MULQ_S_PH |
| { 2201, 3, 1, 4, 1648, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList33, OperandInfo72 }, // Inst #2201 = MULQ_RS_W_MMR2 |
| { 2200, 3, 1, 4, 1484, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList33, OperandInfo72 }, // Inst #2200 = MULQ_RS_W |
| { 2199, 3, 1, 4, 1573, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList33, OperandInfo172 }, // Inst #2199 = MULQ_RS_PH_MM |
| { 2198, 3, 1, 4, 1407, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList33, OperandInfo172 }, // Inst #2198 = MULQ_RS_PH |
| { 2197, 3, 1, 4, 1572, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList33, OperandInfo172 }, // Inst #2197 = MULEU_S_PH_QBR_MM |
| { 2196, 3, 1, 4, 1406, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList33, OperandInfo172 }, // Inst #2196 = MULEU_S_PH_QBR |
| { 2195, 3, 1, 4, 1571, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList33, OperandInfo172 }, // Inst #2195 = MULEU_S_PH_QBL_MM |
| { 2194, 3, 1, 4, 1405, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList33, OperandInfo172 }, // Inst #2194 = MULEU_S_PH_QBL |
| { 2193, 3, 1, 4, 1570, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList33, OperandInfo214 }, // Inst #2193 = MULEQ_S_W_PHR_MM |
| { 2192, 3, 1, 4, 1404, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList33, OperandInfo214 }, // Inst #2192 = MULEQ_S_W_PHR |
| { 2191, 3, 1, 4, 1569, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList33, OperandInfo214 }, // Inst #2191 = MULEQ_S_W_PHL_MM |
| { 2190, 3, 1, 4, 1403, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList33, OperandInfo214 }, // Inst #2190 = MULEQ_S_W_PHL |
| { 2189, 3, 1, 4, 486, 0, 2, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, ImplicitList6, OperandInfo72 }, // Inst #2189 = MUL |
| { 2188, 3, 1, 4, 893, 0, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, OperandInfo72 }, // Inst #2188 = MUH_MMR6 |
| { 2187, 3, 1, 4, 892, 0, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, OperandInfo72 }, // Inst #2187 = MUHU_MMR6 |
| { 2186, 3, 1, 4, 870, 0, 0, 0, 0x6ULL, nullptr, OperandInfo72 }, // Inst #2186 = MUHU |
| { 2185, 3, 1, 4, 869, 0, 0, 0, 0x6ULL, nullptr, OperandInfo72 }, // Inst #2185 = MUH |
| { 2184, 5, 1, 4, 1064, 0, 0, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo310 }, // Inst #2184 = MTTR |
| { 2183, 1, 0, 4, 1205, 0, 1, 0|(1ULL<<MCID::MoveReg), 0x1ULL, ImplicitList32, OperandInfo95 }, // Inst #2183 = MTP2 |
| { 2182, 1, 0, 4, 1205, 0, 1, 0|(1ULL<<MCID::MoveReg), 0x1ULL, ImplicitList31, OperandInfo95 }, // Inst #2182 = MTP1 |
| { 2181, 1, 0, 4, 1205, 0, 1, 0|(1ULL<<MCID::MoveReg), 0x1ULL, ImplicitList30, OperandInfo95 }, // Inst #2181 = MTP0 |
| { 2180, 1, 0, 4, 1205, 0, 4, 0|(1ULL<<MCID::MoveReg), 0x1ULL, ImplicitList29, OperandInfo95 }, // Inst #2180 = MTM2 |
| { 2179, 1, 0, 4, 1205, 0, 4, 0|(1ULL<<MCID::MoveReg), 0x1ULL, ImplicitList28, OperandInfo95 }, // Inst #2179 = MTM1 |
| { 2178, 1, 0, 4, 1205, 0, 4, 0|(1ULL<<MCID::MoveReg), 0x1ULL, ImplicitList27, OperandInfo95 }, // Inst #2178 = MTM0 |
| { 2177, 1, 0, 4, 890, 0, 1, 0|(1ULL<<MCID::MoveReg), 0x1ULL, ImplicitList25, OperandInfo58 }, // Inst #2177 = MTLO_MM |
| { 2176, 2, 1, 4, 1568, 0, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo332 }, // Inst #2176 = MTLO_DSP_MM |
| { 2175, 2, 1, 4, 1356, 0, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo332 }, // Inst #2175 = MTLO_DSP |
| { 2174, 1, 0, 4, 908, 0, 1, 0|(1ULL<<MCID::MoveReg), 0x1ULL, ImplicitList26, OperandInfo95 }, // Inst #2174 = MTLO64 |
| { 2173, 1, 0, 4, 493, 0, 1, 0|(1ULL<<MCID::MoveReg), 0x1ULL, ImplicitList25, OperandInfo58 }, // Inst #2173 = MTLO |
| { 2172, 3, 1, 4, 1567, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList4, OperandInfo331 }, // Inst #2172 = MTHLIP_MM |
| { 2171, 3, 1, 4, 1354, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList4, OperandInfo331 }, // Inst #2171 = MTHLIP |
| { 2170, 1, 0, 4, 890, 0, 1, 0|(1ULL<<MCID::MoveReg), 0x1ULL, ImplicitList23, OperandInfo58 }, // Inst #2170 = MTHI_MM |
| { 2169, 2, 1, 4, 1566, 0, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo330 }, // Inst #2169 = MTHI_DSP_MM |
| { 2168, 2, 1, 4, 1355, 0, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo330 }, // Inst #2168 = MTHI_DSP |
| { 2167, 1, 0, 4, 908, 0, 1, 0|(1ULL<<MCID::MoveReg), 0x1ULL, ImplicitList24, OperandInfo95 }, // Inst #2167 = MTHI64 |
| { 2166, 1, 0, 4, 493, 0, 1, 0|(1ULL<<MCID::MoveReg), 0x1ULL, ImplicitList23, OperandInfo58 }, // Inst #2166 = MTHI |
| { 2165, 3, 1, 4, 1079, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, OperandInfo128 }, // Inst #2165 = MTHGC0_MM |
| { 2164, 3, 1, 4, 424, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo128 }, // Inst #2164 = MTHGC0 |
| { 2163, 2, 1, 4, 1045, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo222 }, // Inst #2163 = MTHC2_MMR6 |
| { 2162, 3, 1, 4, 1270, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo329 }, // Inst #2162 = MTHC1_D64_MM |
| { 2161, 3, 1, 4, 687, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo329 }, // Inst #2161 = MTHC1_D64 |
| { 2160, 3, 1, 4, 1270, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo328 }, // Inst #2160 = MTHC1_D32_MM |
| { 2159, 3, 1, 4, 687, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo328 }, // Inst #2159 = MTHC1_D32 |
| { 2158, 3, 1, 4, 1043, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo128 }, // Inst #2158 = MTHC0_MMR6 |
| { 2157, 3, 1, 4, 1078, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, OperandInfo128 }, // Inst #2157 = MTGC0_MM |
| { 2156, 3, 1, 4, 423, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo128 }, // Inst #2156 = MTGC0 |
| { 2155, 2, 1, 4, 1045, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo222 }, // Inst #2155 = MTC2_MMR6 |
| { 2154, 3, 1, 4, 419, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo327 }, // Inst #2154 = MTC2 |
| { 2153, 2, 1, 4, 1313, 0, 0, 0|(1ULL<<MCID::Bitcast), 0x6ULL, nullptr, OperandInfo129 }, // Inst #2153 = MTC1_MMR6 |
| { 2152, 2, 1, 4, 1269, 0, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast), 0x4ULL, nullptr, OperandInfo129 }, // Inst #2152 = MTC1_MM |
| { 2151, 2, 1, 4, 1269, 0, 0, 0|(1ULL<<MCID::MoveReg), 0x4ULL, nullptr, OperandInfo135 }, // Inst #2151 = MTC1_D64_MM |
| { 2150, 2, 1, 4, 686, 0, 0, 0|(1ULL<<MCID::MoveReg), 0x4ULL, nullptr, OperandInfo135 }, // Inst #2150 = MTC1_D64 |
| { 2149, 2, 1, 4, 686, 0, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast), 0x4ULL, nullptr, OperandInfo129 }, // Inst #2149 = MTC1 |
| { 2148, 3, 1, 4, 1044, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo128 }, // Inst #2148 = MTC0_MMR6 |
| { 2147, 3, 1, 4, 417, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo128 }, // Inst #2147 = MTC0 |
| { 2146, 4, 1, 4, 1282, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo306 }, // Inst #2146 = MSUB_S_MM |
| { 2145, 4, 1, 4, 680, 0, 0, 0, 0x4ULL, nullptr, OperandInfo306 }, // Inst #2145 = MSUB_S |
| { 2144, 4, 1, 4, 674, 0, 0, 0, 0x6ULL, nullptr, OperandInfo60 }, // Inst #2144 = MSUB_Q_W |
| { 2143, 4, 1, 4, 674, 0, 0, 0, 0x6ULL, nullptr, OperandInfo61 }, // Inst #2143 = MSUB_Q_H |
| { 2142, 2, 0, 4, 882, 2, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList20, OperandInfo45 }, // Inst #2142 = MSUB_MM |
| { 2141, 4, 1, 4, 1565, 0, 0, 0, 0x6ULL, nullptr, OperandInfo243 }, // Inst #2141 = MSUB_DSP_MM |
| { 2140, 4, 1, 4, 1402, 0, 0, 0, 0x6ULL, nullptr, OperandInfo243 }, // Inst #2140 = MSUB_DSP |
| { 2139, 4, 1, 4, 679, 0, 0, 0, 0x4ULL, nullptr, OperandInfo305 }, // Inst #2139 = MSUB_D64 |
| { 2138, 4, 1, 4, 1283, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo304 }, // Inst #2138 = MSUB_D32_MM |
| { 2137, 4, 1, 4, 679, 0, 0, 0, 0x4ULL, nullptr, OperandInfo304 }, // Inst #2137 = MSUB_D32 |
| { 2136, 4, 1, 4, 668, 0, 0, 0, 0x6ULL, nullptr, OperandInfo60 }, // Inst #2136 = MSUBV_W |
| { 2135, 4, 1, 4, 668, 0, 0, 0, 0x6ULL, nullptr, OperandInfo61 }, // Inst #2135 = MSUBV_H |
| { 2134, 4, 1, 4, 668, 0, 0, 0, 0x6ULL, nullptr, OperandInfo59 }, // Inst #2134 = MSUBV_D |
| { 2133, 4, 1, 4, 668, 0, 0, 0, 0x6ULL, nullptr, OperandInfo196 }, // Inst #2133 = MSUBV_B |
| { 2132, 2, 0, 4, 883, 2, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList20, OperandInfo45 }, // Inst #2132 = MSUBU_MM |
| { 2131, 4, 1, 4, 1564, 0, 0, 0, 0x6ULL, nullptr, OperandInfo243 }, // Inst #2131 = MSUBU_DSP_MM |
| { 2130, 4, 1, 4, 1401, 0, 0, 0, 0x6ULL, nullptr, OperandInfo243 }, // Inst #2130 = MSUBU_DSP |
| { 2129, 2, 0, 4, 856, 2, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList20, OperandInfo45 }, // Inst #2129 = MSUBU |
| { 2128, 4, 1, 4, 673, 0, 0, 0, 0x6ULL, nullptr, OperandInfo60 }, // Inst #2128 = MSUBR_Q_W |
| { 2127, 4, 1, 4, 673, 0, 0, 0, 0x6ULL, nullptr, OperandInfo61 }, // Inst #2127 = MSUBR_Q_H |
| { 2126, 4, 1, 4, 1332, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo303 }, // Inst #2126 = MSUBF_S_MMR6 |
| { 2125, 4, 1, 4, 1235, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo303 }, // Inst #2125 = MSUBF_S |
| { 2124, 4, 1, 4, 1331, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo302 }, // Inst #2124 = MSUBF_D_MMR6 |
| { 2123, 4, 1, 4, 1237, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo302 }, // Inst #2123 = MSUBF_D |
| { 2122, 2, 0, 4, 855, 2, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList20, OperandInfo45 }, // Inst #2122 = MSUB |
| { 2121, 4, 1, 4, 1245, 0, 0, 0, 0x4ULL, nullptr, OperandInfo326 }, // Inst #2121 = MOVZ_I_S_MM |
| { 2120, 4, 1, 4, 709, 0, 0, 0, 0x4ULL, nullptr, OperandInfo326 }, // Inst #2120 = MOVZ_I_S |
| { 2119, 4, 1, 4, 1563, 0, 0, 0, 0x4ULL, nullptr, OperandInfo324 }, // Inst #2119 = MOVZ_I_MM |
| { 2118, 4, 1, 4, 911, 0, 0, 0, 0x4ULL, nullptr, OperandInfo325 }, // Inst #2118 = MOVZ_I_I64 |
| { 2117, 4, 1, 4, 483, 0, 0, 0, 0x4ULL, nullptr, OperandInfo324 }, // Inst #2117 = MOVZ_I_I |
| { 2116, 4, 1, 4, 708, 0, 0, 0, 0x4ULL, nullptr, OperandInfo323 }, // Inst #2116 = MOVZ_I_D64 |
| { 2115, 4, 1, 4, 1244, 0, 0, 0, 0x4ULL, nullptr, OperandInfo322 }, // Inst #2115 = MOVZ_I_D32_MM |
| { 2114, 4, 1, 4, 708, 0, 0, 0, 0x4ULL, nullptr, OperandInfo322 }, // Inst #2114 = MOVZ_I_D32 |
| { 2113, 4, 1, 4, 1217, 0, 0, 0, 0x4ULL, nullptr, OperandInfo321 }, // Inst #2113 = MOVZ_I64_S |
| { 2112, 4, 1, 4, 911, 0, 0, 0, 0x4ULL, nullptr, OperandInfo320 }, // Inst #2112 = MOVZ_I64_I64 |
| { 2111, 4, 1, 4, 911, 0, 0, 0, 0x4ULL, nullptr, OperandInfo319 }, // Inst #2111 = MOVZ_I64_I |
| { 2110, 4, 1, 4, 1220, 0, 0, 0, 0x4ULL, nullptr, OperandInfo318 }, // Inst #2110 = MOVZ_I64_D64 |
| { 2109, 4, 1, 4, 1243, 0, 0, 0, 0x4ULL, nullptr, OperandInfo317 }, // Inst #2109 = MOVT_S_MM |
| { 2108, 4, 1, 4, 534, 0, 0, 0, 0x4ULL, nullptr, OperandInfo317 }, // Inst #2108 = MOVT_S |
| { 2107, 4, 1, 4, 889, 0, 0, 0, 0x4ULL, nullptr, OperandInfo315 }, // Inst #2107 = MOVT_I_MM |
| { 2106, 4, 1, 4, 1215, 0, 0, 0, 0x4ULL, nullptr, OperandInfo316 }, // Inst #2106 = MOVT_I64 |
| { 2105, 4, 1, 4, 698, 0, 0, 0, 0x4ULL, nullptr, OperandInfo315 }, // Inst #2105 = MOVT_I |
| { 2104, 4, 1, 4, 533, 0, 0, 0, 0x4ULL, nullptr, OperandInfo314 }, // Inst #2104 = MOVT_D64 |
| { 2103, 4, 1, 4, 1242, 0, 0, 0, 0x4ULL, nullptr, OperandInfo313 }, // Inst #2103 = MOVT_D32_MM |
| { 2102, 4, 1, 4, 533, 0, 0, 0, 0x4ULL, nullptr, OperandInfo313 }, // Inst #2102 = MOVT_D32 |
| { 2101, 4, 1, 4, 1241, 0, 0, 0, 0x4ULL, nullptr, OperandInfo326 }, // Inst #2101 = MOVN_I_S_MM |
| { 2100, 4, 1, 4, 707, 0, 0, 0, 0x4ULL, nullptr, OperandInfo326 }, // Inst #2100 = MOVN_I_S |
| { 2099, 4, 1, 4, 1562, 0, 0, 0, 0x4ULL, nullptr, OperandInfo324 }, // Inst #2099 = MOVN_I_MM |
| { 2098, 4, 1, 4, 910, 0, 0, 0, 0x4ULL, nullptr, OperandInfo325 }, // Inst #2098 = MOVN_I_I64 |
| { 2097, 4, 1, 4, 482, 0, 0, 0, 0x4ULL, nullptr, OperandInfo324 }, // Inst #2097 = MOVN_I_I |
| { 2096, 4, 1, 4, 706, 0, 0, 0, 0x4ULL, nullptr, OperandInfo323 }, // Inst #2096 = MOVN_I_D64 |
| { 2095, 4, 1, 4, 1240, 0, 0, 0, 0x4ULL, nullptr, OperandInfo322 }, // Inst #2095 = MOVN_I_D32_MM |
| { 2094, 4, 1, 4, 706, 0, 0, 0, 0x4ULL, nullptr, OperandInfo322 }, // Inst #2094 = MOVN_I_D32 |
| { 2093, 4, 1, 4, 1219, 0, 0, 0, 0x4ULL, nullptr, OperandInfo321 }, // Inst #2093 = MOVN_I64_S |
| { 2092, 4, 1, 4, 910, 0, 0, 0, 0x4ULL, nullptr, OperandInfo320 }, // Inst #2092 = MOVN_I64_I64 |
| { 2091, 4, 1, 4, 910, 0, 0, 0, 0x4ULL, nullptr, OperandInfo319 }, // Inst #2091 = MOVN_I64_I |
| { 2090, 4, 1, 4, 1218, 0, 0, 0, 0x4ULL, nullptr, OperandInfo318 }, // Inst #2090 = MOVN_I64_D64 |
| { 2089, 4, 1, 4, 1239, 0, 0, 0, 0x4ULL, nullptr, OperandInfo317 }, // Inst #2089 = MOVF_S_MM |
| { 2088, 4, 1, 4, 532, 0, 0, 0, 0x4ULL, nullptr, OperandInfo317 }, // Inst #2088 = MOVF_S |
| { 2087, 4, 1, 4, 888, 0, 0, 0, 0x4ULL, nullptr, OperandInfo315 }, // Inst #2087 = MOVF_I_MM |
| { 2086, 4, 1, 4, 1216, 0, 0, 0, 0x4ULL, nullptr, OperandInfo316 }, // Inst #2086 = MOVF_I64 |
| { 2085, 4, 1, 4, 697, 0, 0, 0, 0x4ULL, nullptr, OperandInfo315 }, // Inst #2085 = MOVF_I |
| { 2084, 4, 1, 4, 531, 0, 0, 0, 0x4ULL, nullptr, OperandInfo314 }, // Inst #2084 = MOVF_D64 |
| { 2083, 4, 1, 4, 1238, 0, 0, 0, 0x4ULL, nullptr, OperandInfo313 }, // Inst #2083 = MOVF_D32_MM |
| { 2082, 4, 1, 4, 531, 0, 0, 0, 0x4ULL, nullptr, OperandInfo313 }, // Inst #2082 = MOVF_D32 |
| { 2081, 2, 1, 4, 546, 0, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo312 }, // Inst #2081 = MOVE_V |
| { 2080, 4, 2, 2, 1561, 0, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo311 }, // Inst #2080 = MOVEP_MMR6 |
| { 2079, 4, 2, 2, 751, 0, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo311 }, // Inst #2079 = MOVEP_MM |
| { 2078, 2, 1, 2, 792, 0, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo45 }, // Inst #2078 = MOVE16_MMR6 |
| { 2077, 2, 1, 2, 750, 0, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo45 }, // Inst #2077 = MOVE16_MM |
| { 2076, 3, 1, 4, 613, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #2076 = MOD_U_W |
| { 2075, 3, 1, 4, 613, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #2075 = MOD_U_H |
| { 2074, 3, 1, 4, 613, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #2074 = MOD_U_D |
| { 2073, 3, 1, 4, 613, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #2073 = MOD_U_B |
| { 2072, 3, 1, 4, 613, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #2072 = MOD_S_W |
| { 2071, 3, 1, 4, 613, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #2071 = MOD_S_H |
| { 2070, 3, 1, 4, 613, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #2070 = MOD_S_D |
| { 2069, 3, 1, 4, 613, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #2069 = MOD_S_B |
| { 2068, 3, 1, 4, 897, 0, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UsesCustomInserter), 0x6ULL, nullptr, OperandInfo72 }, // Inst #2068 = MOD_MMR6 |
| { 2067, 3, 1, 4, 896, 0, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UsesCustomInserter), 0x6ULL, nullptr, OperandInfo72 }, // Inst #2067 = MODU_MMR6 |
| { 2066, 3, 1, 4, 874, 0, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL, nullptr, OperandInfo72 }, // Inst #2066 = MODU |
| { 2065, 3, 1, 4, 1560, 0, 0, 0, 0x6ULL, nullptr, OperandInfo72 }, // Inst #2065 = MODSUB_MM |
| { 2064, 3, 1, 4, 1400, 0, 0, 0, 0x6ULL, nullptr, OperandInfo72 }, // Inst #2064 = MODSUB |
| { 2063, 3, 1, 4, 873, 0, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL, nullptr, OperandInfo72 }, // Inst #2063 = MOD |
| { 2062, 3, 1, 4, 618, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #2062 = MIN_U_W |
| { 2061, 3, 1, 4, 618, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #2061 = MIN_U_H |
| { 2060, 3, 1, 4, 618, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #2060 = MIN_U_D |
| { 2059, 3, 1, 4, 618, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #2059 = MIN_U_B |
| { 2058, 3, 1, 4, 617, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #2058 = MIN_S_W |
| { 2057, 3, 1, 4, 1319, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo250 }, // Inst #2057 = MIN_S_MMR6 |
| { 2056, 3, 1, 4, 617, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #2056 = MIN_S_H |
| { 2055, 3, 1, 4, 617, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #2055 = MIN_S_D |
| { 2054, 3, 1, 4, 617, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #2054 = MIN_S_B |
| { 2053, 3, 1, 4, 1225, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo250 }, // Inst #2053 = MIN_S |
| { 2052, 3, 1, 4, 1318, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo173 }, // Inst #2052 = MIN_D_MMR6 |
| { 2051, 3, 1, 4, 1226, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo173 }, // Inst #2051 = MIN_D |
| { 2050, 3, 1, 4, 619, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #2050 = MIN_A_W |
| { 2049, 3, 1, 4, 619, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #2049 = MIN_A_H |
| { 2048, 3, 1, 4, 619, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #2048 = MIN_A_D |
| { 2047, 3, 1, 4, 619, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #2047 = MIN_A_B |
| { 2046, 3, 1, 4, 620, 0, 0, 0, 0x6ULL, nullptr, OperandInfo179 }, // Inst #2046 = MINI_U_W |
| { 2045, 3, 1, 4, 620, 0, 0, 0, 0x6ULL, nullptr, OperandInfo178 }, // Inst #2045 = MINI_U_H |
| { 2044, 3, 1, 4, 620, 0, 0, 0, 0x6ULL, nullptr, OperandInfo177 }, // Inst #2044 = MINI_U_D |
| { 2043, 3, 1, 4, 620, 0, 0, 0, 0x6ULL, nullptr, OperandInfo176 }, // Inst #2043 = MINI_U_B |
| { 2042, 3, 1, 4, 620, 0, 0, 0, 0x6ULL, nullptr, OperandInfo179 }, // Inst #2042 = MINI_S_W |
| { 2041, 3, 1, 4, 620, 0, 0, 0, 0x6ULL, nullptr, OperandInfo178 }, // Inst #2041 = MINI_S_H |
| { 2040, 3, 1, 4, 620, 0, 0, 0, 0x6ULL, nullptr, OperandInfo177 }, // Inst #2040 = MINI_S_D |
| { 2039, 3, 1, 4, 620, 0, 0, 0, 0x6ULL, nullptr, OperandInfo176 }, // Inst #2039 = MINI_S_B |
| { 2038, 3, 1, 4, 1323, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo250 }, // Inst #2038 = MINA_S_MMR6 |
| { 2037, 3, 1, 4, 1226, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo250 }, // Inst #2037 = MINA_S |
| { 2036, 3, 1, 4, 1322, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo173 }, // Inst #2036 = MINA_D_MMR6 |
| { 2035, 3, 1, 4, 1225, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo173 }, // Inst #2035 = MINA_D |
| { 2034, 5, 1, 4, 1063, 0, 0, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo310 }, // Inst #2034 = MFTR |
| { 2033, 1, 1, 4, 887, 1, 0, 0|(1ULL<<MCID::MoveReg), 0x1ULL, ImplicitList21, OperandInfo58 }, // Inst #2033 = MFLO_MM |
| { 2032, 2, 1, 4, 1559, 0, 0, 0, 0x6ULL, nullptr, OperandInfo119 }, // Inst #2032 = MFLO_DSP_MM |
| { 2031, 2, 1, 4, 1399, 0, 0, 0|(1ULL<<MCID::MoveReg), 0x6ULL, nullptr, OperandInfo119 }, // Inst #2031 = MFLO_DSP |
| { 2030, 1, 1, 4, 906, 1, 0, 0|(1ULL<<MCID::MoveReg), 0x1ULL, ImplicitList22, OperandInfo95 }, // Inst #2030 = MFLO64 |
| { 2029, 1, 1, 2, 887, 1, 0, 0|(1ULL<<MCID::MoveReg), 0x0ULL, ImplicitList21, OperandInfo58 }, // Inst #2029 = MFLO16_MM |
| { 2028, 1, 1, 4, 478, 1, 0, 0|(1ULL<<MCID::MoveReg), 0x1ULL, ImplicitList21, OperandInfo58 }, // Inst #2028 = MFLO |
| { 2027, 1, 1, 4, 887, 1, 0, 0|(1ULL<<MCID::MoveReg), 0x1ULL, ImplicitList21, OperandInfo58 }, // Inst #2027 = MFHI_MM |
| { 2026, 2, 1, 4, 1558, 0, 0, 0, 0x6ULL, nullptr, OperandInfo119 }, // Inst #2026 = MFHI_DSP_MM |
| { 2025, 2, 1, 4, 1398, 0, 0, 0|(1ULL<<MCID::MoveReg), 0x6ULL, nullptr, OperandInfo119 }, // Inst #2025 = MFHI_DSP |
| { 2024, 1, 1, 4, 906, 1, 0, 0|(1ULL<<MCID::MoveReg), 0x1ULL, ImplicitList22, OperandInfo95 }, // Inst #2024 = MFHI64 |
| { 2023, 1, 1, 2, 887, 1, 0, 0|(1ULL<<MCID::MoveReg), 0x0ULL, ImplicitList21, OperandInfo58 }, // Inst #2023 = MFHI16_MM |
| { 2022, 1, 1, 4, 478, 1, 0, 0|(1ULL<<MCID::MoveReg), 0x1ULL, ImplicitList21, OperandInfo58 }, // Inst #2022 = MFHI |
| { 2021, 3, 1, 4, 1077, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, OperandInfo120 }, // Inst #2021 = MFHGC0_MM |
| { 2020, 3, 1, 4, 422, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo120 }, // Inst #2020 = MFHGC0 |
| { 2019, 2, 1, 4, 1042, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo209 }, // Inst #2019 = MFHC2_MMR6 |
| { 2018, 2, 1, 4, 1268, 0, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo307 }, // Inst #2018 = MFHC1_D64_MM |
| { 2017, 2, 1, 4, 696, 0, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo307 }, // Inst #2017 = MFHC1_D64 |
| { 2016, 2, 1, 4, 1268, 0, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo309 }, // Inst #2016 = MFHC1_D32_MM |
| { 2015, 2, 1, 4, 696, 0, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo309 }, // Inst #2015 = MFHC1_D32 |
| { 2014, 3, 1, 4, 1040, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo120 }, // Inst #2014 = MFHC0_MMR6 |
| { 2013, 3, 1, 4, 1076, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, OperandInfo120 }, // Inst #2013 = MFGC0_MM |
| { 2012, 3, 1, 4, 421, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo120 }, // Inst #2012 = MFGC0 |
| { 2011, 2, 1, 4, 1042, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo209 }, // Inst #2011 = MFC2_MMR6 |
| { 2010, 3, 1, 4, 418, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo308 }, // Inst #2010 = MFC2 |
| { 2009, 2, 1, 4, 1312, 0, 0, 0|(1ULL<<MCID::Bitcast), 0x6ULL, nullptr, OperandInfo121 }, // Inst #2009 = MFC1_MMR6 |
| { 2008, 2, 1, 4, 1267, 0, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast), 0x4ULL, nullptr, OperandInfo121 }, // Inst #2008 = MFC1_MM |
| { 2007, 2, 1, 4, 695, 0, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo307 }, // Inst #2007 = MFC1_D64 |
| { 2006, 2, 1, 4, 695, 0, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast), 0x4ULL, nullptr, OperandInfo121 }, // Inst #2006 = MFC1 |
| { 2005, 3, 1, 4, 1041, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo120 }, // Inst #2005 = MFC0_MMR6 |
| { 2004, 3, 1, 4, 416, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo120 }, // Inst #2004 = MFC0 |
| { 2003, 3, 1, 4, 618, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #2003 = MAX_U_W |
| { 2002, 3, 1, 4, 618, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #2002 = MAX_U_H |
| { 2001, 3, 1, 4, 618, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #2001 = MAX_U_D |
| { 2000, 3, 1, 4, 618, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #2000 = MAX_U_B |
| { 1999, 3, 1, 4, 617, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1999 = MAX_S_W |
| { 1998, 3, 1, 4, 1317, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo250 }, // Inst #1998 = MAX_S_MMR6 |
| { 1997, 3, 1, 4, 617, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #1997 = MAX_S_H |
| { 1996, 3, 1, 4, 617, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1996 = MAX_S_D |
| { 1995, 3, 1, 4, 617, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #1995 = MAX_S_B |
| { 1994, 3, 1, 4, 1223, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo250 }, // Inst #1994 = MAX_S |
| { 1993, 3, 1, 4, 1316, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo173 }, // Inst #1993 = MAX_D_MMR6 |
| { 1992, 3, 1, 4, 1224, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo173 }, // Inst #1992 = MAX_D |
| { 1991, 3, 1, 4, 619, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1991 = MAX_A_W |
| { 1990, 3, 1, 4, 619, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #1990 = MAX_A_H |
| { 1989, 3, 1, 4, 619, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1989 = MAX_A_D |
| { 1988, 3, 1, 4, 619, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #1988 = MAX_A_B |
| { 1987, 3, 1, 4, 620, 0, 0, 0, 0x6ULL, nullptr, OperandInfo179 }, // Inst #1987 = MAXI_U_W |
| { 1986, 3, 1, 4, 620, 0, 0, 0, 0x6ULL, nullptr, OperandInfo178 }, // Inst #1986 = MAXI_U_H |
| { 1985, 3, 1, 4, 620, 0, 0, 0, 0x6ULL, nullptr, OperandInfo177 }, // Inst #1985 = MAXI_U_D |
| { 1984, 3, 1, 4, 620, 0, 0, 0, 0x6ULL, nullptr, OperandInfo176 }, // Inst #1984 = MAXI_U_B |
| { 1983, 3, 1, 4, 620, 0, 0, 0, 0x6ULL, nullptr, OperandInfo179 }, // Inst #1983 = MAXI_S_W |
| { 1982, 3, 1, 4, 620, 0, 0, 0, 0x6ULL, nullptr, OperandInfo178 }, // Inst #1982 = MAXI_S_H |
| { 1981, 3, 1, 4, 620, 0, 0, 0, 0x6ULL, nullptr, OperandInfo177 }, // Inst #1981 = MAXI_S_D |
| { 1980, 3, 1, 4, 620, 0, 0, 0, 0x6ULL, nullptr, OperandInfo176 }, // Inst #1980 = MAXI_S_B |
| { 1979, 3, 1, 4, 1321, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo250 }, // Inst #1979 = MAXA_S_MMR6 |
| { 1978, 3, 1, 4, 1223, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo250 }, // Inst #1978 = MAXA_S |
| { 1977, 3, 1, 4, 1320, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo173 }, // Inst #1977 = MAXA_D_MMR6 |
| { 1976, 3, 1, 4, 1224, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo173 }, // Inst #1976 = MAXA_D |
| { 1975, 4, 1, 4, 1557, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList14, OperandInfo243 }, // Inst #1975 = MAQ_S_W_PHR_MM |
| { 1974, 4, 1, 4, 1397, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList14, OperandInfo243 }, // Inst #1974 = MAQ_S_W_PHR |
| { 1973, 4, 1, 4, 1556, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList14, OperandInfo243 }, // Inst #1973 = MAQ_S_W_PHL_MM |
| { 1972, 4, 1, 4, 1396, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList14, OperandInfo243 }, // Inst #1972 = MAQ_S_W_PHL |
| { 1971, 4, 1, 4, 1555, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList14, OperandInfo243 }, // Inst #1971 = MAQ_SA_W_PHR_MM |
| { 1970, 4, 1, 4, 1395, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList14, OperandInfo243 }, // Inst #1970 = MAQ_SA_W_PHR |
| { 1969, 4, 1, 4, 1554, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList14, OperandInfo243 }, // Inst #1969 = MAQ_SA_W_PHL_MM |
| { 1968, 4, 1, 4, 1394, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList14, OperandInfo243 }, // Inst #1968 = MAQ_SA_W_PHL |
| { 1967, 4, 1, 4, 1253, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo306 }, // Inst #1967 = MADD_S_MM |
| { 1966, 4, 1, 4, 678, 0, 0, 0, 0x4ULL, nullptr, OperandInfo306 }, // Inst #1966 = MADD_S |
| { 1965, 4, 1, 4, 672, 0, 0, 0, 0x6ULL, nullptr, OperandInfo60 }, // Inst #1965 = MADD_Q_W |
| { 1964, 4, 1, 4, 672, 0, 0, 0, 0x6ULL, nullptr, OperandInfo61 }, // Inst #1964 = MADD_Q_H |
| { 1963, 2, 0, 4, 880, 2, 2, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList20, OperandInfo45 }, // Inst #1963 = MADD_MM |
| { 1962, 4, 1, 4, 1553, 0, 0, 0, 0x6ULL, nullptr, OperandInfo243 }, // Inst #1962 = MADD_DSP_MM |
| { 1961, 4, 1, 4, 1393, 0, 0, 0, 0x6ULL, nullptr, OperandInfo243 }, // Inst #1961 = MADD_DSP |
| { 1960, 4, 1, 4, 677, 0, 0, 0, 0x4ULL, nullptr, OperandInfo305 }, // Inst #1960 = MADD_D64 |
| { 1959, 4, 1, 4, 1254, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo304 }, // Inst #1959 = MADD_D32_MM |
| { 1958, 4, 1, 4, 677, 0, 0, 0, 0x4ULL, nullptr, OperandInfo304 }, // Inst #1958 = MADD_D32 |
| { 1957, 4, 1, 4, 669, 0, 0, 0, 0x6ULL, nullptr, OperandInfo60 }, // Inst #1957 = MADDV_W |
| { 1956, 4, 1, 4, 669, 0, 0, 0, 0x6ULL, nullptr, OperandInfo61 }, // Inst #1956 = MADDV_H |
| { 1955, 4, 1, 4, 669, 0, 0, 0, 0x6ULL, nullptr, OperandInfo59 }, // Inst #1955 = MADDV_D |
| { 1954, 4, 1, 4, 669, 0, 0, 0, 0x6ULL, nullptr, OperandInfo196 }, // Inst #1954 = MADDV_B |
| { 1953, 2, 0, 4, 881, 2, 2, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList20, OperandInfo45 }, // Inst #1953 = MADDU_MM |
| { 1952, 4, 1, 4, 1552, 0, 0, 0, 0x6ULL, nullptr, OperandInfo243 }, // Inst #1952 = MADDU_DSP_MM |
| { 1951, 4, 1, 4, 1392, 0, 0, 0, 0x6ULL, nullptr, OperandInfo243 }, // Inst #1951 = MADDU_DSP |
| { 1950, 2, 0, 4, 854, 2, 2, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList20, OperandInfo45 }, // Inst #1950 = MADDU |
| { 1949, 4, 1, 4, 671, 0, 0, 0, 0x6ULL, nullptr, OperandInfo60 }, // Inst #1949 = MADDR_Q_W |
| { 1948, 4, 1, 4, 671, 0, 0, 0, 0x6ULL, nullptr, OperandInfo61 }, // Inst #1948 = MADDR_Q_H |
| { 1947, 4, 1, 4, 1330, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo303 }, // Inst #1947 = MADDF_S_MMR6 |
| { 1946, 4, 1, 4, 1234, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo303 }, // Inst #1946 = MADDF_S |
| { 1945, 4, 1, 4, 1329, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo302 }, // Inst #1945 = MADDF_D_MMR6 |
| { 1944, 4, 1, 4, 1236, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo302 }, // Inst #1944 = MADDF_D |
| { 1943, 2, 0, 4, 853, 2, 2, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList20, OperandInfo45 }, // Inst #1943 = MADD |
| { 1942, 3, 1, 4, 1113, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo185 }, // Inst #1942 = LwRxSpImmX16 |
| { 1941, 3, 1, 4, 1113, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo300 }, // Inst #1941 = LwRxRyOffMemX16 |
| { 1940, 3, 1, 4, 1113, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo301 }, // Inst #1940 = LwRxPcTcpX16 |
| { 1939, 3, 1, 2, 1113, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo301 }, // Inst #1939 = LwRxPcTcp16 |
| { 1938, 2, 1, 4, 735, 0, 0, 0, 0x0ULL, nullptr, OperandInfo183 }, // Inst #1938 = LiRxImmX16 |
| { 1937, 2, 1, 4, 735, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo183 }, // Inst #1937 = LiRxImmAlignX16 |
| { 1936, 2, 1, 2, 735, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo183 }, // Inst #1936 = LiRxImm16 |
| { 1935, 3, 1, 4, 1112, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo300 }, // Inst #1935 = LhuRxRyOffMemX16 |
| { 1934, 3, 1, 4, 1111, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo300 }, // Inst #1934 = LhRxRyOffMemX16 |
| { 1933, 3, 1, 4, 1110, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo300 }, // Inst #1933 = LbuRxRyOffMemX16 |
| { 1932, 3, 1, 4, 1109, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo300 }, // Inst #1932 = LbRxRyOffMemX16 |
| { 1931, 3, 1, 4, 1165, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, OperandInfo113 }, // Inst #1931 = LWu |
| { 1930, 3, 1, 4, 1152, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, OperandInfo96 }, // Inst #1930 = LW_MMR6 |
| { 1929, 3, 1, 4, 1123, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, OperandInfo96 }, // Inst #1929 = LW_MM |
| { 1928, 3, 1, 4, 1551, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, OperandInfo274 }, // Inst #1928 = LWX_MM |
| { 1927, 3, 1, 4, 1129, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, nullptr, OperandInfo274 }, // Inst #1927 = LWXS_MM |
| { 1926, 3, 1, 4, 1299, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, OperandInfo299 }, // Inst #1926 = LWXC1_MM |
| { 1925, 3, 1, 4, 713, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, OperandInfo299 }, // Inst #1925 = LWXC1 |
| { 1924, 3, 1, 4, 1391, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, OperandInfo274 }, // Inst #1924 = LWX |
| { 1923, 3, 1, 4, 1128, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, OperandInfo96 }, // Inst #1923 = LWU_MM |
| { 1922, 2, 1, 4, 1184, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo114 }, // Inst #1922 = LWUPC |
| { 1921, 3, 1, 2, 1123, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo298 }, // Inst #1921 = LWSP_MM |
| { 1920, 4, 1, 4, 1127, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, OperandInfo295 }, // Inst #1920 = LWR_MM |
| { 1919, 4, 1, 4, 1097, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, OperandInfo295 }, // Inst #1919 = LWRE_MM |
| { 1918, 4, 1, 4, 451, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo295 }, // Inst #1918 = LWRE |
| { 1917, 4, 1, 4, 1172, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, OperandInfo283 }, // Inst #1917 = LWR64 |
| { 1916, 4, 1, 4, 449, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, OperandInfo295 }, // Inst #1916 = LWR |
| { 1915, 4, 2, 4, 1126, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo297 }, // Inst #1915 = LWP_MM |
| { 1914, 2, 1, 4, 1151, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo114 }, // Inst #1914 = LWPC_MMR6 |
| { 1913, 2, 1, 4, 447, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo114 }, // Inst #1913 = LWPC |
| { 1912, 3, 1, 4, 1125, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo110 }, // Inst #1912 = LWM32_MM |
| { 1911, 3, 1, 2, 1149, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo296 }, // Inst #1911 = LWM16_MMR6 |
| { 1910, 3, 1, 2, 1125, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo296 }, // Inst #1910 = LWM16_MM |
| { 1909, 4, 1, 4, 1124, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, OperandInfo295 }, // Inst #1909 = LWL_MM |
| { 1908, 4, 1, 4, 1096, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, OperandInfo295 }, // Inst #1908 = LWLE_MM |
| { 1907, 4, 1, 4, 450, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo295 }, // Inst #1907 = LWLE |
| { 1906, 4, 1, 4, 1171, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, OperandInfo283 }, // Inst #1906 = LWL64 |
| { 1905, 4, 1, 4, 448, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, OperandInfo295 }, // Inst #1905 = LWL |
| { 1904, 3, 1, 2, 1123, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo294 }, // Inst #1904 = LWGP_MM |
| { 1903, 3, 1, 4, 1095, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo96 }, // Inst #1903 = LWE_MM |
| { 1902, 3, 1, 4, 445, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo96 }, // Inst #1902 = LWE |
| { 1901, 3, 1, 4, 1506, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo293 }, // Inst #1901 = LWDSP_MM |
| { 1900, 3, 1, 4, 1343, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo293 }, // Inst #1900 = LWDSP |
| { 1899, 3, 1, 4, 438, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, OperandInfo278 }, // Inst #1899 = LWC3 |
| { 1898, 3, 1, 4, 1083, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo276 }, // Inst #1898 = LWC2_R6 |
| { 1897, 3, 1, 4, 1150, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, OperandInfo277 }, // Inst #1897 = LWC2_MMR6 |
| { 1896, 3, 1, 4, 437, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, OperandInfo276 }, // Inst #1896 = LWC2 |
| { 1895, 3, 1, 4, 1298, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, OperandInfo292 }, // Inst #1895 = LWC1_MM |
| { 1894, 3, 1, 4, 712, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, OperandInfo292 }, // Inst #1894 = LWC1 |
| { 1893, 3, 1, 4, 1170, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, OperandInfo113 }, // Inst #1893 = LW64 |
| { 1892, 3, 1, 2, 1123, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, OperandInfo273 }, // Inst #1892 = LW16_MM |
| { 1891, 3, 1, 4, 435, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, OperandInfo96 }, // Inst #1891 = LW |
| { 1890, 2, 1, 4, 749, 0, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2ULL, nullptr, OperandInfo114 }, // Inst #1890 = LUi_MM |
| { 1889, 2, 1, 4, 841, 0, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2ULL, nullptr, OperandInfo112 }, // Inst #1889 = LUi64 |
| { 1888, 2, 1, 4, 365, 0, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2ULL, nullptr, OperandInfo114 }, // Inst #1888 = LUi |
| { 1887, 3, 1, 4, 1297, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, nullptr, OperandInfo285 }, // Inst #1887 = LUXC1_MM |
| { 1886, 3, 1, 4, 714, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, nullptr, OperandInfo285 }, // Inst #1886 = LUXC164 |
| { 1885, 3, 1, 4, 714, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, nullptr, OperandInfo284 }, // Inst #1885 = LUXC1 |
| { 1884, 2, 1, 4, 791, 0, 0, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, OperandInfo114 }, // Inst #1884 = LUI_MMR6 |
| { 1883, 4, 1, 4, 733, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo180 }, // Inst #1883 = LSA_R6 |
| { 1882, 4, 1, 4, 790, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo180 }, // Inst #1882 = LSA_MMR6 |
| { 1881, 4, 1, 4, 513, 0, 0, 0, 0x6ULL, nullptr, OperandInfo180 }, // Inst #1881 = LSA |
| { 1880, 3, 1, 4, 1082, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo290 }, // Inst #1880 = LL_R6 |
| { 1879, 3, 1, 4, 1148, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo96 }, // Inst #1879 = LL_MMR6 |
| { 1878, 3, 1, 4, 1122, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo96 }, // Inst #1878 = LL_MM |
| { 1877, 3, 1, 4, 1098, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo96 }, // Inst #1877 = LLE_MM |
| { 1876, 3, 1, 4, 446, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo96 }, // Inst #1876 = LLE |
| { 1875, 3, 1, 4, 1186, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo291 }, // Inst #1875 = LLD_R6 |
| { 1874, 3, 1, 4, 1164, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo113 }, // Inst #1874 = LLD |
| { 1873, 3, 1, 4, 1187, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo290 }, // Inst #1873 = LL64_R6 |
| { 1872, 3, 1, 4, 1164, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo96 }, // Inst #1872 = LL64 |
| { 1871, 3, 1, 4, 436, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo96 }, // Inst #1871 = LL |
| { 1870, 2, 1, 2, 789, 0, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, OperandInfo169 }, // Inst #1870 = LI16_MMR6 |
| { 1869, 2, 1, 2, 748, 0, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, OperandInfo169 }, // Inst #1869 = LI16_MM |
| { 1868, 3, 1, 4, 1120, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, OperandInfo96 }, // Inst #1868 = LHu_MM |
| { 1867, 3, 1, 4, 1094, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo96 }, // Inst #1867 = LHuE_MM |
| { 1866, 3, 1, 4, 444, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo96 }, // Inst #1866 = LHuE |
| { 1865, 3, 1, 4, 1169, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, OperandInfo113 }, // Inst #1865 = LHu64 |
| { 1864, 3, 1, 4, 434, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, OperandInfo96 }, // Inst #1864 = LHu |
| { 1863, 3, 1, 4, 1121, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, OperandInfo96 }, // Inst #1863 = LH_MM |
| { 1862, 3, 1, 4, 1550, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, OperandInfo274 }, // Inst #1862 = LHX_MM |
| { 1861, 3, 1, 4, 1390, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, OperandInfo274 }, // Inst #1861 = LHX |
| { 1860, 3, 1, 2, 1120, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo273 }, // Inst #1860 = LHU16_MM |
| { 1859, 3, 1, 4, 1093, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo96 }, // Inst #1859 = LHE_MM |
| { 1858, 3, 1, 4, 443, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo96 }, // Inst #1858 = LHE |
| { 1857, 3, 1, 4, 1168, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, OperandInfo113 }, // Inst #1857 = LH64 |
| { 1856, 3, 1, 4, 433, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, OperandInfo96 }, // Inst #1856 = LH |
| { 1855, 3, 1, 4, 738, 0, 0, 0, 0x2ULL, nullptr, OperandInfo96 }, // Inst #1855 = LEA_ADDiu_MM |
| { 1854, 3, 1, 4, 840, 0, 0, 0, 0x2ULL, nullptr, OperandInfo113 }, // Inst #1854 = LEA_ADDiu64 |
| { 1853, 3, 1, 4, 724, 0, 0, 0, 0x2ULL, nullptr, OperandInfo96 }, // Inst #1853 = LEA_ADDiu |
| { 1852, 3, 1, 4, 715, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, OperandInfo289 }, // Inst #1852 = LD_W |
| { 1851, 3, 1, 4, 715, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, OperandInfo288 }, // Inst #1851 = LD_H |
| { 1850, 3, 1, 4, 715, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, OperandInfo287 }, // Inst #1850 = LD_D |
| { 1849, 3, 1, 4, 715, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, OperandInfo286 }, // Inst #1849 = LD_B |
| { 1848, 3, 1, 4, 711, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, OperandInfo285 }, // Inst #1848 = LDXC164 |
| { 1847, 3, 1, 4, 711, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, OperandInfo284 }, // Inst #1847 = LDXC1 |
| { 1846, 4, 1, 4, 1174, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, OperandInfo283 }, // Inst #1846 = LDR |
| { 1845, 2, 1, 4, 1185, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo112 }, // Inst #1845 = LDPC |
| { 1844, 4, 1, 4, 1173, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, OperandInfo283 }, // Inst #1844 = LDL |
| { 1843, 2, 1, 4, 547, 0, 0, 0|(1ULL<<MCID::Rematerializable), 0x6ULL, nullptr, OperandInfo282 }, // Inst #1843 = LDI_W |
| { 1842, 2, 1, 4, 547, 0, 0, 0|(1ULL<<MCID::Rematerializable), 0x6ULL, nullptr, OperandInfo281 }, // Inst #1842 = LDI_H |
| { 1841, 2, 1, 4, 547, 0, 0, 0|(1ULL<<MCID::Rematerializable), 0x6ULL, nullptr, OperandInfo280 }, // Inst #1841 = LDI_D |
| { 1840, 2, 1, 4, 547, 0, 0, 0|(1ULL<<MCID::Rematerializable), 0x6ULL, nullptr, OperandInfo279 }, // Inst #1840 = LDI_B |
| { 1839, 3, 1, 4, 440, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, OperandInfo278 }, // Inst #1839 = LDC3 |
| { 1838, 3, 1, 4, 1081, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo276 }, // Inst #1838 = LDC2_R6 |
| { 1837, 3, 1, 4, 1147, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, OperandInfo277 }, // Inst #1837 = LDC2_MMR6 |
| { 1836, 3, 1, 4, 439, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, OperandInfo276 }, // Inst #1836 = LDC2 |
| { 1835, 3, 1, 4, 1296, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, OperandInfo275 }, // Inst #1835 = LDC1_MM_D64 |
| { 1834, 3, 1, 4, 1296, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, OperandInfo158 }, // Inst #1834 = LDC1_MM_D32 |
| { 1833, 3, 1, 4, 1339, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, OperandInfo275 }, // Inst #1833 = LDC1_D64_MMR6 |
| { 1832, 3, 1, 4, 710, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, OperandInfo275 }, // Inst #1832 = LDC164 |
| { 1831, 3, 1, 4, 710, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, OperandInfo158 }, // Inst #1831 = LDC1 |
| { 1830, 3, 1, 4, 1163, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, OperandInfo113 }, // Inst #1830 = LD |
| { 1829, 3, 1, 4, 1118, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, OperandInfo96 }, // Inst #1829 = LBu_MM |
| { 1828, 3, 1, 4, 1092, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo96 }, // Inst #1828 = LBuE_MM |
| { 1827, 3, 1, 4, 442, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo96 }, // Inst #1827 = LBuE |
| { 1826, 3, 1, 4, 1167, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, OperandInfo113 }, // Inst #1826 = LBu64 |
| { 1825, 3, 1, 4, 432, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, OperandInfo96 }, // Inst #1825 = LBu |
| { 1824, 3, 1, 4, 1146, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo96 }, // Inst #1824 = LB_MMR6 |
| { 1823, 3, 1, 4, 1119, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, OperandInfo96 }, // Inst #1823 = LB_MM |
| { 1822, 3, 1, 4, 1145, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo96 }, // Inst #1822 = LBU_MMR6 |
| { 1821, 3, 1, 4, 1549, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, OperandInfo274 }, // Inst #1821 = LBUX_MM |
| { 1820, 3, 1, 4, 1389, 0, 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, OperandInfo274 }, // Inst #1820 = LBUX |
| { 1819, 3, 1, 2, 1118, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo273 }, // Inst #1819 = LBU16_MM |
| { 1818, 3, 1, 4, 1091, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo96 }, // Inst #1818 = LBE_MM |
| { 1817, 3, 1, 4, 441, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo96 }, // Inst #1817 = LBE |
| { 1816, 3, 1, 4, 1166, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, OperandInfo113 }, // Inst #1816 = LB64 |
| { 1815, 3, 1, 4, 431, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, OperandInfo96 }, // Inst #1815 = LB |
| { 1814, 1, 0, 2, 942, 0, 1, 0|(1ULL<<MCID::Call), 0x0ULL, ImplicitList3, OperandInfo272 }, // Inst #1814 = JumpLinkReg16 |
| { 1813, 1, 0, 2, 939, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, OperandInfo272 }, // Inst #1813 = JrcRx16 |
| { 1812, 0, 0, 2, 939, 0, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #1812 = JrcRa16 |
| { 1811, 0, 0, 2, 939, 0, 0, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #1811 = JrRa16 |
| { 1810, 1, 0, 6, 941, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList3, OperandInfo2 }, // Inst #1810 = JalB16 |
| { 1809, 1, 0, 6, 941, 0, 1, 0|(1ULL<<MCID::Call), 0x0ULL, ImplicitList3, OperandInfo2 }, // Inst #1809 = Jal16 |
| { 1808, 1, 0, 4, 955, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x13ULL, ImplicitList2, OperandInfo2 }, // Inst #1808 = J_MM |
| { 1807, 1, 0, 4, 954, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x11ULL, nullptr, OperandInfo58 }, // Inst #1807 = JR_MM |
| { 1806, 1, 0, 4, 934, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo58 }, // Inst #1806 = JR_HB_R6 |
| { 1805, 1, 0, 4, 1022, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo95 }, // Inst #1805 = JR_HB64_R6 |
| { 1804, 1, 0, 4, 1014, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x13ULL, nullptr, OperandInfo95 }, // Inst #1804 = JR_HB64 |
| { 1803, 1, 0, 4, 386, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x13ULL, nullptr, OperandInfo58 }, // Inst #1803 = JR_HB |
| { 1802, 1, 0, 2, 993, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo2 }, // Inst #1802 = JRCADDIUSP_MMR6 |
| { 1801, 1, 0, 2, 995, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo58 }, // Inst #1801 = JRC16_MMR6 |
| { 1800, 1, 0, 2, 994, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo58 }, // Inst #1800 = JRC16_MM |
| { 1799, 1, 0, 2, 993, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo2 }, // Inst #1799 = JRADDIUSP |
| { 1798, 1, 0, 4, 1011, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x11ULL, nullptr, OperandInfo95 }, // Inst #1798 = JR64 |
| { 1797, 1, 0, 2, 954, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo58 }, // Inst #1797 = JR16_MM |
| { 1796, 1, 0, 4, 923, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x11ULL, nullptr, OperandInfo58 }, // Inst #1796 = JR |
| { 1795, 2, 0, 4, 992, 0, 1, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList2, OperandInfo114 }, // Inst #1795 = JIC_MMR6 |
| { 1794, 2, 0, 4, 1019, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, ImplicitList2, OperandInfo112 }, // Inst #1794 = JIC64 |
| { 1793, 2, 0, 4, 933, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, ImplicitList2, OperandInfo114 }, // Inst #1793 = JIC |
| { 1792, 2, 0, 4, 1004, 0, 1, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList3, OperandInfo114 }, // Inst #1792 = JIALC_MMR6 |
| { 1791, 2, 0, 4, 1021, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, ImplicitList3, OperandInfo112 }, // Inst #1791 = JIALC64 |
| { 1790, 2, 0, 4, 928, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, ImplicitList3, OperandInfo114 }, // Inst #1790 = JIALC |
| { 1789, 1, 0, 4, 962, 0, 1, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call), 0x13ULL, ImplicitList3, OperandInfo2 }, // Inst #1789 = JAL_MM |
| { 1788, 1, 0, 4, 962, 0, 1, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call), 0x13ULL, ImplicitList3, OperandInfo2 }, // Inst #1788 = JALX_MM |
| { 1787, 1, 0, 4, 409, 0, 1, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call), 0x13ULL, ImplicitList3, OperandInfo2 }, // Inst #1787 = JALX |
| { 1786, 1, 0, 4, 961, 0, 1, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x3ULL, ImplicitList3, OperandInfo2 }, // Inst #1786 = JALS_MM |
| { 1785, 2, 1, 4, 959, 0, 1, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x11ULL, ImplicitList3, OperandInfo45 }, // Inst #1785 = JALR_MM |
| { 1784, 2, 1, 4, 1013, 0, 0, 0|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x13ULL, nullptr, OperandInfo122 }, // Inst #1784 = JALR_HB64 |
| { 1783, 2, 1, 4, 408, 0, 0, 0|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x13ULL, nullptr, OperandInfo45 }, // Inst #1783 = JALR_HB |
| { 1782, 2, 1, 4, 960, 0, 1, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList3, OperandInfo45 }, // Inst #1782 = JALRS_MM |
| { 1781, 1, 0, 2, 960, 0, 1, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList3, OperandInfo58 }, // Inst #1781 = JALRS16_MM |
| { 1780, 2, 1, 4, 1003, 0, 1, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList3, OperandInfo45 }, // Inst #1780 = JALRC_MMR6 |
| { 1779, 2, 1, 4, 1002, 0, 0, 0|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::UnmodeledSideEffects), 0x3ULL, nullptr, OperandInfo45 }, // Inst #1779 = JALRC_HB_MMR6 |
| { 1778, 1, 0, 2, 1001, 0, 1, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, ImplicitList3, OperandInfo58 }, // Inst #1778 = JALRC16_MMR6 |
| { 1777, 2, 1, 4, 1012, 0, 1, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x11ULL, ImplicitList3, OperandInfo122 }, // Inst #1777 = JALR64 |
| { 1776, 1, 0, 2, 959, 0, 1, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, ImplicitList3, OperandInfo58 }, // Inst #1776 = JALR16_MM |
| { 1775, 2, 1, 4, 407, 0, 1, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x11ULL, ImplicitList3, OperandInfo45 }, // Inst #1775 = JALR |
| { 1774, 1, 0, 4, 406, 0, 1, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call), 0x13ULL, ImplicitList3, OperandInfo2 }, // Inst #1774 = JAL |
| { 1773, 1, 0, 4, 922, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x13ULL, ImplicitList2, OperandInfo2 }, // Inst #1773 = J |
| { 1772, 5, 1, 4, 788, 0, 0, 0, 0x1ULL, nullptr, OperandInfo262 }, // Inst #1772 = INS_MMR6 |
| { 1771, 5, 1, 4, 747, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, OperandInfo262 }, // Inst #1771 = INS_MM |
| { 1770, 3, 1, 4, 1548, 2, 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL, ImplicitList19, OperandInfo267 }, // Inst #1770 = INSV_MM |
| { 1769, 5, 1, 4, 607, 0, 0, 0, 0x6ULL, nullptr, OperandInfo271 }, // Inst #1769 = INSVE_W |
| { 1768, 5, 1, 4, 607, 0, 0, 0, 0x6ULL, nullptr, OperandInfo270 }, // Inst #1768 = INSVE_H |
| { 1767, 5, 1, 4, 607, 0, 0, 0, 0x6ULL, nullptr, OperandInfo269 }, // Inst #1767 = INSVE_D |
| { 1766, 5, 1, 4, 607, 0, 0, 0, 0x6ULL, nullptr, OperandInfo268 }, // Inst #1766 = INSVE_B |
| { 1765, 3, 1, 4, 1353, 2, 0, 0|(1ULL<<MCID::MayLoad), 0x6ULL, ImplicitList19, OperandInfo267 }, // Inst #1765 = INSV |
| { 1764, 4, 1, 4, 518, 0, 0, 0, 0x6ULL, nullptr, OperandInfo266 }, // Inst #1764 = INSERT_W |
| { 1763, 4, 1, 4, 518, 0, 0, 0, 0x6ULL, nullptr, OperandInfo265 }, // Inst #1763 = INSERT_H |
| { 1762, 4, 1, 4, 518, 0, 0, 0, 0x6ULL, nullptr, OperandInfo264 }, // Inst #1762 = INSERT_D |
| { 1761, 4, 1, 4, 518, 0, 0, 0, 0x6ULL, nullptr, OperandInfo263 }, // Inst #1761 = INSERT_B |
| { 1760, 5, 1, 4, 495, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, OperandInfo262 }, // Inst #1760 = INS |
| { 1759, 3, 1, 4, 605, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1759 = ILVR_W |
| { 1758, 3, 1, 4, 605, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #1758 = ILVR_H |
| { 1757, 3, 1, 4, 605, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1757 = ILVR_D |
| { 1756, 3, 1, 4, 605, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #1756 = ILVR_B |
| { 1755, 3, 1, 4, 606, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1755 = ILVOD_W |
| { 1754, 3, 1, 4, 606, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #1754 = ILVOD_H |
| { 1753, 3, 1, 4, 606, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1753 = ILVOD_D |
| { 1752, 3, 1, 4, 606, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #1752 = ILVOD_B |
| { 1751, 3, 1, 4, 605, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1751 = ILVL_W |
| { 1750, 3, 1, 4, 605, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #1750 = ILVL_H |
| { 1749, 3, 1, 4, 605, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1749 = ILVL_D |
| { 1748, 3, 1, 4, 605, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #1748 = ILVL_B |
| { 1747, 3, 1, 4, 606, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1747 = ILVEV_W |
| { 1746, 3, 1, 4, 606, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #1746 = ILVEV_H |
| { 1745, 3, 1, 4, 606, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1745 = ILVEV_D |
| { 1744, 3, 1, 4, 606, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #1744 = ILVEV_B |
| { 1743, 1, 0, 4, 1069, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo2 }, // Inst #1743 = HYPCALL_MM |
| { 1742, 1, 0, 4, 420, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo2 }, // Inst #1742 = HYPCALL |
| { 1741, 3, 1, 4, 616, 0, 0, 0, 0x6ULL, nullptr, OperandInfo239 }, // Inst #1741 = HSUB_U_W |
| { 1740, 3, 1, 4, 616, 0, 0, 0, 0x6ULL, nullptr, OperandInfo238 }, // Inst #1740 = HSUB_U_H |
| { 1739, 3, 1, 4, 616, 0, 0, 0, 0x6ULL, nullptr, OperandInfo237 }, // Inst #1739 = HSUB_U_D |
| { 1738, 3, 1, 4, 616, 0, 0, 0, 0x6ULL, nullptr, OperandInfo239 }, // Inst #1738 = HSUB_S_W |
| { 1737, 3, 1, 4, 616, 0, 0, 0, 0x6ULL, nullptr, OperandInfo238 }, // Inst #1737 = HSUB_S_H |
| { 1736, 3, 1, 4, 616, 0, 0, 0, 0x6ULL, nullptr, OperandInfo237 }, // Inst #1736 = HSUB_S_D |
| { 1735, 3, 1, 4, 615, 0, 0, 0, 0x6ULL, nullptr, OperandInfo239 }, // Inst #1735 = HADD_U_W |
| { 1734, 3, 1, 4, 615, 0, 0, 0, 0x6ULL, nullptr, OperandInfo238 }, // Inst #1734 = HADD_U_H |
| { 1733, 3, 1, 4, 615, 0, 0, 0, 0x6ULL, nullptr, OperandInfo237 }, // Inst #1733 = HADD_U_D |
| { 1732, 3, 1, 4, 615, 0, 0, 0, 0x6ULL, nullptr, OperandInfo239 }, // Inst #1732 = HADD_S_W |
| { 1731, 3, 1, 4, 615, 0, 0, 0, 0x6ULL, nullptr, OperandInfo238 }, // Inst #1731 = HADD_S_H |
| { 1730, 3, 1, 4, 615, 0, 0, 0, 0x6ULL, nullptr, OperandInfo237 }, // Inst #1730 = HADD_S_D |
| { 1729, 2, 0, 4, 1144, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo114 }, // Inst #1729 = GINVT_MMR6 |
| { 1728, 2, 0, 4, 1090, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo114 }, // Inst #1728 = GINVT |
| { 1727, 1, 0, 4, 1143, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo58 }, // Inst #1727 = GINVI_MMR6 |
| { 1726, 1, 0, 4, 1089, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo58 }, // Inst #1726 = GINVI |
| { 1725, 2, 1, 4, 595, 0, 0, 0, 0x6ULL, nullptr, OperandInfo77 }, // Inst #1725 = FTRUNC_U_W |
| { 1724, 2, 1, 4, 595, 0, 0, 0, 0x6ULL, nullptr, OperandInfo76 }, // Inst #1724 = FTRUNC_U_D |
| { 1723, 2, 1, 4, 595, 0, 0, 0, 0x6ULL, nullptr, OperandInfo77 }, // Inst #1723 = FTRUNC_S_W |
| { 1722, 2, 1, 4, 595, 0, 0, 0, 0x6ULL, nullptr, OperandInfo76 }, // Inst #1722 = FTRUNC_S_D |
| { 1721, 3, 1, 4, 594, 0, 0, 0, 0x6ULL, nullptr, OperandInfo255 }, // Inst #1721 = FTQ_W |
| { 1720, 3, 1, 4, 594, 0, 0, 0, 0x6ULL, nullptr, OperandInfo254 }, // Inst #1720 = FTQ_H |
| { 1719, 2, 1, 4, 592, 0, 0, 0, 0x6ULL, nullptr, OperandInfo77 }, // Inst #1719 = FTINT_U_W |
| { 1718, 2, 1, 4, 592, 0, 0, 0, 0x6ULL, nullptr, OperandInfo76 }, // Inst #1718 = FTINT_U_D |
| { 1717, 2, 1, 4, 592, 0, 0, 0, 0x6ULL, nullptr, OperandInfo77 }, // Inst #1717 = FTINT_S_W |
| { 1716, 2, 1, 4, 592, 0, 0, 0, 0x6ULL, nullptr, OperandInfo76 }, // Inst #1716 = FTINT_S_D |
| { 1715, 3, 1, 4, 576, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1715 = FSUN_W |
| { 1714, 3, 1, 4, 576, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1714 = FSUN_D |
| { 1713, 3, 1, 4, 575, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1713 = FSUNE_W |
| { 1712, 3, 1, 4, 575, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1712 = FSUNE_D |
| { 1711, 3, 1, 4, 574, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1711 = FSULT_W |
| { 1710, 3, 1, 4, 574, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1710 = FSULT_D |
| { 1709, 3, 1, 4, 573, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1709 = FSULE_W |
| { 1708, 3, 1, 4, 573, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1708 = FSULE_D |
| { 1707, 3, 1, 4, 572, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1707 = FSUEQ_W |
| { 1706, 3, 1, 4, 572, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1706 = FSUEQ_D |
| { 1705, 3, 1, 4, 664, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1705 = FSUB_W |
| { 1704, 3, 1, 4, 1335, 0, 0, 0, 0x6ULL, nullptr, OperandInfo250 }, // Inst #1704 = FSUB_S_MMR6 |
| { 1703, 3, 1, 4, 1281, 0, 0, 0, 0x4ULL, nullptr, OperandInfo250 }, // Inst #1703 = FSUB_S_MM |
| { 1702, 3, 1, 4, 636, 0, 0, 0, 0x4ULL, nullptr, OperandInfo250 }, // Inst #1702 = FSUB_S |
| { 1701, 3, 1, 4, 635, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo173 }, // Inst #1701 = FSUB_PS64 |
| { 1700, 3, 1, 4, 1280, 0, 0, 0, 0x4ULL, nullptr, OperandInfo173 }, // Inst #1700 = FSUB_D64_MM |
| { 1699, 3, 1, 4, 634, 0, 0, 0, 0x4ULL, nullptr, OperandInfo173 }, // Inst #1699 = FSUB_D64 |
| { 1698, 3, 1, 4, 1280, 0, 0, 0, 0x4ULL, nullptr, OperandInfo249 }, // Inst #1698 = FSUB_D32_MM |
| { 1697, 3, 1, 4, 634, 0, 0, 0, 0x4ULL, nullptr, OperandInfo249 }, // Inst #1697 = FSUB_D32 |
| { 1696, 3, 1, 4, 664, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1696 = FSUB_D |
| { 1695, 2, 1, 4, 660, 0, 0, 0, 0x6ULL, nullptr, OperandInfo77 }, // Inst #1695 = FSQRT_W |
| { 1694, 2, 1, 4, 1286, 0, 0, 0, 0x4ULL, nullptr, OperandInfo207 }, // Inst #1694 = FSQRT_S_MM |
| { 1693, 2, 1, 4, 648, 0, 0, 0, 0x4ULL, nullptr, OperandInfo207 }, // Inst #1693 = FSQRT_S |
| { 1692, 2, 1, 4, 1287, 0, 0, 0, 0x4ULL, nullptr, OperandInfo203 }, // Inst #1692 = FSQRT_D64_MM |
| { 1691, 2, 1, 4, 649, 0, 0, 0, 0x4ULL, nullptr, OperandInfo203 }, // Inst #1691 = FSQRT_D64 |
| { 1690, 2, 1, 4, 1287, 0, 0, 0, 0x4ULL, nullptr, OperandInfo248 }, // Inst #1690 = FSQRT_D32_MM |
| { 1689, 2, 1, 4, 649, 0, 0, 0, 0x4ULL, nullptr, OperandInfo248 }, // Inst #1689 = FSQRT_D32 |
| { 1688, 2, 1, 4, 661, 0, 0, 0, 0x6ULL, nullptr, OperandInfo76 }, // Inst #1688 = FSQRT_D |
| { 1687, 3, 1, 4, 571, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1687 = FSOR_W |
| { 1686, 3, 1, 4, 571, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1686 = FSOR_D |
| { 1685, 3, 1, 4, 571, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1685 = FSNE_W |
| { 1684, 3, 1, 4, 571, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1684 = FSNE_D |
| { 1683, 3, 1, 4, 571, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1683 = FSLT_W |
| { 1682, 3, 1, 4, 571, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1682 = FSLT_D |
| { 1681, 3, 1, 4, 571, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1681 = FSLE_W |
| { 1680, 3, 1, 4, 571, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1680 = FSLE_D |
| { 1679, 3, 1, 4, 571, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1679 = FSEQ_W |
| { 1678, 3, 1, 4, 571, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1678 = FSEQ_D |
| { 1677, 3, 1, 4, 571, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1677 = FSAF_W |
| { 1676, 3, 1, 4, 571, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1676 = FSAF_D |
| { 1675, 2, 1, 4, 651, 0, 0, 0, 0x6ULL, nullptr, OperandInfo77 }, // Inst #1675 = FRSQRT_W |
| { 1674, 2, 1, 4, 651, 0, 0, 0, 0x6ULL, nullptr, OperandInfo76 }, // Inst #1674 = FRSQRT_D |
| { 1673, 2, 1, 4, 593, 0, 0, 0, 0x6ULL, nullptr, OperandInfo77 }, // Inst #1673 = FRINT_W |
| { 1672, 2, 1, 4, 593, 0, 0, 0, 0x6ULL, nullptr, OperandInfo76 }, // Inst #1672 = FRINT_D |
| { 1671, 2, 1, 4, 650, 0, 0, 0, 0x6ULL, nullptr, OperandInfo77 }, // Inst #1671 = FRCP_W |
| { 1670, 2, 1, 4, 650, 0, 0, 0, 0x6ULL, nullptr, OperandInfo76 }, // Inst #1670 = FRCP_D |
| { 1669, 3, 2, 4, 1066, 0, 0, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo72 }, // Inst #1669 = FORK |
| { 1668, 2, 1, 4, 1300, 0, 0, 0, 0x4ULL, nullptr, OperandInfo207 }, // Inst #1668 = FNEG_S_MMR6 |
| { 1667, 2, 1, 4, 1273, 0, 0, 0, 0x4ULL, nullptr, OperandInfo207 }, // Inst #1667 = FNEG_S_MM |
| { 1666, 2, 1, 4, 537, 0, 0, 0, 0x4ULL, nullptr, OperandInfo207 }, // Inst #1666 = FNEG_S |
| { 1665, 2, 1, 4, 1273, 0, 0, 0, 0x4ULL, nullptr, OperandInfo203 }, // Inst #1665 = FNEG_D64_MM |
| { 1664, 2, 1, 4, 537, 0, 0, 0, 0x4ULL, nullptr, OperandInfo203 }, // Inst #1664 = FNEG_D64 |
| { 1663, 2, 1, 4, 1273, 0, 0, 0, 0x4ULL, nullptr, OperandInfo248 }, // Inst #1663 = FNEG_D32_MM |
| { 1662, 2, 1, 4, 537, 0, 0, 0, 0x4ULL, nullptr, OperandInfo248 }, // Inst #1662 = FNEG_D32 |
| { 1661, 3, 1, 4, 662, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1661 = FMUL_W |
| { 1660, 3, 1, 4, 1334, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo250 }, // Inst #1660 = FMUL_S_MMR6 |
| { 1659, 3, 1, 4, 1279, 0, 0, 0|(1ULL<<MCID::Commutable), 0x4ULL, nullptr, OperandInfo250 }, // Inst #1659 = FMUL_S_MM |
| { 1658, 3, 1, 4, 633, 0, 0, 0|(1ULL<<MCID::Commutable), 0x4ULL, nullptr, OperandInfo250 }, // Inst #1658 = FMUL_S |
| { 1657, 3, 1, 4, 632, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo173 }, // Inst #1657 = FMUL_PS64 |
| { 1656, 3, 1, 4, 1278, 0, 0, 0|(1ULL<<MCID::Commutable), 0x4ULL, nullptr, OperandInfo173 }, // Inst #1656 = FMUL_D64_MM |
| { 1655, 3, 1, 4, 631, 0, 0, 0|(1ULL<<MCID::Commutable), 0x4ULL, nullptr, OperandInfo173 }, // Inst #1655 = FMUL_D64 |
| { 1654, 3, 1, 4, 1278, 0, 0, 0|(1ULL<<MCID::Commutable), 0x4ULL, nullptr, OperandInfo249 }, // Inst #1654 = FMUL_D32_MM |
| { 1653, 3, 1, 4, 631, 0, 0, 0|(1ULL<<MCID::Commutable), 0x4ULL, nullptr, OperandInfo249 }, // Inst #1653 = FMUL_D32 |
| { 1652, 3, 1, 4, 662, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1652 = FMUL_D |
| { 1651, 4, 1, 4, 657, 0, 0, 0, 0x6ULL, nullptr, OperandInfo60 }, // Inst #1651 = FMSUB_W |
| { 1650, 4, 1, 4, 657, 0, 0, 0, 0x6ULL, nullptr, OperandInfo59 }, // Inst #1650 = FMSUB_D |
| { 1649, 2, 1, 4, 1333, 0, 0, 0, 0x4ULL, nullptr, OperandInfo207 }, // Inst #1649 = FMOV_S_MMR6 |
| { 1648, 2, 1, 4, 1277, 0, 0, 0|(1ULL<<MCID::MoveReg), 0x4ULL, nullptr, OperandInfo207 }, // Inst #1648 = FMOV_S_MM |
| { 1647, 2, 1, 4, 536, 0, 0, 0|(1ULL<<MCID::MoveReg), 0x4ULL, nullptr, OperandInfo207 }, // Inst #1647 = FMOV_S |
| { 1646, 2, 1, 4, 1336, 0, 0, 0, 0x4ULL, nullptr, OperandInfo203 }, // Inst #1646 = FMOV_D_MMR6 |
| { 1645, 2, 1, 4, 1276, 0, 0, 0, 0x4ULL, nullptr, OperandInfo203 }, // Inst #1645 = FMOV_D64_MM |
| { 1644, 2, 1, 4, 535, 0, 0, 0|(1ULL<<MCID::MoveReg), 0x4ULL, nullptr, OperandInfo203 }, // Inst #1644 = FMOV_D64 |
| { 1643, 2, 1, 4, 1276, 0, 0, 0, 0x4ULL, nullptr, OperandInfo248 }, // Inst #1643 = FMOV_D32_MM |
| { 1642, 2, 1, 4, 535, 0, 0, 0|(1ULL<<MCID::MoveReg), 0x4ULL, nullptr, OperandInfo248 }, // Inst #1642 = FMOV_D32 |
| { 1641, 3, 1, 4, 603, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1641 = FMIN_W |
| { 1640, 3, 1, 4, 603, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1640 = FMIN_D |
| { 1639, 3, 1, 4, 602, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1639 = FMIN_A_W |
| { 1638, 3, 1, 4, 602, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1638 = FMIN_A_D |
| { 1637, 3, 1, 4, 601, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1637 = FMAX_W |
| { 1636, 3, 1, 4, 601, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1636 = FMAX_D |
| { 1635, 3, 1, 4, 600, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1635 = FMAX_A_W |
| { 1634, 3, 1, 4, 600, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1634 = FMAX_A_D |
| { 1633, 4, 1, 4, 656, 0, 0, 0, 0x6ULL, nullptr, OperandInfo60 }, // Inst #1633 = FMADD_W |
| { 1632, 4, 1, 4, 656, 0, 0, 0, 0x6ULL, nullptr, OperandInfo59 }, // Inst #1632 = FMADD_D |
| { 1631, 2, 1, 4, 1310, 0, 0, 0, 0x4ULL, nullptr, OperandInfo207 }, // Inst #1631 = FLOOR_W_S_MMR6 |
| { 1630, 2, 1, 4, 1248, 0, 0, 0, 0x4ULL, nullptr, OperandInfo207 }, // Inst #1630 = FLOOR_W_S_MM |
| { 1629, 2, 1, 4, 718, 0, 0, 0, 0x4ULL, nullptr, OperandInfo207 }, // Inst #1629 = FLOOR_W_S |
| { 1628, 2, 1, 4, 1248, 0, 0, 0, 0x4ULL, nullptr, OperandInfo205 }, // Inst #1628 = FLOOR_W_MM |
| { 1627, 2, 1, 4, 1310, 0, 0, 0, 0x4ULL, nullptr, OperandInfo205 }, // Inst #1627 = FLOOR_W_D_MMR6 |
| { 1626, 2, 1, 4, 718, 0, 0, 0, 0x4ULL, nullptr, OperandInfo206 }, // Inst #1626 = FLOOR_W_D64 |
| { 1625, 2, 1, 4, 718, 0, 0, 0, 0x4ULL, nullptr, OperandInfo205 }, // Inst #1625 = FLOOR_W_D32 |
| { 1624, 2, 1, 4, 1310, 0, 0, 0, 0x4ULL, nullptr, OperandInfo204 }, // Inst #1624 = FLOOR_L_S_MMR6 |
| { 1623, 2, 1, 4, 718, 0, 0, 0, 0x4ULL, nullptr, OperandInfo204 }, // Inst #1623 = FLOOR_L_S |
| { 1622, 2, 1, 4, 1310, 0, 0, 0, 0x4ULL, nullptr, OperandInfo203 }, // Inst #1622 = FLOOR_L_D_MMR6 |
| { 1621, 2, 1, 4, 718, 0, 0, 0, 0x4ULL, nullptr, OperandInfo203 }, // Inst #1621 = FLOOR_L_D64 |
| { 1620, 2, 1, 4, 604, 0, 0, 0, 0x6ULL, nullptr, OperandInfo77 }, // Inst #1620 = FLOG2_W |
| { 1619, 2, 1, 4, 604, 0, 0, 0, 0x6ULL, nullptr, OperandInfo76 }, // Inst #1619 = FLOG2_D |
| { 1618, 2, 1, 4, 544, 0, 0, 0, 0x6ULL, nullptr, OperandInfo261 }, // Inst #1618 = FILL_W |
| { 1617, 2, 1, 4, 544, 0, 0, 0, 0x6ULL, nullptr, OperandInfo260 }, // Inst #1617 = FILL_H |
| { 1616, 2, 1, 4, 544, 0, 0, 0, 0x6ULL, nullptr, OperandInfo259 }, // Inst #1616 = FILL_D |
| { 1615, 2, 1, 4, 544, 0, 0, 0, 0x6ULL, nullptr, OperandInfo258 }, // Inst #1615 = FILL_B |
| { 1614, 2, 1, 4, 591, 0, 0, 0, 0x6ULL, nullptr, OperandInfo257 }, // Inst #1614 = FFQR_W |
| { 1613, 2, 1, 4, 591, 0, 0, 0, 0x6ULL, nullptr, OperandInfo256 }, // Inst #1613 = FFQR_D |
| { 1612, 2, 1, 4, 590, 0, 0, 0, 0x6ULL, nullptr, OperandInfo257 }, // Inst #1612 = FFQL_W |
| { 1611, 2, 1, 4, 590, 0, 0, 0, 0x6ULL, nullptr, OperandInfo256 }, // Inst #1611 = FFQL_D |
| { 1610, 2, 1, 4, 589, 0, 0, 0, 0x6ULL, nullptr, OperandInfo77 }, // Inst #1610 = FFINT_U_W |
| { 1609, 2, 1, 4, 589, 0, 0, 0, 0x6ULL, nullptr, OperandInfo76 }, // Inst #1609 = FFINT_U_D |
| { 1608, 2, 1, 4, 589, 0, 0, 0, 0x6ULL, nullptr, OperandInfo77 }, // Inst #1608 = FFINT_S_W |
| { 1607, 2, 1, 4, 589, 0, 0, 0, 0x6ULL, nullptr, OperandInfo76 }, // Inst #1607 = FFINT_S_D |
| { 1606, 2, 1, 4, 598, 0, 0, 0, 0x6ULL, nullptr, OperandInfo257 }, // Inst #1606 = FEXUPR_W |
| { 1605, 2, 1, 4, 598, 0, 0, 0, 0x6ULL, nullptr, OperandInfo256 }, // Inst #1605 = FEXUPR_D |
| { 1604, 2, 1, 4, 597, 0, 0, 0, 0x6ULL, nullptr, OperandInfo257 }, // Inst #1604 = FEXUPL_W |
| { 1603, 2, 1, 4, 597, 0, 0, 0, 0x6ULL, nullptr, OperandInfo256 }, // Inst #1603 = FEXUPL_D |
| { 1602, 3, 1, 4, 553, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1602 = FEXP2_W |
| { 1601, 3, 1, 4, 553, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1601 = FEXP2_D |
| { 1600, 3, 1, 4, 596, 0, 0, 0, 0x6ULL, nullptr, OperandInfo255 }, // Inst #1600 = FEXDO_W |
| { 1599, 3, 1, 4, 596, 0, 0, 0, 0x6ULL, nullptr, OperandInfo254 }, // Inst #1599 = FEXDO_H |
| { 1598, 3, 1, 4, 658, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1598 = FDIV_W |
| { 1597, 3, 1, 4, 1337, 0, 0, 0, 0x6ULL, nullptr, OperandInfo250 }, // Inst #1597 = FDIV_S_MMR6 |
| { 1596, 3, 1, 4, 1284, 0, 0, 0, 0x4ULL, nullptr, OperandInfo250 }, // Inst #1596 = FDIV_S_MM |
| { 1595, 3, 1, 4, 646, 0, 0, 0, 0x4ULL, nullptr, OperandInfo250 }, // Inst #1595 = FDIV_S |
| { 1594, 3, 1, 4, 1285, 0, 0, 0, 0x4ULL, nullptr, OperandInfo173 }, // Inst #1594 = FDIV_D64_MM |
| { 1593, 3, 1, 4, 647, 0, 0, 0, 0x4ULL, nullptr, OperandInfo173 }, // Inst #1593 = FDIV_D64 |
| { 1592, 3, 1, 4, 1285, 0, 0, 0, 0x4ULL, nullptr, OperandInfo249 }, // Inst #1592 = FDIV_D32_MM |
| { 1591, 3, 1, 4, 647, 0, 0, 0, 0x4ULL, nullptr, OperandInfo249 }, // Inst #1591 = FDIV_D32 |
| { 1590, 3, 1, 4, 659, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1590 = FDIV_D |
| { 1589, 3, 1, 4, 587, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo48 }, // Inst #1589 = FCUN_W |
| { 1588, 3, 1, 4, 587, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo46 }, // Inst #1588 = FCUN_D |
| { 1587, 3, 1, 4, 586, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo48 }, // Inst #1587 = FCUNE_W |
| { 1586, 3, 1, 4, 586, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo46 }, // Inst #1586 = FCUNE_D |
| { 1585, 3, 1, 4, 585, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo48 }, // Inst #1585 = FCULT_W |
| { 1584, 3, 1, 4, 585, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo46 }, // Inst #1584 = FCULT_D |
| { 1583, 3, 1, 4, 584, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo48 }, // Inst #1583 = FCULE_W |
| { 1582, 3, 1, 4, 584, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo46 }, // Inst #1582 = FCULE_D |
| { 1581, 3, 1, 4, 583, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo48 }, // Inst #1581 = FCUEQ_W |
| { 1580, 3, 1, 4, 583, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo46 }, // Inst #1580 = FCUEQ_D |
| { 1579, 3, 1, 4, 582, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo48 }, // Inst #1579 = FCOR_W |
| { 1578, 3, 1, 4, 582, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo46 }, // Inst #1578 = FCOR_D |
| { 1577, 3, 1, 4, 581, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo48 }, // Inst #1577 = FCNE_W |
| { 1576, 3, 1, 4, 581, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo46 }, // Inst #1576 = FCNE_D |
| { 1575, 3, 0, 4, 1265, 0, 1, 0, 0x44ULL, ImplicitList18, OperandInfo253 }, // Inst #1575 = FCMP_S32_MM |
| { 1574, 3, 0, 4, 643, 0, 1, 0, 0x44ULL, ImplicitList18, OperandInfo253 }, // Inst #1574 = FCMP_S32 |
| { 1573, 3, 0, 4, 642, 0, 1, 0, 0x44ULL, ImplicitList18, OperandInfo252 }, // Inst #1573 = FCMP_D64 |
| { 1572, 3, 0, 4, 1266, 0, 1, 0, 0x44ULL, ImplicitList18, OperandInfo251 }, // Inst #1572 = FCMP_D32_MM |
| { 1571, 3, 0, 4, 642, 0, 1, 0, 0x44ULL, ImplicitList18, OperandInfo251 }, // Inst #1571 = FCMP_D32 |
| { 1570, 3, 1, 4, 580, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1570 = FCLT_W |
| { 1569, 3, 1, 4, 580, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1569 = FCLT_D |
| { 1568, 3, 1, 4, 579, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1568 = FCLE_W |
| { 1567, 3, 1, 4, 579, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1567 = FCLE_D |
| { 1566, 2, 1, 4, 599, 0, 0, 0, 0x6ULL, nullptr, OperandInfo77 }, // Inst #1566 = FCLASS_W |
| { 1565, 2, 1, 4, 599, 0, 0, 0, 0x6ULL, nullptr, OperandInfo76 }, // Inst #1565 = FCLASS_D |
| { 1564, 3, 1, 4, 578, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo48 }, // Inst #1564 = FCEQ_W |
| { 1563, 3, 1, 4, 578, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo46 }, // Inst #1563 = FCEQ_D |
| { 1562, 3, 1, 4, 577, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo48 }, // Inst #1562 = FCAF_W |
| { 1561, 3, 1, 4, 577, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo46 }, // Inst #1561 = FCAF_D |
| { 1560, 3, 1, 4, 663, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo48 }, // Inst #1560 = FADD_W |
| { 1559, 3, 1, 4, 1315, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo250 }, // Inst #1559 = FADD_S_MMR6 |
| { 1558, 3, 1, 4, 1275, 0, 0, 0|(1ULL<<MCID::Commutable), 0x4ULL, nullptr, OperandInfo250 }, // Inst #1558 = FADD_S_MM |
| { 1557, 3, 1, 4, 630, 0, 0, 0|(1ULL<<MCID::Commutable), 0x4ULL, nullptr, OperandInfo250 }, // Inst #1557 = FADD_S |
| { 1556, 3, 1, 4, 629, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo173 }, // Inst #1556 = FADD_PS64 |
| { 1555, 3, 1, 4, 1274, 0, 0, 0|(1ULL<<MCID::Commutable), 0x4ULL, nullptr, OperandInfo173 }, // Inst #1555 = FADD_D64_MM |
| { 1554, 3, 1, 4, 628, 0, 0, 0|(1ULL<<MCID::Commutable), 0x4ULL, nullptr, OperandInfo173 }, // Inst #1554 = FADD_D64 |
| { 1553, 3, 1, 4, 1274, 0, 0, 0|(1ULL<<MCID::Commutable), 0x4ULL, nullptr, OperandInfo249 }, // Inst #1553 = FADD_D32_MM |
| { 1552, 3, 1, 4, 628, 0, 0, 0|(1ULL<<MCID::Commutable), 0x4ULL, nullptr, OperandInfo249 }, // Inst #1552 = FADD_D32 |
| { 1551, 3, 1, 4, 663, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo46 }, // Inst #1551 = FADD_D |
| { 1550, 2, 1, 4, 1272, 0, 0, 0, 0x4ULL, nullptr, OperandInfo207 }, // Inst #1550 = FABS_S_MM |
| { 1549, 2, 1, 4, 530, 0, 0, 0, 0x4ULL, nullptr, OperandInfo207 }, // Inst #1549 = FABS_S |
| { 1548, 2, 1, 4, 1271, 0, 0, 0, 0x4ULL, nullptr, OperandInfo203 }, // Inst #1548 = FABS_D64_MM |
| { 1547, 2, 1, 4, 530, 0, 0, 0, 0x4ULL, nullptr, OperandInfo203 }, // Inst #1547 = FABS_D64 |
| { 1546, 2, 1, 4, 1271, 0, 0, 0, 0x4ULL, nullptr, OperandInfo248 }, // Inst #1546 = FABS_D32_MM |
| { 1545, 2, 1, 4, 530, 0, 0, 0, 0x4ULL, nullptr, OperandInfo248 }, // Inst #1545 = FABS_D32 |
| { 1544, 4, 1, 4, 787, 0, 0, 0, 0x1ULL, nullptr, OperandInfo213 }, // Inst #1544 = EXT_MMR6 |
| { 1543, 4, 1, 4, 746, 0, 0, 0, 0x1ULL, nullptr, OperandInfo213 }, // Inst #1543 = EXT_MM |
| { 1542, 4, 1, 4, 1204, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, OperandInfo211 }, // Inst #1542 = EXTS32 |
| { 1541, 4, 1, 4, 1204, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, OperandInfo211 }, // Inst #1541 = EXTS |
| { 1540, 3, 1, 4, 1547, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList17, OperandInfo246 }, // Inst #1540 = EXTR_W_MM |
| { 1539, 3, 1, 4, 1352, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList17, OperandInfo246 }, // Inst #1539 = EXTR_W |
| { 1538, 3, 1, 4, 1546, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList17, OperandInfo246 }, // Inst #1538 = EXTR_S_H_MM |
| { 1537, 3, 1, 4, 1351, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList17, OperandInfo246 }, // Inst #1537 = EXTR_S_H |
| { 1536, 3, 1, 4, 1545, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList17, OperandInfo246 }, // Inst #1536 = EXTR_R_W_MM |
| { 1535, 3, 1, 4, 1350, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList17, OperandInfo246 }, // Inst #1535 = EXTR_R_W |
| { 1534, 3, 1, 4, 1544, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList17, OperandInfo246 }, // Inst #1534 = EXTR_RS_W_MM |
| { 1533, 3, 1, 4, 1349, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList17, OperandInfo246 }, // Inst #1533 = EXTR_RS_W |
| { 1532, 3, 1, 4, 1543, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList17, OperandInfo247 }, // Inst #1532 = EXTRV_W_MM |
| { 1531, 3, 1, 4, 1348, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList17, OperandInfo247 }, // Inst #1531 = EXTRV_W |
| { 1530, 3, 1, 4, 1542, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList17, OperandInfo247 }, // Inst #1530 = EXTRV_S_H_MM |
| { 1529, 3, 1, 4, 1347, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList17, OperandInfo247 }, // Inst #1529 = EXTRV_S_H |
| { 1528, 3, 1, 4, 1541, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList17, OperandInfo247 }, // Inst #1528 = EXTRV_R_W_MM |
| { 1527, 3, 1, 4, 1346, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList17, OperandInfo247 }, // Inst #1527 = EXTRV_R_W |
| { 1526, 3, 1, 4, 1540, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList17, OperandInfo247 }, // Inst #1526 = EXTRV_RS_W_MM |
| { 1525, 3, 1, 4, 1345, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList17, OperandInfo247 }, // Inst #1525 = EXTRV_RS_W |
| { 1524, 3, 1, 4, 1539, 1, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList15, OperandInfo246 }, // Inst #1524 = EXTP_MM |
| { 1523, 3, 1, 4, 1538, 1, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList15, OperandInfo247 }, // Inst #1523 = EXTPV_MM |
| { 1522, 3, 1, 4, 1387, 1, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList15, OperandInfo247 }, // Inst #1522 = EXTPV |
| { 1521, 3, 1, 4, 1537, 1, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList16, OperandInfo246 }, // Inst #1521 = EXTPDP_MM |
| { 1520, 3, 1, 4, 1536, 1, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList16, OperandInfo247 }, // Inst #1520 = EXTPDPV_MM |
| { 1519, 3, 1, 4, 1385, 1, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList16, OperandInfo247 }, // Inst #1519 = EXTPDPV |
| { 1518, 3, 1, 4, 1386, 1, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList16, OperandInfo246 }, // Inst #1518 = EXTPDP |
| { 1517, 3, 1, 4, 1388, 1, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList15, OperandInfo246 }, // Inst #1517 = EXTP |
| { 1516, 4, 1, 4, 494, 0, 0, 0, 0x1ULL, nullptr, OperandInfo213 }, // Inst #1516 = EXT |
| { 1515, 1, 1, 4, 1046, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo58 }, // Inst #1515 = EVP_MMR6 |
| { 1514, 1, 1, 4, 1062, 0, 0, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo58 }, // Inst #1514 = EVPE |
| { 1513, 1, 1, 4, 1025, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo58 }, // Inst #1513 = EVP |
| { 1512, 0, 0, 4, 991, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr }, // Inst #1512 = ERET_MMR6 |
| { 1511, 0, 0, 4, 953, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr }, // Inst #1511 = ERET_MM |
| { 1510, 0, 0, 4, 989, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr }, // Inst #1510 = ERETNC_MMR6 |
| { 1509, 0, 0, 4, 383, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr }, // Inst #1509 = ERETNC |
| { 1508, 0, 0, 4, 381, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr }, // Inst #1508 = ERET |
| { 1507, 1, 1, 4, 1061, 0, 0, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo58 }, // Inst #1507 = EMT |
| { 1506, 1, 1, 4, 1049, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo58 }, // Inst #1506 = EI_MMR6 |
| { 1505, 1, 1, 4, 1032, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo58 }, // Inst #1505 = EI_MM |
| { 1504, 1, 1, 4, 477, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo58 }, // Inst #1504 = EI |
| { 1503, 0, 0, 4, 1050, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr }, // Inst #1503 = EHB_MMR6 |
| { 1502, 0, 0, 4, 1033, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr }, // Inst #1502 = EHB_MM |
| { 1501, 0, 0, 4, 479, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr }, // Inst #1501 = EHB |
| { 1500, 2, 0, 2, 877, 0, 2, 0, 0x0ULL, ImplicitList6, OperandInfo130 }, // Inst #1500 = DivuRxRy16 |
| { 1499, 2, 0, 2, 876, 0, 2, 0, 0x0ULL, ImplicitList6, OperandInfo130 }, // Inst #1499 = DivRxRy16 |
| { 1498, 1, 1, 4, 1047, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo58 }, // Inst #1498 = DVP_MMR6 |
| { 1497, 1, 1, 4, 1060, 0, 0, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo58 }, // Inst #1497 = DVPE |
| { 1496, 1, 1, 4, 1026, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo58 }, // Inst #1496 = DVP |
| { 1495, 2, 0, 4, 905, 0, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList13, OperandInfo122 }, // Inst #1495 = DUDIV |
| { 1494, 3, 1, 4, 839, 0, 0, 0|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, OperandInfo71 }, // Inst #1494 = DSUBu |
| { 1493, 3, 1, 4, 838, 0, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, OperandInfo71 }, // Inst #1493 = DSUB |
| { 1492, 3, 1, 4, 837, 0, 0, 0, 0x1ULL, nullptr, OperandInfo244 }, // Inst #1492 = DSRLV |
| { 1491, 3, 1, 4, 836, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, OperandInfo70 }, // Inst #1491 = DSRL32 |
| { 1490, 3, 1, 4, 835, 0, 0, 0, 0x1ULL, nullptr, OperandInfo70 }, // Inst #1490 = DSRL |
| { 1489, 3, 1, 4, 834, 0, 0, 0, 0x1ULL, nullptr, OperandInfo244 }, // Inst #1489 = DSRAV |
| { 1488, 3, 1, 4, 833, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, OperandInfo70 }, // Inst #1488 = DSRA32 |
| { 1487, 3, 1, 4, 832, 0, 0, 0, 0x1ULL, nullptr, OperandInfo70 }, // Inst #1487 = DSRA |
| { 1486, 3, 1, 4, 831, 0, 0, 0, 0x1ULL, nullptr, OperandInfo244 }, // Inst #1486 = DSLLV |
| { 1485, 2, 1, 4, 808, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, OperandInfo245 }, // Inst #1485 = DSLL64_32 |
| { 1484, 3, 1, 4, 830, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, OperandInfo70 }, // Inst #1484 = DSLL32 |
| { 1483, 3, 1, 4, 829, 0, 0, 0, 0x1ULL, nullptr, OperandInfo70 }, // Inst #1483 = DSLL |
| { 1482, 2, 1, 4, 828, 0, 0, 0, 0x1ULL, nullptr, OperandInfo122 }, // Inst #1482 = DSHD |
| { 1481, 2, 0, 4, 904, 0, 2, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList13, OperandInfo122 }, // Inst #1481 = DSDIV |
| { 1480, 2, 1, 4, 827, 0, 0, 0, 0x1ULL, nullptr, OperandInfo122 }, // Inst #1480 = DSBH |
| { 1479, 3, 1, 4, 826, 0, 0, 0, 0x1ULL, nullptr, OperandInfo244 }, // Inst #1479 = DROTRV |
| { 1478, 3, 1, 4, 825, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, OperandInfo70 }, // Inst #1478 = DROTR32 |
| { 1477, 3, 1, 4, 824, 0, 0, 0, 0x1ULL, nullptr, OperandInfo70 }, // Inst #1477 = DROTR |
| { 1476, 4, 1, 4, 1642, 0, 0, 0, 0x6ULL, nullptr, OperandInfo243 }, // Inst #1476 = DPS_W_PH_MMR2 |
| { 1475, 4, 1, 4, 1478, 0, 0, 0, 0x6ULL, nullptr, OperandInfo243 }, // Inst #1475 = DPS_W_PH |
| { 1474, 4, 1, 4, 1645, 0, 0, 0, 0x6ULL, nullptr, OperandInfo243 }, // Inst #1474 = DPSX_W_PH_MMR2 |
| { 1473, 4, 1, 4, 1481, 0, 0, 0, 0x6ULL, nullptr, OperandInfo243 }, // Inst #1473 = DPSX_W_PH |
| { 1472, 4, 1, 4, 1535, 0, 0, 0, 0x6ULL, nullptr, OperandInfo243 }, // Inst #1472 = DPSU_H_QBR_MM |
| { 1471, 4, 1, 4, 1384, 0, 0, 0, 0x6ULL, nullptr, OperandInfo243 }, // Inst #1471 = DPSU_H_QBR |
| { 1470, 4, 1, 4, 1534, 0, 0, 0, 0x6ULL, nullptr, OperandInfo243 }, // Inst #1470 = DPSU_H_QBL_MM |
| { 1469, 4, 1, 4, 1383, 0, 0, 0, 0x6ULL, nullptr, OperandInfo243 }, // Inst #1469 = DPSU_H_QBL |
| { 1468, 4, 1, 4, 666, 0, 0, 0, 0x6ULL, nullptr, OperandInfo242 }, // Inst #1468 = DPSUB_U_W |
| { 1467, 4, 1, 4, 666, 0, 0, 0, 0x6ULL, nullptr, OperandInfo241 }, // Inst #1467 = DPSUB_U_H |
| { 1466, 4, 1, 4, 666, 0, 0, 0, 0x6ULL, nullptr, OperandInfo240 }, // Inst #1466 = DPSUB_U_D |
| { 1465, 4, 1, 4, 666, 0, 0, 0, 0x6ULL, nullptr, OperandInfo242 }, // Inst #1465 = DPSUB_S_W |
| { 1464, 4, 1, 4, 666, 0, 0, 0, 0x6ULL, nullptr, OperandInfo241 }, // Inst #1464 = DPSUB_S_H |
| { 1463, 4, 1, 4, 666, 0, 0, 0, 0x6ULL, nullptr, OperandInfo240 }, // Inst #1463 = DPSUB_S_D |
| { 1462, 4, 1, 4, 1533, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList14, OperandInfo243 }, // Inst #1462 = DPSQ_S_W_PH_MM |
| { 1461, 4, 1, 4, 1382, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList14, OperandInfo243 }, // Inst #1461 = DPSQ_S_W_PH |
| { 1460, 4, 1, 4, 1532, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList14, OperandInfo243 }, // Inst #1460 = DPSQ_SA_L_W_MM |
| { 1459, 4, 1, 4, 1381, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList14, OperandInfo243 }, // Inst #1459 = DPSQ_SA_L_W |
| { 1458, 4, 1, 4, 1643, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList14, OperandInfo243 }, // Inst #1458 = DPSQX_S_W_PH_MMR2 |
| { 1457, 4, 1, 4, 1479, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList14, OperandInfo243 }, // Inst #1457 = DPSQX_S_W_PH |
| { 1456, 4, 1, 4, 1644, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList14, OperandInfo243 }, // Inst #1456 = DPSQX_SA_W_PH_MMR2 |
| { 1455, 4, 1, 4, 1480, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList14, OperandInfo243 }, // Inst #1455 = DPSQX_SA_W_PH |
| { 1454, 2, 1, 4, 1203, 0, 0, 0, 0x1ULL, nullptr, OperandInfo122 }, // Inst #1454 = DPOP |
| { 1453, 4, 1, 4, 1638, 0, 0, 0, 0x6ULL, nullptr, OperandInfo243 }, // Inst #1453 = DPA_W_PH_MMR2 |
| { 1452, 4, 1, 4, 1474, 0, 0, 0, 0x6ULL, nullptr, OperandInfo243 }, // Inst #1452 = DPA_W_PH |
| { 1451, 4, 1, 4, 1641, 0, 0, 0, 0x6ULL, nullptr, OperandInfo243 }, // Inst #1451 = DPAX_W_PH_MMR2 |
| { 1450, 4, 1, 4, 1477, 0, 0, 0, 0x6ULL, nullptr, OperandInfo243 }, // Inst #1450 = DPAX_W_PH |
| { 1449, 4, 1, 4, 1531, 0, 0, 0, 0x6ULL, nullptr, OperandInfo243 }, // Inst #1449 = DPAU_H_QBR_MM |
| { 1448, 4, 1, 4, 1380, 0, 0, 0, 0x6ULL, nullptr, OperandInfo243 }, // Inst #1448 = DPAU_H_QBR |
| { 1447, 4, 1, 4, 1530, 0, 0, 0, 0x6ULL, nullptr, OperandInfo243 }, // Inst #1447 = DPAU_H_QBL_MM |
| { 1446, 4, 1, 4, 1379, 0, 0, 0, 0x6ULL, nullptr, OperandInfo243 }, // Inst #1446 = DPAU_H_QBL |
| { 1445, 4, 1, 4, 1529, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList14, OperandInfo243 }, // Inst #1445 = DPAQ_S_W_PH_MM |
| { 1444, 4, 1, 4, 1378, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList14, OperandInfo243 }, // Inst #1444 = DPAQ_S_W_PH |
| { 1443, 4, 1, 4, 1528, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList14, OperandInfo243 }, // Inst #1443 = DPAQ_SA_L_W_MM |
| { 1442, 4, 1, 4, 1377, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList14, OperandInfo243 }, // Inst #1442 = DPAQ_SA_L_W |
| { 1441, 4, 1, 4, 1640, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList14, OperandInfo243 }, // Inst #1441 = DPAQX_S_W_PH_MMR2 |
| { 1440, 4, 1, 4, 1476, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList14, OperandInfo243 }, // Inst #1440 = DPAQX_S_W_PH |
| { 1439, 4, 1, 4, 1639, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList14, OperandInfo243 }, // Inst #1439 = DPAQX_SA_W_PH_MMR2 |
| { 1438, 4, 1, 4, 1475, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList14, OperandInfo243 }, // Inst #1438 = DPAQX_SA_W_PH |
| { 1437, 4, 1, 4, 665, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo242 }, // Inst #1437 = DPADD_U_W |
| { 1436, 4, 1, 4, 665, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo241 }, // Inst #1436 = DPADD_U_H |
| { 1435, 4, 1, 4, 665, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo240 }, // Inst #1435 = DPADD_U_D |
| { 1434, 4, 1, 4, 665, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo242 }, // Inst #1434 = DPADD_S_W |
| { 1433, 4, 1, 4, 665, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo241 }, // Inst #1433 = DPADD_S_H |
| { 1432, 4, 1, 4, 665, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo240 }, // Inst #1432 = DPADD_S_D |
| { 1431, 3, 1, 4, 667, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo239 }, // Inst #1431 = DOTP_U_W |
| { 1430, 3, 1, 4, 667, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo238 }, // Inst #1430 = DOTP_U_H |
| { 1429, 3, 1, 4, 667, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo237 }, // Inst #1429 = DOTP_U_D |
| { 1428, 3, 1, 4, 667, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo239 }, // Inst #1428 = DOTP_S_W |
| { 1427, 3, 1, 4, 667, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo238 }, // Inst #1427 = DOTP_S_H |
| { 1426, 3, 1, 4, 667, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo237 }, // Inst #1426 = DOTP_S_D |
| { 1425, 3, 1, 4, 914, 0, 0, 0, 0x6ULL, nullptr, OperandInfo71 }, // Inst #1425 = DMUL_R6 |
| { 1424, 3, 1, 4, 901, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo71 }, // Inst #1424 = DMULU |
| { 1423, 2, 0, 4, 903, 0, 2, 0|(1ULL<<MCID::Commutable), 0x1ULL, ImplicitList13, OperandInfo122 }, // Inst #1423 = DMULTu |
| { 1422, 2, 0, 4, 902, 0, 2, 0|(1ULL<<MCID::Commutable), 0x1ULL, ImplicitList13, OperandInfo122 }, // Inst #1422 = DMULT |
| { 1421, 3, 1, 4, 1209, 0, 5, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, ImplicitList12, OperandInfo71 }, // Inst #1421 = DMUL |
| { 1420, 3, 1, 4, 913, 0, 0, 0, 0x6ULL, nullptr, OperandInfo71 }, // Inst #1420 = DMUHU |
| { 1419, 3, 1, 4, 912, 0, 0, 0, 0x6ULL, nullptr, OperandInfo71 }, // Inst #1419 = DMUH |
| { 1418, 3, 1, 4, 1068, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo235 }, // Inst #1418 = DMTGC0 |
| { 1417, 2, 2, 4, 1202, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo112 }, // Inst #1417 = DMTC2_OCTEON |
| { 1416, 3, 1, 4, 1056, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo236 }, // Inst #1416 = DMTC2 |
| { 1415, 2, 1, 4, 1341, 0, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast), 0x4ULL, nullptr, OperandInfo134 }, // Inst #1415 = DMTC1 |
| { 1414, 3, 1, 4, 1054, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo235 }, // Inst #1414 = DMTC0 |
| { 1413, 1, 1, 4, 1059, 0, 0, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo58 }, // Inst #1413 = DMT |
| { 1412, 3, 1, 4, 918, 0, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL, nullptr, OperandInfo71 }, // Inst #1412 = DMODU |
| { 1411, 3, 1, 4, 916, 0, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL, nullptr, OperandInfo71 }, // Inst #1411 = DMOD |
| { 1410, 3, 1, 4, 1067, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo232 }, // Inst #1410 = DMFGC0 |
| { 1409, 2, 2, 4, 1201, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo112 }, // Inst #1409 = DMFC2_OCTEON |
| { 1408, 3, 1, 4, 1055, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo234 }, // Inst #1408 = DMFC2 |
| { 1407, 2, 1, 4, 1340, 0, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast), 0x4ULL, nullptr, OperandInfo233 }, // Inst #1407 = DMFC1 |
| { 1406, 3, 1, 4, 1053, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo232 }, // Inst #1406 = DMFC0 |
| { 1405, 4, 1, 4, 851, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo230 }, // Inst #1405 = DLSA_R6 |
| { 1404, 4, 1, 4, 851, 0, 0, 0, 0x6ULL, nullptr, OperandInfo230 }, // Inst #1404 = DLSA |
| { 1403, 1, 1, 4, 1048, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo58 }, // Inst #1403 = DI_MMR6 |
| { 1402, 1, 1, 4, 1031, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo58 }, // Inst #1402 = DI_MM |
| { 1401, 3, 1, 4, 614, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1401 = DIV_U_W |
| { 1400, 3, 1, 4, 614, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #1400 = DIV_U_H |
| { 1399, 3, 1, 4, 614, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1399 = DIV_U_D |
| { 1398, 3, 1, 4, 614, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #1398 = DIV_U_B |
| { 1397, 3, 1, 4, 614, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1397 = DIV_S_W |
| { 1396, 3, 1, 4, 614, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #1396 = DIV_S_H |
| { 1395, 3, 1, 4, 614, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1395 = DIV_S_D |
| { 1394, 3, 1, 4, 614, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #1394 = DIV_S_B |
| { 1393, 3, 1, 4, 899, 0, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UsesCustomInserter), 0x6ULL, nullptr, OperandInfo72 }, // Inst #1393 = DIV_MMR6 |
| { 1392, 3, 1, 4, 898, 0, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UsesCustomInserter), 0x6ULL, nullptr, OperandInfo72 }, // Inst #1392 = DIVU_MMR6 |
| { 1391, 3, 1, 4, 485, 0, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL, nullptr, OperandInfo72 }, // Inst #1391 = DIVU |
| { 1390, 3, 1, 4, 484, 0, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL, nullptr, OperandInfo72 }, // Inst #1390 = DIV |
| { 1389, 5, 1, 4, 823, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, OperandInfo231 }, // Inst #1389 = DINSU |
| { 1388, 5, 1, 4, 823, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, OperandInfo231 }, // Inst #1388 = DINSM |
| { 1387, 5, 1, 4, 823, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, OperandInfo231 }, // Inst #1387 = DINS |
| { 1386, 1, 1, 4, 476, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo58 }, // Inst #1386 = DI |
| { 1385, 4, 1, 4, 822, 0, 0, 0, 0x1ULL, nullptr, OperandInfo211 }, // Inst #1385 = DEXTU |
| { 1384, 4, 1, 4, 822, 0, 0, 0, 0x1ULL, nullptr, OperandInfo211 }, // Inst #1384 = DEXTM |
| { 1383, 4, 1, 4, 807, 0, 0, 0, 0x1ULL, nullptr, OperandInfo212 }, // Inst #1383 = DEXT64_32 |
| { 1382, 4, 1, 4, 822, 0, 0, 0, 0x1ULL, nullptr, OperandInfo211 }, // Inst #1382 = DEXT |
| { 1381, 0, 0, 4, 988, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr }, // Inst #1381 = DERET_MMR6 |
| { 1380, 0, 0, 4, 952, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr }, // Inst #1380 = DERET_MM |
| { 1379, 0, 0, 4, 380, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr }, // Inst #1379 = DERET |
| { 1378, 3, 1, 4, 917, 0, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL, nullptr, OperandInfo71 }, // Inst #1378 = DDIVU |
| { 1377, 3, 1, 4, 915, 0, 0, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL, nullptr, OperandInfo71 }, // Inst #1377 = DDIV |
| { 1376, 2, 1, 4, 849, 0, 0, 0, 0x6ULL, nullptr, OperandInfo122 }, // Inst #1376 = DCLZ_R6 |
| { 1375, 2, 1, 4, 821, 0, 0, 0, 0x1ULL, nullptr, OperandInfo122 }, // Inst #1375 = DCLZ |
| { 1374, 2, 1, 4, 848, 0, 0, 0, 0x6ULL, nullptr, OperandInfo122 }, // Inst #1374 = DCLO_R6 |
| { 1373, 2, 1, 4, 820, 0, 0, 0, 0x1ULL, nullptr, OperandInfo122 }, // Inst #1373 = DCLO |
| { 1372, 2, 1, 4, 850, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo122 }, // Inst #1372 = DBITSWAP |
| { 1371, 3, 1, 4, 847, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo70 }, // Inst #1371 = DAUI |
| { 1370, 3, 1, 4, 846, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo229 }, // Inst #1370 = DATI |
| { 1369, 4, 1, 4, 844, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo230 }, // Inst #1369 = DALIGN |
| { 1368, 3, 1, 4, 845, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo229 }, // Inst #1368 = DAHI |
| { 1367, 3, 1, 4, 819, 0, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, OperandInfo71 }, // Inst #1367 = DADDu |
| { 1366, 3, 1, 4, 818, 0, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2ULL, nullptr, OperandInfo70 }, // Inst #1366 = DADDiu |
| { 1365, 3, 1, 4, 817, 0, 0, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, OperandInfo70 }, // Inst #1365 = DADDi |
| { 1364, 3, 1, 4, 816, 0, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, OperandInfo71 }, // Inst #1364 = DADD |
| { 1363, 2, 0, 4, 735, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList7, OperandInfo183 }, // Inst #1363 = CmpiRxImmX16 |
| { 1362, 2, 0, 2, 735, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList7, OperandInfo183 }, // Inst #1362 = CmpiRxImm16 |
| { 1361, 2, 0, 2, 735, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList7, OperandInfo130 }, // Inst #1361 = CmpRxRy16 |
| { 1360, 3, 1, 4, 1260, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo228 }, // Inst #1360 = C_UN_S_MM |
| { 1359, 3, 1, 4, 641, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo228 }, // Inst #1359 = C_UN_S |
| { 1358, 3, 1, 4, 1259, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo227 }, // Inst #1358 = C_UN_D64_MM |
| { 1357, 3, 1, 4, 640, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo227 }, // Inst #1357 = C_UN_D64 |
| { 1356, 3, 1, 4, 1259, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo226 }, // Inst #1356 = C_UN_D32_MM |
| { 1355, 3, 1, 4, 640, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo226 }, // Inst #1355 = C_UN_D32 |
| { 1354, 3, 1, 4, 1262, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo228 }, // Inst #1354 = C_ULT_S_MM |
| { 1353, 3, 1, 4, 641, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo228 }, // Inst #1353 = C_ULT_S |
| { 1352, 3, 1, 4, 1261, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo227 }, // Inst #1352 = C_ULT_D64_MM |
| { 1351, 3, 1, 4, 640, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo227 }, // Inst #1351 = C_ULT_D64 |
| { 1350, 3, 1, 4, 1261, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo226 }, // Inst #1350 = C_ULT_D32_MM |
| { 1349, 3, 1, 4, 640, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo226 }, // Inst #1349 = C_ULT_D32 |
| { 1348, 3, 1, 4, 1262, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo228 }, // Inst #1348 = C_ULE_S_MM |
| { 1347, 3, 1, 4, 641, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo228 }, // Inst #1347 = C_ULE_S |
| { 1346, 3, 1, 4, 1261, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo227 }, // Inst #1346 = C_ULE_D64_MM |
| { 1345, 3, 1, 4, 640, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo227 }, // Inst #1345 = C_ULE_D64 |
| { 1344, 3, 1, 4, 1261, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo226 }, // Inst #1344 = C_ULE_D32_MM |
| { 1343, 3, 1, 4, 640, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo226 }, // Inst #1343 = C_ULE_D32 |
| { 1342, 3, 1, 4, 1262, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo228 }, // Inst #1342 = C_UEQ_S_MM |
| { 1341, 3, 1, 4, 641, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo228 }, // Inst #1341 = C_UEQ_S |
| { 1340, 3, 1, 4, 1261, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo227 }, // Inst #1340 = C_UEQ_D64_MM |
| { 1339, 3, 1, 4, 640, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo227 }, // Inst #1339 = C_UEQ_D64 |
| { 1338, 3, 1, 4, 1261, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo226 }, // Inst #1338 = C_UEQ_D32_MM |
| { 1337, 3, 1, 4, 640, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo226 }, // Inst #1337 = C_UEQ_D32 |
| { 1336, 3, 1, 4, 1260, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo228 }, // Inst #1336 = C_SF_S_MM |
| { 1335, 3, 1, 4, 641, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo228 }, // Inst #1335 = C_SF_S |
| { 1334, 3, 1, 4, 1259, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo227 }, // Inst #1334 = C_SF_D64_MM |
| { 1333, 3, 1, 4, 640, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo227 }, // Inst #1333 = C_SF_D64 |
| { 1332, 3, 1, 4, 1259, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo226 }, // Inst #1332 = C_SF_D32_MM |
| { 1331, 3, 1, 4, 640, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo226 }, // Inst #1331 = C_SF_D32 |
| { 1330, 3, 1, 4, 1262, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo228 }, // Inst #1330 = C_SEQ_S_MM |
| { 1329, 3, 1, 4, 641, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo228 }, // Inst #1329 = C_SEQ_S |
| { 1328, 3, 1, 4, 1261, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo227 }, // Inst #1328 = C_SEQ_D64_MM |
| { 1327, 3, 1, 4, 640, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo227 }, // Inst #1327 = C_SEQ_D64 |
| { 1326, 3, 1, 4, 1261, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo226 }, // Inst #1326 = C_SEQ_D32_MM |
| { 1325, 3, 1, 4, 640, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo226 }, // Inst #1325 = C_SEQ_D32 |
| { 1324, 3, 1, 4, 1262, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo228 }, // Inst #1324 = C_OLT_S_MM |
| { 1323, 3, 1, 4, 641, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo228 }, // Inst #1323 = C_OLT_S |
| { 1322, 3, 1, 4, 1261, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo227 }, // Inst #1322 = C_OLT_D64_MM |
| { 1321, 3, 1, 4, 640, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo227 }, // Inst #1321 = C_OLT_D64 |
| { 1320, 3, 1, 4, 1261, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo226 }, // Inst #1320 = C_OLT_D32_MM |
| { 1319, 3, 1, 4, 640, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo226 }, // Inst #1319 = C_OLT_D32 |
| { 1318, 3, 1, 4, 1262, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo228 }, // Inst #1318 = C_OLE_S_MM |
| { 1317, 3, 1, 4, 641, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo228 }, // Inst #1317 = C_OLE_S |
| { 1316, 3, 1, 4, 1261, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo227 }, // Inst #1316 = C_OLE_D64_MM |
| { 1315, 3, 1, 4, 640, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo227 }, // Inst #1315 = C_OLE_D64 |
| { 1314, 3, 1, 4, 1261, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo226 }, // Inst #1314 = C_OLE_D32_MM |
| { 1313, 3, 1, 4, 640, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo226 }, // Inst #1313 = C_OLE_D32 |
| { 1312, 3, 1, 4, 1262, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo228 }, // Inst #1312 = C_NGT_S_MM |
| { 1311, 3, 1, 4, 641, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo228 }, // Inst #1311 = C_NGT_S |
| { 1310, 3, 1, 4, 1261, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo227 }, // Inst #1310 = C_NGT_D64_MM |
| { 1309, 3, 1, 4, 640, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo227 }, // Inst #1309 = C_NGT_D64 |
| { 1308, 3, 1, 4, 1261, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo226 }, // Inst #1308 = C_NGT_D32_MM |
| { 1307, 3, 1, 4, 640, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo226 }, // Inst #1307 = C_NGT_D32 |
| { 1306, 3, 1, 4, 1262, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo228 }, // Inst #1306 = C_NGL_S_MM |
| { 1305, 3, 1, 4, 641, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo228 }, // Inst #1305 = C_NGL_S |
| { 1304, 3, 1, 4, 1261, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo227 }, // Inst #1304 = C_NGL_D64_MM |
| { 1303, 3, 1, 4, 640, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo227 }, // Inst #1303 = C_NGL_D64 |
| { 1302, 3, 1, 4, 1261, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo226 }, // Inst #1302 = C_NGL_D32_MM |
| { 1301, 3, 1, 4, 640, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo226 }, // Inst #1301 = C_NGL_D32 |
| { 1300, 3, 1, 4, 1264, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo228 }, // Inst #1300 = C_NGLE_S_MM |
| { 1299, 3, 1, 4, 641, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo228 }, // Inst #1299 = C_NGLE_S |
| { 1298, 3, 1, 4, 1263, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo227 }, // Inst #1298 = C_NGLE_D64_MM |
| { 1297, 3, 1, 4, 640, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo227 }, // Inst #1297 = C_NGLE_D64 |
| { 1296, 3, 1, 4, 1263, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo226 }, // Inst #1296 = C_NGLE_D32_MM |
| { 1295, 3, 1, 4, 640, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo226 }, // Inst #1295 = C_NGLE_D32 |
| { 1294, 3, 1, 4, 1262, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo228 }, // Inst #1294 = C_NGE_S_MM |
| { 1293, 3, 1, 4, 641, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo228 }, // Inst #1293 = C_NGE_S |
| { 1292, 3, 1, 4, 1261, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo227 }, // Inst #1292 = C_NGE_D64_MM |
| { 1291, 3, 1, 4, 640, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo227 }, // Inst #1291 = C_NGE_D64 |
| { 1290, 3, 1, 4, 1261, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo226 }, // Inst #1290 = C_NGE_D32_MM |
| { 1289, 3, 1, 4, 640, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo226 }, // Inst #1289 = C_NGE_D32 |
| { 1288, 3, 1, 4, 1260, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo228 }, // Inst #1288 = C_LT_S_MM |
| { 1287, 3, 1, 4, 641, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo228 }, // Inst #1287 = C_LT_S |
| { 1286, 3, 1, 4, 1259, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo227 }, // Inst #1286 = C_LT_D64_MM |
| { 1285, 3, 1, 4, 640, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo227 }, // Inst #1285 = C_LT_D64 |
| { 1284, 3, 1, 4, 1259, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo226 }, // Inst #1284 = C_LT_D32_MM |
| { 1283, 3, 1, 4, 640, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo226 }, // Inst #1283 = C_LT_D32 |
| { 1282, 3, 1, 4, 1260, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo228 }, // Inst #1282 = C_LE_S_MM |
| { 1281, 3, 1, 4, 641, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo228 }, // Inst #1281 = C_LE_S |
| { 1280, 3, 1, 4, 1259, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo227 }, // Inst #1280 = C_LE_D64_MM |
| { 1279, 3, 1, 4, 640, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo227 }, // Inst #1279 = C_LE_D64 |
| { 1278, 3, 1, 4, 1259, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo226 }, // Inst #1278 = C_LE_D32_MM |
| { 1277, 3, 1, 4, 640, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo226 }, // Inst #1277 = C_LE_D32 |
| { 1276, 3, 1, 4, 1258, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo228 }, // Inst #1276 = C_F_S_MM |
| { 1275, 3, 1, 4, 641, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo228 }, // Inst #1275 = C_F_S |
| { 1274, 3, 1, 4, 1257, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo227 }, // Inst #1274 = C_F_D64_MM |
| { 1273, 3, 1, 4, 640, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo227 }, // Inst #1273 = C_F_D64 |
| { 1272, 3, 1, 4, 1257, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo226 }, // Inst #1272 = C_F_D32_MM |
| { 1271, 3, 1, 4, 640, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo226 }, // Inst #1271 = C_F_D32 |
| { 1270, 3, 1, 4, 1260, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo228 }, // Inst #1270 = C_EQ_S_MM |
| { 1269, 3, 1, 4, 641, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo228 }, // Inst #1269 = C_EQ_S |
| { 1268, 3, 1, 4, 1259, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo227 }, // Inst #1268 = C_EQ_D64_MM |
| { 1267, 3, 1, 4, 640, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo227 }, // Inst #1267 = C_EQ_D64 |
| { 1266, 3, 1, 4, 1259, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo226 }, // Inst #1266 = C_EQ_D32_MM |
| { 1265, 3, 1, 4, 640, 0, 0, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, OperandInfo226 }, // Inst #1265 = C_EQ_D32 |
| { 1264, 2, 1, 4, 1307, 0, 0, 0, 0x4ULL, nullptr, OperandInfo207 }, // Inst #1264 = CVT_W_S_MMR6 |
| { 1263, 2, 1, 4, 1246, 0, 0, 0, 0x4ULL, nullptr, OperandInfo207 }, // Inst #1263 = CVT_W_S_MM |
| { 1262, 2, 1, 4, 638, 0, 0, 0, 0x4ULL, nullptr, OperandInfo207 }, // Inst #1262 = CVT_W_S |
| { 1261, 2, 1, 4, 1246, 0, 0, 0, 0x4ULL, nullptr, OperandInfo206 }, // Inst #1261 = CVT_W_D64_MM |
| { 1260, 2, 1, 4, 638, 0, 0, 0, 0x4ULL, nullptr, OperandInfo206 }, // Inst #1260 = CVT_W_D64 |
| { 1259, 2, 1, 4, 1246, 0, 0, 0, 0x4ULL, nullptr, OperandInfo205 }, // Inst #1259 = CVT_W_D32_MM |
| { 1258, 2, 1, 4, 638, 0, 0, 0, 0x4ULL, nullptr, OperandInfo205 }, // Inst #1258 = CVT_W_D32 |
| { 1257, 2, 1, 4, 1307, 0, 0, 0, 0x4ULL, nullptr, OperandInfo207 }, // Inst #1257 = CVT_S_W_MMR6 |
| { 1256, 2, 1, 4, 1246, 0, 0, 0, 0x4ULL, nullptr, OperandInfo207 }, // Inst #1256 = CVT_S_W_MM |
| { 1255, 2, 1, 4, 638, 0, 0, 0, 0x4ULL, nullptr, OperandInfo207 }, // Inst #1255 = CVT_S_W |
| { 1254, 2, 1, 4, 639, 0, 0, 0, 0x4ULL, nullptr, OperandInfo206 }, // Inst #1254 = CVT_S_PU64 |
| { 1253, 2, 1, 4, 639, 0, 0, 0, 0x4ULL, nullptr, OperandInfo206 }, // Inst #1253 = CVT_S_PL64 |
| { 1252, 2, 1, 4, 1307, 0, 0, 0, 0x4ULL, nullptr, OperandInfo204 }, // Inst #1252 = CVT_S_L_MMR6 |
| { 1251, 2, 1, 4, 638, 0, 0, 0, 0x4ULL, nullptr, OperandInfo206 }, // Inst #1251 = CVT_S_L |
| { 1250, 2, 1, 4, 1246, 0, 0, 0, 0x4ULL, nullptr, OperandInfo206 }, // Inst #1250 = CVT_S_D64_MM |
| { 1249, 2, 1, 4, 638, 0, 0, 0, 0x4ULL, nullptr, OperandInfo206 }, // Inst #1249 = CVT_S_D64 |
| { 1248, 2, 1, 4, 1246, 0, 0, 0, 0x4ULL, nullptr, OperandInfo205 }, // Inst #1248 = CVT_S_D32_MM |
| { 1247, 2, 1, 4, 638, 0, 0, 0, 0x4ULL, nullptr, OperandInfo205 }, // Inst #1247 = CVT_S_D32 |
| { 1246, 2, 1, 4, 1212, 0, 0, 0, 0x4ULL, nullptr, OperandInfo203 }, // Inst #1246 = CVT_PW_PS64 |
| { 1245, 3, 1, 4, 639, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo225 }, // Inst #1245 = CVT_PS_S64 |
| { 1244, 2, 1, 4, 1212, 0, 0, 0, 0x4ULL, nullptr, OperandInfo203 }, // Inst #1244 = CVT_PS_PW64 |
| { 1243, 2, 1, 4, 1307, 0, 0, 0, 0x4ULL, nullptr, OperandInfo204 }, // Inst #1243 = CVT_L_S_MMR6 |
| { 1242, 2, 1, 4, 1246, 0, 0, 0, 0x4ULL, nullptr, OperandInfo204 }, // Inst #1242 = CVT_L_S_MM |
| { 1241, 2, 1, 4, 638, 0, 0, 0, 0x4ULL, nullptr, OperandInfo204 }, // Inst #1241 = CVT_L_S |
| { 1240, 2, 1, 4, 1307, 0, 0, 0, 0x4ULL, nullptr, OperandInfo203 }, // Inst #1240 = CVT_L_D_MMR6 |
| { 1239, 2, 1, 4, 1246, 0, 0, 0, 0x4ULL, nullptr, OperandInfo203 }, // Inst #1239 = CVT_L_D64_MM |
| { 1238, 2, 1, 4, 638, 0, 0, 0, 0x4ULL, nullptr, OperandInfo203 }, // Inst #1238 = CVT_L_D64 |
| { 1237, 2, 1, 4, 1307, 0, 0, 0, 0x4ULL, nullptr, OperandInfo203 }, // Inst #1237 = CVT_D_L_MMR6 |
| { 1236, 2, 1, 4, 1246, 0, 0, 0, 0x4ULL, nullptr, OperandInfo204 }, // Inst #1236 = CVT_D64_W_MM |
| { 1235, 2, 1, 4, 638, 0, 0, 0, 0x4ULL, nullptr, OperandInfo204 }, // Inst #1235 = CVT_D64_W |
| { 1234, 2, 1, 4, 1246, 0, 0, 0, 0x4ULL, nullptr, OperandInfo204 }, // Inst #1234 = CVT_D64_S_MM |
| { 1233, 2, 1, 4, 638, 0, 0, 0, 0x4ULL, nullptr, OperandInfo204 }, // Inst #1233 = CVT_D64_S |
| { 1232, 2, 1, 4, 638, 0, 0, 0, 0x4ULL, nullptr, OperandInfo203 }, // Inst #1232 = CVT_D64_L |
| { 1231, 2, 1, 4, 1246, 0, 0, 0, 0x4ULL, nullptr, OperandInfo224 }, // Inst #1231 = CVT_D32_W_MM |
| { 1230, 2, 1, 4, 638, 0, 0, 0, 0x4ULL, nullptr, OperandInfo224 }, // Inst #1230 = CVT_D32_W |
| { 1229, 2, 1, 4, 1246, 0, 0, 0, 0x4ULL, nullptr, OperandInfo224 }, // Inst #1229 = CVT_D32_S_MM |
| { 1228, 2, 1, 4, 638, 0, 0, 0, 0x4ULL, nullptr, OperandInfo224 }, // Inst #1228 = CVT_D32_S |
| { 1227, 2, 0, 4, 529, 0, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo223 }, // Inst #1227 = CTCMSA |
| { 1226, 2, 1, 4, 1058, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo222 }, // Inst #1226 = CTC2_MM |
| { 1225, 2, 1, 4, 1295, 0, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo221 }, // Inst #1225 = CTC1_MM |
| { 1224, 2, 1, 4, 685, 0, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo221 }, // Inst #1224 = CTC1 |
| { 1223, 3, 1, 4, 1192, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo72 }, // Inst #1223 = CRC32W |
| { 1222, 3, 1, 4, 1191, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo72 }, // Inst #1222 = CRC32H |
| { 1221, 3, 1, 4, 1196, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo72 }, // Inst #1221 = CRC32D |
| { 1220, 3, 1, 4, 1195, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo72 }, // Inst #1220 = CRC32CW |
| { 1219, 3, 1, 4, 1194, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo72 }, // Inst #1219 = CRC32CH |
| { 1218, 3, 1, 4, 1197, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo72 }, // Inst #1218 = CRC32CD |
| { 1217, 3, 1, 4, 1193, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo72 }, // Inst #1217 = CRC32CB |
| { 1216, 3, 1, 4, 1190, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo72 }, // Inst #1216 = CRC32B |
| { 1215, 3, 1, 4, 688, 0, 0, 0, 0x6ULL, nullptr, OperandInfo220 }, // Inst #1215 = COPY_U_W |
| { 1214, 3, 1, 4, 688, 0, 0, 0, 0x6ULL, nullptr, OperandInfo219 }, // Inst #1214 = COPY_U_H |
| { 1213, 3, 1, 4, 688, 0, 0, 0, 0x6ULL, nullptr, OperandInfo217 }, // Inst #1213 = COPY_U_B |
| { 1212, 3, 1, 4, 689, 0, 0, 0, 0x6ULL, nullptr, OperandInfo220 }, // Inst #1212 = COPY_S_W |
| { 1211, 3, 1, 4, 689, 0, 0, 0, 0x6ULL, nullptr, OperandInfo219 }, // Inst #1211 = COPY_S_H |
| { 1210, 3, 1, 4, 689, 0, 0, 0, 0x6ULL, nullptr, OperandInfo218 }, // Inst #1210 = COPY_S_D |
| { 1209, 3, 1, 4, 689, 0, 0, 0, 0x6ULL, nullptr, OperandInfo217 }, // Inst #1209 = COPY_S_B |
| { 1208, 3, 1, 4, 1302, 0, 0, 0, 0x16ULL, nullptr, OperandInfo216 }, // Inst #1208 = CMP_UN_S_MMR6 |
| { 1207, 3, 1, 4, 558, 0, 0, 0, 0x16ULL, nullptr, OperandInfo216 }, // Inst #1207 = CMP_UN_S |
| { 1206, 3, 1, 4, 1301, 0, 0, 0, 0x16ULL, nullptr, OperandInfo215 }, // Inst #1206 = CMP_UN_D_MMR6 |
| { 1205, 3, 1, 4, 557, 0, 0, 0, 0x16ULL, nullptr, OperandInfo215 }, // Inst #1205 = CMP_UN_D |
| { 1204, 3, 1, 4, 1304, 0, 0, 0, 0x16ULL, nullptr, OperandInfo216 }, // Inst #1204 = CMP_ULT_S_MMR6 |
| { 1203, 3, 1, 4, 566, 0, 0, 0, 0x16ULL, nullptr, OperandInfo216 }, // Inst #1203 = CMP_ULT_S |
| { 1202, 3, 1, 4, 1303, 0, 0, 0, 0x16ULL, nullptr, OperandInfo215 }, // Inst #1202 = CMP_ULT_D_MMR6 |
| { 1201, 3, 1, 4, 565, 0, 0, 0, 0x16ULL, nullptr, OperandInfo215 }, // Inst #1201 = CMP_ULT_D |
| { 1200, 3, 1, 4, 1304, 0, 0, 0, 0x16ULL, nullptr, OperandInfo216 }, // Inst #1200 = CMP_ULE_S_MMR6 |
| { 1199, 3, 1, 4, 570, 0, 0, 0, 0x16ULL, nullptr, OperandInfo216 }, // Inst #1199 = CMP_ULE_S |
| { 1198, 3, 1, 4, 1303, 0, 0, 0, 0x16ULL, nullptr, OperandInfo215 }, // Inst #1198 = CMP_ULE_D_MMR6 |
| { 1197, 3, 1, 4, 569, 0, 0, 0, 0x16ULL, nullptr, OperandInfo215 }, // Inst #1197 = CMP_ULE_D |
| { 1196, 3, 1, 4, 1304, 0, 0, 0, 0x16ULL, nullptr, OperandInfo216 }, // Inst #1196 = CMP_UEQ_S_MMR6 |
| { 1195, 3, 1, 4, 560, 0, 0, 0, 0x16ULL, nullptr, OperandInfo216 }, // Inst #1195 = CMP_UEQ_S |
| { 1194, 3, 1, 4, 1303, 0, 0, 0, 0x16ULL, nullptr, OperandInfo215 }, // Inst #1194 = CMP_UEQ_D_MMR6 |
| { 1193, 3, 1, 4, 559, 0, 0, 0, 0x16ULL, nullptr, OperandInfo215 }, // Inst #1193 = CMP_UEQ_D |
| { 1192, 3, 1, 4, 1304, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo216 }, // Inst #1192 = CMP_SUN_S_MMR6 |
| { 1191, 3, 1, 4, 1688, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo216 }, // Inst #1191 = CMP_SUN_S |
| { 1190, 3, 1, 4, 1303, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo215 }, // Inst #1190 = CMP_SUN_D_MMR6 |
| { 1189, 3, 1, 4, 1687, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo215 }, // Inst #1189 = CMP_SUN_D |
| { 1188, 3, 1, 4, 1306, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo216 }, // Inst #1188 = CMP_SULT_S_MMR6 |
| { 1187, 3, 1, 4, 1686, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo216 }, // Inst #1187 = CMP_SULT_S |
| { 1186, 3, 1, 4, 1305, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo215 }, // Inst #1186 = CMP_SULT_D_MMR6 |
| { 1185, 3, 1, 4, 1685, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo215 }, // Inst #1185 = CMP_SULT_D |
| { 1184, 3, 1, 4, 1306, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo216 }, // Inst #1184 = CMP_SULE_S_MMR6 |
| { 1183, 3, 1, 4, 1684, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo216 }, // Inst #1183 = CMP_SULE_S |
| { 1182, 3, 1, 4, 1305, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo215 }, // Inst #1182 = CMP_SULE_D_MMR6 |
| { 1181, 3, 1, 4, 1683, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo215 }, // Inst #1181 = CMP_SULE_D |
| { 1180, 3, 1, 4, 1306, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo216 }, // Inst #1180 = CMP_SUEQ_S_MMR6 |
| { 1179, 3, 1, 4, 1682, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo216 }, // Inst #1179 = CMP_SUEQ_S |
| { 1178, 3, 1, 4, 1305, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo215 }, // Inst #1178 = CMP_SUEQ_D_MMR6 |
| { 1177, 3, 1, 4, 1681, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo215 }, // Inst #1177 = CMP_SUEQ_D |
| { 1176, 3, 1, 4, 1304, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo216 }, // Inst #1176 = CMP_SLT_S_MMR6 |
| { 1175, 3, 1, 4, 1680, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo216 }, // Inst #1175 = CMP_SLT_S |
| { 1174, 3, 1, 4, 1303, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo215 }, // Inst #1174 = CMP_SLT_D_MMR6 |
| { 1173, 3, 1, 4, 1679, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo215 }, // Inst #1173 = CMP_SLT_D |
| { 1172, 3, 1, 4, 1304, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo216 }, // Inst #1172 = CMP_SLE_S_MMR6 |
| { 1171, 3, 1, 4, 1678, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo216 }, // Inst #1171 = CMP_SLE_S |
| { 1170, 3, 1, 4, 1303, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo215 }, // Inst #1170 = CMP_SLE_D_MMR6 |
| { 1169, 3, 1, 4, 1677, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo215 }, // Inst #1169 = CMP_SLE_D |
| { 1168, 3, 1, 4, 1304, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo216 }, // Inst #1168 = CMP_SEQ_S_MMR6 |
| { 1167, 3, 1, 4, 1676, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo216 }, // Inst #1167 = CMP_SEQ_S |
| { 1166, 3, 1, 4, 1303, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo215 }, // Inst #1166 = CMP_SEQ_D_MMR6 |
| { 1165, 3, 1, 4, 1675, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo215 }, // Inst #1165 = CMP_SEQ_D |
| { 1164, 3, 1, 4, 1304, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo216 }, // Inst #1164 = CMP_SAF_S_MMR6 |
| { 1163, 3, 1, 4, 1674, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo216 }, // Inst #1163 = CMP_SAF_S |
| { 1162, 3, 1, 4, 1303, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo215 }, // Inst #1162 = CMP_SAF_D_MMR6 |
| { 1161, 3, 1, 4, 1673, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo215 }, // Inst #1161 = CMP_SAF_D |
| { 1160, 3, 1, 4, 1302, 0, 0, 0, 0x16ULL, nullptr, OperandInfo216 }, // Inst #1160 = CMP_LT_S_MMR6 |
| { 1159, 3, 1, 4, 564, 0, 0, 0, 0x16ULL, nullptr, OperandInfo216 }, // Inst #1159 = CMP_LT_S |
| { 1158, 2, 0, 4, 1527, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList11, OperandInfo168 }, // Inst #1158 = CMP_LT_PH_MM |
| { 1157, 2, 0, 4, 1376, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList11, OperandInfo168 }, // Inst #1157 = CMP_LT_PH |
| { 1156, 3, 1, 4, 1301, 0, 0, 0, 0x16ULL, nullptr, OperandInfo215 }, // Inst #1156 = CMP_LT_D_MMR6 |
| { 1155, 3, 1, 4, 563, 0, 0, 0, 0x16ULL, nullptr, OperandInfo215 }, // Inst #1155 = CMP_LT_D |
| { 1154, 3, 1, 4, 1302, 0, 0, 0, 0x16ULL, nullptr, OperandInfo216 }, // Inst #1154 = CMP_LE_S_MMR6 |
| { 1153, 3, 1, 4, 568, 0, 0, 0, 0x16ULL, nullptr, OperandInfo216 }, // Inst #1153 = CMP_LE_S |
| { 1152, 2, 0, 4, 1526, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList11, OperandInfo168 }, // Inst #1152 = CMP_LE_PH_MM |
| { 1151, 2, 0, 4, 1375, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList11, OperandInfo168 }, // Inst #1151 = CMP_LE_PH |
| { 1150, 3, 1, 4, 1301, 0, 0, 0, 0x16ULL, nullptr, OperandInfo215 }, // Inst #1150 = CMP_LE_D_MMR6 |
| { 1149, 3, 1, 4, 567, 0, 0, 0, 0x16ULL, nullptr, OperandInfo215 }, // Inst #1149 = CMP_LE_D |
| { 1148, 3, 1, 4, 1672, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo216 }, // Inst #1148 = CMP_F_S |
| { 1147, 3, 1, 4, 1671, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo215 }, // Inst #1147 = CMP_F_D |
| { 1146, 3, 1, 4, 1302, 0, 0, 0, 0x16ULL, nullptr, OperandInfo216 }, // Inst #1146 = CMP_EQ_S_MMR6 |
| { 1145, 3, 1, 4, 562, 0, 0, 0, 0x16ULL, nullptr, OperandInfo216 }, // Inst #1145 = CMP_EQ_S |
| { 1144, 2, 0, 4, 1525, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList11, OperandInfo168 }, // Inst #1144 = CMP_EQ_PH_MM |
| { 1143, 2, 0, 4, 1374, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList11, OperandInfo168 }, // Inst #1143 = CMP_EQ_PH |
| { 1142, 3, 1, 4, 1301, 0, 0, 0, 0x16ULL, nullptr, OperandInfo215 }, // Inst #1142 = CMP_EQ_D_MMR6 |
| { 1141, 3, 1, 4, 561, 0, 0, 0, 0x16ULL, nullptr, OperandInfo215 }, // Inst #1141 = CMP_EQ_D |
| { 1140, 3, 1, 4, 1302, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo216 }, // Inst #1140 = CMP_AF_S_MMR6 |
| { 1139, 3, 1, 4, 1301, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo215 }, // Inst #1139 = CMP_AF_D_MMR6 |
| { 1138, 2, 0, 4, 1524, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList11, OperandInfo168 }, // Inst #1138 = CMPU_LT_QB_MM |
| { 1137, 2, 0, 4, 1373, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList11, OperandInfo168 }, // Inst #1137 = CMPU_LT_QB |
| { 1136, 2, 0, 4, 1523, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList11, OperandInfo168 }, // Inst #1136 = CMPU_LE_QB_MM |
| { 1135, 2, 0, 4, 1372, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList11, OperandInfo168 }, // Inst #1135 = CMPU_LE_QB |
| { 1134, 2, 0, 4, 1522, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList11, OperandInfo168 }, // Inst #1134 = CMPU_EQ_QB_MM |
| { 1133, 2, 0, 4, 1371, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList11, OperandInfo168 }, // Inst #1133 = CMPU_EQ_QB |
| { 1132, 3, 1, 4, 1521, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo214 }, // Inst #1132 = CMPGU_LT_QB_MM |
| { 1131, 3, 1, 4, 1370, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo214 }, // Inst #1131 = CMPGU_LT_QB |
| { 1130, 3, 1, 4, 1520, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo214 }, // Inst #1130 = CMPGU_LE_QB_MM |
| { 1129, 3, 1, 4, 1369, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo214 }, // Inst #1129 = CMPGU_LE_QB |
| { 1128, 3, 1, 4, 1519, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo214 }, // Inst #1128 = CMPGU_EQ_QB_MM |
| { 1127, 3, 1, 4, 1368, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo214 }, // Inst #1127 = CMPGU_EQ_QB |
| { 1126, 3, 1, 4, 1637, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList11, OperandInfo214 }, // Inst #1126 = CMPGDU_LT_QB_MMR2 |
| { 1125, 3, 1, 4, 1473, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList11, OperandInfo214 }, // Inst #1125 = CMPGDU_LT_QB |
| { 1124, 3, 1, 4, 1636, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList11, OperandInfo214 }, // Inst #1124 = CMPGDU_LE_QB_MMR2 |
| { 1123, 3, 1, 4, 1472, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList11, OperandInfo214 }, // Inst #1123 = CMPGDU_LE_QB |
| { 1122, 3, 1, 4, 1635, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList11, OperandInfo214 }, // Inst #1122 = CMPGDU_EQ_QB_MMR2 |
| { 1121, 3, 1, 4, 1471, 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList11, OperandInfo214 }, // Inst #1121 = CMPGDU_EQ_QB |
| { 1120, 2, 1, 4, 732, 0, 0, 0, 0x6ULL, nullptr, OperandInfo45 }, // Inst #1120 = CLZ_R6 |
| { 1119, 2, 1, 4, 786, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo45 }, // Inst #1119 = CLZ_MMR6 |
| { 1118, 2, 1, 4, 745, 0, 0, 0, 0x1ULL, nullptr, OperandInfo45 }, // Inst #1118 = CLZ_MM |
| { 1117, 2, 1, 4, 475, 0, 0, 0, 0x1ULL, nullptr, OperandInfo45 }, // Inst #1117 = CLZ |
| { 1116, 3, 1, 4, 554, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1116 = CLT_U_W |
| { 1115, 3, 1, 4, 554, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #1115 = CLT_U_H |
| { 1114, 3, 1, 4, 554, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1114 = CLT_U_D |
| { 1113, 3, 1, 4, 554, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #1113 = CLT_U_B |
| { 1112, 3, 1, 4, 554, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1112 = CLT_S_W |
| { 1111, 3, 1, 4, 554, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #1111 = CLT_S_H |
| { 1110, 3, 1, 4, 554, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1110 = CLT_S_D |
| { 1109, 3, 1, 4, 554, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #1109 = CLT_S_B |
| { 1108, 3, 1, 4, 554, 0, 0, 0, 0x6ULL, nullptr, OperandInfo179 }, // Inst #1108 = CLTI_U_W |
| { 1107, 3, 1, 4, 554, 0, 0, 0, 0x6ULL, nullptr, OperandInfo178 }, // Inst #1107 = CLTI_U_H |
| { 1106, 3, 1, 4, 554, 0, 0, 0, 0x6ULL, nullptr, OperandInfo177 }, // Inst #1106 = CLTI_U_D |
| { 1105, 3, 1, 4, 554, 0, 0, 0, 0x6ULL, nullptr, OperandInfo176 }, // Inst #1105 = CLTI_U_B |
| { 1104, 3, 1, 4, 554, 0, 0, 0, 0x6ULL, nullptr, OperandInfo179 }, // Inst #1104 = CLTI_S_W |
| { 1103, 3, 1, 4, 554, 0, 0, 0, 0x6ULL, nullptr, OperandInfo178 }, // Inst #1103 = CLTI_S_H |
| { 1102, 3, 1, 4, 554, 0, 0, 0, 0x6ULL, nullptr, OperandInfo177 }, // Inst #1102 = CLTI_S_D |
| { 1101, 3, 1, 4, 554, 0, 0, 0, 0x6ULL, nullptr, OperandInfo176 }, // Inst #1101 = CLTI_S_B |
| { 1100, 2, 1, 4, 731, 0, 0, 0, 0x6ULL, nullptr, OperandInfo45 }, // Inst #1100 = CLO_R6 |
| { 1099, 2, 1, 4, 785, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo45 }, // Inst #1099 = CLO_MMR6 |
| { 1098, 2, 1, 4, 744, 0, 0, 0, 0x1ULL, nullptr, OperandInfo45 }, // Inst #1098 = CLO_MM |
| { 1097, 2, 1, 4, 474, 0, 0, 0, 0x1ULL, nullptr, OperandInfo45 }, // Inst #1097 = CLO |
| { 1096, 3, 1, 4, 555, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1096 = CLE_U_W |
| { 1095, 3, 1, 4, 555, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #1095 = CLE_U_H |
| { 1094, 3, 1, 4, 555, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1094 = CLE_U_D |
| { 1093, 3, 1, 4, 555, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #1093 = CLE_U_B |
| { 1092, 3, 1, 4, 555, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1092 = CLE_S_W |
| { 1091, 3, 1, 4, 555, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #1091 = CLE_S_H |
| { 1090, 3, 1, 4, 555, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1090 = CLE_S_D |
| { 1089, 3, 1, 4, 555, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #1089 = CLE_S_B |
| { 1088, 3, 1, 4, 555, 0, 0, 0, 0x6ULL, nullptr, OperandInfo179 }, // Inst #1088 = CLEI_U_W |
| { 1087, 3, 1, 4, 555, 0, 0, 0, 0x6ULL, nullptr, OperandInfo178 }, // Inst #1087 = CLEI_U_H |
| { 1086, 3, 1, 4, 555, 0, 0, 0, 0x6ULL, nullptr, OperandInfo177 }, // Inst #1086 = CLEI_U_D |
| { 1085, 3, 1, 4, 555, 0, 0, 0, 0x6ULL, nullptr, OperandInfo176 }, // Inst #1085 = CLEI_U_B |
| { 1084, 3, 1, 4, 555, 0, 0, 0, 0x6ULL, nullptr, OperandInfo179 }, // Inst #1084 = CLEI_S_W |
| { 1083, 3, 1, 4, 555, 0, 0, 0, 0x6ULL, nullptr, OperandInfo178 }, // Inst #1083 = CLEI_S_H |
| { 1082, 3, 1, 4, 555, 0, 0, 0, 0x6ULL, nullptr, OperandInfo177 }, // Inst #1082 = CLEI_S_D |
| { 1081, 3, 1, 4, 555, 0, 0, 0, 0x6ULL, nullptr, OperandInfo176 }, // Inst #1081 = CLEI_S_B |
| { 1080, 2, 1, 4, 1314, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo207 }, // Inst #1080 = CLASS_S_MMR6 |
| { 1079, 2, 1, 4, 1227, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo207 }, // Inst #1079 = CLASS_S |
| { 1078, 2, 1, 4, 1314, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo203 }, // Inst #1078 = CLASS_D_MMR6 |
| { 1077, 2, 1, 4, 1228, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo203 }, // Inst #1077 = CLASS_D |
| { 1076, 4, 1, 4, 1200, 0, 0, 0, 0x1ULL, nullptr, OperandInfo213 }, // Inst #1076 = CINS_i32 |
| { 1075, 4, 1, 4, 1200, 0, 0, 0, 0x1ULL, nullptr, OperandInfo212 }, // Inst #1075 = CINS64_32 |
| { 1074, 4, 1, 4, 1200, 0, 0, 0, 0x1ULL, nullptr, OperandInfo211 }, // Inst #1074 = CINS32 |
| { 1073, 4, 1, 4, 1200, 0, 0, 0, 0x1ULL, nullptr, OperandInfo211 }, // Inst #1073 = CINS |
| { 1072, 2, 1, 4, 529, 0, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo210 }, // Inst #1072 = CFCMSA |
| { 1071, 2, 1, 4, 1057, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo209 }, // Inst #1071 = CFC2_MM |
| { 1070, 2, 1, 4, 1294, 0, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo208 }, // Inst #1070 = CFC1_MM |
| { 1069, 2, 1, 4, 694, 0, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, OperandInfo208 }, // Inst #1069 = CFC1 |
| { 1068, 3, 1, 4, 556, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo48 }, // Inst #1068 = CEQ_W |
| { 1067, 3, 1, 4, 556, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo47 }, // Inst #1067 = CEQ_H |
| { 1066, 3, 1, 4, 556, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo46 }, // Inst #1066 = CEQ_D |
| { 1065, 3, 1, 4, 556, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo174 }, // Inst #1065 = CEQ_B |
| { 1064, 3, 1, 4, 556, 0, 0, 0, 0x6ULL, nullptr, OperandInfo179 }, // Inst #1064 = CEQI_W |
| { 1063, 3, 1, 4, 556, 0, 0, 0, 0x6ULL, nullptr, OperandInfo178 }, // Inst #1063 = CEQI_H |
| { 1062, 3, 1, 4, 556, 0, 0, 0, 0x6ULL, nullptr, OperandInfo177 }, // Inst #1062 = CEQI_D |
| { 1061, 3, 1, 4, 556, 0, 0, 0, 0x6ULL, nullptr, OperandInfo176 }, // Inst #1061 = CEQI_B |
| { 1060, 2, 1, 4, 1311, 0, 0, 0, 0x4ULL, nullptr, OperandInfo207 }, // Inst #1060 = CEIL_W_S_MMR6 |
| { 1059, 2, 1, 4, 1247, 0, 0, 0, 0x4ULL, nullptr, OperandInfo207 }, // Inst #1059 = CEIL_W_S_MM |
| { 1058, 2, 1, 4, 717, 0, 0, 0, 0x4ULL, nullptr, OperandInfo207 }, // Inst #1058 = CEIL_W_S |
| { 1057, 2, 1, 4, 1247, 0, 0, 0, 0x4ULL, nullptr, OperandInfo205 }, // Inst #1057 = CEIL_W_MM |
| { 1056, 2, 1, 4, 1311, 0, 0, 0, 0x4ULL, nullptr, OperandInfo205 }, // Inst #1056 = CEIL_W_D_MMR6 |
| { 1055, 2, 1, 4, 717, 0, 0, 0, 0x4ULL, nullptr, OperandInfo206 }, // Inst #1055 = CEIL_W_D64 |
| { 1054, 2, 1, 4, 717, 0, 0, 0, 0x4ULL, nullptr, OperandInfo205 }, // Inst #1054 = CEIL_W_D32 |
| { 1053, 2, 1, 4, 1311, 0, 0, 0, 0x4ULL, nullptr, OperandInfo204 }, // Inst #1053 = CEIL_L_S_MMR6 |
| { 1052, 2, 1, 4, 717, 0, 0, 0, 0x4ULL, nullptr, OperandInfo204 }, // Inst #1052 = CEIL_L_S |
| { 1051, 2, 1, 4, 1311, 0, 0, 0, 0x4ULL, nullptr, OperandInfo203 }, // Inst #1051 = CEIL_L_D_MMR6 |
| { 1050, 2, 1, 4, 717, 0, 0, 0, 0x4ULL, nullptr, OperandInfo203 }, // Inst #1050 = CEIL_L_D64 |
| { 1049, 3, 0, 4, 1088, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo202 }, // Inst #1049 = CACHE_R6 |
| { 1048, 3, 0, 4, 1162, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo202 }, // Inst #1048 = CACHE_MMR6 |
| { 1047, 3, 0, 4, 1140, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo202 }, // Inst #1047 = CACHE_MM |
| { 1046, 3, 0, 4, 1107, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo202 }, // Inst #1046 = CACHEE_MM |
| { 1045, 3, 0, 4, 471, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo202 }, // Inst #1045 = CACHEE |
| { 1044, 3, 0, 4, 470, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo202 }, // Inst #1044 = CACHE |
| { 1043, 1, 0, 4, 939, 1, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList7, OperandInfo2 }, // Inst #1043 = BtnezX16 |
| { 1042, 1, 0, 2, 939, 1, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList7, OperandInfo2 }, // Inst #1042 = Btnez16 |
| { 1041, 1, 0, 4, 939, 1, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList7, OperandInfo2 }, // Inst #1041 = BteqzX16 |
| { 1040, 1, 0, 2, 939, 1, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList7, OperandInfo2 }, // Inst #1040 = Bteqz16 |
| { 1039, 0, 0, 2, 943, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr }, // Inst #1039 = Break16 |
| { 1038, 2, 0, 4, 939, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo201 }, // Inst #1038 = BnezRxImmX16 |
| { 1037, 2, 0, 2, 939, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, OperandInfo201 }, // Inst #1037 = BnezRxImm16 |
| { 1036, 1, 0, 4, 939, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo55 }, // Inst #1036 = BimmX16 |
| { 1035, 1, 0, 2, 939, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, OperandInfo55 }, // Inst #1035 = Bimm16 |
| { 1034, 2, 0, 4, 939, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo201 }, // Inst #1034 = BeqzRxImmX16 |
| { 1033, 2, 0, 2, 939, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, OperandInfo201 }, // Inst #1033 = BeqzRxImm16 |
| { 1032, 2, 0, 4, 528, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList2, OperandInfo200 }, // Inst #1032 = BZ_W |
| { 1031, 2, 0, 4, 528, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList2, OperandInfo197 }, // Inst #1031 = BZ_V |
| { 1030, 2, 0, 4, 528, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList2, OperandInfo199 }, // Inst #1030 = BZ_H |
| { 1029, 2, 0, 4, 528, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList2, OperandInfo198 }, // Inst #1029 = BZ_D |
| { 1028, 2, 0, 4, 528, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList2, OperandInfo197 }, // Inst #1028 = BZ_B |
| { 1027, 3, 1, 4, 520, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #1027 = BSET_W |
| { 1026, 3, 1, 4, 520, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #1026 = BSET_H |
| { 1025, 3, 1, 4, 520, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #1025 = BSET_D |
| { 1024, 3, 1, 4, 520, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #1024 = BSET_B |
| { 1023, 3, 1, 4, 520, 0, 0, 0, 0x6ULL, nullptr, OperandInfo179 }, // Inst #1023 = BSETI_W |
| { 1022, 3, 1, 4, 520, 0, 0, 0, 0x6ULL, nullptr, OperandInfo178 }, // Inst #1022 = BSETI_H |
| { 1021, 3, 1, 4, 520, 0, 0, 0, 0x6ULL, nullptr, OperandInfo177 }, // Inst #1021 = BSETI_D |
| { 1020, 3, 1, 4, 520, 0, 0, 0, 0x6ULL, nullptr, OperandInfo176 }, // Inst #1020 = BSETI_B |
| { 1019, 4, 1, 4, 523, 0, 0, 0, 0x6ULL, nullptr, OperandInfo196 }, // Inst #1019 = BSEL_V |
| { 1018, 4, 1, 4, 523, 0, 0, 0, 0x6ULL, nullptr, OperandInfo192 }, // Inst #1018 = BSELI_B |
| { 1017, 2, 0, 4, 1007, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo7 }, // Inst #1017 = BREAK_MMR6 |
| { 1016, 2, 0, 4, 966, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo7 }, // Inst #1016 = BREAK_MM |
| { 1015, 1, 0, 2, 1007, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo2 }, // Inst #1015 = BREAK16_MMR6 |
| { 1014, 1, 0, 2, 966, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo2 }, // Inst #1014 = BREAK16_MM |
| { 1013, 2, 0, 4, 379, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo7 }, // Inst #1013 = BREAK |
| { 1012, 1, 0, 4, 1518, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo55 }, // Inst #1012 = BPOSGE32_MM |
| { 1011, 1, 0, 4, 1670, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo55 }, // Inst #1011 = BPOSGE32C_MMR3 |
| { 1010, 1, 0, 4, 1367, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo55 }, // Inst #1010 = BPOSGE32 |
| { 1009, 3, 0, 4, 985, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, ImplicitList2, OperandInfo57 }, // Inst #1009 = BOVC_MMR6 |
| { 1008, 3, 0, 4, 931, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, ImplicitList2, OperandInfo57 }, // Inst #1008 = BOVC |
| { 1007, 2, 0, 4, 528, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList2, OperandInfo200 }, // Inst #1007 = BNZ_W |
| { 1006, 2, 0, 4, 528, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList2, OperandInfo197 }, // Inst #1006 = BNZ_V |
| { 1005, 2, 0, 4, 528, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList2, OperandInfo199 }, // Inst #1005 = BNZ_H |
| { 1004, 2, 0, 4, 528, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList2, OperandInfo198 }, // Inst #1004 = BNZ_D |
| { 1003, 2, 0, 4, 528, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList2, OperandInfo197 }, // Inst #1003 = BNZ_B |
| { 1002, 3, 0, 4, 985, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, ImplicitList2, OperandInfo57 }, // Inst #1002 = BNVC_MMR6 |
| { 1001, 3, 0, 4, 931, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, ImplicitList2, OperandInfo57 }, // Inst #1001 = BNVC |
| { 1000, 3, 0, 4, 951, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, ImplicitList2, OperandInfo57 }, // Inst #1000 = BNE_MM |
| { 999, 2, 0, 4, 987, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x36ULL, ImplicitList2, OperandInfo108 }, // Inst #999 = BNEZC_MMR6 |
| { 998, 2, 0, 4, 950, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, ImplicitList2, OperandInfo108 }, // Inst #998 = BNEZC_MM |
| { 997, 2, 0, 4, 1018, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, ImplicitList2, OperandInfo109 }, // Inst #997 = BNEZC64 |
| { 996, 2, 0, 2, 986, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList2, OperandInfo191 }, // Inst #996 = BNEZC16_MMR6 |
| { 995, 2, 0, 4, 932, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, ImplicitList2, OperandInfo108 }, // Inst #995 = BNEZC |
| { 994, 2, 0, 4, 1000, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, ImplicitList3, OperandInfo108 }, // Inst #994 = BNEZALC_MMR6 |
| { 993, 2, 0, 4, 927, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, ImplicitList3, OperandInfo108 }, // Inst #993 = BNEZALC |
| { 992, 2, 0, 2, 949, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList2, OperandInfo191 }, // Inst #992 = BNEZ16_MM |
| { 991, 3, 0, 4, 377, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, ImplicitList2, OperandInfo57 }, // Inst #991 = BNEL |
| { 990, 3, 1, 4, 522, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #990 = BNEG_W |
| { 989, 3, 1, 4, 522, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #989 = BNEG_H |
| { 988, 3, 1, 4, 522, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #988 = BNEG_D |
| { 987, 3, 1, 4, 522, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #987 = BNEG_B |
| { 986, 3, 1, 4, 522, 0, 0, 0, 0x6ULL, nullptr, OperandInfo179 }, // Inst #986 = BNEGI_W |
| { 985, 3, 1, 4, 522, 0, 0, 0, 0x6ULL, nullptr, OperandInfo178 }, // Inst #985 = BNEGI_H |
| { 984, 3, 1, 4, 522, 0, 0, 0, 0x6ULL, nullptr, OperandInfo177 }, // Inst #984 = BNEGI_D |
| { 983, 3, 1, 4, 522, 0, 0, 0, 0x6ULL, nullptr, OperandInfo176 }, // Inst #983 = BNEGI_B |
| { 982, 3, 0, 4, 985, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, ImplicitList2, OperandInfo57 }, // Inst #982 = BNEC_MMR6 |
| { 981, 3, 0, 4, 1017, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, ImplicitList2, OperandInfo106 }, // Inst #981 = BNEC64 |
| { 980, 3, 0, 4, 931, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, ImplicitList2, OperandInfo57 }, // Inst #980 = BNEC |
| { 979, 3, 0, 4, 1009, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, ImplicitList2, OperandInfo106 }, // Inst #979 = BNE64 |
| { 978, 3, 0, 4, 920, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, ImplicitList2, OperandInfo57 }, // Inst #978 = BNE |
| { 977, 4, 1, 4, 524, 0, 0, 0, 0x6ULL, nullptr, OperandInfo196 }, // Inst #977 = BMZ_V |
| { 976, 4, 1, 4, 524, 0, 0, 0, 0x6ULL, nullptr, OperandInfo192 }, // Inst #976 = BMZI_B |
| { 975, 4, 1, 4, 524, 0, 0, 0, 0x6ULL, nullptr, OperandInfo196 }, // Inst #975 = BMNZ_V |
| { 974, 4, 1, 4, 524, 0, 0, 0, 0x6ULL, nullptr, OperandInfo192 }, // Inst #974 = BMNZI_B |
| { 973, 2, 0, 4, 949, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, ImplicitList2, OperandInfo108 }, // Inst #973 = BLTZ_MM |
| { 972, 2, 0, 4, 378, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, ImplicitList2, OperandInfo108 }, // Inst #972 = BLTZL |
| { 971, 2, 0, 4, 987, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, ImplicitList2, OperandInfo108 }, // Inst #971 = BLTZC_MMR6 |
| { 970, 2, 0, 4, 1018, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, ImplicitList2, OperandInfo109 }, // Inst #970 = BLTZC64 |
| { 969, 2, 0, 4, 932, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, ImplicitList2, OperandInfo108 }, // Inst #969 = BLTZC |
| { 968, 2, 0, 4, 958, 0, 1, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, ImplicitList3, OperandInfo108 }, // Inst #968 = BLTZAL_MM |
| { 967, 2, 0, 4, 957, 0, 1, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, ImplicitList3, OperandInfo108 }, // Inst #967 = BLTZALS_MM |
| { 966, 2, 0, 4, 376, 0, 1, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, ImplicitList3, OperandInfo108 }, // Inst #966 = BLTZALL |
| { 965, 2, 0, 4, 1000, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, ImplicitList3, OperandInfo108 }, // Inst #965 = BLTZALC_MMR6 |
| { 964, 2, 0, 4, 927, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, ImplicitList3, OperandInfo108 }, // Inst #964 = BLTZALC |
| { 963, 2, 0, 4, 919, 0, 1, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, ImplicitList3, OperandInfo108 }, // Inst #963 = BLTZAL |
| { 962, 2, 0, 4, 1010, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, ImplicitList2, OperandInfo109 }, // Inst #962 = BLTZ64 |
| { 961, 2, 0, 4, 921, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, ImplicitList2, OperandInfo108 }, // Inst #961 = BLTZ |
| { 960, 3, 0, 4, 985, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, ImplicitList2, OperandInfo57 }, // Inst #960 = BLTUC_MMR6 |
| { 959, 3, 0, 4, 1017, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, ImplicitList2, OperandInfo106 }, // Inst #959 = BLTUC64 |
| { 958, 3, 0, 4, 931, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, ImplicitList2, OperandInfo57 }, // Inst #958 = BLTUC |
| { 957, 3, 0, 4, 985, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, ImplicitList2, OperandInfo57 }, // Inst #957 = BLTC_MMR6 |
| { 956, 3, 0, 4, 1017, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, ImplicitList2, OperandInfo106 }, // Inst #956 = BLTC64 |
| { 955, 3, 0, 4, 931, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, ImplicitList2, OperandInfo57 }, // Inst #955 = BLTC |
| { 954, 2, 0, 4, 949, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, ImplicitList2, OperandInfo108 }, // Inst #954 = BLEZ_MM |
| { 953, 2, 0, 4, 378, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, ImplicitList2, OperandInfo108 }, // Inst #953 = BLEZL |
| { 952, 2, 0, 4, 987, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, ImplicitList2, OperandInfo108 }, // Inst #952 = BLEZC_MMR6 |
| { 951, 2, 0, 4, 1018, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, ImplicitList2, OperandInfo109 }, // Inst #951 = BLEZC64 |
| { 950, 2, 0, 4, 932, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, ImplicitList2, OperandInfo108 }, // Inst #950 = BLEZC |
| { 949, 2, 0, 4, 1000, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, ImplicitList3, OperandInfo108 }, // Inst #949 = BLEZALC_MMR6 |
| { 948, 2, 0, 4, 927, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, ImplicitList3, OperandInfo108 }, // Inst #948 = BLEZALC |
| { 947, 2, 0, 4, 1010, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, ImplicitList2, OperandInfo109 }, // Inst #947 = BLEZ64 |
| { 946, 2, 0, 4, 921, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, ImplicitList2, OperandInfo108 }, // Inst #946 = BLEZ |
| { 945, 2, 1, 4, 784, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo45 }, // Inst #945 = BITSWAP_MMR6 |
| { 944, 2, 1, 4, 730, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, OperandInfo45 }, // Inst #944 = BITSWAP |
| { 943, 2, 1, 4, 1517, 0, 0, 0, 0x6ULL, nullptr, OperandInfo45 }, // Inst #943 = BITREV_MM |
| { 942, 2, 1, 4, 1366, 0, 0, 0, 0x6ULL, nullptr, OperandInfo45 }, // Inst #942 = BITREV |
| { 941, 4, 1, 4, 517, 0, 0, 0, 0x6ULL, nullptr, OperandInfo60 }, // Inst #941 = BINSR_W |
| { 940, 4, 1, 4, 517, 0, 0, 0, 0x6ULL, nullptr, OperandInfo61 }, // Inst #940 = BINSR_H |
| { 939, 4, 1, 4, 517, 0, 0, 0, 0x6ULL, nullptr, OperandInfo59 }, // Inst #939 = BINSR_D |
| { 938, 4, 1, 4, 517, 0, 0, 0, 0x6ULL, nullptr, OperandInfo196 }, // Inst #938 = BINSR_B |
| { 937, 4, 1, 4, 517, 0, 0, 0, 0x6ULL, nullptr, OperandInfo195 }, // Inst #937 = BINSRI_W |
| { 936, 4, 1, 4, 517, 0, 0, 0, 0x6ULL, nullptr, OperandInfo194 }, // Inst #936 = BINSRI_H |
| { 935, 4, 1, 4, 517, 0, 0, 0, 0x6ULL, nullptr, OperandInfo193 }, // Inst #935 = BINSRI_D |
| { 934, 4, 1, 4, 517, 0, 0, 0, 0x6ULL, nullptr, OperandInfo192 }, // Inst #934 = BINSRI_B |
| { 933, 4, 1, 4, 516, 0, 0, 0, 0x6ULL, nullptr, OperandInfo60 }, // Inst #933 = BINSL_W |
| { 932, 4, 1, 4, 516, 0, 0, 0, 0x6ULL, nullptr, OperandInfo61 }, // Inst #932 = BINSL_H |
| { 931, 4, 1, 4, 516, 0, 0, 0, 0x6ULL, nullptr, OperandInfo59 }, // Inst #931 = BINSL_D |
| { 930, 4, 1, 4, 516, 0, 0, 0, 0x6ULL, nullptr, OperandInfo196 }, // Inst #930 = BINSL_B |
| { 929, 4, 1, 4, 516, 0, 0, 0, 0x6ULL, nullptr, OperandInfo195 }, // Inst #929 = BINSLI_W |
| { 928, 4, 1, 4, 516, 0, 0, 0, 0x6ULL, nullptr, OperandInfo194 }, // Inst #928 = BINSLI_H |
| { 927, 4, 1, 4, 516, 0, 0, 0, 0x6ULL, nullptr, OperandInfo193 }, // Inst #927 = BINSLI_D |
| { 926, 4, 1, 4, 516, 0, 0, 0, 0x6ULL, nullptr, OperandInfo192 }, // Inst #926 = BINSLI_B |
| { 925, 2, 0, 4, 949, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, ImplicitList2, OperandInfo108 }, // Inst #925 = BGTZ_MM |
| { 924, 2, 0, 4, 378, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, ImplicitList2, OperandInfo108 }, // Inst #924 = BGTZL |
| { 923, 2, 0, 4, 987, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, ImplicitList2, OperandInfo108 }, // Inst #923 = BGTZC_MMR6 |
| { 922, 2, 0, 4, 1018, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, ImplicitList2, OperandInfo109 }, // Inst #922 = BGTZC64 |
| { 921, 2, 0, 4, 932, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, ImplicitList2, OperandInfo108 }, // Inst #921 = BGTZC |
| { 920, 2, 0, 4, 1000, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, ImplicitList3, OperandInfo108 }, // Inst #920 = BGTZALC_MMR6 |
| { 919, 2, 0, 4, 927, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, ImplicitList3, OperandInfo108 }, // Inst #919 = BGTZALC |
| { 918, 2, 0, 4, 1010, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, ImplicitList2, OperandInfo109 }, // Inst #918 = BGTZ64 |
| { 917, 2, 0, 4, 921, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, ImplicitList2, OperandInfo108 }, // Inst #917 = BGTZ |
| { 916, 2, 0, 4, 949, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, ImplicitList2, OperandInfo108 }, // Inst #916 = BGEZ_MM |
| { 915, 2, 0, 4, 378, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, ImplicitList2, OperandInfo108 }, // Inst #915 = BGEZL |
| { 914, 2, 0, 4, 987, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, ImplicitList2, OperandInfo108 }, // Inst #914 = BGEZC_MMR6 |
| { 913, 2, 0, 4, 1018, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, ImplicitList2, OperandInfo109 }, // Inst #913 = BGEZC64 |
| { 912, 2, 0, 4, 932, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, ImplicitList2, OperandInfo108 }, // Inst #912 = BGEZC |
| { 911, 2, 0, 4, 958, 0, 1, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, ImplicitList3, OperandInfo108 }, // Inst #911 = BGEZAL_MM |
| { 910, 2, 0, 4, 957, 0, 1, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, ImplicitList3, OperandInfo108 }, // Inst #910 = BGEZALS_MM |
| { 909, 2, 0, 4, 376, 0, 1, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, ImplicitList3, OperandInfo108 }, // Inst #909 = BGEZALL |
| { 908, 2, 0, 4, 1000, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, ImplicitList3, OperandInfo108 }, // Inst #908 = BGEZALC_MMR6 |
| { 907, 2, 0, 4, 927, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, ImplicitList3, OperandInfo108 }, // Inst #907 = BGEZALC |
| { 906, 2, 0, 4, 925, 0, 1, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, ImplicitList3, OperandInfo108 }, // Inst #906 = BGEZAL |
| { 905, 2, 0, 4, 1010, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, ImplicitList2, OperandInfo109 }, // Inst #905 = BGEZ64 |
| { 904, 2, 0, 4, 921, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, ImplicitList2, OperandInfo108 }, // Inst #904 = BGEZ |
| { 903, 3, 0, 4, 985, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, ImplicitList2, OperandInfo57 }, // Inst #903 = BGEUC_MMR6 |
| { 902, 3, 0, 4, 1017, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, ImplicitList2, OperandInfo106 }, // Inst #902 = BGEUC64 |
| { 901, 3, 0, 4, 931, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, ImplicitList2, OperandInfo57 }, // Inst #901 = BGEUC |
| { 900, 3, 0, 4, 985, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, ImplicitList2, OperandInfo57 }, // Inst #900 = BGEC_MMR6 |
| { 899, 3, 0, 4, 1017, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, ImplicitList2, OperandInfo106 }, // Inst #899 = BGEC64 |
| { 898, 3, 0, 4, 931, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, ImplicitList2, OperandInfo57 }, // Inst #898 = BGEC |
| { 897, 3, 0, 4, 951, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, ImplicitList2, OperandInfo57 }, // Inst #897 = BEQ_MM |
| { 896, 2, 0, 4, 987, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x36ULL, ImplicitList2, OperandInfo108 }, // Inst #896 = BEQZC_MMR6 |
| { 895, 2, 0, 4, 950, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, ImplicitList2, OperandInfo108 }, // Inst #895 = BEQZC_MM |
| { 894, 2, 0, 4, 1018, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, ImplicitList2, OperandInfo109 }, // Inst #894 = BEQZC64 |
| { 893, 2, 0, 2, 986, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList2, OperandInfo191 }, // Inst #893 = BEQZC16_MMR6 |
| { 892, 2, 0, 4, 932, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, ImplicitList2, OperandInfo108 }, // Inst #892 = BEQZC |
| { 891, 2, 0, 4, 1000, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, ImplicitList3, OperandInfo108 }, // Inst #891 = BEQZALC_MMR6 |
| { 890, 2, 0, 4, 927, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, ImplicitList3, OperandInfo108 }, // Inst #890 = BEQZALC |
| { 889, 2, 0, 2, 949, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList2, OperandInfo191 }, // Inst #889 = BEQZ16_MM |
| { 888, 3, 0, 4, 377, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, ImplicitList2, OperandInfo57 }, // Inst #888 = BEQL |
| { 887, 3, 0, 4, 985, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, ImplicitList2, OperandInfo57 }, // Inst #887 = BEQC_MMR6 |
| { 886, 3, 0, 4, 1017, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, ImplicitList2, OperandInfo106 }, // Inst #886 = BEQC64 |
| { 885, 3, 0, 4, 931, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, ImplicitList2, OperandInfo57 }, // Inst #885 = BEQC |
| { 884, 3, 0, 4, 1009, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, ImplicitList2, OperandInfo106 }, // Inst #884 = BEQ64 |
| { 883, 3, 0, 4, 920, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, ImplicitList2, OperandInfo57 }, // Inst #883 = BEQ |
| { 882, 1, 0, 4, 982, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x16ULL, nullptr, OperandInfo55 }, // Inst #882 = BC_MMR6 |
| { 881, 3, 1, 4, 521, 0, 0, 0, 0x6ULL, nullptr, OperandInfo48 }, // Inst #881 = BCLR_W |
| { 880, 3, 1, 4, 521, 0, 0, 0, 0x6ULL, nullptr, OperandInfo47 }, // Inst #880 = BCLR_H |
| { 879, 3, 1, 4, 521, 0, 0, 0, 0x6ULL, nullptr, OperandInfo46 }, // Inst #879 = BCLR_D |
| { 878, 3, 1, 4, 521, 0, 0, 0, 0x6ULL, nullptr, OperandInfo174 }, // Inst #878 = BCLR_B |
| { 877, 3, 1, 4, 521, 0, 0, 0, 0x6ULL, nullptr, OperandInfo179 }, // Inst #877 = BCLRI_W |
| { 876, 3, 1, 4, 521, 0, 0, 0, 0x6ULL, nullptr, OperandInfo178 }, // Inst #876 = BCLRI_H |
| { 875, 3, 1, 4, 521, 0, 0, 0, 0x6ULL, nullptr, OperandInfo177 }, // Inst #875 = BCLRI_D |
| { 874, 3, 1, 4, 521, 0, 0, 0, 0x6ULL, nullptr, OperandInfo176 }, // Inst #874 = BCLRI_B |
| { 873, 2, 0, 4, 984, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, ImplicitList2, OperandInfo190 }, // Inst #873 = BC2NEZC_MMR6 |
| { 872, 2, 0, 4, 930, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo190 }, // Inst #872 = BC2NEZ |
| { 871, 2, 0, 4, 984, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, ImplicitList2, OperandInfo190 }, // Inst #871 = BC2EQZC_MMR6 |
| { 870, 2, 0, 4, 930, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo190 }, // Inst #870 = BC2EQZ |
| { 869, 2, 0, 4, 948, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x45ULL, ImplicitList2, OperandInfo189 }, // Inst #869 = BC1T_MM |
| { 868, 2, 0, 4, 693, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x45ULL, ImplicitList2, OperandInfo189 }, // Inst #868 = BC1TL |
| { 867, 2, 0, 4, 692, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x45ULL, ImplicitList2, OperandInfo189 }, // Inst #867 = BC1T |
| { 866, 2, 0, 4, 983, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, ImplicitList2, OperandInfo188 }, // Inst #866 = BC1NEZC_MMR6 |
| { 865, 2, 0, 4, 1231, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo188 }, // Inst #865 = BC1NEZ |
| { 864, 2, 0, 4, 947, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x45ULL, ImplicitList2, OperandInfo189 }, // Inst #864 = BC1F_MM |
| { 863, 2, 0, 4, 691, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x45ULL, ImplicitList2, OperandInfo189 }, // Inst #863 = BC1FL |
| { 862, 2, 0, 4, 690, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x45ULL, ImplicitList2, OperandInfo189 }, // Inst #862 = BC1F |
| { 861, 2, 0, 4, 983, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, ImplicitList2, OperandInfo188 }, // Inst #861 = BC1EQZC_MMR6 |
| { 860, 2, 0, 4, 1231, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo188 }, // Inst #860 = BC1EQZ |
| { 859, 1, 0, 2, 982, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList2, OperandInfo55 }, // Inst #859 = BC16_MMR6 |
| { 858, 1, 0, 4, 929, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, OperandInfo55 }, // Inst #858 = BC |
| { 857, 3, 0, 4, 1199, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x2ULL, ImplicitList2, OperandInfo187 }, // Inst #857 = BBIT132 |
| { 856, 3, 0, 4, 1199, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x2ULL, ImplicitList2, OperandInfo187 }, // Inst #856 = BBIT1 |
| { 855, 3, 0, 4, 1199, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x2ULL, ImplicitList2, OperandInfo187 }, // Inst #855 = BBIT032 |
| { 854, 3, 0, 4, 1199, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x2ULL, ImplicitList2, OperandInfo187 }, // Inst #854 = BBIT0 |
| { 853, 4, 1, 4, 1634, 0, 0, 0, 0x6ULL, nullptr, OperandInfo182 }, // Inst #853 = BALIGN_MMR2 |
| { 852, 4, 1, 4, 1470, 0, 0, 0, 0x6ULL, nullptr, OperandInfo182 }, // Inst #852 = BALIGN |
| { 851, 1, 0, 4, 999, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, ImplicitList3, OperandInfo55 }, // Inst #851 = BALC_MMR6 |
| { 850, 1, 0, 4, 926, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, ImplicitList3, OperandInfo55 }, // Inst #850 = BALC |
| { 849, 1, 0, 4, 375, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, ImplicitList3, OperandInfo55 }, // Inst #849 = BAL |
| { 848, 3, 1, 4, 1198, 0, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, OperandInfo71 }, // Inst #848 = BADDu |
| { 847, 1, 0, 2, 945, 0, 1, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList2, OperandInfo55 }, // Inst #847 = B16_MM |
| { 846, 3, 1, 2, 735, 0, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, OperandInfo186 }, // Inst #846 = AndRxRxRy16 |
| { 845, 3, 1, 2, 735, 0, 0, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, OperandInfo131 }, // Inst #845 = AdduRxRyRz16 |
| { 844, 1, 0, 4, 735, 1, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, OperandInfo2 }, // Inst #844 = AddiuSpImmX16 |
| { 843, 1, 0, 2, 735, 1, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, OperandInfo2 }, // Inst #843 = AddiuSpImm16 |
| { 842, 3, 1, 4, 735, 0, 0, 0, 0x0ULL, nullptr, OperandInfo185 }, // Inst #842 = AddiuRxRyOffMemX16 |
| { 841, 3, 1, 4, 735, 0, 0, 0|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, OperandInfo184 }, // Inst #841 = AddiuRxRxImmX16 |
| { 840, 3, 1, 2, 735, 0, 0, 0|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, OperandInfo184 }, // Inst #840 = AddiuRxRxImm16 |
| { 839, 2, 1, 4, 735, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo183 }, // Inst #839 = AddiuRxPcImmX16 |
| { 838, 2, 1, 4, 735, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, OperandInfo183 }, // Inst #838 = AddiuRxImmX16 |
| { 837, 3, 1, 4, 542, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo48 }, // Inst #837 = AVE_U_W |
| { 836, 3, 1, 4, 542, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo47 }, // Inst #836 = AVE_U_H |
| { 835, 3, 1, 4, 542, 0, 0, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, OperandInfo46
|
