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/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|* *|
|* Global Instruction Selector for the Mips target *|
|* *|
|* Automatically generated file, do not edit! *|
|* *|
\*===----------------------------------------------------------------------===*/
#ifdef GET_GLOBALISEL_PREDICATE_BITSET
const unsigned MAX_SUBTARGET_PREDICATES = 44;
using PredicateBitset = llvm::PredicateBitsetImpl<MAX_SUBTARGET_PREDICATES>;
#endif // ifdef GET_GLOBALISEL_PREDICATE_BITSET
#ifdef GET_GLOBALISEL_TEMPORARIES_DECL
mutable MatcherState State;
typedef ComplexRendererFns(MipsInstructionSelector::*ComplexMatcherMemFn)(MachineOperand &) const;
typedef void(MipsInstructionSelector::*CustomRendererFn)(MachineInstrBuilder &, const MachineInstr &, int) const;
const ISelInfoTy<PredicateBitset, ComplexMatcherMemFn, CustomRendererFn> ISelInfo;
static MipsInstructionSelector::ComplexMatcherMemFn ComplexPredicateFns[];
static MipsInstructionSelector::CustomRendererFn CustomRenderers[];
bool testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const override;
bool testImmPredicate_APInt(unsigned PredicateID, const APInt &Imm) const override;
bool testImmPredicate_APFloat(unsigned PredicateID, const APFloat &Imm) const override;
const int64_t *getMatchTable() const override;
bool testMIPredicate_MI(unsigned PredicateID, const MachineInstr &MI, const std::array<const MachineOperand *, 3> &Operands) const override;
#endif // ifdef GET_GLOBALISEL_TEMPORARIES_DECL
#ifdef GET_GLOBALISEL_TEMPORARIES_INIT
, State(0),
ISelInfo(TypeObjects, NumTypeObjects, FeatureBitsets, ComplexPredicateFns, CustomRenderers)
#endif // ifdef GET_GLOBALISEL_TEMPORARIES_INIT
#ifdef GET_GLOBALISEL_IMPL
// Bits for subtarget features that participate in instruction matching.
enum SubtargetFeatureBits : uint8_t {
Feature_HasMips2Bit = 7,
Feature_HasMips3Bit = 17,
Feature_HasMips4_32Bit = 27,
Feature_NotMips4_32Bit = 28,
Feature_HasMips4_32r2Bit = 18,
Feature_HasMips32Bit = 3,
Feature_HasMips32r2Bit = 6,
Feature_HasMips32r6Bit = 29,
Feature_NotMips32r6Bit = 4,
Feature_IsGP64bitBit = 22,
Feature_IsPTR64bitBit = 24,
Feature_HasMips64Bit = 25,
Feature_HasMips64r2Bit = 23,
Feature_HasMips64r6Bit = 30,
Feature_NotMips64r6Bit = 5,
Feature_InMips16ModeBit = 31,
Feature_NotInMips16ModeBit = 0,
Feature_HasCnMipsBit = 26,
Feature_NotCnMipsBit = 8,
Feature_IsSym32Bit = 38,
Feature_IsSym64Bit = 39,
Feature_IsN64Bit = 40,
Feature_RelocNotPICBit = 9,
Feature_RelocPICBit = 37,
Feature_NoNaNsFPMathBit = 21,
Feature_UseAbsBit = 14,
Feature_HasStdEncBit = 1,
Feature_NotDSPBit = 11,
Feature_InMicroMipsBit = 35,
Feature_NotInMicroMipsBit = 2,
Feature_IsLEBit = 42,
Feature_IsBEBit = 43,
Feature_IsNotNaClBit = 19,
Feature_HasEVABit = 36,
Feature_HasMSABit = 34,
Feature_HasMadd4Bit = 20,
Feature_UseIndirectJumpsHazardBit = 12,
Feature_NoIndirectJumpGuardsBit = 10,
Feature_AllowFPOpFusionBit = 41,
Feature_IsFP64bitBit = 16,
Feature_NotFP64bitBit = 15,
Feature_IsNotSoftFloatBit = 13,
Feature_HasDSPBit = 32,
Feature_HasDSPR2Bit = 33,
};
PredicateBitset MipsInstructionSelector::
computeAvailableModuleFeatures(const MipsSubtarget *Subtarget) const {
PredicateBitset Features;
if (Subtarget->hasMips2())
Features.set(Feature_HasMips2Bit);
if (Subtarget->hasMips3())
Features.set(Feature_HasMips3Bit);
if (Subtarget->hasMips4_32())
Features.set(Feature_HasMips4_32Bit);
if (!Subtarget->hasMips4_32())
Features.set(Feature_NotMips4_32Bit);
if (Subtarget->hasMips4_32r2())
Features.set(Feature_HasMips4_32r2Bit);
if (Subtarget->hasMips32())
Features.set(Feature_HasMips32Bit);
if (Subtarget->hasMips32r2())
Features.set(Feature_HasMips32r2Bit);
if (Subtarget->hasMips32r6())
Features.set(Feature_HasMips32r6Bit);
if (!Subtarget->hasMips32r6())
Features.set(Feature_NotMips32r6Bit);
if (Subtarget->isGP64bit())
Features.set(Feature_IsGP64bitBit);
if (Subtarget->isABI_N64())
Features.set(Feature_IsPTR64bitBit);
if (Subtarget->hasMips64())
Features.set(Feature_HasMips64Bit);
if (Subtarget->hasMips64r2())
Features.set(Feature_HasMips64r2Bit);
if (Subtarget->hasMips64r6())
Features.set(Feature_HasMips64r6Bit);
if (!Subtarget->hasMips64r6())
Features.set(Feature_NotMips64r6Bit);
if (Subtarget->inMips16Mode())
Features.set(Feature_InMips16ModeBit);
if (!Subtarget->inMips16Mode())
Features.set(Feature_NotInMips16ModeBit);
if (Subtarget->hasCnMips())
Features.set(Feature_HasCnMipsBit);
if (!Subtarget->hasCnMips())
Features.set(Feature_NotCnMipsBit);
if (Subtarget->hasSym32())
Features.set(Feature_IsSym32Bit);
if (!Subtarget->hasSym32())
Features.set(Feature_IsSym64Bit);
if (Subtarget->isABI_N64())
Features.set(Feature_IsN64Bit);
if (!TM.isPositionIndependent())
Features.set(Feature_RelocNotPICBit);
if (TM.isPositionIndependent())
Features.set(Feature_RelocPICBit);
if (TM.Options.NoNaNsFPMath)
Features.set(Feature_NoNaNsFPMathBit);
if (Subtarget->inAbs2008Mode() ||TM.Options.NoNaNsFPMath)
Features.set(Feature_UseAbsBit);
if (Subtarget->hasStandardEncoding())
Features.set(Feature_HasStdEncBit);
if (!Subtarget->hasDSP())
Features.set(Feature_NotDSPBit);
if (Subtarget->inMicroMipsMode())
Features.set(Feature_InMicroMipsBit);
if (!Subtarget->inMicroMipsMode())
Features.set(Feature_NotInMicroMipsBit);
if (Subtarget->isLittle())
Features.set(Feature_IsLEBit);
if (!Subtarget->isLittle())
Features.set(Feature_IsBEBit);
if (!Subtarget->isTargetNaCl())
Features.set(Feature_IsNotNaClBit);
if (Subtarget->hasEVA())
Features.set(Feature_HasEVABit);
if (Subtarget->hasMSA())
Features.set(Feature_HasMSABit);
if (!Subtarget->disableMadd4())
Features.set(Feature_HasMadd4Bit);
if (Subtarget->useIndirectJumpsHazard())
Features.set(Feature_UseIndirectJumpsHazardBit);
if (!Subtarget->useIndirectJumpsHazard())
Features.set(Feature_NoIndirectJumpGuardsBit);
if (TM.Options.AllowFPOpFusion == FPOpFusion::Fast)
Features.set(Feature_AllowFPOpFusionBit);
if (Subtarget->isFP64bit())
Features.set(Feature_IsFP64bitBit);
if (!Subtarget->isFP64bit())
Features.set(Feature_NotFP64bitBit);
if (!Subtarget->useSoftFloat())
Features.set(Feature_IsNotSoftFloatBit);
if (Subtarget->hasDSP())
Features.set(Feature_HasDSPBit);
if (Subtarget->hasDSPR2())
Features.set(Feature_HasDSPR2Bit);
return Features;
}
void MipsInstructionSelector::setupGeneratedPerFunctionState(MachineFunction &MF) {
AvailableFunctionFeatures = computeAvailableFunctionFeatures((const MipsSubtarget *)&MF.getSubtarget(), &MF);
}
PredicateBitset MipsInstructionSelector::
computeAvailableFunctionFeatures(const MipsSubtarget *Subtarget, const MachineFunction *MF) const {
PredicateBitset Features;
return Features;
}
// LLT Objects.
enum {
GILLT_s16,
GILLT_s32,
GILLT_s64,
GILLT_v2s16,
GILLT_v2s64,
GILLT_v4s8,
GILLT_v4s32,
GILLT_v8s16,
GILLT_v16s8,
};
const static size_t NumTypeObjects = 9;
const static LLT TypeObjects[] = {
LLT::scalar(16),
LLT::scalar(32),
LLT::scalar(64),
LLT::vector(ElementCount::getFixed(2), 16),
LLT::vector(ElementCount::getFixed(2), 64),
LLT::vector(ElementCount::getFixed(4), 8),
LLT::vector(ElementCount::getFixed(4), 32),
LLT::vector(ElementCount::getFixed(8), 16),
LLT::vector(ElementCount::getFixed(16), 8),
};
// Feature bitsets.
enum {
GIFBS_Invalid,
GIFBS_HasCnMips,
GIFBS_HasDSP,
GIFBS_HasDSPR2,
GIFBS_HasMSA,
GIFBS_InMicroMips,
GIFBS_InMips16Mode,
GIFBS_IsFP64bit,
GIFBS_NotFP64bit,
GIFBS_HasDSP_InMicroMips,
GIFBS_HasDSP_NotInMicroMips,
GIFBS_HasDSPR2_InMicroMips,
GIFBS_HasMSA_HasStdEnc,
GIFBS_HasMSA_IsBE,
GIFBS_HasMSA_IsLE,
GIFBS_HasMips32r6_HasStdEnc,
GIFBS_HasMips32r6_InMicroMips,
GIFBS_HasMips64r2_HasStdEnc,
GIFBS_HasMips64r6_HasStdEnc,
GIFBS_HasStdEnc_IsNotSoftFloat,
GIFBS_HasStdEnc_NotInMicroMips,
GIFBS_HasStdEnc_NotMips4_32,
GIFBS_InMicroMips_IsFP64bit,
GIFBS_InMicroMips_IsNotSoftFloat,
GIFBS_InMicroMips_NotFP64bit,
GIFBS_InMicroMips_NotMips32r6,
GIFBS_IsGP64bit_NotInMips16Mode,
GIFBS_AllowFPOpFusion_HasMSA_HasStdEnc,
GIFBS_HasMSA_HasMips64_HasStdEnc,
GIFBS_HasMips3_HasStdEnc_IsGP64bit,
GIFBS_HasMips3_HasStdEnc_NotInMicroMips,
GIFBS_HasMips32r2_HasStdEnc_NotInMicroMips,
GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips,
GIFBS_HasMips32r6_InMicroMips_IsNotSoftFloat,
GIFBS_HasMips64r2_HasStdEnc_NotInMicroMips,
GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips,
GIFBS_HasStdEnc_IsFP64bit_NotInMicroMips,
GIFBS_HasStdEnc_IsFP64bit_NotMips4_32,
GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
GIFBS_HasStdEnc_NotFP64bit_NotInMicroMips,
GIFBS_HasStdEnc_NotFP64bit_NotMips4_32,
GIFBS_HasStdEnc_NotInMicroMips_RelocNotPIC,
GIFBS_InMicroMips_IsFP64bit_IsNotSoftFloat,
GIFBS_InMicroMips_IsNotSoftFloat_NotFP64bit,
GIFBS_InMicroMips_IsNotSoftFloat_UseAbs,
GIFBS_InMicroMips_NotFP64bit_NotMips32r6,
GIFBS_InMicroMips_NotMips32r6_RelocNotPIC,
GIFBS_InMicroMips_NotMips32r6_RelocPIC,
GIFBS_IsFP64bit_IsNotSoftFloat_NotInMips16Mode,
GIFBS_IsNotSoftFloat_NotFP64bit_NotInMips16Mode,
GIFBS_HasMips2_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
GIFBS_HasMips3_HasStdEnc_IsGP64bit_NotInMicroMips,
GIFBS_HasMips3_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
GIFBS_HasMips32r6_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
GIFBS_HasMips4_32_HasStdEnc_NotMips32r6_NotMips64r6,
GIFBS_HasMips64r2_HasStdEnc_IsGP64bit_NotInMicroMips,
GIFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips,
GIFBS_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips,
GIFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips_UseAbs,
GIFBS_HasMips2_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips,
GIFBS_HasMips2_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips,
GIFBS_HasMips32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6,
GIFBS_HasMips4_32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6,
GIFBS_HasMips64_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips64r6,
GIFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips_UseAbs,
GIFBS_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips_UseAbs,
GIFBS_HasMadd4_InMicroMips_InMicroMips_NoNaNsFPMath_NotMips32r6_NotMips32r6,
GIFBS_HasMips4_32_HasStdEnc_IsFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
GIFBS_HasMips4_32_HasStdEnc_IsGP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
GIFBS_HasMips4_32_HasStdEnc_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6,
GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6,
GIFBS_HasMadd4_InMicroMips_InMicroMips_NoNaNsFPMath_NotFP64bit_NotMips32r6_NotMips32r6,
GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips_NotMips32r6_NotMips64r6,
GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsFP64bit_NoNaNsFPMath_NotInMicroMips_NotMips32r6_NotMips64r6,
GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_IsNotSoftFloat_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
GIFBS_HasMadd4_HasMips4_32r2_HasStdEnc_NoNaNsFPMath_NotFP64bit_NotInMicroMips_NotMips32r6_NotMips64r6,
};
const static PredicateBitset FeatureBitsets[] {
{}, // GIFBS_Invalid
{Feature_HasCnMipsBit, },
{Feature_HasDSPBit, },
{Feature_HasDSPR2Bit, },
{Feature_HasMSABit, },
{Feature_InMicroMipsBit, },
{Feature_InMips16ModeBit, },
{Feature_IsFP64bitBit, },
{Feature_NotFP64bitBit, },
{Feature_HasDSPBit, Feature_InMicroMipsBit, },
{Feature_HasDSPBit, Feature_NotInMicroMipsBit, },
{Feature_HasDSPR2Bit, Feature_InMicroMipsBit, },
{Feature_HasMSABit, Feature_HasStdEncBit, },
{Feature_HasMSABit, Feature_IsBEBit, },
{Feature_HasMSABit, Feature_IsLEBit, },
{Feature_HasMips32r6Bit, Feature_HasStdEncBit, },
{Feature_HasMips32r6Bit, Feature_InMicroMipsBit, },
{Feature_HasMips64r2Bit, Feature_HasStdEncBit, },
{Feature_HasMips64r6Bit, Feature_HasStdEncBit, },
{Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, },
{Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
{Feature_HasStdEncBit, Feature_NotMips4_32Bit, },
{Feature_InMicroMipsBit, Feature_IsFP64bitBit, },
{Feature_InMicroMipsBit, Feature_IsNotSoftFloatBit, },
{Feature_InMicroMipsBit, Feature_NotFP64bitBit, },
{Feature_InMicroMipsBit, Feature_NotMips32r6Bit, },
{Feature_IsGP64bitBit, Feature_NotInMips16ModeBit, },
{Feature_AllowFPOpFusionBit, Feature_HasMSABit, Feature_HasStdEncBit, },
{Feature_HasMSABit, Feature_HasMips64Bit, Feature_HasStdEncBit, },
{Feature_HasMips3Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, },
{Feature_HasMips3Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
{Feature_HasMips32r2Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
{Feature_HasMips32r6Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
{Feature_HasMips32r6Bit, Feature_InMicroMipsBit, Feature_IsNotSoftFloatBit, },
{Feature_HasMips64r2Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
{Feature_HasMips64r6Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
{Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NotInMicroMipsBit, },
{Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NotMips4_32Bit, },
{Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
{Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, },
{Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_NotMips4_32Bit, },
{Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_RelocNotPICBit, },
{Feature_InMicroMipsBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, },
{Feature_InMicroMipsBit, Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, },
{Feature_InMicroMipsBit, Feature_IsNotSoftFloatBit, Feature_UseAbsBit, },
{Feature_InMicroMipsBit, Feature_NotFP64bitBit, Feature_NotMips32r6Bit, },
{Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_RelocNotPICBit, },
{Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_RelocPICBit, },
{Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMips16ModeBit, },
{Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, Feature_NotInMips16ModeBit, },
{Feature_HasMips2Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
{Feature_HasMips3Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_NotInMicroMipsBit, },
{Feature_HasMips3Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
{Feature_HasMips32r6Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
{Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
{Feature_HasMips64r2Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_NotInMicroMipsBit, },
{Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
{Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, },
{Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_UseAbsBit, },
{Feature_HasMips2Bit, Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
{Feature_HasMips2Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, },
{Feature_HasMips32Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
{Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
{Feature_HasMips64Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips64r6Bit, },
{Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_UseAbsBit, },
{Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, Feature_UseAbsBit, },
{Feature_HasMadd4Bit, Feature_InMicroMipsBit, Feature_InMicroMipsBit, Feature_NoNaNsFPMathBit, Feature_NotMips32r6Bit, Feature_NotMips32r6Bit, },
{Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
{Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
{Feature_HasMips4_32Bit, Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
{Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
{Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_NoNaNsFPMathBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
{Feature_HasMadd4Bit, Feature_InMicroMipsBit, Feature_InMicroMipsBit, Feature_NoNaNsFPMathBit, Feature_NotFP64bitBit, Feature_NotMips32r6Bit, Feature_NotMips32r6Bit, },
{Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
{Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NoNaNsFPMathBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
{Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
{Feature_HasMadd4Bit, Feature_HasMips4_32r2Bit, Feature_HasStdEncBit, Feature_NoNaNsFPMathBit, Feature_NotFP64bitBit, Feature_NotInMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
};
// ComplexPattern predicates.
enum {
GICP_Invalid,
};
// See constructor for table contents
// PatFrag predicates.
enum {
GIPFP_I64_Predicate_immLi16 = GIPFP_I64_Invalid + 1,
GIPFP_I64_Predicate_immSExt10,
GIPFP_I64_Predicate_immSExt6,
GIPFP_I64_Predicate_immSExtAddiur2,
GIPFP_I64_Predicate_immSExtAddius5,
GIPFP_I64_Predicate_immZExt1,
GIPFP_I64_Predicate_immZExt10,
GIPFP_I64_Predicate_immZExt1Ptr,
GIPFP_I64_Predicate_immZExt2,
GIPFP_I64_Predicate_immZExt2Lsa,
GIPFP_I64_Predicate_immZExt2Ptr,
GIPFP_I64_Predicate_immZExt2Shift,
GIPFP_I64_Predicate_immZExt3,
GIPFP_I64_Predicate_immZExt3Ptr,
GIPFP_I64_Predicate_immZExt4,
GIPFP_I64_Predicate_immZExt4Ptr,
GIPFP_I64_Predicate_immZExt5,
GIPFP_I64_Predicate_immZExt5_64,
GIPFP_I64_Predicate_immZExt6,
GIPFP_I64_Predicate_immZExt8,
GIPFP_I64_Predicate_immZExtAndi16,
GIPFP_I64_Predicate_immi32Cst15,
GIPFP_I64_Predicate_immi32Cst31,
GIPFP_I64_Predicate_immi32Cst7,
GIPFP_I64_Predicate_timmSExt6,
GIPFP_I64_Predicate_timmZExt1,
GIPFP_I64_Predicate_timmZExt10,
GIPFP_I64_Predicate_timmZExt1Ptr,
GIPFP_I64_Predicate_timmZExt2,
GIPFP_I64_Predicate_timmZExt2Ptr,
GIPFP_I64_Predicate_timmZExt3,
GIPFP_I64_Predicate_timmZExt3Ptr,
GIPFP_I64_Predicate_timmZExt4,
GIPFP_I64_Predicate_timmZExt4Ptr,
GIPFP_I64_Predicate_timmZExt5,
GIPFP_I64_Predicate_timmZExt6,
GIPFP_I64_Predicate_timmZExt8,
};
bool MipsInstructionSelector::testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const {
switch (PredicateID) {
case GIPFP_I64_Predicate_immLi16: {
return Imm >= -1 && Imm <= 126;
llvm_unreachable("ImmediateCode should have returned");
return false;
}
case GIPFP_I64_Predicate_immSExt10: {
return isInt<10>(Imm);
llvm_unreachable("ImmediateCode should have returned");
return false;
}
case GIPFP_I64_Predicate_immSExt6: {
return isInt<6>(Imm);
llvm_unreachable("ImmediateCode should have returned");
return false;
}
case GIPFP_I64_Predicate_immSExtAddiur2: {
return Imm == 1 || Imm == -1 ||
((Imm % 4 == 0) &&
Imm < 28 && Imm > 0);
llvm_unreachable("ImmediateCode should have returned");
return false;
}
case GIPFP_I64_Predicate_immSExtAddius5: {
return Imm >= -8 && Imm <= 7;
llvm_unreachable("ImmediateCode should have returned");
return false;
}
case GIPFP_I64_Predicate_immZExt1: {
return isUInt<1>(Imm);
llvm_unreachable("ImmediateCode should have returned");
return false;
}
case GIPFP_I64_Predicate_immZExt10: {
return isUInt<10>(Imm);
llvm_unreachable("ImmediateCode should have returned");
return false;
}
case GIPFP_I64_Predicate_immZExt1Ptr: {
return isUInt<1>(Imm);
llvm_unreachable("ImmediateCode should have returned");
return false;
}
case GIPFP_I64_Predicate_immZExt2: {
return isUInt<2>(Imm);
llvm_unreachable("ImmediateCode should have returned");
return false;
}
case GIPFP_I64_Predicate_immZExt2Lsa: {
return isUInt<2>(Imm - 1);
llvm_unreachable("ImmediateCode should have returned");
return false;
}
case GIPFP_I64_Predicate_immZExt2Ptr: {
return isUInt<2>(Imm);
llvm_unreachable("ImmediateCode should have returned");
return false;
}
case GIPFP_I64_Predicate_immZExt2Shift: {
return Imm >= 1 && Imm <= 8;
llvm_unreachable("ImmediateCode should have returned");
return false;
}
case GIPFP_I64_Predicate_immZExt3: {
return isUInt<3>(Imm);
llvm_unreachable("ImmediateCode should have returned");
return false;
}
case GIPFP_I64_Predicate_immZExt3Ptr: {
return isUInt<3>(Imm);
llvm_unreachable("ImmediateCode should have returned");
return false;
}
case GIPFP_I64_Predicate_immZExt4: {
return isUInt<4>(Imm);
llvm_unreachable("ImmediateCode should have returned");
return false;
}
case GIPFP_I64_Predicate_immZExt4Ptr: {
return isUInt<4>(Imm);
llvm_unreachable("ImmediateCode should have returned");
return false;
}
case GIPFP_I64_Predicate_immZExt5: {
return Imm == (Imm & 0x1f);
llvm_unreachable("ImmediateCode should have returned");
return false;
}
case GIPFP_I64_Predicate_immZExt5_64: {
return Imm == (Imm & 0x1f);
llvm_unreachable("ImmediateCode should have returned");
return false;
}
case GIPFP_I64_Predicate_immZExt6: {
return Imm == (Imm & 0x3f);
llvm_unreachable("ImmediateCode should have returned");
return false;
}
case GIPFP_I64_Predicate_immZExt8: {
return isUInt<8>(Imm);
llvm_unreachable("ImmediateCode should have returned");
return false;
}
case GIPFP_I64_Predicate_immZExtAndi16: {
return (Imm == 128 || (Imm >= 1 && Imm <= 4) || Imm == 7 || Imm == 8 ||
Imm == 15 || Imm == 16 || Imm == 31 || Imm == 32 || Imm == 63 ||
Imm == 64 || Imm == 255 || Imm == 32768 || Imm == 65535 );
llvm_unreachable("ImmediateCode should have returned");
return false;
}
case GIPFP_I64_Predicate_immi32Cst15: {
return isUInt<32>(Imm) && Imm == 15;
llvm_unreachable("ImmediateCode should have returned");
return false;
}
case GIPFP_I64_Predicate_immi32Cst31: {
return isUInt<32>(Imm) && Imm == 31;
llvm_unreachable("ImmediateCode should have returned");
return false;
}
case GIPFP_I64_Predicate_immi32Cst7: {
return isUInt<32>(Imm) && Imm == 7;
llvm_unreachable("ImmediateCode should have returned");
return false;
}
case GIPFP_I64_Predicate_timmSExt6: {
return isInt<6>(Imm);
llvm_unreachable("ImmediateCode should have returned");
return false;
}
case GIPFP_I64_Predicate_timmZExt1: {
return isUInt<1>(Imm);
llvm_unreachable("ImmediateCode should have returned");
return false;
}
case GIPFP_I64_Predicate_timmZExt10: {
return isUInt<10>(Imm);
llvm_unreachable("ImmediateCode should have returned");
return false;
}
case GIPFP_I64_Predicate_timmZExt1Ptr: {
return isUInt<1>(Imm);
llvm_unreachable("ImmediateCode should have returned");
return false;
}
case GIPFP_I64_Predicate_timmZExt2: {
return isUInt<2>(Imm);
llvm_unreachable("ImmediateCode should have returned");
return false;
}
case GIPFP_I64_Predicate_timmZExt2Ptr: {
return isUInt<2>(Imm);
llvm_unreachable("ImmediateCode should have returned");
return false;
}
case GIPFP_I64_Predicate_timmZExt3: {
return isUInt<3>(Imm);
llvm_unreachable("ImmediateCode should have returned");
return false;
}
case GIPFP_I64_Predicate_timmZExt3Ptr: {
return isUInt<3>(Imm);
llvm_unreachable("ImmediateCode should have returned");
return false;
}
case GIPFP_I64_Predicate_timmZExt4: {
return isUInt<4>(Imm);
llvm_unreachable("ImmediateCode should have returned");
return false;
}
case GIPFP_I64_Predicate_timmZExt4Ptr: {
return isUInt<4>(Imm);
llvm_unreachable("ImmediateCode should have returned");
return false;
}
case GIPFP_I64_Predicate_timmZExt5: {
return Imm == (Imm & 0x1f);
llvm_unreachable("ImmediateCode should have returned");
return false;
}
case GIPFP_I64_Predicate_timmZExt6: {
return Imm == (Imm & 0x3f);
llvm_unreachable("ImmediateCode should have returned");
return false;
}
case GIPFP_I64_Predicate_timmZExt8: {
return isUInt<8>(Imm);
llvm_unreachable("ImmediateCode should have returned");
return false;
}
}
llvm_unreachable("Unknown predicate");
return false;
}
bool MipsInstructionSelector::testImmPredicate_APFloat(unsigned PredicateID, const APFloat & Imm) const {
llvm_unreachable("Unknown predicate");
return false;
}
// PatFrag predicates.
enum {
GIPFP_APInt_Predicate_imm32SExt16 = GIPFP_APInt_Invalid + 1,
GIPFP_APInt_Predicate_imm32ZExt16,
};
bool MipsInstructionSelector::testImmPredicate_APInt(unsigned PredicateID, const APInt & Imm) const {
switch (PredicateID) {
case GIPFP_APInt_Predicate_imm32SExt16: {
return isInt<16>(Imm.getSExtValue());
llvm_unreachable("ImmediateCode should have returned");
return false;
}
case GIPFP_APInt_Predicate_imm32ZExt16: {
return (uint32_t)Imm.getZExtValue() == (unsigned short)Imm.getZExtValue();
llvm_unreachable("ImmediateCode should have returned");
return false;
}
}
llvm_unreachable("Unknown predicate");
return false;
}
bool MipsInstructionSelector::testMIPredicate_MI(unsigned PredicateID, const MachineInstr & MI, const std::array<const MachineOperand *, 3> &Operands) const {
const MachineFunction &MF = *MI.getParent()->getParent();
const MachineRegisterInfo &MRI = MF.getRegInfo();
(void)MRI;
llvm_unreachable("Unknown predicate");
return false;
}
MipsInstructionSelector::ComplexMatcherMemFn
MipsInstructionSelector::ComplexPredicateFns[] = {
nullptr, // GICP_Invalid
};
// Custom renderers.
enum {
GICR_Invalid,
};
MipsInstructionSelector::CustomRendererFn
MipsInstructionSelector::CustomRenderers[] = {
nullptr, // GICR_Invalid
};
bool MipsInstructionSelector::selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const {
MachineFunction &MF = *I.getParent()->getParent();
MachineRegisterInfo &MRI = MF.getRegInfo();
const PredicateBitset AvailableFeatures = getAvailableFeatures();
NewMIVector OutMIs;
State.MIs.clear();
State.MIs.push_back(&I);
if (executeMatchTable(*this, OutMIs, State, ISelInfo, getMatchTable(), TII, MRI, TRI, RBI, AvailableFeatures, CoverageInfo)) {
return true;
}
return false;
}
const int64_t *MipsInstructionSelector::getMatchTable() const {
constexpr static int64_t MatchTable0[] = {
GIM_SwitchOpcode, /*MI*/0, /*[*/46, 215, /*)*//*default:*//*Label 58*/ 60447,
/*TargetOpcode::G_ADD*//*Label 0*/ 174,
/*TargetOpcode::G_SUB*//*Label 1*/ 1394,
/*TargetOpcode::G_MUL*//*Label 2*/ 2006,
/*TargetOpcode::G_SDIV*//*Label 3*/ 2382,
/*TargetOpcode::G_UDIV*//*Label 4*/ 2603,
/*TargetOpcode::G_SREM*//*Label 5*/ 2824,
/*TargetOpcode::G_UREM*//*Label 6*/ 3045, 0, 0,
/*TargetOpcode::G_AND*//*Label 7*/ 3266,
/*TargetOpcode::G_OR*//*Label 8*/ 3753,
/*TargetOpcode::G_XOR*//*Label 9*/ 4098, 0, 0, 0, 0, 0, 0, 0,
/*TargetOpcode::G_MERGE_VALUES*//*Label 10*/ 4938,
/*TargetOpcode::G_BUILD_VECTOR*//*Label 11*/ 5003, 0, 0, 0, 0,
/*TargetOpcode::G_BITCAST*//*Label 12*/ 5364, 0, 0, 0, 0, 0, 0, 0,
/*TargetOpcode::G_LOAD*//*Label 13*/ 9017,
/*TargetOpcode::G_SEXTLOAD*//*Label 14*/ 9083,
/*TargetOpcode::G_ZEXTLOAD*//*Label 15*/ 9149, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/*TargetOpcode::G_INTRINSIC*//*Label 16*/ 9215,
/*TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS*//*Label 17*/ 25490,
/*TargetOpcode::G_ANYEXT*//*Label 18*/ 30474,
/*TargetOpcode::G_TRUNC*//*Label 19*/ 30540,
/*TargetOpcode::G_CONSTANT*//*Label 20*/ 30603, 0, 0, 0,
/*TargetOpcode::G_SEXT*//*Label 21*/ 30663, 0,
/*TargetOpcode::G_ZEXT*//*Label 22*/ 31921,
/*TargetOpcode::G_SHL*//*Label 23*/ 32115,
/*TargetOpcode::G_LSHR*//*Label 24*/ 33868,
/*TargetOpcode::G_ASHR*//*Label 25*/ 35621, 0, 0,
/*TargetOpcode::G_ROTR*//*Label 26*/ 37331, 0,
/*TargetOpcode::G_ICMP*//*Label 27*/ 37594,
/*TargetOpcode::G_FCMP*//*Label 28*/ 40098,
/*TargetOpcode::G_SELECT*//*Label 29*/ 41818, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/*TargetOpcode::G_UMULH*//*Label 30*/ 54098,
/*TargetOpcode::G_SMULH*//*Label 31*/ 54185, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/*TargetOpcode::G_FADD*//*Label 32*/ 54272,
/*TargetOpcode::G_FSUB*//*Label 33*/ 55151,
/*TargetOpcode::G_FMUL*//*Label 34*/ 55727,
/*TargetOpcode::G_FMA*//*Label 35*/ 56164, 0,
/*TargetOpcode::G_FDIV*//*Label 36*/ 56254, 0, 0, 0, 0,
/*TargetOpcode::G_FEXP2*//*Label 37*/ 56505, 0,
/*TargetOpcode::G_FLOG2*//*Label 38*/ 56563, 0,
/*TargetOpcode::G_FNEG*//*Label 39*/ 56621,
/*TargetOpcode::G_FPEXT*//*Label 40*/ 57917,
/*TargetOpcode::G_FPTRUNC*//*Label 41*/ 58066,
/*TargetOpcode::G_FPTOSI*//*Label 42*/ 58194,
/*TargetOpcode::G_FPTOUI*//*Label 43*/ 58252,
/*TargetOpcode::G_SITOFP*//*Label 44*/ 58310,
/*TargetOpcode::G_UITOFP*//*Label 45*/ 58518,
/*TargetOpcode::G_FABS*//*Label 46*/ 58576, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
/*TargetOpcode::G_SMIN*//*Label 47*/ 58759,
/*TargetOpcode::G_SMAX*//*Label 48*/ 58899,
/*TargetOpcode::G_UMIN*//*Label 49*/ 59039,
/*TargetOpcode::G_UMAX*//*Label 50*/ 59179, 0, 0, 0,
/*TargetOpcode::G_BR*//*Label 51*/ 59319, 0, 0,
/*TargetOpcode::G_EXTRACT_VECTOR_ELT*//*Label 52*/ 59404, 0, 0, 0,
/*TargetOpcode::G_CTLZ*//*Label 53*/ 59460, 0,
/*TargetOpcode::G_CTPOP*//*Label 54*/ 59895,
/*TargetOpcode::G_BSWAP*//*Label 55*/ 60054, 0, 0, 0, 0,
/*TargetOpcode::G_FSQRT*//*Label 56*/ 60206, 0,
/*TargetOpcode::G_FRINT*//*Label 57*/ 60389,
// Label 0: @174
GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 67*/ 1393,
/*GILLT_s32*//*Label 59*/ 188,
/*GILLT_s64*//*Label 60*/ 580,
/*GILLT_v2s16*//*Label 61*/ 743,
/*GILLT_v2s64*//*Label 62*/ 770,
/*GILLT_v4s8*//*Label 63*/ 919,
/*GILLT_v4s32*//*Label 64*/ 946,
/*GILLT_v8s16*//*Label 65*/ 1095,
/*GILLT_v16s8*//*Label 66*/ 1244,
// Label 59: @188
GIM_Try, /*On fail goto*//*Label 68*/ 579,
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
GIM_Try, /*On fail goto*//*Label 69*/ 266, // Rule ID 2348 //
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL,
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_immZExt2Lsa,
// MIs[2] Operand 1
// No operand predicates
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
GIM_CheckIsSafeToFold, /*InsnID*/1,
GIM_CheckIsSafeToFold, /*InsnID*/2,
// (add:{ *:[i32] } (shl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt2Lsa>>:$sa), GPR32Opnd:{ *:[i32] }:$rt) => (LSA:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$sa)
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::LSA,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sa
GIR_EraseFromParent, /*InsnID*/0,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 2348,
GIR_Done,
// Label 69: @266
GIM_Try, /*On fail goto*//*Label 70*/ 334, // Rule ID 822 //
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL,
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_immZExt2Lsa,
// MIs[2] Operand 1
// No operand predicates
GIM_CheckIsSafeToFold, /*InsnID*/1,
GIM_CheckIsSafeToFold, /*InsnID*/2,
// (add:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rt, (shl:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt2Lsa>>:$sa)) => (LSA:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt, (imm:{ *:[i32] }):$sa)
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::LSA,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sa
GIR_EraseFromParent, /*InsnID*/0,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 822,
GIR_Done,
// Label 70: @334
GIM_Try, /*On fail goto*//*Label 71*/ 377, // Rule ID 40 //
GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
GIM_CheckAPIntImmPredicate, /*MI*/1, /*Predicate*/GIPFP_APInt_Predicate_imm32SExt16,
// MIs[1] Operand 1
// No operand predicates
GIM_CheckIsSafeToFold, /*InsnID*/1,
// (add:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_imm32SExt16>>:$imm16) => (ADDiu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$imm16)
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDiu,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm16
GIR_EraseFromParent, /*InsnID*/0,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 40,
GIR_Done,
// Label 71: @377
GIM_Try, /*On fail goto*//*Label 72*/ 420, // Rule ID 2123 //
GIM_CheckFeatures, GIFBS_InMicroMips,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immSExtAddiur2,
// MIs[1] Operand 1
// No operand predicates
GIM_CheckIsSafeToFold, /*InsnID*/1,
// (add:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immSExtAddiur2>>:$imm) => (ADDIUR2_MM:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immSExtAddiur2>>:$imm)
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDIUR2_MM,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
GIR_EraseFromParent, /*InsnID*/0,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 2123,
GIR_Done,
// Label 72: @420
GIM_Try, /*On fail goto*//*Label 73*/ 463, // Rule ID 2124 //
GIM_CheckFeatures, GIFBS_InMicroMips,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immSExtAddius5,
// MIs[1] Operand 1
// No operand predicates
GIM_CheckIsSafeToFold, /*InsnID*/1,
// (add:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immSExtAddius5>>:$imm) => (ADDIUS5_MM:{ *:[i32] } GPR32:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immSExtAddius5>>:$imm)
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ADDIUS5_MM,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
GIR_EraseFromParent, /*InsnID*/0,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 2124,
GIR_Done,
// Label 73: @463
GIM_Try, /*On fail goto*//*Label 74*/ 486, // Rule ID 1196 //
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPRMM16RegClassID,
// (add:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) => (ADDU16_MMR6:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDU16_MMR6,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 1196,
GIR_Done,
// Label 74: @486
GIM_Try, /*On fail goto*//*Label 75*/ 509, // Rule ID 46 //
GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
// (add:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (ADDu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDu,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 46,
GIR_Done,
// Label 75: @509
GIM_Try, /*On fail goto*//*Label 76*/ 532, // Rule ID 1048 //
GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPRMM16RegClassID,
// (add:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) => (ADDU16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDU16_MM,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 1048,
GIR_Done,
// Label 76: @532
GIM_Try, /*On fail goto*//*Label 77*/ 555, // Rule ID 1060 //
GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
// (add:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (ADDu_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDu_MM,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 1060,
GIR_Done,
// Label 77: @555
GIM_Try, /*On fail goto*//*Label 78*/ 578, // Rule ID 1783 //
GIM_CheckFeatures, GIFBS_InMips16Mode,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
// (add:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r) => (AdduRxRyRz16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AdduRxRyRz16,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 1783,
GIR_Done,
// Label 78: @578
GIM_Reject,
// Label 68: @579
GIM_Reject,
// Label 60: @580
GIM_Try, /*On fail goto*//*Label 79*/ 742,
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
GIM_Try, /*On fail goto*//*Label 80*/ 658, // Rule ID 2349 //
GIM_CheckFeatures, GIFBS_HasMSA_HasMips64_HasStdEnc,
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL,
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_immZExt2Lsa,
// MIs[2] Operand 1
// No operand predicates
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
GIM_CheckIsSafeToFold, /*InsnID*/1,
GIM_CheckIsSafeToFold, /*InsnID*/2,
// (add:{ *:[i64] } (shl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt2Lsa>>:$sa), GPR64Opnd:{ *:[i64] }:$rt) => (DLSA:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$sa)
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DLSA,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rt
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sa
GIR_EraseFromParent, /*InsnID*/0,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 2349,
GIR_Done,
// Label 80: @658
GIM_Try, /*On fail goto*//*Label 81*/ 722, // Rule ID 823 //
GIM_CheckFeatures, GIFBS_HasMSA_HasMips64_HasStdEnc,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_SHL,
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
GIM_CheckOpcode, /*MI*/2, TargetOpcode::G_CONSTANT,
GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIPFP_I64_Predicate_immZExt2Lsa,
// MIs[2] Operand 1
// No operand predicates
GIM_CheckIsSafeToFold, /*InsnID*/1,
GIM_CheckIsSafeToFold, /*InsnID*/2,
// (add:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rt, (shl:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, (imm:{ *:[i32] })<<P:Predicate_immZExt2Lsa>>:$sa)) => (DLSA:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt, (imm:{ *:[i32] }):$sa)
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::DLSA,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rt
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sa
GIR_EraseFromParent, /*InsnID*/0,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 823,
GIR_Done,
// Label 81: @722
GIM_Try, /*On fail goto*//*Label 82*/ 741, // Rule ID 196 //
GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_NotInMicroMips,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
// (add:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DADDu:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DADDu,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 196,
GIR_Done,
// Label 82: @741
GIM_Reject,
// Label 79: @742
GIM_Reject,
// Label 61: @743
GIM_Try, /*On fail goto*//*Label 83*/ 769, // Rule ID 1882 //
GIM_CheckFeatures, GIFBS_HasDSP,
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
// (add:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b) => (ADDQ_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDQ_PH,
GIR_AddImplicitDef, /*InsnID*/0, Mips::DSPOutFlag20,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 1882,
GIR_Done,
// Label 83: @769
GIM_Reject,
// Label 62: @770
GIM_Try, /*On fail goto*//*Label 84*/ 918,
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
GIM_Try, /*On fail goto*//*Label 85*/ 841, // Rule ID 2353 //
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
GIM_CheckIsSafeToFold, /*InsnID*/1,
// (add:{ *:[v2i64] } (mul:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt), MSA128DOpnd:{ *:[v2i64] }:$wd_in) => (MADDV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_D,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
GIR_EraseFromParent, /*InsnID*/0,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 2353,
GIR_Done,
// Label 85: @841
GIM_Try, /*On fail goto*//*Label 86*/ 898, // Rule ID 831 //
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
GIM_CheckIsSafeToFold, /*InsnID*/1,
// (add:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, (mul:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)) => (MADDV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_D,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
GIR_EraseFromParent, /*InsnID*/0,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 831,
GIR_Done,
// Label 86: @898
GIM_Try, /*On fail goto*//*Label 87*/ 917, // Rule ID 498 //
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
// (add:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (ADDV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDV_D,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 498,
GIR_Done,
// Label 87: @917
GIM_Reject,
// Label 84: @918
GIM_Reject,
// Label 63: @919
GIM_Try, /*On fail goto*//*Label 88*/ 945, // Rule ID 1888 //
GIM_CheckFeatures, GIFBS_HasDSP,
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s8,
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
// (add:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b) => (ADDU_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b)
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDU_QB,
GIR_AddImplicitDef, /*InsnID*/0, Mips::DSPOutFlag20,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 1888,
GIR_Done,
// Label 88: @945
GIM_Reject,
// Label 64: @946
GIM_Try, /*On fail goto*//*Label 89*/ 1094,
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
GIM_Try, /*On fail goto*//*Label 90*/ 1017, // Rule ID 2352 //
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
GIM_CheckIsSafeToFold, /*InsnID*/1,
// (add:{ *:[v4i32] } (mul:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt), MSA128WOpnd:{ *:[v4i32] }:$wd_in) => (MADDV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_W,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
GIR_EraseFromParent, /*InsnID*/0,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 2352,
GIR_Done,
// Label 90: @1017
GIM_Try, /*On fail goto*//*Label 91*/ 1074, // Rule ID 830 //
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
GIM_CheckIsSafeToFold, /*InsnID*/1,
// (add:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, (mul:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)) => (MADDV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_W,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
GIR_EraseFromParent, /*InsnID*/0,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 830,
GIR_Done,
// Label 91: @1074
GIM_Try, /*On fail goto*//*Label 92*/ 1093, // Rule ID 497 //
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
// (add:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (ADDV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDV_W,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 497,
GIR_Done,
// Label 92: @1093
GIM_Reject,
// Label 89: @1094
GIM_Reject,
// Label 65: @1095
GIM_Try, /*On fail goto*//*Label 93*/ 1243,
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
GIM_Try, /*On fail goto*//*Label 94*/ 1166, // Rule ID 2351 //
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
GIM_CheckIsSafeToFold, /*InsnID*/1,
// (add:{ *:[v8i16] } (mul:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt), MSA128HOpnd:{ *:[v8i16] }:$wd_in) => (MADDV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_H,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
GIR_EraseFromParent, /*InsnID*/0,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 2351,
GIR_Done,
// Label 94: @1166
GIM_Try, /*On fail goto*//*Label 95*/ 1223, // Rule ID 829 //
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
GIM_CheckIsSafeToFold, /*InsnID*/1,
// (add:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, (mul:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)) => (MADDV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_H,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
GIR_EraseFromParent, /*InsnID*/0,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 829,
GIR_Done,
// Label 95: @1223
GIM_Try, /*On fail goto*//*Label 96*/ 1242, // Rule ID 496 //
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
// (add:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (ADDV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDV_H,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 496,
GIR_Done,
// Label 96: @1242
GIM_Reject,
// Label 93: @1243
GIM_Reject,
// Label 66: @1244
GIM_Try, /*On fail goto*//*Label 97*/ 1392,
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
GIM_Try, /*On fail goto*//*Label 98*/ 1315, // Rule ID 2350 //
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
GIM_CheckIsSafeToFold, /*InsnID*/1,
// (add:{ *:[v16i8] } (mul:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt), MSA128BOpnd:{ *:[v16i8] }:$wd_in) => (MADDV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_B,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // wd_in
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
GIR_EraseFromParent, /*InsnID*/0,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 2350,
GIR_Done,
// Label 98: @1315
GIM_Try, /*On fail goto*//*Label 99*/ 1372, // Rule ID 828 //
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
GIM_CheckIsSafeToFold, /*InsnID*/1,
// (add:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, (mul:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)) => (MADDV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MADDV_B,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
GIR_EraseFromParent, /*InsnID*/0,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 828,
GIR_Done,
// Label 99: @1372
GIM_Try, /*On fail goto*//*Label 100*/ 1391, // Rule ID 495 //
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
// (add:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (ADDV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::ADDV_B,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 495,
GIR_Done,
// Label 100: @1391
GIM_Reject,
// Label 97: @1392
GIM_Reject,
// Label 67: @1393
GIM_Reject,
// Label 1: @1394
GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 109*/ 2005,
/*GILLT_s32*//*Label 101*/ 1408,
/*GILLT_s64*//*Label 102*/ 1567,
/*GILLT_v2s16*//*Label 103*/ 1599,
/*GILLT_v2s64*//*Label 104*/ 1626,
/*GILLT_v4s8*//*Label 105*/ 1714,
/*GILLT_v4s32*//*Label 106*/ 1741,
/*GILLT_v8s16*//*Label 107*/ 1829,
/*GILLT_v16s8*//*Label 108*/ 1917,
// Label 101: @1408
GIM_Try, /*On fail goto*//*Label 110*/ 1566,
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
GIM_Try, /*On fail goto*//*Label 111*/ 1450, // Rule ID 1782 //
GIM_CheckFeatures, GIFBS_InMips16Mode,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
GIM_CheckConstantInt, /*MI*/0, /*Op*/1, 0,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
// (sub:{ *:[i32] } 0:{ *:[i32] }, CPU16Regs:{ *:[i32] }:$r) => (NegRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$r)
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::NegRxRy16,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rx
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // r
GIR_EraseFromParent, /*InsnID*/0,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 1782,
GIR_Done,
// Label 111: @1450
GIM_Try, /*On fail goto*//*Label 112*/ 1473, // Rule ID 1198 //
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPRMM16RegClassID,
// (sub:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) => (SUBU16_MMR6:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBU16_MMR6,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 1198,
GIR_Done,
// Label 112: @1473
GIM_Try, /*On fail goto*//*Label 113*/ 1496, // Rule ID 47 //
GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
// (sub:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (SUBu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBu,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 47,
GIR_Done,
// Label 113: @1496
GIM_Try, /*On fail goto*//*Label 114*/ 1519, // Rule ID 1052 //
GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPRMM16RegClassID,
// (sub:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) => (SUBU16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBU16_MM,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 1052,
GIR_Done,
// Label 114: @1519
GIM_Try, /*On fail goto*//*Label 115*/ 1542, // Rule ID 1061 //
GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
// (sub:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (SUBu_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBu_MM,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 1061,
GIR_Done,
// Label 115: @1542
GIM_Try, /*On fail goto*//*Label 116*/ 1565, // Rule ID 1787 //
GIM_CheckFeatures, GIFBS_InMips16Mode,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
// (sub:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r) => (SubuRxRyRz16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SubuRxRyRz16,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 1787,
GIR_Done,
// Label 116: @1565
GIM_Reject,
// Label 110: @1566
GIM_Reject,
// Label 102: @1567
GIM_Try, /*On fail goto*//*Label 117*/ 1598, // Rule ID 197 //
GIM_CheckFeatures, GIFBS_HasMips3_HasStdEnc_NotInMicroMips,
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
// (sub:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DSUBu:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DSUBu,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 197,
GIR_Done,
// Label 117: @1598
GIM_Reject,
// Label 103: @1599
GIM_Try, /*On fail goto*//*Label 118*/ 1625, // Rule ID 1884 //
GIM_CheckFeatures, GIFBS_HasDSP,
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
// (sub:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b) => (SUBQ_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBQ_PH,
GIR_AddImplicitDef, /*InsnID*/0, Mips::DSPOutFlag20,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 1884,
GIR_Done,
// Label 118: @1625
GIM_Reject,
// Label 104: @1626
GIM_Try, /*On fail goto*//*Label 119*/ 1713,
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
GIM_Try, /*On fail goto*//*Label 120*/ 1697, // Rule ID 887 //
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s64,
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s64,
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
GIM_CheckIsSafeToFold, /*InsnID*/1,
// (sub:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, (mul:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)) => (MSUBV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$wd_in, MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUBV_D,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
GIR_EraseFromParent, /*InsnID*/0,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 887,
GIR_Done,
// Label 120: @1697
GIM_Try, /*On fail goto*//*Label 121*/ 1712, // Rule ID 1016 //
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
// (sub:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (SUBV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBV_D,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 1016,
GIR_Done,
// Label 121: @1712
GIM_Reject,
// Label 119: @1713
GIM_Reject,
// Label 105: @1714
GIM_Try, /*On fail goto*//*Label 122*/ 1740, // Rule ID 1890 //
GIM_CheckFeatures, GIFBS_HasDSP,
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s8,
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s8,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
// (sub:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b) => (SUBU_QB:{ *:[v4i8] } v4i8:{ *:[v4i8] }:$a, v4i8:{ *:[v4i8] }:$b)
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBU_QB,
GIR_AddImplicitDef, /*InsnID*/0, Mips::DSPOutFlag20,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 1890,
GIR_Done,
// Label 122: @1740
GIM_Reject,
// Label 106: @1741
GIM_Try, /*On fail goto*//*Label 123*/ 1828,
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
GIM_Try, /*On fail goto*//*Label 124*/ 1812, // Rule ID 886 //
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
GIM_CheckIsSafeToFold, /*InsnID*/1,
// (sub:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, (mul:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)) => (MSUBV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$wd_in, MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUBV_W,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
GIR_EraseFromParent, /*InsnID*/0,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 886,
GIR_Done,
// Label 124: @1812
GIM_Try, /*On fail goto*//*Label 125*/ 1827, // Rule ID 1015 //
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
// (sub:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (SUBV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBV_W,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 1015,
GIR_Done,
// Label 125: @1827
GIM_Reject,
// Label 123: @1828
GIM_Reject,
// Label 107: @1829
GIM_Try, /*On fail goto*//*Label 126*/ 1916,
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
GIM_Try, /*On fail goto*//*Label 127*/ 1900, // Rule ID 885 //
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
GIM_CheckIsSafeToFold, /*InsnID*/1,
// (sub:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, (mul:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)) => (MSUBV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$wd_in, MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUBV_H,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
GIR_EraseFromParent, /*InsnID*/0,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 885,
GIR_Done,
// Label 127: @1900
GIM_Try, /*On fail goto*//*Label 128*/ 1915, // Rule ID 1014 //
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
// (sub:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (SUBV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBV_H,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 1014,
GIR_Done,
// Label 128: @1915
GIM_Reject,
// Label 126: @1916
GIM_Reject,
// Label 108: @1917
GIM_Try, /*On fail goto*//*Label 129*/ 2004,
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
GIM_Try, /*On fail goto*//*Label 130*/ 1988, // Rule ID 884 //
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_MUL,
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
GIM_CheckIsSafeToFold, /*InsnID*/1,
// (sub:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, (mul:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)) => (MSUBV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$wd_in, MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::MSUBV_B,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // wd
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // wd_in
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ws
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // wt
GIR_EraseFromParent, /*InsnID*/0,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 884,
GIR_Done,
// Label 130: @1988
GIM_Try, /*On fail goto*//*Label 131*/ 2003, // Rule ID 1013 //
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
// (sub:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (SUBV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::SUBV_B,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 1013,
GIR_Done,
// Label 131: @2003
GIM_Reject,
// Label 129: @2004
GIM_Reject,
// Label 109: @2005
GIM_Reject,
// Label 2: @2006
GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 139*/ 2381,
/*GILLT_s32*//*Label 132*/ 2020,
/*GILLT_s64*//*Label 133*/ 2165,
/*GILLT_v2s16*//*Label 134*/ 2226,
/*GILLT_v2s64*//*Label 135*/ 2253, 0,
/*GILLT_v4s32*//*Label 136*/ 2285,
/*GILLT_v8s16*//*Label 137*/ 2317,
/*GILLT_v16s8*//*Label 138*/ 2349,
// Label 132: @2020
GIM_Try, /*On fail goto*//*Label 140*/ 2164,
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
GIM_Try, /*On fail goto*//*Label 141*/ 2059, // Rule ID 48 //
GIM_CheckFeatures, GIFBS_HasMips32_HasStdEnc_NotInMicroMips_NotMips32r6_NotMips64r6,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
// (mul:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MUL:{ *:[i32] }:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MUL,
GIR_AddImplicitDef, /*InsnID*/0, Mips::HI0,
GIR_AddImplicitDef, /*InsnID*/0, Mips::LO0,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 48,
GIR_Done,
// Label 141: @2059
GIM_Try, /*On fail goto*//*Label 142*/ 2082, // Rule ID 320 //
GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
// (mul:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MUL_R6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MUL_R6,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 320,
GIR_Done,
// Label 142: @2082
GIM_Try, /*On fail goto*//*Label 143*/ 2111, // Rule ID 1062 //
GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
// (mul:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MUL_MM:{ *:[i32] }:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MUL_MM,
GIR_AddImplicitDef, /*InsnID*/0, Mips::HI0,
GIR_AddImplicitDef, /*InsnID*/0, Mips::LO0,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 1062,
GIR_Done,
// Label 143: @2111
GIM_Try, /*On fail goto*//*Label 144*/ 2134, // Rule ID 1167 //
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
// (mul:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MUL_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MUL_MMR6,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 1167,
GIR_Done,
// Label 144: @2134
GIM_Try, /*On fail goto*//*Label 145*/ 2163, // Rule ID 1785 //
GIM_CheckFeatures, GIFBS_InMips16Mode,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
// (mul:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r) => (MultRxRyRz16:{ *:[i32] }:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MultRxRyRz16,
GIR_AddImplicitDef, /*InsnID*/0, Mips::HI0,
GIR_AddImplicitDef, /*InsnID*/0, Mips::LO0,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 1785,
GIR_Done,
// Label 145: @2163
GIM_Reject,
// Label 140: @2164
GIM_Reject,
// Label 133: @2165
GIM_Try, /*On fail goto*//*Label 146*/ 2225,
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
GIM_Try, /*On fail goto*//*Label 147*/ 2213, // Rule ID 262 //
GIM_CheckFeatures, GIFBS_HasCnMips,
// (mul:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DMUL:{ *:[i64] }:{ *:[i32] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DMUL,
GIR_AddImplicitDef, /*InsnID*/0, Mips::HI0,
GIR_AddImplicitDef, /*InsnID*/0, Mips::LO0,
GIR_AddImplicitDef, /*InsnID*/0, Mips::P0,
GIR_AddImplicitDef, /*InsnID*/0, Mips::P1,
GIR_AddImplicitDef, /*InsnID*/0, Mips::P2,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 262,
GIR_Done,
// Label 147: @2213
GIM_Try, /*On fail goto*//*Label 148*/ 2224, // Rule ID 335 //
GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips,
// (mul:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DMUL_R6:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DMUL_R6,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 335,
GIR_Done,
// Label 148: @2224
GIM_Reject,
// Label 146: @2225
GIM_Reject,
// Label 134: @2226
GIM_Try, /*On fail goto*//*Label 149*/ 2252, // Rule ID 1886 //
GIM_CheckFeatures, GIFBS_HasDSPR2,
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::DSPRRegClassID,
// (mul:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b) => (MUL_PH:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a, v2i16:{ *:[v2i16] }:$b)
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MUL_PH,
GIR_AddImplicitDef, /*InsnID*/0, Mips::DSPOutFlag21,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 1886,
GIR_Done,
// Label 149: @2252
GIM_Reject,
// Label 135: @2253
GIM_Try, /*On fail goto*//*Label 150*/ 2284, // Rule ID 895 //
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
// (mul:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (MULV_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MULV_D,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 895,
GIR_Done,
// Label 150: @2284
GIM_Reject,
// Label 136: @2285
GIM_Try, /*On fail goto*//*Label 151*/ 2316, // Rule ID 894 //
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
// (mul:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MULV_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MULV_W,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 894,
GIR_Done,
// Label 151: @2316
GIM_Reject,
// Label 137: @2317
GIM_Try, /*On fail goto*//*Label 152*/ 2348, // Rule ID 893 //
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
// (mul:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MULV_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MULV_H,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 893,
GIR_Done,
// Label 152: @2348
GIM_Reject,
// Label 138: @2349
GIM_Try, /*On fail goto*//*Label 153*/ 2380, // Rule ID 892 //
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
// (mul:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (MULV_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MULV_B,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 892,
GIR_Done,
// Label 153: @2380
GIM_Reject,
// Label 139: @2381
GIM_Reject,
// Label 3: @2382
GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 160*/ 2602,
/*GILLT_s32*//*Label 154*/ 2396,
/*GILLT_s64*//*Label 155*/ 2442, 0,
/*GILLT_v2s64*//*Label 156*/ 2474, 0,
/*GILLT_v4s32*//*Label 157*/ 2506,
/*GILLT_v8s16*//*Label 158*/ 2538,
/*GILLT_v16s8*//*Label 159*/ 2570,
// Label 154: @2396
GIM_Try, /*On fail goto*//*Label 161*/ 2441,
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
GIM_Try, /*On fail goto*//*Label 162*/ 2429, // Rule ID 314 //
GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips,
// (sdiv:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (DIV:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 314,
GIR_Done,
// Label 162: @2429
GIM_Try, /*On fail goto*//*Label 163*/ 2440, // Rule ID 1160 //
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
// (sdiv:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (DIV_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_MMR6,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 1160,
GIR_Done,
// Label 163: @2440
GIM_Reject,
// Label 161: @2441
GIM_Reject,
// Label 155: @2442
GIM_Try, /*On fail goto*//*Label 164*/ 2473, // Rule ID 329 //
GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips,
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
// (sdiv:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DDIV:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DDIV,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 329,
GIR_Done,
// Label 164: @2473
GIM_Reject,
// Label 156: @2474
GIM_Try, /*On fail goto*//*Label 165*/ 2505, // Rule ID 635 //
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
// (sdiv:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (DIV_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_S_D,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 635,
GIR_Done,
// Label 165: @2505
GIM_Reject,
// Label 157: @2506
GIM_Try, /*On fail goto*//*Label 166*/ 2537, // Rule ID 634 //
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
// (sdiv:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (DIV_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_S_W,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 634,
GIR_Done,
// Label 166: @2537
GIM_Reject,
// Label 158: @2538
GIM_Try, /*On fail goto*//*Label 167*/ 2569, // Rule ID 633 //
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
// (sdiv:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (DIV_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_S_H,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 633,
GIR_Done,
// Label 167: @2569
GIM_Reject,
// Label 159: @2570
GIM_Try, /*On fail goto*//*Label 168*/ 2601, // Rule ID 632 //
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
// (sdiv:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (DIV_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_S_B,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 632,
GIR_Done,
// Label 168: @2601
GIM_Reject,
// Label 160: @2602
GIM_Reject,
// Label 4: @2603
GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 175*/ 2823,
/*GILLT_s32*//*Label 169*/ 2617,
/*GILLT_s64*//*Label 170*/ 2663, 0,
/*GILLT_v2s64*//*Label 171*/ 2695, 0,
/*GILLT_v4s32*//*Label 172*/ 2727,
/*GILLT_v8s16*//*Label 173*/ 2759,
/*GILLT_v16s8*//*Label 174*/ 2791,
// Label 169: @2617
GIM_Try, /*On fail goto*//*Label 176*/ 2662,
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
GIM_Try, /*On fail goto*//*Label 177*/ 2650, // Rule ID 315 //
GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips,
// (udiv:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (DIVU:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIVU,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 315,
GIR_Done,
// Label 177: @2650
GIM_Try, /*On fail goto*//*Label 178*/ 2661, // Rule ID 1161 //
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
// (udiv:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (DIVU_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIVU_MMR6,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 1161,
GIR_Done,
// Label 178: @2661
GIM_Reject,
// Label 176: @2662
GIM_Reject,
// Label 170: @2663
GIM_Try, /*On fail goto*//*Label 179*/ 2694, // Rule ID 330 //
GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips,
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
// (udiv:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DDIVU:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DDIVU,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 330,
GIR_Done,
// Label 179: @2694
GIM_Reject,
// Label 171: @2695
GIM_Try, /*On fail goto*//*Label 180*/ 2726, // Rule ID 639 //
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
// (udiv:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (DIV_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_U_D,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 639,
GIR_Done,
// Label 180: @2726
GIM_Reject,
// Label 172: @2727
GIM_Try, /*On fail goto*//*Label 181*/ 2758, // Rule ID 638 //
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
// (udiv:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (DIV_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_U_W,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 638,
GIR_Done,
// Label 181: @2758
GIM_Reject,
// Label 173: @2759
GIM_Try, /*On fail goto*//*Label 182*/ 2790, // Rule ID 637 //
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
// (udiv:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (DIV_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_U_H,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 637,
GIR_Done,
// Label 182: @2790
GIM_Reject,
// Label 174: @2791
GIM_Try, /*On fail goto*//*Label 183*/ 2822, // Rule ID 636 //
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
// (udiv:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (DIV_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DIV_U_B,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 636,
GIR_Done,
// Label 183: @2822
GIM_Reject,
// Label 175: @2823
GIM_Reject,
// Label 5: @2824
GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 190*/ 3044,
/*GILLT_s32*//*Label 184*/ 2838,
/*GILLT_s64*//*Label 185*/ 2884, 0,
/*GILLT_v2s64*//*Label 186*/ 2916, 0,
/*GILLT_v4s32*//*Label 187*/ 2948,
/*GILLT_v8s16*//*Label 188*/ 2980,
/*GILLT_v16s8*//*Label 189*/ 3012,
// Label 184: @2838
GIM_Try, /*On fail goto*//*Label 191*/ 2883,
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
GIM_Try, /*On fail goto*//*Label 192*/ 2871, // Rule ID 316 //
GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips,
// (srem:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MOD:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 316,
GIR_Done,
// Label 192: @2871
GIM_Try, /*On fail goto*//*Label 193*/ 2882, // Rule ID 1165 //
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
// (srem:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MOD_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_MMR6,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 1165,
GIR_Done,
// Label 193: @2882
GIM_Reject,
// Label 191: @2883
GIM_Reject,
// Label 185: @2884
GIM_Try, /*On fail goto*//*Label 194*/ 2915, // Rule ID 331 //
GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips,
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
// (srem:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DMOD:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DMOD,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 331,
GIR_Done,
// Label 194: @2915
GIM_Reject,
// Label 186: @2916
GIM_Try, /*On fail goto*//*Label 195*/ 2947, // Rule ID 875 //
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
// (srem:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (MOD_S_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_S_D,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 875,
GIR_Done,
// Label 195: @2947
GIM_Reject,
// Label 187: @2948
GIM_Try, /*On fail goto*//*Label 196*/ 2979, // Rule ID 874 //
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
// (srem:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MOD_S_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_S_W,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 874,
GIR_Done,
// Label 196: @2979
GIM_Reject,
// Label 188: @2980
GIM_Try, /*On fail goto*//*Label 197*/ 3011, // Rule ID 873 //
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
// (srem:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MOD_S_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_S_H,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 873,
GIR_Done,
// Label 197: @3011
GIM_Reject,
// Label 189: @3012
GIM_Try, /*On fail goto*//*Label 198*/ 3043, // Rule ID 872 //
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
// (srem:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (MOD_S_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_S_B,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 872,
GIR_Done,
// Label 198: @3043
GIM_Reject,
// Label 190: @3044
GIM_Reject,
// Label 6: @3045
GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 205*/ 3265,
/*GILLT_s32*//*Label 199*/ 3059,
/*GILLT_s64*//*Label 200*/ 3105, 0,
/*GILLT_v2s64*//*Label 201*/ 3137, 0,
/*GILLT_v4s32*//*Label 202*/ 3169,
/*GILLT_v8s16*//*Label 203*/ 3201,
/*GILLT_v16s8*//*Label 204*/ 3233,
// Label 199: @3059
GIM_Try, /*On fail goto*//*Label 206*/ 3104,
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
GIM_Try, /*On fail goto*//*Label 207*/ 3092, // Rule ID 317 //
GIM_CheckFeatures, GIFBS_HasMips32r6_HasStdEnc_NotInMicroMips,
// (urem:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MODU:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MODU,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 317,
GIR_Done,
// Label 207: @3092
GIM_Try, /*On fail goto*//*Label 208*/ 3103, // Rule ID 1166 //
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
// (urem:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MODU_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MODU_MMR6,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 1166,
GIR_Done,
// Label 208: @3103
GIM_Reject,
// Label 206: @3104
GIM_Reject,
// Label 200: @3105
GIM_Try, /*On fail goto*//*Label 209*/ 3136, // Rule ID 332 //
GIM_CheckFeatures, GIFBS_HasMips64r6_HasStdEnc_NotInMicroMips,
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
// (urem:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (DMODU:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::DMODU,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 332,
GIR_Done,
// Label 209: @3136
GIM_Reject,
// Label 201: @3137
GIM_Try, /*On fail goto*//*Label 210*/ 3168, // Rule ID 879 //
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
// (urem:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (MOD_U_D:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_U_D,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 879,
GIR_Done,
// Label 210: @3168
GIM_Reject,
// Label 202: @3169
GIM_Try, /*On fail goto*//*Label 211*/ 3200, // Rule ID 878 //
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
// (urem:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (MOD_U_W:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_U_W,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 878,
GIR_Done,
// Label 211: @3200
GIM_Reject,
// Label 203: @3201
GIM_Try, /*On fail goto*//*Label 212*/ 3232, // Rule ID 877 //
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
// (urem:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (MOD_U_H:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_U_H,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 877,
GIR_Done,
// Label 212: @3232
GIM_Reject,
// Label 204: @3233
GIM_Try, /*On fail goto*//*Label 213*/ 3264, // Rule ID 876 //
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s8,
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s8,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128BRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128BRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128BRegClassID,
// (urem:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt) => (MOD_U_B:{ *:[v16i8] } MSA128BOpnd:{ *:[v16i8] }:$ws, MSA128BOpnd:{ *:[v16i8] }:$wt)
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MOD_U_B,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 876,
GIR_Done,
// Label 213: @3264
GIM_Reject,
// Label 205: @3265
GIM_Reject,
// Label 7: @3266
GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/1, 9, /*)*//*default:*//*Label 220*/ 3752,
/*GILLT_s32*//*Label 214*/ 3280,
/*GILLT_s64*//*Label 215*/ 3536, 0,
/*GILLT_v2s64*//*Label 216*/ 3624, 0,
/*GILLT_v4s32*//*Label 217*/ 3656,
/*GILLT_v8s16*//*Label 218*/ 3688,
/*GILLT_v16s8*//*Label 219*/ 3720,
// Label 214: @3280
GIM_Try, /*On fail goto*//*Label 221*/ 3535,
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
GIM_Try, /*On fail goto*//*Label 222*/ 3333, // Rule ID 41 //
GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
GIM_CheckAPIntImmPredicate, /*MI*/1, /*Predicate*/GIPFP_APInt_Predicate_imm32ZExt16,
// MIs[1] Operand 1
// No operand predicates
GIM_CheckIsSafeToFold, /*InsnID*/1,
// (and:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] })<<P:Predicate_imm32ZExt16>>:$imm16) => (ANDi:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, (imm:{ *:[i32] }):$imm16)
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ANDi,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rt
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rs
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm16
GIR_EraseFromParent, /*InsnID*/0,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 41,
GIR_Done,
// Label 222: @3333
GIM_Try, /*On fail goto*//*Label 223*/ 3376, // Rule ID 2126 //
GIM_CheckFeatures, GIFBS_InMicroMips,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExtAndi16,
// MIs[1] Operand 1
// No operand predicates
GIM_CheckIsSafeToFold, /*InsnID*/1,
// (and:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExtAndi16>>:$imm) => (ANDI16_MM:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExtAndi16>>:$imm)
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ANDI16_MM,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
GIR_EraseFromParent, /*InsnID*/0,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 2126,
GIR_Done,
// Label 223: @3376
GIM_Try, /*On fail goto*//*Label 224*/ 3419, // Rule ID 2285 //
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_CONSTANT,
GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIPFP_I64_Predicate_immZExtAndi16,
// MIs[1] Operand 1
// No operand predicates
GIM_CheckIsSafeToFold, /*InsnID*/1,
// (and:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExtAndi16>>:$imm) => (ANDI16_MMR6:{ *:[i32] } GPRMM16:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_immZExtAndi16>>:$imm)
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::ANDI16_MMR6,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
GIR_EraseFromParent, /*InsnID*/0,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 2285,
GIR_Done,
// Label 224: @3419
GIM_Try, /*On fail goto*//*Label 225*/ 3442, // Rule ID 51 //
GIM_CheckFeatures, GIFBS_HasStdEnc_NotInMicroMips,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
// (and:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (AND:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 51,
GIR_Done,
// Label 225: @3442
GIM_Try, /*On fail goto*//*Label 226*/ 3465, // Rule ID 1049 //
GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPRMM16RegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPRMM16RegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPRMM16RegClassID,
// (and:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt) => (AND16_MM:{ *:[i32] } GPRMM16Opnd:{ *:[i32] }:$rs, GPRMM16Opnd:{ *:[i32] }:$rt)
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND16_MM,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 1049,
GIR_Done,
// Label 226: @3465
GIM_Try, /*On fail goto*//*Label 227*/ 3488, // Rule ID 1065 //
GIM_CheckFeatures, GIFBS_InMicroMips_NotMips32r6,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
// (and:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (AND_MM:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND_MM,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 1065,
GIR_Done,
// Label 227: @3488
GIM_Try, /*On fail goto*//*Label 228*/ 3511, // Rule ID 1158 //
GIM_CheckFeatures, GIFBS_HasMips32r6_InMicroMips,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR32RegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR32RegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR32RegClassID,
// (and:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (AND_MMR6:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND_MMR6,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 1158,
GIR_Done,
// Label 228: @3511
GIM_Try, /*On fail goto*//*Label 229*/ 3534, // Rule ID 1784 //
GIM_CheckFeatures, GIFBS_InMips16Mode,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::CPU16RegsRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::CPU16RegsRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::CPU16RegsRegClassID,
// (and:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r) => (AndRxRxRy16:{ *:[i32] } CPU16Regs:{ *:[i32] }:$l, CPU16Regs:{ *:[i32] }:$r)
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AndRxRxRy16,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 1784,
GIR_Done,
// Label 229: @3534
GIM_Reject,
// Label 221: @3535
GIM_Reject,
// Label 215: @3536
GIM_Try, /*On fail goto*//*Label 230*/ 3623,
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::GPR64RegClassID,
GIM_Try, /*On fail goto*//*Label 231*/ 3603, // Rule ID 257 //
GIM_CheckFeatures, GIFBS_HasCnMips,
GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_ADD,
GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
GIM_CheckConstantInt, /*MI*/0, /*Op*/2, 255,
GIM_CheckIsSafeToFold, /*InsnID*/1,
// (and:{ *:[i64] } (add:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt), 255:{ *:[i64] }) => (BADDu:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
GIR_BuildMI, /*InsnID*/0, /*Opcode*/Mips::BADDu,
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // rd
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // rs
GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // rt
GIR_EraseFromParent, /*InsnID*/0,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 257,
GIR_Done,
// Label 231: @3603
GIM_Try, /*On fail goto*//*Label 232*/ 3622, // Rule ID 200 //
GIM_CheckFeatures, GIFBS_IsGP64bit_NotInMips16Mode,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::GPR64RegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::GPR64RegClassID,
// (and:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt) => (AND64:{ *:[i64] } GPR64Opnd:{ *:[i64] }:$rs, GPR64Opnd:{ *:[i64] }:$rt)
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND64,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 200,
GIR_Done,
// Label 232: @3622
GIM_Reject,
// Label 230: @3623
GIM_Reject,
// Label 216: @3624
GIM_Try, /*On fail goto*//*Label 233*/ 3655, // Rule ID 506 //
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128DRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128DRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128DRegClassID,
// (and:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt) => (AND_V_D_PSEUDO:{ *:[v2i64] } MSA128DOpnd:{ *:[v2i64] }:$ws, MSA128DOpnd:{ *:[v2i64] }:$wt)
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND_V_D_PSEUDO,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 506,
GIR_Done,
// Label 233: @3655
GIM_Reject,
// Label 217: @3656
GIM_Try, /*On fail goto*//*Label 234*/ 3687, // Rule ID 505 //
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128WRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128WRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128WRegClassID,
// (and:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt) => (AND_V_W_PSEUDO:{ *:[v4i32] } MSA128WOpnd:{ *:[v4i32] }:$ws, MSA128WOpnd:{ *:[v4i32] }:$wt)
GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::AND_V_W_PSEUDO,
GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
// GIR_Coverage, 505,
GIR_Done,
// Label 234: @3687
GIM_Reject,
// Label 218: @3688
GIM_Try, /*On fail goto*//*Label 235*/ 3719, // Rule ID 504 //
GIM_CheckFeatures, GIFBS_HasMSA_HasStdEnc,
GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/Mips::MSA128HRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/Mips::MSA128HRegClassID,
GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Mips::MSA128HRegClassID,
// (and:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt) => (AND_V_H_PSEUDO:{ *:[v8i16] } MSA128HOpnd:{ *:[v8i16] }:$ws, MSA128HOpnd:{ *:[v8i16] }:$wt)
GIR_MutateOpcode,