| /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
| |* *| |
| |* Target Instruction Enum Values and Descriptors *| |
| |* *| |
| |* Automatically generated file, do not edit! *| |
| |* *| |
| \*===----------------------------------------------------------------------===*/ |
| |
| #ifdef GET_INSTRINFO_ENUM |
| #undef GET_INSTRINFO_ENUM |
| namespace llvm { |
| |
| namespace ARM { |
| enum { |
| PHI = 0, |
| INLINEASM = 1, |
| INLINEASM_BR = 2, |
| CFI_INSTRUCTION = 3, |
| EH_LABEL = 4, |
| GC_LABEL = 5, |
| ANNOTATION_LABEL = 6, |
| KILL = 7, |
| EXTRACT_SUBREG = 8, |
| INSERT_SUBREG = 9, |
| IMPLICIT_DEF = 10, |
| SUBREG_TO_REG = 11, |
| COPY_TO_REGCLASS = 12, |
| DBG_VALUE = 13, |
| DBG_VALUE_LIST = 14, |
| DBG_INSTR_REF = 15, |
| DBG_PHI = 16, |
| DBG_LABEL = 17, |
| REG_SEQUENCE = 18, |
| COPY = 19, |
| BUNDLE = 20, |
| LIFETIME_START = 21, |
| LIFETIME_END = 22, |
| PSEUDO_PROBE = 23, |
| ARITH_FENCE = 24, |
| STACKMAP = 25, |
| FENTRY_CALL = 26, |
| PATCHPOINT = 27, |
| LOAD_STACK_GUARD = 28, |
| PREALLOCATED_SETUP = 29, |
| PREALLOCATED_ARG = 30, |
| STATEPOINT = 31, |
| LOCAL_ESCAPE = 32, |
| FAULTING_OP = 33, |
| PATCHABLE_OP = 34, |
| PATCHABLE_FUNCTION_ENTER = 35, |
| PATCHABLE_RET = 36, |
| PATCHABLE_FUNCTION_EXIT = 37, |
| PATCHABLE_TAIL_CALL = 38, |
| PATCHABLE_EVENT_CALL = 39, |
| PATCHABLE_TYPED_EVENT_CALL = 40, |
| ICALL_BRANCH_FUNNEL = 41, |
| MEMBARRIER = 42, |
| G_ASSERT_SEXT = 43, |
| G_ASSERT_ZEXT = 44, |
| G_ASSERT_ALIGN = 45, |
| G_ADD = 46, |
| G_SUB = 47, |
| G_MUL = 48, |
| G_SDIV = 49, |
| G_UDIV = 50, |
| G_SREM = 51, |
| G_UREM = 52, |
| G_SDIVREM = 53, |
| G_UDIVREM = 54, |
| G_AND = 55, |
| G_OR = 56, |
| G_XOR = 57, |
| G_IMPLICIT_DEF = 58, |
| G_PHI = 59, |
| G_FRAME_INDEX = 60, |
| G_GLOBAL_VALUE = 61, |
| G_EXTRACT = 62, |
| G_UNMERGE_VALUES = 63, |
| G_INSERT = 64, |
| G_MERGE_VALUES = 65, |
| G_BUILD_VECTOR = 66, |
| G_BUILD_VECTOR_TRUNC = 67, |
| G_CONCAT_VECTORS = 68, |
| G_PTRTOINT = 69, |
| G_INTTOPTR = 70, |
| G_BITCAST = 71, |
| G_FREEZE = 72, |
| G_INTRINSIC_FPTRUNC_ROUND = 73, |
| G_INTRINSIC_TRUNC = 74, |
| G_INTRINSIC_ROUND = 75, |
| G_INTRINSIC_LRINT = 76, |
| G_INTRINSIC_ROUNDEVEN = 77, |
| G_READCYCLECOUNTER = 78, |
| G_LOAD = 79, |
| G_SEXTLOAD = 80, |
| G_ZEXTLOAD = 81, |
| G_INDEXED_LOAD = 82, |
| G_INDEXED_SEXTLOAD = 83, |
| G_INDEXED_ZEXTLOAD = 84, |
| G_STORE = 85, |
| G_INDEXED_STORE = 86, |
| G_ATOMIC_CMPXCHG_WITH_SUCCESS = 87, |
| G_ATOMIC_CMPXCHG = 88, |
| G_ATOMICRMW_XCHG = 89, |
| G_ATOMICRMW_ADD = 90, |
| G_ATOMICRMW_SUB = 91, |
| G_ATOMICRMW_AND = 92, |
| G_ATOMICRMW_NAND = 93, |
| G_ATOMICRMW_OR = 94, |
| G_ATOMICRMW_XOR = 95, |
| G_ATOMICRMW_MAX = 96, |
| G_ATOMICRMW_MIN = 97, |
| G_ATOMICRMW_UMAX = 98, |
| G_ATOMICRMW_UMIN = 99, |
| G_ATOMICRMW_FADD = 100, |
| G_ATOMICRMW_FSUB = 101, |
| G_ATOMICRMW_FMAX = 102, |
| G_ATOMICRMW_FMIN = 103, |
| G_ATOMICRMW_UINC_WRAP = 104, |
| G_ATOMICRMW_UDEC_WRAP = 105, |
| G_FENCE = 106, |
| G_BRCOND = 107, |
| G_BRINDIRECT = 108, |
| G_INVOKE_REGION_START = 109, |
| G_INTRINSIC = 110, |
| G_INTRINSIC_W_SIDE_EFFECTS = 111, |
| G_ANYEXT = 112, |
| G_TRUNC = 113, |
| G_CONSTANT = 114, |
| G_FCONSTANT = 115, |
| G_VASTART = 116, |
| G_VAARG = 117, |
| G_SEXT = 118, |
| G_SEXT_INREG = 119, |
| G_ZEXT = 120, |
| G_SHL = 121, |
| G_LSHR = 122, |
| G_ASHR = 123, |
| G_FSHL = 124, |
| G_FSHR = 125, |
| G_ROTR = 126, |
| G_ROTL = 127, |
| G_ICMP = 128, |
| G_FCMP = 129, |
| G_SELECT = 130, |
| G_UADDO = 131, |
| G_UADDE = 132, |
| G_USUBO = 133, |
| G_USUBE = 134, |
| G_SADDO = 135, |
| G_SADDE = 136, |
| G_SSUBO = 137, |
| G_SSUBE = 138, |
| G_UMULO = 139, |
| G_SMULO = 140, |
| G_UMULH = 141, |
| G_SMULH = 142, |
| G_UADDSAT = 143, |
| G_SADDSAT = 144, |
| G_USUBSAT = 145, |
| G_SSUBSAT = 146, |
| G_USHLSAT = 147, |
| G_SSHLSAT = 148, |
| G_SMULFIX = 149, |
| G_UMULFIX = 150, |
| G_SMULFIXSAT = 151, |
| G_UMULFIXSAT = 152, |
| G_SDIVFIX = 153, |
| G_UDIVFIX = 154, |
| G_SDIVFIXSAT = 155, |
| G_UDIVFIXSAT = 156, |
| G_FADD = 157, |
| G_FSUB = 158, |
| G_FMUL = 159, |
| G_FMA = 160, |
| G_FMAD = 161, |
| G_FDIV = 162, |
| G_FREM = 163, |
| G_FPOW = 164, |
| G_FPOWI = 165, |
| G_FEXP = 166, |
| G_FEXP2 = 167, |
| G_FLOG = 168, |
| G_FLOG2 = 169, |
| G_FLOG10 = 170, |
| G_FNEG = 171, |
| G_FPEXT = 172, |
| G_FPTRUNC = 173, |
| G_FPTOSI = 174, |
| G_FPTOUI = 175, |
| G_SITOFP = 176, |
| G_UITOFP = 177, |
| G_FABS = 178, |
| G_FCOPYSIGN = 179, |
| G_IS_FPCLASS = 180, |
| G_FCANONICALIZE = 181, |
| G_FMINNUM = 182, |
| G_FMAXNUM = 183, |
| G_FMINNUM_IEEE = 184, |
| G_FMAXNUM_IEEE = 185, |
| G_FMINIMUM = 186, |
| G_FMAXIMUM = 187, |
| G_PTR_ADD = 188, |
| G_PTRMASK = 189, |
| G_SMIN = 190, |
| G_SMAX = 191, |
| G_UMIN = 192, |
| G_UMAX = 193, |
| G_ABS = 194, |
| G_LROUND = 195, |
| G_LLROUND = 196, |
| G_BR = 197, |
| G_BRJT = 198, |
| G_INSERT_VECTOR_ELT = 199, |
| G_EXTRACT_VECTOR_ELT = 200, |
| G_SHUFFLE_VECTOR = 201, |
| G_CTTZ = 202, |
| G_CTTZ_ZERO_UNDEF = 203, |
| G_CTLZ = 204, |
| G_CTLZ_ZERO_UNDEF = 205, |
| G_CTPOP = 206, |
| G_BSWAP = 207, |
| G_BITREVERSE = 208, |
| G_FCEIL = 209, |
| G_FCOS = 210, |
| G_FSIN = 211, |
| G_FSQRT = 212, |
| G_FFLOOR = 213, |
| G_FRINT = 214, |
| G_FNEARBYINT = 215, |
| G_ADDRSPACE_CAST = 216, |
| G_BLOCK_ADDR = 217, |
| G_JUMP_TABLE = 218, |
| G_DYN_STACKALLOC = 219, |
| G_STRICT_FADD = 220, |
| G_STRICT_FSUB = 221, |
| G_STRICT_FMUL = 222, |
| G_STRICT_FDIV = 223, |
| G_STRICT_FREM = 224, |
| G_STRICT_FMA = 225, |
| G_STRICT_FSQRT = 226, |
| G_READ_REGISTER = 227, |
| G_WRITE_REGISTER = 228, |
| G_MEMCPY = 229, |
| G_MEMCPY_INLINE = 230, |
| G_MEMMOVE = 231, |
| G_MEMSET = 232, |
| G_BZERO = 233, |
| G_VECREDUCE_SEQ_FADD = 234, |
| G_VECREDUCE_SEQ_FMUL = 235, |
| G_VECREDUCE_FADD = 236, |
| G_VECREDUCE_FMUL = 237, |
| G_VECREDUCE_FMAX = 238, |
| G_VECREDUCE_FMIN = 239, |
| G_VECREDUCE_ADD = 240, |
| G_VECREDUCE_MUL = 241, |
| G_VECREDUCE_AND = 242, |
| G_VECREDUCE_OR = 243, |
| G_VECREDUCE_XOR = 244, |
| G_VECREDUCE_SMAX = 245, |
| G_VECREDUCE_SMIN = 246, |
| G_VECREDUCE_UMAX = 247, |
| G_VECREDUCE_UMIN = 248, |
| G_SBFX = 249, |
| G_UBFX = 250, |
| ABS = 251, |
| ADDSri = 252, |
| ADDSrr = 253, |
| ADDSrsi = 254, |
| ADDSrsr = 255, |
| ADJCALLSTACKDOWN = 256, |
| ADJCALLSTACKUP = 257, |
| ASRi = 258, |
| ASRr = 259, |
| B = 260, |
| BCCZi64 = 261, |
| BCCi64 = 262, |
| BLX_noip = 263, |
| BLX_pred_noip = 264, |
| BL_PUSHLR = 265, |
| BMOVPCB_CALL = 266, |
| BMOVPCRX_CALL = 267, |
| BR_JTadd = 268, |
| BR_JTm_i12 = 269, |
| BR_JTm_rs = 270, |
| BR_JTr = 271, |
| BX_CALL = 272, |
| CMP_SWAP_16 = 273, |
| CMP_SWAP_32 = 274, |
| CMP_SWAP_64 = 275, |
| CMP_SWAP_8 = 276, |
| CONSTPOOL_ENTRY = 277, |
| COPY_STRUCT_BYVAL_I32 = 278, |
| ITasm = 279, |
| Int_eh_sjlj_dispatchsetup = 280, |
| Int_eh_sjlj_longjmp = 281, |
| Int_eh_sjlj_setjmp = 282, |
| Int_eh_sjlj_setjmp_nofp = 283, |
| Int_eh_sjlj_setup_dispatch = 284, |
| JUMPTABLE_ADDRS = 285, |
| JUMPTABLE_INSTS = 286, |
| JUMPTABLE_TBB = 287, |
| JUMPTABLE_TBH = 288, |
| LDMIA_RET = 289, |
| LDRBT_POST = 290, |
| LDRConstPool = 291, |
| LDRHTii = 292, |
| LDRLIT_ga_abs = 293, |
| LDRLIT_ga_pcrel = 294, |
| LDRLIT_ga_pcrel_ldr = 295, |
| LDRSBTii = 296, |
| LDRSHTii = 297, |
| LDRT_POST = 298, |
| LEApcrel = 299, |
| LEApcrelJT = 300, |
| LOADDUAL = 301, |
| LSLi = 302, |
| LSLr = 303, |
| LSRi = 304, |
| LSRr = 305, |
| MEMCPY = 306, |
| MLAv5 = 307, |
| MOVCCi = 308, |
| MOVCCi16 = 309, |
| MOVCCi32imm = 310, |
| MOVCCr = 311, |
| MOVCCsi = 312, |
| MOVCCsr = 313, |
| MOVPCRX = 314, |
| MOVTi16_ga_pcrel = 315, |
| MOV_ga_pcrel = 316, |
| MOV_ga_pcrel_ldr = 317, |
| MOVi16_ga_pcrel = 318, |
| MOVi32imm = 319, |
| MOVsra_flag = 320, |
| MOVsrl_flag = 321, |
| MQPRCopy = 322, |
| MQQPRLoad = 323, |
| MQQPRStore = 324, |
| MQQQQPRLoad = 325, |
| MQQQQPRStore = 326, |
| MULv5 = 327, |
| MVE_MEMCPYLOOPINST = 328, |
| MVE_MEMSETLOOPINST = 329, |
| MVNCCi = 330, |
| PICADD = 331, |
| PICLDR = 332, |
| PICLDRB = 333, |
| PICLDRH = 334, |
| PICLDRSB = 335, |
| PICLDRSH = 336, |
| PICSTR = 337, |
| PICSTRB = 338, |
| PICSTRH = 339, |
| RORi = 340, |
| RORr = 341, |
| RRX = 342, |
| RRXi = 343, |
| RSBSri = 344, |
| RSBSrsi = 345, |
| RSBSrsr = 346, |
| SEH_EpilogEnd = 347, |
| SEH_EpilogStart = 348, |
| SEH_Nop = 349, |
| SEH_Nop_Ret = 350, |
| SEH_PrologEnd = 351, |
| SEH_SaveFRegs = 352, |
| SEH_SaveLR = 353, |
| SEH_SaveRegs = 354, |
| SEH_SaveRegs_Ret = 355, |
| SEH_SaveSP = 356, |
| SEH_StackAlloc = 357, |
| SMLALv5 = 358, |
| SMULLv5 = 359, |
| SPACE = 360, |
| STOREDUAL = 361, |
| STRBT_POST = 362, |
| STRBi_preidx = 363, |
| STRBr_preidx = 364, |
| STRH_preidx = 365, |
| STRT_POST = 366, |
| STRi_preidx = 367, |
| STRr_preidx = 368, |
| SUBS_PC_LR = 369, |
| SUBSri = 370, |
| SUBSrr = 371, |
| SUBSrsi = 372, |
| SUBSrsr = 373, |
| SpeculationBarrierISBDSBEndBB = 374, |
| SpeculationBarrierSBEndBB = 375, |
| TAILJMPd = 376, |
| TAILJMPr = 377, |
| TAILJMPr4 = 378, |
| TCRETURNdi = 379, |
| TCRETURNri = 380, |
| TPsoft = 381, |
| UMLALv5 = 382, |
| UMULLv5 = 383, |
| VLD1LNdAsm_16 = 384, |
| VLD1LNdAsm_32 = 385, |
| VLD1LNdAsm_8 = 386, |
| VLD1LNdWB_fixed_Asm_16 = 387, |
| VLD1LNdWB_fixed_Asm_32 = 388, |
| VLD1LNdWB_fixed_Asm_8 = 389, |
| VLD1LNdWB_register_Asm_16 = 390, |
| VLD1LNdWB_register_Asm_32 = 391, |
| VLD1LNdWB_register_Asm_8 = 392, |
| VLD2LNdAsm_16 = 393, |
| VLD2LNdAsm_32 = 394, |
| VLD2LNdAsm_8 = 395, |
| VLD2LNdWB_fixed_Asm_16 = 396, |
| VLD2LNdWB_fixed_Asm_32 = 397, |
| VLD2LNdWB_fixed_Asm_8 = 398, |
| VLD2LNdWB_register_Asm_16 = 399, |
| VLD2LNdWB_register_Asm_32 = 400, |
| VLD2LNdWB_register_Asm_8 = 401, |
| VLD2LNqAsm_16 = 402, |
| VLD2LNqAsm_32 = 403, |
| VLD2LNqWB_fixed_Asm_16 = 404, |
| VLD2LNqWB_fixed_Asm_32 = 405, |
| VLD2LNqWB_register_Asm_16 = 406, |
| VLD2LNqWB_register_Asm_32 = 407, |
| VLD3DUPdAsm_16 = 408, |
| VLD3DUPdAsm_32 = 409, |
| VLD3DUPdAsm_8 = 410, |
| VLD3DUPdWB_fixed_Asm_16 = 411, |
| VLD3DUPdWB_fixed_Asm_32 = 412, |
| VLD3DUPdWB_fixed_Asm_8 = 413, |
| VLD3DUPdWB_register_Asm_16 = 414, |
| VLD3DUPdWB_register_Asm_32 = 415, |
| VLD3DUPdWB_register_Asm_8 = 416, |
| VLD3DUPqAsm_16 = 417, |
| VLD3DUPqAsm_32 = 418, |
| VLD3DUPqAsm_8 = 419, |
| VLD3DUPqWB_fixed_Asm_16 = 420, |
| VLD3DUPqWB_fixed_Asm_32 = 421, |
| VLD3DUPqWB_fixed_Asm_8 = 422, |
| VLD3DUPqWB_register_Asm_16 = 423, |
| VLD3DUPqWB_register_Asm_32 = 424, |
| VLD3DUPqWB_register_Asm_8 = 425, |
| VLD3LNdAsm_16 = 426, |
| VLD3LNdAsm_32 = 427, |
| VLD3LNdAsm_8 = 428, |
| VLD3LNdWB_fixed_Asm_16 = 429, |
| VLD3LNdWB_fixed_Asm_32 = 430, |
| VLD3LNdWB_fixed_Asm_8 = 431, |
| VLD3LNdWB_register_Asm_16 = 432, |
| VLD3LNdWB_register_Asm_32 = 433, |
| VLD3LNdWB_register_Asm_8 = 434, |
| VLD3LNqAsm_16 = 435, |
| VLD3LNqAsm_32 = 436, |
| VLD3LNqWB_fixed_Asm_16 = 437, |
| VLD3LNqWB_fixed_Asm_32 = 438, |
| VLD3LNqWB_register_Asm_16 = 439, |
| VLD3LNqWB_register_Asm_32 = 440, |
| VLD3dAsm_16 = 441, |
| VLD3dAsm_32 = 442, |
| VLD3dAsm_8 = 443, |
| VLD3dWB_fixed_Asm_16 = 444, |
| VLD3dWB_fixed_Asm_32 = 445, |
| VLD3dWB_fixed_Asm_8 = 446, |
| VLD3dWB_register_Asm_16 = 447, |
| VLD3dWB_register_Asm_32 = 448, |
| VLD3dWB_register_Asm_8 = 449, |
| VLD3qAsm_16 = 450, |
| VLD3qAsm_32 = 451, |
| VLD3qAsm_8 = 452, |
| VLD3qWB_fixed_Asm_16 = 453, |
| VLD3qWB_fixed_Asm_32 = 454, |
| VLD3qWB_fixed_Asm_8 = 455, |
| VLD3qWB_register_Asm_16 = 456, |
| VLD3qWB_register_Asm_32 = 457, |
| VLD3qWB_register_Asm_8 = 458, |
| VLD4DUPdAsm_16 = 459, |
| VLD4DUPdAsm_32 = 460, |
| VLD4DUPdAsm_8 = 461, |
| VLD4DUPdWB_fixed_Asm_16 = 462, |
| VLD4DUPdWB_fixed_Asm_32 = 463, |
| VLD4DUPdWB_fixed_Asm_8 = 464, |
| VLD4DUPdWB_register_Asm_16 = 465, |
| VLD4DUPdWB_register_Asm_32 = 466, |
| VLD4DUPdWB_register_Asm_8 = 467, |
| VLD4DUPqAsm_16 = 468, |
| VLD4DUPqAsm_32 = 469, |
| VLD4DUPqAsm_8 = 470, |
| VLD4DUPqWB_fixed_Asm_16 = 471, |
| VLD4DUPqWB_fixed_Asm_32 = 472, |
| VLD4DUPqWB_fixed_Asm_8 = 473, |
| VLD4DUPqWB_register_Asm_16 = 474, |
| VLD4DUPqWB_register_Asm_32 = 475, |
| VLD4DUPqWB_register_Asm_8 = 476, |
| VLD4LNdAsm_16 = 477, |
| VLD4LNdAsm_32 = 478, |
| VLD4LNdAsm_8 = 479, |
| VLD4LNdWB_fixed_Asm_16 = 480, |
| VLD4LNdWB_fixed_Asm_32 = 481, |
| VLD4LNdWB_fixed_Asm_8 = 482, |
| VLD4LNdWB_register_Asm_16 = 483, |
| VLD4LNdWB_register_Asm_32 = 484, |
| VLD4LNdWB_register_Asm_8 = 485, |
| VLD4LNqAsm_16 = 486, |
| VLD4LNqAsm_32 = 487, |
| VLD4LNqWB_fixed_Asm_16 = 488, |
| VLD4LNqWB_fixed_Asm_32 = 489, |
| VLD4LNqWB_register_Asm_16 = 490, |
| VLD4LNqWB_register_Asm_32 = 491, |
| VLD4dAsm_16 = 492, |
| VLD4dAsm_32 = 493, |
| VLD4dAsm_8 = 494, |
| VLD4dWB_fixed_Asm_16 = 495, |
| VLD4dWB_fixed_Asm_32 = 496, |
| VLD4dWB_fixed_Asm_8 = 497, |
| VLD4dWB_register_Asm_16 = 498, |
| VLD4dWB_register_Asm_32 = 499, |
| VLD4dWB_register_Asm_8 = 500, |
| VLD4qAsm_16 = 501, |
| VLD4qAsm_32 = 502, |
| VLD4qAsm_8 = 503, |
| VLD4qWB_fixed_Asm_16 = 504, |
| VLD4qWB_fixed_Asm_32 = 505, |
| VLD4qWB_fixed_Asm_8 = 506, |
| VLD4qWB_register_Asm_16 = 507, |
| VLD4qWB_register_Asm_32 = 508, |
| VLD4qWB_register_Asm_8 = 509, |
| VMOVD0 = 510, |
| VMOVDcc = 511, |
| VMOVHcc = 512, |
| VMOVQ0 = 513, |
| VMOVScc = 514, |
| VST1LNdAsm_16 = 515, |
| VST1LNdAsm_32 = 516, |
| VST1LNdAsm_8 = 517, |
| VST1LNdWB_fixed_Asm_16 = 518, |
| VST1LNdWB_fixed_Asm_32 = 519, |
| VST1LNdWB_fixed_Asm_8 = 520, |
| VST1LNdWB_register_Asm_16 = 521, |
| VST1LNdWB_register_Asm_32 = 522, |
| VST1LNdWB_register_Asm_8 = 523, |
| VST2LNdAsm_16 = 524, |
| VST2LNdAsm_32 = 525, |
| VST2LNdAsm_8 = 526, |
| VST2LNdWB_fixed_Asm_16 = 527, |
| VST2LNdWB_fixed_Asm_32 = 528, |
| VST2LNdWB_fixed_Asm_8 = 529, |
| VST2LNdWB_register_Asm_16 = 530, |
| VST2LNdWB_register_Asm_32 = 531, |
| VST2LNdWB_register_Asm_8 = 532, |
| VST2LNqAsm_16 = 533, |
| VST2LNqAsm_32 = 534, |
| VST2LNqWB_fixed_Asm_16 = 535, |
| VST2LNqWB_fixed_Asm_32 = 536, |
| VST2LNqWB_register_Asm_16 = 537, |
| VST2LNqWB_register_Asm_32 = 538, |
| VST3LNdAsm_16 = 539, |
| VST3LNdAsm_32 = 540, |
| VST3LNdAsm_8 = 541, |
| VST3LNdWB_fixed_Asm_16 = 542, |
| VST3LNdWB_fixed_Asm_32 = 543, |
| VST3LNdWB_fixed_Asm_8 = 544, |
| VST3LNdWB_register_Asm_16 = 545, |
| VST3LNdWB_register_Asm_32 = 546, |
| VST3LNdWB_register_Asm_8 = 547, |
| VST3LNqAsm_16 = 548, |
| VST3LNqAsm_32 = 549, |
| VST3LNqWB_fixed_Asm_16 = 550, |
| VST3LNqWB_fixed_Asm_32 = 551, |
| VST3LNqWB_register_Asm_16 = 552, |
| VST3LNqWB_register_Asm_32 = 553, |
| VST3dAsm_16 = 554, |
| VST3dAsm_32 = 555, |
| VST3dAsm_8 = 556, |
| VST3dWB_fixed_Asm_16 = 557, |
| VST3dWB_fixed_Asm_32 = 558, |
| VST3dWB_fixed_Asm_8 = 559, |
| VST3dWB_register_Asm_16 = 560, |
| VST3dWB_register_Asm_32 = 561, |
| VST3dWB_register_Asm_8 = 562, |
| VST3qAsm_16 = 563, |
| VST3qAsm_32 = 564, |
| VST3qAsm_8 = 565, |
| VST3qWB_fixed_Asm_16 = 566, |
| VST3qWB_fixed_Asm_32 = 567, |
| VST3qWB_fixed_Asm_8 = 568, |
| VST3qWB_register_Asm_16 = 569, |
| VST3qWB_register_Asm_32 = 570, |
| VST3qWB_register_Asm_8 = 571, |
| VST4LNdAsm_16 = 572, |
| VST4LNdAsm_32 = 573, |
| VST4LNdAsm_8 = 574, |
| VST4LNdWB_fixed_Asm_16 = 575, |
| VST4LNdWB_fixed_Asm_32 = 576, |
| VST4LNdWB_fixed_Asm_8 = 577, |
| VST4LNdWB_register_Asm_16 = 578, |
| VST4LNdWB_register_Asm_32 = 579, |
| VST4LNdWB_register_Asm_8 = 580, |
| VST4LNqAsm_16 = 581, |
| VST4LNqAsm_32 = 582, |
| VST4LNqWB_fixed_Asm_16 = 583, |
| VST4LNqWB_fixed_Asm_32 = 584, |
| VST4LNqWB_register_Asm_16 = 585, |
| VST4LNqWB_register_Asm_32 = 586, |
| VST4dAsm_16 = 587, |
| VST4dAsm_32 = 588, |
| VST4dAsm_8 = 589, |
| VST4dWB_fixed_Asm_16 = 590, |
| VST4dWB_fixed_Asm_32 = 591, |
| VST4dWB_fixed_Asm_8 = 592, |
| VST4dWB_register_Asm_16 = 593, |
| VST4dWB_register_Asm_32 = 594, |
| VST4dWB_register_Asm_8 = 595, |
| VST4qAsm_16 = 596, |
| VST4qAsm_32 = 597, |
| VST4qAsm_8 = 598, |
| VST4qWB_fixed_Asm_16 = 599, |
| VST4qWB_fixed_Asm_32 = 600, |
| VST4qWB_fixed_Asm_8 = 601, |
| VST4qWB_register_Asm_16 = 602, |
| VST4qWB_register_Asm_32 = 603, |
| VST4qWB_register_Asm_8 = 604, |
| WIN__CHKSTK = 605, |
| WIN__DBZCHK = 606, |
| t2ABS = 607, |
| t2ADDSri = 608, |
| t2ADDSrr = 609, |
| t2ADDSrs = 610, |
| t2BF_LabelPseudo = 611, |
| t2BR_JT = 612, |
| t2CALL_BTI = 613, |
| t2DoLoopStart = 614, |
| t2DoLoopStartTP = 615, |
| t2LDMIA_RET = 616, |
| t2LDRBpcrel = 617, |
| t2LDRConstPool = 618, |
| t2LDRHpcrel = 619, |
| t2LDRLIT_ga_pcrel = 620, |
| t2LDRSBpcrel = 621, |
| t2LDRSHpcrel = 622, |
| t2LDR_POST_imm = 623, |
| t2LDR_PRE_imm = 624, |
| t2LDRpci_pic = 625, |
| t2LDRpcrel = 626, |
| t2LEApcrel = 627, |
| t2LEApcrelJT = 628, |
| t2LoopDec = 629, |
| t2LoopEnd = 630, |
| t2LoopEndDec = 631, |
| t2MOVCCasr = 632, |
| t2MOVCCi = 633, |
| t2MOVCCi16 = 634, |
| t2MOVCCi32imm = 635, |
| t2MOVCClsl = 636, |
| t2MOVCClsr = 637, |
| t2MOVCCr = 638, |
| t2MOVCCror = 639, |
| t2MOVSsi = 640, |
| t2MOVSsr = 641, |
| t2MOVTi16_ga_pcrel = 642, |
| t2MOV_ga_pcrel = 643, |
| t2MOVi16_ga_pcrel = 644, |
| t2MOVi32imm = 645, |
| t2MOVsi = 646, |
| t2MOVsr = 647, |
| t2MVNCCi = 648, |
| t2RSBSri = 649, |
| t2RSBSrs = 650, |
| t2STRB_preidx = 651, |
| t2STRH_preidx = 652, |
| t2STR_POST_imm = 653, |
| t2STR_PRE_imm = 654, |
| t2STR_preidx = 655, |
| t2SUBSri = 656, |
| t2SUBSrr = 657, |
| t2SUBSrs = 658, |
| t2SpeculationBarrierISBDSBEndBB = 659, |
| t2SpeculationBarrierSBEndBB = 660, |
| t2TBB_JT = 661, |
| t2TBH_JT = 662, |
| t2WhileLoopSetup = 663, |
| t2WhileLoopStart = 664, |
| t2WhileLoopStartLR = 665, |
| t2WhileLoopStartTP = 666, |
| tADCS = 667, |
| tADDSi3 = 668, |
| tADDSi8 = 669, |
| tADDSrr = 670, |
| tADDframe = 671, |
| tADJCALLSTACKDOWN = 672, |
| tADJCALLSTACKUP = 673, |
| tBLXNS_CALL = 674, |
| tBLXr_noip = 675, |
| tBL_PUSHLR = 676, |
| tBRIND = 677, |
| tBR_JTr = 678, |
| tBXNS_RET = 679, |
| tBX_CALL = 680, |
| tBX_RET = 681, |
| tBX_RET_vararg = 682, |
| tBfar = 683, |
| tCMP_SWAP_16 = 684, |
| tCMP_SWAP_32 = 685, |
| tCMP_SWAP_8 = 686, |
| tLDMIA_UPD = 687, |
| tLDRConstPool = 688, |
| tLDRLIT_ga_abs = 689, |
| tLDRLIT_ga_pcrel = 690, |
| tLDR_postidx = 691, |
| tLDRpci_pic = 692, |
| tLEApcrel = 693, |
| tLEApcrelJT = 694, |
| tLSLSri = 695, |
| tMOVCCr_pseudo = 696, |
| tPOP_RET = 697, |
| tRSBS = 698, |
| tSBCS = 699, |
| tSUBSi3 = 700, |
| tSUBSi8 = 701, |
| tSUBSrr = 702, |
| tTAILJMPd = 703, |
| tTAILJMPdND = 704, |
| tTAILJMPr = 705, |
| tTBB_JT = 706, |
| tTBH_JT = 707, |
| tTPsoft = 708, |
| ADCri = 709, |
| ADCrr = 710, |
| ADCrsi = 711, |
| ADCrsr = 712, |
| ADDri = 713, |
| ADDrr = 714, |
| ADDrsi = 715, |
| ADDrsr = 716, |
| ADR = 717, |
| AESD = 718, |
| AESE = 719, |
| AESIMC = 720, |
| AESMC = 721, |
| ANDri = 722, |
| ANDrr = 723, |
| ANDrsi = 724, |
| ANDrsr = 725, |
| BF16VDOTI_VDOTD = 726, |
| BF16VDOTI_VDOTQ = 727, |
| BF16VDOTS_VDOTD = 728, |
| BF16VDOTS_VDOTQ = 729, |
| BF16_VCVT = 730, |
| BF16_VCVTB = 731, |
| BF16_VCVTT = 732, |
| BFC = 733, |
| BFI = 734, |
| BICri = 735, |
| BICrr = 736, |
| BICrsi = 737, |
| BICrsr = 738, |
| BKPT = 739, |
| BL = 740, |
| BLX = 741, |
| BLX_pred = 742, |
| BLXi = 743, |
| BL_pred = 744, |
| BX = 745, |
| BXJ = 746, |
| BX_RET = 747, |
| BX_pred = 748, |
| Bcc = 749, |
| CDE_CX1 = 750, |
| CDE_CX1A = 751, |
| CDE_CX1D = 752, |
| CDE_CX1DA = 753, |
| CDE_CX2 = 754, |
| CDE_CX2A = 755, |
| CDE_CX2D = 756, |
| CDE_CX2DA = 757, |
| CDE_CX3 = 758, |
| CDE_CX3A = 759, |
| CDE_CX3D = 760, |
| CDE_CX3DA = 761, |
| CDE_VCX1A_fpdp = 762, |
| CDE_VCX1A_fpsp = 763, |
| CDE_VCX1A_vec = 764, |
| CDE_VCX1_fpdp = 765, |
| CDE_VCX1_fpsp = 766, |
| CDE_VCX1_vec = 767, |
| CDE_VCX2A_fpdp = 768, |
| CDE_VCX2A_fpsp = 769, |
| CDE_VCX2A_vec = 770, |
| CDE_VCX2_fpdp = 771, |
| CDE_VCX2_fpsp = 772, |
| CDE_VCX2_vec = 773, |
| CDE_VCX3A_fpdp = 774, |
| CDE_VCX3A_fpsp = 775, |
| CDE_VCX3A_vec = 776, |
| CDE_VCX3_fpdp = 777, |
| CDE_VCX3_fpsp = 778, |
| CDE_VCX3_vec = 779, |
| CDP = 780, |
| CDP2 = 781, |
| CLREX = 782, |
| CLZ = 783, |
| CMNri = 784, |
| CMNzrr = 785, |
| CMNzrsi = 786, |
| CMNzrsr = 787, |
| CMPri = 788, |
| CMPrr = 789, |
| CMPrsi = 790, |
| CMPrsr = 791, |
| CPS1p = 792, |
| CPS2p = 793, |
| CPS3p = 794, |
| CRC32B = 795, |
| CRC32CB = 796, |
| CRC32CH = 797, |
| CRC32CW = 798, |
| CRC32H = 799, |
| CRC32W = 800, |
| DBG = 801, |
| DMB = 802, |
| DSB = 803, |
| EORri = 804, |
| EORrr = 805, |
| EORrsi = 806, |
| EORrsr = 807, |
| ERET = 808, |
| FCONSTD = 809, |
| FCONSTH = 810, |
| FCONSTS = 811, |
| FLDMXDB_UPD = 812, |
| FLDMXIA = 813, |
| FLDMXIA_UPD = 814, |
| FMSTAT = 815, |
| FSTMXDB_UPD = 816, |
| FSTMXIA = 817, |
| FSTMXIA_UPD = 818, |
| HINT = 819, |
| HLT = 820, |
| HVC = 821, |
| ISB = 822, |
| LDA = 823, |
| LDAB = 824, |
| LDAEX = 825, |
| LDAEXB = 826, |
| LDAEXD = 827, |
| LDAEXH = 828, |
| LDAH = 829, |
| LDC2L_OFFSET = 830, |
| LDC2L_OPTION = 831, |
| LDC2L_POST = 832, |
| LDC2L_PRE = 833, |
| LDC2_OFFSET = 834, |
| LDC2_OPTION = 835, |
| LDC2_POST = 836, |
| LDC2_PRE = 837, |
| LDCL_OFFSET = 838, |
| LDCL_OPTION = 839, |
| LDCL_POST = 840, |
| LDCL_PRE = 841, |
| LDC_OFFSET = 842, |
| LDC_OPTION = 843, |
| LDC_POST = 844, |
| LDC_PRE = 845, |
| LDMDA = 846, |
| LDMDA_UPD = 847, |
| LDMDB = 848, |
| LDMDB_UPD = 849, |
| LDMIA = 850, |
| LDMIA_UPD = 851, |
| LDMIB = 852, |
| LDMIB_UPD = 853, |
| LDRBT_POST_IMM = 854, |
| LDRBT_POST_REG = 855, |
| LDRB_POST_IMM = 856, |
| LDRB_POST_REG = 857, |
| LDRB_PRE_IMM = 858, |
| LDRB_PRE_REG = 859, |
| LDRBi12 = 860, |
| LDRBrs = 861, |
| LDRD = 862, |
| LDRD_POST = 863, |
| LDRD_PRE = 864, |
| LDREX = 865, |
| LDREXB = 866, |
| LDREXD = 867, |
| LDREXH = 868, |
| LDRH = 869, |
| LDRHTi = 870, |
| LDRHTr = 871, |
| LDRH_POST = 872, |
| LDRH_PRE = 873, |
| LDRSB = 874, |
| LDRSBTi = 875, |
| LDRSBTr = 876, |
| LDRSB_POST = 877, |
| LDRSB_PRE = 878, |
| LDRSH = 879, |
| LDRSHTi = 880, |
| LDRSHTr = 881, |
| LDRSH_POST = 882, |
| LDRSH_PRE = 883, |
| LDRT_POST_IMM = 884, |
| LDRT_POST_REG = 885, |
| LDR_POST_IMM = 886, |
| LDR_POST_REG = 887, |
| LDR_PRE_IMM = 888, |
| LDR_PRE_REG = 889, |
| LDRcp = 890, |
| LDRi12 = 891, |
| LDRrs = 892, |
| MCR = 893, |
| MCR2 = 894, |
| MCRR = 895, |
| MCRR2 = 896, |
| MLA = 897, |
| MLS = 898, |
| MOVPCLR = 899, |
| MOVTi16 = 900, |
| MOVi = 901, |
| MOVi16 = 902, |
| MOVr = 903, |
| MOVr_TC = 904, |
| MOVsi = 905, |
| MOVsr = 906, |
| MRC = 907, |
| MRC2 = 908, |
| MRRC = 909, |
| MRRC2 = 910, |
| MRS = 911, |
| MRSbanked = 912, |
| MRSsys = 913, |
| MSR = 914, |
| MSRbanked = 915, |
| MSRi = 916, |
| MUL = 917, |
| MVE_ASRLi = 918, |
| MVE_ASRLr = 919, |
| MVE_DLSTP_16 = 920, |
| MVE_DLSTP_32 = 921, |
| MVE_DLSTP_64 = 922, |
| MVE_DLSTP_8 = 923, |
| MVE_LCTP = 924, |
| MVE_LETP = 925, |
| MVE_LSLLi = 926, |
| MVE_LSLLr = 927, |
| MVE_LSRL = 928, |
| MVE_SQRSHR = 929, |
| MVE_SQRSHRL = 930, |
| MVE_SQSHL = 931, |
| MVE_SQSHLL = 932, |
| MVE_SRSHR = 933, |
| MVE_SRSHRL = 934, |
| MVE_UQRSHL = 935, |
| MVE_UQRSHLL = 936, |
| MVE_UQSHL = 937, |
| MVE_UQSHLL = 938, |
| MVE_URSHR = 939, |
| MVE_URSHRL = 940, |
| MVE_VABAVs16 = 941, |
| MVE_VABAVs32 = 942, |
| MVE_VABAVs8 = 943, |
| MVE_VABAVu16 = 944, |
| MVE_VABAVu32 = 945, |
| MVE_VABAVu8 = 946, |
| MVE_VABDf16 = 947, |
| MVE_VABDf32 = 948, |
| MVE_VABDs16 = 949, |
| MVE_VABDs32 = 950, |
| MVE_VABDs8 = 951, |
| MVE_VABDu16 = 952, |
| MVE_VABDu32 = 953, |
| MVE_VABDu8 = 954, |
| MVE_VABSf16 = 955, |
| MVE_VABSf32 = 956, |
| MVE_VABSs16 = 957, |
| MVE_VABSs32 = 958, |
| MVE_VABSs8 = 959, |
| MVE_VADC = 960, |
| MVE_VADCI = 961, |
| MVE_VADDLVs32acc = 962, |
| MVE_VADDLVs32no_acc = 963, |
| MVE_VADDLVu32acc = 964, |
| MVE_VADDLVu32no_acc = 965, |
| MVE_VADDVs16acc = 966, |
| MVE_VADDVs16no_acc = 967, |
| MVE_VADDVs32acc = 968, |
| MVE_VADDVs32no_acc = 969, |
| MVE_VADDVs8acc = 970, |
| MVE_VADDVs8no_acc = 971, |
| MVE_VADDVu16acc = 972, |
| MVE_VADDVu16no_acc = 973, |
| MVE_VADDVu32acc = 974, |
| MVE_VADDVu32no_acc = 975, |
| MVE_VADDVu8acc = 976, |
| MVE_VADDVu8no_acc = 977, |
| MVE_VADD_qr_f16 = 978, |
| MVE_VADD_qr_f32 = 979, |
| MVE_VADD_qr_i16 = 980, |
| MVE_VADD_qr_i32 = 981, |
| MVE_VADD_qr_i8 = 982, |
| MVE_VADDf16 = 983, |
| MVE_VADDf32 = 984, |
| MVE_VADDi16 = 985, |
| MVE_VADDi32 = 986, |
| MVE_VADDi8 = 987, |
| MVE_VAND = 988, |
| MVE_VBIC = 989, |
| MVE_VBICimmi16 = 990, |
| MVE_VBICimmi32 = 991, |
| MVE_VBRSR16 = 992, |
| MVE_VBRSR32 = 993, |
| MVE_VBRSR8 = 994, |
| MVE_VCADDf16 = 995, |
| MVE_VCADDf32 = 996, |
| MVE_VCADDi16 = 997, |
| MVE_VCADDi32 = 998, |
| MVE_VCADDi8 = 999, |
| MVE_VCLSs16 = 1000, |
| MVE_VCLSs32 = 1001, |
| MVE_VCLSs8 = 1002, |
| MVE_VCLZs16 = 1003, |
| MVE_VCLZs32 = 1004, |
| MVE_VCLZs8 = 1005, |
| MVE_VCMLAf16 = 1006, |
| MVE_VCMLAf32 = 1007, |
| MVE_VCMPf16 = 1008, |
| MVE_VCMPf16r = 1009, |
| MVE_VCMPf32 = 1010, |
| MVE_VCMPf32r = 1011, |
| MVE_VCMPi16 = 1012, |
| MVE_VCMPi16r = 1013, |
| MVE_VCMPi32 = 1014, |
| MVE_VCMPi32r = 1015, |
| MVE_VCMPi8 = 1016, |
| MVE_VCMPi8r = 1017, |
| MVE_VCMPs16 = 1018, |
| MVE_VCMPs16r = 1019, |
| MVE_VCMPs32 = 1020, |
| MVE_VCMPs32r = 1021, |
| MVE_VCMPs8 = 1022, |
| MVE_VCMPs8r = 1023, |
| MVE_VCMPu16 = 1024, |
| MVE_VCMPu16r = 1025, |
| MVE_VCMPu32 = 1026, |
| MVE_VCMPu32r = 1027, |
| MVE_VCMPu8 = 1028, |
| MVE_VCMPu8r = 1029, |
| MVE_VCMULf16 = 1030, |
| MVE_VCMULf32 = 1031, |
| MVE_VCTP16 = 1032, |
| MVE_VCTP32 = 1033, |
| MVE_VCTP64 = 1034, |
| MVE_VCTP8 = 1035, |
| MVE_VCVTf16f32bh = 1036, |
| MVE_VCVTf16f32th = 1037, |
| MVE_VCVTf16s16_fix = 1038, |
| MVE_VCVTf16s16n = 1039, |
| MVE_VCVTf16u16_fix = 1040, |
| MVE_VCVTf16u16n = 1041, |
| MVE_VCVTf32f16bh = 1042, |
| MVE_VCVTf32f16th = 1043, |
| MVE_VCVTf32s32_fix = 1044, |
| MVE_VCVTf32s32n = 1045, |
| MVE_VCVTf32u32_fix = 1046, |
| MVE_VCVTf32u32n = 1047, |
| MVE_VCVTs16f16_fix = 1048, |
| MVE_VCVTs16f16a = 1049, |
| MVE_VCVTs16f16m = 1050, |
| MVE_VCVTs16f16n = 1051, |
| MVE_VCVTs16f16p = 1052, |
| MVE_VCVTs16f16z = 1053, |
| MVE_VCVTs32f32_fix = 1054, |
| MVE_VCVTs32f32a = 1055, |
| MVE_VCVTs32f32m = 1056, |
| MVE_VCVTs32f32n = 1057, |
| MVE_VCVTs32f32p = 1058, |
| MVE_VCVTs32f32z = 1059, |
| MVE_VCVTu16f16_fix = 1060, |
| MVE_VCVTu16f16a = 1061, |
| MVE_VCVTu16f16m = 1062, |
| MVE_VCVTu16f16n = 1063, |
| MVE_VCVTu16f16p = 1064, |
| MVE_VCVTu16f16z = 1065, |
| MVE_VCVTu32f32_fix = 1066, |
| MVE_VCVTu32f32a = 1067, |
| MVE_VCVTu32f32m = 1068, |
| MVE_VCVTu32f32n = 1069, |
| MVE_VCVTu32f32p = 1070, |
| MVE_VCVTu32f32z = 1071, |
| MVE_VDDUPu16 = 1072, |
| MVE_VDDUPu32 = 1073, |
| MVE_VDDUPu8 = 1074, |
| MVE_VDUP16 = 1075, |
| MVE_VDUP32 = 1076, |
| MVE_VDUP8 = 1077, |
| MVE_VDWDUPu16 = 1078, |
| MVE_VDWDUPu32 = 1079, |
| MVE_VDWDUPu8 = 1080, |
| MVE_VEOR = 1081, |
| MVE_VFMA_qr_Sf16 = 1082, |
| MVE_VFMA_qr_Sf32 = 1083, |
| MVE_VFMA_qr_f16 = 1084, |
| MVE_VFMA_qr_f32 = 1085, |
| MVE_VFMAf16 = 1086, |
| MVE_VFMAf32 = 1087, |
| MVE_VFMSf16 = 1088, |
| MVE_VFMSf32 = 1089, |
| MVE_VHADD_qr_s16 = 1090, |
| MVE_VHADD_qr_s32 = 1091, |
| MVE_VHADD_qr_s8 = 1092, |
| MVE_VHADD_qr_u16 = 1093, |
| MVE_VHADD_qr_u32 = 1094, |
| MVE_VHADD_qr_u8 = 1095, |
| MVE_VHADDs16 = 1096, |
| MVE_VHADDs32 = 1097, |
| MVE_VHADDs8 = 1098, |
| MVE_VHADDu16 = 1099, |
| MVE_VHADDu32 = 1100, |
| MVE_VHADDu8 = 1101, |
| MVE_VHCADDs16 = 1102, |
| MVE_VHCADDs32 = 1103, |
| MVE_VHCADDs8 = 1104, |
| MVE_VHSUB_qr_s16 = 1105, |
| MVE_VHSUB_qr_s32 = 1106, |
| MVE_VHSUB_qr_s8 = 1107, |
| MVE_VHSUB_qr_u16 = 1108, |
| MVE_VHSUB_qr_u32 = 1109, |
| MVE_VHSUB_qr_u8 = 1110, |
| MVE_VHSUBs16 = 1111, |
| MVE_VHSUBs32 = 1112, |
| MVE_VHSUBs8 = 1113, |
| MVE_VHSUBu16 = 1114, |
| MVE_VHSUBu32 = 1115, |
| MVE_VHSUBu8 = 1116, |
| MVE_VIDUPu16 = 1117, |
| MVE_VIDUPu32 = 1118, |
| MVE_VIDUPu8 = 1119, |
| MVE_VIWDUPu16 = 1120, |
| MVE_VIWDUPu32 = 1121, |
| MVE_VIWDUPu8 = 1122, |
| MVE_VLD20_16 = 1123, |
| MVE_VLD20_16_wb = 1124, |
| MVE_VLD20_32 = 1125, |
| MVE_VLD20_32_wb = 1126, |
| MVE_VLD20_8 = 1127, |
| MVE_VLD20_8_wb = 1128, |
| MVE_VLD21_16 = 1129, |
| MVE_VLD21_16_wb = 1130, |
| MVE_VLD21_32 = 1131, |
| MVE_VLD21_32_wb = 1132, |
| MVE_VLD21_8 = 1133, |
| MVE_VLD21_8_wb = 1134, |
| MVE_VLD40_16 = 1135, |
| MVE_VLD40_16_wb = 1136, |
| MVE_VLD40_32 = 1137, |
| MVE_VLD40_32_wb = 1138, |
| MVE_VLD40_8 = 1139, |
| MVE_VLD40_8_wb = 1140, |
| MVE_VLD41_16 = 1141, |
| MVE_VLD41_16_wb = 1142, |
| MVE_VLD41_32 = 1143, |
| MVE_VLD41_32_wb = 1144, |
| MVE_VLD41_8 = 1145, |
| MVE_VLD41_8_wb = 1146, |
| MVE_VLD42_16 = 1147, |
| MVE_VLD42_16_wb = 1148, |
| MVE_VLD42_32 = 1149, |
| MVE_VLD42_32_wb = 1150, |
| MVE_VLD42_8 = 1151, |
| MVE_VLD42_8_wb = 1152, |
| MVE_VLD43_16 = 1153, |
| MVE_VLD43_16_wb = 1154, |
| MVE_VLD43_32 = 1155, |
| MVE_VLD43_32_wb = 1156, |
| MVE_VLD43_8 = 1157, |
| MVE_VLD43_8_wb = 1158, |
| MVE_VLDRBS16 = 1159, |
| MVE_VLDRBS16_post = 1160, |
| MVE_VLDRBS16_pre = 1161, |
| MVE_VLDRBS16_rq = 1162, |
| MVE_VLDRBS32 = 1163, |
| MVE_VLDRBS32_post = 1164, |
| MVE_VLDRBS32_pre = 1165, |
| MVE_VLDRBS32_rq = 1166, |
| MVE_VLDRBU16 = 1167, |
| MVE_VLDRBU16_post = 1168, |
| MVE_VLDRBU16_pre = 1169, |
| MVE_VLDRBU16_rq = 1170, |
| MVE_VLDRBU32 = 1171, |
| MVE_VLDRBU32_post = 1172, |
| MVE_VLDRBU32_pre = 1173, |
| MVE_VLDRBU32_rq = 1174, |
| MVE_VLDRBU8 = 1175, |
| MVE_VLDRBU8_post = 1176, |
| MVE_VLDRBU8_pre = 1177, |
| MVE_VLDRBU8_rq = 1178, |
| MVE_VLDRDU64_qi = 1179, |
| MVE_VLDRDU64_qi_pre = 1180, |
| MVE_VLDRDU64_rq = 1181, |
| MVE_VLDRDU64_rq_u = 1182, |
| MVE_VLDRHS32 = 1183, |
| MVE_VLDRHS32_post = 1184, |
| MVE_VLDRHS32_pre = 1185, |
| MVE_VLDRHS32_rq = 1186, |
| MVE_VLDRHS32_rq_u = 1187, |
| MVE_VLDRHU16 = 1188, |
| MVE_VLDRHU16_post = 1189, |
| MVE_VLDRHU16_pre = 1190, |
| MVE_VLDRHU16_rq = 1191, |
| MVE_VLDRHU16_rq_u = 1192, |
| MVE_VLDRHU32 = 1193, |
| MVE_VLDRHU32_post = 1194, |
| MVE_VLDRHU32_pre = 1195, |
| MVE_VLDRHU32_rq = 1196, |
| MVE_VLDRHU32_rq_u = 1197, |
| MVE_VLDRWU32 = 1198, |
| MVE_VLDRWU32_post = 1199, |
| MVE_VLDRWU32_pre = 1200, |
| MVE_VLDRWU32_qi = 1201, |
| MVE_VLDRWU32_qi_pre = 1202, |
| MVE_VLDRWU32_rq = 1203, |
| MVE_VLDRWU32_rq_u = 1204, |
| MVE_VMAXAVs16 = 1205, |
| MVE_VMAXAVs32 = 1206, |
| MVE_VMAXAVs8 = 1207, |
| MVE_VMAXAs16 = 1208, |
| MVE_VMAXAs32 = 1209, |
| MVE_VMAXAs8 = 1210, |
| MVE_VMAXNMAVf16 = 1211, |
| MVE_VMAXNMAVf32 = 1212, |
| MVE_VMAXNMAf16 = 1213, |
| MVE_VMAXNMAf32 = 1214, |
| MVE_VMAXNMVf16 = 1215, |
| MVE_VMAXNMVf32 = 1216, |
| MVE_VMAXNMf16 = 1217, |
| MVE_VMAXNMf32 = 1218, |
| MVE_VMAXVs16 = 1219, |
| MVE_VMAXVs32 = 1220, |
| MVE_VMAXVs8 = 1221, |
| MVE_VMAXVu16 = 1222, |
| MVE_VMAXVu32 = 1223, |
| MVE_VMAXVu8 = 1224, |
| MVE_VMAXs16 = 1225, |
| MVE_VMAXs32 = 1226, |
| MVE_VMAXs8 = 1227, |
| MVE_VMAXu16 = 1228, |
| MVE_VMAXu32 = 1229, |
| MVE_VMAXu8 = 1230, |
| MVE_VMINAVs16 = 1231, |
| MVE_VMINAVs32 = 1232, |
| MVE_VMINAVs8 = 1233, |
| MVE_VMINAs16 = 1234, |
| MVE_VMINAs32 = 1235, |
| MVE_VMINAs8 = 1236, |
| MVE_VMINNMAVf16 = 1237, |
| MVE_VMINNMAVf32 = 1238, |
| MVE_VMINNMAf16 = 1239, |
| MVE_VMINNMAf32 = 1240, |
| MVE_VMINNMVf16 = 1241, |
| MVE_VMINNMVf32 = 1242, |
| MVE_VMINNMf16 = 1243, |
| MVE_VMINNMf32 = 1244, |
| MVE_VMINVs16 = 1245, |
| MVE_VMINVs32 = 1246, |
| MVE_VMINVs8 = 1247, |
| MVE_VMINVu16 = 1248, |
| MVE_VMINVu32 = 1249, |
| MVE_VMINVu8 = 1250, |
| MVE_VMINs16 = 1251, |
| MVE_VMINs32 = 1252, |
| MVE_VMINs8 = 1253, |
| MVE_VMINu16 = 1254, |
| MVE_VMINu32 = 1255, |
| MVE_VMINu8 = 1256, |
| MVE_VMLADAVas16 = 1257, |
| MVE_VMLADAVas32 = 1258, |
| MVE_VMLADAVas8 = 1259, |
| MVE_VMLADAVau16 = 1260, |
| MVE_VMLADAVau32 = 1261, |
| MVE_VMLADAVau8 = 1262, |
| MVE_VMLADAVaxs16 = 1263, |
| MVE_VMLADAVaxs32 = 1264, |
| MVE_VMLADAVaxs8 = 1265, |
| MVE_VMLADAVs16 = 1266, |
| MVE_VMLADAVs32 = 1267, |
| MVE_VMLADAVs8 = 1268, |
| MVE_VMLADAVu16 = 1269, |
| MVE_VMLADAVu32 = 1270, |
| MVE_VMLADAVu8 = 1271, |
| MVE_VMLADAVxs16 = 1272, |
| MVE_VMLADAVxs32 = 1273, |
| MVE_VMLADAVxs8 = 1274, |
| MVE_VMLALDAVas16 = 1275, |
| MVE_VMLALDAVas32 = 1276, |
| MVE_VMLALDAVau16 = 1277, |
| MVE_VMLALDAVau32 = 1278, |
| MVE_VMLALDAVaxs16 = 1279, |
| MVE_VMLALDAVaxs32 = 1280, |
| MVE_VMLALDAVs16 = 1281, |
| MVE_VMLALDAVs32 = 1282, |
| MVE_VMLALDAVu16 = 1283, |
| MVE_VMLALDAVu32 = 1284, |
| MVE_VMLALDAVxs16 = 1285, |
| MVE_VMLALDAVxs32 = 1286, |
| MVE_VMLAS_qr_i16 = 1287, |
| MVE_VMLAS_qr_i32 = 1288, |
| MVE_VMLAS_qr_i8 = 1289, |
| MVE_VMLA_qr_i16 = 1290, |
| MVE_VMLA_qr_i32 = 1291, |
| MVE_VMLA_qr_i8 = 1292, |
| MVE_VMLSDAVas16 = 1293, |
| MVE_VMLSDAVas32 = 1294, |
| MVE_VMLSDAVas8 = 1295, |
| MVE_VMLSDAVaxs16 = 1296, |
| MVE_VMLSDAVaxs32 = 1297, |
| MVE_VMLSDAVaxs8 = 1298, |
| MVE_VMLSDAVs16 = 1299, |
| MVE_VMLSDAVs32 = 1300, |
| MVE_VMLSDAVs8 = 1301, |
| MVE_VMLSDAVxs16 = 1302, |
| MVE_VMLSDAVxs32 = 1303, |
| MVE_VMLSDAVxs8 = 1304, |
| MVE_VMLSLDAVas16 = 1305, |
| MVE_VMLSLDAVas32 = 1306, |
| MVE_VMLSLDAVaxs16 = 1307, |
| MVE_VMLSLDAVaxs32 = 1308, |
| MVE_VMLSLDAVs16 = 1309, |
| MVE_VMLSLDAVs32 = 1310, |
| MVE_VMLSLDAVxs16 = 1311, |
| MVE_VMLSLDAVxs32 = 1312, |
| MVE_VMOVLs16bh = 1313, |
| MVE_VMOVLs16th = 1314, |
| MVE_VMOVLs8bh = 1315, |
| MVE_VMOVLs8th = 1316, |
| MVE_VMOVLu16bh = 1317, |
| MVE_VMOVLu16th = 1318, |
| MVE_VMOVLu8bh = 1319, |
| MVE_VMOVLu8th = 1320, |
| MVE_VMOVNi16bh = 1321, |
| MVE_VMOVNi16th = 1322, |
| MVE_VMOVNi32bh = 1323, |
| MVE_VMOVNi32th = 1324, |
| MVE_VMOV_from_lane_32 = 1325, |
| MVE_VMOV_from_lane_s16 = 1326, |
| MVE_VMOV_from_lane_s8 = 1327, |
| MVE_VMOV_from_lane_u16 = 1328, |
| MVE_VMOV_from_lane_u8 = 1329, |
| MVE_VMOV_q_rr = 1330, |
| MVE_VMOV_rr_q = 1331, |
| MVE_VMOV_to_lane_16 = 1332, |
| MVE_VMOV_to_lane_32 = 1333, |
| MVE_VMOV_to_lane_8 = 1334, |
| MVE_VMOVimmf32 = 1335, |
| MVE_VMOVimmi16 = 1336, |
| MVE_VMOVimmi32 = 1337, |
| MVE_VMOVimmi64 = 1338, |
| MVE_VMOVimmi8 = 1339, |
| MVE_VMULHs16 = 1340, |
| MVE_VMULHs32 = 1341, |
| MVE_VMULHs8 = 1342, |
| MVE_VMULHu16 = 1343, |
| MVE_VMULHu32 = 1344, |
| MVE_VMULHu8 = 1345, |
| MVE_VMULLBp16 = 1346, |
| MVE_VMULLBp8 = 1347, |
| MVE_VMULLBs16 = 1348, |
| MVE_VMULLBs32 = 1349, |
| MVE_VMULLBs8 = 1350, |
| MVE_VMULLBu16 = 1351, |
| MVE_VMULLBu32 = 1352, |
| MVE_VMULLBu8 = 1353, |
| MVE_VMULLTp16 = 1354, |
| MVE_VMULLTp8 = 1355, |
| MVE_VMULLTs16 = 1356, |
| MVE_VMULLTs32 = 1357, |
| MVE_VMULLTs8 = 1358, |
| MVE_VMULLTu16 = 1359, |
| MVE_VMULLTu32 = 1360, |
| MVE_VMULLTu8 = 1361, |
| MVE_VMUL_qr_f16 = 1362, |
| MVE_VMUL_qr_f32 = 1363, |
| MVE_VMUL_qr_i16 = 1364, |
| MVE_VMUL_qr_i32 = 1365, |
| MVE_VMUL_qr_i8 = 1366, |
| MVE_VMULf16 = 1367, |
| MVE_VMULf32 = 1368, |
| MVE_VMULi16 = 1369, |
| MVE_VMULi32 = 1370, |
| MVE_VMULi8 = 1371, |
| MVE_VMVN = 1372, |
| MVE_VMVNimmi16 = 1373, |
| MVE_VMVNimmi32 = 1374, |
| MVE_VNEGf16 = 1375, |
| MVE_VNEGf32 = 1376, |
| MVE_VNEGs16 = 1377, |
| MVE_VNEGs32 = 1378, |
| MVE_VNEGs8 = 1379, |
| MVE_VORN = 1380, |
| MVE_VORR = 1381, |
| MVE_VORRimmi16 = 1382, |
| MVE_VORRimmi32 = 1383, |
| MVE_VPNOT = 1384, |
| MVE_VPSEL = 1385, |
| MVE_VPST = 1386, |
| MVE_VPTv16i8 = 1387, |
| MVE_VPTv16i8r = 1388, |
| MVE_VPTv16s8 = 1389, |
| MVE_VPTv16s8r = 1390, |
| MVE_VPTv16u8 = 1391, |
| MVE_VPTv16u8r = 1392, |
| MVE_VPTv4f32 = 1393, |
| MVE_VPTv4f32r = 1394, |
| MVE_VPTv4i32 = 1395, |
| MVE_VPTv4i32r = 1396, |
| MVE_VPTv4s32 = 1397, |
| MVE_VPTv4s32r = 1398, |
| MVE_VPTv4u32 = 1399, |
| MVE_VPTv4u32r = 1400, |
| MVE_VPTv8f16 = 1401, |
| MVE_VPTv8f16r = 1402, |
| MVE_VPTv8i16 = 1403, |
| MVE_VPTv8i16r = 1404, |
| MVE_VPTv8s16 = 1405, |
| MVE_VPTv8s16r = 1406, |
| MVE_VPTv8u16 = 1407, |
| MVE_VPTv8u16r = 1408, |
| MVE_VQABSs16 = 1409, |
| MVE_VQABSs32 = 1410, |
| MVE_VQABSs8 = 1411, |
| MVE_VQADD_qr_s16 = 1412, |
| MVE_VQADD_qr_s32 = 1413, |
| MVE_VQADD_qr_s8 = 1414, |
| MVE_VQADD_qr_u16 = 1415, |
| MVE_VQADD_qr_u32 = 1416, |
| MVE_VQADD_qr_u8 = 1417, |
| MVE_VQADDs16 = 1418, |
| MVE_VQADDs32 = 1419, |
| MVE_VQADDs8 = 1420, |
| MVE_VQADDu16 = 1421, |
| MVE_VQADDu32 = 1422, |
| MVE_VQADDu8 = 1423, |
| MVE_VQDMLADHXs16 = 1424, |
| MVE_VQDMLADHXs32 = 1425, |
| MVE_VQDMLADHXs8 = 1426, |
| MVE_VQDMLADHs16 = 1427, |
| MVE_VQDMLADHs32 = 1428, |
| MVE_VQDMLADHs8 = 1429, |
| MVE_VQDMLAH_qrs16 = 1430, |
| MVE_VQDMLAH_qrs32 = 1431, |
| MVE_VQDMLAH_qrs8 = 1432, |
| MVE_VQDMLASH_qrs16 = 1433, |
| MVE_VQDMLASH_qrs32 = 1434, |
| MVE_VQDMLASH_qrs8 = 1435, |
| MVE_VQDMLSDHXs16 = 1436, |
| MVE_VQDMLSDHXs32 = 1437, |
| MVE_VQDMLSDHXs8 = 1438, |
| MVE_VQDMLSDHs16 = 1439, |
| MVE_VQDMLSDHs32 = 1440, |
| MVE_VQDMLSDHs8 = 1441, |
| MVE_VQDMULH_qr_s16 = 1442, |
| MVE_VQDMULH_qr_s32 = 1443, |
| MVE_VQDMULH_qr_s8 = 1444, |
| MVE_VQDMULHi16 = 1445, |
| MVE_VQDMULHi32 = 1446, |
| MVE_VQDMULHi8 = 1447, |
| MVE_VQDMULL_qr_s16bh = 1448, |
| MVE_VQDMULL_qr_s16th = 1449, |
| MVE_VQDMULL_qr_s32bh = 1450, |
| MVE_VQDMULL_qr_s32th = 1451, |
| MVE_VQDMULLs16bh = 1452, |
| MVE_VQDMULLs16th = 1453, |
| MVE_VQDMULLs32bh = 1454, |
| MVE_VQDMULLs32th = 1455, |
| MVE_VQMOVNs16bh = 1456, |
| MVE_VQMOVNs16th = 1457, |
| MVE_VQMOVNs32bh = 1458, |
| MVE_VQMOVNs32th = 1459, |
| MVE_VQMOVNu16bh = 1460, |
| MVE_VQMOVNu16th = 1461, |
| MVE_VQMOVNu32bh = 1462, |
| MVE_VQMOVNu32th = 1463, |
| MVE_VQMOVUNs16bh = 1464, |
| MVE_VQMOVUNs16th = 1465, |
| MVE_VQMOVUNs32bh = 1466, |
| MVE_VQMOVUNs32th = 1467, |
| MVE_VQNEGs16 = 1468, |
| MVE_VQNEGs32 = 1469, |
| MVE_VQNEGs8 = 1470, |
| MVE_VQRDMLADHXs16 = 1471, |
| MVE_VQRDMLADHXs32 = 1472, |
| MVE_VQRDMLADHXs8 = 1473, |
| MVE_VQRDMLADHs16 = 1474, |
| MVE_VQRDMLADHs32 = 1475, |
| MVE_VQRDMLADHs8 = 1476, |
| MVE_VQRDMLAH_qrs16 = 1477, |
| MVE_VQRDMLAH_qrs32 = 1478, |
| MVE_VQRDMLAH_qrs8 = 1479, |
| MVE_VQRDMLASH_qrs16 = 1480, |
| MVE_VQRDMLASH_qrs32 = 1481, |
| MVE_VQRDMLASH_qrs8 = 1482, |
| MVE_VQRDMLSDHXs16 = 1483, |
| MVE_VQRDMLSDHXs32 = 1484, |
| MVE_VQRDMLSDHXs8 = 1485, |
| MVE_VQRDMLSDHs16 = 1486, |
| MVE_VQRDMLSDHs32 = 1487, |
| MVE_VQRDMLSDHs8 = 1488, |
| MVE_VQRDMULH_qr_s16 = 1489, |
| MVE_VQRDMULH_qr_s32 = 1490, |
| MVE_VQRDMULH_qr_s8 = 1491, |
| MVE_VQRDMULHi16 = 1492, |
| MVE_VQRDMULHi32 = 1493, |
| MVE_VQRDMULHi8 = 1494, |
| MVE_VQRSHL_by_vecs16 = 1495, |
| MVE_VQRSHL_by_vecs32 = 1496, |
| MVE_VQRSHL_by_vecs8 = 1497, |
| MVE_VQRSHL_by_vecu16 = 1498, |
| MVE_VQRSHL_by_vecu32 = 1499, |
| MVE_VQRSHL_by_vecu8 = 1500, |
| MVE_VQRSHL_qrs16 = 1501, |
| MVE_VQRSHL_qrs32 = 1502, |
| MVE_VQRSHL_qrs8 = 1503, |
| MVE_VQRSHL_qru16 = 1504, |
| MVE_VQRSHL_qru32 = 1505, |
| MVE_VQRSHL_qru8 = 1506, |
| MVE_VQRSHRNbhs16 = 1507, |
| MVE_VQRSHRNbhs32 = 1508, |
| MVE_VQRSHRNbhu16 = 1509, |
| MVE_VQRSHRNbhu32 = 1510, |
| MVE_VQRSHRNths16 = 1511, |
| MVE_VQRSHRNths32 = 1512, |
| MVE_VQRSHRNthu16 = 1513, |
| MVE_VQRSHRNthu32 = 1514, |
| MVE_VQRSHRUNs16bh = 1515, |
| MVE_VQRSHRUNs16th = 1516, |
| MVE_VQRSHRUNs32bh = 1517, |
| MVE_VQRSHRUNs32th = 1518, |
| MVE_VQSHLU_imms16 = 1519, |
| MVE_VQSHLU_imms32 = 1520, |
| MVE_VQSHLU_imms8 = 1521, |
| MVE_VQSHL_by_vecs16 = 1522, |
| MVE_VQSHL_by_vecs32 = 1523, |
| MVE_VQSHL_by_vecs8 = 1524, |
| MVE_VQSHL_by_vecu16 = 1525, |
| MVE_VQSHL_by_vecu32 = 1526, |
| MVE_VQSHL_by_vecu8 = 1527, |
| MVE_VQSHL_qrs16 = 1528, |
| MVE_VQSHL_qrs32 = 1529, |
| MVE_VQSHL_qrs8 = 1530, |
| MVE_VQSHL_qru16 = 1531, |
| MVE_VQSHL_qru32 = 1532, |
| MVE_VQSHL_qru8 = 1533, |
| MVE_VQSHLimms16 = 1534, |
| MVE_VQSHLimms32 = 1535, |
| MVE_VQSHLimms8 = 1536, |
| MVE_VQSHLimmu16 = 1537, |
| MVE_VQSHLimmu32 = 1538, |
| MVE_VQSHLimmu8 = 1539, |
| MVE_VQSHRNbhs16 = 1540, |
| MVE_VQSHRNbhs32 = 1541, |
| MVE_VQSHRNbhu16 = 1542, |
| MVE_VQSHRNbhu32 = 1543, |
| MVE_VQSHRNths16 = 1544, |
| MVE_VQSHRNths32 = 1545, |
| MVE_VQSHRNthu16 = 1546, |
| MVE_VQSHRNthu32 = 1547, |
| MVE_VQSHRUNs16bh = 1548, |
| MVE_VQSHRUNs16th = 1549, |
| MVE_VQSHRUNs32bh = 1550, |
| MVE_VQSHRUNs32th = 1551, |
| MVE_VQSUB_qr_s16 = 1552, |
| MVE_VQSUB_qr_s32 = 1553, |
| MVE_VQSUB_qr_s8 = 1554, |
| MVE_VQSUB_qr_u16 = 1555, |
| MVE_VQSUB_qr_u32 = 1556, |
| MVE_VQSUB_qr_u8 = 1557, |
| MVE_VQSUBs16 = 1558, |
| MVE_VQSUBs32 = 1559, |
| MVE_VQSUBs8 = 1560, |
| MVE_VQSUBu16 = 1561, |
| MVE_VQSUBu32 = 1562, |
| MVE_VQSUBu8 = 1563, |
| MVE_VREV16_8 = 1564, |
| MVE_VREV32_16 = 1565, |
| MVE_VREV32_8 = 1566, |
| MVE_VREV64_16 = 1567, |
| MVE_VREV64_32 = 1568, |
| MVE_VREV64_8 = 1569, |
| MVE_VRHADDs16 = 1570, |
| MVE_VRHADDs32 = 1571, |
| MVE_VRHADDs8 = 1572, |
| MVE_VRHADDu16 = 1573, |
| MVE_VRHADDu32 = 1574, |
| MVE_VRHADDu8 = 1575, |
| MVE_VRINTf16A = 1576, |
| MVE_VRINTf16M = 1577, |
| MVE_VRINTf16N = 1578, |
| MVE_VRINTf16P = 1579, |
| MVE_VRINTf16X = 1580, |
| MVE_VRINTf16Z = 1581, |
| MVE_VRINTf32A = 1582, |
| MVE_VRINTf32M = 1583, |
| MVE_VRINTf32N = 1584, |
| MVE_VRINTf32P = 1585, |
| MVE_VRINTf32X = 1586, |
| MVE_VRINTf32Z = 1587, |
| MVE_VRMLALDAVHas32 = 1588, |
| MVE_VRMLALDAVHau32 = 1589, |
| MVE_VRMLALDAVHaxs32 = 1590, |
| MVE_VRMLALDAVHs32 = 1591, |
| MVE_VRMLALDAVHu32 = 1592, |
| MVE_VRMLALDAVHxs32 = 1593, |
| MVE_VRMLSLDAVHas32 = 1594, |
| MVE_VRMLSLDAVHaxs32 = 1595, |
| MVE_VRMLSLDAVHs32 = 1596, |
| MVE_VRMLSLDAVHxs32 = 1597, |
| MVE_VRMULHs16 = 1598, |
| MVE_VRMULHs32 = 1599, |
| MVE_VRMULHs8 = 1600, |
| MVE_VRMULHu16 = 1601, |
| MVE_VRMULHu32 = 1602, |
| MVE_VRMULHu8 = 1603, |
| MVE_VRSHL_by_vecs16 = 1604, |
| MVE_VRSHL_by_vecs32 = 1605, |
| MVE_VRSHL_by_vecs8 = 1606, |
| MVE_VRSHL_by_vecu16 = 1607, |
| MVE_VRSHL_by_vecu32 = 1608, |
| MVE_VRSHL_by_vecu8 = 1609, |
| MVE_VRSHL_qrs16 = 1610, |
| MVE_VRSHL_qrs32 = 1611, |
| MVE_VRSHL_qrs8 = 1612, |
| MVE_VRSHL_qru16 = 1613, |
| MVE_VRSHL_qru32 = 1614, |
| MVE_VRSHL_qru8 = 1615, |
| MVE_VRSHRNi16bh = 1616, |
| MVE_VRSHRNi16th = 1617, |
| MVE_VRSHRNi32bh = 1618, |
| MVE_VRSHRNi32th = 1619, |
| MVE_VRSHR_imms16 = 1620, |
| MVE_VRSHR_imms32 = 1621, |
| MVE_VRSHR_imms8 = 1622, |
| MVE_VRSHR_immu16 = 1623, |
| MVE_VRSHR_immu32 = 1624, |
| MVE_VRSHR_immu8 = 1625, |
| MVE_VSBC = 1626, |
| MVE_VSBCI = 1627, |
| MVE_VSHLC = 1628, |
| MVE_VSHLL_imms16bh = 1629, |
| MVE_VSHLL_imms16th = 1630, |
| MVE_VSHLL_imms8bh = 1631, |
| MVE_VSHLL_imms8th = 1632, |
| MVE_VSHLL_immu16bh = 1633, |
| MVE_VSHLL_immu16th = 1634, |
| MVE_VSHLL_immu8bh = 1635, |
| MVE_VSHLL_immu8th = 1636, |
| MVE_VSHLL_lws16bh = 1637, |
| MVE_VSHLL_lws16th = 1638, |
| MVE_VSHLL_lws8bh = 1639, |
| MVE_VSHLL_lws8th = 1640, |
| MVE_VSHLL_lwu16bh = 1641, |
| MVE_VSHLL_lwu16th = 1642, |
| MVE_VSHLL_lwu8bh = 1643, |
| MVE_VSHLL_lwu8th = 1644, |
| MVE_VSHL_by_vecs16 = 1645, |
| MVE_VSHL_by_vecs32 = 1646, |
| MVE_VSHL_by_vecs8 = 1647, |
| MVE_VSHL_by_vecu16 = 1648, |
| MVE_VSHL_by_vecu32 = 1649, |
| MVE_VSHL_by_vecu8 = 1650, |
| MVE_VSHL_immi16 = 1651, |
| MVE_VSHL_immi32 = 1652, |
| MVE_VSHL_immi8 = 1653, |
| MVE_VSHL_qrs16 = 1654, |
| MVE_VSHL_qrs32 = 1655, |
| MVE_VSHL_qrs8 = 1656, |
| MVE_VSHL_qru16 = 1657, |
| MVE_VSHL_qru32 = 1658, |
| MVE_VSHL_qru8 = 1659, |
| MVE_VSHRNi16bh = 1660, |
| MVE_VSHRNi16th = 1661, |
| MVE_VSHRNi32bh = 1662, |
| MVE_VSHRNi32th = 1663, |
| MVE_VSHR_imms16 = 1664, |
| MVE_VSHR_imms32 = 1665, |
| MVE_VSHR_imms8 = 1666, |
| MVE_VSHR_immu16 = 1667, |
| MVE_VSHR_immu32 = 1668, |
| MVE_VSHR_immu8 = 1669, |
| MVE_VSLIimm16 = 1670, |
| MVE_VSLIimm32 = 1671, |
| MVE_VSLIimm8 = 1672, |
| MVE_VSRIimm16 = 1673, |
| MVE_VSRIimm32 = 1674, |
| MVE_VSRIimm8 = 1675, |
| MVE_VST20_16 = 1676, |
| MVE_VST20_16_wb = 1677, |
| MVE_VST20_32 = 1678, |
| MVE_VST20_32_wb = 1679, |
| MVE_VST20_8 = 1680, |
| MVE_VST20_8_wb = 1681, |
| MVE_VST21_16 = 1682, |
| MVE_VST21_16_wb = 1683, |
| MVE_VST21_32 = 1684, |
| MVE_VST21_32_wb = 1685, |
| MVE_VST21_8 = 1686, |
| MVE_VST21_8_wb = 1687, |
| MVE_VST40_16 = 1688, |
| MVE_VST40_16_wb = 1689, |
| MVE_VST40_32 = 1690, |
| MVE_VST40_32_wb = 1691, |
| MVE_VST40_8 = 1692, |
| MVE_VST40_8_wb = 1693, |
| MVE_VST41_16 = 1694, |
| MVE_VST41_16_wb = 1695, |
| MVE_VST41_32 = 1696, |
| MVE_VST41_32_wb = 1697, |
| MVE_VST41_8 = 1698, |
| MVE_VST41_8_wb = 1699, |
| MVE_VST42_16 = 1700, |
| MVE_VST42_16_wb = 1701, |
| MVE_VST42_32 = 1702, |
| MVE_VST42_32_wb = 1703, |
| MVE_VST42_8 = 1704, |
| MVE_VST42_8_wb = 1705, |
| MVE_VST43_16 = 1706, |
| MVE_VST43_16_wb = 1707, |
| MVE_VST43_32 = 1708, |
| MVE_VST43_32_wb = 1709, |
| MVE_VST43_8 = 1710, |
| MVE_VST43_8_wb = 1711, |
| MVE_VSTRB16 = 1712, |
| MVE_VSTRB16_post = 1713, |
| MVE_VSTRB16_pre = 1714, |
| MVE_VSTRB16_rq = 1715, |
| MVE_VSTRB32 = 1716, |
| MVE_VSTRB32_post = 1717, |
| MVE_VSTRB32_pre = 1718, |
| MVE_VSTRB32_rq = 1719, |
| MVE_VSTRB8_rq = 1720, |
| MVE_VSTRBU8 = 1721, |
| MVE_VSTRBU8_post = 1722, |
| MVE_VSTRBU8_pre = 1723, |
| MVE_VSTRD64_qi = 1724, |
| MVE_VSTRD64_qi_pre = 1725, |
| MVE_VSTRD64_rq = 1726, |
| MVE_VSTRD64_rq_u = 1727, |
| MVE_VSTRH16_rq = 1728, |
| MVE_VSTRH16_rq_u = 1729, |
| MVE_VSTRH32 = 1730, |
| MVE_VSTRH32_post = 1731, |
| MVE_VSTRH32_pre = 1732, |
| MVE_VSTRH32_rq = 1733, |
| MVE_VSTRH32_rq_u = 1734, |
| MVE_VSTRHU16 = 1735, |
| MVE_VSTRHU16_post = 1736, |
| MVE_VSTRHU16_pre = 1737, |
| MVE_VSTRW32_qi = 1738, |
| MVE_VSTRW32_qi_pre = 1739, |
| MVE_VSTRW32_rq = 1740, |
| MVE_VSTRW32_rq_u = 1741, |
| MVE_VSTRWU32 = 1742, |
| MVE_VSTRWU32_post = 1743, |
| MVE_VSTRWU32_pre = 1744, |
| MVE_VSUB_qr_f16 = 1745, |
| MVE_VSUB_qr_f32 = 1746, |
| MVE_VSUB_qr_i16 = 1747, |
| MVE_VSUB_qr_i32 = 1748, |
| MVE_VSUB_qr_i8 = 1749, |
| MVE_VSUBf16 = 1750, |
| MVE_VSUBf32 = 1751, |
| MVE_VSUBi16 = 1752, |
| MVE_VSUBi32 = 1753, |
| MVE_VSUBi8 = 1754, |
| MVE_WLSTP_16 = 1755, |
| MVE_WLSTP_32 = 1756, |
| MVE_WLSTP_64 = 1757, |
| MVE_WLSTP_8 = 1758, |
| MVNi = 1759, |
| MVNr = 1760, |
| MVNsi = 1761, |
| MVNsr = 1762, |
| NEON_VMAXNMNDf = 1763, |
| NEON_VMAXNMNDh = 1764, |
| NEON_VMAXNMNQf = 1765, |
| NEON_VMAXNMNQh = 1766, |
| NEON_VMINNMNDf = 1767, |
| NEON_VMINNMNDh = 1768, |
| NEON_VMINNMNQf = 1769, |
| NEON_VMINNMNQh = 1770, |
| ORRri = 1771, |
| ORRrr = 1772, |
| ORRrsi = 1773, |
| ORRrsr = 1774, |
| PKHBT = 1775, |
| PKHTB = 1776, |
| PLDWi12 = 1777, |
| PLDWrs = 1778, |
| PLDi12 = 1779, |
| PLDrs = 1780, |
| PLIi12 = 1781, |
| PLIrs = 1782, |
| QADD = 1783, |
| QADD16 = 1784, |
| QADD8 = 1785, |
| QASX = 1786, |
| QDADD = 1787, |
| QDSUB = 1788, |
| QSAX = 1789, |
| QSUB = 1790, |
| QSUB16 = 1791, |
| QSUB8 = 1792, |
| RBIT = 1793, |
| REV = 1794, |
| REV16 = 1795, |
| REVSH = 1796, |
| RFEDA = 1797, |
| RFEDA_UPD = 1798, |
| RFEDB = 1799, |
| RFEDB_UPD = 1800, |
| RFEIA = 1801, |
| RFEIA_UPD = 1802, |
| RFEIB = 1803, |
| RFEIB_UPD = 1804, |
| RSBri = 1805, |
| RSBrr = 1806, |
| RSBrsi = 1807, |
| RSBrsr = 1808, |
| RSCri = 1809, |
| RSCrr = 1810, |
| RSCrsi = 1811, |
| RSCrsr = 1812, |
| SADD16 = 1813, |
| SADD8 = 1814, |
| SASX = 1815, |
| SB = 1816, |
| SBCri = 1817, |
| SBCrr = 1818, |
| SBCrsi = 1819, |
| SBCrsr = 1820, |
| SBFX = 1821, |
| SDIV = 1822, |
| SEL = 1823, |
| SETEND = 1824, |
| SETPAN = 1825, |
| SHA1C = 1826, |
| SHA1H = 1827, |
| SHA1M = 1828, |
| SHA1P = 1829, |
| SHA1SU0 = 1830, |
| SHA1SU1 = 1831, |
| SHA256H = 1832, |
| SHA256H2 = 1833, |
| SHA256SU0 = 1834, |
| SHA256SU1 = 1835, |
| SHADD16 = 1836, |
| SHADD8 = 1837, |
| SHASX = 1838, |
| SHSAX = 1839, |
| SHSUB16 = 1840, |
| SHSUB8 = 1841, |
| SMC = 1842, |
| SMLABB = 1843, |
| SMLABT = 1844, |
| SMLAD = 1845, |
| SMLADX = 1846, |
| SMLAL = 1847, |
| SMLALBB = 1848, |
| SMLALBT = 1849, |
| SMLALD = 1850, |
| SMLALDX = 1851, |
| SMLALTB = 1852, |
| SMLALTT = 1853, |
| SMLATB = 1854, |
| SMLATT = 1855, |
| SMLAWB = 1856, |
| SMLAWT = 1857, |
| SMLSD = 1858, |
| SMLSDX = 1859, |
| SMLSLD = 1860, |
| SMLSLDX = 1861, |
| SMMLA = 1862, |
| SMMLAR = 1863, |
| SMMLS = 1864, |
| SMMLSR = 1865, |
| SMMUL = 1866, |
| SMMULR = 1867, |
| SMUAD = 1868, |
| SMUADX = 1869, |
| SMULBB = 1870, |
| SMULBT = 1871, |
| SMULL = 1872, |
| SMULTB = 1873, |
| SMULTT = 1874, |
| SMULWB = 1875, |
| SMULWT = 1876, |
| SMUSD = 1877, |
| SMUSDX = 1878, |
| SRSDA = 1879, |
| SRSDA_UPD = 1880, |
| SRSDB = 1881, |
| SRSDB_UPD = 1882, |
| SRSIA = 1883, |
| SRSIA_UPD = 1884, |
| SRSIB = 1885, |
| SRSIB_UPD = 1886, |
| SSAT = 1887, |
| SSAT16 = 1888, |
| SSAX = 1889, |
| SSUB16 = 1890, |
| SSUB8 = 1891, |
| STC2L_OFFSET = 1892, |
| STC2L_OPTION = 1893, |
| STC2L_POST = 1894, |
| STC2L_PRE = 1895, |
| STC2_OFFSET = 1896, |
| STC2_OPTION = 1897, |
| STC2_POST = 1898, |
| STC2_PRE = 1899, |
| STCL_OFFSET = 1900, |
| STCL_OPTION = 1901, |
| STCL_POST = 1902, |
| STCL_PRE = 1903, |
| STC_OFFSET = 1904, |
| STC_OPTION = 1905, |
| STC_POST = 1906, |
| STC_PRE = 1907, |
| STL = 1908, |
| STLB = 1909, |
| STLEX = 1910, |
| STLEXB = 1911, |
| STLEXD = 1912, |
| STLEXH = 1913, |
| STLH = 1914, |
| STMDA = 1915, |
| STMDA_UPD = 1916, |
| STMDB = 1917, |
| STMDB_UPD = 1918, |
| STMIA = 1919, |
| STMIA_UPD = 1920, |
| STMIB = 1921, |
| STMIB_UPD = 1922, |
| STRBT_POST_IMM = 1923, |
| STRBT_POST_REG = 1924, |
| STRB_POST_IMM = 1925, |
| STRB_POST_REG = 1926, |
| STRB_PRE_IMM = 1927, |
| STRB_PRE_REG = 1928, |
| STRBi12 = 1929, |
| STRBrs = 1930, |
| STRD = 1931, |
| STRD_POST = 1932, |
| STRD_PRE = 1933, |
| STREX = 1934, |
| STREXB = 1935, |
| STREXD = 1936, |
| STREXH = 1937, |
| STRH = 1938, |
| STRHTi = 1939, |
| STRHTr = 1940, |
| STRH_POST = 1941, |
| STRH_PRE = 1942, |
| STRT_POST_IMM = 1943, |
| STRT_POST_REG = 1944, |
| STR_POST_IMM = 1945, |
| STR_POST_REG = 1946, |
| STR_PRE_IMM = 1947, |
| STR_PRE_REG = 1948, |
| STRi12 = 1949, |
| STRrs = 1950, |
| SUBri = 1951, |
| SUBrr = 1952, |
| SUBrsi = 1953, |
| SUBrsr = 1954, |
| SVC = 1955, |
| SWP = 1956, |
| SWPB = 1957, |
| SXTAB = 1958, |
| SXTAB16 = 1959, |
| SXTAH = 1960, |
| SXTB = 1961, |
| SXTB16 = 1962, |
| SXTH = 1963, |
| TEQri = 1964, |
| TEQrr = 1965, |
| TEQrsi = 1966, |
| TEQrsr = 1967, |
| TRAP = 1968, |
| TRAPNaCl = 1969, |
| TSB = 1970, |
| TSTri = 1971, |
| TSTrr = 1972, |
| TSTrsi = 1973, |
| TSTrsr = 1974, |
| UADD16 = 1975, |
| UADD8 = 1976, |
| UASX = 1977, |
| UBFX = 1978, |
| UDF = 1979, |
| UDIV = 1980, |
| UHADD16 = 1981, |
| UHADD8 = 1982, |
| UHASX = 1983, |
| UHSAX = 1984, |
| UHSUB16 = 1985, |
| UHSUB8 = 1986, |
| UMAAL = 1987, |
| UMLAL = 1988, |
| UMULL = 1989, |
| UQADD16 = 1990, |
| UQADD8 = 1991, |
| UQASX = 1992, |
| UQSAX = 1993, |
| UQSUB16 = 1994, |
| UQSUB8 = 1995, |
| USAD8 = 1996, |
| USADA8 = 1997, |
| USAT = 1998, |
| USAT16 = 1999, |
| USAX = 2000, |
| USUB16 = 2001, |
| USUB8 = 2002, |
| UXTAB = 2003, |
| UXTAB16 = 2004, |
| UXTAH = 2005, |
| UXTB = 2006, |
| UXTB16 = 2007, |
| UXTH = 2008, |
| VABALsv2i64 = 2009, |
| VABALsv4i32 = 2010, |
| VABALsv8i16 = 2011, |
| VABALuv2i64 = 2012, |
| VABALuv4i32 = 2013, |
| VABALuv8i16 = 2014, |
| VABAsv16i8 = 2015, |
| VABAsv2i32 = 2016, |
| VABAsv4i16 = 2017, |
| VABAsv4i32 = 2018, |
| VABAsv8i16 = 2019, |
| VABAsv8i8 = 2020, |
| VABAuv16i8 = 2021, |
| VABAuv2i32 = 2022, |
| VABAuv4i16 = 2023, |
| VABAuv4i32 = 2024, |
| VABAuv8i16 = 2025, |
| VABAuv8i8 = 2026, |
| VABDLsv2i64 = 2027, |
| VABDLsv4i32 = 2028, |
| VABDLsv8i16 = 2029, |
| VABDLuv2i64 = 2030, |
| VABDLuv4i32 = 2031, |
| VABDLuv8i16 = 2032, |
| VABDfd = 2033, |
| VABDfq = 2034, |
| VABDhd = 2035, |
| VABDhq = 2036, |
| VABDsv16i8 = 2037, |
| VABDsv2i32 = 2038, |
| VABDsv4i16 = 2039, |
| VABDsv4i32 = 2040, |
| VABDsv8i16 = 2041, |
| VABDsv8i8 = 2042, |
| VABDuv16i8 = 2043, |
| VABDuv2i32 = 2044, |
| VABDuv4i16 = 2045, |
| VABDuv4i32 = 2046, |
| VABDuv8i16 = 2047, |
| VABDuv8i8 = 2048, |
| VABSD = 2049, |
| VABSH = 2050, |
| VABSS = 2051, |
| VABSfd = 2052, |
| VABSfq = 2053, |
| VABShd = 2054, |
| VABShq = 2055, |
| VABSv16i8 = 2056, |
| VABSv2i32 = 2057, |
| VABSv4i16 = 2058, |
| VABSv4i32 = 2059, |
| VABSv8i16 = 2060, |
| VABSv8i8 = 2061, |
| VACGEfd = 2062, |
| VACGEfq = 2063, |
| VACGEhd = 2064, |
| VACGEhq = 2065, |
| VACGTfd = 2066, |
| VACGTfq = 2067, |
| VACGThd = 2068, |
| VACGThq = 2069, |
| VADDD = 2070, |
| VADDH = 2071, |
| VADDHNv2i32 = 2072, |
| VADDHNv4i16 = 2073, |
| VADDHNv8i8 = 2074, |
| VADDLsv2i64 = 2075, |
| VADDLsv4i32 = 2076, |
| VADDLsv8i16 = 2077, |
| VADDLuv2i64 = 2078, |
| VADDLuv4i32 = 2079, |
| VADDLuv8i16 = 2080, |
| VADDS = 2081, |
| VADDWsv2i64 = 2082, |
| VADDWsv4i32 = 2083, |
| VADDWsv8i16 = 2084, |
| VADDWuv2i64 = 2085, |
| VADDWuv4i32 = 2086, |
| VADDWuv8i16 = 2087, |
| VADDfd = 2088, |
| VADDfq = 2089, |
| VADDhd = 2090, |
| VADDhq = 2091, |
| VADDv16i8 = 2092, |
| VADDv1i64 = 2093, |
| VADDv2i32 = 2094, |
| VADDv2i64 = 2095, |
| VADDv4i16 = 2096, |
| VADDv4i32 = 2097, |
| VADDv8i16 = 2098, |
| VADDv8i8 = 2099, |
| VANDd = 2100, |
| VANDq = 2101, |
| VBF16MALBQ = 2102, |
| VBF16MALBQI = 2103, |
| VBF16MALTQ = 2104, |
| VBF16MALTQI = 2105, |
| VBICd = 2106, |
| VBICiv2i32 = 2107, |
| VBICiv4i16 = 2108, |
| VBICiv4i32 = 2109, |
| VBICiv8i16 = 2110, |
| VBICq = 2111, |
| VBIFd = 2112, |
| VBIFq = 2113, |
| VBITd = 2114, |
| VBITq = 2115, |
| VBSLd = 2116, |
| VBSLq = 2117, |
| VBSPd = 2118, |
| VBSPq = 2119, |
| VCADDv2f32 = 2120, |
| VCADDv4f16 = 2121, |
| VCADDv4f32 = 2122, |
| VCADDv8f16 = 2123, |
| VCEQfd = 2124, |
| VCEQfq = 2125, |
| VCEQhd = 2126, |
| VCEQhq = 2127, |
| VCEQv16i8 = 2128, |
| VCEQv2i32 = 2129, |
| VCEQv4i16 = 2130, |
| VCEQv4i32 = 2131, |
| VCEQv8i16 = 2132, |
| VCEQv8i8 = 2133, |
| VCEQzv16i8 = 2134, |
| VCEQzv2f32 = 2135, |
| VCEQzv2i32 = 2136, |
| VCEQzv4f16 = 2137, |
| VCEQzv4f32 = 2138, |
| VCEQzv4i16 = 2139, |
| VCEQzv4i32 = 2140, |
| VCEQzv8f16 = 2141, |
| VCEQzv8i16 = 2142, |
| VCEQzv8i8 = 2143, |
| VCGEfd = 2144, |
| VCGEfq = 2145, |
| VCGEhd = 2146, |
| VCGEhq = 2147, |
| VCGEsv16i8 = 2148, |
| VCGEsv2i32 = 2149, |
| VCGEsv4i16 = 2150, |
| VCGEsv4i32 = 2151, |
| VCGEsv8i16 = 2152, |
| VCGEsv8i8 = 2153, |
| VCGEuv16i8 = 2154, |
| VCGEuv2i32 = 2155, |
| VCGEuv4i16 = 2156, |
| VCGEuv4i32 = 2157, |
| VCGEuv8i16 = 2158, |
| VCGEuv8i8 = 2159, |
| VCGEzv16i8 = 2160, |
| VCGEzv2f32 = 2161, |
| VCGEzv2i32 = 2162, |
| VCGEzv4f16 = 2163, |
| VCGEzv4f32 = 2164, |
| VCGEzv4i16 = 2165, |
| VCGEzv4i32 = 2166, |
| VCGEzv8f16 = 2167, |
| VCGEzv8i16 = 2168, |
| VCGEzv8i8 = 2169, |
| VCGTfd = 2170, |
| VCGTfq = 2171, |
| VCGThd = 2172, |
| VCGThq = 2173, |
| VCGTsv16i8 = 2174, |
| VCGTsv2i32 = 2175, |
| VCGTsv4i16 = 2176, |
| VCGTsv4i32 = 2177, |
| VCGTsv8i16 = 2178, |
| VCGTsv8i8 = 2179, |
| VCGTuv16i8 = 2180, |
| VCGTuv2i32 = 2181, |
| VCGTuv4i16 = 2182, |
| VCGTuv4i32 = 2183, |
| VCGTuv8i16 = 2184, |
| VCGTuv8i8 = 2185, |
| VCGTzv16i8 = 2186, |
| VCGTzv2f32 = 2187, |
| VCGTzv2i32 = 2188, |
| VCGTzv4f16 = 2189, |
| VCGTzv4f32 = 2190, |
| VCGTzv4i16 = 2191, |
| VCGTzv4i32 = 2192, |
| VCGTzv8f16 = 2193, |
| VCGTzv8i16 = 2194, |
| VCGTzv8i8 = 2195, |
| VCLEzv16i8 = 2196, |
| VCLEzv2f32 = 2197, |
| VCLEzv2i32 = 2198, |
| VCLEzv4f16 = 2199, |
| VCLEzv4f32 = 2200, |
| VCLEzv4i16 = 2201, |
| VCLEzv4i32 = 2202, |
| VCLEzv8f16 = 2203, |
| VCLEzv8i16 = 2204, |
| VCLEzv8i8 = 2205, |
| VCLSv16i8 = 2206, |
| VCLSv2i32 = 2207, |
| VCLSv4i16 = 2208, |
| VCLSv4i32 = 2209, |
| VCLSv8i16 = 2210, |
| VCLSv8i8 = 2211, |
| VCLTzv16i8 = 2212, |
| VCLTzv2f32 = 2213, |
| VCLTzv2i32 = 2214, |
| VCLTzv4f16 = 2215, |
| VCLTzv4f32 = 2216, |
| VCLTzv4i16 = 2217, |
| VCLTzv4i32 = 2218, |
| VCLTzv8f16 = 2219, |
| VCLTzv8i16 = 2220, |
| VCLTzv8i8 = 2221, |
| VCLZv16i8 = 2222, |
| VCLZv2i32 = 2223, |
| VCLZv4i16 = 2224, |
| VCLZv4i32 = 2225, |
| VCLZv8i16 = 2226, |
| VCLZv8i8 = 2227, |
| VCMLAv2f32 = 2228, |
| VCMLAv2f32_indexed = 2229, |
| VCMLAv4f16 = 2230, |
| VCMLAv4f16_indexed = 2231, |
| VCMLAv4f32 = 2232, |
| VCMLAv4f32_indexed = 2233, |
| VCMLAv8f16 = 2234, |
| VCMLAv8f16_indexed = 2235, |
| VCMPD = 2236, |
| VCMPED = 2237, |
| VCMPEH = 2238, |
| VCMPES = 2239, |
| VCMPEZD = 2240, |
| VCMPEZH = 2241, |
| VCMPEZS = 2242, |
| VCMPH = 2243, |
| VCMPS = 2244, |
| VCMPZD = 2245, |
| VCMPZH = 2246, |
| VCMPZS = 2247, |
| VCNTd = 2248, |
| VCNTq = 2249, |
| VCVTANSDf = 2250, |
| VCVTANSDh = 2251, |
| VCVTANSQf = 2252, |
| VCVTANSQh = 2253, |
| VCVTANUDf = 2254, |
| VCVTANUDh = 2255, |
| VCVTANUQf = 2256, |
| VCVTANUQh = 2257, |
| VCVTASD = 2258, |
| VCVTASH = 2259, |
| VCVTASS = 2260, |
| VCVTAUD = 2261, |
| VCVTAUH = 2262, |
| VCVTAUS = 2263, |
| VCVTBDH = 2264, |
| VCVTBHD = 2265, |
| VCVTBHS = 2266, |
| VCVTBSH = 2267, |
| VCVTDS = 2268, |
| VCVTMNSDf = 2269, |
| VCVTMNSDh = 2270, |
| VCVTMNSQf = 2271, |
| VCVTMNSQh = 2272, |
| VCVTMNUDf = 2273, |
| VCVTMNUDh = 2274, |
| VCVTMNUQf = 2275, |
| VCVTMNUQh = 2276, |
| VCVTMSD = 2277, |
| VCVTMSH = 2278, |
| VCVTMSS = 2279, |
| VCVTMUD = 2280, |
| VCVTMUH = 2281, |
| VCVTMUS = 2282, |
| VCVTNNSDf = 2283, |
| VCVTNNSDh = 2284, |
| VCVTNNSQf = 2285, |
| VCVTNNSQh = 2286, |
| VCVTNNUDf = 2287, |
| VCVTNNUDh = 2288, |
| VCVTNNUQf = 2289, |
| VCVTNNUQh = 2290, |
| VCVTNSD = 2291, |
| VCVTNSH = 2292, |
| VCVTNSS = 2293, |
| VCVTNUD = 2294, |
| VCVTNUH = 2295, |
| VCVTNUS = 2296, |
| VCVTPNSDf = 2297, |
| VCVTPNSDh = 2298, |
| VCVTPNSQf = 2299, |
| VCVTPNSQh = 2300, |
| VCVTPNUDf = 2301, |
| VCVTPNUDh = 2302, |
| VCVTPNUQf = 2303, |
| VCVTPNUQh = 2304, |
| VCVTPSD = 2305, |
| VCVTPSH = 2306, |
| VCVTPSS = 2307, |
| VCVTPUD = 2308, |
| VCVTPUH = 2309, |
| VCVTPUS = 2310, |
| VCVTSD = 2311, |
| VCVTTDH = 2312, |
| VCVTTHD = 2313, |
| VCVTTHS = 2314, |
| VCVTTSH = 2315, |
| VCVTf2h = 2316, |
| VCVTf2sd = 2317, |
| VCVTf2sq = 2318, |
| VCVTf2ud = 2319, |
| VCVTf2uq = 2320, |
| VCVTf2xsd = 2321, |
| VCVTf2xsq = 2322, |
| VCVTf2xud = 2323, |
| VCVTf2xuq = 2324, |
| VCVTh2f = 2325, |
| VCVTh2sd = 2326, |
| VCVTh2sq = 2327, |
| VCVTh2ud = 2328, |
| VCVTh2uq = 2329, |
| VCVTh2xsd = 2330, |
| VCVTh2xsq = 2331, |
| VCVTh2xud = 2332, |
| VCVTh2xuq = 2333, |
| VCVTs2fd = 2334, |
| VCVTs2fq = 2335, |
| VCVTs2hd = 2336, |
| VCVTs2hq = 2337, |
| VCVTu2fd = 2338, |
| VCVTu2fq = 2339, |
| VCVTu2hd = 2340, |
| VCVTu2hq = 2341, |
| VCVTxs2fd = 2342, |
| VCVTxs2fq = 2343, |
| VCVTxs2hd = 2344, |
| VCVTxs2hq = 2345, |
| VCVTxu2fd = 2346, |
| VCVTxu2fq = 2347, |
| VCVTxu2hd = 2348, |
| VCVTxu2hq = 2349, |
| VDIVD = 2350, |
| VDIVH = 2351, |
| VDIVS = 2352, |
| VDUP16d = 2353, |
| VDUP16q = 2354, |
| VDUP32d = 2355, |
| VDUP32q = 2356, |
| VDUP8d = 2357, |
| VDUP8q = 2358, |
| VDUPLN16d = 2359, |
| VDUPLN16q = 2360, |
| VDUPLN32d = 2361, |
| VDUPLN32q = 2362, |
| VDUPLN8d = 2363, |
| VDUPLN8q = 2364, |
| VEORd = 2365, |
| VEORq = 2366, |
| VEXTd16 = 2367, |
| VEXTd32 = 2368, |
| VEXTd8 = 2369, |
| VEXTq16 = 2370, |
| VEXTq32 = 2371, |
| VEXTq64 = 2372, |
| VEXTq8 = 2373, |
| VFMAD = 2374, |
| VFMAH = 2375, |
| VFMALD = 2376, |
| VFMALDI = 2377, |
| VFMALQ = 2378, |
| VFMALQI = 2379, |
| VFMAS = 2380, |
| VFMAfd = 2381, |
| VFMAfq = 2382, |
| VFMAhd = 2383, |
| VFMAhq = 2384, |
| VFMSD = 2385, |
| VFMSH = 2386, |
| VFMSLD = 2387, |
| VFMSLDI = 2388, |
| VFMSLQ = 2389, |
| VFMSLQI = 2390, |
| VFMSS = 2391, |
| VFMSfd = 2392, |
| VFMSfq = 2393, |
| VFMShd = 2394, |
| VFMShq = 2395, |
| VFNMAD = 2396, |
| VFNMAH = 2397, |
| VFNMAS = 2398, |
| VFNMSD = 2399, |
| VFNMSH = 2400, |
| VFNMSS = 2401, |
| VFP_VMAXNMD = 2402, |
| VFP_VMAXNMH = 2403, |
| VFP_VMAXNMS = 2404, |
| VFP_VMINNMD = 2405, |
| VFP_VMINNMH = 2406, |
| VFP_VMINNMS = 2407, |
| VGETLNi32 = 2408, |
| VGETLNs16 = 2409, |
| VGETLNs8 = 2410, |
| VGETLNu16 = 2411, |
| VGETLNu8 = 2412, |
| VHADDsv16i8 = 2413, |
| VHADDsv2i32 = 2414, |
| VHADDsv4i16 = 2415, |
| VHADDsv4i32 = 2416, |
| VHADDsv8i16 = 2417, |
| VHADDsv8i8 = 2418, |
| VHADDuv16i8 = 2419, |
| VHADDuv2i32 = 2420, |
| VHADDuv4i16 = 2421, |
| VHADDuv4i32 = 2422, |
| VHADDuv8i16 = 2423, |
| VHADDuv8i8 = 2424, |
| VHSUBsv16i8 = 2425, |
| VHSUBsv2i32 = 2426, |
| VHSUBsv4i16 = 2427, |
| VHSUBsv4i32 = 2428, |
| VHSUBsv8i16 = 2429, |
| VHSUBsv8i8 = 2430, |
| VHSUBuv16i8 = 2431, |
| VHSUBuv2i32 = 2432, |
| VHSUBuv4i16 = 2433, |
| VHSUBuv4i32 = 2434, |
| VHSUBuv8i16 = 2435, |
| VHSUBuv8i8 = 2436, |
| VINSH = 2437, |
| VJCVT = 2438, |
| VLD1DUPd16 = 2439, |
| VLD1DUPd16wb_fixed = 2440, |
| VLD1DUPd16wb_register = 2441, |
| VLD1DUPd32 = 2442, |
| VLD1DUPd32wb_fixed = 2443, |
| VLD1DUPd32wb_register = 2444, |
| VLD1DUPd8 = 2445, |
| VLD1DUPd8wb_fixed = 2446, |
| VLD1DUPd8wb_register = 2447, |
| VLD1DUPq16 = 2448, |
| VLD1DUPq16wb_fixed = 2449, |
| VLD1DUPq16wb_register = 2450, |
| VLD1DUPq32 = 2451, |
| VLD1DUPq32wb_fixed = 2452, |
| VLD1DUPq32wb_register = 2453, |
| VLD1DUPq8 = 2454, |
| VLD1DUPq8wb_fixed = 2455, |
| VLD1DUPq8wb_register = 2456, |
| VLD1LNd16 = 2457, |
| VLD1LNd16_UPD = 2458, |
| VLD1LNd32 = 2459, |
| VLD1LNd32_UPD = 2460, |
| VLD1LNd8 = 2461, |
| VLD1LNd8_UPD = 2462, |
| VLD1LNq16Pseudo = 2463, |
| VLD1LNq16Pseudo_UPD = 2464, |
| VLD1LNq32Pseudo = 2465, |
| VLD1LNq32Pseudo_UPD = 2466, |
| VLD1LNq8Pseudo = 2467, |
| VLD1LNq8Pseudo_UPD = 2468, |
| VLD1d16 = 2469, |
| VLD1d16Q = 2470, |
| VLD1d16QPseudo = 2471, |
| VLD1d16QPseudoWB_fixed = 2472, |
| VLD1d16QPseudoWB_register = 2473, |
| VLD1d16Qwb_fixed = 2474, |
| VLD1d16Qwb_register = 2475, |
| VLD1d16T = 2476, |
| VLD1d16TPseudo = 2477, |
| VLD1d16TPseudoWB_fixed = 2478, |
| VLD1d16TPseudoWB_register = 2479, |
| VLD1d16Twb_fixed = 2480, |
| VLD1d16Twb_register = 2481, |
| VLD1d16wb_fixed = 2482, |
| VLD1d16wb_register = 2483, |
| VLD1d32 = 2484, |
| VLD1d32Q = 2485, |
| VLD1d32QPseudo = 2486, |
| VLD1d32QPseudoWB_fixed = 2487, |
| VLD1d32QPseudoWB_register = 2488, |
| VLD1d32Qwb_fixed = 2489, |
| VLD1d32Qwb_register = 2490, |
| VLD1d32T = 2491, |
| VLD1d32TPseudo = 2492, |
| VLD1d32TPseudoWB_fixed = 2493, |
| VLD1d32TPseudoWB_register = 2494, |
| VLD1d32Twb_fixed = 2495, |
| VLD1d32Twb_register = 2496, |
| VLD1d32wb_fixed = 2497, |
| VLD1d32wb_register = 2498, |
| VLD1d64 = 2499, |
| VLD1d64Q = 2500, |
| VLD1d64QPseudo = 2501, |
| VLD1d64QPseudoWB_fixed = 2502, |
| VLD1d64QPseudoWB_register = 2503, |
| VLD1d64Qwb_fixed = 2504, |
| VLD1d64Qwb_register = 2505, |
| VLD1d64T = 2506, |
| VLD1d64TPseudo = 2507, |
| VLD1d64TPseudoWB_fixed = 2508, |
| VLD1d64TPseudoWB_register = 2509, |
| VLD1d64Twb_fixed = 2510, |
| VLD1d64Twb_register = 2511, |
| VLD1d64wb_fixed = 2512, |
| VLD1d64wb_register = 2513, |
| VLD1d8 = 2514, |
| VLD1d8Q = 2515, |
| VLD1d8QPseudo = 2516, |
| VLD1d8QPseudoWB_fixed = 2517, |
| VLD1d8QPseudoWB_register = 2518, |
| VLD1d8Qwb_fixed = 2519, |
| VLD1d8Qwb_register = 2520, |
| VLD1d8T = 2521, |
| VLD1d8TPseudo = 2522, |
| VLD1d8TPseudoWB_fixed = 2523, |
| VLD1d8TPseudoWB_register = 2524, |
| VLD1d8Twb_fixed = 2525, |
| VLD1d8Twb_register = 2526, |
| VLD1d8wb_fixed = 2527, |
| VLD1d8wb_register = 2528, |
| VLD1q16 = 2529, |
| VLD1q16HighQPseudo = 2530, |
| VLD1q16HighQPseudo_UPD = 2531, |
| VLD1q16HighTPseudo = 2532, |
| VLD1q16HighTPseudo_UPD = 2533, |
| VLD1q16LowQPseudo_UPD = 2534, |
| VLD1q16LowTPseudo_UPD = 2535, |
| VLD1q16wb_fixed = 2536, |
| VLD1q16wb_register = 2537, |
| VLD1q32 = 2538, |
| VLD1q32HighQPseudo = 2539, |
| VLD1q32HighQPseudo_UPD = 2540, |
| VLD1q32HighTPseudo = 2541, |
| VLD1q32HighTPseudo_UPD = 2542, |
| VLD1q32LowQPseudo_UPD = 2543, |
| VLD1q32LowTPseudo_UPD = 2544, |
| VLD1q32wb_fixed = 2545, |
| VLD1q32wb_register = 2546, |
| VLD1q64 = 2547, |
| VLD1q64HighQPseudo = 2548, |
| VLD1q64HighQPseudo_UPD = 2549, |
| VLD1q64HighTPseudo = 2550, |
| VLD1q64HighTPseudo_UPD = 2551, |
| VLD1q64LowQPseudo_UPD = 2552, |
| VLD1q64LowTPseudo_UPD = 2553, |
| VLD1q64wb_fixed = 2554, |
| VLD1q64wb_register = 2555, |
| VLD1q8 = 2556, |
| VLD1q8HighQPseudo = 2557, |
| VLD1q8HighQPseudo_UPD = 2558, |
| VLD1q8HighTPseudo = 2559, |
| VLD1q8HighTPseudo_UPD = 2560, |
| VLD1q8LowQPseudo_UPD = 2561, |
| VLD1q8LowTPseudo_UPD = 2562, |
| VLD1q8wb_fixed = 2563, |
| VLD1q8wb_register = 2564, |
| VLD2DUPd16 = 2565, |
| VLD2DUPd16wb_fixed = 2566, |
| VLD2DUPd16wb_register = 2567, |
| VLD2DUPd16x2 = 2568, |
| VLD2DUPd16x2wb_fixed = 2569, |
| VLD2DUPd16x2wb_register = 2570, |
| VLD2DUPd32 = 2571, |
| VLD2DUPd32wb_fixed = 2572, |
| VLD2DUPd32wb_register = 2573, |
| VLD2DUPd32x2 = 2574, |
| VLD2DUPd32x2wb_fixed = 2575, |
| VLD2DUPd32x2wb_register = 2576, |
| VLD2DUPd8 = 2577, |
| VLD2DUPd8wb_fixed = 2578, |
| VLD2DUPd8wb_register = 2579, |
| VLD2DUPd8x2 = 2580, |
| VLD2DUPd8x2wb_fixed = 2581, |
| VLD2DUPd8x2wb_register = 2582, |
| VLD2DUPq16EvenPseudo = 2583, |
| VLD2DUPq16OddPseudo = 2584, |
| VLD2DUPq16OddPseudoWB_fixed = 2585, |
| VLD2DUPq16OddPseudoWB_register = 2586, |
| VLD2DUPq32EvenPseudo = 2587, |
| VLD2DUPq32OddPseudo = 2588, |
| VLD2DUPq32OddPseudoWB_fixed = 2589, |
| VLD2DUPq32OddPseudoWB_register = 2590, |
| VLD2DUPq8EvenPseudo = 2591, |
| VLD2DUPq8OddPseudo = 2592, |
| VLD2DUPq8OddPseudoWB_fixed = 2593, |
| VLD2DUPq8OddPseudoWB_register = 2594, |
| VLD2LNd16 = 2595, |
| VLD2LNd16Pseudo = 2596, |
| VLD2LNd16Pseudo_UPD = 2597, |
| VLD2LNd16_UPD = 2598, |
| VLD2LNd32 = 2599, |
| VLD2LNd32Pseudo = 2600, |
| VLD2LNd32Pseudo_UPD = 2601, |
| VLD2LNd32_UPD = 2602, |
| VLD2LNd8 = 2603, |
| VLD2LNd8Pseudo = 2604, |
| VLD2LNd8Pseudo_UPD = 2605, |
| VLD2LNd8_UPD = 2606, |
| VLD2LNq16 = 2607, |
| VLD2LNq16Pseudo = 2608, |
| VLD2LNq16Pseudo_UPD = 2609, |
| VLD2LNq16_UPD = 2610, |
| VLD2LNq32 = 2611, |
| VLD2LNq32Pseudo = 2612, |
| VLD2LNq32Pseudo_UPD = 2613, |
| VLD2LNq32_UPD = 2614, |
| VLD2b16 = 2615, |
| VLD2b16wb_fixed = 2616, |
| VLD2b16wb_register = 2617, |
| VLD2b32 = 2618, |
| VLD2b32wb_fixed = 2619, |
| VLD2b32wb_register = 2620, |
| VLD2b8 = 2621, |
| VLD2b8wb_fixed = 2622, |
| VLD2b8wb_register = 2623, |
| VLD2d16 = 2624, |
| VLD2d16wb_fixed = 2625, |
| VLD2d16wb_register = 2626, |
| VLD2d32 = 2627, |
| VLD2d32wb_fixed = 2628, |
| VLD2d32wb_register = 2629, |
| VLD2d8 = 2630, |
| VLD2d8wb_fixed = 2631, |
| VLD2d8wb_register = 2632, |
| VLD2q16 = 2633, |
| VLD2q16Pseudo = 2634, |
| VLD2q16PseudoWB_fixed = 2635, |
| VLD2q16PseudoWB_register = 2636, |
| VLD2q16wb_fixed = 2637, |
| VLD2q16wb_register = 2638, |
| VLD2q32 = 2639, |
| VLD2q32Pseudo = 2640, |
| VLD2q32PseudoWB_fixed = 2641, |
| VLD2q32PseudoWB_register = 2642, |
| VLD2q32wb_fixed = 2643, |
| VLD2q32wb_register = 2644, |
| VLD2q8 = 2645, |
| VLD2q8Pseudo = 2646, |
| VLD2q8PseudoWB_fixed = 2647, |
| VLD2q8PseudoWB_register = 2648, |
| VLD2q8wb_fixed = 2649, |
| VLD2q8wb_register = 2650, |
| VLD3DUPd16 = 2651, |
| VLD3DUPd16Pseudo = 2652, |
| VLD3DUPd16Pseudo_UPD = 2653, |
| VLD3DUPd16_UPD = 2654, |
| VLD3DUPd32 = 2655, |
| VLD3DUPd32Pseudo = 2656, |
| VLD3DUPd32Pseudo_UPD = 2657, |
| VLD3DUPd32_UPD = 2658, |
| VLD3DUPd8 = 2659, |
| VLD3DUPd8Pseudo = 2660, |
| VLD3DUPd8Pseudo_UPD = 2661, |
| VLD3DUPd8_UPD = 2662, |
| VLD3DUPq16 = 2663, |
| VLD3DUPq16EvenPseudo = 2664, |
| VLD3DUPq16OddPseudo = 2665, |
| VLD3DUPq16OddPseudo_UPD = 2666, |
| VLD3DUPq16_UPD = 2667, |
| VLD3DUPq32 = 2668, |
| VLD3DUPq32EvenPseudo = 2669, |
| VLD3DUPq32OddPseudo = 2670, |
| VLD3DUPq32OddPseudo_UPD = 2671, |
| VLD3DUPq32_UPD = 2672, |
| VLD3DUPq8 = 2673, |
| VLD3DUPq8EvenPseudo = 2674, |
| VLD3DUPq8OddPseudo = 2675, |
| VLD3DUPq8OddPseudo_UPD = 2676, |
| VLD3DUPq8_UPD = 2677, |
| VLD3LNd16 = 2678, |
| VLD3LNd16Pseudo = 2679, |
| VLD3LNd16Pseudo_UPD = 2680, |
| VLD3LNd16_UPD = 2681, |
| VLD3LNd32 = 2682, |
| VLD3LNd32Pseudo = 2683, |
| VLD3LNd32Pseudo_UPD = 2684, |
| VLD3LNd32_UPD = 2685, |
| VLD3LNd8 = 2686, |
| VLD3LNd8Pseudo = 2687, |
| VLD3LNd8Pseudo_UPD = 2688, |
| VLD3LNd8_UPD = 2689, |
| VLD3LNq16 = 2690, |
| VLD3LNq16Pseudo = 2691, |
| VLD3LNq16Pseudo_UPD = 2692, |
| VLD3LNq16_UPD = 2693, |
| VLD3LNq32 = 2694, |
| VLD3LNq32Pseudo = 2695, |
| VLD3LNq32Pseudo_UPD = 2696, |
| VLD3LNq32_UPD = 2697, |
| VLD3d16 = 2698, |
| VLD3d16Pseudo = 2699, |
| VLD3d16Pseudo_UPD = 2700, |
| VLD3d16_UPD = 2701, |
| VLD3d32 = 2702, |
| VLD3d32Pseudo = 2703, |
| VLD3d32Pseudo_UPD = 2704, |
| VLD3d32_UPD = 2705, |
| VLD3d8 = 2706, |
| VLD3d8Pseudo = 2707, |
| VLD3d8Pseudo_UPD = 2708, |
| VLD3d8_UPD = 2709, |
| VLD3q16 = 2710, |
| VLD3q16Pseudo_UPD = 2711, |
| VLD3q16_UPD = 2712, |
| VLD3q16oddPseudo = 2713, |
| VLD3q16oddPseudo_UPD = 2714, |
| VLD3q32 = 2715, |
| VLD3q32Pseudo_UPD = 2716, |
| VLD3q32_UPD = 2717, |
| VLD3q32oddPseudo = 2718, |
| VLD3q32oddPseudo_UPD = 2719, |
| VLD3q8 = 2720, |
| VLD3q8Pseudo_UPD = 2721, |
| VLD3q8_UPD = 2722, |
| VLD3q8oddPseudo = 2723, |
| VLD3q8oddPseudo_UPD = 2724, |
| VLD4DUPd16 = 2725, |
| VLD4DUPd16Pseudo = 2726, |
| VLD4DUPd16Pseudo_UPD = 2727, |
| VLD4DUPd16_UPD = 2728, |
| VLD4DUPd32 = 2729, |
| VLD4DUPd32Pseudo = 2730, |
| VLD4DUPd32Pseudo_UPD = 2731, |
| VLD4DUPd32_UPD = 2732, |
| VLD4DUPd8 = 2733, |
| VLD4DUPd8Pseudo = 2734, |
| VLD4DUPd8Pseudo_UPD = 2735, |
| VLD4DUPd8_UPD = 2736, |
| VLD4DUPq16 = 2737, |
| VLD4DUPq16EvenPseudo = 2738, |
| VLD4DUPq16OddPseudo = 2739, |
| VLD4DUPq16OddPseudo_UPD = 2740, |
| VLD4DUPq16_UPD = 2741, |
| VLD4DUPq32 = 2742, |
| VLD4DUPq32EvenPseudo = 2743, |
| VLD4DUPq32OddPseudo = 2744, |
| VLD4DUPq32OddPseudo_UPD = 2745, |
| VLD4DUPq32_UPD = 2746, |
| VLD4DUPq8 = 2747, |
| VLD4DUPq8EvenPseudo = 2748, |
| VLD4DUPq8OddPseudo = 2749, |
| VLD4DUPq8OddPseudo_UPD = 2750, |
| VLD4DUPq8_UPD = 2751, |
| VLD4LNd16 = 2752, |
| VLD4LNd16Pseudo = 2753, |
| VLD4LNd16Pseudo_UPD = 2754, |
| VLD4LNd16_UPD = 2755, |
| VLD4LNd32 = 2756, |
| VLD4LNd32Pseudo = 2757, |
| VLD4LNd32Pseudo_UPD = 2758, |
| VLD4LNd32_UPD = 2759, |
| VLD4LNd8 = 2760, |
| VLD4LNd8Pseudo = 2761, |
| VLD4LNd8Pseudo_UPD = 2762, |
| VLD4LNd8_UPD = 2763, |
| VLD4LNq16 = 2764, |
| VLD4LNq16Pseudo = 2765, |
| VLD4LNq16Pseudo_UPD = 2766, |
| VLD4LNq16_UPD = 2767, |
| VLD4LNq32 = 2768, |
| VLD4LNq32Pseudo = 2769, |
| VLD4LNq32Pseudo_UPD = 2770, |
| VLD4LNq32_UPD = 2771, |
| VLD4d16 = 2772, |
| VLD4d16Pseudo = 2773, |
| VLD4d16Pseudo_UPD = 2774, |
| VLD4d16_UPD = 2775, |
| VLD4d32 = 2776, |
| VLD4d32Pseudo = 2777, |
| VLD4d32Pseudo_UPD = 2778, |
| VLD4d32_UPD = 2779, |
| VLD4d8 = 2780, |
| VLD4d8Pseudo = 2781, |
| VLD4d8Pseudo_UPD = 2782, |
| VLD4d8_UPD = 2783, |
| VLD4q16 = 2784, |
| VLD4q16Pseudo_UPD = 2785, |
| VLD4q16_UPD = 2786, |
| VLD4q16oddPseudo = 2787, |
| VLD4q16oddPseudo_UPD = 2788, |
| VLD4q32 = 2789, |
| VLD4q32Pseudo_UPD = 2790, |
| VLD4q32_UPD = 2791, |
| VLD4q32oddPseudo = 2792, |
| VLD4q32oddPseudo_UPD = 2793, |
| VLD4q8 = 2794, |
| VLD4q8Pseudo_UPD = 2795, |
| VLD4q8_UPD = 2796, |
| VLD4q8oddPseudo = 2797, |
| VLD4q8oddPseudo_UPD = 2798, |
| VLDMDDB_UPD = 2799, |
| VLDMDIA = 2800, |
| VLDMDIA_UPD = 2801, |
| VLDMQIA = 2802, |
| VLDMSDB_UPD = 2803, |
| VLDMSIA = 2804, |
| VLDMSIA_UPD = 2805, |
| VLDRD = 2806, |
| VLDRH = 2807, |
| VLDRS = 2808, |
| VLDR_FPCXTNS_off = 2809, |
| VLDR_FPCXTNS_post = 2810, |
| VLDR_FPCXTNS_pre = 2811, |
| VLDR_FPCXTS_off = 2812, |
| VLDR_FPCXTS_post = 2813, |
| VLDR_FPCXTS_pre = 2814, |
| VLDR_FPSCR_NZCVQC_off = 2815, |
| VLDR_FPSCR_NZCVQC_post = 2816, |
| VLDR_FPSCR_NZCVQC_pre = 2817, |
| VLDR_FPSCR_off = 2818, |
| VLDR_FPSCR_post = 2819, |
| VLDR_FPSCR_pre = 2820, |
| VLDR_P0_off = 2821, |
| VLDR_P0_post = 2822, |
| VLDR_P0_pre = 2823, |
| VLDR_VPR_off = 2824, |
| VLDR_VPR_post = 2825, |
| VLDR_VPR_pre = 2826, |
| VLLDM = 2827, |
| VLSTM = 2828, |
| VMAXfd = 2829, |
| VMAXfq = 2830, |
| VMAXhd = 2831, |
| VMAXhq = 2832, |
| VMAXsv16i8 = 2833, |
| VMAXsv2i32 = 2834, |
| VMAXsv4i16 = 2835, |
| VMAXsv4i32 = 2836, |
| VMAXsv8i16 = 2837, |
| VMAXsv8i8 = 2838, |
| VMAXuv16i8 = 2839, |
| VMAXuv2i32 = 2840, |
| VMAXuv4i16 = 2841, |
| VMAXuv4i32 = 2842, |
| VMAXuv8i16 = 2843, |
| VMAXuv8i8 = 2844, |
| VMINfd = 2845, |
| VMINfq = 2846, |
| VMINhd = 2847, |
| VMINhq = 2848, |
| VMINsv16i8 = 2849, |
| VMINsv2i32 = 2850, |
| VMINsv4i16 = 2851, |
| VMINsv4i32 = 2852, |
| VMINsv8i16 = 2853, |
| VMINsv8i8 = 2854, |
| VMINuv16i8 = 2855, |
| VMINuv2i32 = 2856, |
| VMINuv4i16 = 2857, |
| VMINuv4i32 = 2858, |
| VMINuv8i16 = 2859, |
| VMINuv8i8 = 2860, |
| VMLAD = 2861, |
| VMLAH = 2862, |
| VMLALslsv2i32 = 2863, |
| VMLALslsv4i16 = 2864, |
| VMLALsluv2i32 = 2865, |
| VMLALsluv4i16 = 2866, |
| VMLALsv2i64 = 2867, |
| VMLALsv4i32 = 2868, |
| VMLALsv8i16 = 2869, |
| VMLALuv2i64 = 2870, |
| VMLALuv4i32 = 2871, |
| VMLALuv8i16 = 2872, |
| VMLAS = 2873, |
| VMLAfd = 2874, |
| VMLAfq = 2875, |
| VMLAhd = 2876, |
| VMLAhq = 2877, |
| VMLAslfd = 2878, |
| VMLAslfq = 2879, |
| VMLAslhd = 2880, |
| VMLAslhq = 2881, |
| VMLAslv2i32 = 2882, |
| VMLAslv4i16 = 2883, |
| VMLAslv4i32 = 2884, |
| VMLAslv8i16 = 2885, |
| VMLAv16i8 = 2886, |
| VMLAv2i32 = 2887, |
| VMLAv4i16 = 2888, |
| VMLAv4i32 = 2889, |
| VMLAv8i16 = 2890, |
| VMLAv8i8 = 2891, |
| VMLSD = 2892, |
| VMLSH = 2893, |
| VMLSLslsv2i32 = 2894, |
| VMLSLslsv4i16 = 2895, |
| VMLSLsluv2i32 = 2896, |
| VMLSLsluv4i16 = 2897, |
| VMLSLsv2i64 = 2898, |
| VMLSLsv4i32 = 2899, |
| VMLSLsv8i16 = 2900, |
| VMLSLuv2i64 = 2901, |
| VMLSLuv4i32 = 2902, |
| VMLSLuv8i16 = 2903, |
| VMLSS = 2904, |
| VMLSfd = 2905, |
| VMLSfq = 2906, |
| VMLShd = 2907, |
| VMLShq = 2908, |
| VMLSslfd = 2909, |
| VMLSslfq = 2910, |
| VMLSslhd = 2911, |
| VMLSslhq = 2912, |
| VMLSslv2i32 = 2913, |
| VMLSslv4i16 = 2914, |
| VMLSslv4i32 = 2915, |
| VMLSslv8i16 = 2916, |
| VMLSv16i8 = 2917, |
| VMLSv2i32 = 2918, |
| VMLSv4i16 = 2919, |
| VMLSv4i32 = 2920, |
| VMLSv8i16 = 2921, |
| VMLSv8i8 = 2922, |
| VMMLA = 2923, |
| VMOVD = 2924, |
| VMOVDRR = 2925, |
| VMOVH = 2926, |
| VMOVHR = 2927, |
| VMOVLsv2i64 = 2928, |
| VMOVLsv4i32 = 2929, |
| VMOVLsv8i16 = 2930, |
| VMOVLuv2i64 = 2931, |
| VMOVLuv4i32 = 2932, |
| VMOVLuv8i16 = 2933, |
| VMOVNv2i32 = 2934, |
| VMOVNv4i16 = 2935, |
| VMOVNv8i8 = 2936, |
| VMOVRH = 2937, |
| VMOVRRD = 2938, |
| VMOVRRS = 2939, |
| VMOVRS = 2940, |
| VMOVS = 2941, |
| VMOVSR = 2942, |
| VMOVSRR = 2943, |
| VMOVv16i8 = 2944, |
| VMOVv1i64 = 2945, |
| VMOVv2f32 = 2946, |
| VMOVv2i32 = 2947, |
| VMOVv2i64 = 2948, |
| VMOVv4f32 = 2949, |
| VMOVv4i16 = 2950, |
| VMOVv4i32 = 2951, |
| VMOVv8i16 = 2952, |
| VMOVv8i8 = 2953, |
| VMRS = 2954, |
| VMRS_FPCXTNS = 2955, |
| VMRS_FPCXTS = 2956, |
| VMRS_FPEXC = 2957, |
| VMRS_FPINST = 2958, |
| VMRS_FPINST2 = 2959, |
| VMRS_FPSCR_NZCVQC = 2960, |
| VMRS_FPSID = 2961, |
| VMRS_MVFR0 = 2962, |
| VMRS_MVFR1 = 2963, |
| VMRS_MVFR2 = 2964, |
| VMRS_P0 = 2965, |
| VMRS_VPR = 2966, |
| VMSR = 2967, |
| VMSR_FPCXTNS = 2968, |
| VMSR_FPCXTS = 2969, |
| VMSR_FPEXC = 2970, |
| VMSR_FPINST = 2971, |
| VMSR_FPINST2 = 2972, |
| VMSR_FPSCR_NZCVQC = 2973, |
| VMSR_FPSID = 2974, |
| VMSR_P0 = 2975, |
| VMSR_VPR = 2976, |
| VMULD = 2977, |
| VMULH = 2978, |
| VMULLp64 = 2979, |
| VMULLp8 = 2980, |
| VMULLslsv2i32 = 2981, |
| VMULLslsv4i16 = 2982, |
| VMULLsluv2i32 = 2983, |
| VMULLsluv4i16 = 2984, |
| VMULLsv2i64 = 2985, |
| VMULLsv4i32 = 2986, |
| VMULLsv8i16 = 2987, |
| VMULLuv2i64 = 2988, |
| VMULLuv4i32 = 2989, |
| VMULLuv8i16 = 2990, |
| VMULS = 2991, |
| VMULfd = 2992, |
| VMULfq = 2993, |
| VMULhd = 2994, |
| VMULhq = 2995, |
| VMULpd = 2996, |
| VMULpq = 2997, |
| VMULslfd = 2998, |
| VMULslfq = 2999, |
| VMULslhd = 3000, |
| VMULslhq = 3001, |
| VMULslv2i32 = 3002, |
| VMULslv4i16 = 3003, |
| VMULslv4i32 = 3004, |
| VMULslv8i16 = 3005, |
| VMULv16i8 = 3006, |
| VMULv2i32 = 3007, |
| VMULv4i16 = 3008, |
| VMULv4i32 = 3009, |
| VMULv8i16 = 3010, |
| VMULv8i8 = 3011, |
| VMVNd = 3012, |
| VMVNq = 3013, |
| VMVNv2i32 = 3014, |
| VMVNv4i16 = 3015, |
| VMVNv4i32 = 3016, |
| VMVNv8i16 = 3017, |
| VNEGD = 3018, |
| VNEGH = 3019, |
| VNEGS = 3020, |
| VNEGf32q = 3021, |
| VNEGfd = 3022, |
| VNEGhd = 3023, |
| VNEGhq = 3024, |
| VNEGs16d = 3025, |
| VNEGs16q = 3026, |
| VNEGs32d = 3027, |
| VNEGs32q = 3028, |
| VNEGs8d = 3029, |
| VNEGs8q = 3030, |
| VNMLAD = 3031, |
| VNMLAH = 3032, |
| VNMLAS = 3033, |
| VNMLSD = 3034, |
| VNMLSH = 3035, |
| VNMLSS = 3036, |
| VNMULD = 3037, |
| VNMULH = 3038, |
| VNMULS = 3039, |
| VORNd = 3040, |
| VORNq = 3041, |
| VORRd = 3042, |
| VORRiv2i32 = 3043, |
| VORRiv4i16 = 3044, |
| VORRiv4i32 = 3045, |
| VORRiv8i16 = 3046, |
| VORRq = 3047, |
| VPADALsv16i8 = 3048, |
| VPADALsv2i32 = 3049, |
| VPADALsv4i16 = 3050, |
| VPADALsv4i32 = 3051, |
| VPADALsv8i16 = 3052, |
| VPADALsv8i8 = 3053, |
| VPADALuv16i8 = 3054, |
| VPADALuv2i32 = 3055, |
| VPADALuv4i16 = 3056, |
| VPADALuv4i32 = 3057, |
| VPADALuv8i16 = 3058, |
| VPADALuv8i8 = 3059, |
| VPADDLsv16i8 = 3060, |
| VPADDLsv2i32 = 3061, |
| VPADDLsv4i16 = 3062, |
| VPADDLsv4i32 = 3063, |
| VPADDLsv8i16 = 3064, |
| VPADDLsv8i8 = 3065, |
| VPADDLuv16i8 = 3066, |
| VPADDLuv2i32 = 3067, |
| VPADDLuv4i16 = 3068, |
| VPADDLuv4i32 = 3069, |
| VPADDLuv8i16 = 3070, |
| VPADDLuv8i8 = 3071, |
| VPADDf = 3072, |
| VPADDh = 3073, |
| VPADDi16 = 3074, |
| VPADDi32 = 3075, |
| VPADDi8 = 3076, |
| VPMAXf = 3077, |
| VPMAXh = 3078, |
| VPMAXs16 = 3079, |
| VPMAXs32 = 3080, |
| VPMAXs8 = 3081, |
| VPMAXu16 = 3082, |
| VPMAXu32 = 3083, |
| VPMAXu8 = 3084, |
| VPMINf = 3085, |
| VPMINh = 3086, |
| VPMINs16 = 3087, |
| VPMINs32 = 3088, |
| VPMINs8 = 3089, |
| VPMINu16 = 3090, |
| VPMINu32 = 3091, |
| VPMINu8 = 3092, |
| VQABSv16i8 = 3093, |
| VQABSv2i32 = 3094, |
| VQABSv4i16 = 3095, |
| VQABSv4i32 = 3096, |
| VQABSv8i16 = 3097, |
| VQABSv8i8 = 3098, |
| VQADDsv16i8 = 3099, |
| VQADDsv1i64 = 3100, |
| VQADDsv2i32 = 3101, |
| VQADDsv2i64 = 3102, |
| VQADDsv4i16 = 3103, |
| VQADDsv4i32 = 3104, |
| VQADDsv8i16 = 3105, |
| VQADDsv8i8 = 3106, |
| VQADDuv16i8 = 3107, |
| VQADDuv1i64 = 3108, |
| VQADDuv2i32 = 3109, |
| VQADDuv2i64 = 3110, |
| VQADDuv4i16 = 3111, |
| VQADDuv4i32 = 3112, |
| VQADDuv8i16 = 3113, |
| VQADDuv8i8 = 3114, |
| VQDMLALslv2i32 = 3115, |
| VQDMLALslv4i16 = 3116, |
| VQDMLALv2i64 = 3117, |
| VQDMLALv4i32 = 3118, |
| VQDMLSLslv2i32 = 3119, |
| VQDMLSLslv4i16 = 3120, |
| VQDMLSLv2i64 = 3121, |
| VQDMLSLv4i32 = 3122, |
| VQDMULHslv2i32 = 3123, |
| VQDMULHslv4i16 = 3124, |
| VQDMULHslv4i32 = 3125, |
| VQDMULHslv8i16 = 3126, |
| VQDMULHv2i32 = 3127, |
| VQDMULHv4i16 = 3128, |
| VQDMULHv4i32 = 3129, |
| VQDMULHv8i16 = 3130, |
| VQDMULLslv2i32 = 3131, |
| VQDMULLslv4i16 = 3132, |
| VQDMULLv2i64 = 3133, |
| VQDMULLv4i32 = 3134, |
| VQMOVNsuv2i32 = 3135, |
| VQMOVNsuv4i16 = 3136, |
| VQMOVNsuv8i8 = 3137, |
| VQMOVNsv2i32 = 3138, |
| VQMOVNsv4i16 = 3139, |
| VQMOVNsv8i8 = 3140, |
| VQMOVNuv2i32 = 3141, |
| VQMOVNuv4i16 = 3142, |
| VQMOVNuv8i8 = 3143, |
| VQNEGv16i8 = 3144, |
| VQNEGv2i32 = 3145, |
| VQNEGv4i16 = 3146, |
| VQNEGv4i32 = 3147, |
| VQNEGv8i16 = 3148, |
| VQNEGv8i8 = 3149, |
| VQRDMLAHslv2i32 = 3150, |
| VQRDMLAHslv4i16 = 3151, |
| VQRDMLAHslv4i32 = 3152, |
| VQRDMLAHslv8i16 = 3153, |
| VQRDMLAHv2i32 = 3154, |
| VQRDMLAHv4i16 = 3155, |
| VQRDMLAHv4i32 = 3156, |
| VQRDMLAHv8i16 = 3157, |
| VQRDMLSHslv2i32 = 3158, |
| VQRDMLSHslv4i16 = 3159, |
| VQRDMLSHslv4i32 = 3160, |
| VQRDMLSHslv8i16 = 3161, |
| VQRDMLSHv2i32 = 3162, |
| VQRDMLSHv4i16 = 3163, |
| VQRDMLSHv4i32 = 3164, |
| VQRDMLSHv8i16 = 3165, |
| VQRDMULHslv2i32 = 3166, |
| VQRDMULHslv4i16 = 3167, |
| VQRDMULHslv4i32 = 3168, |
| VQRDMULHslv8i16 = 3169, |
| VQRDMULHv2i32 = 3170, |
| VQRDMULHv4i16 = 3171, |
| VQRDMULHv4i32 = 3172, |
| VQRDMULHv8i16 = 3173, |
| VQRSHLsv16i8 = 3174, |
| VQRSHLsv1i64 = 3175, |
| VQRSHLsv2i32 = 3176, |
| VQRSHLsv2i64 = 3177, |
| VQRSHLsv4i16 = 3178, |
| VQRSHLsv4i32 = 3179, |
| VQRSHLsv8i16 = 3180, |
| VQRSHLsv8i8 = 3181, |
| VQRSHLuv16i8 = 3182, |
| VQRSHLuv1i64 = 3183, |
| VQRSHLuv2i32 = 3184, |
| VQRSHLuv2i64 = 3185, |
| VQRSHLuv4i16 = 3186, |
| VQRSHLuv4i32 = 3187, |
| VQRSHLuv8i16 = 3188, |
| VQRSHLuv8i8 = 3189, |
| VQRSHRNsv2i32 = 3190, |
| VQRSHRNsv4i16 = 3191, |
| VQRSHRNsv8i8 = 3192, |
| VQRSHRNuv2i32 = 3193, |
| VQRSHRNuv4i16 = 3194, |
| VQRSHRNuv8i8 = 3195, |
| VQRSHRUNv2i32 = 3196, |
| VQRSHRUNv4i16 = 3197, |
| VQRSHRUNv8i8 = 3198, |
| VQSHLsiv16i8 = 3199, |
| VQSHLsiv1i64 = 3200, |
| VQSHLsiv2i32 = 3201, |
| VQSHLsiv2i64 = 3202, |
| VQSHLsiv4i16 = 3203, |
| VQSHLsiv4i32 = 3204, |
| VQSHLsiv8i16 = 3205, |
| VQSHLsiv8i8 = 3206, |
| VQSHLsuv16i8 = 3207, |
| VQSHLsuv1i64 = 3208, |
| VQSHLsuv2i32 = 3209, |
| VQSHLsuv2i64 = 3210, |
| VQSHLsuv4i16 = 3211, |
| VQSHLsuv4i32 = 3212, |
| VQSHLsuv8i16 = 3213, |
| VQSHLsuv8i8 = 3214, |
| VQSHLsv16i8 = 3215, |
| VQSHLsv1i64 = 3216, |
| VQSHLsv2i32 = 3217, |
| VQSHLsv2i64 = 3218, |
| VQSHLsv4i16 = 3219, |
| VQSHLsv4i32 = 3220, |
| VQSHLsv8i16 = 3221, |
| VQSHLsv8i8 = 3222, |
| VQSHLuiv16i8 = 3223, |
| VQSHLuiv1i64 = 3224, |
| VQSHLuiv2i32 = 3225, |
| VQSHLuiv2i64 = 3226, |
| VQSHLuiv4i16 = 3227, |
| VQSHLuiv4i32 = 3228, |
| VQSHLuiv8i16 = 3229, |
| VQSHLuiv8i8 = 3230, |
| VQSHLuv16i8 = 3231, |
| VQSHLuv1i64 = 3232, |
| VQSHLuv2i32 = 3233, |
| VQSHLuv2i64 = 3234, |
| VQSHLuv4i16 = 3235, |
| VQSHLuv4i32 = 3236, |
| VQSHLuv8i16 = 3237, |
| VQSHLuv8i8 = 3238, |
| VQSHRNsv2i32 = 3239, |
| VQSHRNsv4i16 = 3240, |
| VQSHRNsv8i8 = 3241, |
| VQSHRNuv2i32 = 3242, |
| VQSHRNuv4i16 = 3243, |
| VQSHRNuv8i8 = 3244, |
| VQSHRUNv2i32 = 3245, |
| VQSHRUNv4i16 = 3246, |
| VQSHRUNv8i8 = 3247, |
| VQSUBsv16i8 = 3248, |
| VQSUBsv1i64 = 3249, |
| VQSUBsv2i32 = 3250, |
| VQSUBsv2i64 = 3251, |
| VQSUBsv4i16 = 3252, |
| VQSUBsv4i32 = 3253, |
| VQSUBsv8i16 = 3254, |
| VQSUBsv8i8 = 3255, |
| VQSUBuv16i8 = 3256, |
| VQSUBuv1i64 = 3257, |
| VQSUBuv2i32 = 3258, |
| VQSUBuv2i64 = 3259, |
| VQSUBuv4i16 = 3260, |
| VQSUBuv4i32 = 3261, |
| VQSUBuv8i16 = 3262, |
| VQSUBuv8i8 = 3263, |
| VRADDHNv2i32 = 3264, |
| VRADDHNv4i16 = 3265, |
| VRADDHNv8i8 = 3266, |
| VRECPEd = 3267, |
| VRECPEfd = 3268, |
| VRECPEfq = 3269, |
| VRECPEhd = 3270, |
| VRECPEhq = 3271, |
| VRECPEq = 3272, |
| VRECPSfd = 3273, |
| VRECPSfq = 3274, |
| VRECPShd = 3275, |
| VRECPShq = 3276, |
| VREV16d8 = 3277, |
| VREV16q8 = 3278, |
| VREV32d16 = 3279, |
| VREV32d8 = 3280, |
| VREV32q16 = 3281, |
| VREV32q8 = 3282, |
| VREV64d16 = 3283, |
| VREV64d32 = 3284, |
| VREV64d8 = 3285, |
| VREV64q16 = 3286, |
| VREV64q32 = 3287, |
| VREV64q8 = 3288, |
| VRHADDsv16i8 = 3289, |
| VRHADDsv2i32 = 3290, |
| VRHADDsv4i16 = 3291, |
| VRHADDsv4i32 = 3292, |
| VRHADDsv8i16 = 3293, |
| VRHADDsv8i8 = 3294, |
| VRHADDuv16i8 = 3295, |
| VRHADDuv2i32 = 3296, |
| VRHADDuv4i16 = 3297, |
| VRHADDuv4i32 = 3298, |
| VRHADDuv8i16 = 3299, |
| VRHADDuv8i8 = 3300, |
| VRINTAD = 3301, |
| VRINTAH = 3302, |
| VRINTANDf = 3303, |
| VRINTANDh = 3304, |
| VRINTANQf = 3305, |
| VRINTANQh = 3306, |
| VRINTAS = 3307, |
| VRINTMD = 3308, |
| VRINTMH = 3309, |
| VRINTMNDf = 3310, |
| VRINTMNDh = 3311, |
| VRINTMNQf = 3312, |
| VRINTMNQh = 3313, |
| VRINTMS = 3314, |
| VRINTND = 3315, |
| VRINTNH = 3316, |
| VRINTNNDf = 3317, |
| VRINTNNDh = 3318, |
| VRINTNNQf = 3319, |
| VRINTNNQh = 3320, |
| VRINTNS = 3321, |
| VRINTPD = 3322, |
| VRINTPH = 3323, |
| VRINTPNDf = 3324, |
| VRINTPNDh = 3325, |
| VRINTPNQf = 3326, |
| VRINTPNQh = 3327, |
| VRINTPS = 3328, |
| VRINTRD = 3329, |
| VRINTRH = 3330, |
| VRINTRS = 3331, |
| VRINTXD = 3332, |
| VRINTXH = 3333, |
| VRINTXNDf = 3334, |
| VRINTXNDh = 3335, |
| VRINTXNQf = 3336, |
| VRINTXNQh = 3337, |
| VRINTXS = 3338, |
| VRINTZD = 3339, |
| VRINTZH = 3340, |
| VRINTZNDf = 3341, |
| VRINTZNDh = 3342, |
| VRINTZNQf = 3343, |
| VRINTZNQh = 3344, |
| VRINTZS = 3345, |
| VRSHLsv16i8 = 3346, |
| VRSHLsv1i64 = 3347, |
| VRSHLsv2i32 = 3348, |
| VRSHLsv2i64 = 3349, |
| VRSHLsv4i16 = 3350, |
| VRSHLsv4i32 = 3351, |
| VRSHLsv8i16 = 3352, |
| VRSHLsv8i8 = 3353, |
| VRSHLuv16i8 = 3354, |
| VRSHLuv1i64 = 3355, |
| VRSHLuv2i32 = 3356, |
| VRSHLuv2i64 = 3357, |
| VRSHLuv4i16 = 3358, |
| VRSHLuv4i32 = 3359, |
| VRSHLuv8i16 = 3360, |
| VRSHLuv8i8 = 3361, |
| VRSHRNv2i32 = 3362, |
| VRSHRNv4i16 = 3363, |
| VRSHRNv8i8 = 3364, |
| VRSHRsv16i8 = 3365, |
| VRSHRsv1i64 = 3366, |
| VRSHRsv2i32 = 3367, |
| VRSHRsv2i64 = 3368, |
| VRSHRsv4i16 = 3369, |
| VRSHRsv4i32 = 3370, |
| VRSHRsv8i16 = 3371, |
| VRSHRsv8i8 = 3372, |
| VRSHRuv16i8 = 3373, |
| VRSHRuv1i64 = 3374, |
| VRSHRuv2i32 = 3375, |
| VRSHRuv2i64 = 3376, |
| VRSHRuv4i16 = 3377, |
| VRSHRuv4i32 = 3378, |
| VRSHRuv8i16 = 3379, |
| VRSHRuv8i8 = 3380, |
| VRSQRTEd = 3381, |
| VRSQRTEfd = 3382, |
| VRSQRTEfq = 3383, |
| VRSQRTEhd = 3384, |
| VRSQRTEhq = 3385, |
| VRSQRTEq = 3386, |
| VRSQRTSfd = 3387, |
| VRSQRTSfq = 3388, |
| VRSQRTShd = 3389, |
| VRSQRTShq = 3390, |
| VRSRAsv16i8 = 3391, |
| VRSRAsv1i64 = 3392, |
| VRSRAsv2i32 = 3393, |
| VRSRAsv2i64 = 3394, |
| VRSRAsv4i16 = 3395, |
| VRSRAsv4i32 = 3396, |
| VRSRAsv8i16 = 3397, |
| VRSRAsv8i8 = 3398, |
| VRSRAuv16i8 = 3399, |
| VRSRAuv1i64 = 3400, |
| VRSRAuv2i32 = 3401, |
| VRSRAuv2i64 = 3402, |
| VRSRAuv4i16 = 3403, |
| VRSRAuv4i32 = 3404, |
| VRSRAuv8i16 = 3405, |
| VRSRAuv8i8 = 3406, |
| VRSUBHNv2i32 = 3407, |
| VRSUBHNv4i16 = 3408, |
| VRSUBHNv8i8 = 3409, |
| VSCCLRMD = 3410, |
| VSCCLRMS = 3411, |
| VSDOTD = 3412, |
| VSDOTDI = 3413, |
| VSDOTQ = 3414, |
| VSDOTQI = 3415, |
| VSELEQD = 3416, |
| VSELEQH = 3417, |
| VSELEQS = 3418, |
| VSELGED = 3419, |
| VSELGEH = 3420, |
| VSELGES = 3421, |
| VSELGTD = 3422, |
| VSELGTH = 3423, |
| VSELGTS = 3424, |
| VSELVSD = 3425, |
| VSELVSH = 3426, |
| VSELVSS = 3427, |
| VSETLNi16 = 3428, |
| VSETLNi32 = 3429, |
| VSETLNi8 = 3430, |
| VSHLLi16 = 3431, |
| VSHLLi32 = 3432, |
| VSHLLi8 = 3433, |
| VSHLLsv2i64 = 3434, |
| VSHLLsv4i32 = 3435, |
| VSHLLsv8i16 = 3436, |
| VSHLLuv2i64 = 3437, |
| VSHLLuv4i32 = 3438, |
| VSHLLuv8i16 = 3439, |
| VSHLiv16i8 = 3440, |
| VSHLiv1i64 = 3441, |
| VSHLiv2i32 = 3442, |
| VSHLiv2i64 = 3443, |
| VSHLiv4i16 = 3444, |
| VSHLiv4i32 = 3445, |
| VSHLiv8i16 = 3446, |
| VSHLiv8i8 = 3447, |
| VSHLsv16i8 = 3448, |
| VSHLsv1i64 = 3449, |
| VSHLsv2i32 = 3450, |
| VSHLsv2i64 = 3451, |
| VSHLsv4i16 = 3452, |
| VSHLsv4i32 = 3453, |
| VSHLsv8i16 = 3454, |
| VSHLsv8i8 = 3455, |
| VSHLuv16i8 = 3456, |
| VSHLuv1i64 = 3457, |
| VSHLuv2i32 = 3458, |
| VSHLuv2i64 = 3459, |
| VSHLuv4i16 = 3460, |
| VSHLuv4i32 = 3461, |
| VSHLuv8i16 = 3462, |
| VSHLuv8i8 = 3463, |
| VSHRNv2i32 = 3464, |
| VSHRNv4i16 = 3465, |
| VSHRNv8i8 = 3466, |
| VSHRsv16i8 = 3467, |
| VSHRsv1i64 = 3468, |
| VSHRsv2i32 = 3469, |
| VSHRsv2i64 = 3470, |
| VSHRsv4i16 = 3471, |
| VSHRsv4i32 = 3472, |
| VSHRsv8i16 = 3473, |
| VSHRsv8i8 = 3474, |
| VSHRuv16i8 = 3475, |
| VSHRuv1i64 = 3476, |
| VSHRuv2i32 = 3477, |
| VSHRuv2i64 = 3478, |
| VSHRuv4i16 = 3479, |
| VSHRuv4i32 = 3480, |
| VSHRuv8i16 = 3481, |
| VSHRuv8i8 = 3482, |
| VSHTOD = 3483, |
| VSHTOH = 3484, |
| VSHTOS = 3485, |
| VSITOD = 3486, |
| VSITOH = 3487, |
| VSITOS = 3488, |
| VSLIv16i8 = 3489, |
| VSLIv1i64 = 3490, |
| VSLIv2i32 = 3491, |
| VSLIv2i64 = 3492, |
| VSLIv4i16 = 3493, |
| VSLIv4i32 = 3494, |
| VSLIv8i16 = 3495, |
| VSLIv8i8 = 3496, |
| VSLTOD = 3497, |
| VSLTOH = 3498, |
| VSLTOS = 3499, |
| VSMMLA = 3500, |
| VSQRTD = 3501, |
| VSQRTH = 3502, |
| VSQRTS = 3503, |
| VSRAsv16i8 = 3504, |
| VSRAsv1i64 = 3505, |
| VSRAsv2i32 = 3506, |
| VSRAsv2i64 = 3507, |
| VSRAsv4i16 = 3508, |
| VSRAsv4i32 = 3509, |
| VSRAsv8i16 = 3510, |
| VSRAsv8i8 = 3511, |
| VSRAuv16i8 = 3512, |
| VSRAuv1i64 = 3513, |
| VSRAuv2i32 = 3514, |
| VSRAuv2i64 = 3515, |
| VSRAuv4i16 = 3516, |
| VSRAuv4i32 = 3517, |
| VSRAuv8i16 = 3518, |
| VSRAuv8i8 = 3519, |
| VSRIv16i8 = 3520, |
| VSRIv1i64 = 3521, |
| VSRIv2i32 = 3522, |
| VSRIv2i64 = 3523, |
| VSRIv4i16 = 3524, |
| VSRIv4i32 = 3525, |
| VSRIv8i16 = 3526, |
| VSRIv8i8 = 3527, |
| VST1LNd16 = 3528, |
| VST1LNd16_UPD = 3529, |
| VST1LNd32 = 3530, |
| VST1LNd32_UPD = 3531, |
| VST1LNd8 = 3532, |
| VST1LNd8_UPD = 3533, |
| VST1LNq16Pseudo = 3534, |
| VST1LNq16Pseudo_UPD = 3535, |
| VST1LNq32Pseudo = 3536, |
| VST1LNq32Pseudo_UPD = 3537, |
| VST1LNq8Pseudo = 3538, |
| VST1LNq8Pseudo_UPD = 3539, |
| VST1d16 = 3540, |
| VST1d16Q = 3541, |
| VST1d16QPseudo = 3542, |
| VST1d16QPseudoWB_fixed = 3543, |
| VST1d16QPseudoWB_register = 3544, |
| VST1d16Qwb_fixed = 3545, |
| VST1d16Qwb_register = 3546, |
| VST1d16T = 3547, |
| VST1d16TPseudo = 3548, |
| VST1d16TPseudoWB_fixed = 3549, |
| VST1d16TPseudoWB_register = 3550, |
| VST1d16Twb_fixed = 3551, |
| VST1d16Twb_register = 3552, |
| VST1d16wb_fixed = 3553, |
| VST1d16wb_register = 3554, |
| VST1d32 = 3555, |
| VST1d32Q = 3556, |
| VST1d32QPseudo = 3557, |
| VST1d32QPseudoWB_fixed = 3558, |
| VST1d32QPseudoWB_register = 3559, |
| VST1d32Qwb_fixed = 3560, |
| VST1d32Qwb_register = 3561, |
| VST1d32T = 3562, |
| VST1d32TPseudo = 3563, |
| VST1d32TPseudoWB_fixed = 3564, |
| VST1d32TPseudoWB_register = 3565, |
| VST1d32Twb_fixed = 3566, |
| VST1d32Twb_register = 3567, |
| VST1d32wb_fixed = 3568, |
| VST1d32wb_register = 3569, |
| VST1d64 = 3570, |
| VST1d64Q = 3571, |
| VST1d64QPseudo = 3572, |
| VST1d64QPseudoWB_fixed = 3573, |
| VST1d64QPseudoWB_register = 3574, |
| VST1d64Qwb_fixed = 3575, |
| VST1d64Qwb_register = 3576, |
| VST1d64T = 3577, |
| VST1d64TPseudo = 3578, |
| VST1d64TPseudoWB_fixed = 3579, |
| VST1d64TPseudoWB_register = 3580, |
| VST1d64Twb_fixed = 3581, |
| VST1d64Twb_register = 3582, |
| VST1d64wb_fixed = 3583, |
| VST1d64wb_register = 3584, |
| VST1d8 = 3585, |
| VST1d8Q = 3586, |
| VST1d8QPseudo = 3587, |
| VST1d8QPseudoWB_fixed = 3588, |
| VST1d8QPseudoWB_register = 3589, |
| VST1d8Qwb_fixed = 3590, |
| VST1d8Qwb_register = 3591, |
| VST1d8T = 3592, |
| VST1d8TPseudo = 3593, |
| VST1d8TPseudoWB_fixed = 3594, |
| VST1d8TPseudoWB_register = 3595, |
| VST1d8Twb_fixed = 3596, |
| VST1d8Twb_register = 3597, |
| VST1d8wb_fixed = 3598, |
| VST1d8wb_register = 3599, |
| VST1q16 = 3600, |
| VST1q16HighQPseudo = 3601, |
| VST1q16HighQPseudo_UPD = 3602, |
| VST1q16HighTPseudo = 3603, |
| VST1q16HighTPseudo_UPD = 3604, |
| VST1q16LowQPseudo_UPD = 3605, |
| VST1q16LowTPseudo_UPD = 3606, |
| VST1q16wb_fixed = 3607, |
| VST1q16wb_register = 3608, |
| VST1q32 = 3609, |
| VST1q32HighQPseudo = 3610, |
| VST1q32HighQPseudo_UPD = 3611, |
| VST1q32HighTPseudo = 3612, |
| VST1q32HighTPseudo_UPD = 3613, |
| VST1q32LowQPseudo_UPD = 3614, |
| VST1q32LowTPseudo_UPD = 3615, |
| VST1q32wb_fixed = 3616, |
| VST1q32wb_register = 3617, |
| VST1q64 = 3618, |
| VST1q64HighQPseudo = 3619, |
| VST1q64HighQPseudo_UPD = 3620, |
| VST1q64HighTPseudo = 3621, |
| VST1q64HighTPseudo_UPD = 3622, |
| VST1q64LowQPseudo_UPD = 3623, |
| VST1q64LowTPseudo_UPD = 3624, |
| VST1q64wb_fixed = 3625, |
| VST1q64wb_register = 3626, |
| VST1q8 = 3627, |
| VST1q8HighQPseudo = 3628, |
| VST1q8HighQPseudo_UPD = 3629, |
| VST1q8HighTPseudo = 3630, |
| VST1q8HighTPseudo_UPD = 3631, |
| VST1q8LowQPseudo_UPD = 3632, |
| VST1q8LowTPseudo_UPD = 3633, |
| VST1q8wb_fixed = 3634, |
| VST1q8wb_register = 3635, |
| VST2LNd16 = 3636, |
| VST2LNd16Pseudo = 3637, |
| VST2LNd16Pseudo_UPD = 3638, |
| VST2LNd16_UPD = 3639, |
| VST2LNd32 = 3640, |
| VST2LNd32Pseudo = 3641, |
| VST2LNd32Pseudo_UPD = 3642, |
| VST2LNd32_UPD = 3643, |
| VST2LNd8 = 3644, |
| VST2LNd8Pseudo = 3645, |
| VST2LNd8Pseudo_UPD = 3646, |
| VST2LNd8_UPD = 3647, |
| VST2LNq16 = 3648, |
| VST2LNq16Pseudo = 3649, |
| VST2LNq16Pseudo_UPD = 3650, |
| VST2LNq16_UPD = 3651, |
| VST2LNq32 = 3652, |
| VST2LNq32Pseudo = 3653, |
| VST2LNq32Pseudo_UPD = 3654, |
| VST2LNq32_UPD = 3655, |
| VST2b16 = 3656, |
| VST2b16wb_fixed = 3657, |
| VST2b16wb_register = 3658, |
| VST2b32 = 3659, |
| VST2b32wb_fixed = 3660, |
| VST2b32wb_register = 3661, |
| VST2b8 = 3662, |
| VST2b8wb_fixed = 3663, |
| VST2b8wb_register = 3664, |
| VST2d16 = 3665, |
| VST2d16wb_fixed = 3666, |
| VST2d16wb_register = 3667, |
| VST2d32 = 3668, |
| VST2d32wb_fixed = 3669, |
| VST2d32wb_register = 3670, |
| VST2d8 = 3671, |
| VST2d8wb_fixed = 3672, |
| VST2d8wb_register = 3673, |
| VST2q16 = 3674, |
| VST2q16Pseudo = 3675, |
| VST2q16PseudoWB_fixed = 3676, |
| VST2q16PseudoWB_register = 3677, |
| VST2q16wb_fixed = 3678, |
| VST2q16wb_register = 3679, |
| VST2q32 = 3680, |
| VST2q32Pseudo = 3681, |
| VST2q32PseudoWB_fixed = 3682, |
| VST2q32PseudoWB_register = 3683, |
| VST2q32wb_fixed = 3684, |
| VST2q32wb_register = 3685, |
| VST2q8 = 3686, |
| VST2q8Pseudo = 3687, |
| VST2q8PseudoWB_fixed = 3688, |
| VST2q8PseudoWB_register = 3689, |
| VST2q8wb_fixed = 3690, |
| VST2q8wb_register = 3691, |
| VST3LNd16 = 3692, |
| VST3LNd16Pseudo = 3693, |
| VST3LNd16Pseudo_UPD = 3694, |
| VST3LNd16_UPD = 3695, |
| VST3LNd32 = 3696, |
| VST3LNd32Pseudo = 3697, |
| VST3LNd32Pseudo_UPD = 3698, |
| VST3LNd32_UPD = 3699, |
| VST3LNd8 = 3700, |
| VST3LNd8Pseudo = 3701, |
| VST3LNd8Pseudo_UPD = 3702, |
| VST3LNd8_UPD = 3703, |
| VST3LNq16 = 3704, |
| VST3LNq16Pseudo = 3705, |
| VST3LNq16Pseudo_UPD = 3706, |
| VST3LNq16_UPD = 3707, |
| VST3LNq32 = 3708, |
| VST3LNq32Pseudo = 3709, |
| VST3LNq32Pseudo_UPD = 3710, |
| VST3LNq32_UPD = 3711, |
| VST3d16 = 3712, |
| VST3d16Pseudo = 3713, |
| VST3d16Pseudo_UPD = 3714, |
| VST3d16_UPD = 3715, |
| VST3d32 = 3716, |
| VST3d32Pseudo = 3717, |
| VST3d32Pseudo_UPD = 3718, |
| VST3d32_UPD = 3719, |
| VST3d8 = 3720, |
| VST3d8Pseudo = 3721, |
| VST3d8Pseudo_UPD = 3722, |
| VST3d8_UPD = 3723, |
| VST3q16 = 3724, |
| VST3q16Pseudo_UPD = 3725, |
| VST3q16_UPD = 3726, |
| VST3q16oddPseudo = 3727, |
| VST3q16oddPseudo_UPD = 3728, |
| VST3q32 = 3729, |
| VST3q32Pseudo_UPD = 3730, |
| VST3q32_UPD = 3731, |
| VST3q32oddPseudo = 3732, |
| VST3q32oddPseudo_UPD = 3733, |
| VST3q8 = 3734, |
| VST3q8Pseudo_UPD = 3735, |
| VST3q8_UPD = 3736, |
| VST3q8oddPseudo = 3737, |
| VST3q8oddPseudo_UPD = 3738, |
| VST4LNd16 = 3739, |
| VST4LNd16Pseudo = 3740, |
| VST4LNd16Pseudo_UPD = 3741, |
| VST4LNd16_UPD = 3742, |
| VST4LNd32 = 3743, |
| VST4LNd32Pseudo = 3744, |
| VST4LNd32Pseudo_UPD = 3745, |
| VST4LNd32_UPD = 3746, |
| VST4LNd8 = 3747, |
| VST4LNd8Pseudo = 3748, |
| VST4LNd8Pseudo_UPD = 3749, |
| VST4LNd8_UPD = 3750, |
| VST4LNq16 = 3751, |
| VST4LNq16Pseudo = 3752, |
| VST4LNq16Pseudo_UPD = 3753, |
| VST4LNq16_UPD = 3754, |
| VST4LNq32 = 3755, |
| VST4LNq32Pseudo = 3756, |
| VST4LNq32Pseudo_UPD = 3757, |
| VST4LNq32_UPD = 3758, |
| VST4d16 = 3759, |
| VST4d16Pseudo = 3760, |
| VST4d16Pseudo_UPD = 3761, |
| VST4d16_UPD = 3762, |
| VST4d32 = 3763, |
| VST4d32Pseudo = 3764, |
| VST4d32Pseudo_UPD = 3765, |
| VST4d32_UPD = 3766, |
| VST4d8 = 3767, |
| VST4d8Pseudo = 3768, |
| VST4d8Pseudo_UPD = 3769, |
| VST4d8_UPD = 3770, |
| VST4q16 = 3771, |
| VST4q16Pseudo_UPD = 3772, |
| VST4q16_UPD = 3773, |
| VST4q16oddPseudo = 3774, |
| VST4q16oddPseudo_UPD = 3775, |
| VST4q32 = 3776, |
| VST4q32Pseudo_UPD = 3777, |
| VST4q32_UPD = 3778, |
| VST4q32oddPseudo = 3779, |
| VST4q32oddPseudo_UPD = 3780, |
| VST4q8 = 3781, |
| VST4q8Pseudo_UPD = 3782, |
| VST4q8_UPD = 3783, |
| VST4q8oddPseudo = 3784, |
| VST4q8oddPseudo_UPD = 3785, |
| VSTMDDB_UPD = 3786, |
| VSTMDIA = 3787, |
| VSTMDIA_UPD = 3788, |
| VSTMQIA = 3789, |
| VSTMSDB_UPD = 3790, |
| VSTMSIA = 3791, |
| VSTMSIA_UPD = 3792, |
| VSTRD = 3793, |
| VSTRH = 3794, |
| VSTRS = 3795, |
| VSTR_FPCXTNS_off = 3796, |
| VSTR_FPCXTNS_post = 3797, |
| VSTR_FPCXTNS_pre = 3798, |
| VSTR_FPCXTS_off = 3799, |
| VSTR_FPCXTS_post = 3800, |
| VSTR_FPCXTS_pre = 3801, |
| VSTR_FPSCR_NZCVQC_off = 3802, |
| VSTR_FPSCR_NZCVQC_post = 3803, |
| VSTR_FPSCR_NZCVQC_pre = 3804, |
| VSTR_FPSCR_off = 3805, |
| VSTR_FPSCR_post = 3806, |
| VSTR_FPSCR_pre = 3807, |
| VSTR_P0_off = 3808, |
| VSTR_P0_post = 3809, |
| VSTR_P0_pre = 3810, |
| VSTR_VPR_off = 3811, |
| VSTR_VPR_post = 3812, |
| VSTR_VPR_pre = 3813, |
| VSUBD = 3814, |
| VSUBH = 3815, |
| VSUBHNv2i32 = 3816, |
| VSUBHNv4i16 = 3817, |
| VSUBHNv8i8 = 3818, |
| VSUBLsv2i64 = 3819, |
| VSUBLsv4i32 = 3820, |
| VSUBLsv8i16 = 3821, |
| VSUBLuv2i64 = 3822, |
| VSUBLuv4i32 = 3823, |
| VSUBLuv8i16 = 3824, |
| VSUBS = 3825, |
| VSUBWsv2i64 = 3826, |
| VSUBWsv4i32 = 3827, |
| VSUBWsv8i16 = 3828, |
| VSUBWuv2i64 = 3829, |
| VSUBWuv4i32 = 3830, |
| VSUBWuv8i16 = 3831, |
| VSUBfd = 3832, |
| VSUBfq = 3833, |
| VSUBhd = 3834, |
| VSUBhq = 3835, |
| VSUBv16i8 = 3836, |
| VSUBv1i64 = 3837, |
| VSUBv2i32 = 3838, |
| VSUBv2i64 = 3839, |
| VSUBv4i16 = 3840, |
| VSUBv4i32 = 3841, |
| VSUBv8i16 = 3842, |
| VSUBv8i8 = 3843, |
| VSUDOTDI = 3844, |
| VSUDOTQI = 3845, |
| VSWPd = 3846, |
| VSWPq = 3847, |
| VTBL1 = 3848, |
| VTBL2 = 3849, |
| VTBL3 = 3850, |
| VTBL3Pseudo = 3851, |
| VTBL4 = 3852, |
| VTBL4Pseudo = 3853, |
| VTBX1 = 3854, |
| VTBX2 = 3855, |
| VTBX3 = 3856, |
| VTBX3Pseudo = 3857, |
| VTBX4 = 3858, |
| VTBX4Pseudo = 3859, |
| VTOSHD = 3860, |
| VTOSHH = 3861, |
| VTOSHS = 3862, |
| VTOSIRD = 3863, |
| VTOSIRH = 3864, |
| VTOSIRS = 3865, |
| VTOSIZD = 3866, |
| VTOSIZH = 3867, |
| VTOSIZS = 3868, |
| VTOSLD = 3869, |
| VTOSLH = 3870, |
| VTOSLS = 3871, |
| VTOUHD = 3872, |
| VTOUHH = 3873, |
| VTOUHS = 3874, |
| VTOUIRD = 3875, |
| VTOUIRH = 3876, |
| VTOUIRS = 3877, |
| VTOUIZD = 3878, |
| VTOUIZH = 3879, |
| VTOUIZS = 3880, |
| VTOULD = 3881, |
| VTOULH = 3882, |
| VTOULS = 3883, |
| VTRNd16 = 3884, |
| VTRNd32 = 3885, |
| VTRNd8 = 3886, |
| VTRNq16 = 3887, |
| VTRNq32 = 3888, |
| VTRNq8 = 3889, |
| VTSTv16i8 = 3890, |
| VTSTv2i32 = 3891, |
| VTSTv4i16 = 3892, |
| VTSTv4i32 = 3893, |
| VTSTv8i16 = 3894, |
| VTSTv8i8 = 3895, |
| VUDOTD = 3896, |
| VUDOTDI = 3897, |
| VUDOTQ = 3898, |
| VUDOTQI = 3899, |
| VUHTOD = 3900, |
| VUHTOH = 3901, |
| VUHTOS = 3902, |
| VUITOD = 3903, |
| VUITOH = 3904, |
| VUITOS = 3905, |
| VULTOD = 3906, |
| VULTOH = 3907, |
| VULTOS = 3908, |
| VUMMLA = 3909, |
| VUSDOTD = 3910, |
| VUSDOTDI = 3911, |
| VUSDOTQ = 3912, |
| VUSDOTQI = 3913, |
| VUSMMLA = 3914, |
| VUZPd16 = 3915, |
| VUZPd8 = 3916, |
| VUZPq16 = 3917, |
| VUZPq32 = 3918, |
| VUZPq8 = 3919, |
| VZIPd16 = 3920, |
| VZIPd8 = 3921, |
| VZIPq16 = 3922, |
| VZIPq32 = 3923, |
| VZIPq8 = 3924, |
| sysLDMDA = 3925, |
| sysLDMDA_UPD = 3926, |
| sysLDMDB = 3927, |
| sysLDMDB_UPD = 3928, |
| sysLDMIA = 3929, |
| sysLDMIA_UPD = 3930, |
| sysLDMIB = 3931, |
| sysLDMIB_UPD = 3932, |
| sysSTMDA = 3933, |
| sysSTMDA_UPD = 3934, |
| sysSTMDB = 3935, |
| sysSTMDB_UPD = 3936, |
| sysSTMIA = 3937, |
| sysSTMIA_UPD = 3938, |
| sysSTMIB = 3939, |
| sysSTMIB_UPD = 3940, |
| t2ADCri = 3941, |
| t2ADCrr = 3942, |
| t2ADCrs = 3943, |
| t2ADDri = 3944, |
| t2ADDri12 = 3945, |
| t2ADDrr = 3946, |
| t2ADDrs = 3947, |
| t2ADDspImm = 3948, |
| t2ADDspImm12 = 3949, |
| t2ADR = 3950, |
| t2ANDri = 3951, |
| t2ANDrr = 3952, |
| t2ANDrs = 3953, |
| t2ASRri = 3954, |
| t2ASRrr = 3955, |
| t2AUT = 3956, |
| t2AUTG = 3957, |
| t2B = 3958, |
| t2BFC = 3959, |
| t2BFI = 3960, |
| t2BFLi = 3961, |
| t2BFLr = 3962, |
| t2BFi = 3963, |
| t2BFic = 3964, |
| t2BFr = 3965, |
| t2BICri = 3966, |
| t2BICrr = 3967, |
| t2BICrs = 3968, |
| t2BTI = 3969, |
| t2BXAUT = 3970, |
| t2BXJ = 3971, |
| t2Bcc = 3972, |
| t2CDP = 3973, |
| t2CDP2 = 3974, |
| t2CLREX = 3975, |
| t2CLRM = 3976, |
| t2CLZ = 3977, |
| t2CMNri = 3978, |
| t2CMNzrr = 3979, |
| t2CMNzrs = 3980, |
| t2CMPri = 3981, |
| t2CMPrr = 3982, |
| t2CMPrs = 3983, |
| t2CPS1p = 3984, |
| t2CPS2p = 3985, |
| t2CPS3p = 3986, |
| t2CRC32B = 3987, |
| t2CRC32CB = 3988, |
| t2CRC32CH = 3989, |
| t2CRC32CW = 3990, |
| t2CRC32H = 3991, |
| t2CRC32W = 3992, |
| t2CSEL = 3993, |
| t2CSINC = 3994, |
| t2CSINV = 3995, |
| t2CSNEG = 3996, |
| t2DBG = 3997, |
| t2DCPS1 = 3998, |
| t2DCPS2 = 3999, |
| t2DCPS3 = 4000, |
| t2DLS = 4001, |
| t2DMB = 4002, |
| t2DSB = 4003, |
| t2EORri = 4004, |
| t2EORrr = 4005, |
| t2EORrs = 4006, |
| t2HINT = 4007, |
| t2HVC = 4008, |
| t2ISB = 4009, |
| t2IT = 4010, |
| t2Int_eh_sjlj_setjmp = 4011, |
| t2Int_eh_sjlj_setjmp_nofp = 4012, |
| t2LDA = 4013, |
| t2LDAB = 4014, |
| t2LDAEX = 4015, |
| t2LDAEXB = 4016, |
| t2LDAEXD = 4017, |
| t2LDAEXH = 4018, |
| t2LDAH = 4019, |
| t2LDC2L_OFFSET = 4020, |
| t2LDC2L_OPTION = 4021, |
| t2LDC2L_POST = 4022, |
| t2LDC2L_PRE = 4023, |
| t2LDC2_OFFSET = 4024, |
| t2LDC2_OPTION = 4025, |
| t2LDC2_POST = 4026, |
| t2LDC2_PRE = 4027, |
| t2LDCL_OFFSET = 4028, |
| t2LDCL_OPTION = 4029, |
| t2LDCL_POST = 4030, |
| t2LDCL_PRE = 4031, |
| t2LDC_OFFSET = 4032, |
| t2LDC_OPTION = 4033, |
| t2LDC_POST = 4034, |
| t2LDC_PRE = 4035, |
| t2LDMDB = 4036, |
| t2LDMDB_UPD = 4037, |
| t2LDMIA = 4038, |
| t2LDMIA_UPD = 4039, |
| t2LDRBT = 4040, |
| t2LDRB_POST = 4041, |
| t2LDRB_PRE = 4042, |
| t2LDRBi12 = 4043, |
| t2LDRBi8 = 4044, |
| t2LDRBpci = 4045, |
| t2LDRBs = 4046, |
| t2LDRD_POST = 4047, |
| t2LDRD_PRE = 4048, |
| t2LDRDi8 = 4049, |
| t2LDREX = 4050, |
| t2LDREXB = 4051, |
| t2LDREXD = 4052, |
| t2LDREXH = 4053, |
| t2LDRHT = 4054, |
| t2LDRH_POST = 4055, |
| t2LDRH_PRE = 4056, |
| t2LDRHi12 = 4057, |
| t2LDRHi8 = 4058, |
| t2LDRHpci = 4059, |
| t2LDRHs = 4060, |
| t2LDRSBT = 4061, |
| t2LDRSB_POST = 4062, |
| t2LDRSB_PRE = 4063, |
| t2LDRSBi12 = 4064, |
| t2LDRSBi8 = 4065, |
| t2LDRSBpci = 4066, |
| t2LDRSBs = 4067, |
| t2LDRSHT = 4068, |
| t2LDRSH_POST = 4069, |
| t2LDRSH_PRE = 4070, |
| t2LDRSHi12 = 4071, |
| t2LDRSHi8 = 4072, |
| t2LDRSHpci = 4073, |
| t2LDRSHs = 4074, |
| t2LDRT = 4075, |
| t2LDR_POST = 4076, |
| t2LDR_PRE = 4077, |
| t2LDRi12 = 4078, |
| t2LDRi8 = 4079, |
| t2LDRpci = 4080, |
| t2LDRs = 4081, |
| t2LE = 4082, |
| t2LEUpdate = 4083, |
| t2LSLri = 4084, |
| t2LSLrr = 4085, |
| t2LSRri = 4086, |
| t2LSRrr = 4087, |
| t2MCR = 4088, |
| t2MCR2 = 4089, |
| t2MCRR = 4090, |
| t2MCRR2 = 4091, |
| t2MLA = 4092, |
| t2MLS = 4093, |
| t2MOVTi16 = 4094, |
| t2MOVi = 4095, |
| t2MOVi16 = 4096, |
| t2MOVr = 4097, |
| t2MOVsra_flag = 4098, |
| t2MOVsrl_flag = 4099, |
| t2MRC = 4100, |
| t2MRC2 = 4101, |
| t2MRRC = 4102, |
| t2MRRC2 = 4103, |
| t2MRS_AR = 4104, |
| t2MRS_M = 4105, |
| t2MRSbanked = 4106, |
| t2MRSsys_AR = 4107, |
| t2MSR_AR = 4108, |
| t2MSR_M = 4109, |
| t2MSRbanked = 4110, |
| t2MUL = 4111, |
| t2MVNi = 4112, |
| t2MVNr = 4113, |
| t2MVNs = 4114, |
| t2ORNri = 4115, |
| t2ORNrr = 4116, |
| t2ORNrs = 4117, |
| t2ORRri = 4118, |
| t2ORRrr = 4119, |
| t2ORRrs = 4120, |
| t2PAC = 4121, |
| t2PACBTI = 4122, |
| t2PACG = 4123, |
| t2PKHBT = 4124, |
| t2PKHTB = 4125, |
| t2PLDWi12 = 4126, |
| t2PLDWi8 = 4127, |
| t2PLDWs = 4128, |
| t2PLDi12 = 4129, |
| t2PLDi8 = 4130, |
| t2PLDpci = 4131, |
| t2PLDs = 4132, |
| t2PLIi12 = 4133, |
| t2PLIi8 = 4134, |
| t2PLIpci = 4135, |
| t2PLIs = 4136, |
| t2QADD = 4137, |
| t2QADD16 = 4138, |
| t2QADD8 = 4139, |
| t2QASX = 4140, |
| t2QDADD = 4141, |
| t2QDSUB = 4142, |
| t2QSAX = 4143, |
| t2QSUB = 4144, |
| t2QSUB16 = 4145, |
| t2QSUB8 = 4146, |
| t2RBIT = 4147, |
| t2REV = 4148, |
| t2REV16 = 4149, |
| t2REVSH = 4150, |
| t2RFEDB = 4151, |
| t2RFEDBW = 4152, |
| t2RFEIA = 4153, |
| t2RFEIAW = 4154, |
| t2RORri = 4155, |
| t2RORrr = 4156, |
| t2RRX = 4157, |
| t2RSBri = 4158, |
| t2RSBrr = 4159, |
| t2RSBrs = 4160, |
| t2SADD16 = 4161, |
| t2SADD8 = 4162, |
| t2SASX = 4163, |
| t2SB = 4164, |
| t2SBCri = 4165, |
| t2SBCrr = 4166, |
| t2SBCrs = 4167, |
| t2SBFX = 4168, |
| t2SDIV = 4169, |
| t2SEL = 4170, |
| t2SETPAN = 4171, |
| t2SG = 4172, |
| t2SHADD16 = 4173, |
| t2SHADD8 = 4174, |
| t2SHASX = 4175, |
| t2SHSAX = 4176, |
| t2SHSUB16 = 4177, |
| t2SHSUB8 = 4178, |
| t2SMC = 4179, |
| t2SMLABB = 4180, |
| t2SMLABT = 4181, |
| t2SMLAD = 4182, |
| t2SMLADX = 4183, |
| t2SMLAL = 4184, |
| t2SMLALBB = 4185, |
| t2SMLALBT = 4186, |
| t2SMLALD = 4187, |
| t2SMLALDX = 4188, |
| t2SMLALTB = 4189, |
| t2SMLALTT = 4190, |
| t2SMLATB = 4191, |
| t2SMLATT = 4192, |
| t2SMLAWB = 4193, |
| t2SMLAWT = 4194, |
| t2SMLSD = 4195, |
| t2SMLSDX = 4196, |
| t2SMLSLD = 4197, |
| t2SMLSLDX = 4198, |
| t2SMMLA = 4199, |
| t2SMMLAR = 4200, |
| t2SMMLS = 4201, |
| t2SMMLSR = 4202, |
| t2SMMUL = 4203, |
| t2SMMULR = 4204, |
| t2SMUAD = 4205, |
| t2SMUADX = 4206, |
| t2SMULBB = 4207, |
| t2SMULBT = 4208, |
| t2SMULL = 4209, |
| t2SMULTB = 4210, |
| t2SMULTT = 4211, |
| t2SMULWB = 4212, |
| t2SMULWT = 4213, |
| t2SMUSD = 4214, |
| t2SMUSDX = 4215, |
| t2SRSDB = 4216, |
| t2SRSDB_UPD = 4217, |
| t2SRSIA = 4218, |
| t2SRSIA_UPD = 4219, |
| t2SSAT = 4220, |
| t2SSAT16 = 4221, |
| t2SSAX = 4222, |
| t2SSUB16 = 4223, |
| t2SSUB8 = 4224, |
| t2STC2L_OFFSET = 4225, |
| t2STC2L_OPTION = 4226, |
| t2STC2L_POST = 4227, |
| t2STC2L_PRE = 4228, |
| t2STC2_OFFSET = 4229, |
| t2STC2_OPTION = 4230, |
| t2STC2_POST = 4231, |
| t2STC2_PRE = 4232, |
| t2STCL_OFFSET = 4233, |
| t2STCL_OPTION = 4234, |
| t2STCL_POST = 4235, |
| t2STCL_PRE = 4236, |
| t2STC_OFFSET = 4237, |
| t2STC_OPTION = 4238, |
| t2STC_POST = 4239, |
| t2STC_PRE = 4240, |
| t2STL = 4241, |
| t2STLB = 4242, |
| t2STLEX = 4243, |
| t2STLEXB = 4244, |
| t2STLEXD = 4245, |
| t2STLEXH = 4246, |
| t2STLH = 4247, |
| t2STMDB = 4248, |
| t2STMDB_UPD = 4249, |
| t2STMIA = 4250, |
| t2STMIA_UPD = 4251, |
| t2STRBT = 4252, |
| t2STRB_POST = 4253, |
| t2STRB_PRE = 4254, |
| t2STRBi12 = 4255, |
| t2STRBi8 = 4256, |
| t2STRBs = 4257, |
| t2STRD_POST = 4258, |
| t2STRD_PRE = 4259, |
| t2STRDi8 = 4260, |
| t2STREX = 4261, |
| t2STREXB = 4262, |
| t2STREXD = 4263, |
| t2STREXH = 4264, |
| t2STRHT = 4265, |
| t2STRH_POST = 4266, |
| t2STRH_PRE = 4267, |
| t2STRHi12 = 4268, |
| t2STRHi8 = 4269, |
| t2STRHs = 4270, |
| t2STRT = 4271, |
| t2STR_POST = 4272, |
| t2STR_PRE = 4273, |
| t2STRi12 = 4274, |
| t2STRi8 = 4275, |
| t2STRs = 4276, |
| t2SUBS_PC_LR = 4277, |
| t2SUBri = 4278, |
| t2SUBri12 = 4279, |
| t2SUBrr = 4280, |
| t2SUBrs = 4281, |
| t2SUBspImm = 4282, |
| t2SUBspImm12 = 4283, |
| t2SXTAB = 4284, |
| t2SXTAB16 = 4285, |
| t2SXTAH = 4286, |
| t2SXTB = 4287, |
| t2SXTB16 = 4288, |
| t2SXTH = 4289, |
| t2TBB = 4290, |
| t2TBH = 4291, |
| t2TEQri = 4292, |
| t2TEQrr = 4293, |
| t2TEQrs = 4294, |
| t2TSB = 4295, |
| t2TSTri = 4296, |
| t2TSTrr = 4297, |
| t2TSTrs = 4298, |
| t2TT = 4299, |
| t2TTA = 4300, |
| t2TTAT = 4301, |
| t2TTT = 4302, |
| t2UADD16 = 4303, |
| t2UADD8 = 4304, |
| t2UASX = 4305, |
| t2UBFX = 4306, |
| t2UDF = 4307, |
| t2UDIV = 4308, |
| t2UHADD16 = 4309, |
| t2UHADD8 = 4310, |
| t2UHASX = 4311, |
| t2UHSAX = 4312, |
| t2UHSUB16 = 4313, |
| t2UHSUB8 = 4314, |
| t2UMAAL = 4315, |
| t2UMLAL = 4316, |
| t2UMULL = 4317, |
| t2UQADD16 = 4318, |
| t2UQADD8 = 4319, |
| t2UQASX = 4320, |
| t2UQSAX = 4321, |
| t2UQSUB16 = 4322, |
| t2UQSUB8 = 4323, |
| t2USAD8 = 4324, |
| t2USADA8 = 4325, |
| t2USAT = 4326, |
| t2USAT16 = 4327, |
| t2USAX = 4328, |
| t2USUB16 = 4329, |
| t2USUB8 = 4330, |
| t2UXTAB = 4331, |
| t2UXTAB16 = 4332, |
| t2UXTAH = 4333, |
| t2UXTB = 4334, |
| t2UXTB16 = 4335, |
| t2UXTH = 4336, |
| t2WLS = 4337, |
| tADC = 4338, |
| tADDhirr = 4339, |
| tADDi3 = 4340, |
| tADDi8 = 4341, |
| tADDrSP = 4342, |
| tADDrSPi = 4343, |
| tADDrr = 4344, |
| tADDspi = 4345, |
| tADDspr = 4346, |
| tADR = 4347, |
| tAND = 4348, |
| tASRri = 4349, |
| tASRrr = 4350, |
| tB = 4351, |
| tBIC = 4352, |
| tBKPT = 4353, |
| tBL = 4354, |
| tBLXNSr = 4355, |
| tBLXi = 4356, |
| tBLXr = 4357, |
| tBX = 4358, |
| tBXNS = 4359, |
| tBcc = 4360, |
| tCBNZ = 4361, |
| tCBZ = 4362, |
| tCMNz = 4363, |
| tCMPhir = 4364, |
| tCMPi8 = 4365, |
| tCMPr = 4366, |
| tCPS = 4367, |
| tEOR = 4368, |
| tHINT = 4369, |
| tHLT = 4370, |
| tInt_WIN_eh_sjlj_longjmp = 4371, |
| tInt_eh_sjlj_longjmp = 4372, |
| tInt_eh_sjlj_setjmp = 4373, |
| tLDMIA = 4374, |
| tLDRBi = 4375, |
| tLDRBr = 4376, |
| tLDRHi = 4377, |
| tLDRHr = 4378, |
| tLDRSB = 4379, |
| tLDRSH = 4380, |
| tLDRi = 4381, |
| tLDRpci = 4382, |
| tLDRr = 4383, |
| tLDRspi = 4384, |
| tLSLri = 4385, |
| tLSLrr = 4386, |
| tLSRri = 4387, |
| tLSRrr = 4388, |
| tMOVSr = 4389, |
| tMOVi8 = 4390, |
| tMOVr = 4391, |
| tMUL = 4392, |
| tMVN = 4393, |
| tORR = 4394, |
| tPICADD = 4395, |
| tPOP = 4396, |
| tPUSH = 4397, |
| tREV = 4398, |
| tREV16 = 4399, |
| tREVSH = 4400, |
| tROR = 4401, |
| tRSB = 4402, |
| tSBC = 4403, |
| tSETEND = 4404, |
| tSTMIA_UPD = 4405, |
| tSTRBi = 4406, |
| tSTRBr = 4407, |
| tSTRHi = 4408, |
| tSTRHr = 4409, |
| tSTRi = 4410, |
| tSTRr = 4411, |
| tSTRspi = 4412, |
| tSUBi3 = 4413, |
| tSUBi8 = 4414, |
| tSUBrr = 4415, |
| tSUBspi = 4416, |
| tSVC = 4417, |
| tSXTB = 4418, |
| tSXTH = 4419, |
| tTRAP = 4420, |
| tTST = 4421, |
| tUDF = 4422, |
| tUXTB = 4423, |
| tUXTH = 4424, |
| t__brkdiv0 = 4425, |
| INSTRUCTION_LIST_END = 4426 |
| }; |
| |
| } // end namespace ARM |
| } // end namespace llvm |
| #endif // GET_INSTRINFO_ENUM |
| |
| #ifdef GET_INSTRINFO_SCHED_ENUM |
| #undef GET_INSTRINFO_SCHED_ENUM |
| namespace llvm { |
| |
| namespace ARM { |
| namespace Sched { |
| enum { |
| NoInstrModel = 0, |
| IIC_iALUi_WriteALU_ReadALU = 1, |
| IIC_iALUr_WriteALU_ReadALU_ReadALU = 2, |
| IIC_iALUsr_WriteALUsi_ReadALU = 3, |
| IIC_iALUsr_WriteALUSsr_ReadALUsr = 4, |
| IIC_Br_WriteBr = 5, |
| IIC_Br_WriteBrL = 6, |
| IIC_Br_WriteBrTbl = 7, |
| IIC_iLoad_mBr = 8, |
| IIC_iLoad_i = 9, |
| IIC_iLoadiALU = 10, |
| IIC_iLoad_d_r = 11, |
| IIC_iMAC32_WriteMAC32_ReadMUL_ReadMUL_ReadMAC = 12, |
| IIC_iCMOVi_WriteALU = 13, |
| IIC_iMOVi_WriteALU = 14, |
| IIC_iCMOVix2 = 15, |
| IIC_iCMOVr_WriteALU = 16, |
| IIC_iCMOVsr_WriteALU = 17, |
| IIC_iMOVix2addpc = 18, |
| IIC_iMOVix2ld = 19, |
| IIC_iMOVix2 = 20, |
| IIC_iMOVsi_WriteALU = 21, |
| IIC_iMUL32_WriteMUL32_ReadMUL_ReadMUL = 22, |
| IIC_iALUr_WriteALU_ReadALU = 23, |
| IIC_iLoad_r = 24, |
| IIC_iLoad_bh_r = 25, |
| IIC_iStore_r = 26, |
| IIC_iStore_bh_r = 27, |
| IIC_iMAC64_WriteMAC64Lo_WriteMAC64Hi_ReadMUL_ReadMUL_ReadMAC_ReadMAC = 28, |
| IIC_iMUL64_WriteMUL64Lo_WriteMUL64Hi_ReadMUL_ReadMUL = 29, |
| IIC_iStore_d_r = 30, |
| IIC_iStore_ru = 31, |
| IIC_Br = 32, |
| IIC_VMOVImm = 33, |
| IIC_fpUNA64 = 34, |
| IIC_fpUNA16 = 35, |
| IIC_fpUNA32 = 36, |
| IIC_iALUsi_WriteALUsi_ReadALUsr = 37, |
| IIC_iCMOVsi_WriteALU = 38, |
| IIC_iALUsi_WriteALUsi_ReadALU = 39, |
| IIC_iStore_ru_WriteST = 40, |
| IIC_iALUr_WriteALU = 41, |
| IIC_iALUi_WriteALU = 42, |
| IIC_iLoad_mu = 43, |
| IIC_iPop_Br_WriteBrL = 44, |
| IIC_iALUsr_WriteALUsr_ReadALUsr = 45, |
| IIC_iBITi_WriteALU_ReadALU = 46, |
| IIC_iBITr_WriteALU_ReadALU_ReadALU = 47, |
| IIC_iBITsr_WriteALUsi_ReadALU = 48, |
| IIC_iBITsr_WriteALUsr_ReadALUsr = 49, |
| IIC_VDOTPROD = 50, |
| IIC_iUNAsi = 51, |
| WriteBrL = 52, |
| WriteBr = 53, |
| IIC_iUNAr_WriteALU = 54, |
| IIC_iCMPi_WriteCMP_ReadALU = 55, |
| IIC_iCMPr_WriteCMP_ReadALU_ReadALU = 56, |
| IIC_iCMPsr_WriteCMPsi_ReadALU = 57, |
| IIC_iCMPsr_WriteCMPsr_ReadALU = 58, |
| IIC_fpSTAT = 59, |
| IIC_iLoad_m = 60, |
| IIC_iLoad_bh_ru = 61, |
| IIC_iLoad_bh_iu = 62, |
| IIC_iLoad_bh_si = 63, |
| IIC_iLoad_d_ru = 64, |
| IIC_iLoad_ru = 65, |
| IIC_iLoad_iu = 66, |
| IIC_iLoad_si = 67, |
| IIC_iMOVr_WriteALU = 68, |
| IIC_iMOVsr_WriteALU = 69, |
| IIC_iMVNi_WriteALU = 70, |
| IIC_iMVNr_WriteALU = 71, |
| IIC_iMVNsr_WriteALU = 72, |
| IIC_iBITsi_WriteALUsi_ReadALU = 73, |
| IIC_Preload_WritePreLd = 74, |
| IIC_iDIV_WriteDIV = 75, |
| IIC_iMAC16_WriteMAC16_ReadMUL_ReadMUL_ReadMAC = 76, |
| WriteMAC32_ReadMUL_ReadMUL_ReadMAC = 77, |
| WriteMAC64Lo_WriteMAC64Hi_ReadMUL_ReadMUL_ReadMAC_ReadMAC = 78, |
| WriteMUL64Lo_WriteMUL64Hi_ReadMUL_ReadMUL = 79, |
| WriteMUL32_ReadMUL_ReadMUL = 80, |
| IIC_iMUL16_WriteMUL16_ReadMUL_ReadMUL = 81, |
| IIC_iStore_m = 82, |
| IIC_iStore_mu = 83, |
| IIC_iStore_bh_ru = 84, |
| IIC_iStore_bh_iu = 85, |
| IIC_iStore_bh_si = 86, |
| IIC_iStore_d_ru = 87, |
| IIC_iStore_iu = 88, |
| IIC_iStore_si = 89, |
| IIC_iEXTAr_WriteALUsr = 90, |
| IIC_iEXTr_WriteALUsi = 91, |
| IIC_iTSTi_WriteCMP_ReadALU = 92, |
| IIC_iTSTr_WriteCMP_ReadALU_ReadALU = 93, |
| IIC_iTSTsr_WriteCMPsi_ReadALU = 94, |
| IIC_iTSTsr_WriteCMPsr_ReadALU = 95, |
| IIC_iMUL64_WriteMAC64Lo_WriteMAC64Hi_ReadMUL_ReadMUL = 96, |
| WriteALU_ReadALU_ReadALU = 97, |
| IIC_VABAD = 98, |
| IIC_VABAQ = 99, |
| IIC_VSUBi4Q = 100, |
| IIC_VBIND = 101, |
| IIC_VBINQ = 102, |
| IIC_VSUBi4D = 103, |
| IIC_VUNAD = 104, |
| IIC_VUNAQ = 105, |
| IIC_VUNAiQ = 106, |
| IIC_VUNAiD = 107, |
| IIC_fpALU64_WriteFPALU64 = 108, |
| IIC_fpALU16_WriteFPALU32 = 109, |
| IIC_VBINi4D = 110, |
| IIC_VSHLiD = 111, |
| IIC_fpALU32_WriteFPALU32 = 112, |
| IIC_VSUBiD = 113, |
| IIC_VBINiQ = 114, |
| IIC_VBINiD = 115, |
| IIC_VMACD = 116, |
| IIC_VMACQ = 117, |
| IIC_VCNTiQ = 118, |
| IIC_VCNTiD = 119, |
| IIC_fpCMP64 = 120, |
| IIC_fpCMP16 = 121, |
| IIC_fpCMP32 = 122, |
| WriteFPCVT = 123, |
| IIC_fpCVTSH_WriteFPCVT = 124, |
| IIC_fpCVTHS_WriteFPCVT = 125, |
| IIC_fpCVTDS_WriteFPCVT = 126, |
| IIC_fpCVTSD_WriteFPCVT = 127, |
| IIC_fpDIV64_WriteFPDIV64 = 128, |
| IIC_fpDIV16_WriteFPDIV32 = 129, |
| IIC_fpDIV32_WriteFPDIV32 = 130, |
| IIC_VMOVIS = 131, |
| IIC_VMOVD = 132, |
| IIC_VMOVQ = 133, |
| IIC_VEXTD = 134, |
| IIC_VEXTQ = 135, |
| IIC_fpFMAC64_WriteFPMAC64_ReadFPMAC_ReadFPMUL_ReadFPMUL = 136, |
| IIC_fpFMAC16_WriteFPMAC32_ReadFPMAC_ReadFPMUL_ReadFPMUL = 137, |
| IIC_fpFMAC32_WriteFPMAC32_ReadFPMAC_ReadFPMUL_ReadFPMUL = 138, |
| IIC_VFMACD = 139, |
| IIC_VFMACQ = 140, |
| IIC_VMOVSI = 141, |
| IIC_VBINi4Q = 142, |
| IIC_fpCVTDI = 143, |
| IIC_VLD1dup_WriteVLD2 = 144, |
| IIC_VLD1dupu = 145, |
| IIC_VLD1dup = 146, |
| IIC_VLD1dupu_WriteVLD1 = 147, |
| IIC_VLD1ln = 148, |
| IIC_VLD1lnu_WriteVLD1 = 149, |
| IIC_VLD1ln_WriteVLD1 = 150, |
| IIC_VLD1_WriteVLD1 = 151, |
| IIC_VLD1x4_WriteVLD4 = 152, |
| IIC_VLD1x2u_WriteVLD4 = 153, |
| IIC_VLD1x3_WriteVLD3 = 154, |
| IIC_VLD1x2u_WriteVLD3 = 155, |
| IIC_VLD1u_WriteVLD1 = 156, |
| IIC_VLD1x2_WriteVLD2 = 157, |
| IIC_VLD1x2u_WriteVLD2 = 158, |
| IIC_VLD2dup = 159, |
| IIC_VLD2dupu_WriteVLD1 = 160, |
| IIC_VLD2dup_WriteVLD2 = 161, |
| IIC_VLD2ln_WriteVLD1 = 162, |
| IIC_VLD2lnu_WriteVLD1 = 163, |
| IIC_VLD2lnu = 164, |
| IIC_VLD2_WriteVLD2 = 165, |
| IIC_VLD2u_WriteVLD2 = 166, |
| IIC_VLD2x2_WriteVLD4 = 167, |
| IIC_VLD2x2u_WriteVLD4 = 168, |
| IIC_VLD3dup_WriteVLD2 = 169, |
| IIC_VLD3dupu_WriteVLD2 = 170, |
| IIC_VLD3ln_WriteVLD2 = 171, |
| IIC_VLD3lnu_WriteVLD2 = 172, |
| IIC_VLD3_WriteVLD3 = 173, |
| IIC_VLD3u_WriteVLD3 = 174, |
| IIC_VLD4dup = 175, |
| IIC_VLD4dup_WriteVLD2 = 176, |
| IIC_VLD4dupu_WriteVLD2 = 177, |
| IIC_VLD4ln_WriteVLD2 = 178, |
| IIC_VLD4lnu_WriteVLD2 = 179, |
| IIC_VLD4lnu = 180, |
| IIC_VLD4_WriteVLD4 = 181, |
| IIC_VLD4u_WriteVLD4 = 182, |
| IIC_fpLoad_mu = 183, |
| IIC_fpLoad_m = 184, |
| IIC_fpLoad64 = 185, |
| IIC_fpLoad16 = 186, |
| IIC_fpLoad32 = 187, |
| IIC_fpMAC64_WriteFPMAC64_ReadFPMAC_ReadFPMUL_ReadFPMUL = 188, |
| IIC_fpMAC16 = 189, |
| IIC_VMACi32D = 190, |
| IIC_VMACi16D = 191, |
| IIC_fpMAC32_WriteFPMAC32_ReadFPMAC_ReadFPMUL_ReadFPMUL = 192, |
| IIC_VMACi32Q = 193, |
| IIC_VMACi16Q = 194, |
| IIC_fpMOVID_WriteFPMOV = 195, |
| IIC_fpMOVIS_WriteFPMOV = 196, |
| IIC_VQUNAiD = 197, |
| IIC_VMOVN = 198, |
| IIC_fpMOVSI_WriteFPMOV = 199, |
| IIC_fpMOVDI_WriteFPMOV = 200, |
| IIC_fpMUL64_WriteFPMUL64_ReadFPMUL_ReadFPMUL = 201, |
| IIC_fpMUL16_WriteFPMUL32_ReadFPMUL_ReadFPMUL = 202, |
| IIC_VMULi16D = 203, |
| IIC_VMULi32D = 204, |
| IIC_fpMUL32_WriteFPMUL32_ReadFPMUL_ReadFPMUL = 205, |
| IIC_VFMULD = 206, |
| IIC_VFMULQ = 207, |
| IIC_VMULi16Q = 208, |
| IIC_VMULi32Q = 209, |
| IIC_VSHLiQ = 210, |
| IIC_VPALiQ = 211, |
| IIC_VPALiD = 212, |
| IIC_VPBIND = 213, |
| IIC_VQUNAiQ = 214, |
| IIC_VSHLi4Q = 215, |
| IIC_VSHLi4D = 216, |
| IIC_VRECSD = 217, |
| IIC_VRECSQ = 218, |
| IIC_VMOVISL = 219, |
| IIC_fpCVTID_WriteFPCVT = 220, |
| IIC_fpCVTIH_WriteFPCVT = 221, |
| IIC_fpCVTIS_WriteFPCVT = 222, |
| IIC_fpSQRT64_WriteFPSQRT64 = 223, |
| IIC_fpSQRT16 = 224, |
| IIC_fpSQRT32_WriteFPSQRT32 = 225, |
| IIC_VST1ln_WriteVST1 = 226, |
| IIC_VST1lnu_WriteVST1 = 227, |
| IIC_VST1_WriteVST1 = 228, |
| IIC_VST1x4_WriteVST4 = 229, |
| IIC_VST1x4u_WriteVST4 = 230, |
| IIC_VLD1x4u_WriteVST4 = 231, |
| IIC_VST1x3_WriteVST3 = 232, |
| IIC_VST1x3u_WriteVST3 = 233, |
| IIC_VLD1x3u_WriteVST3 = 234, |
| IIC_VLD1u_WriteVST1 = 235, |
| IIC_VST1x2_WriteVST2 = 236, |
| IIC_VLD1x2u_WriteVST2 = 237, |
| IIC_VST2ln_WriteVST1 = 238, |
| IIC_VST2lnu_WriteVST1 = 239, |
| IIC_VST2lnu = 240, |
| IIC_VST2 = 241, |
| IIC_VLD1u_WriteVST2 = 242, |
| IIC_VST2_WriteVST2 = 243, |
| IIC_VST2x2_WriteVST4 = 244, |
| IIC_VST2x2u_WriteVST4 = 245, |
| IIC_VLD1u_WriteVST4 = 246, |
| IIC_VST3ln_WriteVST2 = 247, |
| IIC_VST3lnu_WriteVST2 = 248, |
| IIC_VST3lnu = 249, |
| IIC_VST3ln = 250, |
| IIC_VST3_WriteVST3 = 251, |
| IIC_VST3u_WriteVST3 = 252, |
| IIC_VST4ln_WriteVST2 = 253, |
| IIC_VST4lnu_WriteVST2 = 254, |
| IIC_VST4lnu = 255, |
| IIC_VST4_WriteVST4 = 256, |
| IIC_VST4u_WriteVST4 = 257, |
| IIC_fpStore_mu = 258, |
| IIC_fpStore_m = 259, |
| IIC_fpStore64 = 260, |
| IIC_fpStore16 = 261, |
| IIC_fpStore32 = 262, |
| IIC_VSUBiQ = 263, |
| IIC_VTB1 = 264, |
| IIC_VTB2 = 265, |
| IIC_VTB3 = 266, |
| IIC_VTB4 = 267, |
| IIC_VTBX1 = 268, |
| IIC_VTBX2 = 269, |
| IIC_VTBX3 = 270, |
| IIC_VTBX4 = 271, |
| IIC_fpCVTDI_WriteFPCVT = 272, |
| IIC_fpCVTHI_WriteFPCVT = 273, |
| IIC_fpCVTSI_WriteFPCVT = 274, |
| IIC_VPERMD = 275, |
| IIC_VPERMQ = 276, |
| IIC_VPERMQ3 = 277, |
| IIC_iUNAsi_WriteALU = 278, |
| IIC_iBITi_WriteALU = 279, |
| IIC_iCMPsi_WriteCMPsi_ReadALU_ReadALU = 280, |
| IIC_iCMPi_WriteCMP = 281, |
| IIC_iCMPr_WriteCMP = 282, |
| IIC_iCMPsi_WriteCMPsi = 283, |
| IIC_iALUx = 284, |
| WriteLd = 285, |
| IIC_iLoad_bh_i_WriteLd = 286, |
| IIC_iLoad_bh_iu_WriteLd = 287, |
| IIC_iLoad_bh_si_WriteLd = 288, |
| IIC_iLoad_d_ru_WriteLd = 289, |
| IIC_iLoad_d_i_WriteLd = 290, |
| IIC_iLoad_i_WriteLd = 291, |
| IIC_iLoad_iu_WriteLd = 292, |
| IIC_iLoad_si_WriteLd = 293, |
| IIC_iMVNsi_WriteALU = 294, |
| IIC_iALUsir_WriteALUsi_ReadALU = 295, |
| IIC_iMUL16_WriteMAC16_ReadMUL_ReadMUL_ReadMAC = 296, |
| IIC_iMAC32 = 297, |
| WriteALU = 298, |
| WriteST = 299, |
| IIC_iStore_bh_i_WriteST = 300, |
| IIC_iStore_bh_iu_WriteST = 301, |
| IIC_iStore_bh_si_WriteST = 302, |
| IIC_iStore_d_ru_WriteST = 303, |
| IIC_iStore_d_r_WriteST = 304, |
| IIC_iStore_iu_WriteST = 305, |
| IIC_iStore_i_WriteST = 306, |
| IIC_iStore_si_WriteST = 307, |
| IIC_iEXTAsr_WriteALU_ReadALU = 308, |
| IIC_iEXTr_WriteALU_ReadALU = 309, |
| IIC_iTSTi_WriteCMP = 310, |
| IIC_iTSTr_WriteCMP = 311, |
| IIC_iTSTsi_WriteCMPsi = 312, |
| IIC_iBITr_WriteALU = 313, |
| IIC_iLoad_bh_r_WriteLd = 314, |
| IIC_iLoad_r_WriteLd = 315, |
| IIC_iPop_WriteLd = 316, |
| IIC_iStore_m_WriteST = 317, |
| IIC_iStore_bh_r_WriteST = 318, |
| IIC_iStore_r_WriteST = 319, |
| IIC_iTSTr_WriteALU = 320, |
| ANDri_ORRri_EORri_BICri = 321, |
| ANDrr_ORRrr_EORrr_BICrr = 322, |
| ANDrsi_ORRrsi_EORrsi_BICrsi = 323, |
| ANDrsr_ORRrsr_EORrsr_BICrsr = 324, |
| MOVsra_flag_MOVsrl_flag = 325, |
| MOVsr_MOVsi = 326, |
| MVNsr = 327, |
| MOVCCsi_MOVCCsr = 328, |
| MVNr = 329, |
| MOVCCi32imm = 330, |
| MOVi32imm = 331, |
| MOV_ga_pcrel = 332, |
| MOV_ga_pcrel_ldr = 333, |
| SEL = 334, |
| BFC_BFI_UBFX_SBFX = 335, |
| MULv5_MUL_SMMUL_SMMULR = 336, |
| MLAv5_MLA_MLS_SMMLA_SMMLAR_SMMLS_SMMLSR = 337, |
| SMULLv5_SMULL_UMULLv5 = 338, |
| UMULL = 339, |
| SMLAL_UMLALv5_UMLAL_UMAAL_SMLALv5_SMLALBB_SMLALBT_SMLALTB_SMLALTT = 340, |
| SMLAD_SMLADX_SMLSD_SMLSDX = 341, |
| SMLALD_SMLSLD = 342, |
| SMLALDX_SMLSLDX = 343, |
| SMUAD_SMUADX_SMUSD_SMUSDX = 344, |
| SMULBB_SMULBT_SMULTB_SMULTT_SMULWB_SMULWT = 345, |
| SMLABB_SMLABT_SMLATB_SMLATT_SMLAWB_SMLAWT = 346, |
| LDRi12_PICLDR = 347, |
| LDRrs = 348, |
| LDRBi12_PICLDRH_PICLDRB_PICLDRSH_PICLDRSB_LDRH_LDRSH_LDRSB = 349, |
| LDRHTii_LDRSHTii_LDRSBTii = 350, |
| LDRHTi_LDRHTr_LDRH_POST_LDRH_PRE_LDRSHTi_LDRSHTr_LDRSH_POST_LDRSH_PRE_LDRSBTi_LDRSBTr_LDRSB_POST_LDRSB_PRE = 351, |
| SXTB_SXTB16_SXTH_UXTB_UXTB16_UXTH = 352, |
| t2SXTB_t2SXTB16_t2SXTH_t2UXTB_t2UXTB16_t2UXTH = 353, |
| t2MOVCCi32imm = 354, |
| t2MOVi32imm = 355, |
| t2MOV_ga_pcrel = 356, |
| t2MOVi16_ga_pcrel = 357, |
| t2SEL = 358, |
| t2BFC_t2UBFX_t2SBFX = 359, |
| t2BFI = 360, |
| QADD_QADD16_QADD8_QSUB_QSUB16_QSUB8_QDADD_QDSUB_QASX_QSAX_UQADD8_UQADD16_UQSUB8_UQSUB16_UQASX_UQSAX = 361, |
| SSAT_SSAT16_USAT_USAT16_t2QADD_t2QADD16_t2QADD8_t2QSUB_t2QSUB16_t2QSUB8_t2QDADD_t2QDSUB_t2QASX_t2QSAX_t2UQADD8_t2UQADD16_t2UQSUB8_t2UQSUB16_t2UQASX_t2UQSAX = 362, |
| t2SSAT_t2SSAT16_t2USAT_t2USAT16 = 363, |
| SADD8_SADD16_SSUB8_SSUB16_SASX_SSAX_UADD8_UADD16_USUB8_USUB16_UASX_USAX = 364, |
| t2SADD8_t2SADD16_t2SSUB8_t2SSUB16_t2SASX_t2SSAX_t2UADD8_t2UADD16_t2USUB8_t2USUB16_t2UASX_t2USAX = 365, |
| SHADD8_SHADD16_SHSUB8_SHSUB16_SHASX_SHSAX_UHADD8_UHADD16_UHSUB8_UHSUB16_UHASX_UHSAX = 366, |
| SXTAB_SXTAB16_SXTAH_UXTAB_UXTAB16_UXTAH = 367, |
| t2SHADD8_t2SHADD16_t2SHSUB8_t2SHSUB16_t2SHASX_t2SHSAX_t2UHADD8_t2UHADD16_t2UHSUB8_t2UHSUB16_t2UHASX_t2UHSAX = 368, |
| t2SXTAB_t2SXTAB16_t2SXTAH_t2UXTAB_t2UXTAB16_t2UXTAH = 369, |
| USAD8 = 370, |
| USADA8 = 371, |
| SMUSD_SMUSDX = 372, |
| t2MUL_t2SMMUL_t2SMMULR = 373, |
| t2SMULBB_t2SMULBT_t2SMULTB_t2SMULTT_t2SMULWB_t2SMULWT = 374, |
| t2SMUSD_t2SMUSDX = 375, |
| t2MLA_t2MLS_t2SMMLA_t2SMMLAR_t2SMMLS_t2SMMLSR = 376, |
| t2SMUAD_t2SMUADX = 377, |
| SMLSD_SMLSDX = 378, |
| t2SMLABB_t2SMLABT_t2SMLATB_t2SMLATT_t2SMLAWB_t2SMLAWT = 379, |
| t2SMLSD_t2SMLSDX = 380, |
| t2SMLAD_t2SMLADX = 381, |
| SMULL = 382, |
| t2SMULL_t2UMULL = 383, |
| t2SMLAL_t2SMLALBB_t2SMLALBT_t2SMLALD_t2SMLALDX_t2SMLALTB_t2SMLALTT_t2UMLAL_t2SMLSLD_t2SMLSLDX_t2UMAAL = 384, |
| SDIV_UDIV_t2SDIV_t2UDIV = 385, |
| LDRi12 = 386, |
| LDRBi12 = 387, |
| LDRBrs = 388, |
| t2LDRpci_pic = 389, |
| t2LDRi12_t2LDRi8_t2LDRpci_tLDRi_tLDRpci_tLDRspi = 390, |
| t2LDRs = 391, |
| t2LDRBi12_t2LDRBi8_t2LDRBpci_t2LDRHi12_t2LDRHi8_t2LDRHpci_tLDRBi_tLDRHi = 392, |
| t2LDRBs_t2LDRHs = 393, |
| LDREX_LDREXB_LDREXD_LDREXH_tLDRpci_pic = 394, |
| tLDRBr_tLDRHr = 395, |
| tLDRr = 396, |
| LDRH_PICLDRB_PICLDRH = 397, |
| LDRcp = 398, |
| t2LDRSBpcrel_t2LDRSHpcrel = 399, |
| t2LDRSBi12_t2LDRSBi8_t2LDRSBpci_t2LDRSHi12_t2LDRSHi8_t2LDRSHpci = 400, |
| t2LDRSBs_t2LDRSHs = 401, |
| tLDRSB_tLDRSH = 402, |
| LDRBT_POST_IMM_LDRBT_POST_REG_LDRB_POST_REG_LDRB_PRE_REG = 403, |
| LDRB_POST_IMM_LDRB_PRE_IMM = 404, |
| LDRT_POST_IMM_LDRT_POST_REG_LDR_POST_REG_LDR_PRE_REG = 405, |
| LDR_POST_IMM_LDR_PRE_IMM = 406, |
| LDRH_POST_LDRH_PRE_LDRHTi_LDRHTr = 407, |
| LDRHTii = 408, |
| t2LDR_POST_imm_t2LDR_PRE_imm = 409, |
| t2LDRB_POST_t2LDRB_PRE_t2LDRH_POST_t2LDRH_PRE = 410, |
| t2LDR_POST_t2LDR_PRE = 411, |
| t2LDRBT_t2LDRHT = 412, |
| t2LDRT = 413, |
| t2LDRSB_POST_t2LDRSB_PRE_t2LDRSH_POST_t2LDRSH_PRE = 414, |
| t2LDRSBT_t2LDRSHT = 415, |
| t2LDRDi8 = 416, |
| LDRD = 417, |
| LDRD_POST_LDRD_PRE = 418, |
| t2LDRD_POST_t2LDRD_PRE = 419, |
| LDMDA_LDMDB_LDMIA_LDMIB_t2LDMDB_t2LDMIA_sysLDMDA_sysLDMDB_sysLDMIA_sysLDMIB_tLDMIA = 420, |
| LDMDA_UPD_LDMDB_UPD_LDMIA_UPD_LDMIB_UPD_tLDMIA_UPD_sysLDMDA_UPD_sysLDMDB_UPD_sysLDMIA_UPD_sysLDMIB_UPD_t2LDMDB_UPD_t2LDMIA_UPD = 421, |
| LDMIA_RET_t2LDMIA_RET = 422, |
| tPOP_RET = 423, |
| tPOP = 424, |
| PICSTR_STRi12 = 425, |
| PICSTRB_PICSTRH_STRBi12_STRH = 426, |
| STRrs = 427, |
| STRBrs = 428, |
| STREX_STREXB_STREXD_STREXH = 429, |
| t2STRi12_t2STRi8_tSTRi_tSTRspi = 430, |
| t2STRs = 431, |
| t2STRBi12_t2STRBi8_t2STRHi12_t2STRHi8_tSTRBi_tSTRHi = 432, |
| t2STRBs_t2STRHs = 433, |
| tSTRBr_tSTRHr = 434, |
| tSTRr = 435, |
| STRBT_POST_IMM_STRBT_POST_REG_STRB_POST_REG_STRB_PRE_REG_STRH_POST_STRH_PRE_STRHTi_STRHTr = 436, |
| STRB_POST_IMM_STRB_PRE_IMM = 437, |
| STRT_POST_IMM_STRT_POST_REG_STR_POST_REG_STR_PRE_REG_STRi_preidx_STRr_preidx_STRBi_preidx_STRBr_preidx_STRH_preidx = 438, |
| STR_POST_IMM_STR_PRE_IMM = 439, |
| STRBT_POST_STRT_POST_t2STR_POST_imm_t2STR_PRE_imm = 440, |
| t2STR_POST_t2STR_PRE_t2STRH_PRE = 441, |
| t2STRB_POST_t2STRB_PRE_t2STRH_POST = 442, |
| t2STR_preidx_t2STRB_preidx_t2STRH_preidx = 443, |
| t2STRBT_t2STRHT = 444, |
| t2STRT = 445, |
| STRD = 446, |
| t2STRDi8 = 447, |
| t2STRD_POST_t2STRD_PRE = 448, |
| STRD_POST_STRD_PRE = 449, |
| STMDA_STMDB_STMIA_STMIB_sysSTMDA_sysSTMDB_sysSTMIA_sysSTMIB_t2STMDB_t2STMIA = 450, |
| STMDA_UPD_STMDB_UPD_STMIA_UPD_STMIB_UPD_sysSTMDA_UPD_sysSTMDB_UPD_sysSTMIA_UPD_sysSTMIB_UPD_t2STMDB_UPD_t2STMIA_UPD_tSTMIA_UPD = 451, |
| tPUSH = 452, |
| LDRLIT_ga_abs_tLDRLIT_ga_abs = 453, |
| LDRLIT_ga_pcrel_tLDRLIT_ga_pcrel = 454, |
| LDRLIT_ga_pcrel_ldr = 455, |
| t2IT = 456, |
| ITasm = 457, |
| VADDv16i8_VADDv2i64_VADDv4i32_VADDv8i16_VANDq_VBICq_VEORq_VORNq_VORRq_VBIFq_VBITq_VBSLq_VBSPq = 458, |
| VADDv1i64_VADDv2i32_VADDv4i16_VADDv8i8_VANDd_VBICd_VEORd_VORNd_VORRd_VBIFd_VBITd_VBSLd_VBSPd = 459, |
| VSUBv16i8_VSUBv2i64_VSUBv4i32_VSUBv8i16 = 460, |
| VSUBv1i64_VSUBv2i32_VSUBv4i16_VSUBv8i8_VADDWsv2i64_VADDWsv4i32_VADDWsv8i16_VADDWuv2i64_VADDWuv4i32_VADDWuv8i16_VSUBWsv2i64_VSUBWsv4i32_VSUBWsv8i16_VSUBWuv2i64_VSUBWuv4i32_VSUBWuv8i16 = 461, |
| VNEGf32q = 462, |
| VNEGfd = 463, |
| VNEGs16d_VNEGs32d_VNEGs8d_VADDLsv2i64_VADDLsv4i32_VADDLsv8i16_VADDLuv2i64_VADDLuv4i32_VADDLuv8i16_VSUBLsv2i64_VSUBLsv4i32_VSUBLsv8i16_VSUBLuv2i64_VSUBLuv4i32_VSUBLuv8i16_VPADDi16_VPADDi32_VPADDi8_VPADDLsv16i8_VPADDLsv2i32_VPADDLsv4i16_VPADDLsv4i32_VPADDLsv8i16_VPADDLsv8i8_VPADDLuv16i8_VPADDLuv2i32_VPADDLuv4i16_VPADDLuv4i32_VPADDLuv8i16_VPADDLuv8i8_VSHLLi16_VSHLLi32_VSHLLi8_VSHLLsv2i64_VSHLLsv4i32_VSHLLsv8i16_VSHLLuv2i64_VSHLLuv4i32_VSHLLuv8i16_VSHLiv16i8_VSHLiv1i64_VSHLiv2i32_VSHLiv2i64_VSHLiv4i16_VSHLiv4i32_VSHLiv8i16_VSHLiv8i8_VSHLsv1i64_VSHLsv2i32_VSHLsv4i16_VSHLsv8i8_VSHLuv1i64_VSHLuv2i32_VSHLuv4i16_VSHLuv8i8_VSHRsv16i8_VSHRsv1i64_VSHRsv2i32_VSHRsv2i64_VSHRsv4i16_VSHRsv4i32_VSHRsv8i16_VSHRsv8i8_VSHRuv16i8_VSHRuv1i64_VSHRuv2i32_VSHRuv2i64_VSHRuv4i16_VSHRuv4i32_VSHRuv8i16_VSHRuv8i8_VSLIv1i64_VSLIv2i32_VSLIv4i16_VSLIv8i8_VSRIv1i64_VSRIv2i32_VSRIv4i16_VSRIv8i8 = 464, |
| VNEGs16q_VNEGs32q_VNEGs8q_VSHLsv16i8_VSHLsv2i64_VSHLsv4i32_VSHLsv8i16_VSHLuv16i8_VSHLuv2i64_VSHLuv4i32_VSHLuv8i16_VSLIv16i8_VSLIv2i64_VSLIv4i32_VSLIv8i16_VSRIv16i8_VSRIv2i64_VSRIv4i32_VSRIv8i16 = 465, |
| VHADDsv16i8_VHADDsv4i32_VHADDsv8i16_VHADDuv16i8_VHADDuv4i32_VHADDuv8i16_VRHADDsv16i8_VRHADDsv4i32_VRHADDsv8i16_VRHADDuv16i8_VRHADDuv4i32_VRHADDuv8i16_VTSTv16i8_VTSTv4i32_VTSTv8i16 = 466, |
| VHADDsv2i32_VHADDsv4i16_VHADDsv8i8_VHADDuv2i32_VHADDuv4i16_VHADDuv8i8_VRHADDsv2i32_VRHADDsv4i16_VRHADDsv8i8_VRHADDuv2i32_VRHADDuv4i16_VRHADDuv8i8_VTSTv2i32_VTSTv4i16_VTSTv8i8 = 467, |
| VHSUBsv16i8_VHSUBsv4i32_VHSUBsv8i16_VHSUBuv16i8_VHSUBuv4i32_VHSUBuv8i16 = 468, |
| VHSUBsv2i32_VHSUBsv4i16_VHSUBsv8i8_VHSUBuv2i32_VHSUBuv4i16_VHSUBuv8i8 = 469, |
| VBICiv2i32_VBICiv4i16_VBICiv4i32_VBICiv8i16_VORRiv2i32_VORRiv4i16_VORRiv4i32_VORRiv8i16 = 470, |
| VQSHLsiv16i8_VQSHLsiv1i64_VQSHLsiv2i32_VQSHLsiv2i64_VQSHLsiv4i16_VQSHLsiv4i32_VQSHLsiv8i16_VQSHLsiv8i8_VQSHLsuv16i8_VQSHLsuv1i64_VQSHLsuv2i32_VQSHLsuv2i64_VQSHLsuv4i16_VQSHLsuv4i32_VQSHLsuv8i16_VQSHLsuv8i8_VQSHLsv1i64_VQSHLsv2i32_VQSHLsv4i16_VQSHLsv8i8_VQSHLuiv16i8_VQSHLuiv1i64_VQSHLuiv2i32_VQSHLuiv2i64_VQSHLuiv4i16_VQSHLuiv4i32_VQSHLuiv8i16_VQSHLuiv8i8_VQSHLuv1i64_VQSHLuv2i32_VQSHLuv4i16_VQSHLuv8i8 = 471, |
| VQSHLsv16i8_VQSHLsv2i64_VQSHLsv4i32_VQSHLsv8i16_VQSHLuv16i8_VQSHLuv2i64_VQSHLuv4i32_VQSHLuv8i16 = 472, |
| VCLSv16i8_VCLSv4i32_VCLSv8i16_VCLZv16i8_VCLZv4i32_VCLZv8i16_VCNTq = 473, |
| VCLSv2i32_VCLSv4i16_VCLSv8i8_VCLZv2i32_VCLZv4i16_VCLZv8i8_VCNTd = 474, |
| VEXTd16_VEXTd32_VEXTd8 = 475, |
| VEXTq16_VEXTq32_VEXTq64_VEXTq8 = 476, |
| VREV16d8_VREV32d16_VREV32d8_VREV64d16_VREV64d32_VREV64d8 = 477, |
| VREV16q8_VREV32q16_VREV32q8_VREV64q16_VREV64q32_VREV64q8 = 478, |
| VABALsv2i64_VABALsv4i32_VABALsv8i16_VABALuv2i64_VABALuv4i32_VABALuv8i16_VABAsv2i32_VABAsv4i16_VABAsv8i8_VABAuv2i32_VABAuv4i16_VABAuv8i8 = 479, |
| VABAsv16i8_VABAsv4i32_VABAsv8i16_VABAuv16i8_VABAuv4i32_VABAuv8i16 = 480, |
| VPADALsv16i8_VPADALsv4i32_VPADALsv8i16_VPADALuv16i8_VPADALuv4i32_VPADALuv8i16 = 481, |
| VPADALsv2i32_VPADALsv4i16_VPADALsv8i8_VPADALuv2i32_VPADALuv4i16_VPADALuv8i8_VRSRAsv16i8_VRSRAsv1i64_VRSRAsv2i32_VRSRAsv2i64_VRSRAsv4i16_VRSRAsv4i32_VRSRAsv8i16_VRSRAsv8i8_VRSRAuv16i8_VRSRAuv1i64_VRSRAuv2i32_VRSRAuv2i64_VRSRAuv4i16_VRSRAuv4i32_VRSRAuv8i16_VRSRAuv8i8_VSRAsv16i8_VSRAsv1i64_VSRAsv2i32_VSRAsv2i64_VSRAsv4i16_VSRAsv4i32_VSRAsv8i16_VSRAsv8i8_VSRAuv16i8_VSRAuv1i64_VSRAuv2i32_VSRAuv2i64_VSRAuv4i16_VSRAuv4i32_VSRAuv8i16_VSRAuv8i8 = 482, |
| VACGEfd_VACGEhd_VACGTfd_VACGThd_VCEQfd_VCEQhd_VCGEfd_VCGEhd_VCGTfd_VCGThd = 483, |
| VACGEfq_VACGEhq_VACGTfq_VACGThq_VCEQfq_VCEQhq_VCGEfq_VCGEhq_VCGTfq_VCGThq = 484, |
| VCEQv16i8_VCEQv4i32_VCEQv8i16_VCGEsv16i8_VCGEsv4i32_VCGEsv8i16_VCGEuv16i8_VCGEuv4i32_VCGEuv8i16_VCGTsv16i8_VCGTsv4i32_VCGTsv8i16_VCGTuv16i8_VCGTuv4i32_VCGTuv8i16_VQSUBsv16i8_VQSUBsv2i64_VQSUBsv4i32_VQSUBsv8i16_VQSUBuv16i8_VQSUBuv2i64_VQSUBuv4i32_VQSUBuv8i16 = 485, |
| VCEQv2i32_VCEQv4i16_VCEQv8i8_VCGEsv2i32_VCGEsv4i16_VCGEsv8i8_VCGEuv2i32_VCGEuv4i16_VCGEuv8i8_VCGTsv2i32_VCGTsv4i16_VCGTsv8i8_VCGTuv2i32_VCGTuv4i16_VCGTuv8i8_VQSUBsv1i64_VQSUBsv2i32_VQSUBsv4i16_VQSUBsv8i8_VQSUBuv1i64_VQSUBuv2i32_VQSUBuv4i16_VQSUBuv8i8 = 486, |
| VCEQzv16i8_VCEQzv2f32_VCEQzv2i32_VCEQzv4f16_VCEQzv4f32_VCEQzv4i16_VCEQzv4i32_VCEQzv8f16_VCEQzv8i16_VCEQzv8i8_VCGEzv16i8_VCGEzv2f32_VCGEzv2i32_VCGEzv4f16_VCGEzv4f32_VCGEzv4i16_VCGEzv4i32_VCGEzv8f16_VCGEzv8i16_VCGEzv8i8_VCGTzv16i8_VCGTzv2f32_VCGTzv2i32_VCGTzv4f16_VCGTzv4f32_VCGTzv4i16_VCGTzv4i32_VCGTzv8f16_VCGTzv8i16_VCGTzv8i8_VCLEzv16i8_VCLEzv2f32_VCLEzv2i32_VCLEzv4f16_VCLEzv4f32_VCLEzv4i16_VCLEzv4i32_VCLEzv8f16_VCLEzv8i16_VCLEzv8i8_VCLTzv16i8_VCLTzv2f32_VCLTzv2i32_VCLTzv4f16_VCLTzv4f32_VCLTzv4i16_VCLTzv4i32_VCLTzv8f16_VCLTzv8i16_VCLTzv8i8 = 487, |
| VRSHLsv16i8_VRSHLsv2i64_VRSHLsv4i32_VRSHLsv8i16_VRSHLuv16i8_VRSHLuv2i64_VRSHLuv4i32_VRSHLuv8i16_VQRSHLsv16i8_VQRSHLsv2i64_VQRSHLsv4i32_VQRSHLsv8i16_VQRSHLuv16i8_VQRSHLuv2i64_VQRSHLuv4i32_VQRSHLuv8i16 = 488, |
| VRSHLsv1i64_VRSHLsv2i32_VRSHLsv4i16_VRSHLsv8i8_VRSHLuv1i64_VRSHLuv2i32_VRSHLuv4i16_VRSHLuv8i8_VQRSHLsv1i64_VQRSHLsv2i32_VQRSHLsv4i16_VQRSHLsv8i8_VQRSHLuv1i64_VQRSHLuv2i32_VQRSHLuv4i16_VQRSHLuv8i8_VRSHRsv16i8_VRSHRsv1i64_VRSHRsv2i32_VRSHRsv2i64_VRSHRsv4i16_VRSHRsv4i32_VRSHRsv8i16_VRSHRsv8i8_VRSHRuv16i8_VRSHRuv1i64_VRSHRuv2i32_VRSHRuv2i64_VRSHRuv4i16_VRSHRuv4i32_VRSHRuv8i16_VRSHRuv8i8 = 489, |
| VABSfd = 490, |
| VABSfq = 491, |
| VABSv16i8_VABSv4i32_VABSv8i16 = 492, |
| VABSv2i32_VABSv4i16_VABSv8i8 = 493, |
| VQABSv16i8_VQABSv4i32_VQABSv8i16_VQNEGv16i8_VQNEGv4i32_VQNEGv8i16 = 494, |
| VQABSv2i32_VQABSv4i16_VQABSv8i8_VQNEGv2i32_VQNEGv4i16_VQNEGv8i8 = 495, |
| VQADDsv16i8_VQADDsv2i64_VQADDsv4i32_VQADDsv8i16_VQADDuv16i8_VQADDuv2i64_VQADDuv4i32_VQADDuv8i16 = 496, |
| VQADDsv1i64_VQADDsv2i32_VQADDsv4i16_VQADDsv8i8_VQADDuv1i64_VQADDuv2i32_VQADDuv4i16_VQADDuv8i8 = 497, |
| VRECPEd_VRECPEfd_VRECPEhd_VRSQRTEd_VRSQRTEfd_VRSQRTEhd = 498, |
| VRECPEfq_VRECPEhq_VRECPEq_VRSQRTEfq_VRSQRTEhq_VRSQRTEq = 499, |
| VADDHNv2i32_VADDHNv4i16_VADDHNv8i8_VSUBHNv2i32_VSUBHNv4i16_VSUBHNv8i8 = 500, |
| VSHRNv2i32_VSHRNv4i16_VSHRNv8i8 = 501, |
| VRADDHNv2i32_VRADDHNv4i16_VRADDHNv8i8_VRSUBHNv2i32_VRSUBHNv4i16_VRSUBHNv8i8 = 502, |
| VRSHRNv2i32_VRSHRNv4i16_VRSHRNv8i8_VQSHRNsv2i32_VQSHRNsv4i16_VQSHRNsv8i8_VQSHRNuv2i32_VQSHRNuv4i16_VQSHRNuv8i8_VQSHRUNv2i32_VQSHRUNv4i16_VQSHRUNv8i8_VQRSHRNsv2i32_VQRSHRNsv4i16_VQRSHRNsv8i8_VQRSHRNuv2i32_VQRSHRNuv4i16_VQRSHRNuv8i8_VQRSHRUNv2i32_VQRSHRUNv4i16_VQRSHRUNv8i8 = 503, |
| VTBL1 = 504, |
| VTBX1 = 505, |
| VTBL2 = 506, |
| VTBX2 = 507, |
| VTBL3_VTBL3Pseudo = 508, |
| VTBX3_VTBX3Pseudo = 509, |
| VTBL4_VTBL4Pseudo = 510, |
| VTBX4_VTBX4Pseudo = 511, |
| VSWPd_VSWPq = 512, |
| VTRNd16_VTRNd32_VTRNd8_VUZPd16_VUZPd8_VZIPd16_VZIPd8 = 513, |
| VTRNq16_VTRNq32_VTRNq8 = 514, |
| VUZPq16_VUZPq32_VUZPq8_VZIPq16_VZIPq32_VZIPq8 = 515, |
| VABSD_VNEGD = 516, |
| VABSS_VNEGS = 517, |
| VCMPD_VCMPZD_VCMPED_VCMPEZD = 518, |
| VCMPS_VCMPZS_VCMPES_VCMPEZS = 519, |
| VADDS_VSUBS = 520, |
| VADDfd_VSUBfd_VABDfd_VABDhd_VMAXfd_VMAXhd_VMINfd_VMINhd = 521, |
| VADDfq_VSUBfq_VABDfq_VABDhq_VMAXfq_VMAXhq_VMINfq_VMINhq = 522, |
| VABDLsv2i64_VABDLsv4i32_VABDLsv8i16_VABDLuv2i64_VABDLuv4i32_VABDLuv8i16_VABDsv16i8_VABDsv4i32_VABDsv8i16_VABDuv16i8_VABDuv4i32_VABDuv8i16_VMAXsv16i8_VMAXsv4i32_VMAXsv8i16_VMAXuv16i8_VMAXuv4i32_VMAXuv8i16_VMINsv16i8_VMINsv4i32_VMINsv8i16_VMINuv16i8_VMINuv4i32_VMINuv8i16 = 523, |
| VABDsv2i32_VABDsv4i16_VABDsv8i8_VABDuv2i32_VABDuv4i16_VABDuv8i8_VMAXsv2i32_VMAXsv4i16_VMAXsv8i8_VMAXuv2i32_VMAXuv4i16_VMAXuv8i8_VMINsv2i32_VMINsv4i16_VMINsv8i8_VMINuv2i32_VMINuv4i16_VMINuv8i8_VPMAXs16_VPMAXs32_VPMAXs8_VPMAXu16_VPMAXu32_VPMAXu8_VPMINs16_VPMINs32_VPMINs8_VPMINu16_VPMINu32_VPMINu8 = 524, |
| VPADDf_VPMAXf_VPMAXh_VPMINf_VPMINh = 525, |
| VADDD_VSUBD = 526, |
| VRECPSfd_VRECPShd_VRSQRTSfd_VRSQRTShd = 527, |
| VRECPSfq_VRECPShq_VRSQRTSfq_VRSQRTShq = 528, |
| VMULS_VNMULS = 529, |
| VMULfd = 530, |
| VMULfq = 531, |
| VMULpd_VMULslhd_VMULslv4i16_VMULv4i16_VMULv8i8_VQDMULHslv4i16_VQDMULHv4i16_VQRDMULHslv4i16_VQRDMULHv4i16_VMULLp8_VMULLslsv2i32_VMULLslsv4i16_VMULLsluv2i32_VMULLsluv4i16_VMULLsv4i32_VMULLsv8i16_VMULLuv4i32_VMULLuv8i16_VQDMULLslv2i32_VQDMULLslv4i16_VQDMULLv4i32 = 532, |
| VMULpq_VMULslhq_VMULslv8i16_VMULv16i8_VMULv8i16_VQDMULHslv8i16_VQDMULHv8i16_VQRDMULHslv8i16_VQRDMULHv8i16 = 533, |
| VMULslfd = 534, |
| VMULslfq = 535, |
| VMULslv2i32_VMULv2i32_VQDMULHslv2i32_VQDMULHv2i32_VQRDMULHslv2i32_VQRDMULHv2i32_VMULLsv2i64_VMULLuv2i64_VQDMULLv2i64 = 536, |
| VMULslv4i32_VMULv4i32_VQDMULHslv4i32_VQDMULHv4i32_VQRDMULHslv4i32_VQRDMULHv4i32 = 537, |
| VMULLp64 = 538, |
| VMLAD_VMLSD_VNMLAD_VNMLSD = 539, |
| VMLAH_VMLSH_VNMLAH_VNMLSH = 540, |
| VMLALslsv2i32_VMLALsluv2i32_VMLALsv2i64_VMLALuv2i64_VMLAslv2i32_VMLAv2i32_VMLSLslsv2i32_VMLSLsluv2i32_VMLSLsv2i64_VMLSLuv2i64_VMLSslv2i32_VMLSv2i32_VQDMLALslv2i32_VQDMLALv2i64_VQDMLSLslv2i32_VQDMLSLv2i64 = 541, |
| VMLALslsv4i16_VMLALsluv4i16_VMLALsv4i32_VMLALsv8i16_VMLALuv4i32_VMLALuv8i16_VMLAslv4i16_VMLAv4i16_VMLAv8i8_VMLSLslsv4i16_VMLSLsluv4i16_VMLSLsv4i32_VMLSLsv8i16_VMLSLuv4i32_VMLSLuv8i16_VMLSslv4i16_VMLSv4i16_VMLSv8i8_VQDMLALslv4i16_VQDMLALv4i32_VQDMLSLslv4i16_VQDMLSLv4i32 = 542, |
| VMLAS_VMLSS_VNMLAS_VNMLSS = 543, |
| VMLAfd_VMLAhd_VMLAslfd_VMLAslhd_VMLSfd_VMLShd_VMLSslfd_VMLSslhd = 544, |
| VMLAfq_VMLAhq_VMLAslfq_VMLAslhq_VMLSfq_VMLShq_VMLSslfq_VMLSslhq = 545, |
| VMLAslv4i32_VMLAv4i32_VMLSslv4i32_VMLSv4i32 = 546, |
| VMLAslv8i16_VMLAv16i8_VMLAv8i16_VMLSslv8i16_VMLSv16i8_VMLSv8i16 = 547, |
| VFMAD_VFMSD_VFNMAD_VFNMSD = 548, |
| VFMAS_VFMSS_VFNMAS_VFNMSS = 549, |
| VFNMAH_VFNMSH = 550, |
| VFMAfd_VFMSfd = 551, |
| VFMAfq_VFMSfq = 552, |
| VCVTANSDf_VCVTANSDh_VCVTANSQf_VCVTANSQh_VCVTANUDf_VCVTANUDh_VCVTANUQf_VCVTANUQh_VCVTASD_VCVTASH_VCVTASS_VCVTAUD_VCVTAUH_VCVTAUS_VCVTBDH_VCVTMNSDf_VCVTMNSDh_VCVTMNSQf_VCVTMNSQh_VCVTMNUDf_VCVTMNUDh_VCVTMNUQf_VCVTMNUQh_VCVTMSD_VCVTMSH_VCVTMSS_VCVTMUD_VCVTMUH_VCVTMUS_VCVTNNSDf_VCVTNNSDh_VCVTNNSQf_VCVTNNSQh_VCVTNNUDf_VCVTNNUDh_VCVTNNUQf_VCVTNNUQh_VCVTNSD_VCVTNSH_VCVTNSS_VCVTNUD_VCVTNUH_VCVTNUS_VCVTPNSDf_VCVTPNSDh_VCVTPNSQf_VCVTPNSQh_VCVTPNUDf_VCVTPNUDh_VCVTPNUQf_VCVTPNUQh_VCVTPSD_VCVTPSH_VCVTPSS_VCVTPUD_VCVTPUH_VCVTPUS_VCVTTDH_VCVTTHD = 553, |
| VCVTBHD = 554, |
| VCVTBHS_VCVTTHS = 555, |
| VCVTBSH_VCVTTSH = 556, |
| VCVTDS = 557, |
| VCVTSD = 558, |
| VCVTf2h_VCVTf2sq_VCVTf2uq_VCVTf2xsq_VCVTf2xuq_VCVTh2f_VCVTh2sq_VCVTh2uq_VCVTh2xsq_VCVTh2xuq_VCVTs2fq_VCVTs2hq_VCVTu2fq_VCVTu2hq_VCVTxs2fq_VCVTxs2hq_VCVTxu2fq_VCVTxu2hq = 559, |
| VCVTf2sd_VCVTf2ud_VCVTf2xsd_VCVTf2xud_VCVTh2sd_VCVTh2ud_VCVTh2xsd_VCVTh2xud_VCVTs2fd_VCVTs2hd_VCVTu2fd_VCVTu2hd_VCVTxs2fd_VCVTxs2hd_VCVTxu2fd_VCVTxu2hd = 560, |
| VSITOD_VUITOD = 561, |
| VSITOH_VUITOH = 562, |
| VSITOS_VUITOS = 563, |
| VTOSHD_VTOSIRD_VTOSIZD_VTOSLD_VTOUHD_VTOUIRD_VTOUIZD_VTOULD = 564, |
| VTOSHH_VTOSIRH_VTOSIZH_VTOSLH_VTOUHH_VTOUIRH_VTOUIZH_VTOULH = 565, |
| VTOSHS_VTOSIRS_VTOSIZS_VTOSLS_VTOUHS_VTOUIRS_VTOUIZS_VTOULS = 566, |
| VMOVv16i8_VMOVv1i64_VMOVv2f32_VMOVv2i32_VMOVv2i64_VMOVv4f32_VMOVv4i16_VMOVv4i32_VMOVv8i16_VMOVv8i8_VMVNv2i32_VMVNv4i16_VMVNv4i32_VMVNv8i16 = 567, |
| VMOVD_VMOVDcc_FCONSTD = 568, |
| VMOVS_VMOVScc_FCONSTS = 569, |
| VMVNd_VMVNq = 570, |
| VMOVNv2i32_VMOVNv4i16_VMOVNv8i8 = 571, |
| VMOVLsv2i64_VMOVLsv4i32_VMOVLsv8i16_VMOVLuv2i64_VMOVLuv4i32_VMOVLuv8i16 = 572, |
| VQMOVNsuv2i32_VQMOVNsuv4i16_VQMOVNsuv8i8_VQMOVNsv2i32_VQMOVNsv4i16_VQMOVNsv8i8_VQMOVNuv2i32_VQMOVNuv4i16_VQMOVNuv8i8 = 573, |
| VDUPLN16d_VDUPLN32d_VDUPLN8d = 574, |
| VDUPLN16q_VDUPLN32q_VDUPLN8q = 575, |
| VDUP16d_VDUP16q_VDUP32d_VDUP32q_VDUP8d_VDUP8q = 576, |
| VMOVRS = 577, |
| VMOVSR = 578, |
| VSETLNi16_VSETLNi32_VSETLNi8 = 579, |
| VMOVRRD_VMOVRRS = 580, |
| VMOVDRR = 581, |
| VMOVSRR = 582, |
| VGETLNi32_VGETLNu16_VGETLNu8 = 583, |
| VGETLNs16_VGETLNs8 = 584, |
| VMRS_VMRS_FPCXTNS_VMRS_FPCXTS_VMRS_FPEXC_VMRS_FPINST_VMRS_FPINST2_VMRS_FPSCR_NZCVQC_VMRS_FPSID_VMRS_MVFR0_VMRS_MVFR1_VMRS_MVFR2_VMRS_P0_VMRS_VPR = 585, |
| VMSR_VMSR_FPCXTNS_VMSR_FPCXTS_VMSR_FPEXC_VMSR_FPINST_VMSR_FPINST2_VMSR_FPSCR_NZCVQC_VMSR_FPSID_VMSR_P0_VMSR_VPR = 586, |
| FMSTAT = 587, |
| VLDRD = 588, |
| VLDRS = 589, |
| VSTRD = 590, |
| VSTRS = 591, |
| VLDMQIA = 592, |
| VSTMQIA = 593, |
| VLDMDIA_VLDMSIA = 594, |
| VLDMDDB_UPD_VLDMDIA_UPD_VLDMSDB_UPD_VLDMSIA_UPD = 595, |
| VSTMDIA_VSTMSIA = 596, |
| VSTMDDB_UPD_VSTMDIA_UPD_VSTMSDB_UPD_VSTMSIA_UPD = 597, |
| VLD1d16_VLD1d32_VLD1d64_VLD1d8 = 598, |
| VLD1q16_VLD1q32_VLD1q64_VLD1q8 = 599, |
| VLD1d16wb_fixed_VLD1d16wb_register_VLD1d32wb_fixed_VLD1d32wb_register_VLD1d64wb_fixed_VLD1d64wb_register_VLD1d8wb_fixed_VLD1d8wb_register = 600, |
| VLD1q16wb_fixed_VLD1q16wb_register_VLD1q32wb_fixed_VLD1q32wb_register_VLD1q64wb_fixed_VLD1q64wb_register_VLD1q8wb_fixed_VLD1q8wb_register = 601, |
| VLD1d16T_VLD1d32T_VLD1d64T_VLD1d8T_VLD1d64TPseudo_VLD1d64TPseudoWB_fixed_VLD1d64TPseudoWB_register = 602, |
| VLD1d16Twb_fixed_VLD1d16Twb_register_VLD1d32Twb_fixed_VLD1d32Twb_register_VLD1d64Twb_fixed_VLD1d64Twb_register_VLD1d8Twb_fixed_VLD1d8Twb_register = 603, |
| VLD1d16Q_VLD1d32Q_VLD1d64Q_VLD1d8Q_VLD1d64QPseudo_VLD1d64QPseudoWB_fixed_VLD1d64QPseudoWB_register = 604, |
| VLD1d16Qwb_fixed_VLD1d16Qwb_register_VLD1d32Qwb_fixed_VLD1d32Qwb_register_VLD1d64Qwb_fixed_VLD1d64Qwb_register_VLD1d8Qwb_fixed_VLD1d8Qwb_register = 605, |
| VLD2b16_VLD2b32_VLD2b8_VLD2d16_VLD2d32_VLD2d8 = 606, |
| VLD2q16_VLD2q32_VLD2q8_VLD2q16Pseudo_VLD2q32Pseudo_VLD2q8Pseudo = 607, |
| VLD2b16wb_fixed_VLD2b16wb_register_VLD2b32wb_fixed_VLD2b32wb_register_VLD2b8wb_fixed_VLD2b8wb_register_VLD2d16wb_fixed_VLD2d16wb_register_VLD2d32wb_fixed_VLD2d32wb_register_VLD2d8wb_fixed_VLD2d8wb_register = 608, |
| VLD2q16wb_fixed_VLD2q16wb_register_VLD2q32wb_fixed_VLD2q32wb_register_VLD2q8wb_fixed_VLD2q8wb_register_VLD2q16PseudoWB_fixed_VLD2q16PseudoWB_register_VLD2q32PseudoWB_fixed_VLD2q32PseudoWB_register_VLD2q8PseudoWB_fixed_VLD2q8PseudoWB_register = 609, |
| VLD3d16_VLD3d32_VLD3d8_VLD3q16_VLD3q32_VLD3q8 = 610, |
| VLD3d16Pseudo_VLD3d32Pseudo_VLD3d8Pseudo_VLD3q16oddPseudo_VLD3q32oddPseudo_VLD3q8oddPseudo = 611, |
| VLD3d16_UPD_VLD3d32_UPD_VLD3d8_UPD_VLD3q16_UPD_VLD3q32_UPD_VLD3q8_UPD = 612, |
| VLD3d16Pseudo_UPD_VLD3d32Pseudo_UPD_VLD3d8Pseudo_UPD_VLD3q16Pseudo_UPD_VLD3q16oddPseudo_UPD_VLD3q32Pseudo_UPD_VLD3q32oddPseudo_UPD_VLD3q8Pseudo_UPD_VLD3q8oddPseudo_UPD = 613, |
| VLD4d16_VLD4d32_VLD4d8_VLD4q16_VLD4q32_VLD4q8 = 614, |
| VLD4d16Pseudo_VLD4d32Pseudo_VLD4d8Pseudo_VLD4q16oddPseudo_VLD4q32oddPseudo_VLD4q8oddPseudo = 615, |
| VLD4d16_UPD_VLD4d32_UPD_VLD4d8_UPD_VLD4q16_UPD_VLD4q32_UPD_VLD4q8_UPD = 616, |
| VLD4d16Pseudo_UPD_VLD4d32Pseudo_UPD_VLD4d8Pseudo_UPD_VLD4q16Pseudo_UPD_VLD4q16oddPseudo_UPD_VLD4q32Pseudo_UPD_VLD4q32oddPseudo_UPD_VLD4q8Pseudo_UPD_VLD4q8oddPseudo_UPD = 617, |
| VLD1DUPd16_VLD1DUPd32_VLD1DUPd8 = 618, |
| VLD1DUPq16_VLD1DUPq32_VLD1DUPq8 = 619, |
| VLD1LNd16_VLD1LNd8 = 620, |
| VLD1LNd32_VLD1LNq16Pseudo_VLD1LNq32Pseudo_VLD1LNq8Pseudo = 621, |
| VLD1DUPd16wb_fixed_VLD1DUPd16wb_register_VLD1DUPd32wb_fixed_VLD1DUPd32wb_register_VLD1DUPd8wb_fixed_VLD1DUPd8wb_register_VLD1DUPq16wb_register_VLD1DUPq32wb_register_VLD1DUPq8wb_register = 622, |
| VLD1DUPq16wb_fixed_VLD1DUPq32wb_fixed_VLD1DUPq8wb_fixed = 623, |
| VLD1LNd16_UPD_VLD1LNd32_UPD_VLD1LNd8_UPD_VLD1LNq16Pseudo_UPD_VLD1LNq32Pseudo_UPD_VLD1LNq8Pseudo_UPD = 624, |
| VLD2DUPd16_VLD2DUPd16x2_VLD2DUPd32_VLD2DUPd32x2_VLD2DUPd8_VLD2DUPd8x2 = 625, |
| VLD2LNd16_VLD2LNd32_VLD2LNd8_VLD2LNq16_VLD2LNq32_VLD2LNd16Pseudo_VLD2LNd32Pseudo_VLD2LNd8Pseudo_VLD2LNq16Pseudo_VLD2LNq32Pseudo = 626, |
| VLD2LNd16_UPD_VLD2LNd32_UPD_VLD2LNd8_UPD_VLD2LNq16_UPD_VLD2LNq32_UPD = 627, |
| VLD2DUPd16wb_fixed_VLD2DUPd16wb_register_VLD2DUPd16x2wb_fixed_VLD2DUPd16x2wb_register_VLD2DUPd32wb_fixed_VLD2DUPd32wb_register_VLD2DUPd32x2wb_fixed_VLD2DUPd32x2wb_register_VLD2DUPd8wb_fixed_VLD2DUPd8wb_register_VLD2DUPd8x2wb_fixed_VLD2DUPd8x2wb_register = 628, |
| VLD2LNd16Pseudo_UPD_VLD2LNd32Pseudo_UPD_VLD2LNd8Pseudo_UPD_VLD2LNq16Pseudo_UPD_VLD2LNq32Pseudo_UPD = 629, |
| VLD3DUPd16_VLD3DUPd32_VLD3DUPd8_VLD3DUPq16_VLD3DUPq32_VLD3DUPq8_VLD3DUPd16Pseudo_VLD3DUPd32Pseudo_VLD3DUPd8Pseudo = 630, |
| VLD3LNd16_VLD3LNd32_VLD3LNd8_VLD3LNq16_VLD3LNq32_VLD3LNd16Pseudo_VLD3LNd32Pseudo_VLD3LNd8Pseudo_VLD3LNq16Pseudo_VLD3LNq32Pseudo = 631, |
| VLD3DUPd16_UPD_VLD3DUPd32_UPD_VLD3DUPd8_UPD_VLD3DUPq16_UPD_VLD3DUPq32_UPD_VLD3DUPq8_UPD = 632, |
| VLD3LNd16_UPD_VLD3LNd32_UPD_VLD3LNd8_UPD_VLD3LNq16_UPD_VLD3LNq32_UPD = 633, |
| VLD3DUPd16Pseudo_UPD_VLD3DUPd32Pseudo_UPD_VLD3DUPd8Pseudo_UPD = 634, |
| VLD3LNd16Pseudo_UPD_VLD3LNd32Pseudo_UPD_VLD3LNd8Pseudo_UPD_VLD3LNq16Pseudo_UPD_VLD3LNq32Pseudo_UPD = 635, |
| VLD4DUPd16_VLD4DUPd32_VLD4DUPd8_VLD4DUPq16_VLD4DUPq32_VLD4DUPq8 = 636, |
| VLD4LNd16_VLD4LNd32_VLD4LNd8_VLD4LNq16_VLD4LNq32_VLD4LNd16Pseudo_VLD4LNd32Pseudo_VLD4LNd8Pseudo_VLD4LNq16Pseudo_VLD4LNq32Pseudo = 637, |
| VLD4DUPd16Pseudo_VLD4DUPd32Pseudo_VLD4DUPd8Pseudo = 638, |
| VLD4DUPd16_UPD_VLD4DUPd32_UPD_VLD4DUPd8_UPD_VLD4DUPq16_UPD_VLD4DUPq32_UPD_VLD4DUPq8_UPD = 639, |
| VLD4LNd16_UPD_VLD4LNd32_UPD_VLD4LNd8_UPD_VLD4LNq16_UPD_VLD4LNq32_UPD = 640, |
| VLD4DUPd16Pseudo_UPD_VLD4DUPd32Pseudo_UPD_VLD4DUPd8Pseudo_UPD = 641, |
| VLD4LNd16Pseudo_UPD_VLD4LNd32Pseudo_UPD_VLD4LNd8Pseudo_UPD_VLD4LNq16Pseudo_UPD_VLD4LNq32Pseudo_UPD = 642, |
| VST1d16_VST1d32_VST1d64_VST1d8 = 643, |
| VST1q16_VST1q32_VST1q64_VST1q8 = 644, |
| VST1d16wb_fixed_VST1d16wb_register_VST1d32wb_fixed_VST1d32wb_register_VST1d64wb_fixed_VST1d64wb_register_VST1d8wb_fixed_VST1d8wb_register = 645, |
| VST1q16wb_fixed_VST1q16wb_register_VST1q32wb_fixed_VST1q32wb_register_VST1q64wb_fixed_VST1q64wb_register_VST1q8wb_fixed_VST1q8wb_register = 646, |
| VST1d16T_VST1d32T_VST1d64T_VST1d8T_VST1d64TPseudo = 647, |
| VST1d16Twb_fixed_VST1d16Twb_register_VST1d32Twb_fixed_VST1d32Twb_register_VST1d64Twb_fixed_VST1d64Twb_register_VST1d8Twb_fixed_VST1d8Twb_register = 648, |
| VST1d64TPseudoWB_fixed_VST1d64TPseudoWB_register = 649, |
| VST1d16Q_VST1d16QPseudo_VST1d32Q_VST1d32QPseudo_VST1d64Q_VST1d64QPseudo_VST1d8Q_VST1d8QPseudo = 650, |
| VST1d16QPseudoWB_fixed_VST1d16QPseudoWB_register_VST1d32QPseudoWB_fixed_VST1d32QPseudoWB_register_VST1d64QPseudoWB_fixed_VST1d64QPseudoWB_register_VST1d8QPseudoWB_fixed_VST1d8QPseudoWB_register = 651, |
| VST1d16Qwb_fixed_VST1d16Qwb_register_VST1d32Qwb_fixed_VST1d32Qwb_register_VST1d64Qwb_fixed_VST1d64Qwb_register_VST1d8Qwb_fixed_VST1d8Qwb_register = 652, |
| VST2b16_VST2b32_VST2b8 = 653, |
| VST2d16_VST2d32_VST2d8 = 654, |
| VST2b16wb_fixed_VST2b16wb_register_VST2b32wb_fixed_VST2b32wb_register_VST2b8wb_fixed_VST2b8wb_register_VST2d16wb_fixed_VST2d16wb_register_VST2d32wb_fixed_VST2d32wb_register_VST2d8wb_fixed_VST2d8wb_register = 655, |
| VST2q16_VST2q32_VST2q8_VST2q16Pseudo_VST2q32Pseudo_VST2q8Pseudo = 656, |
| VST2q16wb_fixed_VST2q16wb_register_VST2q32wb_fixed_VST2q32wb_register_VST2q8wb_fixed_VST2q8wb_register = 657, |
| VST2q16PseudoWB_fixed_VST2q16PseudoWB_register_VST2q32PseudoWB_fixed_VST2q32PseudoWB_register_VST2q8PseudoWB_fixed_VST2q8PseudoWB_register = 658, |
| VST3d16_VST3d32_VST3d8_VST3q16_VST3q32_VST3q8_VST3d16Pseudo_VST3d32Pseudo_VST3d8Pseudo_VST3q16oddPseudo_VST3q32oddPseudo_VST3q8oddPseudo = 659, |
| VST3d16_UPD_VST3d32_UPD_VST3d8_UPD_VST3q16_UPD_VST3q32_UPD_VST3q8_UPD_VST3d16Pseudo_UPD_VST3d32Pseudo_UPD_VST3d8Pseudo_UPD_VST3q16Pseudo_UPD_VST3q16oddPseudo_UPD_VST3q32Pseudo_UPD_VST3q32oddPseudo_UPD_VST3q8Pseudo_UPD_VST3q8oddPseudo_UPD = 660, |
| VST4d16_VST4d32_VST4d8_VST4q16_VST4q32_VST4q8_VST4d16Pseudo_VST4d32Pseudo_VST4d8Pseudo_VST4q16oddPseudo_VST4q32oddPseudo_VST4q8oddPseudo = 661, |
| VST4d16_UPD_VST4d32_UPD_VST4d8_UPD_VST4q16_UPD_VST4q32_UPD_VST4q8_UPD_VST4d16Pseudo_UPD_VST4d32Pseudo_UPD_VST4d8Pseudo_UPD_VST4q16Pseudo_UPD_VST4q16oddPseudo_UPD_VST4q32Pseudo_UPD_VST4q32oddPseudo_UPD_VST4q8Pseudo_UPD_VST4q8oddPseudo_UPD = 662, |
| VST1LNd16_VST1LNd32_VST1LNd8_VST1LNq16Pseudo_VST1LNq32Pseudo_VST1LNq8Pseudo = 663, |
| VST1LNd16_UPD_VST1LNd32_UPD_VST1LNd8_UPD_VST1LNq16Pseudo_UPD_VST1LNq32Pseudo_UPD_VST1LNq8Pseudo_UPD = 664, |
| VST2LNd16_VST2LNd32_VST2LNd8_VST2LNq16_VST2LNq32_VST2LNd16Pseudo_VST2LNd32Pseudo_VST2LNd8Pseudo_VST2LNq16Pseudo_VST2LNq32Pseudo = 665, |
| VST2LNd16_UPD_VST2LNd32_UPD_VST2LNd8_UPD_VST2LNq16_UPD_VST2LNq32_UPD = 666, |
| VST2LNd16Pseudo_UPD_VST2LNd32Pseudo_UPD_VST2LNd8Pseudo_UPD_VST2LNq16Pseudo_UPD_VST2LNq32Pseudo_UPD = 667, |
| VST3LNd16_VST3LNd32_VST3LNd8_VST3LNq16_VST3LNq32_VST3LNd16Pseudo_VST3LNd32Pseudo_VST3LNd8Pseudo = 668, |
| VST3LNq16Pseudo_VST3LNq32Pseudo = 669, |
| VST3LNd16_UPD_VST3LNd32_UPD_VST3LNd8_UPD_VST3LNq16_UPD_VST3LNq32_UPD = 670, |
| VST3LNd16Pseudo_UPD_VST3LNd32Pseudo_UPD_VST3LNd8Pseudo_UPD_VST3LNq16Pseudo_UPD_VST3LNq32Pseudo_UPD = 671, |
| VST4LNd16_VST4LNd32_VST4LNd8_VST4LNq16_VST4LNq32_VST4LNd16Pseudo_VST4LNd32Pseudo_VST4LNd8Pseudo_VST4LNq16Pseudo_VST4LNq32Pseudo = 672, |
| VST4LNd16_UPD_VST4LNd32_UPD_VST4LNd8_UPD_VST4LNq16_UPD_VST4LNq32_UPD = 673, |
| VST4LNd16Pseudo_UPD_VST4LNd32Pseudo_UPD_VST4LNd8Pseudo_UPD_VST4LNq16Pseudo_UPD_VST4LNq32Pseudo_UPD = 674, |
| VDIVS = 675, |
| VSQRTS = 676, |
| VDIVD = 677, |
| VSQRTD = 678, |
| ABS = 679, |
| COPY = 680, |
| t2MOVCCi_t2MOVCCi16 = 681, |
| t2MOVi_t2MOVi16 = 682, |
| t2ABS = 683, |
| t2USAD8_t2USADA8 = 684, |
| t2SDIV_t2UDIV = 685, |
| t2LDREX_t2LDREXB_t2LDREXD_t2LDREXH_t2LDA_t2LDAB_t2LDAEX_t2LDAEXB_t2LDAEXD_t2LDAEXH_t2LDAH = 686, |
| LDA_LDAB_LDAEX_LDAEXB_LDAEXD_LDAEXH_LDAH = 687, |
| LDRBT_POST = 688, |
| MOVsr = 689, |
| t2MOVSsr_t2MOVsr = 690, |
| t2MOVsra_flag_t2MOVsrl_flag = 691, |
| MOVTi16_ga_pcrel_MOVTi16_t2MOVTi16_ga_pcrel_t2MOVTi16 = 692, |
| ADDSri_ADCri_ADDri_RSBSri_RSBri_RSCri_SBCri_t2ADDSri_t2ADCri_t2ADDri_t2ADDri12_t2RSBSri_t2RSBri_t2SBCri = 693, |
| CLZ_t2CLZ = 694, |
| t2ANDri_t2BICri_t2EORri_t2ORRri = 695, |
| t2MVNCCi = 696, |
| t2MVNi = 697, |
| t2MVNr = 698, |
| t2MVNs = 699, |
| ADDSrr_ADCrr_ADDrr_RSBrr_RSCrr_SBCrr_t2ADDSrr_t2ADCrr_t2ADDrr_t2SBCrr = 700, |
| CRC32B_CRC32CB_CRC32CH_CRC32CW_CRC32H_CRC32W_t2CRC32B_t2CRC32CB_t2CRC32CH_t2CRC32CW_t2CRC32H_t2CRC32W = 701, |
| t2ANDrr_t2BICrr_t2EORrr = 702, |
| ADDSrsi_ADCrsi_ADDrsi_RSBrsi_RSCrsi_SBCrsi = 703, |
| t2ADDSrs = 704, |
| t2ADCrs_t2ADDrs_t2SBCrs = 705, |
| t2ANDrs_t2BICrs_t2EORrs_t2ORRrs = 706, |
| t2RSBrs = 707, |
| ADDSrsr = 708, |
| ADCrsr_ADDrsr_RSBrsr_RSCrsr_SBCrsr = 709, |
| ADR = 710, |
| MVNi = 711, |
| MVNsi = 712, |
| t2MOVSsi_t2MOVsi = 713, |
| ASRi_RORi = 714, |
| ASRr_RORr_LSRi_LSRr_LSLi_LSLr = 715, |
| CMPri_CMNri = 716, |
| CMPrr_CMNzrr = 717, |
| CMPrsi_CMNzrsi = 718, |
| CMPrsr_CMNzrsr = 719, |
| t2LDC2L_OFFSET_t2LDC2L_OPTION_t2LDC2L_POST_t2LDC2L_PRE_t2LDC2_OFFSET_t2LDC2_OPTION_t2LDC2_POST_t2LDC2_PRE_t2LDCL_OFFSET_t2LDCL_OPTION_t2LDCL_POST_t2LDCL_PRE_t2LDC_OFFSET_t2LDC_OPTION_t2LDC_POST_t2LDC_PRE_RRXi = 720, |
| RBIT_REV_REV16_REVSH = 721, |
| RRX = 722, |
| TSTri = 723, |
| TSTrr = 724, |
| TSTrsi = 725, |
| TSTrsr = 726, |
| MRS_MRSbanked_MRSsys = 727, |
| MSR_MSRbanked_MSRi = 728, |
| SRSDA_SRSDA_UPD_SRSDB_SRSDB_UPD_SRSIA_SRSIA_UPD_SRSIB_SRSIB_UPD_t2SRSDB_t2SRSDB_UPD_t2SRSIA_t2SRSIA_UPD_RFEDA_RFEDA_UPD_RFEDB_RFEDB_UPD_RFEIA_RFEIA_UPD_RFEIB_RFEIB_UPD_t2RFEDB_t2RFEDBW_t2RFEIA_t2RFEIAW = 729, |
| t2STREX_t2STREXB_t2STREXD_t2STREXH = 730, |
| STL_STLB_STLEX_STLEXB_STLEXD_STLEXH_STLH = 731, |
| t2STL_t2STLB_t2STLEX_t2STLEXB_t2STLEXD_t2STLEXH_t2STLH = 732, |
| VABDfd_VABDhd = 733, |
| VABDfq_VABDhq = 734, |
| VABSD = 735, |
| VABSH = 736, |
| VABSS = 737, |
| VABShd = 738, |
| VABShq = 739, |
| VACGEfd_VACGEhd_VACGTfd_VACGThd = 740, |
| VACGEfq_VACGEhq_VACGTfq_VACGThq = 741, |
| VADDH_VSUBH = 742, |
| VADDfd_VSUBfd = 743, |
| VADDhd_VSUBhd = 744, |
| VADDfq_VSUBfq = 745, |
| VADDhq_VSUBhq = 746, |
| VLDRH = 747, |
| VLDR_FPCXTNS_off_VLDR_FPCXTNS_post_VLDR_FPCXTNS_pre_VLDR_FPCXTS_off_VLDR_FPCXTS_post_VLDR_FPCXTS_pre_VLDR_FPSCR_NZCVQC_off_VLDR_FPSCR_NZCVQC_post_VLDR_FPSCR_NZCVQC_pre_VLDR_FPSCR_off_VLDR_FPSCR_post_VLDR_FPSCR_pre_VLDR_P0_off_VLDR_P0_post_VLDR_P0_pre_VLDR_VPR_off_VLDR_VPR_post_VLDR_VPR_pre = 748, |
| VSTRH = 749, |
| VSTR_FPCXTNS_off_VSTR_FPCXTNS_post_VSTR_FPCXTNS_pre_VSTR_FPCXTS_off_VSTR_FPCXTS_post_VSTR_FPCXTS_pre_VSTR_FPSCR_NZCVQC_off_VSTR_FPSCR_NZCVQC_post_VSTR_FPSCR_NZCVQC_pre_VSTR_FPSCR_off_VSTR_FPSCR_post_VSTR_FPSCR_pre_VSTR_P0_off_VSTR_P0_post_VSTR_P0_pre_VSTR_VPR_off_VSTR_VPR_post_VSTR_VPR_pre = 750, |
| VABAsv2i32_VABAsv4i16_VABAsv8i8_VABAuv2i32_VABAuv4i16_VABAuv8i8 = 751, |
| VABDsv2i32_VABDsv4i16_VABDsv8i8_VABDuv2i32_VABDuv4i16_VABDuv8i8 = 752, |
| VABDsv16i8_VABDsv4i32_VABDsv8i16_VABDuv16i8_VABDuv4i32_VABDuv8i16 = 753, |
| VABDLsv4i32_VABDLsv8i16_VABDLuv4i32_VABDLuv8i16 = 754, |
| VADDv1i64_VADDv2i32_VADDv4i16_VADDv8i8 = 755, |
| VSUBv1i64_VSUBv2i32_VSUBv4i16_VSUBv8i8 = 756, |
| VADDv16i8_VADDv2i64_VADDv4i32_VADDv8i16 = 757, |
| VADDLsv2i64_VADDLsv4i32_VADDLsv8i16_VADDLuv2i64_VADDLuv4i32_VADDLuv8i16_VSUBLsv2i64_VSUBLsv4i32_VSUBLsv8i16_VSUBLuv2i64_VSUBLuv4i32_VSUBLuv8i16 = 758, |
| VANDd_VBICd_VEORd = 759, |
| VANDq_VBICq_VEORq = 760, |
| VBICiv2i32_VBICiv4i16 = 761, |
| VBICiv4i32_VBICiv8i16 = 762, |
| VBIFd_VBITd_VBSLd_VBSPd = 763, |
| VBIFq_VBITq_VBSLq_VBSPq = 764, |
| VCEQv16i8_VCEQv4i32_VCEQv8i16_VCGEsv16i8_VCGEsv4i32_VCGEsv8i16_VCGEuv16i8_VCGEuv4i32_VCGEuv8i16_VCGTsv16i8_VCGTsv4i32_VCGTsv8i16_VCGTuv16i8_VCGTuv4i32_VCGTuv8i16 = 765, |
| VCEQv2i32_VCEQv4i16_VCEQv8i8_VCGEsv2i32_VCGEsv4i16_VCGEsv8i8_VCGEuv2i32_VCGEuv4i16_VCGEuv8i8_VCGTsv2i32_VCGTsv4i16_VCGTsv8i8_VCGTuv2i32_VCGTuv4i16_VCGTuv8i8 = 766, |
| VCLZv16i8_VCLZv4i32_VCLZv8i16_VCNTq = 767, |
| VCLZv2i32_VCLZv4i16_VCLZv8i8_VCNTd = 768, |
| VCMPEH_VCMPEZH_VCMPH_VCMPZH = 769, |
| VDUP16d_VDUP32d_VDUP8d = 770, |
| VSELEQD_VSELEQH_VSELEQS_VSELGED_VSELGEH_VSELGES_VSELGTD_VSELGTH_VSELGTS_VSELVSD_VSELVSH_VSELVSS = 771, |
| VFMAhd_VFMShd = 772, |
| VFMAhq_VFMShq = 773, |
| VHADDsv2i32_VHADDsv4i16_VHADDsv8i8_VHADDuv2i32_VHADDuv4i16_VHADDuv8i8 = 774, |
| VHADDsv16i8_VHADDsv4i32_VHADDsv8i16_VHADDuv16i8_VHADDuv4i32_VHADDuv8i16 = 775, |
| VMAXsv16i8_VMAXsv4i32_VMAXsv8i16_VMAXuv16i8_VMAXuv4i32_VMAXuv8i16_VMINsv16i8_VMINsv4i32_VMINsv8i16_VMINuv16i8_VMINuv4i32_VMINuv8i16 = 776, |
| VPMAXf_VPMAXh_VPMINf_VPMINh = 777, |
| VNEGH = 778, |
| VNEGhd = 779, |
| VNEGhq = 780, |
| VNEGs16d_VNEGs32d_VNEGs8d = 781, |
| VNEGs16q_VNEGs32q_VNEGs8q = 782, |
| VPADDi16_VPADDi32_VPADDi8 = 783, |
| VPADALsv2i32_VPADALsv4i16_VPADALsv8i8_VPADALuv2i32_VPADALuv4i16_VPADALuv8i8 = 784, |
| VPADDLsv16i8_VPADDLsv2i32_VPADDLsv4i16_VPADDLsv4i32_VPADDLsv8i16_VPADDLsv8i8_VPADDLuv16i8_VPADDLuv2i32_VPADDLuv4i16_VPADDLuv4i32_VPADDLuv8i16_VPADDLuv8i8 = 785, |
| VQABSv2i32_VQABSv4i16_VQABSv8i8 = 786, |
| VQABSv16i8_VQABSv4i32_VQABSv8i16 = 787, |
| VQDMLALslv2i32_VQDMLALv2i64_VQDMLSLslv2i32_VQDMLSLv2i64 = 788, |
| VQDMLALslv4i16_VQDMLALv4i32_VQDMLSLslv4i16_VQDMLSLv4i32 = 789, |
| VQDMULHslv2i32_VQDMULHv2i32_VQDMULLv2i64_VQRDMULHslv2i32_VQRDMULHv2i32 = 790, |
| VQDMULHslv4i16_VQDMULHv4i16_VQDMULLslv2i32_VQDMULLslv4i16_VQDMULLv4i32_VQRDMULHslv4i16_VQRDMULHv4i16 = 791, |
| VQDMULHslv4i32_VQDMULHv4i32_VQRDMULHslv4i32_VQRDMULHv4i32 = 792, |
| VQDMULHslv8i16_VQDMULHv8i16_VQRDMULHslv8i16_VQRDMULHv8i16 = 793, |
| VQSHRNsv2i32_VQSHRNsv4i16_VQSHRNsv8i8_VQSHRNuv2i32_VQSHRNuv4i16_VQSHRNuv8i8 = 794, |
| VRSHLsv16i8_VRSHLsv2i64_VRSHLsv4i32_VRSHLsv8i16_VRSHLuv16i8_VRSHLuv2i64_VRSHLuv4i32_VRSHLuv8i16 = 795, |
| VRSHLsv1i64_VRSHLsv2i32_VRSHLsv4i16_VRSHLsv8i8_VRSHLuv1i64_VRSHLuv2i32_VRSHLuv4i16_VRSHLuv8i8_VRSHRsv16i8_VRSHRsv1i64_VRSHRsv2i32_VRSHRsv2i64_VRSHRsv4i16_VRSHRsv4i32_VRSHRsv8i16_VRSHRsv8i8_VRSHRuv16i8_VRSHRuv1i64_VRSHRuv2i32_VRSHRuv2i64_VRSHRuv4i16_VRSHRuv4i32_VRSHRuv8i16_VRSHRuv8i8 = 796, |
| VRSHRNv2i32_VRSHRNv4i16_VRSHRNv8i8 = 797, |
| VST1d16T_VST1d32T_VST1d64T_VST1d8T = 798, |
| VST1d16Q_VST1d32Q_VST1d64Q_VST1d8Q = 799, |
| VST1d64QPseudo = 800, |
| VST1LNd16_VST1LNd32_VST1LNd8 = 801, |
| VST1LNdAsm_16_VST1LNdAsm_32_VST1LNdAsm_8 = 802, |
| VST1d64QPseudoWB_fixed_VST1d64QPseudoWB_register = 803, |
| VST1LNd16_UPD_VST1LNd32_UPD_VST1LNd8_UPD = 804, |
| VST1LNdWB_fixed_Asm_16_VST1LNdWB_fixed_Asm_32_VST1LNdWB_fixed_Asm_8_VST1LNdWB_register_Asm_16_VST1LNdWB_register_Asm_32_VST1LNdWB_register_Asm_8 = 805, |
| VST2q16_VST2q32_VST2q8 = 806, |
| VST2LNd16_VST2LNd32_VST2LNd8 = 807, |
| VST2LNdAsm_16_VST2LNdAsm_32_VST2LNdAsm_8 = 808, |
| VST2LNd16Pseudo_VST2LNd32Pseudo_VST2LNd8Pseudo = 809, |
| VST2LNq16_VST2LNq32 = 810, |
| VST2LNqAsm_16_VST2LNqAsm_32 = 811, |
| VST2LNd16_UPD_VST2LNd32_UPD_VST2LNd8_UPD = 812, |
| VST2LNdWB_fixed_Asm_16_VST2LNdWB_fixed_Asm_32_VST2LNdWB_fixed_Asm_8_VST2LNdWB_register_Asm_16_VST2LNdWB_register_Asm_32_VST2LNdWB_register_Asm_8 = 813, |
| VST2LNd16Pseudo_UPD_VST2LNd32Pseudo_UPD_VST2LNd8Pseudo_UPD = 814, |
| VST2LNqWB_fixed_Asm_16_VST2LNqWB_fixed_Asm_32_VST2LNqWB_register_Asm_16_VST2LNqWB_register_Asm_32 = 815, |
| VST3d16_VST3d32_VST3d8_VST3q16_VST3q32_VST3q8 = 816, |
| VST3dAsm_16_VST3dAsm_32_VST3dAsm_8_VST3qAsm_16_VST3qAsm_32_VST3qAsm_8 = 817, |
| VST3d16Pseudo_VST3d32Pseudo_VST3d8Pseudo = 818, |
| VST3LNd16_VST3LNd32_VST3LNd8 = 819, |
| VST3LNdAsm_16_VST3LNdAsm_32_VST3LNdAsm_8 = 820, |
| VST3LNd16Pseudo_VST3LNd32Pseudo_VST3LNd8Pseudo = 821, |
| VST3LNqAsm_16_VST3LNqAsm_32 = 822, |
| VST3d16_UPD_VST3d32_UPD_VST3d8_UPD_VST3q16_UPD_VST3q32_UPD_VST3q8_UPD = 823, |
| VST3dWB_fixed_Asm_16_VST3dWB_fixed_Asm_32_VST3dWB_fixed_Asm_8_VST3dWB_register_Asm_16_VST3dWB_register_Asm_32_VST3dWB_register_Asm_8_VST3qWB_fixed_Asm_16_VST3qWB_fixed_Asm_32_VST3qWB_fixed_Asm_8_VST3qWB_register_Asm_16_VST3qWB_register_Asm_32_VST3qWB_register_Asm_8 = 824, |
| VST3LNd16_UPD_VST3LNd32_UPD_VST3LNd8_UPD = 825, |
| VST3LNdWB_fixed_Asm_16_VST3LNdWB_fixed_Asm_32_VST3LNdWB_fixed_Asm_8_VST3LNdWB_register_Asm_16_VST3LNdWB_register_Asm_32_VST3LNdWB_register_Asm_8 = 826, |
| VST3LNd16Pseudo_UPD_VST3LNd32Pseudo_UPD_VST3LNd8Pseudo_UPD = 827, |
| VST3LNqWB_fixed_Asm_16_VST3LNqWB_fixed_Asm_32_VST3LNqWB_register_Asm_16_VST3LNqWB_register_Asm_32 = 828, |
| VST4d16_VST4d32_VST4d8_VST4q16_VST4q32_VST4q8 = 829, |
| VST4dAsm_16_VST4dAsm_32_VST4dAsm_8_VST4qAsm_16_VST4qAsm_32_VST4qAsm_8 = 830, |
| VST4d16Pseudo_VST4d32Pseudo_VST4d8Pseudo = 831, |
| VST4LNd16_VST4LNd32_VST4LNd8 = 832, |
| VST4LNdAsm_16_VST4LNdAsm_32_VST4LNdAsm_8 = 833, |
| VST4LNd16Pseudo_VST4LNd32Pseudo_VST4LNd8Pseudo = 834, |
| VST4LNq16_VST4LNq32 = 835, |
| VST4LNqAsm_16_VST4LNqAsm_32 = 836, |
| VST4d16_UPD_VST4d32_UPD_VST4d8_UPD_VST4q16_UPD_VST4q32_UPD_VST4q8_UPD = 837, |
| VST4dWB_fixed_Asm_16_VST4dWB_fixed_Asm_32_VST4dWB_fixed_Asm_8_VST4dWB_register_Asm_16_VST4dWB_register_Asm_32_VST4dWB_register_Asm_8_VST4qWB_fixed_Asm_16_VST4qWB_fixed_Asm_32_VST4qWB_fixed_Asm_8_VST4qWB_register_Asm_16_VST4qWB_register_Asm_32_VST4qWB_register_Asm_8 = 838, |
| VST4LNd16_UPD_VST4LNd32_UPD_VST4LNd8_UPD = 839, |
| VST4LNdWB_fixed_Asm_16_VST4LNdWB_fixed_Asm_32_VST4LNdWB_fixed_Asm_8_VST4LNdWB_register_Asm_16_VST4LNdWB_register_Asm_32_VST4LNdWB_register_Asm_8 = 840, |
| VST4LNd16Pseudo_UPD_VST4LNd32Pseudo_UPD_VST4LNd8Pseudo_UPD = 841, |
| VST4LNqWB_fixed_Asm_16_VST4LNqWB_fixed_Asm_32_VST4LNqWB_register_Asm_16_VST4LNqWB_register_Asm_32 = 842, |
| BKPT_tBKPT_CDP_CDP2_t2CDP_t2CDP2_CLREX_t2CLREX_CONSTPOOL_ENTRY_COPY_STRUCT_BYVAL_I32_CPS1p_CPS2p_CPS3p_t2CPS1p_t2CPS2p_t2CPS3p_DBG_t2DBG_DMB_t2DMB_DSB_t2DSB_ERET_HINT_t2HINT_tHINT_HLT_tHLT_HVC_ISB_t2ISB_SETEND_tSETEND_SETPAN_t2SETPAN_SMC_t2SMC_SPACE_SWP_SWPB_TRAP_TRAPNaCl_UDF_t2DCPS1_t2DCPS2_t2DCPS3_t2SG_t2TT_t2TTA_t2TTAT_t2TTT_tCPS_CMP_SWAP_16_CMP_SWAP_32_CMP_SWAP_64_CMP_SWAP_8 = 843, |
| t2HVC_tTRAP_SVC_tSVC = 844, |
| t2UDF_tUDF_t__brkdiv0 = 845, |
| LDC2L_OFFSET_LDC2L_OPTION_LDC2L_POST_LDC2L_PRE_LDC2_OFFSET_LDC2_OPTION_LDC2_POST_LDC2_PRE_LDCL_OFFSET_LDCL_OPTION_LDCL_POST_LDCL_PRE_LDC_OFFSET_LDC_OPTION_LDC_POST_LDC_PRE_STC2L_OFFSET_STC2L_OPTION_STC2L_POST_STC2L_PRE_STC2_OFFSET_STC2_OPTION_STC2_POST_STC2_PRE_STCL_OFFSET_STCL_OPTION_STCL_POST_STCL_PRE_STC_OFFSET_STC_OPTION_STC_POST_STC_PRE_t2STC2L_OFFSET_t2STC2L_OPTION_t2STC2L_POST_t2STC2L_PRE_t2STC2_OFFSET_t2STC2_OPTION_t2STC2_POST_t2STC2_PRE_t2STCL_OFFSET_t2STCL_OPTION_t2STCL_POST_t2STCL_PRE_t2STC_OFFSET_t2STC_OPTION_t2STC_POST_t2STC_PRE_MEMCPY = 846, |
| t2LDC2L_OFFSET_t2LDC2L_OPTION_t2LDC2L_POST_t2LDC2L_PRE_t2LDC2_OFFSET_t2LDC2_OPTION_t2LDC2_POST_t2LDC2_PRE_t2LDCL_OFFSET_t2LDCL_OPTION_t2LDCL_POST_t2LDCL_PRE_t2LDC_OFFSET_t2LDC_OPTION_t2LDC_POST_t2LDC_PRE = 847, |
| LDREX_LDREXB_LDREXD_LDREXH = 848, |
| MCR_MCR2_MCRR_MCRR2_t2MCR_t2MCR2_t2MCRR_t2MCRR2_MRC_MRC2_t2MRC_t2MRC2_MRRC_MRRC2_t2MRRC_t2MRRC2_t2MRS_AR_t2MRS_M_t2MRSbanked_t2MRSsys_AR_t2MSR_AR_t2MSR_M_t2MSRbanked = 849, |
| FLDMXDB_UPD_FLDMXIA_FLDMXIA_UPD_FSTMXDB_UPD_FSTMXIA_FSTMXIA_UPD = 850, |
| ADJCALLSTACKDOWN_tADJCALLSTACKDOWN_ADJCALLSTACKUP_tADJCALLSTACKUP_Int_eh_sjlj_dispatchsetup_Int_eh_sjlj_longjmp_Int_eh_sjlj_setjmp_Int_eh_sjlj_setjmp_nofp_Int_eh_sjlj_setup_dispatch_t2Int_eh_sjlj_setjmp_t2Int_eh_sjlj_setjmp_nofp_tInt_eh_sjlj_longjmp_tInt_eh_sjlj_setjmp_t2SUBS_PC_LR_JUMPTABLE_ADDRS_JUMPTABLE_INSTS_JUMPTABLE_TBB_JUMPTABLE_TBH_tInt_WIN_eh_sjlj_longjmp_VLD1LNdAsm_16_VLD1LNdAsm_32_VLD1LNdAsm_8_VLD1LNdWB_fixed_Asm_16_VLD1LNdWB_fixed_Asm_32_VLD1LNdWB_fixed_Asm_8_VLD1LNdWB_register_Asm_16_VLD1LNdWB_register_Asm_32_VLD1LNdWB_register_Asm_8_VLD2LNdAsm_16_VLD2LNdAsm_32_VLD2LNdAsm_8_VLD2LNdWB_fixed_Asm_16_VLD2LNdWB_fixed_Asm_32_VLD2LNdWB_fixed_Asm_8_VLD2LNdWB_register_Asm_16_VLD2LNdWB_register_Asm_32_VLD2LNdWB_register_Asm_8_VLD2LNqAsm_16_VLD2LNqAsm_32_VLD2LNqWB_fixed_Asm_16_VLD2LNqWB_fixed_Asm_32_VLD2LNqWB_register_Asm_16_VLD2LNqWB_register_Asm_32_VLD3DUPdAsm_16_VLD3DUPdAsm_32_VLD3DUPdAsm_8_VLD3DUPdWB_fixed_Asm_16_VLD3DUPdWB_fixed_Asm_32_VLD3DUPdWB_fixed_Asm_8_VLD3DUPdWB_register_Asm_16_VLD3DUPdWB_register_Asm_32_VLD3DUPdWB_register_Asm_8_VLD3DUPqAsm_16_VLD3DUPqAsm_32_VLD3DUPqAsm_8_VLD3DUPqWB_fixed_Asm_16_VLD3DUPqWB_fixed_Asm_32_VLD3DUPqWB_fixed_Asm_8_VLD3DUPqWB_register_Asm_16_VLD3DUPqWB_register_Asm_32_VLD3DUPqWB_register_Asm_8_VLD3LNdAsm_16_VLD3LNdAsm_32_VLD3LNdAsm_8_VLD3LNdWB_fixed_Asm_16_VLD3LNdWB_fixed_Asm_32_VLD3LNdWB_fixed_Asm_8_VLD3LNdWB_register_Asm_16_VLD3LNdWB_register_Asm_32_VLD3LNdWB_register_Asm_8_VLD3LNqAsm_16_VLD3LNqAsm_32_VLD3LNqWB_fixed_Asm_16_VLD3LNqWB_fixed_Asm_32_VLD3LNqWB_register_Asm_16_VLD3LNqWB_register_Asm_32_VLD3dAsm_16_VLD3dAsm_32_VLD3dAsm_8_VLD3dWB_fixed_Asm_16_VLD3dWB_fixed_Asm_32_VLD3dWB_fixed_Asm_8_VLD3dWB_register_Asm_16_VLD3dWB_register_Asm_32_VLD3dWB_register_Asm_8_VLD3qAsm_16_VLD3qAsm_32_VLD3qAsm_8_VLD3qWB_fixed_Asm_16_VLD3qWB_fixed_Asm_32_VLD3qWB_fixed_Asm_8_VLD3qWB_register_Asm_16_VLD3qWB_register_Asm_32_VLD3qWB_register_Asm_8_VLD4DUPdAsm_16_VLD4DUPdAsm_32_VLD4DUPdAsm_8_VLD4DUPdWB_fixed_Asm_16_VLD4DUPdWB_fixed_Asm_32_VLD4DUPdWB_fixed_Asm_8_VLD4DUPdWB_register_Asm_16_VLD4DUPdWB_register_Asm_32_VLD4DUPdWB_register_Asm_8_VLD4DUPqAsm_16_VLD4DUPqAsm_32_VLD4DUPqAsm_8_VLD4DUPqWB_fixed_Asm_16_VLD4DUPqWB_fixed_Asm_32_VLD4DUPqWB_fixed_Asm_8_VLD4DUPqWB_register_Asm_16_VLD4DUPqWB_register_Asm_32_VLD4DUPqWB_register_Asm_8_VLD4LNdAsm_16_VLD4LNdAsm_32_VLD4LNdAsm_8_VLD4LNdWB_fixed_Asm_16_VLD4LNdWB_fixed_Asm_32_VLD4LNdWB_fixed_Asm_8_VLD4LNdWB_register_Asm_16_VLD4LNdWB_register_Asm_32_VLD4LNdWB_register_Asm_8_VLD4LNqAsm_16_VLD4LNqAsm_32_VLD4LNqWB_fixed_Asm_16_VLD4LNqWB_fixed_Asm_32_VLD4LNqWB_register_Asm_16_VLD4LNqWB_register_Asm_32_VLD4dAsm_16_VLD4dAsm_32_VLD4dAsm_8_VLD4dWB_fixed_Asm_16_VLD4dWB_fixed_Asm_32_VLD4dWB_fixed_Asm_8_VLD4dWB_register_Asm_16_VLD4dWB_register_Asm_32_VLD4dWB_register_Asm_8_VLD4qAsm_16_VLD4qAsm_32_VLD4qAsm_8_VLD4qWB_fixed_Asm_16_VLD4qWB_fixed_Asm_32_VLD4qWB_fixed_Asm_8_VLD4qWB_register_Asm_16_VLD4qWB_register_Asm_32_VLD4qWB_register_Asm_8_WIN__CHKSTK_WIN__DBZCHK = 851, |
| SUBS_PC_LR = 852, |
| B_t2B_tB_BX_CALL_tBXNS_RET_tBX_CALL_tBX_RET_tBX_RET_vararg_BX_BX_RET_BX_pred_tBX_tBXNS_Bcc_t2Bcc_tBcc_TAILJMPd_TAILJMPr_TAILJMPr4_tTAILJMPd_tTAILJMPdND_tTAILJMPr_TCRETURNdi_TCRETURNri_tCBNZ_tCBZ = 853, |
| BXJ = 854, |
| tBfar = 855, |
| BL_tBL_BL_pred_tBLXi = 856, |
| BLXi = 857, |
| TPsoft_tTPsoft = 858, |
| BLX_noip_BLX_pred_noip_BLX_BLX_pred_tBLXr_noip_tBLXNSr_tBLXr = 859, |
| BCCi64_BCCZi64 = 860, |
| BR_JTadd_tBR_JTr_t2TBB_t2TBH = 861, |
| BR_JTr_t2BR_JT_t2TBB_JT_t2TBH_JT_tBRIND = 862, |
| t2BXJ = 863, |
| BR_JTm_i12_BR_JTm_rs = 864, |
| tADDframe = 865, |
| MOVi16_ga_pcrel_MOVi_MOVi16_MOVCCi16_tMOVi8 = 866, |
| MOVr_MOVr_TC_tMOVSr_tMOVr = 867, |
| MVNCCi_MOVCCi = 868, |
| BMOVPCB_CALL_BMOVPCRX_CALL = 869, |
| MOVCCr = 870, |
| tMOVCCr_pseudo = 871, |
| tMVN = 872, |
| MOVCCsi = 873, |
| t2ASRri_tASRri_t2LSRri_tLSRri_t2LSLri_tLSLri_t2RORri_t2RRX = 874, |
| LSRi_LSLi = 875, |
| t2MOVCCasr_t2MOVCClsl_t2MOVCClsr_t2MOVCCror = 876, |
| t2MOVCCr = 877, |
| t2MOVTi16_ga_pcrel_t2MOVTi16 = 878, |
| t2MOVr = 879, |
| tROR = 880, |
| t2ASRrr_tASRrr_t2LSRrr_tLSRrr_t2LSLrr_tLSLrr_t2RORrr = 881, |
| MOVPCRX_MOVPCLR = 882, |
| tMUL = 883, |
| SADD16_SADD8_SSUB16_SSUB8_UADD16_UADD8_USUB16_USUB8 = 884, |
| t2SADD16_t2SADD8_t2SSUB16_t2SSUB8_t2UADD16_t2UADD8_t2USUB16_t2USUB8 = 885, |
| SHADD16_SHADD8_SHSUB16_SHSUB8_UHADD16_UHADD8_UHSUB16_UHSUB8 = 886, |
| t2SHADD16_t2SHADD8_t2SHSUB16_t2SHSUB8_t2UHADD16_t2UHADD8_t2UHSUB16_t2UHSUB8 = 887, |
| QADD16_QADD8_QSUB16_QSUB8_UQADD16_UQADD8_UQSUB16_UQSUB8 = 888, |
| t2QADD_t2QADD16_t2QADD8_t2UQADD16_t2UQADD8_t2QSUB_t2QSUB16_t2QSUB8_t2UQSUB16_t2UQSUB8 = 889, |
| QASX_QSAX_UQASX_UQSAX = 890, |
| t2QASX_t2QSAX_t2UQASX_t2UQSAX = 891, |
| SSAT_SSAT16_USAT_USAT16 = 892, |
| QADD_QSUB = 893, |
| SBFX_UBFX = 894, |
| t2SBFX_t2UBFX = 895, |
| SXTB_SXTH_UXTB_UXTH = 896, |
| t2SXTB_t2SXTH_t2UXTB_t2UXTH = 897, |
| tSXTB_tSXTH_tUXTB_tUXTH = 898, |
| SXTAB_SXTAH_UXTAB_UXTAH = 899, |
| t2SXTAB_t2SXTAH_t2UXTAB_t2UXTAH = 900, |
| LDRConstPool_t2LDRConstPool_tLDRConstPool = 901, |
| PICLDRB_PICLDRH = 902, |
| PICLDRSB_PICLDRSH = 903, |
| tLDR_postidx = 904, |
| tLDRBi_tLDRHi = 905, |
| tLDRi_tLDRpci_tLDRspi = 906, |
| t2LDRBpcrel_t2LDRHpcrel_t2LDRpcrel = 907, |
| LDR_PRE_IMM = 908, |
| LDRB_PRE_IMM = 909, |
| t2LDRB_PRE = 910, |
| LDR_PRE_REG = 911, |
| LDRB_PRE_REG = 912, |
| LDRH_PRE = 913, |
| LDRSB_PRE_LDRSH_PRE = 914, |
| t2LDR_PRE_imm = 915, |
| t2LDRH_PRE = 916, |
| t2LDRSB_PRE_t2LDRSH_PRE = 917, |
| t2LDR_PRE = 918, |
| LDRD_PRE = 919, |
| t2LDRD_PRE = 920, |
| LDRT_POST_IMM = 921, |
| LDRBT_POST_IMM = 922, |
| LDRHTi = 923, |
| LDRSBTi_LDRSHTi = 924, |
| t2LDRB_POST = 925, |
| LDRH_POST = 926, |
| LDRSB_POST_LDRSH_POST = 927, |
| LDR_POST_REG = 928, |
| LDRB_POST_REG = 929, |
| LDRT_POST = 930, |
| PLDi12_t2PLDi12_PLDWi12_t2PLDWi12_t2PLDWi8_t2PLDWs_t2PLDi8_t2PLDpci_t2PLDs_PLIi12_PLIrs_t2PLIi12_t2PLIi8_t2PLIpci_t2PLIs = 931, |
| PLDrs_PLDWrs = 932, |
| VLLDM = 933, |
| STRBi12_PICSTRB_PICSTRH = 934, |
| t2STRBT = 935, |
| STR_PRE_IMM = 936, |
| STRB_PRE_IMM = 937, |
| STRBi_preidx_STRBr_preidx_STRi_preidx_STRr_preidx_STRH_preidx = 938, |
| STRH_PRE = 939, |
| t2STRH_PRE_t2STR_PRE = 940, |
| t2STR_PRE_imm = 941, |
| t2STRB_PRE = 942, |
| t2STRD_PRE = 943, |
| STR_PRE_REG = 944, |
| STRB_PRE_REG = 945, |
| STRD_PRE = 946, |
| STRT_POST_IMM = 947, |
| STRBT_POST_IMM = 948, |
| t2STR_POST_imm = 949, |
| t2STRB_POST = 950, |
| STRBT_POST_REG_STRB_POST_REG = 951, |
| VLSTM = 952, |
| VCVTASD_VCVTASH_VCVTASS_VCVTAUD_VCVTAUH_VCVTAUS_VCVTMSD_VCVTMSH_VCVTMSS_VCVTMUD_VCVTMUH_VCVTMUS_VCVTNSD_VCVTNSH_VCVTNSS_VCVTNUD_VCVTNUH_VCVTNUS_VCVTPSD_VCVTPSH_VCVTPSS_VCVTPUD_VCVTPUH_VCVTPUS_VCVTBDH_VCVTTDH_VCVTTHD = 953, |
| VTOSLS_VTOUHS_VTOULS = 954, |
| VJCVT = 955, |
| VRINTAD_VRINTAH_VRINTAS_VRINTMD_VRINTMH_VRINTMS_VRINTND_VRINTNH_VRINTNS_VRINTPD_VRINTPH_VRINTPS_VRINTRD_VRINTRH_VRINTRS_VRINTXD_VRINTXH_VRINTXS_VRINTZD_VRINTZH_VRINTZS = 956, |
| VSQRTH = 957, |
| VMAXsv2i32_VMAXsv4i16_VMAXsv8i8_VMAXuv2i32_VMAXuv4i16_VMAXuv8i8_VMINsv2i32_VMINsv4i16_VMINsv8i8_VMINuv2i32_VMINuv4i16_VMINuv8i8 = 958, |
| VUDOTD_VUDOTDI_VSDOTD_VSDOTDI_VUDOTQ_VUDOTQI_VSDOTQ_VSDOTQI = 959, |
| FCONSTD = 960, |
| FCONSTH = 961, |
| FCONSTS = 962, |
| VMOVHcc_VMOVH = 963, |
| VINSH = 964, |
| VSTMSIA = 965, |
| VSTMSDB_UPD_VSTMSIA_UPD = 966, |
| VRHADDsv16i8_VRHADDsv4i32_VRHADDsv8i16_VRHADDuv16i8_VRHADDuv4i32_VRHADDuv8i16 = 967, |
| VRHADDsv2i32_VRHADDsv4i16_VRHADDsv8i8_VRHADDuv2i32_VRHADDuv4i16_VRHADDuv8i8 = 968, |
| VMVNv2i32_VMVNv4i16_VMVNv4i32_VMVNv8i16 = 969, |
| VMULpd_VMULv4i16_VMULv8i8_VMULslv4i16 = 970, |
| VMULv2i32_VMULslv2i32 = 971, |
| VQDMULHslv2i32_VQDMULHv2i32_VQRDMULHslv2i32_VQRDMULHv2i32 = 972, |
| VQDMULHslv4i16_VQDMULHv4i16_VQRDMULHslv4i16_VQRDMULHv4i16 = 973, |
| VMULpq_VMULv16i8_VMULv8i16_VMULslv8i16 = 974, |
| VMLAslv2i32_VMLAv2i32_VMLSslv2i32_VMLSv2i32 = 975, |
| VMLAslv4i16_VMLAv4i16_VMLAv8i8_VMLSslv4i16_VMLSv4i16_VMLSv8i8 = 976, |
| VQRDMLAHslv2i32_VQRDMLAHv2i32_VQRDMLSHslv2i32_VQRDMLSHv2i32 = 977, |
| VQRDMLAHslv4i16_VQRDMLAHv4i16_VQRDMLSHslv4i16_VQRDMLSHv4i16 = 978, |
| VQRDMLAHslv4i32_VQRDMLAHv4i32_VQRDMLSHslv4i32_VQRDMLSHv4i32 = 979, |
| VQRDMLAHslv8i16_VQRDMLAHv8i16_VQRDMLSHslv8i16_VQRDMLSHv8i16 = 980, |
| VMULLp8_VMULLslsv2i32_VMULLslsv4i16_VMULLsluv2i32_VMULLsluv4i16_VMULLsv4i32_VMULLsv8i16_VMULLuv4i32_VMULLuv8i16 = 981, |
| VSHLiv16i8_VSHLiv1i64_VSHLiv2i32_VSHLiv2i64_VSHLiv4i16_VSHLiv4i32_VSHLiv8i16_VSHLiv8i8_VSHLLi16_VSHLLi32_VSHLLi8_VSHLLsv2i64_VSHLLsv4i32_VSHLLsv8i16_VSHLLuv2i64_VSHLLuv4i32_VSHLLuv8i16_VSHRsv16i8_VSHRsv1i64_VSHRsv2i32_VSHRsv2i64_VSHRsv4i16_VSHRsv4i32_VSHRsv8i16_VSHRsv8i8_VSHRuv16i8_VSHRuv1i64_VSHRuv2i32_VSHRuv2i64_VSHRuv4i16_VSHRuv4i32_VSHRuv8i16_VSHRuv8i8 = 982, |
| VQSHLsiv16i8_VQSHLsiv1i64_VQSHLsiv2i32_VQSHLsiv2i64_VQSHLsiv4i16_VQSHLsiv4i32_VQSHLsiv8i16_VQSHLsiv8i8_VQSHLsuv16i8_VQSHLsuv1i64_VQSHLsuv2i32_VQSHLsuv2i64_VQSHLsuv4i16_VQSHLsuv4i32_VQSHLsuv8i16_VQSHLsuv8i8_VQSHLuiv16i8_VQSHLuiv1i64_VQSHLuiv2i32_VQSHLuiv2i64_VQSHLuiv4i16_VQSHLuiv4i32_VQSHLuiv8i16_VQSHLuiv8i8 = 983, |
| VRSHRsv16i8_VRSHRsv1i64_VRSHRsv2i32_VRSHRsv2i64_VRSHRsv4i16_VRSHRsv4i32_VRSHRsv8i16_VRSHRsv8i8_VRSHRuv16i8_VRSHRuv1i64_VRSHRuv2i32_VRSHRuv2i64_VRSHRuv4i16_VRSHRuv4i32_VRSHRuv8i16_VRSHRuv8i8 = 984, |
| VSLIv1i64_VSLIv2i32_VSLIv4i16_VSLIv8i8_VSRIv1i64_VSRIv2i32_VSRIv4i16_VSRIv8i8 = 985, |
| VSLIv16i8_VSLIv2i64_VSLIv4i32_VSLIv8i16_VSRIv16i8_VSRIv2i64_VSRIv4i32_VSRIv8i16 = 986, |
| VPADDh = 987, |
| VCADDv2f32_VCADDv4f16_VCMLAv2f32_VCMLAv2f32_indexed_VCMLAv4f16_VCMLAv4f16_indexed = 988, |
| VCADDv4f32_VCADDv8f16_VCMLAv4f32_VCMLAv4f32_indexed_VCMLAv8f16_VCMLAv8f16_indexed = 989, |
| VCVTf2sd_VCVTf2ud_VCVTf2xsd_VCVTf2xud_VCVTs2fd_VCVTu2fd_VCVTxs2fd_VCVTxu2fd = 990, |
| VCVTf2sq_VCVTf2uq_VCVTs2fq_VCVTu2fq_VCVTf2xsq_VCVTf2xuq_VCVTxs2fq_VCVTxu2fq = 991, |
| NEON_VMAXNMNDf_NEON_VMAXNMNDh_NEON_VMAXNMNQf_NEON_VMAXNMNQh_VFP_VMAXNMD_VFP_VMAXNMH_VFP_VMAXNMS_NEON_VMINNMNDf_NEON_VMINNMNDh_NEON_VMINNMNQf_NEON_VMINNMNQh_VFP_VMINNMD_VFP_VMINNMH_VFP_VMINNMS = 992, |
| VMULhd = 993, |
| VMULhq = 994, |
| VRINTANDf_VRINTANDh_VRINTANQf_VRINTANQh_VRINTMNDf_VRINTMNDh_VRINTMNQf_VRINTMNQh_VRINTNNDf_VRINTNNDh_VRINTNNQf_VRINTNNQh_VRINTPNDf_VRINTPNDh_VRINTPNQf_VRINTPNQh_VRINTXNDf_VRINTXNDh_VRINTXNQf_VRINTXNQh_VRINTZNDf_VRINTZNDh_VRINTZNQf_VRINTZNQh = 995, |
| VMOVD0_VMOVQ0 = 996, |
| VTRNd16_VTRNd32_VTRNd8 = 997, |
| VLD2d16_VLD2d32_VLD2d8 = 998, |
| VLD2d16wb_fixed_VLD2d16wb_register_VLD2d32wb_fixed_VLD2d32wb_register_VLD2d8wb_fixed_VLD2d8wb_register = 999, |
| VLD3LNd32_VLD3LNq32_VLD3LNd32Pseudo_VLD3LNq32Pseudo = 1000, |
| VLD3LNd32_UPD_VLD3LNq32_UPD = 1001, |
| VLD3LNd32Pseudo_UPD_VLD3LNq32Pseudo_UPD = 1002, |
| VLD4LNd32_VLD4LNq32_VLD4LNd32Pseudo_VLD4LNq32Pseudo = 1003, |
| VLD4LNd32_UPD_VLD4LNq32_UPD = 1004, |
| VLD4LNd32Pseudo_UPD_VLD4LNq32Pseudo_UPD = 1005, |
| AESD_AESE_AESIMC_AESMC = 1006, |
| SHA1SU0 = 1007, |
| SHA1H_SHA1SU1 = 1008, |
| SHA1C_SHA1M_SHA1P = 1009, |
| SHA256SU0 = 1010, |
| SHA256H_SHA256H2_SHA256SU1 = 1011, |
| t2LDMIA_RET = 1012, |
| tLDMIA_UPD_t2LDMDB_UPD_t2LDMIA_UPD = 1013, |
| t2LDMDB_t2LDMIA_tLDMIA = 1014, |
| t2LDRConstPool_tLDRConstPool = 1015, |
| t2LDRLIT_ga_pcrel = 1016, |
| tLDRLIT_ga_abs = 1017, |
| tLDRLIT_ga_pcrel = 1018, |
| t2LDREX_t2LDREXB_t2LDREXD_t2LDREXH = 1019, |
| t2STMDB_t2STMIA = 1020, |
| t2STMDB_UPD_t2STMIA_UPD_tSTMIA_UPD = 1021, |
| tMOVSr_tMOVr = 1022, |
| tMOVi8 = 1023, |
| t2MSR_AR_t2MSR_M_t2MSRbanked_t2MRS_AR_t2MRS_M_t2MRSbanked_t2MRSsys_AR = 1024, |
| t2CLREX = 1025, |
| t2SMLAL_t2SMLALBB_t2SMLALBT_t2SMLALD_t2SMLALDX_t2SMLALTB_t2SMLALTT_t2SMLSLD_t2SMLSLDX = 1026, |
| t2REV_t2REV16_t2REVSH_tREV_tREV16_tREVSH = 1027, |
| t2CDP_t2CDP2 = 1028, |
| t2MCR_t2MCR2_t2MCRR_t2MCRR2_t2MRC_t2MRC2_t2MRRC_t2MRRC2 = 1029, |
| t2STC2L_OFFSET_t2STC2L_OPTION_t2STC2L_POST_t2STC2L_PRE_t2STC2_OFFSET_t2STC2_OPTION_t2STC2_POST_t2STC2_PRE_t2STCL_OFFSET_t2STCL_OPTION_t2STCL_POST_t2STCL_PRE_t2STC_OFFSET_t2STC_OPTION_t2STC_POST_t2STC_PRE = 1030, |
| tCPS_t2ISB_t2DSB_t2DMB_t2HINT_tHINT = 1031, |
| t2UDF_tUDF = 1032, |
| tBKPT_t2DBG = 1033, |
| Int_eh_sjlj_dispatchsetup_Int_eh_sjlj_longjmp_Int_eh_sjlj_setjmp_Int_eh_sjlj_setjmp_nofp_Int_eh_sjlj_setup_dispatch_t2Int_eh_sjlj_setjmp_t2Int_eh_sjlj_setjmp_nofp_tInt_eh_sjlj_longjmp_tInt_eh_sjlj_setjmp_ADJCALLSTACKDOWN_ADJCALLSTACKUP_tADJCALLSTACKDOWN_tADJCALLSTACKUP = 1034, |
| CMP_SWAP_16_CMP_SWAP_32_CMP_SWAP_64_CMP_SWAP_8 = 1035, |
| JUMPTABLE_ADDRS_JUMPTABLE_INSTS_JUMPTABLE_TBB_JUMPTABLE_TBH = 1036, |
| MEMCPY = 1037, |
| VSETLNi32 = 1038, |
| VGETLNi32 = 1039, |
| VLD1LNdAsm_16_VLD1LNdAsm_32_VLD1LNdAsm_8_VLD1LNdWB_fixed_Asm_16_VLD1LNdWB_fixed_Asm_32_VLD1LNdWB_fixed_Asm_8_VLD1LNdWB_register_Asm_16_VLD1LNdWB_register_Asm_32_VLD1LNdWB_register_Asm_8_VLD2LNdAsm_16_VLD2LNdAsm_32_VLD2LNdAsm_8_VLD2LNdWB_fixed_Asm_16_VLD2LNdWB_fixed_Asm_32_VLD2LNdWB_fixed_Asm_8_VLD2LNdWB_register_Asm_16_VLD2LNdWB_register_Asm_32_VLD2LNdWB_register_Asm_8_VLD2LNqAsm_16_VLD2LNqAsm_32_VLD2LNqWB_fixed_Asm_16_VLD2LNqWB_fixed_Asm_32_VLD2LNqWB_register_Asm_16_VLD2LNqWB_register_Asm_32_VLD3DUPdAsm_16_VLD3DUPdAsm_32_VLD3DUPdAsm_8_VLD3DUPdWB_fixed_Asm_16_VLD3DUPdWB_fixed_Asm_32_VLD3DUPdWB_fixed_Asm_8_VLD3DUPdWB_register_Asm_16_VLD3DUPdWB_register_Asm_32_VLD3DUPdWB_register_Asm_8_VLD3DUPqAsm_16_VLD3DUPqAsm_32_VLD3DUPqAsm_8_VLD3DUPqWB_fixed_Asm_16_VLD3DUPqWB_fixed_Asm_32_VLD3DUPqWB_fixed_Asm_8_VLD3DUPqWB_register_Asm_16_VLD3DUPqWB_register_Asm_32_VLD3DUPqWB_register_Asm_8_VLD3LNdAsm_16_VLD3LNdAsm_32_VLD3LNdAsm_8_VLD3LNdWB_fixed_Asm_16_VLD3LNdWB_fixed_Asm_32_VLD3LNdWB_fixed_Asm_8_VLD3LNdWB_register_Asm_16_VLD3LNdWB_register_Asm_32_VLD3LNdWB_register_Asm_8_VLD3LNqAsm_16_VLD3LNqAsm_32_VLD3LNqWB_fixed_Asm_16_VLD3LNqWB_fixed_Asm_32_VLD3LNqWB_register_Asm_16_VLD3LNqWB_register_Asm_32_VLD3dAsm_16_VLD3dAsm_32_VLD3dAsm_8_VLD3dWB_fixed_Asm_16_VLD3dWB_fixed_Asm_32_VLD3dWB_fixed_Asm_8_VLD3dWB_register_Asm_16_VLD3dWB_register_Asm_32_VLD3dWB_register_Asm_8_VLD3qAsm_16_VLD3qAsm_32_VLD3qAsm_8_VLD3qWB_fixed_Asm_16_VLD3qWB_fixed_Asm_32_VLD3qWB_fixed_Asm_8_VLD3qWB_register_Asm_16_VLD3qWB_register_Asm_32_VLD3qWB_register_Asm_8_VLD4DUPdAsm_16_VLD4DUPdAsm_32_VLD4DUPdAsm_8_VLD4DUPdWB_fixed_Asm_16_VLD4DUPdWB_fixed_Asm_32_VLD4DUPdWB_fixed_Asm_8_VLD4DUPdWB_register_Asm_16_VLD4DUPdWB_register_Asm_32_VLD4DUPdWB_register_Asm_8_VLD4DUPqAsm_16_VLD4DUPqAsm_32_VLD4DUPqAsm_8_VLD4DUPqWB_fixed_Asm_16_VLD4DUPqWB_fixed_Asm_32_VLD4DUPqWB_fixed_Asm_8_VLD4DUPqWB_register_Asm_16_VLD4DUPqWB_register_Asm_32_VLD4DUPqWB_register_Asm_8_VLD4LNdAsm_16_VLD4LNdAsm_32_VLD4LNdAsm_8_VLD4LNdWB_fixed_Asm_16_VLD4LNdWB_fixed_Asm_32_VLD4LNdWB_fixed_Asm_8_VLD4LNdWB_register_Asm_16_VLD4LNdWB_register_Asm_32_VLD4LNdWB_register_Asm_8_VLD4LNqAsm_16_VLD4LNqAsm_32_VLD4LNqWB_fixed_Asm_16_VLD4LNqWB_fixed_Asm_32_VLD4LNqWB_register_Asm_16_VLD4LNqWB_register_Asm_32_VLD4dAsm_16_VLD4dAsm_32_VLD4dAsm_8_VLD4dWB_fixed_Asm_16_VLD4dWB_fixed_Asm_32_VLD4dWB_fixed_Asm_8_VLD4dWB_register_Asm_16_VLD4dWB_register_Asm_32_VLD4dWB_register_Asm_8_VLD4qAsm_16_VLD4qAsm_32_VLD4qAsm_8_VLD4qWB_fixed_Asm_16_VLD4qWB_fixed_Asm_32_VLD4qWB_fixed_Asm_8_VLD4qWB_register_Asm_16_VLD4qWB_register_Asm_32_VLD4qWB_register_Asm_8 = 1040, |
| VLD1d16QPseudo_VLD1d16QPseudoWB_fixed_VLD1d16QPseudoWB_register_VLD1d32QPseudo_VLD1d32QPseudoWB_fixed_VLD1d32QPseudoWB_register_VLD1d8QPseudo_VLD1d8QPseudoWB_fixed_VLD1d8QPseudoWB_register_VLD1q16HighQPseudo_VLD1q16HighQPseudo_UPD_VLD1q16LowQPseudo_UPD_VLD1q32HighQPseudo_VLD1q32HighQPseudo_UPD_VLD1q32LowQPseudo_UPD_VLD1q64HighQPseudo_VLD1q64HighQPseudo_UPD_VLD1q64LowQPseudo_UPD_VLD1q8HighQPseudo_VLD1q8HighQPseudo_UPD_VLD1q8LowQPseudo_UPD = 1041, |
| VLD1d16TPseudo_VLD1d16TPseudoWB_fixed_VLD1d16TPseudoWB_register_VLD1d32TPseudo_VLD1d32TPseudoWB_fixed_VLD1d32TPseudoWB_register_VLD1d8TPseudo_VLD1d8TPseudoWB_fixed_VLD1d8TPseudoWB_register_VLD1q16HighTPseudo_VLD1q16HighTPseudo_UPD_VLD1q16LowTPseudo_UPD_VLD1q32HighTPseudo_VLD1q32HighTPseudo_UPD_VLD1q32LowTPseudo_UPD_VLD1q64HighTPseudo_VLD1q64HighTPseudo_UPD_VLD1q64LowTPseudo_UPD_VLD1q8HighTPseudo_VLD1q8HighTPseudo_UPD_VLD1q8LowTPseudo_UPD = 1042, |
| VLD2DUPq16EvenPseudo_VLD2DUPq16OddPseudo_VLD2DUPq16OddPseudoWB_fixed_VLD2DUPq16OddPseudoWB_register_VLD2DUPq32EvenPseudo_VLD2DUPq32OddPseudo_VLD2DUPq32OddPseudoWB_fixed_VLD2DUPq32OddPseudoWB_register_VLD2DUPq8EvenPseudo_VLD2DUPq8OddPseudo_VLD2DUPq8OddPseudoWB_fixed_VLD2DUPq8OddPseudoWB_register = 1043, |
| VLD3DUPq16EvenPseudo_VLD3DUPq16OddPseudo_VLD3DUPq32EvenPseudo_VLD3DUPq32OddPseudo_VLD3DUPq8EvenPseudo_VLD3DUPq8OddPseudo = 1044, |
| VLD3DUPq16OddPseudo_UPD_VLD3DUPq32OddPseudo_UPD_VLD3DUPq8OddPseudo_UPD = 1045, |
| VLD4DUPq16EvenPseudo_VLD4DUPq16OddPseudo_VLD4DUPq32EvenPseudo_VLD4DUPq32OddPseudo_VLD4DUPq8EvenPseudo_VLD4DUPq8OddPseudo = 1046, |
| VLD4DUPq16OddPseudo_UPD_VLD4DUPq32OddPseudo_UPD_VLD4DUPq8OddPseudo_UPD = 1047, |
| VST1d16TPseudo_VST1d32TPseudo_VST1d8TPseudo_VST1q16HighTPseudo_VST1q16HighTPseudo_UPD_VST1q16LowTPseudo_UPD_VST1q32HighTPseudo_VST1q32HighTPseudo_UPD_VST1q32LowTPseudo_UPD_VST1q64HighTPseudo_VST1q64HighTPseudo_UPD_VST1q64LowTPseudo_UPD_VST1q8HighTPseudo_VST1q8HighTPseudo_UPD_VST1q8LowTPseudo_UPD = 1048, |
| VST1d16TPseudoWB_fixed_VST1d16TPseudoWB_register_VST1d32TPseudoWB_fixed_VST1d32TPseudoWB_register_VST1d8TPseudoWB_fixed_VST1d8TPseudoWB_register = 1049, |
| VST1q16HighQPseudo_VST1q16HighQPseudo_UPD_VST1q16LowQPseudo_UPD_VST1q32HighQPseudo_VST1q32HighQPseudo_UPD_VST1q32LowQPseudo_UPD_VST1q64HighQPseudo_VST1q64HighQPseudo_UPD_VST1q64LowQPseudo_UPD_VST1q8HighQPseudo_VST1q8HighQPseudo_UPD_VST1q8LowQPseudo_UPD = 1050, |
| VMOVD0 = 1051, |
| t2CPS1p_t2CPS2p_t2CPS3p_t2SG_t2TT_t2TTA_t2TTAT_t2TTT = 1052, |
| t2DBG = 1053, |
| t2SUBS_PC_LR = 1054, |
| COPY_TO_REGCLASS = 1055, |
| COPY_STRUCT_BYVAL_I32 = 1056, |
| t2CSEL_t2CSINC_t2CSINV_t2CSNEG = 1057, |
| t2ADDrr_t2ADDSrr_t2SBCrr = 1058, |
| t2ASRri_t2LSLri_t2LSRri = 1059, |
| t2ASRrr_t2LSLrr_t2LSRrr_t2RORrr = 1060, |
| t2CMNzrr = 1061, |
| t2CMPri = 1062, |
| t2CMPrr = 1063, |
| t2ORRrr = 1064, |
| t2REV_t2REV16_t2REVSH = 1065, |
| t2RSBri_t2RSBSri = 1066, |
| t2RSBrr_t2SUBSrr_t2SUBrr = 1067, |
| t2TEQrr_t2TSTrr = 1068, |
| t2STRi12 = 1069, |
| t2STRBi12_t2STRHi12 = 1070, |
| t2STMIA_UPD_t2STMDB_UPD = 1071, |
| t2SETPAN_tHLT_tSETEND = 1072, |
| tADC_tADDhirr_tADDrSP_tADDrr_tADDspr_tPICADD_tSBC_tSUBrr = 1073, |
| tADDrSPi_tADDspi_tADR_tRSB_tSUBspi = 1074, |
| tAND_tBIC_tEOR_tORR = 1075, |
| tASRri_tLSLri_tLSRri = 1076, |
| tCBNZ_tCBZ = 1077, |
| tCMNz_tCMPhir_tCMPr = 1078, |
| tCMPi8 = 1079, |
| tCPS_tHINT = 1080, |
| tMOVSr = 1081, |
| tSTRBi_tSTRHi = 1082, |
| tSTRi_tSTRspi = 1083, |
| tSVC_tTRAP = 1084, |
| tTST = 1085, |
| tUDF = 1086, |
| tB_tBX_tBXNS_tBcc = 1087, |
| tBLXNSr_tBLXr = 1088, |
| t2DMB_t2DSB_t2ISB = 1089, |
| t2MCR_t2MCR2_t2MCRR_t2MCRR2_t2MRC_t2MRC2 = 1090, |
| t2MOVSsi = 1091, |
| t2MOVSsr = 1092, |
| t2MUL = 1093, |
| t2SMMLA_t2SMMLAR_t2SMMLS_t2SMMLSR = 1094, |
| t2UXTAB_t2UXTAH = 1095, |
| t2UXTAB16 = 1096, |
| MVE_SQRSHR_MVE_SQSHL_MVE_SRSHR_MVE_UQRSHL_MVE_UQSHL_MVE_URSHR = 1097, |
| MVE_ASRLi_MVE_ASRLr_MVE_LSLLi_MVE_LSLLr_MVE_LSRL_MVE_SQRSHRL_MVE_SQSHLL_MVE_SRSHRL_MVE_UQRSHLL_MVE_UQSHLL_MVE_URSHRL = 1098, |
| t2CLRM = 1099, |
| t2LDRBi12_t2LDRHi12 = 1100, |
| t2LDRi12 = 1101, |
| t2LDMDB_t2LDMIA = 1102, |
| t2LDMDB_UPD_t2LDMIA_UPD = 1103, |
| tADDi3_tADDi8_tSUBi3_tSUBi8 = 1104, |
| t2ADDSri_t2ADDri = 1105, |
| t2SUBSri_t2SUBri = 1106, |
| t2LoopDec = 1107, |
| MVE_VLDRBS16_MVE_VLDRBS32_MVE_VLDRBU16_MVE_VLDRBU32_MVE_VLDRBU8_MVE_VLDRHS32_MVE_VLDRHU16_MVE_VLDRHU32_MVE_VLDRWU32 = 1108, |
| MVE_VLDRBS16_post_MVE_VLDRBS16_pre_MVE_VLDRBS32_post_MVE_VLDRBS32_pre_MVE_VLDRBU16_post_MVE_VLDRBU16_pre_MVE_VLDRBU32_post_MVE_VLDRBU32_pre_MVE_VLDRBU8_post_MVE_VLDRBU8_pre_MVE_VLDRHS32_post_MVE_VLDRHS32_pre_MVE_VLDRHU16_post_MVE_VLDRHU16_pre_MVE_VLDRHU32_post_MVE_VLDRHU32_pre_MVE_VLDRWU32_post_MVE_VLDRWU32_pre = 1109, |
| MVE_VLDRBS16_rq_MVE_VLDRBS32_rq_MVE_VLDRBU16_rq_MVE_VLDRBU32_rq_MVE_VLDRBU8_rq_MVE_VLDRDU64_rq_MVE_VLDRDU64_rq_u_MVE_VLDRHS32_rq_MVE_VLDRHS32_rq_u_MVE_VLDRHU16_rq_MVE_VLDRHU16_rq_u_MVE_VLDRHU32_rq_MVE_VLDRHU32_rq_u_MVE_VLDRWU32_rq_MVE_VLDRWU32_rq_u = 1110, |
| MVE_VLDRDU64_qi_MVE_VLDRWU32_qi = 1111, |
| MVE_VLDRDU64_qi_pre_MVE_VLDRWU32_qi_pre = 1112, |
| MVE_VLD20_16_MVE_VLD20_32_MVE_VLD20_8_MVE_VLD21_16_MVE_VLD21_32_MVE_VLD21_8_MVE_VLD40_16_MVE_VLD40_32_MVE_VLD40_8_MVE_VLD41_16_MVE_VLD41_32_MVE_VLD41_8_MVE_VLD42_16_MVE_VLD42_32_MVE_VLD42_8_MVE_VLD43_16_MVE_VLD43_32_MVE_VLD43_8 = 1113, |
| MVE_VLD20_16_wb_MVE_VLD20_32_wb_MVE_VLD20_8_wb_MVE_VLD21_16_wb_MVE_VLD21_32_wb_MVE_VLD21_8_wb_MVE_VLD40_16_wb_MVE_VLD40_32_wb_MVE_VLD40_8_wb_MVE_VLD41_16_wb_MVE_VLD41_32_wb_MVE_VLD41_8_wb_MVE_VLD42_16_wb_MVE_VLD42_32_wb_MVE_VLD42_8_wb_MVE_VLD43_16_wb_MVE_VLD43_32_wb_MVE_VLD43_8_wb = 1114, |
| MVE_VSTRB16_MVE_VSTRB32_MVE_VSTRBU8_MVE_VSTRH32_MVE_VSTRHU16_MVE_VSTRWU32 = 1115, |
| MVE_VSTRB16_post_MVE_VSTRB16_pre_MVE_VSTRB32_post_MVE_VSTRB32_pre_MVE_VSTRBU8_post_MVE_VSTRBU8_pre_MVE_VSTRH32_post_MVE_VSTRH32_pre_MVE_VSTRHU16_post_MVE_VSTRHU16_pre_MVE_VSTRWU32_post_MVE_VSTRWU32_pre = 1116, |
| MVE_VSTRB16_rq_MVE_VSTRB32_rq_MVE_VSTRB8_rq_MVE_VSTRD64_rq_MVE_VSTRD64_rq_u_MVE_VSTRH16_rq_MVE_VSTRH16_rq_u_MVE_VSTRH32_rq_MVE_VSTRH32_rq_u_MVE_VSTRW32_rq_MVE_VSTRW32_rq_u = 1117, |
| MVE_VSTRD64_qi_MVE_VSTRD64_qi_pre_MVE_VSTRW32_qi_MVE_VSTRW32_qi_pre = 1118, |
| MVE_VST20_16_MVE_VST20_16_wb_MVE_VST20_32_MVE_VST20_32_wb_MVE_VST20_8_MVE_VST20_8_wb_MVE_VST21_16_MVE_VST21_16_wb_MVE_VST21_32_MVE_VST21_32_wb_MVE_VST21_8_MVE_VST21_8_wb_MVE_VST40_16_MVE_VST40_16_wb_MVE_VST40_32_MVE_VST40_32_wb_MVE_VST40_8_MVE_VST40_8_wb_MVE_VST41_16_MVE_VST41_16_wb_MVE_VST41_32_MVE_VST41_32_wb_MVE_VST41_8_MVE_VST41_8_wb_MVE_VST42_16_MVE_VST42_16_wb_MVE_VST42_32_MVE_VST42_32_wb_MVE_VST42_8_MVE_VST42_8_wb_MVE_VST43_16_MVE_VST43_16_wb_MVE_VST43_32_MVE_VST43_32_wb_MVE_VST43_8_MVE_VST43_8_wb = 1119, |
| MVE_VABAVs16_MVE_VABAVs32_MVE_VABAVs8_MVE_VABAVu16_MVE_VABAVu32_MVE_VABAVu8 = 1120, |
| MVE_VABDs16_MVE_VABDs32_MVE_VABDs8_MVE_VABDu16_MVE_VABDu32_MVE_VABDu8 = 1121, |
| MVE_VABSs16_MVE_VABSs32_MVE_VABSs8 = 1122, |
| MVE_VADC_MVE_VADCI = 1123, |
| MVE_VADD_qr_i16_MVE_VADD_qr_i32_MVE_VADD_qr_i8_MVE_VADDi16_MVE_VADDi32_MVE_VADDi8 = 1124, |
| MVE_VAND = 1125, |
| MVE_VBIC_MVE_VBICimmi16_MVE_VBICimmi32 = 1126, |
| MVE_VBRSR16_MVE_VBRSR32_MVE_VBRSR8 = 1127, |
| MVE_VCADDi16_MVE_VCADDi32_MVE_VCADDi8 = 1128, |
| MVE_VCLSs16_MVE_VCLSs32_MVE_VCLSs8 = 1129, |
| MVE_VCLZs16_MVE_VCLZs32_MVE_VCLZs8 = 1130, |
| MVE_VDDUPu16_MVE_VDDUPu32_MVE_VDDUPu8_MVE_VDUP16_MVE_VDUP32_MVE_VDUP8_MVE_VDWDUPu16_MVE_VDWDUPu32_MVE_VDWDUPu8_MVE_VIDUPu16_MVE_VIDUPu32_MVE_VIDUPu8_MVE_VIWDUPu16_MVE_VIWDUPu32_MVE_VIWDUPu8 = 1131, |
| MVE_VEOR = 1132, |
| MVE_VHADD_qr_s16_MVE_VHADD_qr_s32_MVE_VHADD_qr_s8_MVE_VHADD_qr_u16_MVE_VHADD_qr_u32_MVE_VHADD_qr_u8_MVE_VHADDs16_MVE_VHADDs32_MVE_VHADDs8_MVE_VHADDu16_MVE_VHADDu32_MVE_VHADDu8 = 1133, |
| MVE_VHCADDs16_MVE_VHCADDs32_MVE_VHCADDs8 = 1134, |
| MVE_VHSUB_qr_s16_MVE_VHSUB_qr_s32_MVE_VHSUB_qr_s8_MVE_VHSUB_qr_u16_MVE_VHSUB_qr_u32_MVE_VHSUB_qr_u8_MVE_VHSUBs16_MVE_VHSUBs32_MVE_VHSUBs8_MVE_VHSUBu16_MVE_VHSUBu32_MVE_VHSUBu8 = 1135, |
| MVE_VMAXAs16_MVE_VMAXAs32_MVE_VMAXAs8_MVE_VMAXs16_MVE_VMAXs32_MVE_VMAXs8_MVE_VMAXu16_MVE_VMAXu32_MVE_VMAXu8_MVE_VMINAs16_MVE_VMINAs32_MVE_VMINAs8_MVE_VMINs16_MVE_VMINs32_MVE_VMINs8_MVE_VMINu16_MVE_VMINu32_MVE_VMINu8 = 1136, |
| MVE_VMAXAVs8_MVE_VMAXVs8_MVE_VMAXVu8_MVE_VMINAVs8_MVE_VMINVs8_MVE_VMINVu8 = 1137, |
| MVE_VMAXAVs16_MVE_VMAXVs16_MVE_VMAXVu16_MVE_VMINAVs16_MVE_VMINVs16_MVE_VMINVu16 = 1138, |
| MVE_VMAXAVs32_MVE_VMAXVs32_MVE_VMAXVu32_MVE_VMINAVs32_MVE_VMINVs32_MVE_VMINVu32 = 1139, |
| MVE_VMOVNi16bh_MVE_VMOVNi16th_MVE_VMOVNi32bh_MVE_VMOVNi32th = 1140, |
| MVE_VMOVLs16bh_MVE_VMOVLs16th_MVE_VMOVLs8bh_MVE_VMOVLs8th_MVE_VMOVLu16bh_MVE_VMOVLu16th_MVE_VMOVLu8bh_MVE_VMOVLu8th = 1141, |
| MVE_VMULLBp16_MVE_VMULLBp8_MVE_VMULLTp16_MVE_VMULLTp8 = 1142, |
| MVE_VMVN_MVE_VMVNimmi16_MVE_VMVNimmi32 = 1143, |
| MVE_VNEGs16_MVE_VNEGs32_MVE_VNEGs8 = 1144, |
| MVE_VORN = 1145, |
| MVE_VORR_MVE_VORRimmi16_MVE_VORRimmi32 = 1146, |
| MVE_VPSEL = 1147, |
| MQPRCopy = 1148, |
| MVE_VQABSs16_MVE_VQABSs32_MVE_VQABSs8 = 1149, |
| MVE_VQADD_qr_s16_MVE_VQADD_qr_s32_MVE_VQADD_qr_s8_MVE_VQADD_qr_u16_MVE_VQADD_qr_u32_MVE_VQADD_qr_u8_MVE_VQADDs16_MVE_VQADDs32_MVE_VQADDs8_MVE_VQADDu16_MVE_VQADDu32_MVE_VQADDu8 = 1150, |
| MVE_VQMOVNs16bh_MVE_VQMOVNs16th_MVE_VQMOVNs32bh_MVE_VQMOVNs32th_MVE_VQMOVNu16bh_MVE_VQMOVNu16th_MVE_VQMOVNu32bh_MVE_VQMOVNu32th_MVE_VQMOVUNs16bh_MVE_VQMOVUNs16th_MVE_VQMOVUNs32bh_MVE_VQMOVUNs32th = 1151, |
| MVE_VQNEGs16_MVE_VQNEGs32_MVE_VQNEGs8 = 1152, |
| MVE_VSHLC_MVE_VSHLL_imms16bh_MVE_VSHLL_imms16th_MVE_VSHLL_imms8bh_MVE_VSHLL_imms8th_MVE_VSHLL_immu16bh_MVE_VSHLL_immu16th_MVE_VSHLL_immu8bh_MVE_VSHLL_immu8th_MVE_VSHLL_lws16bh_MVE_VSHLL_lws16th_MVE_VSHLL_lws8bh_MVE_VSHLL_lws8th_MVE_VSHLL_lwu16bh_MVE_VSHLL_lwu16th_MVE_VSHLL_lwu8bh_MVE_VSHLL_lwu8th_MVE_VSHL_by_vecs16_MVE_VSHL_by_vecs32_MVE_VSHL_by_vecs8_MVE_VSHL_by_vecu16_MVE_VSHL_by_vecu32_MVE_VSHL_by_vecu8_MVE_VSHL_immi16_MVE_VSHL_immi32_MVE_VSHL_immi8_MVE_VSHL_qrs16_MVE_VSHL_qrs32_MVE_VSHL_qrs8_MVE_VSHL_qru16_MVE_VSHL_qru32_MVE_VSHL_qru8 = 1153, |
| MVE_VQSHLU_imms16_MVE_VQSHLU_imms32_MVE_VQSHLU_imms8_MVE_VQSHL_by_vecs16_MVE_VQSHL_by_vecs32_MVE_VQSHL_by_vecs8_MVE_VQSHL_by_vecu16_MVE_VQSHL_by_vecu32_MVE_VQSHL_by_vecu8_MVE_VQSHL_qrs16_MVE_VQSHL_qrs32_MVE_VQSHL_qrs8_MVE_VQSHL_qru16_MVE_VQSHL_qru32_MVE_VQSHL_qru8_MVE_VQSHLimms16_MVE_VQSHLimms32_MVE_VQSHLimms8_MVE_VQSHLimmu16_MVE_VQSHLimmu32_MVE_VQSHLimmu8_MVE_VRSHL_by_vecs16_MVE_VRSHL_by_vecs32_MVE_VRSHL_by_vecs8_MVE_VRSHL_by_vecu16_MVE_VRSHL_by_vecu32_MVE_VRSHL_by_vecu8_MVE_VRSHL_qrs16_MVE_VRSHL_qrs32_MVE_VRSHL_qrs8_MVE_VRSHL_qru16_MVE_VRSHL_qru32_MVE_VRSHL_qru8 = 1154, |
| MVE_VQRSHL_by_vecs16_MVE_VQRSHL_by_vecs32_MVE_VQRSHL_by_vecs8_MVE_VQRSHL_by_vecu16_MVE_VQRSHL_by_vecu32_MVE_VQRSHL_by_vecu8_MVE_VQRSHL_qrs16_MVE_VQRSHL_qrs32_MVE_VQRSHL_qrs8_MVE_VQRSHL_qru16_MVE_VQRSHL_qru32_MVE_VQRSHL_qru8 = 1155, |
| MVE_VQRSHRNbhs16_MVE_VQRSHRNbhs32_MVE_VQRSHRNbhu16_MVE_VQRSHRNbhu32_MVE_VQRSHRNths16_MVE_VQRSHRNths32_MVE_VQRSHRNthu16_MVE_VQRSHRNthu32_MVE_VQRSHRUNs16bh_MVE_VQRSHRUNs16th_MVE_VQRSHRUNs32bh_MVE_VQRSHRUNs32th_MVE_VQSHRNbhs16_MVE_VQSHRNbhs32_MVE_VQSHRNbhu16_MVE_VQSHRNbhu32_MVE_VQSHRNths16_MVE_VQSHRNths32_MVE_VQSHRNthu16_MVE_VQSHRNthu32_MVE_VQSHRUNs16bh_MVE_VQSHRUNs16th_MVE_VQSHRUNs32bh_MVE_VQSHRUNs32th_MVE_VRSHRNi16bh_MVE_VRSHRNi16th_MVE_VRSHRNi32bh_MVE_VRSHRNi32th_MVE_VSHRNi16bh_MVE_VSHRNi16th_MVE_VSHRNi32bh_MVE_VSHRNi32th = 1156, |
| MVE_VSHR_imms16_MVE_VSHR_imms32_MVE_VSHR_imms8_MVE_VSHR_immu16_MVE_VSHR_immu32_MVE_VSHR_immu8 = 1157, |
| MVE_VRSHR_imms16_MVE_VRSHR_imms32_MVE_VRSHR_imms8_MVE_VRSHR_immu16_MVE_VRSHR_immu32_MVE_VRSHR_immu8 = 1158, |
| MVE_VQSUB_qr_s16_MVE_VQSUB_qr_s32_MVE_VQSUB_qr_s8_MVE_VQSUB_qr_u16_MVE_VQSUB_qr_u32_MVE_VQSUB_qr_u8_MVE_VQSUBs16_MVE_VQSUBs32_MVE_VQSUBs8_MVE_VQSUBu16_MVE_VQSUBu32_MVE_VQSUBu8 = 1159, |
| MVE_VREV16_8_MVE_VREV32_16_MVE_VREV32_8_MVE_VREV64_16_MVE_VREV64_32_MVE_VREV64_8 = 1160, |
| MVE_VRHADDs16_MVE_VRHADDs32_MVE_VRHADDs8_MVE_VRHADDu16_MVE_VRHADDu32_MVE_VRHADDu8 = 1161, |
| MVE_VSBC_MVE_VSBCI = 1162, |
| MVE_VSLIimm16_MVE_VSLIimm32_MVE_VSLIimm8 = 1163, |
| MVE_VSRIimm16_MVE_VSRIimm32_MVE_VSRIimm8 = 1164, |
| MVE_VSUB_qr_i16_MVE_VSUB_qr_i32_MVE_VSUB_qr_i8_MVE_VSUBi16_MVE_VSUBi32_MVE_VSUBi8 = 1165, |
| MVE_VABDf16_MVE_VABDf32 = 1166, |
| MVE_VABSf16_MVE_VABSf32 = 1167, |
| MVE_VADDf16_MVE_VADDf32 = 1168, |
| MVE_VADD_qr_f16_MVE_VADD_qr_f32 = 1169, |
| MVE_VADDLVs32acc_MVE_VADDLVs32no_acc_MVE_VADDLVu32acc_MVE_VADDLVu32no_acc = 1170, |
| MVE_VADDVs16acc_MVE_VADDVs16no_acc_MVE_VADDVs32acc_MVE_VADDVs32no_acc_MVE_VADDVs8acc_MVE_VADDVs8no_acc_MVE_VADDVu16acc_MVE_VADDVu16no_acc_MVE_VADDVu32acc_MVE_VADDVu32no_acc_MVE_VADDVu8acc_MVE_VADDVu8no_acc = 1171, |
| MVE_VCADDf16_MVE_VCADDf32 = 1172, |
| MVE_VCMLAf16_MVE_VCMLAf32 = 1173, |
| MVE_VCMULf16_MVE_VCMULf32 = 1174, |
| MVE_VCMPi16_MVE_VCMPi16r_MVE_VCMPi32_MVE_VCMPi32r_MVE_VCMPi8_MVE_VCMPi8r_MVE_VCMPs16_MVE_VCMPs16r_MVE_VCMPs32_MVE_VCMPs32r_MVE_VCMPs8_MVE_VCMPs8r_MVE_VCMPu16_MVE_VCMPu16r_MVE_VCMPu32_MVE_VCMPu32r_MVE_VCMPu8_MVE_VCMPu8r_MVE_VPTv16i8_MVE_VPTv16i8r_MVE_VPTv16s8_MVE_VPTv16s8r_MVE_VPTv16u8_MVE_VPTv16u8r_MVE_VPTv4i32_MVE_VPTv4i32r_MVE_VPTv4s32_MVE_VPTv4s32r_MVE_VPTv4u32_MVE_VPTv4u32r_MVE_VPTv8i16_MVE_VPTv8i16r_MVE_VPTv8s16_MVE_VPTv8s16r_MVE_VPTv8u16_MVE_VPTv8u16r = 1175, |
| MVE_VCMPf16_MVE_VCMPf16r_MVE_VCMPf32_MVE_VCMPf32r_MVE_VPTv4f32_MVE_VPTv4f32r_MVE_VPTv8f16_MVE_VPTv8f16r = 1176, |
| MVE_VCVTf16s16_fix_MVE_VCVTf16s16n_MVE_VCVTf16u16_fix_MVE_VCVTf16u16n = 1177, |
| MVE_VCVTf32s32_fix_MVE_VCVTf32s32n_MVE_VCVTf32u32_fix_MVE_VCVTf32u32n = 1178, |
| MVE_VCVTs16f16_fix_MVE_VCVTs16f16a_MVE_VCVTs16f16m_MVE_VCVTs16f16n_MVE_VCVTs16f16p_MVE_VCVTs16f16z_MVE_VCVTu16f16_fix_MVE_VCVTu16f16a_MVE_VCVTu16f16m_MVE_VCVTu16f16n_MVE_VCVTu16f16p_MVE_VCVTu16f16z = 1179, |
| MVE_VCVTs32f32_fix_MVE_VCVTs32f32a_MVE_VCVTs32f32m_MVE_VCVTs32f32n_MVE_VCVTs32f32p_MVE_VCVTs32f32z_MVE_VCVTu32f32_fix_MVE_VCVTu32f32a_MVE_VCVTu32f32m_MVE_VCVTu32f32n_MVE_VCVTu32f32p_MVE_VCVTu32f32z = 1180, |
| MVE_VCVTf16f32bh_MVE_VCVTf16f32th = 1181, |
| MVE_VCVTf32f16bh_MVE_VCVTf32f16th = 1182, |
| MVE_VFMA_qr_Sf16_MVE_VFMA_qr_Sf32_MVE_VFMA_qr_f16_MVE_VFMA_qr_f32_MVE_VFMAf16_MVE_VFMAf32_MVE_VFMSf16_MVE_VFMSf32 = 1183, |
| MVE_VMAXNMAVf16_MVE_VMAXNMAVf32_MVE_VMAXNMAf16_MVE_VMAXNMAf32_MVE_VMAXNMVf16_MVE_VMAXNMVf32_MVE_VMAXNMf16_MVE_VMAXNMf32_MVE_VMINNMAVf16_MVE_VMINNMAVf32_MVE_VMINNMAf16_MVE_VMINNMAf32_MVE_VMINNMVf16_MVE_VMINNMVf32_MVE_VMINNMf16_MVE_VMINNMf32 = 1184, |
| MVE_VMOV_from_lane_32_MVE_VMOV_from_lane_s16_MVE_VMOV_from_lane_s8_MVE_VMOV_from_lane_u16_MVE_VMOV_from_lane_u8 = 1185, |
| MVE_VMOV_rr_q = 1186, |
| MVE_VMOVimmf32_MVE_VMOVimmi16_MVE_VMOVimmi32_MVE_VMOVimmi64_MVE_VMOVimmi8 = 1187, |
| MVE_VMUL_qr_f16_MVE_VMUL_qr_f32_MVE_VMUL_qr_i16_MVE_VMUL_qr_i32_MVE_VMUL_qr_i8_MVE_VMULf16_MVE_VMULf32_MVE_VMULi16_MVE_VMULi32_MVE_VMULi8 = 1188, |
| MVE_VMULHs16_MVE_VMULHs32_MVE_VMULHs8_MVE_VMULHu16_MVE_VMULHu32_MVE_VMULHu8_MVE_VQDMULH_qr_s16_MVE_VQDMULH_qr_s32_MVE_VQDMULH_qr_s8_MVE_VQDMULHi16_MVE_VQDMULHi32_MVE_VQDMULHi8_MVE_VQRDMULH_qr_s16_MVE_VQRDMULH_qr_s32_MVE_VQRDMULH_qr_s8_MVE_VQRDMULHi16_MVE_VQRDMULHi32_MVE_VQRDMULHi8_MVE_VRMULHs16_MVE_VRMULHs32_MVE_VRMULHs8_MVE_VRMULHu16_MVE_VRMULHu32_MVE_VRMULHu8 = 1189, |
| MVE_VMULLBs16_MVE_VMULLBs32_MVE_VMULLBs8_MVE_VMULLBu16_MVE_VMULLBu32_MVE_VMULLBu8_MVE_VMULLTs16_MVE_VMULLTs32_MVE_VMULLTs8_MVE_VMULLTu16_MVE_VMULLTu32_MVE_VMULLTu8_MVE_VQDMULLs16bh_MVE_VQDMULLs16th_MVE_VQDMULLs32bh_MVE_VQDMULLs32th = 1190, |
| MVE_VQDMULL_qr_s16bh_MVE_VQDMULL_qr_s16th_MVE_VQDMULL_qr_s32bh_MVE_VQDMULL_qr_s32th = 1191, |
| MVE_VMLADAVas16_MVE_VMLADAVas32_MVE_VMLADAVas8_MVE_VMLADAVau16_MVE_VMLADAVau32_MVE_VMLADAVau8_MVE_VMLADAVaxs16_MVE_VMLADAVaxs32_MVE_VMLADAVaxs8_MVE_VMLADAVs16_MVE_VMLADAVs32_MVE_VMLADAVs8_MVE_VMLADAVu16_MVE_VMLADAVu32_MVE_VMLADAVu8_MVE_VMLADAVxs16_MVE_VMLADAVxs32_MVE_VMLADAVxs8_MVE_VMLAS_qr_i16_MVE_VMLAS_qr_i32_MVE_VMLAS_qr_i8_MVE_VMLA_qr_i16_MVE_VMLA_qr_i32_MVE_VMLA_qr_i8_MVE_VMLSDAVas16_MVE_VMLSDAVas32_MVE_VMLSDAVas8_MVE_VMLSDAVaxs16_MVE_VMLSDAVaxs32_MVE_VMLSDAVaxs8_MVE_VMLSDAVs16_MVE_VMLSDAVs32_MVE_VMLSDAVs8_MVE_VMLSDAVxs16_MVE_VMLSDAVxs32_MVE_VMLSDAVxs8_MVE_VQDMLADHXs16_MVE_VQDMLADHXs32_MVE_VQDMLADHXs8_MVE_VQDMLADHs16_MVE_VQDMLADHs32_MVE_VQDMLADHs8_MVE_VQDMLAH_qrs16_MVE_VQDMLAH_qrs32_MVE_VQDMLAH_qrs8_MVE_VQDMLASH_qrs16_MVE_VQDMLASH_qrs32_MVE_VQDMLASH_qrs8_MVE_VQDMLSDHXs16_MVE_VQDMLSDHXs32_MVE_VQDMLSDHXs8_MVE_VQDMLSDHs16_MVE_VQDMLSDHs32_MVE_VQDMLSDHs8_MVE_VQRDMLADHXs16_MVE_VQRDMLADHXs32_MVE_VQRDMLADHXs8_MVE_VQRDMLADHs16_MVE_VQRDMLADHs32_MVE_VQRDMLADHs8_MVE_VQRDMLAH_qrs16_MVE_VQRDMLAH_qrs32_MVE_VQRDMLAH_qrs8_MVE_VQRDMLASH_qrs16_MVE_VQRDMLASH_qrs32_MVE_VQRDMLASH_qrs8_MVE_VQRDMLSDHXs16_MVE_VQRDMLSDHXs32_MVE_VQRDMLSDHXs8_MVE_VQRDMLSDHs16_MVE_VQRDMLSDHs32_MVE_VQRDMLSDHs8 = 1192, |
| MVE_VMLALDAVas16_MVE_VMLALDAVas32_MVE_VMLALDAVau16_MVE_VMLALDAVau32_MVE_VMLALDAVaxs16_MVE_VMLALDAVaxs32_MVE_VMLALDAVs16_MVE_VMLALDAVs32_MVE_VMLALDAVu16_MVE_VMLALDAVu32_MVE_VMLALDAVxs16_MVE_VMLALDAVxs32_MVE_VMLSLDAVas16_MVE_VMLSLDAVas32_MVE_VMLSLDAVaxs16_MVE_VMLSLDAVaxs32_MVE_VMLSLDAVs16_MVE_VMLSLDAVs32_MVE_VMLSLDAVxs16_MVE_VMLSLDAVxs32_MVE_VRMLALDAVHas32_MVE_VRMLALDAVHau32_MVE_VRMLALDAVHaxs32_MVE_VRMLALDAVHs32_MVE_VRMLALDAVHu32_MVE_VRMLALDAVHxs32_MVE_VRMLSLDAVHas32_MVE_VRMLSLDAVHaxs32_MVE_VRMLSLDAVHs32_MVE_VRMLSLDAVHxs32 = 1193, |
| MVE_VNEGf16_MVE_VNEGf32 = 1194, |
| MVE_VRINTf16A_MVE_VRINTf16M_MVE_VRINTf16N_MVE_VRINTf16P_MVE_VRINTf16X_MVE_VRINTf16Z_MVE_VRINTf32A_MVE_VRINTf32M_MVE_VRINTf32N_MVE_VRINTf32P_MVE_VRINTf32X_MVE_VRINTf32Z = 1195, |
| MVE_VSUBf16_MVE_VSUBf32 = 1196, |
| MVE_VSUB_qr_f16_MVE_VSUB_qr_f32 = 1197, |
| MVE_VMOV_to_lane_16_MVE_VMOV_to_lane_32_MVE_VMOV_to_lane_8_MVE_VMOV_q_rr = 1198, |
| MVE_VCTP16_MVE_VCTP32_MVE_VCTP64_MVE_VCTP8 = 1199, |
| MVE_VPNOT = 1200, |
| MVE_VPST = 1201, |
| VCVTASD_VCVTASH_VCVTASS_VCVTAUD_VCVTAUH_VCVTAUS_VCVTMSD_VCVTMSH_VCVTMSS_VCVTMUD_VCVTMUH_VCVTMUS_VCVTNSD_VCVTNSH_VCVTNSS_VCVTNUD_VCVTNUH_VCVTNUS_VCVTPSD_VCVTPSH_VCVTPSS_VCVTPUD_VCVTPUH_VCVTPUS = 1202, |
| VDIVH = 1203, |
| VFMAH_VFMSH = 1204, |
| VFP_VMAXNMD_VFP_VMAXNMH_VFP_VMAXNMS_VFP_VMINNMD_VFP_VMINNMH_VFP_VMINNMS = 1205, |
| VMOVH = 1206, |
| VMOVHR = 1207, |
| VMOVD = 1208, |
| VMOVS = 1209, |
| VMOVRH = 1210, |
| tSVC = 1211, |
| t2HVC = 1212, |
| t2SMC_ERET = 1213, |
| tHINT = 1214, |
| BUNDLE = 1215, |
| t2LDRBpcrel_t2LDRHpcrel = 1216, |
| t2LDRBpci_t2LDRHpci = 1217, |
| t2LDRSBpci_t2LDRSHpci = 1218, |
| t2LDREX = 1219, |
| t2LDREXB_t2LDREXH = 1220, |
| t2STREX_t2STREXB_t2STREXH = 1221, |
| t2LDRpci = 1222, |
| t2PLDpci_t2PLIpci = 1223, |
| tLDRpci = 1224, |
| t2PLDWi12_t2PLDWi8_t2PLDi12_t2PLDi8_t2PLIi12_t2PLIi8 = 1225, |
| t2PLDs_t2PLIs = 1226, |
| t2TBB_JT_t2TBH_JT = 1227, |
| t2TBB_t2TBH = 1228, |
| t2RSBSrs_t2SUBrs = 1229, |
| t2SUBSrs = 1230, |
| t2BICrs_t2EORrs_t2ORRrs = 1231, |
| t2ORNrs = 1232, |
| t2CMNzrs = 1233, |
| t2CMPrs = 1234, |
| t2TEQrs_t2TSTrs = 1235, |
| t2RRX = 1236, |
| tLSLSri = 1237, |
| t2CLZ = 1238, |
| t2USAD8 = 1239, |
| t2RBIT = 1240, |
| t2PKHBT_t2PKHTB = 1241, |
| VCVTASS_VCVTAUS_VCVTMSS_VCVTMUS_VCVTNSS_VCVTNUS_VCVTPSS_VCVTPUS = 1242, |
| VFP_VMAXNMS_VFP_VMINNMS = 1243, |
| VRINTAS_VRINTMS_VRINTNS_VRINTPS_VRINTRS_VRINTXS_VRINTZS = 1244, |
| VCVTASD_VCVTAUD_VCVTMSD_VCVTMUD_VCVTNSD_VCVTNUD_VCVTPSD_VCVTPUD = 1245, |
| VCVTTHD = 1246, |
| VFP_VMAXNMD_VFP_VMINNMD = 1247, |
| VRINTAD_VRINTMD_VRINTND_VRINTPD_VRINTRD_VRINTXD_VRINTZD = 1248, |
| VCMPS = 1249, |
| VCMPD = 1250, |
| VSELEQS_VSELGES_VSELGTS_VSELVSS = 1251, |
| VSELEQD_VSELGED_VSELGTD_VSELVSD = 1252, |
| VMULD_VNMULD = 1253, |
| SCHED_LIST_END = 1254 |
| }; |
| } // end namespace Sched |
| } // end namespace ARM |
| } // end namespace llvm |
| #endif // GET_INSTRINFO_SCHED_ENUM |
| |
| #ifdef GET_INSTRINFO_MC_DESC |
| #undef GET_INSTRINFO_MC_DESC |
| namespace llvm { |
| |
| static const MCPhysReg ImplicitList1[] = { ARM::CPSR }; |
| static const MCPhysReg ImplicitList2[] = { ARM::SP, ARM::SP }; |
| static const MCPhysReg ImplicitList3[] = { ARM::SP, ARM::LR }; |
| static const MCPhysReg ImplicitList4[] = { ARM::R7, ARM::LR, ARM::SP }; |
| static const MCPhysReg ImplicitList5[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR, ARM::CPSR, ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 }; |
| static const MCPhysReg ImplicitList6[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR, ARM::CPSR }; |
| static const MCPhysReg ImplicitList7[] = { ARM::SP }; |
| static const MCPhysReg ImplicitList8[] = { ARM::SP, ARM::R0, ARM::R12, ARM::LR, ARM::CPSR }; |
| static const MCPhysReg ImplicitList9[] = { ARM::R4, ARM::R4, ARM::SP }; |
| static const MCPhysReg ImplicitList10[] = { ARM::CPSR, ARM::CPSR }; |
| static const MCPhysReg ImplicitList11[] = { ARM::LR }; |
| static const MCPhysReg ImplicitList12[] = { ARM::PC }; |
| static const MCPhysReg ImplicitList13[] = { ARM::FPSCR_NZCV, ARM::CPSR }; |
| static const MCPhysReg ImplicitList14[] = { ARM::VPR }; |
| static const MCPhysReg ImplicitList15[] = { ARM::FPSCR_NZCV }; |
| static const MCPhysReg ImplicitList16[] = { ARM::FPSCR }; |
| static const MCPhysReg ImplicitList17[] = { ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, ARM::VPR, ARM::FPSCR, ARM::FPSCR_NZCV }; |
| static const MCPhysReg ImplicitList18[] = { ARM::R12, ARM::LR, ARM::SP }; |
| static const MCPhysReg ImplicitList19[] = { ARM::ITSTATE }; |
| static const MCPhysReg ImplicitList20[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR, ARM::CPSR, ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 }; |
| static const MCPhysReg ImplicitList21[] = { ARM::LR, ARM::SP, ARM::R12 }; |
| static const MCPhysReg ImplicitList22[] = { ARM::R11, ARM::LR, ARM::SP }; |
| static const MCPhysReg ImplicitList23[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3, ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::R12, ARM::CPSR }; |
| |
| static const MCOperandInfo OperandInfo2[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo3[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; |
| static const MCOperandInfo OperandInfo4[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; |
| static const MCOperandInfo OperandInfo5[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; |
| static const MCOperandInfo OperandInfo6[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; |
| static const MCOperandInfo OperandInfo7[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo8[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; |
| static const MCOperandInfo OperandInfo9[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, }; |
| static const MCOperandInfo OperandInfo10[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; |
| static const MCOperandInfo OperandInfo11[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; |
| static const MCOperandInfo OperandInfo12[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo13[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; |
| static const MCOperandInfo OperandInfo14[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; |
| static const MCOperandInfo OperandInfo15[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo16[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo17[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, }; |
| static const MCOperandInfo OperandInfo18[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, }; |
| static const MCOperandInfo OperandInfo19[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, }; |
| static const MCOperandInfo OperandInfo20[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, }; |
| static const MCOperandInfo OperandInfo21[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo22[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, }; |
| static const MCOperandInfo OperandInfo23[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, }; |
| static const MCOperandInfo OperandInfo24[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, }; |
| static const MCOperandInfo OperandInfo25[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, }; |
| static const MCOperandInfo OperandInfo26[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; |
| static const MCOperandInfo OperandInfo27[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo28[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo29[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, }; |
| static const MCOperandInfo OperandInfo30[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, }; |
| static const MCOperandInfo OperandInfo31[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, }; |
| static const MCOperandInfo OperandInfo32[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo33[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, }; |
| static const MCOperandInfo OperandInfo34[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, }; |
| static const MCOperandInfo OperandInfo35[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, }; |
| static const MCOperandInfo OperandInfo36[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, }; |
| static const MCOperandInfo OperandInfo37[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, }; |
| static const MCOperandInfo OperandInfo38[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, }; |
| static const MCOperandInfo OperandInfo39[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, }; |
| static const MCOperandInfo OperandInfo40[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, }; |
| static const MCOperandInfo OperandInfo41[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo42[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, }; |
| static const MCOperandInfo OperandInfo43[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, }; |
| static const MCOperandInfo OperandInfo44[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, }; |
| static const MCOperandInfo OperandInfo45[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo46[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo47[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo48[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo49[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo50[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo51[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo52[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo53[] = { { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; |
| static const MCOperandInfo OperandInfo54[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; |
| static const MCOperandInfo OperandInfo55[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; |
| static const MCOperandInfo OperandInfo56[] = { { ARM::GPRnoipRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo57[] = { { ARM::GPRlrRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; |
| static const MCOperandInfo OperandInfo58[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo59[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; |
| static const MCOperandInfo OperandInfo60[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; |
| static const MCOperandInfo OperandInfo61[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; |
| static const MCOperandInfo OperandInfo62[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; |
| static const MCOperandInfo OperandInfo63[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo64[] = { { ARM::GPRPairRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo65[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; |
| static const MCOperandInfo OperandInfo66[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo67[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo68[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo69[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo70[] = { { ARM::GPRPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; |
| static const MCOperandInfo OperandInfo71[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; |
| static const MCOperandInfo OperandInfo72[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo73[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo74[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo75[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo76[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo77[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo78[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo79[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo80[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo81[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo82[] = { { ARM::MQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo83[] = { { ARM::MQQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo84[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo85[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo86[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo87[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo88[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo89[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo90[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo91[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo92[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo93[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo94[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo95[] = { { ARM::tcGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo96[] = { { ARM::tcGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; |
| static const MCOperandInfo OperandInfo97[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo98[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo99[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo100[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo101[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo102[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo103[] = { { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo104[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo105[] = { { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo106[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo107[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo108[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo109[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo110[] = { { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; |
| static const MCOperandInfo OperandInfo111[] = { { ARM::GPRlrRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo112[] = { { ARM::GPRlrRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo113[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo114[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; |
| static const MCOperandInfo OperandInfo115[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo116[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo117[] = { { ARM::GPRlrRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRlrRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo118[] = { { ARM::GPRlrRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRlrRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; |
| static const MCOperandInfo OperandInfo119[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo120[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo121[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo122[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo123[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo124[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo125[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo126[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo127[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo128[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo129[] = { { ARM::GPRlrRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; |
| static const MCOperandInfo OperandInfo130[] = { { ARM::GPRlrRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; |
| static const MCOperandInfo OperandInfo131[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo132[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo133[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; |
| static const MCOperandInfo OperandInfo134[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo135[] = { { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnoipRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo136[] = { { ARM::GPRlrRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; |
| static const MCOperandInfo OperandInfo137[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo138[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; |
| static const MCOperandInfo OperandInfo139[] = { { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo140[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo141[] = { { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo142[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo143[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo144[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo145[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo146[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo147[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo148[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo149[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo150[] = { { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo151[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo152[] = { { ARM::tGPRwithpcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; |
| static const MCOperandInfo OperandInfo153[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo154[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo155[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo156[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo157[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo158[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo159[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo160[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo161[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo162[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo163[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo164[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo165[] = { { ARM::GPRwithAPSR_NZCVnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo166[] = { { ARM::GPRwithAPSR_NZCVnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRwithAPSR_NZCVnospRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo167[] = { { ARM::GPRPairnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo168[] = { { ARM::GPRPairnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRPairnospRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo169[] = { { ARM::GPRwithAPSR_NZCVnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRwithAPSR_NZCVnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo170[] = { { ARM::GPRwithAPSR_NZCVnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRwithAPSR_NZCVnospRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::GPRwithAPSR_NZCVnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo171[] = { { ARM::GPRPairnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRwithAPSR_NZCVnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo172[] = { { ARM::GPRPairnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRPairnospRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::GPRwithAPSR_NZCVnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo173[] = { { ARM::GPRwithAPSR_NZCVnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRwithAPSR_NZCVnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRwithAPSR_NZCVnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo174[] = { { ARM::GPRwithAPSR_NZCVnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRwithAPSR_NZCVnospRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::GPRwithAPSR_NZCVnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRwithAPSR_NZCVnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo175[] = { { ARM::GPRPairnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRwithAPSR_NZCVnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRwithAPSR_NZCVnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo176[] = { { ARM::GPRPairnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRPairnospRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::GPRwithAPSR_NZCVnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRwithAPSR_NZCVnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo177[] = { { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo178[] = { { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo179[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, }; |
| static const MCOperandInfo OperandInfo180[] = { { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo181[] = { { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo182[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, MCOI_TIED_TO(0) }, }; |
| static const MCOperandInfo OperandInfo183[] = { { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo184[] = { { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo185[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, }; |
| static const MCOperandInfo OperandInfo186[] = { { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo187[] = { { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo188[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, MCOI_TIED_TO(0) }, }; |
| static const MCOperandInfo OperandInfo189[] = { { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo190[] = { { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo191[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, }; |
| static const MCOperandInfo OperandInfo192[] = { { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo193[] = { { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo194[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, MCOI_TIED_TO(0) }, }; |
| static const MCOperandInfo OperandInfo195[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo196[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo197[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo198[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo199[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo200[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo201[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo202[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo203[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo204[] = { { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo205[] = { { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo206[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo207[] = { { ARM::GPRPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo208[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; |
| static const MCOperandInfo OperandInfo209[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo210[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo211[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo212[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo213[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo214[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo215[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo216[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo217[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(2) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo218[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo219[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo220[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo221[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo222[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo223[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo224[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo225[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo226[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo227[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo228[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo229[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo230[] = { { ARM::tcGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tcGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo231[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo232[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo233[] = { { ARM::GPRwithAPSRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo234[] = { { ARM::GPRwithAPSRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo235[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo236[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo237[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo238[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo239[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo240[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo241[] = { { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPROddRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::tGPROddRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo242[] = { { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::tGPROddRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::tGPROddRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo243[] = { { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::tGPROddRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::tGPROddRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo244[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, }; |
| static const MCOperandInfo OperandInfo245[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, MCOI_TIED_TO(0) }, }; |
| static const MCOperandInfo OperandInfo246[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, MCOI_TIED_TO(0) }, }; |
| static const MCOperandInfo OperandInfo247[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::cl_FPSCR_NZCVRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::cl_FPSCR_NZCVRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, MCOI_TIED_TO(0) }, }; |
| static const MCOperandInfo OperandInfo248[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::cl_FPSCR_NZCVRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, MCOI_TIED_TO(0) }, }; |
| static const MCOperandInfo OperandInfo249[] = { { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPROddRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::tGPROddRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, }; |
| static const MCOperandInfo OperandInfo250[] = { { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPROddRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, }; |
| static const MCOperandInfo OperandInfo251[] = { { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, }; |
| static const MCOperandInfo OperandInfo252[] = { { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, }; |
| static const MCOperandInfo OperandInfo253[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, MCOI_TIED_TO(0) }, }; |
| static const MCOperandInfo OperandInfo254[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, }; |
| static const MCOperandInfo OperandInfo255[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, MCOI_TIED_TO(0) }, }; |
| static const MCOperandInfo OperandInfo256[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, MCOI_TIED_TO(0) }, }; |
| static const MCOperandInfo OperandInfo257[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, }; |
| static const MCOperandInfo OperandInfo258[] = { { ARM::VCCRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, }; |
| static const MCOperandInfo OperandInfo259[] = { { ARM::VCCRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRwithZRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, }; |
| static const MCOperandInfo OperandInfo260[] = { { ARM::VCCRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, }; |
| static const MCOperandInfo OperandInfo261[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, }; |
| static const MCOperandInfo OperandInfo262[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, MCOI_TIED_TO(0) }, }; |
| static const MCOperandInfo OperandInfo263[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, MCOI_TIED_TO(0) }, }; |
| static const MCOperandInfo OperandInfo264[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, MCOI_TIED_TO(0) }, }; |
| static const MCOperandInfo OperandInfo265[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { ARM::tGPROddRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, MCOI_TIED_TO(0) }, }; |
| static const MCOperandInfo OperandInfo266[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, }; |
| static const MCOperandInfo OperandInfo267[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, }; |
| static const MCOperandInfo OperandInfo268[] = { { ARM::MQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, }; |
| static const MCOperandInfo OperandInfo269[] = { { ARM::MQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, }; |
| static const MCOperandInfo OperandInfo270[] = { { ARM::MQQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, }; |
| static const MCOperandInfo OperandInfo271[] = { { ARM::MQQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, }; |
| static const MCOperandInfo OperandInfo272[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, }; |
| static const MCOperandInfo OperandInfo273[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, }; |
| static const MCOperandInfo OperandInfo274[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, }; |
| static const MCOperandInfo OperandInfo275[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, }; |
| static const MCOperandInfo OperandInfo276[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, }; |
| static const MCOperandInfo OperandInfo277[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, }; |
| static const MCOperandInfo OperandInfo278[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, }; |
| static const MCOperandInfo OperandInfo279[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, }; |
| static const MCOperandInfo OperandInfo280[] = { { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, }; |
| static const MCOperandInfo OperandInfo281[] = { { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, }; |
| static const MCOperandInfo OperandInfo282[] = { { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPROddRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::tGPROddRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, }; |
| static const MCOperandInfo OperandInfo283[] = { { ARM::tGPREvenRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPROddRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, }; |
| static const MCOperandInfo OperandInfo284[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo285[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo286[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo287[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo288[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, MCOI_TIED_TO(0) }, }; |
| static const MCOperandInfo OperandInfo289[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, MCOI_TIED_TO(0) }, }; |
| static const MCOperandInfo OperandInfo290[] = { { ARM::VCCRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::VCCRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, }; |
| static const MCOperandInfo OperandInfo291[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, }; |
| static const MCOperandInfo OperandInfo292[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo293[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRwithZRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo294[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, }; |
| static const MCOperandInfo OperandInfo295[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, MCOI_TIED_TO(0) }, }; |
| static const MCOperandInfo OperandInfo296[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, }; |
| static const MCOperandInfo OperandInfo297[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, }; |
| static const MCOperandInfo OperandInfo298[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_R, 0 }, { ARM::MQPRRegClassID, 0, ARM::OPERAND_VPRED_R, MCOI_TIED_TO(0) }, }; |
| static const MCOperandInfo OperandInfo299[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, }; |
| static const MCOperandInfo OperandInfo300[] = { { ARM::MQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, }; |
| static const MCOperandInfo OperandInfo301[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, }; |
| static const MCOperandInfo OperandInfo302[] = { { ARM::MQQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, }; |
| static const MCOperandInfo OperandInfo303[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, }; |
| static const MCOperandInfo OperandInfo304[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, }; |
| static const MCOperandInfo OperandInfo305[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, }; |
| static const MCOperandInfo OperandInfo306[] = { { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::MQPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::VCCRRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, { ARM::GPRlrRegClassID, 0, ARM::OPERAND_VPRED_N, 0 }, }; |
| static const MCOperandInfo OperandInfo307[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo308[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo309[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo310[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo311[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; |
| static const MCOperandInfo OperandInfo312[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; |
| static const MCOperandInfo OperandInfo313[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo314[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo315[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo316[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo317[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo318[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo319[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo320[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo321[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo322[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::GPRPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo323[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo324[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo325[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo326[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo327[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo328[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo329[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo330[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo331[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo332[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo333[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo334[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo335[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo336[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo337[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo338[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo339[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo340[] = { { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo341[] = { { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo342[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo343[] = { { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo344[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo345[] = { { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo346[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo347[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo348[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo349[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo350[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo351[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo352[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo353[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo354[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo355[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo356[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo357[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo358[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo359[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo360[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo361[] = { { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo362[] = { { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo363[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo364[] = { { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo365[] = { { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo366[] = { { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo367[] = { { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo368[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo369[] = { { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo370[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo371[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo372[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo373[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo374[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo375[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo376[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo377[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo378[] = { { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo379[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo380[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPR_8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo381[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo382[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo383[] = { { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo384[] = { { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo385[] = { { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo386[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo387[] = { { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo388[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo389[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo390[] = { { ARM::DPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo391[] = { { ARM::DPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo392[] = { { ARM::DPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo393[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo394[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo395[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo396[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo397[] = { { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo398[] = { { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo399[] = { { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo400[] = { { ARM::QQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo401[] = { { ARM::QQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo402[] = { { ARM::DPairSpcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo403[] = { { ARM::DPairSpcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo404[] = { { ARM::DPairSpcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo405[] = { { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo406[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo407[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(2) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo408[] = { { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo409[] = { { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo410[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo411[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(3) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo412[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(2) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo413[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(3) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(2) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo414[] = { { ARM::QQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo415[] = { { ARM::QQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo416[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo417[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(4) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo418[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(2) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(3) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo419[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(4) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(2) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(3) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo420[] = { { ARM::DPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo421[] = { { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo422[] = { { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo423[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo424[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo425[] = { { ARM::VCCRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo426[] = { { ARM::VCCRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(1) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo427[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo428[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo429[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo430[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo431[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo432[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo433[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo434[] = { { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo435[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo436[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo437[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo438[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo439[] = { { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo440[] = { { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo441[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo442[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::cl_FPSCR_NZCVRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo443[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::VCCRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo444[] = { { ARM::cl_FPSCR_NZCVRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo445[] = { { ARM::VCCRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo446[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo447[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo448[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo449[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_VFP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo450[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo451[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPR_8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo452[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo453[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo454[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo455[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo456[] = { { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo457[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo458[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo459[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo460[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo461[] = { { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo462[] = { { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo463[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo464[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo465[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo466[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo467[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo468[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo469[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo470[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo471[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo472[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo473[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo474[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo475[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo476[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo477[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo478[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo479[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo480[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo481[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo482[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo483[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo484[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo485[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo486[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo487[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo488[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::QQQQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo489[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo490[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo491[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo492[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo493[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo494[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo495[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::VCCRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo496[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo497[] = { { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::QPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo498[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo499[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo500[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::DPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo501[] = { { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::QQPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::DPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo502[] = { { ARM::SPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::HPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo503[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo504[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo505[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo506[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo507[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo508[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo509[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo510[] = { { ARM::GPRspRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRspRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo511[] = { { ARM::GPRspRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRspRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo512[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo513[] = { { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo514[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo515[] = { { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo516[] = { { -1, 0, MCOI::OPERAND_PCREL, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo517[] = { { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo518[] = { { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo519[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo520[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo521[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo522[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRwithZRnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRwithZRnospRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo523[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo524[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo525[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo526[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo527[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo528[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(2) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo529[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo530[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo531[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo532[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo533[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo534[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo535[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo536[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo537[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo538[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo539[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo540[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo541[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo542[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo543[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo544[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo545[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo546[] = { { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo547[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo548[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(1) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo549[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo550[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo551[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo552[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo553[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo554[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo555[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo556[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo557[] = { { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo558[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::rGPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo559[] = { { ARM::rGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo560[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo561[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo562[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo563[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRspRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo564[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRspRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo565[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo566[] = { { ARM::GPRspRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRspRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo567[] = { { ARM::GPRspRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRspRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo568[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo569[] = { { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRnopcRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo570[] = { { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo571[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; |
| static const MCOperandInfo OperandInfo572[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo573[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo574[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo575[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo576[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo577[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo578[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo579[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo580[] = { { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::CCRRegClassID, 0|(1<<MCOI::OptionalDef), MCOI::OPERAND_UNKNOWN, 0 }, { ARM::tGPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo581[] = { { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { ARM::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| |
| extern const MCInstrDesc ARMInsts[] = { |
| { 4425, 0, 0, 2, 845, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr }, // Inst #4425 = t__brkdiv0 |
| { 4424, 4, 1, 2, 898, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo572 }, // Inst #4424 = tUXTH |
| { 4423, 4, 1, 2, 898, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo572 }, // Inst #4423 = tUXTB |
| { 4422, 1, 0, 2, 1086, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo2 }, // Inst #4422 = tUDF |
| { 4421, 4, 0, 2, 1085, 0, 1, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0xc80ULL, ImplicitList1, OperandInfo572 }, // Inst #4421 = tTST |
| { 4420, 0, 0, 2, 1084, 0, 0, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr }, // Inst #4420 = tTRAP |
| { 4419, 4, 1, 2, 898, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo572 }, // Inst #4419 = tSXTH |
| { 4418, 4, 1, 2, 898, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo572 }, // Inst #4418 = tSXTB |
| { 4417, 3, 0, 2, 1211, 1, 0, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, ImplicitList7, OperandInfo202 }, // Inst #4417 = tSVC |
| { 4416, 5, 1, 2, 1074, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo566 }, // Inst #4416 = tSUBspi |
| { 4415, 6, 2, 2, 1073, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL, nullptr, OperandInfo565 }, // Inst #4415 = tSUBrr |
| { 4414, 6, 2, 2, 1104, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL, nullptr, OperandInfo562 }, // Inst #4414 = tSUBi8 |
| { 4413, 6, 2, 2, 1104, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL, nullptr, OperandInfo561 }, // Inst #4413 = tSUBi3 |
| { 4412, 5, 0, 2, 1083, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8aULL, nullptr, OperandInfo577 }, // Inst #4412 = tSTRspi |
| { 4411, 5, 0, 2, 435, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc89ULL, nullptr, OperandInfo575 }, // Inst #4411 = tSTRr |
| { 4410, 5, 0, 2, 1083, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc89ULL, nullptr, OperandInfo574 }, // Inst #4410 = tSTRi |
| { 4409, 5, 0, 2, 434, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc88ULL, nullptr, OperandInfo575 }, // Inst #4409 = tSTRHr |
| { 4408, 5, 0, 2, 1082, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc88ULL, nullptr, OperandInfo574 }, // Inst #4408 = tSTRHi |
| { 4407, 5, 0, 2, 434, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc87ULL, nullptr, OperandInfo575 }, // Inst #4407 = tSTRBr |
| { 4406, 5, 0, 2, 1082, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc87ULL, nullptr, OperandInfo574 }, // Inst #4406 = tSTRBi |
| { 4405, 5, 1, 2, 1021, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc80ULL, nullptr, OperandInfo144 }, // Inst #4405 = tSTMIA_UPD |
| { 4404, 1, 0, 2, 1072, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo2 }, // Inst #4404 = tSETEND |
| { 4403, 6, 2, 2, 1073, 1, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::UnmodeledSideEffects), 0x80c80ULL, ImplicitList1, OperandInfo560 }, // Inst #4403 = tSBC |
| { 4402, 5, 2, 2, 1074, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL, nullptr, OperandInfo580 }, // Inst #4402 = tRSB |
| { 4401, 6, 2, 2, 880, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL, nullptr, OperandInfo560 }, // Inst #4401 = tROR |
| { 4400, 4, 1, 2, 1027, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo572 }, // Inst #4400 = tREVSH |
| { 4399, 4, 1, 2, 1027, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo572 }, // Inst #4399 = tREV16 |
| { 4398, 4, 1, 2, 1027, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo572 }, // Inst #4398 = tREV |
| { 4397, 3, 0, 2, 452, 1, 1, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc80ULL, ImplicitList2, OperandInfo150 }, // Inst #4397 = tPUSH |
| { 4396, 3, 0, 2, 424, 1, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0xc80ULL, ImplicitList2, OperandInfo150 }, // Inst #4396 = tPOP |
| { 4395, 3, 1, 2, 1073, 0, 0, 0|(1ULL<<MCID::NotDuplicable), 0xc80ULL, nullptr, OperandInfo581 }, // Inst #4395 = tPICADD |
| { 4394, 6, 2, 2, 1075, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL, nullptr, OperandInfo560 }, // Inst #4394 = tORR |
| { 4393, 5, 2, 2, 872, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL, nullptr, OperandInfo580 }, // Inst #4393 = tMVN |
| { 4392, 6, 2, 2, 883, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL, nullptr, OperandInfo579 }, // Inst #4392 = tMUL |
| { 4391, 4, 1, 2, 1022, 0, 0, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo197 }, // Inst #4391 = tMOVr |
| { 4390, 5, 2, 2, 1023, 0, 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL, nullptr, OperandInfo578 }, // Inst #4390 = tMOVi8 |
| { 4389, 2, 1, 2, 1081, 0, 1, 0|(1ULL<<MCID::MoveReg), 0xc80ULL, ImplicitList1, OperandInfo151 }, // Inst #4389 = tMOVSr |
| { 4388, 6, 2, 2, 881, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL, nullptr, OperandInfo560 }, // Inst #4388 = tLSRrr |
| { 4387, 6, 2, 2, 1076, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL, nullptr, OperandInfo561 }, // Inst #4387 = tLSRri |
| { 4386, 6, 2, 2, 881, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL, nullptr, OperandInfo560 }, // Inst #4386 = tLSLrr |
| { 4385, 6, 2, 2, 1076, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL, nullptr, OperandInfo561 }, // Inst #4385 = tLSLri |
| { 4384, 5, 1, 2, 906, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc8aULL, nullptr, OperandInfo577 }, // Inst #4384 = tLDRspi |
| { 4383, 5, 1, 2, 396, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc89ULL, nullptr, OperandInfo575 }, // Inst #4383 = tLDRr |
| { 4382, 4, 1, 2, 1224, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc8aULL, nullptr, OperandInfo576 }, // Inst #4382 = tLDRpci |
| { 4381, 5, 1, 2, 906, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc89ULL, nullptr, OperandInfo574 }, // Inst #4381 = tLDRi |
| { 4380, 5, 1, 2, 402, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc88ULL, nullptr, OperandInfo575 }, // Inst #4380 = tLDRSH |
| { 4379, 5, 1, 2, 402, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc87ULL, nullptr, OperandInfo575 }, // Inst #4379 = tLDRSB |
| { 4378, 5, 1, 2, 395, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc88ULL, nullptr, OperandInfo575 }, // Inst #4378 = tLDRHr |
| { 4377, 5, 1, 2, 905, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc88ULL, nullptr, OperandInfo574 }, // Inst #4377 = tLDRHi |
| { 4376, 5, 1, 2, 395, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc87ULL, nullptr, OperandInfo575 }, // Inst #4376 = tLDRBr |
| { 4375, 5, 1, 2, 905, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc87ULL, nullptr, OperandInfo574 }, // Inst #4375 = tLDRBi |
| { 4374, 4, 0, 2, 1014, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0xc80ULL, nullptr, OperandInfo573 }, // Inst #4374 = tLDMIA |
| { 4373, 2, 0, 12, 1034, 0, 10, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, ImplicitList23, OperandInfo151 }, // Inst #4373 = tInt_eh_sjlj_setjmp |
| { 4372, 2, 0, 10, 1034, 0, 3, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList4, OperandInfo151 }, // Inst #4372 = tInt_eh_sjlj_longjmp |
| { 4371, 2, 0, 12, 851, 0, 3, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList22, OperandInfo45 }, // Inst #4371 = tInt_WIN_eh_sjlj_longjmp |
| { 4370, 1, 0, 2, 1072, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo2 }, // Inst #4370 = tHLT |
| { 4369, 3, 0, 2, 1214, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo202 }, // Inst #4369 = tHINT |
| { 4368, 6, 2, 2, 1075, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL, nullptr, OperandInfo560 }, // Inst #4368 = tEOR |
| { 4367, 2, 0, 2, 1080, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo7 }, // Inst #4367 = tCPS |
| { 4366, 4, 0, 2, 1078, 0, 1, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL, ImplicitList1, OperandInfo572 }, // Inst #4366 = tCMPr |
| { 4365, 4, 0, 2, 1079, 0, 1, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL, ImplicitList1, OperandInfo145 }, // Inst #4365 = tCMPi8 |
| { 4364, 4, 0, 2, 1078, 0, 1, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, ImplicitList1, OperandInfo197 }, // Inst #4364 = tCMPhir |
| { 4363, 4, 0, 2, 1078, 0, 1, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL, ImplicitList1, OperandInfo572 }, // Inst #4363 = tCMNz |
| { 4362, 2, 0, 2, 1077, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo571 }, // Inst #4362 = tCBZ |
| { 4361, 2, 0, 2, 1077, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo571 }, // Inst #4361 = tCBNZ |
| { 4360, 3, 0, 2, 1087, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo141 }, // Inst #4360 = tBcc |
| { 4359, 3, 0, 2, 1087, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo137 }, // Inst #4359 = tBXNS |
| { 4358, 3, 0, 2, 1087, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo137 }, // Inst #4358 = tBX |
| { 4357, 3, 0, 2, 1088, 1, 1, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable), 0xc80ULL, ImplicitList3, OperandInfo570 }, // Inst #4357 = tBLXr |
| { 4356, 3, 0, 4, 856, 1, 1, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, ImplicitList3, OperandInfo110 }, // Inst #4356 = tBLXi |
| { 4355, 3, 0, 2, 1088, 1, 1, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, ImplicitList3, OperandInfo569 }, // Inst #4355 = tBLXNSr |
| { 4354, 3, 0, 4, 856, 1, 1, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable), 0xc80ULL, ImplicitList3, OperandInfo110 }, // Inst #4354 = tBL |
| { 4353, 1, 0, 2, 1033, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo2 }, // Inst #4353 = tBKPT |
| { 4352, 6, 2, 2, 1075, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL, nullptr, OperandInfo560 }, // Inst #4352 = tBIC |
| { 4351, 3, 0, 2, 1087, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0xc80ULL, nullptr, OperandInfo141 }, // Inst #4351 = tB |
| { 4350, 6, 2, 2, 881, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL, nullptr, OperandInfo560 }, // Inst #4350 = tASRrr |
| { 4349, 6, 2, 2, 1076, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL, nullptr, OperandInfo561 }, // Inst #4349 = tASRri |
| { 4348, 6, 2, 2, 1075, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL, nullptr, OperandInfo560 }, // Inst #4348 = tAND |
| { 4347, 4, 1, 2, 1074, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo568 }, // Inst #4347 = tADR |
| { 4346, 5, 1, 2, 1073, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo567 }, // Inst #4346 = tADDspr |
| { 4345, 5, 1, 2, 1074, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo566 }, // Inst #4345 = tADDspi |
| { 4344, 6, 2, 2, 1073, 0, 0, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL, nullptr, OperandInfo565 }, // Inst #4344 = tADDrr |
| { 4343, 5, 1, 2, 1074, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo564 }, // Inst #4343 = tADDrSPi |
| { 4342, 5, 1, 2, 1073, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo563 }, // Inst #4342 = tADDrSP |
| { 4341, 6, 2, 2, 1104, 0, 0, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL, nullptr, OperandInfo562 }, // Inst #4341 = tADDi8 |
| { 4340, 6, 2, 2, 1104, 0, 0, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL, nullptr, OperandInfo561 }, // Inst #4340 = tADDi3 |
| { 4339, 5, 1, 2, 1073, 0, 0, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo75 }, // Inst #4339 = tADDhirr |
| { 4338, 6, 2, 2, 1073, 1, 0, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::UnmodeledSideEffects), 0x80c80ULL, ImplicitList1, OperandInfo560 }, // Inst #4338 = tADC |
| { 4337, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo129 }, // Inst #4337 = t2WLS |
| { 4336, 5, 1, 4, 897, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo126 }, // Inst #4336 = t2UXTH |
| { 4335, 5, 1, 4, 353, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo126 }, // Inst #4335 = t2UXTB16 |
| { 4334, 5, 1, 4, 897, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo126 }, // Inst #4334 = t2UXTB |
| { 4333, 6, 1, 4, 1095, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo543 }, // Inst #4333 = t2UXTAH |
| { 4332, 6, 1, 4, 1096, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo543 }, // Inst #4332 = t2UXTAB16 |
| { 4331, 6, 1, 4, 1095, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo543 }, // Inst #4331 = t2UXTAB |
| { 4330, 5, 1, 4, 885, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo539 }, // Inst #4330 = t2USUB8 |
| { 4329, 5, 1, 4, 885, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo539 }, // Inst #4329 = t2USUB16 |
| { 4328, 5, 1, 4, 365, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo539 }, // Inst #4328 = t2USAX |
| { 4327, 5, 1, 4, 363, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo550 }, // Inst #4327 = t2USAT16 |
| { 4326, 6, 1, 4, 363, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo549 }, // Inst #4326 = t2USAT |
| { 4325, 6, 1, 4, 684, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo534 }, // Inst #4325 = t2USADA8 |
| { 4324, 5, 1, 4, 1239, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo539 }, // Inst #4324 = t2USAD8 |
| { 4323, 5, 1, 4, 889, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo539 }, // Inst #4323 = t2UQSUB8 |
| { 4322, 5, 1, 4, 889, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo539 }, // Inst #4322 = t2UQSUB16 |
| { 4321, 5, 1, 4, 891, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo539 }, // Inst #4321 = t2UQSAX |
| { 4320, 5, 1, 4, 891, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo539 }, // Inst #4320 = t2UQASX |
| { 4319, 5, 1, 4, 889, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo539 }, // Inst #4319 = t2UQADD8 |
| { 4318, 5, 1, 4, 889, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo539 }, // Inst #4318 = t2UQADD16 |
| { 4317, 6, 2, 4, 383, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0xc80ULL, nullptr, OperandInfo534 }, // Inst #4317 = t2UMULL |
| { 4316, 8, 2, 4, 384, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo548 }, // Inst #4316 = t2UMLAL |
| { 4315, 8, 2, 4, 384, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo548 }, // Inst #4315 = t2UMAAL |
| { 4314, 5, 1, 4, 887, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo539 }, // Inst #4314 = t2UHSUB8 |
| { 4313, 5, 1, 4, 887, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo539 }, // Inst #4313 = t2UHSUB16 |
| { 4312, 5, 1, 4, 368, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo539 }, // Inst #4312 = t2UHSAX |
| { 4311, 5, 1, 4, 368, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo539 }, // Inst #4311 = t2UHASX |
| { 4310, 5, 1, 4, 887, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo539 }, // Inst #4310 = t2UHADD8 |
| { 4309, 5, 1, 4, 887, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo539 }, // Inst #4309 = t2UHADD16 |
| { 4308, 5, 1, 4, 685, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo539 }, // Inst #4308 = t2UDIV |
| { 4307, 1, 0, 4, 1032, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo2 }, // Inst #4307 = t2UDF |
| { 4306, 6, 1, 4, 895, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo547 }, // Inst #4306 = t2UBFX |
| { 4305, 5, 1, 4, 365, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo539 }, // Inst #4305 = t2UASX |
| { 4304, 5, 1, 4, 885, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo539 }, // Inst #4304 = t2UADD8 |
| { 4303, 5, 1, 4, 885, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo539 }, // Inst #4303 = t2UADD16 |
| { 4302, 4, 1, 4, 1052, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo559 }, // Inst #4302 = t2TTT |
| { 4301, 4, 1, 4, 1052, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo559 }, // Inst #4301 = t2TTAT |
| { 4300, 4, 1, 4, 1052, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo559 }, // Inst #4300 = t2TTA |
| { 4299, 4, 1, 4, 1052, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo559 }, // Inst #4299 = t2TT |
| { 4298, 5, 0, 4, 1235, 0, 1, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL, ImplicitList1, OperandInfo123 }, // Inst #4298 = t2TSTrs |
| { 4297, 4, 0, 4, 1068, 0, 1, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL, ImplicitList1, OperandInfo519 }, // Inst #4297 = t2TSTrr |
| { 4296, 4, 0, 4, 310, 0, 1, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL, ImplicitList1, OperandInfo512 }, // Inst #4296 = t2TSTri |
| { 4295, 3, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo202 }, // Inst #4295 = t2TSB |
| { 4294, 5, 0, 4, 1235, 0, 1, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL, ImplicitList1, OperandInfo123 }, // Inst #4294 = t2TEQrs |
| { 4293, 4, 0, 4, 1068, 0, 1, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL, ImplicitList1, OperandInfo519 }, // Inst #4293 = t2TEQrr |
| { 4292, 4, 0, 4, 310, 0, 1, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL, ImplicitList1, OperandInfo512 }, // Inst #4292 = t2TEQri |
| { 4291, 4, 0, 4, 1228, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo558 }, // Inst #4291 = t2TBH |
| { 4290, 4, 0, 4, 1228, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo558 }, // Inst #4290 = t2TBB |
| { 4289, 5, 1, 4, 897, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo126 }, // Inst #4289 = t2SXTH |
| { 4288, 5, 1, 4, 353, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo126 }, // Inst #4288 = t2SXTB16 |
| { 4287, 5, 1, 4, 897, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo126 }, // Inst #4287 = t2SXTB |
| { 4286, 6, 1, 4, 900, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo543 }, // Inst #4286 = t2SXTAH |
| { 4285, 6, 1, 4, 369, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo543 }, // Inst #4285 = t2SXTAB16 |
| { 4284, 6, 1, 4, 900, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo543 }, // Inst #4284 = t2SXTAB |
| { 4283, 5, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo511 }, // Inst #4283 = t2SUBspImm12 |
| { 4282, 6, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo510 }, // Inst #4282 = t2SUBspImm |
| { 4281, 7, 1, 4, 1229, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, OperandInfo509 }, // Inst #4281 = t2SUBrs |
| { 4280, 6, 1, 4, 1067, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, OperandInfo508 }, // Inst #4280 = t2SUBrr |
| { 4279, 5, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo507 }, // Inst #4279 = t2SUBri12 |
| { 4278, 6, 1, 4, 1106, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, OperandInfo506 }, // Inst #4278 = t2SUBri |
| { 4277, 3, 0, 4, 1054, 0, 1, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0xc80ULL, ImplicitList12, OperandInfo202 }, // Inst #4277 = t2SUBS_PC_LR |
| { 4276, 6, 0, 4, 431, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8fULL, nullptr, OperandInfo532 }, // Inst #4276 = t2STRs |
| { 4275, 5, 0, 4, 430, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8eULL, nullptr, OperandInfo87 }, // Inst #4275 = t2STRi8 |
| { 4274, 5, 0, 4, 1069, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8bULL, nullptr, OperandInfo87 }, // Inst #4274 = t2STRi12 |
| { 4273, 6, 1, 4, 940, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xcacULL, nullptr, OperandInfo557 }, // Inst #4273 = t2STR_PRE |
| { 4272, 6, 1, 4, 441, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xcccULL, nullptr, OperandInfo557 }, // Inst #4272 = t2STR_POST |
| { 4271, 5, 0, 4, 445, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc8dULL, nullptr, OperandInfo525 }, // Inst #4271 = t2STRT |
| { 4270, 6, 0, 4, 433, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8fULL, nullptr, OperandInfo554 }, // Inst #4270 = t2STRHs |
| { 4269, 5, 0, 4, 432, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8eULL, nullptr, OperandInfo525 }, // Inst #4269 = t2STRHi8 |
| { 4268, 5, 0, 4, 1070, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8bULL, nullptr, OperandInfo525 }, // Inst #4268 = t2STRHi12 |
| { 4267, 6, 1, 4, 940, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xcacULL, nullptr, OperandInfo553 }, // Inst #4267 = t2STRH_PRE |
| { 4266, 6, 1, 4, 442, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xcccULL, nullptr, OperandInfo553 }, // Inst #4266 = t2STRH_POST |
| { 4265, 5, 0, 4, 444, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc8dULL, nullptr, OperandInfo525 }, // Inst #4265 = t2STRHT |
| { 4264, 5, 1, 4, 1221, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo551 }, // Inst #4264 = t2STREXH |
| { 4263, 6, 1, 4, 730, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc80ULL, nullptr, OperandInfo552 }, // Inst #4263 = t2STREXD |
| { 4262, 5, 1, 4, 1221, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo551 }, // Inst #4262 = t2STREXB |
| { 4261, 6, 1, 4, 1221, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc94ULL, nullptr, OperandInfo556 }, // Inst #4261 = t2STREX |
| { 4260, 6, 0, 4, 447, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc91ULL, nullptr, OperandInfo529 }, // Inst #4260 = t2STRDi8 |
| { 4259, 7, 1, 4, 943, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc91ULL, nullptr, OperandInfo555 }, // Inst #4259 = t2STRD_PRE |
| { 4258, 7, 1, 4, 448, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc91ULL, nullptr, OperandInfo555 }, // Inst #4258 = t2STRD_POST |
| { 4257, 6, 0, 4, 433, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8fULL, nullptr, OperandInfo554 }, // Inst #4257 = t2STRBs |
| { 4256, 5, 0, 4, 432, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8eULL, nullptr, OperandInfo525 }, // Inst #4256 = t2STRBi8 |
| { 4255, 5, 0, 4, 1070, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8bULL, nullptr, OperandInfo525 }, // Inst #4255 = t2STRBi12 |
| { 4254, 6, 1, 4, 942, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xcacULL, nullptr, OperandInfo553 }, // Inst #4254 = t2STRB_PRE |
| { 4253, 6, 1, 4, 950, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xcccULL, nullptr, OperandInfo553 }, // Inst #4253 = t2STRB_POST |
| { 4252, 5, 0, 4, 935, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc8dULL, nullptr, OperandInfo525 }, // Inst #4252 = t2STRBT |
| { 4251, 5, 1, 4, 1071, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc80ULL, nullptr, OperandInfo66 }, // Inst #4251 = t2STMIA_UPD |
| { 4250, 4, 0, 4, 1020, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc80ULL, nullptr, OperandInfo206 }, // Inst #4250 = t2STMIA |
| { 4249, 5, 1, 4, 1071, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc80ULL, nullptr, OperandInfo66 }, // Inst #4249 = t2STMDB_UPD |
| { 4248, 4, 0, 4, 1020, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc80ULL, nullptr, OperandInfo206 }, // Inst #4248 = t2STMDB |
| { 4247, 4, 0, 4, 732, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo523 }, // Inst #4247 = t2STLH |
| { 4246, 5, 1, 4, 732, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo551 }, // Inst #4246 = t2STLEXH |
| { 4245, 6, 1, 4, 732, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xc80ULL, nullptr, OperandInfo552 }, // Inst #4245 = t2STLEXD |
| { 4244, 5, 1, 4, 732, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo551 }, // Inst #4244 = t2STLEXB |
| { 4243, 5, 1, 4, 732, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo551 }, // Inst #4243 = t2STLEX |
| { 4242, 4, 0, 4, 732, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo523 }, // Inst #4242 = t2STLB |
| { 4241, 4, 0, 4, 732, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo523 }, // Inst #4241 = t2STL |
| { 4240, 6, 0, 4, 1030, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo210 }, // Inst #4240 = t2STC_PRE |
| { 4239, 6, 0, 4, 1030, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo210 }, // Inst #4239 = t2STC_POST |
| { 4238, 6, 0, 4, 1030, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo211 }, // Inst #4238 = t2STC_OPTION |
| { 4237, 6, 0, 4, 1030, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc85ULL, nullptr, OperandInfo210 }, // Inst #4237 = t2STC_OFFSET |
| { 4236, 6, 0, 4, 1030, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo210 }, // Inst #4236 = t2STCL_PRE |
| { 4235, 6, 0, 4, 1030, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo210 }, // Inst #4235 = t2STCL_POST |
| { 4234, 6, 0, 4, 1030, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo211 }, // Inst #4234 = t2STCL_OPTION |
| { 4233, 6, 0, 4, 1030, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc85ULL, nullptr, OperandInfo210 }, // Inst #4233 = t2STCL_OFFSET |
| { 4232, 6, 0, 4, 1030, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo210 }, // Inst #4232 = t2STC2_PRE |
| { 4231, 6, 0, 4, 1030, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo210 }, // Inst #4231 = t2STC2_POST |
| { 4230, 6, 0, 4, 1030, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo211 }, // Inst #4230 = t2STC2_OPTION |
| { 4229, 6, 0, 4, 1030, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc85ULL, nullptr, OperandInfo210 }, // Inst #4229 = t2STC2_OFFSET |
| { 4228, 6, 0, 4, 1030, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo210 }, // Inst #4228 = t2STC2L_PRE |
| { 4227, 6, 0, 4, 1030, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo210 }, // Inst #4227 = t2STC2L_POST |
| { 4226, 6, 0, 4, 1030, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo211 }, // Inst #4226 = t2STC2L_OPTION |
| { 4225, 6, 0, 4, 1030, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc85ULL, nullptr, OperandInfo210 }, // Inst #4225 = t2STC2L_OFFSET |
| { 4224, 5, 1, 4, 885, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo539 }, // Inst #4224 = t2SSUB8 |
| { 4223, 5, 1, 4, 885, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo539 }, // Inst #4223 = t2SSUB16 |
| { 4222, 5, 1, 4, 365, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo539 }, // Inst #4222 = t2SSAX |
| { 4221, 5, 1, 4, 363, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo550 }, // Inst #4221 = t2SSAT16 |
| { 4220, 6, 1, 4, 363, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo549 }, // Inst #4220 = t2SSAT |
| { 4219, 3, 0, 4, 729, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo202 }, // Inst #4219 = t2SRSIA_UPD |
| { 4218, 3, 0, 4, 729, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo202 }, // Inst #4218 = t2SRSIA |
| { 4217, 3, 0, 4, 729, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo202 }, // Inst #4217 = t2SRSDB_UPD |
| { 4216, 3, 0, 4, 729, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo202 }, // Inst #4216 = t2SRSDB |
| { 4215, 5, 1, 4, 375, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo539 }, // Inst #4215 = t2SMUSDX |
| { 4214, 5, 1, 4, 375, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo539 }, // Inst #4214 = t2SMUSD |
| { 4213, 5, 1, 4, 374, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo539 }, // Inst #4213 = t2SMULWT |
| { 4212, 5, 1, 4, 374, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo539 }, // Inst #4212 = t2SMULWB |
| { 4211, 5, 1, 4, 374, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo539 }, // Inst #4211 = t2SMULTT |
| { 4210, 5, 1, 4, 374, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo539 }, // Inst #4210 = t2SMULTB |
| { 4209, 6, 2, 4, 383, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0xc80ULL, nullptr, OperandInfo534 }, // Inst #4209 = t2SMULL |
| { 4208, 5, 1, 4, 374, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo539 }, // Inst #4208 = t2SMULBT |
| { 4207, 5, 1, 4, 374, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo539 }, // Inst #4207 = t2SMULBB |
| { 4206, 5, 1, 4, 377, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo539 }, // Inst #4206 = t2SMUADX |
| { 4205, 5, 1, 4, 377, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo539 }, // Inst #4205 = t2SMUAD |
| { 4204, 5, 1, 4, 373, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo539 }, // Inst #4204 = t2SMMULR |
| { 4203, 5, 1, 4, 373, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo539 }, // Inst #4203 = t2SMMUL |
| { 4202, 6, 1, 4, 1094, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo534 }, // Inst #4202 = t2SMMLSR |
| { 4201, 6, 1, 4, 1094, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo534 }, // Inst #4201 = t2SMMLS |
| { 4200, 6, 1, 4, 1094, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo534 }, // Inst #4200 = t2SMMLAR |
| { 4199, 6, 1, 4, 1094, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo534 }, // Inst #4199 = t2SMMLA |
| { 4198, 8, 2, 4, 1026, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo548 }, // Inst #4198 = t2SMLSLDX |
| { 4197, 8, 2, 4, 1026, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo548 }, // Inst #4197 = t2SMLSLD |
| { 4196, 6, 1, 4, 380, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo534 }, // Inst #4196 = t2SMLSDX |
| { 4195, 6, 1, 4, 380, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo534 }, // Inst #4195 = t2SMLSD |
| { 4194, 6, 1, 4, 379, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo534 }, // Inst #4194 = t2SMLAWT |
| { 4193, 6, 1, 4, 379, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo534 }, // Inst #4193 = t2SMLAWB |
| { 4192, 6, 1, 4, 379, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo534 }, // Inst #4192 = t2SMLATT |
| { 4191, 6, 1, 4, 379, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo534 }, // Inst #4191 = t2SMLATB |
| { 4190, 8, 2, 4, 1026, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo548 }, // Inst #4190 = t2SMLALTT |
| { 4189, 8, 2, 4, 1026, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo548 }, // Inst #4189 = t2SMLALTB |
| { 4188, 8, 2, 4, 1026, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo548 }, // Inst #4188 = t2SMLALDX |
| { 4187, 8, 2, 4, 1026, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo548 }, // Inst #4187 = t2SMLALD |
| { 4186, 8, 2, 4, 1026, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo548 }, // Inst #4186 = t2SMLALBT |
| { 4185, 8, 2, 4, 1026, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo548 }, // Inst #4185 = t2SMLALBB |
| { 4184, 8, 2, 4, 1026, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo548 }, // Inst #4184 = t2SMLAL |
| { 4183, 6, 1, 4, 381, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo534 }, // Inst #4183 = t2SMLADX |
| { 4182, 6, 1, 4, 381, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo534 }, // Inst #4182 = t2SMLAD |
| { 4181, 6, 1, 4, 379, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo534 }, // Inst #4181 = t2SMLABT |
| { 4180, 6, 1, 4, 379, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo534 }, // Inst #4180 = t2SMLABB |
| { 4179, 3, 0, 4, 1213, 1, 0, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, ImplicitList7, OperandInfo202 }, // Inst #4179 = t2SMC |
| { 4178, 5, 1, 4, 887, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo539 }, // Inst #4178 = t2SHSUB8 |
| { 4177, 5, 1, 4, 887, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo539 }, // Inst #4177 = t2SHSUB16 |
| { 4176, 5, 1, 4, 368, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo539 }, // Inst #4176 = t2SHSAX |
| { 4175, 5, 1, 4, 368, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo539 }, // Inst #4175 = t2SHASX |
| { 4174, 5, 1, 4, 887, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo539 }, // Inst #4174 = t2SHADD8 |
| { 4173, 5, 1, 4, 887, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo539 }, // Inst #4173 = t2SHADD16 |
| { 4172, 2, 0, 4, 1052, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo139 }, // Inst #4172 = t2SG |
| { 4171, 1, 0, 2, 1072, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo2 }, // Inst #4171 = t2SETPAN |
| { 4170, 5, 1, 4, 358, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo47 }, // Inst #4170 = t2SEL |
| { 4169, 5, 1, 4, 685, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo539 }, // Inst #4169 = t2SDIV |
| { 4168, 6, 1, 4, 895, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo547 }, // Inst #4168 = t2SBFX |
| { 4167, 7, 1, 4, 705, 1, 1, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0xc80ULL, ImplicitList10, OperandInfo505 }, // Inst #4167 = t2SBCrs |
| { 4166, 6, 1, 4, 1058, 1, 1, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0xc80ULL, ImplicitList10, OperandInfo504 }, // Inst #4166 = t2SBCrr |
| { 4165, 6, 1, 4, 693, 1, 1, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0xc80ULL, ImplicitList10, OperandInfo503 }, // Inst #4165 = t2SBCri |
| { 4164, 0, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr }, // Inst #4164 = t2SB |
| { 4163, 5, 1, 4, 365, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo539 }, // Inst #4163 = t2SASX |
| { 4162, 5, 1, 4, 885, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo539 }, // Inst #4162 = t2SADD8 |
| { 4161, 5, 1, 4, 885, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo539 }, // Inst #4161 = t2SADD16 |
| { 4160, 7, 1, 4, 707, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, OperandInfo505 }, // Inst #4160 = t2RSBrs |
| { 4159, 6, 1, 4, 1067, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo504 }, // Inst #4159 = t2RSBrr |
| { 4158, 6, 1, 4, 1066, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, OperandInfo503 }, // Inst #4158 = t2RSBri |
| { 4157, 5, 1, 4, 1236, 1, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, ImplicitList1, OperandInfo540 }, // Inst #4157 = t2RRX |
| { 4156, 6, 1, 4, 1060, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, OperandInfo504 }, // Inst #4156 = t2RORrr |
| { 4155, 6, 1, 4, 874, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, OperandInfo503 }, // Inst #4155 = t2RORri |
| { 4154, 3, 0, 4, 729, 0, 1, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, ImplicitList12, OperandInfo137 }, // Inst #4154 = t2RFEIAW |
| { 4153, 3, 0, 4, 729, 0, 1, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, ImplicitList12, OperandInfo137 }, // Inst #4153 = t2RFEIA |
| { 4152, 3, 0, 4, 729, 0, 1, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, ImplicitList12, OperandInfo137 }, // Inst #4152 = t2RFEDBW |
| { 4151, 3, 0, 4, 729, 0, 1, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, ImplicitList12, OperandInfo137 }, // Inst #4151 = t2RFEDB |
| { 4150, 4, 1, 4, 1065, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo519 }, // Inst #4150 = t2REVSH |
| { 4149, 4, 1, 4, 1065, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo519 }, // Inst #4149 = t2REV16 |
| { 4148, 4, 1, 4, 1065, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo519 }, // Inst #4148 = t2REV |
| { 4147, 4, 1, 4, 1240, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo519 }, // Inst #4147 = t2RBIT |
| { 4146, 5, 1, 4, 889, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo539 }, // Inst #4146 = t2QSUB8 |
| { 4145, 5, 1, 4, 889, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo539 }, // Inst #4145 = t2QSUB16 |
| { 4144, 5, 1, 4, 889, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo539 }, // Inst #4144 = t2QSUB |
| { 4143, 5, 1, 4, 891, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo539 }, // Inst #4143 = t2QSAX |
| { 4142, 5, 1, 4, 362, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo539 }, // Inst #4142 = t2QDSUB |
| { 4141, 5, 1, 4, 362, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo539 }, // Inst #4141 = t2QDADD |
| { 4140, 5, 1, 4, 891, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo539 }, // Inst #4140 = t2QASX |
| { 4139, 5, 1, 4, 889, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo539 }, // Inst #4139 = t2QADD8 |
| { 4138, 5, 1, 4, 889, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo539 }, // Inst #4138 = t2QADD16 |
| { 4137, 5, 1, 4, 889, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo539 }, // Inst #4137 = t2QADD |
| { 4136, 5, 0, 4, 1226, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8fULL, nullptr, OperandInfo545 }, // Inst #4136 = t2PLIs |
| { 4135, 3, 0, 4, 1223, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc90ULL, nullptr, OperandInfo546 }, // Inst #4135 = t2PLIpci |
| { 4134, 4, 0, 4, 1225, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8eULL, nullptr, OperandInfo544 }, // Inst #4134 = t2PLIi8 |
| { 4133, 4, 0, 4, 1225, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8bULL, nullptr, OperandInfo544 }, // Inst #4133 = t2PLIi12 |
| { 4132, 5, 0, 4, 1226, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8fULL, nullptr, OperandInfo545 }, // Inst #4132 = t2PLDs |
| { 4131, 3, 0, 4, 1223, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc90ULL, nullptr, OperandInfo546 }, // Inst #4131 = t2PLDpci |
| { 4130, 4, 0, 4, 1225, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8eULL, nullptr, OperandInfo544 }, // Inst #4130 = t2PLDi8 |
| { 4129, 4, 0, 4, 1225, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8bULL, nullptr, OperandInfo544 }, // Inst #4129 = t2PLDi12 |
| { 4128, 5, 0, 4, 931, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8fULL, nullptr, OperandInfo545 }, // Inst #4128 = t2PLDWs |
| { 4127, 4, 0, 4, 1225, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8eULL, nullptr, OperandInfo544 }, // Inst #4127 = t2PLDWi8 |
| { 4126, 4, 0, 4, 1225, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0xc8bULL, nullptr, OperandInfo544 }, // Inst #4126 = t2PLDWi12 |
| { 4125, 6, 1, 4, 1241, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo543 }, // Inst #4125 = t2PKHTB |
| { 4124, 6, 1, 4, 1241, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo543 }, // Inst #4124 = t2PKHBT |
| { 4123, 5, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo542 }, // Inst #4123 = t2PACG |
| { 4122, 0, 0, 4, 0, 2, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, ImplicitList21, nullptr }, // Inst #4122 = t2PACBTI |
| { 4121, 0, 0, 4, 0, 2, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, ImplicitList21, nullptr }, // Inst #4121 = t2PAC |
| { 4120, 7, 1, 4, 1231, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, OperandInfo505 }, // Inst #4120 = t2ORRrs |
| { 4119, 6, 1, 4, 1064, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, OperandInfo504 }, // Inst #4119 = t2ORRrr |
| { 4118, 6, 1, 4, 695, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, OperandInfo503 }, // Inst #4118 = t2ORRri |
| { 4117, 7, 1, 4, 1232, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, OperandInfo505 }, // Inst #4117 = t2ORNrs |
| { 4116, 6, 1, 4, 47, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, OperandInfo504 }, // Inst #4116 = t2ORNrr |
| { 4115, 6, 1, 4, 46, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, OperandInfo503 }, // Inst #4115 = t2ORNri |
| { 4114, 6, 1, 4, 699, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, OperandInfo541 }, // Inst #4114 = t2MVNs |
| { 4113, 5, 1, 4, 698, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, OperandInfo540 }, // Inst #4113 = t2MVNr |
| { 4112, 5, 1, 4, 697, 0, 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::CheapAsAMove), 0xc80ULL, nullptr, OperandInfo535 }, // Inst #4112 = t2MVNi |
| { 4111, 5, 1, 4, 1093, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0xc80ULL, nullptr, OperandInfo539 }, // Inst #4111 = t2MUL |
| { 4110, 4, 0, 4, 1024, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo538 }, // Inst #4110 = t2MSRbanked |
| { 4109, 4, 0, 4, 1024, 0, 1, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, ImplicitList1, OperandInfo538 }, // Inst #4109 = t2MSR_M |
| { 4108, 4, 0, 4, 1024, 0, 1, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, ImplicitList1, OperandInfo538 }, // Inst #4108 = t2MSR_AR |
| { 4107, 3, 1, 4, 1024, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo137 }, // Inst #4107 = t2MRSsys_AR |
| { 4106, 4, 1, 4, 1024, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo512 }, // Inst #4106 = t2MRSbanked |
| { 4105, 4, 1, 4, 1024, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo512 }, // Inst #4105 = t2MRS_M |
| { 4104, 3, 1, 4, 1024, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo137 }, // Inst #4104 = t2MRS_AR |
| { 4103, 7, 2, 4, 1029, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo537 }, // Inst #4103 = t2MRRC2 |
| { 4102, 7, 2, 4, 1029, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo537 }, // Inst #4102 = t2MRRC |
| { 4101, 8, 1, 4, 1090, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo233 }, // Inst #4101 = t2MRC2 |
| { 4100, 8, 1, 4, 1090, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo233 }, // Inst #4100 = t2MRC |
| { 4099, 4, 1, 4, 691, 0, 1, 0|(1ULL<<MCID::Predicable), 0xc80ULL, ImplicitList1, OperandInfo519 }, // Inst #4099 = t2MOVsrl_flag |
| { 4098, 4, 1, 4, 691, 0, 1, 0|(1ULL<<MCID::Predicable), 0xc80ULL, ImplicitList1, OperandInfo519 }, // Inst #4098 = t2MOVsra_flag |
| { 4097, 5, 1, 4, 879, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, OperandInfo536 }, // Inst #4097 = t2MOVr |
| { 4096, 4, 1, 4, 682, 0, 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0xc80ULL, nullptr, OperandInfo512 }, // Inst #4096 = t2MOVi16 |
| { 4095, 5, 1, 4, 682, 0, 0, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::CheapAsAMove), 0xc80ULL, nullptr, OperandInfo535 }, // Inst #4095 = t2MOVi |
| { 4094, 5, 1, 4, 878, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo120 }, // Inst #4094 = t2MOVTi16 |
| { 4093, 6, 1, 4, 376, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo534 }, // Inst #4093 = t2MLS |
| { 4092, 6, 1, 4, 376, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo534 }, // Inst #4092 = t2MLA |
| { 4091, 7, 0, 4, 1090, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo533 }, // Inst #4091 = t2MCRR2 |
| { 4090, 7, 0, 4, 1090, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo533 }, // Inst #4090 = t2MCRR |
| { 4089, 8, 0, 4, 1090, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo222 }, // Inst #4089 = t2MCR2 |
| { 4088, 8, 0, 4, 1090, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo222 }, // Inst #4088 = t2MCR |
| { 4087, 6, 1, 4, 1060, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, OperandInfo504 }, // Inst #4087 = t2LSRrr |
| { 4086, 6, 1, 4, 1059, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, OperandInfo503 }, // Inst #4086 = t2LSRri |
| { 4085, 6, 1, 4, 1060, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, OperandInfo504 }, // Inst #4085 = t2LSLrr |
| { 4084, 6, 1, 4, 1059, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, OperandInfo503 }, // Inst #4084 = t2LSLri |
| { 4083, 3, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo118 }, // Inst #4083 = t2LEUpdate |
| { 4082, 1, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo53 }, // Inst #4082 = t2LE |
| { 4081, 6, 1, 4, 391, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc8fULL, nullptr, OperandInfo532 }, // Inst #4081 = t2LDRs |
| { 4080, 4, 1, 4, 1222, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc90ULL, nullptr, OperandInfo531 }, // Inst #4080 = t2LDRpci |
| { 4079, 5, 1, 4, 390, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc8eULL, nullptr, OperandInfo87 }, // Inst #4079 = t2LDRi8 |
| { 4078, 5, 1, 4, 1101, 0, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc8bULL, nullptr, OperandInfo87 }, // Inst #4078 = t2LDRi12 |
| { 4077, 6, 2, 4, 918, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xcacULL, nullptr, OperandInfo213 }, // Inst #4077 = t2LDR_PRE |
| { 4076, 6, 2, 4, 411, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xcccULL, nullptr, OperandInfo213 }, // Inst #4076 = t2LDR_POST |
| { 4075, 5, 1, 4, 413, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc8dULL, nullptr, OperandInfo525 }, // Inst #4075 = t2LDRT |
| { 4074, 6, 1, 4, 401, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc8fULL, nullptr, OperandInfo527 }, // Inst #4074 = t2LDRSHs |
| { 4073, 4, 1, 4, 1218, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc90ULL, nullptr, OperandInfo526 }, // Inst #4073 = t2LDRSHpci |
| { 4072, 5, 1, 4, 400, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc8eULL, nullptr, OperandInfo214 }, // Inst #4072 = t2LDRSHi8 |
| { 4071, 5, 1, 4, 400, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc8bULL, nullptr, OperandInfo214 }, // Inst #4071 = t2LDRSHi12 |
| { 4070, 6, 2, 4, 917, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xcacULL, nullptr, OperandInfo213 }, // Inst #4070 = t2LDRSH_PRE |
| { 4069, 6, 2, 4, 414, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xcccULL, nullptr, OperandInfo213 }, // Inst #4069 = t2LDRSH_POST |
| { 4068, 5, 1, 4, 415, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc8dULL, nullptr, OperandInfo525 }, // Inst #4068 = t2LDRSHT |
| { 4067, 6, 1, 4, 401, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc8fULL, nullptr, OperandInfo527 }, // Inst #4067 = t2LDRSBs |
| { 4066, 4, 1, 4, 1218, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc90ULL, nullptr, OperandInfo526 }, // Inst #4066 = t2LDRSBpci |
| { 4065, 5, 1, 4, 400, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc8eULL, nullptr, OperandInfo214 }, // Inst #4065 = t2LDRSBi8 |
| { 4064, 5, 1, 4, 400, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc8bULL, nullptr, OperandInfo214 }, // Inst #4064 = t2LDRSBi12 |
| { 4063, 6, 2, 4, 917, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xcacULL, nullptr, OperandInfo213 }, // Inst #4063 = t2LDRSB_PRE |
| { 4062, 6, 2, 4, 414, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xcccULL, nullptr, OperandInfo213 }, // Inst #4062 = t2LDRSB_POST |
| { 4061, 5, 1, 4, 415, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc8dULL, nullptr, OperandInfo525 }, // Inst #4061 = t2LDRSBT |
| { 4060, 6, 1, 4, 393, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc8fULL, nullptr, OperandInfo527 }, // Inst #4060 = t2LDRHs |
| { 4059, 4, 1, 4, 1217, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc90ULL, nullptr, OperandInfo526 }, // Inst #4059 = t2LDRHpci |
| { 4058, 5, 1, 4, 392, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc8eULL, nullptr, OperandInfo214 }, // Inst #4058 = t2LDRHi8 |
| { 4057, 5, 1, 4, 1100, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc8bULL, nullptr, OperandInfo214 }, // Inst #4057 = t2LDRHi12 |
| { 4056, 6, 2, 4, 916, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xcacULL, nullptr, OperandInfo213 }, // Inst #4056 = t2LDRH_PRE |
| { 4055, 6, 2, 4, 410, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xcccULL, nullptr, OperandInfo213 }, // Inst #4055 = t2LDRH_POST |
| { 4054, 5, 1, 4, 412, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc8dULL, nullptr, OperandInfo525 }, // Inst #4054 = t2LDRHT |
| { 4053, 4, 1, 4, 1220, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo523 }, // Inst #4053 = t2LDREXH |
| { 4052, 5, 2, 4, 1019, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xc80ULL, nullptr, OperandInfo524 }, // Inst #4052 = t2LDREXD |
| { 4051, 4, 1, 4, 1220, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo523 }, // Inst #4051 = t2LDREXB |
| { 4050, 5, 1, 4, 1219, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc94ULL, nullptr, OperandInfo530 }, // Inst #4050 = t2LDREX |
| { 4049, 6, 2, 4, 416, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xc91ULL, nullptr, OperandInfo529 }, // Inst #4049 = t2LDRDi8 |
| { 4048, 7, 3, 4, 920, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc91ULL, nullptr, OperandInfo528 }, // Inst #4048 = t2LDRD_PRE |
| { 4047, 7, 3, 4, 419, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc91ULL, nullptr, OperandInfo528 }, // Inst #4047 = t2LDRD_POST |
| { 4046, 6, 1, 4, 393, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc8fULL, nullptr, OperandInfo527 }, // Inst #4046 = t2LDRBs |
| { 4045, 4, 1, 4, 1217, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc90ULL, nullptr, OperandInfo526 }, // Inst #4045 = t2LDRBpci |
| { 4044, 5, 1, 4, 392, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc8eULL, nullptr, OperandInfo214 }, // Inst #4044 = t2LDRBi8 |
| { 4043, 5, 1, 4, 1100, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc8bULL, nullptr, OperandInfo214 }, // Inst #4043 = t2LDRBi12 |
| { 4042, 6, 2, 4, 910, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xcacULL, nullptr, OperandInfo213 }, // Inst #4042 = t2LDRB_PRE |
| { 4041, 6, 2, 4, 925, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xcccULL, nullptr, OperandInfo213 }, // Inst #4041 = t2LDRB_POST |
| { 4040, 5, 1, 4, 412, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc8dULL, nullptr, OperandInfo525 }, // Inst #4040 = t2LDRBT |
| { 4039, 5, 1, 4, 1103, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0xc80ULL, nullptr, OperandInfo66 }, // Inst #4039 = t2LDMIA_UPD |
| { 4038, 4, 0, 4, 1102, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0xc80ULL, nullptr, OperandInfo206 }, // Inst #4038 = t2LDMIA |
| { 4037, 5, 1, 4, 1103, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0xc80ULL, nullptr, OperandInfo66 }, // Inst #4037 = t2LDMDB_UPD |
| { 4036, 4, 0, 4, 1102, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::VariadicOpsAreDefs), 0xc80ULL, nullptr, OperandInfo206 }, // Inst #4036 = t2LDMDB |
| { 4035, 6, 0, 4, 847, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo210 }, // Inst #4035 = t2LDC_PRE |
| { 4034, 6, 0, 4, 847, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo210 }, // Inst #4034 = t2LDC_POST |
| { 4033, 6, 0, 4, 847, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo211 }, // Inst #4033 = t2LDC_OPTION |
| { 4032, 6, 0, 4, 847, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc85ULL, nullptr, OperandInfo210 }, // Inst #4032 = t2LDC_OFFSET |
| { 4031, 6, 0, 4, 847, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo210 }, // Inst #4031 = t2LDCL_PRE |
| { 4030, 6, 0, 4, 847, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo210 }, // Inst #4030 = t2LDCL_POST |
| { 4029, 6, 0, 4, 847, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo211 }, // Inst #4029 = t2LDCL_OPTION |
| { 4028, 6, 0, 4, 847, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc85ULL, nullptr, OperandInfo210 }, // Inst #4028 = t2LDCL_OFFSET |
| { 4027, 6, 0, 4, 847, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo210 }, // Inst #4027 = t2LDC2_PRE |
| { 4026, 6, 0, 4, 847, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo210 }, // Inst #4026 = t2LDC2_POST |
| { 4025, 6, 0, 4, 847, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo211 }, // Inst #4025 = t2LDC2_OPTION |
| { 4024, 6, 0, 4, 847, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc85ULL, nullptr, OperandInfo210 }, // Inst #4024 = t2LDC2_OFFSET |
| { 4023, 6, 0, 4, 847, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo210 }, // Inst #4023 = t2LDC2L_PRE |
| { 4022, 6, 0, 4, 847, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo210 }, // Inst #4022 = t2LDC2L_POST |
| { 4021, 6, 0, 4, 847, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo211 }, // Inst #4021 = t2LDC2L_OPTION |
| { 4020, 6, 0, 4, 847, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc85ULL, nullptr, OperandInfo210 }, // Inst #4020 = t2LDC2L_OFFSET |
| { 4019, 4, 1, 4, 686, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo523 }, // Inst #4019 = t2LDAH |
| { 4018, 4, 1, 4, 686, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo523 }, // Inst #4018 = t2LDAEXH |
| { 4017, 5, 2, 4, 686, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0xc80ULL, nullptr, OperandInfo524 }, // Inst #4017 = t2LDAEXD |
| { 4016, 4, 1, 4, 686, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo523 }, // Inst #4016 = t2LDAEXB |
| { 4015, 4, 1, 4, 686, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo523 }, // Inst #4015 = t2LDAEX |
| { 4014, 4, 1, 4, 686, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo523 }, // Inst #4014 = t2LDAB |
| { 4013, 4, 1, 4, 686, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo523 }, // Inst #4013 = t2LDA |
| { 4012, 2, 0, 12, 1034, 0, 15, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, ImplicitList6, OperandInfo151 }, // Inst #4012 = t2Int_eh_sjlj_setjmp_nofp |
| { 4011, 2, 0, 12, 1034, 0, 27, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, ImplicitList20, OperandInfo151 }, // Inst #4011 = t2Int_eh_sjlj_setjmp |
| { 4010, 2, 0, 2, 456, 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, ImplicitList19, OperandInfo7 }, // Inst #4010 = t2IT |
| { 4009, 3, 0, 4, 1089, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo202 }, // Inst #4009 = t2ISB |
| { 4008, 1, 0, 4, 1212, 0, 0, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo2 }, // Inst #4008 = t2HVC |
| { 4007, 3, 0, 4, 1031, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo202 }, // Inst #4007 = t2HINT |
| { 4006, 7, 1, 4, 1231, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, OperandInfo505 }, // Inst #4006 = t2EORrs |
| { 4005, 6, 1, 4, 702, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, OperandInfo504 }, // Inst #4005 = t2EORrr |
| { 4004, 6, 1, 4, 695, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, OperandInfo503 }, // Inst #4004 = t2EORri |
| { 4003, 3, 0, 4, 1089, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo202 }, // Inst #4003 = t2DSB |
| { 4002, 3, 0, 4, 1089, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo202 }, // Inst #4002 = t2DMB |
| { 4001, 2, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo111 }, // Inst #4001 = t2DLS |
| { 4000, 2, 0, 4, 843, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo139 }, // Inst #4000 = t2DCPS3 |
| { 3999, 2, 0, 4, 843, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo139 }, // Inst #3999 = t2DCPS2 |
| { 3998, 2, 0, 4, 843, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo139 }, // Inst #3998 = t2DCPS1 |
| { 3997, 3, 0, 4, 1053, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo202 }, // Inst #3997 = t2DBG |
| { 3996, 4, 1, 4, 1057, 1, 0, 0, 0xc80ULL, ImplicitList1, OperandInfo522 }, // Inst #3996 = t2CSNEG |
| { 3995, 4, 1, 4, 1057, 1, 0, 0, 0xc80ULL, ImplicitList1, OperandInfo522 }, // Inst #3995 = t2CSINV |
| { 3994, 4, 1, 4, 1057, 1, 0, 0, 0xc80ULL, ImplicitList1, OperandInfo522 }, // Inst #3994 = t2CSINC |
| { 3993, 4, 1, 4, 1057, 1, 0, 0, 0xc80ULL, ImplicitList1, OperandInfo522 }, // Inst #3993 = t2CSEL |
| { 3992, 3, 1, 4, 701, 0, 0, 0, 0xc80ULL, nullptr, OperandInfo85 }, // Inst #3992 = t2CRC32W |
| { 3991, 3, 1, 4, 701, 0, 0, 0, 0xc80ULL, nullptr, OperandInfo85 }, // Inst #3991 = t2CRC32H |
| { 3990, 3, 1, 4, 701, 0, 0, 0, 0xc80ULL, nullptr, OperandInfo85 }, // Inst #3990 = t2CRC32CW |
| { 3989, 3, 1, 4, 701, 0, 0, 0, 0xc80ULL, nullptr, OperandInfo85 }, // Inst #3989 = t2CRC32CH |
| { 3988, 3, 1, 4, 701, 0, 0, 0, 0xc80ULL, nullptr, OperandInfo85 }, // Inst #3988 = t2CRC32CB |
| { 3987, 3, 1, 4, 701, 0, 0, 0, 0xc80ULL, nullptr, OperandInfo85 }, // Inst #3987 = t2CRC32B |
| { 3986, 3, 0, 4, 1052, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo4 }, // Inst #3986 = t2CPS3p |
| { 3985, 2, 0, 4, 1052, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo7 }, // Inst #3985 = t2CPS2p |
| { 3984, 1, 0, 4, 1052, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo2 }, // Inst #3984 = t2CPS1p |
| { 3983, 5, 0, 4, 1234, 0, 1, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL, ImplicitList1, OperandInfo521 }, // Inst #3983 = t2CMPrs |
| { 3982, 4, 0, 4, 1063, 0, 1, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL, ImplicitList1, OperandInfo520 }, // Inst #3982 = t2CMPrr |
| { 3981, 4, 0, 4, 1062, 0, 1, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL, ImplicitList1, OperandInfo113 }, // Inst #3981 = t2CMPri |
| { 3980, 5, 0, 4, 1233, 0, 1, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL, ImplicitList1, OperandInfo521 }, // Inst #3980 = t2CMNzrs |
| { 3979, 4, 0, 4, 1061, 0, 1, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL, ImplicitList1, OperandInfo520 }, // Inst #3979 = t2CMNzrr |
| { 3978, 4, 0, 4, 55, 0, 1, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Predicable), 0xc80ULL, ImplicitList1, OperandInfo113 }, // Inst #3978 = t2CMNri |
| { 3977, 4, 1, 4, 1238, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo519 }, // Inst #3977 = t2CLZ |
| { 3976, 3, 0, 4, 1099, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo150 }, // Inst #3976 = t2CLRM |
| { 3975, 2, 0, 4, 1025, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo139 }, // Inst #3975 = t2CLREX |
| { 3974, 8, 0, 4, 1028, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo195 }, // Inst #3974 = t2CDP2 |
| { 3973, 8, 0, 4, 1028, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo195 }, // Inst #3973 = t2CDP |
| { 3972, 3, 0, 4, 853, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo141 }, // Inst #3972 = t2Bcc |
| { 3971, 3, 0, 4, 863, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo237 }, // Inst #3971 = t2BXJ |
| { 3970, 5, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo518 }, // Inst #3970 = t2BXAUT |
| { 3969, 0, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr }, // Inst #3969 = t2BTI |
| { 3968, 7, 1, 4, 1231, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, OperandInfo505 }, // Inst #3968 = t2BICrs |
| { 3967, 6, 1, 4, 702, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, OperandInfo504 }, // Inst #3967 = t2BICrr |
| { 3966, 6, 1, 4, 695, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, OperandInfo503 }, // Inst #3966 = t2BICri |
| { 3965, 4, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo516 }, // Inst #3965 = t2BFr |
| { 3964, 4, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo517 }, // Inst #3964 = t2BFic |
| { 3963, 4, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo515 }, // Inst #3963 = t2BFi |
| { 3962, 4, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo516 }, // Inst #3962 = t2BFLr |
| { 3961, 4, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo515 }, // Inst #3961 = t2BFLi |
| { 3960, 6, 1, 4, 360, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo514 }, // Inst #3960 = t2BFI |
| { 3959, 5, 1, 4, 359, 0, 0, 0|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo120 }, // Inst #3959 = t2BFC |
| { 3958, 3, 0, 4, 853, 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0xc80ULL, nullptr, OperandInfo141 }, // Inst #3958 = t2B |
| { 3957, 5, 0, 4, 0, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo513 }, // Inst #3957 = t2AUTG |
| { 3956, 0, 0, 4, 0, 3, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, ImplicitList18, nullptr }, // Inst #3956 = t2AUT |
| { 3955, 6, 1, 4, 1060, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, OperandInfo504 }, // Inst #3955 = t2ASRrr |
| { 3954, 6, 1, 4, 1059, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, OperandInfo503 }, // Inst #3954 = t2ASRri |
| { 3953, 7, 1, 4, 706, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, OperandInfo505 }, // Inst #3953 = t2ANDrs |
| { 3952, 6, 1, 4, 702, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, OperandInfo504 }, // Inst #3952 = t2ANDrr |
| { 3951, 6, 1, 4, 695, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, OperandInfo503 }, // Inst #3951 = t2ANDri |
| { 3950, 4, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo512 }, // Inst #3950 = t2ADR |
| { 3949, 5, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo511 }, // Inst #3949 = t2ADDspImm12 |
| { 3948, 6, 1, 4, 1, 0, 0, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, OperandInfo510 }, // Inst #3948 = t2ADDspImm |
| { 3947, 7, 1, 4, 705, 0, 0, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, OperandInfo509 }, // Inst #3947 = t2ADDrs |
| { 3946, 6, 1, 4, 1058, 0, 0, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, OperandInfo508 }, // Inst #3946 = t2ADDrr |
| { 3945, 5, 1, 4, 693, 0, 0, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable), 0xc80ULL, nullptr, OperandInfo507 }, // Inst #3945 = t2ADDri12 |
| { 3944, 6, 1, 4, 1105, 0, 0, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, OperandInfo506 }, // Inst #3944 = t2ADDri |
| { 3943, 7, 1, 4, 705, 1, 1, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0xc80ULL, ImplicitList10, OperandInfo505 }, // Inst #3943 = t2ADCrs |
| { 3942, 6, 1, 4, 700, 1, 1, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0xc80ULL, ImplicitList10, OperandInfo504 }, // Inst #3942 = t2ADCrr |
| { 3941, 6, 1, 4, 693, 1, 1, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0xc80ULL, ImplicitList10, OperandInfo503 }, // Inst #3941 = t2ADCri |
| { 3940, 5, 1, 4, 451, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x564ULL, nullptr, OperandInfo66 }, // Inst #3940 = sysSTMIB_UPD |
| { 3939, 4, 0, 4, 450, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x504ULL, nullptr, OperandInfo206 }, // Inst #3939 = sysSTMIB |
| { 3938, 5, 1, 4, 451, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x564ULL, nullptr, OperandInfo66 }, // Inst #3938 = sysSTMIA_UPD |
| { 3937, 4, 0, 4, 450, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x504ULL, nullptr, OperandInfo206 }, // Inst #3937 = sysSTMIA |
| { 3936, 5, 1, 4, 451, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x564ULL, nullptr, OperandInfo66 }, // Inst #3936 = sysSTMDB_UPD |
| { 3935, 4, 0, 4, 450, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x504ULL, nullptr, OperandInfo206 }, // Inst #3935 = sysSTMDB |
| { 3934, 5, 1, 4, 451, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x564ULL, nullptr, OperandInfo66 }, // Inst #3934 = sysSTMDA_UPD |
| { 3933, 4, 0, 4, 450, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x504ULL, nullptr, OperandInfo206 }, // Inst #3933 = sysSTMDA |
| { 3932, 5, 1, 4, 421, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x564ULL, nullptr, OperandInfo66 }, // Inst #3932 = sysLDMIB_UPD |
| { 3931, 4, 0, 4, 420, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x504ULL, nullptr, OperandInfo206 }, // Inst #3931 = sysLDMIB |
| { 3930, 5, 1, 4, 421, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x564ULL, nullptr, OperandInfo66 }, // Inst #3930 = sysLDMIA_UPD |
| { 3929, 4, 0, 4, 420, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x504ULL, nullptr, OperandInfo206 }, // Inst #3929 = sysLDMIA |
| { 3928, 5, 1, 4, 421, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x564ULL, nullptr, OperandInfo66 }, // Inst #3928 = sysLDMDB_UPD |
| { 3927, 4, 0, 4, 420, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x504ULL, nullptr, OperandInfo206 }, // Inst #3927 = sysLDMDB |
| { 3926, 5, 1, 4, 421, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x564ULL, nullptr, OperandInfo66 }, // Inst #3926 = sysLDMDA_UPD |
| { 3925, 4, 0, 4, 420, 0, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x504ULL, nullptr, OperandInfo206 }, // Inst #3925 = sysLDMDA |
| { 3924, 6, 2, 4, 515, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL, nullptr, OperandInfo497 }, // Inst #3924 = VZIPq8 |
| { 3923, 6, 2, 4, 515, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL, nullptr, OperandInfo497 }, // Inst #3923 = VZIPq32 |
| { 3922, 6, 2, 4, 515, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL, nullptr, OperandInfo497 }, // Inst #3922 = VZIPq16 |
| { 3921, 6, 2, 4, 513, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL, nullptr, OperandInfo496 }, // Inst #3921 = VZIPd8 |
| { 3920, 6, 2, 4, 513, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL, nullptr, OperandInfo496 }, // Inst #3920 = VZIPd16 |
| { 3919, 6, 2, 4, 515, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL, nullptr, OperandInfo497 }, // Inst #3919 = VUZPq8 |
| { 3918, 6, 2, 4, 515, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL, nullptr, OperandInfo497 }, // Inst #3918 = VUZPq32 |
| { 3917, 6, 2, 4, 515, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL, nullptr, OperandInfo497 }, // Inst #3917 = VUZPq16 |
| { 3916, 6, 2, 4, 513, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL, nullptr, OperandInfo496 }, // Inst #3916 = VUZPd8 |
| { 3915, 6, 2, 4, 513, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL, nullptr, OperandInfo496 }, // Inst #3915 = VUZPd16 |
| { 3914, 4, 1, 4, 0, 0, 0, 0, 0x11280ULL, nullptr, OperandInfo162 }, // Inst #3914 = VUSMMLA |
| { 3913, 5, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x11280ULL, nullptr, OperandInfo160 }, // Inst #3913 = VUSDOTQI |
| { 3912, 4, 1, 4, 50, 0, 0, 0, 0x11280ULL, nullptr, OperandInfo162 }, // Inst #3912 = VUSDOTQ |
| { 3911, 5, 1, 4, 0, 0, 0, 0, 0x11280ULL, nullptr, OperandInfo159 }, // Inst #3911 = VUSDOTDI |
| { 3910, 4, 1, 4, 50, 0, 0, 0, 0x11280ULL, nullptr, OperandInfo161 }, // Inst #3910 = VUSDOTD |
| { 3909, 4, 1, 4, 0, 0, 0, 0, 0x11280ULL, nullptr, OperandInfo162 }, // Inst #3909 = VUMMLA |
| { 3908, 5, 1, 4, 222, 0, 0, 0|(1ULL<<MCID::Predicable), 0x28880ULL, nullptr, OperandInfo461 }, // Inst #3908 = VULTOS |
| { 3907, 5, 1, 4, 221, 0, 0, 0, 0x8880ULL, nullptr, OperandInfo461 }, // Inst #3907 = VULTOH |
| { 3906, 5, 1, 4, 220, 0, 0, 0|(1ULL<<MCID::Predicable), 0x8880ULL, nullptr, OperandInfo460 }, // Inst #3906 = VULTOD |
| { 3905, 4, 1, 4, 563, 0, 0, 0|(1ULL<<MCID::Predicable), 0x28880ULL, nullptr, OperandInfo341 }, // Inst #3905 = VUITOS |
| { 3904, 4, 1, 4, 562, 0, 0, 0, 0x8880ULL, nullptr, OperandInfo462 }, // Inst #3904 = VUITOH |
| { 3903, 4, 1, 4, 561, 0, 0, 0|(1ULL<<MCID::Predicable), 0x8880ULL, nullptr, OperandInfo368 }, // Inst #3903 = VUITOD |
| { 3902, 5, 1, 4, 222, 0, 0, 0|(1ULL<<MCID::Predicable), 0x28880ULL, nullptr, OperandInfo461 }, // Inst #3902 = VUHTOS |
| { 3901, 5, 1, 4, 221, 0, 0, 0, 0x8880ULL, nullptr, OperandInfo461 }, // Inst #3901 = VUHTOH |
| { 3900, 5, 1, 4, 220, 0, 0, 0|(1ULL<<MCID::Predicable), 0x8880ULL, nullptr, OperandInfo460 }, // Inst #3900 = VUHTOD |
| { 3899, 5, 1, 4, 959, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x11280ULL, nullptr, OperandInfo160 }, // Inst #3899 = VUDOTQI |
| { 3898, 4, 1, 4, 959, 0, 0, 0, 0x11280ULL, nullptr, OperandInfo162 }, // Inst #3898 = VUDOTQ |
| { 3897, 5, 1, 4, 959, 0, 0, 0, 0x11280ULL, nullptr, OperandInfo159 }, // Inst #3897 = VUDOTDI |
| { 3896, 4, 1, 4, 959, 0, 0, 0, 0x11280ULL, nullptr, OperandInfo161 }, // Inst #3896 = VUDOTD |
| { 3895, 5, 1, 4, 467, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, OperandInfo337 }, // Inst #3895 = VTSTv8i8 |
| { 3894, 5, 1, 4, 466, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, OperandInfo338 }, // Inst #3894 = VTSTv8i16 |
| { 3893, 5, 1, 4, 466, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, OperandInfo338 }, // Inst #3893 = VTSTv4i32 |
| { 3892, 5, 1, 4, 467, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, OperandInfo337 }, // Inst #3892 = VTSTv4i16 |
| { 3891, 5, 1, 4, 467, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, OperandInfo337 }, // Inst #3891 = VTSTv2i32 |
| { 3890, 5, 1, 4, 466, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable), 0x11280ULL, nullptr, OperandInfo338 }, // Inst #3890 = VTSTv16i8 |
| { 3889, 6, 2, 4, 514, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL, nullptr, OperandInfo497 }, // Inst #3889 = VTRNq8 |
| { 3888, 6, 2, 4, 514, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL, nullptr, OperandInfo497 }, // Inst #3888 = VTRNq32 |
| { 3887, 6, 2, 4, 514, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL, nullptr, OperandInfo497 }, // Inst #3887 = VTRNq16 |
| { 3886, 6, 2, 4, 997, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL, nullptr, OperandInfo496 }, // Inst #3886 = VTRNd8 |
| { 3885, 6, 2, 4, 997, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL, nullptr, OperandInfo496 }, // Inst #3885 = VTRNd32 |
| { 3884, 6, 2, 4, 997, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL, nullptr, OperandInfo496 }, // Inst #3884 = VTRNd16 |
| { 3883, 5, 1, 4, 954, 0, 0, 0|(1ULL<<MCID::Predicable), 0x28880ULL, nullptr, OperandInfo461 }, // Inst #3883 = VTOULS |
| { 3882, 5, 1, 4, 565, 0, 0, 0, 0x8880ULL, nullptr, OperandInfo461 }, // Inst #3882 = VTOULH |
| { 3881, 5, 1, 4, 564, 0, 0, 0|(1ULL<<MCID::Predicable), 0x8880ULL, nullptr, OperandInfo460 }, // Inst #3881 = VTOULD |
| { 3880, 4, 1, 4, 566, 0, 0, 0|(1ULL<<MCID::Predicable), 0x28880ULL, nullptr, OperandInfo341 }, // Inst #3880 = VTOUIZS |
| { 3879, 4, 1, 4, 565, 0, 0, 0, 0x8880ULL, nullptr, OperandInfo502 }, // Inst #3879 = VTOUIZH |
| { 3878, 4, 1, 4, 564, 0, 0, 0|(1ULL<<MCID::Predicable), 0x8880ULL, nullptr, OperandInfo369 }, // Inst #3878 = VTOUIZD |
| { 3877, 4, 1, 4, 566, 1, 0, 0|(1ULL<<MCID::Predicable), 0x8880ULL, ImplicitList16, OperandInfo341 }, // Inst #3877 = VTOUIRS |
| { 3876, 4, 1, 4, 565, 1, 0, 0, 0x8880ULL, ImplicitList16, OperandInfo341 }, // Inst #3876 = VTOUIRH |
| { 3875, 4, 1, 4, 564, 1, 0, 0|(1ULL<<MCID::Predicable), 0x8880ULL, ImplicitList16, OperandInfo369 }, // Inst #3875 = VTOUIRD |
| { 3874, 5, 1, 4, 954, 0, 0, 0|(1ULL<<MCID::Predicable), 0x28880ULL, nullptr, OperandInfo461 }, // Inst #3874 = VTOUHS |
| { 3873, 5, 1, 4, 565, 0, 0, 0, 0x8880ULL, nullptr, OperandInfo461 }, // Inst #3873 = VTOUHH |
| { 3872, 5, 1, 4, 564, 0, 0, 0|(1ULL<<MCID::Predicable), 0x8880ULL, nullptr, OperandInfo460 }, // Inst #3872 = VTOUHD |
| { 3871, 5, 1, 4, 954, 0, 0, 0|(1ULL<<MCID::Predicable), 0x28880ULL, nullptr, OperandInfo461 }, // Inst #3871 = VTOSLS |
| { 3870, 5, 1, 4, 565, 0, 0, 0, 0x8880ULL, nullptr, OperandInfo461 }, // Inst #3870 = VTOSLH |
| { 3869, 5, 1, 4, 564, 0, 0, 0|(1ULL<<MCID::Predicable), 0x8880ULL, nullptr, OperandInfo460 }, // Inst #3869 = VTOSLD |
| { 3868, 4, 1, 4, 566, 0, 0, 0|(1ULL<<MCID::Predicable), 0x28880ULL, nullptr, OperandInfo341 }, // Inst #3868 = VTOSIZS |
| { 3867, 4, 1, 4, 565, 0, 0, 0, 0x8880ULL, nullptr, OperandInfo502 }, // Inst #3867 = VTOSIZH |
| { 3866, 4, 1, 4, 564, 0, 0, 0|(1ULL<<MCID::Predicable), 0x8880ULL, nullptr, OperandInfo369 }, // Inst #3866 = VTOSIZD |
| { 3865, 4, 1, 4, 566, 1, 0, 0|(1ULL<<MCID::Predicable), 0x8880ULL, ImplicitList16, OperandInfo341 }, // Inst #3865 = VTOSIRS |
| { 3864, 4, 1, 4, 565, 1, 0, 0, 0x8880ULL, ImplicitList16, OperandInfo341 }, // Inst #3864 = VTOSIRH |
| { 3863, 4, 1, 4, 564, 1, 0, 0|(1ULL<<MCID::Predicable), 0x8880ULL, ImplicitList16, OperandInfo369 }, // Inst #3863 = VTOSIRD |
| { 3862, 5, 1, 4, 566, 0, 0, 0|(1ULL<<MCID::Predicable), 0x28880ULL, nullptr, OperandInfo461 }, // Inst #3862 = VTOSHS |
| { 3861, 5, 1, 4, 565, 0, 0, 0, 0x8880ULL, nullptr, OperandInfo461 }, // Inst #3861 = VTOSHH |
| { 3860, 5, 1, 4, 564, 0, 0, 0|(1ULL<<MCID::Predicable), 0x8880ULL, nullptr, OperandInfo460 }, // Inst #3860 = VTOSHD |
| { 3859, 6, 1, 4, 511, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x10000ULL, nullptr, OperandInfo501 }, // Inst #3859 = VTBX4Pseudo |
| { 3858, 6, 1, 4, 511, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x11480ULL, nullptr, OperandInfo335 }, // Inst #3858 = VTBX4 |
| { 3857, 6, 1, 4, 509, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x10000ULL, nullptr, OperandInfo501 }, // Inst #3857 = VTBX3Pseudo |
| { 3856, 6, 1, 4, 509, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x11480ULL, nullptr, OperandInfo335 }, // Inst #3856 = VTBX3 |
| { 3855, 6, 1, 4, 507, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x11480ULL, nullptr, OperandInfo500 }, // Inst #3855 = VTBX2 |
| { 3854, 6, 1, 4, 505, 0, 0, 0|(1ULL<<MCID::Predicable), 0x11480ULL, nullptr, OperandInfo335 }, // Inst #3854 = VTBX1 |
| { 3853, 5, 1, 4, 510, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x10000ULL, nullptr, OperandInfo499 }, // Inst #3853 = VTBL4Pseudo |
| { 3852, 5, 1, 4, 510, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x11480ULL, nullptr, OperandInfo337 }, // Inst #3852 = VTBL4 |
| { 3851, 5, 1, 4, 508, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x10000ULL, nullptr, OperandInfo499 }, // Inst #3851 = VTBL3Pseudo |
| { 3850, 5, 1, 4, 508, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x11480ULL, nullptr, OperandInfo337 }, // Inst #3850 = VTBL3 |
| { 3849, 5, 1, 4, 506, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x11480ULL, nullptr, OperandInfo498 }, // Inst #3849 = VTBL2 |
| { 3848, 5, 1, 4, 504, 0, 0, 0|(1ULL<<MCID::Predicable), 0x11480ULL, nullptr, OperandInfo337 }, // Inst #3848 = VTBL1 |
| { 3847, 6, 2, 4, 512, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL, nullptr, OperandInfo497 }, // Inst #3847 = VSWPq |
| { 3846, 6, 2, 4, 512, 0, 0, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x11000ULL, nullptr, OperandInfo496 }, // Inst #3846 = VSWPd |
| { 3845, 5, 1, 4, 0, 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x11280ULL, nullptr, OperandInfo160 }, // Inst #3845 = VSUDOTQI |
| { 3844, 5, 1, 4, 0, 0, 0, 0, 0x11280ULL, nullptr, OperandInfo159 }, // Inst #3844 = VSUDOTDI |
| { 3843, 5, 1, 4, 756, 0, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, OperandInfo337 }, // Inst #3843 = VSUBv8i8 |
| { 3842, 5, 1, 4, 460, 0, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, OperandInfo338 }, // Inst #3842 = VSUBv8i16 |
| { 3841, 5, 1, 4, 460, 0, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, OperandInfo338 }, // Inst #3841 = VSUBv4i32 |
| { 3840, 5, 1, 4, 756, 0, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, OperandInfo337 }, // Inst #3840 = VSUBv4i16 |
| { 3839, 5, 1, 4, 460, 0, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, OperandInfo338 }, // Inst #3839 = VSUBv2i64 |
| { 3838, 5, 1, 4, 756, 0, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, OperandInfo337 }, // Inst #3838 = VSUBv2i32 |
| { 3837, 5, 1, 4, 756, 0, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, OperandInfo337 }, // Inst #3837 = VSUBv1i64 |
| { 3836, 5, 1, 4, 460, 0, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, OperandInfo338 }, // Inst #3836 = VSUBv16i8 |
| { 3835, 5, 1, 4, 746, 0, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, OperandInfo338 }, // Inst #3835 = VSUBhq |
| { 3834, 5, 1, 4, 744, 0, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, OperandInfo337 }, // Inst #3834 = VSUBhd |
| { 3833, 5, 1, 4, 745, 0, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, OperandInfo338 }, // Inst #3833 = VSUBfq |
| { 3832, 5, 1, 4, 743, 0, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, OperandInfo337 }, // Inst #3832 = VSUBfd |
| { 3831, 5, 1, 4, 461, 0, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, OperandInfo346 }, // Inst #3831 = VSUBWuv8i16 |
| { 3830, 5, 1, 4, 461, 0, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, OperandInfo346 }, // Inst #3830 = VSUBWuv4i32 |
| { 3829, 5, 1, 4, 461, 0, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, OperandInfo346 }, // Inst #3829 = VSUBWuv2i64 |
| { 3828, 5, 1, 4, 461, 0, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, OperandInfo346 }, // Inst #3828 = VSUBWsv8i16 |
| { 3827, 5, 1, 4, 461, 0, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, OperandInfo346 }, // Inst #3827 = VSUBWsv4i32 |
| { 3826, 5, 1, 4, 461, 0, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, OperandInfo346 }, // Inst #3826 = VSUBWsv2i64 |
| { 3825, 5, 1, 4, 520, 0, 0, 0|(1ULL<<MCID::Predicable), 0x28800ULL, nullptr, OperandInfo345 }, // Inst #3825 = VSUBS |
| { 3824, 5, 1, 4, 758, 0, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, OperandInfo336 }, // Inst #3824 = VSUBLuv8i16 |
| { 3823, 5, 1, 4, 758, 0, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, OperandInfo336 }, // Inst #3823 = VSUBLuv4i32 |
| { 3822, 5, 1, 4, 758, 0, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, OperandInfo336 }, // Inst #3822 = VSUBLuv2i64 |
| { 3821, 5, 1, 4, 758, 0, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, OperandInfo336 }, // Inst #3821 = VSUBLsv8i16 |
| { 3820, 5, 1, 4, 758, 0, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, OperandInfo336 }, // Inst #3820 = VSUBLsv4i32 |
| { 3819, 5, 1, 4, 758, 0, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, OperandInfo336 }, // Inst #3819 = VSUBLsv2i64 |
| { 3818, 5, 1, 4, 500, 0, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, OperandInfo344 }, // Inst #3818 = VSUBHNv8i8 |
| { 3817, 5, 1, 4, 500, 0, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, OperandInfo344 }, // Inst #3817 = VSUBHNv4i16 |
| { 3816, 5, 1, 4, 500, 0, 0, 0|(1ULL<<MCID::Predicable), 0x11280ULL, nullptr, OperandInfo344 }, // Inst #3816 = VSUBHNv2i32 |
| { 3815, 5, 1, 4, 742, 0, 0, 0, 0x8800ULL, nullptr, OperandInfo343 }, // Inst #3815 = VSUBH |
| { 3814, 5, 1, 4, 526, 0, 0, 0|(1ULL<<MCID::Predicable), 0x8800ULL, nullptr, OperandInfo337 }, // Inst #3814 = VSUBD |
| { 3813, 5, 1, 4, 750, 1, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b35ULL, ImplicitList14, OperandInfo424 }, // Inst #3813 = VSTR_VPR_pre |
| { 3812, 5, 1, 4, 750, 1, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL, ImplicitList14, OperandInfo424 }, // Inst #3812 = VSTR_VPR_post |
| { 3811, 4, 0, 4, 750, 1, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL, ImplicitList14, OperandInfo423 }, // Inst #3811 = VSTR_VPR_off |
| { 3810, 6, 1, 4, 750, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b35ULL, nullptr, OperandInfo495 }, // Inst #3810 = VSTR_P0_pre |
| { 3809, 6, 1, 4, 750, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL, nullptr, OperandInfo495 }, // Inst #3809 = VSTR_P0_post |
| { 3808, 5, 0, 4, 750, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL, nullptr, OperandInfo425 }, // Inst #3808 = VSTR_P0_off |
| { 3807, 5, 1, 4, 750, 0, 1, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b35ULL, ImplicitList16, OperandInfo424 }, // Inst #3807 = VSTR_FPSCR_pre |
| { 3806, 5, 1, 4, 750, 0, 1, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL, ImplicitList16, OperandInfo424 }, // Inst #3806 = VSTR_FPSCR_post |
| { 3805, 4, 0, 4, 750, 0, 1, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL, ImplicitList16, OperandInfo423 }, // Inst #3805 = VSTR_FPSCR_off |
| { 3804, 5, 1, 4, 750, 0, 1, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b35ULL, ImplicitList16, OperandInfo424 }, // Inst #3804 = VSTR_FPSCR_NZCVQC_pre |
| { 3803, 5, 1, 4, 750, 0, 1, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL, ImplicitList16, OperandInfo424 }, // Inst #3803 = VSTR_FPSCR_NZCVQC_post |
| { 3802, 4, 0, 4, 750, 0, 1, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL, ImplicitList16, OperandInfo423 }, // Inst #3802 = VSTR_FPSCR_NZCVQC_off |
| { 3801, 5, 1, 4, 750, 0, 1, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b35ULL, ImplicitList16, OperandInfo424 }, // Inst #3801 = VSTR_FPCXTS_pre |
| { 3800, 5, 1, 4, 750, 0, 1, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL, ImplicitList16, OperandInfo424 }, // Inst #3800 = VSTR_FPCXTS_post |
| { 3799, 4, 0, 4, 750, 0, 1, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL, ImplicitList16, OperandInfo423 }, // Inst #3799 = VSTR_FPCXTS_off |
| { 3798, 5, 1, 4, 750, 0, 1, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b35ULL, ImplicitList16, OperandInfo424 }, // Inst #3798 = VSTR_FPCXTNS_pre |
| { 3797, 5, 1, 4, 750, 0, 1, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL, ImplicitList16, OperandInfo424 }, // Inst #3797 = VSTR_FPCXTNS_post |
| { 3796, 4, 0, 4, 750, 0, 1, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x8b55ULL, ImplicitList16, OperandInfo423 }, // Inst #3796 = VSTR_FPCXTNS_off |
| { 3795, 5, 0, 4, 591, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x18b05ULL, nullptr, OperandInfo422 }, // Inst #3795 = VSTRS |
| { 3794, 5, 0, 4, 749, 0, 0, 0|(1ULL<<MCID::MayStore), 0x18b13ULL, nullptr, OperandInfo421 }, // Inst #3794 = VSTRH |
| { 3793, 5, 0, 4, 590, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x18b05ULL, nullptr, OperandInfo99 }, // Inst #3793 = VSTRD |
| { 3792, 5, 1, 4, 966, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x18be4ULL, nullptr, OperandInfo66 }, // Inst #3792 = VSTMSIA_UPD |
| { 3791, 4, 0, 4, 965, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x18b84ULL, nullptr, OperandInfo206 }, // Inst #3791 = VSTMSIA |
| { 3790, 5, 1, 4, 966, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x18be4ULL, nullptr, OperandInfo66 }, // Inst #3790 = VSTMSDB_UPD |
| { 3789, 4, 0, 4, 593, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable), 0x18004ULL, nullptr, OperandInfo420 }, // Inst #3789 = VSTMQIA |
| { 3788, 5, 1, 4, 597, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8be4ULL, nullptr, OperandInfo66 }, // Inst #3788 = VSTMDIA_UPD |
| { 3787, 4, 0, 4, 596, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8b84ULL, nullptr, OperandInfo206 }, // Inst #3787 = VSTMDIA |
| { 3786, 5, 1, 4, 597, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x8be4ULL, nullptr, OperandInfo66 }, // Inst #3786 = VSTMDDB_UPD |
| { 3785, 7, 1, 4, 662, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, OperandInfo477 }, // Inst #3785 = VST4q8oddPseudo_UPD |
| { 3784, 5, 0, 4, 661, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, OperandInfo476 }, // Inst #3784 = VST4q8oddPseudo |
| { 3783, 10, 1, 4, 837, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, OperandInfo494 }, // Inst #3783 = VST4q8_UPD |
| { 3782, 7, 1, 4, 662, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, OperandInfo477 }, // Inst #3782 = VST4q8Pseudo_UPD |
| { 3781, 8, 0, 4, 829, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, OperandInfo493 }, // Inst #3781 = VST4q8 |
| { 3780, 7, 1, 4, 662, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, OperandInfo477 }, // Inst #3780 = VST4q32oddPseudo_UPD |
| { 3779, 5, 0, 4, 661, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, OperandInfo476 }, // Inst #3779 = VST4q32oddPseudo |
| { 3778, 10, 1, 4, 837, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, OperandInfo494 }, // Inst #3778 = VST4q32_UPD |
| { 3777, 7, 1, 4, 662, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, OperandInfo477 }, // Inst #3777 = VST4q32Pseudo_UPD |
| { 3776, 8, 0, 4, 829, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, OperandInfo493 }, // Inst #3776 = VST4q32 |
| { 3775, 7, 1, 4, 662, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, OperandInfo477 }, // Inst #3775 = VST4q16oddPseudo_UPD |
| { 3774, 5, 0, 4, 661, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, OperandInfo476 }, // Inst #3774 = VST4q16oddPseudo |
| { 3773, 10, 1, 4, 837, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, OperandInfo494 }, // Inst #3773 = VST4q16_UPD |
| { 3772, 7, 1, 4, 662, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, OperandInfo477 }, // Inst #3772 = VST4q16Pseudo_UPD |
| { 3771, 8, 0, 4, 829, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, OperandInfo493 }, // Inst #3771 = VST4q16 |
| { 3770, 10, 1, 4, 837, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, OperandInfo494 }, // Inst #3770 = VST4d8_UPD |
| { 3769, 7, 1, 4, 662, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, OperandInfo472 }, // Inst #3769 = VST4d8Pseudo_UPD |
| { 3768, 5, 0, 4, 831, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, OperandInfo470 }, // Inst #3768 = VST4d8Pseudo |
| { 3767, 8, 0, 4, 829, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, OperandInfo493 }, // Inst #3767 = VST4d8 |
| { 3766, 10, 1, 4, 837, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, OperandInfo494 }, // Inst #3766 = VST4d32_UPD |
| { 3765, 7, 1, 4, 662, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, OperandInfo472 }, // Inst #3765 = VST4d32Pseudo_UPD |
| { 3764, 5, 0, 4, 831, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, OperandInfo470 }, // Inst #3764 = VST4d32Pseudo |
| { 3763, 8, 0, 4, 829, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, OperandInfo493 }, // Inst #3763 = VST4d32 |
| { 3762, 10, 1, 4, 837, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, OperandInfo494 }, // Inst #3762 = VST4d16_UPD |
| { 3761, 7, 1, 4, 662, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, OperandInfo472 }, // Inst #3761 = VST4d16Pseudo_UPD |
| { 3760, 5, 0, 4, 831, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, OperandInfo470 }, // Inst #3760 = VST4d16Pseudo |
| { 3759, 8, 0, 4, 829, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, OperandInfo493 }, // Inst #3759 = VST4d16 |
| { 3758, 11, 1, 4, 673, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, OperandInfo492 }, // Inst #3758 = VST4LNq32_UPD |
| { 3757, 8, 1, 4, 674, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, OperandInfo488 }, // Inst #3757 = VST4LNq32Pseudo_UPD |
| { 3756, 6, 0, 4, 672, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, OperandInfo487 }, // Inst #3756 = VST4LNq32Pseudo |
| { 3755, 9, 0, 4, 835, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, OperandInfo491 }, // Inst #3755 = VST4LNq32 |
| { 3754, 11, 1, 4, 673, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, OperandInfo492 }, // Inst #3754 = VST4LNq16_UPD |
| { 3753, 8, 1, 4, 674, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, OperandInfo488 }, // Inst #3753 = VST4LNq16Pseudo_UPD |
| { 3752, 6, 0, 4, 672, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, OperandInfo487 }, // Inst #3752 = VST4LNq16Pseudo |
| { 3751, 9, 0, 4, 835, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, OperandInfo491 }, // Inst #3751 = VST4LNq16 |
| { 3750, 11, 1, 4, 839, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, OperandInfo492 }, // Inst #3750 = VST4LNd8_UPD |
| { 3749, 8, 1, 4, 841, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, OperandInfo483 }, // Inst #3749 = VST4LNd8Pseudo_UPD |
| { 3748, 6, 0, 4, 834, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, OperandInfo482 }, // Inst #3748 = VST4LNd8Pseudo |
| { 3747, 9, 0, 4, 832, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, OperandInfo491 }, // Inst #3747 = VST4LNd8 |
| { 3746, 11, 1, 4, 839, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, OperandInfo492 }, // Inst #3746 = VST4LNd32_UPD |
| { 3745, 8, 1, 4, 841, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, OperandInfo483 }, // Inst #3745 = VST4LNd32Pseudo_UPD |
| { 3744, 6, 0, 4, 834, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, OperandInfo482 }, // Inst #3744 = VST4LNd32Pseudo |
| { 3743, 9, 0, 4, 832, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, OperandInfo491 }, // Inst #3743 = VST4LNd32 |
| { 3742, 11, 1, 4, 839, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, OperandInfo492 }, // Inst #3742 = VST4LNd16_UPD |
| { 3741, 8, 1, 4, 841, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, OperandInfo483 }, // Inst #3741 = VST4LNd16Pseudo_UPD |
| { 3740, 6, 0, 4, 834, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, OperandInfo482 }, // Inst #3740 = VST4LNd16Pseudo |
| { 3739, 9, 0, 4, 832, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, OperandInfo491 }, // Inst #3739 = VST4LNd16 |
| { 3738, 7, 1, 4, 660, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, OperandInfo477 }, // Inst #3738 = VST3q8oddPseudo_UPD |
| { 3737, 5, 0, 4, 659, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, OperandInfo476 }, // Inst #3737 = VST3q8oddPseudo |
| { 3736, 9, 1, 4, 823, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, OperandInfo490 }, // Inst #3736 = VST3q8_UPD |
| { 3735, 7, 1, 4, 660, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, OperandInfo477 }, // Inst #3735 = VST3q8Pseudo_UPD |
| { 3734, 7, 0, 4, 816, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, OperandInfo489 }, // Inst #3734 = VST3q8 |
| { 3733, 7, 1, 4, 660, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, OperandInfo477 }, // Inst #3733 = VST3q32oddPseudo_UPD |
| { 3732, 5, 0, 4, 659, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, OperandInfo476 }, // Inst #3732 = VST3q32oddPseudo |
| { 3731, 9, 1, 4, 823, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, OperandInfo490 }, // Inst #3731 = VST3q32_UPD |
| { 3730, 7, 1, 4, 660, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, OperandInfo477 }, // Inst #3730 = VST3q32Pseudo_UPD |
| { 3729, 7, 0, 4, 816, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, OperandInfo489 }, // Inst #3729 = VST3q32 |
| { 3728, 7, 1, 4, 660, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, OperandInfo477 }, // Inst #3728 = VST3q16oddPseudo_UPD |
| { 3727, 5, 0, 4, 659, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, OperandInfo476 }, // Inst #3727 = VST3q16oddPseudo |
| { 3726, 9, 1, 4, 823, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, OperandInfo490 }, // Inst #3726 = VST3q16_UPD |
| { 3725, 7, 1, 4, 660, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, OperandInfo477 }, // Inst #3725 = VST3q16Pseudo_UPD |
| { 3724, 7, 0, 4, 816, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, OperandInfo489 }, // Inst #3724 = VST3q16 |
| { 3723, 9, 1, 4, 823, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, OperandInfo490 }, // Inst #3723 = VST3d8_UPD |
| { 3722, 7, 1, 4, 660, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, OperandInfo472 }, // Inst #3722 = VST3d8Pseudo_UPD |
| { 3721, 5, 0, 4, 818, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, OperandInfo470 }, // Inst #3721 = VST3d8Pseudo |
| { 3720, 7, 0, 4, 816, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, OperandInfo489 }, // Inst #3720 = VST3d8 |
| { 3719, 9, 1, 4, 823, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, OperandInfo490 }, // Inst #3719 = VST3d32_UPD |
| { 3718, 7, 1, 4, 660, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, OperandInfo472 }, // Inst #3718 = VST3d32Pseudo_UPD |
| { 3717, 5, 0, 4, 818, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, OperandInfo470 }, // Inst #3717 = VST3d32Pseudo |
| { 3716, 7, 0, 4, 816, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, OperandInfo489 }, // Inst #3716 = VST3d32 |
| { 3715, 9, 1, 4, 823, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, OperandInfo490 }, // Inst #3715 = VST3d16_UPD |
| { 3714, 7, 1, 4, 660, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, OperandInfo472 }, // Inst #3714 = VST3d16Pseudo_UPD |
| { 3713, 5, 0, 4, 818, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, OperandInfo470 }, // Inst #3713 = VST3d16Pseudo |
| { 3712, 7, 0, 4, 816, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, OperandInfo489 }, // Inst #3712 = VST3d16 |
| { 3711, 10, 1, 4, 670, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, OperandInfo486 }, // Inst #3711 = VST3LNq32_UPD |
| { 3710, 8, 1, 4, 671, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, OperandInfo488 }, // Inst #3710 = VST3LNq32Pseudo_UPD |
| { 3709, 6, 0, 4, 669, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, OperandInfo487 }, // Inst #3709 = VST3LNq32Pseudo |
| { 3708, 8, 0, 4, 668, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, OperandInfo485 }, // Inst #3708 = VST3LNq32 |
| { 3707, 10, 1, 4, 670, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, OperandInfo486 }, // Inst #3707 = VST3LNq16_UPD |
| { 3706, 8, 1, 4, 671, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, OperandInfo488 }, // Inst #3706 = VST3LNq16Pseudo_UPD |
| { 3705, 6, 0, 4, 669, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, OperandInfo487 }, // Inst #3705 = VST3LNq16Pseudo |
| { 3704, 8, 0, 4, 668, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, OperandInfo485 }, // Inst #3704 = VST3LNq16 |
| { 3703, 10, 1, 4, 825, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, OperandInfo486 }, // Inst #3703 = VST3LNd8_UPD |
| { 3702, 8, 1, 4, 827, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, OperandInfo483 }, // Inst #3702 = VST3LNd8Pseudo_UPD |
| { 3701, 6, 0, 4, 821, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, OperandInfo482 }, // Inst #3701 = VST3LNd8Pseudo |
| { 3700, 8, 0, 4, 819, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, OperandInfo485 }, // Inst #3700 = VST3LNd8 |
| { 3699, 10, 1, 4, 825, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, OperandInfo486 }, // Inst #3699 = VST3LNd32_UPD |
| { 3698, 8, 1, 4, 827, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, OperandInfo483 }, // Inst #3698 = VST3LNd32Pseudo_UPD |
| { 3697, 6, 0, 4, 821, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, OperandInfo482 }, // Inst #3697 = VST3LNd32Pseudo |
| { 3696, 8, 0, 4, 819, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, OperandInfo485 }, // Inst #3696 = VST3LNd32 |
| { 3695, 10, 1, 4, 825, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, OperandInfo486 }, // Inst #3695 = VST3LNd16_UPD |
| { 3694, 8, 1, 4, 827, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, OperandInfo483 }, // Inst #3694 = VST3LNd16Pseudo_UPD |
| { 3693, 6, 0, 4, 821, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, OperandInfo482 }, // Inst #3693 = VST3LNd16Pseudo |
| { 3692, 8, 0, 4, 819, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, OperandInfo485 }, // Inst #3692 = VST3LNd16 |
| { 3691, 7, 1, 4, 657, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, OperandInfo474 }, // Inst #3691 = VST2q8wb_register |
| { 3690, 6, 1, 4, 657, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, OperandInfo473 }, // Inst #3690 = VST2q8wb_fixed |
| { 3689, 7, 1, 4, 658, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, OperandInfo484 }, // Inst #3689 = VST2q8PseudoWB_register |
| { 3688, 6, 1, 4, 658, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, OperandInfo471 }, // Inst #3688 = VST2q8PseudoWB_fixed |
| { 3687, 5, 0, 4, 656, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, OperandInfo470 }, // Inst #3687 = VST2q8Pseudo |
| { 3686, 5, 0, 4, 806, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, OperandInfo469 }, // Inst #3686 = VST2q8 |
| { 3685, 7, 1, 4, 657, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, OperandInfo474 }, // Inst #3685 = VST2q32wb_register |
| { 3684, 6, 1, 4, 657, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, OperandInfo473 }, // Inst #3684 = VST2q32wb_fixed |
| { 3683, 7, 1, 4, 658, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, OperandInfo484 }, // Inst #3683 = VST2q32PseudoWB_register |
| { 3682, 6, 1, 4, 658, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, OperandInfo471 }, // Inst #3682 = VST2q32PseudoWB_fixed |
| { 3681, 5, 0, 4, 656, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, OperandInfo470 }, // Inst #3681 = VST2q32Pseudo |
| { 3680, 5, 0, 4, 806, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, OperandInfo469 }, // Inst #3680 = VST2q32 |
| { 3679, 7, 1, 4, 657, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, OperandInfo474 }, // Inst #3679 = VST2q16wb_register |
| { 3678, 6, 1, 4, 657, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, OperandInfo473 }, // Inst #3678 = VST2q16wb_fixed |
| { 3677, 7, 1, 4, 658, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, OperandInfo484 }, // Inst #3677 = VST2q16PseudoWB_register |
| { 3676, 6, 1, 4, 658, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, OperandInfo471 }, // Inst #3676 = VST2q16PseudoWB_fixed |
| { 3675, 5, 0, 4, 656, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10006ULL, nullptr, OperandInfo470 }, // Inst #3675 = VST2q16Pseudo |
| { 3674, 5, 0, 4, 806, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, OperandInfo469 }, // Inst #3674 = VST2q16 |
| { 3673, 7, 1, 4, 655, 0, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, OperandInfo479 }, // Inst #3673 = VST2d8wb_register |
| { 3672, 6, 1, |
