Rename Subzero traits Operand to AsmOperand
Ice::Operand is a base class representing high-level operands.
X86Operand is a subclass of it which is an x86-specific operand, but
still part of the high-level IR.
The traits Operand has no direct relationship to that hierarchy, and
just holds low-level x86 encoding parameters related to an operand.
Since it's mostly used by the AssemblerX8632[64|32] class, it is being
renamed to AsmOperand to disambiguate it from Ice::Operand.
This is a step towards making the X86 backends traits free.
Bug: b/192890685
Change-Id: I588ca87b73c6502522bb09dd41a9ce73446ea601
Reviewed-on: https://swiftshader-review.googlesource.com/c/SwiftShader/+/55748
Presubmit-Ready: Nicolas Capens <nicolascapens@google.com>
Tested-by: Nicolas Capens <nicolascapens@google.com>
Kokoro-Result: kokoro <noreply+kokoro@google.com>
Reviewed-by: Sean Risser <srisser@google.com>
Reviewed-by: Nicolas Capens <nicolascapens@google.com>
diff --git a/third_party/subzero/src/IceAssemblerX8632.cpp b/third_party/subzero/src/IceAssemblerX8632.cpp
index 492a48b..ca4fd79 100644
--- a/third_party/subzero/src/IceAssemblerX8632.cpp
+++ b/third_party/subzero/src/IceAssemblerX8632.cpp
@@ -1946,9 +1946,9 @@
if (Ty == IceType_i16)
emitOperandSizeOverride();
if (isByteSizedType(Ty)) {
- emitComplexI8(Tag, Operand(reg), imm);
+ emitComplexI8(Tag, AsmOperand(reg), imm);
} else {
- emitComplex(Ty, Tag, Operand(reg), imm);
+ emitComplex(Ty, Tag, AsmOperand(reg), imm);
}
}
@@ -2453,7 +2453,7 @@
}
void AssemblerX8632::rol(Type Ty, GPRRegister operand, GPRRegister shifter) {
- emitGenericShift(0, Ty, Operand(operand), shifter);
+ emitGenericShift(0, Ty, AsmOperand(operand), shifter);
}
void AssemblerX8632::rol(Type Ty, const Address &operand, GPRRegister shifter) {
@@ -2465,7 +2465,7 @@
}
void AssemblerX8632::shl(Type Ty, GPRRegister operand, GPRRegister shifter) {
- emitGenericShift(4, Ty, Operand(operand), shifter);
+ emitGenericShift(4, Ty, AsmOperand(operand), shifter);
}
void AssemblerX8632::shl(Type Ty, const Address &operand, GPRRegister shifter) {
@@ -2477,7 +2477,7 @@
}
void AssemblerX8632::shr(Type Ty, GPRRegister operand, GPRRegister shifter) {
- emitGenericShift(5, Ty, Operand(operand), shifter);
+ emitGenericShift(5, Ty, AsmOperand(operand), shifter);
}
void AssemblerX8632::shr(Type Ty, const Address &operand, GPRRegister shifter) {
@@ -2489,7 +2489,7 @@
}
void AssemblerX8632::sar(Type Ty, GPRRegister operand, GPRRegister shifter) {
- emitGenericShift(7, Ty, Operand(operand), shifter);
+ emitGenericShift(7, Ty, AsmOperand(operand), shifter);
}
void AssemblerX8632::sar(Type Ty, const Address &address, GPRRegister shifter) {
@@ -2974,7 +2974,7 @@
L->bindTo(Bound);
}
-void AssemblerX8632::emitOperand(int rm, const Operand &operand,
+void AssemblerX8632::emitOperand(int rm, const AsmOperand &operand,
RelocOffsetT Addend) {
assert(rm >= 0 && rm < 8);
const intptr_t length = operand.length_;
@@ -3030,7 +3030,7 @@
emitInt32(0);
}
-void AssemblerX8632::emitComplexI8(int rm, const Operand &operand,
+void AssemblerX8632::emitComplexI8(int rm, const AsmOperand &operand,
const Immediate &immediate) {
assert(rm >= 0 && rm < 8);
assert(immediate.is_int8());
@@ -3047,7 +3047,7 @@
}
}
-void AssemblerX8632::emitComplex(Type Ty, int rm, const Operand &operand,
+void AssemblerX8632::emitComplex(Type Ty, int rm, const AsmOperand &operand,
const Immediate &immediate) {
assert(rm >= 0 && rm < 8);
if (immediate.is_int8()) {
@@ -3103,16 +3103,16 @@
emitOperandSizeOverride();
if (imm.value() == 1) {
emitUint8(isByteSizedArithType(Ty) ? 0xD0 : 0xD1);
- emitOperand(rm, Operand(reg));
+ emitOperand(rm, AsmOperand(reg));
} else {
emitUint8(isByteSizedArithType(Ty) ? 0xC0 : 0xC1);
static constexpr RelocOffsetT OffsetFromNextInstruction = 1;
- emitOperand(rm, Operand(reg), OffsetFromNextInstruction);
+ emitOperand(rm, AsmOperand(reg), OffsetFromNextInstruction);
emitUint8(imm.value() & 0xFF);
}
}
-void AssemblerX8632::emitGenericShift(int rm, Type Ty, const Operand &operand,
+void AssemblerX8632::emitGenericShift(int rm, Type Ty, const AsmOperand &operand,
GPRRegister shifter) {
AssemblerBuffer::EnsureCapacity ensured(&Buffer);
assert(shifter == Traits::Encoded_Reg_Counter);
diff --git a/third_party/subzero/src/IceAssemblerX8632.h b/third_party/subzero/src/IceAssemblerX8632.h
index 1f78bf9..dadfc67 100644
--- a/third_party/subzero/src/IceAssemblerX8632.h
+++ b/third_party/subzero/src/IceAssemblerX8632.h
@@ -48,7 +48,7 @@
using BrCond = CondX86::BrCond;
using CmppsCond = CondX86::CmppsCond;
using GPRRegister = typename Traits::GPRRegister;
- using Operand = typename Traits::Operand;
+ using AsmOperand = typename Traits::AsmOperand;
using XmmRegister = typename Traits::XmmRegister;
static constexpr int MAX_NOP_SIZE = 8;
@@ -699,18 +699,18 @@
inline void emitXmmRegisterOperand(RegType reg, RmType rm);
inline void emitOperandSizeOverride();
- void emitOperand(int rm, const Operand &operand, RelocOffsetT Addend = 0);
+ void emitOperand(int rm, const AsmOperand &operand, RelocOffsetT Addend = 0);
void emitImmediate(Type ty, const Immediate &imm);
- void emitComplexI8(int rm, const Operand &operand,
+ void emitComplexI8(int rm, const AsmOperand &operand,
const Immediate &immediate);
- void emitComplex(Type Ty, int rm, const Operand &operand,
+ void emitComplex(Type Ty, int rm, const AsmOperand &operand,
const Immediate &immediate);
void emitLabel(Label *label, intptr_t instruction_size);
void emitLabelLink(Label *label);
void emitNearLabelLink(Label *label);
void emitGenericShift(int rm, Type Ty, GPRRegister reg, const Immediate &imm);
- void emitGenericShift(int rm, Type Ty, const Operand &operand,
+ void emitGenericShift(int rm, Type Ty, const AsmOperand &operand,
GPRRegister shifter);
using LabelVector = std::vector<Label *>;
diff --git a/third_party/subzero/src/IceAssemblerX8664.cpp b/third_party/subzero/src/IceAssemblerX8664.cpp
index 4182654..111cf4a 100644
--- a/third_party/subzero/src/IceAssemblerX8664.cpp
+++ b/third_party/subzero/src/IceAssemblerX8664.cpp
@@ -2079,9 +2079,9 @@
emitOperandSizeOverride();
emitRexB(Ty, reg);
if (isByteSizedType(Ty)) {
- emitComplexI8(Tag, Operand(reg), imm);
+ emitComplexI8(Tag, AsmOperand(reg), imm);
} else {
- emitComplex(Ty, Tag, Operand(reg), imm);
+ emitComplex(Ty, Tag, AsmOperand(reg), imm);
}
}
@@ -2607,7 +2607,7 @@
}
void AssemblerX8664::rol(Type Ty, GPRRegister operand, GPRRegister shifter) {
- emitGenericShift(0, Ty, Operand(operand), shifter);
+ emitGenericShift(0, Ty, AsmOperand(operand), shifter);
}
void AssemblerX8664::rol(Type Ty, const Address &operand, GPRRegister shifter) {
@@ -2619,7 +2619,7 @@
}
void AssemblerX8664::shl(Type Ty, GPRRegister operand, GPRRegister shifter) {
- emitGenericShift(4, Ty, Operand(operand), shifter);
+ emitGenericShift(4, Ty, AsmOperand(operand), shifter);
}
void AssemblerX8664::shl(Type Ty, const Address &operand, GPRRegister shifter) {
@@ -2631,7 +2631,7 @@
}
void AssemblerX8664::shr(Type Ty, GPRRegister operand, GPRRegister shifter) {
- emitGenericShift(5, Ty, Operand(operand), shifter);
+ emitGenericShift(5, Ty, AsmOperand(operand), shifter);
}
void AssemblerX8664::shr(Type Ty, const Address &operand, GPRRegister shifter) {
@@ -2643,7 +2643,7 @@
}
void AssemblerX8664::sar(Type Ty, GPRRegister operand, GPRRegister shifter) {
- emitGenericShift(7, Ty, Operand(operand), shifter);
+ emitGenericShift(7, Ty, AsmOperand(operand), shifter);
}
void AssemblerX8664::sar(Type Ty, const Address &address, GPRRegister shifter) {
@@ -3153,7 +3153,7 @@
L->bindTo(Bound);
}
-void AssemblerX8664::emitOperand(int rm, const Operand &operand,
+void AssemblerX8664::emitOperand(int rm, const AsmOperand &operand,
RelocOffsetT Addend) {
assert(rm >= 0 && rm < 8);
const intptr_t length = operand.length_;
@@ -3209,7 +3209,7 @@
emitInt32(0);
}
-void AssemblerX8664::emitComplexI8(int rm, const Operand &operand,
+void AssemblerX8664::emitComplexI8(int rm, const AsmOperand &operand,
const Immediate &immediate) {
assert(rm >= 0 && rm < 8);
assert(immediate.is_int8());
@@ -3226,7 +3226,7 @@
}
}
-void AssemblerX8664::emitComplex(Type Ty, int rm, const Operand &operand,
+void AssemblerX8664::emitComplex(Type Ty, int rm, const AsmOperand &operand,
const Immediate &immediate) {
assert(rm >= 0 && rm < 8);
if (immediate.is_int8()) {
@@ -3283,16 +3283,16 @@
emitRexB(Ty, reg);
if (imm.value() == 1) {
emitUint8(isByteSizedArithType(Ty) ? 0xD0 : 0xD1);
- emitOperand(rm, Operand(reg));
+ emitOperand(rm, AsmOperand(reg));
} else {
emitUint8(isByteSizedArithType(Ty) ? 0xC0 : 0xC1);
static constexpr RelocOffsetT OffsetFromNextInstruction = 1;
- emitOperand(rm, Operand(reg), OffsetFromNextInstruction);
+ emitOperand(rm, AsmOperand(reg), OffsetFromNextInstruction);
emitUint8(imm.value() & 0xFF);
}
}
-void AssemblerX8664::emitGenericShift(int rm, Type Ty, const Operand &operand,
+void AssemblerX8664::emitGenericShift(int rm, Type Ty, const AsmOperand &operand,
GPRRegister shifter) {
AssemblerBuffer::EnsureCapacity ensured(&Buffer);
assert(shifter == Traits::Encoded_Reg_Counter);
diff --git a/third_party/subzero/src/IceAssemblerX8664.h b/third_party/subzero/src/IceAssemblerX8664.h
index 1bc0d17..f4e7446 100644
--- a/third_party/subzero/src/IceAssemblerX8664.h
+++ b/third_party/subzero/src/IceAssemblerX8664.h
@@ -48,7 +48,7 @@
using BrCond = CondX86::BrCond;
using CmppsCond = CondX86::CmppsCond;
using GPRRegister = typename Traits::GPRRegister;
- using Operand = typename Traits::Operand;
+ using AsmOperand = typename Traits::AsmOperand;
using XmmRegister = typename Traits::XmmRegister;
static constexpr int MAX_NOP_SIZE = 8;
@@ -675,18 +675,18 @@
inline void emitXmmRegisterOperand(RegType reg, RmType rm);
inline void emitOperandSizeOverride();
- void emitOperand(int rm, const Operand &operand, RelocOffsetT Addend = 0);
+ void emitOperand(int rm, const AsmOperand &operand, RelocOffsetT Addend = 0);
void emitImmediate(Type ty, const Immediate &imm);
- void emitComplexI8(int rm, const Operand &operand,
+ void emitComplexI8(int rm, const AsmOperand &operand,
const Immediate &immediate);
- void emitComplex(Type Ty, int rm, const Operand &operand,
+ void emitComplex(Type Ty, int rm, const AsmOperand &operand,
const Immediate &immediate);
void emitLabel(Label *label, intptr_t instruction_size);
void emitLabelLink(Label *label);
void emitNearLabelLink(Label *label);
void emitGenericShift(int rm, Type Ty, GPRRegister reg, const Immediate &imm);
- void emitGenericShift(int rm, Type Ty, const Operand &operand,
+ void emitGenericShift(int rm, Type Ty, const AsmOperand &operand,
GPRRegister shifter);
using LabelVector = std::vector<Label *>;
@@ -752,22 +752,22 @@
const RmType Rm,
const Address *Addr = nullptr) {
const uint8_t W = (TyReg == IceType_i64 || TyRm == IceType_i64)
- ? Operand::RexW
- : Operand::RexNone;
- const uint8_t R = (Reg & 0x08) ? Operand::RexR : Operand::RexNone;
+ ? AsmOperand::RexW
+ : AsmOperand::RexNone;
+ const uint8_t R = (Reg & 0x08) ? AsmOperand::RexR : AsmOperand::RexNone;
const uint8_t X = (Addr != nullptr)
- ? (typename Operand::RexBits)Addr->rexX()
- : Operand::RexNone;
+ ? (typename AsmOperand::RexBits)Addr->rexX()
+ : AsmOperand::RexNone;
const uint8_t B = (Addr != nullptr)
- ? (typename Operand::RexBits)Addr->rexB()
- : (Rm & 0x08) ? Operand::RexB
- : Operand::RexNone;
+ ? (typename AsmOperand::RexBits)Addr->rexB()
+ : (Rm & 0x08) ? AsmOperand::RexB
+ : AsmOperand::RexNone;
const uint8_t Prefix = W | R | X | B;
- if (Prefix != Operand::RexNone) {
+ if (Prefix != AsmOperand::RexNone) {
emitUint8(Prefix);
} else if (is8BitRegisterRequiringRex(TyReg, Reg) ||
(Addr == nullptr && is8BitRegisterRequiringRex(TyRm, Rm))) {
- emitUint8(Operand::RexBase);
+ emitUint8(AsmOperand::RexBase);
}
}
diff --git a/third_party/subzero/src/IceTargetLoweringX8632Traits.h b/third_party/subzero/src/IceTargetLoweringX8632Traits.h
index 72ba759..fd9c6a6 100644
--- a/third_party/subzero/src/IceTargetLoweringX8632Traits.h
+++ b/third_party/subzero/src/IceTargetLoweringX8632Traits.h
@@ -68,14 +68,14 @@
static constexpr FixupKind FK_Gotoff = llvm::ELF::R_386_GOTOFF;
static constexpr FixupKind FK_GotPC = llvm::ELF::R_386_GOTPC;
- class Operand {
+ class AsmOperand {
public:
- Operand(const Operand &other)
+ AsmOperand(const AsmOperand &other)
: fixup_(other.fixup_), length_(other.length_) {
memmove(&encoding_[0], &other.encoding_[0], other.length_);
}
- Operand &operator=(const Operand &other) {
+ AsmOperand &operator=(const AsmOperand &other) {
length_ = other.length_;
fixup_ = other.fixup_;
memmove(&encoding_[0], &other.encoding_[0], other.length_);
@@ -116,7 +116,7 @@
AssemblerFixup *fixup() const { return fixup_; }
protected:
- Operand() : fixup_(nullptr), length_(0) {} // Needed by subclass Address.
+ AsmOperand() : fixup_(nullptr), length_(0) {} // Needed by subclass Address.
void SetModRM(int mod, GPRRegister rm) {
assert((mod & ~3) == 0);
@@ -150,7 +150,7 @@
uint8_t encoding_[6];
uint8_t length_;
- explicit Operand(GPRRegister reg) : fixup_(nullptr) { SetModRM(3, reg); }
+ explicit AsmOperand(GPRRegister reg) : fixup_(nullptr) { SetModRM(3, reg); }
/// Get the operand encoding byte at the given index.
uint8_t encoding_at(intptr_t index) const {
@@ -169,14 +169,14 @@
friend class AssemblerX8632;
};
- class Address : public Operand {
+ class Address : public AsmOperand {
Address() = delete;
public:
- Address(const Address &other) : Operand(other) {}
+ Address(const Address &other) : AsmOperand(other) {}
Address &operator=(const Address &other) {
- Operand::operator=(other);
+ AsmOperand::operator=(other);
return *this;
}
diff --git a/third_party/subzero/src/IceTargetLoweringX8664Traits.h b/third_party/subzero/src/IceTargetLoweringX8664Traits.h
index 502c207..f0e49ba 100644
--- a/third_party/subzero/src/IceTargetLoweringX8664Traits.h
+++ b/third_party/subzero/src/IceTargetLoweringX8664Traits.h
@@ -68,7 +68,7 @@
static constexpr FixupKind FK_Gotoff = llvm::ELF::R_X86_64_GOTOFF64;
static constexpr FixupKind FK_GotPC = llvm::ELF::R_X86_64_GOTPC32;
- class Operand {
+ class AsmOperand {
public:
enum RexBits {
RexNone = 0x00,
@@ -81,13 +81,13 @@
protected:
// Needed by subclass Address.
- Operand() = default;
+ AsmOperand() = default;
public:
- Operand(const Operand &) = default;
- Operand(Operand &&) = default;
- Operand &operator=(const Operand &) = default;
- Operand &operator=(Operand &&) = default;
+ AsmOperand(const AsmOperand &) = default;
+ AsmOperand(AsmOperand &&) = default;
+ AsmOperand &operator=(const AsmOperand &) = default;
+ AsmOperand &operator=(AsmOperand &&) = default;
uint8_t mod() const { return (encoding_at(0) >> 6) & 3; }
@@ -157,7 +157,7 @@
uint8_t encoding_[6];
uint8_t length_ = 0;
- explicit Operand(GPRRegister reg) : fixup_(nullptr) { SetModRM(3, reg); }
+ explicit AsmOperand(GPRRegister reg) : fixup_(nullptr) { SetModRM(3, reg); }
/// Get the operand encoding byte at the given index.
uint8_t encoding_at(intptr_t index) const {
@@ -176,7 +176,7 @@
friend class AssemblerX8664;
};
- class Address : public Operand {
+ class Address : public AsmOperand {
Address() = default;
public:
