test/CodeGen/AArch64/GlobalISel/legalize-nonpowerof2eltsvec.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -run-pass=legalizer %s -o - | FileCheck %s

--- |
  target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
  target triple = "aarch64--"
  define void @test_legalize_merge_v3s64() {
    ret void
  }
...
---
name:            test_legalize_merge_v3s64
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
  - { id: 4, class: _ }
  - { id: 5, class: _ }
body: |
  bb.0:
    liveins: $w0
    ; CHECK-LABEL: name: test_legalize_merge_v3s64
    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
    ; CHECK: [[MV:%[0-9]+]]:_(<3 x s64>) = G_MERGE_VALUES [[COPY]](s64), [[COPY]](s64), [[COPY]](s64)
    ; CHECK: $x0 = COPY [[COPY]](s64)
    ; CHECK: $noreg = PATCHABLE_RET [[MV]](<3 x s64>)
    %0(s64) = COPY $x0
    %1(<3 x s64>) = G_MERGE_VALUES %0(s64), %0(s64), %0(s64)
    %2(s64), %3(s64), %4(s64) = G_UNMERGE_VALUES %1(<3 x s64>)
    $x0 = COPY %3(s64)
    $noreg = PATCHABLE_RET %1(<3 x s64>)
...