| // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s |
| |
| // --------------------------------------------------------------------------// |
| // Immediate out of lower bound [-8, 7]. |
| |
| st1d z25.d, p4, [x16, #-9, MUL VL] |
| // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. |
| // CHECK-NEXT: st1d z25.d, p4, [x16, #-9, MUL VL] |
| // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: |
| |
| // Immediate out of upper bound [-8, 7]. |
| st1d z16.d, p4, [x2, #8, MUL VL] |
| // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7]. |
| // CHECK-NEXT: st1d z16.d, p4, [x2, #8, MUL VL] |
| // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: |
| |
| // --------------------------------------------------------------------------// |
| // Restricted predicate has range [0, 7]. |
| |
| st1d z12.d, p8, [x4, #14, MUL VL] |
| // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7]. |
| // CHECK-NEXT: st1d z12.d, p8, [x4, #14, MUL VL] |
| // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: |
| |
| // --------------------------------------------------------------------------// |
| // Invalid vector list |
| |
| st1d { }, p0, [x0] |
| // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected |
| // CHECK-NEXT: st1d { }, p0, [x0] |
| // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: |
| |
| st1d { z1.d, z2.d }, p0, [x0] |
| // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand |
| // CHECK-NEXT: st1d { z1.d, z2.d }, p0, [x0] |
| // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: |
| |
| st1d { v0.2d }, p0, [x0] |
| // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand |
| // CHECK-NEXT: st1d { v0.2d }, p0, [x0] |
| // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: |
| |
| |
| // --------------------------------------------------------------------------// |
| // Invalid scalar + scalar addressing modes |
| |
| st1d z0.d, p0, [x0, x0] |
| // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3' |
| // CHECK-NEXT: st1d z0.d, p0, [x0, x0] |
| // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: |
| |
| st1d z0.d, p0, [x0, xzr] |
| // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3' |
| // CHECK-NEXT: st1d z0.d, p0, [x0, xzr] |
| // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: |
| |
| st1d z0.d, p0, [x0, x0, lsl #2] |
| // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3' |
| // CHECK-NEXT: st1d z0.d, p0, [x0, x0, lsl #2] |
| // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: |
| |
| st1d z0.d, p0, [x0, w0] |
| // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3' |
| // CHECK-NEXT: st1d z0.d, p0, [x0, w0] |
| // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: |
| |
| st1d z0.d, p0, [x0, w0, uxtw] |
| // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3' |
| // CHECK-NEXT: st1d z0.d, p0, [x0, w0, uxtw] |
| // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: |
| |
| |
| // --------------------------------------------------------------------------// |
| // Invalid scalar + vector addressing modes |
| |
| st1d z0.d, p0, [x0, z0.s] |
| // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand |
| // CHECK-NEXT: st1d z0.d, p0, [x0, z0.s] |
| // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: |
| |
| st1d z0.d, p0, [x0, z0.d, uxtw #2] |
| // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #3' |
| // CHECK-NEXT: st1d z0.d, p0, [x0, z0.d, uxtw #2] |
| // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: |
| |
| st1d z0.d, p0, [x0, z0.d, lsl #2] |
| // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #3' |
| // CHECK-NEXT: st1d z0.d, p0, [x0, z0.d, lsl #2] |
| // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: |
| |
| st1d z0.d, p0, [x0, z0.d, lsl] |
| // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected #imm after shift specifier |
| // CHECK-NEXT: st1d z0.d, p0, [x0, z0.d, lsl] |
| // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: |
| |
| |
| // --------------------------------------------------------------------------// |
| // Invalid vector + immediate addressing modes |
| |
| st1d z0.s, p0, [z0.s] |
| // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width |
| // CHECK-NEXT: st1d z0.s, p0, [z0.s] |
| // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: |
| |
| st1d z0.s, p0, [z0.s, #8] |
| // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width |
| // CHECK-NEXT: st1d z0.s, p0, [z0.s, #8] |
| // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: |
| |
| st1d z0.d, p0, [z0.d, #-1] |
| // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 248]. |
| // CHECK-NEXT: st1d z0.d, p0, [z0.d, #-1] |
| // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: |
| |
| st1d z0.d, p0, [z0.d, #-8] |
| // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 248]. |
| // CHECK-NEXT: st1d z0.d, p0, [z0.d, #-8] |
| // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: |
| |
| st1d z0.d, p0, [z0.d, #249] |
| // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 248]. |
| // CHECK-NEXT: st1d z0.d, p0, [z0.d, #249] |
| // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: |
| |
| st1d z0.d, p0, [z0.d, #256] |
| // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 248]. |
| // CHECK-NEXT: st1d z0.d, p0, [z0.d, #256] |
| // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: |
| |
| st1d z0.d, p0, [z0.d, #3] |
| // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 248]. |
| // CHECK-NEXT: st1d z0.d, p0, [z0.d, #3] |
| // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: |
| |
| |
| // --------------------------------------------------------------------------// |
| // Negative tests for instructions that are incompatible with movprfx |
| |
| movprfx z31.d, p7/z, z6.d |
| st1d { z31.d }, p7, [z31.d, #248] |
| // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov |
| // CHECK-NEXT: st1d { z31.d }, p7, [z31.d, #248] |
| // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: |
| |
| movprfx z31, z6 |
| st1d { z31.d }, p7, [z31.d, #248] |
| // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov |
| // CHECK-NEXT: st1d { z31.d }, p7, [z31.d, #248] |
| // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: |