Pipeline/SpirvShader: Move setActiveLaneMask()
Move `setActiveLaneMask()` from `SpirvShader::EmitState` to `SpirvShader`. Also capitalize the function name, as this is the more common style in this class.
The debugger will want to expose which lanes are active, so we'll need to perform additional work whenever this is called.
This is a no-op change.
Bug: b/145351270
Change-Id: I294c1d7cda08faaa6b784db148b70a7c4d84d431
Reviewed-on: https://swiftshader-review.googlesource.com/c/SwiftShader/+/39886
Kokoro-Presubmit: kokoro <noreply+kokoro@google.com>
Tested-by: Ben Clayton <bclayton@google.com>
Reviewed-by: Antonio Maiorano <amaiorano@google.com>
diff --git a/src/Pipeline/SpirvShader.hpp b/src/Pipeline/SpirvShader.hpp
index 696c47f..ea5bb61 100644
--- a/src/Pipeline/SpirvShader.hpp
+++ b/src/Pipeline/SpirvShader.hpp
@@ -879,11 +879,6 @@
return RValue<SIMD::Int>(storesAndAtomicsMaskValue);
}
- void setActiveLaneMask(RValue<SIMD::Int> mask)
- {
- activeLaneMaskValue = mask.value;
- }
-
// Add a new active lane mask edge from the current block to out.
// The edge mask value will be (mask AND activeLaneMaskValue).
// If multiple active lane masks are added for the same edge, then
@@ -1060,6 +1055,9 @@
// Asserts if from is reachable and the edge does not exist.
RValue<SIMD::Int> GetActiveLaneMaskEdge(EmitState *state, Block::ID from, Block::ID to) const;
+ // Updates the current active lane mask.
+ void SetActiveLaneMask(RValue<SIMD::Int> mask, EmitState *state) const;
+
// Emit all the unvisited blocks (except for ignore) in DFS order,
// starting with id.
void EmitBlocks(Block::ID id, EmitState *state, Block::ID ignore = 0) const;
diff --git a/src/Pipeline/SpirvShaderControlFlow.cpp b/src/Pipeline/SpirvShaderControlFlow.cpp
index 5f7a1b1..7826415 100644
--- a/src/Pipeline/SpirvShaderControlFlow.cpp
+++ b/src/Pipeline/SpirvShaderControlFlow.cpp
@@ -300,7 +300,7 @@
auto inMask = GetActiveLaneMaskEdge(state, in, blockId);
activeLaneMask |= inMask;
}
- state->setActiveLaneMask(activeLaneMask);
+ SetActiveLaneMask(activeLaneMask, state);
}
EmitInstructions(block.begin(), block.end(), state);
@@ -377,7 +377,7 @@
Nucleus::setInsertBlock(headerBasicBlock);
// Load the active lane mask.
- state->setActiveLaneMask(loopActiveLaneMask);
+ SetActiveLaneMask(loopActiveLaneMask, state);
// Emit the non-phi loop header block's instructions.
for(auto insn = block.begin(); insn != block.end(); insn++)
@@ -544,20 +544,20 @@
SpirvShader::EmitResult SpirvShader::EmitUnreachable(InsnIterator insn, EmitState *state) const
{
// TODO: Log something in this case?
- state->setActiveLaneMask(SIMD::Int(0));
+ SetActiveLaneMask(SIMD::Int(0), state);
return EmitResult::Terminator;
}
SpirvShader::EmitResult SpirvShader::EmitReturn(InsnIterator insn, EmitState *state) const
{
- state->setActiveLaneMask(SIMD::Int(0));
+ SetActiveLaneMask(SIMD::Int(0), state);
return EmitResult::Terminator;
}
SpirvShader::EmitResult SpirvShader::EmitKill(InsnIterator insn, EmitState *state) const
{
state->routine->killMask |= SignMask(state->activeLaneMask());
- state->setActiveLaneMask(SIMD::Int(0));
+ SetActiveLaneMask(SIMD::Int(0), state);
return EmitResult::Terminator;
}
@@ -699,4 +699,9 @@
rr::Yield(RValue<Int>(int(res)));
}
+void SpirvShader::SetActiveLaneMask(RValue<SIMD::Int> mask, EmitState *state) const
+{
+ state->activeLaneMaskValue = mask.value;
+}
+
} // namespace sw
\ No newline at end of file
