| /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
| |* *| |
| |* Assembly Writer Source Fragment *| |
| |* *| |
| |* Automatically generated file, do not edit! *| |
| |* *| |
| \*===----------------------------------------------------------------------===*/ |
| |
| /// printInstruction - This method is automatically generated by tablegen |
| /// from the instruction set description. |
| void AArch64AppleInstPrinter::printInstruction(const MCInst *MI, const MCSubtargetInfo &STI, raw_ostream &O) { |
| static const char AsmStrs[] = { |
| /* 0 */ 'l', 'd', '1', 9, 0, |
| /* 5 */ 't', 'r', 'n', '1', 9, 0, |
| /* 11 */ 'z', 'i', 'p', '1', 9, 0, |
| /* 17 */ 'u', 'z', 'p', '1', 9, 0, |
| /* 23 */ 'd', 'c', 'p', 's', '1', 9, 0, |
| /* 30 */ 's', 't', '1', 9, 0, |
| /* 35 */ 'r', 'e', 'v', '3', '2', 9, 0, |
| /* 42 */ 'l', 'd', '2', 9, 0, |
| /* 47 */ 'f', 'c', 'v', 't', 'l', '2', 9, 0, |
| /* 55 */ 't', 'r', 'n', '2', 9, 0, |
| /* 61 */ 'f', 'c', 'v', 't', 'n', '2', 9, 0, |
| /* 69 */ 'f', 'c', 'v', 't', 'x', 'n', '2', 9, 0, |
| /* 78 */ 'z', 'i', 'p', '2', 9, 0, |
| /* 84 */ 'u', 'z', 'p', '2', 9, 0, |
| /* 90 */ 'd', 'c', 'p', 's', '2', 9, 0, |
| /* 97 */ 's', 't', '2', 9, 0, |
| /* 102 */ 'l', 'd', '3', 9, 0, |
| /* 107 */ 'd', 'c', 'p', 's', '3', 9, 0, |
| /* 114 */ 's', 't', '3', 9, 0, |
| /* 119 */ 'l', 'd', '4', 9, 0, |
| /* 124 */ 's', 't', '4', 9, 0, |
| /* 129 */ 'r', 'e', 'v', '1', '6', 9, 0, |
| /* 136 */ 'b', 'r', 'a', 'a', 9, 0, |
| /* 142 */ 'l', 'd', 'r', 'a', 'a', 9, 0, |
| /* 149 */ 'b', 'l', 'r', 'a', 'a', 9, 0, |
| /* 156 */ 'p', 'a', 'c', 'd', 'a', 9, 0, |
| /* 163 */ 'l', 'd', 'a', 'd', 'd', 'a', 9, 0, |
| /* 171 */ 'f', 'a', 'd', 'd', 'a', 9, 0, |
| /* 178 */ 'a', 'u', 't', 'd', 'a', 9, 0, |
| /* 185 */ 'p', 'a', 'c', 'g', 'a', 9, 0, |
| /* 192 */ 'p', 'a', 'c', 'i', 'a', 9, 0, |
| /* 199 */ 'a', 'u', 't', 'i', 'a', 9, 0, |
| /* 206 */ 'b', 'r', 'k', 'a', 9, 0, |
| /* 212 */ 'f', 'c', 'm', 'l', 'a', 9, 0, |
| /* 219 */ 'f', 'm', 'l', 'a', 9, 0, |
| /* 225 */ 'f', 'n', 'm', 'l', 'a', 9, 0, |
| /* 232 */ 'l', 'd', 's', 'm', 'i', 'n', 'a', 9, 0, |
| /* 241 */ 'l', 'd', 'u', 'm', 'i', 'n', 'a', 9, 0, |
| /* 250 */ 'b', 'r', 'k', 'p', 'a', 9, 0, |
| /* 257 */ 'c', 'a', 's', 'p', 'a', 9, 0, |
| /* 264 */ 's', 'w', 'p', 'a', 9, 0, |
| /* 270 */ 'f', 'e', 'x', 'p', 'a', 9, 0, |
| /* 277 */ 'l', 'd', 'c', 'l', 'r', 'a', 9, 0, |
| /* 285 */ 'l', 'd', 'e', 'o', 'r', 'a', 9, 0, |
| /* 293 */ 's', 'r', 's', 'r', 'a', 9, 0, |
| /* 300 */ 'u', 'r', 's', 'r', 'a', 9, 0, |
| /* 307 */ 's', 's', 'r', 'a', 9, 0, |
| /* 313 */ 'u', 's', 'r', 'a', 9, 0, |
| /* 319 */ 'c', 'a', 's', 'a', 9, 0, |
| /* 325 */ 'l', 'd', 's', 'e', 't', 'a', 9, 0, |
| /* 333 */ 'f', 'r', 'i', 'n', 't', 'a', 9, 0, |
| /* 341 */ 'c', 'l', 'a', 's', 't', 'a', 9, 0, |
| /* 349 */ 'l', 'd', 's', 'm', 'a', 'x', 'a', 9, 0, |
| /* 358 */ 'l', 'd', 'u', 'm', 'a', 'x', 'a', 9, 0, |
| /* 367 */ 'p', 'a', 'c', 'd', 'z', 'a', 9, 0, |
| /* 375 */ 'a', 'u', 't', 'd', 'z', 'a', 9, 0, |
| /* 383 */ 'p', 'a', 'c', 'i', 'z', 'a', 9, 0, |
| /* 391 */ 'a', 'u', 't', 'i', 'z', 'a', 9, 0, |
| /* 399 */ 'i', 'n', 's', '.', 'b', 9, 0, |
| /* 406 */ 's', 'm', 'o', 'v', '.', 'b', 9, 0, |
| /* 414 */ 'u', 'm', 'o', 'v', '.', 'b', 9, 0, |
| /* 422 */ 'l', 'd', '1', 'b', 9, 0, |
| /* 428 */ 'l', 'd', 'f', 'f', '1', 'b', 9, 0, |
| /* 436 */ 'l', 'd', 'n', 'f', '1', 'b', 9, 0, |
| /* 444 */ 'l', 'd', 'n', 't', '1', 'b', 9, 0, |
| /* 452 */ 's', 't', 'n', 't', '1', 'b', 9, 0, |
| /* 460 */ 's', 't', '1', 'b', 9, 0, |
| /* 466 */ 'c', 'r', 'c', '3', '2', 'b', 9, 0, |
| /* 474 */ 'l', 'd', '2', 'b', 9, 0, |
| /* 480 */ 's', 't', '2', 'b', 9, 0, |
| /* 486 */ 'l', 'd', '3', 'b', 9, 0, |
| /* 492 */ 's', 't', '3', 'b', 9, 0, |
| /* 498 */ 'l', 'd', '4', 'b', 9, 0, |
| /* 504 */ 's', 't', '4', 'b', 9, 0, |
| /* 510 */ 't', 'r', 'n', '1', '.', '1', '6', 'b', 9, 0, |
| /* 520 */ 'z', 'i', 'p', '1', '.', '1', '6', 'b', 9, 0, |
| /* 530 */ 'u', 'z', 'p', '1', '.', '1', '6', 'b', 9, 0, |
| /* 540 */ 'r', 'e', 'v', '3', '2', '.', '1', '6', 'b', 9, 0, |
| /* 551 */ 'r', 's', 'u', 'b', 'h', 'n', '2', '.', '1', '6', 'b', 9, 0, |
| /* 564 */ 'r', 'a', 'd', 'd', 'h', 'n', '2', '.', '1', '6', 'b', 9, 0, |
| /* 577 */ 's', 'q', 's', 'h', 'r', 'n', '2', '.', '1', '6', 'b', 9, 0, |
| /* 590 */ 'u', 'q', 's', 'h', 'r', 'n', '2', '.', '1', '6', 'b', 9, 0, |
| /* 603 */ 's', 'q', 'r', 's', 'h', 'r', 'n', '2', '.', '1', '6', 'b', 9, 0, |
| /* 617 */ 'u', 'q', 'r', 's', 'h', 'r', 'n', '2', '.', '1', '6', 'b', 9, 0, |
| /* 631 */ 't', 'r', 'n', '2', '.', '1', '6', 'b', 9, 0, |
| /* 641 */ 's', 'q', 'x', 't', 'n', '2', '.', '1', '6', 'b', 9, 0, |
| /* 653 */ 'u', 'q', 'x', 't', 'n', '2', '.', '1', '6', 'b', 9, 0, |
| /* 665 */ 's', 'q', 's', 'h', 'r', 'u', 'n', '2', '.', '1', '6', 'b', 9, 0, |
| /* 679 */ 's', 'q', 'r', 's', 'h', 'r', 'u', 'n', '2', '.', '1', '6', 'b', 9, 0, |
| /* 694 */ 's', 'q', 'x', 't', 'u', 'n', '2', '.', '1', '6', 'b', 9, 0, |
| /* 707 */ 'z', 'i', 'p', '2', '.', '1', '6', 'b', 9, 0, |
| /* 717 */ 'u', 'z', 'p', '2', '.', '1', '6', 'b', 9, 0, |
| /* 727 */ 'r', 'e', 'v', '6', '4', '.', '1', '6', 'b', 9, 0, |
| /* 738 */ 'r', 'e', 'v', '1', '6', '.', '1', '6', 'b', 9, 0, |
| /* 749 */ 's', 'a', 'b', 'a', '.', '1', '6', 'b', 9, 0, |
| /* 759 */ 'u', 'a', 'b', 'a', '.', '1', '6', 'b', 9, 0, |
| /* 769 */ 'm', 'l', 'a', '.', '1', '6', 'b', 9, 0, |
| /* 778 */ 's', 'r', 's', 'r', 'a', '.', '1', '6', 'b', 9, 0, |
| /* 789 */ 'u', 'r', 's', 'r', 'a', '.', '1', '6', 'b', 9, 0, |
| /* 800 */ 's', 's', 'r', 'a', '.', '1', '6', 'b', 9, 0, |
| /* 810 */ 'u', 's', 'r', 'a', '.', '1', '6', 'b', 9, 0, |
| /* 820 */ 's', 'h', 's', 'u', 'b', '.', '1', '6', 'b', 9, 0, |
| /* 831 */ 'u', 'h', 's', 'u', 'b', '.', '1', '6', 'b', 9, 0, |
| /* 842 */ 's', 'q', 's', 'u', 'b', '.', '1', '6', 'b', 9, 0, |
| /* 853 */ 'u', 'q', 's', 'u', 'b', '.', '1', '6', 'b', 9, 0, |
| /* 864 */ 'b', 'i', 'c', '.', '1', '6', 'b', 9, 0, |
| /* 873 */ 'a', 'e', 's', 'i', 'm', 'c', '.', '1', '6', 'b', 9, 0, |
| /* 885 */ 'a', 'e', 's', 'm', 'c', '.', '1', '6', 'b', 9, 0, |
| /* 896 */ 's', 'a', 'b', 'd', '.', '1', '6', 'b', 9, 0, |
| /* 906 */ 'u', 'a', 'b', 'd', '.', '1', '6', 'b', 9, 0, |
| /* 916 */ 's', 'r', 'h', 'a', 'd', 'd', '.', '1', '6', 'b', 9, 0, |
| /* 928 */ 'u', 'r', 'h', 'a', 'd', 'd', '.', '1', '6', 'b', 9, 0, |
| /* 940 */ 's', 'h', 'a', 'd', 'd', '.', '1', '6', 'b', 9, 0, |
| /* 951 */ 'u', 'h', 'a', 'd', 'd', '.', '1', '6', 'b', 9, 0, |
| /* 962 */ 'u', 's', 'q', 'a', 'd', 'd', '.', '1', '6', 'b', 9, 0, |
| /* 974 */ 's', 'u', 'q', 'a', 'd', 'd', '.', '1', '6', 'b', 9, 0, |
| /* 986 */ 'a', 'n', 'd', '.', '1', '6', 'b', 9, 0, |
| /* 995 */ 'a', 'e', 's', 'd', '.', '1', '6', 'b', 9, 0, |
| /* 1005 */ 'c', 'm', 'g', 'e', '.', '1', '6', 'b', 9, 0, |
| /* 1015 */ 'c', 'm', 'l', 'e', '.', '1', '6', 'b', 9, 0, |
| /* 1025 */ 'a', 'e', 's', 'e', '.', '1', '6', 'b', 9, 0, |
| /* 1035 */ 'b', 'i', 'f', '.', '1', '6', 'b', 9, 0, |
| /* 1044 */ 's', 'q', 'n', 'e', 'g', '.', '1', '6', 'b', 9, 0, |
| /* 1055 */ 'c', 'm', 'h', 'i', '.', '1', '6', 'b', 9, 0, |
| /* 1065 */ 's', 'l', 'i', '.', '1', '6', 'b', 9, 0, |
| /* 1074 */ 's', 'r', 'i', '.', '1', '6', 'b', 9, 0, |
| /* 1083 */ 'm', 'o', 'v', 'i', '.', '1', '6', 'b', 9, 0, |
| /* 1093 */ 's', 'q', 's', 'h', 'l', '.', '1', '6', 'b', 9, 0, |
| /* 1104 */ 'u', 'q', 's', 'h', 'l', '.', '1', '6', 'b', 9, 0, |
| /* 1115 */ 's', 'q', 'r', 's', 'h', 'l', '.', '1', '6', 'b', 9, 0, |
| /* 1127 */ 'u', 'q', 'r', 's', 'h', 'l', '.', '1', '6', 'b', 9, 0, |
| /* 1139 */ 's', 'r', 's', 'h', 'l', '.', '1', '6', 'b', 9, 0, |
| /* 1150 */ 'u', 'r', 's', 'h', 'l', '.', '1', '6', 'b', 9, 0, |
| /* 1161 */ 's', 's', 'h', 'l', '.', '1', '6', 'b', 9, 0, |
| /* 1171 */ 'u', 's', 'h', 'l', '.', '1', '6', 'b', 9, 0, |
| /* 1181 */ 'b', 's', 'l', '.', '1', '6', 'b', 9, 0, |
| /* 1190 */ 'p', 'm', 'u', 'l', '.', '1', '6', 'b', 9, 0, |
| /* 1200 */ 's', 'm', 'i', 'n', '.', '1', '6', 'b', 9, 0, |
| /* 1210 */ 'u', 'm', 'i', 'n', '.', '1', '6', 'b', 9, 0, |
| /* 1220 */ 'o', 'r', 'n', '.', '1', '6', 'b', 9, 0, |
| /* 1229 */ 'a', 'd', 'd', 'p', '.', '1', '6', 'b', 9, 0, |
| /* 1239 */ 's', 'm', 'i', 'n', 'p', '.', '1', '6', 'b', 9, 0, |
| /* 1250 */ 'u', 'm', 'i', 'n', 'p', '.', '1', '6', 'b', 9, 0, |
| /* 1261 */ 'd', 'u', 'p', '.', '1', '6', 'b', 9, 0, |
| /* 1270 */ 's', 'm', 'a', 'x', 'p', '.', '1', '6', 'b', 9, 0, |
| /* 1281 */ 'u', 'm', 'a', 'x', 'p', '.', '1', '6', 'b', 9, 0, |
| /* 1292 */ 'c', 'm', 'e', 'q', '.', '1', '6', 'b', 9, 0, |
| /* 1302 */ 's', 'r', 's', 'h', 'r', '.', '1', '6', 'b', 9, 0, |
| /* 1313 */ 'u', 'r', 's', 'h', 'r', '.', '1', '6', 'b', 9, 0, |
| /* 1324 */ 's', 's', 'h', 'r', '.', '1', '6', 'b', 9, 0, |
| /* 1334 */ 'u', 's', 'h', 'r', '.', '1', '6', 'b', 9, 0, |
| /* 1344 */ 'e', 'o', 'r', '.', '1', '6', 'b', 9, 0, |
| /* 1353 */ 'o', 'r', 'r', '.', '1', '6', 'b', 9, 0, |
| /* 1362 */ 's', 'q', 'a', 'b', 's', '.', '1', '6', 'b', 9, 0, |
| /* 1373 */ 'c', 'm', 'h', 's', '.', '1', '6', 'b', 9, 0, |
| /* 1383 */ 'c', 'l', 's', '.', '1', '6', 'b', 9, 0, |
| /* 1392 */ 'm', 'l', 's', '.', '1', '6', 'b', 9, 0, |
| /* 1401 */ 'c', 'm', 'g', 't', '.', '1', '6', 'b', 9, 0, |
| /* 1411 */ 'r', 'b', 'i', 't', '.', '1', '6', 'b', 9, 0, |
| /* 1421 */ 'c', 'm', 'l', 't', '.', '1', '6', 'b', 9, 0, |
| /* 1431 */ 'c', 'n', 't', '.', '1', '6', 'b', 9, 0, |
| /* 1440 */ 'n', 'o', 't', '.', '1', '6', 'b', 9, 0, |
| /* 1449 */ 'c', 'm', 't', 's', 't', '.', '1', '6', 'b', 9, 0, |
| /* 1460 */ 'e', 'x', 't', '.', '1', '6', 'b', 9, 0, |
| /* 1469 */ 's', 'q', 's', 'h', 'l', 'u', '.', '1', '6', 'b', 9, 0, |
| /* 1481 */ 'a', 'd', 'd', 'v', '.', '1', '6', 'b', 9, 0, |
| /* 1491 */ 's', 'a', 'd', 'd', 'l', 'v', '.', '1', '6', 'b', 9, 0, |
| /* 1503 */ 'u', 'a', 'd', 'd', 'l', 'v', '.', '1', '6', 'b', 9, 0, |
| /* 1515 */ 's', 'm', 'i', 'n', 'v', '.', '1', '6', 'b', 9, 0, |
| /* 1526 */ 'u', 'm', 'i', 'n', 'v', '.', '1', '6', 'b', 9, 0, |
| /* 1537 */ 's', 'm', 'a', 'x', 'v', '.', '1', '6', 'b', 9, 0, |
| /* 1548 */ 'u', 'm', 'a', 'x', 'v', '.', '1', '6', 'b', 9, 0, |
| /* 1559 */ 's', 'm', 'a', 'x', '.', '1', '6', 'b', 9, 0, |
| /* 1569 */ 'u', 'm', 'a', 'x', '.', '1', '6', 'b', 9, 0, |
| /* 1579 */ 'c', 'l', 'z', '.', '1', '6', 'b', 9, 0, |
| /* 1588 */ 't', 'r', 'n', '1', '.', '8', 'b', 9, 0, |
| /* 1597 */ 'z', 'i', 'p', '1', '.', '8', 'b', 9, 0, |
| /* 1606 */ 'u', 'z', 'p', '1', '.', '8', 'b', 9, 0, |
| /* 1615 */ 'r', 'e', 'v', '3', '2', '.', '8', 'b', 9, 0, |
| /* 1625 */ 't', 'r', 'n', '2', '.', '8', 'b', 9, 0, |
| /* 1634 */ 'z', 'i', 'p', '2', '.', '8', 'b', 9, 0, |
| /* 1643 */ 'u', 'z', 'p', '2', '.', '8', 'b', 9, 0, |
| /* 1652 */ 'r', 'e', 'v', '6', '4', '.', '8', 'b', 9, 0, |
| /* 1662 */ 'r', 'e', 'v', '1', '6', '.', '8', 'b', 9, 0, |
| /* 1672 */ 's', 'a', 'b', 'a', '.', '8', 'b', 9, 0, |
| /* 1681 */ 'u', 'a', 'b', 'a', '.', '8', 'b', 9, 0, |
| /* 1690 */ 'm', 'l', 'a', '.', '8', 'b', 9, 0, |
| /* 1698 */ 's', 'r', 's', 'r', 'a', '.', '8', 'b', 9, 0, |
| /* 1708 */ 'u', 'r', 's', 'r', 'a', '.', '8', 'b', 9, 0, |
| /* 1718 */ 's', 's', 'r', 'a', '.', '8', 'b', 9, 0, |
| /* 1727 */ 'u', 's', 'r', 'a', '.', '8', 'b', 9, 0, |
| /* 1736 */ 's', 'h', 's', 'u', 'b', '.', '8', 'b', 9, 0, |
| /* 1746 */ 'u', 'h', 's', 'u', 'b', '.', '8', 'b', 9, 0, |
| /* 1756 */ 's', 'q', 's', 'u', 'b', '.', '8', 'b', 9, 0, |
| /* 1766 */ 'u', 'q', 's', 'u', 'b', '.', '8', 'b', 9, 0, |
| /* 1776 */ 'b', 'i', 'c', '.', '8', 'b', 9, 0, |
| /* 1784 */ 's', 'a', 'b', 'd', '.', '8', 'b', 9, 0, |
| /* 1793 */ 'u', 'a', 'b', 'd', '.', '8', 'b', 9, 0, |
| /* 1802 */ 's', 'r', 'h', 'a', 'd', 'd', '.', '8', 'b', 9, 0, |
| /* 1813 */ 'u', 'r', 'h', 'a', 'd', 'd', '.', '8', 'b', 9, 0, |
| /* 1824 */ 's', 'h', 'a', 'd', 'd', '.', '8', 'b', 9, 0, |
| /* 1834 */ 'u', 'h', 'a', 'd', 'd', '.', '8', 'b', 9, 0, |
| /* 1844 */ 'u', 's', 'q', 'a', 'd', 'd', '.', '8', 'b', 9, 0, |
| /* 1855 */ 's', 'u', 'q', 'a', 'd', 'd', '.', '8', 'b', 9, 0, |
| /* 1866 */ 'a', 'n', 'd', '.', '8', 'b', 9, 0, |
| /* 1874 */ 'c', 'm', 'g', 'e', '.', '8', 'b', 9, 0, |
| /* 1883 */ 'c', 'm', 'l', 'e', '.', '8', 'b', 9, 0, |
| /* 1892 */ 'b', 'i', 'f', '.', '8', 'b', 9, 0, |
| /* 1900 */ 's', 'q', 'n', 'e', 'g', '.', '8', 'b', 9, 0, |
| /* 1910 */ 'c', 'm', 'h', 'i', '.', '8', 'b', 9, 0, |
| /* 1919 */ 's', 'l', 'i', '.', '8', 'b', 9, 0, |
| /* 1927 */ 's', 'r', 'i', '.', '8', 'b', 9, 0, |
| /* 1935 */ 'm', 'o', 'v', 'i', '.', '8', 'b', 9, 0, |
| /* 1944 */ 's', 'q', 's', 'h', 'l', '.', '8', 'b', 9, 0, |
| /* 1954 */ 'u', 'q', 's', 'h', 'l', '.', '8', 'b', 9, 0, |
| /* 1964 */ 's', 'q', 'r', 's', 'h', 'l', '.', '8', 'b', 9, 0, |
| /* 1975 */ 'u', 'q', 'r', 's', 'h', 'l', '.', '8', 'b', 9, 0, |
| /* 1986 */ 's', 'r', 's', 'h', 'l', '.', '8', 'b', 9, 0, |
| /* 1996 */ 'u', 'r', 's', 'h', 'l', '.', '8', 'b', 9, 0, |
| /* 2006 */ 's', 's', 'h', 'l', '.', '8', 'b', 9, 0, |
| /* 2015 */ 'u', 's', 'h', 'l', '.', '8', 'b', 9, 0, |
| /* 2024 */ 'b', 's', 'l', '.', '8', 'b', 9, 0, |
| /* 2032 */ 'p', 'm', 'u', 'l', '.', '8', 'b', 9, 0, |
| /* 2041 */ 'r', 's', 'u', 'b', 'h', 'n', '.', '8', 'b', 9, 0, |
| /* 2052 */ 'r', 'a', 'd', 'd', 'h', 'n', '.', '8', 'b', 9, 0, |
| /* 2063 */ 's', 'm', 'i', 'n', '.', '8', 'b', 9, 0, |
| /* 2072 */ 'u', 'm', 'i', 'n', '.', '8', 'b', 9, 0, |
| /* 2081 */ 's', 'q', 's', 'h', 'r', 'n', '.', '8', 'b', 9, 0, |
| /* 2092 */ 'u', 'q', 's', 'h', 'r', 'n', '.', '8', 'b', 9, 0, |
| /* 2103 */ 's', 'q', 'r', 's', 'h', 'r', 'n', '.', '8', 'b', 9, 0, |
| /* 2115 */ 'u', 'q', 'r', 's', 'h', 'r', 'n', '.', '8', 'b', 9, 0, |
| /* 2127 */ 'o', 'r', 'n', '.', '8', 'b', 9, 0, |
| /* 2135 */ 's', 'q', 'x', 't', 'n', '.', '8', 'b', 9, 0, |
| /* 2145 */ 'u', 'q', 'x', 't', 'n', '.', '8', 'b', 9, 0, |
| /* 2155 */ 's', 'q', 's', 'h', 'r', 'u', 'n', '.', '8', 'b', 9, 0, |
| /* 2167 */ 's', 'q', 'r', 's', 'h', 'r', 'u', 'n', '.', '8', 'b', 9, 0, |
| /* 2180 */ 's', 'q', 'x', 't', 'u', 'n', '.', '8', 'b', 9, 0, |
| /* 2191 */ 'a', 'd', 'd', 'p', '.', '8', 'b', 9, 0, |
| /* 2200 */ 's', 'm', 'i', 'n', 'p', '.', '8', 'b', 9, 0, |
| /* 2210 */ 'u', 'm', 'i', 'n', 'p', '.', '8', 'b', 9, 0, |
| /* 2220 */ 'd', 'u', 'p', '.', '8', 'b', 9, 0, |
| /* 2228 */ 's', 'm', 'a', 'x', 'p', '.', '8', 'b', 9, 0, |
| /* 2238 */ 'u', 'm', 'a', 'x', 'p', '.', '8', 'b', 9, 0, |
| /* 2248 */ 'c', 'm', 'e', 'q', '.', '8', 'b', 9, 0, |
| /* 2257 */ 's', 'r', 's', 'h', 'r', '.', '8', 'b', 9, 0, |
| /* 2267 */ 'u', 'r', 's', 'h', 'r', '.', '8', 'b', 9, 0, |
| /* 2277 */ 's', 's', 'h', 'r', '.', '8', 'b', 9, 0, |
| /* 2286 */ 'u', 's', 'h', 'r', '.', '8', 'b', 9, 0, |
| /* 2295 */ 'e', 'o', 'r', '.', '8', 'b', 9, 0, |
| /* 2303 */ 'o', 'r', 'r', '.', '8', 'b', 9, 0, |
| /* 2311 */ 's', 'q', 'a', 'b', 's', '.', '8', 'b', 9, 0, |
| /* 2321 */ 'c', 'm', 'h', 's', '.', '8', 'b', 9, 0, |
| /* 2330 */ 'c', 'l', 's', '.', '8', 'b', 9, 0, |
| /* 2338 */ 'm', 'l', 's', '.', '8', 'b', 9, 0, |
| /* 2346 */ 'c', 'm', 'g', 't', '.', '8', 'b', 9, 0, |
| /* 2355 */ 'r', 'b', 'i', 't', '.', '8', 'b', 9, 0, |
| /* 2364 */ 'c', 'm', 'l', 't', '.', '8', 'b', 9, 0, |
| /* 2373 */ 'c', 'n', 't', '.', '8', 'b', 9, 0, |
| /* 2381 */ 'n', 'o', 't', '.', '8', 'b', 9, 0, |
| /* 2389 */ 'c', 'm', 't', 's', 't', '.', '8', 'b', 9, 0, |
| /* 2399 */ 'e', 'x', 't', '.', '8', 'b', 9, 0, |
| /* 2407 */ 's', 'q', 's', 'h', 'l', 'u', '.', '8', 'b', 9, 0, |
| /* 2418 */ 'a', 'd', 'd', 'v', '.', '8', 'b', 9, 0, |
| /* 2427 */ 's', 'a', 'd', 'd', 'l', 'v', '.', '8', 'b', 9, 0, |
| /* 2438 */ 'u', 'a', 'd', 'd', 'l', 'v', '.', '8', 'b', 9, 0, |
| /* 2449 */ 's', 'm', 'i', 'n', 'v', '.', '8', 'b', 9, 0, |
| /* 2459 */ 'u', 'm', 'i', 'n', 'v', '.', '8', 'b', 9, 0, |
| /* 2469 */ 's', 'm', 'a', 'x', 'v', '.', '8', 'b', 9, 0, |
| /* 2479 */ 'u', 'm', 'a', 'x', 'v', '.', '8', 'b', 9, 0, |
| /* 2489 */ 's', 'm', 'a', 'x', '.', '8', 'b', 9, 0, |
| /* 2498 */ 'u', 'm', 'a', 'x', '.', '8', 'b', 9, 0, |
| /* 2507 */ 'c', 'l', 'z', '.', '8', 'b', 9, 0, |
| /* 2515 */ 'l', 'd', 'a', 'd', 'd', 'a', 'b', 9, 0, |
| /* 2524 */ 'l', 'd', 's', 'm', 'i', 'n', 'a', 'b', 9, 0, |
| /* 2534 */ 'l', 'd', 'u', 'm', 'i', 'n', 'a', 'b', 9, 0, |
| /* 2544 */ 's', 'w', 'p', 'a', 'b', 9, 0, |
| /* 2551 */ 'b', 'r', 'a', 'b', 9, 0, |
| /* 2557 */ 'l', 'd', 'r', 'a', 'b', 9, 0, |
| /* 2564 */ 'b', 'l', 'r', 'a', 'b', 9, 0, |
| /* 2571 */ 'l', 'd', 'c', 'l', 'r', 'a', 'b', 9, 0, |
| /* 2580 */ 'l', 'd', 'e', 'o', 'r', 'a', 'b', 9, 0, |
| /* 2589 */ 'c', 'a', 's', 'a', 'b', 9, 0, |
| /* 2596 */ 'l', 'd', 's', 'e', 't', 'a', 'b', 9, 0, |
| /* 2605 */ 'l', 'd', 's', 'm', 'a', 'x', 'a', 'b', 9, 0, |
| /* 2615 */ 'l', 'd', 'u', 'm', 'a', 'x', 'a', 'b', 9, 0, |
| /* 2625 */ 'c', 'r', 'c', '3', '2', 'c', 'b', 9, 0, |
| /* 2634 */ 's', 'q', 'd', 'e', 'c', 'b', 9, 0, |
| /* 2642 */ 'u', 'q', 'd', 'e', 'c', 'b', 9, 0, |
| /* 2650 */ 's', 'q', 'i', 'n', 'c', 'b', 9, 0, |
| /* 2658 */ 'u', 'q', 'i', 'n', 'c', 'b', 9, 0, |
| /* 2666 */ 'p', 'a', 'c', 'd', 'b', 9, 0, |
| /* 2673 */ 'l', 'd', 'a', 'd', 'd', 'b', 9, 0, |
| /* 2681 */ 'a', 'u', 't', 'd', 'b', 9, 0, |
| /* 2688 */ 'p', 'r', 'f', 'b', 9, 0, |
| /* 2694 */ 'p', 'a', 'c', 'i', 'b', 9, 0, |
| /* 2701 */ 'a', 'u', 't', 'i', 'b', 9, 0, |
| /* 2708 */ 'b', 'r', 'k', 'b', 9, 0, |
| /* 2714 */ 'l', 'd', 'a', 'd', 'd', 'a', 'l', 'b', 9, 0, |
| /* 2724 */ 'l', 'd', 's', 'm', 'i', 'n', 'a', 'l', 'b', 9, 0, |
| /* 2735 */ 'l', 'd', 'u', 'm', 'i', 'n', 'a', 'l', 'b', 9, 0, |
| /* 2746 */ 's', 'w', 'p', 'a', 'l', 'b', 9, 0, |
| /* 2754 */ 'l', 'd', 'c', 'l', 'r', 'a', 'l', 'b', 9, 0, |
| /* 2764 */ 'l', 'd', 'e', 'o', 'r', 'a', 'l', 'b', 9, 0, |
| /* 2774 */ 'c', 'a', 's', 'a', 'l', 'b', 9, 0, |
| /* 2782 */ 'l', 'd', 's', 'e', 't', 'a', 'l', 'b', 9, 0, |
| /* 2792 */ 'l', 'd', 's', 'm', 'a', 'x', 'a', 'l', 'b', 9, 0, |
| /* 2803 */ 'l', 'd', 'u', 'm', 'a', 'x', 'a', 'l', 'b', 9, 0, |
| /* 2814 */ 'l', 'd', 'a', 'd', 'd', 'l', 'b', 9, 0, |
| /* 2823 */ 'l', 'd', 's', 'm', 'i', 'n', 'l', 'b', 9, 0, |
| /* 2833 */ 'l', 'd', 'u', 'm', 'i', 'n', 'l', 'b', 9, 0, |
| /* 2843 */ 's', 'w', 'p', 'l', 'b', 9, 0, |
| /* 2850 */ 'l', 'd', 'c', 'l', 'r', 'l', 'b', 9, 0, |
| /* 2859 */ 'l', 'd', 'e', 'o', 'r', 'l', 'b', 9, 0, |
| /* 2868 */ 'c', 'a', 's', 'l', 'b', 9, 0, |
| /* 2875 */ 'l', 'd', 's', 'e', 't', 'l', 'b', 9, 0, |
| /* 2884 */ 'l', 'd', 's', 'm', 'a', 'x', 'l', 'b', 9, 0, |
| /* 2894 */ 'l', 'd', 'u', 'm', 'a', 'x', 'l', 'b', 9, 0, |
| /* 2904 */ 'd', 'm', 'b', 9, 0, |
| /* 2909 */ 'l', 'd', 's', 'm', 'i', 'n', 'b', 9, 0, |
| /* 2918 */ 'l', 'd', 'u', 'm', 'i', 'n', 'b', 9, 0, |
| /* 2927 */ 'b', 'r', 'k', 'p', 'b', 9, 0, |
| /* 2934 */ 's', 'w', 'p', 'b', 9, 0, |
| /* 2940 */ 'l', 'd', '1', 'r', 'q', 'b', 9, 0, |
| /* 2948 */ 'l', 'd', '1', 'r', 'b', 9, 0, |
| /* 2955 */ 'l', 'd', 'a', 'r', 'b', 9, 0, |
| /* 2962 */ 'l', 'd', 'l', 'a', 'r', 'b', 9, 0, |
| /* 2970 */ 'l', 'd', 'r', 'b', 9, 0, |
| /* 2976 */ 'l', 'd', 'c', 'l', 'r', 'b', 9, 0, |
| /* 2984 */ 's', 't', 'l', 'l', 'r', 'b', 9, 0, |
| /* 2992 */ 's', 't', 'l', 'r', 'b', 9, 0, |
| /* 2999 */ 'l', 'd', 'e', 'o', 'r', 'b', 9, 0, |
| /* 3007 */ 'l', 'd', 'a', 'p', 'r', 'b', 9, 0, |
| /* 3015 */ 'l', 'd', 't', 'r', 'b', 9, 0, |
| /* 3022 */ 's', 't', 'r', 'b', 9, 0, |
| /* 3028 */ 's', 't', 't', 'r', 'b', 9, 0, |
| /* 3035 */ 'l', 'd', 'u', 'r', 'b', 9, 0, |
| /* 3042 */ 's', 't', 'l', 'u', 'r', 'b', 9, 0, |
| /* 3050 */ 'l', 'd', 'a', 'p', 'u', 'r', 'b', 9, 0, |
| /* 3059 */ 's', 't', 'u', 'r', 'b', 9, 0, |
| /* 3066 */ 'l', 'd', 'a', 'x', 'r', 'b', 9, 0, |
| /* 3074 */ 'l', 'd', 'x', 'r', 'b', 9, 0, |
| /* 3081 */ 's', 't', 'l', 'x', 'r', 'b', 9, 0, |
| /* 3089 */ 's', 't', 'x', 'r', 'b', 9, 0, |
| /* 3096 */ 'l', 'd', '1', 's', 'b', 9, 0, |
| /* 3103 */ 'l', 'd', 'f', 'f', '1', 's', 'b', 9, 0, |
| /* 3112 */ 'l', 'd', 'n', 'f', '1', 's', 'b', 9, 0, |
| /* 3121 */ 'c', 'a', 's', 'b', 9, 0, |
| /* 3127 */ 'd', 's', 'b', 9, 0, |
| /* 3132 */ 'i', 's', 'b', 9, 0, |
| /* 3137 */ 'f', 'm', 's', 'b', 9, 0, |
| /* 3143 */ 'f', 'n', 'm', 's', 'b', 9, 0, |
| /* 3150 */ 'l', 'd', '1', 'r', 's', 'b', 9, 0, |
| /* 3158 */ 'l', 'd', 'r', 's', 'b', 9, 0, |
| /* 3165 */ 'l', 'd', 't', 'r', 's', 'b', 9, 0, |
| /* 3173 */ 'l', 'd', 'u', 'r', 's', 'b', 9, 0, |
| /* 3181 */ 'l', 'd', 'a', 'p', 'u', 'r', 's', 'b', 9, 0, |
| /* 3191 */ 't', 's', 'b', 9, 0, |
| /* 3196 */ 'l', 'd', 's', 'e', 't', 'b', 9, 0, |
| /* 3204 */ 'c', 'n', 't', 'b', 9, 0, |
| /* 3210 */ 'c', 'l', 'a', 's', 't', 'b', 9, 0, |
| /* 3218 */ 's', 'x', 't', 'b', 9, 0, |
| /* 3224 */ 'u', 'x', 't', 'b', 9, 0, |
| /* 3230 */ 'f', 's', 'u', 'b', 9, 0, |
| /* 3236 */ 'f', 'm', 's', 'u', 'b', 9, 0, |
| /* 3243 */ 'f', 'n', 'm', 's', 'u', 'b', 9, 0, |
| /* 3251 */ 's', 'q', 's', 'u', 'b', 9, 0, |
| /* 3258 */ 'u', 'q', 's', 'u', 'b', 9, 0, |
| /* 3265 */ 'r', 'e', 'v', 'b', 9, 0, |
| /* 3271 */ 'l', 'd', 's', 'm', 'a', 'x', 'b', 9, 0, |
| /* 3280 */ 'l', 'd', 'u', 'm', 'a', 'x', 'b', 9, 0, |
| /* 3289 */ 'p', 'a', 'c', 'd', 'z', 'b', 9, 0, |
| /* 3297 */ 'a', 'u', 't', 'd', 'z', 'b', 9, 0, |
| /* 3305 */ 'p', 'a', 'c', 'i', 'z', 'b', 9, 0, |
| /* 3313 */ 'a', 'u', 't', 'i', 'z', 'b', 9, 0, |
| /* 3321 */ 's', 'b', 'c', 9, 0, |
| /* 3326 */ 'a', 'd', 'c', 9, 0, |
| /* 3331 */ 'b', 'i', 'c', 9, 0, |
| /* 3336 */ 's', 'm', 'c', 9, 0, |
| /* 3341 */ 'c', 's', 'i', 'n', 'c', 9, 0, |
| /* 3348 */ 'h', 'v', 'c', 9, 0, |
| /* 3353 */ 's', 'v', 'c', 9, 0, |
| /* 3358 */ 'f', 'm', 'l', 'a', '.', 'd', 9, 0, |
| /* 3366 */ 'f', 'm', 'u', 'l', '.', 'd', 9, 0, |
| /* 3374 */ 'f', 'm', 'l', 's', '.', 'd', 9, 0, |
| /* 3382 */ 'i', 'n', 's', '.', 'd', 9, 0, |
| /* 3389 */ 'f', 'm', 'o', 'v', '.', 'd', 9, 0, |
| /* 3397 */ 'u', 'm', 'o', 'v', '.', 'd', 9, 0, |
| /* 3405 */ 'f', 'm', 'u', 'l', 'x', '.', 'd', 9, 0, |
| /* 3414 */ 's', 'a', 'd', 'a', 'l', 'p', '.', '1', 'd', 9, 0, |
| /* 3425 */ 'u', 'a', 'd', 'a', 'l', 'p', '.', '1', 'd', 9, 0, |
| /* 3436 */ 's', 'a', 'd', 'd', 'l', 'p', '.', '1', 'd', 9, 0, |
| /* 3447 */ 'u', 'a', 'd', 'd', 'l', 'p', '.', '1', 'd', 9, 0, |
| /* 3458 */ 'l', 'd', '1', 'd', 9, 0, |
| /* 3464 */ 'l', 'd', 'f', 'f', '1', 'd', 9, 0, |
| /* 3472 */ 'l', 'd', 'n', 'f', '1', 'd', 9, 0, |
| /* 3480 */ 'l', 'd', 'n', 't', '1', 'd', 9, 0, |
| /* 3488 */ 's', 't', 'n', 't', '1', 'd', 9, 0, |
| /* 3496 */ 's', 't', '1', 'd', 9, 0, |
| /* 3502 */ 't', 'r', 'n', '1', '.', '2', 'd', 9, 0, |
| /* 3511 */ 'z', 'i', 'p', '1', '.', '2', 'd', 9, 0, |
| /* 3520 */ 'u', 'z', 'p', '1', '.', '2', 'd', 9, 0, |
| /* 3529 */ 's', 'a', 'b', 'a', 'l', '2', '.', '2', 'd', 9, 0, |
| /* 3540 */ 'u', 'a', 'b', 'a', 'l', '2', '.', '2', 'd', 9, 0, |
| /* 3551 */ 's', 'q', 'd', 'm', 'l', 'a', 'l', '2', '.', '2', 'd', 9, 0, |
| /* 3564 */ 's', 'm', 'l', 'a', 'l', '2', '.', '2', 'd', 9, 0, |
| /* 3575 */ 'u', 'm', 'l', 'a', 'l', '2', '.', '2', 'd', 9, 0, |
| /* 3586 */ 's', 's', 'u', 'b', 'l', '2', '.', '2', 'd', 9, 0, |
| /* 3597 */ 'u', 's', 'u', 'b', 'l', '2', '.', '2', 'd', 9, 0, |
| /* 3608 */ 's', 'a', 'b', 'd', 'l', '2', '.', '2', 'd', 9, 0, |
| /* 3619 */ 'u', 'a', 'b', 'd', 'l', '2', '.', '2', 'd', 9, 0, |
| /* 3630 */ 's', 'a', 'd', 'd', 'l', '2', '.', '2', 'd', 9, 0, |
| /* 3641 */ 'u', 'a', 'd', 'd', 'l', '2', '.', '2', 'd', 9, 0, |
| /* 3652 */ 's', 's', 'h', 'l', 'l', '2', '.', '2', 'd', 9, 0, |
| /* 3663 */ 'u', 's', 'h', 'l', 'l', '2', '.', '2', 'd', 9, 0, |
| /* 3674 */ 's', 'q', 'd', 'm', 'u', 'l', 'l', '2', '.', '2', 'd', 9, 0, |
| /* 3687 */ 's', 'm', 'u', 'l', 'l', '2', '.', '2', 'd', 9, 0, |
| /* 3698 */ 'u', 'm', 'u', 'l', 'l', '2', '.', '2', 'd', 9, 0, |
| /* 3709 */ 's', 'q', 'd', 'm', 'l', 's', 'l', '2', '.', '2', 'd', 9, 0, |
| /* 3722 */ 's', 'm', 'l', 's', 'l', '2', '.', '2', 'd', 9, 0, |
| /* 3733 */ 'u', 'm', 'l', 's', 'l', '2', '.', '2', 'd', 9, 0, |
| /* 3744 */ 't', 'r', 'n', '2', '.', '2', 'd', 9, 0, |
| /* 3753 */ 'z', 'i', 'p', '2', '.', '2', 'd', 9, 0, |
| /* 3762 */ 'u', 'z', 'p', '2', '.', '2', 'd', 9, 0, |
| /* 3771 */ 's', 's', 'u', 'b', 'w', '2', '.', '2', 'd', 9, 0, |
| /* 3782 */ 'u', 's', 'u', 'b', 'w', '2', '.', '2', 'd', 9, 0, |
| /* 3793 */ 's', 'a', 'd', 'd', 'w', '2', '.', '2', 'd', 9, 0, |
| /* 3804 */ 'u', 'a', 'd', 'd', 'w', '2', '.', '2', 'd', 9, 0, |
| /* 3815 */ 'f', 'c', 'm', 'l', 'a', '.', '2', 'd', 9, 0, |
| /* 3825 */ 'f', 'm', 'l', 'a', '.', '2', 'd', 9, 0, |
| /* 3834 */ 's', 'r', 's', 'r', 'a', '.', '2', 'd', 9, 0, |
| /* 3844 */ 'u', 'r', 's', 'r', 'a', '.', '2', 'd', 9, 0, |
| /* 3854 */ 's', 's', 'r', 'a', '.', '2', 'd', 9, 0, |
| /* 3863 */ 'u', 's', 'r', 'a', '.', '2', 'd', 9, 0, |
| /* 3872 */ 'f', 'r', 'i', 'n', 't', 'a', '.', '2', 'd', 9, 0, |
| /* 3883 */ 'f', 's', 'u', 'b', '.', '2', 'd', 9, 0, |
| /* 3892 */ 's', 'q', 's', 'u', 'b', '.', '2', 'd', 9, 0, |
| /* 3902 */ 'u', 'q', 's', 'u', 'b', '.', '2', 'd', 9, 0, |
| /* 3912 */ 'f', 'a', 'b', 'd', '.', '2', 'd', 9, 0, |
| /* 3921 */ 'f', 'c', 'a', 'd', 'd', '.', '2', 'd', 9, 0, |
| /* 3931 */ 'f', 'a', 'd', 'd', '.', '2', 'd', 9, 0, |
| /* 3940 */ 'u', 's', 'q', 'a', 'd', 'd', '.', '2', 'd', 9, 0, |
| /* 3951 */ 's', 'u', 'q', 'a', 'd', 'd', '.', '2', 'd', 9, 0, |
| /* 3962 */ 'f', 'a', 'c', 'g', 'e', '.', '2', 'd', 9, 0, |
| /* 3972 */ 'f', 'c', 'm', 'g', 'e', '.', '2', 'd', 9, 0, |
| /* 3982 */ 'f', 'c', 'm', 'l', 'e', '.', '2', 'd', 9, 0, |
| /* 3992 */ 'f', 'r', 'e', 'c', 'p', 'e', '.', '2', 'd', 9, 0, |
| /* 4003 */ 'f', 'r', 's', 'q', 'r', 't', 'e', '.', '2', 'd', 9, 0, |
| /* 4015 */ 's', 'c', 'v', 't', 'f', '.', '2', 'd', 9, 0, |
| /* 4025 */ 'u', 'c', 'v', 't', 'f', '.', '2', 'd', 9, 0, |
| /* 4035 */ 'f', 'n', 'e', 'g', '.', '2', 'd', 9, 0, |
| /* 4044 */ 's', 'q', 'n', 'e', 'g', '.', '2', 'd', 9, 0, |
| /* 4054 */ 'c', 'm', 'h', 'i', '.', '2', 'd', 9, 0, |
| /* 4063 */ 's', 'l', 'i', '.', '2', 'd', 9, 0, |
| /* 4071 */ 's', 'r', 'i', '.', '2', 'd', 9, 0, |
| /* 4079 */ 'f', 'r', 'i', 'n', 't', 'i', '.', '2', 'd', 9, 0, |
| /* 4090 */ 'm', 'o', 'v', 'i', '.', '2', 'd', 9, 0, |
| /* 4099 */ 's', 'a', 'b', 'a', 'l', '.', '2', 'd', 9, 0, |
| /* 4109 */ 'u', 'a', 'b', 'a', 'l', '.', '2', 'd', 9, 0, |
| /* 4119 */ 's', 'q', 'd', 'm', 'l', 'a', 'l', '.', '2', 'd', 9, 0, |
| /* 4131 */ 's', 'm', 'l', 'a', 'l', '.', '2', 'd', 9, 0, |
| /* 4141 */ 'u', 'm', 'l', 'a', 'l', '.', '2', 'd', 9, 0, |
| /* 4151 */ 's', 's', 'u', 'b', 'l', '.', '2', 'd', 9, 0, |
| /* 4161 */ 'u', 's', 'u', 'b', 'l', '.', '2', 'd', 9, 0, |
| /* 4171 */ 's', 'a', 'b', 'd', 'l', '.', '2', 'd', 9, 0, |
| /* 4181 */ 'u', 'a', 'b', 'd', 'l', '.', '2', 'd', 9, 0, |
| /* 4191 */ 's', 'a', 'd', 'd', 'l', '.', '2', 'd', 9, 0, |
| /* 4201 */ 'u', 'a', 'd', 'd', 'l', '.', '2', 'd', 9, 0, |
| /* 4211 */ 's', 'q', 's', 'h', 'l', '.', '2', 'd', 9, 0, |
| /* 4221 */ 'u', 'q', 's', 'h', 'l', '.', '2', 'd', 9, 0, |
| /* 4231 */ 's', 'q', 'r', 's', 'h', 'l', '.', '2', 'd', 9, 0, |
| /* 4242 */ 'u', 'q', 'r', 's', 'h', 'l', '.', '2', 'd', 9, 0, |
| /* 4253 */ 's', 'r', 's', 'h', 'l', '.', '2', 'd', 9, 0, |
| /* 4263 */ 'u', 'r', 's', 'h', 'l', '.', '2', 'd', 9, 0, |
| /* 4273 */ 's', 's', 'h', 'l', '.', '2', 'd', 9, 0, |
| /* 4282 */ 'u', 's', 'h', 'l', '.', '2', 'd', 9, 0, |
| /* 4291 */ 's', 's', 'h', 'l', 'l', '.', '2', 'd', 9, 0, |
| /* 4301 */ 'u', 's', 'h', 'l', 'l', '.', '2', 'd', 9, 0, |
| /* 4311 */ 's', 'q', 'd', 'm', 'u', 'l', 'l', '.', '2', 'd', 9, 0, |
| /* 4323 */ 's', 'm', 'u', 'l', 'l', '.', '2', 'd', 9, 0, |
| /* 4333 */ 'u', 'm', 'u', 'l', 'l', '.', '2', 'd', 9, 0, |
| /* 4343 */ 's', 'q', 'd', 'm', 'l', 's', 'l', '.', '2', 'd', 9, 0, |
| /* 4355 */ 's', 'm', 'l', 's', 'l', '.', '2', 'd', 9, 0, |
| /* 4365 */ 'u', 'm', 'l', 's', 'l', '.', '2', 'd', 9, 0, |
| /* 4375 */ 'f', 'm', 'u', 'l', '.', '2', 'd', 9, 0, |
| /* 4384 */ 'f', 'm', 'i', 'n', 'n', 'm', '.', '2', 'd', 9, 0, |
| /* 4395 */ 'f', 'm', 'a', 'x', 'n', 'm', '.', '2', 'd', 9, 0, |
| /* 4406 */ 'f', 'r', 'i', 'n', 't', 'm', '.', '2', 'd', 9, 0, |
| /* 4417 */ 'f', 'm', 'i', 'n', '.', '2', 'd', 9, 0, |
| /* 4426 */ 'f', 'r', 'i', 'n', 't', 'n', '.', '2', 'd', 9, 0, |
| /* 4437 */ 'f', 'a', 'd', 'd', 'p', '.', '2', 'd', 9, 0, |
| /* 4447 */ 's', 'a', 'd', 'a', 'l', 'p', '.', '2', 'd', 9, 0, |
| /* 4458 */ 'u', 'a', 'd', 'a', 'l', 'p', '.', '2', 'd', 9, 0, |
| /* 4469 */ 's', 'a', 'd', 'd', 'l', 'p', '.', '2', 'd', 9, 0, |
| /* 4480 */ 'u', 'a', 'd', 'd', 'l', 'p', '.', '2', 'd', 9, 0, |
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| /* 4503 */ 'f', 'm', 'a', 'x', 'n', 'm', 'p', '.', '2', 'd', 9, 0, |
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| /* 9081 */ 's', 'q', 'i', 'n', 'c', 'h', 9, 0, |
| /* 9089 */ 'u', 'q', 'i', 'n', 'c', 'h', 9, 0, |
| /* 9097 */ 'l', 'd', 'a', 'd', 'd', 'h', 9, 0, |
| /* 9105 */ 'p', 'r', 'f', 'h', 9, 0, |
| /* 9111 */ 'l', 'd', 'a', 'd', 'd', 'a', 'l', 'h', 9, 0, |
| /* 9121 */ 'l', 'd', 's', 'm', 'i', 'n', 'a', 'l', 'h', 9, 0, |
| /* 9132 */ 'l', 'd', 'u', 'm', 'i', 'n', 'a', 'l', 'h', 9, 0, |
| /* 9143 */ 's', 'w', 'p', 'a', 'l', 'h', 9, 0, |
| /* 9151 */ 'l', 'd', 'c', 'l', 'r', 'a', 'l', 'h', 9, 0, |
| /* 9161 */ 'l', 'd', 'e', 'o', 'r', 'a', 'l', 'h', 9, 0, |
| /* 9171 */ 'c', 'a', 's', 'a', 'l', 'h', 9, 0, |
| /* 9179 */ 'l', 'd', 's', 'e', 't', 'a', 'l', 'h', 9, 0, |
| /* 9189 */ 'l', 'd', 's', 'm', 'a', 'x', 'a', 'l', 'h', 9, 0, |
| /* 9200 */ 'l', 'd', 'u', 'm', 'a', 'x', 'a', 'l', 'h', 9, 0, |
| /* 9211 */ 'l', 'd', 'a', 'd', 'd', 'l', 'h', 9, 0, |
| /* 9220 */ 'l', 'd', 's', 'm', 'i', 'n', 'l', 'h', 9, 0, |
| /* 9230 */ 'l', 'd', 'u', 'm', 'i', 'n', 'l', 'h', 9, 0, |
| /* 9240 */ 's', 'w', 'p', 'l', 'h', 9, 0, |
| /* 9247 */ 'l', 'd', 'c', 'l', 'r', 'l', 'h', 9, 0, |
| /* 9256 */ 'l', 'd', 'e', 'o', 'r', 'l', 'h', 9, 0, |
| /* 9265 */ 'c', 'a', 's', 'l', 'h', 9, 0, |
| /* 9272 */ 'l', 'd', 's', 'e', 't', 'l', 'h', 9, 0, |
| /* 9281 */ 's', 'q', 'd', 'm', 'u', 'l', 'h', 9, 0, |
| /* 9290 */ 's', 'q', 'r', 'd', 'm', 'u', 'l', 'h', 9, 0, |
| /* 9300 */ 's', 'm', 'u', 'l', 'h', 9, 0, |
| /* 9307 */ 'u', 'm', 'u', 'l', 'h', 9, 0, |
| /* 9314 */ 'l', 'd', 's', 'm', 'a', 'x', 'l', 'h', 9, 0, |
| /* 9324 */ 'l', 'd', 'u', 'm', 'a', 'x', 'l', 'h', 9, 0, |
| /* 9334 */ 'l', 'd', 's', 'm', 'i', 'n', 'h', 9, 0, |
| /* 9343 */ 'l', 'd', 'u', 'm', 'i', 'n', 'h', 9, 0, |
| /* 9352 */ 's', 'w', 'p', 'h', 9, 0, |
| /* 9358 */ 'l', 'd', '1', 'r', 'q', 'h', 9, 0, |
| /* 9366 */ 'l', 'd', '1', 'r', 'h', 9, 0, |
| /* 9373 */ 'l', 'd', 'a', 'r', 'h', 9, 0, |
| /* 9380 */ 'l', 'd', 'l', 'a', 'r', 'h', 9, 0, |
| /* 9388 */ 'l', 'd', 'r', 'h', 9, 0, |
| /* 9394 */ 'l', 'd', 'c', 'l', 'r', 'h', 9, 0, |
| /* 9402 */ 's', 't', 'l', 'l', 'r', 'h', 9, 0, |
| /* 9410 */ 's', 't', 'l', 'r', 'h', 9, 0, |
| /* 9417 */ 'l', 'd', 'e', 'o', 'r', 'h', 9, 0, |
| /* 9425 */ 'l', 'd', 'a', 'p', 'r', 'h', 9, 0, |
| /* 9433 */ 'l', 'd', 't', 'r', 'h', 9, 0, |
| /* 9440 */ 's', 't', 'r', 'h', 9, 0, |
| /* 9446 */ 's', 't', 't', 'r', 'h', 9, 0, |
| /* 9453 */ 'l', 'd', 'u', 'r', 'h', 9, 0, |
| /* 9460 */ 's', 't', 'l', 'u', 'r', 'h', 9, 0, |
| /* 9468 */ 'l', 'd', 'a', 'p', 'u', 'r', 'h', 9, 0, |
| /* 9477 */ 's', 't', 'u', 'r', 'h', 9, 0, |
| /* 9484 */ 'l', 'd', 'a', 'x', 'r', 'h', 9, 0, |
| /* 9492 */ 'l', 'd', 'x', 'r', 'h', 9, 0, |
| /* 9499 */ 's', 't', 'l', 'x', 'r', 'h', 9, 0, |
| /* 9507 */ 's', 't', 'x', 'r', 'h', 9, 0, |
| /* 9514 */ 'l', 'd', '1', 's', 'h', 9, 0, |
| /* 9521 */ 'l', 'd', 'f', 'f', '1', 's', 'h', 9, 0, |
| /* 9530 */ 'l', 'd', 'n', 'f', '1', 's', 'h', 9, 0, |
| /* 9539 */ 'c', 'a', 's', 'h', 9, 0, |
| /* 9545 */ 's', 'q', 'r', 'd', 'm', 'l', 's', 'h', 9, 0, |
| /* 9555 */ 'l', 'd', '1', 'r', 's', 'h', 9, 0, |
| /* 9563 */ 'l', 'd', 'r', 's', 'h', 9, 0, |
| /* 9570 */ 'l', 'd', 't', 'r', 's', 'h', 9, 0, |
| /* 9578 */ 'l', 'd', 'u', 'r', 's', 'h', 9, 0, |
| /* 9586 */ 'l', 'd', 'a', 'p', 'u', 'r', 's', 'h', 9, 0, |
| /* 9596 */ 'l', 'd', 's', 'e', 't', 'h', 9, 0, |
| /* 9604 */ 'c', 'n', 't', 'h', 9, 0, |
| /* 9610 */ 's', 'x', 't', 'h', 9, 0, |
| /* 9616 */ 'u', 'x', 't', 'h', 9, 0, |
| /* 9622 */ 'r', 'e', 'v', 'h', 9, 0, |
| /* 9628 */ 'l', 'd', 's', 'm', 'a', 'x', 'h', 9, 0, |
| /* 9637 */ 'l', 'd', 'u', 'm', 'a', 'x', 'h', 9, 0, |
| /* 9646 */ 'x', 'p', 'a', 'c', 'i', 9, 0, |
| /* 9653 */ 'p', 'u', 'n', 'p', 'k', 'h', 'i', 9, 0, |
| /* 9662 */ 's', 'u', 'n', 'p', 'k', 'h', 'i', 9, 0, |
| /* 9671 */ 'u', 'u', 'n', 'p', 'k', 'h', 'i', 9, 0, |
| /* 9680 */ 'c', 'm', 'h', 'i', 9, 0, |
| /* 9686 */ 'c', 'm', 'p', 'h', 'i', 9, 0, |
| /* 9693 */ 's', 'l', 'i', 9, 0, |
| /* 9698 */ 's', 'r', 'i', 9, 0, |
| /* 9703 */ 'f', 'r', 'i', 'n', 't', 'i', 9, 0, |
| /* 9711 */ 'm', 'o', 'v', 'i', 9, 0, |
| /* 9717 */ 'b', 'r', 'k', 9, 0, |
| /* 9722 */ 'm', 'o', 'v', 'k', 9, 0, |
| /* 9728 */ 'l', 'd', 'a', 'd', 'd', 'a', 'l', 9, 0, |
| /* 9737 */ 's', 'q', 'd', 'm', 'l', 'a', 'l', 9, 0, |
| /* 9746 */ 'l', 'd', 's', 'm', 'i', 'n', 'a', 'l', 9, 0, |
| /* 9756 */ 'l', 'd', 'u', 'm', 'i', 'n', 'a', 'l', 9, 0, |
| /* 9766 */ 'c', 'a', 's', 'p', 'a', 'l', 9, 0, |
| /* 9774 */ 's', 'w', 'p', 'a', 'l', 9, 0, |
| /* 9781 */ 'l', 'd', 'c', 'l', 'r', 'a', 'l', 9, 0, |
| /* 9790 */ 'l', 'd', 'e', 'o', 'r', 'a', 'l', 9, 0, |
| /* 9799 */ 'c', 'a', 's', 'a', 'l', 9, 0, |
| /* 9806 */ 'l', 'd', 's', 'e', 't', 'a', 'l', 9, 0, |
| /* 9815 */ 'l', 'd', 's', 'm', 'a', 'x', 'a', 'l', 9, 0, |
| /* 9825 */ 'l', 'd', 'u', 'm', 'a', 'x', 'a', 'l', 9, 0, |
| /* 9835 */ 't', 'b', 'l', 9, 0, |
| /* 9840 */ 's', 'm', 's', 'u', 'b', 'l', 9, 0, |
| /* 9848 */ 'u', 'm', 's', 'u', 'b', 'l', 9, 0, |
| /* 9856 */ 'l', 'd', 'a', 'd', 'd', 'l', 9, 0, |
| /* 9864 */ 's', 'm', 'a', 'd', 'd', 'l', 9, 0, |
| /* 9872 */ 'u', 'm', 'a', 'd', 'd', 'l', 9, 0, |
| /* 9880 */ 'f', 'c', 's', 'e', 'l', 9, 0, |
| /* 9887 */ 'f', 't', 's', 's', 'e', 'l', 9, 0, |
| /* 9895 */ 's', 'q', 's', 'h', 'l', 9, 0, |
| /* 9902 */ 'u', 'q', 's', 'h', 'l', 9, 0, |
| /* 9909 */ 's', 'q', 'r', 's', 'h', 'l', 9, 0, |
| /* 9917 */ 'u', 'q', 'r', 's', 'h', 'l', 9, 0, |
| /* 9925 */ 's', 'r', 's', 'h', 'l', 9, 0, |
| /* 9932 */ 'u', 'r', 's', 'h', 'l', 9, 0, |
| /* 9939 */ 's', 's', 'h', 'l', 9, 0, |
| /* 9945 */ 'u', 's', 'h', 'l', 9, 0, |
| /* 9951 */ 's', 'q', 'd', 'm', 'u', 'l', 'l', 9, 0, |
| /* 9960 */ 'l', 'd', 's', 'm', 'i', 'n', 'l', 9, 0, |
| /* 9969 */ 'l', 'd', 'u', 'm', 'i', 'n', 'l', 9, 0, |
| /* 9978 */ 'a', 'd', 'd', 'p', 'l', 9, 0, |
| /* 9985 */ 'c', 'a', 's', 'p', 'l', 9, 0, |
| /* 9992 */ 's', 'w', 'p', 'l', 9, 0, |
| /* 9998 */ 'l', 'd', 'c', 'l', 'r', 'l', 9, 0, |
| /* 10006 */ 'l', 'd', 'e', 'o', 'r', 'l', 9, 0, |
| /* 10014 */ 'c', 'a', 's', 'l', 9, 0, |
| /* 10020 */ 's', 'q', 'd', 'm', 'l', 's', 'l', 9, 0, |
| /* 10029 */ 's', 'y', 's', 'l', 9, 0, |
| /* 10035 */ 'l', 'd', 's', 'e', 't', 'l', 9, 0, |
| /* 10043 */ 'f', 'c', 'v', 't', 'l', 9, 0, |
| /* 10050 */ 'f', 'm', 'u', 'l', 9, 0, |
| /* 10056 */ 'f', 'n', 'm', 'u', 'l', 9, 0, |
| /* 10063 */ 'f', 't', 's', 'm', 'u', 'l', 9, 0, |
| /* 10071 */ 'a', 'd', 'd', 'v', 'l', 9, 0, |
| /* 10078 */ 'r', 'd', 'v', 'l', 9, 0, |
| /* 10084 */ 'l', 'd', 's', 'm', 'a', 'x', 'l', 9, 0, |
| /* 10093 */ 'l', 'd', 'u', 'm', 'a', 'x', 'l', 9, 0, |
| /* 10102 */ 's', 'b', 'f', 'm', 9, 0, |
| /* 10108 */ 'u', 'b', 'f', 'm', 9, 0, |
| /* 10114 */ 'p', 'r', 'f', 'm', 9, 0, |
| /* 10120 */ 'f', 'm', 'i', 'n', 'n', 'm', 9, 0, |
| /* 10128 */ 'f', 'm', 'a', 'x', 'n', 'm', 9, 0, |
| /* 10136 */ 'd', 'u', 'p', 'm', 9, 0, |
| /* 10142 */ 'f', 'r', 'i', 'n', 't', 'm', 9, 0, |
| /* 10150 */ 'p', 'r', 'f', 'u', 'm', 9, 0, |
| /* 10157 */ 'f', 'm', 'i', 'n', 9, 0, |
| /* 10163 */ 'l', 'd', 's', 'm', 'i', 'n', 9, 0, |
| /* 10171 */ 'l', 'd', 'u', 'm', 'i', 'n', 9, 0, |
| /* 10179 */ 'b', 'r', 'k', 'n', 9, 0, |
| /* 10185 */ 'c', 'c', 'm', 'n', 9, 0, |
| /* 10191 */ 'e', 'o', 'n', 9, 0, |
| /* 10196 */ 's', 'q', 's', 'h', 'r', 'n', 9, 0, |
| /* 10204 */ 'u', 'q', 's', 'h', 'r', 'n', 9, 0, |
| /* 10212 */ 's', 'q', 'r', 's', 'h', 'r', 'n', 9, 0, |
| /* 10221 */ 'u', 'q', 'r', 's', 'h', 'r', 'n', 9, 0, |
| /* 10230 */ 'o', 'r', 'n', 9, 0, |
| /* 10235 */ 'f', 'r', 'i', 'n', 't', 'n', 9, 0, |
| /* 10243 */ 'f', 'c', 'v', 't', 'n', 9, 0, |
| /* 10250 */ 's', 'q', 'x', 't', 'n', 9, 0, |
| /* 10257 */ 'u', 'q', 'x', 't', 'n', 9, 0, |
| /* 10264 */ 's', 'q', 's', 'h', 'r', 'u', 'n', 9, 0, |
| /* 10273 */ 's', 'q', 'r', 's', 'h', 'r', 'u', 'n', 9, 0, |
| /* 10283 */ 's', 'q', 'x', 't', 'u', 'n', 9, 0, |
| /* 10291 */ 'm', 'o', 'v', 'n', 9, 0, |
| /* 10297 */ 'f', 'c', 'v', 't', 'x', 'n', 9, 0, |
| /* 10305 */ 'w', 'h', 'i', 'l', 'e', 'l', 'o', 9, 0, |
| /* 10314 */ 'p', 'u', 'n', 'p', 'k', 'l', 'o', 9, 0, |
| /* 10323 */ 's', 'u', 'n', 'p', 'k', 'l', 'o', 9, 0, |
| /* 10332 */ 'u', 'u', 'n', 'p', 'k', 'l', 'o', 9, 0, |
| /* 10341 */ 'c', 'm', 'p', 'l', 'o', 9, 0, |
| /* 10348 */ 'f', 'c', 'm', 'u', 'o', 9, 0, |
| /* 10355 */ 's', 'q', 'd', 'e', 'c', 'p', 9, 0, |
| /* 10363 */ 'u', 'q', 'd', 'e', 'c', 'p', 9, 0, |
| /* 10371 */ 's', 'q', 'i', 'n', 'c', 'p', 9, 0, |
| /* 10379 */ 'u', 'q', 'i', 'n', 'c', 'p', 9, 0, |
| /* 10387 */ 'l', 'd', 'p', 9, 0, |
| /* 10392 */ 'f', 'c', 'c', 'm', 'p', 9, 0, |
| /* 10399 */ 'f', 'c', 'm', 'p', 9, 0, |
| /* 10405 */ 'l', 'd', 'n', 'p', 9, 0, |
| /* 10411 */ 's', 't', 'n', 'p', 9, 0, |
| /* 10417 */ 'a', 'd', 'r', 'p', 9, 0, |
| /* 10423 */ 'c', 'a', 's', 'p', 9, 0, |
| /* 10429 */ 'c', 'n', 't', 'p', 9, 0, |
| /* 10435 */ 'f', 'r', 'i', 'n', 't', 'p', 9, 0, |
| /* 10443 */ 's', 't', 'p', 9, 0, |
| /* 10448 */ 'f', 'd', 'u', 'p', 9, 0, |
| /* 10454 */ 's', 'w', 'p', 9, 0, |
| /* 10459 */ 'l', 'd', 'a', 'x', 'p', 9, 0, |
| /* 10466 */ 'l', 'd', 'x', 'p', 9, 0, |
| /* 10472 */ 's', 't', 'l', 'x', 'p', 9, 0, |
| /* 10479 */ 's', 't', 'x', 'p', 9, 0, |
| /* 10485 */ 'p', 'm', 'u', 'l', 'l', '2', '.', '1', 'q', 9, 0, |
| /* 10496 */ 'p', 'm', 'u', 'l', 'l', '.', '1', 'q', 9, 0, |
| /* 10506 */ 'f', 'c', 'm', 'e', 'q', 9, 0, |
| /* 10513 */ 'c', 't', 'e', 'r', 'm', 'e', 'q', 9, 0, |
| /* 10522 */ 'c', 'm', 'p', 'e', 'q', 9, 0, |
| /* 10529 */ 'l', 'd', '1', 'r', 9, 0, |
| /* 10535 */ 'l', 'd', '2', 'r', 9, 0, |
| /* 10541 */ 'l', 'd', '3', 'r', 9, 0, |
| /* 10547 */ 'l', 'd', '4', 'r', 9, 0, |
| /* 10553 */ 'l', 'd', 'a', 'r', 9, 0, |
| /* 10559 */ 'l', 'd', 'l', 'a', 'r', 9, 0, |
| /* 10566 */ 'f', 's', 'u', 'b', 'r', 9, 0, |
| /* 10573 */ 'a', 'd', 'r', 9, 0, |
| /* 10578 */ 'l', 'd', 'r', 9, 0, |
| /* 10583 */ 'r', 'd', 'f', 'f', 'r', 9, 0, |
| /* 10590 */ 'w', 'r', 'f', 'f', 'r', 9, 0, |
| /* 10597 */ 's', 'r', 's', 'h', 'r', 9, 0, |
| /* 10604 */ 'u', 'r', 's', 'h', 'r', 9, 0, |
| /* 10611 */ 's', 's', 'h', 'r', 9, 0, |
| /* 10617 */ 'u', 's', 'h', 'r', 9, 0, |
| /* 10623 */ 'b', 'l', 'r', 9, 0, |
| /* 10628 */ 'l', 'd', 'c', 'l', 'r', 9, 0, |
| /* 10635 */ 's', 't', 'l', 'l', 'r', 9, 0, |
| /* 10642 */ 'l', 's', 'l', 'r', 9, 0, |
| /* 10648 */ 's', 't', 'l', 'r', 9, 0, |
| /* 10654 */ 'l', 'd', 'e', 'o', 'r', 9, 0, |
| /* 10661 */ 'n', 'o', 'r', 9, 0, |
| /* 10666 */ 'r', 'o', 'r', 9, 0, |
| /* 10671 */ 'l', 'd', 'a', 'p', 'r', 9, 0, |
| /* 10678 */ 'o', 'r', 'r', 9, 0, |
| /* 10683 */ 'a', 's', 'r', 'r', 9, 0, |
| /* 10689 */ 'l', 's', 'r', 'r', 9, 0, |
| /* 10695 */ 'a', 's', 'r', 9, 0, |
| /* 10700 */ 'l', 's', 'r', 9, 0, |
| /* 10705 */ 'm', 's', 'r', 9, 0, |
| /* 10710 */ 'i', 'n', 's', 'r', 9, 0, |
| /* 10716 */ 'l', 'd', 't', 'r', 9, 0, |
| /* 10722 */ 's', 't', 'r', 9, 0, |
| /* 10727 */ 's', 't', 't', 'r', 9, 0, |
| /* 10733 */ 'e', 'x', 't', 'r', 9, 0, |
| /* 10739 */ 'l', 'd', 'u', 'r', 9, 0, |
| /* 10745 */ 's', 't', 'l', 'u', 'r', 9, 0, |
| /* 10752 */ 'l', 'd', 'a', 'p', 'u', 'r', 9, 0, |
| /* 10760 */ 's', 't', 'u', 'r', 9, 0, |
| /* 10766 */ 'f', 'd', 'i', 'v', 'r', 9, 0, |
| /* 10773 */ 's', 'd', 'i', 'v', 'r', 9, 0, |
| /* 10780 */ 'u', 'd', 'i', 'v', 'r', 9, 0, |
| /* 10787 */ 'l', 'd', 'a', 'x', 'r', 9, 0, |
| /* 10794 */ 'l', 'd', 'x', 'r', 9, 0, |
| /* 10800 */ 's', 't', 'l', 'x', 'r', 9, 0, |
| /* 10807 */ 's', 't', 'x', 'r', 9, 0, |
| /* 10813 */ 'f', 'm', 'l', 'a', '.', 's', 9, 0, |
| /* 10821 */ 's', 'q', 'r', 'd', 'm', 'l', 'a', 'h', '.', 's', 9, 0, |
| /* 10833 */ 's', 'q', 'd', 'm', 'u', 'l', 'h', '.', 's', 9, 0, |
| /* 10844 */ 's', 'q', 'r', 'd', 'm', 'u', 'l', 'h', '.', 's', 9, 0, |
| /* 10856 */ 's', 'q', 'r', 'd', 'm', 'l', 's', 'h', '.', 's', 9, 0, |
| /* 10868 */ 's', 'q', 'd', 'm', 'l', 'a', 'l', '.', 's', 9, 0, |
| /* 10879 */ 's', 'q', 'd', 'm', 'u', 'l', 'l', '.', 's', 9, 0, |
| /* 10890 */ 's', 'q', 'd', 'm', 'l', 's', 'l', '.', 's', 9, 0, |
| /* 10901 */ 'f', 'm', 'u', 'l', '.', 's', 9, 0, |
| /* 10909 */ 'f', 'm', 'l', 's', '.', 's', 9, 0, |
| /* 10917 */ 'i', 'n', 's', '.', 's', 9, 0, |
| /* 10924 */ 's', 'm', 'o', 'v', '.', 's', 9, 0, |
| /* 10932 */ 'u', 'm', 'o', 'v', '.', 's', 9, 0, |
| /* 10940 */ 'f', 'm', 'u', 'l', 'x', '.', 's', 9, 0, |
| /* 10949 */ 't', 'r', 'n', '1', '.', '2', 's', 9, 0, |
| /* 10958 */ 'z', 'i', 'p', '1', '.', '2', 's', 9, 0, |
| /* 10967 */ 'u', 'z', 'p', '1', '.', '2', 's', 9, 0, |
| /* 10976 */ 't', 'r', 'n', '2', '.', '2', 's', 9, 0, |
| /* 10985 */ 'z', 'i', 'p', '2', '.', '2', 's', 9, 0, |
| /* 10994 */ 'u', 'z', 'p', '2', '.', '2', 's', 9, 0, |
| /* 11003 */ 'r', 'e', 'v', '6', '4', '.', '2', 's', 9, 0, |
| /* 11013 */ 's', 'a', 'b', 'a', '.', '2', 's', 9, 0, |
| /* 11022 */ 'u', 'a', 'b', 'a', '.', '2', 's', 9, 0, |
| /* 11031 */ 'f', 'c', 'm', 'l', 'a', '.', '2', 's', 9, 0, |
| /* 11041 */ 'f', 'm', 'l', 'a', '.', '2', 's', 9, 0, |
| /* 11050 */ 's', 'r', 's', 'r', 'a', '.', '2', 's', 9, 0, |
| /* 11060 */ 'u', 'r', 's', 'r', 'a', '.', '2', 's', 9, 0, |
| /* 11070 */ 's', 's', 'r', 'a', '.', '2', 's', 9, 0, |
| /* 11079 */ 'u', 's', 'r', 'a', '.', '2', 's', 9, 0, |
| /* 11088 */ 'f', 'r', 'i', 'n', 't', 'a', '.', '2', 's', 9, 0, |
| /* 11099 */ 'f', 's', 'u', 'b', '.', '2', 's', 9, 0, |
| /* 11108 */ 's', 'h', 's', 'u', 'b', '.', '2', 's', 9, 0, |
| /* 11118 */ 'u', 'h', 's', 'u', 'b', '.', '2', 's', 9, 0, |
| /* 11128 */ 's', 'q', 's', 'u', 'b', '.', '2', 's', 9, 0, |
| /* 11138 */ 'u', 'q', 's', 'u', 'b', '.', '2', 's', 9, 0, |
| /* 11148 */ 'b', 'i', 'c', '.', '2', 's', 9, 0, |
| /* 11156 */ 'f', 'a', 'b', 'd', '.', '2', 's', 9, 0, |
| /* 11165 */ 's', 'a', 'b', 'd', '.', '2', 's', 9, 0, |
| /* 11174 */ 'u', 'a', 'b', 'd', '.', '2', 's', 9, 0, |
| /* 11183 */ 'f', 'c', 'a', 'd', 'd', '.', '2', 's', 9, 0, |
| /* 11193 */ 'f', 'a', 'd', 'd', '.', '2', 's', 9, 0, |
| /* 11202 */ 's', 'r', 'h', 'a', 'd', 'd', '.', '2', 's', 9, 0, |
| /* 11213 */ 'u', 'r', 'h', 'a', 'd', 'd', '.', '2', 's', 9, 0, |
| /* 11224 */ 's', 'h', 'a', 'd', 'd', '.', '2', 's', 9, 0, |
| /* 11234 */ 'u', 'h', 'a', 'd', 'd', '.', '2', 's', 9, 0, |
| /* 11244 */ 'u', 's', 'q', 'a', 'd', 'd', '.', '2', 's', 9, 0, |
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| /* 14120 */ 'f', 'c', 'v', 't', 'n', 'u', '.', '4', 's', 9, 0, |
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| /* 14153 */ 'a', 'd', 'd', 'v', '.', '4', 's', 9, 0, |
| /* 14162 */ 'f', 'd', 'i', 'v', '.', '4', 's', 9, 0, |
| /* 14171 */ 's', 'a', 'd', 'd', 'l', 'v', '.', '4', 's', 9, 0, |
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| /* 14237 */ 'u', 'm', 'i', 'n', 'v', '.', '4', 's', 9, 0, |
| /* 14247 */ 'f', 'm', 'o', 'v', '.', '4', 's', 9, 0, |
| /* 14256 */ 'f', 'm', 'a', 'x', 'v', '.', '4', 's', 9, 0, |
| /* 14266 */ 's', 'm', 'a', 'x', 'v', '.', '4', 's', 9, 0, |
| /* 14276 */ 'u', 'm', 'a', 'x', 'v', '.', '4', 's', 9, 0, |
| /* 14286 */ 's', 's', 'u', 'b', 'w', '.', '4', 's', 9, 0, |
| /* 14296 */ 'u', 's', 'u', 'b', 'w', '.', '4', 's', 9, 0, |
| /* 14306 */ 's', 'a', 'd', 'd', 'w', '.', '4', 's', 9, 0, |
| /* 14316 */ 'u', 'a', 'd', 'd', 'w', '.', '4', 's', 9, 0, |
| /* 14326 */ 'f', 'm', 'a', 'x', '.', '4', 's', 9, 0, |
| /* 14335 */ 's', 'm', 'a', 'x', '.', '4', 's', 9, 0, |
| /* 14344 */ 'u', 'm', 'a', 'x', '.', '4', 's', 9, 0, |
| /* 14353 */ 'f', 'm', 'u', 'l', 'x', '.', '4', 's', 9, 0, |
| /* 14363 */ 'f', 'r', 'i', 'n', 't', 'x', '.', '4', 's', 9, 0, |
| /* 14374 */ 'c', 'l', 'z', '.', '4', 's', 9, 0, |
| /* 14382 */ 'f', 'r', 'i', 'n', 't', 'z', '.', '4', 's', 9, 0, |
| /* 14393 */ 'c', 'a', 's', 9, 0, |
| /* 14398 */ 'b', 'r', 'k', 'a', 's', 9, 0, |
| /* 14405 */ 'b', 'r', 'k', 'p', 'a', 's', 9, 0, |
| /* 14413 */ 'f', 'c', 'v', 't', 'a', 's', 9, 0, |
| /* 14421 */ 'f', 'a', 'b', 's', 9, 0, |
| /* 14427 */ 's', 'q', 'a', 'b', 's', 9, 0, |
| /* 14434 */ 'b', 'r', 'k', 'b', 's', 9, 0, |
| /* 14441 */ 'b', 'r', 'k', 'p', 'b', 's', 9, 0, |
| /* 14449 */ 's', 'u', 'b', 's', 9, 0, |
| /* 14455 */ 's', 'b', 'c', 's', 9, 0, |
| /* 14461 */ 'a', 'd', 'c', 's', 9, 0, |
| /* 14467 */ 'b', 'i', 'c', 's', 9, 0, |
| /* 14473 */ 'a', 'd', 'd', 's', 9, 0, |
| /* 14479 */ 'n', 'a', 'n', 'd', 's', 9, 0, |
| /* 14486 */ 'p', 't', 'r', 'u', 'e', 's', 9, 0, |
| /* 14494 */ 'c', 'm', 'h', 's', 9, 0, |
| /* 14500 */ 'c', 'm', 'p', 'h', 's', 9, 0, |
| /* 14507 */ 'c', 'l', 's', 9, 0, |
| /* 14512 */ 'w', 'h', 'i', 'l', 'e', 'l', 's', 9, 0, |
| /* 14521 */ 'f', 'm', 'l', 's', 9, 0, |
| /* 14527 */ 'f', 'n', 'm', 'l', 's', 9, 0, |
| /* 14534 */ 'c', 'm', 'p', 'l', 's', 9, 0, |
| /* 14541 */ 'f', 'c', 'v', 't', 'm', 's', 9, 0, |
| /* 14549 */ 'b', 'r', 'k', 'n', 's', 9, 0, |
| /* 14556 */ 'o', 'r', 'n', 's', 9, 0, |
| /* 14562 */ 'f', 'c', 'v', 't', 'n', 's', 9, 0, |
| /* 14570 */ 'f', 'r', 'e', 'c', 'p', 's', 9, 0, |
| /* 14578 */ 'f', 'c', 'v', 't', 'p', 's', 9, 0, |
| /* 14586 */ 'r', 'd', 'f', 'f', 'r', 's', 9, 0, |
| /* 14594 */ 'm', 'r', 's', 9, 0, |
| /* 14599 */ 'e', 'o', 'r', 's', 9, 0, |
| /* 14605 */ 'n', 'o', 'r', 's', 9, 0, |
| /* 14611 */ 'o', 'r', 'r', 's', 9, 0, |
| /* 14617 */ 'f', 'r', 's', 'q', 'r', 't', 's', 9, 0, |
| /* 14626 */ 's', 'y', 's', 9, 0, |
| /* 14631 */ 'f', 'c', 'v', 't', 'z', 's', 9, 0, |
| /* 14639 */ 'f', 'j', 'c', 'v', 't', 'z', 's', 9, 0, |
| /* 14648 */ 'c', 'o', 'm', 'p', 'a', 'c', 't', 9, 0, |
| /* 14657 */ 'r', 'e', 't', 9, 0, |
| /* 14662 */ 'l', 'd', 's', 'e', 't', 9, 0, |
| /* 14669 */ 'f', 'a', 'c', 'g', 't', 9, 0, |
| /* 14676 */ 'f', 'c', 'm', 'g', 't', 9, 0, |
| /* 14683 */ 'c', 'm', 'p', 'g', 't', 9, 0, |
| /* 14690 */ 'r', 'b', 'i', 't', 9, 0, |
| /* 14696 */ 'w', 'h', 'i', 'l', 'e', 'l', 't', 9, 0, |
| /* 14705 */ 'h', 'l', 't', 9, 0, |
| /* 14710 */ 'f', 'c', 'm', 'l', 't', 9, 0, |
| /* 14717 */ 'c', 'm', 'p', 'l', 't', 9, 0, |
| /* 14724 */ 'c', 'n', 't', 9, 0, |
| /* 14729 */ 'h', 'i', 'n', 't', 9, 0, |
| /* 14735 */ 's', 'd', 'o', 't', 9, 0, |
| /* 14741 */ 'u', 'd', 'o', 't', 9, 0, |
| /* 14747 */ 'c', 'n', 'o', 't', 9, 0, |
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| /* 14760 */ 'p', 't', 'e', 's', 't', 9, 0, |
| /* 14767 */ 'p', 'f', 'i', 'r', 's', 't', 9, 0, |
| /* 14775 */ 'c', 'm', 't', 's', 't', 9, 0, |
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| /* 14864 */ 'a', 'n', 'd', 'v', 9, 0, |
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| /* 14881 */ 's', 'd', 'i', 'v', 9, 0, |
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| /* 14902 */ 'f', 'm', 'a', 'x', 'n', 'm', 'v', 9, 0, |
| /* 14911 */ 'f', 'm', 'i', 'n', 'v', 9, 0, |
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| /* 14932 */ 'c', 's', 'i', 'n', 'v', 9, 0, |
| /* 14939 */ 'f', 'm', 'o', 'v', 9, 0, |
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| /* 14951 */ 'f', 'm', 'a', 'x', 'v', 9, 0, |
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| /* 14965 */ 'u', 'm', 'a', 'x', 'v', 9, 0, |
| /* 14972 */ 'l', 'd', '1', 'w', 9, 0, |
| /* 14978 */ 'l', 'd', 'f', 'f', '1', 'w', 9, 0, |
| /* 14986 */ 'l', 'd', 'n', 'f', '1', 'w', 9, 0, |
| /* 14994 */ 'l', 'd', 'n', 't', '1', 'w', 9, 0, |
| /* 15002 */ 's', 't', 'n', 't', '1', 'w', 9, 0, |
| /* 15010 */ 's', 't', '1', 'w', 9, 0, |
| /* 15016 */ 'c', 'r', 'c', '3', '2', 'w', 9, 0, |
| /* 15024 */ 'l', 'd', '2', 'w', 9, 0, |
| /* 15030 */ 's', 't', '2', 'w', 9, 0, |
| /* 15036 */ 'l', 'd', '3', 'w', 9, 0, |
| /* 15042 */ 's', 't', '3', 'w', 9, 0, |
| /* 15048 */ 'l', 'd', '4', 'w', 9, 0, |
| /* 15054 */ 's', 't', '4', 'w', 9, 0, |
| /* 15060 */ 'c', 'r', 'c', '3', '2', 'c', 'w', 9, 0, |
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| /* 15101 */ 'p', 'r', 'f', 'w', 9, 0, |
| /* 15107 */ 'l', 'd', '1', 'r', 'q', 'w', 9, 0, |
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| /* 15129 */ 'l', 'd', 'f', 'f', '1', 's', 'w', 9, 0, |
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| /* 15147 */ 'l', 'd', 'p', 's', 'w', 9, 0, |
| /* 15154 */ 'l', 'd', '1', 'r', 's', 'w', 9, 0, |
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| /* 15195 */ 'c', 'n', 't', 'w', 9, 0, |
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| /* 15213 */ 'r', 'e', 'v', 'w', 9, 0, |
| /* 15219 */ 'c', 'r', 'c', '3', '2', 'x', 9, 0, |
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| /* 15249 */ 't', 'b', 'x', 9, 0, |
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| /* 15263 */ 'i', 'n', 'd', 'e', 'x', 9, 0, |
| /* 15270 */ 'c', 'l', 'r', 'e', 'x', 9, 0, |
| /* 15277 */ 'm', 'o', 'v', 'p', 'r', 'f', 'x', 9, 0, |
| /* 15286 */ 'f', 'm', 'u', 'l', 'x', 9, 0, |
| /* 15293 */ 'f', 'r', 'e', 'c', 'p', 'x', 9, 0, |
| /* 15301 */ 'f', 'r', 'i', 'n', 't', 'x', 9, 0, |
| /* 15309 */ 'f', 'c', 'p', 'y', 9, 0, |
| /* 15315 */ 'b', 'r', 'a', 'a', 'z', 9, 0, |
| /* 15322 */ 'b', 'l', 'r', 'a', 'a', 'z', 9, 0, |
| /* 15330 */ 'b', 'r', 'a', 'b', 'z', 9, 0, |
| /* 15337 */ 'b', 'l', 'r', 'a', 'b', 'z', 9, 0, |
| /* 15345 */ 'c', 'b', 'z', 9, 0, |
| /* 15350 */ 't', 'b', 'z', 9, 0, |
| /* 15355 */ 'c', 'l', 'z', 9, 0, |
| /* 15360 */ 'c', 'b', 'n', 'z', 9, 0, |
| /* 15366 */ 't', 'b', 'n', 'z', 9, 0, |
| /* 15372 */ 'f', 'r', 'i', 'n', 't', 'z', 9, 0, |
| /* 15380 */ 'm', 'o', 'v', 'z', 9, 0, |
| /* 15386 */ '.', 't', 'l', 's', 'd', 'e', 's', 'c', 'c', 'a', 'l', 'l', 32, 0, |
| /* 15400 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'F', 'u', 'n', 'c', 't', 'i', 'o', 'n', 32, 'P', 'a', 't', 'c', 'h', 'a', 'b', 'l', 'e', 32, 'R', 'E', 'T', '.', 0, |
| /* 15431 */ 'b', '.', 0, |
| /* 15434 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'T', 'y', 'p', 'e', 'd', 32, 'E', 'v', 'e', 'n', 't', 32, 'L', 'o', 'g', '.', 0, |
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| /* 15506 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'T', 'a', 'i', 'l', 32, 'C', 'a', 'l', 'l', 32, 'E', 'x', 'i', 't', '.', 0, |
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| /* 15551 */ 's', 'h', 'a', '5', '1', '2', 's', 'u', '0', 0, |
| /* 15561 */ 's', 'm', '3', 's', 's', '1', 0, |
| /* 15568 */ 's', 'h', 'a', '5', '1', '2', 's', 'u', '1', 0, |
| /* 15578 */ 's', 'm', '3', 'p', 'a', 'r', 't', 'w', '1', 0, |
| /* 15588 */ 'r', 'a', 'x', '1', 0, |
| /* 15593 */ 's', 'h', 'a', '5', '1', '2', 'h', '2', 0, |
| /* 15602 */ 's', 'm', '3', 'p', 'a', 'r', 't', 'w', '2', 0, |
| /* 15612 */ 'e', 'o', 'r', '3', 0, |
| /* 15617 */ 'p', 'a', 'c', 'i', 'a', '1', '7', '1', '6', 0, |
| /* 15627 */ 'a', 'u', 't', 'i', 'a', '1', '7', '1', '6', 0, |
| /* 15637 */ 'p', 'a', 'c', 'i', 'b', '1', '7', '1', '6', 0, |
| /* 15647 */ 'a', 'u', 't', 'i', 'b', '1', '7', '1', '6', 0, |
| /* 15657 */ 's', 'e', 't', 'f', '1', '6', 0, |
| /* 15664 */ 's', 'e', 't', 'f', '8', 0, |
| /* 15670 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0, |
| /* 15683 */ 'B', 'U', 'N', 'D', 'L', 'E', 0, |
| /* 15690 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0, |
| /* 15700 */ 'D', 'B', 'G', '_', 'L', 'A', 'B', 'E', 'L', 0, |
| /* 15710 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0, |
| /* 15725 */ 's', 'm', '3', 't', 't', '1', 'a', 0, |
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| /* 15748 */ 's', 'm', '3', 't', 't', '1', 'b', 0, |
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| /* 15776 */ 'r', 'm', 'i', 'f', 0, |
| /* 15781 */ 's', 'h', 'a', '5', '1', '2', 'h', 0, |
| /* 15789 */ 'x', 'p', 'a', 'c', 'l', 'r', 'i', 0, |
| /* 15797 */ '#', 32, 'F', 'E', 'n', 't', 'r', 'y', 32, 'c', 'a', 'l', 'l', 0, |
| /* 15811 */ 'p', 'a', 'c', 'i', 'a', 's', 'p', 0, |
| /* 15819 */ 'a', 'u', 't', 'i', 'a', 's', 'p', 0, |
| /* 15827 */ 'p', 'a', 'c', 'i', 'b', 's', 'p', 0, |
| /* 15835 */ 'a', 'u', 't', 'i', 'b', 's', 'p', 0, |
| /* 15843 */ 'x', 'a', 'r', 0, |
| /* 15847 */ 's', 'e', 't', 'f', 'f', 'r', 0, |
| /* 15854 */ 'd', 'r', 'p', 's', 0, |
| /* 15859 */ 'e', 'r', 'e', 't', 0, |
| /* 15864 */ 's', 'd', 'o', 't', 0, |
| /* 15869 */ 'u', 'd', 'o', 't', 0, |
| /* 15874 */ 'c', 'f', 'i', 'n', 'v', 0, |
| /* 15880 */ 'b', 'c', 'a', 'x', 0, |
| /* 15885 */ 's', 'm', '4', 'e', 'k', 'e', 'y', 0, |
| /* 15893 */ 'p', 'a', 'c', 'i', 'a', 'z', 0, |
| /* 15900 */ 'a', 'u', 't', 'i', 'a', 'z', 0, |
| /* 15907 */ 'p', 'a', 'c', 'i', 'b', 'z', 0, |
| /* 15914 */ 'a', 'u', 't', 'i', 'b', 'z', 0, |
| }; |
| |
| static const uint32_t OpInfo0[] = { |
| 0U, // PHI |
| 0U, // INLINEASM |
| 0U, // CFI_INSTRUCTION |
| 0U, // EH_LABEL |
| 0U, // GC_LABEL |
| 0U, // ANNOTATION_LABEL |
| 0U, // KILL |
| 0U, // EXTRACT_SUBREG |
| 0U, // INSERT_SUBREG |
| 0U, // IMPLICIT_DEF |
| 0U, // SUBREG_TO_REG |
| 0U, // COPY_TO_REGCLASS |
| 15691U, // DBG_VALUE |
| 15701U, // DBG_LABEL |
| 0U, // REG_SEQUENCE |
| 0U, // COPY |
| 15684U, // BUNDLE |
| 15711U, // LIFETIME_START |
| 15671U, // LIFETIME_END |
| 0U, // STACKMAP |
| 15798U, // FENTRY_CALL |
| 0U, // PATCHPOINT |
| 0U, // LOAD_STACK_GUARD |
| 0U, // STATEPOINT |
| 0U, // LOCAL_ESCAPE |
| 0U, // FAULTING_OP |
| 0U, // PATCHABLE_OP |
| 15484U, // PATCHABLE_FUNCTION_ENTER |
| 15401U, // PATCHABLE_RET |
| 15530U, // PATCHABLE_FUNCTION_EXIT |
| 15507U, // PATCHABLE_TAIL_CALL |
| 15459U, // PATCHABLE_EVENT_CALL |
| 15435U, // PATCHABLE_TYPED_EVENT_CALL |
| 0U, // ICALL_BRANCH_FUNNEL |
| 0U, // G_ADD |
| 0U, // G_SUB |
| 0U, // G_MUL |
| 0U, // G_SDIV |
| 0U, // G_UDIV |
| 0U, // G_SREM |
| 0U, // G_UREM |
| 0U, // G_AND |
| 0U, // G_OR |
| 0U, // G_XOR |
| 0U, // G_IMPLICIT_DEF |
| 0U, // G_PHI |
| 0U, // G_FRAME_INDEX |
| 0U, // G_GLOBAL_VALUE |
| 0U, // G_EXTRACT |
| 0U, // G_UNMERGE_VALUES |
| 0U, // G_INSERT |
| 0U, // G_MERGE_VALUES |
| 0U, // G_PTRTOINT |
| 0U, // G_INTTOPTR |
| 0U, // G_BITCAST |
| 0U, // G_LOAD |
| 0U, // G_SEXTLOAD |
| 0U, // G_ZEXTLOAD |
| 0U, // G_STORE |
| 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS |
| 0U, // G_ATOMIC_CMPXCHG |
| 0U, // G_ATOMICRMW_XCHG |
| 0U, // G_ATOMICRMW_ADD |
| 0U, // G_ATOMICRMW_SUB |
| 0U, // G_ATOMICRMW_AND |
| 0U, // G_ATOMICRMW_NAND |
| 0U, // G_ATOMICRMW_OR |
| 0U, // G_ATOMICRMW_XOR |
| 0U, // G_ATOMICRMW_MAX |
| 0U, // G_ATOMICRMW_MIN |
| 0U, // G_ATOMICRMW_UMAX |
| 0U, // G_ATOMICRMW_UMIN |
| 0U, // G_BRCOND |
| 0U, // G_BRINDIRECT |
| 0U, // G_INTRINSIC |
| 0U, // G_INTRINSIC_W_SIDE_EFFECTS |
| 0U, // G_ANYEXT |
| 0U, // G_TRUNC |
| 0U, // G_CONSTANT |
| 0U, // G_FCONSTANT |
| 0U, // G_VASTART |
| 0U, // G_VAARG |
| 0U, // G_SEXT |
| 0U, // G_ZEXT |
| 0U, // G_SHL |
| 0U, // G_LSHR |
| 0U, // G_ASHR |
| 0U, // G_ICMP |
| 0U, // G_FCMP |
| 0U, // G_SELECT |
| 0U, // G_UADDE |
| 0U, // G_USUBE |
| 0U, // G_SADDO |
| 0U, // G_SSUBO |
| 0U, // G_UMULO |
| 0U, // G_SMULO |
| 0U, // G_UMULH |
| 0U, // G_SMULH |
| 0U, // G_FADD |
| 0U, // G_FSUB |
| 0U, // G_FMUL |
| 0U, // G_FMA |
| 0U, // G_FDIV |
| 0U, // G_FREM |
| 0U, // G_FPOW |
| 0U, // G_FEXP |
| 0U, // G_FEXP2 |
| 0U, // G_FLOG |
| 0U, // G_FLOG2 |
| 0U, // G_FNEG |
| 0U, // G_FPEXT |
| 0U, // G_FPTRUNC |
| 0U, // G_FPTOSI |
| 0U, // G_FPTOUI |
| 0U, // G_SITOFP |
| 0U, // G_UITOFP |
| 0U, // G_FABS |
| 0U, // G_GEP |
| 0U, // G_PTR_MASK |
| 0U, // G_BR |
| 0U, // G_INSERT_VECTOR_ELT |
| 0U, // G_EXTRACT_VECTOR_ELT |
| 0U, // G_SHUFFLE_VECTOR |
| 0U, // G_BSWAP |
| 0U, // G_ADDRSPACE_CAST |
| 0U, // G_BLOCK_ADDR |
| 30807U, // ABS_ZPmZ_B |
| 47191U, // ABS_ZPmZ_D |
| 68221015U, // ABS_ZPmZ_H |
| 79959U, // ABS_ZPmZ_S |
| 134301013U, // ABSv16i8 |
| 201439319U, // ABSv1i64 |
| 134311644U, // ABSv2i32 |
| 134304263U, // ABSv2i64 |
| 134306254U, // ABSv4i16 |
| 134313575U, // ABSv4i32 |
| 134308138U, // ABSv8i16 |
| 134301962U, // ABSv8i8 |
| 201439358U, // ADCSWr |
| 201439358U, // ADCSXr |
| 201428223U, // ADCWr |
| 201428223U, // ADCXr |
| 134311269U, // ADDHNv2i64_v2i32 |
| 268562772U, // ADDHNv2i64_v4i32 |
| 134305879U, // ADDHNv4i32_v4i16 |
| 268557426U, // ADDHNv4i32_v8i16 |
| 268550710U, // ADDHNv8i16_v16i8 |
| 134301702U, // ADDHNv8i16_v8i8 |
| 201434875U, // ADDPL_XXI |
| 134300878U, // ADDPv16i8 |
| 134311420U, // ADDPv2i32 |
| 134304087U, // ADDPv2i64 |
| 134320471U, // ADDPv2i64p |
| 134306030U, // ADDPv4i16 |
| 134313351U, // ADDPv4i32 |
| 134307914U, // ADDPv8i16 |
| 134301840U, // ADDPv8i8 |
| 201439370U, // ADDSWri |
| 0U, // ADDSWrr |
| 201439370U, // ADDSWrs |
| 201439370U, // ADDSWrx |
| 201439370U, // ADDSXri |
| 0U, // ADDSXrr |
| 201439370U, // ADDSXrs |
| 201439370U, // ADDSXrx |
| 201439370U, // ADDSXrx64 |
| 201434968U, // ADDVL_XXI |
| 134317514U, // ADDVv16i8v |
| 134322865U, // ADDVv4i16v |
| 134330186U, // ADDVv4i32v |
| 134324749U, // ADDVv8i16v |
| 134318451U, // ADDVv8i8v |
| 201429944U, // ADDWri |
| 0U, // ADDWrr |
| 201429944U, // ADDWrs |
| 201429944U, // ADDWrx |
| 201429944U, // ADDXri |
| 0U, // ADDXrr |
| 201429944U, // ADDXrs |
| 201429944U, // ADDXrx |
| 201429944U, // ADDXrx64 |
| 335565752U, // ADD_ZI_B |
| 402691000U, // ADD_ZI_D |
| 471913400U, // ADD_ZI_H |
| 536941496U, // ADD_ZI_S |
| 604001208U, // ADD_ZPmZ_B |
| 604017592U, // ADD_ZPmZ_D |
| 70308792U, // ADD_ZPmZ_H |
| 604050360U, // ADD_ZPmZ_S |
| 335565752U, // ADD_ZZZ_B |
| 402691000U, // ADD_ZZZ_D |
| 471913400U, // ADD_ZZZ_H |
| 536941496U, // ADD_ZZZ_S |
| 0U, // ADDlowTLS |
| 134300568U, // ADDv16i8 |
| 201429944U, // ADDv1i64 |
| 134310834U, // ADDv2i32 |
| 134303572U, // ADDv2i64 |
| 134305467U, // ADDv4i16 |
| 134312661U, // ADDv4i32 |
| 134307305U, // ADDv8i16 |
| 134301454U, // ADDv8i8 |
| 0U, // ADJCALLSTACKDOWN |
| 0U, // ADJCALLSTACKUP |
| 201435470U, // ADR |
| 671197362U, // ADRP |
| 406890830U, // ADR_LSL_ZZZ_D_0 |
| 406890830U, // ADR_LSL_ZZZ_D_1 |
| 406890830U, // ADR_LSL_ZZZ_D_2 |
| 406890830U, // ADR_LSL_ZZZ_D_3 |
| 541141326U, // ADR_LSL_ZZZ_S_0 |
| 541141326U, // ADR_LSL_ZZZ_S_1 |
| 541141326U, // ADR_LSL_ZZZ_S_2 |
| 541141326U, // ADR_LSL_ZZZ_S_3 |
| 406890830U, // ADR_SXTW_ZZZ_D_0 |
| 406890830U, // ADR_SXTW_ZZZ_D_1 |
| 406890830U, // ADR_SXTW_ZZZ_D_2 |
| 406890830U, // ADR_SXTW_ZZZ_D_3 |
| 406890830U, // ADR_UXTW_ZZZ_D_0 |
| 406890830U, // ADR_UXTW_ZZZ_D_1 |
| 406890830U, // ADR_UXTW_ZZZ_D_2 |
| 406890830U, // ADR_UXTW_ZZZ_D_3 |
| 268551140U, // AESDrr |
| 268551170U, // AESErr |
| 134300522U, // AESIMCrr |
| 0U, // AESIMCrrTied |
| 134300534U, // AESMCrr |
| 0U, // AESMCrrTied |
| 201439377U, // ANDSWri |
| 0U, // ANDSWrr |
| 201439377U, // ANDSWrs |
| 201439377U, // ANDSXri |
| 0U, // ANDSXrr |
| 201439377U, // ANDSXrs |
| 604010641U, // ANDS_PPzPP |
| 604092945U, // ANDV_VPZ_B |
| 604092945U, // ANDV_VPZ_D |
| 604092945U, // ANDV_VPZ_H |
| 604092945U, // ANDV_VPZ_S |
| 201430000U, // ANDWri |
| 0U, // ANDWrr |
| 201430000U, // ANDWrs |
| 201430000U, // ANDXri |
| 0U, // ANDXrr |
| 201430000U, // ANDXrs |
| 604001264U, // AND_PPzPP |
| 402691056U, // AND_ZI |
| 604001264U, // AND_ZPmZ_B |
| 604017648U, // AND_ZPmZ_D |
| 70308848U, // AND_ZPmZ_H |
| 604050416U, // AND_ZPmZ_S |
| 402691056U, // AND_ZZZ |
| 134300635U, // ANDv16i8 |
| 134301515U, // ANDv8i8 |
| 604001284U, // ASRD_ZPmI_B |
| 604017668U, // ASRD_ZPmI_D |
| 70308868U, // ASRD_ZPmI_H |
| 604050436U, // ASRD_ZPmI_S |
| 604006844U, // ASRR_ZPmZ_B |
| 604023228U, // ASRR_ZPmZ_D |
| 70314428U, // ASRR_ZPmZ_H |
| 604055996U, // ASRR_ZPmZ_S |
| 201435592U, // ASRVWr |
| 201435592U, // ASRVXr |
| 604006856U, // ASR_WIDE_ZPmZ_B |
| 70314440U, // ASR_WIDE_ZPmZ_H |
| 604056008U, // ASR_WIDE_ZPmZ_S |
| 335571400U, // ASR_WIDE_ZZZ_B |
| 471919048U, // ASR_WIDE_ZZZ_H |
| 536947144U, // ASR_WIDE_ZZZ_S |
| 604006856U, // ASR_ZPmI_B |
| 604023240U, // ASR_ZPmI_D |
| 70314440U, // ASR_ZPmI_H |
| 604056008U, // ASR_ZPmI_S |
| 604006856U, // ASR_ZPmZ_B |
| 604023240U, // ASR_ZPmZ_D |
| 70314440U, // ASR_ZPmZ_H |
| 604056008U, // ASR_ZPmZ_S |
| 335571400U, // ASR_ZZI_B |
| 402696648U, // ASR_ZZI_D |
| 471919048U, // ASR_ZZI_H |
| 536947144U, // ASR_ZZI_S |
| 201425075U, // AUTDA |
| 201427578U, // AUTDB |
| 5341560U, // AUTDZA |
| 5344482U, // AUTDZB |
| 201425096U, // AUTIA |
| 15628U, // AUTIA1716 |
| 15820U, // AUTIASP |
| 15901U, // AUTIAZ |
| 201427598U, // AUTIB |
| 15648U, // AUTIB1716 |
| 15836U, // AUTIBSP |
| 15915U, // AUTIBZ |
| 5341576U, // AUTIZA |
| 5344498U, // AUTIZB |
| 131476U, // B |
| 15881U, // BCAX |
| 738305912U, // BFMWri |
| 738305912U, // BFMXri |
| 0U, // BICSWrr |
| 201439364U, // BICSWrs |
| 0U, // BICSXrr |
| 201439364U, // BICSXrs |
| 604010628U, // BICS_PPzPP |
| 0U, // BICWrr |
| 201428228U, // BICWrs |
| 0U, // BICXrr |
| 201428228U, // BICXrs |
| 603999492U, // BIC_PPzPP |
| 603999492U, // BIC_ZPmZ_B |
| 604015876U, // BIC_ZPmZ_D |
| 70307076U, // BIC_ZPmZ_H |
| 604048644U, // BIC_ZPmZ_S |
| 402689284U, // BIC_ZZZ |
| 134300513U, // BICv16i8 |
| 805432205U, // BICv2i32 |
| 805426838U, // BICv4i16 |
| 805434032U, // BICv4i32 |
| 805428676U, // BICv8i16 |
| 134301425U, // BICv8i8 |
| 134300684U, // BIFv16i8 |
| 134301541U, // BIFv8i8 |
| 268551557U, // BITv16i8 |
| 268552501U, // BITv8i8 |
| 140909U, // BL |
| 5351808U, // BLR |
| 201425046U, // BLRAA |
| 5356507U, // BLRAAZ |
| 201427461U, // BLRAB |
| 5356522U, // BLRABZ |
| 5351754U, // BR |
| 201425033U, // BRAA |
| 5356500U, // BRAAZ |
| 201427448U, // BRAB |
| 5356515U, // BRABZ |
| 157174U, // BRK |
| 604010559U, // BRKAS_PPzP |
| 16591U, // BRKA_PPmP |
| 603996367U, // BRKA_PPzP |
| 604010595U, // BRKBS_PPzP |
| 19093U, // BRKB_PPmP |
| 603998869U, // BRKB_PPzP |
| 604010710U, // BRKNS_PPzP |
| 604006340U, // BRKN_PPzP |
| 604010566U, // BRKPAS_PPzPP |
| 603996411U, // BRKPA_PPzPP |
| 604010602U, // BRKPBS_PPzPP |
| 603999088U, // BRKPB_PPzPP |
| 268551326U, // BSLv16i8 |
| 268552169U, // BSLv8i8 |
| 179272U, // Bcc |
| 738380318U, // CASAB |
| 738386749U, // CASAH |
| 738380503U, // CASALB |
| 738386900U, // CASALH |
| 738387528U, // CASALW |
| 738387528U, // CASALX |
| 738378048U, // CASAW |
| 738378048U, // CASAX |
| 738380850U, // CASB |
| 738387268U, // CASH |
| 738380597U, // CASLB |
| 738386994U, // CASLH |
| 738387743U, // CASLW |
| 738387743U, // CASLX |
| 206375U, // CASPALW |
| 222759U, // CASPALX |
| 196866U, // CASPAW |
| 213250U, // CASPAX |
| 206594U, // CASPLW |
| 222978U, // CASPLX |
| 207032U, // CASPW |
| 223416U, // CASPX |
| 738392122U, // CASW |
| 738392122U, // CASX |
| 872528897U, // CBNZW |
| 872528897U, // CBNZX |
| 872528882U, // CBZW |
| 872528882U, // CBZX |
| 201435082U, // CCMNWi |
| 201435082U, // CCMNWr |
| 201435082U, // CCMNXi |
| 201435082U, // CCMNXr |
| 201435290U, // CCMPWi |
| 201435290U, // CCMPWr |
| 201435290U, // CCMPXi |
| 201435290U, // CCMPXr |
| 15875U, // CFINV |
| 604078422U, // CLASTA_RPZ_B |
| 604078422U, // CLASTA_RPZ_D |
| 604078422U, // CLASTA_RPZ_H |
| 604078422U, // CLASTA_RPZ_S |
| 604078422U, // CLASTA_VPZ_B |
| 604078422U, // CLASTA_VPZ_D |
| 604078422U, // CLASTA_VPZ_H |
| 604078422U, // CLASTA_VPZ_S |
| 603996502U, // CLASTA_ZPZ_B |
| 604012886U, // CLASTA_ZPZ_D |
| 472957270U, // CLASTA_ZPZ_H |
| 604045654U, // CLASTA_ZPZ_S |
| 604081291U, // CLASTB_RPZ_B |
| 604081291U, // CLASTB_RPZ_D |
| 604081291U, // CLASTB_RPZ_H |
| 604081291U, // CLASTB_RPZ_S |
| 604081291U, // CLASTB_VPZ_B |
| 604081291U, // CLASTB_VPZ_D |
| 604081291U, // CLASTB_VPZ_H |
| 604081291U, // CLASTB_VPZ_S |
| 603999371U, // CLASTB_ZPZ_B |
| 604015755U, // CLASTB_ZPZ_D |
| 472960139U, // CLASTB_ZPZ_H |
| 604048523U, // CLASTB_ZPZ_S |
| 5356455U, // CLREX |
| 201439404U, // CLSWr |
| 201439404U, // CLSXr |
| 30892U, // CLS_ZPmZ_B |
| 47276U, // CLS_ZPmZ_D |
| 68221100U, // CLS_ZPmZ_H |
| 80044U, // CLS_ZPmZ_S |
| 134301032U, // CLSv16i8 |
| 134311671U, // CLSv2i32 |
| 134306281U, // CLSv4i16 |
| 134313602U, // CLSv4i32 |
| 134308165U, // CLSv8i16 |
| 134301979U, // CLSv8i8 |
| 201440252U, // CLZWr |
| 201440252U, // CLZXr |
| 31740U, // CLZ_ZPmZ_B |
| 48124U, // CLZ_ZPmZ_D |
| 68221948U, // CLZ_ZPmZ_H |
| 80892U, // CLZ_ZPmZ_S |
| 134301228U, // CLZv16i8 |
| 134311937U, // CLZv2i32 |
| 134306662U, // CLZv4i16 |
| 134314023U, // CLZv4i32 |
| 134308586U, // CLZv8i16 |
| 134302156U, // CLZv8i8 |
| 134300941U, // CMEQv16i8 |
| 134300941U, // CMEQv16i8rz |
| 201435404U, // CMEQv1i64 |
| 201435404U, // CMEQv1i64rz |
| 134311577U, // CMEQv2i32 |
| 134311577U, // CMEQv2i32rz |
| 134304204U, // CMEQv2i64 |
| 134304204U, // CMEQv2i64rz |
| 134306187U, // CMEQv4i16 |
| 134306187U, // CMEQv4i16rz |
| 134313508U, // CMEQv4i32 |
| 134313508U, // CMEQv4i32rz |
| 134308071U, // CMEQv8i16 |
| 134308071U, // CMEQv8i16rz |
| 134301897U, // CMEQv8i8 |
| 134301897U, // CMEQv8i8rz |
| 134300654U, // CMGEv16i8 |
| 134300654U, // CMGEv16i8rz |
| 201430048U, // CMGEv1i64 |
| 201430048U, // CMGEv1i64rz |
| 134310926U, // CMGEv2i32 |
| 134310926U, // CMGEv2i32rz |
| 134303622U, // CMGEv2i64 |
| 134303622U, // CMGEv2i64rz |
| 134305559U, // CMGEv4i16 |
| 134305559U, // CMGEv4i16rz |
| 134312753U, // CMGEv4i32 |
| 134312753U, // CMGEv4i32rz |
| 134307397U, // CMGEv8i16 |
| 134307397U, // CMGEv8i16rz |
| 134301523U, // CMGEv8i8 |
| 134301523U, // CMGEv8i8rz |
| 134301050U, // CMGTv16i8 |
| 134301050U, // CMGTv16i8rz |
| 201439574U, // CMGTv1i64 |
| 201439574U, // CMGTv1i64rz |
| 134311766U, // CMGTv2i32 |
| 134311766U, // CMGTv2i32rz |
| 134304377U, // CMGTv2i64 |
| 134304377U, // CMGTv2i64rz |
| 134306376U, // CMGTv4i16 |
| 134306376U, // CMGTv4i16rz |
| 134313697U, // CMGTv4i32 |
| 134313697U, // CMGTv4i32rz |
| 134308260U, // CMGTv8i16 |
| 134308260U, // CMGTv8i16rz |
| 134301995U, // CMGTv8i8 |
| 134301995U, // CMGTv8i8rz |
| 134300704U, // CMHIv16i8 |
| 201434577U, // CMHIv1i64 |
| 134311081U, // CMHIv2i32 |
| 134303703U, // CMHIv2i64 |
| 134305691U, // CMHIv4i16 |
| 134312920U, // CMHIv4i32 |
| 134307529U, // CMHIv8i16 |
| 134301559U, // CMHIv8i8 |
| 134301022U, // CMHSv16i8 |
| 201439391U, // CMHSv1i64 |
| 134311662U, // CMHSv2i32 |
| 134304281U, // CMHSv2i64 |
| 134306272U, // CMHSv4i16 |
| 134313593U, // CMHSv4i32 |
| 134308156U, // CMHSv8i16 |
| 134301970U, // CMHSv8i8 |
| 134300664U, // CMLEv16i8rz |
| 201430079U, // CMLEv1i64rz |
| 134310936U, // CMLEv2i32rz |
| 134303632U, // CMLEv2i64rz |
| 134305569U, // CMLEv4i16rz |
| 134312763U, // CMLEv4i32rz |
| 134307407U, // CMLEv8i16rz |
| 134301532U, // CMLEv8i8rz |
| 134301070U, // CMLTv16i8rz |
| 201439608U, // CMLTv1i64rz |
| 134311776U, // CMLTv2i32rz |
| 134304387U, // CMLTv2i64rz |
| 134306386U, // CMLTv4i16rz |
| 134313707U, // CMLTv4i32rz |
| 134308270U, // CMLTv8i16rz |
| 134302013U, // CMLTv8i8rz |
| 604006683U, // CMPEQ_PPzZI_B |
| 604023067U, // CMPEQ_PPzZI_D |
| 942729499U, // CMPEQ_PPzZI_H |
| 604055835U, // CMPEQ_PPzZI_S |
| 604006683U, // CMPEQ_PPzZZ_B |
| 604023067U, // CMPEQ_PPzZZ_D |
| 942729499U, // CMPEQ_PPzZZ_H |
| 604055835U, // CMPEQ_PPzZZ_S |
| 604006683U, // CMPEQ_WIDE_PPzZZ_B |
| 942729499U, // CMPEQ_WIDE_PPzZZ_H |
| 604055835U, // CMPEQ_WIDE_PPzZZ_S |
| 604001318U, // CMPGE_PPzZI_B |
| 604017702U, // CMPGE_PPzZI_D |
| 942724134U, // CMPGE_PPzZI_H |
| 604050470U, // CMPGE_PPzZI_S |
| 604001318U, // CMPGE_PPzZZ_B |
| 604017702U, // CMPGE_PPzZZ_D |
| 942724134U, // CMPGE_PPzZZ_H |
| 604050470U, // CMPGE_PPzZZ_S |
| 604001318U, // CMPGE_WIDE_PPzZZ_B |
| 942724134U, // CMPGE_WIDE_PPzZZ_H |
| 604050470U, // CMPGE_WIDE_PPzZZ_S |
| 604010844U, // CMPGT_PPzZI_B |
| 604027228U, // CMPGT_PPzZI_D |
| 942733660U, // CMPGT_PPzZI_H |
| 604059996U, // CMPGT_PPzZI_S |
| 604010844U, // CMPGT_PPzZZ_B |
| 604027228U, // CMPGT_PPzZZ_D |
| 942733660U, // CMPGT_PPzZZ_H |
| 604059996U, // CMPGT_PPzZZ_S |
| 604010844U, // CMPGT_WIDE_PPzZZ_B |
| 942733660U, // CMPGT_WIDE_PPzZZ_H |
| 604059996U, // CMPGT_WIDE_PPzZZ_S |
| 604005847U, // CMPHI_PPzZI_B |
| 604022231U, // CMPHI_PPzZI_D |
| 942728663U, // CMPHI_PPzZI_H |
| 604054999U, // CMPHI_PPzZI_S |
| 604005847U, // CMPHI_PPzZZ_B |
| 604022231U, // CMPHI_PPzZZ_D |
| 942728663U, // CMPHI_PPzZZ_H |
| 604054999U, // CMPHI_PPzZZ_S |
| 604005847U, // CMPHI_WIDE_PPzZZ_B |
| 942728663U, // CMPHI_WIDE_PPzZZ_H |
| 604054999U, // CMPHI_WIDE_PPzZZ_S |
| 604010661U, // CMPHS_PPzZI_B |
| 604027045U, // CMPHS_PPzZI_D |
| 942733477U, // CMPHS_PPzZI_H |
| 604059813U, // CMPHS_PPzZI_S |
| 604010661U, // CMPHS_PPzZZ_B |
| 604027045U, // CMPHS_PPzZZ_D |
| 942733477U, // CMPHS_PPzZZ_H |
| 604059813U, // CMPHS_PPzZZ_S |
| 604010661U, // CMPHS_WIDE_PPzZZ_B |
| 942733477U, // CMPHS_WIDE_PPzZZ_H |
| 604059813U, // CMPHS_WIDE_PPzZZ_S |
| 604001349U, // CMPLE_PPzZI_B |
| 604017733U, // CMPLE_PPzZI_D |
| 942724165U, // CMPLE_PPzZI_H |
| 604050501U, // CMPLE_PPzZI_S |
| 604001349U, // CMPLE_WIDE_PPzZZ_B |
| 942724165U, // CMPLE_WIDE_PPzZZ_H |
| 604050501U, // CMPLE_WIDE_PPzZZ_S |
| 604006502U, // CMPLO_PPzZI_B |
| 604022886U, // CMPLO_PPzZI_D |
| 942729318U, // CMPLO_PPzZI_H |
| 604055654U, // CMPLO_PPzZI_S |
| 604006502U, // CMPLO_WIDE_PPzZZ_B |
| 942729318U, // CMPLO_WIDE_PPzZZ_H |
| 604055654U, // CMPLO_WIDE_PPzZZ_S |
| 604010695U, // CMPLS_PPzZI_B |
| 604027079U, // CMPLS_PPzZI_D |
| 942733511U, // CMPLS_PPzZI_H |
| 604059847U, // CMPLS_PPzZI_S |
| 604010695U, // CMPLS_WIDE_PPzZZ_B |
| 942733511U, // CMPLS_WIDE_PPzZZ_H |
| 604059847U, // CMPLS_WIDE_PPzZZ_S |
| 604010878U, // CMPLT_PPzZI_B |
| 604027262U, // CMPLT_PPzZI_D |
| 942733694U, // CMPLT_PPzZI_H |
| 604060030U, // CMPLT_PPzZI_S |
| 604010878U, // CMPLT_WIDE_PPzZZ_B |
| 942733694U, // CMPLT_WIDE_PPzZZ_H |
| 604060030U, // CMPLT_WIDE_PPzZZ_S |
| 604001372U, // CMPNE_PPzZI_B |
| 604017756U, // CMPNE_PPzZI_D |
| 942724188U, // CMPNE_PPzZI_H |
| 604050524U, // CMPNE_PPzZI_S |
| 604001372U, // CMPNE_PPzZZ_B |
| 604017756U, // CMPNE_PPzZZ_D |
| 942724188U, // CMPNE_PPzZZ_H |
| 604050524U, // CMPNE_PPzZZ_S |
| 604001372U, // CMPNE_WIDE_PPzZZ_B |
| 942724188U, // CMPNE_WIDE_PPzZZ_H |
| 604050524U, // CMPNE_WIDE_PPzZZ_S |
| 0U, // CMP_SWAP_128 |
| 0U, // CMP_SWAP_16 |
| 0U, // CMP_SWAP_32 |
| 0U, // CMP_SWAP_64 |
| 0U, // CMP_SWAP_8 |
| 134301098U, // CMTSTv16i8 |
| 201439672U, // CMTSTv1i64 |
| 134311795U, // CMTSTv2i32 |
| 134304406U, // CMTSTv2i64 |
| 134306405U, // CMTSTv4i16 |
| 134313726U, // CMTSTv4i32 |
| 134308289U, // CMTSTv8i16 |
| 134302038U, // CMTSTv8i8 |
| 31132U, // CNOT_ZPmZ_B |
| 47516U, // CNOT_ZPmZ_D |
| 68221340U, // CNOT_ZPmZ_H |
| 80284U, // CNOT_ZPmZ_S |
| 1006734469U, // CNTB_XPiI |
| 1006736394U, // CNTD_XPiI |
| 1006740869U, // CNTH_XPiI |
| 604088510U, // CNTP_XPP_B |
| 604088510U, // CNTP_XPP_D |
| 604088510U, // CNTP_XPP_H |
| 604088510U, // CNTP_XPP_S |
| 1006746460U, // CNTW_XPiI |
| 31109U, // CNT_ZPmZ_B |
| 47493U, // CNT_ZPmZ_D |
| 68221317U, // CNT_ZPmZ_H |
| 80261U, // CNT_ZPmZ_S |
| 134301080U, // CNTv16i8 |
| 134302022U, // CNTv8i8 |
| 604027193U, // COMPACT_ZPZ_D |
| 604059961U, // COMPACT_ZPZ_S |
| 31695U, // CPY_ZPmI_B |
| 48079U, // CPY_ZPmI_D |
| 68221903U, // CPY_ZPmI_H |
| 80847U, // CPY_ZPmI_S |
| 31695U, // CPY_ZPmR_B |
| 48079U, // CPY_ZPmR_D |
| 68221903U, // CPY_ZPmR_H |
| 80847U, // CPY_ZPmR_S |
| 31695U, // CPY_ZPmV_B |
| 48079U, // CPY_ZPmV_D |
| 68221903U, // CPY_ZPmV_H |
| 80847U, // CPY_ZPmV_S |
| 604011471U, // CPY_ZPzI_B |
| 604027855U, // CPY_ZPzI_D |
| 942734287U, // CPY_ZPzI_H |
| 604060623U, // CPY_ZPzI_S |
| 134330973U, // CPYi16 |
| 134330973U, // CPYi32 |
| 134330973U, // CPYi64 |
| 134330973U, // CPYi8 |
| 201425363U, // CRC32Brr |
| 201427522U, // CRC32CBrr |
| 201433953U, // CRC32CHrr |
| 201439957U, // CRC32CWrr |
| 201440151U, // CRC32CXrr |
| 201430437U, // CRC32Hrr |
| 201439913U, // CRC32Wrr |
| 201440116U, // CRC32Xrr |
| 201434778U, // CSELWr |
| 201434778U, // CSELXr |
| 201428238U, // CSINCWr |
| 201428238U, // CSINCXr |
| 201439829U, // CSINVWr |
| 201439829U, // CSINVXr |
| 201430189U, // CSNEGWr |
| 201430189U, // CSNEGXr |
| 201435410U, // CTERMEQ_WW |
| 201435410U, // CTERMEQ_XX |
| 201430099U, // CTERMNE_WW |
| 201430099U, // CTERMNE_XX |
| 0U, // CompilerBarrier |
| 147480U, // DCPS1 |
| 147547U, // DCPS2 |
| 147564U, // DCPS3 |
| 1073842765U, // DECB_XPiI |
| 1073845144U, // DECD_XPiI |
| 1073779608U, // DECD_ZPiI |
| 1073849196U, // DECH_XPiI |
| 6349676U, // DECH_ZPiI |
| 335652982U, // DECP_XP_B |
| 402761846U, // DECP_XP_D |
| 1140959350U, // DECP_XP_H |
| 536979574U, // DECP_XP_S |
| 43126U, // DECP_ZP_D |
| 1209067638U, // DECP_ZP_H |
| 75894U, // DECP_ZP_S |
| 1073855200U, // DECW_XPiI |
| 1073822432U, // DECW_ZPiI |
| 232281U, // DMB |
| 15855U, // DRPS |
| 232504U, // DSB |
| 1275111321U, // DUPM_ZI |
| 1342204114U, // DUP_ZI_B |
| 1409329362U, // DUP_ZI_D |
| 7399634U, // DUP_ZI_H |
| 1476470994U, // DUP_ZI_S |
| 201353426U, // DUP_ZR_B |
| 201369810U, // DUP_ZR_D |
| 1216407762U, // DUP_ZR_H |
| 201402578U, // DUP_ZR_S |
| 335571154U, // DUP_ZZI_B |
| 402696402U, // DUP_ZZI_D |
| 1545660626U, // DUP_ZZI_H |
| 256210U, // DUP_ZZI_Q |
| 536946898U, // DUP_ZZI_S |
| 201409774U, // DUPv16i8gpr |
| 134300910U, // DUPv16i8lane |
| 201420402U, // DUPv2i32gpr |
| 134311538U, // DUPv2i32lane |
| 201413049U, // DUPv2i64gpr |
| 134304185U, // DUPv2i64lane |
| 201415012U, // DUPv4i16gpr |
| 134306148U, // DUPv4i16lane |
| 201422333U, // DUPv4i32gpr |
| 134313469U, // DUPv4i32lane |
| 201416896U, // DUPv8i16gpr |
| 134308032U, // DUPv8i16lane |
| 201410733U, // DUPv8i8gpr |
| 134301869U, // DUPv8i8lane |
| 0U, // EONWrr |
| 201435088U, // EONWrs |
| 0U, // EONXrr |
| 201435088U, // EONXrs |
| 15613U, // EOR3 |
| 604010760U, // EORS_PPzPP |
| 604093026U, // EORV_VPZ_B |
| 604093026U, // EORV_VPZ_D |
| 604093026U, // EORV_VPZ_H |
| 604093026U, // EORV_VPZ_S |
| 201435553U, // EORWri |
| 0U, // EORWrr |
| 201435553U, // EORWrs |
| 201435553U, // EORXri |
| 0U, // EORXrr |
| 201435553U, // EORXrs |
| 604006817U, // EOR_PPzPP |
| 402696609U, // EOR_ZI |
| 604006817U, // EOR_ZPmZ_B |
| 604023201U, // EOR_ZPmZ_D |
| 70314401U, // EOR_ZPmZ_H |
| 604055969U, // EOR_ZPmZ_S |
| 402696609U, // EOR_ZZZ |
| 134300993U, // EORv16i8 |
| 134301944U, // EORv8i8 |
| 15860U, // ERET |
| 15742U, // ERETAA |
| 15765U, // ERETAB |
| 201435630U, // EXTRWrri |
| 201435630U, // EXTRXrri |
| 335575495U, // EXT_ZZI |
| 134301109U, // EXTv16i8 |
| 134302048U, // EXTv8i8 |
| 0U, // F128CSEL |
| 201429885U, // FABD16 |
| 201429885U, // FABD32 |
| 201429885U, // FABD64 |
| 604017533U, // FABD_ZPmZ_D |
| 70308733U, // FABD_ZPmZ_H |
| 604050301U, // FABD_ZPmZ_S |
| 134310805U, // FABDv2f32 |
| 134303561U, // FABDv2f64 |
| 134305438U, // FABDv4f16 |
| 134312632U, // FABDv4f32 |
| 134307276U, // FABDv8f16 |
| 201439318U, // FABSDr |
| 201439318U, // FABSHr |
| 201439318U, // FABSSr |
| 47190U, // FABS_ZPmZ_D |
| 68221014U, // FABS_ZPmZ_H |
| 79958U, // FABS_ZPmZ_S |
| 134311643U, // FABSv2f32 |
| 134304262U, // FABSv2f64 |
| 134306253U, // FABSv4f16 |
| 134313574U, // FABSv4f32 |
| 134308137U, // FABSv8f16 |
| 201430040U, // FACGE16 |
| 201430040U, // FACGE32 |
| 201430040U, // FACGE64 |
| 604017688U, // FACGE_PPzZZ_D |
| 942724120U, // FACGE_PPzZZ_H |
| 604050456U, // FACGE_PPzZZ_S |
| 134310915U, // FACGEv2f32 |
| 134303611U, // FACGEv2f64 |
| 134305548U, // FACGEv4f16 |
| 134312742U, // FACGEv4f32 |
| 134307386U, // FACGEv8f16 |
| 201439566U, // FACGT16 |
| 201439566U, // FACGT32 |
| 201439566U, // FACGT64 |
| 604027214U, // FACGT_PPzZZ_D |
| 942733646U, // FACGT_PPzZZ_H |
| 604059982U, // FACGT_PPzZZ_S |
| 134311755U, // FACGTv2f32 |
| 134304366U, // FACGTv2f64 |
| 134306365U, // FACGTv4f16 |
| 134313686U, // FACGTv4f32 |
| 134308249U, // FACGTv8f16 |
| 604078252U, // FADDA_VPZ_D |
| 604078252U, // FADDA_VPZ_H |
| 604078252U, // FADDA_VPZ_S |
| 201429956U, // FADDDrr |
| 201429956U, // FADDHrr |
| 134311419U, // FADDPv2f32 |
| 134304086U, // FADDPv2f64 |
| 134321519U, // FADDPv2i16p |
| 134327803U, // FADDPv2i32p |
| 134320470U, // FADDPv2i64p |
| 134306029U, // FADDPv4f16 |
| 134313350U, // FADDPv4f32 |
| 134307913U, // FADDPv8f16 |
| 201429956U, // FADDSrr |
| 604092924U, // FADDV_VPZ_D |
| 604092924U, // FADDV_VPZ_H |
| 604092924U, // FADDV_VPZ_S |
| 604017604U, // FADD_ZPmI_D |
| 70308804U, // FADD_ZPmI_H |
| 604050372U, // FADD_ZPmI_S |
| 604017604U, // FADD_ZPmZ_D |
| 70308804U, // FADD_ZPmZ_H |
| 604050372U, // FADD_ZPmZ_S |
| 402691012U, // FADD_ZZZ_D |
| 471913412U, // FADD_ZZZ_H |
| 536941508U, // FADD_ZZZ_S |
| 134310842U, // FADDv2f32 |
| 134303580U, // FADDv2f64 |
| 134305475U, // FADDv4f16 |
| 134312669U, // FADDv4f32 |
| 134307313U, // FADDv8f16 |
| 604017590U, // FCADD_ZPmZ_D |
| 70308790U, // FCADD_ZPmZ_H |
| 604050358U, // FCADD_ZPmZ_S |
| 134310832U, // FCADDv2f32 |
| 134303570U, // FCADDv2f64 |
| 134305465U, // FCADDv4f16 |
| 134312659U, // FCADDv4f32 |
| 134307303U, // FCADDv8f16 |
| 201435289U, // FCCMPDrr |
| 201430123U, // FCCMPEDrr |
| 201430123U, // FCCMPEHrr |
| 201430123U, // FCCMPESrr |
| 201435289U, // FCCMPHrr |
| 201435289U, // FCCMPSrr |
| 201435403U, // FCMEQ16 |
| 201435403U, // FCMEQ32 |
| 201435403U, // FCMEQ64 |
| 604023051U, // FCMEQ_PPzZ0_D |
| 942729483U, // FCMEQ_PPzZ0_H |
| 604055819U, // FCMEQ_PPzZ0_S |
| 604023051U, // FCMEQ_PPzZZ_D |
| 942729483U, // FCMEQ_PPzZZ_H |
| 604055819U, // FCMEQ_PPzZZ_S |
| 201435403U, // FCMEQv1i16rz |
| 201435403U, // FCMEQv1i32rz |
| 201435403U, // FCMEQv1i64rz |
| 134311576U, // FCMEQv2f32 |
| 134304203U, // FCMEQv2f64 |
| 134311576U, // FCMEQv2i32rz |
| 134304203U, // FCMEQv2i64rz |
| 134306186U, // FCMEQv4f16 |
| 134313507U, // FCMEQv4f32 |
| 134306186U, // FCMEQv4i16rz |
| 134313507U, // FCMEQv4i32rz |
| 134308070U, // FCMEQv8f16 |
| 134308070U, // FCMEQv8i16rz |
| 201430047U, // FCMGE16 |
| 201430047U, // FCMGE32 |
| 201430047U, // FCMGE64 |
| 604017695U, // FCMGE_PPzZ0_D |
| 942724127U, // FCMGE_PPzZ0_H |
| 604050463U, // FCMGE_PPzZ0_S |
| 604017695U, // FCMGE_PPzZZ_D |
| 942724127U, // FCMGE_PPzZZ_H |
| 604050463U, // FCMGE_PPzZZ_S |
| 201430047U, // FCMGEv1i16rz |
| 201430047U, // FCMGEv1i32rz |
| 201430047U, // FCMGEv1i64rz |
| 134310925U, // FCMGEv2f32 |
| 134303621U, // FCMGEv2f64 |
| 134310925U, // FCMGEv2i32rz |
| 134303621U, // FCMGEv2i64rz |
| 134305558U, // FCMGEv4f16 |
| 134312752U, // FCMGEv4f32 |
| 134305558U, // FCMGEv4i16rz |
| 134312752U, // FCMGEv4i32rz |
| 134307396U, // FCMGEv8f16 |
| 134307396U, // FCMGEv8i16rz |
| 201439573U, // FCMGT16 |
| 201439573U, // FCMGT32 |
| 201439573U, // FCMGT64 |
| 604027221U, // FCMGT_PPzZ0_D |
| 942733653U, // FCMGT_PPzZ0_H |
| 604059989U, // FCMGT_PPzZ0_S |
| 604027221U, // FCMGT_PPzZZ_D |
| 942733653U, // FCMGT_PPzZZ_H |
| 604059989U, // FCMGT_PPzZZ_S |
| 201439573U, // FCMGTv1i16rz |
| 201439573U, // FCMGTv1i32rz |
| 201439573U, // FCMGTv1i64rz |
| 134311765U, // FCMGTv2f32 |
| 134304376U, // FCMGTv2f64 |
| 134311765U, // FCMGTv2i32rz |
| 134304376U, // FCMGTv2i64rz |
| 134306375U, // FCMGTv4f16 |
| 134313696U, // FCMGTv4f32 |
| 134306375U, // FCMGTv4i16rz |
| 134313696U, // FCMGTv4i32rz |
| 134308259U, // FCMGTv8f16 |
| 134308259U, // FCMGTv8i16rz |
| 604012757U, // FCMLA_ZPmZZ_D |
| 70303957U, // FCMLA_ZPmZZ_H |
| 604045525U, // FCMLA_ZPmZZ_S |
| 479248597U, // FCMLA_ZZZI_H |
| 1610678485U, // FCMLA_ZZZI_S |
| 268561176U, // FCMLAv2f32 |
| 268553960U, // FCMLAv2f64 |
| 268555809U, // FCMLAv4f16 |
| 268555809U, // FCMLAv4f16_indexed |
| 268562993U, // FCMLAv4f32 |
| 268562993U, // FCMLAv4f32_indexed |
| 268557647U, // FCMLAv8f16 |
| 268557647U, // FCMLAv8f16_indexed |
| 604017726U, // FCMLE_PPzZ0_D |
| 942724158U, // FCMLE_PPzZ0_H |
| 604050494U, // FCMLE_PPzZ0_S |
| 201430078U, // FCMLEv1i16rz |
| 201430078U, // FCMLEv1i32rz |
| 201430078U, // FCMLEv1i64rz |
| 134310935U, // FCMLEv2i32rz |
| 134303631U, // FCMLEv2i64rz |
| 134305568U, // FCMLEv4i16rz |
| 134312762U, // FCMLEv4i32rz |
| 134307406U, // FCMLEv8i16rz |
| 604027255U, // FCMLT_PPzZ0_D |
| 942733687U, // FCMLT_PPzZ0_H |
| 604060023U, // FCMLT_PPzZ0_S |
| 201439607U, // FCMLTv1i16rz |
| 201439607U, // FCMLTv1i32rz |
| 201439607U, // FCMLTv1i64rz |
| 134311775U, // FCMLTv2i32rz |
| 134304386U, // FCMLTv2i64rz |
| 134306385U, // FCMLTv4i16rz |
| 134313706U, // FCMLTv4i32rz |
| 134308269U, // FCMLTv8i16rz |
| 604017740U, // FCMNE_PPzZ0_D |
| 942724172U, // FCMNE_PPzZ0_H |
| 604050508U, // FCMNE_PPzZ0_S |
| 604017740U, // FCMNE_PPzZZ_D |
| 942724172U, // FCMNE_PPzZZ_H |
| 604050508U, // FCMNE_PPzZZ_S |
| 10594464U, // FCMPDri |
| 201435296U, // FCMPDrr |
| 10589299U, // FCMPEDri |
| 201430131U, // FCMPEDrr |
| 10589299U, // FCMPEHri |
| 201430131U, // FCMPEHrr |
| 10589299U, // FCMPESri |
| 201430131U, // FCMPESrr |
| 10594464U, // FCMPHri |
| 201435296U, // FCMPHrr |
| 10594464U, // FCMPSri |
| 201435296U, // FCMPSrr |
| 604022893U, // FCMUO_PPzZZ_D |
| 942729325U, // FCMUO_PPzZZ_H |
| 604055661U, // FCMUO_PPzZZ_S |
| 48078U, // FCPY_ZPmI_D |
| 68221902U, // FCPY_ZPmI_H |
| 80846U, // FCPY_ZPmI_S |
| 201434777U, // FCSELDrrr |
| 201434777U, // FCSELHrrr |
| 201434777U, // FCSELSrrr |
| 201439310U, // FCVTASUWDr |
| 201439310U, // FCVTASUWHr |
| 201439310U, // FCVTASUWSr |
| 201439310U, // FCVTASUXDr |
| 201439310U, // FCVTASUXHr |
| 201439310U, // FCVTASUXSr |
| 201439310U, // FCVTASv1f16 |
| 201439310U, // FCVTASv1i32 |
| 201439310U, // FCVTASv1i64 |
| 134311632U, // FCVTASv2f32 |
| 134304251U, // FCVTASv2f64 |
| 134306242U, // FCVTASv4f16 |
| 134313563U, // FCVTASv4f32 |
| 134308126U, // FCVTASv8f16 |
| 201439692U, // FCVTAUUWDr |
| 201439692U, // FCVTAUUWHr |
| 201439692U, // FCVTAUUWSr |
| 201439692U, // FCVTAUUXDr |
| 201439692U, // FCVTAUUXHr |
| 201439692U, // FCVTAUUXSr |
| 201439692U, // FCVTAUv1f16 |
| 201439692U, // FCVTAUv1i32 |
| 201439692U, // FCVTAUv1i64 |
| 134311805U, // FCVTAUv2f32 |
| 134304416U, // FCVTAUv2f64 |
| 134306415U, // FCVTAUv4f16 |
| 134313736U, // FCVTAUv4f32 |
| 134308299U, // FCVTAUv8f16 |
| 201439679U, // FCVTDHr |
| 201439679U, // FCVTDSr |
| 201439679U, // FCVTHDr |
| 201439679U, // FCVTHSr |
| 1689347900U, // FCVTLv2i32 |
| 146892604U, // FCVTLv4i16 |
| 1756446768U, // FCVTLv4i32 |
| 146882608U, // FCVTLv8i16 |
| 201439438U, // FCVTMSUWDr |
| 201439438U, // FCVTMSUWHr |
| 201439438U, // FCVTMSUWSr |
| 201439438U, // FCVTMSUXDr |
| 201439438U, // FCVTMSUXHr |
| 201439438U, // FCVTMSUXSr |
| 201439438U, // FCVTMSv1f16 |
| 201439438U, // FCVTMSv1i32 |
| 201439438U, // FCVTMSv1i64 |
| 134311688U, // FCVTMSv2f32 |
| 134304299U, // FCVTMSv2f64 |
| 134306298U, // FCVTMSv4f16 |
| 134313619U, // FCVTMSv4f32 |
| 134308182U, // FCVTMSv8f16 |
| 201439708U, // FCVTMUUWDr |
| 201439708U, // FCVTMUUWHr |
| 201439708U, // FCVTMUUWSr |
| 201439708U, // FCVTMUUXDr |
| 201439708U, // FCVTMUUXHr |
| 201439708U, // FCVTMUUXSr |
| 201439708U, // FCVTMUv1f16 |
| 201439708U, // FCVTMUv1i32 |
| 201439708U, // FCVTMUv1i64 |
| 134311827U, // FCVTMUv2f32 |
| 134304438U, // FCVTMUv2f64 |
| 134306437U, // FCVTMUv4f16 |
| 134313758U, // FCVTMUv4f32 |
| 134308321U, // FCVTMUv8f16 |
| 201439459U, // FCVTNSUWDr |
| 201439459U, // FCVTNSUWHr |
| 201439459U, // FCVTNSUWSr |
| 201439459U, // FCVTNSUXDr |
| 201439459U, // FCVTNSUXHr |
| 201439459U, // FCVTNSUXSr |
| 201439459U, // FCVTNSv1f16 |
| 201439459U, // FCVTNSv1i32 |
| 201439459U, // FCVTNSv1i64 |
| 134311699U, // FCVTNSv2f32 |
| 134304310U, // FCVTNSv2f64 |
| 134306309U, // FCVTNSv4f16 |
| 134313630U, // FCVTNSv4f32 |
| 134308193U, // FCVTNSv8f16 |
| 201439716U, // FCVTNUUWDr |
| 201439716U, // FCVTNUUWHr |
| 201439716U, // FCVTNUUWSr |
| 201439716U, // FCVTNUUXDr |
| 201439716U, // FCVTNUUXHr |
| 201439716U, // FCVTNUUXSr |
| 201439716U, // FCVTNUv1f16 |
| 201439716U, // FCVTNUv1i32 |
| 201439716U, // FCVTNUv1i64 |
| 134311838U, // FCVTNUv2f32 |
| 134304449U, // FCVTNUv2f64 |
| 134306448U, // FCVTNUv4f16 |
| 134313769U, // FCVTNUv4f32 |
| 134308332U, // FCVTNUv8f16 |
| 13723652U, // FCVTNv2i32 |
| 14772228U, // FCVTNv4i16 |
| 281133118U, // FCVTNv4i32 |
| 15843390U, // FCVTNv8i16 |
| 201439475U, // FCVTPSUWDr |
| 201439475U, // FCVTPSUWHr |
| 201439475U, // FCVTPSUWSr |
| 201439475U, // FCVTPSUXDr |
| 201439475U, // FCVTPSUXHr |
| 201439475U, // FCVTPSUXSr |
| 201439475U, // FCVTPSv1f16 |
| 201439475U, // FCVTPSv1i32 |
| 201439475U, // FCVTPSv1i64 |
| 134311721U, // FCVTPSv2f32 |
| 134304332U, // FCVTPSv2f64 |
| 134306331U, // FCVTPSv4f16 |
| 134313652U, // FCVTPSv4f32 |
| 134308215U, // FCVTPSv8f16 |
| 201439724U, // FCVTPUUWDr |
| 201439724U, // FCVTPUUWHr |
| 201439724U, // FCVTPUUWSr |
| 201439724U, // FCVTPUUXDr |
| 201439724U, // FCVTPUUXHr |
| 201439724U, // FCVTPUUXSr |
| 201439724U, // FCVTPUv1f16 |
| 201439724U, // FCVTPUv1i32 |
| 201439724U, // FCVTPUv1i64 |
| 134311849U, // FCVTPUv2f32 |
| 134304460U, // FCVTPUv2f64 |
| 134306459U, // FCVTPUv4f16 |
| 134313780U, // FCVTPUv4f32 |
| 134308343U, // FCVTPUv8f16 |
| 201439679U, // FCVTSDr |
| 201439679U, // FCVTSHr |
| 201435194U, // FCVTXNv1i64 |
| 13723706U, // FCVTXNv2f32 |
| 281133126U, // FCVTXNv4f32 |
| 201439528U, // FCVTZSSWDri |
| 201439528U, // FCVTZSSWHri |
| 201439528U, // FCVTZSSWSri |
| 201439528U, // FCVTZSSXDri |
| 201439528U, // FCVTZSSXHri |
| 201439528U, // FCVTZSSXSri |
| 201439528U, // FCVTZSUWDr |
| 201439528U, // FCVTZSUWHr |
| 201439528U, // FCVTZSUWSr |
| 201439528U, // FCVTZSUXDr |
| 201439528U, // FCVTZSUXHr |
| 201439528U, // FCVTZSUXSr |
| 47400U, // FCVTZS_ZPmZ_DtoD |
| 80168U, // FCVTZS_ZPmZ_DtoS |
| 47400U, // FCVTZS_ZPmZ_HtoD |
| 68221224U, // FCVTZS_ZPmZ_HtoH |
| 80168U, // FCVTZS_ZPmZ_HtoS |
| 47400U, // FCVTZS_ZPmZ_StoD |
| 80168U, // FCVTZS_ZPmZ_StoS |
| 201439528U, // FCVTZSd |
| 201439528U, // FCVTZSh |
| 201439528U, // FCVTZSs |
| 201439528U, // FCVTZSv1f16 |
| 201439528U, // FCVTZSv1i32 |
| 201439528U, // FCVTZSv1i64 |
| 134311744U, // FCVTZSv2f32 |
| 134304355U, // FCVTZSv2f64 |
| 134311744U, // FCVTZSv2i32_shift |
| 134304355U, // FCVTZSv2i64_shift |
| 134306354U, // FCVTZSv4f16 |
| 134313675U, // FCVTZSv4f32 |
| 134306354U, // FCVTZSv4i16_shift |
| 134313675U, // FCVTZSv4i32_shift |
| 134308238U, // FCVTZSv8f16 |
| 134308238U, // FCVTZSv8i16_shift |
| 201439732U, // FCVTZUSWDri |
| 201439732U, // FCVTZUSWHri |
| 201439732U, // FCVTZUSWSri |
| 201439732U, // FCVTZUSXDri |
| 201439732U, // FCVTZUSXHri |
| 201439732U, // FCVTZUSXSri |
| 201439732U, // FCVTZUUWDr |
| 201439732U, // FCVTZUUWHr |
| 201439732U, // FCVTZUUWSr |
| 201439732U, // FCVTZUUXDr |
| 201439732U, // FCVTZUUXHr |
| 201439732U, // FCVTZUUXSr |
| 47604U, // FCVTZU_ZPmZ_DtoD |
| 80372U, // FCVTZU_ZPmZ_DtoS |
| 47604U, // FCVTZU_ZPmZ_HtoD |
| 68221428U, // FCVTZU_ZPmZ_HtoH |
| 80372U, // FCVTZU_ZPmZ_HtoS |
| 47604U, // FCVTZU_ZPmZ_StoD |
| 80372U, // FCVTZU_ZPmZ_StoS |
| 201439732U, // FCVTZUd |
| 201439732U, // FCVTZUh |
| 201439732U, // FCVTZUs |
| 201439732U, // FCVTZUv1f16 |
| 201439732U, // FCVTZUv1i32 |
| 201439732U, // FCVTZUv1i64 |
| 134311860U, // FCVTZUv2f32 |
| 134304471U, // FCVTZUv2f64 |
| 134311860U, // FCVTZUv2i32_shift |
| 134304471U, // FCVTZUv2i64_shift |
| 134306470U, // FCVTZUv4f16 |
| 134313791U, // FCVTZUv4f32 |
| 134306470U, // FCVTZUv4i16_shift |
| 134313791U, // FCVTZUv4i32_shift |
| 134308354U, // FCVTZUv8f16 |
| 134308354U, // FCVTZUv8i16_shift |
| 68221375U, // FCVT_ZPmZ_DtoH |
| 80319U, // FCVT_ZPmZ_DtoS |
| 47551U, // FCVT_ZPmZ_HtoD |
| 80319U, // FCVT_ZPmZ_HtoS |
| 47551U, // FCVT_ZPmZ_StoD |
| 68221375U, // FCVT_ZPmZ_StoH |
| 201439772U, // FDIVDrr |
| 201439772U, // FDIVHrr |
| 604023311U, // FDIVR_ZPmZ_D |
| 70314511U, // FDIVR_ZPmZ_H |
| 604056079U, // FDIVR_ZPmZ_S |
| 201439772U, // FDIVSrr |
| 604027420U, // FDIV_ZPmZ_D |
| 70318620U, // FDIV_ZPmZ_H |
| 604060188U, // FDIV_ZPmZ_S |
| 134311871U, // FDIVv2f32 |
| 134304482U, // FDIVv2f64 |
| 134306490U, // FDIVv4f16 |
| 134313811U, // FDIVv4f32 |
| 134308374U, // FDIVv8f16 |
| 1811982545U, // FDUP_ZI_D |
| 16836817U, // FDUP_ZI_H |
| 1812015313U, // FDUP_ZI_S |
| 402686223U, // FEXPA_ZZ_D |
| 1210106127U, // FEXPA_ZZ_H |
| 536936719U, // FEXPA_ZZ_S |
| 201439536U, // FJCVTZS |
| 201429962U, // FMADDDrrr |
| 201429962U, // FMADDHrrr |
| 201429962U, // FMADDSrrr |
| 604017513U, // FMAD_ZPmZZ_D |
| 70308713U, // FMAD_ZPmZZ_H |
| 604050281U, // FMAD_ZPmZZ_S |
| 201440124U, // FMAXDrr |
| 201440124U, // FMAXHrr |
| 201435025U, // FMAXNMDrr |
| 201435025U, // FMAXNMHrr |
| 134311485U, // FMAXNMPv2f32 |
| 134304152U, // FMAXNMPv2f64 |
| 134321541U, // FMAXNMPv2i16p |
| 134327869U, // FMAXNMPv2i32p |
| 134320536U, // FMAXNMPv2i64p |
| 134306095U, // FMAXNMPv4f16 |
| 134313416U, // FMAXNMPv4f32 |
| 134307979U, // FMAXNMPv8f16 |
| 201435025U, // FMAXNMSrr |
| 604092983U, // FMAXNMV_VPZ_D |
| 604092983U, // FMAXNMV_VPZ_H |
| 604092983U, // FMAXNMV_VPZ_S |
| 134322917U, // FMAXNMVv4i16v |
| 134330238U, // FMAXNMVv4i32v |
| 134324801U, // FMAXNMVv8i16v |
| 604022673U, // FMAXNM_ZPmI_D |
| 70313873U, // FMAXNM_ZPmI_H |
| 604055441U, // FMAXNM_ZPmI_S |
| 604022673U, // FMAXNM_ZPmZ_D |
| 70313873U, // FMAXNM_ZPmZ_H |
| 604055441U, // FMAXNM_ZPmZ_S |
| 134311235U, // FMAXNMv2f32 |
| 134304044U, // FMAXNMv2f64 |
| 134305845U, // FMAXNMv4f16 |
| 134313280U, // FMAXNMv4f32 |
| 134307853U, // FMAXNMv8f16 |
| 134311546U, // FMAXPv2f32 |
| 134304193U, // FMAXPv2f64 |
| 134321563U, // FMAXPv2i16p |
| 134327930U, // FMAXPv2i32p |
| 134320577U, // FMAXPv2i64p |
| 134306156U, // FMAXPv4f16 |
| 134313477U, // FMAXPv4f32 |
| 134308040U, // FMAXPv8f16 |
| 201440124U, // FMAXSrr |
| 604093032U, // FMAXV_VPZ_D |
| 604093032U, // FMAXV_VPZ_H |
| 604093032U, // FMAXV_VPZ_S |
| 134322968U, // FMAXVv4i16v |
| 134330289U, // FMAXVv4i32v |
| 134324852U, // FMAXVv8i16v |
| 604027772U, // FMAX_ZPmI_D |
| 70318972U, // FMAX_ZPmI_H |
| 604060540U, // FMAX_ZPmI_S |
| 604027772U, // FMAX_ZPmZ_D |
| 70318972U, // FMAX_ZPmZ_H |
| 604060540U, // FMAX_ZPmZ_S |
| 134311889U, // FMAXv2f32 |
| 134304540U, // FMAXv2f64 |
| 134306614U, // FMAXv4f16 |
| 134313975U, // FMAXv4f32 |
| 134308538U, // FMAXv8f16 |
| 201435054U, // FMINDrr |
| 201435054U, // FMINHrr |
| 201435017U, // FMINNMDrr |
| 201435017U, // FMINNMHrr |
| 134311473U, // FMINNMPv2f32 |
| 134304140U, // FMINNMPv2f64 |
| 134321529U, // FMINNMPv2i16p |
| 134327857U, // FMINNMPv2i32p |
| 134320524U, // FMINNMPv2i64p |
| 134306083U, // FMINNMPv4f16 |
| 134313404U, // FMINNMPv4f32 |
| 134307967U, // FMINNMPv8f16 |
| 201435017U, // FMINNMSrr |
| 604092974U, // FMINNMV_VPZ_D |
| 604092974U, // FMINNMV_VPZ_H |
| 604092974U, // FMINNMV_VPZ_S |
| 134322905U, // FMINNMVv4i16v |
| 134330226U, // FMINNMVv4i32v |
| 134324789U, // FMINNMVv8i16v |
| 604022665U, // FMINNM_ZPmI_D |
| 70313865U, // FMINNM_ZPmI_H |
| 604055433U, // FMINNM_ZPmI_S |
| 604022665U, // FMINNM_ZPmZ_D |
| 70313865U, // FMINNM_ZPmZ_H |
| 604055433U, // FMINNM_ZPmZ_S |
| 134311224U, // FMINNMv2f32 |
| 134304033U, // FMINNMv2f64 |
| 134305834U, // FMINNMv4f16 |
| 134313269U, // FMINNMv4f32 |
| 134307842U, // FMINNMv8f16 |
| 134311497U, // FMINPv2f32 |
| 134304164U, // FMINPv2f64 |
| 134321553U, // FMINPv2i16p |
| 134327881U, // FMINPv2i32p |
| 134320548U, // FMINPv2i64p |
| 134306107U, // FMINPv4f16 |
| 134313428U, // FMINPv4f32 |
| 134307991U, // FMINPv8f16 |
| 201435054U, // FMINSrr |
| 604092992U, // FMINV_VPZ_D |
| 604092992U, // FMINV_VPZ_H |
| 604092992U, // FMINV_VPZ_S |
| 134322929U, // FMINVv4i16v |
| 134330250U, // FMINVv4i32v |
| 134324813U, // FMINVv8i16v |
| 604022702U, // FMIN_ZPmI_D |
| 70313902U, // FMIN_ZPmI_H |
| 604055470U, // FMIN_ZPmI_S |
| 604022702U, // FMIN_ZPmZ_D |
| 70313902U, // FMIN_ZPmZ_H |
| 604055470U, // FMIN_ZPmZ_S |
| 134311279U, // FMINv2f32 |
| 134304066U, // FMINv2f64 |
| 134305889U, // FMINv4f16 |
| 134313302U, // FMINv4f32 |
| 134307875U, // FMINv8f16 |
| 604012764U, // FMLA_ZPmZZ_D |
| 70303964U, // FMLA_ZPmZZ_H |
| 604045532U, // FMLA_ZPmZZ_S |
| 1879081180U, // FMLA_ZZZI_D |
| 1217446108U, // FMLA_ZZZI_H |
| 1610678492U, // FMLA_ZZZI_S |
| 738383028U, // FMLAv1i16_indexed |
| 738388542U, // FMLAv1i32_indexed |
| 738381087U, // FMLAv1i64_indexed |
| 268561186U, // FMLAv2f32 |
| 268553970U, // FMLAv2f64 |
| 268561186U, // FMLAv2i32_indexed |
| 268553970U, // FMLAv2i64_indexed |
| 268555819U, // FMLAv4f16 |
| 268563003U, // FMLAv4f32 |
| 268555819U, // FMLAv4i16_indexed |
| 268563003U, // FMLAv4i32_indexed |
| 268557657U, // FMLAv8f16 |
| 268557657U, // FMLAv8i16_indexed |
| 604027066U, // FMLS_ZPmZZ_D |
| 70318266U, // FMLS_ZPmZZ_H |
| 604059834U, // FMLS_ZPmZZ_S |
| 1879095482U, // FMLS_ZZZI_D |
| 1217460410U, // FMLS_ZZZI_H |
| 1610692794U, // FMLS_ZZZI_S |
| 738383124U, // FMLSv1i16_indexed |
| 738388638U, // FMLSv1i32_indexed |
| 738381103U, // FMLSv1i64_indexed |
| 268562175U, // FMLSv2f32 |
| 268554786U, // FMLSv2f64 |
| 268562175U, // FMLSv2i32_indexed |
| 268554786U, // FMLSv2i64_indexed |
| 268556785U, // FMLSv4f16 |
| 268564106U, // FMLSv4f32 |
| 268556785U, // FMLSv4i16_indexed |
| 268564106U, // FMLSv4i32_indexed |
| 268558669U, // FMLSv8f16 |
| 268558669U, // FMLSv8i16_indexed |
| 0U, // FMOVD0 |
| 134319422U, // FMOVDXHighr |
| 201439836U, // FMOVDXr |
| 1812052572U, // FMOVDi |
| 201439836U, // FMOVDr |
| 0U, // FMOVH0 |
| 201439836U, // FMOVHWr |
| 201439836U, // FMOVHXr |
| 1812052572U, // FMOVHi |
| 201439836U, // FMOVHr |
| 0U, // FMOVS0 |
| 201439836U, // FMOVSWr |
| 1812052572U, // FMOVSi |
| 201439836U, // FMOVSr |
| 201439836U, // FMOVWHr |
| 201439836U, // FMOVWSr |
| 219237694U, // FMOVXDHighr |
| 201439836U, // FMOVXDr |
| 201439836U, // FMOVXHr |
| 1812033480U, // FMOVv2f32_ns |
| 1812026091U, // FMOVv2f64_ns |
| 1812028175U, // FMOVv4f16_ns |
| 1812035496U, // FMOVv4f32_ns |
| 1812030059U, // FMOVv8f16_ns |
| 604015682U, // FMSB_ZPmZZ_D |
| 70306882U, // FMSB_ZPmZZ_H |
| 604048450U, // FMSB_ZPmZZ_S |
| 201428133U, // FMSUBDrrr |
| 201428133U, // FMSUBHrrr |
| 201428133U, // FMSUBSrrr |
| 201434947U, // FMULDrr |
| 201434947U, // FMULHrr |
| 201434947U, // FMULSrr |
| 201440183U, // FMULX16 |
| 201440183U, // FMULX32 |
| 201440183U, // FMULX64 |
| 604027831U, // FMULX_ZPmZ_D |
| 70319031U, // FMULX_ZPmZ_H |
| 604060599U, // FMULX_ZPmZ_S |
| 201430323U, // FMULXv1i16_indexed |
| 201435837U, // FMULXv1i32_indexed |
| 201428302U, // FMULXv1i64_indexed |
| 134311916U, // FMULXv2f32 |
| 134304549U, // FMULXv2f64 |
| 134311916U, // FMULXv2i32_indexed |
| 134304549U, // FMULXv2i64_indexed |
| 134306641U, // FMULXv4f16 |
| 134314002U, // FMULXv4f32 |
| 134306641U, // FMULXv4i16_indexed |
| 134314002U, // FMULXv4i32_indexed |
| 134308565U, // FMULXv8f16 |
| 134308565U, // FMULXv8i16_indexed |
| 604022595U, // FMUL_ZPmI_D |
| 70313795U, // FMUL_ZPmI_H |
| 604055363U, // FMUL_ZPmI_S |
| 604022595U, // FMUL_ZPmZ_D |
| 70313795U, // FMUL_ZPmZ_H |
| 604055363U, // FMUL_ZPmZ_S |
| 402696003U, // FMUL_ZZZI_D |
| 471918403U, // FMUL_ZZZI_H |
| 536946499U, // FMUL_ZZZI_S |
| 402696003U, // FMUL_ZZZ_D |
| 471918403U, // FMUL_ZZZ_H |
| 536946499U, // FMUL_ZZZ_S |
| 201430284U, // FMULv1i16_indexed |
| 201435798U, // FMULv1i32_indexed |
| 201428263U, // FMULv1i64_indexed |
| 134311215U, // FMULv2f32 |
| 134304024U, // FMULv2f64 |
| 134311215U, // FMULv2i32_indexed |
| 134304024U, // FMULv2i64_indexed |
| 134305825U, // FMULv4f16 |
| 134313250U, // FMULv4f32 |
| 134305825U, // FMULv4i16_indexed |
| 134313250U, // FMULv4i32_indexed |
| 134307833U, // FMULv8f16 |
| 134307833U, // FMULv8i16_indexed |
| 201430176U, // FNEGDr |
| 201430176U, // FNEGHr |
| 201430176U, // FNEGSr |
| 38048U, // FNEG_ZPmZ_D |
| 68211872U, // FNEG_ZPmZ_H |
| 70816U, // FNEG_ZPmZ_S |
| 134311011U, // FNEGv2f32 |
| 134303684U, // FNEGv2f64 |
| 134305621U, // FNEGv4f16 |
| 134312838U, // FNEGv4f32 |
| 134307459U, // FNEGv8f16 |
| 201429969U, // FNMADDDrrr |
| 201429969U, // FNMADDHrrr |
| 201429969U, // FNMADDSrrr |
| 604017519U, // FNMAD_ZPmZZ_D |
| 70308719U, // FNMAD_ZPmZZ_H |
| 604050287U, // FNMAD_ZPmZZ_S |
| 604012770U, // FNMLA_ZPmZZ_D |
| 70303970U, // FNMLA_ZPmZZ_H |
| 604045538U, // FNMLA_ZPmZZ_S |
| 604027072U, // FNMLS_ZPmZZ_D |
| 70318272U, // FNMLS_ZPmZZ_H |
| 604059840U, // FNMLS_ZPmZZ_S |
| 604015688U, // FNMSB_ZPmZZ_D |
| 70306888U, // FNMSB_ZPmZZ_H |
| 604048456U, // FNMSB_ZPmZZ_S |
| 201428140U, // FNMSUBDrrr |
| 201428140U, // FNMSUBHrrr |
| 201428140U, // FNMSUBSrrr |
| 201434953U, // FNMULDrr |
| 201434953U, // FNMULHrr |
| 201434953U, // FNMULSrr |
| 402691171U, // FRECPE_ZZ_D |
| 1210111075U, // FRECPE_ZZ_H |
| 536941667U, // FRECPE_ZZ_S |
| 201430115U, // FRECPEv1f16 |
| 201430115U, // FRECPEv1i32 |
| 201430115U, // FRECPEv1i64 |
| 134310945U, // FRECPEv2f32 |
| 134303641U, // FRECPEv2f64 |
| 134305578U, // FRECPEv4f16 |
| 134312772U, // FRECPEv4f32 |
| 134307416U, // FRECPEv8f16 |
| 201439467U, // FRECPS16 |
| 201439467U, // FRECPS32 |
| 201439467U, // FRECPS64 |
| 402700523U, // FRECPS_ZZZ_D |
| 471922923U, // FRECPS_ZZZ_H |
| 536951019U, // FRECPS_ZZZ_S |
| 134311710U, // FRECPSv2f32 |
| 134304321U, // FRECPSv2f64 |
| 134306320U, // FRECPSv4f16 |
| 134313641U, // FRECPSv4f32 |
| 134308204U, // FRECPSv8f16 |
| 48062U, // FRECPX_ZPmZ_D |
| 68221886U, // FRECPX_ZPmZ_H |
| 80830U, // FRECPX_ZPmZ_S |
| 201440190U, // FRECPXv1f16 |
| 201440190U, // FRECPXv1i32 |
| 201440190U, // FRECPXv1i64 |
| 201425230U, // FRINTADr |
| 201425230U, // FRINTAHr |
| 201425230U, // FRINTASr |
| 33102U, // FRINTA_ZPmZ_D |
| 68206926U, // FRINTA_ZPmZ_H |
| 65870U, // FRINTA_ZPmZ_S |
| 134310737U, // FRINTAv2f32 |
| 134303521U, // FRINTAv2f64 |
| 134305370U, // FRINTAv4f16 |
| 134312554U, // FRINTAv4f32 |
| 134307208U, // FRINTAv8f16 |
| 201434600U, // FRINTIDr |
| 201434600U, // FRINTIHr |
| 201434600U, // FRINTISr |
| 42472U, // FRINTI_ZPmZ_D |
| 68216296U, // FRINTI_ZPmZ_H |
| 75240U, // FRINTI_ZPmZ_S |
| 134311115U, // FRINTIv2f32 |
| 134303728U, // FRINTIv2f64 |
| 134305725U, // FRINTIv4f16 |
| 134312954U, // FRINTIv4f32 |
| 134307563U, // FRINTIv8f16 |
| 201435039U, // FRINTMDr |
| 201435039U, // FRINTMHr |
| 201435039U, // FRINTMSr |
| 42911U, // FRINTM_ZPmZ_D |
| 68216735U, // FRINTM_ZPmZ_H |
| 75679U, // FRINTM_ZPmZ_S |
| 134311246U, // FRINTMv2f32 |
| 134304055U, // FRINTMv2f64 |
| 134305856U, // FRINTMv4f16 |
| 134313291U, // FRINTMv4f32 |
| 134307864U, // FRINTMv8f16 |
| 201435132U, // FRINTNDr |
| 201435132U, // FRINTNHr |
| 201435132U, // FRINTNSr |
| 43004U, // FRINTN_ZPmZ_D |
| 68216828U, // FRINTN_ZPmZ_H |
| 75772U, // FRINTN_ZPmZ_S |
| 134311352U, // FRINTNv2f32 |
| 134304075U, // FRINTNv2f64 |
| 134305962U, // FRINTNv4f16 |
| 134313329U, // FRINTNv4f32 |
| 134307902U, // FRINTNv8f16 |
| 201435332U, // FRINTPDr |
| 201435332U, // FRINTPHr |
| 201435332U, // FRINTPSr |
| 43204U, // FRINTP_ZPmZ_D |
| 68217028U, // FRINTP_ZPmZ_H |
| 75972U, // FRINTP_ZPmZ_S |
| 134311527U, // FRINTPv2f32 |
| 134304174U, // FRINTPv2f64 |
| 134306137U, // FRINTPv4f16 |
| 134313458U, // FRINTPv4f32 |
| 134308021U, // FRINTPv8f16 |
| 201440198U, // FRINTXDr |
| 201440198U, // FRINTXHr |
| 201440198U, // FRINTXSr |
| 48070U, // FRINTX_ZPmZ_D |
| 68221894U, // FRINTX_ZPmZ_H |
| 80838U, // FRINTX_ZPmZ_S |
| 134311926U, // FRINTXv2f32 |
| 134304559U, // FRINTXv2f64 |
| 134306651U, // FRINTXv4f16 |
| 134314012U, // FRINTXv4f32 |
| 134308575U, // FRINTXv8f16 |
| 201440269U, // FRINTZDr |
| 201440269U, // FRINTZHr |
| 201440269U, // FRINTZSr |
| 48141U, // FRINTZ_ZPmZ_D |
| 68221965U, // FRINTZ_ZPmZ_H |
| 80909U, // FRINTZ_ZPmZ_S |
| 134311945U, // FRINTZv2f32 |
| 134304570U, // FRINTZv2f64 |
| 134306670U, // FRINTZv4f16 |
| 134314031U, // FRINTZv4f32 |
| 134308594U, // FRINTZv8f16 |
| 402691202U, // FRSQRTE_ZZ_D |
| 1210111106U, // FRSQRTE_ZZ_H |
| 536941698U, // FRSQRTE_ZZ_S |
| 201430146U, // FRSQRTEv1f16 |
| 201430146U, // FRSQRTEv1i32 |
| 201430146U, // FRSQRTEv1i64 |
| 134310967U, // FRSQRTEv2f32 |
| 134303652U, // FRSQRTEv2f64 |
| 134305589U, // FRSQRTEv4f16 |
| 134312794U, // FRSQRTEv4f32 |
| 134307427U, // FRSQRTEv8f16 |
| 201439514U, // FRSQRTS16 |
| 201439514U, // FRSQRTS32 |
| 201439514U, // FRSQRTS64 |
| 402700570U, // FRSQRTS_ZZZ_D |
| 471922970U, // FRSQRTS_ZZZ_H |
| 536951066U, // FRSQRTS_ZZZ_S |
| 134311732U, // FRSQRTSv2f32 |
| 134304343U, // FRSQRTSv2f64 |
| 134306342U, // FRSQRTSv4f16 |
| 134313663U, // FRSQRTSv4f32 |
| 134308226U, // FRSQRTSv8f16 |
| 604017709U, // FSCALE_ZPmZ_D |
| 70308909U, // FSCALE_ZPmZ_H |
| 604050477U, // FSCALE_ZPmZ_S |
| 201439650U, // FSQRTDr |
| 201439650U, // FSQRTHr |
| 201439650U, // FSQRTSr |
| 47522U, // FSQRT_ZPmZ_D |
| 68221346U, // FSQRT_ZPmZ_H |
| 80290U, // FSQRT_ZPmZ_S |
| 134311785U, // FSQRTv2f32 |
| 134304396U, // FSQRTv2f64 |
| 134306395U, // FSQRTv4f16 |
| 134313716U, // FSQRTv4f32 |
| 134308279U, // FSQRTv8f16 |
| 201428127U, // FSUBDrr |
| 201428127U, // FSUBHrr |
| 604023111U, // FSUBR_ZPmI_D |
| 70314311U, // FSUBR_ZPmI_H |
| 604055879U, // FSUBR_ZPmI_S |
| 604023111U, // FSUBR_ZPmZ_D |
| 70314311U, // FSUBR_ZPmZ_H |
| 604055879U, // FSUBR_ZPmZ_S |
| 201428127U, // FSUBSrr |
| 604015775U, // FSUB_ZPmI_D |
| 70306975U, // FSUB_ZPmI_H |
| 604048543U, // FSUB_ZPmI_S |
| 604015775U, // FSUB_ZPmZ_D |
| 70306975U, // FSUB_ZPmZ_H |
| 604048543U, // FSUB_ZPmZ_S |
| 402689183U, // FSUB_ZZZ_D |
| 471911583U, // FSUB_ZZZ_H |
| 536939679U, // FSUB_ZZZ_S |
| 134310748U, // FSUBv2f32 |
| 134303532U, // FSUBv2f64 |
| 134305381U, // FSUBv4f16 |
| 134312565U, // FSUBv4f32 |
| 134307219U, // FSUBv8f16 |
| 402690934U, // FTMAD_ZZI_D |
| 471913334U, // FTMAD_ZZI_H |
| 536941430U, // FTMAD_ZZI_S |
| 402696016U, // FTSMUL_ZZZ_D |
| 471918416U, // FTSMUL_ZZZ_H |
| 536946512U, // FTSMUL_ZZZ_S |
| 402695840U, // FTSSEL_ZZZ_D |
| 471918240U, // FTSSEL_ZZZ_H |
| 536946336U, // FTSSEL_ZZZ_S |
| 1898185127U, // GLD1B_D_IMM_REAL |
| 757334439U, // GLD1B_D_REAL |
| 757334439U, // GLD1B_D_SXTW_REAL |
| 757334439U, // GLD1B_D_UXTW_REAL |
| 1629766055U, // GLD1B_S_IMM_REAL |
| 757350823U, // GLD1B_S_SXTW_REAL |
| 757350823U, // GLD1B_S_UXTW_REAL |
| 1898188163U, // GLD1D_IMM_REAL |
| 757337475U, // GLD1D_REAL |
| 757337475U, // GLD1D_SCALED_REAL |
| 757337475U, // GLD1D_SXTW_REAL |
| 757337475U, // GLD1D_SXTW_SCALED_REAL |
| 757337475U, // GLD1D_UXTW_REAL |
| 757337475U, // GLD1D_UXTW_SCALED_REAL |
| 1898190147U, // GLD1H_D_IMM_REAL |
| 757339459U, // GLD1H_D_REAL |
| 757339459U, // GLD1H_D_SCALED_REAL |
| 757339459U, // GLD1H_D_SXTW_REAL |
| 757339459U, // GLD1H_D_SXTW_SCALED_REAL |
| 757339459U, // GLD1H_D_UXTW_REAL |
| 757339459U, // GLD1H_D_UXTW_SCALED_REAL |
| 1629771075U, // GLD1H_S_IMM_REAL |
| 757355843U, // GLD1H_S_SXTW_REAL |
| 757355843U, // GLD1H_S_SXTW_SCALED_REAL |
| 757355843U, // GLD1H_S_UXTW_REAL |
| 757355843U, // GLD1H_S_UXTW_SCALED_REAL |
| 1898187801U, // GLD1SB_D_IMM_REAL |
| 757337113U, // GLD1SB_D_REAL |
| 757337113U, // GLD1SB_D_SXTW_REAL |
| 757337113U, // GLD1SB_D_UXTW_REAL |
| 1629768729U, // GLD1SB_S_IMM_REAL |
| 757353497U, // GLD1SB_S_SXTW_REAL |
| 757353497U, // GLD1SB_S_UXTW_REAL |
| 1898194219U, // GLD1SH_D_IMM_REAL |
| 757343531U, // GLD1SH_D_REAL |
| 757343531U, // GLD1SH_D_SCALED_REAL |
| 757343531U, // GLD1SH_D_SXTW_REAL |
| 757343531U, // GLD1SH_D_SXTW_SCALED_REAL |
| 757343531U, // GLD1SH_D_UXTW_REAL |
| 757343531U, // GLD1SH_D_UXTW_SCALED_REAL |
| 1629775147U, // GLD1SH_S_IMM_REAL |
| 757359915U, // GLD1SH_S_SXTW_REAL |
| 757359915U, // GLD1SH_S_SXTW_SCALED_REAL |
| 757359915U, // GLD1SH_S_UXTW_REAL |
| 757359915U, // GLD1SH_S_UXTW_SCALED_REAL |
| 1898199827U, // GLD1SW_D_IMM_REAL |
| 757349139U, // GLD1SW_D_REAL |
| 757349139U, // GLD1SW_D_SCALED_REAL |
| 757349139U, // GLD1SW_D_SXTW_REAL |
| 757349139U, // GLD1SW_D_SXTW_SCALED_REAL |
| 757349139U, // GLD1SW_D_UXTW_REAL |
| 757349139U, // GLD1SW_D_UXTW_SCALED_REAL |
| 1898199677U, // GLD1W_D_IMM_REAL |
| 757348989U, // GLD1W_D_REAL |
| 757348989U, // GLD1W_D_SCALED_REAL |
| 757348989U, // GLD1W_D_SXTW_REAL |
| 757348989U, // GLD1W_D_SXTW_SCALED_REAL |
| 757348989U, // GLD1W_D_UXTW_REAL |
| 757348989U, // GLD1W_D_UXTW_SCALED_REAL |
| 1629780605U, // GLD1W_IMM_REAL |
| 757365373U, // GLD1W_SXTW_REAL |
| 757365373U, // GLD1W_SXTW_SCALED_REAL |
| 757365373U, // GLD1W_UXTW_REAL |
| 757365373U, // GLD1W_UXTW_SCALED_REAL |
| 1898185133U, // GLDFF1B_D_IMM_REAL |
| 757334445U, // GLDFF1B_D_REAL |
| 757334445U, // GLDFF1B_D_SXTW_REAL |
| 757334445U, // GLDFF1B_D_UXTW_REAL |
| 1629766061U, // GLDFF1B_S_IMM_REAL |
| 757350829U, // GLDFF1B_S_SXTW_REAL |
| 757350829U, // GLDFF1B_S_UXTW_REAL |
| 1898188169U, // GLDFF1D_IMM_REAL |
| 757337481U, // GLDFF1D_REAL |
| 757337481U, // GLDFF1D_SCALED_REAL |
| 757337481U, // GLDFF1D_SXTW_REAL |
| 757337481U, // GLDFF1D_SXTW_SCALED_REAL |
| 757337481U, // GLDFF1D_UXTW_REAL |
| 757337481U, // GLDFF1D_UXTW_SCALED_REAL |
| 1898190153U, // GLDFF1H_D_IMM_REAL |
| 757339465U, // GLDFF1H_D_REAL |
| 757339465U, // GLDFF1H_D_SCALED_REAL |
| 757339465U, // GLDFF1H_D_SXTW_REAL |
| 757339465U, // GLDFF1H_D_SXTW_SCALED_REAL |
| 757339465U, // GLDFF1H_D_UXTW_REAL |
| 757339465U, // GLDFF1H_D_UXTW_SCALED_REAL |
| 1629771081U, // GLDFF1H_S_IMM_REAL |
| 757355849U, // GLDFF1H_S_SXTW_REAL |
| 757355849U, // GLDFF1H_S_SXTW_SCALED_REAL |
| 757355849U, // GLDFF1H_S_UXTW_REAL |
| 757355849U, // GLDFF1H_S_UXTW_SCALED_REAL |
| 1898187808U, // GLDFF1SB_D_IMM_REAL |
| 757337120U, // GLDFF1SB_D_REAL |
| 757337120U, // GLDFF1SB_D_SXTW_REAL |
| 757337120U, // GLDFF1SB_D_UXTW_REAL |
| 1629768736U, // GLDFF1SB_S_IMM_REAL |
| 757353504U, // GLDFF1SB_S_SXTW_REAL |
| 757353504U, // GLDFF1SB_S_UXTW_REAL |
| 1898194226U, // GLDFF1SH_D_IMM_REAL |
| 757343538U, // GLDFF1SH_D_REAL |
| 757343538U, // GLDFF1SH_D_SCALED_REAL |
| 757343538U, // GLDFF1SH_D_SXTW_REAL |
| 757343538U, // GLDFF1SH_D_SXTW_SCALED_REAL |
| 757343538U, // GLDFF1SH_D_UXTW_REAL |
| 757343538U, // GLDFF1SH_D_UXTW_SCALED_REAL |
| 1629775154U, // GLDFF1SH_S_IMM_REAL |
| 757359922U, // GLDFF1SH_S_SXTW_REAL |
| 757359922U, // GLDFF1SH_S_SXTW_SCALED_REAL |
| 757359922U, // GLDFF1SH_S_UXTW_REAL |
| 757359922U, // GLDFF1SH_S_UXTW_SCALED_REAL |
| 1898199834U, // GLDFF1SW_D_IMM_REAL |
| 757349146U, // GLDFF1SW_D_REAL |
| 757349146U, // GLDFF1SW_D_SCALED_REAL |
| 757349146U, // GLDFF1SW_D_SXTW_REAL |
| 757349146U, // GLDFF1SW_D_SXTW_SCALED_REAL |
| 757349146U, // GLDFF1SW_D_UXTW_REAL |
| 757349146U, // GLDFF1SW_D_UXTW_SCALED_REAL |
| 1898199683U, // GLDFF1W_D_IMM_REAL |
| 757348995U, // GLDFF1W_D_REAL |
| 757348995U, // GLDFF1W_D_SCALED_REAL |
| 757348995U, // GLDFF1W_D_SXTW_REAL |
| 757348995U, // GLDFF1W_D_SXTW_SCALED_REAL |
| 757348995U, // GLDFF1W_D_UXTW_REAL |
| 757348995U, // GLDFF1W_D_UXTW_SCALED_REAL |
| 1629780611U, // GLDFF1W_IMM_REAL |
| 757365379U, // GLDFF1W_SXTW_REAL |
| 757365379U, // GLDFF1W_SXTW_SCALED_REAL |
| 757365379U, // GLDFF1W_UXTW_REAL |
| 757365379U, // GLDFF1W_UXTW_SCALED_REAL |
| 309642U, // HINT |
| 162162U, // HLT |
| 150805U, // HVC |
| 1073842781U, // INCB_XPiI |
| 1073845160U, // INCD_XPiI |
| 1073779624U, // INCD_ZPiI |
| 1073849212U, // INCH_XPiI |
| 6349692U, // INCH_ZPiI |
| 335652998U, // INCP_XP_B |
| 402761862U, // INCP_XP_D |
| 1140959366U, // INCP_XP_H |
| 536979590U, // INCP_XP_S |
| 43142U, // INCP_ZP_D |
| 1209067654U, // INCP_ZP_H |
| 75910U, // INCP_ZP_S |
| 1073855216U, // INCW_XPiI |
| 1073822448U, // INCW_ZPiI |
| 201358240U, // INDEX_II_B |
| 201374624U, // INDEX_II_D |
| 478215072U, // INDEX_II_H |
| 201407392U, // INDEX_II_S |
| 201358240U, // INDEX_IR_B |
| 201374624U, // INDEX_IR_D |
| 478215072U, // INDEX_IR_H |
| 201407392U, // INDEX_IR_S |
| 201358240U, // INDEX_RI_B |
| 201374624U, // INDEX_RI_D |
| 478215072U, // INDEX_RI_H |
| 201407392U, // INDEX_RI_S |
| 201358240U, // INDEX_RR_B |
| 201374624U, // INDEX_RR_D |
| 478215072U, // INDEX_RR_H |
| 201407392U, // INDEX_RR_S |
| 738224599U, // INSR_ZR_B |
| 738240983U, // INSR_ZR_D |
| 1227942359U, // INSR_ZR_H |
| 738273751U, // INSR_ZR_S |
| 738224599U, // INSR_ZV_B |
| 738240983U, // INSR_ZV_D |
| 1227942359U, // INSR_ZV_H |
| 738273751U, // INSR_ZV_S |
| 1964102940U, // INSvi16gpr |
| 2031211804U, // INSvi16lane |
| 1964108454U, // INSvi32gpr |
| 2031217318U, // INSvi32lane |
| 1964100919U, // INSvi64gpr |
| 2031209783U, // INSvi64lane |
| 1964097936U, // INSvi8gpr |
| 2031206800U, // INSvi8lane |
| 232509U, // ISB |
| 604078423U, // LASTA_RPZ_B |
| 604078423U, // LASTA_RPZ_D |
| 604078423U, // LASTA_RPZ_H |
| 604078423U, // LASTA_RPZ_S |
| 604078423U, // LASTA_VPZ_B |
| 604078423U, // LASTA_VPZ_D |
| 604078423U, // LASTA_VPZ_H |
| 604078423U, // LASTA_VPZ_S |
| 604081292U, // LASTB_RPZ_B |
| 604081292U, // LASTB_RPZ_D |
| 604081292U, // LASTB_RPZ_H |
| 604081292U, // LASTB_RPZ_S |
| 604081292U, // LASTB_VPZ_B |
| 604081292U, // LASTB_VPZ_D |
| 604081292U, // LASTB_VPZ_H |
| 604081292U, // LASTB_VPZ_S |
| 757383591U, // LD1B |
| 757334439U, // LD1B_D |
| 757334439U, // LD1B_D_IMM_REAL |
| 757399975U, // LD1B_H |
| 757399975U, // LD1B_H_IMM_REAL |
| 757383591U, // LD1B_IMM_REAL |
| 757350823U, // LD1B_S |
| 757350823U, // LD1B_S_IMM_REAL |
| 757337475U, // LD1D |
| 757337475U, // LD1D_IMM_REAL |
| 344065U, // LD1Fourv16b |
| 21331969U, // LD1Fourv16b_POST |
| 376833U, // LD1Fourv1d |
| 22413313U, // LD1Fourv1d_POST |
| 409601U, // LD1Fourv2d |
| 21397505U, // LD1Fourv2d_POST |
| 442369U, // LD1Fourv2s |
| 22478849U, // LD1Fourv2s_POST |
| 475137U, // LD1Fourv4h |
| 22511617U, // LD1Fourv4h_POST |
| 507905U, // LD1Fourv4s |
| 21495809U, // LD1Fourv4s_POST |
| 540673U, // LD1Fourv8b |
| 22577153U, // LD1Fourv8b_POST |
| 573441U, // LD1Fourv8h |
| 21561345U, // LD1Fourv8h_POST |
| 757404995U, // LD1H |
| 757339459U, // LD1H_D |
| 757339459U, // LD1H_D_IMM_REAL |
| 757404995U, // LD1H_IMM_REAL |
| 757355843U, // LD1H_S |
| 757355843U, // LD1H_S_IMM_REAL |
| 344065U, // LD1Onev16b |
| 23429121U, // LD1Onev16b_POST |
| 376833U, // LD1Onev1d |
| 24510465U, // LD1Onev1d_POST |
| 409601U, // LD1Onev2d |
| 23494657U, // LD1Onev2d_POST |
| 442369U, // LD1Onev2s |
| 24576001U, // LD1Onev2s_POST |
| 475137U, // LD1Onev4h |
| 24608769U, // LD1Onev4h_POST |
| 507905U, // LD1Onev4s |
| 23592961U, // LD1Onev4s_POST |
| 540673U, // LD1Onev8b |
| 24674305U, // LD1Onev8b_POST |
| 573441U, // LD1Onev8h |
| 23658497U, // LD1Onev8h_POST |
| 757336965U, // LD1RB_D_IMM |
| 757402501U, // LD1RB_H_IMM |
| 757386117U, // LD1RB_IMM |
| 757353349U, // LD1RB_S_IMM |
| 757339133U, // LD1RD_IMM |
| 757343383U, // LD1RH_D_IMM |
| 757408919U, // LD1RH_IMM |
| 757359767U, // LD1RH_S_IMM |
| 757386109U, // LD1RQ_B |
| 757386109U, // LD1RQ_B_IMM |
| 757339125U, // LD1RQ_D |
| 757339125U, // LD1RQ_D_IMM |
| 757408911U, // LD1RQ_H |
| 757408911U, // LD1RQ_H_IMM |
| 757365508U, // LD1RQ_W |
| 757365508U, // LD1RQ_W_IMM |
| 757337167U, // LD1RSB_D_IMM |
| 757402703U, // LD1RSB_H_IMM |
| 757353551U, // LD1RSB_S_IMM |
| 757343572U, // LD1RSH_D_IMM |
| 757359956U, // LD1RSH_S_IMM |
| 757349171U, // LD1RSW_IMM |
| 757349132U, // LD1RW_D_IMM |
| 757365516U, // LD1RW_IMM |
| 354594U, // LD1Rv16b |
| 25536802U, // LD1Rv16b_POST |
| 387362U, // LD1Rv1d |
| 24520994U, // LD1Rv1d_POST |
| 420130U, // LD1Rv2d |
| 24553762U, // LD1Rv2d_POST |
| 452898U, // LD1Rv2s |
| 26683682U, // LD1Rv2s_POST |
| 485666U, // LD1Rv4h |
| 27765026U, // LD1Rv4h_POST |
| 518434U, // LD1Rv4s |
| 26749218U, // LD1Rv4s_POST |
| 551202U, // LD1Rv8b |
| 25733410U, // LD1Rv8b_POST |
| 583970U, // LD1Rv8h |
| 27863330U, // LD1Rv8h_POST |
| 757337113U, // LD1SB_D |
| 757337113U, // LD1SB_D_IMM_REAL |
| 757402649U, // LD1SB_H |
| 757402649U, // LD1SB_H_IMM_REAL |
| 757353497U, // LD1SB_S |
| 757353497U, // LD1SB_S_IMM_REAL |
| 757343531U, // LD1SH_D |
| 757343531U, // LD1SH_D_IMM_REAL |
| 757359915U, // LD1SH_S |
| 757359915U, // LD1SH_S_IMM_REAL |
| 757349139U, // LD1SW_D |
| 757349139U, // LD1SW_D_IMM_REAL |
| 344065U, // LD1Threev16b |
| 28672001U, // LD1Threev16b_POST |
| 376833U, // LD1Threev1d |
| 29753345U, // LD1Threev1d_POST |
| 409601U, // LD1Threev2d |
| 28737537U, // LD1Threev2d_POST |
| 442369U, // LD1Threev2s |
| 29818881U, // LD1Threev2s_POST |
| 475137U, // LD1Threev4h |
| 29851649U, // LD1Threev4h_POST |
| 507905U, // LD1Threev4s |
| 28835841U, // LD1Threev4s_POST |
| 540673U, // LD1Threev8b |
| 29917185U, // LD1Threev8b_POST |
| 573441U, // LD1Threev8h |
| 28901377U, // LD1Threev8h_POST |
| 344065U, // LD1Twov16b |
| 22380545U, // LD1Twov16b_POST |
| 376833U, // LD1Twov1d |
| 23461889U, // LD1Twov1d_POST |
| 409601U, // LD1Twov2d |
| 22446081U, // LD1Twov2d_POST |
| 442369U, // LD1Twov2s |
| 23527425U, // LD1Twov2s_POST |
| 475137U, // LD1Twov4h |
| 23560193U, // LD1Twov4h_POST |
| 507905U, // LD1Twov4s |
| 22544385U, // LD1Twov4s_POST |
| 540673U, // LD1Twov8b |
| 23625729U, // LD1Twov8b_POST |
| 573441U, // LD1Twov8h |
| 22609921U, // LD1Twov8h_POST |
| 757365373U, // LD1W |
| 757348989U, // LD1W_D |
| 757348989U, // LD1W_D_IMM_REAL |
| 757365373U, // LD1W_IMM_REAL |
| 31014913U, // LD1i16 |
| 32079873U, // LD1i16_POST |
| 31047681U, // LD1i32 |
| 33161217U, // LD1i32_POST |
| 31080449U, // LD1i64 |
| 34242561U, // LD1i64_POST |
| 31113217U, // LD1i8 |
| 35323905U, // LD1i8_POST |
| 757383643U, // LD2B |
| 757383643U, // LD2B_IMM |
| 757338949U, // LD2D |
| 757338949U, // LD2D_IMM |
| 757405101U, // LD2H |
| 757405101U, // LD2H_IMM |
| 354600U, // LD2Rv16b |
| 27633960U, // LD2Rv16b_POST |
| 387368U, // LD2Rv1d |
| 23472424U, // LD2Rv1d_POST |
| 420136U, // LD2Rv2d |
| 23505192U, // LD2Rv2d_POST |
| 452904U, // LD2Rv2s |
| 24586536U, // LD2Rv2s_POST |
| 485672U, // LD2Rv4h |
| 26716456U, // LD2Rv4h_POST |
| 518440U, // LD2Rv4s |
| 24652072U, // LD2Rv4s_POST |
| 551208U, // LD2Rv8b |
| 27830568U, // LD2Rv8b_POST |
| 583976U, // LD2Rv8h |
| 26814760U, // LD2Rv8h_POST |
| 344107U, // LD2Twov16b |
| 22380587U, // LD2Twov16b_POST |
| 409643U, // LD2Twov2d |
| 22446123U, // LD2Twov2d_POST |
| 442411U, // LD2Twov2s |
| 23527467U, // LD2Twov2s_POST |
| 475179U, // LD2Twov4h |
| 23560235U, // LD2Twov4h_POST |
| 507947U, // LD2Twov4s |
| 22544427U, // LD2Twov4s_POST |
| 540715U, // LD2Twov8b |
| 23625771U, // LD2Twov8b_POST |
| 573483U, // LD2Twov8h |
| 22609963U, // LD2Twov8h_POST |
| 757365425U, // LD2W |
| 757365425U, // LD2W_IMM |
| 31014955U, // LD2i16 |
| 33128491U, // LD2i16_POST |
| 31047723U, // LD2i32 |
| 34209835U, // LD2i32_POST |
| 31080491U, // LD2i64 |
| 36339755U, // LD2i64_POST |
| 31113259U, // LD2i8 |
| 32178219U, // LD2i8_POST |
| 757383655U, // LD3B |
| 757383655U, // LD3B_IMM |
| 757338961U, // LD3D |
| 757338961U, // LD3D_IMM |
| 757405113U, // LD3H |
| 757405113U, // LD3H_IMM |
| 354606U, // LD3Rv16b |
| 37071150U, // LD3Rv16b_POST |
| 387374U, // LD3Rv1d |
| 29763886U, // LD3Rv1d_POST |
| 420142U, // LD3Rv2d |
| 29796654U, // LD3Rv2d_POST |
| 452910U, // LD3Rv2s |
| 38218030U, // LD3Rv2s_POST |
| 485678U, // LD3Rv4h |
| 39299374U, // LD3Rv4h_POST |
| 518446U, // LD3Rv4s |
| 38283566U, // LD3Rv4s_POST |
| 551214U, // LD3Rv8b |
| 37267758U, // LD3Rv8b_POST |
| 583982U, // LD3Rv8h |
| 39397678U, // LD3Rv8h_POST |
| 344167U, // LD3Threev16b |
| 28672103U, // LD3Threev16b_POST |
| 409703U, // LD3Threev2d |
| 28737639U, // LD3Threev2d_POST |
| 442471U, // LD3Threev2s |
| 29818983U, // LD3Threev2s_POST |
| 475239U, // LD3Threev4h |
| 29851751U, // LD3Threev4h_POST |
| 508007U, // LD3Threev4s |
| 28835943U, // LD3Threev4s_POST |
| 540775U, // LD3Threev8b |
| 29917287U, // LD3Threev8b_POST |
| 573543U, // LD3Threev8h |
| 28901479U, // LD3Threev8h_POST |
| 757365437U, // LD3W |
| 757365437U, // LD3W_IMM |
| 31015015U, // LD3i16 |
| 40468583U, // LD3i16_POST |
| 31047783U, // LD3i32 |
| 41549927U, // LD3i32_POST |
| 31080551U, // LD3i64 |
| 42631271U, // LD3i64_POST |
| 31113319U, // LD3i8 |
| 43712615U, // LD3i8_POST |
| 757383667U, // LD4B |
| 757383667U, // LD4B_IMM |
| 757338973U, // LD4D |
| 757338973U, // LD4D_IMM |
| 344184U, // LD4Fourv16b |
| 21332088U, // LD4Fourv16b_POST |
| 409720U, // LD4Fourv2d |
| 21397624U, // LD4Fourv2d_POST |
| 442488U, // LD4Fourv2s |
| 22478968U, // LD4Fourv2s_POST |
| 475256U, // LD4Fourv4h |
| 22511736U, // LD4Fourv4h_POST |
| 508024U, // LD4Fourv4s |
| 21495928U, // LD4Fourv4s_POST |
| 540792U, // LD4Fourv8b |
| 22577272U, // LD4Fourv8b_POST |
| 573560U, // LD4Fourv8h |
| 21561464U, // LD4Fourv8h_POST |
| 757406585U, // LD4H |
| 757406585U, // LD4H_IMM |
| 354612U, // LD4Rv16b |
| 26585396U, // LD4Rv16b_POST |
| 387380U, // LD4Rv1d |
| 22423860U, // LD4Rv1d_POST |
| 420148U, // LD4Rv2d |
| 22456628U, // LD4Rv2d_POST |
| 452916U, // LD4Rv2s |
| 23537972U, // LD4Rv2s_POST |
| 485684U, // LD4Rv4h |
| 24619316U, // LD4Rv4h_POST |
| 518452U, // LD4Rv4s |
| 23603508U, // LD4Rv4s_POST |
| 551220U, // LD4Rv8b |
| 26782004U, // LD4Rv8b_POST |
| 583988U, // LD4Rv8h |
| 24717620U, // LD4Rv8h_POST |
| 757365449U, // LD4W |
| 757365449U, // LD4W_IMM |
| 31015032U, // LD4i16 |
| 34177144U, // LD4i16_POST |
| 31047800U, // LD4i32 |
| 36307064U, // LD4i32_POST |
| 31080568U, // LD4i64 |
| 44728440U, // LD4i64_POST |
| 31113336U, // LD4i8 |
| 33226872U, // LD4i8_POST |
| 2080557524U, // LDADDAB |
| 2080563965U, // LDADDAH |
| 2080557723U, // LDADDALB |
| 2080564120U, // LDADDALH |
| 2080564737U, // LDADDALW |
| 2080564737U, // LDADDALX |
| 2080555172U, // LDADDAW |
| 2080555172U, // LDADDAX |
| 2080557682U, // LDADDB |
| 2080564106U, // LDADDH |
| 2080557823U, // LDADDLB |
| 2080564220U, // LDADDLH |
| 2080564865U, // LDADDLW |
| 2080564865U, // LDADDLX |
| 2080560061U, // LDADDW |
| 2080560061U, // LDADDX |
| 205622208U, // LDAPRB |
| 205628626U, // LDAPRH |
| 205629872U, // LDAPRW |
| 205629872U, // LDAPRX |
| 205622251U, // LDAPURBi |
| 205628669U, // LDAPURHi |
| 205622382U, // LDAPURSBWi |
| 205622382U, // LDAPURSBXi |
| 205628787U, // LDAPURSHWi |
| 205628787U, // LDAPURSHXi |
| 205634386U, // LDAPURSWi |
| 205629953U, // LDAPURXi |
| 205629953U, // LDAPURi |
| 205622156U, // LDARB |
| 205628574U, // LDARH |
| 205629754U, // LDARW |
| 205629754U, // LDARX |
| 201435356U, // LDAXPW |
| 201435356U, // LDAXPX |
| 205622267U, // LDAXRB |
| 205628685U, // LDAXRH |
| 205629988U, // LDAXRW |
| 205629988U, // LDAXRX |
| 2080557580U, // LDCLRAB |
| 2080564011U, // LDCLRAH |
| 2080557763U, // LDCLRALB |
| 2080564160U, // LDCLRALH |
| 2080564790U, // LDCLRALW |
| 2080564790U, // LDCLRALX |
| 2080555286U, // LDCLRAW |
| 2080555286U, // LDCLRAX |
| 2080557985U, // LDCLRB |
| 2080564403U, // LDCLRH |
| 2080557859U, // LDCLRLB |
| 2080564256U, // LDCLRLH |
| 2080565007U, // LDCLRLW |
| 2080565007U, // LDCLRLX |
| 2080565637U, // LDCLRW |
| 2080565637U, // LDCLRX |
| 2080557589U, // LDEORAB |
| 2080564020U, // LDEORAH |
| 2080557773U, // LDEORALB |
| 2080564170U, // LDEORALH |
| 2080564799U, // LDEORALW |
| 2080564799U, // LDEORALX |
| 2080555294U, // LDEORAW |
| 2080555294U, // LDEORAX |
| 2080558008U, // LDEORB |
| 2080564426U, // LDEORH |
| 2080557868U, // LDEORLB |
| 2080564265U, // LDEORLH |
| 2080565015U, // LDEORLW |
| 2080565015U, // LDEORLX |
| 2080565663U, // LDEORW |
| 2080565663U, // LDEORX |
| 757334445U, // LDFF1B_D_REAL |
| 757399981U, // LDFF1B_H_REAL |
| 757383597U, // LDFF1B_REAL |
| 757350829U, // LDFF1B_S_REAL |
| 757337481U, // LDFF1D_REAL |
| 757339465U, // LDFF1H_D_REAL |
| 757405001U, // LDFF1H_REAL |
| 757355849U, // LDFF1H_S_REAL |
| 757337120U, // LDFF1SB_D_REAL |
| 757402656U, // LDFF1SB_H_REAL |
| 757353504U, // LDFF1SB_S_REAL |
| 757343538U, // LDFF1SH_D_REAL |
| 757359922U, // LDFF1SH_S_REAL |
| 757349146U, // LDFF1SW_D_REAL |
| 757348995U, // LDFF1W_D_REAL |
| 757365379U, // LDFF1W_REAL |
| 205622163U, // LDLARB |
| 205628581U, // LDLARH |
| 205629760U, // LDLARW |
| 205629760U, // LDLARX |
| 757334453U, // LDNF1B_D_IMM_REAL |
| 757399989U, // LDNF1B_H_IMM_REAL |
| 757383605U, // LDNF1B_IMM_REAL |
| 757350837U, // LDNF1B_S_IMM_REAL |
| 757337489U, // LDNF1D_IMM_REAL |
| 757339473U, // LDNF1H_D_IMM_REAL |
| 757405009U, // LDNF1H_IMM_REAL |
| 757355857U, // LDNF1H_S_IMM_REAL |
| 757337129U, // LDNF1SB_D_IMM_REAL |
| 757402665U, // LDNF1SB_H_IMM_REAL |
| 757353513U, // LDNF1SB_S_IMM_REAL |
| 757343547U, // LDNF1SH_D_IMM_REAL |
| 757359931U, // LDNF1SH_S_IMM_REAL |
| 757349155U, // LDNF1SW_D_IMM_REAL |
| 757349003U, // LDNF1W_D_IMM_REAL |
| 757365387U, // LDNF1W_IMM_REAL |
| 201435302U, // LDNPDi |
| 201435302U, // LDNPQi |
| 201435302U, // LDNPSi |
| 201435302U, // LDNPWi |
| 201435302U, // LDNPXi |
| 757383613U, // LDNT1B_ZRI |
| 757383613U, // LDNT1B_ZRR |
| 757337497U, // LDNT1D_ZRI |
| 757337497U, // LDNT1D_ZRR |
| 757405017U, // LDNT1H_ZRI |
| 757405017U, // LDNT1H_ZRR |
| 757365395U, // LDNT1W_ZRI |
| 757365395U, // LDNT1W_ZRR |
| 201435284U, // LDPDi |
| 738388116U, // LDPDpost |
| 738388116U, // LDPDpre |
| 201435284U, // LDPQi |
| 738388116U, // LDPQpost |
| 738388116U, // LDPQpre |
| 201440044U, // LDPSWi |
| 738392876U, // LDPSWpost |
| 738392876U, // LDPSWpre |
| 201435284U, // LDPSi |
| 738388116U, // LDPSpost |
| 738388116U, // LDPSpre |
| 201435284U, // LDPWi |
| 738388116U, // LDPWpost |
| 738388116U, // LDPWpre |
| 201435284U, // LDPXi |
| 738388116U, // LDPXpost |
| 738388116U, // LDPXpre |
| 205619343U, // LDRAAindexed |
| 742572175U, // LDRAAwriteback |
| 205621758U, // LDRABindexed |
| 742574590U, // LDRABwriteback |
| 742575003U, // LDRBBpost |
| 742575003U, // LDRBBpre |
| 205622171U, // LDRBBroW |
| 205622171U, // LDRBBroX |
| 205622171U, // LDRBBui |
| 742582611U, // LDRBpost |
| 742582611U, // LDRBpre |
| 205629779U, // LDRBroW |
| 205629779U, // LDRBroX |
| 205629779U, // LDRBui |
| 872524115U, // LDRDl |
| 742582611U, // LDRDpost |
| 742582611U, // LDRDpre |
| 205629779U, // LDRDroW |
| 205629779U, // LDRDroX |
| 205629779U, // LDRDui |
| 742581421U, // LDRHHpost |
| 742581421U, // LDRHHpre |
| 205628589U, // LDRHHroW |
| 205628589U, // LDRHHroX |
| 205628589U, // LDRHHui |
| 742582611U, // LDRHpost |
| 742582611U, // LDRHpre |
| 205629779U, // LDRHroW |
| 205629779U, // LDRHroX |
| 205629779U, // LDRHui |
| 872524115U, // LDRQl |
| 742582611U, // LDRQpost |
| 742582611U, // LDRQpre |
| 205629779U, // LDRQroW |
| 205629779U, // LDRQroX |
| 205629779U, // LDRQui |
| 742575191U, // LDRSBWpost |
| 742575191U, // LDRSBWpre |
| 205622359U, // LDRSBWroW |
| 205622359U, // LDRSBWroX |
| 205622359U, // LDRSBWui |
| 742575191U, // LDRSBXpost |
| 742575191U, // LDRSBXpre |
| 205622359U, // LDRSBXroW |
| 205622359U, // LDRSBXroX |
| 205622359U, // LDRSBXui |
| 742581596U, // LDRSHWpost |
| 742581596U, // LDRSHWpre |
| 205628764U, // LDRSHWroW |
| 205628764U, // LDRSHWroX |
| 205628764U, // LDRSHWui |
| 742581596U, // LDRSHXpost |
| 742581596U, // LDRSHXpre |
| 205628764U, // LDRSHXroW |
| 205628764U, // LDRSHXroX |
| 205628764U, // LDRSHXui |
| 872528699U, // LDRSWl |
| 742587195U, // LDRSWpost |
| 742587195U, // LDRSWpre |
| 205634363U, // LDRSWroW |
| 205634363U, // LDRSWroX |
| 205634363U, // LDRSWui |
| 872524115U, // LDRSl |
| 742582611U, // LDRSpost |
| 742582611U, // LDRSpre |
| 205629779U, // LDRSroW |
| 205629779U, // LDRSroX |
| 205629779U, // LDRSui |
| 872524115U, // LDRWl |
| 742582611U, // LDRWpost |
| 742582611U, // LDRWpre |
| 205629779U, // LDRWroW |
| 205629779U, // LDRWroX |
| 205629779U, // LDRWui |
| 872524115U, // LDRXl |
| 742582611U, // LDRXpost |
| 742582611U, // LDRXpre |
| 205629779U, // LDRXroW |
| 205629779U, // LDRXroX |
| 205629779U, // LDRXui |
| 206268755U, // LDR_PXI |
| 206268755U, // LDR_ZXI |
| 2080557605U, // LDSETAB |
| 2080564036U, // LDSETAH |
| 2080557791U, // LDSETALB |
| 2080564188U, // LDSETALH |
| 2080564815U, // LDSETALW |
| 2080564815U, // LDSETALX |
| 2080555334U, // LDSETAW |
| 2080555334U, // LDSETAX |
| 2080558205U, // LDSETB |
| 2080564605U, // LDSETH |
| 2080557884U, // LDSETLB |
| 2080564281U, // LDSETLH |
| 2080565044U, // LDSETLW |
| 2080565044U, // LDSETLX |
| 2080569671U, // LDSETW |
| 2080569671U, // LDSETX |
| 2080557614U, // LDSMAXAB |
| 2080564045U, // LDSMAXAH |
| 2080557801U, // LDSMAXALB |
| 2080564198U, // LDSMAXALH |
| 2080564824U, // LDSMAXALW |
| 2080564824U, // LDSMAXALX |
| 2080555358U, // LDSMAXAW |
| 2080555358U, // LDSMAXAX |
| 2080558280U, // LDSMAXB |
| 2080564637U, // LDSMAXH |
| 2080557893U, // LDSMAXLB |
| 2080564323U, // LDSMAXLH |
| 2080565093U, // LDSMAXLW |
| 2080565093U, // LDSMAXLX |
| 2080570242U, // LDSMAXW |
| 2080570242U, // LDSMAXX |
| 2080557533U, // LDSMINAB |
| 2080563984U, // LDSMINAH |
| 2080557733U, // LDSMINALB |
| 2080564130U, // LDSMINALH |
| 2080564755U, // LDSMINALW |
| 2080564755U, // LDSMINALX |
| 2080555241U, // LDSMINAW |
| 2080555241U, // LDSMINAX |
| 2080557918U, // LDSMINB |
| 2080564343U, // LDSMINH |
| 2080557832U, // LDSMINLB |
| 2080564229U, // LDSMINLH |
| 2080564969U, // LDSMINLW |
| 2080564969U, // LDSMINLX |
| 2080565172U, // LDSMINW |
| 2080565172U, // LDSMINX |
| 205622216U, // LDTRBi |
| 205628634U, // LDTRHi |
| 205622366U, // LDTRSBWi |
| 205622366U, // LDTRSBXi |
| 205628771U, // LDTRSHWi |
| 205628771U, // LDTRSHXi |
| 205634370U, // LDTRSWi |
| 205629917U, // LDTRWi |
| 205629917U, // LDTRXi |
| 2080557624U, // LDUMAXAB |
| 2080564055U, // LDUMAXAH |
| 2080557812U, // LDUMAXALB |
| 2080564209U, // LDUMAXALH |
| 2080564834U, // LDUMAXALW |
| 2080564834U, // LDUMAXALX |
| 2080555367U, // LDUMAXAW |
| 2080555367U, // LDUMAXAX |
| 2080558289U, // LDUMAXB |
| 2080564646U, // LDUMAXH |
| 2080557903U, // LDUMAXLB |
| 2080564333U, // LDUMAXLH |
| 2080565102U, // LDUMAXLW |
| 2080565102U, // LDUMAXLX |
| 2080570250U, // LDUMAXW |
| 2080570250U, // LDUMAXX |
| 2080557543U, // LDUMINAB |
| 2080563994U, // LDUMINAH |
| 2080557744U, // LDUMINALB |
| 2080564141U, // LDUMINALH |
| 2080564765U, // LDUMINALW |
| 2080564765U, // LDUMINALX |
| 2080555250U, // LDUMINAW |
| 2080555250U, // LDUMINAX |
| 2080557927U, // LDUMINB |
| 2080564352U, // LDUMINH |
| 2080557842U, // LDUMINLB |
| 2080564239U, // LDUMINLH |
| 2080564978U, // LDUMINLW |
| 2080564978U, // LDUMINLX |
| 2080565180U, // LDUMINW |
| 2080565180U, // LDUMINX |
| 205622236U, // LDURBBi |
| 205629940U, // LDURBi |
| 205629940U, // LDURDi |
| 205628654U, // LDURHHi |
| 205629940U, // LDURHi |
| 205629940U, // LDURQi |
| 205622374U, // LDURSBWi |
| 205622374U, // LDURSBXi |
| 205628779U, // LDURSHWi |
| 205628779U, // LDURSHXi |
| 205634378U, // LDURSWi |
| 205629940U, // LDURSi |
| 205629940U, // LDURWi |
| 205629940U, // LDURXi |
| 201435363U, // LDXPW |
| 201435363U, // LDXPX |
| 205622275U, // LDXRB |
| 205628693U, // LDXRH |
| 205629995U, // LDXRW |
| 205629995U, // LDXRX |
| 0U, // LOADgot |
| 604006803U, // LSLR_ZPmZ_B |
| 604023187U, // LSLR_ZPmZ_D |
| 70314387U, // LSLR_ZPmZ_H |
| 604055955U, // LSLR_ZPmZ_S |
| 201434921U, // LSLVWr |
| 201434921U, // LSLVXr |
| 604006185U, // LSL_WIDE_ZPmZ_B |
| 70313769U, // LSL_WIDE_ZPmZ_H |
| 604055337U, // LSL_WIDE_ZPmZ_S |
| 335570729U, // LSL_WIDE_ZZZ_B |
| 471918377U, // LSL_WIDE_ZZZ_H |
| 536946473U, // LSL_WIDE_ZZZ_S |
| 604006185U, // LSL_ZPmI_B |
| 604022569U, // LSL_ZPmI_D |
| 70313769U, // LSL_ZPmI_H |
| 604055337U, // LSL_ZPmI_S |
| 604006185U, // LSL_ZPmZ_B |
| 604022569U, // LSL_ZPmZ_D |
| 70313769U, // LSL_ZPmZ_H |
| 604055337U, // LSL_ZPmZ_S |
| 335570729U, // LSL_ZZI_B |
| 402695977U, // LSL_ZZI_D |
| 471918377U, // LSL_ZZI_H |
| 536946473U, // LSL_ZZI_S |
| 604006850U, // LSRR_ZPmZ_B |
| 604023234U, // LSRR_ZPmZ_D |
| 70314434U, // LSRR_ZPmZ_H |
| 604056002U, // LSRR_ZPmZ_S |
| 201435597U, // LSRVWr |
| 201435597U, // LSRVXr |
| 604006861U, // LSR_WIDE_ZPmZ_B |
| 70314445U, // LSR_WIDE_ZPmZ_H |
| 604056013U, // LSR_WIDE_ZPmZ_S |
| 335571405U, // LSR_WIDE_ZZZ_B |
| 471919053U, // LSR_WIDE_ZZZ_H |
| 536947149U, // LSR_WIDE_ZZZ_S |
| 604006861U, // LSR_ZPmI_B |
| 604023245U, // LSR_ZPmI_D |
| 70314445U, // LSR_ZPmI_H |
| 604056013U, // LSR_ZPmI_S |
| 604006861U, // LSR_ZPmZ_B |
| 604023245U, // LSR_ZPmZ_D |
| 70314445U, // LSR_ZPmZ_H |
| 604056013U, // LSR_ZPmZ_S |
| 335571405U, // LSR_ZZI_B |
| 402696653U, // LSR_ZZI_D |
| 471919053U, // LSR_ZZI_H |
| 536947149U, // LSR_ZZI_S |
| 201429963U, // MADDWrrr |
| 201429963U, // MADDXrrr |
| 604001130U, // MAD_ZPmZZ_B |
| 604017514U, // MAD_ZPmZZ_D |
| 70308714U, // MAD_ZPmZZ_H |
| 604050282U, // MAD_ZPmZZ_S |
| 603996375U, // MLA_ZPmZZ_B |
| 604012759U, // MLA_ZPmZZ_D |
| 70303959U, // MLA_ZPmZZ_H |
| 604045527U, // MLA_ZPmZZ_S |
| 268550914U, // MLAv16i8 |
| 268561178U, // MLAv2i32 |
| 268561178U, // MLAv2i32_indexed |
| 268555811U, // MLAv4i16 |
| 268555811U, // MLAv4i16_indexed |
| 268562995U, // MLAv4i32 |
| 268562995U, // MLAv4i32_indexed |
| 268557649U, // MLAv8i16 |
| 268557649U, // MLAv8i16_indexed |
| 268551835U, // MLAv8i8 |
| 604010683U, // MLS_ZPmZZ_B |
| 604027067U, // MLS_ZPmZZ_D |
| 70318267U, // MLS_ZPmZZ_H |
| 604059835U, // MLS_ZPmZZ_S |
| 268551537U, // MLSv16i8 |
| 268562176U, // MLSv2i32 |
| 268562176U, // MLSv2i32_indexed |
| 268556786U, // MLSv4i16 |
| 268556786U, // MLSv4i16_indexed |
| 268564107U, // MLSv4i32 |
| 268564107U, // MLSv4i32_indexed |
| 268558670U, // MLSv8i16 |
| 268558670U, // MLSv8i16_indexed |
| 268552483U, // MLSv8i8 |
| 2147591664U, // MOVID |
| 2214675516U, // MOVIv16b_ns |
| 2147569659U, // MOVIv2d_ns |
| 2214685910U, // MOVIv2i32 |
| 2214685910U, // MOVIv2s_msl |
| 2214680520U, // MOVIv4i16 |
| 2214687749U, // MOVIv4i32 |
| 2214687749U, // MOVIv4s_msl |
| 2214676368U, // MOVIv8b_ns |
| 2214682358U, // MOVIv8i16 |
| 805414395U, // MOVKWi |
| 805414395U, // MOVKXi |
| 2214701108U, // MOVNWi |
| 2214701108U, // MOVNXi |
| 31662U, // MOVPRFX_ZPmZ_B |
| 48046U, // MOVPRFX_ZPmZ_D |
| 68221870U, // MOVPRFX_ZPmZ_H |
| 80814U, // MOVPRFX_ZPmZ_S |
| 604011438U, // MOVPRFX_ZPzZ_B |
| 604027822U, // MOVPRFX_ZPzZ_D |
| 942734254U, // MOVPRFX_ZPzZ_H |
| 604060590U, // MOVPRFX_ZPzZ_S |
| 604732334U, // MOVPRFX_ZZ |
| 2214706197U, // MOVZWi |
| 2214706197U, // MOVZXi |
| 0U, // MOVaddr |
| 0U, // MOVaddrBA |
| 0U, // MOVaddrCP |
| 0U, // MOVaddrEXT |
| 0U, // MOVaddrJT |
| 0U, // MOVaddrTLS |
| 0U, // MOVbaseTLS |
| 0U, // MOVi32imm |
| 0U, // MOVi64imm |
| 2281814275U, // MRS |
| 603999299U, // MSB_ZPmZZ_B |
| 604015683U, // MSB_ZPmZZ_D |
| 70306883U, // MSB_ZPmZZ_H |
| 604048451U, // MSB_ZPmZZ_S |
| 764370U, // MSR |
| 780754U, // MSRpstateImm1 |
| 780754U, // MSRpstateImm4 |
| 201428134U, // MSUBWrrr |
| 201428134U, // MSUBXrrr |
| 335570756U, // MUL_ZI_B |
| 402696004U, // MUL_ZI_D |
| 471918404U, // MUL_ZI_H |
| 536946500U, // MUL_ZI_S |
| 604006212U, // MUL_ZPmZ_B |
| 604022596U, // MUL_ZPmZ_D |
| 70313796U, // MUL_ZPmZ_H |
| 604055364U, // MUL_ZPmZ_S |
| 134300840U, // MULv16i8 |
| 134311216U, // MULv2i32 |
| 134311216U, // MULv2i32_indexed |
| 134305826U, // MULv4i16 |
| 134305826U, // MULv4i16_indexed |
| 134313251U, // MULv4i32 |
| 134313251U, // MULv4i32_indexed |
| 134307834U, // MULv8i16 |
| 134307834U, // MULv8i16_indexed |
| 134301682U, // MULv8i8 |
| 2214685882U, // MVNIv2i32 |
| 2214685882U, // MVNIv2s_msl |
| 2214680492U, // MVNIv4i16 |
| 2214687721U, // MVNIv4i32 |
| 2214687721U, // MVNIv4s_msl |
| 2214682330U, // MVNIv8i16 |
| 604010640U, // NANDS_PPzPP |
| 604001263U, // NAND_PPzPP |
| 21665U, // NEG_ZPmZ_B |
| 38049U, // NEG_ZPmZ_D |
| 68211873U, // NEG_ZPmZ_H |
| 70817U, // NEG_ZPmZ_S |
| 134300695U, // NEGv16i8 |
| 201430177U, // NEGv1i64 |
| 134311012U, // NEGv2i32 |
| 134303685U, // NEGv2i64 |
| 134305622U, // NEGv4i16 |
| 134312839U, // NEGv4i32 |
| 134307460U, // NEGv8i16 |
| 134301551U, // NEGv8i8 |
| 604010766U, // NORS_PPzPP |
| 604006822U, // NOR_PPzPP |
| 31133U, // NOT_ZPmZ_B |
| 47517U, // NOT_ZPmZ_D |
| 68221341U, // NOT_ZPmZ_H |
| 80285U, // NOT_ZPmZ_S |
| 134301089U, // NOTv16i8 |
| 134302030U, // NOTv8i8 |
| 604010717U, // ORNS_PPzPP |
| 0U, // ORNWrr |
| 201435127U, // ORNWrs |
| 0U, // ORNXrr |
| 201435127U, // ORNXrs |
| 604006391U, // ORN_PPzPP |
| 134300869U, // ORNv16i8 |
| 134301776U, // ORNv8i8 |
| 604010772U, // ORRS_PPzPP |
| 201435575U, // ORRWri |
| 0U, // ORRWrr |
| 201435575U, // ORRWrs |
| 201435575U, // ORRXri |
| 0U, // ORRXrr |
| 201435575U, // ORRXrs |
| 604006839U, // ORR_PPzPP |
| 402696631U, // ORR_ZI |
| 604006839U, // ORR_ZPmZ_B |
| 604023223U, // ORR_ZPmZ_D |
| 70314423U, // ORR_ZPmZ_H |
| 604055991U, // ORR_ZPmZ_S |
| 402696631U, // ORR_ZZZ |
| 134301002U, // ORRv16i8 |
| 805433032U, // ORRv2i32 |
| 805427642U, // ORRv4i16 |
| 805434963U, // ORRv4i32 |
| 805429526U, // ORRv8i16 |
| 134301952U, // ORRv8i8 |
| 604093027U, // ORV_VPZ_B |
| 604093027U, // ORV_VPZ_D |
| 604093027U, // ORV_VPZ_H |
| 604093027U, // ORV_VPZ_S |
| 201425053U, // PACDA |
| 201427563U, // PACDB |
| 5341552U, // PACDZA |
| 5344474U, // PACDZB |
| 201425082U, // PACGA |
| 201425089U, // PACIA |
| 15618U, // PACIA1716 |
| 15812U, // PACIASP |
| 15894U, // PACIAZ |
| 201427591U, // PACIB |
| 15638U, // PACIB1716 |
| 15828U, // PACIBSP |
| 15908U, // PACIBZ |
| 5341568U, // PACIZA |
| 5344490U, // PACIZB |
| 5264506U, // PFALSE |
| 134306862U, // PMULLv16i8 |
| 134310145U, // PMULLv1i64 |
| 134310134U, // PMULLv2i64 |
| 134307783U, // PMULLv8i8 |
| 134300839U, // PMULv16i8 |
| 134301681U, // PMULv8i8 |
| 604010949U, // PNEXT_B |
| 604027333U, // PNEXT_D |
| 472971717U, // PNEXT_H |
| 604060101U, // PNEXT_S |
| 1992034945U, // PRFB_D_PZI |
| 490474113U, // PRFB_D_SCALED |
| 490474113U, // PRFB_D_SXTW_SCALED |
| 490474113U, // PRFB_D_UXTW_SCALED |
| 490474113U, // PRFB_PRI |
| 490474113U, // PRFB_PRR |
| 1993083521U, // PRFB_S_PZI |
| 490474113U, // PRFB_S_SXTW_SCALED |
| 490474113U, // PRFB_S_UXTW_SCALED |
| 2394690537U, // PRFD_D_PZI |
| 490476521U, // PRFD_D_SCALED |
| 490476521U, // PRFD_D_SXTW_SCALED |
| 490476521U, // PRFD_D_UXTW_SCALED |
| 490476521U, // PRFD_PRI |
| 490476521U, // PRFD_PRR |
| 2395739113U, // PRFD_S_PZI |
| 490476521U, // PRFD_S_SXTW_SCALED |
| 490476521U, // PRFD_S_UXTW_SCALED |
| 2461803410U, // PRFH_D_PZI |
| 490480530U, // PRFH_D_SCALED |
| 490480530U, // PRFH_D_SXTW_SCALED |
| 490480530U, // PRFH_D_UXTW_SCALED |
| 490480530U, // PRFH_PRI |
| 490480530U, // PRFH_PRR |
| 2462851986U, // PRFH_S_PZI |
| 490480530U, // PRFH_S_SXTW_SCALED |
| 490480530U, // PRFH_S_UXTW_SCALED |
| 873228163U, // PRFMl |
| 206333827U, // PRFMroW |
| 206333827U, // PRFMroX |
| 206333827U, // PRFMui |
| 490486526U, // PRFS_PRR |
| 206333863U, // PRFUMi |
| 2528918270U, // PRFW_D_PZI |
| 490486526U, // PRFW_D_SCALED |
| 490486526U, // PRFW_D_SXTW_SCALED |
| 490486526U, // PRFW_D_UXTW_SCALED |
| 490486526U, // PRFW_PRI |
| 2529966846U, // PRFW_S_PZI |
| 490486526U, // PRFW_S_SXTW_SCALED |
| 490486526U, // PRFW_S_UXTW_SCALED |
| 336296361U, // PTEST_PP |
| 1006663831U, // PTRUES_B |
| 1006680215U, // PTRUES_D |
| 47249559U, // PTRUES_H |
| 1006712983U, // PTRUES_S |
| 1006654603U, // PTRUE_B |
| 1006670987U, // PTRUE_D |
| 47240331U, // PTRUE_H |
| 1006703755U, // PTRUE_S |
| 48293302U, // PUNPKHI_PP |
| 48293963U, // PUNPKLO_PP |
| 134311268U, // RADDHNv2i64_v2i32 |
| 268562771U, // RADDHNv2i64_v4i32 |
| 134305878U, // RADDHNv4i32_v4i16 |
| 268557425U, // RADDHNv4i32_v8i16 |
| 268550709U, // RADDHNv8i16_v16i8 |
| 134301701U, // RADDHNv8i16_v8i8 |
| 15589U, // RAX1 |
| 201439587U, // RBITWr |
| 201439587U, // RBITXr |
| 31075U, // RBIT_ZPmZ_B |
| 47459U, // RBIT_ZPmZ_D |
| 68221283U, // RBIT_ZPmZ_H |
| 80227U, // RBIT_ZPmZ_S |
| 134301060U, // RBITv16i8 |
| 134302004U, // RBITv8i8 |
| 604010747U, // RDFFRS_PPz |
| 5269848U, // RDFFR_P |
| 604006744U, // RDFFR_PPz |
| 201434975U, // RDVLI_XI |
| 5355842U, // RET |
| 15743U, // RETAA |
| 15766U, // RETAB |
| 0U, // RET_ReallyLR |
| 201425026U, // REV16Wr |
| 201425026U, // REV16Xr |
| 134300387U, // REV16v16i8 |
| 134301311U, // REV16v8i8 |
| 201424932U, // REV32Xr |
| 134300189U, // REV32v16i8 |
| 134305248U, // REV32v4i16 |
| 134306720U, // REV32v8i16 |
| 134301264U, // REV32v8i8 |
| 134300376U, // REV64v16i8 |
| 134310652U, // REV64v2i32 |
| 134305285U, // REV64v4i16 |
| 134312469U, // REV64v4i32 |
| 134307123U, // REV64v8i16 |
| 134301301U, // REV64v8i8 |
| 36034U, // REVB_ZPmZ_D |
| 68209858U, // REVB_ZPmZ_H |
| 68802U, // REVB_ZPmZ_S |
| 42391U, // REVH_ZPmZ_D |
| 75159U, // REVH_ZPmZ_S |
| 47982U, // REVW_ZPmZ_D |
| 201439767U, // REVWr |
| 201439767U, // REVXr |
| 335575575U, // REV_PP_B |
| 402700823U, // REV_PP_D |
| 1210120727U, // REV_PP_H |
| 536951319U, // REV_PP_S |
| 335575575U, // REV_ZZ_B |
| 402700823U, // REV_ZZ_D |
| 1210120727U, // REV_ZZ_H |
| 536951319U, // REV_ZZ_S |
| 15777U, // RMIF |
| 201435563U, // RORVWr |
| 201435563U, // RORVXr |
| 268550750U, // RSHRNv16i8_shift |
| 134311330U, // RSHRNv2i32_shift |
| 134305940U, // RSHRNv4i16_shift |
| 268562809U, // RSHRNv4i32_shift |
| 268557463U, // RSHRNv8i16_shift |
| 134301754U, // RSHRNv8i8_shift |
| 134311257U, // RSUBHNv2i64_v2i32 |
| 268562759U, // RSUBHNv2i64_v4i32 |
| 134305867U, // RSUBHNv4i32_v4i16 |
| 268557413U, // RSUBHNv4i32_v8i16 |
| 268550696U, // RSUBHNv8i16_v16i8 |
| 134301690U, // RSUBHNv8i16_v8i8 |
| 268557226U, // SABALv16i8_v8i16 |
| 268554244U, // SABALv2i32_v2i64 |
| 268563470U, // SABALv4i16_v4i32 |
| 268553674U, // SABALv4i32_v2i64 |
| 268562544U, // SABALv8i16_v4i32 |
| 268558079U, // SABALv8i8_v8i16 |
| 268550894U, // SABAv16i8 |
| 268561158U, // SABAv2i32 |
| 268555791U, // SABAv4i16 |
| 268562975U, // SABAv4i32 |
| 268557629U, // SABAv8i16 |
| 268551817U, // SABAv8i8 |
| 134306796U, // SABDLv16i8_v8i16 |
| 134303820U, // SABDLv2i32_v2i64 |
| 134313046U, // SABDLv4i16_v4i32 |
| 134303257U, // SABDLv4i32_v2i64 |
| 134312127U, // SABDLv8i16_v4i32 |
| 134307643U, // SABDLv8i8_v8i16 |
| 604001155U, // SABD_ZPmZ_B |
| 604017539U, // SABD_ZPmZ_D |
| 70308739U, // SABD_ZPmZ_H |
| 604050307U, // SABD_ZPmZ_S |
| 134300545U, // SABDv16i8 |
| 134310814U, // SABDv2i32 |
| 134305447U, // SABDv4i16 |
| 134312641U, // SABDv4i32 |
| 134307285U, // SABDv8i16 |
| 134301433U, // SABDv8i8 |
| 268558419U, // SADALPv16i8_v8i16 |
| 268553559U, // SADALPv2i32_v1i64 |
| 268561925U, // SADALPv4i16_v2i32 |
| 268554592U, // SADALPv4i32_v2i64 |
| 268563856U, // SADALPv8i16_v4i32 |
| 268556535U, // SADALPv8i8_v4i16 |
| 134307945U, // SADDLPv16i8_v8i16 |
| 134303085U, // SADDLPv2i32_v1i64 |
| 134311451U, // SADDLPv4i16_v2i32 |
| 134304118U, // SADDLPv4i32_v2i64 |
| 134313382U, // SADDLPv8i16_v4i32 |
| 134306061U, // SADDLPv8i8_v4i16 |
| 134317524U, // SADDLVv16i8v |
| 134322883U, // SADDLVv4i16v |
| 134330204U, // SADDLVv4i32v |
| 134324767U, // SADDLVv8i16v |
| 134318460U, // SADDLVv8i8v |
| 134306818U, // SADDLv16i8_v8i16 |
| 134303840U, // SADDLv2i32_v2i64 |
| 134313066U, // SADDLv4i16_v4i32 |
| 134303279U, // SADDLv4i32_v2i64 |
| 134312149U, // SADDLv8i16_v4i32 |
| 134307663U, // SADDLv8i8_v8i16 |
| 604092931U, // SADDV_VPZ_B |
| 604092931U, // SADDV_VPZ_H |
| 604092931U, // SADDV_VPZ_S |
| 134307101U, // SADDWv16i8_v8i16 |
| 134304520U, // SADDWv2i32_v2i64 |
| 134313955U, // SADDWv4i16_v4i32 |
| 134303442U, // SADDWv4i32_v2i64 |
| 134312447U, // SADDWv8i16_v4i32 |
| 134308518U, // SADDWv8i8_v8i16 |
| 201439352U, // SBCSWr |
| 201439352U, // SBCSXr |
| 201428218U, // SBCWr |
| 201428218U, // SBCXr |
| 201434999U, // SBFMWri |
| 201434999U, // SBFMXri |
| 201430162U, // SCVTFSWDri |
| 201430162U, // SCVTFSWHri |
| 201430162U, // SCVTFSWSri |
| 201430162U, // SCVTFSXDri |
| 201430162U, // SCVTFSXHri |
| 201430162U, // SCVTFSXSri |
| 201430162U, // SCVTFUWDri |
| 201430162U, // SCVTFUWHri |
| 201430162U, // SCVTFUWSri |
| 201430162U, // SCVTFUXDri |
| 201430162U, // SCVTFUXHri |
| 201430162U, // SCVTFUXSri |
| 38034U, // SCVTF_ZPmZ_DtoD |
| 68211858U, // SCVTF_ZPmZ_DtoH |
| 70802U, // SCVTF_ZPmZ_DtoS |
| 68211858U, // SCVTF_ZPmZ_HtoH |
| 38034U, // SCVTF_ZPmZ_StoD |
| 68211858U, // SCVTF_ZPmZ_StoH |
| 70802U, // SCVTF_ZPmZ_StoS |
| 201430162U, // SCVTFd |
| 201430162U, // SCVTFh |
| 201430162U, // SCVTFs |
| 201430162U, // SCVTFv1i16 |
| 201430162U, // SCVTFv1i32 |
| 201430162U, // SCVTFv1i64 |
| 134310991U, // SCVTFv2f32 |
| 134303664U, // SCVTFv2f64 |
| 134310991U, // SCVTFv2i32_shift |
| 134303664U, // SCVTFv2i64_shift |
| 134305601U, // SCVTFv4f16 |
| 134312818U, // SCVTFv4f32 |
| 134305601U, // SCVTFv4i16_shift |
| 134312818U, // SCVTFv4i32_shift |
| 134307439U, // SCVTFv8f16 |
| 134307439U, // SCVTFv8i16_shift |
| 604023318U, // SDIVR_ZPmZ_D |
| 604056086U, // SDIVR_ZPmZ_S |
| 201439778U, // SDIVWr |
| 201439778U, // SDIVXr |
| 604027426U, // SDIV_ZPmZ_D |
| 604060194U, // SDIV_ZPmZ_S |
| 2550184336U, // SDOT_ZZZI_D |
| 2617325968U, // SDOT_ZZZI_S |
| 2550184336U, // SDOT_ZZZ_D |
| 2617325968U, // SDOT_ZZZ_S |
| 268564880U, // SDOTlanev16i8 |
| 268564880U, // SDOTlanev8i8 |
| 15865U, // SDOTv16i8 |
| 15865U, // SDOTv8i8 |
| 604006043U, // SEL_PPPP |
| 604006043U, // SEL_ZPZZ_B |
| 604022427U, // SEL_ZPZZ_D |
| 472966811U, // SEL_ZPZZ_H |
| 604055195U, // SEL_ZPZZ_S |
| 15658U, // SETF16 |
| 15665U, // SETF8 |
| 15848U, // SETFFR |
| 738390694U, // SHA1Crrr |
| 201430332U, // SHA1Hrr |
| 738391339U, // SHA1Mrrr |
| 738391420U, // SHA1Prrr |
| 268562452U, // SHA1SU0rrr |
| 268562505U, // SHA1SU1rr |
| 738390115U, // SHA256H2rrr |
| 738390937U, // SHA256Hrrr |
| 268562464U, // SHA256SU0rr |
| 268562517U, // SHA256SU1rrr |
| 15782U, // SHA512H |
| 15594U, // SHA512H2 |
| 15552U, // SHA512SU0 |
| 15569U, // SHA512SU1 |
| 134300589U, // SHADDv16i8 |
| 134310873U, // SHADDv2i32 |
| 134305506U, // SHADDv4i16 |
| 134312700U, // SHADDv4i32 |
| 134307344U, // SHADDv8i16 |
| 134301473U, // SHADDv8i8 |
| 134306841U, // SHLLv16i8 |
| 134303941U, // SHLLv2i32 |
| 134313167U, // SHLLv4i16 |
| 134303302U, // SHLLv4i32 |
| 134312172U, // SHLLv8i16 |
| 134307764U, // SHLLv8i8 |
| 201434794U, // SHLd |
| 134300744U, // SHLv16i8_shift |
| 134311137U, // SHLv2i32_shift |
| 134303862U, // SHLv2i64_shift |
| 134305747U, // SHLv4i16_shift |
| 134313088U, // SHLv4i32_shift |
| 134307685U, // SHLv8i16_shift |
| 134301595U, // SHLv8i8_shift |
| 268550724U, // SHRNv16i8_shift |
| 134311308U, // SHRNv2i32_shift |
| 134305918U, // SHRNv4i16_shift |
| 268562785U, // SHRNv4i32_shift |
| 268557439U, // SHRNv8i16_shift |
| 134301732U, // SHRNv8i8_shift |
| 134300469U, // SHSUBv16i8 |
| 134310757U, // SHSUBv2i32 |
| 134305390U, // SHSUBv4i16 |
| 134312574U, // SHSUBv4i32 |
| 134307228U, // SHSUBv8i16 |
| 134301385U, // SHSUBv8i8 |
| 738387422U, // SLId |
| 268551210U, // SLIv16i8_shift |
| 268561586U, // SLIv2i32_shift |
| 268554208U, // SLIv2i64_shift |
| 268556196U, // SLIv4i16_shift |
| 268563425U, // SLIv4i32_shift |
| 268558034U, // SLIv8i16_shift |
| 268552064U, // SLIv8i8_shift |
| 15579U, // SM3PARTW1 |
| 15603U, // SM3PARTW2 |
| 15562U, // SM3SS1 |
| 15726U, // SM3TT1A |
| 15749U, // SM3TT1B |
| 15734U, // SM3TT2A |
| 15757U, // SM3TT2B |
| 15772U, // SM4E |
| 15886U, // SM4ENCKEY |
| 201434761U, // SMADDLrrr |
| 134300919U, // SMAXPv16i8 |
| 134311556U, // SMAXPv2i32 |
| 134306166U, // SMAXPv4i16 |
| 134313487U, // SMAXPv4i32 |
| 134308050U, // SMAXPv8i16 |
| 134301877U, // SMAXPv8i8 |
| 604093039U, // SMAXV_VPZ_B |
| 604093039U, // SMAXV_VPZ_D |
| 604093039U, // SMAXV_VPZ_H |
| 604093039U, // SMAXV_VPZ_S |
| 134317570U, // SMAXVv16i8v |
| 134322978U, // SMAXVv4i16v |
| 134330299U, // SMAXVv4i32v |
| 134324862U, // SMAXVv8i16v |
| 134318502U, // SMAXVv8i8v |
| 335575940U, // SMAX_ZI_B |
| 402701188U, // SMAX_ZI_D |
| 471923588U, // SMAX_ZI_H |
| 536951684U, // SMAX_ZI_S |
| 604011396U, // SMAX_ZPmZ_B |
| 604027780U, // SMAX_ZPmZ_D |
| 70318980U, // SMAX_ZPmZ_H |
| 604060548U, // SMAX_ZPmZ_S |
| 134301208U, // SMAXv16i8 |
| 134311898U, // SMAXv2i32 |
| 134306623U, // SMAXv4i16 |
| 134313984U, // SMAXv4i32 |
| 134308547U, // SMAXv8i16 |
| 134302138U, // SMAXv8i8 |
| 150793U, // SMC |
| 134300888U, // SMINPv16i8 |
| 134311507U, // SMINPv2i32 |
| 134306117U, // SMINPv4i16 |
| 134313438U, // SMINPv4i32 |
| 134308001U, // SMINPv8i16 |
| 134301849U, // SMINPv8i8 |
| 604092999U, // SMINV_VPZ_B |
| 604092999U, // SMINV_VPZ_D |
| 604092999U, // SMINV_VPZ_H |
| 604092999U, // SMINV_VPZ_S |
| 134317548U, // SMINVv16i8v |
| 134322939U, // SMINVv4i16v |
| 134330260U, // SMINVv4i32v |
| 134324823U, // SMINVv8i16v |
| 134318482U, // SMINVv8i8v |
| 335570870U, // SMIN_ZI_B |
| 402696118U, // SMIN_ZI_D |
| 471918518U, // SMIN_ZI_H |
| 536946614U, // SMIN_ZI_S |
| 604006326U, // SMIN_ZPmZ_B |
| 604022710U, // SMIN_ZPmZ_D |
| 70313910U, // SMIN_ZPmZ_H |
| 604055478U, // SMIN_ZPmZ_S |
| 134300849U, // SMINv16i8 |
| 134311288U, // SMINv2i32 |
| 134305898U, // SMINv4i16 |
| 134313311U, // SMINv4i32 |
| 134307884U, // SMINv8i16 |
| 134301712U, // SMINv8i8 |
| 268557248U, // SMLALv16i8_v8i16 |
| 268554276U, // SMLALv2i32_indexed |
| 268554276U, // SMLALv2i32_v2i64 |
| 268563502U, // SMLALv4i16_indexed |
| 268563502U, // SMLALv4i16_v4i32 |
| 268553709U, // SMLALv4i32_indexed |
| 268553709U, // SMLALv4i32_v2i64 |
| 268562579U, // SMLALv8i16_indexed |
| 268562579U, // SMLALv8i16_v4i32 |
| 268558099U, // SMLALv8i8_v8i16 |
| 268557391U, // SMLSLv16i8_v8i16 |
| 268554500U, // SMLSLv2i32_indexed |
| 268554500U, // SMLSLv2i32_v2i64 |
| 268563726U, // SMLSLv4i16_indexed |
| 268563726U, // SMLSLv4i16_v4i32 |
| 268553867U, // SMLSLv4i32_indexed |
| 268553867U, // SMLSLv4i32_v2i64 |
| 268562737U, // SMLSLv8i16_indexed |
| 268562737U, // SMLSLv8i16_v4i32 |
| 268558309U, // SMLSLv8i8_v8i16 |
| 134321443U, // SMOVvi16to32 |
| 134321443U, // SMOVvi16to64 |
| 134326957U, // SMOVvi32to64 |
| 134316439U, // SMOVvi8to32 |
| 134316439U, // SMOVvi8to64 |
| 201434737U, // SMSUBLrrr |
| 604005461U, // SMULH_ZPmZ_B |
| 604021845U, // SMULH_ZPmZ_D |
| 70313045U, // SMULH_ZPmZ_H |
| 604054613U, // SMULH_ZPmZ_S |
| 201434197U, // SMULHrr |
| 134306873U, // SMULLv16i8_v8i16 |
| 134303972U, // SMULLv2i32_indexed |
| 134303972U, // SMULLv2i32_v2i64 |
| 134313198U, // SMULLv4i16_indexed |
| 134313198U, // SMULLv4i16_v4i32 |
| 134303336U, // SMULLv4i32_indexed |
| 134303336U, // SMULLv4i32_v2i64 |
| 134312206U, // SMULLv8i16_indexed |
| 134312206U, // SMULLv8i16_v4i32 |
| 134307793U, // SMULLv8i8_v8i16 |
| 604001296U, // SPLICE_ZPZ_B |
| 604017680U, // SPLICE_ZPZ_D |
| 472962064U, // SPLICE_ZPZ_H |
| 604050448U, // SPLICE_ZPZ_S |
| 134301011U, // SQABSv16i8 |
| 201439324U, // SQABSv1i16 |
| 201439324U, // SQABSv1i32 |
| 201439324U, // SQABSv1i64 |
| 201439324U, // SQABSv1i8 |
| 134311652U, // SQABSv2i32 |
| 134304271U, // SQABSv2i64 |
| 134306262U, // SQABSv4i16 |
| 134313583U, // SQABSv4i32 |
| 134308146U, // SQABSv8i16 |
| 134301960U, // SQABSv8i8 |
| 335565786U, // SQADD_ZI_B |
| 402691034U, // SQADD_ZI_D |
| 471913434U, // SQADD_ZI_H |
| 536941530U, // SQADD_ZI_S |
| 335565786U, // SQADD_ZZZ_B |
| 402691034U, // SQADD_ZZZ_D |
| 471913434U, // SQADD_ZZZ_H |
| 536941530U, // SQADD_ZZZ_S |
| 134300612U, // SQADDv16i8 |
| 201429978U, // SQADDv1i16 |
| 201429978U, // SQADDv1i32 |
| 201429978U, // SQADDv1i64 |
| 201429978U, // SQADDv1i8 |
| 134310894U, // SQADDv2i32 |
| 134303590U, // SQADDv2i64 |
| 134305527U, // SQADDv4i16 |
| 134312721U, // SQADDv4i32 |
| 134307365U, // SQADDv8i16 |
| 134301494U, // SQADDv8i8 |
| 1073842763U, // SQDECB_XPiI |
| 2684455499U, // SQDECB_XPiWdI |
| 1073845142U, // SQDECD_XPiI |
| 2684457878U, // SQDECD_XPiWdI |
| 1073779606U, // SQDECD_ZPiI |
| 1073849194U, // SQDECH_XPiI |
| 2684461930U, // SQDECH_XPiWdI |
| 6349674U, // SQDECH_ZPiI |
| 335652980U, // SQDECP_XPWd_B |
| 402761844U, // SQDECP_XPWd_D |
| 1140959348U, // SQDECP_XPWd_H |
| 536979572U, // SQDECP_XPWd_S |
| 335652980U, // SQDECP_XP_B |
| 402761844U, // SQDECP_XP_D |
| 1140959348U, // SQDECP_XP_H |
| 536979572U, // SQDECP_XP_S |
| 43124U, // SQDECP_ZP_D |
| 1209067636U, // SQDECP_ZP_H |
| 75892U, // SQDECP_ZP_S |
| 1073855198U, // SQDECW_XPiI |
| 2684467934U, // SQDECW_XPiWdI |
| 1073822430U, // SQDECW_ZPiI |
| 738387466U, // SQDMLALi16 |
| 738387466U, // SQDMLALi32 |
| 738383083U, // SQDMLALv1i32_indexed |
| 738388597U, // SQDMLALv1i64_indexed |
| 268554264U, // SQDMLALv2i32_indexed |
| 268554264U, // SQDMLALv2i32_v2i64 |
| 268563490U, // SQDMLALv4i16_indexed |
| 268563490U, // SQDMLALv4i16_v4i32 |
| 268553696U, // SQDMLALv4i32_indexed |
| 268553696U, // SQDMLALv4i32_v2i64 |
| 268562566U, // SQDMLALv8i16_indexed |
| 268562566U, // SQDMLALv8i16_v4i32 |
| 738387749U, // SQDMLSLi16 |
| 738387749U, // SQDMLSLi32 |
| 738383105U, // SQDMLSLv1i32_indexed |
| 738388619U, // SQDMLSLv1i64_indexed |
| 268554488U, // SQDMLSLv2i32_indexed |
| 268554488U, // SQDMLSLv2i32_v2i64 |
| 268563714U, // SQDMLSLv4i16_indexed |
| 268563714U, // SQDMLSLv4i16_v4i32 |
| 268553854U, // SQDMLSLv4i32_indexed |
| 268553854U, // SQDMLSLv4i32_v2i64 |
| 268562724U, // SQDMLSLv8i16_indexed |
| 268562724U, // SQDMLSLv8i16_v4i32 |
| 201434178U, // SQDMULHv1i16 |
| 201430216U, // SQDMULHv1i16_indexed |
| 201434178U, // SQDMULHv1i32 |
| 201435730U, // SQDMULHv1i32_indexed |
| 134311043U, // SQDMULHv2i32 |
| 134311043U, // SQDMULHv2i32_indexed |
| 134305653U, // SQDMULHv4i16 |
| 134305653U, // SQDMULHv4i16_indexed |
| 134312882U, // SQDMULHv4i32 |
| 134312882U, // SQDMULHv4i32_indexed |
| 134307491U, // SQDMULHv8i16 |
| 134307491U, // SQDMULHv8i16_indexed |
| 201434848U, // SQDMULLi16 |
| 201434848U, // SQDMULLi32 |
| 201430262U, // SQDMULLv1i32_indexed |
| 201435776U, // SQDMULLv1i64_indexed |
| 134303960U, // SQDMULLv2i32_indexed |
| 134303960U, // SQDMULLv2i32_v2i64 |
| 134313186U, // SQDMULLv4i16_indexed |
| 134313186U, // SQDMULLv4i16_v4i32 |
| 134303323U, // SQDMULLv4i32_indexed |
| 134303323U, // SQDMULLv4i32_v2i64 |
| 134312193U, // SQDMULLv8i16_indexed |
| 134312193U, // SQDMULLv8i16_v4i32 |
| 1073842779U, // SQINCB_XPiI |
| 2684455515U, // SQINCB_XPiWdI |
| 1073845158U, // SQINCD_XPiI |
| 2684457894U, // SQINCD_XPiWdI |
| 1073779622U, // SQINCD_ZPiI |
| 1073849210U, // SQINCH_XPiI |
| 2684461946U, // SQINCH_XPiWdI |
| 6349690U, // SQINCH_ZPiI |
| 335652996U, // SQINCP_XPWd_B |
| 402761860U, // SQINCP_XPWd_D |
| 1140959364U, // SQINCP_XPWd_H |
| 536979588U, // SQINCP_XPWd_S |
| 335652996U, // SQINCP_XP_B |
| 402761860U, // SQINCP_XP_D |
| 1140959364U, // SQINCP_XP_H |
| 536979588U, // SQINCP_XP_S |
| 43140U, // SQINCP_ZP_D |
| 1209067652U, // SQINCP_ZP_H |
| 75908U, // SQINCP_ZP_S |
| 1073855214U, // SQINCW_XPiI |
| 2684467950U, // SQINCW_XPiWdI |
| 1073822446U, // SQINCW_ZPiI |
| 134300693U, // SQNEGv16i8 |
| 201430182U, // SQNEGv1i16 |
| 201430182U, // SQNEGv1i32 |
| 201430182U, // SQNEGv1i64 |
| 201430182U, // SQNEGv1i8 |
| 134311020U, // SQNEGv2i32 |
| 134303693U, // SQNEGv2i64 |
| 134305630U, // SQNEGv4i16 |
| 134312847U, // SQNEGv4i32 |
| 134307468U, // SQNEGv8i16 |
| 134301549U, // SQNEGv8i8 |
| 738383036U, // SQRDMLAHi16_indexed |
| 738388550U, // SQRDMLAHi32_indexed |
| 738386694U, // SQRDMLAHv1i16 |
| 738386694U, // SQRDMLAHv1i32 |
| 268561526U, // SQRDMLAHv2i32 |
| 268561526U, // SQRDMLAHv2i32_indexed |
| 268556136U, // SQRDMLAHv4i16 |
| 268556136U, // SQRDMLAHv4i16_indexed |
| 268563365U, // SQRDMLAHv4i32 |
| 268563365U, // SQRDMLAHv4i32_indexed |
| 268557974U, // SQRDMLAHv8i16 |
| 268557974U, // SQRDMLAHv8i16_indexed |
| 738383071U, // SQRDMLSHi16_indexed |
| 738388585U, // SQRDMLSHi32_indexed |
| 738387274U, // SQRDMLSHv1i16 |
| 738387274U, // SQRDMLSHv1i32 |
| 268561564U, // SQRDMLSHv2i32 |
| 268561564U, // SQRDMLSHv2i32_indexed |
| 268556174U, // SQRDMLSHv4i16 |
| 268556174U, // SQRDMLSHv4i16_indexed |
| 268563403U, // SQRDMLSHv4i32 |
| 268563403U, // SQRDMLSHv4i32_indexed |
| 268558012U, // SQRDMLSHv8i16 |
| 268558012U, // SQRDMLSHv8i16_indexed |
| 201434187U, // SQRDMULHv1i16 |
| 201430227U, // SQRDMULHv1i16_indexed |
| 201434187U, // SQRDMULHv1i32 |
| 201435741U, // SQRDMULHv1i32_indexed |
| 134311055U, // SQRDMULHv2i32 |
| 134311055U, // SQRDMULHv2i32_indexed |
| 134305665U, // SQRDMULHv4i16 |
| 134305665U, // SQRDMULHv4i16_indexed |
| 134312894U, // SQRDMULHv4i32 |
| 134312894U, // SQRDMULHv4i32_indexed |
| 134307503U, // SQRDMULHv8i16 |
| 134307503U, // SQRDMULHv8i16_indexed |
| 134300764U, // SQRSHLv16i8 |
| 201434806U, // SQRSHLv1i16 |
| 201434806U, // SQRSHLv1i32 |
| 201434806U, // SQRSHLv1i64 |
| 201434806U, // SQRSHLv1i8 |
| 134311155U, // SQRSHLv2i32 |
| 134303880U, // SQRSHLv2i64 |
| 134305765U, // SQRSHLv4i16 |
| 134313106U, // SQRSHLv4i32 |
| 134307703U, // SQRSHLv8i16 |
| 134301613U, // SQRSHLv8i8 |
| 201435109U, // SQRSHRNb |
| 201435109U, // SQRSHRNh |
| 201435109U, // SQRSHRNs |
| 268550748U, // SQRSHRNv16i8_shift |
| 134311328U, // SQRSHRNv2i32_shift |
| 134305938U, // SQRSHRNv4i16_shift |
| 268562807U, // SQRSHRNv4i32_shift |
| 268557461U, // SQRSHRNv8i16_shift |
| 134301752U, // SQRSHRNv8i8_shift |
| 201435170U, // SQRSHRUNb |
| 201435170U, // SQRSHRUNh |
| 201435170U, // SQRSHRUNs |
| 268550824U, // SQRSHRUNv16i8_shift |
| 134311395U, // SQRSHRUNv2i32_shift |
| 134306005U, // SQRSHRUNv4i16_shift |
| 268562877U, // SQRSHRUNv4i32_shift |
| 268557531U, // SQRSHRUNv8i16_shift |
| 134301816U, // SQRSHRUNv8i8_shift |
| 201439700U, // SQSHLUb |
| 201439700U, // SQSHLUd |
| 201439700U, // SQSHLUh |
| 201439700U, // SQSHLUs |
| 134301118U, // SQSHLUv16i8_shift |
| 134311816U, // SQSHLUv2i32_shift |
| 134304427U, // SQSHLUv2i64_shift |
| 134306426U, // SQSHLUv4i16_shift |
| 134313747U, // SQSHLUv4i32_shift |
| 134308310U, // SQSHLUv8i16_shift |
| 134302056U, // SQSHLUv8i8_shift |
| 201434792U, // SQSHLb |
| 201434792U, // SQSHLd |
| 201434792U, // SQSHLh |
| 201434792U, // SQSHLs |
| 134300742U, // SQSHLv16i8 |
| 134300742U, // SQSHLv16i8_shift |
| 201434792U, // SQSHLv1i16 |
| 201434792U, // SQSHLv1i32 |
| 201434792U, // SQSHLv1i64 |
| 201434792U, // SQSHLv1i8 |
| 134311135U, // SQSHLv2i32 |
| 134311135U, // SQSHLv2i32_shift |
| 134303860U, // SQSHLv2i64 |
| 134303860U, // SQSHLv2i64_shift |
| 134305745U, // SQSHLv4i16 |
| 134305745U, // SQSHLv4i16_shift |
| 134313086U, // SQSHLv4i32 |
| 134313086U, // SQSHLv4i32_shift |
| 134307683U, // SQSHLv8i16 |
| 134307683U, // SQSHLv8i16_shift |
| 134301593U, // SQSHLv8i8 |
| 134301593U, // SQSHLv8i8_shift |
| 201435093U, // SQSHRNb |
| 201435093U, // SQSHRNh |
| 201435093U, // SQSHRNs |
| 268550722U, // SQSHRNv16i8_shift |
| 134311306U, // SQSHRNv2i32_shift |
| 134305916U, // SQSHRNv4i16_shift |
| 268562783U, // SQSHRNv4i32_shift |
| 268557437U, // SQSHRNv8i16_shift |
| 134301730U, // SQSHRNv8i8_shift |
| 201435161U, // SQSHRUNb |
| 201435161U, // SQSHRUNh |
| 201435161U, // SQSHRUNs |
| 268550810U, // SQSHRUNv16i8_shift |
| 134311383U, // SQSHRUNv2i32_shift |
| 134305993U, // SQSHRUNv4i16_shift |
| 268562864U, // SQSHRUNv4i32_shift |
| 268557518U, // SQSHRUNv8i16_shift |
| 134301804U, // SQSHRUNv8i8_shift |
| 335563956U, // SQSUB_ZI_B |
| 402689204U, // SQSUB_ZI_D |
| 471911604U, // SQSUB_ZI_H |
| 536939700U, // SQSUB_ZI_S |
| 335563956U, // SQSUB_ZZZ_B |
| 402689204U, // SQSUB_ZZZ_D |
| 471911604U, // SQSUB_ZZZ_H |
| 536939700U, // SQSUB_ZZZ_S |
| 134300491U, // SQSUBv16i8 |
| 201428148U, // SQSUBv1i16 |
| 201428148U, // SQSUBv1i32 |
| 201428148U, // SQSUBv1i64 |
| 201428148U, // SQSUBv1i8 |
| 134310777U, // SQSUBv2i32 |
| 134303541U, // SQSUBv2i64 |
| 134305410U, // SQSUBv4i16 |
| 134312594U, // SQSUBv4i32 |
| 134307248U, // SQSUBv8i16 |
| 134301405U, // SQSUBv8i8 |
| 268550786U, // SQXTNv16i8 |
| 201435147U, // SQXTNv1i16 |
| 201435147U, // SQXTNv1i32 |
| 201435147U, // SQXTNv1i8 |
| 134311363U, // SQXTNv2i32 |
| 134305973U, // SQXTNv4i16 |
| 268562842U, // SQXTNv4i32 |
| 268557496U, // SQXTNv8i16 |
| 134301784U, // SQXTNv8i8 |
| 268550839U, // SQXTUNv16i8 |
| 201435180U, // SQXTUNv1i16 |
| 201435180U, // SQXTUNv1i32 |
| 201435180U, // SQXTUNv1i8 |
| 134311408U, // SQXTUNv2i32 |
| 134306018U, // SQXTUNv4i16 |
| 268562891U, // SQXTUNv4i32 |
| 268557545U, // SQXTUNv8i16 |
| 134301829U, // SQXTUNv8i8 |
| 134300565U, // SRHADDv16i8 |
| 134310851U, // SRHADDv2i32 |
| 134305484U, // SRHADDv4i16 |
| 134312678U, // SRHADDv4i32 |
| 134307322U, // SRHADDv8i16 |
| 134301451U, // SRHADDv8i8 |
| 738387427U, // SRId |
| 268551219U, // SRIv16i8_shift |
| 268561603U, // SRIv2i32_shift |
| 268554216U, // SRIv2i64_shift |
| 268556213U, // SRIv4i16_shift |
| 268563442U, // SRIv4i32_shift |
| 268558051U, // SRIv8i16_shift |
| 268552072U, // SRIv8i8_shift |
| 134300788U, // SRSHLv16i8 |
| 201434822U, // SRSHLv1i64 |
| 134311177U, // SRSHLv2i32 |
| 134303902U, // SRSHLv2i64 |
| 134305787U, // SRSHLv4i16 |
| 134313128U, // SRSHLv4i32 |
| 134307725U, // SRSHLv8i16 |
| 134301635U, // SRSHLv8i8 |
| 201435494U, // SRSHRd |
| 134300951U, // SRSHRv16i8_shift |
| 134311586U, // SRSHRv2i32_shift |
| 134304213U, // SRSHRv2i64_shift |
| 134306196U, // SRSHRv4i16_shift |
| 134313517U, // SRSHRv4i32_shift |
| 134308080U, // SRSHRv8i16_shift |
| 134301906U, // SRSHRv8i8_shift |
| 738378022U, // SRSRAd |
| 268550923U, // SRSRAv16i8_shift |
| 268561195U, // SRSRAv2i32_shift |
| 268553979U, // SRSRAv2i64_shift |
| 268555828U, // SRSRAv4i16_shift |
| 268563012U, // SRSRAv4i32_shift |
| 268557666U, // SRSRAv8i16_shift |
| 268551843U, // SRSRAv8i8_shift |
| 134306840U, // SSHLLv16i8_shift |
| 134303940U, // SSHLLv2i32_shift |
| 134313166U, // SSHLLv4i16_shift |
| 134303301U, // SSHLLv4i32_shift |
| 134312171U, // SSHLLv8i16_shift |
| 134307763U, // SSHLLv8i8_shift |
| 134300810U, // SSHLv16i8 |
| 201434836U, // SSHLv1i64 |
| 134311197U, // SSHLv2i32 |
| 134303922U, // SSHLv2i64 |
| 134305807U, // SSHLv4i16 |
| 134313148U, // SSHLv4i32 |
| 134307745U, // SSHLv8i16 |
| 134301655U, // SSHLv8i8 |
| 201435508U, // SSHRd |
| 134300973U, // SSHRv16i8_shift |
| 134311606U, // SSHRv2i32_shift |
| 134304233U, // SSHRv2i64_shift |
| 134306216U, // SSHRv4i16_shift |
| 134313537U, // SSHRv4i32_shift |
| 134308100U, // SSHRv8i16_shift |
| 134301926U, // SSHRv8i8_shift |
| 738378036U, // SSRAd |
| 268550945U, // SSRAv16i8_shift |
| 268561215U, // SSRAv2i32_shift |
| 268553999U, // SSRAv2i64_shift |
| 268555848U, // SSRAv4i16_shift |
| 268563032U, // SSRAv4i32_shift |
| 268557686U, // SSRAv8i16_shift |
| 268551863U, // SSRAv8i8_shift |
| 742654413U, // SST1B_D |
| 1883505101U, // SST1B_D_IMM |
| 742654413U, // SST1B_D_SXTW |
| 742654413U, // SST1B_D_UXTW |
| 1615086029U, // SST1B_S_IMM |
| 742670797U, // SST1B_S_SXTW |
| 742670797U, // SST1B_S_UXTW |
| 742657449U, // SST1D |
| 1883508137U, // SST1D_IMM |
| 742657449U, // SST1D_SCALED |
| 742657449U, // SST1D_SXTW |
| 742657449U, // SST1D_SXTW_SCALED |
| 742657449U, // SST1D_UXTW |
| 742657449U, // SST1D_UXTW_SCALED |
| 742659433U, // SST1H_D |
| 1883510121U, // SST1H_D_IMM |
| 742659433U, // SST1H_D_SCALED |
| 742659433U, // SST1H_D_SXTW |
| 742659433U, // SST1H_D_SXTW_SCALED |
| 742659433U, // SST1H_D_UXTW |
| 742659433U, // SST1H_D_UXTW_SCALED |
| 1615091049U, // SST1H_S_IMM |
| 742675817U, // SST1H_S_SXTW |
| 742675817U, // SST1H_S_SXTW_SCALED |
| 742675817U, // SST1H_S_UXTW |
| 742675817U, // SST1H_S_UXTW_SCALED |
| 742668963U, // SST1W_D |
| 1883519651U, // SST1W_D_IMM |
| 742668963U, // SST1W_D_SCALED |
| 742668963U, // SST1W_D_SXTW |
| 742668963U, // SST1W_D_SXTW_SCALED |
| 742668963U, // SST1W_D_UXTW |
| 742668963U, // SST1W_D_UXTW_SCALED |
| 1615100579U, // SST1W_IMM |
| 742685347U, // SST1W_SXTW |
| 742685347U, // SST1W_SXTW_SCALED |
| 742685347U, // SST1W_UXTW |
| 742685347U, // SST1W_UXTW_SCALED |
| 134306774U, // SSUBLv16i8_v8i16 |
| 134303800U, // SSUBLv2i32_v2i64 |
| 134313026U, // SSUBLv4i16_v4i32 |
| 134303235U, // SSUBLv4i32_v2i64 |
| 134312105U, // SSUBLv8i16_v4i32 |
| 134307623U, // SSUBLv8i8_v8i16 |
| 134307079U, // SSUBWv16i8_v8i16 |
| 134304500U, // SSUBWv2i32_v2i64 |
| 134313935U, // SSUBWv4i16_v4i32 |
| 134303420U, // SSUBWv4i32_v2i64 |
| 134312425U, // SSUBWv8i16_v4i32 |
| 134308498U, // SSUBWv8i8_v8i16 |
| 742703565U, // ST1B |
| 742654413U, // ST1B_D |
| 742654413U, // ST1B_D_IMM |
| 742719949U, // ST1B_H |
| 742719949U, // ST1B_H_IMM |
| 742703565U, // ST1B_IMM |
| 742670797U, // ST1B_S |
| 742670797U, // ST1B_S_IMM |
| 742657449U, // ST1D |
| 742657449U, // ST1D_IMM |
| 344095U, // ST1Fourv16b |
| 21331999U, // ST1Fourv16b_POST |
| 376863U, // ST1Fourv1d |
| 22413343U, // ST1Fourv1d_POST |
| 409631U, // ST1Fourv2d |
| 21397535U, // ST1Fourv2d_POST |
| 442399U, // ST1Fourv2s |
| 22478879U, // ST1Fourv2s_POST |
| 475167U, // ST1Fourv4h |
| 22511647U, // ST1Fourv4h_POST |
| 507935U, // ST1Fourv4s |
| 21495839U, // ST1Fourv4s_POST |
| 540703U, // ST1Fourv8b |
| 22577183U, // ST1Fourv8b_POST |
| 573471U, // ST1Fourv8h |
| 21561375U, // ST1Fourv8h_POST |
| 742724969U, // ST1H |
| 742659433U, // ST1H_D |
| 742659433U, // ST1H_D_IMM |
| 742724969U, // ST1H_IMM |
| 742675817U, // ST1H_S |
| 742675817U, // ST1H_S_IMM |
| 344095U, // ST1Onev16b |
| 23429151U, // ST1Onev16b_POST |
| 376863U, // ST1Onev1d |
| 24510495U, // ST1Onev1d_POST |
| 409631U, // ST1Onev2d |
| 23494687U, // ST1Onev2d_POST |
| 442399U, // ST1Onev2s |
| 24576031U, // ST1Onev2s_POST |
| 475167U, // ST1Onev4h |
| 24608799U, // ST1Onev4h_POST |
| 507935U, // ST1Onev4s |
| 23592991U, // ST1Onev4s_POST |
| 540703U, // ST1Onev8b |
| 24674335U, // ST1Onev8b_POST |
| 573471U, // ST1Onev8h |
| 23658527U, // ST1Onev8h_POST |
| 344095U, // ST1Threev16b |
| 28672031U, // ST1Threev16b_POST |
| 376863U, // ST1Threev1d |
| 29753375U, // ST1Threev1d_POST |
| 409631U, // ST1Threev2d |
| 28737567U, // ST1Threev2d_POST |
| 442399U, // ST1Threev2s |
| 29818911U, // ST1Threev2s_POST |
| 475167U, // ST1Threev4h |
| 29851679U, // ST1Threev4h_POST |
| 507935U, // ST1Threev4s |
| 28835871U, // ST1Threev4s_POST |
| 540703U, // ST1Threev8b |
| 29917215U, // ST1Threev8b_POST |
| 573471U, // ST1Threev8h |
| 28901407U, // ST1Threev8h_POST |
| 344095U, // ST1Twov16b |
| 22380575U, // ST1Twov16b_POST |
| 376863U, // ST1Twov1d |
| 23461919U, // ST1Twov1d_POST |
| 409631U, // ST1Twov2d |
| 22446111U, // ST1Twov2d_POST |
| 442399U, // ST1Twov2s |
| 23527455U, // ST1Twov2s_POST |
| 475167U, // ST1Twov4h |
| 23560223U, // ST1Twov4h_POST |
| 507935U, // ST1Twov4s |
| 22544415U, // ST1Twov4s_POST |
| 540703U, // ST1Twov8b |
| 23625759U, // ST1Twov8b_POST |
| 573471U, // ST1Twov8h |
| 22609951U, // ST1Twov8h_POST |
| 742685347U, // ST1W |
| 742668963U, // ST1W_D |
| 742668963U, // ST1W_D_IMM |
| 742685347U, // ST1W_IMM |
| 819231U, // ST1i16 |
| 2801352735U, // ST1i16_POST |
| 835615U, // ST1i32 |
| 2868494367U, // ST1i32_POST |
| 851999U, // ST1i64 |
| 2935635999U, // ST1i64_POST |
| 868383U, // ST1i8 |
| 3002777631U, // ST1i8_POST |
| 742703585U, // ST2B |
| 742703585U, // ST2B_IMM |
| 742658891U, // ST2D |
| 742658891U, // ST2D_IMM |
| 742725043U, // ST2H |
| 742725043U, // ST2H_IMM |
| 344162U, // ST2Twov16b |
| 22380642U, // ST2Twov16b_POST |
| 409698U, // ST2Twov2d |
| 22446178U, // ST2Twov2d_POST |
| 442466U, // ST2Twov2s |
| 23527522U, // ST2Twov2s_POST |
| 475234U, // ST2Twov4h |
| 23560290U, // ST2Twov4h_POST |
| 508002U, // ST2Twov4s |
| 22544482U, // ST2Twov4s_POST |
| 540770U, // ST2Twov8b |
| 23625826U, // ST2Twov8b_POST |
| 573538U, // ST2Twov8h |
| 22610018U, // ST2Twov8h_POST |
| 742685367U, // ST2W |
| 742685367U, // ST2W_IMM |
| 819298U, // ST2i16 |
| 2868461666U, // ST2i16_POST |
| 835682U, // ST2i32 |
| 2935603298U, // ST2i32_POST |
| 852066U, // ST2i64 |
| 3069853794U, // ST2i64_POST |
| 868450U, // ST2i8 |
| 2801451106U, // ST2i8_POST |
| 742703597U, // ST3B |
| 742703597U, // ST3B_IMM |
| 742658903U, // ST3D |
| 742658903U, // ST3D_IMM |
| 742725055U, // ST3H |
| 742725055U, // ST3H_IMM |
| 344179U, // ST3Threev16b |
| 28672115U, // ST3Threev16b_POST |
| 409715U, // ST3Threev2d |
| 28737651U, // ST3Threev2d_POST |
| 442483U, // ST3Threev2s |
| 29818995U, // ST3Threev2s_POST |
| 475251U, // ST3Threev4h |
| 29851763U, // ST3Threev4h_POST |
| 508019U, // ST3Threev4s |
| 28835955U, // ST3Threev4s_POST |
| 540787U, // ST3Threev8b |
| 29917299U, // ST3Threev8b_POST |
| 573555U, // ST3Threev8h |
| 28901491U, // ST3Threev8h_POST |
| 742685379U, // ST3W |
| 742685379U, // ST3W_IMM |
| 819315U, // ST3i16 |
| 3136897139U, // ST3i16_POST |
| 835699U, // ST3i32 |
| 3204038771U, // ST3i32_POST |
| 852083U, // ST3i64 |
| 3271180403U, // ST3i64_POST |
| 868467U, // ST3i8 |
| 3338322035U, // ST3i8_POST |
| 742703609U, // ST4B |
| 742703609U, // ST4B_IMM |
| 742658915U, // ST4D |
| 742658915U, // ST4D_IMM |
| 344189U, // ST4Fourv16b |
| 21332093U, // ST4Fourv16b_POST |
| 409725U, // ST4Fourv2d |
| 21397629U, // ST4Fourv2d_POST |
| 442493U, // ST4Fourv2s |
| 22478973U, // ST4Fourv2s_POST |
| 475261U, // ST4Fourv4h |
| 22511741U, // ST4Fourv4h_POST |
| 508029U, // ST4Fourv4s |
| 21495933U, // ST4Fourv4s_POST |
| 540797U, // ST4Fourv8b |
| 22577277U, // ST4Fourv8b_POST |
| 573565U, // ST4Fourv8h |
| 21561469U, // ST4Fourv8h_POST |
| 742726527U, // ST4H |
| 742726527U, // ST4H_IMM |
| 742685391U, // ST4W |
| 742685391U, // ST4W_IMM |
| 819325U, // ST4i16 |
| 2935570557U, // ST4i16_POST |
| 835709U, // ST4i32 |
| 3069821053U, // ST4i32_POST |
| 852093U, // ST4i64 |
| 3405398141U, // ST4i64_POST |
| 868477U, // ST4i8 |
| 2868559997U, // ST4i8_POST |
| 205622185U, // STLLRB |
| 205628603U, // STLLRH |
| 205629836U, // STLLRW |
| 205629836U, // STLLRX |
| 205622193U, // STLRB |
| 205628611U, // STLRH |
| 205629849U, // STLRW |
| 205629849U, // STLRX |
| 205622243U, // STLURBi |
| 205628661U, // STLURHi |
| 205629946U, // STLURWi |
| 205629946U, // STLURXi |
| 201435369U, // STLXPW |
| 201435369U, // STLXPX |
| 201427978U, // STLXRB |
| 201434396U, // STLXRH |
| 201435697U, // STLXRW |
| 201435697U, // STLXRX |
| 201435308U, // STNPDi |
| 201435308U, // STNPQi |
| 201435308U, // STNPSi |
| 201435308U, // STNPWi |
| 201435308U, // STNPXi |
| 742703557U, // STNT1B_ZRI |
| 742703557U, // STNT1B_ZRR |
| 742657441U, // STNT1D_ZRI |
| 742657441U, // STNT1D_ZRR |
| 742724961U, // STNT1H_ZRI |
| 742724961U, // STNT1H_ZRR |
| 742685339U, // STNT1W_ZRI |
| 742685339U, // STNT1W_ZRR |
| 201435340U, // STPDi |
| 738388172U, // STPDpost |
| 738388172U, // STPDpre |
| 201435340U, // STPQi |
| 738388172U, // STPQpost |
| 738388172U, // STPQpre |
| 201435340U, // STPSi |
| 738388172U, // STPSpost |
| 738388172U, // STPSpre |
| 201435340U, // STPWi |
| 738388172U, // STPWpost |
| 738388172U, // STPWpre |
| 201435340U, // STPXi |
| 738388172U, // STPXpost |
| 738388172U, // STPXpre |
| 742575055U, // STRBBpost |
| 742575055U, // STRBBpre |
| 205622223U, // STRBBroW |
| 205622223U, // STRBBroX |
| 205622223U, // STRBBui |
| 742582755U, // STRBpost |
| 742582755U, // STRBpre |
| 205629923U, // STRBroW |
| 205629923U, // STRBroX |
| 205629923U, // STRBui |
| 742582755U, // STRDpost |
| 742582755U, // STRDpre |
| 205629923U, // STRDroW |
| 205629923U, // STRDroX |
| 205629923U, // STRDui |
| 742581473U, // STRHHpost |
| 742581473U, // STRHHpre |
| 205628641U, // STRHHroW |
| 205628641U, // STRHHroX |
| 205628641U, // STRHHui |
| 742582755U, // STRHpost |
| 742582755U, // STRHpre |
| 205629923U, // STRHroW |
| 205629923U, // STRHroX |
| 205629923U, // STRHui |
| 742582755U, // STRQpost |
| 742582755U, // STRQpre |
| 205629923U, // STRQroW |
| 205629923U, // STRQroX |
| 205629923U, // STRQui |
| 742582755U, // STRSpost |
| 742582755U, // STRSpre |
| 205629923U, // STRSroW |
| 205629923U, // STRSroX |
| 205629923U, // STRSui |
| 742582755U, // STRWpost |
| 742582755U, // STRWpre |
| 205629923U, // STRWroW |
| 205629923U, // STRWroX |
| 205629923U, // STRWui |
| 742582755U, // STRXpost |
| 742582755U, // STRXpre |
| 205629923U, // STRXroW |
| 205629923U, // STRXroX |
| 205629923U, // STRXui |
| 206268899U, // STR_PXI |
| 206268899U, // STR_ZXI |
| 205622229U, // STTRBi |
| 205628647U, // STTRHi |
| 205629928U, // STTRWi |
| 205629928U, // STTRXi |
| 205622260U, // STURBBi |
| 205629961U, // STURBi |
| 205629961U, // STURDi |
| 205628678U, // STURHHi |
| 205629961U, // STURHi |
| 205629961U, // STURQi |
| 205629961U, // STURSi |
| 205629961U, // STURWi |
| 205629961U, // STURXi |
| 201435376U, // STXPW |
| 201435376U, // STXPX |
| 201427986U, // STXRB |
| 201434404U, // STXRH |
| 201435704U, // STXRW |
| 201435704U, // STXRX |
| 134311258U, // SUBHNv2i64_v2i32 |
| 268562760U, // SUBHNv2i64_v4i32 |
| 134305868U, // SUBHNv4i32_v4i16 |
| 268557414U, // SUBHNv4i32_v8i16 |
| 268550697U, // SUBHNv8i16_v16i8 |
| 134301691U, // SUBHNv8i16_v8i8 |
| 335571272U, // SUBR_ZI_B |
| 402696520U, // SUBR_ZI_D |
| 471918920U, // SUBR_ZI_H |
| 536947016U, // SUBR_ZI_S |
| 604006728U, // SUBR_ZPmZ_B |
| 604023112U, // SUBR_ZPmZ_D |
| 70314312U, // SUBR_ZPmZ_H |
| 604055880U, // SUBR_ZPmZ_S |
| 201439346U, // SUBSWri |
| 0U, // SUBSWrr |
| 201439346U, // SUBSWrs |
| 201439346U, // SUBSWrx |
| 201439346U, // SUBSXri |
| 0U, // SUBSXrr |
| 201439346U, // SUBSXrs |
| 201439346U, // SUBSXrx |
| 201439346U, // SUBSXrx64 |
| 201428128U, // SUBWri |
| 0U, // SUBWrr |
| 201428128U, // SUBWrs |
| 201428128U, // SUBWrx |
| 201428128U, // SUBXri |
| 0U, // SUBXrr |
| 201428128U, // SUBXrs |
| 201428128U, // SUBXrx |
| 201428128U, // SUBXrx64 |
| 335563936U, // SUB_ZI_B |
| 402689184U, // SUB_ZI_D |
| 471911584U, // SUB_ZI_H |
| 536939680U, // SUB_ZI_S |
| 603999392U, // SUB_ZPmZ_B |
| 604015776U, // SUB_ZPmZ_D |
| 70306976U, // SUB_ZPmZ_H |
| 604048544U, // SUB_ZPmZ_S |
| 335563936U, // SUB_ZZZ_B |
| 402689184U, // SUB_ZZZ_D |
| 471911584U, // SUB_ZZZ_H |
| 536939680U, // SUB_ZZZ_S |
| 134300471U, // SUBv16i8 |
| 201428128U, // SUBv1i64 |
| 134310749U, // SUBv2i32 |
| 134303533U, // SUBv2i64 |
| 134305382U, // SUBv4i16 |
| 134312566U, // SUBv4i32 |
| 134307220U, // SUBv8i16 |
| 134301387U, // SUBv8i8 |
| 536913343U, // SUNPKHI_ZZ_D |
| 48293311U, // SUNPKHI_ZZ_H |
| 1140925887U, // SUNPKHI_ZZ_S |
| 536914004U, // SUNPKLO_ZZ_D |
| 48293972U, // SUNPKLO_ZZ_H |
| 1140926548U, // SUNPKLO_ZZ_S |
| 268551119U, // SUQADDv16i8 |
| 738382817U, // SUQADDv1i16 |
| 738382817U, // SUQADDv1i32 |
| 738382817U, // SUQADDv1i64 |
| 738382817U, // SUQADDv1i8 |
| 268561400U, // SUQADDv2i32 |
| 268554096U, // SUQADDv2i64 |
| 268556033U, // SUQADDv4i16 |
| 268563227U, // SUQADDv4i32 |
| 268557871U, // SUQADDv8i16 |
| 268552000U, // SUQADDv8i8 |
| 150810U, // SVC |
| 2080557553U, // SWPAB |
| 2080564004U, // SWPAH |
| 2080557755U, // SWPALB |
| 2080564152U, // SWPALH |
| 2080564783U, // SWPALW |
| 2080564783U, // SWPALX |
| 2080555273U, // SWPAW |
| 2080555273U, // SWPAX |
| 2080557943U, // SWPB |
| 2080564361U, // SWPH |
| 2080557852U, // SWPLB |
| 2080564249U, // SWPLH |
| 2080565001U, // SWPLW |
| 2080565001U, // SWPLX |
| 2080565463U, // SWPW |
| 2080565463U, // SWPX |
| 35987U, // SXTB_ZPmZ_D |
| 68209811U, // SXTB_ZPmZ_H |
| 68755U, // SXTB_ZPmZ_S |
| 42379U, // SXTH_ZPmZ_D |
| 75147U, // SXTH_ZPmZ_S |
| 47970U, // SXTW_ZPmZ_D |
| 201434926U, // SYSLxt |
| 3422664995U, // SYSxt |
| 3489687148U, // TBL_ZZZ_B |
| 3556812396U, // TBL_ZZZ_D |
| 50390636U, // TBL_ZZZ_H |
| 3623954028U, // TBL_ZZZ_S |
| 3742459500U, // TBLv16i8Four |
| 3742459500U, // TBLv16i8One |
| 3742459500U, // TBLv16i8Three |
| 3742459500U, // TBLv16i8Two |
| 3743508076U, // TBLv8i8Four |
| 3743508076U, // TBLv8i8One |
| 3743508076U, // TBLv8i8Three |
| 3743508076U, // TBLv8i8Two |
| 201440263U, // TBNZW |
| 201440263U, // TBNZX |
| 3809606546U, // TBXv16i8Four |
| 3809606546U, // TBXv16i8One |
| 3809606546U, // TBXv16i8Three |
| 3809606546U, // TBXv16i8Two |
| 3810655122U, // TBXv8i8Four |
| 3810655122U, // TBXv8i8One |
| 3810655122U, // TBXv8i8Three |
| 3810655122U, // TBXv8i8Two |
| 201440247U, // TBZW |
| 201440247U, // TBZX |
| 0U, // TCRETURNdi |
| 0U, // TCRETURNri |
| 5356571U, // TLSDESCCALL |
| 0U, // TLSDESC_CALLSEQ |
| 335560710U, // TRN1_PPP_B |
| 402685958U, // TRN1_PPP_D |
| 471908358U, // TRN1_PPP_H |
| 536936454U, // TRN1_PPP_S |
| 335560710U, // TRN1_ZZZ_B |
| 402685958U, // TRN1_ZZZ_D |
| 471908358U, // TRN1_ZZZ_H |
| 536936454U, // TRN1_ZZZ_S |
| 134300159U, // TRN1v16i8 |
| 134310598U, // TRN1v2i32 |
| 134303151U, // TRN1v2i64 |
| 134305221U, // TRN1v4i16 |
| 134311982U, // TRN1v4i32 |
| 134306693U, // TRN1v8i16 |
| 134301237U, // TRN1v8i8 |
| 335560760U, // TRN2_PPP_B |
| 402686008U, // TRN2_PPP_D |
| 471908408U, // TRN2_PPP_H |
| 536936504U, // TRN2_PPP_S |
| 335560760U, // TRN2_ZZZ_B |
| 402686008U, // TRN2_ZZZ_D |
| 471908408U, // TRN2_ZZZ_H |
| 536936504U, // TRN2_ZZZ_S |
| 134300280U, // TRN2v16i8 |
| 134310625U, // TRN2v2i32 |
| 134303393U, // TRN2v2i64 |
| 134305258U, // TRN2v4i16 |
| 134312337U, // TRN2v4i32 |
| 134306991U, // TRN2v8i16 |
| 134301274U, // TRN2v8i8 |
| 232568U, // TSB |
| 268557237U, // UABALv16i8_v8i16 |
| 268554254U, // UABALv2i32_v2i64 |
| 268563480U, // UABALv4i16_v4i32 |
| 268553685U, // UABALv4i32_v2i64 |
| 268562555U, // UABALv8i16_v4i32 |
| 268558089U, // UABALv8i8_v8i16 |
| 268550904U, // UABAv16i8 |
| 268561167U, // UABAv2i32 |
| 268555800U, // UABAv4i16 |
| 268562984U, // UABAv4i32 |
| 268557638U, // UABAv8i16 |
| 268551826U, // UABAv8i8 |
| 134306807U, // UABDLv16i8_v8i16 |
| 134303830U, // UABDLv2i32_v2i64 |
| 134313056U, // UABDLv4i16_v4i32 |
| 134303268U, // UABDLv4i32_v2i64 |
| 134312138U, // UABDLv8i16_v4i32 |
| 134307653U, // UABDLv8i8_v8i16 |
| 604001161U, // UABD_ZPmZ_B |
| 604017545U, // UABD_ZPmZ_D |
| 70308745U, // UABD_ZPmZ_H |
| 604050313U, // UABD_ZPmZ_S |
| 134300555U, // UABDv16i8 |
| 134310823U, // UABDv2i32 |
| 134305456U, // UABDv4i16 |
| 134312650U, // UABDv4i32 |
| 134307294U, // UABDv8i16 |
| 134301442U, // UABDv8i8 |
| 268558430U, // UADALPv16i8_v8i16 |
| 268553570U, // UADALPv2i32_v1i64 |
| 268561936U, // UADALPv4i16_v2i32 |
| 268554603U, // UADALPv4i32_v2i64 |
| 268563867U, // UADALPv8i16_v4i32 |
| 268556546U, // UADALPv8i8_v4i16 |
| 134307956U, // UADDLPv16i8_v8i16 |
| 134303096U, // UADDLPv2i32_v1i64 |
| 134311462U, // UADDLPv4i16_v2i32 |
| 134304129U, // UADDLPv4i32_v2i64 |
| 134313393U, // UADDLPv8i16_v4i32 |
| 134306072U, // UADDLPv8i8_v4i16 |
| 134317536U, // UADDLVv16i8v |
| 134322894U, // UADDLVv4i16v |
| 134330215U, // UADDLVv4i32v |
| 134324778U, // UADDLVv8i16v |
| 134318471U, // UADDLVv8i8v |
| 134306829U, // UADDLv16i8_v8i16 |
| 134303850U, // UADDLv2i32_v2i64 |
| 134313076U, // UADDLv4i16_v4i32 |
| 134303290U, // UADDLv4i32_v2i64 |
| 134312160U, // UADDLv8i16_v4i32 |
| 134307673U, // UADDLv8i8_v8i16 |
| 604092938U, // UADDV_VPZ_B |
| 604092938U, // UADDV_VPZ_D |
| 604092938U, // UADDV_VPZ_H |
| 604092938U, // UADDV_VPZ_S |
| 134307112U, // UADDWv16i8_v8i16 |
| 134304530U, // UADDWv2i32_v2i64 |
| 134313965U, // UADDWv4i16_v4i32 |
| 134303453U, // UADDWv4i32_v2i64 |
| 134312458U, // UADDWv8i16_v4i32 |
| 134308528U, // UADDWv8i8_v8i16 |
| 201435005U, // UBFMWri |
| 201435005U, // UBFMXri |
| 201430169U, // UCVTFSWDri |
| 201430169U, // UCVTFSWHri |
| 201430169U, // UCVTFSWSri |
| 201430169U, // UCVTFSXDri |
| 201430169U, // UCVTFSXHri |
| 201430169U, // UCVTFSXSri |
| 201430169U, // UCVTFUWDri |
| 201430169U, // UCVTFUWHri |
| 201430169U, // UCVTFUWSri |
| 201430169U, // UCVTFUXDri |
| 201430169U, // UCVTFUXHri |
| 201430169U, // UCVTFUXSri |
| 38041U, // UCVTF_ZPmZ_DtoD |
| 68211865U, // UCVTF_ZPmZ_DtoH |
| 70809U, // UCVTF_ZPmZ_DtoS |
| 68211865U, // UCVTF_ZPmZ_HtoH |
| 38041U, // UCVTF_ZPmZ_StoD |
| 68211865U, // UCVTF_ZPmZ_StoH |
| 70809U, // UCVTF_ZPmZ_StoS |
| 201430169U, // UCVTFd |
| 201430169U, // UCVTFh |
| 201430169U, // UCVTFs |
| 201430169U, // UCVTFv1i16 |
| 201430169U, // UCVTFv1i32 |
| 201430169U, // UCVTFv1i64 |
| 134311001U, // UCVTFv2f32 |
| 134303674U, // UCVTFv2f64 |
| 134311001U, // UCVTFv2i32_shift |
| 134303674U, // UCVTFv2i64_shift |
| 134305611U, // UCVTFv4f16 |
| 134312828U, // UCVTFv4f32 |
| 134305611U, // UCVTFv4i16_shift |
| 134312828U, // UCVTFv4i32_shift |
| 134307449U, // UCVTFv8f16 |
| 134307449U, // UCVTFv8i16_shift |
| 604023325U, // UDIVR_ZPmZ_D |
| 604056093U, // UDIVR_ZPmZ_S |
| 201439784U, // UDIVWr |
| 201439784U, // UDIVXr |
| 604027432U, // UDIV_ZPmZ_D |
| 604060200U, // UDIV_ZPmZ_S |
| 2550184342U, // UDOT_ZZZI_D |
| 2617325974U, // UDOT_ZZZI_S |
| 2550184342U, // UDOT_ZZZ_D |
| 2617325974U, // UDOT_ZZZ_S |
| 268564886U, // UDOTlanev16i8 |
| 268564886U, // UDOTlanev8i8 |
| 15870U, // UDOTv16i8 |
| 15870U, // UDOTv8i8 |
| 134300600U, // UHADDv16i8 |
| 134310883U, // UHADDv2i32 |
| 134305516U, // UHADDv4i16 |
| 134312710U, // UHADDv4i32 |
| 134307354U, // UHADDv8i16 |
| 134301483U, // UHADDv8i8 |
| 134300480U, // UHSUBv16i8 |
| 134310767U, // UHSUBv2i32 |
| 134305400U, // UHSUBv4i16 |
| 134312584U, // UHSUBv4i32 |
| 134307238U, // UHSUBv8i16 |
| 134301395U, // UHSUBv8i8 |
| 201434769U, // UMADDLrrr |
| 134300930U, // UMAXPv16i8 |
| 134311566U, // UMAXPv2i32 |
| 134306176U, // UMAXPv4i16 |
| 134313497U, // UMAXPv4i32 |
| 134308060U, // UMAXPv8i16 |
| 134301887U, // UMAXPv8i8 |
| 604093046U, // UMAXV_VPZ_B |
| 604093046U, // UMAXV_VPZ_D |
| 604093046U, // UMAXV_VPZ_H |
| 604093046U, // UMAXV_VPZ_S |
| 134317581U, // UMAXVv16i8v |
| 134322988U, // UMAXVv4i16v |
| 134330309U, // UMAXVv4i32v |
| 134324872U, // UMAXVv8i16v |
| 134318512U, // UMAXVv8i8v |
| 335575948U, // UMAX_ZI_B |
| 402701196U, // UMAX_ZI_D |
| 471923596U, // UMAX_ZI_H |
| 536951692U, // UMAX_ZI_S |
| 604011404U, // UMAX_ZPmZ_B |
| 604027788U, // UMAX_ZPmZ_D |
| 70318988U, // UMAX_ZPmZ_H |
| 604060556U, // UMAX_ZPmZ_S |
| 134301218U, // UMAXv16i8 |
| 134311907U, // UMAXv2i32 |
| 134306632U, // UMAXv4i16 |
| 134313993U, // UMAXv4i32 |
| 134308556U, // UMAXv8i16 |
| 134302147U, // UMAXv8i8 |
| 134300899U, // UMINPv16i8 |
| 134311517U, // UMINPv2i32 |
| 134306127U, // UMINPv4i16 |
| 134313448U, // UMINPv4i32 |
| 134308011U, // UMINPv8i16 |
| 134301859U, // UMINPv8i8 |
| 604093006U, // UMINV_VPZ_B |
| 604093006U, // UMINV_VPZ_D |
| 604093006U, // UMINV_VPZ_H |
| 604093006U, // UMINV_VPZ_S |
| 134317559U, // UMINVv16i8v |
| 134322949U, // UMINVv4i16v |
| 134330270U, // UMINVv4i32v |
| 134324833U, // UMINVv8i16v |
| 134318492U, // UMINVv8i8v |
| 335570878U, // UMIN_ZI_B |
| 402696126U, // UMIN_ZI_D |
| 471918526U, // UMIN_ZI_H |
| 536946622U, // UMIN_ZI_S |
| 604006334U, // UMIN_ZPmZ_B |
| 604022718U, // UMIN_ZPmZ_D |
| 70313918U, // UMIN_ZPmZ_H |
| 604055486U, // UMIN_ZPmZ_S |
| 134300859U, // UMINv16i8 |
| 134311297U, // UMINv2i32 |
| 134305907U, // UMINv4i16 |
| 134313320U, // UMINv4i32 |
| 134307893U, // UMINv8i16 |
| 134301721U, // UMINv8i8 |
| 268557259U, // UMLALv16i8_v8i16 |
| 268554286U, // UMLALv2i32_indexed |
| 268554286U, // UMLALv2i32_v2i64 |
| 268563512U, // UMLALv4i16_indexed |
| 268563512U, // UMLALv4i16_v4i32 |
| 268553720U, // UMLALv4i32_indexed |
| 268553720U, // UMLALv4i32_v2i64 |
| 268562590U, // UMLALv8i16_indexed |
| 268562590U, // UMLALv8i16_v4i32 |
| 268558109U, // UMLALv8i8_v8i16 |
| 268557402U, // UMLSLv16i8_v8i16 |
| 268554510U, // UMLSLv2i32_indexed |
| 268554510U, // UMLSLv2i32_v2i64 |
| 268563736U, // UMLSLv4i16_indexed |
| 268563736U, // UMLSLv4i16_v4i32 |
| 268553878U, // UMLSLv4i32_indexed |
| 268553878U, // UMLSLv4i32_v2i64 |
| 268562748U, // UMLSLv8i16_indexed |
| 268562748U, // UMLSLv8i16_v4i32 |
| 268558319U, // UMLSLv8i8_v8i16 |
| 134321451U, // UMOVvi16 |
| 134326965U, // UMOVvi32 |
| 134319430U, // UMOVvi64 |
| 134316447U, // UMOVvi8 |
| 201434745U, // UMSUBLrrr |
| 604005468U, // UMULH_ZPmZ_B |
| 604021852U, // UMULH_ZPmZ_D |
| 70313052U, // UMULH_ZPmZ_H |
| 604054620U, // UMULH_ZPmZ_S |
| 201434204U, // UMULHrr |
| 134306884U, // UMULLv16i8_v8i16 |
| 134303982U, // UMULLv2i32_indexed |
| 134303982U, // UMULLv2i32_v2i64 |
| 134313208U, // UMULLv4i16_indexed |
| 134313208U, // UMULLv4i16_v4i32 |
| 134303347U, // UMULLv4i32_indexed |
| 134303347U, // UMULLv4i32_v2i64 |
| 134312217U, // UMULLv8i16_indexed |
| 134312217U, // UMULLv8i16_v4i32 |
| 134307803U, // UMULLv8i8_v8i16 |
| 335565794U, // UQADD_ZI_B |
| 402691042U, // UQADD_ZI_D |
| 471913442U, // UQADD_ZI_H |
| 536941538U, // UQADD_ZI_S |
| 335565794U, // UQADD_ZZZ_B |
| 402691042U, // UQADD_ZZZ_D |
| 471913442U, // UQADD_ZZZ_H |
| 536941538U, // UQADD_ZZZ_S |
| 134300624U, // UQADDv16i8 |
| 201429986U, // UQADDv1i16 |
| 201429986U, // UQADDv1i32 |
| 201429986U, // UQADDv1i64 |
| 201429986U, // UQADDv1i8 |
| 134310905U, // UQADDv2i32 |
| 134303601U, // UQADDv2i64 |
| 134305538U, // UQADDv4i16 |
| 134312732U, // UQADDv4i32 |
| 134307376U, // UQADDv8i16 |
| 134301505U, // UQADDv8i8 |
| 1073842771U, // UQDECB_WPiI |
| 1073842771U, // UQDECB_XPiI |
| 1073845150U, // UQDECD_WPiI |
| 1073845150U, // UQDECD_XPiI |
| 1073779614U, // UQDECD_ZPiI |
| 1073849202U, // UQDECH_WPiI |
| 1073849202U, // UQDECH_XPiI |
| 6349682U, // UQDECH_ZPiI |
| 335652988U, // UQDECP_WP_B |
| 402761852U, // UQDECP_WP_D |
| 1140959356U, // UQDECP_WP_H |
| 536979580U, // UQDECP_WP_S |
| 335652988U, // UQDECP_XP_B |
| 402761852U, // UQDECP_XP_D |
| 1140959356U, // UQDECP_XP_H |
| 536979580U, // UQDECP_XP_S |
| 43132U, // UQDECP_ZP_D |
| 1209067644U, // UQDECP_ZP_H |
| 75900U, // UQDECP_ZP_S |
| 1073855206U, // UQDECW_WPiI |
| 1073855206U, // UQDECW_XPiI |
| 1073822438U, // UQDECW_ZPiI |
| 1073842787U, // UQINCB_WPiI |
| 1073842787U, // UQINCB_XPiI |
| 1073845166U, // UQINCD_WPiI |
| 1073845166U, // UQINCD_XPiI |
| 1073779630U, // UQINCD_ZPiI |
| 1073849218U, // UQINCH_WPiI |
| 1073849218U, // UQINCH_XPiI |
| 6349698U, // UQINCH_ZPiI |
| 335653004U, // UQINCP_WP_B |
| 402761868U, // UQINCP_WP_D |
| 1140959372U, // UQINCP_WP_H |
| 536979596U, // UQINCP_WP_S |
| 335653004U, // UQINCP_XP_B |
| 402761868U, // UQINCP_XP_D |
| 1140959372U, // UQINCP_XP_H |
| 536979596U, // UQINCP_XP_S |
| 43148U, // UQINCP_ZP_D |
| 1209067660U, // UQINCP_ZP_H |
| 75916U, // UQINCP_ZP_S |
| 1073855222U, // UQINCW_WPiI |
| 1073855222U, // UQINCW_XPiI |
| 1073822454U, // UQINCW_ZPiI |
| 134300776U, // UQRSHLv16i8 |
| 201434814U, // UQRSHLv1i16 |
| 201434814U, // UQRSHLv1i32 |
| 201434814U, // UQRSHLv1i64 |
| 201434814U, // UQRSHLv1i8 |
| 134311166U, // UQRSHLv2i32 |
| 134303891U, // UQRSHLv2i64 |
| 134305776U, // UQRSHLv4i16 |
| 134313117U, // UQRSHLv4i32 |
| 134307714U, // UQRSHLv8i16 |
| 134301624U, // UQRSHLv8i8 |
| 201435118U, // UQRSHRNb |
| 201435118U, // UQRSHRNh |
| 201435118U, // UQRSHRNs |
| 268550762U, // UQRSHRNv16i8_shift |
| 134311340U, // UQRSHRNv2i32_shift |
| 134305950U, // UQRSHRNv4i16_shift |
| 268562820U, // UQRSHRNv4i32_shift |
| 268557474U, // UQRSHRNv8i16_shift |
| 134301764U, // UQRSHRNv8i8_shift |
| 201434799U, // UQSHLb |
| 201434799U, // UQSHLd |
| 201434799U, // UQSHLh |
| 201434799U, // UQSHLs |
| 134300753U, // UQSHLv16i8 |
| 134300753U, // UQSHLv16i8_shift |
| 201434799U, // UQSHLv1i16 |
| 201434799U, // UQSHLv1i32 |
| 201434799U, // UQSHLv1i64 |
| 201434799U, // UQSHLv1i8 |
| 134311145U, // UQSHLv2i32 |
| 134311145U, // UQSHLv2i32_shift |
| 134303870U, // UQSHLv2i64 |
| 134303870U, // UQSHLv2i64_shift |
| 134305755U, // UQSHLv4i16 |
| 134305755U, // UQSHLv4i16_shift |
| 134313096U, // UQSHLv4i32 |
| 134313096U, // UQSHLv4i32_shift |
| 134307693U, // UQSHLv8i16 |
| 134307693U, // UQSHLv8i16_shift |
| 134301603U, // UQSHLv8i8 |
| 134301603U, // UQSHLv8i8_shift |
| 201435101U, // UQSHRNb |
| 201435101U, // UQSHRNh |
| 201435101U, // UQSHRNs |
| 268550735U, // UQSHRNv16i8_shift |
| 134311317U, // UQSHRNv2i32_shift |
| 134305927U, // UQSHRNv4i16_shift |
| 268562795U, // UQSHRNv4i32_shift |
| 268557449U, // UQSHRNv8i16_shift |
| 134301741U, // UQSHRNv8i8_shift |
| 335563963U, // UQSUB_ZI_B |
| 402689211U, // UQSUB_ZI_D |
| 471911611U, // UQSUB_ZI_H |
| 536939707U, // UQSUB_ZI_S |
| 335563963U, // UQSUB_ZZZ_B |
| 402689211U, // UQSUB_ZZZ_D |
| 471911611U, // UQSUB_ZZZ_H |
| 536939707U, // UQSUB_ZZZ_S |
| 134300502U, // UQSUBv16i8 |
| 201428155U, // UQSUBv1i16 |
| 201428155U, // UQSUBv1i32 |
| 201428155U, // UQSUBv1i64 |
| 201428155U, // UQSUBv1i8 |
| 134310787U, // UQSUBv2i32 |
| 134303551U, // UQSUBv2i64 |
| 134305420U, // UQSUBv4i16 |
| 134312604U, // UQSUBv4i32 |
| 134307258U, // UQSUBv8i16 |
| 134301415U, // UQSUBv8i8 |
| 268550798U, // UQXTNv16i8 |
| 201435154U, // UQXTNv1i16 |
| 201435154U, // UQXTNv1i32 |
| 201435154U, // UQXTNv1i8 |
| 134311373U, // UQXTNv2i32 |
| 134305983U, // UQXTNv4i16 |
| 268562853U, // UQXTNv4i32 |
| 268557507U, // UQXTNv8i16 |
| 134301794U, // UQXTNv8i8 |
| 134310956U, // URECPEv2i32 |
| 134312783U, // URECPEv4i32 |
| 134300577U, // URHADDv16i8 |
| 134310862U, // URHADDv2i32 |
| 134305495U, // URHADDv4i16 |
| 134312689U, // URHADDv4i32 |
| 134307333U, // URHADDv8i16 |
| 134301462U, // URHADDv8i8 |
| 134300799U, // URSHLv16i8 |
| 201434829U, // URSHLv1i64 |
| 134311187U, // URSHLv2i32 |
| 134303912U, // URSHLv2i64 |
| 134305797U, // URSHLv4i16 |
| 134313138U, // URSHLv4i32 |
| 134307735U, // URSHLv8i16 |
| 134301645U, // URSHLv8i8 |
| 201435501U, // URSHRd |
| 134300962U, // URSHRv16i8_shift |
| 134311596U, // URSHRv2i32_shift |
| 134304223U, // URSHRv2i64_shift |
| 134306206U, // URSHRv4i16_shift |
| 134313527U, // URSHRv4i32_shift |
| 134308090U, // URSHRv8i16_shift |
| 134301916U, // URSHRv8i8_shift |
| 134310979U, // URSQRTEv2i32 |
| 134312806U, // URSQRTEv4i32 |
| 738378029U, // URSRAd |
| 268550934U, // URSRAv16i8_shift |
| 268561205U, // URSRAv2i32_shift |
| 268553989U, // URSRAv2i64_shift |
| 268555838U, // URSRAv4i16_shift |
| 268563022U, // URSRAv4i32_shift |
| 268557676U, // URSRAv8i16_shift |
| 268551853U, // URSRAv8i8_shift |
| 134306851U, // USHLLv16i8_shift |
| 134303950U, // USHLLv2i32_shift |
| 134313176U, // USHLLv4i16_shift |
| 134303312U, // USHLLv4i32_shift |
| 134312182U, // USHLLv8i16_shift |
| 134307773U, // USHLLv8i8_shift |
| 134300820U, // USHLv16i8 |
| 201434842U, // USHLv1i64 |
| 134311206U, // USHLv2i32 |
| 134303931U, // USHLv2i64 |
| 134305816U, // USHLv4i16 |
| 134313157U, // USHLv4i32 |
| 134307754U, // USHLv8i16 |
| 134301664U, // USHLv8i8 |
| 201435514U, // USHRd |
| 134300983U, // USHRv16i8_shift |
| 134311615U, // USHRv2i32_shift |
| 134304242U, // USHRv2i64_shift |
| 134306225U, // USHRv4i16_shift |
| 134313546U, // USHRv4i32_shift |
| 134308109U, // USHRv8i16_shift |
| 134301935U, // USHRv8i8_shift |
| 268551107U, // USQADDv16i8 |
| 738382809U, // USQADDv1i16 |
| 738382809U, // USQADDv1i32 |
| 738382809U, // USQADDv1i64 |
| 738382809U, // USQADDv1i8 |
| 268561389U, // USQADDv2i32 |
| 268554085U, // USQADDv2i64 |
| 268556022U, // USQADDv4i16 |
| 268563216U, // USQADDv4i32 |
| 268557860U, // USQADDv8i16 |
| 268551989U, // USQADDv8i8 |
| 738378042U, // USRAd |
| 268550955U, // USRAv16i8_shift |
| 268561224U, // USRAv2i32_shift |
| 268554008U, // USRAv2i64_shift |
| 268555857U, // USRAv4i16_shift |
| 268563041U, // USRAv4i32_shift |
| 268557695U, // USRAv8i16_shift |
| 268551872U, // USRAv8i8_shift |
| 134306785U, // USUBLv16i8_v8i16 |
| 134303810U, // USUBLv2i32_v2i64 |
| 134313036U, // USUBLv4i16_v4i32 |
| 134303246U, // USUBLv4i32_v2i64 |
| 134312116U, // USUBLv8i16_v4i32 |
| 134307633U, // USUBLv8i8_v8i16 |
| 134307090U, // USUBWv16i8_v8i16 |
| 134304510U, // USUBWv2i32_v2i64 |
| 134313945U, // USUBWv4i16_v4i32 |
| 134303431U, // USUBWv4i32_v2i64 |
| 134312436U, // USUBWv8i16_v4i32 |
| 134308508U, // USUBWv8i8_v8i16 |
| 536913352U, // UUNPKHI_ZZ_D |
| 48293320U, // UUNPKHI_ZZ_H |
| 1140925896U, // UUNPKHI_ZZ_S |
| 536914013U, // UUNPKLO_ZZ_D |
| 48293981U, // UUNPKLO_ZZ_H |
| 1140926557U, // UUNPKLO_ZZ_S |
| 35993U, // UXTB_ZPmZ_D |
| 68209817U, // UXTB_ZPmZ_H |
| 68761U, // UXTB_ZPmZ_S |
| 42385U, // UXTH_ZPmZ_D |
| 75153U, // UXTH_ZPmZ_S |
| 47976U, // UXTW_ZPmZ_D |
| 335560722U, // UZP1_PPP_B |
| 402685970U, // UZP1_PPP_D |
| 471908370U, // UZP1_PPP_H |
| 536936466U, // UZP1_PPP_S |
| 335560722U, // UZP1_ZZZ_B |
| 402685970U, // UZP1_ZZZ_D |
| 471908370U, // UZP1_ZZZ_H |
| 536936466U, // UZP1_ZZZ_S |
| 134300179U, // UZP1v16i8 |
| 134310616U, // UZP1v2i32 |
| 134303169U, // UZP1v2i64 |
| 134305239U, // UZP1v4i16 |
| 134312000U, // UZP1v4i32 |
| 134306711U, // UZP1v8i16 |
| 134301255U, // UZP1v8i8 |
| 335560789U, // UZP2_PPP_B |
| 402686037U, // UZP2_PPP_D |
| 471908437U, // UZP2_PPP_H |
| 536936533U, // UZP2_PPP_S |
| 335560789U, // UZP2_ZZZ_B |
| 402686037U, // UZP2_ZZZ_D |
| 471908437U, // UZP2_ZZZ_H |
| 536936533U, // UZP2_ZZZ_S |
| 134300366U, // UZP2v16i8 |
| 134310643U, // UZP2v2i32 |
| 134303411U, // UZP2v2i64 |
| 134305276U, // UZP2v4i16 |
| 134312416U, // UZP2v4i32 |
| 134307070U, // UZP2v8i16 |
| 134301292U, // UZP2v8i8 |
| 201348149U, // WHILELE_PWW_B |
| 201364533U, // WHILELE_PWW_D |
| 478204981U, // WHILELE_PWW_H |
| 201397301U, // WHILELE_PWW_S |
| 201348149U, // WHILELE_PXX_B |
| 201364533U, // WHILELE_PXX_D |
| 478204981U, // WHILELE_PXX_H |
| 201397301U, // WHILELE_PXX_S |
| 201353282U, // WHILELO_PWW_B |
| 201369666U, // WHILELO_PWW_D |
| 478210114U, // WHILELO_PWW_H |
| 201402434U, // WHILELO_PWW_S |
| 201353282U, // WHILELO_PXX_B |
| 201369666U, // WHILELO_PXX_D |
| 478210114U, // WHILELO_PXX_H |
| 201402434U, // WHILELO_PXX_S |
| 201357489U, // WHILELS_PWW_B |
| 201373873U, // WHILELS_PWW_D |
| 478214321U, // WHILELS_PWW_H |
| 201406641U, // WHILELS_PWW_S |
| 201357489U, // WHILELS_PXX_B |
| 201373873U, // WHILELS_PXX_D |
| 478214321U, // WHILELS_PXX_H |
| 201406641U, // WHILELS_PXX_S |
| 201357673U, // WHILELT_PWW_B |
| 201374057U, // WHILELT_PWW_D |
| 478214505U, // WHILELT_PWW_H |
| 201406825U, // WHILELT_PWW_S |
| 201357673U, // WHILELT_PXX_B |
| 201374057U, // WHILELT_PXX_D |
| 478214505U, // WHILELT_PXX_H |
| 201406825U, // WHILELT_PXX_S |
| 5269855U, // WRFFR |
| 15844U, // XAR |
| 5346191U, // XPACD |
| 5350831U, // XPACI |
| 15790U, // XPACLRI |
| 268550788U, // XTNv16i8 |
| 134311365U, // XTNv2i32 |
| 134305975U, // XTNv4i16 |
| 268562844U, // XTNv4i32 |
| 268557498U, // XTNv8i16 |
| 134301786U, // XTNv8i8 |
| 335560716U, // ZIP1_PPP_B |
| 402685964U, // ZIP1_PPP_D |
| 471908364U, // ZIP1_PPP_H |
| 536936460U, // ZIP1_PPP_S |
| 335560716U, // ZIP1_ZZZ_B |
| 402685964U, // ZIP1_ZZZ_D |
| 471908364U, // ZIP1_ZZZ_H |
| 536936460U, // ZIP1_ZZZ_S |
| 134300169U, // ZIP1v16i8 |
| 134310607U, // ZIP1v2i32 |
| 134303160U, // ZIP1v2i64 |
| 134305230U, // ZIP1v4i16 |
| 134311991U, // ZIP1v4i32 |
| 134306702U, // ZIP1v8i16 |
| 134301246U, // ZIP1v8i8 |
| 335560783U, // ZIP2_PPP_B |
| 402686031U, // ZIP2_PPP_D |
| 471908431U, // ZIP2_PPP_H |
| 536936527U, // ZIP2_PPP_S |
| 335560783U, // ZIP2_ZZZ_B |
| 402686031U, // ZIP2_ZZZ_D |
| 471908431U, // ZIP2_ZZZ_H |
| 536936527U, // ZIP2_ZZZ_S |
| 134300356U, // ZIP2v16i8 |
| 134310634U, // ZIP2v2i32 |
| 134303402U, // ZIP2v2i64 |
| 134305267U, // ZIP2v4i16 |
| 134312407U, // ZIP2v4i32 |
| 134307061U, // ZIP2v8i16 |
| 134301283U, // ZIP2v8i8 |
| 604010928U, // anonymous_1349 |
| }; |
| |
| static const uint32_t OpInfo1[] = { |
| 0U, // PHI |
| 0U, // INLINEASM |
| 0U, // CFI_INSTRUCTION |
| 0U, // EH_LABEL |
| 0U, // GC_LABEL |
| 0U, // ANNOTATION_LABEL |
| 0U, // KILL |
| 0U, // EXTRACT_SUBREG |
| 0U, // INSERT_SUBREG |
| 0U, // IMPLICIT_DEF |
| 0U, // SUBREG_TO_REG |
| 0U, // COPY_TO_REGCLASS |
| 0U, // DBG_VALUE |
| 0U, // DBG_LABEL |
| 0U, // REG_SEQUENCE |
| 0U, // COPY |
| 0U, // BUNDLE |
| 0U, // LIFETIME_START |
| 0U, // LIFETIME_END |
| 0U, // STACKMAP |
| 0U, // FENTRY_CALL |
| 0U, // PATCHPOINT |
| 0U, // LOAD_STACK_GUARD |
| 0U, // STATEPOINT |
| 0U, // LOCAL_ESCAPE |
| 0U, // FAULTING_OP |
| 0U, // PATCHABLE_OP |
| 0U, // PATCHABLE_FUNCTION_ENTER |
| 0U, // PATCHABLE_RET |
| 0U, // PATCHABLE_FUNCTION_EXIT |
| 0U, // PATCHABLE_TAIL_CALL |
| 0U, // PATCHABLE_EVENT_CALL |
| 0U, // PATCHABLE_TYPED_EVENT_CALL |
| 0U, // ICALL_BRANCH_FUNNEL |
| 0U, // G_ADD |
| 0U, // G_SUB |
| 0U, // G_MUL |
| 0U, // G_SDIV |
| 0U, // G_UDIV |
| 0U, // G_SREM |
| 0U, // G_UREM |
| 0U, // G_AND |
| 0U, // G_OR |
| 0U, // G_XOR |
| 0U, // G_IMPLICIT_DEF |
| 0U, // G_PHI |
| 0U, // G_FRAME_INDEX |
| 0U, // G_GLOBAL_VALUE |
| 0U, // G_EXTRACT |
| 0U, // G_UNMERGE_VALUES |
| 0U, // G_INSERT |
| 0U, // G_MERGE_VALUES |
| 0U, // G_PTRTOINT |
| 0U, // G_INTTOPTR |
| 0U, // G_BITCAST |
| 0U, // G_LOAD |
| 0U, // G_SEXTLOAD |
| 0U, // G_ZEXTLOAD |
| 0U, // G_STORE |
| 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS |
| 0U, // G_ATOMIC_CMPXCHG |
| 0U, // G_ATOMICRMW_XCHG |
| 0U, // G_ATOMICRMW_ADD |
| 0U, // G_ATOMICRMW_SUB |
| 0U, // G_ATOMICRMW_AND |
| 0U, // G_ATOMICRMW_NAND |
| 0U, // G_ATOMICRMW_OR |
| 0U, // G_ATOMICRMW_XOR |
| 0U, // G_ATOMICRMW_MAX |
| 0U, // G_ATOMICRMW_MIN |
| 0U, // G_ATOMICRMW_UMAX |
| 0U, // G_ATOMICRMW_UMIN |
| 0U, // G_BRCOND |
| 0U, // G_BRINDIRECT |
| 0U, // G_INTRINSIC |
| 0U, // G_INTRINSIC_W_SIDE_EFFECTS |
| 0U, // G_ANYEXT |
| 0U, // G_TRUNC |
| 0U, // G_CONSTANT |
| 0U, // G_FCONSTANT |
| 0U, // G_VASTART |
| 0U, // G_VAARG |
| 0U, // G_SEXT |
| 0U, // G_ZEXT |
| 0U, // G_SHL |
| 0U, // G_LSHR |
| 0U, // G_ASHR |
| 0U, // G_ICMP |
| 0U, // G_FCMP |
| 0U, // G_SELECT |
| 0U, // G_UADDE |
| 0U, // G_USUBE |
| 0U, // G_SADDO |
| 0U, // G_SSUBO |
| 0U, // G_UMULO |
| 0U, // G_SMULO |
| 0U, // G_UMULH |
| 0U, // G_SMULH |
| 0U, // G_FADD |
| 0U, // G_FSUB |
| 0U, // G_FMUL |
| 0U, // G_FMA |
| 0U, // G_FDIV |
| 0U, // G_FREM |
| 0U, // G_FPOW |
| 0U, // G_FEXP |
| 0U, // G_FEXP2 |
| 0U, // G_FLOG |
| 0U, // G_FLOG2 |
| 0U, // G_FNEG |
| 0U, // G_FPEXT |
| 0U, // G_FPTRUNC |
| 0U, // G_FPTOSI |
| 0U, // G_FPTOUI |
| 0U, // G_SITOFP |
| 0U, // G_UITOFP |
| 0U, // G_FABS |
| 0U, // G_GEP |
| 0U, // G_PTR_MASK |
| 0U, // G_BR |
| 0U, // G_INSERT_VECTOR_ELT |
| 0U, // G_EXTRACT_VECTOR_ELT |
| 0U, // G_SHUFFLE_VECTOR |
| 0U, // G_BSWAP |
| 0U, // G_ADDRSPACE_CAST |
| 0U, // G_BLOCK_ADDR |
| 0U, // ABS_ZPmZ_B |
| 64U, // ABS_ZPmZ_D |
| 129U, // ABS_ZPmZ_H |
| 192U, // ABS_ZPmZ_S |
| 2U, // ABSv16i8 |
| 2U, // ABSv1i64 |
| 2U, // ABSv2i32 |
| 2U, // ABSv2i64 |
| 2U, // ABSv4i16 |
| 2U, // ABSv4i32 |
| 2U, // ABSv8i16 |
| 2U, // ABSv8i8 |
| 259U, // ADCSWr |
| 259U, // ADCSXr |
| 259U, // ADCWr |
| 259U, // ADCXr |
| 323U, // ADDHNv2i64_v2i32 |
| 387U, // ADDHNv2i64_v4i32 |
| 323U, // ADDHNv4i32_v4i16 |
| 387U, // ADDHNv4i32_v8i16 |
| 387U, // ADDHNv8i16_v16i8 |
| 323U, // ADDHNv8i16_v8i8 |
| 259U, // ADDPL_XXI |
| 323U, // ADDPv16i8 |
| 323U, // ADDPv2i32 |
| 323U, // ADDPv2i64 |
| 2U, // ADDPv2i64p |
| 323U, // ADDPv4i16 |
| 323U, // ADDPv4i32 |
| 323U, // ADDPv8i16 |
| 323U, // ADDPv8i8 |
| 451U, // ADDSWri |
| 0U, // ADDSWrr |
| 515U, // ADDSWrs |
| 579U, // ADDSWrx |
| 451U, // ADDSXri |
| 0U, // ADDSXrr |
| 515U, // ADDSXrs |
| 579U, // ADDSXrx |
| 8451U, // ADDSXrx64 |
| 259U, // ADDVL_XXI |
| 2U, // ADDVv16i8v |
| 2U, // ADDVv4i16v |
| 2U, // ADDVv4i32v |
| 2U, // ADDVv8i16v |
| 2U, // ADDVv8i8v |
| 451U, // ADDWri |
| 0U, // ADDWrr |
| 515U, // ADDWrs |
| 579U, // ADDWrx |
| 451U, // ADDXri |
| 0U, // ADDXrr |
| 515U, // ADDXrs |
| 579U, // ADDXrx |
| 8451U, // ADDXrx64 |
| 643U, // ADD_ZI_B |
| 707U, // ADD_ZI_D |
| 4U, // ADD_ZI_H |
| 771U, // ADD_ZI_S |
| 17216U, // ADD_ZPmZ_B |
| 279424U, // ADD_ZPmZ_D |
| 549829U, // ADD_ZPmZ_H |
| 803840U, // ADD_ZPmZ_S |
| 835U, // ADD_ZZZ_B |
| 899U, // ADD_ZZZ_D |
| 133U, // ADD_ZZZ_H |
| 1027U, // ADD_ZZZ_S |
| 0U, // ADDlowTLS |
| 323U, // ADDv16i8 |
| 259U, // ADDv1i64 |
| 323U, // ADDv2i32 |
| 323U, // ADDv2i64 |
| 323U, // ADDv4i16 |
| 323U, // ADDv4i32 |
| 323U, // ADDv8i16 |
| 323U, // ADDv8i8 |
| 0U, // ADJCALLSTACKDOWN |
| 0U, // ADJCALLSTACKUP |
| 2U, // ADR |
| 0U, // ADRP |
| 1091U, // ADR_LSL_ZZZ_D_0 |
| 1155U, // ADR_LSL_ZZZ_D_1 |
| 1219U, // ADR_LSL_ZZZ_D_2 |
| 1283U, // ADR_LSL_ZZZ_D_3 |
| 1347U, // ADR_LSL_ZZZ_S_0 |
| 1411U, // ADR_LSL_ZZZ_S_1 |
| 1475U, // ADR_LSL_ZZZ_S_2 |
| 1539U, // ADR_LSL_ZZZ_S_3 |
| 1603U, // ADR_SXTW_ZZZ_D_0 |
| 1667U, // ADR_SXTW_ZZZ_D_1 |
| 1731U, // ADR_SXTW_ZZZ_D_2 |
| 1795U, // ADR_SXTW_ZZZ_D_3 |
| 1859U, // ADR_UXTW_ZZZ_D_0 |
| 1923U, // ADR_UXTW_ZZZ_D_1 |
| 1987U, // ADR_UXTW_ZZZ_D_2 |
| 2051U, // ADR_UXTW_ZZZ_D_3 |
| 2U, // AESDrr |
| 2U, // AESErr |
| 2U, // AESIMCrr |
| 0U, // AESIMCrrTied |
| 2U, // AESMCrr |
| 0U, // AESMCrrTied |
| 2115U, // ANDSWri |
| 0U, // ANDSWrr |
| 515U, // ANDSWrs |
| 2179U, // ANDSXri |
| 0U, // ANDSXrr |
| 515U, // ANDSXrs |
| 17222U, // ANDS_PPzPP |
| 835U, // ANDV_VPZ_B |
| 899U, // ANDV_VPZ_D |
| 2243U, // ANDV_VPZ_H |
| 1027U, // ANDV_VPZ_S |
| 2115U, // ANDWri |
| 0U, // ANDWrr |
| 515U, // ANDWrs |
| 2179U, // ANDXri |
| 0U, // ANDXrr |
| 515U, // ANDXrs |
| 17222U, // AND_PPzPP |
| 2179U, // AND_ZI |
| 17216U, // AND_ZPmZ_B |
| 279424U, // AND_ZPmZ_D |
| 549829U, // AND_ZPmZ_H |
| 803840U, // AND_ZPmZ_S |
| 899U, // AND_ZZZ |
| 323U, // ANDv16i8 |
| 323U, // ANDv8i8 |
| 1065792U, // ASRD_ZPmI_B |
| 1065856U, // ASRD_ZPmI_D |
| 33733U, // ASRD_ZPmI_H |
| 1065984U, // ASRD_ZPmI_S |
| 17216U, // ASRR_ZPmZ_B |
| 279424U, // ASRR_ZPmZ_D |
| 549829U, // ASRR_ZPmZ_H |
| 803840U, // ASRR_ZPmZ_S |
| 259U, // ASRVWr |
| 259U, // ASRVXr |
| 279360U, // ASR_WIDE_ZPmZ_B |
| 41925U, // ASR_WIDE_ZPmZ_H |
| 279552U, // ASR_WIDE_ZPmZ_S |
| 899U, // ASR_WIDE_ZZZ_B |
| 7U, // ASR_WIDE_ZZZ_H |
| 899U, // ASR_WIDE_ZZZ_S |
| 1065792U, // ASR_ZPmI_B |
| 1065856U, // ASR_ZPmI_D |
| 33733U, // ASR_ZPmI_H |
| 1065984U, // ASR_ZPmI_S |
| 17216U, // ASR_ZPmZ_B |
| 279424U, // ASR_ZPmZ_D |
| 549829U, // ASR_ZPmZ_H |
| 803840U, // ASR_ZPmZ_S |
| 259U, // ASR_ZZI_B |
| 259U, // ASR_ZZI_D |
| 8U, // ASR_ZZI_H |
| 259U, // ASR_ZZI_S |
| 2U, // AUTDA |
| 2U, // AUTDB |
| 0U, // AUTDZA |
| 0U, // AUTDZB |
| 2U, // AUTIA |
| 0U, // AUTIA1716 |
| 0U, // AUTIASP |
| 0U, // AUTIAZ |
| 2U, // AUTIB |
| 0U, // AUTIB1716 |
| 0U, // AUTIBSP |
| 0U, // AUTIBZ |
| 0U, // AUTIZA |
| 0U, // AUTIZB |
| 0U, // B |
| 0U, // BCAX |
| 1329411U, // BFMWri |
| 1329411U, // BFMXri |
| 0U, // BICSWrr |
| 515U, // BICSWrs |
| 0U, // BICSXrr |
| 515U, // BICSXrs |
| 17222U, // BICS_PPzPP |
| 0U, // BICWrr |
| 515U, // BICWrs |
| 0U, // BICXrr |
| 515U, // BICXrs |
| 17222U, // BIC_PPzPP |
| 17216U, // BIC_ZPmZ_B |
| 279424U, // BIC_ZPmZ_D |
| 549829U, // BIC_ZPmZ_H |
| 803840U, // BIC_ZPmZ_S |
| 899U, // BIC_ZZZ |
| 323U, // BICv16i8 |
| 0U, // BICv2i32 |
| 0U, // BICv4i16 |
| 0U, // BICv4i32 |
| 0U, // BICv8i16 |
| 323U, // BICv8i8 |
| 323U, // BIFv16i8 |
| 323U, // BIFv8i8 |
| 387U, // BITv16i8 |
| 387U, // BITv8i8 |
| 0U, // BL |
| 0U, // BLR |
| 2U, // BLRAA |
| 0U, // BLRAAZ |
| 2U, // BLRAB |
| 0U, // BLRABZ |
| 0U, // BR |
| 2U, // BRAA |
| 0U, // BRAAZ |
| 2U, // BRAB |
| 0U, // BRABZ |
| 0U, // BRK |
| 838U, // BRKAS_PPzP |
| 0U, // BRKA_PPmP |
| 838U, // BRKA_PPzP |
| 838U, // BRKBS_PPzP |
| 0U, // BRKB_PPmP |
| 838U, // BRKB_PPzP |
| 17222U, // BRKNS_PPzP |
| 17222U, // BRKN_PPzP |
| 17222U, // BRKPAS_PPzPP |
| 17222U, // BRKPA_PPzPP |
| 17222U, // BRKPBS_PPzPP |
| 17222U, // BRKPB_PPzPP |
| 387U, // BSLv16i8 |
| 387U, // BSLv8i8 |
| 0U, // Bcc |
| 51465U, // CASAB |
| 51465U, // CASAH |
| 51465U, // CASALB |
| 51465U, // CASALH |
| 51465U, // CASALW |
| 51465U, // CASALX |
| 51465U, // CASAW |
| 51465U, // CASAX |
| 51465U, // CASB |
| 51465U, // CASH |
| 51465U, // CASLB |
| 51465U, // CASLH |
| 51465U, // CASLW |
| 51465U, // CASLX |
| 0U, // CASPALW |
| 0U, // CASPALX |
| 0U, // CASPAW |
| 0U, // CASPAX |
| 0U, // CASPLW |
| 0U, // CASPLX |
| 0U, // CASPW |
| 0U, // CASPX |
| 51465U, // CASW |
| 51465U, // CASX |
| 0U, // CBNZW |
| 0U, // CBNZX |
| 0U, // CBZW |
| 0U, // CBZX |
| 1589507U, // CCMNWi |
| 1589507U, // CCMNWr |
| 1589507U, // CCMNXi |
| 1589507U, // CCMNXr |
| 1589507U, // CCMPWi |
| 1589507U, // CCMPWr |
| 1589507U, // CCMPXi |
| 1589507U, // CCMPXr |
| 0U, // CFINV |
| 16643U, // CLASTA_RPZ_B |
| 278787U, // CLASTA_RPZ_D |
| 1851651U, // CLASTA_RPZ_H |
| 803075U, // CLASTA_RPZ_S |
| 16643U, // CLASTA_VPZ_B |
| 278787U, // CLASTA_VPZ_D |
| 1851651U, // CLASTA_VPZ_H |
| 803075U, // CLASTA_VPZ_S |
| 17219U, // CLASTA_ZPZ_B |
| 279427U, // CLASTA_ZPZ_D |
| 549829U, // CLASTA_ZPZ_H |
| 803843U, // CLASTA_ZPZ_S |
| 16643U, // CLASTB_RPZ_B |
| 278787U, // CLASTB_RPZ_D |
| 1851651U, // CLASTB_RPZ_H |
| 803075U, // CLASTB_RPZ_S |
| 16643U, // CLASTB_VPZ_B |
| 278787U, // CLASTB_VPZ_D |
| 1851651U, // CLASTB_VPZ_H |
| 803075U, // CLASTB_VPZ_S |
| 17219U, // CLASTB_ZPZ_B |
| 279427U, // CLASTB_ZPZ_D |
| 549829U, // CLASTB_ZPZ_H |
| 803843U, // CLASTB_ZPZ_S |
| 0U, // CLREX |
| 2U, // CLSWr |
| 2U, // CLSXr |
| 0U, // CLS_ZPmZ_B |
| 64U, // CLS_ZPmZ_D |
| 129U, // CLS_ZPmZ_H |
| 192U, // CLS_ZPmZ_S |
| 2U, // CLSv16i8 |
| 2U, // CLSv2i32 |
| 2U, // CLSv4i16 |
| 2U, // CLSv4i32 |
| 2U, // CLSv8i16 |
| 2U, // CLSv8i8 |
| 2U, // CLZWr |
| 2U, // CLZXr |
| 0U, // CLZ_ZPmZ_B |
| 64U, // CLZ_ZPmZ_D |
| 129U, // CLZ_ZPmZ_H |
| 192U, // CLZ_ZPmZ_S |
| 2U, // CLZv16i8 |
| 2U, // CLZv2i32 |
| 2U, // CLZv4i16 |
| 2U, // CLZv4i32 |
| 2U, // CLZv8i16 |
| 2U, // CLZv8i8 |
| 323U, // CMEQv16i8 |
| 10U, // CMEQv16i8rz |
| 259U, // CMEQv1i64 |
| 10U, // CMEQv1i64rz |
| 323U, // CMEQv2i32 |
| 10U, // CMEQv2i32rz |
| 323U, // CMEQv2i64 |
| 10U, // CMEQv2i64rz |
| 323U, // CMEQv4i16 |
| 10U, // CMEQv4i16rz |
| 323U, // CMEQv4i32 |
| 10U, // CMEQv4i32rz |
| 323U, // CMEQv8i16 |
| 10U, // CMEQv8i16rz |
| 323U, // CMEQv8i8 |
| 10U, // CMEQv8i8rz |
| 323U, // CMGEv16i8 |
| 10U, // CMGEv16i8rz |
| 259U, // CMGEv1i64 |
| 10U, // CMGEv1i64rz |
| 323U, // CMGEv2i32 |
| 10U, // CMGEv2i32rz |
| 323U, // CMGEv2i64 |
| 10U, // CMGEv2i64rz |
| 323U, // CMGEv4i16 |
| 10U, // CMGEv4i16rz |
| 323U, // CMGEv4i32 |
| 10U, // CMGEv4i32rz |
| 323U, // CMGEv8i16 |
| 10U, // CMGEv8i16rz |
| 323U, // CMGEv8i8 |
| 10U, // CMGEv8i8rz |
| 323U, // CMGTv16i8 |
| 10U, // CMGTv16i8rz |
| 259U, // CMGTv1i64 |
| 10U, // CMGTv1i64rz |
| 323U, // CMGTv2i32 |
| 10U, // CMGTv2i32rz |
| 323U, // CMGTv2i64 |
| 10U, // CMGTv2i64rz |
| 323U, // CMGTv4i16 |
| 10U, // CMGTv4i16rz |
| 323U, // CMGTv4i32 |
| 10U, // CMGTv4i32rz |
| 323U, // CMGTv8i16 |
| 10U, // CMGTv8i16rz |
| 323U, // CMGTv8i8 |
| 10U, // CMGTv8i8rz |
| 323U, // CMHIv16i8 |
| 259U, // CMHIv1i64 |
| 323U, // CMHIv2i32 |
| 323U, // CMHIv2i64 |
| 323U, // CMHIv4i16 |
| 323U, // CMHIv4i32 |
| 323U, // CMHIv8i16 |
| 323U, // CMHIv8i8 |
| 323U, // CMHSv16i8 |
| 259U, // CMHSv1i64 |
| 323U, // CMHSv2i32 |
| 323U, // CMHSv2i64 |
| 323U, // CMHSv4i16 |
| 323U, // CMHSv4i32 |
| 323U, // CMHSv8i16 |
| 323U, // CMHSv8i8 |
| 10U, // CMLEv16i8rz |
| 10U, // CMLEv1i64rz |
| 10U, // CMLEv2i32rz |
| 10U, // CMLEv2i64rz |
| 10U, // CMLEv4i16rz |
| 10U, // CMLEv4i32rz |
| 10U, // CMLEv8i16rz |
| 10U, // CMLEv8i8rz |
| 10U, // CMLTv16i8rz |
| 10U, // CMLTv1i64rz |
| 10U, // CMLTv2i32rz |
| 10U, // CMLTv2i64rz |
| 10U, // CMLTv4i16rz |
| 10U, // CMLTv4i32rz |
| 10U, // CMLTv8i16rz |
| 10U, // CMLTv8i8rz |
| 1065798U, // CMPEQ_PPzZI_B |
| 1065862U, // CMPEQ_PPzZI_D |
| 33733U, // CMPEQ_PPzZI_H |
| 1065990U, // CMPEQ_PPzZI_S |
| 17222U, // CMPEQ_PPzZZ_B |
| 279430U, // CMPEQ_PPzZZ_D |
| 549829U, // CMPEQ_PPzZZ_H |
| 803846U, // CMPEQ_PPzZZ_S |
| 279366U, // CMPEQ_WIDE_PPzZZ_B |
| 41925U, // CMPEQ_WIDE_PPzZZ_H |
| 279558U, // CMPEQ_WIDE_PPzZZ_S |
| 1065798U, // CMPGE_PPzZI_B |
| 1065862U, // CMPGE_PPzZI_D |
| 33733U, // CMPGE_PPzZI_H |
| 1065990U, // CMPGE_PPzZI_S |
| 17222U, // CMPGE_PPzZZ_B |
| 279430U, // CMPGE_PPzZZ_D |
| 549829U, // CMPGE_PPzZZ_H |
| 803846U, // CMPGE_PPzZZ_S |
| 279366U, // CMPGE_WIDE_PPzZZ_B |
| 41925U, // CMPGE_WIDE_PPzZZ_H |
| 279558U, // CMPGE_WIDE_PPzZZ_S |
| 1065798U, // CMPGT_PPzZI_B |
| 1065862U, // CMPGT_PPzZI_D |
| 33733U, // CMPGT_PPzZI_H |
| 1065990U, // CMPGT_PPzZI_S |
| 17222U, // CMPGT_PPzZZ_B |
| 279430U, // CMPGT_PPzZZ_D |
| 549829U, // CMPGT_PPzZZ_H |
| 803846U, // CMPGT_PPzZZ_S |
| 279366U, // CMPGT_WIDE_PPzZZ_B |
| 41925U, // CMPGT_WIDE_PPzZZ_H |
| 279558U, // CMPGT_WIDE_PPzZZ_S |
| 2114374U, // CMPHI_PPzZI_B |
| 2114438U, // CMPHI_PPzZI_D |
| 58309U, // CMPHI_PPzZI_H |
| 2114566U, // CMPHI_PPzZI_S |
| 17222U, // CMPHI_PPzZZ_B |
| 279430U, // CMPHI_PPzZZ_D |
| 549829U, // CMPHI_PPzZZ_H |
| 803846U, // CMPHI_PPzZZ_S |
| 279366U, // CMPHI_WIDE_PPzZZ_B |
| 41925U, // CMPHI_WIDE_PPzZZ_H |
| 279558U, // CMPHI_WIDE_PPzZZ_S |
| 2114374U, // CMPHS_PPzZI_B |
| 2114438U, // CMPHS_PPzZI_D |
| 58309U, // CMPHS_PPzZI_H |
| 2114566U, // CMPHS_PPzZI_S |
| 17222U, // CMPHS_PPzZZ_B |
| 279430U, // CMPHS_PPzZZ_D |
| 549829U, // CMPHS_PPzZZ_H |
| 803846U, // CMPHS_PPzZZ_S |
| 279366U, // CMPHS_WIDE_PPzZZ_B |
| 41925U, // CMPHS_WIDE_PPzZZ_H |
| 279558U, // CMPHS_WIDE_PPzZZ_S |
| 1065798U, // CMPLE_PPzZI_B |
| 1065862U, // CMPLE_PPzZI_D |
| 33733U, // CMPLE_PPzZI_H |
| 1065990U, // CMPLE_PPzZI_S |
| 279366U, // CMPLE_WIDE_PPzZZ_B |
| 41925U, // CMPLE_WIDE_PPzZZ_H |
| 279558U, // CMPLE_WIDE_PPzZZ_S |
| 2114374U, // CMPLO_PPzZI_B |
| 2114438U, // CMPLO_PPzZI_D |
| 58309U, // CMPLO_PPzZI_H |
| 2114566U, // CMPLO_PPzZI_S |
| 279366U, // CMPLO_WIDE_PPzZZ_B |
| 41925U, // CMPLO_WIDE_PPzZZ_H |
| 279558U, // CMPLO_WIDE_PPzZZ_S |
| 2114374U, // CMPLS_PPzZI_B |
| 2114438U, // CMPLS_PPzZI_D |
| 58309U, // CMPLS_PPzZI_H |
| 2114566U, // CMPLS_PPzZI_S |
| 279366U, // CMPLS_WIDE_PPzZZ_B |
| 41925U, // CMPLS_WIDE_PPzZZ_H |
| 279558U, // CMPLS_WIDE_PPzZZ_S |
| 1065798U, // CMPLT_PPzZI_B |
| 1065862U, // CMPLT_PPzZI_D |
| 33733U, // CMPLT_PPzZI_H |
| 1065990U, // CMPLT_PPzZI_S |
| 279366U, // CMPLT_WIDE_PPzZZ_B |
| 41925U, // CMPLT_WIDE_PPzZZ_H |
| 279558U, // CMPLT_WIDE_PPzZZ_S |
| 1065798U, // CMPNE_PPzZI_B |
| 1065862U, // CMPNE_PPzZI_D |
| 33733U, // CMPNE_PPzZI_H |
| 1065990U, // CMPNE_PPzZI_S |
| 17222U, // CMPNE_PPzZZ_B |
| 279430U, // CMPNE_PPzZZ_D |
| 549829U, // CMPNE_PPzZZ_H |
| 803846U, // CMPNE_PPzZZ_S |
| 279366U, // CMPNE_WIDE_PPzZZ_B |
| 41925U, // CMPNE_WIDE_PPzZZ_H |
| 279558U, // CMPNE_WIDE_PPzZZ_S |
| 0U, // CMP_SWAP_128 |
| 0U, // CMP_SWAP_16 |
| 0U, // CMP_SWAP_32 |
| 0U, // CMP_SWAP_64 |
| 0U, // CMP_SWAP_8 |
| 323U, // CMTSTv16i8 |
| 259U, // CMTSTv1i64 |
| 323U, // CMTSTv2i32 |
| 323U, // CMTSTv2i64 |
| 323U, // CMTSTv4i16 |
| 323U, // CMTSTv4i32 |
| 323U, // CMTSTv8i16 |
| 323U, // CMTSTv8i8 |
| 0U, // CNOT_ZPmZ_B |
| 64U, // CNOT_ZPmZ_D |
| 129U, // CNOT_ZPmZ_H |
| 192U, // CNOT_ZPmZ_S |
| 11U, // CNTB_XPiI |
| 11U, // CNTD_XPiI |
| 11U, // CNTH_XPiI |
| 835U, // CNTP_XPP_B |
| 899U, // CNTP_XPP_D |
| 2243U, // CNTP_XPP_H |
| 1027U, // CNTP_XPP_S |
| 11U, // CNTW_XPiI |
| 0U, // CNT_ZPmZ_B |
| 64U, // CNT_ZPmZ_D |
| 129U, // CNT_ZPmZ_H |
| 192U, // CNT_ZPmZ_S |
| 2U, // CNTv16i8 |
| 2U, // CNTv8i8 |
| 899U, // COMPACT_ZPZ_D |
| 1027U, // COMPACT_ZPZ_S |
| 2368U, // CPY_ZPmI_B |
| 2432U, // CPY_ZPmI_D |
| 12U, // CPY_ZPmI_H |
| 2496U, // CPY_ZPmI_S |
| 2304U, // CPY_ZPmR_B |
| 2304U, // CPY_ZPmR_D |
| 141U, // CPY_ZPmR_H |
| 2304U, // CPY_ZPmR_S |
| 2304U, // CPY_ZPmV_B |
| 2304U, // CPY_ZPmV_D |
| 141U, // CPY_ZPmV_H |
| 2304U, // CPY_ZPmV_S |
| 2566U, // CPY_ZPzI_B |
| 2630U, // CPY_ZPzI_D |
| 14U, // CPY_ZPzI_H |
| 2694U, // CPY_ZPzI_S |
| 15U, // CPYi16 |
| 15U, // CPYi32 |
| 15U, // CPYi64 |
| 15U, // CPYi8 |
| 259U, // CRC32Brr |
| 259U, // CRC32CBrr |
| 259U, // CRC32CHrr |
| 259U, // CRC32CWrr |
| 259U, // CRC32CXrr |
| 259U, // CRC32Hrr |
| 259U, // CRC32Wrr |
| 259U, // CRC32Xrr |
| 1589507U, // CSELWr |
| 1589507U, // CSELXr |
| 1589507U, // CSINCWr |
| 1589507U, // CSINCXr |
| 1589507U, // CSINVWr |
| 1589507U, // CSINVXr |
| 1589507U, // CSNEGWr |
| 1589507U, // CSNEGXr |
| 2U, // CTERMEQ_WW |
| 2U, // CTERMEQ_XX |
| 2U, // CTERMNE_WW |
| 2U, // CTERMNE_XX |
| 0U, // CompilerBarrier |
| 0U, // DCPS1 |
| 0U, // DCPS2 |
| 0U, // DCPS3 |
| 0U, // DECB_XPiI |
| 0U, // DECD_XPiI |
| 0U, // DECD_ZPiI |
| 0U, // DECH_XPiI |
| 0U, // DECH_ZPiI |
| 2U, // DECP_XP_B |
| 2U, // DECP_XP_D |
| 2U, // DECP_XP_H |
| 2U, // DECP_XP_S |
| 2U, // DECP_ZP_D |
| 0U, // DECP_ZP_H |
| 2U, // DECP_ZP_S |
| 0U, // DECW_XPiI |
| 0U, // DECW_ZPiI |
| 0U, // DMB |
| 0U, // DRPS |
| 0U, // DSB |
| 0U, // DUPM_ZI |
| 0U, // DUP_ZI_B |
| 0U, // DUP_ZI_D |
| 0U, // DUP_ZI_H |
| 0U, // DUP_ZI_S |
| 2U, // DUP_ZR_B |
| 2U, // DUP_ZR_D |
| 0U, // DUP_ZR_H |
| 2U, // DUP_ZR_S |
| 15U, // DUP_ZZI_B |
| 15U, // DUP_ZZI_D |
| 0U, // DUP_ZZI_H |
| 0U, // DUP_ZZI_Q |
| 15U, // DUP_ZZI_S |
| 2U, // DUPv16i8gpr |
| 15U, // DUPv16i8lane |
| 2U, // DUPv2i32gpr |
| 15U, // DUPv2i32lane |
| 2U, // DUPv2i64gpr |
| 15U, // DUPv2i64lane |
| 2U, // DUPv4i16gpr |
| 15U, // DUPv4i16lane |
| 2U, // DUPv4i32gpr |
| 15U, // DUPv4i32lane |
| 2U, // DUPv8i16gpr |
| 15U, // DUPv8i16lane |
| 2U, // DUPv8i8gpr |
| 15U, // DUPv8i8lane |
| 0U, // EONWrr |
| 515U, // EONWrs |
| 0U, // EONXrr |
| 515U, // EONXrs |
| 0U, // EOR3 |
| 17222U, // EORS_PPzPP |
| 835U, // EORV_VPZ_B |
| 899U, // EORV_VPZ_D |
| 2243U, // EORV_VPZ_H |
| 1027U, // EORV_VPZ_S |
| 2115U, // EORWri |
| 0U, // EORWrr |
| 515U, // EORWrs |
| 2179U, // EORXri |
| 0U, // EORXrr |
| 515U, // EORXrs |
| 17222U, // EOR_PPzPP |
| 2179U, // EOR_ZI |
| 17216U, // EOR_ZPmZ_B |
| 279424U, // EOR_ZPmZ_D |
| 549829U, // EOR_ZPmZ_H |
| 803840U, // EOR_ZPmZ_S |
| 899U, // EOR_ZZZ |
| 323U, // EORv16i8 |
| 323U, // EORv8i8 |
| 0U, // ERET |
| 0U, // ERETAA |
| 0U, // ERETAB |
| 1065219U, // EXTRWrri |
| 1065219U, // EXTRXrri |
| 2114371U, // EXT_ZZI |
| 1065283U, // EXTv16i8 |
| 1065283U, // EXTv8i8 |
| 0U, // F128CSEL |
| 259U, // FABD16 |
| 259U, // FABD32 |
| 259U, // FABD64 |
| 279424U, // FABD_ZPmZ_D |
| 549829U, // FABD_ZPmZ_H |
| 803840U, // FABD_ZPmZ_S |
| 323U, // FABDv2f32 |
| 323U, // FABDv2f64 |
| 323U, // FABDv4f16 |
| 323U, // FABDv4f32 |
| 323U, // FABDv8f16 |
| 2U, // FABSDr |
| 2U, // FABSHr |
| 2U, // FABSSr |
| 64U, // FABS_ZPmZ_D |
| 129U, // FABS_ZPmZ_H |
| 192U, // FABS_ZPmZ_S |
| 2U, // FABSv2f32 |
| 2U, // FABSv2f64 |
| 2U, // FABSv4f16 |
| 2U, // FABSv4f32 |
| 2U, // FABSv8f16 |
| 259U, // FACGE16 |
| 259U, // FACGE32 |
| 259U, // FACGE64 |
| 279430U, // FACGE_PPzZZ_D |
| 549829U, // FACGE_PPzZZ_H |
| 803846U, // FACGE_PPzZZ_S |
| 323U, // FACGEv2f32 |
| 323U, // FACGEv2f64 |
| 323U, // FACGEv4f16 |
| 323U, // FACGEv4f32 |
| 323U, // FACGEv8f16 |
| 259U, // FACGT16 |
| 259U, // FACGT32 |
| 259U, // FACGT64 |
| 279430U, // FACGT_PPzZZ_D |
| 549829U, // FACGT_PPzZZ_H |
| 803846U, // FACGT_PPzZZ_S |
| 323U, // FACGTv2f32 |
| 323U, // FACGTv2f64 |
| 323U, // FACGTv4f16 |
| 323U, // FACGTv4f32 |
| 323U, // FACGTv8f16 |
| 278787U, // FADDA_VPZ_D |
| 1851651U, // FADDA_VPZ_H |
| 803075U, // FADDA_VPZ_S |
| 259U, // FADDDrr |
| 259U, // FADDHrr |
| 323U, // FADDPv2f32 |
| 323U, // FADDPv2f64 |
| 2U, // FADDPv2i16p |
| 2U, // FADDPv2i32p |
| 2U, // FADDPv2i64p |
| 323U, // FADDPv4f16 |
| 323U, // FADDPv4f32 |
| 323U, // FADDPv8f16 |
| 259U, // FADDSrr |
| 899U, // FADDV_VPZ_D |
| 2243U, // FADDV_VPZ_H |
| 1027U, // FADDV_VPZ_S |
| 2376576U, // FADD_ZPmI_D |
| 66501U, // FADD_ZPmI_H |
| 2376704U, // FADD_ZPmI_S |
| 279424U, // FADD_ZPmZ_D |
| 549829U, // FADD_ZPmZ_H |
| 803840U, // FADD_ZPmZ_S |
| 899U, // FADD_ZZZ_D |
| 133U, // FADD_ZZZ_H |
| 1027U, // FADD_ZZZ_S |
| 323U, // FADDv2f32 |
| 323U, // FADDv2f64 |
| 323U, // FADDv4f16 |
| 323U, // FADDv4f32 |
| 323U, // FADDv8f16 |
| 17056640U, // FCADD_ZPmZ_D |
| 36201413U, // FCADD_ZPmZ_H |
| 17581056U, // FCADD_ZPmZ_S |
| 2900291U, // FCADDv2f32 |
| 2900291U, // FCADDv2f64 |
| 2900291U, // FCADDv4f16 |
| 2900291U, // FCADDv4f32 |
| 2900291U, // FCADDv8f16 |
| 1589507U, // FCCMPDrr |
| 1589507U, // FCCMPEDrr |
| 1589507U, // FCCMPEHrr |
| 1589507U, // FCCMPESrr |
| 1589507U, // FCCMPHrr |
| 1589507U, // FCCMPSrr |
| 259U, // FCMEQ16 |
| 259U, // FCMEQ32 |
| 259U, // FCMEQ64 |
| 74630U, // FCMEQ_PPzZ0_D |
| 2757U, // FCMEQ_PPzZ0_H |
| 74758U, // FCMEQ_PPzZ0_S |
| 279430U, // FCMEQ_PPzZZ_D |
| 549829U, // FCMEQ_PPzZZ_H |
| 803846U, // FCMEQ_PPzZZ_S |
| 16U, // FCMEQv1i16rz |
| 16U, // FCMEQv1i32rz |
| 16U, // FCMEQv1i64rz |
| 323U, // FCMEQv2f32 |
| 323U, // FCMEQv2f64 |
| 16U, // FCMEQv2i32rz |
| 16U, // FCMEQv2i64rz |
| 323U, // FCMEQv4f16 |
| 323U, // FCMEQv4f32 |
| 16U, // FCMEQv4i16rz |
| 16U, // FCMEQv4i32rz |
| 323U, // FCMEQv8f16 |
| 16U, // FCMEQv8i16rz |
| 259U, // FCMGE16 |
| 259U, // FCMGE32 |
| 259U, // FCMGE64 |
| 74630U, // FCMGE_PPzZ0_D |
| 2757U, // FCMGE_PPzZ0_H |
| 74758U, // FCMGE_PPzZ0_S |
| 279430U, // FCMGE_PPzZZ_D |
| 549829U, // FCMGE_PPzZZ_H |
| 803846U, // FCMGE_PPzZZ_S |
| 16U, // FCMGEv1i16rz |
| 16U, // FCMGEv1i32rz |
| 16U, // FCMGEv1i64rz |
| 323U, // FCMGEv2f32 |
| 323U, // FCMGEv2f64 |
| 16U, // FCMGEv2i32rz |
| 16U, // FCMGEv2i64rz |
| 323U, // FCMGEv4f16 |
| 323U, // FCMGEv4f32 |
| 16U, // FCMGEv4i16rz |
| 16U, // FCMGEv4i32rz |
| 323U, // FCMGEv8f16 |
| 16U, // FCMGEv8i16rz |
| 259U, // FCMGT16 |
| 259U, // FCMGT32 |
| 259U, // FCMGT64 |
| 74630U, // FCMGT_PPzZ0_D |
| 2757U, // FCMGT_PPzZ0_H |
| 74758U, // FCMGT_PPzZ0_S |
| 279430U, // FCMGT_PPzZZ_D |
| 549829U, // FCMGT_PPzZZ_H |
| 803846U, // FCMGT_PPzZZ_S |
| 16U, // FCMGTv1i16rz |
| 16U, // FCMGTv1i32rz |
| 16U, // FCMGTv1i64rz |
| 323U, // FCMGTv2f32 |
| 323U, // FCMGTv2f64 |
| 16U, // FCMGTv2i32rz |
| 16U, // FCMGTv2i64rz |
| 323U, // FCMGTv4f16 |
| 323U, // FCMGTv4f32 |
| 16U, // FCMGTv4i16rz |
| 16U, // FCMGTv4i32rz |
| 323U, // FCMGTv8f16 |
| 16U, // FCMGTv8i16rz |
| 154157120U, // FCMLA_ZPmZZ_D |
| 53035969U, // FCMLA_ZPmZZ_H |
| 154419392U, // FCMLA_ZPmZZ_S |
| 17U, // FCMLA_ZZZI_H |
| 3689234U, // FCMLA_ZZZI_S |
| 3948931U, // FCMLAv2f32 |
| 3948931U, // FCMLAv2f64 |
| 3948931U, // FCMLAv4f16 |
| 53043587U, // FCMLAv4f16_indexed |
| 3948931U, // FCMLAv4f32 |
| 53043587U, // FCMLAv4f32_indexed |
| 3948931U, // FCMLAv8f16 |
| 53043587U, // FCMLAv8f16_indexed |
| 74630U, // FCMLE_PPzZ0_D |
| 2757U, // FCMLE_PPzZ0_H |
| 74758U, // FCMLE_PPzZ0_S |
| 16U, // FCMLEv1i16rz |
| 16U, // FCMLEv1i32rz |
| 16U, // FCMLEv1i64rz |
| 16U, // FCMLEv2i32rz |
| 16U, // FCMLEv2i64rz |
| 16U, // FCMLEv4i16rz |
| 16U, // FCMLEv4i32rz |
| 16U, // FCMLEv8i16rz |
| 74630U, // FCMLT_PPzZ0_D |
| 2757U, // FCMLT_PPzZ0_H |
| 74758U, // FCMLT_PPzZ0_S |
| 16U, // FCMLTv1i16rz |
| 16U, // FCMLTv1i32rz |
| 16U, // FCMLTv1i64rz |
| 16U, // FCMLTv2i32rz |
| 16U, // FCMLTv2i64rz |
| 16U, // FCMLTv4i16rz |
| 16U, // FCMLTv4i32rz |
| 16U, // FCMLTv8i16rz |
| 74630U, // FCMNE_PPzZ0_D |
| 2757U, // FCMNE_PPzZ0_H |
| 74758U, // FCMNE_PPzZ0_S |
| 279430U, // FCMNE_PPzZZ_D |
| 549829U, // FCMNE_PPzZZ_H |
| 803846U, // FCMNE_PPzZZ_S |
| 0U, // FCMPDri |
| 2U, // FCMPDrr |
| 0U, // FCMPEDri |
| 2U, // FCMPEDrr |
| 0U, // FCMPEHri |
| 2U, // FCMPEHrr |
| 0U, // FCMPESri |
| 2U, // FCMPESrr |
| 0U, // FCMPHri |
| 2U, // FCMPHrr |
| 0U, // FCMPSri |
| 2U, // FCMPSrr |
| 279430U, // FCMUO_PPzZZ_D |
| 549829U, // FCMUO_PPzZZ_H |
| 803846U, // FCMUO_PPzZZ_S |
| 2880U, // FCPY_ZPmI_D |
| 19U, // FCPY_ZPmI_H |
| 2880U, // FCPY_ZPmI_S |
| 1589507U, // FCSELDrrr |
| 1589507U, // FCSELHrrr |
| 1589507U, // FCSELSrrr |
| 2U, // FCVTASUWDr |
| 2U, // FCVTASUWHr |
| 2U, // FCVTASUWSr |
| 2U, // FCVTASUXDr |
| 2U, // FCVTASUXHr |
| 2U, // FCVTASUXSr |
| 2U, // FCVTASv1f16 |
| 2U, // FCVTASv1i32 |
| 2U, // FCVTASv1i64 |
| 2U, // FCVTASv2f32 |
| 2U, // FCVTASv2f64 |
| 2U, // FCVTASv4f16 |
| 2U, // FCVTASv4f32 |
| 2U, // FCVTASv8f16 |
| 2U, // FCVTAUUWDr |
| 2U, // FCVTAUUWHr |
| 2U, // FCVTAUUWSr |
| 2U, // FCVTAUUXDr |
| 2U, // FCVTAUUXHr |
| 2U, // FCVTAUUXSr |
| 2U, // FCVTAUv1f16 |
| 2U, // FCVTAUv1i32 |
| 2U, // FCVTAUv1i64 |
| 2U, // FCVTAUv2f32 |
| 2U, // FCVTAUv2f64 |
| 2U, // FCVTAUv4f16 |
| 2U, // FCVTAUv4f32 |
| 2U, // FCVTAUv8f16 |
| 2U, // FCVTDHr |
| 2U, // FCVTDSr |
| 2U, // FCVTHDr |
| 2U, // FCVTHSr |
| 0U, // FCVTLv2i32 |
| 20U, // FCVTLv4i16 |
| 0U, // FCVTLv4i32 |
| 21U, // FCVTLv8i16 |
| 2U, // FCVTMSUWDr |
| 2U, // FCVTMSUWHr |
| 2U, // FCVTMSUWSr |
| 2U, // FCVTMSUXDr |
| 2U, // FCVTMSUXHr |
| 2U, // FCVTMSUXSr |
| 2U, // FCVTMSv1f16 |
| 2U, // FCVTMSv1i32 |
| 2U, // FCVTMSv1i64 |
| 2U, // FCVTMSv2f32 |
| 2U, // FCVTMSv2f64 |
| 2U, // FCVTMSv4f16 |
| 2U, // FCVTMSv4f32 |
| 2U, // FCVTMSv8f16 |
| 2U, // FCVTMUUWDr |
| 2U, // FCVTMUUWHr |
| 2U, // FCVTMUUWSr |
| 2U, // FCVTMUUXDr |
| 2U, // FCVTMUUXHr |
| 2U, // FCVTMUUXSr |
| 2U, // FCVTMUv1f16 |
| 2U, // FCVTMUv1i32 |
| 2U, // FCVTMUv1i64 |
| 2U, // FCVTMUv2f32 |
| 2U, // FCVTMUv2f64 |
| 2U, // FCVTMUv4f16 |
| 2U, // FCVTMUv4f32 |
| 2U, // FCVTMUv8f16 |
| 2U, // FCVTNSUWDr |
| 2U, // FCVTNSUWHr |
| 2U, // FCVTNSUWSr |
| 2U, // FCVTNSUXDr |
| 2U, // FCVTNSUXHr |
| 2U, // FCVTNSUXSr |
| 2U, // FCVTNSv1f16 |
| 2U, // FCVTNSv1i32 |
| 2U, // FCVTNSv1i64 |
| 2U, // FCVTNSv2f32 |
| 2U, // FCVTNSv2f64 |
| 2U, // FCVTNSv4f16 |
| 2U, // FCVTNSv4f32 |
| 2U, // FCVTNSv8f16 |
| 2U, // FCVTNUUWDr |
| 2U, // FCVTNUUWHr |
| 2U, // FCVTNUUWSr |
| 2U, // FCVTNUUXDr |
| 2U, // FCVTNUUXHr |
| 2U, // FCVTNUUXSr |
| 2U, // FCVTNUv1f16 |
| 2U, // FCVTNUv1i32 |
| 2U, // FCVTNUv1i64 |
| 2U, // FCVTNUv2f32 |
| 2U, // FCVTNUv2f64 |
| 2U, // FCVTNUv4f16 |
| 2U, // FCVTNUv4f32 |
| 2U, // FCVTNUv8f16 |
| 0U, // FCVTNv2i32 |
| 0U, // FCVTNv4i16 |
| 22U, // FCVTNv4i32 |
| 0U, // FCVTNv8i16 |
| 2U, // FCVTPSUWDr |
| 2U, // FCVTPSUWHr |
| 2U, // FCVTPSUWSr |
| 2U, // FCVTPSUXDr |
| 2U, // FCVTPSUXHr |
| 2U, // FCVTPSUXSr |
| 2U, // FCVTPSv1f16 |
| 2U, // FCVTPSv1i32 |
| 2U, // FCVTPSv1i64 |
| 2U, // FCVTPSv2f32 |
| 2U, // FCVTPSv2f64 |
| 2U, // FCVTPSv4f16 |
| 2U, // FCVTPSv4f32 |
| 2U, // FCVTPSv8f16 |
| 2U, // FCVTPUUWDr |
| 2U, // FCVTPUUWHr |
| 2U, // FCVTPUUWSr |
| 2U, // FCVTPUUXDr |
| 2U, // FCVTPUUXHr |
| 2U, // FCVTPUUXSr |
| 2U, // FCVTPUv1f16 |
| 2U, // FCVTPUv1i32 |
| 2U, // FCVTPUv1i64 |
| 2U, // FCVTPUv2f32 |
| 2U, // FCVTPUv2f64 |
| 2U, // FCVTPUv4f16 |
| 2U, // FCVTPUv4f32 |
| 2U, // FCVTPUv8f16 |
| 2U, // FCVTSDr |
| 2U, // FCVTSHr |
| 2U, // FCVTXNv1i64 |
| 0U, // FCVTXNv2f32 |
| 22U, // FCVTXNv4f32 |
| 259U, // FCVTZSSWDri |
| 259U, // FCVTZSSWHri |
| 259U, // FCVTZSSWSri |
| 259U, // FCVTZSSXDri |
| 259U, // FCVTZSSXHri |
| 259U, // FCVTZSSXSri |
| 2U, // FCVTZSUWDr |
| 2U, // FCVTZSUWHr |
| 2U, // FCVTZSUWSr |
| 2U, // FCVTZSUXDr |
| 2U, // FCVTZSUXHr |
| 2U, // FCVTZSUXSr |
| 64U, // FCVTZS_ZPmZ_DtoD |
| 64U, // FCVTZS_ZPmZ_DtoS |
| 2944U, // FCVTZS_ZPmZ_HtoD |
| 129U, // FCVTZS_ZPmZ_HtoH |
| 2944U, // FCVTZS_ZPmZ_HtoS |
| 192U, // FCVTZS_ZPmZ_StoD |
| 192U, // FCVTZS_ZPmZ_StoS |
| 259U, // FCVTZSd |
| 259U, // FCVTZSh |
| 259U, // FCVTZSs |
| 2U, // FCVTZSv1f16 |
| 2U, // FCVTZSv1i32 |
| 2U, // FCVTZSv1i64 |
| 2U, // FCVTZSv2f32 |
| 2U, // FCVTZSv2f64 |
| 259U, // FCVTZSv2i32_shift |
| 259U, // FCVTZSv2i64_shift |
| 2U, // FCVTZSv4f16 |
| 2U, // FCVTZSv4f32 |
| 259U, // FCVTZSv4i16_shift |
| 259U, // FCVTZSv4i32_shift |
| 2U, // FCVTZSv8f16 |
| 259U, // FCVTZSv8i16_shift |
| 259U, // FCVTZUSWDri |
| 259U, // FCVTZUSWHri |
| 259U, // FCVTZUSWSri |
| 259U, // FCVTZUSXDri |
| 259U, // FCVTZUSXHri |
| 259U, // FCVTZUSXSri |
| 2U, // FCVTZUUWDr |
| 2U, // FCVTZUUWHr |
| 2U, // FCVTZUUWSr |
| 2U, // FCVTZUUXDr |
| 2U, // FCVTZUUXHr |
| 2U, // FCVTZUUXSr |
| 64U, // FCVTZU_ZPmZ_DtoD |
| 64U, // FCVTZU_ZPmZ_DtoS |
| 2944U, // FCVTZU_ZPmZ_HtoD |
| 129U, // FCVTZU_ZPmZ_HtoH |
| 2944U, // FCVTZU_ZPmZ_HtoS |
| 192U, // FCVTZU_ZPmZ_StoD |
| 192U, // FCVTZU_ZPmZ_StoS |
| 259U, // FCVTZUd |
| 259U, // FCVTZUh |
| 259U, // FCVTZUs |
| 2U, // FCVTZUv1f16 |
| 2U, // FCVTZUv1i32 |
| 2U, // FCVTZUv1i64 |
| 2U, // FCVTZUv2f32 |
| 2U, // FCVTZUv2f64 |
| 259U, // FCVTZUv2i32_shift |
| 259U, // FCVTZUv2i64_shift |
| 2U, // FCVTZUv4f16 |
| 2U, // FCVTZUv4f32 |
| 259U, // FCVTZUv4i16_shift |
| 259U, // FCVTZUv4i32_shift |
| 2U, // FCVTZUv8f16 |
| 259U, // FCVTZUv8i16_shift |
| 151U, // FCVT_ZPmZ_DtoH |
| 64U, // FCVT_ZPmZ_DtoS |
| 2944U, // FCVT_ZPmZ_HtoD |
| 2944U, // FCVT_ZPmZ_HtoS |
| 192U, // FCVT_ZPmZ_StoD |
| 146U, // FCVT_ZPmZ_StoH |
| 259U, // FDIVDrr |
| 259U, // FDIVHrr |
| 279424U, // FDIVR_ZPmZ_D |
| 549829U, // FDIVR_ZPmZ_H |
| 803840U, // FDIVR_ZPmZ_S |
| 259U, // FDIVSrr |
| 279424U, // FDIV_ZPmZ_D |
| 549829U, // FDIV_ZPmZ_H |
| 803840U, // FDIV_ZPmZ_S |
| 323U, // FDIVv2f32 |
| 323U, // FDIVv2f64 |
| 323U, // FDIVv4f16 |
| 323U, // FDIVv4f32 |
| 323U, // FDIVv8f16 |
| 0U, // FDUP_ZI_D |
| 0U, // FDUP_ZI_H |
| 0U, // FDUP_ZI_S |
| 2U, // FEXPA_ZZ_D |
| 0U, // FEXPA_ZZ_H |
| 2U, // FEXPA_ZZ_S |
| 2U, // FJCVTZS |
| 1065219U, // FMADDDrrr |
| 1065219U, // FMADDHrrr |
| 1065219U, // FMADDSrrr |
| 3162176U, // FMAD_ZPmZZ_D |
| 607169U, // FMAD_ZPmZZ_H |
| 3424448U, // FMAD_ZPmZZ_S |
| 259U, // FMAXDrr |
| 259U, // FMAXHrr |
| 259U, // FMAXNMDrr |
| 259U, // FMAXNMHrr |
| 323U, // FMAXNMPv2f32 |
| 323U, // FMAXNMPv2f64 |
| 2U, // FMAXNMPv2i16p |
| 2U, // FMAXNMPv2i32p |
| 2U, // FMAXNMPv2i64p |
| 323U, // FMAXNMPv4f16 |
| 323U, // FMAXNMPv4f32 |
| 323U, // FMAXNMPv8f16 |
| 259U, // FMAXNMSrr |
| 899U, // FMAXNMV_VPZ_D |
| 2243U, // FMAXNMV_VPZ_H |
| 1027U, // FMAXNMV_VPZ_S |
| 2U, // FMAXNMVv4i16v |
| 2U, // FMAXNMVv4i32v |
| 2U, // FMAXNMVv8i16v |
| 4211584U, // FMAXNM_ZPmI_D |
| 99269U, // FMAXNM_ZPmI_H |
| 4211712U, // FMAXNM_ZPmI_S |
| 279424U, // FMAXNM_ZPmZ_D |
| 549829U, // FMAXNM_ZPmZ_H |
| 803840U, // FMAXNM_ZPmZ_S |
| 323U, // FMAXNMv2f32 |
| 323U, // FMAXNMv2f64 |
| 323U, // FMAXNMv4f16 |
| 323U, // FMAXNMv4f32 |
| 323U, // FMAXNMv8f16 |
| 323U, // FMAXPv2f32 |
| 323U, // FMAXPv2f64 |
| 2U, // FMAXPv2i16p |
| 2U, // FMAXPv2i32p |
| 2U, // FMAXPv2i64p |
| 323U, // FMAXPv4f16 |
| 323U, // FMAXPv4f32 |
| 323U, // FMAXPv8f16 |
| 259U, // FMAXSrr |
| 899U, // FMAXV_VPZ_D |
| 2243U, // FMAXV_VPZ_H |
| 1027U, // FMAXV_VPZ_S |
| 2U, // FMAXVv4i16v |
| 2U, // FMAXVv4i32v |
| 2U, // FMAXVv8i16v |
| 4211584U, // FMAX_ZPmI_D |
| 99269U, // FMAX_ZPmI_H |
| 4211712U, // FMAX_ZPmI_S |
| 279424U, // FMAX_ZPmZ_D |
| 549829U, // FMAX_ZPmZ_H |
| 803840U, // FMAX_ZPmZ_S |
| 323U, // FMAXv2f32 |
| 323U, // FMAXv2f64 |
| 323U, // FMAXv4f16 |
| 323U, // FMAXv4f32 |
| 323U, // FMAXv8f16 |
| 259U, // FMINDrr |
| 259U, // FMINHrr |
| 259U, // FMINNMDrr |
| 259U, // FMINNMHrr |
| 323U, // FMINNMPv2f32 |
| 323U, // FMINNMPv2f64 |
| 2U, // FMINNMPv2i16p |
| 2U, // FMINNMPv2i32p |
| 2U, // FMINNMPv2i64p |
| 323U, // FMINNMPv4f16 |
| 323U, // FMINNMPv4f32 |
| 323U, // FMINNMPv8f16 |
| 259U, // FMINNMSrr |
| 899U, // FMINNMV_VPZ_D |
| 2243U, // FMINNMV_VPZ_H |
| 1027U, // FMINNMV_VPZ_S |
| 2U, // FMINNMVv4i16v |
| 2U, // FMINNMVv4i32v |
| 2U, // FMINNMVv8i16v |
| 4211584U, // FMINNM_ZPmI_D |
| 99269U, // FMINNM_ZPmI_H |
| 4211712U, // FMINNM_ZPmI_S |
| 279424U, // FMINNM_ZPmZ_D |
| 549829U, // FMINNM_ZPmZ_H |
| 803840U, // FMINNM_ZPmZ_S |
| 323U, // FMINNMv2f32 |
| 323U, // FMINNMv2f64 |
| 323U, // FMINNMv4f16 |
| 323U, // FMINNMv4f32 |
| 323U, // FMINNMv8f16 |
| 323U, // FMINPv2f32 |
| 323U, // FMINPv2f64 |
| 2U, // FMINPv2i16p |
| 2U, // FMINPv2i32p |
| 2U, // FMINPv2i64p |
| 323U, // FMINPv4f16 |
| 323U, // FMINPv4f32 |
| 323U, // FMINPv8f16 |
| 259U, // FMINSrr |
| 899U, // FMINV_VPZ_D |
| 2243U, // FMINV_VPZ_H |
| 1027U, // FMINV_VPZ_S |
| 2U, // FMINVv4i16v |
| 2U, // FMINVv4i32v |
| 2U, // FMINVv8i16v |
| 4211584U, // FMIN_ZPmI_D |
| 99269U, // FMIN_ZPmI_H |
| 4211712U, // FMIN_ZPmI_S |
| 279424U, // FMIN_ZPmZ_D |
| 549829U, // FMIN_ZPmZ_H |
| 803840U, // FMIN_ZPmZ_S |
| 323U, // FMINv2f32 |
| 323U, // FMINv2f64 |
| 323U, // FMINv4f16 |
| 323U, // FMINv4f32 |
| 323U, // FMINv8f16 |
| 3162176U, // FMLA_ZPmZZ_D |
| 607169U, // FMLA_ZPmZZ_H |
| 3424448U, // FMLA_ZPmZZ_S |
| 2839U, // FMLA_ZZZI_D |
| 0U, // FMLA_ZZZI_H |
| 2834U, // FMLA_ZZZI_S |
| 614787U, // FMLAv1i16_indexed |
| 614787U, // FMLAv1i32_indexed |
| 614787U, // FMLAv1i64_indexed |
| 387U, // FMLAv2f32 |
| 387U, // FMLAv2f64 |
| 614787U, // FMLAv2i32_indexed |
| 614787U, // FMLAv2i64_indexed |
| 387U, // FMLAv4f16 |
| 387U, // FMLAv4f32 |
| 614787U, // FMLAv4i16_indexed |
| 614787U, // FMLAv4i32_indexed |
| 387U, // FMLAv8f16 |
| 614787U, // FMLAv8i16_indexed |
| 3162176U, // FMLS_ZPmZZ_D |
| 607169U, // FMLS_ZPmZZ_H |
| 3424448U, // FMLS_ZPmZZ_S |
| 2839U, // FMLS_ZZZI_D |
| 0U, // FMLS_ZZZI_H |
| 2834U, // FMLS_ZZZI_S |
| 614787U, // FMLSv1i16_indexed |
| 614787U, // FMLSv1i32_indexed |
| 614787U, // FMLSv1i64_indexed |
| 387U, // FMLSv2f32 |
| 387U, // FMLSv2f64 |
| 614787U, // FMLSv2i32_indexed |
| 614787U, // FMLSv2i64_indexed |
| 387U, // FMLSv4f16 |
| 387U, // FMLSv4f32 |
| 614787U, // FMLSv4i16_indexed |
| 614787U, // FMLSv4i32_indexed |
| 387U, // FMLSv8f16 |
| 614787U, // FMLSv8i16_indexed |
| 0U, // FMOVD0 |
| 15U, // FMOVDXHighr |
| 2U, // FMOVDXr |
| 0U, // FMOVDi |
| 2U, // FMOVDr |
| 0U, // FMOVH0 |
| 2U, // FMOVHWr |
| 2U, // FMOVHXr |
| 0U, // FMOVHi |
| 2U, // FMOVHr |
| 0U, // FMOVS0 |
| 2U, // FMOVSWr |
| 0U, // FMOVSi |
| 2U, // FMOVSr |
| 2U, // FMOVWHr |
| 2U, // FMOVWSr |
| 2U, // FMOVXDHighr |
| 2U, // FMOVXDr |
| 2U, // FMOVXHr |
| 0U, // FMOVv2f32_ns |
| 0U, // FMOVv2f64_ns |
| 0U, // FMOVv4f16_ns |
| 0U, // FMOVv4f32_ns |
| 0U, // FMOVv8f16_ns |
| 3162176U, // FMSB_ZPmZZ_D |
| 607169U, // FMSB_ZPmZZ_H |
| 3424448U, // FMSB_ZPmZZ_S |
| 1065219U, // FMSUBDrrr |
| 1065219U, // FMSUBHrrr |
| 1065219U, // FMSUBSrrr |
| 259U, // FMULDrr |
| 259U, // FMULHrr |
| 259U, // FMULSrr |
| 259U, // FMULX16 |
| 259U, // FMULX32 |
| 259U, // FMULX64 |
| 279424U, // FMULX_ZPmZ_D |
| 549829U, // FMULX_ZPmZ_H |
| 803840U, // FMULX_ZPmZ_S |
| 106819U, // FMULXv1i16_indexed |
| 106819U, // FMULXv1i32_indexed |
| 106819U, // FMULXv1i64_indexed |
| 323U, // FMULXv2f32 |
| 323U, // FMULXv2f64 |
| 106819U, // FMULXv2i32_indexed |
| 106819U, // FMULXv2i64_indexed |
| 323U, // FMULXv4f16 |
| 323U, // FMULXv4f32 |
| 106819U, // FMULXv4i16_indexed |
| 106819U, // FMULXv4i32_indexed |
| 323U, // FMULXv8f16 |
| 106819U, // FMULXv8i16_indexed |
| 4473728U, // FMUL_ZPmI_D |
| 115653U, // FMUL_ZPmI_H |
| 4473856U, // FMUL_ZPmI_S |
| 279424U, // FMUL_ZPmZ_D |
| 549829U, // FMUL_ZPmZ_H |
| 803840U, // FMUL_ZPmZ_S |
| 107395U, // FMUL_ZZZI_D |
| 3013U, // FMUL_ZZZI_H |
| 107523U, // FMUL_ZZZI_S |
| 899U, // FMUL_ZZZ_D |
| 133U, // FMUL_ZZZ_H |
| 1027U, // FMUL_ZZZ_S |
| 106819U, // FMULv1i16_indexed |
| 106819U, // FMULv1i32_indexed |
| 106819U, // FMULv1i64_indexed |
| 323U, // FMULv2f32 |
| 323U, // FMULv2f64 |
| 106819U, // FMULv2i32_indexed |
| 106819U, // FMULv2i64_indexed |
| 323U, // FMULv4f16 |
| 323U, // FMULv4f32 |
| 106819U, // FMULv4i16_indexed |
| 106819U, // FMULv4i32_indexed |
| 323U, // FMULv8f16 |
| 106819U, // FMULv8i16_indexed |
| 2U, // FNEGDr |
| 2U, // FNEGHr |
| 2U, // FNEGSr |
| 64U, // FNEG_ZPmZ_D |
| 129U, // FNEG_ZPmZ_H |
| 192U, // FNEG_ZPmZ_S |
| 2U, // FNEGv2f32 |
| 2U, // FNEGv2f64 |
| 2U, // FNEGv4f16 |
| 2U, // FNEGv4f32 |
| 2U, // FNEGv8f16 |
| 1065219U, // FNMADDDrrr |
| 1065219U, // FNMADDHrrr |
| 1065219U, // FNMADDSrrr |
| 3162176U, // FNMAD_ZPmZZ_D |
| 607169U, // FNMAD_ZPmZZ_H |
| 3424448U, // FNMAD_ZPmZZ_S |
| 3162176U, // FNMLA_ZPmZZ_D |
| 607169U, // FNMLA_ZPmZZ_H |
| 3424448U, // FNMLA_ZPmZZ_S |
| 3162176U, // FNMLS_ZPmZZ_D |
| 607169U, // FNMLS_ZPmZZ_H |
| 3424448U, // FNMLS_ZPmZZ_S |
| 3162176U, // FNMSB_ZPmZZ_D |
| 607169U, // FNMSB_ZPmZZ_H |
| 3424448U, // FNMSB_ZPmZZ_S |
| 1065219U, // FNMSUBDrrr |
| 1065219U, // FNMSUBHrrr |
| 1065219U, // FNMSUBSrrr |
| 259U, // FNMULDrr |
| 259U, // FNMULHrr |
| 259U, // FNMULSrr |
| 2U, // FRECPE_ZZ_D |
| 0U, // FRECPE_ZZ_H |
| 2U, // FRECPE_ZZ_S |
| 2U, // FRECPEv1f16 |
| 2U, // FRECPEv1i32 |
| 2U, // FRECPEv1i64 |
| 2U, // FRECPEv2f32 |
| 2U, // FRECPEv2f64 |
| 2U, // FRECPEv4f16 |
| 2U, // FRECPEv4f32 |
| 2U, // FRECPEv8f16 |
| 259U, // FRECPS16 |
| 259U, // FRECPS32 |
| 259U, // FRECPS64 |
| 899U, // FRECPS_ZZZ_D |
| 133U, // FRECPS_ZZZ_H |
| 1027U, // FRECPS_ZZZ_S |
| 323U, // FRECPSv2f32 |
| 323U, // FRECPSv2f64 |
| 323U, // FRECPSv4f16 |
| 323U, // FRECPSv4f32 |
| 323U, // FRECPSv8f16 |
| 64U, // FRECPX_ZPmZ_D |
| 129U, // FRECPX_ZPmZ_H |
| 192U, // FRECPX_ZPmZ_S |
| 2U, // FRECPXv1f16 |
| 2U, // FRECPXv1i32 |
| 2U, // FRECPXv1i64 |
| 2U, // FRINTADr |
| 2U, // FRINTAHr |
| 2U, // FRINTASr |
| 64U, // FRINTA_ZPmZ_D |
| 129U, // FRINTA_ZPmZ_H |
| 192U, // FRINTA_ZPmZ_S |
| 2U, // FRINTAv2f32 |
| 2U, // FRINTAv2f64 |
| 2U, // FRINTAv4f16 |
| 2U, // FRINTAv4f32 |
| 2U, // FRINTAv8f16 |
| 2U, // FRINTIDr |
| 2U, // FRINTIHr |
| 2U, // FRINTISr |
| 64U, // FRINTI_ZPmZ_D |
| 129U, // FRINTI_ZPmZ_H |
| 192U, // FRINTI_ZPmZ_S |
| 2U, // FRINTIv2f32 |
| 2U, // FRINTIv2f64 |
| 2U, // FRINTIv4f16 |
| 2U, // FRINTIv4f32 |
| 2U, // FRINTIv8f16 |
| 2U, // FRINTMDr |
| 2U, // FRINTMHr |
| 2U, // FRINTMSr |
| 64U, // FRINTM_ZPmZ_D |
| 129U, // FRINTM_ZPmZ_H |
| 192U, // FRINTM_ZPmZ_S |
| 2U, // FRINTMv2f32 |
| 2U, // FRINTMv2f64 |
| 2U, // FRINTMv4f16 |
| 2U, // FRINTMv4f32 |
| 2U, // FRINTMv8f16 |
| 2U, // FRINTNDr |
| 2U, // FRINTNHr |
| 2U, // FRINTNSr |
| 64U, // FRINTN_ZPmZ_D |
| 129U, // FRINTN_ZPmZ_H |
| 192U, // FRINTN_ZPmZ_S |
| 2U, // FRINTNv2f32 |
| 2U, // FRINTNv2f64 |
| 2U, // FRINTNv4f16 |
| 2U, // FRINTNv4f32 |
| 2U, // FRINTNv8f16 |
| 2U, // FRINTPDr |
| 2U, // FRINTPHr |
| 2U, // FRINTPSr |
| 64U, // FRINTP_ZPmZ_D |
| 129U, // FRINTP_ZPmZ_H |
| 192U, // FRINTP_ZPmZ_S |
| 2U, // FRINTPv2f32 |
| 2U, // FRINTPv2f64 |
| 2U, // FRINTPv4f16 |
| 2U, // FRINTPv4f32 |
| 2U, // FRINTPv8f16 |
| 2U, // FRINTXDr |
| 2U, // FRINTXHr |
| 2U, // FRINTXSr |
| 64U, // FRINTX_ZPmZ_D |
| 129U, // FRINTX_ZPmZ_H |
| 192U, // FRINTX_ZPmZ_S |
| 2U, // FRINTXv2f32 |
| 2U, // FRINTXv2f64 |
| 2U, // FRINTXv4f16 |
| 2U, // FRINTXv4f32 |
| 2U, // FRINTXv8f16 |
| 2U, // FRINTZDr |
| 2U, // FRINTZHr |
| 2U, // FRINTZSr |
| 64U, // FRINTZ_ZPmZ_D |
| 129U, // FRINTZ_ZPmZ_H |
| 192U, // FRINTZ_ZPmZ_S |
| 2U, // FRINTZv2f32 |
| 2U, // FRINTZv2f64 |
| 2U, // FRINTZv4f16 |
| 2U, // FRINTZv4f32 |
| 2U, // FRINTZv8f16 |
| 2U, // FRSQRTE_ZZ_D |
| 0U, // FRSQRTE_ZZ_H |
| 2U, // FRSQRTE_ZZ_S |
| 2U, // FRSQRTEv1f16 |
| 2U, // FRSQRTEv1i32 |
| 2U, // FRSQRTEv1i64 |
| 2U, // FRSQRTEv2f32 |
| 2U, // FRSQRTEv2f64 |
| 2U, // FRSQRTEv4f16 |
| 2U, // FRSQRTEv4f32 |
| 2U, // FRSQRTEv8f16 |
| 259U, // FRSQRTS16 |
| 259U, // FRSQRTS32 |
| 259U, // FRSQRTS64 |
| 899U, // FRSQRTS_ZZZ_D |
| 133U, // FRSQRTS_ZZZ_H |
| 1027U, // FRSQRTS_ZZZ_S |
| 323U, // FRSQRTSv2f32 |
| 323U, // FRSQRTSv2f64 |
| 323U, // FRSQRTSv4f16 |
| 323U, // FRSQRTSv4f32 |
| 323U, // FRSQRTSv8f16 |
| 279424U, // FSCALE_ZPmZ_D |
| 549829U, // FSCALE_ZPmZ_H |
| 803840U, // FSCALE_ZPmZ_S |
| 2U, // FSQRTDr |
| 2U, // FSQRTHr |
| 2U, // FSQRTSr |
| 64U, // FSQRT_ZPmZ_D |
| 129U, // FSQRT_ZPmZ_H |
| 192U, // FSQRT_ZPmZ_S |
| 2U, // FSQRTv2f32 |
| 2U, // FSQRTv2f64 |
| 2U, // FSQRTv4f16 |
| 2U, // FSQRTv4f32 |
| 2U, // FSQRTv8f16 |
| 259U, // FSUBDrr |
| 259U, // FSUBHrr |
| 2376576U, // FSUBR_ZPmI_D |
| 66501U, // FSUBR_ZPmI_H |
| 2376704U, // FSUBR_ZPmI_S |
| 279424U, // FSUBR_ZPmZ_D |
| 549829U, // FSUBR_ZPmZ_H |
| 803840U, // FSUBR_ZPmZ_S |
| 259U, // FSUBSrr |
| 2376576U, // FSUB_ZPmI_D |
| 66501U, // FSUB_ZPmI_H |
| 2376704U, // FSUB_ZPmI_S |
| 279424U, // FSUB_ZPmZ_D |
| 549829U, // FSUB_ZPmZ_H |
| 803840U, // FSUB_ZPmZ_S |
| 899U, // FSUB_ZZZ_D |
| 133U, // FSUB_ZZZ_H |
| 1027U, // FSUB_ZZZ_S |
| 323U, // FSUBv2f32 |
| 323U, // FSUBv2f64 |
| 323U, // FSUBv4f16 |
| 323U, // FSUBv4f32 |
| 323U, // FSUBv8f16 |
| 1065859U, // FTMAD_ZZI_D |
| 33733U, // FTMAD_ZZI_H |
| 1065987U, // FTMAD_ZZI_S |
| 899U, // FTSMUL_ZZZ_D |
| 133U, // FTSMUL_ZZZ_H |
| 1027U, // FTSMUL_ZZZ_S |
| 899U, // FTSSEL_ZZZ_D |
| 133U, // FTSSEL_ZZZ_H |
| 1027U, // FTSSEL_ZZZ_S |
| 3085U, // GLD1B_D_IMM_REAL |
| 3139U, // GLD1B_D_REAL |
| 3203U, // GLD1B_D_SXTW_REAL |
| 3267U, // GLD1B_D_UXTW_REAL |
| 3085U, // GLD1B_S_IMM_REAL |
| 3331U, // GLD1B_S_SXTW_REAL |
| 3395U, // GLD1B_S_UXTW_REAL |
| 24U, // GLD1D_IMM_REAL |
| 3139U, // GLD1D_REAL |
| 3459U, // GLD1D_SCALED_REAL |
| 3203U, // GLD1D_SXTW_REAL |
| 3523U, // GLD1D_SXTW_SCALED_REAL |
| 3267U, // GLD1D_UXTW_REAL |
| 3587U, // GLD1D_UXTW_SCALED_REAL |
| 25U, // GLD1H_D_IMM_REAL |
| 3139U, // GLD1H_D_REAL |
| 3651U, // GLD1H_D_SCALED_REAL |
| 3203U, // GLD1H_D_SXTW_REAL |
| 3715U, // GLD1H_D_SXTW_SCALED_REAL |
| 3267U, // GLD1H_D_UXTW_REAL |
| 3779U, // GLD1H_D_UXTW_SCALED_REAL |
| 25U, // GLD1H_S_IMM_REAL |
| 3331U, // GLD1H_S_SXTW_REAL |
| 3843U, // GLD1H_S_SXTW_SCALED_REAL |
| 3395U, // GLD1H_S_UXTW_REAL |
| 3907U, // GLD1H_S_UXTW_SCALED_REAL |
| 3085U, // GLD1SB_D_IMM_REAL |
| 3139U, // GLD1SB_D_REAL |
| 3203U, // GLD1SB_D_SXTW_REAL |
| 3267U, // GLD1SB_D_UXTW_REAL |
| 3085U, // GLD1SB_S_IMM_REAL |
| 3331U, // GLD1SB_S_SXTW_REAL |
| 3395U, // GLD1SB_S_UXTW_REAL |
| 25U, // GLD1SH_D_IMM_REAL |
| 3139U, // GLD1SH_D_REAL |
| 3651U, // GLD1SH_D_SCALED_REAL |
| 3203U, // GLD1SH_D_SXTW_REAL |
| 3715U, // GLD1SH_D_SXTW_SCALED_REAL |
| 3267U, // GLD1SH_D_UXTW_REAL |
| 3779U, // GLD1SH_D_UXTW_SCALED_REAL |
| 25U, // GLD1SH_S_IMM_REAL |
| 3331U, // GLD1SH_S_SXTW_REAL |
| 3843U, // GLD1SH_S_SXTW_SCALED_REAL |
| 3395U, // GLD1SH_S_UXTW_REAL |
| 3907U, // GLD1SH_S_UXTW_SCALED_REAL |
| 26U, // GLD1SW_D_IMM_REAL |
| 3139U, // GLD1SW_D_REAL |
| 3971U, // GLD1SW_D_SCALED_REAL |
| 3203U, // GLD1SW_D_SXTW_REAL |
| 4035U, // GLD1SW_D_SXTW_SCALED_REAL |
| 3267U, // GLD1SW_D_UXTW_REAL |
| 4099U, // GLD1SW_D_UXTW_SCALED_REAL |
| 26U, // GLD1W_D_IMM_REAL |
| 3139U, // GLD1W_D_REAL |
| 3971U, // GLD1W_D_SCALED_REAL |
| 3203U, // GLD1W_D_SXTW_REAL |
| 4035U, // GLD1W_D_SXTW_SCALED_REAL |
| 3267U, // GLD1W_D_UXTW_REAL |
| 4099U, // GLD1W_D_UXTW_SCALED_REAL |
| 26U, // GLD1W_IMM_REAL |
| 3331U, // GLD1W_SXTW_REAL |
| 4163U, // GLD1W_SXTW_SCALED_REAL |
| 3395U, // GLD1W_UXTW_REAL |
| 4227U, // GLD1W_UXTW_SCALED_REAL |
| 3085U, // GLDFF1B_D_IMM_REAL |
| 3139U, // GLDFF1B_D_REAL |
| 3203U, // GLDFF1B_D_SXTW_REAL |
| 3267U, // GLDFF1B_D_UXTW_REAL |
| 3085U, // GLDFF1B_S_IMM_REAL |
| 3331U, // GLDFF1B_S_SXTW_REAL |
| 3395U, // GLDFF1B_S_UXTW_REAL |
| 24U, // GLDFF1D_IMM_REAL |
| 3139U, // GLDFF1D_REAL |
| 3459U, // GLDFF1D_SCALED_REAL |
| 3203U, // GLDFF1D_SXTW_REAL |
| 3523U, // GLDFF1D_SXTW_SCALED_REAL |
| 3267U, // GLDFF1D_UXTW_REAL |
| 3587U, // GLDFF1D_UXTW_SCALED_REAL |
| 25U, // GLDFF1H_D_IMM_REAL |
| 3139U, // GLDFF1H_D_REAL |
| 3651U, // GLDFF1H_D_SCALED_REAL |
| 3203U, // GLDFF1H_D_SXTW_REAL |
| 3715U, // GLDFF1H_D_SXTW_SCALED_REAL |
| 3267U, // GLDFF1H_D_UXTW_REAL |
| 3779U, // GLDFF1H_D_UXTW_SCALED_REAL |
| 25U, // GLDFF1H_S_IMM_REAL |
| 3331U, // GLDFF1H_S_SXTW_REAL |
| 3843U, // GLDFF1H_S_SXTW_SCALED_REAL |
| 3395U, // GLDFF1H_S_UXTW_REAL |
| 3907U, // GLDFF1H_S_UXTW_SCALED_REAL |
| 3085U, // GLDFF1SB_D_IMM_REAL |
| 3139U, // GLDFF1SB_D_REAL |
| 3203U, // GLDFF1SB_D_SXTW_REAL |
| 3267U, // GLDFF1SB_D_UXTW_REAL |
| 3085U, // GLDFF1SB_S_IMM_REAL |
| 3331U, // GLDFF1SB_S_SXTW_REAL |
| 3395U, // GLDFF1SB_S_UXTW_REAL |
| 25U, // GLDFF1SH_D_IMM_REAL |
| 3139U, // GLDFF1SH_D_REAL |
| 3651U, // GLDFF1SH_D_SCALED_REAL |
| 3203U, // GLDFF1SH_D_SXTW_REAL |
| 3715U, // GLDFF1SH_D_SXTW_SCALED_REAL |
| 3267U, // GLDFF1SH_D_UXTW_REAL |
| 3779U, // GLDFF1SH_D_UXTW_SCALED_REAL |
| 25U, // GLDFF1SH_S_IMM_REAL |
| 3331U, // GLDFF1SH_S_SXTW_REAL |
| 3843U, // GLDFF1SH_S_SXTW_SCALED_REAL |
| 3395U, // GLDFF1SH_S_UXTW_REAL |
| 3907U, // GLDFF1SH_S_UXTW_SCALED_REAL |
| 26U, // GLDFF1SW_D_IMM_REAL |
| 3139U, // GLDFF1SW_D_REAL |
| 3971U, // GLDFF1SW_D_SCALED_REAL |
| 3203U, // GLDFF1SW_D_SXTW_REAL |
| 4035U, // GLDFF1SW_D_SXTW_SCALED_REAL |
| 3267U, // GLDFF1SW_D_UXTW_REAL |
| 4099U, // GLDFF1SW_D_UXTW_SCALED_REAL |
| 26U, // GLDFF1W_D_IMM_REAL |
| 3139U, // GLDFF1W_D_REAL |
| 3971U, // GLDFF1W_D_SCALED_REAL |
| 3203U, // GLDFF1W_D_SXTW_REAL |
| 4035U, // GLDFF1W_D_SXTW_SCALED_REAL |
| 3267U, // GLDFF1W_D_UXTW_REAL |
| 4099U, // GLDFF1W_D_UXTW_SCALED_REAL |
| 26U, // GLDFF1W_IMM_REAL |
| 3331U, // GLDFF1W_SXTW_REAL |
| 4163U, // GLDFF1W_SXTW_SCALED_REAL |
| 3395U, // GLDFF1W_UXTW_REAL |
| 4227U, // GLDFF1W_UXTW_SCALED_REAL |
| 0U, // HINT |
| 0U, // HLT |
| 0U, // HVC |
| 0U, // INCB_XPiI |
| 0U, // INCD_XPiI |
| 0U, // INCD_ZPiI |
| 0U, // INCH_XPiI |
| 0U, // INCH_ZPiI |
| 2U, // INCP_XP_B |
| 2U, // INCP_XP_D |
| 2U, // INCP_XP_H |
| 2U, // INCP_XP_S |
| 2U, // INCP_ZP_D |
| 0U, // INCP_ZP_H |
| 2U, // INCP_ZP_S |
| 0U, // INCW_XPiI |
| 0U, // INCW_ZPiI |
| 259U, // INDEX_II_B |
| 259U, // INDEX_II_D |
| 8U, // INDEX_II_H |
| 259U, // INDEX_II_S |
| 259U, // INDEX_IR_B |
| 259U, // INDEX_IR_D |
| 8U, // INDEX_IR_H |
| 259U, // INDEX_IR_S |
| 259U, // INDEX_RI_B |
| 259U, // INDEX_RI_D |
| 8U, // INDEX_RI_H |
| 259U, // INDEX_RI_S |
| 259U, // INDEX_RR_B |
| 259U, // INDEX_RR_D |
| 8U, // INDEX_RR_H |
| 259U, // INDEX_RR_S |
| 2U, // INSR_ZR_B |
| 2U, // INSR_ZR_D |
| 0U, // INSR_ZR_H |
| 2U, // INSR_ZR_S |
| 2U, // INSR_ZV_B |
| 2U, // INSR_ZV_D |
| 0U, // INSR_ZV_H |
| 2U, // INSR_ZV_S |
| 2U, // INSvi16gpr |
| 0U, // INSvi16lane |
| 2U, // INSvi32gpr |
| 0U, // INSvi32lane |
| 2U, // INSvi64gpr |
| 0U, // INSvi64lane |
| 2U, // INSvi8gpr |
| 0U, // INSvi8lane |
| 0U, // ISB |
| 835U, // LASTA_RPZ_B |
| 899U, // LASTA_RPZ_D |
| 2243U, // LASTA_RPZ_H |
| 1027U, // LASTA_RPZ_S |
| 835U, // LASTA_VPZ_B |
| 899U, // LASTA_VPZ_D |
| 2243U, // LASTA_VPZ_H |
| 1027U, // LASTA_VPZ_S |
| 835U, // LASTB_RPZ_B |
| 899U, // LASTB_RPZ_D |
| 2243U, // LASTB_RPZ_H |
| 1027U, // LASTB_RPZ_S |
| 835U, // LASTB_VPZ_B |
| 899U, // LASTB_VPZ_D |
| 2243U, // LASTB_VPZ_H |
| 1027U, // LASTB_VPZ_S |
| 4291U, // LD1B |
| 4291U, // LD1B_D |
| 125187U, // LD1B_D_IMM_REAL |
| 4291U, // LD1B_H |
| 125187U, // LD1B_H_IMM_REAL |
| 125187U, // LD1B_IMM_REAL |
| 4291U, // LD1B_S |
| 125187U, // LD1B_S_IMM_REAL |
| 4355U, // LD1D |
| 125187U, // LD1D_IMM_REAL |
| 0U, // LD1Fourv16b |
| 0U, // LD1Fourv16b_POST |
| 0U, // LD1Fourv1d |
| 0U, // LD1Fourv1d_POST |
| 0U, // LD1Fourv2d |
| 0U, // LD1Fourv2d_POST |
| 0U, // LD1Fourv2s |
| 0U, // LD1Fourv2s_POST |
| 0U, // LD1Fourv4h |
| 0U, // LD1Fourv4h_POST |
| 0U, // LD1Fourv4s |
| 0U, // LD1Fourv4s_POST |
| 0U, // LD1Fourv8b |
| 0U, // LD1Fourv8b_POST |
| 0U, // LD1Fourv8h |
| 0U, // LD1Fourv8h_POST |
| 4419U, // LD1H |
| 4419U, // LD1H_D |
| 125187U, // LD1H_D_IMM_REAL |
| 125187U, // LD1H_IMM_REAL |
| 4419U, // LD1H_S |
| 125187U, // LD1H_S_IMM_REAL |
| 0U, // LD1Onev16b |
| 0U, // LD1Onev16b_POST |
| 0U, // LD1Onev1d |
| 0U, // LD1Onev1d_POST |
| 0U, // LD1Onev2d |
| 0U, // LD1Onev2d_POST |
| 0U, // LD1Onev2s |
| 0U, // LD1Onev2s_POST |
| 0U, // LD1Onev4h |
| 0U, // LD1Onev4h_POST |
| 0U, // LD1Onev4s |
| 0U, // LD1Onev4s_POST |
| 0U, // LD1Onev8b |
| 0U, // LD1Onev8b_POST |
| 0U, // LD1Onev8h |
| 0U, // LD1Onev8h_POST |
| 51459U, // LD1RB_D_IMM |
| 51459U, // LD1RB_H_IMM |
| 51459U, // LD1RB_IMM |
| 51459U, // LD1RB_S_IMM |
| 53635U, // LD1RD_IMM |
| 53699U, // LD1RH_D_IMM |
| 53699U, // LD1RH_IMM |
| 53699U, // LD1RH_S_IMM |
| 4291U, // LD1RQ_B |
| 4611U, // LD1RQ_B_IMM |
| 4355U, // LD1RQ_D |
| 4611U, // LD1RQ_D_IMM |
| 4419U, // LD1RQ_H |
| 4611U, // LD1RQ_H_IMM |
| 4675U, // LD1RQ_W |
| 4611U, // LD1RQ_W_IMM |
| 51459U, // LD1RSB_D_IMM |
| 51459U, // LD1RSB_H_IMM |
| 51459U, // LD1RSB_S_IMM |
| 53699U, // LD1RSH_D_IMM |
| 53699U, // LD1RSH_S_IMM |
| 53891U, // LD1RSW_IMM |
| 53891U, // LD1RW_D_IMM |
| 53891U, // LD1RW_IMM |
| 0U, // LD1Rv16b |
| 0U, // LD1Rv16b_POST |
| 0U, // LD1Rv1d |
| 0U, // LD1Rv1d_POST |
| 0U, // LD1Rv2d |
| 0U, // LD1Rv2d_POST |
| 0U, // LD1Rv2s |
| 0U, // LD1Rv2s_POST |
| 0U, // LD1Rv4h |
| 0U, // LD1Rv4h_POST |
| 0U, // LD1Rv4s |
| 0U, // LD1Rv4s_POST |
| 0U, // LD1Rv8b |
| 0U, // LD1Rv8b_POST |
| 0U, // LD1Rv8h |
| 0U, // LD1Rv8h_POST |
| 4291U, // LD1SB_D |
| 125187U, // LD1SB_D_IMM_REAL |
| 4291U, // LD1SB_H |
| 125187U, // LD1SB_H_IMM_REAL |
| 4291U, // LD1SB_S |
| 125187U, // LD1SB_S_IMM_REAL |
| 4419U, // LD1SH_D |
| 125187U, // LD1SH_D_IMM_REAL |
| 4419U, // LD1SH_S |
| 125187U, // LD1SH_S_IMM_REAL |
| 4675U, // LD1SW_D |
| 125187U, // LD1SW_D_IMM_REAL |
| 0U, // LD1Threev16b |
| 0U, // LD1Threev16b_POST |
| 0U, // LD1Threev1d |
| 0U, // LD1Threev1d_POST |
| 0U, // LD1Threev2d |
| 0U, // LD1Threev2d_POST |
| 0U, // LD1Threev2s |
| 0U, // LD1Threev2s_POST |
| 0U, // LD1Threev4h |
| 0U, // LD1Threev4h_POST |
| 0U, // LD1Threev4s |
| 0U, // LD1Threev4s_POST |
| 0U, // LD1Threev8b |
| 0U, // LD1Threev8b_POST |
| 0U, // LD1Threev8h |
| 0U, // LD1Threev8h_POST |
| 0U, // LD1Twov16b |
| 0U, // LD1Twov16b_POST |
| 0U, // LD1Twov1d |
| 0U, // LD1Twov1d_POST |
| 0U, // LD1Twov2d |
| 0U, // LD1Twov2d_POST |
| 0U, // LD1Twov2s |
| 0U, // LD1Twov2s_POST |
| 0U, // LD1Twov4h |
| 0U, // LD1Twov4h_POST |
| 0U, // LD1Twov4s |
| 0U, // LD1Twov4s_POST |
| 0U, // LD1Twov8b |
| 0U, // LD1Twov8b_POST |
| 0U, // LD1Twov8h |
| 0U, // LD1Twov8h_POST |
| 4675U, // LD1W |
| 4675U, // LD1W_D |
| 125187U, // LD1W_D_IMM_REAL |
| 125187U, // LD1W_IMM_REAL |
| 0U, // LD1i16 |
| 0U, // LD1i16_POST |
| 0U, // LD1i32 |
| 0U, // LD1i32_POST |
| 0U, // LD1i64 |
| 0U, // LD1i64_POST |
| 0U, // LD1i8 |
| 0U, // LD1i8_POST |
| 4291U, // LD2B |
| 127427U, // LD2B_IMM |
| 4355U, // LD2D |
| 127427U, // LD2D_IMM |
| 4419U, // LD2H |
| 127427U, // LD2H_IMM |
| 0U, // LD2Rv16b |
| 0U, // LD2Rv16b_POST |
| 0U, // LD2Rv1d |
| 0U, // LD2Rv1d_POST |
| 0U, // LD2Rv2d |
| 0U, // LD2Rv2d_POST |
| 0U, // LD2Rv2s |
| 0U, // LD2Rv2s_POST |
| 0U, // LD2Rv4h |
| 0U, // LD2Rv4h_POST |
| 0U, // LD2Rv4s |
| 0U, // LD2Rv4s_POST |
| 0U, // LD2Rv8b |
| 0U, // LD2Rv8b_POST |
| 0U, // LD2Rv8h |
| 0U, // LD2Rv8h_POST |
| 0U, // LD2Twov16b |
| 0U, // LD2Twov16b_POST |
| 0U, // LD2Twov2d |
| 0U, // LD2Twov2d_POST |
| 0U, // LD2Twov2s |
| 0U, // LD2Twov2s_POST |
| 0U, // LD2Twov4h |
| 0U, // LD2Twov4h_POST |
| 0U, // LD2Twov4s |
| 0U, // LD2Twov4s_POST |
| 0U, // LD2Twov8b |
| 0U, // LD2Twov8b_POST |
| 0U, // LD2Twov8h |
| 0U, // LD2Twov8h_POST |
| 4675U, // LD2W |
| 127427U, // LD2W_IMM |
| 0U, // LD2i16 |
| 0U, // LD2i16_POST |
| 0U, // LD2i32 |
| 0U, // LD2i32_POST |
| 0U, // LD2i64 |
| 0U, // LD2i64_POST |
| 0U, // LD2i8 |
| 0U, // LD2i8_POST |
| 4291U, // LD3B |
| 4803U, // LD3B_IMM |
| 4355U, // LD3D |
| 4803U, // LD3D_IMM |
| 4419U, // LD3H |
| 4803U, // LD3H_IMM |
| 0U, // LD3Rv16b |
| 0U, // LD3Rv16b_POST |
| 0U, // LD3Rv1d |
| 0U, // LD3Rv1d_POST |
| 0U, // LD3Rv2d |
| 0U, // LD3Rv2d_POST |
| 0U, // LD3Rv2s |
| 0U, // LD3Rv2s_POST |
| 0U, // LD3Rv4h |
| 0U, // LD3Rv4h_POST |
| 0U, // LD3Rv4s |
| 0U, // LD3Rv4s_POST |
| 0U, // LD3Rv8b |
| 0U, // LD3Rv8b_POST |
| 0U, // LD3Rv8h |
| 0U, // LD3Rv8h_POST |
| 0U, // LD3Threev16b |
| 0U, // LD3Threev16b_POST |
| 0U, // LD3Threev2d |
| 0U, // LD3Threev2d_POST |
| 0U, // LD3Threev2s |
| 0U, // LD3Threev2s_POST |
| 0U, // LD3Threev4h |
| 0U, // LD3Threev4h_POST |
| 0U, // LD3Threev4s |
| 0U, // LD3Threev4s_POST |
| 0U, // LD3Threev8b |
| 0U, // LD3Threev8b_POST |
| 0U, // LD3Threev8h |
| 0U, // LD3Threev8h_POST |
| 4675U, // LD3W |
| 4803U, // LD3W_IMM |
| 0U, // LD3i16 |
| 0U, // LD3i16_POST |
| 0U, // LD3i32 |
| 0U, // LD3i32_POST |
| 0U, // LD3i64 |
| 0U, // LD3i64_POST |
| 0U, // LD3i8 |
| 0U, // LD3i8_POST |
| 4291U, // LD4B |
| 127619U, // LD4B_IMM |
| 4355U, // LD4D |
| 127619U, // LD4D_IMM |
| 0U, // LD4Fourv16b |
| 0U, // LD4Fourv16b_POST |
| 0U, // LD4Fourv2d |
| 0U, // LD4Fourv2d_POST |
| 0U, // LD4Fourv2s |
| 0U, // LD4Fourv2s_POST |
| 0U, // LD4Fourv4h |
| 0U, // LD4Fourv4h_POST |
| 0U, // LD4Fourv4s |
| 0U, // LD4Fourv4s_POST |
| 0U, // LD4Fourv8b |
| 0U, // LD4Fourv8b_POST |
| 0U, // LD4Fourv8h |
| 0U, // LD4Fourv8h_POST |
| 4419U, // LD4H |
| 127619U, // LD4H_IMM |
| 0U, // LD4Rv16b |
| 0U, // LD4Rv16b_POST |
| 0U, // LD4Rv1d |
| 0U, // LD4Rv1d_POST |
| 0U, // LD4Rv2d |
| 0U, // LD4Rv2d_POST |
| 0U, // LD4Rv2s |
| 0U, // LD4Rv2s_POST |
| 0U, // LD4Rv4h |
| 0U, // LD4Rv4h_POST |
| 0U, // LD4Rv4s |
| 0U, // LD4Rv4s_POST |
| 0U, // LD4Rv8b |
| 0U, // LD4Rv8b_POST |
| 0U, // LD4Rv8h |
| 0U, // LD4Rv8h_POST |
| 4675U, // LD4W |
| 127619U, // LD4W_IMM |
| 0U, // LD4i16 |
| 0U, // LD4i16_POST |
| 0U, // LD4i32 |
| 0U, // LD4i32_POST |
| 0U, // LD4i64 |
| 0U, // LD4i64_POST |
| 0U, // LD4i8 |
| 0U, // LD4i8_POST |
| 0U, // LDADDAB |
| 0U, // LDADDAH |
| 0U, // LDADDALB |
| 0U, // LDADDALH |
| 0U, // LDADDALW |
| 0U, // LDADDALX |
| 0U, // LDADDAW |
| 0U, // LDADDAX |
| 0U, // LDADDB |
| 0U, // LDADDH |
| 0U, // LDADDLB |
| 0U, // LDADDLH |
| 0U, // LDADDLW |
| 0U, // LDADDLX |
| 0U, // LDADDW |
| 0U, // LDADDX |
| 27U, // LDAPRB |
| 27U, // LDAPRH |
| 27U, // LDAPRW |
| 27U, // LDAPRX |
| 49411U, // LDAPURBi |
| 49411U, // LDAPURHi |
| 49411U, // LDAPURSBWi |
| 49411U, // LDAPURSBXi |
| 49411U, // LDAPURSHWi |
| 49411U, // LDAPURSHXi |
| 49411U, // LDAPURSWi |
| 49411U, // LDAPURXi |
| 49411U, // LDAPURi |
| 27U, // LDARB |
| 27U, // LDARH |
| 27U, // LDARW |
| 27U, // LDARX |
| 49417U, // LDAXPW |
| 49417U, // LDAXPX |
| 27U, // LDAXRB |
| 27U, // LDAXRH |
| 27U, // LDAXRW |
| 27U, // LDAXRX |
| 0U, // LDCLRAB |
| 0U, // LDCLRAH |
| 0U, // LDCLRALB |
| 0U, // LDCLRALH |
| 0U, // LDCLRALW |
| 0U, // LDCLRALX |
| 0U, // LDCLRAW |
| 0U, // LDCLRAX |
| 0U, // LDCLRB |
| 0U, // LDCLRH |
| 0U, // LDCLRLB |
| 0U, // LDCLRLH |
| 0U, // LDCLRLW |
| 0U, // LDCLRLX |
| 0U, // LDCLRW |
| 0U, // LDCLRX |
| 0U, // LDEORAB |
| 0U, // LDEORAH |
| 0U, // LDEORALB |
| 0U, // LDEORALH |
| 0U, // LDEORALW |
| 0U, // LDEORALX |
| 0U, // LDEORAW |
| 0U, // LDEORAX |
| 0U, // LDEORB |
| 0U, // LDEORH |
| 0U, // LDEORLB |
| 0U, // LDEORLH |
| 0U, // LDEORLW |
| 0U, // LDEORLX |
| 0U, // LDEORW |
| 0U, // LDEORX |
| 4291U, // LDFF1B_D_REAL |
| 4291U, // LDFF1B_H_REAL |
| 4291U, // LDFF1B_REAL |
| 4291U, // LDFF1B_S_REAL |
| 4355U, // LDFF1D_REAL |
| 4419U, // LDFF1H_D_REAL |
| 4419U, // LDFF1H_REAL |
| 4419U, // LDFF1H_S_REAL |
| 4291U, // LDFF1SB_D_REAL |
| 4291U, // LDFF1SB_H_REAL |
| 4291U, // LDFF1SB_S_REAL |
| 4419U, // LDFF1SH_D_REAL |
| 4419U, // LDFF1SH_S_REAL |
| 4675U, // LDFF1SW_D_REAL |
| 4675U, // LDFF1W_D_REAL |
| 4675U, // LDFF1W_REAL |
| 27U, // LDLARB |
| 27U, // LDLARH |
| 27U, // LDLARW |
| 27U, // LDLARX |
| 125187U, // LDNF1B_D_IMM_REAL |
| 125187U, // LDNF1B_H_IMM_REAL |
| 125187U, // LDNF1B_IMM_REAL |
| 125187U, // LDNF1B_S_IMM_REAL |
| 125187U, // LDNF1D_IMM_REAL |
| 125187U, // LDNF1H_D_IMM_REAL |
| 125187U, // LDNF1H_IMM_REAL |
| 125187U, // LDNF1H_S_IMM_REAL |
| 125187U, // LDNF1SB_D_IMM_REAL |
| 125187U, // LDNF1SB_H_IMM_REAL |
| 125187U, // LDNF1SB_S_IMM_REAL |
| 125187U, // LDNF1SH_D_IMM_REAL |
| 125187U, // LDNF1SH_S_IMM_REAL |
| 125187U, // LDNF1SW_D_IMM_REAL |
| 125187U, // LDNF1W_D_IMM_REAL |
| 125187U, // LDNF1W_IMM_REAL |
| 4735241U, // LDNPDi |
| 4997385U, // LDNPQi |
| 5259529U, // LDNPSi |
| 5259529U, // LDNPWi |
| 4735241U, // LDNPXi |
| 125187U, // LDNT1B_ZRI |
| 4291U, // LDNT1B_ZRR |
| 125187U, // LDNT1D_ZRI |
| 4355U, // LDNT1D_ZRR |
| 125187U, // LDNT1H_ZRI |
| 4419U, // LDNT1H_ZRR |
| 125187U, // LDNT1W_ZRI |
| 4675U, // LDNT1W_ZRR |
| 4735241U, // LDPDi |
| 5638409U, // LDPDpost |
| 72632585U, // LDPDpre |
| 4997385U, // LDPQi |
| 5900553U, // LDPQpost |
| 72894729U, // LDPQpre |
| 5259529U, // LDPSWi |
| 6162697U, // LDPSWpost |
| 73156873U, // LDPSWpre |
| 5259529U, // LDPSi |
| 6162697U, // LDPSpost |
| 73156873U, // LDPSpre |
| 5259529U, // LDPWi |
| 6162697U, // LDPWpost |
| 73156873U, // LDPWpre |
| 4735241U, // LDPXi |
| 5638409U, // LDPXpost |
| 72632585U, // LDPXpre |
| 4867U, // LDRAAindexed |
| 143747U, // LDRAAwriteback |
| 4867U, // LDRABindexed |
| 143747U, // LDRABwriteback |
| 28U, // LDRBBpost |
| 141571U, // LDRBBpre |
| 6308099U, // LDRBBroW |
| 6570243U, // LDRBBroX |
| 4931U, // LDRBBui |
| 28U, // LDRBpost |
| 141571U, // LDRBpre |
| 6308099U, // LDRBroW |
| 6570243U, // LDRBroX |
| 4931U, // LDRBui |
| 0U, // LDRDl |
| 28U, // LDRDpost |
| 141571U, // LDRDpre |
| 6832387U, // LDRDroW |
| 7094531U, // LDRDroX |
| 4995U, // LDRDui |
| 28U, // LDRHHpost |
| 141571U, // LDRHHpre |
| 7356675U, // LDRHHroW |
| 7618819U, // LDRHHroX |
| 5059U, // LDRHHui |
| 28U, // LDRHpost |
| 141571U, // LDRHpre |
| 7356675U, // LDRHroW |
| 7618819U, // LDRHroX |
| 5059U, // LDRHui |
| 0U, // LDRQl |
| 28U, // LDRQpost |
| 141571U, // LDRQpre |
| 7880963U, // LDRQroW |
| 8143107U, // LDRQroX |
| 5123U, // LDRQui |
| 28U, // LDRSBWpost |
| 141571U, // LDRSBWpre |
| 6308099U, // LDRSBWroW |
| 6570243U, // LDRSBWroX |
| 4931U, // LDRSBWui |
| 28U, // LDRSBXpost |
| 141571U, // LDRSBXpre |
| 6308099U, // LDRSBXroW |
| 6570243U, // LDRSBXroX |
| 4931U, // LDRSBXui |
| 28U, // LDRSHWpost |
| 141571U, // LDRSHWpre |
| 7356675U, // LDRSHWroW |
| 7618819U, // LDRSHWroX |
| 5059U, // LDRSHWui |
| 28U, // LDRSHXpost |
| 141571U, // LDRSHXpre |
| 7356675U, // LDRSHXroW |
| 7618819U, // LDRSHXroX |
| 5059U, // LDRSHXui |
| 0U, // LDRSWl |
| 28U, // LDRSWpost |
| 141571U, // LDRSWpre |
| 8405251U, // LDRSWroW |
| 8667395U, // LDRSWroX |
| 5187U, // LDRSWui |
| 0U, // LDRSl |
| 28U, // LDRSpost |
| 141571U, // LDRSpre |
| 8405251U, // LDRSroW |
| 8667395U, // LDRSroX |
| 5187U, // LDRSui |
| 0U, // LDRWl |
| 28U, // LDRWpost |
| 141571U, // LDRWpre |
| 8405251U, // LDRWroW |
| 8667395U, // LDRWroX |
| 5187U, // LDRWui |
| 0U, // LDRXl |
| 28U, // LDRXpost |
| 141571U, // LDRXpre |
| 6832387U, // LDRXroW |
| 7094531U, // LDRXroX |
| 4995U, // LDRXui |
| 123139U, // LDR_PXI |
| 123139U, // LDR_ZXI |
| 0U, // LDSETAB |
| 0U, // LDSETAH |
| 0U, // LDSETALB |
| 0U, // LDSETALH |
| 0U, // LDSETALW |
| 0U, // LDSETALX |
| 0U, // LDSETAW |
| 0U, // LDSETAX |
| 0U, // LDSETB |
| 0U, // LDSETH |
| 0U, // LDSETLB |
| 0U, // LDSETLH |
| 0U, // LDSETLW |
| 0U, // LDSETLX |
| 0U, // LDSETW |
| 0U, // LDSETX |
| 0U, // LDSMAXAB |
| 0U, // LDSMAXAH |
| 0U, // LDSMAXALB |
| 0U, // LDSMAXALH |
| 0U, // LDSMAXALW |
| 0U, // LDSMAXALX |
| 0U, // LDSMAXAW |
| 0U, // LDSMAXAX |
| 0U, // LDSMAXB |
| 0U, // LDSMAXH |
| 0U, // LDSMAXLB |
| 0U, // LDSMAXLH |
| 0U, // LDSMAXLW |
| 0U, // LDSMAXLX |
| 0U, // LDSMAXW |
| 0U, // LDSMAXX |
| 0U, // LDSMINAB |
| 0U, // LDSMINAH |
| 0U, // LDSMINALB |
| 0U, // LDSMINALH |
| 0U, // LDSMINALW |
| 0U, // LDSMINALX |
| 0U, // LDSMINAW |
| 0U, // LDSMINAX |
| 0U, // LDSMINB |
| 0U, // LDSMINH |
| 0U, // LDSMINLB |
| 0U, // LDSMINLH |
| 0U, // LDSMINLW |
| 0U, // LDSMINLX |
| 0U, // LDSMINW |
| 0U, // LDSMINX |
| 49411U, // LDTRBi |
| 49411U, // LDTRHi |
| 49411U, // LDTRSBWi |
| 49411U, // LDTRSBXi |
| 49411U, // LDTRSHWi |
| 49411U, // LDTRSHXi |
| 49411U, // LDTRSWi |
| 49411U, // LDTRWi |
| 49411U, // LDTRXi |
| 0U, // LDUMAXAB |
| 0U, // LDUMAXAH |
| 0U, // LDUMAXALB |
| 0U, // LDUMAXALH |
| 0U, // LDUMAXALW |
| 0U, // LDUMAXALX |
| 0U, // LDUMAXAW |
| 0U, // LDUMAXAX |
| 0U, // LDUMAXB |
| 0U, // LDUMAXH |
| 0U, // LDUMAXLB |
| 0U, // LDUMAXLH |
| 0U, // LDUMAXLW |
| 0U, // LDUMAXLX |
| 0U, // LDUMAXW |
| 0U, // LDUMAXX |
| 0U, // LDUMINAB |
| 0U, // LDUMINAH |
| 0U, // LDUMINALB |
| 0U, // LDUMINALH |
| 0U, // LDUMINALW |
| 0U, // LDUMINALX |
| 0U, // LDUMINAW |
| 0U, // LDUMINAX |
| 0U, // LDUMINB |
| 0U, // LDUMINH |
| 0U, // LDUMINLB |
| 0U, // LDUMINLH |
| 0U, // LDUMINLW |
| 0U, // LDUMINLX |
| 0U, // LDUMINW |
| 0U, // LDUMINX |
| 49411U, // LDURBBi |
| 49411U, // LDURBi |
| 49411U, // LDURDi |
| 49411U, // LDURHHi |
| 49411U, // LDURHi |
| 49411U, // LDURQi |
| 49411U, // LDURSBWi |
| 49411U, // LDURSBXi |
| 49411U, // LDURSHWi |
| 49411U, // LDURSHXi |
| 49411U, // LDURSWi |
| 49411U, // LDURSi |
| 49411U, // LDURWi |
| 49411U, // LDURXi |
| 49417U, // LDXPW |
| 49417U, // LDXPX |
| 27U, // LDXRB |
| 27U, // LDXRH |
| 27U, // LDXRW |
| 27U, // LDXRX |
| 0U, // LOADgot |
| 17216U, // LSLR_ZPmZ_B |
| 279424U, // LSLR_ZPmZ_D |
| 549829U, // LSLR_ZPmZ_H |
| 803840U, // LSLR_ZPmZ_S |
| 259U, // LSLVWr |
| 259U, // LSLVXr |
| 279360U, // LSL_WIDE_ZPmZ_B |
| 41925U, // LSL_WIDE_ZPmZ_H |
| 279552U, // LSL_WIDE_ZPmZ_S |
| 899U, // LSL_WIDE_ZZZ_B |
| 7U, // LSL_WIDE_ZZZ_H |
| 899U, // LSL_WIDE_ZZZ_S |
| 1065792U, // LSL_ZPmI_B |
| 1065856U, // LSL_ZPmI_D |
| 33733U, // LSL_ZPmI_H |
| 1065984U, // LSL_ZPmI_S |
| 17216U, // LSL_ZPmZ_B |
| 279424U, // LSL_ZPmZ_D |
| 549829U, // LSL_ZPmZ_H |
| 803840U, // LSL_ZPmZ_S |
| 259U, // LSL_ZZI_B |
| 259U, // LSL_ZZI_D |
| 8U, // LSL_ZZI_H |
| 259U, // LSL_ZZI_S |
| 17216U, // LSRR_ZPmZ_B |
| 279424U, // LSRR_ZPmZ_D |
| 549829U, // LSRR_ZPmZ_H |
| 803840U, // LSRR_ZPmZ_S |
| 259U, // LSRVWr |
| 259U, // LSRVXr |
| 279360U, // LSR_WIDE_ZPmZ_B |
| 41925U, // LSR_WIDE_ZPmZ_H |
| 279552U, // LSR_WIDE_ZPmZ_S |
| 899U, // LSR_WIDE_ZZZ_B |
| 7U, // LSR_WIDE_ZZZ_H |
| 899U, // LSR_WIDE_ZZZ_S |
| 1065792U, // LSR_ZPmI_B |
| 1065856U, // LSR_ZPmI_D |
| 33733U, // LSR_ZPmI_H |
| 1065984U, // LSR_ZPmI_S |
| 17216U, // LSR_ZPmZ_B |
| 279424U, // LSR_ZPmZ_D |
| 549829U, // LSR_ZPmZ_H |
| 803840U, // LSR_ZPmZ_S |
| 259U, // LSR_ZZI_B |
| 259U, // LSR_ZZI_D |
| 8U, // LSR_ZZI_H |
| 259U, // LSR_ZZI_S |
| 1065219U, // MADDWrrr |
| 1065219U, // MADDXrrr |
| 8929280U, // MAD_ZPmZZ_B |
| 3162176U, // MAD_ZPmZZ_D |
| 607169U, // MAD_ZPmZZ_H |
| 3424448U, // MAD_ZPmZZ_S |
| 8929280U, // MLA_ZPmZZ_B |
| 3162176U, // MLA_ZPmZZ_D |
| 607169U, // MLA_ZPmZZ_H |
| 3424448U, // MLA_ZPmZZ_S |
| 387U, // MLAv16i8 |
| 387U, // MLAv2i32 |
| 614787U, // MLAv2i32_indexed |
| 387U, // MLAv4i16 |
| 614787U, // MLAv4i16_indexed |
| 387U, // MLAv4i32 |
| 614787U, // MLAv4i32_indexed |
| 387U, // MLAv8i16 |
| 614787U, // MLAv8i16_indexed |
| 387U, // MLAv8i8 |
| 8929280U, // MLS_ZPmZZ_B |
| 3162176U, // MLS_ZPmZZ_D |
| 607169U, // MLS_ZPmZZ_H |
| 3424448U, // MLS_ZPmZZ_S |
| 387U, // MLSv16i8 |
| 387U, // MLSv2i32 |
| 614787U, // MLSv2i32_indexed |
| 387U, // MLSv4i16 |
| 614787U, // MLSv4i16_indexed |
| 387U, // MLSv4i32 |
| 614787U, // MLSv4i32_indexed |
| 387U, // MLSv8i16 |
| 614787U, // MLSv8i16_indexed |
| 387U, // MLSv8i8 |
| 0U, // MOVID |
| 2U, // MOVIv16b_ns |
| 0U, // MOVIv2d_ns |
| 29U, // MOVIv2i32 |
| 29U, // MOVIv2s_msl |
| 29U, // MOVIv4i16 |
| 29U, // MOVIv4i32 |
| 29U, // MOVIv4s_msl |
| 2U, // MOVIv8b_ns |
| 29U, // MOVIv8i16 |
| 0U, // MOVKWi |
| 0U, // MOVKXi |
| 29U, // MOVNWi |
| 29U, // MOVNXi |
| 0U, // MOVPRFX_ZPmZ_B |
| 64U, // MOVPRFX_ZPmZ_D |
| 129U, // MOVPRFX_ZPmZ_H |
| 192U, // MOVPRFX_ZPmZ_S |
| 838U, // MOVPRFX_ZPzZ_B |
| 902U, // MOVPRFX_ZPzZ_D |
| 133U, // MOVPRFX_ZPzZ_H |
| 1030U, // MOVPRFX_ZPzZ_S |
| 2U, // MOVPRFX_ZZ |
| 29U, // MOVZWi |
| 29U, // MOVZXi |
| 0U, // MOVaddr |
| 0U, // MOVaddrBA |
| 0U, // MOVaddrCP |
| 0U, // MOVaddrEXT |
| 0U, // MOVaddrJT |
| 0U, // MOVaddrTLS |
| 0U, // MOVbaseTLS |
| 0U, // MOVi32imm |
| 0U, // MOVi64imm |
| 0U, // MRS |
| 8929280U, // MSB_ZPmZZ_B |
| 3162176U, // MSB_ZPmZZ_D |
| 607169U, // MSB_ZPmZZ_H |
| 3424448U, // MSB_ZPmZZ_S |
| 0U, // MSR |
| 0U, // MSRpstateImm1 |
| 0U, // MSRpstateImm4 |
| 1065219U, // MSUBWrrr |
| 1065219U, // MSUBXrrr |
| 259U, // MUL_ZI_B |
| 259U, // MUL_ZI_D |
| 8U, // MUL_ZI_H |
| 259U, // MUL_ZI_S |
| 17216U, // MUL_ZPmZ_B |
| 279424U, // MUL_ZPmZ_D |
| 549829U, // MUL_ZPmZ_H |
| 803840U, // MUL_ZPmZ_S |
| 323U, // MULv16i8 |
| 323U, // MULv2i32 |
| 106819U, // MULv2i32_indexed |
| 323U, // MULv4i16 |
| 106819U, // MULv4i16_indexed |
| 323U, // MULv4i32 |
| 106819U, // MULv4i32_indexed |
| 323U, // MULv8i16 |
| 106819U, // MULv8i16_indexed |
| 323U, // MULv8i8 |
| 29U, // MVNIv2i32 |
| 29U, // MVNIv2s_msl |
| 29U, // MVNIv4i16 |
| 29U, // MVNIv4i32 |
| 29U, // MVNIv4s_msl |
| 29U, // MVNIv8i16 |
| 17222U, // NANDS_PPzPP |
| 17222U, // NAND_PPzPP |
| 0U, // NEG_ZPmZ_B |
| 64U, // NEG_ZPmZ_D |
| 129U, // NEG_ZPmZ_H |
| 192U, // NEG_ZPmZ_S |
| 2U, // NEGv16i8 |
| 2U, // NEGv1i64 |
| 2U, // NEGv2i32 |
| 2U, // NEGv2i64 |
| 2U, // NEGv4i16 |
| 2U, // NEGv4i32 |
| 2U, // NEGv8i16 |
| 2U, // NEGv8i8 |
| 17222U, // NORS_PPzPP |
| 17222U, // NOR_PPzPP |
| 0U, // NOT_ZPmZ_B |
| 64U, // NOT_ZPmZ_D |
| 129U, // NOT_ZPmZ_H |
| 192U, // NOT_ZPmZ_S |
| 2U, // NOTv16i8 |
| 2U, // NOTv8i8 |
| 17222U, // ORNS_PPzPP |
| 0U, // ORNWrr |
| 515U, // ORNWrs |
| 0U, // ORNXrr |
| 515U, // ORNXrs |
| 17222U, // ORN_PPzPP |
| 323U, // ORNv16i8 |
| 323U, // ORNv8i8 |
| 17222U, // ORRS_PPzPP |
| 2115U, // ORRWri |
| 0U, // ORRWrr |
| 515U, // ORRWrs |
| 2179U, // ORRXri |
| 0U, // ORRXrr |
| 515U, // ORRXrs |
| 17222U, // ORR_PPzPP |
| 2179U, // ORR_ZI |
| 17216U, // ORR_ZPmZ_B |
| 279424U, // ORR_ZPmZ_D |
| 549829U, // ORR_ZPmZ_H |
| 803840U, // ORR_ZPmZ_S |
| 899U, // ORR_ZZZ |
| 323U, // ORRv16i8 |
| 0U, // ORRv2i32 |
| 0U, // ORRv4i16 |
| 0U, // ORRv4i32 |
| 0U, // ORRv8i16 |
| 323U, // ORRv8i8 |
| 835U, // ORV_VPZ_B |
| 899U, // ORV_VPZ_D |
| 2243U, // ORV_VPZ_H |
| 1027U, // ORV_VPZ_S |
| 2U, // PACDA |
| 2U, // PACDB |
| 0U, // PACDZA |
| 0U, // PACDZB |
| 259U, // PACGA |
| 2U, // PACIA |
| 0U, // PACIA1716 |
| 0U, // PACIASP |
| 0U, // PACIAZ |
| 2U, // PACIB |
| 0U, // PACIB1716 |
| 0U, // PACIBSP |
| 0U, // PACIBZ |
| 0U, // PACIZA |
| 0U, // PACIZB |
| 0U, // PFALSE |
| 323U, // PMULLv16i8 |
| 323U, // PMULLv1i64 |
| 323U, // PMULLv2i64 |
| 323U, // PMULLv8i8 |
| 323U, // PMULv16i8 |
| 323U, // PMULv8i8 |
| 835U, // PNEXT_B |
| 899U, // PNEXT_D |
| 133U, // PNEXT_H |
| 1027U, // PNEXT_S |
| 27U, // PRFB_D_PZI |
| 30U, // PRFB_D_SCALED |
| 31U, // PRFB_D_SXTW_SCALED |
| 32U, // PRFB_D_UXTW_SCALED |
| 5261U, // PRFB_PRI |
| 33U, // PRFB_PRR |
| 27U, // PRFB_S_PZI |
| 34U, // PRFB_S_SXTW_SCALED |
| 35U, // PRFB_S_UXTW_SCALED |
| 0U, // PRFD_D_PZI |
| 36U, // PRFD_D_SCALED |
| 37U, // PRFD_D_SXTW_SCALED |
| 38U, // PRFD_D_UXTW_SCALED |
| 5261U, // PRFD_PRI |
| 39U, // PRFD_PRR |
| 0U, // PRFD_S_PZI |
| 40U, // PRFD_S_SXTW_SCALED |
| 41U, // PRFD_S_UXTW_SCALED |
| 0U, // PRFH_D_PZI |
| 42U, // PRFH_D_SCALED |
| 43U, // PRFH_D_SXTW_SCALED |
| 44U, // PRFH_D_UXTW_SCALED |
| 5261U, // PRFH_PRI |
| 45U, // PRFH_PRR |
| 0U, // PRFH_S_PZI |
| 46U, // PRFH_S_SXTW_SCALED |
| 47U, // PRFH_S_UXTW_SCALED |
| 0U, // PRFMl |
| 6832387U, // PRFMroW |
| 7094531U, // PRFMroX |
| 4995U, // PRFMui |
| 48U, // PRFS_PRR |
| 49411U, // PRFUMi |
| 0U, // PRFW_D_PZI |
| 49U, // PRFW_D_SCALED |
| 50U, // PRFW_D_SXTW_SCALED |
| 51U, // PRFW_D_UXTW_SCALED |
| 5261U, // PRFW_PRI |
| 0U, // PRFW_S_PZI |
| 52U, // PRFW_S_SXTW_SCALED |
| 53U, // PRFW_S_UXTW_SCALED |
| 2U, // PTEST_PP |
| 2U, // PTRUES_B |
| 2U, // PTRUES_D |
| 0U, // PTRUES_H |
| 2U, // PTRUES_S |
| 2U, // PTRUE_B |
| 2U, // PTRUE_D |
| 0U, // PTRUE_H |
| 2U, // PTRUE_S |
| 0U, // PUNPKHI_PP |
| 0U, // PUNPKLO_PP |
| 323U, // RADDHNv2i64_v2i32 |
| 387U, // RADDHNv2i64_v4i32 |
| 323U, // RADDHNv4i32_v4i16 |
| 387U, // RADDHNv4i32_v8i16 |
| 387U, // RADDHNv8i16_v16i8 |
| 323U, // RADDHNv8i16_v8i8 |
| 0U, // RAX1 |
| 2U, // RBITWr |
| 2U, // RBITXr |
| 0U, // RBIT_ZPmZ_B |
| 64U, // RBIT_ZPmZ_D |
| 129U, // RBIT_ZPmZ_H |
| 192U, // RBIT_ZPmZ_S |
| 2U, // RBITv16i8 |
| 2U, // RBITv8i8 |
| 54U, // RDFFRS_PPz |
| 0U, // RDFFR_P |
| 54U, // RDFFR_PPz |
| 2U, // RDVLI_XI |
| 0U, // RET |
| 0U, // RETAA |
| 0U, // RETAB |
| 0U, // RET_ReallyLR |
| 2U, // REV16Wr |
| 2U, // REV16Xr |
| 2U, // REV16v16i8 |
| 2U, // REV16v8i8 |
| 2U, // REV32Xr |
| 2U, // REV32v16i8 |
| 2U, // REV32v4i16 |
| 2U, // REV32v8i16 |
| 2U, // REV32v8i8 |
| 2U, // REV64v16i8 |
| 2U, // REV64v2i32 |
| 2U, // REV64v4i16 |
| 2U, // REV64v4i32 |
| 2U, // REV64v8i16 |
| 2U, // REV64v8i8 |
| 64U, // REVB_ZPmZ_D |
| 129U, // REVB_ZPmZ_H |
| 192U, // REVB_ZPmZ_S |
| 64U, // REVH_ZPmZ_D |
| 192U, // REVH_ZPmZ_S |
| 64U, // REVW_ZPmZ_D |
| 2U, // REVWr |
| 2U, // REVXr |
| 2U, // REV_PP_B |
| 2U, // REV_PP_D |
| 0U, // REV_PP_H |
| 2U, // REV_PP_S |
| 2U, // REV_ZZ_B |
| 2U, // REV_ZZ_D |
| 0U, // REV_ZZ_H |
| 2U, // REV_ZZ_S |
| 0U, // RMIF |
| 259U, // RORVWr |
| 259U, // RORVXr |
| 2307U, // RSHRNv16i8_shift |
| 259U, // RSHRNv2i32_shift |
| 259U, // RSHRNv4i16_shift |
| 2307U, // RSHRNv4i32_shift |
| 2307U, // RSHRNv8i16_shift |
| 259U, // RSHRNv8i8_shift |
| 323U, // RSUBHNv2i64_v2i32 |
| 387U, // RSUBHNv2i64_v4i32 |
| 323U, // RSUBHNv4i32_v4i16 |
| 387U, // RSUBHNv4i32_v8i16 |
| 387U, // RSUBHNv8i16_v16i8 |
| 323U, // RSUBHNv8i16_v8i8 |
| 387U, // SABALv16i8_v8i16 |
| 387U, // SABALv2i32_v2i64 |
| 387U, // SABALv4i16_v4i32 |
| 387U, // SABALv4i32_v2i64 |
| 387U, // SABALv8i16_v4i32 |
| 387U, // SABALv8i8_v8i16 |
| 387U, // SABAv16i8 |
| 387U, // SABAv2i32 |
| 387U, // SABAv4i16 |
| 387U, // SABAv4i32 |
| 387U, // SABAv8i16 |
| 387U, // SABAv8i8 |
| 323U, // SABDLv16i8_v8i16 |
| 323U, // SABDLv2i32_v2i64 |
| 323U, // SABDLv4i16_v4i32 |
| 323U, // SABDLv4i32_v2i64 |
| 323U, // SABDLv8i16_v4i32 |
| 323U, // SABDLv8i8_v8i16 |
| 17216U, // SABD_ZPmZ_B |
| 279424U, // SABD_ZPmZ_D |
| 549829U, // SABD_ZPmZ_H |
| 803840U, // SABD_ZPmZ_S |
| 323U, // SABDv16i8 |
| 323U, // SABDv2i32 |
| 323U, // SABDv4i16 |
| 323U, // SABDv4i32 |
| 323U, // SABDv8i16 |
| 323U, // SABDv8i8 |
| 2U, // SADALPv16i8_v8i16 |
| 2U, // SADALPv2i32_v1i64 |
| 2U, // SADALPv4i16_v2i32 |
| 2U, // SADALPv4i32_v2i64 |
| 2U, // SADALPv8i16_v4i32 |
| 2U, // SADALPv8i8_v4i16 |
| 2U, // SADDLPv16i8_v8i16 |
| 2U, // SADDLPv2i32_v1i64 |
| 2U, // SADDLPv4i16_v2i32 |
| 2U, // SADDLPv4i32_v2i64 |
| 2U, // SADDLPv8i16_v4i32 |
| 2U, // SADDLPv8i8_v4i16 |
| 2U, // SADDLVv16i8v |
| 2U, // SADDLVv4i16v |
| 2U, // SADDLVv4i32v |
| 2U, // SADDLVv8i16v |
| 2U, // SADDLVv8i8v |
| 323U, // SADDLv16i8_v8i16 |
| 323U, // SADDLv2i32_v2i64 |
| 323U, // SADDLv4i16_v4i32 |
| 323U, // SADDLv4i32_v2i64 |
| 323U, // SADDLv8i16_v4i32 |
| 323U, // SADDLv8i8_v8i16 |
| 835U, // SADDV_VPZ_B |
| 2243U, // SADDV_VPZ_H |
| 1027U, // SADDV_VPZ_S |
| 323U, // SADDWv16i8_v8i16 |
| 323U, // SADDWv2i32_v2i64 |
| 323U, // SADDWv4i16_v4i32 |
| 323U, // SADDWv4i32_v2i64 |
| 323U, // SADDWv8i16_v4i32 |
| 323U, // SADDWv8i8_v8i16 |
| 259U, // SBCSWr |
| 259U, // SBCSXr |
| 259U, // SBCWr |
| 259U, // SBCXr |
| 1065219U, // SBFMWri |
| 1065219U, // SBFMXri |
| 259U, // SCVTFSWDri |
| 259U, // SCVTFSWHri |
| 259U, // SCVTFSWSri |
| 259U, // SCVTFSXDri |
| 259U, // SCVTFSXHri |
| 259U, // SCVTFSXSri |
| 2U, // SCVTFUWDri |
| 2U, // SCVTFUWHri |
| 2U, // SCVTFUWSri |
| 2U, // SCVTFUXDri |
| 2U, // SCVTFUXHri |
| 2U, // SCVTFUXSri |
| 64U, // SCVTF_ZPmZ_DtoD |
| 151U, // SCVTF_ZPmZ_DtoH |
| 64U, // SCVTF_ZPmZ_DtoS |
| 129U, // SCVTF_ZPmZ_HtoH |
| 192U, // SCVTF_ZPmZ_StoD |
| 146U, // SCVTF_ZPmZ_StoH |
| 192U, // SCVTF_ZPmZ_StoS |
| 259U, // SCVTFd |
| 259U, // SCVTFh |
| 259U, // SCVTFs |
| 2U, // SCVTFv1i16 |
| 2U, // SCVTFv1i32 |
| 2U, // SCVTFv1i64 |
| 2U, // SCVTFv2f32 |
| 2U, // SCVTFv2f64 |
| 259U, // SCVTFv2i32_shift |
| 259U, // SCVTFv2i64_shift |
| 2U, // SCVTFv4f16 |
| 2U, // SCVTFv4f32 |
| 259U, // SCVTFv4i16_shift |
| 259U, // SCVTFv4i32_shift |
| 2U, // SCVTFv8f16 |
| 259U, // SCVTFv8i16_shift |
| 279424U, // SDIVR_ZPmZ_D |
| 803840U, // SDIVR_ZPmZ_S |
| 259U, // SDIVWr |
| 259U, // SDIVXr |
| 279424U, // SDIV_ZPmZ_D |
| 803840U, // SDIV_ZPmZ_S |
| 55U, // SDOT_ZZZI_D |
| 55U, // SDOT_ZZZI_S |
| 2U, // SDOT_ZZZ_D |
| 2U, // SDOT_ZZZ_S |
| 614787U, // SDOTlanev16i8 |
| 614787U, // SDOTlanev8i8 |
| 0U, // SDOTv16i8 |
| 0U, // SDOTv8i8 |
| 17219U, // SEL_PPPP |
| 17219U, // SEL_ZPZZ_B |
| 279427U, // SEL_ZPZZ_D |
| 549829U, // SEL_ZPZZ_H |
| 803843U, // SEL_ZPZZ_S |
| 0U, // SETF16 |
| 0U, // SETF8 |
| 0U, // SETFFR |
| 387U, // SHA1Crrr |
| 2U, // SHA1Hrr |
| 387U, // SHA1Mrrr |
| 387U, // SHA1Prrr |
| 387U, // SHA1SU0rrr |
| 2U, // SHA1SU1rr |
| 387U, // SHA256H2rrr |
| 387U, // SHA256Hrrr |
| 2U, // SHA256SU0rr |
| 387U, // SHA256SU1rrr |
| 0U, // SHA512H |
| 0U, // SHA512H2 |
| 0U, // SHA512SU0 |
| 0U, // SHA512SU1 |
| 323U, // SHADDv16i8 |
| 323U, // SHADDv2i32 |
| 323U, // SHADDv4i16 |
| 323U, // SHADDv4i32 |
| 323U, // SHADDv8i16 |
| 323U, // SHADDv8i8 |
| 56U, // SHLLv16i8 |
| 57U, // SHLLv2i32 |
| 58U, // SHLLv4i16 |
| 57U, // SHLLv4i32 |
| 58U, // SHLLv8i16 |
| 56U, // SHLLv8i8 |
| 259U, // SHLd |
| 259U, // SHLv16i8_shift |
| 259U, // SHLv2i32_shift |
| 259U, // SHLv2i64_shift |
| 259U, // SHLv4i16_shift |
| 259U, // SHLv4i32_shift |
| 259U, // SHLv8i16_shift |
| 259U, // SHLv8i8_shift |
| 2307U, // SHRNv16i8_shift |
| 259U, // SHRNv2i32_shift |
| 259U, // SHRNv4i16_shift |
| 2307U, // SHRNv4i32_shift |
| 2307U, // SHRNv8i16_shift |
| 259U, // SHRNv8i8_shift |
| 323U, // SHSUBv16i8 |
| 323U, // SHSUBv2i32 |
| 323U, // SHSUBv4i16 |
| 323U, // SHSUBv4i32 |
| 323U, // SHSUBv8i16 |
| 323U, // SHSUBv8i8 |
| 2307U, // SLId |
| 2307U, // SLIv16i8_shift |
| 2307U, // SLIv2i32_shift |
| 2307U, // SLIv2i64_shift |
| 2307U, // SLIv4i16_shift |
| 2307U, // SLIv4i32_shift |
| 2307U, // SLIv8i16_shift |
| 2307U, // SLIv8i8_shift |
| 0U, // SM3PARTW1 |
| 0U, // SM3PARTW2 |
| 0U, // SM3SS1 |
| 0U, // SM3TT1A |
| 0U, // SM3TT1B |
| 0U, // SM3TT2A |
| 0U, // SM3TT2B |
| 0U, // SM4E |
| 0U, // SM4ENCKEY |
| 1065219U, // SMADDLrrr |
| 323U, // SMAXPv16i8 |
| 323U, // SMAXPv2i32 |
| 323U, // SMAXPv4i16 |
| 323U, // SMAXPv4i32 |
| 323U, // SMAXPv8i16 |
| 323U, // SMAXPv8i8 |
| 835U, // SMAXV_VPZ_B |
| 899U, // SMAXV_VPZ_D |
| 2243U, // SMAXV_VPZ_H |
| 1027U, // SMAXV_VPZ_S |
| 2U, // SMAXVv16i8v |
| 2U, // SMAXVv4i16v |
| 2U, // SMAXVv4i32v |
| 2U, // SMAXVv8i16v |
| 2U, // SMAXVv8i8v |
| 259U, // SMAX_ZI_B |
| 259U, // SMAX_ZI_D |
| 8U, // SMAX_ZI_H |
| 259U, // SMAX_ZI_S |
| 17216U, // SMAX_ZPmZ_B |
| 279424U, // SMAX_ZPmZ_D |
| 549829U, // SMAX_ZPmZ_H |
| 803840U, // SMAX_ZPmZ_S |
| 323U, // SMAXv16i8 |
| 323U, // SMAXv2i32 |
| 323U, // SMAXv4i16 |
| 323U, // SMAXv4i32 |
| 323U, // SMAXv8i16 |
| 323U, // SMAXv8i8 |
| 0U, // SMC |
| 323U, // SMINPv16i8 |
| 323U, // SMINPv2i32 |
| 323U, // SMINPv4i16 |
| 323U, // SMINPv4i32 |
| 323U, // SMINPv8i16 |
| 323U, // SMINPv8i8 |
| 835U, // SMINV_VPZ_B |
| 899U, // SMINV_VPZ_D |
| 2243U, // SMINV_VPZ_H |
| 1027U, // SMINV_VPZ_S |
| 2U, // SMINVv16i8v |
| 2U, // SMINVv4i16v |
| 2U, // SMINVv4i32v |
| 2U, // SMINVv8i16v |
| 2U, // SMINVv8i8v |
| 259U, // SMIN_ZI_B |
| 259U, // SMIN_ZI_D |
| 8U, // SMIN_ZI_H |
| 259U, // SMIN_ZI_S |
| 17216U, // SMIN_ZPmZ_B |
| 279424U, // SMIN_ZPmZ_D |
| 549829U, // SMIN_ZPmZ_H |
| 803840U, // SMIN_ZPmZ_S |
| 323U, // SMINv16i8 |
| 323U, // SMINv2i32 |
| 323U, // SMINv4i16 |
| 323U, // SMINv4i32 |
| 323U, // SMINv8i16 |
| 323U, // SMINv8i8 |
| 387U, // SMLALv16i8_v8i16 |
| 614787U, // SMLALv2i32_indexed |
| 387U, // SMLALv2i32_v2i64 |
| 614787U, // SMLALv4i16_indexed |
| 387U, // SMLALv4i16_v4i32 |
| 614787U, // SMLALv4i32_indexed |
| 387U, // SMLALv4i32_v2i64 |
| 614787U, // SMLALv8i16_indexed |
| 387U, // SMLALv8i16_v4i32 |
| 387U, // SMLALv8i8_v8i16 |
| 387U, // SMLSLv16i8_v8i16 |
| 614787U, // SMLSLv2i32_indexed |
| 387U, // SMLSLv2i32_v2i64 |
| 614787U, // SMLSLv4i16_indexed |
| 387U, // SMLSLv4i16_v4i32 |
| 614787U, // SMLSLv4i32_indexed |
| 387U, // SMLSLv4i32_v2i64 |
| 614787U, // SMLSLv8i16_indexed |
| 387U, // SMLSLv8i16_v4i32 |
| 387U, // SMLSLv8i8_v8i16 |
| 15U, // SMOVvi16to32 |
| 15U, // SMOVvi16to64 |
| 15U, // SMOVvi32to64 |
| 15U, // SMOVvi8to32 |
| 15U, // SMOVvi8to64 |
| 1065219U, // SMSUBLrrr |
| 17216U, // SMULH_ZPmZ_B |
| 279424U, // SMULH_ZPmZ_D |
| 549829U, // SMULH_ZPmZ_H |
| 803840U, // SMULH_ZPmZ_S |
| 259U, // SMULHrr |
| 323U, // SMULLv16i8_v8i16 |
| 106819U, // SMULLv2i32_indexed |
| 323U, // SMULLv2i32_v2i64 |
| 106819U, // SMULLv4i16_indexed |
| 323U, // SMULLv4i16_v4i32 |
| 106819U, // SMULLv4i32_indexed |
| 323U, // SMULLv4i32_v2i64 |
| 106819U, // SMULLv8i16_indexed |
| 323U, // SMULLv8i16_v4i32 |
| 323U, // SMULLv8i8_v8i16 |
| 17219U, // SPLICE_ZPZ_B |
| 279427U, // SPLICE_ZPZ_D |
| 549829U, // SPLICE_ZPZ_H |
| 803843U, // SPLICE_ZPZ_S |
| 2U, // SQABSv16i8 |
| 2U, // SQABSv1i16 |
| 2U, // SQABSv1i32 |
| 2U, // SQABSv1i64 |
| 2U, // SQABSv1i8 |
| 2U, // SQABSv2i32 |
| 2U, // SQABSv2i64 |
| 2U, // SQABSv4i16 |
| 2U, // SQABSv4i32 |
| 2U, // SQABSv8i16 |
| 2U, // SQABSv8i8 |
| 643U, // SQADD_ZI_B |
| 707U, // SQADD_ZI_D |
| 4U, // SQADD_ZI_H |
| 771U, // SQADD_ZI_S |
| 835U, // SQADD_ZZZ_B |
| 899U, // SQADD_ZZZ_D |
| 133U, // SQADD_ZZZ_H |
| 1027U, // SQADD_ZZZ_S |
| 323U, // SQADDv16i8 |
| 259U, // SQADDv1i16 |
| 259U, // SQADDv1i32 |
| 259U, // SQADDv1i64 |
| 259U, // SQADDv1i8 |
| 323U, // SQADDv2i32 |
| 323U, // SQADDv2i64 |
| 323U, // SQADDv4i16 |
| 323U, // SQADDv4i32 |
| 323U, // SQADDv8i16 |
| 323U, // SQADDv8i8 |
| 0U, // SQDECB_XPiI |
| 0U, // SQDECB_XPiWdI |
| 0U, // SQDECD_XPiI |
| 0U, // SQDECD_XPiWdI |
| 0U, // SQDECD_ZPiI |
| 0U, // SQDECH_XPiI |
| 0U, // SQDECH_XPiWdI |
| 0U, // SQDECH_ZPiI |
| 5315U, // SQDECP_XPWd_B |
| 5315U, // SQDECP_XPWd_D |
| 5315U, // SQDECP_XPWd_H |
| 5315U, // SQDECP_XPWd_S |
| 2U, // SQDECP_XP_B |
| 2U, // SQDECP_XP_D |
| 2U, // SQDECP_XP_H |
| 2U, // SQDECP_XP_S |
| 2U, // SQDECP_ZP_D |
| 0U, // SQDECP_ZP_H |
| 2U, // SQDECP_ZP_S |
| 0U, // SQDECW_XPiI |
| 0U, // SQDECW_XPiWdI |
| 0U, // SQDECW_ZPiI |
| 2307U, // SQDMLALi16 |
| 2307U, // SQDMLALi32 |
| 614787U, // SQDMLALv1i32_indexed |
| 614787U, // SQDMLALv1i64_indexed |
| 614787U, // SQDMLALv2i32_indexed |
| 387U, // SQDMLALv2i32_v2i64 |
| 614787U, // SQDMLALv4i16_indexed |
| 387U, // SQDMLALv4i16_v4i32 |
| 614787U, // SQDMLALv4i32_indexed |
| 387U, // SQDMLALv4i32_v2i64 |
| 614787U, // SQDMLALv8i16_indexed |
| 387U, // SQDMLALv8i16_v4i32 |
| 2307U, // SQDMLSLi16 |
| 2307U, // SQDMLSLi32 |
| 614787U, // SQDMLSLv1i32_indexed |
| 614787U, // SQDMLSLv1i64_indexed |
| 614787U, // SQDMLSLv2i32_indexed |
| 387U, // SQDMLSLv2i32_v2i64 |
| 614787U, // SQDMLSLv4i16_indexed |
| 387U, // SQDMLSLv4i16_v4i32 |
| 614787U, // SQDMLSLv4i32_indexed |
| 387U, // SQDMLSLv4i32_v2i64 |
| 614787U, // SQDMLSLv8i16_indexed |
| 387U, // SQDMLSLv8i16_v4i32 |
| 259U, // SQDMULHv1i16 |
| 106819U, // SQDMULHv1i16_indexed |
| 259U, // SQDMULHv1i32 |
| 106819U, // SQDMULHv1i32_indexed |
| 323U, // SQDMULHv2i32 |
| 106819U, // SQDMULHv2i32_indexed |
| 323U, // SQDMULHv4i16 |
| 106819U, // SQDMULHv4i16_indexed |
| 323U, // SQDMULHv4i32 |
| 106819U, // SQDMULHv4i32_indexed |
| 323U, // SQDMULHv8i16 |
| 106819U, // SQDMULHv8i16_indexed |
| 259U, // SQDMULLi16 |
| 259U, // SQDMULLi32 |
| 106819U, // SQDMULLv1i32_indexed |
| 106819U, // SQDMULLv1i64_indexed |
| 106819U, // SQDMULLv2i32_indexed |
| 323U, // SQDMULLv2i32_v2i64 |
| 106819U, // SQDMULLv4i16_indexed |
| 323U, // SQDMULLv4i16_v4i32 |
| 106819U, // SQDMULLv4i32_indexed |
| 323U, // SQDMULLv4i32_v2i64 |
| 106819U, // SQDMULLv8i16_indexed |
| 323U, // SQDMULLv8i16_v4i32 |
| 0U, // SQINCB_XPiI |
| 0U, // SQINCB_XPiWdI |
| 0U, // SQINCD_XPiI |
| 0U, // SQINCD_XPiWdI |
| 0U, // SQINCD_ZPiI |
| 0U, // SQINCH_XPiI |
| 0U, // SQINCH_XPiWdI |
| 0U, // SQINCH_ZPiI |
| 5315U, // SQINCP_XPWd_B |
| 5315U, // SQINCP_XPWd_D |
| 5315U, // SQINCP_XPWd_H |
| 5315U, // SQINCP_XPWd_S |
| 2U, // SQINCP_XP_B |
| 2U, // SQINCP_XP_D |
| 2U, // SQINCP_XP_H |
| 2U, // SQINCP_XP_S |
| 2U, // SQINCP_ZP_D |
| 0U, // SQINCP_ZP_H |
| 2U, // SQINCP_ZP_S |
| 0U, // SQINCW_XPiI |
| 0U, // SQINCW_XPiWdI |
| 0U, // SQINCW_ZPiI |
| 2U, // SQNEGv16i8 |
| 2U, // SQNEGv1i16 |
| 2U, // SQNEGv1i32 |
| 2U, // SQNEGv1i64 |
| 2U, // SQNEGv1i8 |
| 2U, // SQNEGv2i32 |
| 2U, // SQNEGv2i64 |
| 2U, // SQNEGv4i16 |
| 2U, // SQNEGv4i32 |
| 2U, // SQNEGv8i16 |
| 2U, // SQNEGv8i8 |
| 614787U, // SQRDMLAHi16_indexed |
| 614787U, // SQRDMLAHi32_indexed |
| 2307U, // SQRDMLAHv1i16 |
| 2307U, // SQRDMLAHv1i32 |
| 387U, // SQRDMLAHv2i32 |
| 614787U, // SQRDMLAHv2i32_indexed |
| 387U, // SQRDMLAHv4i16 |
| 614787U, // SQRDMLAHv4i16_indexed |
| 387U, // SQRDMLAHv4i32 |
| 614787U, // SQRDMLAHv4i32_indexed |
| 387U, // SQRDMLAHv8i16 |
| 614787U, // SQRDMLAHv8i16_indexed |
| 614787U, // SQRDMLSHi16_indexed |
| 614787U, // SQRDMLSHi32_indexed |
| 2307U, // SQRDMLSHv1i16 |
| 2307U, // SQRDMLSHv1i32 |
| 387U, // SQRDMLSHv2i32 |
| 614787U, // SQRDMLSHv2i32_indexed |
| 387U, // SQRDMLSHv4i16 |
| 614787U, // SQRDMLSHv4i16_indexed |
| 387U, // SQRDMLSHv4i32 |
| 614787U, // SQRDMLSHv4i32_indexed |
| 387U, // SQRDMLSHv8i16 |
| 614787U, // SQRDMLSHv8i16_indexed |
| 259U, // SQRDMULHv1i16 |
| 106819U, // SQRDMULHv1i16_indexed |
| 259U, // SQRDMULHv1i32 |
| 106819U, // SQRDMULHv1i32_indexed |
| 323U, // SQRDMULHv2i32 |
| 106819U, // SQRDMULHv2i32_indexed |
| 323U, // SQRDMULHv4i16 |
| 106819U, // SQRDMULHv4i16_indexed |
| 323U, // SQRDMULHv4i32 |
| 106819U, // SQRDMULHv4i32_indexed |
| 323U, // SQRDMULHv8i16 |
| 106819U, // SQRDMULHv8i16_indexed |
| 323U, // SQRSHLv16i8 |
| 259U, // SQRSHLv1i16 |
| 259U, // SQRSHLv1i32 |
| 259U, // SQRSHLv1i64 |
| 259U, // SQRSHLv1i8 |
| 323U, // SQRSHLv2i32 |
| 323U, // SQRSHLv2i64 |
| 323U, // SQRSHLv4i16 |
| 323U, // SQRSHLv4i32 |
| 323U, // SQRSHLv8i16 |
| 323U, // SQRSHLv8i8 |
| 259U, // SQRSHRNb |
| 259U, // SQRSHRNh |
| 259U, // SQRSHRNs |
| 2307U, // SQRSHRNv16i8_shift |
| 259U, // SQRSHRNv2i32_shift |
| 259U, // SQRSHRNv4i16_shift |
| 2307U, // SQRSHRNv4i32_shift |
| 2307U, // SQRSHRNv8i16_shift |
| 259U, // SQRSHRNv8i8_shift |
| 259U, // SQRSHRUNb |
| 259U, // SQRSHRUNh |
| 259U, // SQRSHRUNs |
| 2307U, // SQRSHRUNv16i8_shift |
| 259U, // SQRSHRUNv2i32_shift |
| 259U, // SQRSHRUNv4i16_shift |
| 2307U, // SQRSHRUNv4i32_shift |
| 2307U, // SQRSHRUNv8i16_shift |
| 259U, // SQRSHRUNv8i8_shift |
| 259U, // SQSHLUb |
| 259U, // SQSHLUd |
| 259U, // SQSHLUh |
| 259U, // SQSHLUs |
| 259U, // SQSHLUv16i8_shift |
| 259U, // SQSHLUv2i32_shift |
| 259U, // SQSHLUv2i64_shift |
| 259U, // SQSHLUv4i16_shift |
| 259U, // SQSHLUv4i32_shift |
| 259U, // SQSHLUv8i16_shift |
| 259U, // SQSHLUv8i8_shift |
| 259U, // SQSHLb |
| 259U, // SQSHLd |
| 259U, // SQSHLh |
| 259U, // SQSHLs |
| 323U, // SQSHLv16i8 |
| 259U, // SQSHLv16i8_shift |
| 259U, // SQSHLv1i16 |
| 259U, // SQSHLv1i32 |
| 259U, // SQSHLv1i64 |
| 259U, // SQSHLv1i8 |
| 323U, // SQSHLv2i32 |
| 259U, // SQSHLv2i32_shift |
| 323U, // SQSHLv2i64 |
| 259U, // SQSHLv2i64_shift |
| 323U, // SQSHLv4i16 |
| 259U, // SQSHLv4i16_shift |
| 323U, // SQSHLv4i32 |
| 259U, // SQSHLv4i32_shift |
| 323U, // SQSHLv8i16 |
| 259U, // SQSHLv8i16_shift |
| 323U, // SQSHLv8i8 |
| 259U, // SQSHLv8i8_shift |
| 259U, // SQSHRNb |
| 259U, // SQSHRNh |
| 259U, // SQSHRNs |
| 2307U, // SQSHRNv16i8_shift |
| 259U, // SQSHRNv2i32_shift |
| 259U, // SQSHRNv4i16_shift |
| 2307U, // SQSHRNv4i32_shift |
| 2307U, // SQSHRNv8i16_shift |
| 259U, // SQSHRNv8i8_shift |
| 259U, // SQSHRUNb |
| 259U, // SQSHRUNh |
| 259U, // SQSHRUNs |
| 2307U, // SQSHRUNv16i8_shift |
| 259U, // SQSHRUNv2i32_shift |
| 259U, // SQSHRUNv4i16_shift |
| 2307U, // SQSHRUNv4i32_shift |
| 2307U, // SQSHRUNv8i16_shift |
| 259U, // SQSHRUNv8i8_shift |
| 643U, // SQSUB_ZI_B |
| 707U, // SQSUB_ZI_D |
| 4U, // SQSUB_ZI_H |
| 771U, // SQSUB_ZI_S |
| 835U, // SQSUB_ZZZ_B |
| 899U, // SQSUB_ZZZ_D |
| 133U, // SQSUB_ZZZ_H |
| 1027U, // SQSUB_ZZZ_S |
| 323U, // SQSUBv16i8 |
| 259U, // SQSUBv1i16 |
| 259U, // SQSUBv1i32 |
| 259U, // SQSUBv1i64 |
| 259U, // SQSUBv1i8 |
| 323U, // SQSUBv2i32 |
| 323U, // SQSUBv2i64 |
| 323U, // SQSUBv4i16 |
| 323U, // SQSUBv4i32 |
| 323U, // SQSUBv8i16 |
| 323U, // SQSUBv8i8 |
| 2U, // SQXTNv16i8 |
| 2U, // SQXTNv1i16 |
| 2U, // SQXTNv1i32 |
| 2U, // SQXTNv1i8 |
| 2U, // SQXTNv2i32 |
| 2U, // SQXTNv4i16 |
| 2U, // SQXTNv4i32 |
| 2U, // SQXTNv8i16 |
| 2U, // SQXTNv8i8 |
| 2U, // SQXTUNv16i8 |
| 2U, // SQXTUNv1i16 |
| 2U, // SQXTUNv1i32 |
| 2U, // SQXTUNv1i8 |
| 2U, // SQXTUNv2i32 |
| 2U, // SQXTUNv4i16 |
| 2U, // SQXTUNv4i32 |
| 2U, // SQXTUNv8i16 |
| 2U, // SQXTUNv8i8 |
| 323U, // SRHADDv16i8 |
| 323U, // SRHADDv2i32 |
| 323U, // SRHADDv4i16 |
| 323U, // SRHADDv4i32 |
| 323U, // SRHADDv8i16 |
| 323U, // SRHADDv8i8 |
| 2307U, // SRId |
| 2307U, // SRIv16i8_shift |
| 2307U, // SRIv2i32_shift |
| 2307U, // SRIv2i64_shift |
| 2307U, // SRIv4i16_shift |
| 2307U, // SRIv4i32_shift |
| 2307U, // SRIv8i16_shift |
| 2307U, // SRIv8i8_shift |
| 323U, // SRSHLv16i8 |
| 259U, // SRSHLv1i64 |
| 323U, // SRSHLv2i32 |
| 323U, // SRSHLv2i64 |
| 323U, // SRSHLv4i16 |
| 323U, // SRSHLv4i32 |
| 323U, // SRSHLv8i16 |
| 323U, // SRSHLv8i8 |
| 259U, // SRSHRd |
| 259U, // SRSHRv16i8_shift |
| 259U, // SRSHRv2i32_shift |
| 259U, // SRSHRv2i64_shift |
| 259U, // SRSHRv4i16_shift |
| 259U, // SRSHRv4i32_shift |
| 259U, // SRSHRv8i16_shift |
| 259U, // SRSHRv8i8_shift |
| 2307U, // SRSRAd |
| 2307U, // SRSRAv16i8_shift |
| 2307U, // SRSRAv2i32_shift |
| 2307U, // SRSRAv2i64_shift |
| 2307U, // SRSRAv4i16_shift |
| 2307U, // SRSRAv4i32_shift |
| 2307U, // SRSRAv8i16_shift |
| 2307U, // SRSRAv8i8_shift |
| 259U, // SSHLLv16i8_shift |
| 259U, // SSHLLv2i32_shift |
| 259U, // SSHLLv4i16_shift |
| 259U, // SSHLLv4i32_shift |
| 259U, // SSHLLv8i16_shift |
| 259U, // SSHLLv8i8_shift |
| 323U, // SSHLv16i8 |
| 259U, // SSHLv1i64 |
| 323U, // SSHLv2i32 |
| 323U, // SSHLv2i64 |
| 323U, // SSHLv4i16 |
| 323U, // SSHLv4i32 |
| 323U, // SSHLv8i16 |
| 323U, // SSHLv8i8 |
| 259U, // SSHRd |
| 259U, // SSHRv16i8_shift |
| 259U, // SSHRv2i32_shift |
| 259U, // SSHRv2i64_shift |
| 259U, // SSHRv4i16_shift |
| 259U, // SSHRv4i32_shift |
| 259U, // SSHRv8i16_shift |
| 259U, // SSHRv8i8_shift |
| 2307U, // SSRAd |
| 2307U, // SSRAv16i8_shift |
| 2307U, // SSRAv2i32_shift |
| 2307U, // SSRAv2i64_shift |
| 2307U, // SSRAv4i16_shift |
| 2307U, // SSRAv4i32_shift |
| 2307U, // SSRAv8i16_shift |
| 2307U, // SSRAv8i8_shift |
| 3139U, // SST1B_D |
| 3085U, // SST1B_D_IMM |
| 3203U, // SST1B_D_SXTW |
| 3267U, // SST1B_D_UXTW |
| 3085U, // SST1B_S_IMM |
| 3331U, // SST1B_S_SXTW |
| 3395U, // SST1B_S_UXTW |
| 3139U, // SST1D |
| 24U, // SST1D_IMM |
| 3459U, // SST1D_SCALED |
| 3203U, // SST1D_SXTW |
| 3523U, // SST1D_SXTW_SCALED |
| 3267U, // SST1D_UXTW |
| 3587U, // SST1D_UXTW_SCALED |
| 3139U, // SST1H_D |
| 25U, // SST1H_D_IMM |
| 3651U, // SST1H_D_SCALED |
| 3203U, // SST1H_D_SXTW |
| 3715U, // SST1H_D_SXTW_SCALED |
| 3267U, // SST1H_D_UXTW |
| 3779U, // SST1H_D_UXTW_SCALED |
| 25U, // SST1H_S_IMM |
| 3331U, // SST1H_S_SXTW |
| 3843U, // SST1H_S_SXTW_SCALED |
| 3395U, // SST1H_S_UXTW |
| 3907U, // SST1H_S_UXTW_SCALED |
| 3139U, // SST1W_D |
| 26U, // SST1W_D_IMM |
| 3971U, // SST1W_D_SCALED |
| 3203U, // SST1W_D_SXTW |
| 4035U, // SST1W_D_SXTW_SCALED |
| 3267U, // SST1W_D_UXTW |
| 4099U, // SST1W_D_UXTW_SCALED |
| 26U, // SST1W_IMM |
| 3331U, // SST1W_SXTW |
| 4163U, // SST1W_SXTW_SCALED |
| 3395U, // SST1W_UXTW |
| 4227U, // SST1W_UXTW_SCALED |
| 323U, // SSUBLv16i8_v8i16 |
| 323U, // SSUBLv2i32_v2i64 |
| 323U, // SSUBLv4i16_v4i32 |
| 323U, // SSUBLv4i32_v2i64 |
| 323U, // SSUBLv8i16_v4i32 |
| 323U, // SSUBLv8i8_v8i16 |
| 323U, // SSUBWv16i8_v8i16 |
| 323U, // SSUBWv2i32_v2i64 |
| 323U, // SSUBWv4i16_v4i32 |
| 323U, // SSUBWv4i32_v2i64 |
| 323U, // SSUBWv8i16_v4i32 |
| 323U, // SSUBWv8i8_v8i16 |
| 4291U, // ST1B |
| 4291U, // ST1B_D |
| 125187U, // ST1B_D_IMM |
| 4291U, // ST1B_H |
| 125187U, // ST1B_H_IMM |
| 125187U, // ST1B_IMM |
| 4291U, // ST1B_S |
| 125187U, // ST1B_S_IMM |
| 4355U, // ST1D |
| 125187U, // ST1D_IMM |
| 0U, // ST1Fourv16b |
| 0U, // ST1Fourv16b_POST |
| 0U, // ST1Fourv1d |
| 0U, // ST1Fourv1d_POST |
| 0U, // ST1Fourv2d |
| 0U, // ST1Fourv2d_POST |
| 0U, // ST1Fourv2s |
| 0U, // ST1Fourv2s_POST |
| 0U, // ST1Fourv4h |
| 0U, // ST1Fourv4h_POST |
| 0U, // ST1Fourv4s |
| 0U, // ST1Fourv4s_POST |
| 0U, // ST1Fourv8b |
| 0U, // ST1Fourv8b_POST |
| 0U, // ST1Fourv8h |
| 0U, // ST1Fourv8h_POST |
| 4419U, // ST1H |
| 4419U, // ST1H_D |
| 125187U, // ST1H_D_IMM |
| 125187U, // ST1H_IMM |
| 4419U, // ST1H_S |
| 125187U, // ST1H_S_IMM |
| 0U, // ST1Onev16b |
| 0U, // ST1Onev16b_POST |
| 0U, // ST1Onev1d |
| 0U, // ST1Onev1d_POST |
| 0U, // ST1Onev2d |
| 0U, // ST1Onev2d_POST |
| 0U, // ST1Onev2s |
| 0U, // ST1Onev2s_POST |
| 0U, // ST1Onev4h |
| 0U, // ST1Onev4h_POST |
| 0U, // ST1Onev4s |
| 0U, // ST1Onev4s_POST |
| 0U, // ST1Onev8b |
| 0U, // ST1Onev8b_POST |
| 0U, // ST1Onev8h |
| 0U, // ST1Onev8h_POST |
| 0U, // ST1Threev16b |
| 0U, // ST1Threev16b_POST |
| 0U, // ST1Threev1d |
| 0U, // ST1Threev1d_POST |
| 0U, // ST1Threev2d |
| 0U, // ST1Threev2d_POST |
| 0U, // ST1Threev2s |
| 0U, // ST1Threev2s_POST |
| 0U, // ST1Threev4h |
| 0U, // ST1Threev4h_POST |
| 0U, // ST1Threev4s |
| 0U, // ST1Threev4s_POST |
| 0U, // ST1Threev8b |
| 0U, // ST1Threev8b_POST |
| 0U, // ST1Threev8h |
| 0U, // ST1Threev8h_POST |
| 0U, // ST1Twov16b |
| 0U, // ST1Twov16b_POST |
| 0U, // ST1Twov1d |
| 0U, // ST1Twov1d_POST |
| 0U, // ST1Twov2d |
| 0U, // ST1Twov2d_POST |
| 0U, // ST1Twov2s |
| 0U, // ST1Twov2s_POST |
| 0U, // ST1Twov4h |
| 0U, // ST1Twov4h_POST |
| 0U, // ST1Twov4s |
| 0U, // ST1Twov4s_POST |
| 0U, // ST1Twov8b |
| 0U, // ST1Twov8b_POST |
| 0U, // ST1Twov8h |
| 0U, // ST1Twov8h_POST |
| 4675U, // ST1W |
| 4675U, // ST1W_D |
| 125187U, // ST1W_D_IMM |
| 125187U, // ST1W_IMM |
| 0U, // ST1i16 |
| 0U, // ST1i16_POST |
| 0U, // ST1i32 |
| 0U, // ST1i32_POST |
| 0U, // ST1i64 |
| 0U, // ST1i64_POST |
| 0U, // ST1i8 |
| 0U, // ST1i8_POST |
| 4291U, // ST2B |
| 127427U, // ST2B_IMM |
| 4355U, // ST2D |
| 127427U, // ST2D_IMM |
| 4419U, // ST2H |
| 127427U, // ST2H_IMM |
| 0U, // ST2Twov16b |
| 0U, // ST2Twov16b_POST |
| 0U, // ST2Twov2d |
| 0U, // ST2Twov2d_POST |
| 0U, // ST2Twov2s |
| 0U, // ST2Twov2s_POST |
| 0U, // ST2Twov4h |
| 0U, // ST2Twov4h_POST |
| 0U, // ST2Twov4s |
| 0U, // ST2Twov4s_POST |
| 0U, // ST2Twov8b |
| 0U, // ST2Twov8b_POST |
| 0U, // ST2Twov8h |
| 0U, // ST2Twov8h_POST |
| 4675U, // ST2W |
| 127427U, // ST2W_IMM |
| 0U, // ST2i16 |
| 0U, // ST2i16_POST |
| 0U, // ST2i32 |
| 0U, // ST2i32_POST |
| 0U, // ST2i64 |
| 0U, // ST2i64_POST |
| 0U, // ST2i8 |
| 0U, // ST2i8_POST |
| 4291U, // ST3B |
| 4803U, // ST3B_IMM |
| 4355U, // ST3D |
| 4803U, // ST3D_IMM |
| 4419U, // ST3H |
| 4803U, // ST3H_IMM |
| 0U, // ST3Threev16b |
| 0U, // ST3Threev16b_POST |
| 0U, // ST3Threev2d |
| 0U, // ST3Threev2d_POST |
| 0U, // ST3Threev2s |
| 0U, // ST3Threev2s_POST |
| 0U, // ST3Threev4h |
| 0U, // ST3Threev4h_POST |
| 0U, // ST3Threev4s |
| 0U, // ST3Threev4s_POST |
| 0U, // ST3Threev8b |
| 0U, // ST3Threev8b_POST |
| 0U, // ST3Threev8h |
| 0U, // ST3Threev8h_POST |
| 4675U, // ST3W |
| 4803U, // ST3W_IMM |
| 0U, // ST3i16 |
| 0U, // ST3i16_POST |
| 0U, // ST3i32 |
| 0U, // ST3i32_POST |
| 0U, // ST3i64 |
| 0U, // ST3i64_POST |
| 0U, // ST3i8 |
| 0U, // ST3i8_POST |
| 4291U, // ST4B |
| 127619U, // ST4B_IMM |
| 4355U, // ST4D |
| 127619U, // ST4D_IMM |
| 0U, // ST4Fourv16b |
| 0U, // ST4Fourv16b_POST |
| 0U, // ST4Fourv2d |
| 0U, // ST4Fourv2d_POST |
| 0U, // ST4Fourv2s |
| 0U, // ST4Fourv2s_POST |
| 0U, // ST4Fourv4h |
| 0U, // ST4Fourv4h_POST |
| 0U, // ST4Fourv4s |
| 0U, // ST4Fourv4s_POST |
| 0U, // ST4Fourv8b |
| 0U, // ST4Fourv8b_POST |
| 0U, // ST4Fourv8h |
| 0U, // ST4Fourv8h_POST |
| 4419U, // ST4H |
| 127619U, // ST4H_IMM |
| 4675U, // ST4W |
| 127619U, // ST4W_IMM |
| 0U, // ST4i16 |
| 0U, // ST4i16_POST |
| 0U, // ST4i32 |
| 0U, // ST4i32_POST |
| 0U, // ST4i64 |
| 0U, // ST4i64_POST |
| 0U, // ST4i8 |
| 0U, // ST4i8_POST |
| 27U, // STLLRB |
| 27U, // STLLRH |
| 27U, // STLLRW |
| 27U, // STLLRX |
| 27U, // STLRB |
| 27U, // STLRH |
| 27U, // STLRW |
| 27U, // STLRX |
| 49411U, // STLURBi |
| 49411U, // STLURHi |
| 49411U, // STLURWi |
| 49411U, // STLURXi |
| 147715U, // STLXPW |
| 147715U, // STLXPX |
| 49417U, // STLXRB |
| 49417U, // STLXRH |
| 49417U, // STLXRW |
| 49417U, // STLXRX |
| 4735241U, // STNPDi |
| 4997385U, // STNPQi |
| 5259529U, // STNPSi |
| 5259529U, // STNPWi |
| 4735241U, // STNPXi |
| 125187U, // STNT1B_ZRI |
| 4291U, // STNT1B_ZRR |
| 125187U, // STNT1D_ZRI |
| 4355U, // STNT1D_ZRR |
| 125187U, // STNT1H_ZRI |
| 4419U, // STNT1H_ZRR |
| 125187U, // STNT1W_ZRI |
| 4675U, // STNT1W_ZRR |
| 4735241U, // STPDi |
| 5638409U, // STPDpost |
| 72632585U, // STPDpre |
| 4997385U, // STPQi |
| 5900553U, // STPQpost |
| 72894729U, // STPQpre |
| 5259529U, // STPSi |
| 6162697U, // STPSpost |
| 73156873U, // STPSpre |
| 5259529U, // STPWi |
| 6162697U, // STPWpost |
| 73156873U, // STPWpre |
| 4735241U, // STPXi |
| 5638409U, // STPXpost |
| 72632585U, // STPXpre |
| 28U, // STRBBpost |
| 141571U, // STRBBpre |
| 6308099U, // STRBBroW |
| 6570243U, // STRBBroX |
| 4931U, // STRBBui |
| 28U, // STRBpost |
| 141571U, // STRBpre |
| 6308099U, // STRBroW |
| 6570243U, // STRBroX |
| 4931U, // STRBui |
| 28U, // STRDpost |
| 141571U, // STRDpre |
| 6832387U, // STRDroW |
| 7094531U, // STRDroX |
| 4995U, // STRDui |
| 28U, // STRHHpost |
| 141571U, // STRHHpre |
| 7356675U, // STRHHroW |
| 7618819U, // STRHHroX |
| 5059U, // STRHHui |
| 28U, // STRHpost |
| 141571U, // STRHpre |
| 7356675U, // STRHroW |
| 7618819U, // STRHroX |
| 5059U, // STRHui |
| 28U, // STRQpost |
| 141571U, // STRQpre |
| 7880963U, // STRQroW |
| 8143107U, // STRQroX |
| 5123U, // STRQui |
| 28U, // STRSpost |
| 141571U, // STRSpre |
| 8405251U, // STRSroW |
| 8667395U, // STRSroX |
| 5187U, // STRSui |
| 28U, // STRWpost |
| 141571U, // STRWpre |
| 8405251U, // STRWroW |
| 8667395U, // STRWroX |
| 5187U, // STRWui |
| 28U, // STRXpost |
| 141571U, // STRXpre |
| 6832387U, // STRXroW |
| 7094531U, // STRXroX |
| 4995U, // STRXui |
| 123139U, // STR_PXI |
| 123139U, // STR_ZXI |
| 49411U, // STTRBi |
| 49411U, // STTRHi |
| 49411U, // STTRWi |
| 49411U, // STTRXi |
| 49411U, // STURBBi |
| 49411U, // STURBi |
| 49411U, // STURDi |
| 49411U, // STURHHi |
| 49411U, // STURHi |
| 49411U, // STURQi |
| 49411U, // STURSi |
| 49411U, // STURWi |
| 49411U, // STURXi |
| 147715U, // STXPW |
| 147715U, // STXPX |
| 49417U, // STXRB |
| 49417U, // STXRH |
| 49417U, // STXRW |
| 49417U, // STXRX |
| 323U, // SUBHNv2i64_v2i32 |
| 387U, // SUBHNv2i64_v4i32 |
| 323U, // SUBHNv4i32_v4i16 |
| 387U, // SUBHNv4i32_v8i16 |
| 387U, // SUBHNv8i16_v16i8 |
| 323U, // SUBHNv8i16_v8i8 |
| 643U, // SUBR_ZI_B |
| 707U, // SUBR_ZI_D |
| 4U, // SUBR_ZI_H |
| 771U, // SUBR_ZI_S |
| 17216U, // SUBR_ZPmZ_B |
| 279424U, // SUBR_ZPmZ_D |
| 549829U, // SUBR_ZPmZ_H |
| 803840U, // SUBR_ZPmZ_S |
| 451U, // SUBSWri |
| 0U, // SUBSWrr |
| 515U, // SUBSWrs |
| 579U, // SUBSWrx |
| 451U, // SUBSXri |
| 0U, // SUBSXrr |
| 515U, // SUBSXrs |
| 579U, // SUBSXrx |
| 8451U, // SUBSXrx64 |
| 451U, // SUBWri |
| 0U, // SUBWrr |
| 515U, // SUBWrs |
| 579U, // SUBWrx |
| 451U, // SUBXri |
| 0U, // SUBXrr |
| 515U, // SUBXrs |
| 579U, // SUBXrx |
| 8451U, // SUBXrx64 |
| 643U, // SUB_ZI_B |
| 707U, // SUB_ZI_D |
| 4U, // SUB_ZI_H |
| 771U, // SUB_ZI_S |
| 17216U, // SUB_ZPmZ_B |
| 279424U, // SUB_ZPmZ_D |
| 549829U, // SUB_ZPmZ_H |
| 803840U, // SUB_ZPmZ_S |
| 835U, // SUB_ZZZ_B |
| 899U, // SUB_ZZZ_D |
| 133U, // SUB_ZZZ_H |
| 1027U, // SUB_ZZZ_S |
| 323U, // SUBv16i8 |
| 259U, // SUBv1i64 |
| 323U, // SUBv2i32 |
| 323U, // SUBv2i64 |
| 323U, // SUBv4i16 |
| 323U, // SUBv4i32 |
| 323U, // SUBv8i16 |
| 323U, // SUBv8i8 |
| 2U, // SUNPKHI_ZZ_D |
| 0U, // SUNPKHI_ZZ_H |
| 2U, // SUNPKHI_ZZ_S |
| 2U, // SUNPKLO_ZZ_D |
| 0U, // SUNPKLO_ZZ_H |
| 2U, // SUNPKLO_ZZ_S |
| 2U, // SUQADDv16i8 |
| 2U, // SUQADDv1i16 |
| 2U, // SUQADDv1i32 |
| 2U, // SUQADDv1i64 |
| 2U, // SUQADDv1i8 |
| 2U, // SUQADDv2i32 |
| 2U, // SUQADDv2i64 |
| 2U, // SUQADDv4i16 |
| 2U, // SUQADDv4i32 |
| 2U, // SUQADDv8i16 |
| 2U, // SUQADDv8i8 |
| 0U, // SVC |
| 0U, // SWPAB |
| 0U, // SWPAH |
| 0U, // SWPALB |
| 0U, // SWPALH |
| 0U, // SWPALW |
| 0U, // SWPALX |
| 0U, // SWPAW |
| 0U, // SWPAX |
| 0U, // SWPB |
| 0U, // SWPH |
| 0U, // SWPLB |
| 0U, // SWPLH |
| 0U, // SWPLW |
| 0U, // SWPLX |
| 0U, // SWPW |
| 0U, // SWPX |
| 64U, // SXTB_ZPmZ_D |
| 129U, // SXTB_ZPmZ_H |
| 192U, // SXTB_ZPmZ_S |
| 64U, // SXTH_ZPmZ_D |
| 192U, // SXTH_ZPmZ_S |
| 64U, // SXTW_ZPmZ_D |
| 5379U, // SYSLxt |
| 0U, // SYSxt |
| 0U, // TBL_ZZZ_B |
| 0U, // TBL_ZZZ_D |
| 0U, // TBL_ZZZ_H |
| 0U, // TBL_ZZZ_S |
| 59U, // TBLv16i8Four |
| 59U, // TBLv16i8One |
| 59U, // TBLv16i8Three |
| 59U, // TBLv16i8Two |
| 60U, // TBLv8i8Four |
| 60U, // TBLv8i8One |
| 60U, // TBLv8i8Three |
| 60U, // TBLv8i8Two |
| 5443U, // TBNZW |
| 5443U, // TBNZX |
| 59U, // TBXv16i8Four |
| 59U, // TBXv16i8One |
| 59U, // TBXv16i8Three |
| 59U, // TBXv16i8Two |
| 60U, // TBXv8i8Four |
| 60U, // TBXv8i8One |
| 60U, // TBXv8i8Three |
| 60U, // TBXv8i8Two |
| 5443U, // TBZW |
| 5443U, // TBZX |
| 0U, // TCRETURNdi |
| 0U, // TCRETURNri |
| 0U, // TLSDESCCALL |
| 0U, // TLSDESC_CALLSEQ |
| 835U, // TRN1_PPP_B |
| 899U, // TRN1_PPP_D |
| 133U, // TRN1_PPP_H |
| 1027U, // TRN1_PPP_S |
| 835U, // TRN1_ZZZ_B |
| 899U, // TRN1_ZZZ_D |
| 133U, // TRN1_ZZZ_H |
| 1027U, // TRN1_ZZZ_S |
| 323U, // TRN1v16i8 |
| 323U, // TRN1v2i32 |
| 323U, // TRN1v2i64 |
| 323U, // TRN1v4i16 |
| 323U, // TRN1v4i32 |
| 323U, // TRN1v8i16 |
| 323U, // TRN1v8i8 |
| 835U, // TRN2_PPP_B |
| 899U, // TRN2_PPP_D |
| 133U, // TRN2_PPP_H |
| 1027U, // TRN2_PPP_S |
| 835U, // TRN2_ZZZ_B |
| 899U, // TRN2_ZZZ_D |
| 133U, // TRN2_ZZZ_H |
| 1027U, // TRN2_ZZZ_S |
| 323U, // TRN2v16i8 |
| 323U, // TRN2v2i32 |
| 323U, // TRN2v2i64 |
| 323U, // TRN2v4i16 |
| 323U, // TRN2v4i32 |
| 323U, // TRN2v8i16 |
| 323U, // TRN2v8i8 |
| 0U, // TSB |
| 387U, // UABALv16i8_v8i16 |
| 387U, // UABALv2i32_v2i64 |
| 387U, // UABALv4i16_v4i32 |
| 387U, // UABALv4i32_v2i64 |
| 387U, // UABALv8i16_v4i32 |
| 387U, // UABALv8i8_v8i16 |
| 387U, // UABAv16i8 |
| 387U, // UABAv2i32 |
| 387U, // UABAv4i16 |
| 387U, // UABAv4i32 |
| 387U, // UABAv8i16 |
| 387U, // UABAv8i8 |
| 323U, // UABDLv16i8_v8i16 |
| 323U, // UABDLv2i32_v2i64 |
| 323U, // UABDLv4i16_v4i32 |
| 323U, // UABDLv4i32_v2i64 |
| 323U, // UABDLv8i16_v4i32 |
| 323U, // UABDLv8i8_v8i16 |
| 17216U, // UABD_ZPmZ_B |
| 279424U, // UABD_ZPmZ_D |
| 549829U, // UABD_ZPmZ_H |
| 803840U, // UABD_ZPmZ_S |
| 323U, // UABDv16i8 |
| 323U, // UABDv2i32 |
| 323U, // UABDv4i16 |
| 323U, // UABDv4i32 |
| 323U, // UABDv8i16 |
| 323U, // UABDv8i8 |
| 2U, // UADALPv16i8_v8i16 |
| 2U, // UADALPv2i32_v1i64 |
| 2U, // UADALPv4i16_v2i32 |
| 2U, // UADALPv4i32_v2i64 |
| 2U, // UADALPv8i16_v4i32 |
| 2U, // UADALPv8i8_v4i16 |
| 2U, // UADDLPv16i8_v8i16 |
| 2U, // UADDLPv2i32_v1i64 |
| 2U, // UADDLPv4i16_v2i32 |
| 2U, // UADDLPv4i32_v2i64 |
| 2U, // UADDLPv8i16_v4i32 |
| 2U, // UADDLPv8i8_v4i16 |
| 2U, // UADDLVv16i8v |
| 2U, // UADDLVv4i16v |
| 2U, // UADDLVv4i32v |
| 2U, // UADDLVv8i16v |
| 2U, // UADDLVv8i8v |
| 323U, // UADDLv16i8_v8i16 |
| 323U, // UADDLv2i32_v2i64 |
| 323U, // UADDLv4i16_v4i32 |
| 323U, // UADDLv4i32_v2i64 |
| 323U, // UADDLv8i16_v4i32 |
| 323U, // UADDLv8i8_v8i16 |
| 835U, // UADDV_VPZ_B |
| 899U, // UADDV_VPZ_D |
| 2243U, // UADDV_VPZ_H |
| 1027U, // UADDV_VPZ_S |
| 323U, // UADDWv16i8_v8i16 |
| 323U, // UADDWv2i32_v2i64 |
| 323U, // UADDWv4i16_v4i32 |
| 323U, // UADDWv4i32_v2i64 |
| 323U, // UADDWv8i16_v4i32 |
| 323U, // UADDWv8i8_v8i16 |
| 1065219U, // UBFMWri |
| 1065219U, // UBFMXri |
| 259U, // UCVTFSWDri |
| 259U, // UCVTFSWHri |
| 259U, // UCVTFSWSri |
| 259U, // UCVTFSXDri |
| 259U, // UCVTFSXHri |
| 259U, // UCVTFSXSri |
| 2U, // UCVTFUWDri |
| 2U, // UCVTFUWHri |
| 2U, // UCVTFUWSri |
| 2U, // UCVTFUXDri |
| 2U, // UCVTFUXHri |
| 2U, // UCVTFUXSri |
| 64U, // UCVTF_ZPmZ_DtoD |
| 151U, // UCVTF_ZPmZ_DtoH |
| 64U, // UCVTF_ZPmZ_DtoS |
| 129U, // UCVTF_ZPmZ_HtoH |
| 192U, // UCVTF_ZPmZ_StoD |
| 146U, // UCVTF_ZPmZ_StoH |
| 192U, // UCVTF_ZPmZ_StoS |
| 259U, // UCVTFd |
| 259U, // UCVTFh |
| 259U, // UCVTFs |
| 2U, // UCVTFv1i16 |
| 2U, // UCVTFv1i32 |
| 2U, // UCVTFv1i64 |
| 2U, // UCVTFv2f32 |
| 2U, // UCVTFv2f64 |
| 259U, // UCVTFv2i32_shift |
| 259U, // UCVTFv2i64_shift |
| 2U, // UCVTFv4f16 |
| 2U, // UCVTFv4f32 |
| 259U, // UCVTFv4i16_shift |
| 259U, // UCVTFv4i32_shift |
| 2U, // UCVTFv8f16 |
| 259U, // UCVTFv8i16_shift |
| 279424U, // UDIVR_ZPmZ_D |
| 803840U, // UDIVR_ZPmZ_S |
| 259U, // UDIVWr |
| 259U, // UDIVXr |
| 279424U, // UDIV_ZPmZ_D |
| 803840U, // UDIV_ZPmZ_S |
| 55U, // UDOT_ZZZI_D |
| 55U, // UDOT_ZZZI_S |
| 2U, // UDOT_ZZZ_D |
| 2U, // UDOT_ZZZ_S |
| 614787U, // UDOTlanev16i8 |
| 614787U, // UDOTlanev8i8 |
| 0U, // UDOTv16i8 |
| 0U, // UDOTv8i8 |
| 323U, // UHADDv16i8 |
| 323U, // UHADDv2i32 |
| 323U, // UHADDv4i16 |
| 323U, // UHADDv4i32 |
| 323U, // UHADDv8i16 |
| 323U, // UHADDv8i8 |
| 323U, // UHSUBv16i8 |
| 323U, // UHSUBv2i32 |
| 323U, // UHSUBv4i16 |
| 323U, // UHSUBv4i32 |
| 323U, // UHSUBv8i16 |
| 323U, // UHSUBv8i8 |
| 1065219U, // UMADDLrrr |
| 323U, // UMAXPv16i8 |
| 323U, // UMAXPv2i32 |
| 323U, // UMAXPv4i16 |
| 323U, // UMAXPv4i32 |
| 323U, // UMAXPv8i16 |
| 323U, // UMAXPv8i8 |
| 835U, // UMAXV_VPZ_B |
| 899U, // UMAXV_VPZ_D |
| 2243U, // UMAXV_VPZ_H |
| 1027U, // UMAXV_VPZ_S |
| 2U, // UMAXVv16i8v |
| 2U, // UMAXVv4i16v |
| 2U, // UMAXVv4i32v |
| 2U, // UMAXVv8i16v |
| 2U, // UMAXVv8i8v |
| 5507U, // UMAX_ZI_B |
| 5507U, // UMAX_ZI_D |
| 61U, // UMAX_ZI_H |
| 5507U, // UMAX_ZI_S |
| 17216U, // UMAX_ZPmZ_B |
| 279424U, // UMAX_ZPmZ_D |
| 549829U, // UMAX_ZPmZ_H |
| 803840U, // UMAX_ZPmZ_S |
| 323U, // UMAXv16i8 |
| 323U, // UMAXv2i32 |
| 323U, // UMAXv4i16 |
| 323U, // UMAXv4i32 |
| 323U, // UMAXv8i16 |
| 323U, // UMAXv8i8 |
| 323U, // UMINPv16i8 |
| 323U, // UMINPv2i32 |
| 323U, // UMINPv4i16 |
| 323U, // UMINPv4i32 |
| 323U, // UMINPv8i16 |
| 323U, // UMINPv8i8 |
| 835U, // UMINV_VPZ_B |
| 899U, // UMINV_VPZ_D |
| 2243U, // UMINV_VPZ_H |
| 1027U, // UMINV_VPZ_S |
| 2U, // UMINVv16i8v |
| 2U, // UMINVv4i16v |
| 2U, // UMINVv4i32v |
| 2U, // UMINVv8i16v |
| 2U, // UMINVv8i8v |
| 5507U, // UMIN_ZI_B |
| 5507U, // UMIN_ZI_D |
| 61U, // UMIN_ZI_H |
| 5507U, // UMIN_ZI_S |
| 17216U, // UMIN_ZPmZ_B |
| 279424U, // UMIN_ZPmZ_D |
| 549829U, // UMIN_ZPmZ_H |
| 803840U, // UMIN_ZPmZ_S |
| 323U, // UMINv16i8 |
| 323U, // UMINv2i32 |
| 323U, // UMINv4i16 |
| 323U, // UMINv4i32 |
| 323U, // UMINv8i16 |
| 323U, // UMINv8i8 |
| 387U, // UMLALv16i8_v8i16 |
| 614787U, // UMLALv2i32_indexed |
| 387U, // UMLALv2i32_v2i64 |
| 614787U, // UMLALv4i16_indexed |
| 387U, // UMLALv4i16_v4i32 |
| 614787U, // UMLALv4i32_indexed |
| 387U, // UMLALv4i32_v2i64 |
| 614787U, // UMLALv8i16_indexed |
| 387U, // UMLALv8i16_v4i32 |
| 387U, // UMLALv8i8_v8i16 |
| 387U, // UMLSLv16i8_v8i16 |
| 614787U, // UMLSLv2i32_indexed |
| 387U, // UMLSLv2i32_v2i64 |
| 614787U, // UMLSLv4i16_indexed |
| 387U, // UMLSLv4i16_v4i32 |
| 614787U, // UMLSLv4i32_indexed |
| 387U, // UMLSLv4i32_v2i64 |
| 614787U, // UMLSLv8i16_indexed |
| 387U, // UMLSLv8i16_v4i32 |
| 387U, // UMLSLv8i8_v8i16 |
| 15U, // UMOVvi16 |
| 15U, // UMOVvi32 |
| 15U, // UMOVvi64 |
| 15U, // UMOVvi8 |
| 1065219U, // UMSUBLrrr |
| 17216U, // UMULH_ZPmZ_B |
| 279424U, // UMULH_ZPmZ_D |
| 549829U, // UMULH_ZPmZ_H |
| 803840U, // UMULH_ZPmZ_S |
| 259U, // UMULHrr |
| 323U, // UMULLv16i8_v8i16 |
| 106819U, // UMULLv2i32_indexed |
| 323U, // UMULLv2i32_v2i64 |
| 106819U, // UMULLv4i16_indexed |
| 323U, // UMULLv4i16_v4i32 |
| 106819U, // UMULLv4i32_indexed |
| 323U, // UMULLv4i32_v2i64 |
| 106819U, // UMULLv8i16_indexed |
| 323U, // UMULLv8i16_v4i32 |
| 323U, // UMULLv8i8_v8i16 |
| 643U, // UQADD_ZI_B |
| 707U, // UQADD_ZI_D |
| 4U, // UQADD_ZI_H |
| 771U, // UQADD_ZI_S |
| 835U, // UQADD_ZZZ_B |
| 899U, // UQADD_ZZZ_D |
| 133U, // UQADD_ZZZ_H |
| 1027U, // UQADD_ZZZ_S |
| 323U, // UQADDv16i8 |
| 259U, // UQADDv1i16 |
| 259U, // UQADDv1i32 |
| 259U, // UQADDv1i64 |
| 259U, // UQADDv1i8 |
| 323U, // UQADDv2i32 |
| 323U, // UQADDv2i64 |
| 323U, // UQADDv4i16 |
| 323U, // UQADDv4i32 |
| 323U, // UQADDv8i16 |
| 323U, // UQADDv8i8 |
| 0U, // UQDECB_WPiI |
| 0U, // UQDECB_XPiI |
| 0U, // UQDECD_WPiI |
| 0U, // UQDECD_XPiI |
| 0U, // UQDECD_ZPiI |
| 0U, // UQDECH_WPiI |
| 0U, // UQDECH_XPiI |
| 0U, // UQDECH_ZPiI |
| 2U, // UQDECP_WP_B |
| 2U, // UQDECP_WP_D |
| 2U, // UQDECP_WP_H |
| 2U, // UQDECP_WP_S |
| 2U, // UQDECP_XP_B |
| 2U, // UQDECP_XP_D |
| 2U, // UQDECP_XP_H |
| 2U, // UQDECP_XP_S |
| 2U, // UQDECP_ZP_D |
| 0U, // UQDECP_ZP_H |
| 2U, // UQDECP_ZP_S |
| 0U, // UQDECW_WPiI |
| 0U, // UQDECW_XPiI |
| 0U, // UQDECW_ZPiI |
| 0U, // UQINCB_WPiI |
| 0U, // UQINCB_XPiI |
| 0U, // UQINCD_WPiI |
| 0U, // UQINCD_XPiI |
| 0U, // UQINCD_ZPiI |
| 0U, // UQINCH_WPiI |
| 0U, // UQINCH_XPiI |
| 0U, // UQINCH_ZPiI |
| 2U, // UQINCP_WP_B |
| 2U, // UQINCP_WP_D |
| 2U, // UQINCP_WP_H |
| 2U, // UQINCP_WP_S |
| 2U, // UQINCP_XP_B |
| 2U, // UQINCP_XP_D |
| 2U, // UQINCP_XP_H |
| 2U, // UQINCP_XP_S |
| 2U, // UQINCP_ZP_D |
| 0U, // UQINCP_ZP_H |
| 2U, // UQINCP_ZP_S |
| 0U, // UQINCW_WPiI |
| 0U, // UQINCW_XPiI |
| 0U, // UQINCW_ZPiI |
| 323U, // UQRSHLv16i8 |
| 259U, // UQRSHLv1i16 |
| 259U, // UQRSHLv1i32 |
| 259U, // UQRSHLv1i64 |
| 259U, // UQRSHLv1i8 |
| 323U, // UQRSHLv2i32 |
| 323U, // UQRSHLv2i64 |
| 323U, // UQRSHLv4i16 |
| 323U, // UQRSHLv4i32 |
| 323U, // UQRSHLv8i16 |
| 323U, // UQRSHLv8i8 |
| 259U, // UQRSHRNb |
| 259U, // UQRSHRNh |
| 259U, // UQRSHRNs |
| 2307U, // UQRSHRNv16i8_shift |
| 259U, // UQRSHRNv2i32_shift |
| 259U, // UQRSHRNv4i16_shift |
| 2307U, // UQRSHRNv4i32_shift |
| 2307U, // UQRSHRNv8i16_shift |
| 259U, // UQRSHRNv8i8_shift |
| 259U, // UQSHLb |
| 259U, // UQSHLd |
| 259U, // UQSHLh |
| 259U, // UQSHLs |
| 323U, // UQSHLv16i8 |
| 259U, // UQSHLv16i8_shift |
| 259U, // UQSHLv1i16 |
| 259U, // UQSHLv1i32 |
| 259U, // UQSHLv1i64 |
| 259U, // UQSHLv1i8 |
| 323U, // UQSHLv2i32 |
| 259U, // UQSHLv2i32_shift |
| 323U, // UQSHLv2i64 |
| 259U, // UQSHLv2i64_shift |
| 323U, // UQSHLv4i16 |
| 259U, // UQSHLv4i16_shift |
| 323U, // UQSHLv4i32 |
| 259U, // UQSHLv4i32_shift |
| 323U, // UQSHLv8i16 |
| 259U, // UQSHLv8i16_shift |
| 323U, // UQSHLv8i8 |
| 259U, // UQSHLv8i8_shift |
| 259U, // UQSHRNb |
| 259U, // UQSHRNh |
| 259U, // UQSHRNs |
| 2307U, // UQSHRNv16i8_shift |
| 259U, // UQSHRNv2i32_shift |
| 259U, // UQSHRNv4i16_shift |
| 2307U, // UQSHRNv4i32_shift |
| 2307U, // UQSHRNv8i16_shift |
| 259U, // UQSHRNv8i8_shift |
| 643U, // UQSUB_ZI_B |
| 707U, // UQSUB_ZI_D |
| 4U, // UQSUB_ZI_H |
| 771U, // UQSUB_ZI_S |
| 835U, // UQSUB_ZZZ_B |
| 899U, // UQSUB_ZZZ_D |
| 133U, // UQSUB_ZZZ_H |
| 1027U, // UQSUB_ZZZ_S |
| 323U, // UQSUBv16i8 |
| 259U, // UQSUBv1i16 |
| 259U, // UQSUBv1i32 |
| 259U, // UQSUBv1i64 |
| 259U, // UQSUBv1i8 |
| 323U, // UQSUBv2i32 |
| 323U, // UQSUBv2i64 |
| 323U, // UQSUBv4i16 |
| 323U, // UQSUBv4i32 |
| 323U, // UQSUBv8i16 |
| 323U, // UQSUBv8i8 |
| 2U, // UQXTNv16i8 |
| 2U, // UQXTNv1i16 |
| 2U, // UQXTNv1i32 |
| 2U, // UQXTNv1i8 |
| 2U, // UQXTNv2i32 |
| 2U, // UQXTNv4i16 |
| 2U, // UQXTNv4i32 |
| 2U, // UQXTNv8i16 |
| 2U, // UQXTNv8i8 |
| 2U, // URECPEv2i32 |
| 2U, // URECPEv4i32 |
| 323U, // URHADDv16i8 |
| 323U, // URHADDv2i32 |
| 323U, // URHADDv4i16 |
| 323U, // URHADDv4i32 |
| 323U, // URHADDv8i16 |
| 323U, // URHADDv8i8 |
| 323U, // URSHLv16i8 |
| 259U, // URSHLv1i64 |
| 323U, // URSHLv2i32 |
| 323U, // URSHLv2i64 |
| 323U, // URSHLv4i16 |
| 323U, // URSHLv4i32 |
| 323U, // URSHLv8i16 |
| 323U, // URSHLv8i8 |
| 259U, // URSHRd |
| 259U, // URSHRv16i8_shift |
| 259U, // URSHRv2i32_shift |
| 259U, // URSHRv2i64_shift |
| 259U, // URSHRv4i16_shift |
| 259U, // URSHRv4i32_shift |
| 259U, // URSHRv8i16_shift |
| 259U, // URSHRv8i8_shift |
| 2U, // URSQRTEv2i32 |
| 2U, // URSQRTEv4i32 |
| 2307U, // URSRAd |
| 2307U, // URSRAv16i8_shift |
| 2307U, // URSRAv2i32_shift |
| 2307U, // URSRAv2i64_shift |
| 2307U, // URSRAv4i16_shift |
| 2307U, // URSRAv4i32_shift |
| 2307U, // URSRAv8i16_shift |
| 2307U, // URSRAv8i8_shift |
| 259U, // USHLLv16i8_shift |
| 259U, // USHLLv2i32_shift |
| 259U, // USHLLv4i16_shift |
| 259U, // USHLLv4i32_shift |
| 259U, // USHLLv8i16_shift |
| 259U, // USHLLv8i8_shift |
| 323U, // USHLv16i8 |
| 259U, // USHLv1i64 |
| 323U, // USHLv2i32 |
| 323U, // USHLv2i64 |
| 323U, // USHLv4i16 |
| 323U, // USHLv4i32 |
| 323U, // USHLv8i16 |
| 323U, // USHLv8i8 |
| 259U, // USHRd |
| 259U, // USHRv16i8_shift |
| 259U, // USHRv2i32_shift |
| 259U, // USHRv2i64_shift |
| 259U, // USHRv4i16_shift |
| 259U, // USHRv4i32_shift |
| 259U, // USHRv8i16_shift |
| 259U, // USHRv8i8_shift |
| 2U, // USQADDv16i8 |
| 2U, // USQADDv1i16 |
| 2U, // USQADDv1i32 |
| 2U, // USQADDv1i64 |
| 2U, // USQADDv1i8 |
| 2U, // USQADDv2i32 |
| 2U, // USQADDv2i64 |
| 2U, // USQADDv4i16 |
| 2U, // USQADDv4i32 |
| 2U, // USQADDv8i16 |
| 2U, // USQADDv8i8 |
| 2307U, // USRAd |
| 2307U, // USRAv16i8_shift |
| 2307U, // USRAv2i32_shift |
| 2307U, // USRAv2i64_shift |
| 2307U, // USRAv4i16_shift |
| 2307U, // USRAv4i32_shift |
| 2307U, // USRAv8i16_shift |
| 2307U, // USRAv8i8_shift |
| 323U, // USUBLv16i8_v8i16 |
| 323U, // USUBLv2i32_v2i64 |
| 323U, // USUBLv4i16_v4i32 |
| 323U, // USUBLv4i32_v2i64 |
| 323U, // USUBLv8i16_v4i32 |
| 323U, // USUBLv8i8_v8i16 |
| 323U, // USUBWv16i8_v8i16 |
| 323U, // USUBWv2i32_v2i64 |
| 323U, // USUBWv4i16_v4i32 |
| 323U, // USUBWv4i32_v2i64 |
| 323U, // USUBWv8i16_v4i32 |
| 323U, // USUBWv8i8_v8i16 |
| 2U, // UUNPKHI_ZZ_D |
| 0U, // UUNPKHI_ZZ_H |
| 2U, // UUNPKHI_ZZ_S |
| 2U, // UUNPKLO_ZZ_D |
| 0U, // UUNPKLO_ZZ_H |
| 2U, // UUNPKLO_ZZ_S |
| 64U, // UXTB_ZPmZ_D |
| 129U, // UXTB_ZPmZ_H |
| 192U, // UXTB_ZPmZ_S |
| 64U, // UXTH_ZPmZ_D |
| 192U, // UXTH_ZPmZ_S |
| 64U, // UXTW_ZPmZ_D |
| 835U, // UZP1_PPP_B |
| 899U, // UZP1_PPP_D |
| 133U, // UZP1_PPP_H |
| 1027U, // UZP1_PPP_S |
| 835U, // UZP1_ZZZ_B |
| 899U, // UZP1_ZZZ_D |
| 133U, // UZP1_ZZZ_H |
| 1027U, // UZP1_ZZZ_S |
| 323U, // UZP1v16i8 |
| 323U, // UZP1v2i32 |
| 323U, // UZP1v2i64 |
| 323U, // UZP1v4i16 |
| 323U, // UZP1v4i32 |
| 323U, // UZP1v8i16 |
| 323U, // UZP1v8i8 |
| 835U, // UZP2_PPP_B |
| 899U, // UZP2_PPP_D |
| 133U, // UZP2_PPP_H |
| 1027U, // UZP2_PPP_S |
| 835U, // UZP2_ZZZ_B |
| 899U, // UZP2_ZZZ_D |
| 133U, // UZP2_ZZZ_H |
| 1027U, // UZP2_ZZZ_S |
| 323U, // UZP2v16i8 |
| 323U, // UZP2v2i32 |
| 323U, // UZP2v2i64 |
| 323U, // UZP2v4i16 |
| 323U, // UZP2v4i32 |
| 323U, // UZP2v8i16 |
| 323U, // UZP2v8i8 |
| 259U, // WHILELE_PWW_B |
| 259U, // WHILELE_PWW_D |
| 8U, // WHILELE_PWW_H |
| 259U, // WHILELE_PWW_S |
| 259U, // WHILELE_PXX_B |
| 259U, // WHILELE_PXX_D |
| 8U, // WHILELE_PXX_H |
| 259U, // WHILELE_PXX_S |
| 259U, // WHILELO_PWW_B |
| 259U, // WHILELO_PWW_D |
| 8U, // WHILELO_PWW_H |
| 259U, // WHILELO_PWW_S |
| 259U, // WHILELO_PXX_B |
| 259U, // WHILELO_PXX_D |
| 8U, // WHILELO_PXX_H |
| 259U, // WHILELO_PXX_S |
| 259U, // WHILELS_PWW_B |
| 259U, // WHILELS_PWW_D |
| 8U, // WHILELS_PWW_H |
| 259U, // WHILELS_PWW_S |
| 259U, // WHILELS_PXX_B |
| 259U, // WHILELS_PXX_D |
| 8U, // WHILELS_PXX_H |
| 259U, // WHILELS_PXX_S |
| 259U, // WHILELT_PWW_B |
| 259U, // WHILELT_PWW_D |
| 8U, // WHILELT_PWW_H |
| 259U, // WHILELT_PWW_S |
| 259U, // WHILELT_PXX_B |
| 259U, // WHILELT_PXX_D |
| 8U, // WHILELT_PXX_H |
| 259U, // WHILELT_PXX_S |
| 0U, // WRFFR |
| 0U, // XAR |
| 0U, // XPACD |
| 0U, // XPACI |
| 0U, // XPACLRI |
| 2U, // XTNv16i8 |
| 2U, // XTNv2i32 |
| 2U, // XTNv4i16 |
| 2U, // XTNv4i32 |
| 2U, // XTNv8i16 |
| 2U, // XTNv8i8 |
| 835U, // ZIP1_PPP_B |
| 899U, // ZIP1_PPP_D |
| 133U, // ZIP1_PPP_H |
| 1027U, // ZIP1_PPP_S |
| 835U, // ZIP1_ZZZ_B |
| 899U, // ZIP1_ZZZ_D |
| 133U, // ZIP1_ZZZ_H |
| 1027U, // ZIP1_ZZZ_S |
| 323U, // ZIP1v16i8 |
| 323U, // ZIP1v2i32 |
| 323U, // ZIP1v2i64 |
| 323U, // ZIP1v4i16 |
| 323U, // ZIP1v4i32 |
| 323U, // ZIP1v8i16 |
| 323U, // ZIP1v8i8 |
| 835U, // ZIP2_PPP_B |
| 899U, // ZIP2_PPP_D |
| 133U, // ZIP2_PPP_H |
| 1027U, // ZIP2_PPP_S |
| 835U, // ZIP2_ZZZ_B |
| 899U, // ZIP2_ZZZ_D |
| 133U, // ZIP2_ZZZ_H |
| 1027U, // ZIP2_ZZZ_S |
| 323U, // ZIP2v16i8 |
| 323U, // ZIP2v2i32 |
| 323U, // ZIP2v2i64 |
| 323U, // ZIP2v4i16 |
| 323U, // ZIP2v4i32 |
| 323U, // ZIP2v8i16 |
| 323U, // ZIP2v8i8 |
| 835U, // anonymous_1349 |
| }; |
| |
| O << "\t"; |
| |
| // Emit the opcode for the instruction. |
| uint64_t Bits = 0; |
| Bits |= (uint64_t)OpInfo0[MI->getOpcode()] << 0; |
| Bits |= (uint64_t)OpInfo1[MI->getOpcode()] << 32; |
| assert(Bits != 0 && "Cannot print this instruction."); |
| O << AsmStrs+(Bits & 16383)-1; |
| |
| |
| // Fragment 0 encoded into 6 bits for 54 unique commands. |
| switch ((Bits >> 14) & 63) { |
| default: llvm_unreachable("Invalid command number."); |
| case 0: |
| // DBG_VALUE, DBG_LABEL, BUNDLE, LIFETIME_START, LIFETIME_END, FENTRY_CAL... |
| return; |
| break; |
| case 1: |
| // ABS_ZPmZ_B, ADD_ZI_B, ADD_ZPmZ_B, ADD_ZZZ_B, ANDS_PPzPP, AND_PPzPP, AN... |
| printSVERegOp<'b'>(MI, 0, STI, O); |
| break; |
| case 2: |
| // ABS_ZPmZ_D, ADD_ZI_D, ADD_ZPmZ_D, ADD_ZZZ_D, ADR_LSL_ZZZ_D_0, ADR_LSL_... |
| printSVERegOp<'d'>(MI, 0, STI, O); |
| break; |
| case 3: |
| // ABS_ZPmZ_H, ADD_ZI_H, ADD_ZPmZ_H, ADD_ZZZ_H, AND_ZPmZ_H, ASRD_ZPmI_H, ... |
| printSVERegOp<'h'>(MI, 0, STI, O); |
| O << ", "; |
| break; |
| case 4: |
| // ABS_ZPmZ_S, ADD_ZI_S, ADD_ZPmZ_S, ADD_ZZZ_S, ADR_LSL_ZZZ_S_0, ADR_LSL_... |
| printSVERegOp<'s'>(MI, 0, STI, O); |
| break; |
| case 5: |
| // ABSv16i8, ABSv2i32, ABSv2i64, ABSv4i16, ABSv4i32, ABSv8i16, ABSv8i8, A... |
| printVRegOperand(MI, 0, STI, O); |
| break; |
| case 6: |
| // ABSv1i64, ADCSWr, ADCSXr, ADCWr, ADCXr, ADDPL_XXI, ADDPv2i64p, ADDSWri... |
| printOperand(MI, 0, STI, O); |
| break; |
| case 7: |
| // ADDHNv2i64_v4i32, ADDHNv4i32_v8i16, ADDHNv8i16_v16i8, AESDrr, AESErr, ... |
| printVRegOperand(MI, 1, STI, O); |
| break; |
| case 8: |
| // B, BL |
| printAlignedLabel(MI, 0, STI, O); |
| return; |
| break; |
| case 9: |
| // BRK, DCPS1, DCPS2, DCPS3, HLT, HVC, SMC, SVC |
| printImmHex(MI, 0, STI, O); |
| return; |
| break; |
| case 10: |
| // Bcc |
| printCondCode(MI, 0, STI, O); |
| O << "\t"; |
| printAlignedLabel(MI, 1, STI, O); |
| return; |
| break; |
| case 11: |
| // CASAB, CASAH, CASALB, CASALH, CASALW, CASALX, CASAW, CASAX, CASB, CASH... |
| printOperand(MI, 1, STI, O); |
| break; |
| case 12: |
| // CASPALW, CASPAW, CASPLW, CASPW |
| printGPRSeqPairsClassOperand<32>(MI, 1, STI, O); |
| O << ", "; |
| printGPRSeqPairsClassOperand<32>(MI, 2, STI, O); |
| O << ", ["; |
| printOperand(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 13: |
| // CASPALX, CASPAX, CASPLX, CASPX |
| printGPRSeqPairsClassOperand<64>(MI, 1, STI, O); |
| O << ", "; |
| printGPRSeqPairsClassOperand<64>(MI, 2, STI, O); |
| O << ", ["; |
| printOperand(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 14: |
| // DMB, DSB, ISB, TSB |
| printBarrierOption(MI, 0, STI, O); |
| return; |
| break; |
| case 15: |
| // DUP_ZZI_Q |
| printSVERegOp<'q'>(MI, 0, STI, O); |
| O << ", "; |
| printSVERegOp<'q'>(MI, 1, STI, O); |
| printVectorIndex(MI, 2, STI, O); |
| return; |
| break; |
| case 16: |
| // GLD1B_D_IMM_REAL, GLD1B_D_REAL, GLD1B_D_SXTW_REAL, GLD1B_D_UXTW_REAL, ... |
| printTypedVectorList<0,'d'>(MI, 0, STI, O); |
| O << ", "; |
| printSVERegOp<>(MI, 1, STI, O); |
| break; |
| case 17: |
| // GLD1B_S_IMM_REAL, GLD1B_S_SXTW_REAL, GLD1B_S_UXTW_REAL, GLD1H_S_IMM_RE... |
| printTypedVectorList<0,'s'>(MI, 0, STI, O); |
| O << ", "; |
| printSVERegOp<>(MI, 1, STI, O); |
| break; |
| case 18: |
| // HINT |
| printImm(MI, 0, STI, O); |
| return; |
| break; |
| case 19: |
| // LD1B, LD1B_IMM_REAL, LD1RB_IMM, LD1RQ_B, LD1RQ_B_IMM, LD2B, LD2B_IMM, ... |
| printTypedVectorList<0,'b'>(MI, 0, STI, O); |
| O << ", "; |
| printSVERegOp<>(MI, 1, STI, O); |
| break; |
| case 20: |
| // LD1B_H, LD1B_H_IMM_REAL, LD1H, LD1H_IMM_REAL, LD1RB_H_IMM, LD1RH_IMM, ... |
| printTypedVectorList<0,'h'>(MI, 0, STI, O); |
| O << ", "; |
| printSVERegOp<>(MI, 1, STI, O); |
| break; |
| case 21: |
| // LD1Fourv16b, LD1Onev16b, LD1Rv16b, LD1Threev16b, LD1Twov16b, LD2Rv16b,... |
| printTypedVectorList<16, 'b'>(MI, 0, STI, O); |
| O << ", ["; |
| printOperand(MI, 1, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 22: |
| // LD1Fourv16b_POST, LD1Onev16b_POST, LD1Rv16b_POST, LD1Threev16b_POST, L... |
| printTypedVectorList<16, 'b'>(MI, 1, STI, O); |
| O << ", ["; |
| printOperand(MI, 2, STI, O); |
| O << "], "; |
| break; |
| case 23: |
| // LD1Fourv1d, LD1Onev1d, LD1Rv1d, LD1Threev1d, LD1Twov1d, LD2Rv1d, LD3Rv... |
| printTypedVectorList<1, 'd'>(MI, 0, STI, O); |
| O << ", ["; |
| printOperand(MI, 1, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 24: |
| // LD1Fourv1d_POST, LD1Onev1d_POST, LD1Rv1d_POST, LD1Threev1d_POST, LD1Tw... |
| printTypedVectorList<1, 'd'>(MI, 1, STI, O); |
| O << ", ["; |
| printOperand(MI, 2, STI, O); |
| O << "], "; |
| break; |
| case 25: |
| // LD1Fourv2d, LD1Onev2d, LD1Rv2d, LD1Threev2d, LD1Twov2d, LD2Rv2d, LD2Tw... |
| printTypedVectorList<2, 'd'>(MI, 0, STI, O); |
| O << ", ["; |
| printOperand(MI, 1, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 26: |
| // LD1Fourv2d_POST, LD1Onev2d_POST, LD1Rv2d_POST, LD1Threev2d_POST, LD1Tw... |
| printTypedVectorList<2, 'd'>(MI, 1, STI, O); |
| O << ", ["; |
| printOperand(MI, 2, STI, O); |
| O << "], "; |
| break; |
| case 27: |
| // LD1Fourv2s, LD1Onev2s, LD1Rv2s, LD1Threev2s, LD1Twov2s, LD2Rv2s, LD2Tw... |
| printTypedVectorList<2, 's'>(MI, 0, STI, O); |
| O << ", ["; |
| printOperand(MI, 1, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 28: |
| // LD1Fourv2s_POST, LD1Onev2s_POST, LD1Rv2s_POST, LD1Threev2s_POST, LD1Tw... |
| printTypedVectorList<2, 's'>(MI, 1, STI, O); |
| O << ", ["; |
| printOperand(MI, 2, STI, O); |
| O << "], "; |
| break; |
| case 29: |
| // LD1Fourv4h, LD1Onev4h, LD1Rv4h, LD1Threev4h, LD1Twov4h, LD2Rv4h, LD2Tw... |
| printTypedVectorList<4, 'h'>(MI, 0, STI, O); |
| O << ", ["; |
| printOperand(MI, 1, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 30: |
| // LD1Fourv4h_POST, LD1Onev4h_POST, LD1Rv4h_POST, LD1Threev4h_POST, LD1Tw... |
| printTypedVectorList<4, 'h'>(MI, 1, STI, O); |
| O << ", ["; |
| printOperand(MI, 2, STI, O); |
| O << "], "; |
| break; |
| case 31: |
| // LD1Fourv4s, LD1Onev4s, LD1Rv4s, LD1Threev4s, LD1Twov4s, LD2Rv4s, LD2Tw... |
| printTypedVectorList<4, 's'>(MI, 0, STI, O); |
| O << ", ["; |
| printOperand(MI, 1, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 32: |
| // LD1Fourv4s_POST, LD1Onev4s_POST, LD1Rv4s_POST, LD1Threev4s_POST, LD1Tw... |
| printTypedVectorList<4, 's'>(MI, 1, STI, O); |
| O << ", ["; |
| printOperand(MI, 2, STI, O); |
| O << "], "; |
| break; |
| case 33: |
| // LD1Fourv8b, LD1Onev8b, LD1Rv8b, LD1Threev8b, LD1Twov8b, LD2Rv8b, LD2Tw... |
| printTypedVectorList<8, 'b'>(MI, 0, STI, O); |
| O << ", ["; |
| printOperand(MI, 1, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 34: |
| // LD1Fourv8b_POST, LD1Onev8b_POST, LD1Rv8b_POST, LD1Threev8b_POST, LD1Tw... |
| printTypedVectorList<8, 'b'>(MI, 1, STI, O); |
| O << ", ["; |
| printOperand(MI, 2, STI, O); |
| O << "], "; |
| break; |
| case 35: |
| // LD1Fourv8h, LD1Onev8h, LD1Rv8h, LD1Threev8h, LD1Twov8h, LD2Rv8h, LD2Tw... |
| printTypedVectorList<8, 'h'>(MI, 0, STI, O); |
| O << ", ["; |
| printOperand(MI, 1, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 36: |
| // LD1Fourv8h_POST, LD1Onev8h_POST, LD1Rv8h_POST, LD1Threev8h_POST, LD1Tw... |
| printTypedVectorList<8, 'h'>(MI, 1, STI, O); |
| O << ", ["; |
| printOperand(MI, 2, STI, O); |
| O << "], "; |
| break; |
| case 37: |
| // LD1i16, LD2i16, LD3i16, LD4i16, ST1i16_POST, ST2i16_POST, ST3i16_POST,... |
| printTypedVectorList<0, 'h'>(MI, 1, STI, O); |
| printVectorIndex(MI, 2, STI, O); |
| O << ", ["; |
| printOperand(MI, 3, STI, O); |
| break; |
| case 38: |
| // LD1i16_POST, LD2i16_POST, LD3i16_POST, LD4i16_POST |
| printTypedVectorList<0, 'h'>(MI, 2, STI, O); |
| printVectorIndex(MI, 3, STI, O); |
| O << ", ["; |
| printOperand(MI, 4, STI, O); |
| O << "], "; |
| break; |
| case 39: |
| // LD1i32, LD2i32, LD3i32, LD4i32, ST1i32_POST, ST2i32_POST, ST3i32_POST,... |
| printTypedVectorList<0, 's'>(MI, 1, STI, O); |
| printVectorIndex(MI, 2, STI, O); |
| O << ", ["; |
| printOperand(MI, 3, STI, O); |
| break; |
| case 40: |
| // LD1i32_POST, LD2i32_POST, LD3i32_POST, LD4i32_POST |
| printTypedVectorList<0, 's'>(MI, 2, STI, O); |
| printVectorIndex(MI, 3, STI, O); |
| O << ", ["; |
| printOperand(MI, 4, STI, O); |
| O << "], "; |
| break; |
| case 41: |
| // LD1i64, LD2i64, LD3i64, LD4i64, ST1i64_POST, ST2i64_POST, ST3i64_POST,... |
| printTypedVectorList<0, 'd'>(MI, 1, STI, O); |
| printVectorIndex(MI, 2, STI, O); |
| O << ", ["; |
| printOperand(MI, 3, STI, O); |
| break; |
| case 42: |
| // LD1i64_POST, LD2i64_POST, LD3i64_POST, LD4i64_POST |
| printTypedVectorList<0, 'd'>(MI, 2, STI, O); |
| printVectorIndex(MI, 3, STI, O); |
| O << ", ["; |
| printOperand(MI, 4, STI, O); |
| O << "], "; |
| break; |
| case 43: |
| // LD1i8, LD2i8, LD3i8, LD4i8, ST1i8_POST, ST2i8_POST, ST3i8_POST, ST4i8_... |
| printTypedVectorList<0, 'b'>(MI, 1, STI, O); |
| printVectorIndex(MI, 2, STI, O); |
| O << ", ["; |
| printOperand(MI, 3, STI, O); |
| break; |
| case 44: |
| // LD1i8_POST, LD2i8_POST, LD3i8_POST, LD4i8_POST |
| printTypedVectorList<0, 'b'>(MI, 2, STI, O); |
| printVectorIndex(MI, 3, STI, O); |
| O << ", ["; |
| printOperand(MI, 4, STI, O); |
| O << "], "; |
| break; |
| case 45: |
| // LDR_PXI, LDR_ZXI, MOVPRFX_ZZ, PTEST_PP, STR_PXI, STR_ZXI |
| printSVERegOp<>(MI, 0, STI, O); |
| break; |
| case 46: |
| // MSR |
| printMSRSystemRegister(MI, 0, STI, O); |
| O << ", "; |
| printOperand(MI, 1, STI, O); |
| return; |
| break; |
| case 47: |
| // MSRpstateImm1, MSRpstateImm4 |
| printSystemPStateField(MI, 0, STI, O); |
| O << ", "; |
| printOperand(MI, 1, STI, O); |
| return; |
| break; |
| case 48: |
| // PRFB_D_PZI, PRFB_D_SCALED, PRFB_D_SXTW_SCALED, PRFB_D_UXTW_SCALED, PRF... |
| printPrefetchOp<true>(MI, 0, STI, O); |
| O << ", "; |
| printSVERegOp<>(MI, 1, STI, O); |
| O << ", ["; |
| break; |
| case 49: |
| // PRFMl, PRFMroW, PRFMroX, PRFMui, PRFUMi |
| printPrefetchOp(MI, 0, STI, O); |
| break; |
| case 50: |
| // ST1i16, ST2i16, ST3i16, ST4i16 |
| printTypedVectorList<0, 'h'>(MI, 0, STI, O); |
| printVectorIndex(MI, 1, STI, O); |
| O << ", ["; |
| printOperand(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 51: |
| // ST1i32, ST2i32, ST3i32, ST4i32 |
| printTypedVectorList<0, 's'>(MI, 0, STI, O); |
| printVectorIndex(MI, 1, STI, O); |
| O << ", ["; |
| printOperand(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 52: |
| // ST1i64, ST2i64, ST3i64, ST4i64 |
| printTypedVectorList<0, 'd'>(MI, 0, STI, O); |
| printVectorIndex(MI, 1, STI, O); |
| O << ", ["; |
| printOperand(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 53: |
| // ST1i8, ST2i8, ST3i8, ST4i8 |
| printTypedVectorList<0, 'b'>(MI, 0, STI, O); |
| printVectorIndex(MI, 1, STI, O); |
| O << ", ["; |
| printOperand(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| } |
| |
| |
| // Fragment 1 encoded into 6 bits for 51 unique commands. |
| switch ((Bits >> 20) & 63) { |
| default: llvm_unreachable("Invalid command number."); |
| case 0: |
| // ABS_ZPmZ_B, ABS_ZPmZ_D, ABS_ZPmZ_S, ABSv16i8, ABSv1i64, ABSv2i32, ABSv... |
| O << ", "; |
| break; |
| case 1: |
| // ABS_ZPmZ_H, CLS_ZPmZ_H, CLZ_ZPmZ_H, CNOT_ZPmZ_H, CNT_ZPmZ_H, CPY_ZPmI_... |
| printSVERegOp<>(MI, 2, STI, O); |
| break; |
| case 2: |
| // ADD_ZI_H, ADD_ZZZ_H, ASR_WIDE_ZZZ_H, ASR_ZZI_H, DUP_ZZI_H, FADD_ZZZ_H,... |
| printSVERegOp<'h'>(MI, 1, STI, O); |
| break; |
| case 3: |
| // ADD_ZPmZ_H, AND_ZPmZ_H, ASRD_ZPmI_H, ASRR_ZPmZ_H, ASR_WIDE_ZPmZ_H, ASR... |
| printSVERegOp<>(MI, 1, STI, O); |
| break; |
| case 4: |
| // ADR_LSL_ZZZ_D_0, ADR_LSL_ZZZ_D_1, ADR_LSL_ZZZ_D_2, ADR_LSL_ZZZ_D_3, AD... |
| O << ", ["; |
| break; |
| case 5: |
| // AUTDZA, AUTDZB, AUTIZA, AUTIZB, BLR, BLRAAZ, BLRABZ, BR, BRAAZ, BRABZ,... |
| return; |
| break; |
| case 6: |
| // DECH_ZPiI, INCH_ZPiI, SQDECH_ZPiI, SQINCH_ZPiI, UQDECH_ZPiI, UQINCH_ZP... |
| printSVEPattern(MI, 2, STI, O); |
| O << ", mul "; |
| printOperand(MI, 3, STI, O); |
| return; |
| break; |
| case 7: |
| // DUP_ZI_H |
| printImm8OptLsl<int16_t>(MI, 1, STI, O); |
| return; |
| break; |
| case 8: |
| // DUP_ZR_H, INDEX_II_H, INDEX_IR_H, INDEX_RI_H, INDEX_RR_H, WHILELE_PWW_... |
| printOperand(MI, 1, STI, O); |
| break; |
| case 9: |
| // FCMLA_ZZZI_H, FMLA_ZZZI_H, FMLS_ZZZI_H |
| printSVERegOp<'h'>(MI, 2, STI, O); |
| O << ", "; |
| printSVERegOp<'h'>(MI, 3, STI, O); |
| printVectorIndex(MI, 4, STI, O); |
| break; |
| case 10: |
| // FCMPDri, FCMPEDri, FCMPEHri, FCMPESri, FCMPHri, FCMPSri |
| O << ", #0.0"; |
| return; |
| break; |
| case 11: |
| // FCVTLv2i32, FCVTLv4i32 |
| O << ".2d, "; |
| printVRegOperand(MI, 1, STI, O); |
| break; |
| case 12: |
| // FCVTLv4i16, FCVTLv8i16, FCVTNv4i32, FCVTXNv4f32 |
| O << ".4s, "; |
| break; |
| case 13: |
| // FCVTNv2i32, FCVTXNv2f32 |
| O << ".2s, "; |
| printVRegOperand(MI, 1, STI, O); |
| O << ".2d"; |
| return; |
| break; |
| case 14: |
| // FCVTNv4i16 |
| O << ".4h, "; |
| printVRegOperand(MI, 1, STI, O); |
| O << ".4s"; |
| return; |
| break; |
| case 15: |
| // FCVTNv8i16 |
| O << ".8h, "; |
| printVRegOperand(MI, 2, STI, O); |
| O << ".4s"; |
| return; |
| break; |
| case 16: |
| // FDUP_ZI_H |
| printFPImmOperand(MI, 1, STI, O); |
| return; |
| break; |
| case 17: |
| // FMOVXDHighr, INSvi16gpr, INSvi16lane, INSvi32gpr, INSvi32lane, INSvi64... |
| printVectorIndex(MI, 2, STI, O); |
| O << ", "; |
| break; |
| case 18: |
| // GLD1B_D_IMM_REAL, GLD1B_D_REAL, GLD1B_D_SXTW_REAL, GLD1B_D_UXTW_REAL, ... |
| O << "/z, ["; |
| break; |
| case 19: |
| // INSR_ZR_H, INSR_ZV_H, PRFB_D_SCALED, PRFB_D_SXTW_SCALED, PRFB_D_UXTW_S... |
| printOperand(MI, 2, STI, O); |
| break; |
| case 20: |
| // LD1Fourv16b_POST, LD1Fourv2d_POST, LD1Fourv4s_POST, LD1Fourv8h_POST, L... |
| printPostIncOperand<64>(MI, 3, STI, O); |
| return; |
| break; |
| case 21: |
| // LD1Fourv1d_POST, LD1Fourv2s_POST, LD1Fourv4h_POST, LD1Fourv8b_POST, LD... |
| printPostIncOperand<32>(MI, 3, STI, O); |
| return; |
| break; |
| case 22: |
| // LD1Onev16b_POST, LD1Onev2d_POST, LD1Onev4s_POST, LD1Onev8h_POST, LD1Tw... |
| printPostIncOperand<16>(MI, 3, STI, O); |
| return; |
| break; |
| case 23: |
| // LD1Onev1d_POST, LD1Onev2s_POST, LD1Onev4h_POST, LD1Onev8b_POST, LD1Rv1... |
| printPostIncOperand<8>(MI, 3, STI, O); |
| return; |
| break; |
| case 24: |
| // LD1Rv16b_POST, LD1Rv8b_POST |
| printPostIncOperand<1>(MI, 3, STI, O); |
| return; |
| break; |
| case 25: |
| // LD1Rv2s_POST, LD1Rv4s_POST, LD2Rv4h_POST, LD2Rv8h_POST, LD4Rv16b_POST,... |
| printPostIncOperand<4>(MI, 3, STI, O); |
| return; |
| break; |
| case 26: |
| // LD1Rv4h_POST, LD1Rv8h_POST, LD2Rv16b_POST, LD2Rv8b_POST |
| printPostIncOperand<2>(MI, 3, STI, O); |
| return; |
| break; |
| case 27: |
| // LD1Threev16b_POST, LD1Threev2d_POST, LD1Threev4s_POST, LD1Threev8h_POS... |
| printPostIncOperand<48>(MI, 3, STI, O); |
| return; |
| break; |
| case 28: |
| // LD1Threev1d_POST, LD1Threev2s_POST, LD1Threev4h_POST, LD1Threev8b_POST... |
| printPostIncOperand<24>(MI, 3, STI, O); |
| return; |
| break; |
| case 29: |
| // LD1i16, LD1i32, LD1i64, LD1i8, LD2i16, LD2i32, LD2i64, LD2i8, LD3i16, ... |
| O << ']'; |
| return; |
| break; |
| case 30: |
| // LD1i16_POST, LD2i8_POST |
| printPostIncOperand<2>(MI, 5, STI, O); |
| return; |
| break; |
| case 31: |
| // LD1i32_POST, LD2i16_POST, LD4i8_POST |
| printPostIncOperand<4>(MI, 5, STI, O); |
| return; |
| break; |
| case 32: |
| // LD1i64_POST, LD2i32_POST, LD4i16_POST |
| printPostIncOperand<8>(MI, 5, STI, O); |
| return; |
| break; |
| case 33: |
| // LD1i8_POST |
| printPostIncOperand<1>(MI, 5, STI, O); |
| return; |
| break; |
| case 34: |
| // LD2i64_POST, LD4i32_POST |
| printPostIncOperand<16>(MI, 5, STI, O); |
| return; |
| break; |
| case 35: |
| // LD3Rv16b_POST, LD3Rv8b_POST |
| printPostIncOperand<3>(MI, 3, STI, O); |
| return; |
| break; |
| case 36: |
| // LD3Rv2s_POST, LD3Rv4s_POST |
| printPostIncOperand<12>(MI, 3, STI, O); |
| return; |
| break; |
| case 37: |
| // LD3Rv4h_POST, LD3Rv8h_POST |
| printPostIncOperand<6>(MI, 3, STI, O); |
| return; |
| break; |
| case 38: |
| // LD3i16_POST |
| printPostIncOperand<6>(MI, 5, STI, O); |
| return; |
| break; |
| case 39: |
| // LD3i32_POST |
| printPostIncOperand<12>(MI, 5, STI, O); |
| return; |
| break; |
| case 40: |
| // LD3i64_POST |
| printPostIncOperand<24>(MI, 5, STI, O); |
| return; |
| break; |
| case 41: |
| // LD3i8_POST |
| printPostIncOperand<3>(MI, 5, STI, O); |
| return; |
| break; |
| case 42: |
| // LD4i64_POST |
| printPostIncOperand<32>(MI, 5, STI, O); |
| return; |
| break; |
| case 43: |
| // PRFB_D_PZI, PRFD_D_PZI, PRFH_D_PZI, PRFW_D_PZI |
| printSVERegOp<'d'>(MI, 2, STI, O); |
| O << ", "; |
| break; |
| case 44: |
| // PRFB_S_PZI, PRFD_S_PZI, PRFH_S_PZI, PRFW_S_PZI |
| printSVERegOp<'s'>(MI, 2, STI, O); |
| O << ", "; |
| break; |
| case 45: |
| // PTRUES_H, PTRUE_H |
| printSVEPattern(MI, 1, STI, O); |
| return; |
| break; |
| case 46: |
| // PUNPKHI_PP, PUNPKLO_PP, SUNPKHI_ZZ_H, SUNPKLO_ZZ_H, UUNPKHI_ZZ_H, UUNP... |
| printSVERegOp<'b'>(MI, 1, STI, O); |
| return; |
| break; |
| case 47: |
| // ST1i16_POST, ST1i32_POST, ST1i64_POST, ST1i8_POST, ST2i16_POST, ST2i32... |
| O << "], "; |
| break; |
| case 48: |
| // TBL_ZZZ_H |
| printTypedVectorList<0,'h'>(MI, 1, STI, O); |
| O << ", "; |
| printSVERegOp<'h'>(MI, 2, STI, O); |
| return; |
| break; |
| case 49: |
| // TBLv16i8Four, TBLv16i8One, TBLv16i8Three, TBLv16i8Two, TBXv16i8Four, T... |
| O << ".16b, "; |
| break; |
| case 50: |
| // TBLv8i8Four, TBLv8i8One, TBLv8i8Three, TBLv8i8Two, TBXv8i8Four, TBXv8i... |
| O << ".8b, "; |
| break; |
| } |
| |
| |
| // Fragment 2 encoded into 6 bits for 57 unique commands. |
| switch ((Bits >> 26) & 63) { |
| default: llvm_unreachable("Invalid command number."); |
| case 0: |
| // ABS_ZPmZ_B, ABS_ZPmZ_D, ABS_ZPmZ_S, BRKA_PPmP, BRKB_PPmP, CLS_ZPmZ_B, ... |
| printSVERegOp<>(MI, 2, STI, O); |
| break; |
| case 1: |
| // ABS_ZPmZ_H, ADD_ZPmZ_H, AND_ZPmZ_H, ASRD_ZPmI_H, ASRR_ZPmZ_H, ASR_WIDE... |
| O << "/m, "; |
| break; |
| case 2: |
| // ABSv16i8, ABSv2i32, ABSv2i64, ABSv4i16, ABSv4i32, ABSv8i16, ABSv8i8, A... |
| printVRegOperand(MI, 1, STI, O); |
| break; |
| case 3: |
| // ABSv1i64, ADCSWr, ADCSXr, ADCWr, ADCXr, ADDPL_XXI, ADDSWri, ADDSWrs, A... |
| printOperand(MI, 1, STI, O); |
| break; |
| case 4: |
| // ADDHNv2i64_v4i32, ADDHNv4i32_v8i16, ADDHNv8i16_v16i8, AESDrr, AESErr, ... |
| printVRegOperand(MI, 2, STI, O); |
| break; |
| case 5: |
| // ADD_ZI_B, ADD_ZZZ_B, ASR_WIDE_ZZZ_B, ASR_ZZI_B, DECP_XP_B, DUP_ZZI_B, ... |
| printSVERegOp<'b'>(MI, 1, STI, O); |
| break; |
| case 6: |
| // ADD_ZI_D, ADD_ZZZ_D, ADR_LSL_ZZZ_D_0, ADR_LSL_ZZZ_D_1, ADR_LSL_ZZZ_D_2... |
| printSVERegOp<'d'>(MI, 1, STI, O); |
| break; |
| case 7: |
| // ADD_ZI_H, ADD_ZZZ_H, ASR_WIDE_ZZZ_H, ASR_ZZI_H, CLASTA_ZPZ_H, CLASTB_Z... |
| O << ", "; |
| break; |
| case 8: |
| // ADD_ZI_S, ADD_ZZZ_S, ADR_LSL_ZZZ_S_0, ADR_LSL_ZZZ_S_1, ADR_LSL_ZZZ_S_2... |
| printSVERegOp<'s'>(MI, 1, STI, O); |
| break; |
| case 9: |
| // ADD_ZPmZ_B, ADD_ZPmZ_D, ADD_ZPmZ_S, ANDS_PPzPP, ANDV_VPZ_B, ANDV_VPZ_D... |
| printSVERegOp<>(MI, 1, STI, O); |
| break; |
| case 10: |
| // ADRP |
| printAdrpLabel(MI, 1, STI, O); |
| return; |
| break; |
| case 11: |
| // BFMWri, BFMXri, CASAB, CASAH, CASALB, CASALH, CASALW, CASALX, CASAW, C... |
| printOperand(MI, 2, STI, O); |
| break; |
| case 12: |
| // BICv2i32, BICv4i16, BICv4i32, BICv8i16, MOVKWi, MOVKXi, ORRv2i32, ORRv... |
| printImm(MI, 2, STI, O); |
| printShifter(MI, 3, STI, O); |
| return; |
| break; |
| case 13: |
| // CBNZW, CBNZX, CBZW, CBZX, LDRDl, LDRQl, LDRSWl, LDRSl, LDRWl, LDRXl, P... |
| printAlignedLabel(MI, 1, STI, O); |
| return; |
| break; |
| case 14: |
| // CMPEQ_PPzZI_H, CMPEQ_PPzZZ_H, CMPEQ_WIDE_PPzZZ_H, CMPGE_PPzZI_H, CMPGE... |
| O << "/z, "; |
| break; |
| case 15: |
| // CNTB_XPiI, CNTD_XPiI, CNTH_XPiI, CNTW_XPiI, PTRUES_B, PTRUES_D, PTRUES... |
| printSVEPattern(MI, 1, STI, O); |
| break; |
| case 16: |
| // DECB_XPiI, DECD_XPiI, DECD_ZPiI, DECH_XPiI, DECW_XPiI, DECW_ZPiI, INCB... |
| printSVEPattern(MI, 2, STI, O); |
| O << ", mul "; |
| printOperand(MI, 3, STI, O); |
| return; |
| break; |
| case 17: |
| // DECP_XP_H, INCP_XP_H, SQDECP_XPWd_H, SQDECP_XP_H, SQINCP_XPWd_H, SQINC... |
| printSVERegOp<'h'>(MI, 1, STI, O); |
| break; |
| case 18: |
| // DECP_ZP_H, DUP_ZR_H, FEXPA_ZZ_H, FMLA_ZZZI_H, FMLS_ZZZI_H, FRECPE_ZZ_H... |
| return; |
| break; |
| case 19: |
| // DUPM_ZI |
| printLogicalImm<int64_t>(MI, 1, STI, O); |
| return; |
| break; |
| case 20: |
| // DUP_ZI_B |
| printImm8OptLsl<int8_t>(MI, 1, STI, O); |
| return; |
| break; |
| case 21: |
| // DUP_ZI_D |
| printImm8OptLsl<int64_t>(MI, 1, STI, O); |
| return; |
| break; |
| case 22: |
| // DUP_ZI_S |
| printImm8OptLsl<int32_t>(MI, 1, STI, O); |
| return; |
| break; |
| case 23: |
| // DUP_ZZI_H |
| printVectorIndex(MI, 2, STI, O); |
| return; |
| break; |
| case 24: |
| // FCMLA_ZZZI_S, FMLA_ZZZI_S, FMLS_ZZZI_S, GLD1B_S_IMM_REAL, GLD1H_S_IMM_... |
| printSVERegOp<'s'>(MI, 2, STI, O); |
| O << ", "; |
| break; |
| case 25: |
| // FCVTLv2i32 |
| O << ".2s"; |
| return; |
| break; |
| case 26: |
| // FCVTLv4i32 |
| O << ".4s"; |
| return; |
| break; |
| case 27: |
| // FDUP_ZI_D, FDUP_ZI_S, FMOVDi, FMOVHi, FMOVSi, FMOVv2f32_ns, FMOVv2f64_... |
| printFPImmOperand(MI, 1, STI, O); |
| return; |
| break; |
| case 28: |
| // FMLA_ZZZI_D, FMLS_ZZZI_D, GLD1B_D_IMM_REAL, GLD1D_IMM_REAL, GLD1H_D_IM... |
| printSVERegOp<'d'>(MI, 2, STI, O); |
| O << ", "; |
| break; |
| case 29: |
| // INSvi16gpr, INSvi32gpr, INSvi64gpr, INSvi8gpr, PRFB_D_PZI, PRFB_S_PZI |
| printOperand(MI, 3, STI, O); |
| break; |
| case 30: |
| // INSvi16lane, INSvi32lane, INSvi64lane, INSvi8lane |
| printVRegOperand(MI, 3, STI, O); |
| printVectorIndex(MI, 4, STI, O); |
| return; |
| break; |
| case 31: |
| // LDADDAB, LDADDAH, LDADDALB, LDADDALH, LDADDALW, LDADDALX, LDADDAW, LDA... |
| printOperand(MI, 0, STI, O); |
| O << ", ["; |
| printOperand(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 32: |
| // MOVID, MOVIv2d_ns |
| printSIMDType10Operand(MI, 1, STI, O); |
| return; |
| break; |
| case 33: |
| // MOVIv16b_ns, MOVIv2i32, MOVIv2s_msl, MOVIv4i16, MOVIv4i32, MOVIv4s_msl... |
| printImm(MI, 1, STI, O); |
| break; |
| case 34: |
| // MRS |
| printMRSSystemRegister(MI, 1, STI, O); |
| return; |
| break; |
| case 35: |
| // PRFD_D_PZI, PRFD_S_PZI |
| printImmScale<8>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 36: |
| // PRFH_D_PZI, PRFH_S_PZI |
| printImmScale<2>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 37: |
| // PRFW_D_PZI, PRFW_S_PZI |
| printImmScale<4>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 38: |
| // SDOT_ZZZI_D, SDOT_ZZZ_D, UDOT_ZZZI_D, UDOT_ZZZ_D |
| printSVERegOp<'h'>(MI, 2, STI, O); |
| O << ", "; |
| printSVERegOp<'h'>(MI, 3, STI, O); |
| break; |
| case 39: |
| // SDOT_ZZZI_S, SDOT_ZZZ_S, UDOT_ZZZI_S, UDOT_ZZZ_S |
| printSVERegOp<'b'>(MI, 2, STI, O); |
| O << ", "; |
| printSVERegOp<'b'>(MI, 3, STI, O); |
| break; |
| case 40: |
| // SQDECB_XPiWdI, SQDECD_XPiWdI, SQDECH_XPiWdI, SQDECW_XPiWdI, SQINCB_XPi... |
| printGPR64as32(MI, 1, STI, O); |
| O << ", "; |
| printSVEPattern(MI, 2, STI, O); |
| O << ", mul "; |
| printOperand(MI, 3, STI, O); |
| return; |
| break; |
| case 41: |
| // ST1i16_POST, ST2i8_POST |
| printPostIncOperand<2>(MI, 4, STI, O); |
| return; |
| break; |
| case 42: |
| // ST1i32_POST, ST2i16_POST, ST4i8_POST |
| printPostIncOperand<4>(MI, 4, STI, O); |
| return; |
| break; |
| case 43: |
| // ST1i64_POST, ST2i32_POST, ST4i16_POST |
| printPostIncOperand<8>(MI, 4, STI, O); |
| return; |
| break; |
| case 44: |
| // ST1i8_POST |
| printPostIncOperand<1>(MI, 4, STI, O); |
| return; |
| break; |
| case 45: |
| // ST2i64_POST, ST4i32_POST |
| printPostIncOperand<16>(MI, 4, STI, O); |
| return; |
| break; |
| case 46: |
| // ST3i16_POST |
| printPostIncOperand<6>(MI, 4, STI, O); |
| return; |
| break; |
| case 47: |
| // ST3i32_POST |
| printPostIncOperand<12>(MI, 4, STI, O); |
| return; |
| break; |
| case 48: |
| // ST3i64_POST |
| printPostIncOperand<24>(MI, 4, STI, O); |
| return; |
| break; |
| case 49: |
| // ST3i8_POST |
| printPostIncOperand<3>(MI, 4, STI, O); |
| return; |
| break; |
| case 50: |
| // ST4i64_POST |
| printPostIncOperand<32>(MI, 4, STI, O); |
| return; |
| break; |
| case 51: |
| // SYSxt |
| printSysCROperand(MI, 1, STI, O); |
| O << ", "; |
| printSysCROperand(MI, 2, STI, O); |
| O << ", "; |
| printOperand(MI, 3, STI, O); |
| O << ", "; |
| printOperand(MI, 4, STI, O); |
| return; |
| break; |
| case 52: |
| // TBL_ZZZ_B |
| printTypedVectorList<0,'b'>(MI, 1, STI, O); |
| O << ", "; |
| printSVERegOp<'b'>(MI, 2, STI, O); |
| return; |
| break; |
| case 53: |
| // TBL_ZZZ_D |
| printTypedVectorList<0,'d'>(MI, 1, STI, O); |
| O << ", "; |
| printSVERegOp<'d'>(MI, 2, STI, O); |
| return; |
| break; |
| case 54: |
| // TBL_ZZZ_S |
| printTypedVectorList<0,'s'>(MI, 1, STI, O); |
| O << ", "; |
| printSVERegOp<'s'>(MI, 2, STI, O); |
| return; |
| break; |
| case 55: |
| // TBLv16i8Four, TBLv16i8One, TBLv16i8Three, TBLv16i8Two, TBLv8i8Four, TB... |
| printTypedVectorList<16, 'b'>(MI, 1, STI, O); |
| O << ", "; |
| printVRegOperand(MI, 2, STI, O); |
| break; |
| case 56: |
| // TBXv16i8Four, TBXv16i8One, TBXv16i8Three, TBXv16i8Two, TBXv8i8Four, TB... |
| printTypedVectorList<16, 'b'>(MI, 2, STI, O); |
| O << ", "; |
| printVRegOperand(MI, 3, STI, O); |
| break; |
| } |
| |
| |
| // Fragment 3 encoded into 6 bits for 62 unique commands. |
| switch ((Bits >> 32) & 63) { |
| default: llvm_unreachable("Invalid command number."); |
| case 0: |
| // ABS_ZPmZ_B, ABS_ZPmZ_D, ABS_ZPmZ_S, ADD_ZPmZ_B, ADD_ZPmZ_D, ADD_ZPmZ_S... |
| O << "/m, "; |
| break; |
| case 1: |
| // ABS_ZPmZ_H, CLS_ZPmZ_H, CLZ_ZPmZ_H, CNOT_ZPmZ_H, CNT_ZPmZ_H, FABS_ZPmZ... |
| printSVERegOp<'h'>(MI, 3, STI, O); |
| break; |
| case 2: |
| // ABSv16i8, ABSv1i64, ABSv2i32, ABSv2i64, ABSv4i16, ABSv4i32, ABSv8i16, ... |
| return; |
| break; |
| case 3: |
| // ADCSWr, ADCSXr, ADCWr, ADCXr, ADDHNv2i64_v2i32, ADDHNv2i64_v4i32, ADDH... |
| O << ", "; |
| break; |
| case 4: |
| // ADD_ZI_H, SQADD_ZI_H, SQSUB_ZI_H, SUBR_ZI_H, SUB_ZI_H, UQADD_ZI_H, UQS... |
| printImm8OptLsl<uint16_t>(MI, 2, STI, O); |
| return; |
| break; |
| case 5: |
| // ADD_ZPmZ_H, ADD_ZZZ_H, AND_ZPmZ_H, ASRD_ZPmI_H, ASRR_ZPmZ_H, ASR_WIDE_... |
| printSVERegOp<'h'>(MI, 2, STI, O); |
| break; |
| case 6: |
| // ANDS_PPzPP, AND_PPzPP, BICS_PPzPP, BIC_PPzPP, BRKAS_PPzP, BRKA_PPzP, B... |
| O << "/z, "; |
| break; |
| case 7: |
| // ASR_WIDE_ZZZ_H, LSL_WIDE_ZZZ_H, LSR_WIDE_ZZZ_H |
| printSVERegOp<'d'>(MI, 2, STI, O); |
| return; |
| break; |
| case 8: |
| // ASR_ZZI_H, INDEX_II_H, INDEX_IR_H, INDEX_RI_H, INDEX_RR_H, LSL_ZZI_H, ... |
| printOperand(MI, 2, STI, O); |
| return; |
| break; |
| case 9: |
| // CASAB, CASAH, CASALB, CASALH, CASALW, CASALX, CASAW, CASAX, CASB, CASH... |
| O << ", ["; |
| break; |
| case 10: |
| // CMEQv16i8rz, CMEQv1i64rz, CMEQv2i32rz, CMEQv2i64rz, CMEQv4i16rz, CMEQv... |
| O << ", #0"; |
| return; |
| break; |
| case 11: |
| // CNTB_XPiI, CNTD_XPiI, CNTH_XPiI, CNTW_XPiI |
| O << ", mul "; |
| printOperand(MI, 2, STI, O); |
| return; |
| break; |
| case 12: |
| // CPY_ZPmI_H |
| printImm8OptLsl<int16_t>(MI, 3, STI, O); |
| return; |
| break; |
| case 13: |
| // CPY_ZPmR_H, CPY_ZPmV_H, GLD1B_D_IMM_REAL, GLD1B_S_IMM_REAL, GLD1SB_D_I... |
| printOperand(MI, 3, STI, O); |
| break; |
| case 14: |
| // CPY_ZPzI_H |
| printImm8OptLsl<int16_t>(MI, 2, STI, O); |
| return; |
| break; |
| case 15: |
| // CPYi16, CPYi32, CPYi64, CPYi8, DUP_ZZI_B, DUP_ZZI_D, DUP_ZZI_S, DUPv16... |
| printVectorIndex(MI, 2, STI, O); |
| return; |
| break; |
| case 16: |
| // FCMEQv1i16rz, FCMEQv1i32rz, FCMEQv1i64rz, FCMEQv2i32rz, FCMEQv2i64rz, ... |
| O << ", #0.0"; |
| return; |
| break; |
| case 17: |
| // FCMLA_ZZZI_H |
| printComplexRotationOp<90, 0>(MI, 5, STI, O); |
| return; |
| break; |
| case 18: |
| // FCMLA_ZZZI_S, FCVT_ZPmZ_StoH, FMLA_ZZZI_S, FMLS_ZZZI_S, SCVTF_ZPmZ_Sto... |
| printSVERegOp<'s'>(MI, 3, STI, O); |
| break; |
| case 19: |
| // FCPY_ZPmI_H |
| printFPImmOperand(MI, 3, STI, O); |
| return; |
| break; |
| case 20: |
| // FCVTLv4i16 |
| O << ".4h"; |
| return; |
| break; |
| case 21: |
| // FCVTLv8i16 |
| O << ".8h"; |
| return; |
| break; |
| case 22: |
| // FCVTNv4i32, FCVTXNv4f32 |
| O << ".2d"; |
| return; |
| break; |
| case 23: |
| // FCVT_ZPmZ_DtoH, FMLA_ZZZI_D, FMLS_ZZZI_D, SCVTF_ZPmZ_DtoH, UCVTF_ZPmZ_... |
| printSVERegOp<'d'>(MI, 3, STI, O); |
| break; |
| case 24: |
| // GLD1D_IMM_REAL, GLDFF1D_IMM_REAL, SST1D_IMM |
| printImmScale<8>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 25: |
| // GLD1H_D_IMM_REAL, GLD1H_S_IMM_REAL, GLD1SH_D_IMM_REAL, GLD1SH_S_IMM_RE... |
| printImmScale<2>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 26: |
| // GLD1SW_D_IMM_REAL, GLD1W_D_IMM_REAL, GLD1W_IMM_REAL, GLDFF1SW_D_IMM_RE... |
| printImmScale<4>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 27: |
| // LDAPRB, LDAPRH, LDAPRW, LDAPRX, LDARB, LDARH, LDARW, LDARX, LDAXRB, LD... |
| O << ']'; |
| return; |
| break; |
| case 28: |
| // LDRBBpost, LDRBpost, LDRDpost, LDRHHpost, LDRHpost, LDRQpost, LDRSBWpo... |
| O << "], "; |
| printOperand(MI, 3, STI, O); |
| return; |
| break; |
| case 29: |
| // MOVIv2i32, MOVIv2s_msl, MOVIv4i16, MOVIv4i32, MOVIv4s_msl, MOVIv8i16, ... |
| printShifter(MI, 2, STI, O); |
| return; |
| break; |
| case 30: |
| // PRFB_D_SCALED |
| printRegWithShiftExtend<false, 8, 'x', 'd'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 31: |
| // PRFB_D_SXTW_SCALED |
| printRegWithShiftExtend<true, 8, 'w', 'd'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 32: |
| // PRFB_D_UXTW_SCALED |
| printRegWithShiftExtend<false, 8, 'w', 'd'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 33: |
| // PRFB_PRR |
| printRegWithShiftExtend<false, 8, 'x', 0>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 34: |
| // PRFB_S_SXTW_SCALED |
| printRegWithShiftExtend<true, 8, 'w', 's'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 35: |
| // PRFB_S_UXTW_SCALED |
| printRegWithShiftExtend<false, 8, 'w', 's'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 36: |
| // PRFD_D_SCALED |
| printRegWithShiftExtend<false, 64, 'x', 'd'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 37: |
| // PRFD_D_SXTW_SCALED |
| printRegWithShiftExtend<true, 64, 'w', 'd'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 38: |
| // PRFD_D_UXTW_SCALED |
| printRegWithShiftExtend<false, 64, 'w', 'd'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 39: |
| // PRFD_PRR |
| printRegWithShiftExtend<false, 64, 'x', 0>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 40: |
| // PRFD_S_SXTW_SCALED |
| printRegWithShiftExtend<true, 64, 'w', 's'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 41: |
| // PRFD_S_UXTW_SCALED |
| printRegWithShiftExtend<false, 64, 'w', 's'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 42: |
| // PRFH_D_SCALED |
| printRegWithShiftExtend<false, 16, 'x', 'd'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 43: |
| // PRFH_D_SXTW_SCALED |
| printRegWithShiftExtend<true, 16, 'w', 'd'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 44: |
| // PRFH_D_UXTW_SCALED |
| printRegWithShiftExtend<false, 16, 'w', 'd'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 45: |
| // PRFH_PRR |
| printRegWithShiftExtend<false, 16, 'x', 0>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 46: |
| // PRFH_S_SXTW_SCALED |
| printRegWithShiftExtend<true, 16, 'w', 's'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 47: |
| // PRFH_S_UXTW_SCALED |
| printRegWithShiftExtend<false, 16, 'w', 's'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 48: |
| // PRFS_PRR |
| printRegWithShiftExtend<false, 32, 'x', 0>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 49: |
| // PRFW_D_SCALED |
| printRegWithShiftExtend<false, 32, 'x', 'd'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 50: |
| // PRFW_D_SXTW_SCALED |
| printRegWithShiftExtend<true, 32, 'w', 'd'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 51: |
| // PRFW_D_UXTW_SCALED |
| printRegWithShiftExtend<false, 32, 'w', 'd'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 52: |
| // PRFW_S_SXTW_SCALED |
| printRegWithShiftExtend<true, 32, 'w', 's'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 53: |
| // PRFW_S_UXTW_SCALED |
| printRegWithShiftExtend<false, 32, 'w', 's'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 54: |
| // RDFFRS_PPz, RDFFR_PPz |
| O << "/z"; |
| return; |
| break; |
| case 55: |
| // SDOT_ZZZI_D, SDOT_ZZZI_S, UDOT_ZZZI_D, UDOT_ZZZI_S |
| printVectorIndex(MI, 4, STI, O); |
| return; |
| break; |
| case 56: |
| // SHLLv16i8, SHLLv8i8 |
| O << ", #8"; |
| return; |
| break; |
| case 57: |
| // SHLLv2i32, SHLLv4i32 |
| O << ", #32"; |
| return; |
| break; |
| case 58: |
| // SHLLv4i16, SHLLv8i16 |
| O << ", #16"; |
| return; |
| break; |
| case 59: |
| // TBLv16i8Four, TBLv16i8One, TBLv16i8Three, TBLv16i8Two, TBXv16i8Four, T... |
| O << ".16b"; |
| return; |
| break; |
| case 60: |
| // TBLv8i8Four, TBLv8i8One, TBLv8i8Three, TBLv8i8Two, TBXv8i8Four, TBXv8i... |
| O << ".8b"; |
| return; |
| break; |
| case 61: |
| // UMAX_ZI_H, UMIN_ZI_H |
| printImm(MI, 2, STI, O); |
| return; |
| break; |
| } |
| |
| |
| // Fragment 4 encoded into 7 bits for 87 unique commands. |
| switch ((Bits >> 38) & 127) { |
| default: llvm_unreachable("Invalid command number."); |
| case 0: |
| // ABS_ZPmZ_B, BRKA_PPmP, BRKB_PPmP, CLS_ZPmZ_B, CLZ_ZPmZ_B, CNOT_ZPmZ_B,... |
| printSVERegOp<'b'>(MI, 3, STI, O); |
| break; |
| case 1: |
| // ABS_ZPmZ_D, CLS_ZPmZ_D, CLZ_ZPmZ_D, CNOT_ZPmZ_D, CNT_ZPmZ_D, FABS_ZPmZ... |
| printSVERegOp<'d'>(MI, 3, STI, O); |
| break; |
| case 2: |
| // ABS_ZPmZ_H, ADD_ZZZ_H, CLS_ZPmZ_H, CLZ_ZPmZ_H, CNOT_ZPmZ_H, CNT_ZPmZ_H... |
| return; |
| break; |
| case 3: |
| // ABS_ZPmZ_S, CLS_ZPmZ_S, CLZ_ZPmZ_S, CNOT_ZPmZ_S, CNT_ZPmZ_S, FABS_ZPmZ... |
| printSVERegOp<'s'>(MI, 3, STI, O); |
| break; |
| case 4: |
| // ADCSWr, ADCSXr, ADCWr, ADCXr, ADDPL_XXI, ADDSXrx64, ADDVL_XXI, ADDXrx6... |
| printOperand(MI, 2, STI, O); |
| break; |
| case 5: |
| // ADDHNv2i64_v2i32, ADDHNv4i32_v4i16, ADDHNv8i16_v8i8, ADDPv16i8, ADDPv2... |
| printVRegOperand(MI, 2, STI, O); |
| break; |
| case 6: |
| // ADDHNv2i64_v4i32, ADDHNv4i32_v8i16, ADDHNv8i16_v16i8, BITv16i8, BITv8i... |
| printVRegOperand(MI, 3, STI, O); |
| break; |
| case 7: |
| // ADDSWri, ADDSXri, ADDWri, ADDXri, SUBSWri, SUBSXri, SUBWri, SUBXri |
| printAddSubImm(MI, 2, STI, O); |
| return; |
| break; |
| case 8: |
| // ADDSWrs, ADDSXrs, ADDWrs, ADDXrs, ANDSWrs, ANDSXrs, ANDWrs, ANDXrs, BI... |
| printShiftedRegister(MI, 2, STI, O); |
| return; |
| break; |
| case 9: |
| // ADDSWrx, ADDSXrx, ADDWrx, ADDXrx, SUBSWrx, SUBSXrx, SUBWrx, SUBXrx |
| printExtendedRegister(MI, 2, STI, O); |
| return; |
| break; |
| case 10: |
| // ADD_ZI_B, SQADD_ZI_B, SQSUB_ZI_B, SUBR_ZI_B, SUB_ZI_B, UQADD_ZI_B, UQS... |
| printImm8OptLsl<uint8_t>(MI, 2, STI, O); |
| return; |
| break; |
| case 11: |
| // ADD_ZI_D, SQADD_ZI_D, SQSUB_ZI_D, SUBR_ZI_D, SUB_ZI_D, UQADD_ZI_D, UQS... |
| printImm8OptLsl<uint64_t>(MI, 2, STI, O); |
| return; |
| break; |
| case 12: |
| // ADD_ZI_S, SQADD_ZI_S, SQSUB_ZI_S, SUBR_ZI_S, SUB_ZI_S, UQADD_ZI_S, UQS... |
| printImm8OptLsl<uint32_t>(MI, 2, STI, O); |
| return; |
| break; |
| case 13: |
| // ADD_ZPmZ_B, ADD_ZZZ_B, ANDS_PPzPP, ANDV_VPZ_B, AND_PPzPP, AND_ZPmZ_B, ... |
| printSVERegOp<'b'>(MI, 2, STI, O); |
| break; |
| case 14: |
| // ADD_ZPmZ_D, ADD_ZZZ_D, ANDV_VPZ_D, AND_ZPmZ_D, AND_ZZZ, ASRD_ZPmI_D, A... |
| printSVERegOp<'d'>(MI, 2, STI, O); |
| break; |
| case 15: |
| // ADD_ZPmZ_H, AND_ZPmZ_H, ASRD_ZPmI_H, ASRR_ZPmZ_H, ASR_WIDE_ZPmZ_H, ASR... |
| O << ", "; |
| break; |
| case 16: |
| // ADD_ZPmZ_S, ADD_ZZZ_S, ANDV_VPZ_S, AND_ZPmZ_S, ASRD_ZPmI_S, ASRR_ZPmZ_... |
| printSVERegOp<'s'>(MI, 2, STI, O); |
| break; |
| case 17: |
| // ADR_LSL_ZZZ_D_0 |
| printRegWithShiftExtend<false, 8, 'x', 'd'>(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 18: |
| // ADR_LSL_ZZZ_D_1 |
| printRegWithShiftExtend<false, 16, 'x', 'd'>(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 19: |
| // ADR_LSL_ZZZ_D_2 |
| printRegWithShiftExtend<false, 32, 'x', 'd'>(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 20: |
| // ADR_LSL_ZZZ_D_3 |
| printRegWithShiftExtend<false, 64, 'x', 'd'>(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 21: |
| // ADR_LSL_ZZZ_S_0 |
| printRegWithShiftExtend<false, 8, 'x', 's'>(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 22: |
| // ADR_LSL_ZZZ_S_1 |
| printRegWithShiftExtend<false, 16, 'x', 's'>(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 23: |
| // ADR_LSL_ZZZ_S_2 |
| printRegWithShiftExtend<false, 32, 'x', 's'>(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 24: |
| // ADR_LSL_ZZZ_S_3 |
| printRegWithShiftExtend<false, 64, 'x', 's'>(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 25: |
| // ADR_SXTW_ZZZ_D_0 |
| printRegWithShiftExtend<true, 8, 'w', 'd'>(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 26: |
| // ADR_SXTW_ZZZ_D_1 |
| printRegWithShiftExtend<true, 16, 'w', 'd'>(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 27: |
| // ADR_SXTW_ZZZ_D_2 |
| printRegWithShiftExtend<true, 32, 'w', 'd'>(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 28: |
| // ADR_SXTW_ZZZ_D_3 |
| printRegWithShiftExtend<true, 64, 'w', 'd'>(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 29: |
| // ADR_UXTW_ZZZ_D_0 |
| printRegWithShiftExtend<false, 8, 'w', 'd'>(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 30: |
| // ADR_UXTW_ZZZ_D_1 |
| printRegWithShiftExtend<false, 16, 'w', 'd'>(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 31: |
| // ADR_UXTW_ZZZ_D_2 |
| printRegWithShiftExtend<false, 32, 'w', 'd'>(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 32: |
| // ADR_UXTW_ZZZ_D_3 |
| printRegWithShiftExtend<false, 64, 'w', 'd'>(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 33: |
| // ANDSWri, ANDWri, EORWri, ORRWri |
| printLogicalImm<int32_t>(MI, 2, STI, O); |
| return; |
| break; |
| case 34: |
| // ANDSXri, ANDXri, AND_ZI, EORXri, EOR_ZI, ORRXri, ORR_ZI |
| printLogicalImm<int64_t>(MI, 2, STI, O); |
| return; |
| break; |
| case 35: |
| // ANDV_VPZ_H, CNTP_XPP_H, EORV_VPZ_H, FADDV_VPZ_H, FMAXNMV_VPZ_H, FMAXV_... |
| printSVERegOp<'h'>(MI, 2, STI, O); |
| return; |
| break; |
| case 36: |
| // BFMWri, BFMXri, CASAB, CASAH, CASALB, CASALH, CASALW, CASALX, CASAW, C... |
| printOperand(MI, 3, STI, O); |
| break; |
| case 37: |
| // CPY_ZPmI_B |
| printImm8OptLsl<int8_t>(MI, 3, STI, O); |
| return; |
| break; |
| case 38: |
| // CPY_ZPmI_D |
| printImm8OptLsl<int64_t>(MI, 3, STI, O); |
| return; |
| break; |
| case 39: |
| // CPY_ZPmI_S |
| printImm8OptLsl<int32_t>(MI, 3, STI, O); |
| return; |
| break; |
| case 40: |
| // CPY_ZPzI_B |
| printImm8OptLsl<int8_t>(MI, 2, STI, O); |
| return; |
| break; |
| case 41: |
| // CPY_ZPzI_D |
| printImm8OptLsl<int64_t>(MI, 2, STI, O); |
| return; |
| break; |
| case 42: |
| // CPY_ZPzI_S |
| printImm8OptLsl<int32_t>(MI, 2, STI, O); |
| return; |
| break; |
| case 43: |
| // FCMEQ_PPzZ0_H, FCMGE_PPzZ0_H, FCMGT_PPzZ0_H, FCMLE_PPzZ0_H, FCMLT_PPzZ... |
| O << ", #0.0"; |
| return; |
| break; |
| case 44: |
| // FCMLA_ZZZI_S, FMLA_ZZZI_D, FMLA_ZZZI_S, FMLS_ZZZI_D, FMLS_ZZZI_S |
| printVectorIndex(MI, 4, STI, O); |
| break; |
| case 45: |
| // FCPY_ZPmI_D, FCPY_ZPmI_S |
| printFPImmOperand(MI, 3, STI, O); |
| return; |
| break; |
| case 46: |
| // FCVTZS_ZPmZ_HtoD, FCVTZS_ZPmZ_HtoS, FCVTZU_ZPmZ_HtoD, FCVTZU_ZPmZ_HtoS... |
| printSVERegOp<'h'>(MI, 3, STI, O); |
| return; |
| break; |
| case 47: |
| // FMUL_ZZZI_H |
| printVectorIndex(MI, 3, STI, O); |
| return; |
| break; |
| case 48: |
| // GLD1B_D_IMM_REAL, GLD1B_S_IMM_REAL, GLD1SB_D_IMM_REAL, GLD1SB_S_IMM_RE... |
| O << ']'; |
| return; |
| break; |
| case 49: |
| // GLD1B_D_REAL, GLD1D_REAL, GLD1H_D_REAL, GLD1SB_D_REAL, GLD1SH_D_REAL, ... |
| printRegWithShiftExtend<false, 8, 'x', 'd'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 50: |
| // GLD1B_D_SXTW_REAL, GLD1D_SXTW_REAL, GLD1H_D_SXTW_REAL, GLD1SB_D_SXTW_R... |
| printRegWithShiftExtend<true, 8, 'w', 'd'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 51: |
| // GLD1B_D_UXTW_REAL, GLD1D_UXTW_REAL, GLD1H_D_UXTW_REAL, GLD1SB_D_UXTW_R... |
| printRegWithShiftExtend<false, 8, 'w', 'd'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 52: |
| // GLD1B_S_SXTW_REAL, GLD1H_S_SXTW_REAL, GLD1SB_S_SXTW_REAL, GLD1SH_S_SXT... |
| printRegWithShiftExtend<true, 8, 'w', 's'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 53: |
| // GLD1B_S_UXTW_REAL, GLD1H_S_UXTW_REAL, GLD1SB_S_UXTW_REAL, GLD1SH_S_UXT... |
| printRegWithShiftExtend<false, 8, 'w', 's'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 54: |
| // GLD1D_SCALED_REAL, GLDFF1D_SCALED_REAL, SST1D_SCALED |
| printRegWithShiftExtend<false, 64, 'x', 'd'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 55: |
| // GLD1D_SXTW_SCALED_REAL, GLDFF1D_SXTW_SCALED_REAL, SST1D_SXTW_SCALED |
| printRegWithShiftExtend<true, 64, 'w', 'd'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 56: |
| // GLD1D_UXTW_SCALED_REAL, GLDFF1D_UXTW_SCALED_REAL, SST1D_UXTW_SCALED |
| printRegWithShiftExtend<false, 64, 'w', 'd'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 57: |
| // GLD1H_D_SCALED_REAL, GLD1SH_D_SCALED_REAL, GLDFF1H_D_SCALED_REAL, GLDF... |
| printRegWithShiftExtend<false, 16, 'x', 'd'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 58: |
| // GLD1H_D_SXTW_SCALED_REAL, GLD1SH_D_SXTW_SCALED_REAL, GLDFF1H_D_SXTW_SC... |
| printRegWithShiftExtend<true, 16, 'w', 'd'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 59: |
| // GLD1H_D_UXTW_SCALED_REAL, GLD1SH_D_UXTW_SCALED_REAL, GLDFF1H_D_UXTW_SC... |
| printRegWithShiftExtend<false, 16, 'w', 'd'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 60: |
| // GLD1H_S_SXTW_SCALED_REAL, GLD1SH_S_SXTW_SCALED_REAL, GLDFF1H_S_SXTW_SC... |
| printRegWithShiftExtend<true, 16, 'w', 's'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 61: |
| // GLD1H_S_UXTW_SCALED_REAL, GLD1SH_S_UXTW_SCALED_REAL, GLDFF1H_S_UXTW_SC... |
| printRegWithShiftExtend<false, 16, 'w', 's'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 62: |
| // GLD1SW_D_SCALED_REAL, GLD1W_D_SCALED_REAL, GLDFF1SW_D_SCALED_REAL, GLD... |
| printRegWithShiftExtend<false, 32, 'x', 'd'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 63: |
| // GLD1SW_D_SXTW_SCALED_REAL, GLD1W_D_SXTW_SCALED_REAL, GLDFF1SW_D_SXTW_S... |
| printRegWithShiftExtend<true, 32, 'w', 'd'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 64: |
| // GLD1SW_D_UXTW_SCALED_REAL, GLD1W_D_UXTW_SCALED_REAL, GLDFF1SW_D_UXTW_S... |
| printRegWithShiftExtend<false, 32, 'w', 'd'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 65: |
| // GLD1W_SXTW_SCALED_REAL, GLDFF1W_SXTW_SCALED_REAL, SST1W_SXTW_SCALED |
| printRegWithShiftExtend<true, 32, 'w', 's'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 66: |
| // GLD1W_UXTW_SCALED_REAL, GLDFF1W_UXTW_SCALED_REAL, SST1W_UXTW_SCALED |
| printRegWithShiftExtend<false, 32, 'w', 's'>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 67: |
| // LD1B, LD1B_D, LD1B_H, LD1B_S, LD1RQ_B, LD1SB_D, LD1SB_H, LD1SB_S, LD2B... |
| printRegWithShiftExtend<false, 8, 'x', 0>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 68: |
| // LD1D, LD1RQ_D, LD2D, LD3D, LD4D, LDFF1D_REAL, LDNT1D_ZRR, ST1D, ST2D, ... |
| printRegWithShiftExtend<false, 64, 'x', 0>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 69: |
| // LD1H, LD1H_D, LD1H_S, LD1RQ_H, LD1SH_D, LD1SH_S, LD2H, LD3H, LD4H, LDF... |
| printRegWithShiftExtend<false, 16, 'x', 0>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 70: |
| // LD1RD_IMM, LDRAAwriteback, LDRABwriteback |
| printImmScale<8>(MI, 3, STI, O); |
| break; |
| case 71: |
| // LD1RH_D_IMM, LD1RH_IMM, LD1RH_S_IMM, LD1RSH_D_IMM, LD1RSH_S_IMM, LD2B_... |
| printImmScale<2>(MI, 3, STI, O); |
| break; |
| case 72: |
| // LD1RQ_B_IMM, LD1RQ_D_IMM, LD1RQ_H_IMM, LD1RQ_W_IMM |
| printImmScale<16>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 73: |
| // LD1RQ_W, LD1SW_D, LD1W, LD1W_D, LD2W, LD3W, LD4W, LDFF1SW_D_REAL, LDFF... |
| printRegWithShiftExtend<false, 32, 'x', 0>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 74: |
| // LD1RSW_IMM, LD1RW_D_IMM, LD1RW_IMM, LD4B_IMM, LD4D_IMM, LD4H_IMM, LD4W... |
| printImmScale<4>(MI, 3, STI, O); |
| break; |
| case 75: |
| // LD3B_IMM, LD3D_IMM, LD3H_IMM, LD3W_IMM, ST3B_IMM, ST3D_IMM, ST3H_IMM, ... |
| printImmScale<3>(MI, 3, STI, O); |
| O << ", mul vl]"; |
| return; |
| break; |
| case 76: |
| // LDRAAindexed, LDRABindexed |
| printImmScale<8>(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 77: |
| // LDRBBui, LDRBui, LDRSBWui, LDRSBXui, STRBBui, STRBui |
| printUImm12Offset<1>(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 78: |
| // LDRDui, LDRXui, PRFMui, STRDui, STRXui |
| printUImm12Offset<8>(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 79: |
| // LDRHHui, LDRHui, LDRSHWui, LDRSHXui, STRHHui, STRHui |
| printUImm12Offset<2>(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 80: |
| // LDRQui, STRQui |
| printUImm12Offset<16>(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 81: |
| // LDRSWui, LDRSui, LDRWui, STRSui, STRWui |
| printUImm12Offset<4>(MI, 2, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 82: |
| // PRFB_PRI, PRFD_PRI, PRFH_PRI, PRFW_PRI |
| O << ", mul vl]"; |
| return; |
| break; |
| case 83: |
| // SQDECP_XPWd_B, SQDECP_XPWd_D, SQDECP_XPWd_H, SQDECP_XPWd_S, SQINCP_XPW... |
| printGPR64as32(MI, 2, STI, O); |
| return; |
| break; |
| case 84: |
| // SYSLxt |
| printSysCROperand(MI, 2, STI, O); |
| O << ", "; |
| printSysCROperand(MI, 3, STI, O); |
| O << ", "; |
| printOperand(MI, 4, STI, O); |
| return; |
| break; |
| case 85: |
| // TBNZW, TBNZX, TBZW, TBZX |
| printAlignedLabel(MI, 2, STI, O); |
| return; |
| break; |
| case 86: |
| // UMAX_ZI_B, UMAX_ZI_D, UMAX_ZI_S, UMIN_ZI_B, UMIN_ZI_D, UMIN_ZI_S |
| printImm(MI, 2, STI, O); |
| return; |
| break; |
| } |
| |
| |
| // Fragment 5 encoded into 5 bits for 19 unique commands. |
| switch ((Bits >> 45) & 31) { |
| default: llvm_unreachable("Invalid command number."); |
| case 0: |
| // ABS_ZPmZ_B, ABS_ZPmZ_D, ABS_ZPmZ_S, ADCSWr, ADCSXr, ADCWr, ADCXr, ADDH... |
| return; |
| break; |
| case 1: |
| // ADDSXrx64, ADDXrx64, SUBSXrx64, SUBXrx64 |
| printArithExtend(MI, 3, STI, O); |
| return; |
| break; |
| case 2: |
| // ADD_ZPmZ_B, ADD_ZPmZ_D, ADD_ZPmZ_S, ANDS_PPzPP, AND_PPzPP, AND_ZPmZ_B,... |
| O << ", "; |
| break; |
| case 3: |
| // ADD_ZPmZ_H, AND_ZPmZ_H, ASRR_ZPmZ_H, ASR_ZPmZ_H, BIC_ZPmZ_H, CLASTA_ZP... |
| printSVERegOp<'h'>(MI, 3, STI, O); |
| break; |
| case 4: |
| // ASRD_ZPmI_H, ASR_ZPmI_H, CMPEQ_PPzZI_H, CMPGE_PPzZI_H, CMPGT_PPzZI_H, ... |
| printOperand(MI, 3, STI, O); |
| return; |
| break; |
| case 5: |
| // ASR_WIDE_ZPmZ_H, CMPEQ_WIDE_PPzZZ_H, CMPGE_WIDE_PPzZZ_H, CMPGT_WIDE_PP... |
| printSVERegOp<'d'>(MI, 3, STI, O); |
| return; |
| break; |
| case 6: |
| // CASAB, CASAH, CASALB, CASALH, CASALW, CASALX, CASAW, CASAX, CASB, CASH... |
| O << ']'; |
| return; |
| break; |
| case 7: |
| // CMPHI_PPzZI_H, CMPHS_PPzZI_H, CMPLO_PPzZI_H, CMPLS_PPzZI_H |
| printImm(MI, 3, STI, O); |
| return; |
| break; |
| case 8: |
| // FADD_ZPmI_H, FSUBR_ZPmI_H, FSUB_ZPmI_H |
| printExactFPImm<AArch64ExactFPImm::half, AArch64ExactFPImm::one>(MI, 3, STI, O); |
| return; |
| break; |
| case 9: |
| // FCMEQ_PPzZ0_D, FCMEQ_PPzZ0_S, FCMGE_PPzZ0_D, FCMGE_PPzZ0_S, FCMGT_PPzZ... |
| O << ", #0.0"; |
| return; |
| break; |
| case 10: |
| // FCMLA_ZPmZZ_H, FMAD_ZPmZZ_H, FMLA_ZPmZZ_H, FMLS_ZPmZZ_H, FMSB_ZPmZZ_H,... |
| printSVERegOp<'h'>(MI, 4, STI, O); |
| break; |
| case 11: |
| // FCMLAv4f16_indexed, FCMLAv4f32_indexed, FCMLAv8f16_indexed, FMLAv1i16_... |
| printVectorIndex(MI, 4, STI, O); |
| break; |
| case 12: |
| // FMAXNM_ZPmI_H, FMAX_ZPmI_H, FMINNM_ZPmI_H, FMIN_ZPmI_H |
| printExactFPImm<AArch64ExactFPImm::zero, AArch64ExactFPImm::one>(MI, 3, STI, O); |
| return; |
| break; |
| case 13: |
| // FMULXv1i16_indexed, FMULXv1i32_indexed, FMULXv1i64_indexed, FMULXv2i32... |
| printVectorIndex(MI, 3, STI, O); |
| return; |
| break; |
| case 14: |
| // FMUL_ZPmI_H |
| printExactFPImm<AArch64ExactFPImm::half, AArch64ExactFPImm::two>(MI, 3, STI, O); |
| return; |
| break; |
| case 15: |
| // LD1B_D_IMM_REAL, LD1B_H_IMM_REAL, LD1B_IMM_REAL, LD1B_S_IMM_REAL, LD1D... |
| O << ", mul vl]"; |
| return; |
| break; |
| case 16: |
| // LDPDpost, LDPQpost, LDPSWpost, LDPSpost, LDPWpost, LDPXpost, STPDpost,... |
| O << "], "; |
| break; |
| case 17: |
| // LDRAAwriteback, LDRABwriteback, LDRBBpre, LDRBpre, LDRDpre, LDRHHpre, ... |
| O << "]!"; |
| return; |
| break; |
| case 18: |
| // STLXPW, STLXPX, STXPW, STXPX |
| O << ", ["; |
| printOperand(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| } |
| |
| |
| // Fragment 6 encoded into 6 bits for 35 unique commands. |
| switch ((Bits >> 50) & 63) { |
| default: llvm_unreachable("Invalid command number."); |
| case 0: |
| // ADD_ZPmZ_B, ANDS_PPzPP, AND_PPzPP, AND_ZPmZ_B, ASRR_ZPmZ_B, ASR_ZPmZ_B... |
| printSVERegOp<'b'>(MI, 3, STI, O); |
| return; |
| break; |
| case 1: |
| // ADD_ZPmZ_D, AND_ZPmZ_D, ASRR_ZPmZ_D, ASR_WIDE_ZPmZ_B, ASR_WIDE_ZPmZ_S,... |
| printSVERegOp<'d'>(MI, 3, STI, O); |
| break; |
| case 2: |
| // ADD_ZPmZ_H, AND_ZPmZ_H, ASRR_ZPmZ_H, ASR_ZPmZ_H, BIC_ZPmZ_H, CLASTA_ZP... |
| return; |
| break; |
| case 3: |
| // ADD_ZPmZ_S, AND_ZPmZ_S, ASRR_ZPmZ_S, ASR_ZPmZ_S, BIC_ZPmZ_S, CLASTA_RP... |
| printSVERegOp<'s'>(MI, 3, STI, O); |
| break; |
| case 4: |
| // ASRD_ZPmI_B, ASRD_ZPmI_D, ASRD_ZPmI_S, ASR_ZPmI_B, ASR_ZPmI_D, ASR_ZPm... |
| printOperand(MI, 3, STI, O); |
| return; |
| break; |
| case 5: |
| // BFMWri, BFMXri |
| printOperand(MI, 4, STI, O); |
| return; |
| break; |
| case 6: |
| // CCMNWi, CCMNWr, CCMNXi, CCMNXr, CCMPWi, CCMPWr, CCMPXi, CCMPXr, CSELWr... |
| printCondCode(MI, 3, STI, O); |
| return; |
| break; |
| case 7: |
| // CLASTA_RPZ_H, CLASTA_VPZ_H, CLASTB_RPZ_H, CLASTB_VPZ_H, FADDA_VPZ_H |
| printSVERegOp<'h'>(MI, 3, STI, O); |
| return; |
| break; |
| case 8: |
| // CMPHI_PPzZI_B, CMPHI_PPzZI_D, CMPHI_PPzZI_S, CMPHS_PPzZI_B, CMPHS_PPzZ... |
| printImm(MI, 3, STI, O); |
| return; |
| break; |
| case 9: |
| // FADD_ZPmI_D, FADD_ZPmI_S, FSUBR_ZPmI_D, FSUBR_ZPmI_S, FSUB_ZPmI_D, FSU... |
| printExactFPImm<AArch64ExactFPImm::half, AArch64ExactFPImm::one>(MI, 3, STI, O); |
| return; |
| break; |
| case 10: |
| // FCADD_ZPmZ_H, FCMLA_ZPmZZ_H, FCMLAv4f16_indexed, FCMLAv4f32_indexed, F... |
| O << ", "; |
| break; |
| case 11: |
| // FCADDv2f32, FCADDv2f64, FCADDv4f16, FCADDv4f32, FCADDv8f16 |
| printComplexRotationOp<180, 90>(MI, 3, STI, O); |
| return; |
| break; |
| case 12: |
| // FCMLA_ZPmZZ_D, FMAD_ZPmZZ_D, FMLA_ZPmZZ_D, FMLS_ZPmZZ_D, FMSB_ZPmZZ_D,... |
| printSVERegOp<'d'>(MI, 4, STI, O); |
| break; |
| case 13: |
| // FCMLA_ZPmZZ_S, FMAD_ZPmZZ_S, FMLA_ZPmZZ_S, FMLS_ZPmZZ_S, FMSB_ZPmZZ_S,... |
| printSVERegOp<'s'>(MI, 4, STI, O); |
| break; |
| case 14: |
| // FCMLA_ZZZI_S |
| printComplexRotationOp<90, 0>(MI, 5, STI, O); |
| return; |
| break; |
| case 15: |
| // FCMLAv2f32, FCMLAv2f64, FCMLAv4f16, FCMLAv4f32, FCMLAv8f16 |
| printComplexRotationOp<90, 0>(MI, 4, STI, O); |
| return; |
| break; |
| case 16: |
| // FMAXNM_ZPmI_D, FMAXNM_ZPmI_S, FMAX_ZPmI_D, FMAX_ZPmI_S, FMINNM_ZPmI_D,... |
| printExactFPImm<AArch64ExactFPImm::zero, AArch64ExactFPImm::one>(MI, 3, STI, O); |
| return; |
| break; |
| case 17: |
| // FMUL_ZPmI_D, FMUL_ZPmI_S |
| printExactFPImm<AArch64ExactFPImm::half, AArch64ExactFPImm::two>(MI, 3, STI, O); |
| return; |
| break; |
| case 18: |
| // LDNPDi, LDNPXi, LDPDi, LDPXi, STNPDi, STNPXi, STPDi, STPXi |
| printImmScale<8>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 19: |
| // LDNPQi, LDPQi, STNPQi, STPQi |
| printImmScale<16>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 20: |
| // LDNPSi, LDNPWi, LDPSWi, LDPSi, LDPWi, STNPSi, STNPWi, STPSi, STPWi |
| printImmScale<4>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 21: |
| // LDPDpost, LDPDpre, LDPXpost, LDPXpre, STPDpost, STPDpre, STPXpost, STP... |
| printImmScale<8>(MI, 4, STI, O); |
| break; |
| case 22: |
| // LDPQpost, LDPQpre, STPQpost, STPQpre |
| printImmScale<16>(MI, 4, STI, O); |
| break; |
| case 23: |
| // LDPSWpost, LDPSWpre, LDPSpost, LDPSpre, LDPWpost, LDPWpre, STPSpost, S... |
| printImmScale<4>(MI, 4, STI, O); |
| break; |
| case 24: |
| // LDRBBroW, LDRBroW, LDRSBWroW, LDRSBXroW, STRBBroW, STRBroW |
| printMemExtend<'w', 8>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 25: |
| // LDRBBroX, LDRBroX, LDRSBWroX, LDRSBXroX, STRBBroX, STRBroX |
| printMemExtend<'x', 8>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 26: |
| // LDRDroW, LDRXroW, PRFMroW, STRDroW, STRXroW |
| printMemExtend<'w', 64>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 27: |
| // LDRDroX, LDRXroX, PRFMroX, STRDroX, STRXroX |
| printMemExtend<'x', 64>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 28: |
| // LDRHHroW, LDRHroW, LDRSHWroW, LDRSHXroW, STRHHroW, STRHroW |
| printMemExtend<'w', 16>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 29: |
| // LDRHHroX, LDRHroX, LDRSHWroX, LDRSHXroX, STRHHroX, STRHroX |
| printMemExtend<'x', 16>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 30: |
| // LDRQroW, STRQroW |
| printMemExtend<'w', 128>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 31: |
| // LDRQroX, STRQroX |
| printMemExtend<'x', 128>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 32: |
| // LDRSWroW, LDRSroW, LDRWroW, STRSroW, STRWroW |
| printMemExtend<'w', 32>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 33: |
| // LDRSWroX, LDRSroX, LDRWroX, STRSroX, STRWroX |
| printMemExtend<'x', 32>(MI, 3, STI, O); |
| O << ']'; |
| return; |
| break; |
| case 34: |
| // MAD_ZPmZZ_B, MLA_ZPmZZ_B, MLS_ZPmZZ_B, MSB_ZPmZZ_B |
| printSVERegOp<'b'>(MI, 4, STI, O); |
| return; |
| break; |
| } |
| |
| |
| // Fragment 7 encoded into 3 bits for 5 unique commands. |
| switch ((Bits >> 56) & 7) { |
| default: llvm_unreachable("Invalid command number."); |
| case 0: |
| // ADD_ZPmZ_D, ADD_ZPmZ_S, AND_ZPmZ_D, AND_ZPmZ_S, ASRR_ZPmZ_D, ASRR_ZPmZ... |
| return; |
| break; |
| case 1: |
| // FCADD_ZPmZ_D, FCADD_ZPmZ_S, FCMLA_ZPmZZ_D, FCMLA_ZPmZZ_S |
| O << ", "; |
| break; |
| case 2: |
| // FCADD_ZPmZ_H |
| printComplexRotationOp<180, 90>(MI, 4, STI, O); |
| return; |
| break; |
| case 3: |
| // FCMLA_ZPmZZ_H, FCMLAv4f16_indexed, FCMLAv4f32_indexed, FCMLAv8f16_inde... |
| printComplexRotationOp<90, 0>(MI, 5, STI, O); |
| return; |
| break; |
| case 4: |
| // LDPDpre, LDPQpre, LDPSWpre, LDPSpre, LDPWpre, LDPXpre, STPDpre, STPQpr... |
| O << "]!"; |
| return; |
| break; |
| } |
| |
| |
| // Fragment 8 encoded into 1 bits for 2 unique commands. |
| if ((Bits >> 59) & 1) { |
| // FCMLA_ZPmZZ_D, FCMLA_ZPmZZ_S |
| printComplexRotationOp<90, 0>(MI, 5, STI, O); |
| return; |
| } else { |
| // FCADD_ZPmZ_D, FCADD_ZPmZ_S |
| printComplexRotationOp<180, 90>(MI, 4, STI, O); |
| return; |
| } |
| |
| } |
| |
| |
| /// getRegisterName - This method is automatically generated by tblgen |
| /// from the register set description. This returns the assembler name |
| /// for the specified register. |
| const char *AArch64AppleInstPrinter:: |
| getRegisterName(unsigned RegNo, unsigned AltIdx) { |
| assert(RegNo && RegNo < 661 && "Invalid register number!"); |
| |
| static const char AsmStrsNoRegAltName[] = { |
| /* 0 */ 'D', '7', '_', 'D', '8', '_', 'D', '9', '_', 'D', '1', '0', 0, |
| /* 13 */ 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', 0, |
| /* 26 */ 'W', '9', '_', 'W', '1', '0', 0, |
| /* 33 */ 'X', '9', '_', 'X', '1', '0', 0, |
| /* 40 */ 'Z', '7', '_', 'Z', '8', '_', 'Z', '9', '_', 'Z', '1', '0', 0, |
| /* 53 */ 'b', '1', '0', 0, |
| /* 57 */ 'd', '1', '0', 0, |
| /* 61 */ 'h', '1', '0', 0, |
| /* 65 */ 'p', '1', '0', 0, |
| /* 69 */ 'q', '1', '0', 0, |
| /* 73 */ 's', '1', '0', 0, |
| /* 77 */ 'w', '1', '0', 0, |
| /* 81 */ 'x', '1', '0', 0, |
| /* 85 */ 'z', '1', '0', 0, |
| /* 89 */ 'D', '1', '7', '_', 'D', '1', '8', '_', 'D', '1', '9', '_', 'D', '2', '0', 0, |
| /* 105 */ 'Q', '1', '7', '_', 'Q', '1', '8', '_', 'Q', '1', '9', '_', 'Q', '2', '0', 0, |
| /* 121 */ 'W', '1', '9', '_', 'W', '2', '0', 0, |
| /* 129 */ 'X', '1', '9', '_', 'X', '2', '0', 0, |
| /* 137 */ 'Z', '1', '7', '_', 'Z', '1', '8', '_', 'Z', '1', '9', '_', 'Z', '2', '0', 0, |
| /* 153 */ 'b', '2', '0', 0, |
| /* 157 */ 'd', '2', '0', 0, |
| /* 161 */ 'h', '2', '0', 0, |
| /* 165 */ 'q', '2', '0', 0, |
| /* 169 */ 's', '2', '0', 0, |
| /* 173 */ 'w', '2', '0', 0, |
| /* 177 */ 'x', '2', '0', 0, |
| /* 181 */ 'z', '2', '0', 0, |
| /* 185 */ 'D', '2', '7', '_', 'D', '2', '8', '_', 'D', '2', '9', '_', 'D', '3', '0', 0, |
| /* 201 */ 'Q', '2', '7', '_', 'Q', '2', '8', '_', 'Q', '2', '9', '_', 'Q', '3', '0', 0, |
| /* 217 */ 'W', '2', '9', '_', 'W', '3', '0', 0, |
| /* 225 */ 'Z', '2', '7', '_', 'Z', '2', '8', '_', 'Z', '2', '9', '_', 'Z', '3', '0', 0, |
| /* 241 */ 'b', '3', '0', 0, |
| /* 245 */ 'd', '3', '0', 0, |
| /* 249 */ 'h', '3', '0', 0, |
| /* 253 */ 'q', '3', '0', 0, |
| /* 257 */ 's', '3', '0', 0, |
| /* 261 */ 'w', '3', '0', 0, |
| /* 265 */ 'x', '3', '0', 0, |
| /* 269 */ 'z', '3', '0', 0, |
| /* 273 */ 'D', '2', '9', '_', 'D', '3', '0', '_', 'D', '3', '1', '_', 'D', '0', 0, |
| /* 288 */ 'Q', '2', '9', '_', 'Q', '3', '0', '_', 'Q', '3', '1', '_', 'Q', '0', 0, |
| /* 303 */ 'W', 'Z', 'R', '_', 'W', '0', 0, |
| /* 310 */ 'X', 'Z', 'R', '_', 'X', '0', 0, |
| /* 317 */ 'Z', '2', '9', '_', 'Z', '3', '0', '_', 'Z', '3', '1', '_', 'Z', '0', 0, |
| /* 332 */ 'b', '0', 0, |
| /* 335 */ 'd', '0', 0, |
| /* 338 */ 'h', '0', 0, |
| /* 341 */ 'p', '0', 0, |
| /* 344 */ 'q', '0', 0, |
| /* 347 */ 's', '0', 0, |
| /* 350 */ 'w', '0', 0, |
| /* 353 */ 'x', '0', 0, |
| /* 356 */ 'z', '0', 0, |
| /* 359 */ 'D', '8', '_', 'D', '9', '_', 'D', '1', '0', '_', 'D', '1', '1', 0, |
| /* 373 */ 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', '_', 'Q', '1', '1', 0, |
| /* 387 */ 'W', '1', '0', '_', 'W', '1', '1', 0, |
| /* 395 */ 'X', '1', '0', '_', 'X', '1', '1', 0, |
| /* 403 */ 'Z', '8', '_', 'Z', '9', '_', 'Z', '1', '0', '_', 'Z', '1', '1', 0, |
| /* 417 */ 'b', '1', '1', 0, |
| /* 421 */ 'd', '1', '1', 0, |
| /* 425 */ 'h', '1', '1', 0, |
| /* 429 */ 'p', '1', '1', 0, |
| /* 433 */ 'q', '1', '1', 0, |
| /* 437 */ 's', '1', '1', 0, |
| /* 441 */ 'w', '1', '1', 0, |
| /* 445 */ 'x', '1', '1', 0, |
| /* 449 */ 'z', '1', '1', 0, |
| /* 453 */ 'D', '1', '8', '_', 'D', '1', '9', '_', 'D', '2', '0', '_', 'D', '2', '1', 0, |
| /* 469 */ 'Q', '1', '8', '_', 'Q', '1', '9', '_', 'Q', '2', '0', '_', 'Q', '2', '1', 0, |
| /* 485 */ 'W', '2', '0', '_', 'W', '2', '1', 0, |
| /* 493 */ 'X', '2', '0', '_', 'X', '2', '1', 0, |
| /* 501 */ 'Z', '1', '8', '_', 'Z', '1', '9', '_', 'Z', '2', '0', '_', 'Z', '2', '1', 0, |
| /* 517 */ 'b', '2', '1', 0, |
| /* 521 */ 'd', '2', '1', 0, |
| /* 525 */ 'h', '2', '1', 0, |
| /* 529 */ 'q', '2', '1', 0, |
| /* 533 */ 's', '2', '1', 0, |
| /* 537 */ 'w', '2', '1', 0, |
| /* 541 */ 'x', '2', '1', 0, |
| /* 545 */ 'z', '2', '1', 0, |
| /* 549 */ 'D', '2', '8', '_', 'D', '2', '9', '_', 'D', '3', '0', '_', 'D', '3', '1', 0, |
| /* 565 */ 'Q', '2', '8', '_', 'Q', '2', '9', '_', 'Q', '3', '0', '_', 'Q', '3', '1', 0, |
| /* 581 */ 'Z', '2', '8', '_', 'Z', '2', '9', '_', 'Z', '3', '0', '_', 'Z', '3', '1', 0, |
| /* 597 */ 'b', '3', '1', 0, |
| /* 601 */ 'd', '3', '1', 0, |
| /* 605 */ 'h', '3', '1', 0, |
| /* 609 */ 'q', '3', '1', 0, |
| /* 613 */ 's', '3', '1', 0, |
| /* 617 */ 'z', '3', '1', 0, |
| /* 621 */ 'D', '3', '0', '_', 'D', '3', '1', '_', 'D', '0', '_', 'D', '1', 0, |
| /* 635 */ 'Q', '3', '0', '_', 'Q', '3', '1', '_', 'Q', '0', '_', 'Q', '1', 0, |
| /* 649 */ 'W', '0', '_', 'W', '1', 0, |
| /* 655 */ 'X', '0', '_', 'X', '1', 0, |
| /* 661 */ 'Z', '3', '0', '_', 'Z', '3', '1', '_', 'Z', '0', '_', 'Z', '1', 0, |
| /* 675 */ 'b', '1', 0, |
| /* 678 */ 'd', '1', 0, |
| /* 681 */ 'h', '1', 0, |
| /* 684 */ 'p', '1', 0, |
| /* 687 */ 'q', '1', 0, |
| /* 690 */ 's', '1', 0, |
| /* 693 */ 'w', '1', 0, |
| /* 696 */ 'x', '1', 0, |
| /* 699 */ 'z', '1', 0, |
| /* 702 */ 'D', '9', '_', 'D', '1', '0', '_', 'D', '1', '1', '_', 'D', '1', '2', 0, |
| /* 717 */ 'Q', '9', '_', 'Q', '1', '0', '_', 'Q', '1', '1', '_', 'Q', '1', '2', 0, |
| /* 732 */ 'W', '1', '1', '_', 'W', '1', '2', 0, |
| /* 740 */ 'X', '1', '1', '_', 'X', '1', '2', 0, |
| /* 748 */ 'Z', '9', '_', 'Z', '1', '0', '_', 'Z', '1', '1', '_', 'Z', '1', '2', 0, |
| /* 763 */ 'b', '1', '2', 0, |
| /* 767 */ 'd', '1', '2', 0, |
| /* 771 */ 'h', '1', '2', 0, |
| /* 775 */ 'p', '1', '2', 0, |
| /* 779 */ 'q', '1', '2', 0, |
| /* 783 */ 's', '1', '2', 0, |
| /* 787 */ 'w', '1', '2', 0, |
| /* 791 */ 'x', '1', '2', 0, |
| /* 795 */ 'z', '1', '2', 0, |
| /* 799 */ 'D', '1', '9', '_', 'D', '2', '0', '_', 'D', '2', '1', '_', 'D', '2', '2', 0, |
| /* 815 */ 'Q', '1', '9', '_', 'Q', '2', '0', '_', 'Q', '2', '1', '_', 'Q', '2', '2', 0, |
| /* 831 */ 'W', '2', '1', '_', 'W', '2', '2', 0, |
| /* 839 */ 'X', '2', '1', '_', 'X', '2', '2', 0, |
| /* 847 */ 'Z', '1', '9', '_', 'Z', '2', '0', '_', 'Z', '2', '1', '_', 'Z', '2', '2', 0, |
| /* 863 */ 'b', '2', '2', 0, |
| /* 867 */ 'd', '2', '2', 0, |
| /* 871 */ 'h', '2', '2', 0, |
| /* 875 */ 'q', '2', '2', 0, |
| /* 879 */ 's', '2', '2', 0, |
| /* 883 */ 'w', '2', '2', 0, |
| /* 887 */ 'x', '2', '2', 0, |
| /* 891 */ 'z', '2', '2', 0, |
| /* 895 */ 'D', '3', '1', '_', 'D', '0', '_', 'D', '1', '_', 'D', '2', 0, |
| /* 908 */ 'Q', '3', '1', '_', 'Q', '0', '_', 'Q', '1', '_', 'Q', '2', 0, |
| /* 921 */ 'W', '1', '_', 'W', '2', 0, |
| /* 927 */ 'X', '1', '_', 'X', '2', 0, |
| /* 933 */ 'Z', '3', '1', '_', 'Z', '0', '_', 'Z', '1', '_', 'Z', '2', 0, |
| /* 946 */ 'b', '2', 0, |
| /* 949 */ 'd', '2', 0, |
| /* 952 */ 'h', '2', 0, |
| /* 955 */ 'p', '2', 0, |
| /* 958 */ 'q', '2', 0, |
| /* 961 */ 's', '2', 0, |
| /* 964 */ 'w', '2', 0, |
| /* 967 */ 'x', '2', 0, |
| /* 970 */ 'z', '2', 0, |
| /* 973 */ 'D', '1', '0', '_', 'D', '1', '1', '_', 'D', '1', '2', '_', 'D', '1', '3', 0, |
| /* 989 */ 'Q', '1', '0', '_', 'Q', '1', '1', '_', 'Q', '1', '2', '_', 'Q', '1', '3', 0, |
| /* 1005 */ 'W', '1', '2', '_', 'W', '1', '3', 0, |
| /* 1013 */ 'X', '1', '2', '_', 'X', '1', '3', 0, |
| /* 1021 */ 'Z', '1', '0', '_', 'Z', '1', '1', '_', 'Z', '1', '2', '_', 'Z', '1', '3', 0, |
| /* 1037 */ 'b', '1', '3', 0, |
| /* 1041 */ 'd', '1', '3', 0, |
| /* 1045 */ 'h', '1', '3', 0, |
| /* 1049 */ 'p', '1', '3', 0, |
| /* 1053 */ 'q', '1', '3', 0, |
| /* 1057 */ 's', '1', '3', 0, |
| /* 1061 */ 'w', '1', '3', 0, |
| /* 1065 */ 'x', '1', '3', 0, |
| /* 1069 */ 'z', '1', '3', 0, |
| /* 1073 */ 'D', '2', '0', '_', 'D', '2', '1', '_', 'D', '2', '2', '_', 'D', '2', '3', 0, |
| /* 1089 */ 'Q', '2', '0', '_', 'Q', '2', '1', '_', 'Q', '2', '2', '_', 'Q', '2', '3', 0, |
| /* 1105 */ 'W', '2', '2', '_', 'W', '2', '3', 0, |
| /* 1113 */ 'X', '2', '2', '_', 'X', '2', '3', 0, |
| /* 1121 */ 'Z', '2', '0', '_', 'Z', '2', '1', '_', 'Z', '2', '2', '_', 'Z', '2', '3', 0, |
| /* 1137 */ 'b', '2', '3', 0, |
| /* 1141 */ 'd', '2', '3', 0, |
| /* 1145 */ 'h', '2', '3', 0, |
| /* 1149 */ 'q', '2', '3', 0, |
| /* 1153 */ 's', '2', '3', 0, |
| /* 1157 */ 'w', '2', '3', 0, |
| /* 1161 */ 'x', '2', '3', 0, |
| /* 1165 */ 'z', '2', '3', 0, |
| /* 1169 */ 'D', '0', '_', 'D', '1', '_', 'D', '2', '_', 'D', '3', 0, |
| /* 1181 */ 'Q', '0', '_', 'Q', '1', '_', 'Q', '2', '_', 'Q', '3', 0, |
| /* 1193 */ 'W', '2', '_', 'W', '3', 0, |
| /* 1199 */ 'X', '2', '_', 'X', '3', 0, |
| /* 1205 */ 'Z', '0', '_', 'Z', '1', '_', 'Z', '2', '_', 'Z', '3', 0, |
| /* 1217 */ 'b', '3', 0, |
| /* 1220 */ 'd', '3', 0, |
| /* 1223 */ 'h', '3', 0, |
| /* 1226 */ 'p', '3', 0, |
| /* 1229 */ 'q', '3', 0, |
| /* 1232 */ 's', '3', 0, |
| /* 1235 */ 'w', '3', 0, |
| /* 1238 */ 'x', '3', 0, |
| /* 1241 */ 'z', '3', 0, |
| /* 1244 */ 'D', '1', '1', '_', 'D', '1', '2', '_', 'D', '1', '3', '_', 'D', '1', '4', 0, |
| /* 1260 */ 'Q', '1', '1', '_', 'Q', '1', '2', '_', 'Q', '1', '3', '_', 'Q', '1', '4', 0, |
| /* 1276 */ 'W', '1', '3', '_', 'W', '1', '4', 0, |
| /* 1284 */ 'X', '1', '3', '_', 'X', '1', '4', 0, |
| /* 1292 */ 'Z', '1', '1', '_', 'Z', '1', '2', '_', 'Z', '1', '3', '_', 'Z', '1', '4', 0, |
| /* 1308 */ 'b', '1', '4', 0, |
| /* 1312 */ 'd', '1', '4', 0, |
| /* 1316 */ 'h', '1', '4', 0, |
| /* 1320 */ 'p', '1', '4', 0, |
| /* 1324 */ 'q', '1', '4', 0, |
| /* 1328 */ 's', '1', '4', 0, |
| /* 1332 */ 'w', '1', '4', 0, |
| /* 1336 */ 'x', '1', '4', 0, |
| /* 1340 */ 'z', '1', '4', 0, |
| /* 1344 */ 'D', '2', '1', '_', 'D', '2', '2', '_', 'D', '2', '3', '_', 'D', '2', '4', 0, |
| /* 1360 */ 'Q', '2', '1', '_', 'Q', '2', '2', '_', 'Q', '2', '3', '_', 'Q', '2', '4', 0, |
| /* 1376 */ 'W', '2', '3', '_', 'W', '2', '4', 0, |
| /* 1384 */ 'X', '2', '3', '_', 'X', '2', '4', 0, |
| /* 1392 */ 'Z', '2', '1', '_', 'Z', '2', '2', '_', 'Z', '2', '3', '_', 'Z', '2', '4', 0, |
| /* 1408 */ 'b', '2', '4', 0, |
| /* 1412 */ 'd', '2', '4', 0, |
| /* 1416 */ 'h', '2', '4', 0, |
| /* 1420 */ 'q', '2', '4', 0, |
| /* 1424 */ 's', '2', '4', 0, |
| /* 1428 */ 'w', '2', '4', 0, |
| /* 1432 */ 'x', '2', '4', 0, |
| /* 1436 */ 'z', '2', '4', 0, |
| /* 1440 */ 'D', '1', '_', 'D', '2', '_', 'D', '3', '_', 'D', '4', 0, |
| /* 1452 */ 'Q', '1', '_', 'Q', '2', '_', 'Q', '3', '_', 'Q', '4', 0, |
| /* 1464 */ 'W', '3', '_', 'W', '4', 0, |
| /* 1470 */ 'X', '3', '_', 'X', '4', 0, |
| /* 1476 */ 'Z', '1', '_', 'Z', '2', '_', 'Z', '3', '_', 'Z', '4', 0, |
| /* 1488 */ 'b', '4', 0, |
| /* 1491 */ 'd', '4', 0, |
| /* 1494 */ 'h', '4', 0, |
| /* 1497 */ 'p', '4', 0, |
| /* 1500 */ 'q', '4', 0, |
| /* 1503 */ 's', '4', 0, |
| /* 1506 */ 'w', '4', 0, |
| /* 1509 */ 'x', '4', 0, |
| /* 1512 */ 'z', '4', 0, |
| /* 1515 */ 'D', '1', '2', '_', 'D', '1', '3', '_', 'D', '1', '4', '_', 'D', '1', '5', 0, |
| /* 1531 */ 'Q', '1', '2', '_', 'Q', '1', '3', '_', 'Q', '1', '4', '_', 'Q', '1', '5', 0, |
| /* 1547 */ 'W', '1', '4', '_', 'W', '1', '5', 0, |
| /* 1555 */ 'X', '1', '4', '_', 'X', '1', '5', 0, |
| /* 1563 */ 'Z', '1', '2', '_', 'Z', '1', '3', '_', 'Z', '1', '4', '_', 'Z', '1', '5', 0, |
| /* 1579 */ 'b', '1', '5', 0, |
| /* 1583 */ 'd', '1', '5', 0, |
| /* 1587 */ 'h', '1', '5', 0, |
| /* 1591 */ 'p', '1', '5', 0, |
| /* 1595 */ 'q', '1', '5', 0, |
| /* 1599 */ 's', '1', '5', 0, |
| /* 1603 */ 'w', '1', '5', 0, |
| /* 1607 */ 'x', '1', '5', 0, |
| /* 1611 */ 'z', '1', '5', 0, |
| /* 1615 */ 'D', '2', '2', '_', 'D', '2', '3', '_', 'D', '2', '4', '_', 'D', '2', '5', 0, |
| /* 1631 */ 'Q', '2', '2', '_', 'Q', '2', '3', '_', 'Q', '2', '4', '_', 'Q', '2', '5', 0, |
| /* 1647 */ 'W', '2', '4', '_', 'W', '2', '5', 0, |
| /* 1655 */ 'X', '2', '4', '_', 'X', '2', '5', 0, |
| /* 1663 */ 'Z', '2', '2', '_', 'Z', '2', '3', '_', 'Z', '2', '4', '_', 'Z', '2', '5', 0, |
| /* 1679 */ 'b', '2', '5', 0, |
| /* 1683 */ 'd', '2', '5', 0, |
| /* 1687 */ 'h', '2', '5', 0, |
| /* 1691 */ 'q', '2', '5', 0, |
| /* 1695 */ 's', '2', '5', 0, |
| /* 1699 */ 'w', '2', '5', 0, |
| /* 1703 */ 'x', '2', '5', 0, |
| /* 1707 */ 'z', '2', '5', 0, |
| /* 1711 */ 'D', '2', '_', 'D', '3', '_', 'D', '4', '_', 'D', '5', 0, |
| /* 1723 */ 'Q', '2', '_', 'Q', '3', '_', 'Q', '4', '_', 'Q', '5', 0, |
| /* 1735 */ 'W', '4', '_', 'W', '5', 0, |
| /* 1741 */ 'X', '4', '_', 'X', '5', 0, |
| /* 1747 */ 'Z', '2', '_', 'Z', '3', '_', 'Z', '4', '_', 'Z', '5', 0, |
| /* 1759 */ 'b', '5', 0, |
| /* 1762 */ 'd', '5', 0, |
| /* 1765 */ 'h', '5', 0, |
| /* 1768 */ 'p', '5', 0, |
| /* 1771 */ 'q', '5', 0, |
| /* 1774 */ 's', '5', 0, |
| /* 1777 */ 'w', '5', 0, |
| /* 1780 */ 'x', '5', 0, |
| /* 1783 */ 'z', '5', 0, |
| /* 1786 */ 'D', '1', '3', '_', 'D', '1', '4', '_', 'D', '1', '5', '_', 'D', '1', '6', 0, |
| /* 1802 */ 'Q', '1', '3', '_', 'Q', '1', '4', '_', 'Q', '1', '5', '_', 'Q', '1', '6', 0, |
| /* 1818 */ 'W', '1', '5', '_', 'W', '1', '6', 0, |
| /* 1826 */ 'X', '1', '5', '_', 'X', '1', '6', 0, |
| /* 1834 */ 'Z', '1', '3', '_', 'Z', '1', '4', '_', 'Z', '1', '5', '_', 'Z', '1', '6', 0, |
| /* 1850 */ 'b', '1', '6', 0, |
| /* 1854 */ 'd', '1', '6', 0, |
| /* 1858 */ 'h', '1', '6', 0, |
| /* 1862 */ 'q', '1', '6', 0, |
| /* 1866 */ 's', '1', '6', 0, |
| /* 1870 */ 'w', '1', '6', 0, |
| /* 1874 */ 'x', '1', '6', 0, |
| /* 1878 */ 'z', '1', '6', 0, |
| /* 1882 */ 'D', '2', '3', '_', 'D', '2', '4', '_', 'D', '2', '5', '_', 'D', '2', '6', 0, |
| /* 1898 */ 'Q', '2', '3', '_', 'Q', '2', '4', '_', 'Q', '2', '5', '_', 'Q', '2', '6', 0, |
| /* 1914 */ 'W', '2', '5', '_', 'W', '2', '6', 0, |
| /* 1922 */ 'X', '2', '5', '_', 'X', '2', '6', 0, |
| /* 1930 */ 'Z', '2', '3', '_', 'Z', '2', '4', '_', 'Z', '2', '5', '_', 'Z', '2', '6', 0, |
| /* 1946 */ 'b', '2', '6', 0, |
| /* 1950 */ 'd', '2', '6', 0, |
| /* 1954 */ 'h', '2', '6', 0, |
| /* 1958 */ 'q', '2', '6', 0, |
| /* 1962 */ 's', '2', '6', 0, |
| /* 1966 */ 'w', '2', '6', 0, |
| /* 1970 */ 'x', '2', '6', 0, |
| /* 1974 */ 'z', '2', '6', 0, |
| /* 1978 */ 'D', '3', '_', 'D', '4', '_', 'D', '5', '_', 'D', '6', 0, |
| /* 1990 */ 'Q', '3', '_', 'Q', '4', '_', 'Q', '5', '_', 'Q', '6', 0, |
| /* 2002 */ 'W', '5', '_', 'W', '6', 0, |
| /* 2008 */ 'X', '5', '_', 'X', '6', 0, |
| /* 2014 */ 'Z', '3', '_', 'Z', '4', '_', 'Z', '5', '_', 'Z', '6', 0, |
| /* 2026 */ 'b', '6', 0, |
| /* 2029 */ 'd', '6', 0, |
| /* 2032 */ 'h', '6', 0, |
| /* 2035 */ 'p', '6', 0, |
| /* 2038 */ 'q', '6', 0, |
| /* 2041 */ 's', '6', 0, |
| /* 2044 */ 'w', '6', 0, |
| /* 2047 */ 'x', '6', 0, |
| /* 2050 */ 'z', '6', 0, |
| /* 2053 */ 'D', '1', '4', '_', 'D', '1', '5', '_', 'D', '1', '6', '_', 'D', '1', '7', 0, |
| /* 2069 */ 'Q', '1', '4', '_', 'Q', '1', '5', '_', 'Q', '1', '6', '_', 'Q', '1', '7', 0, |
| /* 2085 */ 'W', '1', '6', '_', 'W', '1', '7', 0, |
| /* 2093 */ 'X', '1', '6', '_', 'X', '1', '7', 0, |
| /* 2101 */ 'Z', '1', '4', '_', 'Z', '1', '5', '_', 'Z', '1', '6', '_', 'Z', '1', '7', 0, |
| /* 2117 */ 'b', '1', '7', 0, |
| /* 2121 */ 'd', '1', '7', 0, |
| /* 2125 */ 'h', '1', '7', 0, |
| /* 2129 */ 'q', '1', '7', 0, |
| /* 2133 */ 's', '1', '7', 0, |
| /* 2137 */ 'w', '1', '7', 0, |
| /* 2141 */ 'x', '1', '7', 0, |
| /* 2145 */ 'z', '1', '7', 0, |
| /* 2149 */ 'D', '2', '4', '_', 'D', '2', '5', '_', 'D', '2', '6', '_', 'D', '2', '7', 0, |
| /* 2165 */ 'Q', '2', '4', '_', 'Q', '2', '5', '_', 'Q', '2', '6', '_', 'Q', '2', '7', 0, |
| /* 2181 */ 'W', '2', '6', '_', 'W', '2', '7', 0, |
| /* 2189 */ 'X', '2', '6', '_', 'X', '2', '7', 0, |
| /* 2197 */ 'Z', '2', '4', '_', 'Z', '2', '5', '_', 'Z', '2', '6', '_', 'Z', '2', '7', 0, |
| /* 2213 */ 'b', '2', '7', 0, |
| /* 2217 */ 'd', '2', '7', 0, |
| /* 2221 */ 'h', '2', '7', 0, |
| /* 2225 */ 'q', '2', '7', 0, |
| /* 2229 */ 's', '2', '7', 0, |
| /* 2233 */ 'w', '2', '7', 0, |
| /* 2237 */ 'x', '2', '7', 0, |
| /* 2241 */ 'z', '2', '7', 0, |
| /* 2245 */ 'D', '4', '_', 'D', '5', '_', 'D', '6', '_', 'D', '7', 0, |
| /* 2257 */ 'Q', '4', '_', 'Q', '5', '_', 'Q', '6', '_', 'Q', '7', 0, |
| /* 2269 */ 'W', '6', '_', 'W', '7', 0, |
| /* 2275 */ 'X', '6', '_', 'X', '7', 0, |
| /* 2281 */ 'Z', '4', '_', 'Z', '5', '_', 'Z', '6', '_', 'Z', '7', 0, |
| /* 2293 */ 'b', '7', 0, |
| /* 2296 */ 'd', '7', 0, |
| /* 2299 */ 'h', '7', 0, |
| /* 2302 */ 'p', '7', 0, |
| /* 2305 */ 'q', '7', 0, |
| /* 2308 */ 's', '7', 0, |
| /* 2311 */ 'w', '7', 0, |
| /* 2314 */ 'x', '7', 0, |
| /* 2317 */ 'z', '7', 0, |
| /* 2320 */ 'D', '1', '5', '_', 'D', '1', '6', '_', 'D', '1', '7', '_', 'D', '1', '8', 0, |
| /* 2336 */ 'Q', '1', '5', '_', 'Q', '1', '6', '_', 'Q', '1', '7', '_', 'Q', '1', '8', 0, |
| /* 2352 */ 'W', '1', '7', '_', 'W', '1', '8', 0, |
| /* 2360 */ 'X', '1', '7', '_', 'X', '1', '8', 0, |
| /* 2368 */ 'Z', '1', '5', '_', 'Z', '1', '6', '_', 'Z', '1', '7', '_', 'Z', '1', '8', 0, |
| /* 2384 */ 'b', '1', '8', 0, |
| /* 2388 */ 'd', '1', '8', 0, |
| /* 2392 */ 'h', '1', '8', 0, |
| /* 2396 */ 'q', '1', '8', 0, |
| /* 2400 */ 's', '1', '8', 0, |
| /* 2404 */ 'w', '1', '8', 0, |
| /* 2408 */ 'x', '1', '8', 0, |
| /* 2412 */ 'z', '1', '8', 0, |
| /* 2416 */ 'D', '2', '5', '_', 'D', '2', '6', '_', 'D', '2', '7', '_', 'D', '2', '8', 0, |
| /* 2432 */ 'Q', '2', '5', '_', 'Q', '2', '6', '_', 'Q', '2', '7', '_', 'Q', '2', '8', 0, |
| /* 2448 */ 'W', '2', '7', '_', 'W', '2', '8', 0, |
| /* 2456 */ 'X', '2', '7', '_', 'X', '2', '8', 0, |
| /* 2464 */ 'Z', '2', '5', '_', 'Z', '2', '6', '_', 'Z', '2', '7', '_', 'Z', '2', '8', 0, |
| /* 2480 */ 'b', '2', '8', 0, |
| /* 2484 */ 'd', '2', '8', 0, |
| /* 2488 */ 'h', '2', '8', 0, |
| /* 2492 */ 'q', '2', '8', 0, |
| /* 2496 */ 's', '2', '8', 0, |
| /* 2500 */ 'w', '2', '8', 0, |
| /* 2504 */ 'x', '2', '8', 0, |
| /* 2508 */ 'z', '2', '8', 0, |
| /* 2512 */ 'D', '5', '_', 'D', '6', '_', 'D', '7', '_', 'D', '8', 0, |
| /* 2524 */ 'Q', '5', '_', 'Q', '6', '_', 'Q', '7', '_', 'Q', '8', 0, |
| /* 2536 */ 'W', '7', '_', 'W', '8', 0, |
| /* 2542 */ 'X', '7', '_', 'X', '8', 0, |
| /* 2548 */ 'Z', '5', '_', 'Z', '6', '_', 'Z', '7', '_', 'Z', '8', 0, |
| /* 2560 */ 'b', '8', 0, |
| /* 2563 */ 'd', '8', 0, |
| /* 2566 */ 'h', '8', 0, |
| /* 2569 */ 'p', '8', 0, |
| /* 2572 */ 'q', '8', 0, |
| /* 2575 */ 's', '8', 0, |
| /* 2578 */ 'w', '8', 0, |
| /* 2581 */ 'x', '8', 0, |
| /* 2584 */ 'z', '8', 0, |
| /* 2587 */ 'D', '1', '6', '_', 'D', '1', '7', '_', 'D', '1', '8', '_', 'D', '1', '9', 0, |
| /* 2603 */ 'Q', '1', '6', '_', 'Q', '1', '7', '_', 'Q', '1', '8', '_', 'Q', '1', '9', 0, |
| /* 2619 */ 'W', '1', '8', '_', 'W', '1', '9', 0, |
| /* 2627 */ 'X', '1', '8', '_', 'X', '1', '9', 0, |
| /* 2635 */ 'Z', '1', '6', '_', 'Z', '1', '7', '_', 'Z', '1', '8', '_', 'Z', '1', '9', 0, |
| /* 2651 */ 'b', '1', '9', 0, |
| /* 2655 */ 'd', '1', '9', 0, |
| /* 2659 */ 'h', '1', '9', 0, |
| /* 2663 */ 'q', '1', '9', 0, |
| /* 2667 */ 's', '1', '9', 0, |
| /* 2671 */ 'w', '1', '9', 0, |
| /* 2675 */ 'x', '1', '9', 0, |
| /* 2679 */ 'z', '1', '9', 0, |
| /* 2683 */ 'D', '2', '6', '_', 'D', '2', '7', '_', 'D', '2', '8', '_', 'D', '2', '9', 0, |
| /* 2699 */ 'Q', '2', '6', '_', 'Q', '2', '7', '_', 'Q', '2', '8', '_', 'Q', '2', '9', 0, |
| /* 2715 */ 'W', '2', '8', '_', 'W', '2', '9', 0, |
| /* 2723 */ 'Z', '2', '6', '_', 'Z', '2', '7', '_', 'Z', '2', '8', '_', 'Z', '2', '9', 0, |
| /* 2739 */ 'b', '2', '9', 0, |
| /* 2743 */ 'd', '2', '9', 0, |
| /* 2747 */ 'h', '2', '9', 0, |
| /* 2751 */ 'q', '2', '9', 0, |
| /* 2755 */ 's', '2', '9', 0, |
| /* 2759 */ 'w', '2', '9', 0, |
| /* 2763 */ 'x', '2', '9', 0, |
| /* 2767 */ 'z', '2', '9', 0, |
| /* 2771 */ 'D', '6', '_', 'D', '7', '_', 'D', '8', '_', 'D', '9', 0, |
| /* 2783 */ 'Q', '6', '_', 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', 0, |
| /* 2795 */ 'W', '8', '_', 'W', '9', 0, |
| /* 2801 */ 'X', '8', '_', 'X', '9', 0, |
| /* 2807 */ 'Z', '6', '_', 'Z', '7', '_', 'Z', '8', '_', 'Z', '9', 0, |
| /* 2819 */ 'b', '9', 0, |
| /* 2822 */ 'd', '9', 0, |
| /* 2825 */ 'h', '9', 0, |
| /* 2828 */ 'p', '9', 0, |
| /* 2831 */ 'q', '9', 0, |
| /* 2834 */ 's', '9', 0, |
| /* 2837 */ 'w', '9', 0, |
| /* 2840 */ 'x', '9', 0, |
| /* 2843 */ 'z', '9', 0, |
| /* 2846 */ 'X', '2', '8', '_', 'F', 'P', 0, |
| /* 2853 */ 'F', 'P', '_', 'L', 'R', 0, |
| /* 2859 */ 'W', '3', '0', '_', 'W', 'Z', 'R', 0, |
| /* 2867 */ 'L', 'R', '_', 'X', 'Z', 'R', 0, |
| /* 2874 */ 'z', '1', '0', '_', 'h', 'i', 0, |
| /* 2881 */ 'z', '2', '0', '_', 'h', 'i', 0, |
| /* 2888 */ 'z', '3', '0', '_', 'h', 'i', 0, |
| /* 2895 */ 'z', '0', '_', 'h', 'i', 0, |
| /* 2901 */ 'z', '1', '1', '_', 'h', 'i', 0, |
| /* 2908 */ 'z', '2', '1', '_', 'h', 'i', 0, |
| /* 2915 */ 'z', '3', '1', '_', 'h', 'i', 0, |
| /* 2922 */ 'z', '1', '_', 'h', 'i', 0, |
| /* 2928 */ 'z', '1', '2', '_', 'h', 'i', 0, |
| /* 2935 */ 'z', '2', '2', '_', 'h', 'i', 0, |
| /* 2942 */ 'z', '2', '_', 'h', 'i', 0, |
| /* 2948 */ 'z', '1', '3', '_', 'h', 'i', 0, |
| /* 2955 */ 'z', '2', '3', '_', 'h', 'i', 0, |
| /* 2962 */ 'z', '3', '_', 'h', 'i', 0, |
| /* 2968 */ 'z', '1', '4', '_', 'h', 'i', 0, |
| /* 2975 */ 'z', '2', '4', '_', 'h', 'i', 0, |
| /* 2982 */ 'z', '4', '_', 'h', 'i', 0, |
| /* 2988 */ 'z', '1', '5', '_', 'h', 'i', 0, |
| /* 2995 */ 'z', '2', '5', '_', 'h', 'i', 0, |
| /* 3002 */ 'z', '5', '_', 'h', 'i', 0, |
| /* 3008 */ 'z', '1', '6', '_', 'h', 'i', 0, |
| /* 3015 */ 'z', '2', '6', '_', 'h', 'i', 0, |
| /* 3022 */ 'z', '6', '_', 'h', 'i', 0, |
| /* 3028 */ 'z', '1', '7', '_', 'h', 'i', 0, |
| /* 3035 */ 'z', '2', '7', '_', 'h', 'i', 0, |
| /* 3042 */ 'z', '7', '_', 'h', 'i', 0, |
| /* 3048 */ 'z', '1', '8', '_', 'h', 'i', 0, |
| /* 3055 */ 'z', '2', '8', '_', 'h', 'i', 0, |
| /* 3062 */ 'z', '8', '_', 'h', 'i', 0, |
| /* 3068 */ 'z', '1', '9', '_', 'h', 'i', 0, |
| /* 3075 */ 'z', '2', '9', '_', 'h', 'i', 0, |
| /* 3082 */ 'z', '9', '_', 'h', 'i', 0, |
| /* 3088 */ 'w', 's', 'p', 0, |
| /* 3092 */ 'f', 'f', 'r', 0, |
| /* 3096 */ 'w', 'z', 'r', 0, |
| /* 3100 */ 'x', 'z', 'r', 0, |
| /* 3104 */ 'n', 'z', 'c', 'v', 0, |
| }; |
| |
| static const uint16_t RegAsmOffsetNoRegAltName[] = { |
| 3092, 2763, 265, 3104, 3089, 3088, 3096, 3100, 332, 675, 946, 1217, 1488, 1759, |
| 2026, 2293, 2560, 2819, 53, 417, 763, 1037, 1308, 1579, 1850, 2117, 2384, 2651, |
| 153, 517, 863, 1137, 1408, 1679, 1946, 2213, 2480, 2739, 241, 597, 335, 678, |
| 949, 1220, 1491, 1762, 2029, 2296, 2563, 2822, 57, 421, 767, 1041, 1312, 1583, |
| 1854, 2121, 2388, 2655, 157, 521, 867, 1141, 1412, 1683, 1950, 2217, 2484, 2743, |
| 245, 601, 338, 681, 952, 1223, 1494, 1765, 2032, 2299, 2566, 2825, 61, 425, |
| 771, 1045, 1316, 1587, 1858, 2125, 2392, 2659, 161, 525, 871, 1145, 1416, 1687, |
| 1954, 2221, 2488, 2747, 249, 605, 341, 684, 955, 1226, 1497, 1768, 2035, 2302, |
| 2569, 2828, 65, 429, 775, 1049, 1320, 1591, 344, 687, 958, 1229, 1500, 1771, |
| 2038, 2305, 2572, 2831, 69, 433, 779, 1053, 1324, 1595, 1862, 2129, 2396, 2663, |
| 165, 529, 875, 1149, 1420, 1691, 1958, 2225, 2492, 2751, 253, 609, 347, 690, |
| 961, 1232, 1503, 1774, 2041, 2308, 2575, 2834, 73, 437, 783, 1057, 1328, 1599, |
| 1866, 2133, 2400, 2667, 169, 533, 879, 1153, 1424, 1695, 1962, 2229, 2496, 2755, |
| 257, 613, 350, 693, 964, 1235, 1506, 1777, 2044, 2311, 2578, 2837, 77, 441, |
| 787, 1061, 1332, 1603, 1870, 2137, 2404, 2671, 173, 537, 883, 1157, 1428, 1699, |
| 1966, 2233, 2500, 2759, 261, 353, 696, 967, 1238, 1509, 1780, 2047, 2314, 2581, |
| 2840, 81, 445, 791, 1065, 1336, 1607, 1874, 2141, 2408, 2675, 177, 541, 887, |
| 1161, 1432, 1703, 1970, 2237, 2504, 356, 699, 970, 1241, 1512, 1783, 2050, 2317, |
| 2584, 2843, 85, 449, 795, 1069, 1340, 1611, 1878, 2145, 2412, 2679, 181, 545, |
| 891, 1165, 1436, 1707, 1974, 2241, 2508, 2767, 269, 617, 2895, 2922, 2942, 2962, |
| 2982, 3002, 3022, 3042, 3062, 3082, 2874, 2901, 2928, 2948, 2968, 2988, 3008, 3028, |
| 3048, 3068, 2881, 2908, 2935, 2955, 2975, 2995, 3015, 3035, 3055, 3075, 2888, 2915, |
| 629, 902, 1175, 1446, 1717, 1984, 2251, 2518, 2777, 6, 365, 709, 981, 1252, |
| 1523, 1794, 2061, 2328, 2595, 97, 461, 807, 1081, 1352, 1623, 1890, 2157, 2424, |
| 2691, 193, 557, 281, 1169, 1440, 1711, 1978, 2245, 2512, 2771, 0, 359, 702, |
| 973, 1244, 1515, 1786, 2053, 2320, 2587, 89, 453, 799, 1073, 1344, 1615, 1882, |
| 2149, 2416, 2683, 185, 549, 273, 621, 895, 899, 1172, 1443, 1714, 1981, 2248, |
| 2515, 2774, 3, 362, 705, 977, 1248, 1519, 1790, 2057, 2324, 2591, 93, 457, |
| 803, 1077, 1348, 1619, 1886, 2153, 2420, 2687, 189, 553, 277, 625, 643, 915, |
| 1187, 1458, 1729, 1996, 2263, 2530, 2789, 19, 379, 724, 997, 1268, 1539, 1810, |
| 2077, 2344, 2611, 113, 477, 823, 1097, 1368, 1639, 1906, 2173, 2440, 2707, 209, |
| 573, 296, 1181, 1452, 1723, 1990, 2257, 2524, 2783, 13, 373, 717, 989, 1260, |
| 1531, 1802, 2069, 2336, 2603, 105, 469, 815, 1089, 1360, 1631, 1898, 2165, 2432, |
| 2699, 201, 565, 288, 635, 908, 912, 1184, 1455, 1726, 1993, 2260, 2527, 2786, |
| 16, 376, 720, 993, 1264, 1535, 1806, 2073, 2340, 2607, 109, 473, 819, 1093, |
| 1364, 1635, 1902, 2169, 2436, 2703, 205, 569, 292, 639, 303, 2859, 649, 921, |
| 1193, 1464, 1735, 2002, 2269, 2536, 2795, 26, 387, 732, 1005, 1276, 1547, 1818, |
| 2085, 2352, 2619, 121, 485, 831, 1105, 1376, 1647, 1914, 2181, 2448, 2715, 217, |
| 2853, 2867, 310, 2846, 655, 927, 1199, 1470, 1741, 2008, 2275, 2542, 2801, 33, |
| 395, 740, 1013, 1284, 1555, 1826, 2093, 2360, 2627, 129, 493, 839, 1113, 1384, |
| 1655, 1922, 2189, 2456, 669, 940, 1211, 1482, 1753, 2020, 2287, 2554, 2813, 46, |
| 409, 755, 1029, 1300, 1571, 1842, 2109, 2376, 2643, 145, 509, 855, 1129, 1400, |
| 1671, 1938, 2205, 2472, 2731, 233, 589, 325, 1205, 1476, 1747, 2014, 2281, 2548, |
| 2807, 40, 403, 748, 1021, 1292, 1563, 1834, 2101, 2368, 2635, 137, 501, 847, |
| 1121, 1392, 1663, 1930, 2197, 2464, 2723, 225, 581, 317, 661, 933, 937, 1208, |
| 1479, 1750, 2017, 2284, 2551, 2810, 43, 406, 751, 1025, 1296, 1567, 1838, 2105, |
| 2372, 2639, 141, 505, 851, 1125, 1396, 1667, 1934, 2201, 2468, 2727, 229, 585, |
| 321, 665, |
| }; |
| |
| static const char AsmStrsvlist1[] = { |
| /* 0 */ 0, |
| }; |
| |
| static const uint8_t RegAsmOffsetvlist1[] = { |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
| 0, 0, |
| }; |
| |
| static const char AsmStrsvreg[] = { |
| /* 0 */ 'v', '1', '0', 0, |
| /* 4 */ 'v', '2', '0', 0, |
| /* 8 */ 'v', '3', '0', 0, |
| /* 12 */ 'v', '0', 0, |
| /* 15 */ 'v', '1', '1', 0, |
| /* 19 */ 'v', '2', '1', 0, |
| /* 23 */ 'v', '3', '1', 0, |
| /* 27 */ 'v', '1', 0, |
| /* 30 */ 'v', '1', '2', 0, |
| /* 34 */ 'v', '2', '2', 0, |
| /* 38 */ 'v', '2', 0, |
| /* 41 */ 'v', '1', '3', 0, |
| /* 45 */ 'v', '2', '3', 0, |
| /* 49 */ 'v', '3', 0, |
| /* 52 */ 'v', '1', '4', 0, |
| /* 56 */ 'v', '2', '4', 0, |
| /* 60 */ 'v', '4', 0, |
| /* 63 */ 'v', '1', '5', 0, |
| /* 67 */ 'v', '2', '5', 0, |
| /* 71 */ 'v', '5', 0, |
| /* 74 */ 'v', '1', '6', 0, |
| /* 78 */ 'v', '2', '6', 0, |
| /* 82 */ 'v', '6', 0, |
| /* 85 */ 'v', '1', '7', 0, |
| /* 89 */ 'v', '2', '7', 0, |
| /* 93 */ 'v', '7', 0, |
| /* 96 */ 'v', '1', '8', 0, |
| /* 100 */ 'v', '2', '8', 0, |
| /* 104 */ 'v', '8', 0, |
| /* 107 */ 'v', '1', '9', 0, |
| /* 111 */ 'v', '2', '9', 0, |
| /* 115 */ 'v', '9', 0, |
| }; |
| |
| static const uint8_t RegAsmOffsetvreg[] = { |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 12, 27, |
| 38, 49, 60, 71, 82, 93, 104, 115, 0, 15, 30, 41, 52, 63, |
| 74, 85, 96, 107, 4, 19, 34, 45, 56, 67, 78, 89, 100, 111, |
| 8, 23, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 12, 27, 38, 49, 60, 71, |
| 82, 93, 104, 115, 0, 15, 30, 41, 52, 63, 74, 85, 96, 107, |
| 4, 19, 34, 45, 56, 67, 78, 89, 100, 111, 8, 23, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 12, 27, 38, 49, 60, 71, 82, 93, 104, 115, 0, 15, 30, 41, |
| 52, 63, 74, 85, 96, 107, 4, 19, 34, 45, 56, 67, 78, 89, |
| 100, 111, 8, 23, 12, 27, 38, 49, 60, 71, 82, 93, 104, 115, |
| 0, 15, 30, 41, 52, 63, 74, 85, 96, 107, 4, 19, 34, 45, |
| 56, 67, 78, 89, 100, 111, 8, 23, 12, 27, 38, 49, 60, 71, |
| 82, 93, 104, 115, 0, 15, 30, 41, 52, 63, 74, 85, 96, 107, |
| 4, 19, 34, 45, 56, 67, 78, 89, 100, 111, 8, 23, 12, 27, |
| 38, 49, 60, 71, 82, 93, 104, 115, 0, 15, 30, 41, 52, 63, |
| 74, 85, 96, 107, 4, 19, 34, 45, 56, 67, 78, 89, 100, 111, |
| 8, 23, 12, 27, 38, 49, 60, 71, 82, 93, 104, 115, 0, 15, |
| 30, 41, 52, 63, 74, 85, 96, 107, 4, 19, 34, 45, 56, 67, |
| 78, 89, 100, 111, 8, 23, 12, 27, 38, 49, 60, 71, 82, 93, |
| 104, 115, 0, 15, 30, 41, 52, 63, 74, 85, 96, 107, 4, 19, |
| 34, 45, 56, 67, 78, 89, 100, 111, 8, 23, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, |
| 3, 3, |
| }; |
| |
| switch(AltIdx) { |
| default: llvm_unreachable("Invalid register alt name index!"); |
| case AArch64::NoRegAltName: |
| assert(*(AsmStrsNoRegAltName+RegAsmOffsetNoRegAltName[RegNo-1]) && |
| "Invalid alt name index for register!"); |
| return AsmStrsNoRegAltName+RegAsmOffsetNoRegAltName[RegNo-1]; |
| case AArch64::vlist1: |
| assert(*(AsmStrsvlist1+RegAsmOffsetvlist1[RegNo-1]) && |
| "Invalid alt name index for register!"); |
| return AsmStrsvlist1+RegAsmOffsetvlist1[RegNo-1]; |
| case AArch64::vreg: |
| assert(*(AsmStrsvreg+RegAsmOffsetvreg[RegNo-1]) && |
| "Invalid alt name index for register!"); |
| return AsmStrsvreg+RegAsmOffsetvreg[RegNo-1]; |
| } |
| } |
| |
| #ifdef PRINT_ALIAS_INSTR |
| #undef PRINT_ALIAS_INSTR |
| |
| static bool AArch64AppleInstPrinterValidateMCOperand(const MCOperand &MCOp, |
| const MCSubtargetInfo &STI, |
| unsigned PredicateIndex); |
| bool AArch64AppleInstPrinter::printAliasInstr(const MCInst *MI, const MCSubtargetInfo &STI, raw_ostream &OS) { |
| const char *AsmString; |
| switch (MI->getOpcode()) { |
| default: return false; |
| case AArch64::ADDSWri: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32spRegClassID).contains(MI->getOperand(1).getReg())) { |
| // (ADDSWri WZR, GPR32sp:$src, addsub_shifted_imm32:$imm) |
| AsmString = "cmn $\x02, $\xFF\x03\x01"; |
| break; |
| } |
| return false; |
| case AArch64::ADDSWrs: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (ADDSWrs WZR, GPR32:$src1, GPR32:$src2, 0) |
| AsmString = "cmn $\x02, $\x03"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg())) { |
| // (ADDSWrs WZR, GPR32:$src1, GPR32:$src2, arith_shift32:$sh) |
| AsmString = "cmn $\x02, $\x03$\xFF\x04\x02"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (ADDSWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) |
| AsmString = "adds $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64::ADDSWrx: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32sponlyRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 16) { |
| // (ADDSWrx WZR, GPR32sponly:$src1, GPR32:$src2, 16) |
| AsmString = "cmn $\x02, $\x03"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg())) { |
| // (ADDSWrx WZR, GPR32sp:$src1, GPR32:$src2, arith_extend:$sh) |
| AsmString = "cmn $\x02, $\x03$\xFF\x04\x03"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32sponlyRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 16) { |
| // (ADDSWrx GPR32:$dst, GPR32sponly:$src1, GPR32:$src2, 16) |
| AsmString = "adds $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64::ADDSXri: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).getReg() == AArch64::XZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg())) { |
| // (ADDSXri XZR, GPR64sp:$src, addsub_shifted_imm64:$imm) |
| AsmString = "cmn $\x02, $\xFF\x03\x01"; |
| break; |
| } |
| return false; |
| case AArch64::ADDSXrs: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).getReg() == AArch64::XZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (ADDSXrs XZR, GPR64:$src1, GPR64:$src2, 0) |
| AsmString = "cmn $\x02, $\x03"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).getReg() == AArch64::XZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg())) { |
| // (ADDSXrs XZR, GPR64:$src1, GPR64:$src2, arith_shift64:$sh) |
| AsmString = "cmn $\x02, $\x03$\xFF\x04\x02"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (ADDSXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) |
| AsmString = "adds $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64::ADDSXrx: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).getReg() == AArch64::XZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg())) { |
| // (ADDSXrx XZR, GPR64sp:$src1, GPR32:$src2, arith_extend:$sh) |
| AsmString = "cmn $\x02, $\x03$\xFF\x04\x03"; |
| break; |
| } |
| return false; |
| case AArch64::ADDSXrx64: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).getReg() == AArch64::XZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64sponlyRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 24) { |
| // (ADDSXrx64 XZR, GPR64sponly:$src1, GPR64:$src2, 24) |
| AsmString = "cmn $\x02, $\x03"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).getReg() == AArch64::XZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg())) { |
| // (ADDSXrx64 XZR, GPR64sp:$src1, GPR64:$src2, arith_extendlsl64:$sh) |
| AsmString = "cmn $\x02, $\x03$\xFF\x04\x03"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64sponlyRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 24) { |
| // (ADDSXrx64 GPR64:$dst, GPR64sponly:$src1, GPR64:$src2, 24) |
| AsmString = "adds $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64::ADDWri: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32sponlyRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (ADDWri GPR32sponly:$dst, GPR32sp:$src, 0, 0) |
| AsmString = "mov $\x01, $\x02"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32sponlyRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (ADDWri GPR32sp:$dst, GPR32sponly:$src, 0, 0) |
| AsmString = "mov $\x01, $\x02"; |
| break; |
| } |
| return false; |
| case AArch64::ADDWrs: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (ADDWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) |
| AsmString = "add $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64::ADDWrx: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32sponlyRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 16) { |
| // (ADDWrx GPR32sponly:$dst, GPR32sp:$src1, GPR32:$src2, 16) |
| AsmString = "add $\x01, $\x02, $\x03"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32sponlyRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 16) { |
| // (ADDWrx GPR32sp:$dst, GPR32sponly:$src1, GPR32:$src2, 16) |
| AsmString = "add $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64::ADDXri: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64sponlyRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (ADDXri GPR64sponly:$dst, GPR64sp:$src, 0, 0) |
| AsmString = "mov $\x01, $\x02"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64sponlyRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (ADDXri GPR64sp:$dst, GPR64sponly:$src, 0, 0) |
| AsmString = "mov $\x01, $\x02"; |
| break; |
| } |
| return false; |
| case AArch64::ADDXrs: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (ADDXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) |
| AsmString = "add $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64::ADDXrx64: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64sponlyRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 24) { |
| // (ADDXrx64 GPR64sponly:$dst, GPR64sp:$src1, GPR64:$src2, 24) |
| AsmString = "add $\x01, $\x02, $\x03"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64sponlyRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 24) { |
| // (ADDXrx64 GPR64sp:$dst, GPR64sponly:$src1, GPR64:$src2, 24) |
| AsmString = "add $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64::ANDSWri: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg())) { |
| // (ANDSWri WZR, GPR32:$src1, logical_imm32:$src2) |
| AsmString = "tst $\x02, $\xFF\x03\x04"; |
| break; |
| } |
| return false; |
| case AArch64::ANDSWrs: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, 0) |
| AsmString = "tst $\x02, $\x03"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg())) { |
| // (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, logical_shift32:$sh) |
| AsmString = "tst $\x02, $\x03$\xFF\x04\x02"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (ANDSWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) |
| AsmString = "ands $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64::ANDSXri: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::XZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg())) { |
| // (ANDSXri XZR, GPR64:$src1, logical_imm64:$src2) |
| AsmString = "tst $\x02, $\xFF\x03\x05"; |
| break; |
| } |
| return false; |
| case AArch64::ANDSXrs: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).getReg() == AArch64::XZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, 0) |
| AsmString = "tst $\x02, $\x03"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).getReg() == AArch64::XZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg())) { |
| // (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, logical_shift64:$sh) |
| AsmString = "tst $\x02, $\x03$\xFF\x04\x02"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (ANDSXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) |
| AsmString = "ands $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64::ANDS_PPzPP: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::PPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPRRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::PPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isReg() && |
| MI->getOperand(3).getReg() == MI->getOperand(2).getReg() && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (ANDS_PPzPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPR8:$Pn) |
| AsmString = "movs $\xFF\x01\x06, $\xFF\x02\x07/z, $\xFF\x03\x06"; |
| break; |
| } |
| return false; |
| case AArch64::ANDWrs: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (ANDWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) |
| AsmString = "and $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64::ANDXrs: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (ANDXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) |
| AsmString = "and $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64::AND_PPzPP: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::PPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPRRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::PPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isReg() && |
| MI->getOperand(3).getReg() == MI->getOperand(2).getReg() && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (AND_PPzPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPR8:$Pn) |
| AsmString = "mov $\xFF\x01\x06, $\xFF\x02\x07/z, $\xFF\x03\x06"; |
| break; |
| } |
| return false; |
| case AArch64::AND_ZI: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| AArch64AppleInstPrinterValidateMCOperand(MI->getOperand(2), STI, 1) && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (AND_ZI ZPR8:$Zdn, sve_logical_imm8:$imm) |
| AsmString = "and $\xFF\x01\x06, $\xFF\x01\x06, $\xFF\x03\x08"; |
| break; |
| } |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| AArch64AppleInstPrinterValidateMCOperand(MI->getOperand(2), STI, 2) && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (AND_ZI ZPR16:$Zdn, sve_logical_imm16:$imm) |
| AsmString = "and $\xFF\x01\x09, $\xFF\x01\x09, $\xFF\x03\x0A"; |
| break; |
| } |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| AArch64AppleInstPrinterValidateMCOperand(MI->getOperand(2), STI, 3) && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (AND_ZI ZPR32:$Zdn, sve_logical_imm32:$imm) |
| AsmString = "and $\xFF\x01\x0B, $\xFF\x01\x0B, $\xFF\x03\x04"; |
| break; |
| } |
| return false; |
| case AArch64::BICSWrs: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (BICSWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) |
| AsmString = "bics $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64::BICSXrs: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (BICSXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) |
| AsmString = "bics $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64::BICWrs: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (BICWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) |
| AsmString = "bic $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64::BICXrs: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (BICXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) |
| AsmString = "bic $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64::CLREX: |
| if (MI->getNumOperands() == 1 && |
| MI->getOperand(0).isImm() && |
| MI->getOperand(0).getImm() == 15) { |
| // (CLREX 15) |
| AsmString = "clrex"; |
| break; |
| } |
| return false; |
| case AArch64::CNTB_XPiI: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isImm() && |
| MI->getOperand(1).getImm() == 31 && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (CNTB_XPiI GPR64:$Rd, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "cntb $\x01"; |
| break; |
| } |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (CNTB_XPiI GPR64:$Rd, sve_pred_enum:$pattern, 1) |
| AsmString = "cntb $\x01, $\xFF\x02\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::CNTD_XPiI: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isImm() && |
| MI->getOperand(1).getImm() == 31 && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (CNTD_XPiI GPR64:$Rd, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "cntd $\x01"; |
| break; |
| } |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (CNTD_XPiI GPR64:$Rd, sve_pred_enum:$pattern, 1) |
| AsmString = "cntd $\x01, $\xFF\x02\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::CNTH_XPiI: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isImm() && |
| MI->getOperand(1).getImm() == 31 && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (CNTH_XPiI GPR64:$Rd, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "cnth $\x01"; |
| break; |
| } |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (CNTH_XPiI GPR64:$Rd, sve_pred_enum:$pattern, 1) |
| AsmString = "cnth $\x01, $\xFF\x02\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::CNTW_XPiI: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isImm() && |
| MI->getOperand(1).getImm() == 31 && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (CNTW_XPiI GPR64:$Rd, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "cntw $\x01"; |
| break; |
| } |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (CNTW_XPiI GPR64:$Rd, sve_pred_enum:$pattern, 1) |
| AsmString = "cntw $\x01, $\xFF\x02\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::CPY_ZPmI_B: |
| if (MI->getNumOperands() == 5 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::PPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (CPY_ZPmI_B ZPR8:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i8:$imm) |
| AsmString = "mov $\xFF\x01\x06, $\xFF\x03\x07/m, $\xFF\x04\x0F"; |
| break; |
| } |
| return false; |
| case AArch64::CPY_ZPmI_D: |
| if (MI->getNumOperands() == 5 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::PPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (CPY_ZPmI_D ZPR64:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i64:$imm) |
| AsmString = "mov $\xFF\x01\x10, $\xFF\x03\x07/m, $\xFF\x04\x11"; |
| break; |
| } |
| return false; |
| case AArch64::CPY_ZPmI_H: |
| if (MI->getNumOperands() == 5 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::PPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (CPY_ZPmI_H ZPR16:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i16:$imm) |
| AsmString = "mov $\xFF\x01\x09, $\xFF\x03\x07/m, $\xFF\x04\x12"; |
| break; |
| } |
| return false; |
| case AArch64::CPY_ZPmI_S: |
| if (MI->getNumOperands() == 5 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::PPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (CPY_ZPmI_S ZPR32:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i32:$imm) |
| AsmString = "mov $\xFF\x01\x0B, $\xFF\x03\x07/m, $\xFF\x04\x13"; |
| break; |
| } |
| return false; |
| case AArch64::CPY_ZPmR_B: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isReg() && |
| MRI.getRegClass(AArch64::GPR32spRegClassID).contains(MI->getOperand(3).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (CPY_ZPmR_B ZPR8:$Zd, PPR3bAny:$Pg, GPR32sp:$Rn) |
| AsmString = "mov $\xFF\x01\x06, $\xFF\x03\x07/m, $\x04"; |
| break; |
| } |
| return false; |
| case AArch64::CPY_ZPmR_D: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(3).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (CPY_ZPmR_D ZPR64:$Zd, PPR3bAny:$Pg, GPR64sp:$Rn) |
| AsmString = "mov $\xFF\x01\x10, $\xFF\x03\x07/m, $\x04"; |
| break; |
| } |
| return false; |
| case AArch64::CPY_ZPmR_H: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isReg() && |
| MRI.getRegClass(AArch64::GPR32spRegClassID).contains(MI->getOperand(3).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (CPY_ZPmR_H ZPR16:$Zd, PPR3bAny:$Pg, GPR32sp:$Rn) |
| AsmString = "mov $\xFF\x01\x09, $\xFF\x03\x07/m, $\x04"; |
| break; |
| } |
| return false; |
| case AArch64::CPY_ZPmR_S: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isReg() && |
| MRI.getRegClass(AArch64::GPR32spRegClassID).contains(MI->getOperand(3).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (CPY_ZPmR_S ZPR32:$Zd, PPR3bAny:$Pg, GPR32sp:$Rn) |
| AsmString = "mov $\xFF\x01\x0B, $\xFF\x03\x07/m, $\x04"; |
| break; |
| } |
| return false; |
| case AArch64::CPY_ZPmV_B: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isReg() && |
| MRI.getRegClass(AArch64::FPR8RegClassID).contains(MI->getOperand(3).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (CPY_ZPmV_B ZPR8:$Zd, PPR3bAny:$Pg, FPR8:$Vn) |
| AsmString = "mov $\xFF\x01\x06, $\xFF\x03\x07/m, $\x04"; |
| break; |
| } |
| return false; |
| case AArch64::CPY_ZPmV_D: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isReg() && |
| MRI.getRegClass(AArch64::FPR64RegClassID).contains(MI->getOperand(3).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (CPY_ZPmV_D ZPR64:$Zd, PPR3bAny:$Pg, FPR64:$Vn) |
| AsmString = "mov $\xFF\x01\x10, $\xFF\x03\x07/m, $\x04"; |
| break; |
| } |
| return false; |
| case AArch64::CPY_ZPmV_H: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isReg() && |
| MRI.getRegClass(AArch64::FPR16RegClassID).contains(MI->getOperand(3).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (CPY_ZPmV_H ZPR16:$Zd, PPR3bAny:$Pg, FPR16:$Vn) |
| AsmString = "mov $\xFF\x01\x09, $\xFF\x03\x07/m, $\x04"; |
| break; |
| } |
| return false; |
| case AArch64::CPY_ZPmV_S: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isReg() && |
| MRI.getRegClass(AArch64::FPR32RegClassID).contains(MI->getOperand(3).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (CPY_ZPmV_S ZPR32:$Zd, PPR3bAny:$Pg, FPR32:$Vn) |
| AsmString = "mov $\xFF\x01\x0B, $\xFF\x03\x07/m, $\x04"; |
| break; |
| } |
| return false; |
| case AArch64::CPY_ZPzI_B: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPRRegClassID).contains(MI->getOperand(1).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (CPY_ZPzI_B ZPR8:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i8:$imm) |
| AsmString = "mov $\xFF\x01\x06, $\xFF\x02\x07/z, $\xFF\x03\x0F"; |
| break; |
| } |
| return false; |
| case AArch64::CPY_ZPzI_D: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPRRegClassID).contains(MI->getOperand(1).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (CPY_ZPzI_D ZPR64:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i64:$imm) |
| AsmString = "mov $\xFF\x01\x10, $\xFF\x02\x07/z, $\xFF\x03\x11"; |
| break; |
| } |
| return false; |
| case AArch64::CPY_ZPzI_H: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPRRegClassID).contains(MI->getOperand(1).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (CPY_ZPzI_H ZPR16:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i16:$imm) |
| AsmString = "mov $\xFF\x01\x09, $\xFF\x02\x07/z, $\xFF\x03\x12"; |
| break; |
| } |
| return false; |
| case AArch64::CPY_ZPzI_S: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPRRegClassID).contains(MI->getOperand(1).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (CPY_ZPzI_S ZPR32:$Zd, PPRAny:$Pg, cpy_imm8_opt_lsl_i32:$imm) |
| AsmString = "mov $\xFF\x01\x0B, $\xFF\x02\x07/z, $\xFF\x03\x13"; |
| break; |
| } |
| return false; |
| case AArch64::CSINCWr: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).getReg() == AArch64::WZR && |
| MI->getOperand(2).getReg() == AArch64::WZR && |
| AArch64AppleInstPrinterValidateMCOperand(MI->getOperand(3), STI, 4)) { |
| // (CSINCWr GPR32:$dst, WZR, WZR, inv_ccode:$cc) |
| AsmString = "cset $\x01, $\xFF\x04\x14"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MI->getOperand(2).getReg() == MI->getOperand(1).getReg() && |
| AArch64AppleInstPrinterValidateMCOperand(MI->getOperand(3), STI, 4)) { |
| // (CSINCWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc) |
| AsmString = "cinc $\x01, $\x02, $\xFF\x04\x14"; |
| break; |
| } |
| return false; |
| case AArch64::CSINCXr: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).getReg() == AArch64::XZR && |
| MI->getOperand(2).getReg() == AArch64::XZR && |
| AArch64AppleInstPrinterValidateMCOperand(MI->getOperand(3), STI, 4)) { |
| // (CSINCXr GPR64:$dst, XZR, XZR, inv_ccode:$cc) |
| AsmString = "cset $\x01, $\xFF\x04\x14"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MI->getOperand(2).getReg() == MI->getOperand(1).getReg() && |
| AArch64AppleInstPrinterValidateMCOperand(MI->getOperand(3), STI, 4)) { |
| // (CSINCXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc) |
| AsmString = "cinc $\x01, $\x02, $\xFF\x04\x14"; |
| break; |
| } |
| return false; |
| case AArch64::CSINVWr: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).getReg() == AArch64::WZR && |
| MI->getOperand(2).getReg() == AArch64::WZR && |
| AArch64AppleInstPrinterValidateMCOperand(MI->getOperand(3), STI, 4)) { |
| // (CSINVWr GPR32:$dst, WZR, WZR, inv_ccode:$cc) |
| AsmString = "csetm $\x01, $\xFF\x04\x14"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MI->getOperand(2).getReg() == MI->getOperand(1).getReg() && |
| AArch64AppleInstPrinterValidateMCOperand(MI->getOperand(3), STI, 4)) { |
| // (CSINVWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc) |
| AsmString = "cinv $\x01, $\x02, $\xFF\x04\x14"; |
| break; |
| } |
| return false; |
| case AArch64::CSINVXr: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).getReg() == AArch64::XZR && |
| MI->getOperand(2).getReg() == AArch64::XZR && |
| AArch64AppleInstPrinterValidateMCOperand(MI->getOperand(3), STI, 4)) { |
| // (CSINVXr GPR64:$dst, XZR, XZR, inv_ccode:$cc) |
| AsmString = "csetm $\x01, $\xFF\x04\x14"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MI->getOperand(2).getReg() == MI->getOperand(1).getReg() && |
| AArch64AppleInstPrinterValidateMCOperand(MI->getOperand(3), STI, 4)) { |
| // (CSINVXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc) |
| AsmString = "cinv $\x01, $\x02, $\xFF\x04\x14"; |
| break; |
| } |
| return false; |
| case AArch64::CSNEGWr: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MI->getOperand(2).getReg() == MI->getOperand(1).getReg() && |
| AArch64AppleInstPrinterValidateMCOperand(MI->getOperand(3), STI, 4)) { |
| // (CSNEGWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc) |
| AsmString = "cneg $\x01, $\x02, $\xFF\x04\x14"; |
| break; |
| } |
| return false; |
| case AArch64::CSNEGXr: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MI->getOperand(2).getReg() == MI->getOperand(1).getReg() && |
| AArch64AppleInstPrinterValidateMCOperand(MI->getOperand(3), STI, 4)) { |
| // (CSNEGXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc) |
| AsmString = "cneg $\x01, $\x02, $\xFF\x04\x14"; |
| break; |
| } |
| return false; |
| case AArch64::DCPS1: |
| if (MI->getNumOperands() == 1 && |
| MI->getOperand(0).isImm() && |
| MI->getOperand(0).getImm() == 0) { |
| // (DCPS1 0) |
| AsmString = "dcps1"; |
| break; |
| } |
| return false; |
| case AArch64::DCPS2: |
| if (MI->getNumOperands() == 1 && |
| MI->getOperand(0).isImm() && |
| MI->getOperand(0).getImm() == 0) { |
| // (DCPS2 0) |
| AsmString = "dcps2"; |
| break; |
| } |
| return false; |
| case AArch64::DCPS3: |
| if (MI->getNumOperands() == 1 && |
| MI->getOperand(0).isImm() && |
| MI->getOperand(0).getImm() == 0) { |
| // (DCPS3 0) |
| AsmString = "dcps3"; |
| break; |
| } |
| return false; |
| case AArch64::DECB_XPiI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (DECB_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "decb $\x01"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (DECB_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) |
| AsmString = "decb $\x01, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::DECD_XPiI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (DECD_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "decd $\x01"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (DECD_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) |
| AsmString = "decd $\x01, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::DECD_ZPiI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (DECD_ZPiI ZPR64:$Zdn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "decd $\xFF\x01\x10"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (DECD_ZPiI ZPR64:$Zdn, sve_pred_enum:$pattern, 1) |
| AsmString = "decd $\xFF\x01\x10, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::DECH_XPiI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (DECH_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "dech $\x01"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (DECH_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) |
| AsmString = "dech $\x01, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::DECH_ZPiI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (DECH_ZPiI ZPR16:$Zdn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "dech $\xFF\x01\x09"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (DECH_ZPiI ZPR16:$Zdn, sve_pred_enum:$pattern, 1) |
| AsmString = "dech $\xFF\x01\x09, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::DECW_XPiI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (DECW_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "decw $\x01"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (DECW_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) |
| AsmString = "decw $\x01, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::DECW_ZPiI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (DECW_ZPiI ZPR32:$Zdn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "decw $\xFF\x01\x0B"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (DECW_ZPiI ZPR32:$Zdn, sve_pred_enum:$pattern, 1) |
| AsmString = "decw $\xFF\x01\x0B, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::DUPM_ZI: |
| if (MI->getNumOperands() == 2 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| AArch64AppleInstPrinterValidateMCOperand(MI->getOperand(1), STI, 5) && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (DUPM_ZI ZPR16:$Zd, sve_preferred_logical_imm16:$imm) |
| AsmString = "mov $\xFF\x01\x09, $\xFF\x02\x15"; |
| break; |
| } |
| if (MI->getNumOperands() == 2 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| AArch64AppleInstPrinterValidateMCOperand(MI->getOperand(1), STI, 6) && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (DUPM_ZI ZPR32:$Zd, sve_preferred_logical_imm32:$imm) |
| AsmString = "mov $\xFF\x01\x0B, $\xFF\x02\x16"; |
| break; |
| } |
| if (MI->getNumOperands() == 2 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| AArch64AppleInstPrinterValidateMCOperand(MI->getOperand(1), STI, 7) && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (DUPM_ZI ZPR64:$Zd, sve_preferred_logical_imm64:$imm) |
| AsmString = "mov $\xFF\x01\x10, $\xFF\x02\x17"; |
| break; |
| } |
| if (MI->getNumOperands() == 2 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| AArch64AppleInstPrinterValidateMCOperand(MI->getOperand(1), STI, 1) && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (DUPM_ZI ZPR8:$Zd, sve_logical_imm8:$imm) |
| AsmString = "dupm $\xFF\x01\x06, $\xFF\x02\x08"; |
| break; |
| } |
| if (MI->getNumOperands() == 2 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| AArch64AppleInstPrinterValidateMCOperand(MI->getOperand(1), STI, 2) && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (DUPM_ZI ZPR16:$Zd, sve_logical_imm16:$imm) |
| AsmString = "dupm $\xFF\x01\x09, $\xFF\x02\x0A"; |
| break; |
| } |
| if (MI->getNumOperands() == 2 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| AArch64AppleInstPrinterValidateMCOperand(MI->getOperand(1), STI, 3) && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (DUPM_ZI ZPR32:$Zd, sve_logical_imm32:$imm) |
| AsmString = "dupm $\xFF\x01\x0B, $\xFF\x02\x04"; |
| break; |
| } |
| return false; |
| case AArch64::DUP_ZI_B: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (DUP_ZI_B ZPR8:$Zd, cpy_imm8_opt_lsl_i8:$imm) |
| AsmString = "mov $\xFF\x01\x06, $\xFF\x02\x0F"; |
| break; |
| } |
| return false; |
| case AArch64::DUP_ZI_D: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (DUP_ZI_D ZPR64:$Zd, cpy_imm8_opt_lsl_i64:$imm) |
| AsmString = "mov $\xFF\x01\x10, $\xFF\x02\x11"; |
| break; |
| } |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isImm() && |
| MI->getOperand(1).getImm() == 0 && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (DUP_ZI_D ZPR64:$Zd, 0, 0) |
| AsmString = "fmov $\xFF\x01\x10, #0.0"; |
| break; |
| } |
| return false; |
| case AArch64::DUP_ZI_H: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (DUP_ZI_H ZPR16:$Zd, cpy_imm8_opt_lsl_i16:$imm) |
| AsmString = "mov $\xFF\x01\x09, $\xFF\x02\x12"; |
| break; |
| } |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isImm() && |
| MI->getOperand(1).getImm() == 0 && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (DUP_ZI_H ZPR16:$Zd, 0, 0) |
| AsmString = "fmov $\xFF\x01\x09, #0.0"; |
| break; |
| } |
| return false; |
| case AArch64::DUP_ZI_S: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (DUP_ZI_S ZPR32:$Zd, cpy_imm8_opt_lsl_i32:$imm) |
| AsmString = "mov $\xFF\x01\x0B, $\xFF\x02\x13"; |
| break; |
| } |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isImm() && |
| MI->getOperand(1).getImm() == 0 && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (DUP_ZI_S ZPR32:$Zd, 0, 0) |
| AsmString = "fmov $\xFF\x01\x0B, #0.0"; |
| break; |
| } |
| return false; |
| case AArch64::DUP_ZR_B: |
| if (MI->getNumOperands() == 2 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32spRegClassID).contains(MI->getOperand(1).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (DUP_ZR_B ZPR8:$Zd, GPR32sp:$Rn) |
| AsmString = "mov $\xFF\x01\x06, $\x02"; |
| break; |
| } |
| return false; |
| case AArch64::DUP_ZR_D: |
| if (MI->getNumOperands() == 2 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (DUP_ZR_D ZPR64:$Zd, GPR64sp:$Rn) |
| AsmString = "mov $\xFF\x01\x10, $\x02"; |
| break; |
| } |
| return false; |
| case AArch64::DUP_ZR_H: |
| if (MI->getNumOperands() == 2 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32spRegClassID).contains(MI->getOperand(1).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (DUP_ZR_H ZPR16:$Zd, GPR32sp:$Rn) |
| AsmString = "mov $\xFF\x01\x09, $\x02"; |
| break; |
| } |
| return false; |
| case AArch64::DUP_ZR_S: |
| if (MI->getNumOperands() == 2 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32spRegClassID).contains(MI->getOperand(1).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (DUP_ZR_S ZPR32:$Zd, GPR32sp:$Rn) |
| AsmString = "mov $\xFF\x01\x0B, $\x02"; |
| break; |
| } |
| return false; |
| case AArch64::DUP_ZZI_B: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (DUP_ZZI_B ZPR8:$Zd, FPR8asZPR:$Bn, 0) |
| AsmString = "mov $\xFF\x01\x06, $\xFF\x02\x18"; |
| break; |
| } |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(1).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (DUP_ZZI_B ZPR8:$Zd, ZPR8:$Zn, sve_elm_idx_extdup_b:$idx) |
| AsmString = "mov $\xFF\x01\x06, $\xFF\x02\x06$\xFF\x03\x19"; |
| break; |
| } |
| return false; |
| case AArch64::DUP_ZZI_D: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (DUP_ZZI_D ZPR64:$Zd, FPR64asZPR:$Dn, 0) |
| AsmString = "mov $\xFF\x01\x10, $\xFF\x02\x1A"; |
| break; |
| } |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(1).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (DUP_ZZI_D ZPR64:$Zd, ZPR64:$Zn, sve_elm_idx_extdup_d:$idx) |
| AsmString = "mov $\xFF\x01\x10, $\xFF\x02\x10$\xFF\x03\x19"; |
| break; |
| } |
| return false; |
| case AArch64::DUP_ZZI_H: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (DUP_ZZI_H ZPR16:$Zd, FPR16asZPR:$Hn, 0) |
| AsmString = "mov $\xFF\x01\x09, $\xFF\x02\x1B"; |
| break; |
| } |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(1).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (DUP_ZZI_H ZPR16:$Zd, ZPR16:$Zn, sve_elm_idx_extdup_h:$idx) |
| AsmString = "mov $\xFF\x01\x09, $\xFF\x02\x09$\xFF\x03\x19"; |
| break; |
| } |
| return false; |
| case AArch64::DUP_ZZI_Q: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (DUP_ZZI_Q ZPR128:$Zd, FPR128asZPR:$Qn, 0) |
| AsmString = "mov $\xFF\x01\x1C, $\xFF\x02\x1D"; |
| break; |
| } |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(1).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (DUP_ZZI_Q ZPR128:$Zd, ZPR128:$Zn, sve_elm_idx_extdup_q:$idx) |
| AsmString = "mov $\xFF\x01\x1C, $\xFF\x02\x1C$\xFF\x03\x19"; |
| break; |
| } |
| return false; |
| case AArch64::DUP_ZZI_S: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (DUP_ZZI_S ZPR32:$Zd, FPR32asZPR:$Sn, 0) |
| AsmString = "mov $\xFF\x01\x0B, $\xFF\x02\x1E"; |
| break; |
| } |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(1).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (DUP_ZZI_S ZPR32:$Zd, ZPR32:$Zn, sve_elm_idx_extdup_s:$idx) |
| AsmString = "mov $\xFF\x01\x0B, $\xFF\x02\x0B$\xFF\x03\x19"; |
| break; |
| } |
| return false; |
| case AArch64::EONWrs: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (EONWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) |
| AsmString = "eon $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64::EONXrs: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (EONXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) |
| AsmString = "eon $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64::EORS_PPzPP: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::PPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPRRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::PPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isReg() && |
| MI->getOperand(3).getReg() == MI->getOperand(1).getReg() && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (EORS_PPzPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPRAny:$Pg) |
| AsmString = "nots $\xFF\x01\x06, $\xFF\x02\x07/z, $\xFF\x03\x06"; |
| break; |
| } |
| return false; |
| case AArch64::EORWrs: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (EORWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) |
| AsmString = "eor $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64::EORXrs: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (EORXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) |
| AsmString = "eor $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64::EOR_PPzPP: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::PPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPRRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::PPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isReg() && |
| MI->getOperand(3).getReg() == MI->getOperand(1).getReg() && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (EOR_PPzPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPRAny:$Pg) |
| AsmString = "not $\xFF\x01\x06, $\xFF\x02\x07/z, $\xFF\x03\x06"; |
| break; |
| } |
| return false; |
| case AArch64::EOR_ZI: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| AArch64AppleInstPrinterValidateMCOperand(MI->getOperand(2), STI, 1) && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (EOR_ZI ZPR8:$Zdn, sve_logical_imm8:$imm) |
| AsmString = "eor $\xFF\x01\x06, $\xFF\x01\x06, $\xFF\x03\x08"; |
| break; |
| } |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| AArch64AppleInstPrinterValidateMCOperand(MI->getOperand(2), STI, 2) && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (EOR_ZI ZPR16:$Zdn, sve_logical_imm16:$imm) |
| AsmString = "eor $\xFF\x01\x09, $\xFF\x01\x09, $\xFF\x03\x0A"; |
| break; |
| } |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| AArch64AppleInstPrinterValidateMCOperand(MI->getOperand(2), STI, 3) && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (EOR_ZI ZPR32:$Zdn, sve_logical_imm32:$imm) |
| AsmString = "eor $\xFF\x01\x0B, $\xFF\x01\x0B, $\xFF\x03\x04"; |
| break; |
| } |
| return false; |
| case AArch64::EXTRWrri: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MI->getOperand(2).getReg() == MI->getOperand(1).getReg()) { |
| // (EXTRWrri GPR32:$dst, GPR32:$src, GPR32:$src, imm0_31:$shift) |
| AsmString = "ror $\x01, $\x02, $\x04"; |
| break; |
| } |
| return false; |
| case AArch64::EXTRXrri: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MI->getOperand(2).getReg() == MI->getOperand(1).getReg()) { |
| // (EXTRXrri GPR64:$dst, GPR64:$src, GPR64:$src, imm0_63:$shift) |
| AsmString = "ror $\x01, $\x02, $\x04"; |
| break; |
| } |
| return false; |
| case AArch64::FCPY_ZPmI_D: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::PPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (FCPY_ZPmI_D ZPR64:$Zd, PPRAny:$Pg, fpimm64:$imm8) |
| AsmString = "fmov $\xFF\x01\x10, $\xFF\x03\x07/m, $\xFF\x04\x1F"; |
| break; |
| } |
| return false; |
| case AArch64::FCPY_ZPmI_H: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::PPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (FCPY_ZPmI_H ZPR16:$Zd, PPRAny:$Pg, fpimm16:$imm8) |
| AsmString = "fmov $\xFF\x01\x09, $\xFF\x03\x07/m, $\xFF\x04\x1F"; |
| break; |
| } |
| return false; |
| case AArch64::FCPY_ZPmI_S: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::PPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (FCPY_ZPmI_S ZPR32:$Zd, PPRAny:$Pg, fpimm32:$imm8) |
| AsmString = "fmov $\xFF\x01\x0B, $\xFF\x03\x07/m, $\xFF\x04\x1F"; |
| break; |
| } |
| return false; |
| case AArch64::FDUP_ZI_D: |
| if (MI->getNumOperands() == 2 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (FDUP_ZI_D ZPR64:$Zd, fpimm64:$imm8) |
| AsmString = "fmov $\xFF\x01\x10, $\xFF\x02\x1F"; |
| break; |
| } |
| return false; |
| case AArch64::FDUP_ZI_H: |
| if (MI->getNumOperands() == 2 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (FDUP_ZI_H ZPR16:$Zd, fpimm16:$imm8) |
| AsmString = "fmov $\xFF\x01\x09, $\xFF\x02\x1F"; |
| break; |
| } |
| return false; |
| case AArch64::FDUP_ZI_S: |
| if (MI->getNumOperands() == 2 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (FDUP_ZI_S ZPR32:$Zd, fpimm32:$imm8) |
| AsmString = "fmov $\xFF\x01\x0B, $\xFF\x02\x1F"; |
| break; |
| } |
| return false; |
| case AArch64::GLD1B_D_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (GLD1B_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) |
| AsmString = "ld1b $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]"; |
| break; |
| } |
| return false; |
| case AArch64::GLD1B_S_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (GLD1B_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) |
| AsmString = "ld1b $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]"; |
| break; |
| } |
| return false; |
| case AArch64::GLD1D_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (GLD1D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) |
| AsmString = "ld1d $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]"; |
| break; |
| } |
| return false; |
| case AArch64::GLD1H_D_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (GLD1H_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) |
| AsmString = "ld1h $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]"; |
| break; |
| } |
| return false; |
| case AArch64::GLD1H_S_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (GLD1H_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) |
| AsmString = "ld1h $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]"; |
| break; |
| } |
| return false; |
| case AArch64::GLD1SB_D_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (GLD1SB_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) |
| AsmString = "ld1sb $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]"; |
| break; |
| } |
| return false; |
| case AArch64::GLD1SB_S_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (GLD1SB_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) |
| AsmString = "ld1sb $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]"; |
| break; |
| } |
| return false; |
| case AArch64::GLD1SH_D_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (GLD1SH_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) |
| AsmString = "ld1sh $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]"; |
| break; |
| } |
| return false; |
| case AArch64::GLD1SH_S_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (GLD1SH_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) |
| AsmString = "ld1sh $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]"; |
| break; |
| } |
| return false; |
| case AArch64::GLD1SW_D_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (GLD1SW_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) |
| AsmString = "ld1sw $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]"; |
| break; |
| } |
| return false; |
| case AArch64::GLD1W_D_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (GLD1W_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) |
| AsmString = "ld1w $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]"; |
| break; |
| } |
| return false; |
| case AArch64::GLD1W_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (GLD1W_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) |
| AsmString = "ld1w $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]"; |
| break; |
| } |
| return false; |
| case AArch64::GLDFF1B_D_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (GLDFF1B_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) |
| AsmString = "ldff1b $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]"; |
| break; |
| } |
| return false; |
| case AArch64::GLDFF1B_S_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (GLDFF1B_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) |
| AsmString = "ldff1b $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]"; |
| break; |
| } |
| return false; |
| case AArch64::GLDFF1D_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (GLDFF1D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) |
| AsmString = "ldff1d $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]"; |
| break; |
| } |
| return false; |
| case AArch64::GLDFF1H_D_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (GLDFF1H_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) |
| AsmString = "ldff1h $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]"; |
| break; |
| } |
| return false; |
| case AArch64::GLDFF1H_S_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (GLDFF1H_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) |
| AsmString = "ldff1h $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]"; |
| break; |
| } |
| return false; |
| case AArch64::GLDFF1SB_D_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (GLDFF1SB_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) |
| AsmString = "ldff1sb $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]"; |
| break; |
| } |
| return false; |
| case AArch64::GLDFF1SB_S_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (GLDFF1SB_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) |
| AsmString = "ldff1sb $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]"; |
| break; |
| } |
| return false; |
| case AArch64::GLDFF1SH_D_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (GLDFF1SH_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) |
| AsmString = "ldff1sh $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]"; |
| break; |
| } |
| return false; |
| case AArch64::GLDFF1SH_S_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (GLDFF1SH_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) |
| AsmString = "ldff1sh $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]"; |
| break; |
| } |
| return false; |
| case AArch64::GLDFF1SW_D_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (GLDFF1SW_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) |
| AsmString = "ldff1sw $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]"; |
| break; |
| } |
| return false; |
| case AArch64::GLDFF1W_D_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (GLDFF1W_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) |
| AsmString = "ldff1w $\xFF\x01\x20, $\xFF\x02\x07/z, [$\xFF\x03\x10]"; |
| break; |
| } |
| return false; |
| case AArch64::GLDFF1W_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (GLDFF1W_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) |
| AsmString = "ldff1w $\xFF\x01\x21, $\xFF\x02\x07/z, [$\xFF\x03\x0B]"; |
| break; |
| } |
| return false; |
| case AArch64::HINT: |
| if (MI->getNumOperands() == 1 && |
| MI->getOperand(0).isImm() && |
| MI->getOperand(0).getImm() == 0) { |
| // (HINT { 0, 0, 0 }) |
| AsmString = "nop"; |
| break; |
| } |
| if (MI->getNumOperands() == 1 && |
| MI->getOperand(0).isImm() && |
| MI->getOperand(0).getImm() == 1) { |
| // (HINT { 0, 0, 1 }) |
| AsmString = "yield"; |
| break; |
| } |
| if (MI->getNumOperands() == 1 && |
| MI->getOperand(0).isImm() && |
| MI->getOperand(0).getImm() == 2) { |
| // (HINT { 0, 1, 0 }) |
| AsmString = "wfe"; |
| break; |
| } |
| if (MI->getNumOperands() == 1 && |
| MI->getOperand(0).isImm() && |
| MI->getOperand(0).getImm() == 3) { |
| // (HINT { 0, 1, 1 }) |
| AsmString = "wfi"; |
| break; |
| } |
| if (MI->getNumOperands() == 1 && |
| MI->getOperand(0).isImm() && |
| MI->getOperand(0).getImm() == 4) { |
| // (HINT { 1, 0, 0 }) |
| AsmString = "sev"; |
| break; |
| } |
| if (MI->getNumOperands() == 1 && |
| MI->getOperand(0).isImm() && |
| MI->getOperand(0).getImm() == 5) { |
| // (HINT { 1, 0, 1 }) |
| AsmString = "sevl"; |
| break; |
| } |
| if (MI->getNumOperands() == 1 && |
| MI->getOperand(0).isImm() && |
| MI->getOperand(0).getImm() == 16 && |
| STI.getFeatureBits()[AArch64::FeatureRAS]) { |
| // (HINT { 1, 0, 0, 0, 0 }) |
| AsmString = "esb"; |
| break; |
| } |
| if (MI->getNumOperands() == 1 && |
| MI->getOperand(0).isImm() && |
| MI->getOperand(0).getImm() == 20) { |
| // (HINT 20) |
| AsmString = "csdb"; |
| break; |
| } |
| if (MI->getNumOperands() == 1 && |
| AArch64AppleInstPrinterValidateMCOperand(MI->getOperand(0), STI, 8) && |
| STI.getFeatureBits()[AArch64::FeatureSPE]) { |
| // (HINT psbhint_op:$op) |
| AsmString = "psb $\xFF\x01\x22"; |
| break; |
| } |
| return false; |
| case AArch64::INCB_XPiI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (INCB_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "incb $\x01"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (INCB_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) |
| AsmString = "incb $\x01, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::INCD_XPiI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (INCD_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "incd $\x01"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (INCD_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) |
| AsmString = "incd $\x01, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::INCD_ZPiI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (INCD_ZPiI ZPR64:$Zdn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "incd $\xFF\x01\x10"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (INCD_ZPiI ZPR64:$Zdn, sve_pred_enum:$pattern, 1) |
| AsmString = "incd $\xFF\x01\x10, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::INCH_XPiI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (INCH_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "inch $\x01"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (INCH_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) |
| AsmString = "inch $\x01, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::INCH_ZPiI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (INCH_ZPiI ZPR16:$Zdn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "inch $\xFF\x01\x09"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (INCH_ZPiI ZPR16:$Zdn, sve_pred_enum:$pattern, 1) |
| AsmString = "inch $\xFF\x01\x09, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::INCW_XPiI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (INCW_XPiI GPR64:$Rdn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "incw $\x01"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (INCW_XPiI GPR64:$Rdn, sve_pred_enum:$pattern, 1) |
| AsmString = "incw $\x01, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::INCW_ZPiI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (INCW_ZPiI ZPR32:$Zdn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "incw $\xFF\x01\x0B"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (INCW_ZPiI ZPR32:$Zdn, sve_pred_enum:$pattern, 1) |
| AsmString = "incw $\xFF\x01\x0B, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::INSvi16gpr: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(3).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (INSvi16gpr V128:$dst, VectorIndexH:$idx, GPR32:$src) |
| AsmString = "mov.h $\xFF\x01\x0C$\xFF\x03\x19, $\x04"; |
| break; |
| } |
| return false; |
| case AArch64::INSvi16lane: |
| if (MI->getNumOperands() == 5 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(3).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (INSvi16lane V128:$dst, VectorIndexH:$idx, V128:$src, VectorIndexH:$idx2) |
| AsmString = "mov.h $\xFF\x01\x0C$\xFF\x03\x19, $\xFF\x04\x0C$\xFF\x05\x19"; |
| break; |
| } |
| return false; |
| case AArch64::INSvi32gpr: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(3).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (INSvi32gpr V128:$dst, VectorIndexS:$idx, GPR32:$src) |
| AsmString = "mov.s $\xFF\x01\x0C$\xFF\x03\x19, $\x04"; |
| break; |
| } |
| return false; |
| case AArch64::INSvi32lane: |
| if (MI->getNumOperands() == 5 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(3).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (INSvi32lane V128:$dst, VectorIndexS:$idx, V128:$src, VectorIndexS:$idx2) |
| AsmString = "mov.s $\xFF\x01\x0C$\xFF\x03\x19, $\xFF\x04\x0C$\xFF\x05\x19"; |
| break; |
| } |
| return false; |
| case AArch64::INSvi64gpr: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(3).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (INSvi64gpr V128:$dst, VectorIndexD:$idx, GPR64:$src) |
| AsmString = "mov.d $\xFF\x01\x0C$\xFF\x03\x19, $\x04"; |
| break; |
| } |
| return false; |
| case AArch64::INSvi64lane: |
| if (MI->getNumOperands() == 5 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(3).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (INSvi64lane V128:$dst, VectorIndexD:$idx, V128:$src, VectorIndexD:$idx2) |
| AsmString = "mov.d $\xFF\x01\x0C$\xFF\x03\x19, $\xFF\x04\x0C$\xFF\x05\x19"; |
| break; |
| } |
| return false; |
| case AArch64::INSvi8gpr: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(3).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (INSvi8gpr V128:$dst, VectorIndexB:$idx, GPR32:$src) |
| AsmString = "mov.b $\xFF\x01\x0C$\xFF\x03\x19, $\x04"; |
| break; |
| } |
| return false; |
| case AArch64::INSvi8lane: |
| if (MI->getNumOperands() == 5 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(3).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (INSvi8lane V128:$dst, VectorIndexB:$idx, V128:$src, VectorIndexB:$idx2) |
| AsmString = "mov.b $\xFF\x01\x0C$\xFF\x03\x19, $\xFF\x04\x0C$\xFF\x05\x19"; |
| break; |
| } |
| return false; |
| case AArch64::ISB: |
| if (MI->getNumOperands() == 1 && |
| MI->getOperand(0).isImm() && |
| MI->getOperand(0).getImm() == 15) { |
| // (ISB 15) |
| AsmString = "isb"; |
| break; |
| } |
| return false; |
| case AArch64::LD1B_D_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LD1B_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ld1b $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LD1B_H_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LD1B_H_IMM_REAL Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ld1b $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LD1B_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LD1B_IMM_REAL Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ld1b $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LD1B_S_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LD1B_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ld1b $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LD1D_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LD1D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ld1d $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LD1Fourv16b_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD1Fourv16b_POST GPR64sp:$Rn, VecListFour16b:$Vt, XZR) |
| AsmString = "ld1 $\xFF\x02\x25, [$\x01], #64"; |
| break; |
| } |
| return false; |
| case AArch64::LD1Fourv1d_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDDDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD1Fourv1d_POST GPR64sp:$Rn, VecListFour1d:$Vt, XZR) |
| AsmString = "ld1 $\xFF\x02\x26, [$\x01], #32"; |
| break; |
| } |
| return false; |
| case AArch64::LD1Fourv2d_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD1Fourv2d_POST GPR64sp:$Rn, VecListFour2d:$Vt, XZR) |
| AsmString = "ld1 $\xFF\x02\x27, [$\x01], #64"; |
| break; |
| } |
| return false; |
| case AArch64::LD1Fourv2s_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDDDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD1Fourv2s_POST GPR64sp:$Rn, VecListFour2s:$Vt, XZR) |
| AsmString = "ld1 $\xFF\x02\x28, [$\x01], #32"; |
| break; |
| } |
| return false; |
| case AArch64::LD1Fourv4h_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDDDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD1Fourv4h_POST GPR64sp:$Rn, VecListFour4h:$Vt, XZR) |
| AsmString = "ld1 $\xFF\x02\x29, [$\x01], #32"; |
| break; |
| } |
| return false; |
| case AArch64::LD1Fourv4s_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD1Fourv4s_POST GPR64sp:$Rn, VecListFour4s:$Vt, XZR) |
| AsmString = "ld1 $\xFF\x02\x2A, [$\x01], #64"; |
| break; |
| } |
| return false; |
| case AArch64::LD1Fourv8b_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDDDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD1Fourv8b_POST GPR64sp:$Rn, VecListFour8b:$Vt, XZR) |
| AsmString = "ld1 $\xFF\x02\x2B, [$\x01], #32"; |
| break; |
| } |
| return false; |
| case AArch64::LD1Fourv8h_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD1Fourv8h_POST GPR64sp:$Rn, VecListFour8h:$Vt, XZR) |
| AsmString = "ld1 $\xFF\x02\x2C, [$\x01], #64"; |
| break; |
| } |
| return false; |
| case AArch64::LD1H_D_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LD1H_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ld1h $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LD1H_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LD1H_IMM_REAL Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ld1h $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LD1H_S_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LD1H_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ld1h $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LD1Onev16b_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD1Onev16b_POST GPR64sp:$Rn, VecListOne16b:$Vt, XZR) |
| AsmString = "ld1 $\xFF\x02\x25, [$\x01], #16"; |
| break; |
| } |
| return false; |
| case AArch64::LD1Onev1d_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::FPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD1Onev1d_POST GPR64sp:$Rn, VecListOne1d:$Vt, XZR) |
| AsmString = "ld1 $\xFF\x02\x26, [$\x01], #8"; |
| break; |
| } |
| return false; |
| case AArch64::LD1Onev2d_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD1Onev2d_POST GPR64sp:$Rn, VecListOne2d:$Vt, XZR) |
| AsmString = "ld1 $\xFF\x02\x27, [$\x01], #16"; |
| break; |
| } |
| return false; |
| case AArch64::LD1Onev2s_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::FPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD1Onev2s_POST GPR64sp:$Rn, VecListOne2s:$Vt, XZR) |
| AsmString = "ld1 $\xFF\x02\x28, [$\x01], #8"; |
| break; |
| } |
| return false; |
| case AArch64::LD1Onev4h_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::FPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD1Onev4h_POST GPR64sp:$Rn, VecListOne4h:$Vt, XZR) |
| AsmString = "ld1 $\xFF\x02\x29, [$\x01], #8"; |
| break; |
| } |
| return false; |
| case AArch64::LD1Onev4s_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD1Onev4s_POST GPR64sp:$Rn, VecListOne4s:$Vt, XZR) |
| AsmString = "ld1 $\xFF\x02\x2A, [$\x01], #16"; |
| break; |
| } |
| return false; |
| case AArch64::LD1Onev8b_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::FPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD1Onev8b_POST GPR64sp:$Rn, VecListOne8b:$Vt, XZR) |
| AsmString = "ld1 $\xFF\x02\x2B, [$\x01], #8"; |
| break; |
| } |
| return false; |
| case AArch64::LD1Onev8h_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD1Onev8h_POST GPR64sp:$Rn, VecListOne8h:$Vt, XZR) |
| AsmString = "ld1 $\xFF\x02\x2C, [$\x01], #16"; |
| break; |
| } |
| return false; |
| case AArch64::LD1RB_D_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LD1RB_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ld1rb $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LD1RB_H_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LD1RB_H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ld1rb $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LD1RB_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LD1RB_IMM Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ld1rb $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LD1RB_S_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LD1RB_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ld1rb $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LD1RD_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LD1RD_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ld1rd $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LD1RH_D_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LD1RH_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ld1rh $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LD1RH_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LD1RH_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ld1rh $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LD1RH_S_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LD1RH_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ld1rh $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LD1RQ_B_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LD1RQ_B_IMM Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ld1rqb $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LD1RQ_D_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LD1RQ_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ld1rqd $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LD1RQ_H_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LD1RQ_H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ld1rqh $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LD1RQ_W_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LD1RQ_W_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ld1rqw $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LD1RSB_D_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LD1RSB_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ld1rsb $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LD1RSB_H_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LD1RSB_H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ld1rsb $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LD1RSB_S_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LD1RSB_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ld1rsb $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LD1RSH_D_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LD1RSH_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ld1rsh $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LD1RSH_S_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LD1RSH_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ld1rsh $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LD1RSW_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LD1RSW_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ld1rsw $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LD1RW_D_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LD1RW_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ld1rw $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LD1RW_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LD1RW_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ld1rw $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LD1Rv16b_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD1Rv16b_POST GPR64sp:$Rn, VecListOne16b:$Vt, XZR) |
| AsmString = "ld1r $\xFF\x02\x25, [$\x01], #1"; |
| break; |
| } |
| return false; |
| case AArch64::LD1Rv1d_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::FPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD1Rv1d_POST GPR64sp:$Rn, VecListOne1d:$Vt, XZR) |
| AsmString = "ld1r $\xFF\x02\x26, [$\x01], #8"; |
| break; |
| } |
| return false; |
| case AArch64::LD1Rv2d_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD1Rv2d_POST GPR64sp:$Rn, VecListOne2d:$Vt, XZR) |
| AsmString = "ld1r $\xFF\x02\x27, [$\x01], #8"; |
| break; |
| } |
| return false; |
| case AArch64::LD1Rv2s_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::FPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD1Rv2s_POST GPR64sp:$Rn, VecListOne2s:$Vt, XZR) |
| AsmString = "ld1r $\xFF\x02\x28, [$\x01], #4"; |
| break; |
| } |
| return false; |
| case AArch64::LD1Rv4h_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::FPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD1Rv4h_POST GPR64sp:$Rn, VecListOne4h:$Vt, XZR) |
| AsmString = "ld1r $\xFF\x02\x29, [$\x01], #2"; |
| break; |
| } |
| return false; |
| case AArch64::LD1Rv4s_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD1Rv4s_POST GPR64sp:$Rn, VecListOne4s:$Vt, XZR) |
| AsmString = "ld1r $\xFF\x02\x2A, [$\x01], #4"; |
| break; |
| } |
| return false; |
| case AArch64::LD1Rv8b_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::FPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD1Rv8b_POST GPR64sp:$Rn, VecListOne8b:$Vt, XZR) |
| AsmString = "ld1r $\xFF\x02\x2B, [$\x01], #1"; |
| break; |
| } |
| return false; |
| case AArch64::LD1Rv8h_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD1Rv8h_POST GPR64sp:$Rn, VecListOne8h:$Vt, XZR) |
| AsmString = "ld1r $\xFF\x02\x2C, [$\x01], #2"; |
| break; |
| } |
| return false; |
| case AArch64::LD1SB_D_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LD1SB_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ld1sb $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LD1SB_H_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LD1SB_H_IMM_REAL Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ld1sb $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LD1SB_S_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LD1SB_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ld1sb $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LD1SH_D_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LD1SH_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ld1sh $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LD1SH_S_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LD1SH_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ld1sh $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LD1SW_D_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LD1SW_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ld1sw $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LD1Threev16b_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD1Threev16b_POST GPR64sp:$Rn, VecListThree16b:$Vt, XZR) |
| AsmString = "ld1 $\xFF\x02\x25, [$\x01], #48"; |
| break; |
| } |
| return false; |
| case AArch64::LD1Threev1d_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD1Threev1d_POST GPR64sp:$Rn, VecListThree1d:$Vt, XZR) |
| AsmString = "ld1 $\xFF\x02\x26, [$\x01], #24"; |
| break; |
| } |
| return false; |
| case AArch64::LD1Threev2d_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD1Threev2d_POST GPR64sp:$Rn, VecListThree2d:$Vt, XZR) |
| AsmString = "ld1 $\xFF\x02\x27, [$\x01], #48"; |
| break; |
| } |
| return false; |
| case AArch64::LD1Threev2s_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD1Threev2s_POST GPR64sp:$Rn, VecListThree2s:$Vt, XZR) |
| AsmString = "ld1 $\xFF\x02\x28, [$\x01], #24"; |
| break; |
| } |
| return false; |
| case AArch64::LD1Threev4h_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD1Threev4h_POST GPR64sp:$Rn, VecListThree4h:$Vt, XZR) |
| AsmString = "ld1 $\xFF\x02\x29, [$\x01], #24"; |
| break; |
| } |
| return false; |
| case AArch64::LD1Threev4s_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD1Threev4s_POST GPR64sp:$Rn, VecListThree4s:$Vt, XZR) |
| AsmString = "ld1 $\xFF\x02\x2A, [$\x01], #48"; |
| break; |
| } |
| return false; |
| case AArch64::LD1Threev8b_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD1Threev8b_POST GPR64sp:$Rn, VecListThree8b:$Vt, XZR) |
| AsmString = "ld1 $\xFF\x02\x2B, [$\x01], #24"; |
| break; |
| } |
| return false; |
| case AArch64::LD1Threev8h_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD1Threev8h_POST GPR64sp:$Rn, VecListThree8h:$Vt, XZR) |
| AsmString = "ld1 $\xFF\x02\x2C, [$\x01], #48"; |
| break; |
| } |
| return false; |
| case AArch64::LD1Twov16b_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD1Twov16b_POST GPR64sp:$Rn, VecListTwo16b:$Vt, XZR) |
| AsmString = "ld1 $\xFF\x02\x25, [$\x01], #32"; |
| break; |
| } |
| return false; |
| case AArch64::LD1Twov1d_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD1Twov1d_POST GPR64sp:$Rn, VecListTwo1d:$Vt, XZR) |
| AsmString = "ld1 $\xFF\x02\x26, [$\x01], #16"; |
| break; |
| } |
| return false; |
| case AArch64::LD1Twov2d_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD1Twov2d_POST GPR64sp:$Rn, VecListTwo2d:$Vt, XZR) |
| AsmString = "ld1 $\xFF\x02\x27, [$\x01], #32"; |
| break; |
| } |
| return false; |
| case AArch64::LD1Twov2s_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD1Twov2s_POST GPR64sp:$Rn, VecListTwo2s:$Vt, XZR) |
| AsmString = "ld1 $\xFF\x02\x28, [$\x01], #16"; |
| break; |
| } |
| return false; |
| case AArch64::LD1Twov4h_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD1Twov4h_POST GPR64sp:$Rn, VecListTwo4h:$Vt, XZR) |
| AsmString = "ld1 $\xFF\x02\x29, [$\x01], #16"; |
| break; |
| } |
| return false; |
| case AArch64::LD1Twov4s_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD1Twov4s_POST GPR64sp:$Rn, VecListTwo4s:$Vt, XZR) |
| AsmString = "ld1 $\xFF\x02\x2A, [$\x01], #32"; |
| break; |
| } |
| return false; |
| case AArch64::LD1Twov8b_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD1Twov8b_POST GPR64sp:$Rn, VecListTwo8b:$Vt, XZR) |
| AsmString = "ld1 $\xFF\x02\x2B, [$\x01], #16"; |
| break; |
| } |
| return false; |
| case AArch64::LD1Twov8h_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD1Twov8h_POST GPR64sp:$Rn, VecListTwo8h:$Vt, XZR) |
| AsmString = "ld1 $\xFF\x02\x2C, [$\x01], #32"; |
| break; |
| } |
| return false; |
| case AArch64::LD1W_D_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LD1W_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ld1w $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LD1W_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LD1W_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ld1w $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LD1i16_POST: |
| if (MI->getNumOperands() == 6 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(5).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD1i16_POST GPR64sp:$Rn, VecListOneh:$Vt, VectorIndexH:$idx, XZR) |
| AsmString = "ld1 $\xFF\x02\x2D$\xFF\x04\x19, [$\x01], #2"; |
| break; |
| } |
| return false; |
| case AArch64::LD1i32_POST: |
| if (MI->getNumOperands() == 6 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(5).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD1i32_POST GPR64sp:$Rn, VecListOnes:$Vt, VectorIndexS:$idx, XZR) |
| AsmString = "ld1 $\xFF\x02\x2E$\xFF\x04\x19, [$\x01], #4"; |
| break; |
| } |
| return false; |
| case AArch64::LD1i64_POST: |
| if (MI->getNumOperands() == 6 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(5).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD1i64_POST GPR64sp:$Rn, VecListOned:$Vt, VectorIndexD:$idx, XZR) |
| AsmString = "ld1 $\xFF\x02\x2F$\xFF\x04\x19, [$\x01], #8"; |
| break; |
| } |
| return false; |
| case AArch64::LD1i8_POST: |
| if (MI->getNumOperands() == 6 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(5).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD1i8_POST GPR64sp:$Rn, VecListOneb:$Vt, VectorIndexB:$idx, XZR) |
| AsmString = "ld1 $\xFF\x02\x30$\xFF\x04\x19, [$\x01], #1"; |
| break; |
| } |
| return false; |
| case AArch64::LD2B_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPR2RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LD2B_IMM ZZ_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ld2b $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LD2D_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPR2RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LD2D_IMM ZZ_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ld2d $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LD2H_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPR2RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LD2H_IMM ZZ_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ld2h $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LD2Rv16b_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD2Rv16b_POST GPR64sp:$Rn, VecListTwo16b:$Vt, XZR) |
| AsmString = "ld2r $\xFF\x02\x25, [$\x01], #2"; |
| break; |
| } |
| return false; |
| case AArch64::LD2Rv1d_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD2Rv1d_POST GPR64sp:$Rn, VecListTwo1d:$Vt, XZR) |
| AsmString = "ld2r $\xFF\x02\x26, [$\x01], #16"; |
| break; |
| } |
| return false; |
| case AArch64::LD2Rv2d_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD2Rv2d_POST GPR64sp:$Rn, VecListTwo2d:$Vt, XZR) |
| AsmString = "ld2r $\xFF\x02\x27, [$\x01], #16"; |
| break; |
| } |
| return false; |
| case AArch64::LD2Rv2s_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD2Rv2s_POST GPR64sp:$Rn, VecListTwo2s:$Vt, XZR) |
| AsmString = "ld2r $\xFF\x02\x28, [$\x01], #8"; |
| break; |
| } |
| return false; |
| case AArch64::LD2Rv4h_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD2Rv4h_POST GPR64sp:$Rn, VecListTwo4h:$Vt, XZR) |
| AsmString = "ld2r $\xFF\x02\x29, [$\x01], #4"; |
| break; |
| } |
| return false; |
| case AArch64::LD2Rv4s_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD2Rv4s_POST GPR64sp:$Rn, VecListTwo4s:$Vt, XZR) |
| AsmString = "ld2r $\xFF\x02\x2A, [$\x01], #8"; |
| break; |
| } |
| return false; |
| case AArch64::LD2Rv8b_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD2Rv8b_POST GPR64sp:$Rn, VecListTwo8b:$Vt, XZR) |
| AsmString = "ld2r $\xFF\x02\x2B, [$\x01], #2"; |
| break; |
| } |
| return false; |
| case AArch64::LD2Rv8h_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD2Rv8h_POST GPR64sp:$Rn, VecListTwo8h:$Vt, XZR) |
| AsmString = "ld2r $\xFF\x02\x2C, [$\x01], #4"; |
| break; |
| } |
| return false; |
| case AArch64::LD2Twov16b_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD2Twov16b_POST GPR64sp:$Rn, VecListTwo16b:$Vt, XZR) |
| AsmString = "ld2 $\xFF\x02\x25, [$\x01], #32"; |
| break; |
| } |
| return false; |
| case AArch64::LD2Twov2d_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD2Twov2d_POST GPR64sp:$Rn, VecListTwo2d:$Vt, XZR) |
| AsmString = "ld2 $\xFF\x02\x27, [$\x01], #32"; |
| break; |
| } |
| return false; |
| case AArch64::LD2Twov2s_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD2Twov2s_POST GPR64sp:$Rn, VecListTwo2s:$Vt, XZR) |
| AsmString = "ld2 $\xFF\x02\x28, [$\x01], #16"; |
| break; |
| } |
| return false; |
| case AArch64::LD2Twov4h_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD2Twov4h_POST GPR64sp:$Rn, VecListTwo4h:$Vt, XZR) |
| AsmString = "ld2 $\xFF\x02\x29, [$\x01], #16"; |
| break; |
| } |
| return false; |
| case AArch64::LD2Twov4s_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD2Twov4s_POST GPR64sp:$Rn, VecListTwo4s:$Vt, XZR) |
| AsmString = "ld2 $\xFF\x02\x2A, [$\x01], #32"; |
| break; |
| } |
| return false; |
| case AArch64::LD2Twov8b_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD2Twov8b_POST GPR64sp:$Rn, VecListTwo8b:$Vt, XZR) |
| AsmString = "ld2 $\xFF\x02\x2B, [$\x01], #16"; |
| break; |
| } |
| return false; |
| case AArch64::LD2Twov8h_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD2Twov8h_POST GPR64sp:$Rn, VecListTwo8h:$Vt, XZR) |
| AsmString = "ld2 $\xFF\x02\x2C, [$\x01], #32"; |
| break; |
| } |
| return false; |
| case AArch64::LD2W_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPR2RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LD2W_IMM ZZ_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ld2w $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LD2i16_POST: |
| if (MI->getNumOperands() == 6 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(5).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD2i16_POST GPR64sp:$Rn, VecListTwoh:$Vt, VectorIndexH:$idx, XZR) |
| AsmString = "ld2 $\xFF\x02\x2D$\xFF\x04\x19, [$\x01], #4"; |
| break; |
| } |
| return false; |
| case AArch64::LD2i32_POST: |
| if (MI->getNumOperands() == 6 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(5).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD2i32_POST GPR64sp:$Rn, VecListTwos:$Vt, VectorIndexS:$idx, XZR) |
| AsmString = "ld2 $\xFF\x02\x2E$\xFF\x04\x19, [$\x01], #8"; |
| break; |
| } |
| return false; |
| case AArch64::LD2i64_POST: |
| if (MI->getNumOperands() == 6 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(5).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD2i64_POST GPR64sp:$Rn, VecListTwod:$Vt, VectorIndexD:$idx, XZR) |
| AsmString = "ld2 $\xFF\x02\x2F$\xFF\x04\x19, [$\x01], #16"; |
| break; |
| } |
| return false; |
| case AArch64::LD2i8_POST: |
| if (MI->getNumOperands() == 6 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(5).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD2i8_POST GPR64sp:$Rn, VecListTwob:$Vt, VectorIndexB:$idx, XZR) |
| AsmString = "ld2 $\xFF\x02\x30$\xFF\x04\x19, [$\x01], #2"; |
| break; |
| } |
| return false; |
| case AArch64::LD3B_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPR3RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LD3B_IMM ZZZ_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ld3b $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LD3D_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPR3RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LD3D_IMM ZZZ_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ld3d $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LD3H_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPR3RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LD3H_IMM ZZZ_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ld3h $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LD3Rv16b_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD3Rv16b_POST GPR64sp:$Rn, VecListThree16b:$Vt, XZR) |
| AsmString = "ld3r $\xFF\x02\x25, [$\x01], #3"; |
| break; |
| } |
| return false; |
| case AArch64::LD3Rv1d_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD3Rv1d_POST GPR64sp:$Rn, VecListThree1d:$Vt, XZR) |
| AsmString = "ld3r $\xFF\x02\x26, [$\x01], #24"; |
| break; |
| } |
| return false; |
| case AArch64::LD3Rv2d_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD3Rv2d_POST GPR64sp:$Rn, VecListThree2d:$Vt, XZR) |
| AsmString = "ld3r $\xFF\x02\x27, [$\x01], #24"; |
| break; |
| } |
| return false; |
| case AArch64::LD3Rv2s_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD3Rv2s_POST GPR64sp:$Rn, VecListThree2s:$Vt, XZR) |
| AsmString = "ld3r $\xFF\x02\x28, [$\x01], #12"; |
| break; |
| } |
| return false; |
| case AArch64::LD3Rv4h_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD3Rv4h_POST GPR64sp:$Rn, VecListThree4h:$Vt, XZR) |
| AsmString = "ld3r $\xFF\x02\x29, [$\x01], #6"; |
| break; |
| } |
| return false; |
| case AArch64::LD3Rv4s_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD3Rv4s_POST GPR64sp:$Rn, VecListThree4s:$Vt, XZR) |
| AsmString = "ld3r $\xFF\x02\x2A, [$\x01], #12"; |
| break; |
| } |
| return false; |
| case AArch64::LD3Rv8b_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD3Rv8b_POST GPR64sp:$Rn, VecListThree8b:$Vt, XZR) |
| AsmString = "ld3r $\xFF\x02\x2B, [$\x01], #3"; |
| break; |
| } |
| return false; |
| case AArch64::LD3Rv8h_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD3Rv8h_POST GPR64sp:$Rn, VecListThree8h:$Vt, XZR) |
| AsmString = "ld3r $\xFF\x02\x2C, [$\x01], #6"; |
| break; |
| } |
| return false; |
| case AArch64::LD3Threev16b_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD3Threev16b_POST GPR64sp:$Rn, VecListThree16b:$Vt, XZR) |
| AsmString = "ld3 $\xFF\x02\x25, [$\x01], #48"; |
| break; |
| } |
| return false; |
| case AArch64::LD3Threev2d_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD3Threev2d_POST GPR64sp:$Rn, VecListThree2d:$Vt, XZR) |
| AsmString = "ld3 $\xFF\x02\x27, [$\x01], #48"; |
| break; |
| } |
| return false; |
| case AArch64::LD3Threev2s_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD3Threev2s_POST GPR64sp:$Rn, VecListThree2s:$Vt, XZR) |
| AsmString = "ld3 $\xFF\x02\x28, [$\x01], #24"; |
| break; |
| } |
| return false; |
| case AArch64::LD3Threev4h_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD3Threev4h_POST GPR64sp:$Rn, VecListThree4h:$Vt, XZR) |
| AsmString = "ld3 $\xFF\x02\x29, [$\x01], #24"; |
| break; |
| } |
| return false; |
| case AArch64::LD3Threev4s_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD3Threev4s_POST GPR64sp:$Rn, VecListThree4s:$Vt, XZR) |
| AsmString = "ld3 $\xFF\x02\x2A, [$\x01], #48"; |
| break; |
| } |
| return false; |
| case AArch64::LD3Threev8b_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD3Threev8b_POST GPR64sp:$Rn, VecListThree8b:$Vt, XZR) |
| AsmString = "ld3 $\xFF\x02\x2B, [$\x01], #24"; |
| break; |
| } |
| return false; |
| case AArch64::LD3Threev8h_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD3Threev8h_POST GPR64sp:$Rn, VecListThree8h:$Vt, XZR) |
| AsmString = "ld3 $\xFF\x02\x2C, [$\x01], #48"; |
| break; |
| } |
| return false; |
| case AArch64::LD3W_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPR3RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LD3W_IMM ZZZ_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ld3w $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LD3i16_POST: |
| if (MI->getNumOperands() == 6 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(5).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD3i16_POST GPR64sp:$Rn, VecListThreeh:$Vt, VectorIndexH:$idx, XZR) |
| AsmString = "ld3 $\xFF\x02\x2D$\xFF\x04\x19, [$\x01], #6"; |
| break; |
| } |
| return false; |
| case AArch64::LD3i32_POST: |
| if (MI->getNumOperands() == 6 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(5).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD3i32_POST GPR64sp:$Rn, VecListThrees:$Vt, VectorIndexS:$idx, XZR) |
| AsmString = "ld3 $\xFF\x02\x2E$\xFF\x04\x19, [$\x01], #12"; |
| break; |
| } |
| return false; |
| case AArch64::LD3i64_POST: |
| if (MI->getNumOperands() == 6 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(5).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD3i64_POST GPR64sp:$Rn, VecListThreed:$Vt, VectorIndexD:$idx, XZR) |
| AsmString = "ld3 $\xFF\x02\x2F$\xFF\x04\x19, [$\x01], #24"; |
| break; |
| } |
| return false; |
| case AArch64::LD3i8_POST: |
| if (MI->getNumOperands() == 6 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(5).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD3i8_POST GPR64sp:$Rn, VecListThreeb:$Vt, VectorIndexB:$idx, XZR) |
| AsmString = "ld3 $\xFF\x02\x30$\xFF\x04\x19, [$\x01], #3"; |
| break; |
| } |
| return false; |
| case AArch64::LD4B_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPR4RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LD4B_IMM ZZZZ_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ld4b $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LD4D_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPR4RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LD4D_IMM ZZZZ_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ld4d $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LD4Fourv16b_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD4Fourv16b_POST GPR64sp:$Rn, VecListFour16b:$Vt, XZR) |
| AsmString = "ld4 $\xFF\x02\x25, [$\x01], #64"; |
| break; |
| } |
| return false; |
| case AArch64::LD4Fourv2d_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD4Fourv2d_POST GPR64sp:$Rn, VecListFour2d:$Vt, XZR) |
| AsmString = "ld4 $\xFF\x02\x27, [$\x01], #64"; |
| break; |
| } |
| return false; |
| case AArch64::LD4Fourv2s_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDDDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD4Fourv2s_POST GPR64sp:$Rn, VecListFour2s:$Vt, XZR) |
| AsmString = "ld4 $\xFF\x02\x28, [$\x01], #32"; |
| break; |
| } |
| return false; |
| case AArch64::LD4Fourv4h_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDDDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD4Fourv4h_POST GPR64sp:$Rn, VecListFour4h:$Vt, XZR) |
| AsmString = "ld4 $\xFF\x02\x29, [$\x01], #32"; |
| break; |
| } |
| return false; |
| case AArch64::LD4Fourv4s_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD4Fourv4s_POST GPR64sp:$Rn, VecListFour4s:$Vt, XZR) |
| AsmString = "ld4 $\xFF\x02\x2A, [$\x01], #64"; |
| break; |
| } |
| return false; |
| case AArch64::LD4Fourv8b_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDDDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD4Fourv8b_POST GPR64sp:$Rn, VecListFour8b:$Vt, XZR) |
| AsmString = "ld4 $\xFF\x02\x2B, [$\x01], #32"; |
| break; |
| } |
| return false; |
| case AArch64::LD4Fourv8h_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD4Fourv8h_POST GPR64sp:$Rn, VecListFour8h:$Vt, XZR) |
| AsmString = "ld4 $\xFF\x02\x2C, [$\x01], #64"; |
| break; |
| } |
| return false; |
| case AArch64::LD4H_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPR4RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LD4H_IMM ZZZZ_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ld4h $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LD4Rv16b_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD4Rv16b_POST GPR64sp:$Rn, VecListFour16b:$Vt, XZR) |
| AsmString = "ld4r $\xFF\x02\x25, [$\x01], #4"; |
| break; |
| } |
| return false; |
| case AArch64::LD4Rv1d_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDDDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD4Rv1d_POST GPR64sp:$Rn, VecListFour1d:$Vt, XZR) |
| AsmString = "ld4r $\xFF\x02\x26, [$\x01], #32"; |
| break; |
| } |
| return false; |
| case AArch64::LD4Rv2d_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD4Rv2d_POST GPR64sp:$Rn, VecListFour2d:$Vt, XZR) |
| AsmString = "ld4r $\xFF\x02\x27, [$\x01], #32"; |
| break; |
| } |
| return false; |
| case AArch64::LD4Rv2s_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDDDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD4Rv2s_POST GPR64sp:$Rn, VecListFour2s:$Vt, XZR) |
| AsmString = "ld4r $\xFF\x02\x28, [$\x01], #16"; |
| break; |
| } |
| return false; |
| case AArch64::LD4Rv4h_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDDDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD4Rv4h_POST GPR64sp:$Rn, VecListFour4h:$Vt, XZR) |
| AsmString = "ld4r $\xFF\x02\x29, [$\x01], #8"; |
| break; |
| } |
| return false; |
| case AArch64::LD4Rv4s_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD4Rv4s_POST GPR64sp:$Rn, VecListFour4s:$Vt, XZR) |
| AsmString = "ld4r $\xFF\x02\x2A, [$\x01], #16"; |
| break; |
| } |
| return false; |
| case AArch64::LD4Rv8b_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDDDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD4Rv8b_POST GPR64sp:$Rn, VecListFour8b:$Vt, XZR) |
| AsmString = "ld4r $\xFF\x02\x2B, [$\x01], #4"; |
| break; |
| } |
| return false; |
| case AArch64::LD4Rv8h_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD4Rv8h_POST GPR64sp:$Rn, VecListFour8h:$Vt, XZR) |
| AsmString = "ld4r $\xFF\x02\x2C, [$\x01], #8"; |
| break; |
| } |
| return false; |
| case AArch64::LD4W_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPR4RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LD4W_IMM ZZZZ_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ld4w $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LD4i16_POST: |
| if (MI->getNumOperands() == 6 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(5).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD4i16_POST GPR64sp:$Rn, VecListFourh:$Vt, VectorIndexH:$idx, XZR) |
| AsmString = "ld4 $\xFF\x02\x2D$\xFF\x04\x19, [$\x01], #8"; |
| break; |
| } |
| return false; |
| case AArch64::LD4i32_POST: |
| if (MI->getNumOperands() == 6 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(5).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD4i32_POST GPR64sp:$Rn, VecListFours:$Vt, VectorIndexS:$idx, XZR) |
| AsmString = "ld4 $\xFF\x02\x2E$\xFF\x04\x19, [$\x01], #16"; |
| break; |
| } |
| return false; |
| case AArch64::LD4i64_POST: |
| if (MI->getNumOperands() == 6 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(5).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD4i64_POST GPR64sp:$Rn, VecListFourd:$Vt, VectorIndexD:$idx, XZR) |
| AsmString = "ld4 $\xFF\x02\x2F$\xFF\x04\x19, [$\x01], #32"; |
| break; |
| } |
| return false; |
| case AArch64::LD4i8_POST: |
| if (MI->getNumOperands() == 6 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(5).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (LD4i8_POST GPR64sp:$Rn, VecListFourb:$Vt, VectorIndexB:$idx, XZR) |
| AsmString = "ld4 $\xFF\x02\x30$\xFF\x04\x19, [$\x01], #4"; |
| break; |
| } |
| return false; |
| case AArch64::LDADDB: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDADDB WZR, GPR32:$Rs, GPR64sp:$Rn) |
| AsmString = "staddb $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDADDH: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDADDH WZR, GPR32:$Rs, GPR64sp:$Rn) |
| AsmString = "staddh $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDADDLB: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDADDLB WZR, GPR32:$Rs, GPR64sp:$Rn) |
| AsmString = "staddlb $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDADDLH: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDADDLH WZR, GPR32:$Rs, GPR64sp:$Rn) |
| AsmString = "staddlh $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDADDLW: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDADDLW WZR, GPR32:$Rs, GPR64sp:$Rn) |
| AsmString = "staddl $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDADDLX: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::XZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDADDLX XZR, GPR64:$Rs, GPR64sp:$Rn) |
| AsmString = "staddl $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDADDW: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDADDW WZR, GPR32:$Rs, GPR64sp:$Rn) |
| AsmString = "stadd $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDADDX: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::XZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDADDX XZR, GPR64:$Rs, GPR64sp:$Rn) |
| AsmString = "stadd $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDAPURBi: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::HasV8_4aOps]) { |
| // (LDAPURBi GPR32:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "ldapurb $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::LDAPURHi: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::HasV8_4aOps]) { |
| // (LDAPURHi GPR32:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "ldapurh $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::LDAPURSBWi: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::HasV8_4aOps]) { |
| // (LDAPURSBWi GPR32:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "ldapursb $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::LDAPURSBXi: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::HasV8_4aOps]) { |
| // (LDAPURSBXi GPR64:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "ldapursb $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::LDAPURSHWi: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::HasV8_4aOps]) { |
| // (LDAPURSHWi GPR32:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "ldapursh $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::LDAPURSHXi: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::HasV8_4aOps]) { |
| // (LDAPURSHXi GPR64:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "ldapursh $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::LDAPURSWi: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::HasV8_4aOps]) { |
| // (LDAPURSWi GPR64:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "ldapursw $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::LDAPURXi: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::HasV8_4aOps]) { |
| // (LDAPURXi GPR64:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "ldapur $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::LDAPURi: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::HasV8_4aOps]) { |
| // (LDAPURi GPR32:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "ldapur $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::LDCLRB: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDCLRB WZR, GPR32:$Rs, GPR64sp:$Rn) |
| AsmString = "stclrb $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDCLRH: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDCLRH WZR, GPR32:$Rs, GPR64sp:$Rn) |
| AsmString = "stclrh $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDCLRLB: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDCLRLB WZR, GPR32:$Rs, GPR64sp:$Rn) |
| AsmString = "stclrlb $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDCLRLH: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDCLRLH WZR, GPR32:$Rs, GPR64sp:$Rn) |
| AsmString = "stclrlh $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDCLRLW: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDCLRLW WZR, GPR32:$Rs, GPR64sp:$Rn) |
| AsmString = "stclrl $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDCLRLX: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::XZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDCLRLX XZR, GPR64:$Rs, GPR64sp:$Rn) |
| AsmString = "stclrl $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDCLRW: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDCLRW WZR, GPR32:$Rs, GPR64sp:$Rn) |
| AsmString = "stclr $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDCLRX: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::XZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDCLRX XZR, GPR64:$Rs, GPR64sp:$Rn) |
| AsmString = "stclr $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDEORB: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDEORB WZR, GPR32:$Rs, GPR64sp:$Rn) |
| AsmString = "steorb $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDEORH: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDEORH WZR, GPR32:$Rs, GPR64sp:$Rn) |
| AsmString = "steorh $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDEORLB: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDEORLB WZR, GPR32:$Rs, GPR64sp:$Rn) |
| AsmString = "steorlb $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDEORLH: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDEORLH WZR, GPR32:$Rs, GPR64sp:$Rn) |
| AsmString = "steorlh $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDEORLW: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDEORLW WZR, GPR32:$Rs, GPR64sp:$Rn) |
| AsmString = "steorl $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDEORLX: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::XZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDEORLX XZR, GPR64:$Rs, GPR64sp:$Rn) |
| AsmString = "steorl $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDEORW: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDEORW WZR, GPR32:$Rs, GPR64sp:$Rn) |
| AsmString = "steor $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDEORX: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::XZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDEORX XZR, GPR64:$Rs, GPR64sp:$Rn) |
| AsmString = "steor $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDFF1B_D_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LDFF1B_D_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) |
| AsmString = "ldff1b $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDFF1B_H_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LDFF1B_H_REAL Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) |
| AsmString = "ldff1b $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDFF1B_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LDFF1B_REAL Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) |
| AsmString = "ldff1b $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDFF1B_S_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LDFF1B_S_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) |
| AsmString = "ldff1b $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDFF1D_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LDFF1D_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) |
| AsmString = "ldff1d $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDFF1H_D_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LDFF1H_D_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) |
| AsmString = "ldff1h $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDFF1H_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LDFF1H_REAL Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) |
| AsmString = "ldff1h $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDFF1H_S_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LDFF1H_S_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) |
| AsmString = "ldff1h $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDFF1SB_D_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LDFF1SB_D_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) |
| AsmString = "ldff1sb $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDFF1SB_H_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LDFF1SB_H_REAL Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) |
| AsmString = "ldff1sb $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDFF1SB_S_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LDFF1SB_S_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) |
| AsmString = "ldff1sb $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDFF1SH_D_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LDFF1SH_D_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) |
| AsmString = "ldff1sh $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDFF1SH_S_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LDFF1SH_S_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) |
| AsmString = "ldff1sh $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDFF1SW_D_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LDFF1SW_D_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) |
| AsmString = "ldff1sw $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDFF1W_D_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LDFF1W_D_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) |
| AsmString = "ldff1w $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDFF1W_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LDFF1W_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, XZR) |
| AsmString = "ldff1w $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDNF1B_D_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LDNF1B_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ldnf1b $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDNF1B_H_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LDNF1B_H_IMM_REAL Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ldnf1b $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDNF1B_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LDNF1B_IMM_REAL Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ldnf1b $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDNF1B_S_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LDNF1B_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ldnf1b $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDNF1D_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LDNF1D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ldnf1d $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDNF1H_D_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LDNF1H_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ldnf1h $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDNF1H_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LDNF1H_IMM_REAL Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ldnf1h $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDNF1H_S_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LDNF1H_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ldnf1h $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDNF1SB_D_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LDNF1SB_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ldnf1sb $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDNF1SB_H_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LDNF1SB_H_IMM_REAL Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ldnf1sb $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDNF1SB_S_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LDNF1SB_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ldnf1sb $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDNF1SH_D_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LDNF1SH_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ldnf1sh $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDNF1SH_S_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LDNF1SH_S_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ldnf1sh $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDNF1SW_D_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LDNF1SW_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ldnf1sw $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDNF1W_D_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LDNF1W_D_IMM_REAL Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ldnf1w $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDNF1W_IMM_REAL: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LDNF1W_IMM_REAL Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ldnf1w $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDNPDi: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::FPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (LDNPDi FPR64Op:$Rt, FPR64Op:$Rt2, GPR64sp:$Rn, 0) |
| AsmString = "ldnp $\x01, $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDNPQi: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (LDNPQi FPR128Op:$Rt, FPR128Op:$Rt2, GPR64sp:$Rn, 0) |
| AsmString = "ldnp $\x01, $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDNPSi: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::FPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (LDNPSi FPR32Op:$Rt, FPR32Op:$Rt2, GPR64sp:$Rn, 0) |
| AsmString = "ldnp $\x01, $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDNPWi: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (LDNPWi GPR32z:$Rt, GPR32z:$Rt2, GPR64sp:$Rn, 0) |
| AsmString = "ldnp $\x01, $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDNPXi: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (LDNPXi GPR64z:$Rt, GPR64z:$Rt2, GPR64sp:$Rn, 0) |
| AsmString = "ldnp $\x01, $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDNT1B_ZRI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LDNT1B_ZRI Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ldnt1b $\xFF\x01\x24, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDNT1D_ZRI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LDNT1D_ZRI Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ldnt1d $\xFF\x01\x20, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDNT1H_ZRI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LDNT1H_ZRI Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ldnt1h $\xFF\x01\x23, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDNT1W_ZRI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LDNT1W_ZRI Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "ldnt1w $\xFF\x01\x21, $\xFF\x02\x07/z, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDPDi: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::FPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (LDPDi FPR64Op:$Rt, FPR64Op:$Rt2, GPR64sp:$Rn, 0) |
| AsmString = "ldp $\x01, $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDPQi: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (LDPQi FPR128Op:$Rt, FPR128Op:$Rt2, GPR64sp:$Rn, 0) |
| AsmString = "ldp $\x01, $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDPSWi: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (LDPSWi GPR64z:$Rt, GPR64z:$Rt2, GPR64sp:$Rn, 0) |
| AsmString = "ldpsw $\x01, $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDPSi: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::FPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (LDPSi FPR32Op:$Rt, FPR32Op:$Rt2, GPR64sp:$Rn, 0) |
| AsmString = "ldp $\x01, $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDPWi: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (LDPWi GPR32z:$Rt, GPR32z:$Rt2, GPR64sp:$Rn, 0) |
| AsmString = "ldp $\x01, $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDPXi: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (LDPXi GPR64z:$Rt, GPR64z:$Rt2, GPR64sp:$Rn, 0) |
| AsmString = "ldp $\x01, $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDRAAindexed: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::HasV8_3aOps]) { |
| // (LDRAAindexed GPR64:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "ldraa $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::LDRABindexed: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::HasV8_3aOps]) { |
| // (LDRABindexed GPR64:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "ldrab $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::LDRBBroX: |
| if (MI->getNumOperands() == 5 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| MI->getOperand(4).isImm() && |
| MI->getOperand(4).getImm() == 0) { |
| // (LDRBBroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) |
| AsmString = "ldrb $\x01, [$\x02, $\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDRBBui: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (LDRBBui GPR32:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "ldrb $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::LDRBroX: |
| if (MI->getNumOperands() == 5 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR8RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| MI->getOperand(4).isImm() && |
| MI->getOperand(4).getImm() == 0) { |
| // (LDRBroX FPR8Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) |
| AsmString = "ldr $\x01, [$\x02, $\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDRBui: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR8RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (LDRBui FPR8Op:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "ldr $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::LDRDroX: |
| if (MI->getNumOperands() == 5 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| MI->getOperand(4).isImm() && |
| MI->getOperand(4).getImm() == 0) { |
| // (LDRDroX FPR64Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) |
| AsmString = "ldr $\x01, [$\x02, $\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDRDui: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (LDRDui FPR64Op:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "ldr $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::LDRHHroX: |
| if (MI->getNumOperands() == 5 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| MI->getOperand(4).isImm() && |
| MI->getOperand(4).getImm() == 0) { |
| // (LDRHHroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) |
| AsmString = "ldrh $\x01, [$\x02, $\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDRHHui: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (LDRHHui GPR32:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "ldrh $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::LDRHroX: |
| if (MI->getNumOperands() == 5 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR16RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| MI->getOperand(4).isImm() && |
| MI->getOperand(4).getImm() == 0) { |
| // (LDRHroX FPR16Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) |
| AsmString = "ldr $\x01, [$\x02, $\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDRHui: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR16RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (LDRHui FPR16Op:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "ldr $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::LDRQroX: |
| if (MI->getNumOperands() == 5 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| MI->getOperand(4).isImm() && |
| MI->getOperand(4).getImm() == 0) { |
| // (LDRQroX FPR128Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) |
| AsmString = "ldr $\x01, [$\x02, $\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDRQui: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (LDRQui FPR128Op:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "ldr $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::LDRSBWroX: |
| if (MI->getNumOperands() == 5 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| MI->getOperand(4).isImm() && |
| MI->getOperand(4).getImm() == 0) { |
| // (LDRSBWroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) |
| AsmString = "ldrsb $\x01, [$\x02, $\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDRSBWui: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (LDRSBWui GPR32:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "ldrsb $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::LDRSBXroX: |
| if (MI->getNumOperands() == 5 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| MI->getOperand(4).isImm() && |
| MI->getOperand(4).getImm() == 0) { |
| // (LDRSBXroX GPR64:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) |
| AsmString = "ldrsb $\x01, [$\x02, $\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDRSBXui: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (LDRSBXui GPR64:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "ldrsb $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::LDRSHWroX: |
| if (MI->getNumOperands() == 5 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| MI->getOperand(4).isImm() && |
| MI->getOperand(4).getImm() == 0) { |
| // (LDRSHWroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) |
| AsmString = "ldrsh $\x01, [$\x02, $\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDRSHWui: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (LDRSHWui GPR32:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "ldrsh $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::LDRSHXroX: |
| if (MI->getNumOperands() == 5 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| MI->getOperand(4).isImm() && |
| MI->getOperand(4).getImm() == 0) { |
| // (LDRSHXroX GPR64:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) |
| AsmString = "ldrsh $\x01, [$\x02, $\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDRSHXui: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (LDRSHXui GPR64:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "ldrsh $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::LDRSWroX: |
| if (MI->getNumOperands() == 5 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| MI->getOperand(4).isImm() && |
| MI->getOperand(4).getImm() == 0) { |
| // (LDRSWroX GPR64:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) |
| AsmString = "ldrsw $\x01, [$\x02, $\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDRSWui: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (LDRSWui GPR64:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "ldrsw $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::LDRSroX: |
| if (MI->getNumOperands() == 5 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| MI->getOperand(4).isImm() && |
| MI->getOperand(4).getImm() == 0) { |
| // (LDRSroX FPR32Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) |
| AsmString = "ldr $\x01, [$\x02, $\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDRSui: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (LDRSui FPR32Op:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "ldr $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::LDRWroX: |
| if (MI->getNumOperands() == 5 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| MI->getOperand(4).isImm() && |
| MI->getOperand(4).getImm() == 0) { |
| // (LDRWroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) |
| AsmString = "ldr $\x01, [$\x02, $\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDRWui: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (LDRWui GPR32z:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "ldr $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::LDRXroX: |
| if (MI->getNumOperands() == 5 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| MI->getOperand(4).isImm() && |
| MI->getOperand(4).getImm() == 0) { |
| // (LDRXroX GPR64:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) |
| AsmString = "ldr $\x01, [$\x02, $\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDRXui: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (LDRXui GPR64z:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "ldr $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::LDR_PXI: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::PPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LDR_PXI PPRAny:$Pt, GPR64sp:$Rn, 0) |
| AsmString = "ldr $\xFF\x01\x07, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::LDR_ZXI: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (LDR_ZXI ZPRAny:$Zt, GPR64sp:$Rn, 0) |
| AsmString = "ldr $\xFF\x01\x07, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::LDSETB: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDSETB WZR, GPR32:$Rs, GPR64sp:$Rn) |
| AsmString = "stsetb $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDSETH: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDSETH WZR, GPR32:$Rs, GPR64sp:$Rn) |
| AsmString = "stseth $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDSETLB: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDSETLB WZR, GPR32:$Rs, GPR64sp:$Rn) |
| AsmString = "stsetlb $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDSETLH: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDSETLH WZR, GPR32:$Rs, GPR64sp:$Rn) |
| AsmString = "stsetlh $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDSETLW: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDSETLW WZR, GPR32:$Rs, GPR64sp:$Rn) |
| AsmString = "stsetl $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDSETLX: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::XZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDSETLX XZR, GPR64:$Rs, GPR64sp:$Rn) |
| AsmString = "stsetl $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDSETW: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDSETW WZR, GPR32:$Rs, GPR64sp:$Rn) |
| AsmString = "stset $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDSETX: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::XZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDSETX XZR, GPR64:$Rs, GPR64sp:$Rn) |
| AsmString = "stset $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDSMAXB: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDSMAXB WZR, GPR32:$Rs, GPR64sp:$Rn) |
| AsmString = "stsmaxb $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDSMAXH: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDSMAXH WZR, GPR32:$Rs, GPR64sp:$Rn) |
| AsmString = "stsmaxh $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDSMAXLB: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDSMAXLB WZR, GPR32:$Rs, GPR64sp:$Rn) |
| AsmString = "stsmaxlb $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDSMAXLH: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDSMAXLH WZR, GPR32:$Rs, GPR64sp:$Rn) |
| AsmString = "stsmaxlh $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDSMAXLW: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDSMAXLW WZR, GPR32:$Rs, GPR64sp:$Rn) |
| AsmString = "stsmaxl $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDSMAXLX: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::XZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDSMAXLX XZR, GPR64:$Rs, GPR64sp:$Rn) |
| AsmString = "stsmaxl $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDSMAXW: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDSMAXW WZR, GPR32:$Rs, GPR64sp:$Rn) |
| AsmString = "stsmax $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDSMAXX: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::XZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDSMAXX XZR, GPR64:$Rs, GPR64sp:$Rn) |
| AsmString = "stsmax $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDSMINB: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDSMINB WZR, GPR32:$Rs, GPR64sp:$Rn) |
| AsmString = "stsminb $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDSMINH: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDSMINH WZR, GPR32:$Rs, GPR64sp:$Rn) |
| AsmString = "stsminh $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDSMINLB: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDSMINLB WZR, GPR32:$Rs, GPR64sp:$Rn) |
| AsmString = "stsminlb $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDSMINLH: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDSMINLH WZR, GPR32:$Rs, GPR64sp:$Rn) |
| AsmString = "stsminlh $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDSMINLW: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDSMINLW WZR, GPR32:$Rs, GPR64sp:$Rn) |
| AsmString = "stsminl $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDSMINLX: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::XZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDSMINLX XZR, GPR64:$Rs, GPR64sp:$Rn) |
| AsmString = "stsminl $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDSMINW: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDSMINW WZR, GPR32:$Rs, GPR64sp:$Rn) |
| AsmString = "stsmin $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDSMINX: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::XZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDSMINX XZR, GPR64:$Rs, GPR64sp:$Rn) |
| AsmString = "stsmin $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDTRBi: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (LDTRBi GPR32:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "ldtrb $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::LDTRHi: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (LDTRHi GPR32:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "ldtrh $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::LDTRSBWi: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (LDTRSBWi GPR32:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "ldtrsb $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::LDTRSBXi: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (LDTRSBXi GPR64:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "ldtrsb $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::LDTRSHWi: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (LDTRSHWi GPR32:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "ldtrsh $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::LDTRSHXi: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (LDTRSHXi GPR64:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "ldtrsh $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::LDTRSWi: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (LDTRSWi GPR64:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "ldtrsw $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::LDTRWi: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (LDTRWi GPR32:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "ldtr $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::LDTRXi: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (LDTRXi GPR64:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "ldtr $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::LDUMAXB: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDUMAXB WZR, GPR32:$Rs, GPR64sp:$Rn) |
| AsmString = "stumaxb $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDUMAXH: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDUMAXH WZR, GPR32:$Rs, GPR64sp:$Rn) |
| AsmString = "stumaxh $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDUMAXLB: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDUMAXLB WZR, GPR32:$Rs, GPR64sp:$Rn) |
| AsmString = "stumaxlb $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDUMAXLH: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDUMAXLH WZR, GPR32:$Rs, GPR64sp:$Rn) |
| AsmString = "stumaxlh $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDUMAXLW: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDUMAXLW WZR, GPR32:$Rs, GPR64sp:$Rn) |
| AsmString = "stumaxl $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDUMAXLX: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::XZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDUMAXLX XZR, GPR64:$Rs, GPR64sp:$Rn) |
| AsmString = "stumaxl $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDUMAXW: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDUMAXW WZR, GPR32:$Rs, GPR64sp:$Rn) |
| AsmString = "stumax $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDUMAXX: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::XZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDUMAXX XZR, GPR64:$Rs, GPR64sp:$Rn) |
| AsmString = "stumax $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDUMINB: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDUMINB WZR, GPR32:$Rs, GPR64sp:$Rn) |
| AsmString = "stuminb $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDUMINH: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDUMINH WZR, GPR32:$Rs, GPR64sp:$Rn) |
| AsmString = "stuminh $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDUMINLB: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDUMINLB WZR, GPR32:$Rs, GPR64sp:$Rn) |
| AsmString = "stuminlb $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDUMINLH: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDUMINLH WZR, GPR32:$Rs, GPR64sp:$Rn) |
| AsmString = "stuminlh $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDUMINLW: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDUMINLW WZR, GPR32:$Rs, GPR64sp:$Rn) |
| AsmString = "stuminl $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDUMINLX: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::XZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDUMINLX XZR, GPR64:$Rs, GPR64sp:$Rn) |
| AsmString = "stuminl $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDUMINW: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDUMINW WZR, GPR32:$Rs, GPR64sp:$Rn) |
| AsmString = "stumin $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDUMINX: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).getReg() == AArch64::XZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureLSE]) { |
| // (LDUMINX XZR, GPR64:$Rs, GPR64sp:$Rn) |
| AsmString = "stumin $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::LDURBBi: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (LDURBBi GPR32:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "ldurb $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::LDURBi: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR8RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (LDURBi FPR8Op:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "ldur $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::LDURDi: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (LDURDi FPR64Op:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "ldur $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::LDURHHi: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (LDURHHi GPR32:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "ldurh $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::LDURHi: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR16RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (LDURHi FPR16Op:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "ldur $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::LDURQi: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (LDURQi FPR128Op:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "ldur $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::LDURSBWi: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (LDURSBWi GPR32:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "ldursb $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::LDURSBXi: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (LDURSBXi GPR64:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "ldursb $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::LDURSHWi: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (LDURSHWi GPR32:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "ldursh $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::LDURSHXi: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (LDURSHXi GPR64:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "ldursh $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::LDURSWi: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (LDURSWi GPR64:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "ldursw $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::LDURSi: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (LDURSi FPR32Op:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "ldur $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::LDURWi: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (LDURWi GPR32z:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "ldur $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::LDURXi: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (LDURXi GPR64z:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "ldur $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::MADDWrrr: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::WZR) { |
| // (MADDWrrr GPR32:$dst, GPR32:$src1, GPR32:$src2, WZR) |
| AsmString = "mul $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64::MADDXrrr: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR) { |
| // (MADDXrrr GPR64:$dst, GPR64:$src1, GPR64:$src2, XZR) |
| AsmString = "mul $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64::MSUBWrrr: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::WZR) { |
| // (MSUBWrrr GPR32:$dst, GPR32:$src1, GPR32:$src2, WZR) |
| AsmString = "mneg $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64::MSUBXrrr: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR) { |
| // (MSUBXrrr GPR64:$dst, GPR64:$src1, GPR64:$src2, XZR) |
| AsmString = "mneg $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64::NOTv16i8: |
| if (MI->getNumOperands() == 2 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(1).getReg())) { |
| // (NOTv16i8 V128:$Vd, V128:$Vn) |
| AsmString = "mvn.16b $\xFF\x01\x0C, $\xFF\x02\x0C"; |
| break; |
| } |
| return false; |
| case AArch64::NOTv8i8: |
| if (MI->getNumOperands() == 2 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::FPR64RegClassID).contains(MI->getOperand(1).getReg())) { |
| // (NOTv8i8 V64:$Vd, V64:$Vn) |
| AsmString = "mvn.8b $\xFF\x01\x0C, $\xFF\x02\x0C"; |
| break; |
| } |
| return false; |
| case AArch64::ORNWrs: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).getReg() == AArch64::WZR && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, 0) |
| AsmString = "mvn $\x01, $\x03"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).getReg() == AArch64::WZR && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg())) { |
| // (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, logical_shift32:$sh) |
| AsmString = "mvn $\x01, $\x03$\xFF\x04\x02"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (ORNWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) |
| AsmString = "orn $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64::ORNXrs: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).getReg() == AArch64::XZR && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, 0) |
| AsmString = "mvn $\x01, $\x03"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).getReg() == AArch64::XZR && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg())) { |
| // (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, logical_shift64:$sh) |
| AsmString = "mvn $\x01, $\x03$\xFF\x04\x02"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (ORNXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) |
| AsmString = "orn $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64::ORRS_PPzPP: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::PPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPRRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MI->getOperand(2).getReg() == MI->getOperand(1).getReg() && |
| MI->getOperand(3).isReg() && |
| MI->getOperand(3).getReg() == MI->getOperand(1).getReg() && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (ORRS_PPzPP PPR8:$Pd, PPR8:$Pn, PPR8:$Pn, PPR8:$Pn) |
| AsmString = "movs $\xFF\x01\x06, $\xFF\x02\x06"; |
| break; |
| } |
| return false; |
| case AArch64::ORRWrs: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).getReg() == AArch64::WZR && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (ORRWrs GPR32:$dst, WZR, GPR32:$src, 0) |
| AsmString = "mov $\x01, $\x03"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (ORRWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) |
| AsmString = "orr $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64::ORRXrs: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).getReg() == AArch64::XZR && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (ORRXrs GPR64:$dst, XZR, GPR64:$src, 0) |
| AsmString = "mov $\x01, $\x03"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (ORRXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) |
| AsmString = "orr $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64::ORR_PPzPP: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::PPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPRRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MI->getOperand(2).getReg() == MI->getOperand(1).getReg() && |
| MI->getOperand(3).isReg() && |
| MI->getOperand(3).getReg() == MI->getOperand(1).getReg() && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (ORR_PPzPP PPR8:$Pd, PPR8:$Pn, PPR8:$Pn, PPR8:$Pn) |
| AsmString = "mov $\xFF\x01\x06, $\xFF\x02\x06"; |
| break; |
| } |
| return false; |
| case AArch64::ORR_ZI: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| AArch64AppleInstPrinterValidateMCOperand(MI->getOperand(2), STI, 1) && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (ORR_ZI ZPR8:$Zdn, sve_logical_imm8:$imm) |
| AsmString = "orr $\xFF\x01\x06, $\xFF\x01\x06, $\xFF\x03\x08"; |
| break; |
| } |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| AArch64AppleInstPrinterValidateMCOperand(MI->getOperand(2), STI, 2) && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (ORR_ZI ZPR16:$Zdn, sve_logical_imm16:$imm) |
| AsmString = "orr $\xFF\x01\x09, $\xFF\x01\x09, $\xFF\x03\x0A"; |
| break; |
| } |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| AArch64AppleInstPrinterValidateMCOperand(MI->getOperand(2), STI, 3) && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (ORR_ZI ZPR32:$Zdn, sve_logical_imm32:$imm) |
| AsmString = "orr $\xFF\x01\x0B, $\xFF\x01\x0B, $\xFF\x03\x04"; |
| break; |
| } |
| return false; |
| case AArch64::ORR_ZZZ: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MI->getOperand(2).getReg() == MI->getOperand(1).getReg() && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (ORR_ZZZ ZPR64:$Zd, ZPR64:$Zn, ZPR64:$Zn) |
| AsmString = "mov $\xFF\x01\x10, $\xFF\x02\x10"; |
| break; |
| } |
| return false; |
| case AArch64::ORRv16i8: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MI->getOperand(2).getReg() == MI->getOperand(1).getReg()) { |
| // (ORRv16i8 V128:$dst, V128:$src, V128:$src) |
| AsmString = "mov.16b $\xFF\x01\x0C, $\xFF\x02\x0C"; |
| break; |
| } |
| return false; |
| case AArch64::ORRv8i8: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::FPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MI->getOperand(2).getReg() == MI->getOperand(1).getReg()) { |
| // (ORRv8i8 V64:$dst, V64:$src, V64:$src) |
| AsmString = "mov.8b $\xFF\x01\x0C, $\xFF\x02\x0C"; |
| break; |
| } |
| return false; |
| case AArch64::PRFB_D_PZI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (PRFB_D_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR64:$Zn, 0) |
| AsmString = "prfb $\xFF\x01\x32, $\xFF\x02\x07, [$\xFF\x03\x10]"; |
| break; |
| } |
| return false; |
| case AArch64::PRFB_PRI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (PRFB_PRI sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "prfb $\xFF\x01\x32, $\xFF\x02\x07, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::PRFB_S_PZI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (PRFB_S_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR32:$Zn, 0) |
| AsmString = "prfb $\xFF\x01\x32, $\xFF\x02\x07, [$\xFF\x03\x0B]"; |
| break; |
| } |
| return false; |
| case AArch64::PRFD_D_PZI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (PRFD_D_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR64:$Zn, 0) |
| AsmString = "prfd $\xFF\x01\x32, $\xFF\x02\x07, [$\xFF\x03\x10]"; |
| break; |
| } |
| return false; |
| case AArch64::PRFD_PRI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (PRFD_PRI sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "prfd $\xFF\x01\x32, $\xFF\x02\x07, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::PRFD_S_PZI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (PRFD_S_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR32:$Zn, 0) |
| AsmString = "prfd $\xFF\x01\x32, $\xFF\x02\x07, [$\xFF\x03\x0B]"; |
| break; |
| } |
| return false; |
| case AArch64::PRFH_D_PZI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (PRFH_D_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR64:$Zn, 0) |
| AsmString = "prfh $\xFF\x01\x32, $\xFF\x02\x07, [$\xFF\x03\x10]"; |
| break; |
| } |
| return false; |
| case AArch64::PRFH_PRI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (PRFH_PRI sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "prfh $\xFF\x01\x32, $\xFF\x02\x07, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::PRFH_S_PZI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (PRFH_S_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR32:$Zn, 0) |
| AsmString = "prfh $\xFF\x01\x32, $\xFF\x02\x07, [$\xFF\x03\x0B]"; |
| break; |
| } |
| return false; |
| case AArch64::PRFMroX: |
| if (MI->getNumOperands() == 5 && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| MI->getOperand(4).isImm() && |
| MI->getOperand(4).getImm() == 0) { |
| // (PRFMroX prfop:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) |
| AsmString = "prfm $\xFF\x01\x33, [$\x02, $\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::PRFMui: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (PRFMui prfop:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "prfm $\xFF\x01\x33, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::PRFUMi: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (PRFUMi prfop:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "prfum $\xFF\x01\x33, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::PRFW_D_PZI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (PRFW_D_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR64:$Zn, 0) |
| AsmString = "prfw $\xFF\x01\x32, $\xFF\x02\x07, [$\xFF\x03\x10]"; |
| break; |
| } |
| return false; |
| case AArch64::PRFW_PRI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (PRFW_PRI sve_prfop:$prfop, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "prfw $\xFF\x01\x32, $\xFF\x02\x07, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::PRFW_S_PZI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (PRFW_S_PZI sve_prfop:$prfop, PPR3bAny:$Pg, ZPR32:$Zn, 0) |
| AsmString = "prfw $\xFF\x01\x32, $\xFF\x02\x07, [$\xFF\x03\x0B]"; |
| break; |
| } |
| return false; |
| case AArch64::PTRUES_B: |
| if (MI->getNumOperands() == 2 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::PPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isImm() && |
| MI->getOperand(1).getImm() == 31 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (PTRUES_B PPR8:$Pd, { 1, 1, 1, 1, 1 }) |
| AsmString = "ptrues $\xFF\x01\x06"; |
| break; |
| } |
| return false; |
| case AArch64::PTRUES_D: |
| if (MI->getNumOperands() == 2 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::PPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isImm() && |
| MI->getOperand(1).getImm() == 31 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (PTRUES_D PPR64:$Pd, { 1, 1, 1, 1, 1 }) |
| AsmString = "ptrues $\xFF\x01\x10"; |
| break; |
| } |
| return false; |
| case AArch64::PTRUES_H: |
| if (MI->getNumOperands() == 2 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::PPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isImm() && |
| MI->getOperand(1).getImm() == 31 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (PTRUES_H PPR16:$Pd, { 1, 1, 1, 1, 1 }) |
| AsmString = "ptrues $\xFF\x01\x09"; |
| break; |
| } |
| return false; |
| case AArch64::PTRUES_S: |
| if (MI->getNumOperands() == 2 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::PPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isImm() && |
| MI->getOperand(1).getImm() == 31 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (PTRUES_S PPR32:$Pd, { 1, 1, 1, 1, 1 }) |
| AsmString = "ptrues $\xFF\x01\x0B"; |
| break; |
| } |
| return false; |
| case AArch64::PTRUE_B: |
| if (MI->getNumOperands() == 2 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::PPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isImm() && |
| MI->getOperand(1).getImm() == 31 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (PTRUE_B PPR8:$Pd, { 1, 1, 1, 1, 1 }) |
| AsmString = "ptrue $\xFF\x01\x06"; |
| break; |
| } |
| return false; |
| case AArch64::PTRUE_D: |
| if (MI->getNumOperands() == 2 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::PPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isImm() && |
| MI->getOperand(1).getImm() == 31 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (PTRUE_D PPR64:$Pd, { 1, 1, 1, 1, 1 }) |
| AsmString = "ptrue $\xFF\x01\x10"; |
| break; |
| } |
| return false; |
| case AArch64::PTRUE_H: |
| if (MI->getNumOperands() == 2 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::PPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isImm() && |
| MI->getOperand(1).getImm() == 31 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (PTRUE_H PPR16:$Pd, { 1, 1, 1, 1, 1 }) |
| AsmString = "ptrue $\xFF\x01\x09"; |
| break; |
| } |
| return false; |
| case AArch64::PTRUE_S: |
| if (MI->getNumOperands() == 2 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::PPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isImm() && |
| MI->getOperand(1).getImm() == 31 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (PTRUE_S PPR32:$Pd, { 1, 1, 1, 1, 1 }) |
| AsmString = "ptrue $\xFF\x01\x0B"; |
| break; |
| } |
| return false; |
| case AArch64::RET: |
| if (MI->getNumOperands() == 1 && |
| MI->getOperand(0).getReg() == AArch64::LR) { |
| // (RET LR) |
| AsmString = "ret"; |
| break; |
| } |
| return false; |
| case AArch64::SBCSWr: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).getReg() == AArch64::WZR && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg())) { |
| // (SBCSWr GPR32:$dst, WZR, GPR32:$src) |
| AsmString = "ngcs $\x01, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64::SBCSXr: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).getReg() == AArch64::XZR && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg())) { |
| // (SBCSXr GPR64:$dst, XZR, GPR64:$src) |
| AsmString = "ngcs $\x01, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64::SBCWr: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).getReg() == AArch64::WZR && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg())) { |
| // (SBCWr GPR32:$dst, WZR, GPR32:$src) |
| AsmString = "ngc $\x01, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64::SBCXr: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).getReg() == AArch64::XZR && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg())) { |
| // (SBCXr GPR64:$dst, XZR, GPR64:$src) |
| AsmString = "ngc $\x01, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64::SBFMWri: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 31) { |
| // (SBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31) |
| AsmString = "asr $\x01, $\x02, $\x03"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 7) { |
| // (SBFMWri GPR32:$dst, GPR32:$src, 0, 7) |
| AsmString = "sxtb $\x01, $\x02"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 15) { |
| // (SBFMWri GPR32:$dst, GPR32:$src, 0, 15) |
| AsmString = "sxth $\x01, $\x02"; |
| break; |
| } |
| return false; |
| case AArch64::SBFMXri: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 63) { |
| // (SBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63) |
| AsmString = "asr $\x01, $\x02, $\x03"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 7) { |
| // (SBFMXri GPR64:$dst, GPR64:$src, 0, 7) |
| AsmString = "sxtb $\x01, $\x02"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 15) { |
| // (SBFMXri GPR64:$dst, GPR64:$src, 0, 15) |
| AsmString = "sxth $\x01, $\x02"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 31) { |
| // (SBFMXri GPR64:$dst, GPR64:$src, 0, 31) |
| AsmString = "sxtw $\x01, $\x02"; |
| break; |
| } |
| return false; |
| case AArch64::SEL_PPPP: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::PPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPRRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::PPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isReg() && |
| MI->getOperand(3).getReg() == MI->getOperand(0).getReg() && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SEL_PPPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPR8:$Pd) |
| AsmString = "mov $\xFF\x01\x06, $\xFF\x02\x07/m, $\xFF\x03\x06"; |
| break; |
| } |
| return false; |
| case AArch64::SEL_ZPZZ_B: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPRRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isReg() && |
| MI->getOperand(3).getReg() == MI->getOperand(0).getReg() && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SEL_ZPZZ_B ZPR8:$Zd, PPRAny:$Pg, ZPR8:$Zn, ZPR8:$Zd) |
| AsmString = "mov $\xFF\x01\x06, $\xFF\x02\x07/m, $\xFF\x03\x06"; |
| break; |
| } |
| return false; |
| case AArch64::SEL_ZPZZ_D: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPRRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isReg() && |
| MI->getOperand(3).getReg() == MI->getOperand(0).getReg() && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SEL_ZPZZ_D ZPR64:$Zd, PPRAny:$Pg, ZPR64:$Zn, ZPR64:$Zd) |
| AsmString = "mov $\xFF\x01\x10, $\xFF\x02\x07/m, $\xFF\x03\x10"; |
| break; |
| } |
| return false; |
| case AArch64::SEL_ZPZZ_H: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPRRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isReg() && |
| MI->getOperand(3).getReg() == MI->getOperand(0).getReg() && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SEL_ZPZZ_H ZPR16:$Zd, PPRAny:$Pg, ZPR16:$Zn, ZPR16:$Zd) |
| AsmString = "mov $\xFF\x01\x09, $\xFF\x02\x07/m, $\xFF\x03\x09"; |
| break; |
| } |
| return false; |
| case AArch64::SEL_ZPZZ_S: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPRRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isReg() && |
| MI->getOperand(3).getReg() == MI->getOperand(0).getReg() && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SEL_ZPZZ_S ZPR32:$Zd, PPRAny:$Pg, ZPR32:$Zn, ZPR32:$Zd) |
| AsmString = "mov $\xFF\x01\x0B, $\xFF\x02\x07/m, $\xFF\x03\x0B"; |
| break; |
| } |
| return false; |
| case AArch64::SMADDLrrr: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR) { |
| // (SMADDLrrr GPR64:$dst, GPR32:$src1, GPR32:$src2, XZR) |
| AsmString = "smull $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64::SMSUBLrrr: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR) { |
| // (SMSUBLrrr GPR64:$dst, GPR32:$src1, GPR32:$src2, XZR) |
| AsmString = "smnegl $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64::SQDECB_XPiI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SQDECB_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "sqdecb $\x01"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SQDECB_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) |
| AsmString = "sqdecb $\x01, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::SQDECB_XPiWdI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SQDECB_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "sqdecb $\x01, $\xFF\x02\x34"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SQDECB_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) |
| AsmString = "sqdecb $\x01, $\xFF\x02\x34, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::SQDECD_XPiI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SQDECD_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "sqdecd $\x01"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SQDECD_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) |
| AsmString = "sqdecd $\x01, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::SQDECD_XPiWdI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SQDECD_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "sqdecd $\x01, $\xFF\x02\x34"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SQDECD_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) |
| AsmString = "sqdecd $\x01, $\xFF\x02\x34, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::SQDECD_ZPiI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SQDECD_ZPiI ZPR64:$Zdn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "sqdecd $\xFF\x01\x10"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SQDECD_ZPiI ZPR64:$Zdn, sve_pred_enum:$pattern, 1) |
| AsmString = "sqdecd $\xFF\x01\x10, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::SQDECH_XPiI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SQDECH_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "sqdech $\x01"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SQDECH_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) |
| AsmString = "sqdech $\x01, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::SQDECH_XPiWdI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SQDECH_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "sqdech $\x01, $\xFF\x02\x34"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SQDECH_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) |
| AsmString = "sqdech $\x01, $\xFF\x02\x34, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::SQDECH_ZPiI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SQDECH_ZPiI ZPR16:$Zdn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "sqdech $\xFF\x01\x09"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SQDECH_ZPiI ZPR16:$Zdn, sve_pred_enum:$pattern, 1) |
| AsmString = "sqdech $\xFF\x01\x09, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::SQDECW_XPiI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SQDECW_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "sqdecw $\x01"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SQDECW_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) |
| AsmString = "sqdecw $\x01, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::SQDECW_XPiWdI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SQDECW_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "sqdecw $\x01, $\xFF\x02\x34"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SQDECW_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) |
| AsmString = "sqdecw $\x01, $\xFF\x02\x34, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::SQDECW_ZPiI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SQDECW_ZPiI ZPR32:$Zdn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "sqdecw $\xFF\x01\x0B"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SQDECW_ZPiI ZPR32:$Zdn, sve_pred_enum:$pattern, 1) |
| AsmString = "sqdecw $\xFF\x01\x0B, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::SQINCB_XPiI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SQINCB_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "sqincb $\x01"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SQINCB_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) |
| AsmString = "sqincb $\x01, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::SQINCB_XPiWdI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SQINCB_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "sqincb $\x01, $\xFF\x02\x34"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SQINCB_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) |
| AsmString = "sqincb $\x01, $\xFF\x02\x34, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::SQINCD_XPiI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SQINCD_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "sqincd $\x01"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SQINCD_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) |
| AsmString = "sqincd $\x01, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::SQINCD_XPiWdI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SQINCD_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "sqincd $\x01, $\xFF\x02\x34"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SQINCD_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) |
| AsmString = "sqincd $\x01, $\xFF\x02\x34, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::SQINCD_ZPiI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SQINCD_ZPiI ZPR64:$Zdn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "sqincd $\xFF\x01\x10"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SQINCD_ZPiI ZPR64:$Zdn, sve_pred_enum:$pattern, 1) |
| AsmString = "sqincd $\xFF\x01\x10, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::SQINCH_XPiI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SQINCH_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "sqinch $\x01"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SQINCH_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) |
| AsmString = "sqinch $\x01, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::SQINCH_XPiWdI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SQINCH_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "sqinch $\x01, $\xFF\x02\x34"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SQINCH_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) |
| AsmString = "sqinch $\x01, $\xFF\x02\x34, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::SQINCH_ZPiI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SQINCH_ZPiI ZPR16:$Zdn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "sqinch $\xFF\x01\x09"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SQINCH_ZPiI ZPR16:$Zdn, sve_pred_enum:$pattern, 1) |
| AsmString = "sqinch $\xFF\x01\x09, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::SQINCW_XPiI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SQINCW_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "sqincw $\x01"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SQINCW_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) |
| AsmString = "sqincw $\x01, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::SQINCW_XPiWdI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SQINCW_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "sqincw $\x01, $\xFF\x02\x34"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SQINCW_XPiWdI GPR64z:$Rd, GPR64as32:$Rn, sve_pred_enum:$pattern, 1) |
| AsmString = "sqincw $\x01, $\xFF\x02\x34, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::SQINCW_ZPiI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SQINCW_ZPiI ZPR32:$Zdn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "sqincw $\xFF\x01\x0B"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SQINCW_ZPiI ZPR32:$Zdn, sve_pred_enum:$pattern, 1) |
| AsmString = "sqincw $\xFF\x01\x0B, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::SST1B_D_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SST1B_D_IMM Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) |
| AsmString = "st1b $\xFF\x01\x20, $\xFF\x02\x07, [$\xFF\x03\x10]"; |
| break; |
| } |
| return false; |
| case AArch64::SST1B_S_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SST1B_S_IMM Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) |
| AsmString = "st1b $\xFF\x01\x21, $\xFF\x02\x07, [$\xFF\x03\x0B]"; |
| break; |
| } |
| return false; |
| case AArch64::SST1D_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SST1D_IMM Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) |
| AsmString = "st1d $\xFF\x01\x20, $\xFF\x02\x07, [$\xFF\x03\x10]"; |
| break; |
| } |
| return false; |
| case AArch64::SST1H_D_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SST1H_D_IMM Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) |
| AsmString = "st1h $\xFF\x01\x20, $\xFF\x02\x07, [$\xFF\x03\x10]"; |
| break; |
| } |
| return false; |
| case AArch64::SST1H_S_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SST1H_S_IMM Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) |
| AsmString = "st1h $\xFF\x01\x21, $\xFF\x02\x07, [$\xFF\x03\x0B]"; |
| break; |
| } |
| return false; |
| case AArch64::SST1W_D_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SST1W_D_IMM Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0) |
| AsmString = "st1w $\xFF\x01\x20, $\xFF\x02\x07, [$\xFF\x03\x10]"; |
| break; |
| } |
| return false; |
| case AArch64::SST1W_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (SST1W_IMM Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0) |
| AsmString = "st1w $\xFF\x01\x21, $\xFF\x02\x07, [$\xFF\x03\x0B]"; |
| break; |
| } |
| return false; |
| case AArch64::ST1B_D_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (ST1B_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "st1b $\xFF\x01\x20, $\xFF\x02\x07, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::ST1B_H_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (ST1B_H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "st1b $\xFF\x01\x23, $\xFF\x02\x07, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::ST1B_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (ST1B_IMM Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "st1b $\xFF\x01\x24, $\xFF\x02\x07, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::ST1B_S_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (ST1B_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "st1b $\xFF\x01\x21, $\xFF\x02\x07, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::ST1D_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (ST1D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "st1d $\xFF\x01\x20, $\xFF\x02\x07, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::ST1Fourv16b_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST1Fourv16b_POST GPR64sp:$Rn, VecListFour16b:$Vt, XZR) |
| AsmString = "st1 $\xFF\x02\x25, [$\x01], #64"; |
| break; |
| } |
| return false; |
| case AArch64::ST1Fourv1d_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDDDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST1Fourv1d_POST GPR64sp:$Rn, VecListFour1d:$Vt, XZR) |
| AsmString = "st1 $\xFF\x02\x26, [$\x01], #32"; |
| break; |
| } |
| return false; |
| case AArch64::ST1Fourv2d_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST1Fourv2d_POST GPR64sp:$Rn, VecListFour2d:$Vt, XZR) |
| AsmString = "st1 $\xFF\x02\x27, [$\x01], #64"; |
| break; |
| } |
| return false; |
| case AArch64::ST1Fourv2s_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDDDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST1Fourv2s_POST GPR64sp:$Rn, VecListFour2s:$Vt, XZR) |
| AsmString = "st1 $\xFF\x02\x28, [$\x01], #32"; |
| break; |
| } |
| return false; |
| case AArch64::ST1Fourv4h_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDDDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST1Fourv4h_POST GPR64sp:$Rn, VecListFour4h:$Vt, XZR) |
| AsmString = "st1 $\xFF\x02\x29, [$\x01], #32"; |
| break; |
| } |
| return false; |
| case AArch64::ST1Fourv4s_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST1Fourv4s_POST GPR64sp:$Rn, VecListFour4s:$Vt, XZR) |
| AsmString = "st1 $\xFF\x02\x2A, [$\x01], #64"; |
| break; |
| } |
| return false; |
| case AArch64::ST1Fourv8b_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDDDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST1Fourv8b_POST GPR64sp:$Rn, VecListFour8b:$Vt, XZR) |
| AsmString = "st1 $\xFF\x02\x2B, [$\x01], #32"; |
| break; |
| } |
| return false; |
| case AArch64::ST1Fourv8h_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST1Fourv8h_POST GPR64sp:$Rn, VecListFour8h:$Vt, XZR) |
| AsmString = "st1 $\xFF\x02\x2C, [$\x01], #64"; |
| break; |
| } |
| return false; |
| case AArch64::ST1H_D_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (ST1H_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "st1h $\xFF\x01\x20, $\xFF\x02\x07, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::ST1H_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (ST1H_IMM Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "st1h $\xFF\x01\x23, $\xFF\x02\x07, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::ST1H_S_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (ST1H_S_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "st1h $\xFF\x01\x21, $\xFF\x02\x07, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::ST1Onev16b_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST1Onev16b_POST GPR64sp:$Rn, VecListOne16b:$Vt, XZR) |
| AsmString = "st1 $\xFF\x02\x25, [$\x01], #16"; |
| break; |
| } |
| return false; |
| case AArch64::ST1Onev1d_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::FPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST1Onev1d_POST GPR64sp:$Rn, VecListOne1d:$Vt, XZR) |
| AsmString = "st1 $\xFF\x02\x26, [$\x01], #8"; |
| break; |
| } |
| return false; |
| case AArch64::ST1Onev2d_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST1Onev2d_POST GPR64sp:$Rn, VecListOne2d:$Vt, XZR) |
| AsmString = "st1 $\xFF\x02\x27, [$\x01], #16"; |
| break; |
| } |
| return false; |
| case AArch64::ST1Onev2s_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::FPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST1Onev2s_POST GPR64sp:$Rn, VecListOne2s:$Vt, XZR) |
| AsmString = "st1 $\xFF\x02\x28, [$\x01], #8"; |
| break; |
| } |
| return false; |
| case AArch64::ST1Onev4h_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::FPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST1Onev4h_POST GPR64sp:$Rn, VecListOne4h:$Vt, XZR) |
| AsmString = "st1 $\xFF\x02\x29, [$\x01], #8"; |
| break; |
| } |
| return false; |
| case AArch64::ST1Onev4s_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST1Onev4s_POST GPR64sp:$Rn, VecListOne4s:$Vt, XZR) |
| AsmString = "st1 $\xFF\x02\x2A, [$\x01], #16"; |
| break; |
| } |
| return false; |
| case AArch64::ST1Onev8b_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::FPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST1Onev8b_POST GPR64sp:$Rn, VecListOne8b:$Vt, XZR) |
| AsmString = "st1 $\xFF\x02\x2B, [$\x01], #8"; |
| break; |
| } |
| return false; |
| case AArch64::ST1Onev8h_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST1Onev8h_POST GPR64sp:$Rn, VecListOne8h:$Vt, XZR) |
| AsmString = "st1 $\xFF\x02\x2C, [$\x01], #16"; |
| break; |
| } |
| return false; |
| case AArch64::ST1Threev16b_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST1Threev16b_POST GPR64sp:$Rn, VecListThree16b:$Vt, XZR) |
| AsmString = "st1 $\xFF\x02\x25, [$\x01], #48"; |
| break; |
| } |
| return false; |
| case AArch64::ST1Threev1d_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST1Threev1d_POST GPR64sp:$Rn, VecListThree1d:$Vt, XZR) |
| AsmString = "st1 $\xFF\x02\x26, [$\x01], #24"; |
| break; |
| } |
| return false; |
| case AArch64::ST1Threev2d_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST1Threev2d_POST GPR64sp:$Rn, VecListThree2d:$Vt, XZR) |
| AsmString = "st1 $\xFF\x02\x27, [$\x01], #48"; |
| break; |
| } |
| return false; |
| case AArch64::ST1Threev2s_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST1Threev2s_POST GPR64sp:$Rn, VecListThree2s:$Vt, XZR) |
| AsmString = "st1 $\xFF\x02\x28, [$\x01], #24"; |
| break; |
| } |
| return false; |
| case AArch64::ST1Threev4h_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST1Threev4h_POST GPR64sp:$Rn, VecListThree4h:$Vt, XZR) |
| AsmString = "st1 $\xFF\x02\x29, [$\x01], #24"; |
| break; |
| } |
| return false; |
| case AArch64::ST1Threev4s_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST1Threev4s_POST GPR64sp:$Rn, VecListThree4s:$Vt, XZR) |
| AsmString = "st1 $\xFF\x02\x2A, [$\x01], #48"; |
| break; |
| } |
| return false; |
| case AArch64::ST1Threev8b_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST1Threev8b_POST GPR64sp:$Rn, VecListThree8b:$Vt, XZR) |
| AsmString = "st1 $\xFF\x02\x2B, [$\x01], #24"; |
| break; |
| } |
| return false; |
| case AArch64::ST1Threev8h_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST1Threev8h_POST GPR64sp:$Rn, VecListThree8h:$Vt, XZR) |
| AsmString = "st1 $\xFF\x02\x2C, [$\x01], #48"; |
| break; |
| } |
| return false; |
| case AArch64::ST1Twov16b_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST1Twov16b_POST GPR64sp:$Rn, VecListTwo16b:$Vt, XZR) |
| AsmString = "st1 $\xFF\x02\x25, [$\x01], #32"; |
| break; |
| } |
| return false; |
| case AArch64::ST1Twov1d_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST1Twov1d_POST GPR64sp:$Rn, VecListTwo1d:$Vt, XZR) |
| AsmString = "st1 $\xFF\x02\x26, [$\x01], #16"; |
| break; |
| } |
| return false; |
| case AArch64::ST1Twov2d_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST1Twov2d_POST GPR64sp:$Rn, VecListTwo2d:$Vt, XZR) |
| AsmString = "st1 $\xFF\x02\x27, [$\x01], #32"; |
| break; |
| } |
| return false; |
| case AArch64::ST1Twov2s_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST1Twov2s_POST GPR64sp:$Rn, VecListTwo2s:$Vt, XZR) |
| AsmString = "st1 $\xFF\x02\x28, [$\x01], #16"; |
| break; |
| } |
| return false; |
| case AArch64::ST1Twov4h_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST1Twov4h_POST GPR64sp:$Rn, VecListTwo4h:$Vt, XZR) |
| AsmString = "st1 $\xFF\x02\x29, [$\x01], #16"; |
| break; |
| } |
| return false; |
| case AArch64::ST1Twov4s_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST1Twov4s_POST GPR64sp:$Rn, VecListTwo4s:$Vt, XZR) |
| AsmString = "st1 $\xFF\x02\x2A, [$\x01], #32"; |
| break; |
| } |
| return false; |
| case AArch64::ST1Twov8b_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST1Twov8b_POST GPR64sp:$Rn, VecListTwo8b:$Vt, XZR) |
| AsmString = "st1 $\xFF\x02\x2B, [$\x01], #16"; |
| break; |
| } |
| return false; |
| case AArch64::ST1Twov8h_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST1Twov8h_POST GPR64sp:$Rn, VecListTwo8h:$Vt, XZR) |
| AsmString = "st1 $\xFF\x02\x2C, [$\x01], #32"; |
| break; |
| } |
| return false; |
| case AArch64::ST1W_D_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (ST1W_D_IMM Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "st1w $\xFF\x01\x20, $\xFF\x02\x07, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::ST1W_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (ST1W_IMM Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "st1w $\xFF\x01\x21, $\xFF\x02\x07, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::ST1i16_POST: |
| if (MI->getNumOperands() == 5 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(4).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST1i16_POST GPR64sp:$Rn, VecListOneh:$Vt, VectorIndexH:$idx, XZR) |
| AsmString = "st1 $\xFF\x02\x2D$\xFF\x03\x19, [$\x01], #2"; |
| break; |
| } |
| return false; |
| case AArch64::ST1i32_POST: |
| if (MI->getNumOperands() == 5 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(4).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST1i32_POST GPR64sp:$Rn, VecListOnes:$Vt, VectorIndexS:$idx, XZR) |
| AsmString = "st1 $\xFF\x02\x2E$\xFF\x03\x19, [$\x01], #4"; |
| break; |
| } |
| return false; |
| case AArch64::ST1i64_POST: |
| if (MI->getNumOperands() == 5 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(4).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST1i64_POST GPR64sp:$Rn, VecListOned:$Vt, VectorIndexD:$idx, XZR) |
| AsmString = "st1 $\xFF\x02\x2F$\xFF\x03\x19, [$\x01], #8"; |
| break; |
| } |
| return false; |
| case AArch64::ST1i8_POST: |
| if (MI->getNumOperands() == 5 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(4).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST1i8_POST GPR64sp:$Rn, VecListOneb:$Vt, VectorIndexB:$idx, XZR) |
| AsmString = "st1 $\xFF\x02\x30$\xFF\x03\x19, [$\x01], #1"; |
| break; |
| } |
| return false; |
| case AArch64::ST2B_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPR2RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (ST2B_IMM ZZ_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "st2b $\xFF\x01\x24, $\xFF\x02\x07, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::ST2D_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPR2RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (ST2D_IMM ZZ_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "st2d $\xFF\x01\x20, $\xFF\x02\x07, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::ST2H_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPR2RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (ST2H_IMM ZZ_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "st2h $\xFF\x01\x23, $\xFF\x02\x07, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::ST2Twov16b_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST2Twov16b_POST GPR64sp:$Rn, VecListTwo16b:$Vt, XZR) |
| AsmString = "st2 $\xFF\x02\x25, [$\x01], #32"; |
| break; |
| } |
| return false; |
| case AArch64::ST2Twov2d_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST2Twov2d_POST GPR64sp:$Rn, VecListTwo2d:$Vt, XZR) |
| AsmString = "st2 $\xFF\x02\x27, [$\x01], #32"; |
| break; |
| } |
| return false; |
| case AArch64::ST2Twov2s_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST2Twov2s_POST GPR64sp:$Rn, VecListTwo2s:$Vt, XZR) |
| AsmString = "st2 $\xFF\x02\x28, [$\x01], #16"; |
| break; |
| } |
| return false; |
| case AArch64::ST2Twov4h_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST2Twov4h_POST GPR64sp:$Rn, VecListTwo4h:$Vt, XZR) |
| AsmString = "st2 $\xFF\x02\x29, [$\x01], #16"; |
| break; |
| } |
| return false; |
| case AArch64::ST2Twov4s_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST2Twov4s_POST GPR64sp:$Rn, VecListTwo4s:$Vt, XZR) |
| AsmString = "st2 $\xFF\x02\x2A, [$\x01], #32"; |
| break; |
| } |
| return false; |
| case AArch64::ST2Twov8b_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST2Twov8b_POST GPR64sp:$Rn, VecListTwo8b:$Vt, XZR) |
| AsmString = "st2 $\xFF\x02\x2B, [$\x01], #16"; |
| break; |
| } |
| return false; |
| case AArch64::ST2Twov8h_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST2Twov8h_POST GPR64sp:$Rn, VecListTwo8h:$Vt, XZR) |
| AsmString = "st2 $\xFF\x02\x2C, [$\x01], #32"; |
| break; |
| } |
| return false; |
| case AArch64::ST2W_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPR2RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (ST2W_IMM ZZ_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "st2w $\xFF\x01\x21, $\xFF\x02\x07, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::ST2i16_POST: |
| if (MI->getNumOperands() == 5 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(4).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST2i16_POST GPR64sp:$Rn, VecListTwoh:$Vt, VectorIndexH:$idx, XZR) |
| AsmString = "st2 $\xFF\x02\x2D$\xFF\x03\x19, [$\x01], #4"; |
| break; |
| } |
| return false; |
| case AArch64::ST2i32_POST: |
| if (MI->getNumOperands() == 5 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(4).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST2i32_POST GPR64sp:$Rn, VecListTwos:$Vt, VectorIndexS:$idx, XZR) |
| AsmString = "st2 $\xFF\x02\x2E$\xFF\x03\x19, [$\x01], #8"; |
| break; |
| } |
| return false; |
| case AArch64::ST2i64_POST: |
| if (MI->getNumOperands() == 5 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(4).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST2i64_POST GPR64sp:$Rn, VecListTwod:$Vt, VectorIndexD:$idx, XZR) |
| AsmString = "st2 $\xFF\x02\x2F$\xFF\x03\x19, [$\x01], #16"; |
| break; |
| } |
| return false; |
| case AArch64::ST2i8_POST: |
| if (MI->getNumOperands() == 5 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(4).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST2i8_POST GPR64sp:$Rn, VecListTwob:$Vt, VectorIndexB:$idx, XZR) |
| AsmString = "st2 $\xFF\x02\x30$\xFF\x03\x19, [$\x01], #2"; |
| break; |
| } |
| return false; |
| case AArch64::ST3B_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPR3RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (ST3B_IMM ZZZ_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "st3b $\xFF\x01\x24, $\xFF\x02\x07, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::ST3D_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPR3RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (ST3D_IMM ZZZ_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "st3d $\xFF\x01\x20, $\xFF\x02\x07, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::ST3H_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPR3RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (ST3H_IMM ZZZ_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "st3h $\xFF\x01\x23, $\xFF\x02\x07, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::ST3Threev16b_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST3Threev16b_POST GPR64sp:$Rn, VecListThree16b:$Vt, XZR) |
| AsmString = "st3 $\xFF\x02\x25, [$\x01], #48"; |
| break; |
| } |
| return false; |
| case AArch64::ST3Threev2d_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST3Threev2d_POST GPR64sp:$Rn, VecListThree2d:$Vt, XZR) |
| AsmString = "st3 $\xFF\x02\x27, [$\x01], #48"; |
| break; |
| } |
| return false; |
| case AArch64::ST3Threev2s_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST3Threev2s_POST GPR64sp:$Rn, VecListThree2s:$Vt, XZR) |
| AsmString = "st3 $\xFF\x02\x28, [$\x01], #24"; |
| break; |
| } |
| return false; |
| case AArch64::ST3Threev4h_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST3Threev4h_POST GPR64sp:$Rn, VecListThree4h:$Vt, XZR) |
| AsmString = "st3 $\xFF\x02\x29, [$\x01], #24"; |
| break; |
| } |
| return false; |
| case AArch64::ST3Threev4s_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST3Threev4s_POST GPR64sp:$Rn, VecListThree4s:$Vt, XZR) |
| AsmString = "st3 $\xFF\x02\x2A, [$\x01], #48"; |
| break; |
| } |
| return false; |
| case AArch64::ST3Threev8b_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST3Threev8b_POST GPR64sp:$Rn, VecListThree8b:$Vt, XZR) |
| AsmString = "st3 $\xFF\x02\x2B, [$\x01], #24"; |
| break; |
| } |
| return false; |
| case AArch64::ST3Threev8h_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST3Threev8h_POST GPR64sp:$Rn, VecListThree8h:$Vt, XZR) |
| AsmString = "st3 $\xFF\x02\x2C, [$\x01], #48"; |
| break; |
| } |
| return false; |
| case AArch64::ST3W_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPR3RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (ST3W_IMM ZZZ_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "st3w $\xFF\x01\x21, $\xFF\x02\x07, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::ST3i16_POST: |
| if (MI->getNumOperands() == 5 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(4).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST3i16_POST GPR64sp:$Rn, VecListThreeh:$Vt, VectorIndexH:$idx, XZR) |
| AsmString = "st3 $\xFF\x02\x2D$\xFF\x03\x19, [$\x01], #6"; |
| break; |
| } |
| return false; |
| case AArch64::ST3i32_POST: |
| if (MI->getNumOperands() == 5 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(4).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST3i32_POST GPR64sp:$Rn, VecListThrees:$Vt, VectorIndexS:$idx, XZR) |
| AsmString = "st3 $\xFF\x02\x2E$\xFF\x03\x19, [$\x01], #12"; |
| break; |
| } |
| return false; |
| case AArch64::ST3i64_POST: |
| if (MI->getNumOperands() == 5 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(4).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST3i64_POST GPR64sp:$Rn, VecListThreed:$Vt, VectorIndexD:$idx, XZR) |
| AsmString = "st3 $\xFF\x02\x2F$\xFF\x03\x19, [$\x01], #24"; |
| break; |
| } |
| return false; |
| case AArch64::ST3i8_POST: |
| if (MI->getNumOperands() == 5 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(4).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST3i8_POST GPR64sp:$Rn, VecListThreeb:$Vt, VectorIndexB:$idx, XZR) |
| AsmString = "st3 $\xFF\x02\x30$\xFF\x03\x19, [$\x01], #3"; |
| break; |
| } |
| return false; |
| case AArch64::ST4B_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPR4RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (ST4B_IMM ZZZZ_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "st4b $\xFF\x01\x24, $\xFF\x02\x07, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::ST4D_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPR4RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (ST4D_IMM ZZZZ_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "st4d $\xFF\x01\x20, $\xFF\x02\x07, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::ST4Fourv16b_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST4Fourv16b_POST GPR64sp:$Rn, VecListFour16b:$Vt, XZR) |
| AsmString = "st4 $\xFF\x02\x25, [$\x01], #64"; |
| break; |
| } |
| return false; |
| case AArch64::ST4Fourv2d_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST4Fourv2d_POST GPR64sp:$Rn, VecListFour2d:$Vt, XZR) |
| AsmString = "st4 $\xFF\x02\x27, [$\x01], #64"; |
| break; |
| } |
| return false; |
| case AArch64::ST4Fourv2s_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDDDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST4Fourv2s_POST GPR64sp:$Rn, VecListFour2s:$Vt, XZR) |
| AsmString = "st4 $\xFF\x02\x28, [$\x01], #32"; |
| break; |
| } |
| return false; |
| case AArch64::ST4Fourv4h_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDDDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST4Fourv4h_POST GPR64sp:$Rn, VecListFour4h:$Vt, XZR) |
| AsmString = "st4 $\xFF\x02\x29, [$\x01], #32"; |
| break; |
| } |
| return false; |
| case AArch64::ST4Fourv4s_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST4Fourv4s_POST GPR64sp:$Rn, VecListFour4s:$Vt, XZR) |
| AsmString = "st4 $\xFF\x02\x2A, [$\x01], #64"; |
| break; |
| } |
| return false; |
| case AArch64::ST4Fourv8b_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::DDDDRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST4Fourv8b_POST GPR64sp:$Rn, VecListFour8b:$Vt, XZR) |
| AsmString = "st4 $\xFF\x02\x2B, [$\x01], #32"; |
| break; |
| } |
| return false; |
| case AArch64::ST4Fourv8h_POST: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST4Fourv8h_POST GPR64sp:$Rn, VecListFour8h:$Vt, XZR) |
| AsmString = "st4 $\xFF\x02\x2C, [$\x01], #64"; |
| break; |
| } |
| return false; |
| case AArch64::ST4H_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPR4RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (ST4H_IMM ZZZZ_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "st4h $\xFF\x01\x23, $\xFF\x02\x07, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::ST4W_IMM: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPR4RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (ST4W_IMM ZZZZ_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "st4w $\xFF\x01\x21, $\xFF\x02\x07, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::ST4i16_POST: |
| if (MI->getNumOperands() == 5 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(4).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST4i16_POST GPR64sp:$Rn, VecListFourh:$Vt, VectorIndexH:$idx, XZR) |
| AsmString = "st4 $\xFF\x02\x2D$\xFF\x03\x19, [$\x01], #8"; |
| break; |
| } |
| return false; |
| case AArch64::ST4i32_POST: |
| if (MI->getNumOperands() == 5 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(4).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST4i32_POST GPR64sp:$Rn, VecListFours:$Vt, VectorIndexS:$idx, XZR) |
| AsmString = "st4 $\xFF\x02\x2E$\xFF\x03\x19, [$\x01], #16"; |
| break; |
| } |
| return false; |
| case AArch64::ST4i64_POST: |
| if (MI->getNumOperands() == 5 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(4).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST4i64_POST GPR64sp:$Rn, VecListFourd:$Vt, VectorIndexD:$idx, XZR) |
| AsmString = "st4 $\xFF\x02\x2F$\xFF\x03\x19, [$\x01], #32"; |
| break; |
| } |
| return false; |
| case AArch64::ST4i8_POST: |
| if (MI->getNumOperands() == 5 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::QQQQRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(4).getReg() == AArch64::XZR && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (ST4i8_POST GPR64sp:$Rn, VecListFourb:$Vt, VectorIndexB:$idx, XZR) |
| AsmString = "st4 $\xFF\x02\x30$\xFF\x03\x19, [$\x01], #4"; |
| break; |
| } |
| return false; |
| case AArch64::STLURBi: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::HasV8_4aOps]) { |
| // (STLURBi GPR32:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "stlurb $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::STLURHi: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::HasV8_4aOps]) { |
| // (STLURHi GPR32:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "stlurh $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::STLURWi: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::HasV8_4aOps]) { |
| // (STLURWi GPR32:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "stlur $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::STLURXi: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::HasV8_4aOps]) { |
| // (STLURXi GPR64:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "stlur $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::STNPDi: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::FPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (STNPDi FPR64Op:$Rt, FPR64Op:$Rt2, GPR64sp:$Rn, 0) |
| AsmString = "stnp $\x01, $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::STNPQi: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (STNPQi FPR128Op:$Rt, FPR128Op:$Rt2, GPR64sp:$Rn, 0) |
| AsmString = "stnp $\x01, $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::STNPSi: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::FPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (STNPSi FPR32Op:$Rt, FPR32Op:$Rt2, GPR64sp:$Rn, 0) |
| AsmString = "stnp $\x01, $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::STNPWi: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (STNPWi GPR32z:$Rt, GPR32z:$Rt2, GPR64sp:$Rn, 0) |
| AsmString = "stnp $\x01, $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::STNPXi: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (STNPXi GPR64z:$Rt, GPR64z:$Rt2, GPR64sp:$Rn, 0) |
| AsmString = "stnp $\x01, $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::STNT1B_ZRI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (STNT1B_ZRI Z_b:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "stnt1b $\xFF\x01\x24, $\xFF\x02\x07, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::STNT1D_ZRI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (STNT1D_ZRI Z_d:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "stnt1d $\xFF\x01\x20, $\xFF\x02\x07, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::STNT1H_ZRI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (STNT1H_ZRI Z_h:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "stnt1h $\xFF\x01\x23, $\xFF\x02\x07, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::STNT1W_ZRI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::PPR_3bRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (STNT1W_ZRI Z_s:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, 0) |
| AsmString = "stnt1w $\xFF\x01\x21, $\xFF\x02\x07, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::STPDi: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::FPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (STPDi FPR64Op:$Rt, FPR64Op:$Rt2, GPR64sp:$Rn, 0) |
| AsmString = "stp $\x01, $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::STPQi: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (STPQi FPR128Op:$Rt, FPR128Op:$Rt2, GPR64sp:$Rn, 0) |
| AsmString = "stp $\x01, $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::STPSi: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::FPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (STPSi FPR32Op:$Rt, FPR32Op:$Rt2, GPR64sp:$Rn, 0) |
| AsmString = "stp $\x01, $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::STPWi: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (STPWi GPR32z:$Rt, GPR32z:$Rt2, GPR64sp:$Rn, 0) |
| AsmString = "stp $\x01, $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::STPXi: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (STPXi GPR64z:$Rt, GPR64z:$Rt2, GPR64sp:$Rn, 0) |
| AsmString = "stp $\x01, $\x02, [$\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::STRBBroX: |
| if (MI->getNumOperands() == 5 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| MI->getOperand(4).isImm() && |
| MI->getOperand(4).getImm() == 0) { |
| // (STRBBroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) |
| AsmString = "strb $\x01, [$\x02, $\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::STRBBui: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (STRBBui GPR32z:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "strb $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::STRBroX: |
| if (MI->getNumOperands() == 5 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR8RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| MI->getOperand(4).isImm() && |
| MI->getOperand(4).getImm() == 0) { |
| // (STRBroX FPR8Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) |
| AsmString = "str $\x01, [$\x02, $\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::STRBui: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR8RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (STRBui FPR8Op:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "str $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::STRDroX: |
| if (MI->getNumOperands() == 5 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| MI->getOperand(4).isImm() && |
| MI->getOperand(4).getImm() == 0) { |
| // (STRDroX FPR64Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) |
| AsmString = "str $\x01, [$\x02, $\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::STRDui: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (STRDui FPR64Op:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "str $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::STRHHroX: |
| if (MI->getNumOperands() == 5 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| MI->getOperand(4).isImm() && |
| MI->getOperand(4).getImm() == 0) { |
| // (STRHHroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) |
| AsmString = "strh $\x01, [$\x02, $\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::STRHHui: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (STRHHui GPR32z:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "strh $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::STRHroX: |
| if (MI->getNumOperands() == 5 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR16RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| MI->getOperand(4).isImm() && |
| MI->getOperand(4).getImm() == 0) { |
| // (STRHroX FPR16Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) |
| AsmString = "str $\x01, [$\x02, $\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::STRHui: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR16RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (STRHui FPR16Op:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "str $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::STRQroX: |
| if (MI->getNumOperands() == 5 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| MI->getOperand(4).isImm() && |
| MI->getOperand(4).getImm() == 0) { |
| // (STRQroX FPR128Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) |
| AsmString = "str $\x01, [$\x02, $\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::STRQui: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (STRQui FPR128Op:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "str $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::STRSroX: |
| if (MI->getNumOperands() == 5 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| MI->getOperand(4).isImm() && |
| MI->getOperand(4).getImm() == 0) { |
| // (STRSroX FPR32Op:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) |
| AsmString = "str $\x01, [$\x02, $\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::STRSui: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (STRSui FPR32Op:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "str $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::STRWroX: |
| if (MI->getNumOperands() == 5 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| MI->getOperand(4).isImm() && |
| MI->getOperand(4).getImm() == 0) { |
| // (STRWroX GPR32:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) |
| AsmString = "str $\x01, [$\x02, $\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::STRWui: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (STRWui GPR32z:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "str $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::STRXroX: |
| if (MI->getNumOperands() == 5 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0 && |
| MI->getOperand(4).isImm() && |
| MI->getOperand(4).getImm() == 0) { |
| // (STRXroX GPR64:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0) |
| AsmString = "str $\x01, [$\x02, $\x03]"; |
| break; |
| } |
| return false; |
| case AArch64::STRXui: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (STRXui GPR64z:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "str $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::STR_PXI: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::PPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (STR_PXI PPRAny:$Pt, GPR64sp:$Rn, 0) |
| AsmString = "str $\xFF\x01\x07, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::STR_ZXI: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (STR_ZXI ZPRAny:$Zt, GPR64sp:$Rn, 0) |
| AsmString = "str $\xFF\x01\x07, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::STTRBi: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (STTRBi GPR32:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "sttrb $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::STTRHi: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (STTRHi GPR32:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "sttrh $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::STTRWi: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (STTRWi GPR32:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "sttr $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::STTRXi: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (STTRXi GPR64:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "sttr $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::STURBBi: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (STURBBi GPR32z:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "sturb $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::STURBi: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR8RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (STURBi FPR8Op:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "stur $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::STURDi: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (STURDi FPR64Op:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "stur $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::STURHHi: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (STURHHi GPR32z:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "sturh $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::STURHi: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR16RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (STURHi FPR16Op:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "stur $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::STURQi: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (STURQi FPR128Op:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "stur $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::STURSi: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::FPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (STURSi FPR32Op:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "stur $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::STURWi: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (STURWi GPR32z:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "stur $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::STURXi: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0) { |
| // (STURXi GPR64z:$Rt, GPR64sp:$Rn, 0) |
| AsmString = "stur $\x01, [$\x02]"; |
| break; |
| } |
| return false; |
| case AArch64::SUBSWri: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32spRegClassID).contains(MI->getOperand(1).getReg())) { |
| // (SUBSWri WZR, GPR32sp:$src, addsub_shifted_imm32:$imm) |
| AsmString = "cmp $\x02, $\xFF\x03\x01"; |
| break; |
| } |
| return false; |
| case AArch64::SUBSWrs: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (SUBSWrs WZR, GPR32:$src1, GPR32:$src2, 0) |
| AsmString = "cmp $\x02, $\x03"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg())) { |
| // (SUBSWrs WZR, GPR32:$src1, GPR32:$src2, arith_shift32:$sh) |
| AsmString = "cmp $\x02, $\x03$\xFF\x04\x02"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).getReg() == AArch64::WZR && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (SUBSWrs GPR32:$dst, WZR, GPR32:$src, 0) |
| AsmString = "negs $\x01, $\x03"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).getReg() == AArch64::WZR && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg())) { |
| // (SUBSWrs GPR32:$dst, WZR, GPR32:$src, arith_shift32:$shift) |
| AsmString = "negs $\x01, $\x03$\xFF\x04\x02"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (SUBSWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) |
| AsmString = "subs $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64::SUBSWrx: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32sponlyRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 16) { |
| // (SUBSWrx WZR, GPR32sponly:$src1, GPR32:$src2, 16) |
| AsmString = "cmp $\x02, $\x03"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).getReg() == AArch64::WZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg())) { |
| // (SUBSWrx WZR, GPR32sp:$src1, GPR32:$src2, arith_extend:$sh) |
| AsmString = "cmp $\x02, $\x03$\xFF\x04\x03"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32sponlyRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 16) { |
| // (SUBSWrx GPR32:$dst, GPR32sponly:$src1, GPR32:$src2, 16) |
| AsmString = "subs $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64::SUBSXri: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).getReg() == AArch64::XZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg())) { |
| // (SUBSXri XZR, GPR64sp:$src, addsub_shifted_imm64:$imm) |
| AsmString = "cmp $\x02, $\xFF\x03\x01"; |
| break; |
| } |
| return false; |
| case AArch64::SUBSXrs: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).getReg() == AArch64::XZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (SUBSXrs XZR, GPR64:$src1, GPR64:$src2, 0) |
| AsmString = "cmp $\x02, $\x03"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).getReg() == AArch64::XZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg())) { |
| // (SUBSXrs XZR, GPR64:$src1, GPR64:$src2, arith_shift64:$sh) |
| AsmString = "cmp $\x02, $\x03$\xFF\x04\x02"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).getReg() == AArch64::XZR && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (SUBSXrs GPR64:$dst, XZR, GPR64:$src, 0) |
| AsmString = "negs $\x01, $\x03"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).getReg() == AArch64::XZR && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg())) { |
| // (SUBSXrs GPR64:$dst, XZR, GPR64:$src, arith_shift64:$shift) |
| AsmString = "negs $\x01, $\x03$\xFF\x04\x02"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (SUBSXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) |
| AsmString = "subs $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64::SUBSXrx: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).getReg() == AArch64::XZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg())) { |
| // (SUBSXrx XZR, GPR64sp:$src1, GPR32:$src2, arith_extend:$sh) |
| AsmString = "cmp $\x02, $\x03$\xFF\x04\x03"; |
| break; |
| } |
| return false; |
| case AArch64::SUBSXrx64: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).getReg() == AArch64::XZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64sponlyRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 24) { |
| // (SUBSXrx64 XZR, GPR64sponly:$src1, GPR64:$src2, 24) |
| AsmString = "cmp $\x02, $\x03"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).getReg() == AArch64::XZR && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg())) { |
| // (SUBSXrx64 XZR, GPR64sp:$src1, GPR64:$src2, arith_extendlsl64:$sh) |
| AsmString = "cmp $\x02, $\x03$\xFF\x04\x03"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64sponlyRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 24) { |
| // (SUBSXrx64 GPR64:$dst, GPR64sponly:$src1, GPR64:$src2, 24) |
| AsmString = "subs $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64::SUBWrs: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).getReg() == AArch64::WZR && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (SUBWrs GPR32:$dst, WZR, GPR32:$src, 0) |
| AsmString = "neg $\x01, $\x03"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).getReg() == AArch64::WZR && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg())) { |
| // (SUBWrs GPR32:$dst, WZR, GPR32:$src, arith_shift32:$shift) |
| AsmString = "neg $\x01, $\x03$\xFF\x04\x02"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (SUBWrs GPR32:$dst, GPR32:$src1, GPR32:$src2, 0) |
| AsmString = "sub $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64::SUBWrx: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32sponlyRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 16) { |
| // (SUBWrx GPR32sponly:$dst, GPR32sp:$src1, GPR32:$src2, 16) |
| AsmString = "sub $\x01, $\x02, $\x03"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32sponlyRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 16) { |
| // (SUBWrx GPR32sp:$dst, GPR32sponly:$src1, GPR32:$src2, 16) |
| AsmString = "sub $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64::SUBXrs: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).getReg() == AArch64::XZR && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (SUBXrs GPR64:$dst, XZR, GPR64:$src, 0) |
| AsmString = "neg $\x01, $\x03"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).getReg() == AArch64::XZR && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg())) { |
| // (SUBXrs GPR64:$dst, XZR, GPR64:$src, arith_shift64:$shift) |
| AsmString = "neg $\x01, $\x03$\xFF\x04\x02"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 0) { |
| // (SUBXrs GPR64:$dst, GPR64:$src1, GPR64:$src2, 0) |
| AsmString = "sub $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64::SUBXrx64: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64sponlyRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 24) { |
| // (SUBXrx64 GPR64sponly:$dst, GPR64sp:$src1, GPR64:$src2, 24) |
| AsmString = "sub $\x01, $\x02, $\x03"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64spRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64sponlyRegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 24) { |
| // (SUBXrx64 GPR64sp:$dst, GPR64sponly:$src1, GPR64:$src2, 24) |
| AsmString = "sub $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64::SYSxt: |
| if (MI->getNumOperands() == 5 && |
| MI->getOperand(4).getReg() == AArch64::XZR) { |
| // (SYSxt imm0_7:$op1, sys_cr_op:$Cn, sys_cr_op:$Cm, imm0_7:$op2, XZR) |
| AsmString = "sys $\x01, $\xFF\x02\x35, $\xFF\x03\x35, $\x04"; |
| break; |
| } |
| return false; |
| case AArch64::UBFMWri: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 31) { |
| // (UBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31) |
| AsmString = "lsr $\x01, $\x02, $\x03"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 7) { |
| // (UBFMWri GPR32:$dst, GPR32:$src, 0, 7) |
| AsmString = "uxtb $\x01, $\x02"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 15) { |
| // (UBFMWri GPR32:$dst, GPR32:$src, 0, 15) |
| AsmString = "uxth $\x01, $\x02"; |
| break; |
| } |
| return false; |
| case AArch64::UBFMXri: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 63) { |
| // (UBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63) |
| AsmString = "lsr $\x01, $\x02, $\x03"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 7) { |
| // (UBFMXri GPR64:$dst, GPR64:$src, 0, 7) |
| AsmString = "uxtb $\x01, $\x02"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 15) { |
| // (UBFMXri GPR64:$dst, GPR64:$src, 0, 15) |
| AsmString = "uxth $\x01, $\x02"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 0 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 31) { |
| // (UBFMXri GPR64:$dst, GPR64:$src, 0, 31) |
| AsmString = "uxtw $\x01, $\x02"; |
| break; |
| } |
| return false; |
| case AArch64::UMADDLrrr: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR) { |
| // (UMADDLrrr GPR64:$dst, GPR32:$src1, GPR32:$src2, XZR) |
| AsmString = "umull $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64::UMOVvi32: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(1).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (UMOVvi32 GPR32:$dst, V128:$src, VectorIndexS:$idx) |
| AsmString = "mov.s $\x01, $\xFF\x02\x0C$\xFF\x03\x19"; |
| break; |
| } |
| return false; |
| case AArch64::UMOVvi64: |
| if (MI->getNumOperands() == 3 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::FPR128RegClassID).contains(MI->getOperand(1).getReg()) && |
| STI.getFeatureBits()[AArch64::FeatureNEON]) { |
| // (UMOVvi64 GPR64:$dst, V128:$src, VectorIndexD:$idx) |
| AsmString = "mov.d $\x01, $\xFF\x02\x0C$\xFF\x03\x19"; |
| break; |
| } |
| return false; |
| case AArch64::UMSUBLrrr: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(1).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) && |
| MI->getOperand(2).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) && |
| MI->getOperand(3).getReg() == AArch64::XZR) { |
| // (UMSUBLrrr GPR64:$dst, GPR32:$src1, GPR32:$src2, XZR) |
| AsmString = "umnegl $\x01, $\x02, $\x03"; |
| break; |
| } |
| return false; |
| case AArch64::UQDECB_WPiI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (UQDECB_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "uqdecb $\x01"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (UQDECB_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) |
| AsmString = "uqdecb $\x01, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::UQDECB_XPiI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (UQDECB_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "uqdecb $\x01"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (UQDECB_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) |
| AsmString = "uqdecb $\x01, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::UQDECD_WPiI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (UQDECD_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "uqdecd $\x01"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (UQDECD_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) |
| AsmString = "uqdecd $\x01, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::UQDECD_XPiI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (UQDECD_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "uqdecd $\x01"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (UQDECD_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) |
| AsmString = "uqdecd $\x01, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::UQDECD_ZPiI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (UQDECD_ZPiI ZPR64:$Zdn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "uqdecd $\xFF\x01\x10"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (UQDECD_ZPiI ZPR64:$Zdn, sve_pred_enum:$pattern, 1) |
| AsmString = "uqdecd $\xFF\x01\x10, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::UQDECH_WPiI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (UQDECH_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "uqdech $\x01"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (UQDECH_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) |
| AsmString = "uqdech $\x01, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::UQDECH_XPiI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (UQDECH_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "uqdech $\x01"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (UQDECH_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) |
| AsmString = "uqdech $\x01, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::UQDECH_ZPiI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (UQDECH_ZPiI ZPR16:$Zdn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "uqdech $\xFF\x01\x09"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (UQDECH_ZPiI ZPR16:$Zdn, sve_pred_enum:$pattern, 1) |
| AsmString = "uqdech $\xFF\x01\x09, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::UQDECW_WPiI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (UQDECW_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "uqdecw $\x01"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (UQDECW_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) |
| AsmString = "uqdecw $\x01, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::UQDECW_XPiI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (UQDECW_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "uqdecw $\x01"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (UQDECW_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) |
| AsmString = "uqdecw $\x01, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::UQDECW_ZPiI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (UQDECW_ZPiI ZPR32:$Zdn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "uqdecw $\xFF\x01\x0B"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (UQDECW_ZPiI ZPR32:$Zdn, sve_pred_enum:$pattern, 1) |
| AsmString = "uqdecw $\xFF\x01\x0B, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::UQINCB_WPiI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (UQINCB_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "uqincb $\x01"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (UQINCB_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) |
| AsmString = "uqincb $\x01, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::UQINCB_XPiI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (UQINCB_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "uqincb $\x01"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (UQINCB_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) |
| AsmString = "uqincb $\x01, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::UQINCD_WPiI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (UQINCD_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "uqincd $\x01"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (UQINCD_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) |
| AsmString = "uqincd $\x01, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::UQINCD_XPiI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (UQINCD_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "uqincd $\x01"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (UQINCD_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) |
| AsmString = "uqincd $\x01, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::UQINCD_ZPiI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (UQINCD_ZPiI ZPR64:$Zdn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "uqincd $\xFF\x01\x10"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (UQINCD_ZPiI ZPR64:$Zdn, sve_pred_enum:$pattern, 1) |
| AsmString = "uqincd $\xFF\x01\x10, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::UQINCH_WPiI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (UQINCH_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "uqinch $\x01"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (UQINCH_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) |
| AsmString = "uqinch $\x01, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::UQINCH_XPiI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (UQINCH_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "uqinch $\x01"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (UQINCH_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) |
| AsmString = "uqinch $\x01, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::UQINCH_ZPiI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (UQINCH_ZPiI ZPR16:$Zdn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "uqinch $\xFF\x01\x09"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (UQINCH_ZPiI ZPR16:$Zdn, sve_pred_enum:$pattern, 1) |
| AsmString = "uqinch $\xFF\x01\x09, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::UQINCW_WPiI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (UQINCW_WPiI GPR32z:$Rdn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "uqincw $\x01"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (UQINCW_WPiI GPR32z:$Rdn, sve_pred_enum:$pattern, 1) |
| AsmString = "uqincw $\x01, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::UQINCW_XPiI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (UQINCW_XPiI GPR64z:$Rdn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "uqincw $\x01"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::GPR64RegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (UQINCW_XPiI GPR64z:$Rdn, sve_pred_enum:$pattern, 1) |
| AsmString = "uqincw $\x01, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| case AArch64::UQINCW_ZPiI: |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(2).isImm() && |
| MI->getOperand(2).getImm() == 31 && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (UQINCW_ZPiI ZPR32:$Zdn, { 1, 1, 1, 1, 1 }, 1) |
| AsmString = "uqincw $\xFF\x01\x0B"; |
| break; |
| } |
| if (MI->getNumOperands() == 4 && |
| MI->getOperand(0).isReg() && |
| MRI.getRegClass(AArch64::ZPRRegClassID).contains(MI->getOperand(0).getReg()) && |
| MI->getOperand(3).isImm() && |
| MI->getOperand(3).getImm() == 1 && |
| STI.getFeatureBits()[AArch64::FeatureSVE]) { |
| // (UQINCW_ZPiI ZPR32:$Zdn, sve_pred_enum:$pattern, 1) |
| AsmString = "uqincw $\xFF\x01\x0B, $\xFF\x03\x0E"; |
| break; |
| } |
| return false; |
| } |
| |
| unsigned I = 0; |
| while (AsmString[I] != ' ' && AsmString[I] != '\t' && |
| AsmString[I] != '$' && AsmString[I] != '\0') |
| ++I; |
| OS << '\t' << StringRef(AsmString, I); |
| if (AsmString[I] != '\0') { |
| if (AsmString[I] == ' ' || AsmString[I] == '\t') { |
| OS << '\t'; |
| ++I; |
| } |
| do { |
| if (AsmString[I] == '$') { |
| ++I; |
| if (AsmString[I] == (char)0xff) { |
| ++I; |
| int OpIdx = AsmString[I++] - 1; |
| int PrintMethodIdx = AsmString[I++] - 1; |
| printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, STI, OS); |
| } else |
| printOperand(MI, unsigned(AsmString[I++]) - 1, STI, OS); |
| } else { |
| OS << AsmString[I++]; |
| } |
| } while (AsmString[I] != '\0'); |
| } |
| |
| return true; |
| } |
| |
| void AArch64AppleInstPrinter::printCustomAliasOperand( |
| const MCInst *MI, unsigned OpIdx, |
| unsigned PrintMethodIdx, |
| const MCSubtargetInfo &STI, |
| raw_ostream &OS) { |
| switch (PrintMethodIdx) { |
| default: |
| llvm_unreachable("Unknown PrintMethod kind"); |
| break; |
| case 0: |
| printAddSubImm(MI, OpIdx, STI, OS); |
| break; |
| case 1: |
| printShifter(MI, OpIdx, STI, OS); |
| break; |
| case 2: |
| printArithExtend(MI, OpIdx, STI, OS); |
| break; |
| case 3: |
| printLogicalImm<int32_t>(MI, OpIdx, STI, OS); |
| break; |
| case 4: |
| printLogicalImm<int64_t>(MI, OpIdx, STI, OS); |
| break; |
| case 5: |
| printSVERegOp<'b'>(MI, OpIdx, STI, OS); |
| break; |
| case 6: |
| printSVERegOp<>(MI, OpIdx, STI, OS); |
| break; |
| case 7: |
| printLogicalImm<int8_t>(MI, OpIdx, STI, OS); |
| break; |
| case 8: |
| printSVERegOp<'h'>(MI, OpIdx, STI, OS); |
| break; |
| case 9: |
| printLogicalImm<int16_t>(MI, OpIdx, STI, OS); |
| break; |
| case 10: |
| printSVERegOp<'s'>(MI, OpIdx, STI, OS); |
| break; |
| case 11: |
| printVRegOperand(MI, OpIdx, STI, OS); |
| break; |
| case 12: |
| printImm(MI, OpIdx, STI, OS); |
| break; |
| case 13: |
| printSVEPattern(MI, OpIdx, STI, OS); |
| break; |
| case 14: |
| printImm8OptLsl<int8_t>(MI, OpIdx, STI, OS); |
| break; |
| case 15: |
| printSVERegOp<'d'>(MI, OpIdx, STI, OS); |
| break; |
| case 16: |
| printImm8OptLsl<int64_t>(MI, OpIdx, STI, OS); |
| break; |
| case 17: |
| printImm8OptLsl<int16_t>(MI, OpIdx, STI, OS); |
| break; |
| case 18: |
| printImm8OptLsl<int32_t>(MI, OpIdx, STI, OS); |
| break; |
| case 19: |
| printInverseCondCode(MI, OpIdx, STI, OS); |
| break; |
| case 20: |
| printSVELogicalImm<int16_t>(MI, OpIdx, STI, OS); |
| break; |
| case 21: |
| printSVELogicalImm<int32_t>(MI, OpIdx, STI, OS); |
| break; |
| case 22: |
| printSVELogicalImm<int64_t>(MI, OpIdx, STI, OS); |
| break; |
| case 23: |
| printZPRasFPR<8>(MI, OpIdx, STI, OS); |
| break; |
| case 24: |
| printVectorIndex(MI, OpIdx, STI, OS); |
| break; |
| case 25: |
| printZPRasFPR<64>(MI, OpIdx, STI, OS); |
| break; |
| case 26: |
| printZPRasFPR<16>(MI, OpIdx, STI, OS); |
| break; |
| case 27: |
| printSVERegOp<'q'>(MI, OpIdx, STI, OS); |
| break; |
| case 28: |
| printZPRasFPR<128>(MI, OpIdx, STI, OS); |
| break; |
| case 29: |
| printZPRasFPR<32>(MI, OpIdx, STI, OS); |
| break; |
| case 30: |
| printFPImmOperand(MI, OpIdx, STI, OS); |
| break; |
| case 31: |
| printTypedVectorList<0,'d'>(MI, OpIdx, STI, OS); |
| break; |
| case 32: |
| printTypedVectorList<0,'s'>(MI, OpIdx, STI, OS); |
| break; |
| case 33: |
| printPSBHintOp(MI, OpIdx, STI, OS); |
| break; |
| case 34: |
| printTypedVectorList<0,'h'>(MI, OpIdx, STI, OS); |
| break; |
| case 35: |
| printTypedVectorList<0,'b'>(MI, OpIdx, STI, OS); |
| break; |
| case 36: |
| printTypedVectorList<16, 'b'>(MI, OpIdx, STI, OS); |
| break; |
| case 37: |
| printTypedVectorList<1, 'd'>(MI, OpIdx, STI, OS); |
| break; |
| case 38: |
| printTypedVectorList<2, 'd'>(MI, OpIdx, STI, OS); |
| break; |
| case 39: |
| printTypedVectorList<2, 's'>(MI, OpIdx, STI, OS); |
| break; |
| case 40: |
| printTypedVectorList<4, 'h'>(MI, OpIdx, STI, OS); |
| break; |
| case 41: |
| printTypedVectorList<4, 's'>(MI, OpIdx, STI, OS); |
| break; |
| case 42: |
| printTypedVectorList<8, 'b'>(MI, OpIdx, STI, OS); |
| break; |
| case 43: |
| printTypedVectorList<8, 'h'>(MI, OpIdx, STI, OS); |
| break; |
| case 44: |
| printTypedVectorList<0, 'h'>(MI, OpIdx, STI, OS); |
| break; |
| case 45: |
| printTypedVectorList<0, 's'>(MI, OpIdx, STI, OS); |
| break; |
| case 46: |
| printTypedVectorList<0, 'd'>(MI, OpIdx, STI, OS); |
| break; |
| case 47: |
| printTypedVectorList<0, 'b'>(MI, OpIdx, STI, OS); |
| break; |
| case 48: |
| printImmHex(MI, OpIdx, STI, OS); |
| break; |
| case 49: |
| printPrefetchOp<true>(MI, OpIdx, STI, OS); |
| break; |
| case 50: |
| printPrefetchOp(MI, OpIdx, STI, OS); |
| break; |
| case 51: |
| printGPR64as32(MI, OpIdx, STI, OS); |
| break; |
| case 52: |
| printSysCROperand(MI, OpIdx, STI, OS); |
| break; |
| } |
| } |
| |
| static bool AArch64AppleInstPrinterValidateMCOperand(const MCOperand &MCOp, |
| const MCSubtargetInfo &STI, |
| unsigned PredicateIndex) { |
| switch (PredicateIndex) { |
| default: |
| llvm_unreachable("Unknown MCOperandPredicate kind"); |
| break; |
| case 1: { |
| |
| if (!MCOp.isImm()) |
| return false; |
| int64_t Val = AArch64_AM::decodeLogicalImmediate(MCOp.getImm(), 64); |
| return AArch64_AM::isSVEMaskOfIdenticalElements<int8_t>(Val); |
| |
| } |
| case 2: { |
| |
| if (!MCOp.isImm()) |
| return false; |
| int64_t Val = AArch64_AM::decodeLogicalImmediate(MCOp.getImm(), 64); |
| return AArch64_AM::isSVEMaskOfIdenticalElements<int16_t>(Val); |
| |
| } |
| case 3: { |
| |
| if (!MCOp.isImm()) |
| return false; |
| int64_t Val = AArch64_AM::decodeLogicalImmediate(MCOp.getImm(), 64); |
| return AArch64_AM::isSVEMaskOfIdenticalElements<int32_t>(Val); |
| |
| } |
| case 4: { |
| |
| return MCOp.isImm() && |
| MCOp.getImm() != AArch64CC::AL && |
| MCOp.getImm() != AArch64CC::NV; |
| |
| } |
| case 5: { |
| |
| if (!MCOp.isImm()) |
| return false; |
| int64_t Val = AArch64_AM::decodeLogicalImmediate(MCOp.getImm(), 64); |
| return AArch64_AM::isSVEMaskOfIdenticalElements<int16_t>(Val) && |
| AArch64_AM::isSVEMoveMaskPreferredLogicalImmediate(Val); |
| |
| } |
| case 6: { |
| |
| if (!MCOp.isImm()) |
| return false; |
| int64_t Val = AArch64_AM::decodeLogicalImmediate(MCOp.getImm(), 64); |
| return AArch64_AM::isSVEMaskOfIdenticalElements<int32_t>(Val) && |
| AArch64_AM::isSVEMoveMaskPreferredLogicalImmediate(Val); |
| |
| } |
| case 7: { |
| |
| if (!MCOp.isImm()) |
| return false; |
| int64_t Val = AArch64_AM::decodeLogicalImmediate(MCOp.getImm(), 64); |
| return AArch64_AM::isSVEMaskOfIdenticalElements<int64_t>(Val) && |
| AArch64_AM::isSVEMoveMaskPreferredLogicalImmediate(Val); |
| |
| } |
| case 8: { |
| |
| // Check, if operand is valid, to fix exhaustive aliasing in disassembly. |
| // "psb" is an alias to "hint" only for certain values of CRm:Op2 fields. |
| if (!MCOp.isImm()) |
| return false; |
| return AArch64PSBHint::lookupPSBByEncoding(MCOp.getImm()) != nullptr; |
| |
| } |
| } |
| } |
| |
| #endif // PRINT_ALIAS_INSTR |