| //===--- X86InstPrinterCommon.cpp - X86 assembly instruction printing -----===// |
| // |
| // The LLVM Compiler Infrastructure |
| // |
| // This file is distributed under the University of Illinois Open Source |
| // License. See LICENSE.TXT for details. |
| // |
| //===----------------------------------------------------------------------===// |
| // |
| // This file includes common code for rendering MCInst instances as Intel-style |
| // and Intel-style assembly. |
| // |
| //===----------------------------------------------------------------------===// |
| |
| #include "X86InstPrinterCommon.h" |
| #include "MCTargetDesc/X86BaseInfo.h" |
| #include "llvm/MC/MCExpr.h" |
| #include "llvm/MC/MCInst.h" |
| #include "llvm/MC/MCInstrDesc.h" |
| #include "llvm/MC/MCInstrInfo.h" |
| #include "llvm/Support/raw_ostream.h" |
| #include "llvm/Support/Casting.h" |
| #include <cstdint> |
| #include <cassert> |
| |
| using namespace llvm; |
| |
| void X86InstPrinterCommon::printSSEAVXCC(const MCInst *MI, unsigned Op, |
| raw_ostream &O) { |
| int64_t Imm = MI->getOperand(Op).getImm(); |
| switch (Imm) { |
| default: llvm_unreachable("Invalid ssecc/avxcc argument!"); |
| case 0: O << "eq"; break; |
| case 1: O << "lt"; break; |
| case 2: O << "le"; break; |
| case 3: O << "unord"; break; |
| case 4: O << "neq"; break; |
| case 5: O << "nlt"; break; |
| case 6: O << "nle"; break; |
| case 7: O << "ord"; break; |
| case 8: O << "eq_uq"; break; |
| case 9: O << "nge"; break; |
| case 0xa: O << "ngt"; break; |
| case 0xb: O << "false"; break; |
| case 0xc: O << "neq_oq"; break; |
| case 0xd: O << "ge"; break; |
| case 0xe: O << "gt"; break; |
| case 0xf: O << "true"; break; |
| case 0x10: O << "eq_os"; break; |
| case 0x11: O << "lt_oq"; break; |
| case 0x12: O << "le_oq"; break; |
| case 0x13: O << "unord_s"; break; |
| case 0x14: O << "neq_us"; break; |
| case 0x15: O << "nlt_uq"; break; |
| case 0x16: O << "nle_uq"; break; |
| case 0x17: O << "ord_s"; break; |
| case 0x18: O << "eq_us"; break; |
| case 0x19: O << "nge_uq"; break; |
| case 0x1a: O << "ngt_uq"; break; |
| case 0x1b: O << "false_os"; break; |
| case 0x1c: O << "neq_os"; break; |
| case 0x1d: O << "ge_oq"; break; |
| case 0x1e: O << "gt_oq"; break; |
| case 0x1f: O << "true_us"; break; |
| } |
| } |
| |
| void X86InstPrinterCommon::printXOPCC(const MCInst *MI, unsigned Op, |
| raw_ostream &O) { |
| int64_t Imm = MI->getOperand(Op).getImm(); |
| switch (Imm) { |
| default: llvm_unreachable("Invalid xopcc argument!"); |
| case 0: O << "lt"; break; |
| case 1: O << "le"; break; |
| case 2: O << "gt"; break; |
| case 3: O << "ge"; break; |
| case 4: O << "eq"; break; |
| case 5: O << "neq"; break; |
| case 6: O << "false"; break; |
| case 7: O << "true"; break; |
| } |
| } |
| |
| void X86InstPrinterCommon::printRoundingControl(const MCInst *MI, unsigned Op, |
| raw_ostream &O) { |
| int64_t Imm = MI->getOperand(Op).getImm() & 0x3; |
| switch (Imm) { |
| case 0: O << "{rn-sae}"; break; |
| case 1: O << "{rd-sae}"; break; |
| case 2: O << "{ru-sae}"; break; |
| case 3: O << "{rz-sae}"; break; |
| } |
| } |
| |
| /// printPCRelImm - This is used to print an immediate value that ends up |
| /// being encoded as a pc-relative value (e.g. for jumps and calls). In |
| /// Intel-style these print slightly differently than normal immediates. |
| /// for example, a $ is not emitted. |
| void X86InstPrinterCommon::printPCRelImm(const MCInst *MI, unsigned OpNo, |
| raw_ostream &O) { |
| const MCOperand &Op = MI->getOperand(OpNo); |
| if (Op.isImm()) |
| O << formatImm(Op.getImm()); |
| else { |
| assert(Op.isExpr() && "unknown pcrel immediate operand"); |
| // If a symbolic branch target was added as a constant expression then print |
| // that address in hex. |
| const MCConstantExpr *BranchTarget = dyn_cast<MCConstantExpr>(Op.getExpr()); |
| int64_t Address; |
| if (BranchTarget && BranchTarget->evaluateAsAbsolute(Address)) { |
| O << formatHex((uint64_t)Address); |
| } else { |
| // Otherwise, just print the expression. |
| Op.getExpr()->print(O, &MAI); |
| } |
| } |
| } |
| |
| void X86InstPrinterCommon::printOptionalSegReg(const MCInst *MI, unsigned OpNo, |
| raw_ostream &O) { |
| if (MI->getOperand(OpNo).getReg()) { |
| printOperand(MI, OpNo, O); |
| O << ':'; |
| } |
| } |
| |
| void X86InstPrinterCommon::printInstFlags(const MCInst *MI, raw_ostream &O) { |
| const MCInstrDesc &Desc = MII.get(MI->getOpcode()); |
| uint64_t TSFlags = Desc.TSFlags; |
| unsigned Flags = MI->getFlags(); |
| |
| if ((TSFlags & X86II::LOCK) || (Flags & X86::IP_HAS_LOCK)) |
| O << "\tlock\t"; |
| |
| if ((TSFlags & X86II::NOTRACK) || (Flags & X86::IP_HAS_NOTRACK)) |
| O << "\tnotrack\t"; |
| |
| if (Flags & X86::IP_HAS_REPEAT_NE) |
| O << "\trepne\t"; |
| else if (Flags & X86::IP_HAS_REPEAT) |
| O << "\trep\t"; |
| } |