Eliminate code randomization support from Subzero
SwiftShader has no use for this since shader execution with robustness
features enabled can not access memory outside of the graphics
resources. For Chromium it also runs in the GPU process, which isolates
it from browser-wide and even tab renderer data and code, and also has
its own sandboxing.
If we ever do need randomization to prevent attacks, and project Bunker
doesn't provide the needed site isolation, it should be implemented
either at the Reactor level or as separate transformation passes where
possible.
While previously this feature was already disabled, there might have
been inadvertent randomization which could explain our test time
variability. It may also improve code generation performance a bit to
not have this code around any more.
Bug: b/179832693
Change-Id: If1ccb54981edb61f443dd5949c56b75bab07c7c2
Reviewed-on: https://swiftshader-review.googlesource.com/c/SwiftShader/+/52808
Kokoro-Result: kokoro <noreply+kokoro@google.com>
Tested-by: Nicolas Capens <nicolascapens@google.com>
Presubmit-Ready: Nicolas Capens <nicolascapens@google.com>
Reviewed-by: Antonio Maiorano <amaiorano@google.com>
diff --git a/src/Reactor/BUILD.gn b/src/Reactor/BUILD.gn
index c4070fd..d7ca841 100644
--- a/src/Reactor/BUILD.gn
+++ b/src/Reactor/BUILD.gn
@@ -223,7 +223,6 @@
"$subzero_dir/src/IceMangling.cpp",
"$subzero_dir/src/IceMemory.cpp",
"$subzero_dir/src/IceOperand.cpp",
- "$subzero_dir/src/IceRNG.cpp",
"$subzero_dir/src/IceRangeSpec.cpp",
"$subzero_dir/src/IceRegAlloc.cpp",
"$subzero_dir/src/IceRevision.cpp",
diff --git a/third_party/subzero/CMakeLists.txt b/third_party/subzero/CMakeLists.txt
index ab337a7..40c2735 100644
--- a/third_party/subzero/CMakeLists.txt
+++ b/third_party/subzero/CMakeLists.txt
@@ -38,7 +38,6 @@
src/IceRangeSpec.cpp
src/IceRegAlloc.cpp
src/IceRevision.cpp
- src/IceRNG.cpp
src/IceSwitchLowering.cpp
src/IceTargetLowering.cpp
src/IceThreading.cpp
diff --git a/third_party/subzero/docs/DESIGN.rst b/third_party/subzero/docs/DESIGN.rst
index d9a3d4c..bf3e905 100644
--- a/third_party/subzero/docs/DESIGN.rst
+++ b/third_party/subzero/docs/DESIGN.rst
@@ -1097,211 +1097,6 @@
was designed from the start with security in mind, so one expects fewer attacker
opportunities here.
-Code diversification
-^^^^^^^^^^^^^^^^^^^^
-
-`Return-oriented programming
-<https://en.wikipedia.org/wiki/Return-oriented_programming>`_ (ROP) is a
-now-common technique for starting with e.g. a known buffer overflow situation
-and launching it into a deeper exploit. The attacker scans the executable
-looking for ROP gadgets, which are short sequences of code that happen to load
-known values into known registers and then return. An attacker who manages to
-overwrite parts of the stack can overwrite it with carefully chosen return
-addresses such that certain ROP gadgets are effectively chained together to set
-up the register state as desired, finally returning to some code that manages to
-do something nasty based on those register values.
-
-If there is a popular ``.pexe`` with a large install base, the attacker could
-run Subzero on it and scan the executable for suitable ROP gadgets to use as
-part of a potential exploit. Note that if the trusted validator is working
-correctly, these ROP gadgets are limited to starting at a bundle boundary and
-cannot use the trick of finding a gadget that happens to begin inside another
-instruction. All the same, gadgets with these constraints still exist and the
-attacker has access to them. This is the attack model we focus most on --
-protecting the user against misuse of a "trusted" developer's application, as
-opposed to mischief from a malicious ``.pexe`` file.
-
-Subzero can mitigate these attacks to some degree through code diversification.
-Specifically, we can apply some randomness to the code generation that makes ROP
-gadgets less predictable. This randomness can have some compile-time cost, and
-it can affect the code quality; and some diversifications may be more effective
-than others. A more detailed treatment of hardening techniques may be found in
-the Matasano report "`Attacking Clientside JIT Compilers
-<https://www.nccgroup.trust/globalassets/resources/us/presentations/documents/attacking_clientside_jit_compilers_paper.pdf>`_".
-
-To evaluate diversification effectiveness, we use a third-party ROP gadget
-finder and limit its results to bundle-aligned addresses. For a given
-diversification technique, we run it with a number of different random seeds,
-find ROP gadgets for each version, and determine how persistent each ROP gadget
-is across the different versions. A gadget is persistent if the same gadget is
-found at the same code address. The best diversifications are ones with low
-gadget persistence rates.
-
-Subzero implements 7 different diversification techniques. Below is a
-discussion of each technique, its effectiveness, and its cost. The discussions
-of cost and effectiveness are for a single diversification technique; the
-translation-time costs for multiple techniques are additive, but the effects of
-multiple techniques on code quality and effectiveness are not yet known.
-
-In Subzero's implementation, each randomization is "repeatable" in a sense.
-Each pass that includes a randomization option gets its own private instance of
-a random number generator (RNG). The RNG is seeded with a combination of a
-global seed, the pass ID, and the function's sequence number. The global seed
-is designed to be different across runs (perhaps based on the current time), but
-for debugging, the global seed can be set to a specific value and the results
-will be repeatable.
-
-Subzero-generated code is subject to diversification once per translation, and
-then Chrome caches the diversified binary for subsequent executions. An
-attacker may attempt to run the binary multiple times hoping for
-higher-probability combinations of ROP gadgets. When the attacker guesses
-wrong, a likely outcome is an application crash. Chrome throttles creation of
-crashy processes which reduces the likelihood of the attacker eventually gaining
-a foothold.
-
-Constant blinding
-~~~~~~~~~~~~~~~~~
-
-Here, we prevent attackers from controlling large immediates in the text
-(executable) section. A random cookie is generated for each function, and if
-the constant exceeds a specified threshold, the constant is obfuscated with the
-cookie and equivalent code is generated. For example, instead of this x86
-instruction::
-
- mov $0x11223344, <%Reg/Mem>
-
-the following code might be generated::
-
- mov $(0x11223344+Cookie), %temp
- lea -Cookie(%temp), %temp
- mov %temp, <%Reg/Mem>
-
-The ``lea`` instruction is used rather than e.g. ``add``/``sub`` or ``xor``, to
-prevent unintended effects on the flags register.
-
-This transformation has almost no effect on translation time, and about 1%
-impact on code quality, depending on the threshold chosen. It does little to
-reduce gadget persistence, but it does remove a lot of potential opportunities
-to construct intra-instruction ROP gadgets (which an attacker could use only if
-a validator bug were discovered, since the Native Client sandbox and associated
-validator force returns and other indirect branches to be to bundle-aligned
-addresses).
-
-Constant pooling
-~~~~~~~~~~~~~~~~
-
-This is similar to constant blinding, in that large immediates are removed from
-the text section. In this case, each unique constant above the threshold is
-stored in a read-only data section and the constant is accessed via a memory
-load. For the above example, the following code might be generated::
-
- mov $Label$1, %temp
- mov %temp, <%Reg/Mem>
-
-This has a similarly small impact on translation time and ROP gadget
-persistence, and a smaller (better) impact on code quality. This is because it
-uses fewer instructions, and in some cases good register allocation leads to no
-increase in instruction count. Note that this still gives an attacker some
-limited amount of control over some text section values, unless we randomize the
-constant pool layout.
-
-Static data reordering
-~~~~~~~~~~~~~~~~~~~~~~
-
-This transformation limits the attacker's ability to control bits in global data
-address references. It simply permutes the order in memory of global variables
-and internal constant pool entries. For the constant pool, we only permute
-within a type (i.e., emit a randomized list of ints, followed by a randomized
-list of floats, etc.) to maintain good packing in the face of alignment
-constraints.
-
-As might be expected, this has no impact on code quality, translation time, or
-ROP gadget persistence (though as above, it limits opportunities for
-intra-instruction ROP gadgets with a broken validator).
-
-Basic block reordering
-~~~~~~~~~~~~~~~~~~~~~~
-
-Here, we randomize the order of basic blocks within a function, with the
-constraint that we still want to maintain a topological order as much as
-possible, to avoid making the code too branchy.
-
-This has no impact on code quality, and about 1% impact on translation time, due
-to a separate pass to recompute layout. It ends up having a huge effect on ROP
-gadget persistence, tied for best with nop insertion, reducing ROP gadget
-persistence to less than 5%.
-
-Function reordering
-~~~~~~~~~~~~~~~~~~~
-
-Here, we permute the order that functions are emitted, primarily to shift ROP
-gadgets around to less predictable locations. It may also change call address
-offsets in case the attacker was trying to control that offset in the code.
-
-To control latency and memory footprint, we don't arbitrarily permute functions.
-Instead, for some relatively small value of N, we queue up N assembler buffers,
-and then emit the N functions in random order, and repeat until all functions
-are emitted.
-
-Function reordering has no impact on translation time or code quality.
-Measurements indicate that it reduces ROP gadget persistence to about 15%.
-
-Nop insertion
-~~~~~~~~~~~~~
-
-This diversification randomly adds a nop instruction after each regular
-instruction, with some probability. Nop instructions of different lengths may
-be selected. Nop instructions are never added inside a bundle_lock region.
-Note that when sandboxing is enabled, nop instructions are already being added
-for bundle alignment, so the diversification nop instructions may simply be
-taking the place of alignment nop instructions, though distributed differently
-through the bundle.
-
-In Subzero's currently implementation, nop insertion adds 3-5% to the
-translation time, but this is probably because it is implemented as a separate
-pass that adds actual nop instructions to the IR. The overhead would probably
-be a lot less if it were integrated into the assembler pass. The code quality
-is also reduced by 3-5%, making nop insertion the most expensive of the
-diversification techniques.
-
-Nop insertion is very effective in reducing ROP gadget persistence, at the same
-level as basic block randomization (less than 5%). But given nop insertion's
-impact on translation time and code quality, one would most likely prefer to use
-basic block randomization instead (though the combined effects of the different
-diversification techniques have not yet been studied).
-
-Register allocation randomization
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-In this diversification, the register allocator tries to make different but
-mostly functionally equivalent choices, while maintaining stable code quality.
-
-A naive approach would be the following. Whenever the allocator has more than
-one choice for assigning a register, choose randomly among those options. And
-whenever there are no registers available and there is a tie for the
-lowest-weight variable, randomly select one of the lowest-weight variables to
-evict. Because of the one-pass nature of the linear-scan algorithm, this
-randomization strategy can have a large impact on which variables are ultimately
-assigned registers, with a corresponding large impact on code quality.
-
-Instead, we choose an approach that tries to keep code quality stable regardless
-of the random seed. We partition the set of physical registers into equivalence
-classes. If a register is pre-colored in the function (i.e., referenced
-explicitly by name), it forms its own equivalence class. The remaining
-registers are partitioned according to their combination of attributes such as
-integer versus floating-point, 8-bit versus 32-bit, caller-save versus
-callee-saved, etc. Each equivalence class is randomly permuted, and the
-complete permutation is applied to the final register assignments.
-
-Register randomization reduces ROP gadget persistence to about 10% on average,
-though there tends to be fairly high variance across functions and applications.
-This probably has to do with the set of restrictions in the x86-32 instruction
-set and ABI, such as few general-purpose registers, ``%eax`` used for return
-values, ``%edx`` used for division, ``%cl`` used for shifting, etc. As
-intended, register randomization has no impact on code quality, and a slight
-(0.5%) impact on translation time due to an extra scan over the variables to
-identify pre-colored registers.
-
Fuzzing
^^^^^^^
diff --git a/third_party/subzero/src/IceCfg.cpp b/third_party/subzero/src/IceCfg.cpp
index 98956ef..2bd610d 100644
--- a/third_party/subzero/src/IceCfg.cpp
+++ b/third_party/subzero/src/IceCfg.cpp
@@ -44,15 +44,6 @@
Target = TargetLowering::createLowering(getFlags().getTargetArch(), this);
VMetadata.reset(new VariablesMetadata(this));
TargetAssembler = Target->createAssembler();
-
- if (getFlags().getRandomizeAndPoolImmediatesOption() == RPI_Randomize) {
- // If -randomize-pool-immediates=randomize, create a random number
- // generator to generate a cookie for constant blinding.
- RandomNumberGenerator RNG(getFlags().getRandomSeed(), RPE_ConstantBlinding,
- this->SequenceNumber);
- ConstantBlindingCookie =
- (uint32_t)RNG.next((uint64_t)std::numeric_limits<uint32_t>::max() + 1);
- }
}
Cfg::~Cfg() {
@@ -444,52 +435,6 @@
swapNodes(Reordered);
}
-namespace {
-void getRandomPostOrder(CfgNode *Node, BitVector &ToVisit,
- Ice::NodeList &PostOrder,
- Ice::RandomNumberGenerator *RNG) {
- assert(ToVisit[Node->getIndex()]);
- ToVisit[Node->getIndex()] = false;
- NodeList Outs = Node->getOutEdges();
- Ice::RandomShuffle(Outs.begin(), Outs.end(),
- [RNG](int N) { return RNG->next(N); });
- for (CfgNode *Next : Outs) {
- if (ToVisit[Next->getIndex()])
- getRandomPostOrder(Next, ToVisit, PostOrder, RNG);
- }
- PostOrder.push_back(Node);
-}
-} // end of anonymous namespace
-
-void Cfg::shuffleNodes() {
- if (!getFlags().getReorderBasicBlocks())
- return;
-
- NodeList ReversedReachable;
- NodeList Unreachable;
- BitVector ToVisit(Nodes.size(), true);
- // Create Random number generator for function reordering
- RandomNumberGenerator RNG(getFlags().getRandomSeed(),
- RPE_BasicBlockReordering, SequenceNumber);
- // Traverse from entry node.
- getRandomPostOrder(getEntryNode(), ToVisit, ReversedReachable, &RNG);
- // Collect the unreachable nodes.
- for (CfgNode *Node : Nodes)
- if (ToVisit[Node->getIndex()])
- Unreachable.push_back(Node);
- // Copy the layout list to the Nodes.
- NodeList Shuffled;
- Shuffled.reserve(ReversedReachable.size() + Unreachable.size());
- for (CfgNode *Node : reverse_range(ReversedReachable))
- Shuffled.push_back(Node);
- for (CfgNode *Node : Unreachable)
- Shuffled.push_back(Node);
- assert(Nodes.size() == Shuffled.size());
- swapNodes(Shuffled);
-
- dump("After basic block shuffling");
-}
-
void Cfg::localCSE(bool AssumeSSA) {
// Performs basic-block local common-subexpression elimination
// If we have
@@ -1477,16 +1422,6 @@
}
}
-void Cfg::doNopInsertion() {
- if (!getFlags().getShouldDoNopInsertion())
- return;
- TimerMarker T(TimerStack::TT_doNopInsertion, this);
- RandomNumberGenerator RNG(getFlags().getRandomSeed(), RPE_NopInsertion,
- SequenceNumber);
- for (CfgNode *Node : Nodes)
- Node->doNopInsertion(RNG);
-}
-
void Cfg::genCode() {
TimerMarker T(TimerStack::TT_genCode, this);
for (CfgNode *Node : Nodes)
diff --git a/third_party/subzero/src/IceCfg.h b/third_party/subzero/src/IceCfg.h
index 36bf139..3729e3c 100644
--- a/third_party/subzero/src/IceCfg.h
+++ b/third_party/subzero/src/IceCfg.h
@@ -175,7 +175,6 @@
bool hasComputedFrame() const;
bool getFocusedTiming() const { return FocusedTiming; }
void setFocusedTiming() { FocusedTiming = true; }
- uint32_t getConstantBlindingCookie() const { return ConstantBlindingCookie; }
/// @}
/// Passes over the CFG.
@@ -198,7 +197,6 @@
void deletePhis();
void advancedPhiLowering();
void reorderNodes();
- void shuffleNodes();
void localCSE(bool AssumeSSA);
void floatConstantCSE();
void shortCircuitJumps();
@@ -213,7 +211,6 @@
/// replaced by a shufflevector instruction.
void materializeVectorShuffles();
void doArgLowering();
- void doNopInsertion();
void genCode();
void genFrame();
void generateLoopInfo();
@@ -303,7 +300,6 @@
GlobalContext *Ctx;
uint32_t SequenceNumber; /// output order for emission
OptLevel OptimizationLevel = Opt_m1;
- uint32_t ConstantBlindingCookie = 0; /// cookie for constant blinding
VerboseMask VMask;
GlobalString FunctionName;
Type ReturnType = IceType_void;
diff --git a/third_party/subzero/src/IceCfgNode.cpp b/third_party/subzero/src/IceCfgNode.cpp
index d14e41f..26991bb 100644
--- a/third_party/subzero/src/IceCfgNode.cpp
+++ b/third_party/subzero/src/IceCfgNode.cpp
@@ -610,28 +610,6 @@
}
}
-void CfgNode::doNopInsertion(RandomNumberGenerator &RNG) {
- TargetLowering *Target = Func->getTarget();
- LoweringContext &Context = Target->getContext();
- Context.init(this);
- Context.setInsertPoint(Context.getCur());
- // Do not insert nop in bundle locked instructions.
- bool PauseNopInsertion = false;
- while (!Context.atEnd()) {
- if (llvm::isa<InstBundleLock>(Context.getCur())) {
- PauseNopInsertion = true;
- } else if (llvm::isa<InstBundleUnlock>(Context.getCur())) {
- PauseNopInsertion = false;
- }
- if (!PauseNopInsertion)
- Target->doNopInsertion(RNG);
- // Ensure Cur=Next, so that the nops are inserted before the current
- // instruction rather than after.
- Context.advanceCur();
- Context.advanceNext();
- }
-}
-
// Drives the target lowering. Passes the current instruction and the next
// non-deleted instruction for target lowering.
void CfgNode::genCode() {
diff --git a/third_party/subzero/src/IceCfgNode.h b/third_party/subzero/src/IceCfgNode.h
index 3406bd8..729dfe8 100644
--- a/third_party/subzero/src/IceCfgNode.h
+++ b/third_party/subzero/src/IceCfgNode.h
@@ -102,7 +102,6 @@
void deletePhis();
void advancedPhiLowering();
void doAddressOpt();
- void doNopInsertion(RandomNumberGenerator &RNG);
void genCode();
void livenessLightweight();
bool liveness(Liveness *Liveness);
diff --git a/third_party/subzero/src/IceClFlags.def b/third_party/subzero/src/IceClFlags.def
index 30bde36..690669e 100644
--- a/third_party/subzero/src/IceClFlags.def
+++ b/third_party/subzero/src/IceClFlags.def
@@ -239,56 +239,13 @@
X(ParseParallel, bool, dev_opt_flag, "parse-parallel", \
cl::desc("Parse function blocks in parallel"), cl::init(true)) \
\
- X(RandomizeAndPoolImmediatesOption, Ice::RandomizeAndPoolImmediatesEnum, \
- dev_opt_flag, "randomize-pool-immediates", \
- cl::desc("Randomize or pooling the representation of immediates"), \
- cl::init(Ice::RPI_None), \
- cl::values(clEnumValN(Ice::RPI_None, "none", \
- "Do not randomize or pooling immediates (default)"), \
- clEnumValN(Ice::RPI_Randomize, "randomize", \
- "Turn on immediate constants blinding"), \
- clEnumValN(Ice::RPI_Pool, "pool", \
- "Turn on immediate constants pooling") \
- CLENUMVALEND)) \
- \
- X(RandomizeAndPoolImmediatesThreshold, uint32_t, dev_opt_flag, \
- "randomize-pool-threshold", \
- cl::desc("The threshold for immediates randomization and pooling"), \
- cl::init(0xffff)) \
- \
- X(RandomizeRegisterAllocation, bool, dev_opt_flag, "randomize-regalloc", \
- cl::desc("Randomize register allocation"), cl::init(false)) \
- \
X(SplitLocalVars, bool, dev_opt_flag, "split-local-vars", cl::init(true), \
cl::desc("Block-local variable splitting (O2 only)")) \
\
- X(RandomSeed, unsigned long long, dev_opt_flag, "sz-seed", \
- cl::desc("Seed the random number generator"), cl::init(1)) \
- \
X(RegAllocReserve, bool, dev_opt_flag, "reg-reserve", \
cl::desc("Let register allocation use reserve registers"), \
cl::init(false)) \
\
- X(ReorderBasicBlocks, bool, dev_opt_flag, "reorder-basic-blocks", \
- cl::desc("Shuffle the layout of basic blocks in each function"), \
- cl::init(false)) \
- \
- X(ReorderFunctions, bool, dev_opt_flag, "reorder-functions", \
- cl::desc("Randomize function ordering"), cl::init(false)) \
- \
- X(ReorderFunctionsWindowSize, uint32_t, dev_opt_flag, \
- "reorder-functions-window-size", \
- cl::desc( \
- "The shuffling window size for function reordering. 1 or 0 means " \
- "no effective shuffling."), \
- cl::init(8)) \
- \
- X(ReorderGlobalVariables, bool, dev_opt_flag, "reorder-global-variables", \
- cl::desc("Randomize global data ordering"), cl::init(false)) \
- \
- X(ReorderPooledConstants, bool, dev_opt_flag, "reorder-pooled-constants", \
- cl::desc("Randomize constant pool entry ordering"), cl::init(false)) \
- \
X(RepeatRegAlloc, bool, dev_opt_flag, "regalloc-repeat", \
cl::desc("Repeat register allocation until convergence"), cl::init(true)) \
\
@@ -297,9 +254,6 @@
cl::desc("Instrument compiled code with Address Sanitizer"), \
cl::init(false)) \
\
- X(ShouldDoNopInsertion, bool, dev_opt_flag, "nop-insertion", \
- cl::desc("Randomly insert NOPs"), cl::init(false)) \
- \
X(SkipUnimplemented, bool, dev_opt_flag, "skip-unimplemented", \
cl::desc("Skip through unimplemented lowering code instead of aborting."), \
cl::init(false)) \
@@ -369,7 +323,6 @@
clEnumValN(Ice::IceV_LinearScan, "regalloc", "Linear scan details"), \
clEnumValN(Ice::IceV_Frame, "frame", "Stack frame layout details"), \
clEnumValN(Ice::IceV_AddrOpt, "addropt", "Address mode optimization"), \
- clEnumValN(Ice::IceV_Random, "random", "Randomization details"), \
clEnumValN(Ice::IceV_Folding, "fold", "Instruction folding details"), \
clEnumValN(Ice::IceV_RMW, "rmw", "ReadModifyWrite optimization"), \
clEnumValN(Ice::IceV_Loop, "loop", "Loop nest depth analysis"), \
diff --git a/third_party/subzero/src/IceDefs.h b/third_party/subzero/src/IceDefs.h
index c5f7f5d..01a8f35 100644
--- a/third_party/subzero/src/IceDefs.h
+++ b/third_party/subzero/src/IceDefs.h
@@ -345,11 +345,10 @@
IceV_LinearScan = 1 << 7,
IceV_Frame = 1 << 8,
IceV_AddrOpt = 1 << 9,
- IceV_Random = 1 << 10,
- IceV_Folding = 1 << 11,
- IceV_RMW = 1 << 12,
- IceV_Loop = 1 << 13,
- IceV_Mem = 1 << 14,
+ IceV_Folding = 1 << 10,
+ IceV_RMW = 1 << 11,
+ IceV_Loop = 1 << 12,
+ IceV_Mem = 1 << 13,
// Leave some extra space to make it easier to add new per-pass items.
IceV_NO_PER_PASS_DUMP_BEYOND = 1 << 19,
// Items greater than IceV_NO_PER_PASS_DUMP_BEYOND don't by themselves trigger
@@ -446,21 +445,6 @@
return llvm::make_range(Container.rbegin(), Container.rend());
}
-/// Options for pooling and randomization of immediates.
-enum RandomizeAndPoolImmediatesEnum { RPI_None, RPI_Randomize, RPI_Pool };
-
-/// Salts for Random number generator for different randomization passes.
-enum RandomizationPassesEnum {
- RPE_BasicBlockReordering,
- RPE_ConstantBlinding,
- RPE_FunctionReordering,
- RPE_GlobalVariableReordering,
- RPE_NopInsertion,
- RPE_PooledConstantReordering,
- RPE_RegAllocRandomization,
- RPE_num
-};
-
using RelocOffsetArray = llvm::SmallVector<class RelocOffset *, 4>;
} // end of namespace Ice
diff --git a/third_party/subzero/src/IceELFObjectWriter.cpp b/third_party/subzero/src/IceELFObjectWriter.cpp
index 1f375c6..9f41af6 100644
--- a/third_party/subzero/src/IceELFObjectWriter.cpp
+++ b/third_party/subzero/src/IceELFObjectWriter.cpp
@@ -542,17 +542,6 @@
constexpr SizeT SymbolSize = 0;
Section->setFileOffset(alignFileOffset(Align));
- // If the -reorder-pooled-constant option is set to true, we should shuffle
- // the constants before we emit them.
- if (getFlags().getReorderPooledConstants() && !Pool.empty()) {
- // Use the constant's kind value as the salt for creating random number
- // generator.
- Operand::OperandKind K = (*Pool.begin())->getKind();
- RandomNumberGenerator RNG(getFlags().getRandomSeed(),
- RPE_PooledConstantReordering, K);
- RandomShuffle(Pool.begin(), Pool.end(),
- [&RNG](uint64_t N) { return (uint32_t)RNG.next(N); });
- }
// Write the data.
for (Constant *C : Pool) {
if (!C->getShouldBePooled())
diff --git a/third_party/subzero/src/IceGlobalContext.cpp b/third_party/subzero/src/IceGlobalContext.cpp
index f7cf65f..ecfec85 100644
--- a/third_party/subzero/src/IceGlobalContext.cpp
+++ b/third_party/subzero/src/IceGlobalContext.cpp
@@ -497,15 +497,6 @@
if (getFlags().getDisableTranslation())
return;
- // If we need to shuffle the layout of global variables, shuffle them now.
- if (getFlags().getReorderGlobalVariables()) {
- // Create a random number generator for global variable reordering.
- RandomNumberGenerator RNG(getFlags().getRandomSeed(),
- RPE_GlobalVariableReordering);
- RandomShuffle(Globals.begin(), Globals.end(),
- [&RNG](int N) { return (uint32_t)RNG.next(N); });
- }
-
if (!BuildDefs::minimal() && Instrumentor)
Instrumentor->instrumentGlobals(Globals);
@@ -535,11 +526,6 @@
uint32_t ShuffleStartIndex = DesiredSequenceNumber;
uint32_t ShuffleEndIndex = DesiredSequenceNumber;
bool EmitQueueEmpty = false;
- const uint32_t ShuffleWindowSize =
- std::max(1u, getFlags().getReorderFunctionsWindowSize());
- bool Shuffle = Threaded && getFlags().getReorderFunctions();
- // Create a random number generator for function reordering.
- RandomNumberGenerator RNG(getFlags().getRandomSeed(), RPE_FunctionReordering);
while (!EmitQueueEmpty) {
resizePending(&Pending, DesiredSequenceNumber);
@@ -566,7 +552,6 @@
Pending[DesiredSequenceNumber] = std::move(RawItem);
}
}
- const auto *CurrentWorkItem = Pending[DesiredSequenceNumber].get();
// We have the desired EmitterWorkItem or nullptr as the end notifier.
// If the emitter queue is not empty, increase DesiredSequenceNumber and
@@ -576,26 +561,6 @@
ShuffleEndIndex++;
}
- if (Shuffle) {
- // Continue fetching EmitterWorkItem if function reordering is turned on,
- // and emit queue is not empty, and the number of consecutive pending
- // items is smaller than the window size, and RawItem is not a
- // WI_GlobalInits kind. Emit WI_GlobalInits kind block first to avoid
- // holding an arbitrarily large GlobalDeclarationList.
- if (!EmitQueueEmpty &&
- ShuffleEndIndex - ShuffleStartIndex < ShuffleWindowSize &&
- CurrentWorkItem->getKind() != EmitterWorkItem::WI_GlobalInits)
- continue;
-
- // Emit the EmitterWorkItem between Pending[ShuffleStartIndex] to
- // Pending[ShuffleEndIndex]. If function reordering turned on, shuffle the
- // pending items from Pending[ShuffleStartIndex] to
- // Pending[ShuffleEndIndex].
- RandomShuffle(Pending.begin() + ShuffleStartIndex,
- Pending.begin() + ShuffleEndIndex,
- [&RNG](uint64_t N) { return (uint32_t)RNG.next(N); });
- }
-
// Emit the item from ShuffleStartIndex to ShuffleEndIndex.
for (uint32_t I = ShuffleStartIndex; I < ShuffleEndIndex; I++) {
std::unique_ptr<EmitterWorkItem> Item = std::move(Pending[I]);
@@ -853,17 +818,6 @@
return A.getId() < B.getId();
});
- if (getFlags().getReorderPooledConstants()) {
- // If reorder-pooled-constants option is set to true, we also shuffle the
- // jump tables before emitting them.
-
- // Create a random number generator for jump tables reordering, considering
- // jump tables as pooled constants.
- RandomNumberGenerator RNG(getFlags().getRandomSeed(),
- RPE_PooledConstantReordering);
- RandomShuffle(JumpTables.begin(), JumpTables.end(),
- [&RNG](uint64_t N) { return (uint32_t)RNG.next(N); });
- }
return JumpTables;
}
diff --git a/third_party/subzero/src/IceGlobalContext.h b/third_party/subzero/src/IceGlobalContext.h
index 4c15905..19f7a53 100644
--- a/third_party/subzero/src/IceGlobalContext.h
+++ b/third_party/subzero/src/IceGlobalContext.h
@@ -20,7 +20,6 @@
#include "IceDefs.h"
#include "IceInstrumentation.h"
#include "IceIntrinsics.h"
-#include "IceRNG.h"
#include "IceStringPool.h"
#include "IceSwitchLowering.h"
#include "IceTargetLowering.def"
diff --git a/third_party/subzero/src/IceOperand.h b/third_party/subzero/src/IceOperand.h
index ae65523..9229656 100644
--- a/third_party/subzero/src/IceOperand.h
+++ b/third_party/subzero/src/IceOperand.h
@@ -154,11 +154,6 @@
const GlobalString getLabelName() const { return LabelName; }
- /// Judge if this given immediate should be randomized or pooled By default
- /// should return false, only constant integers should truly go through this
- /// method.
- virtual bool shouldBeRandomizedOrPooled() const { return false; }
-
bool getShouldBePooled() const { return ShouldBePooled; }
// This should be thread-safe because the constant pool lock is acquired
@@ -223,8 +218,6 @@
SizeT hashValue() const override { return std::hash<PrimType>()(Value); }
- virtual bool shouldBeRandomizedOrPooled() const override { return false; }
-
private:
ConstantPrimitive(Type Ty, PrimType Value) : Constant(K, Ty), Value(Value) {}
@@ -294,22 +287,6 @@
Str << static_cast<int32_t>(getValue());
}
-// =========== Immediate Randomization and Pooling routines ==============
-// Specialization of the template member function for ConstantInteger32
-// TODO(stichnot): try to move this specialization into a target-specific file.
-template <> inline bool ConstantInteger32::shouldBeRandomizedOrPooled() const {
- uint32_t Threshold = getFlags().getRandomizeAndPoolImmediatesThreshold();
- if (getFlags().getRandomizeAndPoolImmediatesOption() == RPI_None)
- return false;
- if (getType() != IceType_i32 && getType() != IceType_i16 &&
- getType() != IceType_i8)
- return false;
- // The Following checks if the signed representation of Value is between
- // -Threshold/2 and +Threshold/2
- bool largerThanThreshold = Threshold / 2 + Value >= Threshold;
- return largerThanThreshold;
-}
-
template <>
inline void ConstantInteger64::dump(const Cfg *, Ostream &Str) const {
if (!BuildDefs::dump())
diff --git a/third_party/subzero/src/IceRNG.cpp b/third_party/subzero/src/IceRNG.cpp
deleted file mode 100644
index b0d9077..0000000
--- a/third_party/subzero/src/IceRNG.cpp
+++ /dev/null
@@ -1,56 +0,0 @@
-//===- subzero/src/IceRNG.cpp - PRNG implementation -----------------------===//
-//
-// The Subzero Code Generator
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-///
-/// \file
-/// \brief Implements the random number generator.
-///
-//===----------------------------------------------------------------------===//
-
-#include "IceRNG.h"
-
-#include <climits>
-#include <ctime>
-
-namespace Ice {
-
-namespace {
-constexpr unsigned MAX = 2147483647;
-} // end of anonymous namespace
-
-// TODO(wala,stichnot): Switch to RNG implementation from LLVM or C++11.
-//
-// TODO(wala,stichnot): Make it possible to replay the RNG sequence in a
-// subsequent run, for reproducing a bug. Print the seed in a comment in the
-// asm output. Embed the seed in the binary via metadata that an attacker can't
-// introspect.
-RandomNumberGenerator::RandomNumberGenerator(uint64_t Seed, llvm::StringRef)
- : State(Seed) {}
-
-RandomNumberGenerator::RandomNumberGenerator(
- uint64_t Seed, RandomizationPassesEnum RandomizationPassID, uint64_t Salt) {
- constexpr unsigned NumBitsGlobalSeed = CHAR_BIT * sizeof(State);
- constexpr unsigned NumBitsPassID = 4;
- constexpr unsigned NumBitsSalt = 12;
- static_assert(RPE_num < (1 << NumBitsPassID), "NumBitsPassID too small");
- State =
- Seed ^
- ((uint64_t)RandomizationPassID << (NumBitsGlobalSeed - NumBitsPassID)) ^
- (Salt << (NumBitsGlobalSeed - NumBitsPassID - NumBitsSalt));
-}
-uint64_t RandomNumberGenerator::next(uint64_t Max) {
- // Lewis, Goodman, and Miller (1969)
- State = (16807 * State) % MAX;
- return State % Max;
-}
-
-bool RandomNumberGeneratorWrapper::getTrueWithProbability(float Probability) {
- return static_cast<float>(RNG.next(MAX)) < Probability * static_cast<float>(MAX);
-}
-
-} // end of namespace Ice
diff --git a/third_party/subzero/src/IceRNG.h b/third_party/subzero/src/IceRNG.h
deleted file mode 100644
index 354337c..0000000
--- a/third_party/subzero/src/IceRNG.h
+++ /dev/null
@@ -1,85 +0,0 @@
-//===- subzero/src/IceRNG.h - Random number generator -----------*- C++ -*-===//
-//
-// The Subzero Code Generator
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-///
-/// \file
-/// \brief Declares a random number generator.
-///
-//===----------------------------------------------------------------------===//
-
-#ifndef SUBZERO_SRC_ICERNG_H
-#define SUBZERO_SRC_ICERNG_H
-
-#include "IceDefs.h"
-#include "llvm/ADT/StringRef.h"
-#include "llvm/Support/Compiler.h"
-
-#include <cstdint>
-
-namespace Ice {
-
-class RandomNumberGenerator {
- RandomNumberGenerator() = delete;
- RandomNumberGenerator(const RandomNumberGenerator &) = delete;
- RandomNumberGenerator &operator=(const RandomNumberGenerator &) = delete;
-
-public:
- explicit RandomNumberGenerator(uint64_t Seed, llvm::StringRef Salt = "");
- /// Create a random number generator with: global seed, randomization pass ID
- /// and a salt uint64_t integer.
- /// @param Seed should be a global seed.
- /// @param RandomizationPassID should be one of RandomizationPassesEnum.
- /// @param Salt should be an additional integer input for generating unique
- /// RNG.
- /// The global seed is 64 bits; since it is likely to originate from the
- /// system time, the lower bits are more "valuable" than the upper bits. As
- /// such, we merge the randomization pass ID and the salt into the global seed
- /// by xor'ing them into high bit ranges. We expect the pass ID to fit within
- /// 4 bits, so it gets shifted by 60 to merge into the upper 4 bits. We expect
- /// the salt (usually the function sequence number) to fit within 12 bits, so
- /// it gets shifted by 48 before merging.
- explicit RandomNumberGenerator(uint64_t Seed,
- RandomizationPassesEnum RandomizationPassID,
- uint64_t Salt = 0);
- uint64_t next(uint64_t Max);
-
-private:
- uint64_t State;
-};
-
-/// This class adds additional random number generator utilities. The reason for
-/// the wrapper class is that we want to keep the RandomNumberGenerator
-/// interface identical to LLVM's.
-class RandomNumberGeneratorWrapper {
- RandomNumberGeneratorWrapper() = delete;
- RandomNumberGeneratorWrapper(const RandomNumberGeneratorWrapper &) = delete;
- RandomNumberGeneratorWrapper &
- operator=(const RandomNumberGeneratorWrapper &) = delete;
-
-public:
- uint64_t operator()(uint64_t Max) { return RNG.next(Max); }
- bool getTrueWithProbability(float Probability);
- explicit RandomNumberGeneratorWrapper(RandomNumberGenerator &RNG)
- : RNG(RNG) {}
-
-private:
- RandomNumberGenerator &RNG;
-};
-
-/// RandomShuffle is an implementation of std::random_shuffle() that doesn't
-/// change across stdlib implementations. Adapted from a sample implementation
-/// at cppreference.com.
-template <class RandomIt, class RandomFunc>
-void RandomShuffle(RandomIt First, RandomIt Last, RandomFunc &&RNG) {
- for (auto i = Last - First - 1; i > 0; --i)
- std::swap(First[i], First[RNG(i + 1)]);
-}
-
-} // end of namespace Ice
-
-#endif // SUBZERO_SRC_ICERNG_H
diff --git a/third_party/subzero/src/IceRegAlloc.cpp b/third_party/subzero/src/IceRegAlloc.cpp
index 348f256..4007334 100644
--- a/third_party/subzero/src/IceRegAlloc.cpp
+++ b/third_party/subzero/src/IceRegAlloc.cpp
@@ -779,32 +779,13 @@
dumpLiveRangeTrace("Allocating Z ", Iter.Cur);
}
-void LinearScan::assignFinalRegisters(const SmallBitVector &RegMaskFull,
- const SmallBitVector &PreDefinedRegisters,
- bool Randomized) {
- const size_t NumRegisters = RegMaskFull.size();
- llvm::SmallVector<RegNumT, REGS_SIZE> Permutation(NumRegisters);
- if (Randomized) {
- // Create a random number generator for regalloc randomization. Merge
- // function's sequence and Kind value as the Salt. Because regAlloc() is
- // called twice under O2, the second time with RAK_Phi, we check Kind ==
- // RAK_Phi to determine the lowest-order bit to make sure the Salt is
- // different.
- uint64_t Salt =
- (Func->getSequenceNumber() << 1) ^ (Kind == RAK_Phi ? 0u : 1u);
- Target->makeRandomRegisterPermutation(
- Permutation, PreDefinedRegisters | ~RegMaskFull, Salt);
- }
-
+void LinearScan::assignFinalRegisters(const SmallBitVector &RegMaskFull) {
// Finish up by setting RegNum = RegNumTmp (or a random permutation thereof)
// for each Variable.
for (Variable *Item : Handled) {
const auto RegNum = Item->getRegNumTmp();
auto AssignedRegNum = RegNum;
- if (Randomized && Item->hasRegTmp() && !Item->hasReg()) {
- AssignedRegNum = Permutation[RegNum];
- }
if (BuildDefs::dump() && Verbose) {
Ostream &Str = Ctx->getStrDump();
if (!Item->hasRegTmp()) {
@@ -833,19 +814,13 @@
//
// Requires running Cfg::liveness(Liveness_Intervals) in preparation. Results
// are assigned to Variable::RegNum for each Variable.
-void LinearScan::scan(const SmallBitVector &RegMaskFull, bool Randomized) {
+void LinearScan::scan(const SmallBitVector &RegMaskFull) {
TimerMarker T(TimerStack::TT_linearScan, Func);
assert(RegMaskFull.any()); // Sanity check
if (Verbose)
Ctx->lockStr();
Func->resetCurrentNode();
const size_t NumRegisters = RegMaskFull.size();
- SmallBitVector PreDefinedRegisters(NumRegisters);
- if (Randomized) {
- for (Variable *Var : UnhandledPrecolored) {
- PreDefinedRegisters[Var->getRegNum()] = true;
- }
- }
// Build a LiveRange representing the Kills list.
LiveRange KillsRange(Kills);
@@ -977,7 +952,7 @@
Inactive.clear();
dump(Func);
- assignFinalRegisters(RegMaskFull, PreDefinedRegisters, Randomized);
+ assignFinalRegisters(RegMaskFull);
if (Verbose)
Ctx->unlockStr();
diff --git a/third_party/subzero/src/IceRegAlloc.h b/third_party/subzero/src/IceRegAlloc.h
index 896e178..ce0f9c9 100644
--- a/third_party/subzero/src/IceRegAlloc.h
+++ b/third_party/subzero/src/IceRegAlloc.h
@@ -33,7 +33,7 @@
public:
explicit LinearScan(Cfg *Func);
void init(RegAllocKind Kind, CfgSet<Variable *> ExcludeVars);
- void scan(const SmallBitVector &RegMask, bool Randomized);
+ void scan(const SmallBitVector &RegMask);
// Returns the number of times some variable has been assigned a register but
// later evicted because of a higher-priority allocation. The idea is that we
// can implement "second-chance bin-packing" by rerunning register allocation
@@ -105,9 +105,7 @@
void allocatePreferredRegister(IterationState &Iter);
void allocateFreeRegister(IterationState &Iter, bool Filtered);
void handleNoFreeRegisters(IterationState &Iter);
- void assignFinalRegisters(const SmallBitVector &RegMaskFull,
- const SmallBitVector &PreDefinedRegisters,
- bool Randomized);
+ void assignFinalRegisters(const SmallBitVector &RegMaskFull);
/// @}
void dumpLiveRangeTrace(const char *Label, const Variable *Item);
diff --git a/third_party/subzero/src/IceTargetLowering.cpp b/third_party/subzero/src/IceTargetLowering.cpp
index 1381f03..1a7500e 100644
--- a/third_party/subzero/src/IceTargetLowering.cpp
+++ b/third_party/subzero/src/IceTargetLowering.cpp
@@ -375,19 +375,6 @@
Context.advanceNext();
}
-void TargetLowering::doNopInsertion(RandomNumberGenerator &RNG) {
- Inst *I = iteratorToInst(Context.getCur());
- bool ShouldSkip = llvm::isa<InstFakeUse>(I) || llvm::isa<InstFakeDef>(I) ||
- llvm::isa<InstFakeKill>(I) || I->isRedundantAssign() ||
- I->isDeleted();
- if (!ShouldSkip) {
- int Probability = getFlags().getNopProbabilityAsPercentage();
- for (int I = 0; I < getFlags().getMaxNopsPerInstruction(); ++I) {
- randomlyInsertNop(Probability / 100.0, RNG);
- }
- }
-}
-
// Lowers a single instruction according to the information in Context, by
// checking the Context.Cur instruction kind and calling the appropriate
// lowering method. The lowering method should insert target instructions at
@@ -524,7 +511,7 @@
CfgSet<Variable *> EmptySet;
do {
LinearScan.init(Kind, EmptySet);
- LinearScan.scan(RegMask, getFlags().getRandomizeRegisterAllocation());
+ LinearScan.scan(RegMask);
if (!LinearScan.hasEvictions())
Repeat = false;
Kind = RAK_SecondChance;
@@ -653,7 +640,7 @@
// Run the register allocator with all these new variables included
LinearScan RegAlloc(Func);
RegAlloc.init(RAK_Global, SplitCandidates);
- RegAlloc.scan(RegMask, getFlags().getRandomizeRegisterAllocation());
+ RegAlloc.scan(RegMask);
// Modify the Cfg to use the new variables that now have registers.
for (auto *ExtraVar : ExtraVars) {
diff --git a/third_party/subzero/src/IceTargetLowering.h b/third_party/subzero/src/IceTargetLowering.h
index ef81514..a62e26e 100644
--- a/third_party/subzero/src/IceTargetLowering.h
+++ b/third_party/subzero/src/IceTargetLowering.h
@@ -215,8 +215,6 @@
void genTargetHelperCalls();
/// Tries to do address mode optimization on a single instruction.
void doAddressOpt();
- /// Randomly insert NOPs.
- void doNopInsertion(RandomNumberGenerator &RNG);
/// Lowers a single non-Phi instruction.
void lower();
/// Inserts and lowers a single high-level instruction at a specific insertion
@@ -307,11 +305,6 @@
void regAlloc(RegAllocKind Kind);
void postRegallocSplitting(const SmallBitVector &RegMask);
- virtual void
- makeRandomRegisterPermutation(llvm::SmallVectorImpl<RegNumT> &Permutation,
- const SmallBitVector &ExcludeRegisters,
- uint64_t Salt) const = 0;
-
/// Get the minimum number of clusters required for a jump table to be
/// considered.
virtual SizeT getMinJumpTableSize() const = 0;
@@ -429,8 +422,6 @@
virtual void doAddressOptLoadSubVector() {}
virtual void doAddressOptStoreSubVector() {}
virtual void doMockBoundsCheck(Operand *) {}
- virtual void randomlyInsertNop(float Probability,
- RandomNumberGenerator &RNG) = 0;
/// This gives the target an opportunity to post-process the lowered expansion
/// before returning.
virtual void postLower() {}
diff --git a/third_party/subzero/src/IceTargetLoweringARM32.cpp b/third_party/subzero/src/IceTargetLoweringARM32.cpp
index 3795c04..750374e 100644
--- a/third_party/subzero/src/IceTargetLoweringARM32.cpp
+++ b/third_party/subzero/src/IceTargetLoweringARM32.cpp
@@ -1103,11 +1103,6 @@
// to reduce the amount of work needed for searching for opportunities.
Func->doBranchOpt();
Func->dump("After branch optimization");
-
- // Nop insertion
- if (getFlags().getShouldDoNopInsertion()) {
- Func->doNopInsertion();
- }
}
void TargetARM32::translateOm1() {
@@ -1165,11 +1160,6 @@
if (Func->hasError())
return;
Func->dump("After postLowerLegalization");
-
- // Nop insertion
- if (getFlags().getShouldDoNopInsertion()) {
- Func->doNopInsertion();
- }
}
uint32_t TargetARM32::getStackAlignment() const {
@@ -5925,14 +5915,6 @@
}
}
-void TargetARM32::randomlyInsertNop(float Probability,
- RandomNumberGenerator &RNG) {
- RandomNumberGeneratorWrapper RNGW(RNG);
- if (RNGW.getTrueWithProbability(Probability)) {
- _nop();
- }
-}
-
void TargetARM32::lowerPhi(const InstPhi * /*Instr*/) {
Func->setError("Phi found in regular instruction list");
}
@@ -6650,15 +6632,6 @@
Context.availabilityUpdate();
}
-void TargetARM32::makeRandomRegisterPermutation(
- llvm::SmallVectorImpl<RegNumT> &Permutation,
- const SmallBitVector &ExcludeRegisters, uint64_t Salt) const {
- (void)Permutation;
- (void)ExcludeRegisters;
- (void)Salt;
- UnimplementedError(getFlags());
-}
-
void TargetARM32::emit(const ConstantInteger32 *C) const {
if (!BuildDefs::dump())
return;
@@ -7318,11 +7291,6 @@
<< "\n"
<< "\t.align\t" << Align << "\n";
- if (getFlags().getReorderPooledConstants()) {
- // TODO(jpp): add constant pooling.
- UnimplementedError(getFlags());
- }
-
for (Constant *C : Pool) {
if (!C->getShouldBePooled()) {
continue;
diff --git a/third_party/subzero/src/IceTargetLoweringARM32.h b/third_party/subzero/src/IceTargetLoweringARM32.h
index 51cb63e..d0ac253 100644
--- a/third_party/subzero/src/IceTargetLoweringARM32.h
+++ b/third_party/subzero/src/IceTargetLoweringARM32.h
@@ -296,8 +296,6 @@
void genTargetHelperCallFor(Inst *Instr) override;
void doAddressOptLoad() override;
void doAddressOptStore() override;
- void randomlyInsertNop(float Probability,
- RandomNumberGenerator &RNG) override;
OperandARM32Mem *formMemoryOperand(Operand *Ptr, Type Ty);
@@ -311,11 +309,6 @@
/// Returns a vector in a register with the given constant entries.
Variable *makeVectorOfZeros(Type Ty, RegNumT RegNum = RegNumT());
- void
- makeRandomRegisterPermutation(llvm::SmallVectorImpl<RegNumT> &Permutation,
- const SmallBitVector &ExcludeRegisters,
- uint64_t Salt) const override;
-
// If a divide-by-zero check is needed, inserts a: test; branch .LSKIP; trap;
// .LSKIP: <continuation>. If no check is needed nothing is inserted.
void div0Check(Type Ty, Operand *SrcLo, Operand *SrcHi);
diff --git a/third_party/subzero/src/IceTargetLoweringMIPS32.cpp b/third_party/subzero/src/IceTargetLoweringMIPS32.cpp
index eb9367c..a36401b 100644
--- a/third_party/subzero/src/IceTargetLoweringMIPS32.cpp
+++ b/third_party/subzero/src/IceTargetLoweringMIPS32.cpp
@@ -585,13 +585,7 @@
Intrinsics::IntrinsicID ID = Intrinsic->getIntrinsicID();
if (isVectorType(DestTy) && ID == Intrinsics::Fabs) {
Operand *Src0 = Intrinsic->getArg(0);
- GlobalString FabsFloat = Ctx->getGlobalString("llvm.fabs.f32");
- Operand *CallTarget = Ctx->getConstantExternSym(FabsFloat);
- GlobalString FabsVec = Ctx->getGlobalString("llvm.fabs.v4f32");
- bool BadIntrinsic = false;
- const Intrinsics::FullIntrinsicInfo *FullInfo =
- Ctx->getIntrinsicsInfo().find(FabsVec, BadIntrinsic);
- Intrinsics::IntrinsicInfo Info = FullInfo->Info;
+ Intrinsics::IntrinsicInfo Info = Intrinsic->getIntrinsicInfo();
Variable *T = Func->makeVariable(IceType_v4f32);
auto *Undef = ConstantUndef::create(Ctx, IceType_v4f32);
@@ -605,8 +599,7 @@
Context.insert<InstExtractElement>(Op, Src0, Index);
auto *Res = Func->makeVariable(IceType_f32);
Variable *DestT = Func->makeVariable(IceType_v4f32);
- auto *Intrinsic =
- Context.insert<InstIntrinsic>(1, Res, CallTarget, Info);
+ auto *Intrinsic = Context.insert<InstIntrinsic>(1, Res, Info);
Intrinsic->addArg(Op);
Context.insert<InstInsertElement>(DestT, T, Res, Index);
T = DestT;
@@ -965,11 +958,6 @@
// to reduce the amount of work needed for searching for opportunities.
Func->doBranchOpt();
Func->dump("After branch optimization");
-
- // Nop insertion
- if (getFlags().getShouldDoNopInsertion()) {
- Func->doNopInsertion();
- }
}
void TargetMIPS32::translateOm1() {
@@ -1019,11 +1007,6 @@
if (Func->hasError())
return;
Func->dump("After postLowerLegalization");
-
- // Nop insertion
- if (getFlags().getShouldDoNopInsertion()) {
- Func->doNopInsertion();
- }
}
bool TargetMIPS32::doBranchOpt(Inst *Instr, const CfgNode *NextNode) {
@@ -5446,14 +5429,6 @@
}
}
-void TargetMIPS32::randomlyInsertNop(float Probability,
- RandomNumberGenerator &RNG) {
- RandomNumberGeneratorWrapper RNGW(RNG);
- if (RNGW.getTrueWithProbability(Probability)) {
- _nop();
- }
-}
-
void TargetMIPS32::lowerPhi(const InstPhi * /*Instr*/) {
Func->setError("Phi found in regular instruction list");
}
@@ -5604,7 +5579,7 @@
void TargetMIPS32::lowerStore(const InstStore *Instr) {
Operand *Value = Instr->getData();
- Operand *Addr = Instr->getAddr();
+ Operand *Addr = Instr->getStoreAddress();
OperandMIPS32Mem *NewAddr = formMemoryOperand(Addr, Value->getType());
Type Ty = NewAddr->getType();
@@ -5706,15 +5681,6 @@
Context.availabilityUpdate();
}
-void TargetMIPS32::makeRandomRegisterPermutation(
- llvm::SmallVectorImpl<RegNumT> &Permutation,
- const SmallBitVector &ExcludeRegisters, uint64_t Salt) const {
- (void)Permutation;
- (void)ExcludeRegisters;
- (void)Salt;
- UnimplementedError(getFlags());
-}
-
/* TODO(jvoung): avoid duplicate symbols with multiple targets.
void ConstantUndef::emitWithoutDollar(GlobalContext *) const {
llvm_unreachable("Not expecting to emitWithoutDollar undef");
@@ -5832,10 +5798,6 @@
Str << "\t.section\t.rodata.cst" << Align << ",\"aM\",%progbits," << Align
<< "\n"
<< "\t.align\t" << (Align == 4 ? 2 : 3) << "\n";
- if (getFlags().getReorderPooledConstants()) {
- // TODO(jaydeep.patil): add constant pooling.
- UnimplementedError(getFlags());
- }
for (Constant *C : Pool) {
if (!C->getShouldBePooled()) {
continue;
diff --git a/third_party/subzero/src/IceTargetLoweringMIPS32.h b/third_party/subzero/src/IceTargetLoweringMIPS32.h
index 988de6e..858879c 100644
--- a/third_party/subzero/src/IceTargetLoweringMIPS32.h
+++ b/third_party/subzero/src/IceTargetLoweringMIPS32.h
@@ -793,12 +793,6 @@
void genTargetHelperCallFor(Inst *Instr) override;
void doAddressOptLoad() override;
void doAddressOptStore() override;
- void randomlyInsertNop(float Probability,
- RandomNumberGenerator &RNG) override;
- void
- makeRandomRegisterPermutation(llvm::SmallVectorImpl<RegNumT> &Permutation,
- const SmallBitVector &ExcludeRegisters,
- uint64_t Salt) const override;
OperandMIPS32Mem *formMemoryOperand(Operand *Ptr, Type Ty);
diff --git a/third_party/subzero/src/IceTargetLoweringX8632Traits.h b/third_party/subzero/src/IceTargetLoweringX8632Traits.h
index 2f7de46..5b6702b 100644
--- a/third_party/subzero/src/IceTargetLoweringX8632Traits.h
+++ b/third_party/subzero/src/IceTargetLoweringX8632Traits.h
@@ -591,89 +591,6 @@
return Registers;
}
- static void makeRandomRegisterPermutation(
- Cfg *Func, llvm::SmallVectorImpl<RegNumT> &Permutation,
- const SmallBitVector &ExcludeRegisters, uint64_t Salt) {
- // TODO(stichnot): Declaring Permutation this way loses type/size
- // information. Fix this in conjunction with the caller-side TODO.
- assert(Permutation.size() >= RegisterSet::Reg_NUM);
- // Expected upper bound on the number of registers in a single equivalence
- // class. For x86-32, this would comprise the 8 XMM registers. This is for
- // performance, not correctness.
- static const unsigned MaxEquivalenceClassSize = 8;
- using RegisterList = llvm::SmallVector<RegNumT, MaxEquivalenceClassSize>;
- using EquivalenceClassMap = std::map<uint32_t, RegisterList>;
- EquivalenceClassMap EquivalenceClasses;
- SizeT NumShuffled = 0, NumPreserved = 0;
-
-// Build up the equivalence classes of registers by looking at the register
-// properties as well as whether the registers should be explicitly excluded
-// from shuffling.
-#define X(val, encode, name, base, scratch, preserved, stackptr, frameptr, \
- isGPR, is64, is32, is16, is8, isXmm, is64To8, is32To8, is16To8, \
- isTrunc8Rcvr, isAhRcvr, aliases) \
- if (ExcludeRegisters[RegisterSet::val]) { \
- /* val stays the same in the resulting permutation. */ \
- Permutation[RegisterSet::val] = RegisterSet::val; \
- ++NumPreserved; \
- } else { \
- uint32_t AttrKey = 0; \
- uint32_t Index = 0; \
- /* Combine relevant attributes into an equivalence class key. */ \
- Index |= (scratch << (AttrKey++)); \
- Index |= (preserved << (AttrKey++)); \
- Index |= (is8 << (AttrKey++)); \
- Index |= (is16 << (AttrKey++)); \
- Index |= (is32 << (AttrKey++)); \
- Index |= (is64 << (AttrKey++)); \
- Index |= (isXmm << (AttrKey++)); \
- Index |= (is16To8 << (AttrKey++)); \
- Index |= (is32To8 << (AttrKey++)); \
- Index |= (is64To8 << (AttrKey++)); \
- Index |= (isTrunc8Rcvr << (AttrKey++)); \
- /* val is assigned to an equivalence class based on its properties. */ \
- EquivalenceClasses[Index].push_back(RegisterSet::val); \
- }
- REGX8632_TABLE
-#undef X
-
- // Create a random number generator for regalloc randomization.
- RandomNumberGenerator RNG(getFlags().getRandomSeed(),
- RPE_RegAllocRandomization, Salt);
- RandomNumberGeneratorWrapper RNGW(RNG);
-
- // Shuffle the resulting equivalence classes.
- for (auto I : EquivalenceClasses) {
- const RegisterList &List = I.second;
- RegisterList Shuffled(List);
- RandomShuffle(Shuffled.begin(), Shuffled.end(), RNGW);
- for (size_t SI = 0, SE = Shuffled.size(); SI < SE; ++SI) {
- Permutation[List[SI]] = Shuffled[SI];
- ++NumShuffled;
- }
- }
-
- assert(NumShuffled + NumPreserved == RegisterSet::Reg_NUM);
-
- if (Func->isVerbose(IceV_Random)) {
- OstreamLocker L(Func->getContext());
- Ostream &Str = Func->getContext()->getStrDump();
- Str << "Register equivalence classes:\n";
- for (auto I : EquivalenceClasses) {
- Str << "{";
- const RegisterList &List = I.second;
- bool First = true;
- for (RegNumT Register : List) {
- if (!First)
- Str << " ";
- First = false;
- Str << getRegName(Register);
- }
- Str << "}\n";
- }
- }
- }
-
static RegNumT getRaxOrDie() {
llvm::report_fatal_error("no rax in non-64-bit mode.");
}
@@ -896,10 +813,6 @@
return Operand->getKind() == static_cast<OperandKind>(kMem);
}
- void setRandomized(bool R) { Randomized = R; }
-
- bool getRandomized() const { return Randomized; }
-
private:
X86OperandMem(Cfg *Func, Type Ty, Variable *Base, Constant *Offset,
Variable *Index, uint16_t Shift, SegmentRegisters SegmentReg,
@@ -911,10 +824,6 @@
const uint16_t Shift;
const SegmentRegisters SegmentReg : 16;
const bool IsRebased;
- /// A flag to show if this memory operand is a randomized one. Randomized
- /// memory operands are generated in
- /// TargetX86Base::randomizeOrPoolImmediate()
- bool Randomized = false;
};
/// VariableSplit is a way to treat an f64 memory location as a pair of i32
diff --git a/third_party/subzero/src/IceTargetLoweringX8664Traits.h b/third_party/subzero/src/IceTargetLoweringX8664Traits.h
index b8278f6..ac0fa78 100644
--- a/third_party/subzero/src/IceTargetLoweringX8664Traits.h
+++ b/third_party/subzero/src/IceTargetLoweringX8664Traits.h
@@ -636,89 +636,6 @@
return Registers;
}
- static void makeRandomRegisterPermutation(
- Cfg *Func, llvm::SmallVectorImpl<RegNumT> &Permutation,
- const SmallBitVector &ExcludeRegisters, uint64_t Salt) {
- // TODO(stichnot): Declaring Permutation this way loses type/size
- // information. Fix this in conjunction with the caller-side TODO.
- assert(Permutation.size() >= RegisterSet::Reg_NUM);
- // Expected upper bound on the number of registers in a single equivalence
- // class. For x86-64, this would comprise the 16 XMM registers. This is
- // for performance, not correctness.
- static const unsigned MaxEquivalenceClassSize = 8;
- using RegisterList = llvm::SmallVector<RegNumT, MaxEquivalenceClassSize>;
- using EquivalenceClassMap = std::map<uint32_t, RegisterList>;
- EquivalenceClassMap EquivalenceClasses;
- SizeT NumShuffled = 0, NumPreserved = 0;
-
-// Build up the equivalence classes of registers by looking at the register
-// properties as well as whether the registers should be explicitly excluded
-// from shuffling.
-#define X(val, encode, name, base, scratch, preserved, stackptr, frameptr, \
- sboxres, isGPR, is64, is32, is16, is8, isXmm, is64To8, is32To8, \
- is16To8, isTrunc8Rcvr, isAhRcvr, aliases) \
- if (ExcludeRegisters[RegisterSet::val]) { \
- /* val stays the same in the resulting permutation. */ \
- Permutation[RegisterSet::val] = RegisterSet::val; \
- ++NumPreserved; \
- } else { \
- uint32_t AttrKey = 0; \
- uint32_t Index = 0; \
- /* Combine relevant attributes into an equivalence class key. */ \
- Index |= (scratch << (AttrKey++)); \
- Index |= (preserved << (AttrKey++)); \
- Index |= (is8 << (AttrKey++)); \
- Index |= (is16 << (AttrKey++)); \
- Index |= (is32 << (AttrKey++)); \
- Index |= (is64 << (AttrKey++)); \
- Index |= (isXmm << (AttrKey++)); \
- Index |= (is16To8 << (AttrKey++)); \
- Index |= (is32To8 << (AttrKey++)); \
- Index |= (is64To8 << (AttrKey++)); \
- Index |= (isTrunc8Rcvr << (AttrKey++)); \
- /* val is assigned to an equivalence class based on its properties. */ \
- EquivalenceClasses[Index].push_back(RegisterSet::val); \
- }
- REGX8664_TABLE
-#undef X
-
- // Create a random number generator for regalloc randomization.
- RandomNumberGenerator RNG(getFlags().getRandomSeed(),
- RPE_RegAllocRandomization, Salt);
- RandomNumberGeneratorWrapper RNGW(RNG);
-
- // Shuffle the resulting equivalence classes.
- for (const auto &I : EquivalenceClasses) {
- const RegisterList &List = I.second;
- RegisterList Shuffled(List);
- RandomShuffle(Shuffled.begin(), Shuffled.end(), RNGW);
- for (size_t SI = 0, SE = Shuffled.size(); SI < SE; ++SI) {
- Permutation[List[SI]] = Shuffled[SI];
- ++NumShuffled;
- }
- }
-
- assert(NumShuffled + NumPreserved == RegisterSet::Reg_NUM);
-
- if (Func->isVerbose(IceV_Random)) {
- OstreamLocker L(Func->getContext());
- Ostream &Str = Func->getContext()->getStrDump();
- Str << "Register equivalence classes:\n";
- for (const auto &I : EquivalenceClasses) {
- Str << "{";
- const RegisterList &List = I.second;
- bool First = true;
- for (RegNumT Register : List) {
- if (!First)
- Str << " ";
- First = false;
- Str << getRegName(Register);
- }
- Str << "}\n";
- }
- }
- }
-
static RegNumT getRaxOrDie() { return RegisterSet::Reg_rax; }
static RegNumT getRdxOrDie() { return RegisterSet::Reg_rdx; }
@@ -986,10 +903,6 @@
return Operand->getKind() == static_cast<OperandKind>(kMem);
}
- void setRandomized(bool R) { Randomized = R; }
-
- bool getRandomized() const { return Randomized; }
-
private:
X86OperandMem(Cfg *Func, Type Ty, Variable *Base, Constant *Offset,
Variable *Index, uint16_t Shift, bool IsRebased);
@@ -999,10 +912,6 @@
Variable *const Index;
const uint16_t Shift;
const bool IsRebased;
- /// A flag to show if this memory operand is a randomized one. Randomized
- /// memory operands are generated in
- /// TargetX86Base::randomizeOrPoolImmediate()
- bool Randomized = false;
};
/// VariableSplit is a way to treat an f64 memory location as a pair of i32
diff --git a/third_party/subzero/src/IceTargetLoweringX86Base.h b/third_party/subzero/src/IceTargetLoweringX86Base.h
index 4fffd43..364a797 100644
--- a/third_party/subzero/src/IceTargetLoweringX86Base.h
+++ b/third_party/subzero/src/IceTargetLoweringX86Base.h
@@ -316,8 +316,6 @@
void doAddressOptLoadSubVector() override;
void doAddressOptStoreSubVector() override;
void doMockBoundsCheck(Operand *Opnd) override;
- void randomlyInsertNop(float Probability,
- RandomNumberGenerator &RNG) override;
/// Naive lowering of cmpxchg.
void lowerAtomicCmpxchg(Variable *DestPrev, Operand *Ptr, Operand *Expected,
@@ -465,11 +463,6 @@
X86OperandMem *getMemoryOperandForStackSlot(Type Ty, Variable *Slot,
uint32_t Offset = 0);
- void
- makeRandomRegisterPermutation(llvm::SmallVectorImpl<RegNumT> &Permutation,
- const SmallBitVector &ExcludeRegisters,
- uint64_t Salt) const override;
-
/// AutoMemorySandboxer emits a bundle-lock/bundle-unlock pair if the
/// instruction's operand is a memory reference. This is only needed for
/// x86-64 NaCl sandbox.
@@ -1106,13 +1099,6 @@
// current sandboxing type.
Variable *RebasePtr = nullptr;
- /// Randomize a given immediate operand
- Operand *randomizeOrPoolImmediate(Constant *Immediate,
- RegNumT RegNum = RegNumT());
- X86OperandMem *randomizeOrPoolImmediate(X86OperandMem *MemOperand,
- RegNumT RegNum = RegNumT());
- bool RandomizationPoolingPaused = false;
-
private:
/// dispatchToConcrete is the template voodoo that allows TargetX86Base to
/// invoke methods in Machine (which inherits from TargetX86Base) without
diff --git a/third_party/subzero/src/IceTargetLoweringX86BaseImpl.h b/third_party/subzero/src/IceTargetLoweringX86BaseImpl.h
index fa37f05..d4c41d3 100644
--- a/third_party/subzero/src/IceTargetLoweringX86BaseImpl.h
+++ b/third_party/subzero/src/IceTargetLoweringX86BaseImpl.h
@@ -439,10 +439,7 @@
if (auto *ConstDouble = llvm::dyn_cast<ConstantDouble>(C)) {
return !Utils::isPositiveZero(ConstDouble->getValue());
}
- if (getFlags().getRandomizeAndPoolImmediatesOption() != RPI_Pool) {
- return false;
- }
- return C->shouldBeRandomizedOrPooled();
+ return false;
}
template <typename TraitsType>
@@ -536,11 +533,8 @@
return;
Func->dump("After x86 address mode opt");
- // Disable constant blinding or pooling for load optimization.
- {
- BoolFlagSaver B(RandomizationPoolingPaused, true);
- doLoadOpt();
- }
+ doLoadOpt();
+
Func->genCode();
if (Func->hasError())
return;
@@ -585,9 +579,6 @@
Func->contractEmptyNodes();
Func->reorderNodes();
- // Shuffle basic block order if -reorder-basic-blocks is enabled.
- Func->shuffleNodes();
-
// Branch optimization. This needs to be done just before code emission. In
// particular, no transformations that insert or reorder CfgNodes should be
// done after branch optimization. We go ahead and do it before nop insertion
@@ -595,9 +586,6 @@
Func->doBranchOpt();
Func->dump("After branch optimization");
- // Nop insertion if -nop-insertion is enabled.
- Func->doNopInsertion();
-
// Mark nodes that require sandbox alignment
if (NeedSandboxing) {
Func->markNodesForSandboxing();
@@ -650,12 +638,6 @@
return;
Func->dump("After stack frame mapping");
- // Shuffle basic block order if -reorder-basic-blocks is enabled.
- Func->shuffleNodes();
-
- // Nop insertion if -nop-insertion is enabled.
- Func->doNopInsertion();
-
// Mark nodes that require sandbox alignment
if (NeedSandboxing)
Func->markNodesForSandboxing();
@@ -6133,15 +6115,6 @@
}
template <typename TraitsType>
-void TargetX86Base<TraitsType>::randomlyInsertNop(float Probability,
- RandomNumberGenerator &RNG) {
- RandomNumberGeneratorWrapper RNGW(RNG);
- if (RNGW.getTrueWithProbability(Probability)) {
- _nop(RNGW(Traits::X86_NUM_NOP_VARIANTS));
- }
-}
-
-template <typename TraitsType>
void TargetX86Base<TraitsType>::lowerPhi(const InstPhi * /*Instr*/) {
Func->setError("Phi found in regular instruction list");
}
@@ -7414,9 +7387,6 @@
return;
}
- // Pause constant blinding or pooling, blinding or pooling will be done later
- // during phi lowering assignments
- BoolFlagSaver B(RandomizationPoolingPaused, true);
PhiLowering::prelowerPhis32Bit<TargetX86Base<TraitsType>>(
this, Context.getNode(), Func);
}
@@ -7984,8 +7954,7 @@
Mem->getSegmentRegister());
}
- // For all Memory Operands, we do randomization/pooling here.
- From = randomizeOrPoolImmediate(Mem);
+ From = Mem;
if (!(Allowed & Legal_Mem)) {
From = copyToReg(From, RegNum);
@@ -8016,15 +7985,6 @@
}
}
- // If the operand is an 32 bit constant integer, we should check whether we
- // need to randomize it or pool it.
- if (auto *C = llvm::dyn_cast<ConstantInteger32>(Const)) {
- Operand *NewConst = randomizeOrPoolImmediate(C, RegNum);
- if (NewConst != Const) {
- return NewConst;
- }
- }
-
if (auto *CR = llvm::dyn_cast<ConstantRelocatable>(Const)) {
// If the operand is a ConstantRelocatable, and Legal_AddrAbs is not
// specified, and UseNonsfi is indicated, we need to add RebasePtr.
@@ -8166,25 +8126,16 @@
// later, this save one instruction. By turning blinding and pooling off,
// we guarantee legalize(Offset) will return a Constant*.
if (!llvm::isa<ConstantRelocatable>(Offset)) {
- BoolFlagSaver B(RandomizationPoolingPaused, true);
-
Offset = llvm::cast<Constant>(legalize(Offset));
}
assert(llvm::isa<ConstantInteger32>(Offset) ||
llvm::isa<ConstantRelocatable>(Offset));
}
- // Not completely sure whether it's OK to leave IsRebased unset when
- // creating the mem operand. If DoLegalize is true, it will definitely be
- // applied during the legalize() call, but perhaps not during the
- // randomizeOrPoolImmediate() call. In any case, the emit routines will
- // assert that PIC legalization has been applied.
Mem = X86OperandMem::create(Func, Ty, Base, Offset);
}
- // Do legalization, which contains randomization/pooling or do
- // randomization/pooling.
- return llvm::cast<X86OperandMem>(DoLegalize ? legalize(Mem)
- : randomizeOrPoolImmediate(Mem));
+ // Do legalization, which contains pooling or do pooling.
+ return llvm::cast<X86OperandMem>(DoLegalize ? legalize(Mem) : Mem);
}
template <typename TraitsType>
@@ -8234,14 +8185,6 @@
}
template <typename TraitsType>
-void TargetX86Base<TraitsType>::makeRandomRegisterPermutation(
- llvm::SmallVectorImpl<RegNumT> &Permutation,
- const SmallBitVector &ExcludeRegisters, uint64_t Salt) const {
- Traits::makeRandomRegisterPermutation(Func, Permutation, ExcludeRegisters,
- Salt);
-}
-
-template <typename TraitsType>
void TargetX86Base<TraitsType>::emit(const ConstantInteger32 *C) const {
if (!BuildDefs::dump())
return;
@@ -8293,203 +8236,6 @@
emitWithoutPrefix(C);
}
-/// Randomize or pool an Immediate.
-template <typename TraitsType>
-Operand *
-TargetX86Base<TraitsType>::randomizeOrPoolImmediate(Constant *Immediate,
- RegNumT RegNum) {
- assert(llvm::isa<ConstantInteger32>(Immediate) ||
- llvm::isa<ConstantRelocatable>(Immediate));
- if (getFlags().getRandomizeAndPoolImmediatesOption() == RPI_None ||
- RandomizationPoolingPaused == true) {
- // Immediates randomization/pooling off or paused
- return Immediate;
- }
-
- if (Traits::Is64Bit && NeedSandboxing) {
- // Immediate randomization/pooling is currently disabled for x86-64
- // sandboxing for it could generate invalid memory operands.
- assert(false &&
- "Constant pooling/randomization is disabled for x8664 sandbox.");
- return Immediate;
- }
-
- if (!Immediate->shouldBeRandomizedOrPooled()) {
- // the constant Immediate is not eligible for blinding/pooling
- return Immediate;
- }
- Ctx->statsUpdateRPImms();
- switch (getFlags().getRandomizeAndPoolImmediatesOption()) {
- default:
- llvm::report_fatal_error("Unsupported -randomize-pool-immediates option");
- case RPI_Randomize: {
- // blind the constant
- // FROM:
- // imm
- // TO:
- // insert: mov imm+cookie, Reg
- // insert: lea -cookie[Reg], Reg
- // => Reg
- // If we have already assigned a phy register, we must come from
- // advancedPhiLowering()=>lowerAssign(). In this case we should reuse the
- // assigned register as this assignment is that start of its use-def
- // chain. So we add RegNum argument here. Note we use 'lea' instruction
- // instead of 'xor' to avoid affecting the flags.
- Variable *Reg = makeReg(IceType_i32, RegNum);
- auto *Integer = llvm::cast<ConstantInteger32>(Immediate);
- uint32_t Value = Integer->getValue();
- uint32_t Cookie = Func->getConstantBlindingCookie();
- _mov(Reg, Ctx->getConstantInt(IceType_i32, Cookie + Value));
- Constant *Offset = Ctx->getConstantInt(IceType_i32, 0 - Cookie);
- _lea(Reg, X86OperandMem::create(Func, IceType_i32, Reg, Offset));
- if (Immediate->getType() == IceType_i32) {
- return Reg;
- }
- Variable *TruncReg = makeReg(Immediate->getType(), RegNum);
- _mov(TruncReg, Reg);
- return TruncReg;
- }
- case RPI_Pool: {
- // pool the constant
- // FROM:
- // imm
- // TO:
- // insert: mov $label, Reg
- // => Reg
- assert(getFlags().getRandomizeAndPoolImmediatesOption() == RPI_Pool);
- assert(Immediate->getShouldBePooled());
- // if we have already assigned a phy register, we must come from
- // advancedPhiLowering()=>lowerAssign(). In this case we should reuse the
- // assigned register as this assignment is that start of its use-def
- // chain. So we add RegNum argument here.
- Variable *Reg = makeReg(Immediate->getType(), RegNum);
- constexpr RelocOffsetT Offset = 0;
- Constant *Symbol = Ctx->getConstantSym(Offset, Immediate->getLabelName());
- constexpr Variable *NoBase = nullptr;
- X86OperandMem *MemOperand =
- X86OperandMem::create(Func, Immediate->getType(), NoBase, Symbol);
- _mov(Reg, MemOperand);
- return Reg;
- }
- }
-}
-
-template <typename TraitsType>
-typename TargetX86Base<TraitsType>::X86OperandMem *
-TargetX86Base<TraitsType>::randomizeOrPoolImmediate(X86OperandMem *MemOperand,
- RegNumT RegNum) {
- assert(MemOperand);
- if (getFlags().getRandomizeAndPoolImmediatesOption() == RPI_None ||
- RandomizationPoolingPaused == true) {
- // immediates randomization/pooling is turned off
- return MemOperand;
- }
-
- if (Traits::Is64Bit && NeedSandboxing) {
- // Immediate randomization/pooling is currently disabled for x86-64
- // sandboxing for it could generate invalid memory operands.
- assert(false &&
- "Constant pooling/randomization is disabled for x8664 sandbox.");
- return MemOperand;
- }
-
- // If this memory operand is already a randomized one, we do not randomize it
- // again.
- if (MemOperand->getRandomized())
- return MemOperand;
-
- auto *C = llvm::dyn_cast_or_null<Constant>(MemOperand->getOffset());
-
- if (C == nullptr) {
- return MemOperand;
- }
-
- if (!C->shouldBeRandomizedOrPooled()) {
- return MemOperand;
- }
-
- // The offset of this mem operand should be blinded or pooled
- Ctx->statsUpdateRPImms();
- switch (getFlags().getRandomizeAndPoolImmediatesOption()) {
- default:
- llvm::report_fatal_error("Unsupported -randomize-pool-immediates option");
- case RPI_Randomize: {
- // blind the constant offset
- // FROM:
- // offset[base, index, shift]
- // TO:
- // insert: lea offset+cookie[base], RegTemp
- // => -cookie[RegTemp, index, shift]
- uint32_t Value =
- llvm::dyn_cast<ConstantInteger32>(MemOperand->getOffset())->getValue();
- uint32_t Cookie = Func->getConstantBlindingCookie();
- Constant *Mask1 =
- Ctx->getConstantInt(MemOperand->getOffset()->getType(), Cookie + Value);
- Constant *Mask2 =
- Ctx->getConstantInt(MemOperand->getOffset()->getType(), 0 - Cookie);
-
- X86OperandMem *TempMemOperand = X86OperandMem::create(
- Func, MemOperand->getType(), MemOperand->getBase(), Mask1);
- // If we have already assigned a physical register, we must come from
- // advancedPhiLowering()=>lowerAssign(). In this case we should reuse
- // the assigned register as this assignment is that start of its
- // use-def chain. So we add RegNum argument here.
- Variable *RegTemp = makeReg(MemOperand->getOffset()->getType(), RegNum);
- _lea(RegTemp, TempMemOperand);
-
- X86OperandMem *NewMemOperand = X86OperandMem::create(
- Func, MemOperand->getType(), RegTemp, Mask2, MemOperand->getIndex(),
- MemOperand->getShift(), MemOperand->getSegmentRegister(),
- MemOperand->getIsRebased());
-
- // Label this memory operand as randomized, so we won't randomize it
- // again in case we call legalize() multiple times on this memory
- // operand.
- NewMemOperand->setRandomized(true);
- return NewMemOperand;
- }
- case RPI_Pool: {
- // pool the constant offset
- // FROM:
- // offset[base, index, shift]
- // TO:
- // insert: mov $label, RegTemp
- // insert: lea [base, RegTemp], RegTemp
- // =>[RegTemp, index, shift]
-
- // Memory operand should never exist as source operands in phi lowering
- // assignments, so there is no need to reuse any registers here. For
- // phi lowering, we should not ask for new physical registers in
- // general. However, if we do meet Memory Operand during phi lowering,
- // we should not blind or pool the immediates for now.
- if (RegNum.hasValue())
- return MemOperand;
- Variable *RegTemp = makeReg(IceType_i32);
- assert(MemOperand->getOffset()->getShouldBePooled());
- constexpr RelocOffsetT SymOffset = 0;
- Constant *Symbol =
- Ctx->getConstantSym(SymOffset, MemOperand->getOffset()->getLabelName());
- constexpr Variable *NoBase = nullptr;
- X86OperandMem *SymbolOperand = X86OperandMem::create(
- Func, MemOperand->getOffset()->getType(), NoBase, Symbol);
- _mov(RegTemp, SymbolOperand);
- // If we have a base variable here, we should add the lea instruction
- // to add the value of the base variable to RegTemp. If there is no
- // base variable, we won't need this lea instruction.
- if (MemOperand->getBase()) {
- X86OperandMem *CalculateOperand = X86OperandMem::create(
- Func, MemOperand->getType(), MemOperand->getBase(), nullptr, RegTemp,
- 0, MemOperand->getSegmentRegister());
- _lea(RegTemp, CalculateOperand);
- }
- X86OperandMem *NewMemOperand = X86OperandMem::create(
- Func, MemOperand->getType(), RegTemp, nullptr, MemOperand->getIndex(),
- MemOperand->getShift(), MemOperand->getSegmentRegister());
- return NewMemOperand;
- }
- }
-}
-
template <typename TraitsType>
void TargetX86Base<TraitsType>::emitJumpTable(
const Cfg *, const InstJumpTable *JumpTable) const {
@@ -8524,18 +8270,6 @@
<< "\n";
Str << "\t.align\t" << Align << "\n";
- // If reorder-pooled-constants option is set to true, we need to shuffle the
- // constant pool before emitting it.
- if (getFlags().getReorderPooledConstants() && !Pool.empty()) {
- // Use the constant's kind value as the salt for creating random number
- // generator.
- Operand::OperandKind K = (*Pool.begin())->getKind();
- RandomNumberGenerator RNG(getFlags().getRandomSeed(),
- RPE_PooledConstantReordering, K);
- RandomShuffle(Pool.begin(), Pool.end(),
- [&RNG](uint64_t N) { return (uint32_t)RNG.next(N); });
- }
-
for (Constant *C : Pool) {
if (!C->getShouldBePooled())
continue;
diff --git a/third_party/subzero/src/IceTimerTree.def b/third_party/subzero/src/IceTimerTree.def
index 65da665..8a323ce 100644
--- a/third_party/subzero/src/IceTimerTree.def
+++ b/third_party/subzero/src/IceTimerTree.def
@@ -27,7 +27,6 @@
X(doAddressOpt) \
X(doArgLowering) \
X(doBranchOpt) \
- X(doNopInsertion) \
X(emitAsm) \
X(emitGlobalInitializers) \
X(findRMW) \
