| /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
| |* *| |
| |* Assembly Writer Source Fragment *| |
| |* *| |
| |* Automatically generated file, do not edit! *| |
| |* *| |
| \*===----------------------------------------------------------------------===*/ |
| |
| /// printInstruction - This method is automatically generated by tablegen |
| /// from the instruction set description. |
| void RISCVInstPrinter::printInstruction(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &O) { |
| static const char AsmStrs[] = { |
| /* 0 */ 'c', '.', 's', 'r', 'a', 'i', '6', '4', 9, 0, |
| /* 10 */ 'c', '.', 's', 'l', 'l', 'i', '6', '4', 9, 0, |
| /* 20 */ 'c', '.', 's', 'r', 'l', 'i', '6', '4', 9, 0, |
| /* 30 */ 'l', 'l', 'a', 9, 0, |
| /* 35 */ 's', 'f', 'e', 'n', 'c', 'e', '.', 'v', 'm', 'a', 9, 0, |
| /* 47 */ 's', 'r', 'a', 9, 0, |
| /* 52 */ 'l', 'b', 9, 0, |
| /* 56 */ 's', 'b', 9, 0, |
| /* 60 */ 'c', '.', 's', 'u', 'b', 9, 0, |
| /* 67 */ 'a', 'u', 'i', 'p', 'c', 9, 0, |
| /* 74 */ 'c', 's', 'r', 'r', 'c', 9, 0, |
| /* 81 */ 'f', 's', 'u', 'b', '.', 'd', 9, 0, |
| /* 89 */ 'f', 'm', 's', 'u', 'b', '.', 'd', 9, 0, |
| /* 98 */ 'f', 'n', 'm', 's', 'u', 'b', '.', 'd', 9, 0, |
| /* 108 */ 's', 'c', '.', 'd', 9, 0, |
| /* 114 */ 'f', 'a', 'd', 'd', '.', 'd', 9, 0, |
| /* 122 */ 'f', 'm', 'a', 'd', 'd', '.', 'd', 9, 0, |
| /* 131 */ 'f', 'n', 'm', 'a', 'd', 'd', '.', 'd', 9, 0, |
| /* 141 */ 'a', 'm', 'o', 'a', 'd', 'd', '.', 'd', 9, 0, |
| /* 151 */ 'a', 'm', 'o', 'a', 'n', 'd', '.', 'd', 9, 0, |
| /* 161 */ 'f', 'l', 'e', '.', 'd', 9, 0, |
| /* 168 */ 'f', 's', 'g', 'n', 'j', '.', 'd', 9, 0, |
| /* 177 */ 'f', 'c', 'v', 't', '.', 'l', '.', 'd', 9, 0, |
| /* 187 */ 'f', 'm', 'u', 'l', '.', 'd', 9, 0, |
| /* 195 */ 'f', 'm', 'i', 'n', '.', 'd', 9, 0, |
| /* 203 */ 'a', 'm', 'o', 'm', 'i', 'n', '.', 'd', 9, 0, |
| /* 213 */ 'f', 's', 'g', 'n', 'j', 'n', '.', 'd', 9, 0, |
| /* 223 */ 'a', 'm', 'o', 's', 'w', 'a', 'p', '.', 'd', 9, 0, |
| /* 234 */ 'f', 'e', 'q', '.', 'd', 9, 0, |
| /* 241 */ 'l', 'r', '.', 'd', 9, 0, |
| /* 247 */ 'a', 'm', 'o', 'o', 'r', '.', 'd', 9, 0, |
| /* 256 */ 'a', 'm', 'o', 'x', 'o', 'r', '.', 'd', 9, 0, |
| /* 266 */ 'f', 'c', 'v', 't', '.', 's', '.', 'd', 9, 0, |
| /* 276 */ 'f', 'c', 'l', 'a', 's', 's', '.', 'd', 9, 0, |
| /* 286 */ 'f', 'l', 't', '.', 'd', 9, 0, |
| /* 293 */ 'f', 's', 'q', 'r', 't', '.', 'd', 9, 0, |
| /* 302 */ 'f', 'c', 'v', 't', '.', 'l', 'u', '.', 'd', 9, 0, |
| /* 313 */ 'a', 'm', 'o', 'm', 'i', 'n', 'u', '.', 'd', 9, 0, |
| /* 324 */ 'f', 'c', 'v', 't', '.', 'w', 'u', '.', 'd', 9, 0, |
| /* 335 */ 'a', 'm', 'o', 'm', 'a', 'x', 'u', '.', 'd', 9, 0, |
| /* 346 */ 'f', 'd', 'i', 'v', '.', 'd', 9, 0, |
| /* 354 */ 'f', 'c', 'v', 't', '.', 'w', '.', 'd', 9, 0, |
| /* 364 */ 'f', 'm', 'v', '.', 'x', '.', 'd', 9, 0, |
| /* 373 */ 'f', 'm', 'a', 'x', '.', 'd', 9, 0, |
| /* 381 */ 'a', 'm', 'o', 'm', 'a', 'x', '.', 'd', 9, 0, |
| /* 391 */ 'f', 's', 'g', 'n', 'j', 'x', '.', 'd', 9, 0, |
| /* 401 */ 'c', '.', 'a', 'd', 'd', 9, 0, |
| /* 408 */ 'l', 'a', '.', 't', 'l', 's', '.', 'g', 'd', 9, 0, |
| /* 419 */ 'c', '.', 'l', 'd', 9, 0, |
| /* 425 */ 'c', '.', 'f', 'l', 'd', 9, 0, |
| /* 432 */ 'c', '.', 'a', 'n', 'd', 9, 0, |
| /* 439 */ 'c', '.', 's', 'd', 9, 0, |
| /* 445 */ 'c', '.', 'f', 's', 'd', 9, 0, |
| /* 452 */ 'f', 'e', 'n', 'c', 'e', 9, 0, |
| /* 459 */ 'b', 'g', 'e', 9, 0, |
| /* 464 */ 'l', 'a', '.', 't', 'l', 's', '.', 'i', 'e', 9, 0, |
| /* 475 */ 'b', 'n', 'e', 9, 0, |
| /* 480 */ 'm', 'u', 'l', 'h', 9, 0, |
| /* 486 */ 's', 'h', 9, 0, |
| /* 490 */ 'f', 'e', 'n', 'c', 'e', '.', 'i', 9, 0, |
| /* 499 */ 'c', '.', 's', 'r', 'a', 'i', 9, 0, |
| /* 507 */ 'c', 's', 'r', 'r', 'c', 'i', 9, 0, |
| /* 515 */ 'c', '.', 'a', 'd', 'd', 'i', 9, 0, |
| /* 523 */ 'c', '.', 'a', 'n', 'd', 'i', 9, 0, |
| /* 531 */ 'w', 'f', 'i', 9, 0, |
| /* 536 */ 'c', '.', 'l', 'i', 9, 0, |
| /* 542 */ 'c', '.', 's', 'l', 'l', 'i', 9, 0, |
| /* 550 */ 'c', '.', 's', 'r', 'l', 'i', 9, 0, |
| /* 558 */ 'x', 'o', 'r', 'i', 9, 0, |
| /* 564 */ 'c', 's', 'r', 'r', 's', 'i', 9, 0, |
| /* 572 */ 's', 'l', 't', 'i', 9, 0, |
| /* 578 */ 'c', '.', 'l', 'u', 'i', 9, 0, |
| /* 585 */ 'c', 's', 'r', 'r', 'w', 'i', 9, 0, |
| /* 593 */ 'c', '.', 'j', 9, 0, |
| /* 598 */ 'c', '.', 'e', 'b', 'r', 'e', 'a', 'k', 9, 0, |
| /* 608 */ 'f', 'c', 'v', 't', '.', 'd', '.', 'l', 9, 0, |
| /* 618 */ 'f', 'c', 'v', 't', '.', 's', '.', 'l', 9, 0, |
| /* 628 */ 'c', '.', 'j', 'a', 'l', 9, 0, |
| /* 635 */ 't', 'a', 'i', 'l', 9, 0, |
| /* 641 */ 'e', 'c', 'a', 'l', 'l', 9, 0, |
| /* 648 */ 's', 'l', 'l', 9, 0, |
| /* 653 */ 's', 'c', '.', 'd', '.', 'r', 'l', 9, 0, |
| /* 662 */ 'a', 'm', 'o', 'a', 'd', 'd', '.', 'd', '.', 'r', 'l', 9, 0, |
| /* 675 */ 'a', 'm', 'o', 'a', 'n', 'd', '.', 'd', '.', 'r', 'l', 9, 0, |
| /* 688 */ 'a', 'm', 'o', 'm', 'i', 'n', '.', 'd', '.', 'r', 'l', 9, 0, |
| /* 701 */ 'a', 'm', 'o', 's', 'w', 'a', 'p', '.', 'd', '.', 'r', 'l', 9, 0, |
| /* 715 */ 'l', 'r', '.', 'd', '.', 'r', 'l', 9, 0, |
| /* 724 */ 'a', 'm', 'o', 'o', 'r', '.', 'd', '.', 'r', 'l', 9, 0, |
| /* 736 */ 'a', 'm', 'o', 'x', 'o', 'r', '.', 'd', '.', 'r', 'l', 9, 0, |
| /* 749 */ 'a', 'm', 'o', 'm', 'i', 'n', 'u', '.', 'd', '.', 'r', 'l', 9, 0, |
| /* 763 */ 'a', 'm', 'o', 'm', 'a', 'x', 'u', '.', 'd', '.', 'r', 'l', 9, 0, |
| /* 777 */ 'a', 'm', 'o', 'm', 'a', 'x', '.', 'd', '.', 'r', 'l', 9, 0, |
| /* 790 */ 's', 'c', '.', 'w', '.', 'r', 'l', 9, 0, |
| /* 799 */ 'a', 'm', 'o', 'a', 'd', 'd', '.', 'w', '.', 'r', 'l', 9, 0, |
| /* 812 */ 'a', 'm', 'o', 'a', 'n', 'd', '.', 'w', '.', 'r', 'l', 9, 0, |
| /* 825 */ 'a', 'm', 'o', 'm', 'i', 'n', '.', 'w', '.', 'r', 'l', 9, 0, |
| /* 838 */ 'a', 'm', 'o', 's', 'w', 'a', 'p', '.', 'w', '.', 'r', 'l', 9, 0, |
| /* 852 */ 'l', 'r', '.', 'w', '.', 'r', 'l', 9, 0, |
| /* 861 */ 'a', 'm', 'o', 'o', 'r', '.', 'w', '.', 'r', 'l', 9, 0, |
| /* 873 */ 'a', 'm', 'o', 'x', 'o', 'r', '.', 'w', '.', 'r', 'l', 9, 0, |
| /* 886 */ 'a', 'm', 'o', 'm', 'i', 'n', 'u', '.', 'w', '.', 'r', 'l', 9, 0, |
| /* 900 */ 'a', 'm', 'o', 'm', 'a', 'x', 'u', '.', 'w', '.', 'r', 'l', 9, 0, |
| /* 914 */ 'a', 'm', 'o', 'm', 'a', 'x', '.', 'w', '.', 'r', 'l', 9, 0, |
| /* 927 */ 's', 'c', '.', 'd', '.', 'a', 'q', 'r', 'l', 9, 0, |
| /* 938 */ 'a', 'm', 'o', 'a', 'd', 'd', '.', 'd', '.', 'a', 'q', 'r', 'l', 9, 0, |
| /* 953 */ 'a', 'm', 'o', 'a', 'n', 'd', '.', 'd', '.', 'a', 'q', 'r', 'l', 9, 0, |
| /* 968 */ 'a', 'm', 'o', 'm', 'i', 'n', '.', 'd', '.', 'a', 'q', 'r', 'l', 9, 0, |
| /* 983 */ 'a', 'm', 'o', 's', 'w', 'a', 'p', '.', 'd', '.', 'a', 'q', 'r', 'l', 9, 0, |
| /* 999 */ 'l', 'r', '.', 'd', '.', 'a', 'q', 'r', 'l', 9, 0, |
| /* 1010 */ 'a', 'm', 'o', 'o', 'r', '.', 'd', '.', 'a', 'q', 'r', 'l', 9, 0, |
| /* 1024 */ 'a', 'm', 'o', 'x', 'o', 'r', '.', 'd', '.', 'a', 'q', 'r', 'l', 9, 0, |
| /* 1039 */ 'a', 'm', 'o', 'm', 'i', 'n', 'u', '.', 'd', '.', 'a', 'q', 'r', 'l', 9, 0, |
| /* 1055 */ 'a', 'm', 'o', 'm', 'a', 'x', 'u', '.', 'd', '.', 'a', 'q', 'r', 'l', 9, 0, |
| /* 1071 */ 'a', 'm', 'o', 'm', 'a', 'x', '.', 'd', '.', 'a', 'q', 'r', 'l', 9, 0, |
| /* 1086 */ 's', 'c', '.', 'w', '.', 'a', 'q', 'r', 'l', 9, 0, |
| /* 1097 */ 'a', 'm', 'o', 'a', 'd', 'd', '.', 'w', '.', 'a', 'q', 'r', 'l', 9, 0, |
| /* 1112 */ 'a', 'm', 'o', 'a', 'n', 'd', '.', 'w', '.', 'a', 'q', 'r', 'l', 9, 0, |
| /* 1127 */ 'a', 'm', 'o', 'm', 'i', 'n', '.', 'w', '.', 'a', 'q', 'r', 'l', 9, 0, |
| /* 1142 */ 'a', 'm', 'o', 's', 'w', 'a', 'p', '.', 'w', '.', 'a', 'q', 'r', 'l', 9, 0, |
| /* 1158 */ 'l', 'r', '.', 'w', '.', 'a', 'q', 'r', 'l', 9, 0, |
| /* 1169 */ 'a', 'm', 'o', 'o', 'r', '.', 'w', '.', 'a', 'q', 'r', 'l', 9, 0, |
| /* 1183 */ 'a', 'm', 'o', 'x', 'o', 'r', '.', 'w', '.', 'a', 'q', 'r', 'l', 9, 0, |
| /* 1198 */ 'a', 'm', 'o', 'm', 'i', 'n', 'u', '.', 'w', '.', 'a', 'q', 'r', 'l', 9, 0, |
| /* 1214 */ 'a', 'm', 'o', 'm', 'a', 'x', 'u', '.', 'w', '.', 'a', 'q', 'r', 'l', 9, 0, |
| /* 1230 */ 'a', 'm', 'o', 'm', 'a', 'x', '.', 'w', '.', 'a', 'q', 'r', 'l', 9, 0, |
| /* 1245 */ 's', 'r', 'l', 9, 0, |
| /* 1250 */ 'm', 'u', 'l', 9, 0, |
| /* 1255 */ 'r', 'e', 'm', 9, 0, |
| /* 1260 */ 'c', '.', 'a', 'd', 'd', 'i', '4', 's', 'p', 'n', 9, 0, |
| /* 1272 */ 'f', 'e', 'n', 'c', 'e', '.', 't', 's', 'o', 9, 0, |
| /* 1283 */ 'c', '.', 'u', 'n', 'i', 'm', 'p', 9, 0, |
| /* 1292 */ 'c', '.', 'n', 'o', 'p', 9, 0, |
| /* 1299 */ 'c', '.', 'a', 'd', 'd', 'i', '1', '6', 's', 'p', 9, 0, |
| /* 1311 */ 'c', '.', 'l', 'd', 's', 'p', 9, 0, |
| /* 1319 */ 'c', '.', 'f', 'l', 'd', 's', 'p', 9, 0, |
| /* 1328 */ 'c', '.', 's', 'd', 's', 'p', 9, 0, |
| /* 1336 */ 'c', '.', 'f', 's', 'd', 's', 'p', 9, 0, |
| /* 1345 */ 'c', '.', 'l', 'w', 's', 'p', 9, 0, |
| /* 1353 */ 'c', '.', 'f', 'l', 'w', 's', 'p', 9, 0, |
| /* 1362 */ 'c', '.', 's', 'w', 's', 'p', 9, 0, |
| /* 1370 */ 'c', '.', 'f', 's', 'w', 's', 'p', 9, 0, |
| /* 1379 */ 's', 'c', '.', 'd', '.', 'a', 'q', 9, 0, |
| /* 1388 */ 'a', 'm', 'o', 'a', 'd', 'd', '.', 'd', '.', 'a', 'q', 9, 0, |
| /* 1401 */ 'a', 'm', 'o', 'a', 'n', 'd', '.', 'd', '.', 'a', 'q', 9, 0, |
| /* 1414 */ 'a', 'm', 'o', 'm', 'i', 'n', '.', 'd', '.', 'a', 'q', 9, 0, |
| /* 1427 */ 'a', 'm', 'o', 's', 'w', 'a', 'p', '.', 'd', '.', 'a', 'q', 9, 0, |
| /* 1441 */ 'l', 'r', '.', 'd', '.', 'a', 'q', 9, 0, |
| /* 1450 */ 'a', 'm', 'o', 'o', 'r', '.', 'd', '.', 'a', 'q', 9, 0, |
| /* 1462 */ 'a', 'm', 'o', 'x', 'o', 'r', '.', 'd', '.', 'a', 'q', 9, 0, |
| /* 1475 */ 'a', 'm', 'o', 'm', 'i', 'n', 'u', '.', 'd', '.', 'a', 'q', 9, 0, |
| /* 1489 */ 'a', 'm', 'o', 'm', 'a', 'x', 'u', '.', 'd', '.', 'a', 'q', 9, 0, |
| /* 1503 */ 'a', 'm', 'o', 'm', 'a', 'x', '.', 'd', '.', 'a', 'q', 9, 0, |
| /* 1516 */ 's', 'c', '.', 'w', '.', 'a', 'q', 9, 0, |
| /* 1525 */ 'a', 'm', 'o', 'a', 'd', 'd', '.', 'w', '.', 'a', 'q', 9, 0, |
| /* 1538 */ 'a', 'm', 'o', 'a', 'n', 'd', '.', 'w', '.', 'a', 'q', 9, 0, |
| /* 1551 */ 'a', 'm', 'o', 'm', 'i', 'n', '.', 'w', '.', 'a', 'q', 9, 0, |
| /* 1564 */ 'a', 'm', 'o', 's', 'w', 'a', 'p', '.', 'w', '.', 'a', 'q', 9, 0, |
| /* 1578 */ 'l', 'r', '.', 'w', '.', 'a', 'q', 9, 0, |
| /* 1587 */ 'a', 'm', 'o', 'o', 'r', '.', 'w', '.', 'a', 'q', 9, 0, |
| /* 1599 */ 'a', 'm', 'o', 'x', 'o', 'r', '.', 'w', '.', 'a', 'q', 9, 0, |
| /* 1612 */ 'a', 'm', 'o', 'm', 'i', 'n', 'u', '.', 'w', '.', 'a', 'q', 9, 0, |
| /* 1626 */ 'a', 'm', 'o', 'm', 'a', 'x', 'u', '.', 'w', '.', 'a', 'q', 9, 0, |
| /* 1640 */ 'a', 'm', 'o', 'm', 'a', 'x', '.', 'w', '.', 'a', 'q', 9, 0, |
| /* 1653 */ 'b', 'e', 'q', 9, 0, |
| /* 1658 */ 'c', '.', 'j', 'r', 9, 0, |
| /* 1664 */ 'c', '.', 'j', 'a', 'l', 'r', 9, 0, |
| /* 1672 */ 'c', '.', 'o', 'r', 9, 0, |
| /* 1678 */ 'c', '.', 'x', 'o', 'r', 9, 0, |
| /* 1685 */ 'f', 's', 'u', 'b', '.', 's', 9, 0, |
| /* 1693 */ 'f', 'm', 's', 'u', 'b', '.', 's', 9, 0, |
| /* 1702 */ 'f', 'n', 'm', 's', 'u', 'b', '.', 's', 9, 0, |
| /* 1712 */ 'f', 'c', 'v', 't', '.', 'd', '.', 's', 9, 0, |
| /* 1722 */ 'f', 'a', 'd', 'd', '.', 's', 9, 0, |
| /* 1730 */ 'f', 'm', 'a', 'd', 'd', '.', 's', 9, 0, |
| /* 1739 */ 'f', 'n', 'm', 'a', 'd', 'd', '.', 's', 9, 0, |
| /* 1749 */ 'f', 'l', 'e', '.', 's', 9, 0, |
| /* 1756 */ 'f', 's', 'g', 'n', 'j', '.', 's', 9, 0, |
| /* 1765 */ 'f', 'c', 'v', 't', '.', 'l', '.', 's', 9, 0, |
| /* 1775 */ 'f', 'm', 'u', 'l', '.', 's', 9, 0, |
| /* 1783 */ 'f', 'm', 'i', 'n', '.', 's', 9, 0, |
| /* 1791 */ 'f', 's', 'g', 'n', 'j', 'n', '.', 's', 9, 0, |
| /* 1801 */ 'f', 'e', 'q', '.', 's', 9, 0, |
| /* 1808 */ 'f', 'c', 'l', 'a', 's', 's', '.', 's', 9, 0, |
| /* 1818 */ 'f', 'l', 't', '.', 's', 9, 0, |
| /* 1825 */ 'f', 's', 'q', 'r', 't', '.', 's', 9, 0, |
| /* 1834 */ 'f', 'c', 'v', 't', '.', 'l', 'u', '.', 's', 9, 0, |
| /* 1845 */ 'f', 'c', 'v', 't', '.', 'w', 'u', '.', 's', 9, 0, |
| /* 1856 */ 'f', 'd', 'i', 'v', '.', 's', 9, 0, |
| /* 1864 */ 'f', 'c', 'v', 't', '.', 'w', '.', 's', 9, 0, |
| /* 1874 */ 'f', 'm', 'a', 'x', '.', 's', 9, 0, |
| /* 1882 */ 'f', 's', 'g', 'n', 'j', 'x', '.', 's', 9, 0, |
| /* 1892 */ 'c', 's', 'r', 'r', 's', 9, 0, |
| /* 1899 */ 'm', 'r', 'e', 't', 9, 0, |
| /* 1905 */ 's', 'r', 'e', 't', 9, 0, |
| /* 1911 */ 'u', 'r', 'e', 't', 9, 0, |
| /* 1917 */ 'b', 'l', 't', 9, 0, |
| /* 1922 */ 's', 'l', 't', 9, 0, |
| /* 1927 */ 'l', 'b', 'u', 9, 0, |
| /* 1932 */ 'b', 'g', 'e', 'u', 9, 0, |
| /* 1938 */ 'm', 'u', 'l', 'h', 'u', 9, 0, |
| /* 1945 */ 's', 'l', 't', 'i', 'u', 9, 0, |
| /* 1952 */ 'f', 'c', 'v', 't', '.', 'd', '.', 'l', 'u', 9, 0, |
| /* 1963 */ 'f', 'c', 'v', 't', '.', 's', '.', 'l', 'u', 9, 0, |
| /* 1974 */ 'r', 'e', 'm', 'u', 9, 0, |
| /* 1980 */ 'm', 'u', 'l', 'h', 's', 'u', 9, 0, |
| /* 1988 */ 'b', 'l', 't', 'u', 9, 0, |
| /* 1994 */ 's', 'l', 't', 'u', 9, 0, |
| /* 2000 */ 'd', 'i', 'v', 'u', 9, 0, |
| /* 2006 */ 'f', 'c', 'v', 't', '.', 'd', '.', 'w', 'u', 9, 0, |
| /* 2017 */ 'f', 'c', 'v', 't', '.', 's', '.', 'w', 'u', 9, 0, |
| /* 2028 */ 'l', 'w', 'u', 9, 0, |
| /* 2033 */ 'd', 'i', 'v', 9, 0, |
| /* 2038 */ 'c', '.', 'm', 'v', 9, 0, |
| /* 2044 */ 's', 'c', '.', 'w', 9, 0, |
| /* 2050 */ 'f', 'c', 'v', 't', '.', 'd', '.', 'w', 9, 0, |
| /* 2060 */ 'a', 'm', 'o', 'a', 'd', 'd', '.', 'w', 9, 0, |
| /* 2070 */ 'a', 'm', 'o', 'a', 'n', 'd', '.', 'w', 9, 0, |
| /* 2080 */ 'a', 'm', 'o', 'm', 'i', 'n', '.', 'w', 9, 0, |
| /* 2090 */ 'a', 'm', 'o', 's', 'w', 'a', 'p', '.', 'w', 9, 0, |
| /* 2101 */ 'l', 'r', '.', 'w', 9, 0, |
| /* 2107 */ 'a', 'm', 'o', 'o', 'r', '.', 'w', 9, 0, |
| /* 2116 */ 'a', 'm', 'o', 'x', 'o', 'r', '.', 'w', 9, 0, |
| /* 2126 */ 'f', 'c', 'v', 't', '.', 's', '.', 'w', 9, 0, |
| /* 2136 */ 'a', 'm', 'o', 'm', 'i', 'n', 'u', '.', 'w', 9, 0, |
| /* 2147 */ 'a', 'm', 'o', 'm', 'a', 'x', 'u', '.', 'w', 9, 0, |
| /* 2158 */ 'f', 'm', 'v', '.', 'x', '.', 'w', 9, 0, |
| /* 2167 */ 'a', 'm', 'o', 'm', 'a', 'x', '.', 'w', 9, 0, |
| /* 2177 */ 's', 'r', 'a', 'w', 9, 0, |
| /* 2183 */ 'c', '.', 's', 'u', 'b', 'w', 9, 0, |
| /* 2191 */ 'c', '.', 'a', 'd', 'd', 'w', 9, 0, |
| /* 2199 */ 's', 'r', 'a', 'i', 'w', 9, 0, |
| /* 2206 */ 'c', '.', 'a', 'd', 'd', 'i', 'w', 9, 0, |
| /* 2215 */ 's', 'l', 'l', 'i', 'w', 9, 0, |
| /* 2222 */ 's', 'r', 'l', 'i', 'w', 9, 0, |
| /* 2229 */ 'c', '.', 'l', 'w', 9, 0, |
| /* 2235 */ 'c', '.', 'f', 'l', 'w', 9, 0, |
| /* 2242 */ 's', 'l', 'l', 'w', 9, 0, |
| /* 2248 */ 's', 'r', 'l', 'w', 9, 0, |
| /* 2254 */ 'm', 'u', 'l', 'w', 9, 0, |
| /* 2260 */ 'r', 'e', 'm', 'w', 9, 0, |
| /* 2266 */ 'c', 's', 'r', 'r', 'w', 9, 0, |
| /* 2273 */ 'c', '.', 's', 'w', 9, 0, |
| /* 2279 */ 'c', '.', 'f', 's', 'w', 9, 0, |
| /* 2286 */ 'r', 'e', 'm', 'u', 'w', 9, 0, |
| /* 2293 */ 'd', 'i', 'v', 'u', 'w', 9, 0, |
| /* 2300 */ 'd', 'i', 'v', 'w', 9, 0, |
| /* 2306 */ 'f', 'm', 'v', '.', 'd', '.', 'x', 9, 0, |
| /* 2315 */ 'f', 'm', 'v', '.', 'w', '.', 'x', 9, 0, |
| /* 2324 */ 'c', '.', 'b', 'n', 'e', 'z', 9, 0, |
| /* 2332 */ 'c', '.', 'b', 'e', 'q', 'z', 9, 0, |
| /* 2340 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'F', 'u', 'n', 'c', 't', 'i', 'o', 'n', 32, 'P', 'a', 't', 'c', 'h', 'a', 'b', 'l', 'e', 32, 'R', 'E', 'T', '.', 0, |
| /* 2371 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'T', 'y', 'p', 'e', 'd', 32, 'E', 'v', 'e', 'n', 't', 32, 'L', 'o', 'g', '.', 0, |
| /* 2395 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'C', 'u', 's', 't', 'o', 'm', 32, 'E', 'v', 'e', 'n', 't', 32, 'L', 'o', 'g', '.', 0, |
| /* 2420 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'F', 'u', 'n', 'c', 't', 'i', 'o', 'n', 32, 'E', 'n', 't', 'e', 'r', '.', 0, |
| /* 2443 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'T', 'a', 'i', 'l', 32, 'C', 'a', 'l', 'l', 32, 'E', 'x', 'i', 't', '.', 0, |
| /* 2466 */ '#', 32, 'X', 'R', 'a', 'y', 32, 'F', 'u', 'n', 'c', 't', 'i', 'o', 'n', 32, 'E', 'x', 'i', 't', '.', 0, |
| /* 2488 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0, |
| /* 2501 */ 'B', 'U', 'N', 'D', 'L', 'E', 0, |
| /* 2508 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0, |
| /* 2518 */ 'D', 'B', 'G', '_', 'L', 'A', 'B', 'E', 'L', 0, |
| /* 2528 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0, |
| /* 2543 */ '#', 32, 'F', 'E', 'n', 't', 'r', 'y', 32, 'c', 'a', 'l', 'l', 0, |
| }; |
| |
| static const uint16_t OpInfo0[] = { |
| 0U, // PHI |
| 0U, // INLINEASM |
| 0U, // INLINEASM_BR |
| 0U, // CFI_INSTRUCTION |
| 0U, // EH_LABEL |
| 0U, // GC_LABEL |
| 0U, // ANNOTATION_LABEL |
| 0U, // KILL |
| 0U, // EXTRACT_SUBREG |
| 0U, // INSERT_SUBREG |
| 0U, // IMPLICIT_DEF |
| 0U, // SUBREG_TO_REG |
| 0U, // COPY_TO_REGCLASS |
| 2509U, // DBG_VALUE |
| 2519U, // DBG_LABEL |
| 0U, // REG_SEQUENCE |
| 0U, // COPY |
| 2502U, // BUNDLE |
| 2529U, // LIFETIME_START |
| 2489U, // LIFETIME_END |
| 0U, // STACKMAP |
| 2544U, // FENTRY_CALL |
| 0U, // PATCHPOINT |
| 0U, // LOAD_STACK_GUARD |
| 0U, // STATEPOINT |
| 0U, // LOCAL_ESCAPE |
| 0U, // FAULTING_OP |
| 0U, // PATCHABLE_OP |
| 2421U, // PATCHABLE_FUNCTION_ENTER |
| 2341U, // PATCHABLE_RET |
| 2467U, // PATCHABLE_FUNCTION_EXIT |
| 2444U, // PATCHABLE_TAIL_CALL |
| 2396U, // PATCHABLE_EVENT_CALL |
| 2372U, // PATCHABLE_TYPED_EVENT_CALL |
| 0U, // ICALL_BRANCH_FUNNEL |
| 0U, // G_ADD |
| 0U, // G_SUB |
| 0U, // G_MUL |
| 0U, // G_SDIV |
| 0U, // G_UDIV |
| 0U, // G_SREM |
| 0U, // G_UREM |
| 0U, // G_AND |
| 0U, // G_OR |
| 0U, // G_XOR |
| 0U, // G_IMPLICIT_DEF |
| 0U, // G_PHI |
| 0U, // G_FRAME_INDEX |
| 0U, // G_GLOBAL_VALUE |
| 0U, // G_EXTRACT |
| 0U, // G_UNMERGE_VALUES |
| 0U, // G_INSERT |
| 0U, // G_MERGE_VALUES |
| 0U, // G_BUILD_VECTOR |
| 0U, // G_BUILD_VECTOR_TRUNC |
| 0U, // G_CONCAT_VECTORS |
| 0U, // G_PTRTOINT |
| 0U, // G_INTTOPTR |
| 0U, // G_BITCAST |
| 0U, // G_INTRINSIC_TRUNC |
| 0U, // G_INTRINSIC_ROUND |
| 0U, // G_READCYCLECOUNTER |
| 0U, // G_LOAD |
| 0U, // G_SEXTLOAD |
| 0U, // G_ZEXTLOAD |
| 0U, // G_INDEXED_LOAD |
| 0U, // G_INDEXED_SEXTLOAD |
| 0U, // G_INDEXED_ZEXTLOAD |
| 0U, // G_STORE |
| 0U, // G_INDEXED_STORE |
| 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS |
| 0U, // G_ATOMIC_CMPXCHG |
| 0U, // G_ATOMICRMW_XCHG |
| 0U, // G_ATOMICRMW_ADD |
| 0U, // G_ATOMICRMW_SUB |
| 0U, // G_ATOMICRMW_AND |
| 0U, // G_ATOMICRMW_NAND |
| 0U, // G_ATOMICRMW_OR |
| 0U, // G_ATOMICRMW_XOR |
| 0U, // G_ATOMICRMW_MAX |
| 0U, // G_ATOMICRMW_MIN |
| 0U, // G_ATOMICRMW_UMAX |
| 0U, // G_ATOMICRMW_UMIN |
| 0U, // G_ATOMICRMW_FADD |
| 0U, // G_ATOMICRMW_FSUB |
| 0U, // G_FENCE |
| 0U, // G_BRCOND |
| 0U, // G_BRINDIRECT |
| 0U, // G_INTRINSIC |
| 0U, // G_INTRINSIC_W_SIDE_EFFECTS |
| 0U, // G_ANYEXT |
| 0U, // G_TRUNC |
| 0U, // G_CONSTANT |
| 0U, // G_FCONSTANT |
| 0U, // G_VASTART |
| 0U, // G_VAARG |
| 0U, // G_SEXT |
| 0U, // G_SEXT_INREG |
| 0U, // G_ZEXT |
| 0U, // G_SHL |
| 0U, // G_LSHR |
| 0U, // G_ASHR |
| 0U, // G_ICMP |
| 0U, // G_FCMP |
| 0U, // G_SELECT |
| 0U, // G_UADDO |
| 0U, // G_UADDE |
| 0U, // G_USUBO |
| 0U, // G_USUBE |
| 0U, // G_SADDO |
| 0U, // G_SADDE |
| 0U, // G_SSUBO |
| 0U, // G_SSUBE |
| 0U, // G_UMULO |
| 0U, // G_SMULO |
| 0U, // G_UMULH |
| 0U, // G_SMULH |
| 0U, // G_FADD |
| 0U, // G_FSUB |
| 0U, // G_FMUL |
| 0U, // G_FMA |
| 0U, // G_FMAD |
| 0U, // G_FDIV |
| 0U, // G_FREM |
| 0U, // G_FPOW |
| 0U, // G_FEXP |
| 0U, // G_FEXP2 |
| 0U, // G_FLOG |
| 0U, // G_FLOG2 |
| 0U, // G_FLOG10 |
| 0U, // G_FNEG |
| 0U, // G_FPEXT |
| 0U, // G_FPTRUNC |
| 0U, // G_FPTOSI |
| 0U, // G_FPTOUI |
| 0U, // G_SITOFP |
| 0U, // G_UITOFP |
| 0U, // G_FABS |
| 0U, // G_FCOPYSIGN |
| 0U, // G_FCANONICALIZE |
| 0U, // G_FMINNUM |
| 0U, // G_FMAXNUM |
| 0U, // G_FMINNUM_IEEE |
| 0U, // G_FMAXNUM_IEEE |
| 0U, // G_FMINIMUM |
| 0U, // G_FMAXIMUM |
| 0U, // G_PTR_ADD |
| 0U, // G_PTR_MASK |
| 0U, // G_SMIN |
| 0U, // G_SMAX |
| 0U, // G_UMIN |
| 0U, // G_UMAX |
| 0U, // G_BR |
| 0U, // G_BRJT |
| 0U, // G_INSERT_VECTOR_ELT |
| 0U, // G_EXTRACT_VECTOR_ELT |
| 0U, // G_SHUFFLE_VECTOR |
| 0U, // G_CTTZ |
| 0U, // G_CTTZ_ZERO_UNDEF |
| 0U, // G_CTLZ |
| 0U, // G_CTLZ_ZERO_UNDEF |
| 0U, // G_CTPOP |
| 0U, // G_BSWAP |
| 0U, // G_BITREVERSE |
| 0U, // G_FCEIL |
| 0U, // G_FCOS |
| 0U, // G_FSIN |
| 0U, // G_FSQRT |
| 0U, // G_FFLOOR |
| 0U, // G_FRINT |
| 0U, // G_FNEARBYINT |
| 0U, // G_ADDRSPACE_CAST |
| 0U, // G_BLOCK_ADDR |
| 0U, // G_JUMP_TABLE |
| 0U, // G_DYN_STACKALLOC |
| 0U, // G_READ_REGISTER |
| 0U, // G_WRITE_REGISTER |
| 9U, // ADJCALLSTACKDOWN |
| 9U, // ADJCALLSTACKUP |
| 9U, // BuildPairF64Pseudo |
| 4500U, // PseudoAddTPRel |
| 9U, // PseudoAtomicLoadNand32 |
| 9U, // PseudoAtomicLoadNand64 |
| 9U, // PseudoBR |
| 9U, // PseudoBRIND |
| 21123U, // PseudoCALL |
| 9U, // PseudoCALLIndirect |
| 4739U, // PseudoCALLReg |
| 9U, // PseudoCmpXchg32 |
| 9U, // PseudoCmpXchg64 |
| 37292U, // PseudoFLD |
| 39102U, // PseudoFLW |
| 37312U, // PseudoFSD |
| 39146U, // PseudoFSW |
| 4128U, // PseudoLA |
| 4505U, // PseudoLA_TLS_GD |
| 4561U, // PseudoLA_TLS_IE |
| 4149U, // PseudoLB |
| 6024U, // PseudoLBU |
| 4518U, // PseudoLD |
| 4579U, // PseudoLH |
| 6037U, // PseudoLHU |
| 4635U, // PseudoLI |
| 4127U, // PseudoLLA |
| 6328U, // PseudoLW |
| 6125U, // PseudoLWU |
| 9U, // PseudoMaskedAtomicLoadAdd32 |
| 9U, // PseudoMaskedAtomicLoadMax32 |
| 9U, // PseudoMaskedAtomicLoadMin32 |
| 9U, // PseudoMaskedAtomicLoadNand32 |
| 9U, // PseudoMaskedAtomicLoadSub32 |
| 9U, // PseudoMaskedAtomicLoadUMax32 |
| 9U, // PseudoMaskedAtomicLoadUMin32 |
| 9U, // PseudoMaskedAtomicSwap32 |
| 9U, // PseudoMaskedCmpXchg32 |
| 9U, // PseudoRET |
| 36921U, // PseudoSB |
| 37306U, // PseudoSD |
| 37351U, // PseudoSH |
| 39140U, // PseudoSW |
| 21116U, // PseudoTAIL |
| 9U, // PseudoTAILIndirect |
| 9U, // ReadCycleWide |
| 9U, // Select_FPR32_Using_CC_GPR |
| 9U, // Select_FPR64_Using_CC_GPR |
| 9U, // Select_GPR_Using_CC_GPR |
| 9U, // SplitF64Pseudo |
| 4500U, // ADD |
| 4614U, // ADDI |
| 6305U, // ADDIW |
| 6290U, // ADDW |
| 37006U, // AMOADD_D |
| 38253U, // AMOADD_D_AQ |
| 37803U, // AMOADD_D_AQ_RL |
| 37527U, // AMOADD_D_RL |
| 38925U, // AMOADD_W |
| 38390U, // AMOADD_W_AQ |
| 37962U, // AMOADD_W_AQ_RL |
| 37664U, // AMOADD_W_RL |
| 37016U, // AMOAND_D |
| 38266U, // AMOAND_D_AQ |
| 37818U, // AMOAND_D_AQ_RL |
| 37540U, // AMOAND_D_RL |
| 38935U, // AMOAND_W |
| 38403U, // AMOAND_W_AQ |
| 37977U, // AMOAND_W_AQ_RL |
| 37677U, // AMOAND_W_RL |
| 37200U, // AMOMAXU_D |
| 38354U, // AMOMAXU_D_AQ |
| 37920U, // AMOMAXU_D_AQ_RL |
| 37628U, // AMOMAXU_D_RL |
| 39012U, // AMOMAXU_W |
| 38491U, // AMOMAXU_W_AQ |
| 38079U, // AMOMAXU_W_AQ_RL |
| 37765U, // AMOMAXU_W_RL |
| 37246U, // AMOMAX_D |
| 38368U, // AMOMAX_D_AQ |
| 37936U, // AMOMAX_D_AQ_RL |
| 37642U, // AMOMAX_D_RL |
| 39032U, // AMOMAX_W |
| 38505U, // AMOMAX_W_AQ |
| 38095U, // AMOMAX_W_AQ_RL |
| 37779U, // AMOMAX_W_RL |
| 37178U, // AMOMINU_D |
| 38340U, // AMOMINU_D_AQ |
| 37904U, // AMOMINU_D_AQ_RL |
| 37614U, // AMOMINU_D_RL |
| 39001U, // AMOMINU_W |
| 38477U, // AMOMINU_W_AQ |
| 38063U, // AMOMINU_W_AQ_RL |
| 37751U, // AMOMINU_W_RL |
| 37068U, // AMOMIN_D |
| 38279U, // AMOMIN_D_AQ |
| 37833U, // AMOMIN_D_AQ_RL |
| 37553U, // AMOMIN_D_RL |
| 38945U, // AMOMIN_W |
| 38416U, // AMOMIN_W_AQ |
| 37992U, // AMOMIN_W_AQ_RL |
| 37690U, // AMOMIN_W_RL |
| 37112U, // AMOOR_D |
| 38315U, // AMOOR_D_AQ |
| 37875U, // AMOOR_D_AQ_RL |
| 37589U, // AMOOR_D_RL |
| 38972U, // AMOOR_W |
| 38452U, // AMOOR_W_AQ |
| 38034U, // AMOOR_W_AQ_RL |
| 37726U, // AMOOR_W_RL |
| 37088U, // AMOSWAP_D |
| 38292U, // AMOSWAP_D_AQ |
| 37848U, // AMOSWAP_D_AQ_RL |
| 37566U, // AMOSWAP_D_RL |
| 38955U, // AMOSWAP_W |
| 38429U, // AMOSWAP_W_AQ |
| 38007U, // AMOSWAP_W_AQ_RL |
| 37703U, // AMOSWAP_W_RL |
| 37121U, // AMOXOR_D |
| 38327U, // AMOXOR_D_AQ |
| 37889U, // AMOXOR_D_AQ_RL |
| 37601U, // AMOXOR_D_RL |
| 38981U, // AMOXOR_W |
| 38464U, // AMOXOR_W_AQ |
| 38048U, // AMOXOR_W_AQ_RL |
| 37738U, // AMOXOR_W_RL |
| 4531U, // AND |
| 4622U, // ANDI |
| 4164U, // AUIPC |
| 5750U, // BEQ |
| 4556U, // BGE |
| 6029U, // BGEU |
| 6014U, // BLT |
| 6085U, // BLTU |
| 4572U, // BNE |
| 4171U, // CSRRC |
| 4604U, // CSRRCI |
| 5989U, // CSRRS |
| 4661U, // CSRRSI |
| 6363U, // CSRRW |
| 4682U, // CSRRWI |
| 41362U, // C_ADD |
| 41476U, // C_ADDI |
| 42260U, // C_ADDI16SP |
| 5357U, // C_ADDI4SPN |
| 43167U, // C_ADDIW |
| 41476U, // C_ADDI_HINT_IMM_ZERO |
| 41476U, // C_ADDI_HINT_X0 |
| 41476U, // C_ADDI_NOP |
| 43152U, // C_ADDW |
| 41362U, // C_ADD_HINT |
| 41393U, // C_AND |
| 41484U, // C_ANDI |
| 6429U, // C_BEQZ |
| 6421U, // C_BNEZ |
| 599U, // C_EBREAK |
| 37290U, // C_FLD |
| 38184U, // C_FLDSP |
| 39100U, // C_FLW |
| 38218U, // C_FLWSP |
| 37310U, // C_FSD |
| 38201U, // C_FSDSP |
| 39144U, // C_FSW |
| 38235U, // C_FSWSP |
| 21074U, // C_J |
| 21109U, // C_JAL |
| 22145U, // C_JALR |
| 22139U, // C_JR |
| 37284U, // C_LD |
| 38176U, // C_LDSP |
| 4633U, // C_LI |
| 4633U, // C_LI_HINT |
| 4675U, // C_LUI |
| 4675U, // C_LUI_HINT |
| 39094U, // C_LW |
| 38210U, // C_LWSP |
| 6135U, // C_MV |
| 6135U, // C_MV_HINT |
| 1293U, // C_NOP |
| 21773U, // C_NOP_HINT |
| 42633U, // C_OR |
| 37304U, // C_SD |
| 38193U, // C_SDSP |
| 41503U, // C_SLLI |
| 24587U, // C_SLLI64_HINT |
| 41503U, // C_SLLI_HINT |
| 41460U, // C_SRAI |
| 24577U, // C_SRAI64_HINT |
| 41511U, // C_SRLI |
| 24597U, // C_SRLI64_HINT |
| 41021U, // C_SUB |
| 43144U, // C_SUBW |
| 39138U, // C_SW |
| 38227U, // C_SWSP |
| 1284U, // C_UNIMP |
| 42639U, // C_XOR |
| 6130U, // DIV |
| 6097U, // DIVU |
| 6390U, // DIVUW |
| 6397U, // DIVW |
| 601U, // EBREAK |
| 642U, // ECALL |
| 4211U, // FADD_D |
| 5819U, // FADD_S |
| 4373U, // FCLASS_D |
| 5905U, // FCLASS_S |
| 4705U, // FCVT_D_L |
| 6049U, // FCVT_D_LU |
| 5809U, // FCVT_D_S |
| 6147U, // FCVT_D_W |
| 6103U, // FCVT_D_WU |
| 4399U, // FCVT_LU_D |
| 5931U, // FCVT_LU_S |
| 4274U, // FCVT_L_D |
| 5862U, // FCVT_L_S |
| 4363U, // FCVT_S_D |
| 4715U, // FCVT_S_L |
| 6060U, // FCVT_S_LU |
| 6223U, // FCVT_S_W |
| 6114U, // FCVT_S_WU |
| 4421U, // FCVT_WU_D |
| 5942U, // FCVT_WU_S |
| 4451U, // FCVT_W_D |
| 5961U, // FCVT_W_S |
| 4443U, // FDIV_D |
| 5953U, // FDIV_S |
| 12741U, // FENCE |
| 491U, // FENCE_I |
| 1273U, // FENCE_TSO |
| 4331U, // FEQ_D |
| 5898U, // FEQ_S |
| 37292U, // FLD |
| 4258U, // FLE_D |
| 5846U, // FLE_S |
| 4383U, // FLT_D |
| 5915U, // FLT_S |
| 39102U, // FLW |
| 4219U, // FMADD_D |
| 5827U, // FMADD_S |
| 4470U, // FMAX_D |
| 5971U, // FMAX_S |
| 4292U, // FMIN_D |
| 5880U, // FMIN_S |
| 4186U, // FMSUB_D |
| 5790U, // FMSUB_S |
| 4284U, // FMUL_D |
| 5872U, // FMUL_S |
| 6403U, // FMV_D_X |
| 6412U, // FMV_W_X |
| 4461U, // FMV_X_D |
| 6255U, // FMV_X_W |
| 4228U, // FNMADD_D |
| 5836U, // FNMADD_S |
| 4195U, // FNMSUB_D |
| 5799U, // FNMSUB_S |
| 37312U, // FSD |
| 4310U, // FSGNJN_D |
| 5888U, // FSGNJN_S |
| 4488U, // FSGNJX_D |
| 5979U, // FSGNJX_S |
| 4265U, // FSGNJ_D |
| 5853U, // FSGNJ_S |
| 4390U, // FSQRT_D |
| 5922U, // FSQRT_S |
| 4178U, // FSUB_D |
| 5782U, // FSUB_S |
| 39146U, // FSW |
| 4727U, // JAL |
| 38531U, // JALR |
| 36917U, // LB |
| 38792U, // LBU |
| 37286U, // LD |
| 37347U, // LH |
| 38805U, // LHU |
| 37106U, // LR_D |
| 38306U, // LR_D_AQ |
| 37864U, // LR_D_AQ_RL |
| 37580U, // LR_D_RL |
| 38966U, // LR_W |
| 38443U, // LR_W_AQ |
| 38023U, // LR_W_AQ_RL |
| 37717U, // LR_W_RL |
| 4677U, // LUI |
| 39096U, // LW |
| 38893U, // LWU |
| 1900U, // MRET |
| 5347U, // MUL |
| 4577U, // MULH |
| 6077U, // MULHSU |
| 6035U, // MULHU |
| 6351U, // MULW |
| 5771U, // OR |
| 4656U, // ORI |
| 5352U, // REM |
| 6071U, // REMU |
| 6383U, // REMUW |
| 6357U, // REMW |
| 36921U, // SB |
| 36973U, // SC_D |
| 38244U, // SC_D_AQ |
| 37792U, // SC_D_AQ_RL |
| 37518U, // SC_D_RL |
| 38909U, // SC_W |
| 38381U, // SC_W_AQ |
| 37951U, // SC_W_AQ_RL |
| 37655U, // SC_W_RL |
| 37306U, // SD |
| 4132U, // SFENCE_VMA |
| 37351U, // SH |
| 4745U, // SLL |
| 4641U, // SLLI |
| 6312U, // SLLIW |
| 6339U, // SLLW |
| 6019U, // SLT |
| 4669U, // SLTI |
| 6042U, // SLTIU |
| 6091U, // SLTU |
| 4144U, // SRA |
| 4598U, // SRAI |
| 6296U, // SRAIW |
| 6274U, // SRAW |
| 1906U, // SRET |
| 5342U, // SRL |
| 4649U, // SRLI |
| 6319U, // SRLIW |
| 6345U, // SRLW |
| 4159U, // SUB |
| 6282U, // SUBW |
| 39140U, // SW |
| 1286U, // UNIMP |
| 1912U, // URET |
| 532U, // WFI |
| 5777U, // XOR |
| 4655U, // XORI |
| }; |
| |
| static const uint8_t OpInfo1[] = { |
| 0U, // PHI |
| 0U, // INLINEASM |
| 0U, // INLINEASM_BR |
| 0U, // CFI_INSTRUCTION |
| 0U, // EH_LABEL |
| 0U, // GC_LABEL |
| 0U, // ANNOTATION_LABEL |
| 0U, // KILL |
| 0U, // EXTRACT_SUBREG |
| 0U, // INSERT_SUBREG |
| 0U, // IMPLICIT_DEF |
| 0U, // SUBREG_TO_REG |
| 0U, // COPY_TO_REGCLASS |
| 0U, // DBG_VALUE |
| 0U, // DBG_LABEL |
| 0U, // REG_SEQUENCE |
| 0U, // COPY |
| 0U, // BUNDLE |
| 0U, // LIFETIME_START |
| 0U, // LIFETIME_END |
| 0U, // STACKMAP |
| 0U, // FENTRY_CALL |
| 0U, // PATCHPOINT |
| 0U, // LOAD_STACK_GUARD |
| 0U, // STATEPOINT |
| 0U, // LOCAL_ESCAPE |
| 0U, // FAULTING_OP |
| 0U, // PATCHABLE_OP |
| 0U, // PATCHABLE_FUNCTION_ENTER |
| 0U, // PATCHABLE_RET |
| 0U, // PATCHABLE_FUNCTION_EXIT |
| 0U, // PATCHABLE_TAIL_CALL |
| 0U, // PATCHABLE_EVENT_CALL |
| 0U, // PATCHABLE_TYPED_EVENT_CALL |
| 0U, // ICALL_BRANCH_FUNNEL |
| 0U, // G_ADD |
| 0U, // G_SUB |
| 0U, // G_MUL |
| 0U, // G_SDIV |
| 0U, // G_UDIV |
| 0U, // G_SREM |
| 0U, // G_UREM |
| 0U, // G_AND |
| 0U, // G_OR |
| 0U, // G_XOR |
| 0U, // G_IMPLICIT_DEF |
| 0U, // G_PHI |
| 0U, // G_FRAME_INDEX |
| 0U, // G_GLOBAL_VALUE |
| 0U, // G_EXTRACT |
| 0U, // G_UNMERGE_VALUES |
| 0U, // G_INSERT |
| 0U, // G_MERGE_VALUES |
| 0U, // G_BUILD_VECTOR |
| 0U, // G_BUILD_VECTOR_TRUNC |
| 0U, // G_CONCAT_VECTORS |
| 0U, // G_PTRTOINT |
| 0U, // G_INTTOPTR |
| 0U, // G_BITCAST |
| 0U, // G_INTRINSIC_TRUNC |
| 0U, // G_INTRINSIC_ROUND |
| 0U, // G_READCYCLECOUNTER |
| 0U, // G_LOAD |
| 0U, // G_SEXTLOAD |
| 0U, // G_ZEXTLOAD |
| 0U, // G_INDEXED_LOAD |
| 0U, // G_INDEXED_SEXTLOAD |
| 0U, // G_INDEXED_ZEXTLOAD |
| 0U, // G_STORE |
| 0U, // G_INDEXED_STORE |
| 0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS |
| 0U, // G_ATOMIC_CMPXCHG |
| 0U, // G_ATOMICRMW_XCHG |
| 0U, // G_ATOMICRMW_ADD |
| 0U, // G_ATOMICRMW_SUB |
| 0U, // G_ATOMICRMW_AND |
| 0U, // G_ATOMICRMW_NAND |
| 0U, // G_ATOMICRMW_OR |
| 0U, // G_ATOMICRMW_XOR |
| 0U, // G_ATOMICRMW_MAX |
| 0U, // G_ATOMICRMW_MIN |
| 0U, // G_ATOMICRMW_UMAX |
| 0U, // G_ATOMICRMW_UMIN |
| 0U, // G_ATOMICRMW_FADD |
| 0U, // G_ATOMICRMW_FSUB |
| 0U, // G_FENCE |
| 0U, // G_BRCOND |
| 0U, // G_BRINDIRECT |
| 0U, // G_INTRINSIC |
| 0U, // G_INTRINSIC_W_SIDE_EFFECTS |
| 0U, // G_ANYEXT |
| 0U, // G_TRUNC |
| 0U, // G_CONSTANT |
| 0U, // G_FCONSTANT |
| 0U, // G_VASTART |
| 0U, // G_VAARG |
| 0U, // G_SEXT |
| 0U, // G_SEXT_INREG |
| 0U, // G_ZEXT |
| 0U, // G_SHL |
| 0U, // G_LSHR |
| 0U, // G_ASHR |
| 0U, // G_ICMP |
| 0U, // G_FCMP |
| 0U, // G_SELECT |
| 0U, // G_UADDO |
| 0U, // G_UADDE |
| 0U, // G_USUBO |
| 0U, // G_USUBE |
| 0U, // G_SADDO |
| 0U, // G_SADDE |
| 0U, // G_SSUBO |
| 0U, // G_SSUBE |
| 0U, // G_UMULO |
| 0U, // G_SMULO |
| 0U, // G_UMULH |
| 0U, // G_SMULH |
| 0U, // G_FADD |
| 0U, // G_FSUB |
| 0U, // G_FMUL |
| 0U, // G_FMA |
| 0U, // G_FMAD |
| 0U, // G_FDIV |
| 0U, // G_FREM |
| 0U, // G_FPOW |
| 0U, // G_FEXP |
| 0U, // G_FEXP2 |
| 0U, // G_FLOG |
| 0U, // G_FLOG2 |
| 0U, // G_FLOG10 |
| 0U, // G_FNEG |
| 0U, // G_FPEXT |
| 0U, // G_FPTRUNC |
| 0U, // G_FPTOSI |
| 0U, // G_FPTOUI |
| 0U, // G_SITOFP |
| 0U, // G_UITOFP |
| 0U, // G_FABS |
| 0U, // G_FCOPYSIGN |
| 0U, // G_FCANONICALIZE |
| 0U, // G_FMINNUM |
| 0U, // G_FMAXNUM |
| 0U, // G_FMINNUM_IEEE |
| 0U, // G_FMAXNUM_IEEE |
| 0U, // G_FMINIMUM |
| 0U, // G_FMAXIMUM |
| 0U, // G_PTR_ADD |
| 0U, // G_PTR_MASK |
| 0U, // G_SMIN |
| 0U, // G_SMAX |
| 0U, // G_UMIN |
| 0U, // G_UMAX |
| 0U, // G_BR |
| 0U, // G_BRJT |
| 0U, // G_INSERT_VECTOR_ELT |
| 0U, // G_EXTRACT_VECTOR_ELT |
| 0U, // G_SHUFFLE_VECTOR |
| 0U, // G_CTTZ |
| 0U, // G_CTTZ_ZERO_UNDEF |
| 0U, // G_CTLZ |
| 0U, // G_CTLZ_ZERO_UNDEF |
| 0U, // G_CTPOP |
| 0U, // G_BSWAP |
| 0U, // G_BITREVERSE |
| 0U, // G_FCEIL |
| 0U, // G_FCOS |
| 0U, // G_FSIN |
| 0U, // G_FSQRT |
| 0U, // G_FFLOOR |
| 0U, // G_FRINT |
| 0U, // G_FNEARBYINT |
| 0U, // G_ADDRSPACE_CAST |
| 0U, // G_BLOCK_ADDR |
| 0U, // G_JUMP_TABLE |
| 0U, // G_DYN_STACKALLOC |
| 0U, // G_READ_REGISTER |
| 0U, // G_WRITE_REGISTER |
| 0U, // ADJCALLSTACKDOWN |
| 0U, // ADJCALLSTACKUP |
| 0U, // BuildPairF64Pseudo |
| 0U, // PseudoAddTPRel |
| 0U, // PseudoAtomicLoadNand32 |
| 0U, // PseudoAtomicLoadNand64 |
| 0U, // PseudoBR |
| 0U, // PseudoBRIND |
| 0U, // PseudoCALL |
| 0U, // PseudoCALLIndirect |
| 2U, // PseudoCALLReg |
| 0U, // PseudoCmpXchg32 |
| 0U, // PseudoCmpXchg64 |
| 8U, // PseudoFLD |
| 8U, // PseudoFLW |
| 8U, // PseudoFSD |
| 8U, // PseudoFSW |
| 2U, // PseudoLA |
| 2U, // PseudoLA_TLS_GD |
| 2U, // PseudoLA_TLS_IE |
| 2U, // PseudoLB |
| 2U, // PseudoLBU |
| 2U, // PseudoLD |
| 2U, // PseudoLH |
| 2U, // PseudoLHU |
| 2U, // PseudoLI |
| 2U, // PseudoLLA |
| 2U, // PseudoLW |
| 2U, // PseudoLWU |
| 0U, // PseudoMaskedAtomicLoadAdd32 |
| 0U, // PseudoMaskedAtomicLoadMax32 |
| 0U, // PseudoMaskedAtomicLoadMin32 |
| 0U, // PseudoMaskedAtomicLoadNand32 |
| 0U, // PseudoMaskedAtomicLoadSub32 |
| 0U, // PseudoMaskedAtomicLoadUMax32 |
| 0U, // PseudoMaskedAtomicLoadUMin32 |
| 0U, // PseudoMaskedAtomicSwap32 |
| 0U, // PseudoMaskedCmpXchg32 |
| 0U, // PseudoRET |
| 8U, // PseudoSB |
| 8U, // PseudoSD |
| 8U, // PseudoSH |
| 8U, // PseudoSW |
| 0U, // PseudoTAIL |
| 0U, // PseudoTAILIndirect |
| 0U, // ReadCycleWide |
| 0U, // Select_FPR32_Using_CC_GPR |
| 0U, // Select_FPR64_Using_CC_GPR |
| 0U, // Select_GPR_Using_CC_GPR |
| 0U, // SplitF64Pseudo |
| 32U, // ADD |
| 32U, // ADDI |
| 32U, // ADDIW |
| 32U, // ADDW |
| 16U, // AMOADD_D |
| 16U, // AMOADD_D_AQ |
| 16U, // AMOADD_D_AQ_RL |
| 16U, // AMOADD_D_RL |
| 16U, // AMOADD_W |
| 16U, // AMOADD_W_AQ |
| 16U, // AMOADD_W_AQ_RL |
| 16U, // AMOADD_W_RL |
| 16U, // AMOAND_D |
| 16U, // AMOAND_D_AQ |
| 16U, // AMOAND_D_AQ_RL |
| 16U, // AMOAND_D_RL |
| 16U, // AMOAND_W |
| 16U, // AMOAND_W_AQ |
| 16U, // AMOAND_W_AQ_RL |
| 16U, // AMOAND_W_RL |
| 16U, // AMOMAXU_D |
| 16U, // AMOMAXU_D_AQ |
| 16U, // AMOMAXU_D_AQ_RL |
| 16U, // AMOMAXU_D_RL |
| 16U, // AMOMAXU_W |
| 16U, // AMOMAXU_W_AQ |
| 16U, // AMOMAXU_W_AQ_RL |
| 16U, // AMOMAXU_W_RL |
| 16U, // AMOMAX_D |
| 16U, // AMOMAX_D_AQ |
| 16U, // AMOMAX_D_AQ_RL |
| 16U, // AMOMAX_D_RL |
| 16U, // AMOMAX_W |
| 16U, // AMOMAX_W_AQ |
| 16U, // AMOMAX_W_AQ_RL |
| 16U, // AMOMAX_W_RL |
| 16U, // AMOMINU_D |
| 16U, // AMOMINU_D_AQ |
| 16U, // AMOMINU_D_AQ_RL |
| 16U, // AMOMINU_D_RL |
| 16U, // AMOMINU_W |
| 16U, // AMOMINU_W_AQ |
| 16U, // AMOMINU_W_AQ_RL |
| 16U, // AMOMINU_W_RL |
| 16U, // AMOMIN_D |
| 16U, // AMOMIN_D_AQ |
| 16U, // AMOMIN_D_AQ_RL |
| 16U, // AMOMIN_D_RL |
| 16U, // AMOMIN_W |
| 16U, // AMOMIN_W_AQ |
| 16U, // AMOMIN_W_AQ_RL |
| 16U, // AMOMIN_W_RL |
| 16U, // AMOOR_D |
| 16U, // AMOOR_D_AQ |
| 16U, // AMOOR_D_AQ_RL |
| 16U, // AMOOR_D_RL |
| 16U, // AMOOR_W |
| 16U, // AMOOR_W_AQ |
| 16U, // AMOOR_W_AQ_RL |
| 16U, // AMOOR_W_RL |
| 16U, // AMOSWAP_D |
| 16U, // AMOSWAP_D_AQ |
| 16U, // AMOSWAP_D_AQ_RL |
| 16U, // AMOSWAP_D_RL |
| 16U, // AMOSWAP_W |
| 16U, // AMOSWAP_W_AQ |
| 16U, // AMOSWAP_W_AQ_RL |
| 16U, // AMOSWAP_W_RL |
| 16U, // AMOXOR_D |
| 16U, // AMOXOR_D_AQ |
| 16U, // AMOXOR_D_AQ_RL |
| 16U, // AMOXOR_D_RL |
| 16U, // AMOXOR_W |
| 16U, // AMOXOR_W_AQ |
| 16U, // AMOXOR_W_AQ_RL |
| 16U, // AMOXOR_W_RL |
| 32U, // AND |
| 32U, // ANDI |
| 2U, // AUIPC |
| 32U, // BEQ |
| 32U, // BGE |
| 32U, // BGEU |
| 32U, // BLT |
| 32U, // BLTU |
| 32U, // BNE |
| 1U, // CSRRC |
| 1U, // CSRRCI |
| 1U, // CSRRS |
| 1U, // CSRRSI |
| 1U, // CSRRW |
| 1U, // CSRRWI |
| 2U, // C_ADD |
| 2U, // C_ADDI |
| 2U, // C_ADDI16SP |
| 32U, // C_ADDI4SPN |
| 2U, // C_ADDIW |
| 2U, // C_ADDI_HINT_IMM_ZERO |
| 2U, // C_ADDI_HINT_X0 |
| 2U, // C_ADDI_NOP |
| 2U, // C_ADDW |
| 2U, // C_ADD_HINT |
| 2U, // C_AND |
| 2U, // C_ANDI |
| 2U, // C_BEQZ |
| 2U, // C_BNEZ |
| 0U, // C_EBREAK |
| 4U, // C_FLD |
| 4U, // C_FLDSP |
| 4U, // C_FLW |
| 4U, // C_FLWSP |
| 4U, // C_FSD |
| 4U, // C_FSDSP |
| 4U, // C_FSW |
| 4U, // C_FSWSP |
| 0U, // C_J |
| 0U, // C_JAL |
| 0U, // C_JALR |
| 0U, // C_JR |
| 4U, // C_LD |
| 4U, // C_LDSP |
| 2U, // C_LI |
| 2U, // C_LI_HINT |
| 2U, // C_LUI |
| 2U, // C_LUI_HINT |
| 4U, // C_LW |
| 4U, // C_LWSP |
| 2U, // C_MV |
| 2U, // C_MV_HINT |
| 0U, // C_NOP |
| 0U, // C_NOP_HINT |
| 2U, // C_OR |
| 4U, // C_SD |
| 4U, // C_SDSP |
| 2U, // C_SLLI |
| 0U, // C_SLLI64_HINT |
| 2U, // C_SLLI_HINT |
| 2U, // C_SRAI |
| 0U, // C_SRAI64_HINT |
| 2U, // C_SRLI |
| 0U, // C_SRLI64_HINT |
| 2U, // C_SUB |
| 2U, // C_SUBW |
| 4U, // C_SW |
| 4U, // C_SWSP |
| 0U, // C_UNIMP |
| 2U, // C_XOR |
| 32U, // DIV |
| 32U, // DIVU |
| 32U, // DIVUW |
| 32U, // DIVW |
| 0U, // EBREAK |
| 0U, // ECALL |
| 64U, // FADD_D |
| 64U, // FADD_S |
| 2U, // FCLASS_D |
| 2U, // FCLASS_S |
| 24U, // FCVT_D_L |
| 24U, // FCVT_D_LU |
| 2U, // FCVT_D_S |
| 2U, // FCVT_D_W |
| 2U, // FCVT_D_WU |
| 24U, // FCVT_LU_D |
| 24U, // FCVT_LU_S |
| 24U, // FCVT_L_D |
| 24U, // FCVT_L_S |
| 24U, // FCVT_S_D |
| 24U, // FCVT_S_L |
| 24U, // FCVT_S_LU |
| 24U, // FCVT_S_W |
| 24U, // FCVT_S_WU |
| 24U, // FCVT_WU_D |
| 24U, // FCVT_WU_S |
| 24U, // FCVT_W_D |
| 24U, // FCVT_W_S |
| 64U, // FDIV_D |
| 64U, // FDIV_S |
| 0U, // FENCE |
| 0U, // FENCE_I |
| 0U, // FENCE_TSO |
| 32U, // FEQ_D |
| 32U, // FEQ_S |
| 4U, // FLD |
| 32U, // FLE_D |
| 32U, // FLE_S |
| 32U, // FLT_D |
| 32U, // FLT_S |
| 4U, // FLW |
| 128U, // FMADD_D |
| 128U, // FMADD_S |
| 32U, // FMAX_D |
| 32U, // FMAX_S |
| 32U, // FMIN_D |
| 32U, // FMIN_S |
| 128U, // FMSUB_D |
| 128U, // FMSUB_S |
| 64U, // FMUL_D |
| 64U, // FMUL_S |
| 2U, // FMV_D_X |
| 2U, // FMV_W_X |
| 2U, // FMV_X_D |
| 2U, // FMV_X_W |
| 128U, // FNMADD_D |
| 128U, // FNMADD_S |
| 128U, // FNMSUB_D |
| 128U, // FNMSUB_S |
| 4U, // FSD |
| 32U, // FSGNJN_D |
| 32U, // FSGNJN_S |
| 32U, // FSGNJX_D |
| 32U, // FSGNJX_S |
| 32U, // FSGNJ_D |
| 32U, // FSGNJ_S |
| 24U, // FSQRT_D |
| 24U, // FSQRT_S |
| 64U, // FSUB_D |
| 64U, // FSUB_S |
| 4U, // FSW |
| 2U, // JAL |
| 4U, // JALR |
| 4U, // LB |
| 4U, // LBU |
| 4U, // LD |
| 4U, // LH |
| 4U, // LHU |
| 1U, // LR_D |
| 1U, // LR_D_AQ |
| 1U, // LR_D_AQ_RL |
| 1U, // LR_D_RL |
| 1U, // LR_W |
| 1U, // LR_W_AQ |
| 1U, // LR_W_AQ_RL |
| 1U, // LR_W_RL |
| 2U, // LUI |
| 4U, // LW |
| 4U, // LWU |
| 0U, // MRET |
| 32U, // MUL |
| 32U, // MULH |
| 32U, // MULHSU |
| 32U, // MULHU |
| 32U, // MULW |
| 32U, // OR |
| 32U, // ORI |
| 32U, // REM |
| 32U, // REMU |
| 32U, // REMUW |
| 32U, // REMW |
| 4U, // SB |
| 16U, // SC_D |
| 16U, // SC_D_AQ |
| 16U, // SC_D_AQ_RL |
| 16U, // SC_D_RL |
| 16U, // SC_W |
| 16U, // SC_W_AQ |
| 16U, // SC_W_AQ_RL |
| 16U, // SC_W_RL |
| 4U, // SD |
| 2U, // SFENCE_VMA |
| 4U, // SH |
| 32U, // SLL |
| 32U, // SLLI |
| 32U, // SLLIW |
| 32U, // SLLW |
| 32U, // SLT |
| 32U, // SLTI |
| 32U, // SLTIU |
| 32U, // SLTU |
| 32U, // SRA |
| 32U, // SRAI |
| 32U, // SRAIW |
| 32U, // SRAW |
| 0U, // SRET |
| 32U, // SRL |
| 32U, // SRLI |
| 32U, // SRLIW |
| 32U, // SRLW |
| 32U, // SUB |
| 32U, // SUBW |
| 4U, // SW |
| 0U, // UNIMP |
| 0U, // URET |
| 0U, // WFI |
| 32U, // XOR |
| 32U, // XORI |
| }; |
| |
| O << "\t"; |
| |
| // Emit the opcode for the instruction. |
| uint32_t Bits = 0; |
| Bits |= OpInfo0[MI->getOpcode()] << 0; |
| Bits |= OpInfo1[MI->getOpcode()] << 16; |
| assert(Bits != 0 && "Cannot print this instruction."); |
| O << AsmStrs+(Bits & 4095)-1; |
| |
| |
| // Fragment 0 encoded into 2 bits for 4 unique commands. |
| switch ((Bits >> 12) & 3) { |
| default: llvm_unreachable("Invalid command number."); |
| case 0: |
| // DBG_VALUE, DBG_LABEL, BUNDLE, LIFETIME_START, LIFETIME_END, FENTRY_CAL... |
| return; |
| break; |
| case 1: |
| // PseudoAddTPRel, PseudoCALL, PseudoCALLReg, PseudoFLD, PseudoFLW, Pseud... |
| printOperand(MI, 0, STI, O); |
| break; |
| case 2: |
| // C_ADD, C_ADDI, C_ADDI16SP, C_ADDIW, C_ADDI_HINT_IMM_ZERO, C_ADDI_HINT_... |
| printOperand(MI, 1, STI, O); |
| break; |
| case 3: |
| // FENCE |
| printFenceArg(MI, 0, STI, O); |
| O << ", "; |
| printFenceArg(MI, 1, STI, O); |
| return; |
| break; |
| } |
| |
| |
| // Fragment 1 encoded into 1 bits for 2 unique commands. |
| if ((Bits >> 14) & 1) { |
| // PseudoCALL, PseudoTAIL, C_J, C_JAL, C_JALR, C_JR, C_NOP_HINT, C_SLLI64... |
| return; |
| } else { |
| // PseudoAddTPRel, PseudoCALLReg, PseudoFLD, PseudoFLW, PseudoFSD, Pseudo... |
| O << ", "; |
| } |
| |
| |
| // Fragment 2 encoded into 2 bits for 4 unique commands. |
| switch ((Bits >> 15) & 3) { |
| default: llvm_unreachable("Invalid command number."); |
| case 0: |
| // PseudoAddTPRel, PseudoCALLReg, PseudoLA, PseudoLA_TLS_GD, PseudoLA_TLS... |
| printOperand(MI, 1, STI, O); |
| break; |
| case 1: |
| // PseudoFLD, PseudoFLW, PseudoFSD, PseudoFSW, PseudoSB, PseudoSD, Pseudo... |
| printOperand(MI, 2, STI, O); |
| break; |
| case 2: |
| // CSRRC, CSRRCI, CSRRS, CSRRSI, CSRRW, CSRRWI |
| printCSRSystemRegister(MI, 1, STI, O); |
| O << ", "; |
| printOperand(MI, 2, STI, O); |
| return; |
| break; |
| case 3: |
| // LR_D, LR_D_AQ, LR_D_AQ_RL, LR_D_RL, LR_W, LR_W_AQ, LR_W_AQ_RL, LR_W_RL |
| printAtomicMemOp(MI, 1, STI, O); |
| return; |
| break; |
| } |
| |
| |
| // Fragment 3 encoded into 2 bits for 3 unique commands. |
| switch ((Bits >> 17) & 3) { |
| default: llvm_unreachable("Invalid command number."); |
| case 0: |
| // PseudoAddTPRel, PseudoFLD, PseudoFLW, PseudoFSD, PseudoFSW, PseudoSB, ... |
| O << ", "; |
| break; |
| case 1: |
| // PseudoCALLReg, PseudoLA, PseudoLA_TLS_GD, PseudoLA_TLS_IE, PseudoLB, P... |
| return; |
| break; |
| case 2: |
| // C_FLD, C_FLDSP, C_FLW, C_FLWSP, C_FSD, C_FSDSP, C_FSW, C_FSWSP, C_LD, ... |
| O << '('; |
| printOperand(MI, 1, STI, O); |
| O << ')'; |
| return; |
| break; |
| } |
| |
| |
| // Fragment 4 encoded into 2 bits for 4 unique commands. |
| switch ((Bits >> 19) & 3) { |
| default: llvm_unreachable("Invalid command number."); |
| case 0: |
| // PseudoAddTPRel, ADD, ADDI, ADDIW, ADDW, AND, ANDI, BEQ, BGE, BGEU, BLT... |
| printOperand(MI, 2, STI, O); |
| break; |
| case 1: |
| // PseudoFLD, PseudoFLW, PseudoFSD, PseudoFSW, PseudoSB, PseudoSD, Pseudo... |
| printOperand(MI, 1, STI, O); |
| return; |
| break; |
| case 2: |
| // AMOADD_D, AMOADD_D_AQ, AMOADD_D_AQ_RL, AMOADD_D_RL, AMOADD_W, AMOADD_W... |
| printAtomicMemOp(MI, 1, STI, O); |
| return; |
| break; |
| case 3: |
| // FCVT_D_L, FCVT_D_LU, FCVT_LU_D, FCVT_LU_S, FCVT_L_D, FCVT_L_S, FCVT_S_... |
| printFRMArg(MI, 2, STI, O); |
| return; |
| break; |
| } |
| |
| |
| // Fragment 5 encoded into 1 bits for 2 unique commands. |
| if ((Bits >> 21) & 1) { |
| // ADD, ADDI, ADDIW, ADDW, AND, ANDI, BEQ, BGE, BGEU, BLT, BLTU, BNE, C_A... |
| return; |
| } else { |
| // PseudoAddTPRel, FADD_D, FADD_S, FDIV_D, FDIV_S, FMADD_D, FMADD_S, FMSU... |
| O << ", "; |
| } |
| |
| |
| // Fragment 6 encoded into 1 bits for 2 unique commands. |
| if ((Bits >> 22) & 1) { |
| // FADD_D, FADD_S, FDIV_D, FDIV_S, FMUL_D, FMUL_S, FSUB_D, FSUB_S |
| printFRMArg(MI, 3, STI, O); |
| return; |
| } else { |
| // PseudoAddTPRel, FMADD_D, FMADD_S, FMSUB_D, FMSUB_S, FNMADD_D, FNMADD_S... |
| printOperand(MI, 3, STI, O); |
| } |
| |
| |
| // Fragment 7 encoded into 1 bits for 2 unique commands. |
| if ((Bits >> 23) & 1) { |
| // FMADD_D, FMADD_S, FMSUB_D, FMSUB_S, FNMADD_D, FNMADD_S, FNMSUB_D, FNMS... |
| O << ", "; |
| printFRMArg(MI, 4, STI, O); |
| return; |
| } else { |
| // PseudoAddTPRel |
| return; |
| } |
| |
| } |
| |
| |
| /// getRegisterName - This method is automatically generated by tblgen |
| /// from the register set description. This returns the assembler name |
| /// for the specified register. |
| const char *RISCVInstPrinter:: |
| getRegisterName(unsigned RegNo, unsigned AltIdx) { |
| assert(RegNo && RegNo < 97 && "Invalid register number!"); |
| |
| static const char AsmStrsABIRegAltName[] = { |
| /* 0 */ 'f', 's', '1', '0', 0, |
| /* 5 */ 'f', 't', '1', '0', 0, |
| /* 10 */ 'f', 'a', '0', 0, |
| /* 14 */ 'f', 's', '0', 0, |
| /* 18 */ 'f', 't', '0', 0, |
| /* 22 */ 'f', 's', '1', '1', 0, |
| /* 27 */ 'f', 't', '1', '1', 0, |
| /* 32 */ 'f', 'a', '1', 0, |
| /* 36 */ 'f', 's', '1', 0, |
| /* 40 */ 'f', 't', '1', 0, |
| /* 44 */ 'f', 'a', '2', 0, |
| /* 48 */ 'f', 's', '2', 0, |
| /* 52 */ 'f', 't', '2', 0, |
| /* 56 */ 'f', 'a', '3', 0, |
| /* 60 */ 'f', 's', '3', 0, |
| /* 64 */ 'f', 't', '3', 0, |
| /* 68 */ 'f', 'a', '4', 0, |
| /* 72 */ 'f', 's', '4', 0, |
| /* 76 */ 'f', 't', '4', 0, |
| /* 80 */ 'f', 'a', '5', 0, |
| /* 84 */ 'f', 's', '5', 0, |
| /* 88 */ 'f', 't', '5', 0, |
| /* 92 */ 'f', 'a', '6', 0, |
| /* 96 */ 'f', 's', '6', 0, |
| /* 100 */ 'f', 't', '6', 0, |
| /* 104 */ 'f', 'a', '7', 0, |
| /* 108 */ 'f', 's', '7', 0, |
| /* 112 */ 'f', 't', '7', 0, |
| /* 116 */ 'f', 's', '8', 0, |
| /* 120 */ 'f', 't', '8', 0, |
| /* 124 */ 'f', 's', '9', 0, |
| /* 128 */ 'f', 't', '9', 0, |
| /* 132 */ 'r', 'a', 0, |
| /* 135 */ 'z', 'e', 'r', 'o', 0, |
| /* 140 */ 'g', 'p', 0, |
| /* 143 */ 's', 'p', 0, |
| /* 146 */ 't', 'p', 0, |
| }; |
| |
| static const uint8_t RegAsmOffsetABIRegAltName[] = { |
| 135, 132, 143, 140, 146, 19, 41, 53, 15, 37, 11, 33, 45, 57, |
| 69, 81, 93, 105, 49, 61, 73, 85, 97, 109, 117, 125, 1, 23, |
| 65, 77, 89, 101, 18, 40, 52, 64, 76, 88, 100, 112, 14, 36, |
| 10, 32, 44, 56, 68, 80, 92, 104, 48, 60, 72, 84, 96, 108, |
| 116, 124, 0, 22, 120, 128, 5, 27, 18, 40, 52, 64, 76, 88, |
| 100, 112, 14, 36, 10, 32, 44, 56, 68, 80, 92, 104, 48, 60, |
| 72, 84, 96, 108, 116, 124, 0, 22, 120, 128, 5, 27, |
| }; |
| |
| static const char AsmStrsNoRegAltName[] = { |
| /* 0 */ 'f', '1', '0', 0, |
| /* 4 */ 'x', '1', '0', 0, |
| /* 8 */ 'f', '2', '0', 0, |
| /* 12 */ 'x', '2', '0', 0, |
| /* 16 */ 'f', '3', '0', 0, |
| /* 20 */ 'x', '3', '0', 0, |
| /* 24 */ 'f', '0', 0, |
| /* 27 */ 'x', '0', 0, |
| /* 30 */ 'f', '1', '1', 0, |
| /* 34 */ 'x', '1', '1', 0, |
| /* 38 */ 'f', '2', '1', 0, |
| /* 42 */ 'x', '2', '1', 0, |
| /* 46 */ 'f', '3', '1', 0, |
| /* 50 */ 'x', '3', '1', 0, |
| /* 54 */ 'f', '1', 0, |
| /* 57 */ 'x', '1', 0, |
| /* 60 */ 'f', '1', '2', 0, |
| /* 64 */ 'x', '1', '2', 0, |
| /* 68 */ 'f', '2', '2', 0, |
| /* 72 */ 'x', '2', '2', 0, |
| /* 76 */ 'f', '2', 0, |
| /* 79 */ 'x', '2', 0, |
| /* 82 */ 'f', '1', '3', 0, |
| /* 86 */ 'x', '1', '3', 0, |
| /* 90 */ 'f', '2', '3', 0, |
| /* 94 */ 'x', '2', '3', 0, |
| /* 98 */ 'f', '3', 0, |
| /* 101 */ 'x', '3', 0, |
| /* 104 */ 'f', '1', '4', 0, |
| /* 108 */ 'x', '1', '4', 0, |
| /* 112 */ 'f', '2', '4', 0, |
| /* 116 */ 'x', '2', '4', 0, |
| /* 120 */ 'f', '4', 0, |
| /* 123 */ 'x', '4', 0, |
| /* 126 */ 'f', '1', '5', 0, |
| /* 130 */ 'x', '1', '5', 0, |
| /* 134 */ 'f', '2', '5', 0, |
| /* 138 */ 'x', '2', '5', 0, |
| /* 142 */ 'f', '5', 0, |
| /* 145 */ 'x', '5', 0, |
| /* 148 */ 'f', '1', '6', 0, |
| /* 152 */ 'x', '1', '6', 0, |
| /* 156 */ 'f', '2', '6', 0, |
| /* 160 */ 'x', '2', '6', 0, |
| /* 164 */ 'f', '6', 0, |
| /* 167 */ 'x', '6', 0, |
| /* 170 */ 'f', '1', '7', 0, |
| /* 174 */ 'x', '1', '7', 0, |
| /* 178 */ 'f', '2', '7', 0, |
| /* 182 */ 'x', '2', '7', 0, |
| /* 186 */ 'f', '7', 0, |
| /* 189 */ 'x', '7', 0, |
| /* 192 */ 'f', '1', '8', 0, |
| /* 196 */ 'x', '1', '8', 0, |
| /* 200 */ 'f', '2', '8', 0, |
| /* 204 */ 'x', '2', '8', 0, |
| /* 208 */ 'f', '8', 0, |
| /* 211 */ 'x', '8', 0, |
| /* 214 */ 'f', '1', '9', 0, |
| /* 218 */ 'x', '1', '9', 0, |
| /* 222 */ 'f', '2', '9', 0, |
| /* 226 */ 'x', '2', '9', 0, |
| /* 230 */ 'f', '9', 0, |
| /* 233 */ 'x', '9', 0, |
| }; |
| |
| static const uint8_t RegAsmOffsetNoRegAltName[] = { |
| 27, 57, 79, 101, 123, 145, 167, 189, 211, 233, 4, 34, 64, 86, |
| 108, 130, 152, 174, 196, 218, 12, 42, 72, 94, 116, 138, 160, 182, |
| 204, 226, 20, 50, 24, 54, 76, 98, 120, 142, 164, 186, 208, 230, |
| 0, 30, 60, 82, 104, 126, 148, 170, 192, 214, 8, 38, 68, 90, |
| 112, 134, 156, 178, 200, 222, 16, 46, 24, 54, 76, 98, 120, 142, |
| 164, 186, 208, 230, 0, 30, 60, 82, 104, 126, 148, 170, 192, 214, |
| 8, 38, 68, 90, 112, 134, 156, 178, 200, 222, 16, 46, |
| }; |
| |
| switch(AltIdx) { |
| default: llvm_unreachable("Invalid register alt name index!"); |
| case RISCV::ABIRegAltName: |
| assert(*(AsmStrsABIRegAltName+RegAsmOffsetABIRegAltName[RegNo-1]) && |
| "Invalid alt name index for register!"); |
| return AsmStrsABIRegAltName+RegAsmOffsetABIRegAltName[RegNo-1]; |
| case RISCV::NoRegAltName: |
| assert(*(AsmStrsNoRegAltName+RegAsmOffsetNoRegAltName[RegNo-1]) && |
| "Invalid alt name index for register!"); |
| return AsmStrsNoRegAltName+RegAsmOffsetNoRegAltName[RegNo-1]; |
| } |
| } |
| |
| #ifdef PRINT_ALIAS_INSTR |
| #undef PRINT_ALIAS_INSTR |
| |
| static bool RISCVInstPrinterValidateMCOperand(const MCOperand &MCOp, |
| const MCSubtargetInfo &STI, |
| unsigned PredicateIndex); |
| bool RISCVInstPrinter::printAliasInstr(const MCInst *MI, const MCSubtargetInfo &STI, raw_ostream &OS) { |
| static const PatternsForOpcode OpToPatterns[] = { |
| {RISCV::ADDI, 0, 2 }, |
| {RISCV::ADDIW, 2, 1 }, |
| {RISCV::BEQ, 3, 1 }, |
| {RISCV::BGE, 4, 2 }, |
| {RISCV::BLT, 6, 2 }, |
| {RISCV::BNE, 8, 1 }, |
| {RISCV::CSRRC, 9, 1 }, |
| {RISCV::CSRRCI, 10, 1 }, |
| {RISCV::CSRRS, 11, 11 }, |
| {RISCV::CSRRSI, 22, 1 }, |
| {RISCV::CSRRW, 23, 7 }, |
| {RISCV::CSRRWI, 30, 5 }, |
| {RISCV::FADD_D, 35, 1 }, |
| {RISCV::FADD_S, 36, 1 }, |
| {RISCV::FCVT_D_L, 37, 1 }, |
| {RISCV::FCVT_D_LU, 38, 1 }, |
| {RISCV::FCVT_LU_D, 39, 1 }, |
| {RISCV::FCVT_LU_S, 40, 1 }, |
| {RISCV::FCVT_L_D, 41, 1 }, |
| {RISCV::FCVT_L_S, 42, 1 }, |
| {RISCV::FCVT_S_D, 43, 1 }, |
| {RISCV::FCVT_S_L, 44, 1 }, |
| {RISCV::FCVT_S_LU, 45, 1 }, |
| {RISCV::FCVT_S_W, 46, 1 }, |
| {RISCV::FCVT_S_WU, 47, 1 }, |
| {RISCV::FCVT_WU_D, 48, 1 }, |
| {RISCV::FCVT_WU_S, 49, 1 }, |
| {RISCV::FCVT_W_D, 50, 1 }, |
| {RISCV::FCVT_W_S, 51, 1 }, |
| {RISCV::FDIV_D, 52, 1 }, |
| {RISCV::FDIV_S, 53, 1 }, |
| {RISCV::FENCE, 54, 1 }, |
| {RISCV::FMADD_D, 55, 1 }, |
| {RISCV::FMADD_S, 56, 1 }, |
| {RISCV::FMSUB_D, 57, 1 }, |
| {RISCV::FMSUB_S, 58, 1 }, |
| {RISCV::FMUL_D, 59, 1 }, |
| {RISCV::FMUL_S, 60, 1 }, |
| {RISCV::FNMADD_D, 61, 1 }, |
| {RISCV::FNMADD_S, 62, 1 }, |
| {RISCV::FNMSUB_D, 63, 1 }, |
| {RISCV::FNMSUB_S, 64, 1 }, |
| {RISCV::FSGNJN_D, 65, 1 }, |
| {RISCV::FSGNJN_S, 66, 1 }, |
| {RISCV::FSGNJX_D, 67, 1 }, |
| {RISCV::FSGNJX_S, 68, 1 }, |
| {RISCV::FSGNJ_D, 69, 1 }, |
| {RISCV::FSGNJ_S, 70, 1 }, |
| {RISCV::FSQRT_D, 71, 1 }, |
| {RISCV::FSQRT_S, 72, 1 }, |
| {RISCV::FSUB_D, 73, 1 }, |
| {RISCV::FSUB_S, 74, 1 }, |
| {RISCV::JAL, 75, 2 }, |
| {RISCV::JALR, 77, 6 }, |
| {RISCV::SFENCE_VMA, 83, 2 }, |
| {RISCV::SLT, 85, 2 }, |
| {RISCV::SLTIU, 87, 1 }, |
| {RISCV::SLTU, 88, 1 }, |
| {RISCV::SUB, 89, 1 }, |
| {RISCV::SUBW, 90, 1 }, |
| {RISCV::XORI, 91, 1 }, |
| }; |
| |
| static const AliasPattern Patterns[] = { |
| // RISCV::ADDI - 0 |
| {0, 0, 3, 3 }, |
| {4, 3, 3, 3 }, |
| // RISCV::ADDIW - 2 |
| {14, 6, 3, 4 }, |
| // RISCV::BEQ - 3 |
| {28, 10, 3, 3 }, |
| // RISCV::BGE - 4 |
| {40, 13, 3, 3 }, |
| {52, 16, 3, 3 }, |
| // RISCV::BLT - 6 |
| {64, 19, 3, 3 }, |
| {76, 22, 3, 3 }, |
| // RISCV::BNE - 8 |
| {88, 25, 3, 3 }, |
| // RISCV::CSRRC - 9 |
| {100, 28, 3, 3 }, |
| // RISCV::CSRRCI - 10 |
| {114, 31, 3, 2 }, |
| // RISCV::CSRRS - 11 |
| {129, 33, 3, 4 }, |
| {138, 37, 3, 4 }, |
| {146, 41, 3, 4 }, |
| {157, 45, 3, 3 }, |
| {170, 48, 3, 3 }, |
| {181, 51, 3, 3 }, |
| {191, 54, 3, 4 }, |
| {205, 58, 3, 4 }, |
| {217, 62, 3, 4 }, |
| {228, 66, 3, 3 }, |
| {242, 69, 3, 3 }, |
| // RISCV::CSRRSI - 22 |
| {256, 72, 3, 2 }, |
| // RISCV::CSRRW - 23 |
| {271, 74, 3, 4 }, |
| {280, 78, 3, 4 }, |
| {288, 82, 3, 4 }, |
| {299, 86, 3, 3 }, |
| {313, 89, 3, 4 }, |
| {326, 93, 3, 4 }, |
| {338, 97, 3, 4 }, |
| // RISCV::CSRRWI - 30 |
| {353, 101, 3, 3 }, |
| {362, 104, 3, 3 }, |
| {374, 107, 3, 2 }, |
| {389, 109, 3, 3 }, |
| {402, 112, 3, 3 }, |
| // RISCV::FADD_D - 35 |
| {418, 115, 4, 5 }, |
| // RISCV::FADD_S - 36 |
| {436, 120, 4, 5 }, |
| // RISCV::FCVT_D_L - 37 |
| {454, 125, 3, 5 }, |
| // RISCV::FCVT_D_LU - 38 |
| {470, 130, 3, 5 }, |
| // RISCV::FCVT_LU_D - 39 |
| {487, 135, 3, 5 }, |
| // RISCV::FCVT_LU_S - 40 |
| {504, 140, 3, 5 }, |
| // RISCV::FCVT_L_D - 41 |
| {521, 145, 3, 5 }, |
| // RISCV::FCVT_L_S - 42 |
| {537, 150, 3, 5 }, |
| // RISCV::FCVT_S_D - 43 |
| {553, 155, 3, 4 }, |
| // RISCV::FCVT_S_L - 44 |
| {569, 159, 3, 5 }, |
| // RISCV::FCVT_S_LU - 45 |
| {585, 164, 3, 5 }, |
| // RISCV::FCVT_S_W - 46 |
| {602, 169, 3, 4 }, |
| // RISCV::FCVT_S_WU - 47 |
| {618, 173, 3, 4 }, |
| // RISCV::FCVT_WU_D - 48 |
| {635, 177, 3, 4 }, |
| // RISCV::FCVT_WU_S - 49 |
| {652, 181, 3, 4 }, |
| // RISCV::FCVT_W_D - 50 |
| {669, 185, 3, 4 }, |
| // RISCV::FCVT_W_S - 51 |
| {685, 189, 3, 4 }, |
| // RISCV::FDIV_D - 52 |
| {701, 193, 4, 5 }, |
| // RISCV::FDIV_S - 53 |
| {719, 198, 4, 5 }, |
| // RISCV::FENCE - 54 |
| {737, 203, 2, 2 }, |
| // RISCV::FMADD_D - 55 |
| {743, 205, 5, 6 }, |
| // RISCV::FMADD_S - 56 |
| {766, 211, 5, 6 }, |
| // RISCV::FMSUB_D - 57 |
| {789, 217, 5, 6 }, |
| // RISCV::FMSUB_S - 58 |
| {812, 223, 5, 6 }, |
| // RISCV::FMUL_D - 59 |
| {835, 229, 4, 5 }, |
| // RISCV::FMUL_S - 60 |
| {853, 234, 4, 5 }, |
| // RISCV::FNMADD_D - 61 |
| {871, 239, 5, 6 }, |
| // RISCV::FNMADD_S - 62 |
| {895, 245, 5, 6 }, |
| // RISCV::FNMSUB_D - 63 |
| {919, 251, 5, 6 }, |
| // RISCV::FNMSUB_S - 64 |
| {943, 257, 5, 6 }, |
| // RISCV::FSGNJN_D - 65 |
| {967, 263, 3, 4 }, |
| // RISCV::FSGNJN_S - 66 |
| {981, 267, 3, 4 }, |
| // RISCV::FSGNJX_D - 67 |
| {995, 271, 3, 4 }, |
| // RISCV::FSGNJX_S - 68 |
| {1009, 275, 3, 4 }, |
| // RISCV::FSGNJ_D - 69 |
| {1023, 279, 3, 4 }, |
| // RISCV::FSGNJ_S - 70 |
| {1036, 283, 3, 4 }, |
| // RISCV::FSQRT_D - 71 |
| {1049, 287, 3, 4 }, |
| // RISCV::FSQRT_S - 72 |
| {1064, 291, 3, 4 }, |
| // RISCV::FSUB_D - 73 |
| {1079, 295, 4, 5 }, |
| // RISCV::FSUB_S - 74 |
| {1097, 300, 4, 5 }, |
| // RISCV::JAL - 75 |
| {1115, 305, 2, 2 }, |
| {1120, 307, 2, 2 }, |
| // RISCV::JALR - 77 |
| {1127, 309, 3, 3 }, |
| {1131, 312, 3, 3 }, |
| {1137, 315, 3, 3 }, |
| {1145, 318, 3, 3 }, |
| {1157, 321, 3, 3 }, |
| {1167, 324, 3, 3 }, |
| // RISCV::SFENCE_VMA - 83 |
| {1179, 327, 2, 2 }, |
| {1190, 329, 2, 2 }, |
| // RISCV::SLT - 85 |
| {1204, 331, 3, 3 }, |
| {1216, 334, 3, 3 }, |
| // RISCV::SLTIU - 87 |
| {1228, 337, 3, 3 }, |
| // RISCV::SLTU - 88 |
| {1240, 340, 3, 3 }, |
| // RISCV::SUB - 89 |
| {1252, 343, 3, 3 }, |
| // RISCV::SUBW - 90 |
| {1263, 346, 3, 4 }, |
| // RISCV::XORI - 91 |
| {1275, 350, 3, 3 }, |
| }; |
| |
| static const AliasPatternCond Conds[] = { |
| // (ADDI X0, X0, 0) - 0 |
| {AliasPatternCond::K_Reg, RISCV::X0}, |
| {AliasPatternCond::K_Reg, RISCV::X0}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (ADDI GPR:$rd, GPR:$rs, 0) - 3 |
| {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID}, |
| {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (ADDIW GPR:$rd, GPR:$rs, 0) - 6 |
| {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID}, |
| {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| {AliasPatternCond::K_Feature, RISCV::Feature64Bit}, |
| // (BEQ GPR:$rs, X0, simm13_lsb0:$offset) - 10 |
| {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID}, |
| {AliasPatternCond::K_Reg, RISCV::X0}, |
| {AliasPatternCond::K_Custom, 1}, |
| // (BGE X0, GPR:$rs, simm13_lsb0:$offset) - 13 |
| {AliasPatternCond::K_Reg, RISCV::X0}, |
| {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID}, |
| {AliasPatternCond::K_Custom, 1}, |
| // (BGE GPR:$rs, X0, simm13_lsb0:$offset) - 16 |
| {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID}, |
| {AliasPatternCond::K_Reg, RISCV::X0}, |
| {AliasPatternCond::K_Custom, 1}, |
| // (BLT GPR:$rs, X0, simm13_lsb0:$offset) - 19 |
| {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID}, |
| {AliasPatternCond::K_Reg, RISCV::X0}, |
| {AliasPatternCond::K_Custom, 1}, |
| // (BLT X0, GPR:$rs, simm13_lsb0:$offset) - 22 |
| {AliasPatternCond::K_Reg, RISCV::X0}, |
| {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID}, |
| {AliasPatternCond::K_Custom, 1}, |
| // (BNE GPR:$rs, X0, simm13_lsb0:$offset) - 25 |
| {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID}, |
| {AliasPatternCond::K_Reg, RISCV::X0}, |
| {AliasPatternCond::K_Custom, 1}, |
| // (CSRRC X0, csr_sysreg:$csr, GPR:$rs) - 28 |
| {AliasPatternCond::K_Reg, RISCV::X0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID}, |
| // (CSRRCI X0, csr_sysreg:$csr, uimm5:$imm) - 31 |
| {AliasPatternCond::K_Reg, RISCV::X0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| // (CSRRS GPR:$rd, { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1 }, X0) - 33 |
| {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(3)}, |
| {AliasPatternCond::K_Reg, RISCV::X0}, |
| {AliasPatternCond::K_Feature, RISCV::FeatureStdExtF}, |
| // (CSRRS GPR:$rd, { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 }, X0) - 37 |
| {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(2)}, |
| {AliasPatternCond::K_Reg, RISCV::X0}, |
| {AliasPatternCond::K_Feature, RISCV::FeatureStdExtF}, |
| // (CSRRS GPR:$rd, { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 }, X0) - 41 |
| {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Reg, RISCV::X0}, |
| {AliasPatternCond::K_Feature, RISCV::FeatureStdExtF}, |
| // (CSRRS GPR:$rd, { 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 }, X0) - 45 |
| {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(3074)}, |
| {AliasPatternCond::K_Reg, RISCV::X0}, |
| // (CSRRS GPR:$rd, { 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, X0) - 48 |
| {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(3072)}, |
| {AliasPatternCond::K_Reg, RISCV::X0}, |
| // (CSRRS GPR:$rd, { 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 }, X0) - 51 |
| {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(3073)}, |
| {AliasPatternCond::K_Reg, RISCV::X0}, |
| // (CSRRS GPR:$rd, { 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0 }, X0) - 54 |
| {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(3202)}, |
| {AliasPatternCond::K_Reg, RISCV::X0}, |
| {AliasPatternCond::K_NegFeature, RISCV::Feature64Bit}, |
| // (CSRRS GPR:$rd, { 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 }, X0) - 58 |
| {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(3200)}, |
| {AliasPatternCond::K_Reg, RISCV::X0}, |
| {AliasPatternCond::K_NegFeature, RISCV::Feature64Bit}, |
| // (CSRRS GPR:$rd, { 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1 }, X0) - 62 |
| {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(3201)}, |
| {AliasPatternCond::K_Reg, RISCV::X0}, |
| {AliasPatternCond::K_NegFeature, RISCV::Feature64Bit}, |
| // (CSRRS GPR:$rd, csr_sysreg:$csr, X0) - 66 |
| {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_Reg, RISCV::X0}, |
| // (CSRRS X0, csr_sysreg:$csr, GPR:$rs) - 69 |
| {AliasPatternCond::K_Reg, RISCV::X0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID}, |
| // (CSRRSI X0, csr_sysreg:$csr, uimm5:$imm) - 72 |
| {AliasPatternCond::K_Reg, RISCV::X0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| // (CSRRW X0, { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1 }, GPR:$rs) - 74 |
| {AliasPatternCond::K_Reg, RISCV::X0}, |
| {AliasPatternCond::K_Imm, uint32_t(3)}, |
| {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID}, |
| {AliasPatternCond::K_Feature, RISCV::FeatureStdExtF}, |
| // (CSRRW X0, { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 }, GPR:$rs) - 78 |
| {AliasPatternCond::K_Reg, RISCV::X0}, |
| {AliasPatternCond::K_Imm, uint32_t(2)}, |
| {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID}, |
| {AliasPatternCond::K_Feature, RISCV::FeatureStdExtF}, |
| // (CSRRW X0, { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 }, GPR:$rs) - 82 |
| {AliasPatternCond::K_Reg, RISCV::X0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID}, |
| {AliasPatternCond::K_Feature, RISCV::FeatureStdExtF}, |
| // (CSRRW X0, csr_sysreg:$csr, GPR:$rs) - 86 |
| {AliasPatternCond::K_Reg, RISCV::X0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID}, |
| // (CSRRW GPR:$rd, { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1 }, GPR:$rs) - 89 |
| {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(3)}, |
| {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID}, |
| {AliasPatternCond::K_Feature, RISCV::FeatureStdExtF}, |
| // (CSRRW GPR:$rd, { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 }, GPR:$rs) - 93 |
| {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(2)}, |
| {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID}, |
| {AliasPatternCond::K_Feature, RISCV::FeatureStdExtF}, |
| // (CSRRW GPR:$rd, { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 }, GPR:$rs) - 97 |
| {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID}, |
| {AliasPatternCond::K_Feature, RISCV::FeatureStdExtF}, |
| // (CSRRWI X0, { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 }, uimm5:$imm) - 101 |
| {AliasPatternCond::K_Reg, RISCV::X0}, |
| {AliasPatternCond::K_Imm, uint32_t(2)}, |
| {AliasPatternCond::K_Feature, RISCV::FeatureStdExtF}, |
| // (CSRRWI X0, { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 }, uimm5:$imm) - 104 |
| {AliasPatternCond::K_Reg, RISCV::X0}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, RISCV::FeatureStdExtF}, |
| // (CSRRWI X0, csr_sysreg:$csr, uimm5:$imm) - 107 |
| {AliasPatternCond::K_Reg, RISCV::X0}, |
| {AliasPatternCond::K_Ignore, 0}, |
| // (CSRRWI GPR:$rd, { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 }, uimm5:$imm) - 109 |
| {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(2)}, |
| {AliasPatternCond::K_Feature, RISCV::FeatureStdExtF}, |
| // (CSRRWI GPR:$rd, { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 }, uimm5:$imm) - 112 |
| {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| {AliasPatternCond::K_Feature, RISCV::FeatureStdExtF}, |
| // (FADD_D FPR64:$rd, FPR64:$rs1, FPR64:$rs2, { 1, 1, 1 }) - 115 |
| {AliasPatternCond::K_RegClass, RISCV::FPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, RISCV::FPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, RISCV::FPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(7)}, |
| {AliasPatternCond::K_Feature, RISCV::FeatureStdExtD}, |
| // (FADD_S FPR32:$rd, FPR32:$rs1, FPR32:$rs2, { 1, 1, 1 }) - 120 |
| {AliasPatternCond::K_RegClass, RISCV::FPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, RISCV::FPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, RISCV::FPR32RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(7)}, |
| {AliasPatternCond::K_Feature, RISCV::FeatureStdExtF}, |
| // (FCVT_D_L FPR64:$rd, GPR:$rs1, { 1, 1, 1 }) - 125 |
| {AliasPatternCond::K_RegClass, RISCV::FPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(7)}, |
| {AliasPatternCond::K_Feature, RISCV::FeatureStdExtD}, |
| {AliasPatternCond::K_Feature, RISCV::Feature64Bit}, |
| // (FCVT_D_LU FPR64:$rd, GPR:$rs1, { 1, 1, 1 }) - 130 |
| {AliasPatternCond::K_RegClass, RISCV::FPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(7)}, |
| {AliasPatternCond::K_Feature, RISCV::FeatureStdExtD}, |
| {AliasPatternCond::K_Feature, RISCV::Feature64Bit}, |
| // (FCVT_LU_D GPR:$rd, FPR64:$rs1, { 1, 1, 1 }) - 135 |
| {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID}, |
| {AliasPatternCond::K_RegClass, RISCV::FPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(7)}, |
| {AliasPatternCond::K_Feature, RISCV::FeatureStdExtD}, |
| {AliasPatternCond::K_Feature, RISCV::Feature64Bit}, |
| // (FCVT_LU_S GPR:$rd, FPR32:$rs1, { 1, 1, 1 }) - 140 |
| {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID}, |
| {AliasPatternCond::K_RegClass, RISCV::FPR32RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(7)}, |
| {AliasPatternCond::K_Feature, RISCV::FeatureStdExtF}, |
| {AliasPatternCond::K_Feature, RISCV::Feature64Bit}, |
| // (FCVT_L_D GPR:$rd, FPR64:$rs1, { 1, 1, 1 }) - 145 |
| {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID}, |
| {AliasPatternCond::K_RegClass, RISCV::FPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(7)}, |
| {AliasPatternCond::K_Feature, RISCV::FeatureStdExtD}, |
| {AliasPatternCond::K_Feature, RISCV::Feature64Bit}, |
| // (FCVT_L_S GPR:$rd, FPR32:$rs1, { 1, 1, 1 }) - 150 |
| {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID}, |
| {AliasPatternCond::K_RegClass, RISCV::FPR32RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(7)}, |
| {AliasPatternCond::K_Feature, RISCV::FeatureStdExtF}, |
| {AliasPatternCond::K_Feature, RISCV::Feature64Bit}, |
| // (FCVT_S_D FPR32:$rd, FPR64:$rs1, { 1, 1, 1 }) - 155 |
| {AliasPatternCond::K_RegClass, RISCV::FPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, RISCV::FPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(7)}, |
| {AliasPatternCond::K_Feature, RISCV::FeatureStdExtD}, |
| // (FCVT_S_L FPR32:$rd, GPR:$rs1, { 1, 1, 1 }) - 159 |
| {AliasPatternCond::K_RegClass, RISCV::FPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(7)}, |
| {AliasPatternCond::K_Feature, RISCV::FeatureStdExtF}, |
| {AliasPatternCond::K_Feature, RISCV::Feature64Bit}, |
| // (FCVT_S_LU FPR32:$rd, GPR:$rs1, { 1, 1, 1 }) - 164 |
| {AliasPatternCond::K_RegClass, RISCV::FPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(7)}, |
| {AliasPatternCond::K_Feature, RISCV::FeatureStdExtF}, |
| {AliasPatternCond::K_Feature, RISCV::Feature64Bit}, |
| // (FCVT_S_W FPR32:$rd, GPR:$rs1, { 1, 1, 1 }) - 169 |
| {AliasPatternCond::K_RegClass, RISCV::FPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(7)}, |
| {AliasPatternCond::K_Feature, RISCV::FeatureStdExtF}, |
| // (FCVT_S_WU FPR32:$rd, GPR:$rs1, { 1, 1, 1 }) - 173 |
| {AliasPatternCond::K_RegClass, RISCV::FPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(7)}, |
| {AliasPatternCond::K_Feature, RISCV::FeatureStdExtF}, |
| // (FCVT_WU_D GPR:$rd, FPR64:$rs1, { 1, 1, 1 }) - 177 |
| {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID}, |
| {AliasPatternCond::K_RegClass, RISCV::FPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(7)}, |
| {AliasPatternCond::K_Feature, RISCV::FeatureStdExtD}, |
| // (FCVT_WU_S GPR:$rd, FPR32:$rs1, { 1, 1, 1 }) - 181 |
| {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID}, |
| {AliasPatternCond::K_RegClass, RISCV::FPR32RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(7)}, |
| {AliasPatternCond::K_Feature, RISCV::FeatureStdExtF}, |
| // (FCVT_W_D GPR:$rd, FPR64:$rs1, { 1, 1, 1 }) - 185 |
| {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID}, |
| {AliasPatternCond::K_RegClass, RISCV::FPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(7)}, |
| {AliasPatternCond::K_Feature, RISCV::FeatureStdExtD}, |
| // (FCVT_W_S GPR:$rd, FPR32:$rs1, { 1, 1, 1 }) - 189 |
| {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID}, |
| {AliasPatternCond::K_RegClass, RISCV::FPR32RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(7)}, |
| {AliasPatternCond::K_Feature, RISCV::FeatureStdExtF}, |
| // (FDIV_D FPR64:$rd, FPR64:$rs1, FPR64:$rs2, { 1, 1, 1 }) - 193 |
| {AliasPatternCond::K_RegClass, RISCV::FPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, RISCV::FPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, RISCV::FPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(7)}, |
| {AliasPatternCond::K_Feature, RISCV::FeatureStdExtD}, |
| // (FDIV_S FPR32:$rd, FPR32:$rs1, FPR32:$rs2, { 1, 1, 1 }) - 198 |
| {AliasPatternCond::K_RegClass, RISCV::FPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, RISCV::FPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, RISCV::FPR32RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(7)}, |
| {AliasPatternCond::K_Feature, RISCV::FeatureStdExtF}, |
| // (FENCE 15, 15) - 203 |
| {AliasPatternCond::K_Imm, uint32_t(15)}, |
| {AliasPatternCond::K_Imm, uint32_t(15)}, |
| // (FMADD_D FPR64:$rd, FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, { 1, 1, 1 }) - 205 |
| {AliasPatternCond::K_RegClass, RISCV::FPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, RISCV::FPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, RISCV::FPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, RISCV::FPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(7)}, |
| {AliasPatternCond::K_Feature, RISCV::FeatureStdExtD}, |
| // (FMADD_S FPR32:$rd, FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, { 1, 1, 1 }) - 211 |
| {AliasPatternCond::K_RegClass, RISCV::FPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, RISCV::FPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, RISCV::FPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, RISCV::FPR32RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(7)}, |
| {AliasPatternCond::K_Feature, RISCV::FeatureStdExtF}, |
| // (FMSUB_D FPR64:$rd, FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, { 1, 1, 1 }) - 217 |
| {AliasPatternCond::K_RegClass, RISCV::FPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, RISCV::FPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, RISCV::FPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, RISCV::FPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(7)}, |
| {AliasPatternCond::K_Feature, RISCV::FeatureStdExtD}, |
| // (FMSUB_S FPR32:$rd, FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, { 1, 1, 1 }) - 223 |
| {AliasPatternCond::K_RegClass, RISCV::FPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, RISCV::FPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, RISCV::FPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, RISCV::FPR32RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(7)}, |
| {AliasPatternCond::K_Feature, RISCV::FeatureStdExtF}, |
| // (FMUL_D FPR64:$rd, FPR64:$rs1, FPR64:$rs2, { 1, 1, 1 }) - 229 |
| {AliasPatternCond::K_RegClass, RISCV::FPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, RISCV::FPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, RISCV::FPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(7)}, |
| {AliasPatternCond::K_Feature, RISCV::FeatureStdExtD}, |
| // (FMUL_S FPR32:$rd, FPR32:$rs1, FPR32:$rs2, { 1, 1, 1 }) - 234 |
| {AliasPatternCond::K_RegClass, RISCV::FPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, RISCV::FPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, RISCV::FPR32RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(7)}, |
| {AliasPatternCond::K_Feature, RISCV::FeatureStdExtF}, |
| // (FNMADD_D FPR64:$rd, FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, { 1, 1, 1 }) - 239 |
| {AliasPatternCond::K_RegClass, RISCV::FPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, RISCV::FPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, RISCV::FPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, RISCV::FPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(7)}, |
| {AliasPatternCond::K_Feature, RISCV::FeatureStdExtD}, |
| // (FNMADD_S FPR32:$rd, FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, { 1, 1, 1 }) - 245 |
| {AliasPatternCond::K_RegClass, RISCV::FPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, RISCV::FPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, RISCV::FPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, RISCV::FPR32RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(7)}, |
| {AliasPatternCond::K_Feature, RISCV::FeatureStdExtF}, |
| // (FNMSUB_D FPR64:$rd, FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, { 1, 1, 1 }) - 251 |
| {AliasPatternCond::K_RegClass, RISCV::FPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, RISCV::FPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, RISCV::FPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, RISCV::FPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(7)}, |
| {AliasPatternCond::K_Feature, RISCV::FeatureStdExtD}, |
| // (FNMSUB_S FPR32:$rd, FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, { 1, 1, 1 }) - 257 |
| {AliasPatternCond::K_RegClass, RISCV::FPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, RISCV::FPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, RISCV::FPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, RISCV::FPR32RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(7)}, |
| {AliasPatternCond::K_Feature, RISCV::FeatureStdExtF}, |
| // (FSGNJN_D FPR64:$rd, FPR64:$rs, FPR64:$rs) - 263 |
| {AliasPatternCond::K_RegClass, RISCV::FPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, RISCV::FPR64RegClassID}, |
| {AliasPatternCond::K_TiedReg, 1}, |
| {AliasPatternCond::K_Feature, RISCV::FeatureStdExtD}, |
| // (FSGNJN_S FPR32:$rd, FPR32:$rs, FPR32:$rs) - 267 |
| {AliasPatternCond::K_RegClass, RISCV::FPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, RISCV::FPR32RegClassID}, |
| {AliasPatternCond::K_TiedReg, 1}, |
| {AliasPatternCond::K_Feature, RISCV::FeatureStdExtF}, |
| // (FSGNJX_D FPR64:$rd, FPR64:$rs, FPR64:$rs) - 271 |
| {AliasPatternCond::K_RegClass, RISCV::FPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, RISCV::FPR64RegClassID}, |
| {AliasPatternCond::K_TiedReg, 1}, |
| {AliasPatternCond::K_Feature, RISCV::FeatureStdExtD}, |
| // (FSGNJX_S FPR32:$rd, FPR32:$rs, FPR32:$rs) - 275 |
| {AliasPatternCond::K_RegClass, RISCV::FPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, RISCV::FPR32RegClassID}, |
| {AliasPatternCond::K_TiedReg, 1}, |
| {AliasPatternCond::K_Feature, RISCV::FeatureStdExtF}, |
| // (FSGNJ_D FPR64:$rd, FPR64:$rs, FPR64:$rs) - 279 |
| {AliasPatternCond::K_RegClass, RISCV::FPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, RISCV::FPR64RegClassID}, |
| {AliasPatternCond::K_TiedReg, 1}, |
| {AliasPatternCond::K_Feature, RISCV::FeatureStdExtD}, |
| // (FSGNJ_S FPR32:$rd, FPR32:$rs, FPR32:$rs) - 283 |
| {AliasPatternCond::K_RegClass, RISCV::FPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, RISCV::FPR32RegClassID}, |
| {AliasPatternCond::K_TiedReg, 1}, |
| {AliasPatternCond::K_Feature, RISCV::FeatureStdExtF}, |
| // (FSQRT_D FPR64:$rd, FPR64:$rs1, { 1, 1, 1 }) - 287 |
| {AliasPatternCond::K_RegClass, RISCV::FPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, RISCV::FPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(7)}, |
| {AliasPatternCond::K_Feature, RISCV::FeatureStdExtD}, |
| // (FSQRT_S FPR32:$rd, FPR32:$rs1, { 1, 1, 1 }) - 291 |
| {AliasPatternCond::K_RegClass, RISCV::FPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, RISCV::FPR32RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(7)}, |
| {AliasPatternCond::K_Feature, RISCV::FeatureStdExtF}, |
| // (FSUB_D FPR64:$rd, FPR64:$rs1, FPR64:$rs2, { 1, 1, 1 }) - 295 |
| {AliasPatternCond::K_RegClass, RISCV::FPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, RISCV::FPR64RegClassID}, |
| {AliasPatternCond::K_RegClass, RISCV::FPR64RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(7)}, |
| {AliasPatternCond::K_Feature, RISCV::FeatureStdExtD}, |
| // (FSUB_S FPR32:$rd, FPR32:$rs1, FPR32:$rs2, { 1, 1, 1 }) - 300 |
| {AliasPatternCond::K_RegClass, RISCV::FPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, RISCV::FPR32RegClassID}, |
| {AliasPatternCond::K_RegClass, RISCV::FPR32RegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(7)}, |
| {AliasPatternCond::K_Feature, RISCV::FeatureStdExtF}, |
| // (JAL X0, simm21_lsb0_jal:$offset) - 305 |
| {AliasPatternCond::K_Reg, RISCV::X0}, |
| {AliasPatternCond::K_Custom, 2}, |
| // (JAL X1, simm21_lsb0_jal:$offset) - 307 |
| {AliasPatternCond::K_Reg, RISCV::X1}, |
| {AliasPatternCond::K_Custom, 2}, |
| // (JALR X0, X1, 0) - 309 |
| {AliasPatternCond::K_Reg, RISCV::X0}, |
| {AliasPatternCond::K_Reg, RISCV::X1}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (JALR X0, GPR:$rs, 0) - 312 |
| {AliasPatternCond::K_Reg, RISCV::X0}, |
| {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (JALR X1, GPR:$rs, 0) - 315 |
| {AliasPatternCond::K_Reg, RISCV::X1}, |
| {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (JALR GPR:$rd, GPR:$rs, 0) - 318 |
| {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID}, |
| {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(0)}, |
| // (JALR X0, GPR:$rs, simm12:$offset) - 321 |
| {AliasPatternCond::K_Reg, RISCV::X0}, |
| {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID}, |
| {AliasPatternCond::K_Custom, 3}, |
| // (JALR X1, GPR:$rs, simm12:$offset) - 324 |
| {AliasPatternCond::K_Reg, RISCV::X1}, |
| {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID}, |
| {AliasPatternCond::K_Custom, 3}, |
| // (SFENCE_VMA X0, X0) - 327 |
| {AliasPatternCond::K_Reg, RISCV::X0}, |
| {AliasPatternCond::K_Reg, RISCV::X0}, |
| // (SFENCE_VMA GPR:$rs, X0) - 329 |
| {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID}, |
| {AliasPatternCond::K_Reg, RISCV::X0}, |
| // (SLT GPR:$rd, GPR:$rs, X0) - 331 |
| {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID}, |
| {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID}, |
| {AliasPatternCond::K_Reg, RISCV::X0}, |
| // (SLT GPR:$rd, X0, GPR:$rs) - 334 |
| {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID}, |
| {AliasPatternCond::K_Reg, RISCV::X0}, |
| {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID}, |
| // (SLTIU GPR:$rd, GPR:$rs, 1) - 337 |
| {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID}, |
| {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(1)}, |
| // (SLTU GPR:$rd, X0, GPR:$rs) - 340 |
| {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID}, |
| {AliasPatternCond::K_Reg, RISCV::X0}, |
| {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID}, |
| // (SUB GPR:$rd, X0, GPR:$rs) - 343 |
| {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID}, |
| {AliasPatternCond::K_Reg, RISCV::X0}, |
| {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID}, |
| // (SUBW GPR:$rd, X0, GPR:$rs) - 346 |
| {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID}, |
| {AliasPatternCond::K_Reg, RISCV::X0}, |
| {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID}, |
| {AliasPatternCond::K_Feature, RISCV::Feature64Bit}, |
| // (XORI GPR:$rd, GPR:$rs, -1) - 350 |
| {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID}, |
| {AliasPatternCond::K_RegClass, RISCV::GPRRegClassID}, |
| {AliasPatternCond::K_Imm, uint32_t(-1)}, |
| }; |
| |
| static const char AsmStrings[] = |
| /* 0 */ "nop\0" |
| /* 4 */ "mv $\x01, $\x02\0" |
| /* 14 */ "sext.w $\x01, $\x02\0" |
| /* 28 */ "beqz $\x01, $\x03\0" |
| /* 40 */ "blez $\x02, $\x03\0" |
| /* 52 */ "bgez $\x01, $\x03\0" |
| /* 64 */ "bltz $\x01, $\x03\0" |
| /* 76 */ "bgtz $\x02, $\x03\0" |
| /* 88 */ "bnez $\x01, $\x03\0" |
| /* 100 */ "csrc $\xFF\x02\x01, $\x03\0" |
| /* 114 */ "csrci $\xFF\x02\x01, $\x03\0" |
| /* 129 */ "frcsr $\x01\0" |
| /* 138 */ "frrm $\x01\0" |
| /* 146 */ "frflags $\x01\0" |
| /* 157 */ "rdinstret $\x01\0" |
| /* 170 */ "rdcycle $\x01\0" |
| /* 181 */ "rdtime $\x01\0" |
| /* 191 */ "rdinstreth $\x01\0" |
| /* 205 */ "rdcycleh $\x01\0" |
| /* 217 */ "rdtimeh $\x01\0" |
| /* 228 */ "csrr $\x01, $\xFF\x02\x01\0" |
| /* 242 */ "csrs $\xFF\x02\x01, $\x03\0" |
| /* 256 */ "csrsi $\xFF\x02\x01, $\x03\0" |
| /* 271 */ "fscsr $\x03\0" |
| /* 280 */ "fsrm $\x03\0" |
| /* 288 */ "fsflags $\x03\0" |
| /* 299 */ "csrw $\xFF\x02\x01, $\x03\0" |
| /* 313 */ "fscsr $\x01, $\x03\0" |
| /* 326 */ "fsrm $\x01, $\x03\0" |
| /* 338 */ "fsflags $\x01, $\x03\0" |
| /* 353 */ "fsrmi $\x03\0" |
| /* 362 */ "fsflagsi $\x03\0" |
| /* 374 */ "csrwi $\xFF\x02\x01, $\x03\0" |
| /* 389 */ "fsrmi $\x01, $\x03\0" |
| /* 402 */ "fsflagsi $\x01, $\x03\0" |
| /* 418 */ "fadd.d $\x01, $\x02, $\x03\0" |
| /* 436 */ "fadd.s $\x01, $\x02, $\x03\0" |
| /* 454 */ "fcvt.d.l $\x01, $\x02\0" |
| /* 470 */ "fcvt.d.lu $\x01, $\x02\0" |
| /* 487 */ "fcvt.lu.d $\x01, $\x02\0" |
| /* 504 */ "fcvt.lu.s $\x01, $\x02\0" |
| /* 521 */ "fcvt.l.d $\x01, $\x02\0" |
| /* 537 */ "fcvt.l.s $\x01, $\x02\0" |
| /* 553 */ "fcvt.s.d $\x01, $\x02\0" |
| /* 569 */ "fcvt.s.l $\x01, $\x02\0" |
| /* 585 */ "fcvt.s.lu $\x01, $\x02\0" |
| /* 602 */ "fcvt.s.w $\x01, $\x02\0" |
| /* 618 */ "fcvt.s.wu $\x01, $\x02\0" |
| /* 635 */ "fcvt.wu.d $\x01, $\x02\0" |
| /* 652 */ "fcvt.wu.s $\x01, $\x02\0" |
| /* 669 */ "fcvt.w.d $\x01, $\x02\0" |
| /* 685 */ "fcvt.w.s $\x01, $\x02\0" |
| /* 701 */ "fdiv.d $\x01, $\x02, $\x03\0" |
| /* 719 */ "fdiv.s $\x01, $\x02, $\x03\0" |
| /* 737 */ "fence\0" |
| /* 743 */ "fmadd.d $\x01, $\x02, $\x03, $\x04\0" |
| /* 766 */ "fmadd.s $\x01, $\x02, $\x03, $\x04\0" |
| /* 789 */ "fmsub.d $\x01, $\x02, $\x03, $\x04\0" |
| /* 812 */ "fmsub.s $\x01, $\x02, $\x03, $\x04\0" |
| /* 835 */ "fmul.d $\x01, $\x02, $\x03\0" |
| /* 853 */ "fmul.s $\x01, $\x02, $\x03\0" |
| /* 871 */ "fnmadd.d $\x01, $\x02, $\x03, $\x04\0" |
| /* 895 */ "fnmadd.s $\x01, $\x02, $\x03, $\x04\0" |
| /* 919 */ "fnmsub.d $\x01, $\x02, $\x03, $\x04\0" |
| /* 943 */ "fnmsub.s $\x01, $\x02, $\x03, $\x04\0" |
| /* 967 */ "fneg.d $\x01, $\x02\0" |
| /* 981 */ "fneg.s $\x01, $\x02\0" |
| /* 995 */ "fabs.d $\x01, $\x02\0" |
| /* 1009 */ "fabs.s $\x01, $\x02\0" |
| /* 1023 */ "fmv.d $\x01, $\x02\0" |
| /* 1036 */ "fmv.s $\x01, $\x02\0" |
| /* 1049 */ "fsqrt.d $\x01, $\x02\0" |
| /* 1064 */ "fsqrt.s $\x01, $\x02\0" |
| /* 1079 */ "fsub.d $\x01, $\x02, $\x03\0" |
| /* 1097 */ "fsub.s $\x01, $\x02, $\x03\0" |
| /* 1115 */ "j $\x02\0" |
| /* 1120 */ "jal $\x02\0" |
| /* 1127 */ "ret\0" |
| /* 1131 */ "jr $\x02\0" |
| /* 1137 */ "jalr $\x02\0" |
| /* 1145 */ "jalr $\x01, $\x02\0" |
| /* 1157 */ "jr $\x03($\x02)\0" |
| /* 1167 */ "jalr $\x03($\x02)\0" |
| /* 1179 */ "sfence.vma\0" |
| /* 1190 */ "sfence.vma $\x01\0" |
| /* 1204 */ "sltz $\x01, $\x02\0" |
| /* 1216 */ "sgtz $\x01, $\x03\0" |
| /* 1228 */ "seqz $\x01, $\x02\0" |
| /* 1240 */ "snez $\x01, $\x03\0" |
| /* 1252 */ "neg $\x01, $\x03\0" |
| /* 1263 */ "negw $\x01, $\x03\0" |
| /* 1275 */ "not $\x01, $\x02\0" |
| ; |
| |
| #ifndef NDEBUG |
| static struct SortCheck { |
| SortCheck(ArrayRef<PatternsForOpcode> OpToPatterns) { |
| assert(std::is_sorted( |
| OpToPatterns.begin(), OpToPatterns.end(), |
| [](const PatternsForOpcode &L, const PatternsForOpcode &R) { |
| return L.Opcode < R.Opcode; |
| }) && |
| "tablegen failed to sort opcode patterns"); |
| } |
| } sortCheckVar(OpToPatterns); |
| #endif |
| |
| AliasMatchingData M { |
| makeArrayRef(OpToPatterns), |
| makeArrayRef(Patterns), |
| makeArrayRef(Conds), |
| StringRef(AsmStrings, array_lengthof(AsmStrings)), |
| &RISCVInstPrinterValidateMCOperand, |
| }; |
| const char *AsmString = matchAliasPatterns(MI, &STI, M); |
| if (!AsmString) return false; |
| |
| unsigned I = 0; |
| while (AsmString[I] != ' ' && AsmString[I] != '\t' && |
| AsmString[I] != '$' && AsmString[I] != '\0') |
| ++I; |
| OS << '\t' << StringRef(AsmString, I); |
| if (AsmString[I] != '\0') { |
| if (AsmString[I] == ' ' || AsmString[I] == '\t') { |
| OS << '\t'; |
| ++I; |
| } |
| do { |
| if (AsmString[I] == '$') { |
| ++I; |
| if (AsmString[I] == (char)0xff) { |
| ++I; |
| int OpIdx = AsmString[I++] - 1; |
| int PrintMethodIdx = AsmString[I++] - 1; |
| printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, STI, OS); |
| } else |
| printOperand(MI, unsigned(AsmString[I++]) - 1, STI, OS); |
| } else { |
| OS << AsmString[I++]; |
| } |
| } while (AsmString[I] != '\0'); |
| } |
| |
| return true; |
| } |
| |
| void RISCVInstPrinter::printCustomAliasOperand( |
| const MCInst *MI, unsigned OpIdx, |
| unsigned PrintMethodIdx, |
| const MCSubtargetInfo &STI, |
| raw_ostream &OS) { |
| switch (PrintMethodIdx) { |
| default: |
| llvm_unreachable("Unknown PrintMethod kind"); |
| break; |
| case 0: |
| printCSRSystemRegister(MI, OpIdx, STI, OS); |
| break; |
| } |
| } |
| |
| static bool RISCVInstPrinterValidateMCOperand(const MCOperand &MCOp, |
| const MCSubtargetInfo &STI, |
| unsigned PredicateIndex) { |
| switch (PredicateIndex) { |
| default: |
| llvm_unreachable("Unknown MCOperandPredicate kind"); |
| break; |
| case 1: { |
| |
| int64_t Imm; |
| if (MCOp.evaluateAsConstantImm(Imm)) |
| return isShiftedInt<12, 1>(Imm); |
| return MCOp.isBareSymbolRef(); |
| |
| } |
| case 2: { |
| |
| int64_t Imm; |
| if (MCOp.evaluateAsConstantImm(Imm)) |
| return isShiftedInt<20, 1>(Imm); |
| return MCOp.isBareSymbolRef(); |
| |
| } |
| case 3: { |
| |
| int64_t Imm; |
| if (MCOp.evaluateAsConstantImm(Imm)) |
| return isInt<12>(Imm); |
| return MCOp.isBareSymbolRef(); |
| |
| } |
| } |
| } |
| |
| #endif // PRINT_ALIAS_INSTR |