| /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
| |* *| |
| |* Target Instruction Enum Values and Descriptors *| |
| |* *| |
| |* Automatically generated file, do not edit! *| |
| |* *| |
| \*===----------------------------------------------------------------------===*/ |
| |
| #ifdef GET_INSTRINFO_ENUM |
| #undef GET_INSTRINFO_ENUM |
| namespace llvm { |
| |
| namespace Mips { |
| enum { |
| PHI = 0, |
| INLINEASM = 1, |
| INLINEASM_BR = 2, |
| CFI_INSTRUCTION = 3, |
| EH_LABEL = 4, |
| GC_LABEL = 5, |
| ANNOTATION_LABEL = 6, |
| KILL = 7, |
| EXTRACT_SUBREG = 8, |
| INSERT_SUBREG = 9, |
| IMPLICIT_DEF = 10, |
| SUBREG_TO_REG = 11, |
| COPY_TO_REGCLASS = 12, |
| DBG_VALUE = 13, |
| DBG_LABEL = 14, |
| REG_SEQUENCE = 15, |
| COPY = 16, |
| BUNDLE = 17, |
| LIFETIME_START = 18, |
| LIFETIME_END = 19, |
| STACKMAP = 20, |
| FENTRY_CALL = 21, |
| PATCHPOINT = 22, |
| LOAD_STACK_GUARD = 23, |
| STATEPOINT = 24, |
| LOCAL_ESCAPE = 25, |
| FAULTING_OP = 26, |
| PATCHABLE_OP = 27, |
| PATCHABLE_FUNCTION_ENTER = 28, |
| PATCHABLE_RET = 29, |
| PATCHABLE_FUNCTION_EXIT = 30, |
| PATCHABLE_TAIL_CALL = 31, |
| PATCHABLE_EVENT_CALL = 32, |
| PATCHABLE_TYPED_EVENT_CALL = 33, |
| ICALL_BRANCH_FUNNEL = 34, |
| G_ADD = 35, |
| G_SUB = 36, |
| G_MUL = 37, |
| G_SDIV = 38, |
| G_UDIV = 39, |
| G_SREM = 40, |
| G_UREM = 41, |
| G_AND = 42, |
| G_OR = 43, |
| G_XOR = 44, |
| G_IMPLICIT_DEF = 45, |
| G_PHI = 46, |
| G_FRAME_INDEX = 47, |
| G_GLOBAL_VALUE = 48, |
| G_EXTRACT = 49, |
| G_UNMERGE_VALUES = 50, |
| G_INSERT = 51, |
| G_MERGE_VALUES = 52, |
| G_BUILD_VECTOR = 53, |
| G_BUILD_VECTOR_TRUNC = 54, |
| G_CONCAT_VECTORS = 55, |
| G_PTRTOINT = 56, |
| G_INTTOPTR = 57, |
| G_BITCAST = 58, |
| G_INTRINSIC_TRUNC = 59, |
| G_INTRINSIC_ROUND = 60, |
| G_READCYCLECOUNTER = 61, |
| G_LOAD = 62, |
| G_SEXTLOAD = 63, |
| G_ZEXTLOAD = 64, |
| G_INDEXED_LOAD = 65, |
| G_INDEXED_SEXTLOAD = 66, |
| G_INDEXED_ZEXTLOAD = 67, |
| G_STORE = 68, |
| G_INDEXED_STORE = 69, |
| G_ATOMIC_CMPXCHG_WITH_SUCCESS = 70, |
| G_ATOMIC_CMPXCHG = 71, |
| G_ATOMICRMW_XCHG = 72, |
| G_ATOMICRMW_ADD = 73, |
| G_ATOMICRMW_SUB = 74, |
| G_ATOMICRMW_AND = 75, |
| G_ATOMICRMW_NAND = 76, |
| G_ATOMICRMW_OR = 77, |
| G_ATOMICRMW_XOR = 78, |
| G_ATOMICRMW_MAX = 79, |
| G_ATOMICRMW_MIN = 80, |
| G_ATOMICRMW_UMAX = 81, |
| G_ATOMICRMW_UMIN = 82, |
| G_ATOMICRMW_FADD = 83, |
| G_ATOMICRMW_FSUB = 84, |
| G_FENCE = 85, |
| G_BRCOND = 86, |
| G_BRINDIRECT = 87, |
| G_INTRINSIC = 88, |
| G_INTRINSIC_W_SIDE_EFFECTS = 89, |
| G_ANYEXT = 90, |
| G_TRUNC = 91, |
| G_CONSTANT = 92, |
| G_FCONSTANT = 93, |
| G_VASTART = 94, |
| G_VAARG = 95, |
| G_SEXT = 96, |
| G_SEXT_INREG = 97, |
| G_ZEXT = 98, |
| G_SHL = 99, |
| G_LSHR = 100, |
| G_ASHR = 101, |
| G_ICMP = 102, |
| G_FCMP = 103, |
| G_SELECT = 104, |
| G_UADDO = 105, |
| G_UADDE = 106, |
| G_USUBO = 107, |
| G_USUBE = 108, |
| G_SADDO = 109, |
| G_SADDE = 110, |
| G_SSUBO = 111, |
| G_SSUBE = 112, |
| G_UMULO = 113, |
| G_SMULO = 114, |
| G_UMULH = 115, |
| G_SMULH = 116, |
| G_FADD = 117, |
| G_FSUB = 118, |
| G_FMUL = 119, |
| G_FMA = 120, |
| G_FMAD = 121, |
| G_FDIV = 122, |
| G_FREM = 123, |
| G_FPOW = 124, |
| G_FEXP = 125, |
| G_FEXP2 = 126, |
| G_FLOG = 127, |
| G_FLOG2 = 128, |
| G_FLOG10 = 129, |
| G_FNEG = 130, |
| G_FPEXT = 131, |
| G_FPTRUNC = 132, |
| G_FPTOSI = 133, |
| G_FPTOUI = 134, |
| G_SITOFP = 135, |
| G_UITOFP = 136, |
| G_FABS = 137, |
| G_FCOPYSIGN = 138, |
| G_FCANONICALIZE = 139, |
| G_FMINNUM = 140, |
| G_FMAXNUM = 141, |
| G_FMINNUM_IEEE = 142, |
| G_FMAXNUM_IEEE = 143, |
| G_FMINIMUM = 144, |
| G_FMAXIMUM = 145, |
| G_PTR_ADD = 146, |
| G_PTR_MASK = 147, |
| G_SMIN = 148, |
| G_SMAX = 149, |
| G_UMIN = 150, |
| G_UMAX = 151, |
| G_BR = 152, |
| G_BRJT = 153, |
| G_INSERT_VECTOR_ELT = 154, |
| G_EXTRACT_VECTOR_ELT = 155, |
| G_SHUFFLE_VECTOR = 156, |
| G_CTTZ = 157, |
| G_CTTZ_ZERO_UNDEF = 158, |
| G_CTLZ = 159, |
| G_CTLZ_ZERO_UNDEF = 160, |
| G_CTPOP = 161, |
| G_BSWAP = 162, |
| G_BITREVERSE = 163, |
| G_FCEIL = 164, |
| G_FCOS = 165, |
| G_FSIN = 166, |
| G_FSQRT = 167, |
| G_FFLOOR = 168, |
| G_FRINT = 169, |
| G_FNEARBYINT = 170, |
| G_ADDRSPACE_CAST = 171, |
| G_BLOCK_ADDR = 172, |
| G_JUMP_TABLE = 173, |
| G_DYN_STACKALLOC = 174, |
| G_READ_REGISTER = 175, |
| G_WRITE_REGISTER = 176, |
| ABSMacro = 177, |
| ADJCALLSTACKDOWN = 178, |
| ADJCALLSTACKUP = 179, |
| AND_V_D_PSEUDO = 180, |
| AND_V_H_PSEUDO = 181, |
| AND_V_W_PSEUDO = 182, |
| ATOMIC_CMP_SWAP_I16 = 183, |
| ATOMIC_CMP_SWAP_I16_POSTRA = 184, |
| ATOMIC_CMP_SWAP_I32 = 185, |
| ATOMIC_CMP_SWAP_I32_POSTRA = 186, |
| ATOMIC_CMP_SWAP_I64 = 187, |
| ATOMIC_CMP_SWAP_I64_POSTRA = 188, |
| ATOMIC_CMP_SWAP_I8 = 189, |
| ATOMIC_CMP_SWAP_I8_POSTRA = 190, |
| ATOMIC_LOAD_ADD_I16 = 191, |
| ATOMIC_LOAD_ADD_I16_POSTRA = 192, |
| ATOMIC_LOAD_ADD_I32 = 193, |
| ATOMIC_LOAD_ADD_I32_POSTRA = 194, |
| ATOMIC_LOAD_ADD_I64 = 195, |
| ATOMIC_LOAD_ADD_I64_POSTRA = 196, |
| ATOMIC_LOAD_ADD_I8 = 197, |
| ATOMIC_LOAD_ADD_I8_POSTRA = 198, |
| ATOMIC_LOAD_AND_I16 = 199, |
| ATOMIC_LOAD_AND_I16_POSTRA = 200, |
| ATOMIC_LOAD_AND_I32 = 201, |
| ATOMIC_LOAD_AND_I32_POSTRA = 202, |
| ATOMIC_LOAD_AND_I64 = 203, |
| ATOMIC_LOAD_AND_I64_POSTRA = 204, |
| ATOMIC_LOAD_AND_I8 = 205, |
| ATOMIC_LOAD_AND_I8_POSTRA = 206, |
| ATOMIC_LOAD_MAX_I16 = 207, |
| ATOMIC_LOAD_MAX_I16_POSTRA = 208, |
| ATOMIC_LOAD_MAX_I32 = 209, |
| ATOMIC_LOAD_MAX_I32_POSTRA = 210, |
| ATOMIC_LOAD_MAX_I64 = 211, |
| ATOMIC_LOAD_MAX_I64_POSTRA = 212, |
| ATOMIC_LOAD_MAX_I8 = 213, |
| ATOMIC_LOAD_MAX_I8_POSTRA = 214, |
| ATOMIC_LOAD_MIN_I16 = 215, |
| ATOMIC_LOAD_MIN_I16_POSTRA = 216, |
| ATOMIC_LOAD_MIN_I32 = 217, |
| ATOMIC_LOAD_MIN_I32_POSTRA = 218, |
| ATOMIC_LOAD_MIN_I64 = 219, |
| ATOMIC_LOAD_MIN_I64_POSTRA = 220, |
| ATOMIC_LOAD_MIN_I8 = 221, |
| ATOMIC_LOAD_MIN_I8_POSTRA = 222, |
| ATOMIC_LOAD_NAND_I16 = 223, |
| ATOMIC_LOAD_NAND_I16_POSTRA = 224, |
| ATOMIC_LOAD_NAND_I32 = 225, |
| ATOMIC_LOAD_NAND_I32_POSTRA = 226, |
| ATOMIC_LOAD_NAND_I64 = 227, |
| ATOMIC_LOAD_NAND_I64_POSTRA = 228, |
| ATOMIC_LOAD_NAND_I8 = 229, |
| ATOMIC_LOAD_NAND_I8_POSTRA = 230, |
| ATOMIC_LOAD_OR_I16 = 231, |
| ATOMIC_LOAD_OR_I16_POSTRA = 232, |
| ATOMIC_LOAD_OR_I32 = 233, |
| ATOMIC_LOAD_OR_I32_POSTRA = 234, |
| ATOMIC_LOAD_OR_I64 = 235, |
| ATOMIC_LOAD_OR_I64_POSTRA = 236, |
| ATOMIC_LOAD_OR_I8 = 237, |
| ATOMIC_LOAD_OR_I8_POSTRA = 238, |
| ATOMIC_LOAD_SUB_I16 = 239, |
| ATOMIC_LOAD_SUB_I16_POSTRA = 240, |
| ATOMIC_LOAD_SUB_I32 = 241, |
| ATOMIC_LOAD_SUB_I32_POSTRA = 242, |
| ATOMIC_LOAD_SUB_I64 = 243, |
| ATOMIC_LOAD_SUB_I64_POSTRA = 244, |
| ATOMIC_LOAD_SUB_I8 = 245, |
| ATOMIC_LOAD_SUB_I8_POSTRA = 246, |
| ATOMIC_LOAD_UMAX_I16 = 247, |
| ATOMIC_LOAD_UMAX_I16_POSTRA = 248, |
| ATOMIC_LOAD_UMAX_I32 = 249, |
| ATOMIC_LOAD_UMAX_I32_POSTRA = 250, |
| ATOMIC_LOAD_UMAX_I64 = 251, |
| ATOMIC_LOAD_UMAX_I64_POSTRA = 252, |
| ATOMIC_LOAD_UMAX_I8 = 253, |
| ATOMIC_LOAD_UMAX_I8_POSTRA = 254, |
| ATOMIC_LOAD_UMIN_I16 = 255, |
| ATOMIC_LOAD_UMIN_I16_POSTRA = 256, |
| ATOMIC_LOAD_UMIN_I32 = 257, |
| ATOMIC_LOAD_UMIN_I32_POSTRA = 258, |
| ATOMIC_LOAD_UMIN_I64 = 259, |
| ATOMIC_LOAD_UMIN_I64_POSTRA = 260, |
| ATOMIC_LOAD_UMIN_I8 = 261, |
| ATOMIC_LOAD_UMIN_I8_POSTRA = 262, |
| ATOMIC_LOAD_XOR_I16 = 263, |
| ATOMIC_LOAD_XOR_I16_POSTRA = 264, |
| ATOMIC_LOAD_XOR_I32 = 265, |
| ATOMIC_LOAD_XOR_I32_POSTRA = 266, |
| ATOMIC_LOAD_XOR_I64 = 267, |
| ATOMIC_LOAD_XOR_I64_POSTRA = 268, |
| ATOMIC_LOAD_XOR_I8 = 269, |
| ATOMIC_LOAD_XOR_I8_POSTRA = 270, |
| ATOMIC_SWAP_I16 = 271, |
| ATOMIC_SWAP_I16_POSTRA = 272, |
| ATOMIC_SWAP_I32 = 273, |
| ATOMIC_SWAP_I32_POSTRA = 274, |
| ATOMIC_SWAP_I64 = 275, |
| ATOMIC_SWAP_I64_POSTRA = 276, |
| ATOMIC_SWAP_I8 = 277, |
| ATOMIC_SWAP_I8_POSTRA = 278, |
| B = 279, |
| BAL_BR = 280, |
| BAL_BR_MM = 281, |
| BEQLImmMacro = 282, |
| BGE = 283, |
| BGEImmMacro = 284, |
| BGEL = 285, |
| BGELImmMacro = 286, |
| BGEU = 287, |
| BGEUImmMacro = 288, |
| BGEUL = 289, |
| BGEULImmMacro = 290, |
| BGT = 291, |
| BGTImmMacro = 292, |
| BGTL = 293, |
| BGTLImmMacro = 294, |
| BGTU = 295, |
| BGTUImmMacro = 296, |
| BGTUL = 297, |
| BGTULImmMacro = 298, |
| BLE = 299, |
| BLEImmMacro = 300, |
| BLEL = 301, |
| BLELImmMacro = 302, |
| BLEU = 303, |
| BLEUImmMacro = 304, |
| BLEUL = 305, |
| BLEULImmMacro = 306, |
| BLT = 307, |
| BLTImmMacro = 308, |
| BLTL = 309, |
| BLTLImmMacro = 310, |
| BLTU = 311, |
| BLTUImmMacro = 312, |
| BLTUL = 313, |
| BLTULImmMacro = 314, |
| BNELImmMacro = 315, |
| BPOSGE32_PSEUDO = 316, |
| BSEL_D_PSEUDO = 317, |
| BSEL_FD_PSEUDO = 318, |
| BSEL_FW_PSEUDO = 319, |
| BSEL_H_PSEUDO = 320, |
| BSEL_W_PSEUDO = 321, |
| B_MM = 322, |
| B_MMR6_Pseudo = 323, |
| B_MM_Pseudo = 324, |
| BeqImm = 325, |
| BneImm = 326, |
| BteqzT8CmpX16 = 327, |
| BteqzT8CmpiX16 = 328, |
| BteqzT8SltX16 = 329, |
| BteqzT8SltiX16 = 330, |
| BteqzT8SltiuX16 = 331, |
| BteqzT8SltuX16 = 332, |
| BtnezT8CmpX16 = 333, |
| BtnezT8CmpiX16 = 334, |
| BtnezT8SltX16 = 335, |
| BtnezT8SltiX16 = 336, |
| BtnezT8SltiuX16 = 337, |
| BtnezT8SltuX16 = 338, |
| BuildPairF64 = 339, |
| BuildPairF64_64 = 340, |
| CFTC1 = 341, |
| CONSTPOOL_ENTRY = 342, |
| COPY_FD_PSEUDO = 343, |
| COPY_FW_PSEUDO = 344, |
| CTTC1 = 345, |
| Constant32 = 346, |
| DMULImmMacro = 347, |
| DMULMacro = 348, |
| DMULOMacro = 349, |
| DMULOUMacro = 350, |
| DROL = 351, |
| DROLImm = 352, |
| DROR = 353, |
| DRORImm = 354, |
| DSDivIMacro = 355, |
| DSDivMacro = 356, |
| DSRemIMacro = 357, |
| DSRemMacro = 358, |
| DUDivIMacro = 359, |
| DUDivMacro = 360, |
| DURemIMacro = 361, |
| DURemMacro = 362, |
| ERet = 363, |
| ExtractElementF64 = 364, |
| ExtractElementF64_64 = 365, |
| FABS_D = 366, |
| FABS_W = 367, |
| FEXP2_D_1_PSEUDO = 368, |
| FEXP2_W_1_PSEUDO = 369, |
| FILL_FD_PSEUDO = 370, |
| FILL_FW_PSEUDO = 371, |
| GotPrologue16 = 372, |
| INSERT_B_VIDX64_PSEUDO = 373, |
| INSERT_B_VIDX_PSEUDO = 374, |
| INSERT_D_VIDX64_PSEUDO = 375, |
| INSERT_D_VIDX_PSEUDO = 376, |
| INSERT_FD_PSEUDO = 377, |
| INSERT_FD_VIDX64_PSEUDO = 378, |
| INSERT_FD_VIDX_PSEUDO = 379, |
| INSERT_FW_PSEUDO = 380, |
| INSERT_FW_VIDX64_PSEUDO = 381, |
| INSERT_FW_VIDX_PSEUDO = 382, |
| INSERT_H_VIDX64_PSEUDO = 383, |
| INSERT_H_VIDX_PSEUDO = 384, |
| INSERT_W_VIDX64_PSEUDO = 385, |
| INSERT_W_VIDX_PSEUDO = 386, |
| JALR64Pseudo = 387, |
| JALRHB64Pseudo = 388, |
| JALRHBPseudo = 389, |
| JALRPseudo = 390, |
| JAL_MMR6 = 391, |
| JalOneReg = 392, |
| JalTwoReg = 393, |
| LDMacro = 394, |
| LD_F16 = 395, |
| LOAD_ACC128 = 396, |
| LOAD_ACC64 = 397, |
| LOAD_ACC64DSP = 398, |
| LOAD_CCOND_DSP = 399, |
| LONG_BRANCH_ADDiu = 400, |
| LONG_BRANCH_ADDiu2Op = 401, |
| LONG_BRANCH_DADDiu = 402, |
| LONG_BRANCH_DADDiu2Op = 403, |
| LONG_BRANCH_LUi = 404, |
| LONG_BRANCH_LUi2Op = 405, |
| LONG_BRANCH_LUi2Op_64 = 406, |
| LWM_MM = 407, |
| LoadAddrImm32 = 408, |
| LoadAddrImm64 = 409, |
| LoadAddrReg32 = 410, |
| LoadAddrReg64 = 411, |
| LoadImm32 = 412, |
| LoadImm64 = 413, |
| LoadImmDoubleFGR = 414, |
| LoadImmDoubleFGR_32 = 415, |
| LoadImmDoubleGPR = 416, |
| LoadImmSingleFGR = 417, |
| LoadImmSingleGPR = 418, |
| LwConstant32 = 419, |
| MFTACX = 420, |
| MFTC0 = 421, |
| MFTC1 = 422, |
| MFTDSP = 423, |
| MFTGPR = 424, |
| MFTHC1 = 425, |
| MFTHI = 426, |
| MFTLO = 427, |
| MIPSeh_return32 = 428, |
| MIPSeh_return64 = 429, |
| MSA_FP_EXTEND_D_PSEUDO = 430, |
| MSA_FP_EXTEND_W_PSEUDO = 431, |
| MSA_FP_ROUND_D_PSEUDO = 432, |
| MSA_FP_ROUND_W_PSEUDO = 433, |
| MTTACX = 434, |
| MTTC0 = 435, |
| MTTC1 = 436, |
| MTTDSP = 437, |
| MTTGPR = 438, |
| MTTHC1 = 439, |
| MTTHI = 440, |
| MTTLO = 441, |
| MULImmMacro = 442, |
| MULOMacro = 443, |
| MULOUMacro = 444, |
| MultRxRy16 = 445, |
| MultRxRyRz16 = 446, |
| MultuRxRy16 = 447, |
| MultuRxRyRz16 = 448, |
| NOP = 449, |
| NORImm = 450, |
| NORImm64 = 451, |
| NOR_V_D_PSEUDO = 452, |
| NOR_V_H_PSEUDO = 453, |
| NOR_V_W_PSEUDO = 454, |
| OR_V_D_PSEUDO = 455, |
| OR_V_H_PSEUDO = 456, |
| OR_V_W_PSEUDO = 457, |
| PseudoCMPU_EQ_QB = 458, |
| PseudoCMPU_LE_QB = 459, |
| PseudoCMPU_LT_QB = 460, |
| PseudoCMP_EQ_PH = 461, |
| PseudoCMP_LE_PH = 462, |
| PseudoCMP_LT_PH = 463, |
| PseudoCVT_D32_W = 464, |
| PseudoCVT_D64_L = 465, |
| PseudoCVT_D64_W = 466, |
| PseudoCVT_S_L = 467, |
| PseudoCVT_S_W = 468, |
| PseudoDMULT = 469, |
| PseudoDMULTu = 470, |
| PseudoDSDIV = 471, |
| PseudoDUDIV = 472, |
| PseudoD_SELECT_I = 473, |
| PseudoD_SELECT_I64 = 474, |
| PseudoIndirectBranch = 475, |
| PseudoIndirectBranch64 = 476, |
| PseudoIndirectBranch64R6 = 477, |
| PseudoIndirectBranchR6 = 478, |
| PseudoIndirectBranch_MM = 479, |
| PseudoIndirectBranch_MMR6 = 480, |
| PseudoIndirectHazardBranch = 481, |
| PseudoIndirectHazardBranch64 = 482, |
| PseudoIndrectHazardBranch64R6 = 483, |
| PseudoIndrectHazardBranchR6 = 484, |
| PseudoMADD = 485, |
| PseudoMADDU = 486, |
| PseudoMADDU_MM = 487, |
| PseudoMADD_MM = 488, |
| PseudoMFHI = 489, |
| PseudoMFHI64 = 490, |
| PseudoMFHI_MM = 491, |
| PseudoMFLO = 492, |
| PseudoMFLO64 = 493, |
| PseudoMFLO_MM = 494, |
| PseudoMSUB = 495, |
| PseudoMSUBU = 496, |
| PseudoMSUBU_MM = 497, |
| PseudoMSUB_MM = 498, |
| PseudoMTLOHI = 499, |
| PseudoMTLOHI64 = 500, |
| PseudoMTLOHI_DSP = 501, |
| PseudoMTLOHI_MM = 502, |
| PseudoMULT = 503, |
| PseudoMULT_MM = 504, |
| PseudoMULTu = 505, |
| PseudoMULTu_MM = 506, |
| PseudoPICK_PH = 507, |
| PseudoPICK_QB = 508, |
| PseudoReturn = 509, |
| PseudoReturn64 = 510, |
| PseudoSDIV = 511, |
| PseudoSELECTFP_F_D32 = 512, |
| PseudoSELECTFP_F_D64 = 513, |
| PseudoSELECTFP_F_I = 514, |
| PseudoSELECTFP_F_I64 = 515, |
| PseudoSELECTFP_F_S = 516, |
| PseudoSELECTFP_T_D32 = 517, |
| PseudoSELECTFP_T_D64 = 518, |
| PseudoSELECTFP_T_I = 519, |
| PseudoSELECTFP_T_I64 = 520, |
| PseudoSELECTFP_T_S = 521, |
| PseudoSELECT_D32 = 522, |
| PseudoSELECT_D64 = 523, |
| PseudoSELECT_I = 524, |
| PseudoSELECT_I64 = 525, |
| PseudoSELECT_S = 526, |
| PseudoTRUNC_W_D = 527, |
| PseudoTRUNC_W_D32 = 528, |
| PseudoTRUNC_W_S = 529, |
| PseudoUDIV = 530, |
| ROL = 531, |
| ROLImm = 532, |
| ROR = 533, |
| RORImm = 534, |
| RetRA = 535, |
| RetRA16 = 536, |
| SDC1_M1 = 537, |
| SDIV_MM_Pseudo = 538, |
| SDMacro = 539, |
| SDivIMacro = 540, |
| SDivMacro = 541, |
| SEQIMacro = 542, |
| SEQMacro = 543, |
| SGE = 544, |
| SGEImm = 545, |
| SGEImm64 = 546, |
| SGEU = 547, |
| SGEUImm = 548, |
| SGEUImm64 = 549, |
| SGTImm = 550, |
| SGTImm64 = 551, |
| SGTUImm = 552, |
| SGTUImm64 = 553, |
| SLTImm64 = 554, |
| SLTUImm64 = 555, |
| SNZ_B_PSEUDO = 556, |
| SNZ_D_PSEUDO = 557, |
| SNZ_H_PSEUDO = 558, |
| SNZ_V_PSEUDO = 559, |
| SNZ_W_PSEUDO = 560, |
| SRemIMacro = 561, |
| SRemMacro = 562, |
| STORE_ACC128 = 563, |
| STORE_ACC64 = 564, |
| STORE_ACC64DSP = 565, |
| STORE_CCOND_DSP = 566, |
| ST_F16 = 567, |
| SWM_MM = 568, |
| SZ_B_PSEUDO = 569, |
| SZ_D_PSEUDO = 570, |
| SZ_H_PSEUDO = 571, |
| SZ_V_PSEUDO = 572, |
| SZ_W_PSEUDO = 573, |
| SaaAddr = 574, |
| SaadAddr = 575, |
| SelBeqZ = 576, |
| SelBneZ = 577, |
| SelTBteqZCmp = 578, |
| SelTBteqZCmpi = 579, |
| SelTBteqZSlt = 580, |
| SelTBteqZSlti = 581, |
| SelTBteqZSltiu = 582, |
| SelTBteqZSltu = 583, |
| SelTBtneZCmp = 584, |
| SelTBtneZCmpi = 585, |
| SelTBtneZSlt = 586, |
| SelTBtneZSlti = 587, |
| SelTBtneZSltiu = 588, |
| SelTBtneZSltu = 589, |
| SltCCRxRy16 = 590, |
| SltiCCRxImmX16 = 591, |
| SltiuCCRxImmX16 = 592, |
| SltuCCRxRy16 = 593, |
| SltuRxRyRz16 = 594, |
| TAILCALL = 595, |
| TAILCALL64R6REG = 596, |
| TAILCALLHB64R6REG = 597, |
| TAILCALLHBR6REG = 598, |
| TAILCALLR6REG = 599, |
| TAILCALLREG = 600, |
| TAILCALLREG64 = 601, |
| TAILCALLREGHB = 602, |
| TAILCALLREGHB64 = 603, |
| TAILCALLREG_MM = 604, |
| TAILCALLREG_MMR6 = 605, |
| TAILCALL_MM = 606, |
| TAILCALL_MMR6 = 607, |
| TRAP = 608, |
| TRAP_MM = 609, |
| UDIV_MM_Pseudo = 610, |
| UDivIMacro = 611, |
| UDivMacro = 612, |
| URemIMacro = 613, |
| URemMacro = 614, |
| Ulh = 615, |
| Ulhu = 616, |
| Ulw = 617, |
| Ush = 618, |
| Usw = 619, |
| XOR_V_D_PSEUDO = 620, |
| XOR_V_H_PSEUDO = 621, |
| XOR_V_W_PSEUDO = 622, |
| ABSQ_S_PH = 623, |
| ABSQ_S_PH_MM = 624, |
| ABSQ_S_QB = 625, |
| ABSQ_S_QB_MMR2 = 626, |
| ABSQ_S_W = 627, |
| ABSQ_S_W_MM = 628, |
| ADD = 629, |
| ADDIUPC = 630, |
| ADDIUPC_MM = 631, |
| ADDIUPC_MMR6 = 632, |
| ADDIUR1SP_MM = 633, |
| ADDIUR2_MM = 634, |
| ADDIUS5_MM = 635, |
| ADDIUSP_MM = 636, |
| ADDIU_MMR6 = 637, |
| ADDQH_PH = 638, |
| ADDQH_PH_MMR2 = 639, |
| ADDQH_R_PH = 640, |
| ADDQH_R_PH_MMR2 = 641, |
| ADDQH_R_W = 642, |
| ADDQH_R_W_MMR2 = 643, |
| ADDQH_W = 644, |
| ADDQH_W_MMR2 = 645, |
| ADDQ_PH = 646, |
| ADDQ_PH_MM = 647, |
| ADDQ_S_PH = 648, |
| ADDQ_S_PH_MM = 649, |
| ADDQ_S_W = 650, |
| ADDQ_S_W_MM = 651, |
| ADDSC = 652, |
| ADDSC_MM = 653, |
| ADDS_A_B = 654, |
| ADDS_A_D = 655, |
| ADDS_A_H = 656, |
| ADDS_A_W = 657, |
| ADDS_S_B = 658, |
| ADDS_S_D = 659, |
| ADDS_S_H = 660, |
| ADDS_S_W = 661, |
| ADDS_U_B = 662, |
| ADDS_U_D = 663, |
| ADDS_U_H = 664, |
| ADDS_U_W = 665, |
| ADDU16_MM = 666, |
| ADDU16_MMR6 = 667, |
| ADDUH_QB = 668, |
| ADDUH_QB_MMR2 = 669, |
| ADDUH_R_QB = 670, |
| ADDUH_R_QB_MMR2 = 671, |
| ADDU_MMR6 = 672, |
| ADDU_PH = 673, |
| ADDU_PH_MMR2 = 674, |
| ADDU_QB = 675, |
| ADDU_QB_MM = 676, |
| ADDU_S_PH = 677, |
| ADDU_S_PH_MMR2 = 678, |
| ADDU_S_QB = 679, |
| ADDU_S_QB_MM = 680, |
| ADDVI_B = 681, |
| ADDVI_D = 682, |
| ADDVI_H = 683, |
| ADDVI_W = 684, |
| ADDV_B = 685, |
| ADDV_D = 686, |
| ADDV_H = 687, |
| ADDV_W = 688, |
| ADDWC = 689, |
| ADDWC_MM = 690, |
| ADD_A_B = 691, |
| ADD_A_D = 692, |
| ADD_A_H = 693, |
| ADD_A_W = 694, |
| ADD_MM = 695, |
| ADD_MMR6 = 696, |
| ADDi = 697, |
| ADDi_MM = 698, |
| ADDiu = 699, |
| ADDiu_MM = 700, |
| ADDu = 701, |
| ADDu_MM = 702, |
| ALIGN = 703, |
| ALIGN_MMR6 = 704, |
| ALUIPC = 705, |
| ALUIPC_MMR6 = 706, |
| AND = 707, |
| AND16_MM = 708, |
| AND16_MMR6 = 709, |
| AND64 = 710, |
| ANDI16_MM = 711, |
| ANDI16_MMR6 = 712, |
| ANDI_B = 713, |
| ANDI_MMR6 = 714, |
| AND_MM = 715, |
| AND_MMR6 = 716, |
| AND_V = 717, |
| ANDi = 718, |
| ANDi64 = 719, |
| ANDi_MM = 720, |
| APPEND = 721, |
| APPEND_MMR2 = 722, |
| ASUB_S_B = 723, |
| ASUB_S_D = 724, |
| ASUB_S_H = 725, |
| ASUB_S_W = 726, |
| ASUB_U_B = 727, |
| ASUB_U_D = 728, |
| ASUB_U_H = 729, |
| ASUB_U_W = 730, |
| AUI = 731, |
| AUIPC = 732, |
| AUIPC_MMR6 = 733, |
| AUI_MMR6 = 734, |
| AVER_S_B = 735, |
| AVER_S_D = 736, |
| AVER_S_H = 737, |
| AVER_S_W = 738, |
| AVER_U_B = 739, |
| AVER_U_D = 740, |
| AVER_U_H = 741, |
| AVER_U_W = 742, |
| AVE_S_B = 743, |
| AVE_S_D = 744, |
| AVE_S_H = 745, |
| AVE_S_W = 746, |
| AVE_U_B = 747, |
| AVE_U_D = 748, |
| AVE_U_H = 749, |
| AVE_U_W = 750, |
| AddiuRxImmX16 = 751, |
| AddiuRxPcImmX16 = 752, |
| AddiuRxRxImm16 = 753, |
| AddiuRxRxImmX16 = 754, |
| AddiuRxRyOffMemX16 = 755, |
| AddiuSpImm16 = 756, |
| AddiuSpImmX16 = 757, |
| AdduRxRyRz16 = 758, |
| AndRxRxRy16 = 759, |
| B16_MM = 760, |
| BADDu = 761, |
| BAL = 762, |
| BALC = 763, |
| BALC_MMR6 = 764, |
| BALIGN = 765, |
| BALIGN_MMR2 = 766, |
| BBIT0 = 767, |
| BBIT032 = 768, |
| BBIT1 = 769, |
| BBIT132 = 770, |
| BC = 771, |
| BC16_MMR6 = 772, |
| BC1EQZ = 773, |
| BC1EQZC_MMR6 = 774, |
| BC1F = 775, |
| BC1FL = 776, |
| BC1F_MM = 777, |
| BC1NEZ = 778, |
| BC1NEZC_MMR6 = 779, |
| BC1T = 780, |
| BC1TL = 781, |
| BC1T_MM = 782, |
| BC2EQZ = 783, |
| BC2EQZC_MMR6 = 784, |
| BC2NEZ = 785, |
| BC2NEZC_MMR6 = 786, |
| BCLRI_B = 787, |
| BCLRI_D = 788, |
| BCLRI_H = 789, |
| BCLRI_W = 790, |
| BCLR_B = 791, |
| BCLR_D = 792, |
| BCLR_H = 793, |
| BCLR_W = 794, |
| BC_MMR6 = 795, |
| BEQ = 796, |
| BEQ64 = 797, |
| BEQC = 798, |
| BEQC64 = 799, |
| BEQC_MMR6 = 800, |
| BEQL = 801, |
| BEQZ16_MM = 802, |
| BEQZALC = 803, |
| BEQZALC_MMR6 = 804, |
| BEQZC = 805, |
| BEQZC16_MMR6 = 806, |
| BEQZC64 = 807, |
| BEQZC_MM = 808, |
| BEQZC_MMR6 = 809, |
| BEQ_MM = 810, |
| BGEC = 811, |
| BGEC64 = 812, |
| BGEC_MMR6 = 813, |
| BGEUC = 814, |
| BGEUC64 = 815, |
| BGEUC_MMR6 = 816, |
| BGEZ = 817, |
| BGEZ64 = 818, |
| BGEZAL = 819, |
| BGEZALC = 820, |
| BGEZALC_MMR6 = 821, |
| BGEZALL = 822, |
| BGEZALS_MM = 823, |
| BGEZAL_MM = 824, |
| BGEZC = 825, |
| BGEZC64 = 826, |
| BGEZC_MMR6 = 827, |
| BGEZL = 828, |
| BGEZ_MM = 829, |
| BGTZ = 830, |
| BGTZ64 = 831, |
| BGTZALC = 832, |
| BGTZALC_MMR6 = 833, |
| BGTZC = 834, |
| BGTZC64 = 835, |
| BGTZC_MMR6 = 836, |
| BGTZL = 837, |
| BGTZ_MM = 838, |
| BINSLI_B = 839, |
| BINSLI_D = 840, |
| BINSLI_H = 841, |
| BINSLI_W = 842, |
| BINSL_B = 843, |
| BINSL_D = 844, |
| BINSL_H = 845, |
| BINSL_W = 846, |
| BINSRI_B = 847, |
| BINSRI_D = 848, |
| BINSRI_H = 849, |
| BINSRI_W = 850, |
| BINSR_B = 851, |
| BINSR_D = 852, |
| BINSR_H = 853, |
| BINSR_W = 854, |
| BITREV = 855, |
| BITREV_MM = 856, |
| BITSWAP = 857, |
| BITSWAP_MMR6 = 858, |
| BLEZ = 859, |
| BLEZ64 = 860, |
| BLEZALC = 861, |
| BLEZALC_MMR6 = 862, |
| BLEZC = 863, |
| BLEZC64 = 864, |
| BLEZC_MMR6 = 865, |
| BLEZL = 866, |
| BLEZ_MM = 867, |
| BLTC = 868, |
| BLTC64 = 869, |
| BLTC_MMR6 = 870, |
| BLTUC = 871, |
| BLTUC64 = 872, |
| BLTUC_MMR6 = 873, |
| BLTZ = 874, |
| BLTZ64 = 875, |
| BLTZAL = 876, |
| BLTZALC = 877, |
| BLTZALC_MMR6 = 878, |
| BLTZALL = 879, |
| BLTZALS_MM = 880, |
| BLTZAL_MM = 881, |
| BLTZC = 882, |
| BLTZC64 = 883, |
| BLTZC_MMR6 = 884, |
| BLTZL = 885, |
| BLTZ_MM = 886, |
| BMNZI_B = 887, |
| BMNZ_V = 888, |
| BMZI_B = 889, |
| BMZ_V = 890, |
| BNE = 891, |
| BNE64 = 892, |
| BNEC = 893, |
| BNEC64 = 894, |
| BNEC_MMR6 = 895, |
| BNEGI_B = 896, |
| BNEGI_D = 897, |
| BNEGI_H = 898, |
| BNEGI_W = 899, |
| BNEG_B = 900, |
| BNEG_D = 901, |
| BNEG_H = 902, |
| BNEG_W = 903, |
| BNEL = 904, |
| BNEZ16_MM = 905, |
| BNEZALC = 906, |
| BNEZALC_MMR6 = 907, |
| BNEZC = 908, |
| BNEZC16_MMR6 = 909, |
| BNEZC64 = 910, |
| BNEZC_MM = 911, |
| BNEZC_MMR6 = 912, |
| BNE_MM = 913, |
| BNVC = 914, |
| BNVC_MMR6 = 915, |
| BNZ_B = 916, |
| BNZ_D = 917, |
| BNZ_H = 918, |
| BNZ_V = 919, |
| BNZ_W = 920, |
| BOVC = 921, |
| BOVC_MMR6 = 922, |
| BPOSGE32 = 923, |
| BPOSGE32C_MMR3 = 924, |
| BPOSGE32_MM = 925, |
| BREAK = 926, |
| BREAK16_MM = 927, |
| BREAK16_MMR6 = 928, |
| BREAK_MM = 929, |
| BREAK_MMR6 = 930, |
| BSELI_B = 931, |
| BSEL_V = 932, |
| BSETI_B = 933, |
| BSETI_D = 934, |
| BSETI_H = 935, |
| BSETI_W = 936, |
| BSET_B = 937, |
| BSET_D = 938, |
| BSET_H = 939, |
| BSET_W = 940, |
| BZ_B = 941, |
| BZ_D = 942, |
| BZ_H = 943, |
| BZ_V = 944, |
| BZ_W = 945, |
| BeqzRxImm16 = 946, |
| BeqzRxImmX16 = 947, |
| Bimm16 = 948, |
| BimmX16 = 949, |
| BnezRxImm16 = 950, |
| BnezRxImmX16 = 951, |
| Break16 = 952, |
| Bteqz16 = 953, |
| BteqzX16 = 954, |
| Btnez16 = 955, |
| BtnezX16 = 956, |
| CACHE = 957, |
| CACHEE = 958, |
| CACHEE_MM = 959, |
| CACHE_MM = 960, |
| CACHE_MMR6 = 961, |
| CACHE_R6 = 962, |
| CEIL_L_D64 = 963, |
| CEIL_L_D_MMR6 = 964, |
| CEIL_L_S = 965, |
| CEIL_L_S_MMR6 = 966, |
| CEIL_W_D32 = 967, |
| CEIL_W_D64 = 968, |
| CEIL_W_D_MMR6 = 969, |
| CEIL_W_MM = 970, |
| CEIL_W_S = 971, |
| CEIL_W_S_MM = 972, |
| CEIL_W_S_MMR6 = 973, |
| CEQI_B = 974, |
| CEQI_D = 975, |
| CEQI_H = 976, |
| CEQI_W = 977, |
| CEQ_B = 978, |
| CEQ_D = 979, |
| CEQ_H = 980, |
| CEQ_W = 981, |
| CFC1 = 982, |
| CFC1_MM = 983, |
| CFC2_MM = 984, |
| CFCMSA = 985, |
| CINS = 986, |
| CINS32 = 987, |
| CINS64_32 = 988, |
| CINS_i32 = 989, |
| CLASS_D = 990, |
| CLASS_D_MMR6 = 991, |
| CLASS_S = 992, |
| CLASS_S_MMR6 = 993, |
| CLEI_S_B = 994, |
| CLEI_S_D = 995, |
| CLEI_S_H = 996, |
| CLEI_S_W = 997, |
| CLEI_U_B = 998, |
| CLEI_U_D = 999, |
| CLEI_U_H = 1000, |
| CLEI_U_W = 1001, |
| CLE_S_B = 1002, |
| CLE_S_D = 1003, |
| CLE_S_H = 1004, |
| CLE_S_W = 1005, |
| CLE_U_B = 1006, |
| CLE_U_D = 1007, |
| CLE_U_H = 1008, |
| CLE_U_W = 1009, |
| CLO = 1010, |
| CLO_MM = 1011, |
| CLO_MMR6 = 1012, |
| CLO_R6 = 1013, |
| CLTI_S_B = 1014, |
| CLTI_S_D = 1015, |
| CLTI_S_H = 1016, |
| CLTI_S_W = 1017, |
| CLTI_U_B = 1018, |
| CLTI_U_D = 1019, |
| CLTI_U_H = 1020, |
| CLTI_U_W = 1021, |
| CLT_S_B = 1022, |
| CLT_S_D = 1023, |
| CLT_S_H = 1024, |
| CLT_S_W = 1025, |
| CLT_U_B = 1026, |
| CLT_U_D = 1027, |
| CLT_U_H = 1028, |
| CLT_U_W = 1029, |
| CLZ = 1030, |
| CLZ_MM = 1031, |
| CLZ_MMR6 = 1032, |
| CLZ_R6 = 1033, |
| CMPGDU_EQ_QB = 1034, |
| CMPGDU_EQ_QB_MMR2 = 1035, |
| CMPGDU_LE_QB = 1036, |
| CMPGDU_LE_QB_MMR2 = 1037, |
| CMPGDU_LT_QB = 1038, |
| CMPGDU_LT_QB_MMR2 = 1039, |
| CMPGU_EQ_QB = 1040, |
| CMPGU_EQ_QB_MM = 1041, |
| CMPGU_LE_QB = 1042, |
| CMPGU_LE_QB_MM = 1043, |
| CMPGU_LT_QB = 1044, |
| CMPGU_LT_QB_MM = 1045, |
| CMPU_EQ_QB = 1046, |
| CMPU_EQ_QB_MM = 1047, |
| CMPU_LE_QB = 1048, |
| CMPU_LE_QB_MM = 1049, |
| CMPU_LT_QB = 1050, |
| CMPU_LT_QB_MM = 1051, |
| CMP_AF_D_MMR6 = 1052, |
| CMP_AF_S_MMR6 = 1053, |
| CMP_EQ_D = 1054, |
| CMP_EQ_D_MMR6 = 1055, |
| CMP_EQ_PH = 1056, |
| CMP_EQ_PH_MM = 1057, |
| CMP_EQ_S = 1058, |
| CMP_EQ_S_MMR6 = 1059, |
| CMP_F_D = 1060, |
| CMP_F_S = 1061, |
| CMP_LE_D = 1062, |
| CMP_LE_D_MMR6 = 1063, |
| CMP_LE_PH = 1064, |
| CMP_LE_PH_MM = 1065, |
| CMP_LE_S = 1066, |
| CMP_LE_S_MMR6 = 1067, |
| CMP_LT_D = 1068, |
| CMP_LT_D_MMR6 = 1069, |
| CMP_LT_PH = 1070, |
| CMP_LT_PH_MM = 1071, |
| CMP_LT_S = 1072, |
| CMP_LT_S_MMR6 = 1073, |
| CMP_SAF_D = 1074, |
| CMP_SAF_D_MMR6 = 1075, |
| CMP_SAF_S = 1076, |
| CMP_SAF_S_MMR6 = 1077, |
| CMP_SEQ_D = 1078, |
| CMP_SEQ_D_MMR6 = 1079, |
| CMP_SEQ_S = 1080, |
| CMP_SEQ_S_MMR6 = 1081, |
| CMP_SLE_D = 1082, |
| CMP_SLE_D_MMR6 = 1083, |
| CMP_SLE_S = 1084, |
| CMP_SLE_S_MMR6 = 1085, |
| CMP_SLT_D = 1086, |
| CMP_SLT_D_MMR6 = 1087, |
| CMP_SLT_S = 1088, |
| CMP_SLT_S_MMR6 = 1089, |
| CMP_SUEQ_D = 1090, |
| CMP_SUEQ_D_MMR6 = 1091, |
| CMP_SUEQ_S = 1092, |
| CMP_SUEQ_S_MMR6 = 1093, |
| CMP_SULE_D = 1094, |
| CMP_SULE_D_MMR6 = 1095, |
| CMP_SULE_S = 1096, |
| CMP_SULE_S_MMR6 = 1097, |
| CMP_SULT_D = 1098, |
| CMP_SULT_D_MMR6 = 1099, |
| CMP_SULT_S = 1100, |
| CMP_SULT_S_MMR6 = 1101, |
| CMP_SUN_D = 1102, |
| CMP_SUN_D_MMR6 = 1103, |
| CMP_SUN_S = 1104, |
| CMP_SUN_S_MMR6 = 1105, |
| CMP_UEQ_D = 1106, |
| CMP_UEQ_D_MMR6 = 1107, |
| CMP_UEQ_S = 1108, |
| CMP_UEQ_S_MMR6 = 1109, |
| CMP_ULE_D = 1110, |
| CMP_ULE_D_MMR6 = 1111, |
| CMP_ULE_S = 1112, |
| CMP_ULE_S_MMR6 = 1113, |
| CMP_ULT_D = 1114, |
| CMP_ULT_D_MMR6 = 1115, |
| CMP_ULT_S = 1116, |
| CMP_ULT_S_MMR6 = 1117, |
| CMP_UN_D = 1118, |
| CMP_UN_D_MMR6 = 1119, |
| CMP_UN_S = 1120, |
| CMP_UN_S_MMR6 = 1121, |
| COPY_S_B = 1122, |
| COPY_S_D = 1123, |
| COPY_S_H = 1124, |
| COPY_S_W = 1125, |
| COPY_U_B = 1126, |
| COPY_U_H = 1127, |
| COPY_U_W = 1128, |
| CRC32B = 1129, |
| CRC32CB = 1130, |
| CRC32CD = 1131, |
| CRC32CH = 1132, |
| CRC32CW = 1133, |
| CRC32D = 1134, |
| CRC32H = 1135, |
| CRC32W = 1136, |
| CTC1 = 1137, |
| CTC1_MM = 1138, |
| CTC2_MM = 1139, |
| CTCMSA = 1140, |
| CVT_D32_S = 1141, |
| CVT_D32_S_MM = 1142, |
| CVT_D32_W = 1143, |
| CVT_D32_W_MM = 1144, |
| CVT_D64_L = 1145, |
| CVT_D64_S = 1146, |
| CVT_D64_S_MM = 1147, |
| CVT_D64_W = 1148, |
| CVT_D64_W_MM = 1149, |
| CVT_D_L_MMR6 = 1150, |
| CVT_L_D64 = 1151, |
| CVT_L_D64_MM = 1152, |
| CVT_L_D_MMR6 = 1153, |
| CVT_L_S = 1154, |
| CVT_L_S_MM = 1155, |
| CVT_L_S_MMR6 = 1156, |
| CVT_PS_S64 = 1157, |
| CVT_S_D32 = 1158, |
| CVT_S_D32_MM = 1159, |
| CVT_S_D64 = 1160, |
| CVT_S_D64_MM = 1161, |
| CVT_S_L = 1162, |
| CVT_S_L_MMR6 = 1163, |
| CVT_S_PL64 = 1164, |
| CVT_S_PU64 = 1165, |
| CVT_S_W = 1166, |
| CVT_S_W_MM = 1167, |
| CVT_S_W_MMR6 = 1168, |
| CVT_W_D32 = 1169, |
| CVT_W_D32_MM = 1170, |
| CVT_W_D64 = 1171, |
| CVT_W_D64_MM = 1172, |
| CVT_W_S = 1173, |
| CVT_W_S_MM = 1174, |
| CVT_W_S_MMR6 = 1175, |
| C_EQ_D32 = 1176, |
| C_EQ_D32_MM = 1177, |
| C_EQ_D64 = 1178, |
| C_EQ_D64_MM = 1179, |
| C_EQ_S = 1180, |
| C_EQ_S_MM = 1181, |
| C_F_D32 = 1182, |
| C_F_D32_MM = 1183, |
| C_F_D64 = 1184, |
| C_F_D64_MM = 1185, |
| C_F_S = 1186, |
| C_F_S_MM = 1187, |
| C_LE_D32 = 1188, |
| C_LE_D32_MM = 1189, |
| C_LE_D64 = 1190, |
| C_LE_D64_MM = 1191, |
| C_LE_S = 1192, |
| C_LE_S_MM = 1193, |
| C_LT_D32 = 1194, |
| C_LT_D32_MM = 1195, |
| C_LT_D64 = 1196, |
| C_LT_D64_MM = 1197, |
| C_LT_S = 1198, |
| C_LT_S_MM = 1199, |
| C_NGE_D32 = 1200, |
| C_NGE_D32_MM = 1201, |
| C_NGE_D64 = 1202, |
| C_NGE_D64_MM = 1203, |
| C_NGE_S = 1204, |
| C_NGE_S_MM = 1205, |
| C_NGLE_D32 = 1206, |
| C_NGLE_D32_MM = 1207, |
| C_NGLE_D64 = 1208, |
| C_NGLE_D64_MM = 1209, |
| C_NGLE_S = 1210, |
| C_NGLE_S_MM = 1211, |
| C_NGL_D32 = 1212, |
| C_NGL_D32_MM = 1213, |
| C_NGL_D64 = 1214, |
| C_NGL_D64_MM = 1215, |
| C_NGL_S = 1216, |
| C_NGL_S_MM = 1217, |
| C_NGT_D32 = 1218, |
| C_NGT_D32_MM = 1219, |
| C_NGT_D64 = 1220, |
| C_NGT_D64_MM = 1221, |
| C_NGT_S = 1222, |
| C_NGT_S_MM = 1223, |
| C_OLE_D32 = 1224, |
| C_OLE_D32_MM = 1225, |
| C_OLE_D64 = 1226, |
| C_OLE_D64_MM = 1227, |
| C_OLE_S = 1228, |
| C_OLE_S_MM = 1229, |
| C_OLT_D32 = 1230, |
| C_OLT_D32_MM = 1231, |
| C_OLT_D64 = 1232, |
| C_OLT_D64_MM = 1233, |
| C_OLT_S = 1234, |
| C_OLT_S_MM = 1235, |
| C_SEQ_D32 = 1236, |
| C_SEQ_D32_MM = 1237, |
| C_SEQ_D64 = 1238, |
| C_SEQ_D64_MM = 1239, |
| C_SEQ_S = 1240, |
| C_SEQ_S_MM = 1241, |
| C_SF_D32 = 1242, |
| C_SF_D32_MM = 1243, |
| C_SF_D64 = 1244, |
| C_SF_D64_MM = 1245, |
| C_SF_S = 1246, |
| C_SF_S_MM = 1247, |
| C_UEQ_D32 = 1248, |
| C_UEQ_D32_MM = 1249, |
| C_UEQ_D64 = 1250, |
| C_UEQ_D64_MM = 1251, |
| C_UEQ_S = 1252, |
| C_UEQ_S_MM = 1253, |
| C_ULE_D32 = 1254, |
| C_ULE_D32_MM = 1255, |
| C_ULE_D64 = 1256, |
| C_ULE_D64_MM = 1257, |
| C_ULE_S = 1258, |
| C_ULE_S_MM = 1259, |
| C_ULT_D32 = 1260, |
| C_ULT_D32_MM = 1261, |
| C_ULT_D64 = 1262, |
| C_ULT_D64_MM = 1263, |
| C_ULT_S = 1264, |
| C_ULT_S_MM = 1265, |
| C_UN_D32 = 1266, |
| C_UN_D32_MM = 1267, |
| C_UN_D64 = 1268, |
| C_UN_D64_MM = 1269, |
| C_UN_S = 1270, |
| C_UN_S_MM = 1271, |
| CmpRxRy16 = 1272, |
| CmpiRxImm16 = 1273, |
| CmpiRxImmX16 = 1274, |
| DADD = 1275, |
| DADDi = 1276, |
| DADDiu = 1277, |
| DADDu = 1278, |
| DAHI = 1279, |
| DALIGN = 1280, |
| DATI = 1281, |
| DAUI = 1282, |
| DBITSWAP = 1283, |
| DCLO = 1284, |
| DCLO_R6 = 1285, |
| DCLZ = 1286, |
| DCLZ_R6 = 1287, |
| DDIV = 1288, |
| DDIVU = 1289, |
| DERET = 1290, |
| DERET_MM = 1291, |
| DERET_MMR6 = 1292, |
| DEXT = 1293, |
| DEXT64_32 = 1294, |
| DEXTM = 1295, |
| DEXTU = 1296, |
| DI = 1297, |
| DINS = 1298, |
| DINSM = 1299, |
| DINSU = 1300, |
| DIV = 1301, |
| DIVU = 1302, |
| DIVU_MMR6 = 1303, |
| DIV_MMR6 = 1304, |
| DIV_S_B = 1305, |
| DIV_S_D = 1306, |
| DIV_S_H = 1307, |
| DIV_S_W = 1308, |
| DIV_U_B = 1309, |
| DIV_U_D = 1310, |
| DIV_U_H = 1311, |
| DIV_U_W = 1312, |
| DI_MM = 1313, |
| DI_MMR6 = 1314, |
| DLSA = 1315, |
| DLSA_R6 = 1316, |
| DMFC0 = 1317, |
| DMFC1 = 1318, |
| DMFC2 = 1319, |
| DMFC2_OCTEON = 1320, |
| DMFGC0 = 1321, |
| DMOD = 1322, |
| DMODU = 1323, |
| DMT = 1324, |
| DMTC0 = 1325, |
| DMTC1 = 1326, |
| DMTC2 = 1327, |
| DMTC2_OCTEON = 1328, |
| DMTGC0 = 1329, |
| DMUH = 1330, |
| DMUHU = 1331, |
| DMUL = 1332, |
| DMULT = 1333, |
| DMULTu = 1334, |
| DMULU = 1335, |
| DMUL_R6 = 1336, |
| DOTP_S_D = 1337, |
| DOTP_S_H = 1338, |
| DOTP_S_W = 1339, |
| DOTP_U_D = 1340, |
| DOTP_U_H = 1341, |
| DOTP_U_W = 1342, |
| DPADD_S_D = 1343, |
| DPADD_S_H = 1344, |
| DPADD_S_W = 1345, |
| DPADD_U_D = 1346, |
| DPADD_U_H = 1347, |
| DPADD_U_W = 1348, |
| DPAQX_SA_W_PH = 1349, |
| DPAQX_SA_W_PH_MMR2 = 1350, |
| DPAQX_S_W_PH = 1351, |
| DPAQX_S_W_PH_MMR2 = 1352, |
| DPAQ_SA_L_W = 1353, |
| DPAQ_SA_L_W_MM = 1354, |
| DPAQ_S_W_PH = 1355, |
| DPAQ_S_W_PH_MM = 1356, |
| DPAU_H_QBL = 1357, |
| DPAU_H_QBL_MM = 1358, |
| DPAU_H_QBR = 1359, |
| DPAU_H_QBR_MM = 1360, |
| DPAX_W_PH = 1361, |
| DPAX_W_PH_MMR2 = 1362, |
| DPA_W_PH = 1363, |
| DPA_W_PH_MMR2 = 1364, |
| DPOP = 1365, |
| DPSQX_SA_W_PH = 1366, |
| DPSQX_SA_W_PH_MMR2 = 1367, |
| DPSQX_S_W_PH = 1368, |
| DPSQX_S_W_PH_MMR2 = 1369, |
| DPSQ_SA_L_W = 1370, |
| DPSQ_SA_L_W_MM = 1371, |
| DPSQ_S_W_PH = 1372, |
| DPSQ_S_W_PH_MM = 1373, |
| DPSUB_S_D = 1374, |
| DPSUB_S_H = 1375, |
| DPSUB_S_W = 1376, |
| DPSUB_U_D = 1377, |
| DPSUB_U_H = 1378, |
| DPSUB_U_W = 1379, |
| DPSU_H_QBL = 1380, |
| DPSU_H_QBL_MM = 1381, |
| DPSU_H_QBR = 1382, |
| DPSU_H_QBR_MM = 1383, |
| DPSX_W_PH = 1384, |
| DPSX_W_PH_MMR2 = 1385, |
| DPS_W_PH = 1386, |
| DPS_W_PH_MMR2 = 1387, |
| DROTR = 1388, |
| DROTR32 = 1389, |
| DROTRV = 1390, |
| DSBH = 1391, |
| DSDIV = 1392, |
| DSHD = 1393, |
| DSLL = 1394, |
| DSLL32 = 1395, |
| DSLL64_32 = 1396, |
| DSLLV = 1397, |
| DSRA = 1398, |
| DSRA32 = 1399, |
| DSRAV = 1400, |
| DSRL = 1401, |
| DSRL32 = 1402, |
| DSRLV = 1403, |
| DSUB = 1404, |
| DSUBu = 1405, |
| DUDIV = 1406, |
| DVP = 1407, |
| DVPE = 1408, |
| DVP_MMR6 = 1409, |
| DivRxRy16 = 1410, |
| DivuRxRy16 = 1411, |
| EHB = 1412, |
| EHB_MM = 1413, |
| EHB_MMR6 = 1414, |
| EI = 1415, |
| EI_MM = 1416, |
| EI_MMR6 = 1417, |
| EMT = 1418, |
| ERET = 1419, |
| ERETNC = 1420, |
| ERETNC_MMR6 = 1421, |
| ERET_MM = 1422, |
| ERET_MMR6 = 1423, |
| EVP = 1424, |
| EVPE = 1425, |
| EVP_MMR6 = 1426, |
| EXT = 1427, |
| EXTP = 1428, |
| EXTPDP = 1429, |
| EXTPDPV = 1430, |
| EXTPDPV_MM = 1431, |
| EXTPDP_MM = 1432, |
| EXTPV = 1433, |
| EXTPV_MM = 1434, |
| EXTP_MM = 1435, |
| EXTRV_RS_W = 1436, |
| EXTRV_RS_W_MM = 1437, |
| EXTRV_R_W = 1438, |
| EXTRV_R_W_MM = 1439, |
| EXTRV_S_H = 1440, |
| EXTRV_S_H_MM = 1441, |
| EXTRV_W = 1442, |
| EXTRV_W_MM = 1443, |
| EXTR_RS_W = 1444, |
| EXTR_RS_W_MM = 1445, |
| EXTR_R_W = 1446, |
| EXTR_R_W_MM = 1447, |
| EXTR_S_H = 1448, |
| EXTR_S_H_MM = 1449, |
| EXTR_W = 1450, |
| EXTR_W_MM = 1451, |
| EXTS = 1452, |
| EXTS32 = 1453, |
| EXT_MM = 1454, |
| EXT_MMR6 = 1455, |
| FABS_D32 = 1456, |
| FABS_D32_MM = 1457, |
| FABS_D64 = 1458, |
| FABS_D64_MM = 1459, |
| FABS_S = 1460, |
| FABS_S_MM = 1461, |
| FADD_D = 1462, |
| FADD_D32 = 1463, |
| FADD_D32_MM = 1464, |
| FADD_D64 = 1465, |
| FADD_D64_MM = 1466, |
| FADD_S = 1467, |
| FADD_S_MM = 1468, |
| FADD_S_MMR6 = 1469, |
| FADD_W = 1470, |
| FCAF_D = 1471, |
| FCAF_W = 1472, |
| FCEQ_D = 1473, |
| FCEQ_W = 1474, |
| FCLASS_D = 1475, |
| FCLASS_W = 1476, |
| FCLE_D = 1477, |
| FCLE_W = 1478, |
| FCLT_D = 1479, |
| FCLT_W = 1480, |
| FCMP_D32 = 1481, |
| FCMP_D32_MM = 1482, |
| FCMP_D64 = 1483, |
| FCMP_S32 = 1484, |
| FCMP_S32_MM = 1485, |
| FCNE_D = 1486, |
| FCNE_W = 1487, |
| FCOR_D = 1488, |
| FCOR_W = 1489, |
| FCUEQ_D = 1490, |
| FCUEQ_W = 1491, |
| FCULE_D = 1492, |
| FCULE_W = 1493, |
| FCULT_D = 1494, |
| FCULT_W = 1495, |
| FCUNE_D = 1496, |
| FCUNE_W = 1497, |
| FCUN_D = 1498, |
| FCUN_W = 1499, |
| FDIV_D = 1500, |
| FDIV_D32 = 1501, |
| FDIV_D32_MM = 1502, |
| FDIV_D64 = 1503, |
| FDIV_D64_MM = 1504, |
| FDIV_S = 1505, |
| FDIV_S_MM = 1506, |
| FDIV_S_MMR6 = 1507, |
| FDIV_W = 1508, |
| FEXDO_H = 1509, |
| FEXDO_W = 1510, |
| FEXP2_D = 1511, |
| FEXP2_W = 1512, |
| FEXUPL_D = 1513, |
| FEXUPL_W = 1514, |
| FEXUPR_D = 1515, |
| FEXUPR_W = 1516, |
| FFINT_S_D = 1517, |
| FFINT_S_W = 1518, |
| FFINT_U_D = 1519, |
| FFINT_U_W = 1520, |
| FFQL_D = 1521, |
| FFQL_W = 1522, |
| FFQR_D = 1523, |
| FFQR_W = 1524, |
| FILL_B = 1525, |
| FILL_D = 1526, |
| FILL_H = 1527, |
| FILL_W = 1528, |
| FLOG2_D = 1529, |
| FLOG2_W = 1530, |
| FLOOR_L_D64 = 1531, |
| FLOOR_L_D_MMR6 = 1532, |
| FLOOR_L_S = 1533, |
| FLOOR_L_S_MMR6 = 1534, |
| FLOOR_W_D32 = 1535, |
| FLOOR_W_D64 = 1536, |
| FLOOR_W_D_MMR6 = 1537, |
| FLOOR_W_MM = 1538, |
| FLOOR_W_S = 1539, |
| FLOOR_W_S_MM = 1540, |
| FLOOR_W_S_MMR6 = 1541, |
| FMADD_D = 1542, |
| FMADD_W = 1543, |
| FMAX_A_D = 1544, |
| FMAX_A_W = 1545, |
| FMAX_D = 1546, |
| FMAX_W = 1547, |
| FMIN_A_D = 1548, |
| FMIN_A_W = 1549, |
| FMIN_D = 1550, |
| FMIN_W = 1551, |
| FMOV_D32 = 1552, |
| FMOV_D32_MM = 1553, |
| FMOV_D64 = 1554, |
| FMOV_D64_MM = 1555, |
| FMOV_D_MMR6 = 1556, |
| FMOV_S = 1557, |
| FMOV_S_MM = 1558, |
| FMOV_S_MMR6 = 1559, |
| FMSUB_D = 1560, |
| FMSUB_W = 1561, |
| FMUL_D = 1562, |
| FMUL_D32 = 1563, |
| FMUL_D32_MM = 1564, |
| FMUL_D64 = 1565, |
| FMUL_D64_MM = 1566, |
| FMUL_S = 1567, |
| FMUL_S_MM = 1568, |
| FMUL_S_MMR6 = 1569, |
| FMUL_W = 1570, |
| FNEG_D32 = 1571, |
| FNEG_D32_MM = 1572, |
| FNEG_D64 = 1573, |
| FNEG_D64_MM = 1574, |
| FNEG_S = 1575, |
| FNEG_S_MM = 1576, |
| FNEG_S_MMR6 = 1577, |
| FORK = 1578, |
| FRCP_D = 1579, |
| FRCP_W = 1580, |
| FRINT_D = 1581, |
| FRINT_W = 1582, |
| FRSQRT_D = 1583, |
| FRSQRT_W = 1584, |
| FSAF_D = 1585, |
| FSAF_W = 1586, |
| FSEQ_D = 1587, |
| FSEQ_W = 1588, |
| FSLE_D = 1589, |
| FSLE_W = 1590, |
| FSLT_D = 1591, |
| FSLT_W = 1592, |
| FSNE_D = 1593, |
| FSNE_W = 1594, |
| FSOR_D = 1595, |
| FSOR_W = 1596, |
| FSQRT_D = 1597, |
| FSQRT_D32 = 1598, |
| FSQRT_D32_MM = 1599, |
| FSQRT_D64 = 1600, |
| FSQRT_D64_MM = 1601, |
| FSQRT_S = 1602, |
| FSQRT_S_MM = 1603, |
| FSQRT_W = 1604, |
| FSUB_D = 1605, |
| FSUB_D32 = 1606, |
| FSUB_D32_MM = 1607, |
| FSUB_D64 = 1608, |
| FSUB_D64_MM = 1609, |
| FSUB_S = 1610, |
| FSUB_S_MM = 1611, |
| FSUB_S_MMR6 = 1612, |
| FSUB_W = 1613, |
| FSUEQ_D = 1614, |
| FSUEQ_W = 1615, |
| FSULE_D = 1616, |
| FSULE_W = 1617, |
| FSULT_D = 1618, |
| FSULT_W = 1619, |
| FSUNE_D = 1620, |
| FSUNE_W = 1621, |
| FSUN_D = 1622, |
| FSUN_W = 1623, |
| FTINT_S_D = 1624, |
| FTINT_S_W = 1625, |
| FTINT_U_D = 1626, |
| FTINT_U_W = 1627, |
| FTQ_H = 1628, |
| FTQ_W = 1629, |
| FTRUNC_S_D = 1630, |
| FTRUNC_S_W = 1631, |
| FTRUNC_U_D = 1632, |
| FTRUNC_U_W = 1633, |
| GINVI = 1634, |
| GINVI_MMR6 = 1635, |
| GINVT = 1636, |
| GINVT_MMR6 = 1637, |
| HADD_S_D = 1638, |
| HADD_S_H = 1639, |
| HADD_S_W = 1640, |
| HADD_U_D = 1641, |
| HADD_U_H = 1642, |
| HADD_U_W = 1643, |
| HSUB_S_D = 1644, |
| HSUB_S_H = 1645, |
| HSUB_S_W = 1646, |
| HSUB_U_D = 1647, |
| HSUB_U_H = 1648, |
| HSUB_U_W = 1649, |
| HYPCALL = 1650, |
| HYPCALL_MM = 1651, |
| ILVEV_B = 1652, |
| ILVEV_D = 1653, |
| ILVEV_H = 1654, |
| ILVEV_W = 1655, |
| ILVL_B = 1656, |
| ILVL_D = 1657, |
| ILVL_H = 1658, |
| ILVL_W = 1659, |
| ILVOD_B = 1660, |
| ILVOD_D = 1661, |
| ILVOD_H = 1662, |
| ILVOD_W = 1663, |
| ILVR_B = 1664, |
| ILVR_D = 1665, |
| ILVR_H = 1666, |
| ILVR_W = 1667, |
| INS = 1668, |
| INSERT_B = 1669, |
| INSERT_D = 1670, |
| INSERT_H = 1671, |
| INSERT_W = 1672, |
| INSV = 1673, |
| INSVE_B = 1674, |
| INSVE_D = 1675, |
| INSVE_H = 1676, |
| INSVE_W = 1677, |
| INSV_MM = 1678, |
| INS_MM = 1679, |
| INS_MMR6 = 1680, |
| J = 1681, |
| JAL = 1682, |
| JALR = 1683, |
| JALR16_MM = 1684, |
| JALR64 = 1685, |
| JALRC16_MMR6 = 1686, |
| JALRC_HB_MMR6 = 1687, |
| JALRC_MMR6 = 1688, |
| JALRS16_MM = 1689, |
| JALRS_MM = 1690, |
| JALR_HB = 1691, |
| JALR_HB64 = 1692, |
| JALR_MM = 1693, |
| JALS_MM = 1694, |
| JALX = 1695, |
| JALX_MM = 1696, |
| JAL_MM = 1697, |
| JIALC = 1698, |
| JIALC64 = 1699, |
| JIALC_MMR6 = 1700, |
| JIC = 1701, |
| JIC64 = 1702, |
| JIC_MMR6 = 1703, |
| JR = 1704, |
| JR16_MM = 1705, |
| JR64 = 1706, |
| JRADDIUSP = 1707, |
| JRC16_MM = 1708, |
| JRC16_MMR6 = 1709, |
| JRCADDIUSP_MMR6 = 1710, |
| JR_HB = 1711, |
| JR_HB64 = 1712, |
| JR_HB64_R6 = 1713, |
| JR_HB_R6 = 1714, |
| JR_MM = 1715, |
| J_MM = 1716, |
| Jal16 = 1717, |
| JalB16 = 1718, |
| JrRa16 = 1719, |
| JrcRa16 = 1720, |
| JrcRx16 = 1721, |
| JumpLinkReg16 = 1722, |
| LB = 1723, |
| LB64 = 1724, |
| LBE = 1725, |
| LBE_MM = 1726, |
| LBU16_MM = 1727, |
| LBUX = 1728, |
| LBUX_MM = 1729, |
| LBU_MMR6 = 1730, |
| LB_MM = 1731, |
| LB_MMR6 = 1732, |
| LBu = 1733, |
| LBu64 = 1734, |
| LBuE = 1735, |
| LBuE_MM = 1736, |
| LBu_MM = 1737, |
| LD = 1738, |
| LDC1 = 1739, |
| LDC164 = 1740, |
| LDC1_D64_MMR6 = 1741, |
| LDC1_MM = 1742, |
| LDC2 = 1743, |
| LDC2_MMR6 = 1744, |
| LDC2_R6 = 1745, |
| LDC3 = 1746, |
| LDI_B = 1747, |
| LDI_D = 1748, |
| LDI_H = 1749, |
| LDI_W = 1750, |
| LDL = 1751, |
| LDPC = 1752, |
| LDR = 1753, |
| LDXC1 = 1754, |
| LDXC164 = 1755, |
| LD_B = 1756, |
| LD_D = 1757, |
| LD_H = 1758, |
| LD_W = 1759, |
| LEA_ADDiu = 1760, |
| LEA_ADDiu64 = 1761, |
| LEA_ADDiu_MM = 1762, |
| LH = 1763, |
| LH64 = 1764, |
| LHE = 1765, |
| LHE_MM = 1766, |
| LHU16_MM = 1767, |
| LHX = 1768, |
| LHX_MM = 1769, |
| LH_MM = 1770, |
| LHu = 1771, |
| LHu64 = 1772, |
| LHuE = 1773, |
| LHuE_MM = 1774, |
| LHu_MM = 1775, |
| LI16_MM = 1776, |
| LI16_MMR6 = 1777, |
| LL = 1778, |
| LL64 = 1779, |
| LL64_R6 = 1780, |
| LLD = 1781, |
| LLD_R6 = 1782, |
| LLE = 1783, |
| LLE_MM = 1784, |
| LL_MM = 1785, |
| LL_MMR6 = 1786, |
| LL_R6 = 1787, |
| LSA = 1788, |
| LSA_MMR6 = 1789, |
| LSA_R6 = 1790, |
| LUI_MMR6 = 1791, |
| LUXC1 = 1792, |
| LUXC164 = 1793, |
| LUXC1_MM = 1794, |
| LUi = 1795, |
| LUi64 = 1796, |
| LUi_MM = 1797, |
| LW = 1798, |
| LW16_MM = 1799, |
| LW64 = 1800, |
| LWC1 = 1801, |
| LWC1_MM = 1802, |
| LWC2 = 1803, |
| LWC2_MMR6 = 1804, |
| LWC2_R6 = 1805, |
| LWC3 = 1806, |
| LWDSP = 1807, |
| LWDSP_MM = 1808, |
| LWE = 1809, |
| LWE_MM = 1810, |
| LWGP_MM = 1811, |
| LWL = 1812, |
| LWL64 = 1813, |
| LWLE = 1814, |
| LWLE_MM = 1815, |
| LWL_MM = 1816, |
| LWM16_MM = 1817, |
| LWM16_MMR6 = 1818, |
| LWM32_MM = 1819, |
| LWPC = 1820, |
| LWPC_MMR6 = 1821, |
| LWP_MM = 1822, |
| LWR = 1823, |
| LWR64 = 1824, |
| LWRE = 1825, |
| LWRE_MM = 1826, |
| LWR_MM = 1827, |
| LWSP_MM = 1828, |
| LWUPC = 1829, |
| LWU_MM = 1830, |
| LWX = 1831, |
| LWXC1 = 1832, |
| LWXC1_MM = 1833, |
| LWXS_MM = 1834, |
| LWX_MM = 1835, |
| LW_MM = 1836, |
| LW_MMR6 = 1837, |
| LWu = 1838, |
| LbRxRyOffMemX16 = 1839, |
| LbuRxRyOffMemX16 = 1840, |
| LhRxRyOffMemX16 = 1841, |
| LhuRxRyOffMemX16 = 1842, |
| LiRxImm16 = 1843, |
| LiRxImmAlignX16 = 1844, |
| LiRxImmX16 = 1845, |
| LwRxPcTcp16 = 1846, |
| LwRxPcTcpX16 = 1847, |
| LwRxRyOffMemX16 = 1848, |
| LwRxSpImmX16 = 1849, |
| MADD = 1850, |
| MADDF_D = 1851, |
| MADDF_D_MMR6 = 1852, |
| MADDF_S = 1853, |
| MADDF_S_MMR6 = 1854, |
| MADDR_Q_H = 1855, |
| MADDR_Q_W = 1856, |
| MADDU = 1857, |
| MADDU_DSP = 1858, |
| MADDU_DSP_MM = 1859, |
| MADDU_MM = 1860, |
| MADDV_B = 1861, |
| MADDV_D = 1862, |
| MADDV_H = 1863, |
| MADDV_W = 1864, |
| MADD_D32 = 1865, |
| MADD_D32_MM = 1866, |
| MADD_D64 = 1867, |
| MADD_DSP = 1868, |
| MADD_DSP_MM = 1869, |
| MADD_MM = 1870, |
| MADD_Q_H = 1871, |
| MADD_Q_W = 1872, |
| MADD_S = 1873, |
| MADD_S_MM = 1874, |
| MAQ_SA_W_PHL = 1875, |
| MAQ_SA_W_PHL_MM = 1876, |
| MAQ_SA_W_PHR = 1877, |
| MAQ_SA_W_PHR_MM = 1878, |
| MAQ_S_W_PHL = 1879, |
| MAQ_S_W_PHL_MM = 1880, |
| MAQ_S_W_PHR = 1881, |
| MAQ_S_W_PHR_MM = 1882, |
| MAXA_D = 1883, |
| MAXA_D_MMR6 = 1884, |
| MAXA_S = 1885, |
| MAXA_S_MMR6 = 1886, |
| MAXI_S_B = 1887, |
| MAXI_S_D = 1888, |
| MAXI_S_H = 1889, |
| MAXI_S_W = 1890, |
| MAXI_U_B = 1891, |
| MAXI_U_D = 1892, |
| MAXI_U_H = 1893, |
| MAXI_U_W = 1894, |
| MAX_A_B = 1895, |
| MAX_A_D = 1896, |
| MAX_A_H = 1897, |
| MAX_A_W = 1898, |
| MAX_D = 1899, |
| MAX_D_MMR6 = 1900, |
| MAX_S = 1901, |
| MAX_S_B = 1902, |
| MAX_S_D = 1903, |
| MAX_S_H = 1904, |
| MAX_S_MMR6 = 1905, |
| MAX_S_W = 1906, |
| MAX_U_B = 1907, |
| MAX_U_D = 1908, |
| MAX_U_H = 1909, |
| MAX_U_W = 1910, |
| MFC0 = 1911, |
| MFC0_MMR6 = 1912, |
| MFC1 = 1913, |
| MFC1_D64 = 1914, |
| MFC1_MM = 1915, |
| MFC1_MMR6 = 1916, |
| MFC2 = 1917, |
| MFC2_MMR6 = 1918, |
| MFGC0 = 1919, |
| MFGC0_MM = 1920, |
| MFHC0_MMR6 = 1921, |
| MFHC1_D32 = 1922, |
| MFHC1_D32_MM = 1923, |
| MFHC1_D64 = 1924, |
| MFHC1_D64_MM = 1925, |
| MFHC2_MMR6 = 1926, |
| MFHGC0 = 1927, |
| MFHGC0_MM = 1928, |
| MFHI = 1929, |
| MFHI16_MM = 1930, |
| MFHI64 = 1931, |
| MFHI_DSP = 1932, |
| MFHI_DSP_MM = 1933, |
| MFHI_MM = 1934, |
| MFLO = 1935, |
| MFLO16_MM = 1936, |
| MFLO64 = 1937, |
| MFLO_DSP = 1938, |
| MFLO_DSP_MM = 1939, |
| MFLO_MM = 1940, |
| MFTR = 1941, |
| MINA_D = 1942, |
| MINA_D_MMR6 = 1943, |
| MINA_S = 1944, |
| MINA_S_MMR6 = 1945, |
| MINI_S_B = 1946, |
| MINI_S_D = 1947, |
| MINI_S_H = 1948, |
| MINI_S_W = 1949, |
| MINI_U_B = 1950, |
| MINI_U_D = 1951, |
| MINI_U_H = 1952, |
| MINI_U_W = 1953, |
| MIN_A_B = 1954, |
| MIN_A_D = 1955, |
| MIN_A_H = 1956, |
| MIN_A_W = 1957, |
| MIN_D = 1958, |
| MIN_D_MMR6 = 1959, |
| MIN_S = 1960, |
| MIN_S_B = 1961, |
| MIN_S_D = 1962, |
| MIN_S_H = 1963, |
| MIN_S_MMR6 = 1964, |
| MIN_S_W = 1965, |
| MIN_U_B = 1966, |
| MIN_U_D = 1967, |
| MIN_U_H = 1968, |
| MIN_U_W = 1969, |
| MOD = 1970, |
| MODSUB = 1971, |
| MODSUB_MM = 1972, |
| MODU = 1973, |
| MODU_MMR6 = 1974, |
| MOD_MMR6 = 1975, |
| MOD_S_B = 1976, |
| MOD_S_D = 1977, |
| MOD_S_H = 1978, |
| MOD_S_W = 1979, |
| MOD_U_B = 1980, |
| MOD_U_D = 1981, |
| MOD_U_H = 1982, |
| MOD_U_W = 1983, |
| MOVE16_MM = 1984, |
| MOVE16_MMR6 = 1985, |
| MOVEP_MM = 1986, |
| MOVEP_MMR6 = 1987, |
| MOVE_V = 1988, |
| MOVF_D32 = 1989, |
| MOVF_D32_MM = 1990, |
| MOVF_D64 = 1991, |
| MOVF_I = 1992, |
| MOVF_I64 = 1993, |
| MOVF_I_MM = 1994, |
| MOVF_S = 1995, |
| MOVF_S_MM = 1996, |
| MOVN_I64_D64 = 1997, |
| MOVN_I64_I = 1998, |
| MOVN_I64_I64 = 1999, |
| MOVN_I64_S = 2000, |
| MOVN_I_D32 = 2001, |
| MOVN_I_D32_MM = 2002, |
| MOVN_I_D64 = 2003, |
| MOVN_I_I = 2004, |
| MOVN_I_I64 = 2005, |
| MOVN_I_MM = 2006, |
| MOVN_I_S = 2007, |
| MOVN_I_S_MM = 2008, |
| MOVT_D32 = 2009, |
| MOVT_D32_MM = 2010, |
| MOVT_D64 = 2011, |
| MOVT_I = 2012, |
| MOVT_I64 = 2013, |
| MOVT_I_MM = 2014, |
| MOVT_S = 2015, |
| MOVT_S_MM = 2016, |
| MOVZ_I64_D64 = 2017, |
| MOVZ_I64_I = 2018, |
| MOVZ_I64_I64 = 2019, |
| MOVZ_I64_S = 2020, |
| MOVZ_I_D32 = 2021, |
| MOVZ_I_D32_MM = 2022, |
| MOVZ_I_D64 = 2023, |
| MOVZ_I_I = 2024, |
| MOVZ_I_I64 = 2025, |
| MOVZ_I_MM = 2026, |
| MOVZ_I_S = 2027, |
| MOVZ_I_S_MM = 2028, |
| MSUB = 2029, |
| MSUBF_D = 2030, |
| MSUBF_D_MMR6 = 2031, |
| MSUBF_S = 2032, |
| MSUBF_S_MMR6 = 2033, |
| MSUBR_Q_H = 2034, |
| MSUBR_Q_W = 2035, |
| MSUBU = 2036, |
| MSUBU_DSP = 2037, |
| MSUBU_DSP_MM = 2038, |
| MSUBU_MM = 2039, |
| MSUBV_B = 2040, |
| MSUBV_D = 2041, |
| MSUBV_H = 2042, |
| MSUBV_W = 2043, |
| MSUB_D32 = 2044, |
| MSUB_D32_MM = 2045, |
| MSUB_D64 = 2046, |
| MSUB_DSP = 2047, |
| MSUB_DSP_MM = 2048, |
| MSUB_MM = 2049, |
| MSUB_Q_H = 2050, |
| MSUB_Q_W = 2051, |
| MSUB_S = 2052, |
| MSUB_S_MM = 2053, |
| MTC0 = 2054, |
| MTC0_MMR6 = 2055, |
| MTC1 = 2056, |
| MTC1_D64 = 2057, |
| MTC1_D64_MM = 2058, |
| MTC1_MM = 2059, |
| MTC1_MMR6 = 2060, |
| MTC2 = 2061, |
| MTC2_MMR6 = 2062, |
| MTGC0 = 2063, |
| MTGC0_MM = 2064, |
| MTHC0_MMR6 = 2065, |
| MTHC1_D32 = 2066, |
| MTHC1_D32_MM = 2067, |
| MTHC1_D64 = 2068, |
| MTHC1_D64_MM = 2069, |
| MTHC2_MMR6 = 2070, |
| MTHGC0 = 2071, |
| MTHGC0_MM = 2072, |
| MTHI = 2073, |
| MTHI64 = 2074, |
| MTHI_DSP = 2075, |
| MTHI_DSP_MM = 2076, |
| MTHI_MM = 2077, |
| MTHLIP = 2078, |
| MTHLIP_MM = 2079, |
| MTLO = 2080, |
| MTLO64 = 2081, |
| MTLO_DSP = 2082, |
| MTLO_DSP_MM = 2083, |
| MTLO_MM = 2084, |
| MTM0 = 2085, |
| MTM1 = 2086, |
| MTM2 = 2087, |
| MTP0 = 2088, |
| MTP1 = 2089, |
| MTP2 = 2090, |
| MTTR = 2091, |
| MUH = 2092, |
| MUHU = 2093, |
| MUHU_MMR6 = 2094, |
| MUH_MMR6 = 2095, |
| MUL = 2096, |
| MULEQ_S_W_PHL = 2097, |
| MULEQ_S_W_PHL_MM = 2098, |
| MULEQ_S_W_PHR = 2099, |
| MULEQ_S_W_PHR_MM = 2100, |
| MULEU_S_PH_QBL = 2101, |
| MULEU_S_PH_QBL_MM = 2102, |
| MULEU_S_PH_QBR = 2103, |
| MULEU_S_PH_QBR_MM = 2104, |
| MULQ_RS_PH = 2105, |
| MULQ_RS_PH_MM = 2106, |
| MULQ_RS_W = 2107, |
| MULQ_RS_W_MMR2 = 2108, |
| MULQ_S_PH = 2109, |
| MULQ_S_PH_MMR2 = 2110, |
| MULQ_S_W = 2111, |
| MULQ_S_W_MMR2 = 2112, |
| MULR_Q_H = 2113, |
| MULR_Q_W = 2114, |
| MULSAQ_S_W_PH = 2115, |
| MULSAQ_S_W_PH_MM = 2116, |
| MULSA_W_PH = 2117, |
| MULSA_W_PH_MMR2 = 2118, |
| MULT = 2119, |
| MULTU_DSP = 2120, |
| MULTU_DSP_MM = 2121, |
| MULT_DSP = 2122, |
| MULT_DSP_MM = 2123, |
| MULT_MM = 2124, |
| MULTu = 2125, |
| MULTu_MM = 2126, |
| MULU = 2127, |
| MULU_MMR6 = 2128, |
| MULV_B = 2129, |
| MULV_D = 2130, |
| MULV_H = 2131, |
| MULV_W = 2132, |
| MUL_MM = 2133, |
| MUL_MMR6 = 2134, |
| MUL_PH = 2135, |
| MUL_PH_MMR2 = 2136, |
| MUL_Q_H = 2137, |
| MUL_Q_W = 2138, |
| MUL_R6 = 2139, |
| MUL_S_PH = 2140, |
| MUL_S_PH_MMR2 = 2141, |
| Mfhi16 = 2142, |
| Mflo16 = 2143, |
| Move32R16 = 2144, |
| MoveR3216 = 2145, |
| NLOC_B = 2146, |
| NLOC_D = 2147, |
| NLOC_H = 2148, |
| NLOC_W = 2149, |
| NLZC_B = 2150, |
| NLZC_D = 2151, |
| NLZC_H = 2152, |
| NLZC_W = 2153, |
| NMADD_D32 = 2154, |
| NMADD_D32_MM = 2155, |
| NMADD_D64 = 2156, |
| NMADD_S = 2157, |
| NMADD_S_MM = 2158, |
| NMSUB_D32 = 2159, |
| NMSUB_D32_MM = 2160, |
| NMSUB_D64 = 2161, |
| NMSUB_S = 2162, |
| NMSUB_S_MM = 2163, |
| NOR = 2164, |
| NOR64 = 2165, |
| NORI_B = 2166, |
| NOR_MM = 2167, |
| NOR_MMR6 = 2168, |
| NOR_V = 2169, |
| NOT16_MM = 2170, |
| NOT16_MMR6 = 2171, |
| NegRxRy16 = 2172, |
| NotRxRy16 = 2173, |
| OR = 2174, |
| OR16_MM = 2175, |
| OR16_MMR6 = 2176, |
| OR64 = 2177, |
| ORI_B = 2178, |
| ORI_MMR6 = 2179, |
| OR_MM = 2180, |
| OR_MMR6 = 2181, |
| OR_V = 2182, |
| ORi = 2183, |
| ORi64 = 2184, |
| ORi_MM = 2185, |
| OrRxRxRy16 = 2186, |
| PACKRL_PH = 2187, |
| PACKRL_PH_MM = 2188, |
| PAUSE = 2189, |
| PAUSE_MM = 2190, |
| PAUSE_MMR6 = 2191, |
| PCKEV_B = 2192, |
| PCKEV_D = 2193, |
| PCKEV_H = 2194, |
| PCKEV_W = 2195, |
| PCKOD_B = 2196, |
| PCKOD_D = 2197, |
| PCKOD_H = 2198, |
| PCKOD_W = 2199, |
| PCNT_B = 2200, |
| PCNT_D = 2201, |
| PCNT_H = 2202, |
| PCNT_W = 2203, |
| PICK_PH = 2204, |
| PICK_PH_MM = 2205, |
| PICK_QB = 2206, |
| PICK_QB_MM = 2207, |
| PLL_PS64 = 2208, |
| PLU_PS64 = 2209, |
| POP = 2210, |
| PRECEQU_PH_QBL = 2211, |
| PRECEQU_PH_QBLA = 2212, |
| PRECEQU_PH_QBLA_MM = 2213, |
| PRECEQU_PH_QBL_MM = 2214, |
| PRECEQU_PH_QBR = 2215, |
| PRECEQU_PH_QBRA = 2216, |
| PRECEQU_PH_QBRA_MM = 2217, |
| PRECEQU_PH_QBR_MM = 2218, |
| PRECEQ_W_PHL = 2219, |
| PRECEQ_W_PHL_MM = 2220, |
| PRECEQ_W_PHR = 2221, |
| PRECEQ_W_PHR_MM = 2222, |
| PRECEU_PH_QBL = 2223, |
| PRECEU_PH_QBLA = 2224, |
| PRECEU_PH_QBLA_MM = 2225, |
| PRECEU_PH_QBL_MM = 2226, |
| PRECEU_PH_QBR = 2227, |
| PRECEU_PH_QBRA = 2228, |
| PRECEU_PH_QBRA_MM = 2229, |
| PRECEU_PH_QBR_MM = 2230, |
| PRECRQU_S_QB_PH = 2231, |
| PRECRQU_S_QB_PH_MM = 2232, |
| PRECRQ_PH_W = 2233, |
| PRECRQ_PH_W_MM = 2234, |
| PRECRQ_QB_PH = 2235, |
| PRECRQ_QB_PH_MM = 2236, |
| PRECRQ_RS_PH_W = 2237, |
| PRECRQ_RS_PH_W_MM = 2238, |
| PRECR_QB_PH = 2239, |
| PRECR_QB_PH_MMR2 = 2240, |
| PRECR_SRA_PH_W = 2241, |
| PRECR_SRA_PH_W_MMR2 = 2242, |
| PRECR_SRA_R_PH_W = 2243, |
| PRECR_SRA_R_PH_W_MMR2 = 2244, |
| PREF = 2245, |
| PREFE = 2246, |
| PREFE_MM = 2247, |
| PREFX_MM = 2248, |
| PREF_MM = 2249, |
| PREF_MMR6 = 2250, |
| PREF_R6 = 2251, |
| PREPEND = 2252, |
| PREPEND_MMR2 = 2253, |
| RADDU_W_QB = 2254, |
| RADDU_W_QB_MM = 2255, |
| RDDSP = 2256, |
| RDDSP_MM = 2257, |
| RDHWR = 2258, |
| RDHWR64 = 2259, |
| RDHWR_MM = 2260, |
| RDHWR_MMR6 = 2261, |
| RDPGPR_MMR6 = 2262, |
| RECIP_D32 = 2263, |
| RECIP_D32_MM = 2264, |
| RECIP_D64 = 2265, |
| RECIP_D64_MM = 2266, |
| RECIP_S = 2267, |
| RECIP_S_MM = 2268, |
| REPLV_PH = 2269, |
| REPLV_PH_MM = 2270, |
| REPLV_QB = 2271, |
| REPLV_QB_MM = 2272, |
| REPL_PH = 2273, |
| REPL_PH_MM = 2274, |
| REPL_QB = 2275, |
| REPL_QB_MM = 2276, |
| RINT_D = 2277, |
| RINT_D_MMR6 = 2278, |
| RINT_S = 2279, |
| RINT_S_MMR6 = 2280, |
| ROTR = 2281, |
| ROTRV = 2282, |
| ROTRV_MM = 2283, |
| ROTR_MM = 2284, |
| ROUND_L_D64 = 2285, |
| ROUND_L_D_MMR6 = 2286, |
| ROUND_L_S = 2287, |
| ROUND_L_S_MMR6 = 2288, |
| ROUND_W_D32 = 2289, |
| ROUND_W_D64 = 2290, |
| ROUND_W_D_MMR6 = 2291, |
| ROUND_W_MM = 2292, |
| ROUND_W_S = 2293, |
| ROUND_W_S_MM = 2294, |
| ROUND_W_S_MMR6 = 2295, |
| RSQRT_D32 = 2296, |
| RSQRT_D32_MM = 2297, |
| RSQRT_D64 = 2298, |
| RSQRT_D64_MM = 2299, |
| RSQRT_S = 2300, |
| RSQRT_S_MM = 2301, |
| Restore16 = 2302, |
| RestoreX16 = 2303, |
| SAA = 2304, |
| SAAD = 2305, |
| SAT_S_B = 2306, |
| SAT_S_D = 2307, |
| SAT_S_H = 2308, |
| SAT_S_W = 2309, |
| SAT_U_B = 2310, |
| SAT_U_D = 2311, |
| SAT_U_H = 2312, |
| SAT_U_W = 2313, |
| SB = 2314, |
| SB16_MM = 2315, |
| SB16_MMR6 = 2316, |
| SB64 = 2317, |
| SBE = 2318, |
| SBE_MM = 2319, |
| SB_MM = 2320, |
| SB_MMR6 = 2321, |
| SC = 2322, |
| SC64 = 2323, |
| SC64_R6 = 2324, |
| SCD = 2325, |
| SCD_R6 = 2326, |
| SCE = 2327, |
| SCE_MM = 2328, |
| SC_MM = 2329, |
| SC_MMR6 = 2330, |
| SC_R6 = 2331, |
| SD = 2332, |
| SDBBP = 2333, |
| SDBBP16_MM = 2334, |
| SDBBP16_MMR6 = 2335, |
| SDBBP_MM = 2336, |
| SDBBP_MMR6 = 2337, |
| SDBBP_R6 = 2338, |
| SDC1 = 2339, |
| SDC164 = 2340, |
| SDC1_D64_MMR6 = 2341, |
| SDC1_MM = 2342, |
| SDC2 = 2343, |
| SDC2_MMR6 = 2344, |
| SDC2_R6 = 2345, |
| SDC3 = 2346, |
| SDIV = 2347, |
| SDIV_MM = 2348, |
| SDL = 2349, |
| SDR = 2350, |
| SDXC1 = 2351, |
| SDXC164 = 2352, |
| SEB = 2353, |
| SEB64 = 2354, |
| SEB_MM = 2355, |
| SEH = 2356, |
| SEH64 = 2357, |
| SEH_MM = 2358, |
| SELEQZ = 2359, |
| SELEQZ64 = 2360, |
| SELEQZ_D = 2361, |
| SELEQZ_D_MMR6 = 2362, |
| SELEQZ_MMR6 = 2363, |
| SELEQZ_S = 2364, |
| SELEQZ_S_MMR6 = 2365, |
| SELNEZ = 2366, |
| SELNEZ64 = 2367, |
| SELNEZ_D = 2368, |
| SELNEZ_D_MMR6 = 2369, |
| SELNEZ_MMR6 = 2370, |
| SELNEZ_S = 2371, |
| SELNEZ_S_MMR6 = 2372, |
| SEL_D = 2373, |
| SEL_D_MMR6 = 2374, |
| SEL_S = 2375, |
| SEL_S_MMR6 = 2376, |
| SEQ = 2377, |
| SEQi = 2378, |
| SH = 2379, |
| SH16_MM = 2380, |
| SH16_MMR6 = 2381, |
| SH64 = 2382, |
| SHE = 2383, |
| SHE_MM = 2384, |
| SHF_B = 2385, |
| SHF_H = 2386, |
| SHF_W = 2387, |
| SHILO = 2388, |
| SHILOV = 2389, |
| SHILOV_MM = 2390, |
| SHILO_MM = 2391, |
| SHLLV_PH = 2392, |
| SHLLV_PH_MM = 2393, |
| SHLLV_QB = 2394, |
| SHLLV_QB_MM = 2395, |
| SHLLV_S_PH = 2396, |
| SHLLV_S_PH_MM = 2397, |
| SHLLV_S_W = 2398, |
| SHLLV_S_W_MM = 2399, |
| SHLL_PH = 2400, |
| SHLL_PH_MM = 2401, |
| SHLL_QB = 2402, |
| SHLL_QB_MM = 2403, |
| SHLL_S_PH = 2404, |
| SHLL_S_PH_MM = 2405, |
| SHLL_S_W = 2406, |
| SHLL_S_W_MM = 2407, |
| SHRAV_PH = 2408, |
| SHRAV_PH_MM = 2409, |
| SHRAV_QB = 2410, |
| SHRAV_QB_MMR2 = 2411, |
| SHRAV_R_PH = 2412, |
| SHRAV_R_PH_MM = 2413, |
| SHRAV_R_QB = 2414, |
| SHRAV_R_QB_MMR2 = 2415, |
| SHRAV_R_W = 2416, |
| SHRAV_R_W_MM = 2417, |
| SHRA_PH = 2418, |
| SHRA_PH_MM = 2419, |
| SHRA_QB = 2420, |
| SHRA_QB_MMR2 = 2421, |
| SHRA_R_PH = 2422, |
| SHRA_R_PH_MM = 2423, |
| SHRA_R_QB = 2424, |
| SHRA_R_QB_MMR2 = 2425, |
| SHRA_R_W = 2426, |
| SHRA_R_W_MM = 2427, |
| SHRLV_PH = 2428, |
| SHRLV_PH_MMR2 = 2429, |
| SHRLV_QB = 2430, |
| SHRLV_QB_MM = 2431, |
| SHRL_PH = 2432, |
| SHRL_PH_MMR2 = 2433, |
| SHRL_QB = 2434, |
| SHRL_QB_MM = 2435, |
| SH_MM = 2436, |
| SH_MMR6 = 2437, |
| SIGRIE = 2438, |
| SIGRIE_MMR6 = 2439, |
| SLDI_B = 2440, |
| SLDI_D = 2441, |
| SLDI_H = 2442, |
| SLDI_W = 2443, |
| SLD_B = 2444, |
| SLD_D = 2445, |
| SLD_H = 2446, |
| SLD_W = 2447, |
| SLL = 2448, |
| SLL16_MM = 2449, |
| SLL16_MMR6 = 2450, |
| SLL64_32 = 2451, |
| SLL64_64 = 2452, |
| SLLI_B = 2453, |
| SLLI_D = 2454, |
| SLLI_H = 2455, |
| SLLI_W = 2456, |
| SLLV = 2457, |
| SLLV_MM = 2458, |
| SLL_B = 2459, |
| SLL_D = 2460, |
| SLL_H = 2461, |
| SLL_MM = 2462, |
| SLL_MMR6 = 2463, |
| SLL_W = 2464, |
| SLT = 2465, |
| SLT64 = 2466, |
| SLT_MM = 2467, |
| SLTi = 2468, |
| SLTi64 = 2469, |
| SLTi_MM = 2470, |
| SLTiu = 2471, |
| SLTiu64 = 2472, |
| SLTiu_MM = 2473, |
| SLTu = 2474, |
| SLTu64 = 2475, |
| SLTu_MM = 2476, |
| SNE = 2477, |
| SNEi = 2478, |
| SPLATI_B = 2479, |
| SPLATI_D = 2480, |
| SPLATI_H = 2481, |
| SPLATI_W = 2482, |
| SPLAT_B = 2483, |
| SPLAT_D = 2484, |
| SPLAT_H = 2485, |
| SPLAT_W = 2486, |
| SRA = 2487, |
| SRAI_B = 2488, |
| SRAI_D = 2489, |
| SRAI_H = 2490, |
| SRAI_W = 2491, |
| SRARI_B = 2492, |
| SRARI_D = 2493, |
| SRARI_H = 2494, |
| SRARI_W = 2495, |
| SRAR_B = 2496, |
| SRAR_D = 2497, |
| SRAR_H = 2498, |
| SRAR_W = 2499, |
| SRAV = 2500, |
| SRAV_MM = 2501, |
| SRA_B = 2502, |
| SRA_D = 2503, |
| SRA_H = 2504, |
| SRA_MM = 2505, |
| SRA_W = 2506, |
| SRL = 2507, |
| SRL16_MM = 2508, |
| SRL16_MMR6 = 2509, |
| SRLI_B = 2510, |
| SRLI_D = 2511, |
| SRLI_H = 2512, |
| SRLI_W = 2513, |
| SRLRI_B = 2514, |
| SRLRI_D = 2515, |
| SRLRI_H = 2516, |
| SRLRI_W = 2517, |
| SRLR_B = 2518, |
| SRLR_D = 2519, |
| SRLR_H = 2520, |
| SRLR_W = 2521, |
| SRLV = 2522, |
| SRLV_MM = 2523, |
| SRL_B = 2524, |
| SRL_D = 2525, |
| SRL_H = 2526, |
| SRL_MM = 2527, |
| SRL_W = 2528, |
| SSNOP = 2529, |
| SSNOP_MM = 2530, |
| SSNOP_MMR6 = 2531, |
| ST_B = 2532, |
| ST_D = 2533, |
| ST_H = 2534, |
| ST_W = 2535, |
| SUB = 2536, |
| SUBQH_PH = 2537, |
| SUBQH_PH_MMR2 = 2538, |
| SUBQH_R_PH = 2539, |
| SUBQH_R_PH_MMR2 = 2540, |
| SUBQH_R_W = 2541, |
| SUBQH_R_W_MMR2 = 2542, |
| SUBQH_W = 2543, |
| SUBQH_W_MMR2 = 2544, |
| SUBQ_PH = 2545, |
| SUBQ_PH_MM = 2546, |
| SUBQ_S_PH = 2547, |
| SUBQ_S_PH_MM = 2548, |
| SUBQ_S_W = 2549, |
| SUBQ_S_W_MM = 2550, |
| SUBSUS_U_B = 2551, |
| SUBSUS_U_D = 2552, |
| SUBSUS_U_H = 2553, |
| SUBSUS_U_W = 2554, |
| SUBSUU_S_B = 2555, |
| SUBSUU_S_D = 2556, |
| SUBSUU_S_H = 2557, |
| SUBSUU_S_W = 2558, |
| SUBS_S_B = 2559, |
| SUBS_S_D = 2560, |
| SUBS_S_H = 2561, |
| SUBS_S_W = 2562, |
| SUBS_U_B = 2563, |
| SUBS_U_D = 2564, |
| SUBS_U_H = 2565, |
| SUBS_U_W = 2566, |
| SUBU16_MM = 2567, |
| SUBU16_MMR6 = 2568, |
| SUBUH_QB = 2569, |
| SUBUH_QB_MMR2 = 2570, |
| SUBUH_R_QB = 2571, |
| SUBUH_R_QB_MMR2 = 2572, |
| SUBU_MMR6 = 2573, |
| SUBU_PH = 2574, |
| SUBU_PH_MMR2 = 2575, |
| SUBU_QB = 2576, |
| SUBU_QB_MM = 2577, |
| SUBU_S_PH = 2578, |
| SUBU_S_PH_MMR2 = 2579, |
| SUBU_S_QB = 2580, |
| SUBU_S_QB_MM = 2581, |
| SUBVI_B = 2582, |
| SUBVI_D = 2583, |
| SUBVI_H = 2584, |
| SUBVI_W = 2585, |
| SUBV_B = 2586, |
| SUBV_D = 2587, |
| SUBV_H = 2588, |
| SUBV_W = 2589, |
| SUB_MM = 2590, |
| SUB_MMR6 = 2591, |
| SUBu = 2592, |
| SUBu_MM = 2593, |
| SUXC1 = 2594, |
| SUXC164 = 2595, |
| SUXC1_MM = 2596, |
| SW = 2597, |
| SW16_MM = 2598, |
| SW16_MMR6 = 2599, |
| SW64 = 2600, |
| SWC1 = 2601, |
| SWC1_MM = 2602, |
| SWC2 = 2603, |
| SWC2_MMR6 = 2604, |
| SWC2_R6 = 2605, |
| SWC3 = 2606, |
| SWDSP = 2607, |
| SWDSP_MM = 2608, |
| SWE = 2609, |
| SWE_MM = 2610, |
| SWL = 2611, |
| SWL64 = 2612, |
| SWLE = 2613, |
| SWLE_MM = 2614, |
| SWL_MM = 2615, |
| SWM16_MM = 2616, |
| SWM16_MMR6 = 2617, |
| SWM32_MM = 2618, |
| SWP_MM = 2619, |
| SWR = 2620, |
| SWR64 = 2621, |
| SWRE = 2622, |
| SWRE_MM = 2623, |
| SWR_MM = 2624, |
| SWSP_MM = 2625, |
| SWSP_MMR6 = 2626, |
| SWXC1 = 2627, |
| SWXC1_MM = 2628, |
| SW_MM = 2629, |
| SW_MMR6 = 2630, |
| SYNC = 2631, |
| SYNCI = 2632, |
| SYNCI_MM = 2633, |
| SYNCI_MMR6 = 2634, |
| SYNC_MM = 2635, |
| SYNC_MMR6 = 2636, |
| SYSCALL = 2637, |
| SYSCALL_MM = 2638, |
| Save16 = 2639, |
| SaveX16 = 2640, |
| SbRxRyOffMemX16 = 2641, |
| SebRx16 = 2642, |
| SehRx16 = 2643, |
| ShRxRyOffMemX16 = 2644, |
| SllX16 = 2645, |
| SllvRxRy16 = 2646, |
| SltRxRy16 = 2647, |
| SltiRxImm16 = 2648, |
| SltiRxImmX16 = 2649, |
| SltiuRxImm16 = 2650, |
| SltiuRxImmX16 = 2651, |
| SltuRxRy16 = 2652, |
| SraX16 = 2653, |
| SravRxRy16 = 2654, |
| SrlX16 = 2655, |
| SrlvRxRy16 = 2656, |
| SubuRxRyRz16 = 2657, |
| SwRxRyOffMemX16 = 2658, |
| SwRxSpImmX16 = 2659, |
| TEQ = 2660, |
| TEQI = 2661, |
| TEQI_MM = 2662, |
| TEQ_MM = 2663, |
| TGE = 2664, |
| TGEI = 2665, |
| TGEIU = 2666, |
| TGEIU_MM = 2667, |
| TGEI_MM = 2668, |
| TGEU = 2669, |
| TGEU_MM = 2670, |
| TGE_MM = 2671, |
| TLBGINV = 2672, |
| TLBGINVF = 2673, |
| TLBGINVF_MM = 2674, |
| TLBGINV_MM = 2675, |
| TLBGP = 2676, |
| TLBGP_MM = 2677, |
| TLBGR = 2678, |
| TLBGR_MM = 2679, |
| TLBGWI = 2680, |
| TLBGWI_MM = 2681, |
| TLBGWR = 2682, |
| TLBGWR_MM = 2683, |
| TLBINV = 2684, |
| TLBINVF = 2685, |
| TLBINVF_MMR6 = 2686, |
| TLBINV_MMR6 = 2687, |
| TLBP = 2688, |
| TLBP_MM = 2689, |
| TLBR = 2690, |
| TLBR_MM = 2691, |
| TLBWI = 2692, |
| TLBWI_MM = 2693, |
| TLBWR = 2694, |
| TLBWR_MM = 2695, |
| TLT = 2696, |
| TLTI = 2697, |
| TLTIU_MM = 2698, |
| TLTI_MM = 2699, |
| TLTU = 2700, |
| TLTU_MM = 2701, |
| TLT_MM = 2702, |
| TNE = 2703, |
| TNEI = 2704, |
| TNEI_MM = 2705, |
| TNE_MM = 2706, |
| TRUNC_L_D64 = 2707, |
| TRUNC_L_D_MMR6 = 2708, |
| TRUNC_L_S = 2709, |
| TRUNC_L_S_MMR6 = 2710, |
| TRUNC_W_D32 = 2711, |
| TRUNC_W_D64 = 2712, |
| TRUNC_W_D_MMR6 = 2713, |
| TRUNC_W_MM = 2714, |
| TRUNC_W_S = 2715, |
| TRUNC_W_S_MM = 2716, |
| TRUNC_W_S_MMR6 = 2717, |
| TTLTIU = 2718, |
| UDIV = 2719, |
| UDIV_MM = 2720, |
| V3MULU = 2721, |
| VMM0 = 2722, |
| VMULU = 2723, |
| VSHF_B = 2724, |
| VSHF_D = 2725, |
| VSHF_H = 2726, |
| VSHF_W = 2727, |
| WAIT = 2728, |
| WAIT_MM = 2729, |
| WAIT_MMR6 = 2730, |
| WRDSP = 2731, |
| WRDSP_MM = 2732, |
| WRPGPR_MMR6 = 2733, |
| WSBH = 2734, |
| WSBH_MM = 2735, |
| WSBH_MMR6 = 2736, |
| XOR = 2737, |
| XOR16_MM = 2738, |
| XOR16_MMR6 = 2739, |
| XOR64 = 2740, |
| XORI_B = 2741, |
| XORI_MMR6 = 2742, |
| XOR_MM = 2743, |
| XOR_MMR6 = 2744, |
| XOR_V = 2745, |
| XORi = 2746, |
| XORi64 = 2747, |
| XORi_MM = 2748, |
| XorRxRxRy16 = 2749, |
| YIELD = 2750, |
| INSTRUCTION_LIST_END = 2751 |
| }; |
| |
| } // end namespace Mips |
| } // end namespace llvm |
| #endif // GET_INSTRINFO_ENUM |
| |
| #ifdef GET_INSTRINFO_SCHED_ENUM |
| #undef GET_INSTRINFO_SCHED_ENUM |
| namespace llvm { |
| |
| namespace Mips { |
| namespace Sched { |
| enum { |
| NoInstrModel = 0, |
| IIPseudo = 1, |
| II_B = 2, |
| II_BCCZAL = 3, |
| II_MTC1 = 4, |
| II_MFC1 = 5, |
| II_JALR = 6, |
| II_JAL = 7, |
| II_CVT = 8, |
| II_DMULT = 9, |
| II_DMULTU = 10, |
| II_DDIV = 11, |
| II_DDIVU = 12, |
| II_IndirectBranchPseudo = 13, |
| II_MADD = 14, |
| II_MADDU = 15, |
| II_MFHI_MFLO = 16, |
| II_MSUB = 17, |
| II_MSUBU = 18, |
| II_MTHI_MTLO = 19, |
| II_MULT = 20, |
| II_MULTU = 21, |
| II_ReturnPseudo = 22, |
| II_DIV = 23, |
| II_DIVU = 24, |
| II_J = 25, |
| II_JR = 26, |
| II_TRAP = 27, |
| II_ADD = 28, |
| II_ADDIUPC = 29, |
| II_ADDIU = 30, |
| II_ADDU = 31, |
| II_ADDI = 32, |
| II_ALIGN = 33, |
| II_ALUIPC = 34, |
| II_AND = 35, |
| II_ANDI = 36, |
| II_AUI = 37, |
| II_AUIPC = 38, |
| IIM16Alu = 39, |
| II_BADDU = 40, |
| II_BC = 41, |
| II_BALC = 42, |
| II_BBIT = 43, |
| II_BC1CCZ = 44, |
| II_BC1F = 45, |
| II_BC1FL = 46, |
| II_BC1T = 47, |
| II_BC1TL = 48, |
| II_BC2CCZ = 49, |
| II_BCC = 50, |
| II_BCCC = 51, |
| II_BCCZ = 52, |
| II_BCCZC = 53, |
| II_BCCZALS = 54, |
| II_BITSWAP = 55, |
| II_BREAK = 56, |
| II_CACHE = 57, |
| II_CACHEE = 58, |
| II_CEIL = 59, |
| II_CFC1 = 60, |
| II_CFC2 = 61, |
| II_INS = 62, |
| II_CLASS_D = 63, |
| II_CLASS_S = 64, |
| II_CLO = 65, |
| II_CLZ = 66, |
| II_CMP_CC_D = 67, |
| II_CMP_CC_S = 68, |
| II_CRC32B = 69, |
| II_CRC32CB = 70, |
| II_CRC32CD = 71, |
| II_CRC32CH = 72, |
| II_CRC32CW = 73, |
| II_CRC32D = 74, |
| II_CRC32H = 75, |
| II_CRC32W = 76, |
| II_CTC1 = 77, |
| II_CTC2 = 78, |
| II_C_CC_D = 79, |
| II_C_CC_S = 80, |
| II_DADD = 81, |
| II_DADDI = 82, |
| II_DADDIU = 83, |
| II_DADDU = 84, |
| II_DAHI = 85, |
| II_DALIGN = 86, |
| II_DATI = 87, |
| II_DAUI = 88, |
| II_DBITSWAP = 89, |
| II_DCLO = 90, |
| II_DCLZ = 91, |
| II_DERET = 92, |
| II_EXT = 93, |
| II_DI = 94, |
| II_DLSA = 95, |
| II_DMFC0 = 96, |
| II_DMFC1 = 97, |
| II_DMFC2 = 98, |
| II_DMFGC0 = 99, |
| II_DMOD = 100, |
| II_DMODU = 101, |
| II_DMT = 102, |
| II_DMTC0 = 103, |
| II_DMTC1 = 104, |
| II_DMTC2 = 105, |
| II_DMTGC0 = 106, |
| II_DMUH = 107, |
| II_DMUHU = 108, |
| II_DMUL = 109, |
| II_POP = 110, |
| II_DROTR = 111, |
| II_DROTR32 = 112, |
| II_DROTRV = 113, |
| II_DSBH = 114, |
| II_DSHD = 115, |
| II_DSLL = 116, |
| II_DSLL32 = 117, |
| II_DSLLV = 118, |
| II_DSRA = 119, |
| II_DSRA32 = 120, |
| II_DSRAV = 121, |
| II_DSRL = 122, |
| II_DSRL32 = 123, |
| II_DSRLV = 124, |
| II_DSUB = 125, |
| II_DSUBU = 126, |
| II_DVP = 127, |
| II_DVPE = 128, |
| II_EHB = 129, |
| II_EI = 130, |
| II_EMT = 131, |
| II_ERET = 132, |
| II_ERETNC = 133, |
| II_EVP = 134, |
| II_EVPE = 135, |
| II_ABS = 136, |
| II_SQRT_D = 137, |
| II_ADD_D = 138, |
| II_ADD_S = 139, |
| II_DIV_D = 140, |
| II_DIV_S = 141, |
| II_FLOOR = 142, |
| II_MOV_D = 143, |
| II_MOV_S = 144, |
| II_MUL_D = 145, |
| II_MUL_S = 146, |
| II_NEG = 147, |
| II_FORK = 148, |
| II_SQRT_S = 149, |
| II_SUB_D = 150, |
| II_SUB_S = 151, |
| II_GINVI = 152, |
| II_GINVT = 153, |
| II_HYPCALL = 154, |
| II_JALR_HB = 155, |
| II_JALRC = 156, |
| II_JALRS = 157, |
| II_JALS = 158, |
| II_JIALC = 159, |
| II_JIC = 160, |
| II_JRADDIUSP = 161, |
| II_JRC = 162, |
| II_JR_HB = 163, |
| II_LB = 164, |
| II_LBE = 165, |
| II_LBU = 166, |
| II_LBUE = 167, |
| II_LD = 168, |
| II_LDC1 = 169, |
| II_LDC2 = 170, |
| II_LDC3 = 171, |
| II_LDL = 172, |
| II_LDPC = 173, |
| II_LDR = 174, |
| II_LDXC1 = 175, |
| II_LH = 176, |
| II_LHE = 177, |
| II_LHU = 178, |
| II_LHUE = 179, |
| II_LI = 180, |
| II_LL = 181, |
| II_LLD = 182, |
| II_LLE = 183, |
| II_LSA = 184, |
| II_LUI = 185, |
| II_LUXC1 = 186, |
| II_LW = 187, |
| II_LWC1 = 188, |
| II_LWC2 = 189, |
| II_LWC3 = 190, |
| II_LWE = 191, |
| II_LWL = 192, |
| II_LWLE = 193, |
| II_LWM = 194, |
| II_LWPC = 195, |
| II_LWP = 196, |
| II_LWR = 197, |
| II_LWRE = 198, |
| II_LWUPC = 199, |
| II_LWU = 200, |
| II_LWXC1 = 201, |
| II_LWXS = 202, |
| II_MADDF_D = 203, |
| II_MADDF_S = 204, |
| II_MADD_D = 205, |
| II_MADD_S = 206, |
| II_MAX_D = 207, |
| II_MAXA_D = 208, |
| II_MAX_S = 209, |
| II_MAXA_S = 210, |
| II_MFC0 = 211, |
| II_MFC2 = 212, |
| II_MFGC0 = 213, |
| II_MFHC0 = 214, |
| II_MFHC1 = 215, |
| II_MFHGC0 = 216, |
| II_MFTR = 217, |
| II_MIN_S = 218, |
| II_MINA_D = 219, |
| II_MIN_D = 220, |
| II_MINA_S = 221, |
| II_MOD = 222, |
| II_MODU = 223, |
| II_MOVE = 224, |
| II_MOVF_D = 225, |
| II_MOVF = 226, |
| II_MOVF_S = 227, |
| II_MOVN_D = 228, |
| II_MOVN = 229, |
| II_MOVN_S = 230, |
| II_MOVT_D = 231, |
| II_MOVT = 232, |
| II_MOVT_S = 233, |
| II_MOVZ_D = 234, |
| II_MOVZ = 235, |
| II_MOVZ_S = 236, |
| II_MSUBF_D = 237, |
| II_MSUBF_S = 238, |
| II_MSUB_D = 239, |
| II_MSUB_S = 240, |
| II_MTC0 = 241, |
| II_MTC2 = 242, |
| II_MTGC0 = 243, |
| II_MTHC0 = 244, |
| II_MTHC1 = 245, |
| II_MTHGC0 = 246, |
| II_MTTR = 247, |
| II_MUH = 248, |
| II_MUHU = 249, |
| II_MUL = 250, |
| II_MULU = 251, |
| II_NMADD_D = 252, |
| II_NMADD_S = 253, |
| II_NMSUB_D = 254, |
| II_NMSUB_S = 255, |
| II_NOR = 256, |
| II_NOT = 257, |
| II_OR = 258, |
| II_ORI = 259, |
| II_PAUSE = 260, |
| II_PREF = 261, |
| II_PREFE = 262, |
| II_RDHWR = 263, |
| II_RDPGPR = 264, |
| II_RECIP_D = 265, |
| II_RECIP_S = 266, |
| II_RINT_D = 267, |
| II_RINT_S = 268, |
| II_ROTR = 269, |
| II_ROTRV = 270, |
| II_ROUND = 271, |
| II_RSQRT_D = 272, |
| II_RSQRT_S = 273, |
| II_RESTORE = 274, |
| II_SB = 275, |
| II_SBE = 276, |
| II_SC = 277, |
| II_SCD = 278, |
| II_SCE = 279, |
| II_SD = 280, |
| II_SDBBP = 281, |
| II_SDC1 = 282, |
| II_SDC2 = 283, |
| II_SDC3 = 284, |
| II_SDL = 285, |
| II_SDR = 286, |
| II_SDXC1 = 287, |
| II_SEB = 288, |
| II_SEH = 289, |
| II_SELCCZ = 290, |
| II_SELCCZ_D = 291, |
| II_SELCCZ_S = 292, |
| II_SEL_D = 293, |
| II_SEL_S = 294, |
| II_SEQ_SNE = 295, |
| II_SEQI_SNEI = 296, |
| II_SH = 297, |
| II_SHE = 298, |
| II_SIGRIE = 299, |
| II_SLL = 300, |
| II_SLLV = 301, |
| II_SLT_SLTU = 302, |
| II_SLTI_SLTIU = 303, |
| II_SRA = 304, |
| II_SRAV = 305, |
| II_SRL = 306, |
| II_SRLV = 307, |
| II_SSNOP = 308, |
| II_SUB = 309, |
| II_SUBU = 310, |
| II_SUXC1 = 311, |
| II_SW = 312, |
| II_SWC1 = 313, |
| II_SWC2 = 314, |
| II_SWC3 = 315, |
| II_SWE = 316, |
| II_SWL = 317, |
| II_SWLE = 318, |
| II_SWM = 319, |
| II_SWP = 320, |
| II_SWR = 321, |
| II_SWRE = 322, |
| II_SWXC1 = 323, |
| II_SYNC = 324, |
| II_SYNCI = 325, |
| II_SYSCALL = 326, |
| II_SAVE = 327, |
| II_TEQ = 328, |
| II_TEQI = 329, |
| II_TGE = 330, |
| II_TGEI = 331, |
| II_TGEIU = 332, |
| II_TGEU = 333, |
| II_TLBGINV = 334, |
| II_TLBGINVF = 335, |
| II_TLBGP = 336, |
| II_TLBGR = 337, |
| II_TLBGWI = 338, |
| II_TLBGWR = 339, |
| II_TLBINV = 340, |
| II_TLBINVF = 341, |
| II_TLBP = 342, |
| II_TLBR = 343, |
| II_TLBWI = 344, |
| II_TLBWR = 345, |
| II_TLT = 346, |
| II_TLTI = 347, |
| II_TTLTIU = 348, |
| II_TLTU = 349, |
| II_TNE = 350, |
| II_TNEI = 351, |
| II_TRUNC = 352, |
| II_WAIT = 353, |
| II_WRPGPR = 354, |
| II_WSBH = 355, |
| II_XOR = 356, |
| II_XORI = 357, |
| II_YIELD = 358, |
| AND = 359, |
| LUi = 360, |
| NOR = 361, |
| OR = 362, |
| SLTi_SLTiu = 363, |
| SUB = 364, |
| SUBu = 365, |
| XOR = 366, |
| SSNOP = 367, |
| NOP = 368, |
| B = 369, |
| BAL = 370, |
| BAL_BR_BGEZAL_BGEZALL_BLTZAL_BLTZALL = 371, |
| BEQ_BEQL_BNE_BNEL = 372, |
| BGEZ_BGEZL_BGTZ_BGTZL_BLEZ_BLEZL_BLTZ_BLTZL = 373, |
| BREAK = 374, |
| DERET = 375, |
| ERET = 376, |
| ERet_RetRA = 377, |
| ERETNC = 378, |
| J_TAILCALL = 379, |
| JR_TAILCALLREG_TAILCALLREGHB = 380, |
| JR_HB = 381, |
| PseudoIndirectBranch_PseudoIndirectHazardBranch = 382, |
| PseudoReturn = 383, |
| SDBBP = 384, |
| SYSCALL = 385, |
| TEQ = 386, |
| TEQI = 387, |
| TGE = 388, |
| TGEI = 389, |
| TGEIU = 390, |
| TGEU = 391, |
| TLT = 392, |
| TLTI = 393, |
| TLTU = 394, |
| TNE = 395, |
| TNEI = 396, |
| TRAP = 397, |
| TTLTIU = 398, |
| WAIT = 399, |
| PAUSE = 400, |
| JAL = 401, |
| JALR_JALRHBPseudo_JALRPseudo = 402, |
| JALR_HB = 403, |
| JALX = 404, |
| TLBINV = 405, |
| TLBINVF = 406, |
| TLBP = 407, |
| TLBR = 408, |
| TLBWI = 409, |
| TLBWR = 410, |
| MFC0 = 411, |
| MTC0 = 412, |
| MFC2 = 413, |
| MTC2 = 414, |
| HYPCALL = 415, |
| MFGC0 = 416, |
| MFHGC0 = 417, |
| MTGC0 = 418, |
| MTHGC0 = 419, |
| TLBGINV = 420, |
| TLBGINVF = 421, |
| TLBGP = 422, |
| TLBGR = 423, |
| TLBGWI = 424, |
| TLBGWR = 425, |
| LB = 426, |
| LBu = 427, |
| LH = 428, |
| LHu = 429, |
| LW = 430, |
| LL = 431, |
| LWC2 = 432, |
| LWC3 = 433, |
| LDC2 = 434, |
| LDC3 = 435, |
| LBE = 436, |
| LBuE = 437, |
| LHE = 438, |
| LHuE = 439, |
| LWE = 440, |
| LLE = 441, |
| LWPC = 442, |
| LWL = 443, |
| LWR = 444, |
| LWLE = 445, |
| LWRE = 446, |
| SB = 447, |
| SH = 448, |
| SW = 449, |
| SWC2 = 450, |
| SWC3 = 451, |
| SDC2 = 452, |
| SDC3 = 453, |
| SC = 454, |
| SBE = 455, |
| SHE = 456, |
| SWE = 457, |
| SCE = 458, |
| SWL = 459, |
| SWR = 460, |
| SWLE = 461, |
| SWRE = 462, |
| PREF = 463, |
| PREFE = 464, |
| CACHE = 465, |
| CACHEE = 466, |
| SYNC = 467, |
| SYNCI = 468, |
| CLO = 469, |
| CLZ = 470, |
| DI = 471, |
| EI = 472, |
| MFHI_MFLO_PseudoMFHI_PseudoMFLO = 473, |
| EHB = 474, |
| RDHWR = 475, |
| WSBH = 476, |
| MOVN_I_I = 477, |
| MOVZ_I_I = 478, |
| DIV_PseudoSDIV_SDIV = 479, |
| DIVU_PseudoUDIV_UDIV = 480, |
| MUL = 481, |
| MULT_PseudoMULT = 482, |
| MULTu_PseudoMULTu = 483, |
| MADD_PseudoMADD = 484, |
| MADDU_PseudoMADDU = 485, |
| MSUB_PseudoMSUB = 486, |
| MSUBU_PseudoMSUBU = 487, |
| MTHI_MTLO_PseudoMTLOHI = 488, |
| EXT = 489, |
| INS = 490, |
| ADD = 491, |
| ADDi = 492, |
| ADDiu = 493, |
| ANDi = 494, |
| ORi = 495, |
| ROTR = 496, |
| SEB = 497, |
| SEH = 498, |
| SLT_SLTu = 499, |
| SLL = 500, |
| SRA = 501, |
| SRL = 502, |
| XORi = 503, |
| ADDu = 504, |
| SLLV = 505, |
| SRAV = 506, |
| SRLV = 507, |
| LSA = 508, |
| COPY = 509, |
| VSHF_B_VSHF_D_VSHF_H_VSHF_W = 510, |
| BINSLI_B_BINSLI_D_BINSLI_H_BINSLI_W_BINSL_B_BINSL_D_BINSL_H_BINSL_W = 511, |
| BINSRI_B_BINSRI_D_BINSRI_H_BINSRI_W_BINSR_B_BINSR_D_BINSR_H_BINSR_W = 512, |
| INSERT_B_INSERT_D_INSERT_H_INSERT_W = 513, |
| SLDI_B_SLDI_D_SLDI_H_SLDI_W_SLD_B_SLD_D_SLD_H_SLD_W = 514, |
| BSETI_B_BSETI_D_BSETI_H_BSETI_W_BSET_B_BSET_D_BSET_H_BSET_W = 515, |
| BCLRI_B_BCLRI_D_BCLRI_H_BCLRI_W_BCLR_B_BCLR_D_BCLR_H_BCLR_W = 516, |
| BNEGI_B_BNEGI_D_BNEGI_H_BNEGI_W_BNEG_B_BNEG_D_BNEG_H_BNEG_W = 517, |
| BSELI_B_BSEL_V = 518, |
| BMNZI_B_BMNZ_V_BMZI_B_BMZ_V = 519, |
| BSEL_D_PSEUDO_BSEL_FD_PSEUDO_BSEL_FW_PSEUDO_BSEL_H_PSEUDO_BSEL_W_PSEUDO = 520, |
| PCNT_B_PCNT_D_PCNT_H_PCNT_W = 521, |
| SAT_S_B_SAT_S_D_SAT_S_H_SAT_S_W_SAT_U_B_SAT_U_D_SAT_U_H_SAT_U_W = 522, |
| BNZ_B_BNZ_D_BNZ_H_BNZ_V_BNZ_W_BZ_B_BZ_D_BZ_H_BZ_V_BZ_W = 523, |
| CFCMSA_CTCMSA = 524, |
| FABS_S_FABS_D32_FABS_D64 = 525, |
| MOVF_D32_MOVF_D64 = 526, |
| MOVF_S = 527, |
| MOVT_D32_MOVT_D64 = 528, |
| MOVT_S = 529, |
| FMOV_D32_FMOV_D64 = 530, |
| FMOV_S = 531, |
| FNEG_S_FNEG_D32_FNEG_D64 = 532, |
| ADD_A_B_ADD_A_D_ADD_A_H_ADD_A_W = 533, |
| ADDS_A_B_ADDS_A_D_ADDS_A_H_ADDS_A_W_ADDS_S_B_ADDS_S_D_ADDS_S_H_ADDS_S_W_ADDS_U_B_ADDS_U_D_ADDS_U_H_ADDS_U_W = 534, |
| ADDVI_B_ADDVI_D_ADDVI_H_ADDVI_W_ADDV_B_ADDV_D_ADDV_H_ADDV_W = 535, |
| ASUB_S_B_ASUB_S_D_ASUB_S_H_ASUB_S_W_ASUB_U_B_ASUB_U_D_ASUB_U_H_ASUB_U_W = 536, |
| AVER_S_B_AVER_S_D_AVER_S_H_AVER_S_W_AVER_U_B_AVER_U_D_AVER_U_H_AVER_U_W_AVE_S_B_AVE_S_D_AVE_S_H_AVE_S_W_AVE_U_B_AVE_U_D_AVE_U_H_AVE_U_W = 537, |
| SHF_B_SHF_H_SHF_W = 538, |
| FILL_B_FILL_D_FILL_H_FILL_W = 539, |
| SPLATI_B_SPLATI_D_SPLATI_H_SPLATI_W_SPLAT_B_SPLAT_D_SPLAT_H_SPLAT_W = 540, |
| MOVE_V = 541, |
| LDI_B_LDI_D_LDI_H_LDI_W = 542, |
| AND_V_NOR_V_OR_V_XOR_V = 543, |
| ANDI_B_NORI_B_ORI_B_XORI_B = 544, |
| AND_V_D_PSEUDO_AND_V_H_PSEUDO_AND_V_W_PSEUDO_NOR_V_D_PSEUDO_NOR_V_H_PSEUDO_NOR_V_W_PSEUDO_OR_V_D_PSEUDO_OR_V_H_PSEUDO_OR_V_W_PSEUDO_XOR_V_D_PSEUDO_XOR_V_H_PSEUDO_XOR_V_W_PSEUDO = 545, |
| FILL_FD_PSEUDO_FILL_FW_PSEUDO = 546, |
| INSERT_FD_PSEUDO_INSERT_FW_PSEUDO = 547, |
| FEXP2_D_FEXP2_W = 548, |
| CLTI_S_B_CLTI_S_D_CLTI_S_H_CLTI_S_W_CLTI_U_B_CLTI_U_D_CLTI_U_H_CLTI_U_W_CLT_S_B_CLT_S_D_CLT_S_H_CLT_S_W_CLT_U_B_CLT_U_D_CLT_U_H_CLT_U_W = 549, |
| CLEI_S_B_CLEI_S_D_CLEI_S_H_CLEI_S_W_CLEI_U_B_CLEI_U_D_CLEI_U_H_CLEI_U_W_CLE_S_B_CLE_S_D_CLE_S_H_CLE_S_W_CLE_U_B_CLE_U_D_CLE_U_H_CLE_U_W = 550, |
| CEQI_B_CEQI_D_CEQI_H_CEQI_W_CEQ_B_CEQ_D_CEQ_H_CEQ_W = 551, |
| CMP_UN_D = 552, |
| CMP_UN_S = 553, |
| CMP_UEQ_D = 554, |
| CMP_UEQ_S = 555, |
| CMP_EQ_D = 556, |
| CMP_EQ_S = 557, |
| CMP_LT_D = 558, |
| CMP_LT_S = 559, |
| CMP_ULT_D = 560, |
| CMP_ULT_S = 561, |
| CMP_LE_D = 562, |
| CMP_LE_S = 563, |
| CMP_ULE_D = 564, |
| CMP_ULE_S = 565, |
| FSAF_D_FSAF_W_FSEQ_D_FSEQ_W_FSLE_D_FSLE_W_FSLT_D_FSLT_W_FSNE_D_FSNE_W_FSOR_D_FSOR_W = 566, |
| FSUEQ_D_FSUEQ_W = 567, |
| FSULE_D_FSULE_W = 568, |
| FSULT_D_FSULT_W = 569, |
| FSUNE_D_FSUNE_W = 570, |
| FSUN_D_FSUN_W = 571, |
| FCAF_D_FCAF_W = 572, |
| FCEQ_D_FCEQ_W = 573, |
| FCLE_D_FCLE_W = 574, |
| FCLT_D_FCLT_W = 575, |
| FCNE_D_FCNE_W = 576, |
| FCOR_D_FCOR_W = 577, |
| FCUEQ_D_FCUEQ_W = 578, |
| FCULE_D_FCULE_W = 579, |
| FCULT_D_FCULT_W = 580, |
| FCUNE_D_FCUNE_W = 581, |
| FCUN_D_FCUN_W = 582, |
| FABS_D_FABS_W = 583, |
| FFINT_S_D_FFINT_S_W_FFINT_U_D_FFINT_U_W = 584, |
| FFQL_D_FFQL_W = 585, |
| FFQR_D_FFQR_W = 586, |
| FTINT_S_D_FTINT_S_W_FTINT_U_D_FTINT_U_W = 587, |
| FRINT_D_FRINT_W = 588, |
| FTQ_H_FTQ_W = 589, |
| FTRUNC_S_D_FTRUNC_S_W_FTRUNC_U_D_FTRUNC_U_W = 590, |
| FEXDO_H_FEXDO_W = 591, |
| FEXUPL_D_FEXUPL_W = 592, |
| FEXUPR_D_FEXUPR_W = 593, |
| FCLASS_D_FCLASS_W = 594, |
| FMAX_A_D_FMAX_A_W = 595, |
| FMAX_D_FMAX_W = 596, |
| FMIN_A_D_FMIN_A_W = 597, |
| FMIN_D_FMIN_W = 598, |
| FLOG2_D_FLOG2_W = 599, |
| ILVL_B_ILVL_D_ILVL_H_ILVL_W_ILVR_B_ILVR_D_ILVR_H_ILVR_W = 600, |
| ILVEV_B_ILVEV_D_ILVEV_H_ILVEV_W_ILVOD_B_ILVOD_D_ILVOD_H_ILVOD_W = 601, |
| INSVE_B_INSVE_D_INSVE_H_INSVE_W = 602, |
| SUBS_S_B_SUBS_S_D_SUBS_S_H_SUBS_S_W_SUBS_U_B_SUBS_U_D_SUBS_U_H_SUBS_U_W = 603, |
| SUBSUS_U_B_SUBSUS_U_D_SUBSUS_U_H_SUBSUS_U_W = 604, |
| SUBSUU_S_B_SUBSUU_S_D_SUBSUU_S_H_SUBSUU_S_W = 605, |
| SUBVI_B_SUBVI_D_SUBVI_H_SUBVI_W = 606, |
| SUBV_B_SUBV_D_SUBV_H_SUBV_W = 607, |
| MOD_S_B_MOD_S_D_MOD_S_H_MOD_S_W_MOD_U_B_MOD_U_D_MOD_U_H_MOD_U_W = 608, |
| DIV_S_B_DIV_S_D_DIV_S_H_DIV_S_W_DIV_U_B_DIV_U_D_DIV_U_H_DIV_U_W = 609, |
| HADD_S_D_HADD_S_H_HADD_S_W_HADD_U_D_HADD_U_H_HADD_U_W = 610, |
| HSUB_S_D_HSUB_S_H_HSUB_S_W_HSUB_U_D_HSUB_U_H_HSUB_U_W = 611, |
| MAX_S_B_MAX_S_D_MAX_S_H_MAX_S_W_MIN_S_B_MIN_S_D_MIN_S_H_MIN_S_W = 612, |
| MAX_U_B_MAX_U_D_MAX_U_H_MAX_U_W_MIN_U_B_MIN_U_D_MIN_U_H_MIN_U_W = 613, |
| MAX_A_B_MAX_A_D_MAX_A_H_MAX_A_W_MIN_A_B_MIN_A_D_MIN_A_H_MIN_A_W = 614, |
| MAXI_S_B_MAXI_S_D_MAXI_S_H_MAXI_S_W_MAXI_U_B_MAXI_U_D_MAXI_U_H_MAXI_U_W_MINI_S_B_MINI_S_D_MINI_S_H_MINI_S_W_MINI_U_B_MINI_U_D_MINI_U_H_MINI_U_W = 615, |
| SRAI_B_SRAI_D_SRAI_H_SRAI_W_SRA_B_SRA_D_SRA_H_SRA_W = 616, |
| SRLI_B_SRLI_D_SRLI_H_SRLI_W_SRL_B_SRL_D_SRL_H_SRL_W = 617, |
| SRARI_B_SRARI_D_SRARI_H_SRARI_W_SRAR_B_SRAR_D_SRAR_H_SRAR_W = 618, |
| SRLRI_B_SRLRI_D_SRLRI_H_SRLRI_W_SRLR_B_SRLR_D_SRLR_H_SRLR_W = 619, |
| SLLI_B_SLLI_D_SLLI_H_SLLI_W_SLL_B_SLL_D_SLL_H_SLL_W = 620, |
| PCKEV_B_PCKEV_D_PCKEV_H_PCKEV_W_PCKOD_B_PCKOD_D_PCKOD_H_PCKOD_W = 621, |
| NLOC_B_NLOC_D_NLOC_H_NLOC_W_NLZC_B_NLZC_D_NLZC_H_NLZC_W = 622, |
| FADD_D32_FADD_D64 = 623, |
| FADD_S = 624, |
| FMUL_D32_FMUL_D64 = 625, |
| FMUL_S = 626, |
| FSUB_D32_FSUB_D64 = 627, |
| FSUB_S = 628, |
| TRUNC_L_D64_TRUNC_L_S_TRUNC_W_D32_TRUNC_W_D64_TRUNC_W_S = 629, |
| CVT_D32_S_CVT_D32_W_CVT_D64_L_CVT_D64_S_CVT_D64_W_CVT_L_D64_CVT_L_S_CVT_S_D32_CVT_S_D64_CVT_S_L_CVT_S_W_CVT_W_D32_CVT_W_D64_CVT_W_S = 630, |
| CVT_PS_S64_CVT_S_PL64_CVT_S_PU64 = 631, |
| C_EQ_D32_C_EQ_D64_C_F_D32_C_F_D64_C_LE_D32_C_LE_D64_C_LT_D32_C_LT_D64_C_NGE_D32_C_NGE_D64_C_NGLE_D32_C_NGLE_D64_C_NGL_D32_C_NGL_D64_C_NGT_D32_C_NGT_D64_C_OLE_D32_C_OLE_D64_C_OLT_D32_C_OLT_D64_C_SEQ_D32_C_SEQ_D64_C_SF_D32_C_SF_D64_C_UEQ_D32_C_UEQ_D64_C_ULE_D32_C_ULE_D64_C_ULT_D32_C_ULT_D64_C_UN_D32_C_UN_D64 = 632, |
| C_EQ_S_C_F_S_C_LE_S_C_LT_S_C_NGE_S_C_NGLE_S_C_NGL_S_C_NGT_S_C_OLE_S_C_OLT_S_C_SEQ_S_C_SF_S_C_UEQ_S_C_ULE_S_C_ULT_S_C_UN_S = 633, |
| FCMP_D32_FCMP_D64 = 634, |
| FCMP_S32 = 635, |
| PseudoCVT_D32_W_PseudoCVT_D64_L_PseudoCVT_D64_W_PseudoCVT_S_L_PseudoCVT_S_W = 636, |
| PLL_PS64_PLU_PS64 = 637, |
| FDIV_S = 638, |
| FDIV_D32_FDIV_D64 = 639, |
| FSQRT_S = 640, |
| FSQRT_D32_FSQRT_D64 = 641, |
| FRCP_D_FRCP_W = 642, |
| FRSQRT_D_FRSQRT_W = 643, |
| RECIP_D32_RECIP_D64 = 644, |
| RSQRT_D32_RSQRT_D64 = 645, |
| RECIP_S = 646, |
| RSQRT_S = 647, |
| FMADD_D_FMADD_W = 648, |
| FMSUB_D_FMSUB_W = 649, |
| FDIV_W = 650, |
| FDIV_D = 651, |
| FSQRT_W = 652, |
| FSQRT_D = 653, |
| FMUL_D_FMUL_W = 654, |
| FADD_D_FADD_W = 655, |
| FSUB_D_FSUB_W = 656, |
| DPADD_S_D_DPADD_S_H_DPADD_S_W_DPADD_U_D_DPADD_U_H_DPADD_U_W = 657, |
| DPSUB_S_D_DPSUB_S_H_DPSUB_S_W_DPSUB_U_D_DPSUB_U_H_DPSUB_U_W = 658, |
| DOTP_S_D_DOTP_S_H_DOTP_S_W_DOTP_U_D_DOTP_U_H_DOTP_U_W = 659, |
| MSUBV_B_MSUBV_D_MSUBV_H_MSUBV_W = 660, |
| MADDV_B_MADDV_D_MADDV_H_MADDV_W = 661, |
| MULV_B_MULV_D_MULV_H_MULV_W = 662, |
| MADDR_Q_H_MADDR_Q_W = 663, |
| MADD_Q_H_MADD_Q_W = 664, |
| MSUBR_Q_H_MSUBR_Q_W = 665, |
| MSUB_Q_H_MSUB_Q_W = 666, |
| MULR_Q_H_MULR_Q_W = 667, |
| MUL_Q_H_MUL_Q_W = 668, |
| MADD_D32_MADD_D64 = 669, |
| MADD_S = 670, |
| MSUB_D32_MSUB_D64 = 671, |
| MSUB_S = 672, |
| NMADD_D32_NMADD_D64 = 673, |
| NMADD_S = 674, |
| NMSUB_D32_NMSUB_D64 = 675, |
| NMSUB_S = 676, |
| CTC1 = 677, |
| MTC1_MTC1_D64_BuildPairF64_BuildPairF64_64 = 678, |
| MTHC1_D32_MTHC1_D64 = 679, |
| COPY_U_B_COPY_U_H_COPY_U_W = 680, |
| COPY_S_B_COPY_S_D_COPY_S_H_COPY_S_W = 681, |
| BC1F = 682, |
| BC1FL = 683, |
| BC1T = 684, |
| BC1TL = 685, |
| CFC1 = 686, |
| MFC1_MFC1_D64_ExtractElementF64_ExtractElementF64_64 = 687, |
| MFHC1_D32_MFHC1_D64 = 688, |
| MOVF_I = 689, |
| MOVT_I = 690, |
| SDC1_SDC164 = 691, |
| SDXC1_SDXC164 = 692, |
| SWC1 = 693, |
| SWXC1 = 694, |
| SUXC1_SUXC164 = 695, |
| ST_B_ST_D_ST_H_ST_W = 696, |
| ST_F16 = 697, |
| MOVN_I_D32_MOVN_I_D64 = 698, |
| MOVN_I_S = 699, |
| MOVZ_I_D32_MOVZ_I_D64 = 700, |
| MOVZ_I_S = 701, |
| LDC1_LDC164 = 702, |
| LDXC1_LDXC164 = 703, |
| LWC1 = 704, |
| LWXC1 = 705, |
| LUXC1_LUXC164 = 706, |
| LD_B_LD_D_LD_H_LD_W = 707, |
| LD_F16 = 708, |
| CEIL_L_D64_CEIL_L_S_CEIL_W_D32_CEIL_W_D64_CEIL_W_S = 709, |
| FLOOR_L_D64_FLOOR_L_S_FLOOR_W_D32_FLOOR_W_D64_FLOOR_W_S = 710, |
| ROUND_L_D64_ROUND_L_S_ROUND_W_D32_ROUND_W_D64_ROUND_W_S = 711, |
| ROTRV = 712, |
| ATOMIC_SWAP_I16_POSTRA_ATOMIC_SWAP_I32_POSTRA_ATOMIC_SWAP_I64_POSTRA_ATOMIC_SWAP_I8_POSTRA = 713, |
| ATOMIC_CMP_SWAP_I16_POSTRA_ATOMIC_CMP_SWAP_I32_POSTRA_ATOMIC_CMP_SWAP_I64_POSTRA_ATOMIC_CMP_SWAP_I8_POSTRA = 714, |
| ATOMIC_LOAD_ADD_I16_POSTRA_ATOMIC_LOAD_ADD_I32_POSTRA_ATOMIC_LOAD_ADD_I64_POSTRA_ATOMIC_LOAD_ADD_I8_POSTRA_ATOMIC_LOAD_AND_I16_POSTRA_ATOMIC_LOAD_AND_I32_POSTRA_ATOMIC_LOAD_AND_I64_POSTRA_ATOMIC_LOAD_AND_I8_POSTRA_ATOMIC_LOAD_MAX_I16_POSTRA_ATOMIC_LOAD_MAX_I32_POSTRA_ATOMIC_LOAD_MAX_I64_POSTRA_ATOMIC_LOAD_MAX_I8_POSTRA_ATOMIC_LOAD_MIN_I16_POSTRA_ATOMIC_LOAD_MIN_I32_POSTRA_ATOMIC_LOAD_MIN_I64_POSTRA_ATOMIC_LOAD_MIN_I8_POSTRA_ATOMIC_LOAD_NAND_I16_POSTRA_ATOMIC_LOAD_NAND_I32_POSTRA_ATOMIC_LOAD_NAND_I64_POSTRA_ATOMIC_LOAD_NAND_I8_POSTRA_ATOMIC_LOAD_OR_I16_POSTRA_ATOMIC_LOAD_OR_I32_POSTRA_ATOMIC_LOAD_OR_I64_POSTRA_ATOMIC_LOAD_OR_I8_POSTRA_ATOMIC_LOAD_SUB_I16_POSTRA_ATOMIC_LOAD_SUB_I32_POSTRA_ATOMIC_LOAD_SUB_I64_POSTRA_ATOMIC_LOAD_SUB_I8_POSTRA_ATOMIC_LOAD_UMAX_I16_POSTRA_ATOMIC_LOAD_UMAX_I32_POSTRA_ATOMIC_LOAD_UMAX_I64_POSTRA_ATOMIC_LOAD_UMAX_I8_POSTRA_ATOMIC_LOAD_UMIN_I16_POSTRA_ATOMIC_LOAD_UMIN_I32_POSTRA_ATOMIC_LOAD_UMIN_I64_POSTRA_ATOMIC_LOAD_UMIN_I8_POSTRA_ATOMIC_LOAD_XOR_I16_POSTRA_ATOMIC_LOAD_XOR_I32_POSTRA_ATOMIC_LOAD_XOR_I64_POSTRA_ATOMIC_LOAD_XOR_I8_POSTRA = 715, |
| LEA_ADDiu = 716, |
| ADDIUPC = 717, |
| ALIGN = 718, |
| ALUIPC = 719, |
| AUI = 720, |
| AUIPC = 721, |
| BITSWAP = 722, |
| CLO_R6 = 723, |
| CLZ_R6 = 724, |
| LSA_R6 = 725, |
| SELEQZ_SELNEZ = 726, |
| AddiuRxImmX16_AddiuRxRxImm16_AddiuRxRxImmX16_AddiuRxRyOffMemX16_AddiuRxPcImmX16_AddiuSpImm16_AddiuSpImmX16_AdduRxRyRz16_AndRxRxRy16_CmpRxRy16_CmpiRxImm16_CmpiRxImmX16_LiRxImm16_LiRxImmX16_LiRxImmAlignX16_Move32R16_MoveR3216_Mfhi16_Mflo16_NegRxRy16_NotRxRy16_OrRxRxRy16_SebRx16_SehRx16_SllX16_SllvRxRy16_SltiRxImm16_SltiRxImmX16_SltiuRxImm16_SltiuRxImmX16_SltRxRy16_SltuRxRy16_SravRxRy16_SraX16_SrlvRxRy16_SrlX16_SubuRxRyRz16_XorRxRxRy16 = 727, |
| SltiCCRxImmX16_SltiuCCRxImmX16_SltCCRxRy16_SltuRxRyRz16_SltuCCRxRy16 = 728, |
| Constant32_LwConstant32_GotPrologue16_CONSTPOOL_ENTRY = 729, |
| ADDIUPC_MM_ADDIUR1SP_MM_ADDIUR2_MM_ADDIUS5_MM_ADDIUSP_MM_ADDiu_MM_LEA_ADDiu_MM = 730, |
| ADDU16_MM_ADDu_MM = 731, |
| ADD_MM = 732, |
| ADDi_MM = 733, |
| AND16_MM_ANDI16_MM_AND_MM = 734, |
| ANDi_MM = 735, |
| CLO_MM = 736, |
| CLZ_MM = 737, |
| EXT_MM = 738, |
| INS_MM = 739, |
| LI16_MM = 740, |
| LUi_MM = 741, |
| MOVE16_MM = 742, |
| MOVEP_MM = 743, |
| NOR_MM = 744, |
| NOT16_MM = 745, |
| OR16_MM_OR_MM = 746, |
| ORi_MM = 747, |
| ROTRV_MM = 748, |
| ROTR_MM = 749, |
| SEB_MM = 750, |
| SEH_MM = 751, |
| SLL16_MM_SLL_MM = 752, |
| SLLV_MM = 753, |
| SLT_MM_SLTu_MM = 754, |
| SLTi_MM_SLTiu_MM = 755, |
| SRAV_MM = 756, |
| SRA_MM = 757, |
| SRL16_MM_SRL_MM = 758, |
| SRLV_MM = 759, |
| SSNOP_MM = 760, |
| SUBU16_MM_SUBu_MM = 761, |
| SUB_MM = 762, |
| WSBH_MM = 763, |
| XOR16_MM_XOR_MM = 764, |
| XORi_MM = 765, |
| ADDIUPC_MMR6 = 766, |
| ADDIU_MMR6 = 767, |
| ADDU16_MMR6_ADDU_MMR6 = 768, |
| ADD_MMR6 = 769, |
| ALIGN_MMR6 = 770, |
| ALUIPC_MMR6 = 771, |
| AND16_MMR6_ANDI16_MMR6_AND_MMR6 = 772, |
| ANDI_MMR6 = 773, |
| AUIPC_MMR6 = 774, |
| AUI_MMR6 = 775, |
| BITSWAP_MMR6 = 776, |
| CLO_MMR6 = 777, |
| CLZ_MMR6 = 778, |
| EXT_MMR6 = 779, |
| INS_MMR6 = 780, |
| LI16_MMR6 = 781, |
| LSA_MMR6 = 782, |
| LUI_MMR6 = 783, |
| MOVE16_MMR6 = 784, |
| NOR_MMR6 = 785, |
| NOT16_MMR6 = 786, |
| OR16_MMR6_OR_MMR6 = 787, |
| ORI_MMR6 = 788, |
| SELEQZ_MMR6_SELNEZ_MMR6 = 789, |
| SLL16_MMR6_SLL_MMR6 = 790, |
| SRL16_MMR6 = 791, |
| SSNOP_MMR6 = 792, |
| SUBU16_MMR6_SUBU_MMR6 = 793, |
| SUB_MMR6 = 794, |
| WSBH_MMR6 = 795, |
| XOR16_MMR6_XOR_MMR6 = 796, |
| XORI_MMR6 = 797, |
| AND64_ANDi64 = 798, |
| DEXT64_32 = 799, |
| DSLL64_32 = 800, |
| ORi64 = 801, |
| SEB64 = 802, |
| SEH64 = 803, |
| SLL64_32_SLL64_64 = 804, |
| SLT64_SLTu64 = 805, |
| SLTi64_SLTiu64 = 806, |
| XOR64_XORi64 = 807, |
| DADD = 808, |
| DADDi = 809, |
| DADDiu = 810, |
| DADDu = 811, |
| DCLO = 812, |
| DCLZ = 813, |
| DEXT_DEXTM_DEXTU = 814, |
| DINS_DINSM_DINSU = 815, |
| DROTR = 816, |
| DROTR32 = 817, |
| DROTRV = 818, |
| DSBH = 819, |
| DSHD = 820, |
| DSLL = 821, |
| DSLL32 = 822, |
| DSLLV = 823, |
| DSRA = 824, |
| DSRA32 = 825, |
| DSRAV = 826, |
| DSRL = 827, |
| DSRL32 = 828, |
| DSRLV = 829, |
| DSUB = 830, |
| DSUBu = 831, |
| LEA_ADDiu64 = 832, |
| LUi64 = 833, |
| NOR64 = 834, |
| OR64 = 835, |
| DALIGN = 836, |
| DAHI = 837, |
| DATI = 838, |
| DAUI = 839, |
| DCLO_R6 = 840, |
| DCLZ_R6 = 841, |
| DBITSWAP = 842, |
| DLSA_DLSA_R6 = 843, |
| SELEQZ64_SELNEZ64 = 844, |
| MADD = 845, |
| MADDU = 846, |
| MSUB = 847, |
| MSUBU = 848, |
| PseudoMADD_MM = 849, |
| PseudoMADDU_MM = 850, |
| PseudoMSUB_MM = 851, |
| PseudoMSUBU_MM = 852, |
| PseudoMULT_MM = 853, |
| PseudoMULTu_MM = 854, |
| PseudoMULT = 855, |
| PseudoMULTu = 856, |
| PseudoSDIV_SDIV = 857, |
| PseudoUDIV_UDIV = 858, |
| PseudoMFHI_MM_PseudoMFLO_MM = 859, |
| PseudoMTLOHI_MM = 860, |
| MUH = 861, |
| MUHU = 862, |
| MULU = 863, |
| MUL_R6 = 864, |
| MOD = 865, |
| MODU = 866, |
| MultRxRy16_MultuRxRy16_MultRxRyRz16_MultuRxRyRz16 = 867, |
| DivRxRy16 = 868, |
| DivuRxRy16 = 869, |
| MULT_MM = 870, |
| MULTu_MM = 871, |
| MADD_MM = 872, |
| MADDU_MM = 873, |
| MSUB_MM = 874, |
| MSUBU_MM = 875, |
| MUL_MM = 876, |
| SDIV_MM_SDIV_MM_Pseudo = 877, |
| UDIV_MM_UDIV_MM_Pseudo = 878, |
| MFHI16_MM_MFLO16_MM_MFHI_MM_MFLO_MM = 879, |
| MOVF_I_MM = 880, |
| MOVT_I_MM = 881, |
| MTHI_MM_MTLO_MM = 882, |
| RDHWR_MM = 883, |
| MUHU_MMR6 = 884, |
| MUH_MMR6 = 885, |
| MULU_MMR6 = 886, |
| MUL_MMR6 = 887, |
| MODU_MMR6 = 888, |
| MOD_MMR6 = 889, |
| DIVU_MMR6 = 890, |
| DIV_MMR6 = 891, |
| RDHWR_MMR6 = 892, |
| DMULU = 893, |
| DMULT_PseudoDMULT = 894, |
| DMULTu_PseudoDMULTu = 895, |
| DSDIV_PseudoDSDIV = 896, |
| DUDIV_PseudoDUDIV = 897, |
| MFHI64_MFLO64_PseudoMFHI64_PseudoMFLO64 = 898, |
| PseudoMTLOHI64 = 899, |
| MTHI64_MTLO64 = 900, |
| RDHWR64 = 901, |
| MOVN_I_I64_MOVN_I64_I_MOVN_I64_I64 = 902, |
| MOVZ_I_I64_MOVZ_I64_I_MOVZ_I64_I64 = 903, |
| DMUH = 904, |
| DMUHU = 905, |
| DMUL_R6 = 906, |
| DDIV = 907, |
| DMOD = 908, |
| DDIVU = 909, |
| DMODU = 910, |
| BAL_BR_BLTZAL = 911, |
| BEQ_BNE = 912, |
| BGTZ_BGEZ_BLEZ_BLTZ = 913, |
| J = 914, |
| JR = 915, |
| ERet = 916, |
| BGEZAL = 917, |
| BALC = 918, |
| BEQZALC_BGEZALC_BGTZALC_BLEZALC_BLTZALC_BNEZALC = 919, |
| JIALC = 920, |
| BC = 921, |
| BC2EQZ_BC2NEZ = 922, |
| BEQC_BGEC_BGEUC_BLTC_BLTUC_BNEC_BNVC_BOVC = 923, |
| BEQZC_BGEZC_BGTZC_BLEZC_BLTZC_BNEZC = 924, |
| JIC = 925, |
| JR_HB_R6 = 926, |
| SIGRIE = 927, |
| PseudoIndirectBranchR6_PseudoIndrectHazardBranchR6 = 928, |
| TAILCALLR6REG_TAILCALLHBR6REG = 929, |
| SDBBP_R6 = 930, |
| Bimm16_BimmX16_BeqzRxImm16_BeqzRxImmX16_BnezRxImm16_BnezRxImmX16_Bteqz16_BteqzX16_Btnez16_BtnezX16_JrRa16_JrcRa16_JrcRx16 = 931, |
| BteqzT8CmpX16_BteqzT8CmpiX16_BteqzT8SltX16_BteqzT8SltuX16_BteqzT8SltiX16_BteqzT8SltiuX16_BtnezT8CmpX16_BtnezT8CmpiX16_BtnezT8SltX16_BtnezT8SltuX16_BtnezT8SltiX16_BtnezT8SltiuX16_RetRA16 = 932, |
| Jal16_JalB16 = 933, |
| JumpLinkReg16 = 934, |
| Break16 = 935, |
| SelBeqZ_SelTBteqZCmp_SelTBteqZCmpi_SelTBteqZSlt_SelTBteqZSlti_SelTBteqZSltu_SelTBteqZSltiu_SelBneZ_SelTBtneZCmp_SelTBtneZCmpi_SelTBtneZSlt_SelTBtneZSlti_SelTBtneZSltu_SelTBtneZSltiu = 936, |
| B16_MM_B_MM = 937, |
| BAL_BR_MM = 938, |
| BC1F_MM = 939, |
| BC1T_MM = 940, |
| BEQZ16_MM_BGEZ_MM_BGTZ_MM_BLEZ_MM_BLTZ_MM_BNEZ16_MM = 941, |
| BEQZC_MM_BNEZC_MM = 942, |
| BEQ_MM_BNE_MM = 943, |
| DERET_MM = 944, |
| ERET_MM = 945, |
| JR16_MM_JR_MM = 946, |
| J_MM = 947, |
| B_MM_Pseudo = 948, |
| BGEZALS_MM_BLTZALS_MM = 949, |
| BGEZAL_MM_BLTZAL_MM = 950, |
| JALR16_MM_JALR_MM = 951, |
| JALRS16_MM_JALRS_MM = 952, |
| JALS_MM = 953, |
| JALX_MM_JAL_MM = 954, |
| TAILCALLREG_MM = 955, |
| TAILCALL_MM = 956, |
| PseudoIndirectBranch_MM = 957, |
| BREAK16_MM_BREAK_MM = 958, |
| SDBBP16_MM_SDBBP_MM = 959, |
| SYSCALL_MM = 960, |
| TEQI_MM = 961, |
| TEQ_MM = 962, |
| TGEIU_MM = 963, |
| TGEI_MM = 964, |
| TGEU_MM = 965, |
| TGE_MM = 966, |
| TLTIU_MM = 967, |
| TLTI_MM = 968, |
| TLTU_MM = 969, |
| TLT_MM = 970, |
| TNEI_MM = 971, |
| TNE_MM = 972, |
| TRAP_MM = 973, |
| BC16_MMR6_BC_MMR6 = 974, |
| BC1EQZC_MMR6_BC1NEZC_MMR6 = 975, |
| BC2EQZC_MMR6_BC2NEZC_MMR6 = 976, |
| BEQC_MMR6_BGEC_MMR6_BGEUC_MMR6_BLTC_MMR6_BLTUC_MMR6_BNEC_MMR6_BNVC_MMR6_BOVC_MMR6 = 977, |
| BEQZC16_MMR6_BNEZC16_MMR6 = 978, |
| BEQZC_MMR6_BGEZC_MMR6_BGTZC_MMR6_BLEZC_MMR6_BLTZC_MMR6_BNEZC_MMR6 = 979, |
| DERET_MMR6 = 980, |
| ERETNC_MMR6 = 981, |
| JAL_MMR6 = 982, |
| ERET_MMR6 = 983, |
| JIC_MMR6 = 984, |
| JRADDIUSP_JRCADDIUSP_MMR6 = 985, |
| JRC16_MM = 986, |
| JRC16_MMR6 = 987, |
| SIGRIE_MMR6 = 988, |
| B_MMR6_Pseudo = 989, |
| PseudoIndirectBranch_MMR6 = 990, |
| BALC_MMR6 = 991, |
| BEQZALC_MMR6_BGEZALC_MMR6_BGTZALC_MMR6_BLEZALC_MMR6_BLTZALC_MMR6_BNEZALC_MMR6 = 992, |
| JALRC16_MMR6 = 993, |
| JALRC_HB_MMR6 = 994, |
| JALRC_MMR6 = 995, |
| JIALC_MMR6 = 996, |
| TAILCALLREG_MMR6 = 997, |
| TAILCALL_MMR6 = 998, |
| BREAK16_MMR6_BREAK_MMR6 = 999, |
| SDBBP_MMR6_SDBBP16_MMR6 = 1000, |
| BEQ64_BNE64 = 1001, |
| BGEZ64_BGTZ64_BLEZ64_BLTZ64 = 1002, |
| JR64 = 1003, |
| JALR64_JALR64Pseudo_JALRHB64Pseudo = 1004, |
| JALR_HB64 = 1005, |
| JR_HB64 = 1006, |
| TAILCALLREG64_TAILCALLREGHB64 = 1007, |
| PseudoReturn64 = 1008, |
| BEQC64_BGEC64_BGEUC64_BLTC64_BLTUC64_BNEC64 = 1009, |
| BEQZC64_BGEZC64_BGTZC64_BLEZC64_BLTZC64_BNEZC64 = 1010, |
| JIC64 = 1011, |
| PseudoIndirectBranch64_PseudoIndirectHazardBranch64 = 1012, |
| JIALC64 = 1013, |
| JR_HB64_R6 = 1014, |
| TAILCALL64R6REG_TAILCALLHB64R6REG = 1015, |
| PseudoIndirectBranch64R6_PseudoIndrectHazardBranch64R6 = 1016, |
| EVP = 1017, |
| DVP = 1018, |
| TLBP_MM = 1019, |
| TLBR_MM = 1020, |
| TLBWI_MM = 1021, |
| TLBWR_MM = 1022, |
| DI_MM = 1023, |
| EI_MM = 1024, |
| EHB_MM = 1025, |
| PAUSE_MM = 1026, |
| WAIT_MM = 1027, |
| RDPGPR_MMR6 = 1028, |
| WRPGPR_MMR6 = 1029, |
| TLBINV_MMR6 = 1030, |
| TLBINVF_MMR6 = 1031, |
| MFHC0_MMR6 = 1032, |
| MFC0_MMR6 = 1033, |
| MFHC2_MMR6_MFC2_MMR6 = 1034, |
| MTHC0_MMR6 = 1035, |
| MTC0_MMR6 = 1036, |
| MTHC2_MMR6_MTC2_MMR6 = 1037, |
| EVP_MMR6 = 1038, |
| DVP_MMR6 = 1039, |
| DI_MMR6 = 1040, |
| EI_MMR6 = 1041, |
| EHB_MMR6 = 1042, |
| PAUSE_MMR6 = 1043, |
| WAIT_MMR6 = 1044, |
| DMFC0 = 1045, |
| DMTC0 = 1046, |
| DMFC2 = 1047, |
| DMTC2 = 1048, |
| CFC2_MM = 1049, |
| CTC2_MM = 1050, |
| DMT = 1051, |
| DVPE = 1052, |
| EMT = 1053, |
| EVPE = 1054, |
| MFTR = 1055, |
| MTTR = 1056, |
| YIELD = 1057, |
| FORK = 1058, |
| DMFGC0 = 1059, |
| DMTGC0 = 1060, |
| HYPCALL_MM = 1061, |
| TLBGINVF_MM = 1062, |
| TLBGINV_MM = 1063, |
| TLBGP_MM = 1064, |
| TLBGR_MM = 1065, |
| TLBGWI_MM = 1066, |
| TLBGWR_MM = 1067, |
| MFGC0_MM = 1068, |
| MFHGC0_MM = 1069, |
| MTGC0_MM = 1070, |
| MTHGC0_MM = 1071, |
| SC_MMR6 = 1072, |
| LDC2_R6 = 1073, |
| LL_R6 = 1074, |
| LWC2_R6 = 1075, |
| SWC2_R6 = 1076, |
| SDC2_R6 = 1077, |
| SC_R6 = 1078, |
| PREF_R6 = 1079, |
| CACHE_R6 = 1080, |
| GINVI = 1081, |
| GINVT = 1082, |
| LBE_MM = 1083, |
| LBuE_MM = 1084, |
| LHE_MM = 1085, |
| LHuE_MM = 1086, |
| LWE_MM = 1087, |
| LWLE_MM = 1088, |
| LWRE_MM = 1089, |
| LLE_MM = 1090, |
| SBE_MM = 1091, |
| SB_MM = 1092, |
| SHE_MM = 1093, |
| SWE_MM = 1094, |
| SWLE_MM = 1095, |
| SWRE_MM = 1096, |
| SCE_MM = 1097, |
| PREFE_MM = 1098, |
| CACHEE_MM = 1099, |
| Restore16_RestoreX16 = 1100, |
| LbRxRyOffMemX16 = 1101, |
| LbuRxRyOffMemX16 = 1102, |
| LhRxRyOffMemX16 = 1103, |
| LhuRxRyOffMemX16 = 1104, |
| LwRxRyOffMemX16_LwRxSpImmX16_LwRxPcTcp16_LwRxPcTcpX16 = 1105, |
| Save16_SaveX16 = 1106, |
| SbRxRyOffMemX16 = 1107, |
| ShRxRyOffMemX16 = 1108, |
| SwRxRyOffMemX16_SwRxSpImmX16 = 1109, |
| LBU16_MM_LBu_MM = 1110, |
| LB_MM = 1111, |
| LHU16_MM_LHu_MM = 1112, |
| LH_MM = 1113, |
| LL_MM = 1114, |
| LW16_MM_LWGP_MM_LWSP_MM_LW_MM = 1115, |
| LWL_MM = 1116, |
| LWM16_MM_LWM32_MM = 1117, |
| LWP_MM = 1118, |
| LWR_MM = 1119, |
| LWU_MM = 1120, |
| LWXS_MM = 1121, |
| SB16_MM = 1122, |
| SC_MM = 1123, |
| SH16_MM_SH_MM = 1124, |
| SW16_MM_SWSP_MM_SW_MM = 1125, |
| SWL_MM = 1126, |
| SWM16_MM_SWM32_MM = 1127, |
| SWM_MM = 1128, |
| SWP_MM = 1129, |
| SWR_MM = 1130, |
| PREF_MM_PREFX_MM = 1131, |
| CACHE_MM = 1132, |
| SYNC_MM = 1133, |
| SYNCI_MM = 1134, |
| GINVI_MMR6 = 1135, |
| GINVT_MMR6 = 1136, |
| LBU_MMR6 = 1137, |
| LB_MMR6 = 1138, |
| LDC2_MMR6 = 1139, |
| LL_MMR6 = 1140, |
| LWM16_MMR6 = 1141, |
| LWC2_MMR6 = 1142, |
| LWPC_MMR6 = 1143, |
| LW_MMR6 = 1144, |
| SB16_MMR6_SB_MMR6 = 1145, |
| SDC2_MMR6 = 1146, |
| SH16_MMR6_SH_MMR6 = 1147, |
| SW16_MMR6_SWSP_MMR6_SW_MMR6 = 1148, |
| SWC2_MMR6 = 1149, |
| SWM16_MMR6 = 1150, |
| SYNC_MMR6 = 1151, |
| SYNCI_MMR6 = 1152, |
| PREF_MMR6 = 1153, |
| CACHE_MMR6 = 1154, |
| LD = 1155, |
| LL64_LLD = 1156, |
| LWu = 1157, |
| LB64 = 1158, |
| LBu64 = 1159, |
| LH64 = 1160, |
| LHu64 = 1161, |
| LW64 = 1162, |
| LWL64 = 1163, |
| LWR64 = 1164, |
| LDL = 1165, |
| LDR = 1166, |
| SD = 1167, |
| SC64_SCD = 1168, |
| SB64 = 1169, |
| SH64 = 1170, |
| SW64 = 1171, |
| SWL64 = 1172, |
| SWR64 = 1173, |
| SDL = 1174, |
| SDR = 1175, |
| LWUPC = 1176, |
| LDPC = 1177, |
| LLD_R6 = 1178, |
| LL64_R6 = 1179, |
| SC64_R6 = 1180, |
| SCD_R6 = 1181, |
| CRC32B = 1182, |
| CRC32H = 1183, |
| CRC32W = 1184, |
| CRC32CB = 1185, |
| CRC32CH = 1186, |
| CRC32CW = 1187, |
| CRC32D = 1188, |
| CRC32CD = 1189, |
| BADDu = 1190, |
| BBIT0_BBIT032_BBIT1_BBIT132 = 1191, |
| CINS_CINS32_CINS64_32_CINS_i32 = 1192, |
| DMFC2_OCTEON = 1193, |
| DMTC2_OCTEON = 1194, |
| DPOP_POP = 1195, |
| EXTS_EXTS32 = 1196, |
| MTM0_MTM1_MTM2_MTP0_MTP1_MTP2 = 1197, |
| SEQ_SNE = 1198, |
| SEQi_SNEi = 1199, |
| V3MULU_VMM0_VMULU = 1200, |
| DMUL = 1201, |
| SAA_SAAD = 1202, |
| PseudoTRUNC_W_D_PseudoTRUNC_W_D32_PseudoTRUNC_W_S = 1203, |
| MOVT_I64 = 1204, |
| MOVF_I64 = 1205, |
| MOVZ_I64_S = 1206, |
| MOVN_I64_D64 = 1207, |
| MOVN_I64_S = 1208, |
| MOVZ_I64_D64 = 1209, |
| SELEQZ_S_SELNEZ_S = 1210, |
| SELEQZ_D_SELNEZ_D = 1211, |
| MAX_S_MAXA_S = 1212, |
| MAX_D_MAXA_D = 1213, |
| MIN_S_MINA_D = 1214, |
| MIN_D_MINA_S = 1215, |
| CLASS_S = 1216, |
| CLASS_D = 1217, |
| RINT_S = 1218, |
| RINT_D = 1219, |
| BC1EQZ_BC1NEZ = 1220, |
| SEL_D = 1221, |
| SEL_S = 1222, |
| MADDF_S = 1223, |
| MSUBF_S = 1224, |
| MADDF_D = 1225, |
| MSUBF_D = 1226, |
| MOVF_D32_MM = 1227, |
| MOVF_S_MM = 1228, |
| MOVN_I_D32_MM = 1229, |
| MOVN_I_S_MM = 1230, |
| MOVT_D32_MM = 1231, |
| MOVT_S_MM = 1232, |
| MOVZ_I_D32_MM = 1233, |
| MOVZ_I_S_MM = 1234, |
| CVT_D32_S_MM_CVT_D32_W_MM_CVT_D64_S_MM_CVT_D64_W_MM_CVT_L_D64_MM_CVT_L_S_MM_CVT_S_D32_MM_CVT_S_D64_MM_CVT_S_W_MM_CVT_W_D32_MM_CVT_W_D64_MM_CVT_W_S_MM = 1235, |
| CEIL_W_MM_CEIL_W_S_MM = 1236, |
| FLOOR_W_MM_FLOOR_W_S_MM = 1237, |
| NMADD_S_MM = 1238, |
| NMADD_D32_MM = 1239, |
| NMSUB_S_MM = 1240, |
| NMSUB_D32_MM = 1241, |
| MADD_S_MM = 1242, |
| MADD_D32_MM = 1243, |
| ROUND_W_MM_ROUND_W_S_MM = 1244, |
| TRUNC_W_MM_TRUNC_W_S_MM = 1245, |
| C_F_D32_MM_C_F_D64_MM = 1246, |
| C_F_S_MM = 1247, |
| C_EQ_D32_MM_C_EQ_D64_MM_C_LE_D32_MM_C_LE_D64_MM_C_LT_D32_MM_C_LT_D64_MM_C_SF_D32_MM_C_SF_D64_MM_C_UN_D32_MM_C_UN_D64_MM = 1248, |
| C_EQ_S_MM_C_LE_S_MM_C_LT_S_MM_C_SF_S_MM_C_UN_S_MM = 1249, |
| C_NGE_D32_MM_C_NGE_D64_MM_C_NGL_D32_MM_C_NGL_D64_MM_C_NGT_D32_MM_C_NGT_D64_MM_C_OLE_D32_MM_C_OLE_D64_MM_C_OLT_D32_MM_C_OLT_D64_MM_C_SEQ_D32_MM_C_SEQ_D64_MM_C_UEQ_D32_MM_C_UEQ_D64_MM_C_ULE_D32_MM_C_ULE_D64_MM_C_ULT_D32_MM_C_ULT_D64_MM = 1250, |
| C_NGE_S_MM_C_NGL_S_MM_C_NGT_S_MM_C_OLE_S_MM_C_OLT_S_MM_C_SEQ_S_MM_C_UEQ_S_MM_C_ULE_S_MM_C_ULT_S_MM = 1251, |
| C_NGLE_D32_MM_C_NGLE_D64_MM = 1252, |
| C_NGLE_S_MM = 1253, |
| FCMP_S32_MM = 1254, |
| FCMP_D32_MM = 1255, |
| MFC1_MM = 1256, |
| MFHC1_D32_MM_MFHC1_D64_MM = 1257, |
| MTC1_MM_MTC1_D64_MM = 1258, |
| MTHC1_D32_MM_MTHC1_D64_MM = 1259, |
| FABS_D32_MM_FABS_D64_MM = 1260, |
| FABS_S_MM = 1261, |
| FNEG_D32_MM_FNEG_D64_MM_FNEG_S_MM = 1262, |
| FADD_D32_MM_FADD_D64_MM = 1263, |
| FADD_S_MM = 1264, |
| FMOV_D32_MM_FMOV_D64_MM = 1265, |
| FMOV_S_MM = 1266, |
| FMUL_D32_MM_FMUL_D64_MM = 1267, |
| FMUL_S_MM = 1268, |
| FSUB_D32_MM_FSUB_D64_MM = 1269, |
| FSUB_S_MM = 1270, |
| MSUB_S_MM = 1271, |
| MSUB_D32_MM = 1272, |
| FDIV_S_MM = 1273, |
| FDIV_D32_MM_FDIV_D64_MM = 1274, |
| FSQRT_S_MM = 1275, |
| FSQRT_D32_MM_FSQRT_D64_MM = 1276, |
| RECIP_S_MM_RSQRT_S_MM = 1277, |
| RECIP_D32_MM_RECIP_D64_MM_RSQRT_D32_MM_RSQRT_D64_MM = 1278, |
| SDC1_MM = 1279, |
| SWC1_MM = 1280, |
| SUXC1_MM = 1281, |
| SWXC1_MM = 1282, |
| CFC1_MM = 1283, |
| CTC1_MM = 1284, |
| LDC1_MM = 1285, |
| LUXC1_MM = 1286, |
| LWC1_MM = 1287, |
| LWXC1_MM = 1288, |
| FNEG_S_MMR6 = 1289, |
| CMP_AF_D_MMR6_CMP_EQ_D_MMR6_CMP_LE_D_MMR6_CMP_LT_D_MMR6_CMP_UN_D_MMR6 = 1290, |
| CMP_AF_S_MMR6_CMP_EQ_S_MMR6_CMP_LE_S_MMR6_CMP_LT_S_MMR6_CMP_UN_S_MMR6 = 1291, |
| CMP_SAF_D_MMR6_CMP_SEQ_D_MMR6_CMP_SLE_D_MMR6_CMP_SLT_D_MMR6_CMP_SUN_D_MMR6_CMP_UEQ_D_MMR6_CMP_ULE_D_MMR6_CMP_ULT_D_MMR6 = 1292, |
| CMP_SAF_S_MMR6_CMP_SEQ_S_MMR6_CMP_SLE_S_MMR6_CMP_SLT_S_MMR6_CMP_SUN_S_MMR6_CMP_UEQ_S_MMR6_CMP_ULE_S_MMR6_CMP_ULT_S_MMR6 = 1293, |
| CMP_SUEQ_D_MMR6_CMP_SULE_D_MMR6_CMP_SULT_D_MMR6 = 1294, |
| CMP_SUEQ_S_MMR6_CMP_SULE_S_MMR6_CMP_SULT_S_MMR6 = 1295, |
| CVT_D_L_MMR6_CVT_L_D_MMR6_CVT_L_S_MMR6_CVT_S_L_MMR6_CVT_S_W_MMR6_CVT_W_S_MMR6 = 1296, |
| TRUNC_L_D_MMR6_TRUNC_L_S_MMR6_TRUNC_W_D_MMR6_TRUNC_W_S_MMR6 = 1297, |
| ROUND_L_D_MMR6_ROUND_L_S_MMR6_ROUND_W_D_MMR6_ROUND_W_S_MMR6 = 1298, |
| FLOOR_L_D_MMR6_FLOOR_L_S_MMR6_FLOOR_W_D_MMR6_FLOOR_W_S_MMR6 = 1299, |
| CEIL_L_D_MMR6_CEIL_L_S_MMR6_CEIL_W_D_MMR6_CEIL_W_S_MMR6 = 1300, |
| MFC1_MMR6 = 1301, |
| MTC1_MMR6 = 1302, |
| CLASS_S_MMR6_CLASS_D_MMR6 = 1303, |
| FADD_S_MMR6 = 1304, |
| MAX_D_MMR6 = 1305, |
| MAX_S_MMR6 = 1306, |
| MIN_D_MMR6 = 1307, |
| MIN_S_MMR6 = 1308, |
| MAXA_D_MMR6 = 1309, |
| MAXA_S_MMR6 = 1310, |
| MINA_D_MMR6 = 1311, |
| MINA_S_MMR6 = 1312, |
| SELEQZ_D_MMR6_SELNEZ_D_MMR6 = 1313, |
| SELEQZ_S_MMR6_SELNEZ_S_MMR6 = 1314, |
| SEL_D_MMR6 = 1315, |
| SEL_S_MMR6 = 1316, |
| RINT_S_MMR6_RINT_D_MMR6 = 1317, |
| MADDF_D_MMR6 = 1318, |
| MADDF_S_MMR6 = 1319, |
| MSUBF_D_MMR6 = 1320, |
| MSUBF_S_MMR6 = 1321, |
| FMOV_S_MMR6 = 1322, |
| FMUL_S_MMR6 = 1323, |
| FSUB_S_MMR6 = 1324, |
| FMOV_D_MMR6 = 1325, |
| FDIV_S_MMR6 = 1326, |
| SDC1_D64_MMR6 = 1327, |
| LDC1_D64_MMR6 = 1328, |
| DMFC1 = 1329, |
| DMTC1 = 1330, |
| SWDSP = 1331, |
| LWDSP = 1332, |
| PseudoMTLOHI_DSP = 1333, |
| EXTRV_RS_W = 1334, |
| EXTRV_R_W = 1335, |
| EXTRV_S_H = 1336, |
| EXTRV_W = 1337, |
| EXTR_RS_W = 1338, |
| EXTR_R_W = 1339, |
| EXTR_S_H = 1340, |
| EXTR_W = 1341, |
| INSV = 1342, |
| MTHLIP = 1343, |
| MTHI_DSP = 1344, |
| MTLO_DSP = 1345, |
| ABSQ_S_PH = 1346, |
| ABSQ_S_W = 1347, |
| ADDQ_PH = 1348, |
| ADDQ_S_PH = 1349, |
| ADDQ_S_W = 1350, |
| ADDSC = 1351, |
| ADDU_QB = 1352, |
| ADDU_S_QB = 1353, |
| ADDWC = 1354, |
| BITREV = 1355, |
| BPOSGE32 = 1356, |
| CMPGU_EQ_QB = 1357, |
| CMPGU_LE_QB = 1358, |
| CMPGU_LT_QB = 1359, |
| CMPU_EQ_QB = 1360, |
| CMPU_LE_QB = 1361, |
| CMPU_LT_QB = 1362, |
| CMP_EQ_PH = 1363, |
| CMP_LE_PH = 1364, |
| CMP_LT_PH = 1365, |
| DPAQ_SA_L_W = 1366, |
| DPAQ_S_W_PH = 1367, |
| DPAU_H_QBL = 1368, |
| DPAU_H_QBR = 1369, |
| DPSQ_SA_L_W = 1370, |
| DPSQ_S_W_PH = 1371, |
| DPSU_H_QBL = 1372, |
| DPSU_H_QBR = 1373, |
| EXTPDPV = 1374, |
| EXTPDP = 1375, |
| EXTPV = 1376, |
| EXTP = 1377, |
| LBUX = 1378, |
| LHX = 1379, |
| LWX = 1380, |
| MADDU_DSP = 1381, |
| MADD_DSP = 1382, |
| MAQ_SA_W_PHL = 1383, |
| MAQ_SA_W_PHR = 1384, |
| MAQ_S_W_PHL = 1385, |
| MAQ_S_W_PHR = 1386, |
| MFHI_DSP = 1387, |
| MFLO_DSP = 1388, |
| MODSUB = 1389, |
| MSUBU_DSP = 1390, |
| MSUB_DSP = 1391, |
| MULEQ_S_W_PHL = 1392, |
| MULEQ_S_W_PHR = 1393, |
| MULEU_S_PH_QBL = 1394, |
| MULEU_S_PH_QBR = 1395, |
| MULQ_RS_PH = 1396, |
| MULSAQ_S_W_PH = 1397, |
| MULTU_DSP = 1398, |
| MULT_DSP = 1399, |
| PACKRL_PH = 1400, |
| PICK_PH = 1401, |
| PICK_QB = 1402, |
| PRECEQU_PH_QBLA = 1403, |
| PRECEQU_PH_QBL = 1404, |
| PRECEQU_PH_QBRA = 1405, |
| PRECEQU_PH_QBR = 1406, |
| PRECEQ_W_PHL = 1407, |
| PRECEQ_W_PHR = 1408, |
| PRECEU_PH_QBLA = 1409, |
| PRECEU_PH_QBL = 1410, |
| PRECEU_PH_QBRA = 1411, |
| PRECEU_PH_QBR = 1412, |
| PRECRQU_S_QB_PH = 1413, |
| PRECRQ_PH_W = 1414, |
| PRECRQ_QB_PH = 1415, |
| PRECRQ_RS_PH_W = 1416, |
| RADDU_W_QB = 1417, |
| RDDSP = 1418, |
| REPLV_PH = 1419, |
| REPLV_QB = 1420, |
| REPL_PH = 1421, |
| REPL_QB = 1422, |
| SHILOV = 1423, |
| SHILO = 1424, |
| SHLLV_PH = 1425, |
| SHLLV_QB = 1426, |
| SHLLV_S_PH = 1427, |
| SHLLV_S_W = 1428, |
| SHLL_PH = 1429, |
| SHLL_QB = 1430, |
| SHLL_S_PH = 1431, |
| SHLL_S_W = 1432, |
| SHRAV_PH = 1433, |
| SHRAV_R_PH = 1434, |
| SHRAV_R_W = 1435, |
| SHRA_PH = 1436, |
| SHRA_R_PH = 1437, |
| SHRA_R_W = 1438, |
| SHRLV_QB = 1439, |
| SHRL_QB = 1440, |
| SUBQ_PH = 1441, |
| SUBQ_S_PH = 1442, |
| SUBQ_S_W = 1443, |
| SUBU_QB = 1444, |
| SUBU_S_QB = 1445, |
| WRDSP = 1446, |
| PseudoCMPU_EQ_QB_PseudoCMPU_LE_QB_PseudoCMPU_LT_QB_PseudoCMP_EQ_PH_PseudoCMP_LE_PH_PseudoCMP_LT_PH = 1447, |
| PseudoPICK_PH_PseudoPICK_QB = 1448, |
| ABSQ_S_QB = 1449, |
| ADDQH_PH = 1450, |
| ADDQH_R_PH = 1451, |
| ADDQH_R_W = 1452, |
| ADDQH_W = 1453, |
| ADDUH_QB = 1454, |
| ADDUH_R_QB = 1455, |
| ADDU_PH = 1456, |
| ADDU_S_PH = 1457, |
| APPEND = 1458, |
| BALIGN = 1459, |
| CMPGDU_EQ_QB = 1460, |
| CMPGDU_LE_QB = 1461, |
| CMPGDU_LT_QB = 1462, |
| DPA_W_PH = 1463, |
| DPAQX_SA_W_PH = 1464, |
| DPAQX_S_W_PH = 1465, |
| DPAX_W_PH = 1466, |
| DPS_W_PH = 1467, |
| DPSQX_S_W_PH = 1468, |
| DPSQX_SA_W_PH = 1469, |
| DPSX_W_PH = 1470, |
| MUL_PH = 1471, |
| MUL_S_PH = 1472, |
| MULQ_RS_W = 1473, |
| MULQ_S_PH = 1474, |
| MULQ_S_W = 1475, |
| MULSA_W_PH = 1476, |
| PRECR_QB_PH = 1477, |
| PRECR_SRA_PH_W = 1478, |
| PRECR_SRA_R_PH_W = 1479, |
| PREPEND = 1480, |
| SHRA_QB = 1481, |
| SHRA_R_QB = 1482, |
| SHRAV_QB = 1483, |
| SHRAV_R_QB = 1484, |
| SHRL_PH = 1485, |
| SHRLV_PH = 1486, |
| SUBQH_PH = 1487, |
| SUBQH_R_PH = 1488, |
| SUBQH_W = 1489, |
| SUBQH_R_W = 1490, |
| SUBU_PH = 1491, |
| SUBU_S_PH = 1492, |
| SUBUH_QB = 1493, |
| SUBUH_R_QB = 1494, |
| LWDSP_MM = 1495, |
| SWDSP_MM = 1496, |
| ABSQ_S_PH_MM = 1497, |
| ABSQ_S_W_MM = 1498, |
| ADDQ_PH_MM = 1499, |
| ADDQ_S_PH_MM = 1500, |
| ADDQ_S_W_MM = 1501, |
| ADDSC_MM = 1502, |
| ADDU_QB_MM = 1503, |
| ADDU_S_QB_MM = 1504, |
| ADDWC_MM = 1505, |
| BITREV_MM = 1506, |
| BPOSGE32_MM = 1507, |
| CMPGU_EQ_QB_MM = 1508, |
| CMPGU_LE_QB_MM = 1509, |
| CMPGU_LT_QB_MM = 1510, |
| CMPU_EQ_QB_MM = 1511, |
| CMPU_LE_QB_MM = 1512, |
| CMPU_LT_QB_MM = 1513, |
| CMP_EQ_PH_MM = 1514, |
| CMP_LE_PH_MM = 1515, |
| CMP_LT_PH_MM = 1516, |
| DPAQ_SA_L_W_MM = 1517, |
| DPAQ_S_W_PH_MM = 1518, |
| DPAU_H_QBL_MM = 1519, |
| DPAU_H_QBR_MM = 1520, |
| DPSQ_SA_L_W_MM = 1521, |
| DPSQ_S_W_PH_MM = 1522, |
| DPSU_H_QBL_MM = 1523, |
| DPSU_H_QBR_MM = 1524, |
| EXTPDPV_MM = 1525, |
| EXTPDP_MM = 1526, |
| EXTPV_MM = 1527, |
| EXTP_MM = 1528, |
| EXTRV_RS_W_MM = 1529, |
| EXTRV_R_W_MM = 1530, |
| EXTRV_S_H_MM = 1531, |
| EXTRV_W_MM = 1532, |
| EXTR_RS_W_MM = 1533, |
| EXTR_R_W_MM = 1534, |
| EXTR_S_H_MM = 1535, |
| EXTR_W_MM = 1536, |
| INSV_MM = 1537, |
| LBUX_MM = 1538, |
| LHX_MM = 1539, |
| LWX_MM = 1540, |
| MADDU_DSP_MM = 1541, |
| MADD_DSP_MM = 1542, |
| MAQ_SA_W_PHL_MM = 1543, |
| MAQ_SA_W_PHR_MM = 1544, |
| MAQ_S_W_PHL_MM = 1545, |
| MAQ_S_W_PHR_MM = 1546, |
| MFHI_DSP_MM = 1547, |
| MFLO_DSP_MM = 1548, |
| MODSUB_MM = 1549, |
| MOVEP_MMR6 = 1550, |
| MOVN_I_MM = 1551, |
| MOVZ_I_MM = 1552, |
| MSUBU_DSP_MM = 1553, |
| MSUB_DSP_MM = 1554, |
| MTHI_DSP_MM = 1555, |
| MTHLIP_MM = 1556, |
| MTLO_DSP_MM = 1557, |
| MULEQ_S_W_PHL_MM = 1558, |
| MULEQ_S_W_PHR_MM = 1559, |
| MULEU_S_PH_QBL_MM = 1560, |
| MULEU_S_PH_QBR_MM = 1561, |
| MULQ_RS_PH_MM = 1562, |
| MULSAQ_S_W_PH_MM = 1563, |
| MULTU_DSP_MM = 1564, |
| MULT_DSP_MM = 1565, |
| PACKRL_PH_MM = 1566, |
| PICK_PH_MM = 1567, |
| PICK_QB_MM = 1568, |
| PRECEQU_PH_QBLA_MM = 1569, |
| PRECEQU_PH_QBL_MM = 1570, |
| PRECEQU_PH_QBRA_MM = 1571, |
| PRECEQU_PH_QBR_MM = 1572, |
| PRECEQ_W_PHL_MM = 1573, |
| PRECEQ_W_PHR_MM = 1574, |
| PRECEU_PH_QBLA_MM = 1575, |
| PRECEU_PH_QBL_MM = 1576, |
| PRECEU_PH_QBRA_MM = 1577, |
| PRECEU_PH_QBR_MM = 1578, |
| PRECRQU_S_QB_PH_MM = 1579, |
| PRECRQ_PH_W_MM = 1580, |
| PRECRQ_QB_PH_MM = 1581, |
| PRECRQ_RS_PH_W_MM = 1582, |
| RADDU_W_QB_MM = 1583, |
| RDDSP_MM = 1584, |
| REPLV_PH_MM = 1585, |
| REPLV_QB_MM = 1586, |
| REPL_PH_MM = 1587, |
| REPL_QB_MM = 1588, |
| SHILOV_MM = 1589, |
| SHILO_MM = 1590, |
| SHLLV_PH_MM = 1591, |
| SHLLV_QB_MM = 1592, |
| SHLLV_S_PH_MM = 1593, |
| SHLLV_S_W_MM = 1594, |
| SHLL_PH_MM = 1595, |
| SHLL_QB_MM = 1596, |
| SHLL_S_PH_MM = 1597, |
| SHLL_S_W_MM = 1598, |
| SHRAV_PH_MM = 1599, |
| SHRAV_R_PH_MM = 1600, |
| SHRAV_R_W_MM = 1601, |
| SHRA_PH_MM = 1602, |
| SHRA_R_PH_MM = 1603, |
| SHRA_R_W_MM = 1604, |
| SHRLV_QB_MM = 1605, |
| SHRL_QB_MM = 1606, |
| SUBQ_PH_MM = 1607, |
| SUBQ_S_PH_MM = 1608, |
| SUBQ_S_W_MM = 1609, |
| SUBU_QB_MM = 1610, |
| SUBU_S_QB_MM = 1611, |
| WRDSP_MM = 1612, |
| ABSQ_S_QB_MMR2 = 1613, |
| ADDQH_PH_MMR2 = 1614, |
| ADDQH_R_PH_MMR2 = 1615, |
| ADDQH_R_W_MMR2 = 1616, |
| ADDQH_W_MMR2 = 1617, |
| ADDUH_QB_MMR2 = 1618, |
| ADDUH_R_QB_MMR2 = 1619, |
| ADDU_PH_MMR2 = 1620, |
| ADDU_S_PH_MMR2 = 1621, |
| APPEND_MMR2 = 1622, |
| BALIGN_MMR2 = 1623, |
| CMPGDU_EQ_QB_MMR2 = 1624, |
| CMPGDU_LE_QB_MMR2 = 1625, |
| CMPGDU_LT_QB_MMR2 = 1626, |
| DPA_W_PH_MMR2 = 1627, |
| DPAQX_SA_W_PH_MMR2 = 1628, |
| DPAQX_S_W_PH_MMR2 = 1629, |
| DPAX_W_PH_MMR2 = 1630, |
| DPS_W_PH_MMR2 = 1631, |
| DPSQX_S_W_PH_MMR2 = 1632, |
| DPSQX_SA_W_PH_MMR2 = 1633, |
| DPSX_W_PH_MMR2 = 1634, |
| MUL_PH_MMR2 = 1635, |
| MUL_S_PH_MMR2 = 1636, |
| MULQ_RS_W_MMR2 = 1637, |
| MULQ_S_PH_MMR2 = 1638, |
| MULQ_S_W_MMR2 = 1639, |
| MULSA_W_PH_MMR2 = 1640, |
| PRECR_QB_PH_MMR2 = 1641, |
| PRECR_SRA_PH_W_MMR2 = 1642, |
| PRECR_SRA_R_PH_W_MMR2 = 1643, |
| PREPEND_MMR2 = 1644, |
| SHRA_QB_MMR2 = 1645, |
| SHRA_R_QB_MMR2 = 1646, |
| SHRAV_QB_MMR2 = 1647, |
| SHRAV_R_QB_MMR2 = 1648, |
| SHRL_PH_MMR2 = 1649, |
| SHRLV_PH_MMR2 = 1650, |
| SUBQH_PH_MMR2 = 1651, |
| SUBQH_R_PH_MMR2 = 1652, |
| SUBQH_W_MMR2 = 1653, |
| SUBQH_R_W_MMR2 = 1654, |
| SUBU_PH_MMR2 = 1655, |
| SUBU_S_PH_MMR2 = 1656, |
| SUBUH_QB_MMR2 = 1657, |
| SUBUH_R_QB_MMR2 = 1658, |
| BPOSGE32C_MMR3 = 1659, |
| CMP_F_D = 1660, |
| CMP_F_S = 1661, |
| CMP_SAF_D = 1662, |
| CMP_SAF_S = 1663, |
| CMP_SEQ_D = 1664, |
| CMP_SEQ_S = 1665, |
| CMP_SLE_D = 1666, |
| CMP_SLE_S = 1667, |
| CMP_SLT_D = 1668, |
| CMP_SLT_S = 1669, |
| CMP_SUEQ_D = 1670, |
| CMP_SUEQ_S = 1671, |
| CMP_SULE_D = 1672, |
| CMP_SULE_S = 1673, |
| CMP_SULT_D = 1674, |
| CMP_SULT_S = 1675, |
| CMP_SUN_D = 1676, |
| CMP_SUN_S = 1677, |
| SCHED_LIST_END = 1678 |
| }; |
| } // end namespace Sched |
| } // end namespace Mips |
| } // end namespace llvm |
| #endif // GET_INSTRINFO_SCHED_ENUM |
| |
| #ifdef GET_INSTRINFO_MC_DESC |
| #undef GET_INSTRINFO_MC_DESC |
| namespace llvm { |
| |
| static const MCPhysReg ImplicitList1[] = { Mips::SP, 0 }; |
| static const MCPhysReg ImplicitList2[] = { Mips::AT, 0 }; |
| static const MCPhysReg ImplicitList3[] = { Mips::RA, 0 }; |
| static const MCPhysReg ImplicitList4[] = { Mips::DSPPos, 0 }; |
| static const MCPhysReg ImplicitList5[] = { Mips::V0, Mips::V1, 0 }; |
| static const MCPhysReg ImplicitList6[] = { Mips::HI0, Mips::LO0, 0 }; |
| static const MCPhysReg ImplicitList7[] = { Mips::T8, 0 }; |
| static const MCPhysReg ImplicitList8[] = { Mips::DSPOutFlag20, 0 }; |
| static const MCPhysReg ImplicitList9[] = { Mips::DSPCarry, 0 }; |
| static const MCPhysReg ImplicitList10[] = { Mips::DSPCCond, 0 }; |
| static const MCPhysReg ImplicitList11[] = { Mips::HI0, Mips::LO0, Mips::P0, Mips::P1, Mips::P2, 0 }; |
| static const MCPhysReg ImplicitList12[] = { Mips::HI0_64, Mips::LO0_64, 0 }; |
| static const MCPhysReg ImplicitList13[] = { Mips::DSPOutFlag16_19, 0 }; |
| static const MCPhysReg ImplicitList14[] = { Mips::DSPEFI, 0 }; |
| static const MCPhysReg ImplicitList15[] = { Mips::DSPPos, Mips::DSPEFI, 0 }; |
| static const MCPhysReg ImplicitList16[] = { Mips::DSPOutFlag23, 0 }; |
| static const MCPhysReg ImplicitList17[] = { Mips::FCC0, 0 }; |
| static const MCPhysReg ImplicitList18[] = { Mips::DSPPos, Mips::DSPSCount, 0 }; |
| static const MCPhysReg ImplicitList19[] = { Mips::AC0, 0 }; |
| static const MCPhysReg ImplicitList20[] = { Mips::AC0_64, 0 }; |
| static const MCPhysReg ImplicitList21[] = { Mips::HI0, 0 }; |
| static const MCPhysReg ImplicitList22[] = { Mips::HI0_64, 0 }; |
| static const MCPhysReg ImplicitList23[] = { Mips::LO0, 0 }; |
| static const MCPhysReg ImplicitList24[] = { Mips::LO0_64, 0 }; |
| static const MCPhysReg ImplicitList25[] = { Mips::MPL0, Mips::P0, Mips::P1, Mips::P2, 0 }; |
| static const MCPhysReg ImplicitList26[] = { Mips::MPL1, Mips::P0, Mips::P1, Mips::P2, 0 }; |
| static const MCPhysReg ImplicitList27[] = { Mips::MPL2, Mips::P0, Mips::P1, Mips::P2, 0 }; |
| static const MCPhysReg ImplicitList28[] = { Mips::P0, 0 }; |
| static const MCPhysReg ImplicitList29[] = { Mips::P1, 0 }; |
| static const MCPhysReg ImplicitList30[] = { Mips::P2, 0 }; |
| static const MCPhysReg ImplicitList31[] = { Mips::DSPOutFlag21, 0 }; |
| static const MCPhysReg ImplicitList32[] = { Mips::DSPOutFlag22, 0 }; |
| static const MCPhysReg ImplicitList33[] = { Mips::P0, Mips::P1, Mips::P2, 0 }; |
| static const MCPhysReg ImplicitList34[] = { Mips::MPL1, Mips::MPL2, Mips::P0, Mips::P1, Mips::P2, 0 }; |
| |
| static const MCOperandInfo OperandInfo2[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo3[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; |
| static const MCOperandInfo OperandInfo4[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; |
| static const MCOperandInfo OperandInfo5[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; |
| static const MCOperandInfo OperandInfo6[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; |
| static const MCOperandInfo OperandInfo7[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo8[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; |
| static const MCOperandInfo OperandInfo9[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; |
| static const MCOperandInfo OperandInfo10[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo11[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; |
| static const MCOperandInfo OperandInfo12[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo13[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo14[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, }; |
| static const MCOperandInfo OperandInfo15[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, }; |
| static const MCOperandInfo OperandInfo16[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo17[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo18[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, }; |
| static const MCOperandInfo OperandInfo19[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo20[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, }; |
| static const MCOperandInfo OperandInfo21[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo22[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo23[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, }; |
| static const MCOperandInfo OperandInfo24[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, }; |
| static const MCOperandInfo OperandInfo25[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, }; |
| static const MCOperandInfo OperandInfo26[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, }; |
| static const MCOperandInfo OperandInfo27[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, }; |
| static const MCOperandInfo OperandInfo28[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, }; |
| static const MCOperandInfo OperandInfo29[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, }; |
| static const MCOperandInfo OperandInfo30[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, }; |
| static const MCOperandInfo OperandInfo31[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo32[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, }; |
| static const MCOperandInfo OperandInfo33[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, }; |
| static const MCOperandInfo OperandInfo34[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, }; |
| static const MCOperandInfo OperandInfo35[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo36[] = { { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; |
| static const MCOperandInfo OperandInfo37[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, }; |
| static const MCOperandInfo OperandInfo38[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo39[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo40[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo41[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo42[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo43[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo44[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo45[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo46[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo47[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo48[] = { { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; |
| static const MCOperandInfo OperandInfo49[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; |
| static const MCOperandInfo OperandInfo50[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; |
| static const MCOperandInfo OperandInfo51[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo52[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo53[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo54[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo55[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; |
| static const MCOperandInfo OperandInfo56[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; |
| static const MCOperandInfo OperandInfo57[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo58[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo59[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGRCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo60[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo61[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo62[] = { { Mips::FGRCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo63[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo64[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo65[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo66[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo67[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; |
| static const MCOperandInfo OperandInfo68[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; |
| static const MCOperandInfo OperandInfo69[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo70[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo71[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo72[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo73[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo74[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo75[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo76[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo77[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo78[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo79[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo80[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo81[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo82[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo83[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo84[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo85[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo86[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo87[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo88[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo89[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; |
| static const MCOperandInfo OperandInfo90[] = { { Mips::MSA128F16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; |
| static const MCOperandInfo OperandInfo91[] = { { Mips::ACC128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; |
| static const MCOperandInfo OperandInfo92[] = { { Mips::ACC64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; |
| static const MCOperandInfo OperandInfo93[] = { { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; |
| static const MCOperandInfo OperandInfo94[] = { { Mips::DSPCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; |
| static const MCOperandInfo OperandInfo95[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; |
| static const MCOperandInfo OperandInfo96[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; |
| static const MCOperandInfo OperandInfo97[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; |
| static const MCOperandInfo OperandInfo98[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; |
| static const MCOperandInfo OperandInfo99[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; |
| static const MCOperandInfo OperandInfo100[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; |
| static const MCOperandInfo OperandInfo101[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; |
| static const MCOperandInfo OperandInfo102[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; |
| static const MCOperandInfo OperandInfo103[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo104[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; |
| static const MCOperandInfo OperandInfo105[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo106[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo107[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo108[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo109[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo110[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo111[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::COP0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo112[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo113[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo114[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128F16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo115[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128F16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo116[] = { { Mips::MSA128F16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo117[] = { { Mips::MSA128F16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo118[] = { { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo119[] = { { Mips::COP0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo120[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo121[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo122[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo123[] = { { Mips::DSPCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo124[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo125[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo126[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo127[] = { { Mips::ACC128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo128[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo129[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo130[] = { { Mips::ACC64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, }; |
| static const MCOperandInfo OperandInfo131[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo132[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo133[] = { { Mips::ACC64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo134[] = { { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo135[] = { { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo136[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo137[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo138[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo139[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo140[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo141[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo142[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo143[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo144[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo145[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo146[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo147[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo148[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo149[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; |
| static const MCOperandInfo OperandInfo150[] = { { Mips::GPR32NONZERORegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo151[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo152[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo153[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo154[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo155[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo156[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo157[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo158[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo159[] = { { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo160[] = { { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo161[] = { { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo162[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo163[] = { { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo164[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo165[] = { { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo166[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo167[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo168[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo169[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo170[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo171[] = { { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, }; |
| static const MCOperandInfo OperandInfo172[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, }; |
| static const MCOperandInfo OperandInfo173[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo174[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo175[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsPlusSPRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo176[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo177[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; |
| static const MCOperandInfo OperandInfo178[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; |
| static const MCOperandInfo OperandInfo179[] = { { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; |
| static const MCOperandInfo OperandInfo180[] = { { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; |
| static const MCOperandInfo OperandInfo181[] = { { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; |
| static const MCOperandInfo OperandInfo182[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo183[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo184[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo185[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo186[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo187[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; |
| static const MCOperandInfo OperandInfo188[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; |
| static const MCOperandInfo OperandInfo189[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; |
| static const MCOperandInfo OperandInfo190[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; |
| static const MCOperandInfo OperandInfo191[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, }; |
| static const MCOperandInfo OperandInfo192[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo193[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo194[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo195[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo196[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo197[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo198[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CCRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo199[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo200[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSACtrlRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo201[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo202[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo203[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo204[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo205[] = { { Mips::FGRCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo206[] = { { Mips::FGRCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo207[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo208[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo209[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo210[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo211[] = { { Mips::CCRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo212[] = { { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo213[] = { { Mips::MSACtrlRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo214[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo215[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo216[] = { { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo217[] = { { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo218[] = { { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo219[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo220[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo221[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, }; |
| static const MCOperandInfo OperandInfo222[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::COP0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo223[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo224[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo225[] = { { Mips::COP0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo226[] = { { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo227[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo228[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo229[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo230[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo231[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo232[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo233[] = { { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, }; |
| static const MCOperandInfo OperandInfo234[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo235[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo236[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo237[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo238[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo239[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo240[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo241[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo242[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo243[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo244[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo245[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo246[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo247[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo248[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo249[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo250[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo251[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo252[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo253[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, }; |
| static const MCOperandInfo OperandInfo254[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo255[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo256[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo257[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo258[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo259[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo260[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo261[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo262[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo263[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo264[] = { { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; |
| static const MCOperandInfo OperandInfo265[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo266[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; |
| static const MCOperandInfo OperandInfo267[] = { { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; |
| static const MCOperandInfo OperandInfo268[] = { { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; |
| static const MCOperandInfo OperandInfo269[] = { { Mips::COP3RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; |
| static const MCOperandInfo OperandInfo270[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo271[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo272[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo273[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo274[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, }; |
| static const MCOperandInfo OperandInfo275[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo276[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo277[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; |
| static const MCOperandInfo OperandInfo278[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; |
| static const MCOperandInfo OperandInfo279[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; |
| static const MCOperandInfo OperandInfo280[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; |
| static const MCOperandInfo OperandInfo281[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MipsII::OPERAND_MEM_SIMM9, 0 }, { -1, 0, MipsII::OPERAND_MEM_SIMM9, 0 }, }; |
| static const MCOperandInfo OperandInfo282[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MipsII::OPERAND_MEM_SIMM9, 0 }, { -1, 0, MipsII::OPERAND_MEM_SIMM9, 0 }, }; |
| static const MCOperandInfo OperandInfo283[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; |
| static const MCOperandInfo OperandInfo284[] = { { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; |
| static const MCOperandInfo OperandInfo285[] = { { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 3, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; |
| static const MCOperandInfo OperandInfo286[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, }; |
| static const MCOperandInfo OperandInfo287[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 2, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; |
| static const MCOperandInfo OperandInfo288[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; |
| static const MCOperandInfo OperandInfo289[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 2, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; |
| static const MCOperandInfo OperandInfo290[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo291[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo292[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, }; |
| static const MCOperandInfo OperandInfo293[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo294[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo295[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo296[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo297[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo298[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo299[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo300[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo301[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo302[] = { { Mips::GPRMM16MovePPairFirstRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16MovePPairSecondRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16MovePRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16MovePRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo303[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo304[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, }; |
| static const MCOperandInfo OperandInfo305[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, }; |
| static const MCOperandInfo OperandInfo306[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, }; |
| static const MCOperandInfo OperandInfo307[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, }; |
| static const MCOperandInfo OperandInfo308[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, }; |
| static const MCOperandInfo OperandInfo309[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, }; |
| static const MCOperandInfo OperandInfo310[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, }; |
| static const MCOperandInfo OperandInfo311[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, }; |
| static const MCOperandInfo OperandInfo312[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, }; |
| static const MCOperandInfo OperandInfo313[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, }; |
| static const MCOperandInfo OperandInfo314[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, }; |
| static const MCOperandInfo OperandInfo315[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, }; |
| static const MCOperandInfo OperandInfo316[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, }; |
| static const MCOperandInfo OperandInfo317[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, }; |
| static const MCOperandInfo OperandInfo318[] = { { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo319[] = { { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo320[] = { { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo321[] = { { Mips::HI32DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo322[] = { { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, }; |
| static const MCOperandInfo OperandInfo323[] = { { Mips::LO32DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo324[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo325[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo326[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo327[] = { { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo328[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo329[] = { { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo330[] = { { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, }; |
| static const MCOperandInfo OperandInfo331[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo332[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::HWRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo333[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::HWRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo334[] = { { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo335[] = { { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo336[] = { { Mips::GPRMM16ZeroRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; |
| static const MCOperandInfo OperandInfo337[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; |
| static const MCOperandInfo OperandInfo338[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MipsII::OPERAND_MEM_SIMM9, 0 }, { -1, 0, MipsII::OPERAND_MEM_SIMM9, 0 }, }; |
| static const MCOperandInfo OperandInfo339[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; |
| static const MCOperandInfo OperandInfo340[] = { { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MipsII::OPERAND_MEM_SIMM9, 0 }, { -1, 0, MipsII::OPERAND_MEM_SIMM9, 0 }, }; |
| static const MCOperandInfo OperandInfo341[] = { { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGRCCRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo342[] = { { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, }; |
| static const MCOperandInfo OperandInfo343[] = { { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo344[] = { { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo345[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo346[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo347[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo348[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo349[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo350[] = { { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, }; |
| static const MCOperandInfo OperandInfo351[] = { { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo352[] = { { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo353[] = { { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo354[] = { { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, }; |
| static const MCOperandInfo OperandInfo355[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, }; |
| static const MCOperandInfo OperandInfo356[] = { { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, }; |
| |
| extern const MCInstrDesc MipsInsts[] = { |
| { 0, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #0 = PHI |
| { 1, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1 = INLINEASM |
| { 2, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2 = INLINEASM_BR |
| { 3, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #3 = CFI_INSTRUCTION |
| { 4, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #4 = EH_LABEL |
| { 5, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #5 = GC_LABEL |
| { 6, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #6 = ANNOTATION_LABEL |
| { 7, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #7 = KILL |
| { 8, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr }, // Inst #8 = EXTRACT_SUBREG |
| { 9, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr }, // Inst #9 = INSERT_SUBREG |
| { 10, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #10 = IMPLICIT_DEF |
| { 11, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo6, -1 ,nullptr }, // Inst #11 = SUBREG_TO_REG |
| { 12, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr }, // Inst #12 = COPY_TO_REGCLASS |
| { 13, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #13 = DBG_VALUE |
| { 14, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #14 = DBG_LABEL |
| { 15, 2, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #15 = REG_SEQUENCE |
| { 16, 2, 1, 0, 509, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #16 = COPY |
| { 17, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #17 = BUNDLE |
| { 18, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #18 = LIFETIME_START |
| { 19, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr }, // Inst #19 = LIFETIME_END |
| { 20, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr }, // Inst #20 = STACKMAP |
| { 21, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #21 = FENTRY_CALL |
| { 22, 6, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo9, -1 ,nullptr }, // Inst #22 = PATCHPOINT |
| { 23, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo10, -1 ,nullptr }, // Inst #23 = LOAD_STACK_GUARD |
| { 24, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #24 = STATEPOINT |
| { 25, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr }, // Inst #25 = LOCAL_ESCAPE |
| { 26, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #26 = FAULTING_OP |
| { 27, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #27 = PATCHABLE_OP |
| { 28, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #28 = PATCHABLE_FUNCTION_ENTER |
| { 29, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #29 = PATCHABLE_RET |
| { 30, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #30 = PATCHABLE_FUNCTION_EXIT |
| { 31, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #31 = PATCHABLE_TAIL_CALL |
| { 32, 2, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr }, // Inst #32 = PATCHABLE_EVENT_CALL |
| { 33, 3, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr }, // Inst #33 = PATCHABLE_TYPED_EVENT_CALL |
| { 34, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #34 = ICALL_BRANCH_FUNNEL |
| { 35, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #35 = G_ADD |
| { 36, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #36 = G_SUB |
| { 37, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #37 = G_MUL |
| { 38, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #38 = G_SDIV |
| { 39, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #39 = G_UDIV |
| { 40, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #40 = G_SREM |
| { 41, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #41 = G_UREM |
| { 42, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #42 = G_AND |
| { 43, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #43 = G_OR |
| { 44, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #44 = G_XOR |
| { 45, 1, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #45 = G_IMPLICIT_DEF |
| { 46, 1, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #46 = G_PHI |
| { 47, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #47 = G_FRAME_INDEX |
| { 48, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #48 = G_GLOBAL_VALUE |
| { 49, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #49 = G_EXTRACT |
| { 50, 2, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #50 = G_UNMERGE_VALUES |
| { 51, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr }, // Inst #51 = G_INSERT |
| { 52, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #52 = G_MERGE_VALUES |
| { 53, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #53 = G_BUILD_VECTOR |
| { 54, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #54 = G_BUILD_VECTOR_TRUNC |
| { 55, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #55 = G_CONCAT_VECTORS |
| { 56, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #56 = G_PTRTOINT |
| { 57, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #57 = G_INTTOPTR |
| { 58, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #58 = G_BITCAST |
| { 59, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #59 = G_INTRINSIC_TRUNC |
| { 60, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #60 = G_INTRINSIC_ROUND |
| { 61, 1, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #61 = G_READCYCLECOUNTER |
| { 62, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #62 = G_LOAD |
| { 63, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #63 = G_SEXTLOAD |
| { 64, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #64 = G_ZEXTLOAD |
| { 65, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr }, // Inst #65 = G_INDEXED_LOAD |
| { 66, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr }, // Inst #66 = G_INDEXED_SEXTLOAD |
| { 67, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr }, // Inst #67 = G_INDEXED_ZEXTLOAD |
| { 68, 2, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #68 = G_STORE |
| { 69, 5, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr }, // Inst #69 = G_INDEXED_STORE |
| { 70, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr }, // Inst #70 = G_ATOMIC_CMPXCHG_WITH_SUCCESS |
| { 71, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #71 = G_ATOMIC_CMPXCHG |
| { 72, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr }, // Inst #72 = G_ATOMICRMW_XCHG |
| { 73, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr }, // Inst #73 = G_ATOMICRMW_ADD |
| { 74, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr }, // Inst #74 = G_ATOMICRMW_SUB |
| { 75, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr }, // Inst #75 = G_ATOMICRMW_AND |
| { 76, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr }, // Inst #76 = G_ATOMICRMW_NAND |
| { 77, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr }, // Inst #77 = G_ATOMICRMW_OR |
| { 78, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr }, // Inst #78 = G_ATOMICRMW_XOR |
| { 79, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr }, // Inst #79 = G_ATOMICRMW_MAX |
| { 80, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr }, // Inst #80 = G_ATOMICRMW_MIN |
| { 81, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr }, // Inst #81 = G_ATOMICRMW_UMAX |
| { 82, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr }, // Inst #82 = G_ATOMICRMW_UMIN |
| { 83, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr }, // Inst #83 = G_ATOMICRMW_FADD |
| { 84, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr }, // Inst #84 = G_ATOMICRMW_FSUB |
| { 85, 2, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr }, // Inst #85 = G_FENCE |
| { 86, 2, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #86 = G_BRCOND |
| { 87, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #87 = G_BRINDIRECT |
| { 88, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #88 = G_INTRINSIC |
| { 89, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #89 = G_INTRINSIC_W_SIDE_EFFECTS |
| { 90, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #90 = G_ANYEXT |
| { 91, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #91 = G_TRUNC |
| { 92, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #92 = G_CONSTANT |
| { 93, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #93 = G_FCONSTANT |
| { 94, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr }, // Inst #94 = G_VASTART |
| { 95, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr }, // Inst #95 = G_VAARG |
| { 96, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #96 = G_SEXT |
| { 97, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr }, // Inst #97 = G_SEXT_INREG |
| { 98, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #98 = G_ZEXT |
| { 99, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #99 = G_SHL |
| { 100, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #100 = G_LSHR |
| { 101, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #101 = G_ASHR |
| { 102, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr }, // Inst #102 = G_ICMP |
| { 103, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr }, // Inst #103 = G_FCMP |
| { 104, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #104 = G_SELECT |
| { 105, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #105 = G_UADDO |
| { 106, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr }, // Inst #106 = G_UADDE |
| { 107, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #107 = G_USUBO |
| { 108, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr }, // Inst #108 = G_USUBE |
| { 109, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #109 = G_SADDO |
| { 110, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr }, // Inst #110 = G_SADDE |
| { 111, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #111 = G_SSUBO |
| { 112, 5, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr }, // Inst #112 = G_SSUBE |
| { 113, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #113 = G_UMULO |
| { 114, 4, 2, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr }, // Inst #114 = G_SMULO |
| { 115, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #115 = G_UMULH |
| { 116, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #116 = G_SMULH |
| { 117, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #117 = G_FADD |
| { 118, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #118 = G_FSUB |
| { 119, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #119 = G_FMUL |
| { 120, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo30, -1 ,nullptr }, // Inst #120 = G_FMA |
| { 121, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo30, -1 ,nullptr }, // Inst #121 = G_FMAD |
| { 122, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #122 = G_FDIV |
| { 123, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #123 = G_FREM |
| { 124, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #124 = G_FPOW |
| { 125, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #125 = G_FEXP |
| { 126, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #126 = G_FEXP2 |
| { 127, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #127 = G_FLOG |
| { 128, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #128 = G_FLOG2 |
| { 129, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #129 = G_FLOG10 |
| { 130, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #130 = G_FNEG |
| { 131, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #131 = G_FPEXT |
| { 132, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #132 = G_FPTRUNC |
| { 133, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #133 = G_FPTOSI |
| { 134, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #134 = G_FPTOUI |
| { 135, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #135 = G_SITOFP |
| { 136, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #136 = G_UITOFP |
| { 137, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #137 = G_FABS |
| { 138, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #138 = G_FCOPYSIGN |
| { 139, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #139 = G_FCANONICALIZE |
| { 140, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #140 = G_FMINNUM |
| { 141, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #141 = G_FMAXNUM |
| { 142, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #142 = G_FMINNUM_IEEE |
| { 143, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #143 = G_FMAXNUM_IEEE |
| { 144, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #144 = G_FMINIMUM |
| { 145, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #145 = G_FMAXIMUM |
| { 146, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo27, -1 ,nullptr }, // Inst #146 = G_PTR_ADD |
| { 147, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr }, // Inst #147 = G_PTR_MASK |
| { 148, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #148 = G_SMIN |
| { 149, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #149 = G_SMAX |
| { 150, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #150 = G_UMIN |
| { 151, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr }, // Inst #151 = G_UMAX |
| { 152, 1, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #152 = G_BR |
| { 153, 3, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr }, // Inst #153 = G_BRJT |
| { 154, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr }, // Inst #154 = G_INSERT_VECTOR_ELT |
| { 155, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr }, // Inst #155 = G_EXTRACT_VECTOR_ELT |
| { 156, 4, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr }, // Inst #156 = G_SHUFFLE_VECTOR |
| { 157, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #157 = G_CTTZ |
| { 158, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #158 = G_CTTZ_ZERO_UNDEF |
| { 159, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #159 = G_CTLZ |
| { 160, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #160 = G_CTLZ_ZERO_UNDEF |
| { 161, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #161 = G_CTPOP |
| { 162, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #162 = G_BSWAP |
| { 163, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #163 = G_BITREVERSE |
| { 164, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #164 = G_FCEIL |
| { 165, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #165 = G_FCOS |
| { 166, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #166 = G_FSIN |
| { 167, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #167 = G_FSQRT |
| { 168, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #168 = G_FFLOOR |
| { 169, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #169 = G_FRINT |
| { 170, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr }, // Inst #170 = G_FNEARBYINT |
| { 171, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr }, // Inst #171 = G_ADDRSPACE_CAST |
| { 172, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #172 = G_BLOCK_ADDR |
| { 173, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #173 = G_JUMP_TABLE |
| { 174, 3, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr }, // Inst #174 = G_DYN_STACKALLOC |
| { 175, 2, 1, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr }, // Inst #175 = G_READ_REGISTER |
| { 176, 2, 0, 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr }, // Inst #176 = G_WRITE_REGISTER |
| { 177, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #177 = ABSMacro |
| { 178, 2, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo8, -1 ,nullptr }, // Inst #178 = ADJCALLSTACKDOWN |
| { 179, 2, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo8, -1 ,nullptr }, // Inst #179 = ADJCALLSTACKUP |
| { 180, 3, 1, 4, 545, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #180 = AND_V_D_PSEUDO |
| { 181, 3, 1, 4, 545, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #181 = AND_V_H_PSEUDO |
| { 182, 3, 1, 4, 545, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #182 = AND_V_W_PSEUDO |
| { 183, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #183 = ATOMIC_CMP_SWAP_I16 |
| { 184, 7, 1, 4, 714, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #184 = ATOMIC_CMP_SWAP_I16_POSTRA |
| { 185, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #185 = ATOMIC_CMP_SWAP_I32 |
| { 186, 4, 1, 4, 714, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #186 = ATOMIC_CMP_SWAP_I32_POSTRA |
| { 187, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #187 = ATOMIC_CMP_SWAP_I64 |
| { 188, 4, 1, 4, 714, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #188 = ATOMIC_CMP_SWAP_I64_POSTRA |
| { 189, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #189 = ATOMIC_CMP_SWAP_I8 |
| { 190, 7, 1, 4, 714, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #190 = ATOMIC_CMP_SWAP_I8_POSTRA |
| { 191, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #191 = ATOMIC_LOAD_ADD_I16 |
| { 192, 6, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #192 = ATOMIC_LOAD_ADD_I16_POSTRA |
| { 193, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #193 = ATOMIC_LOAD_ADD_I32 |
| { 194, 3, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #194 = ATOMIC_LOAD_ADD_I32_POSTRA |
| { 195, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #195 = ATOMIC_LOAD_ADD_I64 |
| { 196, 3, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #196 = ATOMIC_LOAD_ADD_I64_POSTRA |
| { 197, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #197 = ATOMIC_LOAD_ADD_I8 |
| { 198, 6, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #198 = ATOMIC_LOAD_ADD_I8_POSTRA |
| { 199, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #199 = ATOMIC_LOAD_AND_I16 |
| { 200, 6, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #200 = ATOMIC_LOAD_AND_I16_POSTRA |
| { 201, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #201 = ATOMIC_LOAD_AND_I32 |
| { 202, 3, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #202 = ATOMIC_LOAD_AND_I32_POSTRA |
| { 203, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #203 = ATOMIC_LOAD_AND_I64 |
| { 204, 3, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #204 = ATOMIC_LOAD_AND_I64_POSTRA |
| { 205, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #205 = ATOMIC_LOAD_AND_I8 |
| { 206, 6, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #206 = ATOMIC_LOAD_AND_I8_POSTRA |
| { 207, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #207 = ATOMIC_LOAD_MAX_I16 |
| { 208, 6, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #208 = ATOMIC_LOAD_MAX_I16_POSTRA |
| { 209, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #209 = ATOMIC_LOAD_MAX_I32 |
| { 210, 3, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #210 = ATOMIC_LOAD_MAX_I32_POSTRA |
| { 211, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #211 = ATOMIC_LOAD_MAX_I64 |
| { 212, 3, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #212 = ATOMIC_LOAD_MAX_I64_POSTRA |
| { 213, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #213 = ATOMIC_LOAD_MAX_I8 |
| { 214, 6, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #214 = ATOMIC_LOAD_MAX_I8_POSTRA |
| { 215, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #215 = ATOMIC_LOAD_MIN_I16 |
| { 216, 6, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #216 = ATOMIC_LOAD_MIN_I16_POSTRA |
| { 217, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #217 = ATOMIC_LOAD_MIN_I32 |
| { 218, 3, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #218 = ATOMIC_LOAD_MIN_I32_POSTRA |
| { 219, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #219 = ATOMIC_LOAD_MIN_I64 |
| { 220, 3, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #220 = ATOMIC_LOAD_MIN_I64_POSTRA |
| { 221, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #221 = ATOMIC_LOAD_MIN_I8 |
| { 222, 6, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #222 = ATOMIC_LOAD_MIN_I8_POSTRA |
| { 223, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #223 = ATOMIC_LOAD_NAND_I16 |
| { 224, 6, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #224 = ATOMIC_LOAD_NAND_I16_POSTRA |
| { 225, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #225 = ATOMIC_LOAD_NAND_I32 |
| { 226, 3, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #226 = ATOMIC_LOAD_NAND_I32_POSTRA |
| { 227, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #227 = ATOMIC_LOAD_NAND_I64 |
| { 228, 3, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #228 = ATOMIC_LOAD_NAND_I64_POSTRA |
| { 229, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #229 = ATOMIC_LOAD_NAND_I8 |
| { 230, 6, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #230 = ATOMIC_LOAD_NAND_I8_POSTRA |
| { 231, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #231 = ATOMIC_LOAD_OR_I16 |
| { 232, 6, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #232 = ATOMIC_LOAD_OR_I16_POSTRA |
| { 233, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #233 = ATOMIC_LOAD_OR_I32 |
| { 234, 3, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #234 = ATOMIC_LOAD_OR_I32_POSTRA |
| { 235, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #235 = ATOMIC_LOAD_OR_I64 |
| { 236, 3, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #236 = ATOMIC_LOAD_OR_I64_POSTRA |
| { 237, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #237 = ATOMIC_LOAD_OR_I8 |
| { 238, 6, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #238 = ATOMIC_LOAD_OR_I8_POSTRA |
| { 239, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #239 = ATOMIC_LOAD_SUB_I16 |
| { 240, 6, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #240 = ATOMIC_LOAD_SUB_I16_POSTRA |
| { 241, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #241 = ATOMIC_LOAD_SUB_I32 |
| { 242, 3, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #242 = ATOMIC_LOAD_SUB_I32_POSTRA |
| { 243, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #243 = ATOMIC_LOAD_SUB_I64 |
| { 244, 3, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #244 = ATOMIC_LOAD_SUB_I64_POSTRA |
| { 245, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #245 = ATOMIC_LOAD_SUB_I8 |
| { 246, 6, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #246 = ATOMIC_LOAD_SUB_I8_POSTRA |
| { 247, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #247 = ATOMIC_LOAD_UMAX_I16 |
| { 248, 6, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #248 = ATOMIC_LOAD_UMAX_I16_POSTRA |
| { 249, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #249 = ATOMIC_LOAD_UMAX_I32 |
| { 250, 3, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #250 = ATOMIC_LOAD_UMAX_I32_POSTRA |
| { 251, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #251 = ATOMIC_LOAD_UMAX_I64 |
| { 252, 3, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #252 = ATOMIC_LOAD_UMAX_I64_POSTRA |
| { 253, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #253 = ATOMIC_LOAD_UMAX_I8 |
| { 254, 6, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #254 = ATOMIC_LOAD_UMAX_I8_POSTRA |
| { 255, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #255 = ATOMIC_LOAD_UMIN_I16 |
| { 256, 6, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #256 = ATOMIC_LOAD_UMIN_I16_POSTRA |
| { 257, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #257 = ATOMIC_LOAD_UMIN_I32 |
| { 258, 3, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #258 = ATOMIC_LOAD_UMIN_I32_POSTRA |
| { 259, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #259 = ATOMIC_LOAD_UMIN_I64 |
| { 260, 3, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #260 = ATOMIC_LOAD_UMIN_I64_POSTRA |
| { 261, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #261 = ATOMIC_LOAD_UMIN_I8 |
| { 262, 6, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #262 = ATOMIC_LOAD_UMIN_I8_POSTRA |
| { 263, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #263 = ATOMIC_LOAD_XOR_I16 |
| { 264, 6, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #264 = ATOMIC_LOAD_XOR_I16_POSTRA |
| { 265, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #265 = ATOMIC_LOAD_XOR_I32 |
| { 266, 3, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #266 = ATOMIC_LOAD_XOR_I32_POSTRA |
| { 267, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #267 = ATOMIC_LOAD_XOR_I64 |
| { 268, 3, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #268 = ATOMIC_LOAD_XOR_I64_POSTRA |
| { 269, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #269 = ATOMIC_LOAD_XOR_I8 |
| { 270, 6, 1, 4, 715, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #270 = ATOMIC_LOAD_XOR_I8_POSTRA |
| { 271, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #271 = ATOMIC_SWAP_I16 |
| { 272, 6, 1, 4, 713, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #272 = ATOMIC_SWAP_I16_POSTRA |
| { 273, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #273 = ATOMIC_SWAP_I32 |
| { 274, 3, 1, 4, 713, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #274 = ATOMIC_SWAP_I32_POSTRA |
| { 275, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #275 = ATOMIC_SWAP_I64 |
| { 276, 3, 1, 4, 713, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #276 = ATOMIC_SWAP_I64_POSTRA |
| { 277, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #277 = ATOMIC_SWAP_I8 |
| { 278, 6, 1, 4, 713, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #278 = ATOMIC_SWAP_I8_POSTRA |
| { 279, 1, 0, 4, 369, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, ImplicitList2, OperandInfo48, -1 ,nullptr }, // Inst #279 = B |
| { 280, 1, 0, 4, 911, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, ImplicitList3, OperandInfo48, -1 ,nullptr }, // Inst #280 = BAL_BR |
| { 281, 1, 0, 4, 938, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, ImplicitList3, OperandInfo48, -1 ,nullptr }, // Inst #281 = BAL_BR_MM |
| { 282, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #282 = BEQLImmMacro |
| { 283, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #283 = BGE |
| { 284, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #284 = BGEImmMacro |
| { 285, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #285 = BGEL |
| { 286, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #286 = BGELImmMacro |
| { 287, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #287 = BGEU |
| { 288, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #288 = BGEUImmMacro |
| { 289, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #289 = BGEUL |
| { 290, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #290 = BGEULImmMacro |
| { 291, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #291 = BGT |
| { 292, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #292 = BGTImmMacro |
| { 293, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #293 = BGTL |
| { 294, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #294 = BGTLImmMacro |
| { 295, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #295 = BGTU |
| { 296, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #296 = BGTUImmMacro |
| { 297, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #297 = BGTUL |
| { 298, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #298 = BGTULImmMacro |
| { 299, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #299 = BLE |
| { 300, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #300 = BLEImmMacro |
| { 301, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #301 = BLEL |
| { 302, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #302 = BLELImmMacro |
| { 303, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #303 = BLEU |
| { 304, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #304 = BLEUImmMacro |
| { 305, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #305 = BLEUL |
| { 306, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #306 = BLEULImmMacro |
| { 307, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #307 = BLT |
| { 308, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #308 = BLTImmMacro |
| { 309, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #309 = BLTL |
| { 310, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #310 = BLTLImmMacro |
| { 311, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #311 = BLTU |
| { 312, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #312 = BLTUImmMacro |
| { 313, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #313 = BLTUL |
| { 314, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #314 = BLTULImmMacro |
| { 315, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #315 = BNELImmMacro |
| { 316, 1, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList4, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #316 = BPOSGE32_PSEUDO |
| { 317, 4, 1, 4, 520, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #317 = BSEL_D_PSEUDO |
| { 318, 4, 1, 4, 520, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #318 = BSEL_FD_PSEUDO |
| { 319, 4, 1, 4, 520, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #319 = BSEL_FW_PSEUDO |
| { 320, 4, 1, 4, 520, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #320 = BSEL_H_PSEUDO |
| { 321, 4, 1, 4, 520, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #321 = BSEL_W_PSEUDO |
| { 322, 1, 0, 4, 937, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, ImplicitList2, OperandInfo48, -1 ,nullptr }, // Inst #322 = B_MM |
| { 323, 1, 0, 4, 989, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #323 = B_MMR6_Pseudo |
| { 324, 1, 0, 4, 948, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #324 = B_MM_Pseudo |
| { 325, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #325 = BeqImm |
| { 326, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #326 = BneImm |
| { 327, 3, 0, 2, 932, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #327 = BteqzT8CmpX16 |
| { 328, 3, 0, 2, 932, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #328 = BteqzT8CmpiX16 |
| { 329, 3, 0, 2, 932, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #329 = BteqzT8SltX16 |
| { 330, 3, 0, 2, 932, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #330 = BteqzT8SltiX16 |
| { 331, 3, 0, 2, 932, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #331 = BteqzT8SltiuX16 |
| { 332, 3, 0, 2, 932, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #332 = BteqzT8SltuX16 |
| { 333, 3, 0, 2, 932, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #333 = BtnezT8CmpX16 |
| { 334, 3, 0, 2, 932, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #334 = BtnezT8CmpiX16 |
| { 335, 3, 0, 2, 932, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #335 = BtnezT8SltX16 |
| { 336, 3, 0, 2, 932, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #336 = BtnezT8SltiX16 |
| { 337, 3, 0, 2, 932, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr }, // Inst #337 = BtnezT8SltiuX16 |
| { 338, 3, 0, 2, 932, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #338 = BtnezT8SltuX16 |
| { 339, 3, 1, 4, 678, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #339 = BuildPairF64 |
| { 340, 3, 1, 4, 678, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #340 = BuildPairF64_64 |
| { 341, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr }, // Inst #341 = CFTC1 |
| { 342, 3, 0, 2, 729, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr }, // Inst #342 = CONSTPOOL_ENTRY |
| { 343, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo60, -1 ,nullptr }, // Inst #343 = COPY_FD_PSEUDO |
| { 344, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #344 = COPY_FW_PSEUDO |
| { 345, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr }, // Inst #345 = CTTC1 |
| { 346, 1, 0, 2, 729, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #346 = Constant32 |
| { 347, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #347 = DMULImmMacro |
| { 348, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #348 = DMULMacro |
| { 349, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #349 = DMULOMacro |
| { 350, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #350 = DMULOUMacro |
| { 351, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #351 = DROL |
| { 352, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #352 = DROLImm |
| { 353, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #353 = DROR |
| { 354, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #354 = DRORImm |
| { 355, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #355 = DSDivIMacro |
| { 356, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #356 = DSDivMacro |
| { 357, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #357 = DSRemIMacro |
| { 358, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #358 = DSRemMacro |
| { 359, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #359 = DUDivIMacro |
| { 360, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #360 = DUDivMacro |
| { 361, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #361 = DURemIMacro |
| { 362, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #362 = DURemMacro |
| { 363, 0, 0, 4, 916, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #363 = ERet |
| { 364, 3, 1, 4, 687, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo67, -1 ,nullptr }, // Inst #364 = ExtractElementF64 |
| { 365, 3, 1, 4, 687, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr }, // Inst #365 = ExtractElementF64_64 |
| { 366, 2, 1, 4, 583, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #366 = FABS_D |
| { 367, 2, 1, 4, 583, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr }, // Inst #367 = FABS_W |
| { 368, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #368 = FEXP2_D_1_PSEUDO |
| { 369, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr }, // Inst #369 = FEXP2_W_1_PSEUDO |
| { 370, 2, 1, 4, 546, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo71, -1 ,nullptr }, // Inst #370 = FILL_FD_PSEUDO |
| { 371, 2, 1, 4, 546, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #371 = FILL_FW_PSEUDO |
| { 372, 4, 2, 2, 729, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #372 = GotPrologue16 |
| { 373, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #373 = INSERT_B_VIDX64_PSEUDO |
| { 374, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #374 = INSERT_B_VIDX_PSEUDO |
| { 375, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo76, -1 ,nullptr }, // Inst #375 = INSERT_D_VIDX64_PSEUDO |
| { 376, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo77, -1 ,nullptr }, // Inst #376 = INSERT_D_VIDX_PSEUDO |
| { 377, 4, 1, 4, 547, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo78, -1 ,nullptr }, // Inst #377 = INSERT_FD_PSEUDO |
| { 378, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo79, -1 ,nullptr }, // Inst #378 = INSERT_FD_VIDX64_PSEUDO |
| { 379, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo80, -1 ,nullptr }, // Inst #379 = INSERT_FD_VIDX_PSEUDO |
| { 380, 4, 1, 4, 547, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #380 = INSERT_FW_PSEUDO |
| { 381, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr }, // Inst #381 = INSERT_FW_VIDX64_PSEUDO |
| { 382, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #382 = INSERT_FW_VIDX_PSEUDO |
| { 383, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr }, // Inst #383 = INSERT_H_VIDX64_PSEUDO |
| { 384, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo85, -1 ,nullptr }, // Inst #384 = INSERT_H_VIDX_PSEUDO |
| { 385, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr }, // Inst #385 = INSERT_W_VIDX64_PSEUDO |
| { 386, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #386 = INSERT_W_VIDX_PSEUDO |
| { 387, 1, 0, 4, 1004, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook), 0x10ULL, nullptr, ImplicitList3, OperandInfo88, -1 ,nullptr }, // Inst #387 = JALR64Pseudo |
| { 388, 1, 0, 4, 1004, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook), 0x10ULL, nullptr, ImplicitList3, OperandInfo88, -1 ,nullptr }, // Inst #388 = JALRHB64Pseudo |
| { 389, 1, 0, 4, 402, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook), 0x10ULL, nullptr, ImplicitList3, OperandInfo51, -1 ,nullptr }, // Inst #389 = JALRHBPseudo |
| { 390, 1, 0, 4, 402, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook), 0x10ULL, nullptr, ImplicitList3, OperandInfo51, -1 ,nullptr }, // Inst #390 = JALRPseudo |
| { 391, 1, 0, 4, 982, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x10ULL, nullptr, ImplicitList3, OperandInfo2, -1 ,nullptr }, // Inst #391 = JAL_MMR6 |
| { 392, 1, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #392 = JalOneReg |
| { 393, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #393 = JalTwoReg |
| { 394, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #394 = LDMacro |
| { 395, 3, 1, 4, 708, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo90, -1 ,nullptr }, // Inst #395 = LD_F16 |
| { 396, 3, 1, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #396 = LOAD_ACC128 |
| { 397, 3, 1, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr }, // Inst #397 = LOAD_ACC64 |
| { 398, 3, 1, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #398 = LOAD_ACC64DSP |
| { 399, 3, 1, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr }, // Inst #399 = LOAD_CCOND_DSP |
| { 400, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #400 = LONG_BRANCH_ADDiu |
| { 401, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #401 = LONG_BRANCH_ADDiu2Op |
| { 402, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr }, // Inst #402 = LONG_BRANCH_DADDiu |
| { 403, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr }, // Inst #403 = LONG_BRANCH_DADDiu2Op |
| { 404, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo98, -1 ,nullptr }, // Inst #404 = LONG_BRANCH_LUi |
| { 405, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo99, -1 ,nullptr }, // Inst #405 = LONG_BRANCH_LUi2Op |
| { 406, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr }, // Inst #406 = LONG_BRANCH_LUi2Op_64 |
| { 407, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr }, // Inst #407 = LWM_MM |
| { 408, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo102, -1 ,nullptr }, // Inst #408 = LoadAddrImm32 |
| { 409, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo103, -1 ,nullptr }, // Inst #409 = LoadAddrImm64 |
| { 410, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #410 = LoadAddrReg32 |
| { 411, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo104, -1 ,nullptr }, // Inst #411 = LoadAddrReg64 |
| { 412, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #412 = LoadImm32 |
| { 413, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo103, -1 ,nullptr }, // Inst #413 = LoadImm64 |
| { 414, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr }, // Inst #414 = LoadImmDoubleFGR |
| { 415, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo107, -1 ,nullptr }, // Inst #415 = LoadImmDoubleFGR_32 |
| { 416, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #416 = LoadImmDoubleGPR |
| { 417, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo108, -1 ,nullptr }, // Inst #417 = LoadImmSingleFGR |
| { 418, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #418 = LoadImmSingleGPR |
| { 419, 3, 1, 2, 729, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr }, // Inst #419 = LwConstant32 |
| { 420, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo110, -1 ,nullptr }, // Inst #420 = MFTACX |
| { 421, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo111, -1 ,nullptr }, // Inst #421 = MFTC0 |
| { 422, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo112, -1 ,nullptr }, // Inst #422 = MFTC1 |
| { 423, 1, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #423 = MFTDSP |
| { 424, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #424 = MFTGPR |
| { 425, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo112, -1 ,nullptr }, // Inst #425 = MFTHC1 |
| { 426, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo110, -1 ,nullptr }, // Inst #426 = MFTHI |
| { 427, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo110, -1 ,nullptr }, // Inst #427 = MFTLO |
| { 428, 2, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x10ULL, ImplicitList5, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #428 = MIPSeh_return32 |
| { 429, 2, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x10ULL, ImplicitList5, nullptr, OperandInfo113, -1 ,nullptr }, // Inst #429 = MIPSeh_return64 |
| { 430, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo114, -1 ,nullptr }, // Inst #430 = MSA_FP_EXTEND_D_PSEUDO |
| { 431, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr }, // Inst #431 = MSA_FP_EXTEND_W_PSEUDO |
| { 432, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo116, -1 ,nullptr }, // Inst #432 = MSA_FP_ROUND_D_PSEUDO |
| { 433, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #433 = MSA_FP_ROUND_W_PSEUDO |
| { 434, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo118, -1 ,nullptr }, // Inst #434 = MTTACX |
| { 435, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr }, // Inst #435 = MTTC0 |
| { 436, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo120, -1 ,nullptr }, // Inst #436 = MTTC1 |
| { 437, 1, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #437 = MTTDSP |
| { 438, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #438 = MTTGPR |
| { 439, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo120, -1 ,nullptr }, // Inst #439 = MTTHC1 |
| { 440, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo118, -1 ,nullptr }, // Inst #440 = MTTHI |
| { 441, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo118, -1 ,nullptr }, // Inst #441 = MTTLO |
| { 442, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #442 = MULImmMacro |
| { 443, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #443 = MULOMacro |
| { 444, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #444 = MULOUMacro |
| { 445, 2, 0, 2, 867, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, ImplicitList6, OperandInfo121, -1 ,nullptr }, // Inst #445 = MultRxRy16 |
| { 446, 3, 1, 2, 867, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, ImplicitList6, OperandInfo122, -1 ,nullptr }, // Inst #446 = MultRxRyRz16 |
| { 447, 2, 0, 2, 867, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, ImplicitList6, OperandInfo121, -1 ,nullptr }, // Inst #447 = MultuRxRy16 |
| { 448, 3, 1, 2, 867, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, ImplicitList6, OperandInfo122, -1 ,nullptr }, // Inst #448 = MultuRxRyRz16 |
| { 449, 0, 0, 4, 368, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #449 = NOP |
| { 450, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #450 = NORImm |
| { 451, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #451 = NORImm64 |
| { 452, 3, 1, 4, 545, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #452 = NOR_V_D_PSEUDO |
| { 453, 3, 1, 4, 545, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #453 = NOR_V_H_PSEUDO |
| { 454, 3, 1, 4, 545, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #454 = NOR_V_W_PSEUDO |
| { 455, 3, 1, 4, 545, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #455 = OR_V_D_PSEUDO |
| { 456, 3, 1, 4, 545, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #456 = OR_V_H_PSEUDO |
| { 457, 3, 1, 4, 545, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #457 = OR_V_W_PSEUDO |
| { 458, 3, 1, 4, 1447, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo123, -1 ,nullptr }, // Inst #458 = PseudoCMPU_EQ_QB |
| { 459, 3, 1, 4, 1447, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo123, -1 ,nullptr }, // Inst #459 = PseudoCMPU_LE_QB |
| { 460, 3, 1, 4, 1447, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo123, -1 ,nullptr }, // Inst #460 = PseudoCMPU_LT_QB |
| { 461, 3, 1, 4, 1447, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo123, -1 ,nullptr }, // Inst #461 = PseudoCMP_EQ_PH |
| { 462, 3, 1, 4, 1447, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo123, -1 ,nullptr }, // Inst #462 = PseudoCMP_LE_PH |
| { 463, 3, 1, 4, 1447, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo123, -1 ,nullptr }, // Inst #463 = PseudoCMP_LT_PH |
| { 464, 2, 1, 4, 636, 0|(1ULL<<MCID::Pseudo), 0x4ULL, nullptr, nullptr, OperandInfo124, -1 ,nullptr }, // Inst #464 = PseudoCVT_D32_W |
| { 465, 2, 1, 4, 636, 0|(1ULL<<MCID::Pseudo), 0x4ULL, nullptr, nullptr, OperandInfo125, -1 ,nullptr }, // Inst #465 = PseudoCVT_D64_L |
| { 466, 2, 1, 4, 636, 0|(1ULL<<MCID::Pseudo), 0x4ULL, nullptr, nullptr, OperandInfo126, -1 ,nullptr }, // Inst #466 = PseudoCVT_D64_W |
| { 467, 2, 1, 4, 636, 0|(1ULL<<MCID::Pseudo), 0x4ULL, nullptr, nullptr, OperandInfo125, -1 ,nullptr }, // Inst #467 = PseudoCVT_S_L |
| { 468, 2, 1, 4, 636, 0|(1ULL<<MCID::Pseudo), 0x4ULL, nullptr, nullptr, OperandInfo120, -1 ,nullptr }, // Inst #468 = PseudoCVT_S_W |
| { 469, 3, 1, 4, 894, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo127, -1 ,nullptr }, // Inst #469 = PseudoDMULT |
| { 470, 3, 1, 4, 895, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo127, -1 ,nullptr }, // Inst #470 = PseudoDMULTu |
| { 471, 3, 1, 4, 896, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo127, -1 ,nullptr }, // Inst #471 = PseudoDSDIV |
| { 472, 3, 1, 4, 897, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo127, -1 ,nullptr }, // Inst #472 = PseudoDUDIV |
| { 473, 7, 2, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo128, -1 ,nullptr }, // Inst #473 = PseudoD_SELECT_I |
| { 474, 7, 2, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo129, -1 ,nullptr }, // Inst #474 = PseudoD_SELECT_I64 |
| { 475, 1, 0, 4, 382, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #475 = PseudoIndirectBranch |
| { 476, 1, 0, 4, 1012, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo88, -1 ,nullptr }, // Inst #476 = PseudoIndirectBranch64 |
| { 477, 1, 0, 4, 1016, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo88, -1 ,nullptr }, // Inst #477 = PseudoIndirectBranch64R6 |
| { 478, 1, 0, 4, 928, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #478 = PseudoIndirectBranchR6 |
| { 479, 1, 0, 4, 957, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #479 = PseudoIndirectBranch_MM |
| { 480, 1, 0, 4, 990, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #480 = PseudoIndirectBranch_MMR6 |
| { 481, 1, 0, 4, 382, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #481 = PseudoIndirectHazardBranch |
| { 482, 1, 0, 4, 1012, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo88, -1 ,nullptr }, // Inst #482 = PseudoIndirectHazardBranch64 |
| { 483, 1, 0, 4, 1016, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo88, -1 ,nullptr }, // Inst #483 = PseudoIndrectHazardBranch64R6 |
| { 484, 1, 0, 4, 928, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #484 = PseudoIndrectHazardBranchR6 |
| { 485, 4, 1, 4, 484, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo130, -1 ,nullptr }, // Inst #485 = PseudoMADD |
| { 486, 4, 1, 4, 485, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo130, -1 ,nullptr }, // Inst #486 = PseudoMADDU |
| { 487, 4, 1, 4, 850, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo130, -1 ,nullptr }, // Inst #487 = PseudoMADDU_MM |
| { 488, 4, 1, 4, 849, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo130, -1 ,nullptr }, // Inst #488 = PseudoMADD_MM |
| { 489, 2, 1, 4, 473, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo131, -1 ,nullptr }, // Inst #489 = PseudoMFHI |
| { 490, 2, 1, 4, 898, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo132, -1 ,nullptr }, // Inst #490 = PseudoMFHI64 |
| { 491, 2, 1, 4, 859, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo131, -1 ,nullptr }, // Inst #491 = PseudoMFHI_MM |
| { 492, 2, 1, 4, 473, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo131, -1 ,nullptr }, // Inst #492 = PseudoMFLO |
| { 493, 2, 1, 4, 898, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo132, -1 ,nullptr }, // Inst #493 = PseudoMFLO64 |
| { 494, 2, 1, 4, 859, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo131, -1 ,nullptr }, // Inst #494 = PseudoMFLO_MM |
| { 495, 4, 1, 4, 486, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo130, -1 ,nullptr }, // Inst #495 = PseudoMSUB |
| { 496, 4, 1, 4, 487, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo130, -1 ,nullptr }, // Inst #496 = PseudoMSUBU |
| { 497, 4, 1, 4, 852, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo130, -1 ,nullptr }, // Inst #497 = PseudoMSUBU_MM |
| { 498, 4, 1, 4, 851, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo130, -1 ,nullptr }, // Inst #498 = PseudoMSUB_MM |
| { 499, 3, 1, 4, 488, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #499 = PseudoMTLOHI |
| { 500, 3, 1, 4, 899, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo127, -1 ,nullptr }, // Inst #500 = PseudoMTLOHI64 |
| { 501, 3, 1, 4, 1333, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr }, // Inst #501 = PseudoMTLOHI_DSP |
| { 502, 3, 1, 4, 860, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #502 = PseudoMTLOHI_MM |
| { 503, 3, 1, 4, 855, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #503 = PseudoMULT |
| { 504, 3, 1, 4, 853, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #504 = PseudoMULT_MM |
| { 505, 3, 1, 4, 856, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #505 = PseudoMULTu |
| { 506, 3, 1, 4, 854, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #506 = PseudoMULTu_MM |
| { 507, 4, 1, 4, 1448, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #507 = PseudoPICK_PH |
| { 508, 4, 1, 4, 1448, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #508 = PseudoPICK_QB |
| { 509, 1, 0, 4, 383, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #509 = PseudoReturn |
| { 510, 1, 0, 4, 1008, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, nullptr, OperandInfo88, -1 ,nullptr }, // Inst #510 = PseudoReturn64 |
| { 511, 3, 1, 4, 857, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #511 = PseudoSDIV |
| { 512, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #512 = PseudoSELECTFP_F_D32 |
| { 513, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #513 = PseudoSELECTFP_F_D64 |
| { 514, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo138, -1 ,nullptr }, // Inst #514 = PseudoSELECTFP_F_I |
| { 515, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #515 = PseudoSELECTFP_F_I64 |
| { 516, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo140, -1 ,nullptr }, // Inst #516 = PseudoSELECTFP_F_S |
| { 517, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo136, -1 ,nullptr }, // Inst #517 = PseudoSELECTFP_T_D32 |
| { 518, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo137, -1 ,nullptr }, // Inst #518 = PseudoSELECTFP_T_D64 |
| { 519, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo138, -1 ,nullptr }, // Inst #519 = PseudoSELECTFP_T_I |
| { 520, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr }, // Inst #520 = PseudoSELECTFP_T_I64 |
| { 521, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo140, -1 ,nullptr }, // Inst #521 = PseudoSELECTFP_T_S |
| { 522, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo141, -1 ,nullptr }, // Inst #522 = PseudoSELECT_D32 |
| { 523, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo142, -1 ,nullptr }, // Inst #523 = PseudoSELECT_D64 |
| { 524, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr }, // Inst #524 = PseudoSELECT_I |
| { 525, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr }, // Inst #525 = PseudoSELECT_I64 |
| { 526, 4, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo145, -1 ,nullptr }, // Inst #526 = PseudoSELECT_S |
| { 527, 3, 1, 4, 1203, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr }, // Inst #527 = PseudoTRUNC_W_D |
| { 528, 3, 1, 4, 1203, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr }, // Inst #528 = PseudoTRUNC_W_D32 |
| { 529, 3, 1, 4, 1203, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo148, -1 ,nullptr }, // Inst #529 = PseudoTRUNC_W_S |
| { 530, 3, 1, 4, 858, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #530 = PseudoUDIV |
| { 531, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #531 = ROL |
| { 532, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #532 = ROLImm |
| { 533, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #533 = ROR |
| { 534, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #534 = RORImm |
| { 535, 0, 0, 4, 377, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #535 = RetRA |
| { 536, 0, 0, 2, 932, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #536 = RetRA16 |
| { 537, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr }, // Inst #537 = SDC1_M1 |
| { 538, 3, 1, 4, 877, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #538 = SDIV_MM_Pseudo |
| { 539, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #539 = SDMacro |
| { 540, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #540 = SDivIMacro |
| { 541, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo150, -1 ,nullptr }, // Inst #541 = SDivMacro |
| { 542, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #542 = SEQIMacro |
| { 543, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #543 = SEQMacro |
| { 544, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #544 = SGE |
| { 545, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #545 = SGEImm |
| { 546, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #546 = SGEImm64 |
| { 547, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #547 = SGEU |
| { 548, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #548 = SGEUImm |
| { 549, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #549 = SGEUImm64 |
| { 550, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #550 = SGTImm |
| { 551, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #551 = SGTImm64 |
| { 552, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #552 = SGTUImm |
| { 553, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #553 = SGTUImm64 |
| { 554, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #554 = SLTImm64 |
| { 555, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #555 = SLTUImm64 |
| { 556, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #556 = SNZ_B_PSEUDO |
| { 557, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo152, -1 ,nullptr }, // Inst #557 = SNZ_D_PSEUDO |
| { 558, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #558 = SNZ_H_PSEUDO |
| { 559, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #559 = SNZ_V_PSEUDO |
| { 560, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #560 = SNZ_W_PSEUDO |
| { 561, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #561 = SRemIMacro |
| { 562, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #562 = SRemMacro |
| { 563, 3, 0, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #563 = STORE_ACC128 |
| { 564, 3, 0, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr }, // Inst #564 = STORE_ACC64 |
| { 565, 3, 0, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr }, // Inst #565 = STORE_ACC64DSP |
| { 566, 3, 0, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr }, // Inst #566 = STORE_CCOND_DSP |
| { 567, 3, 0, 4, 697, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo90, -1 ,nullptr }, // Inst #567 = ST_F16 |
| { 568, 3, 0, 4, 1128, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr }, // Inst #568 = SWM_MM |
| { 569, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #569 = SZ_B_PSEUDO |
| { 570, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo152, -1 ,nullptr }, // Inst #570 = SZ_D_PSEUDO |
| { 571, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr }, // Inst #571 = SZ_H_PSEUDO |
| { 572, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr }, // Inst #572 = SZ_V_PSEUDO |
| { 573, 2, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #573 = SZ_W_PSEUDO |
| { 574, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo104, -1 ,nullptr }, // Inst #574 = SaaAddr |
| { 575, 3, 0, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo104, -1 ,nullptr }, // Inst #575 = SaadAddr |
| { 576, 4, 1, 2, 936, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo155, -1 ,nullptr }, // Inst #576 = SelBeqZ |
| { 577, 4, 1, 2, 936, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo155, -1 ,nullptr }, // Inst #577 = SelBneZ |
| { 578, 5, 1, 2, 936, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr }, // Inst #578 = SelTBteqZCmp |
| { 579, 5, 1, 2, 936, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo157, -1 ,nullptr }, // Inst #579 = SelTBteqZCmpi |
| { 580, 5, 1, 2, 936, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr }, // Inst #580 = SelTBteqZSlt |
| { 581, 5, 1, 2, 936, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo157, -1 ,nullptr }, // Inst #581 = SelTBteqZSlti |
| { 582, 5, 1, 2, 936, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo157, -1 ,nullptr }, // Inst #582 = SelTBteqZSltiu |
| { 583, 5, 1, 2, 936, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr }, // Inst #583 = SelTBteqZSltu |
| { 584, 5, 1, 2, 936, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr }, // Inst #584 = SelTBtneZCmp |
| { 585, 5, 1, 2, 936, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo157, -1 ,nullptr }, // Inst #585 = SelTBtneZCmpi |
| { 586, 5, 1, 2, 936, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr }, // Inst #586 = SelTBtneZSlt |
| { 587, 5, 1, 2, 936, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo157, -1 ,nullptr }, // Inst #587 = SelTBtneZSlti |
| { 588, 5, 1, 2, 936, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo157, -1 ,nullptr }, // Inst #588 = SelTBtneZSltiu |
| { 589, 5, 1, 2, 936, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr }, // Inst #589 = SelTBtneZSltu |
| { 590, 3, 1, 2, 728, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #590 = SltCCRxRy16 |
| { 591, 3, 1, 2, 728, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo158, -1 ,nullptr }, // Inst #591 = SltiCCRxImmX16 |
| { 592, 3, 1, 2, 728, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo158, -1 ,nullptr }, // Inst #592 = SltiuCCRxImmX16 |
| { 593, 3, 1, 2, 728, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #593 = SltuCCRxRy16 |
| { 594, 3, 1, 2, 728, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList7, OperandInfo122, -1 ,nullptr }, // Inst #594 = SltuRxRyRz16 |
| { 595, 1, 0, 4, 379, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo2, -1 ,nullptr }, // Inst #595 = TAILCALL |
| { 596, 1, 0, 4, 1015, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo88, -1 ,nullptr }, // Inst #596 = TAILCALL64R6REG |
| { 597, 1, 0, 4, 1015, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo88, -1 ,nullptr }, // Inst #597 = TAILCALLHB64R6REG |
| { 598, 1, 0, 4, 929, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo51, -1 ,nullptr }, // Inst #598 = TAILCALLHBR6REG |
| { 599, 1, 0, 4, 929, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo51, -1 ,nullptr }, // Inst #599 = TAILCALLR6REG |
| { 600, 1, 0, 4, 380, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo51, -1 ,nullptr }, // Inst #600 = TAILCALLREG |
| { 601, 1, 0, 4, 1007, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo88, -1 ,nullptr }, // Inst #601 = TAILCALLREG64 |
| { 602, 1, 0, 4, 380, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo51, -1 ,nullptr }, // Inst #602 = TAILCALLREGHB |
| { 603, 1, 0, 4, 1007, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo88, -1 ,nullptr }, // Inst #603 = TAILCALLREGHB64 |
| { 604, 1, 0, 4, 955, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo51, -1 ,nullptr }, // Inst #604 = TAILCALLREG_MM |
| { 605, 1, 0, 4, 997, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo51, -1 ,nullptr }, // Inst #605 = TAILCALLREG_MMR6 |
| { 606, 1, 0, 4, 956, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo2, -1 ,nullptr }, // Inst #606 = TAILCALL_MM |
| { 607, 1, 0, 4, 998, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL, nullptr, ImplicitList2, OperandInfo2, -1 ,nullptr }, // Inst #607 = TAILCALL_MMR6 |
| { 608, 0, 0, 4, 397, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #608 = TRAP |
| { 609, 0, 0, 4, 973, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #609 = TRAP_MM |
| { 610, 3, 1, 4, 878, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr }, // Inst #610 = UDIV_MM_Pseudo |
| { 611, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #611 = UDivIMacro |
| { 612, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #612 = UDivMacro |
| { 613, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #613 = URemIMacro |
| { 614, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #614 = URemMacro |
| { 615, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #615 = Ulh |
| { 616, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #616 = Ulhu |
| { 617, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #617 = Ulw |
| { 618, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #618 = Ush |
| { 619, 3, 1, 4, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #619 = Usw |
| { 620, 3, 1, 4, 545, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #620 = XOR_V_D_PSEUDO |
| { 621, 3, 1, 4, 545, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #621 = XOR_V_H_PSEUDO |
| { 622, 3, 1, 4, 545, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #622 = XOR_V_W_PSEUDO |
| { 623, 2, 1, 4, 1346, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo159, -1 ,nullptr }, // Inst #623 = ABSQ_S_PH |
| { 624, 2, 1, 4, 1497, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo159, -1 ,nullptr }, // Inst #624 = ABSQ_S_PH_MM |
| { 625, 2, 1, 4, 1449, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo159, -1 ,nullptr }, // Inst #625 = ABSQ_S_QB |
| { 626, 2, 1, 4, 1613, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo159, -1 ,nullptr }, // Inst #626 = ABSQ_S_QB_MMR2 |
| { 627, 2, 1, 4, 1347, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo38, -1 ,nullptr }, // Inst #627 = ABSQ_S_W |
| { 628, 2, 1, 4, 1498, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo38, -1 ,nullptr }, // Inst #628 = ABSQ_S_W_MM |
| { 629, 3, 1, 4, 491, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #629 = ADD |
| { 630, 2, 1, 4, 717, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #630 = ADDIUPC |
| { 631, 2, 1, 4, 730, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo160, -1 ,nullptr }, // Inst #631 = ADDIUPC_MM |
| { 632, 2, 1, 4, 766, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #632 = ADDIUPC_MMR6 |
| { 633, 2, 1, 2, 730, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo160, -1 ,nullptr }, // Inst #633 = ADDIUR1SP_MM |
| { 634, 3, 1, 2, 730, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr }, // Inst #634 = ADDIUR2_MM |
| { 635, 3, 1, 2, 730, 0, 0x0ULL, nullptr, nullptr, OperandInfo162, -1 ,nullptr }, // Inst #635 = ADDIUS5_MM |
| { 636, 1, 0, 2, 730, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #636 = ADDIUSP_MM |
| { 637, 3, 1, 4, 767, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #637 = ADDIU_MMR6 |
| { 638, 3, 1, 4, 1450, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #638 = ADDQH_PH |
| { 639, 3, 1, 4, 1614, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #639 = ADDQH_PH_MMR2 |
| { 640, 3, 1, 4, 1451, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #640 = ADDQH_R_PH |
| { 641, 3, 1, 4, 1615, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #641 = ADDQH_R_PH_MMR2 |
| { 642, 3, 1, 4, 1452, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #642 = ADDQH_R_W |
| { 643, 3, 1, 4, 1616, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #643 = ADDQH_R_W_MMR2 |
| { 644, 3, 1, 4, 1453, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #644 = ADDQH_W |
| { 645, 3, 1, 4, 1617, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #645 = ADDQH_W_MMR2 |
| { 646, 3, 1, 4, 1348, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, ImplicitList8, OperandInfo163, -1 ,nullptr }, // Inst #646 = ADDQ_PH |
| { 647, 3, 1, 4, 1499, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo163, -1 ,nullptr }, // Inst #647 = ADDQ_PH_MM |
| { 648, 3, 1, 4, 1349, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, ImplicitList8, OperandInfo163, -1 ,nullptr }, // Inst #648 = ADDQ_S_PH |
| { 649, 3, 1, 4, 1500, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, ImplicitList8, OperandInfo163, -1 ,nullptr }, // Inst #649 = ADDQ_S_PH_MM |
| { 650, 3, 1, 4, 1350, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo65, -1 ,nullptr }, // Inst #650 = ADDQ_S_W |
| { 651, 3, 1, 4, 1501, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo65, -1 ,nullptr }, // Inst #651 = ADDQ_S_W_MM |
| { 652, 3, 1, 4, 1351, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList9, OperandInfo65, -1 ,nullptr }, // Inst #652 = ADDSC |
| { 653, 3, 1, 4, 1502, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList9, OperandInfo65, -1 ,nullptr }, // Inst #653 = ADDSC_MM |
| { 654, 3, 1, 4, 534, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #654 = ADDS_A_B |
| { 655, 3, 1, 4, 534, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #655 = ADDS_A_D |
| { 656, 3, 1, 4, 534, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #656 = ADDS_A_H |
| { 657, 3, 1, 4, 534, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #657 = ADDS_A_W |
| { 658, 3, 1, 4, 534, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #658 = ADDS_S_B |
| { 659, 3, 1, 4, 534, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #659 = ADDS_S_D |
| { 660, 3, 1, 4, 534, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #660 = ADDS_S_H |
| { 661, 3, 1, 4, 534, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #661 = ADDS_S_W |
| { 662, 3, 1, 4, 534, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #662 = ADDS_U_B |
| { 663, 3, 1, 4, 534, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #663 = ADDS_U_D |
| { 664, 3, 1, 4, 534, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #664 = ADDS_U_H |
| { 665, 3, 1, 4, 534, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #665 = ADDS_U_W |
| { 666, 3, 1, 2, 731, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo165, -1 ,nullptr }, // Inst #666 = ADDU16_MM |
| { 667, 3, 1, 2, 768, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo165, -1 ,nullptr }, // Inst #667 = ADDU16_MMR6 |
| { 668, 3, 1, 4, 1454, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #668 = ADDUH_QB |
| { 669, 3, 1, 4, 1618, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #669 = ADDUH_QB_MMR2 |
| { 670, 3, 1, 4, 1455, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #670 = ADDUH_R_QB |
| { 671, 3, 1, 4, 1619, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #671 = ADDUH_R_QB_MMR2 |
| { 672, 3, 1, 4, 768, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #672 = ADDU_MMR6 |
| { 673, 3, 1, 4, 1456, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo163, -1 ,nullptr }, // Inst #673 = ADDU_PH |
| { 674, 3, 1, 4, 1620, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo163, -1 ,nullptr }, // Inst #674 = ADDU_PH_MMR2 |
| { 675, 3, 1, 4, 1352, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, ImplicitList8, OperandInfo163, -1 ,nullptr }, // Inst #675 = ADDU_QB |
| { 676, 3, 1, 4, 1503, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo163, -1 ,nullptr }, // Inst #676 = ADDU_QB_MM |
| { 677, 3, 1, 4, 1457, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo163, -1 ,nullptr }, // Inst #677 = ADDU_S_PH |
| { 678, 3, 1, 4, 1621, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo163, -1 ,nullptr }, // Inst #678 = ADDU_S_PH_MMR2 |
| { 679, 3, 1, 4, 1353, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, ImplicitList8, OperandInfo163, -1 ,nullptr }, // Inst #679 = ADDU_S_QB |
| { 680, 3, 1, 4, 1504, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, ImplicitList8, OperandInfo163, -1 ,nullptr }, // Inst #680 = ADDU_S_QB_MM |
| { 681, 3, 1, 4, 535, 0, 0x6ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr }, // Inst #681 = ADDVI_B |
| { 682, 3, 1, 4, 535, 0, 0x6ULL, nullptr, nullptr, OperandInfo167, -1 ,nullptr }, // Inst #682 = ADDVI_D |
| { 683, 3, 1, 4, 535, 0, 0x6ULL, nullptr, nullptr, OperandInfo168, -1 ,nullptr }, // Inst #683 = ADDVI_H |
| { 684, 3, 1, 4, 535, 0, 0x6ULL, nullptr, nullptr, OperandInfo169, -1 ,nullptr }, // Inst #684 = ADDVI_W |
| { 685, 3, 1, 4, 535, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #685 = ADDV_B |
| { 686, 3, 1, 4, 535, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #686 = ADDV_D |
| { 687, 3, 1, 4, 535, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #687 = ADDV_H |
| { 688, 3, 1, 4, 535, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #688 = ADDV_W |
| { 689, 3, 1, 4, 1354, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList9, ImplicitList8, OperandInfo65, -1 ,nullptr }, // Inst #689 = ADDWC |
| { 690, 3, 1, 4, 1505, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList9, ImplicitList8, OperandInfo65, -1 ,nullptr }, // Inst #690 = ADDWC_MM |
| { 691, 3, 1, 4, 533, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #691 = ADD_A_B |
| { 692, 3, 1, 4, 533, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #692 = ADD_A_D |
| { 693, 3, 1, 4, 533, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #693 = ADD_A_H |
| { 694, 3, 1, 4, 533, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #694 = ADD_A_W |
| { 695, 3, 1, 4, 732, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #695 = ADD_MM |
| { 696, 3, 1, 4, 769, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #696 = ADD_MMR6 |
| { 697, 3, 1, 4, 492, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #697 = ADDi |
| { 698, 3, 1, 4, 733, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #698 = ADDi_MM |
| { 699, 3, 1, 4, 493, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #699 = ADDiu |
| { 700, 3, 1, 4, 730, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #700 = ADDiu_MM |
| { 701, 3, 1, 4, 504, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #701 = ADDu |
| { 702, 3, 1, 4, 731, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #702 = ADDu_MM |
| { 703, 4, 1, 4, 718, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo170, -1 ,nullptr }, // Inst #703 = ALIGN |
| { 704, 4, 1, 4, 770, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo170, -1 ,nullptr }, // Inst #704 = ALIGN_MMR6 |
| { 705, 2, 1, 4, 719, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #705 = ALUIPC |
| { 706, 2, 1, 4, 771, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #706 = ALUIPC_MMR6 |
| { 707, 3, 1, 4, 359, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #707 = AND |
| { 708, 3, 1, 2, 734, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #708 = AND16_MM |
| { 709, 3, 1, 2, 772, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #709 = AND16_MMR6 |
| { 710, 3, 1, 4, 798, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #710 = AND64 |
| { 711, 3, 1, 2, 734, 0, 0x0ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr }, // Inst #711 = ANDI16_MM |
| { 712, 3, 1, 2, 772, 0, 0x0ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr }, // Inst #712 = ANDI16_MMR6 |
| { 713, 3, 1, 4, 544, 0, 0x6ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr }, // Inst #713 = ANDI_B |
| { 714, 3, 1, 4, 773, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #714 = ANDI_MMR6 |
| { 715, 3, 1, 4, 734, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #715 = AND_MM |
| { 716, 3, 1, 4, 772, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #716 = AND_MMR6 |
| { 717, 3, 1, 4, 543, 0, 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #717 = AND_V |
| { 718, 3, 1, 4, 494, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #718 = ANDi |
| { 719, 3, 1, 4, 798, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #719 = ANDi64 |
| { 720, 3, 1, 4, 735, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #720 = ANDi_MM |
| { 721, 4, 1, 4, 1458, 0, 0x6ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #721 = APPEND |
| { 722, 4, 1, 4, 1622, 0, 0x6ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #722 = APPEND_MMR2 |
| { 723, 3, 1, 4, 536, 0, 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #723 = ASUB_S_B |
| { 724, 3, 1, 4, 536, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #724 = ASUB_S_D |
| { 725, 3, 1, 4, 536, 0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #725 = ASUB_S_H |
| { 726, 3, 1, 4, 536, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #726 = ASUB_S_W |
| { 727, 3, 1, 4, 536, 0, 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #727 = ASUB_U_B |
| { 728, 3, 1, 4, 536, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #728 = ASUB_U_D |
| { 729, 3, 1, 4, 536, 0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #729 = ASUB_U_H |
| { 730, 3, 1, 4, 536, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #730 = ASUB_U_W |
| { 731, 3, 1, 4, 720, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #731 = AUI |
| { 732, 2, 1, 4, 721, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #732 = AUIPC |
| { 733, 2, 1, 4, 774, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #733 = AUIPC_MMR6 |
| { 734, 3, 1, 4, 775, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #734 = AUI_MMR6 |
| { 735, 3, 1, 4, 537, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #735 = AVER_S_B |
| { 736, 3, 1, 4, 537, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #736 = AVER_S_D |
| { 737, 3, 1, 4, 537, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #737 = AVER_S_H |
| { 738, 3, 1, 4, 537, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #738 = AVER_S_W |
| { 739, 3, 1, 4, 537, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #739 = AVER_U_B |
| { 740, 3, 1, 4, 537, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #740 = AVER_U_D |
| { 741, 3, 1, 4, 537, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #741 = AVER_U_H |
| { 742, 3, 1, 4, 537, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #742 = AVER_U_W |
| { 743, 3, 1, 4, 537, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #743 = AVE_S_B |
| { 744, 3, 1, 4, 537, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #744 = AVE_S_D |
| { 745, 3, 1, 4, 537, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #745 = AVE_S_H |
| { 746, 3, 1, 4, 537, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #746 = AVE_S_W |
| { 747, 3, 1, 4, 537, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #747 = AVE_U_B |
| { 748, 3, 1, 4, 537, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #748 = AVE_U_D |
| { 749, 3, 1, 4, 537, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #749 = AVE_U_H |
| { 750, 3, 1, 4, 537, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #750 = AVE_U_W |
| { 751, 2, 1, 4, 727, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo173, -1 ,nullptr }, // Inst #751 = AddiuRxImmX16 |
| { 752, 2, 1, 4, 727, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo173, -1 ,nullptr }, // Inst #752 = AddiuRxPcImmX16 |
| { 753, 3, 1, 2, 727, 0|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo174, -1 ,nullptr }, // Inst #753 = AddiuRxRxImm16 |
| { 754, 3, 1, 4, 727, 0|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo174, -1 ,nullptr }, // Inst #754 = AddiuRxRxImmX16 |
| { 755, 3, 1, 4, 727, 0, 0x0ULL, nullptr, nullptr, OperandInfo175, -1 ,nullptr }, // Inst #755 = AddiuRxRyOffMemX16 |
| { 756, 1, 0, 2, 727, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo2, -1 ,nullptr }, // Inst #756 = AddiuSpImm16 |
| { 757, 1, 0, 4, 727, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo2, -1 ,nullptr }, // Inst #757 = AddiuSpImmX16 |
| { 758, 3, 1, 2, 727, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #758 = AdduRxRyRz16 |
| { 759, 3, 1, 2, 727, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo176, -1 ,nullptr }, // Inst #759 = AndRxRxRy16 |
| { 760, 1, 0, 2, 937, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList2, OperandInfo48, -1 ,nullptr }, // Inst #760 = B16_MM |
| { 761, 3, 1, 4, 1190, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #761 = BADDu |
| { 762, 1, 0, 4, 370, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList3, OperandInfo48, -1 ,nullptr }, // Inst #762 = BAL |
| { 763, 1, 0, 4, 918, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList3, OperandInfo48, -1 ,nullptr }, // Inst #763 = BALC |
| { 764, 1, 0, 4, 991, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList3, OperandInfo48, -1 ,nullptr }, // Inst #764 = BALC_MMR6 |
| { 765, 4, 1, 4, 1459, 0, 0x6ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #765 = BALIGN |
| { 766, 4, 1, 4, 1623, 0, 0x6ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #766 = BALIGN_MMR2 |
| { 767, 3, 0, 4, 1191, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x2ULL, nullptr, ImplicitList2, OperandInfo177, -1 ,nullptr }, // Inst #767 = BBIT0 |
| { 768, 3, 0, 4, 1191, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x2ULL, nullptr, ImplicitList2, OperandInfo177, -1 ,nullptr }, // Inst #768 = BBIT032 |
| { 769, 3, 0, 4, 1191, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x2ULL, nullptr, ImplicitList2, OperandInfo177, -1 ,nullptr }, // Inst #769 = BBIT1 |
| { 770, 3, 0, 4, 1191, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x2ULL, nullptr, ImplicitList2, OperandInfo177, -1 ,nullptr }, // Inst #770 = BBIT132 |
| { 771, 1, 0, 4, 921, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #771 = BC |
| { 772, 1, 0, 2, 974, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList2, OperandInfo48, -1 ,nullptr }, // Inst #772 = BC16_MMR6 |
| { 773, 2, 0, 4, 1220, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo178, -1 ,nullptr }, // Inst #773 = BC1EQZ |
| { 774, 2, 0, 4, 975, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList2, OperandInfo178, -1 ,nullptr }, // Inst #774 = BC1EQZC_MMR6 |
| { 775, 2, 0, 4, 682, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x45ULL, nullptr, ImplicitList2, OperandInfo179, -1 ,nullptr }, // Inst #775 = BC1F |
| { 776, 2, 0, 4, 683, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x45ULL, nullptr, ImplicitList2, OperandInfo179, -1 ,nullptr }, // Inst #776 = BC1FL |
| { 777, 2, 0, 4, 939, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x45ULL, nullptr, ImplicitList2, OperandInfo179, -1 ,nullptr }, // Inst #777 = BC1F_MM |
| { 778, 2, 0, 4, 1220, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo178, -1 ,nullptr }, // Inst #778 = BC1NEZ |
| { 779, 2, 0, 4, 975, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList2, OperandInfo178, -1 ,nullptr }, // Inst #779 = BC1NEZC_MMR6 |
| { 780, 2, 0, 4, 684, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x45ULL, nullptr, ImplicitList2, OperandInfo179, -1 ,nullptr }, // Inst #780 = BC1T |
| { 781, 2, 0, 4, 685, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x45ULL, nullptr, ImplicitList2, OperandInfo179, -1 ,nullptr }, // Inst #781 = BC1TL |
| { 782, 2, 0, 4, 940, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x45ULL, nullptr, ImplicitList2, OperandInfo179, -1 ,nullptr }, // Inst #782 = BC1T_MM |
| { 783, 2, 0, 4, 922, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #783 = BC2EQZ |
| { 784, 2, 0, 4, 976, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList2, OperandInfo180, -1 ,nullptr }, // Inst #784 = BC2EQZC_MMR6 |
| { 785, 2, 0, 4, 922, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr }, // Inst #785 = BC2NEZ |
| { 786, 2, 0, 4, 976, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList2, OperandInfo180, -1 ,nullptr }, // Inst #786 = BC2NEZC_MMR6 |
| { 787, 3, 1, 4, 516, 0, 0x6ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr }, // Inst #787 = BCLRI_B |
| { 788, 3, 1, 4, 516, 0, 0x6ULL, nullptr, nullptr, OperandInfo167, -1 ,nullptr }, // Inst #788 = BCLRI_D |
| { 789, 3, 1, 4, 516, 0, 0x6ULL, nullptr, nullptr, OperandInfo168, -1 ,nullptr }, // Inst #789 = BCLRI_H |
| { 790, 3, 1, 4, 516, 0, 0x6ULL, nullptr, nullptr, OperandInfo169, -1 ,nullptr }, // Inst #790 = BCLRI_W |
| { 791, 3, 1, 4, 516, 0, 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #791 = BCLR_B |
| { 792, 3, 1, 4, 516, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #792 = BCLR_D |
| { 793, 3, 1, 4, 516, 0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #793 = BCLR_H |
| { 794, 3, 1, 4, 516, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #794 = BCLR_W |
| { 795, 1, 0, 4, 974, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x16ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #795 = BC_MMR6 |
| { 796, 3, 0, 4, 912, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo50, -1 ,nullptr }, // Inst #796 = BEQ |
| { 797, 3, 0, 4, 1001, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo97, -1 ,nullptr }, // Inst #797 = BEQ64 |
| { 798, 3, 0, 4, 923, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo50, -1 ,nullptr }, // Inst #798 = BEQC |
| { 799, 3, 0, 4, 1009, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo97, -1 ,nullptr }, // Inst #799 = BEQC64 |
| { 800, 3, 0, 4, 977, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList2, OperandInfo50, -1 ,nullptr }, // Inst #800 = BEQC_MMR6 |
| { 801, 3, 0, 4, 372, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList2, OperandInfo50, -1 ,nullptr }, // Inst #801 = BEQL |
| { 802, 2, 0, 2, 941, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList2, OperandInfo181, -1 ,nullptr }, // Inst #802 = BEQZ16_MM |
| { 803, 2, 0, 4, 919, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList3, OperandInfo99, -1 ,nullptr }, // Inst #803 = BEQZALC |
| { 804, 2, 0, 4, 992, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList3, OperandInfo99, -1 ,nullptr }, // Inst #804 = BEQZALC_MMR6 |
| { 805, 2, 0, 4, 924, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo99, -1 ,nullptr }, // Inst #805 = BEQZC |
| { 806, 2, 0, 2, 978, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList2, OperandInfo181, -1 ,nullptr }, // Inst #806 = BEQZC16_MMR6 |
| { 807, 2, 0, 4, 1010, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo100, -1 ,nullptr }, // Inst #807 = BEQZC64 |
| { 808, 2, 0, 4, 942, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, ImplicitList2, OperandInfo99, -1 ,nullptr }, // Inst #808 = BEQZC_MM |
| { 809, 2, 0, 4, 979, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x36ULL, nullptr, ImplicitList2, OperandInfo99, -1 ,nullptr }, // Inst #809 = BEQZC_MMR6 |
| { 810, 3, 0, 4, 943, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo50, -1 ,nullptr }, // Inst #810 = BEQ_MM |
| { 811, 3, 0, 4, 923, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo50, -1 ,nullptr }, // Inst #811 = BGEC |
| { 812, 3, 0, 4, 1009, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo97, -1 ,nullptr }, // Inst #812 = BGEC64 |
| { 813, 3, 0, 4, 977, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList2, OperandInfo50, -1 ,nullptr }, // Inst #813 = BGEC_MMR6 |
| { 814, 3, 0, 4, 923, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo50, -1 ,nullptr }, // Inst #814 = BGEUC |
| { 815, 3, 0, 4, 1009, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo97, -1 ,nullptr }, // Inst #815 = BGEUC64 |
| { 816, 3, 0, 4, 977, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList2, OperandInfo50, -1 ,nullptr }, // Inst #816 = BGEUC_MMR6 |
| { 817, 2, 0, 4, 913, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo99, -1 ,nullptr }, // Inst #817 = BGEZ |
| { 818, 2, 0, 4, 1002, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo100, -1 ,nullptr }, // Inst #818 = BGEZ64 |
| { 819, 2, 0, 4, 917, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList3, OperandInfo99, -1 ,nullptr }, // Inst #819 = BGEZAL |
| { 820, 2, 0, 4, 919, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList3, OperandInfo99, -1 ,nullptr }, // Inst #820 = BGEZALC |
| { 821, 2, 0, 4, 992, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList3, OperandInfo99, -1 ,nullptr }, // Inst #821 = BGEZALC_MMR6 |
| { 822, 2, 0, 4, 371, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList3, OperandInfo99, -1 ,nullptr }, // Inst #822 = BGEZALL |
| { 823, 2, 0, 4, 949, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, ImplicitList3, OperandInfo99, -1 ,nullptr }, // Inst #823 = BGEZALS_MM |
| { 824, 2, 0, 4, 950, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList3, OperandInfo99, -1 ,nullptr }, // Inst #824 = BGEZAL_MM |
| { 825, 2, 0, 4, 924, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo99, -1 ,nullptr }, // Inst #825 = BGEZC |
| { 826, 2, 0, 4, 1010, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo100, -1 ,nullptr }, // Inst #826 = BGEZC64 |
| { 827, 2, 0, 4, 979, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList2, OperandInfo99, -1 ,nullptr }, // Inst #827 = BGEZC_MMR6 |
| { 828, 2, 0, 4, 373, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList2, OperandInfo99, -1 ,nullptr }, // Inst #828 = BGEZL |
| { 829, 2, 0, 4, 941, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo99, -1 ,nullptr }, // Inst #829 = BGEZ_MM |
| { 830, 2, 0, 4, 913, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo99, -1 ,nullptr }, // Inst #830 = BGTZ |
| { 831, 2, 0, 4, 1002, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo100, -1 ,nullptr }, // Inst #831 = BGTZ64 |
| { 832, 2, 0, 4, 919, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList3, OperandInfo99, -1 ,nullptr }, // Inst #832 = BGTZALC |
| { 833, 2, 0, 4, 992, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList3, OperandInfo99, -1 ,nullptr }, // Inst #833 = BGTZALC_MMR6 |
| { 834, 2, 0, 4, 924, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo99, -1 ,nullptr }, // Inst #834 = BGTZC |
| { 835, 2, 0, 4, 1010, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo100, -1 ,nullptr }, // Inst #835 = BGTZC64 |
| { 836, 2, 0, 4, 979, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList2, OperandInfo99, -1 ,nullptr }, // Inst #836 = BGTZC_MMR6 |
| { 837, 2, 0, 4, 373, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList2, OperandInfo99, -1 ,nullptr }, // Inst #837 = BGTZL |
| { 838, 2, 0, 4, 941, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo99, -1 ,nullptr }, // Inst #838 = BGTZ_MM |
| { 839, 4, 1, 4, 511, 0, 0x6ULL, nullptr, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #839 = BINSLI_B |
| { 840, 4, 1, 4, 511, 0, 0x6ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #840 = BINSLI_D |
| { 841, 4, 1, 4, 511, 0, 0x6ULL, nullptr, nullptr, OperandInfo184, -1 ,nullptr }, // Inst #841 = BINSLI_H |
| { 842, 4, 1, 4, 511, 0, 0x6ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #842 = BINSLI_W |
| { 843, 4, 1, 4, 511, 0, 0x6ULL, nullptr, nullptr, OperandInfo186, -1 ,nullptr }, // Inst #843 = BINSL_B |
| { 844, 4, 1, 4, 511, 0, 0x6ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #844 = BINSL_D |
| { 845, 4, 1, 4, 511, 0, 0x6ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #845 = BINSL_H |
| { 846, 4, 1, 4, 511, 0, 0x6ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #846 = BINSL_W |
| { 847, 4, 1, 4, 512, 0, 0x6ULL, nullptr, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #847 = BINSRI_B |
| { 848, 4, 1, 4, 512, 0, 0x6ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #848 = BINSRI_D |
| { 849, 4, 1, 4, 512, 0, 0x6ULL, nullptr, nullptr, OperandInfo184, -1 ,nullptr }, // Inst #849 = BINSRI_H |
| { 850, 4, 1, 4, 512, 0, 0x6ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #850 = BINSRI_W |
| { 851, 4, 1, 4, 512, 0, 0x6ULL, nullptr, nullptr, OperandInfo186, -1 ,nullptr }, // Inst #851 = BINSR_B |
| { 852, 4, 1, 4, 512, 0, 0x6ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #852 = BINSR_D |
| { 853, 4, 1, 4, 512, 0, 0x6ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #853 = BINSR_H |
| { 854, 4, 1, 4, 512, 0, 0x6ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #854 = BINSR_W |
| { 855, 2, 1, 4, 1355, 0, 0x6ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #855 = BITREV |
| { 856, 2, 1, 4, 1506, 0, 0x6ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #856 = BITREV_MM |
| { 857, 2, 1, 4, 722, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #857 = BITSWAP |
| { 858, 2, 1, 4, 776, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #858 = BITSWAP_MMR6 |
| { 859, 2, 0, 4, 913, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo99, -1 ,nullptr }, // Inst #859 = BLEZ |
| { 860, 2, 0, 4, 1002, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo100, -1 ,nullptr }, // Inst #860 = BLEZ64 |
| { 861, 2, 0, 4, 919, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList3, OperandInfo99, -1 ,nullptr }, // Inst #861 = BLEZALC |
| { 862, 2, 0, 4, 992, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList3, OperandInfo99, -1 ,nullptr }, // Inst #862 = BLEZALC_MMR6 |
| { 863, 2, 0, 4, 924, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo99, -1 ,nullptr }, // Inst #863 = BLEZC |
| { 864, 2, 0, 4, 1010, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo100, -1 ,nullptr }, // Inst #864 = BLEZC64 |
| { 865, 2, 0, 4, 979, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList2, OperandInfo99, -1 ,nullptr }, // Inst #865 = BLEZC_MMR6 |
| { 866, 2, 0, 4, 373, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList2, OperandInfo99, -1 ,nullptr }, // Inst #866 = BLEZL |
| { 867, 2, 0, 4, 941, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo99, -1 ,nullptr }, // Inst #867 = BLEZ_MM |
| { 868, 3, 0, 4, 923, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo50, -1 ,nullptr }, // Inst #868 = BLTC |
| { 869, 3, 0, 4, 1009, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo97, -1 ,nullptr }, // Inst #869 = BLTC64 |
| { 870, 3, 0, 4, 977, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList2, OperandInfo50, -1 ,nullptr }, // Inst #870 = BLTC_MMR6 |
| { 871, 3, 0, 4, 923, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo50, -1 ,nullptr }, // Inst #871 = BLTUC |
| { 872, 3, 0, 4, 1009, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo97, -1 ,nullptr }, // Inst #872 = BLTUC64 |
| { 873, 3, 0, 4, 977, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList2, OperandInfo50, -1 ,nullptr }, // Inst #873 = BLTUC_MMR6 |
| { 874, 2, 0, 4, 913, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo99, -1 ,nullptr }, // Inst #874 = BLTZ |
| { 875, 2, 0, 4, 1002, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo100, -1 ,nullptr }, // Inst #875 = BLTZ64 |
| { 876, 2, 0, 4, 911, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList3, OperandInfo99, -1 ,nullptr }, // Inst #876 = BLTZAL |
| { 877, 2, 0, 4, 919, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList3, OperandInfo99, -1 ,nullptr }, // Inst #877 = BLTZALC |
| { 878, 2, 0, 4, 992, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList3, OperandInfo99, -1 ,nullptr }, // Inst #878 = BLTZALC_MMR6 |
| { 879, 2, 0, 4, 371, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList3, OperandInfo99, -1 ,nullptr }, // Inst #879 = BLTZALL |
| { 880, 2, 0, 4, 949, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, ImplicitList3, OperandInfo99, -1 ,nullptr }, // Inst #880 = BLTZALS_MM |
| { 881, 2, 0, 4, 950, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList3, OperandInfo99, -1 ,nullptr }, // Inst #881 = BLTZAL_MM |
| { 882, 2, 0, 4, 924, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo99, -1 ,nullptr }, // Inst #882 = BLTZC |
| { 883, 2, 0, 4, 1010, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo100, -1 ,nullptr }, // Inst #883 = BLTZC64 |
| { 884, 2, 0, 4, 979, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList2, OperandInfo99, -1 ,nullptr }, // Inst #884 = BLTZC_MMR6 |
| { 885, 2, 0, 4, 373, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList2, OperandInfo99, -1 ,nullptr }, // Inst #885 = BLTZL |
| { 886, 2, 0, 4, 941, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo99, -1 ,nullptr }, // Inst #886 = BLTZ_MM |
| { 887, 4, 1, 4, 519, 0, 0x6ULL, nullptr, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #887 = BMNZI_B |
| { 888, 4, 1, 4, 519, 0, 0x6ULL, nullptr, nullptr, OperandInfo186, -1 ,nullptr }, // Inst #888 = BMNZ_V |
| { 889, 4, 1, 4, 519, 0, 0x6ULL, nullptr, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #889 = BMZI_B |
| { 890, 4, 1, 4, 519, 0, 0x6ULL, nullptr, nullptr, OperandInfo186, -1 ,nullptr }, // Inst #890 = BMZ_V |
| { 891, 3, 0, 4, 912, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo50, -1 ,nullptr }, // Inst #891 = BNE |
| { 892, 3, 0, 4, 1001, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo97, -1 ,nullptr }, // Inst #892 = BNE64 |
| { 893, 3, 0, 4, 923, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo50, -1 ,nullptr }, // Inst #893 = BNEC |
| { 894, 3, 0, 4, 1009, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo97, -1 ,nullptr }, // Inst #894 = BNEC64 |
| { 895, 3, 0, 4, 977, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList2, OperandInfo50, -1 ,nullptr }, // Inst #895 = BNEC_MMR6 |
| { 896, 3, 1, 4, 517, 0, 0x6ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr }, // Inst #896 = BNEGI_B |
| { 897, 3, 1, 4, 517, 0, 0x6ULL, nullptr, nullptr, OperandInfo167, -1 ,nullptr }, // Inst #897 = BNEGI_D |
| { 898, 3, 1, 4, 517, 0, 0x6ULL, nullptr, nullptr, OperandInfo168, -1 ,nullptr }, // Inst #898 = BNEGI_H |
| { 899, 3, 1, 4, 517, 0, 0x6ULL, nullptr, nullptr, OperandInfo169, -1 ,nullptr }, // Inst #899 = BNEGI_W |
| { 900, 3, 1, 4, 517, 0, 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #900 = BNEG_B |
| { 901, 3, 1, 4, 517, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #901 = BNEG_D |
| { 902, 3, 1, 4, 517, 0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #902 = BNEG_H |
| { 903, 3, 1, 4, 517, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #903 = BNEG_W |
| { 904, 3, 0, 4, 372, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, ImplicitList2, OperandInfo50, -1 ,nullptr }, // Inst #904 = BNEL |
| { 905, 2, 0, 2, 941, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList2, OperandInfo181, -1 ,nullptr }, // Inst #905 = BNEZ16_MM |
| { 906, 2, 0, 4, 919, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList3, OperandInfo99, -1 ,nullptr }, // Inst #906 = BNEZALC |
| { 907, 2, 0, 4, 992, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList3, OperandInfo99, -1 ,nullptr }, // Inst #907 = BNEZALC_MMR6 |
| { 908, 2, 0, 4, 924, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo99, -1 ,nullptr }, // Inst #908 = BNEZC |
| { 909, 2, 0, 2, 978, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList2, OperandInfo181, -1 ,nullptr }, // Inst #909 = BNEZC16_MMR6 |
| { 910, 2, 0, 4, 1010, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo100, -1 ,nullptr }, // Inst #910 = BNEZC64 |
| { 911, 2, 0, 4, 942, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, ImplicitList2, OperandInfo99, -1 ,nullptr }, // Inst #911 = BNEZC_MM |
| { 912, 2, 0, 4, 979, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x36ULL, nullptr, ImplicitList2, OperandInfo99, -1 ,nullptr }, // Inst #912 = BNEZC_MMR6 |
| { 913, 3, 0, 4, 943, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL, nullptr, ImplicitList2, OperandInfo50, -1 ,nullptr }, // Inst #913 = BNE_MM |
| { 914, 3, 0, 4, 923, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo50, -1 ,nullptr }, // Inst #914 = BNVC |
| { 915, 3, 0, 4, 977, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList2, OperandInfo50, -1 ,nullptr }, // Inst #915 = BNVC_MMR6 |
| { 916, 2, 0, 4, 523, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList2, OperandInfo187, -1 ,nullptr }, // Inst #916 = BNZ_B |
| { 917, 2, 0, 4, 523, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList2, OperandInfo188, -1 ,nullptr }, // Inst #917 = BNZ_D |
| { 918, 2, 0, 4, 523, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList2, OperandInfo189, -1 ,nullptr }, // Inst #918 = BNZ_H |
| { 919, 2, 0, 4, 523, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList2, OperandInfo187, -1 ,nullptr }, // Inst #919 = BNZ_V |
| { 920, 2, 0, 4, 523, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList2, OperandInfo190, -1 ,nullptr }, // Inst #920 = BNZ_W |
| { 921, 3, 0, 4, 923, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL, nullptr, ImplicitList2, OperandInfo50, -1 ,nullptr }, // Inst #921 = BOVC |
| { 922, 3, 0, 4, 977, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList2, OperandInfo50, -1 ,nullptr }, // Inst #922 = BOVC_MMR6 |
| { 923, 1, 0, 4, 1356, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #923 = BPOSGE32 |
| { 924, 1, 0, 4, 1659, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #924 = BPOSGE32C_MMR3 |
| { 925, 1, 0, 4, 1507, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #925 = BPOSGE32_MM |
| { 926, 2, 0, 4, 374, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #926 = BREAK |
| { 927, 1, 0, 2, 958, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #927 = BREAK16_MM |
| { 928, 1, 0, 2, 999, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #928 = BREAK16_MMR6 |
| { 929, 2, 0, 4, 958, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #929 = BREAK_MM |
| { 930, 2, 0, 4, 999, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr }, // Inst #930 = BREAK_MMR6 |
| { 931, 4, 1, 4, 518, 0, 0x6ULL, nullptr, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #931 = BSELI_B |
| { 932, 4, 1, 4, 518, 0, 0x6ULL, nullptr, nullptr, OperandInfo186, -1 ,nullptr }, // Inst #932 = BSEL_V |
| { 933, 3, 1, 4, 515, 0, 0x6ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr }, // Inst #933 = BSETI_B |
| { 934, 3, 1, 4, 515, 0, 0x6ULL, nullptr, nullptr, OperandInfo167, -1 ,nullptr }, // Inst #934 = BSETI_D |
| { 935, 3, 1, 4, 515, 0, 0x6ULL, nullptr, nullptr, OperandInfo168, -1 ,nullptr }, // Inst #935 = BSETI_H |
| { 936, 3, 1, 4, 515, 0, 0x6ULL, nullptr, nullptr, OperandInfo169, -1 ,nullptr }, // Inst #936 = BSETI_W |
| { 937, 3, 1, 4, 515, 0, 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #937 = BSET_B |
| { 938, 3, 1, 4, 515, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #938 = BSET_D |
| { 939, 3, 1, 4, 515, 0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #939 = BSET_H |
| { 940, 3, 1, 4, 515, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #940 = BSET_W |
| { 941, 2, 0, 4, 523, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList2, OperandInfo187, -1 ,nullptr }, // Inst #941 = BZ_B |
| { 942, 2, 0, 4, 523, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList2, OperandInfo188, -1 ,nullptr }, // Inst #942 = BZ_D |
| { 943, 2, 0, 4, 523, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList2, OperandInfo189, -1 ,nullptr }, // Inst #943 = BZ_H |
| { 944, 2, 0, 4, 523, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList2, OperandInfo187, -1 ,nullptr }, // Inst #944 = BZ_V |
| { 945, 2, 0, 4, 523, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList2, OperandInfo190, -1 ,nullptr }, // Inst #945 = BZ_W |
| { 946, 2, 0, 2, 931, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo191, -1 ,nullptr }, // Inst #946 = BeqzRxImm16 |
| { 947, 2, 0, 4, 931, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo191, -1 ,nullptr }, // Inst #947 = BeqzRxImmX16 |
| { 948, 1, 0, 2, 931, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #948 = Bimm16 |
| { 949, 1, 0, 4, 931, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr }, // Inst #949 = BimmX16 |
| { 950, 2, 0, 2, 931, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo191, -1 ,nullptr }, // Inst #950 = BnezRxImm16 |
| { 951, 2, 0, 4, 931, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo191, -1 ,nullptr }, // Inst #951 = BnezRxImmX16 |
| { 952, 0, 0, 2, 935, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #952 = Break16 |
| { 953, 1, 0, 2, 931, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList7, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #953 = Bteqz16 |
| { 954, 1, 0, 4, 931, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList7, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #954 = BteqzX16 |
| { 955, 1, 0, 2, 931, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList7, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #955 = Btnez16 |
| { 956, 1, 0, 4, 931, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList7, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #956 = BtnezX16 |
| { 957, 3, 0, 4, 465, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr }, // Inst #957 = CACHE |
| { 958, 3, 0, 4, 466, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr }, // Inst #958 = CACHEE |
| { 959, 3, 0, 4, 1099, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr }, // Inst #959 = CACHEE_MM |
| { 960, 3, 0, 4, 1132, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr }, // Inst #960 = CACHE_MM |
| { 961, 3, 0, 4, 1154, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr }, // Inst #961 = CACHE_MMR6 |
| { 962, 3, 0, 4, 1080, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr }, // Inst #962 = CACHE_R6 |
| { 963, 2, 1, 4, 709, 0, 0x4ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #963 = CEIL_L_D64 |
| { 964, 2, 1, 4, 1300, 0, 0x4ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #964 = CEIL_L_D_MMR6 |
| { 965, 2, 1, 4, 709, 0, 0x4ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr }, // Inst #965 = CEIL_L_S |
| { 966, 2, 1, 4, 1300, 0, 0x4ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr }, // Inst #966 = CEIL_L_S_MMR6 |
| { 967, 2, 1, 4, 709, 0, 0x4ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #967 = CEIL_W_D32 |
| { 968, 2, 1, 4, 709, 0, 0x4ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr }, // Inst #968 = CEIL_W_D64 |
| { 969, 2, 1, 4, 1300, 0, 0x4ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #969 = CEIL_W_D_MMR6 |
| { 970, 2, 1, 4, 1236, 0, 0x4ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #970 = CEIL_W_MM |
| { 971, 2, 1, 4, 709, 0, 0x4ULL, nullptr, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #971 = CEIL_W_S |
| { 972, 2, 1, 4, 1236, 0, 0x4ULL, nullptr, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #972 = CEIL_W_S_MM |
| { 973, 2, 1, 4, 1300, 0, 0x4ULL, nullptr, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #973 = CEIL_W_S_MMR6 |
| { 974, 3, 1, 4, 551, 0, 0x6ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr }, // Inst #974 = CEQI_B |
| { 975, 3, 1, 4, 551, 0, 0x6ULL, nullptr, nullptr, OperandInfo167, -1 ,nullptr }, // Inst #975 = CEQI_D |
| { 976, 3, 1, 4, 551, 0, 0x6ULL, nullptr, nullptr, OperandInfo168, -1 ,nullptr }, // Inst #976 = CEQI_H |
| { 977, 3, 1, 4, 551, 0, 0x6ULL, nullptr, nullptr, OperandInfo169, -1 ,nullptr }, // Inst #977 = CEQI_W |
| { 978, 3, 1, 4, 551, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #978 = CEQ_B |
| { 979, 3, 1, 4, 551, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #979 = CEQ_D |
| { 980, 3, 1, 4, 551, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #980 = CEQ_H |
| { 981, 3, 1, 4, 551, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #981 = CEQ_W |
| { 982, 2, 1, 4, 686, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo198, -1 ,nullptr }, // Inst #982 = CFC1 |
| { 983, 2, 1, 4, 1283, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo198, -1 ,nullptr }, // Inst #983 = CFC1_MM |
| { 984, 2, 1, 4, 1049, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo199, -1 ,nullptr }, // Inst #984 = CFC2_MM |
| { 985, 2, 1, 4, 524, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo200, -1 ,nullptr }, // Inst #985 = CFCMSA |
| { 986, 4, 1, 4, 1192, 0, 0x1ULL, nullptr, nullptr, OperandInfo201, -1 ,nullptr }, // Inst #986 = CINS |
| { 987, 4, 1, 4, 1192, 0, 0x1ULL, nullptr, nullptr, OperandInfo201, -1 ,nullptr }, // Inst #987 = CINS32 |
| { 988, 4, 1, 4, 1192, 0, 0x1ULL, nullptr, nullptr, OperandInfo202, -1 ,nullptr }, // Inst #988 = CINS64_32 |
| { 989, 4, 1, 4, 1192, 0, 0x1ULL, nullptr, nullptr, OperandInfo203, -1 ,nullptr }, // Inst #989 = CINS_i32 |
| { 990, 2, 1, 4, 1217, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #990 = CLASS_D |
| { 991, 2, 1, 4, 1303, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #991 = CLASS_D_MMR6 |
| { 992, 2, 1, 4, 1216, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #992 = CLASS_S |
| { 993, 2, 1, 4, 1303, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #993 = CLASS_S_MMR6 |
| { 994, 3, 1, 4, 550, 0, 0x6ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr }, // Inst #994 = CLEI_S_B |
| { 995, 3, 1, 4, 550, 0, 0x6ULL, nullptr, nullptr, OperandInfo167, -1 ,nullptr }, // Inst #995 = CLEI_S_D |
| { 996, 3, 1, 4, 550, 0, 0x6ULL, nullptr, nullptr, OperandInfo168, -1 ,nullptr }, // Inst #996 = CLEI_S_H |
| { 997, 3, 1, 4, 550, 0, 0x6ULL, nullptr, nullptr, OperandInfo169, -1 ,nullptr }, // Inst #997 = CLEI_S_W |
| { 998, 3, 1, 4, 550, 0, 0x6ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr }, // Inst #998 = CLEI_U_B |
| { 999, 3, 1, 4, 550, 0, 0x6ULL, nullptr, nullptr, OperandInfo167, -1 ,nullptr }, // Inst #999 = CLEI_U_D |
| { 1000, 3, 1, 4, 550, 0, 0x6ULL, nullptr, nullptr, OperandInfo168, -1 ,nullptr }, // Inst #1000 = CLEI_U_H |
| { 1001, 3, 1, 4, 550, 0, 0x6ULL, nullptr, nullptr, OperandInfo169, -1 ,nullptr }, // Inst #1001 = CLEI_U_W |
| { 1002, 3, 1, 4, 550, 0, 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #1002 = CLE_S_B |
| { 1003, 3, 1, 4, 550, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1003 = CLE_S_D |
| { 1004, 3, 1, 4, 550, 0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #1004 = CLE_S_H |
| { 1005, 3, 1, 4, 550, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1005 = CLE_S_W |
| { 1006, 3, 1, 4, 550, 0, 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #1006 = CLE_U_B |
| { 1007, 3, 1, 4, 550, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1007 = CLE_U_D |
| { 1008, 3, 1, 4, 550, 0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #1008 = CLE_U_H |
| { 1009, 3, 1, 4, 550, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1009 = CLE_U_W |
| { 1010, 2, 1, 4, 469, 0, 0x1ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #1010 = CLO |
| { 1011, 2, 1, 4, 736, 0, 0x1ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #1011 = CLO_MM |
| { 1012, 2, 1, 4, 777, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #1012 = CLO_MMR6 |
| { 1013, 2, 1, 4, 723, 0, 0x6ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #1013 = CLO_R6 |
| { 1014, 3, 1, 4, 549, 0, 0x6ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr }, // Inst #1014 = CLTI_S_B |
| { 1015, 3, 1, 4, 549, 0, 0x6ULL, nullptr, nullptr, OperandInfo167, -1 ,nullptr }, // Inst #1015 = CLTI_S_D |
| { 1016, 3, 1, 4, 549, 0, 0x6ULL, nullptr, nullptr, OperandInfo168, -1 ,nullptr }, // Inst #1016 = CLTI_S_H |
| { 1017, 3, 1, 4, 549, 0, 0x6ULL, nullptr, nullptr, OperandInfo169, -1 ,nullptr }, // Inst #1017 = CLTI_S_W |
| { 1018, 3, 1, 4, 549, 0, 0x6ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr }, // Inst #1018 = CLTI_U_B |
| { 1019, 3, 1, 4, 549, 0, 0x6ULL, nullptr, nullptr, OperandInfo167, -1 ,nullptr }, // Inst #1019 = CLTI_U_D |
| { 1020, 3, 1, 4, 549, 0, 0x6ULL, nullptr, nullptr, OperandInfo168, -1 ,nullptr }, // Inst #1020 = CLTI_U_H |
| { 1021, 3, 1, 4, 549, 0, 0x6ULL, nullptr, nullptr, OperandInfo169, -1 ,nullptr }, // Inst #1021 = CLTI_U_W |
| { 1022, 3, 1, 4, 549, 0, 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #1022 = CLT_S_B |
| { 1023, 3, 1, 4, 549, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1023 = CLT_S_D |
| { 1024, 3, 1, 4, 549, 0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #1024 = CLT_S_H |
| { 1025, 3, 1, 4, 549, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1025 = CLT_S_W |
| { 1026, 3, 1, 4, 549, 0, 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #1026 = CLT_U_B |
| { 1027, 3, 1, 4, 549, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1027 = CLT_U_D |
| { 1028, 3, 1, 4, 549, 0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #1028 = CLT_U_H |
| { 1029, 3, 1, 4, 549, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1029 = CLT_U_W |
| { 1030, 2, 1, 4, 470, 0, 0x1ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #1030 = CLZ |
| { 1031, 2, 1, 4, 737, 0, 0x1ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #1031 = CLZ_MM |
| { 1032, 2, 1, 4, 778, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #1032 = CLZ_MMR6 |
| { 1033, 2, 1, 4, 724, 0, 0x6ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #1033 = CLZ_R6 |
| { 1034, 3, 1, 4, 1460, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList10, OperandInfo204, -1 ,nullptr }, // Inst #1034 = CMPGDU_EQ_QB |
| { 1035, 3, 1, 4, 1624, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList10, OperandInfo204, -1 ,nullptr }, // Inst #1035 = CMPGDU_EQ_QB_MMR2 |
| { 1036, 3, 1, 4, 1461, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList10, OperandInfo204, -1 ,nullptr }, // Inst #1036 = CMPGDU_LE_QB |
| { 1037, 3, 1, 4, 1625, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList10, OperandInfo204, -1 ,nullptr }, // Inst #1037 = CMPGDU_LE_QB_MMR2 |
| { 1038, 3, 1, 4, 1462, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList10, OperandInfo204, -1 ,nullptr }, // Inst #1038 = CMPGDU_LT_QB |
| { 1039, 3, 1, 4, 1626, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList10, OperandInfo204, -1 ,nullptr }, // Inst #1039 = CMPGDU_LT_QB_MMR2 |
| { 1040, 3, 1, 4, 1357, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo204, -1 ,nullptr }, // Inst #1040 = CMPGU_EQ_QB |
| { 1041, 3, 1, 4, 1508, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo204, -1 ,nullptr }, // Inst #1041 = CMPGU_EQ_QB_MM |
| { 1042, 3, 1, 4, 1358, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo204, -1 ,nullptr }, // Inst #1042 = CMPGU_LE_QB |
| { 1043, 3, 1, 4, 1509, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo204, -1 ,nullptr }, // Inst #1043 = CMPGU_LE_QB_MM |
| { 1044, 3, 1, 4, 1359, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo204, -1 ,nullptr }, // Inst #1044 = CMPGU_LT_QB |
| { 1045, 3, 1, 4, 1510, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo204, -1 ,nullptr }, // Inst #1045 = CMPGU_LT_QB_MM |
| { 1046, 2, 0, 4, 1360, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList10, OperandInfo159, -1 ,nullptr }, // Inst #1046 = CMPU_EQ_QB |
| { 1047, 2, 0, 4, 1511, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList10, OperandInfo159, -1 ,nullptr }, // Inst #1047 = CMPU_EQ_QB_MM |
| { 1048, 2, 0, 4, 1361, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList10, OperandInfo159, -1 ,nullptr }, // Inst #1048 = CMPU_LE_QB |
| { 1049, 2, 0, 4, 1512, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList10, OperandInfo159, -1 ,nullptr }, // Inst #1049 = CMPU_LE_QB_MM |
| { 1050, 2, 0, 4, 1362, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList10, OperandInfo159, -1 ,nullptr }, // Inst #1050 = CMPU_LT_QB |
| { 1051, 2, 0, 4, 1513, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList10, OperandInfo159, -1 ,nullptr }, // Inst #1051 = CMPU_LT_QB_MM |
| { 1052, 3, 1, 4, 1290, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1052 = CMP_AF_D_MMR6 |
| { 1053, 3, 1, 4, 1291, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1053 = CMP_AF_S_MMR6 |
| { 1054, 3, 1, 4, 556, 0, 0x16ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1054 = CMP_EQ_D |
| { 1055, 3, 1, 4, 1290, 0, 0x16ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1055 = CMP_EQ_D_MMR6 |
| { 1056, 2, 0, 4, 1363, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList10, OperandInfo159, -1 ,nullptr }, // Inst #1056 = CMP_EQ_PH |
| { 1057, 2, 0, 4, 1514, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList10, OperandInfo159, -1 ,nullptr }, // Inst #1057 = CMP_EQ_PH_MM |
| { 1058, 3, 1, 4, 557, 0, 0x16ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1058 = CMP_EQ_S |
| { 1059, 3, 1, 4, 1291, 0, 0x16ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1059 = CMP_EQ_S_MMR6 |
| { 1060, 3, 1, 4, 1660, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1060 = CMP_F_D |
| { 1061, 3, 1, 4, 1661, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1061 = CMP_F_S |
| { 1062, 3, 1, 4, 562, 0, 0x16ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1062 = CMP_LE_D |
| { 1063, 3, 1, 4, 1290, 0, 0x16ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1063 = CMP_LE_D_MMR6 |
| { 1064, 2, 0, 4, 1364, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList10, OperandInfo159, -1 ,nullptr }, // Inst #1064 = CMP_LE_PH |
| { 1065, 2, 0, 4, 1515, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList10, OperandInfo159, -1 ,nullptr }, // Inst #1065 = CMP_LE_PH_MM |
| { 1066, 3, 1, 4, 563, 0, 0x16ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1066 = CMP_LE_S |
| { 1067, 3, 1, 4, 1291, 0, 0x16ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1067 = CMP_LE_S_MMR6 |
| { 1068, 3, 1, 4, 558, 0, 0x16ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1068 = CMP_LT_D |
| { 1069, 3, 1, 4, 1290, 0, 0x16ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1069 = CMP_LT_D_MMR6 |
| { 1070, 2, 0, 4, 1365, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList10, OperandInfo159, -1 ,nullptr }, // Inst #1070 = CMP_LT_PH |
| { 1071, 2, 0, 4, 1516, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList10, OperandInfo159, -1 ,nullptr }, // Inst #1071 = CMP_LT_PH_MM |
| { 1072, 3, 1, 4, 559, 0, 0x16ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1072 = CMP_LT_S |
| { 1073, 3, 1, 4, 1291, 0, 0x16ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1073 = CMP_LT_S_MMR6 |
| { 1074, 3, 1, 4, 1662, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1074 = CMP_SAF_D |
| { 1075, 3, 1, 4, 1292, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1075 = CMP_SAF_D_MMR6 |
| { 1076, 3, 1, 4, 1663, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1076 = CMP_SAF_S |
| { 1077, 3, 1, 4, 1293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1077 = CMP_SAF_S_MMR6 |
| { 1078, 3, 1, 4, 1664, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1078 = CMP_SEQ_D |
| { 1079, 3, 1, 4, 1292, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1079 = CMP_SEQ_D_MMR6 |
| { 1080, 3, 1, 4, 1665, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1080 = CMP_SEQ_S |
| { 1081, 3, 1, 4, 1293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1081 = CMP_SEQ_S_MMR6 |
| { 1082, 3, 1, 4, 1666, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1082 = CMP_SLE_D |
| { 1083, 3, 1, 4, 1292, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1083 = CMP_SLE_D_MMR6 |
| { 1084, 3, 1, 4, 1667, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1084 = CMP_SLE_S |
| { 1085, 3, 1, 4, 1293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1085 = CMP_SLE_S_MMR6 |
| { 1086, 3, 1, 4, 1668, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1086 = CMP_SLT_D |
| { 1087, 3, 1, 4, 1292, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1087 = CMP_SLT_D_MMR6 |
| { 1088, 3, 1, 4, 1669, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1088 = CMP_SLT_S |
| { 1089, 3, 1, 4, 1293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1089 = CMP_SLT_S_MMR6 |
| { 1090, 3, 1, 4, 1670, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1090 = CMP_SUEQ_D |
| { 1091, 3, 1, 4, 1294, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1091 = CMP_SUEQ_D_MMR6 |
| { 1092, 3, 1, 4, 1671, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1092 = CMP_SUEQ_S |
| { 1093, 3, 1, 4, 1295, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1093 = CMP_SUEQ_S_MMR6 |
| { 1094, 3, 1, 4, 1672, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1094 = CMP_SULE_D |
| { 1095, 3, 1, 4, 1294, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1095 = CMP_SULE_D_MMR6 |
| { 1096, 3, 1, 4, 1673, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1096 = CMP_SULE_S |
| { 1097, 3, 1, 4, 1295, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1097 = CMP_SULE_S_MMR6 |
| { 1098, 3, 1, 4, 1674, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1098 = CMP_SULT_D |
| { 1099, 3, 1, 4, 1294, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1099 = CMP_SULT_D_MMR6 |
| { 1100, 3, 1, 4, 1675, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1100 = CMP_SULT_S |
| { 1101, 3, 1, 4, 1295, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1101 = CMP_SULT_S_MMR6 |
| { 1102, 3, 1, 4, 1676, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1102 = CMP_SUN_D |
| { 1103, 3, 1, 4, 1292, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1103 = CMP_SUN_D_MMR6 |
| { 1104, 3, 1, 4, 1677, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1104 = CMP_SUN_S |
| { 1105, 3, 1, 4, 1293, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1105 = CMP_SUN_S_MMR6 |
| { 1106, 3, 1, 4, 554, 0, 0x16ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1106 = CMP_UEQ_D |
| { 1107, 3, 1, 4, 1292, 0, 0x16ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1107 = CMP_UEQ_D_MMR6 |
| { 1108, 3, 1, 4, 555, 0, 0x16ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1108 = CMP_UEQ_S |
| { 1109, 3, 1, 4, 1293, 0, 0x16ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1109 = CMP_UEQ_S_MMR6 |
| { 1110, 3, 1, 4, 564, 0, 0x16ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1110 = CMP_ULE_D |
| { 1111, 3, 1, 4, 1292, 0, 0x16ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1111 = CMP_ULE_D_MMR6 |
| { 1112, 3, 1, 4, 565, 0, 0x16ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1112 = CMP_ULE_S |
| { 1113, 3, 1, 4, 1293, 0, 0x16ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1113 = CMP_ULE_S_MMR6 |
| { 1114, 3, 1, 4, 560, 0, 0x16ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1114 = CMP_ULT_D |
| { 1115, 3, 1, 4, 1292, 0, 0x16ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1115 = CMP_ULT_D_MMR6 |
| { 1116, 3, 1, 4, 561, 0, 0x16ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1116 = CMP_ULT_S |
| { 1117, 3, 1, 4, 1293, 0, 0x16ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1117 = CMP_ULT_S_MMR6 |
| { 1118, 3, 1, 4, 552, 0, 0x16ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1118 = CMP_UN_D |
| { 1119, 3, 1, 4, 1290, 0, 0x16ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr }, // Inst #1119 = CMP_UN_D_MMR6 |
| { 1120, 3, 1, 4, 553, 0, 0x16ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1120 = CMP_UN_S |
| { 1121, 3, 1, 4, 1291, 0, 0x16ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr }, // Inst #1121 = CMP_UN_S_MMR6 |
| { 1122, 3, 1, 4, 681, 0, 0x6ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr }, // Inst #1122 = COPY_S_B |
| { 1123, 3, 1, 4, 681, 0, 0x6ULL, nullptr, nullptr, OperandInfo208, -1 ,nullptr }, // Inst #1123 = COPY_S_D |
| { 1124, 3, 1, 4, 681, 0, 0x6ULL, nullptr, nullptr, OperandInfo209, -1 ,nullptr }, // Inst #1124 = COPY_S_H |
| { 1125, 3, 1, 4, 681, 0, 0x6ULL, nullptr, nullptr, OperandInfo210, -1 ,nullptr }, // Inst #1125 = COPY_S_W |
| { 1126, 3, 1, 4, 680, 0, 0x6ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr }, // Inst #1126 = COPY_U_B |
| { 1127, 3, 1, 4, 680, 0, 0x6ULL, nullptr, nullptr, OperandInfo209, -1 ,nullptr }, // Inst #1127 = COPY_U_H |
| { 1128, 3, 1, 4, 680, 0, 0x6ULL, nullptr, nullptr, OperandInfo210, -1 ,nullptr }, // Inst #1128 = COPY_U_W |
| { 1129, 3, 1, 4, 1182, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #1129 = CRC32B |
| { 1130, 3, 1, 4, 1185, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #1130 = CRC32CB |
| { 1131, 3, 1, 4, 1189, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #1131 = CRC32CD |
| { 1132, 3, 1, 4, 1186, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #1132 = CRC32CH |
| { 1133, 3, 1, 4, 1187, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #1133 = CRC32CW |
| { 1134, 3, 1, 4, 1188, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #1134 = CRC32D |
| { 1135, 3, 1, 4, 1183, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #1135 = CRC32H |
| { 1136, 3, 1, 4, 1184, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #1136 = CRC32W |
| { 1137, 2, 1, 4, 677, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo211, -1 ,nullptr }, // Inst #1137 = CTC1 |
| { 1138, 2, 1, 4, 1284, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo211, -1 ,nullptr }, // Inst #1138 = CTC1_MM |
| { 1139, 2, 1, 4, 1050, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo212, -1 ,nullptr }, // Inst #1139 = CTC2_MM |
| { 1140, 2, 0, 4, 524, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo213, -1 ,nullptr }, // Inst #1140 = CTCMSA |
| { 1141, 2, 1, 4, 630, 0, 0x4ULL, nullptr, nullptr, OperandInfo214, -1 ,nullptr }, // Inst #1141 = CVT_D32_S |
| { 1142, 2, 1, 4, 1235, 0, 0x4ULL, nullptr, nullptr, OperandInfo214, -1 ,nullptr }, // Inst #1142 = CVT_D32_S_MM |
| { 1143, 2, 1, 4, 630, 0, 0x4ULL, nullptr, nullptr, OperandInfo214, -1 ,nullptr }, // Inst #1143 = CVT_D32_W |
| { 1144, 2, 1, 4, 1235, 0, 0x4ULL, nullptr, nullptr, OperandInfo214, -1 ,nullptr }, // Inst #1144 = CVT_D32_W_MM |
| { 1145, 2, 1, 4, 630, 0, 0x4ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #1145 = CVT_D64_L |
| { 1146, 2, 1, 4, 630, 0, 0x4ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr }, // Inst #1146 = CVT_D64_S |
| { 1147, 2, 1, 4, 1235, 0, 0x4ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr }, // Inst #1147 = CVT_D64_S_MM |
| { 1148, 2, 1, 4, 630, 0, 0x4ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr }, // Inst #1148 = CVT_D64_W |
| { 1149, 2, 1, 4, 1235, 0, 0x4ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr }, // Inst #1149 = CVT_D64_W_MM |
| { 1150, 2, 1, 4, 1296, 0, 0x4ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #1150 = CVT_D_L_MMR6 |
| { 1151, 2, 1, 4, 630, 0, 0x4ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #1151 = CVT_L_D64 |
| { 1152, 2, 1, 4, 1235, 0, 0x4ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #1152 = CVT_L_D64_MM |
| { 1153, 2, 1, 4, 1296, 0, 0x4ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #1153 = CVT_L_D_MMR6 |
| { 1154, 2, 1, 4, 630, 0, 0x4ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr }, // Inst #1154 = CVT_L_S |
| { 1155, 2, 1, 4, 1235, 0, 0x4ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr }, // Inst #1155 = CVT_L_S_MM |
| { 1156, 2, 1, 4, 1296, 0, 0x4ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr }, // Inst #1156 = CVT_L_S_MMR6 |
| { 1157, 3, 1, 4, 631, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo215, -1 ,nullptr }, // Inst #1157 = CVT_PS_S64 |
| { 1158, 2, 1, 4, 630, 0, 0x4ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1158 = CVT_S_D32 |
| { 1159, 2, 1, 4, 1235, 0, 0x4ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1159 = CVT_S_D32_MM |
| { 1160, 2, 1, 4, 630, 0, 0x4ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr }, // Inst #1160 = CVT_S_D64 |
| { 1161, 2, 1, 4, 1235, 0, 0x4ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr }, // Inst #1161 = CVT_S_D64_MM |
| { 1162, 2, 1, 4, 630, 0, 0x4ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr }, // Inst #1162 = CVT_S_L |
| { 1163, 2, 1, 4, 1296, 0, 0x4ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr }, // Inst #1163 = CVT_S_L_MMR6 |
| { 1164, 2, 1, 4, 631, 0, 0x4ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr }, // Inst #1164 = CVT_S_PL64 |
| { 1165, 2, 1, 4, 631, 0, 0x4ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr }, // Inst #1165 = CVT_S_PU64 |
| { 1166, 2, 1, 4, 630, 0, 0x4ULL, nullptr, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #1166 = CVT_S_W |
| { 1167, 2, 1, 4, 1235, 0, 0x4ULL, nullptr, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #1167 = CVT_S_W_MM |
| { 1168, 2, 1, 4, 1296, 0, 0x4ULL, nullptr, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #1168 = CVT_S_W_MMR6 |
| { 1169, 2, 1, 4, 630, 0, 0x4ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1169 = CVT_W_D32 |
| { 1170, 2, 1, 4, 1235, 0, 0x4ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1170 = CVT_W_D32_MM |
| { 1171, 2, 1, 4, 630, 0, 0x4ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr }, // Inst #1171 = CVT_W_D64 |
| { 1172, 2, 1, 4, 1235, 0, 0x4ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr }, // Inst #1172 = CVT_W_D64_MM |
| { 1173, 2, 1, 4, 630, 0, 0x4ULL, nullptr, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #1173 = CVT_W_S |
| { 1174, 2, 1, 4, 1235, 0, 0x4ULL, nullptr, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #1174 = CVT_W_S_MM |
| { 1175, 2, 1, 4, 1296, 0, 0x4ULL, nullptr, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #1175 = CVT_W_S_MMR6 |
| { 1176, 3, 1, 4, 632, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo216, -1 ,nullptr }, // Inst #1176 = C_EQ_D32 |
| { 1177, 3, 1, 4, 1248, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo216, -1 ,nullptr }, // Inst #1177 = C_EQ_D32_MM |
| { 1178, 3, 1, 4, 632, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo217, -1 ,nullptr }, // Inst #1178 = C_EQ_D64 |
| { 1179, 3, 1, 4, 1248, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo217, -1 ,nullptr }, // Inst #1179 = C_EQ_D64_MM |
| { 1180, 3, 1, 4, 633, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo218, -1 ,nullptr }, // Inst #1180 = C_EQ_S |
| { 1181, 3, 1, 4, 1249, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo218, -1 ,nullptr }, // Inst #1181 = C_EQ_S_MM |
| { 1182, 3, 1, 4, 632, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo216, -1 ,nullptr }, // Inst #1182 = C_F_D32 |
| { 1183, 3, 1, 4, 1246, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo216, -1 ,nullptr }, // Inst #1183 = C_F_D32_MM |
| { 1184, 3, 1, 4, 632, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo217, -1 ,nullptr }, // Inst #1184 = C_F_D64 |
| { 1185, 3, 1, 4, 1246, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo217, -1 ,nullptr }, // Inst #1185 = C_F_D64_MM |
| { 1186, 3, 1, 4, 633, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo218, -1 ,nullptr }, // Inst #1186 = C_F_S |
| { 1187, 3, 1, 4, 1247, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo218, -1 ,nullptr }, // Inst #1187 = C_F_S_MM |
| { 1188, 3, 1, 4, 632, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo216, -1 ,nullptr }, // Inst #1188 = C_LE_D32 |
| { 1189, 3, 1, 4, 1248, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo216, -1 ,nullptr }, // Inst #1189 = C_LE_D32_MM |
| { 1190, 3, 1, 4, 632, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo217, -1 ,nullptr }, // Inst #1190 = C_LE_D64 |
| { 1191, 3, 1, 4, 1248, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo217, -1 ,nullptr }, // Inst #1191 = C_LE_D64_MM |
| { 1192, 3, 1, 4, 633, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo218, -1 ,nullptr }, // Inst #1192 = C_LE_S |
| { 1193, 3, 1, 4, 1249, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo218, -1 ,nullptr }, // Inst #1193 = C_LE_S_MM |
| { 1194, 3, 1, 4, 632, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo216, -1 ,nullptr }, // Inst #1194 = C_LT_D32 |
| { 1195, 3, 1, 4, 1248, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo216, -1 ,nullptr }, // Inst #1195 = C_LT_D32_MM |
| { 1196, 3, 1, 4, 632, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo217, -1 ,nullptr }, // Inst #1196 = C_LT_D64 |
| { 1197, 3, 1, 4, 1248, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo217, -1 ,nullptr }, // Inst #1197 = C_LT_D64_MM |
| { 1198, 3, 1, 4, 633, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo218, -1 ,nullptr }, // Inst #1198 = C_LT_S |
| { 1199, 3, 1, 4, 1249, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo218, -1 ,nullptr }, // Inst #1199 = C_LT_S_MM |
| { 1200, 3, 1, 4, 632, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo216, -1 ,nullptr }, // Inst #1200 = C_NGE_D32 |
| { 1201, 3, 1, 4, 1250, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo216, -1 ,nullptr }, // Inst #1201 = C_NGE_D32_MM |
| { 1202, 3, 1, 4, 632, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo217, -1 ,nullptr }, // Inst #1202 = C_NGE_D64 |
| { 1203, 3, 1, 4, 1250, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo217, -1 ,nullptr }, // Inst #1203 = C_NGE_D64_MM |
| { 1204, 3, 1, 4, 633, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo218, -1 ,nullptr }, // Inst #1204 = C_NGE_S |
| { 1205, 3, 1, 4, 1251, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo218, -1 ,nullptr }, // Inst #1205 = C_NGE_S_MM |
| { 1206, 3, 1, 4, 632, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo216, -1 ,nullptr }, // Inst #1206 = C_NGLE_D32 |
| { 1207, 3, 1, 4, 1252, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo216, -1 ,nullptr }, // Inst #1207 = C_NGLE_D32_MM |
| { 1208, 3, 1, 4, 632, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo217, -1 ,nullptr }, // Inst #1208 = C_NGLE_D64 |
| { 1209, 3, 1, 4, 1252, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo217, -1 ,nullptr }, // Inst #1209 = C_NGLE_D64_MM |
| { 1210, 3, 1, 4, 633, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo218, -1 ,nullptr }, // Inst #1210 = C_NGLE_S |
| { 1211, 3, 1, 4, 1253, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo218, -1 ,nullptr }, // Inst #1211 = C_NGLE_S_MM |
| { 1212, 3, 1, 4, 632, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo216, -1 ,nullptr }, // Inst #1212 = C_NGL_D32 |
| { 1213, 3, 1, 4, 1250, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo216, -1 ,nullptr }, // Inst #1213 = C_NGL_D32_MM |
| { 1214, 3, 1, 4, 632, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo217, -1 ,nullptr }, // Inst #1214 = C_NGL_D64 |
| { 1215, 3, 1, 4, 1250, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo217, -1 ,nullptr }, // Inst #1215 = C_NGL_D64_MM |
| { 1216, 3, 1, 4, 633, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo218, -1 ,nullptr }, // Inst #1216 = C_NGL_S |
| { 1217, 3, 1, 4, 1251, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo218, -1 ,nullptr }, // Inst #1217 = C_NGL_S_MM |
| { 1218, 3, 1, 4, 632, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo216, -1 ,nullptr }, // Inst #1218 = C_NGT_D32 |
| { 1219, 3, 1, 4, 1250, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo216, -1 ,nullptr }, // Inst #1219 = C_NGT_D32_MM |
| { 1220, 3, 1, 4, 632, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo217, -1 ,nullptr }, // Inst #1220 = C_NGT_D64 |
| { 1221, 3, 1, 4, 1250, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo217, -1 ,nullptr }, // Inst #1221 = C_NGT_D64_MM |
| { 1222, 3, 1, 4, 633, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo218, -1 ,nullptr }, // Inst #1222 = C_NGT_S |
| { 1223, 3, 1, 4, 1251, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo218, -1 ,nullptr }, // Inst #1223 = C_NGT_S_MM |
| { 1224, 3, 1, 4, 632, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo216, -1 ,nullptr }, // Inst #1224 = C_OLE_D32 |
| { 1225, 3, 1, 4, 1250, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo216, -1 ,nullptr }, // Inst #1225 = C_OLE_D32_MM |
| { 1226, 3, 1, 4, 632, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo217, -1 ,nullptr }, // Inst #1226 = C_OLE_D64 |
| { 1227, 3, 1, 4, 1250, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo217, -1 ,nullptr }, // Inst #1227 = C_OLE_D64_MM |
| { 1228, 3, 1, 4, 633, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo218, -1 ,nullptr }, // Inst #1228 = C_OLE_S |
| { 1229, 3, 1, 4, 1251, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo218, -1 ,nullptr }, // Inst #1229 = C_OLE_S_MM |
| { 1230, 3, 1, 4, 632, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo216, -1 ,nullptr }, // Inst #1230 = C_OLT_D32 |
| { 1231, 3, 1, 4, 1250, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo216, -1 ,nullptr }, // Inst #1231 = C_OLT_D32_MM |
| { 1232, 3, 1, 4, 632, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo217, -1 ,nullptr }, // Inst #1232 = C_OLT_D64 |
| { 1233, 3, 1, 4, 1250, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo217, -1 ,nullptr }, // Inst #1233 = C_OLT_D64_MM |
| { 1234, 3, 1, 4, 633, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo218, -1 ,nullptr }, // Inst #1234 = C_OLT_S |
| { 1235, 3, 1, 4, 1251, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo218, -1 ,nullptr }, // Inst #1235 = C_OLT_S_MM |
| { 1236, 3, 1, 4, 632, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo216, -1 ,nullptr }, // Inst #1236 = C_SEQ_D32 |
| { 1237, 3, 1, 4, 1250, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo216, -1 ,nullptr }, // Inst #1237 = C_SEQ_D32_MM |
| { 1238, 3, 1, 4, 632, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo217, -1 ,nullptr }, // Inst #1238 = C_SEQ_D64 |
| { 1239, 3, 1, 4, 1250, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo217, -1 ,nullptr }, // Inst #1239 = C_SEQ_D64_MM |
| { 1240, 3, 1, 4, 633, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo218, -1 ,nullptr }, // Inst #1240 = C_SEQ_S |
| { 1241, 3, 1, 4, 1251, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo218, -1 ,nullptr }, // Inst #1241 = C_SEQ_S_MM |
| { 1242, 3, 1, 4, 632, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo216, -1 ,nullptr }, // Inst #1242 = C_SF_D32 |
| { 1243, 3, 1, 4, 1248, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo216, -1 ,nullptr }, // Inst #1243 = C_SF_D32_MM |
| { 1244, 3, 1, 4, 632, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo217, -1 ,nullptr }, // Inst #1244 = C_SF_D64 |
| { 1245, 3, 1, 4, 1248, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo217, -1 ,nullptr }, // Inst #1245 = C_SF_D64_MM |
| { 1246, 3, 1, 4, 633, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo218, -1 ,nullptr }, // Inst #1246 = C_SF_S |
| { 1247, 3, 1, 4, 1249, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo218, -1 ,nullptr }, // Inst #1247 = C_SF_S_MM |
| { 1248, 3, 1, 4, 632, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo216, -1 ,nullptr }, // Inst #1248 = C_UEQ_D32 |
| { 1249, 3, 1, 4, 1250, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo216, -1 ,nullptr }, // Inst #1249 = C_UEQ_D32_MM |
| { 1250, 3, 1, 4, 632, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo217, -1 ,nullptr }, // Inst #1250 = C_UEQ_D64 |
| { 1251, 3, 1, 4, 1250, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo217, -1 ,nullptr }, // Inst #1251 = C_UEQ_D64_MM |
| { 1252, 3, 1, 4, 633, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo218, -1 ,nullptr }, // Inst #1252 = C_UEQ_S |
| { 1253, 3, 1, 4, 1251, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo218, -1 ,nullptr }, // Inst #1253 = C_UEQ_S_MM |
| { 1254, 3, 1, 4, 632, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo216, -1 ,nullptr }, // Inst #1254 = C_ULE_D32 |
| { 1255, 3, 1, 4, 1250, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo216, -1 ,nullptr }, // Inst #1255 = C_ULE_D32_MM |
| { 1256, 3, 1, 4, 632, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo217, -1 ,nullptr }, // Inst #1256 = C_ULE_D64 |
| { 1257, 3, 1, 4, 1250, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo217, -1 ,nullptr }, // Inst #1257 = C_ULE_D64_MM |
| { 1258, 3, 1, 4, 633, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo218, -1 ,nullptr }, // Inst #1258 = C_ULE_S |
| { 1259, 3, 1, 4, 1251, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo218, -1 ,nullptr }, // Inst #1259 = C_ULE_S_MM |
| { 1260, 3, 1, 4, 632, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo216, -1 ,nullptr }, // Inst #1260 = C_ULT_D32 |
| { 1261, 3, 1, 4, 1250, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo216, -1 ,nullptr }, // Inst #1261 = C_ULT_D32_MM |
| { 1262, 3, 1, 4, 632, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo217, -1 ,nullptr }, // Inst #1262 = C_ULT_D64 |
| { 1263, 3, 1, 4, 1250, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo217, -1 ,nullptr }, // Inst #1263 = C_ULT_D64_MM |
| { 1264, 3, 1, 4, 633, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo218, -1 ,nullptr }, // Inst #1264 = C_ULT_S |
| { 1265, 3, 1, 4, 1251, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo218, -1 ,nullptr }, // Inst #1265 = C_ULT_S_MM |
| { 1266, 3, 1, 4, 632, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo216, -1 ,nullptr }, // Inst #1266 = C_UN_D32 |
| { 1267, 3, 1, 4, 1248, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo216, -1 ,nullptr }, // Inst #1267 = C_UN_D32_MM |
| { 1268, 3, 1, 4, 632, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo217, -1 ,nullptr }, // Inst #1268 = C_UN_D64 |
| { 1269, 3, 1, 4, 1248, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo217, -1 ,nullptr }, // Inst #1269 = C_UN_D64_MM |
| { 1270, 3, 1, 4, 633, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo218, -1 ,nullptr }, // Inst #1270 = C_UN_S |
| { 1271, 3, 1, 4, 1249, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL, nullptr, nullptr, OperandInfo218, -1 ,nullptr }, // Inst #1271 = C_UN_S_MM |
| { 1272, 2, 0, 2, 727, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList7, OperandInfo121, -1 ,nullptr }, // Inst #1272 = CmpRxRy16 |
| { 1273, 2, 0, 2, 727, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList7, OperandInfo173, -1 ,nullptr }, // Inst #1273 = CmpiRxImm16 |
| { 1274, 2, 0, 4, 727, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList7, OperandInfo173, -1 ,nullptr }, // Inst #1274 = CmpiRxImmX16 |
| { 1275, 3, 1, 4, 808, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #1275 = DADD |
| { 1276, 3, 1, 4, 809, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #1276 = DADDi |
| { 1277, 3, 1, 4, 810, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #1277 = DADDiu |
| { 1278, 3, 1, 4, 811, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #1278 = DADDu |
| { 1279, 3, 1, 4, 837, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo219, -1 ,nullptr }, // Inst #1279 = DAHI |
| { 1280, 4, 1, 4, 836, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo220, -1 ,nullptr }, // Inst #1280 = DALIGN |
| { 1281, 3, 1, 4, 838, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo219, -1 ,nullptr }, // Inst #1281 = DATI |
| { 1282, 3, 1, 4, 839, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #1282 = DAUI |
| { 1283, 2, 1, 4, 842, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo113, -1 ,nullptr }, // Inst #1283 = DBITSWAP |
| { 1284, 2, 1, 4, 812, 0, 0x1ULL, nullptr, nullptr, OperandInfo113, -1 ,nullptr }, // Inst #1284 = DCLO |
| { 1285, 2, 1, 4, 840, 0, 0x6ULL, nullptr, nullptr, OperandInfo113, -1 ,nullptr }, // Inst #1285 = DCLO_R6 |
| { 1286, 2, 1, 4, 813, 0, 0x1ULL, nullptr, nullptr, OperandInfo113, -1 ,nullptr }, // Inst #1286 = DCLZ |
| { 1287, 2, 1, 4, 841, 0, 0x6ULL, nullptr, nullptr, OperandInfo113, -1 ,nullptr }, // Inst #1287 = DCLZ_R6 |
| { 1288, 3, 1, 4, 907, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #1288 = DDIV |
| { 1289, 3, 1, 4, 909, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #1289 = DDIVU |
| { 1290, 0, 0, 4, 375, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1290 = DERET |
| { 1291, 0, 0, 4, 944, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1291 = DERET_MM |
| { 1292, 0, 0, 4, 980, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1292 = DERET_MMR6 |
| { 1293, 4, 1, 4, 814, 0, 0x1ULL, nullptr, nullptr, OperandInfo201, -1 ,nullptr }, // Inst #1293 = DEXT |
| { 1294, 4, 1, 4, 799, 0, 0x1ULL, nullptr, nullptr, OperandInfo202, -1 ,nullptr }, // Inst #1294 = DEXT64_32 |
| { 1295, 4, 1, 4, 814, 0, 0x1ULL, nullptr, nullptr, OperandInfo201, -1 ,nullptr }, // Inst #1295 = DEXTM |
| { 1296, 4, 1, 4, 814, 0, 0x1ULL, nullptr, nullptr, OperandInfo201, -1 ,nullptr }, // Inst #1296 = DEXTU |
| { 1297, 1, 1, 4, 471, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #1297 = DI |
| { 1298, 5, 1, 4, 815, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo221, -1 ,nullptr }, // Inst #1298 = DINS |
| { 1299, 5, 1, 4, 815, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo221, -1 ,nullptr }, // Inst #1299 = DINSM |
| { 1300, 5, 1, 4, 815, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo221, -1 ,nullptr }, // Inst #1300 = DINSU |
| { 1301, 3, 1, 4, 479, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #1301 = DIV |
| { 1302, 3, 1, 4, 480, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #1302 = DIVU |
| { 1303, 3, 1, 4, 890, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UsesCustomInserter), 0x6ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #1303 = DIVU_MMR6 |
| { 1304, 3, 1, 4, 891, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UsesCustomInserter), 0x6ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #1304 = DIV_MMR6 |
| { 1305, 3, 1, 4, 609, 0, 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #1305 = DIV_S_B |
| { 1306, 3, 1, 4, 609, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1306 = DIV_S_D |
| { 1307, 3, 1, 4, 609, 0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #1307 = DIV_S_H |
| { 1308, 3, 1, 4, 609, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1308 = DIV_S_W |
| { 1309, 3, 1, 4, 609, 0, 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #1309 = DIV_U_B |
| { 1310, 3, 1, 4, 609, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1310 = DIV_U_D |
| { 1311, 3, 1, 4, 609, 0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #1311 = DIV_U_H |
| { 1312, 3, 1, 4, 609, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1312 = DIV_U_W |
| { 1313, 1, 1, 4, 1023, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #1313 = DI_MM |
| { 1314, 1, 1, 4, 1040, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #1314 = DI_MMR6 |
| { 1315, 4, 1, 4, 843, 0, 0x6ULL, nullptr, nullptr, OperandInfo220, -1 ,nullptr }, // Inst #1315 = DLSA |
| { 1316, 4, 1, 4, 843, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo220, -1 ,nullptr }, // Inst #1316 = DLSA_R6 |
| { 1317, 3, 1, 4, 1045, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo222, -1 ,nullptr }, // Inst #1317 = DMFC0 |
| { 1318, 2, 1, 4, 1329, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast), 0x4ULL, nullptr, nullptr, OperandInfo223, -1 ,nullptr }, // Inst #1318 = DMFC1 |
| { 1319, 3, 1, 4, 1047, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo224, -1 ,nullptr }, // Inst #1319 = DMFC2 |
| { 1320, 2, 2, 4, 1193, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo103, -1 ,nullptr }, // Inst #1320 = DMFC2_OCTEON |
| { 1321, 3, 1, 4, 1059, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo222, -1 ,nullptr }, // Inst #1321 = DMFGC0 |
| { 1322, 3, 1, 4, 908, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #1322 = DMOD |
| { 1323, 3, 1, 4, 910, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #1323 = DMODU |
| { 1324, 1, 1, 4, 1051, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #1324 = DMT |
| { 1325, 3, 1, 4, 1046, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo225, -1 ,nullptr }, // Inst #1325 = DMTC0 |
| { 1326, 2, 1, 4, 1330, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast), 0x4ULL, nullptr, nullptr, OperandInfo125, -1 ,nullptr }, // Inst #1326 = DMTC1 |
| { 1327, 3, 1, 4, 1048, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo226, -1 ,nullptr }, // Inst #1327 = DMTC2 |
| { 1328, 2, 2, 4, 1194, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo103, -1 ,nullptr }, // Inst #1328 = DMTC2_OCTEON |
| { 1329, 3, 1, 4, 1060, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo225, -1 ,nullptr }, // Inst #1329 = DMTGC0 |
| { 1330, 3, 1, 4, 904, 0, 0x6ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #1330 = DMUH |
| { 1331, 3, 1, 4, 905, 0, 0x6ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #1331 = DMUHU |
| { 1332, 3, 1, 4, 1201, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, ImplicitList11, OperandInfo64, -1 ,nullptr }, // Inst #1332 = DMUL |
| { 1333, 2, 0, 4, 894, 0|(1ULL<<MCID::Commutable), 0x1ULL, nullptr, ImplicitList12, OperandInfo113, -1 ,nullptr }, // Inst #1333 = DMULT |
| { 1334, 2, 0, 4, 895, 0|(1ULL<<MCID::Commutable), 0x1ULL, nullptr, ImplicitList12, OperandInfo113, -1 ,nullptr }, // Inst #1334 = DMULTu |
| { 1335, 3, 1, 4, 893, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #1335 = DMULU |
| { 1336, 3, 1, 4, 906, 0, 0x6ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #1336 = DMUL_R6 |
| { 1337, 3, 1, 4, 659, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo227, -1 ,nullptr }, // Inst #1337 = DOTP_S_D |
| { 1338, 3, 1, 4, 659, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo228, -1 ,nullptr }, // Inst #1338 = DOTP_S_H |
| { 1339, 3, 1, 4, 659, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo229, -1 ,nullptr }, // Inst #1339 = DOTP_S_W |
| { 1340, 3, 1, 4, 659, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo227, -1 ,nullptr }, // Inst #1340 = DOTP_U_D |
| { 1341, 3, 1, 4, 659, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo228, -1 ,nullptr }, // Inst #1341 = DOTP_U_H |
| { 1342, 3, 1, 4, 659, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo229, -1 ,nullptr }, // Inst #1342 = DOTP_U_W |
| { 1343, 4, 1, 4, 657, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr }, // Inst #1343 = DPADD_S_D |
| { 1344, 4, 1, 4, 657, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo231, -1 ,nullptr }, // Inst #1344 = DPADD_S_H |
| { 1345, 4, 1, 4, 657, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo232, -1 ,nullptr }, // Inst #1345 = DPADD_S_W |
| { 1346, 4, 1, 4, 657, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr }, // Inst #1346 = DPADD_U_D |
| { 1347, 4, 1, 4, 657, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo231, -1 ,nullptr }, // Inst #1347 = DPADD_U_H |
| { 1348, 4, 1, 4, 657, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo232, -1 ,nullptr }, // Inst #1348 = DPADD_U_W |
| { 1349, 4, 1, 4, 1464, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo233, -1 ,nullptr }, // Inst #1349 = DPAQX_SA_W_PH |
| { 1350, 4, 1, 4, 1628, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo233, -1 ,nullptr }, // Inst #1350 = DPAQX_SA_W_PH_MMR2 |
| { 1351, 4, 1, 4, 1465, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo233, -1 ,nullptr }, // Inst #1351 = DPAQX_S_W_PH |
| { 1352, 4, 1, 4, 1629, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo233, -1 ,nullptr }, // Inst #1352 = DPAQX_S_W_PH_MMR2 |
| { 1353, 4, 1, 4, 1366, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo233, -1 ,nullptr }, // Inst #1353 = DPAQ_SA_L_W |
| { 1354, 4, 1, 4, 1517, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo233, -1 ,nullptr }, // Inst #1354 = DPAQ_SA_L_W_MM |
| { 1355, 4, 1, 4, 1367, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo233, -1 ,nullptr }, // Inst #1355 = DPAQ_S_W_PH |
| { 1356, 4, 1, 4, 1518, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo233, -1 ,nullptr }, // Inst #1356 = DPAQ_S_W_PH_MM |
| { 1357, 4, 1, 4, 1368, 0, 0x6ULL, nullptr, nullptr, OperandInfo233, -1 ,nullptr }, // Inst #1357 = DPAU_H_QBL |
| { 1358, 4, 1, 4, 1519, 0, 0x6ULL, nullptr, nullptr, OperandInfo233, -1 ,nullptr }, // Inst #1358 = DPAU_H_QBL_MM |
| { 1359, 4, 1, 4, 1369, 0, 0x6ULL, nullptr, nullptr, OperandInfo233, -1 ,nullptr }, // Inst #1359 = DPAU_H_QBR |
| { 1360, 4, 1, 4, 1520, 0, 0x6ULL, nullptr, nullptr, OperandInfo233, -1 ,nullptr }, // Inst #1360 = DPAU_H_QBR_MM |
| { 1361, 4, 1, 4, 1466, 0, 0x6ULL, nullptr, nullptr, OperandInfo233, -1 ,nullptr }, // Inst #1361 = DPAX_W_PH |
| { 1362, 4, 1, 4, 1630, 0, 0x6ULL, nullptr, nullptr, OperandInfo233, -1 ,nullptr }, // Inst #1362 = DPAX_W_PH_MMR2 |
| { 1363, 4, 1, 4, 1463, 0, 0x6ULL, nullptr, nullptr, OperandInfo233, -1 ,nullptr }, // Inst #1363 = DPA_W_PH |
| { 1364, 4, 1, 4, 1627, 0, 0x6ULL, nullptr, nullptr, OperandInfo233, -1 ,nullptr }, // Inst #1364 = DPA_W_PH_MMR2 |
| { 1365, 2, 1, 4, 1195, 0, 0x1ULL, nullptr, nullptr, OperandInfo113, -1 ,nullptr }, // Inst #1365 = DPOP |
| { 1366, 4, 1, 4, 1469, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo233, -1 ,nullptr }, // Inst #1366 = DPSQX_SA_W_PH |
| { 1367, 4, 1, 4, 1633, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo233, -1 ,nullptr }, // Inst #1367 = DPSQX_SA_W_PH_MMR2 |
| { 1368, 4, 1, 4, 1468, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo233, -1 ,nullptr }, // Inst #1368 = DPSQX_S_W_PH |
| { 1369, 4, 1, 4, 1632, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo233, -1 ,nullptr }, // Inst #1369 = DPSQX_S_W_PH_MMR2 |
| { 1370, 4, 1, 4, 1370, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo233, -1 ,nullptr }, // Inst #1370 = DPSQ_SA_L_W |
| { 1371, 4, 1, 4, 1521, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo233, -1 ,nullptr }, // Inst #1371 = DPSQ_SA_L_W_MM |
| { 1372, 4, 1, 4, 1371, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo233, -1 ,nullptr }, // Inst #1372 = DPSQ_S_W_PH |
| { 1373, 4, 1, 4, 1522, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo233, -1 ,nullptr }, // Inst #1373 = DPSQ_S_W_PH_MM |
| { 1374, 4, 1, 4, 658, 0, 0x6ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr }, // Inst #1374 = DPSUB_S_D |
| { 1375, 4, 1, 4, 658, 0, 0x6ULL, nullptr, nullptr, OperandInfo231, -1 ,nullptr }, // Inst #1375 = DPSUB_S_H |
| { 1376, 4, 1, 4, 658, 0, 0x6ULL, nullptr, nullptr, OperandInfo232, -1 ,nullptr }, // Inst #1376 = DPSUB_S_W |
| { 1377, 4, 1, 4, 658, 0, 0x6ULL, nullptr, nullptr, OperandInfo230, -1 ,nullptr }, // Inst #1377 = DPSUB_U_D |
| { 1378, 4, 1, 4, 658, 0, 0x6ULL, nullptr, nullptr, OperandInfo231, -1 ,nullptr }, // Inst #1378 = DPSUB_U_H |
| { 1379, 4, 1, 4, 658, 0, 0x6ULL, nullptr, nullptr, OperandInfo232, -1 ,nullptr }, // Inst #1379 = DPSUB_U_W |
| { 1380, 4, 1, 4, 1372, 0, 0x6ULL, nullptr, nullptr, OperandInfo233, -1 ,nullptr }, // Inst #1380 = DPSU_H_QBL |
| { 1381, 4, 1, 4, 1523, 0, 0x6ULL, nullptr, nullptr, OperandInfo233, -1 ,nullptr }, // Inst #1381 = DPSU_H_QBL_MM |
| { 1382, 4, 1, 4, 1373, 0, 0x6ULL, nullptr, nullptr, OperandInfo233, -1 ,nullptr }, // Inst #1382 = DPSU_H_QBR |
| { 1383, 4, 1, 4, 1524, 0, 0x6ULL, nullptr, nullptr, OperandInfo233, -1 ,nullptr }, // Inst #1383 = DPSU_H_QBR_MM |
| { 1384, 4, 1, 4, 1470, 0, 0x6ULL, nullptr, nullptr, OperandInfo233, -1 ,nullptr }, // Inst #1384 = DPSX_W_PH |
| { 1385, 4, 1, 4, 1634, 0, 0x6ULL, nullptr, nullptr, OperandInfo233, -1 ,nullptr }, // Inst #1385 = DPSX_W_PH_MMR2 |
| { 1386, 4, 1, 4, 1467, 0, 0x6ULL, nullptr, nullptr, OperandInfo233, -1 ,nullptr }, // Inst #1386 = DPS_W_PH |
| { 1387, 4, 1, 4, 1631, 0, 0x6ULL, nullptr, nullptr, OperandInfo233, -1 ,nullptr }, // Inst #1387 = DPS_W_PH_MMR2 |
| { 1388, 3, 1, 4, 816, 0, 0x1ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #1388 = DROTR |
| { 1389, 3, 1, 4, 817, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #1389 = DROTR32 |
| { 1390, 3, 1, 4, 818, 0, 0x1ULL, nullptr, nullptr, OperandInfo234, -1 ,nullptr }, // Inst #1390 = DROTRV |
| { 1391, 2, 1, 4, 819, 0, 0x1ULL, nullptr, nullptr, OperandInfo113, -1 ,nullptr }, // Inst #1391 = DSBH |
| { 1392, 2, 0, 4, 896, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, ImplicitList12, OperandInfo113, -1 ,nullptr }, // Inst #1392 = DSDIV |
| { 1393, 2, 1, 4, 820, 0, 0x1ULL, nullptr, nullptr, OperandInfo113, -1 ,nullptr }, // Inst #1393 = DSHD |
| { 1394, 3, 1, 4, 821, 0, 0x1ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #1394 = DSLL |
| { 1395, 3, 1, 4, 822, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #1395 = DSLL32 |
| { 1396, 2, 1, 4, 800, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo235, -1 ,nullptr }, // Inst #1396 = DSLL64_32 |
| { 1397, 3, 1, 4, 823, 0, 0x1ULL, nullptr, nullptr, OperandInfo234, -1 ,nullptr }, // Inst #1397 = DSLLV |
| { 1398, 3, 1, 4, 824, 0, 0x1ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #1398 = DSRA |
| { 1399, 3, 1, 4, 825, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #1399 = DSRA32 |
| { 1400, 3, 1, 4, 826, 0, 0x1ULL, nullptr, nullptr, OperandInfo234, -1 ,nullptr }, // Inst #1400 = DSRAV |
| { 1401, 3, 1, 4, 827, 0, 0x1ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #1401 = DSRL |
| { 1402, 3, 1, 4, 828, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #1402 = DSRL32 |
| { 1403, 3, 1, 4, 829, 0, 0x1ULL, nullptr, nullptr, OperandInfo234, -1 ,nullptr }, // Inst #1403 = DSRLV |
| { 1404, 3, 1, 4, 830, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #1404 = DSUB |
| { 1405, 3, 1, 4, 831, 0|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #1405 = DSUBu |
| { 1406, 2, 0, 4, 897, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, ImplicitList12, OperandInfo113, -1 ,nullptr }, // Inst #1406 = DUDIV |
| { 1407, 1, 1, 4, 1018, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #1407 = DVP |
| { 1408, 1, 1, 4, 1052, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #1408 = DVPE |
| { 1409, 1, 1, 4, 1039, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #1409 = DVP_MMR6 |
| { 1410, 2, 0, 2, 868, 0, 0x0ULL, nullptr, ImplicitList6, OperandInfo121, -1 ,nullptr }, // Inst #1410 = DivRxRy16 |
| { 1411, 2, 0, 2, 869, 0, 0x0ULL, nullptr, ImplicitList6, OperandInfo121, -1 ,nullptr }, // Inst #1411 = DivuRxRy16 |
| { 1412, 0, 0, 4, 474, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1412 = EHB |
| { 1413, 0, 0, 4, 1025, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1413 = EHB_MM |
| { 1414, 0, 0, 4, 1042, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1414 = EHB_MMR6 |
| { 1415, 1, 1, 4, 472, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #1415 = EI |
| { 1416, 1, 1, 4, 1024, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #1416 = EI_MM |
| { 1417, 1, 1, 4, 1041, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #1417 = EI_MMR6 |
| { 1418, 1, 1, 4, 1053, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #1418 = EMT |
| { 1419, 0, 0, 4, 376, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1419 = ERET |
| { 1420, 0, 0, 4, 378, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1420 = ERETNC |
| { 1421, 0, 0, 4, 981, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1421 = ERETNC_MMR6 |
| { 1422, 0, 0, 4, 945, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1422 = ERET_MM |
| { 1423, 0, 0, 4, 983, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1423 = ERET_MMR6 |
| { 1424, 1, 1, 4, 1017, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #1424 = EVP |
| { 1425, 1, 1, 4, 1054, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #1425 = EVPE |
| { 1426, 1, 1, 4, 1038, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #1426 = EVP_MMR6 |
| { 1427, 4, 1, 4, 489, 0, 0x1ULL, nullptr, nullptr, OperandInfo203, -1 ,nullptr }, // Inst #1427 = EXT |
| { 1428, 3, 1, 4, 1377, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList4, ImplicitList14, OperandInfo236, -1 ,nullptr }, // Inst #1428 = EXTP |
| { 1429, 3, 1, 4, 1375, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList4, ImplicitList15, OperandInfo236, -1 ,nullptr }, // Inst #1429 = EXTPDP |
| { 1430, 3, 1, 4, 1374, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList4, ImplicitList15, OperandInfo237, -1 ,nullptr }, // Inst #1430 = EXTPDPV |
| { 1431, 3, 1, 4, 1525, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList4, ImplicitList15, OperandInfo237, -1 ,nullptr }, // Inst #1431 = EXTPDPV_MM |
| { 1432, 3, 1, 4, 1526, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList4, ImplicitList15, OperandInfo236, -1 ,nullptr }, // Inst #1432 = EXTPDP_MM |
| { 1433, 3, 1, 4, 1376, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList4, ImplicitList14, OperandInfo237, -1 ,nullptr }, // Inst #1433 = EXTPV |
| { 1434, 3, 1, 4, 1527, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList4, ImplicitList14, OperandInfo237, -1 ,nullptr }, // Inst #1434 = EXTPV_MM |
| { 1435, 3, 1, 4, 1528, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, ImplicitList4, ImplicitList14, OperandInfo236, -1 ,nullptr }, // Inst #1435 = EXTP_MM |
| { 1436, 3, 1, 4, 1334, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList16, OperandInfo237, -1 ,nullptr }, // Inst #1436 = EXTRV_RS_W |
| { 1437, 3, 1, 4, 1529, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList16, OperandInfo237, -1 ,nullptr }, // Inst #1437 = EXTRV_RS_W_MM |
| { 1438, 3, 1, 4, 1335, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList16, OperandInfo237, -1 ,nullptr }, // Inst #1438 = EXTRV_R_W |
| { 1439, 3, 1, 4, 1530, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList16, OperandInfo237, -1 ,nullptr }, // Inst #1439 = EXTRV_R_W_MM |
| { 1440, 3, 1, 4, 1336, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList16, OperandInfo237, -1 ,nullptr }, // Inst #1440 = EXTRV_S_H |
| { 1441, 3, 1, 4, 1531, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList16, OperandInfo237, -1 ,nullptr }, // Inst #1441 = EXTRV_S_H_MM |
| { 1442, 3, 1, 4, 1337, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList16, OperandInfo237, -1 ,nullptr }, // Inst #1442 = EXTRV_W |
| { 1443, 3, 1, 4, 1532, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList16, OperandInfo237, -1 ,nullptr }, // Inst #1443 = EXTRV_W_MM |
| { 1444, 3, 1, 4, 1338, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList16, OperandInfo236, -1 ,nullptr }, // Inst #1444 = EXTR_RS_W |
| { 1445, 3, 1, 4, 1533, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList16, OperandInfo236, -1 ,nullptr }, // Inst #1445 = EXTR_RS_W_MM |
| { 1446, 3, 1, 4, 1339, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList16, OperandInfo236, -1 ,nullptr }, // Inst #1446 = EXTR_R_W |
| { 1447, 3, 1, 4, 1534, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList16, OperandInfo236, -1 ,nullptr }, // Inst #1447 = EXTR_R_W_MM |
| { 1448, 3, 1, 4, 1340, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList16, OperandInfo236, -1 ,nullptr }, // Inst #1448 = EXTR_S_H |
| { 1449, 3, 1, 4, 1535, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList16, OperandInfo236, -1 ,nullptr }, // Inst #1449 = EXTR_S_H_MM |
| { 1450, 3, 1, 4, 1341, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList16, OperandInfo236, -1 ,nullptr }, // Inst #1450 = EXTR_W |
| { 1451, 3, 1, 4, 1536, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList16, OperandInfo236, -1 ,nullptr }, // Inst #1451 = EXTR_W_MM |
| { 1452, 4, 1, 4, 1196, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo201, -1 ,nullptr }, // Inst #1452 = EXTS |
| { 1453, 4, 1, 4, 1196, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo201, -1 ,nullptr }, // Inst #1453 = EXTS32 |
| { 1454, 4, 1, 4, 738, 0, 0x1ULL, nullptr, nullptr, OperandInfo203, -1 ,nullptr }, // Inst #1454 = EXT_MM |
| { 1455, 4, 1, 4, 779, 0, 0x1ULL, nullptr, nullptr, OperandInfo203, -1 ,nullptr }, // Inst #1455 = EXT_MMR6 |
| { 1456, 2, 1, 4, 525, 0, 0x4ULL, nullptr, nullptr, OperandInfo238, -1 ,nullptr }, // Inst #1456 = FABS_D32 |
| { 1457, 2, 1, 4, 1260, 0, 0x4ULL, nullptr, nullptr, OperandInfo238, -1 ,nullptr }, // Inst #1457 = FABS_D32_MM |
| { 1458, 2, 1, 4, 525, 0, 0x4ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #1458 = FABS_D64 |
| { 1459, 2, 1, 4, 1260, 0, 0x4ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #1459 = FABS_D64_MM |
| { 1460, 2, 1, 4, 525, 0, 0x4ULL, nullptr, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #1460 = FABS_S |
| { 1461, 2, 1, 4, 1261, 0, 0x4ULL, nullptr, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #1461 = FABS_S_MM |
| { 1462, 3, 1, 4, 655, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1462 = FADD_D |
| { 1463, 3, 1, 4, 623, 0|(1ULL<<MCID::Commutable), 0x4ULL, nullptr, nullptr, OperandInfo239, -1 ,nullptr }, // Inst #1463 = FADD_D32 |
| { 1464, 3, 1, 4, 1263, 0|(1ULL<<MCID::Commutable), 0x4ULL, nullptr, nullptr, OperandInfo239, -1 ,nullptr }, // Inst #1464 = FADD_D32_MM |
| { 1465, 3, 1, 4, 623, 0|(1ULL<<MCID::Commutable), 0x4ULL, nullptr, nullptr, OperandInfo240, -1 ,nullptr }, // Inst #1465 = FADD_D64 |
| { 1466, 3, 1, 4, 1263, 0|(1ULL<<MCID::Commutable), 0x4ULL, nullptr, nullptr, OperandInfo240, -1 ,nullptr }, // Inst #1466 = FADD_D64_MM |
| { 1467, 3, 1, 4, 624, 0|(1ULL<<MCID::Commutable), 0x4ULL, nullptr, nullptr, OperandInfo241, -1 ,nullptr }, // Inst #1467 = FADD_S |
| { 1468, 3, 1, 4, 1264, 0|(1ULL<<MCID::Commutable), 0x4ULL, nullptr, nullptr, OperandInfo241, -1 ,nullptr }, // Inst #1468 = FADD_S_MM |
| { 1469, 3, 1, 4, 1304, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo241, -1 ,nullptr }, // Inst #1469 = FADD_S_MMR6 |
| { 1470, 3, 1, 4, 655, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1470 = FADD_W |
| { 1471, 3, 1, 4, 572, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1471 = FCAF_D |
| { 1472, 3, 1, 4, 572, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1472 = FCAF_W |
| { 1473, 3, 1, 4, 573, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1473 = FCEQ_D |
| { 1474, 3, 1, 4, 573, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1474 = FCEQ_W |
| { 1475, 2, 1, 4, 594, 0, 0x6ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #1475 = FCLASS_D |
| { 1476, 2, 1, 4, 594, 0, 0x6ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr }, // Inst #1476 = FCLASS_W |
| { 1477, 3, 1, 4, 574, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1477 = FCLE_D |
| { 1478, 3, 1, 4, 574, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1478 = FCLE_W |
| { 1479, 3, 1, 4, 575, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1479 = FCLT_D |
| { 1480, 3, 1, 4, 575, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1480 = FCLT_W |
| { 1481, 3, 0, 4, 634, 0, 0x44ULL, nullptr, ImplicitList17, OperandInfo242, -1 ,nullptr }, // Inst #1481 = FCMP_D32 |
| { 1482, 3, 0, 4, 1255, 0, 0x44ULL, nullptr, ImplicitList17, OperandInfo242, -1 ,nullptr }, // Inst #1482 = FCMP_D32_MM |
| { 1483, 3, 0, 4, 634, 0, 0x44ULL, nullptr, ImplicitList17, OperandInfo243, -1 ,nullptr }, // Inst #1483 = FCMP_D64 |
| { 1484, 3, 0, 4, 635, 0, 0x44ULL, nullptr, ImplicitList17, OperandInfo244, -1 ,nullptr }, // Inst #1484 = FCMP_S32 |
| { 1485, 3, 0, 4, 1254, 0, 0x44ULL, nullptr, ImplicitList17, OperandInfo244, -1 ,nullptr }, // Inst #1485 = FCMP_S32_MM |
| { 1486, 3, 1, 4, 576, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1486 = FCNE_D |
| { 1487, 3, 1, 4, 576, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1487 = FCNE_W |
| { 1488, 3, 1, 4, 577, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1488 = FCOR_D |
| { 1489, 3, 1, 4, 577, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1489 = FCOR_W |
| { 1490, 3, 1, 4, 578, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1490 = FCUEQ_D |
| { 1491, 3, 1, 4, 578, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1491 = FCUEQ_W |
| { 1492, 3, 1, 4, 579, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1492 = FCULE_D |
| { 1493, 3, 1, 4, 579, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1493 = FCULE_W |
| { 1494, 3, 1, 4, 580, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1494 = FCULT_D |
| { 1495, 3, 1, 4, 580, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1495 = FCULT_W |
| { 1496, 3, 1, 4, 581, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1496 = FCUNE_D |
| { 1497, 3, 1, 4, 581, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1497 = FCUNE_W |
| { 1498, 3, 1, 4, 582, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1498 = FCUN_D |
| { 1499, 3, 1, 4, 582, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1499 = FCUN_W |
| { 1500, 3, 1, 4, 651, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1500 = FDIV_D |
| { 1501, 3, 1, 4, 639, 0, 0x4ULL, nullptr, nullptr, OperandInfo239, -1 ,nullptr }, // Inst #1501 = FDIV_D32 |
| { 1502, 3, 1, 4, 1274, 0, 0x4ULL, nullptr, nullptr, OperandInfo239, -1 ,nullptr }, // Inst #1502 = FDIV_D32_MM |
| { 1503, 3, 1, 4, 639, 0, 0x4ULL, nullptr, nullptr, OperandInfo240, -1 ,nullptr }, // Inst #1503 = FDIV_D64 |
| { 1504, 3, 1, 4, 1274, 0, 0x4ULL, nullptr, nullptr, OperandInfo240, -1 ,nullptr }, // Inst #1504 = FDIV_D64_MM |
| { 1505, 3, 1, 4, 638, 0, 0x4ULL, nullptr, nullptr, OperandInfo241, -1 ,nullptr }, // Inst #1505 = FDIV_S |
| { 1506, 3, 1, 4, 1273, 0, 0x4ULL, nullptr, nullptr, OperandInfo241, -1 ,nullptr }, // Inst #1506 = FDIV_S_MM |
| { 1507, 3, 1, 4, 1326, 0, 0x6ULL, nullptr, nullptr, OperandInfo241, -1 ,nullptr }, // Inst #1507 = FDIV_S_MMR6 |
| { 1508, 3, 1, 4, 650, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1508 = FDIV_W |
| { 1509, 3, 1, 4, 591, 0, 0x6ULL, nullptr, nullptr, OperandInfo245, -1 ,nullptr }, // Inst #1509 = FEXDO_H |
| { 1510, 3, 1, 4, 591, 0, 0x6ULL, nullptr, nullptr, OperandInfo246, -1 ,nullptr }, // Inst #1510 = FEXDO_W |
| { 1511, 3, 1, 4, 548, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1511 = FEXP2_D |
| { 1512, 3, 1, 4, 548, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1512 = FEXP2_W |
| { 1513, 2, 1, 4, 592, 0, 0x6ULL, nullptr, nullptr, OperandInfo247, -1 ,nullptr }, // Inst #1513 = FEXUPL_D |
| { 1514, 2, 1, 4, 592, 0, 0x6ULL, nullptr, nullptr, OperandInfo248, -1 ,nullptr }, // Inst #1514 = FEXUPL_W |
| { 1515, 2, 1, 4, 593, 0, 0x6ULL, nullptr, nullptr, OperandInfo247, -1 ,nullptr }, // Inst #1515 = FEXUPR_D |
| { 1516, 2, 1, 4, 593, 0, 0x6ULL, nullptr, nullptr, OperandInfo248, -1 ,nullptr }, // Inst #1516 = FEXUPR_W |
| { 1517, 2, 1, 4, 584, 0, 0x6ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #1517 = FFINT_S_D |
| { 1518, 2, 1, 4, 584, 0, 0x6ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr }, // Inst #1518 = FFINT_S_W |
| { 1519, 2, 1, 4, 584, 0, 0x6ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #1519 = FFINT_U_D |
| { 1520, 2, 1, 4, 584, 0, 0x6ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr }, // Inst #1520 = FFINT_U_W |
| { 1521, 2, 1, 4, 585, 0, 0x6ULL, nullptr, nullptr, OperandInfo247, -1 ,nullptr }, // Inst #1521 = FFQL_D |
| { 1522, 2, 1, 4, 585, 0, 0x6ULL, nullptr, nullptr, OperandInfo248, -1 ,nullptr }, // Inst #1522 = FFQL_W |
| { 1523, 2, 1, 4, 586, 0, 0x6ULL, nullptr, nullptr, OperandInfo247, -1 ,nullptr }, // Inst #1523 = FFQR_D |
| { 1524, 2, 1, 4, 586, 0, 0x6ULL, nullptr, nullptr, OperandInfo248, -1 ,nullptr }, // Inst #1524 = FFQR_W |
| { 1525, 2, 1, 4, 539, 0, 0x6ULL, nullptr, nullptr, OperandInfo249, -1 ,nullptr }, // Inst #1525 = FILL_B |
| { 1526, 2, 1, 4, 539, 0, 0x6ULL, nullptr, nullptr, OperandInfo250, -1 ,nullptr }, // Inst #1526 = FILL_D |
| { 1527, 2, 1, 4, 539, 0, 0x6ULL, nullptr, nullptr, OperandInfo251, -1 ,nullptr }, // Inst #1527 = FILL_H |
| { 1528, 2, 1, 4, 539, 0, 0x6ULL, nullptr, nullptr, OperandInfo252, -1 ,nullptr }, // Inst #1528 = FILL_W |
| { 1529, 2, 1, 4, 599, 0, 0x6ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #1529 = FLOG2_D |
| { 1530, 2, 1, 4, 599, 0, 0x6ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr }, // Inst #1530 = FLOG2_W |
| { 1531, 2, 1, 4, 710, 0, 0x4ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #1531 = FLOOR_L_D64 |
| { 1532, 2, 1, 4, 1299, 0, 0x4ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #1532 = FLOOR_L_D_MMR6 |
| { 1533, 2, 1, 4, 710, 0, 0x4ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr }, // Inst #1533 = FLOOR_L_S |
| { 1534, 2, 1, 4, 1299, 0, 0x4ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr }, // Inst #1534 = FLOOR_L_S_MMR6 |
| { 1535, 2, 1, 4, 710, 0, 0x4ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1535 = FLOOR_W_D32 |
| { 1536, 2, 1, 4, 710, 0, 0x4ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr }, // Inst #1536 = FLOOR_W_D64 |
| { 1537, 2, 1, 4, 1299, 0, 0x4ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1537 = FLOOR_W_D_MMR6 |
| { 1538, 2, 1, 4, 1237, 0, 0x4ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #1538 = FLOOR_W_MM |
| { 1539, 2, 1, 4, 710, 0, 0x4ULL, nullptr, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #1539 = FLOOR_W_S |
| { 1540, 2, 1, 4, 1237, 0, 0x4ULL, nullptr, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #1540 = FLOOR_W_S_MM |
| { 1541, 2, 1, 4, 1299, 0, 0x4ULL, nullptr, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #1541 = FLOOR_W_S_MMR6 |
| { 1542, 4, 1, 4, 648, 0, 0x6ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #1542 = FMADD_D |
| { 1543, 4, 1, 4, 648, 0, 0x6ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #1543 = FMADD_W |
| { 1544, 3, 1, 4, 595, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1544 = FMAX_A_D |
| { 1545, 3, 1, 4, 595, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1545 = FMAX_A_W |
| { 1546, 3, 1, 4, 596, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1546 = FMAX_D |
| { 1547, 3, 1, 4, 596, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1547 = FMAX_W |
| { 1548, 3, 1, 4, 597, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1548 = FMIN_A_D |
| { 1549, 3, 1, 4, 597, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1549 = FMIN_A_W |
| { 1550, 3, 1, 4, 598, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1550 = FMIN_D |
| { 1551, 3, 1, 4, 598, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1551 = FMIN_W |
| { 1552, 2, 1, 4, 530, 0|(1ULL<<MCID::MoveReg), 0x4ULL, nullptr, nullptr, OperandInfo238, -1 ,nullptr }, // Inst #1552 = FMOV_D32 |
| { 1553, 2, 1, 4, 1265, 0, 0x4ULL, nullptr, nullptr, OperandInfo238, -1 ,nullptr }, // Inst #1553 = FMOV_D32_MM |
| { 1554, 2, 1, 4, 530, 0|(1ULL<<MCID::MoveReg), 0x4ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #1554 = FMOV_D64 |
| { 1555, 2, 1, 4, 1265, 0, 0x4ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #1555 = FMOV_D64_MM |
| { 1556, 2, 1, 4, 1325, 0, 0x4ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #1556 = FMOV_D_MMR6 |
| { 1557, 2, 1, 4, 531, 0|(1ULL<<MCID::MoveReg), 0x4ULL, nullptr, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #1557 = FMOV_S |
| { 1558, 2, 1, 4, 1266, 0|(1ULL<<MCID::MoveReg), 0x4ULL, nullptr, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #1558 = FMOV_S_MM |
| { 1559, 2, 1, 4, 1322, 0, 0x4ULL, nullptr, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #1559 = FMOV_S_MMR6 |
| { 1560, 4, 1, 4, 649, 0, 0x6ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #1560 = FMSUB_D |
| { 1561, 4, 1, 4, 649, 0, 0x6ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #1561 = FMSUB_W |
| { 1562, 3, 1, 4, 654, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1562 = FMUL_D |
| { 1563, 3, 1, 4, 625, 0|(1ULL<<MCID::Commutable), 0x4ULL, nullptr, nullptr, OperandInfo239, -1 ,nullptr }, // Inst #1563 = FMUL_D32 |
| { 1564, 3, 1, 4, 1267, 0|(1ULL<<MCID::Commutable), 0x4ULL, nullptr, nullptr, OperandInfo239, -1 ,nullptr }, // Inst #1564 = FMUL_D32_MM |
| { 1565, 3, 1, 4, 625, 0|(1ULL<<MCID::Commutable), 0x4ULL, nullptr, nullptr, OperandInfo240, -1 ,nullptr }, // Inst #1565 = FMUL_D64 |
| { 1566, 3, 1, 4, 1267, 0|(1ULL<<MCID::Commutable), 0x4ULL, nullptr, nullptr, OperandInfo240, -1 ,nullptr }, // Inst #1566 = FMUL_D64_MM |
| { 1567, 3, 1, 4, 626, 0|(1ULL<<MCID::Commutable), 0x4ULL, nullptr, nullptr, OperandInfo241, -1 ,nullptr }, // Inst #1567 = FMUL_S |
| { 1568, 3, 1, 4, 1268, 0|(1ULL<<MCID::Commutable), 0x4ULL, nullptr, nullptr, OperandInfo241, -1 ,nullptr }, // Inst #1568 = FMUL_S_MM |
| { 1569, 3, 1, 4, 1323, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo241, -1 ,nullptr }, // Inst #1569 = FMUL_S_MMR6 |
| { 1570, 3, 1, 4, 654, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1570 = FMUL_W |
| { 1571, 2, 1, 4, 532, 0, 0x4ULL, nullptr, nullptr, OperandInfo238, -1 ,nullptr }, // Inst #1571 = FNEG_D32 |
| { 1572, 2, 1, 4, 1262, 0, 0x4ULL, nullptr, nullptr, OperandInfo238, -1 ,nullptr }, // Inst #1572 = FNEG_D32_MM |
| { 1573, 2, 1, 4, 532, 0, 0x4ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #1573 = FNEG_D64 |
| { 1574, 2, 1, 4, 1262, 0, 0x4ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #1574 = FNEG_D64_MM |
| { 1575, 2, 1, 4, 532, 0, 0x4ULL, nullptr, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #1575 = FNEG_S |
| { 1576, 2, 1, 4, 1262, 0, 0x4ULL, nullptr, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #1576 = FNEG_S_MM |
| { 1577, 2, 1, 4, 1289, 0, 0x4ULL, nullptr, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #1577 = FNEG_S_MMR6 |
| { 1578, 3, 2, 4, 1058, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #1578 = FORK |
| { 1579, 2, 1, 4, 642, 0, 0x6ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #1579 = FRCP_D |
| { 1580, 2, 1, 4, 642, 0, 0x6ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr }, // Inst #1580 = FRCP_W |
| { 1581, 2, 1, 4, 588, 0, 0x6ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #1581 = FRINT_D |
| { 1582, 2, 1, 4, 588, 0, 0x6ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr }, // Inst #1582 = FRINT_W |
| { 1583, 2, 1, 4, 643, 0, 0x6ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #1583 = FRSQRT_D |
| { 1584, 2, 1, 4, 643, 0, 0x6ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr }, // Inst #1584 = FRSQRT_W |
| { 1585, 3, 1, 4, 566, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1585 = FSAF_D |
| { 1586, 3, 1, 4, 566, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1586 = FSAF_W |
| { 1587, 3, 1, 4, 566, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1587 = FSEQ_D |
| { 1588, 3, 1, 4, 566, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1588 = FSEQ_W |
| { 1589, 3, 1, 4, 566, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1589 = FSLE_D |
| { 1590, 3, 1, 4, 566, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1590 = FSLE_W |
| { 1591, 3, 1, 4, 566, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1591 = FSLT_D |
| { 1592, 3, 1, 4, 566, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1592 = FSLT_W |
| { 1593, 3, 1, 4, 566, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1593 = FSNE_D |
| { 1594, 3, 1, 4, 566, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1594 = FSNE_W |
| { 1595, 3, 1, 4, 566, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1595 = FSOR_D |
| { 1596, 3, 1, 4, 566, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1596 = FSOR_W |
| { 1597, 2, 1, 4, 653, 0, 0x6ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #1597 = FSQRT_D |
| { 1598, 2, 1, 4, 641, 0, 0x4ULL, nullptr, nullptr, OperandInfo238, -1 ,nullptr }, // Inst #1598 = FSQRT_D32 |
| { 1599, 2, 1, 4, 1276, 0, 0x4ULL, nullptr, nullptr, OperandInfo238, -1 ,nullptr }, // Inst #1599 = FSQRT_D32_MM |
| { 1600, 2, 1, 4, 641, 0, 0x4ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #1600 = FSQRT_D64 |
| { 1601, 2, 1, 4, 1276, 0, 0x4ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #1601 = FSQRT_D64_MM |
| { 1602, 2, 1, 4, 640, 0, 0x4ULL, nullptr, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #1602 = FSQRT_S |
| { 1603, 2, 1, 4, 1275, 0, 0x4ULL, nullptr, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #1603 = FSQRT_S_MM |
| { 1604, 2, 1, 4, 652, 0, 0x6ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr }, // Inst #1604 = FSQRT_W |
| { 1605, 3, 1, 4, 656, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1605 = FSUB_D |
| { 1606, 3, 1, 4, 627, 0, 0x4ULL, nullptr, nullptr, OperandInfo239, -1 ,nullptr }, // Inst #1606 = FSUB_D32 |
| { 1607, 3, 1, 4, 1269, 0, 0x4ULL, nullptr, nullptr, OperandInfo239, -1 ,nullptr }, // Inst #1607 = FSUB_D32_MM |
| { 1608, 3, 1, 4, 627, 0, 0x4ULL, nullptr, nullptr, OperandInfo240, -1 ,nullptr }, // Inst #1608 = FSUB_D64 |
| { 1609, 3, 1, 4, 1269, 0, 0x4ULL, nullptr, nullptr, OperandInfo240, -1 ,nullptr }, // Inst #1609 = FSUB_D64_MM |
| { 1610, 3, 1, 4, 628, 0, 0x4ULL, nullptr, nullptr, OperandInfo241, -1 ,nullptr }, // Inst #1610 = FSUB_S |
| { 1611, 3, 1, 4, 1270, 0, 0x4ULL, nullptr, nullptr, OperandInfo241, -1 ,nullptr }, // Inst #1611 = FSUB_S_MM |
| { 1612, 3, 1, 4, 1324, 0, 0x6ULL, nullptr, nullptr, OperandInfo241, -1 ,nullptr }, // Inst #1612 = FSUB_S_MMR6 |
| { 1613, 3, 1, 4, 656, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1613 = FSUB_W |
| { 1614, 3, 1, 4, 567, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1614 = FSUEQ_D |
| { 1615, 3, 1, 4, 567, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1615 = FSUEQ_W |
| { 1616, 3, 1, 4, 568, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1616 = FSULE_D |
| { 1617, 3, 1, 4, 568, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1617 = FSULE_W |
| { 1618, 3, 1, 4, 569, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1618 = FSULT_D |
| { 1619, 3, 1, 4, 569, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1619 = FSULT_W |
| { 1620, 3, 1, 4, 570, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1620 = FSUNE_D |
| { 1621, 3, 1, 4, 570, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1621 = FSUNE_W |
| { 1622, 3, 1, 4, 571, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1622 = FSUN_D |
| { 1623, 3, 1, 4, 571, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1623 = FSUN_W |
| { 1624, 2, 1, 4, 587, 0, 0x6ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #1624 = FTINT_S_D |
| { 1625, 2, 1, 4, 587, 0, 0x6ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr }, // Inst #1625 = FTINT_S_W |
| { 1626, 2, 1, 4, 587, 0, 0x6ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #1626 = FTINT_U_D |
| { 1627, 2, 1, 4, 587, 0, 0x6ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr }, // Inst #1627 = FTINT_U_W |
| { 1628, 3, 1, 4, 589, 0, 0x6ULL, nullptr, nullptr, OperandInfo245, -1 ,nullptr }, // Inst #1628 = FTQ_H |
| { 1629, 3, 1, 4, 589, 0, 0x6ULL, nullptr, nullptr, OperandInfo246, -1 ,nullptr }, // Inst #1629 = FTQ_W |
| { 1630, 2, 1, 4, 590, 0, 0x6ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #1630 = FTRUNC_S_D |
| { 1631, 2, 1, 4, 590, 0, 0x6ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr }, // Inst #1631 = FTRUNC_S_W |
| { 1632, 2, 1, 4, 590, 0, 0x6ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #1632 = FTRUNC_U_D |
| { 1633, 2, 1, 4, 590, 0, 0x6ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr }, // Inst #1633 = FTRUNC_U_W |
| { 1634, 1, 0, 4, 1081, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #1634 = GINVI |
| { 1635, 1, 0, 4, 1135, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #1635 = GINVI_MMR6 |
| { 1636, 2, 0, 4, 1082, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #1636 = GINVT |
| { 1637, 2, 0, 4, 1136, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #1637 = GINVT_MMR6 |
| { 1638, 3, 1, 4, 610, 0, 0x6ULL, nullptr, nullptr, OperandInfo227, -1 ,nullptr }, // Inst #1638 = HADD_S_D |
| { 1639, 3, 1, 4, 610, 0, 0x6ULL, nullptr, nullptr, OperandInfo228, -1 ,nullptr }, // Inst #1639 = HADD_S_H |
| { 1640, 3, 1, 4, 610, 0, 0x6ULL, nullptr, nullptr, OperandInfo229, -1 ,nullptr }, // Inst #1640 = HADD_S_W |
| { 1641, 3, 1, 4, 610, 0, 0x6ULL, nullptr, nullptr, OperandInfo227, -1 ,nullptr }, // Inst #1641 = HADD_U_D |
| { 1642, 3, 1, 4, 610, 0, 0x6ULL, nullptr, nullptr, OperandInfo228, -1 ,nullptr }, // Inst #1642 = HADD_U_H |
| { 1643, 3, 1, 4, 610, 0, 0x6ULL, nullptr, nullptr, OperandInfo229, -1 ,nullptr }, // Inst #1643 = HADD_U_W |
| { 1644, 3, 1, 4, 611, 0, 0x6ULL, nullptr, nullptr, OperandInfo227, -1 ,nullptr }, // Inst #1644 = HSUB_S_D |
| { 1645, 3, 1, 4, 611, 0, 0x6ULL, nullptr, nullptr, OperandInfo228, -1 ,nullptr }, // Inst #1645 = HSUB_S_H |
| { 1646, 3, 1, 4, 611, 0, 0x6ULL, nullptr, nullptr, OperandInfo229, -1 ,nullptr }, // Inst #1646 = HSUB_S_W |
| { 1647, 3, 1, 4, 611, 0, 0x6ULL, nullptr, nullptr, OperandInfo227, -1 ,nullptr }, // Inst #1647 = HSUB_U_D |
| { 1648, 3, 1, 4, 611, 0, 0x6ULL, nullptr, nullptr, OperandInfo228, -1 ,nullptr }, // Inst #1648 = HSUB_U_H |
| { 1649, 3, 1, 4, 611, 0, 0x6ULL, nullptr, nullptr, OperandInfo229, -1 ,nullptr }, // Inst #1649 = HSUB_U_W |
| { 1650, 1, 0, 4, 415, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #1650 = HYPCALL |
| { 1651, 1, 0, 4, 1061, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #1651 = HYPCALL_MM |
| { 1652, 3, 1, 4, 601, 0, 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #1652 = ILVEV_B |
| { 1653, 3, 1, 4, 601, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1653 = ILVEV_D |
| { 1654, 3, 1, 4, 601, 0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #1654 = ILVEV_H |
| { 1655, 3, 1, 4, 601, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1655 = ILVEV_W |
| { 1656, 3, 1, 4, 600, 0, 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #1656 = ILVL_B |
| { 1657, 3, 1, 4, 600, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1657 = ILVL_D |
| { 1658, 3, 1, 4, 600, 0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #1658 = ILVL_H |
| { 1659, 3, 1, 4, 600, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1659 = ILVL_W |
| { 1660, 3, 1, 4, 601, 0, 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #1660 = ILVOD_B |
| { 1661, 3, 1, 4, 601, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1661 = ILVOD_D |
| { 1662, 3, 1, 4, 601, 0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #1662 = ILVOD_H |
| { 1663, 3, 1, 4, 601, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1663 = ILVOD_W |
| { 1664, 3, 1, 4, 600, 0, 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #1664 = ILVR_B |
| { 1665, 3, 1, 4, 600, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1665 = ILVR_D |
| { 1666, 3, 1, 4, 600, 0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #1666 = ILVR_H |
| { 1667, 3, 1, 4, 600, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1667 = ILVR_W |
| { 1668, 5, 1, 4, 490, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo253, -1 ,nullptr }, // Inst #1668 = INS |
| { 1669, 4, 1, 4, 513, 0, 0x6ULL, nullptr, nullptr, OperandInfo254, -1 ,nullptr }, // Inst #1669 = INSERT_B |
| { 1670, 4, 1, 4, 513, 0, 0x6ULL, nullptr, nullptr, OperandInfo255, -1 ,nullptr }, // Inst #1670 = INSERT_D |
| { 1671, 4, 1, 4, 513, 0, 0x6ULL, nullptr, nullptr, OperandInfo256, -1 ,nullptr }, // Inst #1671 = INSERT_H |
| { 1672, 4, 1, 4, 513, 0, 0x6ULL, nullptr, nullptr, OperandInfo257, -1 ,nullptr }, // Inst #1672 = INSERT_W |
| { 1673, 3, 1, 4, 1342, 0|(1ULL<<MCID::MayLoad), 0x6ULL, ImplicitList18, nullptr, OperandInfo258, -1 ,nullptr }, // Inst #1673 = INSV |
| { 1674, 5, 1, 4, 602, 0, 0x6ULL, nullptr, nullptr, OperandInfo259, -1 ,nullptr }, // Inst #1674 = INSVE_B |
| { 1675, 5, 1, 4, 602, 0, 0x6ULL, nullptr, nullptr, OperandInfo260, -1 ,nullptr }, // Inst #1675 = INSVE_D |
| { 1676, 5, 1, 4, 602, 0, 0x6ULL, nullptr, nullptr, OperandInfo261, -1 ,nullptr }, // Inst #1676 = INSVE_H |
| { 1677, 5, 1, 4, 602, 0, 0x6ULL, nullptr, nullptr, OperandInfo262, -1 ,nullptr }, // Inst #1677 = INSVE_W |
| { 1678, 3, 1, 4, 1537, 0|(1ULL<<MCID::MayLoad), 0x6ULL, ImplicitList18, nullptr, OperandInfo258, -1 ,nullptr }, // Inst #1678 = INSV_MM |
| { 1679, 5, 1, 4, 739, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo253, -1 ,nullptr }, // Inst #1679 = INS_MM |
| { 1680, 5, 1, 4, 780, 0, 0x1ULL, nullptr, nullptr, OperandInfo253, -1 ,nullptr }, // Inst #1680 = INS_MMR6 |
| { 1681, 1, 0, 4, 914, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x13ULL, nullptr, ImplicitList2, OperandInfo2, -1 ,nullptr }, // Inst #1681 = J |
| { 1682, 1, 0, 4, 401, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call), 0x13ULL, nullptr, ImplicitList3, OperandInfo2, -1 ,nullptr }, // Inst #1682 = JAL |
| { 1683, 2, 1, 4, 402, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x11ULL, nullptr, ImplicitList3, OperandInfo38, -1 ,nullptr }, // Inst #1683 = JALR |
| { 1684, 1, 0, 2, 951, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList3, OperandInfo51, -1 ,nullptr }, // Inst #1684 = JALR16_MM |
| { 1685, 2, 1, 4, 1004, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x11ULL, nullptr, ImplicitList3, OperandInfo113, -1 ,nullptr }, // Inst #1685 = JALR64 |
| { 1686, 1, 0, 2, 993, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook), 0x0ULL, nullptr, ImplicitList3, OperandInfo51, -1 ,nullptr }, // Inst #1686 = JALRC16_MMR6 |
| { 1687, 2, 1, 4, 994, 0|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::UnmodeledSideEffects), 0x3ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #1687 = JALRC_HB_MMR6 |
| { 1688, 2, 1, 4, 995, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList3, OperandInfo38, -1 ,nullptr }, // Inst #1688 = JALRC_MMR6 |
| { 1689, 1, 0, 2, 952, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList3, OperandInfo51, -1 ,nullptr }, // Inst #1689 = JALRS16_MM |
| { 1690, 2, 1, 4, 952, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, ImplicitList3, OperandInfo38, -1 ,nullptr }, // Inst #1690 = JALRS_MM |
| { 1691, 2, 1, 4, 403, 0|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x13ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #1691 = JALR_HB |
| { 1692, 2, 1, 4, 1005, 0|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x13ULL, nullptr, nullptr, OperandInfo113, -1 ,nullptr }, // Inst #1692 = JALR_HB64 |
| { 1693, 2, 1, 4, 951, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x11ULL, nullptr, ImplicitList3, OperandInfo38, -1 ,nullptr }, // Inst #1693 = JALR_MM |
| { 1694, 1, 0, 4, 953, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x3ULL, nullptr, ImplicitList3, OperandInfo2, -1 ,nullptr }, // Inst #1694 = JALS_MM |
| { 1695, 1, 0, 4, 404, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call), 0x13ULL, nullptr, ImplicitList3, OperandInfo2, -1 ,nullptr }, // Inst #1695 = JALX |
| { 1696, 1, 0, 4, 954, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call), 0x13ULL, nullptr, ImplicitList3, OperandInfo2, -1 ,nullptr }, // Inst #1696 = JALX_MM |
| { 1697, 1, 0, 4, 954, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call), 0x13ULL, nullptr, ImplicitList3, OperandInfo2, -1 ,nullptr }, // Inst #1697 = JAL_MM |
| { 1698, 2, 0, 4, 920, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList3, OperandInfo105, -1 ,nullptr }, // Inst #1698 = JIALC |
| { 1699, 2, 0, 4, 1013, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList3, OperandInfo103, -1 ,nullptr }, // Inst #1699 = JIALC64 |
| { 1700, 2, 0, 4, 996, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList3, OperandInfo105, -1 ,nullptr }, // Inst #1700 = JIALC_MMR6 |
| { 1701, 2, 0, 4, 925, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList2, OperandInfo105, -1 ,nullptr }, // Inst #1701 = JIC |
| { 1702, 2, 0, 4, 1011, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList2, OperandInfo103, -1 ,nullptr }, // Inst #1702 = JIC64 |
| { 1703, 2, 0, 4, 984, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList2, OperandInfo105, -1 ,nullptr }, // Inst #1703 = JIC_MMR6 |
| { 1704, 1, 0, 4, 915, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x11ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #1704 = JR |
| { 1705, 1, 0, 2, 946, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #1705 = JR16_MM |
| { 1706, 1, 0, 4, 1003, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x11ULL, nullptr, nullptr, OperandInfo88, -1 ,nullptr }, // Inst #1706 = JR64 |
| { 1707, 1, 0, 2, 985, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #1707 = JRADDIUSP |
| { 1708, 1, 0, 2, 986, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #1708 = JRC16_MM |
| { 1709, 1, 0, 2, 987, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #1709 = JRC16_MMR6 |
| { 1710, 1, 0, 2, 985, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #1710 = JRCADDIUSP_MMR6 |
| { 1711, 1, 0, 4, 381, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x13ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #1711 = JR_HB |
| { 1712, 1, 0, 4, 1006, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x13ULL, nullptr, nullptr, OperandInfo88, -1 ,nullptr }, // Inst #1712 = JR_HB64 |
| { 1713, 1, 0, 4, 1014, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo88, -1 ,nullptr }, // Inst #1713 = JR_HB64_R6 |
| { 1714, 1, 0, 4, 926, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #1714 = JR_HB_R6 |
| { 1715, 1, 0, 4, 946, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x11ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #1715 = JR_MM |
| { 1716, 1, 0, 4, 947, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x13ULL, nullptr, ImplicitList2, OperandInfo2, -1 ,nullptr }, // Inst #1716 = J_MM |
| { 1717, 1, 0, 6, 933, 0|(1ULL<<MCID::Call), 0x0ULL, nullptr, ImplicitList3, OperandInfo2, -1 ,nullptr }, // Inst #1717 = Jal16 |
| { 1718, 1, 0, 6, 933, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList3, OperandInfo2, -1 ,nullptr }, // Inst #1718 = JalB16 |
| { 1719, 0, 0, 2, 931, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1719 = JrRa16 |
| { 1720, 0, 0, 2, 931, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #1720 = JrcRa16 |
| { 1721, 1, 0, 2, 931, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo263, -1 ,nullptr }, // Inst #1721 = JrcRx16 |
| { 1722, 1, 0, 2, 934, 0|(1ULL<<MCID::Call), 0x0ULL, nullptr, ImplicitList3, OperandInfo263, -1 ,nullptr }, // Inst #1722 = JumpLinkReg16 |
| { 1723, 3, 1, 4, 426, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #1723 = LB |
| { 1724, 3, 1, 4, 1158, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo104, -1 ,nullptr }, // Inst #1724 = LB64 |
| { 1725, 3, 1, 4, 436, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #1725 = LBE |
| { 1726, 3, 1, 4, 1083, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #1726 = LBE_MM |
| { 1727, 3, 1, 2, 1110, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo264, -1 ,nullptr }, // Inst #1727 = LBU16_MM |
| { 1728, 3, 1, 4, 1378, 0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, nullptr, OperandInfo265, -1 ,nullptr }, // Inst #1728 = LBUX |
| { 1729, 3, 1, 4, 1538, 0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, nullptr, OperandInfo265, -1 ,nullptr }, // Inst #1729 = LBUX_MM |
| { 1730, 3, 1, 4, 1137, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #1730 = LBU_MMR6 |
| { 1731, 3, 1, 4, 1111, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #1731 = LB_MM |
| { 1732, 3, 1, 4, 1138, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #1732 = LB_MMR6 |
| { 1733, 3, 1, 4, 427, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #1733 = LBu |
| { 1734, 3, 1, 4, 1159, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo104, -1 ,nullptr }, // Inst #1734 = LBu64 |
| { 1735, 3, 1, 4, 437, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #1735 = LBuE |
| { 1736, 3, 1, 4, 1084, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #1736 = LBuE_MM |
| { 1737, 3, 1, 4, 1110, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #1737 = LBu_MM |
| { 1738, 3, 1, 4, 1155, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo104, -1 ,nullptr }, // Inst #1738 = LD |
| { 1739, 3, 1, 4, 702, 0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr }, // Inst #1739 = LDC1 |
| { 1740, 3, 1, 4, 702, 0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, nullptr, OperandInfo266, -1 ,nullptr }, // Inst #1740 = LDC164 |
| { 1741, 3, 1, 4, 1328, 0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, nullptr, OperandInfo266, -1 ,nullptr }, // Inst #1741 = LDC1_D64_MMR6 |
| { 1742, 3, 1, 4, 1285, 0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr }, // Inst #1742 = LDC1_MM |
| { 1743, 3, 1, 4, 434, 0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, nullptr, OperandInfo267, -1 ,nullptr }, // Inst #1743 = LDC2 |
| { 1744, 3, 1, 4, 1139, 0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, nullptr, OperandInfo268, -1 ,nullptr }, // Inst #1744 = LDC2_MMR6 |
| { 1745, 3, 1, 4, 1073, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo267, -1 ,nullptr }, // Inst #1745 = LDC2_R6 |
| { 1746, 3, 1, 4, 435, 0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, nullptr, OperandInfo269, -1 ,nullptr }, // Inst #1746 = LDC3 |
| { 1747, 2, 1, 4, 542, 0|(1ULL<<MCID::Rematerializable), 0x6ULL, nullptr, nullptr, OperandInfo270, -1 ,nullptr }, // Inst #1747 = LDI_B |
| { 1748, 2, 1, 4, 542, 0|(1ULL<<MCID::Rematerializable), 0x6ULL, nullptr, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #1748 = LDI_D |
| { 1749, 2, 1, 4, 542, 0|(1ULL<<MCID::Rematerializable), 0x6ULL, nullptr, nullptr, OperandInfo272, -1 ,nullptr }, // Inst #1749 = LDI_H |
| { 1750, 2, 1, 4, 542, 0|(1ULL<<MCID::Rematerializable), 0x6ULL, nullptr, nullptr, OperandInfo273, -1 ,nullptr }, // Inst #1750 = LDI_W |
| { 1751, 4, 1, 4, 1165, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo274, -1 ,nullptr }, // Inst #1751 = LDL |
| { 1752, 2, 1, 4, 1177, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo103, -1 ,nullptr }, // Inst #1752 = LDPC |
| { 1753, 4, 1, 4, 1166, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo274, -1 ,nullptr }, // Inst #1753 = LDR |
| { 1754, 3, 1, 4, 703, 0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, nullptr, OperandInfo275, -1 ,nullptr }, // Inst #1754 = LDXC1 |
| { 1755, 3, 1, 4, 703, 0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #1755 = LDXC164 |
| { 1756, 3, 1, 4, 707, 0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #1756 = LD_B |
| { 1757, 3, 1, 4, 707, 0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #1757 = LD_D |
| { 1758, 3, 1, 4, 707, 0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, nullptr, OperandInfo279, -1 ,nullptr }, // Inst #1758 = LD_H |
| { 1759, 3, 1, 4, 707, 0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #1759 = LD_W |
| { 1760, 3, 1, 4, 716, 0, 0x2ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #1760 = LEA_ADDiu |
| { 1761, 3, 1, 4, 832, 0, 0x2ULL, nullptr, nullptr, OperandInfo104, -1 ,nullptr }, // Inst #1761 = LEA_ADDiu64 |
| { 1762, 3, 1, 4, 730, 0, 0x2ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #1762 = LEA_ADDiu_MM |
| { 1763, 3, 1, 4, 428, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #1763 = LH |
| { 1764, 3, 1, 4, 1160, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo104, -1 ,nullptr }, // Inst #1764 = LH64 |
| { 1765, 3, 1, 4, 438, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #1765 = LHE |
| { 1766, 3, 1, 4, 1085, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #1766 = LHE_MM |
| { 1767, 3, 1, 2, 1112, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo264, -1 ,nullptr }, // Inst #1767 = LHU16_MM |
| { 1768, 3, 1, 4, 1379, 0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, nullptr, OperandInfo265, -1 ,nullptr }, // Inst #1768 = LHX |
| { 1769, 3, 1, 4, 1539, 0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, nullptr, OperandInfo265, -1 ,nullptr }, // Inst #1769 = LHX_MM |
| { 1770, 3, 1, 4, 1113, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #1770 = LH_MM |
| { 1771, 3, 1, 4, 429, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #1771 = LHu |
| { 1772, 3, 1, 4, 1161, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo104, -1 ,nullptr }, // Inst #1772 = LHu64 |
| { 1773, 3, 1, 4, 439, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #1773 = LHuE |
| { 1774, 3, 1, 4, 1086, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #1774 = LHuE_MM |
| { 1775, 3, 1, 4, 1112, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #1775 = LHu_MM |
| { 1776, 2, 1, 2, 740, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo160, -1 ,nullptr }, // Inst #1776 = LI16_MM |
| { 1777, 2, 1, 2, 781, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo160, -1 ,nullptr }, // Inst #1777 = LI16_MMR6 |
| { 1778, 3, 1, 4, 431, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #1778 = LL |
| { 1779, 3, 1, 4, 1156, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #1779 = LL64 |
| { 1780, 3, 1, 4, 1179, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo281, -1 ,nullptr }, // Inst #1780 = LL64_R6 |
| { 1781, 3, 1, 4, 1156, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo104, -1 ,nullptr }, // Inst #1781 = LLD |
| { 1782, 3, 1, 4, 1178, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #1782 = LLD_R6 |
| { 1783, 3, 1, 4, 441, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #1783 = LLE |
| { 1784, 3, 1, 4, 1090, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #1784 = LLE_MM |
| { 1785, 3, 1, 4, 1114, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #1785 = LL_MM |
| { 1786, 3, 1, 4, 1140, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #1786 = LL_MMR6 |
| { 1787, 3, 1, 4, 1074, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo281, -1 ,nullptr }, // Inst #1787 = LL_R6 |
| { 1788, 4, 1, 4, 508, 0, 0x6ULL, nullptr, nullptr, OperandInfo170, -1 ,nullptr }, // Inst #1788 = LSA |
| { 1789, 4, 1, 4, 782, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo170, -1 ,nullptr }, // Inst #1789 = LSA_MMR6 |
| { 1790, 4, 1, 4, 725, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo170, -1 ,nullptr }, // Inst #1790 = LSA_R6 |
| { 1791, 2, 1, 4, 783, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #1791 = LUI_MMR6 |
| { 1792, 3, 1, 4, 706, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, nullptr, nullptr, OperandInfo275, -1 ,nullptr }, // Inst #1792 = LUXC1 |
| { 1793, 3, 1, 4, 706, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, nullptr, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #1793 = LUXC164 |
| { 1794, 3, 1, 4, 1286, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, nullptr, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #1794 = LUXC1_MM |
| { 1795, 2, 1, 4, 360, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #1795 = LUi |
| { 1796, 2, 1, 4, 833, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2ULL, nullptr, nullptr, OperandInfo103, -1 ,nullptr }, // Inst #1796 = LUi64 |
| { 1797, 2, 1, 4, 741, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #1797 = LUi_MM |
| { 1798, 3, 1, 4, 430, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #1798 = LW |
| { 1799, 3, 1, 2, 1115, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo264, -1 ,nullptr }, // Inst #1799 = LW16_MM |
| { 1800, 3, 1, 4, 1162, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo104, -1 ,nullptr }, // Inst #1800 = LW64 |
| { 1801, 3, 1, 4, 704, 0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #1801 = LWC1 |
| { 1802, 3, 1, 4, 1287, 0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #1802 = LWC1_MM |
| { 1803, 3, 1, 4, 432, 0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, nullptr, OperandInfo267, -1 ,nullptr }, // Inst #1803 = LWC2 |
| { 1804, 3, 1, 4, 1142, 0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, nullptr, OperandInfo268, -1 ,nullptr }, // Inst #1804 = LWC2_MMR6 |
| { 1805, 3, 1, 4, 1075, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo267, -1 ,nullptr }, // Inst #1805 = LWC2_R6 |
| { 1806, 3, 1, 4, 433, 0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, nullptr, OperandInfo269, -1 ,nullptr }, // Inst #1806 = LWC3 |
| { 1807, 3, 1, 4, 1332, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #1807 = LWDSP |
| { 1808, 3, 1, 4, 1495, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #1808 = LWDSP_MM |
| { 1809, 3, 1, 4, 440, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #1809 = LWE |
| { 1810, 3, 1, 4, 1087, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #1810 = LWE_MM |
| { 1811, 3, 1, 2, 1115, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo285, -1 ,nullptr }, // Inst #1811 = LWGP_MM |
| { 1812, 4, 1, 4, 443, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo286, -1 ,nullptr }, // Inst #1812 = LWL |
| { 1813, 4, 1, 4, 1163, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo274, -1 ,nullptr }, // Inst #1813 = LWL64 |
| { 1814, 4, 1, 4, 445, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo286, -1 ,nullptr }, // Inst #1814 = LWLE |
| { 1815, 4, 1, 4, 1088, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo286, -1 ,nullptr }, // Inst #1815 = LWLE_MM |
| { 1816, 4, 1, 4, 1116, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo286, -1 ,nullptr }, // Inst #1816 = LWL_MM |
| { 1817, 3, 1, 2, 1117, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #1817 = LWM16_MM |
| { 1818, 3, 1, 2, 1141, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #1818 = LWM16_MMR6 |
| { 1819, 3, 1, 4, 1117, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr }, // Inst #1819 = LWM32_MM |
| { 1820, 2, 1, 4, 442, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #1820 = LWPC |
| { 1821, 2, 1, 4, 1143, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #1821 = LWPC_MMR6 |
| { 1822, 4, 2, 4, 1118, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo288, -1 ,nullptr }, // Inst #1822 = LWP_MM |
| { 1823, 4, 1, 4, 444, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo286, -1 ,nullptr }, // Inst #1823 = LWR |
| { 1824, 4, 1, 4, 1164, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo274, -1 ,nullptr }, // Inst #1824 = LWR64 |
| { 1825, 4, 1, 4, 446, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo286, -1 ,nullptr }, // Inst #1825 = LWRE |
| { 1826, 4, 1, 4, 1089, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo286, -1 ,nullptr }, // Inst #1826 = LWRE_MM |
| { 1827, 4, 1, 4, 1119, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo286, -1 ,nullptr }, // Inst #1827 = LWR_MM |
| { 1828, 3, 1, 2, 1115, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo289, -1 ,nullptr }, // Inst #1828 = LWSP_MM |
| { 1829, 2, 1, 4, 1176, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #1829 = LWUPC |
| { 1830, 3, 1, 4, 1120, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #1830 = LWU_MM |
| { 1831, 3, 1, 4, 1380, 0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, nullptr, OperandInfo265, -1 ,nullptr }, // Inst #1831 = LWX |
| { 1832, 3, 1, 4, 705, 0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, nullptr, OperandInfo290, -1 ,nullptr }, // Inst #1832 = LWXC1 |
| { 1833, 3, 1, 4, 1288, 0|(1ULL<<MCID::MayLoad), 0x5ULL, nullptr, nullptr, OperandInfo290, -1 ,nullptr }, // Inst #1833 = LWXC1_MM |
| { 1834, 3, 1, 4, 1121, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, nullptr, nullptr, OperandInfo265, -1 ,nullptr }, // Inst #1834 = LWXS_MM |
| { 1835, 3, 1, 4, 1540, 0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, nullptr, OperandInfo265, -1 ,nullptr }, // Inst #1835 = LWX_MM |
| { 1836, 3, 1, 4, 1115, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #1836 = LW_MM |
| { 1837, 3, 1, 4, 1144, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #1837 = LW_MMR6 |
| { 1838, 3, 1, 4, 1157, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo104, -1 ,nullptr }, // Inst #1838 = LWu |
| { 1839, 3, 1, 4, 1101, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #1839 = LbRxRyOffMemX16 |
| { 1840, 3, 1, 4, 1102, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #1840 = LbuRxRyOffMemX16 |
| { 1841, 3, 1, 4, 1103, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #1841 = LhRxRyOffMemX16 |
| { 1842, 3, 1, 4, 1104, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #1842 = LhuRxRyOffMemX16 |
| { 1843, 2, 1, 2, 727, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo173, -1 ,nullptr }, // Inst #1843 = LiRxImm16 |
| { 1844, 2, 1, 4, 727, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo173, -1 ,nullptr }, // Inst #1844 = LiRxImmAlignX16 |
| { 1845, 2, 1, 4, 727, 0, 0x0ULL, nullptr, nullptr, OperandInfo173, -1 ,nullptr }, // Inst #1845 = LiRxImmX16 |
| { 1846, 3, 1, 2, 1105, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo292, -1 ,nullptr }, // Inst #1846 = LwRxPcTcp16 |
| { 1847, 3, 1, 4, 1105, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo292, -1 ,nullptr }, // Inst #1847 = LwRxPcTcpX16 |
| { 1848, 3, 1, 4, 1105, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #1848 = LwRxRyOffMemX16 |
| { 1849, 3, 1, 4, 1105, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo175, -1 ,nullptr }, // Inst #1849 = LwRxSpImmX16 |
| { 1850, 2, 0, 4, 845, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList6, ImplicitList6, OperandInfo38, -1 ,nullptr }, // Inst #1850 = MADD |
| { 1851, 4, 1, 4, 1225, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo293, -1 ,nullptr }, // Inst #1851 = MADDF_D |
| { 1852, 4, 1, 4, 1318, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo293, -1 ,nullptr }, // Inst #1852 = MADDF_D_MMR6 |
| { 1853, 4, 1, 4, 1223, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo294, -1 ,nullptr }, // Inst #1853 = MADDF_S |
| { 1854, 4, 1, 4, 1319, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo294, -1 ,nullptr }, // Inst #1854 = MADDF_S_MMR6 |
| { 1855, 4, 1, 4, 663, 0, 0x6ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #1855 = MADDR_Q_H |
| { 1856, 4, 1, 4, 663, 0, 0x6ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #1856 = MADDR_Q_W |
| { 1857, 2, 0, 4, 846, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList6, ImplicitList6, OperandInfo38, -1 ,nullptr }, // Inst #1857 = MADDU |
| { 1858, 4, 1, 4, 1381, 0, 0x6ULL, nullptr, nullptr, OperandInfo233, -1 ,nullptr }, // Inst #1858 = MADDU_DSP |
| { 1859, 4, 1, 4, 1541, 0, 0x6ULL, nullptr, nullptr, OperandInfo233, -1 ,nullptr }, // Inst #1859 = MADDU_DSP_MM |
| { 1860, 2, 0, 4, 873, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList6, ImplicitList6, OperandInfo38, -1 ,nullptr }, // Inst #1860 = MADDU_MM |
| { 1861, 4, 1, 4, 661, 0, 0x6ULL, nullptr, nullptr, OperandInfo186, -1 ,nullptr }, // Inst #1861 = MADDV_B |
| { 1862, 4, 1, 4, 661, 0, 0x6ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #1862 = MADDV_D |
| { 1863, 4, 1, 4, 661, 0, 0x6ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #1863 = MADDV_H |
| { 1864, 4, 1, 4, 661, 0, 0x6ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #1864 = MADDV_W |
| { 1865, 4, 1, 4, 669, 0, 0x4ULL, nullptr, nullptr, OperandInfo295, -1 ,nullptr }, // Inst #1865 = MADD_D32 |
| { 1866, 4, 1, 4, 1243, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo295, -1 ,nullptr }, // Inst #1866 = MADD_D32_MM |
| { 1867, 4, 1, 4, 669, 0, 0x4ULL, nullptr, nullptr, OperandInfo296, -1 ,nullptr }, // Inst #1867 = MADD_D64 |
| { 1868, 4, 1, 4, 1382, 0, 0x6ULL, nullptr, nullptr, OperandInfo233, -1 ,nullptr }, // Inst #1868 = MADD_DSP |
| { 1869, 4, 1, 4, 1542, 0, 0x6ULL, nullptr, nullptr, OperandInfo233, -1 ,nullptr }, // Inst #1869 = MADD_DSP_MM |
| { 1870, 2, 0, 4, 872, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList6, ImplicitList6, OperandInfo38, -1 ,nullptr }, // Inst #1870 = MADD_MM |
| { 1871, 4, 1, 4, 664, 0, 0x6ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #1871 = MADD_Q_H |
| { 1872, 4, 1, 4, 664, 0, 0x6ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #1872 = MADD_Q_W |
| { 1873, 4, 1, 4, 670, 0, 0x4ULL, nullptr, nullptr, OperandInfo297, -1 ,nullptr }, // Inst #1873 = MADD_S |
| { 1874, 4, 1, 4, 1242, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo297, -1 ,nullptr }, // Inst #1874 = MADD_S_MM |
| { 1875, 4, 1, 4, 1383, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo233, -1 ,nullptr }, // Inst #1875 = MAQ_SA_W_PHL |
| { 1876, 4, 1, 4, 1543, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo233, -1 ,nullptr }, // Inst #1876 = MAQ_SA_W_PHL_MM |
| { 1877, 4, 1, 4, 1384, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo233, -1 ,nullptr }, // Inst #1877 = MAQ_SA_W_PHR |
| { 1878, 4, 1, 4, 1544, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo233, -1 ,nullptr }, // Inst #1878 = MAQ_SA_W_PHR_MM |
| { 1879, 4, 1, 4, 1385, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo233, -1 ,nullptr }, // Inst #1879 = MAQ_S_W_PHL |
| { 1880, 4, 1, 4, 1545, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo233, -1 ,nullptr }, // Inst #1880 = MAQ_S_W_PHL_MM |
| { 1881, 4, 1, 4, 1386, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo233, -1 ,nullptr }, // Inst #1881 = MAQ_S_W_PHR |
| { 1882, 4, 1, 4, 1546, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo233, -1 ,nullptr }, // Inst #1882 = MAQ_S_W_PHR_MM |
| { 1883, 3, 1, 4, 1213, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo240, -1 ,nullptr }, // Inst #1883 = MAXA_D |
| { 1884, 3, 1, 4, 1309, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo240, -1 ,nullptr }, // Inst #1884 = MAXA_D_MMR6 |
| { 1885, 3, 1, 4, 1212, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo241, -1 ,nullptr }, // Inst #1885 = MAXA_S |
| { 1886, 3, 1, 4, 1310, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo241, -1 ,nullptr }, // Inst #1886 = MAXA_S_MMR6 |
| { 1887, 3, 1, 4, 615, 0, 0x6ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr }, // Inst #1887 = MAXI_S_B |
| { 1888, 3, 1, 4, 615, 0, 0x6ULL, nullptr, nullptr, OperandInfo167, -1 ,nullptr }, // Inst #1888 = MAXI_S_D |
| { 1889, 3, 1, 4, 615, 0, 0x6ULL, nullptr, nullptr, OperandInfo168, -1 ,nullptr }, // Inst #1889 = MAXI_S_H |
| { 1890, 3, 1, 4, 615, 0, 0x6ULL, nullptr, nullptr, OperandInfo169, -1 ,nullptr }, // Inst #1890 = MAXI_S_W |
| { 1891, 3, 1, 4, 615, 0, 0x6ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr }, // Inst #1891 = MAXI_U_B |
| { 1892, 3, 1, 4, 615, 0, 0x6ULL, nullptr, nullptr, OperandInfo167, -1 ,nullptr }, // Inst #1892 = MAXI_U_D |
| { 1893, 3, 1, 4, 615, 0, 0x6ULL, nullptr, nullptr, OperandInfo168, -1 ,nullptr }, // Inst #1893 = MAXI_U_H |
| { 1894, 3, 1, 4, 615, 0, 0x6ULL, nullptr, nullptr, OperandInfo169, -1 ,nullptr }, // Inst #1894 = MAXI_U_W |
| { 1895, 3, 1, 4, 614, 0, 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #1895 = MAX_A_B |
| { 1896, 3, 1, 4, 614, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1896 = MAX_A_D |
| { 1897, 3, 1, 4, 614, 0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #1897 = MAX_A_H |
| { 1898, 3, 1, 4, 614, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1898 = MAX_A_W |
| { 1899, 3, 1, 4, 1213, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo240, -1 ,nullptr }, // Inst #1899 = MAX_D |
| { 1900, 3, 1, 4, 1305, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo240, -1 ,nullptr }, // Inst #1900 = MAX_D_MMR6 |
| { 1901, 3, 1, 4, 1212, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo241, -1 ,nullptr }, // Inst #1901 = MAX_S |
| { 1902, 3, 1, 4, 612, 0, 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #1902 = MAX_S_B |
| { 1903, 3, 1, 4, 612, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1903 = MAX_S_D |
| { 1904, 3, 1, 4, 612, 0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #1904 = MAX_S_H |
| { 1905, 3, 1, 4, 1306, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo241, -1 ,nullptr }, // Inst #1905 = MAX_S_MMR6 |
| { 1906, 3, 1, 4, 612, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1906 = MAX_S_W |
| { 1907, 3, 1, 4, 613, 0, 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #1907 = MAX_U_B |
| { 1908, 3, 1, 4, 613, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1908 = MAX_U_D |
| { 1909, 3, 1, 4, 613, 0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #1909 = MAX_U_H |
| { 1910, 3, 1, 4, 613, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1910 = MAX_U_W |
| { 1911, 3, 1, 4, 411, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo111, -1 ,nullptr }, // Inst #1911 = MFC0 |
| { 1912, 3, 1, 4, 1033, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo111, -1 ,nullptr }, // Inst #1912 = MFC0_MMR6 |
| { 1913, 2, 1, 4, 687, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast), 0x4ULL, nullptr, nullptr, OperandInfo112, -1 ,nullptr }, // Inst #1913 = MFC1 |
| { 1914, 2, 1, 4, 687, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo298, -1 ,nullptr }, // Inst #1914 = MFC1_D64 |
| { 1915, 2, 1, 4, 1256, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast), 0x4ULL, nullptr, nullptr, OperandInfo112, -1 ,nullptr }, // Inst #1915 = MFC1_MM |
| { 1916, 2, 1, 4, 1301, 0|(1ULL<<MCID::Bitcast), 0x6ULL, nullptr, nullptr, OperandInfo112, -1 ,nullptr }, // Inst #1916 = MFC1_MMR6 |
| { 1917, 3, 1, 4, 413, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo299, -1 ,nullptr }, // Inst #1917 = MFC2 |
| { 1918, 2, 1, 4, 1034, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo199, -1 ,nullptr }, // Inst #1918 = MFC2_MMR6 |
| { 1919, 3, 1, 4, 416, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo111, -1 ,nullptr }, // Inst #1919 = MFGC0 |
| { 1920, 3, 1, 4, 1068, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo111, -1 ,nullptr }, // Inst #1920 = MFGC0_MM |
| { 1921, 3, 1, 4, 1032, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo111, -1 ,nullptr }, // Inst #1921 = MFHC0_MMR6 |
| { 1922, 2, 1, 4, 688, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo300, -1 ,nullptr }, // Inst #1922 = MFHC1_D32 |
| { 1923, 2, 1, 4, 1257, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo300, -1 ,nullptr }, // Inst #1923 = MFHC1_D32_MM |
| { 1924, 2, 1, 4, 688, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo298, -1 ,nullptr }, // Inst #1924 = MFHC1_D64 |
| { 1925, 2, 1, 4, 1257, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo298, -1 ,nullptr }, // Inst #1925 = MFHC1_D64_MM |
| { 1926, 2, 1, 4, 1034, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo199, -1 ,nullptr }, // Inst #1926 = MFHC2_MMR6 |
| { 1927, 3, 1, 4, 417, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo111, -1 ,nullptr }, // Inst #1927 = MFHGC0 |
| { 1928, 3, 1, 4, 1069, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo111, -1 ,nullptr }, // Inst #1928 = MFHGC0_MM |
| { 1929, 1, 1, 4, 473, 0|(1ULL<<MCID::MoveReg), 0x1ULL, ImplicitList19, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #1929 = MFHI |
| { 1930, 1, 1, 2, 879, 0|(1ULL<<MCID::MoveReg), 0x0ULL, ImplicitList19, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #1930 = MFHI16_MM |
| { 1931, 1, 1, 4, 898, 0|(1ULL<<MCID::MoveReg), 0x1ULL, ImplicitList20, nullptr, OperandInfo88, -1 ,nullptr }, // Inst #1931 = MFHI64 |
| { 1932, 2, 1, 4, 1387, 0|(1ULL<<MCID::MoveReg), 0x6ULL, nullptr, nullptr, OperandInfo110, -1 ,nullptr }, // Inst #1932 = MFHI_DSP |
| { 1933, 2, 1, 4, 1547, 0, 0x6ULL, nullptr, nullptr, OperandInfo110, -1 ,nullptr }, // Inst #1933 = MFHI_DSP_MM |
| { 1934, 1, 1, 4, 879, 0|(1ULL<<MCID::MoveReg), 0x1ULL, ImplicitList19, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #1934 = MFHI_MM |
| { 1935, 1, 1, 4, 473, 0|(1ULL<<MCID::MoveReg), 0x1ULL, ImplicitList19, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #1935 = MFLO |
| { 1936, 1, 1, 2, 879, 0|(1ULL<<MCID::MoveReg), 0x0ULL, ImplicitList19, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #1936 = MFLO16_MM |
| { 1937, 1, 1, 4, 898, 0|(1ULL<<MCID::MoveReg), 0x1ULL, ImplicitList20, nullptr, OperandInfo88, -1 ,nullptr }, // Inst #1937 = MFLO64 |
| { 1938, 2, 1, 4, 1388, 0|(1ULL<<MCID::MoveReg), 0x6ULL, nullptr, nullptr, OperandInfo110, -1 ,nullptr }, // Inst #1938 = MFLO_DSP |
| { 1939, 2, 1, 4, 1548, 0, 0x6ULL, nullptr, nullptr, OperandInfo110, -1 ,nullptr }, // Inst #1939 = MFLO_DSP_MM |
| { 1940, 1, 1, 4, 879, 0|(1ULL<<MCID::MoveReg), 0x1ULL, ImplicitList19, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #1940 = MFLO_MM |
| { 1941, 5, 1, 4, 1055, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #1941 = MFTR |
| { 1942, 3, 1, 4, 1214, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo240, -1 ,nullptr }, // Inst #1942 = MINA_D |
| { 1943, 3, 1, 4, 1311, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo240, -1 ,nullptr }, // Inst #1943 = MINA_D_MMR6 |
| { 1944, 3, 1, 4, 1215, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo241, -1 ,nullptr }, // Inst #1944 = MINA_S |
| { 1945, 3, 1, 4, 1312, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo241, -1 ,nullptr }, // Inst #1945 = MINA_S_MMR6 |
| { 1946, 3, 1, 4, 615, 0, 0x6ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr }, // Inst #1946 = MINI_S_B |
| { 1947, 3, 1, 4, 615, 0, 0x6ULL, nullptr, nullptr, OperandInfo167, -1 ,nullptr }, // Inst #1947 = MINI_S_D |
| { 1948, 3, 1, 4, 615, 0, 0x6ULL, nullptr, nullptr, OperandInfo168, -1 ,nullptr }, // Inst #1948 = MINI_S_H |
| { 1949, 3, 1, 4, 615, 0, 0x6ULL, nullptr, nullptr, OperandInfo169, -1 ,nullptr }, // Inst #1949 = MINI_S_W |
| { 1950, 3, 1, 4, 615, 0, 0x6ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr }, // Inst #1950 = MINI_U_B |
| { 1951, 3, 1, 4, 615, 0, 0x6ULL, nullptr, nullptr, OperandInfo167, -1 ,nullptr }, // Inst #1951 = MINI_U_D |
| { 1952, 3, 1, 4, 615, 0, 0x6ULL, nullptr, nullptr, OperandInfo168, -1 ,nullptr }, // Inst #1952 = MINI_U_H |
| { 1953, 3, 1, 4, 615, 0, 0x6ULL, nullptr, nullptr, OperandInfo169, -1 ,nullptr }, // Inst #1953 = MINI_U_W |
| { 1954, 3, 1, 4, 614, 0, 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #1954 = MIN_A_B |
| { 1955, 3, 1, 4, 614, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1955 = MIN_A_D |
| { 1956, 3, 1, 4, 614, 0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #1956 = MIN_A_H |
| { 1957, 3, 1, 4, 614, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1957 = MIN_A_W |
| { 1958, 3, 1, 4, 1215, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo240, -1 ,nullptr }, // Inst #1958 = MIN_D |
| { 1959, 3, 1, 4, 1307, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo240, -1 ,nullptr }, // Inst #1959 = MIN_D_MMR6 |
| { 1960, 3, 1, 4, 1214, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo241, -1 ,nullptr }, // Inst #1960 = MIN_S |
| { 1961, 3, 1, 4, 612, 0, 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #1961 = MIN_S_B |
| { 1962, 3, 1, 4, 612, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1962 = MIN_S_D |
| { 1963, 3, 1, 4, 612, 0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #1963 = MIN_S_H |
| { 1964, 3, 1, 4, 1308, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo241, -1 ,nullptr }, // Inst #1964 = MIN_S_MMR6 |
| { 1965, 3, 1, 4, 612, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1965 = MIN_S_W |
| { 1966, 3, 1, 4, 613, 0, 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #1966 = MIN_U_B |
| { 1967, 3, 1, 4, 613, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1967 = MIN_U_D |
| { 1968, 3, 1, 4, 613, 0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #1968 = MIN_U_H |
| { 1969, 3, 1, 4, 613, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1969 = MIN_U_W |
| { 1970, 3, 1, 4, 865, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #1970 = MOD |
| { 1971, 3, 1, 4, 1389, 0, 0x6ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #1971 = MODSUB |
| { 1972, 3, 1, 4, 1549, 0, 0x6ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #1972 = MODSUB_MM |
| { 1973, 3, 1, 4, 866, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #1973 = MODU |
| { 1974, 3, 1, 4, 888, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UsesCustomInserter), 0x6ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #1974 = MODU_MMR6 |
| { 1975, 3, 1, 4, 889, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UsesCustomInserter), 0x6ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #1975 = MOD_MMR6 |
| { 1976, 3, 1, 4, 608, 0, 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #1976 = MOD_S_B |
| { 1977, 3, 1, 4, 608, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1977 = MOD_S_D |
| { 1978, 3, 1, 4, 608, 0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #1978 = MOD_S_H |
| { 1979, 3, 1, 4, 608, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1979 = MOD_S_W |
| { 1980, 3, 1, 4, 608, 0, 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #1980 = MOD_U_B |
| { 1981, 3, 1, 4, 608, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #1981 = MOD_U_D |
| { 1982, 3, 1, 4, 608, 0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #1982 = MOD_U_H |
| { 1983, 3, 1, 4, 608, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #1983 = MOD_U_W |
| { 1984, 2, 1, 2, 742, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #1984 = MOVE16_MM |
| { 1985, 2, 1, 2, 784, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #1985 = MOVE16_MMR6 |
| { 1986, 4, 2, 2, 743, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo302, -1 ,nullptr }, // Inst #1986 = MOVEP_MM |
| { 1987, 4, 2, 2, 1550, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo302, -1 ,nullptr }, // Inst #1987 = MOVEP_MMR6 |
| { 1988, 2, 1, 4, 541, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #1988 = MOVE_V |
| { 1989, 4, 1, 4, 526, 0, 0x4ULL, nullptr, nullptr, OperandInfo304, -1 ,nullptr }, // Inst #1989 = MOVF_D32 |
| { 1990, 4, 1, 4, 1227, 0, 0x4ULL, nullptr, nullptr, OperandInfo304, -1 ,nullptr }, // Inst #1990 = MOVF_D32_MM |
| { 1991, 4, 1, 4, 526, 0, 0x4ULL, nullptr, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #1991 = MOVF_D64 |
| { 1992, 4, 1, 4, 689, 0, 0x4ULL, nullptr, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #1992 = MOVF_I |
| { 1993, 4, 1, 4, 1205, 0, 0x4ULL, nullptr, nullptr, OperandInfo307, -1 ,nullptr }, // Inst #1993 = MOVF_I64 |
| { 1994, 4, 1, 4, 880, 0, 0x4ULL, nullptr, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #1994 = MOVF_I_MM |
| { 1995, 4, 1, 4, 527, 0, 0x4ULL, nullptr, nullptr, OperandInfo308, -1 ,nullptr }, // Inst #1995 = MOVF_S |
| { 1996, 4, 1, 4, 1228, 0, 0x4ULL, nullptr, nullptr, OperandInfo308, -1 ,nullptr }, // Inst #1996 = MOVF_S_MM |
| { 1997, 4, 1, 4, 1207, 0, 0x4ULL, nullptr, nullptr, OperandInfo309, -1 ,nullptr }, // Inst #1997 = MOVN_I64_D64 |
| { 1998, 4, 1, 4, 902, 0, 0x4ULL, nullptr, nullptr, OperandInfo310, -1 ,nullptr }, // Inst #1998 = MOVN_I64_I |
| { 1999, 4, 1, 4, 902, 0, 0x4ULL, nullptr, nullptr, OperandInfo311, -1 ,nullptr }, // Inst #1999 = MOVN_I64_I64 |
| { 2000, 4, 1, 4, 1208, 0, 0x4ULL, nullptr, nullptr, OperandInfo312, -1 ,nullptr }, // Inst #2000 = MOVN_I64_S |
| { 2001, 4, 1, 4, 698, 0, 0x4ULL, nullptr, nullptr, OperandInfo313, -1 ,nullptr }, // Inst #2001 = MOVN_I_D32 |
| { 2002, 4, 1, 4, 1229, 0, 0x4ULL, nullptr, nullptr, OperandInfo313, -1 ,nullptr }, // Inst #2002 = MOVN_I_D32_MM |
| { 2003, 4, 1, 4, 698, 0, 0x4ULL, nullptr, nullptr, OperandInfo314, -1 ,nullptr }, // Inst #2003 = MOVN_I_D64 |
| { 2004, 4, 1, 4, 477, 0, 0x4ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2004 = MOVN_I_I |
| { 2005, 4, 1, 4, 902, 0, 0x4ULL, nullptr, nullptr, OperandInfo316, -1 ,nullptr }, // Inst #2005 = MOVN_I_I64 |
| { 2006, 4, 1, 4, 1551, 0, 0x4ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2006 = MOVN_I_MM |
| { 2007, 4, 1, 4, 699, 0, 0x4ULL, nullptr, nullptr, OperandInfo317, -1 ,nullptr }, // Inst #2007 = MOVN_I_S |
| { 2008, 4, 1, 4, 1230, 0, 0x4ULL, nullptr, nullptr, OperandInfo317, -1 ,nullptr }, // Inst #2008 = MOVN_I_S_MM |
| { 2009, 4, 1, 4, 528, 0, 0x4ULL, nullptr, nullptr, OperandInfo304, -1 ,nullptr }, // Inst #2009 = MOVT_D32 |
| { 2010, 4, 1, 4, 1231, 0, 0x4ULL, nullptr, nullptr, OperandInfo304, -1 ,nullptr }, // Inst #2010 = MOVT_D32_MM |
| { 2011, 4, 1, 4, 528, 0, 0x4ULL, nullptr, nullptr, OperandInfo305, -1 ,nullptr }, // Inst #2011 = MOVT_D64 |
| { 2012, 4, 1, 4, 690, 0, 0x4ULL, nullptr, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #2012 = MOVT_I |
| { 2013, 4, 1, 4, 1204, 0, 0x4ULL, nullptr, nullptr, OperandInfo307, -1 ,nullptr }, // Inst #2013 = MOVT_I64 |
| { 2014, 4, 1, 4, 881, 0, 0x4ULL, nullptr, nullptr, OperandInfo306, -1 ,nullptr }, // Inst #2014 = MOVT_I_MM |
| { 2015, 4, 1, 4, 529, 0, 0x4ULL, nullptr, nullptr, OperandInfo308, -1 ,nullptr }, // Inst #2015 = MOVT_S |
| { 2016, 4, 1, 4, 1232, 0, 0x4ULL, nullptr, nullptr, OperandInfo308, -1 ,nullptr }, // Inst #2016 = MOVT_S_MM |
| { 2017, 4, 1, 4, 1209, 0, 0x4ULL, nullptr, nullptr, OperandInfo309, -1 ,nullptr }, // Inst #2017 = MOVZ_I64_D64 |
| { 2018, 4, 1, 4, 903, 0, 0x4ULL, nullptr, nullptr, OperandInfo310, -1 ,nullptr }, // Inst #2018 = MOVZ_I64_I |
| { 2019, 4, 1, 4, 903, 0, 0x4ULL, nullptr, nullptr, OperandInfo311, -1 ,nullptr }, // Inst #2019 = MOVZ_I64_I64 |
| { 2020, 4, 1, 4, 1206, 0, 0x4ULL, nullptr, nullptr, OperandInfo312, -1 ,nullptr }, // Inst #2020 = MOVZ_I64_S |
| { 2021, 4, 1, 4, 700, 0, 0x4ULL, nullptr, nullptr, OperandInfo313, -1 ,nullptr }, // Inst #2021 = MOVZ_I_D32 |
| { 2022, 4, 1, 4, 1233, 0, 0x4ULL, nullptr, nullptr, OperandInfo313, -1 ,nullptr }, // Inst #2022 = MOVZ_I_D32_MM |
| { 2023, 4, 1, 4, 700, 0, 0x4ULL, nullptr, nullptr, OperandInfo314, -1 ,nullptr }, // Inst #2023 = MOVZ_I_D64 |
| { 2024, 4, 1, 4, 478, 0, 0x4ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2024 = MOVZ_I_I |
| { 2025, 4, 1, 4, 903, 0, 0x4ULL, nullptr, nullptr, OperandInfo316, -1 ,nullptr }, // Inst #2025 = MOVZ_I_I64 |
| { 2026, 4, 1, 4, 1552, 0, 0x4ULL, nullptr, nullptr, OperandInfo315, -1 ,nullptr }, // Inst #2026 = MOVZ_I_MM |
| { 2027, 4, 1, 4, 701, 0, 0x4ULL, nullptr, nullptr, OperandInfo317, -1 ,nullptr }, // Inst #2027 = MOVZ_I_S |
| { 2028, 4, 1, 4, 1234, 0, 0x4ULL, nullptr, nullptr, OperandInfo317, -1 ,nullptr }, // Inst #2028 = MOVZ_I_S_MM |
| { 2029, 2, 0, 4, 847, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList6, ImplicitList6, OperandInfo38, -1 ,nullptr }, // Inst #2029 = MSUB |
| { 2030, 4, 1, 4, 1226, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo293, -1 ,nullptr }, // Inst #2030 = MSUBF_D |
| { 2031, 4, 1, 4, 1320, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo293, -1 ,nullptr }, // Inst #2031 = MSUBF_D_MMR6 |
| { 2032, 4, 1, 4, 1224, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo294, -1 ,nullptr }, // Inst #2032 = MSUBF_S |
| { 2033, 4, 1, 4, 1321, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo294, -1 ,nullptr }, // Inst #2033 = MSUBF_S_MMR6 |
| { 2034, 4, 1, 4, 665, 0, 0x6ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #2034 = MSUBR_Q_H |
| { 2035, 4, 1, 4, 665, 0, 0x6ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #2035 = MSUBR_Q_W |
| { 2036, 2, 0, 4, 848, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList6, ImplicitList6, OperandInfo38, -1 ,nullptr }, // Inst #2036 = MSUBU |
| { 2037, 4, 1, 4, 1390, 0, 0x6ULL, nullptr, nullptr, OperandInfo233, -1 ,nullptr }, // Inst #2037 = MSUBU_DSP |
| { 2038, 4, 1, 4, 1553, 0, 0x6ULL, nullptr, nullptr, OperandInfo233, -1 ,nullptr }, // Inst #2038 = MSUBU_DSP_MM |
| { 2039, 2, 0, 4, 875, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList6, ImplicitList6, OperandInfo38, -1 ,nullptr }, // Inst #2039 = MSUBU_MM |
| { 2040, 4, 1, 4, 660, 0, 0x6ULL, nullptr, nullptr, OperandInfo186, -1 ,nullptr }, // Inst #2040 = MSUBV_B |
| { 2041, 4, 1, 4, 660, 0, 0x6ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #2041 = MSUBV_D |
| { 2042, 4, 1, 4, 660, 0, 0x6ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #2042 = MSUBV_H |
| { 2043, 4, 1, 4, 660, 0, 0x6ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #2043 = MSUBV_W |
| { 2044, 4, 1, 4, 671, 0, 0x4ULL, nullptr, nullptr, OperandInfo295, -1 ,nullptr }, // Inst #2044 = MSUB_D32 |
| { 2045, 4, 1, 4, 1272, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo295, -1 ,nullptr }, // Inst #2045 = MSUB_D32_MM |
| { 2046, 4, 1, 4, 671, 0, 0x4ULL, nullptr, nullptr, OperandInfo296, -1 ,nullptr }, // Inst #2046 = MSUB_D64 |
| { 2047, 4, 1, 4, 1391, 0, 0x6ULL, nullptr, nullptr, OperandInfo233, -1 ,nullptr }, // Inst #2047 = MSUB_DSP |
| { 2048, 4, 1, 4, 1554, 0, 0x6ULL, nullptr, nullptr, OperandInfo233, -1 ,nullptr }, // Inst #2048 = MSUB_DSP_MM |
| { 2049, 2, 0, 4, 874, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, ImplicitList6, ImplicitList6, OperandInfo38, -1 ,nullptr }, // Inst #2049 = MSUB_MM |
| { 2050, 4, 1, 4, 666, 0, 0x6ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #2050 = MSUB_Q_H |
| { 2051, 4, 1, 4, 666, 0, 0x6ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #2051 = MSUB_Q_W |
| { 2052, 4, 1, 4, 672, 0, 0x4ULL, nullptr, nullptr, OperandInfo297, -1 ,nullptr }, // Inst #2052 = MSUB_S |
| { 2053, 4, 1, 4, 1271, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo297, -1 ,nullptr }, // Inst #2053 = MSUB_S_MM |
| { 2054, 3, 1, 4, 412, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr }, // Inst #2054 = MTC0 |
| { 2055, 3, 1, 4, 1036, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr }, // Inst #2055 = MTC0_MMR6 |
| { 2056, 2, 1, 4, 678, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast), 0x4ULL, nullptr, nullptr, OperandInfo120, -1 ,nullptr }, // Inst #2056 = MTC1 |
| { 2057, 2, 1, 4, 678, 0|(1ULL<<MCID::MoveReg), 0x4ULL, nullptr, nullptr, OperandInfo126, -1 ,nullptr }, // Inst #2057 = MTC1_D64 |
| { 2058, 2, 1, 4, 1258, 0|(1ULL<<MCID::MoveReg), 0x4ULL, nullptr, nullptr, OperandInfo126, -1 ,nullptr }, // Inst #2058 = MTC1_D64_MM |
| { 2059, 2, 1, 4, 1258, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast), 0x4ULL, nullptr, nullptr, OperandInfo120, -1 ,nullptr }, // Inst #2059 = MTC1_MM |
| { 2060, 2, 1, 4, 1302, 0|(1ULL<<MCID::Bitcast), 0x6ULL, nullptr, nullptr, OperandInfo120, -1 ,nullptr }, // Inst #2060 = MTC1_MMR6 |
| { 2061, 3, 1, 4, 414, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo318, -1 ,nullptr }, // Inst #2061 = MTC2 |
| { 2062, 2, 1, 4, 1037, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo212, -1 ,nullptr }, // Inst #2062 = MTC2_MMR6 |
| { 2063, 3, 1, 4, 418, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr }, // Inst #2063 = MTGC0 |
| { 2064, 3, 1, 4, 1070, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr }, // Inst #2064 = MTGC0_MM |
| { 2065, 3, 1, 4, 1035, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr }, // Inst #2065 = MTHC0_MMR6 |
| { 2066, 3, 1, 4, 679, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo319, -1 ,nullptr }, // Inst #2066 = MTHC1_D32 |
| { 2067, 3, 1, 4, 1259, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo319, -1 ,nullptr }, // Inst #2067 = MTHC1_D32_MM |
| { 2068, 3, 1, 4, 679, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo320, -1 ,nullptr }, // Inst #2068 = MTHC1_D64 |
| { 2069, 3, 1, 4, 1259, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo320, -1 ,nullptr }, // Inst #2069 = MTHC1_D64_MM |
| { 2070, 2, 1, 4, 1037, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo212, -1 ,nullptr }, // Inst #2070 = MTHC2_MMR6 |
| { 2071, 3, 1, 4, 419, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr }, // Inst #2071 = MTHGC0 |
| { 2072, 3, 1, 4, 1071, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr }, // Inst #2072 = MTHGC0_MM |
| { 2073, 1, 0, 4, 488, 0|(1ULL<<MCID::MoveReg), 0x1ULL, nullptr, ImplicitList21, OperandInfo51, -1 ,nullptr }, // Inst #2073 = MTHI |
| { 2074, 1, 0, 4, 900, 0|(1ULL<<MCID::MoveReg), 0x1ULL, nullptr, ImplicitList22, OperandInfo88, -1 ,nullptr }, // Inst #2074 = MTHI64 |
| { 2075, 2, 1, 4, 1344, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo321, -1 ,nullptr }, // Inst #2075 = MTHI_DSP |
| { 2076, 2, 1, 4, 1555, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo321, -1 ,nullptr }, // Inst #2076 = MTHI_DSP_MM |
| { 2077, 1, 0, 4, 882, 0|(1ULL<<MCID::MoveReg), 0x1ULL, nullptr, ImplicitList21, OperandInfo51, -1 ,nullptr }, // Inst #2077 = MTHI_MM |
| { 2078, 3, 1, 4, 1343, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList4, OperandInfo322, -1 ,nullptr }, // Inst #2078 = MTHLIP |
| { 2079, 3, 1, 4, 1556, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList4, OperandInfo322, -1 ,nullptr }, // Inst #2079 = MTHLIP_MM |
| { 2080, 1, 0, 4, 488, 0|(1ULL<<MCID::MoveReg), 0x1ULL, nullptr, ImplicitList23, OperandInfo51, -1 ,nullptr }, // Inst #2080 = MTLO |
| { 2081, 1, 0, 4, 900, 0|(1ULL<<MCID::MoveReg), 0x1ULL, nullptr, ImplicitList24, OperandInfo88, -1 ,nullptr }, // Inst #2081 = MTLO64 |
| { 2082, 2, 1, 4, 1345, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo323, -1 ,nullptr }, // Inst #2082 = MTLO_DSP |
| { 2083, 2, 1, 4, 1557, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo323, -1 ,nullptr }, // Inst #2083 = MTLO_DSP_MM |
| { 2084, 1, 0, 4, 882, 0|(1ULL<<MCID::MoveReg), 0x1ULL, nullptr, ImplicitList23, OperandInfo51, -1 ,nullptr }, // Inst #2084 = MTLO_MM |
| { 2085, 1, 0, 4, 1197, 0|(1ULL<<MCID::MoveReg), 0x1ULL, nullptr, ImplicitList25, OperandInfo88, -1 ,nullptr }, // Inst #2085 = MTM0 |
| { 2086, 1, 0, 4, 1197, 0|(1ULL<<MCID::MoveReg), 0x1ULL, nullptr, ImplicitList26, OperandInfo88, -1 ,nullptr }, // Inst #2086 = MTM1 |
| { 2087, 1, 0, 4, 1197, 0|(1ULL<<MCID::MoveReg), 0x1ULL, nullptr, ImplicitList27, OperandInfo88, -1 ,nullptr }, // Inst #2087 = MTM2 |
| { 2088, 1, 0, 4, 1197, 0|(1ULL<<MCID::MoveReg), 0x1ULL, nullptr, ImplicitList28, OperandInfo88, -1 ,nullptr }, // Inst #2088 = MTP0 |
| { 2089, 1, 0, 4, 1197, 0|(1ULL<<MCID::MoveReg), 0x1ULL, nullptr, ImplicitList29, OperandInfo88, -1 ,nullptr }, // Inst #2089 = MTP1 |
| { 2090, 1, 0, 4, 1197, 0|(1ULL<<MCID::MoveReg), 0x1ULL, nullptr, ImplicitList30, OperandInfo88, -1 ,nullptr }, // Inst #2090 = MTP2 |
| { 2091, 5, 1, 4, 1056, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo301, -1 ,nullptr }, // Inst #2091 = MTTR |
| { 2092, 3, 1, 4, 861, 0, 0x6ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #2092 = MUH |
| { 2093, 3, 1, 4, 862, 0, 0x6ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #2093 = MUHU |
| { 2094, 3, 1, 4, 884, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #2094 = MUHU_MMR6 |
| { 2095, 3, 1, 4, 885, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #2095 = MUH_MMR6 |
| { 2096, 3, 1, 4, 481, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, ImplicitList6, OperandInfo65, -1 ,nullptr }, // Inst #2096 = MUL |
| { 2097, 3, 1, 4, 1392, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList31, OperandInfo204, -1 ,nullptr }, // Inst #2097 = MULEQ_S_W_PHL |
| { 2098, 3, 1, 4, 1558, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList31, OperandInfo204, -1 ,nullptr }, // Inst #2098 = MULEQ_S_W_PHL_MM |
| { 2099, 3, 1, 4, 1393, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList31, OperandInfo204, -1 ,nullptr }, // Inst #2099 = MULEQ_S_W_PHR |
| { 2100, 3, 1, 4, 1559, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList31, OperandInfo204, -1 ,nullptr }, // Inst #2100 = MULEQ_S_W_PHR_MM |
| { 2101, 3, 1, 4, 1394, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList31, OperandInfo163, -1 ,nullptr }, // Inst #2101 = MULEU_S_PH_QBL |
| { 2102, 3, 1, 4, 1560, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList31, OperandInfo163, -1 ,nullptr }, // Inst #2102 = MULEU_S_PH_QBL_MM |
| { 2103, 3, 1, 4, 1395, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList31, OperandInfo163, -1 ,nullptr }, // Inst #2103 = MULEU_S_PH_QBR |
| { 2104, 3, 1, 4, 1561, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList31, OperandInfo163, -1 ,nullptr }, // Inst #2104 = MULEU_S_PH_QBR_MM |
| { 2105, 3, 1, 4, 1396, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList31, OperandInfo163, -1 ,nullptr }, // Inst #2105 = MULQ_RS_PH |
| { 2106, 3, 1, 4, 1562, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList31, OperandInfo163, -1 ,nullptr }, // Inst #2106 = MULQ_RS_PH_MM |
| { 2107, 3, 1, 4, 1473, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList31, OperandInfo65, -1 ,nullptr }, // Inst #2107 = MULQ_RS_W |
| { 2108, 3, 1, 4, 1637, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList31, OperandInfo65, -1 ,nullptr }, // Inst #2108 = MULQ_RS_W_MMR2 |
| { 2109, 3, 1, 4, 1474, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList31, OperandInfo163, -1 ,nullptr }, // Inst #2109 = MULQ_S_PH |
| { 2110, 3, 1, 4, 1638, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList31, OperandInfo163, -1 ,nullptr }, // Inst #2110 = MULQ_S_PH_MMR2 |
| { 2111, 3, 1, 4, 1475, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList31, OperandInfo65, -1 ,nullptr }, // Inst #2111 = MULQ_S_W |
| { 2112, 3, 1, 4, 1639, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList31, OperandInfo65, -1 ,nullptr }, // Inst #2112 = MULQ_S_W_MMR2 |
| { 2113, 3, 1, 4, 667, 0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #2113 = MULR_Q_H |
| { 2114, 3, 1, 4, 667, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #2114 = MULR_Q_W |
| { 2115, 4, 1, 4, 1397, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo233, -1 ,nullptr }, // Inst #2115 = MULSAQ_S_W_PH |
| { 2116, 4, 1, 4, 1563, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList13, OperandInfo233, -1 ,nullptr }, // Inst #2116 = MULSAQ_S_W_PH_MM |
| { 2117, 4, 1, 4, 1476, 0, 0x6ULL, nullptr, nullptr, OperandInfo233, -1 ,nullptr }, // Inst #2117 = MULSA_W_PH |
| { 2118, 4, 1, 4, 1640, 0, 0x6ULL, nullptr, nullptr, OperandInfo233, -1 ,nullptr }, // Inst #2118 = MULSA_W_PH_MMR2 |
| { 2119, 2, 0, 4, 482, 0|(1ULL<<MCID::Commutable), 0x1ULL, nullptr, ImplicitList6, OperandInfo38, -1 ,nullptr }, // Inst #2119 = MULT |
| { 2120, 3, 1, 4, 1398, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr }, // Inst #2120 = MULTU_DSP |
| { 2121, 3, 1, 4, 1564, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr }, // Inst #2121 = MULTU_DSP_MM |
| { 2122, 3, 1, 4, 1399, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr }, // Inst #2122 = MULT_DSP |
| { 2123, 3, 1, 4, 1565, 0|(1ULL<<MCID::Commutable), 0x6ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr }, // Inst #2123 = MULT_DSP_MM |
| { 2124, 2, 0, 4, 870, 0|(1ULL<<MCID::Commutable), 0x1ULL, nullptr, ImplicitList6, OperandInfo38, -1 ,nullptr }, // Inst #2124 = MULT_MM |
| { 2125, 2, 0, 4, 483, 0|(1ULL<<MCID::Commutable), 0x1ULL, nullptr, ImplicitList6, OperandInfo38, -1 ,nullptr }, // Inst #2125 = MULTu |
| { 2126, 2, 0, 4, 871, 0|(1ULL<<MCID::Commutable), 0x1ULL, nullptr, ImplicitList6, OperandInfo38, -1 ,nullptr }, // Inst #2126 = MULTu_MM |
| { 2127, 3, 1, 4, 863, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #2127 = MULU |
| { 2128, 3, 1, 4, 886, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #2128 = MULU_MMR6 |
| { 2129, 3, 1, 4, 662, 0, 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #2129 = MULV_B |
| { 2130, 3, 1, 4, 662, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #2130 = MULV_D |
| { 2131, 3, 1, 4, 662, 0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #2131 = MULV_H |
| { 2132, 3, 1, 4, 662, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #2132 = MULV_W |
| { 2133, 3, 1, 4, 876, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, ImplicitList6, OperandInfo65, -1 ,nullptr }, // Inst #2133 = MUL_MM |
| { 2134, 3, 1, 4, 887, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #2134 = MUL_MMR6 |
| { 2135, 3, 1, 4, 1471, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList31, OperandInfo163, -1 ,nullptr }, // Inst #2135 = MUL_PH |
| { 2136, 3, 1, 4, 1635, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList31, OperandInfo163, -1 ,nullptr }, // Inst #2136 = MUL_PH_MMR2 |
| { 2137, 3, 1, 4, 668, 0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #2137 = MUL_Q_H |
| { 2138, 3, 1, 4, 668, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #2138 = MUL_Q_W |
| { 2139, 3, 1, 4, 864, 0, 0x6ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #2139 = MUL_R6 |
| { 2140, 3, 1, 4, 1472, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList31, OperandInfo163, -1 ,nullptr }, // Inst #2140 = MUL_S_PH |
| { 2141, 3, 1, 4, 1636, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList31, OperandInfo163, -1 ,nullptr }, // Inst #2141 = MUL_S_PH_MMR2 |
| { 2142, 1, 1, 2, 727, 0|(1ULL<<MCID::MoveReg), 0x0ULL, ImplicitList21, nullptr, OperandInfo263, -1 ,nullptr }, // Inst #2142 = Mfhi16 |
| { 2143, 1, 1, 2, 727, 0, 0x0ULL, ImplicitList23, nullptr, OperandInfo263, -1 ,nullptr }, // Inst #2143 = Mflo16 |
| { 2144, 2, 1, 2, 727, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo324, -1 ,nullptr }, // Inst #2144 = Move32R16 |
| { 2145, 2, 1, 2, 727, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo325, -1 ,nullptr }, // Inst #2145 = MoveR3216 |
| { 2146, 2, 1, 4, 622, 0, 0x6ULL, nullptr, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #2146 = NLOC_B |
| { 2147, 2, 1, 4, 622, 0, 0x6ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #2147 = NLOC_D |
| { 2148, 2, 1, 4, 622, 0, 0x6ULL, nullptr, nullptr, OperandInfo326, -1 ,nullptr }, // Inst #2148 = NLOC_H |
| { 2149, 2, 1, 4, 622, 0, 0x6ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr }, // Inst #2149 = NLOC_W |
| { 2150, 2, 1, 4, 622, 0, 0x6ULL, nullptr, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #2150 = NLZC_B |
| { 2151, 2, 1, 4, 622, 0, 0x6ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #2151 = NLZC_D |
| { 2152, 2, 1, 4, 622, 0, 0x6ULL, nullptr, nullptr, OperandInfo326, -1 ,nullptr }, // Inst #2152 = NLZC_H |
| { 2153, 2, 1, 4, 622, 0, 0x6ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr }, // Inst #2153 = NLZC_W |
| { 2154, 4, 1, 4, 673, 0, 0x4ULL, nullptr, nullptr, OperandInfo295, -1 ,nullptr }, // Inst #2154 = NMADD_D32 |
| { 2155, 4, 1, 4, 1239, 0, 0x4ULL, nullptr, nullptr, OperandInfo295, -1 ,nullptr }, // Inst #2155 = NMADD_D32_MM |
| { 2156, 4, 1, 4, 673, 0, 0x4ULL, nullptr, nullptr, OperandInfo296, -1 ,nullptr }, // Inst #2156 = NMADD_D64 |
| { 2157, 4, 1, 4, 674, 0, 0x4ULL, nullptr, nullptr, OperandInfo297, -1 ,nullptr }, // Inst #2157 = NMADD_S |
| { 2158, 4, 1, 4, 1238, 0, 0x4ULL, nullptr, nullptr, OperandInfo297, -1 ,nullptr }, // Inst #2158 = NMADD_S_MM |
| { 2159, 4, 1, 4, 675, 0, 0x4ULL, nullptr, nullptr, OperandInfo295, -1 ,nullptr }, // Inst #2159 = NMSUB_D32 |
| { 2160, 4, 1, 4, 1241, 0, 0x4ULL, nullptr, nullptr, OperandInfo295, -1 ,nullptr }, // Inst #2160 = NMSUB_D32_MM |
| { 2161, 4, 1, 4, 675, 0, 0x4ULL, nullptr, nullptr, OperandInfo296, -1 ,nullptr }, // Inst #2161 = NMSUB_D64 |
| { 2162, 4, 1, 4, 676, 0, 0x4ULL, nullptr, nullptr, OperandInfo297, -1 ,nullptr }, // Inst #2162 = NMSUB_S |
| { 2163, 4, 1, 4, 1240, 0, 0x4ULL, nullptr, nullptr, OperandInfo297, -1 ,nullptr }, // Inst #2163 = NMSUB_S_MM |
| { 2164, 3, 1, 4, 361, 0|(1ULL<<MCID::Commutable), 0x1ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #2164 = NOR |
| { 2165, 3, 1, 4, 834, 0|(1ULL<<MCID::Commutable), 0x1ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #2165 = NOR64 |
| { 2166, 3, 1, 4, 544, 0, 0x6ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr }, // Inst #2166 = NORI_B |
| { 2167, 3, 1, 4, 744, 0|(1ULL<<MCID::Commutable), 0x1ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #2167 = NOR_MM |
| { 2168, 3, 1, 4, 785, 0|(1ULL<<MCID::Commutable), 0x1ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #2168 = NOR_MMR6 |
| { 2169, 3, 1, 4, 543, 0, 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #2169 = NOR_V |
| { 2170, 2, 1, 2, 745, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2170 = NOT16_MM |
| { 2171, 2, 1, 2, 786, 0, 0x0ULL, nullptr, nullptr, OperandInfo327, -1 ,nullptr }, // Inst #2171 = NOT16_MMR6 |
| { 2172, 2, 1, 2, 727, 0, 0x0ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr }, // Inst #2172 = NegRxRy16 |
| { 2173, 2, 1, 2, 727, 0, 0x0ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr }, // Inst #2173 = NotRxRy16 |
| { 2174, 3, 1, 4, 362, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #2174 = OR |
| { 2175, 3, 1, 2, 746, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #2175 = OR16_MM |
| { 2176, 3, 1, 2, 787, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #2176 = OR16_MMR6 |
| { 2177, 3, 1, 4, 835, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #2177 = OR64 |
| { 2178, 3, 1, 4, 544, 0, 0x6ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr }, // Inst #2178 = ORI_B |
| { 2179, 3, 1, 4, 788, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #2179 = ORI_MMR6 |
| { 2180, 3, 1, 4, 746, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #2180 = OR_MM |
| { 2181, 3, 1, 4, 787, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #2181 = OR_MMR6 |
| { 2182, 3, 1, 4, 543, 0, 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #2182 = OR_V |
| { 2183, 3, 1, 4, 495, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #2183 = ORi |
| { 2184, 3, 1, 4, 801, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #2184 = ORi64 |
| { 2185, 3, 1, 4, 747, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #2185 = ORi_MM |
| { 2186, 3, 1, 2, 727, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo176, -1 ,nullptr }, // Inst #2186 = OrRxRxRy16 |
| { 2187, 3, 1, 4, 1400, 0, 0x6ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #2187 = PACKRL_PH |
| { 2188, 3, 1, 4, 1566, 0, 0x6ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #2188 = PACKRL_PH_MM |
| { 2189, 0, 0, 4, 400, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2189 = PAUSE |
| { 2190, 0, 0, 4, 1026, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2190 = PAUSE_MM |
| { 2191, 0, 0, 4, 1043, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2191 = PAUSE_MMR6 |
| { 2192, 3, 1, 4, 621, 0, 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #2192 = PCKEV_B |
| { 2193, 3, 1, 4, 621, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #2193 = PCKEV_D |
| { 2194, 3, 1, 4, 621, 0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #2194 = PCKEV_H |
| { 2195, 3, 1, 4, 621, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #2195 = PCKEV_W |
| { 2196, 3, 1, 4, 621, 0, 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #2196 = PCKOD_B |
| { 2197, 3, 1, 4, 621, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #2197 = PCKOD_D |
| { 2198, 3, 1, 4, 621, 0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #2198 = PCKOD_H |
| { 2199, 3, 1, 4, 621, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #2199 = PCKOD_W |
| { 2200, 2, 1, 4, 521, 0, 0x6ULL, nullptr, nullptr, OperandInfo303, -1 ,nullptr }, // Inst #2200 = PCNT_B |
| { 2201, 2, 1, 4, 521, 0, 0x6ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr }, // Inst #2201 = PCNT_D |
| { 2202, 2, 1, 4, 521, 0, 0x6ULL, nullptr, nullptr, OperandInfo326, -1 ,nullptr }, // Inst #2202 = PCNT_H |
| { 2203, 2, 1, 4, 521, 0, 0x6ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr }, // Inst #2203 = PCNT_W |
| { 2204, 3, 1, 4, 1401, 0|(1ULL<<MCID::MayLoad), 0x6ULL, ImplicitList10, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #2204 = PICK_PH |
| { 2205, 3, 1, 4, 1567, 0|(1ULL<<MCID::MayLoad), 0x6ULL, ImplicitList10, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #2205 = PICK_PH_MM |
| { 2206, 3, 1, 4, 1402, 0|(1ULL<<MCID::MayLoad), 0x6ULL, ImplicitList10, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #2206 = PICK_QB |
| { 2207, 3, 1, 4, 1568, 0|(1ULL<<MCID::MayLoad), 0x6ULL, ImplicitList10, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #2207 = PICK_QB_MM |
| { 2208, 3, 1, 4, 637, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo240, -1 ,nullptr }, // Inst #2208 = PLL_PS64 |
| { 2209, 3, 1, 4, 637, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo240, -1 ,nullptr }, // Inst #2209 = PLU_PS64 |
| { 2210, 2, 1, 4, 1195, 0, 0x1ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #2210 = POP |
| { 2211, 2, 1, 4, 1404, 0, 0x6ULL, nullptr, nullptr, OperandInfo159, -1 ,nullptr }, // Inst #2211 = PRECEQU_PH_QBL |
| { 2212, 2, 1, 4, 1403, 0, 0x6ULL, nullptr, nullptr, OperandInfo159, -1 ,nullptr }, // Inst #2212 = PRECEQU_PH_QBLA |
| { 2213, 2, 1, 4, 1569, 0, 0x6ULL, nullptr, nullptr, OperandInfo159, -1 ,nullptr }, // Inst #2213 = PRECEQU_PH_QBLA_MM |
| { 2214, 2, 1, 4, 1570, 0, 0x6ULL, nullptr, nullptr, OperandInfo159, -1 ,nullptr }, // Inst #2214 = PRECEQU_PH_QBL_MM |
| { 2215, 2, 1, 4, 1406, 0, 0x6ULL, nullptr, nullptr, OperandInfo159, -1 ,nullptr }, // Inst #2215 = PRECEQU_PH_QBR |
| { 2216, 2, 1, 4, 1405, 0, 0x6ULL, nullptr, nullptr, OperandInfo159, -1 ,nullptr }, // Inst #2216 = PRECEQU_PH_QBRA |
| { 2217, 2, 1, 4, 1571, 0, 0x6ULL, nullptr, nullptr, OperandInfo159, -1 ,nullptr }, // Inst #2217 = PRECEQU_PH_QBRA_MM |
| { 2218, 2, 1, 4, 1572, 0, 0x6ULL, nullptr, nullptr, OperandInfo159, -1 ,nullptr }, // Inst #2218 = PRECEQU_PH_QBR_MM |
| { 2219, 2, 1, 4, 1407, 0, 0x6ULL, nullptr, nullptr, OperandInfo328, -1 ,nullptr }, // Inst #2219 = PRECEQ_W_PHL |
| { 2220, 2, 1, 4, 1573, 0, 0x6ULL, nullptr, nullptr, OperandInfo328, -1 ,nullptr }, // Inst #2220 = PRECEQ_W_PHL_MM |
| { 2221, 2, 1, 4, 1408, 0, 0x6ULL, nullptr, nullptr, OperandInfo328, -1 ,nullptr }, // Inst #2221 = PRECEQ_W_PHR |
| { 2222, 2, 1, 4, 1574, 0, 0x6ULL, nullptr, nullptr, OperandInfo328, -1 ,nullptr }, // Inst #2222 = PRECEQ_W_PHR_MM |
| { 2223, 2, 1, 4, 1410, 0, 0x6ULL, nullptr, nullptr, OperandInfo159, -1 ,nullptr }, // Inst #2223 = PRECEU_PH_QBL |
| { 2224, 2, 1, 4, 1409, 0, 0x6ULL, nullptr, nullptr, OperandInfo159, -1 ,nullptr }, // Inst #2224 = PRECEU_PH_QBLA |
| { 2225, 2, 1, 4, 1575, 0, 0x6ULL, nullptr, nullptr, OperandInfo159, -1 ,nullptr }, // Inst #2225 = PRECEU_PH_QBLA_MM |
| { 2226, 2, 1, 4, 1576, 0, 0x6ULL, nullptr, nullptr, OperandInfo159, -1 ,nullptr }, // Inst #2226 = PRECEU_PH_QBL_MM |
| { 2227, 2, 1, 4, 1412, 0, 0x6ULL, nullptr, nullptr, OperandInfo159, -1 ,nullptr }, // Inst #2227 = PRECEU_PH_QBR |
| { 2228, 2, 1, 4, 1411, 0, 0x6ULL, nullptr, nullptr, OperandInfo159, -1 ,nullptr }, // Inst #2228 = PRECEU_PH_QBRA |
| { 2229, 2, 1, 4, 1577, 0, 0x6ULL, nullptr, nullptr, OperandInfo159, -1 ,nullptr }, // Inst #2229 = PRECEU_PH_QBRA_MM |
| { 2230, 2, 1, 4, 1578, 0, 0x6ULL, nullptr, nullptr, OperandInfo159, -1 ,nullptr }, // Inst #2230 = PRECEU_PH_QBR_MM |
| { 2231, 3, 1, 4, 1413, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList32, OperandInfo163, -1 ,nullptr }, // Inst #2231 = PRECRQU_S_QB_PH |
| { 2232, 3, 1, 4, 1579, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList32, OperandInfo163, -1 ,nullptr }, // Inst #2232 = PRECRQU_S_QB_PH_MM |
| { 2233, 3, 1, 4, 1414, 0, 0x6ULL, nullptr, nullptr, OperandInfo329, -1 ,nullptr }, // Inst #2233 = PRECRQ_PH_W |
| { 2234, 3, 1, 4, 1580, 0, 0x6ULL, nullptr, nullptr, OperandInfo329, -1 ,nullptr }, // Inst #2234 = PRECRQ_PH_W_MM |
| { 2235, 3, 1, 4, 1415, 0, 0x6ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #2235 = PRECRQ_QB_PH |
| { 2236, 3, 1, 4, 1581, 0, 0x6ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #2236 = PRECRQ_QB_PH_MM |
| { 2237, 3, 1, 4, 1416, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList32, OperandInfo329, -1 ,nullptr }, // Inst #2237 = PRECRQ_RS_PH_W |
| { 2238, 3, 1, 4, 1582, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList32, OperandInfo329, -1 ,nullptr }, // Inst #2238 = PRECRQ_RS_PH_W_MM |
| { 2239, 3, 1, 4, 1477, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #2239 = PRECR_QB_PH |
| { 2240, 3, 1, 4, 1641, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #2240 = PRECR_QB_PH_MMR2 |
| { 2241, 4, 1, 4, 1478, 0, 0x6ULL, nullptr, nullptr, OperandInfo330, -1 ,nullptr }, // Inst #2241 = PRECR_SRA_PH_W |
| { 2242, 4, 1, 4, 1642, 0, 0x6ULL, nullptr, nullptr, OperandInfo330, -1 ,nullptr }, // Inst #2242 = PRECR_SRA_PH_W_MMR2 |
| { 2243, 4, 1, 4, 1479, 0, 0x6ULL, nullptr, nullptr, OperandInfo330, -1 ,nullptr }, // Inst #2243 = PRECR_SRA_R_PH_W |
| { 2244, 4, 1, 4, 1643, 0, 0x6ULL, nullptr, nullptr, OperandInfo330, -1 ,nullptr }, // Inst #2244 = PRECR_SRA_R_PH_W_MMR2 |
| { 2245, 3, 0, 4, 463, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr }, // Inst #2245 = PREF |
| { 2246, 3, 0, 4, 464, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr }, // Inst #2246 = PREFE |
| { 2247, 3, 0, 4, 1098, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr }, // Inst #2247 = PREFE_MM |
| { 2248, 3, 0, 4, 1131, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo331, -1 ,nullptr }, // Inst #2248 = PREFX_MM |
| { 2249, 3, 0, 4, 1131, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr }, // Inst #2249 = PREF_MM |
| { 2250, 3, 0, 4, 1153, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr }, // Inst #2250 = PREF_MMR6 |
| { 2251, 3, 0, 4, 1079, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr }, // Inst #2251 = PREF_R6 |
| { 2252, 4, 1, 4, 1480, 0, 0x6ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #2252 = PREPEND |
| { 2253, 4, 1, 4, 1644, 0, 0x6ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #2253 = PREPEND_MMR2 |
| { 2254, 2, 1, 4, 1417, 0, 0x6ULL, nullptr, nullptr, OperandInfo328, -1 ,nullptr }, // Inst #2254 = RADDU_W_QB |
| { 2255, 2, 1, 4, 1583, 0, 0x6ULL, nullptr, nullptr, OperandInfo328, -1 ,nullptr }, // Inst #2255 = RADDU_W_QB_MM |
| { 2256, 2, 1, 4, 1418, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #2256 = RDDSP |
| { 2257, 2, 1, 4, 1584, 0|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #2257 = RDDSP_MM |
| { 2258, 3, 1, 4, 475, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo332, -1 ,nullptr }, // Inst #2258 = RDHWR |
| { 2259, 3, 1, 4, 901, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo333, -1 ,nullptr }, // Inst #2259 = RDHWR64 |
| { 2260, 3, 1, 4, 883, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo332, -1 ,nullptr }, // Inst #2260 = RDHWR_MM |
| { 2261, 3, 1, 4, 892, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo332, -1 ,nullptr }, // Inst #2261 = RDHWR_MMR6 |
| { 2262, 2, 1, 4, 1028, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #2262 = RDPGPR_MMR6 |
| { 2263, 2, 1, 4, 644, 0, 0x4ULL, nullptr, nullptr, OperandInfo238, -1 ,nullptr }, // Inst #2263 = RECIP_D32 |
| { 2264, 2, 1, 4, 1278, 0, 0x4ULL, nullptr, nullptr, OperandInfo238, -1 ,nullptr }, // Inst #2264 = RECIP_D32_MM |
| { 2265, 2, 1, 4, 644, 0, 0x4ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #2265 = RECIP_D64 |
| { 2266, 2, 1, 4, 1278, 0, 0x4ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #2266 = RECIP_D64_MM |
| { 2267, 2, 1, 4, 646, 0, 0x4ULL, nullptr, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #2267 = RECIP_S |
| { 2268, 2, 1, 4, 1277, 0, 0x4ULL, nullptr, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #2268 = RECIP_S_MM |
| { 2269, 2, 1, 4, 1419, 0, 0x6ULL, nullptr, nullptr, OperandInfo334, -1 ,nullptr }, // Inst #2269 = REPLV_PH |
| { 2270, 2, 1, 4, 1585, 0, 0x6ULL, nullptr, nullptr, OperandInfo334, -1 ,nullptr }, // Inst #2270 = REPLV_PH_MM |
| { 2271, 2, 1, 4, 1420, 0, 0x6ULL, nullptr, nullptr, OperandInfo334, -1 ,nullptr }, // Inst #2271 = REPLV_QB |
| { 2272, 2, 1, 4, 1586, 0, 0x6ULL, nullptr, nullptr, OperandInfo334, -1 ,nullptr }, // Inst #2272 = REPLV_QB_MM |
| { 2273, 2, 1, 4, 1421, 0, 0x6ULL, nullptr, nullptr, OperandInfo335, -1 ,nullptr }, // Inst #2273 = REPL_PH |
| { 2274, 2, 1, 4, 1587, 0, 0x6ULL, nullptr, nullptr, OperandInfo335, -1 ,nullptr }, // Inst #2274 = REPL_PH_MM |
| { 2275, 2, 1, 4, 1422, 0, 0x6ULL, nullptr, nullptr, OperandInfo335, -1 ,nullptr }, // Inst #2275 = REPL_QB |
| { 2276, 2, 1, 4, 1588, 0, 0x6ULL, nullptr, nullptr, OperandInfo335, -1 ,nullptr }, // Inst #2276 = REPL_QB_MM |
| { 2277, 2, 1, 4, 1219, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #2277 = RINT_D |
| { 2278, 2, 1, 4, 1317, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #2278 = RINT_D_MMR6 |
| { 2279, 2, 1, 4, 1218, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #2279 = RINT_S |
| { 2280, 2, 1, 4, 1317, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #2280 = RINT_S_MMR6 |
| { 2281, 3, 1, 4, 496, 0, 0x1ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #2281 = ROTR |
| { 2282, 3, 1, 4, 712, 0, 0x1ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #2282 = ROTRV |
| { 2283, 3, 1, 4, 748, 0, 0x1ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #2283 = ROTRV_MM |
| { 2284, 3, 1, 4, 749, 0, 0x1ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #2284 = ROTR_MM |
| { 2285, 2, 1, 4, 711, 0, 0x4ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #2285 = ROUND_L_D64 |
| { 2286, 2, 1, 4, 1298, 0, 0x4ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #2286 = ROUND_L_D_MMR6 |
| { 2287, 2, 1, 4, 711, 0, 0x4ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr }, // Inst #2287 = ROUND_L_S |
| { 2288, 2, 1, 4, 1298, 0, 0x4ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr }, // Inst #2288 = ROUND_L_S_MMR6 |
| { 2289, 2, 1, 4, 711, 0, 0x4ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #2289 = ROUND_W_D32 |
| { 2290, 2, 1, 4, 711, 0, 0x4ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr }, // Inst #2290 = ROUND_W_D64 |
| { 2291, 2, 1, 4, 1298, 0, 0x4ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #2291 = ROUND_W_D_MMR6 |
| { 2292, 2, 1, 4, 1244, 0, 0x4ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #2292 = ROUND_W_MM |
| { 2293, 2, 1, 4, 711, 0, 0x4ULL, nullptr, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #2293 = ROUND_W_S |
| { 2294, 2, 1, 4, 1244, 0, 0x4ULL, nullptr, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #2294 = ROUND_W_S_MM |
| { 2295, 2, 1, 4, 1298, 0, 0x4ULL, nullptr, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #2295 = ROUND_W_S_MMR6 |
| { 2296, 2, 1, 4, 645, 0, 0x4ULL, nullptr, nullptr, OperandInfo238, -1 ,nullptr }, // Inst #2296 = RSQRT_D32 |
| { 2297, 2, 1, 4, 1278, 0, 0x4ULL, nullptr, nullptr, OperandInfo238, -1 ,nullptr }, // Inst #2297 = RSQRT_D32_MM |
| { 2298, 2, 1, 4, 645, 0, 0x4ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #2298 = RSQRT_D64 |
| { 2299, 2, 1, 4, 1278, 0, 0x4ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #2299 = RSQRT_D64_MM |
| { 2300, 2, 1, 4, 647, 0, 0x4ULL, nullptr, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #2300 = RSQRT_S |
| { 2301, 2, 1, 4, 1277, 0, 0x4ULL, nullptr, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #2301 = RSQRT_S_MM |
| { 2302, 0, 0, 2, 1100, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, ImplicitList1, nullptr, -1 ,nullptr }, // Inst #2302 = Restore16 |
| { 2303, 0, 0, 2, 1100, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, ImplicitList1, nullptr, -1 ,nullptr }, // Inst #2303 = RestoreX16 |
| { 2304, 2, 0, 4, 1202, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo113, -1 ,nullptr }, // Inst #2304 = SAA |
| { 2305, 2, 0, 4, 1202, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo113, -1 ,nullptr }, // Inst #2305 = SAAD |
| { 2306, 3, 1, 4, 522, 0, 0x6ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr }, // Inst #2306 = SAT_S_B |
| { 2307, 3, 1, 4, 522, 0, 0x6ULL, nullptr, nullptr, OperandInfo167, -1 ,nullptr }, // Inst #2307 = SAT_S_D |
| { 2308, 3, 1, 4, 522, 0, 0x6ULL, nullptr, nullptr, OperandInfo168, -1 ,nullptr }, // Inst #2308 = SAT_S_H |
| { 2309, 3, 1, 4, 522, 0, 0x6ULL, nullptr, nullptr, OperandInfo169, -1 ,nullptr }, // Inst #2309 = SAT_S_W |
| { 2310, 3, 1, 4, 522, 0, 0x6ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr }, // Inst #2310 = SAT_U_B |
| { 2311, 3, 1, 4, 522, 0, 0x6ULL, nullptr, nullptr, OperandInfo167, -1 ,nullptr }, // Inst #2311 = SAT_U_D |
| { 2312, 3, 1, 4, 522, 0, 0x6ULL, nullptr, nullptr, OperandInfo168, -1 ,nullptr }, // Inst #2312 = SAT_U_H |
| { 2313, 3, 1, 4, 522, 0, 0x6ULL, nullptr, nullptr, OperandInfo169, -1 ,nullptr }, // Inst #2313 = SAT_U_W |
| { 2314, 3, 0, 4, 447, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #2314 = SB |
| { 2315, 3, 0, 2, 1122, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #2315 = SB16_MM |
| { 2316, 3, 0, 2, 1145, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #2316 = SB16_MMR6 |
| { 2317, 3, 0, 4, 1169, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo104, -1 ,nullptr }, // Inst #2317 = SB64 |
| { 2318, 3, 0, 4, 455, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #2318 = SBE |
| { 2319, 3, 0, 4, 1091, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #2319 = SBE_MM |
| { 2320, 3, 0, 4, 1092, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #2320 = SB_MM |
| { 2321, 3, 0, 4, 1145, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #2321 = SB_MMR6 |
| { 2322, 4, 1, 4, 454, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo337, -1 ,nullptr }, // Inst #2322 = SC |
| { 2323, 4, 1, 4, 1168, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo337, -1 ,nullptr }, // Inst #2323 = SC64 |
| { 2324, 4, 1, 4, 1180, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo338, -1 ,nullptr }, // Inst #2324 = SC64_R6 |
| { 2325, 4, 1, 4, 1168, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo339, -1 ,nullptr }, // Inst #2325 = SCD |
| { 2326, 4, 1, 4, 1181, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo340, -1 ,nullptr }, // Inst #2326 = SCD_R6 |
| { 2327, 4, 1, 4, 458, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo337, -1 ,nullptr }, // Inst #2327 = SCE |
| { 2328, 4, 1, 4, 1097, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo337, -1 ,nullptr }, // Inst #2328 = SCE_MM |
| { 2329, 4, 1, 4, 1123, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo337, -1 ,nullptr }, // Inst #2329 = SC_MM |
| { 2330, 4, 1, 4, 1072, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo337, -1 ,nullptr }, // Inst #2330 = SC_MMR6 |
| { 2331, 4, 1, 4, 1078, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo338, -1 ,nullptr }, // Inst #2331 = SC_R6 |
| { 2332, 3, 0, 4, 1167, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo104, -1 ,nullptr }, // Inst #2332 = SD |
| { 2333, 1, 0, 4, 384, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #2333 = SDBBP |
| { 2334, 1, 0, 2, 959, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #2334 = SDBBP16_MM |
| { 2335, 1, 0, 2, 1000, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #2335 = SDBBP16_MMR6 |
| { 2336, 1, 0, 4, 959, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #2336 = SDBBP_MM |
| { 2337, 1, 0, 4, 1000, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #2337 = SDBBP_MMR6 |
| { 2338, 1, 0, 4, 930, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #2338 = SDBBP_R6 |
| { 2339, 3, 0, 4, 691, 0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr }, // Inst #2339 = SDC1 |
| { 2340, 3, 0, 4, 691, 0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, nullptr, OperandInfo266, -1 ,nullptr }, // Inst #2340 = SDC164 |
| { 2341, 3, 0, 4, 1327, 0|(1ULL<<MCID::MayStore), 0x6ULL, nullptr, nullptr, OperandInfo266, -1 ,nullptr }, // Inst #2341 = SDC1_D64_MMR6 |
| { 2342, 3, 0, 4, 1279, 0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr }, // Inst #2342 = SDC1_MM |
| { 2343, 3, 0, 4, 452, 0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, nullptr, OperandInfo267, -1 ,nullptr }, // Inst #2343 = SDC2 |
| { 2344, 3, 0, 4, 1146, 0|(1ULL<<MCID::MayStore), 0x6ULL, nullptr, nullptr, OperandInfo268, -1 ,nullptr }, // Inst #2344 = SDC2_MMR6 |
| { 2345, 3, 0, 4, 1077, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo267, -1 ,nullptr }, // Inst #2345 = SDC2_R6 |
| { 2346, 3, 0, 4, 453, 0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, nullptr, OperandInfo269, -1 ,nullptr }, // Inst #2346 = SDC3 |
| { 2347, 2, 0, 4, 857, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, ImplicitList6, OperandInfo38, -1 ,nullptr }, // Inst #2347 = SDIV |
| { 2348, 2, 0, 4, 877, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, ImplicitList6, OperandInfo38, -1 ,nullptr }, // Inst #2348 = SDIV_MM |
| { 2349, 3, 0, 4, 1174, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo104, -1 ,nullptr }, // Inst #2349 = SDL |
| { 2350, 3, 0, 4, 1175, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo104, -1 ,nullptr }, // Inst #2350 = SDR |
| { 2351, 3, 0, 4, 692, 0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, nullptr, OperandInfo275, -1 ,nullptr }, // Inst #2351 = SDXC1 |
| { 2352, 3, 0, 4, 692, 0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #2352 = SDXC164 |
| { 2353, 2, 1, 4, 497, 0, 0x1ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #2353 = SEB |
| { 2354, 2, 1, 4, 802, 0, 0x1ULL, nullptr, nullptr, OperandInfo113, -1 ,nullptr }, // Inst #2354 = SEB64 |
| { 2355, 2, 1, 4, 750, 0, 0x1ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #2355 = SEB_MM |
| { 2356, 2, 1, 4, 498, 0, 0x1ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #2356 = SEH |
| { 2357, 2, 1, 4, 803, 0, 0x1ULL, nullptr, nullptr, OperandInfo113, -1 ,nullptr }, // Inst #2357 = SEH64 |
| { 2358, 2, 1, 4, 751, 0, 0x1ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #2358 = SEH_MM |
| { 2359, 3, 1, 4, 726, 0, 0x6ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #2359 = SELEQZ |
| { 2360, 3, 1, 4, 844, 0, 0x6ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #2360 = SELEQZ64 |
| { 2361, 3, 1, 4, 1211, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo240, -1 ,nullptr }, // Inst #2361 = SELEQZ_D |
| { 2362, 3, 1, 4, 1313, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo240, -1 ,nullptr }, // Inst #2362 = SELEQZ_D_MMR6 |
| { 2363, 3, 1, 4, 789, 0, 0x6ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #2363 = SELEQZ_MMR6 |
| { 2364, 3, 1, 4, 1210, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo241, -1 ,nullptr }, // Inst #2364 = SELEQZ_S |
| { 2365, 3, 1, 4, 1314, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo241, -1 ,nullptr }, // Inst #2365 = SELEQZ_S_MMR6 |
| { 2366, 3, 1, 4, 726, 0, 0x6ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #2366 = SELNEZ |
| { 2367, 3, 1, 4, 844, 0, 0x6ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #2367 = SELNEZ64 |
| { 2368, 3, 1, 4, 1211, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo240, -1 ,nullptr }, // Inst #2368 = SELNEZ_D |
| { 2369, 3, 1, 4, 1313, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo240, -1 ,nullptr }, // Inst #2369 = SELNEZ_D_MMR6 |
| { 2370, 3, 1, 4, 789, 0, 0x6ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #2370 = SELNEZ_MMR6 |
| { 2371, 3, 1, 4, 1210, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo241, -1 ,nullptr }, // Inst #2371 = SELNEZ_S |
| { 2372, 3, 1, 4, 1314, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo241, -1 ,nullptr }, // Inst #2372 = SELNEZ_S_MMR6 |
| { 2373, 4, 1, 4, 1221, 0, 0x6ULL, nullptr, nullptr, OperandInfo293, -1 ,nullptr }, // Inst #2373 = SEL_D |
| { 2374, 4, 1, 4, 1315, 0, 0x6ULL, nullptr, nullptr, OperandInfo293, -1 ,nullptr }, // Inst #2374 = SEL_D_MMR6 |
| { 2375, 4, 1, 4, 1222, 0, 0x6ULL, nullptr, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #2375 = SEL_S |
| { 2376, 4, 1, 4, 1316, 0, 0x6ULL, nullptr, nullptr, OperandInfo341, -1 ,nullptr }, // Inst #2376 = SEL_S_MMR6 |
| { 2377, 3, 1, 4, 1198, 0, 0x1ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #2377 = SEQ |
| { 2378, 3, 1, 4, 1199, 0, 0x2ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #2378 = SEQi |
| { 2379, 3, 0, 4, 448, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #2379 = SH |
| { 2380, 3, 0, 2, 1124, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #2380 = SH16_MM |
| { 2381, 3, 0, 2, 1147, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #2381 = SH16_MMR6 |
| { 2382, 3, 0, 4, 1170, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo104, -1 ,nullptr }, // Inst #2382 = SH64 |
| { 2383, 3, 0, 4, 456, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #2383 = SHE |
| { 2384, 3, 0, 4, 1093, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #2384 = SHE_MM |
| { 2385, 3, 1, 4, 538, 0, 0x6ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr }, // Inst #2385 = SHF_B |
| { 2386, 3, 1, 4, 538, 0, 0x6ULL, nullptr, nullptr, OperandInfo168, -1 ,nullptr }, // Inst #2386 = SHF_H |
| { 2387, 3, 1, 4, 538, 0, 0x6ULL, nullptr, nullptr, OperandInfo169, -1 ,nullptr }, // Inst #2387 = SHF_W |
| { 2388, 3, 1, 4, 1424, 0, 0x6ULL, nullptr, nullptr, OperandInfo342, -1 ,nullptr }, // Inst #2388 = SHILO |
| { 2389, 3, 1, 4, 1423, 0, 0x6ULL, nullptr, nullptr, OperandInfo322, -1 ,nullptr }, // Inst #2389 = SHILOV |
| { 2390, 3, 1, 4, 1589, 0, 0x6ULL, nullptr, nullptr, OperandInfo322, -1 ,nullptr }, // Inst #2390 = SHILOV_MM |
| { 2391, 3, 1, 4, 1590, 0, 0x6ULL, nullptr, nullptr, OperandInfo342, -1 ,nullptr }, // Inst #2391 = SHILO_MM |
| { 2392, 3, 1, 4, 1425, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList32, OperandInfo343, -1 ,nullptr }, // Inst #2392 = SHLLV_PH |
| { 2393, 3, 1, 4, 1591, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList32, OperandInfo343, -1 ,nullptr }, // Inst #2393 = SHLLV_PH_MM |
| { 2394, 3, 1, 4, 1426, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList32, OperandInfo343, -1 ,nullptr }, // Inst #2394 = SHLLV_QB |
| { 2395, 3, 1, 4, 1592, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList32, OperandInfo343, -1 ,nullptr }, // Inst #2395 = SHLLV_QB_MM |
| { 2396, 3, 1, 4, 1427, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList32, OperandInfo343, -1 ,nullptr }, // Inst #2396 = SHLLV_S_PH |
| { 2397, 3, 1, 4, 1593, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList32, OperandInfo343, -1 ,nullptr }, // Inst #2397 = SHLLV_S_PH_MM |
| { 2398, 3, 1, 4, 1428, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList32, OperandInfo65, -1 ,nullptr }, // Inst #2398 = SHLLV_S_W |
| { 2399, 3, 1, 4, 1594, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList32, OperandInfo65, -1 ,nullptr }, // Inst #2399 = SHLLV_S_W_MM |
| { 2400, 3, 1, 4, 1429, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList32, OperandInfo344, -1 ,nullptr }, // Inst #2400 = SHLL_PH |
| { 2401, 3, 1, 4, 1595, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList32, OperandInfo344, -1 ,nullptr }, // Inst #2401 = SHLL_PH_MM |
| { 2402, 3, 1, 4, 1430, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList32, OperandInfo344, -1 ,nullptr }, // Inst #2402 = SHLL_QB |
| { 2403, 3, 1, 4, 1596, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList32, OperandInfo344, -1 ,nullptr }, // Inst #2403 = SHLL_QB_MM |
| { 2404, 3, 1, 4, 1431, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList32, OperandInfo344, -1 ,nullptr }, // Inst #2404 = SHLL_S_PH |
| { 2405, 3, 1, 4, 1597, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList32, OperandInfo344, -1 ,nullptr }, // Inst #2405 = SHLL_S_PH_MM |
| { 2406, 3, 1, 4, 1432, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList32, OperandInfo66, -1 ,nullptr }, // Inst #2406 = SHLL_S_W |
| { 2407, 3, 1, 4, 1598, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList32, OperandInfo66, -1 ,nullptr }, // Inst #2407 = SHLL_S_W_MM |
| { 2408, 3, 1, 4, 1433, 0, 0x6ULL, nullptr, nullptr, OperandInfo343, -1 ,nullptr }, // Inst #2408 = SHRAV_PH |
| { 2409, 3, 1, 4, 1599, 0, 0x6ULL, nullptr, nullptr, OperandInfo343, -1 ,nullptr }, // Inst #2409 = SHRAV_PH_MM |
| { 2410, 3, 1, 4, 1483, 0, 0x6ULL, nullptr, nullptr, OperandInfo343, -1 ,nullptr }, // Inst #2410 = SHRAV_QB |
| { 2411, 3, 1, 4, 1647, 0, 0x6ULL, nullptr, nullptr, OperandInfo343, -1 ,nullptr }, // Inst #2411 = SHRAV_QB_MMR2 |
| { 2412, 3, 1, 4, 1434, 0, 0x6ULL, nullptr, nullptr, OperandInfo343, -1 ,nullptr }, // Inst #2412 = SHRAV_R_PH |
| { 2413, 3, 1, 4, 1600, 0, 0x6ULL, nullptr, nullptr, OperandInfo343, -1 ,nullptr }, // Inst #2413 = SHRAV_R_PH_MM |
| { 2414, 3, 1, 4, 1484, 0, 0x6ULL, nullptr, nullptr, OperandInfo343, -1 ,nullptr }, // Inst #2414 = SHRAV_R_QB |
| { 2415, 3, 1, 4, 1648, 0, 0x6ULL, nullptr, nullptr, OperandInfo343, -1 ,nullptr }, // Inst #2415 = SHRAV_R_QB_MMR2 |
| { 2416, 3, 1, 4, 1435, 0, 0x6ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #2416 = SHRAV_R_W |
| { 2417, 3, 1, 4, 1601, 0, 0x6ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #2417 = SHRAV_R_W_MM |
| { 2418, 3, 1, 4, 1436, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo344, -1 ,nullptr }, // Inst #2418 = SHRA_PH |
| { 2419, 3, 1, 4, 1602, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo344, -1 ,nullptr }, // Inst #2419 = SHRA_PH_MM |
| { 2420, 3, 1, 4, 1481, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo344, -1 ,nullptr }, // Inst #2420 = SHRA_QB |
| { 2421, 3, 1, 4, 1645, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo344, -1 ,nullptr }, // Inst #2421 = SHRA_QB_MMR2 |
| { 2422, 3, 1, 4, 1437, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo344, -1 ,nullptr }, // Inst #2422 = SHRA_R_PH |
| { 2423, 3, 1, 4, 1603, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo344, -1 ,nullptr }, // Inst #2423 = SHRA_R_PH_MM |
| { 2424, 3, 1, 4, 1482, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo344, -1 ,nullptr }, // Inst #2424 = SHRA_R_QB |
| { 2425, 3, 1, 4, 1646, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo344, -1 ,nullptr }, // Inst #2425 = SHRA_R_QB_MMR2 |
| { 2426, 3, 1, 4, 1438, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #2426 = SHRA_R_W |
| { 2427, 3, 1, 4, 1604, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #2427 = SHRA_R_W_MM |
| { 2428, 3, 1, 4, 1486, 0, 0x6ULL, nullptr, nullptr, OperandInfo343, -1 ,nullptr }, // Inst #2428 = SHRLV_PH |
| { 2429, 3, 1, 4, 1650, 0, 0x6ULL, nullptr, nullptr, OperandInfo343, -1 ,nullptr }, // Inst #2429 = SHRLV_PH_MMR2 |
| { 2430, 3, 1, 4, 1439, 0, 0x6ULL, nullptr, nullptr, OperandInfo343, -1 ,nullptr }, // Inst #2430 = SHRLV_QB |
| { 2431, 3, 1, 4, 1605, 0, 0x6ULL, nullptr, nullptr, OperandInfo343, -1 ,nullptr }, // Inst #2431 = SHRLV_QB_MM |
| { 2432, 3, 1, 4, 1485, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo344, -1 ,nullptr }, // Inst #2432 = SHRL_PH |
| { 2433, 3, 1, 4, 1649, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo344, -1 ,nullptr }, // Inst #2433 = SHRL_PH_MMR2 |
| { 2434, 3, 1, 4, 1440, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo344, -1 ,nullptr }, // Inst #2434 = SHRL_QB |
| { 2435, 3, 1, 4, 1606, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo344, -1 ,nullptr }, // Inst #2435 = SHRL_QB_MM |
| { 2436, 3, 0, 4, 1124, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #2436 = SH_MM |
| { 2437, 3, 0, 4, 1147, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #2437 = SH_MMR6 |
| { 2438, 1, 0, 4, 927, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #2438 = SIGRIE |
| { 2439, 1, 0, 4, 988, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #2439 = SIGRIE_MMR6 |
| { 2440, 4, 1, 4, 514, 0, 0x6ULL, nullptr, nullptr, OperandInfo182, -1 ,nullptr }, // Inst #2440 = SLDI_B |
| { 2441, 4, 1, 4, 514, 0, 0x6ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr }, // Inst #2441 = SLDI_D |
| { 2442, 4, 1, 4, 514, 0, 0x6ULL, nullptr, nullptr, OperandInfo184, -1 ,nullptr }, // Inst #2442 = SLDI_H |
| { 2443, 4, 1, 4, 514, 0, 0x6ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr }, // Inst #2443 = SLDI_W |
| { 2444, 4, 1, 4, 514, 0, 0x6ULL, nullptr, nullptr, OperandInfo345, -1 ,nullptr }, // Inst #2444 = SLD_B |
| { 2445, 4, 1, 4, 514, 0, 0x6ULL, nullptr, nullptr, OperandInfo346, -1 ,nullptr }, // Inst #2445 = SLD_D |
| { 2446, 4, 1, 4, 514, 0, 0x6ULL, nullptr, nullptr, OperandInfo347, -1 ,nullptr }, // Inst #2446 = SLD_H |
| { 2447, 4, 1, 4, 514, 0, 0x6ULL, nullptr, nullptr, OperandInfo348, -1 ,nullptr }, // Inst #2447 = SLD_W |
| { 2448, 3, 1, 4, 500, 0, 0x1ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #2448 = SLL |
| { 2449, 3, 1, 2, 752, 0, 0x0ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr }, // Inst #2449 = SLL16_MM |
| { 2450, 3, 1, 2, 790, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr }, // Inst #2450 = SLL16_MMR6 |
| { 2451, 2, 1, 4, 804, 0|(1ULL<<MCID::MoveReg), 0x1ULL, nullptr, nullptr, OperandInfo235, -1 ,nullptr }, // Inst #2451 = SLL64_32 |
| { 2452, 2, 1, 4, 804, 0|(1ULL<<MCID::MoveReg), 0x1ULL, nullptr, nullptr, OperandInfo113, -1 ,nullptr }, // Inst #2452 = SLL64_64 |
| { 2453, 3, 1, 4, 620, 0, 0x6ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr }, // Inst #2453 = SLLI_B |
| { 2454, 3, 1, 4, 620, 0, 0x6ULL, nullptr, nullptr, OperandInfo167, -1 ,nullptr }, // Inst #2454 = SLLI_D |
| { 2455, 3, 1, 4, 620, 0, 0x6ULL, nullptr, nullptr, OperandInfo168, -1 ,nullptr }, // Inst #2455 = SLLI_H |
| { 2456, 3, 1, 4, 620, 0, 0x6ULL, nullptr, nullptr, OperandInfo169, -1 ,nullptr }, // Inst #2456 = SLLI_W |
| { 2457, 3, 1, 4, 505, 0, 0x1ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #2457 = SLLV |
| { 2458, 3, 1, 4, 753, 0, 0x1ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #2458 = SLLV_MM |
| { 2459, 3, 1, 4, 620, 0, 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #2459 = SLL_B |
| { 2460, 3, 1, 4, 620, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #2460 = SLL_D |
| { 2461, 3, 1, 4, 620, 0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #2461 = SLL_H |
| { 2462, 3, 1, 4, 752, 0, 0x1ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #2462 = SLL_MM |
| { 2463, 3, 1, 4, 790, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #2463 = SLL_MMR6 |
| { 2464, 3, 1, 4, 620, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #2464 = SLL_W |
| { 2465, 3, 1, 4, 499, 0, 0x1ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #2465 = SLT |
| { 2466, 3, 1, 4, 805, 0, 0x1ULL, nullptr, nullptr, OperandInfo349, -1 ,nullptr }, // Inst #2466 = SLT64 |
| { 2467, 3, 1, 4, 754, 0, 0x1ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #2467 = SLT_MM |
| { 2468, 3, 1, 4, 363, 0, 0x2ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #2468 = SLTi |
| { 2469, 3, 1, 4, 806, 0, 0x2ULL, nullptr, nullptr, OperandInfo350, -1 ,nullptr }, // Inst #2469 = SLTi64 |
| { 2470, 3, 1, 4, 755, 0, 0x2ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #2470 = SLTi_MM |
| { 2471, 3, 1, 4, 363, 0, 0x2ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #2471 = SLTiu |
| { 2472, 3, 1, 4, 806, 0, 0x2ULL, nullptr, nullptr, OperandInfo350, -1 ,nullptr }, // Inst #2472 = SLTiu64 |
| { 2473, 3, 1, 4, 755, 0, 0x2ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #2473 = SLTiu_MM |
| { 2474, 3, 1, 4, 499, 0, 0x1ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #2474 = SLTu |
| { 2475, 3, 1, 4, 805, 0, 0x1ULL, nullptr, nullptr, OperandInfo349, -1 ,nullptr }, // Inst #2475 = SLTu64 |
| { 2476, 3, 1, 4, 754, 0, 0x1ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #2476 = SLTu_MM |
| { 2477, 3, 1, 4, 1198, 0, 0x1ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #2477 = SNE |
| { 2478, 3, 1, 4, 1199, 0, 0x2ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #2478 = SNEi |
| { 2479, 3, 1, 4, 540, 0, 0x6ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr }, // Inst #2479 = SPLATI_B |
| { 2480, 3, 1, 4, 540, 0, 0x6ULL, nullptr, nullptr, OperandInfo167, -1 ,nullptr }, // Inst #2480 = SPLATI_D |
| { 2481, 3, 1, 4, 540, 0, 0x6ULL, nullptr, nullptr, OperandInfo168, -1 ,nullptr }, // Inst #2481 = SPLATI_H |
| { 2482, 3, 1, 4, 540, 0, 0x6ULL, nullptr, nullptr, OperandInfo169, -1 ,nullptr }, // Inst #2482 = SPLATI_W |
| { 2483, 3, 1, 4, 540, 0, 0x6ULL, nullptr, nullptr, OperandInfo351, -1 ,nullptr }, // Inst #2483 = SPLAT_B |
| { 2484, 3, 1, 4, 540, 0, 0x6ULL, nullptr, nullptr, OperandInfo352, -1 ,nullptr }, // Inst #2484 = SPLAT_D |
| { 2485, 3, 1, 4, 540, 0, 0x6ULL, nullptr, nullptr, OperandInfo353, -1 ,nullptr }, // Inst #2485 = SPLAT_H |
| { 2486, 3, 1, 4, 540, 0, 0x6ULL, nullptr, nullptr, OperandInfo354, -1 ,nullptr }, // Inst #2486 = SPLAT_W |
| { 2487, 3, 1, 4, 501, 0, 0x1ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #2487 = SRA |
| { 2488, 3, 1, 4, 616, 0, 0x6ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr }, // Inst #2488 = SRAI_B |
| { 2489, 3, 1, 4, 616, 0, 0x6ULL, nullptr, nullptr, OperandInfo167, -1 ,nullptr }, // Inst #2489 = SRAI_D |
| { 2490, 3, 1, 4, 616, 0, 0x6ULL, nullptr, nullptr, OperandInfo168, -1 ,nullptr }, // Inst #2490 = SRAI_H |
| { 2491, 3, 1, 4, 616, 0, 0x6ULL, nullptr, nullptr, OperandInfo169, -1 ,nullptr }, // Inst #2491 = SRAI_W |
| { 2492, 3, 1, 4, 618, 0, 0x6ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr }, // Inst #2492 = SRARI_B |
| { 2493, 3, 1, 4, 618, 0, 0x6ULL, nullptr, nullptr, OperandInfo167, -1 ,nullptr }, // Inst #2493 = SRARI_D |
| { 2494, 3, 1, 4, 618, 0, 0x6ULL, nullptr, nullptr, OperandInfo168, -1 ,nullptr }, // Inst #2494 = SRARI_H |
| { 2495, 3, 1, 4, 618, 0, 0x6ULL, nullptr, nullptr, OperandInfo169, -1 ,nullptr }, // Inst #2495 = SRARI_W |
| { 2496, 3, 1, 4, 618, 0, 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #2496 = SRAR_B |
| { 2497, 3, 1, 4, 618, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #2497 = SRAR_D |
| { 2498, 3, 1, 4, 618, 0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #2498 = SRAR_H |
| { 2499, 3, 1, 4, 618, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #2499 = SRAR_W |
| { 2500, 3, 1, 4, 506, 0, 0x1ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #2500 = SRAV |
| { 2501, 3, 1, 4, 756, 0, 0x1ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #2501 = SRAV_MM |
| { 2502, 3, 1, 4, 616, 0, 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #2502 = SRA_B |
| { 2503, 3, 1, 4, 616, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #2503 = SRA_D |
| { 2504, 3, 1, 4, 616, 0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #2504 = SRA_H |
| { 2505, 3, 1, 4, 757, 0, 0x1ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #2505 = SRA_MM |
| { 2506, 3, 1, 4, 616, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #2506 = SRA_W |
| { 2507, 3, 1, 4, 502, 0, 0x1ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #2507 = SRL |
| { 2508, 3, 1, 2, 758, 0, 0x0ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr }, // Inst #2508 = SRL16_MM |
| { 2509, 3, 1, 2, 791, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr }, // Inst #2509 = SRL16_MMR6 |
| { 2510, 3, 1, 4, 617, 0, 0x6ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr }, // Inst #2510 = SRLI_B |
| { 2511, 3, 1, 4, 617, 0, 0x6ULL, nullptr, nullptr, OperandInfo167, -1 ,nullptr }, // Inst #2511 = SRLI_D |
| { 2512, 3, 1, 4, 617, 0, 0x6ULL, nullptr, nullptr, OperandInfo168, -1 ,nullptr }, // Inst #2512 = SRLI_H |
| { 2513, 3, 1, 4, 617, 0, 0x6ULL, nullptr, nullptr, OperandInfo169, -1 ,nullptr }, // Inst #2513 = SRLI_W |
| { 2514, 3, 1, 4, 619, 0, 0x6ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr }, // Inst #2514 = SRLRI_B |
| { 2515, 3, 1, 4, 619, 0, 0x6ULL, nullptr, nullptr, OperandInfo167, -1 ,nullptr }, // Inst #2515 = SRLRI_D |
| { 2516, 3, 1, 4, 619, 0, 0x6ULL, nullptr, nullptr, OperandInfo168, -1 ,nullptr }, // Inst #2516 = SRLRI_H |
| { 2517, 3, 1, 4, 619, 0, 0x6ULL, nullptr, nullptr, OperandInfo169, -1 ,nullptr }, // Inst #2517 = SRLRI_W |
| { 2518, 3, 1, 4, 619, 0, 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #2518 = SRLR_B |
| { 2519, 3, 1, 4, 619, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #2519 = SRLR_D |
| { 2520, 3, 1, 4, 619, 0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #2520 = SRLR_H |
| { 2521, 3, 1, 4, 619, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #2521 = SRLR_W |
| { 2522, 3, 1, 4, 507, 0, 0x1ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #2522 = SRLV |
| { 2523, 3, 1, 4, 759, 0, 0x1ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #2523 = SRLV_MM |
| { 2524, 3, 1, 4, 617, 0, 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #2524 = SRL_B |
| { 2525, 3, 1, 4, 617, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #2525 = SRL_D |
| { 2526, 3, 1, 4, 617, 0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #2526 = SRL_H |
| { 2527, 3, 1, 4, 758, 0, 0x1ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #2527 = SRL_MM |
| { 2528, 3, 1, 4, 617, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #2528 = SRL_W |
| { 2529, 0, 0, 4, 367, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2529 = SSNOP |
| { 2530, 0, 0, 4, 760, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2530 = SSNOP_MM |
| { 2531, 0, 0, 4, 792, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2531 = SSNOP_MMR6 |
| { 2532, 3, 0, 4, 696, 0|(1ULL<<MCID::MayStore), 0x6ULL, nullptr, nullptr, OperandInfo277, -1 ,nullptr }, // Inst #2532 = ST_B |
| { 2533, 3, 0, 4, 696, 0|(1ULL<<MCID::MayStore), 0x6ULL, nullptr, nullptr, OperandInfo278, -1 ,nullptr }, // Inst #2533 = ST_D |
| { 2534, 3, 0, 4, 696, 0|(1ULL<<MCID::MayStore), 0x6ULL, nullptr, nullptr, OperandInfo279, -1 ,nullptr }, // Inst #2534 = ST_H |
| { 2535, 3, 0, 4, 696, 0|(1ULL<<MCID::MayStore), 0x6ULL, nullptr, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #2535 = ST_W |
| { 2536, 3, 1, 4, 364, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #2536 = SUB |
| { 2537, 3, 1, 4, 1487, 0, 0x6ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #2537 = SUBQH_PH |
| { 2538, 3, 1, 4, 1651, 0, 0x6ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #2538 = SUBQH_PH_MMR2 |
| { 2539, 3, 1, 4, 1488, 0, 0x6ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #2539 = SUBQH_R_PH |
| { 2540, 3, 1, 4, 1652, 0, 0x6ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #2540 = SUBQH_R_PH_MMR2 |
| { 2541, 3, 1, 4, 1490, 0, 0x6ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #2541 = SUBQH_R_W |
| { 2542, 3, 1, 4, 1654, 0, 0x6ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #2542 = SUBQH_R_W_MMR2 |
| { 2543, 3, 1, 4, 1489, 0, 0x6ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #2543 = SUBQH_W |
| { 2544, 3, 1, 4, 1653, 0, 0x6ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #2544 = SUBQH_W_MMR2 |
| { 2545, 3, 1, 4, 1441, 0, 0x6ULL, nullptr, ImplicitList8, OperandInfo163, -1 ,nullptr }, // Inst #2545 = SUBQ_PH |
| { 2546, 3, 1, 4, 1607, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo163, -1 ,nullptr }, // Inst #2546 = SUBQ_PH_MM |
| { 2547, 3, 1, 4, 1442, 0, 0x6ULL, nullptr, ImplicitList8, OperandInfo163, -1 ,nullptr }, // Inst #2547 = SUBQ_S_PH |
| { 2548, 3, 1, 4, 1608, 0, 0x6ULL, nullptr, ImplicitList8, OperandInfo163, -1 ,nullptr }, // Inst #2548 = SUBQ_S_PH_MM |
| { 2549, 3, 1, 4, 1443, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo65, -1 ,nullptr }, // Inst #2549 = SUBQ_S_W |
| { 2550, 3, 1, 4, 1609, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo65, -1 ,nullptr }, // Inst #2550 = SUBQ_S_W_MM |
| { 2551, 3, 1, 4, 604, 0, 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #2551 = SUBSUS_U_B |
| { 2552, 3, 1, 4, 604, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #2552 = SUBSUS_U_D |
| { 2553, 3, 1, 4, 604, 0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #2553 = SUBSUS_U_H |
| { 2554, 3, 1, 4, 604, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #2554 = SUBSUS_U_W |
| { 2555, 3, 1, 4, 605, 0, 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #2555 = SUBSUU_S_B |
| { 2556, 3, 1, 4, 605, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #2556 = SUBSUU_S_D |
| { 2557, 3, 1, 4, 605, 0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #2557 = SUBSUU_S_H |
| { 2558, 3, 1, 4, 605, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #2558 = SUBSUU_S_W |
| { 2559, 3, 1, 4, 603, 0, 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #2559 = SUBS_S_B |
| { 2560, 3, 1, 4, 603, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #2560 = SUBS_S_D |
| { 2561, 3, 1, 4, 603, 0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #2561 = SUBS_S_H |
| { 2562, 3, 1, 4, 603, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #2562 = SUBS_S_W |
| { 2563, 3, 1, 4, 603, 0, 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #2563 = SUBS_U_B |
| { 2564, 3, 1, 4, 603, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #2564 = SUBS_U_D |
| { 2565, 3, 1, 4, 603, 0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #2565 = SUBS_U_H |
| { 2566, 3, 1, 4, 603, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #2566 = SUBS_U_W |
| { 2567, 3, 1, 2, 761, 0, 0x0ULL, nullptr, nullptr, OperandInfo165, -1 ,nullptr }, // Inst #2567 = SUBU16_MM |
| { 2568, 3, 1, 2, 793, 0, 0x0ULL, nullptr, nullptr, OperandInfo165, -1 ,nullptr }, // Inst #2568 = SUBU16_MMR6 |
| { 2569, 3, 1, 4, 1493, 0, 0x6ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #2569 = SUBUH_QB |
| { 2570, 3, 1, 4, 1657, 0, 0x6ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #2570 = SUBUH_QB_MMR2 |
| { 2571, 3, 1, 4, 1494, 0, 0x6ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #2571 = SUBUH_R_QB |
| { 2572, 3, 1, 4, 1658, 0, 0x6ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr }, // Inst #2572 = SUBUH_R_QB_MMR2 |
| { 2573, 3, 1, 4, 793, 0|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #2573 = SUBU_MMR6 |
| { 2574, 3, 1, 4, 1491, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo163, -1 ,nullptr }, // Inst #2574 = SUBU_PH |
| { 2575, 3, 1, 4, 1655, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo163, -1 ,nullptr }, // Inst #2575 = SUBU_PH_MMR2 |
| { 2576, 3, 1, 4, 1444, 0, 0x6ULL, nullptr, ImplicitList8, OperandInfo163, -1 ,nullptr }, // Inst #2576 = SUBU_QB |
| { 2577, 3, 1, 4, 1610, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo163, -1 ,nullptr }, // Inst #2577 = SUBU_QB_MM |
| { 2578, 3, 1, 4, 1492, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo163, -1 ,nullptr }, // Inst #2578 = SUBU_S_PH |
| { 2579, 3, 1, 4, 1656, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, ImplicitList8, OperandInfo163, -1 ,nullptr }, // Inst #2579 = SUBU_S_PH_MMR2 |
| { 2580, 3, 1, 4, 1445, 0, 0x6ULL, nullptr, ImplicitList8, OperandInfo163, -1 ,nullptr }, // Inst #2580 = SUBU_S_QB |
| { 2581, 3, 1, 4, 1611, 0, 0x6ULL, nullptr, ImplicitList8, OperandInfo163, -1 ,nullptr }, // Inst #2581 = SUBU_S_QB_MM |
| { 2582, 3, 1, 4, 606, 0, 0x6ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr }, // Inst #2582 = SUBVI_B |
| { 2583, 3, 1, 4, 606, 0, 0x6ULL, nullptr, nullptr, OperandInfo167, -1 ,nullptr }, // Inst #2583 = SUBVI_D |
| { 2584, 3, 1, 4, 606, 0, 0x6ULL, nullptr, nullptr, OperandInfo168, -1 ,nullptr }, // Inst #2584 = SUBVI_H |
| { 2585, 3, 1, 4, 606, 0, 0x6ULL, nullptr, nullptr, OperandInfo169, -1 ,nullptr }, // Inst #2585 = SUBVI_W |
| { 2586, 3, 1, 4, 607, 0, 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #2586 = SUBV_B |
| { 2587, 3, 1, 4, 607, 0, 0x6ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr }, // Inst #2587 = SUBV_D |
| { 2588, 3, 1, 4, 607, 0, 0x6ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr }, // Inst #2588 = SUBV_H |
| { 2589, 3, 1, 4, 607, 0, 0x6ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr }, // Inst #2589 = SUBV_W |
| { 2590, 3, 1, 4, 762, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #2590 = SUB_MM |
| { 2591, 3, 1, 4, 794, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #2591 = SUB_MMR6 |
| { 2592, 3, 1, 4, 365, 0|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #2592 = SUBu |
| { 2593, 3, 1, 4, 761, 0|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #2593 = SUBu_MM |
| { 2594, 3, 0, 4, 695, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, nullptr, nullptr, OperandInfo275, -1 ,nullptr }, // Inst #2594 = SUXC1 |
| { 2595, 3, 0, 4, 695, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, nullptr, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #2595 = SUXC164 |
| { 2596, 3, 0, 4, 1281, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL, nullptr, nullptr, OperandInfo276, -1 ,nullptr }, // Inst #2596 = SUXC1_MM |
| { 2597, 3, 0, 4, 449, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #2597 = SW |
| { 2598, 3, 0, 2, 1125, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #2598 = SW16_MM |
| { 2599, 3, 0, 2, 1148, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo336, -1 ,nullptr }, // Inst #2599 = SW16_MMR6 |
| { 2600, 3, 0, 4, 1171, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo104, -1 ,nullptr }, // Inst #2600 = SW64 |
| { 2601, 3, 0, 4, 693, 0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #2601 = SWC1 |
| { 2602, 3, 0, 4, 1280, 0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, nullptr, OperandInfo283, -1 ,nullptr }, // Inst #2602 = SWC1_MM |
| { 2603, 3, 0, 4, 450, 0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, nullptr, OperandInfo267, -1 ,nullptr }, // Inst #2603 = SWC2 |
| { 2604, 3, 0, 4, 1149, 0|(1ULL<<MCID::MayStore), 0x6ULL, nullptr, nullptr, OperandInfo268, -1 ,nullptr }, // Inst #2604 = SWC2_MMR6 |
| { 2605, 3, 0, 4, 1076, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo267, -1 ,nullptr }, // Inst #2605 = SWC2_R6 |
| { 2606, 3, 0, 4, 451, 0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, nullptr, OperandInfo269, -1 ,nullptr }, // Inst #2606 = SWC3 |
| { 2607, 3, 0, 4, 1331, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #2607 = SWDSP |
| { 2608, 3, 0, 4, 1496, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo284, -1 ,nullptr }, // Inst #2608 = SWDSP_MM |
| { 2609, 3, 0, 4, 457, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #2609 = SWE |
| { 2610, 3, 0, 4, 1094, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #2610 = SWE_MM |
| { 2611, 3, 0, 4, 459, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #2611 = SWL |
| { 2612, 3, 0, 4, 1172, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo104, -1 ,nullptr }, // Inst #2612 = SWL64 |
| { 2613, 3, 0, 4, 461, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #2613 = SWLE |
| { 2614, 3, 0, 4, 1095, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #2614 = SWLE_MM |
| { 2615, 3, 0, 4, 1126, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #2615 = SWL_MM |
| { 2616, 3, 0, 2, 1127, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #2616 = SWM16_MM |
| { 2617, 3, 0, 2, 1150, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo287, -1 ,nullptr }, // Inst #2617 = SWM16_MMR6 |
| { 2618, 3, 0, 4, 1127, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr }, // Inst #2618 = SWM32_MM |
| { 2619, 4, 0, 4, 1129, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo288, -1 ,nullptr }, // Inst #2619 = SWP_MM |
| { 2620, 3, 0, 4, 460, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #2620 = SWR |
| { 2621, 3, 0, 4, 1173, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo104, -1 ,nullptr }, // Inst #2621 = SWR64 |
| { 2622, 3, 0, 4, 462, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #2622 = SWRE |
| { 2623, 3, 0, 4, 1096, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #2623 = SWRE_MM |
| { 2624, 3, 0, 4, 1130, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #2624 = SWR_MM |
| { 2625, 3, 0, 2, 1125, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo289, -1 ,nullptr }, // Inst #2625 = SWSP_MM |
| { 2626, 3, 0, 2, 1148, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo289, -1 ,nullptr }, // Inst #2626 = SWSP_MMR6 |
| { 2627, 3, 0, 4, 694, 0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, nullptr, OperandInfo290, -1 ,nullptr }, // Inst #2627 = SWXC1 |
| { 2628, 3, 0, 4, 1282, 0|(1ULL<<MCID::MayStore), 0x5ULL, nullptr, nullptr, OperandInfo290, -1 ,nullptr }, // Inst #2628 = SWXC1_MM |
| { 2629, 3, 0, 4, 1125, 0|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #2629 = SW_MM |
| { 2630, 3, 0, 4, 1148, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #2630 = SW_MMR6 |
| { 2631, 1, 0, 4, 467, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #2631 = SYNC |
| { 2632, 2, 0, 4, 468, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo355, -1 ,nullptr }, // Inst #2632 = SYNCI |
| { 2633, 2, 0, 4, 1134, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo355, -1 ,nullptr }, // Inst #2633 = SYNCI_MM |
| { 2634, 2, 0, 4, 1152, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo355, -1 ,nullptr }, // Inst #2634 = SYNCI_MMR6 |
| { 2635, 1, 0, 4, 1133, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #2635 = SYNC_MM |
| { 2636, 1, 0, 4, 1151, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #2636 = SYNC_MMR6 |
| { 2637, 1, 0, 4, 385, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #2637 = SYSCALL |
| { 2638, 1, 0, 4, 960, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #2638 = SYSCALL_MM |
| { 2639, 0, 0, 2, 1106, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, ImplicitList1, nullptr, -1 ,nullptr }, // Inst #2639 = Save16 |
| { 2640, 0, 0, 2, 1106, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, ImplicitList1, nullptr, -1 ,nullptr }, // Inst #2640 = SaveX16 |
| { 2641, 3, 0, 4, 1107, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #2641 = SbRxRyOffMemX16 |
| { 2642, 2, 1, 2, 727, 0, 0x0ULL, nullptr, nullptr, OperandInfo356, -1 ,nullptr }, // Inst #2642 = SebRx16 |
| { 2643, 2, 1, 2, 727, 0, 0x0ULL, nullptr, nullptr, OperandInfo356, -1 ,nullptr }, // Inst #2643 = SehRx16 |
| { 2644, 3, 0, 4, 1108, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #2644 = ShRxRyOffMemX16 |
| { 2645, 3, 1, 4, 727, 0, 0x0ULL, nullptr, nullptr, OperandInfo158, -1 ,nullptr }, // Inst #2645 = SllX16 |
| { 2646, 3, 1, 2, 727, 0, 0x0ULL, nullptr, nullptr, OperandInfo176, -1 ,nullptr }, // Inst #2646 = SllvRxRy16 |
| { 2647, 2, 0, 2, 727, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList7, OperandInfo121, -1 ,nullptr }, // Inst #2647 = SltRxRy16 |
| { 2648, 2, 0, 2, 727, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList7, OperandInfo173, -1 ,nullptr }, // Inst #2648 = SltiRxImm16 |
| { 2649, 2, 0, 4, 727, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList7, OperandInfo173, -1 ,nullptr }, // Inst #2649 = SltiRxImmX16 |
| { 2650, 2, 0, 2, 727, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList7, OperandInfo173, -1 ,nullptr }, // Inst #2650 = SltiuRxImm16 |
| { 2651, 2, 0, 4, 727, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList7, OperandInfo173, -1 ,nullptr }, // Inst #2651 = SltiuRxImmX16 |
| { 2652, 2, 0, 2, 727, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList7, OperandInfo121, -1 ,nullptr }, // Inst #2652 = SltuRxRy16 |
| { 2653, 3, 1, 4, 727, 0, 0x0ULL, nullptr, nullptr, OperandInfo158, -1 ,nullptr }, // Inst #2653 = SraX16 |
| { 2654, 3, 1, 2, 727, 0, 0x0ULL, nullptr, nullptr, OperandInfo176, -1 ,nullptr }, // Inst #2654 = SravRxRy16 |
| { 2655, 3, 1, 4, 727, 0, 0x0ULL, nullptr, nullptr, OperandInfo158, -1 ,nullptr }, // Inst #2655 = SrlX16 |
| { 2656, 3, 1, 2, 727, 0, 0x0ULL, nullptr, nullptr, OperandInfo176, -1 ,nullptr }, // Inst #2656 = SrlvRxRy16 |
| { 2657, 3, 1, 2, 727, 0|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo122, -1 ,nullptr }, // Inst #2657 = SubuRxRyRz16 |
| { 2658, 3, 0, 4, 1109, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo291, -1 ,nullptr }, // Inst #2658 = SwRxRyOffMemX16 |
| { 2659, 3, 0, 4, 1109, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo175, -1 ,nullptr }, // Inst #2659 = SwRxSpImmX16 |
| { 2660, 3, 0, 4, 386, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #2660 = TEQ |
| { 2661, 2, 0, 4, 387, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #2661 = TEQI |
| { 2662, 2, 0, 4, 961, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #2662 = TEQI_MM |
| { 2663, 3, 0, 4, 962, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #2663 = TEQ_MM |
| { 2664, 3, 0, 4, 388, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #2664 = TGE |
| { 2665, 2, 0, 4, 389, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #2665 = TGEI |
| { 2666, 2, 0, 4, 390, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #2666 = TGEIU |
| { 2667, 2, 0, 4, 963, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #2667 = TGEIU_MM |
| { 2668, 2, 0, 4, 964, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #2668 = TGEI_MM |
| { 2669, 3, 0, 4, 391, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #2669 = TGEU |
| { 2670, 3, 0, 4, 965, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #2670 = TGEU_MM |
| { 2671, 3, 0, 4, 966, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #2671 = TGE_MM |
| { 2672, 0, 0, 4, 420, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2672 = TLBGINV |
| { 2673, 0, 0, 4, 421, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2673 = TLBGINVF |
| { 2674, 0, 0, 4, 1062, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2674 = TLBGINVF_MM |
| { 2675, 0, 0, 4, 1063, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2675 = TLBGINV_MM |
| { 2676, 0, 0, 4, 422, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2676 = TLBGP |
| { 2677, 0, 0, 4, 1064, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2677 = TLBGP_MM |
| { 2678, 0, 0, 4, 423, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2678 = TLBGR |
| { 2679, 0, 0, 4, 1065, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2679 = TLBGR_MM |
| { 2680, 0, 0, 4, 424, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2680 = TLBGWI |
| { 2681, 0, 0, 4, 1066, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2681 = TLBGWI_MM |
| { 2682, 0, 0, 4, 425, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2682 = TLBGWR |
| { 2683, 0, 0, 4, 1067, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2683 = TLBGWR_MM |
| { 2684, 0, 0, 4, 405, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2684 = TLBINV |
| { 2685, 0, 0, 4, 406, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2685 = TLBINVF |
| { 2686, 0, 0, 4, 1031, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2686 = TLBINVF_MMR6 |
| { 2687, 0, 0, 4, 1030, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2687 = TLBINV_MMR6 |
| { 2688, 0, 0, 4, 407, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2688 = TLBP |
| { 2689, 0, 0, 4, 1019, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2689 = TLBP_MM |
| { 2690, 0, 0, 4, 408, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2690 = TLBR |
| { 2691, 0, 0, 4, 1020, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2691 = TLBR_MM |
| { 2692, 0, 0, 4, 409, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2692 = TLBWI |
| { 2693, 0, 0, 4, 1021, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2693 = TLBWI_MM |
| { 2694, 0, 0, 4, 410, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2694 = TLBWR |
| { 2695, 0, 0, 4, 1022, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2695 = TLBWR_MM |
| { 2696, 3, 0, 4, 392, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #2696 = TLT |
| { 2697, 2, 0, 4, 393, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #2697 = TLTI |
| { 2698, 2, 0, 4, 967, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #2698 = TLTIU_MM |
| { 2699, 2, 0, 4, 968, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #2699 = TLTI_MM |
| { 2700, 3, 0, 4, 394, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #2700 = TLTU |
| { 2701, 3, 0, 4, 969, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #2701 = TLTU_MM |
| { 2702, 3, 0, 4, 970, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #2702 = TLT_MM |
| { 2703, 3, 0, 4, 395, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #2703 = TNE |
| { 2704, 2, 0, 4, 396, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #2704 = TNEI |
| { 2705, 2, 0, 4, 971, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #2705 = TNEI_MM |
| { 2706, 3, 0, 4, 972, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #2706 = TNE_MM |
| { 2707, 2, 1, 4, 629, 0, 0x4ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #2707 = TRUNC_L_D64 |
| { 2708, 2, 1, 4, 1297, 0, 0x4ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr }, // Inst #2708 = TRUNC_L_D_MMR6 |
| { 2709, 2, 1, 4, 629, 0, 0x4ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr }, // Inst #2709 = TRUNC_L_S |
| { 2710, 2, 1, 4, 1297, 0, 0x4ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr }, // Inst #2710 = TRUNC_L_S_MMR6 |
| { 2711, 2, 1, 4, 629, 0, 0x4ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #2711 = TRUNC_W_D32 |
| { 2712, 2, 1, 4, 629, 0, 0x4ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr }, // Inst #2712 = TRUNC_W_D64 |
| { 2713, 2, 1, 4, 1297, 0, 0x4ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr }, // Inst #2713 = TRUNC_W_D_MMR6 |
| { 2714, 2, 1, 4, 1245, 0, 0x4ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr }, // Inst #2714 = TRUNC_W_MM |
| { 2715, 2, 1, 4, 629, 0, 0x4ULL, nullptr, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #2715 = TRUNC_W_S |
| { 2716, 2, 1, 4, 1245, 0, 0x4ULL, nullptr, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #2716 = TRUNC_W_S_MM |
| { 2717, 2, 1, 4, 1297, 0, 0x4ULL, nullptr, nullptr, OperandInfo197, -1 ,nullptr }, // Inst #2717 = TRUNC_W_S_MMR6 |
| { 2718, 2, 0, 4, 398, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #2718 = TTLTIU |
| { 2719, 2, 0, 4, 858, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, ImplicitList6, OperandInfo38, -1 ,nullptr }, // Inst #2719 = UDIV |
| { 2720, 2, 0, 4, 878, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, ImplicitList6, OperandInfo38, -1 ,nullptr }, // Inst #2720 = UDIV_MM |
| { 2721, 3, 1, 4, 1200, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, ImplicitList33, OperandInfo64, -1 ,nullptr }, // Inst #2721 = V3MULU |
| { 2722, 3, 1, 4, 1200, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, ImplicitList25, OperandInfo64, -1 ,nullptr }, // Inst #2722 = VMM0 |
| { 2723, 3, 1, 4, 1200, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, ImplicitList34, OperandInfo64, -1 ,nullptr }, // Inst #2723 = VMULU |
| { 2724, 4, 1, 4, 510, 0, 0x6ULL, nullptr, nullptr, OperandInfo186, -1 ,nullptr }, // Inst #2724 = VSHF_B |
| { 2725, 4, 1, 4, 510, 0, 0x6ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #2725 = VSHF_D |
| { 2726, 4, 1, 4, 510, 0, 0x6ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #2726 = VSHF_H |
| { 2727, 4, 1, 4, 510, 0, 0x6ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #2727 = VSHF_W |
| { 2728, 0, 0, 4, 399, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, nullptr, -1 ,nullptr }, // Inst #2728 = WAIT |
| { 2729, 1, 0, 4, 1027, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #2729 = WAIT_MM |
| { 2730, 1, 0, 4, 1044, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr }, // Inst #2730 = WAIT_MMR6 |
| { 2731, 2, 0, 4, 1446, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #2731 = WRDSP |
| { 2732, 2, 0, 4, 1612, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr }, // Inst #2732 = WRDSP_MM |
| { 2733, 2, 1, 4, 1029, 0, 0x6ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #2733 = WRPGPR_MMR6 |
| { 2734, 2, 1, 4, 476, 0, 0x1ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #2734 = WSBH |
| { 2735, 2, 1, 4, 763, 0, 0x1ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #2735 = WSBH_MM |
| { 2736, 2, 1, 4, 795, 0, 0x6ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #2736 = WSBH_MMR6 |
| { 2737, 3, 1, 4, 366, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #2737 = XOR |
| { 2738, 3, 1, 2, 764, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #2738 = XOR16_MM |
| { 2739, 3, 1, 2, 796, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #2739 = XOR16_MMR6 |
| { 2740, 3, 1, 4, 807, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr }, // Inst #2740 = XOR64 |
| { 2741, 3, 1, 4, 544, 0, 0x6ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr }, // Inst #2741 = XORI_B |
| { 2742, 3, 1, 4, 797, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #2742 = XORI_MMR6 |
| { 2743, 3, 1, 4, 764, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #2743 = XOR_MM |
| { 2744, 3, 1, 4, 796, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #2744 = XOR_MMR6 |
| { 2745, 3, 1, 4, 543, 0, 0x6ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr }, // Inst #2745 = XOR_V |
| { 2746, 3, 1, 4, 503, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #2746 = XORi |
| { 2747, 3, 1, 4, 807, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #2747 = XORi64 |
| { 2748, 3, 1, 4, 765, 0|(1ULL<<MCID::Rematerializable), 0x2ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr }, // Inst #2748 = XORi_MM |
| { 2749, 3, 1, 2, 727, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo176, -1 ,nullptr }, // Inst #2749 = XorRxRxRy16 |
| { 2750, 2, 1, 4, 1057, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr }, // Inst #2750 = YIELD |
| }; |
| |
| extern const char MipsInstrNameData[] = { |
| /* 0 */ 'G', '_', 'F', 'L', 'O', 'G', '1', '0', 0, |
| /* 9 */ 'D', 'M', 'F', 'C', '0', 0, |
| /* 15 */ 'D', 'M', 'F', 'G', 'C', '0', 0, |
| /* 22 */ 'M', 'F', 'H', 'G', 'C', '0', 0, |
| /* 29 */ 'M', 'T', 'H', 'G', 'C', '0', 0, |
| /* 36 */ 'D', 'M', 'T', 'G', 'C', '0', 0, |
| /* 43 */ 'M', 'F', 'T', 'C', '0', 0, |
| /* 49 */ 'D', 'M', 'T', 'C', '0', 0, |
| /* 55 */ 'M', 'T', 'T', 'C', '0', 0, |
| /* 61 */ 'V', 'M', 'M', '0', 0, |
| /* 66 */ 'M', 'T', 'M', '0', 0, |
| /* 71 */ 'M', 'T', 'P', '0', 0, |
| /* 76 */ 'B', 'B', 'I', 'T', '0', 0, |
| /* 82 */ 'L', 'D', 'C', '1', 0, |
| /* 87 */ 'S', 'D', 'C', '1', 0, |
| /* 92 */ 'C', 'F', 'C', '1', 0, |
| /* 97 */ 'D', 'M', 'F', 'C', '1', 0, |
| /* 103 */ 'M', 'F', 'T', 'H', 'C', '1', 0, |
| /* 110 */ 'M', 'T', 'T', 'H', 'C', '1', 0, |
| /* 117 */ 'C', 'T', 'C', '1', 0, |
| /* 122 */ 'C', 'F', 'T', 'C', '1', 0, |
| /* 128 */ 'M', 'F', 'T', 'C', '1', 0, |
| /* 134 */ 'D', 'M', 'T', 'C', '1', 0, |
| /* 140 */ 'C', 'T', 'T', 'C', '1', 0, |
| /* 146 */ 'M', 'T', 'T', 'C', '1', 0, |
| /* 152 */ 'L', 'W', 'C', '1', 0, |
| /* 157 */ 'S', 'W', 'C', '1', 0, |
| /* 162 */ 'L', 'D', 'X', 'C', '1', 0, |
| /* 168 */ 'S', 'D', 'X', 'C', '1', 0, |
| /* 174 */ 'L', 'U', 'X', 'C', '1', 0, |
| /* 180 */ 'S', 'U', 'X', 'C', '1', 0, |
| /* 186 */ 'L', 'W', 'X', 'C', '1', 0, |
| /* 192 */ 'S', 'W', 'X', 'C', '1', 0, |
| /* 198 */ 'M', 'T', 'M', '1', 0, |
| /* 203 */ 'S', 'D', 'C', '1', '_', 'M', '1', 0, |
| /* 211 */ 'M', 'T', 'P', '1', 0, |
| /* 216 */ 'B', 'B', 'I', 'T', '1', 0, |
| /* 222 */ 'B', 'B', 'I', 'T', '0', '3', '2', 0, |
| /* 230 */ 'B', 'B', 'I', 'T', '1', '3', '2', 0, |
| /* 238 */ 'D', 'S', 'R', 'A', '3', '2', 0, |
| /* 245 */ 'M', 'F', 'H', 'C', '1', '_', 'D', '3', '2', 0, |
| /* 255 */ 'M', 'T', 'H', 'C', '1', '_', 'D', '3', '2', 0, |
| /* 265 */ 'F', 'S', 'U', 'B', '_', 'D', '3', '2', 0, |
| /* 274 */ 'N', 'M', 'S', 'U', 'B', '_', 'D', '3', '2', 0, |
| /* 284 */ 'F', 'A', 'D', 'D', '_', 'D', '3', '2', 0, |
| /* 293 */ 'N', 'M', 'A', 'D', 'D', '_', 'D', '3', '2', 0, |
| /* 303 */ 'C', '_', 'N', 'G', 'E', '_', 'D', '3', '2', 0, |
| /* 313 */ 'C', '_', 'N', 'G', 'L', 'E', '_', 'D', '3', '2', 0, |
| /* 324 */ 'C', '_', 'O', 'L', 'E', '_', 'D', '3', '2', 0, |
| /* 334 */ 'C', '_', 'U', 'L', 'E', '_', 'D', '3', '2', 0, |
| /* 344 */ 'C', '_', 'L', 'E', '_', 'D', '3', '2', 0, |
| /* 353 */ 'C', '_', 'S', 'F', '_', 'D', '3', '2', 0, |
| /* 362 */ 'M', 'O', 'V', 'F', '_', 'D', '3', '2', 0, |
| /* 371 */ 'C', '_', 'F', '_', 'D', '3', '2', 0, |
| /* 379 */ 'P', 's', 'e', 'u', 'd', 'o', 'S', 'E', 'L', 'E', 'C', 'T', 'F', 'P', '_', 'F', '_', 'D', '3', '2', 0, |
| /* 400 */ 'F', 'N', 'E', 'G', '_', 'D', '3', '2', 0, |
| /* 409 */ 'M', 'O', 'V', 'N', '_', 'I', '_', 'D', '3', '2', 0, |
| /* 420 */ 'M', 'O', 'V', 'Z', '_', 'I', '_', 'D', '3', '2', 0, |
| /* 431 */ 'C', '_', 'N', 'G', 'L', '_', 'D', '3', '2', 0, |
| /* 441 */ 'F', 'M', 'U', 'L', '_', 'D', '3', '2', 0, |
| /* 450 */ 'C', '_', 'U', 'N', '_', 'D', '3', '2', 0, |
| /* 459 */ 'R', 'E', 'C', 'I', 'P', '_', 'D', '3', '2', 0, |
| /* 469 */ 'F', 'C', 'M', 'P', '_', 'D', '3', '2', 0, |
| /* 478 */ 'C', '_', 'S', 'E', 'Q', '_', 'D', '3', '2', 0, |
| /* 488 */ 'C', '_', 'U', 'E', 'Q', '_', 'D', '3', '2', 0, |
| /* 498 */ 'C', '_', 'E', 'Q', '_', 'D', '3', '2', 0, |
| /* 507 */ 'F', 'A', 'B', 'S', '_', 'D', '3', '2', 0, |
| /* 516 */ 'C', 'V', 'T', '_', 'S', '_', 'D', '3', '2', 0, |
| /* 526 */ 'P', 's', 'e', 'u', 'd', 'o', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'D', '3', '2', 0, |
| /* 543 */ 'C', '_', 'N', 'G', 'T', '_', 'D', '3', '2', 0, |
| /* 553 */ 'C', '_', 'O', 'L', 'T', '_', 'D', '3', '2', 0, |
| /* 563 */ 'C', '_', 'U', 'L', 'T', '_', 'D', '3', '2', 0, |
| /* 573 */ 'C', '_', 'L', 'T', '_', 'D', '3', '2', 0, |
| /* 582 */ 'F', 'S', 'Q', 'R', 'T', '_', 'D', '3', '2', 0, |
| /* 592 */ 'R', 'S', 'Q', 'R', 'T', '_', 'D', '3', '2', 0, |
| /* 602 */ 'M', 'O', 'V', 'T', '_', 'D', '3', '2', 0, |
| /* 611 */ 'P', 's', 'e', 'u', 'd', 'o', 'S', 'E', 'L', 'E', 'C', 'T', 'F', 'P', '_', 'T', '_', 'D', '3', '2', 0, |
| /* 632 */ 'F', 'D', 'I', 'V', '_', 'D', '3', '2', 0, |
| /* 641 */ 'F', 'M', 'O', 'V', '_', 'D', '3', '2', 0, |
| /* 650 */ 'P', 's', 'e', 'u', 'd', 'o', 'T', 'R', 'U', 'N', 'C', '_', 'W', '_', 'D', '3', '2', 0, |
| /* 668 */ 'R', 'O', 'U', 'N', 'D', '_', 'W', '_', 'D', '3', '2', 0, |
| /* 680 */ 'C', 'E', 'I', 'L', '_', 'W', '_', 'D', '3', '2', 0, |
| /* 691 */ 'F', 'L', 'O', 'O', 'R', '_', 'W', '_', 'D', '3', '2', 0, |
| /* 703 */ 'C', 'V', 'T', '_', 'W', '_', 'D', '3', '2', 0, |
| /* 713 */ 'B', 'P', 'O', 'S', 'G', 'E', '3', '2', 0, |
| /* 722 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'S', 'U', 'B', '_', 'I', '3', '2', 0, |
| /* 742 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'A', 'D', 'D', '_', 'I', '3', '2', 0, |
| /* 762 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'N', 'A', 'N', 'D', '_', 'I', '3', '2', 0, |
| /* 783 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'A', 'N', 'D', '_', 'I', '3', '2', 0, |
| /* 803 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'U', 'M', 'I', 'N', '_', 'I', '3', '2', 0, |
| /* 824 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'M', 'I', 'N', '_', 'I', '3', '2', 0, |
| /* 844 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'S', 'W', 'A', 'P', '_', 'I', '3', '2', 0, |
| /* 860 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'C', 'M', 'P', '_', 'S', 'W', 'A', 'P', '_', 'I', '3', '2', 0, |
| /* 880 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'X', 'O', 'R', '_', 'I', '3', '2', 0, |
| /* 900 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'O', 'R', '_', 'I', '3', '2', 0, |
| /* 919 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'U', 'M', 'A', 'X', '_', 'I', '3', '2', 0, |
| /* 940 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'M', 'A', 'X', '_', 'I', '3', '2', 0, |
| /* 960 */ 'D', 'S', 'L', 'L', '3', '2', 0, |
| /* 967 */ 'D', 'S', 'R', 'L', '3', '2', 0, |
| /* 974 */ 'D', 'R', 'O', 'T', 'R', '3', '2', 0, |
| /* 982 */ 'C', 'I', 'N', 'S', '3', '2', 0, |
| /* 989 */ 'E', 'X', 'T', 'S', '3', '2', 0, |
| /* 996 */ 'F', 'C', 'M', 'P', '_', 'S', '3', '2', 0, |
| /* 1005 */ 'D', 'S', 'L', 'L', '6', '4', '_', '3', '2', 0, |
| /* 1015 */ 'C', 'I', 'N', 'S', '6', '4', '_', '3', '2', 0, |
| /* 1025 */ 'D', 'E', 'X', 'T', '6', '4', '_', '3', '2', 0, |
| /* 1035 */ 'L', 'o', 'a', 'd', 'I', 'm', 'm', 'D', 'o', 'u', 'b', 'l', 'e', 'F', 'G', 'R', '_', '3', '2', 0, |
| /* 1055 */ 'L', 'o', 'a', 'd', 'A', 'd', 'd', 'r', 'R', 'e', 'g', '3', '2', 0, |
| /* 1069 */ 'C', 'I', 'N', 'S', '_', 'i', '3', '2', 0, |
| /* 1078 */ 'L', 'o', 'a', 'd', 'I', 'm', 'm', '3', '2', 0, |
| /* 1088 */ 'L', 'o', 'a', 'd', 'A', 'd', 'd', 'r', 'I', 'm', 'm', '3', '2', 0, |
| /* 1102 */ 'M', 'I', 'P', 'S', 'e', 'h', '_', 'r', 'e', 't', 'u', 'r', 'n', '3', '2', 0, |
| /* 1118 */ 'L', 'w', 'C', 'o', 'n', 's', 't', 'a', 'n', 't', '3', '2', 0, |
| /* 1131 */ 'L', 'D', 'C', '2', 0, |
| /* 1136 */ 'S', 'D', 'C', '2', 0, |
| /* 1141 */ 'D', 'M', 'F', 'C', '2', 0, |
| /* 1147 */ 'D', 'M', 'T', 'C', '2', 0, |
| /* 1153 */ 'L', 'W', 'C', '2', 0, |
| /* 1158 */ 'S', 'W', 'C', '2', 0, |
| /* 1163 */ 'G', '_', 'F', 'L', 'O', 'G', '2', 0, |
| /* 1171 */ 'M', 'T', 'M', '2', 0, |
| /* 1176 */ 'M', 'T', 'P', '2', 0, |
| /* 1181 */ 'G', '_', 'F', 'E', 'X', 'P', '2', 0, |
| /* 1189 */ 'S', 'H', 'R', 'A', '_', 'Q', 'B', '_', 'M', 'M', 'R', '2', 0, |
| /* 1202 */ 'C', 'M', 'P', 'G', 'D', 'U', '_', 'L', 'E', '_', 'Q', 'B', '_', 'M', 'M', 'R', '2', 0, |
| /* 1220 */ 'S', 'U', 'B', 'U', 'H', '_', 'Q', 'B', '_', 'M', 'M', 'R', '2', 0, |
| /* 1234 */ 'A', 'D', 'D', 'U', 'H', '_', 'Q', 'B', '_', 'M', 'M', 'R', '2', 0, |
| /* 1248 */ 'C', 'M', 'P', 'G', 'D', 'U', '_', 'E', 'Q', '_', 'Q', 'B', '_', 'M', 'M', 'R', '2', 0, |
| /* 1266 */ 'S', 'H', 'R', 'A', '_', 'R', '_', 'Q', 'B', '_', 'M', 'M', 'R', '2', 0, |
| /* 1281 */ 'S', 'U', 'B', 'U', 'H', '_', 'R', '_', 'Q', 'B', '_', 'M', 'M', 'R', '2', 0, |
| /* 1297 */ 'A', 'D', 'D', 'U', 'H', '_', 'R', '_', 'Q', 'B', '_', 'M', 'M', 'R', '2', 0, |
| /* 1313 */ 'S', 'H', 'R', 'A', 'V', '_', 'R', '_', 'Q', 'B', '_', 'M', 'M', 'R', '2', 0, |
| /* 1329 */ 'A', 'B', 'S', 'Q', '_', 'S', '_', 'Q', 'B', '_', 'M', 'M', 'R', '2', 0, |
| /* 1344 */ 'C', 'M', 'P', 'G', 'D', 'U', '_', 'L', 'T', '_', 'Q', 'B', '_', 'M', 'M', 'R', '2', 0, |
| /* 1362 */ 'S', 'H', 'R', 'A', 'V', '_', 'Q', 'B', '_', 'M', 'M', 'R', '2', 0, |
| /* 1376 */ 'P', 'R', 'E', 'P', 'E', 'N', 'D', '_', 'M', 'M', 'R', '2', 0, |
| /* 1389 */ 'A', 'P', 'P', 'E', 'N', 'D', '_', 'M', 'M', 'R', '2', 0, |
| /* 1401 */ 'P', 'R', 'E', 'C', 'R', '_', 'Q', 'B', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0, |
| /* 1418 */ 'S', 'U', 'B', 'Q', 'H', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0, |
| /* 1432 */ 'A', 'D', 'D', 'Q', 'H', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0, |
| /* 1446 */ 'S', 'H', 'R', 'L', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0, |
| /* 1459 */ 'M', 'U', 'L', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0, |
| /* 1471 */ 'S', 'U', 'B', 'Q', 'H', '_', 'R', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0, |
| /* 1487 */ 'A', 'D', 'D', 'Q', 'H', '_', 'R', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0, |
| /* 1503 */ 'M', 'U', 'L', '_', 'S', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0, |
| /* 1517 */ 'M', 'U', 'L', 'Q', '_', 'S', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0, |
| /* 1532 */ 'S', 'U', 'B', 'U', '_', 'S', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0, |
| /* 1547 */ 'A', 'D', 'D', 'U', '_', 'S', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0, |
| /* 1562 */ 'S', 'U', 'B', 'U', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0, |
| /* 1575 */ 'A', 'D', 'D', 'U', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0, |
| /* 1588 */ 'S', 'H', 'R', 'L', 'V', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0, |
| /* 1602 */ 'D', 'P', 'A', '_', 'W', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0, |
| /* 1616 */ 'M', 'U', 'L', 'S', 'A', '_', 'W', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0, |
| /* 1632 */ 'D', 'P', 'A', 'Q', 'X', '_', 'S', 'A', '_', 'W', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0, |
| /* 1651 */ 'D', 'P', 'S', 'Q', 'X', '_', 'S', 'A', '_', 'W', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0, |
| /* 1670 */ 'D', 'P', 'S', '_', 'W', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0, |
| /* 1684 */ 'D', 'P', 'A', 'Q', 'X', '_', 'S', '_', 'W', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0, |
| /* 1702 */ 'D', 'P', 'S', 'Q', 'X', '_', 'S', '_', 'W', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0, |
| /* 1720 */ 'D', 'P', 'A', 'X', '_', 'W', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0, |
| /* 1735 */ 'D', 'P', 'S', 'X', '_', 'W', '_', 'P', 'H', '_', 'M', 'M', 'R', '2', 0, |
| /* 1750 */ 'B', 'A', 'L', 'I', 'G', 'N', '_', 'M', 'M', 'R', '2', 0, |
| /* 1762 */ 'P', 'R', 'E', 'C', 'R', '_', 'S', 'R', 'A', '_', 'P', 'H', '_', 'W', '_', 'M', 'M', 'R', '2', 0, |
| /* 1782 */ 'P', 'R', 'E', 'C', 'R', '_', 'S', 'R', 'A', '_', 'R', '_', 'P', 'H', '_', 'W', '_', 'M', 'M', 'R', '2', 0, |
| /* 1804 */ 'S', 'U', 'B', 'Q', 'H', '_', 'W', '_', 'M', 'M', 'R', '2', 0, |
| /* 1817 */ 'A', 'D', 'D', 'Q', 'H', '_', 'W', '_', 'M', 'M', 'R', '2', 0, |
| /* 1830 */ 'S', 'U', 'B', 'Q', 'H', '_', 'R', '_', 'W', '_', 'M', 'M', 'R', '2', 0, |
| /* 1845 */ 'A', 'D', 'D', 'Q', 'H', '_', 'R', '_', 'W', '_', 'M', 'M', 'R', '2', 0, |
| /* 1860 */ 'M', 'U', 'L', 'Q', '_', 'R', 'S', '_', 'W', '_', 'M', 'M', 'R', '2', 0, |
| /* 1875 */ 'M', 'U', 'L', 'Q', '_', 'S', '_', 'W', '_', 'M', 'M', 'R', '2', 0, |
| /* 1889 */ 'L', 'D', 'C', '3', 0, |
| /* 1894 */ 'S', 'D', 'C', '3', 0, |
| /* 1899 */ 'L', 'W', 'C', '3', 0, |
| /* 1904 */ 'S', 'W', 'C', '3', 0, |
| /* 1909 */ 'B', 'P', 'O', 'S', 'G', 'E', '3', '2', 'C', '_', 'M', 'M', 'R', '3', 0, |
| /* 1924 */ 'L', 'D', 'C', '1', '6', '4', 0, |
| /* 1931 */ 'S', 'D', 'C', '1', '6', '4', 0, |
| /* 1938 */ 'L', 'D', 'X', 'C', '1', '6', '4', 0, |
| /* 1946 */ 'S', 'D', 'X', 'C', '1', '6', '4', 0, |
| /* 1954 */ 'L', 'U', 'X', 'C', '1', '6', '4', 0, |
| /* 1962 */ 'S', 'U', 'X', 'C', '1', '6', '4', 0, |
| /* 1970 */ 'S', 'E', 'B', '6', '4', 0, |
| /* 1976 */ 'T', 'A', 'I', 'L', 'C', 'A', 'L', 'L', 'R', 'E', 'G', 'H', 'B', '6', '4', 0, |
| /* 1992 */ 'J', 'R', '_', 'H', 'B', '6', '4', 0, |
| /* 2000 */ 'J', 'A', 'L', 'R', '_', 'H', 'B', '6', '4', 0, |
| /* 2010 */ 'L', 'B', '6', '4', 0, |
| /* 2015 */ 'S', 'B', '6', '4', 0, |
| /* 2020 */ 'L', 'O', 'A', 'D', '_', 'A', 'C', 'C', '6', '4', 0, |
| /* 2031 */ 'S', 'T', 'O', 'R', 'E', '_', 'A', 'C', 'C', '6', '4', 0, |
| /* 2043 */ 'B', 'G', 'E', 'C', '6', '4', 0, |
| /* 2050 */ 'B', 'N', 'E', 'C', '6', '4', 0, |
| /* 2057 */ 'J', 'I', 'C', '6', '4', 0, |
| /* 2063 */ 'J', 'I', 'A', 'L', 'C', '6', '4', 0, |
| /* 2071 */ 'B', 'E', 'Q', 'C', '6', '4', 0, |
| /* 2078 */ 'S', 'C', '6', '4', 0, |
| /* 2083 */ 'B', 'L', 'T', 'C', '6', '4', 0, |
| /* 2090 */ 'B', 'G', 'E', 'U', 'C', '6', '4', 0, |
| /* 2098 */ 'B', 'L', 'T', 'U', 'C', '6', '4', 0, |
| /* 2106 */ 'B', 'G', 'E', 'Z', 'C', '6', '4', 0, |
| /* 2114 */ 'B', 'L', 'E', 'Z', 'C', '6', '4', 0, |
| /* 2122 */ 'B', 'N', 'E', 'Z', 'C', '6', '4', 0, |
| /* 2130 */ 'B', 'E', 'Q', 'Z', 'C', '6', '4', 0, |
| /* 2138 */ 'B', 'G', 'T', 'Z', 'C', '6', '4', 0, |
| /* 2146 */ 'B', 'L', 'T', 'Z', 'C', '6', '4', 0, |
| /* 2154 */ 'A', 'N', 'D', '6', '4', 0, |
| /* 2160 */ 'M', 'F', 'C', '1', '_', 'D', '6', '4', 0, |
| /* 2169 */ 'M', 'F', 'H', 'C', '1', '_', 'D', '6', '4', 0, |
| /* 2179 */ 'M', 'T', 'H', 'C', '1', '_', 'D', '6', '4', 0, |
| /* 2189 */ 'M', 'T', 'C', '1', '_', 'D', '6', '4', 0, |
| /* 2198 */ 'M', 'O', 'V', 'N', '_', 'I', '6', '4', '_', 'D', '6', '4', 0, |
| /* 2211 */ 'M', 'O', 'V', 'Z', '_', 'I', '6', '4', '_', 'D', '6', '4', 0, |
| /* 2224 */ 'F', 'S', 'U', 'B', '_', 'D', '6', '4', 0, |
| /* 2233 */ 'N', 'M', 'S', 'U', 'B', '_', 'D', '6', '4', 0, |
| /* 2243 */ 'F', 'A', 'D', 'D', '_', 'D', '6', '4', 0, |
| /* 2252 */ 'N', 'M', 'A', 'D', 'D', '_', 'D', '6', '4', 0, |
| /* 2262 */ 'C', '_', 'N', 'G', 'E', '_', 'D', '6', '4', 0, |
| /* 2272 */ 'C', '_', 'N', 'G', 'L', 'E', '_', 'D', '6', '4', 0, |
| /* 2283 */ 'C', '_', 'O', 'L', 'E', '_', 'D', '6', '4', 0, |
| /* 2293 */ 'C', '_', 'U', 'L', 'E', '_', 'D', '6', '4', 0, |
| /* 2303 */ 'C', '_', 'L', 'E', '_', 'D', '6', '4', 0, |
| /* 2312 */ 'C', '_', 'S', 'F', '_', 'D', '6', '4', 0, |
| /* 2321 */ 'M', 'O', 'V', 'F', '_', 'D', '6', '4', 0, |
| /* 2330 */ 'C', '_', 'F', '_', 'D', '6', '4', 0, |
| /* 2338 */ 'P', 's', 'e', 'u', 'd', 'o', 'S', 'E', 'L', 'E', 'C', 'T', 'F', 'P', '_', 'F', '_', 'D', '6', '4', 0, |
| /* 2359 */ 'F', 'N', 'E', 'G', '_', 'D', '6', '4', 0, |
| /* 2368 */ 'M', 'O', 'V', 'N', '_', 'I', '_', 'D', '6', '4', 0, |
| /* 2379 */ 'M', 'O', 'V', 'Z', '_', 'I', '_', 'D', '6', '4', 0, |
| /* 2390 */ 'C', '_', 'N', 'G', 'L', '_', 'D', '6', '4', 0, |
| /* 2400 */ 'F', 'M', 'U', 'L', '_', 'D', '6', '4', 0, |
| /* 2409 */ 'T', 'R', 'U', 'N', 'C', '_', 'L', '_', 'D', '6', '4', 0, |
| /* 2421 */ 'R', 'O', 'U', 'N', 'D', '_', 'L', '_', 'D', '6', '4', 0, |
| /* 2433 */ 'C', 'E', 'I', 'L', '_', 'L', '_', 'D', '6', '4', 0, |
| /* 2444 */ 'F', 'L', 'O', 'O', 'R', '_', 'L', '_', 'D', '6', '4', 0, |
| /* 2456 */ 'C', 'V', 'T', '_', 'L', '_', 'D', '6', '4', 0, |
| /* 2466 */ 'C', '_', 'U', 'N', '_', 'D', '6', '4', 0, |
| /* 2475 */ 'R', 'E', 'C', 'I', 'P', '_', 'D', '6', '4', 0, |
| /* 2485 */ 'F', 'C', 'M', 'P', '_', 'D', '6', '4', 0, |
| /* 2494 */ 'C', '_', 'S', 'E', 'Q', '_', 'D', '6', '4', 0, |
| /* 2504 */ 'C', '_', 'U', 'E', 'Q', '_', 'D', '6', '4', 0, |
| /* 2514 */ 'C', '_', 'E', 'Q', '_', 'D', '6', '4', 0, |
| /* 2523 */ 'F', 'A', 'B', 'S', '_', 'D', '6', '4', 0, |
| /* 2532 */ 'C', 'V', 'T', '_', 'S', '_', 'D', '6', '4', 0, |
| /* 2542 */ 'P', 's', 'e', 'u', 'd', 'o', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'D', '6', '4', 0, |
| /* 2559 */ 'C', '_', 'N', 'G', 'T', '_', 'D', '6', '4', 0, |
| /* 2569 */ 'C', '_', 'O', 'L', 'T', '_', 'D', '6', '4', 0, |
| /* 2579 */ 'C', '_', 'U', 'L', 'T', '_', 'D', '6', '4', 0, |
| /* 2589 */ 'C', '_', 'L', 'T', '_', 'D', '6', '4', 0, |
| /* 2598 */ 'F', 'S', 'Q', 'R', 'T', '_', 'D', '6', '4', 0, |
| /* 2608 */ 'R', 'S', 'Q', 'R', 'T', '_', 'D', '6', '4', 0, |
| /* 2618 */ 'M', 'O', 'V', 'T', '_', 'D', '6', '4', 0, |
| /* 2627 */ 'P', 's', 'e', 'u', 'd', 'o', 'S', 'E', 'L', 'E', 'C', 'T', 'F', 'P', '_', 'T', '_', 'D', '6', '4', 0, |
| /* 2648 */ 'F', 'D', 'I', 'V', '_', 'D', '6', '4', 0, |
| /* 2657 */ 'F', 'M', 'O', 'V', '_', 'D', '6', '4', 0, |
| /* 2666 */ 'T', 'R', 'U', 'N', 'C', '_', 'W', '_', 'D', '6', '4', 0, |
| /* 2678 */ 'R', 'O', 'U', 'N', 'D', '_', 'W', '_', 'D', '6', '4', 0, |
| /* 2690 */ 'C', 'E', 'I', 'L', '_', 'W', '_', 'D', '6', '4', 0, |
| /* 2701 */ 'F', 'L', 'O', 'O', 'R', '_', 'W', '_', 'D', '6', '4', 0, |
| /* 2713 */ 'C', 'V', 'T', '_', 'W', '_', 'D', '6', '4', 0, |
| /* 2723 */ 'B', 'N', 'E', '6', '4', 0, |
| /* 2729 */ 'B', 'u', 'i', 'l', 'd', 'P', 'a', 'i', 'r', 'F', '6', '4', 0, |
| /* 2742 */ 'E', 'x', 't', 'r', 'a', 'c', 't', 'E', 'l', 'e', 'm', 'e', 'n', 't', 'F', '6', '4', 0, |
| /* 2760 */ 'T', 'A', 'I', 'L', 'C', 'A', 'L', 'L', 'R', 'E', 'G', '6', '4', 0, |
| /* 2774 */ 'S', 'E', 'H', '6', '4', 0, |
| /* 2780 */ 'L', 'H', '6', '4', 0, |
| /* 2785 */ 'S', 'H', '6', '4', 0, |
| /* 2790 */ 'P', 's', 'e', 'u', 'd', 'o', 'M', 'F', 'H', 'I', '6', '4', 0, |
| /* 2803 */ 'P', 's', 'e', 'u', 'd', 'o', 'M', 'T', 'L', 'O', 'H', 'I', '6', '4', 0, |
| /* 2818 */ 'M', 'T', 'H', 'I', '6', '4', 0, |
| /* 2825 */ 'M', 'O', 'V', 'N', '_', 'I', '6', '4', '_', 'I', '6', '4', 0, |
| /* 2838 */ 'M', 'O', 'V', 'Z', '_', 'I', '6', '4', '_', 'I', '6', '4', 0, |
| /* 2851 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'S', 'U', 'B', '_', 'I', '6', '4', 0, |
| /* 2871 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'A', 'D', 'D', '_', 'I', '6', '4', 0, |
| /* 2891 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'N', 'A', 'N', 'D', '_', 'I', '6', '4', 0, |
| /* 2912 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'A', 'N', 'D', '_', 'I', '6', '4', 0, |
| /* 2932 */ 'M', 'O', 'V', 'F', '_', 'I', '6', '4', 0, |
| /* 2941 */ 'P', 's', 'e', 'u', 'd', 'o', 'S', 'E', 'L', 'E', 'C', 'T', 'F', 'P', '_', 'F', '_', 'I', '6', '4', 0, |
| /* 2962 */ 'M', 'O', 'V', 'N', '_', 'I', '_', 'I', '6', '4', 0, |
| /* 2973 */ 'M', 'O', 'V', 'Z', '_', 'I', '_', 'I', '6', '4', 0, |
| /* 2984 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'U', 'M', 'I', 'N', '_', 'I', '6', '4', 0, |
| /* 3005 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'M', 'I', 'N', '_', 'I', '6', '4', 0, |
| /* 3025 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'S', 'W', 'A', 'P', '_', 'I', '6', '4', 0, |
| /* 3041 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'C', 'M', 'P', '_', 'S', 'W', 'A', 'P', '_', 'I', '6', '4', 0, |
| /* 3061 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'X', 'O', 'R', '_', 'I', '6', '4', 0, |
| /* 3081 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'O', 'R', '_', 'I', '6', '4', 0, |
| /* 3100 */ 'P', 's', 'e', 'u', 'd', 'o', 'D', '_', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'I', '6', '4', 0, |
| /* 3119 */ 'P', 's', 'e', 'u', 'd', 'o', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'I', '6', '4', 0, |
| /* 3136 */ 'M', 'O', 'V', 'T', '_', 'I', '6', '4', 0, |
| /* 3145 */ 'P', 's', 'e', 'u', 'd', 'o', 'S', 'E', 'L', 'E', 'C', 'T', 'F', 'P', '_', 'T', '_', 'I', '6', '4', 0, |
| /* 3166 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'U', 'M', 'A', 'X', '_', 'I', '6', '4', 0, |
| /* 3187 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'M', 'A', 'X', '_', 'I', '6', '4', 0, |
| /* 3207 */ 'L', 'L', '6', '4', 0, |
| /* 3212 */ 'C', 'V', 'T', '_', 'S', '_', 'P', 'L', '6', '4', 0, |
| /* 3223 */ 'L', 'W', 'L', '6', '4', 0, |
| /* 3229 */ 'S', 'W', 'L', '6', '4', 0, |
| /* 3235 */ 'P', 's', 'e', 'u', 'd', 'o', 'M', 'F', 'L', 'O', '6', '4', 0, |
| /* 3248 */ 'M', 'T', 'L', 'O', '6', '4', 0, |
| /* 3255 */ 'B', 'E', 'Q', '6', '4', 0, |
| /* 3261 */ 'J', 'R', '6', '4', 0, |
| /* 3266 */ 'J', 'A', 'L', 'R', '6', '4', 0, |
| /* 3273 */ 'N', 'O', 'R', '6', '4', 0, |
| /* 3279 */ 'X', 'O', 'R', '6', '4', 0, |
| /* 3285 */ 'R', 'D', 'H', 'W', 'R', '6', '4', 0, |
| /* 3293 */ 'L', 'W', 'R', '6', '4', 0, |
| /* 3299 */ 'S', 'W', 'R', '6', '4', 0, |
| /* 3305 */ 'P', 'L', 'L', '_', 'P', 'S', '6', '4', 0, |
| /* 3314 */ 'P', 'L', 'U', '_', 'P', 'S', '6', '4', 0, |
| /* 3323 */ 'C', 'V', 'T', '_', 'P', 'S', '_', 'S', '6', '4', 0, |
| /* 3334 */ 'S', 'L', 'T', '6', '4', 0, |
| /* 3340 */ 'C', 'V', 'T', '_', 'S', '_', 'P', 'U', '6', '4', 0, |
| /* 3351 */ 'L', 'W', '6', '4', 0, |
| /* 3356 */ 'S', 'W', '6', '4', 0, |
| /* 3361 */ 'B', 'G', 'E', 'Z', '6', '4', 0, |
| /* 3368 */ 'B', 'L', 'E', 'Z', '6', '4', 0, |
| /* 3375 */ 'S', 'E', 'L', 'N', 'E', 'Z', '6', '4', 0, |
| /* 3384 */ 'S', 'E', 'L', 'E', 'Q', 'Z', '6', '4', 0, |
| /* 3393 */ 'B', 'G', 'T', 'Z', '6', '4', 0, |
| /* 3400 */ 'B', 'L', 'T', 'Z', '6', '4', 0, |
| /* 3407 */ 'B', 'u', 'i', 'l', 'd', 'P', 'a', 'i', 'r', 'F', '6', '4', '_', '6', '4', 0, |
| /* 3423 */ 'E', 'x', 't', 'r', 'a', 'c', 't', 'E', 'l', 'e', 'm', 'e', 'n', 't', 'F', '6', '4', '_', '6', '4', 0, |
| /* 3444 */ 'S', 'L', 'L', '6', '4', '_', '6', '4', 0, |
| /* 3453 */ 'L', 'O', 'N', 'G', '_', 'B', 'R', 'A', 'N', 'C', 'H', '_', 'L', 'U', 'i', '2', 'O', 'p', '_', '6', '4', 0, |
| /* 3475 */ 'L', 'o', 'a', 'd', 'A', 'd', 'd', 'r', 'R', 'e', 'g', '6', '4', 0, |
| /* 3489 */ 'P', 's', 'e', 'u', 'd', 'o', 'I', 'n', 'd', 'i', 'r', 'e', 'c', 't', 'H', 'a', 'z', 'a', 'r', 'd', 'B', 'r', 'a', 'n', 'c', 'h', '6', '4', 0, |
| /* 3518 */ 'P', 's', 'e', 'u', 'd', 'o', 'I', 'n', 'd', 'i', 'r', 'e', 'c', 't', 'B', 'r', 'a', 'n', 'c', 'h', '6', '4', 0, |
| /* 3541 */ 'A', 'N', 'D', 'i', '6', '4', 0, |
| /* 3548 */ 'X', 'O', 'R', 'i', '6', '4', 0, |
| /* 3555 */ 'S', 'L', 'T', 'i', '6', '4', 0, |
| /* 3562 */ 'L', 'U', 'i', '6', '4', 0, |
| /* 3568 */ 'S', 'G', 'E', 'I', 'm', 'm', '6', '4', 0, |
| /* 3577 */ 'N', 'O', 'R', 'I', 'm', 'm', '6', '4', 0, |
| /* 3586 */ 'S', 'G', 'T', 'I', 'm', 'm', '6', '4', 0, |
| /* 3595 */ 'S', 'L', 'T', 'I', 'm', 'm', '6', '4', 0, |
| /* 3604 */ 'S', 'G', 'E', 'U', 'I', 'm', 'm', '6', '4', 0, |
| /* 3614 */ 'S', 'G', 'T', 'U', 'I', 'm', 'm', '6', '4', 0, |
| /* 3624 */ 'S', 'L', 'T', 'U', 'I', 'm', 'm', '6', '4', 0, |
| /* 3634 */ 'L', 'o', 'a', 'd', 'I', 'm', 'm', '6', '4', 0, |
| /* 3644 */ 'L', 'o', 'a', 'd', 'A', 'd', 'd', 'r', 'I', 'm', 'm', '6', '4', 0, |
| /* 3658 */ 'P', 's', 'e', 'u', 'd', 'o', 'R', 'e', 't', 'u', 'r', 'n', '6', '4', 0, |
| /* 3673 */ 'M', 'I', 'P', 'S', 'e', 'h', '_', 'r', 'e', 't', 'u', 'r', 'n', '6', '4', 0, |
| /* 3689 */ 'L', 'B', 'u', '6', '4', 0, |
| /* 3695 */ 'L', 'H', 'u', '6', '4', 0, |
| /* 3701 */ 'S', 'L', 'T', 'u', '6', '4', 0, |
| /* 3708 */ 'L', 'E', 'A', '_', 'A', 'D', 'D', 'i', 'u', '6', '4', 0, |
| /* 3720 */ 'S', 'L', 'T', 'i', 'u', '6', '4', 0, |
| /* 3728 */ 'M', 'o', 'v', 'e', 'R', '3', '2', '1', '6', 0, |
| /* 3738 */ 'R', 'e', 't', 'R', 'A', '1', '6', 0, |
| /* 3746 */ 'J', 'a', 'l', 'B', '1', '6', 0, |
| /* 3753 */ 'L', 'D', '_', 'F', '1', '6', 0, |
| /* 3760 */ 'S', 'T', '_', 'F', '1', '6', 0, |
| /* 3767 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'S', 'U', 'B', '_', 'I', '1', '6', 0, |
| /* 3787 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'A', 'D', 'D', '_', 'I', '1', '6', 0, |
| /* 3807 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'N', 'A', 'N', 'D', '_', 'I', '1', '6', 0, |
| /* 3828 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'A', 'N', 'D', '_', 'I', '1', '6', 0, |
| /* 3848 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'U', 'M', 'I', 'N', '_', 'I', '1', '6', 0, |
| /* 3869 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'M', 'I', 'N', '_', 'I', '1', '6', 0, |
| /* 3889 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'S', 'W', 'A', 'P', '_', 'I', '1', '6', 0, |
| /* 3905 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'C', 'M', 'P', '_', 'S', 'W', 'A', 'P', '_', 'I', '1', '6', 0, |
| /* 3925 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'X', 'O', 'R', '_', 'I', '1', '6', 0, |
| /* 3945 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'O', 'R', '_', 'I', '1', '6', 0, |
| /* 3964 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'U', 'M', 'A', 'X', '_', 'I', '1', '6', 0, |
| /* 3985 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'M', 'A', 'X', '_', 'I', '1', '6', 0, |
| /* 4005 */ 'M', 'o', 'v', 'e', '3', '2', 'R', '1', '6', 0, |
| /* 4015 */ 'S', 'r', 'a', 'X', '1', '6', 0, |
| /* 4022 */ 'R', 'e', 's', 't', 'o', 'r', 'e', 'X', '1', '6', 0, |
| /* 4033 */ 'S', 'a', 'v', 'e', 'X', '1', '6', 0, |
| /* 4041 */ 'B', 't', 'n', 'e', 'z', 'T', '8', 'C', 'm', 'p', 'i', 'X', '1', '6', 0, |
| /* 4056 */ 'B', 't', 'e', 'q', 'z', 'T', '8', 'C', 'm', 'p', 'i', 'X', '1', '6', 0, |
| /* 4071 */ 'B', 't', 'n', 'e', 'z', 'T', '8', 'S', 'l', 't', 'i', 'X', '1', '6', 0, |
| /* 4086 */ 'B', 't', 'e', 'q', 'z', 'T', '8', 'S', 'l', 't', 'i', 'X', '1', '6', 0, |
| /* 4101 */ 'S', 'l', 'l', 'X', '1', '6', 0, |
| /* 4108 */ 'S', 'r', 'l', 'X', '1', '6', 0, |
| /* 4115 */ 'L', 'b', 'R', 'x', 'R', 'y', 'O', 'f', 'f', 'M', 'e', 'm', 'X', '1', '6', 0, |
| /* 4131 */ 'S', 'b', 'R', 'x', 'R', 'y', 'O', 'f', 'f', 'M', 'e', 'm', 'X', '1', '6', 0, |
| /* 4147 */ 'L', 'h', 'R', 'x', 'R', 'y', 'O', 'f', 'f', 'M', 'e', 'm', 'X', '1', '6', 0, |
| /* 4163 */ 'S', 'h', 'R', 'x', 'R', 'y', 'O', 'f', 'f', 'M', 'e', 'm', 'X', '1', '6', 0, |
| /* 4179 */ 'L', 'b', 'u', 'R', 'x', 'R', 'y', 'O', 'f', 'f', 'M', 'e', 'm', 'X', '1', '6', 0, |
| /* 4196 */ 'L', 'h', 'u', 'R', 'x', 'R', 'y', 'O', 'f', 'f', 'M', 'e', 'm', 'X', '1', '6', 0, |
| /* 4213 */ 'A', 'd', 'd', 'i', 'u', 'R', 'x', 'R', 'y', 'O', 'f', 'f', 'M', 'e', 'm', 'X', '1', '6', 0, |
| /* 4232 */ 'L', 'w', 'R', 'x', 'R', 'y', 'O', 'f', 'f', 'M', 'e', 'm', 'X', '1', '6', 0, |
| /* 4248 */ 'S', 'w', 'R', 'x', 'R', 'y', 'O', 'f', 'f', 'M', 'e', 'm', 'X', '1', '6', 0, |
| /* 4264 */ 'A', 'd', 'd', 'i', 'u', 'R', 'x', 'P', 'c', 'I', 'm', 'm', 'X', '1', '6', 0, |
| /* 4280 */ 'A', 'd', 'd', 'i', 'u', 'S', 'p', 'I', 'm', 'm', 'X', '1', '6', 0, |
| /* 4294 */ 'L', 'w', 'R', 'x', 'S', 'p', 'I', 'm', 'm', 'X', '1', '6', 0, |
| /* 4307 */ 'S', 'w', 'R', 'x', 'S', 'p', 'I', 'm', 'm', 'X', '1', '6', 0, |
| /* 4320 */ 'S', 'l', 't', 'i', 'C', 'C', 'R', 'x', 'I', 'm', 'm', 'X', '1', '6', 0, |
| /* 4335 */ 'S', 'l', 't', 'i', 'u', 'C', 'C', 'R', 'x', 'I', 'm', 'm', 'X', '1', '6', 0, |
| /* 4351 */ 'L', 'i', 'R', 'x', 'I', 'm', 'm', 'X', '1', '6', 0, |
| /* 4362 */ 'C', 'm', 'p', 'i', 'R', 'x', 'I', 'm', 'm', 'X', '1', '6', 0, |
| /* 4375 */ 'S', 'l', 't', 'i', 'R', 'x', 'I', 'm', 'm', 'X', '1', '6', 0, |
| /* 4388 */ 'A', 'd', 'd', 'i', 'u', 'R', 'x', 'I', 'm', 'm', 'X', '1', '6', 0, |
| /* 4402 */ 'S', 'l', 't', 'i', 'u', 'R', 'x', 'I', 'm', 'm', 'X', '1', '6', 0, |
| /* 4416 */ 'A', 'd', 'd', 'i', 'u', 'R', 'x', 'R', 'x', 'I', 'm', 'm', 'X', '1', '6', 0, |
| /* 4432 */ 'B', 'n', 'e', 'z', 'R', 'x', 'I', 'm', 'm', 'X', '1', '6', 0, |
| /* 4445 */ 'B', 'e', 'q', 'z', 'R', 'x', 'I', 'm', 'm', 'X', '1', '6', 0, |
| /* 4458 */ 'B', 'i', 'm', 'm', 'X', '1', '6', 0, |
| /* 4466 */ 'L', 'i', 'R', 'x', 'I', 'm', 'm', 'A', 'l', 'i', 'g', 'n', 'X', '1', '6', 0, |
| /* 4482 */ 'L', 'w', 'R', 'x', 'P', 'c', 'T', 'c', 'p', 'X', '1', '6', 0, |
| /* 4495 */ 'B', 't', 'n', 'e', 'z', 'T', '8', 'C', 'm', 'p', 'X', '1', '6', 0, |
| /* 4509 */ 'B', 't', 'e', 'q', 'z', 'T', '8', 'C', 'm', 'p', 'X', '1', '6', 0, |
| /* 4523 */ 'B', 't', 'n', 'e', 'z', 'T', '8', 'S', 'l', 't', 'X', '1', '6', 0, |
| /* 4537 */ 'B', 't', 'e', 'q', 'z', 'T', '8', 'S', 'l', 't', 'X', '1', '6', 0, |
| /* 4551 */ 'B', 't', 'n', 'e', 'z', 'T', '8', 'S', 'l', 't', 'i', 'u', 'X', '1', '6', 0, |
| /* 4567 */ 'B', 't', 'e', 'q', 'z', 'T', '8', 'S', 'l', 't', 'i', 'u', 'X', '1', '6', 0, |
| /* 4583 */ 'B', 't', 'n', 'e', 'z', 'T', '8', 'S', 'l', 't', 'u', 'X', '1', '6', 0, |
| /* 4598 */ 'B', 't', 'e', 'q', 'z', 'T', '8', 'S', 'l', 't', 'u', 'X', '1', '6', 0, |
| /* 4613 */ 'B', 't', 'n', 'e', 'z', 'X', '1', '6', 0, |
| /* 4622 */ 'B', 't', 'e', 'q', 'z', 'X', '1', '6', 0, |
| /* 4631 */ 'J', 'r', 'c', 'R', 'a', '1', '6', 0, |
| /* 4639 */ 'J', 'r', 'R', 'a', '1', '6', 0, |
| /* 4646 */ 'R', 'e', 's', 't', 'o', 'r', 'e', '1', '6', 0, |
| /* 4656 */ 'G', 'o', 't', 'P', 'r', 'o', 'l', 'o', 'g', 'u', 'e', '1', '6', 0, |
| /* 4670 */ 'S', 'a', 'v', 'e', '1', '6', 0, |
| /* 4677 */ 'J', 'u', 'm', 'p', 'L', 'i', 'n', 'k', 'R', 'e', 'g', '1', '6', 0, |
| /* 4691 */ 'M', 'f', 'h', 'i', '1', '6', 0, |
| /* 4698 */ 'B', 'r', 'e', 'a', 'k', '1', '6', 0, |
| /* 4706 */ 'J', 'a', 'l', '1', '6', 0, |
| /* 4712 */ 'A', 'd', 'd', 'i', 'u', 'S', 'p', 'I', 'm', 'm', '1', '6', 0, |
| /* 4725 */ 'L', 'i', 'R', 'x', 'I', 'm', 'm', '1', '6', 0, |
| /* 4735 */ 'C', 'm', 'p', 'i', 'R', 'x', 'I', 'm', 'm', '1', '6', 0, |
| /* 4747 */ 'S', 'l', 't', 'i', 'R', 'x', 'I', 'm', 'm', '1', '6', 0, |
| /* 4759 */ 'S', 'l', 't', 'i', 'u', 'R', 'x', 'I', 'm', 'm', '1', '6', 0, |
| /* 4772 */ 'A', 'd', 'd', 'i', 'u', 'R', 'x', 'R', 'x', 'I', 'm', 'm', '1', '6', 0, |
| /* 4787 */ 'B', 'n', 'e', 'z', 'R', 'x', 'I', 'm', 'm', '1', '6', 0, |
| /* 4799 */ 'B', 'e', 'q', 'z', 'R', 'x', 'I', 'm', 'm', '1', '6', 0, |
| /* 4811 */ 'B', 'i', 'm', 'm', '1', '6', 0, |
| /* 4818 */ 'M', 'f', 'l', 'o', '1', '6', 0, |
| /* 4825 */ 'L', 'w', 'R', 'x', 'P', 'c', 'T', 'c', 'p', '1', '6', 0, |
| /* 4837 */ 'S', 'e', 'b', 'R', 'x', '1', '6', 0, |
| /* 4845 */ 'J', 'r', 'c', 'R', 'x', '1', '6', 0, |
| /* 4853 */ 'S', 'e', 'h', 'R', 'x', '1', '6', 0, |
| /* 4861 */ 'S', 'l', 't', 'C', 'C', 'R', 'x', 'R', 'y', '1', '6', 0, |
| /* 4873 */ 'S', 'l', 't', 'u', 'C', 'C', 'R', 'x', 'R', 'y', '1', '6', 0, |
| /* 4886 */ 'N', 'e', 'g', 'R', 'x', 'R', 'y', '1', '6', 0, |
| /* 4896 */ 'C', 'm', 'p', 'R', 'x', 'R', 'y', '1', '6', 0, |
| /* 4906 */ 'S', 'l', 't', 'R', 'x', 'R', 'y', '1', '6', 0, |
| /* 4916 */ 'M', 'u', 'l', 't', 'R', 'x', 'R', 'y', '1', '6', 0, |
| /* 4927 */ 'N', 'o', 't', 'R', 'x', 'R', 'y', '1', '6', 0, |
| /* 4937 */ 'S', 'l', 't', 'u', 'R', 'x', 'R', 'y', '1', '6', 0, |
| /* 4948 */ 'M', 'u', 'l', 't', 'u', 'R', 'x', 'R', 'y', '1', '6', 0, |
| /* 4960 */ 'D', 'i', 'v', 'u', 'R', 'x', 'R', 'y', '1', '6', 0, |
| /* 4971 */ 'S', 'r', 'a', 'v', 'R', 'x', 'R', 'y', '1', '6', 0, |
| /* 4982 */ 'D', 'i', 'v', 'R', 'x', 'R', 'y', '1', '6', 0, |
| /* 4992 */ 'S', 'l', 'l', 'v', 'R', 'x', 'R', 'y', '1', '6', 0, |
| /* 5003 */ 'S', 'r', 'l', 'v', 'R', 'x', 'R', 'y', '1', '6', 0, |
| /* 5014 */ 'A', 'n', 'd', 'R', 'x', 'R', 'x', 'R', 'y', '1', '6', 0, |
| /* 5026 */ 'O', 'r', 'R', 'x', 'R', 'x', 'R', 'y', '1', '6', 0, |
| /* 5037 */ 'X', 'o', 'r', 'R', 'x', 'R', 'x', 'R', 'y', '1', '6', 0, |
| /* 5049 */ 'M', 'u', 'l', 't', 'R', 'x', 'R', 'y', 'R', 'z', '1', '6', 0, |
| /* 5062 */ 'S', 'u', 'b', 'u', 'R', 'x', 'R', 'y', 'R', 'z', '1', '6', 0, |
| /* 5075 */ 'A', 'd', 'd', 'u', 'R', 'x', 'R', 'y', 'R', 'z', '1', '6', 0, |
| /* 5088 */ 'S', 'l', 't', 'u', 'R', 'x', 'R', 'y', 'R', 'z', '1', '6', 0, |
| /* 5101 */ 'M', 'u', 'l', 't', 'u', 'R', 'x', 'R', 'y', 'R', 'z', '1', '6', 0, |
| /* 5115 */ 'B', 't', 'n', 'e', 'z', '1', '6', 0, |
| /* 5123 */ 'B', 't', 'e', 'q', 'z', '1', '6', 0, |
| /* 5131 */ 'P', 's', 'e', 'u', 'd', 'o', 'I', 'n', 'd', 'r', 'e', 'c', 't', 'H', 'a', 'z', 'a', 'r', 'd', 'B', 'r', 'a', 'n', 'c', 'h', '6', '4', 'R', '6', 0, |
| /* 5161 */ 'P', 's', 'e', 'u', 'd', 'o', 'I', 'n', 'd', 'i', 'r', 'e', 'c', 't', 'B', 'r', 'a', 'n', 'c', 'h', '6', '4', 'R', '6', 0, |
| /* 5186 */ 'M', 'F', 'C', '0', '_', 'M', 'M', 'R', '6', 0, |
| /* 5196 */ 'M', 'F', 'H', 'C', '0', '_', 'M', 'M', 'R', '6', 0, |
| /* 5207 */ 'M', 'T', 'H', 'C', '0', '_', 'M', 'M', 'R', '6', 0, |
| /* 5218 */ 'M', 'T', 'C', '0', '_', 'M', 'M', 'R', '6', 0, |
| /* 5228 */ 'M', 'F', 'C', '1', '_', 'M', 'M', 'R', '6', 0, |
| /* 5238 */ 'M', 'T', 'C', '1', '_', 'M', 'M', 'R', '6', 0, |
| /* 5248 */ 'L', 'D', 'C', '2', '_', 'M', 'M', 'R', '6', 0, |
| /* 5258 */ 'S', 'D', 'C', '2', '_', 'M', 'M', 'R', '6', 0, |
| /* 5268 */ 'M', 'F', 'C', '2', '_', 'M', 'M', 'R', '6', 0, |
| /* 5278 */ 'M', 'F', 'H', 'C', '2', '_', 'M', 'M', 'R', '6', 0, |
| /* 5289 */ 'M', 'T', 'H', 'C', '2', '_', 'M', 'M', 'R', '6', 0, |
| /* 5300 */ 'M', 'T', 'C', '2', '_', 'M', 'M', 'R', '6', 0, |
| /* 5310 */ 'L', 'W', 'C', '2', '_', 'M', 'M', 'R', '6', 0, |
| /* 5320 */ 'S', 'W', 'C', '2', '_', 'M', 'M', 'R', '6', 0, |
| /* 5330 */ 'L', 'D', 'C', '1', '_', 'D', '6', '4', '_', 'M', 'M', 'R', '6', 0, |
| /* 5344 */ 'S', 'D', 'C', '1', '_', 'D', '6', '4', '_', 'M', 'M', 'R', '6', 0, |
| /* 5358 */ 'S', 'B', '1', '6', '_', 'M', 'M', 'R', '6', 0, |
| /* 5368 */ 'B', 'C', '1', '6', '_', 'M', 'M', 'R', '6', 0, |
| /* 5378 */ 'J', 'R', 'C', '1', '6', '_', 'M', 'M', 'R', '6', 0, |
| /* 5389 */ 'J', 'A', 'L', 'R', 'C', '1', '6', '_', 'M', 'M', 'R', '6', 0, |
| /* 5402 */ 'B', 'N', 'E', 'Z', 'C', '1', '6', '_', 'M', 'M', 'R', '6', 0, |
| /* 5415 */ 'B', 'E', 'Q', 'Z', 'C', '1', '6', '_', 'M', 'M', 'R', '6', 0, |
| /* 5428 */ 'A', 'N', 'D', '1', '6', '_', 'M', 'M', 'R', '6', 0, |
| /* 5439 */ 'M', 'O', 'V', 'E', '1', '6', '_', 'M', 'M', 'R', '6', 0, |
| /* 5451 */ 'S', 'H', '1', '6', '_', 'M', 'M', 'R', '6', 0, |
| /* 5461 */ 'A', 'N', 'D', 'I', '1', '6', '_', 'M', 'M', 'R', '6', 0, |
| /* 5473 */ 'L', 'I', '1', '6', '_', 'M', 'M', 'R', '6', 0, |
| /* 5483 */ 'B', 'R', 'E', 'A', 'K', '1', '6', '_', 'M', 'M', 'R', '6', 0, |
| /* 5496 */ 'S', 'L', 'L', '1', '6', '_', 'M', 'M', 'R', '6', 0, |
| /* 5507 */ 'S', 'R', 'L', '1', '6', '_', 'M', 'M', 'R', '6', 0, |
| /* 5518 */ 'L', 'W', 'M', '1', '6', '_', 'M', 'M', 'R', '6', 0, |
| /* 5529 */ 'S', 'W', 'M', '1', '6', '_', 'M', 'M', 'R', '6', 0, |
| /* 5540 */ 'S', 'D', 'B', 'B', 'P', '1', '6', '_', 'M', 'M', 'R', '6', 0, |
| /* 5553 */ 'X', 'O', 'R', '1', '6', '_', 'M', 'M', 'R', '6', 0, |
| /* 5564 */ 'N', 'O', 'T', '1', '6', '_', 'M', 'M', 'R', '6', 0, |
| /* 5575 */ 'S', 'U', 'B', 'U', '1', '6', '_', 'M', 'M', 'R', '6', 0, |
| /* 5587 */ 'A', 'D', 'D', 'U', '1', '6', '_', 'M', 'M', 'R', '6', 0, |
| /* 5599 */ 'S', 'W', '1', '6', '_', 'M', 'M', 'R', '6', 0, |
| /* 5609 */ 'L', 'S', 'A', '_', 'M', 'M', 'R', '6', 0, |
| /* 5618 */ 'E', 'H', 'B', '_', 'M', 'M', 'R', '6', 0, |
| /* 5627 */ 'J', 'A', 'L', 'R', 'C', '_', 'H', 'B', '_', 'M', 'M', 'R', '6', 0, |
| /* 5641 */ 'L', 'B', '_', 'M', 'M', 'R', '6', 0, |
| /* 5649 */ 'S', 'B', '_', 'M', 'M', 'R', '6', 0, |
| /* 5657 */ 'S', 'U', 'B', '_', 'M', 'M', 'R', '6', 0, |
| /* 5666 */ 'B', 'C', '_', 'M', 'M', 'R', '6', 0, |
| /* 5674 */ 'B', 'G', 'E', 'C', '_', 'M', 'M', 'R', '6', 0, |
| /* 5684 */ 'B', 'N', 'E', 'C', '_', 'M', 'M', 'R', '6', 0, |
| /* 5694 */ 'J', 'I', 'C', '_', 'M', 'M', 'R', '6', 0, |
| /* 5703 */ 'B', 'A', 'L', 'C', '_', 'M', 'M', 'R', '6', 0, |
| /* 5713 */ 'J', 'I', 'A', 'L', 'C', '_', 'M', 'M', 'R', '6', 0, |
| /* 5724 */ 'B', 'G', 'E', 'Z', 'A', 'L', 'C', '_', 'M', 'M', 'R', '6', 0, |
| /* 5737 */ 'B', 'L', 'E', 'Z', 'A', 'L', 'C', '_', 'M', 'M', 'R', '6', 0, |
| /* 5750 */ 'B', 'N', 'E', 'Z', 'A', 'L', 'C', '_', 'M', 'M', 'R', '6', 0, |
| /* 5763 */ 'B', 'E', 'Q', 'Z', 'A', 'L', 'C', '_', 'M', 'M', 'R', '6', 0, |
| /* 5776 */ 'B', 'G', 'T', 'Z', 'A', 'L', 'C', '_', 'M', 'M', 'R', '6', 0, |
| /* 5789 */ 'B', 'L', 'T', 'Z', 'A', 'L', 'C', '_', 'M', 'M', 'R', '6', 0, |
| /* 5802 */ 'E', 'R', 'E', 'T', 'N', 'C', '_', 'M', 'M', 'R', '6', 0, |
| /* 5814 */ 'S', 'Y', 'N', 'C', '_', 'M', 'M', 'R', '6', 0, |
| /* 5824 */ 'A', 'U', 'I', 'P', 'C', '_', 'M', 'M', 'R', '6', 0, |
| /* 5835 */ 'A', 'L', 'U', 'I', 'P', 'C', '_', 'M', 'M', 'R', '6', 0, |
| /* 5847 */ 'A', 'D', 'D', 'I', 'U', 'P', 'C', '_', 'M', 'M', 'R', '6', 0, |
| /* 5860 */ 'L', 'W', 'P', 'C', '_', 'M', 'M', 'R', '6', 0, |
| /* 5870 */ 'B', 'E', 'Q', 'C', '_', 'M', 'M', 'R', '6', 0, |
| /* 5880 */ 'J', 'A', 'L', 'R', 'C', '_', 'M', 'M', 'R', '6', 0, |
| /* 5891 */ 'S', 'C', '_', 'M', 'M', 'R', '6', 0, |
| /* 5899 */ 'B', 'L', 'T', 'C', '_', 'M', 'M', 'R', '6', 0, |
| /* 5909 */ 'B', 'G', 'E', 'U', 'C', '_', 'M', 'M', 'R', '6', 0, |
| /* 5920 */ 'B', 'L', 'T', 'U', 'C', '_', 'M', 'M', 'R', '6', 0, |
| /* 5931 */ 'B', 'N', 'V', 'C', '_', 'M', 'M', 'R', '6', 0, |
| /* 5941 */ 'B', 'O', 'V', 'C', '_', 'M', 'M', 'R', '6', 0, |
| /* 5951 */ 'B', 'G', 'E', 'Z', 'C', '_', 'M', 'M', 'R', '6', 0, |
| /* 5962 */ 'B', 'L', 'E', 'Z', 'C', '_', 'M', 'M', 'R', '6', 0, |
| /* 5973 */ 'B', 'C', '1', 'N', 'E', 'Z', 'C', '_', 'M', 'M', 'R', '6', 0, |
| /* 5986 */ 'B', 'C', '2', 'N', 'E', 'Z', 'C', '_', 'M', 'M', 'R', '6', 0, |
| /* 5999 */ 'B', 'N', 'E', 'Z', 'C', '_', 'M', 'M', 'R', '6', 0, |
| /* 6010 */ 'B', 'C', '1', 'E', 'Q', 'Z', 'C', '_', 'M', 'M', 'R', '6', 0, |
| /* 6023 */ 'B', 'C', '2', 'E', 'Q', 'Z', 'C', '_', 'M', 'M', 'R', '6', 0, |
| /* 6036 */ 'B', 'E', 'Q', 'Z', 'C', '_', 'M', 'M', 'R', '6', 0, |
| /* 6047 */ 'B', 'G', 'T', 'Z', 'C', '_', 'M', 'M', 'R', '6', 0, |
| /* 6058 */ 'B', 'L', 'T', 'Z', 'C', '_', 'M', 'M', 'R', '6', 0, |
| /* 6069 */ 'A', 'D', 'D', '_', 'M', 'M', 'R', '6', 0, |
| /* 6078 */ 'A', 'N', 'D', '_', 'M', 'M', 'R', '6', 0, |
| /* 6087 */ 'M', 'O', 'D', '_', 'M', 'M', 'R', '6', 0, |
| /* 6096 */ 'M', 'I', 'N', 'A', '_', 'D', '_', 'M', 'M', 'R', '6', 0, |
| /* 6108 */ 'M', 'A', 'X', 'A', '_', 'D', '_', 'M', 'M', 'R', '6', 0, |
| /* 6120 */ 'C', 'M', 'P', '_', 'S', 'L', 'E', '_', 'D', '_', 'M', 'M', 'R', '6', 0, |
| /* 6135 */ 'C', 'M', 'P', '_', 'S', 'U', 'L', 'E', '_', 'D', '_', 'M', 'M', 'R', '6', 0, |
| /* 6151 */ 'C', 'M', 'P', '_', 'U', 'L', 'E', '_', 'D', '_', 'M', 'M', 'R', '6', 0, |
| /* 6166 */ 'C', 'M', 'P', '_', 'L', 'E', '_', 'D', '_', 'M', 'M', 'R', '6', 0, |
| /* 6180 */ 'C', 'M', 'P', '_', 'S', 'A', 'F', '_', 'D', '_', 'M', 'M', 'R', '6', 0, |
| /* 6195 */ 'C', 'M', 'P', '_', 'A', 'F', '_', 'D', '_', 'M', 'M', 'R', '6', 0, |
| /* 6209 */ 'M', 'S', 'U', 'B', 'F', '_', 'D', '_', 'M', 'M', 'R', '6', 0, |
| /* 6222 */ 'M', 'A', 'D', 'D', 'F', '_', 'D', '_', 'M', 'M', 'R', '6', 0, |
| /* 6235 */ 'S', 'E', 'L', '_', 'D', '_', 'M', 'M', 'R', '6', 0, |
| /* 6246 */ 'T', 'R', 'U', 'N', 'C', '_', 'L', '_', 'D', '_', 'M', 'M', 'R', '6', 0, |
| /* 6261 */ 'R', 'O', 'U', 'N', 'D', '_', 'L', '_', 'D', '_', 'M', 'M', 'R', '6', 0, |
| /* 6276 */ 'C', 'E', 'I', 'L', '_', 'L', '_', 'D', '_', 'M', 'M', 'R', '6', 0, |
| /* 6290 */ 'F', 'L', 'O', 'O', 'R', '_', 'L', '_', 'D', '_', 'M', 'M', 'R', '6', 0, |
| /* 6305 */ 'C', 'V', 'T', '_', 'L', '_', 'D', '_', 'M', 'M', 'R', '6', 0, |
| /* 6318 */ 'M', 'I', 'N', '_', 'D', '_', 'M', 'M', 'R', '6', 0, |
| /* 6329 */ 'C', 'M', 'P', '_', 'S', 'U', 'N', '_', 'D', '_', 'M', 'M', 'R', '6', 0, |
| /* 6344 */ 'C', 'M', 'P', '_', 'U', 'N', '_', 'D', '_', 'M', 'M', 'R', '6', 0, |
| /* 6358 */ 'C', 'M', 'P', '_', 'S', 'E', 'Q', '_', 'D', '_', 'M', 'M', 'R', '6', 0, |
| /* 6373 */ 'C', 'M', 'P', '_', 'S', 'U', 'E', 'Q', '_', 'D', '_', 'M', 'M', 'R', '6', 0, |
| /* 6389 */ 'C', 'M', 'P', '_', 'U', 'E', 'Q', '_', 'D', '_', 'M', 'M', 'R', '6', 0, |
| /* 6404 */ 'C', 'M', 'P', '_', 'E', 'Q', '_', 'D', '_', 'M', 'M', 'R', '6', 0, |
| /* 6418 */ 'C', 'L', 'A', 'S', 'S', '_', 'D', '_', 'M', 'M', 'R', '6', 0, |
| /* 6431 */ 'C', 'M', 'P', '_', 'S', 'L', 'T', '_', 'D', '_', 'M', 'M', 'R', '6', 0, |
| /* 6446 */ 'C', 'M', 'P', '_', 'S', 'U', 'L', 'T', '_', 'D', '_', 'M', 'M', 'R', '6', 0, |
| /* 6462 */ 'C', 'M', 'P', '_', 'U', 'L', 'T', '_', 'D', '_', 'M', 'M', 'R', '6', 0, |
| /* 6477 */ 'C', 'M', 'P', '_', 'L', 'T', '_', 'D', '_', 'M', 'M', 'R', '6', 0, |
| /* 6491 */ 'R', 'I', 'N', 'T', '_', 'D', '_', 'M', 'M', 'R', '6', 0, |
| /* 6503 */ 'F', 'M', 'O', 'V', '_', 'D', '_', 'M', 'M', 'R', '6', 0, |
| /* 6515 */ 'T', 'R', 'U', 'N', 'C', '_', 'W', '_', 'D', '_', 'M', 'M', 'R', '6', 0, |
| /* 6530 */ 'R', 'O', 'U', 'N', 'D', '_', 'W', '_', 'D', '_', 'M', 'M', 'R', '6', 0, |
| /* 6545 */ 'C', 'E', 'I', 'L', '_', 'W', '_', 'D', '_', 'M', 'M', 'R', '6', 0, |
| /* 6559 */ 'F', 'L', 'O', 'O', 'R', '_', 'W', '_', 'D', '_', 'M', 'M', 'R', '6', 0, |
| /* 6574 */ 'M', 'A', 'X', '_', 'D', '_', 'M', 'M', 'R', '6', 0, |
| /* 6585 */ 'S', 'E', 'L', 'N', 'E', 'Z', '_', 'D', '_', 'M', 'M', 'R', '6', 0, |
| /* 6599 */ 'S', 'E', 'L', 'E', 'Q', 'Z', '_', 'D', '_', 'M', 'M', 'R', '6', 0, |
| /* 6613 */ 'C', 'A', 'C', 'H', 'E', '_', 'M', 'M', 'R', '6', 0, |
| /* 6624 */ 'S', 'I', 'G', 'R', 'I', 'E', '_', 'M', 'M', 'R', '6', 0, |
| /* 6636 */ 'P', 'A', 'U', 'S', 'E', '_', 'M', 'M', 'R', '6', 0, |
| /* 6647 */ 'P', 'R', 'E', 'F', '_', 'M', 'M', 'R', '6', 0, |
| /* 6657 */ 'T', 'L', 'B', 'I', 'N', 'V', 'F', '_', 'M', 'M', 'R', '6', 0, |
| /* 6670 */ 'T', 'A', 'I', 'L', 'C', 'A', 'L', 'L', 'R', 'E', 'G', '_', 'M', 'M', 'R', '6', 0, |
| /* 6687 */ 'W', 'S', 'B', 'H', '_', 'M', 'M', 'R', '6', 0, |
| /* 6697 */ 'S', 'H', '_', 'M', 'M', 'R', '6', 0, |
| /* 6705 */ 'M', 'U', 'H', '_', 'M', 'M', 'R', '6', 0, |
| /* 6714 */ 'S', 'Y', 'N', 'C', 'I', '_', 'M', 'M', 'R', '6', 0, |
| /* 6725 */ 'A', 'N', 'D', 'I', '_', 'M', 'M', 'R', '6', 0, |
| /* 6735 */ 'E', 'I', '_', 'M', 'M', 'R', '6', 0, |
| /* 6743 */ 'X', 'O', 'R', 'I', '_', 'M', 'M', 'R', '6', 0, |
| /* 6753 */ 'A', 'U', 'I', '_', 'M', 'M', 'R', '6', 0, |
| /* 6762 */ 'L', 'U', 'I', '_', 'M', 'M', 'R', '6', 0, |
| /* 6771 */ 'G', 'I', 'N', 'V', 'I', '_', 'M', 'M', 'R', '6', 0, |
| /* 6782 */ 'B', 'R', 'E', 'A', 'K', '_', 'M', 'M', 'R', '6', 0, |
| /* 6793 */ 'J', 'A', 'L', '_', 'M', 'M', 'R', '6', 0, |
| /* 6802 */ 'T', 'A', 'I', 'L', 'C', 'A', 'L', 'L', '_', 'M', 'M', 'R', '6', 0, |
| /* 6816 */ 'S', 'L', 'L', '_', 'M', 'M', 'R', '6', 0, |
| /* 6825 */ 'M', 'U', 'L', '_', 'M', 'M', 'R', '6', 0, |
| /* 6834 */ 'C', 'V', 'T', '_', 'D', '_', 'L', '_', 'M', 'M', 'R', '6', 0, |
| /* 6847 */ 'C', 'V', 'T', '_', 'S', '_', 'L', '_', 'M', 'M', 'R', '6', 0, |
| /* 6860 */ 'A', 'L', 'I', 'G', 'N', '_', 'M', 'M', 'R', '6', 0, |
| /* 6871 */ 'C', 'L', 'O', '_', 'M', 'M', 'R', '6', 0, |
| /* 6880 */ 'B', 'I', 'T', 'S', 'W', 'A', 'P', '_', 'M', 'M', 'R', '6', 0, |
| /* 6893 */ 'S', 'D', 'B', 'B', 'P', '_', 'M', 'M', 'R', '6', 0, |
| /* 6904 */ 'M', 'O', 'V', 'E', 'P', '_', 'M', 'M', 'R', '6', 0, |
| /* 6915 */ 'S', 'S', 'N', 'O', 'P', '_', 'M', 'M', 'R', '6', 0, |
| /* 6926 */ 'J', 'R', 'C', 'A', 'D', 'D', 'I', 'U', 'S', 'P', '_', 'M', 'M', 'R', '6', 0, |
| /* 6942 */ 'S', 'W', 'S', 'P', '_', 'M', 'M', 'R', '6', 0, |
| /* 6952 */ 'D', 'V', 'P', '_', 'M', 'M', 'R', '6', 0, |
| /* 6961 */ 'E', 'V', 'P', '_', 'M', 'M', 'R', '6', 0, |
| /* 6970 */ 'N', 'O', 'R', '_', 'M', 'M', 'R', '6', 0, |
| /* 6979 */ 'X', 'O', 'R', '_', 'M', 'M', 'R', '6', 0, |
| /* 6988 */ 'R', 'D', 'P', 'G', 'P', 'R', '_', 'M', 'M', 'R', '6', 0, |
| /* 7000 */ 'W', 'R', 'P', 'G', 'P', 'R', '_', 'M', 'M', 'R', '6', 0, |
| /* 7012 */ 'R', 'D', 'H', 'W', 'R', '_', 'M', 'M', 'R', '6', 0, |
| /* 7023 */ 'I', 'N', 'S', '_', 'M', 'M', 'R', '6', 0, |
| /* 7032 */ 'M', 'I', 'N', 'A', '_', 'S', '_', 'M', 'M', 'R', '6', 0, |
| /* 7044 */ 'M', 'A', 'X', 'A', '_', 'S', '_', 'M', 'M', 'R', '6', 0, |
| /* 7056 */ 'F', 'S', 'U', 'B', '_', 'S', '_', 'M', 'M', 'R', '6', 0, |
| /* 7068 */ 'F', 'A', 'D', 'D', '_', 'S', '_', 'M', 'M', 'R', '6', 0, |
| /* 7080 */ 'C', 'M', 'P', '_', 'S', 'L', 'E', '_', 'S', '_', 'M', 'M', 'R', '6', 0, |
| /* 7095 */ 'C', 'M', 'P', '_', 'S', 'U', 'L', 'E', '_', 'S', '_', 'M', 'M', 'R', '6', 0, |
| /* 7111 */ 'C', 'M', 'P', '_', 'U', 'L', 'E', '_', 'S', '_', 'M', 'M', 'R', '6', 0, |
| /* 7126 */ 'C', 'M', 'P', '_', 'L', 'E', '_', 'S', '_', 'M', 'M', 'R', '6', 0, |
| /* 7140 */ 'C', 'M', 'P', '_', 'S', 'A', 'F', '_', 'S', '_', 'M', 'M', 'R', '6', 0, |
| /* 7155 */ 'C', 'M', 'P', '_', 'A', 'F', '_', 'S', '_', 'M', 'M', 'R', '6', 0, |
| /* 7169 */ 'M', 'S', 'U', 'B', 'F', '_', 'S', '_', 'M', 'M', 'R', '6', 0, |
| /* 7182 */ 'M', 'A', 'D', 'D', 'F', '_', 'S', '_', 'M', 'M', 'R', '6', 0, |
| /* 7195 */ 'F', 'N', 'E', 'G', '_', 'S', '_', 'M', 'M', 'R', '6', 0, |
| /* 7207 */ 'S', 'E', 'L', '_', 'S', '_', 'M', 'M', 'R', '6', 0, |
| /* 7218 */ 'F', 'M', 'U', 'L', '_', 'S', '_', 'M', 'M', 'R', '6', 0, |
| /* 7230 */ 'T', 'R', 'U', 'N', 'C', '_', 'L', '_', 'S', '_', 'M', 'M', 'R', '6', 0, |
| /* 7245 */ 'R', 'O', 'U', 'N', 'D', '_', 'L', '_', 'S', '_', 'M', 'M', 'R', '6', 0, |
| /* 7260 */ 'C', 'E', 'I', 'L', '_', 'L', '_', 'S', '_', 'M', 'M', 'R', '6', 0, |
| /* 7274 */ 'F', 'L', 'O', 'O', 'R', '_', 'L', '_', 'S', '_', 'M', 'M', 'R', '6', 0, |
| /* 7289 */ 'C', 'V', 'T', '_', 'L', '_', 'S', '_', 'M', 'M', 'R', '6', 0, |
| /* 7302 */ 'M', 'I', 'N', '_', 'S', '_', 'M', 'M', 'R', '6', 0, |
| /* 7313 */ 'C', 'M', 'P', '_', 'S', 'U', 'N', '_', 'S', '_', 'M', 'M', 'R', '6', 0, |
| /* 7328 */ 'C', 'M', 'P', '_', 'U', 'N', '_', 'S', '_', 'M', 'M', 'R', '6', 0, |
| /* 7342 */ 'C', 'M', 'P', '_', 'S', 'E', 'Q', '_', 'S', '_', 'M', 'M', 'R', '6', 0, |
| /* 7357 */ 'C', 'M', 'P', '_', 'S', 'U', 'E', 'Q', '_', 'S', '_', 'M', 'M', 'R', '6', 0, |
| /* 7373 */ 'C', 'M', 'P', '_', 'U', 'E', 'Q', '_', 'S', '_', 'M', 'M', 'R', '6', 0, |
| /* 7388 */ 'C', 'M', 'P', '_', 'E', 'Q', '_', 'S', '_', 'M', 'M', 'R', '6', 0, |
| /* 7402 */ 'C', 'L', 'A', 'S', 'S', '_', 'S', '_', 'M', 'M', 'R', '6', 0, |
| /* 7415 */ 'C', 'M', 'P', '_', 'S', 'L', 'T', '_', 'S', '_', 'M', 'M', 'R', '6', 0, |
| /* 7430 */ 'C', 'M', 'P', '_', 'S', 'U', 'L', 'T', '_', 'S', '_', 'M', 'M', 'R', '6', 0, |
| /* 7446 */ 'C', 'M', 'P', '_', 'U', 'L', 'T', '_', 'S', '_', 'M', 'M', 'R', '6', 0, |
| /* 7461 */ 'C', 'M', 'P', '_', 'L', 'T', '_', 'S', '_', 'M', 'M', 'R', '6', 0, |
| /* 7475 */ 'R', 'I', 'N', 'T', '_', 'S', '_', 'M', 'M', 'R', '6', 0, |
| /* 7487 */ 'F', 'D', 'I', 'V', '_', 'S', '_', 'M', 'M', 'R', '6', 0, |
| /* 7499 */ 'F', 'M', 'O', 'V', '_', 'S', '_', 'M', 'M', 'R', '6', 0, |
| /* 7511 */ 'T', 'R', 'U', 'N', 'C', '_', 'W', '_', 'S', '_', 'M', 'M', 'R', '6', 0, |
| /* 7526 */ 'R', 'O', 'U', 'N', 'D', '_', 'W', '_', 'S', '_', 'M', 'M', 'R', '6', 0, |
| /* 7541 */ 'C', 'E', 'I', 'L', '_', 'W', '_', 'S', '_', 'M', 'M', 'R', '6', 0, |
| /* 7555 */ 'F', 'L', 'O', 'O', 'R', '_', 'W', '_', 'S', '_', 'M', 'M', 'R', '6', 0, |
| /* 7570 */ 'C', 'V', 'T', '_', 'W', '_', 'S', '_', 'M', 'M', 'R', '6', 0, |
| /* 7583 */ 'M', 'A', 'X', '_', 'S', '_', 'M', 'M', 'R', '6', 0, |
| /* 7594 */ 'S', 'E', 'L', 'N', 'E', 'Z', '_', 'S', '_', 'M', 'M', 'R', '6', 0, |
| /* 7608 */ 'S', 'E', 'L', 'E', 'Q', 'Z', '_', 'S', '_', 'M', 'M', 'R', '6', 0, |
| /* 7622 */ 'D', 'E', 'R', 'E', 'T', '_', 'M', 'M', 'R', '6', 0, |
| /* 7633 */ 'W', 'A', 'I', 'T', '_', 'M', 'M', 'R', '6', 0, |
| /* 7643 */ 'G', 'I', 'N', 'V', 'T', '_', 'M', 'M', 'R', '6', 0, |
| /* 7654 */ 'E', 'X', 'T', '_', 'M', 'M', 'R', '6', 0, |
| /* 7663 */ 'L', 'B', 'U', '_', 'M', 'M', 'R', '6', 0, |
| /* 7672 */ 'S', 'U', 'B', 'U', '_', 'M', 'M', 'R', '6', 0, |
| /* 7682 */ 'A', 'D', 'D', 'U', '_', 'M', 'M', 'R', '6', 0, |
| /* 7692 */ 'M', 'O', 'D', 'U', '_', 'M', 'M', 'R', '6', 0, |
| /* 7702 */ 'M', 'U', 'H', 'U', '_', 'M', 'M', 'R', '6', 0, |
| /* 7712 */ 'A', 'D', 'D', 'I', 'U', '_', 'M', 'M', 'R', '6', 0, |
| /* 7723 */ 'M', 'U', 'L', 'U', '_', 'M', 'M', 'R', '6', 0, |
| /* 7733 */ 'D', 'I', 'V', 'U', '_', 'M', 'M', 'R', '6', 0, |
| /* 7743 */ 'D', 'I', 'V', '_', 'M', 'M', 'R', '6', 0, |
| /* 7752 */ 'T', 'L', 'B', 'I', 'N', 'V', '_', 'M', 'M', 'R', '6', 0, |
| /* 7764 */ 'L', 'W', '_', 'M', 'M', 'R', '6', 0, |
| /* 7772 */ 'S', 'W', '_', 'M', 'M', 'R', '6', 0, |
| /* 7780 */ 'C', 'V', 'T', '_', 'S', '_', 'W', '_', 'M', 'M', 'R', '6', 0, |
| /* 7793 */ 'S', 'E', 'L', 'N', 'E', 'Z', '_', 'M', 'M', 'R', '6', 0, |
| /* 7805 */ 'C', 'L', 'Z', '_', 'M', 'M', 'R', '6', 0, |
| /* 7814 */ 'S', 'E', 'L', 'E', 'Q', 'Z', '_', 'M', 'M', 'R', '6', 0, |
| /* 7826 */ 'P', 's', 'e', 'u', 'd', 'o', 'I', 'n', 'd', 'i', 'r', 'e', 'c', 't', 'B', 'r', 'a', 'n', 'c', 'h', '_', 'M', 'M', 'R', '6', 0, |
| /* 7852 */ 'L', 'D', 'C', '2', '_', 'R', '6', 0, |
| /* 7860 */ 'S', 'D', 'C', '2', '_', 'R', '6', 0, |
| /* 7868 */ 'L', 'W', 'C', '2', '_', 'R', '6', 0, |
| /* 7876 */ 'S', 'W', 'C', '2', '_', 'R', '6', 0, |
| /* 7884 */ 'J', 'R', '_', 'H', 'B', '6', '4', '_', 'R', '6', 0, |
| /* 7895 */ 'S', 'C', '6', '4', '_', 'R', '6', 0, |
| /* 7903 */ 'L', 'L', '6', '4', '_', 'R', '6', 0, |
| /* 7911 */ 'D', 'L', 'S', 'A', '_', 'R', '6', 0, |
| /* 7919 */ 'J', 'R', '_', 'H', 'B', '_', 'R', '6', 0, |
| /* 7928 */ 'S', 'C', '_', 'R', '6', 0, |
| /* 7934 */ 'S', 'C', 'D', '_', 'R', '6', 0, |
| /* 7941 */ 'L', 'L', 'D', '_', 'R', '6', 0, |
| /* 7948 */ 'C', 'A', 'C', 'H', 'E', '_', 'R', '6', 0, |
| /* 7957 */ 'P', 'R', 'E', 'F', '_', 'R', '6', 0, |
| /* 7965 */ 'L', 'L', '_', 'R', '6', 0, |
| /* 7971 */ 'D', 'M', 'U', 'L', '_', 'R', '6', 0, |
| /* 7979 */ 'D', 'C', 'L', 'O', '_', 'R', '6', 0, |
| /* 7987 */ 'S', 'D', 'B', 'B', 'P', '_', 'R', '6', 0, |
| /* 7996 */ 'D', 'C', 'L', 'Z', '_', 'R', '6', 0, |
| /* 8004 */ 'P', 's', 'e', 'u', 'd', 'o', 'I', 'n', 'd', 'r', 'e', 'c', 't', 'H', 'a', 'z', 'a', 'r', 'd', 'B', 'r', 'a', 'n', 'c', 'h', 'R', '6', 0, |
| /* 8032 */ 'P', 's', 'e', 'u', 'd', 'o', 'I', 'n', 'd', 'i', 'r', 'e', 'c', 't', 'B', 'r', 'a', 'n', 'c', 'h', 'R', '6', 0, |
| /* 8055 */ 'L', 'O', 'A', 'D', '_', 'A', 'C', 'C', '1', '2', '8', 0, |
| /* 8067 */ 'S', 'T', 'O', 'R', 'E', '_', 'A', 'C', 'C', '1', '2', '8', 0, |
| /* 8080 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'S', 'U', 'B', '_', 'I', '8', 0, |
| /* 8099 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'A', 'D', 'D', '_', 'I', '8', 0, |
| /* 8118 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'N', 'A', 'N', 'D', '_', 'I', '8', 0, |
| /* 8138 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'A', 'N', 'D', '_', 'I', '8', 0, |
| /* 8157 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'U', 'M', 'I', 'N', '_', 'I', '8', 0, |
| /* 8177 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'M', 'I', 'N', '_', 'I', '8', 0, |
| /* 8196 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'S', 'W', 'A', 'P', '_', 'I', '8', 0, |
| /* 8211 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'C', 'M', 'P', '_', 'S', 'W', 'A', 'P', '_', 'I', '8', 0, |
| /* 8230 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'X', 'O', 'R', '_', 'I', '8', 0, |
| /* 8249 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'O', 'R', '_', 'I', '8', 0, |
| /* 8267 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'U', 'M', 'A', 'X', '_', 'I', '8', 0, |
| /* 8287 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'M', 'A', 'X', '_', 'I', '8', 0, |
| /* 8306 */ 'S', 'A', 'A', 0, |
| /* 8310 */ 'P', 'R', 'E', 'C', 'E', 'U', '_', 'P', 'H', '_', 'Q', 'B', 'L', 'A', 0, |
| /* 8325 */ 'P', 'R', 'E', 'C', 'E', 'Q', 'U', '_', 'P', 'H', '_', 'Q', 'B', 'L', 'A', 0, |
| /* 8341 */ 'G', '_', 'F', 'M', 'A', 0, |
| /* 8347 */ 'P', 'R', 'E', 'C', 'E', 'U', '_', 'P', 'H', '_', 'Q', 'B', 'R', 'A', 0, |
| /* 8362 */ 'P', 'R', 'E', 'C', 'E', 'Q', 'U', '_', 'P', 'H', '_', 'Q', 'B', 'R', 'A', 0, |
| /* 8378 */ 'D', 'S', 'R', 'A', 0, |
| /* 8383 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'S', 'U', 'B', '_', 'I', '3', '2', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0, |
| /* 8410 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'A', 'D', 'D', '_', 'I', '3', '2', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0, |
| /* 8437 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'N', 'A', 'N', 'D', '_', 'I', '3', '2', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0, |
| /* 8465 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'A', 'N', 'D', '_', 'I', '3', '2', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0, |
| /* 8492 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'U', 'M', 'I', 'N', '_', 'I', '3', '2', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0, |
| /* 8520 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'M', 'I', 'N', '_', 'I', '3', '2', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0, |
| /* 8547 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'S', 'W', 'A', 'P', '_', 'I', '3', '2', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0, |
| /* 8570 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'C', 'M', 'P', '_', 'S', 'W', 'A', 'P', '_', 'I', '3', '2', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0, |
| /* 8597 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'X', 'O', 'R', '_', 'I', '3', '2', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0, |
| /* 8624 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'O', 'R', '_', 'I', '3', '2', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0, |
| /* 8650 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'U', 'M', 'A', 'X', '_', 'I', '3', '2', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0, |
| /* 8678 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'M', 'A', 'X', '_', 'I', '3', '2', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0, |
| /* 8705 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'S', 'U', 'B', '_', 'I', '6', '4', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0, |
| /* 8732 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'A', 'D', 'D', '_', 'I', '6', '4', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0, |
| /* 8759 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'N', 'A', 'N', 'D', '_', 'I', '6', '4', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0, |
| /* 8787 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'A', 'N', 'D', '_', 'I', '6', '4', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0, |
| /* 8814 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'U', 'M', 'I', 'N', '_', 'I', '6', '4', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0, |
| /* 8842 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'M', 'I', 'N', '_', 'I', '6', '4', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0, |
| /* 8869 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'S', 'W', 'A', 'P', '_', 'I', '6', '4', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0, |
| /* 8892 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'C', 'M', 'P', '_', 'S', 'W', 'A', 'P', '_', 'I', '6', '4', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0, |
| /* 8919 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'X', 'O', 'R', '_', 'I', '6', '4', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0, |
| /* 8946 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'O', 'R', '_', 'I', '6', '4', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0, |
| /* 8972 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'U', 'M', 'A', 'X', '_', 'I', '6', '4', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0, |
| /* 9000 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'M', 'A', 'X', '_', 'I', '6', '4', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0, |
| /* 9027 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'S', 'U', 'B', '_', 'I', '1', '6', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0, |
| /* 9054 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'A', 'D', 'D', '_', 'I', '1', '6', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0, |
| /* 9081 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'N', 'A', 'N', 'D', '_', 'I', '1', '6', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0, |
| /* 9109 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'A', 'N', 'D', '_', 'I', '1', '6', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0, |
| /* 9136 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'U', 'M', 'I', 'N', '_', 'I', '1', '6', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0, |
| /* 9164 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'M', 'I', 'N', '_', 'I', '1', '6', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0, |
| /* 9191 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'S', 'W', 'A', 'P', '_', 'I', '1', '6', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0, |
| /* 9214 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'C', 'M', 'P', '_', 'S', 'W', 'A', 'P', '_', 'I', '1', '6', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0, |
| /* 9241 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'X', 'O', 'R', '_', 'I', '1', '6', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0, |
| /* 9268 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'O', 'R', '_', 'I', '1', '6', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0, |
| /* 9294 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'U', 'M', 'A', 'X', '_', 'I', '1', '6', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0, |
| /* 9322 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'M', 'A', 'X', '_', 'I', '1', '6', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0, |
| /* 9349 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'S', 'U', 'B', '_', 'I', '8', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0, |
| /* 9375 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'A', 'D', 'D', '_', 'I', '8', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0, |
| /* 9401 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'N', 'A', 'N', 'D', '_', 'I', '8', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0, |
| /* 9428 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'A', 'N', 'D', '_', 'I', '8', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0, |
| /* 9454 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'U', 'M', 'I', 'N', '_', 'I', '8', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0, |
| /* 9481 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'M', 'I', 'N', '_', 'I', '8', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0, |
| /* 9507 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'S', 'W', 'A', 'P', '_', 'I', '8', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0, |
| /* 9529 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'C', 'M', 'P', '_', 'S', 'W', 'A', 'P', '_', 'I', '8', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0, |
| /* 9555 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'X', 'O', 'R', '_', 'I', '8', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0, |
| /* 9581 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'O', 'R', '_', 'I', '8', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0, |
| /* 9606 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'U', 'M', 'A', 'X', '_', 'I', '8', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0, |
| /* 9633 */ 'A', 'T', 'O', 'M', 'I', 'C', '_', 'L', 'O', 'A', 'D', '_', 'M', 'A', 'X', '_', 'I', '8', '_', 'P', 'O', 'S', 'T', 'R', 'A', 0, |
| /* 9659 */ 'R', 'e', 't', 'R', 'A', 0, |
| /* 9665 */ 'D', 'L', 'S', 'A', 0, |
| /* 9670 */ 'C', 'F', 'C', 'M', 'S', 'A', 0, |
| /* 9677 */ 'C', 'T', 'C', 'M', 'S', 'A', 0, |
| /* 9684 */ 'C', 'R', 'C', '3', '2', 'B', 0, |
| /* 9691 */ 'C', 'R', 'C', '3', '2', 'C', 'B', 0, |
| /* 9699 */ 'S', 'E', 'B', 0, |
| /* 9703 */ 'E', 'H', 'B', 0, |
| /* 9707 */ 'T', 'A', 'I', 'L', 'C', 'A', 'L', 'L', 'R', 'E', 'G', 'H', 'B', 0, |
| /* 9721 */ 'J', 'R', '_', 'H', 'B', 0, |
| /* 9727 */ 'J', 'A', 'L', 'R', '_', 'H', 'B', 0, |
| /* 9735 */ 'L', 'B', 0, |
| /* 9738 */ 'S', 'H', 'R', 'A', '_', 'Q', 'B', 0, |
| /* 9746 */ 'C', 'M', 'P', 'G', 'D', 'U', '_', 'L', 'E', '_', 'Q', 'B', 0, |
| /* 9759 */ 'C', 'M', 'P', 'G', 'U', '_', 'L', 'E', '_', 'Q', 'B', 0, |
| /* 9771 */ 'P', 's', 'e', 'u', 'd', 'o', 'C', 'M', 'P', 'U', '_', 'L', 'E', '_', 'Q', 'B', 0, |
| /* 9788 */ 'S', 'U', 'B', 'U', 'H', '_', 'Q', 'B', 0, |
| /* 9797 */ 'A', 'D', 'D', 'U', 'H', '_', 'Q', 'B', 0, |
| /* 9806 */ 'P', 's', 'e', 'u', 'd', 'o', 'P', 'I', 'C', 'K', '_', 'Q', 'B', 0, |
| /* 9820 */ 'S', 'H', 'L', 'L', '_', 'Q', 'B', 0, |
| /* 9828 */ 'R', 'E', 'P', 'L', '_', 'Q', 'B', 0, |
| /* 9836 */ 'S', 'H', 'R', 'L', '_', 'Q', 'B', 0, |
| /* 9844 */ 'C', 'M', 'P', 'G', 'D', 'U', '_', 'E', 'Q', '_', 'Q', 'B', 0, |
| /* 9857 */ 'C', 'M', 'P', 'G', 'U', '_', 'E', 'Q', '_', 'Q', 'B', 0, |
| /* 9869 */ 'P', 's', 'e', 'u', 'd', 'o', 'C', 'M', 'P', 'U', '_', 'E', 'Q', '_', 'Q', 'B', 0, |
| /* 9886 */ 'S', 'H', 'R', 'A', '_', 'R', '_', 'Q', 'B', 0, |
| /* 9896 */ 'S', 'U', 'B', 'U', 'H', '_', 'R', '_', 'Q', 'B', 0, |
| /* 9907 */ 'A', 'D', 'D', 'U', 'H', '_', 'R', '_', 'Q', 'B', 0, |
| /* 9918 */ 'S', 'H', 'R', 'A', 'V', '_', 'R', '_', 'Q', 'B', 0, |
| /* 9929 */ 'A', 'B', 'S', 'Q', '_', 'S', '_', 'Q', 'B', 0, |
| /* 9939 */ 'S', 'U', 'B', 'U', '_', 'S', '_', 'Q', 'B', 0, |
| /* 9949 */ 'A', 'D', 'D', 'U', '_', 'S', '_', 'Q', 'B', 0, |
| /* 9959 */ 'C', 'M', 'P', 'G', 'D', 'U', '_', 'L', 'T', '_', 'Q', 'B', 0, |
| /* 9972 */ 'C', 'M', 'P', 'G', 'U', '_', 'L', 'T', '_', 'Q', 'B', 0, |
| /* 9984 */ 'P', 's', 'e', 'u', 'd', 'o', 'C', 'M', 'P', 'U', '_', 'L', 'T', '_', 'Q', 'B', 0, |
| /* 10001 */ 'S', 'U', 'B', 'U', '_', 'Q', 'B', 0, |
| /* 10009 */ 'A', 'D', 'D', 'U', '_', 'Q', 'B', 0, |
| /* 10017 */ 'S', 'H', 'R', 'A', 'V', '_', 'Q', 'B', 0, |
| /* 10026 */ 'S', 'H', 'L', 'L', 'V', '_', 'Q', 'B', 0, |
| /* 10035 */ 'R', 'E', 'P', 'L', 'V', '_', 'Q', 'B', 0, |
| /* 10044 */ 'S', 'H', 'R', 'L', 'V', '_', 'Q', 'B', 0, |
| /* 10053 */ 'R', 'A', 'D', 'D', 'U', '_', 'W', '_', 'Q', 'B', 0, |
| /* 10064 */ 'S', 'B', 0, |
| /* 10067 */ 'M', 'O', 'D', 'S', 'U', 'B', 0, |
| /* 10074 */ 'G', '_', 'F', 'S', 'U', 'B', 0, |
| /* 10081 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'F', 'S', 'U', 'B', 0, |
| /* 10098 */ 'P', 's', 'e', 'u', 'd', 'o', 'M', 'S', 'U', 'B', 0, |
| /* 10109 */ 'G', '_', 'S', 'U', 'B', 0, |
| /* 10115 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'S', 'U', 'B', 0, |
| /* 10131 */ 'S', 'R', 'A', '_', 'B', 0, |
| /* 10137 */ 'A', 'D', 'D', '_', 'A', '_', 'B', 0, |
| /* 10145 */ 'M', 'I', 'N', '_', 'A', '_', 'B', 0, |
| /* 10153 */ 'A', 'D', 'D', 'S', '_', 'A', '_', 'B', 0, |
| /* 10162 */ 'M', 'A', 'X', '_', 'A', '_', 'B', 0, |
| /* 10170 */ 'N', 'L', 'O', 'C', '_', 'B', 0, |
| /* 10177 */ 'N', 'L', 'Z', 'C', '_', 'B', 0, |
| /* 10184 */ 'S', 'L', 'D', '_', 'B', 0, |
| /* 10190 */ 'P', 'C', 'K', 'O', 'D', '_', 'B', 0, |
| /* 10198 */ 'I', 'L', 'V', 'O', 'D', '_', 'B', 0, |
| /* 10206 */ 'I', 'N', 'S', 'V', 'E', '_', 'B', 0, |
| /* 10214 */ 'V', 'S', 'H', 'F', '_', 'B', 0, |
| /* 10221 */ 'B', 'N', 'E', 'G', '_', 'B', 0, |
| /* 10228 */ 'S', 'R', 'A', 'I', '_', 'B', 0, |
| /* 10235 */ 'S', 'L', 'D', 'I', '_', 'B', 0, |
| /* 10242 */ 'A', 'N', 'D', 'I', '_', 'B', 0, |
| /* 10249 */ 'B', 'N', 'E', 'G', 'I', '_', 'B', 0, |
| /* 10257 */ 'B', 'S', 'E', 'L', 'I', '_', 'B', 0, |
| /* 10265 */ 'S', 'L', 'L', 'I', '_', 'B', 0, |
| /* 10272 */ 'S', 'R', 'L', 'I', '_', 'B', 0, |
| /* 10279 */ 'B', 'I', 'N', 'S', 'L', 'I', '_', 'B', 0, |
| /* 10288 */ 'C', 'E', 'Q', 'I', '_', 'B', 0, |
| /* 10295 */ 'S', 'R', 'A', 'R', 'I', '_', 'B', 0, |
| /* 10303 */ 'B', 'C', 'L', 'R', 'I', '_', 'B', 0, |
| /* 10311 */ 'S', 'R', 'L', 'R', 'I', '_', 'B', 0, |
| /* 10319 */ 'N', 'O', 'R', 'I', '_', 'B', 0, |
| /* 10326 */ 'X', 'O', 'R', 'I', '_', 'B', 0, |
| /* 10333 */ 'B', 'I', 'N', 'S', 'R', 'I', '_', 'B', 0, |
| /* 10342 */ 'S', 'P', 'L', 'A', 'T', 'I', '_', 'B', 0, |
| /* 10351 */ 'B', 'S', 'E', 'T', 'I', '_', 'B', 0, |
| /* 10359 */ 'S', 'U', 'B', 'V', 'I', '_', 'B', 0, |
| /* 10367 */ 'A', 'D', 'D', 'V', 'I', '_', 'B', 0, |
| /* 10375 */ 'B', 'M', 'Z', 'I', '_', 'B', 0, |
| /* 10382 */ 'B', 'M', 'N', 'Z', 'I', '_', 'B', 0, |
| /* 10390 */ 'F', 'I', 'L', 'L', '_', 'B', 0, |
| /* 10397 */ 'S', 'L', 'L', '_', 'B', 0, |
| /* 10403 */ 'S', 'R', 'L', '_', 'B', 0, |
| /* 10409 */ 'B', 'I', 'N', 'S', 'L', '_', 'B', 0, |
| /* 10417 */ 'I', 'L', 'V', 'L', '_', 'B', 0, |
| /* 10424 */ 'C', 'E', 'Q', '_', 'B', 0, |
| /* 10430 */ 'S', 'R', 'A', 'R', '_', 'B', 0, |
| /* 10437 */ 'B', 'C', 'L', 'R', '_', 'B', 0, |
| /* 10444 */ 'S', 'R', 'L', 'R', '_', 'B', 0, |
| /* 10451 */ 'B', 'I', 'N', 'S', 'R', '_', 'B', 0, |
| /* 10459 */ 'I', 'L', 'V', 'R', '_', 'B', 0, |
| /* 10466 */ 'A', 'S', 'U', 'B', '_', 'S', '_', 'B', 0, |
| /* 10475 */ 'M', 'O', 'D', '_', 'S', '_', 'B', 0, |
| /* 10483 */ 'C', 'L', 'E', '_', 'S', '_', 'B', 0, |
| /* 10491 */ 'A', 'V', 'E', '_', 'S', '_', 'B', 0, |
| /* 10499 */ 'C', 'L', 'E', 'I', '_', 'S', '_', 'B', 0, |
| /* 10508 */ 'M', 'I', 'N', 'I', '_', 'S', '_', 'B', 0, |
| /* 10517 */ 'C', 'L', 'T', 'I', '_', 'S', '_', 'B', 0, |
| /* 10526 */ 'M', 'A', 'X', 'I', '_', 'S', '_', 'B', 0, |
| /* 10535 */ 'M', 'I', 'N', '_', 'S', '_', 'B', 0, |
| /* 10543 */ 'A', 'V', 'E', 'R', '_', 'S', '_', 'B', 0, |
| /* 10552 */ 'S', 'U', 'B', 'S', '_', 'S', '_', 'B', 0, |
| /* 10561 */ 'A', 'D', 'D', 'S', '_', 'S', '_', 'B', 0, |
| /* 10570 */ 'S', 'A', 'T', '_', 'S', '_', 'B', 0, |
| /* 10578 */ 'C', 'L', 'T', '_', 'S', '_', 'B', 0, |
| /* 10586 */ 'S', 'U', 'B', 'S', 'U', 'U', '_', 'S', '_', 'B', 0, |
| /* 10597 */ 'D', 'I', 'V', '_', 'S', '_', 'B', 0, |
| /* 10605 */ 'M', 'A', 'X', '_', 'S', '_', 'B', 0, |
| /* 10613 */ 'C', 'O', 'P', 'Y', '_', 'S', '_', 'B', 0, |
| /* 10622 */ 'S', 'P', 'L', 'A', 'T', '_', 'B', 0, |
| /* 10630 */ 'B', 'S', 'E', 'T', '_', 'B', 0, |
| /* 10637 */ 'P', 'C', 'N', 'T', '_', 'B', 0, |
| /* 10644 */ 'I', 'N', 'S', 'E', 'R', 'T', '_', 'B', 0, |
| /* 10653 */ 'S', 'T', '_', 'B', 0, |
| /* 10658 */ 'A', 'S', 'U', 'B', '_', 'U', '_', 'B', 0, |
| /* 10667 */ 'M', 'O', 'D', '_', 'U', '_', 'B', 0, |
| /* 10675 */ 'C', 'L', 'E', '_', 'U', '_', 'B', 0, |
| /* 10683 */ 'A', 'V', 'E', '_', 'U', '_', 'B', 0, |
| /* 10691 */ 'C', 'L', 'E', 'I', '_', 'U', '_', 'B', 0, |
| /* 10700 */ 'M', 'I', 'N', 'I', '_', 'U', '_', 'B', 0, |
| /* 10709 */ 'C', 'L', 'T', 'I', '_', 'U', '_', 'B', 0, |
| /* 10718 */ 'M', 'A', 'X', 'I', '_', 'U', '_', 'B', 0, |
| /* 10727 */ 'M', 'I', 'N', '_', 'U', '_', 'B', 0, |
| /* 10735 */ 'A', 'V', 'E', 'R', '_', 'U', '_', 'B', 0, |
| /* 10744 */ 'S', 'U', 'B', 'S', '_', 'U', '_', 'B', 0, |
| /* 10753 */ 'A', 'D', 'D', 'S', '_', 'U', '_', 'B', 0, |
| /* 10762 */ 'S', 'U', 'B', 'S', 'U', 'S', '_', 'U', '_', 'B', 0, |
| /* 10773 */ 'S', 'A', 'T', '_', 'U', '_', 'B', 0, |
| /* 10781 */ 'C', 'L', 'T', '_', 'U', '_', 'B', 0, |
| /* 10789 */ 'D', 'I', 'V', '_', 'U', '_', 'B', 0, |
| /* 10797 */ 'M', 'A', 'X', '_', 'U', '_', 'B', 0, |
| /* 10805 */ 'C', 'O', 'P', 'Y', '_', 'U', '_', 'B', 0, |
| /* 10814 */ 'M', 'S', 'U', 'B', 'V', '_', 'B', 0, |
| /* 10822 */ 'M', 'A', 'D', 'D', 'V', '_', 'B', 0, |
| /* 10830 */ 'P', 'C', 'K', 'E', 'V', '_', 'B', 0, |
| /* 10838 */ 'I', 'L', 'V', 'E', 'V', '_', 'B', 0, |
| /* 10846 */ 'M', 'U', 'L', 'V', '_', 'B', 0, |
| /* 10853 */ 'B', 'Z', '_', 'B', 0, |
| /* 10858 */ 'B', 'N', 'Z', '_', 'B', 0, |
| /* 10864 */ 'B', 'C', 0, |
| /* 10867 */ 'B', 'G', 'E', 'C', 0, |
| /* 10872 */ 'B', 'N', 'E', 'C', 0, |
| /* 10877 */ 'J', 'I', 'C', 0, |
| /* 10881 */ 'G', '_', 'I', 'N', 'T', 'R', 'I', 'N', 'S', 'I', 'C', 0, |
| /* 10893 */ 'B', 'A', 'L', 'C', 0, |
| /* 10898 */ 'J', 'I', 'A', 'L', 'C', 0, |
| /* 10904 */ 'B', 'G', 'E', 'Z', 'A', 'L', 'C', 0, |
| /* 10912 */ 'B', 'L', 'E', 'Z', 'A', 'L', 'C', 0, |
| /* 10920 */ 'B', 'N', 'E', 'Z', 'A', 'L', 'C', 0, |
| /* 10928 */ 'B', 'E', 'Q', 'Z', 'A', 'L', 'C', 0, |
| /* 10936 */ 'B', 'G', 'T', 'Z', 'A', 'L', 'C', 0, |
| /* 10944 */ 'B', 'L', 'T', 'Z', 'A', 'L', 'C', 0, |
| /* 10952 */ 'E', 'R', 'E', 'T', 'N', 'C', 0, |
| /* 10959 */ 'G', '_', 'F', 'P', 'T', 'R', 'U', 'N', 'C', 0, |
| /* 10969 */ 'G', '_', 'I', 'N', 'T', 'R', 'I', 'N', 'S', 'I', 'C', '_', 'T', 'R', 'U', 'N', 'C', 0, |
| /* 10987 */ 'G', '_', 'T', 'R', 'U', 'N', 'C', 0, |
| /* 10995 */ 'G', '_', 'B', 'U', 'I', 'L', 'D', '_', 'V', 'E', 'C', 'T', 'O', 'R', '_', 'T', 'R', 'U', 'N', 'C', 0, |
| /* 11016 */ 'S', 'Y', 'N', 'C', 0, |
| /* 11021 */ 'G', '_', 'D', 'Y', 'N', '_', 'S', 'T', 'A', 'C', 'K', 'A', 'L', 'L', 'O', 'C', 0, |
| /* 11038 */ 'L', 'D', 'P', 'C', 0, |
| /* 11043 */ 'A', 'U', 'I', 'P', 'C', 0, |
| /* 11049 */ 'A', 'L', 'U', 'I', 'P', 'C', 0, |
| /* 11056 */ 'A', 'D', 'D', 'I', 'U', 'P', 'C', 0, |
| /* 11064 */ 'L', 'W', 'U', 'P', 'C', 0, |
| /* 11070 */ 'L', 'W', 'P', 'C', 0, |
| /* 11075 */ 'B', 'E', 'Q', 'C', 0, |
| /* 11080 */ 'A', 'D', 'D', 'S', 'C', 0, |
| /* 11086 */ 'B', 'L', 'T', 'C', 0, |
| /* 11091 */ 'B', 'G', 'E', 'U', 'C', 0, |
| /* 11097 */ 'B', 'L', 'T', 'U', 'C', 0, |
| /* 11103 */ 'B', 'N', 'V', 'C', 0, |
| /* 11108 */ 'B', 'O', 'V', 'C', 0, |
| /* 11113 */ 'A', 'D', 'D', 'W', 'C', 0, |
| /* 11119 */ 'B', 'G', 'E', 'Z', 'C', 0, |
| /* 11125 */ 'B', 'L', 'E', 'Z', 'C', 0, |
| /* 11131 */ 'B', 'N', 'E', 'Z', 'C', 0, |
| /* 11137 */ 'B', 'E', 'Q', 'Z', 'C', 0, |
| /* 11143 */ 'B', 'G', 'T', 'Z', 'C', 0, |
| /* 11149 */ 'B', 'L', 'T', 'Z', 'C', 0, |
| /* 11155 */ 'C', 'R', 'C', '3', '2', 'D', 0, |
| /* 11162 */ 'S', 'A', 'A', 'D', 0, |
| /* 11167 */ 'G', '_', 'F', 'M', 'A', 'D', 0, |
| /* 11174 */ 'G', '_', 'I', 'N', 'D', 'E', 'X', 'E', 'D', '_', 'S', 'E', 'X', 'T', 'L', 'O', 'A', 'D', 0, |
| /* 11193 */ 'G', '_', 'S', 'E', 'X', 'T', 'L', 'O', 'A', 'D', 0, |
| /* 11204 */ 'G', '_', 'I', 'N', 'D', 'E', 'X', 'E', 'D', '_', 'Z', 'E', 'X', 'T', 'L', 'O', 'A', 'D', 0, |
| /* 11223 */ 'G', '_', 'Z', 'E', 'X', 'T', 'L', 'O', 'A', 'D', 0, |
| /* 11234 */ 'G', '_', 'I', 'N', 'D', 'E', 'X', 'E', 'D', '_', 'L', 'O', 'A', 'D', 0, |
| /* 11249 */ 'G', '_', 'L', 'O', 'A', 'D', 0, |
| /* 11256 */ 'C', 'R', 'C', '3', '2', 'C', 'D', 0, |
| /* 11264 */ 'S', 'C', 'D', 0, |
| /* 11268 */ 'D', 'A', 'D', 'D', 0, |
| /* 11273 */ 'G', '_', 'F', 'A', 'D', 'D', 0, |
| /* 11280 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'F', 'A', 'D', 'D', 0, |
| /* 11297 */ 'P', 's', 'e', 'u', 'd', 'o', 'M', 'A', 'D', 'D', 0, |
| /* 11308 */ 'G', '_', 'A', 'D', 'D', 0, |
| /* 11314 */ 'G', '_', 'P', 'T', 'R', '_', 'A', 'D', 'D', 0, |
| /* 11324 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'A', 'D', 'D', 0, |
| /* 11340 */ 'D', 'S', 'H', 'D', 0, |
| /* 11345 */ 'Y', 'I', 'E', 'L', 'D', 0, |
| /* 11351 */ 'L', 'L', 'D', 0, |
| /* 11355 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'N', 'A', 'N', 'D', 0, |
| /* 11372 */ 'G', '_', 'A', 'N', 'D', 0, |
| /* 11378 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'A', 'N', 'D', 0, |
| /* 11394 */ 'P', 'R', 'E', 'P', 'E', 'N', 'D', 0, |
| /* 11402 */ 'A', 'P', 'P', 'E', 'N', 'D', 0, |
| /* 11409 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0, |
| /* 11422 */ 'G', '_', 'B', 'R', 'C', 'O', 'N', 'D', 0, |
| /* 11431 */ 'G', '_', 'I', 'N', 'T', 'R', 'I', 'N', 'S', 'I', 'C', '_', 'R', 'O', 'U', 'N', 'D', 0, |
| /* 11449 */ 'D', 'M', 'O', 'D', 0, |
| /* 11454 */ 'L', 'O', 'A', 'D', '_', 'S', 'T', 'A', 'C', 'K', '_', 'G', 'U', 'A', 'R', 'D', 0, |
| /* 11471 */ 'S', 'D', 0, |
| /* 11474 */ 'F', 'L', 'O', 'G', '2', '_', 'D', 0, |
| /* 11482 */ 'F', 'E', 'X', 'P', '2', '_', 'D', 0, |
| /* 11490 */ 'M', 'I', 'N', 'A', '_', 'D', 0, |
| /* 11497 */ 'S', 'R', 'A', '_', 'D', 0, |
| /* 11503 */ 'M', 'A', 'X', 'A', '_', 'D', 0, |
| /* 11510 */ 'A', 'D', 'D', '_', 'A', '_', 'D', 0, |
| /* 11518 */ 'F', 'M', 'I', 'N', '_', 'A', '_', 'D', 0, |
| /* 11527 */ 'A', 'D', 'D', 'S', '_', 'A', '_', 'D', 0, |
| /* 11536 */ 'F', 'M', 'A', 'X', '_', 'A', '_', 'D', 0, |
| /* 11545 */ 'F', 'S', 'U', 'B', '_', 'D', 0, |
| /* 11552 */ 'F', 'M', 'S', 'U', 'B', '_', 'D', 0, |
| /* 11560 */ 'N', 'L', 'O', 'C', '_', 'D', 0, |
| /* 11567 */ 'N', 'L', 'Z', 'C', '_', 'D', 0, |
| /* 11574 */ 'F', 'A', 'D', 'D', '_', 'D', 0, |
| /* 11581 */ 'F', 'M', 'A', 'D', 'D', '_', 'D', 0, |
| /* 11589 */ 'S', 'L', 'D', '_', 'D', 0, |
| /* 11595 */ 'P', 'C', 'K', 'O', 'D', '_', 'D', 0, |
| /* 11603 */ 'I', 'L', 'V', 'O', 'D', '_', 'D', 0, |
| /* 11611 */ 'F', 'C', 'L', 'E', '_', 'D', 0, |
| /* 11618 */ 'F', 'S', 'L', 'E', '_', 'D', 0, |
| /* 11625 */ 'C', 'M', 'P', '_', 'S', 'L', 'E', '_', 'D', 0, |
| /* 11635 */ 'F', 'C', 'U', 'L', 'E', '_', 'D', 0, |
| /* 11643 */ 'F', 'S', 'U', 'L', 'E', '_', 'D', 0, |
| /* 11651 */ 'C', 'M', 'P', '_', 'S', 'U', 'L', 'E', '_', 'D', 0, |
| /* 11662 */ 'C', 'M', 'P', '_', 'U', 'L', 'E', '_', 'D', 0, |
| /* 11672 */ 'C', 'M', 'P', '_', 'L', 'E', '_', 'D', 0, |
| /* 11681 */ 'F', 'C', 'N', 'E', '_', 'D', 0, |
| /* 11688 */ 'F', 'S', 'N', 'E', '_', 'D', 0, |
| /* 11695 */ 'F', 'C', 'U', 'N', 'E', '_', 'D', 0, |
| /* 11703 */ 'F', 'S', 'U', 'N', 'E', '_', 'D', 0, |
| /* 11711 */ 'I', 'N', 'S', 'V', 'E', '_', 'D', 0, |
| /* 11719 */ 'F', 'C', 'A', 'F', '_', 'D', 0, |
| /* 11726 */ 'F', 'S', 'A', 'F', '_', 'D', 0, |
| /* 11733 */ 'C', 'M', 'P', '_', 'S', 'A', 'F', '_', 'D', 0, |
| /* 11743 */ 'M', 'S', 'U', 'B', 'F', '_', 'D', 0, |
| /* 11751 */ 'M', 'A', 'D', 'D', 'F', '_', 'D', 0, |
| /* 11759 */ 'V', 'S', 'H', 'F', '_', 'D', 0, |
| /* 11766 */ 'C', 'M', 'P', '_', 'F', '_', 'D', 0, |
| /* 11774 */ 'B', 'N', 'E', 'G', '_', 'D', 0, |
| /* 11781 */ 'S', 'R', 'A', 'I', '_', 'D', 0, |
| /* 11788 */ 'S', 'L', 'D', 'I', '_', 'D', 0, |
| /* 11795 */ 'B', 'N', 'E', 'G', 'I', '_', 'D', 0, |
| /* 11803 */ 'S', 'L', 'L', 'I', '_', 'D', 0, |
| /* 11810 */ 'S', 'R', 'L', 'I', '_', 'D', 0, |
| /* 11817 */ 'B', 'I', 'N', 'S', 'L', 'I', '_', 'D', 0, |
| /* 11826 */ 'C', 'E', 'Q', 'I', '_', 'D', 0, |
| /* 11833 */ 'S', 'R', 'A', 'R', 'I', '_', 'D', 0, |
| /* 11841 */ 'B', 'C', 'L', 'R', 'I', '_', 'D', 0, |
| /* 11849 */ 'S', 'R', 'L', 'R', 'I', '_', 'D', 0, |
| /* 11857 */ 'B', 'I', 'N', 'S', 'R', 'I', '_', 'D', 0, |
| /* 11866 */ 'S', 'P', 'L', 'A', 'T', 'I', '_', 'D', 0, |
| /* 11875 */ 'B', 'S', 'E', 'T', 'I', '_', 'D', 0, |
| /* 11883 */ 'S', 'U', 'B', 'V', 'I', '_', 'D', 0, |
| /* 11891 */ 'A', 'D', 'D', 'V', 'I', '_', 'D', 0, |
| /* 11899 */ 'S', 'E', 'L', '_', 'D', 0, |
| /* 11905 */ 'F', 'I', 'L', 'L', '_', 'D', 0, |
| /* 11912 */ 'S', 'L', 'L', '_', 'D', 0, |
| /* 11918 */ 'F', 'E', 'X', 'U', 'P', 'L', '_', 'D', 0, |
| /* 11927 */ 'F', 'F', 'Q', 'L', '_', 'D', 0, |
| /* 11934 */ 'S', 'R', 'L', '_', 'D', 0, |
| /* 11940 */ 'B', 'I', 'N', 'S', 'L', '_', 'D', 0, |
| /* 11948 */ 'F', 'M', 'U', 'L', '_', 'D', 0, |
| /* 11955 */ 'I', 'L', 'V', 'L', '_', 'D', 0, |
| /* 11962 */ 'F', 'M', 'I', 'N', '_', 'D', 0, |
| /* 11969 */ 'F', 'C', 'U', 'N', '_', 'D', 0, |
| /* 11976 */ 'F', 'S', 'U', 'N', '_', 'D', 0, |
| /* 11983 */ 'C', 'M', 'P', '_', 'S', 'U', 'N', '_', 'D', 0, |
| /* 11993 */ 'C', 'M', 'P', '_', 'U', 'N', '_', 'D', 0, |
| /* 12002 */ 'F', 'R', 'C', 'P', '_', 'D', 0, |
| /* 12009 */ 'F', 'C', 'E', 'Q', '_', 'D', 0, |
| /* 12016 */ 'F', 'S', 'E', 'Q', '_', 'D', 0, |
| /* 12023 */ 'C', 'M', 'P', '_', 'S', 'E', 'Q', '_', 'D', 0, |
| /* 12033 */ 'F', 'C', 'U', 'E', 'Q', '_', 'D', 0, |
| /* 12041 */ 'F', 'S', 'U', 'E', 'Q', '_', 'D', 0, |
| /* 12049 */ 'C', 'M', 'P', '_', 'S', 'U', 'E', 'Q', '_', 'D', 0, |
| /* 12060 */ 'C', 'M', 'P', '_', 'U', 'E', 'Q', '_', 'D', 0, |
| /* 12070 */ 'C', 'M', 'P', '_', 'E', 'Q', '_', 'D', 0, |
| /* 12079 */ 'S', 'R', 'A', 'R', '_', 'D', 0, |
| /* 12086 */ 'B', 'C', 'L', 'R', '_', 'D', 0, |
| /* 12093 */ 'S', 'R', 'L', 'R', '_', 'D', 0, |
| /* 12100 */ 'F', 'C', 'O', 'R', '_', 'D', 0, |
| /* 12107 */ 'F', 'S', 'O', 'R', '_', 'D', 0, |
| /* 12114 */ 'F', 'E', 'X', 'U', 'P', 'R', '_', 'D', 0, |
| /* 12123 */ 'F', 'F', 'Q', 'R', '_', 'D', 0, |
| /* 12130 */ 'B', 'I', 'N', 'S', 'R', '_', 'D', 0, |
| /* 12138 */ 'I', 'L', 'V', 'R', '_', 'D', 0, |
| /* 12145 */ 'F', 'A', 'B', 'S', '_', 'D', 0, |
| /* 12152 */ 'F', 'C', 'L', 'A', 'S', 'S', '_', 'D', 0, |
| /* 12161 */ 'A', 'S', 'U', 'B', '_', 'S', '_', 'D', 0, |
| /* 12170 */ 'H', 'S', 'U', 'B', '_', 'S', '_', 'D', 0, |
| /* 12179 */ 'D', 'P', 'S', 'U', 'B', '_', 'S', '_', 'D', 0, |
| /* 12189 */ 'F', 'T', 'R', 'U', 'N', 'C', '_', 'S', '_', 'D', 0, |
| /* 12200 */ 'H', 'A', 'D', 'D', '_', 'S', '_', 'D', 0, |
| /* 12209 */ 'D', 'P', 'A', 'D', 'D', '_', 'S', '_', 'D', 0, |
| /* 12219 */ 'M', 'O', 'D', '_', 'S', '_', 'D', 0, |
| /* 12227 */ 'C', 'L', 'E', '_', 'S', '_', 'D', 0, |
| /* 12235 */ 'A', 'V', 'E', '_', 'S', '_', 'D', 0, |
| /* 12243 */ 'C', 'L', 'E', 'I', '_', 'S', '_', 'D', 0, |
| /* 12252 */ 'M', 'I', 'N', 'I', '_', 'S', '_', 'D', 0, |
| /* 12261 */ 'C', 'L', 'T', 'I', '_', 'S', '_', 'D', 0, |
| /* 12270 */ 'M', 'A', 'X', 'I', '_', 'S', '_', 'D', 0, |
| /* 12279 */ 'M', 'I', 'N', '_', 'S', '_', 'D', 0, |
| /* 12287 */ 'D', 'O', 'T', 'P', '_', 'S', '_', 'D', 0, |
| /* 12296 */ 'A', 'V', 'E', 'R', '_', 'S', '_', 'D', 0, |
| /* 12305 */ 'S', 'U', 'B', 'S', '_', 'S', '_', 'D', 0, |
| /* 12314 */ 'A', 'D', 'D', 'S', '_', 'S', '_', 'D', 0, |
| /* 12323 */ 'S', 'A', 'T', '_', 'S', '_', 'D', 0, |
| /* 12331 */ 'C', 'L', 'T', '_', 'S', '_', 'D', 0, |
| /* 12339 */ 'F', 'F', 'I', 'N', 'T', '_', 'S', '_', 'D', 0, |
| /* 12349 */ 'F', 'T', 'I', 'N', 'T', '_', 'S', '_', 'D', 0, |
| /* 12359 */ 'S', 'U', 'B', 'S', 'U', 'U', '_', 'S', '_', 'D', 0, |
| /* 12370 */ 'D', 'I', 'V', '_', 'S', '_', 'D', 0, |
| /* 12378 */ 'M', 'A', 'X', '_', 'S', '_', 'D', 0, |
| /* 12386 */ 'C', 'O', 'P', 'Y', '_', 'S', '_', 'D', 0, |
| /* 12395 */ 'S', 'P', 'L', 'A', 'T', '_', 'D', 0, |
| /* 12403 */ 'B', 'S', 'E', 'T', '_', 'D', 0, |
| /* 12410 */ 'F', 'C', 'L', 'T', '_', 'D', 0, |
| /* 12417 */ 'F', 'S', 'L', 'T', '_', 'D', 0, |
| /* 12424 */ 'C', 'M', 'P', '_', 'S', 'L', 'T', '_', 'D', 0, |
| /* 12434 */ 'F', 'C', 'U', 'L', 'T', '_', 'D', 0, |
| /* 12442 */ 'F', 'S', 'U', 'L', 'T', '_', 'D', 0, |
| /* 12450 */ 'C', 'M', 'P', '_', 'S', 'U', 'L', 'T', '_', 'D', 0, |
| /* 12461 */ 'C', 'M', 'P', '_', 'U', 'L', 'T', '_', 'D', 0, |
| /* 12471 */ 'C', 'M', 'P', '_', 'L', 'T', '_', 'D', 0, |
| /* 12480 */ 'P', 'C', 'N', 'T', '_', 'D', 0, |
| /* 12487 */ 'F', 'R', 'I', 'N', 'T', '_', 'D', 0, |
| /* 12495 */ 'I', 'N', 'S', 'E', 'R', 'T', '_', 'D', 0, |
| /* 12504 */ 'F', 'S', 'Q', 'R', 'T', '_', 'D', 0, |
| /* 12512 */ 'F', 'R', 'S', 'Q', 'R', 'T', '_', 'D', 0, |
| /* 12521 */ 'S', 'T', '_', 'D', 0, |
| /* 12526 */ 'A', 'S', 'U', 'B', '_', 'U', '_', 'D', 0, |
| /* 12535 */ 'H', 'S', 'U', 'B', '_', 'U', '_', 'D', 0, |
| /* 12544 */ 'D', 'P', 'S', 'U', 'B', '_', 'U', '_', 'D', 0, |
| /* 12554 */ 'F', 'T', 'R', 'U', 'N', 'C', '_', 'U', '_', 'D', 0, |
| /* 12565 */ 'H', 'A', 'D', 'D', '_', 'U', '_', 'D', 0, |
| /* 12574 */ 'D', 'P', 'A', 'D', 'D', '_', 'U', '_', 'D', 0, |
| /* 12584 */ 'M', 'O', 'D', '_', 'U', '_', 'D', 0, |
| /* 12592 */ 'C', 'L', 'E', '_', 'U', '_', 'D', 0, |
| /* 12600 */ 'A', 'V', 'E', '_', 'U', '_', 'D', 0, |
| /* 12608 */ 'C', 'L', 'E', 'I', '_', 'U', '_', 'D', 0, |
| /* 12617 */ 'M', 'I', 'N', 'I', '_', 'U', '_', 'D', 0, |
| /* 12626 */ 'C', 'L', 'T', 'I', '_', 'U', '_', 'D', 0, |
| /* 12635 */ 'M', 'A', 'X', 'I', '_', 'U', '_', 'D', 0, |
| /* 12644 */ 'M', 'I', 'N', '_', 'U', '_', 'D', 0, |
| /* 12652 */ 'D', 'O', 'T', 'P', '_', 'U', '_', 'D', 0, |
| /* 12661 */ 'A', 'V', 'E', 'R', '_', 'U', '_', 'D', 0, |
| /* 12670 */ 'S', 'U', 'B', 'S', '_', 'U', '_', 'D', 0, |
| /* 12679 */ 'A', 'D', 'D', 'S', '_', 'U', '_', 'D', 0, |
| /* 12688 */ 'S', 'U', 'B', 'S', 'U', 'S', '_', 'U', '_', 'D', 0, |
| /* 12699 */ 'S', 'A', 'T', '_', 'U', '_', 'D', 0, |
| /* 12707 */ 'C', 'L', 'T', '_', 'U', '_', 'D', 0, |
| /* 12715 */ 'F', 'F', 'I', 'N', 'T', '_', 'U', '_', 'D', 0, |
| /* 12725 */ 'F', 'T', 'I', 'N', 'T', '_', 'U', '_', 'D', 0, |
| /* 12735 */ 'D', 'I', 'V', '_', 'U', '_', 'D', 0, |
| /* 12743 */ 'M', 'A', 'X', '_', 'U', '_', 'D', 0, |
| /* 12751 */ 'M', 'S', 'U', 'B', 'V', '_', 'D', 0, |
| /* 12759 */ 'M', 'A', 'D', 'D', 'V', '_', 'D', 0, |
| /* 12767 */ 'P', 'C', 'K', 'E', 'V', '_', 'D', 0, |
| /* 12775 */ 'I', 'L', 'V', 'E', 'V', '_', 'D', 0, |
| /* 12783 */ 'F', 'D', 'I', 'V', '_', 'D', 0, |
| /* 12790 */ 'M', 'U', 'L', 'V', '_', 'D', 0, |
| /* 12797 */ 'P', 's', 'e', 'u', 'd', 'o', 'T', 'R', 'U', 'N', 'C', '_', 'W', '_', 'D', 0, |
| /* 12813 */ 'F', 'M', 'A', 'X', '_', 'D', 0, |
| /* 12820 */ 'B', 'Z', '_', 'D', 0, |
| /* 12825 */ 'S', 'E', 'L', 'N', 'E', 'Z', '_', 'D', 0, |
| /* 12834 */ 'B', 'N', 'Z', '_', 'D', 0, |
| /* 12840 */ 'S', 'E', 'L', 'E', 'Q', 'Z', '_', 'D', 0, |
| /* 12849 */ 'L', 'B', 'E', 0, |
| /* 12853 */ 'S', 'B', 'E', 0, |
| /* 12857 */ 'G', '_', 'S', 'S', 'U', 'B', 'E', 0, |
| /* 12865 */ 'G', '_', 'U', 'S', 'U', 'B', 'E', 0, |
| /* 12873 */ 'G', '_', 'F', 'E', 'N', 'C', 'E', 0, |
| /* 12881 */ 'R', 'E', 'G', '_', 'S', 'E', 'Q', 'U', 'E', 'N', 'C', 'E', 0, |
| /* 12894 */ 'S', 'C', 'E', 0, |
| /* 12898 */ 'G', '_', 'S', 'A', 'D', 'D', 'E', 0, |
| /* 12906 */ 'G', '_', 'U', 'A', 'D', 'D', 'E', 0, |
| /* 12914 */ 'G', '_', 'F', 'M', 'I', 'N', 'N', 'U', 'M', '_', 'I', 'E', 'E', 'E', 0, |
| /* 12929 */ 'G', '_', 'F', 'M', 'A', 'X', 'N', 'U', 'M', '_', 'I', 'E', 'E', 'E', 0, |
| /* 12944 */ 'C', 'A', 'C', 'H', 'E', 'E', 0, |
| /* 12951 */ 'P', 'R', 'E', 'F', 'E', 0, |
| /* 12957 */ 'B', 'G', 'E', 0, |
| /* 12961 */ 'S', 'G', 'E', 0, |
| /* 12965 */ 'T', 'G', 'E', 0, |
| /* 12969 */ 'C', 'A', 'C', 'H', 'E', 0, |
| /* 12975 */ 'L', 'H', 'E', 0, |
| /* 12979 */ 'S', 'H', 'E', 0, |
| /* 12983 */ 'S', 'I', 'G', 'R', 'I', 'E', 0, |
| /* 12990 */ 'G', '_', 'J', 'U', 'M', 'P', '_', 'T', 'A', 'B', 'L', 'E', 0, |
| /* 13003 */ 'B', 'U', 'N', 'D', 'L', 'E', 0, |
| /* 13010 */ 'L', 'L', 'E', 0, |
| /* 13014 */ 'L', 'W', 'L', 'E', 0, |
| /* 13019 */ 'S', 'W', 'L', 'E', 0, |
| /* 13024 */ 'B', 'N', 'E', 0, |
| /* 13028 */ 'S', 'N', 'E', 0, |
| /* 13032 */ 'T', 'N', 'E', 0, |
| /* 13036 */ 'L', 'O', 'C', 'A', 'L', '_', 'E', 'S', 'C', 'A', 'P', 'E', 0, |
| /* 13049 */ 'D', 'V', 'P', 'E', 0, |
| /* 13054 */ 'E', 'V', 'P', 'E', 0, |
| /* 13059 */ 'G', '_', 'I', 'N', 'D', 'E', 'X', 'E', 'D', '_', 'S', 'T', 'O', 'R', 'E', 0, |
| /* 13075 */ 'G', '_', 'S', 'T', 'O', 'R', 'E', 0, |
| /* 13083 */ 'L', 'W', 'R', 'E', 0, |
| /* 13088 */ 'S', 'W', 'R', 'E', 0, |
| /* 13093 */ 'G', '_', 'B', 'I', 'T', 'R', 'E', 'V', 'E', 'R', 'S', 'E', 0, |
| /* 13106 */ 'P', 'A', 'U', 'S', 'E', 0, |
| /* 13112 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0, |
| /* 13122 */ 'G', '_', 'G', 'L', 'O', 'B', 'A', 'L', '_', 'V', 'A', 'L', 'U', 'E', 0, |
| /* 13137 */ 'L', 'W', 'E', 0, |
| /* 13141 */ 'S', 'W', 'E', 0, |
| /* 13145 */ 'G', '_', 'F', 'C', 'A', 'N', 'O', 'N', 'I', 'C', 'A', 'L', 'I', 'Z', 'E', 0, |
| /* 13161 */ 'L', 'B', 'u', 'E', 0, |
| /* 13166 */ 'L', 'H', 'u', 'E', 0, |
| /* 13171 */ 'B', 'C', '1', 'F', 0, |
| /* 13176 */ 'G', '_', 'C', 'T', 'L', 'Z', '_', 'Z', 'E', 'R', 'O', '_', 'U', 'N', 'D', 'E', 'F', 0, |
| /* 13194 */ 'G', '_', 'C', 'T', 'T', 'Z', '_', 'Z', 'E', 'R', 'O', '_', 'U', 'N', 'D', 'E', 'F', 0, |
| /* 13212 */ 'G', '_', 'I', 'M', 'P', 'L', 'I', 'C', 'I', 'T', '_', 'D', 'E', 'F', 0, |
| /* 13227 */ 'P', 'R', 'E', 'F', 0, |
| /* 13232 */ 'T', 'L', 'B', 'I', 'N', 'V', 'F', 0, |
| /* 13240 */ 'T', 'L', 'B', 'G', 'I', 'N', 'V', 'F', 0, |
| /* 13249 */ 'G', '_', 'F', 'N', 'E', 'G', 0, |
| /* 13256 */ 'T', 'A', 'I', 'L', 'C', 'A', 'L', 'L', 'H', 'B', '6', '4', 'R', '6', 'R', 'E', 'G', 0, |
| /* 13274 */ 'T', 'A', 'I', 'L', 'C', 'A', 'L', 'L', '6', '4', 'R', '6', 'R', 'E', 'G', 0, |
| /* 13290 */ 'T', 'A', 'I', 'L', 'C', 'A', 'L', 'L', 'H', 'B', 'R', '6', 'R', 'E', 'G', 0, |
| /* 13306 */ 'T', 'A', 'I', 'L', 'C', 'A', 'L', 'L', 'R', '6', 'R', 'E', 'G', 0, |
| /* 13320 */ 'E', 'X', 'T', 'R', 'A', 'C', 'T', '_', 'S', 'U', 'B', 'R', 'E', 'G', 0, |
| /* 13335 */ 'I', 'N', 'S', 'E', 'R', 'T', '_', 'S', 'U', 'B', 'R', 'E', 'G', 0, |
| /* 13349 */ 'T', 'A', 'I', 'L', 'C', 'A', 'L', 'L', 'R', 'E', 'G', 0, |
| /* 13361 */ 'G', '_', 'S', 'E', 'X', 'T', '_', 'I', 'N', 'R', 'E', 'G', 0, |
| /* 13374 */ 'S', 'U', 'B', 'R', 'E', 'G', '_', 'T', 'O', '_', 'R', 'E', 'G', 0, |
| /* 13388 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'C', 'M', 'P', 'X', 'C', 'H', 'G', 0, |
| /* 13405 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'X', 'C', 'H', 'G', 0, |
| /* 13422 */ 'G', '_', 'F', 'L', 'O', 'G', 0, |
| /* 13429 */ 'G', '_', 'V', 'A', 'A', 'R', 'G', 0, |
| /* 13437 */ 'C', 'R', 'C', '3', '2', 'H', 0, |
| /* 13444 */ 'D', 'S', 'B', 'H', 0, |
| /* 13449 */ 'W', 'S', 'B', 'H', 0, |
| /* 13454 */ 'C', 'R', 'C', '3', '2', 'C', 'H', 0, |
| /* 13462 */ 'S', 'E', 'H', 0, |
| /* 13466 */ 'G', '_', 'S', 'M', 'U', 'L', 'H', 0, |
| /* 13474 */ 'G', '_', 'U', 'M', 'U', 'L', 'H', 0, |
| /* 13482 */ 'S', 'H', 'R', 'A', '_', 'P', 'H', 0, |
| /* 13490 */ 'P', 'R', 'E', 'C', 'R', 'Q', '_', 'Q', 'B', '_', 'P', 'H', 0, |
| /* 13503 */ 'P', 'R', 'E', 'C', 'R', '_', 'Q', 'B', '_', 'P', 'H', 0, |
| /* 13515 */ 'P', 'R', 'E', 'C', 'R', 'Q', 'U', '_', 'S', '_', 'Q', 'B', '_', 'P', 'H', 0, |
| /* 13531 */ 'P', 's', 'e', 'u', 'd', 'o', 'C', 'M', 'P', '_', 'L', 'E', '_', 'P', 'H', 0, |
| /* 13547 */ 'S', 'U', 'B', 'Q', 'H', '_', 'P', 'H', 0, |
| /* 13556 */ 'A', 'D', 'D', 'Q', 'H', '_', 'P', 'H', 0, |
| /* 13565 */ 'P', 's', 'e', 'u', 'd', 'o', 'P', 'I', 'C', 'K', '_', 'P', 'H', 0, |
| /* 13579 */ 'S', 'H', 'L', 'L', '_', 'P', 'H', 0, |
| /* 13587 */ 'R', 'E', 'P', 'L', '_', 'P', 'H', 0, |
| /* 13595 */ 'S', 'H', 'R', 'L', '_', 'P', 'H', 0, |
| /* 13603 */ 'P', 'A', 'C', 'K', 'R', 'L', '_', 'P', 'H', 0, |
| /* 13613 */ 'M', 'U', 'L', '_', 'P', 'H', 0, |
| /* 13620 */ 'S', 'U', 'B', 'Q', '_', 'P', 'H', 0, |
| /* 13628 */ 'A', 'D', 'D', 'Q', '_', 'P', 'H', 0, |
| /* 13636 */ 'P', 's', 'e', 'u', 'd', 'o', 'C', 'M', 'P', '_', 'E', 'Q', '_', 'P', 'H', 0, |
| /* 13652 */ 'S', 'H', 'R', 'A', '_', 'R', '_', 'P', 'H', 0, |
| /* 13662 */ 'S', 'U', 'B', 'Q', 'H', '_', 'R', '_', 'P', 'H', 0, |
| /* 13673 */ 'A', 'D', 'D', 'Q', 'H', '_', 'R', '_', 'P', 'H', 0, |
| /* 13684 */ 'S', 'H', 'R', 'A', 'V', '_', 'R', '_', 'P', 'H', 0, |
| /* 13695 */ 'M', 'U', 'L', 'Q', '_', 'R', 'S', '_', 'P', 'H', 0, |
| /* 13706 */ 'S', 'H', 'L', 'L', '_', 'S', '_', 'P', 'H', 0, |
| /* 13716 */ 'M', 'U', 'L', '_', 'S', '_', 'P', 'H', 0, |
| /* 13725 */ 'S', 'U', 'B', 'Q', '_', 'S', '_', 'P', 'H', 0, |
| /* 13735 */ 'A', 'D', 'D', 'Q', '_', 'S', '_', 'P', 'H', 0, |
| /* 13745 */ 'M', 'U', 'L', 'Q', '_', 'S', '_', 'P', 'H', 0, |
| /* 13755 */ 'A', 'B', 'S', 'Q', '_', 'S', '_', 'P', 'H', 0, |
| /* 13765 */ 'S', 'U', 'B', 'U', '_', 'S', '_', 'P', 'H', 0, |
| /* 13775 */ 'A', 'D', 'D', 'U', '_', 'S', '_', 'P', 'H', 0, |
| /* 13785 */ 'S', 'H', 'L', 'L', 'V', '_', 'S', '_', 'P', 'H', 0, |
| /* 13796 */ 'P', 's', 'e', 'u', 'd', 'o', 'C', 'M', 'P', '_', 'L', 'T', '_', 'P', 'H', 0, |
| /* 13812 */ 'S', 'U', 'B', 'U', '_', 'P', 'H', 0, |
| /* 13820 */ 'A', 'D', 'D', 'U', '_', 'P', 'H', 0, |
| /* 13828 */ 'S', 'H', 'R', 'A', 'V', '_', 'P', 'H', 0, |
| /* 13837 */ 'S', 'H', 'L', 'L', 'V', '_', 'P', 'H', 0, |
| /* 13846 */ 'R', 'E', 'P', 'L', 'V', '_', 'P', 'H', 0, |
| /* 13855 */ 'S', 'H', 'R', 'L', 'V', '_', 'P', 'H', 0, |
| /* 13864 */ 'D', 'P', 'A', '_', 'W', '_', 'P', 'H', 0, |
| /* 13873 */ 'M', 'U', 'L', 'S', 'A', '_', 'W', '_', 'P', 'H', 0, |
| /* 13884 */ 'D', 'P', 'A', 'Q', 'X', '_', 'S', 'A', '_', 'W', '_', 'P', 'H', 0, |
| /* 13898 */ 'D', 'P', 'S', 'Q', 'X', '_', 'S', 'A', '_', 'W', '_', 'P', 'H', 0, |
| /* 13912 */ 'D', 'P', 'S', '_', 'W', '_', 'P', 'H', 0, |
| /* 13921 */ 'D', 'P', 'A', 'Q', '_', 'S', '_', 'W', '_', 'P', 'H', 0, |
| /* 13933 */ 'M', 'U', 'L', 'S', 'A', 'Q', '_', 'S', '_', 'W', '_', 'P', 'H', 0, |
| /* 13947 */ 'D', 'P', 'S', 'Q', '_', 'S', '_', 'W', '_', 'P', 'H', 0, |
| /* 13959 */ 'D', 'P', 'A', 'Q', 'X', '_', 'S', '_', 'W', '_', 'P', 'H', 0, |
| /* 13972 */ 'D', 'P', 'S', 'Q', 'X', '_', 'S', '_', 'W', '_', 'P', 'H', 0, |
| /* 13985 */ 'D', 'P', 'A', 'X', '_', 'W', '_', 'P', 'H', 0, |
| /* 13995 */ 'D', 'P', 'S', 'X', '_', 'W', '_', 'P', 'H', 0, |
| /* 14005 */ 'S', 'H', 0, |
| /* 14008 */ 'D', 'M', 'U', 'H', 0, |
| /* 14013 */ 'S', 'R', 'A', '_', 'H', 0, |
| /* 14019 */ 'A', 'D', 'D', '_', 'A', '_', 'H', 0, |
| /* 14027 */ 'M', 'I', 'N', '_', 'A', '_', 'H', 0, |
| /* 14035 */ 'A', 'D', 'D', 'S', '_', 'A', '_', 'H', 0, |
| /* 14044 */ 'M', 'A', 'X', '_', 'A', '_', 'H', 0, |
| /* 14052 */ 'N', 'L', 'O', 'C', '_', 'H', 0, |
| /* 14059 */ 'N', 'L', 'Z', 'C', '_', 'H', 0, |
| /* 14066 */ 'S', 'L', 'D', '_', 'H', 0, |
| /* 14072 */ 'P', 'C', 'K', 'O', 'D', '_', 'H', 0, |
| /* 14080 */ 'I', 'L', 'V', 'O', 'D', '_', 'H', 0, |
| /* 14088 */ 'I', 'N', 'S', 'V', 'E', '_', 'H', 0, |
| /* 14096 */ 'V', 'S', 'H', 'F', '_', 'H', 0, |
| /* 14103 */ 'B', 'N', 'E', 'G', '_', 'H', 0, |
| /* 14110 */ 'S', 'R', 'A', 'I', '_', 'H', 0, |
| /* 14117 */ 'S', 'L', 'D', 'I', '_', 'H', 0, |
| /* 14124 */ 'B', 'N', 'E', 'G', 'I', '_', 'H', 0, |
| /* 14132 */ 'S', 'L', 'L', 'I', '_', 'H', 0, |
| /* 14139 */ 'S', 'R', 'L', 'I', '_', 'H', 0, |
| /* 14146 */ 'B', 'I', 'N', 'S', 'L', 'I', '_', 'H', 0, |
| /* 14155 */ 'C', 'E', 'Q', 'I', '_', 'H', 0, |
| /* 14162 */ 'S', 'R', 'A', 'R', 'I', '_', 'H', 0, |
| /* 14170 */ 'B', 'C', 'L', 'R', 'I', '_', 'H', 0, |
| /* 14178 */ 'S', 'R', 'L', 'R', 'I', '_', 'H', 0, |
| /* 14186 */ 'B', 'I', 'N', 'S', 'R', 'I', '_', 'H', 0, |
| /* 14195 */ 'S', 'P', 'L', 'A', 'T', 'I', '_', 'H', 0, |
| /* 14204 */ 'B', 'S', 'E', 'T', 'I', '_', 'H', 0, |
| /* 14212 */ 'S', 'U', 'B', 'V', 'I', '_', 'H', 0, |
| /* 14220 */ 'A', 'D', 'D', 'V', 'I', '_', 'H', 0, |
| /* 14228 */ 'F', 'I', 'L', 'L', '_', 'H', 0, |
| /* 14235 */ 'S', 'L', 'L', '_', 'H', 0, |
| /* 14241 */ 'S', 'R', 'L', '_', 'H', 0, |
| /* 14247 */ 'B', 'I', 'N', 'S', 'L', '_', 'H', 0, |
| /* 14255 */ 'I', 'L', 'V', 'L', '_', 'H', 0, |
| /* 14262 */ 'F', 'E', 'X', 'D', 'O', '_', 'H', 0, |
| /* 14270 */ 'C', 'E', 'Q', '_', 'H', 0, |
| /* 14276 */ 'F', 'T', 'Q', '_', 'H', 0, |
| /* 14282 */ 'M', 'S', 'U', 'B', '_', 'Q', '_', 'H', 0, |
| /* 14291 */ 'M', 'A', 'D', 'D', '_', 'Q', '_', 'H', 0, |
| /* 14300 */ 'M', 'U', 'L', '_', 'Q', '_', 'H', 0, |
| /* 14308 */ 'M', 'S', 'U', 'B', 'R', '_', 'Q', '_', 'H', 0, |
| /* 14318 */ 'M', 'A', 'D', 'D', 'R', '_', 'Q', '_', 'H', 0, |
| /* 14328 */ 'M', 'U', 'L', 'R', '_', 'Q', '_', 'H', 0, |
| /* 14337 */ 'S', 'R', 'A', 'R', '_', 'H', 0, |
| /* 14344 */ 'B', 'C', 'L', 'R', '_', 'H', 0, |
| /* 14351 */ 'S', 'R', 'L', 'R', '_', 'H', 0, |
| /* 14358 */ 'B', 'I', 'N', 'S', 'R', '_', 'H', 0, |
| /* 14366 */ 'I', 'L', 'V', 'R', '_', 'H', 0, |
| /* 14373 */ 'A', 'S', 'U', 'B', '_', 'S', '_', 'H', 0, |
| /* 14382 */ 'H', 'S', 'U', 'B', '_', 'S', '_', 'H', 0, |
| /* 14391 */ 'D', 'P', 'S', 'U', 'B', '_', 'S', '_', 'H', 0, |
| /* 14401 */ 'H', 'A', 'D', 'D', '_', 'S', '_', 'H', 0, |
| /* 14410 */ 'D', 'P', 'A', 'D', 'D', '_', 'S', '_', 'H', 0, |
| /* 14420 */ 'M', 'O', 'D', '_', 'S', '_', 'H', 0, |
| /* 14428 */ 'C', 'L', 'E', '_', 'S', '_', 'H', 0, |
| /* 14436 */ 'A', 'V', 'E', '_', 'S', '_', 'H', 0, |
| /* 14444 */ 'C', 'L', 'E', 'I', '_', 'S', '_', 'H', 0, |
| /* 14453 */ 'M', 'I', 'N', 'I', '_', 'S', '_', 'H', 0, |
| /* 14462 */ 'C', 'L', 'T', 'I', '_', 'S', '_', 'H', 0, |
| /* 14471 */ 'M', 'A', 'X', 'I', '_', 'S', '_', 'H', 0, |
| /* 14480 */ 'M', 'I', 'N', '_', 'S', '_', 'H', 0, |
| /* 14488 */ 'D', 'O', 'T', 'P', '_', 'S', '_', 'H', 0, |
| /* 14497 */ 'A', 'V', 'E', 'R', '_', 'S', '_', 'H', 0, |
| /* 14506 */ 'E', 'X', 'T', 'R', '_', 'S', '_', 'H', 0, |
| /* 14515 */ 'S', 'U', 'B', 'S', '_', 'S', '_', 'H', 0, |
| /* 14524 */ 'A', 'D', 'D', 'S', '_', 'S', '_', 'H', 0, |
| /* 14533 */ 'S', 'A', 'T', '_', 'S', '_', 'H', 0, |
| /* 14541 */ 'C', 'L', 'T', '_', 'S', '_', 'H', 0, |
| /* 14549 */ 'S', 'U', 'B', 'S', 'U', 'U', '_', 'S', '_', 'H', 0, |
| /* 14560 */ 'D', 'I', 'V', '_', 'S', '_', 'H', 0, |
| /* 14568 */ 'E', 'X', 'T', 'R', 'V', '_', 'S', '_', 'H', 0, |
| /* 14578 */ 'M', 'A', 'X', '_', 'S', '_', 'H', 0, |
| /* 14586 */ 'C', 'O', 'P', 'Y', '_', 'S', '_', 'H', 0, |
| /* 14595 */ 'S', 'P', 'L', 'A', 'T', '_', 'H', 0, |
| /* 14603 */ 'B', 'S', 'E', 'T', '_', 'H', 0, |
| /* 14610 */ 'P', 'C', 'N', 'T', '_', 'H', 0, |
| /* 14617 */ 'I', 'N', 'S', 'E', 'R', 'T', '_', 'H', 0, |
| /* 14626 */ 'S', 'T', '_', 'H', 0, |
| /* 14631 */ 'A', 'S', 'U', 'B', '_', 'U', '_', 'H', 0, |
| /* 14640 */ 'H', 'S', 'U', 'B', '_', 'U', '_', 'H', 0, |
| /* 14649 */ 'D', 'P', 'S', 'U', 'B', '_', 'U', '_', 'H', 0, |
| /* 14659 */ 'H', 'A', 'D', 'D', '_', 'U', '_', 'H', 0, |
| /* 14668 */ 'D', 'P', 'A', 'D', 'D', '_', 'U', '_', 'H', 0, |
| /* 14678 */ 'M', 'O', 'D', '_', 'U', '_', 'H', 0, |
| /* 14686 */ 'C', 'L', 'E', '_', 'U', '_', 'H', 0, |
| /* 14694 */ 'A', 'V', 'E', '_', 'U', '_', 'H', 0, |
| /* 14702 */ 'C', 'L', 'E', 'I', '_', 'U', '_', 'H', 0, |
| /* 14711 */ 'M', 'I', 'N', 'I', '_', 'U', '_', 'H', 0, |
| /* 14720 */ 'C', 'L', 'T', 'I', '_', 'U', '_', 'H', 0, |
| /* 14729 */ 'M', 'A', 'X', 'I', '_', 'U', '_', 'H', 0, |
| /* 14738 */ 'M', 'I', 'N', '_', 'U', '_', 'H', 0, |
| /* 14746 */ 'D', 'O', 'T', 'P', '_', 'U', '_', 'H', 0, |
| /* 14755 */ 'A', 'V', 'E', 'R', '_', 'U', '_', 'H', 0, |
| /* 14764 */ 'S', 'U', 'B', 'S', '_', 'U', '_', 'H', 0, |
| /* 14773 */ 'A', 'D', 'D', 'S', '_', 'U', '_', 'H', 0, |
| /* 14782 */ 'S', 'U', 'B', 'S', 'U', 'S', '_', 'U', '_', 'H', 0, |
| /* 14793 */ 'S', 'A', 'T', '_', 'U', '_', 'H', 0, |
| /* 14801 */ 'C', 'L', 'T', '_', 'U', '_', 'H', 0, |
| /* 14809 */ 'D', 'I', 'V', '_', 'U', '_', 'H', 0, |
| /* 14817 */ 'M', 'A', 'X', '_', 'U', '_', 'H', 0, |
| /* 14825 */ 'C', 'O', 'P', 'Y', '_', 'U', '_', 'H', 0, |
| /* 14834 */ 'M', 'S', 'U', 'B', 'V', '_', 'H', 0, |
| /* 14842 */ 'M', 'A', 'D', 'D', 'V', '_', 'H', 0, |
| /* 14850 */ 'P', 'C', 'K', 'E', 'V', '_', 'H', 0, |
| /* 14858 */ 'I', 'L', 'V', 'E', 'V', '_', 'H', 0, |
| /* 14866 */ 'M', 'U', 'L', 'V', '_', 'H', 0, |
| /* 14873 */ 'B', 'Z', '_', 'H', 0, |
| /* 14878 */ 'B', 'N', 'Z', '_', 'H', 0, |
| /* 14884 */ 'S', 'Y', 'N', 'C', 'I', 0, |
| /* 14890 */ 'D', 'I', 0, |
| /* 14893 */ 'T', 'G', 'E', 'I', 0, |
| /* 14898 */ 'T', 'N', 'E', 'I', 0, |
| /* 14903 */ 'D', 'A', 'H', 'I', 0, |
| /* 14908 */ 'P', 's', 'e', 'u', 'd', 'o', 'M', 'F', 'H', 'I', 0, |
| /* 14919 */ 'P', 's', 'e', 'u', 'd', 'o', 'M', 'T', 'L', 'O', 'H', 'I', 0, |
| /* 14932 */ 'G', '_', 'P', 'H', 'I', 0, |
| /* 14938 */ 'M', 'F', 'T', 'H', 'I', 0, |
| /* 14944 */ 'M', 'T', 'H', 'I', 0, |
| /* 14949 */ 'M', 'T', 'T', 'H', 'I', 0, |
| /* 14955 */ 'T', 'E', 'Q', 'I', 0, |
| /* 14960 */ 'G', '_', 'F', 'P', 'T', 'O', 'S', 'I', 0, |
| /* 14969 */ 'D', 'A', 'T', 'I', 0, |
| /* 14974 */ 'T', 'L', 'T', 'I', 0, |
| /* 14979 */ 'D', 'A', 'U', 'I', 0, |
| /* 14984 */ 'G', '_', 'F', 'P', 'T', 'O', 'U', 'I', 0, |
| /* 14993 */ 'G', 'I', 'N', 'V', 'I', 0, |
| /* 14999 */ 'T', 'L', 'B', 'W', 'I', 0, |
| /* 15005 */ 'T', 'L', 'B', 'G', 'W', 'I', 0, |
| /* 15012 */ 'M', 'O', 'V', 'N', '_', 'I', '6', '4', '_', 'I', 0, |
| /* 15023 */ 'M', 'O', 'V', 'Z', '_', 'I', '6', '4', '_', 'I', 0, |
| /* 15034 */ 'M', 'O', 'V', 'F', '_', 'I', 0, |
| /* 15041 */ 'P', 's', 'e', 'u', 'd', 'o', 'S', 'E', 'L', 'E', 'C', 'T', 'F', 'P', '_', 'F', '_', 'I', 0, |
| /* 15060 */ 'M', 'O', 'V', 'N', '_', 'I', '_', 'I', 0, |
| /* 15069 */ 'M', 'O', 'V', 'Z', '_', 'I', '_', 'I', 0, |
| /* 15078 */ 'P', 's', 'e', 'u', 'd', 'o', 'D', '_', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'I', 0, |
| /* 15095 */ 'P', 's', 'e', 'u', 'd', 'o', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'I', 0, |
| /* 15110 */ 'M', 'O', 'V', 'T', '_', 'I', 0, |
| /* 15117 */ 'P', 's', 'e', 'u', 'd', 'o', 'S', 'E', 'L', 'E', 'C', 'T', 'F', 'P', '_', 'T', '_', 'I', 0, |
| /* 15136 */ 'J', 0, |
| /* 15138 */ 'B', 'R', 'E', 'A', 'K', 0, |
| /* 15144 */ 'F', 'O', 'R', 'K', 0, |
| /* 15149 */ 'G', '_', 'P', 'T', 'R', '_', 'M', 'A', 'S', 'K', 0, |
| /* 15160 */ 'B', 'A', 'L', 0, |
| /* 15164 */ 'J', 'A', 'L', 0, |
| /* 15168 */ 'B', 'G', 'E', 'Z', 'A', 'L', 0, |
| /* 15175 */ 'B', 'L', 'T', 'Z', 'A', 'L', 0, |
| /* 15182 */ 'M', 'U', 'L', 'E', 'U', '_', 'S', '_', 'P', 'H', '_', 'Q', 'B', 'L', 0, |
| /* 15197 */ 'P', 'R', 'E', 'C', 'E', 'U', '_', 'P', 'H', '_', 'Q', 'B', 'L', 0, |
| /* 15211 */ 'P', 'R', 'E', 'C', 'E', 'Q', 'U', '_', 'P', 'H', '_', 'Q', 'B', 'L', 0, |
| /* 15226 */ 'D', 'P', 'A', 'U', '_', 'H', '_', 'Q', 'B', 'L', 0, |
| /* 15237 */ 'D', 'P', 'S', 'U', '_', 'H', '_', 'Q', 'B', 'L', 0, |
| /* 15248 */ 'L', 'D', 'L', 0, |
| /* 15252 */ 'S', 'D', 'L', 0, |
| /* 15256 */ 'G', 'C', '_', 'L', 'A', 'B', 'E', 'L', 0, |
| /* 15265 */ 'D', 'B', 'G', '_', 'L', 'A', 'B', 'E', 'L', 0, |
| /* 15275 */ 'E', 'H', '_', 'L', 'A', 'B', 'E', 'L', 0, |
| /* 15284 */ 'A', 'N', 'N', 'O', 'T', 'A', 'T', 'I', 'O', 'N', '_', 'L', 'A', 'B', 'E', 'L', 0, |
| /* 15301 */ 'B', 'G', 'E', 'L', 0, |
| /* 15306 */ 'B', 'L', 'E', 'L', 0, |
| /* 15311 */ 'B', 'N', 'E', 'L', 0, |
| /* 15316 */ 'I', 'C', 'A', 'L', 'L', '_', 'B', 'R', 'A', 'N', 'C', 'H', '_', 'F', 'U', 'N', 'N', 'E', 'L', 0, |
| /* 15336 */ 'B', 'C', '1', 'F', 'L', 0, |
| /* 15342 */ 'M', 'A', 'Q', '_', 'S', 'A', '_', 'W', '_', 'P', 'H', 'L', 0, |
| /* 15355 */ 'P', 'R', 'E', 'C', 'E', 'Q', '_', 'W', '_', 'P', 'H', 'L', 0, |
| /* 15368 */ 'M', 'A', 'Q', '_', 'S', '_', 'W', '_', 'P', 'H', 'L', 0, |
| /* 15380 */ 'M', 'U', 'L', 'E', 'Q', '_', 'S', '_', 'W', '_', 'P', 'H', 'L', 0, |
| /* 15394 */ 'G', '_', 'S', 'H', 'L', 0, |
| /* 15400 */ 'G', '_', 'F', 'C', 'E', 'I', 'L', 0, |
| /* 15408 */ 'T', 'A', 'I', 'L', 'C', 'A', 'L', 'L', 0, |
| /* 15417 */ 'H', 'Y', 'P', 'C', 'A', 'L', 'L', 0, |
| /* 15425 */ 'S', 'Y', 'S', 'C', 'A', 'L', 'L', 0, |
| /* 15433 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'T', 'A', 'I', 'L', '_', 'C', 'A', 'L', 'L', 0, |
| /* 15453 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'T', 'Y', 'P', 'E', 'D', '_', 'E', 'V', 'E', 'N', 'T', '_', 'C', 'A', 'L', 'L', 0, |
| /* 15480 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'E', 'V', 'E', 'N', 'T', '_', 'C', 'A', 'L', 'L', 0, |
| /* 15501 */ 'F', 'E', 'N', 'T', 'R', 'Y', '_', 'C', 'A', 'L', 'L', 0, |
| /* 15513 */ 'B', 'G', 'E', 'Z', 'A', 'L', 'L', 0, |
| /* 15521 */ 'B', 'L', 'T', 'Z', 'A', 'L', 'L', 0, |
| /* 15529 */ 'K', 'I', 'L', 'L', 0, |
| /* 15534 */ 'D', 'S', 'L', 'L', 0, |
| /* 15539 */ 'D', 'R', 'O', 'L', 0, |
| /* 15544 */ 'B', 'E', 'Q', 'L', 0, |
| /* 15549 */ 'D', 'S', 'R', 'L', 0, |
| /* 15554 */ 'B', 'C', '1', 'T', 'L', 0, |
| /* 15560 */ 'B', 'G', 'T', 'L', 0, |
| /* 15565 */ 'B', 'L', 'T', 'L', 0, |
| /* 15570 */ 'B', 'G', 'E', 'U', 'L', 0, |
| /* 15576 */ 'B', 'L', 'E', 'U', 'L', 0, |
| /* 15582 */ 'D', 'M', 'U', 'L', 0, |
| /* 15587 */ 'G', '_', 'F', 'M', 'U', 'L', 0, |
| /* 15594 */ 'G', '_', 'M', 'U', 'L', 0, |
| /* 15600 */ 'B', 'G', 'T', 'U', 'L', 0, |
| /* 15606 */ 'B', 'L', 'T', 'U', 'L', 0, |
| /* 15612 */ 'L', 'W', 'L', 0, |
| /* 15616 */ 'S', 'W', 'L', 0, |
| /* 15620 */ 'B', 'G', 'E', 'Z', 'L', 0, |
| /* 15626 */ 'B', 'L', 'E', 'Z', 'L', 0, |
| /* 15632 */ 'B', 'G', 'T', 'Z', 'L', 0, |
| /* 15638 */ 'B', 'L', 'T', 'Z', 'L', 0, |
| /* 15644 */ 'P', 's', 'e', 'u', 'd', 'o', 'C', 'V', 'T', '_', 'D', '6', '4', '_', 'L', 0, |
| /* 15660 */ 'P', 's', 'e', 'u', 'd', 'o', 'C', 'V', 'T', '_', 'S', '_', 'L', 0, |
| /* 15674 */ 'G', '_', 'F', 'R', 'E', 'M', 0, |
| /* 15681 */ 'G', '_', 'S', 'R', 'E', 'M', 0, |
| /* 15688 */ 'G', '_', 'U', 'R', 'E', 'M', 0, |
| /* 15695 */ 'M', 'F', 'G', 'C', '0', '_', 'M', 'M', 0, |
| /* 15704 */ 'M', 'F', 'H', 'G', 'C', '0', '_', 'M', 'M', 0, |
| /* 15714 */ 'M', 'T', 'H', 'G', 'C', '0', '_', 'M', 'M', 0, |
| /* 15724 */ 'M', 'T', 'G', 'C', '0', '_', 'M', 'M', 0, |
| /* 15733 */ 'L', 'D', 'C', '1', '_', 'M', 'M', 0, |
| /* 15741 */ 'S', 'D', 'C', '1', '_', 'M', 'M', 0, |
| /* 15749 */ 'C', 'F', 'C', '1', '_', 'M', 'M', 0, |
| /* 15757 */ 'M', 'F', 'C', '1', '_', 'M', 'M', 0, |
| /* 15765 */ 'C', 'T', 'C', '1', '_', 'M', 'M', 0, |
| /* 15773 */ 'M', 'T', 'C', '1', '_', 'M', 'M', 0, |
| /* 15781 */ 'L', 'W', 'C', '1', '_', 'M', 'M', 0, |
| /* 15789 */ 'S', 'W', 'C', '1', '_', 'M', 'M', 0, |
| /* 15797 */ 'L', 'U', 'X', 'C', '1', '_', 'M', 'M', 0, |
| /* 15806 */ 'S', 'U', 'X', 'C', '1', '_', 'M', 'M', 0, |
| /* 15815 */ 'L', 'W', 'X', 'C', '1', '_', 'M', 'M', 0, |
| /* 15824 */ 'S', 'W', 'X', 'C', '1', '_', 'M', 'M', 0, |
| /* 15833 */ 'M', 'F', 'H', 'C', '1', '_', 'D', '3', '2', '_', 'M', 'M', 0, |
| /* 15846 */ 'M', 'T', 'H', 'C', '1', '_', 'D', '3', '2', '_', 'M', 'M', 0, |
| /* 15859 */ 'F', 'S', 'U', 'B', '_', 'D', '3', '2', '_', 'M', 'M', 0, |
| /* 15871 */ 'N', 'M', 'S', 'U', 'B', '_', 'D', '3', '2', '_', 'M', 'M', 0, |
| /* 15884 */ 'F', 'A', 'D', 'D', '_', 'D', '3', '2', '_', 'M', 'M', 0, |
| /* 15896 */ 'N', 'M', 'A', 'D', 'D', '_', 'D', '3', '2', '_', 'M', 'M', 0, |
| /* 15909 */ 'C', '_', 'N', 'G', 'E', '_', 'D', '3', '2', '_', 'M', 'M', 0, |
| /* 15922 */ 'C', '_', 'N', 'G', 'L', 'E', '_', 'D', '3', '2', '_', 'M', 'M', 0, |
| /* 15936 */ 'C', '_', 'O', 'L', 'E', '_', 'D', '3', '2', '_', 'M', 'M', 0, |
| /* 15949 */ 'C', '_', 'U', 'L', 'E', '_', 'D', '3', '2', '_', 'M', 'M', 0, |
| /* 15962 */ 'C', '_', 'L', 'E', '_', 'D', '3', '2', '_', 'M', 'M', 0, |
| /* 15974 */ 'C', '_', 'S', 'F', '_', 'D', '3', '2', '_', 'M', 'M', 0, |
| /* 15986 */ 'M', 'O', 'V', 'F', '_', 'D', '3', '2', '_', 'M', 'M', 0, |
| /* 15998 */ 'C', '_', 'F', '_', 'D', '3', '2', '_', 'M', 'M', 0, |
| /* 16009 */ 'F', 'N', 'E', 'G', '_', 'D', '3', '2', '_', 'M', 'M', 0, |
| /* 16021 */ 'M', 'O', 'V', 'N', '_', 'I', '_', 'D', '3', '2', '_', 'M', 'M', 0, |
| /* 16035 */ 'M', 'O', 'V', 'Z', '_', 'I', '_', 'D', '3', '2', '_', 'M', 'M', 0, |
| /* 16049 */ 'C', '_', 'N', 'G', 'L', '_', 'D', '3', '2', '_', 'M', 'M', 0, |
| /* 16062 */ 'F', 'M', 'U', 'L', '_', 'D', '3', '2', '_', 'M', 'M', 0, |
| /* 16074 */ 'C', '_', 'U', 'N', '_', 'D', '3', '2', '_', 'M', 'M', 0, |
| /* 16086 */ 'R', 'E', 'C', 'I', 'P', '_', 'D', '3', '2', '_', 'M', 'M', 0, |
| /* 16099 */ 'F', 'C', 'M', 'P', '_', 'D', '3', '2', '_', 'M', 'M', 0, |
| /* 16111 */ 'C', '_', 'S', 'E', 'Q', '_', 'D', '3', '2', '_', 'M', 'M', 0, |
| /* 16124 */ 'C', '_', 'U', 'E', 'Q', '_', 'D', '3', '2', '_', 'M', 'M', 0, |
| /* 16137 */ 'C', '_', 'E', 'Q', '_', 'D', '3', '2', '_', 'M', 'M', 0, |
| /* 16149 */ 'F', 'A', 'B', 'S', '_', 'D', '3', '2', '_', 'M', 'M', 0, |
| /* 16161 */ 'C', 'V', 'T', '_', 'S', '_', 'D', '3', '2', '_', 'M', 'M', 0, |
| /* 16174 */ 'C', '_', 'N', 'G', 'T', '_', 'D', '3', '2', '_', 'M', 'M', 0, |
| /* 16187 */ 'C', '_', 'O', 'L', 'T', '_', 'D', '3', '2', '_', 'M', 'M', 0, |
| /* 16200 */ 'C', '_', 'U', 'L', 'T', '_', 'D', '3', '2', '_', 'M', 'M', 0, |
| /* 16213 */ 'C', '_', 'L', 'T', '_', 'D', '3', '2', '_', 'M', 'M', 0, |
| /* 16225 */ 'F', 'S', 'Q', 'R', 'T', '_', 'D', '3', '2', '_', 'M', 'M', 0, |
| /* 16238 */ 'R', 'S', 'Q', 'R', 'T', '_', 'D', '3', '2', '_', 'M', 'M', 0, |
| /* 16251 */ 'M', 'O', 'V', 'T', '_', 'D', '3', '2', '_', 'M', 'M', 0, |
| /* 16263 */ 'F', 'D', 'I', 'V', '_', 'D', '3', '2', '_', 'M', 'M', 0, |
| /* 16275 */ 'F', 'M', 'O', 'V', '_', 'D', '3', '2', '_', 'M', 'M', 0, |
| /* 16287 */ 'C', 'V', 'T', '_', 'W', '_', 'D', '3', '2', '_', 'M', 'M', 0, |
| /* 16300 */ 'B', 'P', 'O', 'S', 'G', 'E', '3', '2', '_', 'M', 'M', 0, |
| /* 16312 */ 'L', 'W', 'M', '3', '2', '_', 'M', 'M', 0, |
| /* 16321 */ 'S', 'W', 'M', '3', '2', '_', 'M', 'M', 0, |
| /* 16330 */ 'F', 'C', 'M', 'P', '_', 'S', '3', '2', '_', 'M', 'M', 0, |
| /* 16342 */ 'C', 'F', 'C', '2', '_', 'M', 'M', 0, |
| /* 16350 */ 'C', 'T', 'C', '2', '_', 'M', 'M', 0, |
| /* 16358 */ 'A', 'D', 'D', 'I', 'U', 'R', '2', '_', 'M', 'M', 0, |
| /* 16369 */ 'M', 'F', 'H', 'C', '1', '_', 'D', '6', '4', '_', 'M', 'M', 0, |
| /* 16382 */ 'M', 'T', 'H', 'C', '1', '_', 'D', '6', '4', '_', 'M', 'M', 0, |
| /* 16395 */ 'M', 'T', 'C', '1', '_', 'D', '6', '4', '_', 'M', 'M', 0, |
| /* 16407 */ 'F', 'S', 'U', 'B', '_', 'D', '6', '4', '_', 'M', 'M', 0, |
| /* 16419 */ 'F', 'A', 'D', 'D', '_', 'D', '6', '4', '_', 'M', 'M', 0, |
| /* 16431 */ 'C', '_', 'N', 'G', 'E', '_', 'D', '6', '4', '_', 'M', 'M', 0, |
| /* 16444 */ 'C', '_', 'N', 'G', 'L', 'E', '_', 'D', '6', '4', '_', 'M', 'M', 0, |
| /* 16458 */ 'C', '_', 'O', 'L', 'E', '_', 'D', '6', '4', '_', 'M', 'M', 0, |
| /* 16471 */ 'C', '_', 'U', 'L', 'E', '_', 'D', '6', '4', '_', 'M', 'M', 0, |
| /* 16484 */ 'C', '_', 'L', 'E', '_', 'D', '6', '4', '_', 'M', 'M', 0, |
| /* 16496 */ 'C', '_', 'S', 'F', '_', 'D', '6', '4', '_', 'M', 'M', 0, |
| /* 16508 */ 'C', '_', 'F', '_', 'D', '6', '4', '_', 'M', 'M', 0, |
| /* 16519 */ 'F', 'N', 'E', 'G', '_', 'D', '6', '4', '_', 'M', 'M', 0, |
| /* 16531 */ 'C', '_', 'N', 'G', 'L', '_', 'D', '6', '4', '_', 'M', 'M', 0, |
| /* 16544 */ 'F', 'M', 'U', 'L', '_', 'D', '6', '4', '_', 'M', 'M', 0, |
| /* 16556 */ 'C', 'V', 'T', '_', 'L', '_', 'D', '6', '4', '_', 'M', 'M', 0, |
| /* 16569 */ 'C', '_', 'U', 'N', '_', 'D', '6', '4', '_', 'M', 'M', 0, |
| /* 16581 */ 'R', 'E', 'C', 'I', 'P', '_', 'D', '6', '4', '_', 'M', 'M', 0, |
| /* 16594 */ 'C', '_', 'S', 'E', 'Q', '_', 'D', '6', '4', '_', 'M', 'M', 0, |
| /* 16607 */ 'C', '_', 'U', 'E', 'Q', '_', 'D', '6', '4', '_', 'M', 'M', 0, |
| /* 16620 */ 'C', '_', 'E', 'Q', '_', 'D', '6', '4', '_', 'M', 'M', 0, |
| /* 16632 */ 'F', 'A', 'B', 'S', '_', 'D', '6', '4', '_', 'M', 'M', 0, |
| /* 16644 */ 'C', 'V', 'T', '_', 'S', '_', 'D', '6', '4', '_', 'M', 'M', 0, |
| /* 16657 */ 'C', '_', 'N', 'G', 'T', '_', 'D', '6', '4', '_', 'M', 'M', 0, |
| /* 16670 */ 'C', '_', 'O', 'L', 'T', '_', 'D', '6', '4', '_', 'M', 'M', 0, |
| /* 16683 */ 'C', '_', 'U', 'L', 'T', '_', 'D', '6', '4', '_', 'M', 'M', 0, |
| /* 16696 */ 'C', '_', 'L', 'T', '_', 'D', '6', '4', '_', 'M', 'M', 0, |
| /* 16708 */ 'F', 'S', 'Q', 'R', 'T', '_', 'D', '6', '4', '_', 'M', 'M', 0, |
| /* 16721 */ 'R', 'S', 'Q', 'R', 'T', '_', 'D', '6', '4', '_', 'M', 'M', 0, |
| /* 16734 */ 'F', 'D', 'I', 'V', '_', 'D', '6', '4', '_', 'M', 'M', 0, |
| /* 16746 */ 'F', 'M', 'O', 'V', '_', 'D', '6', '4', '_', 'M', 'M', 0, |
| /* 16758 */ 'C', 'V', 'T', '_', 'W', '_', 'D', '6', '4', '_', 'M', 'M', 0, |
| /* 16771 */ 'A', 'D', 'D', 'I', 'U', 'S', '5', '_', 'M', 'M', 0, |
| /* 16782 */ 'S', 'B', '1', '6', '_', 'M', 'M', 0, |
| /* 16790 */ 'J', 'R', 'C', '1', '6', '_', 'M', 'M', 0, |
| /* 16799 */ 'A', 'N', 'D', '1', '6', '_', 'M', 'M', 0, |
| /* 16808 */ 'M', 'O', 'V', 'E', '1', '6', '_', 'M', 'M', 0, |
| /* 16818 */ 'S', 'H', '1', '6', '_', 'M', 'M', 0, |
| /* 16826 */ 'A', 'N', 'D', 'I', '1', '6', '_', 'M', 'M', 0, |
| /* 16836 */ 'M', 'F', 'H', 'I', '1', '6', '_', 'M', 'M', 0, |
| /* 16846 */ 'L', 'I', '1', '6', '_', 'M', 'M', 0, |
| /* 16854 */ 'B', 'R', 'E', 'A', 'K', '1', '6', '_', 'M', 'M', 0, |
| /* 16865 */ 'S', 'L', 'L', '1', '6', '_', 'M', 'M', 0, |
| /* 16874 */ 'S', 'R', 'L', '1', '6', '_', 'M', 'M', 0, |
| /* 16883 */ 'L', 'W', 'M', '1', '6', '_', 'M', 'M', 0, |
| /* 16892 */ 'S', 'W', 'M', '1', '6', '_', 'M', 'M', 0, |
| /* 16901 */ 'M', 'F', 'L', 'O', '1', '6', '_', 'M', 'M', 0, |
| /* 16911 */ 'S', 'D', 'B', 'B', 'P', '1', '6', '_', 'M', 'M', 0, |
| /* 16922 */ 'J', 'R', '1', '6', '_', 'M', 'M', 0, |
| /* 16930 */ 'J', 'A', 'L', 'R', '1', '6', '_', 'M', 'M', 0, |
| /* 16940 */ 'X', 'O', 'R', '1', '6', '_', 'M', 'M', 0, |
| /* 16949 */ 'J', 'A', 'L', 'R', 'S', '1', '6', '_', 'M', 'M', 0, |
| /* 16960 */ 'N', 'O', 'T', '1', '6', '_', 'M', 'M', 0, |
| /* 16969 */ 'L', 'B', 'U', '1', '6', '_', 'M', 'M', 0, |
| /* 16978 */ 'S', 'U', 'B', 'U', '1', '6', '_', 'M', 'M', 0, |
| /* 16988 */ 'A', 'D', 'D', 'U', '1', '6', '_', 'M', 'M', 0, |
| /* 16998 */ 'L', 'H', 'U', '1', '6', '_', 'M', 'M', 0, |
| /* 17007 */ 'L', 'W', '1', '6', '_', 'M', 'M', 0, |
| /* 17015 */ 'S', 'W', '1', '6', '_', 'M', 'M', 0, |
| /* 17023 */ 'B', 'N', 'E', 'Z', '1', '6', '_', 'M', 'M', 0, |
| /* 17033 */ 'B', 'E', 'Q', 'Z', '1', '6', '_', 'M', 'M', 0, |
| /* 17043 */ 'P', 'R', 'E', 'C', 'E', 'U', '_', 'P', 'H', '_', 'Q', 'B', 'L', 'A', '_', 'M', 'M', 0, |
| /* 17061 */ 'P', 'R', 'E', 'C', 'E', 'Q', 'U', '_', 'P', 'H', '_', 'Q', 'B', 'L', 'A', '_', 'M', 'M', 0, |
| /* 17080 */ 'P', 'R', 'E', 'C', 'E', 'U', '_', 'P', 'H', '_', 'Q', 'B', 'R', 'A', '_', 'M', 'M', 0, |
| /* 17098 */ 'P', 'R', 'E', 'C', 'E', 'Q', 'U', '_', 'P', 'H', '_', 'Q', 'B', 'R', 'A', '_', 'M', 'M', 0, |
| /* 17117 */ 'S', 'R', 'A', '_', 'M', 'M', 0, |
| /* 17124 */ 'S', 'E', 'B', '_', 'M', 'M', 0, |
| /* 17131 */ 'E', 'H', 'B', '_', 'M', 'M', 0, |
| /* 17138 */ 'L', 'B', '_', 'M', 'M', 0, |
| /* 17144 */ 'C', 'M', 'P', 'G', 'U', '_', 'L', 'E', '_', 'Q', 'B', '_', 'M', 'M', 0, |
| /* 17159 */ 'C', 'M', 'P', 'U', '_', 'L', 'E', '_', 'Q', 'B', '_', 'M', 'M', 0, |
| /* 17173 */ 'P', 'I', 'C', 'K', '_', 'Q', 'B', '_', 'M', 'M', 0, |
| /* 17184 */ 'S', 'H', 'L', 'L', '_', 'Q', 'B', '_', 'M', 'M', 0, |
| /* 17195 */ 'R', 'E', 'P', 'L', '_', 'Q', 'B', '_', 'M', 'M', 0, |
| /* 17206 */ 'S', 'H', 'R', 'L', '_', 'Q', 'B', '_', 'M', 'M', 0, |
| /* 17217 */ 'C', 'M', 'P', 'G', 'U', '_', 'E', 'Q', '_', 'Q', 'B', '_', 'M', 'M', 0, |
| /* 17232 */ 'C', 'M', 'P', 'U', '_', 'E', 'Q', '_', 'Q', 'B', '_', 'M', 'M', 0, |
| /* 17246 */ 'S', 'U', 'B', 'U', '_', 'S', '_', 'Q', 'B', '_', 'M', 'M', 0, |
| /* 17259 */ 'A', 'D', 'D', 'U', '_', 'S', '_', 'Q', 'B', '_', 'M', 'M', 0, |
| /* 17272 */ 'C', 'M', 'P', 'G', 'U', '_', 'L', 'T', '_', 'Q', 'B', '_', 'M', 'M', 0, |
| /* 17287 */ 'C', 'M', 'P', 'U', '_', 'L', 'T', '_', 'Q', 'B', '_', 'M', 'M', 0, |
| /* 17301 */ 'S', 'U', 'B', 'U', '_', 'Q', 'B', '_', 'M', 'M', 0, |
| /* 17312 */ 'A', 'D', 'D', 'U', '_', 'Q', 'B', '_', 'M', 'M', 0, |
| /* 17323 */ 'S', 'H', 'L', 'L', 'V', '_', 'Q', 'B', '_', 'M', 'M', 0, |
| /* 17335 */ 'R', 'E', 'P', 'L', 'V', '_', 'Q', 'B', '_', 'M', 'M', 0, |
| /* 17347 */ 'S', 'H', 'R', 'L', 'V', '_', 'Q', 'B', '_', 'M', 'M', 0, |
| /* 17359 */ 'R', 'A', 'D', 'D', 'U', '_', 'W', '_', 'Q', 'B', '_', 'M', 'M', 0, |
| /* 17373 */ 'S', 'B', '_', 'M', 'M', 0, |
| /* 17379 */ 'M', 'O', 'D', 'S', 'U', 'B', '_', 'M', 'M', 0, |
| /* 17389 */ 'P', 's', 'e', 'u', 'd', 'o', 'M', 'S', 'U', 'B', '_', 'M', 'M', 0, |
| /* 17403 */ 'S', 'Y', 'N', 'C', '_', 'M', 'M', 0, |
| /* 17411 */ 'A', 'D', 'D', 'I', 'U', 'P', 'C', '_', 'M', 'M', 0, |
| /* 17422 */ 'A', 'D', 'D', 'S', 'C', '_', 'M', 'M', 0, |
| /* 17431 */ 'A', 'D', 'D', 'W', 'C', '_', 'M', 'M', 0, |
| /* 17440 */ 'B', 'N', 'E', 'Z', 'C', '_', 'M', 'M', 0, |
| /* 17449 */ 'B', 'E', 'Q', 'Z', 'C', '_', 'M', 'M', 0, |
| /* 17458 */ 'P', 's', 'e', 'u', 'd', 'o', 'M', 'A', 'D', 'D', '_', 'M', 'M', 0, |
| /* 17472 */ 'A', 'N', 'D', '_', 'M', 'M', 0, |
| /* 17479 */ 'L', 'B', 'E', '_', 'M', 'M', 0, |
| /* 17486 */ 'S', 'B', 'E', '_', 'M', 'M', 0, |
| /* 17493 */ 'S', 'C', 'E', '_', 'M', 'M', 0, |
| /* 17500 */ 'C', 'A', 'C', 'H', 'E', 'E', '_', 'M', 'M', 0, |
| /* 17510 */ 'P', 'R', 'E', 'F', 'E', '_', 'M', 'M', 0, |
| /* 17519 */ 'T', 'G', 'E', '_', 'M', 'M', 0, |
| /* 17526 */ 'C', 'A', 'C', 'H', 'E', '_', 'M', 'M', 0, |
| /* 17535 */ 'L', 'H', 'E', '_', 'M', 'M', 0, |
| /* 17542 */ 'S', 'H', 'E', '_', 'M', 'M', 0, |
| /* 17549 */ 'L', 'L', 'E', '_', 'M', 'M', 0, |
| /* 17556 */ 'L', 'W', 'L', 'E', '_', 'M', 'M', 0, |
| /* 17564 */ 'S', 'W', 'L', 'E', '_', 'M', 'M', 0, |
| /* 17572 */ 'B', 'N', 'E', '_', 'M', 'M', 0, |
| /* 17579 */ 'T', 'N', 'E', '_', 'M', 'M', 0, |
| /* 17586 */ 'L', 'W', 'R', 'E', '_', 'M', 'M', 0, |
| /* 17594 */ 'S', 'W', 'R', 'E', '_', 'M', 'M', 0, |
| /* 17602 */ 'P', 'A', 'U', 'S', 'E', '_', 'M', 'M', 0, |
| /* 17611 */ 'L', 'W', 'E', '_', 'M', 'M', 0, |
| /* 17618 */ 'S', 'W', 'E', '_', 'M', 'M', 0, |
| /* 17625 */ 'L', 'B', 'u', 'E', '_', 'M', 'M', 0, |
| /* 17633 */ 'L', 'H', 'u', 'E', '_', 'M', 'M', 0, |
| /* 17641 */ 'B', 'C', '1', 'F', '_', 'M', 'M', 0, |
| /* 17649 */ 'P', 'R', 'E', 'F', '_', 'M', 'M', 0, |
| /* 17657 */ 'T', 'L', 'B', 'G', 'I', 'N', 'V', 'F', '_', 'M', 'M', 0, |
| /* 17669 */ 'T', 'A', 'I', 'L', 'C', 'A', 'L', 'L', 'R', 'E', 'G', '_', 'M', 'M', 0, |
| /* 17684 */ 'W', 'S', 'B', 'H', '_', 'M', 'M', 0, |
| /* 17692 */ 'S', 'E', 'H', '_', 'M', 'M', 0, |
| /* 17699 */ 'L', 'H', '_', 'M', 'M', 0, |
| /* 17705 */ 'S', 'H', 'R', 'A', '_', 'P', 'H', '_', 'M', 'M', 0, |
| /* 17716 */ 'P', 'R', 'E', 'C', 'R', 'Q', '_', 'Q', 'B', '_', 'P', 'H', '_', 'M', 'M', 0, |
| /* 17732 */ 'P', 'R', 'E', 'C', 'R', 'Q', 'U', '_', 'S', '_', 'Q', 'B', '_', 'P', 'H', '_', 'M', 'M', 0, |
| /* 17751 */ 'C', 'M', 'P', '_', 'L', 'E', '_', 'P', 'H', '_', 'M', 'M', 0, |
| /* 17764 */ 'P', 'I', 'C', 'K', '_', 'P', 'H', '_', 'M', 'M', 0, |
| /* 17775 */ 'S', 'H', 'L', 'L', '_', 'P', 'H', '_', 'M', 'M', 0, |
| /* 17786 */ 'R', 'E', 'P', 'L', '_', 'P', 'H', '_', 'M', 'M', 0, |
| /* 17797 */ 'P', 'A', 'C', 'K', 'R', 'L', '_', 'P', 'H', '_', 'M', 'M', 0, |
| /* 17810 */ 'S', 'U', 'B', 'Q', '_', 'P', 'H', '_', 'M', 'M', 0, |
| /* 17821 */ 'A', 'D', 'D', 'Q', '_', 'P', 'H', '_', 'M', 'M', 0, |
| /* 17832 */ 'C', 'M', 'P', '_', 'E', 'Q', '_', 'P', 'H', '_', 'M', 'M', 0, |
| /* 17845 */ 'S', 'H', 'R', 'A', '_', 'R', '_', 'P', 'H', '_', 'M', 'M', 0, |
| /* 17858 */ 'S', 'H', 'R', 'A', 'V', '_', 'R', '_', 'P', 'H', '_', 'M', 'M', 0, |
| /* 17872 */ 'M', 'U', 'L', 'Q', '_', 'R', 'S', '_', 'P', 'H', '_', 'M', 'M', 0, |
| /* 17886 */ 'S', 'H', 'L', 'L', '_', 'S', '_', 'P', 'H', '_', 'M', 'M', 0, |
| /* 17899 */ 'S', 'U', 'B', 'Q', '_', 'S', '_', 'P', 'H', '_', 'M', 'M', 0, |
| /* 17912 */ 'A', 'D', 'D', 'Q', '_', 'S', '_', 'P', 'H', '_', 'M', 'M', 0, |
| /* 17925 */ 'A', 'B', 'S', 'Q', '_', 'S', '_', 'P', 'H', '_', 'M', 'M', 0, |
| /* 17938 */ 'S', 'H', 'L', 'L', 'V', '_', 'S', '_', 'P', 'H', '_', 'M', 'M', 0, |
| /* 17952 */ 'C', 'M', 'P', '_', 'L', 'T', '_', 'P', 'H', '_', 'M', 'M', 0, |
| /* 17965 */ 'S', 'H', 'R', 'A', 'V', '_', 'P', 'H', '_', 'M', 'M', 0, |
| /* 17977 */ 'S', 'H', 'L', 'L', 'V', '_', 'P', 'H', '_', 'M', 'M', 0, |
| /* 17989 */ 'R', 'E', 'P', 'L', 'V', '_', 'P', 'H', '_', 'M', 'M', 0, |
| /* 18001 */ 'D', 'P', 'A', 'Q', '_', 'S', '_', 'W', '_', 'P', 'H', '_', 'M', 'M', 0, |
| /* 18016 */ 'M', 'U', 'L', 'S', 'A', 'Q', '_', 'S', '_', 'W', '_', 'P', 'H', '_', 'M', 'M', 0, |
| /* 18033 */ 'D', 'P', 'S', 'Q', '_', 'S', '_', 'W', '_', 'P', 'H', '_', 'M', 'M', 0, |
| /* 18048 */ 'S', 'H', '_', 'M', 'M', 0, |
| /* 18054 */ 'E', 'X', 'T', 'R', '_', 'S', '_', 'H', '_', 'M', 'M', 0, |
| /* 18066 */ 'E', 'X', 'T', 'R', 'V', '_', 'S', '_', 'H', '_', 'M', 'M', 0, |
| /* 18079 */ 'S', 'Y', 'N', 'C', 'I', '_', 'M', 'M', 0, |
| /* 18088 */ 'D', 'I', '_', 'M', 'M', 0, |
| /* 18094 */ 'T', 'G', 'E', 'I', '_', 'M', 'M', 0, |
| /* 18102 */ 'T', 'N', 'E', 'I', '_', 'M', 'M', 0, |
| /* 18110 */ 'P', 's', 'e', 'u', 'd', 'o', 'M', 'F', 'H', 'I', '_', 'M', 'M', 0, |
| /* 18124 */ 'P', 's', 'e', 'u', 'd', 'o', 'M', 'T', 'L', 'O', 'H', 'I', '_', 'M', 'M', 0, |
| /* 18140 */ 'M', 'T', 'H', 'I', '_', 'M', 'M', 0, |
| /* 18148 */ 'T', 'E', 'Q', 'I', '_', 'M', 'M', 0, |
| /* 18156 */ 'T', 'L', 'T', 'I', '_', 'M', 'M', 0, |
| /* 18164 */ 'T', 'L', 'B', 'W', 'I', '_', 'M', 'M', 0, |
| /* 18173 */ 'T', 'L', 'B', 'G', 'W', 'I', '_', 'M', 'M', 0, |
| /* 18183 */ 'M', 'O', 'V', 'F', '_', 'I', '_', 'M', 'M', 0, |
| /* 18193 */ 'M', 'O', 'V', 'N', '_', 'I', '_', 'M', 'M', 0, |
| /* 18203 */ 'M', 'O', 'V', 'T', '_', 'I', '_', 'M', 'M', 0, |
| /* 18213 */ 'M', 'O', 'V', 'Z', '_', 'I', '_', 'M', 'M', 0, |
| /* 18223 */ 'J', '_', 'M', 'M', 0, |
| /* 18228 */ 'B', 'R', 'E', 'A', 'K', '_', 'M', 'M', 0, |
| /* 18237 */ 'J', 'A', 'L', '_', 'M', 'M', 0, |
| /* 18244 */ 'B', 'G', 'E', 'Z', 'A', 'L', '_', 'M', 'M', 0, |
| /* 18254 */ 'B', 'L', 'T', 'Z', 'A', 'L', '_', 'M', 'M', 0, |
| /* 18264 */ 'M', 'U', 'L', 'E', 'U', '_', 'S', '_', 'P', 'H', '_', 'Q', 'B', 'L', '_', 'M', 'M', 0, |
| /* 18282 */ 'P', 'R', 'E', 'C', 'E', 'U', '_', 'P', 'H', '_', 'Q', 'B', 'L', '_', 'M', 'M', 0, |
| /* 18299 */ 'P', 'R', 'E', 'C', 'E', 'Q', 'U', '_', 'P', 'H', '_', 'Q', 'B', 'L', '_', 'M', 'M', 0, |
| /* 18317 */ 'D', 'P', 'A', 'U', '_', 'H', '_', 'Q', 'B', 'L', '_', 'M', 'M', 0, |
| /* 18331 */ 'D', 'P', 'S', 'U', '_', 'H', '_', 'Q', 'B', 'L', '_', 'M', 'M', 0, |
| /* 18345 */ 'M', 'A', 'Q', '_', 'S', 'A', '_', 'W', '_', 'P', 'H', 'L', '_', 'M', 'M', 0, |
| /* 18361 */ 'P', 'R', 'E', 'C', 'E', 'Q', '_', 'W', '_', 'P', 'H', 'L', '_', 'M', 'M', 0, |
| /* 18377 */ 'M', 'A', 'Q', '_', 'S', '_', 'W', '_', 'P', 'H', 'L', '_', 'M', 'M', 0, |
| /* 18392 */ 'M', 'U', 'L', 'E', 'Q', '_', 'S', '_', 'W', '_', 'P', 'H', 'L', '_', 'M', 'M', 0, |
| /* 18409 */ 'T', 'A', 'I', 'L', 'C', 'A', 'L', 'L', '_', 'M', 'M', 0, |
| /* 18421 */ 'H', 'Y', 'P', 'C', 'A', 'L', 'L', '_', 'M', 'M', 0, |
| /* 18432 */ 'S', 'Y', 'S', 'C', 'A', 'L', 'L', '_', 'M', 'M', 0, |
| /* 18443 */ 'S', 'L', 'L', '_', 'M', 'M', 0, |
| /* 18450 */ 'S', 'R', 'L', '_', 'M', 'M', 0, |
| /* 18457 */ 'M', 'U', 'L', '_', 'M', 'M', 0, |
| /* 18464 */ 'L', 'W', 'L', '_', 'M', 'M', 0, |
| /* 18471 */ 'S', 'W', 'L', '_', 'M', 'M', 0, |
| /* 18478 */ 'L', 'W', 'M', '_', 'M', 'M', 0, |
| /* 18485 */ 'S', 'W', 'M', '_', 'M', 'M', 0, |
| /* 18492 */ 'C', 'L', 'O', '_', 'M', 'M', 0, |
| /* 18499 */ 'P', 's', 'e', 'u', 'd', 'o', 'M', 'F', 'L', 'O', '_', 'M', 'M', 0, |
| /* 18513 */ 'S', 'H', 'I', 'L', 'O', '_', 'M', 'M', 0, |
| /* 18522 */ 'M', 'T', 'L', 'O', '_', 'M', 'M', 0, |
| /* 18530 */ 'T', 'R', 'A', 'P', '_', 'M', 'M', 0, |
| /* 18538 */ 'S', 'D', 'B', 'B', 'P', '_', 'M', 'M', 0, |
| /* 18547 */ 'T', 'L', 'B', 'P', '_', 'M', 'M', 0, |
| /* 18555 */ 'E', 'X', 'T', 'P', 'D', 'P', '_', 'M', 'M', 0, |
| /* 18565 */ 'M', 'O', 'V', 'E', 'P', '_', 'M', 'M', 0, |
| /* 18574 */ 'T', 'L', 'B', 'G', 'P', '_', 'M', 'M', 0, |
| /* 18583 */ 'L', 'W', 'G', 'P', '_', 'M', 'M', 0, |
| /* 18591 */ 'M', 'T', 'H', 'L', 'I', 'P', '_', 'M', 'M', 0, |
| /* 18601 */ 'S', 'S', 'N', 'O', 'P', '_', 'M', 'M', 0, |
| /* 18610 */ 'A', 'D', 'D', 'I', 'U', 'R', '1', 'S', 'P', '_', 'M', 'M', 0, |
| /* 18623 */ 'R', 'D', 'D', 'S', 'P', '_', 'M', 'M', 0, |
| /* 18632 */ 'W', 'R', 'D', 'S', 'P', '_', 'M', 'M', 0, |
| /* 18641 */ 'L', 'W', 'D', 'S', 'P', '_', 'M', 'M', 0, |
| /* 18650 */ 'S', 'W', 'D', 'S', 'P', '_', 'M', 'M', 0, |
| /* 18659 */ 'M', 'S', 'U', 'B', '_', 'D', 'S', 'P', '_', 'M', 'M', 0, |
| /* 18671 */ 'M', 'A', 'D', 'D', '_', 'D', 'S', 'P', '_', 'M', 'M', 0, |
| /* 18683 */ 'M', 'F', 'H', 'I', '_', 'D', 'S', 'P', '_', 'M', 'M', 0, |
| /* 18695 */ 'M', 'T', 'H', 'I', '_', 'D', 'S', 'P', '_', 'M', 'M', 0, |
| /* 18707 */ 'M', 'F', 'L', 'O', '_', 'D', 'S', 'P', '_', 'M', 'M', 0, |
| /* 18719 */ 'M', 'T', 'L', 'O', '_', 'D', 'S', 'P', '_', 'M', 'M', 0, |
| /* 18731 */ 'M', 'U', 'L', 'T', '_', 'D', 'S', 'P', '_', 'M', 'M', 0, |
| /* 18743 */ 'M', 'S', 'U', 'B', 'U', '_', 'D', 'S', 'P', '_', 'M', 'M', 0, |
| /* 18756 */ 'M', 'A', 'D', 'D', 'U', '_', 'D', 'S', 'P', '_', 'M', 'M', 0, |
| /* 18769 */ 'M', 'U', 'L', 'T', 'U', '_', 'D', 'S', 'P', '_', 'M', 'M', 0, |
| /* 18782 */ 'A', 'D', 'D', 'I', 'U', 'S', 'P', '_', 'M', 'M', 0, |
| /* 18793 */ 'L', 'W', 'S', 'P', '_', 'M', 'M', 0, |
| /* 18801 */ 'S', 'W', 'S', 'P', '_', 'M', 'M', 0, |
| /* 18809 */ 'E', 'X', 'T', 'P', '_', 'M', 'M', 0, |
| /* 18817 */ 'L', 'W', 'P', '_', 'M', 'M', 0, |
| /* 18824 */ 'S', 'W', 'P', '_', 'M', 'M', 0, |
| /* 18831 */ 'B', 'E', 'Q', '_', 'M', 'M', 0, |
| /* 18838 */ 'T', 'E', 'Q', '_', 'M', 'M', 0, |
| /* 18845 */ 'T', 'L', 'B', 'R', '_', 'M', 'M', 0, |
| /* 18853 */ 'M', 'U', 'L', 'E', 'U', '_', 'S', '_', 'P', 'H', '_', 'Q', 'B', 'R', '_', 'M', 'M', 0, |
| /* 18871 */ 'P', 'R', 'E', 'C', 'E', 'U', '_', 'P', 'H', '_', 'Q', 'B', 'R', '_', 'M', 'M', 0, |
| /* 18888 */ 'P', 'R', 'E', 'C', 'E', 'Q', 'U', '_', 'P', 'H', '_', 'Q', 'B', 'R', '_', 'M', 'M', 0, |
| /* 18906 */ 'D', 'P', 'A', 'U', '_', 'H', '_', 'Q', 'B', 'R', '_', 'M', 'M', 0, |
| /* 18920 */ 'D', 'P', 'S', 'U', '_', 'H', '_', 'Q', 'B', 'R', '_', 'M', 'M', 0, |
| /* 18934 */ 'B', 'A', 'L', '_', 'B', 'R', '_', 'M', 'M', 0, |
| /* 18944 */ 'T', 'L', 'B', 'G', 'R', '_', 'M', 'M', 0, |
| /* 18953 */ 'M', 'A', 'Q', '_', 'S', 'A', '_', 'W', '_', 'P', 'H', 'R', '_', 'M', 'M', 0, |
| /* 18969 */ 'P', 'R', 'E', 'C', 'E', 'Q', '_', 'W', '_', 'P', 'H', 'R', '_', 'M', 'M', 0, |
| /* 18985 */ 'M', 'A', 'Q', '_', 'S', '_', 'W', '_', 'P', 'H', 'R', '_', 'M', 'M', 0, |
| /* 19000 */ 'M', 'U', 'L', 'E', 'Q', '_', 'S', '_', 'W', '_', 'P', 'H', 'R', '_', 'M', 'M', 0, |
| /* 19017 */ 'J', 'R', '_', 'M', 'M', 0, |
| /* 19023 */ 'J', 'A', 'L', 'R', '_', 'M', 'M', 0, |
| /* 19031 */ 'N', 'O', 'R', '_', 'M', 'M', 0, |
| /* 19038 */ 'X', 'O', 'R', '_', 'M', 'M', 0, |
| /* 19045 */ 'R', 'O', 'T', 'R', '_', 'M', 'M', 0, |
| /* 19053 */ 'T', 'L', 'B', 'W', 'R', '_', 'M', 'M', 0, |
| /* 19062 */ 'T', 'L', 'B', 'G', 'W', 'R', '_', 'M', 'M', 0, |
| /* 19072 */ 'R', 'D', 'H', 'W', 'R', '_', 'M', 'M', 0, |
| /* 19081 */ 'L', 'W', 'R', '_', 'M', 'M', 0, |
| /* 19088 */ 'S', 'W', 'R', '_', 'M', 'M', 0, |
| /* 19095 */ 'J', 'A', 'L', 'S', '_', 'M', 'M', 0, |
| /* 19103 */ 'B', 'G', 'E', 'Z', 'A', 'L', 'S', '_', 'M', 'M', 0, |
| /* 19114 */ 'B', 'L', 'T', 'Z', 'A', 'L', 'S', '_', 'M', 'M', 0, |
| /* 19125 */ 'I', 'N', 'S', '_', 'M', 'M', 0, |
| /* 19132 */ 'J', 'A', 'L', 'R', 'S', '_', 'M', 'M', 0, |
| /* 19141 */ 'L', 'W', 'X', 'S', '_', 'M', 'M', 0, |
| /* 19149 */ 'C', 'V', 'T', '_', 'D', '3', '2', '_', 'S', '_', 'M', 'M', 0, |
| /* 19162 */ 'C', 'V', 'T', '_', 'D', '6', '4', '_', 'S', '_', 'M', 'M', 0, |
| /* 19175 */ 'F', 'S', 'U', 'B', '_', 'S', '_', 'M', 'M', 0, |
| /* 19185 */ 'N', 'M', 'S', 'U', 'B', '_', 'S', '_', 'M', 'M', 0, |
| /* 19196 */ 'F', 'A', 'D', 'D', '_', 'S', '_', 'M', 'M', 0, |
| /* 19206 */ 'N', 'M', 'A', 'D', 'D', '_', 'S', '_', 'M', 'M', 0, |
| /* 19217 */ 'C', '_', 'N', 'G', 'E', '_', 'S', '_', 'M', 'M', 0, |
| /* 19228 */ 'C', '_', 'N', 'G', 'L', 'E', '_', 'S', '_', 'M', 'M', 0, |
| /* 19240 */ 'C', '_', 'O', 'L', 'E', '_', 'S', '_', 'M', 'M', 0, |
| /* 19251 */ 'C', '_', 'U', 'L', 'E', '_', 'S', '_', 'M', 'M', 0, |
| /* 19262 */ 'C', '_', 'L', 'E', '_', 'S', '_', 'M', 'M', 0, |
| /* 19272 */ 'C', '_', 'S', 'F', '_', 'S', '_', 'M', 'M', 0, |
| /* 19282 */ 'M', 'O', 'V', 'F', '_', 'S', '_', 'M', 'M', 0, |
| /* 19292 */ 'C', '_', 'F', '_', 'S', '_', 'M', 'M', 0, |
| /* 19301 */ 'F', 'N', 'E', 'G', '_', 'S', '_', 'M', 'M', 0, |
| /* 19311 */ 'M', 'O', 'V', 'N', '_', 'I', '_', 'S', '_', 'M', 'M', 0, |
| /* 19323 */ 'M', 'O', 'V', 'Z', '_', 'I', '_', 'S', '_', 'M', 'M', 0, |
| /* 19335 */ 'C', '_', 'N', 'G', 'L', '_', 'S', '_', 'M', 'M', 0, |
| /* 19346 */ 'F', 'M', 'U', 'L', '_', 'S', '_', 'M', 'M', 0, |
| /* 19356 */ 'C', 'V', 'T', '_', 'L', '_', 'S', '_', 'M', 'M', 0, |
| /* 19367 */ 'C', '_', 'U', 'N', '_', 'S', '_', 'M', 'M', 0, |
| /* 19377 */ 'R', 'E', 'C', 'I', 'P', '_', 'S', '_', 'M', 'M', 0, |
| /* 19388 */ 'C', '_', 'S', 'E', 'Q', '_', 'S', '_', 'M', 'M', 0, |
| /* 19399 */ 'C', '_', 'U', 'E', 'Q', '_', 'S', '_', 'M', 'M', 0, |
| /* 19410 */ 'C', '_', 'E', 'Q', '_', 'S', '_', 'M', 'M', 0, |
| /* 19420 */ 'F', 'A', 'B', 'S', '_', 'S', '_', 'M', 'M', 0, |
| /* 19430 */ 'C', '_', 'N', 'G', 'T', '_', 'S', '_', 'M', 'M', 0, |
| /* 19441 */ 'C', '_', 'O', 'L', 'T', '_', 'S', '_', 'M', 'M', 0, |
| /* 19452 */ 'C', '_', 'U', 'L', 'T', '_', 'S', '_', 'M', 'M', 0, |
| /* 19463 */ 'C', '_', 'L', 'T', '_', 'S', '_', 'M', 'M', 0, |
| /* 19473 */ 'F', 'S', 'Q', 'R', 'T', '_', 'S', '_', 'M', 'M', 0, |
| /* 19484 */ 'R', 'S', 'Q', 'R', 'T', '_', 'S', '_', 'M', 'M', 0, |
| /* 19495 */ 'M', 'O', 'V', 'T', '_', 'S', '_', 'M', 'M', 0, |
| /* 19505 */ 'F', 'D', 'I', 'V', '_', 'S', '_', 'M', 'M', 0, |
| /* 19515 */ 'F', 'M', 'O', 'V', '_', 'S', '_', 'M', 'M', 0, |
| /* 19525 */ 'T', 'R', 'U', 'N', 'C', '_', 'W', '_', 'S', '_', 'M', 'M', 0, |
| /* 19538 */ 'R', 'O', 'U', 'N', 'D', '_', 'W', '_', 'S', '_', 'M', 'M', 0, |
| /* 19551 */ 'C', 'E', 'I', 'L', '_', 'W', '_', 'S', '_', 'M', 'M', 0, |
| /* 19563 */ 'F', 'L', 'O', 'O', 'R', '_', 'W', '_', 'S', '_', 'M', 'M', 0, |
| /* 19576 */ 'C', 'V', 'T', '_', 'W', '_', 'S', '_', 'M', 'M', 0, |
| /* 19587 */ 'B', 'C', '1', 'T', '_', 'M', 'M', 0, |
| /* 19595 */ 'D', 'E', 'R', 'E', 'T', '_', 'M', 'M', 0, |
| /* 19604 */ 'W', 'A', 'I', 'T', '_', 'M', 'M', 0, |
| /* 19612 */ 'S', 'L', 'T', '_', 'M', 'M', 0, |
| /* 19619 */ 'T', 'L', 'T', '_', 'M', 'M', 0, |
| /* 19626 */ 'P', 's', 'e', 'u', 'd', 'o', 'M', 'U', 'L', 'T', '_', 'M', 'M', 0, |
| /* 19640 */ 'E', 'X', 'T', '_', 'M', 'M', 0, |
| /* 19647 */ 'P', 's', 'e', 'u', 'd', 'o', 'M', 'S', 'U', 'B', 'U', '_', 'M', 'M', 0, |
| /* 19662 */ 'P', 's', 'e', 'u', 'd', 'o', 'M', 'A', 'D', 'D', 'U', '_', 'M', 'M', 0, |
| /* 19677 */ 'T', 'G', 'E', 'U', '_', 'M', 'M', 0, |
| /* 19685 */ 'T', 'G', 'E', 'I', 'U', '_', 'M', 'M', 0, |
| /* 19694 */ 'T', 'L', 'T', 'I', 'U', '_', 'M', 'M', 0, |
| /* 19703 */ 'T', 'L', 'T', 'U', '_', 'M', 'M', 0, |
| /* 19711 */ 'L', 'W', 'U', '_', 'M', 'M', 0, |
| /* 19718 */ 'S', 'R', 'A', 'V', '_', 'M', 'M', 0, |
| /* 19726 */ 'B', 'I', 'T', 'R', 'E', 'V', '_', 'M', 'M', 0, |
| /* 19736 */ 'S', 'D', 'I', 'V', '_', 'M', 'M', 0, |
| /* 19744 */ 'U', 'D', 'I', 'V', '_', 'M', 'M', 0, |
| /* 19752 */ 'S', 'L', 'L', 'V', '_', 'M', 'M', 0, |
| /* 19760 */ 'S', 'R', 'L', 'V', '_', 'M', 'M', 0, |
| /* 19768 */ 'T', 'L', 'B', 'G', 'I', 'N', 'V', '_', 'M', 'M', 0, |
| /* 19779 */ 'S', 'H', 'I', 'L', 'O', 'V', '_', 'M', 'M', 0, |
| /* 19789 */ 'E', 'X', 'T', 'P', 'D', 'P', 'V', '_', 'M', 'M', 0, |
| /* 19800 */ 'E', 'X', 'T', 'P', 'V', '_', 'M', 'M', 0, |
| /* 19809 */ 'R', 'O', 'T', 'R', 'V', '_', 'M', 'M', 0, |
| /* 19818 */ 'I', 'N', 'S', 'V', '_', 'M', 'M', 0, |
| /* 19826 */ 'L', 'W', '_', 'M', 'M', 0, |
| /* 19832 */ 'S', 'W', '_', 'M', 'M', 0, |
| /* 19838 */ 'C', 'V', 'T', '_', 'D', '3', '2', '_', 'W', '_', 'M', 'M', 0, |
| /* 19851 */ 'C', 'V', 'T', '_', 'D', '6', '4', '_', 'W', '_', 'M', 'M', 0, |
| /* 19864 */ 'T', 'R', 'U', 'N', 'C', '_', 'W', '_', 'M', 'M', 0, |
| /* 19875 */ 'R', 'O', 'U', 'N', 'D', '_', 'W', '_', 'M', 'M', 0, |
| /* 19886 */ 'P', 'R', 'E', 'C', 'R', 'Q', '_', 'P', 'H', '_', 'W', '_', 'M', 'M', 0, |
| /* 19901 */ 'P', 'R', 'E', 'C', 'R', 'Q', '_', 'R', 'S', '_', 'P', 'H', '_', 'W', '_', 'M', 'M', 0, |
| /* 19919 */ 'C', 'E', 'I', 'L', '_', 'W', '_', 'M', 'M', 0, |
| /* 19929 */ 'D', 'P', 'A', 'Q', '_', 'S', 'A', '_', 'L', '_', 'W', '_', 'M', 'M', 0, |
| /* 19944 */ 'D', 'P', 'S', 'Q', '_', 'S', 'A', '_', 'L', '_', 'W', '_', 'M', 'M', 0, |
| /* 19959 */ 'F', 'L', 'O', 'O', 'R', '_', 'W', '_', 'M', 'M', 0, |
| /* 19970 */ 'E', 'X', 'T', 'R', '_', 'W', '_', 'M', 'M', 0, |
| /* 19980 */ 'S', 'H', 'R', 'A', '_', 'R', '_', 'W', '_', 'M', 'M', 0, |
| /* 19992 */ 'E', 'X', 'T', 'R', '_', 'R', '_', 'W', '_', 'M', 'M', 0, |
| /* 20004 */ 'S', 'H', 'R', 'A', 'V', '_', 'R', '_', 'W', '_', 'M', 'M', 0, |
| /* 20017 */ 'E', 'X', 'T', 'R', 'V', '_', 'R', '_', 'W', '_', 'M', 'M', 0, |
| /* 20030 */ 'E', 'X', 'T', 'R', '_', 'R', 'S', '_', 'W', '_', 'M', 'M', 0, |
| /* 20043 */ 'E', 'X', 'T', 'R', 'V', '_', 'R', 'S', '_', 'W', '_', 'M', 'M', 0, |
| /* 20057 */ 'S', 'H', 'L', 'L', '_', 'S', '_', 'W', '_', 'M', 'M', 0, |
| /* 20069 */ 'S', 'U', 'B', 'Q', '_', 'S', '_', 'W', '_', 'M', 'M', 0, |
| /* 20081 */ 'A', 'D', 'D', 'Q', '_', 'S', '_', 'W', '_', 'M', 'M', 0, |
| /* 20093 */ 'A', 'B', 'S', 'Q', '_', 'S', '_', 'W', '_', 'M', 'M', 0, |
| /* 20105 */ 'C', 'V', 'T', '_', 'S', '_', 'W', '_', 'M', 'M', 0, |
| /* 20116 */ 'S', 'H', 'L', 'L', 'V', '_', 'S', '_', 'W', '_', 'M', 'M', 0, |
| /* 20129 */ 'E', 'X', 'T', 'R', 'V', '_', 'W', '_', 'M', 'M', 0, |
| /* 20140 */ 'P', 'R', 'E', 'F', 'X', '_', 'M', 'M', 0, |
| /* 20149 */ 'L', 'H', 'X', '_', 'M', 'M', 0, |
| /* 20156 */ 'J', 'A', 'L', 'X', '_', 'M', 'M', 0, |
| /* 20164 */ 'L', 'B', 'U', 'X', '_', 'M', 'M', 0, |
| /* 20172 */ 'L', 'W', 'X', '_', 'M', 'M', 0, |
| /* 20179 */ 'B', 'G', 'E', 'Z', '_', 'M', 'M', 0, |
| /* 20187 */ 'B', 'L', 'E', 'Z', '_', 'M', 'M', 0, |
| /* 20195 */ 'C', 'L', 'Z', '_', 'M', 'M', 0, |
| /* 20202 */ 'B', 'G', 'T', 'Z', '_', 'M', 'M', 0, |
| /* 20210 */ 'B', 'L', 'T', 'Z', '_', 'M', 'M', 0, |
| /* 20218 */ 'P', 's', 'e', 'u', 'd', 'o', 'I', 'n', 'd', 'i', 'r', 'e', 'c', 't', 'B', 'r', 'a', 'n', 'c', 'h', '_', 'M', 'M', 0, |
| /* 20242 */ 'A', 'D', 'D', 'i', '_', 'M', 'M', 0, |
| /* 20250 */ 'A', 'N', 'D', 'i', '_', 'M', 'M', 0, |
| /* 20258 */ 'X', 'O', 'R', 'i', '_', 'M', 'M', 0, |
| /* 20266 */ 'S', 'L', 'T', 'i', '_', 'M', 'M', 0, |
| /* 20274 */ 'L', 'U', 'i', '_', 'M', 'M', 0, |
| /* 20281 */ 'L', 'B', 'u', '_', 'M', 'M', 0, |
| /* 20288 */ 'S', 'U', 'B', 'u', '_', 'M', 'M', 0, |
| /* 20296 */ 'A', 'D', 'D', 'u', '_', 'M', 'M', 0, |
| /* 20304 */ 'L', 'H', 'u', '_', 'M', 'M', 0, |
| /* 20311 */ 'S', 'L', 'T', 'u', '_', 'M', 'M', 0, |
| /* 20319 */ 'P', 's', 'e', 'u', 'd', 'o', 'M', 'U', 'L', 'T', 'u', '_', 'M', 'M', 0, |
| /* 20334 */ 'L', 'E', 'A', '_', 'A', 'D', 'D', 'i', 'u', '_', 'M', 'M', 0, |
| /* 20347 */ 'S', 'L', 'T', 'i', 'u', '_', 'M', 'M', 0, |
| /* 20356 */ 'I', 'N', 'L', 'I', 'N', 'E', 'A', 'S', 'M', 0, |
| /* 20366 */ 'D', 'I', 'N', 'S', 'M', 0, |
| /* 20372 */ 'D', 'E', 'X', 'T', 'M', 0, |
| /* 20378 */ 'G', '_', 'F', 'M', 'I', 'N', 'I', 'M', 'U', 'M', 0, |
| /* 20389 */ 'G', '_', 'F', 'M', 'A', 'X', 'I', 'M', 'U', 'M', 0, |
| /* 20400 */ 'G', '_', 'F', 'M', 'I', 'N', 'N', 'U', 'M', 0, |
| /* 20410 */ 'G', '_', 'F', 'M', 'A', 'X', 'N', 'U', 'M', 0, |
| /* 20420 */ 'B', 'A', 'L', 'I', 'G', 'N', 0, |
| /* 20427 */ 'D', 'A', 'L', 'I', 'G', 'N', 0, |
| /* 20434 */ 'G', '_', 'F', 'C', 'O', 'P', 'Y', 'S', 'I', 'G', 'N', 0, |
| /* 20446 */ 'G', '_', 'S', 'M', 'I', 'N', 0, |
| /* 20453 */ 'G', '_', 'U', 'M', 'I', 'N', 0, |
| /* 20460 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'U', 'M', 'I', 'N', 0, |
| /* 20477 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'M', 'I', 'N', 0, |
| /* 20493 */ 'G', '_', 'F', 'S', 'I', 'N', 0, |
| /* 20500 */ 'D', 'M', 'F', 'C', '2', '_', 'O', 'C', 'T', 'E', 'O', 'N', 0, |
| /* 20513 */ 'D', 'M', 'T', 'C', '2', '_', 'O', 'C', 'T', 'E', 'O', 'N', 0, |
| /* 20526 */ 'C', 'F', 'I', '_', 'I', 'N', 'S', 'T', 'R', 'U', 'C', 'T', 'I', 'O', 'N', 0, |
| /* 20542 */ 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'D', 'O', 'W', 'N', 0, |
| /* 20559 */ 'G', '_', 'S', 'S', 'U', 'B', 'O', 0, |
| /* 20567 */ 'G', '_', 'U', 'S', 'U', 'B', 'O', 0, |
| /* 20575 */ 'G', '_', 'S', 'A', 'D', 'D', 'O', 0, |
| /* 20583 */ 'G', '_', 'U', 'A', 'D', 'D', 'O', 0, |
| /* 20591 */ 'F', 'E', 'X', 'P', '2', '_', 'D', '_', '1', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0, |
| /* 20608 */ 'F', 'E', 'X', 'P', '2', '_', 'W', '_', '1', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0, |
| /* 20625 */ 'B', 'P', 'O', 'S', 'G', 'E', '3', '2', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0, |
| /* 20641 */ 'I', 'N', 'S', 'E', 'R', 'T', '_', 'B', '_', 'V', 'I', 'D', 'X', '6', '4', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0, |
| /* 20664 */ 'I', 'N', 'S', 'E', 'R', 'T', '_', 'F', 'D', '_', 'V', 'I', 'D', 'X', '6', '4', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0, |
| /* 20688 */ 'I', 'N', 'S', 'E', 'R', 'T', '_', 'D', '_', 'V', 'I', 'D', 'X', '6', '4', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0, |
| /* 20711 */ 'I', 'N', 'S', 'E', 'R', 'T', '_', 'H', '_', 'V', 'I', 'D', 'X', '6', '4', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0, |
| /* 20734 */ 'I', 'N', 'S', 'E', 'R', 'T', '_', 'F', 'W', '_', 'V', 'I', 'D', 'X', '6', '4', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0, |
| /* 20758 */ 'I', 'N', 'S', 'E', 'R', 'T', '_', 'W', '_', 'V', 'I', 'D', 'X', '6', '4', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0, |
| /* 20781 */ 'S', 'N', 'Z', '_', 'B', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0, |
| /* 20794 */ 'S', 'Z', '_', 'B', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0, |
| /* 20806 */ 'B', 'S', 'E', 'L', '_', 'F', 'D', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0, |
| /* 20821 */ 'F', 'I', 'L', 'L', '_', 'F', 'D', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0, |
| /* 20836 */ 'I', 'N', 'S', 'E', 'R', 'T', '_', 'F', 'D', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0, |
| /* 20853 */ 'C', 'O', 'P', 'Y', '_', 'F', 'D', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0, |
| /* 20868 */ 'M', 'S', 'A', '_', 'F', 'P', '_', 'E', 'X', 'T', 'E', 'N', 'D', '_', 'D', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0, |
| /* 20891 */ 'M', 'S', 'A', '_', 'F', 'P', '_', 'R', 'O', 'U', 'N', 'D', '_', 'D', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0, |
| /* 20913 */ 'B', 'S', 'E', 'L', '_', 'D', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0, |
| /* 20927 */ 'A', 'N', 'D', '_', 'V', '_', 'D', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0, |
| /* 20942 */ 'N', 'O', 'R', '_', 'V', '_', 'D', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0, |
| /* 20957 */ 'X', 'O', 'R', '_', 'V', '_', 'D', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0, |
| /* 20972 */ 'S', 'N', 'Z', '_', 'D', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0, |
| /* 20985 */ 'S', 'Z', '_', 'D', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0, |
| /* 20997 */ 'B', 'S', 'E', 'L', '_', 'H', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0, |
| /* 21011 */ 'A', 'N', 'D', '_', 'V', '_', 'H', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0, |
| /* 21026 */ 'N', 'O', 'R', '_', 'V', '_', 'H', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0, |
| /* 21041 */ 'X', 'O', 'R', '_', 'V', '_', 'H', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0, |
| /* 21056 */ 'S', 'N', 'Z', '_', 'H', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0, |
| /* 21069 */ 'S', 'Z', '_', 'H', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0, |
| /* 21081 */ 'S', 'N', 'Z', '_', 'V', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0, |
| /* 21094 */ 'S', 'Z', '_', 'V', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0, |
| /* 21106 */ 'B', 'S', 'E', 'L', '_', 'F', 'W', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0, |
| /* 21121 */ 'F', 'I', 'L', 'L', '_', 'F', 'W', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0, |
| /* 21136 */ 'I', 'N', 'S', 'E', 'R', 'T', '_', 'F', 'W', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0, |
| /* 21153 */ 'C', 'O', 'P', 'Y', '_', 'F', 'W', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0, |
| /* 21168 */ 'M', 'S', 'A', '_', 'F', 'P', '_', 'E', 'X', 'T', 'E', 'N', 'D', '_', 'W', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0, |
| /* 21191 */ 'M', 'S', 'A', '_', 'F', 'P', '_', 'R', 'O', 'U', 'N', 'D', '_', 'W', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0, |
| /* 21213 */ 'B', 'S', 'E', 'L', '_', 'W', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0, |
| /* 21227 */ 'A', 'N', 'D', '_', 'V', '_', 'W', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0, |
| /* 21242 */ 'N', 'O', 'R', '_', 'V', '_', 'W', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0, |
| /* 21257 */ 'X', 'O', 'R', '_', 'V', '_', 'W', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0, |
| /* 21272 */ 'S', 'N', 'Z', '_', 'W', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0, |
| /* 21285 */ 'S', 'Z', '_', 'W', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0, |
| /* 21297 */ 'I', 'N', 'S', 'E', 'R', 'T', '_', 'B', '_', 'V', 'I', 'D', 'X', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0, |
| /* 21318 */ 'I', 'N', 'S', 'E', 'R', 'T', '_', 'F', 'D', '_', 'V', 'I', 'D', 'X', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0, |
| /* 21340 */ 'I', 'N', 'S', 'E', 'R', 'T', '_', 'D', '_', 'V', 'I', 'D', 'X', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0, |
| /* 21361 */ 'I', 'N', 'S', 'E', 'R', 'T', '_', 'H', '_', 'V', 'I', 'D', 'X', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0, |
| /* 21382 */ 'I', 'N', 'S', 'E', 'R', 'T', '_', 'F', 'W', '_', 'V', 'I', 'D', 'X', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0, |
| /* 21404 */ 'I', 'N', 'S', 'E', 'R', 'T', '_', 'W', '_', 'V', 'I', 'D', 'X', '_', 'P', 'S', 'E', 'U', 'D', 'O', 0, |
| /* 21425 */ 'D', 'C', 'L', 'O', 0, |
| /* 21430 */ 'P', 's', 'e', 'u', 'd', 'o', 'M', 'F', 'L', 'O', 0, |
| /* 21441 */ 'S', 'H', 'I', 'L', 'O', 0, |
| /* 21447 */ 'M', 'F', 'T', 'L', 'O', 0, |
| /* 21453 */ 'M', 'T', 'L', 'O', 0, |
| /* 21458 */ 'M', 'T', 'T', 'L', 'O', 0, |
| /* 21464 */ 'G', '_', 'S', 'M', 'U', 'L', 'O', 0, |
| /* 21472 */ 'G', '_', 'U', 'M', 'U', 'L', 'O', 0, |
| /* 21480 */ 'S', 'T', 'A', 'C', 'K', 'M', 'A', 'P', 0, |
| /* 21489 */ 'T', 'R', 'A', 'P', 0, |
| /* 21494 */ 'G', '_', 'B', 'S', 'W', 'A', 'P', 0, |
| /* 21502 */ 'D', 'B', 'I', 'T', 'S', 'W', 'A', 'P', 0, |
| /* 21511 */ 'S', 'D', 'B', 'B', 'P', 0, |
| /* 21517 */ 'T', 'L', 'B', 'P', 0, |
| /* 21522 */ 'E', 'X', 'T', 'P', 'D', 'P', 0, |
| /* 21529 */ 'G', '_', 'S', 'I', 'T', 'O', 'F', 'P', 0, |
| /* 21538 */ 'G', '_', 'U', 'I', 'T', 'O', 'F', 'P', 0, |
| /* 21547 */ 'T', 'L', 'B', 'G', 'P', 0, |
| /* 21553 */ 'M', 'T', 'H', 'L', 'I', 'P', 0, |
| /* 21560 */ 'G', '_', 'F', 'C', 'M', 'P', 0, |
| /* 21567 */ 'G', '_', 'I', 'C', 'M', 'P', 0, |
| /* 21574 */ 'S', 'S', 'N', 'O', 'P', 0, |
| /* 21580 */ 'D', 'P', 'O', 'P', 0, |
| /* 21585 */ 'G', '_', 'C', 'T', 'P', 'O', 'P', 0, |
| /* 21593 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'O', 'P', 0, |
| /* 21606 */ 'F', 'A', 'U', 'L', 'T', 'I', 'N', 'G', '_', 'O', 'P', 0, |
| /* 21618 */ 'L', 'O', 'A', 'D', '_', 'A', 'C', 'C', '6', '4', 'D', 'S', 'P', 0, |
| /* 21632 */ 'S', 'T', 'O', 'R', 'E', '_', 'A', 'C', 'C', '6', '4', 'D', 'S', 'P', 0, |
| /* 21647 */ 'R', 'D', 'D', 'S', 'P', 0, |
| /* 21653 */ 'W', 'R', 'D', 'S', 'P', 0, |
| /* 21659 */ 'M', 'F', 'T', 'D', 'S', 'P', 0, |
| /* 21666 */ 'M', 'T', 'T', 'D', 'S', 'P', 0, |
| /* 21673 */ 'L', 'W', 'D', 'S', 'P', 0, |
| /* 21679 */ 'S', 'W', 'D', 'S', 'P', 0, |
| /* 21685 */ 'M', 'S', 'U', 'B', '_', 'D', 'S', 'P', 0, |
| /* 21694 */ 'M', 'A', 'D', 'D', '_', 'D', 'S', 'P', 0, |
| /* 21703 */ 'L', 'O', 'A', 'D', '_', 'C', 'C', 'O', 'N', 'D', '_', 'D', 'S', 'P', 0, |
| /* 21718 */ 'S', 'T', 'O', 'R', 'E', '_', 'C', 'C', 'O', 'N', 'D', '_', 'D', 'S', 'P', 0, |
| /* 21734 */ 'M', 'F', 'H', 'I', '_', 'D', 'S', 'P', 0, |
| /* 21743 */ 'P', 's', 'e', 'u', 'd', 'o', 'M', 'T', 'L', 'O', 'H', 'I', '_', 'D', 'S', 'P', 0, |
| /* 21760 */ 'M', 'T', 'H', 'I', '_', 'D', 'S', 'P', 0, |
| /* 21769 */ 'M', 'F', 'L', 'O', '_', 'D', 'S', 'P', 0, |
| /* 21778 */ 'M', 'T', 'L', 'O', '_', 'D', 'S', 'P', 0, |
| /* 21787 */ 'M', 'U', 'L', 'T', '_', 'D', 'S', 'P', 0, |
| /* 21796 */ 'M', 'S', 'U', 'B', 'U', '_', 'D', 'S', 'P', 0, |
| /* 21806 */ 'M', 'A', 'D', 'D', 'U', '_', 'D', 'S', 'P', 0, |
| /* 21816 */ 'M', 'U', 'L', 'T', 'U', '_', 'D', 'S', 'P', 0, |
| /* 21826 */ 'J', 'R', 'A', 'D', 'D', 'I', 'U', 'S', 'P', 0, |
| /* 21836 */ 'E', 'X', 'T', 'P', 0, |
| /* 21841 */ 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'U', 'P', 0, |
| /* 21856 */ 'D', 'V', 'P', 0, |
| /* 21860 */ 'E', 'V', 'P', 0, |
| /* 21864 */ 'G', '_', 'F', 'E', 'X', 'P', 0, |
| /* 21871 */ 'B', 'E', 'Q', 0, |
| /* 21875 */ 'S', 'E', 'Q', 0, |
| /* 21879 */ 'T', 'E', 'Q', 0, |
| /* 21883 */ 'T', 'L', 'B', 'R', 0, |
| /* 21888 */ 'M', 'U', 'L', 'E', 'U', '_', 'S', '_', 'P', 'H', '_', 'Q', 'B', 'R', 0, |
| /* 21903 */ 'P', 'R', 'E', 'C', 'E', 'U', '_', 'P', 'H', '_', 'Q', 'B', 'R', 0, |
| /* 21917 */ 'P', 'R', 'E', 'C', 'E', 'Q', 'U', '_', 'P', 'H', '_', 'Q', 'B', 'R', 0, |
| /* 21932 */ 'D', 'P', 'A', 'U', '_', 'H', '_', 'Q', 'B', 'R', 0, |
| /* 21943 */ 'D', 'P', 'S', 'U', '_', 'H', '_', 'Q', 'B', 'R', 0, |
| /* 21954 */ 'G', '_', 'B', 'R', 0, |
| /* 21959 */ 'B', 'A', 'L', '_', 'B', 'R', 0, |
| /* 21966 */ 'I', 'N', 'L', 'I', 'N', 'E', 'A', 'S', 'M', '_', 'B', 'R', 0, |
| /* 21979 */ 'G', '_', 'B', 'L', 'O', 'C', 'K', '_', 'A', 'D', 'D', 'R', 0, |
| /* 21992 */ 'L', 'D', 'R', 0, |
| /* 21996 */ 'S', 'D', 'R', 0, |
| /* 22000 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'F', 'U', 'N', 'C', 'T', 'I', 'O', 'N', '_', 'E', 'N', 'T', 'E', 'R', 0, |
| /* 22025 */ 'G', '_', 'R', 'E', 'A', 'D', 'C', 'Y', 'C', 'L', 'E', 'C', 'O', 'U', 'N', 'T', 'E', 'R', 0, |
| /* 22044 */ 'G', '_', 'R', 'E', 'A', 'D', '_', 'R', 'E', 'G', 'I', 'S', 'T', 'E', 'R', 0, |
| /* 22060 */ 'G', '_', 'W', 'R', 'I', 'T', 'E', '_', 'R', 'E', 'G', 'I', 'S', 'T', 'E', 'R', 0, |
| /* 22077 */ 'T', 'L', 'B', 'G', 'R', 0, |
| /* 22083 */ 'L', 'o', 'a', 'd', 'I', 'm', 'm', 'D', 'o', 'u', 'b', 'l', 'e', 'F', 'G', 'R', 0, |
| /* 22100 */ 'L', 'o', 'a', 'd', 'I', 'm', 'm', 'S', 'i', 'n', 'g', 'l', 'e', 'F', 'G', 'R', 0, |
| /* 22117 */ 'M', 'A', 'Q', '_', 'S', 'A', '_', 'W', '_', 'P', 'H', 'R', 0, |
| /* 22130 */ 'P', 'R', 'E', 'C', 'E', 'Q', '_', 'W', '_', 'P', 'H', 'R', 0, |
| /* 22143 */ 'M', 'A', 'Q', '_', 'S', '_', 'W', '_', 'P', 'H', 'R', 0, |
| /* 22155 */ 'M', 'U', 'L', 'E', 'Q', '_', 'S', '_', 'W', '_', 'P', 'H', 'R', 0, |
| /* 22169 */ 'G', '_', 'A', 'S', 'H', 'R', 0, |
| /* 22176 */ 'G', '_', 'L', 'S', 'H', 'R', 0, |
| /* 22183 */ 'J', 'R', 0, |
| /* 22186 */ 'J', 'A', 'L', 'R', 0, |
| /* 22191 */ 'N', 'O', 'R', 0, |
| /* 22195 */ 'G', '_', 'F', 'F', 'L', 'O', 'O', 'R', 0, |
| /* 22204 */ 'D', 'R', 'O', 'R', 0, |
| /* 22209 */ 'G', '_', 'B', 'U', 'I', 'L', 'D', '_', 'V', 'E', 'C', 'T', 'O', 'R', 0, |
| /* 22224 */ 'G', '_', 'S', 'H', 'U', 'F', 'F', 'L', 'E', '_', 'V', 'E', 'C', 'T', 'O', 'R', 0, |
| /* 22241 */ 'G', '_', 'X', 'O', 'R', 0, |
| /* 22247 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'X', 'O', 'R', 0, |
| /* 22263 */ 'G', '_', 'O', 'R', 0, |
| /* 22268 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'O', 'R', 0, |
| /* 22283 */ 'M', 'F', 'T', 'G', 'P', 'R', 0, |
| /* 22290 */ 'M', 'T', 'T', 'G', 'P', 'R', 0, |
| /* 22297 */ 'L', 'o', 'a', 'd', 'I', 'm', 'm', 'D', 'o', 'u', 'b', 'l', 'e', 'G', 'P', 'R', 0, |
| /* 22314 */ 'L', 'o', 'a', 'd', 'I', 'm', 'm', 'S', 'i', 'n', 'g', 'l', 'e', 'G', 'P', 'R', 0, |
| /* 22331 */ 'M', 'F', 'T', 'R', 0, |
| /* 22336 */ 'D', 'R', 'O', 'T', 'R', 0, |
| /* 22342 */ 'G', '_', 'I', 'N', 'T', 'T', 'O', 'P', 'T', 'R', 0, |
| /* 22353 */ 'M', 'T', 'T', 'R', 0, |
| /* 22358 */ 'T', 'L', 'B', 'W', 'R', 0, |
| /* 22364 */ 'T', 'L', 'B', 'G', 'W', 'R', 0, |
| /* 22371 */ 'R', 'D', 'H', 'W', 'R', 0, |
| /* 22377 */ 'L', 'W', 'R', 0, |
| /* 22381 */ 'S', 'W', 'R', 0, |
| /* 22385 */ 'G', '_', 'F', 'A', 'B', 'S', 0, |
| /* 22392 */ 'G', '_', 'U', 'N', 'M', 'E', 'R', 'G', 'E', '_', 'V', 'A', 'L', 'U', 'E', 'S', 0, |
| /* 22409 */ 'G', '_', 'M', 'E', 'R', 'G', 'E', '_', 'V', 'A', 'L', 'U', 'E', 'S', 0, |
| /* 22424 */ 'C', 'I', 'N', 'S', 0, |
| /* 22429 */ 'D', 'I', 'N', 'S', 0, |
| /* 22434 */ 'G', '_', 'F', 'C', 'O', 'S', 0, |
| /* 22441 */ 'G', '_', 'C', 'O', 'N', 'C', 'A', 'T', '_', 'V', 'E', 'C', 'T', 'O', 'R', 'S', 0, |
| /* 22458 */ 'C', 'O', 'P', 'Y', '_', 'T', 'O', '_', 'R', 'E', 'G', 'C', 'L', 'A', 'S', 'S', 0, |
| /* 22475 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', '_', 'C', 'M', 'P', 'X', 'C', 'H', 'G', '_', 'W', 'I', 'T', 'H', '_', 'S', 'U', 'C', 'C', 'E', 'S', 'S', 0, |
| /* 22505 */ 'G', '_', 'I', 'N', 'T', 'R', 'I', 'N', 'S', 'I', 'C', '_', 'W', '_', 'S', 'I', 'D', 'E', '_', 'E', 'F', 'F', 'E', 'C', 'T', 'S', 0, |
| /* 22532 */ 'E', 'X', 'T', 'S', 0, |
| /* 22537 */ 'C', 'V', 'T', '_', 'D', '3', '2', '_', 'S', 0, |
| /* 22547 */ 'C', 'V', 'T', '_', 'D', '6', '4', '_', 'S', 0, |
| /* 22557 */ 'M', 'O', 'V', 'N', '_', 'I', '6', '4', '_', 'S', 0, |
| /* 22568 */ 'M', 'O', 'V', 'Z', '_', 'I', '6', '4', '_', 'S', 0, |
| /* 22579 */ 'M', 'I', 'N', 'A', '_', 'S', 0, |
| /* 22586 */ 'M', 'A', 'X', 'A', '_', 'S', 0, |
| /* 22593 */ 'F', 'S', 'U', 'B', '_', 'S', 0, |
| /* 22600 */ 'N', 'M', 'S', 'U', 'B', '_', 'S', 0, |
| /* 22608 */ 'F', 'A', 'D', 'D', '_', 'S', 0, |
| /* 22615 */ 'N', 'M', 'A', 'D', 'D', '_', 'S', 0, |
| /* 22623 */ 'C', '_', 'N', 'G', 'E', '_', 'S', 0, |
| /* 22631 */ 'C', '_', 'N', 'G', 'L', 'E', '_', 'S', 0, |
| /* 22640 */ 'C', '_', 'O', 'L', 'E', '_', 'S', 0, |
| /* 22648 */ 'C', 'M', 'P', '_', 'S', 'L', 'E', '_', 'S', 0, |
| /* 22658 */ 'C', 'M', 'P', '_', 'S', 'U', 'L', 'E', '_', 'S', 0, |
| /* 22669 */ 'C', '_', 'U', 'L', 'E', '_', 'S', 0, |
| /* 22677 */ 'C', 'M', 'P', '_', 'U', 'L', 'E', '_', 'S', 0, |
| /* 22687 */ 'C', '_', 'L', 'E', '_', 'S', 0, |
| /* 22694 */ 'C', 'M', 'P', '_', 'L', 'E', '_', 'S', 0, |
| /* 22703 */ 'C', 'M', 'P', '_', 'S', 'A', 'F', '_', 'S', 0, |
| /* 22713 */ 'M', 'S', 'U', 'B', 'F', '_', 'S', 0, |
| /* 22721 */ 'M', 'A', 'D', 'D', 'F', '_', 'S', 0, |
| /* 22729 */ 'C', '_', 'S', 'F', '_', 'S', 0, |
| /* 22736 */ 'M', 'O', 'V', 'F', '_', 'S', 0, |
| /* 22743 */ 'C', '_', 'F', '_', 'S', 0, |
| /* 22749 */ 'P', 's', 'e', 'u', 'd', 'o', 'S', 'E', 'L', 'E', 'C', 'T', 'F', 'P', '_', 'F', '_', 'S', 0, |
| /* 22768 */ 'C', 'M', 'P', '_', 'F', '_', 'S', 0, |
| /* 22776 */ 'F', 'N', 'E', 'G', '_', 'S', 0, |
| /* 22783 */ 'M', 'O', 'V', 'N', '_', 'I', '_', 'S', 0, |
| /* 22792 */ 'M', 'O', 'V', 'Z', '_', 'I', '_', 'S', 0, |
| /* 22801 */ 'S', 'E', 'L', '_', 'S', 0, |
| /* 22807 */ 'C', '_', 'N', 'G', 'L', '_', 'S', 0, |
| /* 22815 */ 'F', 'M', 'U', 'L', '_', 'S', 0, |
| /* 22822 */ 'T', 'R', 'U', 'N', 'C', '_', 'L', '_', 'S', 0, |
| /* 22832 */ 'R', 'O', 'U', 'N', 'D', '_', 'L', '_', 'S', 0, |
| /* 22842 */ 'C', 'E', 'I', 'L', '_', 'L', '_', 'S', 0, |
| /* 22851 */ 'F', 'L', 'O', 'O', 'R', '_', 'L', '_', 'S', 0, |
| /* 22861 */ 'C', 'V', 'T', '_', 'L', '_', 'S', 0, |
| /* 22869 */ 'M', 'I', 'N', '_', 'S', 0, |
| /* 22875 */ 'C', 'M', 'P', '_', 'S', 'U', 'N', '_', 'S', 0, |
| /* 22885 */ 'C', '_', 'U', 'N', '_', 'S', 0, |
| /* 22892 */ 'C', 'M', 'P', '_', 'U', 'N', '_', 'S', 0, |
| /* 22901 */ 'R', 'E', 'C', 'I', 'P', '_', 'S', 0, |
| /* 22909 */ 'C', '_', 'S', 'E', 'Q', '_', 'S', 0, |
| /* 22917 */ 'C', 'M', 'P', '_', 'S', 'E', 'Q', '_', 'S', 0, |
| /* 22927 */ 'C', 'M', 'P', '_', 'S', 'U', 'E', 'Q', '_', 'S', 0, |
| /* 22938 */ 'C', '_', 'U', 'E', 'Q', '_', 'S', 0, |
| /* 22946 */ 'C', 'M', 'P', '_', 'U', 'E', 'Q', '_', 'S', 0, |
| /* 22956 */ 'C', '_', 'E', 'Q', '_', 'S', 0, |
| /* 22963 */ 'C', 'M', 'P', '_', 'E', 'Q', '_', 'S', 0, |
| /* 22972 */ 'F', 'A', 'B', 'S', '_', 'S', 0, |
| /* 22979 */ 'C', 'L', 'A', 'S', 'S', '_', 'S', 0, |
| /* 22987 */ 'P', 's', 'e', 'u', 'd', 'o', 'S', 'E', 'L', 'E', 'C', 'T', '_', 'S', 0, |
| /* 23002 */ 'C', '_', 'N', 'G', 'T', '_', 'S', 0, |
| /* 23010 */ 'C', '_', 'O', 'L', 'T', '_', 'S', 0, |
| /* 23018 */ 'C', 'M', 'P', '_', 'S', 'L', 'T', '_', 'S', 0, |
| /* 23028 */ 'C', 'M', 'P', '_', 'S', 'U', 'L', 'T', '_', 'S', 0, |
| /* 23039 */ 'C', '_', 'U', 'L', 'T', '_', 'S', 0, |
| /* 23047 */ 'C', 'M', 'P', '_', 'U', 'L', 'T', '_', 'S', 0, |
| /* 23057 */ 'C', '_', 'L', 'T', '_', 'S', 0, |
| /* 23064 */ 'C', 'M', 'P', '_', 'L', 'T', '_', 'S', 0, |
| /* 23073 */ 'R', 'I', 'N', 'T', '_', 'S', 0, |
| /* 23080 */ 'F', 'S', 'Q', 'R', 'T', '_', 'S', 0, |
| /* 23088 */ 'R', 'S', 'Q', 'R', 'T', '_', 'S', 0, |
| /* 23096 */ 'M', 'O', 'V', 'T', '_', 'S', 0, |
| /* 23103 */ 'P', 's', 'e', 'u', 'd', 'o', 'S', 'E', 'L', 'E', 'C', 'T', 'F', 'P', '_', 'T', '_', 'S', 0, |
| /* 23122 */ 'F', 'D', 'I', 'V', '_', 'S', 0, |
| /* 23129 */ 'F', 'M', 'O', 'V', '_', 'S', 0, |
| /* 23136 */ 'P', 's', 'e', 'u', 'd', 'o', 'T', 'R', 'U', 'N', 'C', '_', 'W', '_', 'S', 0, |
| /* 23152 */ 'R', 'O', 'U', 'N', 'D', '_', 'W', '_', 'S', 0, |
| /* 23162 */ 'C', 'E', 'I', 'L', '_', 'W', '_', 'S', 0, |
| /* 23171 */ 'F', 'L', 'O', 'O', 'R', '_', 'W', '_', 'S', 0, |
| /* 23181 */ 'C', 'V', 'T', '_', 'W', '_', 'S', 0, |
| /* 23189 */ 'M', 'A', 'X', '_', 'S', 0, |
| /* 23195 */ 'S', 'E', 'L', 'N', 'E', 'Z', '_', 'S', 0, |
| /* 23204 */ 'S', 'E', 'L', 'E', 'Q', 'Z', '_', 'S', 0, |
| /* 23213 */ 'B', 'C', '1', 'T', 0, |
| /* 23218 */ 'G', '_', 'E', 'X', 'T', 'R', 'A', 'C', 'T', 0, |
| /* 23228 */ 'G', '_', 'S', 'E', 'L', 'E', 'C', 'T', 0, |
| /* 23237 */ 'G', '_', 'B', 'R', 'I', 'N', 'D', 'I', 'R', 'E', 'C', 'T', 0, |
| /* 23250 */ 'D', 'E', 'R', 'E', 'T', 0, |
| /* 23256 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'R', 'E', 'T', 0, |
| /* 23270 */ 'B', 'G', 'T', 0, |
| /* 23274 */ 'W', 'A', 'I', 'T', 0, |
| /* 23279 */ 'P', 'A', 'T', 'C', 'H', 'A', 'B', 'L', 'E', '_', 'F', 'U', 'N', 'C', 'T', 'I', 'O', 'N', '_', 'E', 'X', 'I', 'T', 0, |
| /* 23303 */ 'G', '_', 'B', 'R', 'J', 'T', 0, |
| /* 23310 */ 'B', 'L', 'T', 0, |
| /* 23314 */ 'G', '_', 'E', 'X', 'T', 'R', 'A', 'C', 'T', '_', 'V', 'E', 'C', 'T', 'O', 'R', '_', 'E', 'L', 'T', 0, |
| /* 23335 */ 'G', '_', 'I', 'N', 'S', 'E', 'R', 'T', '_', 'V', 'E', 'C', 'T', 'O', 'R', '_', 'E', 'L', 'T', 0, |
| /* 23355 */ 'S', 'L', 'T', 0, |
| /* 23359 */ 'T', 'L', 'T', 0, |
| /* 23363 */ 'P', 's', 'e', 'u', 'd', 'o', 'D', 'M', 'U', 'L', 'T', 0, |
| /* 23375 */ 'P', 's', 'e', 'u', 'd', 'o', 'M', 'U', 'L', 'T', 0, |
| /* 23386 */ 'D', 'M', 'T', 0, |
| /* 23390 */ 'E', 'M', 'T', 0, |
| /* 23394 */ 'G', '_', 'F', 'C', 'O', 'N', 'S', 'T', 'A', 'N', 'T', 0, |
| /* 23406 */ 'G', '_', 'C', 'O', 'N', 'S', 'T', 'A', 'N', 'T', 0, |
| /* 23417 */ 'S', 'T', 'A', 'T', 'E', 'P', 'O', 'I', 'N', 'T', 0, |
| /* 23428 */ 'P', 'A', 'T', 'C', 'H', 'P', 'O', 'I', 'N', 'T', 0, |
| /* 23439 */ 'G', '_', 'P', 'T', 'R', 'T', 'O', 'I', 'N', 'T', 0, |
| /* 23450 */ 'G', '_', 'F', 'R', 'I', 'N', 'T', 0, |
| /* 23458 */ 'G', '_', 'F', 'N', 'E', 'A', 'R', 'B', 'Y', 'I', 'N', 'T', 0, |
| /* 23471 */ 'G', '_', 'V', 'A', 'S', 'T', 'A', 'R', 'T', 0, |
| /* 23481 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0, |
| /* 23496 */ 'G', '_', 'I', 'N', 'S', 'E', 'R', 'T', 0, |
| /* 23505 */ 'G', '_', 'F', 'S', 'Q', 'R', 'T', 0, |
| /* 23513 */ 'G', '_', 'B', 'I', 'T', 'C', 'A', 'S', 'T', 0, |
| /* 23523 */ 'G', '_', 'A', 'D', 'D', 'R', 'S', 'P', 'A', 'C', 'E', '_', 'C', 'A', 'S', 'T', 0, |
| /* 23540 */ 'G', 'I', 'N', 'V', 'T', 0, |
| /* 23546 */ 'D', 'E', 'X', 'T', 0, |
| /* 23551 */ 'G', '_', 'F', 'P', 'E', 'X', 'T', 0, |
| /* 23559 */ 'G', '_', 'S', 'E', 'X', 'T', 0, |
| /* 23566 */ 'G', '_', 'A', 'N', 'Y', 'E', 'X', 'T', 0, |
| /* 23575 */ 'G', '_', 'Z', 'E', 'X', 'T', 0, |
| /* 23582 */ 'P', 's', 'e', 'u', 'd', 'o', 'M', 'S', 'U', 'B', 'U', 0, |
| /* 23594 */ 'P', 's', 'e', 'u', 'd', 'o', 'M', 'A', 'D', 'D', 'U', 0, |
| /* 23606 */ 'D', 'M', 'O', 'D', 'U', 0, |
| /* 23612 */ 'B', 'G', 'E', 'U', 0, |
| /* 23617 */ 'S', 'G', 'E', 'U', 0, |
| /* 23622 */ 'T', 'G', 'E', 'U', 0, |
| /* 23627 */ 'B', 'L', 'E', 'U', 0, |
| /* 23632 */ 'D', 'M', 'U', 'H', 'U', 0, |
| /* 23638 */ 'T', 'G', 'E', 'I', 'U', 0, |
| /* 23644 */ 'T', 'T', 'L', 'T', 'I', 'U', 0, |
| /* 23651 */ 'V', '3', 'M', 'U', 'L', 'U', 0, |
| /* 23658 */ 'D', 'M', 'U', 'L', 'U', 0, |
| /* 23664 */ 'V', 'M', 'U', 'L', 'U', 0, |
| /* 23670 */ 'D', 'I', 'N', 'S', 'U', 0, |
| /* 23676 */ 'B', 'G', 'T', 'U', 0, |
| /* 23681 */ 'B', 'L', 'T', 'U', 0, |
| /* 23686 */ 'T', 'L', 'T', 'U', 0, |
| /* 23691 */ 'D', 'E', 'X', 'T', 'U', 0, |
| /* 23697 */ 'D', 'D', 'I', 'V', 'U', 0, |
| /* 23703 */ 'D', 'S', 'R', 'A', 'V', 0, |
| /* 23709 */ 'B', 'I', 'T', 'R', 'E', 'V', 0, |
| /* 23716 */ 'D', 'D', 'I', 'V', 0, |
| /* 23721 */ 'G', '_', 'F', 'D', 'I', 'V', 0, |
| /* 23728 */ 'P', 's', 'e', 'u', 'd', 'o', 'D', 'S', 'D', 'I', 'V', 0, |
| /* 23740 */ 'G', '_', 'S', 'D', 'I', 'V', 0, |
| /* 23747 */ 'P', 's', 'e', 'u', 'd', 'o', 'S', 'D', 'I', 'V', 0, |
| /* 23758 */ 'P', 's', 'e', 'u', 'd', 'o', 'D', 'U', 'D', 'I', 'V', 0, |
| /* 23770 */ 'G', '_', 'U', 'D', 'I', 'V', 0, |
| /* 23777 */ 'P', 's', 'e', 'u', 'd', 'o', 'U', 'D', 'I', 'V', 0, |
| /* 23788 */ 'D', 'S', 'L', 'L', 'V', 0, |
| /* 23794 */ 'D', 'S', 'R', 'L', 'V', 0, |
| /* 23800 */ 'T', 'L', 'B', 'I', 'N', 'V', 0, |
| /* 23807 */ 'T', 'L', 'B', 'G', 'I', 'N', 'V', 0, |
| /* 23815 */ 'S', 'H', 'I', 'L', 'O', 'V', 0, |
| /* 23822 */ 'E', 'X', 'T', 'P', 'D', 'P', 'V', 0, |
| /* 23830 */ 'E', 'X', 'T', 'P', 'V', 0, |
| /* 23836 */ 'D', 'R', 'O', 'T', 'R', 'V', 0, |
| /* 23843 */ 'I', 'N', 'S', 'V', 0, |
| /* 23848 */ 'A', 'N', 'D', '_', 'V', 0, |
| /* 23854 */ 'M', 'O', 'V', 'E', '_', 'V', 0, |
| /* 23861 */ 'B', 'S', 'E', 'L', '_', 'V', 0, |
| /* 23868 */ 'N', 'O', 'R', '_', 'V', 0, |
| /* 23874 */ 'X', 'O', 'R', '_', 'V', 0, |
| /* 23880 */ 'B', 'Z', '_', 'V', 0, |
| /* 23885 */ 'B', 'M', 'Z', '_', 'V', 0, |
| /* 23891 */ 'B', 'N', 'Z', '_', 'V', 0, |
| /* 23897 */ 'B', 'M', 'N', 'Z', '_', 'V', 0, |
| /* 23904 */ 'C', 'R', 'C', '3', '2', 'W', 0, |
| /* 23911 */ 'C', 'R', 'C', '3', '2', 'C', 'W', 0, |
| /* 23919 */ 'L', 'W', 0, |
| /* 23922 */ 'G', '_', 'F', 'P', 'O', 'W', 0, |
| /* 23929 */ 'S', 'W', 0, |
| /* 23932 */ 'P', 's', 'e', 'u', 'd', 'o', 'C', 'V', 'T', '_', 'D', '3', '2', '_', 'W', 0, |
| /* 23948 */ 'F', 'L', 'O', 'G', '2', '_', 'W', 0, |
| /* 23956 */ 'F', 'E', 'X', 'P', '2', '_', 'W', 0, |
| /* 23964 */ 'P', 's', 'e', 'u', 'd', 'o', 'C', 'V', 'T', '_', 'D', '6', '4', '_', 'W', 0, |
| /* 23980 */ 'S', 'R', 'A', '_', 'W', 0, |
| /* 23986 */ 'A', 'D', 'D', '_', 'A', '_', 'W', 0, |
| /* 23994 */ 'F', 'M', 'I', 'N', '_', 'A', '_', 'W', 0, |
| /* 24003 */ 'A', 'D', 'D', 'S', '_', 'A', '_', 'W', 0, |
| /* 24012 */ 'F', 'M', 'A', 'X', '_', 'A', '_', 'W', 0, |
| /* 24021 */ 'F', 'S', 'U', 'B', '_', 'W', 0, |
| /* 24028 */ 'F', 'M', 'S', 'U', 'B', '_', 'W', 0, |
| /* 24036 */ 'N', 'L', 'O', 'C', '_', 'W', 0, |
| /* 24043 */ 'N', 'L', 'Z', 'C', '_', 'W', 0, |
| /* 24050 */ 'F', 'A', 'D', 'D', '_', 'W', 0, |
| /* 24057 */ 'F', 'M', 'A', 'D', 'D', '_', 'W', 0, |
| /* 24065 */ 'S', 'L', 'D', '_', 'W', 0, |
| /* 24071 */ 'P', 'C', 'K', 'O', 'D', '_', 'W', 0, |
| /* 24079 */ 'I', 'L', 'V', 'O', 'D', '_', 'W', 0, |
| /* 24087 */ 'F', 'C', 'L', 'E', '_', 'W', 0, |
| /* 24094 */ 'F', 'S', 'L', 'E', '_', 'W', 0, |
| /* 24101 */ 'F', 'C', 'U', 'L', 'E', '_', 'W', 0, |
| /* 24109 */ 'F', 'S', 'U', 'L', 'E', '_', 'W', 0, |
| /* 24117 */ 'F', 'C', 'N', 'E', '_', 'W', 0, |
| /* 24124 */ 'F', 'S', 'N', 'E', '_', 'W', 0, |
| /* 24131 */ 'F', 'C', 'U', 'N', 'E', '_', 'W', 0, |
| /* 24139 */ 'F', 'S', 'U', 'N', 'E', '_', 'W', 0, |
| /* 24147 */ 'I', 'N', 'S', 'V', 'E', '_', 'W', 0, |
| /* 24155 */ 'F', 'C', 'A', 'F', '_', 'W', 0, |
| /* 24162 */ 'F', 'S', 'A', 'F', '_', 'W', 0, |
| /* 24169 */ 'V', 'S', 'H', 'F', '_', 'W', 0, |
| /* 24176 */ 'B', 'N', 'E', 'G', '_', 'W', 0, |
| /* 24183 */ 'P', 'R', 'E', 'C', 'R', '_', 'S', 'R', 'A', '_', 'P', 'H', '_', 'W', 0, |
| /* 24198 */ 'P', 'R', 'E', 'C', 'R', 'Q', '_', 'P', 'H', '_', 'W', 0, |
| /* 24210 */ 'P', 'R', 'E', 'C', 'R', '_', 'S', 'R', 'A', '_', 'R', '_', 'P', 'H', '_', 'W', 0, |
| /* 24227 */ 'P', 'R', 'E', 'C', 'R', 'Q', '_', 'R', 'S', '_', 'P', 'H', '_', 'W', 0, |
| /* 24242 */ 'S', 'U', 'B', 'Q', 'H', '_', 'W', 0, |
| /* 24250 */ 'A', 'D', 'D', 'Q', 'H', '_', 'W', 0, |
| /* 24258 */ 'S', 'R', 'A', 'I', '_', 'W', 0, |
| /* 24265 */ 'S', 'L', 'D', 'I', '_', 'W', 0, |
| /* 24272 */ 'B', 'N', 'E', 'G', 'I', '_', 'W', 0, |
| /* 24280 */ 'S', 'L', 'L', 'I', '_', 'W', 0, |
| /* 24287 */ 'S', 'R', 'L', 'I', '_', 'W', 0, |
| /* 24294 */ 'B', 'I', 'N', 'S', 'L', 'I', '_', 'W', 0, |
| /* 24303 */ 'C', 'E', 'Q', 'I', '_', 'W', 0, |
| /* 24310 */ 'S', 'R', 'A', 'R', 'I', '_', 'W', 0, |
| /* 24318 */ 'B', 'C', 'L', 'R', 'I', '_', 'W', 0, |
| /* 24326 */ 'S', 'R', 'L', 'R', 'I', '_', 'W', 0, |
| /* 24334 */ 'B', 'I', 'N', 'S', 'R', 'I', '_', 'W', 0, |
| /* 24343 */ 'S', 'P', 'L', 'A', 'T', 'I', '_', 'W', 0, |
| /* 24352 */ 'B', 'S', 'E', 'T', 'I', '_', 'W', 0, |
| /* 24360 */ 'S', 'U', 'B', 'V', 'I', '_', 'W', 0, |
| /* 24368 */ 'A', 'D', 'D', 'V', 'I', '_', 'W', 0, |
| /* 24376 */ 'F', 'I', 'L', 'L', '_', 'W', 0, |
| /* 24383 */ 'S', 'L', 'L', '_', 'W', 0, |
| /* 24389 */ 'F', 'E', 'X', 'U', 'P', 'L', '_', 'W', 0, |
| /* 24398 */ 'F', 'F', 'Q', 'L', '_', 'W', 0, |
| /* 24405 */ 'S', 'R', 'L', '_', 'W', 0, |
| /* 24411 */ 'B', 'I', 'N', 'S', 'L', '_', 'W', 0, |
| /* 24419 */ 'F', 'M', 'U', 'L', '_', 'W', 0, |
| /* 24426 */ 'I', 'L', 'V', 'L', '_', 'W', 0, |
| /* 24433 */ 'D', 'P', 'A', 'Q', '_', 'S', 'A', '_', 'L', '_', 'W', 0, |
| /* 24445 */ 'D', 'P', 'S', 'Q', '_', 'S', 'A', '_', 'L', '_', 'W', 0, |
| /* 24457 */ 'F', 'M', 'I', 'N', '_', 'W', 0, |
| /* 24464 */ 'F', 'C', 'U', 'N', '_', 'W', 0, |
| /* 24471 */ 'F', 'S', 'U', 'N', '_', 'W', 0, |
| /* 24478 */ 'F', 'E', 'X', 'D', 'O', '_', 'W', 0, |
| /* 24486 */ 'F', 'R', 'C', 'P', '_', 'W', 0, |
| /* 24493 */ 'F', 'C', 'E', 'Q', '_', 'W', 0, |
| /* 24500 */ 'F', 'S', 'E', 'Q', '_', 'W', 0, |
| /* 24507 */ 'F', 'C', 'U', 'E', 'Q', '_', 'W', 0, |
| /* 24515 */ 'F', 'S', 'U', 'E', 'Q', '_', 'W', 0, |
| /* 24523 */ 'F', 'T', 'Q', '_', 'W', 0, |
| /* 24529 */ 'M', 'S', 'U', 'B', '_', 'Q', '_', 'W', 0, |
| /* 24538 */ 'M', 'A', 'D', 'D', '_', 'Q', '_', 'W', 0, |
| /* 24547 */ 'M', 'U', 'L', '_', 'Q', '_', 'W', 0, |
| /* 24555 */ 'M', 'S', 'U', 'B', 'R', '_', 'Q', '_', 'W', 0, |
| /* 24565 */ 'M', 'A', 'D', 'D', 'R', '_', 'Q', '_', 'W', 0, |
| /* 24575 */ 'M', 'U', 'L', 'R', '_', 'Q', '_', 'W', 0, |
| /* 24584 */ 'S', 'R', 'A', 'R', '_', 'W', 0, |
| /* 24591 */ 'B', 'C', 'L', 'R', '_', 'W', 0, |
| /* 24598 */ 'S', 'R', 'L', 'R', '_', 'W', 0, |
| /* 24605 */ 'F', 'C', 'O', 'R', '_', 'W', 0, |
| /* 24612 */ 'F', 'S', 'O', 'R', '_', 'W', 0, |
| /* 24619 */ 'F', 'E', 'X', 'U', 'P', 'R', '_', 'W', 0, |
| /* 24628 */ 'F', 'F', 'Q', 'R', '_', 'W', 0, |
| /* 24635 */ 'B', 'I', 'N', 'S', 'R', '_', 'W', 0, |
| /* 24643 */ 'E', 'X', 'T', 'R', '_', 'W', 0, |
| /* 24650 */ 'I', 'L', 'V', 'R', '_', 'W', 0, |
| /* 24657 */ 'S', 'H', 'R', 'A', '_', 'R', '_', 'W', 0, |
| /* 24666 */ 'S', 'U', 'B', 'Q', 'H', '_', 'R', '_', 'W', 0, |
| /* 24676 */ 'A', 'D', 'D', 'Q', 'H', '_', 'R', '_', 'W', 0, |
| /* 24686 */ 'E', 'X', 'T', 'R', '_', 'R', '_', 'W', 0, |
| /* 24695 */ 'S', 'H', 'R', 'A', 'V', '_', 'R', '_', 'W', 0, |
| /* 24705 */ 'E', 'X', 'T', 'R', 'V', '_', 'R', '_', 'W', 0, |
| /* 24715 */ 'F', 'A', 'B', 'S', '_', 'W', 0, |
| /* 24722 */ 'M', 'U', 'L', 'Q', '_', 'R', 'S', '_', 'W', 0, |
| /* 24732 */ 'E', 'X', 'T', 'R', '_', 'R', 'S', '_', 'W', 0, |
| /* 24742 */ 'E', 'X', 'T', 'R', 'V', '_', 'R', 'S', '_', 'W', 0, |
| /* 24753 */ 'F', 'C', 'L', 'A', 'S', 'S', '_', 'W', 0, |
| /* 24762 */ 'A', 'S', 'U', 'B', '_', 'S', '_', 'W', 0, |
| /* 24771 */ 'H', 'S', 'U', 'B', '_', 'S', '_', 'W', 0, |
| /* 24780 */ 'D', 'P', 'S', 'U', 'B', '_', 'S', '_', 'W', 0, |
| /* 24790 */ 'F', 'T', 'R', 'U', 'N', 'C', '_', 'S', '_', 'W', 0, |
| /* 24801 */ 'H', 'A', 'D', 'D', '_', 'S', '_', 'W', 0, |
| /* 24810 */ 'D', 'P', 'A', 'D', 'D', '_', 'S', '_', 'W', 0, |
| /* 24820 */ 'M', 'O', 'D', '_', 'S', '_', 'W', 0, |
| /* 24828 */ 'C', 'L', 'E', '_', 'S', '_', 'W', 0, |
| /* 24836 */ 'A', 'V', 'E', '_', 'S', '_', 'W', 0, |
| /* 24844 */ 'C', 'L', 'E', 'I', '_', 'S', '_', 'W', 0, |
| /* 24853 */ 'M', 'I', 'N', 'I', '_', 'S', '_', 'W', 0, |
| /* 24862 */ 'C', 'L', 'T', 'I', '_', 'S', '_', 'W', 0, |
| /* 24871 */ 'M', 'A', 'X', 'I', '_', 'S', '_', 'W', 0, |
| /* 24880 */ 'S', 'H', 'L', 'L', '_', 'S', '_', 'W', 0, |
| /* 24889 */ 'M', 'I', 'N', '_', 'S', '_', 'W', 0, |
| /* 24897 */ 'D', 'O', 'T', 'P', '_', 'S', '_', 'W', 0, |
| /* 24906 */ 'S', 'U', 'B', 'Q', '_', 'S', '_', 'W', 0, |
| /* 24915 */ 'A', 'D', 'D', 'Q', '_', 'S', '_', 'W', 0, |
| /* 24924 */ 'M', 'U', 'L', 'Q', '_', 'S', '_', 'W', 0, |
| /* 24933 */ 'A', 'B', 'S', 'Q', '_', 'S', '_', 'W', 0, |
| /* 24942 */ 'A', 'V', 'E', 'R', '_', 'S', '_', 'W', 0, |
| /* 24951 */ 'S', 'U', 'B', 'S', '_', 'S', '_', 'W', 0, |
| /* 24960 */ 'A', 'D', 'D', 'S', '_', 'S', '_', 'W', 0, |
| /* 24969 */ 'S', 'A', 'T', '_', 'S', '_', 'W', 0, |
| /* 24977 */ 'C', 'L', 'T', '_', 'S', '_', 'W', 0, |
| /* 24985 */ 'F', 'F', 'I', 'N', 'T', '_', 'S', '_', 'W', 0, |
| /* 24995 */ 'F', 'T', 'I', 'N', 'T', '_', 'S', '_', 'W', 0, |
| /* 25005 */ 'P', 's', 'e', 'u', 'd', 'o', 'C', 'V', 'T', '_', 'S', '_', 'W', 0, |
| /* 25019 */ 'S', 'U', 'B', 'S', 'U', 'U', '_', 'S', '_', 'W', 0, |
| /* 25030 */ 'D', 'I', 'V', '_', 'S', '_', 'W', 0, |
| /* 25038 */ 'S', 'H', 'L', 'L', 'V', '_', 'S', '_', 'W', 0, |
| /* 25048 */ 'M', 'A', 'X', '_', 'S', '_', 'W', 0, |
| /* 25056 */ 'C', 'O', 'P', 'Y', '_', 'S', '_', 'W', 0, |
| /* 25065 */ 'S', 'P', 'L', 'A', 'T', '_', 'W', 0, |
| /* 25073 */ 'B', 'S', 'E', 'T', '_', 'W', 0, |
| /* 25080 */ 'F', 'C', 'L', 'T', '_', 'W', 0, |
| /* 25087 */ 'F', 'S', 'L', 'T', '_', 'W', 0, |
| /* 25094 */ 'F', 'C', 'U', 'L', 'T', '_', 'W', 0, |
| /* 25102 */ 'F', 'S', 'U', 'L', 'T', '_', 'W', 0, |
| /* 25110 */ 'P', 'C', 'N', 'T', '_', 'W', 0, |
| /* 25117 */ 'F', 'R', 'I', 'N', 'T', '_', 'W', 0, |
| /* 25125 */ 'I', 'N', 'S', 'E', 'R', 'T', '_', 'W', 0, |
| /* 25134 */ 'F', 'S', 'Q', 'R', 'T', '_', 'W', 0, |
| /* 25142 */ 'F', 'R', 'S', 'Q', 'R', 'T', '_', 'W', 0, |
| /* 25151 */ 'S', 'T', '_', 'W', 0, |
| /* 25156 */ 'A', 'S', 'U', 'B', '_', 'U', '_', 'W', 0, |
| /* 25165 */ 'H', 'S', 'U', 'B', '_', 'U', '_', 'W', 0, |
| /* 25174 */ 'D', 'P', 'S', 'U', 'B', '_', 'U', '_', 'W', 0, |
| /* 25184 */ 'F', 'T', 'R', 'U', 'N', 'C', '_', 'U', '_', 'W', 0, |
| /* 25195 */ 'H', 'A', 'D', 'D', '_', 'U', '_', 'W', 0, |
| /* 25204 */ 'D', 'P', 'A', 'D', 'D', '_', 'U', '_', 'W', 0, |
| /* 25214 */ 'M', 'O', 'D', '_', 'U', '_', 'W', 0, |
| /* 25222 */ 'C', 'L', 'E', '_', 'U', '_', 'W', 0, |
| /* 25230 */ 'A', 'V', 'E', '_', 'U', '_', 'W', 0, |
| /* 25238 */ 'C', 'L', 'E', 'I', '_', 'U', '_', 'W', 0, |
| /* 25247 */ 'M', 'I', 'N', 'I', '_', 'U', '_', 'W', 0, |
| /* 25256 */ 'C', 'L', 'T', 'I', '_', 'U', '_', 'W', 0, |
| /* 25265 */ 'M', 'A', 'X', 'I', '_', 'U', '_', 'W', 0, |
| /* 25274 */ 'M', 'I', 'N', '_', 'U', '_', 'W', 0, |
| /* 25282 */ 'D', 'O', 'T', 'P', '_', 'U', '_', 'W', 0, |
| /* 25291 */ 'A', 'V', 'E', 'R', '_', 'U', '_', 'W', 0, |
| /* 25300 */ 'S', 'U', 'B', 'S', '_', 'U', '_', 'W', 0, |
| /* 25309 */ 'A', 'D', 'D', 'S', '_', 'U', '_', 'W', 0, |
| /* 25318 */ 'S', 'U', 'B', 'S', 'U', 'S', '_', 'U', '_', 'W', 0, |
| /* 25329 */ 'S', 'A', 'T', '_', 'U', '_', 'W', 0, |
| /* 25337 */ 'C', 'L', 'T', '_', 'U', '_', 'W', 0, |
| /* 25345 */ 'F', 'F', 'I', 'N', 'T', '_', 'U', '_', 'W', 0, |
| /* 25355 */ 'F', 'T', 'I', 'N', 'T', '_', 'U', '_', 'W', 0, |
| /* 25365 */ 'D', 'I', 'V', '_', 'U', '_', 'W', 0, |
| /* 25373 */ 'M', 'A', 'X', '_', 'U', '_', 'W', 0, |
| /* 25381 */ 'C', 'O', 'P', 'Y', '_', 'U', '_', 'W', 0, |
| /* 25390 */ 'M', 'S', 'U', 'B', 'V', '_', 'W', 0, |
| /* 25398 */ 'M', 'A', 'D', 'D', 'V', '_', 'W', 0, |
| /* 25406 */ 'P', 'C', 'K', 'E', 'V', '_', 'W', 0, |
| /* 25414 */ 'I', 'L', 'V', 'E', 'V', '_', 'W', 0, |
| /* 25422 */ 'F', 'D', 'I', 'V', '_', 'W', 0, |
| /* 25429 */ 'M', 'U', 'L', 'V', '_', 'W', 0, |
| /* 25436 */ 'E', 'X', 'T', 'R', 'V', '_', 'W', 0, |
| /* 25444 */ 'F', 'M', 'A', 'X', '_', 'W', 0, |
| /* 25451 */ 'B', 'Z', '_', 'W', 0, |
| /* 25456 */ 'B', 'N', 'Z', '_', 'W', 0, |
| /* 25462 */ 'G', '_', 'S', 'M', 'A', 'X', 0, |
| /* 25469 */ 'G', '_', 'U', 'M', 'A', 'X', 0, |
| /* 25476 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'U', 'M', 'A', 'X', 0, |
| /* 25493 */ 'G', '_', 'A', 'T', 'O', 'M', 'I', 'C', 'R', 'M', 'W', '_', 'M', 'A', 'X', 0, |
| /* 25509 */ 'M', 'F', 'T', 'A', 'C', 'X', 0, |
| /* 25516 */ 'M', 'T', 'T', 'A', 'C', 'X', 0, |
| /* 25523 */ 'G', '_', 'F', 'R', 'A', 'M', 'E', '_', 'I', 'N', 'D', 'E', 'X', 0, |
| /* 25537 */ 'L', 'H', 'X', 0, |
| /* 25541 */ 'J', 'A', 'L', 'X', 0, |
| /* 25546 */ 'L', 'B', 'U', 'X', 0, |
| /* 25551 */ 'L', 'W', 'X', 0, |
| /* 25555 */ 'C', 'O', 'P', 'Y', 0, |
| /* 25560 */ 'C', 'O', 'N', 'S', 'T', 'P', 'O', 'O', 'L', '_', 'E', 'N', 'T', 'R', 'Y', 0, |
| /* 25576 */ 'B', 'G', 'E', 'Z', 0, |
| /* 25581 */ 'B', 'L', 'E', 'Z', 0, |
| /* 25586 */ 'B', 'C', '1', 'N', 'E', 'Z', 0, |
| /* 25593 */ 'B', 'C', '2', 'N', 'E', 'Z', 0, |
| /* 25600 */ 'S', 'E', 'L', 'N', 'E', 'Z', 0, |
| /* 25607 */ 'D', 'C', 'L', 'Z', 0, |
| /* 25612 */ 'G', '_', 'C', 'T', 'L', 'Z', 0, |
| /* 25619 */ 'B', 'C', '1', 'E', 'Q', 'Z', 0, |
| /* 25626 */ 'B', 'C', '2', 'E', 'Q', 'Z', 0, |
| /* 25633 */ 'S', 'E', 'L', 'E', 'Q', 'Z', 0, |
| /* 25640 */ 'B', 'G', 'T', 'Z', 0, |
| /* 25645 */ 'B', 'L', 'T', 'Z', 0, |
| /* 25650 */ 'G', '_', 'C', 'T', 'T', 'Z', 0, |
| /* 25657 */ 'S', 'e', 'l', 'B', 'n', 'e', 'Z', 0, |
| /* 25665 */ 'S', 'e', 'l', 'B', 'e', 'q', 'Z', 0, |
| /* 25673 */ 'J', 'a', 'l', 'O', 'n', 'e', 'R', 'e', 'g', 0, |
| /* 25683 */ 'J', 'a', 'l', 'T', 'w', 'o', 'R', 'e', 'g', 0, |
| /* 25693 */ 'P', 's', 'e', 'u', 'd', 'o', 'I', 'n', 'd', 'i', 'r', 'e', 'c', 't', 'H', 'a', 'z', 'a', 'r', 'd', 'B', 'r', 'a', 'n', 'c', 'h', 0, |
| /* 25720 */ 'P', 's', 'e', 'u', 'd', 'o', 'I', 'n', 'd', 'i', 'r', 'e', 'c', 't', 'B', 'r', 'a', 'n', 'c', 'h', 0, |
| /* 25741 */ 'U', 'l', 'h', 0, |
| /* 25745 */ 'U', 's', 'h', 0, |
| /* 25749 */ 'D', 'A', 'D', 'D', 'i', 0, |
| /* 25755 */ 'A', 'N', 'D', 'i', 0, |
| /* 25760 */ 'S', 'N', 'E', 'i', 0, |
| /* 25765 */ 'S', 'E', 'Q', 'i', 0, |
| /* 25770 */ 'X', 'O', 'R', 'i', 0, |
| /* 25775 */ 'S', 'L', 'T', 'i', 0, |
| /* 25780 */ 'L', 'O', 'N', 'G', '_', 'B', 'R', 'A', 'N', 'C', 'H', '_', 'L', 'U', 'i', 0, |
| /* 25796 */ 'S', 'e', 'l', 'T', 'B', 't', 'n', 'e', 'Z', 'C', 'm', 'p', 'i', 0, |
| /* 25810 */ 'S', 'e', 'l', 'T', 'B', 't', 'e', 'q', 'Z', 'C', 'm', 'p', 'i', 0, |
| /* 25824 */ 'S', 'e', 'l', 'T', 'B', 't', 'n', 'e', 'Z', 'S', 'l', 't', 'i', 0, |
| /* 25838 */ 'S', 'e', 'l', 'T', 'B', 't', 'e', 'q', 'Z', 'S', 'l', 't', 'i', 0, |
| /* 25852 */ 'S', 'G', 'E', 'I', 'm', 'm', 0, |
| /* 25859 */ 'D', 'R', 'O', 'L', 'I', 'm', 'm', 0, |
| /* 25867 */ 'N', 'O', 'R', 'I', 'm', 'm', 0, |
| /* 25874 */ 'D', 'R', 'O', 'R', 'I', 'm', 'm', 0, |
| /* 25882 */ 'S', 'G', 'T', 'I', 'm', 'm', 0, |
| /* 25889 */ 'S', 'G', 'E', 'U', 'I', 'm', 'm', 0, |
| /* 25897 */ 'S', 'G', 'T', 'U', 'I', 'm', 'm', 0, |
| /* 25905 */ 'B', 'n', 'e', 'I', 'm', 'm', 0, |
| /* 25912 */ 'B', 'e', 'q', 'I', 'm', 'm', 0, |
| /* 25919 */ 'P', 's', 'e', 'u', 'd', 'o', 'R', 'e', 't', 'u', 'r', 'n', 0, |
| /* 25932 */ 'J', 'A', 'L', 'R', 'H', 'B', '6', '4', 'P', 's', 'e', 'u', 'd', 'o', 0, |
| /* 25947 */ 'J', 'A', 'L', 'R', '6', '4', 'P', 's', 'e', 'u', 'd', 'o', 0, |
| /* 25960 */ 'J', 'A', 'L', 'R', 'H', 'B', 'P', 's', 'e', 'u', 'd', 'o', 0, |
| /* 25973 */ 'J', 'A', 'L', 'R', 'P', 's', 'e', 'u', 'd', 'o', 0, |
| /* 25984 */ 'B', '_', 'M', 'M', 'R', '6', '_', 'P', 's', 'e', 'u', 'd', 'o', 0, |
| /* 25998 */ 'B', '_', 'M', 'M', '_', 'P', 's', 'e', 'u', 'd', 'o', 0, |
| /* 26010 */ 'S', 'D', 'I', 'V', '_', 'M', 'M', '_', 'P', 's', 'e', 'u', 'd', 'o', 0, |
| /* 26025 */ 'U', 'D', 'I', 'V', '_', 'M', 'M', '_', 'P', 's', 'e', 'u', 'd', 'o', 0, |
| /* 26040 */ 'L', 'D', 'M', 'a', 'c', 'r', 'o', 0, |
| /* 26048 */ 'S', 'D', 'M', 'a', 'c', 'r', 'o', 0, |
| /* 26056 */ 'S', 'E', 'Q', 'I', 'M', 'a', 'c', 'r', 'o', 0, |
| /* 26066 */ 'D', 'S', 'R', 'e', 'm', 'I', 'M', 'a', 'c', 'r', 'o', 0, |
| /* 26078 */ 'D', 'U', 'R', 'e', 'm', 'I', 'M', 'a', 'c', 'r', 'o', 0, |
| /* 26090 */ 'D', 'S', 'D', 'i', 'v', 'I', 'M', 'a', 'c', 'r', 'o', 0, |
| /* 26102 */ 'D', 'U', 'D', 'i', 'v', 'I', 'M', 'a', 'c', 'r', 'o', 0, |
| /* 26114 */ 'D', 'M', 'U', 'L', 'M', 'a', 'c', 'r', 'o', 0, |
| /* 26124 */ 'D', 'M', 'U', 'L', 'O', 'M', 'a', 'c', 'r', 'o', 0, |
| /* 26135 */ 'S', 'E', 'Q', 'M', 'a', 'c', 'r', 'o', 0, |
| /* 26144 */ 'A', 'B', 'S', 'M', 'a', 'c', 'r', 'o', 0, |
| /* 26153 */ 'D', 'M', 'U', 'L', 'O', 'U', 'M', 'a', 'c', 'r', 'o', 0, |
| /* 26165 */ 'D', 'S', 'R', 'e', 'm', 'M', 'a', 'c', 'r', 'o', 0, |
| /* 26176 */ 'D', 'U', 'R', 'e', 'm', 'M', 'a', 'c', 'r', 'o', 0, |
| /* 26187 */ 'B', 'G', 'E', 'I', 'm', 'm', 'M', 'a', 'c', 'r', 'o', 0, |
| /* 26199 */ 'B', 'L', 'E', 'I', 'm', 'm', 'M', 'a', 'c', 'r', 'o', 0, |
| /* 26211 */ 'B', 'G', 'E', 'L', 'I', 'm', 'm', 'M', 'a', 'c', 'r', 'o', 0, |
| /* 26224 */ 'B', 'L', 'E', 'L', 'I', 'm', 'm', 'M', 'a', 'c', 'r', 'o', 0, |
| /* 26237 */ 'B', 'N', 'E', 'L', 'I', 'm', 'm', 'M', 'a', 'c', 'r', 'o', 0, |
| /* 26250 */ 'B', 'E', 'Q', 'L', 'I', 'm', 'm', 'M', 'a', 'c', 'r', 'o', 0, |
| /* 26263 */ 'B', 'G', 'T', 'L', 'I', 'm', 'm', 'M', 'a', 'c', 'r', 'o', 0, |
| /* 26276 */ 'B', 'L', 'T', 'L', 'I', 'm', 'm', 'M', 'a', 'c', 'r', 'o', 0, |
| /* 26289 */ 'B', 'G', 'E', 'U', 'L', 'I', 'm', 'm', 'M', 'a', 'c', 'r', 'o', 0, |
| /* 26303 */ 'B', 'L', 'E', 'U', 'L', 'I', 'm', 'm', 'M', 'a', 'c', 'r', 'o', 0, |
| /* 26317 */ 'D', 'M', 'U', 'L', 'I', 'm', 'm', 'M', 'a', 'c', 'r', 'o', 0, |
| /* 26330 */ 'B', 'G', 'T', 'U', 'L', 'I', 'm', 'm', 'M', 'a', 'c', 'r', 'o', 0, |
| /* 26344 */ 'B', 'L', 'T', 'U', 'L', 'I', 'm', 'm', 'M', 'a', 'c', 'r', 'o', 0, |
| /* 26358 */ 'B', 'G', 'T', 'I', 'm', 'm', 'M', 'a', 'c', 'r', 'o', 0, |
| /* 26370 */ 'B', 'L', 'T', 'I', 'm', 'm', 'M', 'a', 'c', 'r', 'o', 0, |
| /* 26382 */ 'B', 'G', 'E', 'U', 'I', 'm', 'm', 'M', 'a', 'c', 'r', 'o', 0, |
| /* 26395 */ 'B', 'L', 'E', 'U', 'I', 'm', 'm', 'M', 'a', 'c', 'r', 'o', 0, |
| /* 26408 */ 'B', 'G', 'T', 'U', 'I', 'm', 'm', 'M', 'a', 'c', 'r', 'o', 0, |
| /* 26421 */ 'B', 'L', 'T', 'U', 'I', 'm', 'm', 'M', 'a', 'c', 'r', 'o', 0, |
| /* 26434 */ 'D', 'S', 'D', 'i', 'v', 'M', 'a', 'c', 'r', 'o', 0, |
| /* 26445 */ 'D', 'U', 'D', 'i', 'v', 'M', 'a', 'c', 'r', 'o', 0, |
| /* 26456 */ 'L', 'O', 'N', 'G', '_', 'B', 'R', 'A', 'N', 'C', 'H', '_', 'L', 'U', 'i', '2', 'O', 'p', 0, |
| /* 26475 */ 'L', 'O', 'N', 'G', '_', 'B', 'R', 'A', 'N', 'C', 'H', '_', 'D', 'A', 'D', 'D', 'i', 'u', '2', 'O', 'p', 0, |
| /* 26497 */ 'L', 'O', 'N', 'G', '_', 'B', 'R', 'A', 'N', 'C', 'H', '_', 'A', 'D', 'D', 'i', 'u', '2', 'O', 'p', 0, |
| /* 26518 */ 'S', 'e', 'l', 'T', 'B', 't', 'n', 'e', 'Z', 'C', 'm', 'p', 0, |
| /* 26531 */ 'S', 'e', 'l', 'T', 'B', 't', 'e', 'q', 'Z', 'C', 'm', 'p', 0, |
| /* 26544 */ 'S', 'a', 'a', 'A', 'd', 'd', 'r', 0, |
| /* 26552 */ 'S', 'a', 'a', 'd', 'A', 'd', 'd', 'r', 0, |
| /* 26561 */ 'E', 'R', 'e', 't', 0, |
| /* 26566 */ 'S', 'e', 'l', 'T', 'B', 't', 'n', 'e', 'Z', 'S', 'l', 't', 0, |
| /* 26579 */ 'S', 'e', 'l', 'T', 'B', 't', 'e', 'q', 'Z', 'S', 'l', 't', 0, |
| /* 26592 */ 'L', 'B', 'u', 0, |
| /* 26596 */ 'D', 'S', 'U', 'B', 'u', 0, |
| /* 26602 */ 'B', 'A', 'D', 'D', 'u', 0, |
| /* 26608 */ 'D', 'A', 'D', 'D', 'u', 0, |
| /* 26614 */ 'L', 'H', 'u', 0, |
| /* 26618 */ 'S', 'L', 'T', 'u', 0, |
| /* 26623 */ 'P', 's', 'e', 'u', 'd', 'o', 'D', 'M', 'U', 'L', 'T', 'u', 0, |
| /* 26636 */ 'P', 's', 'e', 'u', 'd', 'o', 'M', 'U', 'L', 'T', 'u', 0, |
| /* 26648 */ 'L', 'W', 'u', 0, |
| /* 26652 */ 'U', 'l', 'h', 'u', 0, |
| /* 26657 */ 'L', 'O', 'N', 'G', '_', 'B', 'R', 'A', 'N', 'C', 'H', '_', 'D', 'A', 'D', 'D', 'i', 'u', 0, |
| /* 26676 */ 'L', 'E', 'A', '_', 'A', 'D', 'D', 'i', 'u', 0, |
| /* 26686 */ 'L', 'O', 'N', 'G', '_', 'B', 'R', 'A', 'N', 'C', 'H', '_', 'A', 'D', 'D', 'i', 'u', 0, |
| /* 26704 */ 'S', 'L', 'T', 'i', 'u', 0, |
| /* 26710 */ 'S', 'e', 'l', 'T', 'B', 't', 'n', 'e', 'Z', 'S', 'l', 't', 'i', 'u', 0, |
| /* 26725 */ 'S', 'e', 'l', 'T', 'B', 't', 'e', 'q', 'Z', 'S', 'l', 't', 'i', 'u', 0, |
| /* 26740 */ 'S', 'e', 'l', 'T', 'B', 't', 'n', 'e', 'Z', 'S', 'l', 't', 'u', 0, |
| /* 26754 */ 'S', 'e', 'l', 'T', 'B', 't', 'e', 'q', 'Z', 'S', 'l', 't', 'u', 0, |
| /* 26768 */ 'U', 'l', 'w', 0, |
| /* 26772 */ 'U', 's', 'w', 0, |
| }; |
| |
| extern const unsigned MipsInstrNameIndices[] = { |
| 14934U, 20356U, 21966U, 20526U, 15275U, 15256U, 15284U, 15529U, |
| 13320U, 13335U, 13214U, 13374U, 22458U, 13112U, 15265U, 12881U, |
| 25555U, 13003U, 23481U, 11409U, 21480U, 15501U, 23428U, 11454U, |
| 23417U, 13036U, 21606U, 21593U, 22000U, 23256U, 23279U, 15433U, |
| 15480U, 15453U, 15316U, 11308U, 10109U, 15594U, 23740U, 23770U, |
| 15681U, 15688U, 11372U, 22263U, 22241U, 13212U, 14932U, 25523U, |
| 13122U, 23218U, 22392U, 23496U, 22409U, 22209U, 10995U, 22441U, |
| 23439U, 22342U, 23513U, 10969U, 11431U, 22025U, 11249U, 11193U, |
| 11223U, 11234U, 11174U, 11204U, 13075U, 13059U, 22475U, 13388U, |
| 13405U, 11324U, 10115U, 11378U, 11355U, 22268U, 22247U, 25493U, |
| 20477U, 25476U, 20460U, 11280U, 10081U, 12873U, 11422U, 23237U, |
| 10881U, 22505U, 23566U, 10987U, 23406U, 23394U, 23471U, 13429U, |
| 23559U, 13361U, 23575U, 15394U, 22176U, 22169U, 21567U, 21560U, |
| 23228U, 20583U, 12906U, 20567U, 12865U, 20575U, 12898U, 20559U, |
| 12857U, 21472U, 21464U, 13474U, 13466U, 11273U, 10074U, 15587U, |
| 8341U, 11167U, 23721U, 15674U, 23922U, 21864U, 1181U, 13422U, |
| 1163U, 0U, 13249U, 23551U, 10959U, 14960U, 14984U, 21529U, |
| 21538U, 22385U, 20434U, 13145U, 20400U, 20410U, 12914U, 12929U, |
| 20378U, 20389U, 11314U, 15149U, 20446U, 25462U, 20453U, 25469U, |
| 21954U, 23303U, 23335U, 23314U, 22224U, 25650U, 13194U, 25612U, |
| 13176U, 21585U, 21494U, 13093U, 15400U, 22434U, 20493U, 23505U, |
| 22195U, 23450U, 23458U, 23523U, 21979U, 12990U, 11021U, 22044U, |
| 22060U, 26144U, 20542U, 21841U, 20927U, 21011U, 21227U, 3905U, |
| 9214U, 860U, 8570U, 3041U, 8892U, 8211U, 9529U, 3787U, |
| 9054U, 742U, 8410U, 2871U, 8732U, 8099U, 9375U, 3828U, |
| 9109U, 783U, 8465U, 2912U, 8787U, 8138U, 9428U, 3985U, |
| 9322U, 940U, 8678U, 3187U, 9000U, 8287U, 9633U, 3869U, |
| 9164U, 824U, 8520U, 3005U, 8842U, 8177U, 9481U, 3807U, |
| 9081U, 762U, 8437U, 2891U, 8759U, 8118U, 9401U, 3945U, |
| 9268U, 900U, 8624U, 3081U, 8946U, 8249U, 9581U, 3767U, |
| 9027U, 722U, 8383U, 2851U, 8705U, 8080U, 9349U, 3964U, |
| 9294U, 919U, 8650U, 3166U, 8972U, 8267U, 9606U, 3848U, |
| 9136U, 803U, 8492U, 2984U, 8814U, 8157U, 9454U, 3925U, |
| 9241U, 880U, 8597U, 3061U, 8919U, 8230U, 9555U, 3889U, |
| 9191U, 844U, 8547U, 3025U, 8869U, 8196U, 9507U, 9689U, |
| 21959U, 18934U, 26250U, 12957U, 26187U, 15301U, 26211U, 23612U, |
| 26382U, 15570U, 26289U, 23270U, 26358U, 15560U, 26263U, 23676U, |
| 26408U, 15600U, 26330U, 12999U, 26199U, 15306U, 26224U, 23627U, |
| 26395U, 15576U, 26303U, 23310U, 26370U, 15565U, 26276U, 23681U, |
| 26421U, 15606U, 26344U, 26237U, 20625U, 20913U, 20806U, 21106U, |
| 20997U, 21213U, 17126U, 25984U, 25998U, 25912U, 25905U, 4509U, |
| 4056U, 4537U, 4086U, 4567U, 4598U, 4495U, 4041U, 4523U, |
| 4071U, 4551U, 4583U, 2729U, 3407U, 122U, 25560U, 20853U, |
| 21153U, 140U, 1120U, 26317U, 26114U, 26124U, 26153U, 15539U, |
| 25859U, 22204U, 25874U, 26090U, 26434U, 26066U, 26165U, 26102U, |
| 26445U, 26078U, 26176U, 26561U, 2742U, 3423U, 12145U, 24715U, |
| 20591U, 20608U, 20821U, 21121U, 4656U, 20641U, 21297U, 20688U, |
| 21340U, 20836U, 20664U, 21318U, 21136U, 20734U, 21382U, 20711U, |
| 21361U, 20758U, 21404U, 25947U, 25932U, 25960U, 25973U, 6793U, |
| 25673U, 25683U, 26040U, 3753U, 8055U, 2020U, 21618U, 21703U, |
| 26686U, 26497U, 26657U, 26475U, 25780U, 26456U, 3453U, 18478U, |
| 1088U, 3644U, 1055U, 3475U, 1078U, 3634U, 22083U, 1035U, |
| 22297U, 22100U, 22314U, 1118U, 25509U, 43U, 128U, 21659U, |
| 22283U, 103U, 14938U, 21447U, 1102U, 3673U, 20868U, 21168U, |
| 20891U, 21191U, 25516U, 55U, 146U, 21666U, 22290U, 110U, |
| 14949U, 21458U, 26318U, 26125U, 26154U, 4916U, 5049U, 4948U, |
| 5101U, 21576U, 25867U, 3577U, 20942U, 21026U, 21242U, 20943U, |
| 21027U, 21243U, 9869U, 9771U, 9984U, 13636U, 13531U, 13796U, |
| 23932U, 15644U, 23964U, 15660U, 25005U, 23363U, 26623U, 23728U, |
| 23758U, 15078U, 3100U, 25720U, 3518U, 5161U, 8032U, 20218U, |
| 7826U, 25693U, 3489U, 5131U, 8004U, 11297U, 23594U, 19662U, |
| 17458U, 14908U, 2790U, 18110U, 21430U, 3235U, 18499U, 10098U, |
| 23582U, 19647U, 17389U, 14919U, 2803U, 21743U, 18124U, 23375U, |
| 19626U, 26636U, 20319U, 13565U, 9806U, 25919U, 3658U, 23747U, |
| 379U, 2338U, 15041U, 2941U, 22749U, 611U, 2627U, 15117U, |
| 3145U, 23103U, 526U, 2542U, 15095U, 3119U, 22987U, 12797U, |
| 650U, 23136U, 23777U, 15540U, 25860U, 22205U, 25875U, 9659U, |
| 3738U, 203U, 26010U, 26048U, 26091U, 26435U, 26056U, 26135U, |
| 12961U, 25852U, 3568U, 23617U, 25889U, 3604U, 25882U, 3586U, |
| 25897U, 3614U, 3595U, 3624U, 20781U, 20972U, 21056U, 21081U, |
| 21272U, 26067U, 26166U, 8067U, 2031U, 21632U, 21718U, 3760U, |
| 18485U, 20794U, 20985U, 21069U, 21094U, 21285U, 26544U, 26552U, |
| 25665U, 25657U, 26531U, 25810U, 26579U, 25838U, 26725U, 26754U, |
| 26518U, 25796U, 26566U, 25824U, 26710U, 26740U, 4861U, 4320U, |
| 4335U, 4873U, 5088U, 15408U, 13274U, 13256U, 13290U, 13306U, |
| 13349U, 2760U, 9707U, 1976U, 17669U, 6670U, 18409U, 6802U, |
| 21489U, 18530U, 26025U, 26103U, 26446U, 26079U, 26177U, 25741U, |
| 26652U, 26768U, 25745U, 26772U, 20957U, 21041U, 21257U, 13755U, |
| 17925U, 9929U, 1329U, 24933U, 20093U, 11269U, 11056U, 17411U, |
| 5847U, 18610U, 16358U, 16771U, 18782U, 7712U, 13556U, 1432U, |
| 13673U, 1487U, 24676U, 1845U, 24250U, 1817U, 13628U, 17821U, |
| 13735U, 17912U, 24915U, 20081U, 11080U, 17422U, 10153U, 11527U, |
| 14035U, 24003U, 10561U, 12314U, 14524U, 24960U, 10753U, 12679U, |
| 14773U, 25309U, 16988U, 5587U, 9797U, 1234U, 9907U, 1297U, |
| 7682U, 13820U, 1575U, 10009U, 17312U, 13775U, 1547U, 9949U, |
| 17259U, 10367U, 11891U, 14220U, 24368U, 10823U, 12760U, 14843U, |
| 25399U, 11113U, 17431U, 10137U, 11510U, 14019U, 23986U, 17465U, |
| 6069U, 25750U, 20242U, 26670U, 20338U, 26603U, 20296U, 20421U, |
| 6860U, 11049U, 5835U, 11368U, 16799U, 5428U, 2154U, 16826U, |
| 5461U, 10242U, 6725U, 17472U, 6078U, 23848U, 25755U, 3541U, |
| 20250U, 11402U, 1389U, 10466U, 12161U, 14373U, 24762U, 10658U, |
| 12526U, 14631U, 25156U, 14980U, 11043U, 5824U, 6753U, 10543U, |
| 12296U, 14497U, 24942U, 10735U, 12661U, 14755U, 25291U, 10491U, |
| 12235U, 14436U, 24836U, 10683U, 12600U, 14694U, 25230U, 4388U, |
| 4264U, 4772U, 4416U, 4213U, 4712U, 4280U, 5075U, 5014U, |
| 16783U, 26602U, 15160U, 10893U, 5703U, 20420U, 1750U, 76U, |
| 222U, 216U, 230U, 10864U, 5368U, 25619U, 6010U, 13171U, |
| 15336U, 17641U, 25586U, 5973U, 23213U, 15554U, 19587U, 25626U, |
| 6023U, 25593U, 5986U, 10303U, 11841U, 14170U, 24318U, 10437U, |
| 12086U, 14344U, 24591U, 5666U, 21871U, 3255U, 11075U, 2071U, |
| 5870U, 15544U, 17033U, 10928U, 5763U, 11137U, 5415U, 2130U, |
| 17449U, 6036U, 18831U, 10867U, 2043U, 5674U, 11091U, 2090U, |
| 5909U, 25576U, 3361U, 15168U, 10904U, 5724U, 15513U, 19103U, |
| 18244U, 11119U, 2106U, 5951U, 15620U, 20179U, 25640U, 3393U, |
| 10936U, 5776U, 11143U, 2138U, 6047U, 15632U, 20202U, 10279U, |
| 11817U, 14146U, 24294U, 10409U, 11940U, 14247U, 24411U, 10333U, |
| 11857U, 14186U, 24334U, 10451U, 12130U, 14358U, 24635U, 23709U, |
| 19726U, 21503U, 6880U, 25581U, 3368U, 10912U, 5737U, 11125U, |
| 2114U, 5962U, 15626U, 20187U, 11086U, 2083U, 5899U, 11097U, |
| 2098U, 5920U, 25645U, 3400U, 15175U, 10944U, 5789U, 15521U, |
| 19114U, 18254U, 11149U, 2146U, 6058U, 15638U, 20210U, 10382U, |
| 23897U, 10375U, 23885U, 13024U, 2723U, 10872U, 2050U, 5684U, |
| 10249U, 11795U, 14124U, 24272U, 10221U, 11774U, 14103U, 24176U, |
| 15311U, 17023U, 10920U, 5750U, 11131U, 5402U, 2122U, 17440U, |
| 5999U, 17572U, 11103U, 5931U, 10858U, 12834U, 14878U, 23891U, |
| 25456U, 11108U, 5941U, 713U, 1909U, 16300U, 15138U, 16854U, |
| 5483U, 18228U, 6782U, 10257U, 23861U, 10351U, 11875U, 14204U, |
| 24352U, 10630U, 12403U, 14603U, 25073U, 10853U, 12820U, 14873U, |
| 23880U, 25451U, 4799U, 4445U, 4811U, 4458U, 4787U, 4432U, |
| 4698U, 5123U, 4622U, 5115U, 4613U, 12969U, 12944U, 17500U, |
| 17526U, 6613U, 7948U, 2433U, 6276U, 22842U, 7260U, 680U, |
| 2690U, 6545U, 19919U, 23162U, 19551U, 7541U, 10288U, 11826U, |
| 14155U, 24303U, 10424U, 12010U, 14270U, 24494U, 92U, 15749U, |
| 16342U, 9670U, 22424U, 982U, 1015U, 1069U, 12153U, 6418U, |
| 22979U, 7402U, 10499U, 12243U, 14444U, 24844U, 10691U, 12608U, |
| 14702U, 25238U, 10483U, 12227U, 14428U, 24828U, 10675U, 12592U, |
| 14686U, 25222U, 21426U, 18492U, 6871U, 7980U, 10517U, 12261U, |
| 14462U, 24862U, 10709U, 12626U, 14720U, 25256U, 10578U, 12331U, |
| 14541U, 24977U, 10781U, 12707U, 14801U, 25337U, 25608U, 20195U, |
| 7805U, 7997U, 9844U, 1248U, 9746U, 1202U, 9959U, 1344U, |
| 9857U, 17217U, 9759U, 17144U, 9972U, 17272U, 9875U, 17232U, |
| 9777U, 17159U, 9990U, 17287U, 6195U, 7155U, 12070U, 6404U, |
| 13642U, 17832U, 22963U, 7388U, 11766U, 22768U, 11672U, 6166U, |
| 13537U, 17751U, 22694U, 7126U, 12471U, 6477U, 13802U, 17952U, |
| 23064U, 7461U, 11733U, 6180U, 22703U, 7140U, 12023U, 6358U, |
| 22917U, 7342U, 11625U, 6120U, 22648U, 7080U, 12424U, 6431U, |
| 23018U, 7415U, 12049U, 6373U, 22927U, 7357U, 11651U, 6135U, |
| 22658U, 7095U, 12450U, 6446U, 23028U, 7430U, 11983U, 6329U, |
| 22875U, 7313U, 12060U, 6389U, 22946U, 7373U, 11662U, 6151U, |
| 22677U, 7111U, 12461U, 6462U, 23047U, 7446U, 11993U, 6344U, |
| 22892U, 7328U, 10613U, 12386U, 14586U, 25056U, 10805U, 14825U, |
| 25381U, 9684U, 9691U, 11256U, 13454U, 23911U, 11155U, 13437U, |
| 23904U, 117U, 15765U, 16350U, 9677U, 22537U, 19149U, 23938U, |
| 19838U, 15650U, 22547U, 19162U, 23970U, 19851U, 6834U, 2456U, |
| 16556U, 6305U, 22861U, 19356U, 7289U, 3323U, 516U, 16161U, |
| 2532U, 16644U, 15666U, 6847U, 3212U, 3340U, 25011U, 20105U, |
| 7780U, 703U, 16287U, 2713U, 16758U, 23181U, 19576U, 7570U, |
| 498U, 16137U, 2514U, 16620U, 22956U, 19410U, 371U, 15998U, |
| 2330U, 16508U, 22743U, 19292U, 344U, 15962U, 2303U, 16484U, |
| 22687U, 19262U, 573U, 16213U, 2589U, 16696U, 23057U, 19463U, |
| 303U, 15909U, 2262U, 16431U, 22623U, 19217U, 313U, 15922U, |
| 2272U, 16444U, 22631U, 19228U, 431U, 16049U, 2390U, 16531U, |
| 22807U, 19335U, 543U, 16174U, 2559U, 16657U, 23002U, 19430U, |
| 324U, 15936U, 2283U, 16458U, 22640U, 19240U, 553U, 16187U, |
| 2569U, 16670U, 23010U, 19441U, 478U, 16111U, 2494U, 16594U, |
| 22909U, 19388U, 353U, 15974U, 2312U, 16496U, 22729U, 19272U, |
| 488U, 16124U, 2504U, 16607U, 22938U, 19399U, 334U, 15949U, |
| 2293U, 16471U, 22669U, 19251U, 563U, 16200U, 2579U, 16683U, |
| 23039U, 19452U, 450U, 16074U, 2466U, 16569U, 22885U, 19367U, |
| 4896U, 4735U, 4362U, 11268U, 25749U, 26669U, 26608U, 14903U, |
| 20427U, 14969U, 14979U, 21502U, 21425U, 7979U, 25607U, 7996U, |
| 23716U, 23697U, 23250U, 19595U, 7622U, 23546U, 1025U, 20372U, |
| 23691U, 14890U, 22429U, 20366U, 23670U, 23717U, 23698U, 7733U, |
| 7743U, 10597U, 12370U, 14560U, 25030U, 10789U, 12735U, 14809U, |
| 25365U, 18088U, 6727U, 9665U, 7911U, 9U, 97U, 1141U, |
| 20500U, 15U, 11449U, 23606U, 23386U, 49U, 134U, 1147U, |
| 20513U, 36U, 14008U, 23632U, 15582U, 23369U, 26629U, 23658U, |
| 7971U, 12287U, 14488U, 24897U, 12652U, 14746U, 25282U, 12209U, |
| 14410U, 24810U, 12574U, 14668U, 25204U, 13884U, 1632U, 13959U, |
| 1684U, 24433U, 19929U, 13921U, 18001U, 15226U, 18317U, 21932U, |
| 18906U, 13985U, 1720U, 13864U, 1602U, 21580U, 13898U, 1651U, |
| 13972U, 1702U, 24445U, 19944U, 13947U, 18033U, 12179U, 14391U, |
| 24780U, 12544U, 14649U, 25174U, 15237U, 18331U, 21943U, 18920U, |
| 13995U, 1735U, 13912U, 1670U, 22336U, 974U, 23836U, 13444U, |
| 23734U, 11340U, 15534U, 960U, 1005U, 23788U, 8378U, 238U, |
| 23703U, 15549U, 967U, 23794U, 10069U, 26596U, 23764U, 21856U, |
| 13049U, 6952U, 4982U, 4960U, 9703U, 17131U, 5618U, 14895U, |
| 18096U, 6735U, 23390U, 23251U, 10952U, 5802U, 19596U, 7623U, |
| 21860U, 13054U, 6961U, 23547U, 21836U, 21522U, 23822U, 19789U, |
| 18555U, 23830U, 19800U, 18809U, 24742U, 20043U, 24705U, 20017U, |
| 14568U, 18066U, 25436U, 20129U, 24732U, 20030U, 24686U, 19992U, |
| 14506U, 18054U, 24643U, 19970U, 22532U, 989U, 19640U, 7654U, |
| 507U, 16149U, 2523U, 16632U, 22972U, 19420U, 11574U, 284U, |
| 15884U, 2243U, 16419U, 22608U, 19196U, 7068U, 24050U, 11719U, |
| 24155U, 12009U, 24493U, 12152U, 24753U, 11611U, 24087U, 12410U, |
| 25080U, 469U, 16099U, 2485U, 996U, 16330U, 11681U, 24117U, |
| 12100U, 24605U, 12033U, 24507U, 11635U, 24101U, 12434U, 25094U, |
| 11695U, 24131U, 11969U, 24464U, 12783U, 632U, 16263U, 2648U, |
| 16734U, 23122U, 19505U, 7487U, 25422U, 14262U, 24478U, 11482U, |
| 23956U, 11918U, 24389U, 12114U, 24619U, 12339U, 24985U, 12715U, |
| 25345U, 11927U, 24398U, 12123U, 24628U, 10390U, 11905U, 14228U, |
| 24376U, 11474U, 23948U, 2444U, 6290U, 22851U, 7274U, 691U, |
| 2701U, 6559U, 19959U, 23171U, 19563U, 7555U, 11581U, 24057U, |
| 11536U, 24012U, 12813U, 25444U, 11518U, 23994U, 11962U, 24457U, |
| 641U, 16275U, 2657U, 16746U, 6503U, 23129U, 19515U, 7499U, |
| 11552U, 24028U, 11948U, 441U, 16062U, 2400U, 16544U, 22815U, |
| 19346U, 7218U, 24419U, 400U, 16009U, 2359U, 16519U, 22776U, |
| 19301U, 7195U, 15144U, 12002U, 24486U, 12487U, 25117U, 12512U, |
| 25142U, 11726U, 24162U, 12016U, 24500U, 11618U, 24094U, 12417U, |
| 25087U, 11688U, 24124U, 12107U, 24612U, 12504U, 582U, 16225U, |
| 2598U, 16708U, 23080U, 19473U, 25134U, 11545U, 265U, 15859U, |
| 2224U, 16407U, 22593U, 19175U, 7056U, 24021U, 12041U, 24515U, |
| 11643U, 24109U, 12442U, 25102U, 11703U, 24139U, 11976U, 24471U, |
| 12349U, 24995U, 12725U, 25355U, 14276U, 24523U, 12189U, 24790U, |
| 12554U, 25184U, 14993U, 6771U, 23540U, 7643U, 12200U, 14401U, |
| 24801U, 12565U, 14659U, 25195U, 12170U, 14382U, 24771U, 12535U, |
| 14640U, 25165U, 15417U, 18421U, 10838U, 12775U, 14858U, 25414U, |
| 10417U, 11955U, 14255U, 24426U, 10198U, 11603U, 14080U, 24079U, |
| 10459U, 12138U, 14366U, 24650U, 22425U, 10644U, 12495U, 14617U, |
| 25125U, 23843U, 10206U, 11711U, 14088U, 24147U, 19818U, 19125U, |
| 7023U, 15136U, 15164U, 22186U, 16930U, 3266U, 5389U, 5627U, |
| 5880U, 16949U, 19132U, 9727U, 2000U, 19023U, 19095U, 25541U, |
| 20156U, 18237U, 10898U, 2063U, 5713U, 10877U, 2057U, 5694U, |
| 22183U, 16922U, 3261U, 21826U, 16790U, 5378U, 6926U, 9721U, |
| 1992U, 7884U, 7919U, 19017U, 18223U, 4706U, 3746U, 4639U, |
| 4631U, 4845U, 4677U, 9735U, 2010U, 12849U, 17479U, 16969U, |
| 25546U, 20164U, 7663U, 17138U, 5641U, 26592U, 3689U, 13161U, |
| 17625U, 20281U, 11348U, 82U, 1924U, 5330U, 15733U, 1131U, |
| 5248U, 7852U, 1889U, 10236U, 11789U, 14118U, 24266U, 15248U, |
| 11038U, 21992U, 162U, 1938U, 10185U, 11590U, 14067U, 24066U, |
| 26676U, 3708U, 20334U, 13471U, 2780U, 12975U, 17535U, 16998U, |
| 25537U, 20149U, 17699U, 26614U, 3695U, 13166U, 17633U, 20304U, |
| 16846U, 5473U, 15414U, 3207U, 7903U, 11351U, 7941U, 13010U, |
| 17549U, 18415U, 6808U, 7965U, 9666U, 5609U, 7912U, 6762U, |
| 174U, 1954U, 15797U, 25792U, 3562U, 20274U, 23919U, 17007U, |
| 3351U, 152U, 15781U, 1153U, 5310U, 7868U, 1899U, 21673U, |
| 18641U, 13137U, 17611U, 18583U, 15612U, 3223U, 13014U, 17556U, |
| 18464U, 16883U, 5518U, 16312U, 11070U, 5860U, 18817U, 22377U, |
| 3293U, 13083U, 17586U, 19081U, 18793U, 11064U, 19711U, 25551U, |
| 186U, 15815U, 19141U, 20172U, 19826U, 7764U, 26648U, 4115U, |
| 4179U, 4147U, 4196U, 4725U, 4466U, 4351U, 4825U, 4482U, |
| 4232U, 4294U, 11303U, 11751U, 6222U, 22721U, 7182U, 14318U, |
| 24565U, 23600U, 21806U, 18756U, 19668U, 10822U, 12759U, 14842U, |
| 25398U, 294U, 15897U, 2253U, 21694U, 18671U, 17464U, 14291U, |
| 24538U, 22616U, 19207U, 15342U, 18345U, 22117U, 18953U, 15368U, |
| 18377U, 22143U, 18985U, 11503U, 6108U, 22586U, 7044U, 10526U, |
| 12270U, 14471U, 24871U, 10718U, 12635U, 14729U, 25265U, 10162U, |
| 11537U, 14044U, 24013U, 12814U, 6574U, 23189U, 10605U, 12378U, |
| 14578U, 7583U, 25048U, 10797U, 12743U, 14817U, 25373U, 10U, |
| 5186U, 98U, 2160U, 15757U, 5228U, 1142U, 5268U, 16U, |
| 15695U, 5196U, 245U, 15833U, 2169U, 16369U, 5278U, 22U, |
| 15704U, 14914U, 16836U, 2796U, 21734U, 18683U, 18116U, 21436U, |
| 16901U, 3241U, 21769U, 18707U, 18505U, 22331U, 11490U, 6096U, |
| 22579U, 7032U, 10508U, 12252U, 14453U, 24853U, 10700U, 12617U, |
| 14711U, 25247U, 10145U, 11519U, 14027U, 23995U, 11963U, 6318U, |
| 22869U, 10535U, 12279U, 14480U, 7302U, 24889U, 10727U, 12644U, |
| 14738U, 25274U, 11450U, 10067U, 17379U, 23607U, 7692U, 6087U, |
| 10475U, 12219U, 14420U, 24820U, 10667U, 12584U, 14678U, 25214U, |
| 16808U, 5439U, 18565U, 6904U, 23854U, 362U, 15986U, 2321U, |
| 15034U, 2932U, 18183U, 22736U, 19282U, 2198U, 15012U, 2825U, |
| 22557U, 409U, 16021U, 2368U, 15060U, 2962U, 18193U, 22783U, |
| 19311U, 602U, 16251U, 2618U, 15110U, 3136U, 18203U, 23096U, |
| 19495U, 2211U, 15023U, 2838U, 22568U, 420U, 16035U, 2379U, |
| 15069U, 2973U, 18213U, 22792U, 19323U, 10104U, 11743U, 6209U, |
| 22713U, 7169U, 14308U, 24555U, 23588U, 21796U, 18743U, 19653U, |
| 10814U, 12751U, 14834U, 25390U, 275U, 15872U, 2234U, 21685U, |
| 18659U, 17395U, 14282U, 24529U, 22601U, 19186U, 50U, 5218U, |
| 135U, 2189U, 16395U, 15773U, 5238U, 1148U, 5300U, 37U, |
| 15724U, 5207U, 255U, 15846U, 2179U, 16382U, 5289U, 29U, |
| 15714U, 14944U, 2818U, 21760U, 18695U, 18140U, 21553U, 18591U, |
| 21453U, 3248U, 21778U, 18719U, 18522U, 66U, 198U, 1171U, |
| 71U, 211U, 1176U, 22353U, 14009U, 23633U, 7702U, 6705U, |
| 15583U, 15380U, 18392U, 22155U, 19000U, 15182U, 18264U, 21888U, |
| 18853U, 13695U, 17872U, 24722U, 1860U, 13745U, 1517U, 24924U, |
| 1875U, 14328U, 24575U, 13933U, 18016U, 13873U, 1616U, 23370U, |
| 21816U, 18769U, 21787U, 18731U, 19632U, 26630U, 20325U, 23653U, |
| 7723U, 10846U, 12790U, 14866U, 25429U, 18457U, 6825U, 13613U, |
| 1459U, 14300U, 24547U, 7972U, 13716U, 1503U, 4691U, 4818U, |
| 4005U, 3728U, 10170U, 11560U, 14052U, 24036U, 10177U, 11567U, |
| 14059U, 24043U, 293U, 15896U, 2252U, 22615U, 19206U, 274U, |
| 15871U, 2233U, 22600U, 19185U, 22191U, 3273U, 10319U, 19031U, |
| 6970U, 23868U, 16960U, 5564U, 4886U, 4927U, 22192U, 16941U, |
| 5554U, 3274U, 10320U, 6744U, 19032U, 6971U, 23869U, 25771U, |
| 3549U, 20259U, 5026U, 13603U, 17797U, 13106U, 17602U, 6636U, |
| 10830U, 12767U, 14850U, 25406U, 10190U, 11595U, 14072U, 24071U, |
| 10637U, 12480U, 14610U, 25110U, 13571U, 17764U, 9812U, 17173U, |
| 3305U, 3314U, 21581U, 15211U, 8325U, 17061U, 18299U, 21917U, |
| 8362U, 17098U, 18888U, 15355U, 18361U, 22130U, 18969U, 15197U, |
| 8310U, 17043U, 18282U, 21903U, 8347U, 17080U, 18871U, 13515U, |
| 17732U, 24198U, 19886U, 13490U, 17716U, 24227U, 19901U, 13503U, |
| 1401U, 24183U, 1762U, 24210U, 1782U, 13227U, 12951U, 17510U, |
| 20140U, 17649U, 6647U, 7957U, 11394U, 1376U, 10053U, 17359U, |
| 21647U, 18623U, 22371U, 3285U, 19072U, 7012U, 6988U, 459U, |
| 16086U, 2475U, 16581U, 22901U, 19377U, 13846U, 17989U, 10035U, |
| 17335U, 13587U, 17786U, 9828U, 17195U, 12488U, 6491U, 23073U, |
| 7475U, 22337U, 23837U, 19809U, 19045U, 2421U, 6261U, 22832U, |
| 7245U, 668U, 2678U, 6530U, 19875U, 23152U, 19538U, 7526U, |
| 592U, 16238U, 2608U, 16721U, 23088U, 19484U, 4646U, 4022U, |
| 8306U, 11162U, 10570U, 12323U, 14533U, 24969U, 10773U, 12699U, |
| 14793U, 25329U, 10064U, 16782U, 5358U, 2015U, 12853U, 17486U, |
| 17373U, 5649U, 11083U, 2078U, 7895U, 11264U, 7934U, 12894U, |
| 17493U, 17425U, 5891U, 7928U, 11471U, 21511U, 16911U, 5540U, |
| 18538U, 6893U, 7987U, 87U, 1931U, 5344U, 15741U, 1136U, |
| 5258U, 7860U, 1894U, 23735U, 19736U, 15252U, 21996U, 168U, |
| 1946U, 9699U, 1970U, 17124U, 13462U, 2774U, 17692U, 25633U, |
| 3384U, 12840U, 6599U, 7814U, 23204U, 7608U, 25600U, 3375U, |
| 12825U, 6585U, 7793U, 23195U, 7594U, 11899U, 6235U, 22801U, |
| 7207U, 21875U, 25765U, 14005U, 16818U, 5451U, 2785U, 12979U, |
| 17542U, 10215U, 14097U, 24170U, 21441U, 23815U, 19779U, 18513U, |
| 13837U, 17977U, 10026U, 17323U, 13785U, 17938U, 25038U, 20116U, |
| 13579U, 17775U, 9820U, 17184U, 13706U, 17886U, 24880U, 20057U, |
| 13828U, 17965U, 10017U, 1362U, 13684U, 17858U, 9918U, 1313U, |
| 24695U, 20004U, 13482U, 17705U, 9738U, 1189U, 13652U, 17845U, |
| 9886U, 1266U, 24657U, 19980U, 13855U, 1588U, 10044U, 17347U, |
| 13595U, 1446U, 9836U, 17206U, 18048U, 6697U, 12983U, 6624U, |
| 10235U, 11788U, 14117U, 24265U, 10184U, 11589U, 14066U, 24065U, |
| 15535U, 16865U, 5496U, 1006U, 3444U, 10265U, 11803U, 14132U, |
| 24280U, 23789U, 19752U, 10397U, 11912U, 14235U, 18443U, 6816U, |
| 24383U, 23355U, 3334U, 19612U, 25775U, 3555U, 20266U, 26704U, |
| 3720U, 20347U, 26618U, 3701U, 20311U, 13028U, 25760U, 10342U, |
| 11866U, 14195U, 24343U, 10622U, 12395U, 14595U, 25065U, 8379U, |
| 10228U, 11781U, 14110U, 24258U, 10295U, 11833U, 14162U, 24310U, |
| 10430U, 12079U, 14337U, 24584U, 23704U, 19718U, 10131U, 11497U, |
| 14013U, 17117U, 23980U, 15550U, 16874U, 5507U, 10272U, 11810U, |
| 14139U, 24287U, 10311U, 11849U, 14178U, 24326U, 10444U, 12093U, |
| 14351U, 24598U, 23795U, 19760U, 10403U, 11934U, 14241U, 18450U, |
| 24405U, 21574U, 18601U, 6915U, 10653U, 12521U, 14626U, 25151U, |
| 10070U, 13547U, 1418U, 13662U, 1471U, 24666U, 1830U, 24242U, |
| 1804U, 13620U, 17810U, 13725U, 17899U, 24906U, 20069U, 10762U, |
| 12688U, 14782U, 25318U, 10586U, 12359U, 14549U, 25019U, 10552U, |
| 12305U, 14515U, 24951U, 10744U, 12670U, 14764U, 25300U, 16978U, |
| 5575U, 9788U, 1220U, 9896U, 1281U, 7672U, 13812U, 1562U, |
| 10001U, 17301U, 13765U, 1532U, 9939U, 17246U, 10359U, 11883U, |
| 14212U, 24360U, 10815U, 12752U, 14835U, 25391U, 17382U, 5657U, |
| 26597U, 20288U, 180U, 1962U, 15806U, 23929U, 17015U, 5599U, |
| 3356U, 157U, 15789U, 1158U, 5320U, 7876U, 1904U, 21679U, |
| 18650U, 13141U, 17618U, 15616U, 3229U, 13019U, 17564U, 18471U, |
| 16892U, 5529U, 16321U, 18824U, 22381U, 3299U, 13088U, 17594U, |
| 19088U, 18801U, 6942U, 192U, 15824U, 19832U, 7772U, 11016U, |
| 14884U, 18079U, 6714U, 17403U, 5814U, 15425U, 18432U, 4670U, |
| 4033U, 4131U, 4837U, 4853U, 4163U, 4101U, 4992U, 4906U, |
| 4747U, 4375U, 4759U, 4402U, 4937U, 4015U, 4971U, 4108U, |
| 5003U, 5062U, 4248U, 4307U, 21879U, 14955U, 18148U, 18838U, |
| 12965U, 14893U, 23638U, 19685U, 18094U, 23622U, 19677U, 17519U, |
| 23807U, 13240U, 17657U, 19768U, 21547U, 18574U, 22077U, 18944U, |
| 15005U, 18173U, 22364U, 19062U, 23800U, 13232U, 6657U, 7752U, |
| 21517U, 18547U, 21883U, 18845U, 14999U, 18164U, 22358U, 19053U, |
| 23359U, 14974U, 19694U, 18156U, 23686U, 19703U, 19619U, 13032U, |
| 14898U, 18102U, 17579U, 2409U, 6246U, 22822U, 7230U, 656U, |
| 2666U, 6515U, 19864U, 23142U, 19525U, 7511U, 23644U, 23765U, |
| 19744U, 23651U, 61U, 23664U, 10214U, 11759U, 14096U, 24169U, |
| 23274U, 19604U, 7633U, 21653U, 18632U, 7000U, 13449U, 17684U, |
| 6687U, 22243U, 16940U, 5553U, 3279U, 10326U, 6743U, 19038U, |
| 6979U, 23874U, 25770U, 3548U, 20258U, 5037U, 11345U, |
| }; |
| |
| static inline void InitMipsMCInstrInfo(MCInstrInfo *II) { |
| II->InitMCInstrInfo(MipsInsts, MipsInstrNameIndices, MipsInstrNameData, 2751); |
| } |
| |
| } // end namespace llvm |
| #endif // GET_INSTRINFO_MC_DESC |
| |
| #ifdef GET_INSTRINFO_HEADER |
| #undef GET_INSTRINFO_HEADER |
| namespace llvm { |
| struct MipsGenInstrInfo : public TargetInstrInfo { |
| explicit MipsGenInstrInfo(int CFSetupOpcode = -1, int CFDestroyOpcode = -1, int CatchRetOpcode = -1, int ReturnOpcode = -1); |
| ~MipsGenInstrInfo() override = default; |
| |
| }; |
| } // end namespace llvm |
| #endif // GET_INSTRINFO_HEADER |
| |
| #ifdef GET_INSTRINFO_HELPER_DECLS |
| #undef GET_INSTRINFO_HELPER_DECLS |
| |
| |
| #endif // GET_INSTRINFO_HELPER_DECLS |
| |
| #ifdef GET_INSTRINFO_HELPERS |
| #undef GET_INSTRINFO_HELPERS |
| |
| #endif // GET_INSTRINFO_HELPERS |
| |
| #ifdef GET_INSTRINFO_CTOR_DTOR |
| #undef GET_INSTRINFO_CTOR_DTOR |
| namespace llvm { |
| extern const MCInstrDesc MipsInsts[]; |
| extern const unsigned MipsInstrNameIndices[]; |
| extern const char MipsInstrNameData[]; |
| MipsGenInstrInfo::MipsGenInstrInfo(int CFSetupOpcode, int CFDestroyOpcode, int CatchRetOpcode, int ReturnOpcode) |
| : TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) { |
| InitMCInstrInfo(MipsInsts, MipsInstrNameIndices, MipsInstrNameData, 2751); |
| } |
| } // end namespace llvm |
| #endif // GET_INSTRINFO_CTOR_DTOR |
| |
| #ifdef GET_INSTRINFO_OPERAND_ENUM |
| #undef GET_INSTRINFO_OPERAND_ENUM |
| namespace llvm { |
| namespace Mips { |
| namespace OpName { |
| enum { |
| OPERAND_LAST |
| }; |
| } // end namespace OpName |
| } // end namespace Mips |
| } // end namespace llvm |
| #endif //GET_INSTRINFO_OPERAND_ENUM |
| |
| #ifdef GET_INSTRINFO_NAMED_OPS |
| #undef GET_INSTRINFO_NAMED_OPS |
| namespace llvm { |
| namespace Mips { |
| LLVM_READONLY |
| int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) { |
| return -1; |
| } |
| } // end namespace Mips |
| } // end namespace llvm |
| #endif //GET_INSTRINFO_NAMED_OPS |
| |
| #ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM |
| #undef GET_INSTRINFO_OPERAND_TYPES_ENUM |
| namespace llvm { |
| namespace Mips { |
| namespace OpTypes { |
| enum OperandType { |
| InvertedImOperand = 0, |
| InvertedImOperand64 = 1, |
| PtrRC = 2, |
| brtarget = 3, |
| brtarget10_mm = 4, |
| brtarget1SImm16 = 5, |
| brtarget21 = 6, |
| brtarget21_mm = 7, |
| brtarget26 = 8, |
| brtarget26_mm = 9, |
| brtarget7_mm = 10, |
| brtarget_lsl2_mm = 11, |
| brtarget_mm = 12, |
| brtargetr6 = 13, |
| calloffset16 = 14, |
| calltarget = 15, |
| calltarget_mm = 16, |
| condcode = 17, |
| cpinst_operand = 18, |
| f32imm = 19, |
| f64imm = 20, |
| i16imm = 21, |
| i1imm = 22, |
| i32imm = 23, |
| i64imm = 24, |
| i8imm = 25, |
| imm64 = 26, |
| jmpoffset16 = 27, |
| jmptarget = 28, |
| jmptarget_mm = 29, |
| li16_imm = 30, |
| mem = 31, |
| mem16 = 32, |
| mem16_ea = 33, |
| mem16sp = 34, |
| mem_ea = 35, |
| mem_mm_11 = 36, |
| mem_mm_12 = 37, |
| mem_mm_16 = 38, |
| mem_mm_4 = 39, |
| mem_mm_4_lsl1 = 40, |
| mem_mm_4_lsl2 = 41, |
| mem_mm_4sp = 42, |
| mem_mm_9 = 43, |
| mem_mm_gp_simm7_lsl2 = 44, |
| mem_mm_sp_imm5_lsl2 = 45, |
| mem_msa = 46, |
| mem_simm10 = 47, |
| mem_simm10_lsl1 = 48, |
| mem_simm10_lsl2 = 49, |
| mem_simm10_lsl3 = 50, |
| mem_simm11 = 51, |
| mem_simm12 = 52, |
| mem_simm16 = 53, |
| mem_simm9 = 54, |
| mem_simm9_exp = 55, |
| mem_simmptr = 56, |
| pcrel16 = 57, |
| ptype0 = 58, |
| ptype1 = 59, |
| ptype2 = 60, |
| ptype3 = 61, |
| ptype4 = 62, |
| ptype5 = 63, |
| reglist = 64, |
| reglist16 = 65, |
| simm10 = 66, |
| simm10_64 = 67, |
| simm10_lsl1 = 68, |
| simm10_lsl2 = 69, |
| simm10_lsl3 = 70, |
| simm11 = 71, |
| simm12 = 72, |
| simm16 = 73, |
| simm16_64 = 74, |
| simm16_relaxed = 75, |
| simm18_lsl3 = 76, |
| simm19_lsl2 = 77, |
| simm23_lsl2 = 78, |
| simm32 = 79, |
| simm32_relaxed = 80, |
| simm3_lsa2 = 81, |
| simm4 = 82, |
| simm5 = 83, |
| simm6 = 84, |
| simm7_lsl2 = 85, |
| simm9 = 86, |
| simm9_addiusp = 87, |
| size_ins = 88, |
| type0 = 89, |
| type1 = 90, |
| type2 = 91, |
| type3 = 92, |
| type4 = 93, |
| type5 = 94, |
| uimm1 = 95, |
| uimm10 = 96, |
| uimm16 = 97, |
| uimm16_64 = 98, |
| uimm16_64_relaxed = 99, |
| uimm16_altrelaxed = 100, |
| uimm16_relaxed = 101, |
| uimm1_ptr = 102, |
| uimm2 = 103, |
| uimm20 = 104, |
| uimm26 = 105, |
| uimm2_plus1 = 106, |
| uimm2_ptr = 107, |
| uimm3 = 108, |
| uimm32_coerced = 109, |
| uimm3_ptr = 110, |
| uimm3_shift = 111, |
| uimm4 = 112, |
| uimm4_andi = 113, |
| uimm4_ptr = 114, |
| uimm5 = 115, |
| uimm5_64 = 116, |
| uimm5_64_report_uimm6 = 117, |
| uimm5_inssize_plus1 = 118, |
| uimm5_lsl2 = 119, |
| uimm5_plus1 = 120, |
| uimm5_plus1_report_uimm6 = 121, |
| uimm5_plus32 = 122, |
| uimm5_plus32_normalize = 123, |
| uimm5_plus32_normalize_64 = 124, |
| uimm5_plus33 = 125, |
| uimm5_report_uimm6 = 126, |
| uimm6 = 127, |
| uimm6_lsl2 = 128, |
| uimm7 = 129, |
| uimm8 = 130, |
| uimm_range_2_64 = 131, |
| uimmz = 132, |
| untyped_imm_0 = 133, |
| vsplat_simm10 = 134, |
| vsplat_simm5 = 135, |
| vsplat_uimm1 = 136, |
| vsplat_uimm2 = 137, |
| vsplat_uimm3 = 138, |
| vsplat_uimm4 = 139, |
| vsplat_uimm5 = 140, |
| vsplat_uimm6 = 141, |
| vsplat_uimm8 = 142, |
| ACC64DSPOpnd = 143, |
| AFGR64Opnd = 144, |
| CCROpnd = 145, |
| COP0Opnd = 146, |
| COP2Opnd = 147, |
| COP3Opnd = 148, |
| DSPROpnd = 149, |
| FCCRegsOpnd = 150, |
| FGR32Opnd = 151, |
| FGR64Opnd = 152, |
| FGRCCOpnd = 153, |
| GPR32NonZeroOpnd = 154, |
| GPR32Opnd = 155, |
| GPR32ZeroOpnd = 156, |
| GPR64Opnd = 157, |
| GPRMM16Opnd = 158, |
| GPRMM16OpndMoveP = 159, |
| GPRMM16OpndMovePPairFirst = 160, |
| GPRMM16OpndMovePPairSecond = 161, |
| GPRMM16OpndZero = 162, |
| HI32DSPOpnd = 163, |
| HWRegsOpnd = 164, |
| LO32DSPOpnd = 165, |
| MSA128BOpnd = 166, |
| MSA128CROpnd = 167, |
| MSA128DOpnd = 168, |
| MSA128F16Opnd = 169, |
| MSA128HOpnd = 170, |
| MSA128WOpnd = 171, |
| StrictlyAFGR64Opnd = 172, |
| StrictlyFGR32Opnd = 173, |
| StrictlyFGR64Opnd = 174, |
| ACC128 = 175, |
| ACC64 = 176, |
| ACC64DSP = 177, |
| AFGR64 = 178, |
| CCR = 179, |
| COP0 = 180, |
| COP2 = 181, |
| COP3 = 182, |
| CPU16Regs = 183, |
| CPU16RegsPlusSP = 184, |
| CPURAReg = 185, |
| CPUSPReg = 186, |
| DSPCC = 187, |
| DSPR = 188, |
| FCC = 189, |
| FGR32 = 190, |
| FGR64 = 191, |
| FGRCC = 192, |
| GP32 = 193, |
| GP64 = 194, |
| GPR32 = 195, |
| GPR32NONZERO = 196, |
| GPR32ZERO = 197, |
| GPR64 = 198, |
| GPRMM16 = 199, |
| GPRMM16MoveP = 200, |
| GPRMM16MovePPairFirst = 201, |
| GPRMM16MovePPairSecond = 202, |
| GPRMM16Zero = 203, |
| HI32 = 204, |
| HI32DSP = 205, |
| HI64 = 206, |
| HWRegs = 207, |
| LO32 = 208, |
| LO32DSP = 209, |
| LO64 = 210, |
| MSA128B = 211, |
| MSA128D = 212, |
| MSA128F16 = 213, |
| MSA128H = 214, |
| MSA128W = 215, |
| MSA128WEvens = 216, |
| MSACtrl = 217, |
| OCTEON_MPL = 218, |
| OCTEON_P = 219, |
| SP32 = 220, |
| SP64 = 221, |
| OPERAND_TYPE_LIST_END |
| }; |
| } // end namespace OpTypes |
| } // end namespace Mips |
| } // end namespace llvm |
| #endif // GET_INSTRINFO_OPERAND_TYPES_ENUM |
| |
| #ifdef GET_INSTRINFO_OPERAND_TYPE |
| #undef GET_INSTRINFO_OPERAND_TYPE |
| namespace llvm { |
| namespace Mips { |
| LLVM_READONLY |
| static int getOperandType(uint16_t Opcode, uint16_t OpIdx) { |
| const int Offsets[] = { |
| 0, |
| 1, |
| 1, |
| 1, |
| 2, |
| 3, |
| 4, |
| 5, |
| 5, |
| 8, |
| 12, |
| 13, |
| 17, |
| 20, |
| 20, |
| 21, |
| 23, |
| 25, |
| 25, |
| 26, |
| 27, |
| 29, |
| 29, |
| 35, |
| 36, |
| 36, |
| 38, |
| 39, |
| 39, |
| 39, |
| 39, |
| 39, |
| 39, |
| 41, |
| 44, |
| 44, |
| 47, |
| 50, |
| 53, |
| 56, |
| 59, |
| 62, |
| 65, |
| 68, |
| 71, |
| 74, |
| 75, |
| 76, |
| 78, |
| 80, |
| 83, |
| 85, |
| 89, |
| 91, |
| 93, |
| 95, |
| 97, |
| 99, |
| 101, |
| 103, |
| 105, |
| 107, |
| 108, |
| 110, |
| 112, |
| 114, |
| 119, |
| 124, |
| 129, |
| 131, |
| 136, |
| 141, |
| 145, |
| 148, |
| 151, |
| 154, |
| 157, |
| 160, |
| 163, |
| 166, |
| 169, |
| 172, |
| 175, |
| 178, |
| 181, |
| 184, |
| 186, |
| 188, |
| 189, |
| 190, |
| 191, |
| 193, |
| 195, |
| 197, |
| 199, |
| 200, |
| 203, |
| 205, |
| 208, |
| 210, |
| 213, |
| 216, |
| 219, |
| 223, |
| 227, |
| 231, |
| 235, |
| 240, |
| 244, |
| 249, |
| 253, |
| 258, |
| 262, |
| 267, |
| 271, |
| 275, |
| 278, |
| 281, |
| 284, |
| 287, |
| 290, |
| 294, |
| 298, |
| 301, |
| 304, |
| 307, |
| 309, |
| 311, |
| 313, |
| 315, |
| 317, |
| 319, |
| 321, |
| 323, |
| 325, |
| 327, |
| 329, |
| 331, |
| 333, |
| 336, |
| 338, |
| 341, |
| 344, |
| 347, |
| 350, |
| 353, |
| 356, |
| 359, |
| 362, |
| 365, |
| 368, |
| 371, |
| 374, |
| 375, |
| 378, |
| 382, |
| 385, |
| 389, |
| 391, |
| 393, |
| 395, |
| 397, |
| 399, |
| 401, |
| 403, |
| 405, |
| 407, |
| 409, |
| 411, |
| 413, |
| 415, |
| 417, |
| 419, |
| 421, |
| 423, |
| 426, |
| 428, |
| 430, |
| 432, |
| 434, |
| 436, |
| 439, |
| 442, |
| 445, |
| 449, |
| 456, |
| 460, |
| 464, |
| 468, |
| 472, |
| 476, |
| 483, |
| 486, |
| 492, |
| 495, |
| 498, |
| 501, |
| 504, |
| 507, |
| 513, |
| 516, |
| 522, |
| 525, |
| 528, |
| 531, |
| 534, |
| 537, |
| 543, |
| 546, |
| 552, |
| 555, |
| 558, |
| 561, |
| 564, |
| 567, |
| 573, |
| 576, |
| 582, |
| 585, |
| 588, |
| 591, |
| 594, |
| 597, |
| 603, |
| 606, |
| 612, |
| 615, |
| 618, |
| 621, |
| 624, |
| 627, |
| 633, |
| 636, |
| 642, |
| 645, |
| 648, |
| 651, |
| 654, |
| 657, |
| 663, |
| 666, |
| 672, |
| 675, |
| 678, |
| 681, |
| 684, |
| 687, |
| 693, |
| 696, |
| 702, |
| 705, |
| 708, |
| 711, |
| 714, |
| 717, |
| 723, |
| 726, |
| 732, |
| 735, |
| 738, |
| 741, |
| 744, |
| 747, |
| 753, |
| 756, |
| 762, |
| 765, |
| 768, |
| 771, |
| 774, |
| 777, |
| 783, |
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| 801, |
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| 888, |
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| 900, |
| 903, |
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| 915, |
| 918, |
| 919, |
| 923, |
| 927, |
| 931, |
| 935, |
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| 948, |
| 951, |
| 954, |
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| 978, |
| 981, |
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| 998, |
| 1001, |
| 1003, |
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| 1022, |
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| 1102, |
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| 1110, |
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| 1130, |
| 1131, |
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| 1141, |
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| 1147, |
| 1150, |
| 1153, |
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| 1160, |
| 1163, |
| 1167, |
| 1170, |
| 1173, |
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| 1180, |
| 1182, |
| 1184, |
| 1187, |
| 1190, |
| 1192, |
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| 1198, |
| 1200, |
| 1202, |
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| 1212, |
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| 1250, |
| 1252, |
| 1255, |
| 1258, |
| 1261, |
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| 1266, |
| 1268, |
| 1271, |
| 1271, |
| 1274, |
| 1277, |
| 1280, |
| 1283, |
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| 1289, |
| 1292, |
| 1295, |
| 1298, |
| 1301, |
| 1304, |
| 1307, |
| 1310, |
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| 1319, |
| 1321, |
| 1323, |
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| 1332, |
| 1335, |
| 1342, |
| 1349, |
| 1350, |
| 1351, |
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| 1354, |
| 1355, |
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| 1363, |
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| 1371, |
| 1375, |
| 1377, |
| 1379, |
| 1381, |
| 1383, |
| 1385, |
| 1387, |
| 1391, |
| 1395, |
| 1399, |
| 1403, |
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| 1409, |
| 1412, |
| 1415, |
| 1418, |
| 1421, |
| 1424, |
| 1427, |
| 1431, |
| 1435, |
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| 1440, |
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| 1460, |
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| 1480, |
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| 1492, |
| 1496, |
| 1500, |
| 1503, |
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| 1515, |
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| 1521, |
| 1524, |
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| 1527, |
| 1530, |
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| 1581, |
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| 1597, |
| 1600, |
| 1603, |
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| 1609, |
| 1612, |
| 1615, |
| 1617, |
| 1619, |
| 1621, |
| 1623, |
| 1625, |
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| 1635, |
| 1639, |
| 1644, |
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| 1654, |
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| 1679, |
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| 1702, |
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| 1727, |
| 1727, |
| 1727, |
| 1730, |
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| 1736, |
| 1739, |
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| 1760, |
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| 1768, |
| 1770, |
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| 1781, |
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| 1802, |
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| 1835, |
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| 1850, |
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| 1859, |
| 1862, |
| 1865, |
| 1868, |
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| 2592, |
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| 2601, |
| 2604, |
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| 2636, |
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| 2637, |
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| 2643, |
| 2646, |
| 2649, |
| 2652, |
| 2655, |
| 2658, |
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| 2664, |
| 2666, |
| 2668, |
| 2670, |
| 2672, |
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| 2680, |
| 2683, |
| 2686, |
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| 2692, |
| 2695, |
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| 2992, |
| 2995, |
| 2998, |
| 3001, |
| 3004, |
| 3007, |
| 3010, |
| 3013, |
| 3016, |
| 3019, |
| 3022, |
| 3025, |
| 3028, |
| 3031, |
| 3034, |
| 3037, |
| 3040, |
| 3043, |
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| 3049, |
| 3052, |
| 3055, |
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| 3061, |
| 3064, |
| 3067, |
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| 3082, |
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| 3088, |
| 3091, |
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| 3097, |
| 3100, |
| 3103, |
| 3106, |
| 3109, |
| 3112, |
| 3115, |
| 3118, |
| 3121, |
| 3124, |
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| 6382, |
| 6384, |
| 6386, |
| 6388, |
| 6390, |
| 6390, |
| 6390, |
| 6392, |
| 6394, |
| 6397, |
| 6400, |
| 6403, |
| 6406, |
| 6409, |
| 6412, |
| 6415, |
| 6418, |
| 6421, |
| 6424, |
| 6427, |
| 6430, |
| 6433, |
| 6436, |
| 6439, |
| 6442, |
| 6446, |
| 6450, |
| 6454, |
| 6458, |
| 6462, |
| 6466, |
| 6470, |
| 6474, |
| 6478, |
| 6482, |
| 6485, |
| 6486, |
| 6487, |
| 6488, |
| 6489, |
| 6490, |
| 6491, |
| 6494, |
| 6497, |
| 6500, |
| 6503, |
| 6506, |
| 6509, |
| 6512, |
| 6515, |
| 6517, |
| 6519, |
| 6522, |
| 6525, |
| 6528, |
| 6531, |
| 6533, |
| 6535, |
| 6537, |
| 6539, |
| 6541, |
| 6543, |
| 6546, |
| 6549, |
| 6552, |
| 6555, |
| 6558, |
| 6561, |
| 6564, |
| 6567, |
| 6570, |
| 6573, |
| 6576, |
| 6579, |
| 6582, |
| 6585, |
| 6589, |
| 6593, |
| 6597, |
| 6601, |
| 6604, |
| 6607, |
| 6610, |
| 6613, |
| 6616, |
| 6619, |
| 6622, |
| 6625, |
| 6628, |
| 6631, |
| 6634, |
| 6637, |
| 6640, |
| 6643, |
| 6646, |
| 6649, |
| 6652, |
| 6655, |
| 6658, |
| 6661, |
| 6664, |
| 6667, |
| 6670, |
| 6673, |
| 6676, |
| 6679, |
| 6682, |
| 6685, |
| 6688, |
| 6691, |
| 6694, |
| 6697, |
| 6700, |
| 6703, |
| 6706, |
| 6709, |
| 6712, |
| 6715, |
| 6718, |
| 6721, |
| 6724, |
| 6727, |
| 6730, |
| 6733, |
| 6736, |
| 6739, |
| 6742, |
| 6745, |
| 6748, |
| 6751, |
| 6754, |
| 6757, |
| 6760, |
| 6763, |
| 6766, |
| 6769, |
| 6772, |
| 6775, |
| 6778, |
| 6781, |
| 6784, |
| 6785, |
| 6786, |
| 6790, |
| 6794, |
| 6798, |
| 6802, |
| 6806, |
| 6810, |
| 6814, |
| 6818, |
| 6821, |
| 6824, |
| 6827, |
| 6829, |
| 6831, |
| 6834, |
| 6837, |
| 6840, |
| 6843, |
| 6846, |
| 6849, |
| 6852, |
| 6855, |
| 6858, |
| 6861, |
| 6864, |
| 6867, |
| 6870, |
| 6873, |
| 6876, |
| 6879, |
| 6882, |
| 6885, |
| 6888, |
| 6891, |
| 6894, |
| 6897, |
| 6900, |
| 6903, |
| 6906, |
| 6909, |
| 6912, |
| 6915, |
| 6918, |
| 6921, |
| 6924, |
| 6927, |
| 6930, |
| 6933, |
| 6936, |
| 6939, |
| 6942, |
| 6945, |
| 6948, |
| 6951, |
| 6954, |
| 6957, |
| 6960, |
| 6963, |
| 6966, |
| 6969, |
| 6972, |
| 6975, |
| 6978, |
| 6981, |
| 6984, |
| 6987, |
| 6990, |
| 6993, |
| 6996, |
| 6999, |
| 7002, |
| 7005, |
| 7008, |
| 7011, |
| 7014, |
| 7017, |
| 7020, |
| 7023, |
| 7026, |
| 7029, |
| 7032, |
| 7035, |
| 7038, |
| 7041, |
| 7044, |
| 7047, |
| 7050, |
| 7053, |
| 7056, |
| 7059, |
| 7059, |
| 7059, |
| 7059, |
| 7062, |
| 7065, |
| 7068, |
| 7071, |
| 7074, |
| 7077, |
| 7080, |
| 7083, |
| 7086, |
| 7089, |
| 7092, |
| 7095, |
| 7098, |
| 7101, |
| 7104, |
| 7107, |
| 7110, |
| 7113, |
| 7116, |
| 7119, |
| 7122, |
| 7125, |
| 7128, |
| 7131, |
| 7134, |
| 7137, |
| 7140, |
| 7143, |
| 7146, |
| 7149, |
| 7152, |
| 7155, |
| 7158, |
| 7161, |
| 7164, |
| 7167, |
| 7170, |
| 7173, |
| 7176, |
| 7179, |
| 7182, |
| 7185, |
| 7188, |
| 7191, |
| 7194, |
| 7197, |
| 7200, |
| 7203, |
| 7206, |
| 7209, |
| 7212, |
| 7215, |
| 7218, |
| 7221, |
| 7224, |
| 7227, |
| 7230, |
| 7233, |
| 7236, |
| 7239, |
| 7242, |
| 7245, |
| 7248, |
| 7251, |
| 7254, |
| 7257, |
| 7260, |
| 7263, |
| 7266, |
| 7269, |
| 7272, |
| 7275, |
| 7278, |
| 7281, |
| 7284, |
| 7287, |
| 7290, |
| 7293, |
| 7296, |
| 7299, |
| 7302, |
| 7305, |
| 7308, |
| 7311, |
| 7314, |
| 7317, |
| 7320, |
| 7324, |
| 7327, |
| 7330, |
| 7333, |
| 7336, |
| 7339, |
| 7342, |
| 7345, |
| 7348, |
| 7351, |
| 7354, |
| 7357, |
| 7358, |
| 7360, |
| 7362, |
| 7364, |
| 7365, |
| 7366, |
| 7367, |
| 7368, |
| 7368, |
| 7368, |
| 7371, |
| 7373, |
| 7375, |
| 7378, |
| 7381, |
| 7384, |
| 7386, |
| 7388, |
| 7390, |
| 7392, |
| 7394, |
| 7396, |
| 7399, |
| 7402, |
| 7405, |
| 7408, |
| 7411, |
| 7414, |
| 7417, |
| 7420, |
| 7422, |
| 7424, |
| 7427, |
| 7430, |
| 7432, |
| 7434, |
| 7436, |
| 7438, |
| 7441, |
| 7444, |
| 7447, |
| 7447, |
| 7447, |
| 7447, |
| 7447, |
| 7447, |
| 7447, |
| 7447, |
| 7447, |
| 7447, |
| 7447, |
| 7447, |
| 7447, |
| 7447, |
| 7447, |
| 7447, |
| 7447, |
| 7447, |
| 7447, |
| 7447, |
| 7447, |
| 7447, |
| 7447, |
| 7447, |
| 7447, |
| 7450, |
| 7452, |
| 7454, |
| 7456, |
| 7459, |
| 7462, |
| 7465, |
| 7468, |
| 7470, |
| 7472, |
| 7475, |
| 7477, |
| 7479, |
| 7481, |
| 7483, |
| 7485, |
| 7487, |
| 7489, |
| 7491, |
| 7493, |
| 7495, |
| 7497, |
| 7499, |
| 7501, |
| 7503, |
| 7506, |
| 7509, |
| 7512, |
| 7516, |
| 7520, |
| 7524, |
| 7528, |
| 7528, |
| 7529, |
| 7530, |
| 7532, |
| 7534, |
| 7536, |
| 7538, |
| 7540, |
| 7542, |
| 7545, |
| 7548, |
| 7551, |
| 7554, |
| 7557, |
| 7560, |
| 7563, |
| 7566, |
| 7569, |
| 7572, |
| 7575, |
| 7578, |
| 7581, |
| }; |
| const int OpcodeOperandTypes[] = { |
| -1, |
| /**/ |
| /**/ |
| OpTypes::i32imm, |
| OpTypes::i32imm, |
| OpTypes::i32imm, |
| OpTypes::i32imm, |
| /**/ |
| -1, -1, OpTypes::i32imm, |
| -1, -1, -1, OpTypes::i32imm, |
| -1, |
| -1, -1, -1, OpTypes::i32imm, |
| -1, -1, OpTypes::i32imm, |
| /**/ |
| -1, |
| -1, -1, |
| -1, -1, |
| /**/ |
| OpTypes::i32imm, |
| OpTypes::i32imm, |
| OpTypes::i64imm, OpTypes::i32imm, |
| /**/ |
| -1, OpTypes::i64imm, OpTypes::i32imm, -1, OpTypes::i32imm, OpTypes::i32imm, |
| -1, |
| /**/ |
| -1, OpTypes::i32imm, |
| -1, |
| /**/ |
| /**/ |
| /**/ |
| /**/ |
| /**/ |
| -1, -1, |
| -1, -1, -1, |
| /**/ |
| OpTypes::type0, OpTypes::type0, OpTypes::type0, |
| OpTypes::type0, OpTypes::type0, OpTypes::type0, |
| OpTypes::type0, OpTypes::type0, OpTypes::type0, |
| OpTypes::type0, OpTypes::type0, OpTypes::type0, |
| OpTypes::type0, OpTypes::type0, OpTypes::type0, |
| OpTypes::type0, OpTypes::type0, OpTypes::type0, |
| OpTypes::type0, OpTypes::type0, OpTypes::type0, |
| OpTypes::type0, OpTypes::type0, OpTypes::type0, |
| OpTypes::type0, OpTypes::type0, OpTypes::type0, |
| OpTypes::type0, OpTypes::type0, OpTypes::type0, |
| OpTypes::type0, |
| OpTypes::type0, |
| OpTypes::type0, -1, |
| OpTypes::type0, -1, |
| OpTypes::type0, OpTypes::type1, -1, |
| OpTypes::type0, OpTypes::type1, |
| OpTypes::type0, OpTypes::type0, OpTypes::type1, -1, |
| OpTypes::type0, OpTypes::type1, |
| OpTypes::type0, OpTypes::type1, |
| OpTypes::type0, OpTypes::type1, |
| OpTypes::type0, OpTypes::type1, |
| OpTypes::type0, OpTypes::type1, |
| OpTypes::type0, OpTypes::type1, |
| OpTypes::type0, OpTypes::type1, |
| OpTypes::type0, OpTypes::type0, |
| OpTypes::type0, OpTypes::type0, |
| OpTypes::type0, |
| OpTypes::type0, OpTypes::ptype1, |
| OpTypes::type0, OpTypes::ptype1, |
| OpTypes::type0, OpTypes::ptype1, |
| OpTypes::type0, OpTypes::ptype1, OpTypes::ptype1, OpTypes::type2, -1, |
| OpTypes::type0, OpTypes::ptype1, OpTypes::ptype1, OpTypes::type2, -1, |
| OpTypes::type0, OpTypes::ptype1, OpTypes::ptype1, OpTypes::type2, -1, |
| OpTypes::type0, OpTypes::ptype1, |
| OpTypes::ptype0, OpTypes::type1, OpTypes::ptype0, OpTypes::ptype2, -1, |
| OpTypes::type0, OpTypes::type1, OpTypes::type2, OpTypes::type0, OpTypes::type0, |
| OpTypes::type0, OpTypes::ptype1, OpTypes::type0, OpTypes::type0, |
| OpTypes::type0, OpTypes::ptype1, OpTypes::type0, |
| OpTypes::type0, OpTypes::ptype1, OpTypes::type0, |
| OpTypes::type0, OpTypes::ptype1, OpTypes::type0, |
| OpTypes::type0, OpTypes::ptype1, OpTypes::type0, |
| OpTypes::type0, OpTypes::ptype1, OpTypes::type0, |
| OpTypes::type0, OpTypes::ptype1, OpTypes::type0, |
| OpTypes::type0, OpTypes::ptype1, OpTypes::type0, |
| OpTypes::type0, OpTypes::ptype1, OpTypes::type0, |
| OpTypes::type0, OpTypes::ptype1, OpTypes::type0, |
| OpTypes::type0, OpTypes::ptype1, OpTypes::type0, |
| OpTypes::type0, OpTypes::ptype1, OpTypes::type0, |
| OpTypes::type0, OpTypes::ptype1, OpTypes::type0, |
| OpTypes::type0, OpTypes::ptype1, OpTypes::type0, |
| OpTypes::i32imm, OpTypes::i32imm, |
| OpTypes::type0, -1, |
| OpTypes::type0, |
| -1, |
| -1, |
| OpTypes::type0, OpTypes::type1, |
| OpTypes::type0, OpTypes::type1, |
| OpTypes::type0, -1, |
| OpTypes::type0, -1, |
| OpTypes::type0, |
| OpTypes::type0, OpTypes::type1, -1, |
| OpTypes::type0, OpTypes::type1, |
| OpTypes::type0, OpTypes::type0, OpTypes::untyped_imm_0, |
| OpTypes::type0, OpTypes::type1, |
| OpTypes::type0, OpTypes::type0, OpTypes::type1, |
| OpTypes::type0, OpTypes::type0, OpTypes::type1, |
| OpTypes::type0, OpTypes::type0, OpTypes::type1, |
| OpTypes::type0, -1, OpTypes::type1, OpTypes::type1, |
| OpTypes::type0, -1, OpTypes::type1, OpTypes::type1, |
| OpTypes::type0, OpTypes::type1, OpTypes::type0, OpTypes::type0, |
| OpTypes::type0, OpTypes::type1, OpTypes::type0, OpTypes::type0, |
| OpTypes::type0, OpTypes::type1, OpTypes::type0, OpTypes::type0, OpTypes::type1, |
| OpTypes::type0, OpTypes::type1, OpTypes::type0, OpTypes::type0, |
| OpTypes::type0, OpTypes::type1, OpTypes::type0, OpTypes::type0, OpTypes::type1, |
| OpTypes::type0, OpTypes::type1, OpTypes::type0, OpTypes::type0, |
| OpTypes::type0, OpTypes::type1, OpTypes::type0, OpTypes::type0, OpTypes::type1, |
| OpTypes::type0, OpTypes::type1, OpTypes::type0, OpTypes::type0, |
| OpTypes::type0, OpTypes::type1, OpTypes::type0, OpTypes::type0, OpTypes::type1, |
| OpTypes::type0, OpTypes::type1, OpTypes::type0, OpTypes::type0, |
| OpTypes::type0, OpTypes::type1, OpTypes::type0, OpTypes::type0, |
| OpTypes::type0, OpTypes::type0, OpTypes::type0, |
| OpTypes::type0, OpTypes::type0, OpTypes::type0, |
| OpTypes::type0, OpTypes::type0, OpTypes::type0, |
| OpTypes::type0, OpTypes::type0, OpTypes::type0, |
| OpTypes::type0, OpTypes::type0, OpTypes::type0, |
| OpTypes::type0, OpTypes::type0, OpTypes::type0, OpTypes::type0, |
| OpTypes::type0, OpTypes::type0, OpTypes::type0, OpTypes::type0, |
| OpTypes::type0, OpTypes::type0, OpTypes::type0, |
| OpTypes::type0, OpTypes::type0, OpTypes::type0, |
| OpTypes::type0, OpTypes::type0, OpTypes::type0, |
| OpTypes::type0, OpTypes::type0, |
| OpTypes::type0, OpTypes::type0, |
| OpTypes::type0, OpTypes::type0, |
| OpTypes::type0, OpTypes::type0, |
| OpTypes::type0, OpTypes::type0, |
| OpTypes::type0, OpTypes::type0, |
| OpTypes::type0, OpTypes::type1, |
| OpTypes::type0, OpTypes::type1, |
| OpTypes::type0, OpTypes::type1, |
| OpTypes::type0, OpTypes::type1, |
| OpTypes::type0, OpTypes::type1, |
| OpTypes::type0, OpTypes::type1, |
| OpTypes::type0, OpTypes::type0, |
| OpTypes::type0, OpTypes::type0, OpTypes::type1, |
| OpTypes::type0, OpTypes::type0, |
| OpTypes::type0, OpTypes::type0, OpTypes::type0, |
| OpTypes::type0, OpTypes::type0, OpTypes::type0, |
| OpTypes::type0, OpTypes::type0, OpTypes::type0, |
| OpTypes::type0, OpTypes::type0, OpTypes::type0, |
| OpTypes::type0, OpTypes::type0, OpTypes::type0, |
| OpTypes::type0, OpTypes::type0, OpTypes::type0, |
| OpTypes::type0, OpTypes::type0, OpTypes::type1, |
| OpTypes::type0, OpTypes::type0, -1, |
| OpTypes::type0, OpTypes::type0, OpTypes::type0, |
| OpTypes::type0, OpTypes::type0, OpTypes::type0, |
| OpTypes::type0, OpTypes::type0, OpTypes::type0, |
| OpTypes::type0, OpTypes::type0, OpTypes::type0, |
| -1, |
| OpTypes::ptype0, -1, OpTypes::type1, |
| OpTypes::type0, OpTypes::type0, OpTypes::type1, OpTypes::type2, |
| OpTypes::type0, OpTypes::type1, OpTypes::type2, |
| OpTypes::type0, OpTypes::type1, OpTypes::type1, -1, |
| OpTypes::type0, OpTypes::type1, |
| OpTypes::type0, OpTypes::type1, |
| OpTypes::type0, OpTypes::type1, |
| OpTypes::type0, OpTypes::type1, |
| OpTypes::type0, OpTypes::type1, |
| OpTypes::type0, OpTypes::type0, |
| OpTypes::type0, OpTypes::type0, |
| OpTypes::type0, OpTypes::type0, |
| OpTypes::type0, OpTypes::type0, |
| OpTypes::type0, OpTypes::type0, |
| OpTypes::type0, OpTypes::type0, |
| OpTypes::type0, OpTypes::type0, |
| OpTypes::type0, OpTypes::type0, |
| OpTypes::type0, OpTypes::type0, |
| OpTypes::type0, OpTypes::type1, |
| OpTypes::type0, -1, |
| OpTypes::type0, -1, |
| OpTypes::ptype0, OpTypes::type1, OpTypes::i32imm, |
| OpTypes::type0, -1, |
| -1, OpTypes::type0, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::i32imm, OpTypes::i32imm, |
| OpTypes::i32imm, OpTypes::i32imm, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::GPR32, -1, OpTypes::GPR32, OpTypes::GPR32, |
| OpTypes::GPR32, -1, OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, |
| OpTypes::GPR32, -1, OpTypes::GPR32, OpTypes::GPR32, |
| OpTypes::GPR32, -1, OpTypes::GPR32, OpTypes::GPR32, |
| OpTypes::GPR64, -1, OpTypes::GPR64, OpTypes::GPR64, |
| OpTypes::GPR64, -1, OpTypes::GPR64, OpTypes::GPR64, |
| OpTypes::GPR32, -1, OpTypes::GPR32, OpTypes::GPR32, |
| OpTypes::GPR32, -1, OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, |
| OpTypes::GPR32, -1, OpTypes::GPR32, |
| OpTypes::GPR32, -1, OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, |
| OpTypes::GPR32, -1, OpTypes::GPR32, |
| OpTypes::GPR32, -1, OpTypes::GPR32, |
| OpTypes::GPR64, -1, OpTypes::GPR64, |
| OpTypes::GPR64, -1, OpTypes::GPR64, |
| OpTypes::GPR32, -1, OpTypes::GPR32, |
| OpTypes::GPR32, -1, OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, |
| OpTypes::GPR32, -1, OpTypes::GPR32, |
| OpTypes::GPR32, -1, OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, |
| OpTypes::GPR32, -1, OpTypes::GPR32, |
| OpTypes::GPR32, -1, OpTypes::GPR32, |
| OpTypes::GPR64, -1, OpTypes::GPR64, |
| OpTypes::GPR64, -1, OpTypes::GPR64, |
| OpTypes::GPR32, -1, OpTypes::GPR32, |
| OpTypes::GPR32, -1, OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, |
| OpTypes::GPR32, -1, OpTypes::GPR32, |
| OpTypes::GPR32, -1, OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, |
| OpTypes::GPR32, -1, OpTypes::GPR32, |
| OpTypes::GPR32, -1, OpTypes::GPR32, |
| OpTypes::GPR64, -1, OpTypes::GPR64, |
| OpTypes::GPR64, -1, OpTypes::GPR64, |
| OpTypes::GPR32, -1, OpTypes::GPR32, |
| OpTypes::GPR32, -1, OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, |
| OpTypes::GPR32, -1, OpTypes::GPR32, |
| OpTypes::GPR32, -1, OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, |
| OpTypes::GPR32, -1, OpTypes::GPR32, |
| OpTypes::GPR32, -1, OpTypes::GPR32, |
| OpTypes::GPR64, -1, OpTypes::GPR64, |
| OpTypes::GPR64, -1, OpTypes::GPR64, |
| OpTypes::GPR32, -1, OpTypes::GPR32, |
| OpTypes::GPR32, -1, OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, |
| OpTypes::GPR32, -1, OpTypes::GPR32, |
| OpTypes::GPR32, -1, OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, |
| OpTypes::GPR32, -1, OpTypes::GPR32, |
| OpTypes::GPR32, -1, OpTypes::GPR32, |
| OpTypes::GPR64, -1, OpTypes::GPR64, |
| OpTypes::GPR64, -1, OpTypes::GPR64, |
| OpTypes::GPR32, -1, OpTypes::GPR32, |
| OpTypes::GPR32, -1, OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, |
| OpTypes::GPR32, -1, OpTypes::GPR32, |
| OpTypes::GPR32, -1, OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, |
| OpTypes::GPR32, -1, OpTypes::GPR32, |
| OpTypes::GPR32, -1, OpTypes::GPR32, |
| OpTypes::GPR64, -1, OpTypes::GPR64, |
| OpTypes::GPR64, -1, OpTypes::GPR64, |
| OpTypes::GPR32, -1, OpTypes::GPR32, |
| OpTypes::GPR32, -1, OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, |
| OpTypes::GPR32, -1, OpTypes::GPR32, |
| OpTypes::GPR32, -1, OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, |
| OpTypes::GPR32, -1, OpTypes::GPR32, |
| OpTypes::GPR32, -1, OpTypes::GPR32, |
| OpTypes::GPR64, -1, OpTypes::GPR64, |
| OpTypes::GPR64, -1, OpTypes::GPR64, |
| OpTypes::GPR32, -1, OpTypes::GPR32, |
| OpTypes::GPR32, -1, OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, |
| OpTypes::GPR32, -1, OpTypes::GPR32, |
| OpTypes::GPR32, -1, OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, |
| OpTypes::GPR32, -1, OpTypes::GPR32, |
| OpTypes::GPR32, -1, OpTypes::GPR32, |
| OpTypes::GPR64, -1, OpTypes::GPR64, |
| OpTypes::GPR64, -1, OpTypes::GPR64, |
| OpTypes::GPR32, -1, OpTypes::GPR32, |
| OpTypes::GPR32, -1, OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, |
| OpTypes::GPR32, -1, OpTypes::GPR32, |
| OpTypes::GPR32, -1, OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, |
| OpTypes::GPR32, -1, OpTypes::GPR32, |
| OpTypes::GPR32, -1, OpTypes::GPR32, |
| OpTypes::GPR64, -1, OpTypes::GPR64, |
| OpTypes::GPR64, -1, OpTypes::GPR64, |
| OpTypes::GPR32, -1, OpTypes::GPR32, |
| OpTypes::GPR32, -1, OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, |
| OpTypes::GPR32, -1, OpTypes::GPR32, |
| OpTypes::GPR32, -1, OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, |
| OpTypes::GPR32, -1, OpTypes::GPR32, |
| OpTypes::GPR32, -1, OpTypes::GPR32, |
| OpTypes::GPR64, -1, OpTypes::GPR64, |
| OpTypes::GPR64, -1, OpTypes::GPR64, |
| OpTypes::GPR32, -1, OpTypes::GPR32, |
| OpTypes::GPR32, -1, OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, |
| OpTypes::GPR32, -1, OpTypes::GPR32, |
| OpTypes::GPR32, -1, OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, |
| OpTypes::GPR32, -1, OpTypes::GPR32, |
| OpTypes::GPR32, -1, OpTypes::GPR32, |
| OpTypes::GPR64, -1, OpTypes::GPR64, |
| OpTypes::GPR64, -1, OpTypes::GPR64, |
| OpTypes::GPR32, -1, OpTypes::GPR32, |
| OpTypes::GPR32, -1, OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, OpTypes::GPR32, |
| OpTypes::brtarget, |
| OpTypes::brtarget, |
| OpTypes::brtarget_mm, |
| OpTypes::GPR32Opnd, OpTypes::imm64, OpTypes::brtarget, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::brtarget, |
| OpTypes::GPR32Opnd, OpTypes::imm64, OpTypes::brtarget, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::brtarget, |
| OpTypes::GPR32Opnd, OpTypes::imm64, OpTypes::brtarget, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::brtarget, |
| OpTypes::GPR32Opnd, OpTypes::imm64, OpTypes::brtarget, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::brtarget, |
| OpTypes::GPR32Opnd, OpTypes::imm64, OpTypes::brtarget, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::brtarget, |
| OpTypes::GPR32Opnd, OpTypes::imm64, OpTypes::brtarget, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::brtarget, |
| OpTypes::GPR32Opnd, OpTypes::imm64, OpTypes::brtarget, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::brtarget, |
| OpTypes::GPR32Opnd, OpTypes::imm64, OpTypes::brtarget, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::brtarget, |
| OpTypes::GPR32Opnd, OpTypes::imm64, OpTypes::brtarget, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::brtarget, |
| OpTypes::GPR32Opnd, OpTypes::imm64, OpTypes::brtarget, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::brtarget, |
| OpTypes::GPR32Opnd, OpTypes::imm64, OpTypes::brtarget, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::brtarget, |
| OpTypes::GPR32Opnd, OpTypes::imm64, OpTypes::brtarget, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::brtarget, |
| OpTypes::GPR32Opnd, OpTypes::imm64, OpTypes::brtarget, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::brtarget, |
| OpTypes::GPR32Opnd, OpTypes::imm64, OpTypes::brtarget, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::brtarget, |
| OpTypes::GPR32Opnd, OpTypes::imm64, OpTypes::brtarget, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::brtarget, |
| OpTypes::GPR32Opnd, OpTypes::imm64, OpTypes::brtarget, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::brtarget, |
| OpTypes::GPR32Opnd, OpTypes::imm64, OpTypes::brtarget, |
| OpTypes::GPR32Opnd, OpTypes::imm64, OpTypes::brtarget, |
| OpTypes::GPR32Opnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::brtarget, |
| OpTypes::brtarget_mm, |
| OpTypes::brtarget_mm, |
| OpTypes::GPR32Opnd, OpTypes::imm64, OpTypes::brtarget, |
| OpTypes::GPR32Opnd, OpTypes::imm64, OpTypes::brtarget, |
| OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::brtarget, |
| OpTypes::CPU16Regs, OpTypes::simm16, OpTypes::brtarget, |
| OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::brtarget, |
| OpTypes::CPU16Regs, OpTypes::simm16, OpTypes::brtarget, |
| OpTypes::CPU16Regs, OpTypes::simm16, OpTypes::brtarget, |
| OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::brtarget, |
| OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::brtarget, |
| OpTypes::CPU16Regs, OpTypes::simm16, OpTypes::brtarget, |
| OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::brtarget, |
| OpTypes::CPU16Regs, OpTypes::simm16, OpTypes::brtarget, |
| OpTypes::CPU16Regs, OpTypes::simm16, OpTypes::brtarget, |
| OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::brtarget, |
| OpTypes::AFGR64Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::FGR64Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::FGRCCOpnd, |
| OpTypes::cpinst_operand, OpTypes::cpinst_operand, OpTypes::i32imm, |
| OpTypes::FGR64, OpTypes::MSA128D, OpTypes::uimm1_ptr, |
| OpTypes::FGR32, OpTypes::MSA128W, OpTypes::uimm2_ptr, |
| OpTypes::FGRCCOpnd, OpTypes::GPR32Opnd, |
| OpTypes::simm32, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::simm32_relaxed, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::simm16, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::simm16, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::imm64, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::simm32_relaxed, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::imm64, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::simm32_relaxed, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, |
| /**/ |
| OpTypes::GPR32Opnd, OpTypes::AFGR64Opnd, OpTypes::i32imm, |
| OpTypes::GPR32Opnd, OpTypes::FGR64Opnd, OpTypes::i32imm, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::MSA128D, OpTypes::MSA128D, |
| OpTypes::MSA128W, OpTypes::MSA128W, |
| OpTypes::MSA128D, OpTypes::FGR64, |
| OpTypes::MSA128W, OpTypes::FGR32, |
| OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::simm16, OpTypes::simm16, |
| OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::GPR64Opnd, OpTypes::GPR32Opnd, |
| OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::GPR32Opnd, OpTypes::GPR64Opnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::uimm1, OpTypes::FGR64Opnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::GPR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::GPR32Opnd, OpTypes::FGR64Opnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::uimm2, OpTypes::FGR32Opnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::GPR64Opnd, OpTypes::FGR32Opnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::GPR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::GPR64Opnd, OpTypes::GPR32Opnd, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::GPR64Opnd, OpTypes::GPR32Opnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR64Opnd, |
| OpTypes::GPR64Opnd, |
| OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, |
| OpTypes::calltarget, |
| OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, -1, OpTypes::simm16, |
| OpTypes::MSA128F16, -1, OpTypes::simm10, |
| OpTypes::ACC128, -1, OpTypes::simm16, |
| OpTypes::ACC64, -1, OpTypes::simm16, |
| OpTypes::ACC64DSPOpnd, -1, OpTypes::simm16, |
| OpTypes::DSPCC, -1, OpTypes::simm16, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::brtarget, OpTypes::brtarget, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::brtarget, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::brtarget, OpTypes::brtarget, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::brtarget, |
| OpTypes::GPR32Opnd, OpTypes::brtarget, OpTypes::brtarget, |
| OpTypes::GPR32Opnd, OpTypes::brtarget, |
| OpTypes::GPR64Opnd, OpTypes::brtarget, |
| OpTypes::reglist, -1, OpTypes::simm12, |
| OpTypes::GPR32Opnd, OpTypes::i32imm, |
| OpTypes::GPR64Opnd, OpTypes::imm64, |
| OpTypes::GPR32Opnd, -1, OpTypes::simm16, |
| OpTypes::GPR64Opnd, -1, OpTypes::simm16, |
| OpTypes::GPR32Opnd, OpTypes::uimm32_coerced, |
| OpTypes::GPR64Opnd, OpTypes::imm64, |
| OpTypes::StrictlyFGR64Opnd, OpTypes::imm64, |
| OpTypes::StrictlyAFGR64Opnd, OpTypes::imm64, |
| OpTypes::GPR32Opnd, OpTypes::imm64, |
| OpTypes::StrictlyFGR32Opnd, OpTypes::imm64, |
| OpTypes::GPR32Opnd, OpTypes::imm64, |
| OpTypes::CPU16Regs, OpTypes::simm32, OpTypes::simm32, |
| OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, |
| OpTypes::GPR32Opnd, OpTypes::COP0Opnd, OpTypes::uimm3, |
| OpTypes::GPR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm3, |
| OpTypes::GPR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, |
| OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, |
| OpTypes::GPR32, OpTypes::GPR32, |
| OpTypes::GPR64, OpTypes::GPR64, |
| OpTypes::FGR64Opnd, OpTypes::MSA128F16, |
| OpTypes::FGR32Opnd, OpTypes::MSA128F16, |
| OpTypes::MSA128F16, OpTypes::FGR64Opnd, |
| OpTypes::MSA128F16, OpTypes::FGR32Opnd, |
| OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, |
| OpTypes::COP0Opnd, OpTypes::GPR32Opnd, OpTypes::uimm3, |
| OpTypes::FGR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::FGR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, |
| OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::simm32_relaxed, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::CPU16Regs, OpTypes::CPU16Regs, |
| OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::CPU16Regs, |
| OpTypes::CPU16Regs, OpTypes::CPU16Regs, |
| OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::CPU16Regs, |
| /**/ |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::simm32_relaxed, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::imm64, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::DSPCC, OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::DSPCC, OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::DSPCC, OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::DSPCC, OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::DSPCC, OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::DSPCC, OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::AFGR64Opnd, OpTypes::GPR32Opnd, |
| OpTypes::FGR64Opnd, OpTypes::GPR64Opnd, |
| OpTypes::FGR64Opnd, OpTypes::GPR32Opnd, |
| OpTypes::FGR64Opnd, OpTypes::GPR64Opnd, |
| OpTypes::FGR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::ACC128, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, |
| OpTypes::ACC128, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, |
| OpTypes::ACC128, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, |
| OpTypes::ACC128, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::GPR32Opnd, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, |
| OpTypes::GPR32Opnd, |
| OpTypes::GPR64Opnd, |
| OpTypes::GPR64Opnd, |
| OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, |
| OpTypes::GPR64Opnd, |
| OpTypes::GPR64Opnd, |
| OpTypes::GPR32Opnd, |
| OpTypes::ACC64, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64, |
| OpTypes::ACC64, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64, |
| OpTypes::ACC64, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64, |
| OpTypes::ACC64, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64, |
| OpTypes::GPR32, OpTypes::ACC64, |
| OpTypes::GPR64, OpTypes::ACC128, |
| OpTypes::GPR32, OpTypes::ACC64, |
| OpTypes::GPR32, OpTypes::ACC64, |
| OpTypes::GPR64, OpTypes::ACC128, |
| OpTypes::GPR32, OpTypes::ACC64, |
| OpTypes::ACC64, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64, |
| OpTypes::ACC64, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64, |
| OpTypes::ACC64, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64, |
| OpTypes::ACC64, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64, |
| OpTypes::ACC64, OpTypes::GPR32, OpTypes::GPR32, |
| OpTypes::ACC128, OpTypes::GPR64, OpTypes::GPR64, |
| OpTypes::ACC64DSP, OpTypes::GPR32, OpTypes::GPR32, |
| OpTypes::ACC64, OpTypes::GPR32, OpTypes::GPR32, |
| OpTypes::ACC64, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::ACC64, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::ACC64, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::ACC64, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::DSPROpnd, OpTypes::DSPCC, OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::DSPROpnd, OpTypes::DSPCC, OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::GPR32Opnd, |
| OpTypes::GPR64Opnd, |
| OpTypes::ACC64, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::AFGR64Opnd, OpTypes::FCCRegsOpnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, |
| OpTypes::FGR64Opnd, OpTypes::FCCRegsOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::GPR32Opnd, OpTypes::FCCRegsOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR64Opnd, OpTypes::FCCRegsOpnd, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, |
| OpTypes::FGR32Opnd, OpTypes::FCCRegsOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::AFGR64Opnd, OpTypes::FCCRegsOpnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, |
| OpTypes::FGR64Opnd, OpTypes::FCCRegsOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::GPR32Opnd, OpTypes::FCCRegsOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR64Opnd, OpTypes::FCCRegsOpnd, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, |
| OpTypes::FGR32Opnd, OpTypes::FCCRegsOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::AFGR64Opnd, OpTypes::GPR32Opnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, |
| OpTypes::FGR64Opnd, OpTypes::GPR32Opnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR64Opnd, OpTypes::GPR32Opnd, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, |
| OpTypes::FGR32Opnd, OpTypes::GPR32Opnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FGR32Opnd, OpTypes::FGR64Opnd, OpTypes::GPR32Opnd, |
| OpTypes::FGR32Opnd, OpTypes::AFGR64Opnd, OpTypes::GPR32Opnd, |
| OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::ACC64, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::simm16, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::simm16, |
| /**/ |
| /**/ |
| OpTypes::AFGR64Opnd, -1, OpTypes::simm16, |
| OpTypes::ACC64, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, -1, OpTypes::simm16, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::simm32, |
| OpTypes::GPR32NonZeroOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::simm32_relaxed, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::simm32, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::imm64, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm32_coerced, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::imm64, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::simm32, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::imm64, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm32_coerced, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::imm64, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::imm64, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::imm64, |
| OpTypes::GPR32, OpTypes::MSA128B, |
| OpTypes::GPR32, OpTypes::MSA128D, |
| OpTypes::GPR32, OpTypes::MSA128H, |
| OpTypes::GPR32, OpTypes::MSA128B, |
| OpTypes::GPR32, OpTypes::MSA128W, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::simm32_relaxed, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::ACC128, -1, OpTypes::simm16, |
| OpTypes::ACC64, -1, OpTypes::simm16, |
| OpTypes::ACC64DSPOpnd, -1, OpTypes::simm16, |
| OpTypes::DSPCC, -1, OpTypes::simm16, |
| OpTypes::MSA128F16, -1, OpTypes::simm10, |
| OpTypes::reglist, -1, OpTypes::simm12, |
| OpTypes::GPR32, OpTypes::MSA128B, |
| OpTypes::GPR32, OpTypes::MSA128D, |
| OpTypes::GPR32, OpTypes::MSA128H, |
| OpTypes::GPR32, OpTypes::MSA128B, |
| OpTypes::GPR32, OpTypes::MSA128W, |
| OpTypes::GPR64Opnd, -1, OpTypes::simm16, |
| OpTypes::GPR64Opnd, -1, OpTypes::simm16, |
| OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::CPU16Regs, |
| OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::CPU16Regs, |
| OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::CPU16Regs, |
| OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::simm16, |
| OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::CPU16Regs, |
| OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::simm16, |
| OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::simm16, |
| OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::CPU16Regs, |
| OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::CPU16Regs, |
| OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::simm16, |
| OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::CPU16Regs, |
| OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::simm16, |
| OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::simm16, |
| OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::CPU16Regs, |
| OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::CPU16Regs, |
| OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::simm16, |
| OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::simm16, |
| OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::CPU16Regs, |
| OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::CPU16Regs, |
| OpTypes::calltarget, |
| OpTypes::GPR64Opnd, |
| OpTypes::GPR64Opnd, |
| OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, |
| OpTypes::GPR64Opnd, |
| OpTypes::GPR32Opnd, |
| OpTypes::GPR64Opnd, |
| OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, |
| OpTypes::calltarget, |
| OpTypes::calltarget, |
| /**/ |
| /**/ |
| OpTypes::ACC64, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::simm32, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::simm32_relaxed, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, -1, OpTypes::simm16, |
| OpTypes::GPR32Opnd, -1, OpTypes::simm16, |
| OpTypes::GPR32Opnd, -1, OpTypes::simm16, |
| OpTypes::GPR32Opnd, -1, OpTypes::simm16, |
| OpTypes::GPR32Opnd, -1, OpTypes::simm16, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::simm19_lsl2, |
| OpTypes::GPRMM16Opnd, OpTypes::simm23_lsl2, |
| OpTypes::GPR32Opnd, OpTypes::simm19_lsl2, |
| OpTypes::GPRMM16Opnd, OpTypes::uimm6_lsl2, |
| OpTypes::GPRMM16Opnd, OpTypes::GPRMM16Opnd, OpTypes::simm3_lsa2, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::simm4, |
| OpTypes::simm9_addiusp, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::simm16, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::GPRMM16Opnd, OpTypes::GPRMM16Opnd, OpTypes::GPRMM16Opnd, |
| OpTypes::GPRMM16Opnd, OpTypes::GPRMM16Opnd, OpTypes::GPRMM16Opnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::vsplat_uimm5, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::vsplat_uimm5, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::vsplat_uimm5, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::vsplat_uimm5, |
| OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::simm16_relaxed, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::simm16, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::simm16_relaxed, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::simm16, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm2, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm2, |
| OpTypes::GPR32Opnd, OpTypes::simm16, |
| OpTypes::GPR32Opnd, OpTypes::simm16, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPRMM16Opnd, OpTypes::GPRMM16Opnd, OpTypes::GPRMM16Opnd, |
| OpTypes::GPRMM16Opnd, OpTypes::GPRMM16Opnd, OpTypes::GPRMM16Opnd, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, |
| OpTypes::GPRMM16Opnd, OpTypes::GPRMM16Opnd, OpTypes::uimm4_andi, |
| OpTypes::GPRMM16Opnd, OpTypes::GPRMM16Opnd, OpTypes::uimm4_andi, |
| OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::vsplat_uimm8, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm16, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm16, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::uimm16_64, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm16, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm5, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm5, OpTypes::GPR32Opnd, |
| OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm16, |
| OpTypes::GPR32Opnd, OpTypes::simm16, |
| OpTypes::GPR32Opnd, OpTypes::simm16, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm16, |
| OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::CPU16Regs, OpTypes::simm16, |
| OpTypes::CPU16Regs, OpTypes::simm16, |
| OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::simm16, |
| OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::simm16, |
| OpTypes::CPU16Regs, OpTypes::CPU16RegsPlusSP, OpTypes::simm16, |
| OpTypes::simm16, |
| OpTypes::simm16, |
| OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::CPU16Regs, |
| OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::CPU16Regs, |
| OpTypes::brtarget10_mm, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, |
| OpTypes::brtarget, |
| OpTypes::brtarget26, |
| OpTypes::brtarget26_mm, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm2, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm2, OpTypes::GPR32Opnd, |
| OpTypes::GPR64Opnd, OpTypes::uimm5_64_report_uimm6, OpTypes::brtarget, |
| OpTypes::GPR64Opnd, OpTypes::uimm5_64, OpTypes::brtarget, |
| OpTypes::GPR64Opnd, OpTypes::uimm5_64_report_uimm6, OpTypes::brtarget, |
| OpTypes::GPR64Opnd, OpTypes::uimm5_64, OpTypes::brtarget, |
| OpTypes::brtarget26, |
| OpTypes::brtarget10_mm, |
| OpTypes::FGR64Opnd, OpTypes::brtarget, |
| OpTypes::FGR64Opnd, OpTypes::brtarget_mm, |
| OpTypes::FCCRegsOpnd, OpTypes::brtarget, |
| OpTypes::FCCRegsOpnd, OpTypes::brtarget, |
| OpTypes::FCCRegsOpnd, OpTypes::brtarget_mm, |
| OpTypes::FGR64Opnd, OpTypes::brtarget, |
| OpTypes::FGR64Opnd, OpTypes::brtarget_mm, |
| OpTypes::FCCRegsOpnd, OpTypes::brtarget, |
| OpTypes::FCCRegsOpnd, OpTypes::brtarget, |
| OpTypes::FCCRegsOpnd, OpTypes::brtarget_mm, |
| OpTypes::COP2Opnd, OpTypes::brtarget, |
| OpTypes::COP2Opnd, OpTypes::brtarget_mm, |
| OpTypes::COP2Opnd, OpTypes::brtarget, |
| OpTypes::COP2Opnd, OpTypes::brtarget_mm, |
| OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::vsplat_uimm3, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::vsplat_uimm6, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::vsplat_uimm4, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::vsplat_uimm5, |
| OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::brtarget26_mm, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::brtarget, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::brtarget, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::brtarget, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::brtarget, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::brtarget_lsl2_mm, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::brtarget, |
| OpTypes::GPRMM16Opnd, OpTypes::brtarget7_mm, |
| OpTypes::GPR32Opnd, OpTypes::brtarget, |
| OpTypes::GPR32Opnd, OpTypes::brtarget_mm, |
| OpTypes::GPR32Opnd, OpTypes::brtarget21, |
| OpTypes::GPRMM16Opnd, OpTypes::brtarget7_mm, |
| OpTypes::GPR64Opnd, OpTypes::brtarget21, |
| OpTypes::GPR32Opnd, OpTypes::brtarget_mm, |
| OpTypes::GPR32Opnd, OpTypes::brtarget21_mm, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::brtarget_mm, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::brtarget, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::brtarget, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::brtarget_lsl2_mm, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::brtarget, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::brtarget, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::brtarget_lsl2_mm, |
| OpTypes::GPR32Opnd, OpTypes::brtarget, |
| OpTypes::GPR64Opnd, OpTypes::brtarget, |
| OpTypes::GPR32Opnd, OpTypes::brtarget, |
| OpTypes::GPR32Opnd, OpTypes::brtarget, |
| OpTypes::GPR32Opnd, OpTypes::brtarget_mm, |
| OpTypes::GPR32Opnd, OpTypes::brtarget, |
| OpTypes::GPR32Opnd, OpTypes::brtarget_mm, |
| OpTypes::GPR32Opnd, OpTypes::brtarget_mm, |
| OpTypes::GPR32Opnd, OpTypes::brtarget, |
| OpTypes::GPR64Opnd, OpTypes::brtarget, |
| OpTypes::GPR32Opnd, OpTypes::brtarget_lsl2_mm, |
| OpTypes::GPR32Opnd, OpTypes::brtarget, |
| OpTypes::GPR32Opnd, OpTypes::brtarget_mm, |
| OpTypes::GPR32Opnd, OpTypes::brtarget, |
| OpTypes::GPR64Opnd, OpTypes::brtarget, |
| OpTypes::GPR32Opnd, OpTypes::brtarget, |
| OpTypes::GPR32Opnd, OpTypes::brtarget_mm, |
| OpTypes::GPR32Opnd, OpTypes::brtarget, |
| OpTypes::GPR64Opnd, OpTypes::brtarget, |
| OpTypes::GPR32Opnd, OpTypes::brtarget_lsl2_mm, |
| OpTypes::GPR32Opnd, OpTypes::brtarget, |
| OpTypes::GPR32Opnd, OpTypes::brtarget_mm, |
| OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::vsplat_uimm3, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::vsplat_uimm6, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::vsplat_uimm4, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::vsplat_uimm5, |
| OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::vsplat_uimm3, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::vsplat_uimm6, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::vsplat_uimm4, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::vsplat_uimm5, |
| OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::brtarget, |
| OpTypes::GPR64Opnd, OpTypes::brtarget, |
| OpTypes::GPR32Opnd, OpTypes::brtarget, |
| OpTypes::GPR32Opnd, OpTypes::brtarget_mm, |
| OpTypes::GPR32Opnd, OpTypes::brtarget, |
| OpTypes::GPR64Opnd, OpTypes::brtarget, |
| OpTypes::GPR32Opnd, OpTypes::brtarget_lsl2_mm, |
| OpTypes::GPR32Opnd, OpTypes::brtarget, |
| OpTypes::GPR32Opnd, OpTypes::brtarget_mm, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::brtarget, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::brtarget, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::brtarget_lsl2_mm, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::brtarget, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::brtarget, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::brtarget_lsl2_mm, |
| OpTypes::GPR32Opnd, OpTypes::brtarget, |
| OpTypes::GPR64Opnd, OpTypes::brtarget, |
| OpTypes::GPR32Opnd, OpTypes::brtarget, |
| OpTypes::GPR32Opnd, OpTypes::brtarget, |
| OpTypes::GPR32Opnd, OpTypes::brtarget_mm, |
| OpTypes::GPR32Opnd, OpTypes::brtarget, |
| OpTypes::GPR32Opnd, OpTypes::brtarget_mm, |
| OpTypes::GPR32Opnd, OpTypes::brtarget_mm, |
| OpTypes::GPR32Opnd, OpTypes::brtarget, |
| OpTypes::GPR64Opnd, OpTypes::brtarget, |
| OpTypes::GPR32Opnd, OpTypes::brtarget_lsl2_mm, |
| OpTypes::GPR32Opnd, OpTypes::brtarget, |
| OpTypes::GPR32Opnd, OpTypes::brtarget_mm, |
| OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::vsplat_uimm8, |
| OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, |
| OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::vsplat_uimm8, |
| OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::brtarget, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::brtarget, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::brtarget, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::brtarget, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::brtarget_lsl2_mm, |
| OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::vsplat_uimm3, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::vsplat_uimm6, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::vsplat_uimm4, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::vsplat_uimm5, |
| OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::brtarget, |
| OpTypes::GPRMM16Opnd, OpTypes::brtarget7_mm, |
| OpTypes::GPR32Opnd, OpTypes::brtarget, |
| OpTypes::GPR32Opnd, OpTypes::brtarget_mm, |
| OpTypes::GPR32Opnd, OpTypes::brtarget21, |
| OpTypes::GPRMM16Opnd, OpTypes::brtarget7_mm, |
| OpTypes::GPR64Opnd, OpTypes::brtarget21, |
| OpTypes::GPR32Opnd, OpTypes::brtarget_mm, |
| OpTypes::GPR32Opnd, OpTypes::brtarget21_mm, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::brtarget_mm, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::brtarget, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::brtargetr6, |
| OpTypes::MSA128BOpnd, OpTypes::brtarget, |
| OpTypes::MSA128DOpnd, OpTypes::brtarget, |
| OpTypes::MSA128HOpnd, OpTypes::brtarget, |
| OpTypes::MSA128BOpnd, OpTypes::brtarget, |
| OpTypes::MSA128WOpnd, OpTypes::brtarget, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::brtarget, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::brtargetr6, |
| OpTypes::brtarget, |
| OpTypes::brtarget1SImm16, |
| OpTypes::brtarget_mm, |
| OpTypes::uimm10, OpTypes::uimm10, |
| OpTypes::uimm4, |
| OpTypes::uimm4, |
| OpTypes::uimm10, OpTypes::uimm10, |
| OpTypes::uimm10, OpTypes::uimm10, |
| OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::vsplat_uimm8, |
| OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, |
| OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::vsplat_uimm3, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::vsplat_uimm6, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::vsplat_uimm4, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::vsplat_uimm5, |
| OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::MSA128BOpnd, OpTypes::brtarget, |
| OpTypes::MSA128DOpnd, OpTypes::brtarget, |
| OpTypes::MSA128HOpnd, OpTypes::brtarget, |
| OpTypes::MSA128BOpnd, OpTypes::brtarget, |
| OpTypes::MSA128WOpnd, OpTypes::brtarget, |
| OpTypes::CPU16Regs, OpTypes::brtarget, |
| OpTypes::CPU16Regs, OpTypes::brtarget, |
| OpTypes::brtarget, |
| OpTypes::brtarget, |
| OpTypes::CPU16Regs, OpTypes::brtarget, |
| OpTypes::CPU16Regs, OpTypes::brtarget, |
| /**/ |
| OpTypes::simm16, |
| OpTypes::simm16, |
| OpTypes::simm16, |
| OpTypes::simm16, |
| -1, OpTypes::simm16, OpTypes::uimm5, |
| -1, OpTypes::simm9, OpTypes::uimm5, |
| -1, OpTypes::simm9, OpTypes::uimm5, |
| -1, OpTypes::simm12, OpTypes::uimm5, |
| -1, OpTypes::simm12, OpTypes::uimm5, |
| -1, OpTypes::simm9, OpTypes::uimm5, |
| OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FGR64Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FGR64Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FGR32Opnd, OpTypes::AFGR64Opnd, |
| OpTypes::FGR32Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FGR32Opnd, OpTypes::AFGR64Opnd, |
| OpTypes::FGR32Opnd, OpTypes::AFGR64Opnd, |
| OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::vsplat_simm5, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::vsplat_simm5, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::vsplat_simm5, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::vsplat_simm5, |
| OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::GPR32Opnd, OpTypes::CCROpnd, |
| OpTypes::GPR32Opnd, OpTypes::CCROpnd, |
| OpTypes::GPR32Opnd, OpTypes::COP2Opnd, |
| OpTypes::GPR32Opnd, OpTypes::MSA128CROpnd, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::uimm5, OpTypes::uimm5, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::uimm5, OpTypes::uimm5, |
| OpTypes::GPR64Opnd, OpTypes::GPR32Opnd, OpTypes::uimm5, OpTypes::uimm5, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm5, OpTypes::uimm5, |
| OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::vsplat_simm5, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::vsplat_simm5, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::vsplat_simm5, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::vsplat_simm5, |
| OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::vsplat_uimm5, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::vsplat_uimm5, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::vsplat_uimm5, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::vsplat_uimm5, |
| OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::vsplat_simm5, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::vsplat_simm5, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::vsplat_simm5, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::vsplat_simm5, |
| OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::vsplat_uimm5, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::vsplat_uimm5, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::vsplat_uimm5, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::vsplat_uimm5, |
| OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::GPR32Opnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::GPR32Opnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::GPR32Opnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::GPR32Opnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::GPR32Opnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::GPR32Opnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::GPR32Opnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::GPR32Opnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::GPR32Opnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::GPR32Opnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::GPR32Opnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::FGRCCOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FGRCCOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FGRCCOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FGRCCOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::FGRCCOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FGRCCOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FGRCCOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FGRCCOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FGRCCOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FGRCCOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::FGRCCOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FGRCCOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FGRCCOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FGRCCOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::FGRCCOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FGRCCOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FGRCCOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FGRCCOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FGRCCOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FGRCCOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FGRCCOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FGRCCOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FGRCCOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FGRCCOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FGRCCOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FGRCCOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FGRCCOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FGRCCOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FGRCCOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FGRCCOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FGRCCOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FGRCCOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FGRCCOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FGRCCOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FGRCCOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FGRCCOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FGRCCOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FGRCCOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FGRCCOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FGRCCOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FGRCCOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FGRCCOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FGRCCOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FGRCCOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FGRCCOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FGRCCOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FGRCCOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FGRCCOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FGRCCOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FGRCCOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FGRCCOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FGRCCOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FGRCCOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FGRCCOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FGRCCOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FGRCCOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FGRCCOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FGRCCOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FGRCCOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FGRCCOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FGRCCOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FGRCCOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FGRCCOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FGRCCOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::MSA128BOpnd, OpTypes::uimm4_ptr, |
| OpTypes::GPR64Opnd, OpTypes::MSA128DOpnd, OpTypes::uimm1_ptr, |
| OpTypes::GPR32Opnd, OpTypes::MSA128HOpnd, OpTypes::uimm3_ptr, |
| OpTypes::GPR32Opnd, OpTypes::MSA128WOpnd, OpTypes::uimm2_ptr, |
| OpTypes::GPR32Opnd, OpTypes::MSA128BOpnd, OpTypes::uimm4_ptr, |
| OpTypes::GPR32Opnd, OpTypes::MSA128HOpnd, OpTypes::uimm3_ptr, |
| OpTypes::GPR32Opnd, OpTypes::MSA128WOpnd, OpTypes::uimm2_ptr, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::CCROpnd, OpTypes::GPR32Opnd, |
| OpTypes::CCROpnd, OpTypes::GPR32Opnd, |
| OpTypes::COP2Opnd, OpTypes::GPR32Opnd, |
| OpTypes::MSA128CROpnd, OpTypes::GPR32Opnd, |
| OpTypes::AFGR64Opnd, OpTypes::FGR32Opnd, |
| OpTypes::AFGR64Opnd, OpTypes::FGR32Opnd, |
| OpTypes::AFGR64Opnd, OpTypes::FGR32Opnd, |
| OpTypes::AFGR64Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FGR64Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FGR64Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FGR64Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FGR64Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FGR64Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FGR64Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FGR64Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FGR64Opnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FGR32Opnd, OpTypes::AFGR64Opnd, |
| OpTypes::FGR32Opnd, OpTypes::AFGR64Opnd, |
| OpTypes::FGR32Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FGR32Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FGR32Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FGR64Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FGR32Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FGR32Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FGR32Opnd, OpTypes::AFGR64Opnd, |
| OpTypes::FGR32Opnd, OpTypes::AFGR64Opnd, |
| OpTypes::FGR32Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FGR32Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FCCRegsOpnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, |
| OpTypes::FCCRegsOpnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, |
| OpTypes::FCCRegsOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FCCRegsOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FCCRegsOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FCCRegsOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FCCRegsOpnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, |
| OpTypes::FCCRegsOpnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, |
| OpTypes::FCCRegsOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FCCRegsOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FCCRegsOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FCCRegsOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FCCRegsOpnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, |
| OpTypes::FCCRegsOpnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, |
| OpTypes::FCCRegsOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FCCRegsOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FCCRegsOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FCCRegsOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FCCRegsOpnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, |
| OpTypes::FCCRegsOpnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, |
| OpTypes::FCCRegsOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FCCRegsOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FCCRegsOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FCCRegsOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FCCRegsOpnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, |
| OpTypes::FCCRegsOpnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, |
| OpTypes::FCCRegsOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FCCRegsOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FCCRegsOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FCCRegsOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FCCRegsOpnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, |
| OpTypes::FCCRegsOpnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, |
| OpTypes::FCCRegsOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FCCRegsOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FCCRegsOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FCCRegsOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FCCRegsOpnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, |
| OpTypes::FCCRegsOpnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, |
| OpTypes::FCCRegsOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FCCRegsOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FCCRegsOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FCCRegsOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FCCRegsOpnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, |
| OpTypes::FCCRegsOpnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, |
| OpTypes::FCCRegsOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FCCRegsOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FCCRegsOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FCCRegsOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FCCRegsOpnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, |
| OpTypes::FCCRegsOpnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, |
| OpTypes::FCCRegsOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FCCRegsOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FCCRegsOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FCCRegsOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FCCRegsOpnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, |
| OpTypes::FCCRegsOpnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, |
| OpTypes::FCCRegsOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FCCRegsOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FCCRegsOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FCCRegsOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FCCRegsOpnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, |
| OpTypes::FCCRegsOpnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, |
| OpTypes::FCCRegsOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FCCRegsOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FCCRegsOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FCCRegsOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FCCRegsOpnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, |
| OpTypes::FCCRegsOpnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, |
| OpTypes::FCCRegsOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FCCRegsOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FCCRegsOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FCCRegsOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FCCRegsOpnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, |
| OpTypes::FCCRegsOpnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, |
| OpTypes::FCCRegsOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FCCRegsOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FCCRegsOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FCCRegsOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FCCRegsOpnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, |
| OpTypes::FCCRegsOpnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, |
| OpTypes::FCCRegsOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FCCRegsOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FCCRegsOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FCCRegsOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FCCRegsOpnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, |
| OpTypes::FCCRegsOpnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, |
| OpTypes::FCCRegsOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FCCRegsOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FCCRegsOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FCCRegsOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FCCRegsOpnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, |
| OpTypes::FCCRegsOpnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, |
| OpTypes::FCCRegsOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FCCRegsOpnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FCCRegsOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FCCRegsOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::CPU16Regs, OpTypes::CPU16Regs, |
| OpTypes::CPU16Regs, OpTypes::simm16, |
| OpTypes::CPU16Regs, OpTypes::simm16, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::simm16_64, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::simm16_64, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::uimm16_altrelaxed, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::uimm3, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::uimm16_altrelaxed, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::uimm16, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, |
| /**/ |
| /**/ |
| /**/ |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::uimm5_report_uimm6, OpTypes::uimm5_plus1_report_uimm6, |
| OpTypes::GPR64Opnd, OpTypes::GPR32Opnd, OpTypes::uimm5_report_uimm6, OpTypes::uimm5_plus1, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::uimm5, OpTypes::uimm5_plus33, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::uimm5_plus32, OpTypes::uimm5_plus1, |
| OpTypes::GPR32Opnd, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::uimm6, OpTypes::uimm5_inssize_plus1, OpTypes::GPR64Opnd, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::uimm5, OpTypes::uimm_range_2_64, OpTypes::GPR64Opnd, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::uimm5_plus32, OpTypes::uimm5_inssize_plus1, OpTypes::GPR64Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::uimm2_plus1, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::uimm2_plus1, |
| OpTypes::GPR64Opnd, OpTypes::COP0Opnd, OpTypes::uimm3, |
| OpTypes::GPR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::GPR64Opnd, OpTypes::COP2Opnd, OpTypes::uimm3, |
| OpTypes::GPR64Opnd, OpTypes::uimm16, |
| OpTypes::GPR64Opnd, OpTypes::COP0Opnd, OpTypes::uimm3, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, |
| OpTypes::GPR32Opnd, |
| OpTypes::COP0Opnd, OpTypes::GPR64Opnd, OpTypes::uimm3, |
| OpTypes::FGR64Opnd, OpTypes::GPR64Opnd, |
| OpTypes::COP2Opnd, OpTypes::GPR64Opnd, OpTypes::uimm3, |
| OpTypes::GPR64Opnd, OpTypes::uimm16, |
| OpTypes::COP0Opnd, OpTypes::GPR64Opnd, OpTypes::uimm3, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, |
| OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, |
| OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, |
| OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, |
| OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, |
| OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, |
| OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, |
| OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, |
| OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, |
| OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, |
| OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, |
| OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, |
| OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, |
| OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, |
| OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, |
| OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, |
| OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, |
| OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, |
| OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, |
| OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, |
| OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, |
| OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, |
| OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, |
| OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, |
| OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, |
| OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, |
| OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, |
| OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, |
| OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, |
| OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, |
| OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, |
| OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, |
| OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::uimm6, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::uimm5, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::uimm6, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::uimm5, |
| OpTypes::GPR64, OpTypes::GPR32, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::uimm6, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::uimm5, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::uimm6, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::uimm5, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, |
| OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, |
| OpTypes::CPU16Regs, OpTypes::CPU16Regs, |
| OpTypes::CPU16Regs, OpTypes::CPU16Regs, |
| /**/ |
| /**/ |
| /**/ |
| OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, |
| /**/ |
| /**/ |
| /**/ |
| /**/ |
| /**/ |
| OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm5, OpTypes::uimm5_plus1, |
| OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, OpTypes::uimm5, |
| OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, OpTypes::uimm5, |
| OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, OpTypes::uimm5, |
| OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, OpTypes::uimm5, |
| OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, OpTypes::uimm5, |
| OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, OpTypes::uimm5, |
| OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, OpTypes::uimm5, |
| OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, OpTypes::uimm5, |
| OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, OpTypes::uimm5, |
| OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, OpTypes::uimm5, |
| OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, OpTypes::uimm5, |
| OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, OpTypes::uimm5, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::uimm5, OpTypes::uimm5, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::uimm5, OpTypes::uimm5, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm5, OpTypes::uimm5_plus1, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm5, OpTypes::uimm5_plus1, |
| OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, |
| OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, |
| OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, |
| OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, |
| OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::AFGR64, OpTypes::AFGR64, OpTypes::condcode, |
| OpTypes::AFGR64, OpTypes::AFGR64, OpTypes::condcode, |
| OpTypes::FGR64, OpTypes::FGR64, OpTypes::condcode, |
| OpTypes::FGR32, OpTypes::FGR32, OpTypes::condcode, |
| OpTypes::FGR32, OpTypes::FGR32, OpTypes::condcode, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, |
| OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, |
| OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128HOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128HOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128HOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128HOpnd, |
| OpTypes::MSA128BOpnd, OpTypes::GPR32Opnd, |
| OpTypes::MSA128DOpnd, OpTypes::GPR64Opnd, |
| OpTypes::MSA128HOpnd, OpTypes::GPR32Opnd, |
| OpTypes::MSA128WOpnd, OpTypes::GPR32Opnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FGR64Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FGR64Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FGR32Opnd, OpTypes::AFGR64Opnd, |
| OpTypes::FGR32Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FGR32Opnd, OpTypes::AFGR64Opnd, |
| OpTypes::FGR32Opnd, OpTypes::AFGR64Opnd, |
| OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, |
| OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, |
| OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, |
| OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, |
| OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, |
| OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, |
| OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, |
| OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, |
| OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, |
| OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, |
| OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::uimm2, |
| OpTypes::GPR32Opnd, OpTypes::uimm2, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, |
| OpTypes::uimm10, |
| OpTypes::uimm10, |
| OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm5, OpTypes::uimm5_inssize_plus1, OpTypes::GPR32Opnd, |
| OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::GPR32Opnd, OpTypes::uimm4, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::GPR64Opnd, OpTypes::uimm1, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::GPR32Opnd, OpTypes::uimm3, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::GPR32Opnd, OpTypes::uimm2, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::uimm4, OpTypes::MSA128BOpnd, OpTypes::uimmz, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::uimm1, OpTypes::MSA128DOpnd, OpTypes::uimmz, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::uimm3, OpTypes::MSA128HOpnd, OpTypes::uimmz, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::uimm2, OpTypes::MSA128WOpnd, OpTypes::uimmz, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm5, OpTypes::uimm5_inssize_plus1, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm5, OpTypes::uimm5_inssize_plus1, OpTypes::GPR32Opnd, |
| OpTypes::jmptarget, |
| OpTypes::calltarget, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, |
| OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::calltarget_mm, |
| OpTypes::calltarget, |
| OpTypes::calltarget, |
| OpTypes::calltarget_mm, |
| OpTypes::GPR32Opnd, OpTypes::calloffset16, |
| OpTypes::GPR64Opnd, OpTypes::calloffset16, |
| OpTypes::GPR32Opnd, OpTypes::calloffset16, |
| OpTypes::GPR32Opnd, OpTypes::jmpoffset16, |
| OpTypes::GPR64Opnd, OpTypes::jmpoffset16, |
| OpTypes::GPR32Opnd, OpTypes::jmpoffset16, |
| OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, |
| OpTypes::GPR64Opnd, |
| OpTypes::uimm5_lsl2, |
| OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, |
| OpTypes::uimm5_lsl2, |
| OpTypes::GPR32Opnd, |
| OpTypes::GPR64Opnd, |
| OpTypes::GPR64Opnd, |
| OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, |
| OpTypes::jmptarget_mm, |
| OpTypes::uimm26, |
| OpTypes::uimm26, |
| /**/ |
| /**/ |
| OpTypes::CPU16Regs, |
| OpTypes::CPU16Regs, |
| OpTypes::GPR32Opnd, -1, OpTypes::simm16, |
| OpTypes::GPR64Opnd, -1, OpTypes::simm16, |
| OpTypes::GPR32Opnd, -1, OpTypes::simm9, |
| OpTypes::GPR32Opnd, -1, OpTypes::simm16, |
| OpTypes::GPRMM16Opnd, -1, OpTypes::simm4, |
| OpTypes::GPR32Opnd, -1, -1, |
| OpTypes::GPR32Opnd, -1, -1, |
| OpTypes::GPR32Opnd, -1, OpTypes::simm16, |
| OpTypes::GPR32Opnd, -1, OpTypes::simm16, |
| OpTypes::GPR32Opnd, -1, OpTypes::simm16, |
| OpTypes::GPR32Opnd, -1, OpTypes::simm16, |
| OpTypes::GPR64Opnd, -1, OpTypes::simm16, |
| OpTypes::GPR32Opnd, -1, OpTypes::simm9, |
| OpTypes::GPR32Opnd, -1, OpTypes::simm16, |
| OpTypes::GPR32Opnd, -1, OpTypes::simm16, |
| OpTypes::GPR64Opnd, -1, OpTypes::simm16, |
| OpTypes::AFGR64Opnd, -1, OpTypes::simm16, |
| OpTypes::FGR64Opnd, -1, OpTypes::simm16, |
| OpTypes::FGR64Opnd, -1, OpTypes::simm16, |
| OpTypes::AFGR64Opnd, -1, OpTypes::simm16, |
| OpTypes::COP2Opnd, -1, OpTypes::simm16, |
| OpTypes::COP2Opnd, OpTypes::GPR32, OpTypes::simm11, |
| OpTypes::COP2Opnd, -1, OpTypes::simm11, |
| OpTypes::COP3Opnd, -1, OpTypes::simm16, |
| OpTypes::MSA128BOpnd, OpTypes::vsplat_simm10, |
| OpTypes::MSA128DOpnd, OpTypes::vsplat_simm10, |
| OpTypes::MSA128HOpnd, OpTypes::vsplat_simm10, |
| OpTypes::MSA128WOpnd, OpTypes::vsplat_simm10, |
| OpTypes::GPR64Opnd, -1, OpTypes::simm16, OpTypes::GPR64Opnd, |
| OpTypes::GPR64Opnd, OpTypes::simm18_lsl3, |
| OpTypes::GPR64Opnd, -1, OpTypes::simm16, OpTypes::GPR64Opnd, |
| OpTypes::AFGR64Opnd, -1, -1, |
| OpTypes::FGR64Opnd, -1, -1, |
| OpTypes::MSA128BOpnd, -1, OpTypes::simm10, |
| OpTypes::MSA128DOpnd, -1, OpTypes::simm10_lsl3, |
| OpTypes::MSA128HOpnd, -1, OpTypes::simm10_lsl1, |
| OpTypes::MSA128WOpnd, -1, OpTypes::simm10_lsl2, |
| OpTypes::GPR32Opnd, -1, OpTypes::simm16, |
| OpTypes::GPR64Opnd, -1, OpTypes::simm16, |
| OpTypes::GPR32Opnd, -1, OpTypes::simm16, |
| OpTypes::GPR32Opnd, -1, OpTypes::simm16, |
| OpTypes::GPR64Opnd, -1, OpTypes::simm16, |
| OpTypes::GPR32Opnd, -1, OpTypes::simm9, |
| OpTypes::GPR32Opnd, -1, OpTypes::simm9, |
| OpTypes::GPRMM16Opnd, -1, OpTypes::simm4, |
| OpTypes::GPR32Opnd, -1, -1, |
| OpTypes::GPR32Opnd, -1, -1, |
| OpTypes::GPR32Opnd, -1, OpTypes::simm16, |
| OpTypes::GPR32Opnd, -1, OpTypes::simm16, |
| OpTypes::GPR64Opnd, -1, OpTypes::simm16, |
| OpTypes::GPR32Opnd, -1, OpTypes::simm9, |
| OpTypes::GPR32Opnd, -1, OpTypes::simm9, |
| OpTypes::GPR32Opnd, -1, OpTypes::simm16, |
| OpTypes::GPRMM16Opnd, OpTypes::li16_imm, |
| OpTypes::GPRMM16Opnd, OpTypes::li16_imm, |
| OpTypes::GPR32Opnd, -1, OpTypes::simm16, |
| OpTypes::GPR32Opnd, -1, OpTypes::simm16, |
| OpTypes::GPR32Opnd, -1, OpTypes::simm9, |
| OpTypes::GPR64Opnd, -1, OpTypes::simm16, |
| OpTypes::GPR64Opnd, -1, OpTypes::simm9, |
| OpTypes::GPR32Opnd, -1, OpTypes::simm9, |
| OpTypes::GPR32Opnd, -1, OpTypes::simm9, |
| OpTypes::GPR32Opnd, -1, OpTypes::simm12, |
| OpTypes::GPR32Opnd, -1, OpTypes::simm9, |
| OpTypes::GPR32Opnd, -1, OpTypes::simm9, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm2_plus1, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm2_plus1, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm2_plus1, |
| OpTypes::GPR32Opnd, OpTypes::uimm16, |
| OpTypes::AFGR64Opnd, -1, -1, |
| OpTypes::FGR64Opnd, -1, -1, |
| OpTypes::FGR64Opnd, -1, -1, |
| OpTypes::GPR32Opnd, OpTypes::uimm16_relaxed, |
| OpTypes::GPR64Opnd, OpTypes::uimm16_64_relaxed, |
| OpTypes::GPR32Opnd, OpTypes::uimm16_relaxed, |
| OpTypes::GPR32Opnd, -1, OpTypes::simm16, |
| OpTypes::GPRMM16Opnd, -1, OpTypes::simm4, |
| OpTypes::GPR64Opnd, -1, OpTypes::simm16, |
| OpTypes::FGR32Opnd, -1, OpTypes::simm16, |
| OpTypes::FGR32Opnd, -1, OpTypes::simm16, |
| OpTypes::COP2Opnd, -1, OpTypes::simm16, |
| OpTypes::COP2Opnd, OpTypes::GPR32, OpTypes::simm11, |
| OpTypes::COP2Opnd, -1, OpTypes::simm11, |
| OpTypes::COP3Opnd, -1, OpTypes::simm16, |
| OpTypes::DSPROpnd, -1, OpTypes::simm16, |
| OpTypes::DSPROpnd, -1, OpTypes::simm16, |
| OpTypes::GPR32Opnd, -1, OpTypes::simm9, |
| OpTypes::GPR32Opnd, -1, OpTypes::simm9, |
| OpTypes::GPRMM16Opnd, -1, OpTypes::simm7_lsl2, |
| OpTypes::GPR32Opnd, -1, OpTypes::simm16, OpTypes::GPR32Opnd, |
| OpTypes::GPR64Opnd, -1, OpTypes::simm16, OpTypes::GPR64Opnd, |
| OpTypes::GPR32Opnd, -1, OpTypes::simm9, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, -1, OpTypes::simm9, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, -1, OpTypes::simm12, OpTypes::GPR32Opnd, |
| OpTypes::reglist16, -1, OpTypes::uimm8, |
| OpTypes::reglist16, -1, OpTypes::uimm8, |
| OpTypes::reglist, -1, OpTypes::simm12, |
| OpTypes::GPR32Opnd, OpTypes::simm19_lsl2, |
| OpTypes::GPR32Opnd, OpTypes::simm19_lsl2, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, -1, OpTypes::simm12, |
| OpTypes::GPR32Opnd, -1, OpTypes::simm16, OpTypes::GPR32Opnd, |
| OpTypes::GPR64Opnd, -1, OpTypes::simm16, OpTypes::GPR64Opnd, |
| OpTypes::GPR32Opnd, -1, OpTypes::simm9, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, -1, OpTypes::simm9, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, -1, OpTypes::simm12, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, -1, OpTypes::simm5, |
| OpTypes::GPR32Opnd, OpTypes::simm19_lsl2, |
| OpTypes::GPR32Opnd, -1, OpTypes::simm12, |
| OpTypes::GPR32Opnd, -1, -1, |
| OpTypes::FGR32Opnd, -1, -1, |
| OpTypes::FGR32Opnd, -1, -1, |
| OpTypes::GPR32Opnd, -1, -1, |
| OpTypes::GPR32Opnd, -1, -1, |
| OpTypes::GPR32Opnd, -1, OpTypes::simm16, |
| OpTypes::GPR32Opnd, -1, OpTypes::simm16, |
| OpTypes::GPR64Opnd, -1, OpTypes::simm16, |
| OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::simm16, |
| OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::simm16, |
| OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::simm16, |
| OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::simm16, |
| OpTypes::CPU16Regs, OpTypes::simm16, |
| OpTypes::CPU16Regs, OpTypes::simm16, |
| OpTypes::CPU16Regs, OpTypes::simm16, |
| OpTypes::CPU16Regs, OpTypes::pcrel16, OpTypes::i32imm, |
| OpTypes::CPU16Regs, OpTypes::pcrel16, OpTypes::i32imm, |
| OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::simm16, |
| OpTypes::CPU16Regs, OpTypes::CPU16RegsPlusSP, OpTypes::simm16, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, |
| OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, |
| OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, |
| OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, |
| OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, |
| OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, |
| OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, |
| OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, |
| OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, |
| OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, |
| OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, |
| OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, |
| OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::vsplat_simm5, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::vsplat_simm5, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::vsplat_simm5, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::vsplat_simm5, |
| OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::vsplat_uimm5, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::vsplat_uimm5, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::vsplat_uimm5, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::vsplat_uimm5, |
| OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, |
| OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::GPR32Opnd, OpTypes::COP0Opnd, OpTypes::uimm3, |
| OpTypes::GPR32Opnd, OpTypes::COP0Opnd, OpTypes::uimm3, |
| OpTypes::GPR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::FGR64Opnd, |
| OpTypes::GPR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::COP2Opnd, OpTypes::uimm3, |
| OpTypes::GPR32Opnd, OpTypes::COP2Opnd, |
| OpTypes::GPR32Opnd, OpTypes::COP0Opnd, OpTypes::uimm3, |
| OpTypes::GPR32Opnd, OpTypes::COP0Opnd, OpTypes::uimm3, |
| OpTypes::GPR32Opnd, OpTypes::COP0Opnd, OpTypes::uimm3, |
| OpTypes::GPR32Opnd, OpTypes::AFGR64Opnd, |
| OpTypes::GPR32Opnd, OpTypes::AFGR64Opnd, |
| OpTypes::GPR32Opnd, OpTypes::FGR64Opnd, |
| OpTypes::GPR32Opnd, OpTypes::FGR64Opnd, |
| OpTypes::GPR32Opnd, OpTypes::COP2Opnd, |
| OpTypes::GPR32Opnd, OpTypes::COP0Opnd, OpTypes::uimm3, |
| OpTypes::GPR32Opnd, OpTypes::COP0Opnd, OpTypes::uimm3, |
| OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, |
| OpTypes::GPR64Opnd, |
| OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, |
| OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, |
| OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, |
| OpTypes::GPR64Opnd, |
| OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, |
| OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, |
| OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm1, OpTypes::uimm3, OpTypes::uimm1, |
| OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::vsplat_simm5, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::vsplat_simm5, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::vsplat_simm5, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::vsplat_simm5, |
| OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::vsplat_uimm5, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::vsplat_uimm5, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::vsplat_uimm5, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::vsplat_uimm5, |
| OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, |
| OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPRMM16OpndMovePPairFirst, OpTypes::GPRMM16OpndMovePPairSecond, OpTypes::GPRMM16OpndMoveP, OpTypes::GPRMM16OpndMoveP, |
| OpTypes::GPRMM16OpndMovePPairFirst, OpTypes::GPRMM16OpndMovePPairSecond, OpTypes::GPRMM16OpndMoveP, OpTypes::GPRMM16OpndMoveP, |
| OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, |
| OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, OpTypes::FCCRegsOpnd, OpTypes::AFGR64Opnd, |
| OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, OpTypes::FCCRegsOpnd, OpTypes::AFGR64Opnd, |
| OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, OpTypes::FCCRegsOpnd, OpTypes::FGR64Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::FCCRegsOpnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::FCCRegsOpnd, OpTypes::GPR64Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::FCCRegsOpnd, OpTypes::GPR32Opnd, |
| OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FCCRegsOpnd, OpTypes::FGR32Opnd, |
| OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FCCRegsOpnd, OpTypes::FGR32Opnd, |
| OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, OpTypes::GPR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR64Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, |
| OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::GPR64Opnd, OpTypes::FGR32Opnd, |
| OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, OpTypes::GPR32Opnd, OpTypes::AFGR64Opnd, |
| OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, OpTypes::GPR32Opnd, OpTypes::AFGR64Opnd, |
| OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, OpTypes::GPR32Opnd, OpTypes::FGR64Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::GPR32Opnd, OpTypes::GPR64Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::GPR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::GPR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, OpTypes::FCCRegsOpnd, OpTypes::AFGR64Opnd, |
| OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, OpTypes::FCCRegsOpnd, OpTypes::AFGR64Opnd, |
| OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, OpTypes::FCCRegsOpnd, OpTypes::FGR64Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::FCCRegsOpnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::FCCRegsOpnd, OpTypes::GPR64Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::FCCRegsOpnd, OpTypes::GPR32Opnd, |
| OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FCCRegsOpnd, OpTypes::FGR32Opnd, |
| OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FCCRegsOpnd, OpTypes::FGR32Opnd, |
| OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, OpTypes::GPR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR64Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, |
| OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::GPR64Opnd, OpTypes::FGR32Opnd, |
| OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, OpTypes::GPR32Opnd, OpTypes::AFGR64Opnd, |
| OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, OpTypes::GPR32Opnd, OpTypes::AFGR64Opnd, |
| OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, OpTypes::GPR32Opnd, OpTypes::FGR64Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::GPR32Opnd, OpTypes::GPR64Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::GPR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::GPR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, |
| OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, |
| OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, |
| OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, |
| OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::COP0Opnd, OpTypes::GPR32Opnd, OpTypes::uimm3, |
| OpTypes::COP0Opnd, OpTypes::GPR32Opnd, OpTypes::uimm3, |
| OpTypes::FGR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::FGR64Opnd, OpTypes::GPR32Opnd, |
| OpTypes::FGR64Opnd, OpTypes::GPR32Opnd, |
| OpTypes::FGR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::FGR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::COP2Opnd, OpTypes::GPR32Opnd, OpTypes::uimm3, |
| OpTypes::COP2Opnd, OpTypes::GPR32Opnd, |
| OpTypes::COP0Opnd, OpTypes::GPR32Opnd, OpTypes::uimm3, |
| OpTypes::COP0Opnd, OpTypes::GPR32Opnd, OpTypes::uimm3, |
| OpTypes::COP0Opnd, OpTypes::GPR32Opnd, OpTypes::uimm3, |
| OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, OpTypes::GPR32Opnd, |
| OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, OpTypes::GPR32Opnd, |
| OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, OpTypes::GPR32Opnd, |
| OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, OpTypes::GPR32Opnd, |
| OpTypes::COP2Opnd, OpTypes::GPR32Opnd, |
| OpTypes::COP0Opnd, OpTypes::GPR32Opnd, OpTypes::uimm3, |
| OpTypes::COP0Opnd, OpTypes::GPR32Opnd, OpTypes::uimm3, |
| OpTypes::GPR32Opnd, |
| OpTypes::GPR64Opnd, |
| OpTypes::HI32DSPOpnd, OpTypes::GPR32Opnd, |
| OpTypes::HI32DSPOpnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, |
| OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, |
| OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, |
| OpTypes::GPR32Opnd, |
| OpTypes::GPR64Opnd, |
| OpTypes::LO32DSPOpnd, OpTypes::GPR32Opnd, |
| OpTypes::LO32DSPOpnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, |
| OpTypes::GPR64Opnd, |
| OpTypes::GPR64Opnd, |
| OpTypes::GPR64Opnd, |
| OpTypes::GPR64Opnd, |
| OpTypes::GPR64Opnd, |
| OpTypes::GPR64Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm1, OpTypes::uimm3, OpTypes::uimm1, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::GPR32Opnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::GPR32Opnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::GPR32Opnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, |
| OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, |
| OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, |
| OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::CPU16Regs, |
| OpTypes::CPU16Regs, |
| OpTypes::GPR32, OpTypes::CPU16Regs, |
| OpTypes::CPU16Regs, OpTypes::GPR32, |
| OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, |
| OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, |
| OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, |
| OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, |
| OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, |
| OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::vsplat_uimm8, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, |
| OpTypes::GPRMM16Opnd, OpTypes::GPRMM16Opnd, |
| OpTypes::GPRMM16Opnd, OpTypes::GPRMM16Opnd, |
| OpTypes::CPU16Regs, OpTypes::CPU16Regs, |
| OpTypes::CPU16Regs, OpTypes::CPU16Regs, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPRMM16Opnd, OpTypes::GPRMM16Opnd, OpTypes::GPRMM16Opnd, |
| OpTypes::GPRMM16Opnd, OpTypes::GPRMM16Opnd, OpTypes::GPRMM16Opnd, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, |
| OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::vsplat_uimm8, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm16, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm16, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::uimm16_64, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm16, |
| OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::CPU16Regs, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| /**/ |
| /**/ |
| /**/ |
| OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::GPR32Opnd, OpTypes::DSPROpnd, |
| OpTypes::GPR32Opnd, OpTypes::DSPROpnd, |
| OpTypes::GPR32Opnd, OpTypes::DSPROpnd, |
| OpTypes::GPR32Opnd, OpTypes::DSPROpnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::DSPROpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::DSPROpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::DSPROpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::DSPROpnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::DSPROpnd, OpTypes::GPR32Opnd, OpTypes::uimm5, OpTypes::GPR32Opnd, |
| OpTypes::DSPROpnd, OpTypes::GPR32Opnd, OpTypes::uimm5, OpTypes::GPR32Opnd, |
| OpTypes::DSPROpnd, OpTypes::GPR32Opnd, OpTypes::uimm5, OpTypes::GPR32Opnd, |
| OpTypes::DSPROpnd, OpTypes::GPR32Opnd, OpTypes::uimm5, OpTypes::GPR32Opnd, |
| -1, OpTypes::simm16, OpTypes::uimm5, |
| -1, OpTypes::simm9, OpTypes::uimm5, |
| -1, OpTypes::simm9, OpTypes::uimm5, |
| -1, -1, OpTypes::uimm5, |
| -1, OpTypes::simm12, OpTypes::uimm5, |
| -1, OpTypes::simm12, OpTypes::uimm5, |
| -1, OpTypes::simm9, OpTypes::uimm5, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm5, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm5, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::DSPROpnd, |
| OpTypes::GPR32Opnd, OpTypes::DSPROpnd, |
| OpTypes::GPR32Opnd, OpTypes::uimm10, |
| OpTypes::GPR32Opnd, OpTypes::uimm7, |
| OpTypes::GPR32Opnd, OpTypes::HWRegsOpnd, OpTypes::uimm8, |
| OpTypes::GPR64Opnd, OpTypes::HWRegsOpnd, OpTypes::uimm8, |
| OpTypes::GPR32Opnd, OpTypes::HWRegsOpnd, OpTypes::uimm8, |
| OpTypes::GPR32Opnd, OpTypes::HWRegsOpnd, OpTypes::uimm3, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, |
| OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, |
| OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::DSPROpnd, OpTypes::GPR32Opnd, |
| OpTypes::DSPROpnd, OpTypes::GPR32Opnd, |
| OpTypes::DSPROpnd, OpTypes::GPR32Opnd, |
| OpTypes::DSPROpnd, OpTypes::GPR32Opnd, |
| OpTypes::DSPROpnd, OpTypes::simm10, |
| OpTypes::DSPROpnd, OpTypes::simm10, |
| OpTypes::DSPROpnd, OpTypes::uimm8, |
| OpTypes::DSPROpnd, OpTypes::uimm8, |
| OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm5, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm5, |
| OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FGR64Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FGR64Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FGR32Opnd, OpTypes::AFGR64Opnd, |
| OpTypes::FGR32Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FGR32Opnd, OpTypes::AFGR64Opnd, |
| OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, |
| OpTypes::AFGR64Opnd, OpTypes::AFGR64Opnd, |
| OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| /**/ |
| /**/ |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, |
| OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::uimm3, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::uimm6, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::uimm4, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::uimm5, |
| OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::uimm3, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::uimm6, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::uimm4, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::uimm5, |
| OpTypes::GPR32Opnd, -1, OpTypes::simm16, |
| OpTypes::GPRMM16OpndZero, -1, OpTypes::simm4, |
| OpTypes::GPRMM16OpndZero, -1, OpTypes::simm4, |
| OpTypes::GPR64Opnd, -1, OpTypes::simm16, |
| OpTypes::GPR32Opnd, -1, OpTypes::simm9, |
| OpTypes::GPR32Opnd, -1, OpTypes::simm9, |
| OpTypes::GPR32Opnd, -1, OpTypes::simm16, |
| OpTypes::GPR32Opnd, -1, OpTypes::simm16, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, -1, OpTypes::simm16, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, -1, OpTypes::simm16, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, -1, OpTypes::simm9, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, -1, OpTypes::simm16, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, -1, OpTypes::simm9, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, -1, OpTypes::simm9, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, -1, OpTypes::simm9, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, -1, OpTypes::simm12, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, -1, OpTypes::simm9, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, -1, OpTypes::simm9, |
| OpTypes::GPR64Opnd, -1, OpTypes::simm16, |
| OpTypes::uimm20, |
| OpTypes::uimm4, |
| OpTypes::uimm4, |
| OpTypes::uimm10, |
| OpTypes::uimm20, |
| OpTypes::uimm20, |
| OpTypes::AFGR64Opnd, -1, OpTypes::simm16, |
| OpTypes::FGR64Opnd, -1, OpTypes::simm16, |
| OpTypes::FGR64Opnd, -1, OpTypes::simm16, |
| OpTypes::AFGR64Opnd, -1, OpTypes::simm16, |
| OpTypes::COP2Opnd, -1, OpTypes::simm16, |
| OpTypes::COP2Opnd, OpTypes::GPR32, OpTypes::simm11, |
| OpTypes::COP2Opnd, -1, OpTypes::simm11, |
| OpTypes::COP3Opnd, -1, OpTypes::simm16, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR64Opnd, -1, OpTypes::simm16, |
| OpTypes::GPR64Opnd, -1, OpTypes::simm16, |
| OpTypes::AFGR64Opnd, -1, -1, |
| OpTypes::FGR64Opnd, -1, -1, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, |
| OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, |
| OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FGR32Opnd, OpTypes::FGRCCOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FGR32Opnd, OpTypes::FGRCCOpnd, OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::simm10_64, |
| OpTypes::GPR32Opnd, -1, OpTypes::simm16, |
| OpTypes::GPRMM16OpndZero, -1, OpTypes::simm4, |
| OpTypes::GPRMM16OpndZero, -1, OpTypes::simm4, |
| OpTypes::GPR64Opnd, -1, OpTypes::simm16, |
| OpTypes::GPR32Opnd, -1, OpTypes::simm9, |
| OpTypes::GPR32Opnd, -1, OpTypes::simm9, |
| OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::uimm8, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::uimm8, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::uimm8, |
| OpTypes::ACC64DSPOpnd, OpTypes::simm6, OpTypes::ACC64DSPOpnd, |
| OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, |
| OpTypes::ACC64DSPOpnd, OpTypes::GPR32Opnd, OpTypes::ACC64DSPOpnd, |
| OpTypes::ACC64DSPOpnd, OpTypes::simm6, OpTypes::ACC64DSPOpnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::GPR32Opnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::GPR32Opnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::GPR32Opnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::GPR32Opnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::GPR32Opnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::uimm4, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::uimm4, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::uimm3, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::uimm3, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::uimm4, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::uimm4, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm5, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm5, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::GPR32Opnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::GPR32Opnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::GPR32Opnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::GPR32Opnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::GPR32Opnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::GPR32Opnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::GPR32Opnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::uimm4, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::uimm4, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::uimm3, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::uimm3, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::uimm4, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::uimm4, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::uimm3, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::uimm3, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm5, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm5, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::GPR32Opnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::GPR32Opnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::GPR32Opnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::GPR32Opnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::uimm4, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::uimm4, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::uimm3, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::uimm3, |
| OpTypes::GPR32Opnd, -1, OpTypes::simm16, |
| OpTypes::GPR32Opnd, -1, OpTypes::simm16, |
| OpTypes::uimm16, |
| OpTypes::uimm16, |
| OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::uimm4, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::uimm1, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::uimm3, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::uimm2, |
| OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::GPR32Opnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::GPR32Opnd, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::GPR32Opnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm5, |
| OpTypes::GPRMM16Opnd, OpTypes::GPRMM16Opnd, OpTypes::uimm3_shift, |
| OpTypes::GPRMM16Opnd, OpTypes::GPRMM16Opnd, OpTypes::uimm3_shift, |
| OpTypes::GPR64, OpTypes::GPR32, |
| OpTypes::GPR64, OpTypes::GPR64, |
| OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::vsplat_uimm3, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::vsplat_uimm6, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::vsplat_uimm4, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::vsplat_uimm5, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm5, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm5, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::simm16, |
| OpTypes::GPR32Opnd, OpTypes::GPR64Opnd, OpTypes::simm16_64, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::simm16, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::simm16, |
| OpTypes::GPR32Opnd, OpTypes::GPR64Opnd, OpTypes::simm16_64, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::simm16, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::simm10_64, |
| OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::vsplat_uimm4, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::vsplat_uimm1, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::vsplat_uimm3, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::vsplat_uimm2, |
| OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::GPR32Opnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::GPR32Opnd, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::GPR32Opnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm5, |
| OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::vsplat_uimm3, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::vsplat_uimm6, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::vsplat_uimm4, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::vsplat_uimm5, |
| OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::uimm3, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::uimm6, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::uimm4, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::uimm5, |
| OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm5, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm5, |
| OpTypes::GPRMM16Opnd, OpTypes::GPRMM16Opnd, OpTypes::uimm3_shift, |
| OpTypes::GPRMM16Opnd, OpTypes::GPRMM16Opnd, OpTypes::uimm3_shift, |
| OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::vsplat_uimm3, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::vsplat_uimm6, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::vsplat_uimm4, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::vsplat_uimm5, |
| OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::uimm3, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::uimm6, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::uimm4, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::uimm5, |
| OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm5, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| /**/ |
| /**/ |
| /**/ |
| OpTypes::MSA128BOpnd, -1, OpTypes::simm10, |
| OpTypes::MSA128DOpnd, -1, OpTypes::simm10_lsl3, |
| OpTypes::MSA128HOpnd, -1, OpTypes::simm10_lsl1, |
| OpTypes::MSA128WOpnd, -1, OpTypes::simm10_lsl2, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::GPRMM16Opnd, OpTypes::GPRMM16Opnd, OpTypes::GPRMM16Opnd, |
| OpTypes::GPRMM16Opnd, OpTypes::GPRMM16Opnd, OpTypes::GPRMM16Opnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::DSPROpnd, OpTypes::DSPROpnd, OpTypes::DSPROpnd, |
| OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::vsplat_uimm5, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::vsplat_uimm5, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::vsplat_uimm5, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::vsplat_uimm5, |
| OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::AFGR64Opnd, -1, -1, |
| OpTypes::FGR64Opnd, -1, -1, |
| OpTypes::FGR64Opnd, -1, -1, |
| OpTypes::GPR32Opnd, -1, OpTypes::simm16, |
| OpTypes::GPRMM16OpndZero, -1, OpTypes::simm4, |
| OpTypes::GPRMM16OpndZero, -1, OpTypes::simm4, |
| OpTypes::GPR64Opnd, -1, OpTypes::simm16, |
| OpTypes::FGR32Opnd, -1, OpTypes::simm16, |
| OpTypes::FGR32Opnd, -1, OpTypes::simm16, |
| OpTypes::COP2Opnd, -1, OpTypes::simm16, |
| OpTypes::COP2Opnd, OpTypes::GPR32, OpTypes::simm11, |
| OpTypes::COP2Opnd, -1, OpTypes::simm11, |
| OpTypes::COP3Opnd, -1, OpTypes::simm16, |
| OpTypes::DSPROpnd, -1, OpTypes::simm16, |
| OpTypes::DSPROpnd, -1, OpTypes::simm16, |
| OpTypes::GPR32Opnd, -1, OpTypes::simm9, |
| OpTypes::GPR32Opnd, -1, OpTypes::simm9, |
| OpTypes::GPR32Opnd, -1, OpTypes::simm16, |
| OpTypes::GPR64Opnd, -1, OpTypes::simm16, |
| OpTypes::GPR32Opnd, -1, OpTypes::simm9, |
| OpTypes::GPR32Opnd, -1, OpTypes::simm9, |
| OpTypes::GPR32Opnd, -1, OpTypes::simm12, |
| OpTypes::reglist16, -1, OpTypes::uimm8, |
| OpTypes::reglist16, -1, OpTypes::uimm8, |
| OpTypes::reglist, -1, OpTypes::simm12, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, -1, OpTypes::simm12, |
| OpTypes::GPR32Opnd, -1, OpTypes::simm16, |
| OpTypes::GPR64Opnd, -1, OpTypes::simm16, |
| OpTypes::GPR32Opnd, -1, OpTypes::simm9, |
| OpTypes::GPR32Opnd, -1, OpTypes::simm9, |
| OpTypes::GPR32Opnd, -1, OpTypes::simm12, |
| OpTypes::GPR32Opnd, -1, OpTypes::simm5, |
| OpTypes::GPR32Opnd, -1, OpTypes::simm5, |
| OpTypes::FGR32Opnd, -1, -1, |
| OpTypes::FGR32Opnd, -1, -1, |
| OpTypes::GPR32Opnd, -1, OpTypes::simm16, |
| OpTypes::GPR32Opnd, -1, OpTypes::simm16, |
| OpTypes::uimm5, |
| -1, OpTypes::simm16, |
| -1, OpTypes::simm16, |
| -1, OpTypes::simm16, |
| OpTypes::uimm5, |
| OpTypes::uimm5, |
| OpTypes::uimm20, |
| OpTypes::uimm10, |
| /**/ |
| /**/ |
| OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::simm16, |
| OpTypes::CPU16Regs, OpTypes::CPU16Regs, |
| OpTypes::CPU16Regs, OpTypes::CPU16Regs, |
| OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::simm16, |
| OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::uimm5, |
| OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::CPU16Regs, |
| OpTypes::CPU16Regs, OpTypes::CPU16Regs, |
| OpTypes::CPU16Regs, OpTypes::simm16, |
| OpTypes::CPU16Regs, OpTypes::simm16, |
| OpTypes::CPU16Regs, OpTypes::simm16, |
| OpTypes::CPU16Regs, OpTypes::simm16, |
| OpTypes::CPU16Regs, OpTypes::CPU16Regs, |
| OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::uimm5, |
| OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::CPU16Regs, |
| OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::uimm5, |
| OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::CPU16Regs, |
| OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::CPU16Regs, |
| OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::simm16, |
| OpTypes::CPU16Regs, OpTypes::CPU16RegsPlusSP, OpTypes::simm16, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm10, |
| OpTypes::GPR32Opnd, OpTypes::simm16, |
| OpTypes::GPR32Opnd, OpTypes::simm16, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm4, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm10, |
| OpTypes::GPR32Opnd, OpTypes::simm16, |
| OpTypes::GPR32Opnd, OpTypes::simm16, |
| OpTypes::GPR32Opnd, OpTypes::simm16, |
| OpTypes::GPR32Opnd, OpTypes::simm16, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm10, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm4, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm4, |
| /**/ |
| /**/ |
| /**/ |
| /**/ |
| /**/ |
| /**/ |
| /**/ |
| /**/ |
| /**/ |
| /**/ |
| /**/ |
| /**/ |
| /**/ |
| /**/ |
| /**/ |
| /**/ |
| /**/ |
| /**/ |
| /**/ |
| /**/ |
| /**/ |
| /**/ |
| /**/ |
| /**/ |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm10, |
| OpTypes::GPR32Opnd, OpTypes::simm16, |
| OpTypes::GPR32Opnd, OpTypes::simm16, |
| OpTypes::GPR32Opnd, OpTypes::simm16, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm10, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm4, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm4, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm10, |
| OpTypes::GPR32Opnd, OpTypes::simm16, |
| OpTypes::GPR32Opnd, OpTypes::simm16, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm4, |
| OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FGR64Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FGR64Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FGR64Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FGR32Opnd, OpTypes::AFGR64Opnd, |
| OpTypes::FGR32Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FGR32Opnd, OpTypes::FGR64Opnd, |
| OpTypes::FGR32Opnd, OpTypes::AFGR64Opnd, |
| OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::FGR32Opnd, OpTypes::FGR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::simm16, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, |
| OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, |
| OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, OpTypes::MSA128DOpnd, |
| OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, OpTypes::MSA128HOpnd, |
| OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, OpTypes::MSA128WOpnd, |
| /**/ |
| OpTypes::uimm10, |
| OpTypes::uimm10, |
| OpTypes::GPR32Opnd, OpTypes::uimm10, |
| OpTypes::GPR32Opnd, OpTypes::uimm7, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPRMM16Opnd, OpTypes::GPRMM16Opnd, OpTypes::GPRMM16Opnd, |
| OpTypes::GPRMM16Opnd, OpTypes::GPRMM16Opnd, OpTypes::GPRMM16Opnd, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, |
| OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::vsplat_uimm8, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm16, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, OpTypes::MSA128BOpnd, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm16, |
| OpTypes::GPR64Opnd, OpTypes::GPR64Opnd, OpTypes::uimm16_64, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, OpTypes::uimm16, |
| OpTypes::CPU16Regs, OpTypes::CPU16Regs, OpTypes::CPU16Regs, |
| OpTypes::GPR32Opnd, OpTypes::GPR32Opnd, |
| }; |
| return OpcodeOperandTypes[Offsets[Opcode] + OpIdx]; |
| } |
| } // end namespace Mips |
| } // end namespace llvm |
| #endif // GET_INSTRINFO_OPERAND_TYPE |
| |
| #ifdef GET_INSTRMAP_INFO |
| #undef GET_INSTRMAP_INFO |
| namespace llvm { |
| |
| namespace Mips { |
| |
| enum Arch { |
| Arch_dsp, |
| Arch_mmdsp, |
| Arch_mipsr6, |
| Arch_micromipsr6, |
| Arch_se, |
| Arch_micromips |
| }; |
| |
| // Dsp2MicroMips |
| LLVM_READONLY |
| int Dsp2MicroMips(uint16_t Opcode, enum Arch inArch) { |
| static const uint16_t Dsp2MicroMipsTable[][3] = { |
| { Mips::ABSQ_S_PH, Mips::ABSQ_S_PH, Mips::ABSQ_S_PH_MM }, |
| { Mips::ABSQ_S_QB, Mips::ABSQ_S_QB, Mips::ABSQ_S_QB_MMR2 }, |
| { Mips::ABSQ_S_W, Mips::ABSQ_S_W, Mips::ABSQ_S_W_MM }, |
| { Mips::ADDQH_PH, Mips::ADDQH_PH, Mips::ADDQH_PH_MMR2 }, |
| { Mips::ADDQH_R_PH, Mips::ADDQH_R_PH, Mips::ADDQH_R_PH_MMR2 }, |
| { Mips::ADDQH_R_W, Mips::ADDQH_R_W, Mips::ADDQH_R_W_MMR2 }, |
| { Mips::ADDQH_W, Mips::ADDQH_W, Mips::ADDQH_W_MMR2 }, |
| { Mips::ADDQ_PH, Mips::ADDQ_PH, Mips::ADDQ_PH_MM }, |
| { Mips::ADDQ_S_PH, Mips::ADDQ_S_PH, Mips::ADDQ_S_PH_MM }, |
| { Mips::ADDQ_S_W, Mips::ADDQ_S_W, Mips::ADDQ_S_W_MM }, |
| { Mips::ADDSC, Mips::ADDSC, Mips::ADDSC_MM }, |
| { Mips::ADDUH_QB, Mips::ADDUH_QB, Mips::ADDUH_QB_MMR2 }, |
| { Mips::ADDUH_R_QB, Mips::ADDUH_R_QB, Mips::ADDUH_R_QB_MMR2 }, |
| { Mips::ADDU_PH, Mips::ADDU_PH, Mips::ADDU_PH_MMR2 }, |
| { Mips::ADDU_QB, Mips::ADDU_QB, Mips::ADDU_QB_MM }, |
| { Mips::ADDU_S_PH, Mips::ADDU_S_PH, Mips::ADDU_S_PH_MMR2 }, |
| { Mips::ADDU_S_QB, Mips::ADDU_S_QB, Mips::ADDU_S_QB_MM }, |
| { Mips::ADDWC, Mips::ADDWC, Mips::ADDWC_MM }, |
| { Mips::APPEND, Mips::APPEND, Mips::APPEND_MMR2 }, |
| { Mips::BALIGN, Mips::BALIGN, Mips::BALIGN_MMR2 }, |
| { Mips::BITREV, Mips::BITREV, Mips::BITREV_MM }, |
| { Mips::BPOSGE32, Mips::BPOSGE32, Mips::BPOSGE32_MM }, |
| { Mips::CMPGDU_EQ_QB, Mips::CMPGDU_EQ_QB, Mips::CMPGDU_EQ_QB_MMR2 }, |
| { Mips::CMPGDU_LE_QB, Mips::CMPGDU_LE_QB, Mips::CMPGDU_LE_QB_MMR2 }, |
| { Mips::CMPGDU_LT_QB, Mips::CMPGDU_LT_QB, Mips::CMPGDU_LT_QB_MMR2 }, |
| { Mips::CMPGU_EQ_QB, Mips::CMPGU_EQ_QB, Mips::CMPGU_EQ_QB_MM }, |
| { Mips::CMPGU_LE_QB, Mips::CMPGU_LE_QB, Mips::CMPGU_LE_QB_MM }, |
| { Mips::CMPGU_LT_QB, Mips::CMPGU_LT_QB, Mips::CMPGU_LT_QB_MM }, |
| { Mips::CMPU_EQ_QB, Mips::CMPU_EQ_QB, Mips::CMPU_EQ_QB_MM }, |
| { Mips::CMPU_LE_QB, Mips::CMPU_LE_QB, Mips::CMPU_LE_QB_MM }, |
| { Mips::CMPU_LT_QB, Mips::CMPU_LT_QB, Mips::CMPU_LT_QB_MM }, |
| { Mips::CMP_EQ_PH, Mips::CMP_EQ_PH, Mips::CMP_EQ_PH_MM }, |
| { Mips::CMP_LE_PH, Mips::CMP_LE_PH, Mips::CMP_LE_PH_MM }, |
| { Mips::CMP_LT_PH, Mips::CMP_LT_PH, Mips::CMP_LT_PH_MM }, |
| { Mips::DPAQX_SA_W_PH, Mips::DPAQX_SA_W_PH, Mips::DPAQX_SA_W_PH_MMR2 }, |
| { Mips::DPAQX_S_W_PH, Mips::DPAQX_S_W_PH, Mips::DPAQX_S_W_PH_MMR2 }, |
| { Mips::DPAQ_SA_L_W, Mips::DPAQ_SA_L_W, Mips::DPAQ_SA_L_W_MM }, |
| { Mips::DPAQ_S_W_PH, Mips::DPAQ_S_W_PH, Mips::DPAQ_S_W_PH_MM }, |
| { Mips::DPAU_H_QBL, Mips::DPAU_H_QBL, Mips::DPAU_H_QBL_MM }, |
| { Mips::DPAU_H_QBR, Mips::DPAU_H_QBR, Mips::DPAU_H_QBR_MM }, |
| { Mips::DPAX_W_PH, Mips::DPAX_W_PH, Mips::DPAX_W_PH_MMR2 }, |
| { Mips::DPA_W_PH, Mips::DPA_W_PH, Mips::DPA_W_PH_MMR2 }, |
| { Mips::DPSQX_SA_W_PH, Mips::DPSQX_SA_W_PH, Mips::DPSQX_SA_W_PH_MMR2 }, |
| { Mips::DPSQX_S_W_PH, Mips::DPSQX_S_W_PH, Mips::DPSQX_S_W_PH_MMR2 }, |
| { Mips::DPSQ_SA_L_W, Mips::DPSQ_SA_L_W, Mips::DPSQ_SA_L_W_MM }, |
| { Mips::DPSQ_S_W_PH, Mips::DPSQ_S_W_PH, Mips::DPSQ_S_W_PH_MM }, |
| { Mips::DPSU_H_QBL, Mips::DPSU_H_QBL, Mips::DPSU_H_QBL_MM }, |
| { Mips::DPSU_H_QBR, Mips::DPSU_H_QBR, Mips::DPSU_H_QBR_MM }, |
| { Mips::DPSX_W_PH, Mips::DPSX_W_PH, Mips::DPSX_W_PH_MMR2 }, |
| { Mips::DPS_W_PH, Mips::DPS_W_PH, Mips::DPS_W_PH_MMR2 }, |
| { Mips::EXTP, Mips::EXTP, Mips::EXTP_MM }, |
| { Mips::EXTPDP, Mips::EXTPDP, Mips::EXTPDP_MM }, |
| { Mips::EXTPDPV, Mips::EXTPDPV, Mips::EXTPDPV_MM }, |
| { Mips::EXTPV, Mips::EXTPV, Mips::EXTPV_MM }, |
| { Mips::EXTRV_RS_W, Mips::EXTRV_RS_W, Mips::EXTRV_RS_W_MM }, |
| { Mips::EXTRV_R_W, Mips::EXTRV_R_W, Mips::EXTRV_R_W_MM }, |
| { Mips::EXTRV_S_H, Mips::EXTRV_S_H, Mips::EXTRV_S_H_MM }, |
| { Mips::EXTRV_W, Mips::EXTRV_W, Mips::EXTRV_W_MM }, |
| { Mips::EXTR_RS_W, Mips::EXTR_RS_W, Mips::EXTR_RS_W_MM }, |
| { Mips::EXTR_R_W, Mips::EXTR_R_W, Mips::EXTR_R_W_MM }, |
| { Mips::EXTR_S_H, Mips::EXTR_S_H, Mips::EXTR_S_H_MM }, |
| { Mips::EXTR_W, Mips::EXTR_W, Mips::EXTR_W_MM }, |
| { Mips::INSV, Mips::INSV, Mips::INSV_MM }, |
| { Mips::LBUX, Mips::LBUX, Mips::LBUX_MM }, |
| { Mips::LHX, Mips::LHX, Mips::LHX_MM }, |
| { Mips::LWDSP, Mips::LWDSP, Mips::LWDSP_MM }, |
| { Mips::LWX, Mips::LWX, Mips::LWX_MM }, |
| { Mips::MADDU_DSP, Mips::MADDU_DSP, Mips::MADDU_DSP_MM }, |
| { Mips::MADD_DSP, Mips::MADD_DSP, Mips::MADD_DSP_MM }, |
| { Mips::MAQ_SA_W_PHL, Mips::MAQ_SA_W_PHL, Mips::MAQ_SA_W_PHL_MM }, |
| { Mips::MAQ_SA_W_PHR, Mips::MAQ_SA_W_PHR, Mips::MAQ_SA_W_PHR_MM }, |
| { Mips::MAQ_S_W_PHL, Mips::MAQ_S_W_PHL, Mips::MAQ_S_W_PHL_MM }, |
| { Mips::MAQ_S_W_PHR, Mips::MAQ_S_W_PHR, Mips::MAQ_S_W_PHR_MM }, |
| { Mips::MFHI_DSP, Mips::MFHI_DSP, Mips::MFHI_DSP_MM }, |
| { Mips::MFLO_DSP, Mips::MFLO_DSP, Mips::MFLO_DSP_MM }, |
| { Mips::MODSUB, Mips::MODSUB, Mips::MODSUB_MM }, |
| { Mips::MSUBU_DSP, Mips::MSUBU_DSP, Mips::MSUBU_DSP_MM }, |
| { Mips::MSUB_DSP, Mips::MSUB_DSP, Mips::MSUB_DSP_MM }, |
| { Mips::MTHI_DSP, Mips::MTHI_DSP, Mips::MTHI_DSP_MM }, |
| { Mips::MTHLIP, Mips::MTHLIP, Mips::MTHLIP_MM }, |
| { Mips::MTLO_DSP, Mips::MTLO_DSP, Mips::MTLO_DSP_MM }, |
| { Mips::MULEQ_S_W_PHL, Mips::MULEQ_S_W_PHL, Mips::MULEQ_S_W_PHL_MM }, |
| { Mips::MULEQ_S_W_PHR, Mips::MULEQ_S_W_PHR, Mips::MULEQ_S_W_PHR_MM }, |
| { Mips::MULEU_S_PH_QBL, Mips::MULEU_S_PH_QBL, Mips::MULEU_S_PH_QBL_MM }, |
| { Mips::MULEU_S_PH_QBR, Mips::MULEU_S_PH_QBR, Mips::MULEU_S_PH_QBR_MM }, |
| { Mips::MULQ_RS_PH, Mips::MULQ_RS_PH, Mips::MULQ_RS_PH_MM }, |
| { Mips::MULQ_RS_W, Mips::MULQ_RS_W, Mips::MULQ_RS_W_MMR2 }, |
| { Mips::MULQ_S_PH, Mips::MULQ_S_PH, Mips::MULQ_S_PH_MMR2 }, |
| { Mips::MULQ_S_W, Mips::MULQ_S_W, Mips::MULQ_S_W_MMR2 }, |
| { Mips::MULSAQ_S_W_PH, Mips::MULSAQ_S_W_PH, Mips::MULSAQ_S_W_PH_MM }, |
| { Mips::MULSA_W_PH, Mips::MULSA_W_PH, Mips::MULSA_W_PH_MMR2 }, |
| { Mips::MULTU_DSP, Mips::MULTU_DSP, Mips::MULTU_DSP_MM }, |
| { Mips::MULT_DSP, Mips::MULT_DSP, Mips::MULT_DSP_MM }, |
| { Mips::MUL_PH, Mips::MUL_PH, Mips::MUL_PH_MMR2 }, |
| { Mips::MUL_S_PH, Mips::MUL_S_PH, Mips::MUL_S_PH_MMR2 }, |
| { Mips::PACKRL_PH, Mips::PACKRL_PH, Mips::PACKRL_PH_MM }, |
| { Mips::PICK_PH, Mips::PICK_PH, Mips::PICK_PH_MM }, |
| { Mips::PICK_QB, Mips::PICK_QB, Mips::PICK_QB_MM }, |
| { Mips::PRECEQU_PH_QBL, Mips::PRECEQU_PH_QBL, Mips::PRECEQU_PH_QBL_MM }, |
| { Mips::PRECEQU_PH_QBLA, Mips::PRECEQU_PH_QBLA, Mips::PRECEQU_PH_QBLA_MM }, |
| { Mips::PRECEQU_PH_QBR, Mips::PRECEQU_PH_QBR, Mips::PRECEQU_PH_QBR_MM }, |
| { Mips::PRECEQU_PH_QBRA, Mips::PRECEQU_PH_QBRA, Mips::PRECEQU_PH_QBRA_MM }, |
| { Mips::PRECEQ_W_PHL, Mips::PRECEQ_W_PHL, Mips::PRECEQ_W_PHL_MM }, |
| { Mips::PRECEQ_W_PHR, Mips::PRECEQ_W_PHR, Mips::PRECEQ_W_PHR_MM }, |
| { Mips::PRECEU_PH_QBL, Mips::PRECEU_PH_QBL, Mips::PRECEU_PH_QBL_MM }, |
| { Mips::PRECEU_PH_QBLA, Mips::PRECEU_PH_QBLA, Mips::PRECEU_PH_QBLA_MM }, |
| { Mips::PRECEU_PH_QBR, Mips::PRECEU_PH_QBR, Mips::PRECEU_PH_QBR_MM }, |
| { Mips::PRECEU_PH_QBRA, Mips::PRECEU_PH_QBRA, Mips::PRECEU_PH_QBRA_MM }, |
| { Mips::PRECRQU_S_QB_PH, Mips::PRECRQU_S_QB_PH, Mips::PRECRQU_S_QB_PH_MM }, |
| { Mips::PRECRQ_PH_W, Mips::PRECRQ_PH_W, Mips::PRECRQ_PH_W_MM }, |
| { Mips::PRECRQ_QB_PH, Mips::PRECRQ_QB_PH, Mips::PRECRQ_QB_PH_MM }, |
| { Mips::PRECRQ_RS_PH_W, Mips::PRECRQ_RS_PH_W, Mips::PRECRQ_RS_PH_W_MM }, |
| { Mips::PRECR_QB_PH, Mips::PRECR_QB_PH, Mips::PRECR_QB_PH_MMR2 }, |
| { Mips::PRECR_SRA_PH_W, Mips::PRECR_SRA_PH_W, Mips::PRECR_SRA_PH_W_MMR2 }, |
| { Mips::PRECR_SRA_R_PH_W, Mips::PRECR_SRA_R_PH_W, Mips::PRECR_SRA_R_PH_W_MMR2 }, |
| { Mips::PREPEND, Mips::PREPEND, Mips::PREPEND_MMR2 }, |
| { Mips::RADDU_W_QB, Mips::RADDU_W_QB, Mips::RADDU_W_QB_MM }, |
| { Mips::RDDSP, Mips::RDDSP, Mips::RDDSP_MM }, |
| { Mips::REPLV_PH, Mips::REPLV_PH, Mips::REPLV_PH_MM }, |
| { Mips::REPLV_QB, Mips::REPLV_QB, Mips::REPLV_QB_MM }, |
| { Mips::REPL_PH, Mips::REPL_PH, Mips::REPL_PH_MM }, |
| { Mips::REPL_QB, Mips::REPL_QB, Mips::REPL_QB_MM }, |
| { Mips::SHILO, Mips::SHILO, Mips::SHILO_MM }, |
| { Mips::SHILOV, Mips::SHILOV, Mips::SHILOV_MM }, |
| { Mips::SHLLV_PH, Mips::SHLLV_PH, Mips::SHLLV_PH_MM }, |
| { Mips::SHLLV_QB, Mips::SHLLV_QB, Mips::SHLLV_QB_MM }, |
| { Mips::SHLLV_S_PH, Mips::SHLLV_S_PH, Mips::SHLLV_S_PH_MM }, |
| { Mips::SHLLV_S_W, Mips::SHLLV_S_W, Mips::SHLLV_S_W_MM }, |
| { Mips::SHLL_PH, Mips::SHLL_PH, Mips::SHLL_PH_MM }, |
| { Mips::SHLL_QB, Mips::SHLL_QB, Mips::SHLL_QB_MM }, |
| { Mips::SHLL_S_PH, Mips::SHLL_S_PH, Mips::SHLL_S_PH_MM }, |
| { Mips::SHLL_S_W, Mips::SHLL_S_W, Mips::SHLL_S_W_MM }, |
| { Mips::SHRAV_PH, Mips::SHRAV_PH, Mips::SHRAV_PH_MM }, |
| { Mips::SHRAV_QB, Mips::SHRAV_QB, Mips::SHRAV_QB_MMR2 }, |
| { Mips::SHRAV_R_PH, Mips::SHRAV_R_PH, Mips::SHRAV_R_PH_MM }, |
| { Mips::SHRAV_R_QB, Mips::SHRAV_R_QB, Mips::SHRAV_R_QB_MMR2 }, |
| { Mips::SHRAV_R_W, Mips::SHRAV_R_W, Mips::SHRAV_R_W_MM }, |
| { Mips::SHRA_PH, Mips::SHRA_PH, Mips::SHRA_PH_MM }, |
| { Mips::SHRA_QB, Mips::SHRA_QB, Mips::SHRA_QB_MMR2 }, |
| { Mips::SHRA_R_PH, Mips::SHRA_R_PH, Mips::SHRA_R_PH_MM }, |
| { Mips::SHRA_R_QB, Mips::SHRA_R_QB, Mips::SHRA_R_QB_MMR2 }, |
| { Mips::SHRA_R_W, Mips::SHRA_R_W, Mips::SHRA_R_W_MM }, |
| { Mips::SHRLV_PH, Mips::SHRLV_PH, Mips::SHRLV_PH_MMR2 }, |
| { Mips::SHRLV_QB, Mips::SHRLV_QB, Mips::SHRLV_QB_MM }, |
| { Mips::SHRL_PH, Mips::SHRL_PH, Mips::SHRL_PH_MMR2 }, |
| { Mips::SHRL_QB, Mips::SHRL_QB, Mips::SHRL_QB_MM }, |
| { Mips::SUBQH_PH, Mips::SUBQH_PH, Mips::SUBQH_PH_MMR2 }, |
| { Mips::SUBQH_R_PH, Mips::SUBQH_R_PH, Mips::SUBQH_R_PH_MMR2 }, |
| { Mips::SUBQH_R_W, Mips::SUBQH_R_W, Mips::SUBQH_R_W_MMR2 }, |
| { Mips::SUBQH_W, Mips::SUBQH_W, Mips::SUBQH_W_MMR2 }, |
| { Mips::SUBQ_PH, Mips::SUBQ_PH, Mips::SUBQ_PH_MM }, |
| { Mips::SUBQ_S_PH, Mips::SUBQ_S_PH, Mips::SUBQ_S_PH_MM }, |
| { Mips::SUBQ_S_W, Mips::SUBQ_S_W, Mips::SUBQ_S_W_MM }, |
| { Mips::SUBUH_QB, Mips::SUBUH_QB, Mips::SUBUH_QB_MMR2 }, |
| { Mips::SUBUH_R_QB, Mips::SUBUH_R_QB, Mips::SUBUH_R_QB_MMR2 }, |
| { Mips::SUBU_PH, Mips::SUBU_PH, Mips::SUBU_PH_MMR2 }, |
| { Mips::SUBU_QB, Mips::SUBU_QB, Mips::SUBU_QB_MM }, |
| { Mips::SUBU_S_PH, Mips::SUBU_S_PH, Mips::SUBU_S_PH_MMR2 }, |
| { Mips::SUBU_S_QB, Mips::SUBU_S_QB, Mips::SUBU_S_QB_MM }, |
| { Mips::SWDSP, Mips::SWDSP, Mips::SWDSP_MM }, |
| }; // End of Dsp2MicroMipsTable |
| |
| unsigned mid; |
| unsigned start = 0; |
| unsigned end = 160; |
| while (start < end) { |
| mid = start + (end - start)/2; |
| if (Opcode == Dsp2MicroMipsTable[mid][0]) { |
| break; |
| } |
| if (Opcode < Dsp2MicroMipsTable[mid][0]) |
| end = mid; |
| else |
| start = mid + 1; |
| } |
| if (start == end) |
| return -1; // Instruction doesn't exist in this table. |
| |
| if (inArch == Arch_dsp) |
| return Dsp2MicroMipsTable[mid][1]; |
| if (inArch == Arch_mmdsp) |
| return Dsp2MicroMipsTable[mid][2]; |
| return -1;} |
| |
| // MipsR62MicroMipsR6 |
| LLVM_READONLY |
| int MipsR62MicroMipsR6(uint16_t Opcode, enum Arch inArch) { |
| static const uint16_t MipsR62MicroMipsR6Table[][3] = { |
| { Mips::ADDIUPC, Mips::ADDIUPC, Mips::ADDIUPC_MMR6 }, |
| { Mips::ALIGN, Mips::ALIGN, Mips::ALIGN_MMR6 }, |
| { Mips::ALUIPC, Mips::ALUIPC, Mips::ALUIPC_MMR6 }, |
| { Mips::AUI, Mips::AUI, Mips::AUI_MMR6 }, |
| { Mips::AUIPC, Mips::AUIPC, Mips::AUIPC_MMR6 }, |
| { Mips::BALC, Mips::BALC, Mips::BALC_MMR6 }, |
| { Mips::BC, Mips::BC, Mips::BC_MMR6 }, |
| { Mips::BEQC, Mips::BEQC, Mips::BEQC_MMR6 }, |
| { Mips::BEQZALC, Mips::BEQZALC, Mips::BEQZALC_MMR6 }, |
| { Mips::BEQZC, Mips::BEQZC, Mips::BEQZC_MMR6 }, |
| { Mips::BGEC, Mips::BGEC, Mips::BGEC_MMR6 }, |
| { Mips::BGEUC, Mips::BGEUC, Mips::BGEUC_MMR6 }, |
| { Mips::BGEZALC, Mips::BGEZALC, Mips::BGEZALC_MMR6 }, |
| { Mips::BGEZC, Mips::BGEZC, Mips::BGEZC_MMR6 }, |
| { Mips::BGTZALC, Mips::BGTZALC, Mips::BGTZALC_MMR6 }, |
| { Mips::BGTZC, Mips::BGTZC, Mips::BGTZC_MMR6 }, |
| { Mips::BITSWAP, Mips::BITSWAP, Mips::BITSWAP_MMR6 }, |
| { Mips::BLEZALC, Mips::BLEZALC, Mips::BLEZALC_MMR6 }, |
| { Mips::BLEZC, Mips::BLEZC, Mips::BLEZC_MMR6 }, |
| { Mips::BLTC, Mips::BLTC, Mips::BLTC_MMR6 }, |
| { Mips::BLTUC, Mips::BLTUC, Mips::BLTUC_MMR6 }, |
| { Mips::BLTZALC, Mips::BLTZALC, Mips::BLTZALC_MMR6 }, |
| { Mips::BLTZC, Mips::BLTZC, Mips::BLTZC_MMR6 }, |
| { Mips::BNEC, Mips::BNEC, Mips::BNEC_MMR6 }, |
| { Mips::BNEZALC, Mips::BNEZALC, Mips::BNEZALC_MMR6 }, |
| { Mips::BNEZC, Mips::BNEZC, Mips::BNEZC_MMR6 }, |
| { Mips::BNVC, Mips::BNVC, Mips::BNVC_MMR6 }, |
| { Mips::BOVC, Mips::BOVC, Mips::BOVC_MMR6 }, |
| { Mips::CACHE_R6, Mips::CACHE_R6, Mips::CACHE_MMR6 }, |
| { Mips::CLO_R6, Mips::CLO_R6, Mips::CLO_MMR6 }, |
| { Mips::CLZ_R6, Mips::CLZ_R6, Mips::CLZ_MMR6 }, |
| { Mips::CMP_EQ_D, Mips::CMP_EQ_D, Mips::CMP_EQ_D_MMR6 }, |
| { Mips::CMP_EQ_S, Mips::CMP_EQ_S, Mips::CMP_EQ_S_MMR6 }, |
| { Mips::CMP_F_D, Mips::CMP_F_D, Mips::CMP_AF_D_MMR6 }, |
| { Mips::CMP_F_S, Mips::CMP_F_S, Mips::CMP_AF_S_MMR6 }, |
| { Mips::CMP_LE_D, Mips::CMP_LE_D, Mips::CMP_LE_D_MMR6 }, |
| { Mips::CMP_LE_S, Mips::CMP_LE_S, Mips::CMP_LE_S_MMR6 }, |
| { Mips::CMP_LT_D, Mips::CMP_LT_D, Mips::CMP_LT_D_MMR6 }, |
| { Mips::CMP_LT_S, Mips::CMP_LT_S, Mips::CMP_LT_S_MMR6 }, |
| { Mips::CMP_SAF_D, Mips::CMP_SAF_D, Mips::CMP_SAF_D_MMR6 }, |
| { Mips::CMP_SAF_S, Mips::CMP_SAF_S, Mips::CMP_SAF_S_MMR6 }, |
| { Mips::CMP_SEQ_D, Mips::CMP_SEQ_D, Mips::CMP_SEQ_D_MMR6 }, |
| { Mips::CMP_SEQ_S, Mips::CMP_SEQ_S, Mips::CMP_SEQ_S_MMR6 }, |
| { Mips::CMP_SLE_D, Mips::CMP_SLE_D, Mips::CMP_SLE_D_MMR6 }, |
| { Mips::CMP_SLE_S, Mips::CMP_SLE_S, Mips::CMP_SLE_S_MMR6 }, |
| { Mips::CMP_SLT_D, Mips::CMP_SLT_D, Mips::CMP_SLT_D_MMR6 }, |
| { Mips::CMP_SLT_S, Mips::CMP_SLT_S, Mips::CMP_SLT_S_MMR6 }, |
| { Mips::CMP_SUEQ_D, Mips::CMP_SUEQ_D, Mips::CMP_SUEQ_D_MMR6 }, |
| { Mips::CMP_SUEQ_S, Mips::CMP_SUEQ_S, Mips::CMP_SUEQ_S_MMR6 }, |
| { Mips::CMP_SULE_D, Mips::CMP_SULE_D, Mips::CMP_SULE_D_MMR6 }, |
| { Mips::CMP_SULE_S, Mips::CMP_SULE_S, Mips::CMP_SULE_S_MMR6 }, |
| { Mips::CMP_SULT_D, Mips::CMP_SULT_D, Mips::CMP_SULT_D_MMR6 }, |
| { Mips::CMP_SULT_S, Mips::CMP_SULT_S, Mips::CMP_SULT_S_MMR6 }, |
| { Mips::CMP_SUN_D, Mips::CMP_SUN_D, Mips::CMP_SUN_D_MMR6 }, |
| { Mips::CMP_SUN_S, Mips::CMP_SUN_S, Mips::CMP_SUN_S_MMR6 }, |
| { Mips::CMP_UEQ_D, Mips::CMP_UEQ_D, Mips::CMP_UEQ_D_MMR6 }, |
| { Mips::CMP_UEQ_S, Mips::CMP_UEQ_S, Mips::CMP_UEQ_S_MMR6 }, |
| { Mips::CMP_ULE_D, Mips::CMP_ULE_D, Mips::CMP_ULE_D_MMR6 }, |
| { Mips::CMP_ULE_S, Mips::CMP_ULE_S, Mips::CMP_ULE_S_MMR6 }, |
| { Mips::CMP_ULT_D, Mips::CMP_ULT_D, Mips::CMP_ULT_D_MMR6 }, |
| { Mips::CMP_ULT_S, Mips::CMP_ULT_S, Mips::CMP_ULT_S_MMR6 }, |
| { Mips::CMP_UN_D, Mips::CMP_UN_D, Mips::CMP_UN_D_MMR6 }, |
| { Mips::CMP_UN_S, Mips::CMP_UN_S, Mips::CMP_UN_S_MMR6 }, |
| { Mips::CRC32B, Mips::CRC32B, (uint16_t)-1U }, |
| { Mips::CRC32CB, Mips::CRC32CB, (uint16_t)-1U }, |
| { Mips::CRC32CD, Mips::CRC32CD, (uint16_t)-1U }, |
| { Mips::CRC32CH, Mips::CRC32CH, (uint16_t)-1U }, |
| { Mips::CRC32CW, Mips::CRC32CW, (uint16_t)-1U }, |
| { Mips::CRC32D, Mips::CRC32D, (uint16_t)-1U }, |
| { Mips::CRC32H, Mips::CRC32H, (uint16_t)-1U }, |
| { Mips::CRC32W, Mips::CRC32W, (uint16_t)-1U }, |
| { Mips::DIV, Mips::DIV, Mips::DIV_MMR6 }, |
| { Mips::DIVU, Mips::DIVU, Mips::DIVU_MMR6 }, |
| { Mips::DVP, Mips::DVP, Mips::DVP_MMR6 }, |
| { Mips::EVP, Mips::EVP, Mips::EVP_MMR6 }, |
| { Mips::GINVI, Mips::GINVI, Mips::GINVI_MMR6 }, |
| { Mips::GINVT, Mips::GINVT, Mips::GINVT_MMR6 }, |
| { Mips::JIALC, Mips::JIALC, Mips::JIALC_MMR6 }, |
| { Mips::JIC, Mips::JIC, Mips::JIC_MMR6 }, |
| { Mips::LSA_R6, Mips::LSA_R6, Mips::LSA_MMR6 }, |
| { Mips::LWPC, Mips::LWPC, Mips::LWPC_MMR6 }, |
| { Mips::MOD, Mips::MOD, Mips::MOD_MMR6 }, |
| { Mips::MODU, Mips::MODU, Mips::MODU_MMR6 }, |
| { Mips::MUH, Mips::MUH, Mips::MUH_MMR6 }, |
| { Mips::MUHU, Mips::MUHU, Mips::MUHU_MMR6 }, |
| { Mips::MULU, Mips::MULU, Mips::MULU_MMR6 }, |
| { Mips::MUL_R6, Mips::MUL_R6, Mips::MUL_MMR6 }, |
| { Mips::PREF_R6, Mips::PREF_R6, Mips::PREF_MMR6 }, |
| { Mips::SELEQZ, Mips::SELEQZ, Mips::SELEQZ_MMR6 }, |
| { Mips::SELEQZ_D, Mips::SELEQZ_D, Mips::SELEQZ_D_MMR6 }, |
| { Mips::SELEQZ_S, Mips::SELEQZ_S, Mips::SELEQZ_S_MMR6 }, |
| { Mips::SELNEZ, Mips::SELNEZ, Mips::SELNEZ_MMR6 }, |
| { Mips::SELNEZ_D, Mips::SELNEZ_D, Mips::SELNEZ_D_MMR6 }, |
| { Mips::SELNEZ_S, Mips::SELNEZ_S, Mips::SELNEZ_S_MMR6 }, |
| { Mips::SEL_D, Mips::SEL_D, Mips::SEL_D_MMR6 }, |
| { Mips::SEL_S, Mips::SEL_S, Mips::SEL_S_MMR6 }, |
| }; // End of MipsR62MicroMipsR6Table |
| |
| unsigned mid; |
| unsigned start = 0; |
| unsigned end = 96; |
| while (start < end) { |
| mid = start + (end - start)/2; |
| if (Opcode == MipsR62MicroMipsR6Table[mid][0]) { |
| break; |
| } |
| if (Opcode < MipsR62MicroMipsR6Table[mid][0]) |
| end = mid; |
| else |
| start = mid + 1; |
| } |
| if (start == end) |
| return -1; // Instruction doesn't exist in this table. |
| |
| if (inArch == Arch_mipsr6) |
| return MipsR62MicroMipsR6Table[mid][1]; |
| if (inArch == Arch_micromipsr6) |
| return MipsR62MicroMipsR6Table[mid][2]; |
| return -1;} |
| |
| // Std2MicroMips |
| LLVM_READONLY |
| int Std2MicroMips(uint16_t Opcode, enum Arch inArch) { |
| static const uint16_t Std2MicroMipsTable[][3] = { |
| { Mips::ADD, Mips::ADD, Mips::ADD_MM }, |
| { Mips::ADDi, Mips::ADDi, Mips::ADDi_MM }, |
| { Mips::ADDiu, Mips::ADDiu, Mips::ADDiu_MM }, |
| { Mips::ADDu, Mips::ADDu, Mips::ADDu_MM }, |
| { Mips::AND, Mips::AND, Mips::AND_MM }, |
| { Mips::ANDi, Mips::ANDi, Mips::ANDi_MM }, |
| { Mips::BC1F, Mips::BC1F, Mips::BC1F_MM }, |
| { Mips::BC1FL, Mips::BC1FL, (uint16_t)-1U }, |
| { Mips::BC1T, Mips::BC1T, Mips::BC1T_MM }, |
| { Mips::BC1TL, Mips::BC1TL, (uint16_t)-1U }, |
| { Mips::BEQ, Mips::BEQ, Mips::BEQ_MM }, |
| { Mips::BEQL, Mips::BEQL, (uint16_t)-1U }, |
| { Mips::BGEZ, Mips::BGEZ, Mips::BGEZ_MM }, |
| { Mips::BGEZAL, Mips::BGEZAL, Mips::BGEZAL_MM }, |
| { Mips::BGEZALL, Mips::BGEZALL, (uint16_t)-1U }, |
| { Mips::BGEZL, Mips::BGEZL, (uint16_t)-1U }, |
| { Mips::BGTZ, Mips::BGTZ, Mips::BGTZ_MM }, |
| { Mips::BGTZL, Mips::BGTZL, (uint16_t)-1U }, |
| { Mips::BLEZ, Mips::BLEZ, Mips::BLEZ_MM }, |
| { Mips::BLEZL, Mips::BLEZL, (uint16_t)-1U }, |
| { Mips::BLTZ, Mips::BLTZ, Mips::BLTZ_MM }, |
| { Mips::BLTZAL, Mips::BLTZAL, Mips::BLTZAL_MM }, |
| { Mips::BLTZALL, Mips::BLTZALL, (uint16_t)-1U }, |
| { Mips::BLTZL, Mips::BLTZL, (uint16_t)-1U }, |
| { Mips::BNE, Mips::BNE, Mips::BNE_MM }, |
| { Mips::BNEL, Mips::BNEL, (uint16_t)-1U }, |
| { Mips::BREAK, Mips::BREAK, Mips::BREAK_MM }, |
| { Mips::CACHE, Mips::CACHE, Mips::CACHE_MM }, |
| { Mips::CACHEE, Mips::CACHEE, Mips::CACHEE_MM }, |
| { Mips::CEIL_W_D32, Mips::CEIL_W_D32, Mips::CEIL_W_MM }, |
| { Mips::CEIL_W_S, Mips::CEIL_W_S, Mips::CEIL_W_S_MM }, |
| { Mips::CFC1, Mips::CFC1, Mips::CFC1_MM }, |
| { Mips::CLO, Mips::CLO, Mips::CLO_MM }, |
| { Mips::CLZ, Mips::CLZ, Mips::CLZ_MM }, |
| { Mips::CTC1, Mips::CTC1, Mips::CTC1_MM }, |
| { Mips::CVT_D32_S, Mips::CVT_D32_S, Mips::CVT_D32_S_MM }, |
| { Mips::CVT_D32_W, Mips::CVT_D32_W, Mips::CVT_D32_W_MM }, |
| { Mips::CVT_L_D64, Mips::CVT_L_D64, Mips::CVT_L_D64_MM }, |
| { Mips::CVT_L_S, Mips::CVT_L_S, Mips::CVT_L_S_MM }, |
| { Mips::CVT_S_D32, Mips::CVT_S_D32, Mips::CVT_S_D32_MM }, |
| { Mips::CVT_S_W, Mips::CVT_S_W, Mips::CVT_S_W_MM }, |
| { Mips::CVT_W_D32, Mips::CVT_W_D32, Mips::CVT_W_D32_MM }, |
| { Mips::CVT_W_S, Mips::CVT_W_S, Mips::CVT_W_S_MM }, |
| { Mips::C_EQ_D32, Mips::C_EQ_D32, Mips::C_EQ_D32_MM }, |
| { Mips::C_EQ_D64, Mips::C_EQ_D64, Mips::C_EQ_D64_MM }, |
| { Mips::C_EQ_S, Mips::C_EQ_S, Mips::C_EQ_S_MM }, |
| { Mips::C_F_D32, Mips::C_F_D32, Mips::C_F_D32_MM }, |
| { Mips::C_F_D64, Mips::C_F_D64, Mips::C_F_D64_MM }, |
| { Mips::C_F_S, Mips::C_F_S, Mips::C_F_S_MM }, |
| { Mips::C_LE_D32, Mips::C_LE_D32, Mips::C_LE_D32_MM }, |
| { Mips::C_LE_D64, Mips::C_LE_D64, Mips::C_LE_D64_MM }, |
| { Mips::C_LE_S, Mips::C_LE_S, Mips::C_LE_S_MM }, |
| { Mips::C_LT_D32, Mips::C_LT_D32, Mips::C_LT_D32_MM }, |
| { Mips::C_LT_D64, Mips::C_LT_D64, Mips::C_LT_D64_MM }, |
| { Mips::C_LT_S, Mips::C_LT_S, Mips::C_LT_S_MM }, |
| { Mips::C_NGE_D32, Mips::C_NGE_D32, Mips::C_NGE_D32_MM }, |
| { Mips::C_NGE_D64, Mips::C_NGE_D64, Mips::C_NGE_D64_MM }, |
| { Mips::C_NGE_S, Mips::C_NGE_S, Mips::C_NGE_S_MM }, |
| { Mips::C_NGLE_D32, Mips::C_NGLE_D32, Mips::C_NGLE_D32_MM }, |
| { Mips::C_NGLE_D64, Mips::C_NGLE_D64, Mips::C_NGLE_D64_MM }, |
| { Mips::C_NGLE_S, Mips::C_NGLE_S, Mips::C_NGLE_S_MM }, |
| { Mips::C_NGL_D32, Mips::C_NGL_D32, Mips::C_NGL_D32_MM }, |
| { Mips::C_NGL_D64, Mips::C_NGL_D64, Mips::C_NGL_D64_MM }, |
| { Mips::C_NGL_S, Mips::C_NGL_S, Mips::C_NGL_S_MM }, |
| { Mips::C_NGT_D32, Mips::C_NGT_D32, Mips::C_NGT_D32_MM }, |
| { Mips::C_NGT_D64, Mips::C_NGT_D64, Mips::C_NGT_D64_MM }, |
| { Mips::C_NGT_S, Mips::C_NGT_S, Mips::C_NGT_S_MM }, |
| { Mips::C_OLE_D32, Mips::C_OLE_D32, Mips::C_OLE_D32_MM }, |
| { Mips::C_OLE_D64, Mips::C_OLE_D64, Mips::C_OLE_D64_MM }, |
| { Mips::C_OLE_S, Mips::C_OLE_S, Mips::C_OLE_S_MM }, |
| { Mips::C_OLT_D32, Mips::C_OLT_D32, Mips::C_OLT_D32_MM }, |
| { Mips::C_OLT_D64, Mips::C_OLT_D64, Mips::C_OLT_D64_MM }, |
| { Mips::C_OLT_S, Mips::C_OLT_S, Mips::C_OLT_S_MM }, |
| { Mips::C_SEQ_D32, Mips::C_SEQ_D32, Mips::C_SEQ_D32_MM }, |
| { Mips::C_SEQ_D64, Mips::C_SEQ_D64, Mips::C_SEQ_D64_MM }, |
| { Mips::C_SEQ_S, Mips::C_SEQ_S, Mips::C_SEQ_S_MM }, |
| { Mips::C_SF_D32, Mips::C_SF_D32, Mips::C_SF_D32_MM }, |
| { Mips::C_SF_D64, Mips::C_SF_D64, Mips::C_SF_D64_MM }, |
| { Mips::C_SF_S, Mips::C_SF_S, Mips::C_SF_S_MM }, |
| { Mips::C_UEQ_D32, Mips::C_UEQ_D32, Mips::C_UEQ_D32_MM }, |
| { Mips::C_UEQ_D64, Mips::C_UEQ_D64, Mips::C_UEQ_D64_MM }, |
| { Mips::C_UEQ_S, Mips::C_UEQ_S, Mips::C_UEQ_S_MM }, |
| { Mips::C_ULE_D32, Mips::C_ULE_D32, Mips::C_ULE_D32_MM }, |
| { Mips::C_ULE_D64, Mips::C_ULE_D64, Mips::C_ULE_D64_MM }, |
| { Mips::C_ULE_S, Mips::C_ULE_S, Mips::C_ULE_S_MM }, |
| { Mips::C_ULT_D32, Mips::C_ULT_D32, Mips::C_ULT_D32_MM }, |
| { Mips::C_ULT_D64, Mips::C_ULT_D64, Mips::C_ULT_D64_MM }, |
| { Mips::C_ULT_S, Mips::C_ULT_S, Mips::C_ULT_S_MM }, |
| { Mips::C_UN_D32, Mips::C_UN_D32, Mips::C_UN_D32_MM }, |
| { Mips::C_UN_D64, Mips::C_UN_D64, Mips::C_UN_D64_MM }, |
| { Mips::C_UN_S, Mips::C_UN_S, Mips::C_UN_S_MM }, |
| { Mips::DERET, Mips::DERET, Mips::DERET_MM }, |
| { Mips::DI, Mips::DI, Mips::DI_MM }, |
| { Mips::EHB, Mips::EHB, Mips::EHB_MM }, |
| { Mips::EI, Mips::EI, Mips::EI_MM }, |
| { Mips::ERET, Mips::ERET, Mips::ERET_MM }, |
| { Mips::ERETNC, Mips::ERETNC, (uint16_t)-1U }, |
| { Mips::EXT, Mips::EXT, Mips::EXT_MM }, |
| { Mips::FABS_D32, Mips::FABS_D32, Mips::FABS_D32_MM }, |
| { Mips::FABS_S, Mips::FABS_S, Mips::FABS_S_MM }, |
| { Mips::FADD_D32, Mips::FADD_D32, Mips::FADD_D32_MM }, |
| { Mips::FADD_S, Mips::FADD_S, Mips::FADD_S_MM }, |
| { Mips::FCMP_D32, Mips::FCMP_D32, Mips::FCMP_D32_MM }, |
| { Mips::FCMP_S32, Mips::FCMP_S32, Mips::FCMP_S32_MM }, |
| { Mips::FDIV_D32, Mips::FDIV_D32, Mips::FDIV_D32_MM }, |
| { Mips::FDIV_S, Mips::FDIV_S, Mips::FDIV_S_MM }, |
| { Mips::FLOOR_W_D32, Mips::FLOOR_W_D32, Mips::FLOOR_W_MM }, |
| { Mips::FLOOR_W_S, Mips::FLOOR_W_S, Mips::FLOOR_W_S_MM }, |
| { Mips::FMOV_D32, Mips::FMOV_D32, Mips::FMOV_D32_MM }, |
| { Mips::FMOV_S, Mips::FMOV_S, Mips::FMOV_S_MM }, |
| { Mips::FMUL_D32, Mips::FMUL_D32, Mips::FMUL_D32_MM }, |
| { Mips::FMUL_S, Mips::FMUL_S, Mips::FMUL_S_MM }, |
| { Mips::FNEG_D32, Mips::FNEG_D32, Mips::FNEG_D32_MM }, |
| { Mips::FNEG_S, Mips::FNEG_S, Mips::FNEG_S_MM }, |
| { Mips::FSQRT_D32, Mips::FSQRT_D32, Mips::FSQRT_D32_MM }, |
| { Mips::FSQRT_S, Mips::FSQRT_S, Mips::FSQRT_S_MM }, |
| { Mips::FSUB_D32, Mips::FSUB_D32, Mips::FSUB_D32_MM }, |
| { Mips::FSUB_S, Mips::FSUB_S, Mips::FSUB_S_MM }, |
| { Mips::HYPCALL, Mips::HYPCALL, Mips::HYPCALL_MM }, |
| { Mips::INS, Mips::INS, Mips::INS_MM }, |
| { Mips::J, Mips::J, Mips::J_MM }, |
| { Mips::JAL, Mips::JAL, Mips::JAL_MM }, |
| { Mips::JALX, Mips::JALX, Mips::JALX_MM }, |
| { Mips::JR, Mips::JR, Mips::JR_MM }, |
| { Mips::LB, Mips::LB, Mips::LB_MM }, |
| { Mips::LBE, Mips::LBE, Mips::LBE_MM }, |
| { Mips::LBu, Mips::LBu, Mips::LBu_MM }, |
| { Mips::LBuE, Mips::LBuE, Mips::LBuE_MM }, |
| { Mips::LDC1, Mips::LDC1, Mips::LDC1_MM }, |
| { Mips::LEA_ADDiu, Mips::LEA_ADDiu, Mips::LEA_ADDiu_MM }, |
| { Mips::LH, Mips::LH, Mips::LH_MM }, |
| { Mips::LHE, Mips::LHE, Mips::LHE_MM }, |
| { Mips::LHu, Mips::LHu, Mips::LHu_MM }, |
| { Mips::LHuE, Mips::LHuE, Mips::LHuE_MM }, |
| { Mips::LLE, Mips::LLE, Mips::LLE_MM }, |
| { Mips::LUXC1, Mips::LUXC1, Mips::LUXC1_MM }, |
| { Mips::LUi, Mips::LUi, Mips::LUi_MM }, |
| { Mips::LW, Mips::LW, Mips::LW_MM }, |
| { Mips::LWC1, Mips::LWC1, Mips::LWC1_MM }, |
| { Mips::LWE, Mips::LWE, Mips::LWE_MM }, |
| { Mips::LWL, Mips::LWL, Mips::LWL_MM }, |
| { Mips::LWLE, Mips::LWLE, Mips::LWLE_MM }, |
| { Mips::LWR, Mips::LWR, Mips::LWR_MM }, |
| { Mips::LWRE, Mips::LWRE, Mips::LWRE_MM }, |
| { Mips::LWXC1, Mips::LWXC1, Mips::LWXC1_MM }, |
| { Mips::LWu, Mips::LWu, Mips::LWU_MM }, |
| { Mips::MADD, Mips::MADD, Mips::MADD_MM }, |
| { Mips::MADDU, Mips::MADDU, Mips::MADDU_MM }, |
| { Mips::MADD_D32, Mips::MADD_D32, Mips::MADD_D32_MM }, |
| { Mips::MADD_S, Mips::MADD_S, Mips::MADD_S_MM }, |
| { Mips::MFC1, Mips::MFC1, Mips::MFC1_MM }, |
| { Mips::MFGC0, Mips::MFGC0, Mips::MFGC0_MM }, |
| { Mips::MFHC1_D32, Mips::MFHC1_D32, Mips::MFHC1_D32_MM }, |
| { Mips::MFHGC0, Mips::MFHGC0, Mips::MFHGC0_MM }, |
| { Mips::MFHI, Mips::MFHI, Mips::MFHI_MM }, |
| { Mips::MFLO, Mips::MFLO, Mips::MFLO_MM }, |
| { Mips::MOVF_D32, Mips::MOVF_D32, Mips::MOVF_D32_MM }, |
| { Mips::MOVF_I, Mips::MOVF_I, Mips::MOVF_I_MM }, |
| { Mips::MOVF_S, Mips::MOVF_S, Mips::MOVF_S_MM }, |
| { Mips::MOVN_I_D32, Mips::MOVN_I_D32, Mips::MOVN_I_D32_MM }, |
| { Mips::MOVN_I_I, Mips::MOVN_I_I, Mips::MOVN_I_MM }, |
| { Mips::MOVN_I_S, Mips::MOVN_I_S, Mips::MOVN_I_S_MM }, |
| { Mips::MOVT_D32, Mips::MOVT_D32, Mips::MOVT_D32_MM }, |
| { Mips::MOVT_I, Mips::MOVT_I, Mips::MOVT_I_MM }, |
| { Mips::MOVT_S, Mips::MOVT_S, Mips::MOVT_S_MM }, |
| { Mips::MOVZ_I_D32, Mips::MOVZ_I_D32, Mips::MOVZ_I_D32_MM }, |
| { Mips::MOVZ_I_I, Mips::MOVZ_I_I, Mips::MOVZ_I_MM }, |
| { Mips::MOVZ_I_S, Mips::MOVZ_I_S, Mips::MOVZ_I_S_MM }, |
| { Mips::MSUB, Mips::MSUB, Mips::MSUB_MM }, |
| { Mips::MSUBU, Mips::MSUBU, Mips::MSUBU_MM }, |
| { Mips::MSUB_D32, Mips::MSUB_D32, Mips::MSUB_D32_MM }, |
| { Mips::MSUB_S, Mips::MSUB_S, Mips::MSUB_S_MM }, |
| { Mips::MTC1, Mips::MTC1, Mips::MTC1_MM }, |
| { Mips::MTGC0, Mips::MTGC0, Mips::MTGC0_MM }, |
| { Mips::MTHC1_D32, Mips::MTHC1_D32, Mips::MTHC1_D32_MM }, |
| { Mips::MTHGC0, Mips::MTHGC0, Mips::MTHGC0_MM }, |
| { Mips::MTHI, Mips::MTHI, Mips::MTHI_MM }, |
| { Mips::MTLO, Mips::MTLO, Mips::MTLO_MM }, |
| { Mips::MUL, Mips::MUL, Mips::MUL_MM }, |
| { Mips::MULT, Mips::MULT, Mips::MULT_MM }, |
| { Mips::MULTu, Mips::MULTu, Mips::MULTu_MM }, |
| { Mips::NMADD_D32, Mips::NMADD_D32, Mips::NMADD_D32_MM }, |
| { Mips::NMADD_S, Mips::NMADD_S, Mips::NMADD_S_MM }, |
| { Mips::NMSUB_D32, Mips::NMSUB_D32, Mips::NMSUB_D32_MM }, |
| { Mips::NMSUB_S, Mips::NMSUB_S, Mips::NMSUB_S_MM }, |
| { Mips::NOR, Mips::NOR, Mips::NOR_MM }, |
| { Mips::OR, Mips::OR, Mips::OR_MM }, |
| { Mips::ORi, Mips::ORi, Mips::ORi_MM }, |
| { Mips::PAUSE, Mips::PAUSE, Mips::PAUSE_MM }, |
| { Mips::PREF, Mips::PREF, Mips::PREF_MM }, |
| { Mips::PREFE, Mips::PREFE, Mips::PREFE_MM }, |
| { Mips::RDHWR, Mips::RDHWR, Mips::RDHWR_MM }, |
| { Mips::RECIP_D32, Mips::RECIP_D32, Mips::RECIP_D32_MM }, |
| { Mips::RECIP_D64, Mips::RECIP_D64, Mips::RECIP_D64_MM }, |
| { Mips::RECIP_S, Mips::RECIP_S, Mips::RECIP_S_MM }, |
| { Mips::ROTR, Mips::ROTR, Mips::ROTR_MM }, |
| { Mips::ROTRV, Mips::ROTRV, Mips::ROTRV_MM }, |
| { Mips::ROUND_W_D32, Mips::ROUND_W_D32, Mips::ROUND_W_MM }, |
| { Mips::ROUND_W_S, Mips::ROUND_W_S, Mips::ROUND_W_S_MM }, |
| { Mips::RSQRT_D32, Mips::RSQRT_D32, Mips::RSQRT_D32_MM }, |
| { Mips::RSQRT_D64, Mips::RSQRT_D64, Mips::RSQRT_D64_MM }, |
| { Mips::RSQRT_S, Mips::RSQRT_S, Mips::RSQRT_S_MM }, |
| { Mips::SB, Mips::SB, Mips::SB_MM }, |
| { Mips::SBE, Mips::SBE, Mips::SBE_MM }, |
| { Mips::SCE, Mips::SCE, Mips::SCE_MM }, |
| { Mips::SDBBP, Mips::SDBBP, Mips::SDBBP_MM }, |
| { Mips::SDC1, Mips::SDC1, Mips::SDC1_MM }, |
| { Mips::SDIV, Mips::SDIV, Mips::SDIV_MM }, |
| { Mips::SEB, Mips::SEB, Mips::SEB_MM }, |
| { Mips::SEH, Mips::SEH, Mips::SEH_MM }, |
| { Mips::SH, Mips::SH, Mips::SH_MM }, |
| { Mips::SHE, Mips::SHE, Mips::SHE_MM }, |
| { Mips::SLL, Mips::SLL, Mips::SLL_MM }, |
| { Mips::SLLV, Mips::SLLV, Mips::SLLV_MM }, |
| { Mips::SLT, Mips::SLT, Mips::SLT_MM }, |
| { Mips::SLTi, Mips::SLTi, Mips::SLTi_MM }, |
| { Mips::SLTiu, Mips::SLTiu, Mips::SLTiu_MM }, |
| { Mips::SLTu, Mips::SLTu, Mips::SLTu_MM }, |
| { Mips::SRA, Mips::SRA, Mips::SRA_MM }, |
| { Mips::SRAV, Mips::SRAV, Mips::SRAV_MM }, |
| { Mips::SRL, Mips::SRL, Mips::SRL_MM }, |
| { Mips::SRLV, Mips::SRLV, Mips::SRLV_MM }, |
| { Mips::SSNOP, Mips::SSNOP, Mips::SSNOP_MM }, |
| { Mips::SUB, Mips::SUB, Mips::SUB_MM }, |
| { Mips::SUBu, Mips::SUBu, Mips::SUBu_MM }, |
| { Mips::SUXC1, Mips::SUXC1, Mips::SUXC1_MM }, |
| { Mips::SW, Mips::SW, Mips::SW_MM }, |
| { Mips::SWC1, Mips::SWC1, Mips::SWC1_MM }, |
| { Mips::SWE, Mips::SWE, Mips::SWE_MM }, |
| { Mips::SWL, Mips::SWL, Mips::SWL_MM }, |
| { Mips::SWLE, Mips::SWLE, Mips::SWLE_MM }, |
| { Mips::SWR, Mips::SWR, Mips::SWR_MM }, |
| { Mips::SWRE, Mips::SWRE, Mips::SWRE_MM }, |
| { Mips::SWXC1, Mips::SWXC1, Mips::SWXC1_MM }, |
| { Mips::SYNC, Mips::SYNC, Mips::SYNC_MM }, |
| { Mips::SYNCI, Mips::SYNCI, Mips::SYNCI_MM }, |
| { Mips::SYSCALL, Mips::SYSCALL, Mips::SYSCALL_MM }, |
| { Mips::TEQ, Mips::TEQ, Mips::TEQ_MM }, |
| { Mips::TEQI, Mips::TEQI, Mips::TEQI_MM }, |
| { Mips::TGE, Mips::TGE, Mips::TGE_MM }, |
| { Mips::TGEI, Mips::TGEI, Mips::TGEI_MM }, |
| { Mips::TGEIU, Mips::TGEIU, Mips::TGEIU_MM }, |
| { Mips::TGEU, Mips::TGEU, Mips::TGEU_MM }, |
| { Mips::TLBGINV, Mips::TLBGINV, Mips::TLBGINV_MM }, |
| { Mips::TLBGINVF, Mips::TLBGINVF, Mips::TLBGINVF_MM }, |
| { Mips::TLBGP, Mips::TLBGP, Mips::TLBGP_MM }, |
| { Mips::TLBGR, Mips::TLBGR, Mips::TLBGR_MM }, |
| { Mips::TLBGWI, Mips::TLBGWI, Mips::TLBGWI_MM }, |
| { Mips::TLBGWR, Mips::TLBGWR, Mips::TLBGWR_MM }, |
| { Mips::TLBP, Mips::TLBP, Mips::TLBP_MM }, |
| { Mips::TLBR, Mips::TLBR, Mips::TLBR_MM }, |
| { Mips::TLBWI, Mips::TLBWI, Mips::TLBWI_MM }, |
| { Mips::TLBWR, Mips::TLBWR, Mips::TLBWR_MM }, |
| { Mips::TLT, Mips::TLT, Mips::TLT_MM }, |
| { Mips::TLTI, Mips::TLTI, Mips::TLTI_MM }, |
| { Mips::TLTU, Mips::TLTU, Mips::TLTU_MM }, |
| { Mips::TNE, Mips::TNE, Mips::TNE_MM }, |
| { Mips::TNEI, Mips::TNEI, Mips::TNEI_MM }, |
| { Mips::TRUNC_W_D32, Mips::TRUNC_W_D32, Mips::TRUNC_W_MM }, |
| { Mips::TRUNC_W_S, Mips::TRUNC_W_S, Mips::TRUNC_W_S_MM }, |
| { Mips::TTLTIU, Mips::TTLTIU, Mips::TLTIU_MM }, |
| { Mips::UDIV, Mips::UDIV, Mips::UDIV_MM }, |
| { Mips::WAIT, Mips::WAIT, Mips::WAIT_MM }, |
| { Mips::WSBH, Mips::WSBH, Mips::WSBH_MM }, |
| { Mips::XOR, Mips::XOR, Mips::XOR_MM }, |
| { Mips::XORi, Mips::XORi, Mips::XORi_MM }, |
| }; // End of Std2MicroMipsTable |
| |
| unsigned mid; |
| unsigned start = 0; |
| unsigned end = 266; |
| while (start < end) { |
| mid = start + (end - start)/2; |
| if (Opcode == Std2MicroMipsTable[mid][0]) { |
| break; |
| } |
| if (Opcode < Std2MicroMipsTable[mid][0]) |
| end = mid; |
| else |
| start = mid + 1; |
| } |
| if (start == end) |
| return -1; // Instruction doesn't exist in this table. |
| |
| if (inArch == Arch_se) |
| return Std2MicroMipsTable[mid][1]; |
| if (inArch == Arch_micromips) |
| return Std2MicroMipsTable[mid][2]; |
| return -1;} |
| |
| // Std2MicroMipsR6 |
| LLVM_READONLY |
| int Std2MicroMipsR6(uint16_t Opcode, enum Arch inArch) { |
| static const uint16_t Std2MicroMipsR6Table[][3] = { |
| { Mips::ADD, Mips::ADD, Mips::ADD_MMR6 }, |
| { Mips::ADDiu, Mips::ADDiu, Mips::ADDIU_MMR6 }, |
| { Mips::ADDu, Mips::ADDu, Mips::ADDU_MMR6 }, |
| { Mips::AND, Mips::AND, Mips::AND_MMR6 }, |
| { Mips::ANDi, Mips::ANDi, Mips::ANDI_MMR6 }, |
| { Mips::BREAK, Mips::BREAK, Mips::BREAK_MMR6 }, |
| { Mips::CEIL_W_D64, Mips::CEIL_W_D64, Mips::CEIL_W_D_MMR6 }, |
| { Mips::CEIL_W_S, Mips::CEIL_W_S, Mips::CEIL_W_S_MMR6 }, |
| { Mips::CVT_W_D64, Mips::CVT_W_D64, (uint16_t)-1U }, |
| { Mips::DI, Mips::DI, Mips::DI_MMR6 }, |
| { Mips::EI, Mips::EI, Mips::EI_MMR6 }, |
| { Mips::EXT, Mips::EXT, Mips::EXT_MMR6 }, |
| { Mips::FABS_D64, Mips::FABS_D64, (uint16_t)-1U }, |
| { Mips::FLOOR_W_D64, Mips::FLOOR_W_D64, Mips::FLOOR_W_D_MMR6 }, |
| { Mips::FLOOR_W_S, Mips::FLOOR_W_S, Mips::FLOOR_W_S_MMR6 }, |
| { Mips::FMOV_D64, Mips::FMOV_D64, Mips::FMOV_D_MMR6 }, |
| { Mips::FNEG_D64, Mips::FNEG_D64, (uint16_t)-1U }, |
| { Mips::FSQRT_D64, Mips::FSQRT_D64, (uint16_t)-1U }, |
| { Mips::FSQRT_S, Mips::FSQRT_S, (uint16_t)-1U }, |
| { Mips::INS, Mips::INS, Mips::INS_MMR6 }, |
| { Mips::LDC1, Mips::LDC1, (uint16_t)-1U }, |
| { Mips::LDC164, Mips::LDC164, Mips::LDC1_D64_MMR6 }, |
| { Mips::LDC2, Mips::LDC2, Mips::LDC2_MMR6 }, |
| { Mips::LW, Mips::LW, Mips::LW_MMR6 }, |
| { Mips::LWC2, Mips::LWC2, Mips::LWC2_MMR6 }, |
| { Mips::MFC1, Mips::MFC1, Mips::MFC1_MMR6 }, |
| { Mips::MTC1, Mips::MTC1, Mips::MTC1_MMR6 }, |
| { Mips::MTHC1_D32, Mips::MTHC1_D32, (uint16_t)-1U }, |
| { Mips::NOR, Mips::NOR, Mips::NOR_MMR6 }, |
| { Mips::OR, Mips::OR, Mips::OR_MMR6 }, |
| { Mips::ORi, Mips::ORi, Mips::ORI_MMR6 }, |
| { Mips::PAUSE, Mips::PAUSE, Mips::PAUSE_MMR6 }, |
| { Mips::ROUND_W_D64, Mips::ROUND_W_D64, Mips::ROUND_W_D_MMR6 }, |
| { Mips::ROUND_W_S, Mips::ROUND_W_S, Mips::ROUND_W_S_MMR6 }, |
| { Mips::SB, Mips::SB, Mips::SB_MMR6 }, |
| { Mips::SDC164, Mips::SDC164, Mips::SDC1_D64_MMR6 }, |
| { Mips::SDC2, Mips::SDC2, Mips::SDC2_MMR6 }, |
| { Mips::SEB, Mips::SEB, (uint16_t)-1U }, |
| { Mips::SEH, Mips::SEH, (uint16_t)-1U }, |
| { Mips::SSNOP, Mips::SSNOP, Mips::SSNOP_MMR6 }, |
| { Mips::SUB, Mips::SUB, Mips::SUB_MMR6 }, |
| { Mips::SUBu, Mips::SUBu, Mips::SUBU_MMR6 }, |
| { Mips::SW, Mips::SW, Mips::SW_MMR6 }, |
| { Mips::SWC2, Mips::SWC2, Mips::SWC2_MMR6 }, |
| { Mips::SYNC, Mips::SYNC, Mips::SYNC_MMR6 }, |
| { Mips::SYNCI, Mips::SYNCI, Mips::SYNCI_MMR6 }, |
| { Mips::TRUNC_W_D64, Mips::TRUNC_W_D64, Mips::TRUNC_W_D_MMR6 }, |
| { Mips::TRUNC_W_S, Mips::TRUNC_W_S, Mips::TRUNC_W_S_MMR6 }, |
| { Mips::WAIT, Mips::WAIT, Mips::WAIT_MMR6 }, |
| { Mips::XOR, Mips::XOR, Mips::XOR_MMR6 }, |
| { Mips::XORi, Mips::XORi, Mips::XORI_MMR6 }, |
| }; // End of Std2MicroMipsR6Table |
| |
| unsigned mid; |
| unsigned start = 0; |
| unsigned end = 51; |
| while (start < end) { |
| mid = start + (end - start)/2; |
| if (Opcode == Std2MicroMipsR6Table[mid][0]) { |
| break; |
| } |
| if (Opcode < Std2MicroMipsR6Table[mid][0]) |
| end = mid; |
| else |
| start = mid + 1; |
| } |
| if (start == end) |
| return -1; // Instruction doesn't exist in this table. |
| |
| if (inArch == Arch_se) |
| return Std2MicroMipsR6Table[mid][1]; |
| if (inArch == Arch_micromipsr6) |
| return Std2MicroMipsR6Table[mid][2]; |
| return -1;} |
| |
| } // end namespace Mips |
| } // end namespace llvm |
| #endif // GET_INSTRMAP_INFO |
| |
