| /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
| |* *| |
| |* Machine Code Emitter *| |
| |* *| |
| |* Automatically generated file, do not edit! *| |
| |* *| |
| \*===----------------------------------------------------------------------===*/ |
| |
| uint64_t AArch64MCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI, |
| SmallVectorImpl<MCFixup> &Fixups, |
| const MCSubtargetInfo &STI) const { |
| static const uint64_t InstBits[] = { |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(0), |
| UINT64_C(68591616), // ABS_ZPmZ_B |
| UINT64_C(81174528), // ABS_ZPmZ_D |
| UINT64_C(72785920), // ABS_ZPmZ_H |
| UINT64_C(76980224), // ABS_ZPmZ_S |
| UINT64_C(1310767104), // ABSv16i8 |
| UINT64_C(1591785472), // ABSv1i64 |
| UINT64_C(245413888), // ABSv2i32 |
| UINT64_C(1323350016), // ABSv2i64 |
| UINT64_C(241219584), // ABSv4i16 |
| UINT64_C(1319155712), // ABSv4i32 |
| UINT64_C(1314961408), // ABSv8i16 |
| UINT64_C(237025280), // ABSv8i8 |
| UINT64_C(1161875456), // ADCLB_ZZZ_D |
| UINT64_C(1157681152), // ADCLB_ZZZ_S |
| UINT64_C(1161876480), // ADCLT_ZZZ_D |
| UINT64_C(1157682176), // ADCLT_ZZZ_S |
| UINT64_C(973078528), // ADCSWr |
| UINT64_C(3120562176), // ADCSXr |
| UINT64_C(436207616), // ADCWr |
| UINT64_C(2583691264), // ADCXr |
| UINT64_C(2441084928), // ADDG |
| UINT64_C(1163943936), // ADDHNB_ZZZ_B |
| UINT64_C(1168138240), // ADDHNB_ZZZ_H |
| UINT64_C(1172332544), // ADDHNB_ZZZ_S |
| UINT64_C(1163944960), // ADDHNT_ZZZ_B |
| UINT64_C(1168139264), // ADDHNT_ZZZ_H |
| UINT64_C(1172333568), // ADDHNT_ZZZ_S |
| UINT64_C(245383168), // ADDHNv2i64_v2i32 |
| UINT64_C(1319124992), // ADDHNv2i64_v4i32 |
| UINT64_C(241188864), // ADDHNv4i32_v4i16 |
| UINT64_C(1314930688), // ADDHNv4i32_v8i16 |
| UINT64_C(1310736384), // ADDHNv8i16_v16i8 |
| UINT64_C(236994560), // ADDHNv8i16_v8i8 |
| UINT64_C(73420800), // ADDPL_XXI |
| UINT64_C(1142005760), // ADDP_ZPmZ_B |
| UINT64_C(1154588672), // ADDP_ZPmZ_D |
| UINT64_C(1146200064), // ADDP_ZPmZ_H |
| UINT64_C(1150394368), // ADDP_ZPmZ_S |
| UINT64_C(1310768128), // ADDPv16i8 |
| UINT64_C(245414912), // ADDPv2i32 |
| UINT64_C(1323351040), // ADDPv2i64 |
| UINT64_C(1592899584), // ADDPv2i64p |
| UINT64_C(241220608), // ADDPv4i16 |
| UINT64_C(1319156736), // ADDPv4i32 |
| UINT64_C(1314962432), // ADDPv8i16 |
| UINT64_C(237026304), // ADDPv8i8 |
| UINT64_C(822083584), // ADDSWri |
| UINT64_C(0), // ADDSWrr |
| UINT64_C(721420288), // ADDSWrs |
| UINT64_C(723517440), // ADDSWrx |
| UINT64_C(2969567232), // ADDSXri |
| UINT64_C(0), // ADDSXrr |
| UINT64_C(2868903936), // ADDSXrs |
| UINT64_C(2871001088), // ADDSXrx |
| UINT64_C(2871025664), // ADDSXrx64 |
| UINT64_C(69226496), // ADDVL_XXI |
| UINT64_C(1311881216), // ADDVv16i8v |
| UINT64_C(242333696), // ADDVv4i16v |
| UINT64_C(1320269824), // ADDVv4i32v |
| UINT64_C(1316075520), // ADDVv8i16v |
| UINT64_C(238139392), // ADDVv8i8v |
| UINT64_C(285212672), // ADDWri |
| UINT64_C(0), // ADDWrr |
| UINT64_C(184549376), // ADDWrs |
| UINT64_C(186646528), // ADDWrx |
| UINT64_C(2432696320), // ADDXri |
| UINT64_C(0), // ADDXrr |
| UINT64_C(2332033024), // ADDXrs |
| UINT64_C(2334130176), // ADDXrx |
| UINT64_C(2334154752), // ADDXrx64 |
| UINT64_C(622903296), // ADD_ZI_B |
| UINT64_C(635486208), // ADD_ZI_D |
| UINT64_C(627097600), // ADD_ZI_H |
| UINT64_C(631291904), // ADD_ZI_S |
| UINT64_C(67108864), // ADD_ZPmZ_B |
| UINT64_C(79691776), // ADD_ZPmZ_D |
| UINT64_C(71303168), // ADD_ZPmZ_H |
| UINT64_C(75497472), // ADD_ZPmZ_S |
| UINT64_C(69206016), // ADD_ZZZ_B |
| UINT64_C(81788928), // ADD_ZZZ_D |
| UINT64_C(73400320), // ADD_ZZZ_H |
| UINT64_C(77594624), // ADD_ZZZ_S |
| UINT64_C(0), // ADDlowTLS |
| UINT64_C(1310753792), // ADDv16i8 |
| UINT64_C(1591772160), // ADDv1i64 |
| UINT64_C(245400576), // ADDv2i32 |
| UINT64_C(1323336704), // ADDv2i64 |
| UINT64_C(241206272), // ADDv4i16 |
| UINT64_C(1319142400), // ADDv4i32 |
| UINT64_C(1314948096), // ADDv8i16 |
| UINT64_C(237011968), // ADDv8i8 |
| UINT64_C(0), // ADJCALLSTACKDOWN |
| UINT64_C(0), // ADJCALLSTACKUP |
| UINT64_C(268435456), // ADR |
| UINT64_C(2415919104), // ADRP |
| UINT64_C(81829888), // ADR_LSL_ZZZ_D_0 |
| UINT64_C(81830912), // ADR_LSL_ZZZ_D_1 |
| UINT64_C(81831936), // ADR_LSL_ZZZ_D_2 |
| UINT64_C(81832960), // ADR_LSL_ZZZ_D_3 |
| UINT64_C(77635584), // ADR_LSL_ZZZ_S_0 |
| UINT64_C(77636608), // ADR_LSL_ZZZ_S_1 |
| UINT64_C(77637632), // ADR_LSL_ZZZ_S_2 |
| UINT64_C(77638656), // ADR_LSL_ZZZ_S_3 |
| UINT64_C(69246976), // ADR_SXTW_ZZZ_D_0 |
| UINT64_C(69248000), // ADR_SXTW_ZZZ_D_1 |
| UINT64_C(69249024), // ADR_SXTW_ZZZ_D_2 |
| UINT64_C(69250048), // ADR_SXTW_ZZZ_D_3 |
| UINT64_C(73441280), // ADR_UXTW_ZZZ_D_0 |
| UINT64_C(73442304), // ADR_UXTW_ZZZ_D_1 |
| UINT64_C(73443328), // ADR_UXTW_ZZZ_D_2 |
| UINT64_C(73444352), // ADR_UXTW_ZZZ_D_3 |
| UINT64_C(1159914496), // AESD_ZZZ_B |
| UINT64_C(1311266816), // AESDrr |
| UINT64_C(1159913472), // AESE_ZZZ_B |
| UINT64_C(1311262720), // AESErr |
| UINT64_C(1159783424), // AESIMC_ZZ_B |
| UINT64_C(1311275008), // AESIMCrr |
| UINT64_C(0), // AESIMCrrTied |
| UINT64_C(1159782400), // AESMC_ZZ_B |
| UINT64_C(1311270912), // AESMCrr |
| UINT64_C(0), // AESMCrrTied |
| UINT64_C(1912602624), // ANDSWri |
| UINT64_C(0), // ANDSWrr |
| UINT64_C(1778384896), // ANDSWrs |
| UINT64_C(4060086272), // ANDSXri |
| UINT64_C(0), // ANDSXrr |
| UINT64_C(3925868544), // ANDSXrs |
| UINT64_C(624967680), // ANDS_PPzPP |
| UINT64_C(68820992), // ANDV_VPZ_B |
| UINT64_C(81403904), // ANDV_VPZ_D |
| UINT64_C(73015296), // ANDV_VPZ_H |
| UINT64_C(77209600), // ANDV_VPZ_S |
| UINT64_C(301989888), // ANDWri |
| UINT64_C(0), // ANDWrr |
| UINT64_C(167772160), // ANDWrs |
| UINT64_C(2449473536), // ANDXri |
| UINT64_C(0), // ANDXrr |
| UINT64_C(2315255808), // ANDXrs |
| UINT64_C(620773376), // AND_PPzPP |
| UINT64_C(92274688), // AND_ZI |
| UINT64_C(68812800), // AND_ZPmZ_B |
| UINT64_C(81395712), // AND_ZPmZ_D |
| UINT64_C(73007104), // AND_ZPmZ_H |
| UINT64_C(77201408), // AND_ZPmZ_S |
| UINT64_C(69218304), // AND_ZZZ |
| UINT64_C(1310727168), // ANDv16i8 |
| UINT64_C(236985344), // ANDv8i8 |
| UINT64_C(67404032), // ASRD_ZPmI_B |
| UINT64_C(75792384), // ASRD_ZPmI_D |
| UINT64_C(67404288), // ASRD_ZPmI_H |
| UINT64_C(71598080), // ASRD_ZPmI_S |
| UINT64_C(68452352), // ASRR_ZPmZ_B |
| UINT64_C(81035264), // ASRR_ZPmZ_D |
| UINT64_C(72646656), // ASRR_ZPmZ_H |
| UINT64_C(76840960), // ASRR_ZPmZ_S |
| UINT64_C(448800768), // ASRVWr |
| UINT64_C(2596284416), // ASRVXr |
| UINT64_C(68714496), // ASR_WIDE_ZPmZ_B |
| UINT64_C(72908800), // ASR_WIDE_ZPmZ_H |
| UINT64_C(77103104), // ASR_WIDE_ZPmZ_S |
| UINT64_C(69238784), // ASR_WIDE_ZZZ_B |
| UINT64_C(73433088), // ASR_WIDE_ZZZ_H |
| UINT64_C(77627392), // ASR_WIDE_ZZZ_S |
| UINT64_C(67141888), // ASR_ZPmI_B |
| UINT64_C(75530240), // ASR_ZPmI_D |
| UINT64_C(67142144), // ASR_ZPmI_H |
| UINT64_C(71335936), // ASR_ZPmI_S |
| UINT64_C(68190208), // ASR_ZPmZ_B |
| UINT64_C(80773120), // ASR_ZPmZ_D |
| UINT64_C(72384512), // ASR_ZPmZ_H |
| UINT64_C(76578816), // ASR_ZPmZ_S |
| UINT64_C(69767168), // ASR_ZZI_B |
| UINT64_C(77631488), // ASR_ZZI_D |
| UINT64_C(70291456), // ASR_ZZI_H |
| UINT64_C(73437184), // ASR_ZZI_S |
| UINT64_C(3670087680), // AUTDA |
| UINT64_C(3670088704), // AUTDB |
| UINT64_C(3670096864), // AUTDZA |
| UINT64_C(3670097888), // AUTDZB |
| UINT64_C(3670085632), // AUTIA |
| UINT64_C(3573752223), // AUTIA1716 |
| UINT64_C(3573752767), // AUTIASP |
| UINT64_C(3573752735), // AUTIAZ |
| UINT64_C(3670086656), // AUTIB |
| UINT64_C(3573752287), // AUTIB1716 |
| UINT64_C(3573752831), // AUTIBSP |
| UINT64_C(3573752799), // AUTIBZ |
| UINT64_C(3670094816), // AUTIZA |
| UINT64_C(3670095840), // AUTIZB |
| UINT64_C(3573563487), // AXFLAG |
| UINT64_C(335544320), // B |
| UINT64_C(3458203648), // BCAX |
| UINT64_C(73414656), // BCAX_ZZZZ_D |
| UINT64_C(1157673984), // BDEP_ZZZ_B |
| UINT64_C(1170256896), // BDEP_ZZZ_D |
| UINT64_C(1161868288), // BDEP_ZZZ_H |
| UINT64_C(1166062592), // BDEP_ZZZ_S |
| UINT64_C(1157672960), // BEXT_ZZZ_B |
| UINT64_C(1170255872), // BEXT_ZZZ_D |
| UINT64_C(1161867264), // BEXT_ZZZ_H |
| UINT64_C(1166061568), // BEXT_ZZZ_S |
| UINT64_C(855638016), // BFMWri |
| UINT64_C(3007315968), // BFMXri |
| UINT64_C(1157675008), // BGRP_ZZZ_B |
| UINT64_C(1170257920), // BGRP_ZZZ_D |
| UINT64_C(1161869312), // BGRP_ZZZ_H |
| UINT64_C(1166063616), // BGRP_ZZZ_S |
| UINT64_C(0), // BICSWrr |
| UINT64_C(1780482048), // BICSWrs |
| UINT64_C(0), // BICSXrr |
| UINT64_C(3927965696), // BICSXrs |
| UINT64_C(624967696), // BICS_PPzPP |
| UINT64_C(0), // BICWrr |
| UINT64_C(169869312), // BICWrs |
| UINT64_C(0), // BICXrr |
| UINT64_C(2317352960), // BICXrs |
| UINT64_C(620773392), // BIC_PPzPP |
| UINT64_C(68878336), // BIC_ZPmZ_B |
| UINT64_C(81461248), // BIC_ZPmZ_D |
| UINT64_C(73072640), // BIC_ZPmZ_H |
| UINT64_C(77266944), // BIC_ZPmZ_S |
| UINT64_C(81801216), // BIC_ZZZ |
| UINT64_C(1314921472), // BICv16i8 |
| UINT64_C(788534272), // BICv2i32 |
| UINT64_C(788567040), // BICv4i16 |
| UINT64_C(1862276096), // BICv4i32 |
| UINT64_C(1862308864), // BICv8i16 |
| UINT64_C(241179648), // BICv8i8 |
| UINT64_C(1860180992), // BIFv16i8 |
| UINT64_C(786439168), // BIFv8i8 |
| UINT64_C(1855986688), // BITv16i8 |
| UINT64_C(782244864), // BITv8i8 |
| UINT64_C(2483027968), // BL |
| UINT64_C(3594452992), // BLR |
| UINT64_C(3611232256), // BLRAA |
| UINT64_C(3594455071), // BLRAAZ |
| UINT64_C(3611233280), // BLRAB |
| UINT64_C(3594456095), // BLRABZ |
| UINT64_C(3592355840), // BR |
| UINT64_C(3609135104), // BRAA |
| UINT64_C(3592357919), // BRAAZ |
| UINT64_C(3609136128), // BRAB |
| UINT64_C(3592358943), // BRABZ |
| UINT64_C(3558866944), // BRK |
| UINT64_C(626016256), // BRKAS_PPzP |
| UINT64_C(621821968), // BRKA_PPmP |
| UINT64_C(621821952), // BRKA_PPzP |
| UINT64_C(634404864), // BRKBS_PPzP |
| UINT64_C(630210576), // BRKB_PPmP |
| UINT64_C(630210560), // BRKB_PPzP |
| UINT64_C(626540544), // BRKNS_PPzP |
| UINT64_C(622346240), // BRKN_PPzP |
| UINT64_C(625000448), // BRKPAS_PPzPP |
| UINT64_C(620806144), // BRKPA_PPzPP |
| UINT64_C(625000464), // BRKPBS_PPzPP |
| UINT64_C(620806160), // BRKPB_PPzPP |
| UINT64_C(73415680), // BSL1N_ZZZZ_D |
| UINT64_C(77609984), // BSL2N_ZZZZ_D |
| UINT64_C(69221376), // BSL_ZZZZ_D |
| UINT64_C(1851792384), // BSLv16i8 |
| UINT64_C(778050560), // BSLv8i8 |
| UINT64_C(1409286144), // Bcc |
| UINT64_C(1157683200), // CADD_ZZI_B |
| UINT64_C(1170266112), // CADD_ZZI_D |
| UINT64_C(1161877504), // CADD_ZZI_H |
| UINT64_C(1166071808), // CADD_ZZI_S |
| UINT64_C(148929536), // CASAB |
| UINT64_C(1222671360), // CASAH |
| UINT64_C(148962304), // CASALB |
| UINT64_C(1222704128), // CASALH |
| UINT64_C(2296445952), // CASALW |
| UINT64_C(3370187776), // CASALX |
| UINT64_C(2296413184), // CASAW |
| UINT64_C(3370155008), // CASAX |
| UINT64_C(144735232), // CASB |
| UINT64_C(1218477056), // CASH |
| UINT64_C(144768000), // CASLB |
| UINT64_C(1218509824), // CASLH |
| UINT64_C(2292251648), // CASLW |
| UINT64_C(3365993472), // CASLX |
| UINT64_C(140573696), // CASPALW |
| UINT64_C(1214315520), // CASPALX |
| UINT64_C(140540928), // CASPAW |
| UINT64_C(1214282752), // CASPAX |
| UINT64_C(136379392), // CASPLW |
| UINT64_C(1210121216), // CASPLX |
| UINT64_C(136346624), // CASPW |
| UINT64_C(1210088448), // CASPX |
| UINT64_C(2292218880), // CASW |
| UINT64_C(3365960704), // CASX |
| UINT64_C(0), // CATCHPAD |
| UINT64_C(889192448), // CBNZW |
| UINT64_C(3036676096), // CBNZX |
| UINT64_C(872415232), // CBZW |
| UINT64_C(3019898880), // CBZX |
| UINT64_C(977274880), // CCMNWi |
| UINT64_C(977272832), // CCMNWr |
| UINT64_C(3124758528), // CCMNXi |
| UINT64_C(3124756480), // CCMNXr |
| UINT64_C(2051016704), // CCMPWi |
| UINT64_C(2051014656), // CCMPWr |
| UINT64_C(4198500352), // CCMPXi |
| UINT64_C(4198498304), // CCMPXr |
| UINT64_C(1155547136), // CDOT_ZZZI_D |
| UINT64_C(1151352832), // CDOT_ZZZI_S |
| UINT64_C(1153437696), // CDOT_ZZZ_D |
| UINT64_C(1149243392), // CDOT_ZZZ_S |
| UINT64_C(3573563423), // CFINV |
| UINT64_C(87072768), // CLASTA_RPZ_B |
| UINT64_C(99655680), // CLASTA_RPZ_D |
| UINT64_C(91267072), // CLASTA_RPZ_H |
| UINT64_C(95461376), // CLASTA_RPZ_S |
| UINT64_C(86671360), // CLASTA_VPZ_B |
| UINT64_C(99254272), // CLASTA_VPZ_D |
| UINT64_C(90865664), // CLASTA_VPZ_H |
| UINT64_C(95059968), // CLASTA_VPZ_S |
| UINT64_C(86540288), // CLASTA_ZPZ_B |
| UINT64_C(99123200), // CLASTA_ZPZ_D |
| UINT64_C(90734592), // CLASTA_ZPZ_H |
| UINT64_C(94928896), // CLASTA_ZPZ_S |
| UINT64_C(87138304), // CLASTB_RPZ_B |
| UINT64_C(99721216), // CLASTB_RPZ_D |
| UINT64_C(91332608), // CLASTB_RPZ_H |
| UINT64_C(95526912), // CLASTB_RPZ_S |
| UINT64_C(86736896), // CLASTB_VPZ_B |
| UINT64_C(99319808), // CLASTB_VPZ_D |
| UINT64_C(90931200), // CLASTB_VPZ_H |
| UINT64_C(95125504), // CLASTB_VPZ_S |
| UINT64_C(86605824), // CLASTB_ZPZ_B |
| UINT64_C(99188736), // CLASTB_ZPZ_D |
| UINT64_C(90800128), // CLASTB_ZPZ_H |
| UINT64_C(94994432), // CLASTB_ZPZ_S |
| UINT64_C(3573755999), // CLREX |
| UINT64_C(1522537472), // CLSWr |
| UINT64_C(3670021120), // CLSXr |
| UINT64_C(68722688), // CLS_ZPmZ_B |
| UINT64_C(81305600), // CLS_ZPmZ_D |
| UINT64_C(72916992), // CLS_ZPmZ_H |
| UINT64_C(77111296), // CLS_ZPmZ_S |
| UINT64_C(1310738432), // CLSv16i8 |
| UINT64_C(245385216), // CLSv2i32 |
| UINT64_C(241190912), // CLSv4i16 |
| UINT64_C(1319127040), // CLSv4i32 |
| UINT64_C(1314932736), // CLSv8i16 |
| UINT64_C(236996608), // CLSv8i8 |
| UINT64_C(1522536448), // CLZWr |
| UINT64_C(3670020096), // CLZXr |
| UINT64_C(68788224), // CLZ_ZPmZ_B |
| UINT64_C(81371136), // CLZ_ZPmZ_D |
| UINT64_C(72982528), // CLZ_ZPmZ_H |
| UINT64_C(77176832), // CLZ_ZPmZ_S |
| UINT64_C(1847609344), // CLZv16i8 |
| UINT64_C(782256128), // CLZv2i32 |
| UINT64_C(778061824), // CLZv4i16 |
| UINT64_C(1855997952), // CLZv4i32 |
| UINT64_C(1851803648), // CLZv8i16 |
| UINT64_C(773867520), // CLZv8i8 |
| UINT64_C(1847626752), // CMEQv16i8 |
| UINT64_C(1310758912), // CMEQv16i8rz |
| UINT64_C(2128645120), // CMEQv1i64 |
| UINT64_C(1591777280), // CMEQv1i64rz |
| UINT64_C(782273536), // CMEQv2i32 |
| UINT64_C(245405696), // CMEQv2i32rz |
| UINT64_C(1860209664), // CMEQv2i64 |
| UINT64_C(1323341824), // CMEQv2i64rz |
| UINT64_C(778079232), // CMEQv4i16 |
| UINT64_C(241211392), // CMEQv4i16rz |
| UINT64_C(1856015360), // CMEQv4i32 |
| UINT64_C(1319147520), // CMEQv4i32rz |
| UINT64_C(1851821056), // CMEQv8i16 |
| UINT64_C(1314953216), // CMEQv8i16rz |
| UINT64_C(773884928), // CMEQv8i8 |
| UINT64_C(237017088), // CMEQv8i8rz |
| UINT64_C(1310735360), // CMGEv16i8 |
| UINT64_C(1847625728), // CMGEv16i8rz |
| UINT64_C(1591753728), // CMGEv1i64 |
| UINT64_C(2128644096), // CMGEv1i64rz |
| UINT64_C(245382144), // CMGEv2i32 |
| UINT64_C(782272512), // CMGEv2i32rz |
| UINT64_C(1323318272), // CMGEv2i64 |
| UINT64_C(1860208640), // CMGEv2i64rz |
| UINT64_C(241187840), // CMGEv4i16 |
| UINT64_C(778078208), // CMGEv4i16rz |
| UINT64_C(1319123968), // CMGEv4i32 |
| UINT64_C(1856014336), // CMGEv4i32rz |
| UINT64_C(1314929664), // CMGEv8i16 |
| UINT64_C(1851820032), // CMGEv8i16rz |
| UINT64_C(236993536), // CMGEv8i8 |
| UINT64_C(773883904), // CMGEv8i8rz |
| UINT64_C(1310733312), // CMGTv16i8 |
| UINT64_C(1310754816), // CMGTv16i8rz |
| UINT64_C(1591751680), // CMGTv1i64 |
| UINT64_C(1591773184), // CMGTv1i64rz |
| UINT64_C(245380096), // CMGTv2i32 |
| UINT64_C(245401600), // CMGTv2i32rz |
| UINT64_C(1323316224), // CMGTv2i64 |
| UINT64_C(1323337728), // CMGTv2i64rz |
| UINT64_C(241185792), // CMGTv4i16 |
| UINT64_C(241207296), // CMGTv4i16rz |
| UINT64_C(1319121920), // CMGTv4i32 |
| UINT64_C(1319143424), // CMGTv4i32rz |
| UINT64_C(1314927616), // CMGTv8i16 |
| UINT64_C(1314949120), // CMGTv8i16rz |
| UINT64_C(236991488), // CMGTv8i8 |
| UINT64_C(237012992), // CMGTv8i8rz |
| UINT64_C(1847604224), // CMHIv16i8 |
| UINT64_C(2128622592), // CMHIv1i64 |
| UINT64_C(782251008), // CMHIv2i32 |
| UINT64_C(1860187136), // CMHIv2i64 |
| UINT64_C(778056704), // CMHIv4i16 |
| UINT64_C(1855992832), // CMHIv4i32 |
| UINT64_C(1851798528), // CMHIv8i16 |
| UINT64_C(773862400), // CMHIv8i8 |
| UINT64_C(1847606272), // CMHSv16i8 |
| UINT64_C(2128624640), // CMHSv1i64 |
| UINT64_C(782253056), // CMHSv2i32 |
| UINT64_C(1860189184), // CMHSv2i64 |
| UINT64_C(778058752), // CMHSv4i16 |
| UINT64_C(1855994880), // CMHSv4i32 |
| UINT64_C(1851800576), // CMHSv8i16 |
| UINT64_C(773864448), // CMHSv8i8 |
| UINT64_C(1151361024), // CMLA_ZZZI_H |
| UINT64_C(1155555328), // CMLA_ZZZI_S |
| UINT64_C(1140858880), // CMLA_ZZZ_B |
| UINT64_C(1153441792), // CMLA_ZZZ_D |
| UINT64_C(1145053184), // CMLA_ZZZ_H |
| UINT64_C(1149247488), // CMLA_ZZZ_S |
| UINT64_C(1847629824), // CMLEv16i8rz |
| UINT64_C(2128648192), // CMLEv1i64rz |
| UINT64_C(782276608), // CMLEv2i32rz |
| UINT64_C(1860212736), // CMLEv2i64rz |
| UINT64_C(778082304), // CMLEv4i16rz |
| UINT64_C(1856018432), // CMLEv4i32rz |
| UINT64_C(1851824128), // CMLEv8i16rz |
| UINT64_C(773888000), // CMLEv8i8rz |
| UINT64_C(1310763008), // CMLTv16i8rz |
| UINT64_C(1591781376), // CMLTv1i64rz |
| UINT64_C(245409792), // CMLTv2i32rz |
| UINT64_C(1323345920), // CMLTv2i64rz |
| UINT64_C(241215488), // CMLTv4i16rz |
| UINT64_C(1319151616), // CMLTv4i32rz |
| UINT64_C(1314957312), // CMLTv8i16rz |
| UINT64_C(237021184), // CMLTv8i8rz |
| UINT64_C(620789760), // CMPEQ_PPzZI_B |
| UINT64_C(633372672), // CMPEQ_PPzZI_D |
| UINT64_C(624984064), // CMPEQ_PPzZI_H |
| UINT64_C(629178368), // CMPEQ_PPzZI_S |
| UINT64_C(604020736), // CMPEQ_PPzZZ_B |
| UINT64_C(616603648), // CMPEQ_PPzZZ_D |
| UINT64_C(608215040), // CMPEQ_PPzZZ_H |
| UINT64_C(612409344), // CMPEQ_PPzZZ_S |
| UINT64_C(603987968), // CMPEQ_WIDE_PPzZZ_B |
| UINT64_C(608182272), // CMPEQ_WIDE_PPzZZ_H |
| UINT64_C(612376576), // CMPEQ_WIDE_PPzZZ_S |
| UINT64_C(620756992), // CMPGE_PPzZI_B |
| UINT64_C(633339904), // CMPGE_PPzZI_D |
| UINT64_C(624951296), // CMPGE_PPzZI_H |
| UINT64_C(629145600), // CMPGE_PPzZI_S |
| UINT64_C(604012544), // CMPGE_PPzZZ_B |
| UINT64_C(616595456), // CMPGE_PPzZZ_D |
| UINT64_C(608206848), // CMPGE_PPzZZ_H |
| UINT64_C(612401152), // CMPGE_PPzZZ_S |
| UINT64_C(603996160), // CMPGE_WIDE_PPzZZ_B |
| UINT64_C(608190464), // CMPGE_WIDE_PPzZZ_H |
| UINT64_C(612384768), // CMPGE_WIDE_PPzZZ_S |
| UINT64_C(620757008), // CMPGT_PPzZI_B |
| UINT64_C(633339920), // CMPGT_PPzZI_D |
| UINT64_C(624951312), // CMPGT_PPzZI_H |
| UINT64_C(629145616), // CMPGT_PPzZI_S |
| UINT64_C(604012560), // CMPGT_PPzZZ_B |
| UINT64_C(616595472), // CMPGT_PPzZZ_D |
| UINT64_C(608206864), // CMPGT_PPzZZ_H |
| UINT64_C(612401168), // CMPGT_PPzZZ_S |
| UINT64_C(603996176), // CMPGT_WIDE_PPzZZ_B |
| UINT64_C(608190480), // CMPGT_WIDE_PPzZZ_H |
| UINT64_C(612384784), // CMPGT_WIDE_PPzZZ_S |
| UINT64_C(606076944), // CMPHI_PPzZI_B |
| UINT64_C(618659856), // CMPHI_PPzZI_D |
| UINT64_C(610271248), // CMPHI_PPzZI_H |
| UINT64_C(614465552), // CMPHI_PPzZI_S |
| UINT64_C(603979792), // CMPHI_PPzZZ_B |
| UINT64_C(616562704), // CMPHI_PPzZZ_D |
| UINT64_C(608174096), // CMPHI_PPzZZ_H |
| UINT64_C(612368400), // CMPHI_PPzZZ_S |
| UINT64_C(604028944), // CMPHI_WIDE_PPzZZ_B |
| UINT64_C(608223248), // CMPHI_WIDE_PPzZZ_H |
| UINT64_C(612417552), // CMPHI_WIDE_PPzZZ_S |
| UINT64_C(606076928), // CMPHS_PPzZI_B |
| UINT64_C(618659840), // CMPHS_PPzZI_D |
| UINT64_C(610271232), // CMPHS_PPzZI_H |
| UINT64_C(614465536), // CMPHS_PPzZI_S |
| UINT64_C(603979776), // CMPHS_PPzZZ_B |
| UINT64_C(616562688), // CMPHS_PPzZZ_D |
| UINT64_C(608174080), // CMPHS_PPzZZ_H |
| UINT64_C(612368384), // CMPHS_PPzZZ_S |
| UINT64_C(604028928), // CMPHS_WIDE_PPzZZ_B |
| UINT64_C(608223232), // CMPHS_WIDE_PPzZZ_H |
| UINT64_C(612417536), // CMPHS_WIDE_PPzZZ_S |
| UINT64_C(620765200), // CMPLE_PPzZI_B |
| UINT64_C(633348112), // CMPLE_PPzZI_D |
| UINT64_C(624959504), // CMPLE_PPzZI_H |
| UINT64_C(629153808), // CMPLE_PPzZI_S |
| UINT64_C(604004368), // CMPLE_WIDE_PPzZZ_B |
| UINT64_C(608198672), // CMPLE_WIDE_PPzZZ_H |
| UINT64_C(612392976), // CMPLE_WIDE_PPzZZ_S |
| UINT64_C(606085120), // CMPLO_PPzZI_B |
| UINT64_C(618668032), // CMPLO_PPzZI_D |
| UINT64_C(610279424), // CMPLO_PPzZI_H |
| UINT64_C(614473728), // CMPLO_PPzZI_S |
| UINT64_C(604037120), // CMPLO_WIDE_PPzZZ_B |
| UINT64_C(608231424), // CMPLO_WIDE_PPzZZ_H |
| UINT64_C(612425728), // CMPLO_WIDE_PPzZZ_S |
| UINT64_C(606085136), // CMPLS_PPzZI_B |
| UINT64_C(618668048), // CMPLS_PPzZI_D |
| UINT64_C(610279440), // CMPLS_PPzZI_H |
| UINT64_C(614473744), // CMPLS_PPzZI_S |
| UINT64_C(604037136), // CMPLS_WIDE_PPzZZ_B |
| UINT64_C(608231440), // CMPLS_WIDE_PPzZZ_H |
| UINT64_C(612425744), // CMPLS_WIDE_PPzZZ_S |
| UINT64_C(620765184), // CMPLT_PPzZI_B |
| UINT64_C(633348096), // CMPLT_PPzZI_D |
| UINT64_C(624959488), // CMPLT_PPzZI_H |
| UINT64_C(629153792), // CMPLT_PPzZI_S |
| UINT64_C(604004352), // CMPLT_WIDE_PPzZZ_B |
| UINT64_C(608198656), // CMPLT_WIDE_PPzZZ_H |
| UINT64_C(612392960), // CMPLT_WIDE_PPzZZ_S |
| UINT64_C(620789776), // CMPNE_PPzZI_B |
| UINT64_C(633372688), // CMPNE_PPzZI_D |
| UINT64_C(624984080), // CMPNE_PPzZI_H |
| UINT64_C(629178384), // CMPNE_PPzZI_S |
| UINT64_C(604020752), // CMPNE_PPzZZ_B |
| UINT64_C(616603664), // CMPNE_PPzZZ_D |
| UINT64_C(608215056), // CMPNE_PPzZZ_H |
| UINT64_C(612409360), // CMPNE_PPzZZ_S |
| UINT64_C(603987984), // CMPNE_WIDE_PPzZZ_B |
| UINT64_C(608182288), // CMPNE_WIDE_PPzZZ_H |
| UINT64_C(612376592), // CMPNE_WIDE_PPzZZ_S |
| UINT64_C(0), // CMP_SWAP_128 |
| UINT64_C(0), // CMP_SWAP_16 |
| UINT64_C(0), // CMP_SWAP_32 |
| UINT64_C(0), // CMP_SWAP_64 |
| UINT64_C(0), // CMP_SWAP_8 |
| UINT64_C(1310755840), // CMTSTv16i8 |
| UINT64_C(1591774208), // CMTSTv1i64 |
| UINT64_C(245402624), // CMTSTv2i32 |
| UINT64_C(1323338752), // CMTSTv2i64 |
| UINT64_C(241208320), // CMTSTv4i16 |
| UINT64_C(1319144448), // CMTSTv4i32 |
| UINT64_C(1314950144), // CMTSTv8i16 |
| UINT64_C(237014016), // CMTSTv8i8 |
| UINT64_C(68919296), // CNOT_ZPmZ_B |
| UINT64_C(81502208), // CNOT_ZPmZ_D |
| UINT64_C(73113600), // CNOT_ZPmZ_H |
| UINT64_C(77307904), // CNOT_ZPmZ_S |
| UINT64_C(69263360), // CNTB_XPiI |
| UINT64_C(81846272), // CNTD_XPiI |
| UINT64_C(73457664), // CNTH_XPiI |
| UINT64_C(622886912), // CNTP_XPP_B |
| UINT64_C(635469824), // CNTP_XPP_D |
| UINT64_C(627081216), // CNTP_XPP_H |
| UINT64_C(631275520), // CNTP_XPP_S |
| UINT64_C(77651968), // CNTW_XPiI |
| UINT64_C(68853760), // CNT_ZPmZ_B |
| UINT64_C(81436672), // CNT_ZPmZ_D |
| UINT64_C(73048064), // CNT_ZPmZ_H |
| UINT64_C(77242368), // CNT_ZPmZ_S |
| UINT64_C(1310742528), // CNTv16i8 |
| UINT64_C(237000704), // CNTv8i8 |
| UINT64_C(98664448), // COMPACT_ZPZ_D |
| UINT64_C(94470144), // COMPACT_ZPZ_S |
| UINT64_C(84951040), // CPY_ZPmI_B |
| UINT64_C(97533952), // CPY_ZPmI_D |
| UINT64_C(89145344), // CPY_ZPmI_H |
| UINT64_C(93339648), // CPY_ZPmI_S |
| UINT64_C(86548480), // CPY_ZPmR_B |
| UINT64_C(99131392), // CPY_ZPmR_D |
| UINT64_C(90742784), // CPY_ZPmR_H |
| UINT64_C(94937088), // CPY_ZPmR_S |
| UINT64_C(86016000), // CPY_ZPmV_B |
| UINT64_C(98598912), // CPY_ZPmV_D |
| UINT64_C(90210304), // CPY_ZPmV_H |
| UINT64_C(94404608), // CPY_ZPmV_S |
| UINT64_C(84934656), // CPY_ZPzI_B |
| UINT64_C(97517568), // CPY_ZPzI_D |
| UINT64_C(89128960), // CPY_ZPzI_H |
| UINT64_C(93323264), // CPY_ZPzI_S |
| UINT64_C(1577190400), // CPYi16 |
| UINT64_C(1577321472), // CPYi32 |
| UINT64_C(1577583616), // CPYi64 |
| UINT64_C(1577124864), // CPYi8 |
| UINT64_C(448806912), // CRC32Brr |
| UINT64_C(448811008), // CRC32CBrr |
| UINT64_C(448812032), // CRC32CHrr |
| UINT64_C(448813056), // CRC32CWrr |
| UINT64_C(2596297728), // CRC32CXrr |
| UINT64_C(448807936), // CRC32Hrr |
| UINT64_C(448808960), // CRC32Wrr |
| UINT64_C(2596293632), // CRC32Xrr |
| UINT64_C(444596224), // CSELWr |
| UINT64_C(2592079872), // CSELXr |
| UINT64_C(444597248), // CSINCWr |
| UINT64_C(2592080896), // CSINCXr |
| UINT64_C(1518338048), // CSINVWr |
| UINT64_C(3665821696), // CSINVXr |
| UINT64_C(1518339072), // CSNEGWr |
| UINT64_C(3665822720), // CSNEGXr |
| UINT64_C(631250944), // CTERMEQ_WW |
| UINT64_C(635445248), // CTERMEQ_XX |
| UINT64_C(631250960), // CTERMNE_WW |
| UINT64_C(635445264), // CTERMNE_XX |
| UINT64_C(0), // CompilerBarrier |
| UINT64_C(3567255553), // DCPS1 |
| UINT64_C(3567255554), // DCPS2 |
| UINT64_C(3567255555), // DCPS3 |
| UINT64_C(70312960), // DECB_XPiI |
| UINT64_C(82895872), // DECD_XPiI |
| UINT64_C(82887680), // DECD_ZPiI |
| UINT64_C(74507264), // DECH_XPiI |
| UINT64_C(74499072), // DECH_ZPiI |
| UINT64_C(623740928), // DECP_XP_B |
| UINT64_C(636323840), // DECP_XP_D |
| UINT64_C(627935232), // DECP_XP_H |
| UINT64_C(632129536), // DECP_XP_S |
| UINT64_C(636321792), // DECP_ZP_D |
| UINT64_C(627933184), // DECP_ZP_H |
| UINT64_C(632127488), // DECP_ZP_S |
| UINT64_C(78701568), // DECW_XPiI |
| UINT64_C(78693376), // DECW_ZPiI |
| UINT64_C(3573756095), // DMB |
| UINT64_C(3602842592), // DRPS |
| UINT64_C(3573756063), // DSB |
| UINT64_C(96468992), // DUPM_ZI |
| UINT64_C(624476160), // DUP_ZI_B |
| UINT64_C(637059072), // DUP_ZI_D |
| UINT64_C(628670464), // DUP_ZI_H |
| UINT64_C(632864768), // DUP_ZI_S |
| UINT64_C(85997568), // DUP_ZR_B |
| UINT64_C(98580480), // DUP_ZR_D |
| UINT64_C(90191872), // DUP_ZR_H |
| UINT64_C(94386176), // DUP_ZR_S |
| UINT64_C(86056960), // DUP_ZZI_B |
| UINT64_C(86515712), // DUP_ZZI_D |
| UINT64_C(86122496), // DUP_ZZI_H |
| UINT64_C(87040000), // DUP_ZZI_Q |
| UINT64_C(86253568), // DUP_ZZI_S |
| UINT64_C(1308691456), // DUPv16i8gpr |
| UINT64_C(1308689408), // DUPv16i8lane |
| UINT64_C(235146240), // DUPv2i32gpr |
| UINT64_C(235144192), // DUPv2i32lane |
| UINT64_C(1309150208), // DUPv2i64gpr |
| UINT64_C(1309148160), // DUPv2i64lane |
| UINT64_C(235015168), // DUPv4i16gpr |
| UINT64_C(235013120), // DUPv4i16lane |
| UINT64_C(1308888064), // DUPv4i32gpr |
| UINT64_C(1308886016), // DUPv4i32lane |
| UINT64_C(1308756992), // DUPv8i16gpr |
| UINT64_C(1308754944), // DUPv8i16lane |
| UINT64_C(234949632), // DUPv8i8gpr |
| UINT64_C(234947584), // DUPv8i8lane |
| UINT64_C(0), // EMITBKEY |
| UINT64_C(0), // EONWrr |
| UINT64_C(1243611136), // EONWrs |
| UINT64_C(0), // EONXrr |
| UINT64_C(3391094784), // EONXrs |
| UINT64_C(3456106496), // EOR3 |
| UINT64_C(69220352), // EOR3_ZZZZ_D |
| UINT64_C(1157664768), // EORBT_ZZZ_B |
| UINT64_C(1170247680), // EORBT_ZZZ_D |
| UINT64_C(1161859072), // EORBT_ZZZ_H |
| UINT64_C(1166053376), // EORBT_ZZZ_S |
| UINT64_C(624968192), // EORS_PPzPP |
| UINT64_C(1157665792), // EORTB_ZZZ_B |
| UINT64_C(1170248704), // EORTB_ZZZ_D |
| UINT64_C(1161860096), // EORTB_ZZZ_H |
| UINT64_C(1166054400), // EORTB_ZZZ_S |
| UINT64_C(68755456), // EORV_VPZ_B |
| UINT64_C(81338368), // EORV_VPZ_D |
| UINT64_C(72949760), // EORV_VPZ_H |
| UINT64_C(77144064), // EORV_VPZ_S |
| UINT64_C(1375731712), // EORWri |
| UINT64_C(0), // EORWrr |
| UINT64_C(1241513984), // EORWrs |
| UINT64_C(3523215360), // EORXri |
| UINT64_C(0), // EORXrr |
| UINT64_C(3388997632), // EORXrs |
| UINT64_C(620773888), // EOR_PPzPP |
| UINT64_C(88080384), // EOR_ZI |
| UINT64_C(68747264), // EOR_ZPmZ_B |
| UINT64_C(81330176), // EOR_ZPmZ_D |
| UINT64_C(72941568), // EOR_ZPmZ_H |
| UINT64_C(77135872), // EOR_ZPmZ_S |
| UINT64_C(77606912), // EOR_ZZZ |
| UINT64_C(1847598080), // EORv16i8 |
| UINT64_C(773856256), // EORv8i8 |
| UINT64_C(3600745440), // ERET |
| UINT64_C(3600747519), // ERETAA |
| UINT64_C(3600748543), // ERETAB |
| UINT64_C(327155712), // EXTRWrri |
| UINT64_C(2478833664), // EXTRXrri |
| UINT64_C(85983232), // EXT_ZZI |
| UINT64_C(90177536), // EXT_ZZI_B |
| UINT64_C(1845493760), // EXTv16i8 |
| UINT64_C(771751936), // EXTv8i8 |
| UINT64_C(0), // F128CSEL |
| UINT64_C(2126517248), // FABD16 |
| UINT64_C(2124469248), // FABD32 |
| UINT64_C(2128663552), // FABD64 |
| UINT64_C(1707638784), // FABD_ZPmZ_D |
| UINT64_C(1699250176), // FABD_ZPmZ_H |
| UINT64_C(1703444480), // FABD_ZPmZ_S |
| UINT64_C(782291968), // FABDv2f32 |
| UINT64_C(1860228096), // FABDv2f64 |
| UINT64_C(784339968), // FABDv4f16 |
| UINT64_C(1856033792), // FABDv4f32 |
| UINT64_C(1858081792), // FABDv8f16 |
| UINT64_C(509657088), // FABSDr |
| UINT64_C(518045696), // FABSHr |
| UINT64_C(505462784), // FABSSr |
| UINT64_C(81567744), // FABS_ZPmZ_D |
| UINT64_C(73179136), // FABS_ZPmZ_H |
| UINT64_C(77373440), // FABS_ZPmZ_S |
| UINT64_C(245430272), // FABSv2f32 |
| UINT64_C(1323366400), // FABSv2f64 |
| UINT64_C(251197440), // FABSv4f16 |
| UINT64_C(1319172096), // FABSv4f32 |
| UINT64_C(1324939264), // FABSv8f16 |
| UINT64_C(2118134784), // FACGE16 |
| UINT64_C(2116086784), // FACGE32 |
| UINT64_C(2120281088), // FACGE64 |
| UINT64_C(1707130896), // FACGE_PPzZZ_D |
| UINT64_C(1698742288), // FACGE_PPzZZ_H |
| UINT64_C(1702936592), // FACGE_PPzZZ_S |
| UINT64_C(773909504), // FACGEv2f32 |
| UINT64_C(1851845632), // FACGEv2f64 |
| UINT64_C(775957504), // FACGEv4f16 |
| UINT64_C(1847651328), // FACGEv4f32 |
| UINT64_C(1849699328), // FACGEv8f16 |
| UINT64_C(2126523392), // FACGT16 |
| UINT64_C(2124475392), // FACGT32 |
| UINT64_C(2128669696), // FACGT64 |
| UINT64_C(1707139088), // FACGT_PPzZZ_D |
| UINT64_C(1698750480), // FACGT_PPzZZ_H |
| UINT64_C(1702944784), // FACGT_PPzZZ_S |
| UINT64_C(782298112), // FACGTv2f32 |
| UINT64_C(1860234240), // FACGTv2f64 |
| UINT64_C(784346112), // FACGTv4f16 |
| UINT64_C(1856039936), // FACGTv4f32 |
| UINT64_C(1858087936), // FACGTv8f16 |
| UINT64_C(1708662784), // FADDA_VPZ_D |
| UINT64_C(1700274176), // FADDA_VPZ_H |
| UINT64_C(1704468480), // FADDA_VPZ_S |
| UINT64_C(509618176), // FADDDrr |
| UINT64_C(518006784), // FADDHrr |
| UINT64_C(1691385856), // FADDP_ZPmZZ_D |
| UINT64_C(1682997248), // FADDP_ZPmZZ_H |
| UINT64_C(1687191552), // FADDP_ZPmZZ_S |
| UINT64_C(773903360), // FADDPv2f32 |
| UINT64_C(1851839488), // FADDPv2f64 |
| UINT64_C(1580259328), // FADDPv2i16p |
| UINT64_C(2117130240), // FADDPv2i32p |
| UINT64_C(2121324544), // FADDPv2i64p |
| UINT64_C(775951360), // FADDPv4f16 |
| UINT64_C(1847645184), // FADDPv4f32 |
| UINT64_C(1849693184), // FADDPv8f16 |
| UINT64_C(505423872), // FADDSrr |
| UINT64_C(1707089920), // FADDV_VPZ_D |
| UINT64_C(1698701312), // FADDV_VPZ_H |
| UINT64_C(1702895616), // FADDV_VPZ_S |
| UINT64_C(1708687360), // FADD_ZPmI_D |
| UINT64_C(1700298752), // FADD_ZPmI_H |
| UINT64_C(1704493056), // FADD_ZPmI_S |
| UINT64_C(1707114496), // FADD_ZPmZ_D |
| UINT64_C(1698725888), // FADD_ZPmZ_H |
| UINT64_C(1702920192), // FADD_ZPmZ_S |
| UINT64_C(1707081728), // FADD_ZZZ_D |
| UINT64_C(1698693120), // FADD_ZZZ_H |
| UINT64_C(1702887424), // FADD_ZZZ_S |
| UINT64_C(237032448), // FADDv2f32 |
| UINT64_C(1314968576), // FADDv2f64 |
| UINT64_C(239080448), // FADDv4f16 |
| UINT64_C(1310774272), // FADDv4f32 |
| UINT64_C(1312822272), // FADDv8f16 |
| UINT64_C(1690337280), // FCADD_ZPmZ_D |
| UINT64_C(1681948672), // FCADD_ZPmZ_H |
| UINT64_C(1686142976), // FCADD_ZPmZ_S |
| UINT64_C(780198912), // FCADDv2f32 |
| UINT64_C(1858135040), // FCADDv2f64 |
| UINT64_C(776004608), // FCADDv4f16 |
| UINT64_C(1853940736), // FCADDv4f32 |
| UINT64_C(1849746432), // FCADDv8f16 |
| UINT64_C(509608960), // FCCMPDrr |
| UINT64_C(509608976), // FCCMPEDrr |
| UINT64_C(517997584), // FCCMPEHrr |
| UINT64_C(505414672), // FCCMPESrr |
| UINT64_C(517997568), // FCCMPHrr |
| UINT64_C(505414656), // FCCMPSrr |
| UINT64_C(1581261824), // FCMEQ16 |
| UINT64_C(1579213824), // FCMEQ32 |
| UINT64_C(1583408128), // FCMEQ64 |
| UINT64_C(1708269568), // FCMEQ_PPzZ0_D |
| UINT64_C(1699880960), // FCMEQ_PPzZ0_H |
| UINT64_C(1704075264), // FCMEQ_PPzZ0_S |
| UINT64_C(1707106304), // FCMEQ_PPzZZ_D |
| UINT64_C(1698717696), // FCMEQ_PPzZZ_H |
| UINT64_C(1702912000), // FCMEQ_PPzZZ_S |
| UINT64_C(1593366528), // FCMEQv1i16rz |
| UINT64_C(1587599360), // FCMEQv1i32rz |
| UINT64_C(1591793664), // FCMEQv1i64rz |
| UINT64_C(237036544), // FCMEQv2f32 |
| UINT64_C(1314972672), // FCMEQv2f64 |
| UINT64_C(245422080), // FCMEQv2i32rz |
| UINT64_C(1323358208), // FCMEQv2i64rz |
| UINT64_C(239084544), // FCMEQv4f16 |
| UINT64_C(1310778368), // FCMEQv4f32 |
| UINT64_C(251189248), // FCMEQv4i16rz |
| UINT64_C(1319163904), // FCMEQv4i32rz |
| UINT64_C(1312826368), // FCMEQv8f16 |
| UINT64_C(1324931072), // FCMEQv8i16rz |
| UINT64_C(2118132736), // FCMGE16 |
| UINT64_C(2116084736), // FCMGE32 |
| UINT64_C(2120279040), // FCMGE64 |
| UINT64_C(1708138496), // FCMGE_PPzZ0_D |
| UINT64_C(1699749888), // FCMGE_PPzZ0_H |
| UINT64_C(1703944192), // FCMGE_PPzZ0_S |
| UINT64_C(1707098112), // FCMGE_PPzZZ_D |
| UINT64_C(1698709504), // FCMGE_PPzZZ_H |
| UINT64_C(1702903808), // FCMGE_PPzZZ_S |
| UINT64_C(2130233344), // FCMGEv1i16rz |
| UINT64_C(2124466176), // FCMGEv1i32rz |
| UINT64_C(2128660480), // FCMGEv1i64rz |
| UINT64_C(773907456), // FCMGEv2f32 |
| UINT64_C(1851843584), // FCMGEv2f64 |
| UINT64_C(782288896), // FCMGEv2i32rz |
| UINT64_C(1860225024), // FCMGEv2i64rz |
| UINT64_C(775955456), // FCMGEv4f16 |
| UINT64_C(1847649280), // FCMGEv4f32 |
| UINT64_C(788056064), // FCMGEv4i16rz |
| UINT64_C(1856030720), // FCMGEv4i32rz |
| UINT64_C(1849697280), // FCMGEv8f16 |
| UINT64_C(1861797888), // FCMGEv8i16rz |
| UINT64_C(2126521344), // FCMGT16 |
| UINT64_C(2124473344), // FCMGT32 |
| UINT64_C(2128667648), // FCMGT64 |
| UINT64_C(1708138512), // FCMGT_PPzZ0_D |
| UINT64_C(1699749904), // FCMGT_PPzZ0_H |
| UINT64_C(1703944208), // FCMGT_PPzZ0_S |
| UINT64_C(1707098128), // FCMGT_PPzZZ_D |
| UINT64_C(1698709520), // FCMGT_PPzZZ_H |
| UINT64_C(1702903824), // FCMGT_PPzZZ_S |
| UINT64_C(1593362432), // FCMGTv1i16rz |
| UINT64_C(1587595264), // FCMGTv1i32rz |
| UINT64_C(1591789568), // FCMGTv1i64rz |
| UINT64_C(782296064), // FCMGTv2f32 |
| UINT64_C(1860232192), // FCMGTv2f64 |
| UINT64_C(245417984), // FCMGTv2i32rz |
| UINT64_C(1323354112), // FCMGTv2i64rz |
| UINT64_C(784344064), // FCMGTv4f16 |
| UINT64_C(1856037888), // FCMGTv4f32 |
| UINT64_C(251185152), // FCMGTv4i16rz |
| UINT64_C(1319159808), // FCMGTv4i32rz |
| UINT64_C(1858085888), // FCMGTv8f16 |
| UINT64_C(1324926976), // FCMGTv8i16rz |
| UINT64_C(1690304512), // FCMLA_ZPmZZ_D |
| UINT64_C(1681915904), // FCMLA_ZPmZZ_H |
| UINT64_C(1686110208), // FCMLA_ZPmZZ_S |
| UINT64_C(1688211456), // FCMLA_ZZZI_H |
| UINT64_C(1692405760), // FCMLA_ZZZI_S |
| UINT64_C(780190720), // FCMLAv2f32 |
| UINT64_C(1858126848), // FCMLAv2f64 |
| UINT64_C(775996416), // FCMLAv4f16 |
| UINT64_C(792727552), // FCMLAv4f16_indexed |
| UINT64_C(1853932544), // FCMLAv4f32 |
| UINT64_C(1870663680), // FCMLAv4f32_indexed |
| UINT64_C(1849738240), // FCMLAv8f16 |
| UINT64_C(1866469376), // FCMLAv8f16_indexed |
| UINT64_C(1708204048), // FCMLE_PPzZ0_D |
| UINT64_C(1699815440), // FCMLE_PPzZ0_H |
| UINT64_C(1704009744), // FCMLE_PPzZ0_S |
| UINT64_C(2130237440), // FCMLEv1i16rz |
| UINT64_C(2124470272), // FCMLEv1i32rz |
| UINT64_C(2128664576), // FCMLEv1i64rz |
| UINT64_C(782292992), // FCMLEv2i32rz |
| UINT64_C(1860229120), // FCMLEv2i64rz |
| UINT64_C(788060160), // FCMLEv4i16rz |
| UINT64_C(1856034816), // FCMLEv4i32rz |
| UINT64_C(1861801984), // FCMLEv8i16rz |
| UINT64_C(1708204032), // FCMLT_PPzZ0_D |
| UINT64_C(1699815424), // FCMLT_PPzZ0_H |
| UINT64_C(1704009728), // FCMLT_PPzZ0_S |
| UINT64_C(1593370624), // FCMLTv1i16rz |
| UINT64_C(1587603456), // FCMLTv1i32rz |
| UINT64_C(1591797760), // FCMLTv1i64rz |
| UINT64_C(245426176), // FCMLTv2i32rz |
| UINT64_C(1323362304), // FCMLTv2i64rz |
| UINT64_C(251193344), // FCMLTv4i16rz |
| UINT64_C(1319168000), // FCMLTv4i32rz |
| UINT64_C(1324935168), // FCMLTv8i16rz |
| UINT64_C(1708335104), // FCMNE_PPzZ0_D |
| UINT64_C(1699946496), // FCMNE_PPzZ0_H |
| UINT64_C(1704140800), // FCMNE_PPzZ0_S |
| UINT64_C(1707106320), // FCMNE_PPzZZ_D |
| UINT64_C(1698717712), // FCMNE_PPzZZ_H |
| UINT64_C(1702912016), // FCMNE_PPzZZ_S |
| UINT64_C(509616136), // FCMPDri |
| UINT64_C(509616128), // FCMPDrr |
| UINT64_C(509616152), // FCMPEDri |
| UINT64_C(509616144), // FCMPEDrr |
| UINT64_C(518004760), // FCMPEHri |
| UINT64_C(518004752), // FCMPEHrr |
| UINT64_C(505421848), // FCMPESri |
| UINT64_C(505421840), // FCMPESrr |
| UINT64_C(518004744), // FCMPHri |
| UINT64_C(518004736), // FCMPHrr |
| UINT64_C(505421832), // FCMPSri |
| UINT64_C(505421824), // FCMPSrr |
| UINT64_C(1707130880), // FCMUO_PPzZZ_D |
| UINT64_C(1698742272), // FCMUO_PPzZZ_H |
| UINT64_C(1702936576), // FCMUO_PPzZZ_S |
| UINT64_C(97566720), // FCPY_ZPmI_D |
| UINT64_C(89178112), // FCPY_ZPmI_H |
| UINT64_C(93372416), // FCPY_ZPmI_S |
| UINT64_C(509611008), // FCSELDrrr |
| UINT64_C(517999616), // FCSELHrrr |
| UINT64_C(505416704), // FCSELSrrr |
| UINT64_C(509870080), // FCVTASUWDr |
| UINT64_C(518258688), // FCVTASUWHr |
| UINT64_C(505675776), // FCVTASUWSr |
| UINT64_C(2657353728), // FCVTASUXDr |
| UINT64_C(2665742336), // FCVTASUXHr |
| UINT64_C(2653159424), // FCVTASUXSr |
| UINT64_C(1585039360), // FCVTASv1f16 |
| UINT64_C(1579272192), // FCVTASv1i32 |
| UINT64_C(1583466496), // FCVTASv1i64 |
| UINT64_C(237094912), // FCVTASv2f32 |
| UINT64_C(1315031040), // FCVTASv2f64 |
| UINT64_C(242862080), // FCVTASv4f16 |
| UINT64_C(1310836736), // FCVTASv4f32 |
| UINT64_C(1316603904), // FCVTASv8f16 |
| UINT64_C(509935616), // FCVTAUUWDr |
| UINT64_C(518324224), // FCVTAUUWHr |
| UINT64_C(505741312), // FCVTAUUWSr |
| UINT64_C(2657419264), // FCVTAUUXDr |
| UINT64_C(2665807872), // FCVTAUUXHr |
| UINT64_C(2653224960), // FCVTAUUXSr |
| UINT64_C(2121910272), // FCVTAUv1f16 |
| UINT64_C(2116143104), // FCVTAUv1i32 |
| UINT64_C(2120337408), // FCVTAUv1i64 |
| UINT64_C(773965824), // FCVTAUv2f32 |
| UINT64_C(1851901952), // FCVTAUv2f64 |
| UINT64_C(779732992), // FCVTAUv4f16 |
| UINT64_C(1847707648), // FCVTAUv4f32 |
| UINT64_C(1853474816), // FCVTAUv8f16 |
| UINT64_C(518176768), // FCVTDHr |
| UINT64_C(505593856), // FCVTDSr |
| UINT64_C(509853696), // FCVTHDr |
| UINT64_C(505659392), // FCVTHSr |
| UINT64_C(1686740992), // FCVTLT_ZPmZ_HtoS |
| UINT64_C(1691066368), // FCVTLT_ZPmZ_StoD |
| UINT64_C(241268736), // FCVTLv2i32 |
| UINT64_C(237074432), // FCVTLv4i16 |
| UINT64_C(1315010560), // FCVTLv4i32 |
| UINT64_C(1310816256), // FCVTLv8i16 |
| UINT64_C(510656512), // FCVTMSUWDr |
| UINT64_C(519045120), // FCVTMSUWHr |
| UINT64_C(506462208), // FCVTMSUWSr |
| UINT64_C(2658140160), // FCVTMSUXDr |
| UINT64_C(2666528768), // FCVTMSUXHr |
| UINT64_C(2653945856), // FCVTMSUXSr |
| UINT64_C(1585035264), // FCVTMSv1f16 |
| UINT64_C(1579268096), // FCVTMSv1i32 |
| UINT64_C(1583462400), // FCVTMSv1i64 |
| UINT64_C(237090816), // FCVTMSv2f32 |
| UINT64_C(1315026944), // FCVTMSv2f64 |
| UINT64_C(242857984), // FCVTMSv4f16 |
| UINT64_C(1310832640), // FCVTMSv4f32 |
| UINT64_C(1316599808), // FCVTMSv8f16 |
| UINT64_C(510722048), // FCVTMUUWDr |
| UINT64_C(519110656), // FCVTMUUWHr |
| UINT64_C(506527744), // FCVTMUUWSr |
| UINT64_C(2658205696), // FCVTMUUXDr |
| UINT64_C(2666594304), // FCVTMUUXHr |
| UINT64_C(2654011392), // FCVTMUUXSr |
| UINT64_C(2121906176), // FCVTMUv1f16 |
| UINT64_C(2116139008), // FCVTMUv1i32 |
| UINT64_C(2120333312), // FCVTMUv1i64 |
| UINT64_C(773961728), // FCVTMUv2f32 |
| UINT64_C(1851897856), // FCVTMUv2f64 |
| UINT64_C(779728896), // FCVTMUv4f16 |
| UINT64_C(1847703552), // FCVTMUv4f32 |
| UINT64_C(1853470720), // FCVTMUv8f16 |
| UINT64_C(509607936), // FCVTNSUWDr |
| UINT64_C(517996544), // FCVTNSUWHr |
| UINT64_C(505413632), // FCVTNSUWSr |
| UINT64_C(2657091584), // FCVTNSUXDr |
| UINT64_C(2665480192), // FCVTNSUXHr |
| UINT64_C(2652897280), // FCVTNSUXSr |
| UINT64_C(1585031168), // FCVTNSv1f16 |
| UINT64_C(1579264000), // FCVTNSv1i32 |
| UINT64_C(1583458304), // FCVTNSv1i64 |
| UINT64_C(237086720), // FCVTNSv2f32 |
| UINT64_C(1315022848), // FCVTNSv2f64 |
| UINT64_C(242853888), // FCVTNSv4f16 |
| UINT64_C(1310828544), // FCVTNSv4f32 |
| UINT64_C(1316595712), // FCVTNSv8f16 |
| UINT64_C(1691000832), // FCVTNT_ZPmZ_DtoS |
| UINT64_C(1686675456), // FCVTNT_ZPmZ_StoH |
| UINT64_C(509673472), // FCVTNUUWDr |
| UINT64_C(518062080), // FCVTNUUWHr |
| UINT64_C(505479168), // FCVTNUUWSr |
| UINT64_C(2657157120), // FCVTNUUXDr |
| UINT64_C(2665545728), // FCVTNUUXHr |
| UINT64_C(2652962816), // FCVTNUUXSr |
| UINT64_C(2121902080), // FCVTNUv1f16 |
| UINT64_C(2116134912), // FCVTNUv1i32 |
| UINT64_C(2120329216), // FCVTNUv1i64 |
| UINT64_C(773957632), // FCVTNUv2f32 |
| UINT64_C(1851893760), // FCVTNUv2f64 |
| UINT64_C(779724800), // FCVTNUv4f16 |
| UINT64_C(1847699456), // FCVTNUv4f32 |
| UINT64_C(1853466624), // FCVTNUv8f16 |
| UINT64_C(241264640), // FCVTNv2i32 |
| UINT64_C(237070336), // FCVTNv4i16 |
| UINT64_C(1315006464), // FCVTNv4i32 |
| UINT64_C(1310812160), // FCVTNv8i16 |
| UINT64_C(510132224), // FCVTPSUWDr |
| UINT64_C(518520832), // FCVTPSUWHr |
| UINT64_C(505937920), // FCVTPSUWSr |
| UINT64_C(2657615872), // FCVTPSUXDr |
| UINT64_C(2666004480), // FCVTPSUXHr |
| UINT64_C(2653421568), // FCVTPSUXSr |
| UINT64_C(1593419776), // FCVTPSv1f16 |
| UINT64_C(1587652608), // FCVTPSv1i32 |
| UINT64_C(1591846912), // FCVTPSv1i64 |
| UINT64_C(245475328), // FCVTPSv2f32 |
| UINT64_C(1323411456), // FCVTPSv2f64 |
| UINT64_C(251242496), // FCVTPSv4f16 |
| UINT64_C(1319217152), // FCVTPSv4f32 |
| UINT64_C(1324984320), // FCVTPSv8f16 |
| UINT64_C(510197760), // FCVTPUUWDr |
| UINT64_C(518586368), // FCVTPUUWHr |
| UINT64_C(506003456), // FCVTPUUWSr |
| UINT64_C(2657681408), // FCVTPUUXDr |
| UINT64_C(2666070016), // FCVTPUUXHr |
| UINT64_C(2653487104), // FCVTPUUXSr |
| UINT64_C(2130290688), // FCVTPUv1f16 |
| UINT64_C(2124523520), // FCVTPUv1i32 |
| UINT64_C(2128717824), // FCVTPUv1i64 |
| UINT64_C(782346240), // FCVTPUv2f32 |
| UINT64_C(1860282368), // FCVTPUv2f64 |
| UINT64_C(788113408), // FCVTPUv4f16 |
| UINT64_C(1856088064), // FCVTPUv4f32 |
| UINT64_C(1861855232), // FCVTPUv8f16 |
| UINT64_C(509755392), // FCVTSDr |
| UINT64_C(518144000), // FCVTSHr |
| UINT64_C(1678417920), // FCVTXNT_ZPmZ_DtoS |
| UINT64_C(2120312832), // FCVTXNv1i64 |
| UINT64_C(778135552), // FCVTXNv2f32 |
| UINT64_C(1851877376), // FCVTXNv4f32 |
| UINT64_C(1695195136), // FCVTX_ZPmZ_DtoS |
| UINT64_C(509116416), // FCVTZSSWDri |
| UINT64_C(517505024), // FCVTZSSWHri |
| UINT64_C(504922112), // FCVTZSSWSri |
| UINT64_C(2656567296), // FCVTZSSXDri |
| UINT64_C(2664955904), // FCVTZSSXHri |
| UINT64_C(2652372992), // FCVTZSSXSri |
| UINT64_C(511180800), // FCVTZSUWDr |
| UINT64_C(519569408), // FCVTZSUWHr |
| UINT64_C(506986496), // FCVTZSUWSr |
| UINT64_C(2658664448), // FCVTZSUXDr |
| UINT64_C(2667053056), // FCVTZSUXHr |
| UINT64_C(2654470144), // FCVTZSUXSr |
| UINT64_C(1709088768), // FCVTZS_ZPmZ_DtoD |
| UINT64_C(1708695552), // FCVTZS_ZPmZ_DtoS |
| UINT64_C(1700700160), // FCVTZS_ZPmZ_HtoD |
| UINT64_C(1700438016), // FCVTZS_ZPmZ_HtoH |
| UINT64_C(1700569088), // FCVTZS_ZPmZ_HtoS |
| UINT64_C(1708957696), // FCVTZS_ZPmZ_StoD |
| UINT64_C(1704763392), // FCVTZS_ZPmZ_StoS |
| UINT64_C(1598094336), // FCVTZSd |
| UINT64_C(1594948608), // FCVTZSh |
| UINT64_C(1595997184), // FCVTZSs |
| UINT64_C(1593423872), // FCVTZSv1f16 |
| UINT64_C(1587656704), // FCVTZSv1i32 |
| UINT64_C(1591851008), // FCVTZSv1i64 |
| UINT64_C(245479424), // FCVTZSv2f32 |
| UINT64_C(1323415552), // FCVTZSv2f64 |
| UINT64_C(253819904), // FCVTZSv2i32_shift |
| UINT64_C(1329658880), // FCVTZSv2i64_shift |
| UINT64_C(251246592), // FCVTZSv4f16 |
| UINT64_C(1319221248), // FCVTZSv4f32 |
| UINT64_C(252771328), // FCVTZSv4i16_shift |
| UINT64_C(1327561728), // FCVTZSv4i32_shift |
| UINT64_C(1324988416), // FCVTZSv8f16 |
| UINT64_C(1326513152), // FCVTZSv8i16_shift |
| UINT64_C(509181952), // FCVTZUSWDri |
| UINT64_C(517570560), // FCVTZUSWHri |
| UINT64_C(504987648), // FCVTZUSWSri |
| UINT64_C(2656632832), // FCVTZUSXDri |
| UINT64_C(2665021440), // FCVTZUSXHri |
| UINT64_C(2652438528), // FCVTZUSXSri |
| UINT64_C(511246336), // FCVTZUUWDr |
| UINT64_C(519634944), // FCVTZUUWHr |
| UINT64_C(507052032), // FCVTZUUWSr |
| UINT64_C(2658729984), // FCVTZUUXDr |
| UINT64_C(2667118592), // FCVTZUUXHr |
| UINT64_C(2654535680), // FCVTZUUXSr |
| UINT64_C(1709154304), // FCVTZU_ZPmZ_DtoD |
| UINT64_C(1708761088), // FCVTZU_ZPmZ_DtoS |
| UINT64_C(1700765696), // FCVTZU_ZPmZ_HtoD |
| UINT64_C(1700503552), // FCVTZU_ZPmZ_HtoH |
| UINT64_C(1700634624), // FCVTZU_ZPmZ_HtoS |
| UINT64_C(1709023232), // FCVTZU_ZPmZ_StoD |
| UINT64_C(1704828928), // FCVTZU_ZPmZ_StoS |
| UINT64_C(2134965248), // FCVTZUd |
| UINT64_C(2131819520), // FCVTZUh |
| UINT64_C(2132868096), // FCVTZUs |
| UINT64_C(2130294784), // FCVTZUv1f16 |
| UINT64_C(2124527616), // FCVTZUv1i32 |
| UINT64_C(2128721920), // FCVTZUv1i64 |
| UINT64_C(782350336), // FCVTZUv2f32 |
| UINT64_C(1860286464), // FCVTZUv2f64 |
| UINT64_C(790690816), // FCVTZUv2i32_shift |
| UINT64_C(1866529792), // FCVTZUv2i64_shift |
| UINT64_C(788117504), // FCVTZUv4f16 |
| UINT64_C(1856092160), // FCVTZUv4f32 |
| UINT64_C(789642240), // FCVTZUv4i16_shift |
| UINT64_C(1864432640), // FCVTZUv4i32_shift |
| UINT64_C(1861859328), // FCVTZUv8f16 |
| UINT64_C(1863384064), // FCVTZUv8i16_shift |
| UINT64_C(1707646976), // FCVT_ZPmZ_DtoH |
| UINT64_C(1707778048), // FCVT_ZPmZ_DtoS |
| UINT64_C(1707712512), // FCVT_ZPmZ_HtoD |
| UINT64_C(1703518208), // FCVT_ZPmZ_HtoS |
| UINT64_C(1707843584), // FCVT_ZPmZ_StoD |
| UINT64_C(1703452672), // FCVT_ZPmZ_StoH |
| UINT64_C(509614080), // FDIVDrr |
| UINT64_C(518002688), // FDIVHrr |
| UINT64_C(1707900928), // FDIVR_ZPmZ_D |
| UINT64_C(1699512320), // FDIVR_ZPmZ_H |
| UINT64_C(1703706624), // FDIVR_ZPmZ_S |
| UINT64_C(505419776), // FDIVSrr |
| UINT64_C(1707966464), // FDIV_ZPmZ_D |
| UINT64_C(1699577856), // FDIV_ZPmZ_H |
| UINT64_C(1703772160), // FDIV_ZPmZ_S |
| UINT64_C(773913600), // FDIVv2f32 |
| UINT64_C(1851849728), // FDIVv2f64 |
| UINT64_C(775961600), // FDIVv4f16 |
| UINT64_C(1847655424), // FDIVv4f32 |
| UINT64_C(1849703424), // FDIVv8f16 |
| UINT64_C(637124608), // FDUP_ZI_D |
| UINT64_C(628736000), // FDUP_ZI_H |
| UINT64_C(632930304), // FDUP_ZI_S |
| UINT64_C(81836032), // FEXPA_ZZ_D |
| UINT64_C(73447424), // FEXPA_ZZ_H |
| UINT64_C(77641728), // FEXPA_ZZ_S |
| UINT64_C(511574016), // FJCVTZS |
| UINT64_C(1696505856), // FLOGB_ZPmZ_D |
| UINT64_C(1696243712), // FLOGB_ZPmZ_H |
| UINT64_C(1696374784), // FLOGB_ZPmZ_S |
| UINT64_C(524288000), // FMADDDrrr |
| UINT64_C(532676608), // FMADDHrrr |
| UINT64_C(520093696), // FMADDSrrr |
| UINT64_C(1709211648), // FMAD_ZPmZZ_D |
| UINT64_C(1700823040), // FMAD_ZPmZZ_H |
| UINT64_C(1705017344), // FMAD_ZPmZZ_S |
| UINT64_C(509626368), // FMAXDrr |
| UINT64_C(518014976), // FMAXHrr |
| UINT64_C(509634560), // FMAXNMDrr |
| UINT64_C(518023168), // FMAXNMHrr |
| UINT64_C(1691648000), // FMAXNMP_ZPmZZ_D |
| UINT64_C(1683259392), // FMAXNMP_ZPmZZ_H |
| UINT64_C(1687453696), // FMAXNMP_ZPmZZ_S |
| UINT64_C(773899264), // FMAXNMPv2f32 |
| UINT64_C(1851835392), // FMAXNMPv2f64 |
| UINT64_C(1580255232), // FMAXNMPv2i16p |
| UINT64_C(2117126144), // FMAXNMPv2i32p |
| UINT64_C(2121320448), // FMAXNMPv2i64p |
| UINT64_C(775947264), // FMAXNMPv4f16 |
| UINT64_C(1847641088), // FMAXNMPv4f32 |
| UINT64_C(1849689088), // FMAXNMPv8f16 |
| UINT64_C(505440256), // FMAXNMSrr |
| UINT64_C(1707352064), // FMAXNMV_VPZ_D |
| UINT64_C(1698963456), // FMAXNMV_VPZ_H |
| UINT64_C(1703157760), // FMAXNMV_VPZ_S |
| UINT64_C(238077952), // FMAXNMVv4i16v |
| UINT64_C(1848690688), // FMAXNMVv4i32v |
| UINT64_C(1311819776), // FMAXNMVv8i16v |
| UINT64_C(1708949504), // FMAXNM_ZPmI_D |
| UINT64_C(1700560896), // FMAXNM_ZPmI_H |
| UINT64_C(1704755200), // FMAXNM_ZPmI_S |
| UINT64_C(1707376640), // FMAXNM_ZPmZ_D |
| UINT64_C(1698988032), // FMAXNM_ZPmZ_H |
| UINT64_C(1703182336), // FMAXNM_ZPmZ_S |
| UINT64_C(237028352), // FMAXNMv2f32 |
| UINT64_C(1314964480), // FMAXNMv2f64 |
| UINT64_C(239076352), // FMAXNMv4f16 |
| UINT64_C(1310770176), // FMAXNMv4f32 |
| UINT64_C(1312818176), // FMAXNMv8f16 |
| UINT64_C(1691779072), // FMAXP_ZPmZZ_D |
| UINT64_C(1683390464), // FMAXP_ZPmZZ_H |
| UINT64_C(1687584768), // FMAXP_ZPmZZ_S |
| UINT64_C(773911552), // FMAXPv2f32 |
| UINT64_C(1851847680), // FMAXPv2f64 |
| UINT64_C(1580267520), // FMAXPv2i16p |
| UINT64_C(2117138432), // FMAXPv2i32p |
| UINT64_C(2121332736), // FMAXPv2i64p |
| UINT64_C(775959552), // FMAXPv4f16 |
| UINT64_C(1847653376), // FMAXPv4f32 |
| UINT64_C(1849701376), // FMAXPv8f16 |
| UINT64_C(505432064), // FMAXSrr |
| UINT64_C(1707483136), // FMAXV_VPZ_D |
| UINT64_C(1699094528), // FMAXV_VPZ_H |
| UINT64_C(1703288832), // FMAXV_VPZ_S |
| UINT64_C(238090240), // FMAXVv4i16v |
| UINT64_C(1848702976), // FMAXVv4i32v |
| UINT64_C(1311832064), // FMAXVv8i16v |
| UINT64_C(1709080576), // FMAX_ZPmI_D |
| UINT64_C(1700691968), // FMAX_ZPmI_H |
| UINT64_C(1704886272), // FMAX_ZPmI_S |
| UINT64_C(1707507712), // FMAX_ZPmZ_D |
| UINT64_C(1699119104), // FMAX_ZPmZ_H |
| UINT64_C(1703313408), // FMAX_ZPmZ_S |
| UINT64_C(237040640), // FMAXv2f32 |
| UINT64_C(1314976768), // FMAXv2f64 |
| UINT64_C(239088640), // FMAXv4f16 |
| UINT64_C(1310782464), // FMAXv4f32 |
| UINT64_C(1312830464), // FMAXv8f16 |
| UINT64_C(509630464), // FMINDrr |
| UINT64_C(518019072), // FMINHrr |
| UINT64_C(509638656), // FMINNMDrr |
| UINT64_C(518027264), // FMINNMHrr |
| UINT64_C(1691713536), // FMINNMP_ZPmZZ_D |
| UINT64_C(1683324928), // FMINNMP_ZPmZZ_H |
| UINT64_C(1687519232), // FMINNMP_ZPmZZ_S |
| UINT64_C(782287872), // FMINNMPv2f32 |
| UINT64_C(1860224000), // FMINNMPv2f64 |
| UINT64_C(1588643840), // FMINNMPv2i16p |
| UINT64_C(2125514752), // FMINNMPv2i32p |
| UINT64_C(2129709056), // FMINNMPv2i64p |
| UINT64_C(784335872), // FMINNMPv4f16 |
| UINT64_C(1856029696), // FMINNMPv4f32 |
| UINT64_C(1858077696), // FMINNMPv8f16 |
| UINT64_C(505444352), // FMINNMSrr |
| UINT64_C(1707417600), // FMINNMV_VPZ_D |
| UINT64_C(1699028992), // FMINNMV_VPZ_H |
| UINT64_C(1703223296), // FMINNMV_VPZ_S |
| UINT64_C(246466560), // FMINNMVv4i16v |
| UINT64_C(1857079296), // FMINNMVv4i32v |
| UINT64_C(1320208384), // FMINNMVv8i16v |
| UINT64_C(1709015040), // FMINNM_ZPmI_D |
| UINT64_C(1700626432), // FMINNM_ZPmI_H |
| UINT64_C(1704820736), // FMINNM_ZPmI_S |
| UINT64_C(1707442176), // FMINNM_ZPmZ_D |
| UINT64_C(1699053568), // FMINNM_ZPmZ_H |
| UINT64_C(1703247872), // FMINNM_ZPmZ_S |
| UINT64_C(245416960), // FMINNMv2f32 |
| UINT64_C(1323353088), // FMINNMv2f64 |
| UINT64_C(247464960), // FMINNMv4f16 |
| UINT64_C(1319158784), // FMINNMv4f32 |
| UINT64_C(1321206784), // FMINNMv8f16 |
| UINT64_C(1691844608), // FMINP_ZPmZZ_D |
| UINT64_C(1683456000), // FMINP_ZPmZZ_H |
| UINT64_C(1687650304), // FMINP_ZPmZZ_S |
| UINT64_C(782300160), // FMINPv2f32 |
| UINT64_C(1860236288), // FMINPv2f64 |
| UINT64_C(1588656128), // FMINPv2i16p |
| UINT64_C(2125527040), // FMINPv2i32p |
| UINT64_C(2129721344), // FMINPv2i64p |
| UINT64_C(784348160), // FMINPv4f16 |
| UINT64_C(1856041984), // FMINPv4f32 |
| UINT64_C(1858089984), // FMINPv8f16 |
| UINT64_C(505436160), // FMINSrr |
| UINT64_C(1707548672), // FMINV_VPZ_D |
| UINT64_C(1699160064), // FMINV_VPZ_H |
| UINT64_C(1703354368), // FMINV_VPZ_S |
| UINT64_C(246478848), // FMINVv4i16v |
| UINT64_C(1857091584), // FMINVv4i32v |
| UINT64_C(1320220672), // FMINVv8i16v |
| UINT64_C(1709146112), // FMIN_ZPmI_D |
| UINT64_C(1700757504), // FMIN_ZPmI_H |
| UINT64_C(1704951808), // FMIN_ZPmI_S |
| UINT64_C(1707573248), // FMIN_ZPmZ_D |
| UINT64_C(1699184640), // FMIN_ZPmZ_H |
| UINT64_C(1703378944), // FMIN_ZPmZ_S |
| UINT64_C(245429248), // FMINv2f32 |
| UINT64_C(1323365376), // FMINv2f64 |
| UINT64_C(247477248), // FMINv4f16 |
| UINT64_C(1319171072), // FMINv4f32 |
| UINT64_C(1321219072), // FMINv8f16 |
| UINT64_C(796950528), // FMLAL2lanev4f16 |
| UINT64_C(1870692352), // FMLAL2lanev8f16 |
| UINT64_C(773901312), // FMLAL2v4f16 |
| UINT64_C(1847643136), // FMLAL2v8f16 |
| UINT64_C(1688223744), // FMLALB_ZZZI_SHH |
| UINT64_C(1688240128), // FMLALB_ZZZ_SHH |
| UINT64_C(1688224768), // FMLALT_ZZZI_SHH |
| UINT64_C(1688241152), // FMLALT_ZZZ_SHH |
| UINT64_C(260046848), // FMLALlanev4f16 |
| UINT64_C(1333788672), // FMLALlanev8f16 |
| UINT64_C(237038592), // FMLALv4f16 |
| UINT64_C(1310780416), // FMLALv8f16 |
| UINT64_C(1709178880), // FMLA_ZPmZZ_D |
| UINT64_C(1700790272), // FMLA_ZPmZZ_H |
| UINT64_C(1704984576), // FMLA_ZPmZZ_S |
| UINT64_C(1692401664), // FMLA_ZZZI_D |
| UINT64_C(1679818752), // FMLA_ZZZI_H |
| UINT64_C(1688207360), // FMLA_ZZZI_S |
| UINT64_C(1593839616), // FMLAv1i16_indexed |
| UINT64_C(1602228224), // FMLAv1i32_indexed |
| UINT64_C(1606422528), // FMLAv1i64_indexed |
| UINT64_C(237030400), // FMLAv2f32 |
| UINT64_C(1314966528), // FMLAv2f64 |
| UINT64_C(260050944), // FMLAv2i32_indexed |
| UINT64_C(1337987072), // FMLAv2i64_indexed |
| UINT64_C(239078400), // FMLAv4f16 |
| UINT64_C(1310772224), // FMLAv4f32 |
| UINT64_C(251662336), // FMLAv4i16_indexed |
| UINT64_C(1333792768), // FMLAv4i32_indexed |
| UINT64_C(1312820224), // FMLAv8f16 |
| UINT64_C(1325404160), // FMLAv8i16_indexed |
| UINT64_C(796966912), // FMLSL2lanev4f16 |
| UINT64_C(1870708736), // FMLSL2lanev8f16 |
| UINT64_C(782289920), // FMLSL2v4f16 |
| UINT64_C(1856031744), // FMLSL2v8f16 |
| UINT64_C(1688231936), // FMLSLB_ZZZI_SHH |
| UINT64_C(1688248320), // FMLSLB_ZZZ_SHH |
| UINT64_C(1688232960), // FMLSLT_ZZZI_SHH |
| UINT64_C(1688249344), // FMLSLT_ZZZ_SHH |
| UINT64_C(260063232), // FMLSLlanev4f16 |
| UINT64_C(1333805056), // FMLSLlanev8f16 |
| UINT64_C(245427200), // FMLSLv4f16 |
| UINT64_C(1319169024), // FMLSLv8f16 |
| UINT64_C(1709187072), // FMLS_ZPmZZ_D |
| UINT64_C(1700798464), // FMLS_ZPmZZ_H |
| UINT64_C(1704992768), // FMLS_ZPmZZ_S |
| UINT64_C(1692402688), // FMLS_ZZZI_D |
| UINT64_C(1679819776), // FMLS_ZZZI_H |
| UINT64_C(1688208384), // FMLS_ZZZI_S |
| UINT64_C(1593856000), // FMLSv1i16_indexed |
| UINT64_C(1602244608), // FMLSv1i32_indexed |
| UINT64_C(1606438912), // FMLSv1i64_indexed |
| UINT64_C(245419008), // FMLSv2f32 |
| UINT64_C(1323355136), // FMLSv2f64 |
| UINT64_C(260067328), // FMLSv2i32_indexed |
| UINT64_C(1338003456), // FMLSv2i64_indexed |
| UINT64_C(247467008), // FMLSv4f16 |
| UINT64_C(1319160832), // FMLSv4f32 |
| UINT64_C(251678720), // FMLSv4i16_indexed |
| UINT64_C(1333809152), // FMLSv4i32_indexed |
| UINT64_C(1321208832), // FMLSv8f16 |
| UINT64_C(1325420544), // FMLSv8i16_indexed |
| UINT64_C(0), // FMOVD0 |
| UINT64_C(2662203392), // FMOVDXHighr |
| UINT64_C(2657484800), // FMOVDXr |
| UINT64_C(509612032), // FMOVDi |
| UINT64_C(509624320), // FMOVDr |
| UINT64_C(0), // FMOVH0 |
| UINT64_C(518389760), // FMOVHWr |
| UINT64_C(2665873408), // FMOVHXr |
| UINT64_C(518000640), // FMOVHi |
| UINT64_C(518012928), // FMOVHr |
| UINT64_C(0), // FMOVS0 |
| UINT64_C(505806848), // FMOVSWr |
| UINT64_C(505417728), // FMOVSi |
| UINT64_C(505430016), // FMOVSr |
| UINT64_C(518455296), // FMOVWHr |
| UINT64_C(505872384), // FMOVWSr |
| UINT64_C(2662268928), // FMOVXDHighr |
| UINT64_C(2657550336), // FMOVXDr |
| UINT64_C(2665938944), // FMOVXHr |
| UINT64_C(251720704), // FMOVv2f32_ns |
| UINT64_C(1862333440), // FMOVv2f64_ns |
| UINT64_C(251722752), // FMOVv4f16_ns |
| UINT64_C(1325462528), // FMOVv4f32_ns |
| UINT64_C(1325464576), // FMOVv8f16_ns |
| UINT64_C(1709219840), // FMSB_ZPmZZ_D |
| UINT64_C(1700831232), // FMSB_ZPmZZ_H |
| UINT64_C(1705025536), // FMSB_ZPmZZ_S |
| UINT64_C(524320768), // FMSUBDrrr |
| UINT64_C(532709376), // FMSUBHrrr |
| UINT64_C(520126464), // FMSUBSrrr |
| UINT64_C(509609984), // FMULDrr |
| UINT64_C(517998592), // FMULHrr |
| UINT64_C(505415680), // FMULSrr |
| UINT64_C(1581259776), // FMULX16 |
| UINT64_C(1579211776), // FMULX32 |
| UINT64_C(1583406080), // FMULX64 |
| UINT64_C(1707769856), // FMULX_ZPmZ_D |
| UINT64_C(1699381248), // FMULX_ZPmZ_H |
| UINT64_C(1703575552), // FMULX_ZPmZ_S |
| UINT64_C(2130743296), // FMULXv1i16_indexed |
| UINT64_C(2139131904), // FMULXv1i32_indexed |
| UINT64_C(2143326208), // FMULXv1i64_indexed |
| UINT64_C(237034496), // FMULXv2f32 |
| UINT64_C(1314970624), // FMULXv2f64 |
| UINT64_C(796954624), // FMULXv2i32_indexed |
| UINT64_C(1874890752), // FMULXv2i64_indexed |
| UINT64_C(239082496), // FMULXv4f16 |
| UINT64_C(1310776320), // FMULXv4f32 |
| UINT64_C(788566016), // FMULXv4i16_indexed |
| UINT64_C(1870696448), // FMULXv4i32_indexed |
| UINT64_C(1312824320), // FMULXv8f16 |
| UINT64_C(1862307840), // FMULXv8i16_indexed |
| UINT64_C(1708818432), // FMUL_ZPmI_D |
| UINT64_C(1700429824), // FMUL_ZPmI_H |
| UINT64_C(1704624128), // FMUL_ZPmI_S |
| UINT64_C(1707245568), // FMUL_ZPmZ_D |
| UINT64_C(1698856960), // FMUL_ZPmZ_H |
| UINT64_C(1703051264), // FMUL_ZPmZ_S |
| UINT64_C(1692409856), // FMUL_ZZZI_D |
| UINT64_C(1679826944), // FMUL_ZZZI_H |
| UINT64_C(1688215552), // FMUL_ZZZI_S |
| UINT64_C(1707083776), // FMUL_ZZZ_D |
| UINT64_C(1698695168), // FMUL_ZZZ_H |
| UINT64_C(1702889472), // FMUL_ZZZ_S |
| UINT64_C(1593872384), // FMULv1i16_indexed |
| UINT64_C(1602260992), // FMULv1i32_indexed |
| UINT64_C(1606455296), // FMULv1i64_indexed |
| UINT64_C(773905408), // FMULv2f32 |
| UINT64_C(1851841536), // FMULv2f64 |
| UINT64_C(260083712), // FMULv2i32_indexed |
| UINT64_C(1338019840), // FMULv2i64_indexed |
| UINT64_C(775953408), // FMULv4f16 |
| UINT64_C(1847647232), // FMULv4f32 |
| UINT64_C(251695104), // FMULv4i16_indexed |
| UINT64_C(1333825536), // FMULv4i32_indexed |
| UINT64_C(1849695232), // FMULv8f16 |
| UINT64_C(1325436928), // FMULv8i16_indexed |
| UINT64_C(509689856), // FNEGDr |
| UINT64_C(518078464), // FNEGHr |
| UINT64_C(505495552), // FNEGSr |
| UINT64_C(81633280), // FNEG_ZPmZ_D |
| UINT64_C(73244672), // FNEG_ZPmZ_H |
| UINT64_C(77438976), // FNEG_ZPmZ_S |
| UINT64_C(782301184), // FNEGv2f32 |
| UINT64_C(1860237312), // FNEGv2f64 |
| UINT64_C(788068352), // FNEGv4f16 |
| UINT64_C(1856043008), // FNEGv4f32 |
| UINT64_C(1861810176), // FNEGv8f16 |
| UINT64_C(526385152), // FNMADDDrrr |
| UINT64_C(534773760), // FNMADDHrrr |
| UINT64_C(522190848), // FNMADDSrrr |
| UINT64_C(1709228032), // FNMAD_ZPmZZ_D |
| UINT64_C(1700839424), // FNMAD_ZPmZZ_H |
| UINT64_C(1705033728), // FNMAD_ZPmZZ_S |
| UINT64_C(1709195264), // FNMLA_ZPmZZ_D |
| UINT64_C(1700806656), // FNMLA_ZPmZZ_H |
| UINT64_C(1705000960), // FNMLA_ZPmZZ_S |
| UINT64_C(1709203456), // FNMLS_ZPmZZ_D |
| UINT64_C(1700814848), // FNMLS_ZPmZZ_H |
| UINT64_C(1705009152), // FNMLS_ZPmZZ_S |
| UINT64_C(1709236224), // FNMSB_ZPmZZ_D |
| UINT64_C(1700847616), // FNMSB_ZPmZZ_H |
| UINT64_C(1705041920), // FNMSB_ZPmZZ_S |
| UINT64_C(526417920), // FNMSUBDrrr |
| UINT64_C(534806528), // FNMSUBHrrr |
| UINT64_C(522223616), // FNMSUBSrrr |
| UINT64_C(509642752), // FNMULDrr |
| UINT64_C(518031360), // FNMULHrr |
| UINT64_C(505448448), // FNMULSrr |
| UINT64_C(1708011520), // FRECPE_ZZ_D |
| UINT64_C(1699622912), // FRECPE_ZZ_H |
| UINT64_C(1703817216), // FRECPE_ZZ_S |
| UINT64_C(1593432064), // FRECPEv1f16 |
| UINT64_C(1587664896), // FRECPEv1i32 |
| UINT64_C(1591859200), // FRECPEv1i64 |
| UINT64_C(245487616), // FRECPEv2f32 |
| UINT64_C(1323423744), // FRECPEv2f64 |
| UINT64_C(251254784), // FRECPEv4f16 |
| UINT64_C(1319229440), // FRECPEv4f32 |
| UINT64_C(1324996608), // FRECPEv8f16 |
| UINT64_C(1581267968), // FRECPS16 |
| UINT64_C(1579219968), // FRECPS32 |
| UINT64_C(1583414272), // FRECPS64 |
| UINT64_C(1707087872), // FRECPS_ZZZ_D |
| UINT64_C(1698699264), // FRECPS_ZZZ_H |
| UINT64_C(1702893568), // FRECPS_ZZZ_S |
| UINT64_C(237042688), // FRECPSv2f32 |
| UINT64_C(1314978816), // FRECPSv2f64 |
| UINT64_C(239090688), // FRECPSv4f16 |
| UINT64_C(1310784512), // FRECPSv4f32 |
| UINT64_C(1312832512), // FRECPSv8f16 |
| UINT64_C(1707909120), // FRECPX_ZPmZ_D |
| UINT64_C(1699520512), // FRECPX_ZPmZ_H |
| UINT64_C(1703714816), // FRECPX_ZPmZ_S |
| UINT64_C(1593440256), // FRECPXv1f16 |
| UINT64_C(1587673088), // FRECPXv1i32 |
| UINT64_C(1591867392), // FRECPXv1i64 |
| UINT64_C(510181376), // FRINT32XDr |
| UINT64_C(505987072), // FRINT32XSr |
| UINT64_C(773974016), // FRINT32Xv2f32 |
| UINT64_C(1851910144), // FRINT32Xv2f64 |
| UINT64_C(1847715840), // FRINT32Xv4f32 |
| UINT64_C(510148608), // FRINT32ZDr |
| UINT64_C(505954304), // FRINT32ZSr |
| UINT64_C(237103104), // FRINT32Zv2f32 |
| UINT64_C(1315039232), // FRINT32Zv2f64 |
| UINT64_C(1310844928), // FRINT32Zv4f32 |
| UINT64_C(510246912), // FRINT64XDr |
| UINT64_C(506052608), // FRINT64XSr |
| UINT64_C(773978112), // FRINT64Xv2f32 |
| UINT64_C(1851914240), // FRINT64Xv2f64 |
| UINT64_C(1847719936), // FRINT64Xv4f32 |
| UINT64_C(510214144), // FRINT64ZDr |
| UINT64_C(506019840), // FRINT64ZSr |
| UINT64_C(237107200), // FRINT64Zv2f32 |
| UINT64_C(1315043328), // FRINT64Zv2f64 |
| UINT64_C(1310849024), // FRINT64Zv4f32 |
| UINT64_C(510017536), // FRINTADr |
| UINT64_C(518406144), // FRINTAHr |
| UINT64_C(505823232), // FRINTASr |
| UINT64_C(1707384832), // FRINTA_ZPmZ_D |
| UINT64_C(1698996224), // FRINTA_ZPmZ_H |
| UINT64_C(1703190528), // FRINTA_ZPmZ_S |
| UINT64_C(773949440), // FRINTAv2f32 |
| UINT64_C(1851885568), // FRINTAv2f64 |
| UINT64_C(779716608), // FRINTAv4f16 |
| UINT64_C(1847691264), // FRINTAv4f32 |
| UINT64_C(1853458432), // FRINTAv8f16 |
| UINT64_C(510115840), // FRINTIDr |
| UINT64_C(518504448), // FRINTIHr |
| UINT64_C(505921536), // FRINTISr |
| UINT64_C(1707581440), // FRINTI_ZPmZ_D |
| UINT64_C(1699192832), // FRINTI_ZPmZ_H |
| UINT64_C(1703387136), // FRINTI_ZPmZ_S |
| UINT64_C(782342144), // FRINTIv2f32 |
| UINT64_C(1860278272), // FRINTIv2f64 |
| UINT64_C(788109312), // FRINTIv4f16 |
| UINT64_C(1856083968), // FRINTIv4f32 |
| UINT64_C(1861851136), // FRINTIv8f16 |
| UINT64_C(509952000), // FRINTMDr |
| UINT64_C(518340608), // FRINTMHr |
| UINT64_C(505757696), // FRINTMSr |
| UINT64_C(1707253760), // FRINTM_ZPmZ_D |
| UINT64_C(1698865152), // FRINTM_ZPmZ_H |
| UINT64_C(1703059456), // FRINTM_ZPmZ_S |
| UINT64_C(237082624), // FRINTMv2f32 |
| UINT64_C(1315018752), // FRINTMv2f64 |
| UINT64_C(242849792), // FRINTMv4f16 |
| UINT64_C(1310824448), // FRINTMv4f32 |
| UINT64_C(1316591616), // FRINTMv8f16 |
| UINT64_C(509886464), // FRINTNDr |
| UINT64_C(518275072), // FRINTNHr |
| UINT64_C(505692160), // FRINTNSr |
| UINT64_C(1707122688), // FRINTN_ZPmZ_D |
| UINT64_C(1698734080), // FRINTN_ZPmZ_H |
| UINT64_C(1702928384), // FRINTN_ZPmZ_S |
| UINT64_C(237078528), // FRINTNv2f32 |
| UINT64_C(1315014656), // FRINTNv2f64 |
| UINT64_C(242845696), // FRINTNv4f16 |
| UINT64_C(1310820352), // FRINTNv4f32 |
| UINT64_C(1316587520), // FRINTNv8f16 |
| UINT64_C(509919232), // FRINTPDr |
| UINT64_C(518307840), // FRINTPHr |
| UINT64_C(505724928), // FRINTPSr |
| UINT64_C(1707188224), // FRINTP_ZPmZ_D |
| UINT64_C(1698799616), // FRINTP_ZPmZ_H |
| UINT64_C(1702993920), // FRINTP_ZPmZ_S |
| UINT64_C(245467136), // FRINTPv2f32 |
| UINT64_C(1323403264), // FRINTPv2f64 |
| UINT64_C(251234304), // FRINTPv4f16 |
| UINT64_C(1319208960), // FRINTPv4f32 |
| UINT64_C(1324976128), // FRINTPv8f16 |
| UINT64_C(510083072), // FRINTXDr |
| UINT64_C(518471680), // FRINTXHr |
| UINT64_C(505888768), // FRINTXSr |
| UINT64_C(1707515904), // FRINTX_ZPmZ_D |
| UINT64_C(1699127296), // FRINTX_ZPmZ_H |
| UINT64_C(1703321600), // FRINTX_ZPmZ_S |
| UINT64_C(773953536), // FRINTXv2f32 |
| UINT64_C(1851889664), // FRINTXv2f64 |
| UINT64_C(779720704), // FRINTXv4f16 |
| UINT64_C(1847695360), // FRINTXv4f32 |
| UINT64_C(1853462528), // FRINTXv8f16 |
| UINT64_C(509984768), // FRINTZDr |
| UINT64_C(518373376), // FRINTZHr |
| UINT64_C(505790464), // FRINTZSr |
| UINT64_C(1707319296), // FRINTZ_ZPmZ_D |
| UINT64_C(1698930688), // FRINTZ_ZPmZ_H |
| UINT64_C(1703124992), // FRINTZ_ZPmZ_S |
| UINT64_C(245471232), // FRINTZv2f32 |
| UINT64_C(1323407360), // FRINTZv2f64 |
| UINT64_C(251238400), // FRINTZv4f16 |
| UINT64_C(1319213056), // FRINTZv4f32 |
| UINT64_C(1324980224), // FRINTZv8f16 |
| UINT64_C(1708077056), // FRSQRTE_ZZ_D |
| UINT64_C(1699688448), // FRSQRTE_ZZ_H |
| UINT64_C(1703882752), // FRSQRTE_ZZ_S |
| UINT64_C(2130302976), // FRSQRTEv1f16 |
| UINT64_C(2124535808), // FRSQRTEv1i32 |
| UINT64_C(2128730112), // FRSQRTEv1i64 |
| UINT64_C(782358528), // FRSQRTEv2f32 |
| UINT64_C(1860294656), // FRSQRTEv2f64 |
| UINT64_C(788125696), // FRSQRTEv4f16 |
| UINT64_C(1856100352), // FRSQRTEv4f32 |
| UINT64_C(1861867520), // FRSQRTEv8f16 |
| UINT64_C(1589656576), // FRSQRTS16 |
| UINT64_C(1587608576), // FRSQRTS32 |
| UINT64_C(1591802880), // FRSQRTS64 |
| UINT64_C(1707088896), // FRSQRTS_ZZZ_D |
| UINT64_C(1698700288), // FRSQRTS_ZZZ_H |
| UINT64_C(1702894592), // FRSQRTS_ZZZ_S |
| UINT64_C(245431296), // FRSQRTSv2f32 |
| UINT64_C(1323367424), // FRSQRTSv2f64 |
| UINT64_C(247479296), // FRSQRTSv4f16 |
| UINT64_C(1319173120), // FRSQRTSv4f32 |
| UINT64_C(1321221120), // FRSQRTSv8f16 |
| UINT64_C(1707704320), // FSCALE_ZPmZ_D |
| UINT64_C(1699315712), // FSCALE_ZPmZ_H |
| UINT64_C(1703510016), // FSCALE_ZPmZ_S |
| UINT64_C(509722624), // FSQRTDr |
| UINT64_C(518111232), // FSQRTHr |
| UINT64_C(505528320), // FSQRTSr |
| UINT64_C(1707974656), // FSQRT_ZPmZ_D |
| UINT64_C(1699586048), // FSQRT_ZPmZ_H |
| UINT64_C(1703780352), // FSQRT_ZPmZ_S |
| UINT64_C(782366720), // FSQRTv2f32 |
| UINT64_C(1860302848), // FSQRTv2f64 |
| UINT64_C(788133888), // FSQRTv4f16 |
| UINT64_C(1856108544), // FSQRTv4f32 |
| UINT64_C(1861875712), // FSQRTv8f16 |
| UINT64_C(509622272), // FSUBDrr |
| UINT64_C(518010880), // FSUBHrr |
| UINT64_C(1708883968), // FSUBR_ZPmI_D |
| UINT64_C(1700495360), // FSUBR_ZPmI_H |
| UINT64_C(1704689664), // FSUBR_ZPmI_S |
| UINT64_C(1707311104), // FSUBR_ZPmZ_D |
| UINT64_C(1698922496), // FSUBR_ZPmZ_H |
| UINT64_C(1703116800), // FSUBR_ZPmZ_S |
| UINT64_C(505427968), // FSUBSrr |
| UINT64_C(1708752896), // FSUB_ZPmI_D |
| UINT64_C(1700364288), // FSUB_ZPmI_H |
| UINT64_C(1704558592), // FSUB_ZPmI_S |
| UINT64_C(1707180032), // FSUB_ZPmZ_D |
| UINT64_C(1698791424), // FSUB_ZPmZ_H |
| UINT64_C(1702985728), // FSUB_ZPmZ_S |
| UINT64_C(1707082752), // FSUB_ZZZ_D |
| UINT64_C(1698694144), // FSUB_ZZZ_H |
| UINT64_C(1702888448), // FSUB_ZZZ_S |
| UINT64_C(245421056), // FSUBv2f32 |
| UINT64_C(1323357184), // FSUBv2f64 |
| UINT64_C(247469056), // FSUBv4f16 |
| UINT64_C(1319162880), // FSUBv4f32 |
| UINT64_C(1321210880), // FSUBv8f16 |
| UINT64_C(1708163072), // FTMAD_ZZI_D |
| UINT64_C(1699774464), // FTMAD_ZZI_H |
| UINT64_C(1703968768), // FTMAD_ZZI_S |
| UINT64_C(1707084800), // FTSMUL_ZZZ_D |
| UINT64_C(1698696192), // FTSMUL_ZZZ_H |
| UINT64_C(1702890496), // FTSMUL_ZZZ_S |
| UINT64_C(81833984), // FTSSEL_ZZZ_D |
| UINT64_C(73445376), // FTSSEL_ZZZ_H |
| UINT64_C(77639680), // FTSSEL_ZZZ_S |
| UINT64_C(3290480640), // GLD1B_D_IMM_REAL |
| UINT64_C(3292577792), // GLD1B_D_REAL |
| UINT64_C(3292545024), // GLD1B_D_SXTW_REAL |
| UINT64_C(3288350720), // GLD1B_D_UXTW_REAL |
| UINT64_C(2216738816), // GLD1B_S_IMM_REAL |
| UINT64_C(2218803200), // GLD1B_S_SXTW_REAL |
| UINT64_C(2214608896), // GLD1B_S_UXTW_REAL |
| UINT64_C(3315646464), // GLD1D_IMM_REAL |
| UINT64_C(3317743616), // GLD1D_REAL |
| UINT64_C(3319840768), // GLD1D_SCALED_REAL |
| UINT64_C(3317710848), // GLD1D_SXTW_REAL |
| UINT64_C(3319808000), // GLD1D_SXTW_SCALED_REAL |
| UINT64_C(3313516544), // GLD1D_UXTW_REAL |
| UINT64_C(3315613696), // GLD1D_UXTW_SCALED_REAL |
| UINT64_C(3298869248), // GLD1H_D_IMM_REAL |
| UINT64_C(3300966400), // GLD1H_D_REAL |
| UINT64_C(3303063552), // GLD1H_D_SCALED_REAL |
| UINT64_C(3300933632), // GLD1H_D_SXTW_REAL |
| UINT64_C(3303030784), // GLD1H_D_SXTW_SCALED_REAL |
| UINT64_C(3296739328), // GLD1H_D_UXTW_REAL |
| UINT64_C(3298836480), // GLD1H_D_UXTW_SCALED_REAL |
| UINT64_C(2225127424), // GLD1H_S_IMM_REAL |
| UINT64_C(2227191808), // GLD1H_S_SXTW_REAL |
| UINT64_C(2229288960), // GLD1H_S_SXTW_SCALED_REAL |
| UINT64_C(2222997504), // GLD1H_S_UXTW_REAL |
| UINT64_C(2225094656), // GLD1H_S_UXTW_SCALED_REAL |
| UINT64_C(3290464256), // GLD1SB_D_IMM_REAL |
| UINT64_C(3292561408), // GLD1SB_D_REAL |
| UINT64_C(3292528640), // GLD1SB_D_SXTW_REAL |
| UINT64_C(3288334336), // GLD1SB_D_UXTW_REAL |
| UINT64_C(2216722432), // GLD1SB_S_IMM_REAL |
| UINT64_C(2218786816), // GLD1SB_S_SXTW_REAL |
| UINT64_C(2214592512), // GLD1SB_S_UXTW_REAL |
| UINT64_C(3298852864), // GLD1SH_D_IMM_REAL |
| UINT64_C(3300950016), // GLD1SH_D_REAL |
| UINT64_C(3303047168), // GLD1SH_D_SCALED_REAL |
| UINT64_C(3300917248), // GLD1SH_D_SXTW_REAL |
| UINT64_C(3303014400), // GLD1SH_D_SXTW_SCALED_REAL |
| UINT64_C(3296722944), // GLD1SH_D_UXTW_REAL |
| UINT64_C(3298820096), // GLD1SH_D_UXTW_SCALED_REAL |
| UINT64_C(2225111040), // GLD1SH_S_IMM_REAL |
| UINT64_C(2227175424), // GLD1SH_S_SXTW_REAL |
| UINT64_C(2229272576), // GLD1SH_S_SXTW_SCALED_REAL |
| UINT64_C(2222981120), // GLD1SH_S_UXTW_REAL |
| UINT64_C(2225078272), // GLD1SH_S_UXTW_SCALED_REAL |
| UINT64_C(3307241472), // GLD1SW_D_IMM_REAL |
| UINT64_C(3309338624), // GLD1SW_D_REAL |
| UINT64_C(3311435776), // GLD1SW_D_SCALED_REAL |
| UINT64_C(3309305856), // GLD1SW_D_SXTW_REAL |
| UINT64_C(3311403008), // GLD1SW_D_SXTW_SCALED_REAL |
| UINT64_C(3305111552), // GLD1SW_D_UXTW_REAL |
| UINT64_C(3307208704), // GLD1SW_D_UXTW_SCALED_REAL |
| UINT64_C(3307257856), // GLD1W_D_IMM_REAL |
| UINT64_C(3309355008), // GLD1W_D_REAL |
| UINT64_C(3311452160), // GLD1W_D_SCALED_REAL |
| UINT64_C(3309322240), // GLD1W_D_SXTW_REAL |
| UINT64_C(3311419392), // GLD1W_D_SXTW_SCALED_REAL |
| UINT64_C(3305127936), // GLD1W_D_UXTW_REAL |
| UINT64_C(3307225088), // GLD1W_D_UXTW_SCALED_REAL |
| UINT64_C(2233516032), // GLD1W_IMM_REAL |
| UINT64_C(2235580416), // GLD1W_SXTW_REAL |
| UINT64_C(2237677568), // GLD1W_SXTW_SCALED_REAL |
| UINT64_C(2231386112), // GLD1W_UXTW_REAL |
| UINT64_C(2233483264), // GLD1W_UXTW_SCALED_REAL |
| UINT64_C(3290488832), // GLDFF1B_D_IMM_REAL |
| UINT64_C(3292585984), // GLDFF1B_D_REAL |
| UINT64_C(3292553216), // GLDFF1B_D_SXTW_REAL |
| UINT64_C(3288358912), // GLDFF1B_D_UXTW_REAL |
| UINT64_C(2216747008), // GLDFF1B_S_IMM_REAL |
| UINT64_C(2218811392), // GLDFF1B_S_SXTW_REAL |
| UINT64_C(2214617088), // GLDFF1B_S_UXTW_REAL |
| UINT64_C(3315654656), // GLDFF1D_IMM_REAL |
| UINT64_C(3317751808), // GLDFF1D_REAL |
| UINT64_C(3319848960), // GLDFF1D_SCALED_REAL |
| UINT64_C(3317719040), // GLDFF1D_SXTW_REAL |
| UINT64_C(3319816192), // GLDFF1D_SXTW_SCALED_REAL |
| UINT64_C(3313524736), // GLDFF1D_UXTW_REAL |
| UINT64_C(3315621888), // GLDFF1D_UXTW_SCALED_REAL |
| UINT64_C(3298877440), // GLDFF1H_D_IMM_REAL |
| UINT64_C(3300974592), // GLDFF1H_D_REAL |
| UINT64_C(3303071744), // GLDFF1H_D_SCALED_REAL |
| UINT64_C(3300941824), // GLDFF1H_D_SXTW_REAL |
| UINT64_C(3303038976), // GLDFF1H_D_SXTW_SCALED_REAL |
| UINT64_C(3296747520), // GLDFF1H_D_UXTW_REAL |
| UINT64_C(3298844672), // GLDFF1H_D_UXTW_SCALED_REAL |
| UINT64_C(2225135616), // GLDFF1H_S_IMM_REAL |
| UINT64_C(2227200000), // GLDFF1H_S_SXTW_REAL |
| UINT64_C(2229297152), // GLDFF1H_S_SXTW_SCALED_REAL |
| UINT64_C(2223005696), // GLDFF1H_S_UXTW_REAL |
| UINT64_C(2225102848), // GLDFF1H_S_UXTW_SCALED_REAL |
| UINT64_C(3290472448), // GLDFF1SB_D_IMM_REAL |
| UINT64_C(3292569600), // GLDFF1SB_D_REAL |
| UINT64_C(3292536832), // GLDFF1SB_D_SXTW_REAL |
| UINT64_C(3288342528), // GLDFF1SB_D_UXTW_REAL |
| UINT64_C(2216730624), // GLDFF1SB_S_IMM_REAL |
| UINT64_C(2218795008), // GLDFF1SB_S_SXTW_REAL |
| UINT64_C(2214600704), // GLDFF1SB_S_UXTW_REAL |
| UINT64_C(3298861056), // GLDFF1SH_D_IMM_REAL |
| UINT64_C(3300958208), // GLDFF1SH_D_REAL |
| UINT64_C(3303055360), // GLDFF1SH_D_SCALED_REAL |
| UINT64_C(3300925440), // GLDFF1SH_D_SXTW_REAL |
| UINT64_C(3303022592), // GLDFF1SH_D_SXTW_SCALED_REAL |
| UINT64_C(3296731136), // GLDFF1SH_D_UXTW_REAL |
| UINT64_C(3298828288), // GLDFF1SH_D_UXTW_SCALED_REAL |
| UINT64_C(2225119232), // GLDFF1SH_S_IMM_REAL |
| UINT64_C(2227183616), // GLDFF1SH_S_SXTW_REAL |
| UINT64_C(2229280768), // GLDFF1SH_S_SXTW_SCALED_REAL |
| UINT64_C(2222989312), // GLDFF1SH_S_UXTW_REAL |
| UINT64_C(2225086464), // GLDFF1SH_S_UXTW_SCALED_REAL |
| UINT64_C(3307249664), // GLDFF1SW_D_IMM_REAL |
| UINT64_C(3309346816), // GLDFF1SW_D_REAL |
| UINT64_C(3311443968), // GLDFF1SW_D_SCALED_REAL |
| UINT64_C(3309314048), // GLDFF1SW_D_SXTW_REAL |
| UINT64_C(3311411200), // GLDFF1SW_D_SXTW_SCALED_REAL |
| UINT64_C(3305119744), // GLDFF1SW_D_UXTW_REAL |
| UINT64_C(3307216896), // GLDFF1SW_D_UXTW_SCALED_REAL |
| UINT64_C(3307266048), // GLDFF1W_D_IMM_REAL |
| UINT64_C(3309363200), // GLDFF1W_D_REAL |
| UINT64_C(3311460352), // GLDFF1W_D_SCALED_REAL |
| UINT64_C(3309330432), // GLDFF1W_D_SXTW_REAL |
| UINT64_C(3311427584), // GLDFF1W_D_SXTW_SCALED_REAL |
| UINT64_C(3305136128), // GLDFF1W_D_UXTW_REAL |
| UINT64_C(3307233280), // GLDFF1W_D_UXTW_SCALED_REAL |
| UINT64_C(2233524224), // GLDFF1W_IMM_REAL |
| UINT64_C(2235588608), // GLDFF1W_SXTW_REAL |
| UINT64_C(2237685760), // GLDFF1W_SXTW_SCALED_REAL |
| UINT64_C(2231394304), // GLDFF1W_UXTW_REAL |
| UINT64_C(2233491456), // GLDFF1W_UXTW_SCALED_REAL |
| UINT64_C(2596279296), // GMI |
| UINT64_C(3573751839), // HINT |
| UINT64_C(1172357120), // HISTCNT_ZPzZZ_D |
| UINT64_C(1168162816), // HISTCNT_ZPzZZ_S |
| UINT64_C(1159766016), // HISTSEG_ZZZ |
| UINT64_C(3560964096), // HLT |
| UINT64_C(3556769794), // HVC |
| UINT64_C(0), // HWASAN_CHECK_MEMACCESS |
| UINT64_C(0), // HWASAN_CHECK_MEMACCESS_SHORTGRANULES |
| UINT64_C(70311936), // INCB_XPiI |
| UINT64_C(82894848), // INCD_XPiI |
| UINT64_C(82886656), // INCD_ZPiI |
| UINT64_C(74506240), // INCH_XPiI |
| UINT64_C(74498048), // INCH_ZPiI |
| UINT64_C(623675392), // INCP_XP_B |
| UINT64_C(636258304), // INCP_XP_D |
| UINT64_C(627869696), // INCP_XP_H |
| UINT64_C(632064000), // INCP_XP_S |
| UINT64_C(636256256), // INCP_ZP_D |
| UINT64_C(627867648), // INCP_ZP_H |
| UINT64_C(632061952), // INCP_ZP_S |
| UINT64_C(78700544), // INCW_XPiI |
| UINT64_C(78692352), // INCW_ZPiI |
| UINT64_C(69222400), // INDEX_II_B |
| UINT64_C(81805312), // INDEX_II_D |
| UINT64_C(73416704), // INDEX_II_H |
| UINT64_C(77611008), // INDEX_II_S |
| UINT64_C(69224448), // INDEX_IR_B |
| UINT64_C(81807360), // INDEX_IR_D |
| UINT64_C(73418752), // INDEX_IR_H |
| UINT64_C(77613056), // INDEX_IR_S |
| UINT64_C(69223424), // INDEX_RI_B |
| UINT64_C(81806336), // INDEX_RI_D |
| UINT64_C(73417728), // INDEX_RI_H |
| UINT64_C(77612032), // INDEX_RI_S |
| UINT64_C(69225472), // INDEX_RR_B |
| UINT64_C(81808384), // INDEX_RR_D |
| UINT64_C(73419776), // INDEX_RR_H |
| UINT64_C(77614080), // INDEX_RR_S |
| UINT64_C(86259712), // INSR_ZR_B |
| UINT64_C(98842624), // INSR_ZR_D |
| UINT64_C(90454016), // INSR_ZR_H |
| UINT64_C(94648320), // INSR_ZR_S |
| UINT64_C(87308288), // INSR_ZV_B |
| UINT64_C(99891200), // INSR_ZV_D |
| UINT64_C(91502592), // INSR_ZV_H |
| UINT64_C(95696896), // INSR_ZV_S |
| UINT64_C(1308761088), // INSvi16gpr |
| UINT64_C(1845625856), // INSvi16lane |
| UINT64_C(1308892160), // INSvi32gpr |
| UINT64_C(1845756928), // INSvi32lane |
| UINT64_C(1309154304), // INSvi64gpr |
| UINT64_C(1846019072), // INSvi64lane |
| UINT64_C(1308695552), // INSvi8gpr |
| UINT64_C(1845560320), // INSvi8lane |
| UINT64_C(2596278272), // IRG |
| UINT64_C(0), // IRGstack |
| UINT64_C(3573756127), // ISB |
| UINT64_C(0), // JumpTableDest16 |
| UINT64_C(0), // JumpTableDest32 |
| UINT64_C(0), // JumpTableDest8 |
| UINT64_C(86024192), // LASTA_RPZ_B |
| UINT64_C(98607104), // LASTA_RPZ_D |
| UINT64_C(90218496), // LASTA_RPZ_H |
| UINT64_C(94412800), // LASTA_RPZ_S |
| UINT64_C(86147072), // LASTA_VPZ_B |
| UINT64_C(98729984), // LASTA_VPZ_D |
| UINT64_C(90341376), // LASTA_VPZ_H |
| UINT64_C(94535680), // LASTA_VPZ_S |
| UINT64_C(86089728), // LASTB_RPZ_B |
| UINT64_C(98672640), // LASTB_RPZ_D |
| UINT64_C(90284032), // LASTB_RPZ_H |
| UINT64_C(94478336), // LASTB_RPZ_S |
| UINT64_C(86212608), // LASTB_VPZ_B |
| UINT64_C(98795520), // LASTB_VPZ_D |
| UINT64_C(90406912), // LASTB_VPZ_H |
| UINT64_C(94601216), // LASTB_VPZ_S |
| UINT64_C(2751479808), // LD1B |
| UINT64_C(2757771264), // LD1B_D |
| UINT64_C(2757795840), // LD1B_D_IMM |
| UINT64_C(2753576960), // LD1B_H |
| UINT64_C(2753601536), // LD1B_H_IMM |
| UINT64_C(2751504384), // LD1B_IMM |
| UINT64_C(2755674112), // LD1B_S |
| UINT64_C(2755698688), // LD1B_S_IMM |
| UINT64_C(2782937088), // LD1D |
| UINT64_C(2782961664), // LD1D_IMM |
| UINT64_C(1279270912), // LD1Fourv16b |
| UINT64_C(1287659520), // LD1Fourv16b_POST |
| UINT64_C(205532160), // LD1Fourv1d |
| UINT64_C(213920768), // LD1Fourv1d_POST |
| UINT64_C(1279273984), // LD1Fourv2d |
| UINT64_C(1287662592), // LD1Fourv2d_POST |
| UINT64_C(205531136), // LD1Fourv2s |
| UINT64_C(213919744), // LD1Fourv2s_POST |
| UINT64_C(205530112), // LD1Fourv4h |
| UINT64_C(213918720), // LD1Fourv4h_POST |
| UINT64_C(1279272960), // LD1Fourv4s |
| UINT64_C(1287661568), // LD1Fourv4s_POST |
| UINT64_C(205529088), // LD1Fourv8b |
| UINT64_C(213917696), // LD1Fourv8b_POST |
| UINT64_C(1279271936), // LD1Fourv8h |
| UINT64_C(1287660544), // LD1Fourv8h_POST |
| UINT64_C(2761965568), // LD1H |
| UINT64_C(2766159872), // LD1H_D |
| UINT64_C(2766184448), // LD1H_D_IMM |
| UINT64_C(2761990144), // LD1H_IMM |
| UINT64_C(2764062720), // LD1H_S |
| UINT64_C(2764087296), // LD1H_S_IMM |
| UINT64_C(1279291392), // LD1Onev16b |
| UINT64_C(1287680000), // LD1Onev16b_POST |
| UINT64_C(205552640), // LD1Onev1d |
| UINT64_C(213941248), // LD1Onev1d_POST |
| UINT64_C(1279294464), // LD1Onev2d |
| UINT64_C(1287683072), // LD1Onev2d_POST |
| UINT64_C(205551616), // LD1Onev2s |
| UINT64_C(213940224), // LD1Onev2s_POST |
| UINT64_C(205550592), // LD1Onev4h |
| UINT64_C(213939200), // LD1Onev4h_POST |
| UINT64_C(1279293440), // LD1Onev4s |
| UINT64_C(1287682048), // LD1Onev4s_POST |
| UINT64_C(205549568), // LD1Onev8b |
| UINT64_C(213938176), // LD1Onev8b_POST |
| UINT64_C(1279292416), // LD1Onev8h |
| UINT64_C(1287681024), // LD1Onev8h_POST |
| UINT64_C(2218844160), // LD1RB_D_IMM |
| UINT64_C(2218827776), // LD1RB_H_IMM |
| UINT64_C(2218819584), // LD1RB_IMM |
| UINT64_C(2218835968), // LD1RB_S_IMM |
| UINT64_C(2244009984), // LD1RD_IMM |
| UINT64_C(2227232768), // LD1RH_D_IMM |
| UINT64_C(2227216384), // LD1RH_IMM |
| UINT64_C(2227224576), // LD1RH_S_IMM |
| UINT64_C(2751463424), // LD1RQ_B |
| UINT64_C(2751471616), // LD1RQ_B_IMM |
| UINT64_C(2776629248), // LD1RQ_D |
| UINT64_C(2776637440), // LD1RQ_D_IMM |
| UINT64_C(2759852032), // LD1RQ_H |
| UINT64_C(2759860224), // LD1RQ_H_IMM |
| UINT64_C(2768240640), // LD1RQ_W |
| UINT64_C(2768248832), // LD1RQ_W_IMM |
| UINT64_C(2243985408), // LD1RSB_D_IMM |
| UINT64_C(2244001792), // LD1RSB_H_IMM |
| UINT64_C(2243993600), // LD1RSB_S_IMM |
| UINT64_C(2235596800), // LD1RSH_D_IMM |
| UINT64_C(2235604992), // LD1RSH_S_IMM |
| UINT64_C(2227208192), // LD1RSW_IMM |
| UINT64_C(2235621376), // LD1RW_D_IMM |
| UINT64_C(2235613184), // LD1RW_IMM |
| UINT64_C(1296089088), // LD1Rv16b |
| UINT64_C(1304477696), // LD1Rv16b_POST |
| UINT64_C(222350336), // LD1Rv1d |
| UINT64_C(230738944), // LD1Rv1d_POST |
| UINT64_C(1296092160), // LD1Rv2d |
| UINT64_C(1304480768), // LD1Rv2d_POST |
| UINT64_C(222349312), // LD1Rv2s |
| UINT64_C(230737920), // LD1Rv2s_POST |
| UINT64_C(222348288), // LD1Rv4h |
| UINT64_C(230736896), // LD1Rv4h_POST |
| UINT64_C(1296091136), // LD1Rv4s |
| UINT64_C(1304479744), // LD1Rv4s_POST |
| UINT64_C(222347264), // LD1Rv8b |
| UINT64_C(230735872), // LD1Rv8b_POST |
| UINT64_C(1296090112), // LD1Rv8h |
| UINT64_C(1304478720), // LD1Rv8h_POST |
| UINT64_C(2776645632), // LD1SB_D |
| UINT64_C(2776670208), // LD1SB_D_IMM |
| UINT64_C(2780839936), // LD1SB_H |
| UINT64_C(2780864512), // LD1SB_H_IMM |
| UINT64_C(2778742784), // LD1SB_S |
| UINT64_C(2778767360), // LD1SB_S_IMM |
| UINT64_C(2768257024), // LD1SH_D |
| UINT64_C(2768281600), // LD1SH_D_IMM |
| UINT64_C(2770354176), // LD1SH_S |
| UINT64_C(2770378752), // LD1SH_S_IMM |
| UINT64_C(2759868416), // LD1SW_D |
| UINT64_C(2759892992), // LD1SW_D_IMM |
| UINT64_C(1279287296), // LD1Threev16b |
| UINT64_C(1287675904), // LD1Threev16b_POST |
| UINT64_C(205548544), // LD1Threev1d |
| UINT64_C(213937152), // LD1Threev1d_POST |
| UINT64_C(1279290368), // LD1Threev2d |
| UINT64_C(1287678976), // LD1Threev2d_POST |
| UINT64_C(205547520), // LD1Threev2s |
| UINT64_C(213936128), // LD1Threev2s_POST |
| UINT64_C(205546496), // LD1Threev4h |
| UINT64_C(213935104), // LD1Threev4h_POST |
| UINT64_C(1279289344), // LD1Threev4s |
| UINT64_C(1287677952), // LD1Threev4s_POST |
| UINT64_C(205545472), // LD1Threev8b |
| UINT64_C(213934080), // LD1Threev8b_POST |
| UINT64_C(1279288320), // LD1Threev8h |
| UINT64_C(1287676928), // LD1Threev8h_POST |
| UINT64_C(1279303680), // LD1Twov16b |
| UINT64_C(1287692288), // LD1Twov16b_POST |
| UINT64_C(205564928), // LD1Twov1d |
| UINT64_C(213953536), // LD1Twov1d_POST |
| UINT64_C(1279306752), // LD1Twov2d |
| UINT64_C(1287695360), // LD1Twov2d_POST |
| UINT64_C(205563904), // LD1Twov2s |
| UINT64_C(213952512), // LD1Twov2s_POST |
| UINT64_C(205562880), // LD1Twov4h |
| UINT64_C(213951488), // LD1Twov4h_POST |
| UINT64_C(1279305728), // LD1Twov4s |
| UINT64_C(1287694336), // LD1Twov4s_POST |
| UINT64_C(205561856), // LD1Twov8b |
| UINT64_C(213950464), // LD1Twov8b_POST |
| UINT64_C(1279304704), // LD1Twov8h |
| UINT64_C(1287693312), // LD1Twov8h_POST |
| UINT64_C(2772451328), // LD1W |
| UINT64_C(2774548480), // LD1W_D |
| UINT64_C(2774573056), // LD1W_D_IMM |
| UINT64_C(2772475904), // LD1W_IMM |
| UINT64_C(222314496), // LD1i16 |
| UINT64_C(230703104), // LD1i16_POST |
| UINT64_C(222330880), // LD1i32 |
| UINT64_C(230719488), // LD1i32_POST |
| UINT64_C(222331904), // LD1i64 |
| UINT64_C(230720512), // LD1i64_POST |
| UINT64_C(222298112), // LD1i8 |
| UINT64_C(230686720), // LD1i8_POST |
| UINT64_C(2753609728), // LD2B |
| UINT64_C(2753617920), // LD2B_IMM |
| UINT64_C(2778775552), // LD2D |
| UINT64_C(2778783744), // LD2D_IMM |
| UINT64_C(2761998336), // LD2H |
| UINT64_C(2762006528), // LD2H_IMM |
| UINT64_C(1298186240), // LD2Rv16b |
| UINT64_C(1306574848), // LD2Rv16b_POST |
| UINT64_C(224447488), // LD2Rv1d |
| UINT64_C(232836096), // LD2Rv1d_POST |
| UINT64_C(1298189312), // LD2Rv2d |
| UINT64_C(1306577920), // LD2Rv2d_POST |
| UINT64_C(224446464), // LD2Rv2s |
| UINT64_C(232835072), // LD2Rv2s_POST |
| UINT64_C(224445440), // LD2Rv4h |
| UINT64_C(232834048), // LD2Rv4h_POST |
| UINT64_C(1298188288), // LD2Rv4s |
| UINT64_C(1306576896), // LD2Rv4s_POST |
| UINT64_C(224444416), // LD2Rv8b |
| UINT64_C(232833024), // LD2Rv8b_POST |
| UINT64_C(1298187264), // LD2Rv8h |
| UINT64_C(1306575872), // LD2Rv8h_POST |
| UINT64_C(1279295488), // LD2Twov16b |
| UINT64_C(1287684096), // LD2Twov16b_POST |
| UINT64_C(1279298560), // LD2Twov2d |
| UINT64_C(1287687168), // LD2Twov2d_POST |
| UINT64_C(205555712), // LD2Twov2s |
| UINT64_C(213944320), // LD2Twov2s_POST |
| UINT64_C(205554688), // LD2Twov4h |
| UINT64_C(213943296), // LD2Twov4h_POST |
| UINT64_C(1279297536), // LD2Twov4s |
| UINT64_C(1287686144), // LD2Twov4s_POST |
| UINT64_C(205553664), // LD2Twov8b |
| UINT64_C(213942272), // LD2Twov8b_POST |
| UINT64_C(1279296512), // LD2Twov8h |
| UINT64_C(1287685120), // LD2Twov8h_POST |
| UINT64_C(2770386944), // LD2W |
| UINT64_C(2770395136), // LD2W_IMM |
| UINT64_C(224411648), // LD2i16 |
| UINT64_C(232800256), // LD2i16_POST |
| UINT64_C(224428032), // LD2i32 |
| UINT64_C(232816640), // LD2i32_POST |
| UINT64_C(224429056), // LD2i64 |
| UINT64_C(232817664), // LD2i64_POST |
| UINT64_C(224395264), // LD2i8 |
| UINT64_C(232783872), // LD2i8_POST |
| UINT64_C(2755706880), // LD3B |
| UINT64_C(2755715072), // LD3B_IMM |
| UINT64_C(2780872704), // LD3D |
| UINT64_C(2780880896), // LD3D_IMM |
| UINT64_C(2764095488), // LD3H |
| UINT64_C(2764103680), // LD3H_IMM |
| UINT64_C(1296097280), // LD3Rv16b |
| UINT64_C(1304485888), // LD3Rv16b_POST |
| UINT64_C(222358528), // LD3Rv1d |
| UINT64_C(230747136), // LD3Rv1d_POST |
| UINT64_C(1296100352), // LD3Rv2d |
| UINT64_C(1304488960), // LD3Rv2d_POST |
| UINT64_C(222357504), // LD3Rv2s |
| UINT64_C(230746112), // LD3Rv2s_POST |
| UINT64_C(222356480), // LD3Rv4h |
| UINT64_C(230745088), // LD3Rv4h_POST |
| UINT64_C(1296099328), // LD3Rv4s |
| UINT64_C(1304487936), // LD3Rv4s_POST |
| UINT64_C(222355456), // LD3Rv8b |
| UINT64_C(230744064), // LD3Rv8b_POST |
| UINT64_C(1296098304), // LD3Rv8h |
| UINT64_C(1304486912), // LD3Rv8h_POST |
| UINT64_C(1279279104), // LD3Threev16b |
| UINT64_C(1287667712), // LD3Threev16b_POST |
| UINT64_C(1279282176), // LD3Threev2d |
| UINT64_C(1287670784), // LD3Threev2d_POST |
| UINT64_C(205539328), // LD3Threev2s |
| UINT64_C(213927936), // LD3Threev2s_POST |
| UINT64_C(205538304), // LD3Threev4h |
| UINT64_C(213926912), // LD3Threev4h_POST |
| UINT64_C(1279281152), // LD3Threev4s |
| UINT64_C(1287669760), // LD3Threev4s_POST |
| UINT64_C(205537280), // LD3Threev8b |
| UINT64_C(213925888), // LD3Threev8b_POST |
| UINT64_C(1279280128), // LD3Threev8h |
| UINT64_C(1287668736), // LD3Threev8h_POST |
| UINT64_C(2772484096), // LD3W |
| UINT64_C(2772492288), // LD3W_IMM |
| UINT64_C(222322688), // LD3i16 |
| UINT64_C(230711296), // LD3i16_POST |
| UINT64_C(222339072), // LD3i32 |
| UINT64_C(230727680), // LD3i32_POST |
| UINT64_C(222340096), // LD3i64 |
| UINT64_C(230728704), // LD3i64_POST |
| UINT64_C(222306304), // LD3i8 |
| UINT64_C(230694912), // LD3i8_POST |
| UINT64_C(2757804032), // LD4B |
| UINT64_C(2757812224), // LD4B_IMM |
| UINT64_C(2782969856), // LD4D |
| UINT64_C(2782978048), // LD4D_IMM |
| UINT64_C(1279262720), // LD4Fourv16b |
| UINT64_C(1287651328), // LD4Fourv16b_POST |
| UINT64_C(1279265792), // LD4Fourv2d |
| UINT64_C(1287654400), // LD4Fourv2d_POST |
| UINT64_C(205522944), // LD4Fourv2s |
| UINT64_C(213911552), // LD4Fourv2s_POST |
| UINT64_C(205521920), // LD4Fourv4h |
| UINT64_C(213910528), // LD4Fourv4h_POST |
| UINT64_C(1279264768), // LD4Fourv4s |
| UINT64_C(1287653376), // LD4Fourv4s_POST |
| UINT64_C(205520896), // LD4Fourv8b |
| UINT64_C(213909504), // LD4Fourv8b_POST |
| UINT64_C(1279263744), // LD4Fourv8h |
| UINT64_C(1287652352), // LD4Fourv8h_POST |
| UINT64_C(2766192640), // LD4H |
| UINT64_C(2766200832), // LD4H_IMM |
| UINT64_C(1298194432), // LD4Rv16b |
| UINT64_C(1306583040), // LD4Rv16b_POST |
| UINT64_C(224455680), // LD4Rv1d |
| UINT64_C(232844288), // LD4Rv1d_POST |
| UINT64_C(1298197504), // LD4Rv2d |
| UINT64_C(1306586112), // LD4Rv2d_POST |
| UINT64_C(224454656), // LD4Rv2s |
| UINT64_C(232843264), // LD4Rv2s_POST |
| UINT64_C(224453632), // LD4Rv4h |
| UINT64_C(232842240), // LD4Rv4h_POST |
| UINT64_C(1298196480), // LD4Rv4s |
| UINT64_C(1306585088), // LD4Rv4s_POST |
| UINT64_C(224452608), // LD4Rv8b |
| UINT64_C(232841216), // LD4Rv8b_POST |
| UINT64_C(1298195456), // LD4Rv8h |
| UINT64_C(1306584064), // LD4Rv8h_POST |
| UINT64_C(2774581248), // LD4W |
| UINT64_C(2774589440), // LD4W_IMM |
| UINT64_C(224419840), // LD4i16 |
| UINT64_C(232808448), // LD4i16_POST |
| UINT64_C(224436224), // LD4i32 |
| UINT64_C(232824832), // LD4i32_POST |
| UINT64_C(224437248), // LD4i64 |
| UINT64_C(232825856), // LD4i64_POST |
| UINT64_C(224403456), // LD4i8 |
| UINT64_C(232792064), // LD4i8_POST |
| UINT64_C(950009856), // LDADDAB |
| UINT64_C(2023751680), // LDADDAH |
| UINT64_C(954204160), // LDADDALB |
| UINT64_C(2027945984), // LDADDALH |
| UINT64_C(3101687808), // LDADDALW |
| UINT64_C(4175429632), // LDADDALX |
| UINT64_C(3097493504), // LDADDAW |
| UINT64_C(4171235328), // LDADDAX |
| UINT64_C(941621248), // LDADDB |
| UINT64_C(2015363072), // LDADDH |
| UINT64_C(945815552), // LDADDLB |
| UINT64_C(2019557376), // LDADDLH |
| UINT64_C(3093299200), // LDADDLW |
| UINT64_C(4167041024), // LDADDLX |
| UINT64_C(3089104896), // LDADDW |
| UINT64_C(4162846720), // LDADDX |
| UINT64_C(952090624), // LDAPRB |
| UINT64_C(2025832448), // LDAPRH |
| UINT64_C(3099574272), // LDAPRW |
| UINT64_C(4173316096), // LDAPRX |
| UINT64_C(423624704), // LDAPURBi |
| UINT64_C(1497366528), // LDAPURHi |
| UINT64_C(432013312), // LDAPURSBWi |
| UINT64_C(427819008), // LDAPURSBXi |
| UINT64_C(1505755136), // LDAPURSHWi |
| UINT64_C(1501560832), // LDAPURSHXi |
| UINT64_C(2575302656), // LDAPURSWi |
| UINT64_C(3644850176), // LDAPURXi |
| UINT64_C(2571108352), // LDAPURi |
| UINT64_C(148896768), // LDARB |
| UINT64_C(1222638592), // LDARH |
| UINT64_C(2296380416), // LDARW |
| UINT64_C(3370122240), // LDARX |
| UINT64_C(2288025600), // LDAXPW |
| UINT64_C(3361767424), // LDAXPX |
| UINT64_C(140508160), // LDAXRB |
| UINT64_C(1214249984), // LDAXRH |
| UINT64_C(2287991808), // LDAXRW |
| UINT64_C(3361733632), // LDAXRX |
| UINT64_C(950013952), // LDCLRAB |
| UINT64_C(2023755776), // LDCLRAH |
| UINT64_C(954208256), // LDCLRALB |
| UINT64_C(2027950080), // LDCLRALH |
| UINT64_C(3101691904), // LDCLRALW |
| UINT64_C(4175433728), // LDCLRALX |
| UINT64_C(3097497600), // LDCLRAW |
| UINT64_C(4171239424), // LDCLRAX |
| UINT64_C(941625344), // LDCLRB |
| UINT64_C(2015367168), // LDCLRH |
| UINT64_C(945819648), // LDCLRLB |
| UINT64_C(2019561472), // LDCLRLH |
| UINT64_C(3093303296), // LDCLRLW |
| UINT64_C(4167045120), // LDCLRLX |
| UINT64_C(3089108992), // LDCLRW |
| UINT64_C(4162850816), // LDCLRX |
| UINT64_C(950018048), // LDEORAB |
| UINT64_C(2023759872), // LDEORAH |
| UINT64_C(954212352), // LDEORALB |
| UINT64_C(2027954176), // LDEORALH |
| UINT64_C(3101696000), // LDEORALW |
| UINT64_C(4175437824), // LDEORALX |
| UINT64_C(3097501696), // LDEORAW |
| UINT64_C(4171243520), // LDEORAX |
| UINT64_C(941629440), // LDEORB |
| UINT64_C(2015371264), // LDEORH |
| UINT64_C(945823744), // LDEORLB |
| UINT64_C(2019565568), // LDEORLH |
| UINT64_C(3093307392), // LDEORLW |
| UINT64_C(4167049216), // LDEORLX |
| UINT64_C(3089113088), // LDEORW |
| UINT64_C(4162854912), // LDEORX |
| UINT64_C(2757779456), // LDFF1B_D_REAL |
| UINT64_C(2753585152), // LDFF1B_H_REAL |
| UINT64_C(2751488000), // LDFF1B_REAL |
| UINT64_C(2755682304), // LDFF1B_S_REAL |
| UINT64_C(2782945280), // LDFF1D_REAL |
| UINT64_C(2766168064), // LDFF1H_D_REAL |
| UINT64_C(2761973760), // LDFF1H_REAL |
| UINT64_C(2764070912), // LDFF1H_S_REAL |
| UINT64_C(2776653824), // LDFF1SB_D_REAL |
| UINT64_C(2780848128), // LDFF1SB_H_REAL |
| UINT64_C(2778750976), // LDFF1SB_S_REAL |
| UINT64_C(2768265216), // LDFF1SH_D_REAL |
| UINT64_C(2770362368), // LDFF1SH_S_REAL |
| UINT64_C(2759876608), // LDFF1SW_D_REAL |
| UINT64_C(2774556672), // LDFF1W_D_REAL |
| UINT64_C(2772459520), // LDFF1W_REAL |
| UINT64_C(3646947328), // LDG |
| UINT64_C(3655335936), // LDGM |
| UINT64_C(148864000), // LDLARB |
| UINT64_C(1222605824), // LDLARH |
| UINT64_C(2296347648), // LDLARW |
| UINT64_C(3370089472), // LDLARX |
| UINT64_C(2758844416), // LDNF1B_D_IMM |
| UINT64_C(2754650112), // LDNF1B_H_IMM |
| UINT64_C(2752552960), // LDNF1B_IMM |
| UINT64_C(2756747264), // LDNF1B_S_IMM |
| UINT64_C(2784010240), // LDNF1D_IMM |
| UINT64_C(2767233024), // LDNF1H_D_IMM |
| UINT64_C(2763038720), // LDNF1H_IMM |
| UINT64_C(2765135872), // LDNF1H_S_IMM |
| UINT64_C(2777718784), // LDNF1SB_D_IMM |
| UINT64_C(2781913088), // LDNF1SB_H_IMM |
| UINT64_C(2779815936), // LDNF1SB_S_IMM |
| UINT64_C(2769330176), // LDNF1SH_D_IMM |
| UINT64_C(2771427328), // LDNF1SH_S_IMM |
| UINT64_C(2760941568), // LDNF1SW_D_IMM |
| UINT64_C(2775621632), // LDNF1W_D_IMM |
| UINT64_C(2773524480), // LDNF1W_IMM |
| UINT64_C(1816133632), // LDNPDi |
| UINT64_C(2889875456), // LDNPQi |
| UINT64_C(742391808), // LDNPSi |
| UINT64_C(675282944), // LDNPWi |
| UINT64_C(2822766592), // LDNPXi |
| UINT64_C(2751520768), // LDNT1B_ZRI |
| UINT64_C(2751512576), // LDNT1B_ZRR |
| UINT64_C(3288383488), // LDNT1B_ZZR_D_REAL |
| UINT64_C(2214633472), // LDNT1B_ZZR_S_REAL |
| UINT64_C(2776686592), // LDNT1D_ZRI |
| UINT64_C(2776678400), // LDNT1D_ZRR |
| UINT64_C(3313549312), // LDNT1D_ZZR_D_REAL |
| UINT64_C(2759909376), // LDNT1H_ZRI |
| UINT64_C(2759901184), // LDNT1H_ZRR |
| UINT64_C(3296772096), // LDNT1H_ZZR_D_REAL |
| UINT64_C(2223022080), // LDNT1H_ZZR_S_REAL |
| UINT64_C(3288367104), // LDNT1SB_ZZR_D_REAL |
| UINT64_C(2214625280), // LDNT1SB_ZZR_S_REAL |
| UINT64_C(3296755712), // LDNT1SH_ZZR_D_REAL |
| UINT64_C(2223013888), // LDNT1SH_ZZR_S_REAL |
| UINT64_C(3305144320), // LDNT1SW_ZZR_D_REAL |
| UINT64_C(2768297984), // LDNT1W_ZRI |
| UINT64_C(2768289792), // LDNT1W_ZRR |
| UINT64_C(3305160704), // LDNT1W_ZZR_D_REAL |
| UINT64_C(2231410688), // LDNT1W_ZZR_S_REAL |
| UINT64_C(1832910848), // LDPDi |
| UINT64_C(1824522240), // LDPDpost |
| UINT64_C(1841299456), // LDPDpre |
| UINT64_C(2906652672), // LDPQi |
| UINT64_C(2898264064), // LDPQpost |
| UINT64_C(2915041280), // LDPQpre |
| UINT64_C(1765801984), // LDPSWi |
| UINT64_C(1757413376), // LDPSWpost |
| UINT64_C(1774190592), // LDPSWpre |
| UINT64_C(759169024), // LDPSi |
| UINT64_C(750780416), // LDPSpost |
| UINT64_C(767557632), // LDPSpre |
| UINT64_C(692060160), // LDPWi |
| UINT64_C(683671552), // LDPWpost |
| UINT64_C(700448768), // LDPWpre |
| UINT64_C(2839543808), // LDPXi |
| UINT64_C(2831155200), // LDPXpost |
| UINT64_C(2847932416), // LDPXpre |
| UINT64_C(4162847744), // LDRAAindexed |
| UINT64_C(4162849792), // LDRAAwriteback |
| UINT64_C(4171236352), // LDRABindexed |
| UINT64_C(4171238400), // LDRABwriteback |
| UINT64_C(943719424), // LDRBBpost |
| UINT64_C(943721472), // LDRBBpre |
| UINT64_C(945833984), // LDRBBroW |
| UINT64_C(945842176), // LDRBBroX |
| UINT64_C(960495616), // LDRBBui |
| UINT64_C(1010828288), // LDRBpost |
| UINT64_C(1010830336), // LDRBpre |
| UINT64_C(1012942848), // LDRBroW |
| UINT64_C(1012951040), // LDRBroX |
| UINT64_C(1027604480), // LDRBui |
| UINT64_C(1543503872), // LDRDl |
| UINT64_C(4232053760), // LDRDpost |
| UINT64_C(4232055808), // LDRDpre |
| UINT64_C(4234168320), // LDRDroW |
| UINT64_C(4234176512), // LDRDroX |
| UINT64_C(4248829952), // LDRDui |
| UINT64_C(2017461248), // LDRHHpost |
| UINT64_C(2017463296), // LDRHHpre |
| UINT64_C(2019575808), // LDRHHroW |
| UINT64_C(2019584000), // LDRHHroX |
| UINT64_C(2034237440), // LDRHHui |
| UINT64_C(2084570112), // LDRHpost |
| UINT64_C(2084572160), // LDRHpre |
| UINT64_C(2086684672), // LDRHroW |
| UINT64_C(2086692864), // LDRHroX |
| UINT64_C(2101346304), // LDRHui |
| UINT64_C(2617245696), // LDRQl |
| UINT64_C(1019216896), // LDRQpost |
| UINT64_C(1019218944), // LDRQpre |
| UINT64_C(1021331456), // LDRQroW |
| UINT64_C(1021339648), // LDRQroX |
| UINT64_C(1035993088), // LDRQui |
| UINT64_C(952108032), // LDRSBWpost |
| UINT64_C(952110080), // LDRSBWpre |
| UINT64_C(954222592), // LDRSBWroW |
| UINT64_C(954230784), // LDRSBWroX |
| UINT64_C(968884224), // LDRSBWui |
| UINT64_C(947913728), // LDRSBXpost |
| UINT64_C(947915776), // LDRSBXpre |
| UINT64_C(950028288), // LDRSBXroW |
| UINT64_C(950036480), // LDRSBXroX |
| UINT64_C(964689920), // LDRSBXui |
| UINT64_C(2025849856), // LDRSHWpost |
| UINT64_C(2025851904), // LDRSHWpre |
| UINT64_C(2027964416), // LDRSHWroW |
| UINT64_C(2027972608), // LDRSHWroX |
| UINT64_C(2042626048), // LDRSHWui |
| UINT64_C(2021655552), // LDRSHXpost |
| UINT64_C(2021657600), // LDRSHXpre |
| UINT64_C(2023770112), // LDRSHXroW |
| UINT64_C(2023778304), // LDRSHXroX |
| UINT64_C(2038431744), // LDRSHXui |
| UINT64_C(2550136832), // LDRSWl |
| UINT64_C(3095397376), // LDRSWpost |
| UINT64_C(3095399424), // LDRSWpre |
| UINT64_C(3097511936), // LDRSWroW |
| UINT64_C(3097520128), // LDRSWroX |
| UINT64_C(3112173568), // LDRSWui |
| UINT64_C(469762048), // LDRSl |
| UINT64_C(3158311936), // LDRSpost |
| UINT64_C(3158313984), // LDRSpre |
| UINT64_C(3160426496), // LDRSroW |
| UINT64_C(3160434688), // LDRSroX |
| UINT64_C(3175088128), // LDRSui |
| UINT64_C(402653184), // LDRWl |
| UINT64_C(3091203072), // LDRWpost |
| UINT64_C(3091205120), // LDRWpre |
| UINT64_C(3093317632), // LDRWroW |
| UINT64_C(3093325824), // LDRWroX |
| UINT64_C(3107979264), // LDRWui |
| UINT64_C(1476395008), // LDRXl |
| UINT64_C(4164944896), // LDRXpost |
| UINT64_C(4164946944), // LDRXpre |
| UINT64_C(4167059456), // LDRXroW |
| UINT64_C(4167067648), // LDRXroX |
| UINT64_C(4181721088), // LDRXui |
| UINT64_C(2239758336), // LDR_PXI |
| UINT64_C(2239774720), // LDR_ZXI |
| UINT64_C(950022144), // LDSETAB |
| UINT64_C(2023763968), // LDSETAH |
| UINT64_C(954216448), // LDSETALB |
| UINT64_C(2027958272), // LDSETALH |
| UINT64_C(3101700096), // LDSETALW |
| UINT64_C(4175441920), // LDSETALX |
| UINT64_C(3097505792), // LDSETAW |
| UINT64_C(4171247616), // LDSETAX |
| UINT64_C(941633536), // LDSETB |
| UINT64_C(2015375360), // LDSETH |
| UINT64_C(945827840), // LDSETLB |
| UINT64_C(2019569664), // LDSETLH |
| UINT64_C(3093311488), // LDSETLW |
| UINT64_C(4167053312), // LDSETLX |
| UINT64_C(3089117184), // LDSETW |
| UINT64_C(4162859008), // LDSETX |
| UINT64_C(950026240), // LDSMAXAB |
| UINT64_C(2023768064), // LDSMAXAH |
| UINT64_C(954220544), // LDSMAXALB |
| UINT64_C(2027962368), // LDSMAXALH |
| UINT64_C(3101704192), // LDSMAXALW |
| UINT64_C(4175446016), // LDSMAXALX |
| UINT64_C(3097509888), // LDSMAXAW |
| UINT64_C(4171251712), // LDSMAXAX |
| UINT64_C(941637632), // LDSMAXB |
| UINT64_C(2015379456), // LDSMAXH |
| UINT64_C(945831936), // LDSMAXLB |
| UINT64_C(2019573760), // LDSMAXLH |
| UINT64_C(3093315584), // LDSMAXLW |
| UINT64_C(4167057408), // LDSMAXLX |
| UINT64_C(3089121280), // LDSMAXW |
| UINT64_C(4162863104), // LDSMAXX |
| UINT64_C(950030336), // LDSMINAB |
| UINT64_C(2023772160), // LDSMINAH |
| UINT64_C(954224640), // LDSMINALB |
| UINT64_C(2027966464), // LDSMINALH |
| UINT64_C(3101708288), // LDSMINALW |
| UINT64_C(4175450112), // LDSMINALX |
| UINT64_C(3097513984), // LDSMINAW |
| UINT64_C(4171255808), // LDSMINAX |
| UINT64_C(941641728), // LDSMINB |
| UINT64_C(2015383552), // LDSMINH |
| UINT64_C(945836032), // LDSMINLB |
| UINT64_C(2019577856), // LDSMINLH |
| UINT64_C(3093319680), // LDSMINLW |
| UINT64_C(4167061504), // LDSMINLX |
| UINT64_C(3089125376), // LDSMINW |
| UINT64_C(4162867200), // LDSMINX |
| UINT64_C(943720448), // LDTRBi |
| UINT64_C(2017462272), // LDTRHi |
| UINT64_C(952109056), // LDTRSBWi |
| UINT64_C(947914752), // LDTRSBXi |
| UINT64_C(2025850880), // LDTRSHWi |
| UINT64_C(2021656576), // LDTRSHXi |
| UINT64_C(3095398400), // LDTRSWi |
| UINT64_C(3091204096), // LDTRWi |
| UINT64_C(4164945920), // LDTRXi |
| UINT64_C(950034432), // LDUMAXAB |
| UINT64_C(2023776256), // LDUMAXAH |
| UINT64_C(954228736), // LDUMAXALB |
| UINT64_C(2027970560), // LDUMAXALH |
| UINT64_C(3101712384), // LDUMAXALW |
| UINT64_C(4175454208), // LDUMAXALX |
| UINT64_C(3097518080), // LDUMAXAW |
| UINT64_C(4171259904), // LDUMAXAX |
| UINT64_C(941645824), // LDUMAXB |
| UINT64_C(2015387648), // LDUMAXH |
| UINT64_C(945840128), // LDUMAXLB |
| UINT64_C(2019581952), // LDUMAXLH |
| UINT64_C(3093323776), // LDUMAXLW |
| UINT64_C(4167065600), // LDUMAXLX |
| UINT64_C(3089129472), // LDUMAXW |
| UINT64_C(4162871296), // LDUMAXX |
| UINT64_C(950038528), // LDUMINAB |
| UINT64_C(2023780352), // LDUMINAH |
| UINT64_C(954232832), // LDUMINALB |
| UINT64_C(2027974656), // LDUMINALH |
| UINT64_C(3101716480), // LDUMINALW |
| UINT64_C(4175458304), // LDUMINALX |
| UINT64_C(3097522176), // LDUMINAW |
| UINT64_C(4171264000), // LDUMINAX |
| UINT64_C(941649920), // LDUMINB |
| UINT64_C(2015391744), // LDUMINH |
| UINT64_C(945844224), // LDUMINLB |
| UINT64_C(2019586048), // LDUMINLH |
| UINT64_C(3093327872), // LDUMINLW |
| UINT64_C(4167069696), // LDUMINLX |
| UINT64_C(3089133568), // LDUMINW |
| UINT64_C(4162875392), // LDUMINX |
| UINT64_C(943718400), // LDURBBi |
| UINT64_C(1010827264), // LDURBi |
| UINT64_C(4232052736), // LDURDi |
| UINT64_C(2017460224), // LDURHHi |
| UINT64_C(2084569088), // LDURHi |
| UINT64_C(1019215872), // LDURQi |
| UINT64_C(952107008), // LDURSBWi |
| UINT64_C(947912704), // LDURSBXi |
| UINT64_C(2025848832), // LDURSHWi |
| UINT64_C(2021654528), // LDURSHXi |
| UINT64_C(3095396352), // LDURSWi |
| UINT64_C(3158310912), // LDURSi |
| UINT64_C(3091202048), // LDURWi |
| UINT64_C(4164943872), // LDURXi |
| UINT64_C(2287992832), // LDXPW |
| UINT64_C(3361734656), // LDXPX |
| UINT64_C(140475392), // LDXRB |
| UINT64_C(1214217216), // LDXRH |
| UINT64_C(2287959040), // LDXRW |
| UINT64_C(3361700864), // LDXRX |
| UINT64_C(0), // LOADgot |
| UINT64_C(68648960), // LSLR_ZPmZ_B |
| UINT64_C(81231872), // LSLR_ZPmZ_D |
| UINT64_C(72843264), // LSLR_ZPmZ_H |
| UINT64_C(77037568), // LSLR_ZPmZ_S |
| UINT64_C(448798720), // LSLVWr |
| UINT64_C(2596282368), // LSLVXr |
| UINT64_C(68911104), // LSL_WIDE_ZPmZ_B |
| UINT64_C(73105408), // LSL_WIDE_ZPmZ_H |
| UINT64_C(77299712), // LSL_WIDE_ZPmZ_S |
| UINT64_C(69241856), // LSL_WIDE_ZZZ_B |
| UINT64_C(73436160), // LSL_WIDE_ZZZ_H |
| UINT64_C(77630464), // LSL_WIDE_ZZZ_S |
| UINT64_C(67338496), // LSL_ZPmI_B |
| UINT64_C(75726848), // LSL_ZPmI_D |
| UINT64_C(67338752), // LSL_ZPmI_H |
| UINT64_C(71532544), // LSL_ZPmI_S |
| UINT64_C(68386816), // LSL_ZPmZ_B |
| UINT64_C(80969728), // LSL_ZPmZ_D |
| UINT64_C(72581120), // LSL_ZPmZ_H |
| UINT64_C(76775424), // LSL_ZPmZ_S |
| UINT64_C(69770240), // LSL_ZZI_B |
| UINT64_C(77634560), // LSL_ZZI_D |
| UINT64_C(70294528), // LSL_ZZI_H |
| UINT64_C(73440256), // LSL_ZZI_S |
| UINT64_C(68517888), // LSRR_ZPmZ_B |
| UINT64_C(81100800), // LSRR_ZPmZ_D |
| UINT64_C(72712192), // LSRR_ZPmZ_H |
| UINT64_C(76906496), // LSRR_ZPmZ_S |
| UINT64_C(448799744), // LSRVWr |
| UINT64_C(2596283392), // LSRVXr |
| UINT64_C(68780032), // LSR_WIDE_ZPmZ_B |
| UINT64_C(72974336), // LSR_WIDE_ZPmZ_H |
| UINT64_C(77168640), // LSR_WIDE_ZPmZ_S |
| UINT64_C(69239808), // LSR_WIDE_ZZZ_B |
| UINT64_C(73434112), // LSR_WIDE_ZZZ_H |
| UINT64_C(77628416), // LSR_WIDE_ZZZ_S |
| UINT64_C(67207424), // LSR_ZPmI_B |
| UINT64_C(75595776), // LSR_ZPmI_D |
| UINT64_C(67207680), // LSR_ZPmI_H |
| UINT64_C(71401472), // LSR_ZPmI_S |
| UINT64_C(68255744), // LSR_ZPmZ_B |
| UINT64_C(80838656), // LSR_ZPmZ_D |
| UINT64_C(72450048), // LSR_ZPmZ_H |
| UINT64_C(76644352), // LSR_ZPmZ_S |
| UINT64_C(69768192), // LSR_ZZI_B |
| UINT64_C(77632512), // LSR_ZZI_D |
| UINT64_C(70292480), // LSR_ZZI_H |
| UINT64_C(73438208), // LSR_ZZI_S |
| UINT64_C(452984832), // MADDWrrr |
| UINT64_C(2600468480), // MADDXrrr |
| UINT64_C(67158016), // MAD_ZPmZZ_B |
| UINT64_C(79740928), // MAD_ZPmZZ_D |
| UINT64_C(71352320), // MAD_ZPmZZ_H |
| UINT64_C(75546624), // MAD_ZPmZZ_S |
| UINT64_C(1159757824), // MATCH_PPzZZ_B |
| UINT64_C(1163952128), // MATCH_PPzZZ_H |
| UINT64_C(67125248), // MLA_ZPmZZ_B |
| UINT64_C(79708160), // MLA_ZPmZZ_D |
| UINT64_C(71319552), // MLA_ZPmZZ_H |
| UINT64_C(75513856), // MLA_ZPmZZ_S |
| UINT64_C(1155532800), // MLA_ZZZI_D |
| UINT64_C(1142949888), // MLA_ZZZI_H |
| UINT64_C(1151338496), // MLA_ZZZI_S |
| UINT64_C(1310757888), // MLAv16i8 |
| UINT64_C(245404672), // MLAv2i32 |
| UINT64_C(796917760), // MLAv2i32_indexed |
| UINT64_C(241210368), // MLAv4i16 |
| UINT64_C(792723456), // MLAv4i16_indexed |
| UINT64_C(1319146496), // MLAv4i32 |
| UINT64_C(1870659584), // MLAv4i32_indexed |
| UINT64_C(1314952192), // MLAv8i16 |
| UINT64_C(1866465280), // MLAv8i16_indexed |
| UINT64_C(237016064), // MLAv8i8 |
| UINT64_C(67133440), // MLS_ZPmZZ_B |
| UINT64_C(79716352), // MLS_ZPmZZ_D |
| UINT64_C(71327744), // MLS_ZPmZZ_H |
| UINT64_C(75522048), // MLS_ZPmZZ_S |
| UINT64_C(1155533824), // MLS_ZZZI_D |
| UINT64_C(1142950912), // MLS_ZZZI_H |
| UINT64_C(1151339520), // MLS_ZZZI_S |
| UINT64_C(1847628800), // MLSv16i8 |
| UINT64_C(782275584), // MLSv2i32 |
| UINT64_C(796934144), // MLSv2i32_indexed |
| UINT64_C(778081280), // MLSv4i16 |
| UINT64_C(792739840), // MLSv4i16_indexed |
| UINT64_C(1856017408), // MLSv4i32 |
| UINT64_C(1870675968), // MLSv4i32_indexed |
| UINT64_C(1851823104), // MLSv8i16 |
| UINT64_C(1866481664), // MLSv8i16_indexed |
| UINT64_C(773886976), // MLSv8i8 |
| UINT64_C(788587520), // MOVID |
| UINT64_C(1325458432), // MOVIv16b_ns |
| UINT64_C(1862329344), // MOVIv2d_ns |
| UINT64_C(251659264), // MOVIv2i32 |
| UINT64_C(251708416), // MOVIv2s_msl |
| UINT64_C(251692032), // MOVIv4i16 |
| UINT64_C(1325401088), // MOVIv4i32 |
| UINT64_C(1325450240), // MOVIv4s_msl |
| UINT64_C(251716608), // MOVIv8b_ns |
| UINT64_C(1325433856), // MOVIv8i16 |
| UINT64_C(1920991232), // MOVKWi |
| UINT64_C(4068474880), // MOVKXi |
| UINT64_C(0), // MOVMCSym |
| UINT64_C(310378496), // MOVNWi |
| UINT64_C(2457862144), // MOVNXi |
| UINT64_C(68231168), // MOVPRFX_ZPmZ_B |
| UINT64_C(80814080), // MOVPRFX_ZPmZ_D |
| UINT64_C(72425472), // MOVPRFX_ZPmZ_H |
| UINT64_C(76619776), // MOVPRFX_ZPmZ_S |
| UINT64_C(68165632), // MOVPRFX_ZPzZ_B |
| UINT64_C(80748544), // MOVPRFX_ZPzZ_D |
| UINT64_C(72359936), // MOVPRFX_ZPzZ_H |
| UINT64_C(76554240), // MOVPRFX_ZPzZ_S |
| UINT64_C(69254144), // MOVPRFX_ZZ |
| UINT64_C(1384120320), // MOVZWi |
| UINT64_C(3531603968), // MOVZXi |
| UINT64_C(0), // MOVaddr |
| UINT64_C(0), // MOVaddrBA |
| UINT64_C(0), // MOVaddrCP |
| UINT64_C(0), // MOVaddrEXT |
| UINT64_C(0), // MOVaddrJT |
| UINT64_C(0), // MOVaddrTLS |
| UINT64_C(0), // MOVbaseTLS |
| UINT64_C(0), // MOVi32imm |
| UINT64_C(0), // MOVi64imm |
| UINT64_C(3575644160), // MRS |
| UINT64_C(67166208), // MSB_ZPmZZ_B |
| UINT64_C(79749120), // MSB_ZPmZZ_D |
| UINT64_C(71360512), // MSB_ZPmZZ_H |
| UINT64_C(75554816), // MSB_ZPmZZ_S |
| UINT64_C(3573547008), // MSR |
| UINT64_C(3573563423), // MSRpstateImm1 |
| UINT64_C(3573563423), // MSRpstateImm4 |
| UINT64_C(453017600), // MSUBWrrr |
| UINT64_C(2600501248), // MSUBXrrr |
| UINT64_C(623951872), // MUL_ZI_B |
| UINT64_C(636534784), // MUL_ZI_D |
| UINT64_C(628146176), // MUL_ZI_H |
| UINT64_C(632340480), // MUL_ZI_S |
| UINT64_C(68157440), // MUL_ZPmZ_B |
| UINT64_C(80740352), // MUL_ZPmZ_D |
| UINT64_C(72351744), // MUL_ZPmZ_H |
| UINT64_C(76546048), // MUL_ZPmZ_S |
| UINT64_C(1155594240), // MUL_ZZZI_D |
| UINT64_C(1143011328), // MUL_ZZZI_H |
| UINT64_C(1151399936), // MUL_ZZZI_S |
| UINT64_C(69230592), // MUL_ZZZ_B |
| UINT64_C(81813504), // MUL_ZZZ_D |
| UINT64_C(73424896), // MUL_ZZZ_H |
| UINT64_C(77619200), // MUL_ZZZ_S |
| UINT64_C(1310759936), // MULv16i8 |
| UINT64_C(245406720), // MULv2i32 |
| UINT64_C(260079616), // MULv2i32_indexed |
| UINT64_C(241212416), // MULv4i16 |
| UINT64_C(255885312), // MULv4i16_indexed |
| UINT64_C(1319148544), // MULv4i32 |
| UINT64_C(1333821440), // MULv4i32_indexed |
| UINT64_C(1314954240), // MULv8i16 |
| UINT64_C(1329627136), // MULv8i16_indexed |
| UINT64_C(237018112), // MULv8i8 |
| UINT64_C(788530176), // MVNIv2i32 |
| UINT64_C(788579328), // MVNIv2s_msl |
| UINT64_C(788562944), // MVNIv4i16 |
| UINT64_C(1862272000), // MVNIv4i32 |
| UINT64_C(1862321152), // MVNIv4s_msl |
| UINT64_C(1862304768), // MVNIv8i16 |
| UINT64_C(633356816), // NANDS_PPzPP |
| UINT64_C(629162512), // NAND_PPzPP |
| UINT64_C(81804288), // NBSL_ZZZZ_D |
| UINT64_C(68657152), // NEG_ZPmZ_B |
| UINT64_C(81240064), // NEG_ZPmZ_D |
| UINT64_C(72851456), // NEG_ZPmZ_H |
| UINT64_C(77045760), // NEG_ZPmZ_S |
| UINT64_C(1847638016), // NEGv16i8 |
| UINT64_C(2128656384), // NEGv1i64 |
| UINT64_C(782284800), // NEGv2i32 |
| UINT64_C(1860220928), // NEGv2i64 |
| UINT64_C(778090496), // NEGv4i16 |
| UINT64_C(1856026624), // NEGv4i32 |
| UINT64_C(1851832320), // NEGv8i16 |
| UINT64_C(773896192), // NEGv8i8 |
| UINT64_C(1159757840), // NMATCH_PPzZZ_B |
| UINT64_C(1163952144), // NMATCH_PPzZZ_H |
| UINT64_C(633356800), // NORS_PPzPP |
| UINT64_C(629162496), // NOR_PPzPP |
| UINT64_C(69115904), // NOT_ZPmZ_B |
| UINT64_C(81698816), // NOT_ZPmZ_D |
| UINT64_C(73310208), // NOT_ZPmZ_H |
| UINT64_C(77504512), // NOT_ZPmZ_S |
| UINT64_C(1847613440), // NOTv16i8 |
| UINT64_C(773871616), // NOTv8i8 |
| UINT64_C(633356304), // ORNS_PPzPP |
| UINT64_C(0), // ORNWrr |
| UINT64_C(706740224), // ORNWrs |
| UINT64_C(0), // ORNXrr |
| UINT64_C(2854223872), // ORNXrs |
| UINT64_C(629162000), // ORN_PPzPP |
| UINT64_C(1323310080), // ORNv16i8 |
| UINT64_C(249568256), // ORNv8i8 |
| UINT64_C(633356288), // ORRS_PPzPP |
| UINT64_C(838860800), // ORRWri |
| UINT64_C(0), // ORRWrr |
| UINT64_C(704643072), // ORRWrs |
| UINT64_C(2986344448), // ORRXri |
| UINT64_C(0), // ORRXrr |
| UINT64_C(2852126720), // ORRXrs |
| UINT64_C(629161984), // ORR_PPzPP |
| UINT64_C(83886080), // ORR_ZI |
| UINT64_C(68681728), // ORR_ZPmZ_B |
| UINT64_C(81264640), // ORR_ZPmZ_D |
| UINT64_C(72876032), // ORR_ZPmZ_H |
| UINT64_C(77070336), // ORR_ZPmZ_S |
| UINT64_C(73412608), // ORR_ZZZ |
| UINT64_C(1319115776), // ORRv16i8 |
| UINT64_C(251663360), // ORRv2i32 |
| UINT64_C(251696128), // ORRv4i16 |
| UINT64_C(1325405184), // ORRv4i32 |
| UINT64_C(1325437952), // ORRv8i16 |
| UINT64_C(245373952), // ORRv8i8 |
| UINT64_C(68689920), // ORV_VPZ_B |
| UINT64_C(81272832), // ORV_VPZ_D |
| UINT64_C(72884224), // ORV_VPZ_H |
| UINT64_C(77078528), // ORV_VPZ_S |
| UINT64_C(3670083584), // PACDA |
| UINT64_C(3670084608), // PACDB |
| UINT64_C(3670092768), // PACDZA |
| UINT64_C(3670093792), // PACDZB |
| UINT64_C(2596286464), // PACGA |
| UINT64_C(3670081536), // PACIA |
| UINT64_C(3573752095), // PACIA1716 |
| UINT64_C(3573752639), // PACIASP |
| UINT64_C(3573752607), // PACIAZ |
| UINT64_C(3670082560), // PACIB |
| UINT64_C(3573752159), // PACIB1716 |
| UINT64_C(3573752703), // PACIBSP |
| UINT64_C(3573752671), // PACIBZ |
| UINT64_C(3670090720), // PACIZA |
| UINT64_C(3670091744), // PACIZB |
| UINT64_C(622388224), // PFALSE |
| UINT64_C(626573312), // PFIRST_B |
| UINT64_C(1170237440), // PMULLB_ZZZ_D |
| UINT64_C(1161848832), // PMULLB_ZZZ_H |
| UINT64_C(1157654528), // PMULLB_ZZZ_Q |
| UINT64_C(1170238464), // PMULLT_ZZZ_D |
| UINT64_C(1161849856), // PMULLT_ZZZ_H |
| UINT64_C(1157655552), // PMULLT_ZZZ_Q |
| UINT64_C(1310777344), // PMULLv16i8 |
| UINT64_C(249618432), // PMULLv1i64 |
| UINT64_C(1323360256), // PMULLv2i64 |
| UINT64_C(237035520), // PMULLv8i8 |
| UINT64_C(69231616), // PMUL_ZZZ_B |
| UINT64_C(1847630848), // PMULv16i8 |
| UINT64_C(773889024), // PMULv8i8 |
| UINT64_C(622445568), // PNEXT_B |
| UINT64_C(635028480), // PNEXT_D |
| UINT64_C(626639872), // PNEXT_H |
| UINT64_C(630834176), // PNEXT_S |
| UINT64_C(3288391680), // PRFB_D_PZI |
| UINT64_C(3294658560), // PRFB_D_SCALED |
| UINT64_C(3294625792), // PRFB_D_SXTW_SCALED |
| UINT64_C(3290431488), // PRFB_D_UXTW_SCALED |
| UINT64_C(2243952640), // PRFB_PRI |
| UINT64_C(2214641664), // PRFB_PRR |
| UINT64_C(2214649856), // PRFB_S_PZI |
| UINT64_C(2220883968), // PRFB_S_SXTW_SCALED |
| UINT64_C(2216689664), // PRFB_S_UXTW_SCALED |
| UINT64_C(3313557504), // PRFD_D_PZI |
| UINT64_C(3294683136), // PRFD_D_SCALED |
| UINT64_C(3294650368), // PRFD_D_SXTW_SCALED |
| UINT64_C(3290456064), // PRFD_D_UXTW_SCALED |
| UINT64_C(2243977216), // PRFD_PRI |
| UINT64_C(2239807488), // PRFD_PRR |
| UINT64_C(2239815680), // PRFD_S_PZI |
| UINT64_C(2220908544), // PRFD_S_SXTW_SCALED |
| UINT64_C(2216714240), // PRFD_S_UXTW_SCALED |
| UINT64_C(3296780288), // PRFH_D_PZI |
| UINT64_C(3294666752), // PRFH_D_SCALED |
| UINT64_C(3294633984), // PRFH_D_SXTW_SCALED |
| UINT64_C(3290439680), // PRFH_D_UXTW_SCALED |
| UINT64_C(2243960832), // PRFH_PRI |
| UINT64_C(2223030272), // PRFH_PRR |
| UINT64_C(2223038464), // PRFH_S_PZI |
| UINT64_C(2220892160), // PRFH_S_SXTW_SCALED |
| UINT64_C(2216697856), // PRFH_S_UXTW_SCALED |
| UINT64_C(3623878656), // PRFMl |
| UINT64_C(4171253760), // PRFMroW |
| UINT64_C(4171261952), // PRFMroX |
| UINT64_C(4185915392), // PRFMui |
| UINT64_C(2231418880), // PRFS_PRR |
| UINT64_C(4169138176), // PRFUMi |
| UINT64_C(3305168896), // PRFW_D_PZI |
| UINT64_C(3294674944), // PRFW_D_SCALED |
| UINT64_C(3294642176), // PRFW_D_SXTW_SCALED |
| UINT64_C(3290447872), // PRFW_D_UXTW_SCALED |
| UINT64_C(2243969024), // PRFW_PRI |
| UINT64_C(2231427072), // PRFW_S_PZI |
| UINT64_C(2220900352), // PRFW_S_SXTW_SCALED |
| UINT64_C(2216706048), // PRFW_S_UXTW_SCALED |
| UINT64_C(626049024), // PTEST_PP |
| UINT64_C(622452736), // PTRUES_B |
| UINT64_C(635035648), // PTRUES_D |
| UINT64_C(626647040), // PTRUES_H |
| UINT64_C(630841344), // PTRUES_S |
| UINT64_C(622387200), // PTRUE_B |
| UINT64_C(634970112), // PTRUE_D |
| UINT64_C(626581504), // PTRUE_H |
| UINT64_C(630775808), // PTRUE_S |
| UINT64_C(87113728), // PUNPKHI_PP |
| UINT64_C(87048192), // PUNPKLO_PP |
| UINT64_C(1163945984), // RADDHNB_ZZZ_B |
| UINT64_C(1168140288), // RADDHNB_ZZZ_H |
| UINT64_C(1172334592), // RADDHNB_ZZZ_S |
| UINT64_C(1163947008), // RADDHNT_ZZZ_B |
| UINT64_C(1168141312), // RADDHNT_ZZZ_H |
| UINT64_C(1172335616), // RADDHNT_ZZZ_S |
| UINT64_C(782254080), // RADDHNv2i64_v2i32 |
| UINT64_C(1855995904), // RADDHNv2i64_v4i32 |
| UINT64_C(778059776), // RADDHNv4i32_v4i16 |
| UINT64_C(1851801600), // RADDHNv4i32_v8i16 |
| UINT64_C(1847607296), // RADDHNv8i16_v16i8 |
| UINT64_C(773865472), // RADDHNv8i16_v8i8 |
| UINT64_C(3462433792), // RAX1 |
| UINT64_C(1159787520), // RAX1_ZZZ_D |
| UINT64_C(1522532352), // RBITWr |
| UINT64_C(3670016000), // RBITXr |
| UINT64_C(86474752), // RBIT_ZPmZ_B |
| UINT64_C(99057664), // RBIT_ZPmZ_D |
| UINT64_C(90669056), // RBIT_ZPmZ_H |
| UINT64_C(94863360), // RBIT_ZPmZ_S |
| UINT64_C(1851807744), // RBITv16i8 |
| UINT64_C(778065920), // RBITv8i8 |
| UINT64_C(626585600), // RDFFRS_PPz |
| UINT64_C(622456832), // RDFFR_P |
| UINT64_C(622391296), // RDFFR_PPz |
| UINT64_C(79646720), // RDVLI_XI |
| UINT64_C(3596550144), // RET |
| UINT64_C(3596553215), // RETAA |
| UINT64_C(3596554239), // RETAB |
| UINT64_C(0), // RET_ReallyLR |
| UINT64_C(1522533376), // REV16Wr |
| UINT64_C(3670017024), // REV16Xr |
| UINT64_C(1310726144), // REV16v16i8 |
| UINT64_C(236984320), // REV16v8i8 |
| UINT64_C(3670018048), // REV32Xr |
| UINT64_C(1847592960), // REV32v16i8 |
| UINT64_C(778045440), // REV32v4i16 |
| UINT64_C(1851787264), // REV32v8i16 |
| UINT64_C(773851136), // REV32v8i8 |
| UINT64_C(1310722048), // REV64v16i8 |
| UINT64_C(245368832), // REV64v2i32 |
| UINT64_C(241174528), // REV64v4i16 |
| UINT64_C(1319110656), // REV64v4i32 |
| UINT64_C(1314916352), // REV64v8i16 |
| UINT64_C(236980224), // REV64v8i8 |
| UINT64_C(98861056), // REVB_ZPmZ_D |
| UINT64_C(90472448), // REVB_ZPmZ_H |
| UINT64_C(94666752), // REVB_ZPmZ_S |
| UINT64_C(98926592), // REVH_ZPmZ_D |
| UINT64_C(94732288), // REVH_ZPmZ_S |
| UINT64_C(98992128), // REVW_ZPmZ_D |
| UINT64_C(1522534400), // REVWr |
| UINT64_C(3670019072), // REVXr |
| UINT64_C(87310336), // REV_PP_B |
| UINT64_C(99893248), // REV_PP_D |
| UINT64_C(91504640), // REV_PP_H |
| UINT64_C(95698944), // REV_PP_S |
| UINT64_C(87570432), // REV_ZZ_B |
| UINT64_C(100153344), // REV_ZZ_D |
| UINT64_C(91764736), // REV_ZZ_H |
| UINT64_C(95959040), // REV_ZZ_S |
| UINT64_C(3120563200), // RMIF |
| UINT64_C(448801792), // RORVWr |
| UINT64_C(2596285440), // RORVXr |
| UINT64_C(1160255488), // RSHRNB_ZZI_B |
| UINT64_C(1160779776), // RSHRNB_ZZI_H |
| UINT64_C(1163925504), // RSHRNB_ZZI_S |
| UINT64_C(1160256512), // RSHRNT_ZZI_B |
| UINT64_C(1160780800), // RSHRNT_ZZI_H |
| UINT64_C(1163926528), // RSHRNT_ZZI_S |
| UINT64_C(1325960192), // RSHRNv16i8_shift |
| UINT64_C(253791232), // RSHRNv2i32_shift |
| UINT64_C(252742656), // RSHRNv4i16_shift |
| UINT64_C(1327533056), // RSHRNv4i32_shift |
| UINT64_C(1326484480), // RSHRNv8i16_shift |
| UINT64_C(252218368), // RSHRNv8i8_shift |
| UINT64_C(1163950080), // RSUBHNB_ZZZ_B |
| UINT64_C(1168144384), // RSUBHNB_ZZZ_H |
| UINT64_C(1172338688), // RSUBHNB_ZZZ_S |
| UINT64_C(1163951104), // RSUBHNT_ZZZ_B |
| UINT64_C(1168145408), // RSUBHNT_ZZZ_H |
| UINT64_C(1172339712), // RSUBHNT_ZZZ_S |
| UINT64_C(782262272), // RSUBHNv2i64_v2i32 |
| UINT64_C(1856004096), // RSUBHNv2i64_v4i32 |
| UINT64_C(778067968), // RSUBHNv4i32_v4i16 |
| UINT64_C(1851809792), // RSUBHNv4i32_v8i16 |
| UINT64_C(1847615488), // RSUBHNv8i16_v16i8 |
| UINT64_C(773873664), // RSUBHNv8i16_v8i8 |
| UINT64_C(1170259968), // SABALB_ZZZ_D |
| UINT64_C(1161871360), // SABALB_ZZZ_H |
| UINT64_C(1166065664), // SABALB_ZZZ_S |
| UINT64_C(1170260992), // SABALT_ZZZ_D |
| UINT64_C(1161872384), // SABALT_ZZZ_H |
| UINT64_C(1166066688), // SABALT_ZZZ_S |
| UINT64_C(1310740480), // SABALv16i8_v8i16 |
| UINT64_C(245387264), // SABALv2i32_v2i64 |
| UINT64_C(241192960), // SABALv4i16_v4i32 |
| UINT64_C(1319129088), // SABALv4i32_v2i64 |
| UINT64_C(1314934784), // SABALv8i16_v4i32 |
| UINT64_C(236998656), // SABALv8i8_v8i16 |
| UINT64_C(1157691392), // SABA_ZZZ_B |
| UINT64_C(1170274304), // SABA_ZZZ_D |
| UINT64_C(1161885696), // SABA_ZZZ_H |
| UINT64_C(1166080000), // SABA_ZZZ_S |
| UINT64_C(1310751744), // SABAv16i8 |
| UINT64_C(245398528), // SABAv2i32 |
| UINT64_C(241204224), // SABAv4i16 |
| UINT64_C(1319140352), // SABAv4i32 |
| UINT64_C(1314946048), // SABAv8i16 |
| UINT64_C(237009920), // SABAv8i8 |
| UINT64_C(1170223104), // SABDLB_ZZZ_D |
| UINT64_C(1161834496), // SABDLB_ZZZ_H |
| UINT64_C(1166028800), // SABDLB_ZZZ_S |
| UINT64_C(1170224128), // SABDLT_ZZZ_D |
| UINT64_C(1161835520), // SABDLT_ZZZ_H |
| UINT64_C(1166029824), // SABDLT_ZZZ_S |
| UINT64_C(1310748672), // SABDLv16i8_v8i16 |
| UINT64_C(245395456), // SABDLv2i32_v2i64 |
| UINT64_C(241201152), // SABDLv4i16_v4i32 |
| UINT64_C(1319137280), // SABDLv4i32_v2i64 |
| UINT64_C(1314942976), // SABDLv8i16_v4i32 |
| UINT64_C(237006848), // SABDLv8i8_v8i16 |
| UINT64_C(67895296), // SABD_ZPmZ_B |
| UINT64_C(80478208), // SABD_ZPmZ_D |
| UINT64_C(72089600), // SABD_ZPmZ_H |
| UINT64_C(76283904), // SABD_ZPmZ_S |
| UINT64_C(1310749696), // SABDv16i8 |
| UINT64_C(245396480), // SABDv2i32 |
| UINT64_C(241202176), // SABDv4i16 |
| UINT64_C(1319138304), // SABDv4i32 |
| UINT64_C(1314944000), // SABDv8i16 |
| UINT64_C(237007872), // SABDv8i8 |
| UINT64_C(1153736704), // SADALP_ZPmZ_D |
| UINT64_C(1145348096), // SADALP_ZPmZ_H |
| UINT64_C(1149542400), // SADALP_ZPmZ_S |
| UINT64_C(1310746624), // SADALPv16i8_v8i16 |
| UINT64_C(245393408), // SADALPv2i32_v1i64 |
| UINT64_C(241199104), // SADALPv4i16_v2i32 |
| UINT64_C(1319135232), // SADALPv4i32_v2i64 |
| UINT64_C(1314940928), // SADALPv8i16_v4i32 |
| UINT64_C(237004800), // SADALPv8i8_v4i16 |
| UINT64_C(1170243584), // SADDLBT_ZZZ_D |
| UINT64_C(1161854976), // SADDLBT_ZZZ_H |
| UINT64_C(1166049280), // SADDLBT_ZZZ_S |
| UINT64_C(1170210816), // SADDLB_ZZZ_D |
| UINT64_C(1161822208), // SADDLB_ZZZ_H |
| UINT64_C(1166016512), // SADDLB_ZZZ_S |
| UINT64_C(1310730240), // SADDLPv16i8_v8i16 |
| UINT64_C(245377024), // SADDLPv2i32_v1i64 |
| UINT64_C(241182720), // SADDLPv4i16_v2i32 |
| UINT64_C(1319118848), // SADDLPv4i32_v2i64 |
| UINT64_C(1314924544), // SADDLPv8i16_v4i32 |
| UINT64_C(236988416), // SADDLPv8i8_v4i16 |
| UINT64_C(1170211840), // SADDLT_ZZZ_D |
| UINT64_C(1161823232), // SADDLT_ZZZ_H |
| UINT64_C(1166017536), // SADDLT_ZZZ_S |
| UINT64_C(1311782912), // SADDLVv16i8v |
| UINT64_C(242235392), // SADDLVv4i16v |
| UINT64_C(1320171520), // SADDLVv4i32v |
| UINT64_C(1315977216), // SADDLVv8i16v |
| UINT64_C(238041088), // SADDLVv8i8v |
| UINT64_C(1310720000), // SADDLv16i8_v8i16 |
| UINT64_C(245366784), // SADDLv2i32_v2i64 |
| UINT64_C(241172480), // SADDLv4i16_v4i32 |
| UINT64_C(1319108608), // SADDLv4i32_v2i64 |
| UINT64_C(1314914304), // SADDLv8i16_v4i32 |
| UINT64_C(236978176), // SADDLv8i8_v8i16 |
| UINT64_C(67117056), // SADDV_VPZ_B |
| UINT64_C(71311360), // SADDV_VPZ_H |
| UINT64_C(75505664), // SADDV_VPZ_S |
| UINT64_C(1170227200), // SADDWB_ZZZ_D |
| UINT64_C(1161838592), // SADDWB_ZZZ_H |
| UINT64_C(1166032896), // SADDWB_ZZZ_S |
| UINT64_C(1170228224), // SADDWT_ZZZ_D |
| UINT64_C(1161839616), // SADDWT_ZZZ_H |
| UINT64_C(1166033920), // SADDWT_ZZZ_S |
| UINT64_C(1310724096), // SADDWv16i8_v8i16 |
| UINT64_C(245370880), // SADDWv2i32_v2i64 |
| UINT64_C(241176576), // SADDWv4i16_v4i32 |
| UINT64_C(1319112704), // SADDWv4i32_v2i64 |
| UINT64_C(1314918400), // SADDWv8i16_v4i32 |
| UINT64_C(236982272), // SADDWv8i8_v8i16 |
| UINT64_C(3573756159), // SB |
| UINT64_C(1170264064), // SBCLB_ZZZ_D |
| UINT64_C(1166069760), // SBCLB_ZZZ_S |
| UINT64_C(1170265088), // SBCLT_ZZZ_D |
| UINT64_C(1166070784), // SBCLT_ZZZ_S |
| UINT64_C(2046820352), // SBCSWr |
| UINT64_C(4194304000), // SBCSXr |
| UINT64_C(1509949440), // SBCWr |
| UINT64_C(3657433088), // SBCXr |
| UINT64_C(318767104), // SBFMWri |
| UINT64_C(2470445056), // SBFMXri |
| UINT64_C(507674624), // SCVTFSWDri |
| UINT64_C(516063232), // SCVTFSWHri |
| UINT64_C(503480320), // SCVTFSWSri |
| UINT64_C(2655125504), // SCVTFSXDri |
| UINT64_C(2663514112), // SCVTFSXHri |
| UINT64_C(2650931200), // SCVTFSXSri |
| UINT64_C(509739008), // SCVTFUWDri |
| UINT64_C(518127616), // SCVTFUWHri |
| UINT64_C(505544704), // SCVTFUWSri |
| UINT64_C(2657222656), // SCVTFUXDri |
| UINT64_C(2665611264), // SCVTFUXHri |
| UINT64_C(2653028352), // SCVTFUXSri |
| UINT64_C(1708564480), // SCVTF_ZPmZ_DtoD |
| UINT64_C(1700175872), // SCVTF_ZPmZ_DtoH |
| UINT64_C(1708433408), // SCVTF_ZPmZ_DtoS |
| UINT64_C(1699913728), // SCVTF_ZPmZ_HtoH |
| UINT64_C(1708171264), // SCVTF_ZPmZ_StoD |
| UINT64_C(1700044800), // SCVTF_ZPmZ_StoH |
| UINT64_C(1704239104), // SCVTF_ZPmZ_StoS |
| UINT64_C(1598088192), // SCVTFd |
| UINT64_C(1594942464), // SCVTFh |
| UINT64_C(1595991040), // SCVTFs |
| UINT64_C(1585043456), // SCVTFv1i16 |
| UINT64_C(1579276288), // SCVTFv1i32 |
| UINT64_C(1583470592), // SCVTFv1i64 |
| UINT64_C(237099008), // SCVTFv2f32 |
| UINT64_C(1315035136), // SCVTFv2f64 |
| UINT64_C(253813760), // SCVTFv2i32_shift |
| UINT64_C(1329652736), // SCVTFv2i64_shift |
| UINT64_C(242866176), // SCVTFv4f16 |
| UINT64_C(1310840832), // SCVTFv4f32 |
| UINT64_C(252765184), // SCVTFv4i16_shift |
| UINT64_C(1327555584), // SCVTFv4i32_shift |
| UINT64_C(1316608000), // SCVTFv8f16 |
| UINT64_C(1326507008), // SCVTFv8i16_shift |
| UINT64_C(81133568), // SDIVR_ZPmZ_D |
| UINT64_C(76939264), // SDIVR_ZPmZ_S |
| UINT64_C(448793600), // SDIVWr |
| UINT64_C(2596277248), // SDIVXr |
| UINT64_C(81002496), // SDIV_ZPmZ_D |
| UINT64_C(76808192), // SDIV_ZPmZ_S |
| UINT64_C(1155530752), // SDOT_ZZZI_D |
| UINT64_C(1151336448), // SDOT_ZZZI_S |
| UINT64_C(1153433600), // SDOT_ZZZ_D |
| UINT64_C(1149239296), // SDOT_ZZZ_S |
| UINT64_C(1333846016), // SDOTlanev16i8 |
| UINT64_C(260104192), // SDOTlanev8i8 |
| UINT64_C(1317049344), // SDOTv16i8 |
| UINT64_C(243307520), // SDOTv8i8 |
| UINT64_C(620773904), // SEL_PPPP |
| UINT64_C(86032384), // SEL_ZPZZ_B |
| UINT64_C(98615296), // SEL_ZPZZ_D |
| UINT64_C(90226688), // SEL_ZPZZ_H |
| UINT64_C(94420992), // SEL_ZPZZ_S |
| UINT64_C(973096973), // SETF16 |
| UINT64_C(973080589), // SETF8 |
| UINT64_C(623677440), // SETFFR |
| UINT64_C(1577058304), // SHA1Crrr |
| UINT64_C(1579681792), // SHA1Hrr |
| UINT64_C(1577066496), // SHA1Mrrr |
| UINT64_C(1577062400), // SHA1Prrr |
| UINT64_C(1577070592), // SHA1SU0rrr |
| UINT64_C(1579685888), // SHA1SU1rr |
| UINT64_C(1577078784), // SHA256H2rrr |
| UINT64_C(1577074688), // SHA256Hrrr |
| UINT64_C(1579689984), // SHA256SU0rr |
| UINT64_C(1577082880), // SHA256SU1rrr |
| UINT64_C(3462430720), // SHA512H |
| UINT64_C(3462431744), // SHA512H2 |
| UINT64_C(3468722176), // SHA512SU0 |
| UINT64_C(3462432768), // SHA512SU1 |
| UINT64_C(1141932032), // SHADD_ZPmZ_B |
| UINT64_C(1154514944), // SHADD_ZPmZ_D |
| UINT64_C(1146126336), // SHADD_ZPmZ_H |
| UINT64_C(1150320640), // SHADD_ZPmZ_S |
| UINT64_C(1310721024), // SHADDv16i8 |
| UINT64_C(245367808), // SHADDv2i32 |
| UINT64_C(241173504), // SHADDv4i16 |
| UINT64_C(1319109632), // SHADDv4i32 |
| UINT64_C(1314915328), // SHADDv8i16 |
| UINT64_C(236979200), // SHADDv8i8 |
| UINT64_C(1847670784), // SHLLv16i8 |
| UINT64_C(782317568), // SHLLv2i32 |
| UINT64_C(778123264), // SHLLv4i16 |
| UINT64_C(1856059392), // SHLLv4i32 |
| UINT64_C(1851865088), // SHLLv8i16 |
| UINT64_C(773928960), // SHLLv8i8 |
| UINT64_C(1598051328), // SHLd |
| UINT64_C(1325945856), // SHLv16i8_shift |
| UINT64_C(253776896), // SHLv2i32_shift |
| UINT64_C(1329615872), // SHLv2i64_shift |
| UINT64_C(252728320), // SHLv4i16_shift |
| UINT64_C(1327518720), // SHLv4i32_shift |
| UINT64_C(1326470144), // SHLv8i16_shift |
| UINT64_C(252204032), // SHLv8i8_shift |
| UINT64_C(1160253440), // SHRNB_ZZI_B |
| UINT64_C(1160777728), // SHRNB_ZZI_H |
| UINT64_C(1163923456), // SHRNB_ZZI_S |
| UINT64_C(1160254464), // SHRNT_ZZI_B |
| UINT64_C(1160778752), // SHRNT_ZZI_H |
| UINT64_C(1163924480), // SHRNT_ZZI_S |
| UINT64_C(1325958144), // SHRNv16i8_shift |
| UINT64_C(253789184), // SHRNv2i32_shift |
| UINT64_C(252740608), // SHRNv4i16_shift |
| UINT64_C(1327531008), // SHRNv4i32_shift |
| UINT64_C(1326482432), // SHRNv8i16_shift |
| UINT64_C(252216320), // SHRNv8i8_shift |
| UINT64_C(1142325248), // SHSUBR_ZPmZ_B |
| UINT64_C(1154908160), // SHSUBR_ZPmZ_D |
| UINT64_C(1146519552), // SHSUBR_ZPmZ_H |
| UINT64_C(1150713856), // SHSUBR_ZPmZ_S |
| UINT64_C(1142063104), // SHSUB_ZPmZ_B |
| UINT64_C(1154646016), // SHSUB_ZPmZ_D |
| UINT64_C(1146257408), // SHSUB_ZPmZ_H |
| UINT64_C(1150451712), // SHSUB_ZPmZ_S |
| UINT64_C(1310729216), // SHSUBv16i8 |
| UINT64_C(245376000), // SHSUBv2i32 |
| UINT64_C(241181696), // SHSUBv4i16 |
| UINT64_C(1319117824), // SHSUBv4i32 |
| UINT64_C(1314923520), // SHSUBv8i16 |
| UINT64_C(236987392), // SHSUBv8i8 |
| UINT64_C(1158214656), // SLI_ZZI_B |
| UINT64_C(1166078976), // SLI_ZZI_D |
| UINT64_C(1158738944), // SLI_ZZI_H |
| UINT64_C(1161884672), // SLI_ZZI_S |
| UINT64_C(2134922240), // SLId |
| UINT64_C(1862816768), // SLIv16i8_shift |
| UINT64_C(790647808), // SLIv2i32_shift |
| UINT64_C(1866486784), // SLIv2i64_shift |
| UINT64_C(789599232), // SLIv4i16_shift |
| UINT64_C(1864389632), // SLIv4i32_shift |
| UINT64_C(1863341056), // SLIv8i16_shift |
| UINT64_C(789074944), // SLIv8i8_shift |
| UINT64_C(3462447104), // SM3PARTW1 |
| UINT64_C(3462448128), // SM3PARTW2 |
| UINT64_C(3460300800), // SM3SS1 |
| UINT64_C(3460333568), // SM3TT1A |
| UINT64_C(3460334592), // SM3TT1B |
| UINT64_C(3460335616), // SM3TT2A |
| UINT64_C(3460336640), // SM3TT2B |
| UINT64_C(3468723200), // SM4E |
| UINT64_C(1159786496), // SM4EKEY_ZZZ_S |
| UINT64_C(3462449152), // SM4ENCKEY |
| UINT64_C(1159979008), // SM4E_ZZZ_S |
| UINT64_C(2602565632), // SMADDLrrr |
| UINT64_C(1142202368), // SMAXP_ZPmZ_B |
| UINT64_C(1154785280), // SMAXP_ZPmZ_D |
| UINT64_C(1146396672), // SMAXP_ZPmZ_H |
| UINT64_C(1150590976), // SMAXP_ZPmZ_S |
| UINT64_C(1310761984), // SMAXPv16i8 |
| UINT64_C(245408768), // SMAXPv2i32 |
| UINT64_C(241214464), // SMAXPv4i16 |
| UINT64_C(1319150592), // SMAXPv4i32 |
| UINT64_C(1314956288), // SMAXPv8i16 |
| UINT64_C(237020160), // SMAXPv8i8 |
| UINT64_C(67641344), // SMAXV_VPZ_B |
| UINT64_C(80224256), // SMAXV_VPZ_D |
| UINT64_C(71835648), // SMAXV_VPZ_H |
| UINT64_C(76029952), // SMAXV_VPZ_S |
| UINT64_C(1311811584), // SMAXVv16i8v |
| UINT64_C(242264064), // SMAXVv4i16v |
| UINT64_C(1320200192), // SMAXVv4i32v |
| UINT64_C(1316005888), // SMAXVv8i16v |
| UINT64_C(238069760), // SMAXVv8i8v |
| UINT64_C(623427584), // SMAX_ZI_B |
| UINT64_C(636010496), // SMAX_ZI_D |
| UINT64_C(627621888), // SMAX_ZI_H |
| UINT64_C(631816192), // SMAX_ZI_S |
| UINT64_C(67633152), // SMAX_ZPmZ_B |
| UINT64_C(80216064), // SMAX_ZPmZ_D |
| UINT64_C(71827456), // SMAX_ZPmZ_H |
| UINT64_C(76021760), // SMAX_ZPmZ_S |
| UINT64_C(1310745600), // SMAXv16i8 |
| UINT64_C(245392384), // SMAXv2i32 |
| UINT64_C(241198080), // SMAXv4i16 |
| UINT64_C(1319134208), // SMAXv4i32 |
| UINT64_C(1314939904), // SMAXv8i16 |
| UINT64_C(237003776), // SMAXv8i8 |
| UINT64_C(3556769795), // SMC |
| UINT64_C(1142333440), // SMINP_ZPmZ_B |
| UINT64_C(1154916352), // SMINP_ZPmZ_D |
| UINT64_C(1146527744), // SMINP_ZPmZ_H |
| UINT64_C(1150722048), // SMINP_ZPmZ_S |
| UINT64_C(1310764032), // SMINPv16i8 |
| UINT64_C(245410816), // SMINPv2i32 |
| UINT64_C(241216512), // SMINPv4i16 |
| UINT64_C(1319152640), // SMINPv4i32 |
| UINT64_C(1314958336), // SMINPv8i16 |
| UINT64_C(237022208), // SMINPv8i8 |
| UINT64_C(67772416), // SMINV_VPZ_B |
| UINT64_C(80355328), // SMINV_VPZ_D |
| UINT64_C(71966720), // SMINV_VPZ_H |
| UINT64_C(76161024), // SMINV_VPZ_S |
| UINT64_C(1311877120), // SMINVv16i8v |
| UINT64_C(242329600), // SMINVv4i16v |
| UINT64_C(1320265728), // SMINVv4i32v |
| UINT64_C(1316071424), // SMINVv8i16v |
| UINT64_C(238135296), // SMINVv8i8v |
| UINT64_C(623558656), // SMIN_ZI_B |
| UINT64_C(636141568), // SMIN_ZI_D |
| UINT64_C(627752960), // SMIN_ZI_H |
| UINT64_C(631947264), // SMIN_ZI_S |
| UINT64_C(67764224), // SMIN_ZPmZ_B |
| UINT64_C(80347136), // SMIN_ZPmZ_D |
| UINT64_C(71958528), // SMIN_ZPmZ_H |
| UINT64_C(76152832), // SMIN_ZPmZ_S |
| UINT64_C(1310747648), // SMINv16i8 |
| UINT64_C(245394432), // SMINv2i32 |
| UINT64_C(241200128), // SMINv4i16 |
| UINT64_C(1319136256), // SMINv4i32 |
| UINT64_C(1314941952), // SMINv8i16 |
| UINT64_C(237005824), // SMINv8i8 |
| UINT64_C(1155563520), // SMLALB_ZZZI_D |
| UINT64_C(1151369216), // SMLALB_ZZZI_S |
| UINT64_C(1153449984), // SMLALB_ZZZ_D |
| UINT64_C(1145061376), // SMLALB_ZZZ_H |
| UINT64_C(1149255680), // SMLALB_ZZZ_S |
| UINT64_C(1155564544), // SMLALT_ZZZI_D |
| UINT64_C(1151370240), // SMLALT_ZZZI_S |
| UINT64_C(1153451008), // SMLALT_ZZZ_D |
| UINT64_C(1145062400), // SMLALT_ZZZ_H |
| UINT64_C(1149256704), // SMLALT_ZZZ_S |
| UINT64_C(1310752768), // SMLALv16i8_v8i16 |
| UINT64_C(260055040), // SMLALv2i32_indexed |
| UINT64_C(245399552), // SMLALv2i32_v2i64 |
| UINT64_C(255860736), // SMLALv4i16_indexed |
| UINT64_C(241205248), // SMLALv4i16_v4i32 |
| UINT64_C(1333796864), // SMLALv4i32_indexed |
| UINT64_C(1319141376), // SMLALv4i32_v2i64 |
| UINT64_C(1329602560), // SMLALv8i16_indexed |
| UINT64_C(1314947072), // SMLALv8i16_v4i32 |
| UINT64_C(237010944), // SMLALv8i8_v8i16 |
| UINT64_C(1155571712), // SMLSLB_ZZZI_D |
| UINT64_C(1151377408), // SMLSLB_ZZZI_S |
| UINT64_C(1153454080), // SMLSLB_ZZZ_D |
| UINT64_C(1145065472), // SMLSLB_ZZZ_H |
| UINT64_C(1149259776), // SMLSLB_ZZZ_S |
| UINT64_C(1155572736), // SMLSLT_ZZZI_D |
| UINT64_C(1151378432), // SMLSLT_ZZZI_S |
| UINT64_C(1153455104), // SMLSLT_ZZZ_D |
| UINT64_C(1145066496), // SMLSLT_ZZZ_H |
| UINT64_C(1149260800), // SMLSLT_ZZZ_S |
| UINT64_C(1310760960), // SMLSLv16i8_v8i16 |
| UINT64_C(260071424), // SMLSLv2i32_indexed |
| UINT64_C(245407744), // SMLSLv2i32_v2i64 |
| UINT64_C(255877120), // SMLSLv4i16_indexed |
| UINT64_C(241213440), // SMLSLv4i16_v4i32 |
| UINT64_C(1333813248), // SMLSLv4i32_indexed |
| UINT64_C(1319149568), // SMLSLv4i32_v2i64 |
| UINT64_C(1329618944), // SMLSLv8i16_indexed |
| UINT64_C(1314955264), // SMLSLv8i16_v4i32 |
| UINT64_C(237019136), // SMLSLv8i8_v8i16 |
| UINT64_C(235023360), // SMOVvi16to32 |
| UINT64_C(1308765184), // SMOVvi16to64 |
| UINT64_C(1308896256), // SMOVvi32to64 |
| UINT64_C(234957824), // SMOVvi8to32 |
| UINT64_C(1308699648), // SMOVvi8to64 |
| UINT64_C(2602598400), // SMSUBLrrr |
| UINT64_C(68288512), // SMULH_ZPmZ_B |
| UINT64_C(80871424), // SMULH_ZPmZ_D |
| UINT64_C(72482816), // SMULH_ZPmZ_H |
| UINT64_C(76677120), // SMULH_ZPmZ_S |
| UINT64_C(69232640), // SMULH_ZZZ_B |
| UINT64_C(81815552), // SMULH_ZZZ_D |
| UINT64_C(73426944), // SMULH_ZZZ_H |
| UINT64_C(77621248), // SMULH_ZZZ_S |
| UINT64_C(2604662784), // SMULHrr |
| UINT64_C(1155579904), // SMULLB_ZZZI_D |
| UINT64_C(1151385600), // SMULLB_ZZZI_S |
| UINT64_C(1170239488), // SMULLB_ZZZ_D |
| UINT64_C(1161850880), // SMULLB_ZZZ_H |
| UINT64_C(1166045184), // SMULLB_ZZZ_S |
| UINT64_C(1155580928), // SMULLT_ZZZI_D |
| UINT64_C(1151386624), // SMULLT_ZZZI_S |
| UINT64_C(1170240512), // SMULLT_ZZZ_D |
| UINT64_C(1161851904), // SMULLT_ZZZ_H |
| UINT64_C(1166046208), // SMULLT_ZZZ_S |
| UINT64_C(1310769152), // SMULLv16i8_v8i16 |
| UINT64_C(260087808), // SMULLv2i32_indexed |
| UINT64_C(245415936), // SMULLv2i32_v2i64 |
| UINT64_C(255893504), // SMULLv4i16_indexed |
| UINT64_C(241221632), // SMULLv4i16_v4i32 |
| UINT64_C(1333829632), // SMULLv4i32_indexed |
| UINT64_C(1319157760), // SMULLv4i32_v2i64 |
| UINT64_C(1329635328), // SMULLv8i16_indexed |
| UINT64_C(1314963456), // SMULLv8i16_v4i32 |
| UINT64_C(237027328), // SMULLv8i8_v8i16 |
| UINT64_C(0), // SPACE |
| UINT64_C(86867968), // SPLICE_ZPZZ_B |
| UINT64_C(99450880), // SPLICE_ZPZZ_D |
| UINT64_C(91062272), // SPLICE_ZPZZ_H |
| UINT64_C(95256576), // SPLICE_ZPZZ_S |
| UINT64_C(86802432), // SPLICE_ZPZ_B |
| UINT64_C(99385344), // SPLICE_ZPZ_D |
| UINT64_C(90996736), // SPLICE_ZPZ_H |
| UINT64_C(95191040), // SPLICE_ZPZ_S |
| UINT64_C(1141415936), // SQABS_ZPmZ_B |
| UINT64_C(1153998848), // SQABS_ZPmZ_D |
| UINT64_C(1145610240), // SQABS_ZPmZ_H |
| UINT64_C(1149804544), // SQABS_ZPmZ_S |
| UINT64_C(1310750720), // SQABSv16i8 |
| UINT64_C(1583380480), // SQABSv1i16 |
| UINT64_C(1587574784), // SQABSv1i32 |
| UINT64_C(1591769088), // SQABSv1i64 |
| UINT64_C(1579186176), // SQABSv1i8 |
| UINT64_C(245397504), // SQABSv2i32 |
| UINT64_C(1323333632), // SQABSv2i64 |
| UINT64_C(241203200), // SQABSv4i16 |
| UINT64_C(1319139328), // SQABSv4i32 |
| UINT64_C(1314945024), // SQABSv8i16 |
| UINT64_C(237008896), // SQABSv8i8 |
| UINT64_C(623165440), // SQADD_ZI_B |
| UINT64_C(635748352), // SQADD_ZI_D |
| UINT64_C(627359744), // SQADD_ZI_H |
| UINT64_C(631554048), // SQADD_ZI_S |
| UINT64_C(1142456320), // SQADD_ZPmZ_B |
| UINT64_C(1155039232), // SQADD_ZPmZ_D |
| UINT64_C(1146650624), // SQADD_ZPmZ_H |
| UINT64_C(1150844928), // SQADD_ZPmZ_S |
| UINT64_C(69210112), // SQADD_ZZZ_B |
| UINT64_C(81793024), // SQADD_ZZZ_D |
| UINT64_C(73404416), // SQADD_ZZZ_H |
| UINT64_C(77598720), // SQADD_ZZZ_S |
| UINT64_C(1310723072), // SQADDv16i8 |
| UINT64_C(1583352832), // SQADDv1i16 |
| UINT64_C(1587547136), // SQADDv1i32 |
| UINT64_C(1591741440), // SQADDv1i64 |
| UINT64_C(1579158528), // SQADDv1i8 |
| UINT64_C(245369856), // SQADDv2i32 |
| UINT64_C(1323305984), // SQADDv2i64 |
| UINT64_C(241175552), // SQADDv4i16 |
| UINT64_C(1319111680), // SQADDv4i32 |
| UINT64_C(1314917376), // SQADDv8i16 |
| UINT64_C(236981248), // SQADDv8i8 |
| UINT64_C(1157748736), // SQCADD_ZZI_B |
| UINT64_C(1170331648), // SQCADD_ZZI_D |
| UINT64_C(1161943040), // SQCADD_ZZI_H |
| UINT64_C(1166137344), // SQCADD_ZZI_S |
| UINT64_C(70318080), // SQDECB_XPiI |
| UINT64_C(69269504), // SQDECB_XPiWdI |
| UINT64_C(82900992), // SQDECD_XPiI |
| UINT64_C(81852416), // SQDECD_XPiWdI |
| UINT64_C(81840128), // SQDECD_ZPiI |
| UINT64_C(74512384), // SQDECH_XPiI |
| UINT64_C(73463808), // SQDECH_XPiWdI |
| UINT64_C(73451520), // SQDECH_ZPiI |
| UINT64_C(623544320), // SQDECP_XPWd_B |
| UINT64_C(636127232), // SQDECP_XPWd_D |
| UINT64_C(627738624), // SQDECP_XPWd_H |
| UINT64_C(631932928), // SQDECP_XPWd_S |
| UINT64_C(623545344), // SQDECP_XP_B |
| UINT64_C(636128256), // SQDECP_XP_D |
| UINT64_C(627739648), // SQDECP_XP_H |
| UINT64_C(631933952), // SQDECP_XP_S |
| UINT64_C(636125184), // SQDECP_ZP_D |
| UINT64_C(627736576), // SQDECP_ZP_H |
| UINT64_C(631930880), // SQDECP_ZP_S |
| UINT64_C(78706688), // SQDECW_XPiI |
| UINT64_C(77658112), // SQDECW_XPiWdI |
| UINT64_C(77645824), // SQDECW_ZPiI |
| UINT64_C(1153435648), // SQDMLALBT_ZZZ_D |
| UINT64_C(1145047040), // SQDMLALBT_ZZZ_H |
| UINT64_C(1149241344), // SQDMLALBT_ZZZ_S |
| UINT64_C(1155538944), // SQDMLALB_ZZZI_D |
| UINT64_C(1151344640), // SQDMLALB_ZZZI_S |
| UINT64_C(1153458176), // SQDMLALB_ZZZ_D |
| UINT64_C(1145069568), // SQDMLALB_ZZZ_H |
| UINT64_C(1149263872), // SQDMLALB_ZZZ_S |
| UINT64_C(1155539968), // SQDMLALT_ZZZI_D |
| UINT64_C(1151345664), // SQDMLALT_ZZZI_S |
| UINT64_C(1153459200), // SQDMLALT_ZZZ_D |
| UINT64_C(1145070592), // SQDMLALT_ZZZ_H |
| UINT64_C(1149264896), // SQDMLALT_ZZZ_S |
| UINT64_C(1583386624), // SQDMLALi16 |
| UINT64_C(1587580928), // SQDMLALi32 |
| UINT64_C(1598042112), // SQDMLALv1i32_indexed |
| UINT64_C(1602236416), // SQDMLALv1i64_indexed |
| UINT64_C(260059136), // SQDMLALv2i32_indexed |
| UINT64_C(245403648), // SQDMLALv2i32_v2i64 |
| UINT64_C(255864832), // SQDMLALv4i16_indexed |
| UINT64_C(241209344), // SQDMLALv4i16_v4i32 |
| UINT64_C(1333800960), // SQDMLALv4i32_indexed |
| UINT64_C(1319145472), // SQDMLALv4i32_v2i64 |
| UINT64_C(1329606656), // SQDMLALv8i16_indexed |
| UINT64_C(1314951168), // SQDMLALv8i16_v4i32 |
| UINT64_C(1153436672), // SQDMLSLBT_ZZZ_D |
| UINT64_C(1145048064), // SQDMLSLBT_ZZZ_H |
| UINT64_C(1149242368), // SQDMLSLBT_ZZZ_S |
| UINT64_C(1155543040), // SQDMLSLB_ZZZI_D |
| UINT64_C(1151348736), // SQDMLSLB_ZZZI_S |
| UINT64_C(1153460224), // SQDMLSLB_ZZZ_D |
| UINT64_C(1145071616), // SQDMLSLB_ZZZ_H |
| UINT64_C(1149265920), // SQDMLSLB_ZZZ_S |
| UINT64_C(1155544064), // SQDMLSLT_ZZZI_D |
| UINT64_C(1151349760), // SQDMLSLT_ZZZI_S |
| UINT64_C(1153461248), // SQDMLSLT_ZZZ_D |
| UINT64_C(1145072640), // SQDMLSLT_ZZZ_H |
| UINT64_C(1149266944), // SQDMLSLT_ZZZ_S |
| UINT64_C(1583394816), // SQDMLSLi16 |
| UINT64_C(1587589120), // SQDMLSLi32 |
| UINT64_C(1598058496), // SQDMLSLv1i32_indexed |
| UINT64_C(1602252800), // SQDMLSLv1i64_indexed |
| UINT64_C(260075520), // SQDMLSLv2i32_indexed |
| UINT64_C(245411840), // SQDMLSLv2i32_v2i64 |
| UINT64_C(255881216), // SQDMLSLv4i16_indexed |
| UINT64_C(241217536), // SQDMLSLv4i16_v4i32 |
| UINT64_C(1333817344), // SQDMLSLv4i32_indexed |
| UINT64_C(1319153664), // SQDMLSLv4i32_v2i64 |
| UINT64_C(1329623040), // SQDMLSLv8i16_indexed |
| UINT64_C(1314959360), // SQDMLSLv8i16_v4i32 |
| UINT64_C(1155592192), // SQDMULH_ZZZI_D |
| UINT64_C(1143009280), // SQDMULH_ZZZI_H |
| UINT64_C(1151397888), // SQDMULH_ZZZI_S |
| UINT64_C(69234688), // SQDMULH_ZZZ_B |
| UINT64_C(81817600), // SQDMULH_ZZZ_D |
| UINT64_C(73428992), // SQDMULH_ZZZ_H |
| UINT64_C(77623296), // SQDMULH_ZZZ_S |
| UINT64_C(1583395840), // SQDMULHv1i16 |
| UINT64_C(1598078976), // SQDMULHv1i16_indexed |
| UINT64_C(1587590144), // SQDMULHv1i32 |
| UINT64_C(1602273280), // SQDMULHv1i32_indexed |
| UINT64_C(245412864), // SQDMULHv2i32 |
| UINT64_C(260096000), // SQDMULHv2i32_indexed |
| UINT64_C(241218560), // SQDMULHv4i16 |
| UINT64_C(255901696), // SQDMULHv4i16_indexed |
| UINT64_C(1319154688), // SQDMULHv4i32 |
| UINT64_C(1333837824), // SQDMULHv4i32_indexed |
| UINT64_C(1314960384), // SQDMULHv8i16 |
| UINT64_C(1329643520), // SQDMULHv8i16_indexed |
| UINT64_C(1155588096), // SQDMULLB_ZZZI_D |
| UINT64_C(1151393792), // SQDMULLB_ZZZI_S |
| UINT64_C(1170235392), // SQDMULLB_ZZZ_D |
| UINT64_C(1161846784), // SQDMULLB_ZZZ_H |
| UINT64_C(1166041088), // SQDMULLB_ZZZ_S |
| UINT64_C(1155589120), // SQDMULLT_ZZZI_D |
| UINT64_C(1151394816), // SQDMULLT_ZZZI_S |
| UINT64_C(1170236416), // SQDMULLT_ZZZ_D |
| UINT64_C(1161847808), // SQDMULLT_ZZZ_H |
| UINT64_C(1166042112), // SQDMULLT_ZZZ_S |
| UINT64_C(1583403008), // SQDMULLi16 |
| UINT64_C(1587597312), // SQDMULLi32 |
| UINT64_C(1598074880), // SQDMULLv1i32_indexed |
| UINT64_C(1602269184), // SQDMULLv1i64_indexed |
| UINT64_C(260091904), // SQDMULLv2i32_indexed |
| UINT64_C(245420032), // SQDMULLv2i32_v2i64 |
| UINT64_C(255897600), // SQDMULLv4i16_indexed |
| UINT64_C(241225728), // SQDMULLv4i16_v4i32 |
| UINT64_C(1333833728), // SQDMULLv4i32_indexed |
| UINT64_C(1319161856), // SQDMULLv4i32_v2i64 |
| UINT64_C(1329639424), // SQDMULLv8i16_indexed |
| UINT64_C(1314967552), // SQDMULLv8i16_v4i32 |
| UINT64_C(70316032), // SQINCB_XPiI |
| UINT64_C(69267456), // SQINCB_XPiWdI |
| UINT64_C(82898944), // SQINCD_XPiI |
| UINT64_C(81850368), // SQINCD_XPiWdI |
| UINT64_C(81838080), // SQINCD_ZPiI |
| UINT64_C(74510336), // SQINCH_XPiI |
| UINT64_C(73461760), // SQINCH_XPiWdI |
| UINT64_C(73449472), // SQINCH_ZPiI |
| UINT64_C(623413248), // SQINCP_XPWd_B |
| UINT64_C(635996160), // SQINCP_XPWd_D |
| UINT64_C(627607552), // SQINCP_XPWd_H |
| UINT64_C(631801856), // SQINCP_XPWd_S |
| UINT64_C(623414272), // SQINCP_XP_B |
| UINT64_C(635997184), // SQINCP_XP_D |
| UINT64_C(627608576), // SQINCP_XP_H |
| UINT64_C(631802880), // SQINCP_XP_S |
| UINT64_C(635994112), // SQINCP_ZP_D |
| UINT64_C(627605504), // SQINCP_ZP_H |
| UINT64_C(631799808), // SQINCP_ZP_S |
| UINT64_C(78704640), // SQINCW_XPiI |
| UINT64_C(77656064), // SQINCW_XPiWdI |
| UINT64_C(77643776), // SQINCW_ZPiI |
| UINT64_C(1141481472), // SQNEG_ZPmZ_B |
| UINT64_C(1154064384), // SQNEG_ZPmZ_D |
| UINT64_C(1145675776), // SQNEG_ZPmZ_H |
| UINT64_C(1149870080), // SQNEG_ZPmZ_S |
| UINT64_C(1847621632), // SQNEGv16i8 |
| UINT64_C(2120251392), // SQNEGv1i16 |
| UINT64_C(2124445696), // SQNEGv1i32 |
| UINT64_C(2128640000), // SQNEGv1i64 |
| UINT64_C(2116057088), // SQNEGv1i8 |
| UINT64_C(782268416), // SQNEGv2i32 |
| UINT64_C(1860204544), // SQNEGv2i64 |
| UINT64_C(778074112), // SQNEGv4i16 |
| UINT64_C(1856010240), // SQNEGv4i32 |
| UINT64_C(1851815936), // SQNEGv8i16 |
| UINT64_C(773879808), // SQNEGv8i8 |
| UINT64_C(1151365120), // SQRDCMLAH_ZZZI_H |
| UINT64_C(1155559424), // SQRDCMLAH_ZZZI_S |
| UINT64_C(1140862976), // SQRDCMLAH_ZZZ_B |
| UINT64_C(1153445888), // SQRDCMLAH_ZZZ_D |
| UINT64_C(1145057280), // SQRDCMLAH_ZZZ_H |
| UINT64_C(1149251584), // SQRDCMLAH_ZZZ_S |
| UINT64_C(1155534848), // SQRDMLAH_ZZZI_D |
| UINT64_C(1142951936), // SQRDMLAH_ZZZI_H |
| UINT64_C(1151340544), // SQRDMLAH_ZZZI_S |
| UINT64_C(1140879360), // SQRDMLAH_ZZZ_B |
| UINT64_C(1153462272), // SQRDMLAH_ZZZ_D |
| UINT64_C(1145073664), // SQRDMLAH_ZZZ_H |
| UINT64_C(1149267968), // SQRDMLAH_ZZZ_S |
| UINT64_C(2134953984), // SQRDMLAHi16_indexed |
| UINT64_C(2139148288), // SQRDMLAHi32_indexed |
| UINT64_C(2118157312), // SQRDMLAHv1i16 |
| UINT64_C(2122351616), // SQRDMLAHv1i32 |
| UINT64_C(780174336), // SQRDMLAHv2i32 |
| UINT64_C(796971008), // SQRDMLAHv2i32_indexed |
| UINT64_C(775980032), // SQRDMLAHv4i16 |
| UINT64_C(792776704), // SQRDMLAHv4i16_indexed |
| UINT64_C(1853916160), // SQRDMLAHv4i32 |
| UINT64_C(1870712832), // SQRDMLAHv4i32_indexed |
| UINT64_C(1849721856), // SQRDMLAHv8i16 |
| UINT64_C(1866518528), // SQRDMLAHv8i16_indexed |
| UINT64_C(1155535872), // SQRDMLSH_ZZZI_D |
| UINT64_C(1142952960), // SQRDMLSH_ZZZI_H |
| UINT64_C(1151341568), // SQRDMLSH_ZZZI_S |
| UINT64_C(1140880384), // SQRDMLSH_ZZZ_B |
| UINT64_C(1153463296), // SQRDMLSH_ZZZ_D |
| UINT64_C(1145074688), // SQRDMLSH_ZZZ_H |
| UINT64_C(1149268992), // SQRDMLSH_ZZZ_S |
| UINT64_C(2134962176), // SQRDMLSHi16_indexed |
| UINT64_C(2139156480), // SQRDMLSHi32_indexed |
| UINT64_C(2118159360), // SQRDMLSHv1i16 |
| UINT64_C(2122353664), // SQRDMLSHv1i32 |
| UINT64_C(780176384), // SQRDMLSHv2i32 |
| UINT64_C(796979200), // SQRDMLSHv2i32_indexed |
| UINT64_C(775982080), // SQRDMLSHv4i16 |
| UINT64_C(792784896), // SQRDMLSHv4i16_indexed |
| UINT64_C(1853918208), // SQRDMLSHv4i32 |
| UINT64_C(1870721024), // SQRDMLSHv4i32_indexed |
| UINT64_C(1849723904), // SQRDMLSHv8i16 |
| UINT64_C(1866526720), // SQRDMLSHv8i16_indexed |
| UINT64_C(1155593216), // SQRDMULH_ZZZI_D |
| UINT64_C(1143010304), // SQRDMULH_ZZZI_H |
| UINT64_C(1151398912), // SQRDMULH_ZZZI_S |
| UINT64_C(69235712), // SQRDMULH_ZZZ_B |
| UINT64_C(81818624), // SQRDMULH_ZZZ_D |
| UINT64_C(73430016), // SQRDMULH_ZZZ_H |
| UINT64_C(77624320), // SQRDMULH_ZZZ_S |
| UINT64_C(2120266752), // SQRDMULHv1i16 |
| UINT64_C(1598083072), // SQRDMULHv1i16_indexed |
| UINT64_C(2124461056), // SQRDMULHv1i32 |
| UINT64_C(1602277376), // SQRDMULHv1i32_indexed |
| UINT64_C(782283776), // SQRDMULHv2i32 |
| UINT64_C(260100096), // SQRDMULHv2i32_indexed |
| UINT64_C(778089472), // SQRDMULHv4i16 |
| UINT64_C(255905792), // SQRDMULHv4i16_indexed |
| UINT64_C(1856025600), // SQRDMULHv4i32 |
| UINT64_C(1333841920), // SQRDMULHv4i32_indexed |
| UINT64_C(1851831296), // SQRDMULHv8i16 |
| UINT64_C(1329647616), // SQRDMULHv8i16_indexed |
| UINT64_C(1141800960), // SQRSHLR_ZPmZ_B |
| UINT64_C(1154383872), // SQRSHLR_ZPmZ_D |
| UINT64_C(1145995264), // SQRSHLR_ZPmZ_H |
| UINT64_C(1150189568), // SQRSHLR_ZPmZ_S |
| UINT64_C(1141538816), // SQRSHL_ZPmZ_B |
| UINT64_C(1154121728), // SQRSHL_ZPmZ_D |
| UINT64_C(1145733120), // SQRSHL_ZPmZ_H |
| UINT64_C(1149927424), // SQRSHL_ZPmZ_S |
| UINT64_C(1310743552), // SQRSHLv16i8 |
| UINT64_C(1583373312), // SQRSHLv1i16 |
| UINT64_C(1587567616), // SQRSHLv1i32 |
| UINT64_C(1591761920), // SQRSHLv1i64 |
| UINT64_C(1579179008), // SQRSHLv1i8 |
| UINT64_C(245390336), // SQRSHLv2i32 |
| UINT64_C(1323326464), // SQRSHLv2i64 |
| UINT64_C(241196032), // SQRSHLv4i16 |
| UINT64_C(1319132160), // SQRSHLv4i32 |
| UINT64_C(1314937856), // SQRSHLv8i16 |
| UINT64_C(237001728), // SQRSHLv8i8 |
| UINT64_C(1160259584), // SQRSHRNB_ZZI_B |
| UINT64_C(1160783872), // SQRSHRNB_ZZI_H |
| UINT64_C(1163929600), // SQRSHRNB_ZZI_S |
| UINT64_C(1160260608), // SQRSHRNT_ZZI_B |
| UINT64_C(1160784896), // SQRSHRNT_ZZI_H |
| UINT64_C(1163930624), // SQRSHRNT_ZZI_S |
| UINT64_C(1594399744), // SQRSHRNb |
| UINT64_C(1594924032), // SQRSHRNh |
| UINT64_C(1595972608), // SQRSHRNs |
| UINT64_C(1325964288), // SQRSHRNv16i8_shift |
| UINT64_C(253795328), // SQRSHRNv2i32_shift |
| UINT64_C(252746752), // SQRSHRNv4i16_shift |
| UINT64_C(1327537152), // SQRSHRNv4i32_shift |
| UINT64_C(1326488576), // SQRSHRNv8i16_shift |
| UINT64_C(252222464), // SQRSHRNv8i8_shift |
| UINT64_C(1160251392), // SQRSHRUNB_ZZI_B |
| UINT64_C(1160775680), // SQRSHRUNB_ZZI_H |
| UINT64_C(1163921408), // SQRSHRUNB_ZZI_S |
| UINT64_C(1160252416), // SQRSHRUNT_ZZI_B |
| UINT64_C(1160776704), // SQRSHRUNT_ZZI_H |
| UINT64_C(1163922432), // SQRSHRUNT_ZZI_S |
| UINT64_C(2131266560), // SQRSHRUNb |
| UINT64_C(2131790848), // SQRSHRUNh |
| UINT64_C(2132839424), // SQRSHRUNs |
| UINT64_C(1862831104), // SQRSHRUNv16i8_shift |
| UINT64_C(790662144), // SQRSHRUNv2i32_shift |
| UINT64_C(789613568), // SQRSHRUNv4i16_shift |
| UINT64_C(1864403968), // SQRSHRUNv4i32_shift |
| UINT64_C(1863355392), // SQRSHRUNv8i16_shift |
| UINT64_C(789089280), // SQRSHRUNv8i8_shift |
| UINT64_C(1141669888), // SQSHLR_ZPmZ_B |
| UINT64_C(1154252800), // SQSHLR_ZPmZ_D |
| UINT64_C(1145864192), // SQSHLR_ZPmZ_H |
| UINT64_C(1150058496), // SQSHLR_ZPmZ_S |
| UINT64_C(68124928), // SQSHLU_ZPmI_B |
| UINT64_C(76513280), // SQSHLU_ZPmI_D |
| UINT64_C(68125184), // SQSHLU_ZPmI_H |
| UINT64_C(72318976), // SQSHLU_ZPmI_S |
| UINT64_C(2131256320), // SQSHLUb |
| UINT64_C(2134926336), // SQSHLUd |
| UINT64_C(2131780608), // SQSHLUh |
| UINT64_C(2132829184), // SQSHLUs |
| UINT64_C(1862820864), // SQSHLUv16i8_shift |
| UINT64_C(790651904), // SQSHLUv2i32_shift |
| UINT64_C(1866490880), // SQSHLUv2i64_shift |
| UINT64_C(789603328), // SQSHLUv4i16_shift |
| UINT64_C(1864393728), // SQSHLUv4i32_shift |
| UINT64_C(1863345152), // SQSHLUv8i16_shift |
| UINT64_C(789079040), // SQSHLUv8i8_shift |
| UINT64_C(67535104), // SQSHL_ZPmI_B |
| UINT64_C(75923456), // SQSHL_ZPmI_D |
| UINT64_C(67535360), // SQSHL_ZPmI_H |
| UINT64_C(71729152), // SQSHL_ZPmI_S |
| UINT64_C(1141407744), // SQSHL_ZPmZ_B |
| UINT64_C(1153990656), // SQSHL_ZPmZ_D |
| UINT64_C(1145602048), // SQSHL_ZPmZ_H |
| UINT64_C(1149796352), // SQSHL_ZPmZ_S |
| UINT64_C(1594389504), // SQSHLb |
| UINT64_C(1598059520), // SQSHLd |
| UINT64_C(1594913792), // SQSHLh |
| UINT64_C(1595962368), // SQSHLs |
| UINT64_C(1310739456), // SQSHLv16i8 |
| UINT64_C(1325954048), // SQSHLv16i8_shift |
| UINT64_C(1583369216), // SQSHLv1i16 |
| UINT64_C(1587563520), // SQSHLv1i32 |
| UINT64_C(1591757824), // SQSHLv1i64 |
| UINT64_C(1579174912), // SQSHLv1i8 |
| UINT64_C(245386240), // SQSHLv2i32 |
| UINT64_C(253785088), // SQSHLv2i32_shift |
| UINT64_C(1323322368), // SQSHLv2i64 |
| UINT64_C(1329624064), // SQSHLv2i64_shift |
| UINT64_C(241191936), // SQSHLv4i16 |
| UINT64_C(252736512), // SQSHLv4i16_shift |
| UINT64_C(1319128064), // SQSHLv4i32 |
| UINT64_C(1327526912), // SQSHLv4i32_shift |
| UINT64_C(1314933760), // SQSHLv8i16 |
| UINT64_C(1326478336), // SQSHLv8i16_shift |
| UINT64_C(236997632), // SQSHLv8i8 |
| UINT64_C(252212224), // SQSHLv8i8_shift |
| UINT64_C(1160257536), // SQSHRNB_ZZI_B |
| UINT64_C(1160781824), // SQSHRNB_ZZI_H |
| UINT64_C(1163927552), // SQSHRNB_ZZI_S |
| UINT64_C(1160258560), // SQSHRNT_ZZI_B |
| UINT64_C(1160782848), // SQSHRNT_ZZI_H |
| UINT64_C(1163928576), // SQSHRNT_ZZI_S |
| UINT64_C(1594397696), // SQSHRNb |
| UINT64_C(1594921984), // SQSHRNh |
| UINT64_C(1595970560), // SQSHRNs |
| UINT64_C(1325962240), // SQSHRNv16i8_shift |
| UINT64_C(253793280), // SQSHRNv2i32_shift |
| UINT64_C(252744704), // SQSHRNv4i16_shift |
| UINT64_C(1327535104), // SQSHRNv4i32_shift |
| UINT64_C(1326486528), // SQSHRNv8i16_shift |
| UINT64_C(252220416), // SQSHRNv8i8_shift |
| UINT64_C(1160249344), // SQSHRUNB_ZZI_B |
| UINT64_C(1160773632), // SQSHRUNB_ZZI_H |
| UINT64_C(1163919360), // SQSHRUNB_ZZI_S |
| UINT64_C(1160250368), // SQSHRUNT_ZZI_B |
| UINT64_C(1160774656), // SQSHRUNT_ZZI_H |
| UINT64_C(1163920384), // SQSHRUNT_ZZI_S |
| UINT64_C(2131264512), // SQSHRUNb |
| UINT64_C(2131788800), // SQSHRUNh |
| UINT64_C(2132837376), // SQSHRUNs |
| UINT64_C(1862829056), // SQSHRUNv16i8_shift |
| UINT64_C(790660096), // SQSHRUNv2i32_shift |
| UINT64_C(789611520), // SQSHRUNv4i16_shift |
| UINT64_C(1864401920), // SQSHRUNv4i32_shift |
| UINT64_C(1863353344), // SQSHRUNv8i16_shift |
| UINT64_C(789087232), // SQSHRUNv8i8_shift |
| UINT64_C(1142849536), // SQSUBR_ZPmZ_B |
| UINT64_C(1155432448), // SQSUBR_ZPmZ_D |
| UINT64_C(1147043840), // SQSUBR_ZPmZ_H |
| UINT64_C(1151238144), // SQSUBR_ZPmZ_S |
| UINT64_C(623296512), // SQSUB_ZI_B |
| UINT64_C(635879424), // SQSUB_ZI_D |
| UINT64_C(627490816), // SQSUB_ZI_H |
| UINT64_C(631685120), // SQSUB_ZI_S |
| UINT64_C(1142587392), // SQSUB_ZPmZ_B |
| UINT64_C(1155170304), // SQSUB_ZPmZ_D |
| UINT64_C(1146781696), // SQSUB_ZPmZ_H |
| UINT64_C(1150976000), // SQSUB_ZPmZ_S |
| UINT64_C(69212160), // SQSUB_ZZZ_B |
| UINT64_C(81795072), // SQSUB_ZZZ_D |
| UINT64_C(73406464), // SQSUB_ZZZ_H |
| UINT64_C(77600768), // SQSUB_ZZZ_S |
| UINT64_C(1310731264), // SQSUBv16i8 |
| UINT64_C(1583361024), // SQSUBv1i16 |
| UINT64_C(1587555328), // SQSUBv1i32 |
| UINT64_C(1591749632), // SQSUBv1i64 |
| UINT64_C(1579166720), // SQSUBv1i8 |
| UINT64_C(245378048), // SQSUBv2i32 |
| UINT64_C(1323314176), // SQSUBv2i64 |
| UINT64_C(241183744), // SQSUBv4i16 |
| UINT64_C(1319119872), // SQSUBv4i32 |
| UINT64_C(1314925568), // SQSUBv8i16 |
| UINT64_C(236989440), // SQSUBv8i8 |
| UINT64_C(1160265728), // SQXTNB_ZZ_B |
| UINT64_C(1160790016), // SQXTNB_ZZ_H |
| UINT64_C(1163935744), // SQXTNB_ZZ_S |
| UINT64_C(1160266752), // SQXTNT_ZZ_B |
| UINT64_C(1160791040), // SQXTNT_ZZ_H |
| UINT64_C(1163936768), // SQXTNT_ZZ_S |
| UINT64_C(1310803968), // SQXTNv16i8 |
| UINT64_C(1583433728), // SQXTNv1i16 |
| UINT64_C(1587628032), // SQXTNv1i32 |
| UINT64_C(1579239424), // SQXTNv1i8 |
| UINT64_C(245450752), // SQXTNv2i32 |
| UINT64_C(241256448), // SQXTNv4i16 |
| UINT64_C(1319192576), // SQXTNv4i32 |
| UINT64_C(1314998272), // SQXTNv8i16 |
| UINT64_C(237062144), // SQXTNv8i8 |
| UINT64_C(1160269824), // SQXTUNB_ZZ_B |
| UINT64_C(1160794112), // SQXTUNB_ZZ_H |
| UINT64_C(1163939840), // SQXTUNB_ZZ_S |
| UINT64_C(1160270848), // SQXTUNT_ZZ_B |
| UINT64_C(1160795136), // SQXTUNT_ZZ_H |
| UINT64_C(1163940864), // SQXTUNT_ZZ_S |
| UINT64_C(1847666688), // SQXTUNv16i8 |
| UINT64_C(2120296448), // SQXTUNv1i16 |
| UINT64_C(2124490752), // SQXTUNv1i32 |
| UINT64_C(2116102144), // SQXTUNv1i8 |
| UINT64_C(782313472), // SQXTUNv2i32 |
| UINT64_C(778119168), // SQXTUNv4i16 |
| UINT64_C(1856055296), // SQXTUNv4i32 |
| UINT64_C(1851860992), // SQXTUNv8i16 |
| UINT64_C(773924864), // SQXTUNv8i8 |
| UINT64_C(1142194176), // SRHADD_ZPmZ_B |
| UINT64_C(1154777088), // SRHADD_ZPmZ_D |
| UINT64_C(1146388480), // SRHADD_ZPmZ_H |
| UINT64_C(1150582784), // SRHADD_ZPmZ_S |
| UINT64_C(1310725120), // SRHADDv16i8 |
| UINT64_C(245371904), // SRHADDv2i32 |
| UINT64_C(241177600), // SRHADDv4i16 |
| UINT64_C(1319113728), // SRHADDv4i32 |
| UINT64_C(1314919424), // SRHADDv8i16 |
| UINT64_C(236983296), // SRHADDv8i8 |
| UINT64_C(1158213632), // SRI_ZZI_B |
| UINT64_C(1166077952), // SRI_ZZI_D |
| UINT64_C(1158737920), // SRI_ZZI_H |
| UINT64_C(1161883648), // SRI_ZZI_S |
| UINT64_C(2134918144), // SRId |
| UINT64_C(1862812672), // SRIv16i8_shift |
| UINT64_C(790643712), // SRIv2i32_shift |
| UINT64_C(1866482688), // SRIv2i64_shift |
| UINT64_C(789595136), // SRIv4i16_shift |
| UINT64_C(1864385536), // SRIv4i32_shift |
| UINT64_C(1863336960), // SRIv8i16_shift |
| UINT64_C(789070848), // SRIv8i8_shift |
| UINT64_C(1141276672), // SRSHLR_ZPmZ_B |
| UINT64_C(1153859584), // SRSHLR_ZPmZ_D |
| UINT64_C(1145470976), // SRSHLR_ZPmZ_H |
| UINT64_C(1149665280), // SRSHLR_ZPmZ_S |
| UINT64_C(1141014528), // SRSHL_ZPmZ_B |
| UINT64_C(1153597440), // SRSHL_ZPmZ_D |
| UINT64_C(1145208832), // SRSHL_ZPmZ_H |
| UINT64_C(1149403136), // SRSHL_ZPmZ_S |
| UINT64_C(1310741504), // SRSHLv16i8 |
| UINT64_C(1591759872), // SRSHLv1i64 |
| UINT64_C(245388288), // SRSHLv2i32 |
| UINT64_C(1323324416), // SRSHLv2i64 |
| UINT64_C(241193984), // SRSHLv4i16 |
| UINT64_C(1319130112), // SRSHLv4i32 |
| UINT64_C(1314935808), // SRSHLv8i16 |
| UINT64_C(236999680), // SRSHLv8i8 |
| UINT64_C(67928320), // SRSHR_ZPmI_B |
| UINT64_C(76316672), // SRSHR_ZPmI_D |
| UINT64_C(67928576), // SRSHR_ZPmI_H |
| UINT64_C(72122368), // SRSHR_ZPmI_S |
| UINT64_C(1598039040), // SRSHRd |
| UINT64_C(1325933568), // SRSHRv16i8_shift |
| UINT64_C(253764608), // SRSHRv2i32_shift |
| UINT64_C(1329603584), // SRSHRv2i64_shift |
| UINT64_C(252716032), // SRSHRv4i16_shift |
| UINT64_C(1327506432), // SRSHRv4i32_shift |
| UINT64_C(1326457856), // SRSHRv8i16_shift |
| UINT64_C(252191744), // SRSHRv8i8_shift |
| UINT64_C(1158211584), // SRSRA_ZZI_B |
| UINT64_C(1166075904), // SRSRA_ZZI_D |
| UINT64_C(1158735872), // SRSRA_ZZI_H |
| UINT64_C(1161881600), // SRSRA_ZZI_S |
| UINT64_C(1598043136), // SRSRAd |
| UINT64_C(1325937664), // SRSRAv16i8_shift |
| UINT64_C(253768704), // SRSRAv2i32_shift |
| UINT64_C(1329607680), // SRSRAv2i64_shift |
| UINT64_C(252720128), // SRSRAv4i16_shift |
| UINT64_C(1327510528), // SRSRAv4i32_shift |
| UINT64_C(1326461952), // SRSRAv8i16_shift |
| UINT64_C(252195840), // SRSRAv8i8_shift |
| UINT64_C(1161863168), // SSHLLB_ZZI_D |
| UINT64_C(1158193152), // SSHLLB_ZZI_H |
| UINT64_C(1158717440), // SSHLLB_ZZI_S |
| UINT64_C(1161864192), // SSHLLT_ZZI_D |
| UINT64_C(1158194176), // SSHLLT_ZZI_H |
| UINT64_C(1158718464), // SSHLLT_ZZI_S |
| UINT64_C(1325966336), // SSHLLv16i8_shift |
| UINT64_C(253797376), // SSHLLv2i32_shift |
| UINT64_C(252748800), // SSHLLv4i16_shift |
| UINT64_C(1327539200), // SSHLLv4i32_shift |
| UINT64_C(1326490624), // SSHLLv8i16_shift |
| UINT64_C(252224512), // SSHLLv8i8_shift |
| UINT64_C(1310737408), // SSHLv16i8 |
| UINT64_C(1591755776), // SSHLv1i64 |
| UINT64_C(245384192), // SSHLv2i32 |
| UINT64_C(1323320320), // SSHLv2i64 |
| UINT64_C(241189888), // SSHLv4i16 |
| UINT64_C(1319126016), // SSHLv4i32 |
| UINT64_C(1314931712), // SSHLv8i16 |
| UINT64_C(236995584), // SSHLv8i8 |
| UINT64_C(1598030848), // SSHRd |
| UINT64_C(1325925376), // SSHRv16i8_shift |
| UINT64_C(253756416), // SSHRv2i32_shift |
| UINT64_C(1329595392), // SSHRv2i64_shift |
| UINT64_C(252707840), // SSHRv4i16_shift |
| UINT64_C(1327498240), // SSHRv4i32_shift |
| UINT64_C(1326449664), // SSHRv8i16_shift |
| UINT64_C(252183552), // SSHRv8i8_shift |
| UINT64_C(1158209536), // SSRA_ZZI_B |
| UINT64_C(1166073856), // SSRA_ZZI_D |
| UINT64_C(1158733824), // SSRA_ZZI_H |
| UINT64_C(1161879552), // SSRA_ZZI_S |
| UINT64_C(1598034944), // SSRAd |
| UINT64_C(1325929472), // SSRAv16i8_shift |
| UINT64_C(253760512), // SSRAv2i32_shift |
| UINT64_C(1329599488), // SSRAv2i64_shift |
| UINT64_C(252711936), // SSRAv4i16_shift |
| UINT64_C(1327502336), // SSRAv4i32_shift |
| UINT64_C(1326453760), // SSRAv8i16_shift |
| UINT64_C(252187648), // SSRAv8i8_shift |
| UINT64_C(3829440512), // SST1B_D_IMM |
| UINT64_C(3825246208), // SST1B_D_REAL |
| UINT64_C(3825254400), // SST1B_D_SXTW |
| UINT64_C(3825238016), // SST1B_D_UXTW |
| UINT64_C(3831537664), // SST1B_S_IMM |
| UINT64_C(3829448704), // SST1B_S_SXTW |
| UINT64_C(3829432320), // SST1B_S_UXTW |
| UINT64_C(3854606336), // SST1D_IMM |
| UINT64_C(3850412032), // SST1D_REAL |
| UINT64_C(3852509184), // SST1D_SCALED_SCALED_REAL |
| UINT64_C(3850420224), // SST1D_SXTW |
| UINT64_C(3852517376), // SST1D_SXTW_SCALED |
| UINT64_C(3850403840), // SST1D_UXTW |
| UINT64_C(3852500992), // SST1D_UXTW_SCALED |
| UINT64_C(3837829120), // SST1H_D_IMM |
| UINT64_C(3833634816), // SST1H_D_REAL |
| UINT64_C(3835731968), // SST1H_D_SCALED_SCALED_REAL |
| UINT64_C(3833643008), // SST1H_D_SXTW |
| UINT64_C(3835740160), // SST1H_D_SXTW_SCALED |
| UINT64_C(3833626624), // SST1H_D_UXTW |
| UINT64_C(3835723776), // SST1H_D_UXTW_SCALED |
| UINT64_C(3839926272), // SST1H_S_IMM |
| UINT64_C(3837837312), // SST1H_S_SXTW |
| UINT64_C(3839934464), // SST1H_S_SXTW_SCALED |
| UINT64_C(3837820928), // SST1H_S_UXTW |
| UINT64_C(3839918080), // SST1H_S_UXTW_SCALED |
| UINT64_C(3846217728), // SST1W_D_IMM |
| UINT64_C(3842023424), // SST1W_D_REAL |
| UINT64_C(3844120576), // SST1W_D_SCALED_SCALED_REAL |
| UINT64_C(3842031616), // SST1W_D_SXTW |
| UINT64_C(3844128768), // SST1W_D_SXTW_SCALED |
| UINT64_C(3842015232), // SST1W_D_UXTW |
| UINT64_C(3844112384), // SST1W_D_UXTW_SCALED |
| UINT64_C(3848314880), // SST1W_IMM |
| UINT64_C(3846225920), // SST1W_SXTW |
| UINT64_C(3848323072), // SST1W_SXTW_SCALED |
| UINT64_C(3846209536), // SST1W_UXTW |
| UINT64_C(3848306688), // SST1W_UXTW_SCALED |
| UINT64_C(1170245632), // SSUBLBT_ZZZ_D |
| UINT64_C(1161857024), // SSUBLBT_ZZZ_H |
| UINT64_C(1166051328), // SSUBLBT_ZZZ_S |
| UINT64_C(1170214912), // SSUBLB_ZZZ_D |
| UINT64_C(1161826304), // SSUBLB_ZZZ_H |
| UINT64_C(1166020608), // SSUBLB_ZZZ_S |
| UINT64_C(1170246656), // SSUBLTB_ZZZ_D |
| UINT64_C(1161858048), // SSUBLTB_ZZZ_H |
| UINT64_C(1166052352), // SSUBLTB_ZZZ_S |
| UINT64_C(1170215936), // SSUBLT_ZZZ_D |
| UINT64_C(1161827328), // SSUBLT_ZZZ_H |
| UINT64_C(1166021632), // SSUBLT_ZZZ_S |
| UINT64_C(1310728192), // SSUBLv16i8_v8i16 |
| UINT64_C(245374976), // SSUBLv2i32_v2i64 |
| UINT64_C(241180672), // SSUBLv4i16_v4i32 |
| UINT64_C(1319116800), // SSUBLv4i32_v2i64 |
| UINT64_C(1314922496), // SSUBLv8i16_v4i32 |
| UINT64_C(236986368), // SSUBLv8i8_v8i16 |
| UINT64_C(1170231296), // SSUBWB_ZZZ_D |
| UINT64_C(1161842688), // SSUBWB_ZZZ_H |
| UINT64_C(1166036992), // SSUBWB_ZZZ_S |
| UINT64_C(1170232320), // SSUBWT_ZZZ_D |
| UINT64_C(1161843712), // SSUBWT_ZZZ_H |
| UINT64_C(1166038016), // SSUBWT_ZZZ_S |
| UINT64_C(1310732288), // SSUBWv16i8_v8i16 |
| UINT64_C(245379072), // SSUBWv2i32_v2i64 |
| UINT64_C(241184768), // SSUBWv4i16_v4i32 |
| UINT64_C(1319120896), // SSUBWv4i32_v2i64 |
| UINT64_C(1314926592), // SSUBWv8i16_v4i32 |
| UINT64_C(236990464), // SSUBWv8i8_v8i16 |
| UINT64_C(3825221632), // ST1B |
| UINT64_C(3831513088), // ST1B_D |
| UINT64_C(3831554048), // ST1B_D_IMM |
| UINT64_C(3827318784), // ST1B_H |
| UINT64_C(3827359744), // ST1B_H_IMM |
| UINT64_C(3825262592), // ST1B_IMM |
| UINT64_C(3829415936), // ST1B_S |
| UINT64_C(3829456896), // ST1B_S_IMM |
| UINT64_C(3856678912), // ST1D |
| UINT64_C(3856719872), // ST1D_IMM |
| UINT64_C(1275076608), // ST1Fourv16b |
| UINT64_C(1283465216), // ST1Fourv16b_POST |
| UINT64_C(201337856), // ST1Fourv1d |
| UINT64_C(209726464), // ST1Fourv1d_POST |
| UINT64_C(1275079680), // ST1Fourv2d |
| UINT64_C(1283468288), // ST1Fourv2d_POST |
| UINT64_C(201336832), // ST1Fourv2s |
| UINT64_C(209725440), // ST1Fourv2s_POST |
| UINT64_C(201335808), // ST1Fourv4h |
| UINT64_C(209724416), // ST1Fourv4h_POST |
| UINT64_C(1275078656), // ST1Fourv4s |
| UINT64_C(1283467264), // ST1Fourv4s_POST |
| UINT64_C(201334784), // ST1Fourv8b |
| UINT64_C(209723392), // ST1Fourv8b_POST |
| UINT64_C(1275077632), // ST1Fourv8h |
| UINT64_C(1283466240), // ST1Fourv8h_POST |
| UINT64_C(3835707392), // ST1H |
| UINT64_C(3839901696), // ST1H_D |
| UINT64_C(3839942656), // ST1H_D_IMM |
| UINT64_C(3835748352), // ST1H_IMM |
| UINT64_C(3837804544), // ST1H_S |
| UINT64_C(3837845504), // ST1H_S_IMM |
| UINT64_C(1275097088), // ST1Onev16b |
| UINT64_C(1283485696), // ST1Onev16b_POST |
| UINT64_C(201358336), // ST1Onev1d |
| UINT64_C(209746944), // ST1Onev1d_POST |
| UINT64_C(1275100160), // ST1Onev2d |
| UINT64_C(1283488768), // ST1Onev2d_POST |
| UINT64_C(201357312), // ST1Onev2s |
| UINT64_C(209745920), // ST1Onev2s_POST |
| UINT64_C(201356288), // ST1Onev4h |
| UINT64_C(209744896), // ST1Onev4h_POST |
| UINT64_C(1275099136), // ST1Onev4s |
| UINT64_C(1283487744), // ST1Onev4s_POST |
| UINT64_C(201355264), // ST1Onev8b |
| UINT64_C(209743872), // ST1Onev8b_POST |
| UINT64_C(1275098112), // ST1Onev8h |
| UINT64_C(1283486720), // ST1Onev8h_POST |
| UINT64_C(1275092992), // ST1Threev16b |
| UINT64_C(1283481600), // ST1Threev16b_POST |
| UINT64_C(201354240), // ST1Threev1d |
| UINT64_C(209742848), // ST1Threev1d_POST |
| UINT64_C(1275096064), // ST1Threev2d |
| UINT64_C(1283484672), // ST1Threev2d_POST |
| UINT64_C(201353216), // ST1Threev2s |
| UINT64_C(209741824), // ST1Threev2s_POST |
| UINT64_C(201352192), // ST1Threev4h |
| UINT64_C(209740800), // ST1Threev4h_POST |
| UINT64_C(1275095040), // ST1Threev4s |
| UINT64_C(1283483648), // ST1Threev4s_POST |
| UINT64_C(201351168), // ST1Threev8b |
| UINT64_C(209739776), // ST1Threev8b_POST |
| UINT64_C(1275094016), // ST1Threev8h |
| UINT64_C(1283482624), // ST1Threev8h_POST |
| UINT64_C(1275109376), // ST1Twov16b |
| UINT64_C(1283497984), // ST1Twov16b_POST |
| UINT64_C(201370624), // ST1Twov1d |
| UINT64_C(209759232), // ST1Twov1d_POST |
| UINT64_C(1275112448), // ST1Twov2d |
| UINT64_C(1283501056), // ST1Twov2d_POST |
| UINT64_C(201369600), // ST1Twov2s |
| UINT64_C(209758208), // ST1Twov2s_POST |
| UINT64_C(201368576), // ST1Twov4h |
| UINT64_C(209757184), // ST1Twov4h_POST |
| UINT64_C(1275111424), // ST1Twov4s |
| UINT64_C(1283500032), // ST1Twov4s_POST |
| UINT64_C(201367552), // ST1Twov8b |
| UINT64_C(209756160), // ST1Twov8b_POST |
| UINT64_C(1275110400), // ST1Twov8h |
| UINT64_C(1283499008), // ST1Twov8h_POST |
| UINT64_C(3846193152), // ST1W |
| UINT64_C(3848290304), // ST1W_D |
| UINT64_C(3848331264), // ST1W_D_IMM |
| UINT64_C(3846234112), // ST1W_IMM |
| UINT64_C(218120192), // ST1i16 |
| UINT64_C(226508800), // ST1i16_POST |
| UINT64_C(218136576), // ST1i32 |
| UINT64_C(226525184), // ST1i32_POST |
| UINT64_C(218137600), // ST1i64 |
| UINT64_C(226526208), // ST1i64_POST |
| UINT64_C(218103808), // ST1i8 |
| UINT64_C(226492416), // ST1i8_POST |
| UINT64_C(3827326976), // ST2B |
| UINT64_C(3828408320), // ST2B_IMM |
| UINT64_C(3852492800), // ST2D |
| UINT64_C(3853574144), // ST2D_IMM |
| UINT64_C(3651143680), // ST2GOffset |
| UINT64_C(3651142656), // ST2GPostIndex |
| UINT64_C(3651144704), // ST2GPreIndex |
| UINT64_C(3835715584), // ST2H |
| UINT64_C(3836796928), // ST2H_IMM |
| UINT64_C(1275101184), // ST2Twov16b |
| UINT64_C(1283489792), // ST2Twov16b_POST |
| UINT64_C(1275104256), // ST2Twov2d |
| UINT64_C(1283492864), // ST2Twov2d_POST |
| UINT64_C(201361408), // ST2Twov2s |
| UINT64_C(209750016), // ST2Twov2s_POST |
| UINT64_C(201360384), // ST2Twov4h |
| UINT64_C(209748992), // ST2Twov4h_POST |
| UINT64_C(1275103232), // ST2Twov4s |
| UINT64_C(1283491840), // ST2Twov4s_POST |
| UINT64_C(201359360), // ST2Twov8b |
| UINT64_C(209747968), // ST2Twov8b_POST |
| UINT64_C(1275102208), // ST2Twov8h |
| UINT64_C(1283490816), // ST2Twov8h_POST |
| UINT64_C(3844104192), // ST2W |
| UINT64_C(3845185536), // ST2W_IMM |
| UINT64_C(220217344), // ST2i16 |
| UINT64_C(228605952), // ST2i16_POST |
| UINT64_C(220233728), // ST2i32 |
| UINT64_C(228622336), // ST2i32_POST |
| UINT64_C(220234752), // ST2i64 |
| UINT64_C(228623360), // ST2i64_POST |
| UINT64_C(220200960), // ST2i8 |
| UINT64_C(228589568), // ST2i8_POST |
| UINT64_C(3829424128), // ST3B |
| UINT64_C(3830505472), // ST3B_IMM |
| UINT64_C(3854589952), // ST3D |
| UINT64_C(3855671296), // ST3D_IMM |
| UINT64_C(3837812736), // ST3H |
| UINT64_C(3838894080), // ST3H_IMM |
| UINT64_C(1275084800), // ST3Threev16b |
| UINT64_C(1283473408), // ST3Threev16b_POST |
| UINT64_C(1275087872), // ST3Threev2d |
| UINT64_C(1283476480), // ST3Threev2d_POST |
| UINT64_C(201345024), // ST3Threev2s |
| UINT64_C(209733632), // ST3Threev2s_POST |
| UINT64_C(201344000), // ST3Threev4h |
| UINT64_C(209732608), // ST3Threev4h_POST |
| UINT64_C(1275086848), // ST3Threev4s |
| UINT64_C(1283475456), // ST3Threev4s_POST |
| UINT64_C(201342976), // ST3Threev8b |
| UINT64_C(209731584), // ST3Threev8b_POST |
| UINT64_C(1275085824), // ST3Threev8h |
| UINT64_C(1283474432), // ST3Threev8h_POST |
| UINT64_C(3846201344), // ST3W |
| UINT64_C(3847282688), // ST3W_IMM |
| UINT64_C(218128384), // ST3i16 |
| UINT64_C(226516992), // ST3i16_POST |
| UINT64_C(218144768), // ST3i32 |
| UINT64_C(226533376), // ST3i32_POST |
| UINT64_C(218145792), // ST3i64 |
| UINT64_C(226534400), // ST3i64_POST |
| UINT64_C(218112000), // ST3i8 |
| UINT64_C(226500608), // ST3i8_POST |
| UINT64_C(3831521280), // ST4B |
| UINT64_C(3832602624), // ST4B_IMM |
| UINT64_C(3856687104), // ST4D |
| UINT64_C(3857768448), // ST4D_IMM |
| UINT64_C(1275068416), // ST4Fourv16b |
| UINT64_C(1283457024), // ST4Fourv16b_POST |
| UINT64_C(1275071488), // ST4Fourv2d |
| UINT64_C(1283460096), // ST4Fourv2d_POST |
| UINT64_C(201328640), // ST4Fourv2s |
| UINT64_C(209717248), // ST4Fourv2s_POST |
| UINT64_C(201327616), // ST4Fourv4h |
| UINT64_C(209716224), // ST4Fourv4h_POST |
| UINT64_C(1275070464), // ST4Fourv4s |
| UINT64_C(1283459072), // ST4Fourv4s_POST |
| UINT64_C(201326592), // ST4Fourv8b |
| UINT64_C(209715200), // ST4Fourv8b_POST |
| UINT64_C(1275069440), // ST4Fourv8h |
| UINT64_C(1283458048), // ST4Fourv8h_POST |
| UINT64_C(3839909888), // ST4H |
| UINT64_C(3840991232), // ST4H_IMM |
| UINT64_C(3848298496), // ST4W |
| UINT64_C(3849379840), // ST4W_IMM |
| UINT64_C(220225536), // ST4i16 |
| UINT64_C(228614144), // ST4i16_POST |
| UINT64_C(220241920), // ST4i32 |
| UINT64_C(228630528), // ST4i32_POST |
| UINT64_C(220242944), // ST4i64 |
| UINT64_C(228631552), // ST4i64_POST |
| UINT64_C(220209152), // ST4i8 |
| UINT64_C(228597760), // ST4i8_POST |
| UINT64_C(3651141632), // STGM |
| UINT64_C(3642755072), // STGOffset |
| UINT64_C(1761607680), // STGPi |
| UINT64_C(3642754048), // STGPostIndex |
| UINT64_C(1753219072), // STGPpost |
| UINT64_C(1769996288), // STGPpre |
| UINT64_C(3642756096), // STGPreIndex |
| UINT64_C(0), // STGloop |
| UINT64_C(144669696), // STLLRB |
| UINT64_C(1218411520), // STLLRH |
| UINT64_C(2292153344), // STLLRW |
| UINT64_C(3365895168), // STLLRX |
| UINT64_C(144702464), // STLRB |
| UINT64_C(1218444288), // STLRH |
| UINT64_C(2292186112), // STLRW |
| UINT64_C(3365927936), // STLRX |
| UINT64_C(419430400), // STLURBi |
| UINT64_C(1493172224), // STLURHi |
| UINT64_C(2566914048), // STLURWi |
| UINT64_C(3640655872), // STLURXi |
| UINT64_C(2283831296), // STLXPW |
| UINT64_C(3357573120), // STLXPX |
| UINT64_C(134250496), // STLXRB |
| UINT64_C(1207992320), // STLXRH |
| UINT64_C(2281734144), // STLXRW |
| UINT64_C(3355475968), // STLXRX |
| UINT64_C(1811939328), // STNPDi |
| UINT64_C(2885681152), // STNPQi |
| UINT64_C(738197504), // STNPSi |
| UINT64_C(671088640), // STNPWi |
| UINT64_C(2818572288), // STNPXi |
| UINT64_C(3826311168), // STNT1B_ZRI |
| UINT64_C(3825229824), // STNT1B_ZRR |
| UINT64_C(3825213440), // STNT1B_ZZR_D_REAL |
| UINT64_C(3829407744), // STNT1B_ZZR_S_REAL |
| UINT64_C(3851476992), // STNT1D_ZRI |
| UINT64_C(3850395648), // STNT1D_ZRR |
| UINT64_C(3850379264), // STNT1D_ZZR_D_REAL |
| UINT64_C(3834699776), // STNT1H_ZRI |
| UINT64_C(3833618432), // STNT1H_ZRR |
| UINT64_C(3833602048), // STNT1H_ZZR_D_REAL |
| UINT64_C(3837796352), // STNT1H_ZZR_S_REAL |
| UINT64_C(3843088384), // STNT1W_ZRI |
| UINT64_C(3842007040), // STNT1W_ZRR |
| UINT64_C(3841990656), // STNT1W_ZZR_D_REAL |
| UINT64_C(3846184960), // STNT1W_ZZR_S_REAL |
| UINT64_C(1828716544), // STPDi |
| UINT64_C(1820327936), // STPDpost |
| UINT64_C(1837105152), // STPDpre |
| UINT64_C(2902458368), // STPQi |
| UINT64_C(2894069760), // STPQpost |
| UINT64_C(2910846976), // STPQpre |
| UINT64_C(754974720), // STPSi |
| UINT64_C(746586112), // STPSpost |
| UINT64_C(763363328), // STPSpre |
| UINT64_C(687865856), // STPWi |
| UINT64_C(679477248), // STPWpost |
| UINT64_C(696254464), // STPWpre |
| UINT64_C(2835349504), // STPXi |
| UINT64_C(2826960896), // STPXpost |
| UINT64_C(2843738112), // STPXpre |
| UINT64_C(939525120), // STRBBpost |
| UINT64_C(939527168), // STRBBpre |
| UINT64_C(941639680), // STRBBroW |
| UINT64_C(941647872), // STRBBroX |
| UINT64_C(956301312), // STRBBui |
| UINT64_C(1006633984), // STRBpost |
| UINT64_C(1006636032), // STRBpre |
| UINT64_C(1008748544), // STRBroW |
| UINT64_C(1008756736), // STRBroX |
| UINT64_C(1023410176), // STRBui |
| UINT64_C(4227859456), // STRDpost |
| UINT64_C(4227861504), // STRDpre |
| UINT64_C(4229974016), // STRDroW |
| UINT64_C(4229982208), // STRDroX |
| UINT64_C(4244635648), // STRDui |
| UINT64_C(2013266944), // STRHHpost |
| UINT64_C(2013268992), // STRHHpre |
| UINT64_C(2015381504), // STRHHroW |
| UINT64_C(2015389696), // STRHHroX |
| UINT64_C(2030043136), // STRHHui |
| UINT64_C(2080375808), // STRHpost |
| UINT64_C(2080377856), // STRHpre |
| UINT64_C(2082490368), // STRHroW |
| UINT64_C(2082498560), // STRHroX |
| UINT64_C(2097152000), // STRHui |
| UINT64_C(1015022592), // STRQpost |
| UINT64_C(1015024640), // STRQpre |
| UINT64_C(1017137152), // STRQroW |
| UINT64_C(1017145344), // STRQroX |
| UINT64_C(1031798784), // STRQui |
| UINT64_C(3154117632), // STRSpost |
| UINT64_C(3154119680), // STRSpre |
| UINT64_C(3156232192), // STRSroW |
| UINT64_C(3156240384), // STRSroX |
| UINT64_C(3170893824), // STRSui |
| UINT64_C(3087008768), // STRWpost |
| UINT64_C(3087010816), // STRWpre |
| UINT64_C(3089123328), // STRWroW |
| UINT64_C(3089131520), // STRWroX |
| UINT64_C(3103784960), // STRWui |
| UINT64_C(4160750592), // STRXpost |
| UINT64_C(4160752640), // STRXpre |
| UINT64_C(4162865152), // STRXroW |
| UINT64_C(4162873344), // STRXroX |
| UINT64_C(4177526784), // STRXui |
| UINT64_C(3850371072), // STR_PXI |
| UINT64_C(3850387456), // STR_ZXI |
| UINT64_C(939526144), // STTRBi |
| UINT64_C(2013267968), // STTRHi |
| UINT64_C(3087009792), // STTRWi |
| UINT64_C(4160751616), // STTRXi |
| UINT64_C(939524096), // STURBBi |
| UINT64_C(1006632960), // STURBi |
| UINT64_C(4227858432), // STURDi |
| UINT64_C(2013265920), // STURHHi |
| UINT64_C(2080374784), // STURHi |
| UINT64_C(1015021568), // STURQi |
| UINT64_C(3154116608), // STURSi |
| UINT64_C(3087007744), // STURWi |
| UINT64_C(4160749568), // STURXi |
| UINT64_C(2283798528), // STXPW |
| UINT64_C(3357540352), // STXPX |
| UINT64_C(134217728), // STXRB |
| UINT64_C(1207959552), // STXRH |
| UINT64_C(2281701376), // STXRW |
| UINT64_C(3355443200), // STXRX |
| UINT64_C(3655337984), // STZ2GOffset |
| UINT64_C(3655336960), // STZ2GPostIndex |
| UINT64_C(3655339008), // STZ2GPreIndex |
| UINT64_C(3642753024), // STZGM |
| UINT64_C(3646949376), // STZGOffset |
| UINT64_C(3646948352), // STZGPostIndex |
| UINT64_C(3646950400), // STZGPreIndex |
| UINT64_C(0), // STZGloop |
| UINT64_C(3514826752), // SUBG |
| UINT64_C(1163948032), // SUBHNB_ZZZ_B |
| UINT64_C(1168142336), // SUBHNB_ZZZ_H |
| UINT64_C(1172336640), // SUBHNB_ZZZ_S |
| UINT64_C(1163949056), // SUBHNT_ZZZ_B |
| UINT64_C(1168143360), // SUBHNT_ZZZ_H |
| UINT64_C(1172337664), // SUBHNT_ZZZ_S |
| UINT64_C(245391360), // SUBHNv2i64_v2i32 |
| UINT64_C(1319133184), // SUBHNv2i64_v4i32 |
| UINT64_C(241197056), // SUBHNv4i32_v4i16 |
| UINT64_C(1314938880), // SUBHNv4i32_v8i16 |
| UINT64_C(1310744576), // SUBHNv8i16_v16i8 |
| UINT64_C(237002752), // SUBHNv8i16_v8i8 |
| UINT64_C(2596274176), // SUBP |
| UINT64_C(3133145088), // SUBPS |
| UINT64_C(623099904), // SUBR_ZI_B |
| UINT64_C(635682816), // SUBR_ZI_D |
| UINT64_C(627294208), // SUBR_ZI_H |
| UINT64_C(631488512), // SUBR_ZI_S |
| UINT64_C(67305472), // SUBR_ZPmZ_B |
| UINT64_C(79888384), // SUBR_ZPmZ_D |
| UINT64_C(71499776), // SUBR_ZPmZ_H |
| UINT64_C(75694080), // SUBR_ZPmZ_S |
| UINT64_C(1895825408), // SUBSWri |
| UINT64_C(0), // SUBSWrr |
| UINT64_C(1795162112), // SUBSWrs |
| UINT64_C(1797259264), // SUBSWrx |
| UINT64_C(4043309056), // SUBSXri |
| UINT64_C(0), // SUBSXrr |
| UINT64_C(3942645760), // SUBSXrs |
| UINT64_C(3944742912), // SUBSXrx |
| UINT64_C(3944767488), // SUBSXrx64 |
| UINT64_C(1358954496), // SUBWri |
| UINT64_C(0), // SUBWrr |
| UINT64_C(1258291200), // SUBWrs |
| UINT64_C(1260388352), // SUBWrx |
| UINT64_C(3506438144), // SUBXri |
| UINT64_C(0), // SUBXrr |
| UINT64_C(3405774848), // SUBXrs |
| UINT64_C(3407872000), // SUBXrx |
| UINT64_C(3407896576), // SUBXrx64 |
| UINT64_C(622968832), // SUB_ZI_B |
| UINT64_C(635551744), // SUB_ZI_D |
| UINT64_C(627163136), // SUB_ZI_H |
| UINT64_C(631357440), // SUB_ZI_S |
| UINT64_C(67174400), // SUB_ZPmZ_B |
| UINT64_C(79757312), // SUB_ZPmZ_D |
| UINT64_C(71368704), // SUB_ZPmZ_H |
| UINT64_C(75563008), // SUB_ZPmZ_S |
| UINT64_C(69207040), // SUB_ZZZ_B |
| UINT64_C(81789952), // SUB_ZZZ_D |
| UINT64_C(73401344), // SUB_ZZZ_H |
| UINT64_C(77595648), // SUB_ZZZ_S |
| UINT64_C(1847624704), // SUBv16i8 |
| UINT64_C(2128643072), // SUBv1i64 |
| UINT64_C(782271488), // SUBv2i32 |
| UINT64_C(1860207616), // SUBv2i64 |
| UINT64_C(778077184), // SUBv4i16 |
| UINT64_C(1856013312), // SUBv4i32 |
| UINT64_C(1851819008), // SUBv8i16 |
| UINT64_C(773882880), // SUBv8i8 |
| UINT64_C(99694592), // SUNPKHI_ZZ_D |
| UINT64_C(91305984), // SUNPKHI_ZZ_H |
| UINT64_C(95500288), // SUNPKHI_ZZ_S |
| UINT64_C(99629056), // SUNPKLO_ZZ_D |
| UINT64_C(91240448), // SUNPKLO_ZZ_H |
| UINT64_C(95434752), // SUNPKLO_ZZ_S |
| UINT64_C(1142718464), // SUQADD_ZPmZ_B |
| UINT64_C(1155301376), // SUQADD_ZPmZ_D |
| UINT64_C(1146912768), // SUQADD_ZPmZ_H |
| UINT64_C(1151107072), // SUQADD_ZPmZ_S |
| UINT64_C(1310734336), // SUQADDv16i8 |
| UINT64_C(1583364096), // SUQADDv1i16 |
| UINT64_C(1587558400), // SUQADDv1i32 |
| UINT64_C(1591752704), // SUQADDv1i64 |
| UINT64_C(1579169792), // SUQADDv1i8 |
| UINT64_C(245381120), // SUQADDv2i32 |
| UINT64_C(1323317248), // SUQADDv2i64 |
| UINT64_C(241186816), // SUQADDv4i16 |
| UINT64_C(1319122944), // SUQADDv4i32 |
| UINT64_C(1314928640), // SUQADDv8i16 |
| UINT64_C(236992512), // SUQADDv8i8 |
| UINT64_C(3556769793), // SVC |
| UINT64_C(950042624), // SWPAB |
| UINT64_C(2023784448), // SWPAH |
| UINT64_C(954236928), // SWPALB |
| UINT64_C(2027978752), // SWPALH |
| UINT64_C(3101720576), // SWPALW |
| UINT64_C(4175462400), // SWPALX |
| UINT64_C(3097526272), // SWPAW |
| UINT64_C(4171268096), // SWPAX |
| UINT64_C(941654016), // SWPB |
| UINT64_C(2015395840), // SWPH |
| UINT64_C(945848320), // SWPLB |
| UINT64_C(2019590144), // SWPLH |
| UINT64_C(3093331968), // SWPLW |
| UINT64_C(4167073792), // SWPLX |
| UINT64_C(3089137664), // SWPW |
| UINT64_C(4162879488), // SWPX |
| UINT64_C(80781312), // SXTB_ZPmZ_D |
| UINT64_C(72392704), // SXTB_ZPmZ_H |
| UINT64_C(76587008), // SXTB_ZPmZ_S |
| UINT64_C(80912384), // SXTH_ZPmZ_D |
| UINT64_C(76718080), // SXTH_ZPmZ_S |
| UINT64_C(81043456), // SXTW_ZPmZ_D |
| UINT64_C(3576168448), // SYSLxt |
| UINT64_C(3574071296), // SYSxt |
| UINT64_C(0), // SpeculationSafeValueW |
| UINT64_C(0), // SpeculationSafeValueX |
| UINT64_C(0), // TAGPstack |
| UINT64_C(85993472), // TBL_ZZZZ_B |
| UINT64_C(98576384), // TBL_ZZZZ_D |
| UINT64_C(90187776), // TBL_ZZZZ_H |
| UINT64_C(94382080), // TBL_ZZZZ_S |
| UINT64_C(85995520), // TBL_ZZZ_B |
| UINT64_C(98578432), // TBL_ZZZ_D |
| UINT64_C(90189824), // TBL_ZZZ_H |
| UINT64_C(94384128), // TBL_ZZZ_S |
| UINT64_C(1308647424), // TBLv16i8Four |
| UINT64_C(1308622848), // TBLv16i8One |
| UINT64_C(1308639232), // TBLv16i8Three |
| UINT64_C(1308631040), // TBLv16i8Two |
| UINT64_C(234905600), // TBLv8i8Four |
| UINT64_C(234881024), // TBLv8i8One |
| UINT64_C(234897408), // TBLv8i8Three |
| UINT64_C(234889216), // TBLv8i8Two |
| UINT64_C(922746880), // TBNZW |
| UINT64_C(3070230528), // TBNZX |
| UINT64_C(85994496), // TBX_ZZZ_B |
| UINT64_C(98577408), // TBX_ZZZ_D |
| UINT64_C(90188800), // TBX_ZZZ_H |
| UINT64_C(94383104), // TBX_ZZZ_S |
| UINT64_C(1308651520), // TBXv16i8Four |
| UINT64_C(1308626944), // TBXv16i8One |
| UINT64_C(1308643328), // TBXv16i8Three |
| UINT64_C(1308635136), // TBXv16i8Two |
| UINT64_C(234909696), // TBXv8i8Four |
| UINT64_C(234885120), // TBXv8i8One |
| UINT64_C(234901504), // TBXv8i8Three |
| UINT64_C(234893312), // TBXv8i8Two |
| UINT64_C(905969664), // TBZW |
| UINT64_C(3053453312), // TBZX |
| UINT64_C(3563061248), // TCANCEL |
| UINT64_C(3573756031), // TCOMMIT |
| UINT64_C(0), // TCRETURNdi |
| UINT64_C(0), // TCRETURNri |
| UINT64_C(0), // TCRETURNriALL |
| UINT64_C(0), // TCRETURNriBTI |
| UINT64_C(0), // TLSDESCCALL |
| UINT64_C(0), // TLSDESC_CALLSEQ |
| UINT64_C(86003712), // TRN1_PPP_B |
| UINT64_C(98586624), // TRN1_PPP_D |
| UINT64_C(90198016), // TRN1_PPP_H |
| UINT64_C(94392320), // TRN1_PPP_S |
| UINT64_C(86011904), // TRN1_ZZZ_B |
| UINT64_C(98594816), // TRN1_ZZZ_D |
| UINT64_C(90206208), // TRN1_ZZZ_H |
| UINT64_C(94400512), // TRN1_ZZZ_S |
| UINT64_C(1308633088), // TRN1v16i8 |
| UINT64_C(243279872), // TRN1v2i32 |
| UINT64_C(1321216000), // TRN1v2i64 |
| UINT64_C(239085568), // TRN1v4i16 |
| UINT64_C(1317021696), // TRN1v4i32 |
| UINT64_C(1312827392), // TRN1v8i16 |
| UINT64_C(234891264), // TRN1v8i8 |
| UINT64_C(86004736), // TRN2_PPP_B |
| UINT64_C(98587648), // TRN2_PPP_D |
| UINT64_C(90199040), // TRN2_PPP_H |
| UINT64_C(94393344), // TRN2_PPP_S |
| UINT64_C(86012928), // TRN2_ZZZ_B |
| UINT64_C(98595840), // TRN2_ZZZ_D |
| UINT64_C(90207232), // TRN2_ZZZ_H |
| UINT64_C(94401536), // TRN2_ZZZ_S |
| UINT64_C(1308649472), // TRN2v16i8 |
| UINT64_C(243296256), // TRN2v2i32 |
| UINT64_C(1321232384), // TRN2v2i64 |
| UINT64_C(239101952), // TRN2v4i16 |
| UINT64_C(1317038080), // TRN2v4i32 |
| UINT64_C(1312843776), // TRN2v8i16 |
| UINT64_C(234907648), // TRN2v8i8 |
| UINT64_C(3573752415), // TSB |
| UINT64_C(3575853152), // TSTART |
| UINT64_C(3575853408), // TTEST |
| UINT64_C(1170262016), // UABALB_ZZZ_D |
| UINT64_C(1161873408), // UABALB_ZZZ_H |
| UINT64_C(1166067712), // UABALB_ZZZ_S |
| UINT64_C(1170263040), // UABALT_ZZZ_D |
| UINT64_C(1161874432), // UABALT_ZZZ_H |
| UINT64_C(1166068736), // UABALT_ZZZ_S |
| UINT64_C(1847611392), // UABALv16i8_v8i16 |
| UINT64_C(782258176), // UABALv2i32_v2i64 |
| UINT64_C(778063872), // UABALv4i16_v4i32 |
| UINT64_C(1856000000), // UABALv4i32_v2i64 |
| UINT64_C(1851805696), // UABALv8i16_v4i32 |
| UINT64_C(773869568), // UABALv8i8_v8i16 |
| UINT64_C(1157692416), // UABA_ZZZ_B |
| UINT64_C(1170275328), // UABA_ZZZ_D |
| UINT64_C(1161886720), // UABA_ZZZ_H |
| UINT64_C(1166081024), // UABA_ZZZ_S |
| UINT64_C(1847622656), // UABAv16i8 |
| UINT64_C(782269440), // UABAv2i32 |
| UINT64_C(778075136), // UABAv4i16 |
| UINT64_C(1856011264), // UABAv4i32 |
| UINT64_C(1851816960), // UABAv8i16 |
| UINT64_C(773880832), // UABAv8i8 |
| UINT64_C(1170225152), // UABDLB_ZZZ_D |
| UINT64_C(1161836544), // UABDLB_ZZZ_H |
| UINT64_C(1166030848), // UABDLB_ZZZ_S |
| UINT64_C(1170226176), // UABDLT_ZZZ_D |
| UINT64_C(1161837568), // UABDLT_ZZZ_H |
| UINT64_C(1166031872), // UABDLT_ZZZ_S |
| UINT64_C(1847619584), // UABDLv16i8_v8i16 |
| UINT64_C(782266368), // UABDLv2i32_v2i64 |
| UINT64_C(778072064), // UABDLv4i16_v4i32 |
| UINT64_C(1856008192), // UABDLv4i32_v2i64 |
| UINT64_C(1851813888), // UABDLv8i16_v4i32 |
| UINT64_C(773877760), // UABDLv8i8_v8i16 |
| UINT64_C(67960832), // UABD_ZPmZ_B |
| UINT64_C(80543744), // UABD_ZPmZ_D |
| UINT64_C(72155136), // UABD_ZPmZ_H |
| UINT64_C(76349440), // UABD_ZPmZ_S |
| UINT64_C(1847620608), // UABDv16i8 |
| UINT64_C(782267392), // UABDv2i32 |
| UINT64_C(778073088), // UABDv4i16 |
| UINT64_C(1856009216), // UABDv4i32 |
| UINT64_C(1851814912), // UABDv8i16 |
| UINT64_C(773878784), // UABDv8i8 |
| UINT64_C(1153802240), // UADALP_ZPmZ_D |
| UINT64_C(1145413632), // UADALP_ZPmZ_H |
| UINT64_C(1149607936), // UADALP_ZPmZ_S |
| UINT64_C(1847617536), // UADALPv16i8_v8i16 |
| UINT64_C(782264320), // UADALPv2i32_v1i64 |
| UINT64_C(778070016), // UADALPv4i16_v2i32 |
| UINT64_C(1856006144), // UADALPv4i32_v2i64 |
| UINT64_C(1851811840), // UADALPv8i16_v4i32 |
| UINT64_C(773875712), // UADALPv8i8_v4i16 |
| UINT64_C(1170212864), // UADDLB_ZZZ_D |
| UINT64_C(1161824256), // UADDLB_ZZZ_H |
| UINT64_C(1166018560), // UADDLB_ZZZ_S |
| UINT64_C(1847601152), // UADDLPv16i8_v8i16 |
| UINT64_C(782247936), // UADDLPv2i32_v1i64 |
| UINT64_C(778053632), // UADDLPv4i16_v2i32 |
| UINT64_C(1855989760), // UADDLPv4i32_v2i64 |
| UINT64_C(1851795456), // UADDLPv8i16_v4i32 |
| UINT64_C(773859328), // UADDLPv8i8_v4i16 |
| UINT64_C(1170213888), // UADDLT_ZZZ_D |
| UINT64_C(1161825280), // UADDLT_ZZZ_H |
| UINT64_C(1166019584), // UADDLT_ZZZ_S |
| UINT64_C(1848653824), // UADDLVv16i8v |
| UINT64_C(779106304), // UADDLVv4i16v |
| UINT64_C(1857042432), // UADDLVv4i32v |
| UINT64_C(1852848128), // UADDLVv8i16v |
| UINT64_C(774912000), // UADDLVv8i8v |
| UINT64_C(1847590912), // UADDLv16i8_v8i16 |
| UINT64_C(782237696), // UADDLv2i32_v2i64 |
| UINT64_C(778043392), // UADDLv4i16_v4i32 |
| UINT64_C(1855979520), // UADDLv4i32_v2i64 |
| UINT64_C(1851785216), // UADDLv8i16_v4i32 |
| UINT64_C(773849088), // UADDLv8i8_v8i16 |
| UINT64_C(67182592), // UADDV_VPZ_B |
| UINT64_C(79765504), // UADDV_VPZ_D |
| UINT64_C(71376896), // UADDV_VPZ_H |
| UINT64_C(75571200), // UADDV_VPZ_S |
| UINT64_C(1170229248), // UADDWB_ZZZ_D |
| UINT64_C(1161840640), // UADDWB_ZZZ_H |
| UINT64_C(1166034944), // UADDWB_ZZZ_S |
| UINT64_C(1170230272), // UADDWT_ZZZ_D |
| UINT64_C(1161841664), // UADDWT_ZZZ_H |
| UINT64_C(1166035968), // UADDWT_ZZZ_S |
| UINT64_C(1847595008), // UADDWv16i8_v8i16 |
| UINT64_C(782241792), // UADDWv2i32_v2i64 |
| UINT64_C(778047488), // UADDWv4i16_v4i32 |
| UINT64_C(1855983616), // UADDWv4i32_v2i64 |
| UINT64_C(1851789312), // UADDWv8i16_v4i32 |
| UINT64_C(773853184), // UADDWv8i8_v8i16 |
| UINT64_C(1392508928), // UBFMWri |
| UINT64_C(3544186880), // UBFMXri |
| UINT64_C(507740160), // UCVTFSWDri |
| UINT64_C(516128768), // UCVTFSWHri |
| UINT64_C(503545856), // UCVTFSWSri |
| UINT64_C(2655191040), // UCVTFSXDri |
| UINT64_C(2663579648), // UCVTFSXHri |
| UINT64_C(2650996736), // UCVTFSXSri |
| UINT64_C(509804544), // UCVTFUWDri |
| UINT64_C(518193152), // UCVTFUWHri |
| UINT64_C(505610240), // UCVTFUWSri |
| UINT64_C(2657288192), // UCVTFUXDri |
| UINT64_C(2665676800), // UCVTFUXHri |
| UINT64_C(2653093888), // UCVTFUXSri |
| UINT64_C(1708630016), // UCVTF_ZPmZ_DtoD |
| UINT64_C(1700241408), // UCVTF_ZPmZ_DtoH |
| UINT64_C(1708498944), // UCVTF_ZPmZ_DtoS |
| UINT64_C(1699979264), // UCVTF_ZPmZ_HtoH |
| UINT64_C(1708236800), // UCVTF_ZPmZ_StoD |
| UINT64_C(1700110336), // UCVTF_ZPmZ_StoH |
| UINT64_C(1704304640), // UCVTF_ZPmZ_StoS |
| UINT64_C(2134959104), // UCVTFd |
| UINT64_C(2131813376), // UCVTFh |
| UINT64_C(2132861952), // UCVTFs |
| UINT64_C(2121914368), // UCVTFv1i16 |
| UINT64_C(2116147200), // UCVTFv1i32 |
| UINT64_C(2120341504), // UCVTFv1i64 |
| UINT64_C(773969920), // UCVTFv2f32 |
| UINT64_C(1851906048), // UCVTFv2f64 |
| UINT64_C(790684672), // UCVTFv2i32_shift |
| UINT64_C(1866523648), // UCVTFv2i64_shift |
| UINT64_C(779737088), // UCVTFv4f16 |
| UINT64_C(1847711744), // UCVTFv4f32 |
| UINT64_C(789636096), // UCVTFv4i16_shift |
| UINT64_C(1864426496), // UCVTFv4i32_shift |
| UINT64_C(1853478912), // UCVTFv8f16 |
| UINT64_C(1863377920), // UCVTFv8i16_shift |
| UINT64_C(0), // UDF |
| UINT64_C(81199104), // UDIVR_ZPmZ_D |
| UINT64_C(77004800), // UDIVR_ZPmZ_S |
| UINT64_C(448792576), // UDIVWr |
| UINT64_C(2596276224), // UDIVXr |
| UINT64_C(81068032), // UDIV_ZPmZ_D |
| UINT64_C(76873728), // UDIV_ZPmZ_S |
| UINT64_C(1155531776), // UDOT_ZZZI_D |
| UINT64_C(1151337472), // UDOT_ZZZI_S |
| UINT64_C(1153434624), // UDOT_ZZZ_D |
| UINT64_C(1149240320), // UDOT_ZZZ_S |
| UINT64_C(1870716928), // UDOTlanev16i8 |
| UINT64_C(796975104), // UDOTlanev8i8 |
| UINT64_C(1853920256), // UDOTv16i8 |
| UINT64_C(780178432), // UDOTv8i8 |
| UINT64_C(1141997568), // UHADD_ZPmZ_B |
| UINT64_C(1154580480), // UHADD_ZPmZ_D |
| UINT64_C(1146191872), // UHADD_ZPmZ_H |
| UINT64_C(1150386176), // UHADD_ZPmZ_S |
| UINT64_C(1847591936), // UHADDv16i8 |
| UINT64_C(782238720), // UHADDv2i32 |
| UINT64_C(778044416), // UHADDv4i16 |
| UINT64_C(1855980544), // UHADDv4i32 |
| UINT64_C(1851786240), // UHADDv8i16 |
| UINT64_C(773850112), // UHADDv8i8 |
| UINT64_C(1142390784), // UHSUBR_ZPmZ_B |
| UINT64_C(1154973696), // UHSUBR_ZPmZ_D |
| UINT64_C(1146585088), // UHSUBR_ZPmZ_H |
| UINT64_C(1150779392), // UHSUBR_ZPmZ_S |
| UINT64_C(1142128640), // UHSUB_ZPmZ_B |
| UINT64_C(1154711552), // UHSUB_ZPmZ_D |
| UINT64_C(1146322944), // UHSUB_ZPmZ_H |
| UINT64_C(1150517248), // UHSUB_ZPmZ_S |
| UINT64_C(1847600128), // UHSUBv16i8 |
| UINT64_C(782246912), // UHSUBv2i32 |
| UINT64_C(778052608), // UHSUBv4i16 |
| UINT64_C(1855988736), // UHSUBv4i32 |
| UINT64_C(1851794432), // UHSUBv8i16 |
| UINT64_C(773858304), // UHSUBv8i8 |
| UINT64_C(2610954240), // UMADDLrrr |
| UINT64_C(1142267904), // UMAXP_ZPmZ_B |
| UINT64_C(1154850816), // UMAXP_ZPmZ_D |
| UINT64_C(1146462208), // UMAXP_ZPmZ_H |
| UINT64_C(1150656512), // UMAXP_ZPmZ_S |
| UINT64_C(1847632896), // UMAXPv16i8 |
| UINT64_C(782279680), // UMAXPv2i32 |
| UINT64_C(778085376), // UMAXPv4i16 |
| UINT64_C(1856021504), // UMAXPv4i32 |
| UINT64_C(1851827200), // UMAXPv8i16 |
| UINT64_C(773891072), // UMAXPv8i8 |
| UINT64_C(67706880), // UMAXV_VPZ_B |
| UINT64_C(80289792), // UMAXV_VPZ_D |
| UINT64_C(71901184), // UMAXV_VPZ_H |
| UINT64_C(76095488), // UMAXV_VPZ_S |
| UINT64_C(1848682496), // UMAXVv16i8v |
| UINT64_C(779134976), // UMAXVv4i16v |
| UINT64_C(1857071104), // UMAXVv4i32v |
| UINT64_C(1852876800), // UMAXVv8i16v |
| UINT64_C(774940672), // UMAXVv8i8v |
| UINT64_C(623493120), // UMAX_ZI_B |
| UINT64_C(636076032), // UMAX_ZI_D |
| UINT64_C(627687424), // UMAX_ZI_H |
| UINT64_C(631881728), // UMAX_ZI_S |
| UINT64_C(67698688), // UMAX_ZPmZ_B |
| UINT64_C(80281600), // UMAX_ZPmZ_D |
| UINT64_C(71892992), // UMAX_ZPmZ_H |
| UINT64_C(76087296), // UMAX_ZPmZ_S |
| UINT64_C(1847616512), // UMAXv16i8 |
| UINT64_C(782263296), // UMAXv2i32 |
| UINT64_C(778068992), // UMAXv4i16 |
| UINT64_C(1856005120), // UMAXv4i32 |
| UINT64_C(1851810816), // UMAXv8i16 |
| UINT64_C(773874688), // UMAXv8i8 |
| UINT64_C(1142398976), // UMINP_ZPmZ_B |
| UINT64_C(1154981888), // UMINP_ZPmZ_D |
| UINT64_C(1146593280), // UMINP_ZPmZ_H |
| UINT64_C(1150787584), // UMINP_ZPmZ_S |
| UINT64_C(1847634944), // UMINPv16i8 |
| UINT64_C(782281728), // UMINPv2i32 |
| UINT64_C(778087424), // UMINPv4i16 |
| UINT64_C(1856023552), // UMINPv4i32 |
| UINT64_C(1851829248), // UMINPv8i16 |
| UINT64_C(773893120), // UMINPv8i8 |
| UINT64_C(67837952), // UMINV_VPZ_B |
| UINT64_C(80420864), // UMINV_VPZ_D |
| UINT64_C(72032256), // UMINV_VPZ_H |
| UINT64_C(76226560), // UMINV_VPZ_S |
| UINT64_C(1848748032), // UMINVv16i8v |
| UINT64_C(779200512), // UMINVv4i16v |
| UINT64_C(1857136640), // UMINVv4i32v |
| UINT64_C(1852942336), // UMINVv8i16v |
| UINT64_C(775006208), // UMINVv8i8v |
| UINT64_C(623624192), // UMIN_ZI_B |
| UINT64_C(636207104), // UMIN_ZI_D |
| UINT64_C(627818496), // UMIN_ZI_H |
| UINT64_C(632012800), // UMIN_ZI_S |
| UINT64_C(67829760), // UMIN_ZPmZ_B |
| UINT64_C(80412672), // UMIN_ZPmZ_D |
| UINT64_C(72024064), // UMIN_ZPmZ_H |
| UINT64_C(76218368), // UMIN_ZPmZ_S |
| UINT64_C(1847618560), // UMINv16i8 |
| UINT64_C(782265344), // UMINv2i32 |
| UINT64_C(778071040), // UMINv4i16 |
| UINT64_C(1856007168), // UMINv4i32 |
| UINT64_C(1851812864), // UMINv8i16 |
| UINT64_C(773876736), // UMINv8i8 |
| UINT64_C(1155567616), // UMLALB_ZZZI_D |
| UINT64_C(1151373312), // UMLALB_ZZZI_S |
| UINT64_C(1153452032), // UMLALB_ZZZ_D |
| UINT64_C(1145063424), // UMLALB_ZZZ_H |
| UINT64_C(1149257728), // UMLALB_ZZZ_S |
| UINT64_C(1155568640), // UMLALT_ZZZI_D |
| UINT64_C(1151374336), // UMLALT_ZZZI_S |
| UINT64_C(1153453056), // UMLALT_ZZZ_D |
| UINT64_C(1145064448), // UMLALT_ZZZ_H |
| UINT64_C(1149258752), // UMLALT_ZZZ_S |
| UINT64_C(1847623680), // UMLALv16i8_v8i16 |
| UINT64_C(796925952), // UMLALv2i32_indexed |
| UINT64_C(782270464), // UMLALv2i32_v2i64 |
| UINT64_C(792731648), // UMLALv4i16_indexed |
| UINT64_C(778076160), // UMLALv4i16_v4i32 |
| UINT64_C(1870667776), // UMLALv4i32_indexed |
| UINT64_C(1856012288), // UMLALv4i32_v2i64 |
| UINT64_C(1866473472), // UMLALv8i16_indexed |
| UINT64_C(1851817984), // UMLALv8i16_v4i32 |
| UINT64_C(773881856), // UMLALv8i8_v8i16 |
| UINT64_C(1155575808), // UMLSLB_ZZZI_D |
| UINT64_C(1151381504), // UMLSLB_ZZZI_S |
| UINT64_C(1153456128), // UMLSLB_ZZZ_D |
| UINT64_C(1145067520), // UMLSLB_ZZZ_H |
| UINT64_C(1149261824), // UMLSLB_ZZZ_S |
| UINT64_C(1155576832), // UMLSLT_ZZZI_D |
| UINT64_C(1151382528), // UMLSLT_ZZZI_S |
| UINT64_C(1153457152), // UMLSLT_ZZZ_D |
| UINT64_C(1145068544), // UMLSLT_ZZZ_H |
| UINT64_C(1149262848), // UMLSLT_ZZZ_S |
| UINT64_C(1847631872), // UMLSLv16i8_v8i16 |
| UINT64_C(796942336), // UMLSLv2i32_indexed |
| UINT64_C(782278656), // UMLSLv2i32_v2i64 |
| UINT64_C(792748032), // UMLSLv4i16_indexed |
| UINT64_C(778084352), // UMLSLv4i16_v4i32 |
| UINT64_C(1870684160), // UMLSLv4i32_indexed |
| UINT64_C(1856020480), // UMLSLv4i32_v2i64 |
| UINT64_C(1866489856), // UMLSLv8i16_indexed |
| UINT64_C(1851826176), // UMLSLv8i16_v4i32 |
| UINT64_C(773890048), // UMLSLv8i8_v8i16 |
| UINT64_C(235027456), // UMOVvi16 |
| UINT64_C(235158528), // UMOVvi32 |
| UINT64_C(1309162496), // UMOVvi64 |
| UINT64_C(234961920), // UMOVvi8 |
| UINT64_C(2610987008), // UMSUBLrrr |
| UINT64_C(68354048), // UMULH_ZPmZ_B |
| UINT64_C(80936960), // UMULH_ZPmZ_D |
| UINT64_C(72548352), // UMULH_ZPmZ_H |
| UINT64_C(76742656), // UMULH_ZPmZ_S |
| UINT64_C(69233664), // UMULH_ZZZ_B |
| UINT64_C(81816576), // UMULH_ZZZ_D |
| UINT64_C(73427968), // UMULH_ZZZ_H |
| UINT64_C(77622272), // UMULH_ZZZ_S |
| UINT64_C(2613051392), // UMULHrr |
| UINT64_C(1155584000), // UMULLB_ZZZI_D |
| UINT64_C(1151389696), // UMULLB_ZZZI_S |
| UINT64_C(1170241536), // UMULLB_ZZZ_D |
| UINT64_C(1161852928), // UMULLB_ZZZ_H |
| UINT64_C(1166047232), // UMULLB_ZZZ_S |
| UINT64_C(1155585024), // UMULLT_ZZZI_D |
| UINT64_C(1151390720), // UMULLT_ZZZI_S |
| UINT64_C(1170242560), // UMULLT_ZZZ_D |
| UINT64_C(1161853952), // UMULLT_ZZZ_H |
| UINT64_C(1166048256), // UMULLT_ZZZ_S |
| UINT64_C(1847640064), // UMULLv16i8_v8i16 |
| UINT64_C(796958720), // UMULLv2i32_indexed |
| UINT64_C(782286848), // UMULLv2i32_v2i64 |
| UINT64_C(792764416), // UMULLv4i16_indexed |
| UINT64_C(778092544), // UMULLv4i16_v4i32 |
| UINT64_C(1870700544), // UMULLv4i32_indexed |
| UINT64_C(1856028672), // UMULLv4i32_v2i64 |
| UINT64_C(1866506240), // UMULLv8i16_indexed |
| UINT64_C(1851834368), // UMULLv8i16_v4i32 |
| UINT64_C(773898240), // UMULLv8i8_v8i16 |
| UINT64_C(623230976), // UQADD_ZI_B |
| UINT64_C(635813888), // UQADD_ZI_D |
| UINT64_C(627425280), // UQADD_ZI_H |
| UINT64_C(631619584), // UQADD_ZI_S |
| UINT64_C(1142521856), // UQADD_ZPmZ_B |
| UINT64_C(1155104768), // UQADD_ZPmZ_D |
| UINT64_C(1146716160), // UQADD_ZPmZ_H |
| UINT64_C(1150910464), // UQADD_ZPmZ_S |
| UINT64_C(69211136), // UQADD_ZZZ_B |
| UINT64_C(81794048), // UQADD_ZZZ_D |
| UINT64_C(73405440), // UQADD_ZZZ_H |
| UINT64_C(77599744), // UQADD_ZZZ_S |
| UINT64_C(1847593984), // UQADDv16i8 |
| UINT64_C(2120223744), // UQADDv1i16 |
| UINT64_C(2124418048), // UQADDv1i32 |
| UINT64_C(2128612352), // UQADDv1i64 |
| UINT64_C(2116029440), // UQADDv1i8 |
| UINT64_C(782240768), // UQADDv2i32 |
| UINT64_C(1860176896), // UQADDv2i64 |
| UINT64_C(778046464), // UQADDv4i16 |
| UINT64_C(1855982592), // UQADDv4i32 |
| UINT64_C(1851788288), // UQADDv8i16 |
| UINT64_C(773852160), // UQADDv8i8 |
| UINT64_C(69270528), // UQDECB_WPiI |
| UINT64_C(70319104), // UQDECB_XPiI |
| UINT64_C(81853440), // UQDECD_WPiI |
| UINT64_C(82902016), // UQDECD_XPiI |
| UINT64_C(81841152), // UQDECD_ZPiI |
| UINT64_C(73464832), // UQDECH_WPiI |
| UINT64_C(74513408), // UQDECH_XPiI |
| UINT64_C(73452544), // UQDECH_ZPiI |
| UINT64_C(623609856), // UQDECP_WP_B |
| UINT64_C(636192768), // UQDECP_WP_D |
| UINT64_C(627804160), // UQDECP_WP_H |
| UINT64_C(631998464), // UQDECP_WP_S |
| UINT64_C(623610880), // UQDECP_XP_B |
| UINT64_C(636193792), // UQDECP_XP_D |
| UINT64_C(627805184), // UQDECP_XP_H |
| UINT64_C(631999488), // UQDECP_XP_S |
| UINT64_C(636190720), // UQDECP_ZP_D |
| UINT64_C(627802112), // UQDECP_ZP_H |
| UINT64_C(631996416), // UQDECP_ZP_S |
| UINT64_C(77659136), // UQDECW_WPiI |
| UINT64_C(78707712), // UQDECW_XPiI |
| UINT64_C(77646848), // UQDECW_ZPiI |
| UINT64_C(69268480), // UQINCB_WPiI |
| UINT64_C(70317056), // UQINCB_XPiI |
| UINT64_C(81851392), // UQINCD_WPiI |
| UINT64_C(82899968), // UQINCD_XPiI |
| UINT64_C(81839104), // UQINCD_ZPiI |
| UINT64_C(73462784), // UQINCH_WPiI |
| UINT64_C(74511360), // UQINCH_XPiI |
| UINT64_C(73450496), // UQINCH_ZPiI |
| UINT64_C(623478784), // UQINCP_WP_B |
| UINT64_C(636061696), // UQINCP_WP_D |
| UINT64_C(627673088), // UQINCP_WP_H |
| UINT64_C(631867392), // UQINCP_WP_S |
| UINT64_C(623479808), // UQINCP_XP_B |
| UINT64_C(636062720), // UQINCP_XP_D |
| UINT64_C(627674112), // UQINCP_XP_H |
| UINT64_C(631868416), // UQINCP_XP_S |
| UINT64_C(636059648), // UQINCP_ZP_D |
| UINT64_C(627671040), // UQINCP_ZP_H |
| UINT64_C(631865344), // UQINCP_ZP_S |
| UINT64_C(77657088), // UQINCW_WPiI |
| UINT64_C(78705664), // UQINCW_XPiI |
| UINT64_C(77644800), // UQINCW_ZPiI |
| UINT64_C(1141866496), // UQRSHLR_ZPmZ_B |
| UINT64_C(1154449408), // UQRSHLR_ZPmZ_D |
| UINT64_C(1146060800), // UQRSHLR_ZPmZ_H |
| UINT64_C(1150255104), // UQRSHLR_ZPmZ_S |
| UINT64_C(1141604352), // UQRSHL_ZPmZ_B |
| UINT64_C(1154187264), // UQRSHL_ZPmZ_D |
| UINT64_C(1145798656), // UQRSHL_ZPmZ_H |
| UINT64_C(1149992960), // UQRSHL_ZPmZ_S |
| UINT64_C(1847614464), // UQRSHLv16i8 |
| UINT64_C(2120244224), // UQRSHLv1i16 |
| UINT64_C(2124438528), // UQRSHLv1i32 |
| UINT64_C(2128632832), // UQRSHLv1i64 |
| UINT64_C(2116049920), // UQRSHLv1i8 |
| UINT64_C(782261248), // UQRSHLv2i32 |
| UINT64_C(1860197376), // UQRSHLv2i64 |
| UINT64_C(778066944), // UQRSHLv4i16 |
| UINT64_C(1856003072), // UQRSHLv4i32 |
| UINT64_C(1851808768), // UQRSHLv8i16 |
| UINT64_C(773872640), // UQRSHLv8i8 |
| UINT64_C(1160263680), // UQRSHRNB_ZZI_B |
| UINT64_C(1160787968), // UQRSHRNB_ZZI_H |
| UINT64_C(1163933696), // UQRSHRNB_ZZI_S |
| UINT64_C(1160264704), // UQRSHRNT_ZZI_B |
| UINT64_C(1160788992), // UQRSHRNT_ZZI_H |
| UINT64_C(1163934720), // UQRSHRNT_ZZI_S |
| UINT64_C(2131270656), // UQRSHRNb |
| UINT64_C(2131794944), // UQRSHRNh |
| UINT64_C(2132843520), // UQRSHRNs |
| UINT64_C(1862835200), // UQRSHRNv16i8_shift |
| UINT64_C(790666240), // UQRSHRNv2i32_shift |
| UINT64_C(789617664), // UQRSHRNv4i16_shift |
| UINT64_C(1864408064), // UQRSHRNv4i32_shift |
| UINT64_C(1863359488), // UQRSHRNv8i16_shift |
| UINT64_C(789093376), // UQRSHRNv8i8_shift |
| UINT64_C(1141735424), // UQSHLR_ZPmZ_B |
| UINT64_C(1154318336), // UQSHLR_ZPmZ_D |
| UINT64_C(1145929728), // UQSHLR_ZPmZ_H |
| UINT64_C(1150124032), // UQSHLR_ZPmZ_S |
| UINT64_C(67600640), // UQSHL_ZPmI_B |
| UINT64_C(75988992), // UQSHL_ZPmI_D |
| UINT64_C(67600896), // UQSHL_ZPmI_H |
| UINT64_C(71794688), // UQSHL_ZPmI_S |
| UINT64_C(1141473280), // UQSHL_ZPmZ_B |
| UINT64_C(1154056192), // UQSHL_ZPmZ_D |
| UINT64_C(1145667584), // UQSHL_ZPmZ_H |
| UINT64_C(1149861888), // UQSHL_ZPmZ_S |
| UINT64_C(2131260416), // UQSHLb |
| UINT64_C(2134930432), // UQSHLd |
| UINT64_C(2131784704), // UQSHLh |
| UINT64_C(2132833280), // UQSHLs |
| UINT64_C(1847610368), // UQSHLv16i8 |
| UINT64_C(1862824960), // UQSHLv16i8_shift |
| UINT64_C(2120240128), // UQSHLv1i16 |
| UINT64_C(2124434432), // UQSHLv1i32 |
| UINT64_C(2128628736), // UQSHLv1i64 |
| UINT64_C(2116045824), // UQSHLv1i8 |
| UINT64_C(782257152), // UQSHLv2i32 |
| UINT64_C(790656000), // UQSHLv2i32_shift |
| UINT64_C(1860193280), // UQSHLv2i64 |
| UINT64_C(1866494976), // UQSHLv2i64_shift |
| UINT64_C(778062848), // UQSHLv4i16 |
| UINT64_C(789607424), // UQSHLv4i16_shift |
| UINT64_C(1855998976), // UQSHLv4i32 |
| UINT64_C(1864397824), // UQSHLv4i32_shift |
| UINT64_C(1851804672), // UQSHLv8i16 |
| UINT64_C(1863349248), // UQSHLv8i16_shift |
| UINT64_C(773868544), // UQSHLv8i8 |
| UINT64_C(789083136), // UQSHLv8i8_shift |
| UINT64_C(1160261632), // UQSHRNB_ZZI_B |
| UINT64_C(1160785920), // UQSHRNB_ZZI_H |
| UINT64_C(1163931648), // UQSHRNB_ZZI_S |
| UINT64_C(1160262656), // UQSHRNT_ZZI_B |
| UINT64_C(1160786944), // UQSHRNT_ZZI_H |
| UINT64_C(1163932672), // UQSHRNT_ZZI_S |
| UINT64_C(2131268608), // UQSHRNb |
| UINT64_C(2131792896), // UQSHRNh |
| UINT64_C(2132841472), // UQSHRNs |
| UINT64_C(1862833152), // UQSHRNv16i8_shift |
| UINT64_C(790664192), // UQSHRNv2i32_shift |
| UINT64_C(789615616), // UQSHRNv4i16_shift |
| UINT64_C(1864406016), // UQSHRNv4i32_shift |
| UINT64_C(1863357440), // UQSHRNv8i16_shift |
| UINT64_C(789091328), // UQSHRNv8i8_shift |
| UINT64_C(1142915072), // UQSUBR_ZPmZ_B |
| UINT64_C(1155497984), // UQSUBR_ZPmZ_D |
| UINT64_C(1147109376), // UQSUBR_ZPmZ_H |
| UINT64_C(1151303680), // UQSUBR_ZPmZ_S |
| UINT64_C(623362048), // UQSUB_ZI_B |
| UINT64_C(635944960), // UQSUB_ZI_D |
| UINT64_C(627556352), // UQSUB_ZI_H |
| UINT64_C(631750656), // UQSUB_ZI_S |
| UINT64_C(1142652928), // UQSUB_ZPmZ_B |
| UINT64_C(1155235840), // UQSUB_ZPmZ_D |
| UINT64_C(1146847232), // UQSUB_ZPmZ_H |
| UINT64_C(1151041536), // UQSUB_ZPmZ_S |
| UINT64_C(69213184), // UQSUB_ZZZ_B |
| UINT64_C(81796096), // UQSUB_ZZZ_D |
| UINT64_C(73407488), // UQSUB_ZZZ_H |
| UINT64_C(77601792), // UQSUB_ZZZ_S |
| UINT64_C(1847602176), // UQSUBv16i8 |
| UINT64_C(2120231936), // UQSUBv1i16 |
| UINT64_C(2124426240), // UQSUBv1i32 |
| UINT64_C(2128620544), // UQSUBv1i64 |
| UINT64_C(2116037632), // UQSUBv1i8 |
| UINT64_C(782248960), // UQSUBv2i32 |
| UINT64_C(1860185088), // UQSUBv2i64 |
| UINT64_C(778054656), // UQSUBv4i16 |
| UINT64_C(1855990784), // UQSUBv4i32 |
| UINT64_C(1851796480), // UQSUBv8i16 |
| UINT64_C(773860352), // UQSUBv8i8 |
| UINT64_C(1160267776), // UQXTNB_ZZ_B |
| UINT64_C(1160792064), // UQXTNB_ZZ_H |
| UINT64_C(1163937792), // UQXTNB_ZZ_S |
| UINT64_C(1160268800), // UQXTNT_ZZ_B |
| UINT64_C(1160793088), // UQXTNT_ZZ_H |
| UINT64_C(1163938816), // UQXTNT_ZZ_S |
| UINT64_C(1847674880), // UQXTNv16i8 |
| UINT64_C(2120304640), // UQXTNv1i16 |
| UINT64_C(2124498944), // UQXTNv1i32 |
| UINT64_C(2116110336), // UQXTNv1i8 |
| UINT64_C(782321664), // UQXTNv2i32 |
| UINT64_C(778127360), // UQXTNv4i16 |
| UINT64_C(1856063488), // UQXTNv4i32 |
| UINT64_C(1851869184), // UQXTNv8i16 |
| UINT64_C(773933056), // UQXTNv8i8 |
| UINT64_C(1149280256), // URECPE_ZPmZ_S |
| UINT64_C(245483520), // URECPEv2i32 |
| UINT64_C(1319225344), // URECPEv4i32 |
| UINT64_C(1142259712), // URHADD_ZPmZ_B |
| UINT64_C(1154842624), // URHADD_ZPmZ_D |
| UINT64_C(1146454016), // URHADD_ZPmZ_H |
| UINT64_C(1150648320), // URHADD_ZPmZ_S |
| UINT64_C(1847596032), // URHADDv16i8 |
| UINT64_C(782242816), // URHADDv2i32 |
| UINT64_C(778048512), // URHADDv4i16 |
| UINT64_C(1855984640), // URHADDv4i32 |
| UINT64_C(1851790336), // URHADDv8i16 |
| UINT64_C(773854208), // URHADDv8i8 |
| UINT64_C(1141342208), // URSHLR_ZPmZ_B |
| UINT64_C(1153925120), // URSHLR_ZPmZ_D |
| UINT64_C(1145536512), // URSHLR_ZPmZ_H |
| UINT64_C(1149730816), // URSHLR_ZPmZ_S |
| UINT64_C(1141080064), // URSHL_ZPmZ_B |
| UINT64_C(1153662976), // URSHL_ZPmZ_D |
| UINT64_C(1145274368), // URSHL_ZPmZ_H |
| UINT64_C(1149468672), // URSHL_ZPmZ_S |
| UINT64_C(1847612416), // URSHLv16i8 |
| UINT64_C(2128630784), // URSHLv1i64 |
| UINT64_C(782259200), // URSHLv2i32 |
| UINT64_C(1860195328), // URSHLv2i64 |
| UINT64_C(778064896), // URSHLv4i16 |
| UINT64_C(1856001024), // URSHLv4i32 |
| UINT64_C(1851806720), // URSHLv8i16 |
| UINT64_C(773870592), // URSHLv8i8 |
| UINT64_C(67993856), // URSHR_ZPmI_B |
| UINT64_C(76382208), // URSHR_ZPmI_D |
| UINT64_C(67994112), // URSHR_ZPmI_H |
| UINT64_C(72187904), // URSHR_ZPmI_S |
| UINT64_C(2134909952), // URSHRd |
| UINT64_C(1862804480), // URSHRv16i8_shift |
| UINT64_C(790635520), // URSHRv2i32_shift |
| UINT64_C(1866474496), // URSHRv2i64_shift |
| UINT64_C(789586944), // URSHRv4i16_shift |
| UINT64_C(1864377344), // URSHRv4i32_shift |
| UINT64_C(1863328768), // URSHRv8i16_shift |
| UINT64_C(789062656), // URSHRv8i8_shift |
| UINT64_C(1149345792), // URSQRTE_ZPmZ_S |
| UINT64_C(782354432), // URSQRTEv2i32 |
| UINT64_C(1856096256), // URSQRTEv4i32 |
| UINT64_C(1158212608), // URSRA_ZZI_B |
| UINT64_C(1166076928), // URSRA_ZZI_D |
| UINT64_C(1158736896), // URSRA_ZZI_H |
| UINT64_C(1161882624), // URSRA_ZZI_S |
| UINT64_C(2134914048), // URSRAd |
| UINT64_C(1862808576), // URSRAv16i8_shift |
| UINT64_C(790639616), // URSRAv2i32_shift |
| UINT64_C(1866478592), // URSRAv2i64_shift |
| UINT64_C(789591040), // URSRAv4i16_shift |
| UINT64_C(1864381440), // URSRAv4i32_shift |
| UINT64_C(1863332864), // URSRAv8i16_shift |
| UINT64_C(789066752), // URSRAv8i8_shift |
| UINT64_C(1161865216), // USHLLB_ZZI_D |
| UINT64_C(1158195200), // USHLLB_ZZI_H |
| UINT64_C(1158719488), // USHLLB_ZZI_S |
| UINT64_C(1161866240), // USHLLT_ZZI_D |
| UINT64_C(1158196224), // USHLLT_ZZI_H |
| UINT64_C(1158720512), // USHLLT_ZZI_S |
| UINT64_C(1862837248), // USHLLv16i8_shift |
| UINT64_C(790668288), // USHLLv2i32_shift |
| UINT64_C(789619712), // USHLLv4i16_shift |
| UINT64_C(1864410112), // USHLLv4i32_shift |
| UINT64_C(1863361536), // USHLLv8i16_shift |
| UINT64_C(789095424), // USHLLv8i8_shift |
| UINT64_C(1847608320), // USHLv16i8 |
| UINT64_C(2128626688), // USHLv1i64 |
| UINT64_C(782255104), // USHLv2i32 |
| UINT64_C(1860191232), // USHLv2i64 |
| UINT64_C(778060800), // USHLv4i16 |
| UINT64_C(1855996928), // USHLv4i32 |
| UINT64_C(1851802624), // USHLv8i16 |
| UINT64_C(773866496), // USHLv8i8 |
| UINT64_C(2134901760), // USHRd |
| UINT64_C(1862796288), // USHRv16i8_shift |
| UINT64_C(790627328), // USHRv2i32_shift |
| UINT64_C(1866466304), // USHRv2i64_shift |
| UINT64_C(789578752), // USHRv4i16_shift |
| UINT64_C(1864369152), // USHRv4i32_shift |
| UINT64_C(1863320576), // USHRv8i16_shift |
| UINT64_C(789054464), // USHRv8i8_shift |
| UINT64_C(1142784000), // USQADD_ZPmZ_B |
| UINT64_C(1155366912), // USQADD_ZPmZ_D |
| UINT64_C(1146978304), // USQADD_ZPmZ_H |
| UINT64_C(1151172608), // USQADD_ZPmZ_S |
| UINT64_C(1847605248), // USQADDv16i8 |
| UINT64_C(2120235008), // USQADDv1i16 |
| UINT64_C(2124429312), // USQADDv1i32 |
| UINT64_C(2128623616), // USQADDv1i64 |
| UINT64_C(2116040704), // USQADDv1i8 |
| UINT64_C(782252032), // USQADDv2i32 |
| UINT64_C(1860188160), // USQADDv2i64 |
| UINT64_C(778057728), // USQADDv4i16 |
| UINT64_C(1855993856), // USQADDv4i32 |
| UINT64_C(1851799552), // USQADDv8i16 |
| UINT64_C(773863424), // USQADDv8i8 |
| UINT64_C(1158210560), // USRA_ZZI_B |
| UINT64_C(1166074880), // USRA_ZZI_D |
| UINT64_C(1158734848), // USRA_ZZI_H |
| UINT64_C(1161880576), // USRA_ZZI_S |
| UINT64_C(2134905856), // USRAd |
| UINT64_C(1862800384), // USRAv16i8_shift |
| UINT64_C(790631424), // USRAv2i32_shift |
| UINT64_C(1866470400), // USRAv2i64_shift |
| UINT64_C(789582848), // USRAv4i16_shift |
| UINT64_C(1864373248), // USRAv4i32_shift |
| UINT64_C(1863324672), // USRAv8i16_shift |
| UINT64_C(789058560), // USRAv8i8_shift |
| UINT64_C(1170216960), // USUBLB_ZZZ_D |
| UINT64_C(1161828352), // USUBLB_ZZZ_H |
| UINT64_C(1166022656), // USUBLB_ZZZ_S |
| UINT64_C(1170217984), // USUBLT_ZZZ_D |
| UINT64_C(1161829376), // USUBLT_ZZZ_H |
| UINT64_C(1166023680), // USUBLT_ZZZ_S |
| UINT64_C(1847599104), // USUBLv16i8_v8i16 |
| UINT64_C(782245888), // USUBLv2i32_v2i64 |
| UINT64_C(778051584), // USUBLv4i16_v4i32 |
| UINT64_C(1855987712), // USUBLv4i32_v2i64 |
| UINT64_C(1851793408), // USUBLv8i16_v4i32 |
| UINT64_C(773857280), // USUBLv8i8_v8i16 |
| UINT64_C(1170233344), // USUBWB_ZZZ_D |
| UINT64_C(1161844736), // USUBWB_ZZZ_H |
| UINT64_C(1166039040), // USUBWB_ZZZ_S |
| UINT64_C(1170234368), // USUBWT_ZZZ_D |
| UINT64_C(1161845760), // USUBWT_ZZZ_H |
| UINT64_C(1166040064), // USUBWT_ZZZ_S |
| UINT64_C(1847603200), // USUBWv16i8_v8i16 |
| UINT64_C(782249984), // USUBWv2i32_v2i64 |
| UINT64_C(778055680), // USUBWv4i16_v4i32 |
| UINT64_C(1855991808), // USUBWv4i32_v2i64 |
| UINT64_C(1851797504), // USUBWv8i16_v4i32 |
| UINT64_C(773861376), // USUBWv8i8_v8i16 |
| UINT64_C(99825664), // UUNPKHI_ZZ_D |
| UINT64_C(91437056), // UUNPKHI_ZZ_H |
| UINT64_C(95631360), // UUNPKHI_ZZ_S |
| UINT64_C(99760128), // UUNPKLO_ZZ_D |
| UINT64_C(91371520), // UUNPKLO_ZZ_H |
| UINT64_C(95565824), // UUNPKLO_ZZ_S |
| UINT64_C(80846848), // UXTB_ZPmZ_D |
| UINT64_C(72458240), // UXTB_ZPmZ_H |
| UINT64_C(76652544), // UXTB_ZPmZ_S |
| UINT64_C(80977920), // UXTH_ZPmZ_D |
| UINT64_C(76783616), // UXTH_ZPmZ_S |
| UINT64_C(81108992), // UXTW_ZPmZ_D |
| UINT64_C(86001664), // UZP1_PPP_B |
| UINT64_C(98584576), // UZP1_PPP_D |
| UINT64_C(90195968), // UZP1_PPP_H |
| UINT64_C(94390272), // UZP1_PPP_S |
| UINT64_C(86009856), // UZP1_ZZZ_B |
| UINT64_C(98592768), // UZP1_ZZZ_D |
| UINT64_C(90204160), // UZP1_ZZZ_H |
| UINT64_C(94398464), // UZP1_ZZZ_S |
| UINT64_C(1308628992), // UZP1v16i8 |
| UINT64_C(243275776), // UZP1v2i32 |
| UINT64_C(1321211904), // UZP1v2i64 |
| UINT64_C(239081472), // UZP1v4i16 |
| UINT64_C(1317017600), // UZP1v4i32 |
| UINT64_C(1312823296), // UZP1v8i16 |
| UINT64_C(234887168), // UZP1v8i8 |
| UINT64_C(86002688), // UZP2_PPP_B |
| UINT64_C(98585600), // UZP2_PPP_D |
| UINT64_C(90196992), // UZP2_PPP_H |
| UINT64_C(94391296), // UZP2_PPP_S |
| UINT64_C(86010880), // UZP2_ZZZ_B |
| UINT64_C(98593792), // UZP2_ZZZ_D |
| UINT64_C(90205184), // UZP2_ZZZ_H |
| UINT64_C(94399488), // UZP2_ZZZ_S |
| UINT64_C(1308645376), // UZP2v16i8 |
| UINT64_C(243292160), // UZP2v2i32 |
| UINT64_C(1321228288), // UZP2v2i64 |
| UINT64_C(239097856), // UZP2v4i16 |
| UINT64_C(1317033984), // UZP2v4i32 |
| UINT64_C(1312839680), // UZP2v8i16 |
| UINT64_C(234903552), // UZP2v8i8 |
| UINT64_C(622854144), // WHILEGE_PWW_B |
| UINT64_C(635437056), // WHILEGE_PWW_D |
| UINT64_C(627048448), // WHILEGE_PWW_H |
| UINT64_C(631242752), // WHILEGE_PWW_S |
| UINT64_C(622858240), // WHILEGE_PXX_B |
| UINT64_C(635441152), // WHILEGE_PXX_D |
| UINT64_C(627052544), // WHILEGE_PXX_H |
| UINT64_C(631246848), // WHILEGE_PXX_S |
| UINT64_C(622854160), // WHILEGT_PWW_B |
| UINT64_C(635437072), // WHILEGT_PWW_D |
| UINT64_C(627048464), // WHILEGT_PWW_H |
| UINT64_C(631242768), // WHILEGT_PWW_S |
| UINT64_C(622858256), // WHILEGT_PXX_B |
| UINT64_C(635441168), // WHILEGT_PXX_D |
| UINT64_C(627052560), // WHILEGT_PXX_H |
| UINT64_C(631246864), // WHILEGT_PXX_S |
| UINT64_C(622856208), // WHILEHI_PWW_B |
| UINT64_C(635439120), // WHILEHI_PWW_D |
| UINT64_C(627050512), // WHILEHI_PWW_H |
| UINT64_C(631244816), // WHILEHI_PWW_S |
| UINT64_C(622860304), // WHILEHI_PXX_B |
| UINT64_C(635443216), // WHILEHI_PXX_D |
| UINT64_C(627054608), // WHILEHI_PXX_H |
| UINT64_C(631248912), // WHILEHI_PXX_S |
| UINT64_C(622856192), // WHILEHS_PWW_B |
| UINT64_C(635439104), // WHILEHS_PWW_D |
| UINT64_C(627050496), // WHILEHS_PWW_H |
| UINT64_C(631244800), // WHILEHS_PWW_S |
| UINT64_C(622860288), // WHILEHS_PXX_B |
| UINT64_C(635443200), // WHILEHS_PXX_D |
| UINT64_C(627054592), // WHILEHS_PXX_H |
| UINT64_C(631248896), // WHILEHS_PXX_S |
| UINT64_C(622855184), // WHILELE_PWW_B |
| UINT64_C(635438096), // WHILELE_PWW_D |
| UINT64_C(627049488), // WHILELE_PWW_H |
| UINT64_C(631243792), // WHILELE_PWW_S |
| UINT64_C(622859280), // WHILELE_PXX_B |
| UINT64_C(635442192), // WHILELE_PXX_D |
| UINT64_C(627053584), // WHILELE_PXX_H |
| UINT64_C(631247888), // WHILELE_PXX_S |
| UINT64_C(622857216), // WHILELO_PWW_B |
| UINT64_C(635440128), // WHILELO_PWW_D |
| UINT64_C(627051520), // WHILELO_PWW_H |
| UINT64_C(631245824), // WHILELO_PWW_S |
| UINT64_C(622861312), // WHILELO_PXX_B |
| UINT64_C(635444224), // WHILELO_PXX_D |
| UINT64_C(627055616), // WHILELO_PXX_H |
| UINT64_C(631249920), // WHILELO_PXX_S |
| UINT64_C(622857232), // WHILELS_PWW_B |
| UINT64_C(635440144), // WHILELS_PWW_D |
| UINT64_C(627051536), // WHILELS_PWW_H |
| UINT64_C(631245840), // WHILELS_PWW_S |
| UINT64_C(622861328), // WHILELS_PXX_B |
| UINT64_C(635444240), // WHILELS_PXX_D |
| UINT64_C(627055632), // WHILELS_PXX_H |
| UINT64_C(631249936), // WHILELS_PXX_S |
| UINT64_C(622855168), // WHILELT_PWW_B |
| UINT64_C(635438080), // WHILELT_PWW_D |
| UINT64_C(627049472), // WHILELT_PWW_H |
| UINT64_C(631243776), // WHILELT_PWW_S |
| UINT64_C(622859264), // WHILELT_PXX_B |
| UINT64_C(635442176), // WHILELT_PXX_D |
| UINT64_C(627053568), // WHILELT_PXX_H |
| UINT64_C(631247872), // WHILELT_PXX_S |
| UINT64_C(622866448), // WHILERW_PXX_B |
| UINT64_C(635449360), // WHILERW_PXX_D |
| UINT64_C(627060752), // WHILERW_PXX_H |
| UINT64_C(631255056), // WHILERW_PXX_S |
| UINT64_C(622866432), // WHILEWR_PXX_B |
| UINT64_C(635449344), // WHILEWR_PXX_D |
| UINT64_C(627060736), // WHILEWR_PXX_H |
| UINT64_C(631255040), // WHILEWR_PXX_S |
| UINT64_C(623415296), // WRFFR |
| UINT64_C(3573563455), // XAFLAG |
| UINT64_C(3464495104), // XAR |
| UINT64_C(69743616), // XAR_ZZZI_B |
| UINT64_C(77607936), // XAR_ZZZI_D |
| UINT64_C(70267904), // XAR_ZZZI_H |
| UINT64_C(73413632), // XAR_ZZZI_S |
| UINT64_C(3670099936), // XPACD |
| UINT64_C(3670098912), // XPACI |
| UINT64_C(3573752063), // XPACLRI |
| UINT64_C(1310795776), // XTNv16i8 |
| UINT64_C(245442560), // XTNv2i32 |
| UINT64_C(241248256), // XTNv4i16 |
| UINT64_C(1319184384), // XTNv4i32 |
| UINT64_C(1314990080), // XTNv8i16 |
| UINT64_C(237053952), // XTNv8i8 |
| UINT64_C(85999616), // ZIP1_PPP_B |
| UINT64_C(98582528), // ZIP1_PPP_D |
| UINT64_C(90193920), // ZIP1_PPP_H |
| UINT64_C(94388224), // ZIP1_PPP_S |
| UINT64_C(86007808), // ZIP1_ZZZ_B |
| UINT64_C(98590720), // ZIP1_ZZZ_D |
| UINT64_C(90202112), // ZIP1_ZZZ_H |
| UINT64_C(94396416), // ZIP1_ZZZ_S |
| UINT64_C(1308637184), // ZIP1v16i8 |
| UINT64_C(243283968), // ZIP1v2i32 |
| UINT64_C(1321220096), // ZIP1v2i64 |
| UINT64_C(239089664), // ZIP1v4i16 |
| UINT64_C(1317025792), // ZIP1v4i32 |
| UINT64_C(1312831488), // ZIP1v8i16 |
| UINT64_C(234895360), // ZIP1v8i8 |
| UINT64_C(86000640), // ZIP2_PPP_B |
| UINT64_C(98583552), // ZIP2_PPP_D |
| UINT64_C(90194944), // ZIP2_PPP_H |
| UINT64_C(94389248), // ZIP2_PPP_S |
| UINT64_C(86008832), // ZIP2_ZZZ_B |
| UINT64_C(98591744), // ZIP2_ZZZ_D |
| UINT64_C(90203136), // ZIP2_ZZZ_H |
| UINT64_C(94397440), // ZIP2_ZZZ_S |
| UINT64_C(1308653568), // ZIP2v16i8 |
| UINT64_C(243300352), // ZIP2v2i32 |
| UINT64_C(1321236480), // ZIP2v2i64 |
| UINT64_C(239106048), // ZIP2v4i16 |
| UINT64_C(1317042176), // ZIP2v4i32 |
| UINT64_C(1312847872), // ZIP2v8i16 |
| UINT64_C(234911744), // ZIP2v8i8 |
| UINT64_C(0) |
| }; |
| const unsigned opcode = MI.getOpcode(); |
| uint64_t Value = InstBits[opcode]; |
| uint64_t op = 0; |
| (void)op; // suppress warning |
| switch (opcode) { |
| case AArch64::ADDSWrr: |
| case AArch64::ADDSXrr: |
| case AArch64::ADDWrr: |
| case AArch64::ADDXrr: |
| case AArch64::ADDlowTLS: |
| case AArch64::ADJCALLSTACKDOWN: |
| case AArch64::ADJCALLSTACKUP: |
| case AArch64::AESIMCrrTied: |
| case AArch64::AESMCrrTied: |
| case AArch64::ANDSWrr: |
| case AArch64::ANDSXrr: |
| case AArch64::ANDWrr: |
| case AArch64::ANDXrr: |
| case AArch64::AUTIA1716: |
| case AArch64::AUTIASP: |
| case AArch64::AUTIAZ: |
| case AArch64::AUTIB1716: |
| case AArch64::AUTIBSP: |
| case AArch64::AUTIBZ: |
| case AArch64::AXFLAG: |
| case AArch64::BICSWrr: |
| case AArch64::BICSXrr: |
| case AArch64::BICWrr: |
| case AArch64::BICXrr: |
| case AArch64::CATCHPAD: |
| case AArch64::CFINV: |
| case AArch64::CMP_SWAP_128: |
| case AArch64::CMP_SWAP_16: |
| case AArch64::CMP_SWAP_32: |
| case AArch64::CMP_SWAP_64: |
| case AArch64::CMP_SWAP_8: |
| case AArch64::CompilerBarrier: |
| case AArch64::DRPS: |
| case AArch64::EMITBKEY: |
| case AArch64::EONWrr: |
| case AArch64::EONXrr: |
| case AArch64::EORWrr: |
| case AArch64::EORXrr: |
| case AArch64::ERET: |
| case AArch64::ERETAA: |
| case AArch64::ERETAB: |
| case AArch64::F128CSEL: |
| case AArch64::FMOVD0: |
| case AArch64::FMOVH0: |
| case AArch64::FMOVS0: |
| case AArch64::HWASAN_CHECK_MEMACCESS: |
| case AArch64::HWASAN_CHECK_MEMACCESS_SHORTGRANULES: |
| case AArch64::IRGstack: |
| case AArch64::JumpTableDest16: |
| case AArch64::JumpTableDest32: |
| case AArch64::JumpTableDest8: |
| case AArch64::LOADgot: |
| case AArch64::MOVMCSym: |
| case AArch64::MOVaddr: |
| case AArch64::MOVaddrBA: |
| case AArch64::MOVaddrCP: |
| case AArch64::MOVaddrEXT: |
| case AArch64::MOVaddrJT: |
| case AArch64::MOVaddrTLS: |
| case AArch64::MOVbaseTLS: |
| case AArch64::MOVi32imm: |
| case AArch64::MOVi64imm: |
| case AArch64::ORNWrr: |
| case AArch64::ORNXrr: |
| case AArch64::ORRWrr: |
| case AArch64::ORRXrr: |
| case AArch64::PACIA1716: |
| case AArch64::PACIASP: |
| case AArch64::PACIAZ: |
| case AArch64::PACIB1716: |
| case AArch64::PACIBSP: |
| case AArch64::PACIBZ: |
| case AArch64::RETAA: |
| case AArch64::RETAB: |
| case AArch64::RET_ReallyLR: |
| case AArch64::SB: |
| case AArch64::SETFFR: |
| case AArch64::SPACE: |
| case AArch64::STGloop: |
| case AArch64::STZGloop: |
| case AArch64::SUBSWrr: |
| case AArch64::SUBSXrr: |
| case AArch64::SUBWrr: |
| case AArch64::SUBXrr: |
| case AArch64::SpeculationSafeValueW: |
| case AArch64::SpeculationSafeValueX: |
| case AArch64::TAGPstack: |
| case AArch64::TCOMMIT: |
| case AArch64::TCRETURNdi: |
| case AArch64::TCRETURNri: |
| case AArch64::TCRETURNriALL: |
| case AArch64::TCRETURNriBTI: |
| case AArch64::TLSDESCCALL: |
| case AArch64::TLSDESC_CALLSEQ: |
| case AArch64::TSB: |
| case AArch64::XAFLAG: |
| case AArch64::XPACLRI: { |
| break; |
| } |
| case AArch64::CLREX: |
| case AArch64::DMB: |
| case AArch64::DSB: |
| case AArch64::ISB: { |
| // op: CRm |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(15); |
| op <<= 8; |
| Value |= op; |
| break; |
| } |
| case AArch64::PFALSE: |
| case AArch64::RDFFR_P: { |
| // op: Pd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(15); |
| Value |= op; |
| break; |
| } |
| case AArch64::ANDS_PPzPP: |
| case AArch64::AND_PPzPP: |
| case AArch64::BICS_PPzPP: |
| case AArch64::BIC_PPzPP: |
| case AArch64::BRKPAS_PPzPP: |
| case AArch64::BRKPA_PPzPP: |
| case AArch64::BRKPBS_PPzPP: |
| case AArch64::BRKPB_PPzPP: |
| case AArch64::EORS_PPzPP: |
| case AArch64::EOR_PPzPP: |
| case AArch64::NANDS_PPzPP: |
| case AArch64::NAND_PPzPP: |
| case AArch64::NORS_PPzPP: |
| case AArch64::NOR_PPzPP: |
| case AArch64::ORNS_PPzPP: |
| case AArch64::ORN_PPzPP: |
| case AArch64::ORRS_PPzPP: |
| case AArch64::ORR_PPzPP: |
| case AArch64::SEL_PPPP: { |
| // op: Pd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(15); |
| Value |= op; |
| // op: Pg |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(15); |
| op <<= 10; |
| Value |= op; |
| // op: Pm |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(15); |
| op <<= 16; |
| Value |= op; |
| // op: Pn |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(15); |
| op <<= 5; |
| Value |= op; |
| break; |
| } |
| case AArch64::BRKAS_PPzP: |
| case AArch64::BRKA_PPzP: |
| case AArch64::BRKBS_PPzP: |
| case AArch64::BRKB_PPzP: { |
| // op: Pd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(15); |
| Value |= op; |
| // op: Pg |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(15); |
| op <<= 10; |
| Value |= op; |
| // op: Pn |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(15); |
| op <<= 5; |
| Value |= op; |
| break; |
| } |
| case AArch64::RDFFRS_PPz: |
| case AArch64::RDFFR_PPz: { |
| // op: Pd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(15); |
| Value |= op; |
| // op: Pg |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(15); |
| op <<= 5; |
| Value |= op; |
| break; |
| } |
| case AArch64::CMPEQ_PPzZZ_B: |
| case AArch64::CMPEQ_PPzZZ_D: |
| case AArch64::CMPEQ_PPzZZ_H: |
| case AArch64::CMPEQ_PPzZZ_S: |
| case AArch64::CMPEQ_WIDE_PPzZZ_B: |
| case AArch64::CMPEQ_WIDE_PPzZZ_H: |
| case AArch64::CMPEQ_WIDE_PPzZZ_S: |
| case AArch64::CMPGE_PPzZZ_B: |
| case AArch64::CMPGE_PPzZZ_D: |
| case AArch64::CMPGE_PPzZZ_H: |
| case AArch64::CMPGE_PPzZZ_S: |
| case AArch64::CMPGE_WIDE_PPzZZ_B: |
| case AArch64::CMPGE_WIDE_PPzZZ_H: |
| case AArch64::CMPGE_WIDE_PPzZZ_S: |
| case AArch64::CMPGT_PPzZZ_B: |
| case AArch64::CMPGT_PPzZZ_D: |
| case AArch64::CMPGT_PPzZZ_H: |
| case AArch64::CMPGT_PPzZZ_S: |
| case AArch64::CMPGT_WIDE_PPzZZ_B: |
| case AArch64::CMPGT_WIDE_PPzZZ_H: |
| case AArch64::CMPGT_WIDE_PPzZZ_S: |
| case AArch64::CMPHI_PPzZZ_B: |
| case AArch64::CMPHI_PPzZZ_D: |
| case AArch64::CMPHI_PPzZZ_H: |
| case AArch64::CMPHI_PPzZZ_S: |
| case AArch64::CMPHI_WIDE_PPzZZ_B: |
| case AArch64::CMPHI_WIDE_PPzZZ_H: |
| case AArch64::CMPHI_WIDE_PPzZZ_S: |
| case AArch64::CMPHS_PPzZZ_B: |
| case AArch64::CMPHS_PPzZZ_D: |
| case AArch64::CMPHS_PPzZZ_H: |
| case AArch64::CMPHS_PPzZZ_S: |
| case AArch64::CMPHS_WIDE_PPzZZ_B: |
| case AArch64::CMPHS_WIDE_PPzZZ_H: |
| case AArch64::CMPHS_WIDE_PPzZZ_S: |
| case AArch64::CMPLE_WIDE_PPzZZ_B: |
| case AArch64::CMPLE_WIDE_PPzZZ_H: |
| case AArch64::CMPLE_WIDE_PPzZZ_S: |
| case AArch64::CMPLO_WIDE_PPzZZ_B: |
| case AArch64::CMPLO_WIDE_PPzZZ_H: |
| case AArch64::CMPLO_WIDE_PPzZZ_S: |
| case AArch64::CMPLS_WIDE_PPzZZ_B: |
| case AArch64::CMPLS_WIDE_PPzZZ_H: |
| case AArch64::CMPLS_WIDE_PPzZZ_S: |
| case AArch64::CMPLT_WIDE_PPzZZ_B: |
| case AArch64::CMPLT_WIDE_PPzZZ_H: |
| case AArch64::CMPLT_WIDE_PPzZZ_S: |
| case AArch64::CMPNE_PPzZZ_B: |
| case AArch64::CMPNE_PPzZZ_D: |
| case AArch64::CMPNE_PPzZZ_H: |
| case AArch64::CMPNE_PPzZZ_S: |
| case AArch64::CMPNE_WIDE_PPzZZ_B: |
| case AArch64::CMPNE_WIDE_PPzZZ_H: |
| case AArch64::CMPNE_WIDE_PPzZZ_S: |
| case AArch64::FACGE_PPzZZ_D: |
| case AArch64::FACGE_PPzZZ_H: |
| case AArch64::FACGE_PPzZZ_S: |
| case AArch64::FACGT_PPzZZ_D: |
| case AArch64::FACGT_PPzZZ_H: |
| case AArch64::FACGT_PPzZZ_S: |
| case AArch64::FCMEQ_PPzZZ_D: |
| case AArch64::FCMEQ_PPzZZ_H: |
| case AArch64::FCMEQ_PPzZZ_S: |
| case AArch64::FCMGE_PPzZZ_D: |
| case AArch64::FCMGE_PPzZZ_H: |
| case AArch64::FCMGE_PPzZZ_S: |
| case AArch64::FCMGT_PPzZZ_D: |
| case AArch64::FCMGT_PPzZZ_H: |
| case AArch64::FCMGT_PPzZZ_S: |
| case AArch64::FCMNE_PPzZZ_D: |
| case AArch64::FCMNE_PPzZZ_H: |
| case AArch64::FCMNE_PPzZZ_S: |
| case AArch64::FCMUO_PPzZZ_D: |
| case AArch64::FCMUO_PPzZZ_H: |
| case AArch64::FCMUO_PPzZZ_S: |
| case AArch64::MATCH_PPzZZ_B: |
| case AArch64::MATCH_PPzZZ_H: |
| case AArch64::NMATCH_PPzZZ_B: |
| case AArch64::NMATCH_PPzZZ_H: { |
| // op: Pd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(15); |
| Value |= op; |
| // op: Pg |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(7); |
| op <<= 10; |
| Value |= op; |
| // op: Zm |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 16; |
| Value |= op; |
| // op: Zn |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| break; |
| } |
| case AArch64::FCMEQ_PPzZ0_D: |
| case AArch64::FCMEQ_PPzZ0_H: |
| case AArch64::FCMEQ_PPzZ0_S: |
| case AArch64::FCMGE_PPzZ0_D: |
| case AArch64::FCMGE_PPzZ0_H: |
| case AArch64::FCMGE_PPzZ0_S: |
| case AArch64::FCMGT_PPzZ0_D: |
| case AArch64::FCMGT_PPzZ0_H: |
| case AArch64::FCMGT_PPzZ0_S: |
| case AArch64::FCMLE_PPzZ0_D: |
| case AArch64::FCMLE_PPzZ0_H: |
| case AArch64::FCMLE_PPzZ0_S: |
| case AArch64::FCMLT_PPzZ0_D: |
| case AArch64::FCMLT_PPzZ0_H: |
| case AArch64::FCMLT_PPzZ0_S: |
| case AArch64::FCMNE_PPzZ0_D: |
| case AArch64::FCMNE_PPzZ0_H: |
| case AArch64::FCMNE_PPzZ0_S: { |
| // op: Pd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(15); |
| Value |= op; |
| // op: Pg |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(7); |
| op <<= 10; |
| Value |= op; |
| // op: Zn |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| break; |
| } |
| case AArch64::CMPEQ_PPzZI_B: |
| case AArch64::CMPEQ_PPzZI_D: |
| case AArch64::CMPEQ_PPzZI_H: |
| case AArch64::CMPEQ_PPzZI_S: |
| case AArch64::CMPGE_PPzZI_B: |
| case AArch64::CMPGE_PPzZI_D: |
| case AArch64::CMPGE_PPzZI_H: |
| case AArch64::CMPGE_PPzZI_S: |
| case AArch64::CMPGT_PPzZI_B: |
| case AArch64::CMPGT_PPzZI_D: |
| case AArch64::CMPGT_PPzZI_H: |
| case AArch64::CMPGT_PPzZI_S: |
| case AArch64::CMPLE_PPzZI_B: |
| case AArch64::CMPLE_PPzZI_D: |
| case AArch64::CMPLE_PPzZI_H: |
| case AArch64::CMPLE_PPzZI_S: |
| case AArch64::CMPLT_PPzZI_B: |
| case AArch64::CMPLT_PPzZI_D: |
| case AArch64::CMPLT_PPzZI_H: |
| case AArch64::CMPLT_PPzZI_S: |
| case AArch64::CMPNE_PPzZI_B: |
| case AArch64::CMPNE_PPzZI_D: |
| case AArch64::CMPNE_PPzZI_H: |
| case AArch64::CMPNE_PPzZI_S: { |
| // op: Pd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(15); |
| Value |= op; |
| // op: Pg |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(7); |
| op <<= 10; |
| Value |= op; |
| // op: Zn |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: imm5 |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 16; |
| Value |= op; |
| break; |
| } |
| case AArch64::CMPHI_PPzZI_B: |
| case AArch64::CMPHI_PPzZI_D: |
| case AArch64::CMPHI_PPzZI_H: |
| case AArch64::CMPHI_PPzZI_S: |
| case AArch64::CMPHS_PPzZI_B: |
| case AArch64::CMPHS_PPzZI_D: |
| case AArch64::CMPHS_PPzZI_H: |
| case AArch64::CMPHS_PPzZI_S: |
| case AArch64::CMPLO_PPzZI_B: |
| case AArch64::CMPLO_PPzZI_D: |
| case AArch64::CMPLO_PPzZI_H: |
| case AArch64::CMPLO_PPzZI_S: |
| case AArch64::CMPLS_PPzZI_B: |
| case AArch64::CMPLS_PPzZI_D: |
| case AArch64::CMPLS_PPzZI_H: |
| case AArch64::CMPLS_PPzZI_S: { |
| // op: Pd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(15); |
| Value |= op; |
| // op: Pg |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(7); |
| op <<= 10; |
| Value |= op; |
| // op: Zn |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: imm7 |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(127); |
| op <<= 14; |
| Value |= op; |
| break; |
| } |
| case AArch64::BRKA_PPmP: |
| case AArch64::BRKB_PPmP: { |
| // op: Pd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(15); |
| Value |= op; |
| // op: Pg |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(15); |
| op <<= 10; |
| Value |= op; |
| // op: Pn |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(15); |
| op <<= 5; |
| Value |= op; |
| break; |
| } |
| case AArch64::TRN1_PPP_B: |
| case AArch64::TRN1_PPP_D: |
| case AArch64::TRN1_PPP_H: |
| case AArch64::TRN1_PPP_S: |
| case AArch64::TRN2_PPP_B: |
| case AArch64::TRN2_PPP_D: |
| case AArch64::TRN2_PPP_H: |
| case AArch64::TRN2_PPP_S: |
| case AArch64::UZP1_PPP_B: |
| case AArch64::UZP1_PPP_D: |
| case AArch64::UZP1_PPP_H: |
| case AArch64::UZP1_PPP_S: |
| case AArch64::UZP2_PPP_B: |
| case AArch64::UZP2_PPP_D: |
| case AArch64::UZP2_PPP_H: |
| case AArch64::UZP2_PPP_S: |
| case AArch64::ZIP1_PPP_B: |
| case AArch64::ZIP1_PPP_D: |
| case AArch64::ZIP1_PPP_H: |
| case AArch64::ZIP1_PPP_S: |
| case AArch64::ZIP2_PPP_B: |
| case AArch64::ZIP2_PPP_D: |
| case AArch64::ZIP2_PPP_H: |
| case AArch64::ZIP2_PPP_S: { |
| // op: Pd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(15); |
| Value |= op; |
| // op: Pm |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(15); |
| op <<= 16; |
| Value |= op; |
| // op: Pn |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(15); |
| op <<= 5; |
| Value |= op; |
| break; |
| } |
| case AArch64::PUNPKHI_PP: |
| case AArch64::PUNPKLO_PP: |
| case AArch64::REV_PP_B: |
| case AArch64::REV_PP_D: |
| case AArch64::REV_PP_H: |
| case AArch64::REV_PP_S: { |
| // op: Pd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(15); |
| Value |= op; |
| // op: Pn |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(15); |
| op <<= 5; |
| Value |= op; |
| break; |
| } |
| case AArch64::WHILEGE_PWW_B: |
| case AArch64::WHILEGE_PWW_D: |
| case AArch64::WHILEGE_PWW_H: |
| case AArch64::WHILEGE_PWW_S: |
| case AArch64::WHILEGE_PXX_B: |
| case AArch64::WHILEGE_PXX_D: |
| case AArch64::WHILEGE_PXX_H: |
| case AArch64::WHILEGE_PXX_S: |
| case AArch64::WHILEGT_PWW_B: |
| case AArch64::WHILEGT_PWW_D: |
| case AArch64::WHILEGT_PWW_H: |
| case AArch64::WHILEGT_PWW_S: |
| case AArch64::WHILEGT_PXX_B: |
| case AArch64::WHILEGT_PXX_D: |
| case AArch64::WHILEGT_PXX_H: |
| case AArch64::WHILEGT_PXX_S: |
| case AArch64::WHILEHI_PWW_B: |
| case AArch64::WHILEHI_PWW_D: |
| case AArch64::WHILEHI_PWW_H: |
| case AArch64::WHILEHI_PWW_S: |
| case AArch64::WHILEHI_PXX_B: |
| case AArch64::WHILEHI_PXX_D: |
| case AArch64::WHILEHI_PXX_H: |
| case AArch64::WHILEHI_PXX_S: |
| case AArch64::WHILEHS_PWW_B: |
| case AArch64::WHILEHS_PWW_D: |
| case AArch64::WHILEHS_PWW_H: |
| case AArch64::WHILEHS_PWW_S: |
| case AArch64::WHILEHS_PXX_B: |
| case AArch64::WHILEHS_PXX_D: |
| case AArch64::WHILEHS_PXX_H: |
| case AArch64::WHILEHS_PXX_S: |
| case AArch64::WHILELE_PWW_B: |
| case AArch64::WHILELE_PWW_D: |
| case AArch64::WHILELE_PWW_H: |
| case AArch64::WHILELE_PWW_S: |
| case AArch64::WHILELE_PXX_B: |
| case AArch64::WHILELE_PXX_D: |
| case AArch64::WHILELE_PXX_H: |
| case AArch64::WHILELE_PXX_S: |
| case AArch64::WHILELO_PWW_B: |
| case AArch64::WHILELO_PWW_D: |
| case AArch64::WHILELO_PWW_H: |
| case AArch64::WHILELO_PWW_S: |
| case AArch64::WHILELO_PXX_B: |
| case AArch64::WHILELO_PXX_D: |
| case AArch64::WHILELO_PXX_H: |
| case AArch64::WHILELO_PXX_S: |
| case AArch64::WHILELS_PWW_B: |
| case AArch64::WHILELS_PWW_D: |
| case AArch64::WHILELS_PWW_H: |
| case AArch64::WHILELS_PWW_S: |
| case AArch64::WHILELS_PXX_B: |
| case AArch64::WHILELS_PXX_D: |
| case AArch64::WHILELS_PXX_H: |
| case AArch64::WHILELS_PXX_S: |
| case AArch64::WHILELT_PWW_B: |
| case AArch64::WHILELT_PWW_D: |
| case AArch64::WHILELT_PWW_H: |
| case AArch64::WHILELT_PWW_S: |
| case AArch64::WHILELT_PXX_B: |
| case AArch64::WHILELT_PXX_D: |
| case AArch64::WHILELT_PXX_H: |
| case AArch64::WHILELT_PXX_S: |
| case AArch64::WHILERW_PXX_B: |
| case AArch64::WHILERW_PXX_D: |
| case AArch64::WHILERW_PXX_H: |
| case AArch64::WHILERW_PXX_S: |
| case AArch64::WHILEWR_PXX_B: |
| case AArch64::WHILEWR_PXX_D: |
| case AArch64::WHILEWR_PXX_H: |
| case AArch64::WHILEWR_PXX_S: { |
| // op: Pd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(15); |
| Value |= op; |
| // op: Rm |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 16; |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| break; |
| } |
| case AArch64::PTRUES_B: |
| case AArch64::PTRUES_D: |
| case AArch64::PTRUES_H: |
| case AArch64::PTRUES_S: |
| case AArch64::PTRUE_B: |
| case AArch64::PTRUE_D: |
| case AArch64::PTRUE_H: |
| case AArch64::PTRUE_S: { |
| // op: Pd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(15); |
| Value |= op; |
| // op: pattern |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| break; |
| } |
| case AArch64::BRKNS_PPzP: |
| case AArch64::BRKN_PPzP: { |
| // op: Pdm |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(15); |
| Value |= op; |
| // op: Pg |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(15); |
| op <<= 10; |
| Value |= op; |
| // op: Pn |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(15); |
| op <<= 5; |
| Value |= op; |
| break; |
| } |
| case AArch64::PFIRST_B: |
| case AArch64::PNEXT_B: |
| case AArch64::PNEXT_D: |
| case AArch64::PNEXT_H: |
| case AArch64::PNEXT_S: { |
| // op: Pdn |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(15); |
| Value |= op; |
| // op: Pg |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(15); |
| op <<= 5; |
| Value |= op; |
| break; |
| } |
| case AArch64::PTEST_PP: { |
| // op: Pg |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(15); |
| op <<= 10; |
| Value |= op; |
| // op: Pn |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(15); |
| op <<= 5; |
| Value |= op; |
| break; |
| } |
| case AArch64::CNTP_XPP_B: |
| case AArch64::CNTP_XPP_D: |
| case AArch64::CNTP_XPP_H: |
| case AArch64::CNTP_XPP_S: { |
| // op: Pg |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(15); |
| op <<= 10; |
| Value |= op; |
| // op: Pn |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(15); |
| op <<= 5; |
| Value |= op; |
| // op: Rd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| break; |
| } |
| case AArch64::SEL_ZPZZ_B: |
| case AArch64::SEL_ZPZZ_D: |
| case AArch64::SEL_ZPZZ_H: |
| case AArch64::SEL_ZPZZ_S: { |
| // op: Pg |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(15); |
| op <<= 10; |
| Value |= op; |
| // op: Zd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Zm |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 16; |
| Value |= op; |
| // op: Zn |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| break; |
| } |
| case AArch64::LASTA_RPZ_B: |
| case AArch64::LASTA_RPZ_D: |
| case AArch64::LASTA_RPZ_H: |
| case AArch64::LASTA_RPZ_S: |
| case AArch64::LASTB_RPZ_B: |
| case AArch64::LASTB_RPZ_D: |
| case AArch64::LASTB_RPZ_H: |
| case AArch64::LASTB_RPZ_S: { |
| // op: Pg |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(7); |
| op <<= 10; |
| Value |= op; |
| // op: Rd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Zn |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| break; |
| } |
| case AArch64::CLASTA_RPZ_B: |
| case AArch64::CLASTA_RPZ_D: |
| case AArch64::CLASTA_RPZ_H: |
| case AArch64::CLASTA_RPZ_S: |
| case AArch64::CLASTB_RPZ_B: |
| case AArch64::CLASTB_RPZ_D: |
| case AArch64::CLASTB_RPZ_H: |
| case AArch64::CLASTB_RPZ_S: { |
| // op: Pg |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(7); |
| op <<= 10; |
| Value |= op; |
| // op: Rdn |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Zm |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| break; |
| } |
| case AArch64::LD2B: |
| case AArch64::LD2D: |
| case AArch64::LD2H: |
| case AArch64::LD2W: |
| case AArch64::LD3B: |
| case AArch64::LD3D: |
| case AArch64::LD3H: |
| case AArch64::LD3W: |
| case AArch64::LD4B: |
| case AArch64::LD4D: |
| case AArch64::LD4H: |
| case AArch64::LD4W: |
| case AArch64::LDNT1B_ZRR: |
| case AArch64::LDNT1D_ZRR: |
| case AArch64::LDNT1H_ZRR: |
| case AArch64::LDNT1W_ZRR: |
| case AArch64::ST1B: |
| case AArch64::ST1B_D: |
| case AArch64::ST1B_H: |
| case AArch64::ST1B_S: |
| case AArch64::ST1D: |
| case AArch64::ST1H: |
| case AArch64::ST1H_D: |
| case AArch64::ST1H_S: |
| case AArch64::ST1W: |
| case AArch64::ST1W_D: |
| case AArch64::ST2B: |
| case AArch64::ST2D: |
| case AArch64::ST2H: |
| case AArch64::ST2W: |
| case AArch64::ST3B: |
| case AArch64::ST3D: |
| case AArch64::ST3H: |
| case AArch64::ST3W: |
| case AArch64::ST4B: |
| case AArch64::ST4D: |
| case AArch64::ST4H: |
| case AArch64::ST4W: |
| case AArch64::STNT1B_ZRR: |
| case AArch64::STNT1D_ZRR: |
| case AArch64::STNT1H_ZRR: |
| case AArch64::STNT1W_ZRR: { |
| // op: Pg |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(7); |
| op <<= 10; |
| Value |= op; |
| // op: Rm |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 16; |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: Zt |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| break; |
| } |
| case AArch64::LDNT1B_ZZR_D_REAL: |
| case AArch64::LDNT1B_ZZR_S_REAL: |
| case AArch64::LDNT1D_ZZR_D_REAL: |
| case AArch64::LDNT1H_ZZR_D_REAL: |
| case AArch64::LDNT1H_ZZR_S_REAL: |
| case AArch64::LDNT1SB_ZZR_D_REAL: |
| case AArch64::LDNT1SB_ZZR_S_REAL: |
| case AArch64::LDNT1SH_ZZR_D_REAL: |
| case AArch64::LDNT1SH_ZZR_S_REAL: |
| case AArch64::LDNT1SW_ZZR_D_REAL: |
| case AArch64::LDNT1W_ZZR_D_REAL: |
| case AArch64::LDNT1W_ZZR_S_REAL: |
| case AArch64::STNT1B_ZZR_D_REAL: |
| case AArch64::STNT1B_ZZR_S_REAL: |
| case AArch64::STNT1D_ZZR_D_REAL: |
| case AArch64::STNT1H_ZZR_D_REAL: |
| case AArch64::STNT1H_ZZR_S_REAL: |
| case AArch64::STNT1W_ZZR_D_REAL: |
| case AArch64::STNT1W_ZZR_S_REAL: { |
| // op: Pg |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(7); |
| op <<= 10; |
| Value |= op; |
| // op: Rm |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 16; |
| Value |= op; |
| // op: Zn |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: Zt |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| break; |
| } |
| case AArch64::GLD1B_D_REAL: |
| case AArch64::GLD1B_D_SXTW_REAL: |
| case AArch64::GLD1B_D_UXTW_REAL: |
| case AArch64::GLD1B_S_SXTW_REAL: |
| case AArch64::GLD1B_S_UXTW_REAL: |
| case AArch64::GLD1D_REAL: |
| case AArch64::GLD1D_SCALED_REAL: |
| case AArch64::GLD1D_SXTW_REAL: |
| case AArch64::GLD1D_SXTW_SCALED_REAL: |
| case AArch64::GLD1D_UXTW_REAL: |
| case AArch64::GLD1D_UXTW_SCALED_REAL: |
| case AArch64::GLD1H_D_REAL: |
| case AArch64::GLD1H_D_SCALED_REAL: |
| case AArch64::GLD1H_D_SXTW_REAL: |
| case AArch64::GLD1H_D_SXTW_SCALED_REAL: |
| case AArch64::GLD1H_D_UXTW_REAL: |
| case AArch64::GLD1H_D_UXTW_SCALED_REAL: |
| case AArch64::GLD1H_S_SXTW_REAL: |
| case AArch64::GLD1H_S_SXTW_SCALED_REAL: |
| case AArch64::GLD1H_S_UXTW_REAL: |
| case AArch64::GLD1H_S_UXTW_SCALED_REAL: |
| case AArch64::GLD1SB_D_REAL: |
| case AArch64::GLD1SB_D_SXTW_REAL: |
| case AArch64::GLD1SB_D_UXTW_REAL: |
| case AArch64::GLD1SB_S_SXTW_REAL: |
| case AArch64::GLD1SB_S_UXTW_REAL: |
| case AArch64::GLD1SH_D_REAL: |
| case AArch64::GLD1SH_D_SCALED_REAL: |
| case AArch64::GLD1SH_D_SXTW_REAL: |
| case AArch64::GLD1SH_D_SXTW_SCALED_REAL: |
| case AArch64::GLD1SH_D_UXTW_REAL: |
| case AArch64::GLD1SH_D_UXTW_SCALED_REAL: |
| case AArch64::GLD1SH_S_SXTW_REAL: |
| case AArch64::GLD1SH_S_SXTW_SCALED_REAL: |
| case AArch64::GLD1SH_S_UXTW_REAL: |
| case AArch64::GLD1SH_S_UXTW_SCALED_REAL: |
| case AArch64::GLD1SW_D_REAL: |
| case AArch64::GLD1SW_D_SCALED_REAL: |
| case AArch64::GLD1SW_D_SXTW_REAL: |
| case AArch64::GLD1SW_D_SXTW_SCALED_REAL: |
| case AArch64::GLD1SW_D_UXTW_REAL: |
| case AArch64::GLD1SW_D_UXTW_SCALED_REAL: |
| case AArch64::GLD1W_D_REAL: |
| case AArch64::GLD1W_D_SCALED_REAL: |
| case AArch64::GLD1W_D_SXTW_REAL: |
| case AArch64::GLD1W_D_SXTW_SCALED_REAL: |
| case AArch64::GLD1W_D_UXTW_REAL: |
| case AArch64::GLD1W_D_UXTW_SCALED_REAL: |
| case AArch64::GLD1W_SXTW_REAL: |
| case AArch64::GLD1W_SXTW_SCALED_REAL: |
| case AArch64::GLD1W_UXTW_REAL: |
| case AArch64::GLD1W_UXTW_SCALED_REAL: |
| case AArch64::GLDFF1B_D_REAL: |
| case AArch64::GLDFF1B_D_SXTW_REAL: |
| case AArch64::GLDFF1B_D_UXTW_REAL: |
| case AArch64::GLDFF1B_S_SXTW_REAL: |
| case AArch64::GLDFF1B_S_UXTW_REAL: |
| case AArch64::GLDFF1D_REAL: |
| case AArch64::GLDFF1D_SCALED_REAL: |
| case AArch64::GLDFF1D_SXTW_REAL: |
| case AArch64::GLDFF1D_SXTW_SCALED_REAL: |
| case AArch64::GLDFF1D_UXTW_REAL: |
| case AArch64::GLDFF1D_UXTW_SCALED_REAL: |
| case AArch64::GLDFF1H_D_REAL: |
| case AArch64::GLDFF1H_D_SCALED_REAL: |
| case AArch64::GLDFF1H_D_SXTW_REAL: |
| case AArch64::GLDFF1H_D_SXTW_SCALED_REAL: |
| case AArch64::GLDFF1H_D_UXTW_REAL: |
| case AArch64::GLDFF1H_D_UXTW_SCALED_REAL: |
| case AArch64::GLDFF1H_S_SXTW_REAL: |
| case AArch64::GLDFF1H_S_SXTW_SCALED_REAL: |
| case AArch64::GLDFF1H_S_UXTW_REAL: |
| case AArch64::GLDFF1H_S_UXTW_SCALED_REAL: |
| case AArch64::GLDFF1SB_D_REAL: |
| case AArch64::GLDFF1SB_D_SXTW_REAL: |
| case AArch64::GLDFF1SB_D_UXTW_REAL: |
| case AArch64::GLDFF1SB_S_SXTW_REAL: |
| case AArch64::GLDFF1SB_S_UXTW_REAL: |
| case AArch64::GLDFF1SH_D_REAL: |
| case AArch64::GLDFF1SH_D_SCALED_REAL: |
| case AArch64::GLDFF1SH_D_SXTW_REAL: |
| case AArch64::GLDFF1SH_D_SXTW_SCALED_REAL: |
| case AArch64::GLDFF1SH_D_UXTW_REAL: |
| case AArch64::GLDFF1SH_D_UXTW_SCALED_REAL: |
| case AArch64::GLDFF1SH_S_SXTW_REAL: |
| case AArch64::GLDFF1SH_S_SXTW_SCALED_REAL: |
| case AArch64::GLDFF1SH_S_UXTW_REAL: |
| case AArch64::GLDFF1SH_S_UXTW_SCALED_REAL: |
| case AArch64::GLDFF1SW_D_REAL: |
| case AArch64::GLDFF1SW_D_SCALED_REAL: |
| case AArch64::GLDFF1SW_D_SXTW_REAL: |
| case AArch64::GLDFF1SW_D_SXTW_SCALED_REAL: |
| case AArch64::GLDFF1SW_D_UXTW_REAL: |
| case AArch64::GLDFF1SW_D_UXTW_SCALED_REAL: |
| case AArch64::GLDFF1W_D_REAL: |
| case AArch64::GLDFF1W_D_SCALED_REAL: |
| case AArch64::GLDFF1W_D_SXTW_REAL: |
| case AArch64::GLDFF1W_D_SXTW_SCALED_REAL: |
| case AArch64::GLDFF1W_D_UXTW_REAL: |
| case AArch64::GLDFF1W_D_UXTW_SCALED_REAL: |
| case AArch64::GLDFF1W_SXTW_REAL: |
| case AArch64::GLDFF1W_SXTW_SCALED_REAL: |
| case AArch64::GLDFF1W_UXTW_REAL: |
| case AArch64::GLDFF1W_UXTW_SCALED_REAL: |
| case AArch64::SST1B_D_REAL: |
| case AArch64::SST1B_D_SXTW: |
| case AArch64::SST1B_D_UXTW: |
| case AArch64::SST1B_S_SXTW: |
| case AArch64::SST1B_S_UXTW: |
| case AArch64::SST1D_REAL: |
| case AArch64::SST1D_SCALED_SCALED_REAL: |
| case AArch64::SST1D_SXTW: |
| case AArch64::SST1D_SXTW_SCALED: |
| case AArch64::SST1D_UXTW: |
| case AArch64::SST1D_UXTW_SCALED: |
| case AArch64::SST1H_D_REAL: |
| case AArch64::SST1H_D_SCALED_SCALED_REAL: |
| case AArch64::SST1H_D_SXTW: |
| case AArch64::SST1H_D_SXTW_SCALED: |
| case AArch64::SST1H_D_UXTW: |
| case AArch64::SST1H_D_UXTW_SCALED: |
| case AArch64::SST1H_S_SXTW: |
| case AArch64::SST1H_S_SXTW_SCALED: |
| case AArch64::SST1H_S_UXTW: |
| case AArch64::SST1H_S_UXTW_SCALED: |
| case AArch64::SST1W_D_REAL: |
| case AArch64::SST1W_D_SCALED_SCALED_REAL: |
| case AArch64::SST1W_D_SXTW: |
| case AArch64::SST1W_D_SXTW_SCALED: |
| case AArch64::SST1W_D_UXTW: |
| case AArch64::SST1W_D_UXTW_SCALED: |
| case AArch64::SST1W_SXTW: |
| case AArch64::SST1W_SXTW_SCALED: |
| case AArch64::SST1W_UXTW: |
| case AArch64::SST1W_UXTW_SCALED: { |
| // op: Pg |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(7); |
| op <<= 10; |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: Zm |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 16; |
| Value |= op; |
| // op: Zt |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| break; |
| } |
| case AArch64::PRFB_D_SCALED: |
| case AArch64::PRFB_D_SXTW_SCALED: |
| case AArch64::PRFB_D_UXTW_SCALED: |
| case AArch64::PRFB_S_SXTW_SCALED: |
| case AArch64::PRFB_S_UXTW_SCALED: |
| case AArch64::PRFD_D_SCALED: |
| case AArch64::PRFD_D_SXTW_SCALED: |
| case AArch64::PRFD_D_UXTW_SCALED: |
| case AArch64::PRFD_S_SXTW_SCALED: |
| case AArch64::PRFD_S_UXTW_SCALED: |
| case AArch64::PRFH_D_SCALED: |
| case AArch64::PRFH_D_SXTW_SCALED: |
| case AArch64::PRFH_D_UXTW_SCALED: |
| case AArch64::PRFH_S_SXTW_SCALED: |
| case AArch64::PRFH_S_UXTW_SCALED: |
| case AArch64::PRFW_D_SCALED: |
| case AArch64::PRFW_D_SXTW_SCALED: |
| case AArch64::PRFW_D_UXTW_SCALED: |
| case AArch64::PRFW_S_SXTW_SCALED: |
| case AArch64::PRFW_S_UXTW_SCALED: { |
| // op: Pg |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(7); |
| op <<= 10; |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: Zm |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 16; |
| Value |= op; |
| // op: prfop |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(15); |
| Value |= op; |
| break; |
| } |
| case AArch64::LD1B_D_IMM: |
| case AArch64::LD1B_H_IMM: |
| case AArch64::LD1B_IMM: |
| case AArch64::LD1B_S_IMM: |
| case AArch64::LD1D_IMM: |
| case AArch64::LD1H_D_IMM: |
| case AArch64::LD1H_IMM: |
| case AArch64::LD1H_S_IMM: |
| case AArch64::LD1SB_D_IMM: |
| case AArch64::LD1SB_H_IMM: |
| case AArch64::LD1SB_S_IMM: |
| case AArch64::LD1SH_D_IMM: |
| case AArch64::LD1SH_S_IMM: |
| case AArch64::LD1SW_D_IMM: |
| case AArch64::LD1W_D_IMM: |
| case AArch64::LD1W_IMM: |
| case AArch64::LDNF1B_D_IMM: |
| case AArch64::LDNF1B_H_IMM: |
| case AArch64::LDNF1B_IMM: |
| case AArch64::LDNF1B_S_IMM: |
| case AArch64::LDNF1D_IMM: |
| case AArch64::LDNF1H_D_IMM: |
| case AArch64::LDNF1H_IMM: |
| case AArch64::LDNF1H_S_IMM: |
| case AArch64::LDNF1SB_D_IMM: |
| case AArch64::LDNF1SB_H_IMM: |
| case AArch64::LDNF1SB_S_IMM: |
| case AArch64::LDNF1SH_D_IMM: |
| case AArch64::LDNF1SH_S_IMM: |
| case AArch64::LDNF1SW_D_IMM: |
| case AArch64::LDNF1W_D_IMM: |
| case AArch64::LDNF1W_IMM: |
| case AArch64::ST1B_D_IMM: |
| case AArch64::ST1B_H_IMM: |
| case AArch64::ST1B_IMM: |
| case AArch64::ST1B_S_IMM: |
| case AArch64::ST1D_IMM: |
| case AArch64::ST1H_D_IMM: |
| case AArch64::ST1H_IMM: |
| case AArch64::ST1H_S_IMM: |
| case AArch64::ST1W_D_IMM: |
| case AArch64::ST1W_IMM: |
| case AArch64::ST2B_IMM: |
| case AArch64::ST2D_IMM: |
| case AArch64::ST2H_IMM: |
| case AArch64::ST2W_IMM: |
| case AArch64::ST3B_IMM: |
| case AArch64::ST3D_IMM: |
| case AArch64::ST3H_IMM: |
| case AArch64::ST3W_IMM: |
| case AArch64::ST4B_IMM: |
| case AArch64::ST4D_IMM: |
| case AArch64::ST4H_IMM: |
| case AArch64::ST4W_IMM: |
| case AArch64::STNT1B_ZRI: |
| case AArch64::STNT1D_ZRI: |
| case AArch64::STNT1H_ZRI: |
| case AArch64::STNT1W_ZRI: { |
| // op: Pg |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(7); |
| op <<= 10; |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: Zt |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: imm4 |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(15); |
| op <<= 16; |
| Value |= op; |
| break; |
| } |
| case AArch64::LD1RB_D_IMM: |
| case AArch64::LD1RB_H_IMM: |
| case AArch64::LD1RB_IMM: |
| case AArch64::LD1RB_S_IMM: |
| case AArch64::LD1RD_IMM: |
| case AArch64::LD1RH_D_IMM: |
| case AArch64::LD1RH_IMM: |
| case AArch64::LD1RH_S_IMM: |
| case AArch64::LD1RSB_D_IMM: |
| case AArch64::LD1RSB_H_IMM: |
| case AArch64::LD1RSB_S_IMM: |
| case AArch64::LD1RSH_D_IMM: |
| case AArch64::LD1RSH_S_IMM: |
| case AArch64::LD1RSW_IMM: |
| case AArch64::LD1RW_D_IMM: |
| case AArch64::LD1RW_IMM: { |
| // op: Pg |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(7); |
| op <<= 10; |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: Zt |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: imm6 |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(63); |
| op <<= 16; |
| Value |= op; |
| break; |
| } |
| case AArch64::ANDV_VPZ_B: |
| case AArch64::ANDV_VPZ_D: |
| case AArch64::ANDV_VPZ_H: |
| case AArch64::ANDV_VPZ_S: |
| case AArch64::EORV_VPZ_B: |
| case AArch64::EORV_VPZ_D: |
| case AArch64::EORV_VPZ_H: |
| case AArch64::EORV_VPZ_S: |
| case AArch64::LASTA_VPZ_B: |
| case AArch64::LASTA_VPZ_D: |
| case AArch64::LASTA_VPZ_H: |
| case AArch64::LASTA_VPZ_S: |
| case AArch64::LASTB_VPZ_B: |
| case AArch64::LASTB_VPZ_D: |
| case AArch64::LASTB_VPZ_H: |
| case AArch64::LASTB_VPZ_S: |
| case AArch64::ORV_VPZ_B: |
| case AArch64::ORV_VPZ_D: |
| case AArch64::ORV_VPZ_H: |
| case AArch64::ORV_VPZ_S: |
| case AArch64::SADDV_VPZ_B: |
| case AArch64::SADDV_VPZ_H: |
| case AArch64::SADDV_VPZ_S: |
| case AArch64::SMAXV_VPZ_B: |
| case AArch64::SMAXV_VPZ_D: |
| case AArch64::SMAXV_VPZ_H: |
| case AArch64::SMAXV_VPZ_S: |
| case AArch64::SMINV_VPZ_B: |
| case AArch64::SMINV_VPZ_D: |
| case AArch64::SMINV_VPZ_H: |
| case AArch64::SMINV_VPZ_S: |
| case AArch64::UADDV_VPZ_B: |
| case AArch64::UADDV_VPZ_D: |
| case AArch64::UADDV_VPZ_H: |
| case AArch64::UADDV_VPZ_S: |
| case AArch64::UMAXV_VPZ_B: |
| case AArch64::UMAXV_VPZ_D: |
| case AArch64::UMAXV_VPZ_H: |
| case AArch64::UMAXV_VPZ_S: |
| case AArch64::UMINV_VPZ_B: |
| case AArch64::UMINV_VPZ_D: |
| case AArch64::UMINV_VPZ_H: |
| case AArch64::UMINV_VPZ_S: { |
| // op: Pg |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(7); |
| op <<= 10; |
| Value |= op; |
| // op: Vd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Zn |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| break; |
| } |
| case AArch64::CLASTA_VPZ_B: |
| case AArch64::CLASTA_VPZ_D: |
| case AArch64::CLASTA_VPZ_H: |
| case AArch64::CLASTA_VPZ_S: |
| case AArch64::CLASTB_VPZ_B: |
| case AArch64::CLASTB_VPZ_D: |
| case AArch64::CLASTB_VPZ_H: |
| case AArch64::CLASTB_VPZ_S: |
| case AArch64::FADDA_VPZ_D: |
| case AArch64::FADDA_VPZ_H: |
| case AArch64::FADDA_VPZ_S: { |
| // op: Pg |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(7); |
| op <<= 10; |
| Value |= op; |
| // op: Vdn |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Zm |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| break; |
| } |
| case AArch64::FMAD_ZPmZZ_D: |
| case AArch64::FMAD_ZPmZZ_H: |
| case AArch64::FMAD_ZPmZZ_S: |
| case AArch64::FMSB_ZPmZZ_D: |
| case AArch64::FMSB_ZPmZZ_H: |
| case AArch64::FMSB_ZPmZZ_S: |
| case AArch64::FNMAD_ZPmZZ_D: |
| case AArch64::FNMAD_ZPmZZ_H: |
| case AArch64::FNMAD_ZPmZZ_S: |
| case AArch64::FNMSB_ZPmZZ_D: |
| case AArch64::FNMSB_ZPmZZ_H: |
| case AArch64::FNMSB_ZPmZZ_S: { |
| // op: Pg |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(7); |
| op <<= 10; |
| Value |= op; |
| // op: Za |
| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 16; |
| Value |= op; |
| // op: Zdn |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Zm |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| break; |
| } |
| case AArch64::COMPACT_ZPZ_D: |
| case AArch64::COMPACT_ZPZ_S: |
| case AArch64::MOVPRFX_ZPzZ_B: |
| case AArch64::MOVPRFX_ZPzZ_D: |
| case AArch64::MOVPRFX_ZPzZ_H: |
| case AArch64::MOVPRFX_ZPzZ_S: { |
| // op: Pg |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(7); |
| op <<= 10; |
| Value |= op; |
| // op: Zd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Zn |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| break; |
| } |
| case AArch64::FMLA_ZPmZZ_D: |
| case AArch64::FMLA_ZPmZZ_H: |
| case AArch64::FMLA_ZPmZZ_S: |
| case AArch64::FMLS_ZPmZZ_D: |
| case AArch64::FMLS_ZPmZZ_H: |
| case AArch64::FMLS_ZPmZZ_S: |
| case AArch64::FNMLA_ZPmZZ_D: |
| case AArch64::FNMLA_ZPmZZ_H: |
| case AArch64::FNMLA_ZPmZZ_S: |
| case AArch64::FNMLS_ZPmZZ_D: |
| case AArch64::FNMLS_ZPmZZ_H: |
| case AArch64::FNMLS_ZPmZZ_S: |
| case AArch64::MLA_ZPmZZ_B: |
| case AArch64::MLA_ZPmZZ_D: |
| case AArch64::MLA_ZPmZZ_H: |
| case AArch64::MLA_ZPmZZ_S: |
| case AArch64::MLS_ZPmZZ_B: |
| case AArch64::MLS_ZPmZZ_D: |
| case AArch64::MLS_ZPmZZ_H: |
| case AArch64::MLS_ZPmZZ_S: { |
| // op: Pg |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(7); |
| op <<= 10; |
| Value |= op; |
| // op: Zda |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Zm |
| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 16; |
| Value |= op; |
| // op: Zn |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| break; |
| } |
| case AArch64::MAD_ZPmZZ_B: |
| case AArch64::MAD_ZPmZZ_D: |
| case AArch64::MAD_ZPmZZ_H: |
| case AArch64::MAD_ZPmZZ_S: |
| case AArch64::MSB_ZPmZZ_B: |
| case AArch64::MSB_ZPmZZ_D: |
| case AArch64::MSB_ZPmZZ_H: |
| case AArch64::MSB_ZPmZZ_S: { |
| // op: Pg |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(7); |
| op <<= 10; |
| Value |= op; |
| // op: Zdn |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Za |
| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: Zm |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 16; |
| Value |= op; |
| break; |
| } |
| case AArch64::ADD_ZPmZ_B: |
| case AArch64::ADD_ZPmZ_D: |
| case AArch64::ADD_ZPmZ_H: |
| case AArch64::ADD_ZPmZ_S: |
| case AArch64::AND_ZPmZ_B: |
| case AArch64::AND_ZPmZ_D: |
| case AArch64::AND_ZPmZ_H: |
| case AArch64::AND_ZPmZ_S: |
| case AArch64::ASRR_ZPmZ_B: |
| case AArch64::ASRR_ZPmZ_D: |
| case AArch64::ASRR_ZPmZ_H: |
| case AArch64::ASRR_ZPmZ_S: |
| case AArch64::ASR_WIDE_ZPmZ_B: |
| case AArch64::ASR_WIDE_ZPmZ_H: |
| case AArch64::ASR_WIDE_ZPmZ_S: |
| case AArch64::ASR_ZPmZ_B: |
| case AArch64::ASR_ZPmZ_D: |
| case AArch64::ASR_ZPmZ_H: |
| case AArch64::ASR_ZPmZ_S: |
| case AArch64::BIC_ZPmZ_B: |
| case AArch64::BIC_ZPmZ_D: |
| case AArch64::BIC_ZPmZ_H: |
| case AArch64::BIC_ZPmZ_S: |
| case AArch64::CLASTA_ZPZ_B: |
| case AArch64::CLASTA_ZPZ_D: |
| case AArch64::CLASTA_ZPZ_H: |
| case AArch64::CLASTA_ZPZ_S: |
| case AArch64::CLASTB_ZPZ_B: |
| case AArch64::CLASTB_ZPZ_D: |
| case AArch64::CLASTB_ZPZ_H: |
| case AArch64::CLASTB_ZPZ_S: |
| case AArch64::EOR_ZPmZ_B: |
| case AArch64::EOR_ZPmZ_D: |
| case AArch64::EOR_ZPmZ_H: |
| case AArch64::EOR_ZPmZ_S: |
| case AArch64::FABD_ZPmZ_D: |
| case AArch64::FABD_ZPmZ_H: |
| case AArch64::FABD_ZPmZ_S: |
| case AArch64::FADD_ZPmZ_D: |
| case AArch64::FADD_ZPmZ_H: |
| case AArch64::FADD_ZPmZ_S: |
| case AArch64::FDIVR_ZPmZ_D: |
| case AArch64::FDIVR_ZPmZ_H: |
| case AArch64::FDIVR_ZPmZ_S: |
| case AArch64::FDIV_ZPmZ_D: |
| case AArch64::FDIV_ZPmZ_H: |
| case AArch64::FDIV_ZPmZ_S: |
| case AArch64::FMAXNM_ZPmZ_D: |
| case AArch64::FMAXNM_ZPmZ_H: |
| case AArch64::FMAXNM_ZPmZ_S: |
| case AArch64::FMAX_ZPmZ_D: |
| case AArch64::FMAX_ZPmZ_H: |
| case AArch64::FMAX_ZPmZ_S: |
| case AArch64::FMINNM_ZPmZ_D: |
| case AArch64::FMINNM_ZPmZ_H: |
| case AArch64::FMINNM_ZPmZ_S: |
| case AArch64::FMIN_ZPmZ_D: |
| case AArch64::FMIN_ZPmZ_H: |
| case AArch64::FMIN_ZPmZ_S: |
| case AArch64::FMULX_ZPmZ_D: |
| case AArch64::FMULX_ZPmZ_H: |
| case AArch64::FMULX_ZPmZ_S: |
| case AArch64::FMUL_ZPmZ_D: |
| case AArch64::FMUL_ZPmZ_H: |
| case AArch64::FMUL_ZPmZ_S: |
| case AArch64::FSCALE_ZPmZ_D: |
| case AArch64::FSCALE_ZPmZ_H: |
| case AArch64::FSCALE_ZPmZ_S: |
| case AArch64::FSUBR_ZPmZ_D: |
| case AArch64::FSUBR_ZPmZ_H: |
| case AArch64::FSUBR_ZPmZ_S: |
| case AArch64::FSUB_ZPmZ_D: |
| case AArch64::FSUB_ZPmZ_H: |
| case AArch64::FSUB_ZPmZ_S: |
| case AArch64::LSLR_ZPmZ_B: |
| case AArch64::LSLR_ZPmZ_D: |
| case AArch64::LSLR_ZPmZ_H: |
| case AArch64::LSLR_ZPmZ_S: |
| case AArch64::LSL_WIDE_ZPmZ_B: |
| case AArch64::LSL_WIDE_ZPmZ_H: |
| case AArch64::LSL_WIDE_ZPmZ_S: |
| case AArch64::LSL_ZPmZ_B: |
| case AArch64::LSL_ZPmZ_D: |
| case AArch64::LSL_ZPmZ_H: |
| case AArch64::LSL_ZPmZ_S: |
| case AArch64::LSRR_ZPmZ_B: |
| case AArch64::LSRR_ZPmZ_D: |
| case AArch64::LSRR_ZPmZ_H: |
| case AArch64::LSRR_ZPmZ_S: |
| case AArch64::LSR_WIDE_ZPmZ_B: |
| case AArch64::LSR_WIDE_ZPmZ_H: |
| case AArch64::LSR_WIDE_ZPmZ_S: |
| case AArch64::LSR_ZPmZ_B: |
| case AArch64::LSR_ZPmZ_D: |
| case AArch64::LSR_ZPmZ_H: |
| case AArch64::LSR_ZPmZ_S: |
| case AArch64::MUL_ZPmZ_B: |
| case AArch64::MUL_ZPmZ_D: |
| case AArch64::MUL_ZPmZ_H: |
| case AArch64::MUL_ZPmZ_S: |
| case AArch64::ORR_ZPmZ_B: |
| case AArch64::ORR_ZPmZ_D: |
| case AArch64::ORR_ZPmZ_H: |
| case AArch64::ORR_ZPmZ_S: |
| case AArch64::SABD_ZPmZ_B: |
| case AArch64::SABD_ZPmZ_D: |
| case AArch64::SABD_ZPmZ_H: |
| case AArch64::SABD_ZPmZ_S: |
| case AArch64::SDIVR_ZPmZ_D: |
| case AArch64::SDIVR_ZPmZ_S: |
| case AArch64::SDIV_ZPmZ_D: |
| case AArch64::SDIV_ZPmZ_S: |
| case AArch64::SMAX_ZPmZ_B: |
| case AArch64::SMAX_ZPmZ_D: |
| case AArch64::SMAX_ZPmZ_H: |
| case AArch64::SMAX_ZPmZ_S: |
| case AArch64::SMIN_ZPmZ_B: |
| case AArch64::SMIN_ZPmZ_D: |
| case AArch64::SMIN_ZPmZ_H: |
| case AArch64::SMIN_ZPmZ_S: |
| case AArch64::SMULH_ZPmZ_B: |
| case AArch64::SMULH_ZPmZ_D: |
| case AArch64::SMULH_ZPmZ_H: |
| case AArch64::SMULH_ZPmZ_S: |
| case AArch64::SPLICE_ZPZ_B: |
| case AArch64::SPLICE_ZPZ_D: |
| case AArch64::SPLICE_ZPZ_H: |
| case AArch64::SPLICE_ZPZ_S: |
| case AArch64::SUBR_ZPmZ_B: |
| case AArch64::SUBR_ZPmZ_D: |
| case AArch64::SUBR_ZPmZ_H: |
| case AArch64::SUBR_ZPmZ_S: |
| case AArch64::SUB_ZPmZ_B: |
| case AArch64::SUB_ZPmZ_D: |
| case AArch64::SUB_ZPmZ_H: |
| case AArch64::SUB_ZPmZ_S: |
| case AArch64::UABD_ZPmZ_B: |
| case AArch64::UABD_ZPmZ_D: |
| case AArch64::UABD_ZPmZ_H: |
| case AArch64::UABD_ZPmZ_S: |
| case AArch64::UDIVR_ZPmZ_D: |
| case AArch64::UDIVR_ZPmZ_S: |
| case AArch64::UDIV_ZPmZ_D: |
| case AArch64::UDIV_ZPmZ_S: |
| case AArch64::UMAX_ZPmZ_B: |
| case AArch64::UMAX_ZPmZ_D: |
| case AArch64::UMAX_ZPmZ_H: |
| case AArch64::UMAX_ZPmZ_S: |
| case AArch64::UMIN_ZPmZ_B: |
| case AArch64::UMIN_ZPmZ_D: |
| case AArch64::UMIN_ZPmZ_H: |
| case AArch64::UMIN_ZPmZ_S: |
| case AArch64::UMULH_ZPmZ_B: |
| case AArch64::UMULH_ZPmZ_D: |
| case AArch64::UMULH_ZPmZ_H: |
| case AArch64::UMULH_ZPmZ_S: { |
| // op: Pg |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(7); |
| op <<= 10; |
| Value |= op; |
| // op: Zdn |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Zm |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| break; |
| } |
| case AArch64::FADD_ZPmI_D: |
| case AArch64::FADD_ZPmI_H: |
| case AArch64::FADD_ZPmI_S: |
| case AArch64::FMAXNM_ZPmI_D: |
| case AArch64::FMAXNM_ZPmI_H: |
| case AArch64::FMAXNM_ZPmI_S: |
| case AArch64::FMAX_ZPmI_D: |
| case AArch64::FMAX_ZPmI_H: |
| case AArch64::FMAX_ZPmI_S: |
| case AArch64::FMINNM_ZPmI_D: |
| case AArch64::FMINNM_ZPmI_H: |
| case AArch64::FMINNM_ZPmI_S: |
| case AArch64::FMIN_ZPmI_D: |
| case AArch64::FMIN_ZPmI_H: |
| case AArch64::FMIN_ZPmI_S: |
| case AArch64::FMUL_ZPmI_D: |
| case AArch64::FMUL_ZPmI_H: |
| case AArch64::FMUL_ZPmI_S: |
| case AArch64::FSUBR_ZPmI_D: |
| case AArch64::FSUBR_ZPmI_H: |
| case AArch64::FSUBR_ZPmI_S: |
| case AArch64::FSUB_ZPmI_D: |
| case AArch64::FSUB_ZPmI_H: |
| case AArch64::FSUB_ZPmI_S: { |
| // op: Pg |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(7); |
| op <<= 10; |
| Value |= op; |
| // op: Zdn |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: i1 |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(1); |
| op <<= 5; |
| Value |= op; |
| break; |
| } |
| case AArch64::LSL_ZPmI_H: |
| case AArch64::SQSHLU_ZPmI_H: |
| case AArch64::SQSHL_ZPmI_H: |
| case AArch64::UQSHL_ZPmI_H: { |
| // op: Pg |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(7); |
| op <<= 10; |
| Value |= op; |
| // op: Zdn |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: imm |
| op = getVecShiftL16OpValue(MI, 3, Fixups, STI); |
| op &= UINT64_C(15); |
| op <<= 5; |
| Value |= op; |
| break; |
| } |
| case AArch64::LSL_ZPmI_S: |
| case AArch64::SQSHLU_ZPmI_S: |
| case AArch64::SQSHL_ZPmI_S: |
| case AArch64::UQSHL_ZPmI_S: { |
| // op: Pg |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(7); |
| op <<= 10; |
| Value |= op; |
| // op: Zdn |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: imm |
| op = getVecShiftL32OpValue(MI, 3, Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| break; |
| } |
| case AArch64::LSL_ZPmI_D: |
| case AArch64::SQSHLU_ZPmI_D: |
| case AArch64::SQSHL_ZPmI_D: |
| case AArch64::UQSHL_ZPmI_D: { |
| // op: Pg |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(7); |
| op <<= 10; |
| Value |= op; |
| // op: Zdn |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: imm |
| op = getVecShiftL64OpValue(MI, 3, Fixups, STI); |
| Value |= (op & UINT64_C(32)) << 17; |
| Value |= (op & UINT64_C(31)) << 5; |
| break; |
| } |
| case AArch64::LSL_ZPmI_B: |
| case AArch64::SQSHLU_ZPmI_B: |
| case AArch64::SQSHL_ZPmI_B: |
| case AArch64::UQSHL_ZPmI_B: { |
| // op: Pg |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(7); |
| op <<= 10; |
| Value |= op; |
| // op: Zdn |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: imm |
| op = getVecShiftL8OpValue(MI, 3, Fixups, STI); |
| op &= UINT64_C(7); |
| op <<= 5; |
| Value |= op; |
| break; |
| } |
| case AArch64::ASRD_ZPmI_H: |
| case AArch64::ASR_ZPmI_H: |
| case AArch64::LSR_ZPmI_H: |
| case AArch64::SRSHR_ZPmI_H: |
| case AArch64::URSHR_ZPmI_H: { |
| // op: Pg |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(7); |
| op <<= 10; |
| Value |= op; |
| // op: Zdn |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: imm |
| op = getVecShiftR16OpValue(MI, 3, Fixups, STI); |
| op &= UINT64_C(15); |
| op <<= 5; |
| Value |= op; |
| break; |
| } |
| case AArch64::ASRD_ZPmI_S: |
| case AArch64::ASR_ZPmI_S: |
| case AArch64::LSR_ZPmI_S: |
| case AArch64::SRSHR_ZPmI_S: |
| case AArch64::URSHR_ZPmI_S: { |
| // op: Pg |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(7); |
| op <<= 10; |
| Value |= op; |
| // op: Zdn |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: imm |
| op = getVecShiftR32OpValue(MI, 3, Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| break; |
| } |
| case AArch64::ASRD_ZPmI_D: |
| case AArch64::ASR_ZPmI_D: |
| case AArch64::LSR_ZPmI_D: |
| case AArch64::SRSHR_ZPmI_D: |
| case AArch64::URSHR_ZPmI_D: { |
| // op: Pg |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(7); |
| op <<= 10; |
| Value |= op; |
| // op: Zdn |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: imm |
| op = getVecShiftR64OpValue(MI, 3, Fixups, STI); |
| Value |= (op & UINT64_C(32)) << 17; |
| Value |= (op & UINT64_C(31)) << 5; |
| break; |
| } |
| case AArch64::ASRD_ZPmI_B: |
| case AArch64::ASR_ZPmI_B: |
| case AArch64::LSR_ZPmI_B: |
| case AArch64::SRSHR_ZPmI_B: |
| case AArch64::URSHR_ZPmI_B: { |
| // op: Pg |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(7); |
| op <<= 10; |
| Value |= op; |
| // op: Zdn |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: imm |
| op = getVecShiftR8OpValue(MI, 3, Fixups, STI); |
| op &= UINT64_C(7); |
| op <<= 5; |
| Value |= op; |
| break; |
| } |
| case AArch64::ADDP_ZPmZ_B: |
| case AArch64::ADDP_ZPmZ_D: |
| case AArch64::ADDP_ZPmZ_H: |
| case AArch64::ADDP_ZPmZ_S: |
| case AArch64::FADDP_ZPmZZ_D: |
| case AArch64::FADDP_ZPmZZ_H: |
| case AArch64::FADDP_ZPmZZ_S: |
| case AArch64::FMAXNMP_ZPmZZ_D: |
| case AArch64::FMAXNMP_ZPmZZ_H: |
| case AArch64::FMAXNMP_ZPmZZ_S: |
| case AArch64::FMAXP_ZPmZZ_D: |
| case AArch64::FMAXP_ZPmZZ_H: |
| case AArch64::FMAXP_ZPmZZ_S: |
| case AArch64::FMINNMP_ZPmZZ_D: |
| case AArch64::FMINNMP_ZPmZZ_H: |
| case AArch64::FMINNMP_ZPmZZ_S: |
| case AArch64::FMINP_ZPmZZ_D: |
| case AArch64::FMINP_ZPmZZ_H: |
| case AArch64::FMINP_ZPmZZ_S: |
| case AArch64::SHADD_ZPmZ_B: |
| case AArch64::SHADD_ZPmZ_D: |
| case AArch64::SHADD_ZPmZ_H: |
| case AArch64::SHADD_ZPmZ_S: |
| case AArch64::SHSUBR_ZPmZ_B: |
| case AArch64::SHSUBR_ZPmZ_D: |
| case AArch64::SHSUBR_ZPmZ_H: |
| case AArch64::SHSUBR_ZPmZ_S: |
| case AArch64::SHSUB_ZPmZ_B: |
| case AArch64::SHSUB_ZPmZ_D: |
| case AArch64::SHSUB_ZPmZ_H: |
| case AArch64::SHSUB_ZPmZ_S: |
| case AArch64::SMAXP_ZPmZ_B: |
| case AArch64::SMAXP_ZPmZ_D: |
| case AArch64::SMAXP_ZPmZ_H: |
| case AArch64::SMAXP_ZPmZ_S: |
| case AArch64::SMINP_ZPmZ_B: |
| case AArch64::SMINP_ZPmZ_D: |
| case AArch64::SMINP_ZPmZ_H: |
| case AArch64::SMINP_ZPmZ_S: |
| case AArch64::SQADD_ZPmZ_B: |
| case AArch64::SQADD_ZPmZ_D: |
| case AArch64::SQADD_ZPmZ_H: |
| case AArch64::SQADD_ZPmZ_S: |
| case AArch64::SQRSHLR_ZPmZ_B: |
| case AArch64::SQRSHLR_ZPmZ_D: |
| case AArch64::SQRSHLR_ZPmZ_H: |
| case AArch64::SQRSHLR_ZPmZ_S: |
| case AArch64::SQRSHL_ZPmZ_B: |
| case AArch64::SQRSHL_ZPmZ_D: |
| case AArch64::SQRSHL_ZPmZ_H: |
| case AArch64::SQRSHL_ZPmZ_S: |
| case AArch64::SQSHLR_ZPmZ_B: |
| case AArch64::SQSHLR_ZPmZ_D: |
| case AArch64::SQSHLR_ZPmZ_H: |
| case AArch64::SQSHLR_ZPmZ_S: |
| case AArch64::SQSHL_ZPmZ_B: |
| case AArch64::SQSHL_ZPmZ_D: |
| case AArch64::SQSHL_ZPmZ_H: |
| case AArch64::SQSHL_ZPmZ_S: |
| case AArch64::SQSUBR_ZPmZ_B: |
| case AArch64::SQSUBR_ZPmZ_D: |
| case AArch64::SQSUBR_ZPmZ_H: |
| case AArch64::SQSUBR_ZPmZ_S: |
| case AArch64::SQSUB_ZPmZ_B: |
| case AArch64::SQSUB_ZPmZ_D: |
| case AArch64::SQSUB_ZPmZ_H: |
| case AArch64::SQSUB_ZPmZ_S: |
| case AArch64::SRHADD_ZPmZ_B: |
| case AArch64::SRHADD_ZPmZ_D: |
| case AArch64::SRHADD_ZPmZ_H: |
| case AArch64::SRHADD_ZPmZ_S: |
| case AArch64::SRSHLR_ZPmZ_B: |
| case AArch64::SRSHLR_ZPmZ_D: |
| case AArch64::SRSHLR_ZPmZ_H: |
| case AArch64::SRSHLR_ZPmZ_S: |
| case AArch64::SRSHL_ZPmZ_B: |
| case AArch64::SRSHL_ZPmZ_D: |
| case AArch64::SRSHL_ZPmZ_H: |
| case AArch64::SRSHL_ZPmZ_S: |
| case AArch64::SUQADD_ZPmZ_B: |
| case AArch64::SUQADD_ZPmZ_D: |
| case AArch64::SUQADD_ZPmZ_H: |
| case AArch64::SUQADD_ZPmZ_S: |
| case AArch64::UHADD_ZPmZ_B: |
| case AArch64::UHADD_ZPmZ_D: |
| case AArch64::UHADD_ZPmZ_H: |
| case AArch64::UHADD_ZPmZ_S: |
| case AArch64::UHSUBR_ZPmZ_B: |
| case AArch64::UHSUBR_ZPmZ_D: |
| case AArch64::UHSUBR_ZPmZ_H: |
| case AArch64::UHSUBR_ZPmZ_S: |
| case AArch64::UHSUB_ZPmZ_B: |
| case AArch64::UHSUB_ZPmZ_D: |
| case AArch64::UHSUB_ZPmZ_H: |
| case AArch64::UHSUB_ZPmZ_S: |
| case AArch64::UMAXP_ZPmZ_B: |
| case AArch64::UMAXP_ZPmZ_D: |
| case AArch64::UMAXP_ZPmZ_H: |
| case AArch64::UMAXP_ZPmZ_S: |
| case AArch64::UMINP_ZPmZ_B: |
| case AArch64::UMINP_ZPmZ_D: |
| case AArch64::UMINP_ZPmZ_H: |
| case AArch64::UMINP_ZPmZ_S: |
| case AArch64::UQADD_ZPmZ_B: |
| case AArch64::UQADD_ZPmZ_D: |
| case AArch64::UQADD_ZPmZ_H: |
| case AArch64::UQADD_ZPmZ_S: |
| case AArch64::UQRSHLR_ZPmZ_B: |
| case AArch64::UQRSHLR_ZPmZ_D: |
| case AArch64::UQRSHLR_ZPmZ_H: |
| case AArch64::UQRSHLR_ZPmZ_S: |
| case AArch64::UQRSHL_ZPmZ_B: |
| case AArch64::UQRSHL_ZPmZ_D: |
| case AArch64::UQRSHL_ZPmZ_H: |
| case AArch64::UQRSHL_ZPmZ_S: |
| case AArch64::UQSHLR_ZPmZ_B: |
| case AArch64::UQSHLR_ZPmZ_D: |
| case AArch64::UQSHLR_ZPmZ_H: |
| case AArch64::UQSHLR_ZPmZ_S: |
| case AArch64::UQSHL_ZPmZ_B: |
| case AArch64::UQSHL_ZPmZ_D: |
| case AArch64::UQSHL_ZPmZ_H: |
| case AArch64::UQSHL_ZPmZ_S: |
| case AArch64::UQSUBR_ZPmZ_B: |
| case AArch64::UQSUBR_ZPmZ_D: |
| case AArch64::UQSUBR_ZPmZ_H: |
| case AArch64::UQSUBR_ZPmZ_S: |
| case AArch64::UQSUB_ZPmZ_B: |
| case AArch64::UQSUB_ZPmZ_D: |
| case AArch64::UQSUB_ZPmZ_H: |
| case AArch64::UQSUB_ZPmZ_S: |
| case AArch64::URHADD_ZPmZ_B: |
| case AArch64::URHADD_ZPmZ_D: |
| case AArch64::URHADD_ZPmZ_H: |
| case AArch64::URHADD_ZPmZ_S: |
| case AArch64::URSHLR_ZPmZ_B: |
| case AArch64::URSHLR_ZPmZ_D: |
| case AArch64::URSHLR_ZPmZ_H: |
| case AArch64::URSHLR_ZPmZ_S: |
| case AArch64::URSHL_ZPmZ_B: |
| case AArch64::URSHL_ZPmZ_D: |
| case AArch64::URSHL_ZPmZ_H: |
| case AArch64::URSHL_ZPmZ_S: |
| case AArch64::USQADD_ZPmZ_B: |
| case AArch64::USQADD_ZPmZ_D: |
| case AArch64::USQADD_ZPmZ_H: |
| case AArch64::USQADD_ZPmZ_S: { |
| // op: Pg |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(7); |
| op <<= 10; |
| Value |= op; |
| // op: Zm |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: Zdn |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| break; |
| } |
| case AArch64::SPLICE_ZPZZ_B: |
| case AArch64::SPLICE_ZPZZ_D: |
| case AArch64::SPLICE_ZPZZ_H: |
| case AArch64::SPLICE_ZPZZ_S: { |
| // op: Pg |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(7); |
| op <<= 10; |
| Value |= op; |
| // op: Zn |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: Zd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| break; |
| } |
| case AArch64::GLD1B_D_IMM_REAL: |
| case AArch64::GLD1B_S_IMM_REAL: |
| case AArch64::GLD1D_IMM_REAL: |
| case AArch64::GLD1H_D_IMM_REAL: |
| case AArch64::GLD1H_S_IMM_REAL: |
| case AArch64::GLD1SB_D_IMM_REAL: |
| case AArch64::GLD1SB_S_IMM_REAL: |
| case AArch64::GLD1SH_D_IMM_REAL: |
| case AArch64::GLD1SH_S_IMM_REAL: |
| case AArch64::GLD1SW_D_IMM_REAL: |
| case AArch64::GLD1W_D_IMM_REAL: |
| case AArch64::GLD1W_IMM_REAL: |
| case AArch64::GLDFF1B_D_IMM_REAL: |
| case AArch64::GLDFF1B_S_IMM_REAL: |
| case AArch64::GLDFF1D_IMM_REAL: |
| case AArch64::GLDFF1H_D_IMM_REAL: |
| case AArch64::GLDFF1H_S_IMM_REAL: |
| case AArch64::GLDFF1SB_D_IMM_REAL: |
| case AArch64::GLDFF1SB_S_IMM_REAL: |
| case AArch64::GLDFF1SH_D_IMM_REAL: |
| case AArch64::GLDFF1SH_S_IMM_REAL: |
| case AArch64::GLDFF1SW_D_IMM_REAL: |
| case AArch64::GLDFF1W_D_IMM_REAL: |
| case AArch64::GLDFF1W_IMM_REAL: { |
| // op: Pg |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(7); |
| op <<= 10; |
| Value |= op; |
| // op: Zn |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: Zt |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: imm5 |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 16; |
| Value |= op; |
| break; |
| } |
| case AArch64::PRFB_D_PZI: |
| case AArch64::PRFB_S_PZI: |
| case AArch64::PRFD_D_PZI: |
| case AArch64::PRFD_S_PZI: |
| case AArch64::PRFH_D_PZI: |
| case AArch64::PRFH_S_PZI: |
| case AArch64::PRFW_D_PZI: |
| case AArch64::PRFW_S_PZI: { |
| // op: Pg |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(7); |
| op <<= 10; |
| Value |= op; |
| // op: Zn |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: imm5 |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 16; |
| Value |= op; |
| // op: prfop |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(15); |
| Value |= op; |
| break; |
| } |
| case AArch64::SADALP_ZPmZ_D: |
| case AArch64::SADALP_ZPmZ_H: |
| case AArch64::SADALP_ZPmZ_S: |
| case AArch64::UADALP_ZPmZ_D: |
| case AArch64::UADALP_ZPmZ_H: |
| case AArch64::UADALP_ZPmZ_S: { |
| // op: Pg |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(7); |
| op <<= 10; |
| Value |= op; |
| // op: Zn |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: Zda |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| break; |
| } |
| case AArch64::SST1B_D_IMM: |
| case AArch64::SST1B_S_IMM: |
| case AArch64::SST1D_IMM: |
| case AArch64::SST1H_D_IMM: |
| case AArch64::SST1H_S_IMM: |
| case AArch64::SST1W_D_IMM: |
| case AArch64::SST1W_IMM: { |
| // op: Pg |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(7); |
| op <<= 10; |
| Value |= op; |
| // op: imm5 |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 16; |
| Value |= op; |
| // op: Zn |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: Zt |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| break; |
| } |
| case AArch64::FCPY_ZPmI_D: |
| case AArch64::FCPY_ZPmI_H: |
| case AArch64::FCPY_ZPmI_S: { |
| // op: Pg |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(15); |
| op <<= 16; |
| Value |= op; |
| // op: Zd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: imm8 |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(255); |
| op <<= 5; |
| Value |= op; |
| break; |
| } |
| case AArch64::CPY_ZPmR_B: |
| case AArch64::CPY_ZPmR_D: |
| case AArch64::CPY_ZPmR_H: |
| case AArch64::CPY_ZPmR_S: { |
| // op: Pg |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(7); |
| op <<= 10; |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: Zd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| break; |
| } |
| case AArch64::CPY_ZPmV_B: |
| case AArch64::CPY_ZPmV_D: |
| case AArch64::CPY_ZPmV_H: |
| case AArch64::CPY_ZPmV_S: { |
| // op: Pg |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(7); |
| op <<= 10; |
| Value |= op; |
| // op: Vn |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: Zd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| break; |
| } |
| case AArch64::ABS_ZPmZ_B: |
| case AArch64::ABS_ZPmZ_D: |
| case AArch64::ABS_ZPmZ_H: |
| case AArch64::ABS_ZPmZ_S: |
| case AArch64::CLS_ZPmZ_B: |
| case AArch64::CLS_ZPmZ_D: |
| case AArch64::CLS_ZPmZ_H: |
| case AArch64::CLS_ZPmZ_S: |
| case AArch64::CLZ_ZPmZ_B: |
| case AArch64::CLZ_ZPmZ_D: |
| case AArch64::CLZ_ZPmZ_H: |
| case AArch64::CLZ_ZPmZ_S: |
| case AArch64::CNOT_ZPmZ_B: |
| case AArch64::CNOT_ZPmZ_D: |
| case AArch64::CNOT_ZPmZ_H: |
| case AArch64::CNOT_ZPmZ_S: |
| case AArch64::CNT_ZPmZ_B: |
| case AArch64::CNT_ZPmZ_D: |
| case AArch64::CNT_ZPmZ_H: |
| case AArch64::CNT_ZPmZ_S: |
| case AArch64::FABS_ZPmZ_D: |
| case AArch64::FABS_ZPmZ_H: |
| case AArch64::FABS_ZPmZ_S: |
| case AArch64::FCVTX_ZPmZ_DtoS: |
| case AArch64::FCVTZS_ZPmZ_DtoD: |
| case AArch64::FCVTZS_ZPmZ_DtoS: |
| case AArch64::FCVTZS_ZPmZ_HtoD: |
| case AArch64::FCVTZS_ZPmZ_HtoH: |
| case AArch64::FCVTZS_ZPmZ_HtoS: |
| case AArch64::FCVTZS_ZPmZ_StoD: |
| case AArch64::FCVTZS_ZPmZ_StoS: |
| case AArch64::FCVTZU_ZPmZ_DtoD: |
| case AArch64::FCVTZU_ZPmZ_DtoS: |
| case AArch64::FCVTZU_ZPmZ_HtoD: |
| case AArch64::FCVTZU_ZPmZ_HtoH: |
| case AArch64::FCVTZU_ZPmZ_HtoS: |
| case AArch64::FCVTZU_ZPmZ_StoD: |
| case AArch64::FCVTZU_ZPmZ_StoS: |
| case AArch64::FCVT_ZPmZ_DtoH: |
| case AArch64::FCVT_ZPmZ_DtoS: |
| case AArch64::FCVT_ZPmZ_HtoD: |
| case AArch64::FCVT_ZPmZ_HtoS: |
| case AArch64::FCVT_ZPmZ_StoD: |
| case AArch64::FCVT_ZPmZ_StoH: |
| case AArch64::FLOGB_ZPmZ_D: |
| case AArch64::FLOGB_ZPmZ_H: |
| case AArch64::FLOGB_ZPmZ_S: |
| case AArch64::FNEG_ZPmZ_D: |
| case AArch64::FNEG_ZPmZ_H: |
| case AArch64::FNEG_ZPmZ_S: |
| case AArch64::FRECPX_ZPmZ_D: |
| case AArch64::FRECPX_ZPmZ_H: |
| case AArch64::FRECPX_ZPmZ_S: |
| case AArch64::FRINTA_ZPmZ_D: |
| case AArch64::FRINTA_ZPmZ_H: |
| case AArch64::FRINTA_ZPmZ_S: |
| case AArch64::FRINTI_ZPmZ_D: |
| case AArch64::FRINTI_ZPmZ_H: |
| case AArch64::FRINTI_ZPmZ_S: |
| case AArch64::FRINTM_ZPmZ_D: |
| case AArch64::FRINTM_ZPmZ_H: |
| case AArch64::FRINTM_ZPmZ_S: |
| case AArch64::FRINTN_ZPmZ_D: |
| case AArch64::FRINTN_ZPmZ_H: |
| case AArch64::FRINTN_ZPmZ_S: |
| case AArch64::FRINTP_ZPmZ_D: |
| case AArch64::FRINTP_ZPmZ_H: |
| case AArch64::FRINTP_ZPmZ_S: |
| case AArch64::FRINTX_ZPmZ_D: |
| case AArch64::FRINTX_ZPmZ_H: |
| case AArch64::FRINTX_ZPmZ_S: |
| case AArch64::FRINTZ_ZPmZ_D: |
| case AArch64::FRINTZ_ZPmZ_H: |
| case AArch64::FRINTZ_ZPmZ_S: |
| case AArch64::FSQRT_ZPmZ_D: |
| case AArch64::FSQRT_ZPmZ_H: |
| case AArch64::FSQRT_ZPmZ_S: |
| case AArch64::MOVPRFX_ZPmZ_B: |
| case AArch64::MOVPRFX_ZPmZ_D: |
| case AArch64::MOVPRFX_ZPmZ_H: |
| case AArch64::MOVPRFX_ZPmZ_S: |
| case AArch64::NEG_ZPmZ_B: |
| case AArch64::NEG_ZPmZ_D: |
| case AArch64::NEG_ZPmZ_H: |
| case AArch64::NEG_ZPmZ_S: |
| case AArch64::NOT_ZPmZ_B: |
| case AArch64::NOT_ZPmZ_D: |
| case AArch64::NOT_ZPmZ_H: |
| case AArch64::NOT_ZPmZ_S: |
| case AArch64::SCVTF_ZPmZ_DtoD: |
| case AArch64::SCVTF_ZPmZ_DtoH: |
| case AArch64::SCVTF_ZPmZ_DtoS: |
| case AArch64::SCVTF_ZPmZ_HtoH: |
| case AArch64::SCVTF_ZPmZ_StoD: |
| case AArch64::SCVTF_ZPmZ_StoH: |
| case AArch64::SCVTF_ZPmZ_StoS: |
| case AArch64::SQABS_ZPmZ_B: |
| case AArch64::SQABS_ZPmZ_D: |
| case AArch64::SQABS_ZPmZ_H: |
| case AArch64::SQABS_ZPmZ_S: |
| case AArch64::SQNEG_ZPmZ_B: |
| case AArch64::SQNEG_ZPmZ_D: |
| case AArch64::SQNEG_ZPmZ_H: |
| case AArch64::SQNEG_ZPmZ_S: |
| case AArch64::SXTB_ZPmZ_D: |
| case AArch64::SXTB_ZPmZ_H: |
| case AArch64::SXTB_ZPmZ_S: |
| case AArch64::SXTH_ZPmZ_D: |
| case AArch64::SXTH_ZPmZ_S: |
| case AArch64::SXTW_ZPmZ_D: |
| case AArch64::UCVTF_ZPmZ_DtoD: |
| case AArch64::UCVTF_ZPmZ_DtoH: |
| case AArch64::UCVTF_ZPmZ_DtoS: |
| case AArch64::UCVTF_ZPmZ_HtoH: |
| case AArch64::UCVTF_ZPmZ_StoD: |
| case AArch64::UCVTF_ZPmZ_StoH: |
| case AArch64::UCVTF_ZPmZ_StoS: |
| case AArch64::URECPE_ZPmZ_S: |
| case AArch64::URSQRTE_ZPmZ_S: |
| case AArch64::UXTB_ZPmZ_D: |
| case AArch64::UXTB_ZPmZ_H: |
| case AArch64::UXTB_ZPmZ_S: |
| case AArch64::UXTH_ZPmZ_D: |
| case AArch64::UXTH_ZPmZ_S: |
| case AArch64::UXTW_ZPmZ_D: { |
| // op: Pg |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(7); |
| op <<= 10; |
| Value |= op; |
| // op: Zd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Zn |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| break; |
| } |
| case AArch64::DECP_ZP_D: |
| case AArch64::DECP_ZP_H: |
| case AArch64::DECP_ZP_S: |
| case AArch64::INCP_ZP_D: |
| case AArch64::INCP_ZP_H: |
| case AArch64::INCP_ZP_S: |
| case AArch64::SQDECP_ZP_D: |
| case AArch64::SQDECP_ZP_H: |
| case AArch64::SQDECP_ZP_S: |
| case AArch64::SQINCP_ZP_D: |
| case AArch64::SQINCP_ZP_H: |
| case AArch64::SQINCP_ZP_S: |
| case AArch64::UQDECP_ZP_D: |
| case AArch64::UQDECP_ZP_H: |
| case AArch64::UQDECP_ZP_S: |
| case AArch64::UQINCP_ZP_D: |
| case AArch64::UQINCP_ZP_H: |
| case AArch64::UQINCP_ZP_S: { |
| // op: Pm |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(15); |
| op <<= 5; |
| Value |= op; |
| // op: Zdn |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| break; |
| } |
| case AArch64::WRFFR: { |
| // op: Pn |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(15); |
| op <<= 5; |
| Value |= op; |
| break; |
| } |
| case AArch64::LDR_PXI: |
| case AArch64::STR_PXI: { |
| // op: Pt |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(15); |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: imm9 |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| Value |= (op & UINT64_C(504)) << 13; |
| Value |= (op & UINT64_C(7)) << 10; |
| break; |
| } |
| case AArch64::AUTDZA: |
| case AArch64::AUTDZB: |
| case AArch64::AUTIZA: |
| case AArch64::AUTIZB: |
| case AArch64::PACDZA: |
| case AArch64::PACDZB: |
| case AArch64::PACIZA: |
| case AArch64::PACIZB: |
| case AArch64::XPACD: |
| case AArch64::XPACI: { |
| // op: Rd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| break; |
| } |
| case AArch64::ADDPL_XXI: |
| case AArch64::ADDVL_XXI: { |
| // op: Rd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 16; |
| Value |= op; |
| // op: imm6 |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(63); |
| op <<= 5; |
| Value |= op; |
| break; |
| } |
| case AArch64::ABSv16i8: |
| case AArch64::ABSv1i64: |
| case AArch64::ABSv2i32: |
| case AArch64::ABSv2i64: |
| case AArch64::ABSv4i16: |
| case AArch64::ABSv4i32: |
| case AArch64::ABSv8i16: |
| case AArch64::ABSv8i8: |
| case AArch64::ADDPv2i64p: |
| case AArch64::ADDVv16i8v: |
| case AArch64::ADDVv4i16v: |
| case AArch64::ADDVv4i32v: |
| case AArch64::ADDVv8i16v: |
| case AArch64::ADDVv8i8v: |
| case AArch64::AESIMCrr: |
| case AArch64::AESMCrr: |
| case AArch64::AUTDA: |
| case AArch64::AUTDB: |
| case AArch64::AUTIA: |
| case AArch64::AUTIB: |
| case AArch64::CLSWr: |
| case AArch64::CLSXr: |
| case AArch64::CLSv16i8: |
| case AArch64::CLSv2i32: |
| case AArch64::CLSv4i16: |
| case AArch64::CLSv4i32: |
| case AArch64::CLSv8i16: |
| case AArch64::CLSv8i8: |
| case AArch64::CLZWr: |
| case AArch64::CLZXr: |
| case AArch64::CLZv16i8: |
| case AArch64::CLZv2i32: |
| case AArch64::CLZv4i16: |
| case AArch64::CLZv4i32: |
| case AArch64::CLZv8i16: |
| case AArch64::CLZv8i8: |
| case AArch64::CMEQv16i8rz: |
| case AArch64::CMEQv1i64rz: |
| case AArch64::CMEQv2i32rz: |
| case AArch64::CMEQv2i64rz: |
| case AArch64::CMEQv4i16rz: |
| case AArch64::CMEQv4i32rz: |
| case AArch64::CMEQv8i16rz: |
| case AArch64::CMEQv8i8rz: |
| case AArch64::CMGEv16i8rz: |
| case AArch64::CMGEv1i64rz: |
| case AArch64::CMGEv2i32rz: |
| case AArch64::CMGEv2i64rz: |
| case AArch64::CMGEv4i16rz: |
| case AArch64::CMGEv4i32rz: |
| case AArch64::CMGEv8i16rz: |
| case AArch64::CMGEv8i8rz: |
| case AArch64::CMGTv16i8rz: |
| case AArch64::CMGTv1i64rz: |
| case AArch64::CMGTv2i32rz: |
| case AArch64::CMGTv2i64rz: |
| case AArch64::CMGTv4i16rz: |
| case AArch64::CMGTv4i32rz: |
| case AArch64::CMGTv8i16rz: |
| case AArch64::CMGTv8i8rz: |
| case AArch64::CMLEv16i8rz: |
| case AArch64::CMLEv1i64rz: |
| case AArch64::CMLEv2i32rz: |
| case AArch64::CMLEv2i64rz: |
| case AArch64::CMLEv4i16rz: |
| case AArch64::CMLEv4i32rz: |
| case AArch64::CMLEv8i16rz: |
| case AArch64::CMLEv8i8rz: |
| case AArch64::CMLTv16i8rz: |
| case AArch64::CMLTv1i64rz: |
| case AArch64::CMLTv2i32rz: |
| case AArch64::CMLTv2i64rz: |
| case AArch64::CMLTv4i16rz: |
| case AArch64::CMLTv4i32rz: |
| case AArch64::CMLTv8i16rz: |
| case AArch64::CMLTv8i8rz: |
| case AArch64::CNTv16i8: |
| case AArch64::CNTv8i8: |
| case AArch64::DUPv16i8gpr: |
| case AArch64::DUPv2i32gpr: |
| case AArch64::DUPv2i64gpr: |
| case AArch64::DUPv4i16gpr: |
| case AArch64::DUPv4i32gpr: |
| case AArch64::DUPv8i16gpr: |
| case AArch64::DUPv8i8gpr: |
| case AArch64::FABSDr: |
| case AArch64::FABSHr: |
| case AArch64::FABSSr: |
| case AArch64::FABSv2f32: |
| case AArch64::FABSv2f64: |
| case AArch64::FABSv4f16: |
| case AArch64::FABSv4f32: |
| case AArch64::FABSv8f16: |
| case AArch64::FADDPv2i16p: |
| case AArch64::FADDPv2i32p: |
| case AArch64::FADDPv2i64p: |
| case AArch64::FCMEQv1i16rz: |
| case AArch64::FCMEQv1i32rz: |
| case AArch64::FCMEQv1i64rz: |
| case AArch64::FCMEQv2i32rz: |
| case AArch64::FCMEQv2i64rz: |
| case AArch64::FCMEQv4i16rz: |
| case AArch64::FCMEQv4i32rz: |
| case AArch64::FCMEQv8i16rz: |
| case AArch64::FCMGEv1i16rz: |
| case AArch64::FCMGEv1i32rz: |
| case AArch64::FCMGEv1i64rz: |
| case AArch64::FCMGEv2i32rz: |
| case AArch64::FCMGEv2i64rz: |
| case AArch64::FCMGEv4i16rz: |
| case AArch64::FCMGEv4i32rz: |
| case AArch64::FCMGEv8i16rz: |
| case AArch64::FCMGTv1i16rz: |
| case AArch64::FCMGTv1i32rz: |
| case AArch64::FCMGTv1i64rz: |
| case AArch64::FCMGTv2i32rz: |
| case AArch64::FCMGTv2i64rz: |
| case AArch64::FCMGTv4i16rz: |
| case AArch64::FCMGTv4i32rz: |
| case AArch64::FCMGTv8i16rz: |
| case AArch64::FCMLEv1i16rz: |
| case AArch64::FCMLEv1i32rz: |
| case AArch64::FCMLEv1i64rz: |
| case AArch64::FCMLEv2i32rz: |
| case AArch64::FCMLEv2i64rz: |
| case AArch64::FCMLEv4i16rz: |
| case AArch64::FCMLEv4i32rz: |
| case AArch64::FCMLEv8i16rz: |
| case AArch64::FCMLTv1i16rz: |
| case AArch64::FCMLTv1i32rz: |
| case AArch64::FCMLTv1i64rz: |
| case AArch64::FCMLTv2i32rz: |
| case AArch64::FCMLTv2i64rz: |
| case AArch64::FCMLTv4i16rz: |
| case AArch64::FCMLTv4i32rz: |
| case AArch64::FCMLTv8i16rz: |
| case AArch64::FCVTASUWDr: |
| case AArch64::FCVTASUWHr: |
| case AArch64::FCVTASUWSr: |
| case AArch64::FCVTASUXDr: |
| case AArch64::FCVTASUXHr: |
| case AArch64::FCVTASUXSr: |
| case AArch64::FCVTASv1f16: |
| case AArch64::FCVTASv1i32: |
| case AArch64::FCVTASv1i64: |
| case AArch64::FCVTASv2f32: |
| case AArch64::FCVTASv2f64: |
| case AArch64::FCVTASv4f16: |
| case AArch64::FCVTASv4f32: |
| case AArch64::FCVTASv8f16: |
| case AArch64::FCVTAUUWDr: |
| case AArch64::FCVTAUUWHr: |
| case AArch64::FCVTAUUWSr: |
| case AArch64::FCVTAUUXDr: |
| case AArch64::FCVTAUUXHr: |
| case AArch64::FCVTAUUXSr: |
| case AArch64::FCVTAUv1f16: |
| case AArch64::FCVTAUv1i32: |
| case AArch64::FCVTAUv1i64: |
| case AArch64::FCVTAUv2f32: |
| case AArch64::FCVTAUv2f64: |
| case AArch64::FCVTAUv4f16: |
| case AArch64::FCVTAUv4f32: |
| case AArch64::FCVTAUv8f16: |
| case AArch64::FCVTDHr: |
| case AArch64::FCVTDSr: |
| case AArch64::FCVTHDr: |
| case AArch64::FCVTHSr: |
| case AArch64::FCVTLv2i32: |
| case AArch64::FCVTLv4i16: |
| case AArch64::FCVTLv4i32: |
| case AArch64::FCVTLv8i16: |
| case AArch64::FCVTMSUWDr: |
| case AArch64::FCVTMSUWHr: |
| case AArch64::FCVTMSUWSr: |
| case AArch64::FCVTMSUXDr: |
| case AArch64::FCVTMSUXHr: |
| case AArch64::FCVTMSUXSr: |
| case AArch64::FCVTMSv1f16: |
| case AArch64::FCVTMSv1i32: |
| case AArch64::FCVTMSv1i64: |
| case AArch64::FCVTMSv2f32: |
| case AArch64::FCVTMSv2f64: |
| case AArch64::FCVTMSv4f16: |
| case AArch64::FCVTMSv4f32: |
| case AArch64::FCVTMSv8f16: |
| case AArch64::FCVTMUUWDr: |
| case AArch64::FCVTMUUWHr: |
| case AArch64::FCVTMUUWSr: |
| case AArch64::FCVTMUUXDr: |
| case AArch64::FCVTMUUXHr: |
| case AArch64::FCVTMUUXSr: |
| case AArch64::FCVTMUv1f16: |
| case AArch64::FCVTMUv1i32: |
| case AArch64::FCVTMUv1i64: |
| case AArch64::FCVTMUv2f32: |
| case AArch64::FCVTMUv2f64: |
| case AArch64::FCVTMUv4f16: |
| case AArch64::FCVTMUv4f32: |
| case AArch64::FCVTMUv8f16: |
| case AArch64::FCVTNSUWDr: |
| case AArch64::FCVTNSUWHr: |
| case AArch64::FCVTNSUWSr: |
| case AArch64::FCVTNSUXDr: |
| case AArch64::FCVTNSUXHr: |
| case AArch64::FCVTNSUXSr: |
| case AArch64::FCVTNSv1f16: |
| case AArch64::FCVTNSv1i32: |
| case AArch64::FCVTNSv1i64: |
| case AArch64::FCVTNSv2f32: |
| case AArch64::FCVTNSv2f64: |
| case AArch64::FCVTNSv4f16: |
| case AArch64::FCVTNSv4f32: |
| case AArch64::FCVTNSv8f16: |
| case AArch64::FCVTNUUWDr: |
| case AArch64::FCVTNUUWHr: |
| case AArch64::FCVTNUUWSr: |
| case AArch64::FCVTNUUXDr: |
| case AArch64::FCVTNUUXHr: |
| case AArch64::FCVTNUUXSr: |
| case AArch64::FCVTNUv1f16: |
| case AArch64::FCVTNUv1i32: |
| case AArch64::FCVTNUv1i64: |
| case AArch64::FCVTNUv2f32: |
| case AArch64::FCVTNUv2f64: |
| case AArch64::FCVTNUv4f16: |
| case AArch64::FCVTNUv4f32: |
| case AArch64::FCVTNUv8f16: |
| case AArch64::FCVTNv2i32: |
| case AArch64::FCVTNv4i16: |
| case AArch64::FCVTPSUWDr: |
| case AArch64::FCVTPSUWHr: |
| case AArch64::FCVTPSUWSr: |
| case AArch64::FCVTPSUXDr: |
| case AArch64::FCVTPSUXHr: |
| case AArch64::FCVTPSUXSr: |
| case AArch64::FCVTPSv1f16: |
| case AArch64::FCVTPSv1i32: |
| case AArch64::FCVTPSv1i64: |
| case AArch64::FCVTPSv2f32: |
| case AArch64::FCVTPSv2f64: |
| case AArch64::FCVTPSv4f16: |
| case AArch64::FCVTPSv4f32: |
| case AArch64::FCVTPSv8f16: |
| case AArch64::FCVTPUUWDr: |
| case AArch64::FCVTPUUWHr: |
| case AArch64::FCVTPUUWSr: |
| case AArch64::FCVTPUUXDr: |
| case AArch64::FCVTPUUXHr: |
| case AArch64::FCVTPUUXSr: |
| case AArch64::FCVTPUv1f16: |
| case AArch64::FCVTPUv1i32: |
| case AArch64::FCVTPUv1i64: |
| case AArch64::FCVTPUv2f32: |
| case AArch64::FCVTPUv2f64: |
| case AArch64::FCVTPUv4f16: |
| case AArch64::FCVTPUv4f32: |
| case AArch64::FCVTPUv8f16: |
| case AArch64::FCVTSDr: |
| case AArch64::FCVTSHr: |
| case AArch64::FCVTXNv1i64: |
| case AArch64::FCVTXNv2f32: |
| case AArch64::FCVTZSUWDr: |
| case AArch64::FCVTZSUWHr: |
| case AArch64::FCVTZSUWSr: |
| case AArch64::FCVTZSUXDr: |
| case AArch64::FCVTZSUXHr: |
| case AArch64::FCVTZSUXSr: |
| case AArch64::FCVTZSv1f16: |
| case AArch64::FCVTZSv1i32: |
| case AArch64::FCVTZSv1i64: |
| case AArch64::FCVTZSv2f32: |
| case AArch64::FCVTZSv2f64: |
| case AArch64::FCVTZSv4f16: |
| case AArch64::FCVTZSv4f32: |
| case AArch64::FCVTZSv8f16: |
| case AArch64::FCVTZUUWDr: |
| case AArch64::FCVTZUUWHr: |
| case AArch64::FCVTZUUWSr: |
| case AArch64::FCVTZUUXDr: |
| case AArch64::FCVTZUUXHr: |
| case AArch64::FCVTZUUXSr: |
| case AArch64::FCVTZUv1f16: |
| case AArch64::FCVTZUv1i32: |
| case AArch64::FCVTZUv1i64: |
| case AArch64::FCVTZUv2f32: |
| case AArch64::FCVTZUv2f64: |
| case AArch64::FCVTZUv4f16: |
| case AArch64::FCVTZUv4f32: |
| case AArch64::FCVTZUv8f16: |
| case AArch64::FJCVTZS: |
| case AArch64::FMAXNMPv2i16p: |
| case AArch64::FMAXNMPv2i32p: |
| case AArch64::FMAXNMPv2i64p: |
| case AArch64::FMAXNMVv4i16v: |
| case AArch64::FMAXNMVv4i32v: |
| case AArch64::FMAXNMVv8i16v: |
| case AArch64::FMAXPv2i16p: |
| case AArch64::FMAXPv2i32p: |
| case AArch64::FMAXPv2i64p: |
| case AArch64::FMAXVv4i16v: |
| case AArch64::FMAXVv4i32v: |
| case AArch64::FMAXVv8i16v: |
| case AArch64::FMINNMPv2i16p: |
| case AArch64::FMINNMPv2i32p: |
| case AArch64::FMINNMPv2i64p: |
| case AArch64::FMINNMVv4i16v: |
| case AArch64::FMINNMVv4i32v: |
| case AArch64::FMINNMVv8i16v: |
| case AArch64::FMINPv2i16p: |
| case AArch64::FMINPv2i32p: |
| case AArch64::FMINPv2i64p: |
| case AArch64::FMINVv4i16v: |
| case AArch64::FMINVv4i32v: |
| case AArch64::FMINVv8i16v: |
| case AArch64::FMOVDXHighr: |
| case AArch64::FMOVDXr: |
| case AArch64::FMOVDr: |
| case AArch64::FMOVHWr: |
| case AArch64::FMOVHXr: |
| case AArch64::FMOVHr: |
| case AArch64::FMOVSWr: |
| case AArch64::FMOVSr: |
| case AArch64::FMOVWHr: |
| case AArch64::FMOVWSr: |
| case AArch64::FMOVXDHighr: |
| case AArch64::FMOVXDr: |
| case AArch64::FMOVXHr: |
| case AArch64::FNEGDr: |
| case AArch64::FNEGHr: |
| case AArch64::FNEGSr: |
| case AArch64::FNEGv2f32: |
| case AArch64::FNEGv2f64: |
| case AArch64::FNEGv4f16: |
| case AArch64::FNEGv4f32: |
| case AArch64::FNEGv8f16: |
| case AArch64::FRECPEv1f16: |
| case AArch64::FRECPEv1i32: |
| case AArch64::FRECPEv1i64: |
| case AArch64::FRECPEv2f32: |
| case AArch64::FRECPEv2f64: |
| case AArch64::FRECPEv4f16: |
| case AArch64::FRECPEv4f32: |
| case AArch64::FRECPEv8f16: |
| case AArch64::FRECPXv1f16: |
| case AArch64::FRECPXv1i32: |
| case AArch64::FRECPXv1i64: |
| case AArch64::FRINT32XDr: |
| case AArch64::FRINT32XSr: |
| case AArch64::FRINT32Xv2f32: |
| case AArch64::FRINT32Xv2f64: |
| case AArch64::FRINT32Xv4f32: |
| case AArch64::FRINT32ZDr: |
| case AArch64::FRINT32ZSr: |
| case AArch64::FRINT32Zv2f32: |
| case AArch64::FRINT32Zv2f64: |
| case AArch64::FRINT32Zv4f32: |
| case AArch64::FRINT64XDr: |
| case AArch64::FRINT64XSr: |
| case AArch64::FRINT64Xv2f32: |
| case AArch64::FRINT64Xv2f64: |
| case AArch64::FRINT64Xv4f32: |
| case AArch64::FRINT64ZDr: |
| case AArch64::FRINT64ZSr: |
| case AArch64::FRINT64Zv2f32: |
| case AArch64::FRINT64Zv2f64: |
| case AArch64::FRINT64Zv4f32: |
| case AArch64::FRINTADr: |
| case AArch64::FRINTAHr: |
| case AArch64::FRINTASr: |
| case AArch64::FRINTAv2f32: |
| case AArch64::FRINTAv2f64: |
| case AArch64::FRINTAv4f16: |
| case AArch64::FRINTAv4f32: |
| case AArch64::FRINTAv8f16: |
| case AArch64::FRINTIDr: |
| case AArch64::FRINTIHr: |
| case AArch64::FRINTISr: |
| case AArch64::FRINTIv2f32: |
| case AArch64::FRINTIv2f64: |
| case AArch64::FRINTIv4f16: |
| case AArch64::FRINTIv4f32: |
| case AArch64::FRINTIv8f16: |
| case AArch64::FRINTMDr: |
| case AArch64::FRINTMHr: |
| case AArch64::FRINTMSr: |
| case AArch64::FRINTMv2f32: |
| case AArch64::FRINTMv2f64: |
| case AArch64::FRINTMv4f16: |
| case AArch64::FRINTMv4f32: |
| case AArch64::FRINTMv8f16: |
| case AArch64::FRINTNDr: |
| case AArch64::FRINTNHr: |
| case AArch64::FRINTNSr: |
| case AArch64::FRINTNv2f32: |
| case AArch64::FRINTNv2f64: |
| case AArch64::FRINTNv4f16: |
| case AArch64::FRINTNv4f32: |
| case AArch64::FRINTNv8f16: |
| case AArch64::FRINTPDr: |
| case AArch64::FRINTPHr: |
| case AArch64::FRINTPSr: |
| case AArch64::FRINTPv2f32: |
| case AArch64::FRINTPv2f64: |
| case AArch64::FRINTPv4f16: |
| case AArch64::FRINTPv4f32: |
| case AArch64::FRINTPv8f16: |
| case AArch64::FRINTXDr: |
| case AArch64::FRINTXHr: |
| case AArch64::FRINTXSr: |
| case AArch64::FRINTXv2f32: |
| case AArch64::FRINTXv2f64: |
| case AArch64::FRINTXv4f16: |
| case AArch64::FRINTXv4f32: |
| case AArch64::FRINTXv8f16: |
| case AArch64::FRINTZDr: |
| case AArch64::FRINTZHr: |
| case AArch64::FRINTZSr: |
| case AArch64::FRINTZv2f32: |
| case AArch64::FRINTZv2f64: |
| case AArch64::FRINTZv4f16: |
| case AArch64::FRINTZv4f32: |
| case AArch64::FRINTZv8f16: |
| case AArch64::FRSQRTEv1f16: |
| case AArch64::FRSQRTEv1i32: |
| case AArch64::FRSQRTEv1i64: |
| case AArch64::FRSQRTEv2f32: |
| case AArch64::FRSQRTEv2f64: |
| case AArch64::FRSQRTEv4f16: |
| case AArch64::FRSQRTEv4f32: |
| case AArch64::FRSQRTEv8f16: |
| case AArch64::FSQRTDr: |
| case AArch64::FSQRTHr: |
| case AArch64::FSQRTSr: |
| case AArch64::FSQRTv2f32: |
| case AArch64::FSQRTv2f64: |
| case AArch64::FSQRTv4f16: |
| case AArch64::FSQRTv4f32: |
| case AArch64::FSQRTv8f16: |
| case AArch64::NEGv16i8: |
| case AArch64::NEGv1i64: |
| case AArch64::NEGv2i32: |
| case AArch64::NEGv2i64: |
| case AArch64::NEGv4i16: |
| case AArch64::NEGv4i32: |
| case AArch64::NEGv8i16: |
| case AArch64::NEGv8i8: |
| case AArch64::NOTv16i8: |
| case AArch64::NOTv8i8: |
| case AArch64::PACDA: |
| case AArch64::PACDB: |
| case AArch64::PACIA: |
| case AArch64::PACIB: |
| case AArch64::RBITWr: |
| case AArch64::RBITXr: |
| case AArch64::RBITv16i8: |
| case AArch64::RBITv8i8: |
| case AArch64::REV16Wr: |
| case AArch64::REV16Xr: |
| case AArch64::REV16v16i8: |
| case AArch64::REV16v8i8: |
| case AArch64::REV32Xr: |
| case AArch64::REV32v16i8: |
| case AArch64::REV32v4i16: |
| case AArch64::REV32v8i16: |
| case AArch64::REV32v8i8: |
| case AArch64::REV64v16i8: |
| case AArch64::REV64v2i32: |
| case AArch64::REV64v4i16: |
| case AArch64::REV64v4i32: |
| case AArch64::REV64v8i16: |
| case AArch64::REV64v8i8: |
| case AArch64::REVWr: |
| case AArch64::REVXr: |
| case AArch64::SADDLPv16i8_v8i16: |
| case AArch64::SADDLPv2i32_v1i64: |
| case AArch64::SADDLPv4i16_v2i32: |
| case AArch64::SADDLPv4i32_v2i64: |
| case AArch64::SADDLPv8i16_v4i32: |
| case AArch64::SADDLPv8i8_v4i16: |
| case AArch64::SADDLVv16i8v: |
| case AArch64::SADDLVv4i16v: |
| case AArch64::SADDLVv4i32v: |
| case AArch64::SADDLVv8i16v: |
| case AArch64::SADDLVv8i8v: |
| case AArch64::SCVTFUWDri: |
| case AArch64::SCVTFUWHri: |
| case AArch64::SCVTFUWSri: |
| case AArch64::SCVTFUXDri: |
| case AArch64::SCVTFUXHri: |
| case AArch64::SCVTFUXSri: |
| case AArch64::SCVTFv1i16: |
| case AArch64::SCVTFv1i32: |
| case AArch64::SCVTFv1i64: |
| case AArch64::SCVTFv2f32: |
| case AArch64::SCVTFv2f64: |
| case AArch64::SCVTFv4f16: |
| case AArch64::SCVTFv4f32: |
| case AArch64::SCVTFv8f16: |
| case AArch64::SHA1Hrr: |
| case AArch64::SHLLv16i8: |
| case AArch64::SHLLv2i32: |
| case AArch64::SHLLv4i16: |
| case AArch64::SHLLv4i32: |
| case AArch64::SHLLv8i16: |
| case AArch64::SHLLv8i8: |
| case AArch64::SMAXVv16i8v: |
| case AArch64::SMAXVv4i16v: |
| case AArch64::SMAXVv4i32v: |
| case AArch64::SMAXVv8i16v: |
| case AArch64::SMAXVv8i8v: |
| case AArch64::SMINVv16i8v: |
| case AArch64::SMINVv4i16v: |
| case AArch64::SMINVv4i32v: |
| case AArch64::SMINVv8i16v: |
| case AArch64::SMINVv8i8v: |
| case AArch64::SQABSv16i8: |
| case AArch64::SQABSv1i16: |
| case AArch64::SQABSv1i32: |
| case AArch64::SQABSv1i64: |
| case AArch64::SQABSv1i8: |
| case AArch64::SQABSv2i32: |
| case AArch64::SQABSv2i64: |
| case AArch64::SQABSv4i16: |
| case AArch64::SQABSv4i32: |
| case AArch64::SQABSv8i16: |
| case AArch64::SQABSv8i8: |
| case AArch64::SQNEGv16i8: |
| case AArch64::SQNEGv1i16: |
| case AArch64::SQNEGv1i32: |
| case AArch64::SQNEGv1i64: |
| case AArch64::SQNEGv1i8: |
| case AArch64::SQNEGv2i32: |
| case AArch64::SQNEGv2i64: |
| case AArch64::SQNEGv4i16: |
| case AArch64::SQNEGv4i32: |
| case AArch64::SQNEGv8i16: |
| case AArch64::SQNEGv8i8: |
| case AArch64::SQXTNv1i16: |
| case AArch64::SQXTNv1i32: |
| case AArch64::SQXTNv1i8: |
| case AArch64::SQXTNv2i32: |
| case AArch64::SQXTNv4i16: |
| case AArch64::SQXTNv8i8: |
| case AArch64::SQXTUNv1i16: |
| case AArch64::SQXTUNv1i32: |
| case AArch64::SQXTUNv1i8: |
| case AArch64::SQXTUNv2i32: |
| case AArch64::SQXTUNv4i16: |
| case AArch64::SQXTUNv8i8: |
| case AArch64::UADDLPv16i8_v8i16: |
| case AArch64::UADDLPv2i32_v1i64: |
| case AArch64::UADDLPv4i16_v2i32: |
| case AArch64::UADDLPv4i32_v2i64: |
| case AArch64::UADDLPv8i16_v4i32: |
| case AArch64::UADDLPv8i8_v4i16: |
| case AArch64::UADDLVv16i8v: |
| case AArch64::UADDLVv4i16v: |
| case AArch64::UADDLVv4i32v: |
| case AArch64::UADDLVv8i16v: |
| case AArch64::UADDLVv8i8v: |
| case AArch64::UCVTFUWDri: |
| case AArch64::UCVTFUWHri: |
| case AArch64::UCVTFUWSri: |
| case AArch64::UCVTFUXDri: |
| case AArch64::UCVTFUXHri: |
| case AArch64::UCVTFUXSri: |
| case AArch64::UCVTFv1i16: |
| case AArch64::UCVTFv1i32: |
| case AArch64::UCVTFv1i64: |
| case AArch64::UCVTFv2f32: |
| case AArch64::UCVTFv2f64: |
| case AArch64::UCVTFv4f16: |
| case AArch64::UCVTFv4f32: |
| case AArch64::UCVTFv8f16: |
| case AArch64::UMAXVv16i8v: |
| case AArch64::UMAXVv4i16v: |
| case AArch64::UMAXVv4i32v: |
| case AArch64::UMAXVv8i16v: |
| case AArch64::UMAXVv8i8v: |
| case AArch64::UMINVv16i8v: |
| case AArch64::UMINVv4i16v: |
| case AArch64::UMINVv4i32v: |
| case AArch64::UMINVv8i16v: |
| case AArch64::UMINVv8i8v: |
| case AArch64::UQXTNv1i16: |
| case AArch64::UQXTNv1i32: |
| case AArch64::UQXTNv1i8: |
| case AArch64::UQXTNv2i32: |
| case AArch64::UQXTNv4i16: |
| case AArch64::UQXTNv8i8: |
| case AArch64::URECPEv2i32: |
| case AArch64::URECPEv4i32: |
| case AArch64::URSQRTEv2i32: |
| case AArch64::URSQRTEv4i32: |
| case AArch64::XTNv2i32: |
| case AArch64::XTNv4i16: |
| case AArch64::XTNv8i8: { |
| // op: Rd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| break; |
| } |
| case AArch64::FMULXv1i16_indexed: |
| case AArch64::FMULXv4i16_indexed: |
| case AArch64::FMULXv8i16_indexed: |
| case AArch64::FMULv1i16_indexed: |
| case AArch64::FMULv4i16_indexed: |
| case AArch64::FMULv8i16_indexed: |
| case AArch64::MULv4i16_indexed: |
| case AArch64::MULv8i16_indexed: |
| case AArch64::SMULLv4i16_indexed: |
| case AArch64::SMULLv8i16_indexed: |
| case AArch64::SQDMULHv1i16_indexed: |
| case AArch64::SQDMULHv4i16_indexed: |
| case AArch64::SQDMULHv8i16_indexed: |
| case AArch64::SQDMULLv1i32_indexed: |
| case AArch64::SQDMULLv4i16_indexed: |
| case AArch64::SQDMULLv8i16_indexed: |
| case AArch64::SQRDMULHv1i16_indexed: |
| case AArch64::SQRDMULHv4i16_indexed: |
| case AArch64::SQRDMULHv8i16_indexed: |
| case AArch64::UMULLv4i16_indexed: |
| case AArch64::UMULLv8i16_indexed: { |
| // op: Rd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: Rm |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(15); |
| op <<= 16; |
| Value |= op; |
| // op: idx |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| Value |= (op & UINT64_C(3)) << 20; |
| Value |= (op & UINT64_C(4)) << 9; |
| break; |
| } |
| case AArch64::ADCSWr: |
| case AArch64::ADCSXr: |
| case AArch64::ADCWr: |
| case AArch64::ADCXr: |
| case AArch64::ADDHNv2i64_v2i32: |
| case AArch64::ADDHNv4i32_v4i16: |
| case AArch64::ADDHNv8i16_v8i8: |
| case AArch64::ADDPv16i8: |
| case AArch64::ADDPv2i32: |
| case AArch64::ADDPv2i64: |
| case AArch64::ADDPv4i16: |
| case AArch64::ADDPv4i32: |
| case AArch64::ADDPv8i16: |
| case AArch64::ADDPv8i8: |
| case AArch64::ADDv16i8: |
| case AArch64::ADDv1i64: |
| case AArch64::ADDv2i32: |
| case AArch64::ADDv2i64: |
| case AArch64::ADDv4i16: |
| case AArch64::ADDv4i32: |
| case AArch64::ADDv8i16: |
| case AArch64::ADDv8i8: |
| case AArch64::ANDv16i8: |
| case AArch64::ANDv8i8: |
| case AArch64::ASRVWr: |
| case AArch64::ASRVXr: |
| case AArch64::BICv16i8: |
| case AArch64::BICv8i8: |
| case AArch64::BIFv16i8: |
| case AArch64::BIFv8i8: |
| case AArch64::CMEQv16i8: |
| case AArch64::CMEQv1i64: |
| case AArch64::CMEQv2i32: |
| case AArch64::CMEQv2i64: |
| case AArch64::CMEQv4i16: |
| case AArch64::CMEQv4i32: |
| case AArch64::CMEQv8i16: |
| case AArch64::CMEQv8i8: |
| case AArch64::CMGEv16i8: |
| case AArch64::CMGEv1i64: |
| case AArch64::CMGEv2i32: |
| case AArch64::CMGEv2i64: |
| case AArch64::CMGEv4i16: |
| case AArch64::CMGEv4i32: |
| case AArch64::CMGEv8i16: |
| case AArch64::CMGEv8i8: |
| case AArch64::CMGTv16i8: |
| case AArch64::CMGTv1i64: |
| case AArch64::CMGTv2i32: |
| case AArch64::CMGTv2i64: |
| case AArch64::CMGTv4i16: |
| case AArch64::CMGTv4i32: |
| case AArch64::CMGTv8i16: |
| case AArch64::CMGTv8i8: |
| case AArch64::CMHIv16i8: |
| case AArch64::CMHIv1i64: |
| case AArch64::CMHIv2i32: |
| case AArch64::CMHIv2i64: |
| case AArch64::CMHIv4i16: |
| case AArch64::CMHIv4i32: |
| case AArch64::CMHIv8i16: |
| case AArch64::CMHIv8i8: |
| case AArch64::CMHSv16i8: |
| case AArch64::CMHSv1i64: |
| case AArch64::CMHSv2i32: |
| case AArch64::CMHSv2i64: |
| case AArch64::CMHSv4i16: |
| case AArch64::CMHSv4i32: |
| case AArch64::CMHSv8i16: |
| case AArch64::CMHSv8i8: |
| case AArch64::CMTSTv16i8: |
| case AArch64::CMTSTv1i64: |
| case AArch64::CMTSTv2i32: |
| case AArch64::CMTSTv2i64: |
| case AArch64::CMTSTv4i16: |
| case AArch64::CMTSTv4i32: |
| case AArch64::CMTSTv8i16: |
| case AArch64::CMTSTv8i8: |
| case AArch64::CRC32Brr: |
| case AArch64::CRC32CBrr: |
| case AArch64::CRC32CHrr: |
| case AArch64::CRC32CWrr: |
| case AArch64::CRC32CXrr: |
| case AArch64::CRC32Hrr: |
| case AArch64::CRC32Wrr: |
| case AArch64::CRC32Xrr: |
| case AArch64::EORv16i8: |
| case AArch64::EORv8i8: |
| case AArch64::FABD16: |
| case AArch64::FABD32: |
| case AArch64::FABD64: |
| case AArch64::FABDv2f32: |
| case AArch64::FABDv2f64: |
| case AArch64::FABDv4f16: |
| case AArch64::FABDv4f32: |
| case AArch64::FABDv8f16: |
| case AArch64::FACGE16: |
| case AArch64::FACGE32: |
| case AArch64::FACGE64: |
| case AArch64::FACGEv2f32: |
| case AArch64::FACGEv2f64: |
| case AArch64::FACGEv4f16: |
| case AArch64::FACGEv4f32: |
| case AArch64::FACGEv8f16: |
| case AArch64::FACGT16: |
| case AArch64::FACGT32: |
| case AArch64::FACGT64: |
| case AArch64::FACGTv2f32: |
| case AArch64::FACGTv2f64: |
| case AArch64::FACGTv4f16: |
| case AArch64::FACGTv4f32: |
| case AArch64::FACGTv8f16: |
| case AArch64::FADDDrr: |
| case AArch64::FADDHrr: |
| case AArch64::FADDPv2f32: |
| case AArch64::FADDPv2f64: |
| case AArch64::FADDPv4f16: |
| case AArch64::FADDPv4f32: |
| case AArch64::FADDPv8f16: |
| case AArch64::FADDSrr: |
| case AArch64::FADDv2f32: |
| case AArch64::FADDv2f64: |
| case AArch64::FADDv4f16: |
| case AArch64::FADDv4f32: |
| case AArch64::FADDv8f16: |
| case AArch64::FCMEQ16: |
| case AArch64::FCMEQ32: |
| case AArch64::FCMEQ64: |
| case AArch64::FCMEQv2f32: |
| case AArch64::FCMEQv2f64: |
| case AArch64::FCMEQv4f16: |
| case AArch64::FCMEQv4f32: |
| case AArch64::FCMEQv8f16: |
| case AArch64::FCMGE16: |
| case AArch64::FCMGE32: |
| case AArch64::FCMGE64: |
| case AArch64::FCMGEv2f32: |
| case AArch64::FCMGEv2f64: |
| case AArch64::FCMGEv4f16: |
| case AArch64::FCMGEv4f32: |
| case AArch64::FCMGEv8f16: |
| case AArch64::FCMGT16: |
| case AArch64::FCMGT32: |
| case AArch64::FCMGT64: |
| case AArch64::FCMGTv2f32: |
| case AArch64::FCMGTv2f64: |
| case AArch64::FCMGTv4f16: |
| case AArch64::FCMGTv4f32: |
| case AArch64::FCMGTv8f16: |
| case AArch64::FDIVDrr: |
| case AArch64::FDIVHrr: |
| case AArch64::FDIVSrr: |
| case AArch64::FDIVv2f32: |
| case AArch64::FDIVv2f64: |
| case AArch64::FDIVv4f16: |
| case AArch64::FDIVv4f32: |
| case AArch64::FDIVv8f16: |
| case AArch64::FMAXDrr: |
| case AArch64::FMAXHrr: |
| case AArch64::FMAXNMDrr: |
| case AArch64::FMAXNMHrr: |
| case AArch64::FMAXNMPv2f32: |
| case AArch64::FMAXNMPv2f64: |
| case AArch64::FMAXNMPv4f16: |
| case AArch64::FMAXNMPv4f32: |
| case AArch64::FMAXNMPv8f16: |
| case AArch64::FMAXNMSrr: |
| case AArch64::FMAXNMv2f32: |
| case AArch64::FMAXNMv2f64: |
| case AArch64::FMAXNMv4f16: |
| case AArch64::FMAXNMv4f32: |
| case AArch64::FMAXNMv8f16: |
| case AArch64::FMAXPv2f32: |
| case AArch64::FMAXPv2f64: |
| case AArch64::FMAXPv4f16: |
| case AArch64::FMAXPv4f32: |
| case AArch64::FMAXPv8f16: |
| case AArch64::FMAXSrr: |
| case AArch64::FMAXv2f32: |
| case AArch64::FMAXv2f64: |
| case AArch64::FMAXv4f16: |
| case AArch64::FMAXv4f32: |
| case AArch64::FMAXv8f16: |
| case AArch64::FMINDrr: |
| case AArch64::FMINHrr: |
| case AArch64::FMINNMDrr: |
| case AArch64::FMINNMHrr: |
| case AArch64::FMINNMPv2f32: |
| case AArch64::FMINNMPv2f64: |
| case AArch64::FMINNMPv4f16: |
| case AArch64::FMINNMPv4f32: |
| case AArch64::FMINNMPv8f16: |
| case AArch64::FMINNMSrr: |
| case AArch64::FMINNMv2f32: |
| case AArch64::FMINNMv2f64: |
| case AArch64::FMINNMv4f16: |
| case AArch64::FMINNMv4f32: |
| case AArch64::FMINNMv8f16: |
| case AArch64::FMINPv2f32: |
| case AArch64::FMINPv2f64: |
| case AArch64::FMINPv4f16: |
| case AArch64::FMINPv4f32: |
| case AArch64::FMINPv8f16: |
| case AArch64::FMINSrr: |
| case AArch64::FMINv2f32: |
| case AArch64::FMINv2f64: |
| case AArch64::FMINv4f16: |
| case AArch64::FMINv4f32: |
| case AArch64::FMINv8f16: |
| case AArch64::FMULDrr: |
| case AArch64::FMULHrr: |
| case AArch64::FMULSrr: |
| case AArch64::FMULX16: |
| case AArch64::FMULX32: |
| case AArch64::FMULX64: |
| case AArch64::FMULXv2f32: |
| case AArch64::FMULXv2f64: |
| case AArch64::FMULXv4f16: |
| case AArch64::FMULXv4f32: |
| case AArch64::FMULXv8f16: |
| case AArch64::FMULv2f32: |
| case AArch64::FMULv2f64: |
| case AArch64::FMULv4f16: |
| case AArch64::FMULv4f32: |
| case AArch64::FMULv8f16: |
| case AArch64::FNMULDrr: |
| case AArch64::FNMULHrr: |
| case AArch64::FNMULSrr: |
| case AArch64::FRECPS16: |
| case AArch64::FRECPS32: |
| case AArch64::FRECPS64: |
| case AArch64::FRECPSv2f32: |
| case AArch64::FRECPSv2f64: |
| case AArch64::FRECPSv4f16: |
| case AArch64::FRECPSv4f32: |
| case AArch64::FRECPSv8f16: |
| case AArch64::FRSQRTS16: |
| case AArch64::FRSQRTS32: |
| case AArch64::FRSQRTS64: |
| case AArch64::FRSQRTSv2f32: |
| case AArch64::FRSQRTSv2f64: |
| case AArch64::FRSQRTSv4f16: |
| case AArch64::FRSQRTSv4f32: |
| case AArch64::FRSQRTSv8f16: |
| case AArch64::FSUBDrr: |
| case AArch64::FSUBHrr: |
| case AArch64::FSUBSrr: |
| case AArch64::FSUBv2f32: |
| case AArch64::FSUBv2f64: |
| case AArch64::FSUBv4f16: |
| case AArch64::FSUBv4f32: |
| case AArch64::FSUBv8f16: |
| case AArch64::GMI: |
| case AArch64::IRG: |
| case AArch64::LSLVWr: |
| case AArch64::LSLVXr: |
| case AArch64::LSRVWr: |
| case AArch64::LSRVXr: |
| case AArch64::MULv16i8: |
| case AArch64::MULv2i32: |
| case AArch64::MULv4i16: |
| case AArch64::MULv4i32: |
| case AArch64::MULv8i16: |
| case AArch64::MULv8i8: |
| case AArch64::ORNv16i8: |
| case AArch64::ORNv8i8: |
| case AArch64::ORRv16i8: |
| case AArch64::ORRv8i8: |
| case AArch64::PACGA: |
| case AArch64::PMULLv16i8: |
| case AArch64::PMULLv1i64: |
| case AArch64::PMULLv2i64: |
| case AArch64::PMULLv8i8: |
| case AArch64::PMULv16i8: |
| case AArch64::PMULv8i8: |
| case AArch64::RADDHNv2i64_v2i32: |
| case AArch64::RADDHNv4i32_v4i16: |
| case AArch64::RADDHNv8i16_v8i8: |
| case AArch64::RORVWr: |
| case AArch64::RORVXr: |
| case AArch64::RSUBHNv2i64_v2i32: |
| case AArch64::RSUBHNv4i32_v4i16: |
| case AArch64::RSUBHNv8i16_v8i8: |
| case AArch64::SABDLv16i8_v8i16: |
| case AArch64::SABDLv2i32_v2i64: |
| case AArch64::SABDLv4i16_v4i32: |
| case AArch64::SABDLv4i32_v2i64: |
| case AArch64::SABDLv8i16_v4i32: |
| case AArch64::SABDLv8i8_v8i16: |
| case AArch64::SABDv16i8: |
| case AArch64::SABDv2i32: |
| case AArch64::SABDv4i16: |
| case AArch64::SABDv4i32: |
| case AArch64::SABDv8i16: |
| case AArch64::SABDv8i8: |
| case AArch64::SADDLv16i8_v8i16: |
| case AArch64::SADDLv2i32_v2i64: |
| case AArch64::SADDLv4i16_v4i32: |
| case AArch64::SADDLv4i32_v2i64: |
| case AArch64::SADDLv8i16_v4i32: |
| case AArch64::SADDLv8i8_v8i16: |
| case AArch64::SADDWv16i8_v8i16: |
| case AArch64::SADDWv2i32_v2i64: |
| case AArch64::SADDWv4i16_v4i32: |
| case AArch64::SADDWv4i32_v2i64: |
| case AArch64::SADDWv8i16_v4i32: |
| case AArch64::SADDWv8i8_v8i16: |
| case AArch64::SBCSWr: |
| case AArch64::SBCSXr: |
| case AArch64::SBCWr: |
| case AArch64::SBCXr: |
| case AArch64::SDIVWr: |
| case AArch64::SDIVXr: |
| case AArch64::SHADDv16i8: |
| case AArch64::SHADDv2i32: |
| case AArch64::SHADDv4i16: |
| case AArch64::SHADDv4i32: |
| case AArch64::SHADDv8i16: |
| case AArch64::SHADDv8i8: |
| case AArch64::SHSUBv16i8: |
| case AArch64::SHSUBv2i32: |
| case AArch64::SHSUBv4i16: |
| case AArch64::SHSUBv4i32: |
| case AArch64::SHSUBv8i16: |
| case AArch64::SHSUBv8i8: |
| case AArch64::SMAXPv16i8: |
| case AArch64::SMAXPv2i32: |
| case AArch64::SMAXPv4i16: |
| case AArch64::SMAXPv4i32: |
| case AArch64::SMAXPv8i16: |
| case AArch64::SMAXPv8i8: |
| case AArch64::SMAXv16i8: |
| case AArch64::SMAXv2i32: |
| case AArch64::SMAXv4i16: |
| case AArch64::SMAXv4i32: |
| case AArch64::SMAXv8i16: |
| case AArch64::SMAXv8i8: |
| case AArch64::SMINPv16i8: |
| case AArch64::SMINPv2i32: |
| case AArch64::SMINPv4i16: |
| case AArch64::SMINPv4i32: |
| case AArch64::SMINPv8i16: |
| case AArch64::SMINPv8i8: |
| case AArch64::SMINv16i8: |
| case AArch64::SMINv2i32: |
| case AArch64::SMINv4i16: |
| case AArch64::SMINv4i32: |
| case AArch64::SMINv8i16: |
| case AArch64::SMINv8i8: |
| case AArch64::SMULLv16i8_v8i16: |
| case AArch64::SMULLv2i32_v2i64: |
| case AArch64::SMULLv4i16_v4i32: |
| case AArch64::SMULLv4i32_v2i64: |
| case AArch64::SMULLv8i16_v4i32: |
| case AArch64::SMULLv8i8_v8i16: |
| case AArch64::SQADDv16i8: |
| case AArch64::SQADDv1i16: |
| case AArch64::SQADDv1i32: |
| case AArch64::SQADDv1i64: |
| case AArch64::SQADDv1i8: |
| case AArch64::SQADDv2i32: |
| case AArch64::SQADDv2i64: |
| case AArch64::SQADDv4i16: |
| case AArch64::SQADDv4i32: |
| case AArch64::SQADDv8i16: |
| case AArch64::SQADDv8i8: |
| case AArch64::SQDMULHv1i16: |
| case AArch64::SQDMULHv1i32: |
| case AArch64::SQDMULHv2i32: |
| case AArch64::SQDMULHv4i16: |
| case AArch64::SQDMULHv4i32: |
| case AArch64::SQDMULHv8i16: |
| case AArch64::SQDMULLi16: |
| case AArch64::SQDMULLi32: |
| case AArch64::SQDMULLv2i32_v2i64: |
| case AArch64::SQDMULLv4i16_v4i32: |
| case AArch64::SQDMULLv4i32_v2i64: |
| case AArch64::SQDMULLv8i16_v4i32: |
| case AArch64::SQRDMULHv1i16: |
| case AArch64::SQRDMULHv1i32: |
| case AArch64::SQRDMULHv2i32: |
| case AArch64::SQRDMULHv4i16: |
| case AArch64::SQRDMULHv4i32: |
| case AArch64::SQRDMULHv8i16: |
| case AArch64::SQRSHLv16i8: |
| case AArch64::SQRSHLv1i16: |
| case AArch64::SQRSHLv1i32: |
| case AArch64::SQRSHLv1i64: |
| case AArch64::SQRSHLv1i8: |
| case AArch64::SQRSHLv2i32: |
| case AArch64::SQRSHLv2i64: |
| case AArch64::SQRSHLv4i16: |
| case AArch64::SQRSHLv4i32: |
| case AArch64::SQRSHLv8i16: |
| case AArch64::SQRSHLv8i8: |
| case AArch64::SQSHLv16i8: |
| case AArch64::SQSHLv1i16: |
| case AArch64::SQSHLv1i32: |
| case AArch64::SQSHLv1i64: |
| case AArch64::SQSHLv1i8: |
| case AArch64::SQSHLv2i32: |
| case AArch64::SQSHLv2i64: |
| case AArch64::SQSHLv4i16: |
| case AArch64::SQSHLv4i32: |
| case AArch64::SQSHLv8i16: |
| case AArch64::SQSHLv8i8: |
| case AArch64::SQSUBv16i8: |
| case AArch64::SQSUBv1i16: |
| case AArch64::SQSUBv1i32: |
| case AArch64::SQSUBv1i64: |
| case AArch64::SQSUBv1i8: |
| case AArch64::SQSUBv2i32: |
| case AArch64::SQSUBv2i64: |
| case AArch64::SQSUBv4i16: |
| case AArch64::SQSUBv4i32: |
| case AArch64::SQSUBv8i16: |
| case AArch64::SQSUBv8i8: |
| case AArch64::SRHADDv16i8: |
| case AArch64::SRHADDv2i32: |
| case AArch64::SRHADDv4i16: |
| case AArch64::SRHADDv4i32: |
| case AArch64::SRHADDv8i16: |
| case AArch64::SRHADDv8i8: |
| case AArch64::SRSHLv16i8: |
| case AArch64::SRSHLv1i64: |
| case AArch64::SRSHLv2i32: |
| case AArch64::SRSHLv2i64: |
| case AArch64::SRSHLv4i16: |
| case AArch64::SRSHLv4i32: |
| case AArch64::SRSHLv8i16: |
| case AArch64::SRSHLv8i8: |
| case AArch64::SSHLv16i8: |
| case AArch64::SSHLv1i64: |
| case AArch64::SSHLv2i32: |
| case AArch64::SSHLv2i64: |
| case AArch64::SSHLv4i16: |
| case AArch64::SSHLv4i32: |
| case AArch64::SSHLv8i16: |
| case AArch64::SSHLv8i8: |
| case AArch64::SSUBLv16i8_v8i16: |
| case AArch64::SSUBLv2i32_v2i64: |
| case AArch64::SSUBLv4i16_v4i32: |
| case AArch64::SSUBLv4i32_v2i64: |
| case AArch64::SSUBLv8i16_v4i32: |
| case AArch64::SSUBLv8i8_v8i16: |
| case AArch64::SSUBWv16i8_v8i16: |
| case AArch64::SSUBWv2i32_v2i64: |
| case AArch64::SSUBWv4i16_v4i32: |
| case AArch64::SSUBWv4i32_v2i64: |
| case AArch64::SSUBWv8i16_v4i32: |
| case AArch64::SSUBWv8i8_v8i16: |
| case AArch64::SUBHNv2i64_v2i32: |
| case AArch64::SUBHNv4i32_v4i16: |
| case AArch64::SUBHNv8i16_v8i8: |
| case AArch64::SUBP: |
| case AArch64::SUBPS: |
| case AArch64::SUBv16i8: |
| case AArch64::SUBv1i64: |
| case AArch64::SUBv2i32: |
| case AArch64::SUBv2i64: |
| case AArch64::SUBv4i16: |
| case AArch64::SUBv4i32: |
| case AArch64::SUBv8i16: |
| case AArch64::SUBv8i8: |
| case AArch64::TRN1v16i8: |
| case AArch64::TRN1v2i32: |
| case AArch64::TRN1v2i64: |
| case AArch64::TRN1v4i16: |
| case AArch64::TRN1v4i32: |
| case AArch64::TRN1v8i16: |
| case AArch64::TRN1v8i8: |
| case AArch64::TRN2v16i8: |
| case AArch64::TRN2v2i32: |
| case AArch64::TRN2v2i64: |
| case AArch64::TRN2v4i16: |
| case AArch64::TRN2v4i32: |
| case AArch64::TRN2v8i16: |
| case AArch64::TRN2v8i8: |
| case AArch64::UABDLv16i8_v8i16: |
| case AArch64::UABDLv2i32_v2i64: |
| case AArch64::UABDLv4i16_v4i32: |
| case AArch64::UABDLv4i32_v2i64: |
| case AArch64::UABDLv8i16_v4i32: |
| case AArch64::UABDLv8i8_v8i16: |
| case AArch64::UABDv16i8: |
| case AArch64::UABDv2i32: |
| case AArch64::UABDv4i16: |
| case AArch64::UABDv4i32: |
| case AArch64::UABDv8i16: |
| case AArch64::UABDv8i8: |
| case AArch64::UADDLv16i8_v8i16: |
| case AArch64::UADDLv2i32_v2i64: |
| case AArch64::UADDLv4i16_v4i32: |
| case AArch64::UADDLv4i32_v2i64: |
| case AArch64::UADDLv8i16_v4i32: |
| case AArch64::UADDLv8i8_v8i16: |
| case AArch64::UADDWv16i8_v8i16: |
| case AArch64::UADDWv2i32_v2i64: |
| case AArch64::UADDWv4i16_v4i32: |
| case AArch64::UADDWv4i32_v2i64: |
| case AArch64::UADDWv8i16_v4i32: |
| case AArch64::UADDWv8i8_v8i16: |
| case AArch64::UDIVWr: |
| case AArch64::UDIVXr: |
| case AArch64::UHADDv16i8: |
| case AArch64::UHADDv2i32: |
| case AArch64::UHADDv4i16: |
| case AArch64::UHADDv4i32: |
| case AArch64::UHADDv8i16: |
| case AArch64::UHADDv8i8: |
| case AArch64::UHSUBv16i8: |
| case AArch64::UHSUBv2i32: |
| case AArch64::UHSUBv4i16: |
| case AArch64::UHSUBv4i32: |
| case AArch64::UHSUBv8i16: |
| case AArch64::UHSUBv8i8: |
| case AArch64::UMAXPv16i8: |
| case AArch64::UMAXPv2i32: |
| case AArch64::UMAXPv4i16: |
| case AArch64::UMAXPv4i32: |
| case AArch64::UMAXPv8i16: |
| case AArch64::UMAXPv8i8: |
| case AArch64::UMAXv16i8: |
| case AArch64::UMAXv2i32: |
| case AArch64::UMAXv4i16: |
| case AArch64::UMAXv4i32: |
| case AArch64::UMAXv8i16: |
| case AArch64::UMAXv8i8: |
| case AArch64::UMINPv16i8: |
| case AArch64::UMINPv2i32: |
| case AArch64::UMINPv4i16: |
| case AArch64::UMINPv4i32: |
| case AArch64::UMINPv8i16: |
| case AArch64::UMINPv8i8: |
| case AArch64::UMINv16i8: |
| case AArch64::UMINv2i32: |
| case AArch64::UMINv4i16: |
| case AArch64::UMINv4i32: |
| case AArch64::UMINv8i16: |
| case AArch64::UMINv8i8: |
| case AArch64::UMULLv16i8_v8i16: |
| case AArch64::UMULLv2i32_v2i64: |
| case AArch64::UMULLv4i16_v4i32: |
| case AArch64::UMULLv4i32_v2i64: |
| case AArch64::UMULLv8i16_v4i32: |
| case AArch64::UMULLv8i8_v8i16: |
| case AArch64::UQADDv16i8: |
| case AArch64::UQADDv1i16: |
| case AArch64::UQADDv1i32: |
| case AArch64::UQADDv1i64: |
| case AArch64::UQADDv1i8: |
| case AArch64::UQADDv2i32: |
| case AArch64::UQADDv2i64: |
| case AArch64::UQADDv4i16: |
| case AArch64::UQADDv4i32: |
| case AArch64::UQADDv8i16: |
| case AArch64::UQADDv8i8: |
| case AArch64::UQRSHLv16i8: |
| case AArch64::UQRSHLv1i16: |
| case AArch64::UQRSHLv1i32: |
| case AArch64::UQRSHLv1i64: |
| case AArch64::UQRSHLv1i8: |
| case AArch64::UQRSHLv2i32: |
| case AArch64::UQRSHLv2i64: |
| case AArch64::UQRSHLv4i16: |
| case AArch64::UQRSHLv4i32: |
| case AArch64::UQRSHLv8i16: |
| case AArch64::UQRSHLv8i8: |
| case AArch64::UQSHLv16i8: |
| case AArch64::UQSHLv1i16: |
| case AArch64::UQSHLv1i32: |
| case AArch64::UQSHLv1i64: |
| case AArch64::UQSHLv1i8: |
| case AArch64::UQSHLv2i32: |
| case AArch64::UQSHLv2i64: |
| case AArch64::UQSHLv4i16: |
| case AArch64::UQSHLv4i32: |
| case AArch64::UQSHLv8i16: |
| case AArch64::UQSHLv8i8: |
| case AArch64::UQSUBv16i8: |
| case AArch64::UQSUBv1i16: |
| case AArch64::UQSUBv1i32: |
| case AArch64::UQSUBv1i64: |
| case AArch64::UQSUBv1i8: |
| case AArch64::UQSUBv2i32: |
| case AArch64::UQSUBv2i64: |
| case AArch64::UQSUBv4i16: |
| case AArch64::UQSUBv4i32: |
| case AArch64::UQSUBv8i16: |
| case AArch64::UQSUBv8i8: |
| case AArch64::URHADDv16i8: |
| case AArch64::URHADDv2i32: |
| case AArch64::URHADDv4i16: |
| case AArch64::URHADDv4i32: |
| case AArch64::URHADDv8i16: |
| case AArch64::URHADDv8i8: |
| case AArch64::URSHLv16i8: |
| case AArch64::URSHLv1i64: |
| case AArch64::URSHLv2i32: |
| case AArch64::URSHLv2i64: |
| case AArch64::URSHLv4i16: |
| case AArch64::URSHLv4i32: |
| case AArch64::URSHLv8i16: |
| case AArch64::URSHLv8i8: |
| case AArch64::USHLv16i8: |
| case AArch64::USHLv1i64: |
| case AArch64::USHLv2i32: |
| case AArch64::USHLv2i64: |
| case AArch64::USHLv4i16: |
| case AArch64::USHLv4i32: |
| case AArch64::USHLv8i16: |
| case AArch64::USHLv8i8: |
| case AArch64::USUBLv16i8_v8i16: |
| case AArch64::USUBLv2i32_v2i64: |
| case AArch64::USUBLv4i16_v4i32: |
| case AArch64::USUBLv4i32_v2i64: |
| case AArch64::USUBLv8i16_v4i32: |
| case AArch64::USUBLv8i8_v8i16: |
| case AArch64::USUBWv16i8_v8i16: |
| case AArch64::USUBWv2i32_v2i64: |
| case AArch64::USUBWv4i16_v4i32: |
| case AArch64::USUBWv4i32_v2i64: |
| case AArch64::USUBWv8i16_v4i32: |
| case AArch64::USUBWv8i8_v8i16: |
| case AArch64::UZP1v16i8: |
| case AArch64::UZP1v2i32: |
| case AArch64::UZP1v2i64: |
| case AArch64::UZP1v4i16: |
| case AArch64::UZP1v4i32: |
| case AArch64::UZP1v8i16: |
| case AArch64::UZP1v8i8: |
| case AArch64::UZP2v16i8: |
| case AArch64::UZP2v2i32: |
| case AArch64::UZP2v2i64: |
| case AArch64::UZP2v4i16: |
| case AArch64::UZP2v4i32: |
| case AArch64::UZP2v8i16: |
| case AArch64::UZP2v8i8: |
| case AArch64::ZIP1v16i8: |
| case AArch64::ZIP1v2i32: |
| case AArch64::ZIP1v2i64: |
| case AArch64::ZIP1v4i16: |
| case AArch64::ZIP1v4i32: |
| case AArch64::ZIP1v8i16: |
| case AArch64::ZIP1v8i8: |
| case AArch64::ZIP2v16i8: |
| case AArch64::ZIP2v2i32: |
| case AArch64::ZIP2v2i64: |
| case AArch64::ZIP2v4i16: |
| case AArch64::ZIP2v4i32: |
| case AArch64::ZIP2v8i16: |
| case AArch64::ZIP2v8i8: { |
| // op: Rd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: Rm |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 16; |
| Value |= op; |
| break; |
| } |
| case AArch64::FMADDDrrr: |
| case AArch64::FMADDHrrr: |
| case AArch64::FMADDSrrr: |
| case AArch64::FMSUBDrrr: |
| case AArch64::FMSUBHrrr: |
| case AArch64::FMSUBSrrr: |
| case AArch64::FNMADDDrrr: |
| case AArch64::FNMADDHrrr: |
| case AArch64::FNMADDSrrr: |
| case AArch64::FNMSUBDrrr: |
| case AArch64::FNMSUBHrrr: |
| case AArch64::FNMSUBSrrr: |
| case AArch64::MADDWrrr: |
| case AArch64::MADDXrrr: |
| case AArch64::MSUBWrrr: |
| case AArch64::MSUBXrrr: |
| case AArch64::SMADDLrrr: |
| case AArch64::SMSUBLrrr: |
| case AArch64::UMADDLrrr: |
| case AArch64::UMSUBLrrr: { |
| // op: Rd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: Rm |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 16; |
| Value |= op; |
| // op: Ra |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 10; |
| Value |= op; |
| break; |
| } |
| case AArch64::CSELWr: |
| case AArch64::CSELXr: |
| case AArch64::CSINCWr: |
| case AArch64::CSINCXr: |
| case AArch64::CSINVWr: |
| case AArch64::CSINVXr: |
| case AArch64::CSNEGWr: |
| case AArch64::CSNEGXr: |
| case AArch64::FCSELDrrr: |
| case AArch64::FCSELHrrr: |
| case AArch64::FCSELSrrr: { |
| // op: Rd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: Rm |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 16; |
| Value |= op; |
| // op: cond |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(15); |
| op <<= 12; |
| Value |= op; |
| break; |
| } |
| case AArch64::ADDSXrx64: |
| case AArch64::ADDXrx64: |
| case AArch64::SUBSXrx64: |
| case AArch64::SUBXrx64: { |
| // op: Rd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: Rm |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 16; |
| Value |= op; |
| // op: ext |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| Value |= (op & UINT64_C(32)) << 10; |
| Value |= (op & UINT64_C(7)) << 10; |
| break; |
| } |
| case AArch64::ADDSWrx: |
| case AArch64::ADDSXrx: |
| case AArch64::ADDWrx: |
| case AArch64::ADDXrx: |
| case AArch64::SUBSWrx: |
| case AArch64::SUBSXrx: |
| case AArch64::SUBWrx: |
| case AArch64::SUBXrx: { |
| // op: Rd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: Rm |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 16; |
| Value |= op; |
| // op: ext |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(63); |
| op <<= 10; |
| Value |= op; |
| break; |
| } |
| case AArch64::FMULXv1i32_indexed: |
| case AArch64::FMULXv2i32_indexed: |
| case AArch64::FMULXv4i32_indexed: |
| case AArch64::FMULv1i32_indexed: |
| case AArch64::FMULv2i32_indexed: |
| case AArch64::FMULv4i32_indexed: |
| case AArch64::MULv2i32_indexed: |
| case AArch64::MULv4i32_indexed: |
| case AArch64::SMULLv2i32_indexed: |
| case AArch64::SMULLv4i32_indexed: |
| case AArch64::SQDMULHv1i32_indexed: |
| case AArch64::SQDMULHv2i32_indexed: |
| case AArch64::SQDMULHv4i32_indexed: |
| case AArch64::SQDMULLv1i64_indexed: |
| case AArch64::SQDMULLv2i32_indexed: |
| case AArch64::SQDMULLv4i32_indexed: |
| case AArch64::SQRDMULHv1i32_indexed: |
| case AArch64::SQRDMULHv2i32_indexed: |
| case AArch64::SQRDMULHv4i32_indexed: |
| case AArch64::UMULLv2i32_indexed: |
| case AArch64::UMULLv4i32_indexed: { |
| // op: Rd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: Rm |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 16; |
| Value |= op; |
| // op: idx |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| Value |= (op & UINT64_C(1)) << 21; |
| Value |= (op & UINT64_C(2)) << 10; |
| break; |
| } |
| case AArch64::FMULXv1i64_indexed: |
| case AArch64::FMULXv2i64_indexed: |
| case AArch64::FMULv1i64_indexed: |
| case AArch64::FMULv2i64_indexed: { |
| // op: Rd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: Rm |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 16; |
| Value |= op; |
| // op: idx |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(1); |
| op <<= 11; |
| Value |= op; |
| break; |
| } |
| case AArch64::EXTv16i8: { |
| // op: Rd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: Rm |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 16; |
| Value |= op; |
| // op: imm |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(15); |
| op <<= 11; |
| Value |= op; |
| break; |
| } |
| case AArch64::EXTRWrri: { |
| // op: Rd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: Rm |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 16; |
| Value |= op; |
| // op: imm |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 10; |
| Value |= op; |
| break; |
| } |
| case AArch64::EXTRXrri: { |
| // op: Rd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: Rm |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 16; |
| Value |= op; |
| // op: imm |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(63); |
| op <<= 10; |
| Value |= op; |
| break; |
| } |
| case AArch64::EXTv8i8: { |
| // op: Rd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: Rm |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 16; |
| Value |= op; |
| // op: imm |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(7); |
| op <<= 11; |
| Value |= op; |
| break; |
| } |
| case AArch64::FCADDv2f32: |
| case AArch64::FCADDv2f64: |
| case AArch64::FCADDv4f16: |
| case AArch64::FCADDv4f32: |
| case AArch64::FCADDv8f16: { |
| // op: Rd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: Rm |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 16; |
| Value |= op; |
| // op: rot |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(1); |
| op <<= 12; |
| Value |= op; |
| break; |
| } |
| case AArch64::SMULHrr: |
| case AArch64::UMULHrr: { |
| // op: Rd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: Rm |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 16; |
| Value |= op; |
| Value = fixMulHigh(MI, Value, STI); |
| break; |
| } |
| case AArch64::DUPv2i64lane: |
| case AArch64::UMOVvi64: { |
| // op: Rd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: idx |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(1); |
| op <<= 20; |
| Value |= op; |
| break; |
| } |
| case AArch64::DUPv16i8lane: |
| case AArch64::DUPv8i8lane: |
| case AArch64::SMOVvi8to32: |
| case AArch64::SMOVvi8to64: |
| case AArch64::UMOVvi8: { |
| // op: Rd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: idx |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(15); |
| op <<= 17; |
| Value |= op; |
| break; |
| } |
| case AArch64::DUPv2i32lane: |
| case AArch64::DUPv4i32lane: |
| case AArch64::SMOVvi32to64: |
| case AArch64::UMOVvi32: { |
| // op: Rd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: idx |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(3); |
| op <<= 19; |
| Value |= op; |
| break; |
| } |
| case AArch64::DUPv4i16lane: |
| case AArch64::DUPv8i16lane: |
| case AArch64::SMOVvi16to32: |
| case AArch64::SMOVvi16to64: |
| case AArch64::UMOVvi16: { |
| // op: Rd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: idx |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(7); |
| op <<= 18; |
| Value |= op; |
| break; |
| } |
| case AArch64::ADDSWri: |
| case AArch64::ADDSXri: |
| case AArch64::ADDWri: |
| case AArch64::ADDXri: |
| case AArch64::SUBSWri: |
| case AArch64::SUBSXri: |
| case AArch64::SUBWri: |
| case AArch64::SUBXri: { |
| // op: Rd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: imm |
| op = getAddSubImmOpValue(MI, 2, Fixups, STI); |
| op &= UINT64_C(16383); |
| op <<= 10; |
| Value |= op; |
| break; |
| } |
| case AArch64::ANDSWri: |
| case AArch64::ANDWri: |
| case AArch64::EORWri: |
| case AArch64::ORRWri: { |
| // op: Rd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: imm |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(4095); |
| op <<= 10; |
| Value |= op; |
| break; |
| } |
| case AArch64::ANDSXri: |
| case AArch64::ANDXri: |
| case AArch64::EORXri: |
| case AArch64::ORRXri: { |
| // op: Rd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: imm |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(8191); |
| op <<= 10; |
| Value |= op; |
| break; |
| } |
| case AArch64::SHLv4i16_shift: |
| case AArch64::SHLv8i16_shift: |
| case AArch64::SQSHLUh: |
| case AArch64::SQSHLUv4i16_shift: |
| case AArch64::SQSHLUv8i16_shift: |
| case AArch64::SQSHLh: |
| case AArch64::SQSHLv4i16_shift: |
| case AArch64::SQSHLv8i16_shift: |
| case AArch64::SSHLLv4i16_shift: |
| case AArch64::SSHLLv8i16_shift: |
| case AArch64::UQSHLh: |
| case AArch64::UQSHLv4i16_shift: |
| case AArch64::UQSHLv8i16_shift: |
| case AArch64::USHLLv4i16_shift: |
| case AArch64::USHLLv8i16_shift: { |
| // op: Rd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: imm |
| op = getVecShiftL16OpValue(MI, 2, Fixups, STI); |
| op &= UINT64_C(15); |
| op <<= 16; |
| Value |= op; |
| break; |
| } |
| case AArch64::SHLv2i32_shift: |
| case AArch64::SHLv4i32_shift: |
| case AArch64::SQSHLUs: |
| case AArch64::SQSHLUv2i32_shift: |
| case AArch64::SQSHLUv4i32_shift: |
| case AArch64::SQSHLs: |
| case AArch64::SQSHLv2i32_shift: |
| case AArch64::SQSHLv4i32_shift: |
| case AArch64::SSHLLv2i32_shift: |
| case AArch64::SSHLLv4i32_shift: |
| case AArch64::UQSHLs: |
| case AArch64::UQSHLv2i32_shift: |
| case AArch64::UQSHLv4i32_shift: |
| case AArch64::USHLLv2i32_shift: |
| case AArch64::USHLLv4i32_shift: { |
| // op: Rd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: imm |
| op = getVecShiftL32OpValue(MI, 2, Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 16; |
| Value |= op; |
| break; |
| } |
| case AArch64::SHLd: |
| case AArch64::SHLv2i64_shift: |
| case AArch64::SQSHLUd: |
| case AArch64::SQSHLUv2i64_shift: |
| case AArch64::SQSHLd: |
| case AArch64::SQSHLv2i64_shift: |
| case AArch64::UQSHLd: |
| case AArch64::UQSHLv2i64_shift: { |
| // op: Rd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: imm |
| op = getVecShiftL64OpValue(MI, 2, Fixups, STI); |
| op &= UINT64_C(63); |
| op <<= 16; |
| Value |= op; |
| break; |
| } |
| case AArch64::SHLv16i8_shift: |
| case AArch64::SHLv8i8_shift: |
| case AArch64::SQSHLUb: |
| case AArch64::SQSHLUv16i8_shift: |
| case AArch64::SQSHLUv8i8_shift: |
| case AArch64::SQSHLb: |
| case AArch64::SQSHLv16i8_shift: |
| case AArch64::SQSHLv8i8_shift: |
| case AArch64::SSHLLv16i8_shift: |
| case AArch64::SSHLLv8i8_shift: |
| case AArch64::UQSHLb: |
| case AArch64::UQSHLv16i8_shift: |
| case AArch64::UQSHLv8i8_shift: |
| case AArch64::USHLLv16i8_shift: |
| case AArch64::USHLLv8i8_shift: { |
| // op: Rd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: imm |
| op = getVecShiftL8OpValue(MI, 2, Fixups, STI); |
| op &= UINT64_C(7); |
| op <<= 16; |
| Value |= op; |
| break; |
| } |
| case AArch64::FCVTZSh: |
| case AArch64::FCVTZSv4i16_shift: |
| case AArch64::FCVTZSv8i16_shift: |
| case AArch64::FCVTZUh: |
| case AArch64::FCVTZUv4i16_shift: |
| case AArch64::FCVTZUv8i16_shift: |
| case AArch64::SCVTFh: |
| case AArch64::SCVTFv4i16_shift: |
| case AArch64::SCVTFv8i16_shift: |
| case AArch64::SQRSHRNh: |
| case AArch64::SQRSHRUNh: |
| case AArch64::SQSHRNh: |
| case AArch64::SQSHRUNh: |
| case AArch64::SRSHRv4i16_shift: |
| case AArch64::SRSHRv8i16_shift: |
| case AArch64::SSHRv4i16_shift: |
| case AArch64::SSHRv8i16_shift: |
| case AArch64::UCVTFh: |
| case AArch64::UCVTFv4i16_shift: |
| case AArch64::UCVTFv8i16_shift: |
| case AArch64::UQRSHRNh: |
| case AArch64::UQSHRNh: |
| case AArch64::URSHRv4i16_shift: |
| case AArch64::URSHRv8i16_shift: |
| case AArch64::USHRv4i16_shift: |
| case AArch64::USHRv8i16_shift: { |
| // op: Rd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: imm |
| op = getVecShiftR16OpValue(MI, 2, Fixups, STI); |
| op &= UINT64_C(15); |
| op <<= 16; |
| Value |= op; |
| break; |
| } |
| case AArch64::RSHRNv8i8_shift: |
| case AArch64::SHRNv8i8_shift: |
| case AArch64::SQRSHRNv8i8_shift: |
| case AArch64::SQRSHRUNv8i8_shift: |
| case AArch64::SQSHRNv8i8_shift: |
| case AArch64::SQSHRUNv8i8_shift: |
| case AArch64::UQRSHRNv8i8_shift: |
| case AArch64::UQSHRNv8i8_shift: { |
| // op: Rd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: imm |
| op = getVecShiftR16OpValue(MI, 2, Fixups, STI); |
| op &= UINT64_C(7); |
| op <<= 16; |
| Value |= op; |
| break; |
| } |
| case AArch64::RSHRNv4i16_shift: |
| case AArch64::SHRNv4i16_shift: |
| case AArch64::SQRSHRNv4i16_shift: |
| case AArch64::SQRSHRUNv4i16_shift: |
| case AArch64::SQSHRNv4i16_shift: |
| case AArch64::SQSHRUNv4i16_shift: |
| case AArch64::UQRSHRNv4i16_shift: |
| case AArch64::UQSHRNv4i16_shift: { |
| // op: Rd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: imm |
| op = getVecShiftR32OpValue(MI, 2, Fixups, STI); |
| op &= UINT64_C(15); |
| op <<= 16; |
| Value |= op; |
| break; |
| } |
| case AArch64::FCVTZSs: |
| case AArch64::FCVTZSv2i32_shift: |
| case AArch64::FCVTZSv4i32_shift: |
| case AArch64::FCVTZUs: |
| case AArch64::FCVTZUv2i32_shift: |
| case AArch64::FCVTZUv4i32_shift: |
| case AArch64::SCVTFs: |
| case AArch64::SCVTFv2i32_shift: |
| case AArch64::SCVTFv4i32_shift: |
| case AArch64::SQRSHRNs: |
| case AArch64::SQRSHRUNs: |
| case AArch64::SQSHRNs: |
| case AArch64::SQSHRUNs: |
| case AArch64::SRSHRv2i32_shift: |
| case AArch64::SRSHRv4i32_shift: |
| case AArch64::SSHRv2i32_shift: |
| case AArch64::SSHRv4i32_shift: |
| case AArch64::UCVTFs: |
| case AArch64::UCVTFv2i32_shift: |
| case AArch64::UCVTFv4i32_shift: |
| case AArch64::UQRSHRNs: |
| case AArch64::UQSHRNs: |
| case AArch64::URSHRv2i32_shift: |
| case AArch64::URSHRv4i32_shift: |
| case AArch64::USHRv2i32_shift: |
| case AArch64::USHRv4i32_shift: { |
| // op: Rd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: imm |
| op = getVecShiftR32OpValue(MI, 2, Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 16; |
| Value |= op; |
| break; |
| } |
| case AArch64::RSHRNv2i32_shift: |
| case AArch64::SHRNv2i32_shift: |
| case AArch64::SQRSHRNv2i32_shift: |
| case AArch64::SQRSHRUNv2i32_shift: |
| case AArch64::SQSHRNv2i32_shift: |
| case AArch64::SQSHRUNv2i32_shift: |
| case AArch64::UQRSHRNv2i32_shift: |
| case AArch64::UQSHRNv2i32_shift: { |
| // op: Rd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: imm |
| op = getVecShiftR64OpValue(MI, 2, Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 16; |
| Value |= op; |
| break; |
| } |
| case AArch64::FCVTZSd: |
| case AArch64::FCVTZSv2i64_shift: |
| case AArch64::FCVTZUd: |
| case AArch64::FCVTZUv2i64_shift: |
| case AArch64::SCVTFd: |
| case AArch64::SCVTFv2i64_shift: |
| case AArch64::SRSHRd: |
| case AArch64::SRSHRv2i64_shift: |
| case AArch64::SSHRd: |
| case AArch64::SSHRv2i64_shift: |
| case AArch64::UCVTFd: |
| case AArch64::UCVTFv2i64_shift: |
| case AArch64::URSHRd: |
| case AArch64::URSHRv2i64_shift: |
| case AArch64::USHRd: |
| case AArch64::USHRv2i64_shift: { |
| // op: Rd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: imm |
| op = getVecShiftR64OpValue(MI, 2, Fixups, STI); |
| op &= UINT64_C(63); |
| op <<= 16; |
| Value |= op; |
| break; |
| } |
| case AArch64::SQRSHRNb: |
| case AArch64::SQRSHRUNb: |
| case AArch64::SQSHRNb: |
| case AArch64::SQSHRUNb: |
| case AArch64::SRSHRv16i8_shift: |
| case AArch64::SRSHRv8i8_shift: |
| case AArch64::SSHRv16i8_shift: |
| case AArch64::SSHRv8i8_shift: |
| case AArch64::UQRSHRNb: |
| case AArch64::UQSHRNb: |
| case AArch64::URSHRv16i8_shift: |
| case AArch64::URSHRv8i8_shift: |
| case AArch64::USHRv16i8_shift: |
| case AArch64::USHRv8i8_shift: { |
| // op: Rd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: imm |
| op = getVecShiftR8OpValue(MI, 2, Fixups, STI); |
| op &= UINT64_C(7); |
| op <<= 16; |
| Value |= op; |
| break; |
| } |
| case AArch64::ADDG: |
| case AArch64::SUBG: { |
| // op: Rd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: imm6 |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(63); |
| op <<= 16; |
| Value |= op; |
| // op: imm4 |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(15); |
| op <<= 10; |
| Value |= op; |
| break; |
| } |
| case AArch64::SBFMWri: |
| case AArch64::UBFMWri: { |
| // op: Rd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: immr |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 16; |
| Value |= op; |
| // op: imms |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 10; |
| Value |= op; |
| break; |
| } |
| case AArch64::SBFMXri: |
| case AArch64::UBFMXri: { |
| // op: Rd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: immr |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(63); |
| op <<= 16; |
| Value |= op; |
| // op: imms |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(63); |
| op <<= 10; |
| Value |= op; |
| break; |
| } |
| case AArch64::FCVTZSSWDri: |
| case AArch64::FCVTZSSWHri: |
| case AArch64::FCVTZSSWSri: |
| case AArch64::FCVTZUSWDri: |
| case AArch64::FCVTZUSWHri: |
| case AArch64::FCVTZUSWSri: |
| case AArch64::SCVTFSWDri: |
| case AArch64::SCVTFSWHri: |
| case AArch64::SCVTFSWSri: |
| case AArch64::UCVTFSWDri: |
| case AArch64::UCVTFSWHri: |
| case AArch64::UCVTFSWSri: { |
| // op: Rd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: scale |
| op = getFixedPointScaleOpValue(MI, 2, Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 10; |
| Value |= op; |
| break; |
| } |
| case AArch64::FCVTZSSXDri: |
| case AArch64::FCVTZSSXHri: |
| case AArch64::FCVTZSSXSri: |
| case AArch64::FCVTZUSXDri: |
| case AArch64::FCVTZUSXHri: |
| case AArch64::FCVTZUSXSri: |
| case AArch64::SCVTFSXDri: |
| case AArch64::SCVTFSXHri: |
| case AArch64::SCVTFSXSri: |
| case AArch64::UCVTFSXDri: |
| case AArch64::UCVTFSXHri: |
| case AArch64::UCVTFSXSri: { |
| // op: Rd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: scale |
| op = getFixedPointScaleOpValue(MI, 2, Fixups, STI); |
| op &= UINT64_C(63); |
| op <<= 10; |
| Value |= op; |
| break; |
| } |
| case AArch64::BFMWri: { |
| // op: Rd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: immr |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 16; |
| Value |= op; |
| // op: imms |
| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 10; |
| Value |= op; |
| break; |
| } |
| case AArch64::BFMXri: { |
| // op: Rd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: immr |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(63); |
| op <<= 16; |
| Value |= op; |
| // op: imms |
| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
| op &= UINT64_C(63); |
| op <<= 10; |
| Value |= op; |
| break; |
| } |
| case AArch64::FMOVDi: |
| case AArch64::FMOVHi: |
| case AArch64::FMOVSi: { |
| // op: Rd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: imm |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(255); |
| op <<= 13; |
| Value |= op; |
| break; |
| } |
| case AArch64::MOVNWi: |
| case AArch64::MOVNXi: { |
| // op: Rd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: imm |
| op = getMoveWideImmOpValue(MI, 1, Fixups, STI); |
| op &= UINT64_C(65535); |
| op <<= 5; |
| Value |= op; |
| // op: shift |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(48); |
| op <<= 17; |
| Value |= op; |
| break; |
| } |
| case AArch64::MOVZWi: |
| case AArch64::MOVZXi: { |
| // op: Rd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: imm |
| op = getMoveWideImmOpValue(MI, 1, Fixups, STI); |
| op &= UINT64_C(65535); |
| op <<= 5; |
| Value |= op; |
| // op: shift |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(48); |
| op <<= 17; |
| Value |= op; |
| Value = fixMOVZ(MI, Value, STI); |
| break; |
| } |
| case AArch64::MOVKWi: |
| case AArch64::MOVKXi: { |
| // op: Rd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: imm |
| op = getMoveWideImmOpValue(MI, 2, Fixups, STI); |
| op &= UINT64_C(65535); |
| op <<= 5; |
| Value |= op; |
| // op: shift |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(48); |
| op <<= 17; |
| Value |= op; |
| break; |
| } |
| case AArch64::CNTB_XPiI: |
| case AArch64::CNTD_XPiI: |
| case AArch64::CNTH_XPiI: |
| case AArch64::CNTW_XPiI: { |
| // op: Rd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: imm4 |
| op = getSVEIncDecImm(MI, 2, Fixups, STI); |
| op &= UINT64_C(15); |
| op <<= 16; |
| Value |= op; |
| // op: pattern |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| break; |
| } |
| case AArch64::RDVLI_XI: { |
| // op: Rd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: imm6 |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(63); |
| op <<= 5; |
| Value |= op; |
| break; |
| } |
| case AArch64::FMOVv2f32_ns: |
| case AArch64::FMOVv2f64_ns: |
| case AArch64::FMOVv4f16_ns: |
| case AArch64::FMOVv4f32_ns: |
| case AArch64::FMOVv8f16_ns: |
| case AArch64::MOVID: |
| case AArch64::MOVIv16b_ns: |
| case AArch64::MOVIv2d_ns: |
| case AArch64::MOVIv8b_ns: { |
| // op: Rd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: imm8 |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| Value |= (op & UINT64_C(224)) << 11; |
| Value |= (op & UINT64_C(31)) << 5; |
| break; |
| } |
| case AArch64::MOVIv2s_msl: |
| case AArch64::MOVIv4s_msl: |
| case AArch64::MVNIv2s_msl: |
| case AArch64::MVNIv4s_msl: { |
| // op: Rd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: imm8 |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| Value |= (op & UINT64_C(224)) << 11; |
| Value |= (op & UINT64_C(31)) << 5; |
| // op: shift |
| op = getMoveVecShifterOpValue(MI, 2, Fixups, STI); |
| op &= UINT64_C(1); |
| op <<= 12; |
| Value |= op; |
| break; |
| } |
| case AArch64::MOVIv4i16: |
| case AArch64::MOVIv8i16: |
| case AArch64::MVNIv4i16: |
| case AArch64::MVNIv8i16: { |
| // op: Rd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: imm8 |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| Value |= (op & UINT64_C(224)) << 11; |
| Value |= (op & UINT64_C(31)) << 5; |
| // op: shift |
| op = getVecShifterOpValue(MI, 2, Fixups, STI); |
| op &= UINT64_C(1); |
| op <<= 13; |
| Value |= op; |
| break; |
| } |
| case AArch64::MOVIv2i32: |
| case AArch64::MOVIv4i32: |
| case AArch64::MVNIv2i32: |
| case AArch64::MVNIv4i32: { |
| // op: Rd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: imm8 |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| Value |= (op & UINT64_C(224)) << 11; |
| Value |= (op & UINT64_C(31)) << 5; |
| // op: shift |
| op = getVecShifterOpValue(MI, 2, Fixups, STI); |
| op &= UINT64_C(3); |
| op <<= 13; |
| Value |= op; |
| break; |
| } |
| case AArch64::AESDrr: |
| case AArch64::AESErr: |
| case AArch64::FCVTNv4i32: |
| case AArch64::FCVTNv8i16: |
| case AArch64::FCVTXNv4f32: |
| case AArch64::SADALPv16i8_v8i16: |
| case AArch64::SADALPv2i32_v1i64: |
| case AArch64::SADALPv4i16_v2i32: |
| case AArch64::SADALPv4i32_v2i64: |
| case AArch64::SADALPv8i16_v4i32: |
| case AArch64::SADALPv8i8_v4i16: |
| case AArch64::SHA1SU1rr: |
| case AArch64::SHA256SU0rr: |
| case AArch64::SQXTNv16i8: |
| case AArch64::SQXTNv4i32: |
| case AArch64::SQXTNv8i16: |
| case AArch64::SQXTUNv16i8: |
| case AArch64::SQXTUNv4i32: |
| case AArch64::SQXTUNv8i16: |
| case AArch64::SUQADDv16i8: |
| case AArch64::SUQADDv1i16: |
| case AArch64::SUQADDv1i32: |
| case AArch64::SUQADDv1i64: |
| case AArch64::SUQADDv1i8: |
| case AArch64::SUQADDv2i32: |
| case AArch64::SUQADDv2i64: |
| case AArch64::SUQADDv4i16: |
| case AArch64::SUQADDv4i32: |
| case AArch64::SUQADDv8i16: |
| case AArch64::SUQADDv8i8: |
| case AArch64::UADALPv16i8_v8i16: |
| case AArch64::UADALPv2i32_v1i64: |
| case AArch64::UADALPv4i16_v2i32: |
| case AArch64::UADALPv4i32_v2i64: |
| case AArch64::UADALPv8i16_v4i32: |
| case AArch64::UADALPv8i8_v4i16: |
| case AArch64::UQXTNv16i8: |
| case AArch64::UQXTNv4i32: |
| case AArch64::UQXTNv8i16: |
| case AArch64::USQADDv16i8: |
| case AArch64::USQADDv1i16: |
| case AArch64::USQADDv1i32: |
| case AArch64::USQADDv1i64: |
| case AArch64::USQADDv1i8: |
| case AArch64::USQADDv2i32: |
| case AArch64::USQADDv2i64: |
| case AArch64::USQADDv4i16: |
| case AArch64::USQADDv4i32: |
| case AArch64::USQADDv8i16: |
| case AArch64::USQADDv8i8: |
| case AArch64::XTNv16i8: |
| case AArch64::XTNv4i32: |
| case AArch64::XTNv8i16: { |
| // op: Rd |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| break; |
| } |
| case AArch64::FMLAL2lanev4f16: |
| case AArch64::FMLAL2lanev8f16: |
| case AArch64::FMLALlanev4f16: |
| case AArch64::FMLALlanev8f16: |
| case AArch64::FMLAv1i16_indexed: |
| case AArch64::FMLAv4i16_indexed: |
| case AArch64::FMLAv8i16_indexed: |
| case AArch64::FMLSL2lanev4f16: |
| case AArch64::FMLSL2lanev8f16: |
| case AArch64::FMLSLlanev4f16: |
| case AArch64::FMLSLlanev8f16: |
| case AArch64::FMLSv1i16_indexed: |
| case AArch64::FMLSv4i16_indexed: |
| case AArch64::FMLSv8i16_indexed: |
| case AArch64::MLAv4i16_indexed: |
| case AArch64::MLAv8i16_indexed: |
| case AArch64::MLSv4i16_indexed: |
| case AArch64::MLSv8i16_indexed: |
| case AArch64::SMLALv4i16_indexed: |
| case AArch64::SMLALv8i16_indexed: |
| case AArch64::SMLSLv4i16_indexed: |
| case AArch64::SMLSLv8i16_indexed: |
| case AArch64::SQDMLALv1i32_indexed: |
| case AArch64::SQDMLALv4i16_indexed: |
| case AArch64::SQDMLALv8i16_indexed: |
| case AArch64::SQDMLSLv1i32_indexed: |
| case AArch64::SQDMLSLv4i16_indexed: |
| case AArch64::SQDMLSLv8i16_indexed: |
| case AArch64::SQRDMLAHi16_indexed: |
| case AArch64::SQRDMLAHv4i16_indexed: |
| case AArch64::SQRDMLAHv8i16_indexed: |
| case AArch64::SQRDMLSHi16_indexed: |
| case AArch64::SQRDMLSHv4i16_indexed: |
| case AArch64::SQRDMLSHv8i16_indexed: |
| case AArch64::UMLALv4i16_indexed: |
| case AArch64::UMLALv8i16_indexed: |
| case AArch64::UMLSLv4i16_indexed: |
| case AArch64::UMLSLv8i16_indexed: { |
| // op: Rd |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: Rm |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(15); |
| op <<= 16; |
| Value |= op; |
| // op: idx |
| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
| Value |= (op & UINT64_C(3)) << 20; |
| Value |= (op & UINT64_C(4)) << 9; |
| break; |
| } |
| case AArch64::ADDHNv2i64_v4i32: |
| case AArch64::ADDHNv4i32_v8i16: |
| case AArch64::ADDHNv8i16_v16i8: |
| case AArch64::BITv16i8: |
| case AArch64::BITv8i8: |
| case AArch64::BSLv16i8: |
| case AArch64::BSLv8i8: |
| case AArch64::FMLAL2v4f16: |
| case AArch64::FMLAL2v8f16: |
| case AArch64::FMLALv4f16: |
| case AArch64::FMLALv8f16: |
| case AArch64::FMLAv2f32: |
| case AArch64::FMLAv2f64: |
| case AArch64::FMLAv4f16: |
| case AArch64::FMLAv4f32: |
| case AArch64::FMLAv8f16: |
| case AArch64::FMLSL2v4f16: |
| case AArch64::FMLSL2v8f16: |
| case AArch64::FMLSLv4f16: |
| case AArch64::FMLSLv8f16: |
| case AArch64::FMLSv2f32: |
| case AArch64::FMLSv2f64: |
| case AArch64::FMLSv4f16: |
| case AArch64::FMLSv4f32: |
| case AArch64::FMLSv8f16: |
| case AArch64::MLAv16i8: |
| case AArch64::MLAv2i32: |
| case AArch64::MLAv4i16: |
| case AArch64::MLAv4i32: |
| case AArch64::MLAv8i16: |
| case AArch64::MLAv8i8: |
| case AArch64::MLSv16i8: |
| case AArch64::MLSv2i32: |
| case AArch64::MLSv4i16: |
| case AArch64::MLSv4i32: |
| case AArch64::MLSv8i16: |
| case AArch64::MLSv8i8: |
| case AArch64::RADDHNv2i64_v4i32: |
| case AArch64::RADDHNv4i32_v8i16: |
| case AArch64::RADDHNv8i16_v16i8: |
| case AArch64::RSUBHNv2i64_v4i32: |
| case AArch64::RSUBHNv4i32_v8i16: |
| case AArch64::RSUBHNv8i16_v16i8: |
| case AArch64::SABALv16i8_v8i16: |
| case AArch64::SABALv2i32_v2i64: |
| case AArch64::SABALv4i16_v4i32: |
| case AArch64::SABALv4i32_v2i64: |
| case AArch64::SABALv8i16_v4i32: |
| case AArch64::SABALv8i8_v8i16: |
| case AArch64::SABAv16i8: |
| case AArch64::SABAv2i32: |
| case AArch64::SABAv4i16: |
| case AArch64::SABAv4i32: |
| case AArch64::SABAv8i16: |
| case AArch64::SABAv8i8: |
| case AArch64::SDOTv16i8: |
| case AArch64::SDOTv8i8: |
| case AArch64::SHA1Crrr: |
| case AArch64::SHA1Mrrr: |
| case AArch64::SHA1Prrr: |
| case AArch64::SHA1SU0rrr: |
| case AArch64::SHA256H2rrr: |
| case AArch64::SHA256Hrrr: |
| case AArch64::SHA256SU1rrr: |
| case AArch64::SMLALv16i8_v8i16: |
| case AArch64::SMLALv2i32_v2i64: |
| case AArch64::SMLALv4i16_v4i32: |
| case AArch64::SMLALv4i32_v2i64: |
| case AArch64::SMLALv8i16_v4i32: |
| case AArch64::SMLALv8i8_v8i16: |
| case AArch64::SMLSLv16i8_v8i16: |
| case AArch64::SMLSLv2i32_v2i64: |
| case AArch64::SMLSLv4i16_v4i32: |
| case AArch64::SMLSLv4i32_v2i64: |
| case AArch64::SMLSLv8i16_v4i32: |
| case AArch64::SMLSLv8i8_v8i16: |
| case AArch64::SQDMLALi16: |
| case AArch64::SQDMLALi32: |
| case AArch64::SQDMLALv2i32_v2i64: |
| case AArch64::SQDMLALv4i16_v4i32: |
| case AArch64::SQDMLALv4i32_v2i64: |
| case AArch64::SQDMLALv8i16_v4i32: |
| case AArch64::SQDMLSLi16: |
| case AArch64::SQDMLSLi32: |
| case AArch64::SQDMLSLv2i32_v2i64: |
| case AArch64::SQDMLSLv4i16_v4i32: |
| case AArch64::SQDMLSLv4i32_v2i64: |
| case AArch64::SQDMLSLv8i16_v4i32: |
| case AArch64::SQRDMLAHv1i16: |
| case AArch64::SQRDMLAHv1i32: |
| case AArch64::SQRDMLAHv2i32: |
| case AArch64::SQRDMLAHv4i16: |
| case AArch64::SQRDMLAHv4i32: |
| case AArch64::SQRDMLAHv8i16: |
| case AArch64::SQRDMLSHv1i16: |
| case AArch64::SQRDMLSHv1i32: |
| case AArch64::SQRDMLSHv2i32: |
| case AArch64::SQRDMLSHv4i16: |
| case AArch64::SQRDMLSHv4i32: |
| case AArch64::SQRDMLSHv8i16: |
| case AArch64::SUBHNv2i64_v4i32: |
| case AArch64::SUBHNv4i32_v8i16: |
| case AArch64::SUBHNv8i16_v16i8: |
| case AArch64::UABALv16i8_v8i16: |
| case AArch64::UABALv2i32_v2i64: |
| case AArch64::UABALv4i16_v4i32: |
| case AArch64::UABALv4i32_v2i64: |
| case AArch64::UABALv8i16_v4i32: |
| case AArch64::UABALv8i8_v8i16: |
| case AArch64::UABAv16i8: |
| case AArch64::UABAv2i32: |
| case AArch64::UABAv4i16: |
| case AArch64::UABAv4i32: |
| case AArch64::UABAv8i16: |
| case AArch64::UABAv8i8: |
| case AArch64::UDOTv16i8: |
| case AArch64::UDOTv8i8: |
| case AArch64::UMLALv16i8_v8i16: |
| case AArch64::UMLALv2i32_v2i64: |
| case AArch64::UMLALv4i16_v4i32: |
| case AArch64::UMLALv4i32_v2i64: |
| case AArch64::UMLALv8i16_v4i32: |
| case AArch64::UMLALv8i8_v8i16: |
| case AArch64::UMLSLv16i8_v8i16: |
| case AArch64::UMLSLv2i32_v2i64: |
| case AArch64::UMLSLv4i16_v4i32: |
| case AArch64::UMLSLv4i32_v2i64: |
| case AArch64::UMLSLv8i16_v4i32: |
| case AArch64::UMLSLv8i8_v8i16: { |
| // op: Rd |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: Rm |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 16; |
| Value |= op; |
| break; |
| } |
| case AArch64::FMLAv1i32_indexed: |
| case AArch64::FMLAv2i32_indexed: |
| case AArch64::FMLAv4i32_indexed: |
| case AArch64::FMLSv1i32_indexed: |
| case AArch64::FMLSv2i32_indexed: |
| case AArch64::FMLSv4i32_indexed: |
| case AArch64::MLAv2i32_indexed: |
| case AArch64::MLAv4i32_indexed: |
| case AArch64::MLSv2i32_indexed: |
| case AArch64::MLSv4i32_indexed: |
| case AArch64::SDOTlanev16i8: |
| case AArch64::SDOTlanev8i8: |
| case AArch64::SMLALv2i32_indexed: |
| case AArch64::SMLALv4i32_indexed: |
| case AArch64::SMLSLv2i32_indexed: |
| case AArch64::SMLSLv4i32_indexed: |
| case AArch64::SQDMLALv1i64_indexed: |
| case AArch64::SQDMLALv2i32_indexed: |
| case AArch64::SQDMLALv4i32_indexed: |
| case AArch64::SQDMLSLv1i64_indexed: |
| case AArch64::SQDMLSLv2i32_indexed: |
| case AArch64::SQDMLSLv4i32_indexed: |
| case AArch64::SQRDMLAHi32_indexed: |
| case AArch64::SQRDMLAHv2i32_indexed: |
| case AArch64::SQRDMLAHv4i32_indexed: |
| case AArch64::SQRDMLSHi32_indexed: |
| case AArch64::SQRDMLSHv2i32_indexed: |
| case AArch64::SQRDMLSHv4i32_indexed: |
| case AArch64::UDOTlanev16i8: |
| case AArch64::UDOTlanev8i8: |
| case AArch64::UMLALv2i32_indexed: |
| case AArch64::UMLALv4i32_indexed: |
| case AArch64::UMLSLv2i32_indexed: |
| case AArch64::UMLSLv4i32_indexed: { |
| // op: Rd |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: Rm |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 16; |
| Value |= op; |
| // op: idx |
| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
| Value |= (op & UINT64_C(1)) << 21; |
| Value |= (op & UINT64_C(2)) << 10; |
| break; |
| } |
| case AArch64::FMLAv1i64_indexed: |
| case AArch64::FMLAv2i64_indexed: |
| case AArch64::FMLSv1i64_indexed: |
| case AArch64::FMLSv2i64_indexed: { |
| // op: Rd |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: Rm |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 16; |
| Value |= op; |
| // op: idx |
| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
| op &= UINT64_C(1); |
| op <<= 11; |
| Value |= op; |
| break; |
| } |
| case AArch64::FCMLAv2f32: |
| case AArch64::FCMLAv2f64: |
| case AArch64::FCMLAv4f16: |
| case AArch64::FCMLAv4f32: |
| case AArch64::FCMLAv8f16: { |
| // op: Rd |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: Rm |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 16; |
| Value |= op; |
| // op: rot |
| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
| op &= UINT64_C(3); |
| op <<= 11; |
| Value |= op; |
| break; |
| } |
| case AArch64::FCMLAv8f16_indexed: { |
| // op: Rd |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: Rm |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 16; |
| Value |= op; |
| // op: rot |
| op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); |
| op &= UINT64_C(3); |
| op <<= 13; |
| Value |= op; |
| // op: idx |
| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
| Value |= (op & UINT64_C(1)) << 21; |
| Value |= (op & UINT64_C(2)) << 10; |
| break; |
| } |
| case AArch64::FCMLAv4f32_indexed: { |
| // op: Rd |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: Rm |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 16; |
| Value |= op; |
| // op: rot |
| op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); |
| op &= UINT64_C(3); |
| op <<= 13; |
| Value |= op; |
| // op: idx |
| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
| op &= UINT64_C(1); |
| op <<= 11; |
| Value |= op; |
| break; |
| } |
| case AArch64::FCMLAv4f16_indexed: { |
| // op: Rd |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: Rm |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 16; |
| Value |= op; |
| // op: rot |
| op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); |
| op &= UINT64_C(3); |
| op <<= 13; |
| Value |= op; |
| // op: idx |
| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
| op &= UINT64_C(1); |
| op <<= 21; |
| Value |= op; |
| break; |
| } |
| case AArch64::SLIv4i16_shift: |
| case AArch64::SLIv8i16_shift: { |
| // op: Rd |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: imm |
| op = getVecShiftL16OpValue(MI, 3, Fixups, STI); |
| op &= UINT64_C(15); |
| op <<= 16; |
| Value |= op; |
| break; |
| } |
| case AArch64::SLIv2i32_shift: |
| case AArch64::SLIv4i32_shift: { |
| // op: Rd |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: imm |
| op = getVecShiftL32OpValue(MI, 3, Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 16; |
| Value |= op; |
| break; |
| } |
| case AArch64::SLId: |
| case AArch64::SLIv2i64_shift: { |
| // op: Rd |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: imm |
| op = getVecShiftL64OpValue(MI, 3, Fixups, STI); |
| op &= UINT64_C(63); |
| op <<= 16; |
| Value |= op; |
| break; |
| } |
| case AArch64::SLIv16i8_shift: |
| case AArch64::SLIv8i8_shift: { |
| // op: Rd |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: imm |
| op = getVecShiftL8OpValue(MI, 3, Fixups, STI); |
| op &= UINT64_C(7); |
| op <<= 16; |
| Value |= op; |
| break; |
| } |
| case AArch64::SRIv4i16_shift: |
| case AArch64::SRIv8i16_shift: |
| case AArch64::SRSRAv4i16_shift: |
| case AArch64::SRSRAv8i16_shift: |
| case AArch64::SSRAv4i16_shift: |
| case AArch64::SSRAv8i16_shift: |
| case AArch64::URSRAv4i16_shift: |
| case AArch64::URSRAv8i16_shift: |
| case AArch64::USRAv4i16_shift: |
| case AArch64::USRAv8i16_shift: { |
| // op: Rd |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: imm |
| op = getVecShiftR16OpValue(MI, 3, Fixups, STI); |
| op &= UINT64_C(15); |
| op <<= 16; |
| Value |= op; |
| break; |
| } |
| case AArch64::RSHRNv16i8_shift: |
| case AArch64::SHRNv16i8_shift: |
| case AArch64::SQRSHRNv16i8_shift: |
| case AArch64::SQRSHRUNv16i8_shift: |
| case AArch64::SQSHRNv16i8_shift: |
| case AArch64::SQSHRUNv16i8_shift: |
| case AArch64::UQRSHRNv16i8_shift: |
| case AArch64::UQSHRNv16i8_shift: { |
| // op: Rd |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: imm |
| op = getVecShiftR16OpValue(MI, 3, Fixups, STI); |
| op &= UINT64_C(7); |
| op <<= 16; |
| Value |= op; |
| break; |
| } |
| case AArch64::RSHRNv8i16_shift: |
| case AArch64::SHRNv8i16_shift: |
| case AArch64::SQRSHRNv8i16_shift: |
| case AArch64::SQRSHRUNv8i16_shift: |
| case AArch64::SQSHRNv8i16_shift: |
| case AArch64::SQSHRUNv8i16_shift: |
| case AArch64::UQRSHRNv8i16_shift: |
| case AArch64::UQSHRNv8i16_shift: { |
| // op: Rd |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: imm |
| op = getVecShiftR32OpValue(MI, 3, Fixups, STI); |
| op &= UINT64_C(15); |
| op <<= 16; |
| Value |= op; |
| break; |
| } |
| case AArch64::SRIv2i32_shift: |
| case AArch64::SRIv4i32_shift: |
| case AArch64::SRSRAv2i32_shift: |
| case AArch64::SRSRAv4i32_shift: |
| case AArch64::SSRAv2i32_shift: |
| case AArch64::SSRAv4i32_shift: |
| case AArch64::URSRAv2i32_shift: |
| case AArch64::URSRAv4i32_shift: |
| case AArch64::USRAv2i32_shift: |
| case AArch64::USRAv4i32_shift: { |
| // op: Rd |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: imm |
| op = getVecShiftR32OpValue(MI, 3, Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 16; |
| Value |= op; |
| break; |
| } |
| case AArch64::RSHRNv4i32_shift: |
| case AArch64::SHRNv4i32_shift: |
| case AArch64::SQRSHRNv4i32_shift: |
| case AArch64::SQRSHRUNv4i32_shift: |
| case AArch64::SQSHRNv4i32_shift: |
| case AArch64::SQSHRUNv4i32_shift: |
| case AArch64::UQRSHRNv4i32_shift: |
| case AArch64::UQSHRNv4i32_shift: { |
| // op: Rd |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: imm |
| op = getVecShiftR64OpValue(MI, 3, Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 16; |
| Value |= op; |
| break; |
| } |
| case AArch64::SRId: |
| case AArch64::SRIv2i64_shift: |
| case AArch64::SRSRAd: |
| case AArch64::SRSRAv2i64_shift: |
| case AArch64::SSRAd: |
| case AArch64::SSRAv2i64_shift: |
| case AArch64::URSRAd: |
| case AArch64::URSRAv2i64_shift: |
| case AArch64::USRAd: |
| case AArch64::USRAv2i64_shift: { |
| // op: Rd |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: imm |
| op = getVecShiftR64OpValue(MI, 3, Fixups, STI); |
| op &= UINT64_C(63); |
| op <<= 16; |
| Value |= op; |
| break; |
| } |
| case AArch64::SRIv16i8_shift: |
| case AArch64::SRIv8i8_shift: |
| case AArch64::SRSRAv16i8_shift: |
| case AArch64::SRSRAv8i8_shift: |
| case AArch64::SSRAv16i8_shift: |
| case AArch64::SSRAv8i8_shift: |
| case AArch64::URSRAv16i8_shift: |
| case AArch64::URSRAv8i8_shift: |
| case AArch64::USRAv16i8_shift: |
| case AArch64::USRAv8i8_shift: { |
| // op: Rd |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: imm |
| op = getVecShiftR8OpValue(MI, 3, Fixups, STI); |
| op &= UINT64_C(7); |
| op <<= 16; |
| Value |= op; |
| break; |
| } |
| case AArch64::INSvi64gpr: { |
| // op: Rd |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: idx |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(1); |
| op <<= 20; |
| Value |= op; |
| break; |
| } |
| case AArch64::INSvi64lane: { |
| // op: Rd |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: idx |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(1); |
| op <<= 20; |
| Value |= op; |
| // op: idx2 |
| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
| op &= UINT64_C(1); |
| op <<= 14; |
| Value |= op; |
| break; |
| } |
| case AArch64::INSvi8gpr: { |
| // op: Rd |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: idx |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(15); |
| op <<= 17; |
| Value |= op; |
| break; |
| } |
| case AArch64::INSvi8lane: { |
| // op: Rd |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: idx |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(15); |
| op <<= 17; |
| Value |= op; |
| // op: idx2 |
| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
| op &= UINT64_C(15); |
| op <<= 11; |
| Value |= op; |
| break; |
| } |
| case AArch64::INSvi32gpr: { |
| // op: Rd |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: idx |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(3); |
| op <<= 19; |
| Value |= op; |
| break; |
| } |
| case AArch64::INSvi32lane: { |
| // op: Rd |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: idx |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(3); |
| op <<= 19; |
| Value |= op; |
| // op: idx2 |
| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
| op &= UINT64_C(3); |
| op <<= 13; |
| Value |= op; |
| break; |
| } |
| case AArch64::INSvi16gpr: { |
| // op: Rd |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: idx |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(7); |
| op <<= 18; |
| Value |= op; |
| break; |
| } |
| case AArch64::INSvi16lane: { |
| // op: Rd |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: idx |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(7); |
| op <<= 18; |
| Value |= op; |
| // op: idx2 |
| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
| op &= UINT64_C(7); |
| op <<= 12; |
| Value |= op; |
| break; |
| } |
| case AArch64::BICv4i16: |
| case AArch64::BICv8i16: |
| case AArch64::ORRv4i16: |
| case AArch64::ORRv8i16: { |
| // op: Rd |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: imm8 |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| Value |= (op & UINT64_C(224)) << 11; |
| Value |= (op & UINT64_C(31)) << 5; |
| // op: shift |
| op = getVecShifterOpValue(MI, 3, Fixups, STI); |
| op &= UINT64_C(1); |
| op <<= 13; |
| Value |= op; |
| break; |
| } |
| case AArch64::BICv2i32: |
| case AArch64::BICv4i32: |
| case AArch64::ORRv2i32: |
| case AArch64::ORRv4i32: { |
| // op: Rd |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: imm8 |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| Value |= (op & UINT64_C(224)) << 11; |
| Value |= (op & UINT64_C(31)) << 5; |
| // op: shift |
| op = getVecShifterOpValue(MI, 3, Fixups, STI); |
| op &= UINT64_C(3); |
| op <<= 13; |
| Value |= op; |
| break; |
| } |
| case AArch64::DECP_XP_B: |
| case AArch64::DECP_XP_D: |
| case AArch64::DECP_XP_H: |
| case AArch64::DECP_XP_S: |
| case AArch64::INCP_XP_B: |
| case AArch64::INCP_XP_D: |
| case AArch64::INCP_XP_H: |
| case AArch64::INCP_XP_S: |
| case AArch64::SQDECP_XPWd_B: |
| case AArch64::SQDECP_XPWd_D: |
| case AArch64::SQDECP_XPWd_H: |
| case AArch64::SQDECP_XPWd_S: |
| case AArch64::SQDECP_XP_B: |
| case AArch64::SQDECP_XP_D: |
| case AArch64::SQDECP_XP_H: |
| case AArch64::SQDECP_XP_S: |
| case AArch64::SQINCP_XPWd_B: |
| case AArch64::SQINCP_XPWd_D: |
| case AArch64::SQINCP_XPWd_H: |
| case AArch64::SQINCP_XPWd_S: |
| case AArch64::SQINCP_XP_B: |
| case AArch64::SQINCP_XP_D: |
| case AArch64::SQINCP_XP_H: |
| case AArch64::SQINCP_XP_S: |
| case AArch64::UQDECP_WP_B: |
| case AArch64::UQDECP_WP_D: |
| case AArch64::UQDECP_WP_H: |
| case AArch64::UQDECP_WP_S: |
| case AArch64::UQDECP_XP_B: |
| case AArch64::UQDECP_XP_D: |
| case AArch64::UQDECP_XP_H: |
| case AArch64::UQDECP_XP_S: |
| case AArch64::UQINCP_WP_B: |
| case AArch64::UQINCP_WP_D: |
| case AArch64::UQINCP_WP_H: |
| case AArch64::UQINCP_WP_S: |
| case AArch64::UQINCP_XP_B: |
| case AArch64::UQINCP_XP_D: |
| case AArch64::UQINCP_XP_H: |
| case AArch64::UQINCP_XP_S: { |
| // op: Rdn |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Pg |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(15); |
| op <<= 5; |
| Value |= op; |
| break; |
| } |
| case AArch64::DECB_XPiI: |
| case AArch64::DECD_XPiI: |
| case AArch64::DECH_XPiI: |
| case AArch64::DECW_XPiI: |
| case AArch64::INCB_XPiI: |
| case AArch64::INCD_XPiI: |
| case AArch64::INCH_XPiI: |
| case AArch64::INCW_XPiI: |
| case AArch64::SQDECB_XPiI: |
| case AArch64::SQDECB_XPiWdI: |
| case AArch64::SQDECD_XPiI: |
| case AArch64::SQDECD_XPiWdI: |
| case AArch64::SQDECH_XPiI: |
| case AArch64::SQDECH_XPiWdI: |
| case AArch64::SQDECW_XPiI: |
| case AArch64::SQDECW_XPiWdI: |
| case AArch64::SQINCB_XPiI: |
| case AArch64::SQINCB_XPiWdI: |
| case AArch64::SQINCD_XPiI: |
| case AArch64::SQINCD_XPiWdI: |
| case AArch64::SQINCH_XPiI: |
| case AArch64::SQINCH_XPiWdI: |
| case AArch64::SQINCW_XPiI: |
| case AArch64::SQINCW_XPiWdI: |
| case AArch64::UQDECB_WPiI: |
| case AArch64::UQDECB_XPiI: |
| case AArch64::UQDECD_WPiI: |
| case AArch64::UQDECD_XPiI: |
| case AArch64::UQDECH_WPiI: |
| case AArch64::UQDECH_XPiI: |
| case AArch64::UQDECW_WPiI: |
| case AArch64::UQDECW_XPiI: |
| case AArch64::UQINCB_WPiI: |
| case AArch64::UQINCB_XPiI: |
| case AArch64::UQINCD_WPiI: |
| case AArch64::UQINCD_XPiI: |
| case AArch64::UQINCH_WPiI: |
| case AArch64::UQINCH_XPiI: |
| case AArch64::UQINCW_WPiI: |
| case AArch64::UQINCW_XPiI: { |
| // op: Rdn |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: pattern |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: imm4 |
| op = getSVEIncDecImm(MI, 3, Fixups, STI); |
| op &= UINT64_C(15); |
| op <<= 16; |
| Value |= op; |
| break; |
| } |
| case AArch64::CTERMEQ_WW: |
| case AArch64::CTERMEQ_XX: |
| case AArch64::CTERMNE_WW: |
| case AArch64::CTERMNE_XX: |
| case AArch64::FCMPDrr: |
| case AArch64::FCMPEDrr: |
| case AArch64::FCMPEHrr: |
| case AArch64::FCMPESrr: |
| case AArch64::FCMPHrr: |
| case AArch64::FCMPSrr: { |
| // op: Rm |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 16; |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| break; |
| } |
| case AArch64::INDEX_IR_B: |
| case AArch64::INDEX_IR_D: |
| case AArch64::INDEX_IR_H: |
| case AArch64::INDEX_IR_S: { |
| // op: Rm |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 16; |
| Value |= op; |
| // op: Zd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: imm5 |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| break; |
| } |
| case AArch64::INSR_ZR_B: |
| case AArch64::INSR_ZR_D: |
| case AArch64::INSR_ZR_H: |
| case AArch64::INSR_ZR_S: { |
| // op: Rm |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: Zdn |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| break; |
| } |
| case AArch64::PRFB_PRR: |
| case AArch64::PRFD_PRR: |
| case AArch64::PRFH_PRR: |
| case AArch64::PRFS_PRR: { |
| // op: Rm |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 16; |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: Pg |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(7); |
| op <<= 10; |
| Value |= op; |
| // op: prfop |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(15); |
| Value |= op; |
| break; |
| } |
| case AArch64::BLR: |
| case AArch64::BLRAAZ: |
| case AArch64::BLRABZ: |
| case AArch64::BR: |
| case AArch64::BRAAZ: |
| case AArch64::BRABZ: |
| case AArch64::RET: |
| case AArch64::SETF16: |
| case AArch64::SETF8: { |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| break; |
| } |
| case AArch64::BLRAA: |
| case AArch64::BLRAB: |
| case AArch64::BRAA: |
| case AArch64::BRAB: { |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: Rm |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| break; |
| } |
| case AArch64::CCMNWr: |
| case AArch64::CCMNXr: |
| case AArch64::CCMPWr: |
| case AArch64::CCMPXr: |
| case AArch64::FCCMPDrr: |
| case AArch64::FCCMPEDrr: |
| case AArch64::FCCMPEHrr: |
| case AArch64::FCCMPESrr: |
| case AArch64::FCCMPHrr: |
| case AArch64::FCCMPSrr: { |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: Rm |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 16; |
| Value |= op; |
| // op: nzcv |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(15); |
| Value |= op; |
| // op: cond |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(15); |
| op <<= 12; |
| Value |= op; |
| break; |
| } |
| case AArch64::CCMNWi: |
| case AArch64::CCMNXi: |
| case AArch64::CCMPWi: |
| case AArch64::CCMPXi: { |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: imm |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 16; |
| Value |= op; |
| // op: nzcv |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(15); |
| Value |= op; |
| // op: cond |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(15); |
| op <<= 12; |
| Value |= op; |
| break; |
| } |
| case AArch64::RMIF: { |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: imm |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(63); |
| op <<= 15; |
| Value |= op; |
| // op: mask |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(15); |
| Value |= op; |
| break; |
| } |
| case AArch64::FCMPDri: |
| case AArch64::FCMPEDri: |
| case AArch64::FCMPEHri: |
| case AArch64::FCMPESri: |
| case AArch64::FCMPHri: |
| case AArch64::FCMPSri: { |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| Value = fixOneOperandFPComparison(MI, Value, STI); |
| break; |
| } |
| case AArch64::LDAPRB: |
| case AArch64::LDAPRH: |
| case AArch64::LDAPRW: |
| case AArch64::LDAPRX: |
| case AArch64::LDGM: |
| case AArch64::STGM: |
| case AArch64::STZGM: { |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: Rt |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| break; |
| } |
| case AArch64::ST2GOffset: |
| case AArch64::STGOffset: |
| case AArch64::STZ2GOffset: |
| case AArch64::STZGOffset: { |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: Rt |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: offset |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(511); |
| op <<= 12; |
| Value |= op; |
| break; |
| } |
| case AArch64::DUP_ZR_B: |
| case AArch64::DUP_ZR_D: |
| case AArch64::DUP_ZR_H: |
| case AArch64::DUP_ZR_S: { |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: Zd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| break; |
| } |
| case AArch64::INDEX_RI_B: |
| case AArch64::INDEX_RI_D: |
| case AArch64::INDEX_RI_H: |
| case AArch64::INDEX_RI_S: { |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: Zd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: imm5 |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 16; |
| Value |= op; |
| break; |
| } |
| case AArch64::LDR_ZXI: |
| case AArch64::STR_ZXI: { |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: Zt |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: imm9 |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| Value |= (op & UINT64_C(504)) << 13; |
| Value |= (op & UINT64_C(7)) << 10; |
| break; |
| } |
| case AArch64::PRFB_PRI: |
| case AArch64::PRFD_PRI: |
| case AArch64::PRFH_PRI: |
| case AArch64::PRFW_PRI: { |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: Pg |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(7); |
| op <<= 10; |
| Value |= op; |
| // op: imm6 |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(63); |
| op <<= 16; |
| Value |= op; |
| // op: prfop |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(15); |
| Value |= op; |
| break; |
| } |
| case AArch64::LDG: |
| case AArch64::ST2GPostIndex: |
| case AArch64::ST2GPreIndex: |
| case AArch64::STGPostIndex: |
| case AArch64::STGPreIndex: |
| case AArch64::STZ2GPostIndex: |
| case AArch64::STZ2GPreIndex: |
| case AArch64::STZGPostIndex: |
| case AArch64::STZGPreIndex: { |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: Rt |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: offset |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(511); |
| op <<= 12; |
| Value |= op; |
| break; |
| } |
| case AArch64::LDADDAB: |
| case AArch64::LDADDAH: |
| case AArch64::LDADDALB: |
| case AArch64::LDADDALH: |
| case AArch64::LDADDALW: |
| case AArch64::LDADDALX: |
| case AArch64::LDADDAW: |
| case AArch64::LDADDAX: |
| case AArch64::LDADDB: |
| case AArch64::LDADDH: |
| case AArch64::LDADDLB: |
| case AArch64::LDADDLH: |
| case AArch64::LDADDLW: |
| case AArch64::LDADDLX: |
| case AArch64::LDADDW: |
| case AArch64::LDADDX: |
| case AArch64::LDCLRAB: |
| case AArch64::LDCLRAH: |
| case AArch64::LDCLRALB: |
| case AArch64::LDCLRALH: |
| case AArch64::LDCLRALW: |
| case AArch64::LDCLRALX: |
| case AArch64::LDCLRAW: |
| case AArch64::LDCLRAX: |
| case AArch64::LDCLRB: |
| case AArch64::LDCLRH: |
| case AArch64::LDCLRLB: |
| case AArch64::LDCLRLH: |
| case AArch64::LDCLRLW: |
| case AArch64::LDCLRLX: |
| case AArch64::LDCLRW: |
| case AArch64::LDCLRX: |
| case AArch64::LDEORAB: |
| case AArch64::LDEORAH: |
| case AArch64::LDEORALB: |
| case AArch64::LDEORALH: |
| case AArch64::LDEORALW: |
| case AArch64::LDEORALX: |
| case AArch64::LDEORAW: |
| case AArch64::LDEORAX: |
| case AArch64::LDEORB: |
| case AArch64::LDEORH: |
| case AArch64::LDEORLB: |
| case AArch64::LDEORLH: |
| case AArch64::LDEORLW: |
| case AArch64::LDEORLX: |
| case AArch64::LDEORW: |
| case AArch64::LDEORX: |
| case AArch64::LDSETAB: |
| case AArch64::LDSETAH: |
| case AArch64::LDSETALB: |
| case AArch64::LDSETALH: |
| case AArch64::LDSETALW: |
| case AArch64::LDSETALX: |
| case AArch64::LDSETAW: |
| case AArch64::LDSETAX: |
| case AArch64::LDSETB: |
| case AArch64::LDSETH: |
| case AArch64::LDSETLB: |
| case AArch64::LDSETLH: |
| case AArch64::LDSETLW: |
| case AArch64::LDSETLX: |
| case AArch64::LDSETW: |
| case AArch64::LDSETX: |
| case AArch64::LDSMAXAB: |
| case AArch64::LDSMAXAH: |
| case AArch64::LDSMAXALB: |
| case AArch64::LDSMAXALH: |
| case AArch64::LDSMAXALW: |
| case AArch64::LDSMAXALX: |
| case AArch64::LDSMAXAW: |
| case AArch64::LDSMAXAX: |
| case AArch64::LDSMAXB: |
| case AArch64::LDSMAXH: |
| case AArch64::LDSMAXLB: |
| case AArch64::LDSMAXLH: |
| case AArch64::LDSMAXLW: |
| case AArch64::LDSMAXLX: |
| case AArch64::LDSMAXW: |
| case AArch64::LDSMAXX: |
| case AArch64::LDSMINAB: |
| case AArch64::LDSMINAH: |
| case AArch64::LDSMINALB: |
| case AArch64::LDSMINALH: |
| case AArch64::LDSMINALW: |
| case AArch64::LDSMINALX: |
| case AArch64::LDSMINAW: |
| case AArch64::LDSMINAX: |
| case AArch64::LDSMINB: |
| case AArch64::LDSMINH: |
| case AArch64::LDSMINLB: |
| case AArch64::LDSMINLH: |
| case AArch64::LDSMINLW: |
| case AArch64::LDSMINLX: |
| case AArch64::LDSMINW: |
| case AArch64::LDSMINX: |
| case AArch64::LDUMAXAB: |
| case AArch64::LDUMAXAH: |
| case AArch64::LDUMAXALB: |
| case AArch64::LDUMAXALH: |
| case AArch64::LDUMAXALW: |
| case AArch64::LDUMAXALX: |
| case AArch64::LDUMAXAW: |
| case AArch64::LDUMAXAX: |
| case AArch64::LDUMAXB: |
| case AArch64::LDUMAXH: |
| case AArch64::LDUMAXLB: |
| case AArch64::LDUMAXLH: |
| case AArch64::LDUMAXLW: |
| case AArch64::LDUMAXLX: |
| case AArch64::LDUMAXW: |
| case AArch64::LDUMAXX: |
| case AArch64::LDUMINAB: |
| case AArch64::LDUMINAH: |
| case AArch64::LDUMINALB: |
| case AArch64::LDUMINALH: |
| case AArch64::LDUMINALW: |
| case AArch64::LDUMINALX: |
| case AArch64::LDUMINAW: |
| case AArch64::LDUMINAX: |
| case AArch64::LDUMINB: |
| case AArch64::LDUMINH: |
| case AArch64::LDUMINLB: |
| case AArch64::LDUMINLH: |
| case AArch64::LDUMINLW: |
| case AArch64::LDUMINLX: |
| case AArch64::LDUMINW: |
| case AArch64::LDUMINX: |
| case AArch64::SWPAB: |
| case AArch64::SWPAH: |
| case AArch64::SWPALB: |
| case AArch64::SWPALH: |
| case AArch64::SWPALW: |
| case AArch64::SWPALX: |
| case AArch64::SWPAW: |
| case AArch64::SWPAX: |
| case AArch64::SWPB: |
| case AArch64::SWPH: |
| case AArch64::SWPLB: |
| case AArch64::SWPLH: |
| case AArch64::SWPLW: |
| case AArch64::SWPLX: |
| case AArch64::SWPW: |
| case AArch64::SWPX: { |
| // op: Rs |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 16; |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: Rt |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| break; |
| } |
| case AArch64::CASAB: |
| case AArch64::CASAH: |
| case AArch64::CASALB: |
| case AArch64::CASALH: |
| case AArch64::CASALW: |
| case AArch64::CASALX: |
| case AArch64::CASAW: |
| case AArch64::CASAX: |
| case AArch64::CASB: |
| case AArch64::CASH: |
| case AArch64::CASLB: |
| case AArch64::CASLH: |
| case AArch64::CASLW: |
| case AArch64::CASLX: |
| case AArch64::CASPALW: |
| case AArch64::CASPALX: |
| case AArch64::CASPAW: |
| case AArch64::CASPAX: |
| case AArch64::CASPLW: |
| case AArch64::CASPLX: |
| case AArch64::CASPW: |
| case AArch64::CASPX: |
| case AArch64::CASW: |
| case AArch64::CASX: { |
| // op: Rs |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 16; |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: Rt |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| break; |
| } |
| case AArch64::TSTART: |
| case AArch64::TTEST: { |
| // op: Rt |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| break; |
| } |
| case AArch64::LDRBBroW: |
| case AArch64::LDRBBroX: |
| case AArch64::LDRBroW: |
| case AArch64::LDRBroX: |
| case AArch64::LDRDroW: |
| case AArch64::LDRDroX: |
| case AArch64::LDRHHroW: |
| case AArch64::LDRHHroX: |
| case AArch64::LDRHroW: |
| case AArch64::LDRHroX: |
| case AArch64::LDRQroW: |
| case AArch64::LDRQroX: |
| case AArch64::LDRSBWroW: |
| case AArch64::LDRSBWroX: |
| case AArch64::LDRSBXroW: |
| case AArch64::LDRSBXroX: |
| case AArch64::LDRSHWroW: |
| case AArch64::LDRSHWroX: |
| case AArch64::LDRSHXroW: |
| case AArch64::LDRSHXroX: |
| case AArch64::LDRSWroW: |
| case AArch64::LDRSWroX: |
| case AArch64::LDRSroW: |
| case AArch64::LDRSroX: |
| case AArch64::LDRWroW: |
| case AArch64::LDRWroX: |
| case AArch64::LDRXroW: |
| case AArch64::LDRXroX: |
| case AArch64::PRFMroW: |
| case AArch64::PRFMroX: |
| case AArch64::STRBBroW: |
| case AArch64::STRBBroX: |
| case AArch64::STRBroW: |
| case AArch64::STRBroX: |
| case AArch64::STRDroW: |
| case AArch64::STRDroX: |
| case AArch64::STRHHroW: |
| case AArch64::STRHHroX: |
| case AArch64::STRHroW: |
| case AArch64::STRHroX: |
| case AArch64::STRQroW: |
| case AArch64::STRQroX: |
| case AArch64::STRSroW: |
| case AArch64::STRSroX: |
| case AArch64::STRWroW: |
| case AArch64::STRWroX: |
| case AArch64::STRXroW: |
| case AArch64::STRXroX: { |
| // op: Rt |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: Rm |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 16; |
| Value |= op; |
| // op: extend |
| op = getMemExtendOpValue(MI, 3, Fixups, STI); |
| Value |= (op & UINT64_C(2)) << 14; |
| Value |= (op & UINT64_C(1)) << 12; |
| break; |
| } |
| case AArch64::LDRQui: |
| case AArch64::STRQui: { |
| // op: Rt |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: offset |
| op = getLdStUImm12OpValue<AArch64::fixup_aarch64_ldst_imm12_scale16>(MI, 2, Fixups, STI); |
| op &= UINT64_C(4095); |
| op <<= 10; |
| Value |= op; |
| break; |
| } |
| case AArch64::LDRBBui: |
| case AArch64::LDRBui: |
| case AArch64::LDRSBWui: |
| case AArch64::LDRSBXui: |
| case AArch64::STRBBui: |
| case AArch64::STRBui: { |
| // op: Rt |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: offset |
| op = getLdStUImm12OpValue<AArch64::fixup_aarch64_ldst_imm12_scale1>(MI, 2, Fixups, STI); |
| op &= UINT64_C(4095); |
| op <<= 10; |
| Value |= op; |
| break; |
| } |
| case AArch64::LDRHHui: |
| case AArch64::LDRHui: |
| case AArch64::LDRSHWui: |
| case AArch64::LDRSHXui: |
| case AArch64::STRHHui: |
| case AArch64::STRHui: { |
| // op: Rt |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: offset |
| op = getLdStUImm12OpValue<AArch64::fixup_aarch64_ldst_imm12_scale2>(MI, 2, Fixups, STI); |
| op &= UINT64_C(4095); |
| op <<= 10; |
| Value |= op; |
| break; |
| } |
| case AArch64::LDRSWui: |
| case AArch64::LDRSui: |
| case AArch64::LDRWui: |
| case AArch64::STRSui: |
| case AArch64::STRWui: { |
| // op: Rt |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: offset |
| op = getLdStUImm12OpValue<AArch64::fixup_aarch64_ldst_imm12_scale4>(MI, 2, Fixups, STI); |
| op &= UINT64_C(4095); |
| op <<= 10; |
| Value |= op; |
| break; |
| } |
| case AArch64::LDRDui: |
| case AArch64::LDRXui: |
| case AArch64::PRFMui: |
| case AArch64::STRDui: |
| case AArch64::STRXui: { |
| // op: Rt |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: offset |
| op = getLdStUImm12OpValue<AArch64::fixup_aarch64_ldst_imm12_scale8>(MI, 2, Fixups, STI); |
| op &= UINT64_C(4095); |
| op <<= 10; |
| Value |= op; |
| break; |
| } |
| case AArch64::LDAPURBi: |
| case AArch64::LDAPURHi: |
| case AArch64::LDAPURSBWi: |
| case AArch64::LDAPURSBXi: |
| case AArch64::LDAPURSHWi: |
| case AArch64::LDAPURSHXi: |
| case AArch64::LDAPURSWi: |
| case AArch64::LDAPURXi: |
| case AArch64::LDAPURi: |
| case AArch64::LDTRBi: |
| case AArch64::LDTRHi: |
| case AArch64::LDTRSBWi: |
| case AArch64::LDTRSBXi: |
| case AArch64::LDTRSHWi: |
| case AArch64::LDTRSHXi: |
| case AArch64::LDTRSWi: |
| case AArch64::LDTRWi: |
| case AArch64::LDTRXi: |
| case AArch64::LDURBBi: |
| case AArch64::LDURBi: |
| case AArch64::LDURDi: |
| case AArch64::LDURHHi: |
| case AArch64::LDURHi: |
| case AArch64::LDURQi: |
| case AArch64::LDURSBWi: |
| case AArch64::LDURSBXi: |
| case AArch64::LDURSHWi: |
| case AArch64::LDURSHXi: |
| case AArch64::LDURSWi: |
| case AArch64::LDURSi: |
| case AArch64::LDURWi: |
| case AArch64::LDURXi: |
| case AArch64::PRFUMi: |
| case AArch64::STLURBi: |
| case AArch64::STLURHi: |
| case AArch64::STLURWi: |
| case AArch64::STLURXi: |
| case AArch64::STTRBi: |
| case AArch64::STTRHi: |
| case AArch64::STTRWi: |
| case AArch64::STTRXi: |
| case AArch64::STURBBi: |
| case AArch64::STURBi: |
| case AArch64::STURDi: |
| case AArch64::STURHHi: |
| case AArch64::STURHi: |
| case AArch64::STURQi: |
| case AArch64::STURSi: |
| case AArch64::STURWi: |
| case AArch64::STURXi: { |
| // op: Rt |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: offset |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(511); |
| op <<= 12; |
| Value |= op; |
| break; |
| } |
| case AArch64::LDARB: |
| case AArch64::LDARH: |
| case AArch64::LDARW: |
| case AArch64::LDARX: |
| case AArch64::LDAXRB: |
| case AArch64::LDAXRH: |
| case AArch64::LDAXRW: |
| case AArch64::LDAXRX: |
| case AArch64::LDLARB: |
| case AArch64::LDLARH: |
| case AArch64::LDLARW: |
| case AArch64::LDLARX: |
| case AArch64::LDXRB: |
| case AArch64::LDXRH: |
| case AArch64::LDXRW: |
| case AArch64::LDXRX: |
| case AArch64::STLLRB: |
| case AArch64::STLLRH: |
| case AArch64::STLLRW: |
| case AArch64::STLLRX: |
| case AArch64::STLRB: |
| case AArch64::STLRH: |
| case AArch64::STLRW: |
| case AArch64::STLRX: { |
| // op: Rt |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| Value = fixLoadStoreExclusive<0,0>(MI, Value, STI); |
| break; |
| } |
| case AArch64::LDNPDi: |
| case AArch64::LDNPQi: |
| case AArch64::LDNPSi: |
| case AArch64::LDNPWi: |
| case AArch64::LDNPXi: |
| case AArch64::LDPDi: |
| case AArch64::LDPQi: |
| case AArch64::LDPSWi: |
| case AArch64::LDPSi: |
| case AArch64::LDPWi: |
| case AArch64::LDPXi: |
| case AArch64::STGPi: |
| case AArch64::STNPDi: |
| case AArch64::STNPQi: |
| case AArch64::STNPSi: |
| case AArch64::STNPWi: |
| case AArch64::STNPXi: |
| case AArch64::STPDi: |
| case AArch64::STPQi: |
| case AArch64::STPSi: |
| case AArch64::STPWi: |
| case AArch64::STPXi: { |
| // op: Rt |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rt2 |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 10; |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: offset |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(127); |
| op <<= 15; |
| Value |= op; |
| break; |
| } |
| case AArch64::LDAXPW: |
| case AArch64::LDAXPX: |
| case AArch64::LDXPW: |
| case AArch64::LDXPX: { |
| // op: Rt |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rt2 |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 10; |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| Value = fixLoadStoreExclusive<0,1>(MI, Value, STI); |
| break; |
| } |
| case AArch64::TBNZW: |
| case AArch64::TBNZX: |
| case AArch64::TBZW: |
| case AArch64::TBZX: { |
| // op: Rt |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: bit_off |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 19; |
| Value |= op; |
| // op: target |
| op = getTestBranchTargetOpValue(MI, 2, Fixups, STI); |
| op &= UINT64_C(16383); |
| op <<= 5; |
| Value |= op; |
| break; |
| } |
| case AArch64::LDRDl: |
| case AArch64::LDRQl: |
| case AArch64::LDRSWl: |
| case AArch64::LDRSl: |
| case AArch64::LDRWl: |
| case AArch64::LDRXl: |
| case AArch64::PRFMl: { |
| // op: Rt |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: label |
| op = getLoadLiteralOpValue(MI, 1, Fixups, STI); |
| op &= UINT64_C(524287); |
| op <<= 5; |
| Value |= op; |
| break; |
| } |
| case AArch64::SYSLxt: { |
| // op: Rt |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: op1 |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(7); |
| op <<= 16; |
| Value |= op; |
| // op: Cn |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(15); |
| op <<= 12; |
| Value |= op; |
| // op: Cm |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(15); |
| op <<= 8; |
| Value |= op; |
| // op: op2 |
| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
| op &= UINT64_C(7); |
| op <<= 5; |
| Value |= op; |
| break; |
| } |
| case AArch64::MRS: { |
| // op: Rt |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: systemreg |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(65535); |
| op <<= 5; |
| Value |= op; |
| break; |
| } |
| case AArch64::CBNZW: |
| case AArch64::CBNZX: |
| case AArch64::CBZW: |
| case AArch64::CBZX: { |
| // op: Rt |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: target |
| op = getCondBranchTargetOpValue(MI, 1, Fixups, STI); |
| op &= UINT64_C(524287); |
| op <<= 5; |
| Value |= op; |
| break; |
| } |
| case AArch64::LDRBBpost: |
| case AArch64::LDRBBpre: |
| case AArch64::LDRBpost: |
| case AArch64::LDRBpre: |
| case AArch64::LDRDpost: |
| case AArch64::LDRDpre: |
| case AArch64::LDRHHpost: |
| case AArch64::LDRHHpre: |
| case AArch64::LDRHpost: |
| case AArch64::LDRHpre: |
| case AArch64::LDRQpost: |
| case AArch64::LDRQpre: |
| case AArch64::LDRSBWpost: |
| case AArch64::LDRSBWpre: |
| case AArch64::LDRSBXpost: |
| case AArch64::LDRSBXpre: |
| case AArch64::LDRSHWpost: |
| case AArch64::LDRSHWpre: |
| case AArch64::LDRSHXpost: |
| case AArch64::LDRSHXpre: |
| case AArch64::LDRSWpost: |
| case AArch64::LDRSWpre: |
| case AArch64::LDRSpost: |
| case AArch64::LDRSpre: |
| case AArch64::LDRWpost: |
| case AArch64::LDRWpre: |
| case AArch64::LDRXpost: |
| case AArch64::LDRXpre: |
| case AArch64::STRBBpost: |
| case AArch64::STRBBpre: |
| case AArch64::STRBpost: |
| case AArch64::STRBpre: |
| case AArch64::STRDpost: |
| case AArch64::STRDpre: |
| case AArch64::STRHHpost: |
| case AArch64::STRHHpre: |
| case AArch64::STRHpost: |
| case AArch64::STRHpre: |
| case AArch64::STRQpost: |
| case AArch64::STRQpre: |
| case AArch64::STRSpost: |
| case AArch64::STRSpre: |
| case AArch64::STRWpost: |
| case AArch64::STRWpre: |
| case AArch64::STRXpost: |
| case AArch64::STRXpre: { |
| // op: Rt |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: offset |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(511); |
| op <<= 12; |
| Value |= op; |
| break; |
| } |
| case AArch64::LDPDpost: |
| case AArch64::LDPDpre: |
| case AArch64::LDPQpost: |
| case AArch64::LDPQpre: |
| case AArch64::LDPSWpost: |
| case AArch64::LDPSWpre: |
| case AArch64::LDPSpost: |
| case AArch64::LDPSpre: |
| case AArch64::LDPWpost: |
| case AArch64::LDPWpre: |
| case AArch64::LDPXpost: |
| case AArch64::LDPXpre: |
| case AArch64::STGPpost: |
| case AArch64::STGPpre: |
| case AArch64::STPDpost: |
| case AArch64::STPDpre: |
| case AArch64::STPQpost: |
| case AArch64::STPQpre: |
| case AArch64::STPSpost: |
| case AArch64::STPSpre: |
| case AArch64::STPWpost: |
| case AArch64::STPWpre: |
| case AArch64::STPXpost: |
| case AArch64::STPXpre: { |
| // op: Rt |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rt2 |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 10; |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: offset |
| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
| op &= UINT64_C(127); |
| op <<= 15; |
| Value |= op; |
| break; |
| } |
| case AArch64::MSR: { |
| // op: Rt |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: systemreg |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(65535); |
| op <<= 5; |
| Value |= op; |
| break; |
| } |
| case AArch64::SYSxt: { |
| // op: Rt |
| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: op1 |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(7); |
| op <<= 16; |
| Value |= op; |
| // op: Cn |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(15); |
| op <<= 12; |
| Value |= op; |
| // op: Cm |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(15); |
| op <<= 8; |
| Value |= op; |
| // op: op2 |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(7); |
| op <<= 5; |
| Value |= op; |
| break; |
| } |
| case AArch64::SHA512SU0: |
| case AArch64::SM4E: { |
| // op: Vd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Vn |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| break; |
| } |
| case AArch64::RAX1: |
| case AArch64::SM4ENCKEY: |
| case AArch64::TBLv16i8Four: |
| case AArch64::TBLv16i8One: |
| case AArch64::TBLv16i8Three: |
| case AArch64::TBLv16i8Two: |
| case AArch64::TBLv8i8Four: |
| case AArch64::TBLv8i8One: |
| case AArch64::TBLv8i8Three: |
| case AArch64::TBLv8i8Two: { |
| // op: Vd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Vn |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: Vm |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 16; |
| Value |= op; |
| break; |
| } |
| case AArch64::BCAX: |
| case AArch64::EOR3: |
| case AArch64::SM3SS1: { |
| // op: Vd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Vn |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: Vm |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 16; |
| Value |= op; |
| // op: Va |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 10; |
| Value |= op; |
| break; |
| } |
| case AArch64::XAR: { |
| // op: Vd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Vn |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: imm |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(63); |
| op <<= 10; |
| Value |= op; |
| // op: Vm |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 16; |
| Value |= op; |
| break; |
| } |
| case AArch64::SHA512H: |
| case AArch64::SHA512H2: |
| case AArch64::SHA512SU1: |
| case AArch64::SM3PARTW1: |
| case AArch64::SM3PARTW2: |
| case AArch64::TBXv16i8Four: |
| case AArch64::TBXv16i8One: |
| case AArch64::TBXv16i8Three: |
| case AArch64::TBXv16i8Two: |
| case AArch64::TBXv8i8Four: |
| case AArch64::TBXv8i8One: |
| case AArch64::TBXv8i8Three: |
| case AArch64::TBXv8i8Two: { |
| // op: Vd |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Vn |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: Vm |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 16; |
| Value |= op; |
| break; |
| } |
| case AArch64::SM3TT1A: |
| case AArch64::SM3TT1B: |
| case AArch64::SM3TT2A: |
| case AArch64::SM3TT2B: { |
| // op: Vd |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Vn |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: imm |
| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
| op &= UINT64_C(3); |
| op <<= 12; |
| Value |= op; |
| // op: Vm |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 16; |
| Value |= op; |
| break; |
| } |
| case AArch64::INSR_ZV_B: |
| case AArch64::INSR_ZV_D: |
| case AArch64::INSR_ZV_H: |
| case AArch64::INSR_ZV_S: { |
| // op: Vm |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: Zdn |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| break; |
| } |
| case AArch64::LD1Fourv16b: |
| case AArch64::LD1Fourv1d: |
| case AArch64::LD1Fourv2d: |
| case AArch64::LD1Fourv2s: |
| case AArch64::LD1Fourv4h: |
| case AArch64::LD1Fourv4s: |
| case AArch64::LD1Fourv8b: |
| case AArch64::LD1Fourv8h: |
| case AArch64::LD1Onev16b: |
| case AArch64::LD1Onev1d: |
| case AArch64::LD1Onev2d: |
| case AArch64::LD1Onev2s: |
| case AArch64::LD1Onev4h: |
| case AArch64::LD1Onev4s: |
| case AArch64::LD1Onev8b: |
| case AArch64::LD1Onev8h: |
| case AArch64::LD1Rv16b: |
| case AArch64::LD1Rv1d: |
| case AArch64::LD1Rv2d: |
| case AArch64::LD1Rv2s: |
| case AArch64::LD1Rv4h: |
| case AArch64::LD1Rv4s: |
| case AArch64::LD1Rv8b: |
| case AArch64::LD1Rv8h: |
| case AArch64::LD1Threev16b: |
| case AArch64::LD1Threev1d: |
| case AArch64::LD1Threev2d: |
| case AArch64::LD1Threev2s: |
| case AArch64::LD1Threev4h: |
| case AArch64::LD1Threev4s: |
| case AArch64::LD1Threev8b: |
| case AArch64::LD1Threev8h: |
| case AArch64::LD1Twov16b: |
| case AArch64::LD1Twov1d: |
| case AArch64::LD1Twov2d: |
| case AArch64::LD1Twov2s: |
| case AArch64::LD1Twov4h: |
| case AArch64::LD1Twov4s: |
| case AArch64::LD1Twov8b: |
| case AArch64::LD1Twov8h: |
| case AArch64::LD2Rv16b: |
| case AArch64::LD2Rv1d: |
| case AArch64::LD2Rv2d: |
| case AArch64::LD2Rv2s: |
| case AArch64::LD2Rv4h: |
| case AArch64::LD2Rv4s: |
| case AArch64::LD2Rv8b: |
| case AArch64::LD2Rv8h: |
| case AArch64::LD2Twov16b: |
| case AArch64::LD2Twov2d: |
| case AArch64::LD2Twov2s: |
| case AArch64::LD2Twov4h: |
| case AArch64::LD2Twov4s: |
| case AArch64::LD2Twov8b: |
| case AArch64::LD2Twov8h: |
| case AArch64::LD3Rv16b: |
| case AArch64::LD3Rv1d: |
| case AArch64::LD3Rv2d: |
| case AArch64::LD3Rv2s: |
| case AArch64::LD3Rv4h: |
| case AArch64::LD3Rv4s: |
| case AArch64::LD3Rv8b: |
| case AArch64::LD3Rv8h: |
| case AArch64::LD3Threev16b: |
| case AArch64::LD3Threev2d: |
| case AArch64::LD3Threev2s: |
| case AArch64::LD3Threev4h: |
| case AArch64::LD3Threev4s: |
| case AArch64::LD3Threev8b: |
| case AArch64::LD3Threev8h: |
| case AArch64::LD4Fourv16b: |
| case AArch64::LD4Fourv2d: |
| case AArch64::LD4Fourv2s: |
| case AArch64::LD4Fourv4h: |
| case AArch64::LD4Fourv4s: |
| case AArch64::LD4Fourv8b: |
| case AArch64::LD4Fourv8h: |
| case AArch64::LD4Rv16b: |
| case AArch64::LD4Rv1d: |
| case AArch64::LD4Rv2d: |
| case AArch64::LD4Rv2s: |
| case AArch64::LD4Rv4h: |
| case AArch64::LD4Rv4s: |
| case AArch64::LD4Rv8b: |
| case AArch64::LD4Rv8h: |
| case AArch64::ST1Fourv16b: |
| case AArch64::ST1Fourv1d: |
| case AArch64::ST1Fourv2d: |
| case AArch64::ST1Fourv2s: |
| case AArch64::ST1Fourv4h: |
| case AArch64::ST1Fourv4s: |
| case AArch64::ST1Fourv8b: |
| case AArch64::ST1Fourv8h: |
| case AArch64::ST1Onev16b: |
| case AArch64::ST1Onev1d: |
| case AArch64::ST1Onev2d: |
| case AArch64::ST1Onev2s: |
| case AArch64::ST1Onev4h: |
| case AArch64::ST1Onev4s: |
| case AArch64::ST1Onev8b: |
| case AArch64::ST1Onev8h: |
| case AArch64::ST1Threev16b: |
| case AArch64::ST1Threev1d: |
| case AArch64::ST1Threev2d: |
| case AArch64::ST1Threev2s: |
| case AArch64::ST1Threev4h: |
| case AArch64::ST1Threev4s: |
| case AArch64::ST1Threev8b: |
| case AArch64::ST1Threev8h: |
| case AArch64::ST1Twov16b: |
| case AArch64::ST1Twov1d: |
| case AArch64::ST1Twov2d: |
| case AArch64::ST1Twov2s: |
| case AArch64::ST1Twov4h: |
| case AArch64::ST1Twov4s: |
| case AArch64::ST1Twov8b: |
| case AArch64::ST1Twov8h: |
| case AArch64::ST2Twov16b: |
| case AArch64::ST2Twov2d: |
| case AArch64::ST2Twov2s: |
| case AArch64::ST2Twov4h: |
| case AArch64::ST2Twov4s: |
| case AArch64::ST2Twov8b: |
| case AArch64::ST2Twov8h: |
| case AArch64::ST3Threev16b: |
| case AArch64::ST3Threev2d: |
| case AArch64::ST3Threev2s: |
| case AArch64::ST3Threev4h: |
| case AArch64::ST3Threev4s: |
| case AArch64::ST3Threev8b: |
| case AArch64::ST3Threev8h: |
| case AArch64::ST4Fourv16b: |
| case AArch64::ST4Fourv2d: |
| case AArch64::ST4Fourv2s: |
| case AArch64::ST4Fourv4h: |
| case AArch64::ST4Fourv4s: |
| case AArch64::ST4Fourv8b: |
| case AArch64::ST4Fourv8h: { |
| // op: Vt |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| break; |
| } |
| case AArch64::ST1i32: |
| case AArch64::ST2i32: |
| case AArch64::ST3i32: |
| case AArch64::ST4i32: { |
| // op: Vt |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: idx |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| Value |= (op & UINT64_C(2)) << 29; |
| Value |= (op & UINT64_C(1)) << 12; |
| break; |
| } |
| case AArch64::ST1i16: |
| case AArch64::ST2i16: |
| case AArch64::ST3i16: |
| case AArch64::ST4i16: { |
| // op: Vt |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: idx |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| Value |= (op & UINT64_C(4)) << 28; |
| Value |= (op & UINT64_C(3)) << 11; |
| break; |
| } |
| case AArch64::ST1i8: |
| case AArch64::ST2i8: |
| case AArch64::ST3i8: |
| case AArch64::ST4i8: { |
| // op: Vt |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: idx |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| Value |= (op & UINT64_C(8)) << 27; |
| Value |= (op & UINT64_C(7)) << 10; |
| break; |
| } |
| case AArch64::ST1i64: |
| case AArch64::ST2i64: |
| case AArch64::ST3i64: |
| case AArch64::ST4i64: { |
| // op: Vt |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: idx |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(1); |
| op <<= 30; |
| Value |= op; |
| break; |
| } |
| case AArch64::LD1Fourv16b_POST: |
| case AArch64::LD1Fourv1d_POST: |
| case AArch64::LD1Fourv2d_POST: |
| case AArch64::LD1Fourv2s_POST: |
| case AArch64::LD1Fourv4h_POST: |
| case AArch64::LD1Fourv4s_POST: |
| case AArch64::LD1Fourv8b_POST: |
| case AArch64::LD1Fourv8h_POST: |
| case AArch64::LD1Onev16b_POST: |
| case AArch64::LD1Onev1d_POST: |
| case AArch64::LD1Onev2d_POST: |
| case AArch64::LD1Onev2s_POST: |
| case AArch64::LD1Onev4h_POST: |
| case AArch64::LD1Onev4s_POST: |
| case AArch64::LD1Onev8b_POST: |
| case AArch64::LD1Onev8h_POST: |
| case AArch64::LD1Rv16b_POST: |
| case AArch64::LD1Rv1d_POST: |
| case AArch64::LD1Rv2d_POST: |
| case AArch64::LD1Rv2s_POST: |
| case AArch64::LD1Rv4h_POST: |
| case AArch64::LD1Rv4s_POST: |
| case AArch64::LD1Rv8b_POST: |
| case AArch64::LD1Rv8h_POST: |
| case AArch64::LD1Threev16b_POST: |
| case AArch64::LD1Threev1d_POST: |
| case AArch64::LD1Threev2d_POST: |
| case AArch64::LD1Threev2s_POST: |
| case AArch64::LD1Threev4h_POST: |
| case AArch64::LD1Threev4s_POST: |
| case AArch64::LD1Threev8b_POST: |
| case AArch64::LD1Threev8h_POST: |
| case AArch64::LD1Twov16b_POST: |
| case AArch64::LD1Twov1d_POST: |
| case AArch64::LD1Twov2d_POST: |
| case AArch64::LD1Twov2s_POST: |
| case AArch64::LD1Twov4h_POST: |
| case AArch64::LD1Twov4s_POST: |
| case AArch64::LD1Twov8b_POST: |
| case AArch64::LD1Twov8h_POST: |
| case AArch64::LD2Rv16b_POST: |
| case AArch64::LD2Rv1d_POST: |
| case AArch64::LD2Rv2d_POST: |
| case AArch64::LD2Rv2s_POST: |
| case AArch64::LD2Rv4h_POST: |
| case AArch64::LD2Rv4s_POST: |
| case AArch64::LD2Rv8b_POST: |
| case AArch64::LD2Rv8h_POST: |
| case AArch64::LD2Twov16b_POST: |
| case AArch64::LD2Twov2d_POST: |
| case AArch64::LD2Twov2s_POST: |
| case AArch64::LD2Twov4h_POST: |
| case AArch64::LD2Twov4s_POST: |
| case AArch64::LD2Twov8b_POST: |
| case AArch64::LD2Twov8h_POST: |
| case AArch64::LD3Rv16b_POST: |
| case AArch64::LD3Rv1d_POST: |
| case AArch64::LD3Rv2d_POST: |
| case AArch64::LD3Rv2s_POST: |
| case AArch64::LD3Rv4h_POST: |
| case AArch64::LD3Rv4s_POST: |
| case AArch64::LD3Rv8b_POST: |
| case AArch64::LD3Rv8h_POST: |
| case AArch64::LD3Threev16b_POST: |
| case AArch64::LD3Threev2d_POST: |
| case AArch64::LD3Threev2s_POST: |
| case AArch64::LD3Threev4h_POST: |
| case AArch64::LD3Threev4s_POST: |
| case AArch64::LD3Threev8b_POST: |
| case AArch64::LD3Threev8h_POST: |
| case AArch64::LD4Fourv16b_POST: |
| case AArch64::LD4Fourv2d_POST: |
| case AArch64::LD4Fourv2s_POST: |
| case AArch64::LD4Fourv4h_POST: |
| case AArch64::LD4Fourv4s_POST: |
| case AArch64::LD4Fourv8b_POST: |
| case AArch64::LD4Fourv8h_POST: |
| case AArch64::LD4Rv16b_POST: |
| case AArch64::LD4Rv1d_POST: |
| case AArch64::LD4Rv2d_POST: |
| case AArch64::LD4Rv2s_POST: |
| case AArch64::LD4Rv4h_POST: |
| case AArch64::LD4Rv4s_POST: |
| case AArch64::LD4Rv8b_POST: |
| case AArch64::LD4Rv8h_POST: |
| case AArch64::ST1Fourv16b_POST: |
| case AArch64::ST1Fourv1d_POST: |
| case AArch64::ST1Fourv2d_POST: |
| case AArch64::ST1Fourv2s_POST: |
| case AArch64::ST1Fourv4h_POST: |
| case AArch64::ST1Fourv4s_POST: |
| case AArch64::ST1Fourv8b_POST: |
| case AArch64::ST1Fourv8h_POST: |
| case AArch64::ST1Onev16b_POST: |
| case AArch64::ST1Onev1d_POST: |
| case AArch64::ST1Onev2d_POST: |
| case AArch64::ST1Onev2s_POST: |
| case AArch64::ST1Onev4h_POST: |
| case AArch64::ST1Onev4s_POST: |
| case AArch64::ST1Onev8b_POST: |
| case AArch64::ST1Onev8h_POST: |
| case AArch64::ST1Threev16b_POST: |
| case AArch64::ST1Threev1d_POST: |
| case AArch64::ST1Threev2d_POST: |
| case AArch64::ST1Threev2s_POST: |
| case AArch64::ST1Threev4h_POST: |
| case AArch64::ST1Threev4s_POST: |
| case AArch64::ST1Threev8b_POST: |
| case AArch64::ST1Threev8h_POST: |
| case AArch64::ST1Twov16b_POST: |
| case AArch64::ST1Twov1d_POST: |
| case AArch64::ST1Twov2d_POST: |
| case AArch64::ST1Twov2s_POST: |
| case AArch64::ST1Twov4h_POST: |
| case AArch64::ST1Twov4s_POST: |
| case AArch64::ST1Twov8b_POST: |
| case AArch64::ST1Twov8h_POST: |
| case AArch64::ST2Twov16b_POST: |
| case AArch64::ST2Twov2d_POST: |
| case AArch64::ST2Twov2s_POST: |
| case AArch64::ST2Twov4h_POST: |
| case AArch64::ST2Twov4s_POST: |
| case AArch64::ST2Twov8b_POST: |
| case AArch64::ST2Twov8h_POST: |
| case AArch64::ST3Threev16b_POST: |
| case AArch64::ST3Threev2d_POST: |
| case AArch64::ST3Threev2s_POST: |
| case AArch64::ST3Threev4h_POST: |
| case AArch64::ST3Threev4s_POST: |
| case AArch64::ST3Threev8b_POST: |
| case AArch64::ST3Threev8h_POST: |
| case AArch64::ST4Fourv16b_POST: |
| case AArch64::ST4Fourv2d_POST: |
| case AArch64::ST4Fourv2s_POST: |
| case AArch64::ST4Fourv4h_POST: |
| case AArch64::ST4Fourv4s_POST: |
| case AArch64::ST4Fourv8b_POST: |
| case AArch64::ST4Fourv8h_POST: { |
| // op: Vt |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: Xm |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 16; |
| Value |= op; |
| break; |
| } |
| case AArch64::LD1i32: |
| case AArch64::LD2i32: |
| case AArch64::LD3i32: |
| case AArch64::LD4i32: { |
| // op: Vt |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: idx |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| Value |= (op & UINT64_C(2)) << 29; |
| Value |= (op & UINT64_C(1)) << 12; |
| break; |
| } |
| case AArch64::ST1i32_POST: |
| case AArch64::ST2i32_POST: |
| case AArch64::ST3i32_POST: |
| case AArch64::ST4i32_POST: { |
| // op: Vt |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: idx |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| Value |= (op & UINT64_C(2)) << 29; |
| Value |= (op & UINT64_C(1)) << 12; |
| // op: Xm |
| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 16; |
| Value |= op; |
| break; |
| } |
| case AArch64::LD1i16: |
| case AArch64::LD2i16: |
| case AArch64::LD3i16: |
| case AArch64::LD4i16: { |
| // op: Vt |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: idx |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| Value |= (op & UINT64_C(4)) << 28; |
| Value |= (op & UINT64_C(3)) << 11; |
| break; |
| } |
| case AArch64::ST1i16_POST: |
| case AArch64::ST2i16_POST: |
| case AArch64::ST3i16_POST: |
| case AArch64::ST4i16_POST: { |
| // op: Vt |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: idx |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| Value |= (op & UINT64_C(4)) << 28; |
| Value |= (op & UINT64_C(3)) << 11; |
| // op: Xm |
| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 16; |
| Value |= op; |
| break; |
| } |
| case AArch64::LD1i8: |
| case AArch64::LD2i8: |
| case AArch64::LD3i8: |
| case AArch64::LD4i8: { |
| // op: Vt |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: idx |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| Value |= (op & UINT64_C(8)) << 27; |
| Value |= (op & UINT64_C(7)) << 10; |
| break; |
| } |
| case AArch64::ST1i8_POST: |
| case AArch64::ST2i8_POST: |
| case AArch64::ST3i8_POST: |
| case AArch64::ST4i8_POST: { |
| // op: Vt |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: idx |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| Value |= (op & UINT64_C(8)) << 27; |
| Value |= (op & UINT64_C(7)) << 10; |
| // op: Xm |
| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 16; |
| Value |= op; |
| break; |
| } |
| case AArch64::LD1i64: |
| case AArch64::LD2i64: |
| case AArch64::LD3i64: |
| case AArch64::LD4i64: { |
| // op: Vt |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: idx |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(1); |
| op <<= 30; |
| Value |= op; |
| break; |
| } |
| case AArch64::ST1i64_POST: |
| case AArch64::ST2i64_POST: |
| case AArch64::ST3i64_POST: |
| case AArch64::ST4i64_POST: { |
| // op: Vt |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: idx |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(1); |
| op <<= 30; |
| Value |= op; |
| // op: Xm |
| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 16; |
| Value |= op; |
| break; |
| } |
| case AArch64::LD1i32_POST: |
| case AArch64::LD2i32_POST: |
| case AArch64::LD3i32_POST: |
| case AArch64::LD4i32_POST: { |
| // op: Vt |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: idx |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| Value |= (op & UINT64_C(2)) << 29; |
| Value |= (op & UINT64_C(1)) << 12; |
| // op: Xm |
| op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 16; |
| Value |= op; |
| break; |
| } |
| case AArch64::LD1i16_POST: |
| case AArch64::LD2i16_POST: |
| case AArch64::LD3i16_POST: |
| case AArch64::LD4i16_POST: { |
| // op: Vt |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: idx |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| Value |= (op & UINT64_C(4)) << 28; |
| Value |= (op & UINT64_C(3)) << 11; |
| // op: Xm |
| op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 16; |
| Value |= op; |
| break; |
| } |
| case AArch64::LD1i8_POST: |
| case AArch64::LD2i8_POST: |
| case AArch64::LD3i8_POST: |
| case AArch64::LD4i8_POST: { |
| // op: Vt |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: idx |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| Value |= (op & UINT64_C(8)) << 27; |
| Value |= (op & UINT64_C(7)) << 10; |
| // op: Xm |
| op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 16; |
| Value |= op; |
| break; |
| } |
| case AArch64::LD1i64_POST: |
| case AArch64::LD2i64_POST: |
| case AArch64::LD3i64_POST: |
| case AArch64::LD4i64_POST: { |
| // op: Vt |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: idx |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(1); |
| op <<= 30; |
| Value |= op; |
| // op: Xm |
| op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 16; |
| Value |= op; |
| break; |
| } |
| case AArch64::STLXRB: |
| case AArch64::STLXRH: |
| case AArch64::STLXRW: |
| case AArch64::STLXRX: |
| case AArch64::STXRB: |
| case AArch64::STXRH: |
| case AArch64::STXRW: |
| case AArch64::STXRX: { |
| // op: Ws |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 16; |
| Value |= op; |
| // op: Rt |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| Value = fixLoadStoreExclusive<1,0>(MI, Value, STI); |
| break; |
| } |
| case AArch64::STLXPW: |
| case AArch64::STLXPX: |
| case AArch64::STXPW: |
| case AArch64::STXPX: { |
| // op: Ws |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 16; |
| Value |= op; |
| // op: Rt |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rt2 |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 10; |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| break; |
| } |
| case AArch64::ADR: |
| case AArch64::ADRP: { |
| // op: Xd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: label |
| op = getAdrLabelOpValue(MI, 1, Fixups, STI); |
| Value |= (op & UINT64_C(3)) << 29; |
| Value |= (op & UINT64_C(2097148)) << 3; |
| break; |
| } |
| case AArch64::CPY_ZPzI_B: |
| case AArch64::CPY_ZPzI_D: |
| case AArch64::CPY_ZPzI_H: |
| case AArch64::CPY_ZPzI_S: { |
| // op: Zd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Pg |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(15); |
| op <<= 16; |
| Value |= op; |
| // op: imm |
| op = getImm8OptLsl(MI, 2, Fixups, STI); |
| op &= UINT64_C(511); |
| op <<= 5; |
| Value |= op; |
| break; |
| } |
| case AArch64::CPY_ZPmI_B: |
| case AArch64::CPY_ZPmI_D: |
| case AArch64::CPY_ZPmI_H: |
| case AArch64::CPY_ZPmI_S: { |
| // op: Zd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Pg |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(15); |
| op <<= 16; |
| Value |= op; |
| // op: imm |
| op = getImm8OptLsl(MI, 3, Fixups, STI); |
| op &= UINT64_C(511); |
| op <<= 5; |
| Value |= op; |
| break; |
| } |
| case AArch64::RBIT_ZPmZ_B: |
| case AArch64::RBIT_ZPmZ_D: |
| case AArch64::RBIT_ZPmZ_H: |
| case AArch64::RBIT_ZPmZ_S: |
| case AArch64::REVB_ZPmZ_D: |
| case AArch64::REVB_ZPmZ_H: |
| case AArch64::REVB_ZPmZ_S: |
| case AArch64::REVH_ZPmZ_D: |
| case AArch64::REVH_ZPmZ_S: |
| case AArch64::REVW_ZPmZ_D: { |
| // op: Zd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Pg |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(7); |
| op <<= 10; |
| Value |= op; |
| // op: Zn |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| break; |
| } |
| case AArch64::INDEX_RR_B: |
| case AArch64::INDEX_RR_D: |
| case AArch64::INDEX_RR_H: |
| case AArch64::INDEX_RR_S: { |
| // op: Zd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rm |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 16; |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| break; |
| } |
| case AArch64::ADD_ZZZ_B: |
| case AArch64::ADD_ZZZ_D: |
| case AArch64::ADD_ZZZ_H: |
| case AArch64::ADD_ZZZ_S: |
| case AArch64::AND_ZZZ: |
| case AArch64::ASR_WIDE_ZZZ_B: |
| case AArch64::ASR_WIDE_ZZZ_H: |
| case AArch64::ASR_WIDE_ZZZ_S: |
| case AArch64::BIC_ZZZ: |
| case AArch64::EOR_ZZZ: |
| case AArch64::FADD_ZZZ_D: |
| case AArch64::FADD_ZZZ_H: |
| case AArch64::FADD_ZZZ_S: |
| case AArch64::FMUL_ZZZ_D: |
| case AArch64::FMUL_ZZZ_H: |
| case AArch64::FMUL_ZZZ_S: |
| case AArch64::FRECPS_ZZZ_D: |
| case AArch64::FRECPS_ZZZ_H: |
| case AArch64::FRECPS_ZZZ_S: |
| case AArch64::FRSQRTS_ZZZ_D: |
| case AArch64::FRSQRTS_ZZZ_H: |
| case AArch64::FRSQRTS_ZZZ_S: |
| case AArch64::FSUB_ZZZ_D: |
| case AArch64::FSUB_ZZZ_H: |
| case AArch64::FSUB_ZZZ_S: |
| case AArch64::FTSMUL_ZZZ_D: |
| case AArch64::FTSMUL_ZZZ_H: |
| case AArch64::FTSMUL_ZZZ_S: |
| case AArch64::FTSSEL_ZZZ_D: |
| case AArch64::FTSSEL_ZZZ_H: |
| case AArch64::FTSSEL_ZZZ_S: |
| case AArch64::LSL_WIDE_ZZZ_B: |
| case AArch64::LSL_WIDE_ZZZ_H: |
| case AArch64::LSL_WIDE_ZZZ_S: |
| case AArch64::LSR_WIDE_ZZZ_B: |
| case AArch64::LSR_WIDE_ZZZ_H: |
| case AArch64::LSR_WIDE_ZZZ_S: |
| case AArch64::MUL_ZZZ_B: |
| case AArch64::MUL_ZZZ_D: |
| case AArch64::MUL_ZZZ_H: |
| case AArch64::MUL_ZZZ_S: |
| case AArch64::ORR_ZZZ: |
| case AArch64::PMUL_ZZZ_B: |
| case AArch64::SMULH_ZZZ_B: |
| case AArch64::SMULH_ZZZ_D: |
| case AArch64::SMULH_ZZZ_H: |
| case AArch64::SMULH_ZZZ_S: |
| case AArch64::SQADD_ZZZ_B: |
| case AArch64::SQADD_ZZZ_D: |
| case AArch64::SQADD_ZZZ_H: |
| case AArch64::SQADD_ZZZ_S: |
| case AArch64::SQDMULH_ZZZ_B: |
| case AArch64::SQDMULH_ZZZ_D: |
| case AArch64::SQDMULH_ZZZ_H: |
| case AArch64::SQDMULH_ZZZ_S: |
| case AArch64::SQRDMULH_ZZZ_B: |
| case AArch64::SQRDMULH_ZZZ_D: |
| case AArch64::SQRDMULH_ZZZ_H: |
| case AArch64::SQRDMULH_ZZZ_S: |
| case AArch64::SQSUB_ZZZ_B: |
| case AArch64::SQSUB_ZZZ_D: |
| case AArch64::SQSUB_ZZZ_H: |
| case AArch64::SQSUB_ZZZ_S: |
| case AArch64::SUB_ZZZ_B: |
| case AArch64::SUB_ZZZ_D: |
| case AArch64::SUB_ZZZ_H: |
| case AArch64::SUB_ZZZ_S: |
| case AArch64::TBL_ZZZZ_B: |
| case AArch64::TBL_ZZZZ_D: |
| case AArch64::TBL_ZZZZ_H: |
| case AArch64::TBL_ZZZZ_S: |
| case AArch64::TBL_ZZZ_B: |
| case AArch64::TBL_ZZZ_D: |
| case AArch64::TBL_ZZZ_H: |
| case AArch64::TBL_ZZZ_S: |
| case AArch64::TRN1_ZZZ_B: |
| case AArch64::TRN1_ZZZ_D: |
| case AArch64::TRN1_ZZZ_H: |
| case AArch64::TRN1_ZZZ_S: |
| case AArch64::TRN2_ZZZ_B: |
| case AArch64::TRN2_ZZZ_D: |
| case AArch64::TRN2_ZZZ_H: |
| case AArch64::TRN2_ZZZ_S: |
| case AArch64::UMULH_ZZZ_B: |
| case AArch64::UMULH_ZZZ_D: |
| case AArch64::UMULH_ZZZ_H: |
| case AArch64::UMULH_ZZZ_S: |
| case AArch64::UQADD_ZZZ_B: |
| case AArch64::UQADD_ZZZ_D: |
| case AArch64::UQADD_ZZZ_H: |
| case AArch64::UQADD_ZZZ_S: |
| case AArch64::UQSUB_ZZZ_B: |
| case AArch64::UQSUB_ZZZ_D: |
| case AArch64::UQSUB_ZZZ_H: |
| case AArch64::UQSUB_ZZZ_S: |
| case AArch64::UZP1_ZZZ_B: |
| case AArch64::UZP1_ZZZ_D: |
| case AArch64::UZP1_ZZZ_H: |
| case AArch64::UZP1_ZZZ_S: |
| case AArch64::UZP2_ZZZ_B: |
| case AArch64::UZP2_ZZZ_D: |
| case AArch64::UZP2_ZZZ_H: |
| case AArch64::UZP2_ZZZ_S: |
| case AArch64::ZIP1_ZZZ_B: |
| case AArch64::ZIP1_ZZZ_D: |
| case AArch64::ZIP1_ZZZ_H: |
| case AArch64::ZIP1_ZZZ_S: |
| case AArch64::ZIP2_ZZZ_B: |
| case AArch64::ZIP2_ZZZ_D: |
| case AArch64::ZIP2_ZZZ_H: |
| case AArch64::ZIP2_ZZZ_S: { |
| // op: Zd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Zm |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 16; |
| Value |= op; |
| // op: Zn |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| break; |
| } |
| case AArch64::TBX_ZZZ_B: |
| case AArch64::TBX_ZZZ_D: |
| case AArch64::TBX_ZZZ_H: |
| case AArch64::TBX_ZZZ_S: { |
| // op: Zd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Zm |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 16; |
| Value |= op; |
| // op: Zn |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| break; |
| } |
| case AArch64::FEXPA_ZZ_D: |
| case AArch64::FEXPA_ZZ_H: |
| case AArch64::FEXPA_ZZ_S: |
| case AArch64::FRECPE_ZZ_D: |
| case AArch64::FRECPE_ZZ_H: |
| case AArch64::FRECPE_ZZ_S: |
| case AArch64::FRSQRTE_ZZ_D: |
| case AArch64::FRSQRTE_ZZ_H: |
| case AArch64::FRSQRTE_ZZ_S: |
| case AArch64::MOVPRFX_ZZ: |
| case AArch64::REV_ZZ_B: |
| case AArch64::REV_ZZ_D: |
| case AArch64::REV_ZZ_H: |
| case AArch64::REV_ZZ_S: |
| case AArch64::SQXTNB_ZZ_B: |
| case AArch64::SQXTNB_ZZ_H: |
| case AArch64::SQXTNB_ZZ_S: |
| case AArch64::SQXTUNB_ZZ_B: |
| case AArch64::SQXTUNB_ZZ_H: |
| case AArch64::SQXTUNB_ZZ_S: |
| case AArch64::SUNPKHI_ZZ_D: |
| case AArch64::SUNPKHI_ZZ_H: |
| case AArch64::SUNPKHI_ZZ_S: |
| case AArch64::SUNPKLO_ZZ_D: |
| case AArch64::SUNPKLO_ZZ_H: |
| case AArch64::SUNPKLO_ZZ_S: |
| case AArch64::UQXTNB_ZZ_B: |
| case AArch64::UQXTNB_ZZ_H: |
| case AArch64::UQXTNB_ZZ_S: |
| case AArch64::UUNPKHI_ZZ_D: |
| case AArch64::UUNPKHI_ZZ_H: |
| case AArch64::UUNPKHI_ZZ_S: |
| case AArch64::UUNPKLO_ZZ_D: |
| case AArch64::UUNPKLO_ZZ_H: |
| case AArch64::UUNPKLO_ZZ_S: { |
| // op: Zd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Zn |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| break; |
| } |
| case AArch64::SMULLB_ZZZI_D: |
| case AArch64::SMULLT_ZZZI_D: |
| case AArch64::SQDMULLB_ZZZI_D: |
| case AArch64::SQDMULLT_ZZZI_D: |
| case AArch64::UMULLB_ZZZI_D: |
| case AArch64::UMULLT_ZZZI_D: { |
| // op: Zd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Zn |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: Zm |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(15); |
| op <<= 16; |
| Value |= op; |
| // op: iop |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| Value |= (op & UINT64_C(2)) << 19; |
| Value |= (op & UINT64_C(1)) << 11; |
| break; |
| } |
| case AArch64::FMUL_ZZZI_D: |
| case AArch64::MUL_ZZZI_D: |
| case AArch64::SQDMULH_ZZZI_D: |
| case AArch64::SQRDMULH_ZZZI_D: { |
| // op: Zd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Zn |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: Zm |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(15); |
| op <<= 16; |
| Value |= op; |
| // op: iop |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(1); |
| op <<= 20; |
| Value |= op; |
| break; |
| } |
| case AArch64::ADDHNB_ZZZ_B: |
| case AArch64::ADDHNB_ZZZ_H: |
| case AArch64::ADDHNB_ZZZ_S: |
| case AArch64::ADR_LSL_ZZZ_D_0: |
| case AArch64::ADR_LSL_ZZZ_D_1: |
| case AArch64::ADR_LSL_ZZZ_D_2: |
| case AArch64::ADR_LSL_ZZZ_D_3: |
| case AArch64::ADR_LSL_ZZZ_S_0: |
| case AArch64::ADR_LSL_ZZZ_S_1: |
| case AArch64::ADR_LSL_ZZZ_S_2: |
| case AArch64::ADR_LSL_ZZZ_S_3: |
| case AArch64::ADR_SXTW_ZZZ_D_0: |
| case AArch64::ADR_SXTW_ZZZ_D_1: |
| case AArch64::ADR_SXTW_ZZZ_D_2: |
| case AArch64::ADR_SXTW_ZZZ_D_3: |
| case AArch64::ADR_UXTW_ZZZ_D_0: |
| case AArch64::ADR_UXTW_ZZZ_D_1: |
| case AArch64::ADR_UXTW_ZZZ_D_2: |
| case AArch64::ADR_UXTW_ZZZ_D_3: |
| case AArch64::BDEP_ZZZ_B: |
| case AArch64::BDEP_ZZZ_D: |
| case AArch64::BDEP_ZZZ_H: |
| case AArch64::BDEP_ZZZ_S: |
| case AArch64::BEXT_ZZZ_B: |
| case AArch64::BEXT_ZZZ_D: |
| case AArch64::BEXT_ZZZ_H: |
| case AArch64::BEXT_ZZZ_S: |
| case AArch64::BGRP_ZZZ_B: |
| case AArch64::BGRP_ZZZ_D: |
| case AArch64::BGRP_ZZZ_H: |
| case AArch64::BGRP_ZZZ_S: |
| case AArch64::HISTSEG_ZZZ: |
| case AArch64::PMULLB_ZZZ_D: |
| case AArch64::PMULLB_ZZZ_H: |
| case AArch64::PMULLB_ZZZ_Q: |
| case AArch64::PMULLT_ZZZ_D: |
| case AArch64::PMULLT_ZZZ_H: |
| case AArch64::PMULLT_ZZZ_Q: |
| case AArch64::RADDHNB_ZZZ_B: |
| case AArch64::RADDHNB_ZZZ_H: |
| case AArch64::RADDHNB_ZZZ_S: |
| case AArch64::RAX1_ZZZ_D: |
| case AArch64::RSUBHNB_ZZZ_B: |
| case AArch64::RSUBHNB_ZZZ_H: |
| case AArch64::RSUBHNB_ZZZ_S: |
| case AArch64::SABDLB_ZZZ_D: |
| case AArch64::SABDLB_ZZZ_H: |
| case AArch64::SABDLB_ZZZ_S: |
| case AArch64::SABDLT_ZZZ_D: |
| case AArch64::SABDLT_ZZZ_H: |
| case AArch64::SABDLT_ZZZ_S: |
| case AArch64::SADDLBT_ZZZ_D: |
| case AArch64::SADDLBT_ZZZ_H: |
| case AArch64::SADDLBT_ZZZ_S: |
| case AArch64::SADDLB_ZZZ_D: |
| case AArch64::SADDLB_ZZZ_H: |
| case AArch64::SADDLB_ZZZ_S: |
| case AArch64::SADDLT_ZZZ_D: |
| case AArch64::SADDLT_ZZZ_H: |
| case AArch64::SADDLT_ZZZ_S: |
| case AArch64::SADDWB_ZZZ_D: |
| case AArch64::SADDWB_ZZZ_H: |
| case AArch64::SADDWB_ZZZ_S: |
| case AArch64::SADDWT_ZZZ_D: |
| case AArch64::SADDWT_ZZZ_H: |
| case AArch64::SADDWT_ZZZ_S: |
| case AArch64::SM4EKEY_ZZZ_S: |
| case AArch64::SMULLB_ZZZ_D: |
| case AArch64::SMULLB_ZZZ_H: |
| case AArch64::SMULLB_ZZZ_S: |
| case AArch64::SMULLT_ZZZ_D: |
| case AArch64::SMULLT_ZZZ_H: |
| case AArch64::SMULLT_ZZZ_S: |
| case AArch64::SQDMULLB_ZZZ_D: |
| case AArch64::SQDMULLB_ZZZ_H: |
| case AArch64::SQDMULLB_ZZZ_S: |
| case AArch64::SQDMULLT_ZZZ_D: |
| case AArch64::SQDMULLT_ZZZ_H: |
| case AArch64::SQDMULLT_ZZZ_S: |
| case AArch64::SSUBLBT_ZZZ_D: |
| case AArch64::SSUBLBT_ZZZ_H: |
| case AArch64::SSUBLBT_ZZZ_S: |
| case AArch64::SSUBLB_ZZZ_D: |
| case AArch64::SSUBLB_ZZZ_H: |
| case AArch64::SSUBLB_ZZZ_S: |
| case AArch64::SSUBLTB_ZZZ_D: |
| case AArch64::SSUBLTB_ZZZ_H: |
| case AArch64::SSUBLTB_ZZZ_S: |
| case AArch64::SSUBLT_ZZZ_D: |
| case AArch64::SSUBLT_ZZZ_H: |
| case AArch64::SSUBLT_ZZZ_S: |
| case AArch64::SSUBWB_ZZZ_D: |
| case AArch64::SSUBWB_ZZZ_H: |
| case AArch64::SSUBWB_ZZZ_S: |
| case AArch64::SSUBWT_ZZZ_D: |
| case AArch64::SSUBWT_ZZZ_H: |
| case AArch64::SSUBWT_ZZZ_S: |
| case AArch64::SUBHNB_ZZZ_B: |
| case AArch64::SUBHNB_ZZZ_H: |
| case AArch64::SUBHNB_ZZZ_S: |
| case AArch64::UABDLB_ZZZ_D: |
| case AArch64::UABDLB_ZZZ_H: |
| case AArch64::UABDLB_ZZZ_S: |
| case AArch64::UABDLT_ZZZ_D: |
| case AArch64::UABDLT_ZZZ_H: |
| case AArch64::UABDLT_ZZZ_S: |
| case AArch64::UADDLB_ZZZ_D: |
| case AArch64::UADDLB_ZZZ_H: |
| case AArch64::UADDLB_ZZZ_S: |
| case AArch64::UADDLT_ZZZ_D: |
| case AArch64::UADDLT_ZZZ_H: |
| case AArch64::UADDLT_ZZZ_S: |
| case AArch64::UADDWB_ZZZ_D: |
| case AArch64::UADDWB_ZZZ_H: |
| case AArch64::UADDWB_ZZZ_S: |
| case AArch64::UADDWT_ZZZ_D: |
| case AArch64::UADDWT_ZZZ_H: |
| case AArch64::UADDWT_ZZZ_S: |
| case AArch64::UMULLB_ZZZ_D: |
| case AArch64::UMULLB_ZZZ_H: |
| case AArch64::UMULLB_ZZZ_S: |
| case AArch64::UMULLT_ZZZ_D: |
| case AArch64::UMULLT_ZZZ_H: |
| case AArch64::UMULLT_ZZZ_S: |
| case AArch64::USUBLB_ZZZ_D: |
| case AArch64::USUBLB_ZZZ_H: |
| case AArch64::USUBLB_ZZZ_S: |
| case AArch64::USUBLT_ZZZ_D: |
| case AArch64::USUBLT_ZZZ_H: |
| case AArch64::USUBLT_ZZZ_S: |
| case AArch64::USUBWB_ZZZ_D: |
| case AArch64::USUBWB_ZZZ_H: |
| case AArch64::USUBWB_ZZZ_S: |
| case AArch64::USUBWT_ZZZ_D: |
| case AArch64::USUBWT_ZZZ_H: |
| case AArch64::USUBWT_ZZZ_S: { |
| // op: Zd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Zn |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: Zm |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 16; |
| Value |= op; |
| break; |
| } |
| case AArch64::FMUL_ZZZI_H: |
| case AArch64::MUL_ZZZI_H: |
| case AArch64::SQDMULH_ZZZI_H: |
| case AArch64::SQRDMULH_ZZZI_H: { |
| // op: Zd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Zn |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: Zm |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(7); |
| op <<= 16; |
| Value |= op; |
| // op: iop |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| Value |= (op & UINT64_C(4)) << 20; |
| Value |= (op & UINT64_C(3)) << 19; |
| break; |
| } |
| case AArch64::SMULLB_ZZZI_S: |
| case AArch64::SMULLT_ZZZI_S: |
| case AArch64::SQDMULLB_ZZZI_S: |
| case AArch64::SQDMULLT_ZZZI_S: |
| case AArch64::UMULLB_ZZZI_S: |
| case AArch64::UMULLT_ZZZI_S: { |
| // op: Zd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Zn |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: Zm |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(7); |
| op <<= 16; |
| Value |= op; |
| // op: iop |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| Value |= (op & UINT64_C(6)) << 18; |
| Value |= (op & UINT64_C(1)) << 11; |
| break; |
| } |
| case AArch64::FMUL_ZZZI_S: |
| case AArch64::MUL_ZZZI_S: |
| case AArch64::SQDMULH_ZZZI_S: |
| case AArch64::SQRDMULH_ZZZI_S: { |
| // op: Zd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Zn |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: Zm |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(7); |
| op <<= 16; |
| Value |= op; |
| // op: iop |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(3); |
| op <<= 19; |
| Value |= op; |
| break; |
| } |
| case AArch64::DUP_ZZI_S: { |
| // op: Zd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Zn |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: idx |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| Value |= (op & UINT64_C(12)) << 20; |
| Value |= (op & UINT64_C(3)) << 19; |
| break; |
| } |
| case AArch64::DUP_ZZI_H: { |
| // op: Zd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Zn |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: idx |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| Value |= (op & UINT64_C(24)) << 19; |
| Value |= (op & UINT64_C(7)) << 18; |
| break; |
| } |
| case AArch64::DUP_ZZI_B: { |
| // op: Zd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Zn |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: idx |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| Value |= (op & UINT64_C(48)) << 18; |
| Value |= (op & UINT64_C(15)) << 17; |
| break; |
| } |
| case AArch64::DUP_ZZI_D: { |
| // op: Zd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Zn |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: idx |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| Value |= (op & UINT64_C(6)) << 21; |
| Value |= (op & UINT64_C(1)) << 20; |
| break; |
| } |
| case AArch64::DUP_ZZI_Q: { |
| // op: Zd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Zn |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: idx |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(3); |
| op <<= 22; |
| Value |= op; |
| break; |
| } |
| case AArch64::LSL_ZZI_H: |
| case AArch64::SSHLLB_ZZI_S: |
| case AArch64::SSHLLT_ZZI_S: |
| case AArch64::USHLLB_ZZI_S: |
| case AArch64::USHLLT_ZZI_S: { |
| // op: Zd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Zn |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: imm |
| op = getVecShiftL16OpValue(MI, 2, Fixups, STI); |
| op &= UINT64_C(15); |
| op <<= 16; |
| Value |= op; |
| break; |
| } |
| case AArch64::LSL_ZZI_S: |
| case AArch64::SSHLLB_ZZI_D: |
| case AArch64::SSHLLT_ZZI_D: |
| case AArch64::USHLLB_ZZI_D: |
| case AArch64::USHLLT_ZZI_D: { |
| // op: Zd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Zn |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: imm |
| op = getVecShiftL32OpValue(MI, 2, Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 16; |
| Value |= op; |
| break; |
| } |
| case AArch64::LSL_ZZI_D: { |
| // op: Zd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Zn |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: imm |
| op = getVecShiftL64OpValue(MI, 2, Fixups, STI); |
| Value |= (op & UINT64_C(32)) << 17; |
| Value |= (op & UINT64_C(31)) << 16; |
| break; |
| } |
| case AArch64::LSL_ZZI_B: |
| case AArch64::SSHLLB_ZZI_H: |
| case AArch64::SSHLLT_ZZI_H: |
| case AArch64::USHLLB_ZZI_H: |
| case AArch64::USHLLT_ZZI_H: { |
| // op: Zd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Zn |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: imm |
| op = getVecShiftL8OpValue(MI, 2, Fixups, STI); |
| op &= UINT64_C(7); |
| op <<= 16; |
| Value |= op; |
| break; |
| } |
| case AArch64::ASR_ZZI_H: |
| case AArch64::LSR_ZZI_H: |
| case AArch64::RSHRNB_ZZI_H: |
| case AArch64::SHRNB_ZZI_H: |
| case AArch64::SQRSHRNB_ZZI_H: |
| case AArch64::SQRSHRUNB_ZZI_H: |
| case AArch64::SQSHRNB_ZZI_H: |
| case AArch64::SQSHRUNB_ZZI_H: |
| case AArch64::UQRSHRNB_ZZI_H: |
| case AArch64::UQSHRNB_ZZI_H: { |
| // op: Zd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Zn |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: imm |
| op = getVecShiftR16OpValue(MI, 2, Fixups, STI); |
| op &= UINT64_C(15); |
| op <<= 16; |
| Value |= op; |
| break; |
| } |
| case AArch64::ASR_ZZI_S: |
| case AArch64::LSR_ZZI_S: |
| case AArch64::RSHRNB_ZZI_S: |
| case AArch64::SHRNB_ZZI_S: |
| case AArch64::SQRSHRNB_ZZI_S: |
| case AArch64::SQRSHRUNB_ZZI_S: |
| case AArch64::SQSHRNB_ZZI_S: |
| case AArch64::SQSHRUNB_ZZI_S: |
| case AArch64::UQRSHRNB_ZZI_S: |
| case AArch64::UQSHRNB_ZZI_S: { |
| // op: Zd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Zn |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: imm |
| op = getVecShiftR32OpValue(MI, 2, Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 16; |
| Value |= op; |
| break; |
| } |
| case AArch64::ASR_ZZI_D: |
| case AArch64::LSR_ZZI_D: { |
| // op: Zd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Zn |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: imm |
| op = getVecShiftR64OpValue(MI, 2, Fixups, STI); |
| Value |= (op & UINT64_C(32)) << 17; |
| Value |= (op & UINT64_C(31)) << 16; |
| break; |
| } |
| case AArch64::ASR_ZZI_B: |
| case AArch64::LSR_ZZI_B: |
| case AArch64::RSHRNB_ZZI_B: |
| case AArch64::SHRNB_ZZI_B: |
| case AArch64::SQRSHRNB_ZZI_B: |
| case AArch64::SQRSHRUNB_ZZI_B: |
| case AArch64::SQSHRNB_ZZI_B: |
| case AArch64::SQSHRUNB_ZZI_B: |
| case AArch64::UQRSHRNB_ZZI_B: |
| case AArch64::UQSHRNB_ZZI_B: { |
| // op: Zd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Zn |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: imm |
| op = getVecShiftR8OpValue(MI, 2, Fixups, STI); |
| op &= UINT64_C(7); |
| op <<= 16; |
| Value |= op; |
| break; |
| } |
| case AArch64::EXT_ZZI_B: { |
| // op: Zd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Zn |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: imm8 |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| Value |= (op & UINT64_C(248)) << 13; |
| Value |= (op & UINT64_C(7)) << 10; |
| break; |
| } |
| case AArch64::SQXTNT_ZZ_B: |
| case AArch64::SQXTNT_ZZ_H: |
| case AArch64::SQXTNT_ZZ_S: |
| case AArch64::SQXTUNT_ZZ_B: |
| case AArch64::SQXTUNT_ZZ_H: |
| case AArch64::SQXTUNT_ZZ_S: |
| case AArch64::UQXTNT_ZZ_B: |
| case AArch64::UQXTNT_ZZ_H: |
| case AArch64::UQXTNT_ZZ_S: { |
| // op: Zd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Zn |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| break; |
| } |
| case AArch64::HISTCNT_ZPzZZ_D: |
| case AArch64::HISTCNT_ZPzZZ_S: { |
| // op: Zd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Zn |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: Pg |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(7); |
| op <<= 10; |
| Value |= op; |
| // op: Zm |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 16; |
| Value |= op; |
| break; |
| } |
| case AArch64::ADDHNT_ZZZ_B: |
| case AArch64::ADDHNT_ZZZ_H: |
| case AArch64::ADDHNT_ZZZ_S: |
| case AArch64::EORBT_ZZZ_B: |
| case AArch64::EORBT_ZZZ_D: |
| case AArch64::EORBT_ZZZ_H: |
| case AArch64::EORBT_ZZZ_S: |
| case AArch64::EORTB_ZZZ_B: |
| case AArch64::EORTB_ZZZ_D: |
| case AArch64::EORTB_ZZZ_H: |
| case AArch64::EORTB_ZZZ_S: |
| case AArch64::RADDHNT_ZZZ_B: |
| case AArch64::RADDHNT_ZZZ_H: |
| case AArch64::RADDHNT_ZZZ_S: |
| case AArch64::RSUBHNT_ZZZ_B: |
| case AArch64::RSUBHNT_ZZZ_H: |
| case AArch64::RSUBHNT_ZZZ_S: |
| case AArch64::SUBHNT_ZZZ_B: |
| case AArch64::SUBHNT_ZZZ_H: |
| case AArch64::SUBHNT_ZZZ_S: { |
| // op: Zd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Zn |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: Zm |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 16; |
| Value |= op; |
| break; |
| } |
| case AArch64::SLI_ZZI_H: { |
| // op: Zd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Zn |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: imm |
| op = getVecShiftL16OpValue(MI, 3, Fixups, STI); |
| op &= UINT64_C(15); |
| op <<= 16; |
| Value |= op; |
| break; |
| } |
| case AArch64::SLI_ZZI_S: { |
| // op: Zd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Zn |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: imm |
| op = getVecShiftL32OpValue(MI, 3, Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 16; |
| Value |= op; |
| break; |
| } |
| case AArch64::SLI_ZZI_D: { |
| // op: Zd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Zn |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: imm |
| op = getVecShiftL64OpValue(MI, 3, Fixups, STI); |
| Value |= (op & UINT64_C(32)) << 17; |
| Value |= (op & UINT64_C(31)) << 16; |
| break; |
| } |
| case AArch64::SLI_ZZI_B: { |
| // op: Zd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Zn |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: imm |
| op = getVecShiftL8OpValue(MI, 3, Fixups, STI); |
| op &= UINT64_C(7); |
| op <<= 16; |
| Value |= op; |
| break; |
| } |
| case AArch64::RSHRNT_ZZI_H: |
| case AArch64::SHRNT_ZZI_H: |
| case AArch64::SQRSHRNT_ZZI_H: |
| case AArch64::SQRSHRUNT_ZZI_H: |
| case AArch64::SQSHRNT_ZZI_H: |
| case AArch64::SQSHRUNT_ZZI_H: |
| case AArch64::SRI_ZZI_H: |
| case AArch64::UQRSHRNT_ZZI_H: |
| case AArch64::UQSHRNT_ZZI_H: { |
| // op: Zd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Zn |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: imm |
| op = getVecShiftR16OpValue(MI, 3, Fixups, STI); |
| op &= UINT64_C(15); |
| op <<= 16; |
| Value |= op; |
| break; |
| } |
| case AArch64::RSHRNT_ZZI_S: |
| case AArch64::SHRNT_ZZI_S: |
| case AArch64::SQRSHRNT_ZZI_S: |
| case AArch64::SQRSHRUNT_ZZI_S: |
| case AArch64::SQSHRNT_ZZI_S: |
| case AArch64::SQSHRUNT_ZZI_S: |
| case AArch64::SRI_ZZI_S: |
| case AArch64::UQRSHRNT_ZZI_S: |
| case AArch64::UQSHRNT_ZZI_S: { |
| // op: Zd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Zn |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: imm |
| op = getVecShiftR32OpValue(MI, 3, Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 16; |
| Value |= op; |
| break; |
| } |
| case AArch64::SRI_ZZI_D: { |
| // op: Zd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Zn |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: imm |
| op = getVecShiftR64OpValue(MI, 3, Fixups, STI); |
| Value |= (op & UINT64_C(32)) << 17; |
| Value |= (op & UINT64_C(31)) << 16; |
| break; |
| } |
| case AArch64::RSHRNT_ZZI_B: |
| case AArch64::SHRNT_ZZI_B: |
| case AArch64::SQRSHRNT_ZZI_B: |
| case AArch64::SQRSHRUNT_ZZI_B: |
| case AArch64::SQSHRNT_ZZI_B: |
| case AArch64::SQSHRUNT_ZZI_B: |
| case AArch64::SRI_ZZI_B: |
| case AArch64::UQRSHRNT_ZZI_B: |
| case AArch64::UQSHRNT_ZZI_B: { |
| // op: Zd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Zn |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: imm |
| op = getVecShiftR8OpValue(MI, 3, Fixups, STI); |
| op &= UINT64_C(7); |
| op <<= 16; |
| Value |= op; |
| break; |
| } |
| case AArch64::FCVTLT_ZPmZ_HtoS: |
| case AArch64::FCVTLT_ZPmZ_StoD: |
| case AArch64::FCVTNT_ZPmZ_DtoS: |
| case AArch64::FCVTNT_ZPmZ_StoH: |
| case AArch64::FCVTXNT_ZPmZ_DtoS: { |
| // op: Zd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Zn |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: Pg |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(7); |
| op <<= 10; |
| Value |= op; |
| break; |
| } |
| case AArch64::DUP_ZI_B: |
| case AArch64::DUP_ZI_D: |
| case AArch64::DUP_ZI_H: |
| case AArch64::DUP_ZI_S: { |
| // op: Zd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: imm |
| op = getImm8OptLsl(MI, 1, Fixups, STI); |
| op &= UINT64_C(511); |
| op <<= 5; |
| Value |= op; |
| break; |
| } |
| case AArch64::INDEX_II_B: |
| case AArch64::INDEX_II_D: |
| case AArch64::INDEX_II_H: |
| case AArch64::INDEX_II_S: { |
| // op: Zd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: imm5 |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: imm5b |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 16; |
| Value |= op; |
| break; |
| } |
| case AArch64::FDUP_ZI_D: |
| case AArch64::FDUP_ZI_H: |
| case AArch64::FDUP_ZI_S: { |
| // op: Zd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: imm8 |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(255); |
| op <<= 5; |
| Value |= op; |
| break; |
| } |
| case AArch64::DUPM_ZI: { |
| // op: Zd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: imms |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(8191); |
| op <<= 5; |
| Value |= op; |
| break; |
| } |
| case AArch64::FCMLA_ZPmZZ_D: |
| case AArch64::FCMLA_ZPmZZ_H: |
| case AArch64::FCMLA_ZPmZZ_S: { |
| // op: Zda |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Pg |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(7); |
| op <<= 10; |
| Value |= op; |
| // op: Zn |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: Zm |
| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 16; |
| Value |= op; |
| // op: imm |
| op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); |
| op &= UINT64_C(3); |
| op <<= 13; |
| Value |= op; |
| break; |
| } |
| case AArch64::SMLALB_ZZZI_D: |
| case AArch64::SMLALT_ZZZI_D: |
| case AArch64::SMLSLB_ZZZI_D: |
| case AArch64::SMLSLT_ZZZI_D: |
| case AArch64::SQDMLALB_ZZZI_D: |
| case AArch64::SQDMLALT_ZZZI_D: |
| case AArch64::SQDMLSLB_ZZZI_D: |
| case AArch64::SQDMLSLT_ZZZI_D: |
| case AArch64::UMLALB_ZZZI_D: |
| case AArch64::UMLALT_ZZZI_D: |
| case AArch64::UMLSLB_ZZZI_D: |
| case AArch64::UMLSLT_ZZZI_D: { |
| // op: Zda |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Zn |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: Zm |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(15); |
| op <<= 16; |
| Value |= op; |
| // op: iop |
| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
| Value |= (op & UINT64_C(2)) << 19; |
| Value |= (op & UINT64_C(1)) << 11; |
| break; |
| } |
| case AArch64::FMLA_ZZZI_D: |
| case AArch64::FMLS_ZZZI_D: |
| case AArch64::MLA_ZZZI_D: |
| case AArch64::MLS_ZZZI_D: |
| case AArch64::SQRDMLAH_ZZZI_D: |
| case AArch64::SQRDMLSH_ZZZI_D: { |
| // op: Zda |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Zn |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: Zm |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(15); |
| op <<= 16; |
| Value |= op; |
| // op: iop |
| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
| op &= UINT64_C(1); |
| op <<= 20; |
| Value |= op; |
| break; |
| } |
| case AArch64::ADCLB_ZZZ_D: |
| case AArch64::ADCLB_ZZZ_S: |
| case AArch64::ADCLT_ZZZ_D: |
| case AArch64::ADCLT_ZZZ_S: |
| case AArch64::FMLALB_ZZZ_SHH: |
| case AArch64::FMLALT_ZZZ_SHH: |
| case AArch64::FMLSLB_ZZZ_SHH: |
| case AArch64::FMLSLT_ZZZ_SHH: |
| case AArch64::SABALB_ZZZ_D: |
| case AArch64::SABALB_ZZZ_H: |
| case AArch64::SABALB_ZZZ_S: |
| case AArch64::SABALT_ZZZ_D: |
| case AArch64::SABALT_ZZZ_H: |
| case AArch64::SABALT_ZZZ_S: |
| case AArch64::SABA_ZZZ_B: |
| case AArch64::SABA_ZZZ_D: |
| case AArch64::SABA_ZZZ_H: |
| case AArch64::SABA_ZZZ_S: |
| case AArch64::SBCLB_ZZZ_D: |
| case AArch64::SBCLB_ZZZ_S: |
| case AArch64::SBCLT_ZZZ_D: |
| case AArch64::SBCLT_ZZZ_S: |
| case AArch64::SDOT_ZZZ_D: |
| case AArch64::SDOT_ZZZ_S: |
| case AArch64::SMLALB_ZZZ_D: |
| case AArch64::SMLALB_ZZZ_H: |
| case AArch64::SMLALB_ZZZ_S: |
| case AArch64::SMLALT_ZZZ_D: |
| case AArch64::SMLALT_ZZZ_H: |
| case AArch64::SMLALT_ZZZ_S: |
| case AArch64::SMLSLB_ZZZ_D: |
| case AArch64::SMLSLB_ZZZ_H: |
| case AArch64::SMLSLB_ZZZ_S: |
| case AArch64::SMLSLT_ZZZ_D: |
| case AArch64::SMLSLT_ZZZ_H: |
| case AArch64::SMLSLT_ZZZ_S: |
| case AArch64::SQDMLALBT_ZZZ_D: |
| case AArch64::SQDMLALBT_ZZZ_H: |
| case AArch64::SQDMLALBT_ZZZ_S: |
| case AArch64::SQDMLALB_ZZZ_D: |
| case AArch64::SQDMLALB_ZZZ_H: |
| case AArch64::SQDMLALB_ZZZ_S: |
| case AArch64::SQDMLALT_ZZZ_D: |
| case AArch64::SQDMLALT_ZZZ_H: |
| case AArch64::SQDMLALT_ZZZ_S: |
| case AArch64::SQDMLSLBT_ZZZ_D: |
| case AArch64::SQDMLSLBT_ZZZ_H: |
| case AArch64::SQDMLSLBT_ZZZ_S: |
| case AArch64::SQDMLSLB_ZZZ_D: |
| case AArch64::SQDMLSLB_ZZZ_H: |
| case AArch64::SQDMLSLB_ZZZ_S: |
| case AArch64::SQDMLSLT_ZZZ_D: |
| case AArch64::SQDMLSLT_ZZZ_H: |
| case AArch64::SQDMLSLT_ZZZ_S: |
| case AArch64::SQRDMLAH_ZZZ_B: |
| case AArch64::SQRDMLAH_ZZZ_D: |
| case AArch64::SQRDMLAH_ZZZ_H: |
| case AArch64::SQRDMLAH_ZZZ_S: |
| case AArch64::SQRDMLSH_ZZZ_B: |
| case AArch64::SQRDMLSH_ZZZ_D: |
| case AArch64::SQRDMLSH_ZZZ_H: |
| case AArch64::SQRDMLSH_ZZZ_S: |
| case AArch64::UABALB_ZZZ_D: |
| case AArch64::UABALB_ZZZ_H: |
| case AArch64::UABALB_ZZZ_S: |
| case AArch64::UABALT_ZZZ_D: |
| case AArch64::UABALT_ZZZ_H: |
| case AArch64::UABALT_ZZZ_S: |
| case AArch64::UABA_ZZZ_B: |
| case AArch64::UABA_ZZZ_D: |
| case AArch64::UABA_ZZZ_H: |
| case AArch64::UABA_ZZZ_S: |
| case AArch64::UDOT_ZZZ_D: |
| case AArch64::UDOT_ZZZ_S: |
| case AArch64::UMLALB_ZZZ_D: |
| case AArch64::UMLALB_ZZZ_H: |
| case AArch64::UMLALB_ZZZ_S: |
| case AArch64::UMLALT_ZZZ_D: |
| case AArch64::UMLALT_ZZZ_H: |
| case AArch64::UMLALT_ZZZ_S: |
| case AArch64::UMLSLB_ZZZ_D: |
| case AArch64::UMLSLB_ZZZ_H: |
| case AArch64::UMLSLB_ZZZ_S: |
| case AArch64::UMLSLT_ZZZ_D: |
| case AArch64::UMLSLT_ZZZ_H: |
| case AArch64::UMLSLT_ZZZ_S: { |
| // op: Zda |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Zn |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: Zm |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 16; |
| Value |= op; |
| break; |
| } |
| case AArch64::CDOT_ZZZ_D: |
| case AArch64::CDOT_ZZZ_S: |
| case AArch64::CMLA_ZZZ_B: |
| case AArch64::CMLA_ZZZ_D: |
| case AArch64::CMLA_ZZZ_H: |
| case AArch64::CMLA_ZZZ_S: |
| case AArch64::SQRDCMLAH_ZZZ_B: |
| case AArch64::SQRDCMLAH_ZZZ_D: |
| case AArch64::SQRDCMLAH_ZZZ_H: |
| case AArch64::SQRDCMLAH_ZZZ_S: { |
| // op: Zda |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Zn |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: Zm |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 16; |
| Value |= op; |
| // op: rot |
| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
| op &= UINT64_C(3); |
| op <<= 10; |
| Value |= op; |
| break; |
| } |
| case AArch64::FMLA_ZZZI_H: |
| case AArch64::FMLS_ZZZI_H: |
| case AArch64::MLA_ZZZI_H: |
| case AArch64::MLS_ZZZI_H: |
| case AArch64::SQRDMLAH_ZZZI_H: |
| case AArch64::SQRDMLSH_ZZZI_H: { |
| // op: Zda |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Zn |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: Zm |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(7); |
| op <<= 16; |
| Value |= op; |
| // op: iop |
| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
| Value |= (op & UINT64_C(4)) << 20; |
| Value |= (op & UINT64_C(3)) << 19; |
| break; |
| } |
| case AArch64::FMLALB_ZZZI_SHH: |
| case AArch64::FMLALT_ZZZI_SHH: |
| case AArch64::FMLSLB_ZZZI_SHH: |
| case AArch64::FMLSLT_ZZZI_SHH: |
| case AArch64::SMLALB_ZZZI_S: |
| case AArch64::SMLALT_ZZZI_S: |
| case AArch64::SMLSLB_ZZZI_S: |
| case AArch64::SMLSLT_ZZZI_S: |
| case AArch64::SQDMLALB_ZZZI_S: |
| case AArch64::SQDMLALT_ZZZI_S: |
| case AArch64::SQDMLSLB_ZZZI_S: |
| case AArch64::SQDMLSLT_ZZZI_S: |
| case AArch64::UMLALB_ZZZI_S: |
| case AArch64::UMLALT_ZZZI_S: |
| case AArch64::UMLSLB_ZZZI_S: |
| case AArch64::UMLSLT_ZZZI_S: { |
| // op: Zda |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Zn |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: Zm |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(7); |
| op <<= 16; |
| Value |= op; |
| // op: iop |
| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
| Value |= (op & UINT64_C(6)) << 18; |
| Value |= (op & UINT64_C(1)) << 11; |
| break; |
| } |
| case AArch64::FMLA_ZZZI_S: |
| case AArch64::FMLS_ZZZI_S: |
| case AArch64::MLA_ZZZI_S: |
| case AArch64::MLS_ZZZI_S: |
| case AArch64::SQRDMLAH_ZZZI_S: |
| case AArch64::SQRDMLSH_ZZZI_S: { |
| // op: Zda |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Zn |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: Zm |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(7); |
| op <<= 16; |
| Value |= op; |
| // op: iop |
| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
| op &= UINT64_C(3); |
| op <<= 19; |
| Value |= op; |
| break; |
| } |
| case AArch64::FCMLA_ZZZI_S: { |
| // op: Zda |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Zn |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: imm |
| op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); |
| op &= UINT64_C(3); |
| op <<= 10; |
| Value |= op; |
| // op: Zm |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(15); |
| op <<= 16; |
| Value |= op; |
| // op: iop |
| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
| op &= UINT64_C(1); |
| op <<= 20; |
| Value |= op; |
| break; |
| } |
| case AArch64::FCMLA_ZZZI_H: { |
| // op: Zda |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Zn |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: imm |
| op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); |
| op &= UINT64_C(3); |
| op <<= 10; |
| Value |= op; |
| // op: Zm |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(7); |
| op <<= 16; |
| Value |= op; |
| // op: iop |
| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
| op &= UINT64_C(3); |
| op <<= 19; |
| Value |= op; |
| break; |
| } |
| case AArch64::SRSRA_ZZI_H: |
| case AArch64::SSRA_ZZI_H: |
| case AArch64::URSRA_ZZI_H: |
| case AArch64::USRA_ZZI_H: { |
| // op: Zda |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Zn |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: imm |
| op = getVecShiftR16OpValue(MI, 3, Fixups, STI); |
| op &= UINT64_C(15); |
| op <<= 16; |
| Value |= op; |
| break; |
| } |
| case AArch64::SRSRA_ZZI_S: |
| case AArch64::SSRA_ZZI_S: |
| case AArch64::URSRA_ZZI_S: |
| case AArch64::USRA_ZZI_S: { |
| // op: Zda |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Zn |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: imm |
| op = getVecShiftR32OpValue(MI, 3, Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 16; |
| Value |= op; |
| break; |
| } |
| case AArch64::SRSRA_ZZI_D: |
| case AArch64::SSRA_ZZI_D: |
| case AArch64::URSRA_ZZI_D: |
| case AArch64::USRA_ZZI_D: { |
| // op: Zda |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Zn |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: imm |
| op = getVecShiftR64OpValue(MI, 3, Fixups, STI); |
| Value |= (op & UINT64_C(32)) << 17; |
| Value |= (op & UINT64_C(31)) << 16; |
| break; |
| } |
| case AArch64::SRSRA_ZZI_B: |
| case AArch64::SSRA_ZZI_B: |
| case AArch64::URSRA_ZZI_B: |
| case AArch64::USRA_ZZI_B: { |
| // op: Zda |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Zn |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: imm |
| op = getVecShiftR8OpValue(MI, 3, Fixups, STI); |
| op &= UINT64_C(7); |
| op <<= 16; |
| Value |= op; |
| break; |
| } |
| case AArch64::SDOT_ZZZI_D: |
| case AArch64::UDOT_ZZZI_D: { |
| // op: Zda |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Zn |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: iop |
| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
| op &= UINT64_C(1); |
| op <<= 20; |
| Value |= op; |
| // op: Zm |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(15); |
| op <<= 16; |
| Value |= op; |
| break; |
| } |
| case AArch64::SDOT_ZZZI_S: |
| case AArch64::UDOT_ZZZI_S: { |
| // op: Zda |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Zn |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: iop |
| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
| op &= UINT64_C(3); |
| op <<= 19; |
| Value |= op; |
| // op: Zm |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(7); |
| op <<= 16; |
| Value |= op; |
| break; |
| } |
| case AArch64::CDOT_ZZZI_D: |
| case AArch64::CMLA_ZZZI_S: |
| case AArch64::SQRDCMLAH_ZZZI_S: { |
| // op: Zda |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Zn |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: rot |
| op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); |
| op &= UINT64_C(3); |
| op <<= 10; |
| Value |= op; |
| // op: iop |
| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
| op &= UINT64_C(1); |
| op <<= 20; |
| Value |= op; |
| // op: Zm |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(15); |
| op <<= 16; |
| Value |= op; |
| break; |
| } |
| case AArch64::CDOT_ZZZI_S: |
| case AArch64::CMLA_ZZZI_H: |
| case AArch64::SQRDCMLAH_ZZZI_H: { |
| // op: Zda |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Zn |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: rot |
| op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); |
| op &= UINT64_C(3); |
| op <<= 10; |
| Value |= op; |
| // op: iop |
| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
| op &= UINT64_C(3); |
| op <<= 19; |
| Value |= op; |
| // op: Zm |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(7); |
| op <<= 16; |
| Value |= op; |
| break; |
| } |
| case AArch64::AESIMC_ZZ_B: |
| case AArch64::AESMC_ZZ_B: { |
| // op: Zdn |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| break; |
| } |
| case AArch64::BCAX_ZZZZ_D: |
| case AArch64::BSL1N_ZZZZ_D: |
| case AArch64::BSL2N_ZZZZ_D: |
| case AArch64::BSL_ZZZZ_D: |
| case AArch64::EOR3_ZZZZ_D: |
| case AArch64::NBSL_ZZZZ_D: { |
| // op: Zdn |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Zk |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: Zm |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 16; |
| Value |= op; |
| break; |
| } |
| case AArch64::AESD_ZZZ_B: |
| case AArch64::AESE_ZZZ_B: |
| case AArch64::SM4E_ZZZ_S: { |
| // op: Zdn |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Zm |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| break; |
| } |
| case AArch64::XAR_ZZZI_H: { |
| // op: Zdn |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Zm |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: imm |
| op = getVecShiftR16OpValue(MI, 3, Fixups, STI); |
| op &= UINT64_C(15); |
| op <<= 16; |
| Value |= op; |
| break; |
| } |
| case AArch64::XAR_ZZZI_S: { |
| // op: Zdn |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Zm |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: imm |
| op = getVecShiftR32OpValue(MI, 3, Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 16; |
| Value |= op; |
| break; |
| } |
| case AArch64::XAR_ZZZI_D: { |
| // op: Zdn |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Zm |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: imm |
| op = getVecShiftR64OpValue(MI, 3, Fixups, STI); |
| Value |= (op & UINT64_C(32)) << 17; |
| Value |= (op & UINT64_C(31)) << 16; |
| break; |
| } |
| case AArch64::XAR_ZZZI_B: { |
| // op: Zdn |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Zm |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: imm |
| op = getVecShiftR8OpValue(MI, 3, Fixups, STI); |
| op &= UINT64_C(7); |
| op <<= 16; |
| Value |= op; |
| break; |
| } |
| case AArch64::FTMAD_ZZI_D: |
| case AArch64::FTMAD_ZZI_H: |
| case AArch64::FTMAD_ZZI_S: { |
| // op: Zdn |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Zm |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: imm3 |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(7); |
| op <<= 16; |
| Value |= op; |
| break; |
| } |
| case AArch64::EXT_ZZI: { |
| // op: Zdn |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Zm |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: imm8 |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| Value |= (op & UINT64_C(248)) << 13; |
| Value |= (op & UINT64_C(7)) << 10; |
| break; |
| } |
| case AArch64::CADD_ZZI_B: |
| case AArch64::CADD_ZZI_D: |
| case AArch64::CADD_ZZI_H: |
| case AArch64::CADD_ZZI_S: |
| case AArch64::SQCADD_ZZI_B: |
| case AArch64::SQCADD_ZZI_D: |
| case AArch64::SQCADD_ZZI_H: |
| case AArch64::SQCADD_ZZI_S: { |
| // op: Zdn |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Zm |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: rot |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(1); |
| op <<= 10; |
| Value |= op; |
| break; |
| } |
| case AArch64::FCADD_ZPmZ_D: |
| case AArch64::FCADD_ZPmZ_H: |
| case AArch64::FCADD_ZPmZ_S: { |
| // op: Zdn |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Zm |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: Pg |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(7); |
| op <<= 10; |
| Value |= op; |
| // op: imm |
| op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
| op &= UINT64_C(1); |
| op <<= 16; |
| Value |= op; |
| break; |
| } |
| case AArch64::ADD_ZI_B: |
| case AArch64::ADD_ZI_D: |
| case AArch64::ADD_ZI_H: |
| case AArch64::ADD_ZI_S: |
| case AArch64::SQADD_ZI_B: |
| case AArch64::SQADD_ZI_D: |
| case AArch64::SQADD_ZI_H: |
| case AArch64::SQADD_ZI_S: |
| case AArch64::SQSUB_ZI_B: |
| case AArch64::SQSUB_ZI_D: |
| case AArch64::SQSUB_ZI_H: |
| case AArch64::SQSUB_ZI_S: |
| case AArch64::SUBR_ZI_B: |
| case AArch64::SUBR_ZI_D: |
| case AArch64::SUBR_ZI_H: |
| case AArch64::SUBR_ZI_S: |
| case AArch64::SUB_ZI_B: |
| case AArch64::SUB_ZI_D: |
| case AArch64::SUB_ZI_H: |
| case AArch64::SUB_ZI_S: |
| case AArch64::UQADD_ZI_B: |
| case AArch64::UQADD_ZI_D: |
| case AArch64::UQADD_ZI_H: |
| case AArch64::UQADD_ZI_S: |
| case AArch64::UQSUB_ZI_B: |
| case AArch64::UQSUB_ZI_D: |
| case AArch64::UQSUB_ZI_H: |
| case AArch64::UQSUB_ZI_S: { |
| // op: Zdn |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: imm |
| op = getImm8OptLsl(MI, 2, Fixups, STI); |
| op &= UINT64_C(511); |
| op <<= 5; |
| Value |= op; |
| break; |
| } |
| case AArch64::MUL_ZI_B: |
| case AArch64::MUL_ZI_D: |
| case AArch64::MUL_ZI_H: |
| case AArch64::MUL_ZI_S: |
| case AArch64::SMAX_ZI_B: |
| case AArch64::SMAX_ZI_D: |
| case AArch64::SMAX_ZI_H: |
| case AArch64::SMAX_ZI_S: |
| case AArch64::SMIN_ZI_B: |
| case AArch64::SMIN_ZI_D: |
| case AArch64::SMIN_ZI_H: |
| case AArch64::SMIN_ZI_S: |
| case AArch64::UMAX_ZI_B: |
| case AArch64::UMAX_ZI_D: |
| case AArch64::UMAX_ZI_H: |
| case AArch64::UMAX_ZI_S: |
| case AArch64::UMIN_ZI_B: |
| case AArch64::UMIN_ZI_D: |
| case AArch64::UMIN_ZI_H: |
| case AArch64::UMIN_ZI_S: { |
| // op: Zdn |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: imm |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(255); |
| op <<= 5; |
| Value |= op; |
| break; |
| } |
| case AArch64::AND_ZI: |
| case AArch64::EOR_ZI: |
| case AArch64::ORR_ZI: { |
| // op: Zdn |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: imms13 |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(8191); |
| op <<= 5; |
| Value |= op; |
| break; |
| } |
| case AArch64::DECD_ZPiI: |
| case AArch64::DECH_ZPiI: |
| case AArch64::DECW_ZPiI: |
| case AArch64::INCD_ZPiI: |
| case AArch64::INCH_ZPiI: |
| case AArch64::INCW_ZPiI: |
| case AArch64::SQDECD_ZPiI: |
| case AArch64::SQDECH_ZPiI: |
| case AArch64::SQDECW_ZPiI: |
| case AArch64::SQINCD_ZPiI: |
| case AArch64::SQINCH_ZPiI: |
| case AArch64::SQINCW_ZPiI: |
| case AArch64::UQDECD_ZPiI: |
| case AArch64::UQDECH_ZPiI: |
| case AArch64::UQDECW_ZPiI: |
| case AArch64::UQINCD_ZPiI: |
| case AArch64::UQINCH_ZPiI: |
| case AArch64::UQINCW_ZPiI: { |
| // op: Zdn |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: pattern |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: imm4 |
| op = getSVEIncDecImm(MI, 3, Fixups, STI); |
| op &= UINT64_C(15); |
| op <<= 16; |
| Value |= op; |
| break; |
| } |
| case AArch64::FADDV_VPZ_D: |
| case AArch64::FADDV_VPZ_H: |
| case AArch64::FADDV_VPZ_S: |
| case AArch64::FMAXNMV_VPZ_D: |
| case AArch64::FMAXNMV_VPZ_H: |
| case AArch64::FMAXNMV_VPZ_S: |
| case AArch64::FMAXV_VPZ_D: |
| case AArch64::FMAXV_VPZ_H: |
| case AArch64::FMAXV_VPZ_S: |
| case AArch64::FMINNMV_VPZ_D: |
| case AArch64::FMINNMV_VPZ_H: |
| case AArch64::FMINNMV_VPZ_S: |
| case AArch64::FMINV_VPZ_D: |
| case AArch64::FMINV_VPZ_H: |
| case AArch64::FMINV_VPZ_S: { |
| // op: Zn |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: Vd |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Pg |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(7); |
| op <<= 10; |
| Value |= op; |
| break; |
| } |
| case AArch64::LD1B: |
| case AArch64::LD1B_D: |
| case AArch64::LD1B_H: |
| case AArch64::LD1B_S: |
| case AArch64::LD1D: |
| case AArch64::LD1H: |
| case AArch64::LD1H_D: |
| case AArch64::LD1H_S: |
| case AArch64::LD1SB_D: |
| case AArch64::LD1SB_H: |
| case AArch64::LD1SB_S: |
| case AArch64::LD1SH_D: |
| case AArch64::LD1SH_S: |
| case AArch64::LD1SW_D: |
| case AArch64::LD1W: |
| case AArch64::LD1W_D: |
| case AArch64::LDFF1B_D_REAL: |
| case AArch64::LDFF1B_H_REAL: |
| case AArch64::LDFF1B_REAL: |
| case AArch64::LDFF1B_S_REAL: |
| case AArch64::LDFF1D_REAL: |
| case AArch64::LDFF1H_D_REAL: |
| case AArch64::LDFF1H_REAL: |
| case AArch64::LDFF1H_S_REAL: |
| case AArch64::LDFF1SB_D_REAL: |
| case AArch64::LDFF1SB_H_REAL: |
| case AArch64::LDFF1SB_S_REAL: |
| case AArch64::LDFF1SH_D_REAL: |
| case AArch64::LDFF1SH_S_REAL: |
| case AArch64::LDFF1SW_D_REAL: |
| case AArch64::LDFF1W_D_REAL: |
| case AArch64::LDFF1W_REAL: { |
| // op: Zt |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Pg |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(7); |
| op <<= 10; |
| Value |= op; |
| // op: Rm |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 16; |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| break; |
| } |
| case AArch64::LD1RQ_B: |
| case AArch64::LD1RQ_D: |
| case AArch64::LD1RQ_H: |
| case AArch64::LD1RQ_W: { |
| // op: Zt |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Pg |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(7); |
| op <<= 10; |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: Rm |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 16; |
| Value |= op; |
| break; |
| } |
| case AArch64::LD2B_IMM: |
| case AArch64::LD2D_IMM: |
| case AArch64::LD2H_IMM: |
| case AArch64::LD2W_IMM: |
| case AArch64::LD3B_IMM: |
| case AArch64::LD3D_IMM: |
| case AArch64::LD3H_IMM: |
| case AArch64::LD3W_IMM: |
| case AArch64::LD4B_IMM: |
| case AArch64::LD4D_IMM: |
| case AArch64::LD4H_IMM: |
| case AArch64::LD4W_IMM: |
| case AArch64::LDNT1B_ZRI: |
| case AArch64::LDNT1D_ZRI: |
| case AArch64::LDNT1H_ZRI: |
| case AArch64::LDNT1W_ZRI: { |
| // op: Zt |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Pg |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(7); |
| op <<= 10; |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: imm4 |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(15); |
| op <<= 16; |
| Value |= op; |
| break; |
| } |
| case AArch64::LD1RQ_B_IMM: |
| case AArch64::LD1RQ_D_IMM: |
| case AArch64::LD1RQ_H_IMM: |
| case AArch64::LD1RQ_W_IMM: { |
| // op: Zt |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: Pg |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(7); |
| op <<= 10; |
| Value |= op; |
| // op: imm4 |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| op &= UINT64_C(15); |
| op <<= 16; |
| Value |= op; |
| break; |
| } |
| case AArch64::B: |
| case AArch64::BL: { |
| // op: addr |
| op = getBranchTargetOpValue(MI, 0, Fixups, STI); |
| op &= UINT64_C(67108863); |
| Value |= op; |
| break; |
| } |
| case AArch64::Bcc: { |
| // op: cond |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(15); |
| Value |= op; |
| // op: target |
| op = getCondBranchTargetOpValue(MI, 1, Fixups, STI); |
| op &= UINT64_C(524287); |
| op <<= 5; |
| Value |= op; |
| break; |
| } |
| case AArch64::CPYi64: { |
| // op: dst |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: src |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: idx |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(1); |
| op <<= 20; |
| Value |= op; |
| break; |
| } |
| case AArch64::CPYi8: { |
| // op: dst |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: src |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: idx |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(15); |
| op <<= 17; |
| Value |= op; |
| break; |
| } |
| case AArch64::CPYi32: { |
| // op: dst |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: src |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: idx |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(3); |
| op <<= 19; |
| Value |= op; |
| break; |
| } |
| case AArch64::CPYi16: { |
| // op: dst |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: src |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: idx |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(7); |
| op <<= 18; |
| Value |= op; |
| break; |
| } |
| case AArch64::ADDSWrs: |
| case AArch64::ADDSXrs: |
| case AArch64::ADDWrs: |
| case AArch64::ADDXrs: |
| case AArch64::ANDSWrs: |
| case AArch64::ANDSXrs: |
| case AArch64::ANDWrs: |
| case AArch64::ANDXrs: |
| case AArch64::BICSWrs: |
| case AArch64::BICSXrs: |
| case AArch64::BICWrs: |
| case AArch64::BICXrs: |
| case AArch64::EONWrs: |
| case AArch64::EONXrs: |
| case AArch64::EORWrs: |
| case AArch64::EORXrs: |
| case AArch64::ORNWrs: |
| case AArch64::ORNXrs: |
| case AArch64::ORRWrs: |
| case AArch64::ORRXrs: |
| case AArch64::SUBSWrs: |
| case AArch64::SUBSXrs: |
| case AArch64::SUBWrs: |
| case AArch64::SUBXrs: { |
| // op: dst |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| // op: src1 |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: src2 |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 16; |
| Value |= op; |
| // op: shift |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| Value |= (op & UINT64_C(192)) << 16; |
| Value |= (op & UINT64_C(63)) << 10; |
| break; |
| } |
| case AArch64::HINT: { |
| // op: imm |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(127); |
| op <<= 5; |
| Value |= op; |
| break; |
| } |
| case AArch64::UDF: { |
| // op: imm |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(65535); |
| Value |= op; |
| break; |
| } |
| case AArch64::BRK: |
| case AArch64::DCPS1: |
| case AArch64::DCPS2: |
| case AArch64::DCPS3: |
| case AArch64::HLT: |
| case AArch64::HVC: |
| case AArch64::SMC: |
| case AArch64::SVC: |
| case AArch64::TCANCEL: { |
| // op: imm |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(65535); |
| op <<= 5; |
| Value |= op; |
| break; |
| } |
| case AArch64::LDRAAindexed: |
| case AArch64::LDRABindexed: { |
| // op: offset |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| Value |= (op & UINT64_C(512)) << 13; |
| Value |= (op & UINT64_C(511)) << 12; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: Rt |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| break; |
| } |
| case AArch64::LDRAAwriteback: |
| case AArch64::LDRABwriteback: { |
| // op: offset |
| op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
| Value |= (op & UINT64_C(512)) << 13; |
| Value |= (op & UINT64_C(511)) << 12; |
| // op: Rn |
| op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
| op &= UINT64_C(31); |
| op <<= 5; |
| Value |= op; |
| // op: Rt |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(31); |
| Value |= op; |
| break; |
| } |
| case AArch64::MSRpstateImm1: { |
| // op: pstatefield |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| Value |= (op & UINT64_C(56)) << 13; |
| Value |= (op & UINT64_C(7)) << 5; |
| // op: imm |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(1); |
| op <<= 8; |
| Value |= op; |
| break; |
| } |
| case AArch64::MSRpstateImm4: { |
| // op: pstatefield |
| op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
| Value |= (op & UINT64_C(56)) << 13; |
| Value |= (op & UINT64_C(7)) << 5; |
| // op: imm |
| op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
| op &= UINT64_C(15); |
| op <<= 8; |
| Value |= op; |
| break; |
| } |
| default: |
| std::string msg; |
| raw_string_ostream Msg(msg); |
| Msg << "Not supported instr: " << MI; |
| report_fatal_error(Msg.str()); |
| } |
| return Value; |
| } |
| |
| #ifdef ENABLE_INSTR_PREDICATE_VERIFIER |
| #undef ENABLE_INSTR_PREDICATE_VERIFIER |
| #include <sstream> |
| |
| // Bits for subtarget features that participate in instruction matching. |
| enum SubtargetFeatureBits : uint8_t { |
| Feature_HasV8_1aBit = 53, |
| Feature_HasV8_2aBit = 54, |
| Feature_HasV8_3aBit = 55, |
| Feature_HasV8_4aBit = 56, |
| Feature_HasV8_5aBit = 57, |
| Feature_HasVHBit = 58, |
| Feature_HasLORBit = 20, |
| Feature_HasPABit = 26, |
| Feature_HasJSBit = 19, |
| Feature_HasCCIDXBit = 5, |
| Feature_HasComplxNumBit = 8, |
| Feature_HasNVBit = 25, |
| Feature_HasRASv8_4Bit = 33, |
| Feature_HasMPAMBit = 22, |
| Feature_HasDITBit = 10, |
| Feature_HasTRACEV8_4Bit = 51, |
| Feature_HasAMBit = 1, |
| Feature_HasSEL2Bit = 38, |
| Feature_HasPMUBit = 29, |
| Feature_HasTLB_RMIBit = 49, |
| Feature_HasFMIBit = 13, |
| Feature_HasRCPC_IMMOBit = 35, |
| Feature_HasFPARMv8Bit = 15, |
| Feature_HasNEONBit = 24, |
| Feature_HasCryptoBit = 9, |
| Feature_HasSM4Bit = 41, |
| Feature_HasSHA3Bit = 40, |
| Feature_HasSHA2Bit = 39, |
| Feature_HasAESBit = 0, |
| Feature_HasDotProdBit = 11, |
| Feature_HasCRCBit = 7, |
| Feature_HasLSEBit = 21, |
| Feature_HasRASBit = 32, |
| Feature_HasRDMBit = 36, |
| Feature_HasFullFP16Bit = 17, |
| Feature_HasFP16FMLBit = 14, |
| Feature_HasSPEBit = 42, |
| Feature_HasFuseAESBit = 18, |
| Feature_HasSVEBit = 43, |
| Feature_HasSVE2Bit = 44, |
| Feature_HasSVE2AESBit = 45, |
| Feature_HasSVE2SM4Bit = 48, |
| Feature_HasSVE2SHA3Bit = 47, |
| Feature_HasSVE2BitPermBit = 46, |
| Feature_HasRCPCBit = 34, |
| Feature_HasAltNZCVBit = 2, |
| Feature_HasFRInt3264Bit = 16, |
| Feature_HasSBBit = 37, |
| Feature_HasPredResBit = 30, |
| Feature_HasCCDPBit = 4, |
| Feature_HasBTIBit = 3, |
| Feature_HasMTEBit = 23, |
| Feature_HasTMEBit = 50, |
| Feature_HasETEBit = 12, |
| Feature_HasTRBEBit = 52, |
| Feature_UseNegativeImmediatesBit = 59, |
| Feature_HasCCPPBit = 6, |
| Feature_HasPANBit = 27, |
| Feature_HasPsUAOBit = 31, |
| Feature_HasPAN_RWVBit = 28, |
| }; |
| |
| #ifndef NDEBUG |
| static const char *SubtargetFeatureNames[] = { |
| "Feature_HasAES", |
| "Feature_HasAM", |
| "Feature_HasAltNZCV", |
| "Feature_HasBTI", |
| "Feature_HasCCDP", |
| "Feature_HasCCIDX", |
| "Feature_HasCCPP", |
| "Feature_HasCRC", |
| "Feature_HasComplxNum", |
| "Feature_HasCrypto", |
| "Feature_HasDIT", |
| "Feature_HasDotProd", |
| "Feature_HasETE", |
| "Feature_HasFMI", |
| "Feature_HasFP16FML", |
| "Feature_HasFPARMv8", |
| "Feature_HasFRInt3264", |
| "Feature_HasFullFP16", |
| "Feature_HasFuseAES", |
| "Feature_HasJS", |
| "Feature_HasLOR", |
| "Feature_HasLSE", |
| "Feature_HasMPAM", |
| "Feature_HasMTE", |
| "Feature_HasNEON", |
| "Feature_HasNV", |
| "Feature_HasPA", |
| "Feature_HasPAN", |
| "Feature_HasPAN_RWV", |
| "Feature_HasPMU", |
| "Feature_HasPredRes", |
| "Feature_HasPsUAO", |
| "Feature_HasRAS", |
| "Feature_HasRASv8_4", |
| "Feature_HasRCPC", |
| "Feature_HasRCPC_IMMO", |
| "Feature_HasRDM", |
| "Feature_HasSB", |
| "Feature_HasSEL2", |
| "Feature_HasSHA2", |
| "Feature_HasSHA3", |
| "Feature_HasSM4", |
| "Feature_HasSPE", |
| "Feature_HasSVE", |
| "Feature_HasSVE2", |
| "Feature_HasSVE2AES", |
| "Feature_HasSVE2BitPerm", |
| "Feature_HasSVE2SHA3", |
| "Feature_HasSVE2SM4", |
| "Feature_HasTLB_RMI", |
| "Feature_HasTME", |
| "Feature_HasTRACEV8_4", |
| "Feature_HasTRBE", |
| "Feature_HasV8_1a", |
| "Feature_HasV8_2a", |
| "Feature_HasV8_3a", |
| "Feature_HasV8_4a", |
| "Feature_HasV8_5a", |
| "Feature_HasVH", |
| "Feature_UseNegativeImmediates", |
| nullptr |
| }; |
| |
| #endif // NDEBUG |
| FeatureBitset AArch64MCCodeEmitter:: |
| computeAvailableFeatures(const FeatureBitset& FB) const { |
| FeatureBitset Features; |
| if ((FB[AArch64::HasV8_1aOps])) |
| Features.set(Feature_HasV8_1aBit); |
| if ((FB[AArch64::HasV8_2aOps])) |
| Features.set(Feature_HasV8_2aBit); |
| if ((FB[AArch64::HasV8_3aOps])) |
| Features.set(Feature_HasV8_3aBit); |
| if ((FB[AArch64::HasV8_4aOps])) |
| Features.set(Feature_HasV8_4aBit); |
| if ((FB[AArch64::HasV8_5aOps])) |
| Features.set(Feature_HasV8_5aBit); |
| if ((FB[AArch64::FeatureVH])) |
| Features.set(Feature_HasVHBit); |
| if ((FB[AArch64::FeatureLOR])) |
| Features.set(Feature_HasLORBit); |
| if ((FB[AArch64::FeaturePA])) |
| Features.set(Feature_HasPABit); |
| if ((FB[AArch64::FeatureJS])) |
| Features.set(Feature_HasJSBit); |
| if ((FB[AArch64::FeatureCCIDX])) |
| Features.set(Feature_HasCCIDXBit); |
| if ((FB[AArch64::FeatureComplxNum])) |
| Features.set(Feature_HasComplxNumBit); |
| if ((FB[AArch64::FeatureNV])) |
| Features.set(Feature_HasNVBit); |
| if ((FB[AArch64::FeatureRASv8_4])) |
| Features.set(Feature_HasRASv8_4Bit); |
| if ((FB[AArch64::FeatureMPAM])) |
| Features.set(Feature_HasMPAMBit); |
| if ((FB[AArch64::FeatureDIT])) |
| Features.set(Feature_HasDITBit); |
| if ((FB[AArch64::FeatureTRACEV8_4])) |
| Features.set(Feature_HasTRACEV8_4Bit); |
| if ((FB[AArch64::FeatureAM])) |
| Features.set(Feature_HasAMBit); |
| if ((FB[AArch64::FeatureSEL2])) |
| Features.set(Feature_HasSEL2Bit); |
| if ((FB[AArch64::FeaturePMU])) |
| Features.set(Feature_HasPMUBit); |
| if ((FB[AArch64::FeatureTLB_RMI])) |
| Features.set(Feature_HasTLB_RMIBit); |
| if ((FB[AArch64::FeatureFMI])) |
| Features.set(Feature_HasFMIBit); |
| if ((FB[AArch64::FeatureRCPC_IMMO])) |
| Features.set(Feature_HasRCPC_IMMOBit); |
| if ((FB[AArch64::FeatureFPARMv8])) |
| Features.set(Feature_HasFPARMv8Bit); |
| if ((FB[AArch64::FeatureNEON])) |
| Features.set(Feature_HasNEONBit); |
| if ((FB[AArch64::FeatureCrypto])) |
| Features.set(Feature_HasCryptoBit); |
| if ((FB[AArch64::FeatureSM4])) |
| Features.set(Feature_HasSM4Bit); |
| if ((FB[AArch64::FeatureSHA3])) |
| Features.set(Feature_HasSHA3Bit); |
| if ((FB[AArch64::FeatureSHA2])) |
| Features.set(Feature_HasSHA2Bit); |
| if ((FB[AArch64::FeatureAES])) |
| Features.set(Feature_HasAESBit); |
| if ((FB[AArch64::FeatureDotProd])) |
| Features.set(Feature_HasDotProdBit); |
| if ((FB[AArch64::FeatureCRC])) |
| Features.set(Feature_HasCRCBit); |
| if ((FB[AArch64::FeatureLSE])) |
| Features.set(Feature_HasLSEBit); |
| if ((FB[AArch64::FeatureRAS])) |
| Features.set(Feature_HasRASBit); |
| if ((FB[AArch64::FeatureRDM])) |
| Features.set(Feature_HasRDMBit); |
| if ((FB[AArch64::FeatureFullFP16])) |
| Features.set(Feature_HasFullFP16Bit); |
| if ((FB[AArch64::FeatureFP16FML])) |
| Features.set(Feature_HasFP16FMLBit); |
| if ((FB[AArch64::FeatureSPE])) |
| Features.set(Feature_HasSPEBit); |
| if ((FB[AArch64::FeatureFuseAES])) |
| Features.set(Feature_HasFuseAESBit); |
| if ((FB[AArch64::FeatureSVE])) |
| Features.set(Feature_HasSVEBit); |
| if ((FB[AArch64::FeatureSVE2])) |
| Features.set(Feature_HasSVE2Bit); |
| if ((FB[AArch64::FeatureSVE2AES])) |
| Features.set(Feature_HasSVE2AESBit); |
| if ((FB[AArch64::FeatureSVE2SM4])) |
| Features.set(Feature_HasSVE2SM4Bit); |
| if ((FB[AArch64::FeatureSVE2SHA3])) |
| Features.set(Feature_HasSVE2SHA3Bit); |
| if ((FB[AArch64::FeatureSVE2BitPerm])) |
| Features.set(Feature_HasSVE2BitPermBit); |
| if ((FB[AArch64::FeatureRCPC])) |
| Features.set(Feature_HasRCPCBit); |
| if ((FB[AArch64::FeatureAltFPCmp])) |
| Features.set(Feature_HasAltNZCVBit); |
| if ((FB[AArch64::FeatureFRInt3264])) |
| Features.set(Feature_HasFRInt3264Bit); |
| if ((FB[AArch64::FeatureSB])) |
| Features.set(Feature_HasSBBit); |
| if ((FB[AArch64::FeaturePredRes])) |
| Features.set(Feature_HasPredResBit); |
| if ((FB[AArch64::FeatureCacheDeepPersist])) |
| Features.set(Feature_HasCCDPBit); |
| if ((FB[AArch64::FeatureBranchTargetId])) |
| Features.set(Feature_HasBTIBit); |
| if ((FB[AArch64::FeatureMTE])) |
| Features.set(Feature_HasMTEBit); |
| if ((FB[AArch64::FeatureTME])) |
| Features.set(Feature_HasTMEBit); |
| if ((FB[AArch64::FeatureETE])) |
| Features.set(Feature_HasETEBit); |
| if ((FB[AArch64::FeatureTRBE])) |
| Features.set(Feature_HasTRBEBit); |
| if ((!FB[AArch64::FeatureNoNegativeImmediates])) |
| Features.set(Feature_UseNegativeImmediatesBit); |
| if ((FB[AArch64::FeatureCCPP])) |
| Features.set(Feature_HasCCPPBit); |
| if ((FB[AArch64::FeaturePAN])) |
| Features.set(Feature_HasPANBit); |
| if ((FB[AArch64::FeaturePsUAO])) |
| Features.set(Feature_HasPsUAOBit); |
| if ((FB[AArch64::FeaturePAN_RWV])) |
| Features.set(Feature_HasPAN_RWVBit); |
| return Features; |
| } |
| |
| #ifndef NDEBUG |
| // Feature bitsets. |
| enum : uint8_t { |
| CEFBS_None, |
| CEFBS_HasAES, |
| CEFBS_HasAltNZCV, |
| CEFBS_HasCRC, |
| CEFBS_HasDotProd, |
| CEFBS_HasFMI, |
| CEFBS_HasFPARMv8, |
| CEFBS_HasFRInt3264, |
| CEFBS_HasFullFP16, |
| CEFBS_HasLOR, |
| CEFBS_HasLSE, |
| CEFBS_HasMTE, |
| CEFBS_HasNEON, |
| CEFBS_HasPA, |
| CEFBS_HasRCPC, |
| CEFBS_HasRCPC_IMMO, |
| CEFBS_HasRDM, |
| CEFBS_HasSB, |
| CEFBS_HasSHA2, |
| CEFBS_HasSHA3, |
| CEFBS_HasSM4, |
| CEFBS_HasSVE, |
| CEFBS_HasSVE2, |
| CEFBS_HasSVE2AES, |
| CEFBS_HasSVE2BitPerm, |
| CEFBS_HasSVE2SHA3, |
| CEFBS_HasSVE2SM4, |
| CEFBS_HasTME, |
| CEFBS_HasTRACEV8_4, |
| CEFBS_HasComplxNum_HasNEON, |
| CEFBS_HasJS_HasFPARMv8, |
| CEFBS_HasNEON_HasFP16FML, |
| CEFBS_HasNEON_HasFullFP16, |
| CEFBS_HasNEON_HasRDM, |
| CEFBS_HasComplxNum_HasNEON_HasFullFP16, |
| }; |
| |
| static constexpr FeatureBitset FeatureBitsets[] = { |
| {}, // CEFBS_None |
| {Feature_HasAESBit, }, |
| {Feature_HasAltNZCVBit, }, |
| {Feature_HasCRCBit, }, |
| {Feature_HasDotProdBit, }, |
| {Feature_HasFMIBit, }, |
| {Feature_HasFPARMv8Bit, }, |
| {Feature_HasFRInt3264Bit, }, |
| {Feature_HasFullFP16Bit, }, |
| {Feature_HasLORBit, }, |
| {Feature_HasLSEBit, }, |
| {Feature_HasMTEBit, }, |
| {Feature_HasNEONBit, }, |
| {Feature_HasPABit, }, |
| {Feature_HasRCPCBit, }, |
| {Feature_HasRCPC_IMMOBit, }, |
| {Feature_HasRDMBit, }, |
| {Feature_HasSBBit, }, |
| {Feature_HasSHA2Bit, }, |
| {Feature_HasSHA3Bit, }, |
| {Feature_HasSM4Bit, }, |
| {Feature_HasSVEBit, }, |
| {Feature_HasSVE2Bit, }, |
| {Feature_HasSVE2AESBit, }, |
| {Feature_HasSVE2BitPermBit, }, |
| {Feature_HasSVE2SHA3Bit, }, |
| {Feature_HasSVE2SM4Bit, }, |
| {Feature_HasTMEBit, }, |
| {Feature_HasTRACEV8_4Bit, }, |
| {Feature_HasComplxNumBit, Feature_HasNEONBit, }, |
| {Feature_HasJSBit, Feature_HasFPARMv8Bit, }, |
| {Feature_HasNEONBit, Feature_HasFP16FMLBit, }, |
| {Feature_HasNEONBit, Feature_HasFullFP16Bit, }, |
| {Feature_HasNEONBit, Feature_HasRDMBit, }, |
| {Feature_HasComplxNumBit, Feature_HasNEONBit, Feature_HasFullFP16Bit, }, |
| }; |
| #endif // NDEBUG |
| |
| void AArch64MCCodeEmitter::verifyInstructionPredicates( |
| const MCInst &Inst, const FeatureBitset &AvailableFeatures) const { |
| #ifndef NDEBUG |
| static uint8_t RequiredFeaturesRefs[] = { |
| CEFBS_None, // PHI = 0 |
| CEFBS_None, // INLINEASM = 1 |
| CEFBS_None, // INLINEASM_BR = 2 |
| CEFBS_None, // CFI_INSTRUCTION = 3 |
| CEFBS_None, // EH_LABEL = 4 |
| CEFBS_None, // GC_LABEL = 5 |
| CEFBS_None, // ANNOTATION_LABEL = 6 |
| CEFBS_None, // KILL = 7 |
| CEFBS_None, // EXTRACT_SUBREG = 8 |
| CEFBS_None, // INSERT_SUBREG = 9 |
| CEFBS_None, // IMPLICIT_DEF = 10 |
| CEFBS_None, // SUBREG_TO_REG = 11 |
| CEFBS_None, // COPY_TO_REGCLASS = 12 |
| CEFBS_None, // DBG_VALUE = 13 |
| CEFBS_None, // DBG_LABEL = 14 |
| CEFBS_None, // REG_SEQUENCE = 15 |
| CEFBS_None, // COPY = 16 |
| CEFBS_None, // BUNDLE = 17 |
| CEFBS_None, // LIFETIME_START = 18 |
| CEFBS_None, // LIFETIME_END = 19 |
| CEFBS_None, // STACKMAP = 20 |
| CEFBS_None, // FENTRY_CALL = 21 |
| CEFBS_None, // PATCHPOINT = 22 |
| CEFBS_None, // LOAD_STACK_GUARD = 23 |
| CEFBS_None, // STATEPOINT = 24 |
| CEFBS_None, // LOCAL_ESCAPE = 25 |
| CEFBS_None, // FAULTING_OP = 26 |
| CEFBS_None, // PATCHABLE_OP = 27 |
| CEFBS_None, // PATCHABLE_FUNCTION_ENTER = 28 |
| CEFBS_None, // PATCHABLE_RET = 29 |
| CEFBS_None, // PATCHABLE_FUNCTION_EXIT = 30 |
| CEFBS_None, // PATCHABLE_TAIL_CALL = 31 |
| CEFBS_None, // PATCHABLE_EVENT_CALL = 32 |
| CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL = 33 |
| CEFBS_None, // ICALL_BRANCH_FUNNEL = 34 |
| CEFBS_None, // G_ADD = 35 |
| CEFBS_None, // G_SUB = 36 |
| CEFBS_None, // G_MUL = 37 |
| CEFBS_None, // G_SDIV = 38 |
| CEFBS_None, // G_UDIV = 39 |
| CEFBS_None, // G_SREM = 40 |
| CEFBS_None, // G_UREM = 41 |
| CEFBS_None, // G_AND = 42 |
| CEFBS_None, // G_OR = 43 |
| CEFBS_None, // G_XOR = 44 |
| CEFBS_None, // G_IMPLICIT_DEF = 45 |
| CEFBS_None, // G_PHI = 46 |
| CEFBS_None, // G_FRAME_INDEX = 47 |
| CEFBS_None, // G_GLOBAL_VALUE = 48 |
| CEFBS_None, // G_EXTRACT = 49 |
| CEFBS_None, // G_UNMERGE_VALUES = 50 |
| CEFBS_None, // G_INSERT = 51 |
| CEFBS_None, // G_MERGE_VALUES = 52 |
| CEFBS_None, // G_BUILD_VECTOR = 53 |
| CEFBS_None, // G_BUILD_VECTOR_TRUNC = 54 |
| CEFBS_None, // G_CONCAT_VECTORS = 55 |
| CEFBS_None, // G_PTRTOINT = 56 |
| CEFBS_None, // G_INTTOPTR = 57 |
| CEFBS_None, // G_BITCAST = 58 |
| CEFBS_None, // G_INTRINSIC_TRUNC = 59 |
| CEFBS_None, // G_INTRINSIC_ROUND = 60 |
| CEFBS_None, // G_READCYCLECOUNTER = 61 |
| CEFBS_None, // G_LOAD = 62 |
| CEFBS_None, // G_SEXTLOAD = 63 |
| CEFBS_None, // G_ZEXTLOAD = 64 |
| CEFBS_None, // G_INDEXED_LOAD = 65 |
| CEFBS_None, // G_INDEXED_SEXTLOAD = 66 |
| CEFBS_None, // G_INDEXED_ZEXTLOAD = 67 |
| CEFBS_None, // G_STORE = 68 |
| CEFBS_None, // G_INDEXED_STORE = 69 |
| CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS = 70 |
| CEFBS_None, // G_ATOMIC_CMPXCHG = 71 |
| CEFBS_None, // G_ATOMICRMW_XCHG = 72 |
| CEFBS_None, // G_ATOMICRMW_ADD = 73 |
| CEFBS_None, // G_ATOMICRMW_SUB = 74 |
| CEFBS_None, // G_ATOMICRMW_AND = 75 |
| CEFBS_None, // G_ATOMICRMW_NAND = 76 |
| CEFBS_None, // G_ATOMICRMW_OR = 77 |
| CEFBS_None, // G_ATOMICRMW_XOR = 78 |
| CEFBS_None, // G_ATOMICRMW_MAX = 79 |
| CEFBS_None, // G_ATOMICRMW_MIN = 80 |
| CEFBS_None, // G_ATOMICRMW_UMAX = 81 |
| CEFBS_None, // G_ATOMICRMW_UMIN = 82 |
| CEFBS_None, // G_ATOMICRMW_FADD = 83 |
| CEFBS_None, // G_ATOMICRMW_FSUB = 84 |
| CEFBS_None, // G_FENCE = 85 |
| CEFBS_None, // G_BRCOND = 86 |
| CEFBS_None, // G_BRINDIRECT = 87 |
| CEFBS_None, // G_INTRINSIC = 88 |
| CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS = 89 |
| CEFBS_None, // G_ANYEXT = 90 |
| CEFBS_None, // G_TRUNC = 91 |
| CEFBS_None, // G_CONSTANT = 92 |
| CEFBS_None, // G_FCONSTANT = 93 |
| CEFBS_None, // G_VASTART = 94 |
| CEFBS_None, // G_VAARG = 95 |
| CEFBS_None, // G_SEXT = 96 |
| CEFBS_None, // G_SEXT_INREG = 97 |
| CEFBS_None, // G_ZEXT = 98 |
| CEFBS_None, // G_SHL = 99 |
| CEFBS_None, // G_LSHR = 100 |
| CEFBS_None, // G_ASHR = 101 |
| CEFBS_None, // G_ICMP = 102 |
| CEFBS_None, // G_FCMP = 103 |
| CEFBS_None, // G_SELECT = 104 |
| CEFBS_None, // G_UADDO = 105 |
| CEFBS_None, // G_UADDE = 106 |
| CEFBS_None, // G_USUBO = 107 |
| CEFBS_None, // G_USUBE = 108 |
| CEFBS_None, // G_SADDO = 109 |
| CEFBS_None, // G_SADDE = 110 |
| CEFBS_None, // G_SSUBO = 111 |
| CEFBS_None, // G_SSUBE = 112 |
| CEFBS_None, // G_UMULO = 113 |
| CEFBS_None, // G_SMULO = 114 |
| CEFBS_None, // G_UMULH = 115 |
| CEFBS_None, // G_SMULH = 116 |
| CEFBS_None, // G_FADD = 117 |
| CEFBS_None, // G_FSUB = 118 |
| CEFBS_None, // G_FMUL = 119 |
| CEFBS_None, // G_FMA = 120 |
| CEFBS_None, // G_FMAD = 121 |
| CEFBS_None, // G_FDIV = 122 |
| CEFBS_None, // G_FREM = 123 |
| CEFBS_None, // G_FPOW = 124 |
| CEFBS_None, // G_FEXP = 125 |
| CEFBS_None, // G_FEXP2 = 126 |
| CEFBS_None, // G_FLOG = 127 |
| CEFBS_None, // G_FLOG2 = 128 |
| CEFBS_None, // G_FLOG10 = 129 |
| CEFBS_None, // G_FNEG = 130 |
| CEFBS_None, // G_FPEXT = 131 |
| CEFBS_None, // G_FPTRUNC = 132 |
| CEFBS_None, // G_FPTOSI = 133 |
| CEFBS_None, // G_FPTOUI = 134 |
| CEFBS_None, // G_SITOFP = 135 |
| CEFBS_None, // G_UITOFP = 136 |
| CEFBS_None, // G_FABS = 137 |
| CEFBS_None, // G_FCOPYSIGN = 138 |
| CEFBS_None, // G_FCANONICALIZE = 139 |
| CEFBS_None, // G_FMINNUM = 140 |
| CEFBS_None, // G_FMAXNUM = 141 |
| CEFBS_None, // G_FMINNUM_IEEE = 142 |
| CEFBS_None, // G_FMAXNUM_IEEE = 143 |
| CEFBS_None, // G_FMINIMUM = 144 |
| CEFBS_None, // G_FMAXIMUM = 145 |
| CEFBS_None, // G_PTR_ADD = 146 |
| CEFBS_None, // G_PTR_MASK = 147 |
| CEFBS_None, // G_SMIN = 148 |
| CEFBS_None, // G_SMAX = 149 |
| CEFBS_None, // G_UMIN = 150 |
| CEFBS_None, // G_UMAX = 151 |
| CEFBS_None, // G_BR = 152 |
| CEFBS_None, // G_BRJT = 153 |
| CEFBS_None, // G_INSERT_VECTOR_ELT = 154 |
| CEFBS_None, // G_EXTRACT_VECTOR_ELT = 155 |
| CEFBS_None, // G_SHUFFLE_VECTOR = 156 |
| CEFBS_None, // G_CTTZ = 157 |
| CEFBS_None, // G_CTTZ_ZERO_UNDEF = 158 |
| CEFBS_None, // G_CTLZ = 159 |
| CEFBS_None, // G_CTLZ_ZERO_UNDEF = 160 |
| CEFBS_None, // G_CTPOP = 161 |
| CEFBS_None, // G_BSWAP = 162 |
| CEFBS_None, // G_BITREVERSE = 163 |
| CEFBS_None, // G_FCEIL = 164 |
| CEFBS_None, // G_FCOS = 165 |
| CEFBS_None, // G_FSIN = 166 |
| CEFBS_None, // G_FSQRT = 167 |
| CEFBS_None, // G_FFLOOR = 168 |
| CEFBS_None, // G_FRINT = 169 |
| CEFBS_None, // G_FNEARBYINT = 170 |
| CEFBS_None, // G_ADDRSPACE_CAST = 171 |
| CEFBS_None, // G_BLOCK_ADDR = 172 |
| CEFBS_None, // G_JUMP_TABLE = 173 |
| CEFBS_None, // G_DYN_STACKALLOC = 174 |
| CEFBS_None, // G_READ_REGISTER = 175 |
| CEFBS_None, // G_WRITE_REGISTER = 176 |
| CEFBS_None, // CATCHRET = 177 |
| CEFBS_None, // CLEANUPRET = 178 |
| CEFBS_None, // SEH_AddFP = 179 |
| CEFBS_None, // SEH_EpilogEnd = 180 |
| CEFBS_None, // SEH_EpilogStart = 181 |
| CEFBS_None, // SEH_Nop = 182 |
| CEFBS_None, // SEH_PrologEnd = 183 |
| CEFBS_None, // SEH_SaveFPLR = 184 |
| CEFBS_None, // SEH_SaveFPLR_X = 185 |
| CEFBS_None, // SEH_SaveFReg = 186 |
| CEFBS_None, // SEH_SaveFRegP = 187 |
| CEFBS_None, // SEH_SaveFRegP_X = 188 |
| CEFBS_None, // SEH_SaveFReg_X = 189 |
| CEFBS_None, // SEH_SaveReg = 190 |
| CEFBS_None, // SEH_SaveRegP = 191 |
| CEFBS_None, // SEH_SaveRegP_X = 192 |
| CEFBS_None, // SEH_SaveReg_X = 193 |
| CEFBS_None, // SEH_SetFP = 194 |
| CEFBS_None, // SEH_StackAlloc = 195 |
| CEFBS_HasSVE, // ABS_ZPmZ_B = 196 |
| CEFBS_HasSVE, // ABS_ZPmZ_D = 197 |
| CEFBS_HasSVE, // ABS_ZPmZ_H = 198 |
| CEFBS_HasSVE, // ABS_ZPmZ_S = 199 |
| CEFBS_HasNEON, // ABSv16i8 = 200 |
| CEFBS_HasNEON, // ABSv1i64 = 201 |
| CEFBS_HasNEON, // ABSv2i32 = 202 |
| CEFBS_HasNEON, // ABSv2i64 = 203 |
| CEFBS_HasNEON, // ABSv4i16 = 204 |
| CEFBS_HasNEON, // ABSv4i32 = 205 |
| CEFBS_HasNEON, // ABSv8i16 = 206 |
| CEFBS_HasNEON, // ABSv8i8 = 207 |
| CEFBS_HasSVE2, // ADCLB_ZZZ_D = 208 |
| CEFBS_HasSVE2, // ADCLB_ZZZ_S = 209 |
| CEFBS_HasSVE2, // ADCLT_ZZZ_D = 210 |
| CEFBS_HasSVE2, // ADCLT_ZZZ_S = 211 |
| CEFBS_None, // ADCSWr = 212 |
| CEFBS_None, // ADCSXr = 213 |
| CEFBS_None, // ADCWr = 214 |
| CEFBS_None, // ADCXr = 215 |
| CEFBS_HasMTE, // ADDG = 216 |
| CEFBS_HasSVE2, // ADDHNB_ZZZ_B = 217 |
| CEFBS_HasSVE2, // ADDHNB_ZZZ_H = 218 |
| CEFBS_HasSVE2, // ADDHNB_ZZZ_S = 219 |
| CEFBS_HasSVE2, // ADDHNT_ZZZ_B = 220 |
| CEFBS_HasSVE2, // ADDHNT_ZZZ_H = 221 |
| CEFBS_HasSVE2, // ADDHNT_ZZZ_S = 222 |
| CEFBS_HasNEON, // ADDHNv2i64_v2i32 = 223 |
| CEFBS_HasNEON, // ADDHNv2i64_v4i32 = 224 |
| CEFBS_HasNEON, // ADDHNv4i32_v4i16 = 225 |
| CEFBS_HasNEON, // ADDHNv4i32_v8i16 = 226 |
| CEFBS_HasNEON, // ADDHNv8i16_v16i8 = 227 |
| CEFBS_HasNEON, // ADDHNv8i16_v8i8 = 228 |
| CEFBS_HasSVE, // ADDPL_XXI = 229 |
| CEFBS_HasSVE2, // ADDP_ZPmZ_B = 230 |
| CEFBS_HasSVE2, // ADDP_ZPmZ_D = 231 |
| CEFBS_HasSVE2, // ADDP_ZPmZ_H = 232 |
| CEFBS_HasSVE2, // ADDP_ZPmZ_S = 233 |
| CEFBS_HasNEON, // ADDPv16i8 = 234 |
| CEFBS_HasNEON, // ADDPv2i32 = 235 |
| CEFBS_HasNEON, // ADDPv2i64 = 236 |
| CEFBS_HasNEON, // ADDPv2i64p = 237 |
| CEFBS_HasNEON, // ADDPv4i16 = 238 |
| CEFBS_HasNEON, // ADDPv4i32 = 239 |
| CEFBS_HasNEON, // ADDPv8i16 = 240 |
| CEFBS_HasNEON, // ADDPv8i8 = 241 |
| CEFBS_None, // ADDSWri = 242 |
| CEFBS_None, // ADDSWrr = 243 |
| CEFBS_None, // ADDSWrs = 244 |
| CEFBS_None, // ADDSWrx = 245 |
| CEFBS_None, // ADDSXri = 246 |
| CEFBS_None, // ADDSXrr = 247 |
| CEFBS_None, // ADDSXrs = 248 |
| CEFBS_None, // ADDSXrx = 249 |
| CEFBS_None, // ADDSXrx64 = 250 |
| CEFBS_HasSVE, // ADDVL_XXI = 251 |
| CEFBS_HasNEON, // ADDVv16i8v = 252 |
| CEFBS_HasNEON, // ADDVv4i16v = 253 |
| CEFBS_HasNEON, // ADDVv4i32v = 254 |
| CEFBS_HasNEON, // ADDVv8i16v = 255 |
| CEFBS_HasNEON, // ADDVv8i8v = 256 |
| CEFBS_None, // ADDWri = 257 |
| CEFBS_None, // ADDWrr = 258 |
| CEFBS_None, // ADDWrs = 259 |
| CEFBS_None, // ADDWrx = 260 |
| CEFBS_None, // ADDXri = 261 |
| CEFBS_None, // ADDXrr = 262 |
| CEFBS_None, // ADDXrs = 263 |
| CEFBS_None, // ADDXrx = 264 |
| CEFBS_None, // ADDXrx64 = 265 |
| CEFBS_HasSVE, // ADD_ZI_B = 266 |
| CEFBS_HasSVE, // ADD_ZI_D = 267 |
| CEFBS_HasSVE, // ADD_ZI_H = 268 |
| CEFBS_HasSVE, // ADD_ZI_S = 269 |
| CEFBS_HasSVE, // ADD_ZPmZ_B = 270 |
| CEFBS_HasSVE, // ADD_ZPmZ_D = 271 |
| CEFBS_HasSVE, // ADD_ZPmZ_H = 272 |
| CEFBS_HasSVE, // ADD_ZPmZ_S = 273 |
| CEFBS_HasSVE, // ADD_ZZZ_B = 274 |
| CEFBS_HasSVE, // ADD_ZZZ_D = 275 |
| CEFBS_HasSVE, // ADD_ZZZ_H = 276 |
| CEFBS_HasSVE, // ADD_ZZZ_S = 277 |
| CEFBS_None, // ADDlowTLS = 278 |
| CEFBS_HasNEON, // ADDv16i8 = 279 |
| CEFBS_HasNEON, // ADDv1i64 = 280 |
| CEFBS_HasNEON, // ADDv2i32 = 281 |
| CEFBS_HasNEON, // ADDv2i64 = 282 |
| CEFBS_HasNEON, // ADDv4i16 = 283 |
| CEFBS_HasNEON, // ADDv4i32 = 284 |
| CEFBS_HasNEON, // ADDv8i16 = 285 |
| CEFBS_HasNEON, // ADDv8i8 = 286 |
| CEFBS_None, // ADJCALLSTACKDOWN = 287 |
| CEFBS_None, // ADJCALLSTACKUP = 288 |
| CEFBS_None, // ADR = 289 |
| CEFBS_None, // ADRP = 290 |
| CEFBS_HasSVE, // ADR_LSL_ZZZ_D_0 = 291 |
| CEFBS_HasSVE, // ADR_LSL_ZZZ_D_1 = 292 |
| CEFBS_HasSVE, // ADR_LSL_ZZZ_D_2 = 293 |
| CEFBS_HasSVE, // ADR_LSL_ZZZ_D_3 = 294 |
| CEFBS_HasSVE, // ADR_LSL_ZZZ_S_0 = 295 |
| CEFBS_HasSVE, // ADR_LSL_ZZZ_S_1 = 296 |
| CEFBS_HasSVE, // ADR_LSL_ZZZ_S_2 = 297 |
| CEFBS_HasSVE, // ADR_LSL_ZZZ_S_3 = 298 |
| CEFBS_HasSVE, // ADR_SXTW_ZZZ_D_0 = 299 |
| CEFBS_HasSVE, // ADR_SXTW_ZZZ_D_1 = 300 |
| CEFBS_HasSVE, // ADR_SXTW_ZZZ_D_2 = 301 |
| CEFBS_HasSVE, // ADR_SXTW_ZZZ_D_3 = 302 |
| CEFBS_HasSVE, // ADR_UXTW_ZZZ_D_0 = 303 |
| CEFBS_HasSVE, // ADR_UXTW_ZZZ_D_1 = 304 |
| CEFBS_HasSVE, // ADR_UXTW_ZZZ_D_2 = 305 |
| CEFBS_HasSVE, // ADR_UXTW_ZZZ_D_3 = 306 |
| CEFBS_HasSVE2AES, // AESD_ZZZ_B = 307 |
| CEFBS_HasAES, // AESDrr = 308 |
| CEFBS_HasSVE2AES, // AESE_ZZZ_B = 309 |
| CEFBS_HasAES, // AESErr = 310 |
| CEFBS_HasSVE2AES, // AESIMC_ZZ_B = 311 |
| CEFBS_HasAES, // AESIMCrr = 312 |
| CEFBS_None, // AESIMCrrTied = 313 |
| CEFBS_HasSVE2AES, // AESMC_ZZ_B = 314 |
| CEFBS_HasAES, // AESMCrr = 315 |
| CEFBS_None, // AESMCrrTied = 316 |
| CEFBS_None, // ANDSWri = 317 |
| CEFBS_None, // ANDSWrr = 318 |
| CEFBS_None, // ANDSWrs = 319 |
| CEFBS_None, // ANDSXri = 320 |
| CEFBS_None, // ANDSXrr = 321 |
| CEFBS_None, // ANDSXrs = 322 |
| CEFBS_HasSVE, // ANDS_PPzPP = 323 |
| CEFBS_HasSVE, // ANDV_VPZ_B = 324 |
| CEFBS_HasSVE, // ANDV_VPZ_D = 325 |
| CEFBS_HasSVE, // ANDV_VPZ_H = 326 |
| CEFBS_HasSVE, // ANDV_VPZ_S = 327 |
| CEFBS_None, // ANDWri = 328 |
| CEFBS_None, // ANDWrr = 329 |
| CEFBS_None, // ANDWrs = 330 |
| CEFBS_None, // ANDXri = 331 |
| CEFBS_None, // ANDXrr = 332 |
| CEFBS_None, // ANDXrs = 333 |
| CEFBS_HasSVE, // AND_PPzPP = 334 |
| CEFBS_HasSVE, // AND_ZI = 335 |
| CEFBS_HasSVE, // AND_ZPmZ_B = 336 |
| CEFBS_HasSVE, // AND_ZPmZ_D = 337 |
| CEFBS_HasSVE, // AND_ZPmZ_H = 338 |
| CEFBS_HasSVE, // AND_ZPmZ_S = 339 |
| CEFBS_HasSVE, // AND_ZZZ = 340 |
| CEFBS_HasNEON, // ANDv16i8 = 341 |
| CEFBS_HasNEON, // ANDv8i8 = 342 |
| CEFBS_HasSVE, // ASRD_ZPmI_B = 343 |
| CEFBS_HasSVE, // ASRD_ZPmI_D = 344 |
| CEFBS_HasSVE, // ASRD_ZPmI_H = 345 |
| CEFBS_HasSVE, // ASRD_ZPmI_S = 346 |
| CEFBS_HasSVE, // ASRR_ZPmZ_B = 347 |
| CEFBS_HasSVE, // ASRR_ZPmZ_D = 348 |
| CEFBS_HasSVE, // ASRR_ZPmZ_H = 349 |
| CEFBS_HasSVE, // ASRR_ZPmZ_S = 350 |
| CEFBS_None, // ASRVWr = 351 |
| CEFBS_None, // ASRVXr = 352 |
| CEFBS_HasSVE, // ASR_WIDE_ZPmZ_B = 353 |
| CEFBS_HasSVE, // ASR_WIDE_ZPmZ_H = 354 |
| CEFBS_HasSVE, // ASR_WIDE_ZPmZ_S = 355 |
| CEFBS_HasSVE, // ASR_WIDE_ZZZ_B = 356 |
| CEFBS_HasSVE, // ASR_WIDE_ZZZ_H = 357 |
| CEFBS_HasSVE, // ASR_WIDE_ZZZ_S = 358 |
| CEFBS_HasSVE, // ASR_ZPmI_B = 359 |
| CEFBS_HasSVE, // ASR_ZPmI_D = 360 |
| CEFBS_HasSVE, // ASR_ZPmI_H = 361 |
| CEFBS_HasSVE, // ASR_ZPmI_S = 362 |
| CEFBS_HasSVE, // ASR_ZPmZ_B = 363 |
| CEFBS_HasSVE, // ASR_ZPmZ_D = 364 |
| CEFBS_HasSVE, // ASR_ZPmZ_H = 365 |
| CEFBS_HasSVE, // ASR_ZPmZ_S = 366 |
| CEFBS_HasSVE, // ASR_ZZI_B = 367 |
| CEFBS_HasSVE, // ASR_ZZI_D = 368 |
| CEFBS_HasSVE, // ASR_ZZI_H = 369 |
| CEFBS_HasSVE, // ASR_ZZI_S = 370 |
| CEFBS_HasPA, // AUTDA = 371 |
| CEFBS_HasPA, // AUTDB = 372 |
| CEFBS_HasPA, // AUTDZA = 373 |
| CEFBS_HasPA, // AUTDZB = 374 |
| CEFBS_HasPA, // AUTIA = 375 |
| CEFBS_None, // AUTIA1716 = 376 |
| CEFBS_None, // AUTIASP = 377 |
| CEFBS_None, // AUTIAZ = 378 |
| CEFBS_HasPA, // AUTIB = 379 |
| CEFBS_None, // AUTIB1716 = 380 |
| CEFBS_None, // AUTIBSP = 381 |
| CEFBS_None, // AUTIBZ = 382 |
| CEFBS_HasPA, // AUTIZA = 383 |
| CEFBS_HasPA, // AUTIZB = 384 |
| CEFBS_HasAltNZCV, // AXFLAG = 385 |
| CEFBS_None, // B = 386 |
| CEFBS_HasSHA3, // BCAX = 387 |
| CEFBS_HasSVE2, // BCAX_ZZZZ_D = 388 |
| CEFBS_HasSVE2BitPerm, // BDEP_ZZZ_B = 389 |
| CEFBS_HasSVE2BitPerm, // BDEP_ZZZ_D = 390 |
| CEFBS_HasSVE2BitPerm, // BDEP_ZZZ_H = 391 |
| CEFBS_HasSVE2BitPerm, // BDEP_ZZZ_S = 392 |
| CEFBS_HasSVE2BitPerm, // BEXT_ZZZ_B = 393 |
| CEFBS_HasSVE2BitPerm, // BEXT_ZZZ_D = 394 |
| CEFBS_HasSVE2BitPerm, // BEXT_ZZZ_H = 395 |
| CEFBS_HasSVE2BitPerm, // BEXT_ZZZ_S = 396 |
| CEFBS_None, // BFMWri = 397 |
| CEFBS_None, // BFMXri = 398 |
| CEFBS_HasSVE2BitPerm, // BGRP_ZZZ_B = 399 |
| CEFBS_HasSVE2BitPerm, // BGRP_ZZZ_D = 400 |
| CEFBS_HasSVE2BitPerm, // BGRP_ZZZ_H = 401 |
| CEFBS_HasSVE2BitPerm, // BGRP_ZZZ_S = 402 |
| CEFBS_None, // BICSWrr = 403 |
| CEFBS_None, // BICSWrs = 404 |
| CEFBS_None, // BICSXrr = 405 |
| CEFBS_None, // BICSXrs = 406 |
| CEFBS_HasSVE, // BICS_PPzPP = 407 |
| CEFBS_None, // BICWrr = 408 |
| CEFBS_None, // BICWrs = 409 |
| CEFBS_None, // BICXrr = 410 |
| CEFBS_None, // BICXrs = 411 |
| CEFBS_HasSVE, // BIC_PPzPP = 412 |
| CEFBS_HasSVE, // BIC_ZPmZ_B = 413 |
| CEFBS_HasSVE, // BIC_ZPmZ_D = 414 |
| CEFBS_HasSVE, // BIC_ZPmZ_H = 415 |
| CEFBS_HasSVE, // BIC_ZPmZ_S = 416 |
| CEFBS_HasSVE, // BIC_ZZZ = 417 |
| CEFBS_HasNEON, // BICv16i8 = 418 |
| CEFBS_HasNEON, // BICv2i32 = 419 |
| CEFBS_HasNEON, // BICv4i16 = 420 |
| CEFBS_HasNEON, // BICv4i32 = 421 |
| CEFBS_HasNEON, // BICv8i16 = 422 |
| CEFBS_HasNEON, // BICv8i8 = 423 |
| CEFBS_HasNEON, // BIFv16i8 = 424 |
| CEFBS_HasNEON, // BIFv8i8 = 425 |
| CEFBS_HasNEON, // BITv16i8 = 426 |
| CEFBS_HasNEON, // BITv8i8 = 427 |
| CEFBS_None, // BL = 428 |
| CEFBS_None, // BLR = 429 |
| CEFBS_HasPA, // BLRAA = 430 |
| CEFBS_HasPA, // BLRAAZ = 431 |
| CEFBS_HasPA, // BLRAB = 432 |
| CEFBS_HasPA, // BLRABZ = 433 |
| CEFBS_None, // BR = 434 |
| CEFBS_HasPA, // BRAA = 435 |
| CEFBS_HasPA, // BRAAZ = 436 |
| CEFBS_HasPA, // BRAB = 437 |
| CEFBS_HasPA, // BRABZ = 438 |
| CEFBS_None, // BRK = 439 |
| CEFBS_HasSVE, // BRKAS_PPzP = 440 |
| CEFBS_HasSVE, // BRKA_PPmP = 441 |
| CEFBS_HasSVE, // BRKA_PPzP = 442 |
| CEFBS_HasSVE, // BRKBS_PPzP = 443 |
| CEFBS_HasSVE, // BRKB_PPmP = 444 |
| CEFBS_HasSVE, // BRKB_PPzP = 445 |
| CEFBS_HasSVE, // BRKNS_PPzP = 446 |
| CEFBS_HasSVE, // BRKN_PPzP = 447 |
| CEFBS_HasSVE, // BRKPAS_PPzPP = 448 |
| CEFBS_HasSVE, // BRKPA_PPzPP = 449 |
| CEFBS_HasSVE, // BRKPBS_PPzPP = 450 |
| CEFBS_HasSVE, // BRKPB_PPzPP = 451 |
| CEFBS_HasSVE2, // BSL1N_ZZZZ_D = 452 |
| CEFBS_HasSVE2, // BSL2N_ZZZZ_D = 453 |
| CEFBS_HasSVE2, // BSL_ZZZZ_D = 454 |
| CEFBS_HasNEON, // BSLv16i8 = 455 |
| CEFBS_HasNEON, // BSLv8i8 = 456 |
| CEFBS_None, // Bcc = 457 |
| CEFBS_HasSVE2, // CADD_ZZI_B = 458 |
| CEFBS_HasSVE2, // CADD_ZZI_D = 459 |
| CEFBS_HasSVE2, // CADD_ZZI_H = 460 |
| CEFBS_HasSVE2, // CADD_ZZI_S = 461 |
| CEFBS_HasLSE, // CASAB = 462 |
| CEFBS_HasLSE, // CASAH = 463 |
| CEFBS_HasLSE, // CASALB = 464 |
| CEFBS_HasLSE, // CASALH = 465 |
| CEFBS_HasLSE, // CASALW = 466 |
| CEFBS_HasLSE, // CASALX = 467 |
| CEFBS_HasLSE, // CASAW = 468 |
| CEFBS_HasLSE, // CASAX = 469 |
| CEFBS_HasLSE, // CASB = 470 |
| CEFBS_HasLSE, // CASH = 471 |
| CEFBS_HasLSE, // CASLB = 472 |
| CEFBS_HasLSE, // CASLH = 473 |
| CEFBS_HasLSE, // CASLW = 474 |
| CEFBS_HasLSE, // CASLX = 475 |
| CEFBS_HasLSE, // CASPALW = 476 |
| CEFBS_HasLSE, // CASPALX = 477 |
| CEFBS_HasLSE, // CASPAW = 478 |
| CEFBS_HasLSE, // CASPAX = 479 |
| CEFBS_HasLSE, // CASPLW = 480 |
| CEFBS_HasLSE, // CASPLX = 481 |
| CEFBS_HasLSE, // CASPW = 482 |
| CEFBS_HasLSE, // CASPX = 483 |
| CEFBS_HasLSE, // CASW = 484 |
| CEFBS_HasLSE, // CASX = 485 |
| CEFBS_None, // CATCHPAD = 486 |
| CEFBS_None, // CBNZW = 487 |
| CEFBS_None, // CBNZX = 488 |
| CEFBS_None, // CBZW = 489 |
| CEFBS_None, // CBZX = 490 |
| CEFBS_None, // CCMNWi = 491 |
| CEFBS_None, // CCMNWr = 492 |
| CEFBS_None, // CCMNXi = 493 |
| CEFBS_None, // CCMNXr = 494 |
| CEFBS_None, // CCMPWi = 495 |
| CEFBS_None, // CCMPWr = 496 |
| CEFBS_None, // CCMPXi = 497 |
| CEFBS_None, // CCMPXr = 498 |
| CEFBS_HasSVE2, // CDOT_ZZZI_D = 499 |
| CEFBS_HasSVE2, // CDOT_ZZZI_S = 500 |
| CEFBS_HasSVE2, // CDOT_ZZZ_D = 501 |
| CEFBS_HasSVE2, // CDOT_ZZZ_S = 502 |
| CEFBS_HasFMI, // CFINV = 503 |
| CEFBS_HasSVE, // CLASTA_RPZ_B = 504 |
| CEFBS_HasSVE, // CLASTA_RPZ_D = 505 |
| CEFBS_HasSVE, // CLASTA_RPZ_H = 506 |
| CEFBS_HasSVE, // CLASTA_RPZ_S = 507 |
| CEFBS_HasSVE, // CLASTA_VPZ_B = 508 |
| CEFBS_HasSVE, // CLASTA_VPZ_D = 509 |
| CEFBS_HasSVE, // CLASTA_VPZ_H = 510 |
| CEFBS_HasSVE, // CLASTA_VPZ_S = 511 |
| CEFBS_HasSVE, // CLASTA_ZPZ_B = 512 |
| CEFBS_HasSVE, // CLASTA_ZPZ_D = 513 |
| CEFBS_HasSVE, // CLASTA_ZPZ_H = 514 |
| CEFBS_HasSVE, // CLASTA_ZPZ_S = 515 |
| CEFBS_HasSVE, // CLASTB_RPZ_B = 516 |
| CEFBS_HasSVE, // CLASTB_RPZ_D = 517 |
| CEFBS_HasSVE, // CLASTB_RPZ_H = 518 |
| CEFBS_HasSVE, // CLASTB_RPZ_S = 519 |
| CEFBS_HasSVE, // CLASTB_VPZ_B = 520 |
| CEFBS_HasSVE, // CLASTB_VPZ_D = 521 |
| CEFBS_HasSVE, // CLASTB_VPZ_H = 522 |
| CEFBS_HasSVE, // CLASTB_VPZ_S = 523 |
| CEFBS_HasSVE, // CLASTB_ZPZ_B = 524 |
| CEFBS_HasSVE, // CLASTB_ZPZ_D = 525 |
| CEFBS_HasSVE, // CLASTB_ZPZ_H = 526 |
| CEFBS_HasSVE, // CLASTB_ZPZ_S = 527 |
| CEFBS_None, // CLREX = 528 |
| CEFBS_None, // CLSWr = 529 |
| CEFBS_None, // CLSXr = 530 |
| CEFBS_HasSVE, // CLS_ZPmZ_B = 531 |
| CEFBS_HasSVE, // CLS_ZPmZ_D = 532 |
| CEFBS_HasSVE, // CLS_ZPmZ_H = 533 |
| CEFBS_HasSVE, // CLS_ZPmZ_S = 534 |
| CEFBS_HasNEON, // CLSv16i8 = 535 |
| CEFBS_HasNEON, // CLSv2i32 = 536 |
| CEFBS_HasNEON, // CLSv4i16 = 537 |
| CEFBS_HasNEON, // CLSv4i32 = 538 |
| CEFBS_HasNEON, // CLSv8i16 = 539 |
| CEFBS_HasNEON, // CLSv8i8 = 540 |
| CEFBS_None, // CLZWr = 541 |
| CEFBS_None, // CLZXr = 542 |
| CEFBS_HasSVE, // CLZ_ZPmZ_B = 543 |
| CEFBS_HasSVE, // CLZ_ZPmZ_D = 544 |
| CEFBS_HasSVE, // CLZ_ZPmZ_H = 545 |
| CEFBS_HasSVE, // CLZ_ZPmZ_S = 546 |
| CEFBS_HasNEON, // CLZv16i8 = 547 |
| CEFBS_HasNEON, // CLZv2i32 = 548 |
| CEFBS_HasNEON, // CLZv4i16 = 549 |
| CEFBS_HasNEON, // CLZv4i32 = 550 |
| CEFBS_HasNEON, // CLZv8i16 = 551 |
| CEFBS_HasNEON, // CLZv8i8 = 552 |
| CEFBS_HasNEON, // CMEQv16i8 = 553 |
| CEFBS_HasNEON, // CMEQv16i8rz = 554 |
| CEFBS_HasNEON, // CMEQv1i64 = 555 |
| CEFBS_HasNEON, // CMEQv1i64rz = 556 |
| CEFBS_HasNEON, // CMEQv2i32 = 557 |
| CEFBS_HasNEON, // CMEQv2i32rz = 558 |
| CEFBS_HasNEON, // CMEQv2i64 = 559 |
| CEFBS_HasNEON, // CMEQv2i64rz = 560 |
| CEFBS_HasNEON, // CMEQv4i16 = 561 |
| CEFBS_HasNEON, // CMEQv4i16rz = 562 |
| CEFBS_HasNEON, // CMEQv4i32 = 563 |
| CEFBS_HasNEON, // CMEQv4i32rz = 564 |
| CEFBS_HasNEON, // CMEQv8i16 = 565 |
| CEFBS_HasNEON, // CMEQv8i16rz = 566 |
| CEFBS_HasNEON, // CMEQv8i8 = 567 |
| CEFBS_HasNEON, // CMEQv8i8rz = 568 |
| CEFBS_HasNEON, // CMGEv16i8 = 569 |
| CEFBS_HasNEON, // CMGEv16i8rz = 570 |
| CEFBS_HasNEON, // CMGEv1i64 = 571 |
| CEFBS_HasNEON, // CMGEv1i64rz = 572 |
| CEFBS_HasNEON, // CMGEv2i32 = 573 |
| CEFBS_HasNEON, // CMGEv2i32rz = 574 |
| CEFBS_HasNEON, // CMGEv2i64 = 575 |
| CEFBS_HasNEON, // CMGEv2i64rz = 576 |
| CEFBS_HasNEON, // CMGEv4i16 = 577 |
| CEFBS_HasNEON, // CMGEv4i16rz = 578 |
| CEFBS_HasNEON, // CMGEv4i32 = 579 |
| CEFBS_HasNEON, // CMGEv4i32rz = 580 |
| CEFBS_HasNEON, // CMGEv8i16 = 581 |
| CEFBS_HasNEON, // CMGEv8i16rz = 582 |
| CEFBS_HasNEON, // CMGEv8i8 = 583 |
| CEFBS_HasNEON, // CMGEv8i8rz = 584 |
| CEFBS_HasNEON, // CMGTv16i8 = 585 |
| CEFBS_HasNEON, // CMGTv16i8rz = 586 |
| CEFBS_HasNEON, // CMGTv1i64 = 587 |
| CEFBS_HasNEON, // CMGTv1i64rz = 588 |
| CEFBS_HasNEON, // CMGTv2i32 = 589 |
| CEFBS_HasNEON, // CMGTv2i32rz = 590 |
| CEFBS_HasNEON, // CMGTv2i64 = 591 |
| CEFBS_HasNEON, // CMGTv2i64rz = 592 |
| CEFBS_HasNEON, // CMGTv4i16 = 593 |
| CEFBS_HasNEON, // CMGTv4i16rz = 594 |
| CEFBS_HasNEON, // CMGTv4i32 = 595 |
| CEFBS_HasNEON, // CMGTv4i32rz = 596 |
| CEFBS_HasNEON, // CMGTv8i16 = 597 |
| CEFBS_HasNEON, // CMGTv8i16rz = 598 |
| CEFBS_HasNEON, // CMGTv8i8 = 599 |
| CEFBS_HasNEON, // CMGTv8i8rz = 600 |
| CEFBS_HasNEON, // CMHIv16i8 = 601 |
| CEFBS_HasNEON, // CMHIv1i64 = 602 |
| CEFBS_HasNEON, // CMHIv2i32 = 603 |
| CEFBS_HasNEON, // CMHIv2i64 = 604 |
| CEFBS_HasNEON, // CMHIv4i16 = 605 |
| CEFBS_HasNEON, // CMHIv4i32 = 606 |
| CEFBS_HasNEON, // CMHIv8i16 = 607 |
| CEFBS_HasNEON, // CMHIv8i8 = 608 |
| CEFBS_HasNEON, // CMHSv16i8 = 609 |
| CEFBS_HasNEON, // CMHSv1i64 = 610 |
| CEFBS_HasNEON, // CMHSv2i32 = 611 |
| CEFBS_HasNEON, // CMHSv2i64 = 612 |
| CEFBS_HasNEON, // CMHSv4i16 = 613 |
| CEFBS_HasNEON, // CMHSv4i32 = 614 |
| CEFBS_HasNEON, // CMHSv8i16 = 615 |
| CEFBS_HasNEON, // CMHSv8i8 = 616 |
| CEFBS_HasSVE2, // CMLA_ZZZI_H = 617 |
| CEFBS_HasSVE2, // CMLA_ZZZI_S = 618 |
| CEFBS_HasSVE2, // CMLA_ZZZ_B = 619 |
| CEFBS_HasSVE2, // CMLA_ZZZ_D = 620 |
| CEFBS_HasSVE2, // CMLA_ZZZ_H = 621 |
| CEFBS_HasSVE2, // CMLA_ZZZ_S = 622 |
| CEFBS_HasNEON, // CMLEv16i8rz = 623 |
| CEFBS_HasNEON, // CMLEv1i64rz = 624 |
| CEFBS_HasNEON, // CMLEv2i32rz = 625 |
| CEFBS_HasNEON, // CMLEv2i64rz = 626 |
| CEFBS_HasNEON, // CMLEv4i16rz = 627 |
| CEFBS_HasNEON, // CMLEv4i32rz = 628 |
| CEFBS_HasNEON, // CMLEv8i16rz = 629 |
| CEFBS_HasNEON, // CMLEv8i8rz = 630 |
| CEFBS_HasNEON, // CMLTv16i8rz = 631 |
| CEFBS_HasNEON, // CMLTv1i64rz = 632 |
| CEFBS_HasNEON, // CMLTv2i32rz = 633 |
| CEFBS_HasNEON, // CMLTv2i64rz = 634 |
| CEFBS_HasNEON, // CMLTv4i16rz = 635 |
| CEFBS_HasNEON, // CMLTv4i32rz = 636 |
| CEFBS_HasNEON, // CMLTv8i16rz = 637 |
| CEFBS_HasNEON, // CMLTv8i8rz = 638 |
| CEFBS_HasSVE, // CMPEQ_PPzZI_B = 639 |
| CEFBS_HasSVE, // CMPEQ_PPzZI_D = 640 |
| CEFBS_HasSVE, // CMPEQ_PPzZI_H = 641 |
| CEFBS_HasSVE, // CMPEQ_PPzZI_S = 642 |
| CEFBS_HasSVE, // CMPEQ_PPzZZ_B = 643 |
| CEFBS_HasSVE, // CMPEQ_PPzZZ_D = 644 |
| CEFBS_HasSVE, // CMPEQ_PPzZZ_H = 645 |
| CEFBS_HasSVE, // CMPEQ_PPzZZ_S = 646 |
| CEFBS_HasSVE, // CMPEQ_WIDE_PPzZZ_B = 647 |
| CEFBS_HasSVE, // CMPEQ_WIDE_PPzZZ_H = 648 |
| CEFBS_HasSVE, // CMPEQ_WIDE_PPzZZ_S = 649 |
| CEFBS_HasSVE, // CMPGE_PPzZI_B = 650 |
| CEFBS_HasSVE, // CMPGE_PPzZI_D = 651 |
| CEFBS_HasSVE, // CMPGE_PPzZI_H = 652 |
| CEFBS_HasSVE, // CMPGE_PPzZI_S = 653 |
| CEFBS_HasSVE, // CMPGE_PPzZZ_B = 654 |
| CEFBS_HasSVE, // CMPGE_PPzZZ_D = 655 |
| CEFBS_HasSVE, // CMPGE_PPzZZ_H = 656 |
| CEFBS_HasSVE, // CMPGE_PPzZZ_S = 657 |
| CEFBS_HasSVE, // CMPGE_WIDE_PPzZZ_B = 658 |
| CEFBS_HasSVE, // CMPGE_WIDE_PPzZZ_H = 659 |
| CEFBS_HasSVE, // CMPGE_WIDE_PPzZZ_S = 660 |
| CEFBS_HasSVE, // CMPGT_PPzZI_B = 661 |
| CEFBS_HasSVE, // CMPGT_PPzZI_D = 662 |
| CEFBS_HasSVE, // CMPGT_PPzZI_H = 663 |
| CEFBS_HasSVE, // CMPGT_PPzZI_S = 664 |
| CEFBS_HasSVE, // CMPGT_PPzZZ_B = 665 |
| CEFBS_HasSVE, // CMPGT_PPzZZ_D = 666 |
| CEFBS_HasSVE, // CMPGT_PPzZZ_H = 667 |
| CEFBS_HasSVE, // CMPGT_PPzZZ_S = 668 |
| CEFBS_HasSVE, // CMPGT_WIDE_PPzZZ_B = 669 |
| CEFBS_HasSVE, // CMPGT_WIDE_PPzZZ_H = 670 |
| CEFBS_HasSVE, // CMPGT_WIDE_PPzZZ_S = 671 |
| CEFBS_HasSVE, // CMPHI_PPzZI_B = 672 |
| CEFBS_HasSVE, // CMPHI_PPzZI_D = 673 |
| CEFBS_HasSVE, // CMPHI_PPzZI_H = 674 |
| CEFBS_HasSVE, // CMPHI_PPzZI_S = 675 |
| CEFBS_HasSVE, // CMPHI_PPzZZ_B = 676 |
| CEFBS_HasSVE, // CMPHI_PPzZZ_D = 677 |
| CEFBS_HasSVE, // CMPHI_PPzZZ_H = 678 |
| CEFBS_HasSVE, // CMPHI_PPzZZ_S = 679 |
| CEFBS_HasSVE, // CMPHI_WIDE_PPzZZ_B = 680 |
| CEFBS_HasSVE, // CMPHI_WIDE_PPzZZ_H = 681 |
| CEFBS_HasSVE, // CMPHI_WIDE_PPzZZ_S = 682 |
| CEFBS_HasSVE, // CMPHS_PPzZI_B = 683 |
| CEFBS_HasSVE, // CMPHS_PPzZI_D = 684 |
| CEFBS_HasSVE, // CMPHS_PPzZI_H = 685 |
| CEFBS_HasSVE, // CMPHS_PPzZI_S = 686 |
| CEFBS_HasSVE, // CMPHS_PPzZZ_B = 687 |
| CEFBS_HasSVE, // CMPHS_PPzZZ_D = 688 |
| CEFBS_HasSVE, // CMPHS_PPzZZ_H = 689 |
| CEFBS_HasSVE, // CMPHS_PPzZZ_S = 690 |
| CEFBS_HasSVE, // CMPHS_WIDE_PPzZZ_B = 691 |
| CEFBS_HasSVE, // CMPHS_WIDE_PPzZZ_H = 692 |
| CEFBS_HasSVE, // CMPHS_WIDE_PPzZZ_S = 693 |
| CEFBS_HasSVE, // CMPLE_PPzZI_B = 694 |
| CEFBS_HasSVE, // CMPLE_PPzZI_D = 695 |
| CEFBS_HasSVE, // CMPLE_PPzZI_H = 696 |
| CEFBS_HasSVE, // CMPLE_PPzZI_S = 697 |
| CEFBS_HasSVE, // CMPLE_WIDE_PPzZZ_B = 698 |
| CEFBS_HasSVE, // CMPLE_WIDE_PPzZZ_H = 699 |
| CEFBS_HasSVE, // CMPLE_WIDE_PPzZZ_S = 700 |
| CEFBS_HasSVE, // CMPLO_PPzZI_B = 701 |
| CEFBS_HasSVE, // CMPLO_PPzZI_D = 702 |
| CEFBS_HasSVE, // CMPLO_PPzZI_H = 703 |
| CEFBS_HasSVE, // CMPLO_PPzZI_S = 704 |
| CEFBS_HasSVE, // CMPLO_WIDE_PPzZZ_B = 705 |
| CEFBS_HasSVE, // CMPLO_WIDE_PPzZZ_H = 706 |
| CEFBS_HasSVE, // CMPLO_WIDE_PPzZZ_S = 707 |
| CEFBS_HasSVE, // CMPLS_PPzZI_B = 708 |
| CEFBS_HasSVE, // CMPLS_PPzZI_D = 709 |
| CEFBS_HasSVE, // CMPLS_PPzZI_H = 710 |
| CEFBS_HasSVE, // CMPLS_PPzZI_S = 711 |
| CEFBS_HasSVE, // CMPLS_WIDE_PPzZZ_B = 712 |
| CEFBS_HasSVE, // CMPLS_WIDE_PPzZZ_H = 713 |
| CEFBS_HasSVE, // CMPLS_WIDE_PPzZZ_S = 714 |
| CEFBS_HasSVE, // CMPLT_PPzZI_B = 715 |
| CEFBS_HasSVE, // CMPLT_PPzZI_D = 716 |
| CEFBS_HasSVE, // CMPLT_PPzZI_H = 717 |
| CEFBS_HasSVE, // CMPLT_PPzZI_S = 718 |
| CEFBS_HasSVE, // CMPLT_WIDE_PPzZZ_B = 719 |
| CEFBS_HasSVE, // CMPLT_WIDE_PPzZZ_H = 720 |
| CEFBS_HasSVE, // CMPLT_WIDE_PPzZZ_S = 721 |
| CEFBS_HasSVE, // CMPNE_PPzZI_B = 722 |
| CEFBS_HasSVE, // CMPNE_PPzZI_D = 723 |
| CEFBS_HasSVE, // CMPNE_PPzZI_H = 724 |
| CEFBS_HasSVE, // CMPNE_PPzZI_S = 725 |
| CEFBS_HasSVE, // CMPNE_PPzZZ_B = 726 |
| CEFBS_HasSVE, // CMPNE_PPzZZ_D = 727 |
| CEFBS_HasSVE, // CMPNE_PPzZZ_H = 728 |
| CEFBS_HasSVE, // CMPNE_PPzZZ_S = 729 |
| CEFBS_HasSVE, // CMPNE_WIDE_PPzZZ_B = 730 |
| CEFBS_HasSVE, // CMPNE_WIDE_PPzZZ_H = 731 |
| CEFBS_HasSVE, // CMPNE_WIDE_PPzZZ_S = 732 |
| CEFBS_None, // CMP_SWAP_128 = 733 |
| CEFBS_None, // CMP_SWAP_16 = 734 |
| CEFBS_None, // CMP_SWAP_32 = 735 |
| CEFBS_None, // CMP_SWAP_64 = 736 |
| CEFBS_None, // CMP_SWAP_8 = 737 |
| CEFBS_HasNEON, // CMTSTv16i8 = 738 |
| CEFBS_HasNEON, // CMTSTv1i64 = 739 |
| CEFBS_HasNEON, // CMTSTv2i32 = 740 |
| CEFBS_HasNEON, // CMTSTv2i64 = 741 |
| CEFBS_HasNEON, // CMTSTv4i16 = 742 |
| CEFBS_HasNEON, // CMTSTv4i32 = 743 |
| CEFBS_HasNEON, // CMTSTv8i16 = 744 |
| CEFBS_HasNEON, // CMTSTv8i8 = 745 |
| CEFBS_HasSVE, // CNOT_ZPmZ_B = 746 |
| CEFBS_HasSVE, // CNOT_ZPmZ_D = 747 |
| CEFBS_HasSVE, // CNOT_ZPmZ_H = 748 |
| CEFBS_HasSVE, // CNOT_ZPmZ_S = 749 |
| CEFBS_HasSVE, // CNTB_XPiI = 750 |
| CEFBS_HasSVE, // CNTD_XPiI = 751 |
| CEFBS_HasSVE, // CNTH_XPiI = 752 |
| CEFBS_HasSVE, // CNTP_XPP_B = 753 |
| CEFBS_HasSVE, // CNTP_XPP_D = 754 |
| CEFBS_HasSVE, // CNTP_XPP_H = 755 |
| CEFBS_HasSVE, // CNTP_XPP_S = 756 |
| CEFBS_HasSVE, // CNTW_XPiI = 757 |
| CEFBS_HasSVE, // CNT_ZPmZ_B = 758 |
| CEFBS_HasSVE, // CNT_ZPmZ_D = 759 |
| CEFBS_HasSVE, // CNT_ZPmZ_H = 760 |
| CEFBS_HasSVE, // CNT_ZPmZ_S = 761 |
| CEFBS_HasNEON, // CNTv16i8 = 762 |
| CEFBS_HasNEON, // CNTv8i8 = 763 |
| CEFBS_HasSVE, // COMPACT_ZPZ_D = 764 |
| CEFBS_HasSVE, // COMPACT_ZPZ_S = 765 |
| CEFBS_HasSVE, // CPY_ZPmI_B = 766 |
| CEFBS_HasSVE, // CPY_ZPmI_D = 767 |
| CEFBS_HasSVE, // CPY_ZPmI_H = 768 |
| CEFBS_HasSVE, // CPY_ZPmI_S = 769 |
| CEFBS_HasSVE, // CPY_ZPmR_B = 770 |
| CEFBS_HasSVE, // CPY_ZPmR_D = 771 |
| CEFBS_HasSVE, // CPY_ZPmR_H = 772 |
| CEFBS_HasSVE, // CPY_ZPmR_S = 773 |
| CEFBS_HasSVE, // CPY_ZPmV_B = 774 |
| CEFBS_HasSVE, // CPY_ZPmV_D = 775 |
| CEFBS_HasSVE, // CPY_ZPmV_H = 776 |
| CEFBS_HasSVE, // CPY_ZPmV_S = 777 |
| CEFBS_HasSVE, // CPY_ZPzI_B = 778 |
| CEFBS_HasSVE, // CPY_ZPzI_D = 779 |
| CEFBS_HasSVE, // CPY_ZPzI_H = 780 |
| CEFBS_HasSVE, // CPY_ZPzI_S = 781 |
| CEFBS_HasNEON, // CPYi16 = 782 |
| CEFBS_HasNEON, // CPYi32 = 783 |
| CEFBS_HasNEON, // CPYi64 = 784 |
| CEFBS_HasNEON, // CPYi8 = 785 |
| CEFBS_HasCRC, // CRC32Brr = 786 |
| CEFBS_HasCRC, // CRC32CBrr = 787 |
| CEFBS_HasCRC, // CRC32CHrr = 788 |
| CEFBS_HasCRC, // CRC32CWrr = 789 |
| CEFBS_HasCRC, // CRC32CXrr = 790 |
| CEFBS_HasCRC, // CRC32Hrr = 791 |
| CEFBS_HasCRC, // CRC32Wrr = 792 |
| CEFBS_HasCRC, // CRC32Xrr = 793 |
| CEFBS_None, // CSELWr = 794 |
| CEFBS_None, // CSELXr = 795 |
| CEFBS_None, // CSINCWr = 796 |
| CEFBS_None, // CSINCXr = 797 |
| CEFBS_None, // CSINVWr = 798 |
| CEFBS_None, // CSINVXr = 799 |
| CEFBS_None, // CSNEGWr = 800 |
| CEFBS_None, // CSNEGXr = 801 |
| CEFBS_HasSVE, // CTERMEQ_WW = 802 |
| CEFBS_HasSVE, // CTERMEQ_XX = 803 |
| CEFBS_HasSVE, // CTERMNE_WW = 804 |
| CEFBS_HasSVE, // CTERMNE_XX = 805 |
| CEFBS_None, // CompilerBarrier = 806 |
| CEFBS_None, // DCPS1 = 807 |
| CEFBS_None, // DCPS2 = 808 |
| CEFBS_None, // DCPS3 = 809 |
| CEFBS_HasSVE, // DECB_XPiI = 810 |
| CEFBS_HasSVE, // DECD_XPiI = 811 |
| CEFBS_HasSVE, // DECD_ZPiI = 812 |
| CEFBS_HasSVE, // DECH_XPiI = 813 |
| CEFBS_HasSVE, // DECH_ZPiI = 814 |
| CEFBS_HasSVE, // DECP_XP_B = 815 |
| CEFBS_HasSVE, // DECP_XP_D = 816 |
| CEFBS_HasSVE, // DECP_XP_H = 817 |
| CEFBS_HasSVE, // DECP_XP_S = 818 |
| CEFBS_HasSVE, // DECP_ZP_D = 819 |
| CEFBS_HasSVE, // DECP_ZP_H = 820 |
| CEFBS_HasSVE, // DECP_ZP_S = 821 |
| CEFBS_HasSVE, // DECW_XPiI = 822 |
| CEFBS_HasSVE, // DECW_ZPiI = 823 |
| CEFBS_None, // DMB = 824 |
| CEFBS_None, // DRPS = 825 |
| CEFBS_None, // DSB = 826 |
| CEFBS_HasSVE, // DUPM_ZI = 827 |
| CEFBS_HasSVE, // DUP_ZI_B = 828 |
| CEFBS_HasSVE, // DUP_ZI_D = 829 |
| CEFBS_HasSVE, // DUP_ZI_H = 830 |
| CEFBS_HasSVE, // DUP_ZI_S = 831 |
| CEFBS_HasSVE, // DUP_ZR_B = 832 |
| CEFBS_HasSVE, // DUP_ZR_D = 833 |
| CEFBS_HasSVE, // DUP_ZR_H = 834 |
| CEFBS_HasSVE, // DUP_ZR_S = 835 |
| CEFBS_HasSVE, // DUP_ZZI_B = 836 |
| CEFBS_HasSVE, // DUP_ZZI_D = 837 |
| CEFBS_HasSVE, // DUP_ZZI_H = 838 |
| CEFBS_HasSVE, // DUP_ZZI_Q = 839 |
| CEFBS_HasSVE, // DUP_ZZI_S = 840 |
| CEFBS_HasNEON, // DUPv16i8gpr = 841 |
| CEFBS_HasNEON, // DUPv16i8lane = 842 |
| CEFBS_HasNEON, // DUPv2i32gpr = 843 |
| CEFBS_HasNEON, // DUPv2i32lane = 844 |
| CEFBS_HasNEON, // DUPv2i64gpr = 845 |
| CEFBS_HasNEON, // DUPv2i64lane = 846 |
| CEFBS_HasNEON, // DUPv4i16gpr = 847 |
| CEFBS_HasNEON, // DUPv4i16lane = 848 |
| CEFBS_HasNEON, // DUPv4i32gpr = 849 |
| CEFBS_HasNEON, // DUPv4i32lane = 850 |
| CEFBS_HasNEON, // DUPv8i16gpr = 851 |
| CEFBS_HasNEON, // DUPv8i16lane = 852 |
| CEFBS_HasNEON, // DUPv8i8gpr = 853 |
| CEFBS_HasNEON, // DUPv8i8lane = 854 |
| CEFBS_None, // EMITBKEY = 855 |
| CEFBS_None, // EONWrr = 856 |
| CEFBS_None, // EONWrs = 857 |
| CEFBS_None, // EONXrr = 858 |
| CEFBS_None, // EONXrs = 859 |
| CEFBS_HasSHA3, // EOR3 = 860 |
| CEFBS_HasSVE2, // EOR3_ZZZZ_D = 861 |
| CEFBS_HasSVE2, // EORBT_ZZZ_B = 862 |
| CEFBS_HasSVE2, // EORBT_ZZZ_D = 863 |
| CEFBS_HasSVE2, // EORBT_ZZZ_H = 864 |
| CEFBS_HasSVE2, // EORBT_ZZZ_S = 865 |
| CEFBS_HasSVE, // EORS_PPzPP = 866 |
| CEFBS_HasSVE2, // EORTB_ZZZ_B = 867 |
| CEFBS_HasSVE2, // EORTB_ZZZ_D = 868 |
| CEFBS_HasSVE2, // EORTB_ZZZ_H = 869 |
| CEFBS_HasSVE2, // EORTB_ZZZ_S = 870 |
| CEFBS_HasSVE, // EORV_VPZ_B = 871 |
| CEFBS_HasSVE, // EORV_VPZ_D = 872 |
| CEFBS_HasSVE, // EORV_VPZ_H = 873 |
| CEFBS_HasSVE, // EORV_VPZ_S = 874 |
| CEFBS_None, // EORWri = 875 |
| CEFBS_None, // EORWrr = 876 |
| CEFBS_None, // EORWrs = 877 |
| CEFBS_None, // EORXri = 878 |
| CEFBS_None, // EORXrr = 879 |
| CEFBS_None, // EORXrs = 880 |
| CEFBS_HasSVE, // EOR_PPzPP = 881 |
| CEFBS_HasSVE, // EOR_ZI = 882 |
| CEFBS_HasSVE, // EOR_ZPmZ_B = 883 |
| CEFBS_HasSVE, // EOR_ZPmZ_D = 884 |
| CEFBS_HasSVE, // EOR_ZPmZ_H = 885 |
| CEFBS_HasSVE, // EOR_ZPmZ_S = 886 |
| CEFBS_HasSVE, // EOR_ZZZ = 887 |
| CEFBS_HasNEON, // EORv16i8 = 888 |
| CEFBS_HasNEON, // EORv8i8 = 889 |
| CEFBS_None, // ERET = 890 |
| CEFBS_HasPA, // ERETAA = 891 |
| CEFBS_HasPA, // ERETAB = 892 |
| CEFBS_None, // EXTRWrri = 893 |
| CEFBS_None, // EXTRXrri = 894 |
| CEFBS_HasSVE, // EXT_ZZI = 895 |
| CEFBS_HasSVE2, // EXT_ZZI_B = 896 |
| CEFBS_HasNEON, // EXTv16i8 = 897 |
| CEFBS_HasNEON, // EXTv8i8 = 898 |
| CEFBS_None, // F128CSEL = 899 |
| CEFBS_HasNEON_HasFullFP16, // FABD16 = 900 |
| CEFBS_HasNEON, // FABD32 = 901 |
| CEFBS_HasNEON, // FABD64 = 902 |
| CEFBS_HasSVE, // FABD_ZPmZ_D = 903 |
| CEFBS_HasSVE, // FABD_ZPmZ_H = 904 |
| CEFBS_HasSVE, // FABD_ZPmZ_S = 905 |
| CEFBS_HasNEON, // FABDv2f32 = 906 |
| CEFBS_HasNEON, // FABDv2f64 = 907 |
| CEFBS_HasNEON_HasFullFP16, // FABDv4f16 = 908 |
| CEFBS_HasNEON, // FABDv4f32 = 909 |
| CEFBS_HasNEON_HasFullFP16, // FABDv8f16 = 910 |
| CEFBS_HasFPARMv8, // FABSDr = 911 |
| CEFBS_HasFullFP16, // FABSHr = 912 |
| CEFBS_HasFPARMv8, // FABSSr = 913 |
| CEFBS_HasSVE, // FABS_ZPmZ_D = 914 |
| CEFBS_HasSVE, // FABS_ZPmZ_H = 915 |
| CEFBS_HasSVE, // FABS_ZPmZ_S = 916 |
| CEFBS_HasNEON, // FABSv2f32 = 917 |
| CEFBS_HasNEON, // FABSv2f64 = 918 |
| CEFBS_HasNEON_HasFullFP16, // FABSv4f16 = 919 |
| CEFBS_HasNEON, // FABSv4f32 = 920 |
| CEFBS_HasNEON_HasFullFP16, // FABSv8f16 = 921 |
| CEFBS_HasNEON_HasFullFP16, // FACGE16 = 922 |
| CEFBS_HasNEON, // FACGE32 = 923 |
| CEFBS_HasNEON, // FACGE64 = 924 |
| CEFBS_HasSVE, // FACGE_PPzZZ_D = 925 |
| CEFBS_HasSVE, // FACGE_PPzZZ_H = 926 |
| CEFBS_HasSVE, // FACGE_PPzZZ_S = 927 |
| CEFBS_HasNEON, // FACGEv2f32 = 928 |
| CEFBS_HasNEON, // FACGEv2f64 = 929 |
| CEFBS_HasNEON_HasFullFP16, // FACGEv4f16 = 930 |
| CEFBS_HasNEON, // FACGEv4f32 = 931 |
| CEFBS_HasNEON_HasFullFP16, // FACGEv8f16 = 932 |
| CEFBS_HasNEON_HasFullFP16, // FACGT16 = 933 |
| CEFBS_HasNEON, // FACGT32 = 934 |
| CEFBS_HasNEON, // FACGT64 = 935 |
| CEFBS_HasSVE, // FACGT_PPzZZ_D = 936 |
| CEFBS_HasSVE, // FACGT_PPzZZ_H = 937 |
| CEFBS_HasSVE, // FACGT_PPzZZ_S = 938 |
| CEFBS_HasNEON, // FACGTv2f32 = 939 |
| CEFBS_HasNEON, // FACGTv2f64 = 940 |
| CEFBS_HasNEON_HasFullFP16, // FACGTv4f16 = 941 |
| CEFBS_HasNEON, // FACGTv4f32 = 942 |
| CEFBS_HasNEON_HasFullFP16, // FACGTv8f16 = 943 |
| CEFBS_HasSVE, // FADDA_VPZ_D = 944 |
| CEFBS_HasSVE, // FADDA_VPZ_H = 945 |
| CEFBS_HasSVE, // FADDA_VPZ_S = 946 |
| CEFBS_HasFPARMv8, // FADDDrr = 947 |
| CEFBS_HasFullFP16, // FADDHrr = 948 |
| CEFBS_HasSVE2, // FADDP_ZPmZZ_D = 949 |
| CEFBS_HasSVE2, // FADDP_ZPmZZ_H = 950 |
| CEFBS_HasSVE2, // FADDP_ZPmZZ_S = 951 |
| CEFBS_HasNEON, // FADDPv2f32 = 952 |
| CEFBS_HasNEON, // FADDPv2f64 = 953 |
| CEFBS_HasNEON_HasFullFP16, // FADDPv2i16p = 954 |
| CEFBS_HasNEON, // FADDPv2i32p = 955 |
| CEFBS_HasNEON, // FADDPv2i64p = 956 |
| CEFBS_HasNEON_HasFullFP16, // FADDPv4f16 = 957 |
| CEFBS_HasNEON, // FADDPv4f32 = 958 |
| CEFBS_HasNEON_HasFullFP16, // FADDPv8f16 = 959 |
| CEFBS_HasFPARMv8, // FADDSrr = 960 |
| CEFBS_HasSVE, // FADDV_VPZ_D = 961 |
| CEFBS_HasSVE, // FADDV_VPZ_H = 962 |
| CEFBS_HasSVE, // FADDV_VPZ_S = 963 |
| CEFBS_HasSVE, // FADD_ZPmI_D = 964 |
| CEFBS_HasSVE, // FADD_ZPmI_H = 965 |
| CEFBS_HasSVE, // FADD_ZPmI_S = 966 |
| CEFBS_HasSVE, // FADD_ZPmZ_D = 967 |
| CEFBS_HasSVE, // FADD_ZPmZ_H = 968 |
| CEFBS_HasSVE, // FADD_ZPmZ_S = 969 |
| CEFBS_HasSVE, // FADD_ZZZ_D = 970 |
| CEFBS_HasSVE, // FADD_ZZZ_H = 971 |
| CEFBS_HasSVE, // FADD_ZZZ_S = 972 |
| CEFBS_HasNEON, // FADDv2f32 = 973 |
| CEFBS_HasNEON, // FADDv2f64 = 974 |
| CEFBS_HasNEON_HasFullFP16, // FADDv4f16 = 975 |
| CEFBS_HasNEON, // FADDv4f32 = 976 |
| CEFBS_HasNEON_HasFullFP16, // FADDv8f16 = 977 |
| CEFBS_HasSVE, // FCADD_ZPmZ_D = 978 |
| CEFBS_HasSVE, // FCADD_ZPmZ_H = 979 |
| CEFBS_HasSVE, // FCADD_ZPmZ_S = 980 |
| CEFBS_HasComplxNum_HasNEON, // FCADDv2f32 = 981 |
| CEFBS_HasComplxNum_HasNEON, // FCADDv2f64 = 982 |
| CEFBS_HasComplxNum_HasNEON_HasFullFP16, // FCADDv4f16 = 983 |
| CEFBS_HasComplxNum_HasNEON, // FCADDv4f32 = 984 |
| CEFBS_HasComplxNum_HasNEON_HasFullFP16, // FCADDv8f16 = 985 |
| CEFBS_HasFPARMv8, // FCCMPDrr = 986 |
| CEFBS_HasFPARMv8, // FCCMPEDrr = 987 |
| CEFBS_HasFullFP16, // FCCMPEHrr = 988 |
| CEFBS_HasFPARMv8, // FCCMPESrr = 989 |
| CEFBS_HasFullFP16, // FCCMPHrr = 990 |
| CEFBS_HasFPARMv8, // FCCMPSrr = 991 |
| CEFBS_HasNEON_HasFullFP16, // FCMEQ16 = 992 |
| CEFBS_HasNEON, // FCMEQ32 = 993 |
| CEFBS_HasNEON, // FCMEQ64 = 994 |
| CEFBS_HasSVE, // FCMEQ_PPzZ0_D = 995 |
| CEFBS_HasSVE, // FCMEQ_PPzZ0_H = 996 |
| CEFBS_HasSVE, // FCMEQ_PPzZ0_S = 997 |
| CEFBS_HasSVE, // FCMEQ_PPzZZ_D = 998 |
| CEFBS_HasSVE, // FCMEQ_PPzZZ_H = 999 |
| CEFBS_HasSVE, // FCMEQ_PPzZZ_S = 1000 |
| CEFBS_HasNEON_HasFullFP16, // FCMEQv1i16rz = 1001 |
| CEFBS_HasNEON, // FCMEQv1i32rz = 1002 |
| CEFBS_HasNEON, // FCMEQv1i64rz = 1003 |
| CEFBS_HasNEON, // FCMEQv2f32 = 1004 |
| CEFBS_HasNEON, // FCMEQv2f64 = 1005 |
| CEFBS_HasNEON, // FCMEQv2i32rz = 1006 |
| CEFBS_HasNEON, // FCMEQv2i64rz = 1007 |
| CEFBS_HasNEON_HasFullFP16, // FCMEQv4f16 = 1008 |
| CEFBS_HasNEON, // FCMEQv4f32 = 1009 |
| CEFBS_HasNEON_HasFullFP16, // FCMEQv4i16rz = 1010 |
| CEFBS_HasNEON, // FCMEQv4i32rz = 1011 |
| CEFBS_HasNEON_HasFullFP16, // FCMEQv8f16 = 1012 |
| CEFBS_HasNEON_HasFullFP16, // FCMEQv8i16rz = 1013 |
| CEFBS_HasNEON_HasFullFP16, // FCMGE16 = 1014 |
| CEFBS_HasNEON, // FCMGE32 = 1015 |
| CEFBS_HasNEON, // FCMGE64 = 1016 |
| CEFBS_HasSVE, // FCMGE_PPzZ0_D = 1017 |
| CEFBS_HasSVE, // FCMGE_PPzZ0_H = 1018 |
| CEFBS_HasSVE, // FCMGE_PPzZ0_S = 1019 |
| CEFBS_HasSVE, // FCMGE_PPzZZ_D = 1020 |
| CEFBS_HasSVE, // FCMGE_PPzZZ_H = 1021 |
| CEFBS_HasSVE, // FCMGE_PPzZZ_S = 1022 |
| CEFBS_HasNEON_HasFullFP16, // FCMGEv1i16rz = 1023 |
| CEFBS_HasNEON, // FCMGEv1i32rz = 1024 |
| CEFBS_HasNEON, // FCMGEv1i64rz = 1025 |
| CEFBS_HasNEON, // FCMGEv2f32 = 1026 |
| CEFBS_HasNEON, // FCMGEv2f64 = 1027 |
| CEFBS_HasNEON, // FCMGEv2i32rz = 1028 |
| CEFBS_HasNEON, // FCMGEv2i64rz = 1029 |
| CEFBS_HasNEON_HasFullFP16, // FCMGEv4f16 = 1030 |
| CEFBS_HasNEON, // FCMGEv4f32 = 1031 |
| CEFBS_HasNEON_HasFullFP16, // FCMGEv4i16rz = 1032 |
| CEFBS_HasNEON, // FCMGEv4i32rz = 1033 |
| CEFBS_HasNEON_HasFullFP16, // FCMGEv8f16 = 1034 |
| CEFBS_HasNEON_HasFullFP16, // FCMGEv8i16rz = 1035 |
| CEFBS_HasNEON_HasFullFP16, // FCMGT16 = 1036 |
| CEFBS_HasNEON, // FCMGT32 = 1037 |
| CEFBS_HasNEON, // FCMGT64 = 1038 |
| CEFBS_HasSVE, // FCMGT_PPzZ0_D = 1039 |
| CEFBS_HasSVE, // FCMGT_PPzZ0_H = 1040 |
| CEFBS_HasSVE, // FCMGT_PPzZ0_S = 1041 |
| CEFBS_HasSVE, // FCMGT_PPzZZ_D = 1042 |
| CEFBS_HasSVE, // FCMGT_PPzZZ_H = 1043 |
| CEFBS_HasSVE, // FCMGT_PPzZZ_S = 1044 |
| CEFBS_HasNEON_HasFullFP16, // FCMGTv1i16rz = 1045 |
| CEFBS_HasNEON, // FCMGTv1i32rz = 1046 |
| CEFBS_HasNEON, // FCMGTv1i64rz = 1047 |
| CEFBS_HasNEON, // FCMGTv2f32 = 1048 |
| CEFBS_HasNEON, // FCMGTv2f64 = 1049 |
| CEFBS_HasNEON, // FCMGTv2i32rz = 1050 |
| CEFBS_HasNEON, // FCMGTv2i64rz = 1051 |
| CEFBS_HasNEON_HasFullFP16, // FCMGTv4f16 = 1052 |
| CEFBS_HasNEON, // FCMGTv4f32 = 1053 |
| CEFBS_HasNEON_HasFullFP16, // FCMGTv4i16rz = 1054 |
| CEFBS_HasNEON, // FCMGTv4i32rz = 1055 |
| CEFBS_HasNEON_HasFullFP16, // FCMGTv8f16 = 1056 |
| CEFBS_HasNEON_HasFullFP16, // FCMGTv8i16rz = 1057 |
| CEFBS_HasSVE, // FCMLA_ZPmZZ_D = 1058 |
| CEFBS_HasSVE, // FCMLA_ZPmZZ_H = 1059 |
| CEFBS_HasSVE, // FCMLA_ZPmZZ_S = 1060 |
| CEFBS_HasSVE, // FCMLA_ZZZI_H = 1061 |
| CEFBS_HasSVE, // FCMLA_ZZZI_S = 1062 |
| CEFBS_HasComplxNum_HasNEON, // FCMLAv2f32 = 1063 |
| CEFBS_HasComplxNum_HasNEON, // FCMLAv2f64 = 1064 |
| CEFBS_HasComplxNum_HasNEON_HasFullFP16, // FCMLAv4f16 = 1065 |
| CEFBS_HasComplxNum_HasNEON_HasFullFP16, // FCMLAv4f16_indexed = 1066 |
| CEFBS_HasComplxNum_HasNEON, // FCMLAv4f32 = 1067 |
| CEFBS_HasComplxNum_HasNEON, // FCMLAv4f32_indexed = 1068 |
| CEFBS_HasComplxNum_HasNEON_HasFullFP16, // FCMLAv8f16 = 1069 |
| CEFBS_HasComplxNum_HasNEON_HasFullFP16, // FCMLAv8f16_indexed = 1070 |
| CEFBS_HasSVE, // FCMLE_PPzZ0_D = 1071 |
| CEFBS_HasSVE, // FCMLE_PPzZ0_H = 1072 |
| CEFBS_HasSVE, // FCMLE_PPzZ0_S = 1073 |
| CEFBS_HasNEON_HasFullFP16, // FCMLEv1i16rz = 1074 |
| CEFBS_HasNEON, // FCMLEv1i32rz = 1075 |
| CEFBS_HasNEON, // FCMLEv1i64rz = 1076 |
| CEFBS_HasNEON, // FCMLEv2i32rz = 1077 |
| CEFBS_HasNEON, // FCMLEv2i64rz = 1078 |
| CEFBS_HasNEON_HasFullFP16, // FCMLEv4i16rz = 1079 |
| CEFBS_HasNEON, // FCMLEv4i32rz = 1080 |
| CEFBS_HasNEON_HasFullFP16, // FCMLEv8i16rz = 1081 |
| CEFBS_HasSVE, // FCMLT_PPzZ0_D = 1082 |
| CEFBS_HasSVE, // FCMLT_PPzZ0_H = 1083 |
| CEFBS_HasSVE, // FCMLT_PPzZ0_S = 1084 |
| CEFBS_HasNEON_HasFullFP16, // FCMLTv1i16rz = 1085 |
| CEFBS_HasNEON, // FCMLTv1i32rz = 1086 |
| CEFBS_HasNEON, // FCMLTv1i64rz = 1087 |
| CEFBS_HasNEON, // FCMLTv2i32rz = 1088 |
| CEFBS_HasNEON, // FCMLTv2i64rz = 1089 |
| CEFBS_HasNEON_HasFullFP16, // FCMLTv4i16rz = 1090 |
| CEFBS_HasNEON, // FCMLTv4i32rz = 1091 |
| CEFBS_HasNEON_HasFullFP16, // FCMLTv8i16rz = 1092 |
| CEFBS_HasSVE, // FCMNE_PPzZ0_D = 1093 |
| CEFBS_HasSVE, // FCMNE_PPzZ0_H = 1094 |
| CEFBS_HasSVE, // FCMNE_PPzZ0_S = 1095 |
| CEFBS_HasSVE, // FCMNE_PPzZZ_D = 1096 |
| CEFBS_HasSVE, // FCMNE_PPzZZ_H = 1097 |
| CEFBS_HasSVE, // FCMNE_PPzZZ_S = 1098 |
| CEFBS_HasFPARMv8, // FCMPDri = 1099 |
| CEFBS_HasFPARMv8, // FCMPDrr = 1100 |
| CEFBS_HasFPARMv8, // FCMPEDri = 1101 |
| CEFBS_HasFPARMv8, // FCMPEDrr = 1102 |
| CEFBS_HasFullFP16, // FCMPEHri = 1103 |
| CEFBS_HasFullFP16, // FCMPEHrr = 1104 |
| CEFBS_HasFPARMv8, // FCMPESri = 1105 |
| CEFBS_HasFPARMv8, // FCMPESrr = 1106 |
| CEFBS_HasFullFP16, // FCMPHri = 1107 |
| CEFBS_HasFullFP16, // FCMPHrr = 1108 |
| CEFBS_HasFPARMv8, // FCMPSri = 1109 |
| CEFBS_HasFPARMv8, // FCMPSrr = 1110 |
| CEFBS_HasSVE, // FCMUO_PPzZZ_D = 1111 |
| CEFBS_HasSVE, // FCMUO_PPzZZ_H = 1112 |
| CEFBS_HasSVE, // FCMUO_PPzZZ_S = 1113 |
| CEFBS_HasSVE, // FCPY_ZPmI_D = 1114 |
| CEFBS_HasSVE, // FCPY_ZPmI_H = 1115 |
| CEFBS_HasSVE, // FCPY_ZPmI_S = 1116 |
| CEFBS_HasFPARMv8, // FCSELDrrr = 1117 |
| CEFBS_HasFullFP16, // FCSELHrrr = 1118 |
| CEFBS_HasFPARMv8, // FCSELSrrr = 1119 |
| CEFBS_HasFPARMv8, // FCVTASUWDr = 1120 |
| CEFBS_HasFullFP16, // FCVTASUWHr = 1121 |
| CEFBS_HasFPARMv8, // FCVTASUWSr = 1122 |
| CEFBS_HasFPARMv8, // FCVTASUXDr = 1123 |
| CEFBS_HasFullFP16, // FCVTASUXHr = 1124 |
| CEFBS_HasFPARMv8, // FCVTASUXSr = 1125 |
| CEFBS_HasNEON_HasFullFP16, // FCVTASv1f16 = 1126 |
| CEFBS_HasNEON, // FCVTASv1i32 = 1127 |
| CEFBS_HasNEON, // FCVTASv1i64 = 1128 |
| CEFBS_HasNEON, // FCVTASv2f32 = 1129 |
| CEFBS_HasNEON, // FCVTASv2f64 = 1130 |
| CEFBS_HasNEON_HasFullFP16, // FCVTASv4f16 = 1131 |
| CEFBS_HasNEON, // FCVTASv4f32 = 1132 |
| CEFBS_HasNEON_HasFullFP16, // FCVTASv8f16 = 1133 |
| CEFBS_HasFPARMv8, // FCVTAUUWDr = 1134 |
| CEFBS_HasFullFP16, // FCVTAUUWHr = 1135 |
| CEFBS_HasFPARMv8, // FCVTAUUWSr = 1136 |
| CEFBS_HasFPARMv8, // FCVTAUUXDr = 1137 |
| CEFBS_HasFullFP16, // FCVTAUUXHr = 1138 |
| CEFBS_HasFPARMv8, // FCVTAUUXSr = 1139 |
| CEFBS_HasNEON_HasFullFP16, // FCVTAUv1f16 = 1140 |
| CEFBS_HasNEON, // FCVTAUv1i32 = 1141 |
| CEFBS_HasNEON, // FCVTAUv1i64 = 1142 |
| CEFBS_HasNEON, // FCVTAUv2f32 = 1143 |
| CEFBS_HasNEON, // FCVTAUv2f64 = 1144 |
| CEFBS_HasNEON_HasFullFP16, // FCVTAUv4f16 = 1145 |
| CEFBS_HasNEON, // FCVTAUv4f32 = 1146 |
| CEFBS_HasNEON_HasFullFP16, // FCVTAUv8f16 = 1147 |
| CEFBS_HasFPARMv8, // FCVTDHr = 1148 |
| CEFBS_HasFPARMv8, // FCVTDSr = 1149 |
| CEFBS_HasFPARMv8, // FCVTHDr = 1150 |
| CEFBS_HasFPARMv8, // FCVTHSr = 1151 |
| CEFBS_HasSVE2, // FCVTLT_ZPmZ_HtoS = 1152 |
| CEFBS_HasSVE2, // FCVTLT_ZPmZ_StoD = 1153 |
| CEFBS_HasNEON, // FCVTLv2i32 = 1154 |
| CEFBS_HasNEON, // FCVTLv4i16 = 1155 |
| CEFBS_HasNEON, // FCVTLv4i32 = 1156 |
| CEFBS_HasNEON, // FCVTLv8i16 = 1157 |
| CEFBS_HasFPARMv8, // FCVTMSUWDr = 1158 |
| CEFBS_HasFullFP16, // FCVTMSUWHr = 1159 |
| CEFBS_HasFPARMv8, // FCVTMSUWSr = 1160 |
| CEFBS_HasFPARMv8, // FCVTMSUXDr = 1161 |
| CEFBS_HasFullFP16, // FCVTMSUXHr = 1162 |
| CEFBS_HasFPARMv8, // FCVTMSUXSr = 1163 |
| CEFBS_HasNEON_HasFullFP16, // FCVTMSv1f16 = 1164 |
| CEFBS_HasNEON, // FCVTMSv1i32 = 1165 |
| CEFBS_HasNEON, // FCVTMSv1i64 = 1166 |
| CEFBS_HasNEON, // FCVTMSv2f32 = 1167 |
| CEFBS_HasNEON, // FCVTMSv2f64 = 1168 |
| CEFBS_HasNEON_HasFullFP16, // FCVTMSv4f16 = 1169 |
| CEFBS_HasNEON, // FCVTMSv4f32 = 1170 |
| CEFBS_HasNEON_HasFullFP16, // FCVTMSv8f16 = 1171 |
| CEFBS_HasFPARMv8, // FCVTMUUWDr = 1172 |
| CEFBS_HasFullFP16, // FCVTMUUWHr = 1173 |
| CEFBS_HasFPARMv8, // FCVTMUUWSr = 1174 |
| CEFBS_HasFPARMv8, // FCVTMUUXDr = 1175 |
| CEFBS_HasFullFP16, // FCVTMUUXHr = 1176 |
| CEFBS_HasFPARMv8, // FCVTMUUXSr = 1177 |
| CEFBS_HasNEON_HasFullFP16, // FCVTMUv1f16 = 1178 |
| CEFBS_HasNEON, // FCVTMUv1i32 = 1179 |
| CEFBS_HasNEON, // FCVTMUv1i64 = 1180 |
| CEFBS_HasNEON, // FCVTMUv2f32 = 1181 |
| CEFBS_HasNEON, // FCVTMUv2f64 = 1182 |
| CEFBS_HasNEON_HasFullFP16, // FCVTMUv4f16 = 1183 |
| CEFBS_HasNEON, // FCVTMUv4f32 = 1184 |
| CEFBS_HasNEON_HasFullFP16, // FCVTMUv8f16 = 1185 |
| CEFBS_HasFPARMv8, // FCVTNSUWDr = 1186 |
| CEFBS_HasFullFP16, // FCVTNSUWHr = 1187 |
| CEFBS_HasFPARMv8, // FCVTNSUWSr = 1188 |
| CEFBS_HasFPARMv8, // FCVTNSUXDr = 1189 |
| CEFBS_HasFullFP16, // FCVTNSUXHr = 1190 |
| CEFBS_HasFPARMv8, // FCVTNSUXSr = 1191 |
| CEFBS_HasNEON_HasFullFP16, // FCVTNSv1f16 = 1192 |
| CEFBS_HasNEON, // FCVTNSv1i32 = 1193 |
| CEFBS_HasNEON, // FCVTNSv1i64 = 1194 |
| CEFBS_HasNEON, // FCVTNSv2f32 = 1195 |
| CEFBS_HasNEON, // FCVTNSv2f64 = 1196 |
| CEFBS_HasNEON_HasFullFP16, // FCVTNSv4f16 = 1197 |
| CEFBS_HasNEON, // FCVTNSv4f32 = 1198 |
| CEFBS_HasNEON_HasFullFP16, // FCVTNSv8f16 = 1199 |
| CEFBS_HasSVE2, // FCVTNT_ZPmZ_DtoS = 1200 |
| CEFBS_HasSVE2, // FCVTNT_ZPmZ_StoH = 1201 |
| CEFBS_HasFPARMv8, // FCVTNUUWDr = 1202 |
| CEFBS_HasFullFP16, // FCVTNUUWHr = 1203 |
| CEFBS_HasFPARMv8, // FCVTNUUWSr = 1204 |
| CEFBS_HasFPARMv8, // FCVTNUUXDr = 1205 |
| CEFBS_HasFullFP16, // FCVTNUUXHr = 1206 |
| CEFBS_HasFPARMv8, // FCVTNUUXSr = 1207 |
| CEFBS_HasNEON_HasFullFP16, // FCVTNUv1f16 = 1208 |
| CEFBS_HasNEON, // FCVTNUv1i32 = 1209 |
| CEFBS_HasNEON, // FCVTNUv1i64 = 1210 |
| CEFBS_HasNEON, // FCVTNUv2f32 = 1211 |
| CEFBS_HasNEON, // FCVTNUv2f64 = 1212 |
| CEFBS_HasNEON_HasFullFP16, // FCVTNUv4f16 = 1213 |
| CEFBS_HasNEON, // FCVTNUv4f32 = 1214 |
| CEFBS_HasNEON_HasFullFP16, // FCVTNUv8f16 = 1215 |
| CEFBS_HasNEON, // FCVTNv2i32 = 1216 |
| CEFBS_HasNEON, // FCVTNv4i16 = 1217 |
| CEFBS_HasNEON, // FCVTNv4i32 = 1218 |
| CEFBS_HasNEON, // FCVTNv8i16 = 1219 |
| CEFBS_HasFPARMv8, // FCVTPSUWDr = 1220 |
| CEFBS_HasFullFP16, // FCVTPSUWHr = 1221 |
| CEFBS_HasFPARMv8, // FCVTPSUWSr = 1222 |
| CEFBS_HasFPARMv8, // FCVTPSUXDr = 1223 |
| CEFBS_HasFullFP16, // FCVTPSUXHr = 1224 |
| CEFBS_HasFPARMv8, // FCVTPSUXSr = 1225 |
| CEFBS_HasNEON_HasFullFP16, // FCVTPSv1f16 = 1226 |
| CEFBS_HasNEON, // FCVTPSv1i32 = 1227 |
| CEFBS_HasNEON, // FCVTPSv1i64 = 1228 |
| CEFBS_HasNEON, // FCVTPSv2f32 = 1229 |
| CEFBS_HasNEON, // FCVTPSv2f64 = 1230 |
| CEFBS_HasNEON_HasFullFP16, // FCVTPSv4f16 = 1231 |
| CEFBS_HasNEON, // FCVTPSv4f32 = 1232 |
| CEFBS_HasNEON_HasFullFP16, // FCVTPSv8f16 = 1233 |
| CEFBS_HasFPARMv8, // FCVTPUUWDr = 1234 |
| CEFBS_HasFullFP16, // FCVTPUUWHr = 1235 |
| CEFBS_HasFPARMv8, // FCVTPUUWSr = 1236 |
| CEFBS_HasFPARMv8, // FCVTPUUXDr = 1237 |
| CEFBS_HasFullFP16, // FCVTPUUXHr = 1238 |
| CEFBS_HasFPARMv8, // FCVTPUUXSr = 1239 |
| CEFBS_HasNEON_HasFullFP16, // FCVTPUv1f16 = 1240 |
| CEFBS_HasNEON, // FCVTPUv1i32 = 1241 |
| CEFBS_HasNEON, // FCVTPUv1i64 = 1242 |
| CEFBS_HasNEON, // FCVTPUv2f32 = 1243 |
| CEFBS_HasNEON, // FCVTPUv2f64 = 1244 |
| CEFBS_HasNEON_HasFullFP16, // FCVTPUv4f16 = 1245 |
| CEFBS_HasNEON, // FCVTPUv4f32 = 1246 |
| CEFBS_HasNEON_HasFullFP16, // FCVTPUv8f16 = 1247 |
| CEFBS_HasFPARMv8, // FCVTSDr = 1248 |
| CEFBS_HasFPARMv8, // FCVTSHr = 1249 |
| CEFBS_HasSVE2, // FCVTXNT_ZPmZ_DtoS = 1250 |
| CEFBS_HasNEON, // FCVTXNv1i64 = 1251 |
| CEFBS_HasNEON, // FCVTXNv2f32 = 1252 |
| CEFBS_HasNEON, // FCVTXNv4f32 = 1253 |
| CEFBS_HasSVE2, // FCVTX_ZPmZ_DtoS = 1254 |
| CEFBS_HasFPARMv8, // FCVTZSSWDri = 1255 |
| CEFBS_HasFullFP16, // FCVTZSSWHri = 1256 |
| CEFBS_HasFPARMv8, // FCVTZSSWSri = 1257 |
| CEFBS_HasFPARMv8, // FCVTZSSXDri = 1258 |
| CEFBS_HasFullFP16, // FCVTZSSXHri = 1259 |
| CEFBS_HasFPARMv8, // FCVTZSSXSri = 1260 |
| CEFBS_HasFPARMv8, // FCVTZSUWDr = 1261 |
| CEFBS_HasFullFP16, // FCVTZSUWHr = 1262 |
| CEFBS_HasFPARMv8, // FCVTZSUWSr = 1263 |
| CEFBS_HasFPARMv8, // FCVTZSUXDr = 1264 |
| CEFBS_HasFullFP16, // FCVTZSUXHr = 1265 |
| CEFBS_HasFPARMv8, // FCVTZSUXSr = 1266 |
| CEFBS_HasSVE, // FCVTZS_ZPmZ_DtoD = 1267 |
| CEFBS_HasSVE, // FCVTZS_ZPmZ_DtoS = 1268 |
| CEFBS_HasSVE, // FCVTZS_ZPmZ_HtoD = 1269 |
| CEFBS_HasSVE, // FCVTZS_ZPmZ_HtoH = 1270 |
| CEFBS_HasSVE, // FCVTZS_ZPmZ_HtoS = 1271 |
| CEFBS_HasSVE, // FCVTZS_ZPmZ_StoD = 1272 |
| CEFBS_HasSVE, // FCVTZS_ZPmZ_StoS = 1273 |
| CEFBS_HasNEON, // FCVTZSd = 1274 |
| CEFBS_HasNEON_HasFullFP16, // FCVTZSh = 1275 |
| CEFBS_HasNEON, // FCVTZSs = 1276 |
| CEFBS_HasNEON_HasFullFP16, // FCVTZSv1f16 = 1277 |
| CEFBS_HasNEON, // FCVTZSv1i32 = 1278 |
| CEFBS_HasNEON, // FCVTZSv1i64 = 1279 |
| CEFBS_HasNEON, // FCVTZSv2f32 = 1280 |
| CEFBS_HasNEON, // FCVTZSv2f64 = 1281 |
| CEFBS_HasNEON, // FCVTZSv2i32_shift = 1282 |
| CEFBS_HasNEON, // FCVTZSv2i64_shift = 1283 |
| CEFBS_HasNEON_HasFullFP16, // FCVTZSv4f16 = 1284 |
| CEFBS_HasNEON, // FCVTZSv4f32 = 1285 |
| CEFBS_HasNEON_HasFullFP16, // FCVTZSv4i16_shift = 1286 |
| CEFBS_HasNEON, // FCVTZSv4i32_shift = 1287 |
| CEFBS_HasNEON_HasFullFP16, // FCVTZSv8f16 = 1288 |
| CEFBS_HasNEON_HasFullFP16, // FCVTZSv8i16_shift = 1289 |
| CEFBS_HasFPARMv8, // FCVTZUSWDri = 1290 |
| CEFBS_HasFullFP16, // FCVTZUSWHri = 1291 |
| CEFBS_HasFPARMv8, // FCVTZUSWSri = 1292 |
| CEFBS_HasFPARMv8, // FCVTZUSXDri = 1293 |
| CEFBS_HasFullFP16, // FCVTZUSXHri = 1294 |
| CEFBS_HasFPARMv8, // FCVTZUSXSri = 1295 |
| CEFBS_HasFPARMv8, // FCVTZUUWDr = 1296 |
| CEFBS_HasFullFP16, // FCVTZUUWHr = 1297 |
| CEFBS_HasFPARMv8, // FCVTZUUWSr = 1298 |
| CEFBS_HasFPARMv8, // FCVTZUUXDr = 1299 |
| CEFBS_HasFullFP16, // FCVTZUUXHr = 1300 |
| CEFBS_HasFPARMv8, // FCVTZUUXSr = 1301 |
| CEFBS_HasSVE, // FCVTZU_ZPmZ_DtoD = 1302 |
| CEFBS_HasSVE, // FCVTZU_ZPmZ_DtoS = 1303 |
| CEFBS_HasSVE, // FCVTZU_ZPmZ_HtoD = 1304 |
| CEFBS_HasSVE, // FCVTZU_ZPmZ_HtoH = 1305 |
| CEFBS_HasSVE, // FCVTZU_ZPmZ_HtoS = 1306 |
| CEFBS_HasSVE, // FCVTZU_ZPmZ_StoD = 1307 |
| CEFBS_HasSVE, // FCVTZU_ZPmZ_StoS = 1308 |
| CEFBS_HasNEON, // FCVTZUd = 1309 |
| CEFBS_HasNEON_HasFullFP16, // FCVTZUh = 1310 |
| CEFBS_HasNEON, // FCVTZUs = 1311 |
| CEFBS_HasNEON_HasFullFP16, // FCVTZUv1f16 = 1312 |
| CEFBS_HasNEON, // FCVTZUv1i32 = 1313 |
| CEFBS_HasNEON, // FCVTZUv1i64 = 1314 |
| CEFBS_HasNEON, // FCVTZUv2f32 = 1315 |
| CEFBS_HasNEON, // FCVTZUv2f64 = 1316 |
| CEFBS_HasNEON, // FCVTZUv2i32_shift = 1317 |
| CEFBS_HasNEON, // FCVTZUv2i64_shift = 1318 |
| CEFBS_HasNEON_HasFullFP16, // FCVTZUv4f16 = 1319 |
| CEFBS_HasNEON, // FCVTZUv4f32 = 1320 |
| CEFBS_HasNEON_HasFullFP16, // FCVTZUv4i16_shift = 1321 |
| CEFBS_HasNEON, // FCVTZUv4i32_shift = 1322 |
| CEFBS_HasNEON_HasFullFP16, // FCVTZUv8f16 = 1323 |
| CEFBS_HasNEON_HasFullFP16, // FCVTZUv8i16_shift = 1324 |
| CEFBS_HasSVE, // FCVT_ZPmZ_DtoH = 1325 |
| CEFBS_HasSVE, // FCVT_ZPmZ_DtoS = 1326 |
| CEFBS_HasSVE, // FCVT_ZPmZ_HtoD = 1327 |
| CEFBS_HasSVE, // FCVT_ZPmZ_HtoS = 1328 |
| CEFBS_HasSVE, // FCVT_ZPmZ_StoD = 1329 |
| CEFBS_HasSVE, // FCVT_ZPmZ_StoH = 1330 |
| CEFBS_HasFPARMv8, // FDIVDrr = 1331 |
| CEFBS_HasFullFP16, // FDIVHrr = 1332 |
| CEFBS_HasSVE, // FDIVR_ZPmZ_D = 1333 |
| CEFBS_HasSVE, // FDIVR_ZPmZ_H = 1334 |
| CEFBS_HasSVE, // FDIVR_ZPmZ_S = 1335 |
| CEFBS_HasFPARMv8, // FDIVSrr = 1336 |
| CEFBS_HasSVE, // FDIV_ZPmZ_D = 1337 |
| CEFBS_HasSVE, // FDIV_ZPmZ_H = 1338 |
| CEFBS_HasSVE, // FDIV_ZPmZ_S = 1339 |
| CEFBS_HasNEON, // FDIVv2f32 = 1340 |
| CEFBS_HasNEON, // FDIVv2f64 = 1341 |
| CEFBS_HasNEON_HasFullFP16, // FDIVv4f16 = 1342 |
| CEFBS_HasNEON, // FDIVv4f32 = 1343 |
| CEFBS_HasNEON_HasFullFP16, // FDIVv8f16 = 1344 |
| CEFBS_HasSVE, // FDUP_ZI_D = 1345 |
| CEFBS_HasSVE, // FDUP_ZI_H = 1346 |
| CEFBS_HasSVE, // FDUP_ZI_S = 1347 |
| CEFBS_HasSVE, // FEXPA_ZZ_D = 1348 |
| CEFBS_HasSVE, // FEXPA_ZZ_H = 1349 |
| CEFBS_HasSVE, // FEXPA_ZZ_S = 1350 |
| CEFBS_HasJS_HasFPARMv8, // FJCVTZS = 1351 |
| CEFBS_HasSVE2, // FLOGB_ZPmZ_D = 1352 |
| CEFBS_HasSVE2, // FLOGB_ZPmZ_H = 1353 |
| CEFBS_HasSVE2, // FLOGB_ZPmZ_S = 1354 |
| CEFBS_HasFPARMv8, // FMADDDrrr = 1355 |
| CEFBS_HasFullFP16, // FMADDHrrr = 1356 |
| CEFBS_HasFPARMv8, // FMADDSrrr = 1357 |
| CEFBS_HasSVE, // FMAD_ZPmZZ_D = 1358 |
| CEFBS_HasSVE, // FMAD_ZPmZZ_H = 1359 |
| CEFBS_HasSVE, // FMAD_ZPmZZ_S = 1360 |
| CEFBS_HasFPARMv8, // FMAXDrr = 1361 |
| CEFBS_HasFullFP16, // FMAXHrr = 1362 |
| CEFBS_HasFPARMv8, // FMAXNMDrr = 1363 |
| CEFBS_HasFullFP16, // FMAXNMHrr = 1364 |
| CEFBS_HasSVE2, // FMAXNMP_ZPmZZ_D = 1365 |
| CEFBS_HasSVE2, // FMAXNMP_ZPmZZ_H = 1366 |
| CEFBS_HasSVE2, // FMAXNMP_ZPmZZ_S = 1367 |
| CEFBS_HasNEON, // FMAXNMPv2f32 = 1368 |
| CEFBS_HasNEON, // FMAXNMPv2f64 = 1369 |
| CEFBS_HasNEON_HasFullFP16, // FMAXNMPv2i16p = 1370 |
| CEFBS_HasNEON, // FMAXNMPv2i32p = 1371 |
| CEFBS_HasNEON, // FMAXNMPv2i64p = 1372 |
| CEFBS_HasNEON_HasFullFP16, // FMAXNMPv4f16 = 1373 |
| CEFBS_HasNEON, // FMAXNMPv4f32 = 1374 |
| CEFBS_HasNEON_HasFullFP16, // FMAXNMPv8f16 = 1375 |
| CEFBS_HasFPARMv8, // FMAXNMSrr = 1376 |
| CEFBS_HasSVE, // FMAXNMV_VPZ_D = 1377 |
| CEFBS_HasSVE, // FMAXNMV_VPZ_H = 1378 |
| CEFBS_HasSVE, // FMAXNMV_VPZ_S = 1379 |
| CEFBS_HasNEON_HasFullFP16, // FMAXNMVv4i16v = 1380 |
| CEFBS_HasNEON, // FMAXNMVv4i32v = 1381 |
| CEFBS_HasNEON_HasFullFP16, // FMAXNMVv8i16v = 1382 |
| CEFBS_HasSVE, // FMAXNM_ZPmI_D = 1383 |
| CEFBS_HasSVE, // FMAXNM_ZPmI_H = 1384 |
| CEFBS_HasSVE, // FMAXNM_ZPmI_S = 1385 |
| CEFBS_HasSVE, // FMAXNM_ZPmZ_D = 1386 |
| CEFBS_HasSVE, // FMAXNM_ZPmZ_H = 1387 |
| CEFBS_HasSVE, // FMAXNM_ZPmZ_S = 1388 |
| CEFBS_HasNEON, // FMAXNMv2f32 = 1389 |
| CEFBS_HasNEON, // FMAXNMv2f64 = 1390 |
| CEFBS_HasNEON_HasFullFP16, // FMAXNMv4f16 = 1391 |
| CEFBS_HasNEON, // FMAXNMv4f32 = 1392 |
| CEFBS_HasNEON_HasFullFP16, // FMAXNMv8f16 = 1393 |
| CEFBS_HasSVE2, // FMAXP_ZPmZZ_D = 1394 |
| CEFBS_HasSVE2, // FMAXP_ZPmZZ_H = 1395 |
| CEFBS_HasSVE2, // FMAXP_ZPmZZ_S = 1396 |
| CEFBS_HasNEON, // FMAXPv2f32 = 1397 |
| CEFBS_HasNEON, // FMAXPv2f64 = 1398 |
| CEFBS_HasNEON_HasFullFP16, // FMAXPv2i16p = 1399 |
| CEFBS_HasNEON, // FMAXPv2i32p = 1400 |
| CEFBS_HasNEON, // FMAXPv2i64p = 1401 |
| CEFBS_HasNEON_HasFullFP16, // FMAXPv4f16 = 1402 |
| CEFBS_HasNEON, // FMAXPv4f32 = 1403 |
| CEFBS_HasNEON_HasFullFP16, // FMAXPv8f16 = 1404 |
| CEFBS_HasFPARMv8, // FMAXSrr = 1405 |
| CEFBS_HasSVE, // FMAXV_VPZ_D = 1406 |
| CEFBS_HasSVE, // FMAXV_VPZ_H = 1407 |
| CEFBS_HasSVE, // FMAXV_VPZ_S = 1408 |
| CEFBS_HasNEON_HasFullFP16, // FMAXVv4i16v = 1409 |
| CEFBS_HasNEON, // FMAXVv4i32v = 1410 |
| CEFBS_HasNEON_HasFullFP16, // FMAXVv8i16v = 1411 |
| CEFBS_HasSVE, // FMAX_ZPmI_D = 1412 |
| CEFBS_HasSVE, // FMAX_ZPmI_H = 1413 |
| CEFBS_HasSVE, // FMAX_ZPmI_S = 1414 |
| CEFBS_HasSVE, // FMAX_ZPmZ_D = 1415 |
| CEFBS_HasSVE, // FMAX_ZPmZ_H = 1416 |
| CEFBS_HasSVE, // FMAX_ZPmZ_S = 1417 |
| CEFBS_HasNEON, // FMAXv2f32 = 1418 |
| CEFBS_HasNEON, // FMAXv2f64 = 1419 |
| CEFBS_HasNEON_HasFullFP16, // FMAXv4f16 = 1420 |
| CEFBS_HasNEON, // FMAXv4f32 = 1421 |
| CEFBS_HasNEON_HasFullFP16, // FMAXv8f16 = 1422 |
| CEFBS_HasFPARMv8, // FMINDrr = 1423 |
| CEFBS_HasFullFP16, // FMINHrr = 1424 |
| CEFBS_HasFPARMv8, // FMINNMDrr = 1425 |
| CEFBS_HasFullFP16, // FMINNMHrr = 1426 |
| CEFBS_HasSVE2, // FMINNMP_ZPmZZ_D = 1427 |
| CEFBS_HasSVE2, // FMINNMP_ZPmZZ_H = 1428 |
| CEFBS_HasSVE2, // FMINNMP_ZPmZZ_S = 1429 |
| CEFBS_HasNEON, // FMINNMPv2f32 = 1430 |
| CEFBS_HasNEON, // FMINNMPv2f64 = 1431 |
| CEFBS_HasNEON_HasFullFP16, // FMINNMPv2i16p = 1432 |
| CEFBS_HasNEON, // FMINNMPv2i32p = 1433 |
| CEFBS_HasNEON, // FMINNMPv2i64p = 1434 |
| CEFBS_HasNEON_HasFullFP16, // FMINNMPv4f16 = 1435 |
| CEFBS_HasNEON, // FMINNMPv4f32 = 1436 |
| CEFBS_HasNEON_HasFullFP16, // FMINNMPv8f16 = 1437 |
| CEFBS_HasFPARMv8, // FMINNMSrr = 1438 |
| CEFBS_HasSVE, // FMINNMV_VPZ_D = 1439 |
| CEFBS_HasSVE, // FMINNMV_VPZ_H = 1440 |
| CEFBS_HasSVE, // FMINNMV_VPZ_S = 1441 |
| CEFBS_HasNEON_HasFullFP16, // FMINNMVv4i16v = 1442 |
| CEFBS_HasNEON, // FMINNMVv4i32v = 1443 |
| CEFBS_HasNEON_HasFullFP16, // FMINNMVv8i16v = 1444 |
| CEFBS_HasSVE, // FMINNM_ZPmI_D = 1445 |
| CEFBS_HasSVE, // FMINNM_ZPmI_H = 1446 |
| CEFBS_HasSVE, // FMINNM_ZPmI_S = 1447 |
| CEFBS_HasSVE, // FMINNM_ZPmZ_D = 1448 |
| CEFBS_HasSVE, // FMINNM_ZPmZ_H = 1449 |
| CEFBS_HasSVE, // FMINNM_ZPmZ_S = 1450 |
| CEFBS_HasNEON, // FMINNMv2f32 = 1451 |
| CEFBS_HasNEON, // FMINNMv2f64 = 1452 |
| CEFBS_HasNEON_HasFullFP16, // FMINNMv4f16 = 1453 |
| CEFBS_HasNEON, // FMINNMv4f32 = 1454 |
| CEFBS_HasNEON_HasFullFP16, // FMINNMv8f16 = 1455 |
| CEFBS_HasSVE2, // FMINP_ZPmZZ_D = 1456 |
| CEFBS_HasSVE2, // FMINP_ZPmZZ_H = 1457 |
| CEFBS_HasSVE2, // FMINP_ZPmZZ_S = 1458 |
| CEFBS_HasNEON, // FMINPv2f32 = 1459 |
| CEFBS_HasNEON, // FMINPv2f64 = 1460 |
| CEFBS_HasNEON_HasFullFP16, // FMINPv2i16p = 1461 |
| CEFBS_HasNEON, // FMINPv2i32p = 1462 |
| CEFBS_HasNEON, // FMINPv2i64p = 1463 |
| CEFBS_HasNEON_HasFullFP16, // FMINPv4f16 = 1464 |
| CEFBS_HasNEON, // FMINPv4f32 = 1465 |
| CEFBS_HasNEON_HasFullFP16, // FMINPv8f16 = 1466 |
| CEFBS_HasFPARMv8, // FMINSrr = 1467 |
| CEFBS_HasSVE, // FMINV_VPZ_D = 1468 |
| CEFBS_HasSVE, // FMINV_VPZ_H = 1469 |
| CEFBS_HasSVE, // FMINV_VPZ_S = 1470 |
| CEFBS_HasNEON_HasFullFP16, // FMINVv4i16v = 1471 |
| CEFBS_HasNEON, // FMINVv4i32v = 1472 |
| CEFBS_HasNEON_HasFullFP16, // FMINVv8i16v = 1473 |
| CEFBS_HasSVE, // FMIN_ZPmI_D = 1474 |
| CEFBS_HasSVE, // FMIN_ZPmI_H = 1475 |
| CEFBS_HasSVE, // FMIN_ZPmI_S = 1476 |
| CEFBS_HasSVE, // FMIN_ZPmZ_D = 1477 |
| CEFBS_HasSVE, // FMIN_ZPmZ_H = 1478 |
| CEFBS_HasSVE, // FMIN_ZPmZ_S = 1479 |
| CEFBS_HasNEON, // FMINv2f32 = 1480 |
| CEFBS_HasNEON, // FMINv2f64 = 1481 |
| CEFBS_HasNEON_HasFullFP16, // FMINv4f16 = 1482 |
| CEFBS_HasNEON, // FMINv4f32 = 1483 |
| CEFBS_HasNEON_HasFullFP16, // FMINv8f16 = 1484 |
| CEFBS_HasNEON_HasFP16FML, // FMLAL2lanev4f16 = 1485 |
| CEFBS_HasNEON_HasFP16FML, // FMLAL2lanev8f16 = 1486 |
| CEFBS_HasNEON_HasFP16FML, // FMLAL2v4f16 = 1487 |
| CEFBS_HasNEON_HasFP16FML, // FMLAL2v8f16 = 1488 |
| CEFBS_HasSVE2, // FMLALB_ZZZI_SHH = 1489 |
| CEFBS_HasSVE2, // FMLALB_ZZZ_SHH = 1490 |
| CEFBS_HasSVE2, // FMLALT_ZZZI_SHH = 1491 |
| CEFBS_HasSVE2, // FMLALT_ZZZ_SHH = 1492 |
| CEFBS_HasNEON_HasFP16FML, // FMLALlanev4f16 = 1493 |
| CEFBS_HasNEON_HasFP16FML, // FMLALlanev8f16 = 1494 |
| CEFBS_HasNEON_HasFP16FML, // FMLALv4f16 = 1495 |
| CEFBS_HasNEON_HasFP16FML, // FMLALv8f16 = 1496 |
| CEFBS_HasSVE, // FMLA_ZPmZZ_D = 1497 |
| CEFBS_HasSVE, // FMLA_ZPmZZ_H = 1498 |
| CEFBS_HasSVE, // FMLA_ZPmZZ_S = 1499 |
| CEFBS_HasSVE, // FMLA_ZZZI_D = 1500 |
| CEFBS_HasSVE, // FMLA_ZZZI_H = 1501 |
| CEFBS_HasSVE, // FMLA_ZZZI_S = 1502 |
| CEFBS_HasNEON_HasFullFP16, // FMLAv1i16_indexed = 1503 |
| CEFBS_HasNEON, // FMLAv1i32_indexed = 1504 |
| CEFBS_HasNEON, // FMLAv1i64_indexed = 1505 |
| CEFBS_HasNEON, // FMLAv2f32 = 1506 |
| CEFBS_HasNEON, // FMLAv2f64 = 1507 |
| CEFBS_HasNEON, // FMLAv2i32_indexed = 1508 |
| CEFBS_HasNEON, // FMLAv2i64_indexed = 1509 |
| CEFBS_HasNEON_HasFullFP16, // FMLAv4f16 = 1510 |
| CEFBS_HasNEON, // FMLAv4f32 = 1511 |
| CEFBS_HasNEON_HasFullFP16, // FMLAv4i16_indexed = 1512 |
| CEFBS_HasNEON, // FMLAv4i32_indexed = 1513 |
| CEFBS_HasNEON_HasFullFP16, // FMLAv8f16 = 1514 |
| CEFBS_HasNEON_HasFullFP16, // FMLAv8i16_indexed = 1515 |
| CEFBS_HasNEON_HasFP16FML, // FMLSL2lanev4f16 = 1516 |
| CEFBS_HasNEON_HasFP16FML, // FMLSL2lanev8f16 = 1517 |
| CEFBS_HasNEON_HasFP16FML, // FMLSL2v4f16 = 1518 |
| CEFBS_HasNEON_HasFP16FML, // FMLSL2v8f16 = 1519 |
| CEFBS_HasSVE2, // FMLSLB_ZZZI_SHH = 1520 |
| CEFBS_HasSVE2, // FMLSLB_ZZZ_SHH = 1521 |
| CEFBS_HasSVE2, // FMLSLT_ZZZI_SHH = 1522 |
| CEFBS_HasSVE2, // FMLSLT_ZZZ_SHH = 1523 |
| CEFBS_HasNEON_HasFP16FML, // FMLSLlanev4f16 = 1524 |
| CEFBS_HasNEON_HasFP16FML, // FMLSLlanev8f16 = 1525 |
| CEFBS_HasNEON_HasFP16FML, // FMLSLv4f16 = 1526 |
| CEFBS_HasNEON_HasFP16FML, // FMLSLv8f16 = 1527 |
| CEFBS_HasSVE, // FMLS_ZPmZZ_D = 1528 |
| CEFBS_HasSVE, // FMLS_ZPmZZ_H = 1529 |
| CEFBS_HasSVE, // FMLS_ZPmZZ_S = 1530 |
| CEFBS_HasSVE, // FMLS_ZZZI_D = 1531 |
| CEFBS_HasSVE, // FMLS_ZZZI_H = 1532 |
| CEFBS_HasSVE, // FMLS_ZZZI_S = 1533 |
| CEFBS_HasNEON_HasFullFP16, // FMLSv1i16_indexed = 1534 |
| CEFBS_HasNEON, // FMLSv1i32_indexed = 1535 |
| CEFBS_HasNEON, // FMLSv1i64_indexed = 1536 |
| CEFBS_HasNEON, // FMLSv2f32 = 1537 |
| CEFBS_HasNEON, // FMLSv2f64 = 1538 |
| CEFBS_HasNEON, // FMLSv2i32_indexed = 1539 |
| CEFBS_HasNEON, // FMLSv2i64_indexed = 1540 |
| CEFBS_HasNEON_HasFullFP16, // FMLSv4f16 = 1541 |
| CEFBS_HasNEON, // FMLSv4f32 = 1542 |
| CEFBS_HasNEON_HasFullFP16, // FMLSv4i16_indexed = 1543 |
| CEFBS_HasNEON, // FMLSv4i32_indexed = 1544 |
| CEFBS_HasNEON_HasFullFP16, // FMLSv8f16 = 1545 |
| CEFBS_HasNEON_HasFullFP16, // FMLSv8i16_indexed = 1546 |
| CEFBS_None, // FMOVD0 = 1547 |
| CEFBS_HasFPARMv8, // FMOVDXHighr = 1548 |
| CEFBS_HasFPARMv8, // FMOVDXr = 1549 |
| CEFBS_HasFPARMv8, // FMOVDi = 1550 |
| CEFBS_HasFPARMv8, // FMOVDr = 1551 |
| CEFBS_HasFullFP16, // FMOVH0 = 1552 |
| CEFBS_HasFullFP16, // FMOVHWr = 1553 |
| CEFBS_HasFullFP16, // FMOVHXr = 1554 |
| CEFBS_HasFullFP16, // FMOVHi = 1555 |
| CEFBS_HasFullFP16, // FMOVHr = 1556 |
| CEFBS_None, // FMOVS0 = 1557 |
| CEFBS_HasFPARMv8, // FMOVSWr = 1558 |
| CEFBS_HasFPARMv8, // FMOVSi = 1559 |
| CEFBS_HasFPARMv8, // FMOVSr = 1560 |
| CEFBS_HasFullFP16, // FMOVWHr = 1561 |
| CEFBS_HasFPARMv8, // FMOVWSr = 1562 |
| CEFBS_HasFPARMv8, // FMOVXDHighr = 1563 |
| CEFBS_HasFPARMv8, // FMOVXDr = 1564 |
| CEFBS_HasFullFP16, // FMOVXHr = 1565 |
| CEFBS_HasNEON, // FMOVv2f32_ns = 1566 |
| CEFBS_HasNEON, // FMOVv2f64_ns = 1567 |
| CEFBS_HasNEON_HasFullFP16, // FMOVv4f16_ns = 1568 |
| CEFBS_HasNEON, // FMOVv4f32_ns = 1569 |
| CEFBS_HasNEON_HasFullFP16, // FMOVv8f16_ns = 1570 |
| CEFBS_HasSVE, // FMSB_ZPmZZ_D = 1571 |
| CEFBS_HasSVE, // FMSB_ZPmZZ_H = 1572 |
| CEFBS_HasSVE, // FMSB_ZPmZZ_S = 1573 |
| CEFBS_HasFPARMv8, // FMSUBDrrr = 1574 |
| CEFBS_HasFullFP16, // FMSUBHrrr = 1575 |
| CEFBS_HasFPARMv8, // FMSUBSrrr = 1576 |
| CEFBS_HasFPARMv8, // FMULDrr = 1577 |
| CEFBS_HasFullFP16, // FMULHrr = 1578 |
| CEFBS_HasFPARMv8, // FMULSrr = 1579 |
| CEFBS_HasNEON_HasFullFP16, // FMULX16 = 1580 |
| CEFBS_HasNEON, // FMULX32 = 1581 |
| CEFBS_HasNEON, // FMULX64 = 1582 |
| CEFBS_HasSVE, // FMULX_ZPmZ_D = 1583 |
| CEFBS_HasSVE, // FMULX_ZPmZ_H = 1584 |
| CEFBS_HasSVE, // FMULX_ZPmZ_S = 1585 |
| CEFBS_HasNEON_HasFullFP16, // FMULXv1i16_indexed = 1586 |
| CEFBS_HasNEON, // FMULXv1i32_indexed = 1587 |
| CEFBS_HasNEON, // FMULXv1i64_indexed = 1588 |
| CEFBS_HasNEON, // FMULXv2f32 = 1589 |
| CEFBS_HasNEON, // FMULXv2f64 = 1590 |
| CEFBS_HasNEON, // FMULXv2i32_indexed = 1591 |
| CEFBS_HasNEON, // FMULXv2i64_indexed = 1592 |
| CEFBS_HasNEON_HasFullFP16, // FMULXv4f16 = 1593 |
| CEFBS_HasNEON, // FMULXv4f32 = 1594 |
| CEFBS_HasNEON_HasFullFP16, // FMULXv4i16_indexed = 1595 |
| CEFBS_HasNEON, // FMULXv4i32_indexed = 1596 |
| CEFBS_HasNEON_HasFullFP16, // FMULXv8f16 = 1597 |
| CEFBS_HasNEON_HasFullFP16, // FMULXv8i16_indexed = 1598 |
| CEFBS_HasSVE, // FMUL_ZPmI_D = 1599 |
| CEFBS_HasSVE, // FMUL_ZPmI_H = 1600 |
| CEFBS_HasSVE, // FMUL_ZPmI_S = 1601 |
| CEFBS_HasSVE, // FMUL_ZPmZ_D = 1602 |
| CEFBS_HasSVE, // FMUL_ZPmZ_H = 1603 |
| CEFBS_HasSVE, // FMUL_ZPmZ_S = 1604 |
| CEFBS_HasSVE, // FMUL_ZZZI_D = 1605 |
| CEFBS_HasSVE, // FMUL_ZZZI_H = 1606 |
| CEFBS_HasSVE, // FMUL_ZZZI_S = 1607 |
| CEFBS_HasSVE, // FMUL_ZZZ_D = 1608 |
| CEFBS_HasSVE, // FMUL_ZZZ_H = 1609 |
| CEFBS_HasSVE, // FMUL_ZZZ_S = 1610 |
| CEFBS_HasNEON_HasFullFP16, // FMULv1i16_indexed = 1611 |
| CEFBS_HasNEON, // FMULv1i32_indexed = 1612 |
| CEFBS_HasNEON, // FMULv1i64_indexed = 1613 |
| CEFBS_HasNEON, // FMULv2f32 = 1614 |
| CEFBS_HasNEON, // FMULv2f64 = 1615 |
| CEFBS_HasNEON, // FMULv2i32_indexed = 1616 |
| CEFBS_HasNEON, // FMULv2i64_indexed = 1617 |
| CEFBS_HasNEON_HasFullFP16, // FMULv4f16 = 1618 |
| CEFBS_HasNEON, // FMULv4f32 = 1619 |
| CEFBS_HasNEON_HasFullFP16, // FMULv4i16_indexed = 1620 |
| CEFBS_HasNEON, // FMULv4i32_indexed = 1621 |
| CEFBS_HasNEON_HasFullFP16, // FMULv8f16 = 1622 |
| CEFBS_HasNEON_HasFullFP16, // FMULv8i16_indexed = 1623 |
| CEFBS_HasFPARMv8, // FNEGDr = 1624 |
| CEFBS_HasFullFP16, // FNEGHr = 1625 |
| CEFBS_HasFPARMv8, // FNEGSr = 1626 |
| CEFBS_HasSVE, // FNEG_ZPmZ_D = 1627 |
| CEFBS_HasSVE, // FNEG_ZPmZ_H = 1628 |
| CEFBS_HasSVE, // FNEG_ZPmZ_S = 1629 |
| CEFBS_HasNEON, // FNEGv2f32 = 1630 |
| CEFBS_HasNEON, // FNEGv2f64 = 1631 |
| CEFBS_HasNEON_HasFullFP16, // FNEGv4f16 = 1632 |
| CEFBS_HasNEON, // FNEGv4f32 = 1633 |
| CEFBS_HasNEON_HasFullFP16, // FNEGv8f16 = 1634 |
| CEFBS_HasFPARMv8, // FNMADDDrrr = 1635 |
| CEFBS_HasFullFP16, // FNMADDHrrr = 1636 |
| CEFBS_HasFPARMv8, // FNMADDSrrr = 1637 |
| CEFBS_HasSVE, // FNMAD_ZPmZZ_D = 1638 |
| CEFBS_HasSVE, // FNMAD_ZPmZZ_H = 1639 |
| CEFBS_HasSVE, // FNMAD_ZPmZZ_S = 1640 |
| CEFBS_HasSVE, // FNMLA_ZPmZZ_D = 1641 |
| CEFBS_HasSVE, // FNMLA_ZPmZZ_H = 1642 |
| CEFBS_HasSVE, // FNMLA_ZPmZZ_S = 1643 |
| CEFBS_HasSVE, // FNMLS_ZPmZZ_D = 1644 |
| CEFBS_HasSVE, // FNMLS_ZPmZZ_H = 1645 |
| CEFBS_HasSVE, // FNMLS_ZPmZZ_S = 1646 |
| CEFBS_HasSVE, // FNMSB_ZPmZZ_D = 1647 |
| CEFBS_HasSVE, // FNMSB_ZPmZZ_H = 1648 |
| CEFBS_HasSVE, // FNMSB_ZPmZZ_S = 1649 |
| CEFBS_HasFPARMv8, // FNMSUBDrrr = 1650 |
| CEFBS_HasFullFP16, // FNMSUBHrrr = 1651 |
| CEFBS_HasFPARMv8, // FNMSUBSrrr = 1652 |
| CEFBS_HasFPARMv8, // FNMULDrr = 1653 |
| CEFBS_HasFullFP16, // FNMULHrr = 1654 |
| CEFBS_HasFPARMv8, // FNMULSrr = 1655 |
| CEFBS_HasSVE, // FRECPE_ZZ_D = 1656 |
| CEFBS_HasSVE, // FRECPE_ZZ_H = 1657 |
| CEFBS_HasSVE, // FRECPE_ZZ_S = 1658 |
| CEFBS_HasNEON_HasFullFP16, // FRECPEv1f16 = 1659 |
| CEFBS_HasNEON, // FRECPEv1i32 = 1660 |
| CEFBS_HasNEON, // FRECPEv1i64 = 1661 |
| CEFBS_HasNEON, // FRECPEv2f32 = 1662 |
| CEFBS_HasNEON, // FRECPEv2f64 = 1663 |
| CEFBS_HasNEON_HasFullFP16, // FRECPEv4f16 = 1664 |
| CEFBS_HasNEON, // FRECPEv4f32 = 1665 |
| CEFBS_HasNEON_HasFullFP16, // FRECPEv8f16 = 1666 |
| CEFBS_HasNEON_HasFullFP16, // FRECPS16 = 1667 |
| CEFBS_HasNEON, // FRECPS32 = 1668 |
| CEFBS_HasNEON, // FRECPS64 = 1669 |
| CEFBS_HasSVE, // FRECPS_ZZZ_D = 1670 |
| CEFBS_HasSVE, // FRECPS_ZZZ_H = 1671 |
| CEFBS_HasSVE, // FRECPS_ZZZ_S = 1672 |
| CEFBS_HasNEON, // FRECPSv2f32 = 1673 |
| CEFBS_HasNEON, // FRECPSv2f64 = 1674 |
| CEFBS_HasNEON_HasFullFP16, // FRECPSv4f16 = 1675 |
| CEFBS_HasNEON, // FRECPSv4f32 = 1676 |
| CEFBS_HasNEON_HasFullFP16, // FRECPSv8f16 = 1677 |
| CEFBS_HasSVE, // FRECPX_ZPmZ_D = 1678 |
| CEFBS_HasSVE, // FRECPX_ZPmZ_H = 1679 |
| CEFBS_HasSVE, // FRECPX_ZPmZ_S = 1680 |
| CEFBS_HasNEON_HasFullFP16, // FRECPXv1f16 = 1681 |
| CEFBS_HasNEON, // FRECPXv1i32 = 1682 |
| CEFBS_HasNEON, // FRECPXv1i64 = 1683 |
| CEFBS_HasFRInt3264, // FRINT32XDr = 1684 |
| CEFBS_HasFRInt3264, // FRINT32XSr = 1685 |
| CEFBS_HasFRInt3264, // FRINT32Xv2f32 = 1686 |
| CEFBS_HasFRInt3264, // FRINT32Xv2f64 = 1687 |
| CEFBS_HasFRInt3264, // FRINT32Xv4f32 = 1688 |
| CEFBS_HasFRInt3264, // FRINT32ZDr = 1689 |
| CEFBS_HasFRInt3264, // FRINT32ZSr = 1690 |
| CEFBS_HasFRInt3264, // FRINT32Zv2f32 = 1691 |
| CEFBS_HasFRInt3264, // FRINT32Zv2f64 = 1692 |
| CEFBS_HasFRInt3264, // FRINT32Zv4f32 = 1693 |
| CEFBS_HasFRInt3264, // FRINT64XDr = 1694 |
| CEFBS_HasFRInt3264, // FRINT64XSr = 1695 |
| CEFBS_HasFRInt3264, // FRINT64Xv2f32 = 1696 |
| CEFBS_HasFRInt3264, // FRINT64Xv2f64 = 1697 |
| CEFBS_HasFRInt3264, // FRINT64Xv4f32 = 1698 |
| CEFBS_HasFRInt3264, // FRINT64ZDr = 1699 |
| CEFBS_HasFRInt3264, // FRINT64ZSr = 1700 |
| CEFBS_HasFRInt3264, // FRINT64Zv2f32 = 1701 |
| CEFBS_HasFRInt3264, // FRINT64Zv2f64 = 1702 |
| CEFBS_HasFRInt3264, // FRINT64Zv4f32 = 1703 |
| CEFBS_HasFPARMv8, // FRINTADr = 1704 |
| CEFBS_HasFullFP16, // FRINTAHr = 1705 |
| CEFBS_HasFPARMv8, // FRINTASr = 1706 |
| CEFBS_HasSVE, // FRINTA_ZPmZ_D = 1707 |
| CEFBS_HasSVE, // FRINTA_ZPmZ_H = 1708 |
| CEFBS_HasSVE, // FRINTA_ZPmZ_S = 1709 |
| CEFBS_HasNEON, // FRINTAv2f32 = 1710 |
| CEFBS_HasNEON, // FRINTAv2f64 = 1711 |
| CEFBS_HasNEON_HasFullFP16, // FRINTAv4f16 = 1712 |
| CEFBS_HasNEON, // FRINTAv4f32 = 1713 |
| CEFBS_HasNEON_HasFullFP16, // FRINTAv8f16 = 1714 |
| CEFBS_HasFPARMv8, // FRINTIDr = 1715 |
| CEFBS_HasFullFP16, // FRINTIHr = 1716 |
| CEFBS_HasFPARMv8, // FRINTISr = 1717 |
| CEFBS_HasSVE, // FRINTI_ZPmZ_D = 1718 |
| CEFBS_HasSVE, // FRINTI_ZPmZ_H = 1719 |
| CEFBS_HasSVE, // FRINTI_ZPmZ_S = 1720 |
| CEFBS_HasNEON, // FRINTIv2f32 = 1721 |
| CEFBS_HasNEON, // FRINTIv2f64 = 1722 |
| CEFBS_HasNEON_HasFullFP16, // FRINTIv4f16 = 1723 |
| CEFBS_HasNEON, // FRINTIv4f32 = 1724 |
| CEFBS_HasNEON_HasFullFP16, // FRINTIv8f16 = 1725 |
| CEFBS_HasFPARMv8, // FRINTMDr = 1726 |
| CEFBS_HasFullFP16, // FRINTMHr = 1727 |
| CEFBS_HasFPARMv8, // FRINTMSr = 1728 |
| CEFBS_HasSVE, // FRINTM_ZPmZ_D = 1729 |
| CEFBS_HasSVE, // FRINTM_ZPmZ_H = 1730 |
| CEFBS_HasSVE, // FRINTM_ZPmZ_S = 1731 |
| CEFBS_HasNEON, // FRINTMv2f32 = 1732 |
| CEFBS_HasNEON, // FRINTMv2f64 = 1733 |
| CEFBS_HasNEON_HasFullFP16, // FRINTMv4f16 = 1734 |
| CEFBS_HasNEON, // FRINTMv4f32 = 1735 |
| CEFBS_HasNEON_HasFullFP16, // FRINTMv8f16 = 1736 |
| CEFBS_HasFPARMv8, // FRINTNDr = 1737 |
| CEFBS_HasFullFP16, // FRINTNHr = 1738 |
| CEFBS_HasFPARMv8, // FRINTNSr = 1739 |
| CEFBS_HasSVE, // FRINTN_ZPmZ_D = 1740 |
| CEFBS_HasSVE, // FRINTN_ZPmZ_H = 1741 |
| CEFBS_HasSVE, // FRINTN_ZPmZ_S = 1742 |
| CEFBS_HasNEON, // FRINTNv2f32 = 1743 |
| CEFBS_HasNEON, // FRINTNv2f64 = 1744 |
| CEFBS_HasNEON_HasFullFP16, // FRINTNv4f16 = 1745 |
| CEFBS_HasNEON, // FRINTNv4f32 = 1746 |
| CEFBS_HasNEON_HasFullFP16, // FRINTNv8f16 = 1747 |
| CEFBS_HasFPARMv8, // FRINTPDr = 1748 |
| CEFBS_HasFullFP16, // FRINTPHr = 1749 |
| CEFBS_HasFPARMv8, // FRINTPSr = 1750 |
| CEFBS_HasSVE, // FRINTP_ZPmZ_D = 1751 |
| CEFBS_HasSVE, // FRINTP_ZPmZ_H = 1752 |
| CEFBS_HasSVE, // FRINTP_ZPmZ_S = 1753 |
| CEFBS_HasNEON, // FRINTPv2f32 = 1754 |
| CEFBS_HasNEON, // FRINTPv2f64 = 1755 |
| CEFBS_HasNEON_HasFullFP16, // FRINTPv4f16 = 1756 |
| CEFBS_HasNEON, // FRINTPv4f32 = 1757 |
| CEFBS_HasNEON_HasFullFP16, // FRINTPv8f16 = 1758 |
| CEFBS_HasFPARMv8, // FRINTXDr = 1759 |
| CEFBS_HasFullFP16, // FRINTXHr = 1760 |
| CEFBS_HasFPARMv8, // FRINTXSr = 1761 |
| CEFBS_HasSVE, // FRINTX_ZPmZ_D = 1762 |
| CEFBS_HasSVE, // FRINTX_ZPmZ_H = 1763 |
| CEFBS_HasSVE, // FRINTX_ZPmZ_S = 1764 |
| CEFBS_HasNEON, // FRINTXv2f32 = 1765 |
| CEFBS_HasNEON, // FRINTXv2f64 = 1766 |
| CEFBS_HasNEON_HasFullFP16, // FRINTXv4f16 = 1767 |
| CEFBS_HasNEON, // FRINTXv4f32 = 1768 |
| CEFBS_HasNEON_HasFullFP16, // FRINTXv8f16 = 1769 |
| CEFBS_HasFPARMv8, // FRINTZDr = 1770 |
| CEFBS_HasFullFP16, // FRINTZHr = 1771 |
| CEFBS_HasFPARMv8, // FRINTZSr = 1772 |
| CEFBS_HasSVE, // FRINTZ_ZPmZ_D = 1773 |
| CEFBS_HasSVE, // FRINTZ_ZPmZ_H = 1774 |
| CEFBS_HasSVE, // FRINTZ_ZPmZ_S = 1775 |
| CEFBS_HasNEON, // FRINTZv2f32 = 1776 |
| CEFBS_HasNEON, // FRINTZv2f64 = 1777 |
| CEFBS_HasNEON_HasFullFP16, // FRINTZv4f16 = 1778 |
| CEFBS_HasNEON, // FRINTZv4f32 = 1779 |
| CEFBS_HasNEON_HasFullFP16, // FRINTZv8f16 = 1780 |
| CEFBS_HasSVE, // FRSQRTE_ZZ_D = 1781 |
| CEFBS_HasSVE, // FRSQRTE_ZZ_H = 1782 |
| CEFBS_HasSVE, // FRSQRTE_ZZ_S = 1783 |
| CEFBS_HasNEON_HasFullFP16, // FRSQRTEv1f16 = 1784 |
| CEFBS_HasNEON, // FRSQRTEv1i32 = 1785 |
| CEFBS_HasNEON, // FRSQRTEv1i64 = 1786 |
| CEFBS_HasNEON, // FRSQRTEv2f32 = 1787 |
| CEFBS_HasNEON, // FRSQRTEv2f64 = 1788 |
| CEFBS_HasNEON_HasFullFP16, // FRSQRTEv4f16 = 1789 |
| CEFBS_HasNEON, // FRSQRTEv4f32 = 1790 |
| CEFBS_HasNEON_HasFullFP16, // FRSQRTEv8f16 = 1791 |
| CEFBS_HasNEON_HasFullFP16, // FRSQRTS16 = 1792 |
| CEFBS_HasNEON, // FRSQRTS32 = 1793 |
| CEFBS_HasNEON, // FRSQRTS64 = 1794 |
| CEFBS_HasSVE, // FRSQRTS_ZZZ_D = 1795 |
| CEFBS_HasSVE, // FRSQRTS_ZZZ_H = 1796 |
| CEFBS_HasSVE, // FRSQRTS_ZZZ_S = 1797 |
| CEFBS_HasNEON, // FRSQRTSv2f32 = 1798 |
| CEFBS_HasNEON, // FRSQRTSv2f64 = 1799 |
| CEFBS_HasNEON_HasFullFP16, // FRSQRTSv4f16 = 1800 |
| CEFBS_HasNEON, // FRSQRTSv4f32 = 1801 |
| CEFBS_HasNEON_HasFullFP16, // FRSQRTSv8f16 = 1802 |
| CEFBS_HasSVE, // FSCALE_ZPmZ_D = 1803 |
| CEFBS_HasSVE, // FSCALE_ZPmZ_H = 1804 |
| CEFBS_HasSVE, // FSCALE_ZPmZ_S = 1805 |
| CEFBS_HasFPARMv8, // FSQRTDr = 1806 |
| CEFBS_HasFullFP16, // FSQRTHr = 1807 |
| CEFBS_HasFPARMv8, // FSQRTSr = 1808 |
| CEFBS_HasSVE, // FSQRT_ZPmZ_D = 1809 |
| CEFBS_HasSVE, // FSQRT_ZPmZ_H = 1810 |
| CEFBS_HasSVE, // FSQRT_ZPmZ_S = 1811 |
| CEFBS_HasNEON, // FSQRTv2f32 = 1812 |
| CEFBS_HasNEON, // FSQRTv2f64 = 1813 |
| CEFBS_HasNEON_HasFullFP16, // FSQRTv4f16 = 1814 |
| CEFBS_HasNEON, // FSQRTv4f32 = 1815 |
| CEFBS_HasNEON_HasFullFP16, // FSQRTv8f16 = 1816 |
| CEFBS_HasFPARMv8, // FSUBDrr = 1817 |
| CEFBS_HasFullFP16, // FSUBHrr = 1818 |
| CEFBS_HasSVE, // FSUBR_ZPmI_D = 1819 |
| CEFBS_HasSVE, // FSUBR_ZPmI_H = 1820 |
| CEFBS_HasSVE, // FSUBR_ZPmI_S = 1821 |
| CEFBS_HasSVE, // FSUBR_ZPmZ_D = 1822 |
| CEFBS_HasSVE, // FSUBR_ZPmZ_H = 1823 |
| CEFBS_HasSVE, // FSUBR_ZPmZ_S = 1824 |
| CEFBS_HasFPARMv8, // FSUBSrr = 1825 |
| CEFBS_HasSVE, // FSUB_ZPmI_D = 1826 |
| CEFBS_HasSVE, // FSUB_ZPmI_H = 1827 |
| CEFBS_HasSVE, // FSUB_ZPmI_S = 1828 |
| CEFBS_HasSVE, // FSUB_ZPmZ_D = 1829 |
| CEFBS_HasSVE, // FSUB_ZPmZ_H = 1830 |
| CEFBS_HasSVE, // FSUB_ZPmZ_S = 1831 |
| CEFBS_HasSVE, // FSUB_ZZZ_D = 1832 |
| CEFBS_HasSVE, // FSUB_ZZZ_H = 1833 |
| CEFBS_HasSVE, // FSUB_ZZZ_S = 1834 |
| CEFBS_HasNEON, // FSUBv2f32 = 1835 |
| CEFBS_HasNEON, // FSUBv2f64 = 1836 |
| CEFBS_HasNEON_HasFullFP16, // FSUBv4f16 = 1837 |
| CEFBS_HasNEON, // FSUBv4f32 = 1838 |
| CEFBS_HasNEON_HasFullFP16, // FSUBv8f16 = 1839 |
| CEFBS_HasSVE, // FTMAD_ZZI_D = 1840 |
| CEFBS_HasSVE, // FTMAD_ZZI_H = 1841 |
| CEFBS_HasSVE, // FTMAD_ZZI_S = 1842 |
| CEFBS_HasSVE, // FTSMUL_ZZZ_D = 1843 |
| CEFBS_HasSVE, // FTSMUL_ZZZ_H = 1844 |
| CEFBS_HasSVE, // FTSMUL_ZZZ_S = 1845 |
| CEFBS_HasSVE, // FTSSEL_ZZZ_D = 1846 |
| CEFBS_HasSVE, // FTSSEL_ZZZ_H = 1847 |
| CEFBS_HasSVE, // FTSSEL_ZZZ_S = 1848 |
| CEFBS_HasSVE, // GLD1B_D_IMM_REAL = 1849 |
| CEFBS_HasSVE, // GLD1B_D_REAL = 1850 |
| CEFBS_HasSVE, // GLD1B_D_SXTW_REAL = 1851 |
| CEFBS_HasSVE, // GLD1B_D_UXTW_REAL = 1852 |
| CEFBS_HasSVE, // GLD1B_S_IMM_REAL = 1853 |
| CEFBS_HasSVE, // GLD1B_S_SXTW_REAL = 1854 |
| CEFBS_HasSVE, // GLD1B_S_UXTW_REAL = 1855 |
| CEFBS_HasSVE, // GLD1D_IMM_REAL = 1856 |
| CEFBS_HasSVE, // GLD1D_REAL = 1857 |
| CEFBS_HasSVE, // GLD1D_SCALED_REAL = 1858 |
| CEFBS_HasSVE, // GLD1D_SXTW_REAL = 1859 |
| CEFBS_HasSVE, // GLD1D_SXTW_SCALED_REAL = 1860 |
| CEFBS_HasSVE, // GLD1D_UXTW_REAL = 1861 |
| CEFBS_HasSVE, // GLD1D_UXTW_SCALED_REAL = 1862 |
| CEFBS_HasSVE, // GLD1H_D_IMM_REAL = 1863 |
| CEFBS_HasSVE, // GLD1H_D_REAL = 1864 |
| CEFBS_HasSVE, // GLD1H_D_SCALED_REAL = 1865 |
| CEFBS_HasSVE, // GLD1H_D_SXTW_REAL = 1866 |
| CEFBS_HasSVE, // GLD1H_D_SXTW_SCALED_REAL = 1867 |
| CEFBS_HasSVE, // GLD1H_D_UXTW_REAL = 1868 |
| CEFBS_HasSVE, // GLD1H_D_UXTW_SCALED_REAL = 1869 |
| CEFBS_HasSVE, // GLD1H_S_IMM_REAL = 1870 |
| CEFBS_HasSVE, // GLD1H_S_SXTW_REAL = 1871 |
| CEFBS_HasSVE, // GLD1H_S_SXTW_SCALED_REAL = 1872 |
| CEFBS_HasSVE, // GLD1H_S_UXTW_REAL = 1873 |
| CEFBS_HasSVE, // GLD1H_S_UXTW_SCALED_REAL = 1874 |
| CEFBS_HasSVE, // GLD1SB_D_IMM_REAL = 1875 |
| CEFBS_HasSVE, // GLD1SB_D_REAL = 1876 |
| CEFBS_HasSVE, // GLD1SB_D_SXTW_REAL = 1877 |
| CEFBS_HasSVE, // GLD1SB_D_UXTW_REAL = 1878 |
| CEFBS_HasSVE, // GLD1SB_S_IMM_REAL = 1879 |
| CEFBS_HasSVE, // GLD1SB_S_SXTW_REAL = 1880 |
| CEFBS_HasSVE, // GLD1SB_S_UXTW_REAL = 1881 |
| CEFBS_HasSVE, // GLD1SH_D_IMM_REAL = 1882 |
| CEFBS_HasSVE, // GLD1SH_D_REAL = 1883 |
| CEFBS_HasSVE, // GLD1SH_D_SCALED_REAL = 1884 |
| CEFBS_HasSVE, // GLD1SH_D_SXTW_REAL = 1885 |
| CEFBS_HasSVE, // GLD1SH_D_SXTW_SCALED_REAL = 1886 |
| CEFBS_HasSVE, // GLD1SH_D_UXTW_REAL = 1887 |
| CEFBS_HasSVE, // GLD1SH_D_UXTW_SCALED_REAL = 1888 |
| CEFBS_HasSVE, // GLD1SH_S_IMM_REAL = 1889 |
| CEFBS_HasSVE, // GLD1SH_S_SXTW_REAL = 1890 |
| CEFBS_HasSVE, // GLD1SH_S_SXTW_SCALED_REAL = 1891 |
| CEFBS_HasSVE, // GLD1SH_S_UXTW_REAL = 1892 |
| CEFBS_HasSVE, // GLD1SH_S_UXTW_SCALED_REAL = 1893 |
| CEFBS_HasSVE, // GLD1SW_D_IMM_REAL = 1894 |
| CEFBS_HasSVE, // GLD1SW_D_REAL = 1895 |
| CEFBS_HasSVE, // GLD1SW_D_SCALED_REAL = 1896 |
| CEFBS_HasSVE, // GLD1SW_D_SXTW_REAL = 1897 |
| CEFBS_HasSVE, // GLD1SW_D_SXTW_SCALED_REAL = 1898 |
| CEFBS_HasSVE, // GLD1SW_D_UXTW_REAL = 1899 |
| CEFBS_HasSVE, // GLD1SW_D_UXTW_SCALED_REAL = 1900 |
| CEFBS_HasSVE, // GLD1W_D_IMM_REAL = 1901 |
| CEFBS_HasSVE, // GLD1W_D_REAL = 1902 |
| CEFBS_HasSVE, // GLD1W_D_SCALED_REAL = 1903 |
| CEFBS_HasSVE, // GLD1W_D_SXTW_REAL = 1904 |
| CEFBS_HasSVE, // GLD1W_D_SXTW_SCALED_REAL = 1905 |
| CEFBS_HasSVE, // GLD1W_D_UXTW_REAL = 1906 |
| CEFBS_HasSVE, // GLD1W_D_UXTW_SCALED_REAL = 1907 |
| CEFBS_HasSVE, // GLD1W_IMM_REAL = 1908 |
| CEFBS_HasSVE, // GLD1W_SXTW_REAL = 1909 |
| CEFBS_HasSVE, // GLD1W_SXTW_SCALED_REAL = 1910 |
| CEFBS_HasSVE, // GLD1W_UXTW_REAL = 1911 |
| CEFBS_HasSVE, // GLD1W_UXTW_SCALED_REAL = 1912 |
| CEFBS_HasSVE, // GLDFF1B_D_IMM_REAL = 1913 |
| CEFBS_HasSVE, // GLDFF1B_D_REAL = 1914 |
| CEFBS_HasSVE, // GLDFF1B_D_SXTW_REAL = 1915 |
| CEFBS_HasSVE, // GLDFF1B_D_UXTW_REAL = 1916 |
| CEFBS_HasSVE, // GLDFF1B_S_IMM_REAL = 1917 |
| CEFBS_HasSVE, // GLDFF1B_S_SXTW_REAL = 1918 |
| CEFBS_HasSVE, // GLDFF1B_S_UXTW_REAL = 1919 |
| CEFBS_HasSVE, // GLDFF1D_IMM_REAL = 1920 |
| CEFBS_HasSVE, // GLDFF1D_REAL = 1921 |
| CEFBS_HasSVE, // GLDFF1D_SCALED_REAL = 1922 |
| CEFBS_HasSVE, // GLDFF1D_SXTW_REAL = 1923 |
| CEFBS_HasSVE, // GLDFF1D_SXTW_SCALED_REAL = 1924 |
| CEFBS_HasSVE, // GLDFF1D_UXTW_REAL = 1925 |
| CEFBS_HasSVE, // GLDFF1D_UXTW_SCALED_REAL = 1926 |
| CEFBS_HasSVE, // GLDFF1H_D_IMM_REAL = 1927 |
| CEFBS_HasSVE, // GLDFF1H_D_REAL = 1928 |
| CEFBS_HasSVE, // GLDFF1H_D_SCALED_REAL = 1929 |
| CEFBS_HasSVE, // GLDFF1H_D_SXTW_REAL = 1930 |
| CEFBS_HasSVE, // GLDFF1H_D_SXTW_SCALED_REAL = 1931 |
| CEFBS_HasSVE, // GLDFF1H_D_UXTW_REAL = 1932 |
| CEFBS_HasSVE, // GLDFF1H_D_UXTW_SCALED_REAL = 1933 |
| CEFBS_HasSVE, // GLDFF1H_S_IMM_REAL = 1934 |
| CEFBS_HasSVE, // GLDFF1H_S_SXTW_REAL = 1935 |
| CEFBS_HasSVE, // GLDFF1H_S_SXTW_SCALED_REAL = 1936 |
| CEFBS_HasSVE, // GLDFF1H_S_UXTW_REAL = 1937 |
| CEFBS_HasSVE, // GLDFF1H_S_UXTW_SCALED_REAL = 1938 |
| CEFBS_HasSVE, // GLDFF1SB_D_IMM_REAL = 1939 |
| CEFBS_HasSVE, // GLDFF1SB_D_REAL = 1940 |
| CEFBS_HasSVE, // GLDFF1SB_D_SXTW_REAL = 1941 |
| CEFBS_HasSVE, // GLDFF1SB_D_UXTW_REAL = 1942 |
| CEFBS_HasSVE, // GLDFF1SB_S_IMM_REAL = 1943 |
| CEFBS_HasSVE, // GLDFF1SB_S_SXTW_REAL = 1944 |
| CEFBS_HasSVE, // GLDFF1SB_S_UXTW_REAL = 1945 |
| CEFBS_HasSVE, // GLDFF1SH_D_IMM_REAL = 1946 |
| CEFBS_HasSVE, // GLDFF1SH_D_REAL = 1947 |
| CEFBS_HasSVE, // GLDFF1SH_D_SCALED_REAL = 1948 |
| CEFBS_HasSVE, // GLDFF1SH_D_SXTW_REAL = 1949 |
| CEFBS_HasSVE, // GLDFF1SH_D_SXTW_SCALED_REAL = 1950 |
| CEFBS_HasSVE, // GLDFF1SH_D_UXTW_REAL = 1951 |
| CEFBS_HasSVE, // GLDFF1SH_D_UXTW_SCALED_REAL = 1952 |
| CEFBS_HasSVE, // GLDFF1SH_S_IMM_REAL = 1953 |
| CEFBS_HasSVE, // GLDFF1SH_S_SXTW_REAL = 1954 |
| CEFBS_HasSVE, // GLDFF1SH_S_SXTW_SCALED_REAL = 1955 |
| CEFBS_HasSVE, // GLDFF1SH_S_UXTW_REAL = 1956 |
| CEFBS_HasSVE, // GLDFF1SH_S_UXTW_SCALED_REAL = 1957 |
| CEFBS_HasSVE, // GLDFF1SW_D_IMM_REAL = 1958 |
| CEFBS_HasSVE, // GLDFF1SW_D_REAL = 1959 |
| CEFBS_HasSVE, // GLDFF1SW_D_SCALED_REAL = 1960 |
| CEFBS_HasSVE, // GLDFF1SW_D_SXTW_REAL = 1961 |
| CEFBS_HasSVE, // GLDFF1SW_D_SXTW_SCALED_REAL = 1962 |
| CEFBS_HasSVE, // GLDFF1SW_D_UXTW_REAL = 1963 |
| CEFBS_HasSVE, // GLDFF1SW_D_UXTW_SCALED_REAL = 1964 |
| CEFBS_HasSVE, // GLDFF1W_D_IMM_REAL = 1965 |
| CEFBS_HasSVE, // GLDFF1W_D_REAL = 1966 |
| CEFBS_HasSVE, // GLDFF1W_D_SCALED_REAL = 1967 |
| CEFBS_HasSVE, // GLDFF1W_D_SXTW_REAL = 1968 |
| CEFBS_HasSVE, // GLDFF1W_D_SXTW_SCALED_REAL = 1969 |
| CEFBS_HasSVE, // GLDFF1W_D_UXTW_REAL = 1970 |
| CEFBS_HasSVE, // GLDFF1W_D_UXTW_SCALED_REAL = 1971 |
| CEFBS_HasSVE, // GLDFF1W_IMM_REAL = 1972 |
| CEFBS_HasSVE, // GLDFF1W_SXTW_REAL = 1973 |
| CEFBS_HasSVE, // GLDFF1W_SXTW_SCALED_REAL = 1974 |
| CEFBS_HasSVE, // GLDFF1W_UXTW_REAL = 1975 |
| CEFBS_HasSVE, // GLDFF1W_UXTW_SCALED_REAL = 1976 |
| CEFBS_HasMTE, // GMI = 1977 |
| CEFBS_None, // HINT = 1978 |
| CEFBS_HasSVE2, // HISTCNT_ZPzZZ_D = 1979 |
| CEFBS_HasSVE2, // HISTCNT_ZPzZZ_S = 1980 |
| CEFBS_HasSVE2, // HISTSEG_ZZZ = 1981 |
| CEFBS_None, // HLT = 1982 |
| CEFBS_None, // HVC = 1983 |
| CEFBS_None, // HWASAN_CHECK_MEMACCESS = 1984 |
| CEFBS_None, // HWASAN_CHECK_MEMACCESS_SHORTGRANULES = 1985 |
| CEFBS_HasSVE, // INCB_XPiI = 1986 |
| CEFBS_HasSVE, // INCD_XPiI = 1987 |
| CEFBS_HasSVE, // INCD_ZPiI = 1988 |
| CEFBS_HasSVE, // INCH_XPiI = 1989 |
| CEFBS_HasSVE, // INCH_ZPiI = 1990 |
| CEFBS_HasSVE, // INCP_XP_B = 1991 |
| CEFBS_HasSVE, // INCP_XP_D = 1992 |
| CEFBS_HasSVE, // INCP_XP_H = 1993 |
| CEFBS_HasSVE, // INCP_XP_S = 1994 |
| CEFBS_HasSVE, // INCP_ZP_D = 1995 |
| CEFBS_HasSVE, // INCP_ZP_H = 1996 |
| CEFBS_HasSVE, // INCP_ZP_S = 1997 |
| CEFBS_HasSVE, // INCW_XPiI = 1998 |
| CEFBS_HasSVE, // INCW_ZPiI = 1999 |
| CEFBS_HasSVE, // INDEX_II_B = 2000 |
| CEFBS_HasSVE, // INDEX_II_D = 2001 |
| CEFBS_HasSVE, // INDEX_II_H = 2002 |
| CEFBS_HasSVE, // INDEX_II_S = 2003 |
| CEFBS_HasSVE, // INDEX_IR_B = 2004 |
| CEFBS_HasSVE, // INDEX_IR_D = 2005 |
| CEFBS_HasSVE, // INDEX_IR_H = 2006 |
| CEFBS_HasSVE, // INDEX_IR_S = 2007 |
| CEFBS_HasSVE, // INDEX_RI_B = 2008 |
| CEFBS_HasSVE, // INDEX_RI_D = 2009 |
| CEFBS_HasSVE, // INDEX_RI_H = 2010 |
| CEFBS_HasSVE, // INDEX_RI_S = 2011 |
| CEFBS_HasSVE, // INDEX_RR_B = 2012 |
| CEFBS_HasSVE, // INDEX_RR_D = 2013 |
| CEFBS_HasSVE, // INDEX_RR_H = 2014 |
| CEFBS_HasSVE, // INDEX_RR_S = 2015 |
| CEFBS_HasSVE, // INSR_ZR_B = 2016 |
| CEFBS_HasSVE, // INSR_ZR_D = 2017 |
| CEFBS_HasSVE, // INSR_ZR_H = 2018 |
| CEFBS_HasSVE, // INSR_ZR_S = 2019 |
| CEFBS_HasSVE, // INSR_ZV_B = 2020 |
| CEFBS_HasSVE, // INSR_ZV_D = 2021 |
| CEFBS_HasSVE, // INSR_ZV_H = 2022 |
| CEFBS_HasSVE, // INSR_ZV_S = 2023 |
| CEFBS_HasNEON, // INSvi16gpr = 2024 |
| CEFBS_HasNEON, // INSvi16lane = 2025 |
| CEFBS_HasNEON, // INSvi32gpr = 2026 |
| CEFBS_HasNEON, // INSvi32lane = 2027 |
| CEFBS_HasNEON, // INSvi64gpr = 2028 |
| CEFBS_HasNEON, // INSvi64lane = 2029 |
| CEFBS_HasNEON, // INSvi8gpr = 2030 |
| CEFBS_HasNEON, // INSvi8lane = 2031 |
| CEFBS_HasMTE, // IRG = 2032 |
| CEFBS_HasMTE, // IRGstack = 2033 |
| CEFBS_None, // ISB = 2034 |
| CEFBS_None, // JumpTableDest16 = 2035 |
| CEFBS_None, // JumpTableDest32 = 2036 |
| CEFBS_None, // JumpTableDest8 = 2037 |
| CEFBS_HasSVE, // LASTA_RPZ_B = 2038 |
| CEFBS_HasSVE, // LASTA_RPZ_D = 2039 |
| CEFBS_HasSVE, // LASTA_RPZ_H = 2040 |
| CEFBS_HasSVE, // LASTA_RPZ_S = 2041 |
| CEFBS_HasSVE, // LASTA_VPZ_B = 2042 |
| CEFBS_HasSVE, // LASTA_VPZ_D = 2043 |
| CEFBS_HasSVE, // LASTA_VPZ_H = 2044 |
| CEFBS_HasSVE, // LASTA_VPZ_S = 2045 |
| CEFBS_HasSVE, // LASTB_RPZ_B = 2046 |
| CEFBS_HasSVE, // LASTB_RPZ_D = 2047 |
| CEFBS_HasSVE, // LASTB_RPZ_H = 2048 |
| CEFBS_HasSVE, // LASTB_RPZ_S = 2049 |
| CEFBS_HasSVE, // LASTB_VPZ_B = 2050 |
| CEFBS_HasSVE, // LASTB_VPZ_D = 2051 |
| CEFBS_HasSVE, // LASTB_VPZ_H = 2052 |
| CEFBS_HasSVE, // LASTB_VPZ_S = 2053 |
| CEFBS_HasSVE, // LD1B = 2054 |
| CEFBS_HasSVE, // LD1B_D = 2055 |
| CEFBS_HasSVE, // LD1B_D_IMM = 2056 |
| CEFBS_HasSVE, // LD1B_H = 2057 |
| CEFBS_HasSVE, // LD1B_H_IMM = 2058 |
| CEFBS_HasSVE, // LD1B_IMM = 2059 |
| CEFBS_HasSVE, // LD1B_S = 2060 |
| CEFBS_HasSVE, // LD1B_S_IMM = 2061 |
| CEFBS_HasSVE, // LD1D = 2062 |
| CEFBS_HasSVE, // LD1D_IMM = 2063 |
| CEFBS_HasNEON, // LD1Fourv16b = 2064 |
| CEFBS_HasNEON, // LD1Fourv16b_POST = 2065 |
| CEFBS_HasNEON, // LD1Fourv1d = 2066 |
| CEFBS_HasNEON, // LD1Fourv1d_POST = 2067 |
| CEFBS_HasNEON, // LD1Fourv2d = 2068 |
| CEFBS_HasNEON, // LD1Fourv2d_POST = 2069 |
| CEFBS_HasNEON, // LD1Fourv2s = 2070 |
| CEFBS_HasNEON, // LD1Fourv2s_POST = 2071 |
| CEFBS_HasNEON, // LD1Fourv4h = 2072 |
| CEFBS_HasNEON, // LD1Fourv4h_POST = 2073 |
| CEFBS_HasNEON, // LD1Fourv4s = 2074 |
| CEFBS_HasNEON, // LD1Fourv4s_POST = 2075 |
| CEFBS_HasNEON, // LD1Fourv8b = 2076 |
| CEFBS_HasNEON, // LD1Fourv8b_POST = 2077 |
| CEFBS_HasNEON, // LD1Fourv8h = 2078 |
| CEFBS_HasNEON, // LD1Fourv8h_POST = 2079 |
| CEFBS_HasSVE, // LD1H = 2080 |
| CEFBS_HasSVE, // LD1H_D = 2081 |
| CEFBS_HasSVE, // LD1H_D_IMM = 2082 |
| CEFBS_HasSVE, // LD1H_IMM = 2083 |
| CEFBS_HasSVE, // LD1H_S = 2084 |
| CEFBS_HasSVE, // LD1H_S_IMM = 2085 |
| CEFBS_HasNEON, // LD1Onev16b = 2086 |
| CEFBS_HasNEON, // LD1Onev16b_POST = 2087 |
| CEFBS_HasNEON, // LD1Onev1d = 2088 |
| CEFBS_HasNEON, // LD1Onev1d_POST = 2089 |
| CEFBS_HasNEON, // LD1Onev2d = 2090 |
| CEFBS_HasNEON, // LD1Onev2d_POST = 2091 |
| CEFBS_HasNEON, // LD1Onev2s = 2092 |
| CEFBS_HasNEON, // LD1Onev2s_POST = 2093 |
| CEFBS_HasNEON, // LD1Onev4h = 2094 |
| CEFBS_HasNEON, // LD1Onev4h_POST = 2095 |
| CEFBS_HasNEON, // LD1Onev4s = 2096 |
| CEFBS_HasNEON, // LD1Onev4s_POST = 2097 |
| CEFBS_HasNEON, // LD1Onev8b = 2098 |
| CEFBS_HasNEON, // LD1Onev8b_POST = 2099 |
| CEFBS_HasNEON, // LD1Onev8h = 2100 |
| CEFBS_HasNEON, // LD1Onev8h_POST = 2101 |
| CEFBS_HasSVE, // LD1RB_D_IMM = 2102 |
| CEFBS_HasSVE, // LD1RB_H_IMM = 2103 |
| CEFBS_HasSVE, // LD1RB_IMM = 2104 |
| CEFBS_HasSVE, // LD1RB_S_IMM = 2105 |
| CEFBS_HasSVE, // LD1RD_IMM = 2106 |
| CEFBS_HasSVE, // LD1RH_D_IMM = 2107 |
| CEFBS_HasSVE, // LD1RH_IMM = 2108 |
| CEFBS_HasSVE, // LD1RH_S_IMM = 2109 |
| CEFBS_HasSVE, // LD1RQ_B = 2110 |
| CEFBS_HasSVE, // LD1RQ_B_IMM = 2111 |
| CEFBS_HasSVE, // LD1RQ_D = 2112 |
| CEFBS_HasSVE, // LD1RQ_D_IMM = 2113 |
| CEFBS_HasSVE, // LD1RQ_H = 2114 |
| CEFBS_HasSVE, // LD1RQ_H_IMM = 2115 |
| CEFBS_HasSVE, // LD1RQ_W = 2116 |
| CEFBS_HasSVE, // LD1RQ_W_IMM = 2117 |
| CEFBS_HasSVE, // LD1RSB_D_IMM = 2118 |
| CEFBS_HasSVE, // LD1RSB_H_IMM = 2119 |
| CEFBS_HasSVE, // LD1RSB_S_IMM = 2120 |
| CEFBS_HasSVE, // LD1RSH_D_IMM = 2121 |
| CEFBS_HasSVE, // LD1RSH_S_IMM = 2122 |
| CEFBS_HasSVE, // LD1RSW_IMM = 2123 |
| CEFBS_HasSVE, // LD1RW_D_IMM = 2124 |
| CEFBS_HasSVE, // LD1RW_IMM = 2125 |
| CEFBS_HasNEON, // LD1Rv16b = 2126 |
| CEFBS_HasNEON, // LD1Rv16b_POST = 2127 |
| CEFBS_HasNEON, // LD1Rv1d = 2128 |
| CEFBS_HasNEON, // LD1Rv1d_POST = 2129 |
| CEFBS_HasNEON, // LD1Rv2d = 2130 |
| CEFBS_HasNEON, // LD1Rv2d_POST = 2131 |
| CEFBS_HasNEON, // LD1Rv2s = 2132 |
| CEFBS_HasNEON, // LD1Rv2s_POST = 2133 |
| CEFBS_HasNEON, // LD1Rv4h = 2134 |
| CEFBS_HasNEON, // LD1Rv4h_POST = 2135 |
| CEFBS_HasNEON, // LD1Rv4s = 2136 |
| CEFBS_HasNEON, // LD1Rv4s_POST = 2137 |
| CEFBS_HasNEON, // LD1Rv8b = 2138 |
| CEFBS_HasNEON, // LD1Rv8b_POST = 2139 |
| CEFBS_HasNEON, // LD1Rv8h = 2140 |
| CEFBS_HasNEON, // LD1Rv8h_POST = 2141 |
| CEFBS_HasSVE, // LD1SB_D = 2142 |
| CEFBS_HasSVE, // LD1SB_D_IMM = 2143 |
| CEFBS_HasSVE, // LD1SB_H = 2144 |
| CEFBS_HasSVE, // LD1SB_H_IMM = 2145 |
| CEFBS_HasSVE, // LD1SB_S = 2146 |
| CEFBS_HasSVE, // LD1SB_S_IMM = 2147 |
| CEFBS_HasSVE, // LD1SH_D = 2148 |
| CEFBS_HasSVE, // LD1SH_D_IMM = 2149 |
| CEFBS_HasSVE, // LD1SH_S = 2150 |
| CEFBS_HasSVE, // LD1SH_S_IMM = 2151 |
| CEFBS_HasSVE, // LD1SW_D = 2152 |
| CEFBS_HasSVE, // LD1SW_D_IMM = 2153 |
| CEFBS_HasNEON, // LD1Threev16b = 2154 |
| CEFBS_HasNEON, // LD1Threev16b_POST = 2155 |
| CEFBS_HasNEON, // LD1Threev1d = 2156 |
| CEFBS_HasNEON, // LD1Threev1d_POST = 2157 |
| CEFBS_HasNEON, // LD1Threev2d = 2158 |
| CEFBS_HasNEON, // LD1Threev2d_POST = 2159 |
| CEFBS_HasNEON, // LD1Threev2s = 2160 |
| CEFBS_HasNEON, // LD1Threev2s_POST = 2161 |
| CEFBS_HasNEON, // LD1Threev4h = 2162 |
| CEFBS_HasNEON, // LD1Threev4h_POST = 2163 |
| CEFBS_HasNEON, // LD1Threev4s = 2164 |
| CEFBS_HasNEON, // LD1Threev4s_POST = 2165 |
| CEFBS_HasNEON, // LD1Threev8b = 2166 |
| CEFBS_HasNEON, // LD1Threev8b_POST = 2167 |
| CEFBS_HasNEON, // LD1Threev8h = 2168 |
| CEFBS_HasNEON, // LD1Threev8h_POST = 2169 |
| CEFBS_HasNEON, // LD1Twov16b = 2170 |
| CEFBS_HasNEON, // LD1Twov16b_POST = 2171 |
| CEFBS_HasNEON, // LD1Twov1d = 2172 |
| CEFBS_HasNEON, // LD1Twov1d_POST = 2173 |
| CEFBS_HasNEON, // LD1Twov2d = 2174 |
| CEFBS_HasNEON, // LD1Twov2d_POST = 2175 |
| CEFBS_HasNEON, // LD1Twov2s = 2176 |
| CEFBS_HasNEON, // LD1Twov2s_POST = 2177 |
| CEFBS_HasNEON, // LD1Twov4h = 2178 |
| CEFBS_HasNEON, // LD1Twov4h_POST = 2179 |
| CEFBS_HasNEON, // LD1Twov4s = 2180 |
| CEFBS_HasNEON, // LD1Twov4s_POST = 2181 |
| CEFBS_HasNEON, // LD1Twov8b = 2182 |
| CEFBS_HasNEON, // LD1Twov8b_POST = 2183 |
| CEFBS_HasNEON, // LD1Twov8h = 2184 |
| CEFBS_HasNEON, // LD1Twov8h_POST = 2185 |
| CEFBS_HasSVE, // LD1W = 2186 |
| CEFBS_HasSVE, // LD1W_D = 2187 |
| CEFBS_HasSVE, // LD1W_D_IMM = 2188 |
| CEFBS_HasSVE, // LD1W_IMM = 2189 |
| CEFBS_HasNEON, // LD1i16 = 2190 |
| CEFBS_HasNEON, // LD1i16_POST = 2191 |
| CEFBS_HasNEON, // LD1i32 = 2192 |
| CEFBS_HasNEON, // LD1i32_POST = 2193 |
| CEFBS_HasNEON, // LD1i64 = 2194 |
| CEFBS_HasNEON, // LD1i64_POST = 2195 |
| CEFBS_HasNEON, // LD1i8 = 2196 |
| CEFBS_HasNEON, // LD1i8_POST = 2197 |
| CEFBS_HasSVE, // LD2B = 2198 |
| CEFBS_HasSVE, // LD2B_IMM = 2199 |
| CEFBS_HasSVE, // LD2D = 2200 |
| CEFBS_HasSVE, // LD2D_IMM = 2201 |
| CEFBS_HasSVE, // LD2H = 2202 |
| CEFBS_HasSVE, // LD2H_IMM = 2203 |
| CEFBS_HasNEON, // LD2Rv16b = 2204 |
| CEFBS_HasNEON, // LD2Rv16b_POST = 2205 |
| CEFBS_HasNEON, // LD2Rv1d = 2206 |
| CEFBS_HasNEON, // LD2Rv1d_POST = 2207 |
| CEFBS_HasNEON, // LD2Rv2d = 2208 |
| CEFBS_HasNEON, // LD2Rv2d_POST = 2209 |
| CEFBS_HasNEON, // LD2Rv2s = 2210 |
| CEFBS_HasNEON, // LD2Rv2s_POST = 2211 |
| CEFBS_HasNEON, // LD2Rv4h = 2212 |
| CEFBS_HasNEON, // LD2Rv4h_POST = 2213 |
| CEFBS_HasNEON, // LD2Rv4s = 2214 |
| CEFBS_HasNEON, // LD2Rv4s_POST = 2215 |
| CEFBS_HasNEON, // LD2Rv8b = 2216 |
| CEFBS_HasNEON, // LD2Rv8b_POST = 2217 |
| CEFBS_HasNEON, // LD2Rv8h = 2218 |
| CEFBS_HasNEON, // LD2Rv8h_POST = 2219 |
| CEFBS_HasNEON, // LD2Twov16b = 2220 |
| CEFBS_HasNEON, // LD2Twov16b_POST = 2221 |
| CEFBS_HasNEON, // LD2Twov2d = 2222 |
| CEFBS_HasNEON, // LD2Twov2d_POST = 2223 |
| CEFBS_HasNEON, // LD2Twov2s = 2224 |
| CEFBS_HasNEON, // LD2Twov2s_POST = 2225 |
| CEFBS_HasNEON, // LD2Twov4h = 2226 |
| CEFBS_HasNEON, // LD2Twov4h_POST = 2227 |
| CEFBS_HasNEON, // LD2Twov4s = 2228 |
| CEFBS_HasNEON, // LD2Twov4s_POST = 2229 |
| CEFBS_HasNEON, // LD2Twov8b = 2230 |
| CEFBS_HasNEON, // LD2Twov8b_POST = 2231 |
| CEFBS_HasNEON, // LD2Twov8h = 2232 |
| CEFBS_HasNEON, // LD2Twov8h_POST = 2233 |
| CEFBS_HasSVE, // LD2W = 2234 |
| CEFBS_HasSVE, // LD2W_IMM = 2235 |
| CEFBS_HasNEON, // LD2i16 = 2236 |
| CEFBS_HasNEON, // LD2i16_POST = 2237 |
| CEFBS_HasNEON, // LD2i32 = 2238 |
| CEFBS_HasNEON, // LD2i32_POST = 2239 |
| CEFBS_HasNEON, // LD2i64 = 2240 |
| CEFBS_HasNEON, // LD2i64_POST = 2241 |
| CEFBS_HasNEON, // LD2i8 = 2242 |
| CEFBS_HasNEON, // LD2i8_POST = 2243 |
| CEFBS_HasSVE, // LD3B = 2244 |
| CEFBS_HasSVE, // LD3B_IMM = 2245 |
| CEFBS_HasSVE, // LD3D = 2246 |
| CEFBS_HasSVE, // LD3D_IMM = 2247 |
| CEFBS_HasSVE, // LD3H = 2248 |
| CEFBS_HasSVE, // LD3H_IMM = 2249 |
| CEFBS_HasNEON, // LD3Rv16b = 2250 |
| CEFBS_HasNEON, // LD3Rv16b_POST = 2251 |
| CEFBS_HasNEON, // LD3Rv1d = 2252 |
| CEFBS_HasNEON, // LD3Rv1d_POST = 2253 |
| CEFBS_HasNEON, // LD3Rv2d = 2254 |
| CEFBS_HasNEON, // LD3Rv2d_POST = 2255 |
| CEFBS_HasNEON, // LD3Rv2s = 2256 |
| CEFBS_HasNEON, // LD3Rv2s_POST = 2257 |
| CEFBS_HasNEON, // LD3Rv4h = 2258 |
| CEFBS_HasNEON, // LD3Rv4h_POST = 2259 |
| CEFBS_HasNEON, // LD3Rv4s = 2260 |
| CEFBS_HasNEON, // LD3Rv4s_POST = 2261 |
| CEFBS_HasNEON, // LD3Rv8b = 2262 |
| CEFBS_HasNEON, // LD3Rv8b_POST = 2263 |
| CEFBS_HasNEON, // LD3Rv8h = 2264 |
| CEFBS_HasNEON, // LD3Rv8h_POST = 2265 |
| CEFBS_HasNEON, // LD3Threev16b = 2266 |
| CEFBS_HasNEON, // LD3Threev16b_POST = 2267 |
| CEFBS_HasNEON, // LD3Threev2d = 2268 |
| CEFBS_HasNEON, // LD3Threev2d_POST = 2269 |
| CEFBS_HasNEON, // LD3Threev2s = 2270 |
| CEFBS_HasNEON, // LD3Threev2s_POST = 2271 |
| CEFBS_HasNEON, // LD3Threev4h = 2272 |
| CEFBS_HasNEON, // LD3Threev4h_POST = 2273 |
| CEFBS_HasNEON, // LD3Threev4s = 2274 |
| CEFBS_HasNEON, // LD3Threev4s_POST = 2275 |
| CEFBS_HasNEON, // LD3Threev8b = 2276 |
| CEFBS_HasNEON, // LD3Threev8b_POST = 2277 |
| CEFBS_HasNEON, // LD3Threev8h = 2278 |
| CEFBS_HasNEON, // LD3Threev8h_POST = 2279 |
| CEFBS_HasSVE, // LD3W = 2280 |
| CEFBS_HasSVE, // LD3W_IMM = 2281 |
| CEFBS_HasNEON, // LD3i16 = 2282 |
| CEFBS_HasNEON, // LD3i16_POST = 2283 |
| CEFBS_HasNEON, // LD3i32 = 2284 |
| CEFBS_HasNEON, // LD3i32_POST = 2285 |
| CEFBS_HasNEON, // LD3i64 = 2286 |
| CEFBS_HasNEON, // LD3i64_POST = 2287 |
| CEFBS_HasNEON, // LD3i8 = 2288 |
| CEFBS_HasNEON, // LD3i8_POST = 2289 |
| CEFBS_HasSVE, // LD4B = 2290 |
| CEFBS_HasSVE, // LD4B_IMM = 2291 |
| CEFBS_HasSVE, // LD4D = 2292 |
| CEFBS_HasSVE, // LD4D_IMM = 2293 |
| CEFBS_HasNEON, // LD4Fourv16b = 2294 |
| CEFBS_HasNEON, // LD4Fourv16b_POST = 2295 |
| CEFBS_HasNEON, // LD4Fourv2d = 2296 |
| CEFBS_HasNEON, // LD4Fourv2d_POST = 2297 |
| CEFBS_HasNEON, // LD4Fourv2s = 2298 |
| CEFBS_HasNEON, // LD4Fourv2s_POST = 2299 |
| CEFBS_HasNEON, // LD4Fourv4h = 2300 |
| CEFBS_HasNEON, // LD4Fourv4h_POST = 2301 |
| CEFBS_HasNEON, // LD4Fourv4s = 2302 |
| CEFBS_HasNEON, // LD4Fourv4s_POST = 2303 |
| CEFBS_HasNEON, // LD4Fourv8b = 2304 |
| CEFBS_HasNEON, // LD4Fourv8b_POST = 2305 |
| CEFBS_HasNEON, // LD4Fourv8h = 2306 |
| CEFBS_HasNEON, // LD4Fourv8h_POST = 2307 |
| CEFBS_HasSVE, // LD4H = 2308 |
| CEFBS_HasSVE, // LD4H_IMM = 2309 |
| CEFBS_HasNEON, // LD4Rv16b = 2310 |
| CEFBS_HasNEON, // LD4Rv16b_POST = 2311 |
| CEFBS_HasNEON, // LD4Rv1d = 2312 |
| CEFBS_HasNEON, // LD4Rv1d_POST = 2313 |
| CEFBS_HasNEON, // LD4Rv2d = 2314 |
| CEFBS_HasNEON, // LD4Rv2d_POST = 2315 |
| CEFBS_HasNEON, // LD4Rv2s = 2316 |
| CEFBS_HasNEON, // LD4Rv2s_POST = 2317 |
| CEFBS_HasNEON, // LD4Rv4h = 2318 |
| CEFBS_HasNEON, // LD4Rv4h_POST = 2319 |
| CEFBS_HasNEON, // LD4Rv4s = 2320 |
| CEFBS_HasNEON, // LD4Rv4s_POST = 2321 |
| CEFBS_HasNEON, // LD4Rv8b = 2322 |
| CEFBS_HasNEON, // LD4Rv8b_POST = 2323 |
| CEFBS_HasNEON, // LD4Rv8h = 2324 |
| CEFBS_HasNEON, // LD4Rv8h_POST = 2325 |
| CEFBS_HasSVE, // LD4W = 2326 |
| CEFBS_HasSVE, // LD4W_IMM = 2327 |
| CEFBS_HasNEON, // LD4i16 = 2328 |
| CEFBS_HasNEON, // LD4i16_POST = 2329 |
| CEFBS_HasNEON, // LD4i32 = 2330 |
| CEFBS_HasNEON, // LD4i32_POST = 2331 |
| CEFBS_HasNEON, // LD4i64 = 2332 |
| CEFBS_HasNEON, // LD4i64_POST = 2333 |
| CEFBS_HasNEON, // LD4i8 = 2334 |
| CEFBS_HasNEON, // LD4i8_POST = 2335 |
| CEFBS_HasLSE, // LDADDAB = 2336 |
| CEFBS_HasLSE, // LDADDAH = 2337 |
| CEFBS_HasLSE, // LDADDALB = 2338 |
| CEFBS_HasLSE, // LDADDALH = 2339 |
| CEFBS_HasLSE, // LDADDALW = 2340 |
| CEFBS_HasLSE, // LDADDALX = 2341 |
| CEFBS_HasLSE, // LDADDAW = 2342 |
| CEFBS_HasLSE, // LDADDAX = 2343 |
| CEFBS_HasLSE, // LDADDB = 2344 |
| CEFBS_HasLSE, // LDADDH = 2345 |
| CEFBS_HasLSE, // LDADDLB = 2346 |
| CEFBS_HasLSE, // LDADDLH = 2347 |
| CEFBS_HasLSE, // LDADDLW = 2348 |
| CEFBS_HasLSE, // LDADDLX = 2349 |
| CEFBS_HasLSE, // LDADDW = 2350 |
| CEFBS_HasLSE, // LDADDX = 2351 |
| CEFBS_HasRCPC, // LDAPRB = 2352 |
| CEFBS_HasRCPC, // LDAPRH = 2353 |
| CEFBS_HasRCPC, // LDAPRW = 2354 |
| CEFBS_HasRCPC, // LDAPRX = 2355 |
| CEFBS_HasRCPC_IMMO, // LDAPURBi = 2356 |
| CEFBS_HasRCPC_IMMO, // LDAPURHi = 2357 |
| CEFBS_HasRCPC_IMMO, // LDAPURSBWi = 2358 |
| CEFBS_HasRCPC_IMMO, // LDAPURSBXi = 2359 |
| CEFBS_HasRCPC_IMMO, // LDAPURSHWi = 2360 |
| CEFBS_HasRCPC_IMMO, // LDAPURSHXi = 2361 |
| CEFBS_HasRCPC_IMMO, // LDAPURSWi = 2362 |
| CEFBS_HasRCPC_IMMO, // LDAPURXi = 2363 |
| CEFBS_HasRCPC_IMMO, // LDAPURi = 2364 |
| CEFBS_None, // LDARB = 2365 |
| CEFBS_None, // LDARH = 2366 |
| CEFBS_None, // LDARW = 2367 |
| CEFBS_None, // LDARX = 2368 |
| CEFBS_None, // LDAXPW = 2369 |
| CEFBS_None, // LDAXPX = 2370 |
| CEFBS_None, // LDAXRB = 2371 |
| CEFBS_None, // LDAXRH = 2372 |
| CEFBS_None, // LDAXRW = 2373 |
| CEFBS_None, // LDAXRX = 2374 |
| CEFBS_HasLSE, // LDCLRAB = 2375 |
| CEFBS_HasLSE, // LDCLRAH = 2376 |
| CEFBS_HasLSE, // LDCLRALB = 2377 |
| CEFBS_HasLSE, // LDCLRALH = 2378 |
| CEFBS_HasLSE, // LDCLRALW = 2379 |
| CEFBS_HasLSE, // LDCLRALX = 2380 |
| CEFBS_HasLSE, // LDCLRAW = 2381 |
| CEFBS_HasLSE, // LDCLRAX = 2382 |
| CEFBS_HasLSE, // LDCLRB = 2383 |
| CEFBS_HasLSE, // LDCLRH = 2384 |
| CEFBS_HasLSE, // LDCLRLB = 2385 |
| CEFBS_HasLSE, // LDCLRLH = 2386 |
| CEFBS_HasLSE, // LDCLRLW = 2387 |
| CEFBS_HasLSE, // LDCLRLX = 2388 |
| CEFBS_HasLSE, // LDCLRW = 2389 |
| CEFBS_HasLSE, // LDCLRX = 2390 |
| CEFBS_HasLSE, // LDEORAB = 2391 |
| CEFBS_HasLSE, // LDEORAH = 2392 |
| CEFBS_HasLSE, // LDEORALB = 2393 |
| CEFBS_HasLSE, // LDEORALH = 2394 |
| CEFBS_HasLSE, // LDEORALW = 2395 |
| CEFBS_HasLSE, // LDEORALX = 2396 |
| CEFBS_HasLSE, // LDEORAW = 2397 |
| CEFBS_HasLSE, // LDEORAX = 2398 |
| CEFBS_HasLSE, // LDEORB = 2399 |
| CEFBS_HasLSE, // LDEORH = 2400 |
| CEFBS_HasLSE, // LDEORLB = 2401 |
| CEFBS_HasLSE, // LDEORLH = 2402 |
| CEFBS_HasLSE, // LDEORLW = 2403 |
| CEFBS_HasLSE, // LDEORLX = 2404 |
| CEFBS_HasLSE, // LDEORW = 2405 |
| CEFBS_HasLSE, // LDEORX = 2406 |
| CEFBS_HasSVE, // LDFF1B_D_REAL = 2407 |
| CEFBS_HasSVE, // LDFF1B_H_REAL = 2408 |
| CEFBS_HasSVE, // LDFF1B_REAL = 2409 |
| CEFBS_HasSVE, // LDFF1B_S_REAL = 2410 |
| CEFBS_HasSVE, // LDFF1D_REAL = 2411 |
| CEFBS_HasSVE, // LDFF1H_D_REAL = 2412 |
| CEFBS_HasSVE, // LDFF1H_REAL = 2413 |
| CEFBS_HasSVE, // LDFF1H_S_REAL = 2414 |
| CEFBS_HasSVE, // LDFF1SB_D_REAL = 2415 |
| CEFBS_HasSVE, // LDFF1SB_H_REAL = 2416 |
| CEFBS_HasSVE, // LDFF1SB_S_REAL = 2417 |
| CEFBS_HasSVE, // LDFF1SH_D_REAL = 2418 |
| CEFBS_HasSVE, // LDFF1SH_S_REAL = 2419 |
| CEFBS_HasSVE, // LDFF1SW_D_REAL = 2420 |
| CEFBS_HasSVE, // LDFF1W_D_REAL = 2421 |
| CEFBS_HasSVE, // LDFF1W_REAL = 2422 |
| CEFBS_HasMTE, // LDG = 2423 |
| CEFBS_HasMTE, // LDGM = 2424 |
| CEFBS_HasLOR, // LDLARB = 2425 |
| CEFBS_HasLOR, // LDLARH = 2426 |
| CEFBS_HasLOR, // LDLARW = 2427 |
| CEFBS_HasLOR, // LDLARX = 2428 |
| CEFBS_HasSVE, // LDNF1B_D_IMM = 2429 |
| CEFBS_HasSVE, // LDNF1B_H_IMM = 2430 |
| CEFBS_HasSVE, // LDNF1B_IMM = 2431 |
| CEFBS_HasSVE, // LDNF1B_S_IMM = 2432 |
| CEFBS_HasSVE, // LDNF1D_IMM = 2433 |
| CEFBS_HasSVE, // LDNF1H_D_IMM = 2434 |
| CEFBS_HasSVE, // LDNF1H_IMM = 2435 |
| CEFBS_HasSVE, // LDNF1H_S_IMM = 2436 |
| CEFBS_HasSVE, // LDNF1SB_D_IMM = 2437 |
| CEFBS_HasSVE, // LDNF1SB_H_IMM = 2438 |
| CEFBS_HasSVE, // LDNF1SB_S_IMM = 2439 |
| CEFBS_HasSVE, // LDNF1SH_D_IMM = 2440 |
| CEFBS_HasSVE, // LDNF1SH_S_IMM = 2441 |
| CEFBS_HasSVE, // LDNF1SW_D_IMM = 2442 |
| CEFBS_HasSVE, // LDNF1W_D_IMM = 2443 |
| CEFBS_HasSVE, // LDNF1W_IMM = 2444 |
| CEFBS_None, // LDNPDi = 2445 |
| CEFBS_None, // LDNPQi = 2446 |
| CEFBS_None, // LDNPSi = 2447 |
| CEFBS_None, // LDNPWi = 2448 |
| CEFBS_None, // LDNPXi = 2449 |
| CEFBS_HasSVE, // LDNT1B_ZRI = 2450 |
| CEFBS_HasSVE, // LDNT1B_ZRR = 2451 |
| CEFBS_HasSVE2, // LDNT1B_ZZR_D_REAL = 2452 |
| CEFBS_HasSVE2, // LDNT1B_ZZR_S_REAL = 2453 |
| CEFBS_HasSVE, // LDNT1D_ZRI = 2454 |
| CEFBS_HasSVE, // LDNT1D_ZRR = 2455 |
| CEFBS_HasSVE2, // LDNT1D_ZZR_D_REAL = 2456 |
| CEFBS_HasSVE, // LDNT1H_ZRI = 2457 |
| CEFBS_HasSVE, // LDNT1H_ZRR = 2458 |
| CEFBS_HasSVE2, // LDNT1H_ZZR_D_REAL = 2459 |
| CEFBS_HasSVE2, // LDNT1H_ZZR_S_REAL = 2460 |
| CEFBS_HasSVE2, // LDNT1SB_ZZR_D_REAL = 2461 |
| CEFBS_HasSVE2, // LDNT1SB_ZZR_S_REAL = 2462 |
| CEFBS_HasSVE2, // LDNT1SH_ZZR_D_REAL = 2463 |
| CEFBS_HasSVE2, // LDNT1SH_ZZR_S_REAL = 2464 |
| CEFBS_HasSVE2, // LDNT1SW_ZZR_D_REAL = 2465 |
| CEFBS_HasSVE, // LDNT1W_ZRI = 2466 |
| CEFBS_HasSVE, // LDNT1W_ZRR = 2467 |
| CEFBS_HasSVE2, // LDNT1W_ZZR_D_REAL = 2468 |
| CEFBS_HasSVE2, // LDNT1W_ZZR_S_REAL = 2469 |
| CEFBS_None, // LDPDi = 2470 |
| CEFBS_None, // LDPDpost = 2471 |
| CEFBS_None, // LDPDpre = 2472 |
| CEFBS_None, // LDPQi = 2473 |
| CEFBS_None, // LDPQpost = 2474 |
| CEFBS_None, // LDPQpre = 2475 |
| CEFBS_None, // LDPSWi = 2476 |
| CEFBS_None, // LDPSWpost = 2477 |
| CEFBS_None, // LDPSWpre = 2478 |
| CEFBS_None, // LDPSi = 2479 |
| CEFBS_None, // LDPSpost = 2480 |
| CEFBS_None, // LDPSpre = 2481 |
| CEFBS_None, // LDPWi = 2482 |
| CEFBS_None, // LDPWpost = 2483 |
| CEFBS_None, // LDPWpre = 2484 |
| CEFBS_None, // LDPXi = 2485 |
| CEFBS_None, // LDPXpost = 2486 |
| CEFBS_None, // LDPXpre = 2487 |
| CEFBS_HasPA, // LDRAAindexed = 2488 |
| CEFBS_HasPA, // LDRAAwriteback = 2489 |
| CEFBS_HasPA, // LDRABindexed = 2490 |
| CEFBS_HasPA, // LDRABwriteback = 2491 |
| CEFBS_None, // LDRBBpost = 2492 |
| CEFBS_None, // LDRBBpre = 2493 |
| CEFBS_None, // LDRBBroW = 2494 |
| CEFBS_None, // LDRBBroX = 2495 |
| CEFBS_None, // LDRBBui = 2496 |
| CEFBS_None, // LDRBpost = 2497 |
| CEFBS_None, // LDRBpre = 2498 |
| CEFBS_None, // LDRBroW = 2499 |
| CEFBS_None, // LDRBroX = 2500 |
| CEFBS_None, // LDRBui = 2501 |
| CEFBS_None, // LDRDl = 2502 |
| CEFBS_None, // LDRDpost = 2503 |
| CEFBS_None, // LDRDpre = 2504 |
| CEFBS_None, // LDRDroW = 2505 |
| CEFBS_None, // LDRDroX = 2506 |
| CEFBS_None, // LDRDui = 2507 |
| CEFBS_None, // LDRHHpost = 2508 |
| CEFBS_None, // LDRHHpre = 2509 |
| CEFBS_None, // LDRHHroW = 2510 |
| CEFBS_None, // LDRHHroX = 2511 |
| CEFBS_None, // LDRHHui = 2512 |
| CEFBS_None, // LDRHpost = 2513 |
| CEFBS_None, // LDRHpre = 2514 |
| CEFBS_None, // LDRHroW = 2515 |
| CEFBS_None, // LDRHroX = 2516 |
| CEFBS_None, // LDRHui = 2517 |
| CEFBS_None, // LDRQl = 2518 |
| CEFBS_None, // LDRQpost = 2519 |
| CEFBS_None, // LDRQpre = 2520 |
| CEFBS_None, // LDRQroW = 2521 |
| CEFBS_None, // LDRQroX = 2522 |
| CEFBS_None, // LDRQui = 2523 |
| CEFBS_None, // LDRSBWpost = 2524 |
| CEFBS_None, // LDRSBWpre = 2525 |
| CEFBS_None, // LDRSBWroW = 2526 |
| CEFBS_None, // LDRSBWroX = 2527 |
| CEFBS_None, // LDRSBWui = 2528 |
| CEFBS_None, // LDRSBXpost = 2529 |
| CEFBS_None, // LDRSBXpre = 2530 |
| CEFBS_None, // LDRSBXroW = 2531 |
| CEFBS_None, // LDRSBXroX = 2532 |
| CEFBS_None, // LDRSBXui = 2533 |
| CEFBS_None, // LDRSHWpost = 2534 |
| CEFBS_None, // LDRSHWpre = 2535 |
| CEFBS_None, // LDRSHWroW = 2536 |
| CEFBS_None, // LDRSHWroX = 2537 |
| CEFBS_None, // LDRSHWui = 2538 |
| CEFBS_None, // LDRSHXpost = 2539 |
| CEFBS_None, // LDRSHXpre = 2540 |
| CEFBS_None, // LDRSHXroW = 2541 |
| CEFBS_None, // LDRSHXroX = 2542 |
| CEFBS_None, // LDRSHXui = 2543 |
| CEFBS_None, // LDRSWl = 2544 |
| CEFBS_None, // LDRSWpost = 2545 |
| CEFBS_None, // LDRSWpre = 2546 |
| CEFBS_None, // LDRSWroW = 2547 |
| CEFBS_None, // LDRSWroX = 2548 |
| CEFBS_None, // LDRSWui = 2549 |
| CEFBS_None, // LDRSl = 2550 |
| CEFBS_None, // LDRSpost = 2551 |
| CEFBS_None, // LDRSpre = 2552 |
| CEFBS_None, // LDRSroW = 2553 |
| CEFBS_None, // LDRSroX = 2554 |
| CEFBS_None, // LDRSui = 2555 |
| CEFBS_None, // LDRWl = 2556 |
| CEFBS_None, // LDRWpost = 2557 |
| CEFBS_None, // LDRWpre = 2558 |
| CEFBS_None, // LDRWroW = 2559 |
| CEFBS_None, // LDRWroX = 2560 |
| CEFBS_None, // LDRWui = 2561 |
| CEFBS_None, // LDRXl = 2562 |
| CEFBS_None, // LDRXpost = 2563 |
| CEFBS_None, // LDRXpre = 2564 |
| CEFBS_None, // LDRXroW = 2565 |
| CEFBS_None, // LDRXroX = 2566 |
| CEFBS_None, // LDRXui = 2567 |
| CEFBS_HasSVE, // LDR_PXI = 2568 |
| CEFBS_HasSVE, // LDR_ZXI = 2569 |
| CEFBS_HasLSE, // LDSETAB = 2570 |
| CEFBS_HasLSE, // LDSETAH = 2571 |
| CEFBS_HasLSE, // LDSETALB = 2572 |
| CEFBS_HasLSE, // LDSETALH = 2573 |
| CEFBS_HasLSE, // LDSETALW = 2574 |
| CEFBS_HasLSE, // LDSETALX = 2575 |
| CEFBS_HasLSE, // LDSETAW = 2576 |
| CEFBS_HasLSE, // LDSETAX = 2577 |
| CEFBS_HasLSE, // LDSETB = 2578 |
| CEFBS_HasLSE, // LDSETH = 2579 |
| CEFBS_HasLSE, // LDSETLB = 2580 |
| CEFBS_HasLSE, // LDSETLH = 2581 |
| CEFBS_HasLSE, // LDSETLW = 2582 |
| CEFBS_HasLSE, // LDSETLX = 2583 |
| CEFBS_HasLSE, // LDSETW = 2584 |
| CEFBS_HasLSE, // LDSETX = 2585 |
| CEFBS_HasLSE, // LDSMAXAB = 2586 |
| CEFBS_HasLSE, // LDSMAXAH = 2587 |
| CEFBS_HasLSE, // LDSMAXALB = 2588 |
| CEFBS_HasLSE, // LDSMAXALH = 2589 |
| CEFBS_HasLSE, // LDSMAXALW = 2590 |
| CEFBS_HasLSE, // LDSMAXALX = 2591 |
| CEFBS_HasLSE, // LDSMAXAW = 2592 |
| CEFBS_HasLSE, // LDSMAXAX = 2593 |
| CEFBS_HasLSE, // LDSMAXB = 2594 |
| CEFBS_HasLSE, // LDSMAXH = 2595 |
| CEFBS_HasLSE, // LDSMAXLB = 2596 |
| CEFBS_HasLSE, // LDSMAXLH = 2597 |
| CEFBS_HasLSE, // LDSMAXLW = 2598 |
| CEFBS_HasLSE, // LDSMAXLX = 2599 |
| CEFBS_HasLSE, // LDSMAXW = 2600 |
| CEFBS_HasLSE, // LDSMAXX = 2601 |
| CEFBS_HasLSE, // LDSMINAB = 2602 |
| CEFBS_HasLSE, // LDSMINAH = 2603 |
| CEFBS_HasLSE, // LDSMINALB = 2604 |
| CEFBS_HasLSE, // LDSMINALH = 2605 |
| CEFBS_HasLSE, // LDSMINALW = 2606 |
| CEFBS_HasLSE, // LDSMINALX = 2607 |
| CEFBS_HasLSE, // LDSMINAW = 2608 |
| CEFBS_HasLSE, // LDSMINAX = 2609 |
| CEFBS_HasLSE, // LDSMINB = 2610 |
| CEFBS_HasLSE, // LDSMINH = 2611 |
| CEFBS_HasLSE, // LDSMINLB = 2612 |
| CEFBS_HasLSE, // LDSMINLH = 2613 |
| CEFBS_HasLSE, // LDSMINLW = 2614 |
| CEFBS_HasLSE, // LDSMINLX = 2615 |
| CEFBS_HasLSE, // LDSMINW = 2616 |
| CEFBS_HasLSE, // LDSMINX = 2617 |
| CEFBS_None, // LDTRBi = 2618 |
| CEFBS_None, // LDTRHi = 2619 |
| CEFBS_None, // LDTRSBWi = 2620 |
| CEFBS_None, // LDTRSBXi = 2621 |
| CEFBS_None, // LDTRSHWi = 2622 |
| CEFBS_None, // LDTRSHXi = 2623 |
| CEFBS_None, // LDTRSWi = 2624 |
| CEFBS_None, // LDTRWi = 2625 |
| CEFBS_None, // LDTRXi = 2626 |
| CEFBS_HasLSE, // LDUMAXAB = 2627 |
| CEFBS_HasLSE, // LDUMAXAH = 2628 |
| CEFBS_HasLSE, // LDUMAXALB = 2629 |
| CEFBS_HasLSE, // LDUMAXALH = 2630 |
| CEFBS_HasLSE, // LDUMAXALW = 2631 |
| CEFBS_HasLSE, // LDUMAXALX = 2632 |
| CEFBS_HasLSE, // LDUMAXAW = 2633 |
| CEFBS_HasLSE, // LDUMAXAX = 2634 |
| CEFBS_HasLSE, // LDUMAXB = 2635 |
| CEFBS_HasLSE, // LDUMAXH = 2636 |
| CEFBS_HasLSE, // LDUMAXLB = 2637 |
| CEFBS_HasLSE, // LDUMAXLH = 2638 |
| CEFBS_HasLSE, // LDUMAXLW = 2639 |
| CEFBS_HasLSE, // LDUMAXLX = 2640 |
| CEFBS_HasLSE, // LDUMAXW = 2641 |
| CEFBS_HasLSE, // LDUMAXX = 2642 |
| CEFBS_HasLSE, // LDUMINAB = 2643 |
| CEFBS_HasLSE, // LDUMINAH = 2644 |
| CEFBS_HasLSE, // LDUMINALB = 2645 |
| CEFBS_HasLSE, // LDUMINALH = 2646 |
| CEFBS_HasLSE, // LDUMINALW = 2647 |
| CEFBS_HasLSE, // LDUMINALX = 2648 |
| CEFBS_HasLSE, // LDUMINAW = 2649 |
| CEFBS_HasLSE, // LDUMINAX = 2650 |
| CEFBS_HasLSE, // LDUMINB = 2651 |
| CEFBS_HasLSE, // LDUMINH = 2652 |
| CEFBS_HasLSE, // LDUMINLB = 2653 |
| CEFBS_HasLSE, // LDUMINLH = 2654 |
| CEFBS_HasLSE, // LDUMINLW = 2655 |
| CEFBS_HasLSE, // LDUMINLX = 2656 |
| CEFBS_HasLSE, // LDUMINW = 2657 |
| CEFBS_HasLSE, // LDUMINX = 2658 |
| CEFBS_None, // LDURBBi = 2659 |
| CEFBS_None, // LDURBi = 2660 |
| CEFBS_None, // LDURDi = 2661 |
| CEFBS_None, // LDURHHi = 2662 |
| CEFBS_None, // LDURHi = 2663 |
| CEFBS_None, // LDURQi = 2664 |
| CEFBS_None, // LDURSBWi = 2665 |
| CEFBS_None, // LDURSBXi = 2666 |
| CEFBS_None, // LDURSHWi = 2667 |
| CEFBS_None, // LDURSHXi = 2668 |
| CEFBS_None, // LDURSWi = 2669 |
| CEFBS_None, // LDURSi = 2670 |
| CEFBS_None, // LDURWi = 2671 |
| CEFBS_None, // LDURXi = 2672 |
| CEFBS_None, // LDXPW = 2673 |
| CEFBS_None, // LDXPX = 2674 |
| CEFBS_None, // LDXRB = 2675 |
| CEFBS_None, // LDXRH = 2676 |
| CEFBS_None, // LDXRW = 2677 |
| CEFBS_None, // LDXRX = 2678 |
| CEFBS_None, // LOADgot = 2679 |
| CEFBS_HasSVE, // LSLR_ZPmZ_B = 2680 |
| CEFBS_HasSVE, // LSLR_ZPmZ_D = 2681 |
| CEFBS_HasSVE, // LSLR_ZPmZ_H = 2682 |
| CEFBS_HasSVE, // LSLR_ZPmZ_S = 2683 |
| CEFBS_None, // LSLVWr = 2684 |
| CEFBS_None, // LSLVXr = 2685 |
| CEFBS_HasSVE, // LSL_WIDE_ZPmZ_B = 2686 |
| CEFBS_HasSVE, // LSL_WIDE_ZPmZ_H = 2687 |
| CEFBS_HasSVE, // LSL_WIDE_ZPmZ_S = 2688 |
| CEFBS_HasSVE, // LSL_WIDE_ZZZ_B = 2689 |
| CEFBS_HasSVE, // LSL_WIDE_ZZZ_H = 2690 |
| CEFBS_HasSVE, // LSL_WIDE_ZZZ_S = 2691 |
| CEFBS_HasSVE, // LSL_ZPmI_B = 2692 |
| CEFBS_HasSVE, // LSL_ZPmI_D = 2693 |
| CEFBS_HasSVE, // LSL_ZPmI_H = 2694 |
| CEFBS_HasSVE, // LSL_ZPmI_S = 2695 |
| CEFBS_HasSVE, // LSL_ZPmZ_B = 2696 |
| CEFBS_HasSVE, // LSL_ZPmZ_D = 2697 |
| CEFBS_HasSVE, // LSL_ZPmZ_H = 2698 |
| CEFBS_HasSVE, // LSL_ZPmZ_S = 2699 |
| CEFBS_HasSVE, // LSL_ZZI_B = 2700 |
| CEFBS_HasSVE, // LSL_ZZI_D = 2701 |
| CEFBS_HasSVE, // LSL_ZZI_H = 2702 |
| CEFBS_HasSVE, // LSL_ZZI_S = 2703 |
| CEFBS_HasSVE, // LSRR_ZPmZ_B = 2704 |
| CEFBS_HasSVE, // LSRR_ZPmZ_D = 2705 |
| CEFBS_HasSVE, // LSRR_ZPmZ_H = 2706 |
| CEFBS_HasSVE, // LSRR_ZPmZ_S = 2707 |
| CEFBS_None, // LSRVWr = 2708 |
| CEFBS_None, // LSRVXr = 2709 |
| CEFBS_HasSVE, // LSR_WIDE_ZPmZ_B = 2710 |
| CEFBS_HasSVE, // LSR_WIDE_ZPmZ_H = 2711 |
| CEFBS_HasSVE, // LSR_WIDE_ZPmZ_S = 2712 |
| CEFBS_HasSVE, // LSR_WIDE_ZZZ_B = 2713 |
| CEFBS_HasSVE, // LSR_WIDE_ZZZ_H = 2714 |
| CEFBS_HasSVE, // LSR_WIDE_ZZZ_S = 2715 |
| CEFBS_HasSVE, // LSR_ZPmI_B = 2716 |
| CEFBS_HasSVE, // LSR_ZPmI_D = 2717 |
| CEFBS_HasSVE, // LSR_ZPmI_H = 2718 |
| CEFBS_HasSVE, // LSR_ZPmI_S = 2719 |
| CEFBS_HasSVE, // LSR_ZPmZ_B = 2720 |
| CEFBS_HasSVE, // LSR_ZPmZ_D = 2721 |
| CEFBS_HasSVE, // LSR_ZPmZ_H = 2722 |
| CEFBS_HasSVE, // LSR_ZPmZ_S = 2723 |
| CEFBS_HasSVE, // LSR_ZZI_B = 2724 |
| CEFBS_HasSVE, // LSR_ZZI_D = 2725 |
| CEFBS_HasSVE, // LSR_ZZI_H = 2726 |
| CEFBS_HasSVE, // LSR_ZZI_S = 2727 |
| CEFBS_None, // MADDWrrr = 2728 |
| CEFBS_None, // MADDXrrr = 2729 |
| CEFBS_HasSVE, // MAD_ZPmZZ_B = 2730 |
| CEFBS_HasSVE, // MAD_ZPmZZ_D = 2731 |
| CEFBS_HasSVE, // MAD_ZPmZZ_H = 2732 |
| CEFBS_HasSVE, // MAD_ZPmZZ_S = 2733 |
| CEFBS_HasSVE2, // MATCH_PPzZZ_B = 2734 |
| CEFBS_HasSVE2, // MATCH_PPzZZ_H = 2735 |
| CEFBS_HasSVE, // MLA_ZPmZZ_B = 2736 |
| CEFBS_HasSVE, // MLA_ZPmZZ_D = 2737 |
| CEFBS_HasSVE, // MLA_ZPmZZ_H = 2738 |
| CEFBS_HasSVE, // MLA_ZPmZZ_S = 2739 |
| CEFBS_HasSVE2, // MLA_ZZZI_D = 2740 |
| CEFBS_HasSVE2, // MLA_ZZZI_H = 2741 |
| CEFBS_HasSVE2, // MLA_ZZZI_S = 2742 |
| CEFBS_HasNEON, // MLAv16i8 = 2743 |
| CEFBS_HasNEON, // MLAv2i32 = 2744 |
| CEFBS_HasNEON, // MLAv2i32_indexed = 2745 |
| CEFBS_HasNEON, // MLAv4i16 = 2746 |
| CEFBS_HasNEON, // MLAv4i16_indexed = 2747 |
| CEFBS_HasNEON, // MLAv4i32 = 2748 |
| CEFBS_HasNEON, // MLAv4i32_indexed = 2749 |
| CEFBS_HasNEON, // MLAv8i16 = 2750 |
| CEFBS_HasNEON, // MLAv8i16_indexed = 2751 |
| CEFBS_HasNEON, // MLAv8i8 = 2752 |
| CEFBS_HasSVE, // MLS_ZPmZZ_B = 2753 |
| CEFBS_HasSVE, // MLS_ZPmZZ_D = 2754 |
| CEFBS_HasSVE, // MLS_ZPmZZ_H = 2755 |
| CEFBS_HasSVE, // MLS_ZPmZZ_S = 2756 |
| CEFBS_HasSVE2, // MLS_ZZZI_D = 2757 |
| CEFBS_HasSVE2, // MLS_ZZZI_H = 2758 |
| CEFBS_HasSVE2, // MLS_ZZZI_S = 2759 |
| CEFBS_HasNEON, // MLSv16i8 = 2760 |
| CEFBS_HasNEON, // MLSv2i32 = 2761 |
| CEFBS_HasNEON, // MLSv2i32_indexed = 2762 |
| CEFBS_HasNEON, // MLSv4i16 = 2763 |
| CEFBS_HasNEON, // MLSv4i16_indexed = 2764 |
| CEFBS_HasNEON, // MLSv4i32 = 2765 |
| CEFBS_HasNEON, // MLSv4i32_indexed = 2766 |
| CEFBS_HasNEON, // MLSv8i16 = 2767 |
| CEFBS_HasNEON, // MLSv8i16_indexed = 2768 |
| CEFBS_HasNEON, // MLSv8i8 = 2769 |
| CEFBS_HasNEON, // MOVID = 2770 |
| CEFBS_HasNEON, // MOVIv16b_ns = 2771 |
| CEFBS_HasNEON, // MOVIv2d_ns = 2772 |
| CEFBS_HasNEON, // MOVIv2i32 = 2773 |
| CEFBS_HasNEON, // MOVIv2s_msl = 2774 |
| CEFBS_HasNEON, // MOVIv4i16 = 2775 |
| CEFBS_HasNEON, // MOVIv4i32 = 2776 |
| CEFBS_HasNEON, // MOVIv4s_msl = 2777 |
| CEFBS_HasNEON, // MOVIv8b_ns = 2778 |
| CEFBS_HasNEON, // MOVIv8i16 = 2779 |
| CEFBS_None, // MOVKWi = 2780 |
| CEFBS_None, // MOVKXi = 2781 |
| CEFBS_None, // MOVMCSym = 2782 |
| CEFBS_None, // MOVNWi = 2783 |
| CEFBS_None, // MOVNXi = 2784 |
| CEFBS_HasSVE, // MOVPRFX_ZPmZ_B = 2785 |
| CEFBS_HasSVE, // MOVPRFX_ZPmZ_D = 2786 |
| CEFBS_HasSVE, // MOVPRFX_ZPmZ_H = 2787 |
| CEFBS_HasSVE, // MOVPRFX_ZPmZ_S = 2788 |
| CEFBS_HasSVE, // MOVPRFX_ZPzZ_B = 2789 |
| CEFBS_HasSVE, // MOVPRFX_ZPzZ_D = 2790 |
| CEFBS_HasSVE, // MOVPRFX_ZPzZ_H = 2791 |
| CEFBS_HasSVE, // MOVPRFX_ZPzZ_S = 2792 |
| CEFBS_HasSVE, // MOVPRFX_ZZ = 2793 |
| CEFBS_None, // MOVZWi = 2794 |
| CEFBS_None, // MOVZXi = 2795 |
| CEFBS_None, // MOVaddr = 2796 |
| CEFBS_None, // MOVaddrBA = 2797 |
| CEFBS_None, // MOVaddrCP = 2798 |
| CEFBS_None, // MOVaddrEXT = 2799 |
| CEFBS_None, // MOVaddrJT = 2800 |
| CEFBS_None, // MOVaddrTLS = 2801 |
| CEFBS_None, // MOVbaseTLS = 2802 |
| CEFBS_None, // MOVi32imm = 2803 |
| CEFBS_None, // MOVi64imm = 2804 |
| CEFBS_None, // MRS = 2805 |
| CEFBS_HasSVE, // MSB_ZPmZZ_B = 2806 |
| CEFBS_HasSVE, // MSB_ZPmZZ_D = 2807 |
| CEFBS_HasSVE, // MSB_ZPmZZ_H = 2808 |
| CEFBS_HasSVE, // MSB_ZPmZZ_S = 2809 |
| CEFBS_None, // MSR = 2810 |
| CEFBS_None, // MSRpstateImm1 = 2811 |
| CEFBS_None, // MSRpstateImm4 = 2812 |
| CEFBS_None, // MSUBWrrr = 2813 |
| CEFBS_None, // MSUBXrrr = 2814 |
| CEFBS_HasSVE, // MUL_ZI_B = 2815 |
| CEFBS_HasSVE, // MUL_ZI_D = 2816 |
| CEFBS_HasSVE, // MUL_ZI_H = 2817 |
| CEFBS_HasSVE, // MUL_ZI_S = 2818 |
| CEFBS_HasSVE, // MUL_ZPmZ_B = 2819 |
| CEFBS_HasSVE, // MUL_ZPmZ_D = 2820 |
| CEFBS_HasSVE, // MUL_ZPmZ_H = 2821 |
| CEFBS_HasSVE, // MUL_ZPmZ_S = 2822 |
| CEFBS_HasSVE2, // MUL_ZZZI_D = 2823 |
| CEFBS_HasSVE2, // MUL_ZZZI_H = 2824 |
| CEFBS_HasSVE2, // MUL_ZZZI_S = 2825 |
| CEFBS_HasSVE2, // MUL_ZZZ_B = 2826 |
| CEFBS_HasSVE2, // MUL_ZZZ_D = 2827 |
| CEFBS_HasSVE2, // MUL_ZZZ_H = 2828 |
| CEFBS_HasSVE2, // MUL_ZZZ_S = 2829 |
| CEFBS_HasNEON, // MULv16i8 = 2830 |
| CEFBS_HasNEON, // MULv2i32 = 2831 |
| CEFBS_HasNEON, // MULv2i32_indexed = 2832 |
| CEFBS_HasNEON, // MULv4i16 = 2833 |
| CEFBS_HasNEON, // MULv4i16_indexed = 2834 |
| CEFBS_HasNEON, // MULv4i32 = 2835 |
| CEFBS_HasNEON, // MULv4i32_indexed = 2836 |
| CEFBS_HasNEON, // MULv8i16 = 2837 |
| CEFBS_HasNEON, // MULv8i16_indexed = 2838 |
| CEFBS_HasNEON, // MULv8i8 = 2839 |
| CEFBS_HasNEON, // MVNIv2i32 = 2840 |
| CEFBS_HasNEON, // MVNIv2s_msl = 2841 |
| CEFBS_HasNEON, // MVNIv4i16 = 2842 |
| CEFBS_HasNEON, // MVNIv4i32 = 2843 |
| CEFBS_HasNEON, // MVNIv4s_msl = 2844 |
| CEFBS_HasNEON, // MVNIv8i16 = 2845 |
| CEFBS_HasSVE, // NANDS_PPzPP = 2846 |
| CEFBS_HasSVE, // NAND_PPzPP = 2847 |
| CEFBS_HasSVE2, // NBSL_ZZZZ_D = 2848 |
| CEFBS_HasSVE, // NEG_ZPmZ_B = 2849 |
| CEFBS_HasSVE, // NEG_ZPmZ_D = 2850 |
| CEFBS_HasSVE, // NEG_ZPmZ_H = 2851 |
| CEFBS_HasSVE, // NEG_ZPmZ_S = 2852 |
| CEFBS_HasNEON, // NEGv16i8 = 2853 |
| CEFBS_HasNEON, // NEGv1i64 = 2854 |
| CEFBS_HasNEON, // NEGv2i32 = 2855 |
| CEFBS_HasNEON, // NEGv2i64 = 2856 |
| CEFBS_HasNEON, // NEGv4i16 = 2857 |
| CEFBS_HasNEON, // NEGv4i32 = 2858 |
| CEFBS_HasNEON, // NEGv8i16 = 2859 |
| CEFBS_HasNEON, // NEGv8i8 = 2860 |
| CEFBS_HasSVE2, // NMATCH_PPzZZ_B = 2861 |
| CEFBS_HasSVE2, // NMATCH_PPzZZ_H = 2862 |
| CEFBS_HasSVE, // NORS_PPzPP = 2863 |
| CEFBS_HasSVE, // NOR_PPzPP = 2864 |
| CEFBS_HasSVE, // NOT_ZPmZ_B = 2865 |
| CEFBS_HasSVE, // NOT_ZPmZ_D = 2866 |
| CEFBS_HasSVE, // NOT_ZPmZ_H = 2867 |
| CEFBS_HasSVE, // NOT_ZPmZ_S = 2868 |
| CEFBS_HasNEON, // NOTv16i8 = 2869 |
| CEFBS_HasNEON, // NOTv8i8 = 2870 |
| CEFBS_HasSVE, // ORNS_PPzPP = 2871 |
| CEFBS_None, // ORNWrr = 2872 |
| CEFBS_None, // ORNWrs = 2873 |
| CEFBS_None, // ORNXrr = 2874 |
| CEFBS_None, // ORNXrs = 2875 |
| CEFBS_HasSVE, // ORN_PPzPP = 2876 |
| CEFBS_HasNEON, // ORNv16i8 = 2877 |
| CEFBS_HasNEON, // ORNv8i8 = 2878 |
| CEFBS_HasSVE, // ORRS_PPzPP = 2879 |
| CEFBS_None, // ORRWri = 2880 |
| CEFBS_None, // ORRWrr = 2881 |
| CEFBS_None, // ORRWrs = 2882 |
| CEFBS_None, // ORRXri = 2883 |
| CEFBS_None, // ORRXrr = 2884 |
| CEFBS_None, // ORRXrs = 2885 |
| CEFBS_HasSVE, // ORR_PPzPP = 2886 |
| CEFBS_HasSVE, // ORR_ZI = 2887 |
| CEFBS_HasSVE, // ORR_ZPmZ_B = 2888 |
| CEFBS_HasSVE, // ORR_ZPmZ_D = 2889 |
| CEFBS_HasSVE, // ORR_ZPmZ_H = 2890 |
| CEFBS_HasSVE, // ORR_ZPmZ_S = 2891 |
| CEFBS_HasSVE, // ORR_ZZZ = 2892 |
| CEFBS_HasNEON, // ORRv16i8 = 2893 |
| CEFBS_HasNEON, // ORRv2i32 = 2894 |
| CEFBS_HasNEON, // ORRv4i16 = 2895 |
| CEFBS_HasNEON, // ORRv4i32 = 2896 |
| CEFBS_HasNEON, // ORRv8i16 = 2897 |
| CEFBS_HasNEON, // ORRv8i8 = 2898 |
| CEFBS_HasSVE, // ORV_VPZ_B = 2899 |
| CEFBS_HasSVE, // ORV_VPZ_D = 2900 |
| CEFBS_HasSVE, // ORV_VPZ_H = 2901 |
| CEFBS_HasSVE, // ORV_VPZ_S = 2902 |
| CEFBS_HasPA, // PACDA = 2903 |
| CEFBS_HasPA, // PACDB = 2904 |
| CEFBS_HasPA, // PACDZA = 2905 |
| CEFBS_HasPA, // PACDZB = 2906 |
| CEFBS_HasPA, // PACGA = 2907 |
| CEFBS_HasPA, // PACIA = 2908 |
| CEFBS_None, // PACIA1716 = 2909 |
| CEFBS_None, // PACIASP = 2910 |
| CEFBS_None, // PACIAZ = 2911 |
| CEFBS_HasPA, // PACIB = 2912 |
| CEFBS_None, // PACIB1716 = 2913 |
| CEFBS_None, // PACIBSP = 2914 |
| CEFBS_None, // PACIBZ = 2915 |
| CEFBS_HasPA, // PACIZA = 2916 |
| CEFBS_HasPA, // PACIZB = 2917 |
| CEFBS_HasSVE, // PFALSE = 2918 |
| CEFBS_HasSVE, // PFIRST_B = 2919 |
| CEFBS_HasSVE2, // PMULLB_ZZZ_D = 2920 |
| CEFBS_HasSVE2, // PMULLB_ZZZ_H = 2921 |
| CEFBS_HasSVE2AES, // PMULLB_ZZZ_Q = 2922 |
| CEFBS_HasSVE2, // PMULLT_ZZZ_D = 2923 |
| CEFBS_HasSVE2, // PMULLT_ZZZ_H = 2924 |
| CEFBS_HasSVE2AES, // PMULLT_ZZZ_Q = 2925 |
| CEFBS_HasNEON, // PMULLv16i8 = 2926 |
| CEFBS_HasAES, // PMULLv1i64 = 2927 |
| CEFBS_HasAES, // PMULLv2i64 = 2928 |
| CEFBS_HasNEON, // PMULLv8i8 = 2929 |
| CEFBS_HasSVE2, // PMUL_ZZZ_B = 2930 |
| CEFBS_HasNEON, // PMULv16i8 = 2931 |
| CEFBS_HasNEON, // PMULv8i8 = 2932 |
| CEFBS_HasSVE, // PNEXT_B = 2933 |
| CEFBS_HasSVE, // PNEXT_D = 2934 |
| CEFBS_HasSVE, // PNEXT_H = 2935 |
| CEFBS_HasSVE, // PNEXT_S = 2936 |
| CEFBS_HasSVE, // PRFB_D_PZI = 2937 |
| CEFBS_HasSVE, // PRFB_D_SCALED = 2938 |
| CEFBS_HasSVE, // PRFB_D_SXTW_SCALED = 2939 |
| CEFBS_HasSVE, // PRFB_D_UXTW_SCALED = 2940 |
| CEFBS_HasSVE, // PRFB_PRI = 2941 |
| CEFBS_HasSVE, // PRFB_PRR = 2942 |
| CEFBS_HasSVE, // PRFB_S_PZI = 2943 |
| CEFBS_HasSVE, // PRFB_S_SXTW_SCALED = 2944 |
| CEFBS_HasSVE, // PRFB_S_UXTW_SCALED = 2945 |
| CEFBS_HasSVE, // PRFD_D_PZI = 2946 |
| CEFBS_HasSVE, // PRFD_D_SCALED = 2947 |
| CEFBS_HasSVE, // PRFD_D_SXTW_SCALED = 2948 |
| CEFBS_HasSVE, // PRFD_D_UXTW_SCALED = 2949 |
| CEFBS_HasSVE, // PRFD_PRI = 2950 |
| CEFBS_HasSVE, // PRFD_PRR = 2951 |
| CEFBS_HasSVE, // PRFD_S_PZI = 2952 |
| CEFBS_HasSVE, // PRFD_S_SXTW_SCALED = 2953 |
| CEFBS_HasSVE, // PRFD_S_UXTW_SCALED = 2954 |
| CEFBS_HasSVE, // PRFH_D_PZI = 2955 |
| CEFBS_HasSVE, // PRFH_D_SCALED = 2956 |
| CEFBS_HasSVE, // PRFH_D_SXTW_SCALED = 2957 |
| CEFBS_HasSVE, // PRFH_D_UXTW_SCALED = 2958 |
| CEFBS_HasSVE, // PRFH_PRI = 2959 |
| CEFBS_HasSVE, // PRFH_PRR = 2960 |
| CEFBS_HasSVE, // PRFH_S_PZI = 2961 |
| CEFBS_HasSVE, // PRFH_S_SXTW_SCALED = 2962 |
| CEFBS_HasSVE, // PRFH_S_UXTW_SCALED = 2963 |
| CEFBS_None, // PRFMl = 2964 |
| CEFBS_None, // PRFMroW = 2965 |
| CEFBS_None, // PRFMroX = 2966 |
| CEFBS_None, // PRFMui = 2967 |
| CEFBS_HasSVE, // PRFS_PRR = 2968 |
| CEFBS_None, // PRFUMi = 2969 |
| CEFBS_HasSVE, // PRFW_D_PZI = 2970 |
| CEFBS_HasSVE, // PRFW_D_SCALED = 2971 |
| CEFBS_HasSVE, // PRFW_D_SXTW_SCALED = 2972 |
| CEFBS_HasSVE, // PRFW_D_UXTW_SCALED = 2973 |
| CEFBS_HasSVE, // PRFW_PRI = 2974 |
| CEFBS_HasSVE, // PRFW_S_PZI = 2975 |
| CEFBS_HasSVE, // PRFW_S_SXTW_SCALED = 2976 |
| CEFBS_HasSVE, // PRFW_S_UXTW_SCALED = 2977 |
| CEFBS_HasSVE, // PTEST_PP = 2978 |
| CEFBS_HasSVE, // PTRUES_B = 2979 |
| CEFBS_HasSVE, // PTRUES_D = 2980 |
| CEFBS_HasSVE, // PTRUES_H = 2981 |
| CEFBS_HasSVE, // PTRUES_S = 2982 |
| CEFBS_HasSVE, // PTRUE_B = 2983 |
| CEFBS_HasSVE, // PTRUE_D = 2984 |
| CEFBS_HasSVE, // PTRUE_H = 2985 |
| CEFBS_HasSVE, // PTRUE_S = 2986 |
| CEFBS_HasSVE, // PUNPKHI_PP = 2987 |
| CEFBS_HasSVE, // PUNPKLO_PP = 2988 |
| CEFBS_HasSVE2, // RADDHNB_ZZZ_B = 2989 |
| CEFBS_HasSVE2, // RADDHNB_ZZZ_H = 2990 |
| CEFBS_HasSVE2, // RADDHNB_ZZZ_S = 2991 |
| CEFBS_HasSVE2, // RADDHNT_ZZZ_B = 2992 |
| CEFBS_HasSVE2, // RADDHNT_ZZZ_H = 2993 |
| CEFBS_HasSVE2, // RADDHNT_ZZZ_S = 2994 |
| CEFBS_HasNEON, // RADDHNv2i64_v2i32 = 2995 |
| CEFBS_HasNEON, // RADDHNv2i64_v4i32 = 2996 |
| CEFBS_HasNEON, // RADDHNv4i32_v4i16 = 2997 |
| CEFBS_HasNEON, // RADDHNv4i32_v8i16 = 2998 |
| CEFBS_HasNEON, // RADDHNv8i16_v16i8 = 2999 |
| CEFBS_HasNEON, // RADDHNv8i16_v8i8 = 3000 |
| CEFBS_HasSHA3, // RAX1 = 3001 |
| CEFBS_HasSVE2SHA3, // RAX1_ZZZ_D = 3002 |
| CEFBS_None, // RBITWr = 3003 |
| CEFBS_None, // RBITXr = 3004 |
| CEFBS_HasSVE, // RBIT_ZPmZ_B = 3005 |
| CEFBS_HasSVE, // RBIT_ZPmZ_D = 3006 |
| CEFBS_HasSVE, // RBIT_ZPmZ_H = 3007 |
| CEFBS_HasSVE, // RBIT_ZPmZ_S = 3008 |
| CEFBS_HasNEON, // RBITv16i8 = 3009 |
| CEFBS_HasNEON, // RBITv8i8 = 3010 |
| CEFBS_HasSVE, // RDFFRS_PPz = 3011 |
| CEFBS_HasSVE, // RDFFR_P = 3012 |
| CEFBS_HasSVE, // RDFFR_PPz = 3013 |
| CEFBS_HasSVE, // RDVLI_XI = 3014 |
| CEFBS_None, // RET = 3015 |
| CEFBS_HasPA, // RETAA = 3016 |
| CEFBS_HasPA, // RETAB = 3017 |
| CEFBS_None, // RET_ReallyLR = 3018 |
| CEFBS_None, // REV16Wr = 3019 |
| CEFBS_None, // REV16Xr = 3020 |
| CEFBS_HasNEON, // REV16v16i8 = 3021 |
| CEFBS_HasNEON, // REV16v8i8 = 3022 |
| CEFBS_None, // REV32Xr = 3023 |
| CEFBS_HasNEON, // REV32v16i8 = 3024 |
| CEFBS_HasNEON, // REV32v4i16 = 3025 |
| CEFBS_HasNEON, // REV32v8i16 = 3026 |
| CEFBS_HasNEON, // REV32v8i8 = 3027 |
| CEFBS_HasNEON, // REV64v16i8 = 3028 |
| CEFBS_HasNEON, // REV64v2i32 = 3029 |
| CEFBS_HasNEON, // REV64v4i16 = 3030 |
| CEFBS_HasNEON, // REV64v4i32 = 3031 |
| CEFBS_HasNEON, // REV64v8i16 = 3032 |
| CEFBS_HasNEON, // REV64v8i8 = 3033 |
| CEFBS_HasSVE, // REVB_ZPmZ_D = 3034 |
| CEFBS_HasSVE, // REVB_ZPmZ_H = 3035 |
| CEFBS_HasSVE, // REVB_ZPmZ_S = 3036 |
| CEFBS_HasSVE, // REVH_ZPmZ_D = 3037 |
| CEFBS_HasSVE, // REVH_ZPmZ_S = 3038 |
| CEFBS_HasSVE, // REVW_ZPmZ_D = 3039 |
| CEFBS_None, // REVWr = 3040 |
| CEFBS_None, // REVXr = 3041 |
| CEFBS_HasSVE, // REV_PP_B = 3042 |
| CEFBS_HasSVE, // REV_PP_D = 3043 |
| CEFBS_HasSVE, // REV_PP_H = 3044 |
| CEFBS_HasSVE, // REV_PP_S = 3045 |
| CEFBS_HasSVE, // REV_ZZ_B = 3046 |
| CEFBS_HasSVE, // REV_ZZ_D = 3047 |
| CEFBS_HasSVE, // REV_ZZ_H = 3048 |
| CEFBS_HasSVE, // REV_ZZ_S = 3049 |
| CEFBS_HasFMI, // RMIF = 3050 |
| CEFBS_None, // RORVWr = 3051 |
| CEFBS_None, // RORVXr = 3052 |
| CEFBS_HasSVE2, // RSHRNB_ZZI_B = 3053 |
| CEFBS_HasSVE2, // RSHRNB_ZZI_H = 3054 |
| CEFBS_HasSVE2, // RSHRNB_ZZI_S = 3055 |
| CEFBS_HasSVE2, // RSHRNT_ZZI_B = 3056 |
| CEFBS_HasSVE2, // RSHRNT_ZZI_H = 3057 |
| CEFBS_HasSVE2, // RSHRNT_ZZI_S = 3058 |
| CEFBS_HasNEON, // RSHRNv16i8_shift = 3059 |
| CEFBS_HasNEON, // RSHRNv2i32_shift = 3060 |
| CEFBS_HasNEON, // RSHRNv4i16_shift = 3061 |
| CEFBS_HasNEON, // RSHRNv4i32_shift = 3062 |
| CEFBS_HasNEON, // RSHRNv8i16_shift = 3063 |
| CEFBS_HasNEON, // RSHRNv8i8_shift = 3064 |
| CEFBS_HasSVE2, // RSUBHNB_ZZZ_B = 3065 |
| CEFBS_HasSVE2, // RSUBHNB_ZZZ_H = 3066 |
| CEFBS_HasSVE2, // RSUBHNB_ZZZ_S = 3067 |
| CEFBS_HasSVE2, // RSUBHNT_ZZZ_B = 3068 |
| CEFBS_HasSVE2, // RSUBHNT_ZZZ_H = 3069 |
| CEFBS_HasSVE2, // RSUBHNT_ZZZ_S = 3070 |
| CEFBS_HasNEON, // RSUBHNv2i64_v2i32 = 3071 |
| CEFBS_HasNEON, // RSUBHNv2i64_v4i32 = 3072 |
| CEFBS_HasNEON, // RSUBHNv4i32_v4i16 = 3073 |
| CEFBS_HasNEON, // RSUBHNv4i32_v8i16 = 3074 |
| CEFBS_HasNEON, // RSUBHNv8i16_v16i8 = 3075 |
| CEFBS_HasNEON, // RSUBHNv8i16_v8i8 = 3076 |
| CEFBS_HasSVE2, // SABALB_ZZZ_D = 3077 |
| CEFBS_HasSVE2, // SABALB_ZZZ_H = 3078 |
| CEFBS_HasSVE2, // SABALB_ZZZ_S = 3079 |
| CEFBS_HasSVE2, // SABALT_ZZZ_D = 3080 |
| CEFBS_HasSVE2, // SABALT_ZZZ_H = 3081 |
| CEFBS_HasSVE2, // SABALT_ZZZ_S = 3082 |
| CEFBS_HasNEON, // SABALv16i8_v8i16 = 3083 |
| CEFBS_HasNEON, // SABALv2i32_v2i64 = 3084 |
| CEFBS_HasNEON, // SABALv4i16_v4i32 = 3085 |
| CEFBS_HasNEON, // SABALv4i32_v2i64 = 3086 |
| CEFBS_HasNEON, // SABALv8i16_v4i32 = 3087 |
| CEFBS_HasNEON, // SABALv8i8_v8i16 = 3088 |
| CEFBS_HasSVE2, // SABA_ZZZ_B = 3089 |
| CEFBS_HasSVE2, // SABA_ZZZ_D = 3090 |
| CEFBS_HasSVE2, // SABA_ZZZ_H = 3091 |
| CEFBS_HasSVE2, // SABA_ZZZ_S = 3092 |
| CEFBS_HasNEON, // SABAv16i8 = 3093 |
| CEFBS_HasNEON, // SABAv2i32 = 3094 |
| CEFBS_HasNEON, // SABAv4i16 = 3095 |
| CEFBS_HasNEON, // SABAv4i32 = 3096 |
| CEFBS_HasNEON, // SABAv8i16 = 3097 |
| CEFBS_HasNEON, // SABAv8i8 = 3098 |
| CEFBS_HasSVE2, // SABDLB_ZZZ_D = 3099 |
| CEFBS_HasSVE2, // SABDLB_ZZZ_H = 3100 |
| CEFBS_HasSVE2, // SABDLB_ZZZ_S = 3101 |
| CEFBS_HasSVE2, // SABDLT_ZZZ_D = 3102 |
| CEFBS_HasSVE2, // SABDLT_ZZZ_H = 3103 |
| CEFBS_HasSVE2, // SABDLT_ZZZ_S = 3104 |
| CEFBS_HasNEON, // SABDLv16i8_v8i16 = 3105 |
| CEFBS_HasNEON, // SABDLv2i32_v2i64 = 3106 |
| CEFBS_HasNEON, // SABDLv4i16_v4i32 = 3107 |
| CEFBS_HasNEON, // SABDLv4i32_v2i64 = 3108 |
| CEFBS_HasNEON, // SABDLv8i16_v4i32 = 3109 |
| CEFBS_HasNEON, // SABDLv8i8_v8i16 = 3110 |
| CEFBS_HasSVE, // SABD_ZPmZ_B = 3111 |
| CEFBS_HasSVE, // SABD_ZPmZ_D = 3112 |
| CEFBS_HasSVE, // SABD_ZPmZ_H = 3113 |
| CEFBS_HasSVE, // SABD_ZPmZ_S = 3114 |
| CEFBS_HasNEON, // SABDv16i8 = 3115 |
| CEFBS_HasNEON, // SABDv2i32 = 3116 |
| CEFBS_HasNEON, // SABDv4i16 = 3117 |
| CEFBS_HasNEON, // SABDv4i32 = 3118 |
| CEFBS_HasNEON, // SABDv8i16 = 3119 |
| CEFBS_HasNEON, // SABDv8i8 = 3120 |
| CEFBS_HasSVE2, // SADALP_ZPmZ_D = 3121 |
| CEFBS_HasSVE2, // SADALP_ZPmZ_H = 3122 |
| CEFBS_HasSVE2, // SADALP_ZPmZ_S = 3123 |
| CEFBS_HasNEON, // SADALPv16i8_v8i16 = 3124 |
| CEFBS_HasNEON, // SADALPv2i32_v1i64 = 3125 |
| CEFBS_HasNEON, // SADALPv4i16_v2i32 = 3126 |
| CEFBS_HasNEON, // SADALPv4i32_v2i64 = 3127 |
| CEFBS_HasNEON, // SADALPv8i16_v4i32 = 3128 |
| CEFBS_HasNEON, // SADALPv8i8_v4i16 = 3129 |
| CEFBS_HasSVE2, // SADDLBT_ZZZ_D = 3130 |
| CEFBS_HasSVE2, // SADDLBT_ZZZ_H = 3131 |
| CEFBS_HasSVE2, // SADDLBT_ZZZ_S = 3132 |
| CEFBS_HasSVE2, // SADDLB_ZZZ_D = 3133 |
| CEFBS_HasSVE2, // SADDLB_ZZZ_H = 3134 |
| CEFBS_HasSVE2, // SADDLB_ZZZ_S = 3135 |
| CEFBS_HasNEON, // SADDLPv16i8_v8i16 = 3136 |
| CEFBS_HasNEON, // SADDLPv2i32_v1i64 = 3137 |
| CEFBS_HasNEON, // SADDLPv4i16_v2i32 = 3138 |
| CEFBS_HasNEON, // SADDLPv4i32_v2i64 = 3139 |
| CEFBS_HasNEON, // SADDLPv8i16_v4i32 = 3140 |
| CEFBS_HasNEON, // SADDLPv8i8_v4i16 = 3141 |
| CEFBS_HasSVE2, // SADDLT_ZZZ_D = 3142 |
| CEFBS_HasSVE2, // SADDLT_ZZZ_H = 3143 |
| CEFBS_HasSVE2, // SADDLT_ZZZ_S = 3144 |
| CEFBS_HasNEON, // SADDLVv16i8v = 3145 |
| CEFBS_HasNEON, // SADDLVv4i16v = 3146 |
| CEFBS_HasNEON, // SADDLVv4i32v = 3147 |
| CEFBS_HasNEON, // SADDLVv8i16v = 3148 |
| CEFBS_HasNEON, // SADDLVv8i8v = 3149 |
| CEFBS_HasNEON, // SADDLv16i8_v8i16 = 3150 |
| CEFBS_HasNEON, // SADDLv2i32_v2i64 = 3151 |
| CEFBS_HasNEON, // SADDLv4i16_v4i32 = 3152 |
| CEFBS_HasNEON, // SADDLv4i32_v2i64 = 3153 |
| CEFBS_HasNEON, // SADDLv8i16_v4i32 = 3154 |
| CEFBS_HasNEON, // SADDLv8i8_v8i16 = 3155 |
| CEFBS_HasSVE, // SADDV_VPZ_B = 3156 |
| CEFBS_HasSVE, // SADDV_VPZ_H = 3157 |
| CEFBS_HasSVE, // SADDV_VPZ_S = 3158 |
| CEFBS_HasSVE2, // SADDWB_ZZZ_D = 3159 |
| CEFBS_HasSVE2, // SADDWB_ZZZ_H = 3160 |
| CEFBS_HasSVE2, // SADDWB_ZZZ_S = 3161 |
| CEFBS_HasSVE2, // SADDWT_ZZZ_D = 3162 |
| CEFBS_HasSVE2, // SADDWT_ZZZ_H = 3163 |
| CEFBS_HasSVE2, // SADDWT_ZZZ_S = 3164 |
| CEFBS_HasNEON, // SADDWv16i8_v8i16 = 3165 |
| CEFBS_HasNEON, // SADDWv2i32_v2i64 = 3166 |
| CEFBS_HasNEON, // SADDWv4i16_v4i32 = 3167 |
| CEFBS_HasNEON, // SADDWv4i32_v2i64 = 3168 |
| CEFBS_HasNEON, // SADDWv8i16_v4i32 = 3169 |
| CEFBS_HasNEON, // SADDWv8i8_v8i16 = 3170 |
| CEFBS_HasSB, // SB = 3171 |
| CEFBS_HasSVE2, // SBCLB_ZZZ_D = 3172 |
| CEFBS_HasSVE2, // SBCLB_ZZZ_S = 3173 |
| CEFBS_HasSVE2, // SBCLT_ZZZ_D = 3174 |
| CEFBS_HasSVE2, // SBCLT_ZZZ_S = 3175 |
| CEFBS_None, // SBCSWr = 3176 |
| CEFBS_None, // SBCSXr = 3177 |
| CEFBS_None, // SBCWr = 3178 |
| CEFBS_None, // SBCXr = 3179 |
| CEFBS_None, // SBFMWri = 3180 |
| CEFBS_None, // SBFMXri = 3181 |
| CEFBS_HasFPARMv8, // SCVTFSWDri = 3182 |
| CEFBS_HasFullFP16, // SCVTFSWHri = 3183 |
| CEFBS_HasFPARMv8, // SCVTFSWSri = 3184 |
| CEFBS_HasFPARMv8, // SCVTFSXDri = 3185 |
| CEFBS_HasFullFP16, // SCVTFSXHri = 3186 |
| CEFBS_HasFPARMv8, // SCVTFSXSri = 3187 |
| CEFBS_HasFPARMv8, // SCVTFUWDri = 3188 |
| CEFBS_HasFullFP16, // SCVTFUWHri = 3189 |
| CEFBS_HasFPARMv8, // SCVTFUWSri = 3190 |
| CEFBS_HasFPARMv8, // SCVTFUXDri = 3191 |
| CEFBS_HasFullFP16, // SCVTFUXHri = 3192 |
| CEFBS_HasFPARMv8, // SCVTFUXSri = 3193 |
| CEFBS_HasSVE, // SCVTF_ZPmZ_DtoD = 3194 |
| CEFBS_HasSVE, // SCVTF_ZPmZ_DtoH = 3195 |
| CEFBS_HasSVE, // SCVTF_ZPmZ_DtoS = 3196 |
| CEFBS_HasSVE, // SCVTF_ZPmZ_HtoH = 3197 |
| CEFBS_HasSVE, // SCVTF_ZPmZ_StoD = 3198 |
| CEFBS_HasSVE, // SCVTF_ZPmZ_StoH = 3199 |
| CEFBS_HasSVE, // SCVTF_ZPmZ_StoS = 3200 |
| CEFBS_HasNEON, // SCVTFd = 3201 |
| CEFBS_HasNEON_HasFullFP16, // SCVTFh = 3202 |
| CEFBS_HasNEON, // SCVTFs = 3203 |
| CEFBS_HasNEON_HasFullFP16, // SCVTFv1i16 = 3204 |
| CEFBS_HasNEON, // SCVTFv1i32 = 3205 |
| CEFBS_HasNEON, // SCVTFv1i64 = 3206 |
| CEFBS_HasNEON, // SCVTFv2f32 = 3207 |
| CEFBS_HasNEON, // SCVTFv2f64 = 3208 |
| CEFBS_HasNEON, // SCVTFv2i32_shift = 3209 |
| CEFBS_HasNEON, // SCVTFv2i64_shift = 3210 |
| CEFBS_HasNEON_HasFullFP16, // SCVTFv4f16 = 3211 |
| CEFBS_HasNEON, // SCVTFv4f32 = 3212 |
| CEFBS_HasNEON_HasFullFP16, // SCVTFv4i16_shift = 3213 |
| CEFBS_HasNEON, // SCVTFv4i32_shift = 3214 |
| CEFBS_HasNEON_HasFullFP16, // SCVTFv8f16 = 3215 |
| CEFBS_HasNEON_HasFullFP16, // SCVTFv8i16_shift = 3216 |
| CEFBS_HasSVE, // SDIVR_ZPmZ_D = 3217 |
| CEFBS_HasSVE, // SDIVR_ZPmZ_S = 3218 |
| CEFBS_None, // SDIVWr = 3219 |
| CEFBS_None, // SDIVXr = 3220 |
| CEFBS_HasSVE, // SDIV_ZPmZ_D = 3221 |
| CEFBS_HasSVE, // SDIV_ZPmZ_S = 3222 |
| CEFBS_HasSVE, // SDOT_ZZZI_D = 3223 |
| CEFBS_HasSVE, // SDOT_ZZZI_S = 3224 |
| CEFBS_HasSVE, // SDOT_ZZZ_D = 3225 |
| CEFBS_HasSVE, // SDOT_ZZZ_S = 3226 |
| CEFBS_HasDotProd, // SDOTlanev16i8 = 3227 |
| CEFBS_HasDotProd, // SDOTlanev8i8 = 3228 |
| CEFBS_HasDotProd, // SDOTv16i8 = 3229 |
| CEFBS_HasDotProd, // SDOTv8i8 = 3230 |
| CEFBS_HasSVE, // SEL_PPPP = 3231 |
| CEFBS_HasSVE, // SEL_ZPZZ_B = 3232 |
| CEFBS_HasSVE, // SEL_ZPZZ_D = 3233 |
| CEFBS_HasSVE, // SEL_ZPZZ_H = 3234 |
| CEFBS_HasSVE, // SEL_ZPZZ_S = 3235 |
| CEFBS_HasFMI, // SETF16 = 3236 |
| CEFBS_HasFMI, // SETF8 = 3237 |
| CEFBS_HasSVE, // SETFFR = 3238 |
| CEFBS_HasSHA2, // SHA1Crrr = 3239 |
| CEFBS_HasSHA2, // SHA1Hrr = 3240 |
| CEFBS_HasSHA2, // SHA1Mrrr = 3241 |
| CEFBS_HasSHA2, // SHA1Prrr = 3242 |
| CEFBS_HasSHA2, // SHA1SU0rrr = 3243 |
| CEFBS_HasSHA2, // SHA1SU1rr = 3244 |
| CEFBS_HasSHA2, // SHA256H2rrr = 3245 |
| CEFBS_HasSHA2, // SHA256Hrrr = 3246 |
| CEFBS_HasSHA2, // SHA256SU0rr = 3247 |
| CEFBS_HasSHA2, // SHA256SU1rrr = 3248 |
| CEFBS_HasSHA3, // SHA512H = 3249 |
| CEFBS_HasSHA3, // SHA512H2 = 3250 |
| CEFBS_HasSHA3, // SHA512SU0 = 3251 |
| CEFBS_HasSHA3, // SHA512SU1 = 3252 |
| CEFBS_HasSVE2, // SHADD_ZPmZ_B = 3253 |
| CEFBS_HasSVE2, // SHADD_ZPmZ_D = 3254 |
| CEFBS_HasSVE2, // SHADD_ZPmZ_H = 3255 |
| CEFBS_HasSVE2, // SHADD_ZPmZ_S = 3256 |
| CEFBS_HasNEON, // SHADDv16i8 = 3257 |
| CEFBS_HasNEON, // SHADDv2i32 = 3258 |
| CEFBS_HasNEON, // SHADDv4i16 = 3259 |
| CEFBS_HasNEON, // SHADDv4i32 = 3260 |
| CEFBS_HasNEON, // SHADDv8i16 = 3261 |
| CEFBS_HasNEON, // SHADDv8i8 = 3262 |
| CEFBS_HasNEON, // SHLLv16i8 = 3263 |
| CEFBS_HasNEON, // SHLLv2i32 = 3264 |
| CEFBS_HasNEON, // SHLLv4i16 = 3265 |
| CEFBS_HasNEON, // SHLLv4i32 = 3266 |
| CEFBS_HasNEON, // SHLLv8i16 = 3267 |
| CEFBS_HasNEON, // SHLLv8i8 = 3268 |
| CEFBS_HasNEON, // SHLd = 3269 |
| CEFBS_HasNEON, // SHLv16i8_shift = 3270 |
| CEFBS_HasNEON, // SHLv2i32_shift = 3271 |
| CEFBS_HasNEON, // SHLv2i64_shift = 3272 |
| CEFBS_HasNEON, // SHLv4i16_shift = 3273 |
| CEFBS_HasNEON, // SHLv4i32_shift = 3274 |
| CEFBS_HasNEON, // SHLv8i16_shift = 3275 |
| CEFBS_HasNEON, // SHLv8i8_shift = 3276 |
| CEFBS_HasSVE2, // SHRNB_ZZI_B = 3277 |
| CEFBS_HasSVE2, // SHRNB_ZZI_H = 3278 |
| CEFBS_HasSVE2, // SHRNB_ZZI_S = 3279 |
| CEFBS_HasSVE2, // SHRNT_ZZI_B = 3280 |
| CEFBS_HasSVE2, // SHRNT_ZZI_H = 3281 |
| CEFBS_HasSVE2, // SHRNT_ZZI_S = 3282 |
| CEFBS_HasNEON, // SHRNv16i8_shift = 3283 |
| CEFBS_HasNEON, // SHRNv2i32_shift = 3284 |
| CEFBS_HasNEON, // SHRNv4i16_shift = 3285 |
| CEFBS_HasNEON, // SHRNv4i32_shift = 3286 |
| CEFBS_HasNEON, // SHRNv8i16_shift = 3287 |
| CEFBS_HasNEON, // SHRNv8i8_shift = 3288 |
| CEFBS_HasSVE2, // SHSUBR_ZPmZ_B = 3289 |
| CEFBS_HasSVE2, // SHSUBR_ZPmZ_D = 3290 |
| CEFBS_HasSVE2, // SHSUBR_ZPmZ_H = 3291 |
| CEFBS_HasSVE2, // SHSUBR_ZPmZ_S = 3292 |
| CEFBS_HasSVE2, // SHSUB_ZPmZ_B = 3293 |
| CEFBS_HasSVE2, // SHSUB_ZPmZ_D = 3294 |
| CEFBS_HasSVE2, // SHSUB_ZPmZ_H = 3295 |
| CEFBS_HasSVE2, // SHSUB_ZPmZ_S = 3296 |
| CEFBS_HasNEON, // SHSUBv16i8 = 3297 |
| CEFBS_HasNEON, // SHSUBv2i32 = 3298 |
| CEFBS_HasNEON, // SHSUBv4i16 = 3299 |
| CEFBS_HasNEON, // SHSUBv4i32 = 3300 |
| CEFBS_HasNEON, // SHSUBv8i16 = 3301 |
| CEFBS_HasNEON, // SHSUBv8i8 = 3302 |
| CEFBS_HasSVE2, // SLI_ZZI_B = 3303 |
| CEFBS_HasSVE2, // SLI_ZZI_D = 3304 |
| CEFBS_HasSVE2, // SLI_ZZI_H = 3305 |
| CEFBS_HasSVE2, // SLI_ZZI_S = 3306 |
| CEFBS_HasNEON, // SLId = 3307 |
| CEFBS_HasNEON, // SLIv16i8_shift = 3308 |
| CEFBS_HasNEON, // SLIv2i32_shift = 3309 |
| CEFBS_HasNEON, // SLIv2i64_shift = 3310 |
| CEFBS_HasNEON, // SLIv4i16_shift = 3311 |
| CEFBS_HasNEON, // SLIv4i32_shift = 3312 |
| CEFBS_HasNEON, // SLIv8i16_shift = 3313 |
| CEFBS_HasNEON, // SLIv8i8_shift = 3314 |
| CEFBS_HasSM4, // SM3PARTW1 = 3315 |
| CEFBS_HasSM4, // SM3PARTW2 = 3316 |
| CEFBS_HasSM4, // SM3SS1 = 3317 |
| CEFBS_HasSM4, // SM3TT1A = 3318 |
| CEFBS_HasSM4, // SM3TT1B = 3319 |
| CEFBS_HasSM4, // SM3TT2A = 3320 |
| CEFBS_HasSM4, // SM3TT2B = 3321 |
| CEFBS_HasSM4, // SM4E = 3322 |
| CEFBS_HasSVE2SM4, // SM4EKEY_ZZZ_S = 3323 |
| CEFBS_HasSM4, // SM4ENCKEY = 3324 |
| CEFBS_HasSVE2SM4, // SM4E_ZZZ_S = 3325 |
| CEFBS_None, // SMADDLrrr = 3326 |
| CEFBS_HasSVE2, // SMAXP_ZPmZ_B = 3327 |
| CEFBS_HasSVE2, // SMAXP_ZPmZ_D = 3328 |
| CEFBS_HasSVE2, // SMAXP_ZPmZ_H = 3329 |
| CEFBS_HasSVE2, // SMAXP_ZPmZ_S = 3330 |
| CEFBS_HasNEON, // SMAXPv16i8 = 3331 |
| CEFBS_HasNEON, // SMAXPv2i32 = 3332 |
| CEFBS_HasNEON, // SMAXPv4i16 = 3333 |
| CEFBS_HasNEON, // SMAXPv4i32 = 3334 |
| CEFBS_HasNEON, // SMAXPv8i16 = 3335 |
| CEFBS_HasNEON, // SMAXPv8i8 = 3336 |
| CEFBS_HasSVE, // SMAXV_VPZ_B = 3337 |
| CEFBS_HasSVE, // SMAXV_VPZ_D = 3338 |
| CEFBS_HasSVE, // SMAXV_VPZ_H = 3339 |
| CEFBS_HasSVE, // SMAXV_VPZ_S = 3340 |
| CEFBS_HasNEON, // SMAXVv16i8v = 3341 |
| CEFBS_HasNEON, // SMAXVv4i16v = 3342 |
| CEFBS_HasNEON, // SMAXVv4i32v = 3343 |
| CEFBS_HasNEON, // SMAXVv8i16v = 3344 |
| CEFBS_HasNEON, // SMAXVv8i8v = 3345 |
| CEFBS_HasSVE, // SMAX_ZI_B = 3346 |
| CEFBS_HasSVE, // SMAX_ZI_D = 3347 |
| CEFBS_HasSVE, // SMAX_ZI_H = 3348 |
| CEFBS_HasSVE, // SMAX_ZI_S = 3349 |
| CEFBS_HasSVE, // SMAX_ZPmZ_B = 3350 |
| CEFBS_HasSVE, // SMAX_ZPmZ_D = 3351 |
| CEFBS_HasSVE, // SMAX_ZPmZ_H = 3352 |
| CEFBS_HasSVE, // SMAX_ZPmZ_S = 3353 |
| CEFBS_HasNEON, // SMAXv16i8 = 3354 |
| CEFBS_HasNEON, // SMAXv2i32 = 3355 |
| CEFBS_HasNEON, // SMAXv4i16 = 3356 |
| CEFBS_HasNEON, // SMAXv4i32 = 3357 |
| CEFBS_HasNEON, // SMAXv8i16 = 3358 |
| CEFBS_HasNEON, // SMAXv8i8 = 3359 |
| CEFBS_None, // SMC = 3360 |
| CEFBS_HasSVE2, // SMINP_ZPmZ_B = 3361 |
| CEFBS_HasSVE2, // SMINP_ZPmZ_D = 3362 |
| CEFBS_HasSVE2, // SMINP_ZPmZ_H = 3363 |
| CEFBS_HasSVE2, // SMINP_ZPmZ_S = 3364 |
| CEFBS_HasNEON, // SMINPv16i8 = 3365 |
| CEFBS_HasNEON, // SMINPv2i32 = 3366 |
| CEFBS_HasNEON, // SMINPv4i16 = 3367 |
| CEFBS_HasNEON, // SMINPv4i32 = 3368 |
| CEFBS_HasNEON, // SMINPv8i16 = 3369 |
| CEFBS_HasNEON, // SMINPv8i8 = 3370 |
| CEFBS_HasSVE, // SMINV_VPZ_B = 3371 |
| CEFBS_HasSVE, // SMINV_VPZ_D = 3372 |
| CEFBS_HasSVE, // SMINV_VPZ_H = 3373 |
| CEFBS_HasSVE, // SMINV_VPZ_S = 3374 |
| CEFBS_HasNEON, // SMINVv16i8v = 3375 |
| CEFBS_HasNEON, // SMINVv4i16v = 3376 |
| CEFBS_HasNEON, // SMINVv4i32v = 3377 |
| CEFBS_HasNEON, // SMINVv8i16v = 3378 |
| CEFBS_HasNEON, // SMINVv8i8v = 3379 |
| CEFBS_HasSVE, // SMIN_ZI_B = 3380 |
| CEFBS_HasSVE, // SMIN_ZI_D = 3381 |
| CEFBS_HasSVE, // SMIN_ZI_H = 3382 |
| CEFBS_HasSVE, // SMIN_ZI_S = 3383 |
| CEFBS_HasSVE, // SMIN_ZPmZ_B = 3384 |
| CEFBS_HasSVE, // SMIN_ZPmZ_D = 3385 |
| CEFBS_HasSVE, // SMIN_ZPmZ_H = 3386 |
| CEFBS_HasSVE, // SMIN_ZPmZ_S = 3387 |
| CEFBS_HasNEON, // SMINv16i8 = 3388 |
| CEFBS_HasNEON, // SMINv2i32 = 3389 |
| CEFBS_HasNEON, // SMINv4i16 = 3390 |
| CEFBS_HasNEON, // SMINv4i32 = 3391 |
| CEFBS_HasNEON, // SMINv8i16 = 3392 |
| CEFBS_HasNEON, // SMINv8i8 = 3393 |
| CEFBS_HasSVE2, // SMLALB_ZZZI_D = 3394 |
| CEFBS_HasSVE2, // SMLALB_ZZZI_S = 3395 |
| CEFBS_HasSVE2, // SMLALB_ZZZ_D = 3396 |
| CEFBS_HasSVE2, // SMLALB_ZZZ_H = 3397 |
| CEFBS_HasSVE2, // SMLALB_ZZZ_S = 3398 |
| CEFBS_HasSVE2, // SMLALT_ZZZI_D = 3399 |
| CEFBS_HasSVE2, // SMLALT_ZZZI_S = 3400 |
| CEFBS_HasSVE2, // SMLALT_ZZZ_D = 3401 |
| CEFBS_HasSVE2, // SMLALT_ZZZ_H = 3402 |
| CEFBS_HasSVE2, // SMLALT_ZZZ_S = 3403 |
| CEFBS_HasNEON, // SMLALv16i8_v8i16 = 3404 |
| CEFBS_HasNEON, // SMLALv2i32_indexed = 3405 |
| CEFBS_HasNEON, // SMLALv2i32_v2i64 = 3406 |
| CEFBS_HasNEON, // SMLALv4i16_indexed = 3407 |
| CEFBS_HasNEON, // SMLALv4i16_v4i32 = 3408 |
| CEFBS_HasNEON, // SMLALv4i32_indexed = 3409 |
| CEFBS_HasNEON, // SMLALv4i32_v2i64 = 3410 |
| CEFBS_HasNEON, // SMLALv8i16_indexed = 3411 |
| CEFBS_HasNEON, // SMLALv8i16_v4i32 = 3412 |
| CEFBS_HasNEON, // SMLALv8i8_v8i16 = 3413 |
| CEFBS_HasSVE2, // SMLSLB_ZZZI_D = 3414 |
| CEFBS_HasSVE2, // SMLSLB_ZZZI_S = 3415 |
| CEFBS_HasSVE2, // SMLSLB_ZZZ_D = 3416 |
| CEFBS_HasSVE2, // SMLSLB_ZZZ_H = 3417 |
| CEFBS_HasSVE2, // SMLSLB_ZZZ_S = 3418 |
| CEFBS_HasSVE2, // SMLSLT_ZZZI_D = 3419 |
| CEFBS_HasSVE2, // SMLSLT_ZZZI_S = 3420 |
| CEFBS_HasSVE2, // SMLSLT_ZZZ_D = 3421 |
| CEFBS_HasSVE2, // SMLSLT_ZZZ_H = 3422 |
| CEFBS_HasSVE2, // SMLSLT_ZZZ_S = 3423 |
| CEFBS_HasNEON, // SMLSLv16i8_v8i16 = 3424 |
| CEFBS_HasNEON, // SMLSLv2i32_indexed = 3425 |
| CEFBS_HasNEON, // SMLSLv2i32_v2i64 = 3426 |
| CEFBS_HasNEON, // SMLSLv4i16_indexed = 3427 |
| CEFBS_HasNEON, // SMLSLv4i16_v4i32 = 3428 |
| CEFBS_HasNEON, // SMLSLv4i32_indexed = 3429 |
| CEFBS_HasNEON, // SMLSLv4i32_v2i64 = 3430 |
| CEFBS_HasNEON, // SMLSLv8i16_indexed = 3431 |
| CEFBS_HasNEON, // SMLSLv8i16_v4i32 = 3432 |
| CEFBS_HasNEON, // SMLSLv8i8_v8i16 = 3433 |
| CEFBS_HasNEON, // SMOVvi16to32 = 3434 |
| CEFBS_HasNEON, // SMOVvi16to64 = 3435 |
| CEFBS_HasNEON, // SMOVvi32to64 = 3436 |
| CEFBS_HasNEON, // SMOVvi8to32 = 3437 |
| CEFBS_HasNEON, // SMOVvi8to64 = 3438 |
| CEFBS_None, // SMSUBLrrr = 3439 |
| CEFBS_HasSVE, // SMULH_ZPmZ_B = 3440 |
| CEFBS_HasSVE, // SMULH_ZPmZ_D = 3441 |
| CEFBS_HasSVE, // SMULH_ZPmZ_H = 3442 |
| CEFBS_HasSVE, // SMULH_ZPmZ_S = 3443 |
| CEFBS_HasSVE2, // SMULH_ZZZ_B = 3444 |
| CEFBS_HasSVE2, // SMULH_ZZZ_D = 3445 |
| CEFBS_HasSVE2, // SMULH_ZZZ_H = 3446 |
| CEFBS_HasSVE2, // SMULH_ZZZ_S = 3447 |
| CEFBS_None, // SMULHrr = 3448 |
| CEFBS_HasSVE2, // SMULLB_ZZZI_D = 3449 |
| CEFBS_HasSVE2, // SMULLB_ZZZI_S = 3450 |
| CEFBS_HasSVE2, // SMULLB_ZZZ_D = 3451 |
| CEFBS_HasSVE2, // SMULLB_ZZZ_H = 3452 |
| CEFBS_HasSVE2, // SMULLB_ZZZ_S = 3453 |
| CEFBS_HasSVE2, // SMULLT_ZZZI_D = 3454 |
| CEFBS_HasSVE2, // SMULLT_ZZZI_S = 3455 |
| CEFBS_HasSVE2, // SMULLT_ZZZ_D = 3456 |
| CEFBS_HasSVE2, // SMULLT_ZZZ_H = 3457 |
| CEFBS_HasSVE2, // SMULLT_ZZZ_S = 3458 |
| CEFBS_HasNEON, // SMULLv16i8_v8i16 = 3459 |
| CEFBS_HasNEON, // SMULLv2i32_indexed = 3460 |
| CEFBS_HasNEON, // SMULLv2i32_v2i64 = 3461 |
| CEFBS_HasNEON, // SMULLv4i16_indexed = 3462 |
| CEFBS_HasNEON, // SMULLv4i16_v4i32 = 3463 |
| CEFBS_HasNEON, // SMULLv4i32_indexed = 3464 |
| CEFBS_HasNEON, // SMULLv4i32_v2i64 = 3465 |
| CEFBS_HasNEON, // SMULLv8i16_indexed = 3466 |
| CEFBS_HasNEON, // SMULLv8i16_v4i32 = 3467 |
| CEFBS_HasNEON, // SMULLv8i8_v8i16 = 3468 |
| CEFBS_None, // SPACE = 3469 |
| CEFBS_HasSVE2, // SPLICE_ZPZZ_B = 3470 |
| CEFBS_HasSVE2, // SPLICE_ZPZZ_D = 3471 |
| CEFBS_HasSVE2, // SPLICE_ZPZZ_H = 3472 |
| CEFBS_HasSVE2, // SPLICE_ZPZZ_S = 3473 |
| CEFBS_HasSVE, // SPLICE_ZPZ_B = 3474 |
| CEFBS_HasSVE, // SPLICE_ZPZ_D = 3475 |
| CEFBS_HasSVE, // SPLICE_ZPZ_H = 3476 |
| CEFBS_HasSVE, // SPLICE_ZPZ_S = 3477 |
| CEFBS_HasSVE2, // SQABS_ZPmZ_B = 3478 |
| CEFBS_HasSVE2, // SQABS_ZPmZ_D = 3479 |
| CEFBS_HasSVE2, // SQABS_ZPmZ_H = 3480 |
| CEFBS_HasSVE2, // SQABS_ZPmZ_S = 3481 |
| CEFBS_HasNEON, // SQABSv16i8 = 3482 |
| CEFBS_HasNEON, // SQABSv1i16 = 3483 |
| CEFBS_HasNEON, // SQABSv1i32 = 3484 |
| CEFBS_HasNEON, // SQABSv1i64 = 3485 |
| CEFBS_HasNEON, // SQABSv1i8 = 3486 |
| CEFBS_HasNEON, // SQABSv2i32 = 3487 |
| CEFBS_HasNEON, // SQABSv2i64 = 3488 |
| CEFBS_HasNEON, // SQABSv4i16 = 3489 |
| CEFBS_HasNEON, // SQABSv4i32 = 3490 |
| CEFBS_HasNEON, // SQABSv8i16 = 3491 |
| CEFBS_HasNEON, // SQABSv8i8 = 3492 |
| CEFBS_HasSVE, // SQADD_ZI_B = 3493 |
| CEFBS_HasSVE, // SQADD_ZI_D = 3494 |
| CEFBS_HasSVE, // SQADD_ZI_H = 3495 |
| CEFBS_HasSVE, // SQADD_ZI_S = 3496 |
| CEFBS_HasSVE2, // SQADD_ZPmZ_B = 3497 |
| CEFBS_HasSVE2, // SQADD_ZPmZ_D = 3498 |
| CEFBS_HasSVE2, // SQADD_ZPmZ_H = 3499 |
| CEFBS_HasSVE2, // SQADD_ZPmZ_S = 3500 |
| CEFBS_HasSVE, // SQADD_ZZZ_B = 3501 |
| CEFBS_HasSVE, // SQADD_ZZZ_D = 3502 |
| CEFBS_HasSVE, // SQADD_ZZZ_H = 3503 |
| CEFBS_HasSVE, // SQADD_ZZZ_S = 3504 |
| CEFBS_HasNEON, // SQADDv16i8 = 3505 |
| CEFBS_HasNEON, // SQADDv1i16 = 3506 |
| CEFBS_HasNEON, // SQADDv1i32 = 3507 |
| CEFBS_HasNEON, // SQADDv1i64 = 3508 |
| CEFBS_HasNEON, // SQADDv1i8 = 3509 |
| CEFBS_HasNEON, // SQADDv2i32 = 3510 |
| CEFBS_HasNEON, // SQADDv2i64 = 3511 |
| CEFBS_HasNEON, // SQADDv4i16 = 3512 |
| CEFBS_HasNEON, // SQADDv4i32 = 3513 |
| CEFBS_HasNEON, // SQADDv8i16 = 3514 |
| CEFBS_HasNEON, // SQADDv8i8 = 3515 |
| CEFBS_HasSVE2, // SQCADD_ZZI_B = 3516 |
| CEFBS_HasSVE2, // SQCADD_ZZI_D = 3517 |
| CEFBS_HasSVE2, // SQCADD_ZZI_H = 3518 |
| CEFBS_HasSVE2, // SQCADD_ZZI_S = 3519 |
| CEFBS_HasSVE, // SQDECB_XPiI = 3520 |
| CEFBS_HasSVE, // SQDECB_XPiWdI = 3521 |
| CEFBS_HasSVE, // SQDECD_XPiI = 3522 |
| CEFBS_HasSVE, // SQDECD_XPiWdI = 3523 |
| CEFBS_HasSVE, // SQDECD_ZPiI = 3524 |
| CEFBS_HasSVE, // SQDECH_XPiI = 3525 |
| CEFBS_HasSVE, // SQDECH_XPiWdI = 3526 |
| CEFBS_HasSVE, // SQDECH_ZPiI = 3527 |
| CEFBS_HasSVE, // SQDECP_XPWd_B = 3528 |
| CEFBS_HasSVE, // SQDECP_XPWd_D = 3529 |
| CEFBS_HasSVE, // SQDECP_XPWd_H = 3530 |
| CEFBS_HasSVE, // SQDECP_XPWd_S = 3531 |
| CEFBS_HasSVE, // SQDECP_XP_B = 3532 |
| CEFBS_HasSVE, // SQDECP_XP_D = 3533 |
| CEFBS_HasSVE, // SQDECP_XP_H = 3534 |
| CEFBS_HasSVE, // SQDECP_XP_S = 3535 |
| CEFBS_HasSVE, // SQDECP_ZP_D = 3536 |
| CEFBS_HasSVE, // SQDECP_ZP_H = 3537 |
| CEFBS_HasSVE, // SQDECP_ZP_S = 3538 |
| CEFBS_HasSVE, // SQDECW_XPiI = 3539 |
| CEFBS_HasSVE, // SQDECW_XPiWdI = 3540 |
| CEFBS_HasSVE, // SQDECW_ZPiI = 3541 |
| CEFBS_HasSVE2, // SQDMLALBT_ZZZ_D = 3542 |
| CEFBS_HasSVE2, // SQDMLALBT_ZZZ_H = 3543 |
| CEFBS_HasSVE2, // SQDMLALBT_ZZZ_S = 3544 |
| CEFBS_HasSVE2, // SQDMLALB_ZZZI_D = 3545 |
| CEFBS_HasSVE2, // SQDMLALB_ZZZI_S = 3546 |
| CEFBS_HasSVE2, // SQDMLALB_ZZZ_D = 3547 |
| CEFBS_HasSVE2, // SQDMLALB_ZZZ_H = 3548 |
| CEFBS_HasSVE2, // SQDMLALB_ZZZ_S = 3549 |
| CEFBS_HasSVE2, // SQDMLALT_ZZZI_D = 3550 |
| CEFBS_HasSVE2, // SQDMLALT_ZZZI_S = 3551 |
| CEFBS_HasSVE2, // SQDMLALT_ZZZ_D = 3552 |
| CEFBS_HasSVE2, // SQDMLALT_ZZZ_H = 3553 |
| CEFBS_HasSVE2, // SQDMLALT_ZZZ_S = 3554 |
| CEFBS_HasNEON, // SQDMLALi16 = 3555 |
| CEFBS_HasNEON, // SQDMLALi32 = 3556 |
| CEFBS_HasNEON, // SQDMLALv1i32_indexed = 3557 |
| CEFBS_HasNEON, // SQDMLALv1i64_indexed = 3558 |
| CEFBS_HasNEON, // SQDMLALv2i32_indexed = 3559 |
| CEFBS_HasNEON, // SQDMLALv2i32_v2i64 = 3560 |
| CEFBS_HasNEON, // SQDMLALv4i16_indexed = 3561 |
| CEFBS_HasNEON, // SQDMLALv4i16_v4i32 = 3562 |
| CEFBS_HasNEON, // SQDMLALv4i32_indexed = 3563 |
| CEFBS_HasNEON, // SQDMLALv4i32_v2i64 = 3564 |
| CEFBS_HasNEON, // SQDMLALv8i16_indexed = 3565 |
| CEFBS_HasNEON, // SQDMLALv8i16_v4i32 = 3566 |
| CEFBS_HasSVE2, // SQDMLSLBT_ZZZ_D = 3567 |
| CEFBS_HasSVE2, // SQDMLSLBT_ZZZ_H = 3568 |
| CEFBS_HasSVE2, // SQDMLSLBT_ZZZ_S = 3569 |
| CEFBS_HasSVE2, // SQDMLSLB_ZZZI_D = 3570 |
| CEFBS_HasSVE2, // SQDMLSLB_ZZZI_S = 3571 |
| CEFBS_HasSVE2, // SQDMLSLB_ZZZ_D = 3572 |
| CEFBS_HasSVE2, // SQDMLSLB_ZZZ_H = 3573 |
| CEFBS_HasSVE2, // SQDMLSLB_ZZZ_S = 3574 |
| CEFBS_HasSVE2, // SQDMLSLT_ZZZI_D = 3575 |
| CEFBS_HasSVE2, // SQDMLSLT_ZZZI_S = 3576 |
| CEFBS_HasSVE2, // SQDMLSLT_ZZZ_D = 3577 |
| CEFBS_HasSVE2, // SQDMLSLT_ZZZ_H = 3578 |
| CEFBS_HasSVE2, // SQDMLSLT_ZZZ_S = 3579 |
| CEFBS_HasNEON, // SQDMLSLi16 = 3580 |
| CEFBS_HasNEON, // SQDMLSLi32 = 3581 |
| CEFBS_HasNEON, // SQDMLSLv1i32_indexed = 3582 |
| CEFBS_HasNEON, // SQDMLSLv1i64_indexed = 3583 |
| CEFBS_HasNEON, // SQDMLSLv2i32_indexed = 3584 |
| CEFBS_HasNEON, // SQDMLSLv2i32_v2i64 = 3585 |
| CEFBS_HasNEON, // SQDMLSLv4i16_indexed = 3586 |
| CEFBS_HasNEON, // SQDMLSLv4i16_v4i32 = 3587 |
| CEFBS_HasNEON, // SQDMLSLv4i32_indexed = 3588 |
| CEFBS_HasNEON, // SQDMLSLv4i32_v2i64 = 3589 |
| CEFBS_HasNEON, // SQDMLSLv8i16_indexed = 3590 |
| CEFBS_HasNEON, // SQDMLSLv8i16_v4i32 = 3591 |
| CEFBS_HasSVE2, // SQDMULH_ZZZI_D = 3592 |
| CEFBS_HasSVE2, // SQDMULH_ZZZI_H = 3593 |
| CEFBS_HasSVE2, // SQDMULH_ZZZI_S = 3594 |
| CEFBS_HasSVE2, // SQDMULH_ZZZ_B = 3595 |
| CEFBS_HasSVE2, // SQDMULH_ZZZ_D = 3596 |
| CEFBS_HasSVE2, // SQDMULH_ZZZ_H = 3597 |
| CEFBS_HasSVE2, // SQDMULH_ZZZ_S = 3598 |
| CEFBS_HasNEON, // SQDMULHv1i16 = 3599 |
| CEFBS_HasNEON, // SQDMULHv1i16_indexed = 3600 |
| CEFBS_HasNEON, // SQDMULHv1i32 = 3601 |
| CEFBS_HasNEON, // SQDMULHv1i32_indexed = 3602 |
| CEFBS_HasNEON, // SQDMULHv2i32 = 3603 |
| CEFBS_HasNEON, // SQDMULHv2i32_indexed = 3604 |
| CEFBS_HasNEON, // SQDMULHv4i16 = 3605 |
| CEFBS_HasNEON, // SQDMULHv4i16_indexed = 3606 |
| CEFBS_HasNEON, // SQDMULHv4i32 = 3607 |
| CEFBS_HasNEON, // SQDMULHv4i32_indexed = 3608 |
| CEFBS_HasNEON, // SQDMULHv8i16 = 3609 |
| CEFBS_HasNEON, // SQDMULHv8i16_indexed = 3610 |
| CEFBS_HasSVE2, // SQDMULLB_ZZZI_D = 3611 |
| CEFBS_HasSVE2, // SQDMULLB_ZZZI_S = 3612 |
| CEFBS_HasSVE2, // SQDMULLB_ZZZ_D = 3613 |
| CEFBS_HasSVE2, // SQDMULLB_ZZZ_H = 3614 |
| CEFBS_HasSVE2, // SQDMULLB_ZZZ_S = 3615 |
| CEFBS_HasSVE2, // SQDMULLT_ZZZI_D = 3616 |
| CEFBS_HasSVE2, // SQDMULLT_ZZZI_S = 3617 |
| CEFBS_HasSVE2, // SQDMULLT_ZZZ_D = 3618 |
| CEFBS_HasSVE2, // SQDMULLT_ZZZ_H = 3619 |
| CEFBS_HasSVE2, // SQDMULLT_ZZZ_S = 3620 |
| CEFBS_HasNEON, // SQDMULLi16 = 3621 |
| CEFBS_HasNEON, // SQDMULLi32 = 3622 |
| CEFBS_HasNEON, // SQDMULLv1i32_indexed = 3623 |
| CEFBS_HasNEON, // SQDMULLv1i64_indexed = 3624 |
| CEFBS_HasNEON, // SQDMULLv2i32_indexed = 3625 |
| CEFBS_HasNEON, // SQDMULLv2i32_v2i64 = 3626 |
| CEFBS_HasNEON, // SQDMULLv4i16_indexed = 3627 |
| CEFBS_HasNEON, // SQDMULLv4i16_v4i32 = 3628 |
| CEFBS_HasNEON, // SQDMULLv4i32_indexed = 3629 |
| CEFBS_HasNEON, // SQDMULLv4i32_v2i64 = 3630 |
| CEFBS_HasNEON, // SQDMULLv8i16_indexed = 3631 |
| CEFBS_HasNEON, // SQDMULLv8i16_v4i32 = 3632 |
| CEFBS_HasSVE, // SQINCB_XPiI = 3633 |
| CEFBS_HasSVE, // SQINCB_XPiWdI = 3634 |
| CEFBS_HasSVE, // SQINCD_XPiI = 3635 |
| CEFBS_HasSVE, // SQINCD_XPiWdI = 3636 |
| CEFBS_HasSVE, // SQINCD_ZPiI = 3637 |
| CEFBS_HasSVE, // SQINCH_XPiI = 3638 |
| CEFBS_HasSVE, // SQINCH_XPiWdI = 3639 |
| CEFBS_HasSVE, // SQINCH_ZPiI = 3640 |
| CEFBS_HasSVE, // SQINCP_XPWd_B = 3641 |
| CEFBS_HasSVE, // SQINCP_XPWd_D = 3642 |
| CEFBS_HasSVE, // SQINCP_XPWd_H = 3643 |
| CEFBS_HasSVE, // SQINCP_XPWd_S = 3644 |
| CEFBS_HasSVE, // SQINCP_XP_B = 3645 |
| CEFBS_HasSVE, // SQINCP_XP_D = 3646 |
| CEFBS_HasSVE, // SQINCP_XP_H = 3647 |
| CEFBS_HasSVE, // SQINCP_XP_S = 3648 |
| CEFBS_HasSVE, // SQINCP_ZP_D = 3649 |
| CEFBS_HasSVE, // SQINCP_ZP_H = 3650 |
| CEFBS_HasSVE, // SQINCP_ZP_S = 3651 |
| CEFBS_HasSVE, // SQINCW_XPiI = 3652 |
| CEFBS_HasSVE, // SQINCW_XPiWdI = 3653 |
| CEFBS_HasSVE, // SQINCW_ZPiI = 3654 |
| CEFBS_HasSVE2, // SQNEG_ZPmZ_B = 3655 |
| CEFBS_HasSVE2, // SQNEG_ZPmZ_D = 3656 |
| CEFBS_HasSVE2, // SQNEG_ZPmZ_H = 3657 |
| CEFBS_HasSVE2, // SQNEG_ZPmZ_S = 3658 |
| CEFBS_HasNEON, // SQNEGv16i8 = 3659 |
| CEFBS_HasNEON, // SQNEGv1i16 = 3660 |
| CEFBS_HasNEON, // SQNEGv1i32 = 3661 |
| CEFBS_HasNEON, // SQNEGv1i64 = 3662 |
| CEFBS_HasNEON, // SQNEGv1i8 = 3663 |
| CEFBS_HasNEON, // SQNEGv2i32 = 3664 |
| CEFBS_HasNEON, // SQNEGv2i64 = 3665 |
| CEFBS_HasNEON, // SQNEGv4i16 = 3666 |
| CEFBS_HasNEON, // SQNEGv4i32 = 3667 |
| CEFBS_HasNEON, // SQNEGv8i16 = 3668 |
| CEFBS_HasNEON, // SQNEGv8i8 = 3669 |
| CEFBS_HasSVE2, // SQRDCMLAH_ZZZI_H = 3670 |
| CEFBS_HasSVE2, // SQRDCMLAH_ZZZI_S = 3671 |
| CEFBS_HasSVE2, // SQRDCMLAH_ZZZ_B = 3672 |
| CEFBS_HasSVE2, // SQRDCMLAH_ZZZ_D = 3673 |
| CEFBS_HasSVE2, // SQRDCMLAH_ZZZ_H = 3674 |
| CEFBS_HasSVE2, // SQRDCMLAH_ZZZ_S = 3675 |
| CEFBS_HasSVE2, // SQRDMLAH_ZZZI_D = 3676 |
| CEFBS_HasSVE2, // SQRDMLAH_ZZZI_H = 3677 |
| CEFBS_HasSVE2, // SQRDMLAH_ZZZI_S = 3678 |
| CEFBS_HasSVE2, // SQRDMLAH_ZZZ_B = 3679 |
| CEFBS_HasSVE2, // SQRDMLAH_ZZZ_D = 3680 |
| CEFBS_HasSVE2, // SQRDMLAH_ZZZ_H = 3681 |
| CEFBS_HasSVE2, // SQRDMLAH_ZZZ_S = 3682 |
| CEFBS_HasNEON_HasRDM, // SQRDMLAHi16_indexed = 3683 |
| CEFBS_HasNEON_HasRDM, // SQRDMLAHi32_indexed = 3684 |
| CEFBS_HasRDM, // SQRDMLAHv1i16 = 3685 |
| CEFBS_HasRDM, // SQRDMLAHv1i32 = 3686 |
| CEFBS_HasNEON_HasRDM, // SQRDMLAHv2i32 = 3687 |
| CEFBS_HasNEON_HasRDM, // SQRDMLAHv2i32_indexed = 3688 |
| CEFBS_HasNEON_HasRDM, // SQRDMLAHv4i16 = 3689 |
| CEFBS_HasNEON_HasRDM, // SQRDMLAHv4i16_indexed = 3690 |
| CEFBS_HasNEON_HasRDM, // SQRDMLAHv4i32 = 3691 |
| CEFBS_HasNEON_HasRDM, // SQRDMLAHv4i32_indexed = 3692 |
| CEFBS_HasNEON_HasRDM, // SQRDMLAHv8i16 = 3693 |
| CEFBS_HasNEON_HasRDM, // SQRDMLAHv8i16_indexed = 3694 |
| CEFBS_HasSVE2, // SQRDMLSH_ZZZI_D = 3695 |
| CEFBS_HasSVE2, // SQRDMLSH_ZZZI_H = 3696 |
| CEFBS_HasSVE2, // SQRDMLSH_ZZZI_S = 3697 |
| CEFBS_HasSVE2, // SQRDMLSH_ZZZ_B = 3698 |
| CEFBS_HasSVE2, // SQRDMLSH_ZZZ_D = 3699 |
| CEFBS_HasSVE2, // SQRDMLSH_ZZZ_H = 3700 |
| CEFBS_HasSVE2, // SQRDMLSH_ZZZ_S = 3701 |
| CEFBS_HasNEON_HasRDM, // SQRDMLSHi16_indexed = 3702 |
| CEFBS_HasNEON_HasRDM, // SQRDMLSHi32_indexed = 3703 |
| CEFBS_HasRDM, // SQRDMLSHv1i16 = 3704 |
| CEFBS_HasRDM, // SQRDMLSHv1i32 = 3705 |
| CEFBS_HasNEON_HasRDM, // SQRDMLSHv2i32 = 3706 |
| CEFBS_HasNEON_HasRDM, // SQRDMLSHv2i32_indexed = 3707 |
| CEFBS_HasNEON_HasRDM, // SQRDMLSHv4i16 = 3708 |
| CEFBS_HasNEON_HasRDM, // SQRDMLSHv4i16_indexed = 3709 |
| CEFBS_HasNEON_HasRDM, // SQRDMLSHv4i32 = 3710 |
| CEFBS_HasNEON_HasRDM, // SQRDMLSHv4i32_indexed = 3711 |
| CEFBS_HasNEON_HasRDM, // SQRDMLSHv8i16 = 3712 |
| CEFBS_HasNEON_HasRDM, // SQRDMLSHv8i16_indexed = 3713 |
| CEFBS_HasSVE2, // SQRDMULH_ZZZI_D = 3714 |
| CEFBS_HasSVE2, // SQRDMULH_ZZZI_H = 3715 |
| CEFBS_HasSVE2, // SQRDMULH_ZZZI_S = 3716 |
| CEFBS_HasSVE2, // SQRDMULH_ZZZ_B = 3717 |
| CEFBS_HasSVE2, // SQRDMULH_ZZZ_D = 3718 |
| CEFBS_HasSVE2, // SQRDMULH_ZZZ_H = 3719 |
| CEFBS_HasSVE2, // SQRDMULH_ZZZ_S = 3720 |
| CEFBS_HasNEON, // SQRDMULHv1i16 = 3721 |
| CEFBS_HasNEON, // SQRDMULHv1i16_indexed = 3722 |
| CEFBS_HasNEON, // SQRDMULHv1i32 = 3723 |
| CEFBS_HasNEON, // SQRDMULHv1i32_indexed = 3724 |
| CEFBS_HasNEON, // SQRDMULHv2i32 = 3725 |
| CEFBS_HasNEON, // SQRDMULHv2i32_indexed = 3726 |
| CEFBS_HasNEON, // SQRDMULHv4i16 = 3727 |
| CEFBS_HasNEON, // SQRDMULHv4i16_indexed = 3728 |
| CEFBS_HasNEON, // SQRDMULHv4i32 = 3729 |
| CEFBS_HasNEON, // SQRDMULHv4i32_indexed = 3730 |
| CEFBS_HasNEON, // SQRDMULHv8i16 = 3731 |
| CEFBS_HasNEON, // SQRDMULHv8i16_indexed = 3732 |
| CEFBS_HasSVE2, // SQRSHLR_ZPmZ_B = 3733 |
| CEFBS_HasSVE2, // SQRSHLR_ZPmZ_D = 3734 |
| CEFBS_HasSVE2, // SQRSHLR_ZPmZ_H = 3735 |
| CEFBS_HasSVE2, // SQRSHLR_ZPmZ_S = 3736 |
| CEFBS_HasSVE2, // SQRSHL_ZPmZ_B = 3737 |
| CEFBS_HasSVE2, // SQRSHL_ZPmZ_D = 3738 |
| CEFBS_HasSVE2, // SQRSHL_ZPmZ_H = 3739 |
| CEFBS_HasSVE2, // SQRSHL_ZPmZ_S = 3740 |
| CEFBS_HasNEON, // SQRSHLv16i8 = 3741 |
| CEFBS_HasNEON, // SQRSHLv1i16 = 3742 |
| CEFBS_HasNEON, // SQRSHLv1i32 = 3743 |
| CEFBS_HasNEON, // SQRSHLv1i64 = 3744 |
| CEFBS_HasNEON, // SQRSHLv1i8 = 3745 |
| CEFBS_HasNEON, // SQRSHLv2i32 = 3746 |
| CEFBS_HasNEON, // SQRSHLv2i64 = 3747 |
| CEFBS_HasNEON, // SQRSHLv4i16 = 3748 |
| CEFBS_HasNEON, // SQRSHLv4i32 = 3749 |
| CEFBS_HasNEON, // SQRSHLv8i16 = 3750 |
| CEFBS_HasNEON, // SQRSHLv8i8 = 3751 |
| CEFBS_HasSVE2, // SQRSHRNB_ZZI_B = 3752 |
| CEFBS_HasSVE2, // SQRSHRNB_ZZI_H = 3753 |
| CEFBS_HasSVE2, // SQRSHRNB_ZZI_S = 3754 |
| CEFBS_HasSVE2, // SQRSHRNT_ZZI_B = 3755 |
| CEFBS_HasSVE2, // SQRSHRNT_ZZI_H = 3756 |
| CEFBS_HasSVE2, // SQRSHRNT_ZZI_S = 3757 |
| CEFBS_HasNEON, // SQRSHRNb = 3758 |
| CEFBS_HasNEON, // SQRSHRNh = 3759 |
| CEFBS_HasNEON, // SQRSHRNs = 3760 |
| CEFBS_HasNEON, // SQRSHRNv16i8_shift = 3761 |
| CEFBS_HasNEON, // SQRSHRNv2i32_shift = 3762 |
| CEFBS_HasNEON, // SQRSHRNv4i16_shift = 3763 |
| CEFBS_HasNEON, // SQRSHRNv4i32_shift = 3764 |
| CEFBS_HasNEON, // SQRSHRNv8i16_shift = 3765 |
| CEFBS_HasNEON, // SQRSHRNv8i8_shift = 3766 |
| CEFBS_HasSVE2, // SQRSHRUNB_ZZI_B = 3767 |
| CEFBS_HasSVE2, // SQRSHRUNB_ZZI_H = 3768 |
| CEFBS_HasSVE2, // SQRSHRUNB_ZZI_S = 3769 |
| CEFBS_HasSVE2, // SQRSHRUNT_ZZI_B = 3770 |
| CEFBS_HasSVE2, // SQRSHRUNT_ZZI_H = 3771 |
| CEFBS_HasSVE2, // SQRSHRUNT_ZZI_S = 3772 |
| CEFBS_HasNEON, // SQRSHRUNb = 3773 |
| CEFBS_HasNEON, // SQRSHRUNh = 3774 |
| CEFBS_HasNEON, // SQRSHRUNs = 3775 |
| CEFBS_HasNEON, // SQRSHRUNv16i8_shift = 3776 |
| CEFBS_HasNEON, // SQRSHRUNv2i32_shift = 3777 |
| CEFBS_HasNEON, // SQRSHRUNv4i16_shift = 3778 |
| CEFBS_HasNEON, // SQRSHRUNv4i32_shift = 3779 |
| CEFBS_HasNEON, // SQRSHRUNv8i16_shift = 3780 |
| CEFBS_HasNEON, // SQRSHRUNv8i8_shift = 3781 |
| CEFBS_HasSVE2, // SQSHLR_ZPmZ_B = 3782 |
| CEFBS_HasSVE2, // SQSHLR_ZPmZ_D = 3783 |
| CEFBS_HasSVE2, // SQSHLR_ZPmZ_H = 3784 |
| CEFBS_HasSVE2, // SQSHLR_ZPmZ_S = 3785 |
| CEFBS_HasSVE2, // SQSHLU_ZPmI_B = 3786 |
| CEFBS_HasSVE2, // SQSHLU_ZPmI_D = 3787 |
| CEFBS_HasSVE2, // SQSHLU_ZPmI_H = 3788 |
| CEFBS_HasSVE2, // SQSHLU_ZPmI_S = 3789 |
| CEFBS_HasNEON, // SQSHLUb = 3790 |
| CEFBS_HasNEON, // SQSHLUd = 3791 |
| CEFBS_HasNEON, // SQSHLUh = 3792 |
| CEFBS_HasNEON, // SQSHLUs = 3793 |
| CEFBS_HasNEON, // SQSHLUv16i8_shift = 3794 |
| CEFBS_HasNEON, // SQSHLUv2i32_shift = 3795 |
| CEFBS_HasNEON, // SQSHLUv2i64_shift = 3796 |
| CEFBS_HasNEON, // SQSHLUv4i16_shift = 3797 |
| CEFBS_HasNEON, // SQSHLUv4i32_shift = 3798 |
| CEFBS_HasNEON, // SQSHLUv8i16_shift = 3799 |
| CEFBS_HasNEON, // SQSHLUv8i8_shift = 3800 |
| CEFBS_HasSVE2, // SQSHL_ZPmI_B = 3801 |
| CEFBS_HasSVE2, // SQSHL_ZPmI_D = 3802 |
| CEFBS_HasSVE2, // SQSHL_ZPmI_H = 3803 |
| CEFBS_HasSVE2, // SQSHL_ZPmI_S = 3804 |
| CEFBS_HasSVE2, // SQSHL_ZPmZ_B = 3805 |
| CEFBS_HasSVE2, // SQSHL_ZPmZ_D = 3806 |
| CEFBS_HasSVE2, // SQSHL_ZPmZ_H = 3807 |
| CEFBS_HasSVE2, // SQSHL_ZPmZ_S = 3808 |
| CEFBS_HasNEON, // SQSHLb = 3809 |
| CEFBS_HasNEON, // SQSHLd = 3810 |
| CEFBS_HasNEON, // SQSHLh = 3811 |
| CEFBS_HasNEON, // SQSHLs = 3812 |
| CEFBS_HasNEON, // SQSHLv16i8 = 3813 |
| CEFBS_HasNEON, // SQSHLv16i8_shift = 3814 |
| CEFBS_HasNEON, // SQSHLv1i16 = 3815 |
| CEFBS_HasNEON, // SQSHLv1i32 = 3816 |
| CEFBS_HasNEON, // SQSHLv1i64 = 3817 |
| CEFBS_HasNEON, // SQSHLv1i8 = 3818 |
| CEFBS_HasNEON, // SQSHLv2i32 = 3819 |
| CEFBS_HasNEON, // SQSHLv2i32_shift = 3820 |
| CEFBS_HasNEON, // SQSHLv2i64 = 3821 |
| CEFBS_HasNEON, // SQSHLv2i64_shift = 3822 |
| CEFBS_HasNEON, // SQSHLv4i16 = 3823 |
| CEFBS_HasNEON, // SQSHLv4i16_shift = 3824 |
| CEFBS_HasNEON, // SQSHLv4i32 = 3825 |
| CEFBS_HasNEON, // SQSHLv4i32_shift = 3826 |
| CEFBS_HasNEON, // SQSHLv8i16 = 3827 |
| CEFBS_HasNEON, // SQSHLv8i16_shift = 3828 |
| CEFBS_HasNEON, // SQSHLv8i8 = 3829 |
| CEFBS_HasNEON, // SQSHLv8i8_shift = 3830 |
| CEFBS_HasSVE2, // SQSHRNB_ZZI_B = 3831 |
| CEFBS_HasSVE2, // SQSHRNB_ZZI_H = 3832 |
| CEFBS_HasSVE2, // SQSHRNB_ZZI_S = 3833 |
| CEFBS_HasSVE2, // SQSHRNT_ZZI_B = 3834 |
| CEFBS_HasSVE2, // SQSHRNT_ZZI_H = 3835 |
| CEFBS_HasSVE2, // SQSHRNT_ZZI_S = 3836 |
| CEFBS_HasNEON, // SQSHRNb = 3837 |
| CEFBS_HasNEON, // SQSHRNh = 3838 |
| CEFBS_HasNEON, // SQSHRNs = 3839 |
| CEFBS_HasNEON, // SQSHRNv16i8_shift = 3840 |
| CEFBS_HasNEON, // SQSHRNv2i32_shift = 3841 |
| CEFBS_HasNEON, // SQSHRNv4i16_shift = 3842 |
| CEFBS_HasNEON, // SQSHRNv4i32_shift = 3843 |
| CEFBS_HasNEON, // SQSHRNv8i16_shift = 3844 |
| CEFBS_HasNEON, // SQSHRNv8i8_shift = 3845 |
| CEFBS_HasSVE2, // SQSHRUNB_ZZI_B = 3846 |
| CEFBS_HasSVE2, // SQSHRUNB_ZZI_H = 3847 |
| CEFBS_HasSVE2, // SQSHRUNB_ZZI_S = 3848 |
| CEFBS_HasSVE2, // SQSHRUNT_ZZI_B = 3849 |
| CEFBS_HasSVE2, // SQSHRUNT_ZZI_H = 3850 |
| CEFBS_HasSVE2, // SQSHRUNT_ZZI_S = 3851 |
| CEFBS_HasNEON, // SQSHRUNb = 3852 |
| CEFBS_HasNEON, // SQSHRUNh = 3853 |
| CEFBS_HasNEON, // SQSHRUNs = 3854 |
| CEFBS_HasNEON, // SQSHRUNv16i8_shift = 3855 |
| CEFBS_HasNEON, // SQSHRUNv2i32_shift = 3856 |
| CEFBS_HasNEON, // SQSHRUNv4i16_shift = 3857 |
| CEFBS_HasNEON, // SQSHRUNv4i32_shift = 3858 |
| CEFBS_HasNEON, // SQSHRUNv8i16_shift = 3859 |
| CEFBS_HasNEON, // SQSHRUNv8i8_shift = 3860 |
| CEFBS_HasSVE2, // SQSUBR_ZPmZ_B = 3861 |
| CEFBS_HasSVE2, // SQSUBR_ZPmZ_D = 3862 |
| CEFBS_HasSVE2, // SQSUBR_ZPmZ_H = 3863 |
| CEFBS_HasSVE2, // SQSUBR_ZPmZ_S = 3864 |
| CEFBS_HasSVE, // SQSUB_ZI_B = 3865 |
| CEFBS_HasSVE, // SQSUB_ZI_D = 3866 |
| CEFBS_HasSVE, // SQSUB_ZI_H = 3867 |
| CEFBS_HasSVE, // SQSUB_ZI_S = 3868 |
| CEFBS_HasSVE2, // SQSUB_ZPmZ_B = 3869 |
| CEFBS_HasSVE2, // SQSUB_ZPmZ_D = 3870 |
| CEFBS_HasSVE2, // SQSUB_ZPmZ_H = 3871 |
| CEFBS_HasSVE2, // SQSUB_ZPmZ_S = 3872 |
| CEFBS_HasSVE, // SQSUB_ZZZ_B = 3873 |
| CEFBS_HasSVE, // SQSUB_ZZZ_D = 3874 |
| CEFBS_HasSVE, // SQSUB_ZZZ_H = 3875 |
| CEFBS_HasSVE, // SQSUB_ZZZ_S = 3876 |
| CEFBS_HasNEON, // SQSUBv16i8 = 3877 |
| CEFBS_HasNEON, // SQSUBv1i16 = 3878 |
| CEFBS_HasNEON, // SQSUBv1i32 = 3879 |
| CEFBS_HasNEON, // SQSUBv1i64 = 3880 |
| CEFBS_HasNEON, // SQSUBv1i8 = 3881 |
| CEFBS_HasNEON, // SQSUBv2i32 = 3882 |
| CEFBS_HasNEON, // SQSUBv2i64 = 3883 |
| CEFBS_HasNEON, // SQSUBv4i16 = 3884 |
| CEFBS_HasNEON, // SQSUBv4i32 = 3885 |
| CEFBS_HasNEON, // SQSUBv8i16 = 3886 |
| CEFBS_HasNEON, // SQSUBv8i8 = 3887 |
| CEFBS_HasSVE2, // SQXTNB_ZZ_B = 3888 |
| CEFBS_HasSVE2, // SQXTNB_ZZ_H = 3889 |
| CEFBS_HasSVE2, // SQXTNB_ZZ_S = 3890 |
| CEFBS_HasSVE2, // SQXTNT_ZZ_B = 3891 |
| CEFBS_HasSVE2, // SQXTNT_ZZ_H = 3892 |
| CEFBS_HasSVE2, // SQXTNT_ZZ_S = 3893 |
| CEFBS_HasNEON, // SQXTNv16i8 = 3894 |
| CEFBS_HasNEON, // SQXTNv1i16 = 3895 |
| CEFBS_HasNEON, // SQXTNv1i32 = 3896 |
| CEFBS_HasNEON, // SQXTNv1i8 = 3897 |
| CEFBS_HasNEON, // SQXTNv2i32 = 3898 |
| CEFBS_HasNEON, // SQXTNv4i16 = 3899 |
| CEFBS_HasNEON, // SQXTNv4i32 = 3900 |
| CEFBS_HasNEON, // SQXTNv8i16 = 3901 |
| CEFBS_HasNEON, // SQXTNv8i8 = 3902 |
| CEFBS_HasSVE2, // SQXTUNB_ZZ_B = 3903 |
| CEFBS_HasSVE2, // SQXTUNB_ZZ_H = 3904 |
| CEFBS_HasSVE2, // SQXTUNB_ZZ_S = 3905 |
| CEFBS_HasSVE2, // SQXTUNT_ZZ_B = 3906 |
| CEFBS_HasSVE2, // SQXTUNT_ZZ_H = 3907 |
| CEFBS_HasSVE2, // SQXTUNT_ZZ_S = 3908 |
| CEFBS_HasNEON, // SQXTUNv16i8 = 3909 |
| CEFBS_HasNEON, // SQXTUNv1i16 = 3910 |
| CEFBS_HasNEON, // SQXTUNv1i32 = 3911 |
| CEFBS_HasNEON, // SQXTUNv1i8 = 3912 |
| CEFBS_HasNEON, // SQXTUNv2i32 = 3913 |
| CEFBS_HasNEON, // SQXTUNv4i16 = 3914 |
| CEFBS_HasNEON, // SQXTUNv4i32 = 3915 |
| CEFBS_HasNEON, // SQXTUNv8i16 = 3916 |
| CEFBS_HasNEON, // SQXTUNv8i8 = 3917 |
| CEFBS_HasSVE2, // SRHADD_ZPmZ_B = 3918 |
| CEFBS_HasSVE2, // SRHADD_ZPmZ_D = 3919 |
| CEFBS_HasSVE2, // SRHADD_ZPmZ_H = 3920 |
| CEFBS_HasSVE2, // SRHADD_ZPmZ_S = 3921 |
| CEFBS_HasNEON, // SRHADDv16i8 = 3922 |
| CEFBS_HasNEON, // SRHADDv2i32 = 3923 |
| CEFBS_HasNEON, // SRHADDv4i16 = 3924 |
| CEFBS_HasNEON, // SRHADDv4i32 = 3925 |
| CEFBS_HasNEON, // SRHADDv8i16 = 3926 |
| CEFBS_HasNEON, // SRHADDv8i8 = 3927 |
| CEFBS_HasSVE2, // SRI_ZZI_B = 3928 |
| CEFBS_HasSVE2, // SRI_ZZI_D = 3929 |
| CEFBS_HasSVE2, // SRI_ZZI_H = 3930 |
| CEFBS_HasSVE2, // SRI_ZZI_S = 3931 |
| CEFBS_HasNEON, // SRId = 3932 |
| CEFBS_HasNEON, // SRIv16i8_shift = 3933 |
| CEFBS_HasNEON, // SRIv2i32_shift = 3934 |
| CEFBS_HasNEON, // SRIv2i64_shift = 3935 |
| CEFBS_HasNEON, // SRIv4i16_shift = 3936 |
| CEFBS_HasNEON, // SRIv4i32_shift = 3937 |
| CEFBS_HasNEON, // SRIv8i16_shift = 3938 |
| CEFBS_HasNEON, // SRIv8i8_shift = 3939 |
| CEFBS_HasSVE2, // SRSHLR_ZPmZ_B = 3940 |
| CEFBS_HasSVE2, // SRSHLR_ZPmZ_D = 3941 |
| CEFBS_HasSVE2, // SRSHLR_ZPmZ_H = 3942 |
| CEFBS_HasSVE2, // SRSHLR_ZPmZ_S = 3943 |
| CEFBS_HasSVE2, // SRSHL_ZPmZ_B = 3944 |
| CEFBS_HasSVE2, // SRSHL_ZPmZ_D = 3945 |
| CEFBS_HasSVE2, // SRSHL_ZPmZ_H = 3946 |
| CEFBS_HasSVE2, // SRSHL_ZPmZ_S = 3947 |
| CEFBS_HasNEON, // SRSHLv16i8 = 3948 |
| CEFBS_HasNEON, // SRSHLv1i64 = 3949 |
| CEFBS_HasNEON, // SRSHLv2i32 = 3950 |
| CEFBS_HasNEON, // SRSHLv2i64 = 3951 |
| CEFBS_HasNEON, // SRSHLv4i16 = 3952 |
| CEFBS_HasNEON, // SRSHLv4i32 = 3953 |
| CEFBS_HasNEON, // SRSHLv8i16 = 3954 |
| CEFBS_HasNEON, // SRSHLv8i8 = 3955 |
| CEFBS_HasSVE2, // SRSHR_ZPmI_B = 3956 |
| CEFBS_HasSVE2, // SRSHR_ZPmI_D = 3957 |
| CEFBS_HasSVE2, // SRSHR_ZPmI_H = 3958 |
| CEFBS_HasSVE2, // SRSHR_ZPmI_S = 3959 |
| CEFBS_HasNEON, // SRSHRd = 3960 |
| CEFBS_HasNEON, // SRSHRv16i8_shift = 3961 |
| CEFBS_HasNEON, // SRSHRv2i32_shift = 3962 |
| CEFBS_HasNEON, // SRSHRv2i64_shift = 3963 |
| CEFBS_HasNEON, // SRSHRv4i16_shift = 3964 |
| CEFBS_HasNEON, // SRSHRv4i32_shift = 3965 |
| CEFBS_HasNEON, // SRSHRv8i16_shift = 3966 |
| CEFBS_HasNEON, // SRSHRv8i8_shift = 3967 |
| CEFBS_HasSVE2, // SRSRA_ZZI_B = 3968 |
| CEFBS_HasSVE2, // SRSRA_ZZI_D = 3969 |
| CEFBS_HasSVE2, // SRSRA_ZZI_H = 3970 |
| CEFBS_HasSVE2, // SRSRA_ZZI_S = 3971 |
| CEFBS_HasNEON, // SRSRAd = 3972 |
| CEFBS_HasNEON, // SRSRAv16i8_shift = 3973 |
| CEFBS_HasNEON, // SRSRAv2i32_shift = 3974 |
| CEFBS_HasNEON, // SRSRAv2i64_shift = 3975 |
| CEFBS_HasNEON, // SRSRAv4i16_shift = 3976 |
| CEFBS_HasNEON, // SRSRAv4i32_shift = 3977 |
| CEFBS_HasNEON, // SRSRAv8i16_shift = 3978 |
| CEFBS_HasNEON, // SRSRAv8i8_shift = 3979 |
| CEFBS_HasSVE2, // SSHLLB_ZZI_D = 3980 |
| CEFBS_HasSVE2, // SSHLLB_ZZI_H = 3981 |
| CEFBS_HasSVE2, // SSHLLB_ZZI_S = 3982 |
| CEFBS_HasSVE2, // SSHLLT_ZZI_D = 3983 |
| CEFBS_HasSVE2, // SSHLLT_ZZI_H = 3984 |
| CEFBS_HasSVE2, // SSHLLT_ZZI_S = 3985 |
| CEFBS_HasNEON, // SSHLLv16i8_shift = 3986 |
| CEFBS_HasNEON, // SSHLLv2i32_shift = 3987 |
| CEFBS_HasNEON, // SSHLLv4i16_shift = 3988 |
| CEFBS_HasNEON, // SSHLLv4i32_shift = 3989 |
| CEFBS_HasNEON, // SSHLLv8i16_shift = 3990 |
| CEFBS_HasNEON, // SSHLLv8i8_shift = 3991 |
| CEFBS_HasNEON, // SSHLv16i8 = 3992 |
| CEFBS_HasNEON, // SSHLv1i64 = 3993 |
| CEFBS_HasNEON, // SSHLv2i32 = 3994 |
| CEFBS_HasNEON, // SSHLv2i64 = 3995 |
| CEFBS_HasNEON, // SSHLv4i16 = 3996 |
| CEFBS_HasNEON, // SSHLv4i32 = 3997 |
| CEFBS_HasNEON, // SSHLv8i16 = 3998 |
| CEFBS_HasNEON, // SSHLv8i8 = 3999 |
| CEFBS_HasNEON, // SSHRd = 4000 |
| CEFBS_HasNEON, // SSHRv16i8_shift = 4001 |
| CEFBS_HasNEON, // SSHRv2i32_shift = 4002 |
| CEFBS_HasNEON, // SSHRv2i64_shift = 4003 |
| CEFBS_HasNEON, // SSHRv4i16_shift = 4004 |
| CEFBS_HasNEON, // SSHRv4i32_shift = 4005 |
| CEFBS_HasNEON, // SSHRv8i16_shift = 4006 |
| CEFBS_HasNEON, // SSHRv8i8_shift = 4007 |
| CEFBS_HasSVE2, // SSRA_ZZI_B = 4008 |
| CEFBS_HasSVE2, // SSRA_ZZI_D = 4009 |
| CEFBS_HasSVE2, // SSRA_ZZI_H = 4010 |
| CEFBS_HasSVE2, // SSRA_ZZI_S = 4011 |
| CEFBS_HasNEON, // SSRAd = 4012 |
| CEFBS_HasNEON, // SSRAv16i8_shift = 4013 |
| CEFBS_HasNEON, // SSRAv2i32_shift = 4014 |
| CEFBS_HasNEON, // SSRAv2i64_shift = 4015 |
| CEFBS_HasNEON, // SSRAv4i16_shift = 4016 |
| CEFBS_HasNEON, // SSRAv4i32_shift = 4017 |
| CEFBS_HasNEON, // SSRAv8i16_shift = 4018 |
| CEFBS_HasNEON, // SSRAv8i8_shift = 4019 |
| CEFBS_HasSVE, // SST1B_D_IMM = 4020 |
| CEFBS_HasSVE, // SST1B_D_REAL = 4021 |
| CEFBS_HasSVE, // SST1B_D_SXTW = 4022 |
| CEFBS_HasSVE, // SST1B_D_UXTW = 4023 |
| CEFBS_HasSVE, // SST1B_S_IMM = 4024 |
| CEFBS_HasSVE, // SST1B_S_SXTW = 4025 |
| CEFBS_HasSVE, // SST1B_S_UXTW = 4026 |
| CEFBS_HasSVE, // SST1D_IMM = 4027 |
| CEFBS_HasSVE, // SST1D_REAL = 4028 |
| CEFBS_HasSVE, // SST1D_SCALED_SCALED_REAL = 4029 |
| CEFBS_HasSVE, // SST1D_SXTW = 4030 |
| CEFBS_HasSVE, // SST1D_SXTW_SCALED = 4031 |
| CEFBS_HasSVE, // SST1D_UXTW = 4032 |
| CEFBS_HasSVE, // SST1D_UXTW_SCALED = 4033 |
| CEFBS_HasSVE, // SST1H_D_IMM = 4034 |
| CEFBS_HasSVE, // SST1H_D_REAL = 4035 |
| CEFBS_HasSVE, // SST1H_D_SCALED_SCALED_REAL = 4036 |
| CEFBS_HasSVE, // SST1H_D_SXTW = 4037 |
| CEFBS_HasSVE, // SST1H_D_SXTW_SCALED = 4038 |
| CEFBS_HasSVE, // SST1H_D_UXTW = 4039 |
| CEFBS_HasSVE, // SST1H_D_UXTW_SCALED = 4040 |
| CEFBS_HasSVE, // SST1H_S_IMM = 4041 |
| CEFBS_HasSVE, // SST1H_S_SXTW = 4042 |
| CEFBS_HasSVE, // SST1H_S_SXTW_SCALED = 4043 |
| CEFBS_HasSVE, // SST1H_S_UXTW = 4044 |
| CEFBS_HasSVE, // SST1H_S_UXTW_SCALED = 4045 |
| CEFBS_HasSVE, // SST1W_D_IMM = 4046 |
| CEFBS_HasSVE, // SST1W_D_REAL = 4047 |
| CEFBS_HasSVE, // SST1W_D_SCALED_SCALED_REAL = 4048 |
| CEFBS_HasSVE, // SST1W_D_SXTW = 4049 |
| CEFBS_HasSVE, // SST1W_D_SXTW_SCALED = 4050 |
| CEFBS_HasSVE, // SST1W_D_UXTW = 4051 |
| CEFBS_HasSVE, // SST1W_D_UXTW_SCALED = 4052 |
| CEFBS_HasSVE, // SST1W_IMM = 4053 |
| CEFBS_HasSVE, // SST1W_SXTW = 4054 |
| CEFBS_HasSVE, // SST1W_SXTW_SCALED = 4055 |
| CEFBS_HasSVE, // SST1W_UXTW = 4056 |
| CEFBS_HasSVE, // SST1W_UXTW_SCALED = 4057 |
| CEFBS_HasSVE2, // SSUBLBT_ZZZ_D = 4058 |
| CEFBS_HasSVE2, // SSUBLBT_ZZZ_H = 4059 |
| CEFBS_HasSVE2, // SSUBLBT_ZZZ_S = 4060 |
| CEFBS_HasSVE2, // SSUBLB_ZZZ_D = 4061 |
| CEFBS_HasSVE2, // SSUBLB_ZZZ_H = 4062 |
| CEFBS_HasSVE2, // SSUBLB_ZZZ_S = 4063 |
| CEFBS_HasSVE2, // SSUBLTB_ZZZ_D = 4064 |
| CEFBS_HasSVE2, // SSUBLTB_ZZZ_H = 4065 |
| CEFBS_HasSVE2, // SSUBLTB_ZZZ_S = 4066 |
| CEFBS_HasSVE2, // SSUBLT_ZZZ_D = 4067 |
| CEFBS_HasSVE2, // SSUBLT_ZZZ_H = 4068 |
| CEFBS_HasSVE2, // SSUBLT_ZZZ_S = 4069 |
| CEFBS_HasNEON, // SSUBLv16i8_v8i16 = 4070 |
| CEFBS_HasNEON, // SSUBLv2i32_v2i64 = 4071 |
| CEFBS_HasNEON, // SSUBLv4i16_v4i32 = 4072 |
| CEFBS_HasNEON, // SSUBLv4i32_v2i64 = 4073 |
| CEFBS_HasNEON, // SSUBLv8i16_v4i32 = 4074 |
| CEFBS_HasNEON, // SSUBLv8i8_v8i16 = 4075 |
| CEFBS_HasSVE2, // SSUBWB_ZZZ_D = 4076 |
| CEFBS_HasSVE2, // SSUBWB_ZZZ_H = 4077 |
| CEFBS_HasSVE2, // SSUBWB_ZZZ_S = 4078 |
| CEFBS_HasSVE2, // SSUBWT_ZZZ_D = 4079 |
| CEFBS_HasSVE2, // SSUBWT_ZZZ_H = 4080 |
| CEFBS_HasSVE2, // SSUBWT_ZZZ_S = 4081 |
| CEFBS_HasNEON, // SSUBWv16i8_v8i16 = 4082 |
| CEFBS_HasNEON, // SSUBWv2i32_v2i64 = 4083 |
| CEFBS_HasNEON, // SSUBWv4i16_v4i32 = 4084 |
| CEFBS_HasNEON, // SSUBWv4i32_v2i64 = 4085 |
| CEFBS_HasNEON, // SSUBWv8i16_v4i32 = 4086 |
| CEFBS_HasNEON, // SSUBWv8i8_v8i16 = 4087 |
| CEFBS_HasSVE, // ST1B = 4088 |
| CEFBS_HasSVE, // ST1B_D = 4089 |
| CEFBS_HasSVE, // ST1B_D_IMM = 4090 |
| CEFBS_HasSVE, // ST1B_H = 4091 |
| CEFBS_HasSVE, // ST1B_H_IMM = 4092 |
| CEFBS_HasSVE, // ST1B_IMM = 4093 |
| CEFBS_HasSVE, // ST1B_S = 4094 |
| CEFBS_HasSVE, // ST1B_S_IMM = 4095 |
| CEFBS_HasSVE, // ST1D = 4096 |
| CEFBS_HasSVE, // ST1D_IMM = 4097 |
| CEFBS_HasNEON, // ST1Fourv16b = 4098 |
| CEFBS_HasNEON, // ST1Fourv16b_POST = 4099 |
| CEFBS_HasNEON, // ST1Fourv1d = 4100 |
| CEFBS_HasNEON, // ST1Fourv1d_POST = 4101 |
| CEFBS_HasNEON, // ST1Fourv2d = 4102 |
| CEFBS_HasNEON, // ST1Fourv2d_POST = 4103 |
| CEFBS_HasNEON, // ST1Fourv2s = 4104 |
| CEFBS_HasNEON, // ST1Fourv2s_POST = 4105 |
| CEFBS_HasNEON, // ST1Fourv4h = 4106 |
| CEFBS_HasNEON, // ST1Fourv4h_POST = 4107 |
| CEFBS_HasNEON, // ST1Fourv4s = 4108 |
| CEFBS_HasNEON, // ST1Fourv4s_POST = 4109 |
| CEFBS_HasNEON, // ST1Fourv8b = 4110 |
| CEFBS_HasNEON, // ST1Fourv8b_POST = 4111 |
| CEFBS_HasNEON, // ST1Fourv8h = 4112 |
| CEFBS_HasNEON, // ST1Fourv8h_POST = 4113 |
| CEFBS_HasSVE, // ST1H = 4114 |
| CEFBS_HasSVE, // ST1H_D = 4115 |
| CEFBS_HasSVE, // ST1H_D_IMM = 4116 |
| CEFBS_HasSVE, // ST1H_IMM = 4117 |
| CEFBS_HasSVE, // ST1H_S = 4118 |
| CEFBS_HasSVE, // ST1H_S_IMM = 4119 |
| CEFBS_HasNEON, // ST1Onev16b = 4120 |
| CEFBS_HasNEON, // ST1Onev16b_POST = 4121 |
| CEFBS_HasNEON, // ST1Onev1d = 4122 |
| CEFBS_HasNEON, // ST1Onev1d_POST = 4123 |
| CEFBS_HasNEON, // ST1Onev2d = 4124 |
| CEFBS_HasNEON, // ST1Onev2d_POST = 4125 |
| CEFBS_HasNEON, // ST1Onev2s = 4126 |
| CEFBS_HasNEON, // ST1Onev2s_POST = 4127 |
| CEFBS_HasNEON, // ST1Onev4h = 4128 |
| CEFBS_HasNEON, // ST1Onev4h_POST = 4129 |
| CEFBS_HasNEON, // ST1Onev4s = 4130 |
| CEFBS_HasNEON, // ST1Onev4s_POST = 4131 |
| CEFBS_HasNEON, // ST1Onev8b = 4132 |
| CEFBS_HasNEON, // ST1Onev8b_POST = 4133 |
| CEFBS_HasNEON, // ST1Onev8h = 4134 |
| CEFBS_HasNEON, // ST1Onev8h_POST = 4135 |
| CEFBS_HasNEON, // ST1Threev16b = 4136 |
| CEFBS_HasNEON, // ST1Threev16b_POST = 4137 |
| CEFBS_HasNEON, // ST1Threev1d = 4138 |
| CEFBS_HasNEON, // ST1Threev1d_POST = 4139 |
| CEFBS_HasNEON, // ST1Threev2d = 4140 |
| CEFBS_HasNEON, // ST1Threev2d_POST = 4141 |
| CEFBS_HasNEON, // ST1Threev2s = 4142 |
| CEFBS_HasNEON, // ST1Threev2s_POST = 4143 |
| CEFBS_HasNEON, // ST1Threev4h = 4144 |
| CEFBS_HasNEON, // ST1Threev4h_POST = 4145 |
| CEFBS_HasNEON, // ST1Threev4s = 4146 |
| CEFBS_HasNEON, // ST1Threev4s_POST = 4147 |
| CEFBS_HasNEON, // ST1Threev8b = 4148 |
| CEFBS_HasNEON, // ST1Threev8b_POST = 4149 |
| CEFBS_HasNEON, // ST1Threev8h = 4150 |
| CEFBS_HasNEON, // ST1Threev8h_POST = 4151 |
| CEFBS_HasNEON, // ST1Twov16b = 4152 |
| CEFBS_HasNEON, // ST1Twov16b_POST = 4153 |
| CEFBS_HasNEON, // ST1Twov1d = 4154 |
| CEFBS_HasNEON, // ST1Twov1d_POST = 4155 |
| CEFBS_HasNEON, // ST1Twov2d = 4156 |
| CEFBS_HasNEON, // ST1Twov2d_POST = 4157 |
| CEFBS_HasNEON, // ST1Twov2s = 4158 |
| CEFBS_HasNEON, // ST1Twov2s_POST = 4159 |
| CEFBS_HasNEON, // ST1Twov4h = 4160 |
| CEFBS_HasNEON, // ST1Twov4h_POST = 4161 |
| CEFBS_HasNEON, // ST1Twov4s = 4162 |
| CEFBS_HasNEON, // ST1Twov4s_POST = 4163 |
| CEFBS_HasNEON, // ST1Twov8b = 4164 |
| CEFBS_HasNEON, // ST1Twov8b_POST = 4165 |
| CEFBS_HasNEON, // ST1Twov8h = 4166 |
| CEFBS_HasNEON, // ST1Twov8h_POST = 4167 |
| CEFBS_HasSVE, // ST1W = 4168 |
| CEFBS_HasSVE, // ST1W_D = 4169 |
| CEFBS_HasSVE, // ST1W_D_IMM = 4170 |
| CEFBS_HasSVE, // ST1W_IMM = 4171 |
| CEFBS_HasNEON, // ST1i16 = 4172 |
| CEFBS_HasNEON, // ST1i16_POST = 4173 |
| CEFBS_HasNEON, // ST1i32 = 4174 |
| CEFBS_HasNEON, // ST1i32_POST = 4175 |
| CEFBS_HasNEON, // ST1i64 = 4176 |
| CEFBS_HasNEON, // ST1i64_POST = 4177 |
| CEFBS_HasNEON, // ST1i8 = 4178 |
| CEFBS_HasNEON, // ST1i8_POST = 4179 |
| CEFBS_HasSVE, // ST2B = 4180 |
| CEFBS_HasSVE, // ST2B_IMM = 4181 |
| CEFBS_HasSVE, // ST2D = 4182 |
| CEFBS_HasSVE, // ST2D_IMM = 4183 |
| CEFBS_HasMTE, // ST2GOffset = 4184 |
| CEFBS_HasMTE, // ST2GPostIndex = 4185 |
| CEFBS_HasMTE, // ST2GPreIndex = 4186 |
| CEFBS_HasSVE, // ST2H = 4187 |
| CEFBS_HasSVE, // ST2H_IMM = 4188 |
| CEFBS_HasNEON, // ST2Twov16b = 4189 |
| CEFBS_HasNEON, // ST2Twov16b_POST = 4190 |
| CEFBS_HasNEON, // ST2Twov2d = 4191 |
| CEFBS_HasNEON, // ST2Twov2d_POST = 4192 |
| CEFBS_HasNEON, // ST2Twov2s = 4193 |
| CEFBS_HasNEON, // ST2Twov2s_POST = 4194 |
| CEFBS_HasNEON, // ST2Twov4h = 4195 |
| CEFBS_HasNEON, // ST2Twov4h_POST = 4196 |
| CEFBS_HasNEON, // ST2Twov4s = 4197 |
| CEFBS_HasNEON, // ST2Twov4s_POST = 4198 |
| CEFBS_HasNEON, // ST2Twov8b = 4199 |
| CEFBS_HasNEON, // ST2Twov8b_POST = 4200 |
| CEFBS_HasNEON, // ST2Twov8h = 4201 |
| CEFBS_HasNEON, // ST2Twov8h_POST = 4202 |
| CEFBS_HasSVE, // ST2W = 4203 |
| CEFBS_HasSVE, // ST2W_IMM = 4204 |
| CEFBS_HasNEON, // ST2i16 = 4205 |
| CEFBS_HasNEON, // ST2i16_POST = 4206 |
| CEFBS_HasNEON, // ST2i32 = 4207 |
| CEFBS_HasNEON, // ST2i32_POST = 4208 |
| CEFBS_HasNEON, // ST2i64 = 4209 |
| CEFBS_HasNEON, // ST2i64_POST = 4210 |
| CEFBS_HasNEON, // ST2i8 = 4211 |
| CEFBS_HasNEON, // ST2i8_POST = 4212 |
| CEFBS_HasSVE, // ST3B = 4213 |
| CEFBS_HasSVE, // ST3B_IMM = 4214 |
| CEFBS_HasSVE, // ST3D = 4215 |
| CEFBS_HasSVE, // ST3D_IMM = 4216 |
| CEFBS_HasSVE, // ST3H = 4217 |
| CEFBS_HasSVE, // ST3H_IMM = 4218 |
| CEFBS_HasNEON, // ST3Threev16b = 4219 |
| CEFBS_HasNEON, // ST3Threev16b_POST = 4220 |
| CEFBS_HasNEON, // ST3Threev2d = 4221 |
| CEFBS_HasNEON, // ST3Threev2d_POST = 4222 |
| CEFBS_HasNEON, // ST3Threev2s = 4223 |
| CEFBS_HasNEON, // ST3Threev2s_POST = 4224 |
| CEFBS_HasNEON, // ST3Threev4h = 4225 |
| CEFBS_HasNEON, // ST3Threev4h_POST = 4226 |
| CEFBS_HasNEON, // ST3Threev4s = 4227 |
| CEFBS_HasNEON, // ST3Threev4s_POST = 4228 |
| CEFBS_HasNEON, // ST3Threev8b = 4229 |
| CEFBS_HasNEON, // ST3Threev8b_POST = 4230 |
| CEFBS_HasNEON, // ST3Threev8h = 4231 |
| CEFBS_HasNEON, // ST3Threev8h_POST = 4232 |
| CEFBS_HasSVE, // ST3W = 4233 |
| CEFBS_HasSVE, // ST3W_IMM = 4234 |
| CEFBS_HasNEON, // ST3i16 = 4235 |
| CEFBS_HasNEON, // ST3i16_POST = 4236 |
| CEFBS_HasNEON, // ST3i32 = 4237 |
| CEFBS_HasNEON, // ST3i32_POST = 4238 |
| CEFBS_HasNEON, // ST3i64 = 4239 |
| CEFBS_HasNEON, // ST3i64_POST = 4240 |
| CEFBS_HasNEON, // ST3i8 = 4241 |
| CEFBS_HasNEON, // ST3i8_POST = 4242 |
| CEFBS_HasSVE, // ST4B = 4243 |
| CEFBS_HasSVE, // ST4B_IMM = 4244 |
| CEFBS_HasSVE, // ST4D = 4245 |
| CEFBS_HasSVE, // ST4D_IMM = 4246 |
| CEFBS_HasNEON, // ST4Fourv16b = 4247 |
| CEFBS_HasNEON, // ST4Fourv16b_POST = 4248 |
| CEFBS_HasNEON, // ST4Fourv2d = 4249 |
| CEFBS_HasNEON, // ST4Fourv2d_POST = 4250 |
| CEFBS_HasNEON, // ST4Fourv2s = 4251 |
| CEFBS_HasNEON, // ST4Fourv2s_POST = 4252 |
| CEFBS_HasNEON, // ST4Fourv4h = 4253 |
| CEFBS_HasNEON, // ST4Fourv4h_POST = 4254 |
| CEFBS_HasNEON, // ST4Fourv4s = 4255 |
| CEFBS_HasNEON, // ST4Fourv4s_POST = 4256 |
| CEFBS_HasNEON, // ST4Fourv8b = 4257 |
| CEFBS_HasNEON, // ST4Fourv8b_POST = 4258 |
| CEFBS_HasNEON, // ST4Fourv8h = 4259 |
| CEFBS_HasNEON, // ST4Fourv8h_POST = 4260 |
| CEFBS_HasSVE, // ST4H = 4261 |
| CEFBS_HasSVE, // ST4H_IMM = 4262 |
| CEFBS_HasSVE, // ST4W = 4263 |
| CEFBS_HasSVE, // ST4W_IMM = 4264 |
| CEFBS_HasNEON, // ST4i16 = 4265 |
| CEFBS_HasNEON, // ST4i16_POST = 4266 |
| CEFBS_HasNEON, // ST4i32 = 4267 |
| CEFBS_HasNEON, // ST4i32_POST = 4268 |
| CEFBS_HasNEON, // ST4i64 = 4269 |
| CEFBS_HasNEON, // ST4i64_POST = 4270 |
| CEFBS_HasNEON, // ST4i8 = 4271 |
| CEFBS_HasNEON, // ST4i8_POST = 4272 |
| CEFBS_HasMTE, // STGM = 4273 |
| CEFBS_HasMTE, // STGOffset = 4274 |
| CEFBS_HasMTE, // STGPi = 4275 |
| CEFBS_HasMTE, // STGPostIndex = 4276 |
| CEFBS_HasMTE, // STGPpost = 4277 |
| CEFBS_HasMTE, // STGPpre = 4278 |
| CEFBS_HasMTE, // STGPreIndex = 4279 |
| CEFBS_HasMTE, // STGloop = 4280 |
| CEFBS_HasLOR, // STLLRB = 4281 |
| CEFBS_HasLOR, // STLLRH = 4282 |
| CEFBS_HasLOR, // STLLRW = 4283 |
| CEFBS_HasLOR, // STLLRX = 4284 |
| CEFBS_None, // STLRB = 4285 |
| CEFBS_None, // STLRH = 4286 |
| CEFBS_None, // STLRW = 4287 |
| CEFBS_None, // STLRX = 4288 |
| CEFBS_HasRCPC_IMMO, // STLURBi = 4289 |
| CEFBS_HasRCPC_IMMO, // STLURHi = 4290 |
| CEFBS_HasRCPC_IMMO, // STLURWi = 4291 |
| CEFBS_HasRCPC_IMMO, // STLURXi = 4292 |
| CEFBS_None, // STLXPW = 4293 |
| CEFBS_None, // STLXPX = 4294 |
| CEFBS_None, // STLXRB = 4295 |
| CEFBS_None, // STLXRH = 4296 |
| CEFBS_None, // STLXRW = 4297 |
| CEFBS_None, // STLXRX = 4298 |
| CEFBS_None, // STNPDi = 4299 |
| CEFBS_None, // STNPQi = 4300 |
| CEFBS_None, // STNPSi = 4301 |
| CEFBS_None, // STNPWi = 4302 |
| CEFBS_None, // STNPXi = 4303 |
| CEFBS_HasSVE, // STNT1B_ZRI = 4304 |
| CEFBS_HasSVE, // STNT1B_ZRR = 4305 |
| CEFBS_HasSVE2, // STNT1B_ZZR_D_REAL = 4306 |
| CEFBS_HasSVE2, // STNT1B_ZZR_S_REAL = 4307 |
| CEFBS_HasSVE, // STNT1D_ZRI = 4308 |
| CEFBS_HasSVE, // STNT1D_ZRR = 4309 |
| CEFBS_HasSVE2, // STNT1D_ZZR_D_REAL = 4310 |
| CEFBS_HasSVE, // STNT1H_ZRI = 4311 |
| CEFBS_HasSVE, // STNT1H_ZRR = 4312 |
| CEFBS_HasSVE2, // STNT1H_ZZR_D_REAL = 4313 |
| CEFBS_HasSVE2, // STNT1H_ZZR_S_REAL = 4314 |
| CEFBS_HasSVE, // STNT1W_ZRI = 4315 |
| CEFBS_HasSVE, // STNT1W_ZRR = 4316 |
| CEFBS_HasSVE2, // STNT1W_ZZR_D_REAL = 4317 |
| CEFBS_HasSVE2, // STNT1W_ZZR_S_REAL = 4318 |
| CEFBS_None, // STPDi = 4319 |
| CEFBS_None, // STPDpost = 4320 |
| CEFBS_None, // STPDpre = 4321 |
| CEFBS_None, // STPQi = 4322 |
| CEFBS_None, // STPQpost = 4323 |
| CEFBS_None, // STPQpre = 4324 |
| CEFBS_None, // STPSi = 4325 |
| CEFBS_None, // STPSpost = 4326 |
| CEFBS_None, // STPSpre = 4327 |
| CEFBS_None, // STPWi = 4328 |
| CEFBS_None, // STPWpost = 4329 |
| CEFBS_None, // STPWpre = 4330 |
| CEFBS_None, // STPXi = 4331 |
| CEFBS_None, // STPXpost = 4332 |
| CEFBS_None, // STPXpre = 4333 |
| CEFBS_None, // STRBBpost = 4334 |
| CEFBS_None, // STRBBpre = 4335 |
| CEFBS_None, // STRBBroW = 4336 |
| CEFBS_None, // STRBBroX = 4337 |
| CEFBS_None, // STRBBui = 4338 |
| CEFBS_None, // STRBpost = 4339 |
| CEFBS_None, // STRBpre = 4340 |
| CEFBS_None, // STRBroW = 4341 |
| CEFBS_None, // STRBroX = 4342 |
| CEFBS_None, // STRBui = 4343 |
| CEFBS_None, // STRDpost = 4344 |
| CEFBS_None, // STRDpre = 4345 |
| CEFBS_None, // STRDroW = 4346 |
| CEFBS_None, // STRDroX = 4347 |
| CEFBS_None, // STRDui = 4348 |
| CEFBS_None, // STRHHpost = 4349 |
| CEFBS_None, // STRHHpre = 4350 |
| CEFBS_None, // STRHHroW = 4351 |
| CEFBS_None, // STRHHroX = 4352 |
| CEFBS_None, // STRHHui = 4353 |
| CEFBS_None, // STRHpost = 4354 |
| CEFBS_None, // STRHpre = 4355 |
| CEFBS_None, // STRHroW = 4356 |
| CEFBS_None, // STRHroX = 4357 |
| CEFBS_None, // STRHui = 4358 |
| CEFBS_None, // STRQpost = 4359 |
| CEFBS_None, // STRQpre = 4360 |
| CEFBS_None, // STRQroW = 4361 |
| CEFBS_None, // STRQroX = 4362 |
| CEFBS_None, // STRQui = 4363 |
| CEFBS_None, // STRSpost = 4364 |
| CEFBS_None, // STRSpre = 4365 |
| CEFBS_None, // STRSroW = 4366 |
| CEFBS_None, // STRSroX = 4367 |
| CEFBS_None, // STRSui = 4368 |
| CEFBS_None, // STRWpost = 4369 |
| CEFBS_None, // STRWpre = 4370 |
| CEFBS_None, // STRWroW = 4371 |
| CEFBS_None, // STRWroX = 4372 |
| CEFBS_None, // STRWui = 4373 |
| CEFBS_None, // STRXpost = 4374 |
| CEFBS_None, // STRXpre = 4375 |
| CEFBS_None, // STRXroW = 4376 |
| CEFBS_None, // STRXroX = 4377 |
| CEFBS_None, // STRXui = 4378 |
| CEFBS_HasSVE, // STR_PXI = 4379 |
| CEFBS_HasSVE, // STR_ZXI = 4380 |
| CEFBS_None, // STTRBi = 4381 |
| CEFBS_None, // STTRHi = 4382 |
| CEFBS_None, // STTRWi = 4383 |
| CEFBS_None, // STTRXi = 4384 |
| CEFBS_None, // STURBBi = 4385 |
| CEFBS_None, // STURBi = 4386 |
| CEFBS_None, // STURDi = 4387 |
| CEFBS_None, // STURHHi = 4388 |
| CEFBS_None, // STURHi = 4389 |
| CEFBS_None, // STURQi = 4390 |
| CEFBS_None, // STURSi = 4391 |
| CEFBS_None, // STURWi = 4392 |
| CEFBS_None, // STURXi = 4393 |
| CEFBS_None, // STXPW = 4394 |
| CEFBS_None, // STXPX = 4395 |
| CEFBS_None, // STXRB = 4396 |
| CEFBS_None, // STXRH = 4397 |
| CEFBS_None, // STXRW = 4398 |
| CEFBS_None, // STXRX = 4399 |
| CEFBS_HasMTE, // STZ2GOffset = 4400 |
| CEFBS_HasMTE, // STZ2GPostIndex = 4401 |
| CEFBS_HasMTE, // STZ2GPreIndex = 4402 |
| CEFBS_HasMTE, // STZGM = 4403 |
| CEFBS_HasMTE, // STZGOffset = 4404 |
| CEFBS_HasMTE, // STZGPostIndex = 4405 |
| CEFBS_HasMTE, // STZGPreIndex = 4406 |
| CEFBS_HasMTE, // STZGloop = 4407 |
| CEFBS_HasMTE, // SUBG = 4408 |
| CEFBS_HasSVE2, // SUBHNB_ZZZ_B = 4409 |
| CEFBS_HasSVE2, // SUBHNB_ZZZ_H = 4410 |
| CEFBS_HasSVE2, // SUBHNB_ZZZ_S = 4411 |
| CEFBS_HasSVE2, // SUBHNT_ZZZ_B = 4412 |
| CEFBS_HasSVE2, // SUBHNT_ZZZ_H = 4413 |
| CEFBS_HasSVE2, // SUBHNT_ZZZ_S = 4414 |
| CEFBS_HasNEON, // SUBHNv2i64_v2i32 = 4415 |
| CEFBS_HasNEON, // SUBHNv2i64_v4i32 = 4416 |
| CEFBS_HasNEON, // SUBHNv4i32_v4i16 = 4417 |
| CEFBS_HasNEON, // SUBHNv4i32_v8i16 = 4418 |
| CEFBS_HasNEON, // SUBHNv8i16_v16i8 = 4419 |
| CEFBS_HasNEON, // SUBHNv8i16_v8i8 = 4420 |
| CEFBS_HasMTE, // SUBP = 4421 |
| CEFBS_HasMTE, // SUBPS = 4422 |
| CEFBS_HasSVE, // SUBR_ZI_B = 4423 |
| CEFBS_HasSVE, // SUBR_ZI_D = 4424 |
| CEFBS_HasSVE, // SUBR_ZI_H = 4425 |
| CEFBS_HasSVE, // SUBR_ZI_S = 4426 |
| CEFBS_HasSVE, // SUBR_ZPmZ_B = 4427 |
| CEFBS_HasSVE, // SUBR_ZPmZ_D = 4428 |
| CEFBS_HasSVE, // SUBR_ZPmZ_H = 4429 |
| CEFBS_HasSVE, // SUBR_ZPmZ_S = 4430 |
| CEFBS_None, // SUBSWri = 4431 |
| CEFBS_None, // SUBSWrr = 4432 |
| CEFBS_None, // SUBSWrs = 4433 |
| CEFBS_None, // SUBSWrx = 4434 |
| CEFBS_None, // SUBSXri = 4435 |
| CEFBS_None, // SUBSXrr = 4436 |
| CEFBS_None, // SUBSXrs = 4437 |
| CEFBS_None, // SUBSXrx = 4438 |
| CEFBS_None, // SUBSXrx64 = 4439 |
| CEFBS_None, // SUBWri = 4440 |
| CEFBS_None, // SUBWrr = 4441 |
| CEFBS_None, // SUBWrs = 4442 |
| CEFBS_None, // SUBWrx = 4443 |
| CEFBS_None, // SUBXri = 4444 |
| CEFBS_None, // SUBXrr = 4445 |
| CEFBS_None, // SUBXrs = 4446 |
| CEFBS_None, // SUBXrx = 4447 |
| CEFBS_None, // SUBXrx64 = 4448 |
| CEFBS_HasSVE, // SUB_ZI_B = 4449 |
| CEFBS_HasSVE, // SUB_ZI_D = 4450 |
| CEFBS_HasSVE, // SUB_ZI_H = 4451 |
| CEFBS_HasSVE, // SUB_ZI_S = 4452 |
| CEFBS_HasSVE, // SUB_ZPmZ_B = 4453 |
| CEFBS_HasSVE, // SUB_ZPmZ_D = 4454 |
| CEFBS_HasSVE, // SUB_ZPmZ_H = 4455 |
| CEFBS_HasSVE, // SUB_ZPmZ_S = 4456 |
| CEFBS_HasSVE, // SUB_ZZZ_B = 4457 |
| CEFBS_HasSVE, // SUB_ZZZ_D = 4458 |
| CEFBS_HasSVE, // SUB_ZZZ_H = 4459 |
| CEFBS_HasSVE, // SUB_ZZZ_S = 4460 |
| CEFBS_HasNEON, // SUBv16i8 = 4461 |
| CEFBS_HasNEON, // SUBv1i64 = 4462 |
| CEFBS_HasNEON, // SUBv2i32 = 4463 |
| CEFBS_HasNEON, // SUBv2i64 = 4464 |
| CEFBS_HasNEON, // SUBv4i16 = 4465 |
| CEFBS_HasNEON, // SUBv4i32 = 4466 |
| CEFBS_HasNEON, // SUBv8i16 = 4467 |
| CEFBS_HasNEON, // SUBv8i8 = 4468 |
| CEFBS_HasSVE, // SUNPKHI_ZZ_D = 4469 |
| CEFBS_HasSVE, // SUNPKHI_ZZ_H = 4470 |
| CEFBS_HasSVE, // SUNPKHI_ZZ_S = 4471 |
| CEFBS_HasSVE, // SUNPKLO_ZZ_D = 4472 |
| CEFBS_HasSVE, // SUNPKLO_ZZ_H = 4473 |
| CEFBS_HasSVE, // SUNPKLO_ZZ_S = 4474 |
| CEFBS_HasSVE2, // SUQADD_ZPmZ_B = 4475 |
| CEFBS_HasSVE2, // SUQADD_ZPmZ_D = 4476 |
| CEFBS_HasSVE2, // SUQADD_ZPmZ_H = 4477 |
| CEFBS_HasSVE2, // SUQADD_ZPmZ_S = 4478 |
| CEFBS_HasNEON, // SUQADDv16i8 = 4479 |
| CEFBS_HasNEON, // SUQADDv1i16 = 4480 |
| CEFBS_HasNEON, // SUQADDv1i32 = 4481 |
| CEFBS_HasNEON, // SUQADDv1i64 = 4482 |
| CEFBS_HasNEON, // SUQADDv1i8 = 4483 |
| CEFBS_HasNEON, // SUQADDv2i32 = 4484 |
| CEFBS_HasNEON, // SUQADDv2i64 = 4485 |
| CEFBS_HasNEON, // SUQADDv4i16 = 4486 |
| CEFBS_HasNEON, // SUQADDv4i32 = 4487 |
| CEFBS_HasNEON, // SUQADDv8i16 = 4488 |
| CEFBS_HasNEON, // SUQADDv8i8 = 4489 |
| CEFBS_None, // SVC = 4490 |
| CEFBS_HasLSE, // SWPAB = 4491 |
| CEFBS_HasLSE, // SWPAH = 4492 |
| CEFBS_HasLSE, // SWPALB = 4493 |
| CEFBS_HasLSE, // SWPALH = 4494 |
| CEFBS_HasLSE, // SWPALW = 4495 |
| CEFBS_HasLSE, // SWPALX = 4496 |
| CEFBS_HasLSE, // SWPAW = 4497 |
| CEFBS_HasLSE, // SWPAX = 4498 |
| CEFBS_HasLSE, // SWPB = 4499 |
| CEFBS_HasLSE, // SWPH = 4500 |
| CEFBS_HasLSE, // SWPLB = 4501 |
| CEFBS_HasLSE, // SWPLH = 4502 |
| CEFBS_HasLSE, // SWPLW = 4503 |
| CEFBS_HasLSE, // SWPLX = 4504 |
| CEFBS_HasLSE, // SWPW = 4505 |
| CEFBS_HasLSE, // SWPX = 4506 |
| CEFBS_HasSVE, // SXTB_ZPmZ_D = 4507 |
| CEFBS_HasSVE, // SXTB_ZPmZ_H = 4508 |
| CEFBS_HasSVE, // SXTB_ZPmZ_S = 4509 |
| CEFBS_HasSVE, // SXTH_ZPmZ_D = 4510 |
| CEFBS_HasSVE, // SXTH_ZPmZ_S = 4511 |
| CEFBS_HasSVE, // SXTW_ZPmZ_D = 4512 |
| CEFBS_None, // SYSLxt = 4513 |
| CEFBS_None, // SYSxt = 4514 |
| CEFBS_None, // SpeculationSafeValueW = 4515 |
| CEFBS_None, // SpeculationSafeValueX = 4516 |
| CEFBS_HasMTE, // TAGPstack = 4517 |
| CEFBS_HasSVE2, // TBL_ZZZZ_B = 4518 |
| CEFBS_HasSVE2, // TBL_ZZZZ_D = 4519 |
| CEFBS_HasSVE2, // TBL_ZZZZ_H = 4520 |
| CEFBS_HasSVE2, // TBL_ZZZZ_S = 4521 |
| CEFBS_HasSVE, // TBL_ZZZ_B = 4522 |
| CEFBS_HasSVE, // TBL_ZZZ_D = 4523 |
| CEFBS_HasSVE, // TBL_ZZZ_H = 4524 |
| CEFBS_HasSVE, // TBL_ZZZ_S = 4525 |
| CEFBS_HasNEON, // TBLv16i8Four = 4526 |
| CEFBS_HasNEON, // TBLv16i8One = 4527 |
| CEFBS_HasNEON, // TBLv16i8Three = 4528 |
| CEFBS_HasNEON, // TBLv16i8Two = 4529 |
| CEFBS_HasNEON, // TBLv8i8Four = 4530 |
| CEFBS_HasNEON, // TBLv8i8One = 4531 |
| CEFBS_HasNEON, // TBLv8i8Three = 4532 |
| CEFBS_HasNEON, // TBLv8i8Two = 4533 |
| CEFBS_None, // TBNZW = 4534 |
| CEFBS_None, // TBNZX = 4535 |
| CEFBS_HasSVE2, // TBX_ZZZ_B = 4536 |
| CEFBS_HasSVE2, // TBX_ZZZ_D = 4537 |
| CEFBS_HasSVE2, // TBX_ZZZ_H = 4538 |
| CEFBS_HasSVE2, // TBX_ZZZ_S = 4539 |
| CEFBS_HasNEON, // TBXv16i8Four = 4540 |
| CEFBS_HasNEON, // TBXv16i8One = 4541 |
| CEFBS_HasNEON, // TBXv16i8Three = 4542 |
| CEFBS_HasNEON, // TBXv16i8Two = 4543 |
| CEFBS_HasNEON, // TBXv8i8Four = 4544 |
| CEFBS_HasNEON, // TBXv8i8One = 4545 |
| CEFBS_HasNEON, // TBXv8i8Three = 4546 |
| CEFBS_HasNEON, // TBXv8i8Two = 4547 |
| CEFBS_None, // TBZW = 4548 |
| CEFBS_None, // TBZX = 4549 |
| CEFBS_HasTME, // TCANCEL = 4550 |
| CEFBS_HasTME, // TCOMMIT = 4551 |
| CEFBS_None, // TCRETURNdi = 4552 |
| CEFBS_None, // TCRETURNri = 4553 |
| CEFBS_None, // TCRETURNriALL = 4554 |
| CEFBS_None, // TCRETURNriBTI = 4555 |
| CEFBS_None, // TLSDESCCALL = 4556 |
| CEFBS_None, // TLSDESC_CALLSEQ = 4557 |
| CEFBS_HasSVE, // TRN1_PPP_B = 4558 |
| CEFBS_HasSVE, // TRN1_PPP_D = 4559 |
| CEFBS_HasSVE, // TRN1_PPP_H = 4560 |
| CEFBS_HasSVE, // TRN1_PPP_S = 4561 |
| CEFBS_HasSVE, // TRN1_ZZZ_B = 4562 |
| CEFBS_HasSVE, // TRN1_ZZZ_D = 4563 |
| CEFBS_HasSVE, // TRN1_ZZZ_H = 4564 |
| CEFBS_HasSVE, // TRN1_ZZZ_S = 4565 |
| CEFBS_HasNEON, // TRN1v16i8 = 4566 |
| CEFBS_HasNEON, // TRN1v2i32 = 4567 |
| CEFBS_HasNEON, // TRN1v2i64 = 4568 |
| CEFBS_HasNEON, // TRN1v4i16 = 4569 |
| CEFBS_HasNEON, // TRN1v4i32 = 4570 |
| CEFBS_HasNEON, // TRN1v8i16 = 4571 |
| CEFBS_HasNEON, // TRN1v8i8 = 4572 |
| CEFBS_HasSVE, // TRN2_PPP_B = 4573 |
| CEFBS_HasSVE, // TRN2_PPP_D = 4574 |
| CEFBS_HasSVE, // TRN2_PPP_H = 4575 |
| CEFBS_HasSVE, // TRN2_PPP_S = 4576 |
| CEFBS_HasSVE, // TRN2_ZZZ_B = 4577 |
| CEFBS_HasSVE, // TRN2_ZZZ_D = 4578 |
| CEFBS_HasSVE, // TRN2_ZZZ_H = 4579 |
| CEFBS_HasSVE, // TRN2_ZZZ_S = 4580 |
| CEFBS_HasNEON, // TRN2v16i8 = 4581 |
| CEFBS_HasNEON, // TRN2v2i32 = 4582 |
| CEFBS_HasNEON, // TRN2v2i64 = 4583 |
| CEFBS_HasNEON, // TRN2v4i16 = 4584 |
| CEFBS_HasNEON, // TRN2v4i32 = 4585 |
| CEFBS_HasNEON, // TRN2v8i16 = 4586 |
| CEFBS_HasNEON, // TRN2v8i8 = 4587 |
| CEFBS_HasTRACEV8_4, // TSB = 4588 |
| CEFBS_HasTME, // TSTART = 4589 |
| CEFBS_HasTME, // TTEST = 4590 |
| CEFBS_HasSVE2, // UABALB_ZZZ_D = 4591 |
| CEFBS_HasSVE2, // UABALB_ZZZ_H = 4592 |
| CEFBS_HasSVE2, // UABALB_ZZZ_S = 4593 |
| CEFBS_HasSVE2, // UABALT_ZZZ_D = 4594 |
| CEFBS_HasSVE2, // UABALT_ZZZ_H = 4595 |
| CEFBS_HasSVE2, // UABALT_ZZZ_S = 4596 |
| CEFBS_HasNEON, // UABALv16i8_v8i16 = 4597 |
| CEFBS_HasNEON, // UABALv2i32_v2i64 = 4598 |
| CEFBS_HasNEON, // UABALv4i16_v4i32 = 4599 |
| CEFBS_HasNEON, // UABALv4i32_v2i64 = 4600 |
| CEFBS_HasNEON, // UABALv8i16_v4i32 = 4601 |
| CEFBS_HasNEON, // UABALv8i8_v8i16 = 4602 |
| CEFBS_HasSVE2, // UABA_ZZZ_B = 4603 |
| CEFBS_HasSVE2, // UABA_ZZZ_D = 4604 |
| CEFBS_HasSVE2, // UABA_ZZZ_H = 4605 |
| CEFBS_HasSVE2, // UABA_ZZZ_S = 4606 |
| CEFBS_HasNEON, // UABAv16i8 = 4607 |
| CEFBS_HasNEON, // UABAv2i32 = 4608 |
| CEFBS_HasNEON, // UABAv4i16 = 4609 |
| CEFBS_HasNEON, // UABAv4i32 = 4610 |
| CEFBS_HasNEON, // UABAv8i16 = 4611 |
| CEFBS_HasNEON, // UABAv8i8 = 4612 |
| CEFBS_HasSVE2, // UABDLB_ZZZ_D = 4613 |
| CEFBS_HasSVE2, // UABDLB_ZZZ_H = 4614 |
| CEFBS_HasSVE2, // UABDLB_ZZZ_S = 4615 |
| CEFBS_HasSVE2, // UABDLT_ZZZ_D = 4616 |
| CEFBS_HasSVE2, // UABDLT_ZZZ_H = 4617 |
| CEFBS_HasSVE2, // UABDLT_ZZZ_S = 4618 |
| CEFBS_HasNEON, // UABDLv16i8_v8i16 = 4619 |
| CEFBS_HasNEON, // UABDLv2i32_v2i64 = 4620 |
| CEFBS_HasNEON, // UABDLv4i16_v4i32 = 4621 |
| CEFBS_HasNEON, // UABDLv4i32_v2i64 = 4622 |
| CEFBS_HasNEON, // UABDLv8i16_v4i32 = 4623 |
| CEFBS_HasNEON, // UABDLv8i8_v8i16 = 4624 |
| CEFBS_HasSVE, // UABD_ZPmZ_B = 4625 |
| CEFBS_HasSVE, // UABD_ZPmZ_D = 4626 |
| CEFBS_HasSVE, // UABD_ZPmZ_H = 4627 |
| CEFBS_HasSVE, // UABD_ZPmZ_S = 4628 |
| CEFBS_HasNEON, // UABDv16i8 = 4629 |
| CEFBS_HasNEON, // UABDv2i32 = 4630 |
| CEFBS_HasNEON, // UABDv4i16 = 4631 |
| CEFBS_HasNEON, // UABDv4i32 = 4632 |
| CEFBS_HasNEON, // UABDv8i16 = 4633 |
| CEFBS_HasNEON, // UABDv8i8 = 4634 |
| CEFBS_HasSVE2, // UADALP_ZPmZ_D = 4635 |
| CEFBS_HasSVE2, // UADALP_ZPmZ_H = 4636 |
| CEFBS_HasSVE2, // UADALP_ZPmZ_S = 4637 |
| CEFBS_HasNEON, // UADALPv16i8_v8i16 = 4638 |
| CEFBS_HasNEON, // UADALPv2i32_v1i64 = 4639 |
| CEFBS_HasNEON, // UADALPv4i16_v2i32 = 4640 |
| CEFBS_HasNEON, // UADALPv4i32_v2i64 = 4641 |
| CEFBS_HasNEON, // UADALPv8i16_v4i32 = 4642 |
| CEFBS_HasNEON, // UADALPv8i8_v4i16 = 4643 |
| CEFBS_HasSVE2, // UADDLB_ZZZ_D = 4644 |
| CEFBS_HasSVE2, // UADDLB_ZZZ_H = 4645 |
| CEFBS_HasSVE2, // UADDLB_ZZZ_S = 4646 |
| CEFBS_HasNEON, // UADDLPv16i8_v8i16 = 4647 |
| CEFBS_HasNEON, // UADDLPv2i32_v1i64 = 4648 |
| CEFBS_HasNEON, // UADDLPv4i16_v2i32 = 4649 |
| CEFBS_HasNEON, // UADDLPv4i32_v2i64 = 4650 |
| CEFBS_HasNEON, // UADDLPv8i16_v4i32 = 4651 |
| CEFBS_HasNEON, // UADDLPv8i8_v4i16 = 4652 |
| CEFBS_HasSVE2, // UADDLT_ZZZ_D = 4653 |
| CEFBS_HasSVE2, // UADDLT_ZZZ_H = 4654 |
| CEFBS_HasSVE2, // UADDLT_ZZZ_S = 4655 |
| CEFBS_HasNEON, // UADDLVv16i8v = 4656 |
| CEFBS_HasNEON, // UADDLVv4i16v = 4657 |
| CEFBS_HasNEON, // UADDLVv4i32v = 4658 |
| CEFBS_HasNEON, // UADDLVv8i16v = 4659 |
| CEFBS_HasNEON, // UADDLVv8i8v = 4660 |
| CEFBS_HasNEON, // UADDLv16i8_v8i16 = 4661 |
| CEFBS_HasNEON, // UADDLv2i32_v2i64 = 4662 |
| CEFBS_HasNEON, // UADDLv4i16_v4i32 = 4663 |
| CEFBS_HasNEON, // UADDLv4i32_v2i64 = 4664 |
| CEFBS_HasNEON, // UADDLv8i16_v4i32 = 4665 |
| CEFBS_HasNEON, // UADDLv8i8_v8i16 = 4666 |
| CEFBS_HasSVE, // UADDV_VPZ_B = 4667 |
| CEFBS_HasSVE, // UADDV_VPZ_D = 4668 |
| CEFBS_HasSVE, // UADDV_VPZ_H = 4669 |
| CEFBS_HasSVE, // UADDV_VPZ_S = 4670 |
| CEFBS_HasSVE2, // UADDWB_ZZZ_D = 4671 |
| CEFBS_HasSVE2, // UADDWB_ZZZ_H = 4672 |
| CEFBS_HasSVE2, // UADDWB_ZZZ_S = 4673 |
| CEFBS_HasSVE2, // UADDWT_ZZZ_D = 4674 |
| CEFBS_HasSVE2, // UADDWT_ZZZ_H = 4675 |
| CEFBS_HasSVE2, // UADDWT_ZZZ_S = 4676 |
| CEFBS_HasNEON, // UADDWv16i8_v8i16 = 4677 |
| CEFBS_HasNEON, // UADDWv2i32_v2i64 = 4678 |
| CEFBS_HasNEON, // UADDWv4i16_v4i32 = 4679 |
| CEFBS_HasNEON, // UADDWv4i32_v2i64 = 4680 |
| CEFBS_HasNEON, // UADDWv8i16_v4i32 = 4681 |
| CEFBS_HasNEON, // UADDWv8i8_v8i16 = 4682 |
| CEFBS_None, // UBFMWri = 4683 |
| CEFBS_None, // UBFMXri = 4684 |
| CEFBS_HasFPARMv8, // UCVTFSWDri = 4685 |
| CEFBS_HasFullFP16, // UCVTFSWHri = 4686 |
| CEFBS_HasFPARMv8, // UCVTFSWSri = 4687 |
| CEFBS_HasFPARMv8, // UCVTFSXDri = 4688 |
| CEFBS_HasFullFP16, // UCVTFSXHri = 4689 |
| CEFBS_HasFPARMv8, // UCVTFSXSri = 4690 |
| CEFBS_HasFPARMv8, // UCVTFUWDri = 4691 |
| CEFBS_HasFullFP16, // UCVTFUWHri = 4692 |
| CEFBS_HasFPARMv8, // UCVTFUWSri = 4693 |
| CEFBS_HasFPARMv8, // UCVTFUXDri = 4694 |
| CEFBS_HasFullFP16, // UCVTFUXHri = 4695 |
| CEFBS_HasFPARMv8, // UCVTFUXSri = 4696 |
| CEFBS_HasSVE, // UCVTF_ZPmZ_DtoD = 4697 |
| CEFBS_HasSVE, // UCVTF_ZPmZ_DtoH = 4698 |
| CEFBS_HasSVE, // UCVTF_ZPmZ_DtoS = 4699 |
| CEFBS_HasSVE, // UCVTF_ZPmZ_HtoH = 4700 |
| CEFBS_HasSVE, // UCVTF_ZPmZ_StoD = 4701 |
| CEFBS_HasSVE, // UCVTF_ZPmZ_StoH = 4702 |
| CEFBS_HasSVE, // UCVTF_ZPmZ_StoS = 4703 |
| CEFBS_HasNEON, // UCVTFd = 4704 |
| CEFBS_HasNEON_HasFullFP16, // UCVTFh = 4705 |
| CEFBS_HasNEON, // UCVTFs = 4706 |
| CEFBS_HasNEON_HasFullFP16, // UCVTFv1i16 = 4707 |
| CEFBS_HasNEON, // UCVTFv1i32 = 4708 |
| CEFBS_HasNEON, // UCVTFv1i64 = 4709 |
| CEFBS_HasNEON, // UCVTFv2f32 = 4710 |
| CEFBS_HasNEON, // UCVTFv2f64 = 4711 |
| CEFBS_HasNEON, // UCVTFv2i32_shift = 4712 |
| CEFBS_HasNEON, // UCVTFv2i64_shift = 4713 |
| CEFBS_HasNEON_HasFullFP16, // UCVTFv4f16 = 4714 |
| CEFBS_HasNEON, // UCVTFv4f32 = 4715 |
| CEFBS_HasNEON_HasFullFP16, // UCVTFv4i16_shift = 4716 |
| CEFBS_HasNEON, // UCVTFv4i32_shift = 4717 |
| CEFBS_HasNEON_HasFullFP16, // UCVTFv8f16 = 4718 |
| CEFBS_HasNEON_HasFullFP16, // UCVTFv8i16_shift = 4719 |
| CEFBS_None, // UDF = 4720 |
| CEFBS_HasSVE, // UDIVR_ZPmZ_D = 4721 |
| CEFBS_HasSVE, // UDIVR_ZPmZ_S = 4722 |
| CEFBS_None, // UDIVWr = 4723 |
| CEFBS_None, // UDIVXr = 4724 |
| CEFBS_HasSVE, // UDIV_ZPmZ_D = 4725 |
| CEFBS_HasSVE, // UDIV_ZPmZ_S = 4726 |
| CEFBS_HasSVE, // UDOT_ZZZI_D = 4727 |
| CEFBS_HasSVE, // UDOT_ZZZI_S = 4728 |
| CEFBS_HasSVE, // UDOT_ZZZ_D = 4729 |
| CEFBS_HasSVE, // UDOT_ZZZ_S = 4730 |
| CEFBS_HasDotProd, // UDOTlanev16i8 = 4731 |
| CEFBS_HasDotProd, // UDOTlanev8i8 = 4732 |
| CEFBS_HasDotProd, // UDOTv16i8 = 4733 |
| CEFBS_HasDotProd, // UDOTv8i8 = 4734 |
| CEFBS_HasSVE2, // UHADD_ZPmZ_B = 4735 |
| CEFBS_HasSVE2, // UHADD_ZPmZ_D = 4736 |
| CEFBS_HasSVE2, // UHADD_ZPmZ_H = 4737 |
| CEFBS_HasSVE2, // UHADD_ZPmZ_S = 4738 |
| CEFBS_HasNEON, // UHADDv16i8 = 4739 |
| CEFBS_HasNEON, // UHADDv2i32 = 4740 |
| CEFBS_HasNEON, // UHADDv4i16 = 4741 |
| CEFBS_HasNEON, // UHADDv4i32 = 4742 |
| CEFBS_HasNEON, // UHADDv8i16 = 4743 |
| CEFBS_HasNEON, // UHADDv8i8 = 4744 |
| CEFBS_HasSVE2, // UHSUBR_ZPmZ_B = 4745 |
| CEFBS_HasSVE2, // UHSUBR_ZPmZ_D = 4746 |
| CEFBS_HasSVE2, // UHSUBR_ZPmZ_H = 4747 |
| CEFBS_HasSVE2, // UHSUBR_ZPmZ_S = 4748 |
| CEFBS_HasSVE2, // UHSUB_ZPmZ_B = 4749 |
| CEFBS_HasSVE2, // UHSUB_ZPmZ_D = 4750 |
| CEFBS_HasSVE2, // UHSUB_ZPmZ_H = 4751 |
| CEFBS_HasSVE2, // UHSUB_ZPmZ_S = 4752 |
| CEFBS_HasNEON, // UHSUBv16i8 = 4753 |
| CEFBS_HasNEON, // UHSUBv2i32 = 4754 |
| CEFBS_HasNEON, // UHSUBv4i16 = 4755 |
| CEFBS_HasNEON, // UHSUBv4i32 = 4756 |
| CEFBS_HasNEON, // UHSUBv8i16 = 4757 |
| CEFBS_HasNEON, // UHSUBv8i8 = 4758 |
| CEFBS_None, // UMADDLrrr = 4759 |
| CEFBS_HasSVE2, // UMAXP_ZPmZ_B = 4760 |
| CEFBS_HasSVE2, // UMAXP_ZPmZ_D = 4761 |
| CEFBS_HasSVE2, // UMAXP_ZPmZ_H = 4762 |
| CEFBS_HasSVE2, // UMAXP_ZPmZ_S = 4763 |
| CEFBS_HasNEON, // UMAXPv16i8 = 4764 |
| CEFBS_HasNEON, // UMAXPv2i32 = 4765 |
| CEFBS_HasNEON, // UMAXPv4i16 = 4766 |
| CEFBS_HasNEON, // UMAXPv4i32 = 4767 |
| CEFBS_HasNEON, // UMAXPv8i16 = 4768 |
| CEFBS_HasNEON, // UMAXPv8i8 = 4769 |
| CEFBS_HasSVE, // UMAXV_VPZ_B = 4770 |
| CEFBS_HasSVE, // UMAXV_VPZ_D = 4771 |
| CEFBS_HasSVE, // UMAXV_VPZ_H = 4772 |
| CEFBS_HasSVE, // UMAXV_VPZ_S = 4773 |
| CEFBS_HasNEON, // UMAXVv16i8v = 4774 |
| CEFBS_HasNEON, // UMAXVv4i16v = 4775 |
| CEFBS_HasNEON, // UMAXVv4i32v = 4776 |
| CEFBS_HasNEON, // UMAXVv8i16v = 4777 |
| CEFBS_HasNEON, // UMAXVv8i8v = 4778 |
| CEFBS_HasSVE, // UMAX_ZI_B = 4779 |
| CEFBS_HasSVE, // UMAX_ZI_D = 4780 |
| CEFBS_HasSVE, // UMAX_ZI_H = 4781 |
| CEFBS_HasSVE, // UMAX_ZI_S = 4782 |
| CEFBS_HasSVE, // UMAX_ZPmZ_B = 4783 |
| CEFBS_HasSVE, // UMAX_ZPmZ_D = 4784 |
| CEFBS_HasSVE, // UMAX_ZPmZ_H = 4785 |
| CEFBS_HasSVE, // UMAX_ZPmZ_S = 4786 |
| CEFBS_HasNEON, // UMAXv16i8 = 4787 |
| CEFBS_HasNEON, // UMAXv2i32 = 4788 |
| CEFBS_HasNEON, // UMAXv4i16 = 4789 |
| CEFBS_HasNEON, // UMAXv4i32 = 4790 |
| CEFBS_HasNEON, // UMAXv8i16 = 4791 |
| CEFBS_HasNEON, // UMAXv8i8 = 4792 |
| CEFBS_HasSVE2, // UMINP_ZPmZ_B = 4793 |
| CEFBS_HasSVE2, // UMINP_ZPmZ_D = 4794 |
| CEFBS_HasSVE2, // UMINP_ZPmZ_H = 4795 |
| CEFBS_HasSVE2, // UMINP_ZPmZ_S = 4796 |
| CEFBS_HasNEON, // UMINPv16i8 = 4797 |
| CEFBS_HasNEON, // UMINPv2i32 = 4798 |
| CEFBS_HasNEON, // UMINPv4i16 = 4799 |
| CEFBS_HasNEON, // UMINPv4i32 = 4800 |
| CEFBS_HasNEON, // UMINPv8i16 = 4801 |
| CEFBS_HasNEON, // UMINPv8i8 = 4802 |
| CEFBS_HasSVE, // UMINV_VPZ_B = 4803 |
| CEFBS_HasSVE, // UMINV_VPZ_D = 4804 |
| CEFBS_HasSVE, // UMINV_VPZ_H = 4805 |
| CEFBS_HasSVE, // UMINV_VPZ_S = 4806 |
| CEFBS_HasNEON, // UMINVv16i8v = 4807 |
| CEFBS_HasNEON, // UMINVv4i16v = 4808 |
| CEFBS_HasNEON, // UMINVv4i32v = 4809 |
| CEFBS_HasNEON, // UMINVv8i16v = 4810 |
| CEFBS_HasNEON, // UMINVv8i8v = 4811 |
| CEFBS_HasSVE, // UMIN_ZI_B = 4812 |
| CEFBS_HasSVE, // UMIN_ZI_D = 4813 |
| CEFBS_HasSVE, // UMIN_ZI_H = 4814 |
| CEFBS_HasSVE, // UMIN_ZI_S = 4815 |
| CEFBS_HasSVE, // UMIN_ZPmZ_B = 4816 |
| CEFBS_HasSVE, // UMIN_ZPmZ_D = 4817 |
| CEFBS_HasSVE, // UMIN_ZPmZ_H = 4818 |
| CEFBS_HasSVE, // UMIN_ZPmZ_S = 4819 |
| CEFBS_HasNEON, // UMINv16i8 = 4820 |
| CEFBS_HasNEON, // UMINv2i32 = 4821 |
| CEFBS_HasNEON, // UMINv4i16 = 4822 |
| CEFBS_HasNEON, // UMINv4i32 = 4823 |
| CEFBS_HasNEON, // UMINv8i16 = 4824 |
| CEFBS_HasNEON, // UMINv8i8 = 4825 |
| CEFBS_HasSVE2, // UMLALB_ZZZI_D = 4826 |
| CEFBS_HasSVE2, // UMLALB_ZZZI_S = 4827 |
| CEFBS_HasSVE2, // UMLALB_ZZZ_D = 4828 |
| CEFBS_HasSVE2, // UMLALB_ZZZ_H = 4829 |
| CEFBS_HasSVE2, // UMLALB_ZZZ_S = 4830 |
| CEFBS_HasSVE2, // UMLALT_ZZZI_D = 4831 |
| CEFBS_HasSVE2, // UMLALT_ZZZI_S = 4832 |
| CEFBS_HasSVE2, // UMLALT_ZZZ_D = 4833 |
| CEFBS_HasSVE2, // UMLALT_ZZZ_H = 4834 |
| CEFBS_HasSVE2, // UMLALT_ZZZ_S = 4835 |
| CEFBS_HasNEON, // UMLALv16i8_v8i16 = 4836 |
| CEFBS_HasNEON, // UMLALv2i32_indexed = 4837 |
| CEFBS_HasNEON, // UMLALv2i32_v2i64 = 4838 |
| CEFBS_HasNEON, // UMLALv4i16_indexed = 4839 |
| CEFBS_HasNEON, // UMLALv4i16_v4i32 = 4840 |
| CEFBS_HasNEON, // UMLALv4i32_indexed = 4841 |
| CEFBS_HasNEON, // UMLALv4i32_v2i64 = 4842 |
| CEFBS_HasNEON, // UMLALv8i16_indexed = 4843 |
| CEFBS_HasNEON, // UMLALv8i16_v4i32 = 4844 |
| CEFBS_HasNEON, // UMLALv8i8_v8i16 = 4845 |
| CEFBS_HasSVE2, // UMLSLB_ZZZI_D = 4846 |
| CEFBS_HasSVE2, // UMLSLB_ZZZI_S = 4847 |
| CEFBS_HasSVE2, // UMLSLB_ZZZ_D = 4848 |
| CEFBS_HasSVE2, // UMLSLB_ZZZ_H = 4849 |
| CEFBS_HasSVE2, // UMLSLB_ZZZ_S = 4850 |
| CEFBS_HasSVE2, // UMLSLT_ZZZI_D = 4851 |
| CEFBS_HasSVE2, // UMLSLT_ZZZI_S = 4852 |
| CEFBS_HasSVE2, // UMLSLT_ZZZ_D = 4853 |
| CEFBS_HasSVE2, // UMLSLT_ZZZ_H = 4854 |
| CEFBS_HasSVE2, // UMLSLT_ZZZ_S = 4855 |
| CEFBS_HasNEON, // UMLSLv16i8_v8i16 = 4856 |
| CEFBS_HasNEON, // UMLSLv2i32_indexed = 4857 |
| CEFBS_HasNEON, // UMLSLv2i32_v2i64 = 4858 |
| CEFBS_HasNEON, // UMLSLv4i16_indexed = 4859 |
| CEFBS_HasNEON, // UMLSLv4i16_v4i32 = 4860 |
| CEFBS_HasNEON, // UMLSLv4i32_indexed = 4861 |
| CEFBS_HasNEON, // UMLSLv4i32_v2i64 = 4862 |
| CEFBS_HasNEON, // UMLSLv8i16_indexed = 4863 |
| CEFBS_HasNEON, // UMLSLv8i16_v4i32 = 4864 |
| CEFBS_HasNEON, // UMLSLv8i8_v8i16 = 4865 |
| CEFBS_HasNEON, // UMOVvi16 = 4866 |
| CEFBS_HasNEON, // UMOVvi32 = 4867 |
| CEFBS_HasNEON, // UMOVvi64 = 4868 |
| CEFBS_HasNEON, // UMOVvi8 = 4869 |
| CEFBS_None, // UMSUBLrrr = 4870 |
| CEFBS_HasSVE, // UMULH_ZPmZ_B = 4871 |
| CEFBS_HasSVE, // UMULH_ZPmZ_D = 4872 |
| CEFBS_HasSVE, // UMULH_ZPmZ_H = 4873 |
| CEFBS_HasSVE, // UMULH_ZPmZ_S = 4874 |
| CEFBS_HasSVE2, // UMULH_ZZZ_B = 4875 |
| CEFBS_HasSVE2, // UMULH_ZZZ_D = 4876 |
| CEFBS_HasSVE2, // UMULH_ZZZ_H = 4877 |
| CEFBS_HasSVE2, // UMULH_ZZZ_S = 4878 |
| CEFBS_None, // UMULHrr = 4879 |
| CEFBS_HasSVE2, // UMULLB_ZZZI_D = 4880 |
| CEFBS_HasSVE2, // UMULLB_ZZZI_S = 4881 |
| CEFBS_HasSVE2, // UMULLB_ZZZ_D = 4882 |
| CEFBS_HasSVE2, // UMULLB_ZZZ_H = 4883 |
| CEFBS_HasSVE2, // UMULLB_ZZZ_S = 4884 |
| CEFBS_HasSVE2, // UMULLT_ZZZI_D = 4885 |
| CEFBS_HasSVE2, // UMULLT_ZZZI_S = 4886 |
| CEFBS_HasSVE2, // UMULLT_ZZZ_D = 4887 |
| CEFBS_HasSVE2, // UMULLT_ZZZ_H = 4888 |
| CEFBS_HasSVE2, // UMULLT_ZZZ_S = 4889 |
| CEFBS_HasNEON, // UMULLv16i8_v8i16 = 4890 |
| CEFBS_HasNEON, // UMULLv2i32_indexed = 4891 |
| CEFBS_HasNEON, // UMULLv2i32_v2i64 = 4892 |
| CEFBS_HasNEON, // UMULLv4i16_indexed = 4893 |
| CEFBS_HasNEON, // UMULLv4i16_v4i32 = 4894 |
| CEFBS_HasNEON, // UMULLv4i32_indexed = 4895 |
| CEFBS_HasNEON, // UMULLv4i32_v2i64 = 4896 |
| CEFBS_HasNEON, // UMULLv8i16_indexed = 4897 |
| CEFBS_HasNEON, // UMULLv8i16_v4i32 = 4898 |
| CEFBS_HasNEON, // UMULLv8i8_v8i16 = 4899 |
| CEFBS_HasSVE, // UQADD_ZI_B = 4900 |
| CEFBS_HasSVE, // UQADD_ZI_D = 4901 |
| CEFBS_HasSVE, // UQADD_ZI_H = 4902 |
| CEFBS_HasSVE, // UQADD_ZI_S = 4903 |
| CEFBS_HasSVE2, // UQADD_ZPmZ_B = 4904 |
| CEFBS_HasSVE2, // UQADD_ZPmZ_D = 4905 |
| CEFBS_HasSVE2, // UQADD_ZPmZ_H = 4906 |
| CEFBS_HasSVE2, // UQADD_ZPmZ_S = 4907 |
| CEFBS_HasSVE, // UQADD_ZZZ_B = 4908 |
| CEFBS_HasSVE, // UQADD_ZZZ_D = 4909 |
| CEFBS_HasSVE, // UQADD_ZZZ_H = 4910 |
| CEFBS_HasSVE, // UQADD_ZZZ_S = 4911 |
| CEFBS_HasNEON, // UQADDv16i8 = 4912 |
| CEFBS_HasNEON, // UQADDv1i16 = 4913 |
| CEFBS_HasNEON, // UQADDv1i32 = 4914 |
| CEFBS_HasNEON, // UQADDv1i64 = 4915 |
| CEFBS_HasNEON, // UQADDv1i8 = 4916 |
| CEFBS_HasNEON, // UQADDv2i32 = 4917 |
| CEFBS_HasNEON, // UQADDv2i64 = 4918 |
| CEFBS_HasNEON, // UQADDv4i16 = 4919 |
| CEFBS_HasNEON, // UQADDv4i32 = 4920 |
| CEFBS_HasNEON, // UQADDv8i16 = 4921 |
| CEFBS_HasNEON, // UQADDv8i8 = 4922 |
| CEFBS_HasSVE, // UQDECB_WPiI = 4923 |
| CEFBS_HasSVE, // UQDECB_XPiI = 4924 |
| CEFBS_HasSVE, // UQDECD_WPiI = 4925 |
| CEFBS_HasSVE, // UQDECD_XPiI = 4926 |
| CEFBS_HasSVE, // UQDECD_ZPiI = 4927 |
| CEFBS_HasSVE, // UQDECH_WPiI = 4928 |
| CEFBS_HasSVE, // UQDECH_XPiI = 4929 |
| CEFBS_HasSVE, // UQDECH_ZPiI = 4930 |
| CEFBS_HasSVE, // UQDECP_WP_B = 4931 |
| CEFBS_HasSVE, // UQDECP_WP_D = 4932 |
| CEFBS_HasSVE, // UQDECP_WP_H = 4933 |
| CEFBS_HasSVE, // UQDECP_WP_S = 4934 |
| CEFBS_HasSVE, // UQDECP_XP_B = 4935 |
| CEFBS_HasSVE, // UQDECP_XP_D = 4936 |
| CEFBS_HasSVE, // UQDECP_XP_H = 4937 |
| CEFBS_HasSVE, // UQDECP_XP_S = 4938 |
| CEFBS_HasSVE, // UQDECP_ZP_D = 4939 |
| CEFBS_HasSVE, // UQDECP_ZP_H = 4940 |
| CEFBS_HasSVE, // UQDECP_ZP_S = 4941 |
| CEFBS_HasSVE, // UQDECW_WPiI = 4942 |
| CEFBS_HasSVE, // UQDECW_XPiI = 4943 |
| CEFBS_HasSVE, // UQDECW_ZPiI = 4944 |
| CEFBS_HasSVE, // UQINCB_WPiI = 4945 |
| CEFBS_HasSVE, // UQINCB_XPiI = 4946 |
| CEFBS_HasSVE, // UQINCD_WPiI = 4947 |
| CEFBS_HasSVE, // UQINCD_XPiI = 4948 |
| CEFBS_HasSVE, // UQINCD_ZPiI = 4949 |
| CEFBS_HasSVE, // UQINCH_WPiI = 4950 |
| CEFBS_HasSVE, // UQINCH_XPiI = 4951 |
| CEFBS_HasSVE, // UQINCH_ZPiI = 4952 |
| CEFBS_HasSVE, // UQINCP_WP_B = 4953 |
| CEFBS_HasSVE, // UQINCP_WP_D = 4954 |
| CEFBS_HasSVE, // UQINCP_WP_H = 4955 |
| CEFBS_HasSVE, // UQINCP_WP_S = 4956 |
| CEFBS_HasSVE, // UQINCP_XP_B = 4957 |
| CEFBS_HasSVE, // UQINCP_XP_D = 4958 |
| CEFBS_HasSVE, // UQINCP_XP_H = 4959 |
| CEFBS_HasSVE, // UQINCP_XP_S = 4960 |
| CEFBS_HasSVE, // UQINCP_ZP_D = 4961 |
| CEFBS_HasSVE, // UQINCP_ZP_H = 4962 |
| CEFBS_HasSVE, // UQINCP_ZP_S = 4963 |
| CEFBS_HasSVE, // UQINCW_WPiI = 4964 |
| CEFBS_HasSVE, // UQINCW_XPiI = 4965 |
| CEFBS_HasSVE, // UQINCW_ZPiI = 4966 |
| CEFBS_HasSVE2, // UQRSHLR_ZPmZ_B = 4967 |
| CEFBS_HasSVE2, // UQRSHLR_ZPmZ_D = 4968 |
| CEFBS_HasSVE2, // UQRSHLR_ZPmZ_H = 4969 |
| CEFBS_HasSVE2, // UQRSHLR_ZPmZ_S = 4970 |
| CEFBS_HasSVE2, // UQRSHL_ZPmZ_B = 4971 |
| CEFBS_HasSVE2, // UQRSHL_ZPmZ_D = 4972 |
| CEFBS_HasSVE2, // UQRSHL_ZPmZ_H = 4973 |
| CEFBS_HasSVE2, // UQRSHL_ZPmZ_S = 4974 |
| CEFBS_HasNEON, // UQRSHLv16i8 = 4975 |
| CEFBS_HasNEON, // UQRSHLv1i16 = 4976 |
| CEFBS_HasNEON, // UQRSHLv1i32 = 4977 |
| CEFBS_HasNEON, // UQRSHLv1i64 = 4978 |
| CEFBS_HasNEON, // UQRSHLv1i8 = 4979 |
| CEFBS_HasNEON, // UQRSHLv2i32 = 4980 |
| CEFBS_HasNEON, // UQRSHLv2i64 = 4981 |
| CEFBS_HasNEON, // UQRSHLv4i16 = 4982 |
| CEFBS_HasNEON, // UQRSHLv4i32 = 4983 |
| CEFBS_HasNEON, // UQRSHLv8i16 = 4984 |
| CEFBS_HasNEON, // UQRSHLv8i8 = 4985 |
| CEFBS_HasSVE2, // UQRSHRNB_ZZI_B = 4986 |
| CEFBS_HasSVE2, // UQRSHRNB_ZZI_H = 4987 |
| CEFBS_HasSVE2, // UQRSHRNB_ZZI_S = 4988 |
| CEFBS_HasSVE2, // UQRSHRNT_ZZI_B = 4989 |
| CEFBS_HasSVE2, // UQRSHRNT_ZZI_H = 4990 |
| CEFBS_HasSVE2, // UQRSHRNT_ZZI_S = 4991 |
| CEFBS_HasNEON, // UQRSHRNb = 4992 |
| CEFBS_HasNEON, // UQRSHRNh = 4993 |
| CEFBS_HasNEON, // UQRSHRNs = 4994 |
| CEFBS_HasNEON, // UQRSHRNv16i8_shift = 4995 |
| CEFBS_HasNEON, // UQRSHRNv2i32_shift = 4996 |
| CEFBS_HasNEON, // UQRSHRNv4i16_shift = 4997 |
| CEFBS_HasNEON, // UQRSHRNv4i32_shift = 4998 |
| CEFBS_HasNEON, // UQRSHRNv8i16_shift = 4999 |
| CEFBS_HasNEON, // UQRSHRNv8i8_shift = 5000 |
| CEFBS_HasSVE2, // UQSHLR_ZPmZ_B = 5001 |
| CEFBS_HasSVE2, // UQSHLR_ZPmZ_D = 5002 |
| CEFBS_HasSVE2, // UQSHLR_ZPmZ_H = 5003 |
| CEFBS_HasSVE2, // UQSHLR_ZPmZ_S = 5004 |
| CEFBS_HasSVE2, // UQSHL_ZPmI_B = 5005 |
| CEFBS_HasSVE2, // UQSHL_ZPmI_D = 5006 |
| CEFBS_HasSVE2, // UQSHL_ZPmI_H = 5007 |
| CEFBS_HasSVE2, // UQSHL_ZPmI_S = 5008 |
| CEFBS_HasSVE2, // UQSHL_ZPmZ_B = 5009 |
| CEFBS_HasSVE2, // UQSHL_ZPmZ_D = 5010 |
| CEFBS_HasSVE2, // UQSHL_ZPmZ_H = 5011 |
| CEFBS_HasSVE2, // UQSHL_ZPmZ_S = 5012 |
| CEFBS_HasNEON, // UQSHLb = 5013 |
| CEFBS_HasNEON, // UQSHLd = 5014 |
| CEFBS_HasNEON, // UQSHLh = 5015 |
| CEFBS_HasNEON, // UQSHLs = 5016 |
| CEFBS_HasNEON, // UQSHLv16i8 = 5017 |
| CEFBS_HasNEON, // UQSHLv16i8_shift = 5018 |
| CEFBS_HasNEON, // UQSHLv1i16 = 5019 |
| CEFBS_HasNEON, // UQSHLv1i32 = 5020 |
| CEFBS_HasNEON, // UQSHLv1i64 = 5021 |
| CEFBS_HasNEON, // UQSHLv1i8 = 5022 |
| CEFBS_HasNEON, // UQSHLv2i32 = 5023 |
| CEFBS_HasNEON, // UQSHLv2i32_shift = 5024 |
| CEFBS_HasNEON, // UQSHLv2i64 = 5025 |
| CEFBS_HasNEON, // UQSHLv2i64_shift = 5026 |
| CEFBS_HasNEON, // UQSHLv4i16 = 5027 |
| CEFBS_HasNEON, // UQSHLv4i16_shift = 5028 |
| CEFBS_HasNEON, // UQSHLv4i32 = 5029 |
| CEFBS_HasNEON, // UQSHLv4i32_shift = 5030 |
| CEFBS_HasNEON, // UQSHLv8i16 = 5031 |
| CEFBS_HasNEON, // UQSHLv8i16_shift = 5032 |
| CEFBS_HasNEON, // UQSHLv8i8 = 5033 |
| CEFBS_HasNEON, // UQSHLv8i8_shift = 5034 |
| CEFBS_HasSVE2, // UQSHRNB_ZZI_B = 5035 |
| CEFBS_HasSVE2, // UQSHRNB_ZZI_H = 5036 |
| CEFBS_HasSVE2, // UQSHRNB_ZZI_S = 5037 |
| CEFBS_HasSVE2, // UQSHRNT_ZZI_B = 5038 |
| CEFBS_HasSVE2, // UQSHRNT_ZZI_H = 5039 |
| CEFBS_HasSVE2, // UQSHRNT_ZZI_S = 5040 |
| CEFBS_HasNEON, // UQSHRNb = 5041 |
| CEFBS_HasNEON, // UQSHRNh = 5042 |
| CEFBS_HasNEON, // UQSHRNs = 5043 |
| CEFBS_HasNEON, // UQSHRNv16i8_shift = 5044 |
| CEFBS_HasNEON, // UQSHRNv2i32_shift = 5045 |
| CEFBS_HasNEON, // UQSHRNv4i16_shift = 5046 |
| CEFBS_HasNEON, // UQSHRNv4i32_shift = 5047 |
| CEFBS_HasNEON, // UQSHRNv8i16_shift = 5048 |
| CEFBS_HasNEON, // UQSHRNv8i8_shift = 5049 |
| CEFBS_HasSVE2, // UQSUBR_ZPmZ_B = 5050 |
| CEFBS_HasSVE2, // UQSUBR_ZPmZ_D = 5051 |
| CEFBS_HasSVE2, // UQSUBR_ZPmZ_H = 5052 |
| CEFBS_HasSVE2, // UQSUBR_ZPmZ_S = 5053 |
| CEFBS_HasSVE, // UQSUB_ZI_B = 5054 |
| CEFBS_HasSVE, // UQSUB_ZI_D = 5055 |
| CEFBS_HasSVE, // UQSUB_ZI_H = 5056 |
| CEFBS_HasSVE, // UQSUB_ZI_S = 5057 |
| CEFBS_HasSVE2, // UQSUB_ZPmZ_B = 5058 |
| CEFBS_HasSVE2, // UQSUB_ZPmZ_D = 5059 |
| CEFBS_HasSVE2, // UQSUB_ZPmZ_H = 5060 |
| CEFBS_HasSVE2, // UQSUB_ZPmZ_S = 5061 |
| CEFBS_HasSVE, // UQSUB_ZZZ_B = 5062 |
| CEFBS_HasSVE, // UQSUB_ZZZ_D = 5063 |
| CEFBS_HasSVE, // UQSUB_ZZZ_H = 5064 |
| CEFBS_HasSVE, // UQSUB_ZZZ_S = 5065 |
| CEFBS_HasNEON, // UQSUBv16i8 = 5066 |
| CEFBS_HasNEON, // UQSUBv1i16 = 5067 |
| CEFBS_HasNEON, // UQSUBv1i32 = 5068 |
| CEFBS_HasNEON, // UQSUBv1i64 = 5069 |
| CEFBS_HasNEON, // UQSUBv1i8 = 5070 |
| CEFBS_HasNEON, // UQSUBv2i32 = 5071 |
| CEFBS_HasNEON, // UQSUBv2i64 = 5072 |
| CEFBS_HasNEON, // UQSUBv4i16 = 5073 |
| CEFBS_HasNEON, // UQSUBv4i32 = 5074 |
| CEFBS_HasNEON, // UQSUBv8i16 = 5075 |
| CEFBS_HasNEON, // UQSUBv8i8 = 5076 |
| CEFBS_HasSVE2, // UQXTNB_ZZ_B = 5077 |
| CEFBS_HasSVE2, // UQXTNB_ZZ_H = 5078 |
| CEFBS_HasSVE2, // UQXTNB_ZZ_S = 5079 |
| CEFBS_HasSVE2, // UQXTNT_ZZ_B = 5080 |
| CEFBS_HasSVE2, // UQXTNT_ZZ_H = 5081 |
| CEFBS_HasSVE2, // UQXTNT_ZZ_S = 5082 |
| CEFBS_HasNEON, // UQXTNv16i8 = 5083 |
| CEFBS_HasNEON, // UQXTNv1i16 = 5084 |
| CEFBS_HasNEON, // UQXTNv1i32 = 5085 |
| CEFBS_HasNEON, // UQXTNv1i8 = 5086 |
| CEFBS_HasNEON, // UQXTNv2i32 = 5087 |
| CEFBS_HasNEON, // UQXTNv4i16 = 5088 |
| CEFBS_HasNEON, // UQXTNv4i32 = 5089 |
| CEFBS_HasNEON, // UQXTNv8i16 = 5090 |
| CEFBS_HasNEON, // UQXTNv8i8 = 5091 |
| CEFBS_HasSVE2, // URECPE_ZPmZ_S = 5092 |
| CEFBS_HasNEON, // URECPEv2i32 = 5093 |
| CEFBS_HasNEON, // URECPEv4i32 = 5094 |
| CEFBS_HasSVE2, // URHADD_ZPmZ_B = 5095 |
| CEFBS_HasSVE2, // URHADD_ZPmZ_D = 5096 |
| CEFBS_HasSVE2, // URHADD_ZPmZ_H = 5097 |
| CEFBS_HasSVE2, // URHADD_ZPmZ_S = 5098 |
| CEFBS_HasNEON, // URHADDv16i8 = 5099 |
| CEFBS_HasNEON, // URHADDv2i32 = 5100 |
| CEFBS_HasNEON, // URHADDv4i16 = 5101 |
| CEFBS_HasNEON, // URHADDv4i32 = 5102 |
| CEFBS_HasNEON, // URHADDv8i16 = 5103 |
| CEFBS_HasNEON, // URHADDv8i8 = 5104 |
| CEFBS_HasSVE2, // URSHLR_ZPmZ_B = 5105 |
| CEFBS_HasSVE2, // URSHLR_ZPmZ_D = 5106 |
| CEFBS_HasSVE2, // URSHLR_ZPmZ_H = 5107 |
| CEFBS_HasSVE2, // URSHLR_ZPmZ_S = 5108 |
| CEFBS_HasSVE2, // URSHL_ZPmZ_B = 5109 |
| CEFBS_HasSVE2, // URSHL_ZPmZ_D = 5110 |
| CEFBS_HasSVE2, // URSHL_ZPmZ_H = 5111 |
| CEFBS_HasSVE2, // URSHL_ZPmZ_S = 5112 |
| CEFBS_HasNEON, // URSHLv16i8 = 5113 |
| CEFBS_HasNEON, // URSHLv1i64 = 5114 |
| CEFBS_HasNEON, // URSHLv2i32 = 5115 |
| CEFBS_HasNEON, // URSHLv2i64 = 5116 |
| CEFBS_HasNEON, // URSHLv4i16 = 5117 |
| CEFBS_HasNEON, // URSHLv4i32 = 5118 |
| CEFBS_HasNEON, // URSHLv8i16 = 5119 |
| CEFBS_HasNEON, // URSHLv8i8 = 5120 |
| CEFBS_HasSVE2, // URSHR_ZPmI_B = 5121 |
| CEFBS_HasSVE2, // URSHR_ZPmI_D = 5122 |
| CEFBS_HasSVE2, // URSHR_ZPmI_H = 5123 |
| CEFBS_HasSVE2, // URSHR_ZPmI_S = 5124 |
| CEFBS_HasNEON, // URSHRd = 5125 |
| CEFBS_HasNEON, // URSHRv16i8_shift = 5126 |
| CEFBS_HasNEON, // URSHRv2i32_shift = 5127 |
| CEFBS_HasNEON, // URSHRv2i64_shift = 5128 |
| CEFBS_HasNEON, // URSHRv4i16_shift = 5129 |
| CEFBS_HasNEON, // URSHRv4i32_shift = 5130 |
| CEFBS_HasNEON, // URSHRv8i16_shift = 5131 |
| CEFBS_HasNEON, // URSHRv8i8_shift = 5132 |
| CEFBS_HasSVE2, // URSQRTE_ZPmZ_S = 5133 |
| CEFBS_HasNEON, // URSQRTEv2i32 = 5134 |
| CEFBS_HasNEON, // URSQRTEv4i32 = 5135 |
| CEFBS_HasSVE2, // URSRA_ZZI_B = 5136 |
| CEFBS_HasSVE2, // URSRA_ZZI_D = 5137 |
| CEFBS_HasSVE2, // URSRA_ZZI_H = 5138 |
| CEFBS_HasSVE2, // URSRA_ZZI_S = 5139 |
| CEFBS_HasNEON, // URSRAd = 5140 |
| CEFBS_HasNEON, // URSRAv16i8_shift = 5141 |
| CEFBS_HasNEON, // URSRAv2i32_shift = 5142 |
| CEFBS_HasNEON, // URSRAv2i64_shift = 5143 |
| CEFBS_HasNEON, // URSRAv4i16_shift = 5144 |
| CEFBS_HasNEON, // URSRAv4i32_shift = 5145 |
| CEFBS_HasNEON, // URSRAv8i16_shift = 5146 |
| CEFBS_HasNEON, // URSRAv8i8_shift = 5147 |
| CEFBS_HasSVE2, // USHLLB_ZZI_D = 5148 |
| CEFBS_HasSVE2, // USHLLB_ZZI_H = 5149 |
| CEFBS_HasSVE2, // USHLLB_ZZI_S = 5150 |
| CEFBS_HasSVE2, // USHLLT_ZZI_D = 5151 |
| CEFBS_HasSVE2, // USHLLT_ZZI_H = 5152 |
| CEFBS_HasSVE2, // USHLLT_ZZI_S = 5153 |
| CEFBS_HasNEON, // USHLLv16i8_shift = 5154 |
| CEFBS_HasNEON, // USHLLv2i32_shift = 5155 |
| CEFBS_HasNEON, // USHLLv4i16_shift = 5156 |
| CEFBS_HasNEON, // USHLLv4i32_shift = 5157 |
| CEFBS_HasNEON, // USHLLv8i16_shift = 5158 |
| CEFBS_HasNEON, // USHLLv8i8_shift = 5159 |
| CEFBS_HasNEON, // USHLv16i8 = 5160 |
| CEFBS_HasNEON, // USHLv1i64 = 5161 |
| CEFBS_HasNEON, // USHLv2i32 = 5162 |
| CEFBS_HasNEON, // USHLv2i64 = 5163 |
| CEFBS_HasNEON, // USHLv4i16 = 5164 |
| CEFBS_HasNEON, // USHLv4i32 = 5165 |
| CEFBS_HasNEON, // USHLv8i16 = 5166 |
| CEFBS_HasNEON, // USHLv8i8 = 5167 |
| CEFBS_HasNEON, // USHRd = 5168 |
| CEFBS_HasNEON, // USHRv16i8_shift = 5169 |
| CEFBS_HasNEON, // USHRv2i32_shift = 5170 |
| CEFBS_HasNEON, // USHRv2i64_shift = 5171 |
| CEFBS_HasNEON, // USHRv4i16_shift = 5172 |
| CEFBS_HasNEON, // USHRv4i32_shift = 5173 |
| CEFBS_HasNEON, // USHRv8i16_shift = 5174 |
| CEFBS_HasNEON, // USHRv8i8_shift = 5175 |
| CEFBS_HasSVE2, // USQADD_ZPmZ_B = 5176 |
| CEFBS_HasSVE2, // USQADD_ZPmZ_D = 5177 |
| CEFBS_HasSVE2, // USQADD_ZPmZ_H = 5178 |
| CEFBS_HasSVE2, // USQADD_ZPmZ_S = 5179 |
| CEFBS_HasNEON, // USQADDv16i8 = 5180 |
| CEFBS_HasNEON, // USQADDv1i16 = 5181 |
| CEFBS_HasNEON, // USQADDv1i32 = 5182 |
| CEFBS_HasNEON, // USQADDv1i64 = 5183 |
| CEFBS_HasNEON, // USQADDv1i8 = 5184 |
| CEFBS_HasNEON, // USQADDv2i32 = 5185 |
| CEFBS_HasNEON, // USQADDv2i64 = 5186 |
| CEFBS_HasNEON, // USQADDv4i16 = 5187 |
| CEFBS_HasNEON, // USQADDv4i32 = 5188 |
| CEFBS_HasNEON, // USQADDv8i16 = 5189 |
| CEFBS_HasNEON, // USQADDv8i8 = 5190 |
| CEFBS_HasSVE2, // USRA_ZZI_B = 5191 |
| CEFBS_HasSVE2, // USRA_ZZI_D = 5192 |
| CEFBS_HasSVE2, // USRA_ZZI_H = 5193 |
| CEFBS_HasSVE2, // USRA_ZZI_S = 5194 |
| CEFBS_HasNEON, // USRAd = 5195 |
| CEFBS_HasNEON, // USRAv16i8_shift = 5196 |
| CEFBS_HasNEON, // USRAv2i32_shift = 5197 |
| CEFBS_HasNEON, // USRAv2i64_shift = 5198 |
| CEFBS_HasNEON, // USRAv4i16_shift = 5199 |
| CEFBS_HasNEON, // USRAv4i32_shift = 5200 |
| CEFBS_HasNEON, // USRAv8i16_shift = 5201 |
| CEFBS_HasNEON, // USRAv8i8_shift = 5202 |
| CEFBS_HasSVE2, // USUBLB_ZZZ_D = 5203 |
| CEFBS_HasSVE2, // USUBLB_ZZZ_H = 5204 |
| CEFBS_HasSVE2, // USUBLB_ZZZ_S = 5205 |
| CEFBS_HasSVE2, // USUBLT_ZZZ_D = 5206 |
| CEFBS_HasSVE2, // USUBLT_ZZZ_H = 5207 |
| CEFBS_HasSVE2, // USUBLT_ZZZ_S = 5208 |
| CEFBS_HasNEON, // USUBLv16i8_v8i16 = 5209 |
| CEFBS_HasNEON, // USUBLv2i32_v2i64 = 5210 |
| CEFBS_HasNEON, // USUBLv4i16_v4i32 = 5211 |
| CEFBS_HasNEON, // USUBLv4i32_v2i64 = 5212 |
| CEFBS_HasNEON, // USUBLv8i16_v4i32 = 5213 |
| CEFBS_HasNEON, // USUBLv8i8_v8i16 = 5214 |
| CEFBS_HasSVE2, // USUBWB_ZZZ_D = 5215 |
| CEFBS_HasSVE2, // USUBWB_ZZZ_H = 5216 |
| CEFBS_HasSVE2, // USUBWB_ZZZ_S = 5217 |
| CEFBS_HasSVE2, // USUBWT_ZZZ_D = 5218 |
| CEFBS_HasSVE2, // USUBWT_ZZZ_H = 5219 |
| CEFBS_HasSVE2, // USUBWT_ZZZ_S = 5220 |
| CEFBS_HasNEON, // USUBWv16i8_v8i16 = 5221 |
| CEFBS_HasNEON, // USUBWv2i32_v2i64 = 5222 |
| CEFBS_HasNEON, // USUBWv4i16_v4i32 = 5223 |
| CEFBS_HasNEON, // USUBWv4i32_v2i64 = 5224 |
| CEFBS_HasNEON, // USUBWv8i16_v4i32 = 5225 |
| CEFBS_HasNEON, // USUBWv8i8_v8i16 = 5226 |
| CEFBS_HasSVE, // UUNPKHI_ZZ_D = 5227 |
| CEFBS_HasSVE, // UUNPKHI_ZZ_H = 5228 |
| CEFBS_HasSVE, // UUNPKHI_ZZ_S = 5229 |
| CEFBS_HasSVE, // UUNPKLO_ZZ_D = 5230 |
| CEFBS_HasSVE, // UUNPKLO_ZZ_H = 5231 |
| CEFBS_HasSVE, // UUNPKLO_ZZ_S = 5232 |
| CEFBS_HasSVE, // UXTB_ZPmZ_D = 5233 |
| CEFBS_HasSVE, // UXTB_ZPmZ_H = 5234 |
| CEFBS_HasSVE, // UXTB_ZPmZ_S = 5235 |
| CEFBS_HasSVE, // UXTH_ZPmZ_D = 5236 |
| CEFBS_HasSVE, // UXTH_ZPmZ_S = 5237 |
| CEFBS_HasSVE, // UXTW_ZPmZ_D = 5238 |
| CEFBS_HasSVE, // UZP1_PPP_B = 5239 |
| CEFBS_HasSVE, // UZP1_PPP_D = 5240 |
| CEFBS_HasSVE, // UZP1_PPP_H = 5241 |
| CEFBS_HasSVE, // UZP1_PPP_S = 5242 |
| CEFBS_HasSVE, // UZP1_ZZZ_B = 5243 |
| CEFBS_HasSVE, // UZP1_ZZZ_D = 5244 |
| CEFBS_HasSVE, // UZP1_ZZZ_H = 5245 |
| CEFBS_HasSVE, // UZP1_ZZZ_S = 5246 |
| CEFBS_HasNEON, // UZP1v16i8 = 5247 |
| CEFBS_HasNEON, // UZP1v2i32 = 5248 |
| CEFBS_HasNEON, // UZP1v2i64 = 5249 |
| CEFBS_HasNEON, // UZP1v4i16 = 5250 |
| CEFBS_HasNEON, // UZP1v4i32 = 5251 |
| CEFBS_HasNEON, // UZP1v8i16 = 5252 |
| CEFBS_HasNEON, // UZP1v8i8 = 5253 |
| CEFBS_HasSVE, // UZP2_PPP_B = 5254 |
| CEFBS_HasSVE, // UZP2_PPP_D = 5255 |
| CEFBS_HasSVE, // UZP2_PPP_H = 5256 |
| CEFBS_HasSVE, // UZP2_PPP_S = 5257 |
| CEFBS_HasSVE, // UZP2_ZZZ_B = 5258 |
| CEFBS_HasSVE, // UZP2_ZZZ_D = 5259 |
| CEFBS_HasSVE, // UZP2_ZZZ_H = 5260 |
| CEFBS_HasSVE, // UZP2_ZZZ_S = 5261 |
| CEFBS_HasNEON, // UZP2v16i8 = 5262 |
| CEFBS_HasNEON, // UZP2v2i32 = 5263 |
| CEFBS_HasNEON, // UZP2v2i64 = 5264 |
| CEFBS_HasNEON, // UZP2v4i16 = 5265 |
| CEFBS_HasNEON, // UZP2v4i32 = 5266 |
| CEFBS_HasNEON, // UZP2v8i16 = 5267 |
| CEFBS_HasNEON, // UZP2v8i8 = 5268 |
| CEFBS_HasSVE2, // WHILEGE_PWW_B = 5269 |
| CEFBS_HasSVE2, // WHILEGE_PWW_D = 5270 |
| CEFBS_HasSVE2, // WHILEGE_PWW_H = 5271 |
| CEFBS_HasSVE2, // WHILEGE_PWW_S = 5272 |
| CEFBS_HasSVE2, // WHILEGE_PXX_B = 5273 |
| CEFBS_HasSVE2, // WHILEGE_PXX_D = 5274 |
| CEFBS_HasSVE2, // WHILEGE_PXX_H = 5275 |
| CEFBS_HasSVE2, // WHILEGE_PXX_S = 5276 |
| CEFBS_HasSVE2, // WHILEGT_PWW_B = 5277 |
| CEFBS_HasSVE2, // WHILEGT_PWW_D = 5278 |
| CEFBS_HasSVE2, // WHILEGT_PWW_H = 5279 |
| CEFBS_HasSVE2, // WHILEGT_PWW_S = 5280 |
| CEFBS_HasSVE2, // WHILEGT_PXX_B = 5281 |
| CEFBS_HasSVE2, // WHILEGT_PXX_D = 5282 |
| CEFBS_HasSVE2, // WHILEGT_PXX_H = 5283 |
| CEFBS_HasSVE2, // WHILEGT_PXX_S = 5284 |
| CEFBS_HasSVE2, // WHILEHI_PWW_B = 5285 |
| CEFBS_HasSVE2, // WHILEHI_PWW_D = 5286 |
| CEFBS_HasSVE2, // WHILEHI_PWW_H = 5287 |
| CEFBS_HasSVE2, // WHILEHI_PWW_S = 5288 |
| CEFBS_HasSVE2, // WHILEHI_PXX_B = 5289 |
| CEFBS_HasSVE2, // WHILEHI_PXX_D = 5290 |
| CEFBS_HasSVE2, // WHILEHI_PXX_H = 5291 |
| CEFBS_HasSVE2, // WHILEHI_PXX_S = 5292 |
| CEFBS_HasSVE2, // WHILEHS_PWW_B = 5293 |
| CEFBS_HasSVE2, // WHILEHS_PWW_D = 5294 |
| CEFBS_HasSVE2, // WHILEHS_PWW_H = 5295 |
| CEFBS_HasSVE2, // WHILEHS_PWW_S = 5296 |
| CEFBS_HasSVE2, // WHILEHS_PXX_B = 5297 |
| CEFBS_HasSVE2, // WHILEHS_PXX_D = 5298 |
| CEFBS_HasSVE2, // WHILEHS_PXX_H = 5299 |
| CEFBS_HasSVE2, // WHILEHS_PXX_S = 5300 |
| CEFBS_HasSVE, // WHILELE_PWW_B = 5301 |
| CEFBS_HasSVE, // WHILELE_PWW_D = 5302 |
| CEFBS_HasSVE, // WHILELE_PWW_H = 5303 |
| CEFBS_HasSVE, // WHILELE_PWW_S = 5304 |
| CEFBS_HasSVE, // WHILELE_PXX_B = 5305 |
| CEFBS_HasSVE, // WHILELE_PXX_D = 5306 |
| CEFBS_HasSVE, // WHILELE_PXX_H = 5307 |
| CEFBS_HasSVE, // WHILELE_PXX_S = 5308 |
| CEFBS_HasSVE, // WHILELO_PWW_B = 5309 |
| CEFBS_HasSVE, // WHILELO_PWW_D = 5310 |
| CEFBS_HasSVE, // WHILELO_PWW_H = 5311 |
| CEFBS_HasSVE, // WHILELO_PWW_S = 5312 |
| CEFBS_HasSVE, // WHILELO_PXX_B = 5313 |
| CEFBS_HasSVE, // WHILELO_PXX_D = 5314 |
| CEFBS_HasSVE, // WHILELO_PXX_H = 5315 |
| CEFBS_HasSVE, // WHILELO_PXX_S = 5316 |
| CEFBS_HasSVE, // WHILELS_PWW_B = 5317 |
| CEFBS_HasSVE, // WHILELS_PWW_D = 5318 |
| CEFBS_HasSVE, // WHILELS_PWW_H = 5319 |
| CEFBS_HasSVE, // WHILELS_PWW_S = 5320 |
| CEFBS_HasSVE, // WHILELS_PXX_B = 5321 |
| CEFBS_HasSVE, // WHILELS_PXX_D = 5322 |
| CEFBS_HasSVE, // WHILELS_PXX_H = 5323 |
| CEFBS_HasSVE, // WHILELS_PXX_S = 5324 |
| CEFBS_HasSVE, // WHILELT_PWW_B = 5325 |
| CEFBS_HasSVE, // WHILELT_PWW_D = 5326 |
| CEFBS_HasSVE, // WHILELT_PWW_H = 5327 |
| CEFBS_HasSVE, // WHILELT_PWW_S = 5328 |
| CEFBS_HasSVE, // WHILELT_PXX_B = 5329 |
| CEFBS_HasSVE, // WHILELT_PXX_D = 5330 |
| CEFBS_HasSVE, // WHILELT_PXX_H = 5331 |
| CEFBS_HasSVE, // WHILELT_PXX_S = 5332 |
| CEFBS_HasSVE2, // WHILERW_PXX_B = 5333 |
| CEFBS_HasSVE2, // WHILERW_PXX_D = 5334 |
| CEFBS_HasSVE2, // WHILERW_PXX_H = 5335 |
| CEFBS_HasSVE2, // WHILERW_PXX_S = 5336 |
| CEFBS_HasSVE2, // WHILEWR_PXX_B = 5337 |
| CEFBS_HasSVE2, // WHILEWR_PXX_D = 5338 |
| CEFBS_HasSVE2, // WHILEWR_PXX_H = 5339 |
| CEFBS_HasSVE2, // WHILEWR_PXX_S = 5340 |
| CEFBS_HasSVE, // WRFFR = 5341 |
| CEFBS_HasAltNZCV, // XAFLAG = 5342 |
| CEFBS_HasSHA3, // XAR = 5343 |
| CEFBS_HasSVE2, // XAR_ZZZI_B = 5344 |
| CEFBS_HasSVE2, // XAR_ZZZI_D = 5345 |
| CEFBS_HasSVE2, // XAR_ZZZI_H = 5346 |
| CEFBS_HasSVE2, // XAR_ZZZI_S = 5347 |
| CEFBS_HasPA, // XPACD = 5348 |
| CEFBS_HasPA, // XPACI = 5349 |
| CEFBS_None, // XPACLRI = 5350 |
| CEFBS_HasNEON, // XTNv16i8 = 5351 |
| CEFBS_HasNEON, // XTNv2i32 = 5352 |
| CEFBS_HasNEON, // XTNv4i16 = 5353 |
| CEFBS_HasNEON, // XTNv4i32 = 5354 |
| CEFBS_HasNEON, // XTNv8i16 = 5355 |
| CEFBS_HasNEON, // XTNv8i8 = 5356 |
| CEFBS_HasSVE, // ZIP1_PPP_B = 5357 |
| CEFBS_HasSVE, // ZIP1_PPP_D = 5358 |
| CEFBS_HasSVE, // ZIP1_PPP_H = 5359 |
| CEFBS_HasSVE, // ZIP1_PPP_S = 5360 |
| CEFBS_HasSVE, // ZIP1_ZZZ_B = 5361 |
| CEFBS_HasSVE, // ZIP1_ZZZ_D = 5362 |
| CEFBS_HasSVE, // ZIP1_ZZZ_H = 5363 |
| CEFBS_HasSVE, // ZIP1_ZZZ_S = 5364 |
| CEFBS_HasNEON, // ZIP1v16i8 = 5365 |
| CEFBS_HasNEON, // ZIP1v2i32 = 5366 |
| CEFBS_HasNEON, // ZIP1v2i64 = 5367 |
| CEFBS_HasNEON, // ZIP1v4i16 = 5368 |
| CEFBS_HasNEON, // ZIP1v4i32 = 5369 |
| CEFBS_HasNEON, // ZIP1v8i16 = 5370 |
| CEFBS_HasNEON, // ZIP1v8i8 = 5371 |
| CEFBS_HasSVE, // ZIP2_PPP_B = 5372 |
| CEFBS_HasSVE, // ZIP2_PPP_D = 5373 |
| CEFBS_HasSVE, // ZIP2_PPP_H = 5374 |
| CEFBS_HasSVE, // ZIP2_PPP_S = 5375 |
| CEFBS_HasSVE, // ZIP2_ZZZ_B = 5376 |
| CEFBS_HasSVE, // ZIP2_ZZZ_D = 5377 |
| CEFBS_HasSVE, // ZIP2_ZZZ_H = 5378 |
| CEFBS_HasSVE, // ZIP2_ZZZ_S = 5379 |
| CEFBS_HasNEON, // ZIP2v16i8 = 5380 |
| CEFBS_HasNEON, // ZIP2v2i32 = 5381 |
| CEFBS_HasNEON, // ZIP2v2i64 = 5382 |
| CEFBS_HasNEON, // ZIP2v4i16 = 5383 |
| CEFBS_HasNEON, // ZIP2v4i32 = 5384 |
| CEFBS_HasNEON, // ZIP2v8i16 = 5385 |
| CEFBS_HasNEON, // ZIP2v8i8 = 5386 |
| }; |
| |
| assert(Inst.getOpcode() < 5387); |
| const FeatureBitset &RequiredFeatures = FeatureBitsets[RequiredFeaturesRefs[Inst.getOpcode()]]; |
| FeatureBitset MissingFeatures = |
| (AvailableFeatures & RequiredFeatures) ^ |
| RequiredFeatures; |
| if (MissingFeatures.any()) { |
| std::ostringstream Msg; |
| Msg << "Attempting to emit " << MCII.getName(Inst.getOpcode()).str() |
| << " instruction but the "; |
| for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i) |
| if (MissingFeatures.test(i)) |
| Msg << SubtargetFeatureNames[i] << " "; |
| Msg << "predicate(s) are not met"; |
| report_fatal_error(Msg.str()); |
| } |
| #else |
| // Silence unused variable warning on targets that don't use MCII for other purposes (e.g. BPF). |
| (void)MCII; |
| #endif // NDEBUG |
| } |
| #endif |
